Schematic Diagrams

SYSTEM BLOCK DIAGRAM

M520N SCHEMATIC

BUSMASTER DEVICE PCI INT IDSEL

ICS9LPR310BGLF Thermal sensor Intel
Clocking PREQ2# GNT#2 TI 7412 SERIRQ INT#A/B/C/D AD23
Pentium 4
Yonah / Merom
CPU FAN
479 uFC-BGA
B.Schematic Diagrams

533/667MHz
LVDS

Sheet 1 of 29 DDR2 DRAM CHANNEL A SODIMM0

SYSTEM BLOCK TV OUT Intel
Calistoga
DIAGRAM 945GM DDR2 DRAM CHANNEL B SODIMM1
USB Port0 CRT 1466ball m- FCBGA

USB Port1
DMI x2 or x4 100MHz
USB Port2
Realtek
PCI-E I/F RTL8111B
Bluetooth USB 2.0
Intel 33MHz, 3.3V PCI 2.2 I/F
PCI-E I/F
CCD ICH7-M
AZALIA I/F 652 BGA TI 7412 CARDBUS
D-SUB Ultra Media

Mini Card IEEE 1394

GOLAN
WIRELESS MDC AUDIOCODEC
HD-MODEM ALC883 Card reader

33MHz, 3.3V LPC I/F

SATA INTERFACE SATA I/F
HDD IN. K/B
IDE I/F KBC H8
IDE INTERFACE H8S-2111
CD-ROM/DVD-ROM EX. K/B
FWH I/F
Flash ROM TOUCH PAD

hexainf@hotmail.com
B - 2 SYSTEM BLOCK DIAGRAM
 Schematic Diagrams

CPU 1/2

JSKT1A J SKT1B
[5] H _A#[31:3] H _A#3 [5] H_D #[ 63: 0] H _D #0 H _D #32 H _D #[63:0] [ 5]
J4 H1 E22 AA23
H _A#4 A[ 3]# ADS# H_AD S# [5] H _D #1 D [0]# D [32]# H _D #33
L4 E2 F24 AB24
H _A#5 M3 A[ 4]# BNR # G5 H_BN R# [5] H _D #2 E26 D [1]# D [33]# V24 H _D #34
A[ 5]# BPR I# H_BPRI# [5] D [2]# D [34]#
H _A#6 K5 H _D #3 H22 V26 H _D #35
A[ 6]# D [3]# D [35]#

DATA GRP 0
H _A#7 M1 H5 H _D #4 F23 W 25 H _D #36

DATA GRP 2
A[ 7]# D EF ER # H_DEFER# [5] D [4]# D [36]#

ADDR GROUP 0
H _A#8 N2 F 21 H _D #5 G25 U 23 H _D #37
H _A#9 A[ 8]# DR DY # H_DR DY # [5] H _D #6 D [5]# D [37]# H _D #38
J1 E1 E25 U 25
H _A#10 A[ 9]# DBSY # H_DBSY # [5] H _D #7 D [6]# D [38]# H _D #39
N3 E23 U 22

CONTROL
H _A#11 A[ 10] # H _D #8 D [7]# D [39]# H _D #40
P5 F1 H_BR 0# [5] K24 AB25
H _A#12 A[ 11] # BR0# H _D #9 D [8]# D [40]# H _D #41
P2 G24 W 22
H _A#13 L1 A[ 12] # D 20 H_IERR # H _D #10 J24 D [9]# D [41]# Y 23 H _D #42
H _A#14 P4 A[ 13] # IERR # B3 H _D #11 J23 D [10 D [42]# AA26 H _D #43
H _A#15 A[ 14] # I NIT# H_INI T# [11] H _D #12 D [11]# D [43]# H _D #44
P1 H26 Y 26
A[ 15] # D [12]# D [44]#

[5]
[5]
H_AD STB#0
H_REQ#[4:0]
H _A#16 R1
L2
H _R EQ#0 K3
A[ 16] #
AD STB[0]#
LOCK#

R ESET#
H4

B1
F3
H_LOCK# [5]

H_CPUR ST# [5]

H _D #13
H _D #14
H _D #15
F26
K22
H25
H23
D [13]#
D [14]#
D [15]#
D [45]#
D [46]#
D [47]#
Y 22
AC26
AA24
W 24
H _D #45
H _D #46
H _D #47
Sheet 2 of 29
REQ[ 0]# RS[0]# H_RS#0 [5] [5] H _D STBN#0 D STBN [0]# DSTBN[2]# H _D STBN#2 [5]
H _R EQ#1 H 2
H _R EQ#2 K2
H _R EQ#3 J 3
H _R EQ#4 L5
REQ[ 1]#
REQ[ 2]#
REQ[ 3]#
RS[1]#
RS[2]#
TR DY #
F4
G3
G2
H_RS#1
H_RS#2
[5]
[5]
H_TR DY # [5]
[5]
[5]
H _D STBP#0
H_DIN V#0
G22
J26 D STBP[ 0]#
D INV[0]#
DSTBP[2]#
D IN V[2]#
Y 25
V23
H _D STBP#2 [5]
H _D INV#2 [5] CPU 1/2
REQ[ 4]# [5] H_D #[ 63: 0] H _D #16 H _D #48 H _D #[63:0] [ 5]
G6 N22 AC22
[5] H _A#[31:3] H _A#17 HIT# H_HIT# [5] H _D #17 D [16]# D [48]# H _D #49
Y2 E4 K25 AC23
H _A#18 A[ 17] # H ITM# H_HITM# [5] H _D #18 D [17]# D [49]# H _D #50
U5 P26 AB22
H _A#19 A[ 18] # H_BPM0# H _D #19 D [18]# D [50]# H _D #51
R3 AD4 R23 AA21
A[ 19] # BPM[0]# D [19]# D [51]#

DATA GRP 1
H _A#20 W6 AD3 H_BPM1# H _D #20 L25 AB21 H _D #52

DATA GRP 3
H _A#21 U4 A[ 20] # BPM[1]# AD1 H_BPM2# H _D #21 L22 D [20]# D [52]# AC25 H _D #53

B.Schematic Diagrams
XDP/ITP SIGNALS
H _A#22 Y5 A[ 21] # BPM[2]# AC4 H_BPM3# H _D #22 L23 D [21]# D [53]# AD20 H _D #54
H _A#23 U2 A[ 22] # BPM[3]# AC2 H_PR DY # H _D #23 M23 D [22]# D [54]# AE22 H _D #55
H _A#24 A[ 23] # PR DY # H_PR EQ# H _D #24 D [23]# D [55]# H _D #56
R4 AC1 P25 AF23
H _A#25 A[ 24] # PR EQ# H_TC K H _D #25 D [24]# D [56]# H _D #57
T5 AC5 P22 AD24
H _A#26 T3 A[ 25] # TC K AA6 H_TD I H _D #26 P23 D [25]# D [57]# AE21 H _D #58
H _A#27 W3 A[ 26] # TD I AB3 H_TD O H _D #27 T24 D [26]# D [58]# AD21 H _D #59
H _A#28 W5 A[ 27] # TD O AB5 H_TMS H _D #28 R24 D [27]# D [59]# AE25 H _D #60
H _A#29 A[ 28] # TMS H_TR ST# H _D #29 D [28]# D [60]# H _D #61
Y4 AB6 L26 AF25
H _A#30 W2 A[ 29] # TR ST# C 20 ITP_D BR ST# H _D #30 T25 D [29]# D [61]# AF22 H _D #62
H _A#31 Y1 A[ 30] # D BR # H _D #31 N24 D [30]# D [62]# AF26 H _D #63
V4 A[ 31] # D 21 H_PR OC H OT# M24 D [31]# D [63]# AD23
[5] H_AD STB#1 AD STB[1]# PR OC HOT H_TH ER MD A [5] H _D STBN#1 D STBN [1]# DSTBN[3]# H _D STBN#3 [5]
A24 N25 AE24
TH ER MD A [5] H _D STBP#1 D STBP[ 1]# DSTBP[3]# H _D STBP#3 [5]
A6 A25 H_TH ER MD C M26 AC20
THERM

[11] H_A20M# A20M# TH ER MD C [5] H_DIN V#1 D INV[1]# D IN V[3]# H _D INV#3 [5]
A5
[11] H _F ER R# FERR # PM_TH RMTR IP# [5,11] H COMP0
C4 C7 R243 1K_04(R) C26 R 26
[11] H _IGNN E# IGNN E# TH ER MTRIP# TEST1 C OMP[0] H COMP1
MISC U 26
PM_TH RMTR IP# [5,11] C OMP[1] H COMP2
D5 R244 51.1_1%_04 D25 U1
[11] H_STPC LK# STPC LK# TEST2 C OMP[2] H COMP3
C6 V1
[11] H _IN TR
H CLK

LI NT0 C OMP[3]
B4 A22 Layout Note: B22
[11] H_NMI LI NT1 BCLK[ 0] CPUC LK [4] [4] CPU_BSEL0 BSEL[0]
A3 A21 B23 E5
[11] H _SMI# SMI# BCLK[ 1] CPUC LK# [4] [4] CPU_BSEL1 BSEL[1] D PR STP# H _D PR STP# [11,21]
0.5" max, Zo= 55 Ohms C21 B5
AA1 [4] CPU_BSEL2 BSEL[2] DPSLP# D 24 H _D PSLP# [ 11]
RSVD [01]# DPWR # H _D PW R# [5]
AA4 T22 D6
RSVD [02]# R SVD [12]# PW RGOOD C PU PW RGD [11]
AB2 R254 1K_1% C PU _GTLREF AD26 D7
RSVD [03]# 1.05VS GTLR EF SLP# H _C PU SLP# [5, 11]
AA3 AE6
RESERVED

RSVD [04]# PSI# PSI# [21]

M4 D2
N5 RSVD [05]# R SVD [13]# F6 C 349 C 347 C348 R256
RSVD [06]# R SVD [14]# 1-1674770-2
T2 D3
RSVD [07]# R SVD [15]#
V3 C1 1U_X7R . 1U _X7R_04 .01U_04 2K_1%
RSVD [08]# R SVD [16]#
B2 AF1
C3 RSVD [09]# R SVD [17]# D 22
RSVD [10]# R SVD [18]# C 23
B25 R SVD [19]# C 24
RSVD [11]# R SVD [20]#
1-1674770-2
If PROCHOT# is routed between CPU, IMVP and
1. 05VS
MCH, pull-up resistor has to be 75 ohm ±
R 253 5% 56_04 H_IER R#
R 32 H_PR EQ#
54. 9_1%
R 18 68 H_PR OC HOT#

R 30 39 H_TMS Layout Note:

R 27 150_1%_04 H_TD I
5 /1 6 TH M_VD D Within 2.0" of the CPU
R 34 27 H_TC K
20 MILE

Q2 R 31 680 H_TR ST#

VD D3 S D R 10 0_1%_04
ND S352AP
VD D3 VD D3 3VS
G

R3 100K_04 R 242 150_1%_04 ITP_D BR ST#

R4 C5
D

Q1
Layout Note:
G 100K_04 1U_04 R 11 R6 R5
[ 19] TH ERM_R ST# COMP0, COMP2: 0.5" Max, Zo=27.4 Ohms
2N 7002W
S

COMP1, COMP3: 0.5" Max, Zo=55 Ohms

20K_04 4.7K_04 4.7K_04 Best estimate is 18 mils wide trace for outer
U1
1 8 SMC_THERM layers and 14 mils wide trace if on internal
VDD SCLK SMC _TH ER M [19]
H _TH ER MDA 10 MI LE 2 7 SMD_TH ER M layers.
H _TH ER MDC 10 MI LE D+ SD ATA SMD _TH ER M [19]
3 6 C A PM_THR M#
4 D- ALERT# 5 D2 SCS751 PM_THR M# [ 12] HC OMP0 R 255 27.4_1%_04
C 328 2200P THERM# GN D HC OMP1 R 257 54.9_1%_04
TH ER M_ALER T# [19] HC OMP2
AD T1032ARM R 24 27.4_1%_04
HC OMP3 R 28 54.9_1%_04
R8 0_04(R ) PM_TH RM#

Near to R7 10K_04 TH M_VD D

Layout Note:
ADM1032
Route H_THERMDA and
H_THERMDC on same layer.
10 mil trace on 10 mil 1.05VS [3,4,5, 6,8,11,13,22]
VD D3 [10,11,14,19,20,23,24,25]
spacing. 3VS [4,5,6, 9,10,11,12,13,14, 15, 16, 18, 20, 21, 24]

CPU 1/2 B - 3
 Schematic Diagrams

CPU-2/2

JSKT1D
A4 P6 VCORE
A8 VSS[001] VSS[082] P21
VCORE VCORE VSS[002] VSS[083]
A11 P24
VSS[003] VSS[084]
JSKT1C A14 R2
A7 AB20 A16 VSS[004] VSS[085] R5 C352 C339 C353 C356 C355 C342 C13 C10 C11 C12
A9 VCC[001] VCC[68] AB7 A19 VSS[005] VSS[086] R22
A10 VCC[002] VCC[69] AC7 A23 VSS[006] VSS[087] R25 10U/10V_08 10U/10V_08 10U/10V_08 10U/10V_08 10U/10V_08 10U/10V_08 10U/10V_08 10U/10V_08 10U/10V_08 10U/10V_08
A12 VCC[003] VCC[70] AC9 A26 VSS[007] VSS[088] T1
VCC[004] VCC[71] VSS[008] VSS[089]
A13 AC12 B6 T4
A15 VCC[005] VCC[72] AC13 B8 VSS[009] VSS[090] T23
VCC[006] VCC[73] VSS[010] VSS[091] VCORE
A17 AC15 B11 T26
A18 VCC[007] VCC[74] AC17 B13 VSS[011] VSS[092] U3
A20 VCC[008] VCC[75] AC18 B16 VSS[012] VSS[093] U6
B7 VCC[009] VCC[76] AD7 B19 VSS[013] VSS[094] U21
B9 VCC[010] VCC[77] AD9 B21 VSS[014] VSS[095] U24 C368 C367 C366 C365 C364 C363 C362 C361 C360 C354
VCC[011] VCC[78] VSS[015] VSS[096]
B10 AD10 B24 V2
VCC[012] VCC[79] VSS[016] VSS[097]
B12 AD12 C5 V5 22U_08 22U_08 22U_08 22U_08 22U_08 22U_08 22U_08 22U_08 22U_08 22U_08
B14 VCC[013] VCC[80] AD14 C8 VSS[017] VSS[098] V22
B15 VCC[014] VCC[81] AD15 C11 VSS[018] VSS[099] V25
B17 VCC[015] VCC[82] AD17 C14 VSS[019] VSS[100] W1
B18 VCC[016] VCC[83] AD18 C16 VSS[020] VSS[101] W4 VCORE
VCC[017] VCC[84] VSS[021] VSS[102]
B20 AE9 C19 W23
B.Schematic Diagrams

C9 VCC[018] VCC[85] AE10 C2 VSS[022] VSS[103] W26

VCC[019] VCC[86] VSS[023] VSS[104]
C10 AE12 C22 Y3
C12 VCC[020] VCC[87] AE13 C25 VSS[024] VSS[105] Y6 C16 C25 C17 C28 C19 C18
C13 VCC[021] VCC[88] AE15 D1 VSS[025] VSS[106] Y21
C15 VCC[022] VCC[89] AE17 D4 VSS[026] VSS[107] Y24 1U_X7R 1U_X7R 1U_X7R 1U_X7R 1U_X7R 1U_X7R
VCC[023] VCC[90] VSS[027] VSS[108]
C17 AE18 D8 AA2
VCC[024] VCC[91] VSS[028] VSS[109]
C18 AE20 D11 AA5
VCC[025] VCC[92] VSS[029] VSS[110]
D9 AF9 D13 AA8

Sheet 3 of 29 D10 VCC[026] VCC[93] AF10 D16 VSS[030] VSS[111] AA11 VCORE
D12 VCC[027] VCC[94] AF12 D19 VSS[031] VSS[112] AA14
D14 VCC[028] VCC[95] AF14 D23 VSS[032] VSS[113] AA16
D15 VCC[029] VCC[96] AF15 D26 VSS[033] VSS[114] AA19

CPU-2/2 D17
D18
E7
VCC[030]
VCC[031]
VCC[032]
VCC[97]
VCC[98]
VCC[99]
AF17
AF18
AF20
E3
E6
E8
VSS[034]
VSS[035]
VSS[036]
VSS[115]
VSS[116]
VSS[117]
AA22
AA25
AB1
C340

1U_X7R
C341

1U_X7R
C350

1U_X7R
C343

1U_X7R
C344

1U_X7R
C351

1U_X7R
E9 VCC[033] VCC[100] E11 VSS[037] VSS[118] AB4
E10 VCC[034]
VCC[035] VCCP[01]
V6 2.5A 1.05VS
E14 VSS[038]
VSS[039]
VSS[119]
VSS[120]
AB8
E12 G21 E16 AB11
VCC[036] VCCP[02] VSS[040] VSS[121] VCORE
E13 J6 E19 AB13
E15 VCC[037] VCCP[03] K6 E21 VSS[041] VSS[122] AB16
VCC[038] VCCP[04] VSS[042] VSS[123]
E17 M6 E24 AB19
E18 VCC[039] VCCP[05] J21 F5 VSS[043] VSS[124] AB23
E20 VCC[040] VCCP[06] K21 F8 VSS[044] VSS[125] AB26 C26 C33 C27 C24 C32 C31
F7 VCC[041] VCCP[07] M21 F11 VSS[045] VSS[126] AC3
F9 VCC[042] VCCP[08] N21 F13 VSS[046] VSS[127] AC6 .1U_X7R_04 .1U_X7R_04 .1U_X7R_04 .1U_X7R_04 .1U_X7R_04 .1U_X7R_04
VCC[043] VCCP[09] VSS[047] VSS[128]
F10 N6 F16 AC8
VCC[044] VCCP[10] 1.5VS VSS[048] VSS[129]
F12 R21 F19 AC11
VCC[045] VCCP[11] VSS[049] VSS[130]
F14 R6 Layout note: F2 AC14
F15 VCC[046] VCCP[12]
VCC[047] VCCP[13]
T21 130mA F22 VSS[050]
VSS[051]
VSS[131]
VSS[132]
AC16
F17 T6 Near pin B26 F25 AC19
F18 VCC[048] VCCP[14] V21 C329 C330 G4 VSS[052] VSS[133] AC21
VCC[049] VCCP[15] VSS[053] VSS[134]
F20 W21 G1 AC24
AA7 VCC[050] VCCP[16] 10U/10V_08 .01U_04 G23 VSS[054] VSS[135] AD2
VCC[051] VSS[055] VSS[136]
AA9 B26 G26 AD5
AA10 VCC[052] VCCA H3 VSS[056] VSS[137] AD8
AA12 VCC[053] H6 VSS[057] VSS[138] AD11
AA13 VCC[054] AD6 H_VID0 H21 VSS[058] VSS[139] AD13
AA15 VCC[055] VID[0] AF5 H_VID1 H24 VSS[059] VSS[140] AD16 1.05VS PLACE NEAR CPU
VCC[056] VID[1] H_VID2 VSS[060] VSS[141]
AA17 AE5 J2 AD19
VCC[057] VID[2] H_VID3 VSS[061] VSS[142]
AA18 AF4 J5 AD22
AA20 VCC[058] VID[3] AE3 H_VID4 J22 VSS[062] VSS[143] AD25
AB9 VCC[059] VID[4] AF2 H_VID5 J25 VSS[063] VSS[144] AE1 C335 C333 C334 C20 C21 C29
AC10 VCC[060] VID[5] AE2 H_VID6 H_VID[6:0] K1 VSS[064] VSS[145] AE4 +
VCC[061] VID[6] H_VID[6:0] [21] VSS[065] VSS[146]
AB10 K4 AE8 220U/4V_V .1U_X7R_04 .1U_X7R_04 .1U_X7R_04 .1U_X7R_04 .1U_X7R_04
VCC[062] VSS[066] VSS[147]
AB12 K23 AE11
AB14 VCC[063] K26 VSS[067] VSS[148] AE14
VCC[064] VCCSENSE VSS[068] VSS[149]
AB15 AF7 L3 AE16
VCC[065]VCCSENSE VCCSENSE [21] VSS[069] VSS[150] 1.05VS
AB17 L6 AE19
AB18 VCC[066] AE7 VSSSENSE L21 VSS[070] VSS[151] AE23
VCC[067] VSSSENSE VSSSENSE [21] VSS[071] VSS[152]
L24 AE26
1-1674770-2 M2 VSS[072] VSS[153] AF3
VSS[073] VSS[154]
R262 R261 M5 AF6 C345 C346 C336 C15 C23
VSS[074] VSS[155]
Layout note: M22 AF8
100_1% 100_1% M25 VSS[075] VSS[156] AF11 .1U_X7R_04 .1U_X7R_04 .1U_X7R_04 .1U_X7R_04 .1U_X7R_04
N1 VSS[076] VSS[157] AF13
Route VCCSENSE and VSS[077] VSS[158]
N4 AF16
VSSSENSE traces at 27.4Ohm N23
VSS[078] VSS[159]
AF19
with 50 mil spacing. VSS[079] VSS[160]
VCORE N26 AF21
P3 VSS[080] VSS[161] AF24
Place PU and PD within 1 VSS[081] VSS[162] +VCCP = 1.05V (0.997V~1.102V)
inch of CPU. 1-1674770-2

1.05VS [2,4,5,6,8,11,13,22]
VCORE [21]
1.5VS [6,11,13,16,24]

hexainf@hotmail.com
B - 4 CPU-2/2
 Schematic Diagrams

CLOCK GENERATOR

L19 HCB1608KF-121T25
3VS

C210 C152 C192 C193 C153 C208 C207 MCHCLK C172 10P_04(R)

10U/10V_08 1U_06 1U_06

.1U_X7R_04 .1U_X7R_04 MCHCLK# C171 10P_04(R)

28

42

56
50
7

1
U16
.1U_X7R_04 .1U_X7R_04

VDD_PCI1
VDDPCIEX

VDDPCIEX

VDD_PCI0

VDDCPU

VDDREF
49 CPUCLK1 3 2 RN28 MCHCLK CPUCLK C195 10P_04(R)
CPUCLK1 48 CPUCLK1# 4 1 4P2R_33_04 MCHCLK# MCHCLK [5]
CPUCLK1# MCHCLK# [5]
L18 HCB1608KF-121T25
3VS CPUCLK0 CPUCLK CPUCLK#
52 3 2 RN31 C194 10P_04(R)
CPUCLK0 CPUCLK0# CPUCLK# CPUCLK [2]
C209 C191 11 51 4 1 4P2R_33_04
VDD_48 CPUCLK0# CPUCLK# [2]
10U/10V_08 1U_06 45 ICH7PCIE_CLK C155 10P_04(R)
VDDA SRCCLK_8
44
PCIEX8 43 SRCCLK_#8
PCIEX8# ICH7PCIE_CLK# C154 10P_04(R)
CLK_BSEL0 R310 2.2K_04 41 SRCCLK_7 3 2 RN27 CLK_PCIE_MINI
PCIEX7 CLK_PCIE_MINI [16]
R322 33_04 40 SRCCLK_#7 4 1 4P2R_33_04 CLK_PCIE_MINI#
[15] CLK48_CARDBUS FS_A 12 PCIEX7# CLK_PCIE_MINI# [16] SATACLK
R323 33_04 C149 10P_04(R)
[12] CLK48_USB FSLA/USB_48MHz_2X SRCCLK_6 ICH7PCIE_CLK
39 3 2 RN23
PCIEX6 ICH7PCIE_CLK [11]

B.Schematic Diagrams
CLK14.3M_I/O R131 33_04 38 SRCCLK_#6 4 1 4P2R_33_04 ICH7PCIE_CLK#
[20] CLK14.3M_I/O CLK_BSEL1 PCIEX6# ICH7PCIE_CLK# [11]
R317 2.2K_04 FS_B 60 SATACLK# C141 10P_04(R)
CLK_BSEL2 R137 2.2K_04 REF0/FSLB 36 SRCCLK_5
R329 33_04 FS_C 61 PCIEX5 35 SRCCLK_#5
[12] CLK14.3M_ICH REF1/FSLC PCIEX5# CLK_PCIE_MINI C170 10P_04(R)
62 30 SRCCLK_4
[12] PM_STPCPU# CPU_STOP# PCIEX4
63 31 SRCCLK_#4
[12] PM_STPPCI# PCI/PCIEX_STOP# PCIEX4# CLK_PCIE_MINI# C156 10P_04(R)
[14] PCLK_FWH
PCLK_FWH

PCLK_SI/O
R319

R321
33_04 PCLK3

33_04 PCLK2_2X 4
5
PCICLK3 SATACLK
SATACLK#
26
27

24
SRCCLK_9
SRCCLK_#9

SRCCLK_3
4
3
1 RN24
2 4P2R_33_04
SATACLK
SATACLK#
SATACLK [11]
SATACLK# [11]
DREFSSCLK C188 10P_04(R)
Sheet 4 of 29
[20] PCLK_SI/O
CLOCK
PCICLK2_2X PCIEX3 25 SRCCLK_#3
PCIEX3# DREFSSCLK#
R300 10K_04(R) C169 10P_04(R)
KBC_PCLK R320 33_04 PCLK1_2X 3 33 3VS
[19] KBC_PCLK PCICLK1_2X PEREQ4# WLAN_CLKREQ# [16]

[15] PCLK_CARDBUS
PCLK_CARDBUS R330 33_04 PCLK0_2X64
PCICLK0_2X
PCIEX2
PCIEX2#
22
23
SRCCLK_2
SRCCLK_#2
4
3
1 RN25
2 4P2R_33_04
CLK_PCIE_GLAN
CLK_PCIE_GLAN# CLK_PCIE_GLAN [17]
CLK_PCIE_GLAN# [17]
DREFCLK C190 10P_04(R)
GENERATOR
32 R301 10K_04(R) DREFCLK# C189 10P_04(R)
PEREQ3# 3VS
R129 10K_04(R) 9
3VS *SELDOT/PCICLK_F1 SRCCLK_1 945GMCLK
19 4 1 RN29
PCIEX1 945GMCLK [5]
PCLK_ICH R308 33_04 PCLK0 8 20 SRCCLK_#1 3 2 4P2R_33_04 945GMCLK# CLK_PCIE_GLAN C151 10P_04(R)
[12] PCLK_ICH PCICLK_F0 PCIEX1# 945GMCLK# [5]
54 34
[9,12,16] SMB_ICHCLK SCLK PEREQ2# MCH_CLKREQ# [5] CLK_PCIE_GLAN#
55 R299 10K_04(R) C150 10P_04(R)
[9,12,16] SMB_ICHDATA SDATA SRCCLK_0 3VS DREFSSCLK
17 4 1 RN30
LCDCLK/PCIEX0 SRCCLK#0 DREFSSCLK# DREFSSCLK [5]
R128 0_04 10 18 3 2 4P2R_33_04
[12,21] CLKEN# VTT_PWRGD#/PD LCDCLK#/PCIEX0# DREFSSCLK# [5] 945GMCLK C168 10P_04(R)
16 R120 10K_04(R)
58 PEREQ1# 3VS
1

C448 22P_04 R318 X1 14 DREF_CLK 4 1 RN32 DREFCLK 945GMCLK# C167 10P_04(R)

27FIX/DOT96 DREF_CLK# DREFCLK# DREFCLK [5]
X2 15 3 2 4P2R_33_04
27SS/DOT96# DREFCLK# [5]
CLK48_CARDBUS C203 10P_04(R)
GNDA
VREF

14.318MHz 1M(R) 57
GND
GND
GND

GND
GND
GND

GND
GND
2

X2 CLK48_USB C204 10P_04(R)

C447 22P_04 ICS9LPR310BGLF KBC_PCLK C452 10P_04(R)

2
6
13
21

37

53
59
47

29

46

PCLK_ICH C205 10P_04(R)

PEREQ1#: PCIECLK 0, 6 PCLK_CARDBUS C212 10P_04(R)
PEREQ2#: PCIECLK 1, 8
R121 CLK14.3M_ICH C450 10P_04(R)
PEREQ3#: PCIECLK 2, 4
PEREQ4#: PCIECLK 3, 5, 7 PCLK_FWH C206 10P_04(R)
4.3K_1%_04
PEREQ[1..4]# have inte rnal pull up PCLK_SI/O C451 10P_04(R)

Layout note:
Place terminationclose to
CK410M
1.05VS 1.05VS

3/8
R309 R133

56_04 1K_04

R119 0_04 CLK_BSEL0 R134 0_04 CLK_BSEL2

[2] CPU_BSEL0 [2] CPU_BSEL2
3/8
R130 1K_04 R127 R132 0_04(R) R135
Host Clock
FSLC FSLB FS_A 1K_04 1K_04
Frequency
BSEL2 BSEL1 BSEL0
MCH_BSEL0 [5] MCH_BSEL2 [5]
100 MHz 1 0 1
1.05VS
133 MHz 0 0 1
166 MHz 0 1 1
R315
200 MHz 1 1 1
1K_04

R314 0_04 CLK_BSEL1

[2] CPU_BSEL1

R316 0_04(R) R313

1K_04
1.05VS [2,3,5,6,8,11,13,22]
3VS [2,5,6,9,10,11,12,13,14,15,16,18,20,21,24]
MCH_BSEL1 [5]

CLOCK GENERATOR B - 5
 Schematic Diagrams

CALISTOGA 1/4

H _D #[0..63] [2]
H_ A#[3.. 31] [2]
U 15 B

T32 AY 35 D DR CLK_A0 [9]

U15A R 32 RS VD _1 SM_C K_0 AR 1
H _D #0 F1 H9 H _A#3 F3 RS VD _2 SM_C K_1 AW 7 D DR CLK_A1 [9]
H _D #1 H _D #_0 H _A# _3 H _A#4 PM_E XTTS0 # RS VD _3 SM_C K_2 D DR CLK_B0 [9]
J1 C9 R9 7 10K_0 4 F7 AW 40
H _D #_1 H _A# _4 3V S RS VD _4 SM_C K_3 D DR CLK_B1 [9]

RSVD
H _D #2 H1 E11 H _A#5 AG 11
H _D #3 J6 H _D #_2 H _A# _5 G11 H _A#6 R1 06 10K_0 4 PM_E XTTS1 # R 96 0_04(R ) PM_E XTTS1#_ R AF 11 RS VD _5 AW 35
H _D #4 H _D #_3 H _A# _6 H _A#7 RS VD _6 S M_ CK #_0 D DR CLK_A0# [ 9]
H3 F11 H7 AT1 D DR CLK_A1# [ 9]
H _D #5 K2 H _D #_4 H _A# _7 G12 H _A#8 J19 RS VD _7 S M_ CK #_1 AY 7
H _D #6 H _D #_5 H _A# _8 H _A#9 PM_E XTTS0# RS VD _8 S M_ CK #_2 D DR CLK_B0# [ 9]
G1 F9 R 95 0_04 K30 AY 40
H _D #7 G2 H _D #_6 H _A# _9 H11 H _A#10 [9] PM_ EXTTS 1# J29 TV_DC ONSEL0 S M_ CK #_3 D DR CLK_B1# [ 9]
H _D #8 K9 H _D #_7 H_ A#_ 10 J12 H _A#11 R 107 0_04 PM_E XTTS1#_ R A41 TV_DC ONSEL1 AU 20
H _D #_8 H_ A#_ 11 [12,21] PM_DPRSLP VR RS VD _11 S M_ CKE_0 SCKE_A0 [9,10]
H _D #9 K1 G14 H _A#12 A35 AT20
H _D #1 0 K7 H _D #_9 H_ A#_ 12 D9 H _A#13 A34 RS VD _12 S M_ CKE_1 BA29 SCKE_A1 [9,10]
H _D #_10 H_ A#_ 13 RS VD _13 S M_ CKE_2 SCKE_B0 [9,10]

MUXING
H _D #1 1 J8 J14 H _A#14 D 28 AY 29
H _D #1 2 H4 H _D #_11 H_ A#_ 14 H13 H _A#15 D 27 RS VD _14 S M_ CKE_3 SCKE_B1 [9,10]
H _D #1 3 J3 H _D #_12 H_ A#_ 15 J15 H _A#16 RS VD _15 AW 13
H _D #_13 H_ A#_ 16 S M_ CS #_0 SCS_A0# [9,10]
H _D #1 4 K11 F14 H _A#17 AW 12
H _D #1 5 G4 H _D #_14 H_ A#_ 17 D12 H _A#18 R68 0_04 CF G0 K16 S M_ CS #_1 AY 21 SCS_A1# [9,10]
H _D #1 6 T10 H _D #_15 H_ A#_ 18 A11 H _A#19 [4] MC H_BSEL0 R29 1 0_04 CF G1 K18 CF G_ 0 S M_ CS #_2 AW 21 SCS_B0# [9,10]
H _D #1 7 W 11 H _D #_16 H_ A#_ 19 C11 H _A#20 [4] MC H_BSEL1 R29 0 0_04 CF G2 J18 CF G_ 1 S M_ CS #_3 SCS_B1# [9,10]
H _D #1 8 H _D #_17 H_ A#_ 20 H _A#21 [4] MC H_BSEL2 CF G3 CF G_ 2
T3 A12 F 18 AL20
H _D #1 9 H _D #_18 H_ A#_ 21 H _A#22 CF G4 CF G_ 3 SM_O CD C OMP_0
U7 A13 E15 AF 10
H _D #2 0 H _D #_19 H_ A#_ 22 H _A#23 MCH_BSEL[2..0] CF G5 CF G_ 4 SM_O CD C OMP_1
B.Schematic Diagrams

U9 E13 F 15
H _D #2 1 H _D #_20 H_ A#_ 23 H _A#24 CF G6 CF G_ 5
U 11 G13 001 = PSB533 E18 BA13

DDR
H _D #2 2 T11 H _D #_21 H_ A#_ 24 F12 H _A#25 CF G7 D 19 CF G_ 6 S M_ OD T_0 BA12 SOD T_A0 [9,10]
H _D #_22 H_ A#_ 25 CF G_ 7 S M_ OD T_1 SOD T_A1 [9,10]
H _D #2 3 W9
H _D #_23 H_ A#_ 26
B12 H _A#26 011 = PSB667 CF G8 D 16
CF G_ 8 S M_ OD T_2
AY 20 SOD T_B0 [9,10]

CFG
H _D #2 4 T1 B14 H _A#27 CF G9 G 16 AU 21
H _D #_24 H_ A#_ 27 CF G_ 9 S M_ OD T_3 SOD T_B1 [9,10]
H _D #2 5
H _D #2 6
T8
T4 H _D #_25 H_ A#_ 28
C12
A14
H _A#28
H _A#29
Others = Reserved CF G10
CF G11
E16
D 15 CF G_ 10 AV9 M_R C OMPN
H _D #2 7 W7 H _D #_26 H_ A#_ 29 C14 H _A#30 CF G12 G 15 CF G_ 11 S M_ RC OMP# AT9 M_R C OMPP
H _D #2 8 U5 H _D #_27 H_ A#_ 30 D14 H _A#31 CF G13 K15 CF G_ 12 SM_R CO MP

Sheet 5 of 29 H _D #2 9
H _D #3 0
H _D #3 1
W6
T9

T5
H _D #_28
H _D #_29
H _D #_30
H_ A#_ 31

H_ AD S#
E8
B9 H _A DS# [2]
CF G14
CF G15
CF G16
C 15
H 16
G 18
CF G_ 13
CF G_ 14
CF G_ 15
SM_V REF_0
SM_V REF_1
AK1
AK41
M_VREF_MC H R 311 1K_1% 1.8V

H _D #3 2 H _D #_31 H _A DS TB# _0 H _A DSTB#0 [2] CF G17 CF G_ 16

AB 7 C13 H 15 C443 C4 44 R 312
CALISTOGA 1/4 H _D #3 3
H _D #3 4
H _D #3 5
AA 9
W4
W3
H _D #_32
H _D #_33
H _D #_34
H _A DS TB# _1
H_VR EF _0
H_ BN R#
J13
C6
F6
HVR EF H _A DSTB#1 [2]

H _B NR # [2]
CF G18
CF G19
CF G20
J25
K27
J26
CF G_ 17
CF G_ 18
CF G_ 19 1U _X7R
1 K_1%
H _D #3 6 Y3 H _D #_35 H_BPR I# C7 H _B PR I# [2] CF G_ 20 .0 1U _04
H _D #_36 H_BR EQ #0 H _B R0# [2]

HOST
H _D #3 7 Y7 B7 G 28
H _D #3 8 W5 H _D #_37 H _C PU RS T# A7 H _C PU RS T# [2] [12 ] PM_ BMBU ST# PM_EXTTS0# F 25 PM_BMBUSY # AF 33
H _D #_38 H _D BS Y# H _D BSY # [2] [9] PM_E XTTS0 # PM_EXTTS#_0 G _C LK IN # 9 45GMCLK# [4]

PM
H _D #3 9 Y 10 C3 PM_EXTTS1#_R H 26 AG33
H _D #4 0 H _D #_39 H_ DE FE R# H _D EF ER # [2] PM_EXTTS#_1 G_ CL KIN 9 45GMCLK [4]
AB 8 J9 G6 A27
H _D PW R # [ 2] [2,11] PM_TH RMTR IP # D R EF CLK # [4]

CLK
H _D #4 1 W2 H _D #_40 H _DPW R# H8 DELAY _PW RGD AH 33 PM_TH R MTRIP# D_ RE FC LK IN # A26
H _D #4 2 H _D #_41 H _D RD Y# HVR EF H _D RD Y# [ 2] [12,21] DE LA Y_ PW RG D N B_R STIN # PW RO K D _R EF CL KIN D R EF CLK [ 4]
AA 4 K13 AH 34 C40
H _D #4 3 AA 7 H _D #_42 H_VR EF _1 RS TIN # D_RE FS SC LK IN # D41 D R EF SSC LK# [4]
H _D #4 4 AA 2 H _D #_43 J7 D _R EF SS CLKIN D R EF SSC LK [ 4]
H _D #_44 H_ DIN V# _0 H _D IN V#0 [ 2]

MISC
H _D #4 5 AA 6 W8 H 28
H _D #4 6 H _D #_45 H_ DIN V# _1 H _D IN V#1 [ 2] SD VO _C TR LC LK
AA10 U3 H _D IN V#2 [ 2] H 27
H _D #4 7 Y8 H _D #_46 H_ DIN V# _2 AB10 K28 SD VO _C TR LD ATA AE35
H _D #4 8 AA 1 H _D #_47 H_ DIN V# _3 H _D IN V#3 [ 2] [12] MCH _IC H_ SY NC # H 32 ICH _S YN C # DMI_ RXN_0 AF 39 D MI_TXN 0 [ 11]
H _D #4 9 AB 4 H _D #_48 K4 [4] MCH _C LKR EQ# CL K_R EQ0# DMI_ RXN_1 AG35 D MI_TXN 1 [ 11]
H _D #5 0 H _D #_49 H _D STB N# _0 H _D STBN #0 [2] DMI_ RXN_2 D MI_TXN 2 [ 11]
AC 9 T7 H _D STBN #1 [2] D1 AH 39 D MI_TXN 3 [ 11]
H _D #5 1 AB11 H _D #_50 H _D STB N# _1 Y5 C 41 NC 0 DMI_ RXN_3
H _D #5 2 H _D #_51 H _D STB N# _2 H _D STBN #2 [2] NC 1
A C 11 AC 4 C1
H _D #5 3 AB 3 H _D #_52 H _D STB N# _3 H _D STBN #3 [2] BA41 NC 2 AC 35
H _D #5 4 AC 2 H _D #_53 K3 BA40 NC 3 D MI_ RXP_0 AE39 D MI_TXP0 [ 11]
H _D #_54 H _D STBP# _0 H _D STBP#0 [2] NC 4 D MI_ RXP_1 D MI_TXP1 [ 11]
H _D #5 5 AD 1 T6 BA39 AF 35
H _D #5 6 H _D #_55 H _D STBP# _1 H _D STBP#1 [2] NC 5 D MI_ RXP_2 D MI_TXP2 [ 11]
AD 9 AA5 H _D STBP#2 [2] B A3 AG39 D MI_TXP3 [ 11]

DMI
H _D #5 7 AC 1 H _D #_56 H _D STBP# _2 AC 5 B A2 NC 6 D MI_ RXP_3
H _D #_57 H _D STBP# _3 H _D STBP#3 [2] NC 7

NC
H _D #5 8 AD 7 B A1
H _D #5 9 AC 6 H _D #_58 B41 NC 8 AE37
H _D #_59 NC 9 D MI_ TXN_0 D MI_R XN 0 [11]
H _D #6 0 AB 5 D3 B2 AF 41
H _D #6 1 H _D #_60 H _H IT# H _H IT# [2] NC 10 D MI_ TXN_1 D MI_R XN 1 [11]
A D 10 D4 AY 41 AG37
H _D #6 2 AD 4 H _D #_61 H_H ITM# B3 H _H ITM# [2] A Y1 NC 11 D MI_ TXN_2 AH 41 D MI_R XN 2 [11]
H _D #6 3 AC 8 H _D #_62 H _L OC K# H _LOC K# [2] AW 41 NC 12 D MI_ TXN_3 D MI_R XN 3 [11]
H _D #_63 A W1 NC 13
H XR CO MP H _R EQ #[ 0.. 4] [2] NC 14
E1 A40 AC 37 D MI_R XP0 [ 11]
H XS CO MP E2 H _XRC OMP D8 H _R EQ#0 A4 NC 15 D MI_ TXP_0 AE41
H XS WIN G H _XSC OMP H_RE Q# _0 H _R EQ#1 NC 16 D MI_ TXP_1 D MI_R XP1 [ 11]
E4 G8 A39 AF 37 D MI_R XP2 [ 11]
H _XSW IN G H_RE Q# _1 B8 H _R EQ#2 A3 NC 17 D MI_ TXP_2 AG41
H YR CO MP Y1 H_RE Q# _2 F8 H _R EQ#3 NC 18 D MI_ TXP_3 D MI_R XP3 [ 11]
H YS CO MP U1 H _Y RC OMP H_RE Q# _3 A8 H _R EQ#4 C AL ISTOG A
H YS WI NG W1 H _Y SC OMP H_RE Q# _4
H _Y SW IN G B4
H _R S# _0 H_RS#0 [2] CFG[17:3] have internal pullup resistors
AG 2 E6 CFG[20:18] have internal pulldown resistors
[4] MCH CLK AG 1 H _C LKIN H _R S# _1 D6 H_RS#1 [2]
[4] MCH CLK# H _C LKIN# H _R S# _2 H_RS#2 [2]
[CFG5] DMI Select Layout note:
E3 Low = DMI x 2 DD RC LK _A 0 Close to MCH
H _S LP CP U# H_CPUSLP # [2, 11] 1.05VS C FG 5
E7 H_TR DY # [2] High = DMI x 4 (Default) R 65 2.2K_04(R ) C158
H _TRD Y#
CA LI STOG A [CFG7] CPU Strap DD RC LK _A 0# 10P _04
R 70 Low = Reserved C FG 7 R 294 2.2K_04(R ) DD RC LK _A 1
High = Intel Pentium M (Default) C49
5/16
100_1%_04 [CFG9] PCIE Graphics Lane C FG 9 R 64 2.2K_04(R ) DD RC LK _A 1# 10P _04
HVREF Low = Lane Reverse Enable DD RC LK _B 0
High = Normal operation (Default) C69
R124 1 00 _04 NB_R STIN# R57 80.6_1% M_R CO MP N R 69 C 87
[1 2,1 4,2 0] PL T_RST# 1.8 V C FG 11 R 283 DD RC LK _B 0#
[CFG11]PSB 4X CLK ENABL 2.2K_04(R ) 10P _04
R56 80.6_1% M_R CO MP P . 1U_04 Low = Reserved DD RC LK _B 1
200_1%_04 High = 8X Enable (Default) C196

[CFG16]FSB Dynamic ODT C FG 16 R 76 2.2K_04(R ) DD RC LK _B 1# 10P _04

Low = Dynamic ODT Disabled
High = Dynamic ODT Enabled(Default) VCC PGD [1 2,2 2]
1. 05VS 1 .05 VS Layout note:
CLOS E TO GM CH C FG 18 R 296 3VS [2 ,4,6,9, 10, 11 ,12,13,14,15,16,18,20,21,24]
[CFG18]GMCH CORE VCC Select 1K_04(R)
MCH_HXSWING and MCH_HYSWING 3VS 2. 5VS [6 ,10 ,22 ]
Layout Notice: Low = 1.05V (Default) 1. 8V [8 ,9,23]
R 40 R 51 should be 10 mils traces and High = 1.5V 1. 05VS [2 ,3,4,6, 8,1 1,1 3,2 2]
10 mils wide, 20 mils spacing
20 mils spacing [CFG19]DMI LANE REVERSAL C FG 19 R 108 1K_04(R)
1.05VS 221_1%_04 2 21 _1% _0 4 3VS
Low = Normal (Default)
H Y SW ING H XS W ING High = Lanes Reversed
H XSC OMP R267 54. 9_1%_04
H YSCO MP R266 54. 9_1%_04 R 41 C 48 R 52 C66 [CFG20]PCIE backward interpoerability mode C FG 20 R 99 1K_04(R) 3VS
Low = Only SVDO or PCIE *1 is operational (Default)
H XRC OMP R268 24. 9_1%_04 . 1U _04 .1U _04 C FG 12 R 67 2.2K_04(R )
H YR CO MP R265 24. 9_1%_04 100_1%_04 1 00 _1% _0 4 High = SDVO and PCIE *1 are operating
C FG 13 R 66 2.2K_04(R )
simultaneously via the PEG port

hexainf@hotmail.com
B - 6 CALISTOGA 1/4
 Schematic Diagrams

CALISTOGA 2/4

+1.5 VS _A UX

R 337 0_08
1. 5VS
C1 30 C 10 6 C1 05 C 14 5

AG28

AG29
AC30
AD 30

AH30
AE28
AF28

AC 29
AD 29

AF29

AG30

AC 31

AF31
AK31
AE 29

AE 30
AF 30

AJ30
AK30

AE 31
AL 30
10U /10V_ 08 1 0U /10 V_ 08
10U/ 10 V_08 10 U/10V _0 8 U 15 H 1 .5VS
1. 05V S

VC C AU X2 0

V C CA UX17
V CC AU X16
V CC AU X1 5
VC C AU X1 4
VC CA U X1 3

V C CA UX11
V CC A UX10

V C CA UX 4
V CC AU X 3
VC CA U X19
VC CA UX18

VC CA UX12

V CC AU X9
V CC AU X8
VC C AU X7
VC CAU X6
VC CAUX 5

V CC AU X2
VC C AU X1
VC CAU X0
AH 22 R 12 3
AJ 21 VC CA U X21 A C1 4
C1 37 C 13 8 C1 04 C 10 7 AH 21 VC CA U X22 VTT_ 0 A B1 4
AJ 20 VC CA U X23 VTT_ 1 W 14 C 37 7 C3 73 C 37 8 C7 8 C 37 U1 5C 24. 9_ 1%_04
.1 U_X7R_ 04 .1U_ X7R _0 4 AH 20 VC CA U X24 VTT_ 2 V 14 +
D32 D 40
.1U _X7R _0 4 .1 U_X7 R_ 04 AH 19 VC CA U X25 VTT_ 3 T14 1 0U /10V_ 08 10U /10V _08 220U/4 V J30 L _BK LTCTL EXP_A_ COMPI D 38
P 19 VC CA U X26 VTT_ 4 R 14 10 U/ 10V_08 10 U/ 10V_ 08 [1 0] BL ON R 110 10K _04 H30 L _BK LTEN EXP_A _C OMPO
P 16 VC CA U X27 VTT_ 5 P 14 3V S R 109 10K _04 H29 L _C LKC TLA F 34
AH 15 VC CA U X28 VTT_ 6 N 14 R 98 10K _04 G26 L _C LKC TLB E XP_ A_ RXN_ 0 G38
VC CA U X29 VTT_ 7 3V S L _D DC _C LK E XP_ A_ RXN_ 1
P 15 M14 R 295 10K _04 G25 H 34
C9 1 C 14 6 C1 03 C 10 2 AH 14 VC CA U X30 VTT_ 8 L 14 R 122 1.5K _04 B38 L _D DC _D ATA E XP_ A_ RXN_ 2 J 38
AG14 VC CA U X31 VTT_ 9 A D1 3 C35 L _IBG E XP_ A_ RXN_ 3 L34
.1 U_X7R_ 04 .1U_ X7R _0 4 AF 14 VC CA U X32 V TT_1 0 A C1 3 C 90 C3 76 C 37 5 C3 74 C 47 C136 F32 L _VB G E XP_ A_ RXN_ 4 M38
VC CA U X33 V TT_1 1 [1 0] E NAV DD L _VD D EN E XP_ A_ RXN_ 5
.1U _X7R _0 4 .1 U_X7 R_ 04 AE 14 A B1 3 R 118 100 K_04 C33 N 34
Y 14 VC CA U X34 V TT_1 2 A A1 3 . 1U _X7R _04 .1U _X7R _04 1 U_X7 R C32 L _VR E FH E XP_ A_ RXN_ 6 P38
VC CA U X35 V TT_1 3 L _VR E FL E XP_ A_ RXN_ 7
AF 13 Y 13 .1 U_ X7R_ 04 .1 U_ X7R_ 04 1U _X7R R 34
VC CA U X36 V TT_1 4 E XP_ A_ RXN_ 8

B.Schematic Diagrams
AE 13 W 13 [10] LVDS -L CLKN A33 T38
AF 12 VC CA U X37 V TT_1 5 V 13 A32 L A_C LK # E XP_ A_ RXN_ 9 V34
VC CA U X38 V TT_1 6 [10] LVDS -L CLKP L A_C LK EXP_A _R XN _1 0
AE 12 U 13 E27 W 38
AD 12 VC CA U X39 V TT_1 7 T13 E26 L B_C LK # EXP_A _R XN _1 1 Y 34
VC CA U X40 V TT_1 8 R 13 C 88 C6 7 C 77 C8 9 C 79 C68 L B_C LK EXP_A _R XN _1 2 AA3 8
V TT_1 9 EXP_A _R XN _1 3

LVDS
N 13 [1 0] LV D S-L0N C37 AB3 4
C133 ,C135 ,C 137,C 139 V TT_2 0 L A_D A TA #_0 EXP_A _R XN _1 4
1 .5V S A H1 M13 . 1U _X7R _04 .1U _X7R _04 .1U _X7R _0 4 [1 0] LV D S-L1N B35 AC3 8
1.5 VS A H2 VC CD _H MPLL0 V TT_2 1 L 13 .1 U_ X7R_ 04 .1 U_ X7R_ 04 .1 U_ X7R_ 04 A37 L A_D A TA #_1 EXP_A _R XN _1 5
must with in 200 miles VC CD _H MPLL1 V TT_2 2 [1 0] LV D S-L2N L A_D A TA #_2
+1.5V S_DP LL A A B1 2 D 34

L48 H CB1608KF- 121T25

C 41 2 1U _X7 R
B 26
VC CA _D PLLA
V TT_2 3
V TT_2 4
V TT_2 5
A A1 2
Y 12
E XP _A_ RXP_ 0
E XP _A_ RXP_ 1
E XP _A_ RXP_ 2
F 38
G34 Sheet 6 of 29

GRAPHICS
W 12 [1 0] LV D S-L0P B37 H 38
V TT_2 6 L A_D A TA _0 E XP _A_ RXP_ 3
C 41 1 .1U _X7R _0 4 V 12 B34 J 34

L16 H CB1608KF- 121T25

C 17 4 1U _X7 R
+1.5V S_DP LL B

C 39
VC CA _D PLLB
V TT_2 7
V TT_2 8
V TT_2 9
V TT_3 0
U 12
T12
R 12
[1 0]
[1 0]
LV D S-L1P
LV D S-L2P A36 L A_D A TA _1
L A_D A TA _2
E XP _A_ RXP_ 4
E XP _A_ RXP_ 5
E XP _A_ RXP_ 6
E XP _A_ RXP_ 7
L38
M34
N 38
CALISTOGA 2/4
C 17 5 P 12 G30 P34
.1U _X7R _0 4 V TT_3 1 N 12 D30 L B_D A TA #_0 E XP _A_ RXP_ 8 R 38
+1 .5VS_ HP LL V TT_3 2 M12 F29 L B_D A TA #_1 E XP _A_ RXP_ 9 T34
C 37 0 1U _X7 R V TT_3 3 L 12 L B_D A TA #_2 EXP_A_R XP _1 0 V38
L41 H CB1608KF- 121T25 A F1 V TT_3 4 R 11 EXP_A_R XP _1 1 W 34
VC CA _H PLL V TT_3 5 P 11 EXP_A_R XP _1 2 Y 38
C 37 1 .1U _X7R _0 4 V TT_3 6 N 11 F30 EXP_A_R XP _1 3 AA3 4

C 43 1U _X7 R
+1 .5V S_MP LL
POWER V TT_3 7
V TT_3 8
V TT_3 9
M11
R 10
D29
F28
L B_D A TA _0
L B_D A TA _1
L B_D A TA _2
EXP_A_R XP _1 4
EXP_A_R XP _1 5
AB3 8

PCI-EXPRESS
L7 H CB1608KF- 121T25 A F2 P 10 F 36
C 42 VC CA _MPLL V TT_4 0 N 10 E XP_A _TXN_ 0 G40
.1U _X7R _0 4 V TT_4 1 M10 E XP_A _TXN_ 1 H 36
V TT_4 2 P9 E XP_A _TXN_ 2 J 40
A 28 V TT_4 3 N9 A16 E XP_A _TXN_ 3 L36
1. 5V S VC CD _L VD S0 V TT_4 4 [2 0] TVDA C_A TV_D A CA _OUT E XP_A _TXN_ 4
B 28 M9 C18 M40
VC CD _L VD S1 V TT_4 5 [2 0] TVDA C_B TV_D A CB _OUT E XP_A _TXN_ 5
C 28 R8 [2 0] TVDA C_C A19 N 36
VC CD _L VD S2 V TT_4 6 TV_D A CC _OUT E XP_A _TXN_ 6

TV
P8 P40
+2.5 VS _TXLV D S C 425 .1U _X7R _04 V TT_4 7 N8 R 63 150_1%_ 04 E XP_A _TXN_ 7 R 36
L15 H CB1608KF- 121T25 Wi th in V TT_4 8 M8 R 75 150_1%_ 04 E XP_A _TXN_ 8 T40
C 30 V TT_4 9 P7 R 28 2 150_1%_ 04 J20 E XP_A _TXN_ 9 V36
2.5VS 20 0 mils
VC C_ TXLV DS 0 V TT_5 0 N7 R 77 4.9 9K_04 TV_I RE F EXP_A_ TXN _1 0 W 40
V TT_5 1 EXP_A_ TXN _1 1
C 42 4 C 42 3 B 30 M7 B16 Y 36
VC C_ TXLV DS 1 V TT_5 2 TV_I RTNA EXP_A_ TXN _1 2
R6 C 121 22P _04(R ) B18 AA4 0
1U_ X7 R .1 U _X7R_ 04 A 30 V TT_5 3 P6 C 122 22P _04(R ) B19 TV_I RTNB EXP_A_ TXN _1 3 AB3 6
Wi thin VC C_ TXLV DS 2 V TT_5 4 M6 C 402 22P _04(R ) TV_I RTNC EXP_A_ TXN _1 4 AC4 0
V TT_5 5 A6 VTTLF _C AP 3 EXP_A_ TXN _1 5
20 0 mils
V TT_5 6 R5 E23 D 36
V TT_5 7 [10 ] B C RT_B LU E E XP_A _TXP_ 0
C 173 .1U _X7R _04 P5 C381 R 86 1 50_1%_0 4 D23 F 40
V TT_5 8 C RT_B LU E# E XP_A _TXP_ 1
2 .5V S A 38 N5 [10 ] G C22 G36
VC CA _L VD S V TT_5 9 C RT_GRE EN E XP_A _TXP_ 2

VGA
B 39 M5 .47U R 85 1 50_1%_0 4 B22 H 40
With in VS SA_L VD S V TT_6 0 P4 A21 C RT_GRE EN # E XP_A _TXP_ 3 J 36
V TT_6 1 [10 ] R C RT_R ED E XP_A _TXP_ 4
200 mi ls N4 R 289 1 50_1%_0 4 B21 L40
+1 .5VS_ PC IE AJ 41 V TT_6 2 M4 C RT_R ED # E XP_A _TXP_ 5 M36
L49 H CB1608KF- 121T25 AB 41 VC C3 G0 V TT_6 3 R3 E XP_A _TXP_ 6 N 40
Y 41 VC C3 G1 V TT_6 4 P3 E XP_A _TXP_ 7 P36
1.5VS VC C3 G2 V TT_6 5 E XP_A _TXP_ 8
V 41 N3 R 40
C 21 7 C4 46 C 44 5 R 41 VC C3 G3 V TT_6 6 M3 C26 E XP_A _TXP_ 9 T36
5/16 +
N 41 VC C3 G4 V TT_6 7 R2 [1 0] VGAD D CC LK C25 C RT_D DC _C LK EXP_A_ TXP_1 0 V40
330U/ 3V 10U /1 0V_ 08 L 41 VC C3 G5 V TT_6 8 P2 [1 0] V GA DD CD A TA R 100 39.2 _1% G23 C RT_D DC _D ATA EXP_A_ TXP_1 1 W 36
VC C3 G6 V TT_6 9 [1 0] H SY C RT_H SY NC EXP_A_ TXP_1 2
10U/ 10 V_08 M2 R 101 39.2 _1% H23 Y 40
V TT_7 0 VTTLF _C AP 2 [1 0] VS Y C RT_V SY NC EXP_A_ TXP_1 3
C 176 .1U _X7R _04 D2 R 88 255 _1% J22 AA3 6
G41 V TT_7 1 A B1 VTTLF _C AP 1 C RT_IR E F EXP_A_ TXP_1 4 AB4 0
2.5 VS H 41 VC CA _3 GBG V TT_7 2 R1 EXP_A_ TXP_1 5
W ithin VS SA_3 GB G V TT_7 3 P1 C372 C 379 CA LIS TOGA
2 00 mi ls V TT_7 4 N1
V TT_7 5 M1 .47U . 22U
+1.5V S _3GPL L V TT_7 6 +3VS_ ATVB G 3VS
L45 H CB16 08KF-12 1T25
L17 H CB16 08KF-12 1T25 AC 33 C3 93 C 101
1. 5V S VC CA _3 GPLL 1.5V S C6 11
+
C 17 7 C157 F 19 10U_ 08 .1U _X7R _0 4
VC C A_ TVD A CA 1 E 19 +3V S_ TVDA CA 33 0U /6. 3V
10U /10V _0 8 .1U _X7R _0 4 VC C A_ TVD A CA 0

A
D 20 5 /18
VC C A_ TVD A CB 1 +3V S_ TVDA CB +3 VS_TVD AC A
3VS A 23 C 20 L11 H CB16 08KF-12 1T25 D 10
B 23 VC C_ HV 0 VC C A_ TVD A CB 0 C8 6 C 100
B 25 VC C_ HV 1 F 20
VC C_ HV 2 VC C A_TVD AC C 1 +3V S_ TVDA CC +1. 5V S_A U X [ 8]
R 87 10 D 13 SC S551V E 20 10U_ 08 .1U _X7R _0 4 SC S551 V
3 VS [2,4 ,5 ,9,1 0, 11, 12,13 ,14,15 ,1 6,18,2 0,21,2 4]

C
C A +2. 5V S_C R TD AC VC C A_TVD AC C 0 3/20
2.5VS 1 .05 VS 1 .0 5V S [2,3 ,4 ,5,8 ,11,1 3,22]
F 21 G20 5/ 18
VC CA _C R TD AC 0 VS SA _TV B G 1 .5 VS [3,1 1, 13, 16,24 ]
L14 H CB1608KF- 121T25 H 20 +3V S_ ATVB G +3 VS_TVD AC B 1 .8 V [5,8 ,9 ,23]
V C CA _TV B G
E 21 L12 H CB16 08KF-12 1T25 2 .5 VS [10,22 ]
VC CA _C R TD AC 1 +1. 5VS_QTV D AC C9 8 C 120 R 55
C1 24 G21 L13 HC B1608 KF -121T25
VS SA_C RTDA C H 19 10U_ 08 .1U _X7R _0 4 10
V CC DQ_TVD A C 1.5VS
.1U_ X7R _0 4 2. 5V S H 22 D 21
VC CS Y NC VC CD _TVD A C
W ithin +3 VS_TVD AC C
C125 L46 H CB16 08KF-12 1T25
2 50 mi ls C9 9 C1 42 C123 C3 97 C 401
.1 U_X7 R_ 04 C AL IS TOGA
.1 U_ X7R _04 . 1U _X7 R_04 10U_ 08 . 1U _X7R _04
W ith in .1 U_ X7 R_ 04 Wit hin
2 50 mi ls 250 mils

CALISTOGA 2/4 B - 7
 Schematic Diagrams

CALISTOGA 3/4

SDQ_B[0..63]
SDQ_B[0..63] [9]

SDQ_A[0..63] [9]
SBA_A[0..2]
SBA_A[0..2] [9,10]
U15D
SDQ_A0 AJ35 AU12 SBA_A0 U15E SBA_B[0..2]
SDQ_A1 SA_DQ0 SA_BS_0 SBA_A1 SDQ_B0 SBA_B[0..2] [9,10]
AJ34 AV14 AK39
SDQ_A2 AM31 SA_DQ1 SA_BS_1 BA20 SBA_A2 SDQ_B1 AJ37 SB_DQ0 AT24 SBA_B0
SDQ_A3 AM33 SA_DQ2 SA_BS_2 SDM_A[0..7] SDQ_B2 AP39 SB_DQ1 SB_BS_0 AV23 SBA_B1
SDQ_A4 SA_DQ3 SDM_A[0..7] [9] SDQ_B3 SB_DQ2 SB_BS_1 SBA_B2
AJ36 AR41 AY28
SDQ_A5 AK35 SA_DQ4 AJ33 SDM_A0 SDQ_B4 AJ38 SB_DQ3 SB_BS_2 SDM_B[0..7]
SDQ_A6 SA_DQ5 SA_DM_0 SDM_A1 SDQ_B5 SB_DQ4 SDM_B[0..7] [9]
AJ32 AM35 AK38
SDQ_A7 AH31 SA_DQ6 SA_DM_1 AL26 SDM_A2 SDQ_B6 AN41 SB_DQ5 AK36 SDM_B0
SDQ_A8 AN35 SA_DQ7 SA_DM_2 AN22 SDM_A3 SDQ_B7 AP41 SB_DQ6 SB_DM_0 AR38 SDM_B1
SDQ_A9 AP33 SA_DQ8 SA_DM_3 AM14 SDM_A4 SDQ_B8 AT40 SB_DQ7 SB_DM_1 AT36 SDM_B2
SDQ_A10 AR31 SA_DQ9 SA_DM_4 AL9 SDM_A5 SDQ_B9 AV41 SB_DQ8 SB_DM_2 BA31 SDM_B3
SDQ_A11 AP31 SA_DQ10 SA_DM_5 AR3 SDM_A6 SDQ_B10 AU38 SB_DQ9 SB_DM_3 AL17 SDM_B4
SDQ_A12 AN38 SA_DQ11 SA_DM_6 AH4 SDM_A7 SDQS_A[0..7] SDQ_B11 AV38 SB_DQ10 SB_DM_4 AH8 SDM_B5
SDQ_A13 SA_DQ12 SA_DM_7 SDQS_A[0..7] [9] SDQ_B12 SB_DQ11 SB_DM_5 SDM_B6
AM36 AP38 BA5
B.Schematic Diagrams

SDQ_A14 AM34 SA_DQ13 AK33 SDQS_A0 SDQ_B13 AR40 SB_DQ12 SB_DM_6 AN4 SDM_B7
SDQ_A15 AN33 SA_DQ14 SA_DQS_0 AT33 SDQS_A1 SDQ_B14 AW38 SB_DQ13 SB_DM_7 SDQS_B[0..7]

A
SDQ_A16 SA_DQ15 SA_DQS_1 SDQS_A2 SDQ_B15 SB_DQ14 SDQS_B[0..7] [9]
AK26 AN28 AY 38
SDQ_A17 AL27 SA_DQ16 SA_DQS_2 AM22 SDQS_A3 SDQ_B16 BA38 SB_DQ15 AM39 SDQS_B0

B
SDQ_A18 AM26 SA_DQ17 SA_DQS_3 AN12 SDQS_A4 SDQ_B17 AV36 SB_DQ16 SB_DQS_0 AT39 SDQS_B1
SDQ_A19 AN24 SA_DQ18 SA_DQS_4 AN8 SDQS_A5 SDQ_B18 AR36 SB_DQ17 SB_DQS_1 AU35 SDQS_B2
SDQ_A20 AK28 SA_DQ19 SA_DQS_5 AP3 SDQS_A6 SDQ_B19 AP36 SB_DQ18 SB_DQS_2 AR29 SDQS_B3

MEMORY
SDQ_A21 SA_DQ20 SA_DQS_6 SDQS_A7 SDQ_B20 SB_DQ19 SB_DQS_3 SDQS_B4
Sheet 7 of 29 SDQ_A22
AL28
AM24 SA_DQ21 SA_DQS_7
AG5
SDQS_A#[0..7] SDQ_B21
BA36
AU36 SB_DQ20 SB_DQS_4
AR16
AR10 SDQS_B5

MEMORY
SDQ_A23 SA_DQ22 SDQS_A#[0..7] [9] SDQ_B22 SB_DQ21 SB_DQS_5 SDQS_B6
AP26 AP35 AR7
SDQ_A24 AP23 SA_DQ23 AK32 SDQS_A#0 SDQ_B23 AP34 SB_DQ22 SB_DQS_6 AN5 SDQS_B7

CALISTOGA 3/4 SDQ_A25

SDQ_A26
SDQ_A27
AL22
AP21
AN20
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
AU33
AN27
AM21
SDQS_A#1
SDQS_A#2
SDQS_A#3
SDQ_B24
SDQ_B25
SDQ_B26
AY 33
BA33
AT31
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQS_7

AM40 SDQS_B#0
SDQS_B#[0..7]
SDQS_B#[0..7] [9]

SDQ_A28 AL23 SA_DQ27 SA_DQS#_3 AM12 SDQS_A#4 SDQ_B27 AU29 SB_DQ26 SB_DQS#_0 AU39 SDQS_B#1
SDQ_A29 AP24 SA_DQ28 SA_DQS#_4 AL8 SDQS_A#5 SDQ_B28 AU31 SB_DQ27 SB_DQS#_1 AT35 SDQS_B#2
SDQ_A30 AP20 SA_DQ29 SA_DQS#_5 AN3 SDQS_A#6 SDQ_B29 AW31 SB_DQ28 SB_DQS#_2 AP29 SDQS_B#3
SDQ_A31 AT21 SA_DQ30 SA_DQS#_6 AH5 SDQS_A#7 SDQ_B30 AV29 SB_DQ29 SB_DQS#_3 AP16 SDQS_B#4
SDQ_A32 AR12 SA_DQ31 SA_DQS#_7 SDQ_B31 AW29 SB_DQ30 SB_DQS#_4 AT10 SDQS_B#5
SA_DQ32 SMAA_A[0..13] SB_DQ31 SB_DQS#_5

SYSTEM
SDQ_A33 AR14 SDQ_B32 AM19 AT7 SDQS_B#6
SDQ_A34 SA_DQ33 SMAA_A[0..13] [9,10] SDQ_B33 SB_DQ32 SB_DQS#_6 SDQS_B#7
AP13 AL19 AP5
SA_DQ34 SB_DQ33 SB_DQS#_7 SMAA_B[0..13]

SYSTEM
SDQ_A35 AP12 AY 16 SMAA_A0 SDQ_B34 AP14
SDQ_A36 SA_DQ35 SA_MA_0 SMAA_A1 SDQ_B35 SB_DQ34 SMAA_B[0..13] [9,10]
AT13 AU14 AN14
SDQ_A37 AT12 SA_DQ36 SA_MA_1 AW16 SMAA_A2 SDQ_B36 AN17 SB_DQ35 AY23 SMAA_B0
SDQ_A38 AL14 SA_DQ37 SA_MA_2 BA16 SMAA_A3 SDQ_B37 AM16 SB_DQ36 SB_MA_0 AW24 SMAA_B1
SDQ_A39 AL12 SA_DQ38 SA_MA_3 BA17 SMAA_A4 SDQ_B38 AP15 SB_DQ37 SB_MA_1 AY24 SMAA_B2
SDQ_A40 AK9 SA_DQ39 SA_MA_4 AU16 SMAA_A5 SDQ_B39 AL15 SB_DQ38 SB_MA_2 AR28 SMAA_B3
SDQ_A41 AN7 SA_DQ40 SA_MA_5 AV17 SMAA_A6 SDQ_B40 AJ11 SB_DQ39 SB_MA_3 AT27 SMAA_B4
SDQ_A42 AK8 SA_DQ41 SA_MA_6 AU17 SMAA_A7 SDQ_B41 AH10 SB_DQ40 SB_MA_4 AT28 SMAA_B5
SDQ_A43 AK7 SA_DQ42 SA_MA_7 AW17 SMAA_A8 SDQ_B42 AJ9 SB_DQ41 SB_MA_5 AU27 SMAA_B6
SDQ_A44 AP9 SA_DQ43 SA_MA_8 AT16 SMAA_A9 SDQ_B43 AN10 SB_DQ42 SB_MA_6 AV28 SMAA_B7
SDQ_A45 AN9 SA_DQ44 SA_MA_9 AU13 SMAA_A10 SDQ_B44 AK13 SB_DQ43 SB_MA_7 AV27 SMAA_B8
DDR
SDQ_A46 AT5 SA_DQ45 SA_MA_10 AT17 SMAA_A11 SDQ_B45 AH11 SB_DQ44 SB_MA_8 AW27 SMAA_B9
SDQ_A47 AL5 SA_DQ46 SA_MA_11 AV20 SMAA_A12 SDQ_B46 AK10 SB_DQ45 SB_MA_9 AV24 SMAA_B10

DDR
SDQ_A48 AY 2 SA_DQ47 SA_MA_12 AV12 SMAA_A13 SDQ_B47 AJ8 SB_DQ46 SB_MA_10 BA27 SMAA_B11
SDQ_A49 AW2 SA_DQ48 SA_MA_13 SDQ_B48 BA10 SB_DQ47 SB_MA_11 AY27 SMAA_B12
SDQ_A50 AP1 SA_DQ49 SDQ_B49 AW10 SB_DQ48 SB_MA_12 AR23 SMAA_B13
SDQ_A51 AN2 SA_DQ50 AY 13 SCAS_A# SDQ_B50 BA4 SB_DQ49 SB_MA_13
SDQ_A52 SA_DQ51 SA_CAS# SRAS_A# SCAS_A# [9,10] SDQ_B51 SB_DQ50 SCAS_B#
AV2 AW14 AW4 AR24
SDQ_A53 SA_DQ52 SA_RAS# SW E_A# SRAS_A# [9,10] SDQ_B52 SB_DQ51 SB_CAS# SRAS_B# SCAS_B# [9,10]
AT3 AY 14 AY 10 AU23
SDQ_A54 SA_DQ53 SA_W E# SWE_A# [9,10] SDQ_B53 SB_DQ52 SB_RAS# SW E_B# SRAS_B# [9,10]
AN1 AY 9 AR27
SDQ_A55 SA_DQ54 SDQ_B54 SB_DQ53 SB_WE# SW E_B# [9,10]
AL2 AK23 AW5
SDQ_A56 AG7 SA_DQ55 SA_RCVENIN# AK24 SDQ_B55 AY 5 SB_DQ54 AK16
SDQ_A57 AF9 SA_DQ56 SA_RCVENOUT# SDQ_B56 AV4 SB_DQ55 SB_RCVENIN# AK18
SDQ_A58 AG4 SA_DQ57 SDQ_B57 AR5 SB_DQ56 SB_RCVENOUT#
SDQ_A59 AF6 SA_DQ58 SDQ_B58 AK4 SB_DQ57
SDQ_A60 AG9 SA_DQ59 SDQ_B59 AK3 SB_DQ58
SDQ_A61 AH6 SA_DQ60 SDQ_B60 AT4 SB_DQ59
SDQ_A62 AF4 SA_DQ61 SDQ_B61 AK5 SB_DQ60
SDQ_A63 AF8 SA_DQ62 SDQ_B62 AJ5 SB_DQ61
SA_DQ63 SDQ_B63 AJ3 SB_DQ62
CALISTOGA SB_DQ63
CALISTOGA

hexainf@hotmail.com
B - 8 CALISTOGA 3/4
 Schematic Diagrams

CALISTOGA 4/4

U 15G
1.05VS AA33
W 33 VCC _0 AU 41
P33 VCC _1 VC C_SM_0 AT41 U15F U 15I U15J
N 33 VCC _2 VC C_SM_1 AM41 AD 27 AC 41 AK34 AT23 J11
L33 VCC _3 VC C_SM_2 AU 40 AC 27 VCC _N CTF0 AE27 AA41 VSS_0 VSS_97 AG34 AN 23 VSS_180 VSS_273 D11
J 33 VCC _4 VC C_SM_3 BA34 C 442 C441 AB27 VCC _N CTF1 VSS_N CTF0 AE26 W 41 VSS_1 VSS_98 AF34 AM23 VSS_181 VSS_274 B11
AA32 VCC _5 VC C_SM_4 AY 34 AA27 VCC _N CTF2 VSS_N CTF1 AE25 T41 VSS_2 VSS_99 AE34 AH 23 VSS_182 VSS_275 AV10
Y 32 VCC _6 VC C_SM_5 AW 34 .47U .47U Y 27 VCC _N CTF3 VSS_N CTF2 AE24 P41 VSS_3 VSS_100 AC34 AC 23 VSS_183 VSS_276 AP10
W 32 VCC _7 VC C_SM_6 AV34 W 27 VCC _N CTF4 VSS_N CTF3 AE23 M41 VSS_4 VSS_101 C 34 W 23 VSS_184 VSS_277 AL10
V32 VCC _8 VC C_SM_7 AU 34 V27 VCC _N CTF5 VSS_N CTF4 AE22 J 41 VSS_5 VSS_102 AW 33 K23 VSS_185 VSS_278 AJ10
P32 VCC _9 VC C_SM_8 AT34 U 27 VCC _N CTF6 VSS_N CTF5 AE21 F 41 VSS_6 VSS_103 AV33 J 23 VSS_186 VSS_279 AG10
N 32 VCC _10 VC C_SM_9 AR 34 T27 VCC _N CTF7 VSS_N CTF6 AE20 AV40 VSS_7 VSS_104 AR33 F 23 VSS_187 VSS_280 AC 10
M32 VCC _11 VCC _SM_10 BA30 R 27 VCC _N CTF8 VSS_N CTF7 AE19 AP40 VSS_8 VSS_105 AE33 C 23 VSS_188 VSS_281 W10
L32 VCC _12 VCC _SM_11 AY 30 AD 26 VCC _N CTF9 VSS_N CTF8 AE18 AN 40 VSS_9 VSS_106 AB33 AA22 VSS_189 VSS_282 U10
J 32 VCC _13 VCC _SM_12 AW 30 AC 26 VCC _N CTF10 VSS_N CTF9 AC 17 AK40 VSS_10 VSS_107 Y 33 K22 VSS_190 VSS_283 BA9
AA31 VCC _14 VCC _SM_13 AV30 1.8V AB26 VCC _N CTF11 VSS_N CTF 10 Y17 AJ 40 VSS_11 VSS_108 V33 G22 VSS_191 VSS_284 AW 9
W 31 VCC _15 VCC _SM_14 AU 30 C 392 C431 AA26 VCC _N CTF12 VSS_N CTF 11 U17 AH 40 VSS_12 VSS_109 T33 F 22 VSS_192 VSS_285 AR 9
V31 VCC _16 VCC _SM_15 AT30 Y 26 VCC _N CTF13 VSS_N CTF 12 AG40 VSS_13 VSS_110 R 33 E22 VSS_193 VSS_286 AH 9
T31 VCC _17 VCC _SM_16 AR 30 10U /10V_08 10U/ 10V_08 W 26 VCC _N CTF14 AF 40 VSS_14 VSS_111 M33 D 22 VSS_194 VSS_287 AB9
R 31 VCC _18 VCC _SM_17 AP30 V26 VCC _N CTF15 AE40 VSS_15 VSS_112 H 33 A22 VSS_195 VSS_288 Y9
P31 VCC _19 VCC _SM_18 AN 30 U 26 VCC _N CTF16 B40 VSS_16 VSS_113 G33 BA21 VSS_196 VSS_289 R9
N 31 VCC _20 VCC _SM_19 AM30 T26 VCC _N CTF17 AY 39 VSS_17 VSS_114 F 33 AV21 VSS_197 VSS_290 G9
M31 VCC _21 VCC _SM_20 AM29 R 26 VCC _N CTF18 AG27 AW 39 VSS_18 VSS_115 D 33 AR 21 VSS_198 VSS_291 E9
VCC _22 VCC _SM_21 VCC _N CTF19 VCC AU X_N CTF0 VSS_19 VSS_116 VSS_199 VSS_292

B.Schematic Diagrams
AA30 AL29 AD 25 AF27 AV39 B33 AN 21 A9
Y 30 VCC _23 VCC _SM_22 AK29 AC 25 VCC _N CTF20 VCC AU X_N CTF1 AG26 AR 39 VSS_20 VSS_117 AH32 AL21 VSS_200 VSS_293 AG8
W 30 VCC _24 VCC _SM_23 AJ 29 C 399 C380 C 92 AB25 VCC _N CTF21 VCC AU X_N CTF2 AF26 AN 39 VSS_21 VSS_118 AG32 AB21 VSS_201 VSS_294 AD 8
V30 VCC _25 VCC _SM_24 AH 29
+
AA25 VCC _N CTF22 VCC AU X_N CTF3 AG25 AJ 39 VSS_22 VSS_119 AF32 Y 21 VSS_202 VSS_295 AA8
U 30 VCC _26 VCC _SM_25 AJ 28 10U /10V_08 10U/ 10V_08 220u/2.5V_B Y 25 VCC _N CTF23 VCC AU X_N CTF4 AF25 AC 39 VSS_23 VSS_120 AE32 P21 VSS_203 VSS_296 U8
T30 VCC _27 VCC _SM_26 AH 28 W 25 VCC _N CTF24 VCC AU X_N CTF5 AG24 AB39 VSS_24 VSS_121 AC32 K21 VSS_204 VSS_297 K8
R 30 VCC _28 VCC _SM_27 AJ 27 V25 VCC _N CTF25 VCC AU X_N CTF6 AF24 AA39 VSS_25 VSS_122 AB32 J 21 VSS_205 VSS_298 C8
P30 VCC _29 VCC _SM_28 AH 27 U 25 VCC _N CTF26 VCC AU X_N CTF7 AG23 Y 39 VSS_26 VSS_123 G32 H 21 VSS_206 VSS_299 BA7
N 30 VCC _30 VCC _SM_29 BA26 T25 VCC _N CTF27 VCC AU X_N CTF8 AF23 W 39 VSS_27 VSS_124 B32 C 21 VSS_207 VSS_300 AV7
M30
L30
AA29
VCC _31
VCC _32
VCC _33
VCC _SM_30
VCC _SM_31
VCC _SM_32
AY 26
AW 26
AV26
C 422 C385 C400
R 25
AD 24
AC 24
VCC _N CTF28
VCC _N CTF29
VCC _N CTF30
VCC AU X_N CTF9
VC CAUX_N CTF 10
VC CAUX_N CTF 11
AG22
AF22
AG21
V39
T39
R 39
VSS_28
VSS_29
VSS_30
VSS_125
VSS_126
VSS_127
AY31
AV31
AN31
AW 20
AR 20
AM20
VSS_208
VSS_209
VSS_210
VSS
VSS_301
VSS_302
VSS_303
AP7
AL7
AJ7
Sheet 8 of 29
Y 29 VCC _34 VCC _SM_33 AU 26 . 1U _X7R_04 .1U _X7R_04 .1U_X7R _04 AB24 VCC _N CTF31 VC CAUX_N CTF 12 AF21 P39 VSS_31 VSS_128 AJ31 AA20 VSS_211 VSS_304 AH 7
W 29
V29
U 29
VCC _35
VCC _36
VCC _37
VCC _SM_34
VCC _SM_35
VCC _SM_36
AT26
AR 26
AJ 26
AA24
Y 24
W 24
VCC _N CTF32
VCC _N CTF33
VCC _N CTF34
VC CAUX_N CTF 13
VC CAUX_N CTF 14
VC CAUX_N CTF 15
AG20
AF20
AG19
N 39
M39
L39
VSS_32
VSS_33
VSS_34 VSS
VSS_129
VSS_130
VSS_131
AG31
AB31
Y 31
K20
B20
A20
VSS_212
VSS_213
VSS_214
VSS_305
VSS_306
VSS_307
AF7
AC 7
R7
CALISTOGA 4/4
R 29 VCC _38 VCC _SM_37 AH 26 V24 VCC _N CTF35 VC CAUX_N CTF 16 AF19 J 39 VSS_35 VSS_132 AB30 AN 19 VSS_215 VSS_308 G7
P29 VCC _39 VCC _SM_38 AJ 25 U 24 VCC _N CTF36 VC CAUX_N CTF 17 R19 H 39 VSS_36 VSS_133 E30 AC 19 VSS_216 VSS_309 D7
M29 VCC _40 VCC _SM_39 AH 25 T24 VCC _N CTF37 VC CAUX_N CTF 18 AG18 G39 VSS_37 VSS_134 AT29 W 19 VSS_217 VSS_310 AG6
L29 VCC _41 VCC _SM_40 AJ 24 R 24 VCC _N CTF38 VC CAUX_N CTF 19 AF18 F 39 VSS_38 VSS_135 AN29 K19 VSS_218 VSS_311 AD 6
AB28 VCC _42 VCC _SM_41 AH 24 AD 23 VCC _N CTF39 VC CAUX_N CTF 20 R18 D 39 VSS_39 VSS_136 AB29 G19 VSS_219 VSS_312 AB6
AA28 VCC _43 VCC _SM_42 BA23 V23 VCC _N CTF40 VC CAUX_N CTF 21 AG17 AT38 VSS_40 VSS_137 T29 C 19 VSS_220 VSS_313 Y6
Y 28 VCC _44 VCC _SM_43 AJ 23 U 23 VCC _N CTF41 VC CAUX_N CTF 22 AF17 AM38 VSS_41 VSS_138 N 29 AH 18 VSS_221 VSS_314 U6
V28 VCC _45 VCC _SM_44 BA22 C421 T23 VCC _N CTF42 VC CAUX_N CTF 23 AE17 AH 38 VSS_42 VSS_139 K29 P18 VSS_222 VSS_315 N6
U 28 VCC _46 VCC _SM_45 AY 22 R 23 VCC _N CTF43 VC CAUX_N CTF 24 AD 17 AG38 VSS_43 VSS_140 G29 H 18 VSS_223 VSS_316 K6
T28 VCC _47 VCC _SM_46 AW 22 .47U AD 22 VCC _N CTF44 VC CAUX_N CTF 25 AB17 AF 38 VSS_44 VSS_141 E29 D 18 VSS_224 VSS_317 H6
R 28 VCC _48 VCC _SM_47 AV22 V22 VCC _N CTF45 VC CAUX_N CTF 26 AA17 AE38 VSS_45 VSS_142 C 29 A18 VSS_225 VSS_318 B6
P28 VCC _49 VCC _SM_48 AU 22 U 22 VCC _N CTF46 VC CAUX_N CTF 27 W17 C 38 VSS_46 VSS_143 B29 AY 17 VSS_226 VSS_319 AV5
N 28 VCC _50 VCC _SM_49 AT22 T22 VCC _N CTF47 VC CAUX_N CTF 28 V17 AK37 VSS_47 VSS_144 A29 AR 17 VSS_227 VSS_320 AF5
M28 VCC _51 VCC _SM_50 AR 22 R 22 VCC _N CTF48 VC CAUX_N CTF 29 T17 AH 37 VSS_48 VSS_145 BA28 AP17 VSS_228 VSS_321 AD 5
L28 VCC _52 VCC _SM_51 AP22 AD 21 VCC _N CTF49 VC CAUX_N CTF 30 R17 AB37 VSS_49 VSS_146 AW 28 AM17 VSS_229 VSS_322 AY 4
P27
N 27
VCC _53
VCC _54
VCC _55
VCC _SM_52
VCC _SM_53
VCC _SM_54
AK22
AJ 22
V21
U 21
VCC _N CTF50
VCC _N CTF51
VCC _N CTF52
NCTF VC CAUX_N CTF 31
VC CAUX_N CTF 32
VC CAUX_N CTF 33
AG16
AF16
AA37
Y 37
VSS_50
VSS_51
VSS_52
VSS_147
VSS_148
VSS_149
AU28
AP28
AK17
AV16
VSS_230
VSS_231
VSS_232
VSS_323
VSS_324
VSS_325
AR 4
AP4
M27 AK21 T21 AE16 W 37 AM28 AN 16 AL4
L27 VCC _56 VCC _SM_55 AK20 R 21 VCC _N CTF53 VC CAUX_N CTF 34 AD 16 V37 VSS_53 VSS_150 AD28 AL16 VSS_233 VSS_326 AJ4
P26 VCC _57 VCC _SM_56 BA19 AD 20 VCC _N CTF54 VC CAUX_N CTF 35 AC 16 T37 VSS_54 VSS_151 AC28 J 16 VSS_234 VSS_327 Y4
N 26 VCC _58 VCC _SM_57 AY 19 V20 VCC _N CTF55 VC CAUX_N CTF 36 AB16 R 37 VSS_55 VSS_152 W 28 F 16 VSS_235 VSS_328 U4
L26 VCC _59 VCC _SM_58 AW 19 U 20 VCC _N CTF56 VC CAUX_N CTF 37 AA16 P37 VSS_56 VSS_153 J 28 C 16 VSS_236 VSS_329 R4
N 25 VCC _60 VCC _SM_59 AV19 T20 VCC _N CTF57 VC CAUX_N CTF 38 Y16 N 37 VSS_57 VSS_154 E28 AN 15 VSS_237 VSS_330 J4
M25 VCC _61 VCC _SM_60 AU 19 R 20 VCC _N CTF58 VC CAUX_N CTF 39 W16 M37 VSS_58 VSS_155 AP27 AM15 VSS_238 VSS_331 F4
L25 VCC _62 VCC _SM_61 AT19 AD 19 VCC _N CTF59 VC CAUX_N CTF 40 V16 L37 VSS_59 VSS_156 AM27 AK15 VSS_239 VSS_332 C4
P24 VCC _63 VCC _SM_62 AR 19 V19 VCC _N CTF60 VC CAUX_N CTF 41 U16 J 37 VSS_60 VSS_157 AK27 N 15 VSS_240 VSS_333 AY 3
N 24 VCC _64 VCC _SM_63 AP19 U 19 VCC _N CTF61 VC CAUX_N CTF 42 T16 H 37 VSS_61 VSS_158 J 27 M15 VSS_241 VSS_334 AW 3
M24 VCC _65 VCC _SM_64 AK19 T19 VCC _N CTF62 VC CAUX_N CTF 43 R16 G37 VSS_62 VSS_159 G27 L15 VSS_242 VSS_335 AV3
AB23 VCC _66 VCC _SM_65 AJ 19 AD 18 VCC _N CTF63 VC CAUX_N CTF 44 AG15 F 37 VSS_63 VSS_160 F 27 B15 VSS_243 VSS_336 AL3
AA23 VCC _67 VCC _SM_66 AJ 18 AC 18 VCC _N CTF64 VC CAUX_N CTF 45 AF15 D 37 VSS_64 VSS_161 C 27 A15 VSS_244 VSS_337 AH 3
Y 23
P23
VCC _68
VCC _69
VCC _70
VCC VCC _SM_67
VCC _SM_68
VCC _SM_69
AJ 17
AH 17
AB18
AA18
VCC _N CTF65
VCC _N CTF66
VCC _N CTF67
VC CAUX_N CTF 46
VC CAUX_N CTF 47
VC CAUX_N CTF 48
AE15
AD 15
AY 36
AW 36
VSS_65
VSS_66
VSS_67
VSS_162
VSS_163
VSS_164
B27
AN26
BA14
AT14
VSS_245
VSS_246
VSS_247
VSS_338
VSS_339
VSS_340
AG3
AF3
N 23 AJ 16 Y 18 AC 15 AN 36 M26 AK14 AD 3
M23 VCC _71 VCC _SM_70 AH 16 W 18 VCC _N CTF68 VC CAUX_N CTF 49 AB15 AH 36 VSS_68 VSS_165 K26 AD 14 VSS_248 VSS_341 AC 3
L23 VCC _72 VCC _SM_71 BA15 V18 VCC _N CTF69 VC CAUX_N CTF 50 AA15 AG36 VSS_69 VSS_166 F 26 AA14 VSS_249 VSS_342 AA3
AC 22 VCC _73 VCC _SM_72 AY 15 U 18 VCC _N CTF70 VC CAUX_N CTF 51 Y15 AF 36 VSS_70 VSS_167 D 26 U 14 VSS_250 VSS_343 G3
AB22 VCC _74 VCC _SM_73 AW 15 C 396 T18 VCC _N CTF71 VC CAUX_N CTF 52 W15 AE36 VSS_71 VSS_168 AK25 K14 VSS_251 VSS_344 AT2
Y 22 VCC _75 VCC _SM_74 AV15 1.05VS VCC _N CTF72 VC CAUX_N CTF 53 V15 AC 36 VSS_72 VSS_169 P25 H 14 VSS_252 VSS_345 AR 2
W 22 VCC _76 VCC _SM_75 AU 15 . 47U VC CAUX_N CTF 54 U15 C 36 VSS_73 VSS_170 K25 E14 VSS_253 VSS_346 AP2
P22 VCC _77 VCC _SM_76 AT15 VC CAUX_N CTF 55 T15 B36 VSS_74 VSS_171 H 25 AV13 VSS_254 VSS_347 AK2
VCC _78 VCC _SM_77 near pin BA15 VC CAUX_N CTF 56 VSS_75 VSS_172 VSS_255 VSS_348
N 22 AR 15 R15 BA35 E25 AR 13 AJ2
M22 VCC _79 VCC _SM_78 AJ 15 VC CAUX_N CTF 57 AV35 VSS_76 VSS_173 D 25 AN 13 VSS_256 VSS_349 AD 2
L22 VCC _80 VCC _SM_79 AJ 14 AR 35 VSS_77 VSS_174 A25 AM13 VSS_257 VSS_350 AB2
VCC _81 VCC _SM_80 CALIS TOGA VSS_78 VSS_175 VSS_258 VSS_351
AC 21 AJ 13 AH 35 BA24 AL13 Y2
AA21 VCC _82 VCC _SM_81 AH 13 AB35 VSS_79 VSS_176 AU24 AG13 VSS_259 VSS_352 U2
VCC _83 VCC _SM_82 +1. 5VS_AUX VSS_80 VSS_177 VSS_260 VSS_353
W 21 AK12 AA35 AL24 P13 T2
N 21 VCC _84 VCC _SM_83 AJ 12 Y 35 VSS_81 VSS_178 AW 23 F 13 VSS_261 VSS_354 N2
M21 VCC _85 VCC _SM_84 AH 12 W 35 VSS_82 VSS_179 D 13 VSS_262 VSS_355 J2
L21 VCC _86 VCC _SM_85 AG12 V35 VSS_83 B13 VSS_263 VSS_356 H2
AC 20 VCC _87 VCC _SM_86 AK11 T35 VSS_84 AY 12 VSS_264 VSS_357 F2
AB20 VCC _88 VCC _SM_87 BA8 R 35 VSS_85 AC 12 VSS_265 VSS_358 C2
Y 20 VCC _89 VCC _SM_88 AY 8 P35 VSS_86 K12 VSS_266 VSS_359 AL1
W 20 VCC _90 VCC _SM_89 AW 8 N 35 VSS_87 H 12 VSS_267 VSS_360
P20 VCC _91 VCC _SM_90 AV8 M35 VSS_88 E12 VSS_268
N 20 VCC _92 VCC _SM_91 AT8 L35 VSS_89 AD 11 VSS_269
M20 VCC _93 VCC _SM_92 AR 8 J 35 VSS_90 AA11 VSS_270
L20 VCC _94 VCC _SM_93 AP8 H 35 VSS_91 Y 11 VSS_271
AB19 VCC _95 VCC _SM_94 BA6 G35 VSS_92 VSS_272
AA19 VCC _96 VCC _SM_95 AY 6 F 35 VSS_93
VCC _97 VCC _SM_96 VSS_94 CALIS TOGA
Y 19 AW 6 D 35
N 19 VCC _98 VCC _SM_97 AV6 AN 34 VSS_95
M19 VCC _99 VCC _SM_98 AT6 VSS_96
L19 VCC _100 VCC _SM_99 AR 6
N 18 VCC _101 VC C_SM_100 AP6 C ALI STOGA
M18 VCC _102 VC C_SM_101 AN 6 1.0 5VS
L18 VCC _103 VC C_SM_102 AL6
P17 VCC _104 VC C_SM_103 AK6
N 17 VCC _105 VC C_SM_104 AJ 6
M17 VCC _106 VC C_SM_105 AV1 C226 C126 C 127 C1 28 C 129 C 144 C143
N 16 VCC _107 VC C_SM_106 AJ 1 +
M16 VCC _108 VC C_SM_107 C369 C 44 220u/4V_V 10U/10V_08 10U /10V_08 1U _X7R . 22U .22U .22U
L16 VCC _109 +1. 5VS_AUX [6]
VCC _110 .47U . 47U 1.05VS [2,3, 4,5 ,6,11,13,22]
1.8V [5,9, 23]
C ALI STOGA

CALISTOGA 4/4 B - 9
 Schematic Diagrams

DDR2 SO-DIMM

1.8V SD Q_A[ 0.. 63] 1.8V S D Q_B[0..6 3]

[7] SDQ_A[0 ..63] [ 7] SD Q _B[ 0.. 63]

112
111

118

103

104

183

121

196
193

162
150

161
149

111
117

103

104

133
183

184

121
122
196
193

162
150
138

149
117

133

184

122

138

112

118

161
96
95

87

77

78
71

40
28

81
82

47

48
81
82

88

47

12
48

72

96
95

87

88

77
12

78
71
72

40
28
8

8
JD IM2 J DI M1
SMAA_A[0..13] SMAA_B[0..13]

VSS
VS S
VS S
VS S
VSS
VSS
VSS
VS S
VS S

VSS
VSS
VS S
VS S
VS S
VSS
VSS
VS S
VS S
VS S
VSS
VSS

VS S
VS S
VSS
VSS
VSS
VS S
VS S
VSS
VSS
VSS
VS S
VS S
VS S
VSS
VSS
VS S
VS S
VS S
VSS
VSS
VSS
VS S
VD D
VSS
VDD
VDD
VDD
VD D
VD D
VD D
VDD
VDD
VD D
VD D
VD D
VDD

VDD
VD D
VD D

VDD
VDD
VD D
VD D
VD D
VDD
VDD
VD D
[7, 10] SMAA_A[0..1 3] [ 7,1 0] SMAA_B[0. .13]
SMAA _A 0 102 5 SD Q_A0 SMAA _B0 102 5 S DQ _B0
SMAA _A 1 101 A0 D Q0 7 SD Q_A1 SMAA _B1 101 A0 DQ0 7 S DQ _B1
SMAA _A 2 100 A1 D Q1 17 SD Q_A2 SMAA _B2 100 A1 DQ1 17 S DQ _B2
SMAA _A 3 99 A2 D Q2 19 SD Q_A3 SMAA _B3 99 A2 DQ2 19 S DQ _B3
SMAA _A 4 98 A3 D Q3 4 SD Q_A4 SMAA _B4 98 A3 DQ3 4 S DQ _B4
SMAA _A 5 97 A4 D Q4 6 SD Q_A5 SMAA _B5 97 A4 DQ4 6 S DQ _B5
SMAA _A 6 94 A5 D Q5 14 SD Q_A6 SMAA _B6 94 A5 DQ5 14 S DQ _B6
SMAA _A 7 92 A6 D Q6 16 SD Q_A7 SMAA _B7 92 A6 DQ6 16 S DQ _B7
SMAA _A 8 93 A7 D Q7 SD Q_A8 SMAA _B8 A7 DQ7 S DQ _B8
23 93 23
SMAA _A 9 91 A8 D Q8 25 SD Q_A9 SMAA _B9 91 A8 DQ8 25 S DQ _B9
SMAA _A 10 105 A9 D Q9 35 SD Q_A10 SMAA _B1 0 105 A9 DQ9 35 S DQ _B10
SMAA _A 11 90 A10/AP DQ10 37 SD Q_A11 SMAA _B1 1 90 A10/AP D Q 10 37 S DQ _B11
SMAA _A 12 89 A11 DQ11 20 SD Q_A12 SMAA _B1 2 89 A11 D Q 11 20 S DQ _B12
SMAA _A 13 116 A12 DQ12 SD Q_A13 SMAA _B1 3 A12 D Q 12 S DQ _B13
22 116 22
86 A13 DQ13 36 SD Q_A14 86 A13 D Q 13 36 S DQ _B14
A14 DQ14 A14 D Q 14
B.Schematic Diagrams

84 38 SD Q_A15 84 38 S DQ _B15
SBA_A2 85 A15 DQ15 43 SD Q_A16 S BA _B 2 85 A15 D Q 15 43 S DQ _B16
[7,10] SB A_A2 SBA_A0 A16/BA2 DQ16 SD Q_A17 [7,1 0] SBA _B 2 S BA _B 0 A16/BA2 D Q 16 S DQ _B17
[7,10] SB A_A0 107 45 [7,1 0] SBA _B 0 107 45
SBA_A1 BA0 DQ17 SD Q_A18 S BA _B 1 BA0 D Q 17 S DQ _B18
[7,10] SB A_A1 106 55 [7,1 0] SBA _B 1 106 55
SDM_A[0. .7] BA1 DQ18 57 SD Q_A19 SD M_B[ 0..7] BA1 D Q 18 57 S DQ _B19
[7] SD M_A[ 0.. 7] DQ19 SD Q_A20 [7] SD M_B[0..7 ] D Q 19 S DQ _B20
44 44
SD M_ A0 10 DQ20 46 SD Q_A21 SD M_ B0 10 D Q 20 46 S DQ _B21
SD M_ A1 26 DM0 DQ21 56 SD Q_A22 SD M_ B1 26 D M0 D Q 21 56 S DQ _B22
SD M_ A2 52 DM1 DQ22 58 SD Q_A23 SD M_ B2 52 D M1 D Q 22 58 S DQ _B23
DM2 DQ23 D M2 D Q 23

Sheet 9 of 29
SD M_ A3 67 61 SD Q_A24 SD M_ B3 67 61 S DQ _B24
SD M_ A4 130 DM3 DQ24 63 SD Q_A25 SD M_ B4 130 D M3 D Q 24 63 S DQ _B25
SD M_ A5 147 DM4 DQ25 73 SD Q_A26 SD M_ B5 147 D M4 D Q 25 73 S DQ _B26
SD M_ A6 170 DM5 DQ26 75 SD Q_A27 SD M_ B6 170 D M5 D Q 26 75 S DQ _B27
SDQS_A[0..7] DM6 DQ27 SD QS_B[0. .7] SD M_ B7 D M6 D Q 27

DDR2 SO-DIMM [7] SD QS_A[ 0.. 7]

SD M_ A7

SD Q S_A0
SD Q S_A1
185

13
31
DM7

DQS0
DQ28
DQ29
DQ30
62
64
74
76
SD Q_A28
SD Q_A29
SD Q_A30
SD Q_A31
[7] SDQS_B[0..7 ]
SD QS _B 0
SD QS _B 1
185

13
31
D M7

D QS0
D Q 28
D Q 29
D Q 30
62
64
74
76
S DQ _B28
S DQ _B29
S DQ _B30
S DQ _B31
SD Q S_A2 51 DQS1 DQ31 12 3 SD Q_A32 SD QS _B 2 51 D QS1 D Q 31 1 23 S DQ _B32
SD Q S_A3 70 DQS2 DQ32 12 5 SD Q_A33 SD QS _B 3 70 D QS2 D Q 32 1 25 S DQ _B33
SD Q S_A4 131 DQS3 DQ33 13 5 SD Q_A34 SD QS _B 4 131 D QS3 D Q 33 1 35 S DQ _B34
SD Q S_A5 148 DQS4 DQ34 13 7 SD Q_A35 SD QS _B 5 148 D QS4 D Q 34 1 37 S DQ _B35
SD Q S_A6 169 DQS5 DQ35 12 4 SD Q_A36 SD QS _B 6 169 D QS5 D Q 35 1 24 S DQ _B36
SD Q S_A7 188 DQS6 DQ36 12 6 SD Q_A37 SD QS _B 7 188 D QS6 D Q 36 1 26 S DQ _B37
DQS7 DQ37 13 4 SD Q_A38 D QS7 D Q 37 1 34 S DQ _B38
DQ38 13 6 SD Q_A39 D Q 38 1 36 S DQ _B39
SRAS_A# 108 DQ39 14 1 SD Q_A40 SRAS_B# 108 D Q 39 1 41 S DQ _B40
[7,10] SR AS_A # SWE_A# 109 RAS# DQ40 14 3 SD Q_A41 [7,10] S RA S_ B# SW E_B# 109 R AS# D Q 40 1 43 S DQ _B41
[7,10] SWE_A# WE# DQ41 [7,10] SW E_ B# WE# D Q 41
SCAS_A# 113 15 1 SD Q_A42 SCAS_B# 113 1 51 S DQ _B42
[7,10] SC AS_A # CAS# DQ42 SD Q_A43 [7,10] S CA S_ B# C AS# D Q 42 S DQ _B43
15 3 1 53
SCS_A0# 110 DQ43 14 0 SD Q_A44 SCS_B0# 110 D Q 43 1 40 S DQ _B44
[5,10] SCS _A 0# SCS_A1# 115 S0# DQ44 14 2 SD Q_A45 [5,10] SCS _B 0# SCS_B1# 115 S0# D Q 44 1 42 S DQ _B45
[5,10] SCS _A 1# S1# DQ45 15 2 SD Q_A46 [5,10] SCS _B 1# S1# D Q 45 1 52 S DQ _B46
SCKE_A0 79 DQ46 15 4 SD Q_A47 SCKE_B0 79 D Q 46 1 54 S DQ _B47
[5,10] SC KE_A 0 SCKE_A1 CKE0 DQ47 SD Q_A48 [5,10] S CK E_ B0 SCKE_B1 C KE0 D Q 47 S DQ _B48
[5,10] SC KE_A 1 80 15 7 [5,10] S CK E_ B1 80 1 57
CKE1 DQ48 SD Q_A49 C KE1 D Q 48 S DQ _B49
15 9 1 59
DQ49 17 3 SD Q_A50 D Q 49 1 73 S DQ _B50
DQ50 17 5 SD Q_A51 D Q 50 1 75 S DQ _B51
D DR CLK_A0 30 DQ51 15 8 SD Q_A52 D DR C LK_B1 30 D Q 51 1 58 S DQ _B52
[5] DD R CLK_A 0 D DR CLK_A0 # CK0 DQ52 SD Q_A53 [5] D DR CL K_ B1 D DR C LK_B1# C K0 D Q 52 S DQ _B53
[5] D D RC LK _A 0# 32 16 0 [5] DD RC LK _B 1# 32 1 60
D DR CLK_A1 CK0# DQ53 SD Q_A54 D DR C LK_B0 C K0# D Q 53 S DQ _B54
[5] DD R CLK_A 1 164 17 4 [5] D DR CL K_ B0 164 1 74
D DR CLK_A1 # 166 CK1 DQ54 17 6 SD Q_A55 D DR C LK_B0# 166 C K1 D Q 54 1 76 S DQ _B55
[5] D D RC LK _A 1# CK1# DQ55 SD Q_A56 [5] DD RC LK _B 0# C K1# D Q 55 S DQ _B56
17 9 1 79
SOD T_A0 114 DQ56 18 1 SD Q_A57 SOD T_B0 114 D Q 56 1 81 S DQ _B57
[5,10] SOD T_A 0 SOD T_A1 OD T0 DQ57 SD Q_A58 [5,10] S OD T_ B0 SOD T_B1 ODT0 D Q 57 S DQ _B58
[5,10] SOD T_A 1 119 18 9 [5,10] S OD T_ B1 119 1 89
OD T1 DQ58 SD Q_A59 ODT1 D Q 58 S DQ _B59
19 1 1 91
SMB_IC HD ATA 195 DQ59 18 0 SD Q_A60 SMB_I CH DA TA 195 D Q 59 1 80 S DQ _B60
[ 4,1 2,1 6] SMB_IC HD ATA SMB_IC HC LK SD A DQ60 SD Q_A61 [4, 12, 16] SMB_IC H DA TA SMB_I CH CL K SDA D Q 60 S DQ _B61
197 18 2 197 1 82
[4 ,12 ,16] SMB_I CH CLK SDQS_A#[0.. 7] SC L DQ61 19 2 SD Q_A62 [4 ,12 ,16] SMB_ ICH C LK SDQS _B#[0. .7] SCL D Q 61 1 92 S DQ _B62
[7] SD QS_A#[0 ..7] DQ62 SD Q_A63 [7] SDQS_B# [0. .7] D Q 62 S DQ _B63
19 4 1 94
SD QS _A #0 11 DQ63 S DQ S_ B# 0 11 D Q 63
SD QS _A #1 29 DQS#0 S DQ S_ B# 1 29 D QS#0
SD QS _A #2 49 DQS#1 83 S DQ S_ B# 2 49 D QS#1 83
SD QS _A #3 68 DQS#2 N C1 12 0 S DQ S_ B# 3 68 D QS#2 NC 1 1 20
SD QS _A #4129 DQS#3 N C2 50 R 138 0_0 4 S DQ S_ B# 4129 D QS#3 NC 2 5 0 R 139 0_0 4
SD QS _A #5146 DQS#4 N C3 PM_EXTTS1 # [5] S DQ S_ B# 5146 D QS#4 NC 3 P M_EXTTS0# [ 5]
69 69
SD QS _A #6167 DQS#5 N C4 16 3 S DQ S_ B# 6167 D QS#5 NC 4 1 63
SD QS _A #7186 DQS#6 NC TEST S DQ S_ B# 7186 D QS#6 N C TEST
DQS#7 D QS#7
Trace Width 12 Mil Trace Width 12 Mil
D IMM_V R EFA 1 DI MM_V RE FB 1
Space 20 Mil VR EF 19 8 R43 10 K_04 Space 20 Mil VREF 1 98 R 264 10K _04
199 SA0 20 0 R42 10 K_04 199 SA0 2 00 R 263 10K _04
3VS VD DSPD SA1 3VS VDD SPD SA1 3VS
VS S
VSS
VSS
VSS
VS S
VS S

VSS
VSS
VS S
VS S
VS S
VSS
VSS
VS S
VS S
VS S
VSS
VSS
VSS
VS S
VS S

VSS
VSS
VS S
VS S
VS S
VSS
VSS
VS S
VS S
VS S
VSS
VSS

VSS
VSS
VS S
VS S
VSS
VSS
VSS
VS S
VS S

VSS
VSS
VS S
VS S
VS S
VSS
VSS
VSS
VS S
VS S
VSS
VSS
VSS
VS S
VS S
VS S
VSS
VSS
VS S
VS S
VS S
VSS
VSS
VSS
VS S
VSS

VSS

VSS
C 51 C 50 C 53 C5 2

. 1U _04 1 0U /10 V_08 .1U_04 10 U/ 10V _08

18

42
54

66
1 27
139
128
145

1 71
1 72
177
187

1 90
9

34
1 32
144
156
168
2
3
15

41
53

65
60

127

1 28
1 45
1 65
171
172

1 87
1 78
190
9

33
1 55

132

1 56
1 68
2
3

39
24
41
53

59
65
60

165

178

21
33
155

27
39

18
24

42
54
59

66

139

177

21

34

144

15
27
1. 8V NEAR DIMM PIN 1.8V NEAR DIMM PIN

R149 D DR 2 S O- DIMM1 R 151 D D R2 SO -D IMM2

addr =1 010 00 0b a ddr =1 01 00 10 b
1.8 V
1.8V 1 .8V [5,8, 23]
3 VS [2,4, 5,6,10,11,12 ,13 ,14,15,16,18,20,21,24]
75 _1%_04 75_1% _04
D IMM_ VR EF A DIMM_ VR EF B

R 143 C 40 6 C4 18 C 435 C4 29 C 180 C184 C 201 C14 7 C 109 C 181 C93 C 13 1 C178 C 108 R 144
C 230 C2 27 C2 28 C 231 C 43 8 C439 C 165 C1 60 C 179 C 163 C164 C 18 5 C2 00 C 199 C159 C 198 C186 C 197
. 1U _X7 R_ 04 . 1U _X7R_ 04 .1 U_ X7R_04 .1U_X7 R_0 4 10 U/ 10V_08 10 U/10V _08 10U/10V_08
1U_06 .1U _X7R _04 .1U_X7R _04 .1U _X7R _04 .1U _X7R _04 .1U _X7R _04 10U /10V_08 1 0U /10V_08 220U (D )(R ) 1U _06 .1 U_X7R _04 . 1U_ X7 R_04 .1U_X7R_ 04 .1 U_ X7R _04 .1U_ X7R _0 4 10 U/1 0V_08 10U /1 0V _08 10U /10V_08
75 _1%_04 75_1% _04 .1U _X7R _04 .1U _X7R _04 . 1U _X7R_04 . 1U _X7 R_ 04 10U /10V_08 1 0U/ 10V_0 8 220U (D )(R )

hexainf@hotmail.com
B - 10 DDR2 SO-DIMM
 Schematic Diagrams

LVDS & CRT & TV OUT

0.9VS

[7,9] SBA_A1
SMAA_A4
SMAA_A2
SMAA_A0
SBA_A1
8
7
6
5
1 R N4
2
3
4
C13 2

C40 5
.1U_X7R_04

.1U_X7R_04
[19 ] BRIGHTN ES S
R 93 1 20K_04

R297

2. 2M_04(R )
BRIGHTN ESS_IN V

C4 13

.1U _04 3VS

LVDS/SPEAKER
8P4R_56_04
SW E_A# 8 1 R N19 C41 4 .1U_X7R_04
INVERTER/SPEAKER CONNECTOR
[7,9] SW E_A# SC AS_A# 7 2
[7,9] S CAS_A# SC S_A1# 6 3 C42 8 .1U_X7R_04 R25 VIN
[5,9] SCS_A1# SODT_A1 5 4
[5,9] S OD T_A1

DDR2 Termination
8P4R_56_04 2.2K_04
SR AS_A# 8 1 R N2 C43 2 .1U_X7R_04
[7,9] S RAS_A# SC S_A0# +
7 2 C 338 C3 37
[5,9] SCS_A0# SMAA_A13 6 3 C41 6 .1U_X7R_04 C A
SODT_A0 [6] BLON
5 4 D6 SC S7 51 10U /25V_12 .1U_04(R ) JIN V1
[5,9] S OD T_A0 8P4R_56_04 R17 100K_04
SBA_A2 8 1 R N26 C42 6 .1U_X7R_04 5/16 JI NV1
[7,9] SBA_A2 SMAA_A12 BKL_EN PAN EL_EN 1
7 2 C A
SMAA_A9 6 3 C40 7 .1U_X7R_04 [19] BKL_EN D5 SC S7 51 PANEL_EN 2
SMAA_A8 5 4 LID _SW# C A BR IGH TNESS_INV 3 10 1
8P4R_56_04 [19,20 ] LID_SW # D7 SC S7 51 4
SMAA_A3 8 1 R N21 C41 9 .1U_X7R_04 PM_PW ROK C A 5
SMAA_A1 [21 ] PM_PWR OK L_OU T+_C 6
7 2 D8 SC S7 51
SMAA_A10 6 3 C42 0 .1U_X7R_04 SW BKON C A [18] L_OUT+_C L_OU T-_C 7
SBA_A0 [12] SWBKON [18] L_OUT-_C R _OUT+_C 8
5 4 D9 SC S7 51

B.Schematic Diagrams
[7,9] SBA_A0 8P4R_56_04 [18] R_OUT+_C R _OUT- _C 9
[18] R_OUT-_C 10
8 1 R N7 C43 0 .1U_X7R_04 R19
SMAA_A6 7 2 87212-1000 1
SMAA_A7 6 3 C43 6 .1U_X7R_04 1M

[5,9] S CKE_A0
SMAA_A11

SC KE_A0 R3 07
5 4
8P4R_56_04
5 6_04 C43 7 .1U_X7R_04 V DD3
Sheet 10 of 29
SC KE_A1 R1 25 5 6_04

LVDS & CRT & TV

[5,9] S CKE_A1 SMAA_A5 R3 03 5 6_04 S YS15V
R1 36
SMAA _A[ 0..13]
[7,9 ] SMAA_A[ 0..1 3] 0.9VS
LC DV DD L28 FCM201 2V-121

SMAA_B5
SMAA_B3
8
7
1 R N5
2
C13 9 .1U_X7R_04
VDD 3

R 140 R 142
0_ 04
6
5
Q12
NTG S41 41N
LCD VDD
C 458

. 1U_ 04
C 456

1 0U/ 10V_08 J LC D1
OUT
SMAA_B1 6 3 C18 3 .1U_X7R_04 C 211 C216 2 4
SMAA_B10 5 4 1 1 JLCD1
8P4R_56_04 4.7U_08 .1U_04 R 141 C22 5 C 221 2
SW E_B# 8 1 R N3 C16 1 .1U_X7R_04 10K_04 100K_04 3 20
[7, 9] SWE_B#

3
SC AS_B# LCD ID0 4
[7, 9] SC AS_B# 7 2 [ 12] LCDI D0 R1 63 100_0 4
SC S_B1# 6 3 C18 2 .1U_X7R_04 LCD ID1 R1 62 100_0 4 5

D
[5, 9] SCS_B1# SODT_B1 5 4 Q14 C222 95.3_06 4.7 U_08 [ 12] LCDI D1 LCD ID2 R3 34 100_0 4 6
[5, 9] SODT_B1 8P4R_56_04 .1U _04 [ 12] LCDI D2 C LV DS- L0N 7 1
SMAA_B13 8 1 R N18 C16 2 .1U_X7R_04 G 5/18 C LV DS- L0P 8
SODT_B0 9
[5, 9] SODT_B0 7 2 .1U _04

S
SC S_B0# 6 3 C18 7 .1U_X7R_04 2N7002W Q15 C LV DS- L1N 10

D
[5, 9] SCS_B0# SR AS_B# 5 4 C LV DS- L1P 11
[7, 9] SR AS_B#

D
8P4R_56_04 Q13 12
SBA_B2 8 1 R N6 C20 2 .1U_X7R_04 G C LV DS- L2N 13
[7, 9] SBA_B2 14
SMAA_B12 7 2 EN AVD D G 2N 7002W C LV DS- L2P
[6] EN AVDD

S
SMAA_B9 6 3 C41 5 .1U_X7R_04 2N7002W 15

S
SMAA_B8 5 4 C LV DS- LCLKN 16
8P4R_56_04 C LV DS- LCLKP 17 26
18 25
SBA_B1 8 1 R N20 C42 7 .1U_X7R_04 19 22
[7, 9] SBA_B1 SMAA_B0 7 2 20 21
SMAA_B2 6 3 C43 4 .1U_X7R_04 L27 0 CL VD S-L0N
[6] LVD S-L 0N CL VD S-L0P
5 4 [6] LVD S-L 0P L26 0 LCD _CON
8P4R_56_04 L25 0 CL VD S-L1N LVC-D20SFY G
SMAA_B4 [6] LVD S-L 1N CL VD S-L1P
8 1 R N22 C43 3 .1U_X7R_04 [6] LVD S-L 1P L24 0
SMAA_B6 7 2 L23 0 CL VD S-L2N
SMAA_B7 6 3 C40 4 .1U_X7R_04 [6] LVD S-L 2N L22 0 CL VD S-L2P
SMAA_B11 [6] LVD S-L 2P CL VD S-LC LKN
5 4 [6] LVD S-LCLKN L21 0
8P4R_56_04 L20 0 CL VD S-LC LKP 3VS
SC KE_B0 R1 26 5 6_04 C41 7 .1U_X7R_04 [6] LV DS- LCL KP C22 4 C2 20 C21 8 C2 14
[5, 9] SC KE_B0 SC KE_B1 R3 04 LCD ID0 R1 61
5 6_04 C223 C 219 C215 C 213 4. 7K_ 04
[5, 9] SC KE_B1 SBA_B0 R1 11 5 6_04 LCD ID1 R1 60 4. 7K_ 04
[7, 9] SBA_B0 LCD ID2 R1 59
10P_04 10P_04 10P _04 10 P_04 4. 7K_ 04
SMAA_B[0..13 ] 10P _04 10P_04 10P_04 10P_04
[7 ,9] SMAA_B[0. .13]

BAV99
D4
2.5VS
BAV99 BAV99
D22
2.5 VS
D3
2.5VS
HS
VS
MID3
L4
L38
L6
5/16

FCM1005KF -121T01
FCM1005KF -121T01
FCM1005KF -121T01
H SY NC
VSY NC
D DC LK +3.3V CVS 3 VS 3VS 5
U10
1
5VS

A
5/16
D 39
C
CRT PORT 3VS 2.5VS
C

C
A

DD CD ATA MID 1 VP NC
L3 FCM1005KF -121T01 D1 S CS7 51 R13
C A 1K_1 % 2 R248 R12 R24 7
R9 VN SCS751
J VGA1 U SB5- 4 3 U SB5+

G
V GA DSUB
AC

AC

C H2 CH1
AC

4.7K _04 2 .2K_04

R L37 F CM1005KF -121 T01 F RED 1 CM1213-02ST(R) 4.7K_04 2.2K_04
[ 6] R G L1 F CM1005KF -121 T01 F GRN 9 D DCD ATA D S
[ 6] G B L2 F CM1005KF -121 T01 F BLU 2 Q29 2N7002W VGAD DCD ATA [ 6]
[ 6] B D DCL K
10 D S VGAD DCC LK [6]
5 /16 3 Q5 2N7002W
11 R2 40 0
R239 R1 R2 4 MID1 U SB5+ [1 1]

G
C2 12 HS 3VS
C325 C1 C3 C 326 C4 5 VS
13 MID3 3 VS

G
150_1%_04 1 50_1%_04 2 2P_ 04 5/16 22P_ 04 22P_04 22P_ 04 6 Q4 2N7002W
15 0_1%_04 22 P_0 4 22P_0 4 14
7 H SY N C D S H SY
HSY [6]
15 VSYN C D S VSY
SY S15V
0.9 VS
[24]
[23]
PLEASE CLOSE TO CONNECTOR 8 C6
VSY [6]
C327 C3 31 C7 Q30 2N7002W
2.5 VS [6,22]
R2 41 0
GND 1

G
3VS [2,4,5,6,9,11,12,13,14, 15,16,1 8,20,21, 24] [11] USB 5-
GN D2

VD D3 [2,11,1 4,19 ,20, 23,2 4,25] 220 P 1000P_0 4

5VS [13,14, 16,1 8,19,20,22, 24] 1000P_04 22 0P
3 VS
VIN [20,21, 22,2 3,24,25]

LVDS & CRT & TV OUT B - 11

 Schematic Diagrams

ICH7-M 1/3
U 22A
[14,19,20] LPC_AD [0..3]
LPC_AD 0 AA6 AE22 H_A20GATE R 376 10K_04 U 22D
LPC_AD 1 AB5 LAD 0 A20GATE H_A20M# 3VS D MI_RXN0
AH 28 F 26 V26
LAD 1 A20M# H _A20M# [2] [16] PC IE_R XN 1_W LAN PERn1 D MI0RXN D MI _R XN 0 [ 5]

LPC
LPC_AD 2AC 4 F 25 V25 D MI_RXP0
LAD 2 [16] PC IE_R XP1_W LAN PERp1 D MI 0RXP D MI _R XP0 [ 5]

Direct Media Interface

LPC_AD 3 Y 6 C558 .1U _04 E28 U 28 D MI_TXN0
LAD 3 [16] PC IE_TXN1_W LAN PETn1 D MI 0TXN D MI _TXN0 [ 5]
AG 27 R210 0_04( R) C559 .1U _04 E27 U 27 D MI_TXP0
CPUSLP# H_CPUSLP# [2,5] [16] PC IE_TXP1_W LAN PETp1 D MI 0TXP D MI _TXP0 [5]
LPC _F RAME# AB3 H 26 Y 26 D MI_RXN1
[14,19,20] LPC_FR AME# LPC _D RQ# LFR AME# 5 /1 6 [ 17] PCIE_R XN 2_GLAN PERn2 D MI1RXN D MI_RXP1 D MI _R XN 1 [ 5]
AC 3 H 25 Y 25
[20] LPC_DR Q# AA5 LDR Q0# AF 24 R389 0_04 [ 17] PCIE_R XP2_GLAN C556 .1U _04 G28 PERp2 D MI 1RXP W 28 D MI_TXN1 D MI _R XP1 [ 5]
LDR Q1#/ GPIO23 ( +3. 3VS) TP1/ DPRSTP# H_DPRSTP# [2,21] [ 17] PCIE_TXN 2_G LAN PETn2 D MI 1TXN D MI _TXN1 [ 5]
AH 25 R393 0_04 C557 .1U _04 G27 W 27 D MI_TXP1
TP2/D PSLP# H_DPSLP# [2] [ 17] PCIE_TXP2_GLAN PETp2 D MI 1TXP D MI _TXP1 [5]
W1
EE_CS

PCI-Express
Y1 R212 56_04 K26 AB26 D MI_RXN2

CPU
EE_SH CLK 1.05VS PERn3 D MI2RXN D MI_RXP2 D MI _R XN 2 [ 5]
Y2 AG 26 R211 56_04 K25 AB25
W3 EE_DOUT FER R # H_FERR # [2] J 28 PERp3 D MI 2RXP AA28 D MI_TXN2 D MI _R XP2 [ 5]
EE_DI N PETn3 D MI 2TXN D MI _TXN2 [ 5]
J 27 AA27 D MI_TXP2
PETp3 D MI 2TXP D MI _TXP2 [5]
V3
LAN _C LK

LAN
AG 24 CPUPW RGD M26 AD25 D MI_RXN3
GPIO49/ CPUPWR GD C PU PW RGD [2] PERn4 D MI3RXN D MI_RXP3 D MI _R XN 3 [ 5]
U3 M25 AD24
LAN _R STSY NC L28 PERp4 D MI 3RXP AC28 D MI_TXN3 D MI _R XP3 [ 5]
H_IGNN E# PETn4 D MI 3TXN D MI_TXP3 D MI _TXN3 [ 5]
U5 AG 22 H _IGNN E# [2] L27 AC27 D MI _TXP3 [5]
LAN _R XD 0 IGN NE# FW H _IN IT# PETp4 D MI 3TXP
V4 AG 21
T5 LAN _R XD 1 I NI T3_3V# FW H _IN IT# [ 14] P26 AE28 I CH 7PCIE_C LK#
LAN _R XD 2 PERn5 DMI_C LKN I CH 7PCIE_C LK# [4]
P25 AE27 I CH 7PCIE_C LK
H_IN IT# PERp5 DMI_C LKP I CH 7PCIE_C LK [4]
U7 AF 22 N 28
LAN _TXD 0 IN IT# H_IN TR H _IN IT# [2] PETn5
V6 AF 25 N 27 C 25
LAN _TXD 1 IN TR H _IN TR [2] PETp5 D MI_ZC OMP
V7 D 25 DMI_I RC OMP
LAN _TXD 2 AG 23 H_RC IN # R388 10K_04 T25 DMI_I RC OMP R201 24.9_1%_04 1.5VS
B.Schematic Diagrams

RC IN # 3VS PERn6 USB0-

R339 39.2_1%_04 U1 T24 F1 Place within
[18,20] AC _BITC LK ACZ _BIT_CLK H_NMI PERp6 U SBP0N USB0+ U SB0- [16]
AH 24 R 28 F2 500 mils of ICH
NMI H _NMI [2] PETn6 U SBP0P U SB0+ [16]

AC-97/AZALIA
R171 39.2_1%_04 R6 AF 23 H_SMI# R 27 G4 USB1-
[ 18, 20] AC_SY NC ACZ _SYN C SMI # H _SMI# [2] PETp6 U SBP1N U SB1- [16]
G3 USB1+
H_STPC LK# SPI_SCLK R2 U SBP1P USB2- U SB1+ [16]
R166 39.2_1%_04 R5 AH 22 H1
[18,20] AC _RST# ACZ _R ST# STPC LK# H _STPC LK# [2] R169 10K_04(R ) SPI_C E# P6 SPI_C LK U SBP2N H2 USB2+ U SB2- [20]
3V SPI_C S# U SBP2P USB3- U SB2+ [20]
[18,20] AC _SDOUT R167 39.2_1%_04 T4 AF 26 R209 56_04 PM_TH R MTR IP# [2, 5] P1 J4 U SB3- [20]
ACZ _SDOUT THERMTR IP# SPI_ARB U SBP3N

SPI
AC_SD IN0 T2 J3 USB3+
[ 18] AC _SDI N0 ACZ _SDI N0 1.05VS U SBP3P U SB3+ [20]
AC_SD IN 1 T3 R208 75_1%_04 SPI_SI P5 K1 USB4-

Sheet 11 of 29 [ 20] AC _SDI N1 ACZ _SDI N1 3V

3V
R170 10K_04(R ) SPI_SO P2 SPI_MOSI
SPI_MISO
U SBP4N
U SBP4P
K2 USB4+
USB5-
U SB4-
U SB4+
[20]
[20]

USB
T1 R154 10K_04(R ) L4
ACZ _SDI N2 ID E_PDA0 OC 0# U SBP5N USB5+ U SB5- [10]
AH 17 IDE_PDA0 [14] [16] O C0# D3 L5 U SB5+ [10]
SATA_LED # AF 18 DA0 AE17 ID E_PDA1 OC 1# C4 OC 0# U SBP5P M1 USB6-

ICH7-M 1/3 [ 14]

[ 14]
[ 14]
SATA_LED#

SATA_R X0-
SATA_RX0+
C 479
C 476
3900P AF3
3900P AE3
SATALED #

SATA0RXN
DA1
DA2
AF 17

AD 16
ID E_PDA2

ID E_PDC S3#
IDE_PDA1 [14]
IDE_PDA2 [14]

IDE_PDC S3# [14]

3 /8
[16]
[16]
O C1#
O C2#
OC 2#
OC 3#
OC 4#
D5
D4
E5
OC 1#
OC 2#
OC 3#
U SBP6N
U SBP6P
U SBP7N
M2
N4
N3
USB6+
USB7-
USB7+
U SB6-
U SB6+
[16]
[16]

C 471 3900P AG2 SATA0RXP DC S3# AE16 ID E_PDC S1# OC 5# C3 OC 4# U SBP7P 5/16
[ 14] SATA_TX0- SATA0TXN DC S1# IDE_PDC S1# [14] OC 5#/ GPIO 29 (+3.3V)
C 472 3900P AH 2 OC 6# A2 D2 U SBRBIAS
[ 14] SATA_TX0+ SATA0TXP IDE_PDD [0. .15] [ 14] OC 6#/ GPIO 30 (+3.3V) U SBRBIAS#
B3 D1 R 341 22_1%_04
ID E_PDD 0 3V OC 7#/ GPIO 31 (+3.3V) USBR BIAS
AB15 R 165 10K_04
DD0

SATA
C 251 3900P( R) AF7 AE14 ID E_PDD 1 IC H 7-M Place within 500
C 252 3900P( R) AE7 SATA2RXN DD1 AG 13 ID E_PDD 2
C 485 3900P( R) AG6 SATA2RXP DD2 AF 13 ID E_PDD 3 mils of ICH
C 486 3900P( R) AH 6 SATA2TXN DD3 AD 14 ID E_PDD 4
SATA2TXP DD4 ID E_PDD 5
AC 13
DD5 AD 12 ID E_PDD 6
AF1 DD6 AC 12 ID E_PDD 7 3V
[ 4] SATACLK# SATA_CLKN DD7 ID E_PDD 8
AE1 AE12

IDE
[ 4] SATAC LK SATA_CLKP DD8 AF 12 ID E_PDD 9 RN 8
DD9 ID E_PDD 10 OC 6#
Within 500mil R 172 24.9_1%_04 AH 10 AB13 8 1
AG10 SATAR BI ASN D D10 AC 14 ID E_PDD 11 7 2 OC 5#
SATAR BI ASP D D11 AF 14 ID E_PDD 12 6 3 OC 3#
D D12 AH 13 ID E_PDD 13 5 4 OC 4#
D D13 ID E_PDD 14
C 247 2 1 10P_04 AB1 AH 14
R TXC1 D D14 AC 15 ID E_PDD 15 8P4R _10K_04
Y2
1
R168 D D15

RTC
AE15 IDE_PDD REQ
D DR EQ IDE_PDD REQ [14]
32.768KH z
2

10M
C 248 2 1 15P_04 AB2 AF 15 IDE_PDI OR #
R TC X2 DIOR # IDE_PDI OW # IDE_PDI OR # [14]
AH 15
5 /16 R TC _R ST# AA3 DIOW # AF 16 IDE_PDD AC K# IDE_PDI OW # [14]
VBAT R TC RST# D DACK# IDE_PDD AC K# [14]
R 164 1M Y5 AH 16 IDE_IR Q14
VBAT I NTRU DER# I DEIRQ IDE_IR Q14 [14]
I CH _IN TVRMEN W4 AG 16 IDE_PIORD Y
I NTVR MEN IOR DY IDE_PIORD Y [14]

R 155 IC H7-M

332K

I CH _IN TVRMEN

R 150

0_04(R )
H _A20GATE R375 0_04
H _RC IN # GA20 [19]
R387 0_04
KBC _R ST# [ 19] 3VS [2,4,5, 6,9,10,12,13,14,15,16,18,20,21,24]
3VS VBAT [13]
3V 1.05VS [2,3,4, 5,6,8, 13, 22]

RTC BATTERY VBAT 8

U7
VDD SI
5
2
R 145
R 147
47(R )
47(R )
SPI_SI
SPI_SO R 173 10K_04 ID E_IR Q14
1.5VS
3V
[3,6,13,16,24]
[12,13,14,16,17,20,21,22,23,24]

A C SO 1 SPI_C E#
J CBAT1 VDD 3 D 37 SC S751 C E# 6 R 146 47(R ) SPI_SCLK R 192 4.7K_04 ID E_PI OR DY
A C R 156 180K_1%_04 R TC_RST# R 335 3.3K(R ) 3 SCK
1 R336 1K_04 D 38 SC S751 W P# C234 C236 C 233 C 235
1

C 460 C 245
2 33P(R ) 33P(R ) 33P(R ) 33P(R)
85204-02001 JC BAT 1 1U_06 .1U _04 JOPEN1 R 148 3.3K(R ) 7 4
OPEN_10m il- 1MM(R ) H OLD# VSS
2
2

SPI(R )
1

hexainf@hotmail.com
B - 12 ICH7-M 1/3
 Schematic Diagrams

ICH7-M 2/3

PCI_AD [0:31]
[ 15] PCI_AD [0:31]
U 22B
PCI _AD 0 E18 D7 PC I_R EQ#0
PCI _AD 1 C18 AD 0 REQ0 # C 16 PC I_R EQ#1 U22C
PCI _AD 2 A16 AD 1 PCI REQ1 # C 17 PC I_R EQ#2 SMCL K C 22 AF19 SI/O DET#
PCI _AD 3 F18 AD 2 REQ2 # E1 3 PC I_R EQ#3 PCI _R EQ #2 [15 ] SMDA TA B22 SMBCL K (+3.3VS) GPIO 21/ SATA0GP AH1 8 LC D ID0 SI /O DET# [20]

SATA GPI O
AD 3 REQ3 # SMBDA TA (+3.3VS) GPIO 19/ SATA1GP LC DI D0 [10]

SMB
PCI _AD 4 E16 A1 3 PC I_R EQ#4 LI NK _ALER T# A26 AH1 9 LC D ID1
PCI _AD 5 A18 AD 4 (+3. 3VS) R EQ4#/ GPIO2 2 C8 PC I_R EQ#5 SMB_ LIN K0 B25 LINKALER T# (+3.3VS) GPIO 36/ SATA2GP AE19 LC D ID2 LC DI D1 [10]
PCI _AD 6 E17 AD 5 (+5VS) GPIO1 /REQ5 # SMB_ LIN K1 SMLINK0 (+3.3VS) GPIO 37/ SATA3GP LC DI D2 [10]
A25
PCI _AD 7 A17 AD 6 E7 PC I_GNT#0 SMLINK1 AC1
AD 7 GN T0 # CLK14 C LK1 4.3M_ICH [ 4]

Clocks
PCI _AD 8 A15 D 16 PC I_GNT#1 PM_R I# A28 B2
PCI _AD 9 C14 AD 8 GN T1 # PC I_GNT#2 R I# CLK48 C LK4 8_U SB [ 4]
D 17 PCI _GNT# 2 [15]
PCI _AD 10 E14 AD 9 GN T2 # F1 3 PC I_GNT#3 A19 C20
PCI _AD 11 D14 AD 10 GN T3 # A1 4 PC I_GNT#4 [14] PC BEEP A27 SPKR SU SC LK
PCI _AD 12 B12 AD 11 (+3. 3VS) GNT4#/ GPIO4 8 D8 PC I_GNT#5 PCI _GNT# 4 [14] [20] SU S_STAT# PM_S YSRST# A22 SUS_S TAT# B24 SUS B#
PCI _AD 13 C13 AD 12 (+3. 3VS) GPIO17/GN T5 # SYS_R ST# SL P_S3# SUS C# SU SB# [ 19, 22, 23,24]
PC I_ C/BE#[0.. 3] [15] D23 SU SC # [ 19]
PCI _AD 14 G15 AD 13 PM_B MBUST# SL P_S4#

SYS GPIO
AB18 F22 SLP_S5#
PCI _AD 15 G13 AD 14 B1 5 PC I_C /BE#0 [5] PM_BMBUST# GPI O0/ BM_BU SY # (+3. 3V) SL P_S5#
PCI _AD 16 E12 AD 15 C/BE0 # C 12 PC I_C /BE#1 SW I# B23 AA4 IC H_PW ROK
PCI _AD 17 C11 AD 16 C/BE1 # PC I_C /BE#2 [19] SW I# GPI O11/SMBA LERT# (+3.3V) PW R OK
D 12 R 202 100K_ 04(R)
PCI _AD 18 D11 AD 17 C/BE2 # C 15 PC I_C /BE#3 PM_S TPPC I# AC 20 AC2 2
PCI _AD 19 A11 AD 18 C/BE3 # [4] P M_STPPC I# PM_S TPCPU# GPI O18/STPP CI# (+3.3VS) (+3. 3VS) GPIO16/DPRS LPVR PM_D PR SLP VR [5 ,21]
AF 21 R 203 100_0 4
PCI _AD 20 A10 AD 19 A7 PC I_I RD Y # [4] PM_STPCPU# GPI O20/STPC PU # (+3.3VS) C21 R 207 10K _04

Power MGT
PCI _AD 21 F11 AD 20 IR DY # PC I_PAR PCI _IR DY # [15] TP0/BATLOW# 3V
E1 0 PCI _PAR [15] A21
PCI _AD 22 F10 AD 21 PA R A1 2 PC I_D EVSEL# GPI O26 (+3.3 V) C23
PCI _AD 23 E9 AD 22 D EVSEL # C9 PC I_PER R# PCI _D EVS EL# [15] B21 PWR BTN# PW R _BTN# [19]
PCI _AD 24 D9 AD 23 PERR # PC I_LOC K# PCI _PERR # [15 ] GPI O27 (+3.3 V)
E1 1 E23

B.Schematic Diagrams
PCI _AD 25 B9 AD 24 PLOCK # B1 0 PC I_SER R# GPI O28 (+3.3 V) C19 R 396 10K _04
PCI _AD 26 A8 AD 25 SERR # F1 5 PC I_STOP# PCI _SERR # [15 ] AG18 LAN _RST#
PCI _AD 27 A6 AD 26 STOP # F1 4 PC I_TRD Y # PCI _STOP # [15] [ 15, 19, 20] PM_C LKRU N# GPI O32/C LKR UN # (+3. 3VS) Y4 R 157 100 _04
PCI _AD 28 C7 AD 27 TR DY # PC I_R ST# PCI _TR DY # [15 ] SB_MUTE AC 19 R SMRST# RSMR ST# [ 19]
B1 8 R 158 10K _04
PCI _AD 29 B6 AD 28 P CIR ST# U2 GPI O33/AZ _D OC K_ EN # (+3.3VS) E20 MBID 0
PCI _AD 30 E6 AD 29 [10] SW BKON GPI O34/AZ _D OC K_ RST# (+3.3VS) (+3.3V) GPIO9 A20 MBID 1 3/8
PCI _AD 31 D6 AD 30 C 26 PLT_R ST# PM_W AKE# F 20 (+3 .3V) G PIO10 F19 R 189 0_0 4(R )
AD 31 P LTR ST# PC LK_IC H PLT_R ST# [5,14 ,20] [1 6,17] PM_W AKE# SERI RQ W AKE# (+3 .3V) G PIO12 SC I# [ 19]
A9 PCLK_ICH [ 4] [ 15, 19, 20] SERI RQ AH 21 E19
PC ICL K SER IR Q (+3 .3V) G PIO13
[ 15] PC I_FR AME #
PCI_FR AME# F16
FR AME# PME #
B1 9 PME#
PME# [15,1 9] [2] PM_THR M#
PM_THR M#

VR M_ PW RG D
AF 20

AD 22
THR M#

VRMPW RGD
(+3 .3V) G PIO14
(+3 .3V) G PIO15
(+3 .3V) G PIO24
R4
E22
R3
D20
P_RST#
GATE_PCIR ST#
Sheet 12 of 29
Interrupt I/F (+3 .3V) G PIO25

ICH7-M 2/3
FW H _W P# AC 21 AD2 1
PC I_IN T# A A3 G8 PC I_I NT#E [14] F WH _W P# R 196 0_04 AC 18 GPI O6 (+3.3V S) (+3.3VS) G PIO35 AD2 0 TPM
[15] PC I_I NT#A PC I_IN T# B B4 PIR QA# (+5VS) GPIO2/ PIR QE # F7 PC I_I NT#F [19] S CI# SMI# E21 GPI O7 (+3.3V S) GPIO (+3.3VS) G PIO38 AE20
[15] PC I_I NT#B PC I_IN T# C PIR QB# (+5VS) GPIO3/ PIR QF # PC I_I NT#G [19] S MI# GPI O8 (+3.3V ) (+3.3VS) G PIO39 FW H_TBL# [14]
[15] PC I_I NT#C C5 F8
PC I_IN T# D B5 PIR QC # (+5VS) GPIO4/ PIR QG # G7 PC I_I NT#H IC H7-M
[15] PC I_I NT#D PIR QD # (+5VS) GPIO5/ PIR QH #

AE5
MISC AH 20
AD5 RSVD [1] MC H_SY NC # AE 9 MC H_ ICH _S YN C# [5] MBI D0
AG4 RSVD [2] R SVD[ 6] AG 8 R216
AH4 RSVD [3] R SVD[ 7] AH 8 VR M_PW RGD R221 10K_04(R ) R 222 10K_04
RSVD [4] R SVD[ 8] 3VS
AD9 F2 1 3V
RSVD [5] R SVD[ 9] 10K_0 4 Q23 M520N: 00

D
I CH 7-M
C LKEN # G R394 10K_04(R) R 395 10K_04
M520X: 01
[4 ,21] C LKEN # MBI D1
2N 7002W

S
3VS

C 305
3V
.1U_04
VB AT [11,1 3]
5

1.0 5VS [2,3, 4,5,6,8,11,13,22] U27

P LT_RS T# 2 C4 74
1.5 V [22,2 4] [ 5,14,20] PLT_R ST# 4 B UF _P LT_RST#
1.5 VS [3,6, 11, 13, 16, 24] BU F_PLT_R ST# [ 16, 17, 19]
2.5 VS [6,10 ,22] 1 .1U_04
3
5V [13,1 6,19,21,23,24]
5VS [10,1 3,14,16,18,19,20,22,2 4] 74AHC 1G08 (SC -88 A)

5
3V [11,1 3,14,16,17,20,21,22,2 3,24] U19 3VS
VC CPGD 2
3VS [2,4, 5,6,9,10,11,13,14,15,1 6,18,2 0,21,24 ] [22] VC CPGD 4 IC H_PW ROK
DE LAY_PW RGD R338 0_ 04 1
[5,21] D ELAY _PW R GD
3 R 204 R197
3V C473 74AHC 1G08(SC -88A)
R 153 10K_04
1U
G ATER ST# D S PCI _R ST# 10K_0 4

G
[ 15, 17] G ATERST# PC I_R ST#
Q20 2N 700 2W 4.7K_04

[4,9, 16] SMB_IC HC LK S D SMC LK

G

GATE_PC IRS T# Q21 2N 7002W

3V 3VS
P_R ST# 3VS
R 340 0_04(R )
3VS 3VS R 190 10K _04(R ) SCI #
RN 13 RN 12 R 206 2.2K_04 SMD ATA R 360 8.2K_04 PM_CL KR UN #
8 1 PC I_R EQ#1 8 1 P CI _IN T#H R 198 2.2K_04 SMC LK R 191 8.2K_04 PM_TH RM# R 215 R214
7 2 PC I_R EQ#2 7 2 P CI _IN T#F R N14 8 1 SI/O D ET#
6 3 PC I_STOP# 6 3 P CI _IN T#E R 194 10K _04 PM_WAKE# 7 2 PM_STPPCI#
5 4 PC I_TRD Y# 5 4 P CI _IN T#G R N15 8 1 SW I# 6 3 PM_STPC PU #
7 2 SMB_LINK1 8P 4R_10K_04 5 4 SER IR Q 10K_0 4

G
8P4R _8. 2K_04 8P 4R _8. 2K_04 6 3 SMI # 4.7K_04
RN 11 8P4R _10K_ 04 5 4 PM_SY SR ST# R 188 10K_04 SCI #
8 1 PC I_R EQ#5 RN 9 S D SMDATA
8 1 P CI _IN T#D PC I_R ST# R193 0_04 [4, 9,16] SMB_I CH DA TA Q22 2N 7002W
7 2 PC I_R EQ#0
6 3 PC I_PER R# 7 2 P CI _IN T#C R N33 8 1 SMB_LINK0
5 4 PC I_IR DY # 6 3 P CI _IN T#A 7 2 LIN K_ALERT# SCI 預留
5 4 P CI _IN T#B PLT_R ST# R411 0_04(R ) 6 3 SUS_STAT#
PCIR ST# [15,16] 8P4R _10K_ 04 5 4 PM_RI# Volt age GP IO Circ uit c hang e
8P4R _8. 2K_04
RN 10 8P 4R _8. 2K_04 3V GPIO 12 ADD R18 8,R1 99
DEL R18 9,R2 11
8 1 PC I_D EVSEL#
7 2 PC I_R EQ#3 R205 10K_0 4 SUSB# 3V S GPIO 7 ADD R18 9,R2 11

6 3 PC I_LOC K# R 177 PC I_F RAME# PC LK_IC H R 351 0 _04(R ) C 492 10P_04(R ) R195 10K_0 4(R ) SLP_S5# DEL R18 8,R1 99

5 4 PC I_SER R# 8.2K_0 4 R200 10K_0 4(R ) SUSC#

R 176 PC I_R EQ#4 PC I_GNT#4 R 187 8 .2K_04 (R )
8P4R _8. 2K_04 8.2K_0 4 C 610 .022U _04
5/16

ICH7-M 2/3 B - 13
 Schematic Diagrams

ICH7-M3/3

U 2 2E
A4 P2 8
U 22 F A23 VSS[1] VSS[98] R1
G10 L1 1 B1 VSS[2] VSS[99] R1 1
V5REF [1] Vc c1 _0 5[ 1] L1 2 1.0 5 VS B8 VSS[3] VSS[ 100] R1 2
VC C 5R EF AD 17 Vc c1 _0 5[ 2] L1 4 C 27 3 C 26 2 C 25 3 B11 VSS[4] VSS[ 101] R1 3
V5REF [2] Vc c1 _0 5[ 3] L1 6 +
B14 VSS[5] VSS[ 102] R1 4
Vc c1 _0 5[ 4]
Layout note: VSS[6] VSS[ 103]
V5REF _SUS F6 L1 7 1U _X7 R B17 R1 5
V5REF _Sus Vc c1 _0 5[ 5] VSS[7] VSS[ 104]
L1 8 .1 U_04 100 U/ 6. 3V_B Place at B20 R1 6
Vc c1 _0 5[ 6] VSS[8] VSS[ 105]
AA22 M11 MCH edge B26 R1 7
Vc c1 _5 _B[1 ] Vc c1 _0 5[ 7] VSS[9] VSS[ 106]
AA23 M18 B28 R1 8
AB22 Vc c1 _5 _B[2 ] Vc c1 _0 5[ 8] VSS[10] VSS[ 107]

CORE
P1 1 C2 T6
Vc c1 _5 _B[3 ] Vc c1 _0 5[ 9] VSS[11] VSS[ 108]
AB23 P1 8 C6 T1 2
Vc c1 _5 _B[4 ] V cc 1_ 05 [1 0] VSS[12] VSS[ 109]
AC 23 T1 1 C 27 T1 3
AC 24 Vc c1 _5 _B[5 ] V cc 1_ 05 [1 1] T1 8 D 10 VSS[13] VSS[ 110] T1 4
AC 25 Vc c1 _5 _B[6 ] V cc 1_ 05 [1 2] U 11 D 13 VSS[14] VSS[ 111] T1 5
AC 26 Vc c1 _5 _B[7 ] V cc 1_ 05 [1 3] U 18 D 18 VSS[15] VSS[ 112] T1 6
AD 26 Vc c1 _5 _B[8 ] V cc 1_ 05 [1 4] V1 1 D 21 VSS[16] VSS[ 113] T1 7
AD 27 Vc c1 _5 _B[9 ] V cc 1_ 05 [1 5] V1 2 D 24 VSS[17] VSS[ 114] U4
AD 28 Vc c1 _5 _B[1 0] V cc 1_ 05 [1 6] V1 4 E1 VSS[18] VSS[ 115] U1 2
D 26 Vc c1 _5 _B[1 1] V cc 1_ 05 [1 7] V1 6 E2 VSS[19] VSS[ 116] U1 3
D 27 Vc c1 _5 _B[1 2] V cc 1_ 05 [1 8] V1 7 E4 VSS[20] VSS[ 117] U1 4
D 28 Vc c1 _5 _B[1 3] V cc 1_ 05 [1 9] V1 8 E8 VSS[21] VSS[ 118] U1 5
Vc c1 _5 _B[1 4] Layout note:
E24 VCC PAUX V cc 1_ 05 [2 0] E15 VSS[22] VSS[ 119] U1 6
E25 Vc c1 _5 _B[1 5] V5 C 27 1 Place on secondary F3 VSS[23] VSS[ 120] U1 7
E26 Vc c1 _5 _B[1 6] Vc c Sus3_3/Vcc LAN 3_ 3[ 1] V1 side under MCH F4 VSS[24] VSS[ 121] U2 4
Vc c1 _5 _B[1 7] Vc c Sus3_3/Vcc LAN 3_ 3[ 2] VSS[25] VSS[ 122]
B.Schematic Diagrams

F 23 W2 .1 U_0 4 F5 U2 5
Vc c1 _5 _B[1 8] Vc c Sus3_3/Vcc LAN 3_ 3[ 3] VSS[26] VSS[ 123]
F 24 W7 3VS F 12 U2 6
+1.5VS_PC IE_IC H Vc c1 _5 _B[1 9] Vc c Sus3_3/Vcc LAN 3_ 3[ 4] VSS[27] VSS[ 124]
G22 F 27 V2
G23 Vc c1 _5 _B[2 0] U6 F 28 VSS[28] VSS[ 125] V1 3
Vc c1 _5 _B[2 1] Vcc 3_ 3/ Vc cH D A 3 VS VSS[29] VSS[ 126]
1.5 VS L3 0 0 _1 2 H 22 G1 V1 5
Vc c1 _5 _B[2 2] VSS[30] VSS[ 127]
H 23 R7 3V C2 5 4 Layout note: G2 V2 4
Vc c1 _5 _B[2 3] Vc cSu s3 _3 /V cc SusH D A VSS[31] VSS[ 128]
C 555 C 2 85 C2 89 C 28 4 J22 G5 V2 7
+
J23 Vc c1 _5 _B[2 4] AE2 3 .1 U_04 Place within 100 mils G6 VSS[32] VSS[ 129] V2 8
Vc c1 _5 _B[2 5] V_CPU _I O[ 1] 1.0 5 VS VSS[33] VSS[ 130]
10 0U / 6.3 V_B . 1U _0 4 .1 U_04 K22 AE2 6 of ICH7 on the bottom G9 W6

Sheet 13 of 29 .1U _ 04 K23 Vc c1 _5 _B[2 6] V_CPU _I O[ 2] AH 2 6 side of 140mils on the top G14 VSS[34] VSS[ 131] W 24

VCCA3GP
L22 Vc c1 _5 _B[2 7] V_CPU _I O[ 3] C 26 3 C 27 7 C 26 1 G18 VSS[35] VSS[ 132] W 25
L23 Vc c1 _5 _B[2 8] AA7 G21 VSS[36] VSS[ 133] W 26
M22 Vc c1 _5 _B[2 9] Vcc 3_3[ 3] AB1 2 .1 U _04 G24 VSS[37] VSS[ 134] Y3
Layout note: Place above Caps within 100 mils
ICH7-M3/3 of ICH on the bottom side or
140 mils on the top near D28,
M23
N 22
N 23
Vc c1 _5 _B[3 0]
Vc c1 _5 _B[3 1]
Vc c1 _5 _B[3 2]
Vcc 3_3[ 4]
Vcc 3_3[ 5]
Vcc 3_3[ 6]
AB2 0
AC 1 6
AD 1 3
.1 U_04 1 U _0 6 G25
G26
H3
VSS[38]
VSS[39]
VSS[40]
VSS[ 135]
VSS[ 136]
VSS[ 137]
Y2 4
Y2 7
Y2 8
Vc c1 _5 _B[3 3] Vcc 3_3[ 7] VSS[41] VSS[ 138]

IDE
T28, AD28 P22 AD 1 8 H4 AA1
P23 Vc c1 _5 _B[3 4] Vcc 3_3[ 8] AG1 2 H5 VSS[42] VSS[ 139] AA2 4
Vc c1 _5 _B[3 5] Vcc 3_3[ 9] 3 VS Layout note: VSS[43] VSS[ 140]
R 22 AG1 5 H 24 AA2 5
Vc c1 _5 _B[3 6] Vc c3 _3 [1 0] Place within 100 mils VSS[44] VSS[ 141]
R 23 AG1 9 C 26 4 H 27 AA2 6
Vc c1 _5 _B[3 7] Vc c3 _3 [1 1] VSS[45] VSS[ 142]
R 24 of ICH7 on the H 28 AB4
R 25 Vc c1 _5 _B[3 8] A5 .1 U_ 04 J1 VSS[46] VSS[ 143] AB6
bottom side of
R 26 Vc c1 _5 _B[3 9] Vc c3 _3 [1 2] B1 3 J2 VSS[47] VSS[ 144] AB1 1
140mils on the top
Vc c1 _5 _B[4 0] Vc c3 _3 [1 3] VSS[48] VSS[ 145]
T22 B1 6 side J5 AB1 4
Vc c1 _5 _B[4 1] Vc c3 _3 [1 4] VSS[49] VSS[ 146]
T23 B7 J 24 AB1 6
T26 Vc c1 _5 _B[4 2] Vc c3 _3 [1 5] C 10 J 25 VSS[50] VSS[ 147] AB1 9
3VS

PCI
T27 Vc c1 _5 _B[4 3] Vc c3 _3 [1 6] D 15 J 26 VSS[51] VSS[ 148] AB2 1
T28 Vc c1 _5 _B[4 4] Vc c3 _3 [1 7] F9 C 24 3 C 26 5 C 26 0 K24 VSS[52] VSS[ 149] AB2 4
Vc c1 _5 _B[4 5] Vc c3 _3 [1 8]
Layout note: VSS[53] VSS[ 150]
U 22 G11 K27 AB2 7
U 23 Vc c1 _5 _B[4 6] Vc c3 _3 [1 9] G12 .1 U _04 Distribute in K28 VSS[54] VSS[ 151] AB2 8
V22 Vc c1 _5 _B[4 7] Vc c3 _3 [2 0] G16 .1 U_04 .1 U _0 4 PCI section L13 VSS[55] VSS[ 152] AC 2
V23 Vc c1 _5 _B[4 8] Vc c3 _3 [2 1] L15 VSS[56] VSS[ 153] AC 5
W 22 Vc c1 _5 _B[4 9] W5 L24 VSS[57] VSS[ 154] AC 9
W 23 Vc c1 _5 _B[5 0] Vc c RTC VBAT L25 VSS[58] VSS[ 155] AC 1 1
3VS Y 22 Vc c1 _5 _B[5 1] P7 C24 4 C 23 8 L26 VSS[59] VSS[ 156] AD 1
Vc c1 _5 _B[5 2] Vc cSus 3_ 3[ 1] VSS[60] VSS[ 157]
Y 23 M3 AD 3
Vc c1 _5 _B[5 3] A2 4 .1 U_04 .1 U _0 4 M4 VSS[61] VSS[ 158] AD 4
Vc cSus 3_ 3[ 2] VSS[62] VSS[ 159]
C 283 .1 U _0 4 B27 C 24 M5 AD 7
Vc c3 _3 [1] Vc cSus 3_ 3[ 3] VSS[63] VSS[ 160]
L3 2 H CB16 08 KF- 12 1T25 D 19 M12 AD 8
AG28 Vc cSus 3_ 3[ 4] D 22 M13 VSS[64] VSS[ 161] AD 1 1
1 .5VS Vc cD MIPLL Vc cSus 3_ 3[ 5] VSS[65] VSS[ 162]
G19 M14 AD 1 5
Vc cSus 3_ 3[ 6] 3V VSS[66] VSS[ 163]
C 29 0 C 291 1. 5VS AB7 M15 AD 1 9
Vc c1 _5 _A[1 ] VSS[67] VSS[ 164]
Layout note: Layout note: AC 6 K3 C27 6 C 24 2 Layout note: Layout note: M16 AD 2 3
10 U /10 V_0 8 C 2 72 AC 7 Vc c1 _5 _A[2 ] Vc cSus 3_ 3[ 7] K4 M17 VSS[68] VSS[ 165] AE2
Place within 100mils .0 1U _ 04 Place within 100mils AD 6 Vc c1 _5 _A[3 ] Vc cSus 3_ 3[ 8] K5 .1 U_04 .1 U _0 4 Place within 100 mils Place within 100 mils M24 VSS[69] VSS[ 166] AE4
Vc c1 _5 _A[4 ] Vc cSus 3_ 3[ 9] VSS[70] VSS[ 167]

ARX
of ICH on the bottom of ICH on the bottom .1 U _0 4 AE6 K6 M27 AE8
Vc c1 _5 _A[5 ] Vc c Su s3 _3 [1 0] of pin AD17 of ICH7 of pin F6 of ICH7 on VSS[71] VSS[ 168]
side or 140 mils side or 140 mils AF 5 L1 M28 AE1 1
AF 6 Vc c1 _5 _A[6 ] Vc c Su s3 _3 [1 1] L2 on the bottom side or the bottom side of N1 VSS[72] VSS[ 169] AE1 3
on the top on the top near pin AG5
Vc c1 _5 _A[7 ]

USB
AG5 Vc c Su s3 _3 [1 2] L3 N2 VSS[73] VSS[ 170] AE1 8
Vc c1 _5 _A[8 ] Vc c Su s3 _3 [1 3] 3V 140 mils on the top 140mils on the top VSS[74] VSS[ 171]
L2 9 HC B20 12 K-50 0 T4 0 AH 5 L6 N5 AE2 1
Vc c1 _5 _A[9 ] Vc c Su s3 _3 [1 4] L7 C25 0 C 24 1 side N6 VSS[75] VSS[ 172] AE2 4
1 .5 VS AD 2 Vc c Su s3 _3 [1 5] M6 N 11 VSS[76] VSS[ 173] AE2 5
C 23 7 C 239 Vc cSATAPLL Vc c Su s3 _3 [1 6] M7 .1 U_04 .1 U _0 4 5VS N 12 VSS[77] VSS[ 174] AF 2
Layout note: Vc c Su s3 _3 [1 7] VSS[78] VSS[ 175]
Place within 100mils AH 11 N7 N 13 AF 4
3 VS Vc c3 _3 [2] Vc c Su s3 _3 [1 8] VSS[79] VSS[ 176]
of ICH on the bottom 10 U /10 V_0 8 N 14 AF 8

A
.1 U _0 4 C 2 67 AB10 AB1 7 N 15 VSS[80] VSS[ 177] AF 1 1
side or 140 mils Layout note: Vc c1 _5 _A[1 0] Vc c1 _5 _A[1 9] VSS[81] VSS[ 178]
on the top AB9 AC 1 7 1 .5 VS D1 7 N 16 AF 2 7
Place within 100mils Vc c1 _5 _A[1 1] Vc c1 _5 _A[2 0] 3VS 5V 3V VSS[82] VSS[ 179]
.1 U _0 4 AC 10 N 17 AF 2 8
of ICH on the bottom AD 10 Vc c1 _5 _A[1 2] T7 SC S75 1 N 18 VSS[83] VSS[ 180] AG1
Vc c1 _5 _A[1 3] Vc c1 _5 _A[2 1] 1 .5 VS VSS[84] VSS[ 181]
Layout note: side or 140 mils AE10 F1 7 N 24 AG3

A
Vc c1 _5 _A[1 4] Vc c1 _5 _A[2 2] VSS[85] VSS[ 182]

C
Place within 100mils C 24 6 AF 10 ATX G17 N 25 AG7
on the top 1 .5 VS
of ICH on the bottom AF 9 Vc c1 _5 _A[1 5] Vc c1 _5 _A[2 3] D 16 R 15 2 D 15 N 26 VSS[86] VSS[ 183] AG1 1
side or 140 mils 1U _ X7 R AG9 Vc c1 _5 _A[1 6] AB8 R1 7 8 P3 VSS[87] VSS[ 184] AG1 4
AH 9 Vc c1 _5 _A[1 7] Vc c1 _5 _A[2 4] AC 8 SCS751 10_ 04 SC S7 51 P4 VSS[88] VSS[ 185] AG1 7
on the top near pin
1 .5VS Vc c1 _5 _A[1 8] Vc c1 _5 _A[2 5] 1 .5 VS VSS[89] VSS[ 186]
AG9 10 0_04 P12 AG2 0
VSS[90] VSS[ 187]

C
E3 K7 C 25 6 P13 AG2 5
3V Vc cSus 3_ 3[ 19] Vc c Su s1 _0 5[ 1] VC C 5R EF V5 R EF _SU S P14 VSS[91] VSS[ 188] AH 1
C2 75 C1 C 28 .1 U_0 4 P15 VSS[92] VSS[ 189] AH 3
1. 5VS Vc cU SBPLL Vc c Su s1 _0 5[ 2] VSS[93] VSS[ 190]
G20 C2 6 6 C 274 C 23 2 C 2 49 P16 AH 7
.1U _ 04 AA2 Vc c Su s1 _0 5[ 3] P17 VSS[94] VSS[ 191] AH 1 2
Y7 V c cSus 1_ 05 /Vcc L AN 1_ 0 5[1] A1 1U _ X7R .1 U _0 4 1U_ X7 R . 1U _ 04 P24 VSS[95] VSS[ 192] AH 2 3
V c cSus 1_ 05 /Vcc L AN 1_ 0 5[2]
Vc c1 _5 _A[2 6] VSS[96] VSS[ 193]
C 25 5 H6 P27 AH 2 7
Vc c1 _5 _A[2 7] VSS[97] VSS[ 194]
USB CORE

H7
.1 U _0 4 Vc c1 _5 _A[2 8] J6 I CH 7 -M
Vc c1 _5 _A[2 9]
J7 1 .5 VS Layout note:
Vc c1 _5 _A[3 0]
IC H 7- M C 25 7 Place within 100 mils
of ICH7 on the
1.5 V S [3 ,6, 11 ,1 6,2 4] .1 U_0 4 bottom side
of 140mils
3V [1 1,1 2, 14 ,1 6, 17 ,20 ,2 1, 22,23,2 4 ]
3VS [2 ,4, 5, 6,9 ,10, 11 ,1 2,1 4, 15,1 6, 18 ,20 ,2 1, 24 ] on the top side
5V [1 6,1 9, 21 ,2 3, 24 ]
5VS [1 0,1 4, 16 ,1 8, 19 ,20 ,2 2, 24]
1.0 5VS [2 ,3, 4, 5,6 ,8,1 1, 22 ]
VBAT [1 1]

hexainf@hotmail.com
B - 14 ICH7-M3/3
 Schematic Diagrams

HDD & CDROM & FAN & ROM

V DD 3

R 332

1 0K_04(R)
CPU_F ANSEN

CPU _S PD R325 0_04(R ) G

D
S Q31
2N7002W (R )
CPU_FAN ROM
VDD 5 3VS

C 45 4 .1 U_0 4 C A
VDD 5
SOCKET PLCC32

B.Schematic Diagrams
1SS355 D 35R 326

C 45 3 .1U _04 C5 09 C508 C288 C301

5
1 .1U _04.1U _04.1U _04.1 U_0 4

27
32
25
V
+

1
1 00K_1%_04 U25

C
S
4 G Q32 D 34 PLT_RST# R 423 100 2

VCC
VC C
VPP

VC CA
R 298 12 0K_ 04 3 O R 327 [5, 12,20] PL T_R ST# PCLK_F WH 31 RST#
[19] CPU_FAN ON - 2.2K_1%_0 4 [4] PCLK_F WH LPC_AD 0 13 CLK 29 R4 21 8.2K_04
[11,19,20] LPC_ AD 0 FW H0 IC
Sheet 14 of 29

G
U 17 ND S352AP LPC_AD 1 14 6 R3 46 8.2K_04
[11,19,20] LPC_ AD 1 FW H1 F GPI0

D
R9 4 S CS7 51 LPC_AD 2 15 5 R3 45 8.2K_04
[11,19,20] LPC_ AD 2

A
C449 LMV331 LPC_AD 3 17 FW H2 F GPI1 4 R4 25 8.2K_04
[11,19,20] LPC_ AD 3 LPC_FR AME # 23 FW H3 F GPI2
JFAN1 3 R4 24 8.2K_04

2. 2M_04 (R) .1U_04

R 328

R 331
4 .99K _1%_04

C4 61
F AN ON
1
2
[ 11, 19,20] LPC _F RA ME#
[11] F WH _IN IT#
FW H _IN IT# 24
18
19
FW H4
INI T#
RF U
F GPI3
F GPI4
I D3
30
9
10
R4 22 8.2K_04
HDD & CDROM &
+ C 45 5 3 20 RF U I D2 11

1 0K_1%_04
10 0U/ 10V _B2 (R) 10U /10V_08
85205-03 00

JFAN 1
[ 12] F W H_W P# R 426 100
21
22
7
RF U
RF U
RF U
I D1
I D0
GN D
12
16
28
FAN & ROM
R 427 100 8 WP# G ND A 26
2/1 6 [ 12] F WH _TBL# TBL# GN D
[ 12] PCI_ GN T#4 R 428 0(R )
3 1 F WH 32
C PU _FANSEN R 324 0_04 CPU_ SPD SOCKET PLCC32
[19] C PU_ FANSEN 3/15
VD D3 R 333 10K_04
3V [11,12, 13, 16,1 7,20,21,22,23,24 ]
3 VS [2,4,5,6,9, 10,1 1,1 2,13,15,16,18,20 ,21, 24] C A
5 VS [10,13, 16, 18,1 9,20,22,24] 1SS3 55 D36
V DD 5 [19,20, 21, 22,2 4]

5VS 5VS
Q8
SATA_LED# R58 10K_04
E C HD D_L ED
C D_LED # R59 10K_04(R) 5VS H DD _LE D [20] 3 VS
5

U3 2N 390 6

HDD/CDROM PC BEEP
B

5
S ATA _LE D# 2 U2
[11] SATA_L ED # 4 R53 4.7K _04 PLT_RST# 2
C D_LED # [5 ,12,20] PLT_RST#
1 4 ID E_ RST#
3 1
74AHC 1G 08( SC -88A) 3
74AH C1G08(SC -88A)

SATA HDD 3V

CD-ROM

5
JH DD1 U8 5/16
JC DR OM1 2 1 KBC_BEE P 2
CD-L 1 2 CD-R 4 2 1 3 [19] K BC_BE EP 4 KBC BEEP
[ 18] C D-L CDG ND 3 1 2 4 CD -R [18] [11] SA TA_ TX0 + 6 4 3 5 SATA_R X0- [1 1] 1
[ 18] C DG ND IDE_RST# 3 4 IDE_PDD8 [11] SA TA_ TX0 - 6 5 7 SATA_R X0+ [11]
5 6 ID E_P DD 8 [11] 8 3
IDE_PDD7 7 5 6 8 IDE_PDD9 10 8 7 9
[ 11] IDE _PD D7 ID E_P DD 9 [11] 74AHC 1G08(SC -88A )
IDE_PDD6 9 7 8 10 IDE_PDD10 10 9 3V
[ 11] IDE _PD D6 IDE_PDD5 9 10 IDE_PDD11 ID E_P DD 10 [11] 60M IL
11 12 SPUSA-10-VB -1
[ 11] IDE _PD D5 IDE_PDD4 11 12 IDE_PDD12 ID E_P DD 11 [11] 5VS
[ 11] IDE _PD D4 13 14 ID E_P DD 12 [11]
13 14

5
IDE_PDD3 15 16 IDE_PDD13 C 470 C464 + C229 U 29
[ 11] IDE _PD D3 IDE_PDD2 17 15 16 18 IDE_PDD14 ID E_P DD 13 [11]
[ 11] IDE _PD D2 IDE_PDD1 17 18 IDE_PDD15 ID E_P DD 14 [11]
19 20 4. 7U_08 4 2 R220 1M
[ 11] IDE _PD D1 IDE_PDD0 21 19 20 22 IDE_PDDREQ ID E_P DD 15 [11] .1 U_0 4 100U/ 16V (D)(R)
[ 11] IDE _PD D0 23 21 22 24 IDE_PDIOR# ID E_P DD REQ [11] 74 AHC 1G 14(SC -88A) C572
IDE_PDIOW# 23 24 ID E_P DIOR# [11]
[11] IDE_P DIO W# 25 26
25 26

3
IDE_PI ORDY 27 28 IDE_PDDACK# 2200P
[11] IDE_P IOR DY IDE_IRQ14 29 27 28 30 ID E_P DD AC K# [11]
[ 11] I DE _IR Q14 IDE_PDA1 29 30 PD IAG#
31 32
[ 11] IDE _PD A1 IDE_PDA0 33 31 32 34 IDE_PDA2 H3 H6 H4 H9 H2 H1 6 H7 H1 H17 H 10 H 18
[ 11] IDE _PD A0 IDE_PDCS1# 35 33 34 36 IDE_PDCS3# ID E_P DA2 [ 11] H 10_ 0D 4_7 H10_0D4_7 H 10_ 0D4 _7 H7_0D 2_3 H 7_0D2_3 H8 _0D 2_8 H 8_0D2_8H 8_0 D2_8 H8_0D 2_8 H 8_0 D2_ 8 H 8_0D2 _8 5/1 6
[11] IDE_P DC S1# CD_LED# 37 35 36 38 ID E_P DC S3# [11]
39 37 38 40 K BC BEE P
41 39 40 42 C 30 4 1 U_ 06
43 41 42 44 P CB EEP
43 44 [ 12] P CBEEP LBP [18]
45 46 R 288 10K_0 4(R ) C 57 3 1 U_ 06
R 275 0_0 4 CSEL 47 45 46 48 PD IAG# S PKR OU T
49 47 48 50 5VS [ 15] SP KR OU T C 30 3 1U_06
49 50 3/22
C DR -50DR X0000A H8 H2 1 H 12 H15 H13 H 11 H5 H 14 H 19 H20
PIN(GND1,GND2)=GND IDE_PD D7 C 276D110 C2 36D 106 C 236 D10 6 C236D 106 C236D 10 6 C 236D106 C236D 10 6 C 236 D106 C 276 D110 GN DPAD
5V S
C 391 R3 06
4.7U_08 C395 C 394 C 95

.1U _04 .1 U_04 100U/ 10V_B 2(R ) 10 K_0 4(R )

HDD & CDROM & FAN & ROM B - 15

 Schematic Diagrams

CARD READER/ 1394-PCI7412

[16 ] A_ C CB E#[0:3] A_CA D [0: 31 ] [16]

A_ CC B E# 0
A_ CC B E# 1
A_ CC B E# 2
A_ CC B E# 3
Card Reader Power

A _C A D10
A _C A D11
A _C A D12
A _C A D13
A _C AD 14
A _C AD 15
A _C AD 16
A _C AD 17
A _C AD 18
A _C AD 19
A _C AD 20
A _C AD 21
A _C AD 22
A_ C AD 23
A_ C AD 24
A_ C AD 25
A_ C AD 26
A_ C AD 27
A_ C AD 28
A_ CA D 29
A_ CA D 30
A_ CA D 31
A_ CA D 0
A_ CA D 1
A_ CA D 2
A _ CA D3
A _ CA D4
A _C A D5
A _C A D6
A _C A D7
A _C A D8
A _C A D9
3VS Q35 VCC _CA RD
N DS35 2A P
S D

M 17
M15

M18
H1 8

N1 8
N1 7

N1 9

H 19

D 19

C 13

C 11

C1 0
E1 8
E1 3
P1 9

K18
K17
K15

F 15
E17

A16
E14
B15
B14
A14

B1 3

E1 1
F1 1
A1 0
L1 7

L19
L18
L15

J 18
J 15
J 17
PC I_AD [0 :3 1]
[ 12] PC I_ AD [0 :31 ]
BGA1 C5 17 C511
P C I_AD 31 M1 F 18 R 38 5

C C BE0
C C BE1
C C BE2
C C BE3
C A D00
C AD 01
C AD 02
C AD 03
C AD 04
C AD 05
C AD 06

C A D26
C A D27
C A D28
C A D29
C A D30
C A D31
C AD 07
C AD 08
C AD 09
C AD 10
C AD 11
C AD 12
C AD 13
C AD 14
CA D 15
CA D 16
CA D 17
CA D 18
CA D 19
CA D 20
CA D 21
CA D 22
CA D 23
CA D24
CA D25
A _C C LK [16]

G
P C I_AD 30 M2 AD 31 CC LK B 12 R364 10 U/ 10 V_ 08.01U_ 04
P C I_AD 29 AD 30 C AUD IO A _C A UD IO [ 16]
M3 A 12 100K_ 04 10 0K _04
P C I_AD 28 AD 29 CSTS C HG A _C S TS CH G [ 16]
M6 H 14
P C I_AD 27 AD 28 CP AR A _C P AR [16] C A RD _P W R EN #
M5 A 11
P C I_AD 26 AD 27 C CLK RU N # A _C C LK RU N # [16]
N1 G15
P C I_AD 25 AD 26 C TRD Y # A _C TR D Y # [16 ]
N2 F 17 A _C IR D Y # [ 16]
P C I_AD 24 N3 AD 25 C IR DY G18
AD 24 CSTOP# A _C S TOP# [ 16] 3V S
P C I_AD 23 P3 G19
AD 23 C PER R # A _C P ER R # [16 ]
P C I_AD 22 R1 E 12
AD 22 C IN T# A _C IN T# [16]
R186 0_04 PM_R S T# P C I_AD 21 R2 G17
[12,16] PCI RS T# AD 21 CGR AN T# A _C GNT# [16]
P C I_AD 20 P5 E 19
AD 20 CF R AME# A _C F RA ME# [1 6]
R185 0_04(R) P C I_AD 19 R3 F 19 C 54 4 C 52 2 C 49 4 C 498 C5 43 C4 99
[12,17] GATER S T# AD 19 C D EV SEL# A _C D EV SEL# [16 ]
P C I_AD 18 T1 C 12
P C I_AD 17 AD 18 C SE R R#//W A IT# A _C S ER R # [16 ]
C 48 7 10P(R) T2 C 14 .0 1U _ 04 .1 U _0 4.1 U_04 .1U_ 04 10 U/ 10 V_0810U/ 10 V_ 08
CLK4 8_ C AR D BU S P C I_AD 16 W 4 AD 17 CR EQ# //IN PAC K# A _C R EQ# [16]
R3 55 0_04(R ) H 15
AD 16 C BLOC K# A _C B LOCK# [1 6]
CardBus
P C I_AD 15 W 7 C 15
P C I_AD 14 AD 15 C R ST# A _C R ST# [16]
R8 M19
P C I_AD 13 AD 14 R SV D_01//D 14 A _C D 14 [16]
U8 H 17
P C I_AD 12 V8 AD 13 R SV D_02 // A18 B 10 A _A 18 [16]
P C I_AD 11 W 9 AD 12 R S VD _04/ /D 2 A 13 A _C D 2 [16] A VDD 33 L6 3 3V S
P C I_AD 10 V9 AD 11 C VS1/ /VS1 # B 16 A _C V S1 [16] H CB 16 08 KF -1 21T25
B.Schematic Diagrams

P C I_AD 9 U9 AD 10 C VS2/ /VS2 # N 15 A _C V S2 [16]

P C I_AD 8 R9 AD 09 C C D1 #// CD 1# B 11 A _C C D1 # [16]
P C I_AD 7 V1 0 AD 08 C C D2 #// CD 2# A _C C D2 # [16] C 53 9 C 540 C 55 0 C4 97
P C I_AD 6 U1 0 AD 07
P C I_AD 5 R1 0 AD 06 P1 . 001 U _0 4.1U _04 10U /10V_ 08 .1U _ 04
P C I_AD 4 W 1 1 AD 05 V CC P_00 W8 3V S
AD 04 V CC P_01

PCI BUS I/F

P C I_AD 3 V1 1 F6
P C I_AD 2 U1 1 AD 03 VC C 33_1 0 F9
P C I_AD 1 P1 1 AD 02 VC C 33_0 9 F 12

Sheet 15 of 29 [ 12 ] PC I_C/B E #[0 ..3]

PC I_ C/ BE#[ 0:3 ] P C I_AD 0 R1 1

P C I_C /B E# 3 P 2
AD 01
AD 00
VC C 33_0 8
VC C 33_0 7
VC C 33_0 6
F 14
J 14
L 14
VDD PLL33 L5 8 3V S
H CB 16 08 KF -1 21T25
P C I_C /B E# 2 U 5 C BE3 VC C 33_0 5 P 10

CARD READER/ P C I_C /B E# 1 V 7

P C I_C /B E# 0W 1 0
C BE2
C BE1
C BE0
VC C 33_0 4
VC C 33_0 3
VC C 33_0 2
P8
P6 C 52 9 C 530 C 51 6 C5 41

VCC/VPP
L6
PC I_ PA R U7 VC C 33_0 1 J6 . 001 U _0 4.1U _04 10U /10V_ 08 .1U _ 04
1394-PCI7412 [1 2] P C I_P A R
[ 12 ] PC I_ FR AME #
[1 2] PC I_TRD Y #
PC I_ FR AME#
PC I_ TR DY #
PC I_ IR DY #
R6
W5
V5
PA R
F R AME#
TR DY #
VC C 33_0 0

A VD D 33_00
P 13
P 14
AV DD 33 3 VS
[1 2] PC I_IRD Y # PC I_ STOP# I RD Y # A VD D 33_01
V6 U 15
[1 2] PC I_STOP # PC I_ DE VSE L# STOP# A VD D 33_02
U6 C507 .1U _ 04
[1 2] P C I_D EVS EL # PC I_ PE RR # D EVS EL #
R7 U 19 R 36 2
[1 2] PC I_P ER R # PC I_ SE RR # W6 PE RR # VD D PLL33 VD DP LL33 R 36 8 C493 1U _0 6
[1 2] PC I_S ER R # PC I_ RE Q#2 L3 SE RR # J 19
[1 2] PC I_R EQ# 2 PC I_ GN T#2 L2 R EQ# VC CC B_00 A 15 U2 3
[1 2] PC I_GN T# 2 PCLK_CARDBUS L1 GN T# VC CC B_01 8 1
[ 4] P CL K_CA R DB U S PC I_ AD 23 R 38 1 1 00_04 N5 PC LK 2 .7K _0 4 2. 7K_04 7 VC C AD0 2
[1 2] P CI _A D2 3 PM_R S T# K3 I DS EL G2 PHY SCLK 6 W E# AD1 3
PM_R ST# PR ST# SCL SC L AD2
Texas Instruments
R 18 4 0 _04 K5 G3 PHY SDATA 5 4
GR ST# SDA SD A GND

PCI7412
PME# L5
[1 2,1 9] PME # R I_OUT# K2 R 3 69 2 20 _0 4 S- 24 C02
CL K4 8_ CAR DB U S F1 VR _E N # E 10
[4] CL K4 8_CA R DB U S C LK_48 U SB_ EN K 19 C 5 15 1U_ 06
R 36 3 4 7K_04 J 5 1. 5V_01
3V S SU SP EN D #
R 37 9 4 7K_04 K1 C 5 14 1U_ 06
1. 5V_00

Miscellaneous
PM_C L KR UN # R 37 8 0 _04(R ) J 3
[12 ,19,2 0] P M_C LKRU N # MF UN C 6
3V S R 37 7 4 7K_04 J 2 R 12 R 3 99 1 K_ 04
PC I_ IN T# D R 36 1 0 _04 J1 MF UN C 5 C PS
[1 2] PC I_IN T# D MF UN C 4
SE RI RQ R 37 0 0 _04 H1 P 15 C 5 28 . 1U _0 4
[1 2, 19 ,20] SE R IR Q MF UN C 3 VD D PLL15
PC I_ IN T# C R 35 4 0 _04 H2 T18 R 38 3 0_04 (R )
[1 2] PC I_IN T# C MF UN C 2 R0 3VS
PC I_ IN T# B R 35 3 0 _04 H5 T19 R 384 6.34K _1 %_04 C ML1 6P -R ID 1
[1 2] PC I_IN T# B MF UN C 1 R1
PC I_ IN T# A R 35 2 0 _04 G1 P 17 R 382 4.7K_ 04 L40 1 8

IEEE1394
[1 2] PC I_IN T# A MF UN C 0 PH Y _TEST_ MA 3VS
SP KR OUT H3 U 12 J 13 94 1
[1 4] S PK RO U T SP KR OU T P C 0_RS VD

. .
R 38 0 4 7K_04(R ) V 12 2 7 4
P C 1_RS VD 3
[1 6] TPS_LATCH C9 W 12 2
LATC H/ /VD 3 //V PPD 0 P C 2_RS VD 1
[1 6] TPS _C LOC K A9 3 6
C LOC K/ /V D1 //VC CD 0#
[1 6] TPS_DA TA B9 C 54 6 1 U_06
D ATA//V D 2// VP PD 1

. .
3V S R 35 6 4 7K _04 C4 R 13 R 403 56. 2_04 4 5
V C C_ C AR D R SVD _0 3/ /V D0 //VC CD 1# //P S _MOD E TP BIA S 0 R 402 56. 2_04 CLOSE TO J _1
J_CR 1
TI7412
FlashMedia
CA R D_ PW R E N# C8 W 13 TPB0- R 20 0 _0 4(R ) 1
F8 MC _P W R_ C TR L_0 TPB 0N V 13 TPB0+ R 21 0 _0 4(R ) 2 TP B#
MC _P W R_ C TR L_1// SM_R /B # TPB 0P W 14 TPA 0- R 22 0 _0 4(R ) 3 TP B
P1 S D _C D # E9 TPA 0N V 14 TPA 0+ R 23 0 _0 4(R ) 4 TP A#
C D_SD P 11 S D _W P E7 SD _C D# TPA 0P R 400 56 .2 _0 4 R 397 5.1 K_04 TP A
W P_SD SD _W P//S M_C E#

SH 1
SH 2
SD _CM D //S M _A LE //S C _GPI O2
P6 P7 R 401 56 .2 _0 4 C 545 22 0P CLOSE TO 1394 CONNECTOR

S D_DA T 0// SM _D 4 //S C_ GPIO6

SD _DA T1 // SM _D 5 //S C_ GPIO5
SD _DA T2 // SM _D 6 //S C_ GPIO4
SD _DA T3 // SM _D 7 //S C_ GPIO3

SD _CL K/ /SM _ RE #/ /S C_ GPIO1

V D D_ SD CLK_SD P 14 CL K_ SD R 357 4 7_ 04 MS /SD _CL KA 7
P1 3 CLK_MS P4 MS _B S/ SD _C MD E 8 MS_C LK //S D _C LK// SM_E L_ W P# 1 394_CON

S M_PH YS_W P#//S C _F CB

XD _CD #/ /SM_ PH Y S_ W P#

5
6
V C C_ MS C MD_SD MS_BS/ /SD _ CMD //SM_W E#
Ground
P 20 W 17 C 547 . 1U _04
BS_MS TP BIA S 1 W 15 R 412 1K_ 04

S M_C LE//SC_ GPIO 0

P9 MS /S D_ D0 B7 TPB 1N V 15 R 404 1K_ 04

S M_R /B# //S C _R FU

P5 D AT0_ SD P 18 MS /S D_ D1 C7 MS_D ATA0 // SD _D A T0//S M_ D 0 TPB 1P W 16

S C_PW R _C T RL
P8 V SS _SD D AT0_ MS P 10 MS /S D_ D2 A6 MS_D ATA1 // SD _D A T1//S M_ D 1 TPA 1N V 16
V SS _SD D AT1_ SD P 19 MS /S D_ D3 B6 MS_D ATA2 // SD _D A T2//S M_ D 2 TPA 1P P 12 R 398 330_0 4
D AT1_ MS MS_D ATA3 // SD _D A T3//S M_ D 3 TEST0
S C_D AT A
P2
S C_VC C 5

A G ND _02
A G ND _01
A G ND _00
S M_C D#
D AT2_ SD
S C _OC#
S C_C D#

GN D _0 3
S C_R ST
S C_C LK

GN D _1 0
GN D _0 9
GN D _0 8
GN D _0 7
GN D _0 6
GN D _0 5
GN D _0 4

GN D _02
GN D_01
GN D_00

V SSP LL
P1 2 P 17 R 19
P2 1 V SS _MS D AT2_ MS P3 MS _C D# A8 XI
V SS _MS D AT3_ SD P 15 MS_C D# R 18 Y3 3/21
P2 2 D AT3_ MS XO
P2 3 GN D P 16 C L K_ SD PC I7 41 2Z HK
B8

B4
E3

A5
B5
E6

A4
A3

F7

P9
F2
F3
E2
F5
E1

G5

D1

C6

C5

F 10
F 13
G14
K14
M 14

P7
N6
K6
H6
R1 4
U1 4
U1 3
R1 7
GN D IN S_MS
G6

C 548 2 4. 57 6MHz C 54 9
3 VS [2 ,4,5, 6,9,1 0, 11, 12 ,13,1 4, 16 ,18,20,2 1, 24 ]
MDR 01 9- C0 -0 01 0(R ev e rse ) C 510
3V [1 1, 12 ,13 ,1 4,16, 17,20 ,2 1,22, 23,24 ]
22P 2 2P
1 0P _04(R )

hexainf@hotmail.com
B - 16 CARD READER/ 1394-PCI7412
 Schematic Diagrams

CARDBUS & MINI CARD & USB

MINI CARD CARDBUS SOCKET

JMIN I1
1 2
[12,17] PM_W AKE# R249 0_ 04(R) 3 W AKE# 3 .3V _0 6 3 VS [ 15] A _C AD [0:3 1] JP CMCIA1 A_C CBE#[0: 3] [15]
[20] BT_D AT R251 0_ 04(R) 5 B T_ DATA 1 .5V _0 8 1.5 VS C 38 C 39 A_C AD 31 66 7 A _CC BE#0
[20] BT_C LK R252 0_ 04 B T_ CH CL K U IM_ PW R 10 C1 4 C 22 A_C AD 30 65 C AD 31/ D1 0 C CBE0#/C E1# 12 A _CC BE#1
3VS U IM_ DA TA A_C AD 29 C AD 30/ D9 C CBE1#/A8 A _CC BE#2
7 12 .1U _0 4 10U /1 0V_08 31 21
[ 4] W LAN _C LKREQ# 11 C LK RE Q# U IM_C LK 14 .1 U_ 04 10U/ 10V _0 8 A_C AD 28 64 C AD 29/ D1 CC BE2# /A12 61 A _CC BE#3
[ 4] CLK_PC IE_MIN I# R EF CL K- UIM_R ES ET A_C AD 27 C AD 28/ D8 C CBE3 #/R EG#
13 16 30 13
[4] C LK_PC IE_MINI R EF CL K+ U IM_VPP A_C AD 26 C AD 27/ D0 CP AR /A13 A_C PAR [15]
9 29
G N D0 A_C AD 25 C AD 26/ A0
15 4 28 19 A_C CLK [15]
G N D1 GN D5 A_C AD 24 C AD 25/ A1 CC LK /A16
27 33 A_C CLKR UN # [15]
A_C AD 23 26 C AD 24/ A2 C CLKR UN #/ IOI S16# 58
A_C AD 22 C AD 23/ A3 C RST# /RESET A_C RST# [15]
KEY 25

B.Schematic Diagrams
A_C AD 21 24 C AD 22/ A4 15
A_C AD 20 C AD 21/ A5 CGN T#/ WE# A_C GN T# [15]
21 18 23 60
27 G N D2 GN D6 26 A_C AD 19 56 C AD 20/ A6 C REQ#/IN PACK# 54 A_C REQ# [15]
29 G N D3 GN D7 34 A_C AD 18 22 C AD 19/ A2 5 C FR AME#/A23 20 A_C FR AME# [15]
5/1 6 G N D4 GN D8 40 A_C AD 17 55 C AD 18/ A7 CI RD Y # /A15 53 A_C IRD Y # [ 15]
GN D9 C AD 17/ A2 4 CTRD Y #/A22 A_C TR DY # [15]
35 50 A_C AD 16 46 50
[19] W LAN_ DET# G N D11 GND 10 A_C AD 15 C AD 16/ A1 7 CD EVSEL#/A21 A_C DEVSEL # [ 15]
R 434 0_04 23 45 49
[ 11] PCIE_R XN 1_WLAN P ETn0 A_C AD 14 C AD 15/ IOW R # CSTOP# /A20 A_C STOP# [ 15]
R 435 0_04 25 20 11 14

Sheet 16 of 29
[ 11] PCIE_R XP1_W LAN P ETp0 W _D ISA BL E# W LA N_ EN [ 19, 20] A_C AD 13 C AD 14/ A9 CPER R#/A14 A_C PERR # [15]
[ 11] PCIE_TXN 1_W LA N 31 22 B UF _P LT_ RS T# [1 2,1 7,1 9] 44 59 A_C SERR # [15]
33 P ER n0 P ER SE T# 30 A_C AD 12 10 C AD 13/ IOR D # CSER R#/W AIT# 16
[ 11] PCIE_TXP1_W LAN P ER p0 NC (SMB_C LK) S MB _IC H CLK [ 4,9 ,12 ] C AD 12/ A1 1 CIN T#/IR EQ# A_C INT# [15]
32 A_C AD 11 9 48
N C( SMB_D ATA) S MB _IC H DA TA [4, 9,1 2] A_C AD 10 C AD 11/ OE # C BLOC K#/A19 A_C BL OC K# [15]
17 36 R3 5 0 _0 4 42 62
U SB 6- [1 1] A_C AU DIO [15 ]

CARDBUS & MINI

19 NC3 N C( US B_D-) 38 R3 6 0 _0 4 A_C AD 9 8 C AD 10/ CE 2# CAUD IO /SPKR # 63
37 NC4 N C( USB_D +) U SB 6+ [1 1] A_C AD 8 41 C AD 9/A 10 C STSCH G /STSC HG# A_C STSC HG [15]
39 NC6 24 A_C AD 7 6 C AD 8/D 15 43
41 NC7 3.3 VAUX 28 3V A_C AD 6 39 C AD 7/D 7 C VS1/VS1# 57 A_C VS1 [15]
NC8 1 .5V _1 C AD 6/D 13 C VS2/VS2# A_C VS2 [15]

R39 0_ 04
43
45
47
49
NC9
N C 10
N C 11
1 .5V _2
3 .3V _1
N C (LED_WW AN #)
48
52
42
44
1. 5VS
3V S
A_C AD 5
A_C AD 4
A_C AD 3
A_C AD 2
5
38
4
37
C AD 5/D 6
C AD 4/D 12
C AD 3/D 5
CC D1#/C D1#
CC D2#/C D2#
36
67

51
A_C CD 1#
A_C CD 2#
[15]
[15] CARD & USB
[20] BT_EN# N C 12 L ED _W LAN# A_C AD 1 C AD 2/D 11 VC C VC CA C
51 46 3 17
[19,20] B T_DET# N C 13 NC (LE D_ WP AN #) A_C AD 0 C AD 1/D 4 VC C
2 52
88 911-5204 C AD 0/D 3 VPP 18
VPP VPPA
1
32 GN D 34
[1 5] A_C D 2 R FU /D2 GN D

GND 1

GND 3

GND 5

GN D 6
GN D2

GN D4
40 35
[1 5] A _C D14 47 R FU /D14 GN D 68
[1 5] A_ A18 R FU /A1 8 GN D
20216 -00 21L

70

72

74
69

71

73
PC B Fo otp rint = 202 16- 0021A

USB PORT 5V
5V U 20 VC CAC
TPS 22 20BDB
9 VPPA
U 21 U18 AVC C 10 C496 .1U _04
4 1 4 1 7 AVC C
VIN VO UT U SB VC C1 VIN V OU T U SB VC C2 12 V VPPA
C 513 C 45 7 20
2 C501 C5 12 2 C4 62 C 46 8 C4 63 12 V 8 C480 C481 C482
GND 4 .7U _0 8 GN D AV PP C495 .1U _04
USBVCC 1 5 3 .1U _04 U SB VC C2 5 3 4 .7U _08 4.7 U_ 08 17 .1U _04 .1U _04 10U/ 10V_08
VOU T VIN VOUT VIN NC
C49 0 C502 4.7U _08 4.7 U_ 08 . 1U_ 04 18
C 500 RT9701C BL R T9 701 CB L L5 5 F CM20 12 V-1 21 1 NC
5VS 2 5V 19
.1U _04 4.7U_08 5V NC
4.7U _08 U SB VC C1 C4 88 .1 U_ 04

O C1 # R 36 5 4 70K _0 4 3 VC CAC
[11] OC 1# DA TA TPS_DATA [15]
4 TPS_CLOC K [15]
+ C LOC K
C5 03 C 45 9 5 TPS_LATC H [15]
R 366 L ATC H 12
RE SE T# P CIR ST# [1 2,1 5]
.1U _0 4 100U /10 V_ B2 (R) L5 3 FC M2 012 V- 121 13 C484 C483 C489
3VS 3. 3V
560K _0 4 15 3 VS
J US B2 OC

SH DN
L5 0 H CB 321 6K -80 0T30 .1U _04 .1U _04 10U/ 10V_08

G ND
NC

NC
NC
NC
1 C4 77 .1 U_ 04 R3 47 10K_04 (R)

NC
NC
L 51 V+
1 2 2

24

21
6
16

11

14
22
23
[11 ] US B1- DA TA_ L
4 3 3
US BV CC 1 [11 ] USB1+ DA TA_ H
PLW3 216 S1 61S Q2
GND 2
GN D1

4
OC 0# R 367 470K_04 GN D
[11] OC0#
C 475 + S K1 071 3 R3 44
C 465
5

R371
.1 U_ 04 100U/ 10V _B 2(R ) 10 K_04(R )
560K_ 04
3V S
L52 HC B3216K-800T3 0 JU SB 3
1
L54 V+ 5VS [10,13,14,18,19,20,22,24]
1 2 2 US BV CC 2 5V [13,19,21,23,24]
[ 11] U SB0- D ATA_L 1.5VS [3,6, 11, 13, 24]
O C2 # 3V [11,12,13,14,17,20,21,22,23,24]
4 3 3 R 343 47 0K _04
[ 11] U SB0+ D ATA_H [ 11] OC 2# 3VS [2,4, 5,6,9,10,11, 12, 13, 14, 15, 18, 20, 21, 24]
PLW 3216S 161SQ 2
GND 1

GN D 2

4
G ND
R3 42 C 46 9

SK 10 713 . 1U _04
5

56 0K _04

CARDBUS & MINI CARD & USB B - 17

 Schematic Diagrams

PCIE GLAN RTL8111b

LAN_AVDD3 LAN_VDD3 LANVDD15

3/15 LAN_VDD3

U4

59

53
46
37
16

58
52
49
43

38

32
21
41

33

15
2
R84 10K_04(R)
R83 3.6K_04

VDD33

VDD33

VDD15

VDD15

VDD15

VDD15
JLAN1

AVDD33
AVDD33

VDD33

VDD33

VDD15

VDD15

VDD1
VDD15

VDD15

VDD15
U5 U11 CM-4M3216-181JT
44 EECS 1 8 L43 1 5 1
EECS MA2/ EESK CS VCC MDI0+ DA+
5 48 2 7 12 13
LAN_AVDD18 AVDD18 EESK SK NC TD4- MX4-

. .
8 47 MA1/ EEDI 3 6 MDI0- 11 14 2 6 2
11 AVDD18 EEDI 45 MA0/ EEDO 4 DI NC 5 C134 .1U_04 V_DAC 10 TD4+ MX4+ 15 DA-
AVDD18 EEDO DO GND MDI1+ TCT4 MCT4
14 9 16 3 7 3
22 AVDD18 MDI1- 8 TD3- MX3- 17 DB+
9346
LAN_EVDD18 EVDD18 TD3+ MX3+

. .
28 3 MDI0+ V_DAC 7 18 4 8 4
EVDD18 MDIP0 4 MDI0- MDI2+ 6 TCT3 MCT3 19 DC+
23 MDIN0 6 MDI1+ MDI2- 5 TD2- MX2- 20 L42 1 5 5
[11] PCIE_TXP2_GLAN HSIP RTL8111B/8100E/8101E MDIP1 MDI1- V_DAC TD2+ MX2+ DC-
24 7 4 21
[11] PCIE_TXN2_GLAN

. .
26 HSIN MDIN1 9 MDI2+ MDI3+ 3 TCT2 MCT2 22 2 6 6
[4] CLK_PCIE_GLAN REFCLK_P MDIP2 MDI2- MDI3- TD1- MX1- DB-
[4] CLK_PCIE_GLAN# 27 10 2 23
REFCLK_N MDIN2 MDI3+ V_DAC 1 TD1+ MX1+
C81 .1U_04 29 12 24 3 7 7 10
[11] PCIE_RXP2_GLAN HSOP MDIP3 MDI3- TCT1 MCT1 DD+ GND
C82 .1U_04 30 13
[11] PCIE_RXN2_GLAN HSON MDIN3

. .
B.Schematic Diagrams

4 8 8 9
19 57 C34 C36 GST5009 LF R29 R37 DD- GND
[12,16] PM_WAKE# LANWAKEB LED0
RSTB 20 56 C30 C35 75_1%_0475_1%_04 CM-4M3216-181JT
PERSTB LED1 55 PJS-A8SN3
R49 2.49K_04_1% 64 LED2 54 .01U_04 .01U_04
RSET LED3
.01U_04 .01U_04
3VS R82 1K_04 36 1 CTRL18 R26 R33
ISOLATEB VCTRL18 CTRL15
R81 15K_04 63 75_1%_0475_1%_04
5/16 C63 .1U_04 62 VCTRL15

Sheet 17 of 29

EGND
GVDD

EGND
C62 1U_06 61
CKTAL2

NC
NC
NC
NC
NC
NC
NC
NC
NC
60 C40
CKTAL1 Y1 25MHz

PCIE GLAN for EMI supression 1000P/2KV_1210

31

17
18

35
39
40
42

51
25

34

50
3/21
C75 C64

RTL8111b R74 0_04 22P 22P

5/17
LAN_VDD3
40 mil 3/15
L9 FCM2012V-121 40 mil
3V
R48 0_04 RSTB
[12,16,19] BUF_PLT_RST# V_DAC
C55 C113 C117 C83 R38 0_04(R)
R47 0_04(R) LANVDD18
[12,15] GATERST#
.1U_04 .1U_04
.1U_04 .1U_04

40 mil
L8 FCM2012V-121
LAN_AVDD3
C73 C61

.1U_04 3/21
NEAR CHIP PIN .1U_04

B
Q41
E C 2SB1188(R)

CTRL18 CTRL15

B
LANVDD15 3V LANVDD18 3V LANVDD15
60 mil Q7 40 mil Q10 60 mil
E C 2SB1188 E C 2SB1182

C56 C71 C96 C112 C114 C115 C116 C97 C84 C74 C41 C65 C46 C135 C85 C119
.1U_04 .1U_04
.1U_04 .1U_04 .1U_04 .1U_04 .1U_04 10U/10V_08 10U/10V_08 10U/10V_08 10U/10V_08
.1U_04 .1U_04 .1U_04 .1U_04 .1U_04

NEAR CHIP PIN

5/18

LANVDD18 LAN_AVDD18 LAN_EVDD18 LANVDD18

40 mil 40 mil 3V [11,12,13,14,16,20,21,22,23,24]
3VS [2,4,5,6,9,10,11,12,13,14,15,16,18,20,21,24]
L44 FCM2012V-121 L10 FCM2012V-121

C60 C59 C58 C57 C70 C72 C80

.1U_04 .1U_04 10U/10V_08 .1U_04

.1U_04 .1U_04 .1U_04

NEAR CHIP PIN NEAR CHIP PIN

hexainf@hotmail.com
B - 18 PCIE GLAN RTL8111b
 Schematic Diagrams

AUDIO CODEC ALC883

L64 F CM2012V-121(R)
3VS L33 F CM2012V-121 VDD AC
C 561 C 560 R 238 C 287 C322 C 300 C323 U 28
6 1
VDD AC VOUT VIN 5VS
10U/ 10V_08 .1U_04 .1U _04 10U /10V_08
0_04 10U /10V_08 .1U_04 4 3 R410
R 409 PG EN 10K_04
5 2
3VS [2,4, 5,6,9, 10, 11, 12,13,14,15,16,20,21,24] AGND R1 AD J
AME8804AEEY
GN D

38
33

25
5VS [10,13,14,16, 19, 20, 22,24]

9
1
C 551 10P_04(R ) U 26 3K_04
AC_SDOUT 5 35 LI NE_OUT_L C569 C 568

D CVOL

AVD D 1
D VD D2
D VD D1

AVDD 2
[11,20] AC _SDOU T SDATA-OU T FR ON T- OU T-L
AC_BITCLK R 413 22_04 6 36 LI NE_OUT_R VO=VREF(R2+R1)/R2 C 240
[11,20] AC _BITC LK BIT-C LK F R ON T-OU T-R
AC_SDIN0 R 405 22_04 8 .1U _04 10U/ 10V_08R 420 VREF=1.215V
[ 11] AC_SD IN 0 AC_SYNC SDATA-IN
10 45 .1U_04
[11, 20] AC_SY NC AC_RST# 11 SYN C SurrBack -L/GPIO0 46
[ 11,20] AC _R ST# R ESET# SurrBac k-R /XTLSEL
R2

AGND
C 292 100P(R ) 28 MIC1-VREF_L 1K_04 F CM2012V-121
MIC 1-VR EF O-L
R 392 1K_04 L36
LBP R 234 10K_04 C293 1U _06 12 48 SPD IF- OU T
[14] LBP PCBEEP SPDI FO SPD IF -OU T [20] C 307 .1U_04

AGND
C 600 .01U _04 AGND C 542 .1U_04
47 EAPD_MU TE R436 10K_04_1% C 505 .1U_04
J D_SENSE 13 SPDI FI/ EAPD 29 5/1 6 C 259 .1U_04
[ 20] JD _SEN SE Sens e A(J D1) LI NE1-VR EF O-L
34 30 MI C2-VR EF
TV_LINE_L Sens e B(J D2) MIC2-VREFO
C309 1U_06( R) 14 31 AGND
TV_LINE_R C310 1U_06( R) 15 LI NE2-L/AUX-L LIN E2-VREFO 2 GPIO0
MIC2 C601 1U_06 5 /1 6 16 LI NE2-R /AUX-R GPIO0/XTLI 3 GPIO1 AGND

B.Schematic Diagrams
C602 1U_06 17 MIC2-L GPI O1/XTLO 32 MIC1-VREF_R
C D-L R 226 4.7K_04 C311 1U_06 18 MIC2-R MIC 1-VREFO-R 37
[14] C D- L C D-L LI NE1-VREFO-R
C D-R R 228 4.7K_04 C313 1U_06 20 39 MSPKL L34
[14] C D- R MIC1 5 /1 6 C D-R SUR R- OU T-L MSPKR VD D A 5VS
C299 1U_06 21 41 F CM2012V-121
LFE C314 1U_06 22 MIC1-L SU R R-OU T-R 40 R 429 20K_04_1%

C D- GN D
LI NE-L C533 1U_06 23 MIC1-R J DR EF 43 C 306 C 571

DVSS1
DVSS2

AVSS1
AVSS2
[20] LIN E-L LI NE1-L C EN -OUT

VREF
LI NE-R C286 1U_06 24 44 C316 C 567 C 570
[20] LIN E- R LI NE1-R LFE-OUT
R 237 10U /10V_08
R 390 R 391 R235 C531
C 532
C 603
C298
C 297
C 296
C295
C 294
C 534 C 324
C535. 01U_04( R) ALC883
AGND .1U_04 10U /10V_08 L35
BK3216HS800 10U /10V_08
. 1U _04
Sheet 18 of 29

42
19

4
7

26

27
.01U_04 .01U _04 . 01U_04 .1U _04 .01U _04(R ) C553 .1U_04
[10]
[10]
[10]
L_OU T+_C
L_OU T-_C
R _OU T+_C
L_OUT+_C
L_OUT-_C
R _OUT+_C
R _OUT-_C
100K_04( R) 4.7K_04
100K_04(R ) 4.7K_04
. 01U_04 .1U _04 .01U _04 . 1U _04 .01U_04(R )

5/ 16 5/1 6
C315 AUDIO CODEC
10U /10V_08 AP GND
ALC883
[10] R_OU T-_C CDGND R227 0_04 C 312 1U_06
AGND [ 14] CD GND
R 414 4.7_04
AGND

VD DAC
R236 0_04( R)
C318 C 562
MIC2-VREF
AGND .1U _04
AMP_MUTE R 180 100K_04 R 181 120K_04 220P_X7R R419
VDD A
AMP_MUTE_M C 554 .1U _04
AMP_MUTE_M [20]

8
C 504 100U/ 4V_B C 574 .1U _04 AGND U9A
+

MSPKR R 438 100_06 MSPKR_M C 521 .1U _04 MIC2- VREF 3 0_04(R )
MSPKR _M [20]
C 268 .1U _04 1 R418 0_04
MSPKL_M
+

MSPKL R 439 100_06 C 317 C566 2

MSPKL_M [20]
MSOP8
C 478 100U/ 4V_B APGND 4.7U _08 .1U _04 LMV358MMX R 417 R408

4
C 269 C270 R 182 R 183
5/18 1K_04
680P_04( R)
680P_04(R ) 1K_04 AGND 4.7K_04 2.2K_04
U9B AGND
5
VIN INTMIC
APGN D MIC2 4. 7U _08 7 C 552 2.2U_08
C 319 6 MSOP8
LMV358MMX C 565 C 308
AP GND
APGND

U24
C278 .22U _04 5 20 C 519 .22U_04 C 564 220P_X7R 1000P_04 470P
L_H P IN R _H P I N
LI NE_OUT_L C281 1U_06 4 21 C 527 1U_06 LIN E_OUT_R R 415 20K_04 C 563 2.2U_08
R386 10K_04 L_LIN E I N R _LIN E I N R 374 10K_04 R 416
R 372
5/ 19
R373
5 /1 8
5/1 8 R2 R1 10K_04
C518 C 520 VO=VIN(R2+R1)/R1 AGND
5 /1 8
15K_04 15K_04 1000P
1000P MIC1-VREF_R R 430 2.2K_04
L_OU T+_C L31 FC M1608K-121T06 L_OUT+ 3 22 R _OUT+ 5 /19 L59 F C M1608K- 121T06 R _OUT+_C
L_OU T- _C L60 FC M1608K-121T06 L_OUT- 10 L_OU T+ R _OUT+ 15 R _OUT- L61 F C M1608K- 121T06 R _OUT-_C
L_OU T- R _OU T- LFE R 229 1K_04 LFE_M
LFE_M [ 20]
C604 C605
6
8 L_BYPASS 19 .01U _04(R ) 470P_04
9 SH UTDOW N R _BYPASS 14 AMP_MU TE
7 MU TE OU T SE/BTL# 16 J MI C1
VD D HP/LI NE#
GND /H S

GN D/H S
GN D /HS
GN D/ HS

L62 18 11 A C EAPD _MUTE INTMIC 1

VD DA VD D MUTE I N
F CM 2 01 2V -12 1 D 21 1SS355( R) AGND 2
C538 C 523 C 525 C 537 R213 R 233
NC
NC
NC

C 280 C 524 C 279 Q40 C302 85204-02001

J MIC
4.7U _08 . 1U _04
12
13
1

24
23
17
2

4.7U_08 4. 7U _08 4.7U_08 TPA0202 1K_04 10K_04 G 2 .1U_04 2 /1 4

VOL_MU TE [19]
. 1U _04 2N7002W R 437 100_04 1
S

.1U_04 MIC1-VREF_L R431 2.2K_04

D

Q42
VDD A
APGN D G EAPD_MU TE MIC 1 R432 1K_04 MIC
MIC [ 20]
APGN D AP GN D 2N7002W
S

C606 C607

.01U _04(R ) 470P_04

APGN D

AGND

AUDIO CODEC ALC883 B - 19

 Schematic Diagrams

H8 2111

3 /2 8
JH 8D BG R 113 1 0K_04 MD 0_ BO OT_F LASH
2 1 K B C_VD D V DD 5 V DD 3
K BC _V DD U13 R 280 1 0K_04 V D D3
L4 7 24 mil 5 1
V D D5 VD D 3 VO V IN R 11 2
10 9 V D D3 10 K_ 04
HC B 20 12K-5 00 T40 (R ) C 45 4 2 C 384 Q 11

G
JH 8D B G1 C 390 BP GN D U6 2 N700 2W R1 14
MD0 _B OO T_FLAS H 10 U/ 10V_0 8 3 1 U_06 3 100 K_ 04
KBC _TXD 1 2 1 K BC _ MD 1 C 54 C3 89 C3 87 C 38 8 C4 03 C 39 8 C1 10 .0 1U _0 4 SD MR# 1 S D
PWR _ SW # 4 3 K BC _ RXD1 GM28 38 GI M2 5 5 R ESE T#
3IN1 6 5 8 0C LK V DD 3 V CC KB C_ RE S ET#
1 0U /10V_ 08 .1U _04 .1U _ 04. 1U _0 4 .1U _04. 1U _0 4 10 U/ 10 V_08 4
8 7 8 0P OR T_D ET# W DI
C 16 6 2
10 9 G ND C1 48
SPU FZ -1 0S3 -B-0- B . 1U _0 4 AA T351 0IGV
J _K B1 3IN 1 1U _0 6
8 52 01 -2405 1 5V

36

76

13
77

86
1
U 14
78 KB -SI 0 4

VC C B

VC L
VC C
VC C
A V ref
AV CC
MD 0_BO OT_F LA SH 10 P 60 /FTCI /KI N0 #/ TMIX 79 KB -SI 1 5 A UX_C LK R 46 10 K_ 04 5V S
K BC _MD 1 9 MD 0 P6 1/ FTOA /K IN1# 80 KB -SI 2 6 A UX_D ATA R 45 10 K_ 04
K BC _TXD 1 13 3 MD 1 P 62/ FTIA /KI N2 #/TMI Y 81 KB -SI 3 8 K BD _C LK R 44 10 K_ 04
K BC _R XD1 P84 /IR Q3# /Tx D1 P63 /FTIB /K IN3# KB -SI 4 K BD _D A TA
13 4 82 11 R 54 10 K_ 04
8 0C LK P85 /IR Q4# /Rx D 1 P64 /FTIC /K IN4# KB -SI 5
23 83 12 R 29 2 R 29 3
3 IN 1 22 P91 /IR Q1# P65 /FTID /K IN5# 84 KB -SI 6 14
P92 /IR Q0# Debug Port P66 /FTOB/K IN 6# /IR Q6 # 1 0K _0 4 10K_ 04
B.Schematic Diagrams

8 0P OR T_ DE T# 27 85 KB -SI 7 15 J _TP1
PE5 P67 /TMOX/K IN 7# /IR Q7 # VD D 3 1
L PC _AD 0 12 1 94 KB -SO 0 1 1 2 T P _D A T A
[ 11, 14 ,20 ] LP C_ AD 0 L PC _AD 1 P30 /D 8/H D B0/LA D 0 PC 0 KB -SO 1 2 T P _C LK
12 2 93 2 3
[ 11, 14 ,20 ] LP C_ AD 1 L PC _AD 2 P31 /D 9/H D B1/LA D 1 PC 1 KB -SO 2 3
[ 11, 14 ,20 ] LP C_ AD 2 12 3 92 3 4
L PC _AD 3 12 4 P32 /D 10 /H DB2/L AD 2 PC 2 91 KB -SO 3 7 RN1 4
[ 11, 14 ,20 ] LP C_ AD 3 P33 /D 11 /H DB3/L AD 3 PC 3
L PC _F R AME# 12 5 90 KB -SO 4 9 K B- SI5 1 10
[11 ,1 4,20] LP C _F RA ME #
B UF _PLT_R ST# 12 6
P34 /D 12 /H DB4/L FR AME # INT. K/B PC 4
89 KB -SO 5 10 K B- SI6 2
1 10
9 KB -SI 3 8 5201- 040 51 C 40 8 C 409 C4 10
[12 ,1 6,1 7] B UF _PLT_R ST# K BC _PC LK P35 /D 13 /H DB5/L R ESET# PC 5 KB -SO 6 K B- SI2 2 9 KB -SI 4
12 7 88 13 3 8 . 1U _0 4 4 7P _04 47 P_ 04
[ 4] KBC _P CL K P36 /D 14 /H DB6/L C LK PC 6 3 8 7

Sheet 19 of 29 [ 12, 15 ,20 ] SE RI RQ

[1 2, 22, 23 ,24 ] SU SB #
S ER IR Q

S US B #
S US C #
12 8

75
74
P37 /D 15 /H DB7/S E RIR Q

P77
PC 7
PD 0
PD 1
87
66
65
64
KB -SO 7
KB -SO 8
KB -SO 9
KB -SO 10
16
17
18
19
K B- SI0 4
5 4
5
7 6
6
1 0K _1 2_ 10P 8R
KB -SI 1
KB -SI 7

[ 12] S U SC # P76 PD 2

H8 2111 [ 12 ,15 ,20] PM_C LK R UN #

SW I# A
P M_ C LK RU N#

C H8 _S W I#
13 1

12 9
P82 /C LK RU N #/H IF SD PD 3
PD 4
PD 5
63
62
61
60
KB -SO 11
KB -SO 12
KB -SO 13
KB -SO 14
20
21
22
23 K B- SO 6 1
R N 17
10
[ 12] S WI #
D 32 SC S 751 P80 /P ME # South PD 6 59 KB -SO 15 24 K B- SO 7 2 1 10 9 KB -SO 4
PD 7 2 9
[ 11] G A2 0
GA2 0 A C H8 _G A 20 13 0
P81 //C S2#/ GA20
Bridge K B- SO 5 3
3 8 7
8 KB -SO 3
D 33 SC S 751 K B- SO 0 4 KB -SO 2
SMI # 1 24 4 7 6
A C H8 _S MI# 12 0 J_ KB 5 KB -SO 1
[ 12] S MI # PB0 /D 0/ WU E 0#/ LS MI # LE D_ SC RO L L 5 6
D 31 SC S 751 1 03
SCI # P20 L ED _S CR OLL [20]
A C H8 _S C I# 11 9 1 02 LE D_ NU M 1 0K _1 2_ 10P 8R
[ 12] 3/ 8 S CI # PB1 /D 1/ WU E 1#/ LS CI P21 LE D_ CAP L ED _N U M [20 ]
D 30 SC S 751 1 01
R SMR ST# 11 5
LED P22 1 00 LE D_ PW R
L ED _C AP [20 ]
[ 12] R SMR ST# PB5 /W U E5 # P23 L ED _P W R [2 0] R N 16
KBC _R S T#
Indicator P24
99 LE D_ AC IN
L ED _A CI N [2 0]
A C H8 _R C IN #11 4 98 LE D_ EMAI L K B- SO 8 1 10
[ 11] KBC _R ST# PB6 /W U E6 # P25 1 10
D 28 SC S 751 97 LE D_ BAT_ CH G K B- SO 9 2 9 KB -S O1 5
PW R_ BTN# P26 L ED _B AT_C H G [20 ] 2 9
A C H8 _P B# 11 3 96 LE D_ BAT_ FU LL K B- SO 10 3 8 KB -S O1 4
[ 12] PW R _B TN # PB7 /W U E7 # P27 L ED _B AT_F UL L [2 0] K B- SO 11 3 8 7 KB -S O1 3
D 27 SC S 751 4
32 WE B0 # 5 4 7 6 KB -S O1 2
PE0 WE B1 # W E B0# [20 ] 5 6
31
THE R M_ RS T# 3 PE1 30 WE B2 # W E B1# [20 ] 1 0K _1 2_ 10P 8R
[2] TH ER M_ R ST# THE R M_ AL ER T# P44 /TMO 1 PE2 CC D_ D ET# W E B2# [20 ] V DD 3
2 29
[2 ] TH ER M_A LE RT# S MD _ TH ER M P43 /TMC 11 PE3 PME# C C D_DE T# [ 20]
13 8 28
[ 2] S MD _THER M
S MC _ TH ER M 13 5
P42 /TMR I0 /SD A 1 Theraml PE4
26 BT_D ET#
P ME# [12 ,1 5] V DD 3
[ 2] S MC _THER M P86 /IR Q5# /SC K 1/S CL 1 PE6 WL AN _D E T# B T_ DET# [16 ,2 0] 3/ 24 H 8_ RC IN #
25 R 11 6 10 K_ 04 D 12
PE7 W L AN _D ET# [1 6]
C H G_EN 16 R SMR ST# R 11 5 10 K_ 04(R) C
[ 25] C HG _EN H 8_ 15 P50 /E xTxD 1* BT_E N H 8_ SMI# S MC _BAT1
15 1 36 R 10 4 10 K_ 04 AC BAV 99
SMC _BA T1 P51 /E xR xD 1* P40 /TMC I0 CC D_ EN B T_ EN [20 ] H 8_ SC I#
R 28 5 100_ 04 14 1 37 R 10 5 10 K_ 04 A
[ 25] SMC _B AT1 P52 /E xS CK 1* /SC L 0 P41 /TMO0 4 WL AN _E N C C D_EN [20 ] H 8_ GA20 R 10 2 10 K_ 04
SMD _BA T1 P 45/ TMR1 1 BK L_ EN W L AN _E N [1 6,2 0] H 8_ SW I#
R 28 4 100_ 04 17 5 R 10 3 10 K_ 04 D 11
[ 25] SMD _B AT1 P97 SD A0 P46 B KL _EN [10 ] H 8_ PB# R 11 7 10 K_ 04 C
BAT1_ DE T R 27 4 100_ 04 H8 _P 706 8 43 H8 _4 3 P ME # R 28 1 10 K_ 04 S MD _BAT1 AC BAV 99
[ 25] BAT1_ DE T P70 /A N0 PF 7/ TMOY *
BAT1_ VO LT R 27 3 100_ 04 H8 _P 716 9 44 H8 _4 4 A
[ 25] BAT1 _V OL T
B AT2_DE T 70
P71 /A N1 Battery P F6 /Ex TMOX*
45 H8 _4 5 W E B0 # R 60 10 K_ 04
B AT2_VO LT P72 /A N2 P F5 /E xTMIY * H8 _4 6 W E B1 #
71 46 R 27 6 10 K_ 04 D 23
CH G _C UR SE NR 50 H8 _P 747 2 P73 /A N3 P F4/E xTMI X* H8 _4 7 W E B2 #
100_ 04 47 R 27 7 10 K_ 04 C
[ 25 ] C H G_CU R SEN TOTA L_ CU R R 27 2 H8 _P 757 3 P74 /A N4 PF3 /TMOB H8 _4 8 B AT1_D E T
[ 25] TOTAL _C U R 100_ 04 48 AC BAV 99
P75 /A N5 PF2 /TMOA 49 SY S_ FANS E N C C D_ DE T# R 61 10 K_ 04 A
GPIO PF 1/TMIB 50 CP U_ FA N SE N B T_ DET# R 62 10 K_ 04
A UX_C LK PF 0/TMIA C P U_ FA NS EN [14 ] W L AN _D ET#
39 R 71 10 K_ 04 D 24
A UX_D A TA 38 PA2 /K IN 10 #/PS2 AC 51 H8 _5 1 C
K BD _C L K 37 PA3 /K IN 11 #/PS2 AD P G7 /Ex SC LB* 52 H8 _5 2 B AT1_V O LT AC
PA4 /K IN 12 #/PS2 BC PG 6/ Ex SD AB* BAV 99
K BD _D A TA 35 53 H8 _5 3 K BC _MD 1 R 78 10 K_ 04 A
TP_ CLK 34
PA5 /K IN 13 #/PS2 BD PS2 P G5 /Ex SC LA*
54 H8 _5 4 K BC _TXD 1 R 90 10 K_ 04
TP_ DATA PA6 /K IN 14 #/PS2 CC PG 4/ Ex SD AA* H8 _5 5 K BC _R XD1
33 55 R 89 10 K_ 04 D 25
PA7 /K IN 15 #/PS2 CD PG3 56 H8 _5 6 8 0C LK R 27 9 10 K_ 04 C
V CO R E_ ON 41 PG2 57 H8 _5 7 8 0P OR T_ D ET# R 27 8 10 K_ 04 C HG _C U RS EN A C
[21 ] VC O RE _O N PA0 /K IN 8# PG1 BAV 99
K BC _PW RG D 40 58 H8 _5 8 A
PA1 /K IN 9# PG0 MO DEL_ ID R 27 1 10 K_ 04
K BC _R E SE T# 8 1 18 SR S_ EN # D 26
KB C _R ES ET# R E SE T_ OU T# R E SE T# PB 2/W U E2# KB C_ BEEP
14 2 1 17 C
R E SE T_ OU T# Power PB 3/W U E3# 1 16 VO L_ MU TE K BC _ BE EP [1 4] R 27 0 10 K_ 04(R) TOTAL_C UR AC
PB 4/W U E4# V O L_MU TE [1 8] BAV 99
[ 23] PW R _S W#
P W R_SW # 24
P90 /IR Q2# /AD TR G # Management A
A C_ IN # 21
[ 25] A C_ IN # P93
MO DEL_ ID 20 1 04 BR IG HTNE SS KBC _PCL K R9 2 10_0 4 C1 11 10P _0 4 S MC _BAT1 R 28 7 4.7 K_ 04
MOD EL_I D D D _ON P94 P1 7/ PW 7 CH G_ C UR B R IGH TNE SS [ 10] S MD _BAT1
[ 24] D D _O N 19 1 05 R 28 6 4.7 K_ 04
L ID _SW# 18 P95 P1 6/ PW 6 1 06 H8 _1 06 B AT1_D E T R 26 9 10 K_ 04
[ 10, 20 ] LID _ SW # P96 /E XC L P1 5/ PW 5 H8 _1 07
1 07
R 91 100 K_04 K BC _LPC P D# 13 2
PWM P1 4/ PW 4 1 08 H8 _1 08 H 8_ P71 C 38 3 1U _0 6
V DD 3 P83 /L PC PD # P1 3/ PW 3
R 72 100 K_04 K BC _STB Y # 12
STB Y # output P1 2/ PW 2
1 09 H8 _1 09
SY S_ FAN H 8_ P74
1 10 C 38 2 1U _0 6
R7 3 10 K_04 P1 1/ PW 1 1 12 CP U_ FA N ON
V D D3 P1 0/ PW 0 C P U_ FA NO N [1 4]
CIR _ RX C A S D NMI 11 H 8_ P75 C 38 6 1U _0 6
[20] C IR _R X N MI
D 14 1S S355 Q9 1 43
XTAL
2N 70 02W 1 44
Consumer IR Clock EXTAL R 30 2
A VS S
G

V SS
VS S
VS S
VS S
VS S

CI R_ EN 6
X2
X1

P47 1 0M
R 80 R 79 H 8S /21 11 LP C X1
14 1
14 0

7
42
95
111
13 9

67

1 0MHz
1 00 K_ 04 C1 33 C 140
10 K_04 22P _0 6 2 2P _0 6

hexainf@hotmail.com
B - 20 H8 2111
 Schematic Diagrams

BD CON & LED & CCD & BT

S
L5
H CB2012K-500T40
D Bluetooth
CCD 5V S
C9
R 15

Q3
+VCC _C CD

G
.1U _0 4 ND S352AP C 33 2 C8
1 00K _04
.1U _04 10U/10V _08

R14 JBT1
FROM H8 def HI 10K_04 1 9

FOR SUPER I/O BOARD

D
R16 10K_04 +VCC _BT
VDD 3
Q6
C CD _EN G 2N 7002W
[19] CC D_EN J BT1

S
PL W321 6S1 61SQ 2 1
+VC C_C CD L57 1 2 2 +3.3v
USB3 - 3 GN D
[11] USB3- USB3 + US B-
R 246 0_04 J CC D1 JCCD1 4 3 4
[11] U SB3+ BT_D ET# US B+
L39 [16,19] BT_ DET# 5
1 2 1 1 R 348 1 0K_ 04 DE TECT#
[11 ] U SB 4+ 2 VDD 3 PCLK_SI/ O
R 350 0 _04 6 J SIO1
3 [16] BT_D AT CH _D ATA
[11 ] U SB4- 4 3 [16] BT_C LK R 349 0 _04 7 C4 40 3VS
PLW 321 6S161SQ2(R ) 4 5 BT_EN# 8 CH _C LK 1

B.Schematic Diagrams
R 245 0_04 5 9 BT_ON# 22P_04 2
87212 -05G0 (PI N9 為作 業 防呆) GN D 3
5VS 4 JSIO1
VD D3 R 250 10K_04 87212-09G0 20
LPC_AD 0 5
[19 ] CC D_D ET# [11,14 ,19] LPC _AD 0 LPC_AD 1 6
[11,14 ,19] LPC _AD 1 LPC_AD 2 7
[11,14 ,19] LPC _AD 2 LPC_AD 3 8
[11,14 ,19] LPC _AD 3 9
10

Sheet 20 of 29
PC LK_SI/O 0_04
[4] PC LK_SI /O 11

MDC/TV OUT JMDC 1

3VS
R 175
S
L56
H C B2012K-50 0T40
D

C 506 C4 91
+VC C_ BT
[12,15,1 9] PM_C LKR UN #
[11] LPC_DR Q#
[ 11, 14, 19] LPC_FR AME#
[5 ,12,14] PLT_RST#
R 305
PM_ CLKRU N#
LPC _DR Q#
LPC_FRAME#
PLT_RS T#
SERIRQ
12
13
14
15
16 1
BD CON & LED &
[ 12, 15, 19] SERI RQ 17
TVD AC _A 1 C2 58 Q16 SUS_STAT#
[6 ] TVDAC_A [12] SU S_STAT#

G
TVD AC _B 2 ND S3 52AP . 1U _04 10U /10V_08 SI/O DET# 18
[6 ]
[6 ]
TVDAC_B
TVDAC_C
TVD AC _C
C 94 .1U _04
3
4
5
.1U_04
1 00K_04
BT_EN#
BT_EN# [16]
[12] SI/O DET#
[4] C LK14.3 M_I/O
C LK 14. 3M_ I/O

20MI L
19 N C 1
20 N C 2
87151-2 007G(R)
CCD & BT
AC_ SD OU T 6
[11,18 ] A C_SD OU T 7
3V AC_ SY NC
[11,18] AC _SYN C 8 R179
AC_ SD IN1 9 10 K_04
[1 1] AC _SD IN 1 AC_ RST# 10 FROM H8 def HI
[1 1,18] AC _R ST# 11

D
AC_BITCLK R 433 22_04 12 VD D3 R 17 4 10K_ 04
[11 ,18] AC_BITCLK
Q19
87151-1207G BT_EN G 2N 7002W
5 /18 [19] BT_EN
C 608

S
2 2P_ 04

FOR USB & PHONE JACK BOARD FOR S/W & LED BOARD
LED INDICATE 3/21

J AD J1
D20 KPB- 3025Y SGC LI NE-R 1
GREEN [18] LINE-R LI NE-L
[18] LINE-L 2
2 1 R232 220_ 08 3 JADJ1 VIN JSW1
5VS SPD IF-OUT 4 1
VIN [10,21,2 2,23,24,25] 4 3 R219 220_ 08 [18] SPDIF -OUT LF E_ M 5 PWR S 1
3V [11,12,1 3,14,16,17,2 1,22,23,2 4] [18] LFE _M MIC 6 [23] PW RS 2
3VS [2,4, 5,6 ,9,1 0,11,12,1 3,14,15,1 6,18,21,2 4] [18] MIC
D

RED 7 3
VD D3 [2,10,11 ,14,19,23,24 ,25] JD _S EN SE 3V LID_SW# 4
5V [13,16,1 9,21,23,24] Q28 [18] JD_ SENSE 8 [10,19] LID _SW# JSW1
BT_ EN G 2N 7002W AMP_MU TE_M 9 5
5VS [10,13,1 4,16,18,19,2 2,24] [19] BT_EN [18 ] AMP_MUTE_M 5VS 6 20
10 12 3/20
VD D5 [14,19,2 1,22,24]
S

MSPKR_ M 11 PC _L ED 7
[18] MSPKR _M
D

MSPKL_M 12 8
Q24 [18] MSPKL_M LED_SCROLL 9
WLAN _EN [ 19] LED_SC ROLL LED_CAP 10
[1 6,19] WLAN _EN G 2N 7002W 85201-12051 [19] LED _C AP LED_NUM 11
[19] LED _N UM
S

HDD_LED 12
[14] HD D_LED WEB0# 13
[19] W EB0# WEB1# 14
[19] W EB1# 15
WEB2#
[19] W EB2# 16 1
17
18
D 19 KP B-3025YSGC D18 KPB- 3025Y SGC 3/ 20 JUS B1 20MIL 19 NC 1
GREEN GREEN 20 NC 2
PC_ LED V DD 5 CI R_R X 1 JU SB3
V DD 5 2 1 R 218 220_0 8 VD D 5 2 1 R230 220_ 08 87151-20 07G
[ 19] C IR _R X 2 1
4 3 R 217 220_0 8 4 3 R231 220_ 08 3
[ 11] U SB 2- 4
[ 11] U SB2+
D

RED RED 5
Q36 Q39 6
U SBVCC 2 7 8
LED_BA T_FULL G 2N7002W LED _PWR G 2N 7002W
[19] LED _BAT_FU LL [19] LED _PW R 8
D

D
S

85204-08001
Q38 Q37 C466 C 46 7
LED_BA T_CH G G 2N 7002W LED _ACIN G 2N 7002W
[19] LED _BAT_CH G [19] LED _AC IN
. 1U _04 . 1U _04
S

BD CON & LED & CCD & BT B - 21

 Schematic Diagrams

+VCORE

5V VIN

PC 34

A
PQ2 7 P C1 6 PC85

5
6
7
8
+
2 _10V_ 06
1U PD 11 1 P C83
IRF 78 21TR PB F . 1U /50 V_06 10U /25 V_12 15U /25V_ V
SC S5 51V PR3 4 4
VI N 10_ 06

2
3
1
C
VD D5 5V 5 /16
PJ 6 2 2 /13
*O PEN _30 m il BST1
1 2 1
V-R C1
1 PC 3 3
1
PR 81 *0_ 04 PC2 5 21U _1 0V _ 06 P R27 0_06
PR8 2
100_1%_ 06 2
1000P_ 06
PR 79 1 2 3/1 5
SGN D3 2 1 2
PR 80 *0_ 04 Z 2901 7 .5K _1%_06 PC 36 15n_ 06 PL4
[ 2,11] H_ DP R STP# E N_VC OR E
PR 25 499_ 1% _06 Z 2902 TG1 18A
B.Schematic Diagrams

[5 ,12] PM_D PR SLPVR

close to IMVP6

VPN1
D RN 1 .5U _1 0* 10* 4.5
3 V 3VS B G1

D RN 1
Modified in

5
6
7
8

5
6
7
8
ISH PQ 26 PQ 10

C
checklist 1 1 1 IR F7831 TR PBF
4 4 IR F7 831TR PBF PD3

40
39
38

34
44
43
42
41

37
36
35
Rev 1.501
PR3 8 P R2 6 PC 35

2
3
1

2
3
1
* 680_06 6 80_ 06 SM340A

VPN 1
VIN 1
BST 1
TG 1
DR N 1
BG 1
V5_ 1
EN
NC
IS H
DPRS L
2
.1U_50V_0 6 5/1 6

Sheet 21 of 29

A
PC 38 2 1 100P_04 2 2
CL KEN# 1 33
[ 4,12] CL KEN# VR EF 2 C LKE N # C S1 + CS1N
PR 87 30.1K _1%_06 PR 85 1 30K_1%_06 32
HY S 3 VR EF C S1- 31 CS2N VC OR E

C S1N
PU2
+VCORE PR 95 124K _1% _06
PR 86 1 30K_1%_06 [3] H_VI D6
CL SET 4
5
6
H YS
C LSE T
VI D6
C S2-
C S2 +
ER R OU T
30
29
28 VC CA 2
PR13 0_06 36A
[3] H_VI D5 VI D5 V CC A
PC 44 1 2 100P_04 7 27
[3]
[3]
H_VI D4
H_VI D3 8 VI D4
VI D3
SC452 AGN D
DAC
26 DAC PR33
9 25 SS 1 1K_1% _06
[3] H_VI D2 VI D2 SS
PC 39 2 1 1000P_0 6 10 24 1 PR30 0_06
[3] H_VI D1 11 VI D1 D RP + 23 P C4 1 PC40 1 PC8 6 PC 84 P C79 PC 22 PC32
[3] H_VI D0 VI D0 D RP - 1 1 + + + + +

PW RGD
E-RC

C S2N
PC 42

DR N 2

1U_10V_06

* 470U /2.5V_V
3VS

VPN 2

1000P_06

470U/2.5V _V

47 0U /2. 5V_V

470U/2.5V _V

47 0U /2. 5V_V
BST 2
SGND 3 PC 46 2 1

VIN 2

V5_ 2
PSI #
GN D

TG2

BG2

F B+
2

FB-
V IN
1 102n_0 4 PC 43 2
PR42 100P_0 4

45

16
17
18

22
12
VP N2 13
14
15

19
20
21
15200P_06
1K_ 04
PQ29 PC 23 PC88
2 VR EF +
[ 5,12] DE LAY _PW R GD P R4 3 1 2 0_04 PC 90

5
6
7
8
.1U/ 50V _06 1 0U /25V_12 15U /25V_ V
SGN D 3 IR F 7821TRP BF
P R4 6 1 2 10_0 6 FB+ 4
[ 3] VCC S EN SE P R4 7 1 2 10_0 6 FB-

2
3
1
[ 3] VSSSE NS E 5/16
[ 2] PSI# DR P -
2 DR P + 3/15

D RN 2
P R9 3 1 2 5/16
PR 55 1 PC 51 1 P C50 1 P C5 3 1 PC5 2 1 2 C S2 P 1 2 P L5
*1 00P _04 *100P_04 * 100 P_04 * 100P_04 PC 37 15n _06 PR45 0_06
1
*680_06 7.5K_1 %_06 18A 5V
TG2
2 2 2 2 . 5U _10*1 0*4 .5

C
5
6
7
8

5
6
7
8
BG2 P Q30 PQ14
3 VS SGND 3 SGN D3 SGN D3 SGN D3 I RF 7831TRPBF IR F7831TR PB F PD 4
DR N2 4 4
1 1 SM340 A PR 52 P R5 3

2
3
1

2
3
1
PR4 4 1 10 K_04 1 0K_04

A
PC4 8 5/ 16 3/15
100_1%_ 06 P C4 7
2
1000P_ 06 EN _VCO R E
2 V-R C2 21 U_ 10 V_ 06 PQ21

D
VIN 2N 70 02W
TH1, TH2 PR31 P Q1 7 P R54
BST2 P R4 0 0_04(R ) VR _ON G G G 2 N7 002W
C S1 N 包裝=0603 [19] VCOR E_O N
1 0K_04(R )

S
0_08 P R4 1 0_04 PQ1 6
PD 7 SGND 3 [10] PM_PW RO K 2N7 002W
PR 83 TH 8
1 2 D RP_L1 2 1 SC S551V
SGND 3 TEST [22 ,23 ,24]
5V

A
28 K_1%_0 6 1 00K_TH_06 1
PR 84 P R88 47K _04 2/14
DR N 1 1 2 1 2 1 2 P C 49
P C8 9 33n_0 6 SS PR 35 *0_04
17.4 K_1 %_06 12 U_ 10 V_ 06
PR 89 47K_ 04 5V
D CR _D R1 1 2 DR P+ PC 54
PC 55 * 0.1u_ 04
PR 90 47K_ 04 3V *22 n_04_X7R
D CR _D R2 1 2 3VS
1 PU3 3V [ 11, 12, 13 ,14 ,16,17,2 0,2 2,23,24]

D
5
PR 92 P R91 47K _04 1 5/16 SG ND 3 * 74AH CT1G02
DR N 2 3 /28 CL KE N# V CO R E [ 3]
1 2 1 2 1 2 P C45 PR 48 R2 59 1 PQ 18 5V [ 13, 16, 19 ,23 ,24]
P C9 1 33n_0 6 R260 4 G *2N 7002W 3 VS [ 2,4,5, 6,9 ,10 ,11,12,1 3,1 4,15,16, 18, 20, 24]
17.4 K_1 %_06 2 P_06
68 1K_04 Z2902 PR 37 *0_04 2
V DD 5 [ 14, 19, 20 ,22 ,24]

S
16. 2K_1%_ 06 10K _04 (R )
PR 94 TH 9 2 U 12 Z2901 PR 36 *0_04 V IN [ 10, 20, 22 ,23 ,24,25]

3
1 2 D RP_L2 2 1 3 2 PM_P WR OK
DR P- VC C RE SE T# PM_PW RO K [10]
C 359
28 K_1%_0 6
1 00K_TH_06 .1U_ 04(R) R2 58 S GN D3
C S2N 1
GN D
100 K_0 4
G 69 0L293T7 3

hexainf@hotmail.com
B - 22 +VCORE
 Schematic Diagrams

+1.5V, +1.05V

VIN

PC131 1U/10V_06
PR108 0_06 PR120 10_04
VDD5
PC132 1U/10V_06
PR125 10K_04 PR121 10_04
3V
VCCPGD
[12] VCCPGD
SGND1 SGND2

A
3/15
PD15 3/15 PD19
SCS551V SCS551V
PC111
PC105 PC 103 PC97 1000P_04 PC114

C
PC92 PC96 PC115 PC109
.1U/50V_06 10U/25V_1210U/25V_12*10U/25V_12 27 13 .1U/50V_06 10U/25V_12 10U/25V_12 *10U/25V_12
PGOOD1 PGOOD2
PC152 1000P_04
PC113 1U/10V_06 3 25

B.Schematic Diagrams
VDDP1 VCCA1
PQ32 PC139 1U/10V_06 17 11 SGND1 SGND2

8
7
6
5
RSS090N03 VDDP2 VCCA2
3/15 PR106 0_06 6 23 PR139 1M_04
1.05VS 5/16 V1.05 4 DH1 TON1
PJ5 PL6 PR107 10K_1%_04 4 9 PR105 750K_04
3
2
1
5/16 ILIM1 TON2
1.5U_7*7*3.5
6A
1 2 5 20 PR137 0_06
Sheet 22 of 29

5
6
7
8
LX1 DH2
C

PQ33 2 21 PR138 0_04 PC151 .1U_50V_06 PQ36

8
7
6
5 DL1 BST2 V1.5 1.5V
6mm PD12 RSS090N03 4 RSS090N03 3/15
PC140 PR140
+
SM240A PC112 .1U/50V_06 7 SC1485 18 PR136 10K_1%_04 PJ7
+1.5V, +1.05V

1
2
3
BST1 ILIM2
PC102 4 PL8 220U/2V_D2
100P_04 11K_1%_04 470U/2.5V_V 26 19 1 2 6A 1 2
A

3
2
1

FBK1 LX2
2.5U_7*7*3.5
24 16 PC104 PC108 8mm

C
5
6
7
8
VOUT1 DL2 + +
8 12 PD13 PR104 PC123
EN/PSV2 FBK2
4 SM240A *470U/2.5V_V
22 10 20K_1%_04 100P_04

1
2
3
EN/PSV1 VOUT2
PR141 PQ35

A
SYS5V RSS090N03
10K_1%_04

AGND1

AGND2

PGND1

PGND2
PR103
PR102
SGND1 10K_1%_04

28

14

15
10K_04 PU6
D

SGND2
PC122
DD_ON# G PQ39 SGND1 SGND2
[23,24] DD_ON#
2N7002W .1U_04 PR142 PR119
S

SGND2 0_06 0_06

SGND1 SGND2
PR114 47K_04
SYS5V 3/15
D

PQ41 PC124
PR113 100K_04 G 2N7002W
3/15 .1U_04 5VS 2.5VS
S

3/15 PU5
PQ51 CM1117CM223
D

2N7002W
1A
D

Gnd/Adj

PC141 3 2
PQ42 G Vin Out
SUSB# G TEST [21,23,24]
2N7002W *1U_06
S

[12,19,23,24] SUSB#
PC100 PR98
S

PIN 100_1%_04
1

C609 4.7U/10V_08 4=FLOATING PC94

.1U_04(R) SGND1 10U/25V_12

PR99
3/15 100_1%_04

1.05VS [2,3,4,5,6,8,11,13]
1.5V [24]
2.5VS [6,10]
3VS [2,4,5,6,9,10,11,12,13,14,15,16,18,20,21,24]
3V [11,12,13,14,16,17,20,21,23,24]
SYS5V [24,25]
VDD5 [14,19,20,21,24]
VIN [10,20,21,23,24,25]

+1.5V, +1.05V B - 23
 Schematic Diagrams

+1.8V, +0.9V

VIN 5V

A
P R77 PR 74
P D 10
1.5M_06 10_ 06
S C S5 51V
P U1 PR 19 *100K_ 04

C
+VD D Q PR 71 10 _06 3 7 3V
VD DQS PGD

PC 30 PR22 PC 82 PC 27
2
100p _04 2.2K_1%_ 06 1U _06 1U _06 TON

VI N
6 PR21 0_06
8 FB 24 PC 81 P C80 P C 14
PR70 10_0 6 RE F BST
9 P C 17 10U_ 25V_12 10U _25V _12 . 1U _50V _06
CO MP

5
6
7
8
PR7 2
PC 18 0_06 . 1U _0 4 PQ 9
PR 75 PR28 23 4 R SS 090N 03
DH
B.Schematic Diagrams

*0. 1U _0 4

1
2
3
10_0 6 10K_1 %_ 06 10 PR73 +VD DQ 5/16
VTTS 7.15K_ 1% _06 3/15
5
VC CA ILI M
21 5 /16 PL3 6A
PR 20 2.5U _7*7*3.5 P J2
PC 28 PC19 P C26 PC 29 22 1 2
LX 1.8V
10_06
1U _0 6 . 068U _06 1000p_06 1U _06 19 O PE N_8A
DL
VSSA
Sheet 23 of 29
4 P C 76 PC 75 P C1 3 PC11
VSSA + +

C
PJ 3 14 1 EN _1. 8V 3 30U_3V _V *3 30U _3V _V .1U_ 04 . 01U _ 04
3A VTT E N/ PSV

5
6
7
8
0.9 VS 2 1 15 PD2
VTT

+1.8V, +0.9V 11 VTTEN PQ 28

O PE N_3A 12 VTTEN 4 R SS 090N 03 S M340A
+VD DQ VD DP2
13 20 5V
VD DP2 VD DP1

1
2
3

A
PR7 6 0_ 06
P R18 PC21 PC 20 PC 1 0 P C12 16 PC1 5 VSSA
+ +
17 PG ND 1 18 5 /16
20K_ 1%_06 150U_ 4V_B *15 0U _4V_ B *10U _10V_0 8 * 10U_ 10V _08 PG ND 2 PGND 1 1U_ 06
S C486

P D8 VA VIN1 PR23 4 7K_04 V TTEN

5V
PR 32 47K _04 EN _1.8V C A
5V
A C PQ11

D
PQ 12 S CS 140P PC 31
D
PC2 4 VIN PD5 SC S140 P
P R56 PQ15 PR 29 100K_0 4 G . 1U _04
PR 24 100K _04 G . 1U _04 2SB1198K
[22,24] D D _O N# VDD 3

S
2N 7002W E C A C 3/15 2N7002W
S

1 0K_04
PD6 SC S140 P PQ13 PQ52

D
2N 70 02W

B
PW R _SW# PR 39
[1 9] PW R _SW#
10 0K_04 [ 12,19 ,22,24] SU SB# G G TES T [ 21 ,22,24]

S
PQ19 PR 51 10K_04 2N7 002W
2N 7 002 W G
PQ 22 3/15

D
S
2N 7002W
PR49 PQ 20
PW RS G 2N 70 02W G DD _O NH
[20] PWR S DD _ON H [24]

S
2 00K_04
PC 56 PR50
3/8 .1U _04 100K_04
COLDER

0.5 V 1. 8V [ 5,8,9]
0. 9VS [ 10]
V IN1 [ 24]
PR 78 0(0603) C A 3V [ 11, 12,13 ,14,16,1 7,2 0, 21 ,22,24]
PCN 1 0.9VS 5V [ 13, 16,19 ,21,24]
PF 2 1. 1A(R) PD9 SC S 140 P
1 V DD 3 [ 2,10,11, 14, 19,20 ,24 ,25]
0.5A VA [ 25]
2 V IN [ 10, 20,21 ,22,24,2 5]
H EA DE R 2 PC87

0.1U F

hexainf@hotmail.com
B - 24 +1.8V, +0.9V
 Schematic Diagrams

VDD3 VDD5
VIN 1

R U N /S S2
5/17
PR 123 10_04
PR 110 0_04(R )
5V
PR 122 10_04
SYS 15V PR 115

VD D 3 6 3V 1M_04 3/15 SY S5V VD D 5

5

32

29
PR 5 7 3A 2 4 3A PU 7 PR 116 0_06 PL 9 P R 101 4A PJ 8 4m m
1 PC 1 33 .01U _ 06 28 27 1 2 1 2

NC

NC
1M_ 04 P Q23 R U N /SS1 PGO OD
N TGS 4141N PC 14 2 180P_04( R ) PC 134 30 26 4. 7U _7*7*3 .5 10m _12
SENSE1+ TG1

5
6
3/15 P R 109 + PC 119 P C 120
PR9 6 PR 126 105K_1% _04 1000P _04 31 25 PC 11 6 .1U _ 50V_ 06 8
EN _15V SENSE1- SW1 PD1 4 PQ37B 150U /6.3V_D . 1U _04
E N _15V PR 127 2 0K_1%_04 1 24 C A 3 SP8K10S
0 _04 PQ31 PR 128 0_ 04(R ) VOSEN SE 1 BOO ST1 1 0_04
I NTVCC 2

D
P C 57 2N7 002W PR 129 0_ 04 0V:220KHz 2 23 RU N /SS 2 S CS551V PQ 37A
PLLF LTR VI N

2
1

4
PC 58 5V:640KHz SP 8K10S
2200 P_04 . 01U _04(R) G DD _ON # PC143 . 01U_ 04 3 22
PLLIN B G1
VIN

S
4 21 P C 125
FCB EXTV C C
PR 145 15K_0 4 PC 14 6 220P_04 5 20 PC 117 PC 118 . 1U _50 V_06 PC9 3 PC 98 PC 99 PC 106 P C 107
I TH 1 IN TV C C .1U_5 0V_0610U /2 5V_1210U/ 25V_1 210U /25V_1210U / 25V_ 12
PC1 45 30P_ 04(R ) 6 19 4. 7U _10 V_08
SGN D PG N D 1U _10V_06

4
VD D 5 6 5V 7 18

B.Schematic Diagrams
3.3VOU T B G2

1
2
5 PR 133 15K_0 4 PC 14 9 220P_04 P D16 3/15 3
3A 2 4 3A 8
I TH 2 BOO ST2
17 C A
1 PC1 47 30P_04(R ) PQ34B
PQ4 6 9 15 PC 126 SC S551V 8 SP8K10S
NTG S4141 N PR 132 20K_1 %_04 VOSEN SE 2 SW2 .1 U_50V _06 PQ34A 3/15
3

6
5
11 14 SP8K1 0S SY S3V VD D 3

7
PR 1 47 SENSE2- TG2 PR 1 18 0_0 6 PL7 PR 100 PJ 4 4m m
4A
SGN D 4 12 13 1 2 1 2

NC

NC
Sheet 24 of 29
EN _15V SENSE2+ R U N/ SS2
0_04 PQ 47 PC 13 5 LTC372 8LXCU H 4. 7U _7*7*3.5 1 0m _12 P C 95

10

16
D

PC 155 2N 7002W P C 148 PR130 1000P _04 PC1 01

+
PR 143 63 .4K_1%_04 . 1U _04
.01U_04(R ) G D D _ON # PC 144 PR 1 44
0_04 (R ) 0 _04
100 0P_04(R )
PR 124 1 0_04
150U/ 4V_B
VDD3 VDD5
S

. 01U_04
PR 131 1 0_04

SG N D4 IN TVC C 2

R UN / SS 2 PR 117 1M_0 4 PJ9 C A

SY S5V
1 2 JU MP
PC 13 6 PC 127 P D 17 SC S 355V
VD D 5 6 5VS
5 . 01U_06 .01U _ 06 A C SY S10V
VD D 5 2 4
PR 148 1 S GN D 4 P D 18 SC S 355V
PQ48 SGN D4 PC 128
PR149 N TGS41 41N 10U /2 5V_12
3

0_04 C A
SY S5V
D

PC 157 PC 154 P C156 PC 137 P D 20 SC S 355V

10K_0 4 PQ49
G 2N 7002W . 01 U _04(R.1U_
) 04 1 0U /1 0V_08 PQ43 .01U _06 A C SY S15V

E
DTA 114EU A
S

PQ5 0 P D 21 SC S 355V
D

D D_ON# B PC 150
[22,2 3] D D_O N #
SU S B# G 2N7 002W 1U /25V_08
[1 2,19, 22,23] SU SB#

C
VD D 3 6 3VS PQ45 P Q44
D

D
S

5 2N7 002W 2 N700 2W DD _O NH

2 4 D D _ON H [23]
PR 97 1 DD _O N G G TEST
[19] D D _O N TEST [21, 22 ,23]
PQ25 PC 15 3 PR 146
S

S
N TGS41 41N
3

0_04 . 1U _04 20 0K_0 4

C612
D

+
PC 62 PC 60 P C61
PQ24 150U /6 .3V_3528
G 2N 7002W . 01 U _04(R.1U_
) 04 1 0U /1 0V_08
5/17 PR 13 5 1M_04 PR 134 10 0K_04 2 1
SY S5V
S

PJ10 2m m

S YS15 V 1. 5V 1.5V S VIN VIN

PL 10 VDD3 [2, 10,1 1, 14,19,20, 23,25]
VDD5 [14,19, 20,21,22]
* HC B32 16K-800T3 0 PC 158 PC 159 S Y S5V [22,25]
PR112 8 VDD 3 3VS 0. 1U _ 50V_ 06 0.1U _50V _06
S Y S3V
7 3
1M_04 6 2 PC 59 0. 1U _0 6 S Y S10V
5 1 VIN VI N S Y S15V [10]
PR 111 3V [11,12, 13,14,16,17 ,20, 21 ,22,2 3]
EN _1 5VS PQ38
R SS090N03 5V [13,16, 19,21,23]
3 VS [2, 4, 5,6 ,9,10, 11,12,13, 14,15, 16,18,2 0, 21]
4

PC121 0_04 PC 160 PC 161 5 VS [10,13, 14,16,18,19 ,20, 22 ]

0. 1U _ 50V_ 06 0.1U _50V _06 1 .5VS [3, 6, 11 ,13,16]
D

2200P _04 PC 110 PC 138 P C129 V IN 3V S

1 .5V [22]
PQ40 V IN 1 [23]
G 2N70 02W . 01 U _04(R.1U_
) 04 1 0U /1 0V_08 PC 63 0. 1U _06 VIN VI N
V IN [10,20, 21,22,23,25 ]
S

PC 130
5/16 PC 162 PC 163
. 1U _06 0. 1U _ 50V_ 06 0.1U _50V _06

5/16

VDD3 VDD5 B - 25
 Schematic Diagrams

AC IN & CHARGER

VB
VIN 8
3 7
2 6
1 5
3/16 PL11
PD 22 3/15 3/20 PQ8

4
VA SBM1040 SI4835BD Y PC 74 PC 9
VA
J _D C IN 1 H CB4 51 6KF -T30 PQ7 A
PL1 A2 SP8 K10S 3/15 . 1U _50 V_ 06
2 PL2 10 U_ 2 5V_12
1
A1 CPR 64 30m _ 20 1 7 1 2
2 H CB4 51 6KF -T30 4. 7U _ 7* 7* 3. 5
GN D 1 PR14 3/15 PR 66
GN D 2

5
6
3/16 30 m_ 2 0

8
2 DC -G2 1 3- B2 00 PC 6 5 PC 64 1 00 K_ 1%_ 0 4 3/20 PC 7 PC 66
PR 150 PC 1 PR 69 PC 67
.1 U_50V_06 . 1U _ 50 V_ 06 .1U _5 0V_ 06 PC 6 1 0U / 25V_ 1 2 PR 16 3 1 0U _ 25 V_ 1 2
10K_ 08 0 _04 * 10 U _2 5V_ 12
PR15 10U/ 25 V_12 0 _04 PQ7 B

4
SP8 K1 0 S
20K_1%_0 4

PC 78 .1 U_50V_06
B.Schematic Diagrams

PR 2 0_0 4 PC 77 1U _ 25 V_ 06

A
3/15
SGN D 6
PD 1
SGN D6
SC S551V

28 C
27
26
25
24
23
22
Sheet 25 of 29 PU 4

OU T- 2
PGN D
OU T -1

XAC OK
VS
VB
CB
1 21 C TL
VCC C TL
2 20

AC IN & CHARGER AC OK
3
4
5
-I NC 1
+IN C1
ACI N
ACOK
GN D
VR EF
RT
CS
19
18
17
PR 67
PC 72
3 9K_ 1%_ 04
. 22 U _0 6
6 16
7 C VM OU TD 15

OU T C 2
+IN E1 - IN E3

F B12 3
+I N C2

+IN E2
-I NC 2
3/16

-IN E1

-IN E2
PR 58
PR61
36 .5 K_ 1% _0 4 1 00 K_ 1% _0 4 SGN D 6
PR 62

10
11
12
8
9

13
14
30K_1%_04 MB39 A11 9
PC 69
TOTAL_ C UR
[1 9] TOTAL _C U R
E C C TL PC70 2 20 0P _ 04
VI N C H G_ C U RSEN
[1 9] C H G_C U R SEN
PQ6 6800P_04

D TA114EUA PC 8 PC 71 PR 6 PR 11

B
3/16 SGND 6 100K_1%_0 4 PR59 PR 10
. 1U _5 0 V_ 06 68 00 P_04 3 00 K_ 1% _0 4

C
PR 3 10K_1 %_0 4 33K_04
B PQ5
SYS5V 47K_1%_04 PR 60
PR9 D TC 1 14EU A 10 K_1 %_0 4
10 K_0 4 PR4
E

11 3K_1%_ 04

PR 63
VB E C BAT1_VOLT
BAT1 _VO LT [ 19 ]
30K_1%_04
PQ1
SY S5V D TA11 4 EU A

B
3/16 PR65 PC 73
3/20

D
6. 8K_ 1%_ 04 .1 U_0 4
PR1 5 2 *0 _04 PQ3
AC OK G
SY S5V
PR 151 2 N70 02 W

S
100K_04 PR 12 10K_04 AC _IN #
VD D 3 AC _IN # [1 9 ]

D
PQ53
G 2 N70 02 W
PR 1 1 M_04 G PQ2
D

S
VA
PJ11 2N 7 002 W
VIN [10 ,20 ,21 ,2 2 ,23 ,2 4 ]

S
PQ54 2 1
C H G_EN G VD D3 [2, 10,1 1, 14 ,19, 20 ,2 3, 24 ]
2 N 70 0 2W PR7
[ 19 ] C HG_ EN VIN [10 ,20 ,21 ,2 2 ,23 ,2 4 ]
2m m
VA [23 ]
S

20 0 K_ 04
SY S5 V [22 ,24 ]

Charge Current 2A
Charge Voltage 16.8V
Total Power 60W
PF1
VB
TOTAL_CUR = 0.75V / 1A
J _MBAT1
5A CHG_CURSEN = 0.735 / 1A
SMC _BAT1 1
[19] SMC _BAT1 2
SMD _BAT1
[19] SMD _BAT1 3
BAT1 _D ET
[19] BAT1_ D ET 4
PC3 PC 2 PC 4 PC6 8 PC5
5
30 P_0 4 30 P_ 04 3 0P_ 04 10U /2 5V_ 12 10 U _2 5 V_12 BTC - 05 AL 0

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B - 26 AC IN & CHARGER
 Schematic Diagrams

RJ11 & TV OUT & MDC BOARD

RJ11 TV OUT
TL1 FCM2012K-241T06
DACA_C
TC1
TR1 TC2

B.Schematic Diagrams
68P 68P
150_1%

MODEM GND_T

TJMDC1 TJRJ1 TL2 FCM2012K-241T06

1
2
TL3
TL4
FCM2012V-121
FCM2012V-121
1
2 XP
XN
3
4
DACB_C
TR2
TC3
TC4 7
4
TSVIDEO1

3
Sheet 26 of 29
68P 68P 6 5
85205-02001 PJS-02BT3
PIN3=TZ1901
150_1% 2 1
RJ11 & TV OUT &
PIN4=TZ1902 GND_T

TJMDC1
DACC_C
GND_T

TL5 FCM2012K-241T06
C10863-107B5
MDC BOARD
TC5
1 2 TR3 TC6 GND_T

68P 68P
150_1%

GND_T 5/16 TH6 TH5 TH2 TH3 TH4 TH7 TH1

H7_0D2_3 H7_0D2_3 H7_0D2_7 H7_0D2_7 H7_0D2_3 H7_0D2_7 H7_0D2_3

TJMDC2
DACA_C 1

MDC
DACA_C DACB_C 2
DACB_C
DACC_C 3 GND_T GND_T GND_T GND_T GND_T GND_T GND_T
DACC_C
TC7 .1U_04 4
TJMDC3 5
TAC_SDOUT 6
TAC_SDOUT
12 11 7
3V_T TAC_SYNC 8
TAC_SYNC TAC_SDIN1
2 1 9
TAC_SDIN1 TAC_RST# 10
TAC_RST#
TJMDC3 11
1 2 TAC_BITCLK 12
GND RESERVED TAC_BITCLK
3 4
TAC_SDOUT Azalia_SDO RESERVED
5 6 3/22 87151-1207G
GND 3.3V Main/aux 3V_T
7 8 TC8 .1U_04
GND_T

TAC_SYNC Azalia_SYNC GND

9 10 GND_T
TAC_SDIN1 Azalia_SDI GND
11 12
TAC_RST# Azalia_RST# Azalia_BCLK
88020-12001 TR4

GND_T 0_04

TAC_BITCLK

TC9

22P_04(R)

RJ11 & TV OUT & MDC BOARD B - 27

 Schematic Diagrams

SWITCH & LED BOARD

+3.3V_L

LR15 2.7K

LU1
LC2 1 3 LID_SW#_10
VS Q
6 4
0.01U 2 PRG GND 5
GND GND
TLE 4917

GND_L
GND_L
B.Schematic Diagrams

3/20

A C LR10 220_08 PC_LED_WO_C SCROLL_LED# CAP_LED# VIN_L

+5VS_L

C
LD7 SML_010MT_G LQ5 LQ2
LJSW1
B SCROLL_LED_C B CAP_LED_C

Sheet 27 of 29 LR4 10K_04 LR5 10K_04 PW RS_10 1

E
2N3904 2N3904 2
3
SCROLL_LED# +3.3V_L LI D_SW#_10 4 LJSW1
A C LR8 220_08

SWITCH & LED LD4

A
LD3
SML_010MT_G
C LR13
SML_010MT_G
220_08 CAP_LED# GND_L GND_L +5VS_L
3/21 PC_LED_WO_C
5
6
7
1

NUM_LED# 8

BOARD
A C LR14 220_08
SC ROLL_LED_C 9
LD2 SML_010MT_G
NUM_LED# CAP_LED_C 10

C
NUM_LED_C 11
LQ1
HD_LED_C 12
NUM_LED_C WEB0#_10 13
B
WEB1#_10 14
LR6 10K_04

E
HD_LED_C WEB2#_10 15
C A LR1 220_08 2N3904
+5VS_L +3.3V_L VIN_L DVD_ON _B 16 20
LD1 SML_010MT_G
17
18
GND_L GND_L 20MIL 19
20
C592 C593 C594 C591 C595 C596 C599 C597 C598
87151-2007G
0.1U_04(R) 0.1U_04(R) 0.1U_04(R) 0.1U_04(R) 0.1U_04(R) 0.1U_04(R) GND_L
0.1U_04(R) 0.1U_04(R) 0.1U_04(R)

GND_L GND_L GND_L

E C DVD_ON_B
VIN_L
LQ6 2SB1198K

B
LR12 100K LR9 100K

C A C A
LSD2 1SS355(R) LD6 1SS355
VIN_L
LSWEB1 LSWEB2 LSWEB3 LSW1 LH1 LH2 LH4 LH3
H6_0D2_2 H6_0D2_3 H6_0D2_2 H6_0D2_3
1 3 WEB1#_10 1 3 C A WEB0#_10 1 3 C A WEB2#_10 1 3 PWRS_10
LSD1 1SS355(R) LD5 1SS355
2 4 2 4 2 4 2 4 LC1
LR7 0
HCH STS-05-A HCH STS-05-A HCH STS-05-A HCH STS-05-A 0.1U

GND_L GND_L GND_L GND_L GND_L GND_L GND_L

GND_L

Email WWW AP / DVD

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B - 28 SWITCH & LED BOARD
 Schematic Diagrams

USB & PHONE JACK BOARD

AJAUDIO1
5

LINE-R_C AL2
LINE_SENSE_C
HCB2012K-500T40
4
3
LINE IN 4 BLUE
6
LINE-L_C AL3 HCB2012K-500T40

AC3 AC1
2
1
2SJ-S351-S02
(SURR)
330P 330P

GND_A

AJAUDIO2
5
4

SPD IF -OUT_C AL4 FCM1608K-121T06

3
6
2
SPDIF 3 BLACK
AC4
1
2SJ-S351-S02 OUT
680P

GND_A

B.Schematic Diagrams
AJAUDIO3
5
MIC_SENSE_C 4
LFE_C

MIC_C
AL9

AL6
FCM1608K-121T06

FCM1608K-121T06
3
6
2
MIC IN 2 PINK
AC9 AC14
1
2SJ-S351-S02 (CENTER)
680P 680P
LINE-R_C
AJADJ1 Sheet 28 of 29
1

GND_A
LINE-L_C

SPDIF-OUT_C
2
3
4
AJADJ1
1
USB & PHONE
LFE_C 5

HP_SENSE_C AJAUDIO4
MIC_C

JD_SENSE_C
6
7
8
JACK BOARD
AMP_MU TE_C 5 AMP_MUTE_C 9
4 10
MSPKR_C

MSPKL_C
AL7

AL8
HCB2012K-500T40

HCB2012K-500T40
3
6
2
SPEAKER OUT 1 GREEN MSPKR_C
MSPKL_C
11
12
12

AC12 AC11 AC13

1
2SJ-S351-S02 (FRONT) GND_A
85203-1202L

680P 680P 0.1U

AJAUDIO1,AJAUDIO2, AJAUDIO3, AJAUDIO4

GND_A

5
4 1
3
2
6
LINE_SENSE_C AR2 10K_04 SOLDER SIDE VIEW
MIC_SENSE_C AR3 20K_04
HP _SE NSE _C AR4 39.2K_04 JD_SENSE_C

AJUSB2
AJUSB1
VDD5_A CIR_RX_C 1
1
2
USBVCC2_A 3
USB2-_C 4
USB2+_C 5
6 8
GND_A

+ USBVCC2_A 7
AC5 AC8 C590 0.1U_04
8
0.1U 100U/16V(D) 85205-08001
AC6 AC7
GND_A AJUSB1 2/14
GND_A AL5 HCB3216K-800T30 1 0.1U 0.1U
AL11 V+
1 2 2 AH2 AH1 AH4
USB2-_C DATA_L H5_0D2_2 H5_0D2_7 H6_3D2_8 AU1
4 3 3 CIR_RX_C O
USB2+_C DATA_H GND_A
PLW3216S161SQ2 G
GND1

GND2

4 AR1 100_08(R) V
GND VDD5_A
C.IR
USB-04RS1 AC10 AC15 IRM-V038/TR1(R)
5

GND_A GND_A GND_A

GND_A
0.1U(R) 4.7U_08(R)

GND_A

GND_A

USB & PHONE JACK BOARD B - 29

 Schematic Diagrams

CLICK BOARD

CLICK BOARD
+5V_C
B.Schematic Diagrams

C C5 CC 6 CC7

+5V_C
0.1U(R ) 0.1U(R ) 0.1U (R)
Sheet 29 of 29
CLICK BOARD C R2 CR 3 GND_C

C JTP 2
10K 10K
12
12 10MIL
11 +5V_C
11 +5V _C +5V _C
10 TP DATA
10 9
9 8 C J TP 1
8 7
GND_C TP CLK 10MIL 1
7 6 C R4 C R1 1
6 2
5 CC 2 TPD ATA 2
5 10K 10K 3
4 C C1 C C3 C C8 C SW 2 C SW 1 TPC LK 4 3
4 3 SW _L 4
C C4
3 2 10MIL 1 3 1 3
2 SW _L SW _R 85201-04051
1 120P 0.1U
1 SW _R
120P 120P 0.1U( R) 2 4 2 4

87152-12071 HC H STS-05-A HC H STS-05-A CJTP1

GND_C GND_C
GND_C GND_C
4 1
CJTP2

1
L R
12

C H1 CH 3 C H2
H 6_0D 2_3 H6_0D 2_3 H 6_0D 2_3

GND_C GND_C GND_C

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