ZQX Ddr3 BDW Ult r1b 0903 Acer Aspire r3-471t

5 4 3 2 1
ZQX_DDR3 BDW ULT SYSTEM BLOCK DIAGRAM 01

Dual Channel DDR III VRAM
DDR3L-SODIMM 1066/1333/1600 MHZ GPU DDR3
Memory Down Broadwell ULT 15W PCIE-5
N15S-GT P21
D
P15 N15V-GM BOM D
MCP 1168pins PCI-E

TX/RX
x4
2Rx16 IMC IV@ : iGPU
DC+GT3 Display X'TAL 27MHz EV@ : Optimus
CLK
40 mm X 24 mm
P16~P21
TDI@ : Touch pad I2C
SATA0
Max. 4G P14 SATA - HDD TSU@ : Touch screen USB
P26
SATA
EDP
eDP Conn.
TSI@ : Touch screen I2C
eDP
P23 SP@ : Special part
TPM@ : TPM
TPMS@ : TPM IC OPTION
DDI1 GT@ : N15S-GT
DP HDMI Conn. P25 GM@ : N15V-GM
GMS@ : N15V-GM
USB2-0 USB3-1 USB3 Port
USB3.0/2.0
USB2-2 MB side
CCD(Camera) P28
Integrated PCH
P23
C C
USB2-5
Touch Screen(option)
P23
USB2.0
CLK
USB board
USB2-1,2 ,7 PCI-E x1 PCIE-4
USB2 IO I/O Board Conn.
P28 USB2-4
Mini CARD
WLAN+BT
X'TAL P27
32.768KHz
USB2 IO PCIE-3
RTL8111GS RJ45
P24
X'TAL 24MHz
10/100/1G P24
CLK
Card Reader P8 BATTERY RTC
P2~P13 X'TAL 25MHz
Azalia IHDA
SPI SPI ROM
B LPC B
P8
Universal jack
EC
Int. MIC ALC283 TPM(option)
DMIC Array
AUDIO CODEC IT8380 P26
P22 P30
Panel seosor board

Panel seosor board
Speaker*2 OCH1691WAD Image Sensor Fan Driver Gyro/eCompass/(Reserve)

P22
K/B Con. HALL SENSOR (PWM Type) G sensor Light Sensor
P29 P23 P32 P29
A A
Quanta Computer Inc.

PROJECT : ZQX
Size Document Number Rev
1B
Block Diagram
Date: Wednesday, September 03, 2014 Sheet 1 of 43
5 4 3 2 1
5 4 3 2 1
SP@ : i3-4010U i3-4020U i5-4210U

Haswell ULT (DISPLAY,eDP)
U28A HSW_ULT_DDR3L
02
D D
eDP Panel
C54 C45 EDP_TXN0
[25] INT_HDMITX2N DDI1_TXN0 EDP_TXN0 EDP_TXN0 [23]
C55 B46 EDP_TXP0
[25] INT_HDMITX2P DDI1_TXP0 EDP_TXP0 EDP_TXP0 [23]
B58 A47 EDP_TXN1
HDMI
[25] INT_HDMITX1N DDI1_TXN1 EDP_TXN1 EDP_TXN1 [23]

C58 B47 EDP_TXP1
[25] INT_HDMITX1P DDI1_TXP1 EDP_TXP1 EDP_TXP1 [23]
B55
[25] INT_HDMITX0N DDI1_TXN2
A55 C47
[25] INT_HDMITX0P DDI1_TXP2 EDP_TXN2
[25] INT_HDMICLK- A57 C46
B57 DDI1_TXN3 EDP_TXP2 A49
[25] INT_HDMICLK+ DDI1_TXP3 DDI EDP EDP_TXN3 B49
C51 EDP_TXP3
C50 DDI2_TXN0 A45 EDP_AUXN
DDI2_TXP0 EDP_AUXN EDP_AUXN [23]
C53 B45 EDP_AUXP
DDI2_TXN1 EDP_AUXP EDP_AUXP [23]
B54
C49 DDI2_TXP1 D20 EDP_RCOMP R229 24.9/F_4
DDI2_TXN2 EDP_RCOMP +VCCIOA_OUT
B50 A43 DP_UTIL R551 *0_4 PCH_BRIGHT
A53 DDI2_TXP2 EDP_DISP_UTIL
B53 DDI2_TXN3
DDI2_TXP3
eDP_RCOMP
R552 *0_4
Trace length < 100 mils
C Trace width = 20 mils C
1 OF 19 Trace spacing = 25 mils
+3V
HSW_ULT_DDR3L
U28I
PCI_PIRQA# R184 10K_4
PCI_PIRQB# R142 10K_4
PCI_PIRQC# R141 10K_4
PCI_PIRQD# R491 10K_4
[23] PCH_BRIGHT PCH_BRIGHT B8 B9 HDMI_DDCCLK_SW [25]
PCH_BLON A9 EDP_BKLCTL DDPB_CTRLCLK C9
[23] PCH_BLON EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA HDMI_DDCDATA_SW [25]
C6 D9
[23] EDP_VDD_EN EDP_VDDEN DDPC_CTRLCLK D11
DDPC_CTRLDATA
+3V
PCI_PIRQA# U6 +3V
PCI_PIRQB# P4 PIRQA/GPIO77 C5 TPD_INT#_D R159 10K_4
B PIRQB/GPIO78 +3V DDPB_AUXN B
PCI_PIRQC# N4 +3V B6
PCI_PIRQD# N2 PIRQC/GPIO79 DISPLAY DDPC_AUXN B5
PIRQD/GPIO80 +3V DDPB_AUXP
PCI_PME# AD4 +3V_S5 A6 DGPU_SELECT# R488 10K_4
TP94 PME PCIE DDPC_AUXP
TPD_INT#_D U7 +3V DGPU_SELECT#,0=defalt,1=iGPU
DGPU_SELECT# L1 GPIO55
GPIO52 +3V
BOARD_ID4 L3 +3V C8
[10] BOARD_ID4 GPIO54 DDPB_HPD INT_HDMI_HPD [25]
BOARD_ID1 R5 +3V A8
[10] BOARD_ID1 GPIO51 DDPC_HPD
BOARD_ID2 L4 +3V D6
[10] BOARD_ID2 GPIO53 EDP_HPD EDP_HPD [23]
R537
9 OF 19 100K_4
+3V
Add 10/31
A A
2
3 1 TPD_INT#_D
[28,29] TPD_INT#
Q19 PROJECT :ZQX
2N7002K Size Document Number Rev
1B
Haswell 3/5 (DDI/eDP)
5 4 3 2 1
5 4 3 2 1
Change Data and DQS to interleave.
Haswell ULT
U28C HSW_ULT_DDR3L
(DDR3L)
U28D
Haswell Processor (DDR3)
HSW_ULT_DDR3L
03
[14] M_A_DQ0 M_A_DQ0 AH63 AU37
M_A_CLK0# [14]
M_A_DQ1 AH62 SA_DQ0 SA_CLK#0 AV37 M_A_DQ32 AY31 AM38
[14] M_A_DQ1 SA_DQ1 SA_CLK0 M_A_CLK0 [14] [14] M_A_DQ32 SB_DQ0 SB_CK#0 M_B_CLK0# [15]
M_A_DQ2 AK63 AW36 M_A_DQ33AW31 AN38
[14] M_A_DQ2 SA_DQ2 SA_CLK#1 M_A_CLK1# [14] [14] M_A_DQ33 SB_DQ1 SB_CK0 M_B_CLK0 [15]
M_A_DQ3 AK62 AY36 M_A_DQ34 AY29 AK38
[14] M_A_DQ3 SA_DQ3 SA_CLK1 M_A_CLK1 [14] [14] M_A_DQ34 SB_DQ2 SB_CK#1 M_B_CLK1# [15]
[14] M_A_DQ4 M_A_DQ4 AH61 [14] M_A_DQ35 M_A_DQ35AW29 AL38
M_B_CLK1 [15]
M_A_DQ5 AH60 SA_DQ4 AU43 M_A_DQ36 AV31 SB_DQ3 SB_CK1
D [14] M_A_DQ5 SA_DQ5 SA_CKE0 M_A_CKE0 [14] [14] M_A_DQ36 SB_DQ4 D
[14] M_A_DQ6 M_A_DQ6 AK61 AW43
M_A_CKE1 [14] [14] M_A_DQ37 M_A_DQ37 AU31 AY49
M_B_CKE0 [15]
M_A_DQ7 AK60 SA_DQ6 SA_CKE1 AY42 M_A_DQ38 AV29 SB_DQ5 SB_CKE0 AU50
[14] M_A_DQ7 SA_DQ7 SA_CKE2 [14] M_A_DQ38 SB_DQ6 SB_CKE1 M_B_CKE1 [15]
M_A_DQ8 AM63 AY43 M_A_DQ39 AU29 AW49
[14] M_A_DQ8 SA_DQ8 SA_CKE3 [14] M_A_DQ39 SB_DQ7 SB_CKE2
M_A_DQ9 AM62 M_A_DQ40 AY27 AV50
[14] M_A_DQ9 SA_DQ9 [14] M_A_DQ40 SB_DQ8 SB_CKE3
M_A_DQ10 AP63 AP33 M_A_DQ41AW27
[14] M_A_DQ10 SA_DQ10 SA_CS#0 M_A_CS#0 [14] [14] M_A_DQ41 SB_DQ9
[14] M_A_DQ11 M_A_DQ11 AP62 AR32
M_A_CS#1 [14] [14] M_A_DQ42 M_A_DQ42 AY25 AM32
M_B_CS#0 [15]
M_A_DQ12 AM61 SA_DQ11 SA_CS#1 M_A_DQ43AW25 SB_DQ10 SB_CS#0 AK32
[14] M_A_DQ12 SA_DQ12 [14] M_A_DQ43 SB_DQ11 SB_CS#1 M_B_CS#1 [15]
M_A_DQ13 AM60 AP32 M_A_DQ44 AV27
[14] M_A_DQ13 SA_DQ13 SA_ODT0 TP46 [14] M_A_DQ44 SB_DQ12
M_A_DQ14 AP61 M_A_DQ45 AU27 AL32 M_B_ODT0
[14] M_A_DQ14 SA_DQ14 [14] M_A_DQ45 SB_DQ13 SB_ODT0 TP45
[14] M_A_DQ15 M_A_DQ15 AP60 AY34
M_A_RAS# [14] [14] M_A_DQ46 M_A_DQ46 AV25
M_B_DQ0 AP58 SA_DQ15 SA_RAS AW34 M_A_DQ47 AU25 SB_DQ14 AM35
[15] M_B_DQ0 SA_DQ16 SA_WE M_A_WE# [14] [14] M_A_DQ47 SB_DQ15 SB_RAS M_B_RAS# [15]
M_B_DQ1 AR58 AU34 M_B_DQ32 AM29 AK35
[15] M_B_DQ1 SA_DQ17 SA_CAS M_A_CAS# [14] [15] M_B_DQ32 SB_DQ16 SB_WE M_B_WE# [15]
M_B_DQ2 AM57 M_B_DQ33 AK29 AM33
[15] M_B_DQ2 SA_DQ18 [15] M_B_DQ33 SB_DQ17 SB_CAS M_B_CAS# [15]
[15] M_B_DQ3 M_B_DQ3 AK57 AU35
M_A_BS#0 [14] [15] M_B_DQ34 M_B_DQ34 AL28
M_B_DQ4 AL58 SA_DQ19 SA_BA0 AV35 M_B_DQ35 AK28 SB_DQ18 AL35
[15] M_B_DQ4 SA_DQ20 SA_BA1 M_A_BS#1 [14] [15] M_B_DQ35 SB_DQ19 SB_BA0 M_B_BS#0 [15]
M_B_DQ5 AK58 AY41 M_B_DQ36 AR29 AM36
[15] M_B_DQ5 SA_DQ21 SA_BA2 M_A_BS#2 [14] [15] M_B_DQ36 SB_DQ20 SB_BA1 M_B_BS#1 [15]
M_B_DQ6 AR57 M_B_DQ37 AN29 AU49
[15] M_B_DQ6 SA_DQ22 M_A_A[15:0] [14] [15] M_B_DQ37 SB_DQ21 SB_BA2 M_B_BS#2 [15]
M_B_DQ7 AN57 AU36 M_A_A0 M_B_DQ38 AR28
[15] M_B_DQ7 SA_DQ23 SA_MA0 [15] M_B_DQ38 SB_DQ22 M_B_A[15:0] [15]
[15] M_B_DQ8 M_B_DQ8 AP55 AY37 M_A_A1
[15] M_B_DQ39 M_B_DQ39 AP28 AP40 M_B_A0
M_B_DQ9 AR55 SA_DQ24 SA_MA1 AR38 M_A_A2 M_B_DQ40 AN26 SB_DQ23 SB_MA0 AR40 M_B_A1
[15] M_B_DQ9 SA_DQ25 SA_MA2 [15] M_B_DQ40 SB_DQ24 SB_MA1
[15] M_B_DQ10 M_B_DQ10 AM54 AP36 M_A_A3
[15] M_B_DQ41 M_B_DQ41 AR26 AP42 M_B_A2
M_B_DQ11 AK54 SA_DQ26 SA_MA3 AU39 M_A_A4 M_B_DQ42 AR25 SB_DQ25 SB_MA2 AR42 M_B_A3
M_B_DQ12 AL55 AR36 M_A_A5 M_B_DQ43 AP25 AR45 M_B_A4
[15] M_B_DQ13 M_B_DQ13 AK55 AV40 M_A_A6
[15] M_B_DQ44 M_B_DQ44 AK26 AP45 M_B_A5
M_B_DQ14 AR54 SA_DQ29 SA_MA6 AW39M_A_A7 M_B_DQ45 AM26 SB_DQ28 SB_MA5 AW46M_B_A6
[15] M_B_DQ14 SA_DQ30 DDR CHANNEL A SA_MA7 [15] M_B_DQ45 SB_DQ29 SB_MA6
[15] M_B_DQ15 M_B_DQ15 AN54 AY39 M_A_A8
[15] M_B_DQ46 M_B_DQ46 AK25 AY46 M_B_A7
M_A_DQ16 AY58 SA_DQ31 SA_MA8 AU40 M_A_A9 M_B_DQ47 AL25 SB_DQ30 SB_MA7 AY47 M_B_A8
[14] M_A_DQ16 SA_DQ32 SA_MA9 [15] M_B_DQ47 SB_DQ31 DDR CHANNEL B SB_MA8
M_A_DQ17AW58 AP35 M_A_A10 M_A_DQ48 AY23 AU46 M_B_A9
[14] M_A_DQ17 SA_DQ33 SA_MA10 [14] M_A_DQ48 SB_DQ32 SB_MA9
M_A_DQ18 AY56 AW41M_A_A11 M_A_DQ49AW23 AK36 M_B_A10
M_A_DQ19AW56 AU41 M_A_A12 M_A_DQ50 AY21 AV47 M_B_A11
[14] M_A_DQ20 M_A_DQ20 AV58 AR35 M_A_A13
[14] M_A_DQ51 M_A_DQ51AW21 AU47 M_B_A12
M_A_DQ21 AU58 SA_DQ36 SA_MA13 AV42 M_A_A14 M_A_DQ52 AV23 SB_DQ35 SB_MA12 AK33 M_B_A13
C [14] M_A_DQ21 SA_DQ37 SA_MA14 [14] M_A_DQ52 SB_DQ36 SB_MA13 C
M_A_DQ22 AV56 AU42 M_A_A15 M_A_DQ53 AU23 AR46 M_B_A14
[14] M_A_DQ23 M_A_DQ23 AU56 [14] M_A_DQ54 M_A_DQ54 AV21 AP46 M_B_A15
M_A_DQ24 AY54 SA_DQ39 AJ61 M_A_DQS#0 M_A_DQ55 AU21 SB_DQ38 SB_MA15
[14] M_A_DQ24 SA_DQ40 SA_DQSN0 M_A_DQS#0 [14] [14] M_A_DQ55 SB_DQ39
M_A_DQ25AW54 AN62 M_A_DQS#1 M_A_DQ56 AY19 AW30 M_A_DQS#4
[14] M_A_DQ25 SA_DQ41 SA_DQSN1 M_A_DQS#1 [14] [14] M_A_DQ56 SB_DQ40 SB_DQSN0 M_A_DQS#4 [14]
M_A_DQ26 AY52 AM58 M_B_DQS#0 M_A_DQ57AW19 AV26 M_A_DQS#5
[14] M_A_DQ26 SA_DQ42 SA_DQSN2 M_B_DQS#0 [15] [14] M_A_DQ57 SB_DQ41 SB_DQSN1 M_A_DQS#5 [14]
M_A_DQ27AW52 AM55 M_B_DQS#1 M_A_DQ58 AY17 AN28 M_B_DQS#4
[14] M_A_DQ27 SA_DQ43 SA_DQSN3 M_B_DQS#1 [15] [14] M_A_DQ58 SB_DQ42 SB_DQSN2 M_B_DQS#4 [15]
[14] M_A_DQ28 M_A_DQ28 AV54 AV57 M_A_DQS#2 M_A_DQS#2 [14] [14] M_A_DQ59 M_A_DQ59AW17 AN25 M_B_DQS#5
M_B_DQS#5 [15]
M_A_DQ29 AU54 SA_DQ44 SA_DQSN4 AV53 M_A_DQS#3 M_A_DQ60 AV19 SB_DQ43 SB_DQSN3 AW22 M_A_DQS#6
[14] M_A_DQ29 SA_DQ45 SA_DQSN5 M_A_DQS#3 [14] [14] M_A_DQ60 SB_DQ44 SB_DQSN4 M_A_DQS#6 [14]
[14] M_A_DQ30 M_A_DQ30 AV52 AL43 M_B_DQS#2 M_B_DQS#2 [15] [14] M_A_DQ61 M_A_DQ61 AU19 AV18 M_A_DQS#7
M_A_DQS#7 [14]
M_A_DQ31 AU52 SA_DQ46 SA_DQSN6 AL48 M_B_DQS#3 M_A_DQ62 AV17 SB_DQ45 SB_DQSN5 AN21 M_B_DQS#6
[14] M_A_DQ31 SA_DQ47 SA_DQSN7 M_B_DQS#3 [15] [14] M_A_DQ62 SB_DQ46 SB_DQSN6 M_B_DQS#6 [15]
M_B_DQ16 AK40 M_A_DQ63 AU17 AN18 M_B_DQS#7
[15] M_B_DQ16 SA_DQ48 [14] M_A_DQ63 SB_DQ47 SB_DQSN7 M_B_DQS#7 [15]
[15] M_B_DQ17 M_B_DQ17 AK42 AJ62 M_A_DQS0 M_A_DQS0 [14] [15] M_B_DQ48 M_B_DQ48 AR21
M_B_DQ18 AM43 SA_DQ49 SA_DQSP0 AN61 M_A_DQS1 M_B_DQ49 AR22 SB_DQ48 AV30 M_A_DQS4
[15] M_B_DQ18 SA_DQ50 SA_DQSP1 M_A_DQS1 [14] [15] M_B_DQ49 SB_DQ49 SB_DQSP0 M_A_DQS4 [14]
[15] M_B_DQ19 M_B_DQ19 AM45 AN58 M_B_DQS0 M_B_DQS0 [15] [15] M_B_DQ50 M_B_DQ50 AL21 AW26 M_A_DQS5 M_A_DQS5 [14]
M_B_DQ20 AK45 SA_DQ51 SA_DQSP2 AN55 M_B_DQS1 M_B_DQ51 AM22 SB_DQ50 SB_DQSP1 AM28 M_B_DQS4
[15] M_B_DQ20 SA_DQ52 SA_DQSP3 M_B_DQS1 [15] [15] M_B_DQ51 SB_DQ51 SB_DQSP2 M_B_DQS4 [15]
M_B_DQ21 AK43 AW57 M_A_DQS2 M_B_DQ52 AN22 AM25 M_B_DQS5
[15] M_B_DQ21 SA_DQ53 SA_DQSP4 M_A_DQS2 [14] [15] M_B_DQ52 SB_DQ52 SB_DQSP3 M_B_DQS5 [15]
M_B_DQ22 AM40 AW53 M_A_DQS3 M_B_DQ53 AP21 AV22 M_A_DQS6
[15] M_B_DQ22 SA_DQ54 SA_DQSP5 M_A_DQS3 [14] [15] M_B_DQ53 SB_DQ53 SB_DQSP4 M_A_DQS6 [14]
M_B_DQ23 AM42 AL42 M_B_DQS2 M_B_DQ54 AK21 AW18 M_A_DQS7
[15] M_B_DQ23 SA_DQ55 SA_DQSP6 M_B_DQS2 [15] [15] M_B_DQ54 SB_DQ54 SB_DQSP5 M_A_DQS7 [14]
[15] M_B_DQ24 M_B_DQ24 AM46 AL49 M_B_DQS3 M_B_DQS3 [15] [15] M_B_DQ55 M_B_DQ55 AK22 AM21 M_B_DQS6 M_B_DQS6 [15]
M_B_DQ25 AK46 SA_DQ56 SA_DQSP7 M_B_DQ56 AN20 SB_DQ55 SB_DQSP6 AM18 M_B_DQS7
[15] M_B_DQ25 SA_DQ57 [15] M_B_DQ56 SB_DQ56 SB_DQSP7 M_B_DQS7 [15]
M_B_DQ26 AM49 AP49 M_B_DQ57 AR20
[15] M_B_DQ26 SA_DQ58 SM_VREF_CA +VREF_CA_CPU [15] M_B_DQ57 SB_DQ57
M_B_DQ27 AK49 AR51 M_B_DQ58 AK18
[15] M_B_DQ27 SA_DQ59 SM_VREF_DQ0 +VREFDQ_SA_M3 [15] M_B_DQ58 SB_DQ58
[15] M_B_DQ28 M_B_DQ28 AM48 AP51
+VREFDQ_SB_M3 [15] M_B_DQ59 M_B_DQ59 AL18
M_B_DQ29 AK48 SA_DQ60 SM_VREF_DQ1 M_B_DQ60 AK20 SB_DQ59
[15] M_B_DQ29 SA_DQ61 [15] M_B_DQ60 SB_DQ60
M_B_DQ30 AM51 M_B_DQ61 AM20
M_B_DQ31 AK51 M_B_DQ62 AR18
M_B_DQ63 AP18
[15] M_B_DQ63 SB_DQ63
B B
3 OF 19 4 OF 19
+VREF_CA_CPU
+VREF_CA_CPU [14]
+VREFDQ_SA_M3
+VREFDQ_SA_M3 [14]
+VREFDQ_SB_M3
+VREFDQ_SB_M3 [15]
Power tracking
A A

PROJECT : ZQX
Haswell 2/5 (DDR3 I/F) 1B

5 4 3 2 1
5 4 3 2 1
04
H_PECI (50ohm)
Haswell ULT (SIDEBAND)
Route on microstrip only
D
Spacing >18 mils D
Trace Length: 0.4~6.125 iches
H_PWRGOOD (50ohm)
Trace Length: 1~11.25 inches HSW_ULT_DDR3L
U28B
CPU_PLTRST# (50ohm)
Trace Length: 10~17 inches PROC_DETECT D61
TP116 PROC_DETECT
CATERR# K61 MISC
TP49 N62 CATERR J62
[29] H_PECI H_PECI XDP_PRDY# XDP_PRDY# [13]
PECI PRDY K62 XDP_PREQ#
PREQ XDP_PREQ# [13]
E60 XDP_TCK0 XDP_TCK0 [8,13] TCK,TMS
PROC_TCK E61 XDP_TMS_CPU
JTAG PROC_TMS XDP_TMS_CPU [13] Trace Length < 9000mils
[29,30,34] H_PROCHOT# H_PROCHOT# R569 56_4 H_PROCHOT#_R K63 E59 XDP_TRST# XDP_TRST# [8,13]
PROCHOT THERMAL
PROC_TRST F63 XDP_TDI_CPU
PROC_TDI XDP_TDI_CPU [13]
F62 XDP_TDO_CPU
PROC_TDO XDP_TDO_CPU [13]
H_PWRGOOD_R C61
PROCPWRGD PWR
J60 XDP_BPM#0
BPM#0 H60 XDP_BPM#0 [13]
XDP_BPM#1
BPM#1 XDP_BPM#1 [13]
H61 XDP_BPM#2 BPM#[0:7]
BPM#2 H62 TP114
XDP_BPM#3 Trace Length 1~6 inches
BPM#3 TP113
SM_RCOMP[0:2] SM_RCOMP_0 AU60 K59 XDP_BPM#4
SM_RCOMP_1 AV60 SM_RCOMP0 DDR3L BPM#4 H63 XDP_BPM#5
TP55 Length match < 300 mils
Trace length < 500 mils SM_RCOMP1 BPM#5 TP117
C SM_RCOMP_2 AU61 K60 XDP_BPM#6 C
Trace width = 12~15 mils CPU_DRAMRST# AV15 SM_RCOMP2 BPM#6 J61 XDP_BPM#7
TP58
Trace spacing = 20 mils SM_DRAMRST DSW BPM#7 TP56
DDR_PG_CTRL AV61
SM_PG_CNTL1
2 OF 19
+1.05V_VCCST +1.05V_VCCST [5,10]

+1.35V_SUS +1.35V_SUS [5,14,15,32]
+VCCIO_OUT +VCCIO_OUT [5]
+5V_S5 +5V_S5 [8,27,31,32,34,36]
Power tracking
B B
DRAM COMP XDP PU/PD DDR3L ODT GENERATION +1.35V_SUS

+1.05V_VCCST
R249 200/F_4 SM_RCOMP_0 +3VSUS +5V_S5 U33
XDP_TDO_CPU R568 51_4
5 1
VCC NC
1
R250 120/F_4 SM_RCOMP_1
1
XDP_TCK0 R269 51_4
XDP_TRST# R262 *51_4 R645 R573 C545 2 R572 *short_4 DDR_PG_CTRL
R248 100/F_4 SM_RCOMP_2 *220K/F_4 220K/F_4 0.1u/10V_4 A
2
2
2
4 3
[32] DDR_VTTT_PG_CTRL Y GND
+1.35V_SUS 74AUP1G07GW
PU/PD of CPU DRAMRST
3
+1.35V_SUS
+VCCIO_OUT 2 Q41
2N7002K
1
H_PROCHOT# R579 *62_4

R220 R544 66.5/F_4 M_B_ODT0_DIMM [15]
+1.05V_VCCST 470_4 R651
1
A *2M/F_4 R542 66.5/F_4 A
M_B_ODT1_DIMM [15]
R578 62_4
CPU DRAM
2
CPU_DRAMRST# R217 *short_4 DDR3_DRAMRST# [14,15]

1
H_PWRGOOD_R R565 10K_4 C154

*0.1u/10V_4
PROJECT : ZQX
2

1B
Haswell 1/5 (PEG/DMI/FDI)
5 4 3 2 1
5 4 3 2 1
VDDQ Output Decoupling Recommendations

330uFx2 7343 BOT socket side +3V +3V [2,7,8,9,10,11,13,14,15,16,17,18,21,22,23,24,25,26,27,28,29,31,32,33,34,35,36]
22uFx11
10uFx10
0805
0805
5 onTOP, 6 on BOT inside socket cavity
5 onTOP, 5 on BOT inside socket cavity
+1.05V
+1.35V_SUS
+1.05V_VCCST
+1.05V [11,13,30,33,34,35]
+1.35V_SUS [4,14,15,32]
+1.05V_VCCST [4,10]
VCC Output Decoupling Recommendations
470uFx4 7343 TOP socket side
05
+VCCIN +VCCIN [34] 22uFx8 0805 4 on TOP, 4 on BOT near socket edge
+1.35V_SUS Power tracking 22uFx11 0805 TOP, inside socket cavity
D D
10uFx11 0805 BOT, inside socket cavity
R231 0_1206
R239 0_1206
Haswell ULT (POWER) + C521
*330u_2.5V_3528
HSW_ULT_DDR3L
U28L
+1.35V_CPU 1.4A +VCCIN 32A
TP57 ULT_RVSD_61 L59 C36 +VCCIN
+1.35V_CPU ULT_RVSD_62 J58 RSVD VCC C40
TP54 RSVD VCC C44
AH26 VCC C48 C236 C257 C269 C285 C267 C255
C220 C216 C277 C219 C276 C217 AJ31 VDDQ VCC C52 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 AJ33 VDDQ VCC C56
AJ37 VDDQ VCC E23
AN33 VDDQ VCC E25
AP43 VDDQ VCC E27
AR48 VDDQ VCC E29
+ AY35 VDDQ VCC E31
C470 C494 C215 C278 C218 AY40 VDDQ VCC E33 C238 C254 C252 C274 C235 C523 +1.05V +VCCIO_OUT
*470u/2V_7343 2.2u/6.3V_6 2.2u/6.3V_6 2.2u/6.3V_6 2.2u/6.3V_6 AY44 VDDQ VCC E35 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8
AY50 VDDQ VCC E37 R555 *0_8
VDDQ VCC E39
F59 VCC E41
+VCCIN VCC VCC
TP61 ULT_RVSD_63 N58 E43 C528
R566 100/F_4 ULT_RVSD_64 AC58 RSVD VCC E45 *4.7u/6.3V_6
+VCCIN TP68 RSVD VCC
C E47 C
R582 *short_4 VCC_SENSE_R E63 VCC E49 C282 C260 C262 C264 C265 C259
[34] VCC_SENSE VCC_SENSE VCC
TP47 ULT_RVSD_65 AB23 E51 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8
A59 RSVD VCC E53
300mA +VCCIO_OUT VCCIO_OUT VCC
300mA +VCCIOA_OUT E20 E55
ULT_RVSD_66 AD23 VCCIOA_OUT VCC E57
TP44 RSVD VCC
TP48 ULT_RVSD_67 AA23 F24
ULT_RVSD_68 AE59 RSVD VCC F28
TP64 RSVD VCC F32
H_CPU_SVIDART# L62 VCC F36 C237 C250 C245 C271 C253 C256
H_CPU_SVIDCLK N63 VIDALERT HSW ULT POWER VCC F40 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8
H_CPU_SVIDDAT L63 VIDSCLK VCC F44
VCCST_PW RGD B59 VIDSOUT VCC F48
[13] VCCST_PW RGD VCCST_PWRGD VCC
VRON_CPU F60 F52
[34] VRON_CPU VR_EN VCC
[10,34] IMVP_PW RGD IMVP_PW RGD C59 F56
VR_READY VCC G23
D63 VCC G25
R277 *short_4 PW R_DEBUG_R H59 VSS VCC G27 C242 C247 C248 C243 C266 C268
[13] PW R_DEBUG PWR_DEBUG VCC
P62 G29 *22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8 *22u/6.3V_8
R570 150_6 ULT_RVSD_69 P60 VSS VCC G31
+1.05V_VCCST TP51 RSVD_TP VCC
TP52 ULT_RVSD_70 P61 G33
ULT_RVSD_71 N59 RSVD_TP VCC G35
TP50 RSVD_TP VCC
TP62 ULT_RVSD_72 N61 G37
ULT_RVSD_73 T59 RSVD_TP VCC G39
TP70 RSVD VCC
ULT_RVSD_74 AD60 G41
+1.05V_VCCST
TP69
TP59 ULT_RVSD_75 AD59 RSVD
RSVD
VCC
VCC
G43 SVID +VCCIO_OUT +1.05V_VCCST
Layout note: need routing together
TP66 ULT_RVSD_76 AA59 G45
TP65 ULT_RVSD_77 AE60 RSVD VCC G47 and ALERT need between CLK and DATA.
R564 *10K_4 ULT_RVSD_78 AC59 RSVD VCC G49
B TP60 RSVD VCC B
TP53 ULT_RVSD_79 AG58 G51
VRON_CPU R580 10K_4 IMVP_PW RGD ULT_RVSD_80 U59 RSVD VCC G53 R260 R259
TP63 RSVD VCC
TP67 ULT_RVSD_81 V59 G55 *130/F_4 130/F_4
RSVD VCC G57
AC22 VCC H23 H_CPU_SVIDDAT R258 *short_4
VCCST VCC VR_SVID_DATA [34]
AE22 J23
AE23 VCCST VCC K23
+1.05V_VCCST VCCST VCC Place PU resistor
K57 close to CPU
AB57 VCC L22 +1.05V_VCCST +VCCIO_OUT
+1.05V +1.05V_VCCST AD57 VCC VCC M23
AG57 VCC VCC M57
R235 *short_8 C24 VCC VCC P57
C28 VCC VCC U57
VCC VCC Place PU resistor
+VCCIN C32 W57 close to CPU R265 R266
C240 VCC VCC 75_4 *75_4
*4.7u/6.3V_6 12 OF 19
H_CPU_SVIDART# R263 43_4 VR_SVID_ALERT# [34]
+3V VCCST PWRGD H_CPU_SVIDCLK R268 *short_4 VR_SVID_CLK [34]

10/30 reserve
HWPG_1.05V for DDR=1.5V DDR=1.5V ,This block POP +3V_S5 U37
+1.05V_VCCST
+1.05V +3V 5 1
R559 VCC NC
*4.7K_4 C573 R612 *0_4 HW PG_1.05V_S5 [13,29,33]
A R587 0.1u/10V_4 2 VCCST_PW RGD_EN R613 *0_4 A
A APW ORK [7,29]
R556 R558 10K_4 R604 *short_4 PCH_PW ROK [7,29]
HW PG_1.05V [29]
*4.7K_4 *4.7K_4
3
VCCST_PW RGD R588 *short_4 VCCST_PW RGD_R 4 3

Y GND
3
R557
2 2 *100K/F_4
Q38
C558
*0.1u/10V_4
74AUP1G07GW Quanta Computer Inc.
1
C535 *MMBT3904-7-F C534 Q40

PROJECT : ZQX
1
*1000p/50V_4 *1000p/50V_4 *DTC144EU

1B
Haswell 4/5 (POWER)
Date: W ednesday, September 03, 2014 Sheet 5 of 43
5 4 3 2 1
5 4 3 2 1
Haswell ULT (CFG,RSVD)

U28S HSW_ULT_DDR3L
06
D CFG0 AC60 AV63 D
[13] CFG0 CFG0 RSVD_TP
[13] CFG1 CFG1 AC62 AU63
CFG2 AC63 CFG1 RSVD_TP
[13] CFG2 CFG2
[13] CFG3 CFG3 AA63
CFG4 AA60 CFG3 C63
[8,13] CFG4 CFG4 RSVD_TP
[13] CFG5 CFG5 Y62 C62
CFG6 Y61 CFG5 RSVD_TP B43
[13] CFG6 CFG6 RSVD
[13] CFG7 CFG7 Y60
CFG8 V62 CFG7 A51
[13] CFG8 CFG8 RSVD_TP
[13] CFG9 CFG9 V61 B51
CFG10 V60 CFG9 RSVD_TP
[13] CFG10 CFG10
[13] CFG11 CFG11 U60 L60
CFG12 T63 CFG11 RSVD_TP
[13] CFG12 CFG12
[13] CFG13 CFG13 T62 RESERVED N60
CFG14 T61 CFG13 RSVD
[13] CFG14 CFG14
[13] CFG15 CFG15 T60 W23
CFG15 RSVD Y22
NOA_STBN_0 AA62 RSVD AY15 OPI_COMP1 R224 49.9/F_4
[13] NOA_STBN_0 CFG16 PROC_OPI_RCOMP
[13] NOA_STBN_1 NOA_STBN_1 U63
NOA_STBP_0 AA61 CFG18 AV62
[13] NOA_STBP_0 CFG17 RSVD
[13] NOA_STBP_1 NOA_STBP_1 U62 D58
CFG19 RSVD
R254 49.9/F_4 CFG_RCOMP V63 P22
CFG_RCOMP VSS N21
C VSS C
A5
TP103 RSVD P20
E1 RSVD R20
D1 RSVD RSVD
J20 RSVD
H18 RSVD
R541 8.2K_4 TD_IREF B12 RSVD
TD_IREF
19 OF 19
Processor Strapping
1 0
CFG0
(DEFAULT) NORMAL OPERATION; NO STALL STALL CFG0 R270 *1K_4
EAR-STALL/NOT STALL RESET SEQUENCE
AFTER PCU PLL IS LOCKED
CFG1 CFG1 R264 *1K_4
PCH/ PCH LESS MODE SELECTION (DEFAULT) NORMAL OPERATION PCH-LESS MODE
B CFG3 DISABLED ENABLED B

CFG3 R561 *1K_4
PHYSICAL_DEBUG_ENABLED (DFX PRIVACY) NO PHYSICAL DISPLAY PORT ATTACHED AN EXTERNAL DISPLAY PORT DEVICE IS
TO CONNECTED
EMBEDDED DISPLAY PORT TO THE EMBEDDED DISPLAY PORT
CFG 8 DISABLED(DEFAULT); IN THIS CASE, NOA ENABLED; NOA WILL BE AVAILABLE

ALLOW THE USE OF NOA ON LOCKED UNITS WILL BE DISABLED IN LOCKED UNITS AND REGARDLESS OF THE LOCKING OF THE UNIT CFG8 R577 *1K_4
ENABLED IN UN-LOCKED UNITS
CFG9 NO VR SUPPORTING SVID IS PRESENT. THE CFG9 R560 *1K_4

NO SVID PROTOCOL CAPABLE VR VRS SUPPORTING SVID PROTOCOL ARE CHIP WILL NOT GENERATE (OR RESPOND TO)
CONNECTED PRESENT SVID ACTIVITY
CFG10 POWER FEATURES ACTIVATED POWER FEATURES (ESPECIALLY CLOCK

CFG10 R308 *1K_4
SAFE MODE BOOT DURING RESET GATINE ARE NOT ACTIVATED
A A

PROJECT : ZQX
1B
Haswell 5/5 (CFG/GND)
5 4 3 2 1
5 4 3 2 1
Haswell ULT PCH (PM)

[29] PCH_SUSACK#
[13] SYS_RESET#
PCH_SUSPWRACK R468
R467 *0_4
*0_4 SUSACK#_R
SYS_RESET#
AK2
U28H HSW_ULT_DDR3L
SYSTEM POWER MANAGEMENT
AW7 DSWVREN
Deep Sx
DSWVREN [8]
07
C571 *1u/6.3V_4 AC3 SUSACK DSWVRMEN AV5 DPWROK_R R479 *0_4
SYS_RESET DPWROK DPWROK [29]
SYS_PWROK R602 *short_4 SYS_PWROK_R AG2 DSW AJ5 PCIE_LAN_WAKE# PCIE_LAN_WAKE# [24,26]
D R598 *0_4 R601 *0_4 EC_PWROK_R AY7 SYS_PWROK WAKE D
EC_PWROK R608 *0_4 R605 *0_4 APWROK_R AB5 PCH_PWROK
PCI_PLTRST# AG7 APWROK V5 CLKRUN#
PLTRST +3V_S5 +3V CLKRUN/GPIO32 AG4 LPCPD#
CLKRUN# [21,29]
+3V_S5 SUS_STAT/GPIO61 LPCPD# [21]
+3V_S5 AE6 PCH_SUSCLK
SUSCLK/GPIO62 TP20
DSW AP5 PCH_SLP_S5# PCH_SLP_S5# [13]
R511 *short_4 PCH_RSMRST# AW6 SLP_S5/GPIO63
[29] RSMRST# RSMRST
[29] PCH_SUSPWARN# R445 *0_4 PCH_SUSPWRACK AV4 +3V_S5
R128 *short_4 PCH_PWRBTN# AL7 SUSWARN/SUSPWRDNACK/GPIO30 AJ6 SUSC#
[29] DNBSWON# PWRBTN DSW DSW SLP_S4 SUSC# [13,29]
[30] ACPRESENT R139 *short_4 PCH_ACPRESENT AJ8 DSW DSW AT4 SUSB# SUSB# [13,29]
PCH_BATLOW# AN4 ACPRESENT/GPIO31 SLP_S3 AL5 PCH_SLP_A#
BATLOW/GPIO72 DSW DSW SLP_A PCH_SLP_A# [13]
[13] PCH_SLP_S0# PCH_SLP_S0# AF3 +3V_S5 DSW AP4 PCH_SLP_SUS# PCH_SLP_SUS# [29]
PCH_SLP_WLAN# AM5 SLP_S0 SLP_SUS AJ7 PCH_SLP_LAN#
TP38 SLP_WLAN/GPIO29 DSW DSW SLP_LAN TP31
8 OF 19
C C
Power Sequence [5,29] APWORK R614 *short_4 APWROK_R
[5,29] PCH_PWROK R518 *short_4 EC_PWROK_R
EC_PWROK R606 *0_4 SYS_PWROK_R

R519 Speed up 250ms to boot up R615
100K_4
RSMRST# R482 *short_4 DPWROK_R for EC power on 250 ms 10K_4
Non Deep Sx
PCH PM PU/PD PLTRST# Buffer Deep Sx Circuit Non Deep Sx

+3V +3V
R204 *Short_6
C127 0.1u/10V_4
CLKRUN# R160 8.2K_4 +3V_S5 +3VCC_S5
5
SYS_RESET# R499 10K_4
2 1 3
4 PLTRST# [13,16,21,24,26,29]
B PCI_PLTRST# 1 B
PCH_RSMRST# R510 10K_4 Q20
2
SYS_PWROK R596 *10K_4 U9 C157 R151 *AO3413
3
DPWROK_R R478 100K/F_4 TC7SH08FU R94 *0.33u/10V_6 *100K_4

100K_4
+3V_S5 R136
*0_6
PCH_SUSPWRACK R453 *10K_4
SYSPWOK
3
+3V_S5
+3V_S5 C561 *0.1u/10V_4 PCH_SLP_SUS# 2
PCH_ACPRESENT R165 10K_4 Q15

5
PCH_BATLOW# R505 8.2K_4 *2N7002K

PCIE_LAN_WAKE# R193 1K_4 2 EC_PWROK EC_PWROK [29]
1
PCH_PWRBTN# R137 *10K_4 DSW PU [13] SYS_PWROK SYS_PWROK 4
1
A +3VPCU IMVP_PWRGD_3V [10] A
U38
3
R134 *10K_4 TC7SH08FU R616

R471
R169
*8.2K_4
*1K_4 R607 *0_4
10K_4 Quanta Computer Inc.
R145 *10K_4
PROJECT : ZQX
1B
LPT 1/6 (DMI/FDI/VGA)
5 4 3 2 1
5 4 3 2 1
Haswell ULT PCH (RTC/HDA/SATA/SPI) Haswell ULT PCH(LPC,SPI,SMBUS,C-LINK,THERMAL)

U28E HSW_ULT_DDR3L
[21,26,29] LPC_LAD0
[21,26,29] LPC_LAD1
AU14
AW12
U28G
LAD0
HSW_ULT_DDR3L
+3V_S5 SMBALERT/GPIO11
+3V_S5
AN2
AP2
SMBALERT#
SMB_PCH_CLK
08
RTC_X1 AW5 AY12 LAD1 SMBCLK AH1 SMB_PCH_DAT
RTCX1 [21,26,29] LPC_LAD2 LAD2
LPC
SMBUS
+3V_S5 SMBDATA
RTC_X2 AY5 [21,26,29] LPC_LAD3 AW11 +3V_S5 SML0ALERT/GPIO60 AL2 SMB0ALERT#
R481 1M_4 SM_INTRUDER# AU6 RTCX2 J5 AV12 LAD3 AN1 SMBCLK0
+3V_RTC INTRUDER SATA_RN0/PERN6_L3 SATA_RXN0 [21] [21,26,29] LPC_LFRAME# LFRAME +3V_S5 SML0CLK
PCH_INTVRMEN AV7 H5 +3V_S5 AK1 SMBDATA0
INTVRMEN SATA_RP0/PERP6_L3 SATA_RXP0 [21] SML0DATA
SRTC_RST# AV6 RTC B15 HDD +3V_S5 AU4 SMB1ALERT#
SRTCRST SATA_TN0/PETN6_L3 SATA_TXN0 [21] SML1ALERT/PCHHOT/GPIO73
[13] RTC_RST# RTC_RST# AU7 A15 +3V_S5 AU3 SMB_ME1_CLK
RTCRST SATA_TP0/PETP6_L3 SATA_TXP0 [21] SML1CLK/GPIO75
+3V_S5 AH3 SMB_ME1_DAT
D J8 PCH_SPI_CLK AA3 SML1DATA/GPIO74 D
SATA_RN1/PERN6_L2 TP35 SPI_CLK
H8 PCH_SPI_CS0# Y7 AF2 CL_CLK
SATA_RP1/PERP6_L2 TP36 SPI_CS0 CL_CLK TP98
A17 Y4 AD2 CL_DAT
SATA_TN1/PETN6_L2 TP41 SPI_CS1 CL_DATA TP96
B17 AC2 SPI C-LINK AF4 CL_RST#
SATA_TP1/PETP6_L2 TP40 SPI_CS2 CL_RST TP97
PCH_SPI_SI AA2
HDA_BCLK_R AW8 J6 PCH_SPI_SO AA4 SPI_MOSI
HDA_SYNC_R AV11 HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6 PCH_SPI_IO2 Y6 SPI_MISO
HDA_RST#_R AU8 HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 B14 PCH_SPI_IO3 AF1 SPI_IO2
AY10 HDA_RST/I2S_MCLK AUDIO SATA SATA_TN2/PETN6_L1 C15 SPI_IO3
[22] PCH_AZ_CODEC_SDIN0 HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1
AU12 +3V
HDA_SDO_R AU11 HDA_SDI1/I2S1_RXD F5 7 OF 19
AW10 HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0 E5 SYS_COM_REQ R495 10K_4
AV10 HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 C17 GPIO36 R185 10K_4
AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17 GPIO37 R498 10K_4
I2S1_SCLK SATA_TP3/PETP6_L0
R465 *10K_4 VGPU_EN R447 10K_4
+3V V1 VGPU_EN VGPU_EN [36]
SATA0GP/GPIO34 U1 SYS_COM_REQ
+3V SATA1GP/GPIO35
+3V V6 GPIO36
SATA2GP/GPIO36 AC1 GPIO37
+3V SATA3GP/GPIO37
AU62 trace width 12~15mil
[4,13] XDP_TRST#
[13] XDP_TCK1 XDP_TCK1 AE62 PCH_TRST A12 SATA_IREF R539 0_4 +V1.05S_ASATA3PLL
SMBus SMBus(PCH)
XDP_TDI AD61 PCH_TCK SATA_IREF L11
[13] XDP_TDI PCH_TDI RSVD
[13] XDP_TDO R303 0_4 PCH_JTAG_TDO AE61 K10 trace width 12~15mil +3V
AD62 PCH_TDO JTAG
RSVD C12 SATA_RCOMP R538 3.01K/F_4 +3V_S5
[13] XDP_TMS PCH_TMS SATA_RCOMP +V1.05S_ASATA3PLL
AL11 U3 SATA_LED# R455 10K_4
RSVD SATALED +3V
AC4 R501 10K_4 SMB0ALERT#
R571 0_4 PCH_JTAGX AE63 RSVD R485 10K_4 SMB1ALERT#
[4,13] XDP_TCK0 JTAGX
AV2 SATA_RCOMP R470 10K_4 SMBALERT#
RSVD R104 R117
Impedance = 50 ohm Q17 4.7K_4 4.7K_4
Trace length < 500 mils 5
Trace spacing = 15 mils R123 2.2K_4 SMB_PCH_CLK
5 OF 19 R124 2.2K_4 SMB_PCH_DAT SMB_PCH_DAT 3 4 CLK_SDATA [13,14,15,26]
C R500 2.2K_4 SMBDATA0 C
R503 2.2K_4 SMBCLK0
2
SMB_PCH_CLK 6 1 CLK_SCLK [13,14,15,26]
RTC Circuitry +3V_RTC_[0:2] +3V_RTC

PCH Quad SPI 2N7002DW
+3V_S5 +3V_PCH_ME
(RTC) Trace width = 20 mils D29 +3V_RTC
Trace width = 30 mils ROM(8M)
+3VPCU R516 *Short_6 +3V_RTC_2 R517 (Default for WIN8) R421 *Short_6 PCH_XDP_WLAN/S5 DDR_TP/S0
RTC_RST#
VCCRTC_2 R509 1K_4 +3V_RTC_1
1
20K/F_4 +3V_PCH_ME
BAT54C +3V_PCH_ME
C152 J6 R416 10K_4 SMBus(EC) +3V_S5
+5V_S5 1u/6.3V_4 *JUMP U24 C420 0.1u/10V_4
20MIL
2
[29] SPI_CS0#_UR_ME R415 *short_4 PCH_SPI_CS0# 1 8

1 3VCCRTC_3 R563 4.7K_4 VCCRTC_4 R574 4.7K_4 R524 CS# VCC
SRTC_RST# PCH_SPI_SO R430 15_4 PCH_SPI_SO_R 2 7 SPI_HOLD_IO3_ME R418 *1K_4
Q39 IO1/DO IO3/HOLD#
1
MMBT3904 20K/F_4 R429 15_4 3 6 R425 15_4 PCH_SPI_CLK R97 R91

[29] PCH_SPI_SO_EC
2
R576 IO2/WP# CLK Q14 *2.2K_4 *2.2K_4

1
68.1K/F_4 C436 C161 J7 5 R427 15_4 PCH_SPI_SI 5

1u/6.3V_4 1u/6.3V_4 *JUMP 4 IO0/DI
reserve for SPI fast read
2
GND 3 4 SMB_ME1_CLK
[19,29] 2ND_MBCLK
C430
W25Q64FVSSIQ -- 8MB *22p/50V_4
BT6 2
R575 reserve for SPI fast read
2
150K/F_4 change PN 11/15 PCH_SPI_CLK_R R426 15_4 PCH_SPI_CLK_EC [29] [19,29] 2ND_MBDATA 6 1 SMB_ME1_DAT
+3V_PCH_ME PCH_SPI_SI_R R428 15_4 PCH_SPI_SI_EC [29]
EC/S5 *2N7002DW PCH/S5
R419 *1K_4 SPI_WP_IO2_ME R423 15_4 PCH_SPI_IO2
B B
3.3K is original and
PCH_SPI_IO3 R422 15_4 SPI_HOLD_IO3_ME 2ND_MBCLK R98 0_4 SMB_ME1_CLK
RTC Clock 32.768KHz (RTC) for no support fast 2ND_MBDATA R92 0_4 SMB_ME1_DAT
read function
C437 18p/50V_4 RTC_X1
ULT Strapping Table

2
1
Y7 R508
32.768KHZ 10M_4 Sampled
Pin Name Strap description Configuration note +3VPCU +3VPCU [7,11,13,21,22,23,28,29,30,31,35,36,37]
3
4
C438 18p/50V_4 RTC_X2 0 = Default enable (iPD 20K)

GPIO81(SPKR) No reboot on TCO Timer PWROK +3V R448 *1K_4 SPKR SPKR [10,22] +3V_S5 +3V_S5 [5,7,9,10,11,13,21,24,27,28,29,31,34,36]
expiration 1 =Disable No-Reboot mode
+3V +3V [2,5,7,9,10,11,13,14,15,16,17,18,21,22,23,24,25
0 = Default can program ME (iPD 20K) HDA_SDO_R R535 0_4 +1.05V_S5
HDA HDA_SDO Flash Descriptor Security PWROK ME_WR# [29] +1.05V_S5 [11,13,33,37]
[22] PCH_AZ_CODEC_RST# R530 33_4 HDA_RST#_R Override / Intel ME Debug Mode 1 =can't program ME
+V1.05S_ASATA3PLL +V1.05S_ASATA3PLL [11]
[22] PCH_AZ_CODEC_SDOUT R536 33_4 HDA_SDO_R
INTVRMEN Integrated 1.05V VRM enable ALWAYS 1=Should be always pull-up +3V_RTC R526 330K_4 PCH_INTVRMEN R525 *330K_4 Power tracking
[22] PCH_AZ_CODEC_BITCLK R529 33_4 HDA_BCLK_R
C448
0 = Default disable (iPD 20K) [10] GPIO66
GPIO66 Top-Block Swap override
*10p/50V_4 1 = Enable TBS function +3V R520 *1K_4 GPIO66 R527 *1K_4
0 = Default SPI (iPD 20K) [10] GPIO86

GPIO86 Boot BIOS Strap Bit
[22] PCH_AZ_CODEC_SYNC R532 33_4 HDA_SYNC_R 1 =LPC +3V R202 *1K_4 GPIO86 R200 *1K_4
C450 *10p/50V_4 0 = Default enable w/o

confidentiality(iPD 20K)
A [10] GPIO15 A
GPIO15 TLS(Transport layer security)
1 =Default enable with R161 8.2K_4 GPIO15 R186 *1K_4
PCH JTAG MP remove(Intel)
+3V_S5
JTAG_TCK,JTAG_TMS
confidentiality
Trace Length < 9000mils +1.05V_S5
0 = Enable an external display
XDP_TMS R272 51_4
CFG4 port is connected to the eDP CFG4 R255 1K_4
DP presence strap
XDP_TDI
PCH_JTAG_TDO
R273
R271
51_4
51_4
1 =disable
[6,13] CFG4
PCH_JTAGX R562 *1K_4
[7] DSWVREN
PROJECT : ZQX
XDP_TCK1 R276 *51_4 DSWVREN Deep Sx well on die VR enable 1=Should be always pull-up Size Document Number Rev
R513 330K_4 DSWVREN R514 *330K_4 1B
+3V_RTC LPT 2/6 (SATA/HDA/SPI)
5 4 3 2 1
5 4 3 2 1
Haswell ULT PCH (PCIE,USB3.0,USB2.0) Haswell ULT PCH (CLOCK) XTAL24_IN C490 12p/50V_4
09
3
4
U28K HSW_ULT_DDR3L R545 Y8
1M_4 24MHz
[16] PEG_RX#0
F10 DSW AN8 USBP1- [27]
1
2
E10 PERN5_L0 USB2N0 AM8
[16] PEG_RX0 PERP5_L0 DSW USB2P0 USBP1+ [27] MB USB3.0 XTAL24_OUT
D D
[16] PEG_TX#0 C478 EV@0.22u/10V_4 R_PEG_TX#0 C23 DSW AR7 USBP2- [27] C489 12p/50V_4
C476 EV@0.22u/10V_4 R_PEG_TX0 C22 PETN5_L0 USB2N1 AT7
[16] PEG_TX0 PETP5_L0 DSW USB2P1 USBP2+ [27] DB USB2.0
F8 AR8 HSW_ULT_DDR3L
[16] PEG_RX#1 DSW TP37 U28F
E8 PERN5_L1 USB2N2 AP8
[16] PEG_RX1 PERP5_L1 DSW USB2P2 TP39
PEG x4
[16] PEG_TX#1 C481 EV@0.22u/10V_4 R_PEG_TX#1 B23 DSW AR10

USBP3- [27]
C480 EV@0.22u/10V_4 R_PEG_TX1 A23 PETN5_L1 USB2N3 AT10
[16] PEG_TX1 PETP5_L1 DSW USB2P3 USBP3+ [27] DB USB2.0 CLK_PCIE_N0 C43 A25 XTAL24_IN
TP108 CLKOUT_PCIE_N0 XTAL24_IN
H10 DSW AM15 TP106 CLK_PCIE_P0 C42 B25 XTAL24_OUT
[16] PEG_RX#2 PERN5_L2 USB2N4 USBP4- [26] CLKOUT_PCIE_P0 XTAL24_OUT
[16] PEG_RX2
G10 DSW AL15 USBP4+ [26] BT TP92 CLK_PCIE_REQ0# U2 +3V
PERP5_L2 USB2P4 PCIECLKRQ0/GPIO18 K21
C467 EV@0.22u/10V_4 R_PEG_TX#2 B21 AM13 B41 RSVD M21
[16] PEG_TX#2 PETN5_L2 DSW USB2N5 USBP5- [23] CLKOUT_PCIE_N1 RSVD
[16] PEG_TX2 C463 EV@0.22u/10V_4 R_PEG_TX2 C21 DSW AN13 USBP5+ [23] Touch screen A41 C26 ICLK_BIAS R546 3.01K/F_4 +V1.05S_AXCK_LCPLL
PETP5_L2 USB2P5 CLK_PCIE_REQ1# Y5 CLKOUT_PCIE_P1 DIFFCLK_BIASREF
TP22 PCIECLKRQ1/GPIO19 +3V
[16] PEG_RX#3
E6 DSW AP11 USBP6- [23]
C35 TESTLOW_C35
F6 PERN5_L3 USB2N6 AN11 C41 CLOCK TESTLOW_C35 C34 TESTLOW_C34
DSW CCD
VGA WLAN LAN

[16] PEG_RX3 PERP5_L3 USB2P6 USBP6+ [23] [24] CLK_PCIE_LANN CLKOUT_PCIE_N2 TESTLOW_C34
[24] CLK_PCIE_LANP
B42 AK8 TESTLOW_AK8
C474 EV@0.22u/10V_4 R_PEG_TX#3 B22 AR13 R450 *short_4CLK_PCIE_REQ2# AD1 CLKOUT_PCIE_P2 SIGNALS TESTLOW_AK8 AL8 TESTLOW_AL8
[16] PEG_TX#3 PETN5_L3 DSW USB2N7 USBP7- [27] [24] CLK_PCIE_LAN_REQ# PCIECLKRQ2/GPIO20 +3V TESTLOW_AL8
C468 EV@0.22u/10V_4 R_PEG_TX3 A21 DSW AP13 Card reader R228 TPM@22_4
[16] PEG_TX3 PETP5_L3 USB2P7 USBP7+ [27] PCLK_TPM [21]
B38 AN15 CLK_PCH_PCI3 R227 22_4
[26] CLK_PCIE_WLANN CLKOUT_PCIE_N3 CLKOUT_LPC_0 CLK_PCI_LPC [26]
G11 C37 AP15 CLK_PCH_PCI4 R225 22_4
LAN
[24] PCIE_RX3-_LAN PERN3 [26] CLK_PCIE_WLANP CLKOUT_PCIE_P3 CLKOUT_LPC_1 CLK_PCI_EC [29]

[24] PCIE_RX3+_LAN
F11 G20 USB3_RXN0 [27] [26] PCIE_CLKREQ_WLAN# R462 *short_4CLK_PCIE_REQ3# N1 +3V
PERP3 USB3RN1 H20 PCIECLKRQ3/GPIO21 B35
USB3RP1 USB3_RXP0 [27] CLKOUT_ITPXDP CLK_PCIE_XDPN [13]
[24] PCIE_TX3-_LAN C497 0.1u/10V_4 PCIE_TX3- C29 MB USB3.0 [16] CLK_PCIE_VGA#
A39 A35 CLK_PCIE_XDPP [13]
C506 0.1u/10V_4 PCIE_TX3+ B30 PETN3 PCIE USB C33 B39 CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P
[24] PCIE_TX3+_LAN PETP3 +3V_S5 USB3TN1 USB3_TXN0 [27] [16] CLK_PCIE_VGA CLKOUT_PCIE_P4
C +3V_S5 B34 USB3_TXP0 [27] [16] CLK_PEGA_REQ# R125 *short_4CLK_PCIE_REQ4# U5 +3V C
F13 USB3TP1 PCIECLKRQ4/GPIO22
[26] PCIE_RX4-_WLAN PERN4
[26] PCIE_RX4+_WLAN
G13 E18 B37
PERP4 USB3RN2 F18 A37 CLKOUT_PCIE_N5
WLAN
C491 0.1u/10V_4 PCIE_TX4- B29 USB3RP2 CLK_PCIE_REQ5# T2 CLKOUT_PCIE_P5

[26] PCIE_TX4-_WLAN PETN4 PCIECLKRQ5/GPIO23 +3V
C493 0.1u/10V_4 PCIE_TX4+ A29 +3V_S5 B33
[26] PCIE_TX4+_WLAN PETP4 USB3TN2
+3V_S5 A33
PCIE_RXN1 G17 USB3TP2 6 OF 19
TP42 PERN1/USB3RN3
TP43 PCIE_RXP1 F17
PERP1/USB3RP3
PCIE_TXN1 C30 USBCOMP
TP105
PCIE_TXP1 C31 PETN1/USB3TN3 +3V_S5 AJ10 USBCOMP R222 22.6/F_4
TP104 PETP1/USB3TP3 +3V_S5 USBRBIAS AJ11
Impedance = 50 ohm +3V
F15 USBRBIAS AN10 Trace length < 500 mils
G15 PERN2/USB3RN4 RSVD AM10 Trace spacing = 15 mils CLK_PCIE_REQ0# R474 10K_4
PERP2/USB3RP4 RSVD CLK_PCIE_REQ1# R143 10K_4
B31 CLK_PCIE_REQ2# R451 10K_4
A31 PETN2/USB3TN4 +3V_S5 USB Overcurrent CLK_PCIE_REQ3# R490 10K_4 CLK_PCI_EC CLK_PCI_LPC
PETP2/USB3TP4 +3V_S5 AL3 USB_OC0# CLK_PCIE_REQ5# R477 10K_4
+3V_S5 OC0/GPIO40 AT1 USB_OC1#
USB_OC0# [27] MB U3 +3V_S5
+3V_S5 OC1/GPIO41 AH2 USB_OC2#
USB_OC1# [27] DB U2 RP6
+3V_S5 OC2/GPIO42
E15 +3V_S5 AV3 USB_OC3# 10 1 TESTLOW_C35 R550 10K_4 C205 C210
E13 RSVD OC3/GPIO43 USB_OC3# 9 2 TESTLOW_C34 R549 10K_4 *18p/50V_4 *18p/50V_4
R232 3.01K/F_4 PCIE_RCOMP A27 RSVD USB_OC1# 8 3 TESTLOW_AK8 R218 10K_4
R233 *short_4 PCIE_IREF B27 PCIE_RCOMP USB_OC2# 7 4 TESTLOW_AL8 R219 10K_4
+V1.05S_AUSB3PLL PCIE_IREF USB_OC0# 6 5
B 10K_10P8R B
11 OF 19
+3V
Swap for layou 11/14 CLK_PCIE_REQ4# R158 10K_4

R183 *1K_4
+V1.05S_AUSB3PLL +V1.05S_AUSB3PLL [11]

+3V_S5 +3V_S5 [5,7,8,10,11,13,21,24,27,28,29,31,34,36]
+3V +3V [2,5,7,8,10,11,13,14,15,16,17,18,21,22,23,24,25,26,27,28,29,31,32,33,34,35,36]
+V1.05S_AXCK_LCPLL +V1.05S_AXCK_LCPLL [11]
Power tracking
A A

PROJECT : ZQX
1B
LPT 3/6 (PCIE/USB/CLK)
5 4 3 2 1
5 4 3 2 1
PCH GPIO PU/PD
High Low
Haswell ULT PCH (GPIO,CPU/MISC,NCTF)
U28J HSW_ULT_DDR3L
10
+3V
GPIO8 touch panel No Touch panel IRQ_SERIRQ R182 10K_4
DEVSLP0 R476 10K_4
BOARD_ID0 P1 +3V D60 THRMTRIP# DEVSLP1 R460 10K_4
D R484 *short_4 AU2 BMBUSY/GPIO76 THRMTRIP V4 SIO_RCIN# SIO_RCIN# R412 10K_4 D
[23] GPIO8 GPIO8 +3V_S5 +3V RCIN/GPIO82 SIO_RCIN# [29]
LAN_DISABLE# AM7 DSW T4 IRQ_SERIRQ IRQ_SERIRQ [21,29] SIO_EXT_SMI# R177 10K_4
GPIO15 AD6 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ AW15 OPI_COMP2 R223 49.9/F_4 SIO_EXT_SCI# R458 10K_4
[8] GPIO15
SKU_ID0 Y1 GPIO15 +3V_S5 MISC PCH_OPI_RCOMP AF20
DGPU_PWROK T3 GPIO16 +3V RSVD AB21
[17] DGPU_PWROK
GPIO24 AD5 GPIO17 +3V RSVD GPIO85 R180 10K_4
TP21
WK_GPIO27 AN5 GPIO24 +3V_S5 GPIO87 R170 10K_4
TP33
GPIO28 AD7 GPIO27 DSW GPIO88 R152 10K_4
TP29
ODD_PRSNT# AN3 GPIO28 +3V_S5 GPIO89 R140 10K_4
TP95 GPIO26 +3V_S5 R6 TP_INT_PCH GPIO90 R459 10K_4
+3V GSPI0_CS/GPIO83 TP_INT_PCH [23]
GPIO56 AG6 L6 GPIO84 GPIO91 R454 10K_4
TP27
GPIO57 AP1 GPIO56 +3V_S5 +3V GSPI0_CLK/GPIO84 N6 GPIO85 GPIO92 R153 10K_4
TP18
GPIO58 AL4 GPIO57 +3V_S5 +3V GSPI0_MISO/GPIO85 L8 GPIO86 GPIO93 R487 10K_4
TP19
GPIO59 AT5 GPIO58 +3V_S5 +3V GSPI0_MOSI/GPIO86 R7 GPIO87
GPIO86 [8]
GPIO94 R486 10K_4
TP34
GPIO44 AK4 GPIO59 +3V_S5 GPIO
+3V GSPI1_CS/GPIO87 L5 GPIO88 GPIO64 R201 10K_4
TP30
GPIO47 AB6 GPIO44 +3V_S5 +3V GSPI1_CLK/GPIO88 N7 GPIO89 GPIO65 R205 10K_4
TP26
DGPU_HOLD_RST# U4 GPIO47 +3V_S5 +3V GSPI1_MISO/GPIO89 K2 GPIO90 TP_INT_PCH R157 10K_4
[16] DGPU_HOLD_RST# GPIO48 +3V +3V GSPI_MOSI/GPIO90 I2C0 connect to Sensor HUB,
DGPU_PWR_EN Y3 J1 GPIO91 GPIO84 R176 10K_4
[37] DGPU_PWR_EN
DGPU_PW_CTRL# P3 GPIO49 +3V +3V UART0_RXD/GPIO91 K3 GPIO92
I2C1 connect touchpanle and
Sensor_PCH_DAT R442 2.2K_4
MODPHY_EN Y2 GPIO50 +3V +3V UART0_TXD/GPIO92 J2 GPIO93
touchpad for Acer request 11/08 Sensor_PCH_CLK R444 2.2K_4
[33] MODPHY_EN
RAM_ID0 AT3 HSIOPC/GPIO71 +3V +3V
SERIAL IO UART0_RTS/GPIO93 G1 GPIO94 I2C1_SDA_GPIO6 R483 2.2K_4
RAM_ID3 AH4 GPIO13 +3V_S5 +3V UART0_CTS/GPIO94 K4 SIO_EXT_SMI# I2C1_SCL_GPIO7 R512 2.2K_4
TP25 GPIO25 AM4 GPIO14 +3V_S5 +3V UART1_RXD/GPIO0 G2 SIO_EXT_SCI#
SIO_EXT_SMI# [29]
GPIO67 R206 10K_4
R138 *short_4GPIO45 AG5 GPIO25 DSW +3V UART1_TXD/GPIO1 J3 DGPU_EVENT#
SIO_EXT_SCI# [29]
GPIO68 R531 10K_4 I2C PULL HIGH
[27,29] Sensor_INT
AG3 GPIO45 +3V_S5 +3V UART1_RST/GPIO2 J4 GC6_FB_EN
DGPU_EVENT# [19]
GPIO69 R515 10K_4
[27,29] G_sen_INT GPIO46 +3V_S5 +3V UART1_CTS/GPIO3 F2 R203 *short_4
GC6_FB_EN [17,19]
C +3V I2C0_SDA/GPIO4 Sensor_PCH_DAT [29] C
RAM_ID1 AM3 +3V_S5 +3V F3 R210 *short_4 Sensor_PCH_CLK [29]
RAM_ID2 AM2 GPIO9 I2C0_SCL/GPIO5 G4
DEVSLP0 P2 GPIO10 +3V_S5 +3V I2C1_SDA/GPIO6 F1
I2C1_SDA_GPIO6 [23,28]
R475 *100K_4 DGPU_PWR_EN R449 10K_4
[21] DEVSLP0 DEVSLP0/GPIO33 +3V +3V I2C1_SCL/GPIO7 I2C1_SCL_GPIO7 [23,28]
BOARD_ID3 C4 +3V +3V E3 GPIO64
DEVSLP1 L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4 GPIO65 DGPU_HOLD_RST# R496 10K_4
TP93 DEVSLP1/GPIO38 +3V +3V SDIO_CMD/GPIO65
SKU_ID1 N5 +3V +3V D3 GPIO66 GPIO66 [8]
SPKR V2 DEVSLP2/GPIO39 SDIO_D0/GPIO66 E4 GPIO67
[8,22] SPKR SPKR/GPIO81 +3V +3V SDIO_D1/GPIO67
+3V C3 GPIO68
SDIO_D2/GPIO68 E2 GPIO69
DEVSLP0 for HDD +3V SDIO_D3/GPIO69 20130926 chnge GPIO port
DEVSLP1 for mSATA 10 OF 19 high UMA Only
GPU power is control by PCH

low GPIO (Discrete, SG or Optimize) +3V
Board ID RAM ID +3V_S5 CPU thermal trip

R493 EV@100K_4 DGPU_PW_CTRL# R464 IV@1K_4
R506 SP@10K_4 RAM_ID0 R472 SP@10K_4 4 +1.05V_VCCST
+3V R191 SP@10K_4 RAM_ID1 R167 SP@10K_4 R494 *10K_4 DGPU_PWROK
3
R502 SP@10K_4 RAM_ID2 R469 SP@10K_4 2
3
R188 10K_4 RAM_ID3 R163 *10K_4 +3V_S5
R492 10K_4 BOARD_ID0 R463 *10K_4 1
[2] BOARD_ID1 Vender RAM_ID Q PN Mfr. PN Freq. IMVP_PWRGD_3V 2 Q43 ODD_PRSNT# R504 10K_4
GPIO8 R473 10K_4
B R181 10K_4 BOARD_ID1 R156 *10K_4 Hynix 0000 AKD5JGETW04 H5TC4G63AFR-PRBA(A) 1600MHz FDV301N B
[2] BOARD_ID2 0001 GPIO24 R187 10K_4
1
GPIO28 R162 10K_4
R178 10K_4 BOARD_ID2 R154 *10K_4 Elpida 0010 AKD5JGST407 EDJ4216EFBG-GN-LF 1600MHz +1.05V_VCCST GPIO56 R189 10K_4
R628 GPIO57 R207 10K_4
R534 NTPM@10K_4 BOARD_ID3 R533 TPM@10K_4 Hynix 0011 AKD5PGSTW03 H5TC4G63MFR-PBA(M) 1600MHz 1K_4 GPIO58 R190 10K_4
GPIO59 R211 10K_4
[2] BOARD_ID4 MICRON 0100 AKD5JGSTL08 MT41K256M16HA-125 1600MHz R627 GPIO44 R166 10K_4
GPIO47 R144 10K_4
2
R489 10K_4 BOARD_ID4 R461 *10K_4 Kingston 0101 1K_4 GPIO45 R164 10K_4
G_sen_INT R452 10K_4
1234 THRMTRIP# 1 3 SYS_SHDN# [21,31,35]
Q42 MMBT3904-7-F +3V_S5
+3V LAN_DISABLE# R209 10K_4

SKU ID +1.05V_VCCST GPIO25 R147 10K_4
Low High R497 IV@10K_4 SKU_ID0 R466 EV@10K_4 R168 10K_4
U39 +3V WK_GPIO27 R192 *10K_4
Reserved R179 IV@10K_4 SKU_ID1 R155 EV@10K_4
1 5
BOARD_ID0 (Default) Reserved NC VCC
1
R623 GPIO27 : If not used then use
2 C579 8.2-kΩ to 10-kΩ pull-down to GND.
BOARD_ID1 Enable on Disable on SKU_ID1 SKU_ID0 VGA H/W Setup [5,34] IMVP_PWRGD A 0.1u/10V_4
10K_4
board memory board memory
2
Signal Menu
A 3 4 IMVP_PWRGD_3V [7]
A
UMA Only 0 0 UMA Hidden UMA boot GND Y
BOARD_ID2 Default(LOW) 74AUP1G07GW
dGPU Only 0 1 GPU Hidden GPU boot
Switchable
1 0 UMA+GPU dGPU/SG UMA boot
BOARD_ID3 No DTPM DTPM (Mux) PROJECT :ZQX
Reserved Optimize Size Document Number Rev
1 1 UMA UMA/SG UMA boot 1B
BOARD_ID4 (Default) Reserved (Muxless) LPT 4/6 (GPIO/MISC)
5 4 3 2 1
5 4 3 2 1
C182
C190
C191
*1u/6.3V_4
1u/6.3V_4
1u/6.3V_4 U28M
Haswell ULT PCH (Power)
HSW_ULT_DDR3L
C203
1u/6.3V_4
+3VCC_S5
11
1.838A K9
+1.05V +1.05V_MODPHY VCCHSIO
L10
VCCHSIO +3V_RTC
1.741A M9
R212 *short_8 +V1.05S_AIDLE N8 VCCHSIO HSIO RTC AH11
P9 VCC1_05 VCCSUS3_3 AG10 C171 C170 C447
D B18 VCC1_05 VCCRTC AE7 +VCCRTCEXT 0.1u/10V_4 0.1u/10V_4 1u/6.3V_4 D
+V1.05S_AUSB3PLL VCCUSB3PLL DCPRTC
C176 B11
+V1.05S_ASATA3PLL VCCSATA3PLL
*1u/6.3V_4
18mA C193
Y20 SPI Y8 +V3.3M_PSPI 0.1u/10V_4
AA21 RSVD VCCSPI R521 *Short_6
R208 *0_6
10mA +V1.05S_APLLOPI
W21 VCCAPLL
OPI
+3V_S5
+1.05V_S5 VCCAPLL AG14 R522 *0_6 +3V
VCCASW AG13 PCH_VCC_1_1_21
C168 C172 VCCASW
10u/6.3V_6 1u/6.3V_4 +1.05V_DCPSUS3 J13 USB3
+1.05V C192
DCPSUS3 J11 +V1.05S_CORE_PCH R221 *Short_6 0.1u/10V_4
VCC1_05 +1.05V
H11
AH14 HDA VCC1_05 H15
R238 *0_6
25mA +1.05V_DCPSUS2
+V3.3DX_1.5DX_1.8DX_AUDIO VCCHDA VCC1_05 AE8 R215 *short_8
+1.05V_S5 VCC1_05 +1.05V
AF22
AH13 VRM VCC1_05 AG19
Deep Sx 0.114A DCPSUS2 CORE DCPSUSBYP
C232 +3VPCU R171 *0_6 AG20 C200 C186 C185
1u/6.3V_4 C202 22u/6.3V_8 DCPSUSBYP AE9 1u/6.3V_4 1u/6.3V_4 10u/6.3V_6
R194 *Short_6 VCCASW AF9
+3V_S5 VCCASW
+3VCC_S5 AC9 AG8
AA9 VCCSUS3_3 VCCASW AD10 +1.05V_DCPSUS1 +PCH_VCCDSW
Non Deep Sx VCCSUS3_3
GPIO/LPC
DCPSUS1
C163 +VCCPDSW AH10 AD8
1u/6.3V_4 +V3.3S_VCCPCORE V8 VCCDSW3_3 DCPSUS1
W9 VCC3_3 C195
VCC3_3 J15 1u/6.3V_4
R523 *short_8
41mA THERMAL SENSOR VCCTS1_5 K14
+3V VCC3_3 +V1.05M_VCCASW
K16
VCC3_3
C446 +V1.05M_VCCASW
0.658A R214 *short_8 +1.05V
C 22u/6.3V_8 J18 C
+V1.05S_AXCK_DCB
K19 VCCCLK SERIAL IO U8
0.109A
A20 VCCCLK VCCSDIO T9 R237 *0_6 C174 C166
+V1.05S_AXCK_LCPLL VCCACLKPLL VCCSDIO
+1.05V J17 +1.05V_S5 1u/6.3V_4 22u/6.3V_8
R21 VCCCLK
+1.05V VCCCLK
C201 1u/6.3V_4 T21 LPT LP POWER C231
C204 1u/6.3V_4 K18 VCCCLK SUS OSCILLATOR AB8 1u/6.3V_4
M20 RSVD DCPSUS4
V21 RSVD
63mA AE20 RSVD AC20
3mA +V1.5S_VCCATS R540 *Short_6
WW15 4/10 Intel +3VCC_S5 VCCSUS3_3 RSVD +1.5V
AE21 AG16
VCCDSW3 G3 can't VCCSUS3_3 USB2 VCC1_05 AG17
1mA +V3.3S_VCCPTS R226 *Short_6 +3V
boot issue.C181 VCC1_05
+VCCPDSW +PCH_VCCDSW
C208
13 OF 19 1u/6.3V_4
0.47u/25V_6
+V3.3S_VCCSDIO
17mA R175 *Short_6 +3V
PCH VCCHSIO Power +1.05V_DCPSUS4 R236 *0_6 +1.05V_S5
C160 +3V_S5 +3V_S5 [5,7,8,9,10,13,21,24,27,28,29,31,34,36]
1u/6.3V_4 +1.5V +1.5V [22,26,35]
C230 +3V +3V [2,5,7,8,9,10,13,14,15,16,17,18,21,22,23,24,25
1u/6.3V_4 +1.05V +1.05V [5,13,30,33,34,35]
+3V_RTC +3V_RTC [8,29]
+3VCC_S5 +3VCC_S5 [7,13]
+1.05V_S5 +1.05V_S5 [8,13,33,37]
+V1.05S_VCCUSBCORE R230 *short_8 +1.05V +V1.05S_AUSB3PLL +V1.05S_AUSB3PLL [9]
+V1.05S_ASATA3PLL +V1.05S_ASATA3PLL [8]
B C229 +V1.05S_AXCK_LCPLL B
+V1.05S_AXCK_LCPLL [9]
1u/6.3V_4
Power tracking
VCCAPLL power +1.05V +V1.05S_AXCK_DCB

7/2 remove LDO instead of MOS switch
+1.05V +V1.05S_APLLOPI L10 2.2uH/210mA_8
0.2A
L9 2.2uH/210mA_8
57mA
C180 C179 C188
47u/6.3V_8 47u/6.3V_8 1u/6.3V_4
C196 C184 C206

*47u/6.3V_8 *47u/6.3V_8 1u/6.3V_4
+1.05V +V1.05S_AXCK_LCPLL
PCH HDA Power L19 2.2uH/210mA_8

31mA
+1.05V_MODPHY +V1.05S_AUSB3PLL +1.05V_MODPHY +V1.05S_ASATA3PLL
11mA
A L11 2.2uH/210mA_8
41mA L18 2.2uH/210mA_8
42mA C460 C461 C462 A
+3V_S5 +V3.3DX_1.5DX_1.8DX_AUDIO 47u/6.3V_8 47u/6.3V_8 1u/6.3V_4
R216 *Short_6
C197 C198 C199 C454 C455 C457
47u/6.3V_8 47u/6.3V_8 1u/6.3V_4 47u/6.3V_8 47u/6.3V_8 1u/6.3V_4
C189
0.1u/10V_4 Quanta Computer Inc.
Place close to ball PROJECT : ZQX
1B
LPT 5/6 (POWER)
5 4 3 2 1
5 4 3 2 1
Haswell ULT (GND) 12

HSW_ULT_DDR3L HSW_ULT_DDR3L HSW_ULT_DDR3L HSW_ULT_DDR3L
U28N U28O U28P U28R
D H17 D
A11 AJ35 AP22 AV59 D33 VSS H57
A14 VSS VSS AJ39 AP23 VSS VSS AV8 D34 VSS VSS J10 N23
A18 VSS VSS AJ41 AP26 VSS VSS AW16 D35 VSS VSS J22 RSVD R23
A24 VSS VSS AJ43 AP29 VSS VSS AW24 D37 VSS VSS J59 RSVD T23
VSS VSS VSS VSS VSS VSS AT2 RSVD
A28 AJ45 AP3 AW33 D38 J63 RSVD U10
VSS VSS VSS VSS VSS VSS AU44 RSVD
A32 AJ47 AP31 AW35 D39 K1 RSVD
VSS VSS VSS VSS VSS VSS AV44
A36 AJ50 AP38 AW37 D41 K12 RSVD
VSS VSS VSS VSS VSS VSS D15
A40 AJ52 AP39 AW4 D42 L13 RSVD AL1
A44 VSS VSS AJ54 AP48 VSS VSS AW40 D43 VSS VSS L15 RSVD AM11
A48 VSS VSS AJ56 AP52 VSS VSS AW42 D45 VSS VSS L17 RSVD AP7
VSS VSS VSS VSS VSS VSS F22 RSVD
A52 AJ58 AP54 AW44 D46 L18 RSVD AU10
VSS VSS VSS VSS VSS VSS H22 RSVD
A56 AJ60 AP57 AW47 D47 L20 RSVD AU15
VSS VSS VSS VSS VSS VSS J21 RSVD
AA1 AJ63 AR11 AW50 D49 L58 RSVD AW14
AA58 VSS VSS AK23 AR15 VSS VSS AW51 D5 VSS VSS L61 RSVD AY14
AB10 VSS VSS AK3 AR17 VSS VSS AW59 D50 VSS VSS L7 RSVD
AB20 VSS VSS AK52 AR23 VSS VSS AW60 D51 VSS VSS M22
AB22 VSS VSS AL10 AR31 VSS VSS AY11 D53 VSS VSS N10 18 OF 19
AB7 VSS VSS AL13 AR33 VSS VSS AY16 D54 VSS VSS N3
AC61 VSS VSS AL17 AR39 VSS VSS AY18 D55 VSS VSS P59
AD21 VSS VSS AL20 AR43 VSS VSS AY22 D57 VSS VSS P63
AD3 VSS VSS AL22 AR49 VSS VSS AY24 D59 VSS VSS R10
AD63 VSS VSS AL23 AR5 VSS VSS AY26 D62 VSS VSS R22
AE10 VSS VSS AL26 AR52 VSS VSS AY30 D8 VSS VSS R8
AE5 VSS VSS AL29 AT13 VSS VSS AY33 E11 VSS VSS T1
AE58 VSS VSS AL31 AT35 VSS VSS AY4 E17 VSS VSS T58
AF11 VSS VSS AL33 AT37 VSS VSS AY51 F20 VSS VSS U20
C AF15 VSS VSS AL40 AT43 VSS VSS AY59 F34 VSS VSS U9 C
AF17 VSS VSS AL45 AT46 VSS VSS AY6 F38 VSS VSS V10
AF18 VSS VSS AL46 AT49 VSS VSS B20 F42 VSS VSS V3
AG1 VSS VSS AL51 AT61 VSS VSS B24 F46 VSS VSS V7
AG11 VSS VSS AL52 AT62 VSS VSS B26 F50 VSS VSS W20
AG21 VSS VSS AL54 AT63 VSS VSS B28 F54 VSS VSS W22
AG23 VSS VSS AL57 AU1 VSS VSS B32 F58 VSS VSS Y10
AG60 VSS VSS AL60 AU16 VSS VSS B36 F61 VSS VSS Y59
AG61 VSS VSS AL61 AU18 VSS VSS B4 G18 VSS VSS Y63
AG62 VSS VSS AM1 AU20 VSS VSS B40 G22 VSS VSS
AG63 VSS VSS AM17 AU22 VSS VSS B44 G3 VSS
AH17 VSS VSS AM23 AU24 VSS VSS B48 G5 VSS V58
AH19 VSS VSS AM31 AU26 VSS VSS B52 G6 VSS VSS AH46
AH20 VSS VSS AM52 AU28 VSS VSS B56 G8 VSS VSS V23
AH22 VSS VSS AN17 AU30 VSS VSS B60 H13 VSS VSS E62 VSS_SENSE_R R581 0_4
VSS VSS VSS VSS VSS VSS_SENSE VSS_SENSE [34]
AH24 AN23 AU33 C11 AH16
AH28 VSS VSS AN31 AU51 VSS VSS C14 16 OF 19 VSS R567 100/F_4
AH30 VSS VSS AN32 AU53 VSS VSS C18
AH38 VSS VSS AN40 AV14 VSS VSS C38
AH44 VSS VSS AN45 AV24 VSS VSS D12
B AH57 VSS VSS AN52 AV39 VSS VSS D23 B
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ25 VSS VSS AP10 AV49 VSS VSS D29
VSS VSS VSS 15 OF 19 VSS
14 OF 19
HSW_ULT_DDR3L
U28Q
DC_TEST_AY2_AW 2 AY2 A3 DC_TEST_A3_B3

DC_TEST_AY3_AW 3 AY3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4 TP_DC_TEST_A4
DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 TP101
TP111 TP_DC_TEST_AY60 AY60
DC_TEST_AY61_AW 61 AY61 DAISY_CHAIN_NCTF_AY60 A60 TP_DC_TEST_A60
DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 TP110
DC_TEST_AY62_AW 62 AY62 A61 DC_TEST_A61_B61
TP_DC_TEST_B2 B2 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A62 TP_DC_TEST_A62
A TP99 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 TP115 A
DC_TEST_A3_B3 B3 AV1 TP_DC_TEST_AV1 TP24
DC_TEST_A61_B61 B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 AW1 TP_DC_TEST_AW 1
DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 TP100
DC_TEST_B62_B63 B62 AW2 DC_TEST_AY2_AW 2
B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW 3
DC_TEST_C1_C2 C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW 61
C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY62_AW 62
DAISY_CHAIN_NCTF_C2
17 OF 19
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63
AW63 TP_DC_TEST_AW 63 TP112 Quanta Computer Inc.
PROJECT : ZQX
1B
LPT 6/6 (GND)
Date: W ednesday, September 03, 2014 Sheet 12 of 43
5 4 3 2 1
5 4 3 2 1
H_SYS_PWROK_XDP R594 *1K_4

+3V_S5
13
+3V CN6
31 30
XDP_DBRESET_N R619 *1K_4 32 31 30 29 NOA_STBP_0
[4] XDP_PREQ# 32 29 NOA_STBP_0 [6]
D [4] XDP_PRDY# 33 28 NOA_STBN_0 NOA_STBN_0 [6] D
34 33 28 27
CFG0 35 34 27 26 CFG8
[6] CFG0 35 26 CFG8 [6]
CFG1 36 25 CFG9
[6] CFG1 36 25 CFG9 [6]
37 24
CFG2 38 37 24 23 CFG10
[6] CFG2 38 23 CFG10 [6]
[6] CFG3 CFG3 39 22 CFG11 CFG11 [6]
40 39 22 21
41 40 21 20 NOA_STBP_1
[4] XDP_BPM#0 41 20 NOA_STBP_1 [6]
42 19 NOA_STBN_1
[4] XDP_BPM#1 42 19 NOA_STBN_1 [6]
43 18
CFG4 44 43 18 17 CFG12
[6,8] CFG4 44 17 CFG12 [6]
[6] CFG5 CFG5 45 16 CFG13 CFG13 [6]
46 45 16 15
CFG6 47 46 15 14 CFG14
[6] CFG6 47 14 CFG14 [6]
[6] CFG7 CFG7 48 13 CFG15 CFG15 [6]
49 48 13 12
R620 *1K_4 VCCST_PWRGD_XDP 50 49 12 11 CK_XDP_P_R R548 *0_4
[5,29,33] HWPG_1.05V_S5 50 11 CLK_PCIE_XDPP [9]
NBSWON# 51 10 CK_XDP_N_R R547 *0_4
51 10 CLK_PCIE_XDPN [9]
52 9
53 52 9 8 XDP_RST_R_N R312 *1K_4
[5] PWR_DEBUG 53 8 PLTRST# [7,16,21,24,26,29]
[7] SYS_PWROK H_SYS_PWROK_XDP 54 7 XDP_DBRESET_N R609 *0_4 SYS_RESET#
R595 *0_4 55 54 7 6
56 55 6 5 XDP_TDO R261 *51_4
[8,14,15,26] CLK_SDATA 56 5 +1.05V_S5
57 4 XDP_TRST_N
C [8,14,15,26] CLK_SCLK 57 4 C
[8] XDP_TCK1 58 3 XDP_TDI
59 58 3 2 XDP_TMS
[4,8] XDP_TCK0 59 2
60 1
60 1
*SEC_BSH-030-01-L-D-A-TR
+3V
C287
*0.1u/10V_4
U16
14
VCC
B XDP_TDO 2 3 B
[8] XDP_TDO 1A 1B XDP_TDO_CPU [4]
1
1OE
XDP_TDI 5 6
[8] XDP_TDI 2A 2B XDP_TDI_CPU [4]
4
2OE
[8] XDP_TMS XDP_TMS 9 8 XDP_TMS_CPU [4]

+3VCC_S5 3A 3B
10
3OE
TP23
XDP_TRST_N 12 11 XDP_TRST# [4,8]
TP14 SUSB# [7,29] 4A 4B
TP83 +3VPCU
13
TP32 PCH_SLP_S5# [7] 4OE 15
TP13 SUSC# [7,29] DPAD
TP16 PCH_SLP_A# [7] 7
GND
*74CBTLV3126
TP102 RTC_RST# [8]
TP119 NBSWON# [27,29] +1.05V +3V

SYS_RESET# U31
TP120 SYS_RESET# [7]
A A
1 5
TP17 PCH_SLP_S0# [7] NC VCC R247
1
*10K_4
2 C536
[5] VCCST_PWRGD A *0.1u/10V_4 Quanta Computer Inc.
2
3 4
GND Y PROJECT :ZQX
*74AUP1G07GW 1B
CPU/PCH XDP
5 4 3 2 1
1 2 3 4 5 6 7 8
<DDR> [3] M_A_DQS#[7:0] BYTE0_0-7 BYTE2_16-23 BYTE5_40-47 BYTE7_56-63

[3] M_A_DQS[7:0]
[3] M_A_DQ[63:0]
+SMDDR_VREF_DIMM M8
U15
BYTE1_8-15
E3 M_A_DQ0 +SMDDR_VREF_DIMM M8
U14
E3
BYTE3_24-31
M_A_DQ16 +SMDDR_VREF_DIMM M8
U13
BYTE4_32-39
E3 M_A_DQ44 +SMDDR_VREF_DIMM M8
U12
BYTE6_48-55
E3 M_A_DQ60
14
+SMDDR_VREF_DQ0 H1 VREFCA DQL0 F7 M_A_DQ2 +SMDDR_VREF_DQ0 H1 VREFCA DQL0 F7 M_A_DQ18 +SMDDR_VREF_DQ0 H1 VREFCA DQL0 F7 M_A_DQ46 +SMDDR_VREF_DQ0 H1 VREFCA DQL0 F7 M_A_DQ58
VREFDQ DQL1 F2 M_A_DQ4 VREFDQ DQL1 F2 M_A_DQ21 VREFDQ DQL1 F2 M_A_DQ45 VREFDQ DQL1 F2 M_A_DQ56
[3] M_A_A[15:0] DQL2 DQL2 DQL2 DQL2
M_A_A0 N3 F8 M_A_DQ6 M_A_A0 N3 F8 M_A_DQ22 M_A_A0 N3 F8 M_A_DQ47 M_A_A0 N3 F8 M_A_DQ59
M_A_A1 P7 A0 DQL3 H3 M_A_DQ1 M_A_A1 P7 A0 DQL3 H3 M_A_DQ17 M_A_A1 P7 A0 DQL3 H3 M_A_DQ40 M_A_A1 P7 A0 DQL3 H3 M_A_DQ57
M_A_A3 N2 A2 DQL5 G2 M_A_DQ5 M_A_A3 N2 A2 DQL5 G2 M_A_DQ20 M_A_A3 N2 A2 DQL5 G2 M_A_DQ41 M_A_A3 N2 A2 DQL5 G2 M_A_DQ61
M_A_A5 P2 A4 DQL7 M_A_A5 P2 A4 DQL7 M_A_A5 P2 A4 DQL7 M_A_A5 P2 A4 DQL7
M_A_A6 R8 A5 M_A_A6 R8 A5 M_A_A6 R8 A5 M_A_A6 R8 A5
M_A_A7 R2 A6 D7 M_A_DQ14 M_A_A7 R2 A6 D7 M_A_DQ26 M_A_A7 R2 A6 D7 M_A_DQ38 M_A_A7 R2 A6 D7 M_A_DQ50
SO-DIMMB SPD Address is 0XA4 A7 DQU0 A7 DQU0 A7 DQU0 A7 DQU0
SO-DIMMB TS Address is 0X34 M_A_A8 T8 C3 M_A_DQ13 M_A_A8 T8 C3 M_A_DQ25 M_A_A8 T8 C3 M_A_DQ37 M_A_A8 T8 C3 M_A_DQ49
M_A_A9 R3 A8 DQU1 C8 M_A_DQ10 M_A_A9 R3 A8 DQU1 C8 M_A_DQ27 M_A_A9 R3 A8 DQU1 C8 M_A_DQ34 M_A_A9 R3 A8 DQU1 C8 M_A_DQ54
M_A_A10 L7 A9 DQU2 C2 M_A_DQ8 M_A_A10 L7 A9 DQU2 C2 M_A_DQ29 M_A_A10 L7 A9 DQU2 C2 M_A_DQ33 M_A_A10 L7 A9 DQU2 C2 M_A_DQ53
M_A_A11 R7 A10/AP DQU3 A7 M_A_DQ15 M_A_A11 R7 A10/AP DQU3 A7 M_A_DQ30 M_A_A11 R7 A10/AP DQU3 A7 M_A_DQ35 M_A_A11 R7 A10/AP DQU3 A7 M_A_DQ51
M_A_A12 N7 A11 DQU4 A2 M_A_DQ9 M_A_A12 N7 A11 DQU4 A2 M_A_DQ28 M_A_A12 N7 A11 DQU4 A2 M_A_DQ36 M_A_A12 N7 A11 DQU4 A2 M_A_DQ48
M_A_A13 T3 A12/BC DQU5 B8 M_A_DQ11 M_A_A13 T3 A12/BC DQU5 B8 M_A_DQ31 M_A_A13 T3 A12/BC DQU5 B8 M_A_DQ39 M_A_A13 T3 A12/BC DQU5 B8 M_A_DQ55
M_A_A14 T7 A13 DQU6 A3 M_A_DQ12 M_A_A14 T7 A13 DQU6 A3 M_A_DQ24 M_A_A14 T7 A13 DQU6 A3 M_A_DQ32 M_A_A14 T7 A13 DQU6 A3 M_A_DQ52
M_A_A15 M7 A14 DQU7 M_A_A15 M7 A14 DQU7 M_A_A15 M7 A14 DQU7 M_A_A15 M7 A14 DQU7
A15 +1.35V_SUS A15 +1.35V_SUS A15 +1.35V_SUS A15 +1.35V_SUS
[3] M_A_BS#[2:0]
M_A_BS#0 M2 B2 M_A_BS#0 M2 B2 M_A_BS#0 M2 B2 M_A_BS#0 M2 B2
M_A_BS#1 N8 BA0 VDD#B2 D9 M_A_BS#1 N8 BA0 VDD#B2 D9 M_A_BS#1 N8 BA0 VDD#B2 D9 M_A_BS#1 N8 BA0 VDD#B2 D9
M_A_BS#2 M3 BA1 VDD#D9 G7 M_A_BS#2 M3 BA1 VDD#D9 G7 M_A_BS#2 M3 BA1 VDD#D9 G7 M_A_BS#2 M3 BA1 VDD#D9 G7
A BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 A
K2 K2 K2 K2
VDD#K2 K8 VDD#K2 K8 VDD#K2 K8 VDD#K2 K8
VDD#K8 N1 VDD#K8 N1 VDD#K8 N1 VDD#K8 N1
J7 VDD#N1 N9 M_A_CLK0 J7 VDD#N1 N9 M_A_CLK0 J7 VDD#N1 N9 M_A_CLK0 J7 VDD#N1 N9
[3] M_A_CLK0 K7 CK VDD#N9 R1 K7 CK VDD#N9 R1 K7 CK VDD#N9 R1 K7 CK VDD#N9 R1
M_A_CLK0# M_A_CLK0# M_A_CLK0#
[3] M_A_CLK0# CK VDD#R1 CK VDD#R1 CK VDD#R1 CK VDD#R1
K9 R9 M_A_CKE0 K9 R9 M_A_CKE0 K9 R9 M_A_CKE0 K9 R9
[3] M_A_CKE0 CKE VDD#R9 CKE VDD#R9 CKE VDD#R9 CKE VDD#R9
M_A_ODT0 K1 A1 M_A_ODT0 K1 A1 M_A_ODT0 K1 A1 M_A_ODT0 K1 A1

L2 ODT VDDQ#A1 A8 M_A_CS#0 L2 ODT VDDQ#A1 A8 M_A_CS#0 L2 ODT VDDQ#A1 A8 M_A_CS#0 L2 ODT VDDQ#A1 A8
[3] M_A_CS#0 CS VDDQ#A8 CS VDDQ#A8 CS VDDQ#A8 CS VDDQ#A8
J3 C1 M_A_RAS# J3 C1 M_A_RAS# J3 C1 M_A_RAS# J3 C1
[3] M_A_RAS# RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1
K3 C9 M_A_CAS# K3 C9 M_A_CAS# K3 C9 M_A_CAS# K3 C9
[3] M_A_CAS# CAS VDDQ#C9 CAS VDDQ#C9 CAS VDDQ#C9 CAS VDDQ#C9
L3 D2 M_A_WE# L3 D2 M_A_WE# L3 D2 M_A_WE# L3 D2
[3] M_A_WE# WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2
E9 E9 E9 E9
VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1
M_A_DQS0 F3 VDDQ#F1 H2 M_A_DQS2 F3 VDDQ#F1 H2 M_A_DQS5 F3 VDDQ#F1 H2 M_A_DQS7 F3 VDDQ#F1 H2
M_A_DQS1 C7 DQSL VDDQ#H2 H9 M_A_DQS3 C7 DQSL VDDQ#H2 H9 M_A_DQS4 C7 DQSL VDDQ#H2 H9 M_A_DQS6 C7 DQSL VDDQ#H2 H9
DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9
E7 A9 E7 A9 E7 A9 E7 A9
D3 DML VSS#A9 B3 D3 DML VSS#A9 B3 D3 DML VSS#A9 B3 D3 DML VSS#A9 B3
DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1
VSS#E1 G8 VSS#E1 G8 VSS#E1 G8 VSS#E1 G8
M_A_DQS#0 G3 VSS#G8 J2 M_A_DQS#2 G3 VSS#G8 J2 M_A_DQS#5 G3 VSS#G8 J2 M_A_DQS#7 G3 VSS#G8 J2
M_A_DQS#1 B7 DQSL VSS#J2 J8 M_A_DQS#3 B7 DQSL VSS#J2 J8 M_A_DQS#4 B7 DQSL VSS#J2 J8 M_A_DQS#6 B7 DQSL VSS#J2 J8
DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1
VSS#M1 M9 VSS#M1 M9 VSS#M1 M9 VSS#M1 M9
VSS#M9 P1 VSS#M9 P1 VSS#M9 P1 VSS#M9 P1
T2 VSS#P1 P9 DDR3_DRAMRST# T2 VSS#P1 P9 DDR3_DRAMRST# T2 VSS#P1 P9 DDR3_DRAMRST# T2 VSS#P1 P9
[4,15] DDR3_DRAMRST# RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
M_A_ZQ1 L8 VSS#T1 T9 M_A_ZQ2 L8 VSS#T1 T9 M_A_ZQ3 L8 VSS#T1 T9 M_A_ZQ4 L8 VSS#T1 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
B1 B1 B1 B1
VSSQ#B1 VSSQ#B1 VSSQ#B1 VSSQ#B1
2
2
B9 B9 B9 B9
R242 VSSQ#B9 D1 R234 VSSQ#B9 D1 R213 VSSQ#B9 D1 R113 VSSQ#B9 D1
VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8
240/F_4 240/F_4 240/F_4 240/F_4
VSSQ#D8 E2 VSSQ#D8 E2 VSSQ#D8 E2 VSSQ#D8 E2
J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8
1
1
L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9
J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1
L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
ESP@RAM _DDR3L ESP@RAM _DDR3L ESP@RAM _DDR3L ESP@RAM _DDR3L
Vendor P/N
Hynix
AKD5JGST400 DDR3L 1333Mhz 4Gb

Elpida BYTE0_0-7 BYTE2_16-23 BYTE5_40-47 BYTE7_56-63
AKD5JGST404 DDR3L 1600Mhz 4Gb
BYTE1_8-15 BYTE3_24-31 BYTE4_32-39 BYTE6_48-55
U32 U29 U27 U26
+SMDDR_VREF_DIMM M8 E3 M_A_DQ2 +SMDDR_VREF_DIMM M8 E3 M_A_DQ18 +SMDDR_VREF_DIMM M8 E3 M_A_DQ46 +SMDDR_VREF_DIMM M8 E3 M_A_DQ58

+SMDDR_VREF_DQ0 H1 VREFCA DQL0 F7 M_A_DQ0 +SMDDR_VREF_DQ0 H1 VREFCA DQL0 F7 M_A_DQ16 +SMDDR_VREF_DQ0 H1 VREFCA DQL0 F7 M_A_DQ44 +SMDDR_VREF_DQ0 H1 VREFCA DQL0 F7 M_A_DQ60
VREFDQ DQL1 F2 M_A_DQ6 VREFDQ DQL1 F2 M_A_DQ22 VREFDQ DQL1 F2 M_A_DQ47 VREFDQ DQL1 F2 M_A_DQ59
B M_A_A0 N3 DQL2 F8 M_A_DQ4 M_A_A0 N3 DQL2 F8 M_A_DQ21 M_A_A0 N3 DQL2 F8 M_A_DQ45 M_A_A0 N3 DQL2 F8 M_A_DQ56 B
M_A_A3 N2 A2 DQL5 G2 M_A_DQ3 M_A_A3 N2 A2 DQL5 G2 M_A_DQ23 M_A_A3 N2 A2 DQL5 G2 M_A_DQ42 M_A_A3 N2 A2 DQL5 G2 M_A_DQ63
M_A_A5 P2 A4 DQL7 M_A_A5 P2 A4 DQL7 M_A_A5 P2 A4 DQL7 M_A_A5 P2 A4 DQL7
M_A_A6 R8 A5 M_A_A6 R8 A5 M_A_A6 R8 A5 M_A_A6 R8 A5
R2 A6 D7 R2 A6 D7 R2 A6 D7 R2 A6 D7
SO-DIMMB SPD Address is 0XA4 M_A_A7 M_A_DQ13 M_A_A7 M_A_DQ25 M_A_A7 M_A_DQ37 M_A_A7 M_A_DQ49
M_A_A8 T8 A7 DQU0 C3 M_A_DQ14 M_A_A8 T8 A7 DQU0 C3 M_A_DQ26 M_A_A8 T8 A7 DQU0 C3 M_A_DQ38 M_A_A8 T8 A7 DQU0 C3 M_A_DQ50
SO-DIMMB TS Address is 0X34 A8 DQU1 A8 DQU1 A8 DQU1 A8 DQU1
M_A_A9 R3 C8 M_A_DQ8 M_A_A9 R3 C8 M_A_DQ29 M_A_A9 R3 C8 M_A_DQ33 M_A_A9 R3 C8 M_A_DQ53
M_A_A10 L7 A9 DQU2 C2 M_A_DQ10 M_A_A10 L7 A9 DQU2 C2 M_A_DQ27 M_A_A10 L7 A9 DQU2 C2 M_A_DQ34 M_A_A10 L7 A9 DQU2 C2 M_A_DQ54
M_A_A11 R7 A10/AP DQU3 A7 M_A_DQ9 M_A_A11 R7 A10/AP DQU3 A7 M_A_DQ28 M_A_A11 R7 A10/AP DQU3 A7 M_A_DQ32 M_A_A11 R7 A10/AP DQU3 A7 M_A_DQ52
M_A_A12 N7 A11 DQU4 A2 M_A_DQ11 M_A_A12 N7 A11 DQU4 A2 M_A_DQ31 M_A_A12 N7 A11 DQU4 A2 M_A_DQ39 M_A_A12 N7 A11 DQU4 A2 M_A_DQ55
M_A_A13 T3 A12/BC DQU5 B8 M_A_DQ12 M_A_A13 T3 A12/BC DQU5 B8 M_A_DQ24 M_A_A13 T3 A12/BC DQU5 B8 M_A_DQ36 M_A_A13 T3 A12/BC DQU5 B8 M_A_DQ48
M_A_A14 T7 A13 DQU6 A3 M_A_DQ15 M_A_A14 T7 A13 DQU6 A3 M_A_DQ30 M_A_A14 T7 A13 DQU6 A3 M_A_DQ35 M_A_A14 T7 A13 DQU6 A3 M_A_DQ51
M_A_A15 M7 A14 DQU7 M_A_A15 M7 A14 DQU7 M_A_A15 M7 A14 DQU7 M_A_A15 M7 A14 DQU7
A15 +1.35V_SUS A15 +1.35V_SUS A15 +1.35V_SUS A15 +1.35V_SUS
M_A_BS#0 M2 B2 M_A_BS#0 M2 B2 M_A_BS#0 M2 B2 M_A_BS#0 M2 B2

M_A_BS#1 N8 BA0 VDD#B2 D9 M_A_BS#1 N8 BA0 VDD#B2 D9 M_A_BS#1 N8 BA0 VDD#B2 D9 M_A_BS#1 N8 BA0 VDD#B2 D9
M_A_BS#2 M3 BA1 VDD#D9 G7 M_A_BS#2 M3 BA1 VDD#D9 G7 M_A_BS#2 M3 BA1 VDD#D9 G7 M_A_BS#2 M3 BA1 VDD#D9 G7
BA2 VDD#G7 K2 BA2 VDD#G7 K2 BA2 VDD#G7 K2 BA2 VDD#G7 K2
J7 VDD#N1 N9 M_A_CLK1 J7 VDD#N1 N9 M_A_CLK1 J7 VDD#N1 N9 M_A_CLK1 J7 VDD#N1 N9
[3] M_A_CLK1 CK VDD#N9 CK VDD#N9 CK VDD#N9 CK VDD#N9
K7 R1 M_A_CLK1# K7 R1 M_A_CLK1# K7 R1 M_A_CLK1# K7 R1
[3] M_A_CLK1# CK VDD#R1 CK VDD#R1 CK VDD#R1 CK VDD#R1
K9 R9 M_A_CKE1 K9 R9 M_A_CKE1 K9 R9 M_A_CKE1 K9 R9
[3] M_A_CKE1 CKE VDD#R9 CKE VDD#R9 CKE VDD#R9 CKE VDD#R9
M_A_ODT0 K1 A1 M_A_ODT0 K1 A1 M_A_ODT0 K1 A1 M_A_ODT0 K1 A1

L2 ODT VDDQ#A1 A8 M_A_CS#1 L2 ODT VDDQ#A1 A8 M_A_CS#1 L2 ODT VDDQ#A1 A8 M_A_CS#1 L2 ODT VDDQ#A1 A8
[3] M_A_CS#1 CS VDDQ#A8 CS VDDQ#A8 CS VDDQ#A8 CS VDDQ#A8
M_A_RAS# J3 C1 M_A_RAS# J3 C1 M_A_RAS# J3 C1 M_A_RAS# J3 C1
M_A_CAS# K3 RAS VDDQ#C1 C9 M_A_CAS# K3 RAS VDDQ#C1 C9 M_A_CAS# K3 RAS VDDQ#C1 C9 M_A_CAS# K3 RAS VDDQ#C1 C9
M_A_WE# L3 CAS VDDQ#C9 D2 M_A_WE# L3 CAS VDDQ#C9 D2 M_A_WE# L3 CAS VDDQ#C9 D2 M_A_WE# L3 CAS VDDQ#C9 D2
WE VDDQ#D2 E9 WE VDDQ#D2 E9 WE VDDQ#D2 E9 WE VDDQ#D2 E9
M_A_DQS0 F3 VDDQ#F1 H2 M_A_DQS2 F3 VDDQ#F1 H2 M_A_DQS5 F3 VDDQ#F1 H2 M_A_DQS7 F3 VDDQ#F1 H2
M_A_DQS1 C7 DQSL VDDQ#H2 H9 M_A_DQS3 C7 DQSL VDDQ#H2 H9 M_A_DQS4 C7 DQSL VDDQ#H2 H9 M_A_DQS6 C7 DQSL VDDQ#H2 H9
DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9
E7 A9 E7 A9 E7 A9 E7 A9
D3 DML VSS#A9 B3 D3 DML VSS#A9 B3 D3 DML VSS#A9 B3 D3 DML VSS#A9 B3
M_A_DQS#0 G3 VSS#G8 J2 M_A_DQS#2 G3 VSS#G8 J2 M_A_DQS#5 G3 VSS#G8 J2 M_A_DQS#7 G3 VSS#G8 J2
M_A_DQS#1 B7 DQSL VSS#J2 J8 M_A_DQS#3 B7 DQSL VSS#J2 J8 M_A_DQS#4 B7 DQSL VSS#J2 J8 M_A_DQS#6 B7 DQSL VSS#J2 J8
DDR3_DRAMRST# T2 VSS#P1 P9 DDR3_DRAMRST# T2 VSS#P1 P9 DDR3_DRAMRST# T2 VSS#P1 P9 DDR3_DRAMRST# T2 VSS#P1 P9
RESET VSS#P9 T1 RESET VSS#P9 T1 RESET VSS#P9 T1 RESET VSS#P9 T1
M_A_ZQ5 L8 VSS#T1 T9 M_A_ZQ6 L8 VSS#T1 T9 M_A_ZQ7 L8 VSS#T1 T9 M_A_ZQ8 L8 VSS#T1 T9
B1 B1 B1 B1
VSSQ#B1 VSSQ#B1 VSSQ#B1 VSSQ#B1
2
2
+1.35V_SUS B9 B9 B9 B9
+1.35V_SUS [4,5,15,32] VSSQ#B9 VSSQ#B9 VSSQ#B9 VSSQ#B9
R586 D1 R553 D1 R543 D1 R528 D1
+DDR_VTT_RUN VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8
+DDR_VTT_RUN [15,32] 240/F_4 240/F_4 240/F_4 240/F_4
+SMDDR_VREF_DIMM J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8
+SMDDR_VREF_DIMM [15]
1
1
J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1
C +VREF_CA_CPU NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 C
+VREF_CA_CPU [3]
+VREFDQ_SA_M3 +VREFDQ_SA_M3 [3] SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
ESP@RAM _DDR3L ESP@RAM _DDR3L ESP@RAM _DDR3L ESP@RAM _DDR3L
SP : ELPIDA DRAM P/N : AKD5JGST400

HYNIX DRAM P/N : AKD5JGQTW01 M1 solution
+1.35V_SUS
Power tracking
+1.35V_SUS R275 Vref_CA

Place these Caps near Memory Down 1.8K/F_4
+SMDDR_VREF_DIMM +3V
+VREF_CA_CPU R279 *Short_6 R280 2/F_6

C459 C298 C511 C194 C543 C458 C233 C440 C244 C158 C479 C187 C214 C280 C498 C526 R174 *1K_4 SPD_A0 R199 *1K_4
2
10u/6.3V_6 10u/6.3V_6 *10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 *10u/6.3V_6 *10u/6.3V_6 10u/6.3V_6 *10u/6.3V_6 10u/6.3V_6 *10u/6.3V_6 *10u/6.3V_6 10u/6.3V_6 *10u/6.3V_6 10u/6.3V_6 *10u/6.3V_6
M3 solution C304 R281 C525 R173 *1K_4 SPD_A1 R198 *1K_4
0.022u/16V_4 1.8K/F_4 470p/50V_4
1
R172 *1K_4 SPD_A2 R197 *1K_4
R274
C183 C435 C517 C484 C275 C249 C178 C538 C293 C456 C167 C228 C270 C297 C313 C263 24.9/F_4
*1u/6.3V_4 *1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 *1u/6.3V_4 1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 1u/6.3V_4 *1u/6.3V_4
U10
[8,13,15,26] CLK_SCLK R133 *0_4 SPD_CLK_SCLK 6 1 SPD_A0
R126 *0_4 SPD_CLK_SDATA 5 SCL A0 2 SPD_A1 +3V
[8,13,15,26] CLK_SDATA SDA A1 3 SPD_A2
A2
C222 C502 C310 C499 C213 C316 C273 C251 C212 C556 C452 C296 C207 C318 C272 C246 R146 *1K_4 7 8
+3V WP VCC
1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 *1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 4
M1 solution GND
R149 *M24C02-WMN6TP C153
+1.35V_SUS *0.1u/10V_4
WP =1 : WRITE DISABLE *1K_4
SPD address:A2
R290 Vref_DQ
C209 C314 C485 C258 C515 C469 C284 C477 C315 C509 C501 C291 C140 C503 C221 C142 1.8K/F_4
1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 *1u/6.3V_4 +SMDDR_VREF_DQ0
+VREFDQ_SA_M3 R282 *Short_6 R283 5.1/F_6

2
C327 R288 C281

M3 solution 0.022u/16V_4 1.8K/F_4 470p/50V_4
1
C505 C433 C453 C557 C540 C241 C444 C211 C173 C227 C141 C434 C143 C500 C483 C472
1u/6.3V_4 1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 1u/6.3V_4 *1u/6.3V_4 1u/6.3V_4 *1u/6.3V_4 *1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 *1u/6.3V_4 1u/6.3V_4 +1.35V_SUS
R289
24.9/F_4
M_A_ODT0 R120 30/F_4
C445 C169 C487 C522 C504 C519 C524 C529 C486 C533 C439 C530 C465 C442 C542 C164
Change to 36 ohm Modify connection on 10/25
*0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4
+DDR_VTT_RUN
D
change to 3.3p 10/28 D
M_A_WE# R112 36/F_4 M_A_CLK0 M_A_CLK1
M_A_CAS# R435 36/F_4
C554 C516 C156 C225 C261 C488 C317 C475 C512 C286 C520 C443 C165 C539 C311 C223 M_A_RAS# R443 36/F_4
*0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4 M_A_BS#0 R438 36/F_4 C553 C552
M_A_BS#1 R111 36/F_4 3.3P/50V_4 3.3P/50V_4
M_A_BS#2 R439 36/F_4 M_A_CLK0# M_A_CLK1#
M_A_CKE0 R109 36/F_4
M_A_CS#0 R108 36/F_4
+SMDDR_VREF_DIMM M_A_A0 R114 36/F_4 R434 R433 R432 R431
+DDR_VTT_RUN M_A_A1 R441 36/F_4 30/F_4 30/F_4 30/F_4 30/F_4
M_A_A2 R440 36/F_4
M_A_A3 R110 36/F_4
1
M_A_A4 R135 36/F_4

C138 C131 C425 C426 C175 C527 C555 C226 C234 C162 C308 C177 M_A_A5 R148 36/F_4
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 C130 0.047u/25V_4 0.047u/25V_4 0.047u/25V_4 0.047u/25V_4 0.047u/25V_4 0.047u/25V_4 0.047u/25V_4 0.047u/25V_4 M_A_A6 R150 36/F_4
2
10u/6.3V_6 M_A_A7 R507 36/F_4 C428 C427

M_A_A8 R480 36/F_4 0.1u/10V_4 0.1u/10V_4
M_A_A9 R122 36/F_4
M_A_A10 R437 36/F_4
+SMDDR_VREF_DQ0 Place these Caps near Memory Down CA & DQ pin M_A_A11 R118 36/F_4
M_A_A12 R115 36/F_4
M_A_A13 R457 36/F_4
C144 C148 C136 C429 C137 M_A_A14 R127 36/F_4
1
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 10u/6.3V_6 M_A_A15 R436 36/F_4

C239 C224 C451 C449 C432 C279 C326 C312
0.047u/25V_4 0.047u/25V_4 0.047u/25V_4 0.047u/25V_4 0.047u/25V_4 0.047u/25V_4 0.047u/25V_4 0.047u/25V_4
PROJECT : ZQX
2
M_A_CKE1 R107 36/F_4

M_A_CS#1 R116 36/F_4 Size Document Number Rev
1B
DDR3 MEMORY DOWNx16 A
1 2 3 4 5 6 7 8
5 4 3 2 1
[3] M_B_A[15:0]
M_B_A0
M_B_A1
M_B_A2
M_B_A3
98
97
96
95
JDIM6A
A0
A1
A2
DQ0
DQ1
DQ2
5
7
15
17
M_B_DQ17
M_B_DQ16
M_B_DQ21
M_B_DQ18
M_B_DQ[63:0] [3]
+1.35V_SUS
75
76
81
82
JDIM6B
VDD1
VDD2
VDD3
VSS16
VSS17
VSS18
44
48
49
54
15
M_B_A4 92 A3 DQ3 4 M_B_DQ23 87 VDD4 VSS19 55
D
M_B_A9 85 A8 DQ8 23 M_B_DQ3
2.48A 100 VDD9 VSS24 71
D

M_B_A11 84 A10/AP DQ10 35 M_B_DQ1 106 VDD11 VSS26 127
PC2100 DDR3 SDRAM SO-DIMM

M_B_A13 119 A12/BC# DQ12 24 M_B_DQ4 112 VDD13 VSS28 133
A15 DQ15 39 M_B_DQ8 123 VDD16 VSS31 139
PC2100 DDR3 SDRAM SO-DIMM

109 DQ16 41 M_B_DQ12 124 VDD17 VSS32 144
[3] M_B_BS#0 BA0 DQ17 VDD18 VSS33
108 51 M_B_DQ10 145
[3] M_B_BS#1 BA1 DQ18 VSS34
79 53 M_B_DQ15 199 150
[3] M_B_BS#2 BA2 DQ19 +3V VDDSPD VSS35
114 40 M_B_DQ9 151
[3] M_B_CS#0 S0# DQ20 VSS36
121 42 M_B_DQ14 77 155
[3] M_B_CS#1 S1# DQ21 NC1 VSS37
101 50 M_B_DQ11 122 156
[3] M_B_CLK0 CK0 DQ22 NC2 VSS38
103 52 M_B_DQ13 125 161
[3] M_B_CLK0# CK0# DQ23 NCTEST VSS39
102 57 M_B_DQ27 162
[3] M_B_CLK1 CK1 DQ24 VSS40
104 59 M_B_DQ31 R121 *10K_4 PM_EXTTS#1 198 167
[3] M_B_CLK1# CK1# DQ25 +3V EVENT# VSS41
73 67 M_B_DQ28 [4,14] DDR3_DRAMRST# 30 168
[3] M_B_CKE0 CKE0 DQ26 RESET# VSS42
74 69 M_B_DQ29 C537 *0.1u/10V_4 172
[3] M_B_CKE1 CKE1 DQ27 VSS43
115 56 M_B_DQ30 173
[3] M_B_CAS# CAS# DQ28 VSS44
110 58 M_B_DQ26 +SMDDR_VREF_DQ1 +SMDDR_VREF_DQ1 1 178
[3] M_B_RAS# RAS# DQ29 VREF_DQ VSS45
113 68 M_B_DQ25 126 179
[3] M_B_WE# WE# DQ30 +SMDDR_VREF_DIMM VREF_CA VSS46
R456 10K_4 DIMM1_SA0 197 70 M_B_DQ24 184
R446 10K_4 DIMM1_SA1 201 SA0 DQ31 129 M_B_DQ34 VSS47 185
+3V SA1 DQ32 VSS48
202 131 M_B_DQ35 2 189
[8,13,14,26] CLK_SCLK 200 SCL DQ33 141 M_B_DQ39 3 VSS1 VSS49 190
[8,13,14,26] CLK_SDATA SDA DQ34 143 M_B_DQ38 8 VSS2 VSS50 195
(204P)
C DQ35 VSS3 VSS51 C
116 130 M_B_DQ32 9 196
[4] M_B_ODT0_DIMM ODT0 DQ36 VSS4 VSS52
120 132 M_B_DQ33 13
[4] M_B_ODT1_DIMM ODT1 DQ37 VSS5
140 M_B_DQ36 14
11 DQ38 142 M_B_DQ37 19 VSS6
28 DM0 DQ39 147 M_B_DQ44 20 VSS7
46 DM1 DQ40 149 M_B_DQ40 25 VSS8
63 DM2
DM3
(204P) DQ41
DQ42
157 M_B_DQ46 26 VSS9
VSS10 VTT1
203 +DDR_VTT_RUN
136 159 M_B_DQ42 31 204
153 DM4 DQ43 146 M_B_DQ41 32 VSS11 VTT2
170 DM5 DQ44 148 M_B_DQ45 37 VSS12 205
187 DM6 DQ45 158 M_B_DQ43 38 VSS13 GND 206
DM7 DQ46 160 M_B_DQ47 43 VSS14 GND
M_B_DQS2 12 DQ47 163 M_B_DQ51 +VREFDQ_SB_M3 VSS15
[3] M_B_DQS2 DQS0 DQ48 +VREFDQ_SB_M3 [3]
[3] M_B_DQS0 M_B_DQS0 29 165 M_B_DQ55
M_B_DQS1 47 DQS1 DQ49 175 M_B_DQ53 +1.05V DDR3-DIMM1_H=5.2_STD
[3] M_B_DQS1 DQS2 DQ50 +1.05V [5,11,13,30,33,34,35]
[3] M_B_DQS3 M_B_DQS3 64 177 M_B_DQ48
M_B_DQS4 137 DQS3 DQ51 164 M_B_DQ52 +SMDDR_VREF_DIMM
[3] M_B_DQS4 DQS4 DQ52 +SMDDR_VREF_DIMM [14]
[3] M_B_DQS5 M_B_DQS5 154 166 M_B_DQ49
M_B_DQS6 171 DQS5 DQ53 174 M_B_DQ50 +DDR_VTT_RUN
[3] M_B_DQS6 DQS6 DQ54 +DDR_VTT_RUN [14,32]
[3] M_B_DQS7 M_B_DQS7 188 176 M_B_DQ54
M_B_DQS#2 10 DQS7 DQ55 181 M_B_DQ57 +3V
[3] M_B_DQS#2 DQS#0 DQ56 +3V [2,5,7,8,9,10,11,13,14,16,17,18,21,22,23,24,25,26,27,28,29,31,32,33,34,35,36]
[3] M_B_DQS#0 M_B_DQS#0 27 183 M_B_DQ56
M_B_DQS#1 45 DQS#1 DQ57 191 M_B_DQ58
[3] M_B_DQS#1 DQS#2 DQ58
[3] M_B_DQS#3 M_B_DQS#3 62 193 M_B_DQ59
M_B_DQS#4 135 DQS#3 DQ59 180 M_B_DQ62
[3] M_B_DQS#4 DQS#4 DQ60
[3] M_B_DQS#5 M_B_DQS#5 152 182 M_B_DQ63
M_B_DQS#6 169 DQS#5 DQ61 192 M_B_DQ61
B [3] M_B_DQS#6 DQS#6 DQ62 Power tracking B
[3] M_B_DQS#7 M_B_DQS#7 186 194 M_B_DQ60
DQS#7 DQ63
DDR3-DIMM1_H=5.2_STD
M1 solution
+1.35V_SUS
+1.35V_SUS Place these Caps near SO-DIMM R286 Vref_DQ

1.8K/F_4
+SMDDR_VREF_DQ1
+VREFDQ_SB_M3 R278 *Short_6 R285 2/F_6

+
2
C496 C492 C510 C514 C507 C518 C473 C513 C508 C482 C495 C471
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 330u/2V_7343
M3 solution C321 R295 C333
0.022u/16V_4 1.8K/F_4 470p/50V_4
1
R284
24.9/F_4
A A
+DDR_VTT_RUN +SMDDR_VREF_DIMM +3V +SMDDR_VREF_DQ1
C441 C128 C129 C135 C133 C132 C134 C466 C464 C147 C146 C334 C332
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 4.7u/6.3V_6 4.7u/6.3V_6 4.7u/6.3V_6 0.1u/10V_4 2.2u/6.3V_6 2.2u/6.3V_6 0.1u/10V_4 0.1u/10V_4 2.2u/6.3V_6
PROJECT : ZQX
1B
DDRIII SO-DIMM-1
5 4 3 2 1
1 2 3 4 5 6 7 8
16
U20A
+3V_GFX +3V_GFX
+1.05V_GFX 1/14 PCI_EXPRESS
Near GPU
C107 EV@22U/6.3VS_6 PEX_WAKE AB6 NVDD = 32.22 ~ 26.66 A +VGPU_CORE
C90 EV@22U/6.3VS_6 Follow Z09 to isolate CLK_REQ#
C91 EV@10U/6.3V_6 AA22 PEX_IOVDD R81 Under GPU U20E
2
C100 EV@10U/6.3V_6 AB23 PEX_IOVDD PEX_RST AC7 EV@10K/F_4 11/14 NVVDD
PEGX_RST# [19]
C88 EV@4.7U/6.3V_6 AC24 PEX_IOVDD C70 EV@1U/6.3V_4 K10 VDD
AD25 PEX_IOVDD PEX_CLKREQ AC6 PEX_CLKREQ# PEX_CLKREQ# 1 3 C79 EV@1U/6.3V_4 K12 VDD
CLK_PEGA_REQ# [9]
C104 EV@1U/6.3V_4 AE26 PEX_IOVDD C55 EV@1U/6.3V_4 K14 VDD
C106 EV@1U/6.3V_4 AE27 PEX_IOVDD PEX_REFCLK AE8 PU at page 9 C67 EV@1U/6.3V_4 K16 VDD
CLK_PCIE_VGA [9]
PEX_REFCLK AD8 Q12 C43 EV@4.7U/6.3V_6 K18 VDD
CLK_PCIE_VGA# [9]
A Under GPU EV@2N7002K C46 EV@4.7U/6.3V_6 L11 VDD
A
AC9 PEG_RX0_C C119 EV@0.22U/10V_4 C44 EV@4.7U/6.3V_6 L13
PEX_IOVDD + PEX_IOVDDQ = 1.042A PEX_TX0
PEX_TX0 AB9 PEG_RX0#_C C118 EV@0.22U/10V_4
PEG_RX0 [9]
PEG_RX#0 [9] R83 *0_4 C73 EV@4.7U/6.3V_6 L15
VDD
VDD
C47 EV@4.7U/6.3V_6 L17 VDD
+1.05V_GFX
PEX_RX0 AG6 C74 EV@4.7U/6.3V_6 M10 VDD
PEG_TX0 [9]
AA10 PEX_IOVDDQ PEX_RX0 AG7 C76 EV@4.7U/6.3V_6 M12 VDD
PEG_TX#0 [9]
C99 EV@22U/6.3VS_6 AA12 PEX_IOVDDQ C59 EV@4.7U/6.3V_6 M14 VDD
C89 EV@22U/6.3VS_6 AA13 PEX_IOVDDQ PEX_TX1 AB10 PEG_RX1_C C116 EV@0.22U/10V_4 C62 EV@4.7U/6.3V_6 M16 VDD
PEG_RX1 [9]
C97 EV@10U/6.3VS_6 AA16 PEX_IOVDDQ PEX_TX1 AC10 PEG_RX1#_C C117 EV@0.22U/10V_4 C60 EV@4.7U/6.3V_6 M18 VDD
PEG_RX#1 [9] +3V
C103 EV@10U/6.3VS_6 AA18 PEX_IOVDDQ N11 VDD
C98 EV@4.7U/6.3V_6 AA19 PEX_IOVDDQ PEX_RX1 AF7 N13 VDD
PEG_TX1 [9]
AA20 PEX_IOVDDQ PEX_RX1 AE7 2 1 N15 VDD
PEG_TX#1 [9]
Near GPU AA21 C395 N17
+
PEX_IOVDDQ VDD
AB22 PEX_IOVDDQ PEX_TX2 AD11 PEG_RX2_C C115 EV@0.22U/10V_4 EV@330u_2.5V_3528 P10 VDD
PEG_RX2 [9]
C105 EV@1U/6.3V_4 AC23 PEX_IOVDDQ PEX_TX2 AC11 PEG_RX2#_C C114 EV@0.22U/10V_4 C417 P12 VDD
PEG_RX#2 [9]
C102 EV@1U/6.3V_4 AD24 PEX_IOVDDQ *0.1U/10V_4 P14 VDD
AE25 PEX_IOVDDQ PEX_RX2 AE9 P16 VDD
PEG_TX2 [9]
5
Under GPU AF26 PEX_IOVDDQ PEX_RX2 AF9 P18 VDD
PEG_TX#2 [9]
AF27 PEX_IOVDDQ SYS_PEX_RST_MON# 2 R11 VDD
PEX_TX3 AC12 PEG_RX3_C C113 EV@0.22U/10V_4 4 PEGX_RST# C77 EV@22U/6.3V_8 R13 VDD
PEG_RX3 [9]
PEX_TX3 AB12 PEG_RX3#_C C112 EV@0.22U/10V_4 R397 *0_4 1 C75 EV@10U/6.3VS_6 R15 VDD
PEG_RX#3 [9] [19] GPU_PEX_RST_HOLD#
R17 VDD
PEX_RX3 AG9 U22 C61 EV@4.7U/6.3VS_6 T10 VDD
PEG_TX3 [9]
3
PEX_RX3 AG10 *MC74VHC1G08DFT2G R399 C58 EV@4.7U/6.3VS_6 T12 VDD
PEG_TX#3 [9]
EV@100K/F_4 C45 EV@4.7U/6.3VS_6 T14 VDD
PEX_TX4 AB13 C42 EV@4.7U/6.3VS_6 T16 VDD
AC13 C72 EV@4.7U/6.3VS_6 T18
PEX_PLL_HVDD + PEX_TX4
U11
VDD
VDD
PEX_SVDD_3V3 = 143mA PEX_RX4 AF10
AE10
Near GPU U13
U15
VDD
PEX_RX4 VDD
B U17 VDD B
PEX_TX5 AD14 R398 V10 VDD
AA8 PEX_PLL_HVDD PEX_TX5 AC14 +3V EV@0_4 V12 VDD
+3V_GFX
AA9 PEX_PLL_HVDD V14 VDD
C92 EV@0.1U/10V_4 PEX_RX5 AE12 V16 VDD
C96 EV@4.7U/6.3V_6 PEX_RX5 AF12 V18 VDD
C95 EV@4.7U/6.3V_6 AB8 PEX_SVDD_3V3
Near GPU PEX_TX6 AC15 C416
PEX_TX6 AB15 EV@0.1U/10V_4 ESP@N14P-GV2
5
PEX_RX6 AG12
PEX_RX6 AG13 2
[7,13,21,24,26,29] PLTRST#
4
AB16 1 SYS_PEX_RST_MON# [19]
PEX_TX7 [10] DGPU_HOLD_RST#
PEX_TX7 AC16
U23
3
PEX_RX7 AF13 EV@MC74VHC1G08DFT2G
PEX_RX7 AE13
PEX_TX8 AD17
NC
PEX_TX8 AC17
NC
Un-stuff Sys_PEX_RST_MON# , stuff PEGX_RST# for not GC6
8mils width PEX_RX8 AE15
NC
(0.2MM) NC PEX_RX8 AF15 stuff Sys_PEX_RST_MON# for GC6
VDD33
F2 AC18
[36] VGA_VCCSENSE VDD_SENSE NC PEX_TX9
AB18
+3V_GFX/
NC PEX_TX9
+3V_MAIN
F1 GND_SENSE PEX_RX9 AG15 t>0
[36] VGA_VSSSENSE NC
AG16 NVDD
C
NC PEX_RX9
U20C VDD33 = 56mA +VGPU_CORE C
PEX_TX10 AB19 14/14 XVDD/VDD33
NC +3V_GFX
PEX_TX10 AC19
NC
AD10 NC VDD33 G10 Near GPU PXE_VDD
AF16 AD7 G12 C37 EV@4.7U/6.3V_6
NC PEX_RX10
AE16 B19
NC VDD33
G8
+1.05V_GFX
NC PEX_RX10 NC VDD33 C94 EV@1U/10V_6 t>0
VDD33 G9 FBVDDQ
AD20 C24 EV@0.1U/10V_4
NC PEX_TX11
AC20 F11
+1.35_GFX
NC PEX_TX11 3V3AUX_NC
Under GPU N15x Power on sequance
PEX_RX11 AE18 V5 FERMI_RSVD1_NC
NC
PEX_RX11 AF18 V6 FERMI_RSVD2_NC
NC
PEX_TX12 AC21
NC +3V_MAIN
AB21
NC PEX_TX12
Power down
R410 *200/F_4 PEX_TSTCLK AF22 AG18
PEX_TSTCLK# AE22
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT
NC
NC
PEX_RX12
PEX_RX12 AG19
CONFIGURABLE
POWER CHANNELS C39 EV@4.7U/6.3V_6 sequence
CX300T30001 Change to 0ohm * nc on substrate C38 EV@1U/10V_6
R80 EV@0_4 PEX_PLLVDD PEX_TX13 AD23
+1.05V_GFX NC
NC PEX_TX13 AE23 G1 XPWR_G1
Near GPU G2 XPWR_G2 C26 EV@0.1U/10V_4
C101 EV@4.7U/6.3V_6 AA14 PEX_PLLVDD PEX_RX13 AF19 G3 XPWR_G3 C25 EV@0.1U/10V_4
NC
C86 EV@1U/6.3V_4 AA15 PEX_PLLVDD NC PEX_RX13 AE19 G4 XPWR_G4
G5 XPWR_G5 Under GPU
C85 EV@0.1U/10V_4 PEX_TX14 AF24 G6 XPWR_G6
NC
Under GPU PEX_TX14 AE24 G7 XPWR_G7
NC
PEX_PLLVDD = 130mA NC PEX_RX14 AE21
PEX_RX14 AF21 V1 XPWR_V1
NC
D R409 EV@10K/F_4 TESTMODE AD9 TESTMODE V2 XPWR_V2
D
PEX_TX15 AG24
NC
NC PEX_TX15 AG25
PEX_RX15 AG21
NC
PEX_RX15 AG22 W1 XPWR_W1
NC
W2
PEX_TERMP AF25
GF117 GF119 W3
W4
XPWR_W2
XPWR_W3 Quanta Computer Inc.
R86 EV@2.49K/F_4 PEX_TERMP XPWR_W4
PROJECT : ZQX
ESP@N14P-GV2 ESP@N14P-GV2 Size Document Number Rev
1B
N14M-GS (PCIE I/F) /NVDD
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
EC_FB_CLAMP R50 *0_4 U20B
17
2/14 FBA VMA_DQ[63:0]
VMA_DQ[63:0] [20]
R43 EV@10K/F_4 FB_CLAMP F3 NC GF119 FBA_D0 E18 VMA_DQ0
FBA_D1 F18 VMA_DQ1
For GC6 2.0 and 1.0 FB_CLAMP FBA_D2 E16 VMA_DQ2
GF117
no stuff GC6_FB_EN F17 VMA_DQ3
FBA_D3
FBA_D4 D20 VMA_DQ4 FBVDDQ + FBVDD = 3.116A U20F
FBA_D5 D21 VMA_DQ5 13/14 GND
FBA_D6 F20 VMA_DQ6 +1.5V_GFX U20D A2 GND GND M13
FBA_D7 E21 VMA_DQ7 12/14 FBVDDQ AB17 GND GND M15
PV modify FBA_D8 E15 VMA_DQ8 AB20 GND GND M17
FBA_D9 D15 VMA_DQ9 C29 EV@0.1U/10V_4 B26 FBVDDQ AB24 GND GND N10
FBA_ODT_L FBA_CMD2 R45 EV@10K/F_4 FBA_D10 F15 VMA_DQ10 C52 EV@0.1U/10V_4 C25 FBVDDQ AC2 GND GND N12
FBA_D11 F13 VMA_DQ11 E23 FBVDDQ AC22 GND GND N14
A FBA_ODT_H FBA_CMD18 R385 EV@10K/F_4 FBA_D12 C13 VMA_DQ12 E26 FBVDDQ AC26 GND GND N16 A
FBA_D13 B13 VMA_DQ13 C48 EV@1U/10V_6 F14 FBVDDQ AC5 GND GND N18
FBA_RST# FBA_CMD5 R56 EV@10K/F_4 FBA_D14 E13 VMA_DQ14 C54 EV@1U/10V_6 F21 FBVDDQ AC8 GND GND P11
FBA_D15 D13 VMA_DQ15 C35 EV@4.7U/6.3V_6 G13 FBVDDQ AD12 GND GND P13
FBA_CKE_L FBA_CMD3 R41 EV@10K/F_4 FBA_D16 B15 VMA_DQ16 C93 EV@10U/6.3V_6 G14 FBVDDQ AD13 GND GND P15
FBA_D17 C16 VMA_DQ17 C83 EV@22U/6.3VS_6 G15 FBVDDQ A26 GND GND P17
FBA_CKE_H FBA_CMD19 R82 EV@10K/F_4 FBA_D18 A13 VMA_DQ18 C36 EV@4.7U/6.3V_6 G16 FBVDDQ AD15 GND GND P2
FBA_D19 A15 VMA_DQ19 G18 FBVDDQ AD16 GND GND P23
FBA_D20 B18 VMA_DQ20 G19 FBVDDQ AD18 GND GND P26
FBA_D21 A18 VMA_DQ21 G20 FBVDDQ AD19 GND GND P5
FBA_D22 A19 VMA_DQ22 G21 FBVDDQ AD21 GND GND R10
FBA_D23 C19 VMA_DQ23 H24 FBVDDQ AD22 GND GND R12
FBA_D24 B24 VMA_DQ24 H26 FBVDDQ AE11 GND GND R14
FBA_D25 C23 VMA_DQ25 J21 FBVDDQ AE14 GND GND R16
FBA_D26 A25 VMA_DQ26 K21 FBVDDQ AE17 GND GND R18
FBA_D27 A24 VMA_DQ27 L22 FBVDDQ AE20 GND GND T11
FBA_D28 A21 VMA_DQ28 L24 FBVDDQ AB11 GND GND T13
FBA_D29 B21 VMA_DQ29 L26 FBVDDQ AF1 GND GND T15
FBA_D30 C20 VMA_DQ30 M21 FBVDDQ AF11 GND GND T17
FBA_D31 C21 VMA_DQ31 N21 FBVDDQ AF14 GND GND U10
FBA_D32 R22 VMA_DQ32 R21 FBVDDQ AF17 GND GND U12
C27 FBA_CMD0 FBA_D33 R24 VMA_DQ33 T21 FBVDDQ AF20 GND GND U14
[20] FBA_CMD0
TP78 FBA_CMD1 C26 FBA_CMD1 FBA_D34 T22 VMA_DQ34 V21 FBVDDQ AF23 GND GND U16
E24 FBA_CMD2 FBA_D35 R23 VMA_DQ35 W 21 FBVDDQ AF5 GND GND U18
[20] FBA_CMD2
F24 FBA_CMD3 FBA_D36 N25 VMA_DQ36 AF8 GND GND U2
[20] FBA_CMD3
D27 FBA_CMD4 FBA_D37 N26 VMA_DQ37 AG2 GND GND U23
[20] FBA_CMD4
D26 FBA_CMD5 FBA_D38 N23 VMA_DQ38 AG26 GND GND U26
[20] FBA_CMD5
F25 FBA_CMD6 FBA_D39 N24 VMA_DQ39 AB14 GND GND U5
[20] FBA_CMD6
F26 FBA_CMD7 FBA_D40 V23 VMA_DQ40 B1 GND GND V11
[20] FBA_CMD7
F23 FBA_CMD8 FBA_D41 V22 VMA_DQ41 B11 GND GND V13
[20] FBA_CMD8
B G22 FBA_CMD9 FBA_D42 T23 VMA_DQ42 B14 GND GND V15 B
[20] FBA_CMD9
G23 FBA_CMD10 FBA_D43 U22 VMA_DQ43 B17 GND GND V17
[20] FBA_CMD10
G24 FBA_CMD11 FBA_D44 Y24 VMA_DQ44 B20 GND GND Y2
[20] FBA_CMD11
F27 FBA_CMD12 FBA_D45 AA24 VMA_DQ45 B23 GND GND Y23
[20] FBA_CMD12
G25 FBA_CMD13 FBA_D46 Y22 VMA_DQ46 B27 GND GND Y26
[20] FBA_CMD13
G27 FBA_CMD14 FBA_D47 AA23 VMA_DQ47 B5 GND GND Y5
[20] FBA_CMD14
G26 FBA_CMD15 FBA_D48 AD27 VMA_DQ48 B8 GND
[20] FBA_CMD15
M24 FBA_CMD16 FBA_D49 AB25 VMA_DQ49 E11 GND
[20] FBA_CMD16
TP11 FBA_CMD17 M23 FBA_CMD17 FBA_D50 AD26 VMA_DQ50 E14 GND
K24 FBA_CMD18 FBA_D51 AC25 VMA_DQ51 E17 GND
[20] FBA_CMD18
K23 FBA_CMD19 FBA_D52 AA27 VMA_DQ52 E2 GND
[20] FBA_CMD19
M27 FBA_CMD20 FBA_D53 AA26 VMA_DQ53 E20 GND
[20] FBA_CMD20
M26 FBA_CMD21 FBA_D54 W 26 VMA_DQ54 E22 GND
[20] FBA_CMD21
M25 FBA_CMD22 FBA_D55 Y25 VMA_DQ55 E25 GND
[20] FBA_CMD22
K26 FBA_CMD23 FBA_D56 R26 VMA_DQ56 E5 GND
[20] FBA_CMD23
K22 FBA_CMD24 FBA_D57 T25 VMA_DQ57 E8 GND
[20] FBA_CMD24
J23 FBA_CMD25 FBA_D58 N27 VMA_DQ58 H2 GND
[20] FBA_CMD25 +1.5V_GFX
J25 FBA_CMD26 FBA_D59 R27 VMA_DQ59 H23 GND
[20] FBA_CMD26
J24 FBA_CMD27 FBA_D60 V26 VMA_DQ60 H25 GND
[20] FBA_CMD27
K27 FBA_CMD28 FBA_D61 V27 VMA_DQ61 FB_CAL_PD_VDDQ D22 FB_CAL_PD_VDDQ R44 EV@40.2/F_4 H5 GND
[20] FBA_CMD28
K25 FBA_CMD29 FBA_D62 W 27 VMA_DQ62 K11 GND
[20] FBA_CMD29
J27 FBA_CMD30 FBA_D63 W 25 VMA_DQ63 K13 GND
[20] FBA_CMD30
TP79 FBA_CMD31 J26 FBA_CMD31 FB_CAL_PU_GND C24 FB_CAL_PU_GND R32 EV@42.2/F_4 K15 GND
K17 GND
FBA_DQM0 D19 VMA_DM0 L10 GND
D14 VMA_DM1 VMA_DM[7:0] [20] B25 FB_CAL_TERM_GND L12
FBA_DQM1 FB_CALTERM_GND R29 EV@51.1/F_4 GND
FBA_DQM2 C17 VMA_DM2 L14 GND
FBA_DQM3 C22 VMA_DM3 L16 GND
FBA_DQM4 P24 VMA_DM4 ESP@N14P-GV2 L18 GND
+1.5V_GFX FBA_DQM5 W 24 VMA_DM5 L2 GND
C
FBA_DQM6 AA25 VMA_DM6 L23 GND C
R53 *60.4_4 F22 FBA_DEBUG0 FBA_DQM7 U25 VMA_DM7 L25 GND
R58 *60.4_4 J22 FBA_DEBUG1 L5 GND GND AA7
M11 GND GND AB7
FBA_DQS_WP0 E19 VMA_WDQS0
C15 VMA_WDQS1 VMA_WDQS[7:0] [20]
FBA_DQS_WP1
D24 FBA_CLK0 FBA_DQS_WP2 B16 VMA_WDQS2
[20] VMA_CLK0
D25 FBA_CLK0 FBA_DQS_WP3 B22 VMA_WDQS3 ESP@N14P-GV2
[20] VMA_CLK0#
N22 FBA_CLK1 FBA_DQS_WP4 R25 VMA_WDQS4
[20] VMA_CLK1
M22 FBA_CLK1 FBA_DQS_WP5 W 23 VMA_WDQS5
[20] VMA_CLK1#
FBA_DQS_WP6 AB26 VMA_WDQS6
FBA_DQS_WP7 T26 VMA_WDQS7 +3V_GFX
D18 FBA_WCK01 FBA_DQS_RN0 F19 VMA_RDQS0 +3V

C18 C14 VMA_RDQS[7:0] [20]
FBA_WCK01 FBA_DQS_RN1 VMA_RDQS1 R358
D17 FBA_WCK23 FBA_DQS_RN2 A16 VMA_RDQS2 DGPU_PGOK-1 EV@4.7K_4
D16 FBA_WCK23 FBA_DQS_RN3 A22 VMA_RDQS3
3
T24 FBA_WCK45 FBA_DQS_RN4 P25 VMA_RDQS4 R347
U24 FBA_WCK45 FBA_DQS_RN5 W 22 VMA_RDQS5 R364 EV@4.7K_4 DGPU_POK4 2 Q32 EV@4.7K_4
[37] HWPG_1.5VGFX DGPU_PWROK [10]
V24 FBA_WCK67 FBA_DQS_RN6 AB27 VMA_RDQS6 EV@METR3904-G
3
V25 FBA_WCK67 FBA_DQS_RN7 T27 VMA_RDQS7
1
FB_PLLAVDD = 55mA C383
+1.05V_GFX *1000P/50V_4 2 Q31 R349
+3V EV@DTC144EUA EV@100K/F_4
L8 EV@BLM15PX331SN1D +FB_PLLAVDD F16 FB_PLLAVDD
1
C69 EV@22U/6.3VS_6 P22 FB_PLLAVDD C378
C64 EV@0.1U/10V_4 EV@1000P/50V_4
C22 EV@0.1U/10V_4 H22 FB_DLLAVDD GF119 C377
D C34 EV@0.1U/10V_4 C375 *0.1u/10V_4 EV@0.1U/10V_4 D
5
FB_PLLAVDD GF117
GPU_PWR_GD ,PD at GPU power side
FB_DLLAVDD = 15mA 2
[36] GPU_PWR_GD R337 EV@0_4
4
FBVDDQ_EN [37]
[10,19] GC6_FB_EN R348 EV@0_4 1
PROJECT :U82
INT
FB_VREF_PROBE D23
[19,29] EC_FB_CLAMP R342 *0_4
U19
3
EV@SN74AHC1G32DCKR R346
ESP@N14P-GV2 stuff EC_FB_CLAMP for not GC6 EV@100K/F_4 Size Document Number Rev
Custom 1B
For support GC6 N14M-GS (MEMORY/GND)
stuff GC6_FB_EN for GC6
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
U20G U20J U20K
AA6
4/14 IFPAB
GF119
IFPAB_RSET
GF117
NC
GF117
NC
NC
GF119
IFPA_TXC
IFPA_TXC
AC4
AC3
7/14 IFPEF
GF119 GF117
GF117
NC
NC
DVI-DL
I2CY_SDA
I2CY_SCL
GF119
DVI-SL/HDMI
I2CY_SDA
I2CY_SCL
DP
IFPE_AUX
IFPE_AUX
J3
J2
W5
AE2
3/14 DACA
GF119
DACA_VDD
DACA_VREF
GF117
NC
TSEN_VREF
GF117
NC
NC
GF119
I2CA_SCL
I2CA_SDA
B7 I2CA_SCL R352
A7 I2CA_SDA R357
EV@2.2K_4
EV@2.2K_4
18
IFPA_TXD0 Y3 J7 IFPEF_PLLVDD AF2 DACA_RSET DACA_HSYNC AE3
NC NC NC NC
IFPA_TXD0 Y4 DACA_VSYNC AE4
NC NC
IFPE_L3 J1
NC TXC TXC
V7 IFPAB_PLLVDD IFPE_L3 K1
NC NC TXC TXC
NC IFPA_TXD1 AA2 K7 IFPEF_PLLVDD NC DACA_RED AG3
NC
W7 IFPAB_PLLVDD IFPA_TXD1 AA3 IFPE_L2 K3
NC NC NC TXD0 TXD0
A
IFPE_L2 K2 DACA_GREEN AF4 A
NC TXD0 TXD0 NC
IFPA_TXD2 AA1 K6 IFPEF_RSET IFPE_L1 M3 DACA_BLUE AF3

NC NC NC TXD1 TXD1 NC
NC IFPA_TXD2 AB1 IFPE_L1 M2
NC TXD1 TXD1
IFPE_L0 M1 27M_XTAL_IN_R
AA5 NC TXD2 TXD2 N1 27M_XTAL_OUT
NC IFPA_TXD3 NC TXD2 TXD2 IFPE_L0
IFPA_TXD3 AA4 ESP@N14P-GV2 Y6
NC
1 3
IFPE 2 4
IFPB_TXC AB4
NC
IFPB_TXC AB5 PLLVDD = 38mA C381 EV@27MHZ C380
NC
NC HPD_E HPD_E GPIO18 C2 EV@10p/50V_4 EV@10p/50V_4
GF119 GF117 L6 EV@BLM15PX331SN1D NV_PLLVDD
+1.05V_GFX
W6 IFPA_IOVDD IFPB_TXD4 AB2 C51 EV@0.1U/10V_4
NC NC
IFPB_TXD4 AB3 C49 EV@22U/6.3VS_6
NC GF119 GF117
Y6 IFPB_IOVDD NC
H6 IFPE_IOVDD NC
NC IFPB_TXD5 AD2 GF119
IFPB_TXD5 AD3 J6 IFPF_IOVDD GF117 SP_PLLVDD = 17mA U20M
NC NC DVI-DL DVI-SL/HDMI DP
9/14 XTAL_PLL
NC IFPF_AUX H4 L7 EV@BLM15PX181SN1D SP_PLLVDD
I2CZ_SDA +1.05V_GFX
IFPB_TXD6 AD1 NC I2CZ_SCL IFPF_AUX H3 C56 EV@0.1U/10V_4 L6 PLLVDD
NC
NC IFPB_TXD6 AE1 C57 EV@0.1U/10V_4 M6 SP_PLLVDD
C66 EV@4.7U/6.3V_6
NC TXC IFPF_L3 J5 C65 EV@22U/6.3VS_6 N6 VID_PLLVDD GF119
IFPB_TXD7 AD5 NC TXC IFPF_L3 J4
NC
IFPB_TXD7 AD4
NC NC GF117
NC TXD3 TXD0 IFPF_L2 K5 VID_PLLVDD = 41mA
NC IFPF_L2 K4
TXD3 TXD0
B B
NC TXD4 TXD1 IFPF_L1 L4 R350 EV@10K/F_4 XTAL_SSIN A10 XTALSSIN XTALOUTBUFF C10 BXTALOUT R356 EV@10K/F_4
IFPF NC TXD4 TXD1 IFPF_L1 L3
NC GPIO14 B3
IFPAB NC TXD5 TXD2 IFPF_L0
IFPF_L0
M5
M4
27M_XTAL_IN_R C11 XTALIN XTALOUT B10 27M_XTAL_OUT
NC TXD5 TXD2
ESP@N14P-GV2 ESP@N14P-GV2
U20H
5/14 IFPC
IFPC NC HPD_F GPIO19 F7
GF119 GF117
T6 IFPC_RSET GF117 GF119
NC
DVI/HDMI DP
M7 IFPC_PLLVDD NC NC I2CW_SDA IFPC_AUX N5 ESP@N14P-GV2

N7 IFPC_PLLVDD NC I2CW_SCL IFPC_AUX N4
NC
N3
3V MAIN POWER
NC TXC IFPC_L3
NC IFPC_L3 N2
TXC
IFPC_L2 R3 +3V_GFX
NC TXD0 +3V_GFX
IFPC_L2 R2
NC TXD0
TXD1 IFPC_L1 R1 60mil

NC
NC TXD1 IFPC_L1 T1 R367
*10K_4
1
IFPC_L0 T3 C390
NC TXD2 +3V_GFX
C
IFPC_L0 T2 *0.022U/25V_4 R376 C
NC TXD2
EV@0_8
R368 *200K_4 2
P6 IFPC_IOVDD NC GPIO15 C3 R363

NC
3
EV@10K_4 Q34 +3V_MAIN

*AO3413
3
ESP@N14P-GV2 C389
2 60mil
[19] 3V_MAIN_EN
U20I *0.022U/25V_4
6/14 IFPD Q33 N15V stuff not support GC6.
*2N7002K 1A-7 2013/10/21 add R5331 for not GC6 support.
GF119 GF117
1
U6 GF117 GF119
IFPD_RSET NC
DVI/HDMI DP
T7 IFPD_PLLVDD I2CX_SDA IFPD_AUX P4

NC NC
IFPD_AUX P3 +3V_GFX
NC I2CX_SCL
R7 IFPD_PLLVDD NC
IFPD_L3 R5
NC TXC
IFPD_L3 R4 +3V
NC TXC
R401
IFPD_L2 T5 EV@4.7K_4
NC TXD0
IFPD_L2 T4
NC TXD0
R383 3V_MAIN_PWGD
U4 3V_MAIN_PWGD [36,37]
NC TXD1 IFPD_L1 EV@4.7K_4
3
IFPD NC TXD1 IFPD_L1 U3

R386
D
IFPD_L0 V4 2 *100K/F_4 D
NC TXD2 +3V_MAIN
IFPD_L0 V3
NC TXD2
3
R381 EV@4.7K_4 2 Q37

1
C402 EV@DTC144EU
R6 IFPD_IOVDD GPIO17 D4 Q36 EV@1000p/50V_4
GF119 NC
1
NC GF117
C398
*1000p/50V_4
EV@MMBT3904-7-F +1.05V_GFX and GPU core power EN PROJECT :U82
ESP@N14P-GV2 Custom 1B
N14M-GS (DISPLAY)
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+3V_MAIN +3V_GFX
TP8 E10
U20L
10/14 MISC2
VMON_IN0
+3V_GFX R361
*4.99K/F_4
R360
*4.99K/F_4
R359
*4.99K/F_4
Default: HYNIX
R20
SP@49.9K/F_4
R19
*4.99K/F_4
R17
SP@10K/F_4
R21
SP@10K/F_4
R18
*10K/F_4
19
TP10 F10 VMON_IN1 ROM_CS D12 ROM_CS R23 EV@10K_4
For N15S-GT sku STRAP0
ROM_SI B12 ROM_SI ROM_SI 4H DM 9S STRAP1
N15S-GT device ID=0x0FE4 A12 ROM_SO ROM_SO 0 0 1 1(0=R36 1=R20) STRAP2
ROM_SO
R3=40.3k pull down. STRAP0 D1 STRAP0 ROM_SCLK C12 ROM_SCLK ROM_SCLK 1 0 0 0 STRAP3
1.ROM_SCLK =4.99K pull down STRAP1 D2 2 1 1 0 STRAP4
STRAP1 3 0 1 1(0=R37 1=R21)
A
2.ROM_SO = 4.99K pull down STRAP2 E4 STRAP2
A
3.ROM_SI= Memory strap setting STRAP3 E3 STRAP3

STRAP4 D3 R355 R354 R353
3.STRAP0 = 50k Pull pu. STRAP4
GMS@4.99K/F_4 GMS@4.99K/F_4 GMS@4.99K/F_4 R36 R35 R33 R37 R34
4.Strap4~1 = reserve Pull pu SP@10K/F_4 GM@10K/F_4 SP@10K/F_4 SP@10K/F_4 GM@10K/F_4
GF119 GF117
and Pull down
C1 STRAP5_NC NC
For N15V-GL-B and N15V-GM-B sku BUFRST D11 N15S Based on RVL. N15S-GT
Board_ID0= N15V pull down10k.
R52 GT@40.2K/F_4 F6 MULTISTRAP_REF0_GND PGOOD D10 STRAP1---> 50k PU
H=N15V-GM,L=N15V-GL Pull Down 4.99k for N15S-GT. N15V-GM\GL
Device ID=0x1140 R3 GF119 GF117 Pull Down 10k for N15V. STRAP4---> 10k PD
R3= N.C. R14 *10K/F_4 +3V_GFX N15S Strap0 pull up 50k, strap1~4 reverve only.
1.ROM_SCLK =10K pull down. F4 MULTISTRAP_REF1_GND N15V Strap4 pull down 10k, strap0~3 based on RVL binary setting.
NC
E9 SYS_PEX_RST_MON#
2.ROM_SI= 10k pull down F5 MULTISTRAP_REF2_GND
CEC SYS_PEX_RST_MON# [16] Logical Strap Bit Mapping
3.ROM_SO= 10k pull down NC +3V_GFX
4.Strap3~0 = RVL memory +3V_MAIN 4.99k CS24992FB26 PU-VDD PD
binary mode setting. 10k CS31002FB26
ESP@N14P-GV2 15k CS31502FB24
5.Strap4 =10k pull down 20k CS32002FB29 4.99K 1000 0000
R343 R344 24.9k CS32492FB16
Q30 EV@4.7K_4 EV@4.7K_4 30.1k CS33012FB18 10K 1001 0001
5 34.8k CS33482FB22
U20N 45.3k CS34532FB18 15K 1010 0010
3 4 GPUT_CLK_L
8/14 MISC1
I2CS_SCL D9 GPUT_CLK_L
[8,29] 2ND_MBCLK 20K 1011 0011
D8 GPUT_DATA_L
I2CS_SDA
2 24.9K 1100 0100
A9 DGPU_EDIDCLK R351 EV@2.2K_4
B
I2CC_SCL
I2CC_SDA B9 DGPU_EDIDDATA R24 EV@2.2K_4 [8,29] 2ND_MBDATA
6 1 GPUT_DATA_L 30.1K 1101 0101 B
EC/S5 VGA/VGA 34.8K 1110 0110

TP9 THERM- E12 GF117 GF119 EV@2N7002DW
THERMDN
NC I2CB_SCL C9 N12E_SCL R25 EV@2.2K_4 45.3K 1111 0111
TP7 THERM+ F12 THERMDP I2CB_SDA C8 N12E_SDA R26 EV@2.2K_4
NC
R345 EV@0_4
TP87 JTAG_TCK AE5 JTAG_TCK R338 *0_4 VRAM Configuration Table

EC_FB_CLAMP [17,29]
TP88 JTAG_TMS AD6 JTAG_TMS 1 3 R341 EV@0_4 GC6_FB_EN [10,17]
TP86 JTAG_TDI AE6 JTAG_TDI
TP85 JTAG_TDO AF6 JTAG_TDO +3V_GFX ROM_SI DESCRIPTION Vendor Vendor P/N QCI P/N STN P/N
JTAG_TRST# AG4 JTAG_TRST GPIO0 C6 FB_CLAMP_M0N Q29 R339
2
GPIO1 B2 *2N7002K EV@10K/F_4 0000 DDR3(L) 256MBx16x4, 64bit,1000MHz( HYNIX H5TC4G63AFR-11C AKD5PGWTW05 AKD5PGWTW13
GPIO2 D6 R64 *0_4 0010(0101) DDR3(L) 256MBx16x4, 64bit,,1000MHz(900MHz) SAMSUNG K4W4G1646D-BC1A
GPIO3 C7 +3V_GFX 0110(1001) DDR3(L) 128MBx16x4, 64bit,1000MHz(900MHz) HYNIX H5TC2G63FFR-11C
F9 R62 R75 *0_4 0111(1010) DDR3(L) 128MBx16x4, 64bit,1000MHz(900MHz) MICRO
GPIO4 FB_CLAMP_REQ# [29] MT41J128M16JT-093G:K
GPIO5 A3 3V_MAIN_EN 3V_MAIN_EN [18] *10K/F_4 1000(1011) DDR3(L) 128MBx16x4, 64bit,,1000MHz(900MHz) SAMSUNG K4W2G1646Q-BC1A
GPIO6 A4 FB_CLAMP_REQ#_R 1 3 R74 *0_4 0001(0100) DDR3(L) 128MBx16x4, 64bit,1000MHz(900MHz) MICRO MT41J256M16HA-093G:E
+3V_GFX DGPU_EVENT# [10]
GPIO7 B6
GPIO8 A6 VGA_OVT# Q11
GPIO9 F8 R644 EV@10K/F_4 R61 *2N7002K
2
GPIO10 C5 EV@10K/F_4 Strap
GPIO11 E7 PWM-VID [36] [3:0] DESCRIPTION Vendor Vendor P/N QCI P/N Note
GPIO12 D7 GPIO12_ACIN
GPIO13 B4 DGPU_PSI 0100 DDR3(L) 256MBx16x4, 64bit,1000MHz(900MHz) HYNIX H5TC4G63AFR-11C
DGPU_PSI [36]
1100 DDR3(L) 128MBx16x4, 64bit,1000MHz(900MHz) HYNIX H5TC2G63FFR-11C
+3V_GFX 0001 DDR3(L) 128MBx16x4, 64bit,1000MHz(900MHz) MICRO MT41J128M16JT-093G:K
GF117 GF119
1101 DDR3(L) 128MBx16x4, 64bit,1000MHz(900MHz) MICRO MT41J256M16HA-093G:E
GPIO16 D5 N15S -> GPIO0 un-stuff Q24 and EC_FB_CLAMP.
C NC C
NC GPIO20 E6 GPIO6 Unstuff Q26\R70 and FB_CLAMP_REQ#.
GPIO21 C4 GPU_PEX_RST_HOLD#
NC GPU_PEX_RST_HOLD# [16]
GPIO I/O PIN USAGE

+3V_GFX
ESP@N14P-GV2
0 IN FB_CLAMP_MON FB Clamp monitor
R57 EV@0_4 GPIO12_ACIN R51 EV@10K/F_4 1 OUT MEM_VDD_CTL Memory VDD VID
[16] PEGX_RST#
2 OUT LCD_BL_PWM Panel Backlight PWM
DGPU_PSI R16 *10K/F_4
3 OUT LCD_VCC PANEL POWER ENABLE
2
dGPU_OPP# = EC control 4 OUT LCD_BLEN PANEL BACKLIGHT ENABLE

VGA_OVT# 1 3 VGA_OVT# R54 EV@10K/F_4
dGPU_OTP# [29]
GPIO12_ACIN 1 3
dGPU_OPP# [29] 5 OUT Reserved --
Q9 Q7 GPIO12 AC detect GPU_PEX_RST_HOLD# R15 EV@10K/F_4
EV@2N7002K EV@2N7002K AC high
6 OUT FB_CLAMP_TGL_REQ Active low FB Clamp toggle request
2
DC low
3V_MAIN_EN R362 *10K/F_4 7 OUT 3D VISION 3D VISION LEFT/RIGHT signal
+3V_GFX
8 I/O OVERT ACTIVE LOW THERMAL OVER TEMP
JTAG_TRST# R85 EV@10K/F_4
9 I/O ALERT ACTIVE LOW THERMAL ALERT
10 OUT MEM VREF_CTL MEMMORY VREF CONTROL
11 OUT PWR_VID GPU CORE_VDD PWM Control signal
D D
12 IN PWR_LEVEL AC Power detect or power supply overdraw input
13 OUT PSI Phase Shedding
GPIO ASSIGNMENTS PROJECT :U82

Custom N14M-GS (GPIO/STRAPS) 1B

1 2 3 4 5 6 7 8
5 4 3 2 1
：AKD5PGWTW08---AKD5PGWTW07
HYU 256Mx16, PN：
[17] VMA_DQ[63..0]
[17] VMA_DM[7..0]
[17] VMA_WDQS[7..0]
[17] VMA_RDQS[7..0]
CHANNEL A: 256MB/512MB DDR3 ：AKD5MZDTW03---AKD5MZDTW02
HYU 128Mx16, PN：
QBC
：AKD5PZDT501---AKD5PZDT500
SAM 256Mx16, PN：
：AKD5MGGT535---AKD5MGGT534
SAM 128Mx16, PN：
TOP B/S
20
VRAM6 VRAM8 VRAM7 VRAM9
VREFC_VMA1 M8 E3 VMA_DQ13 VREFC_VMA1 M8 E3 VMA_DQ21 VREFC_VMA3 M8 E3 VMA_DQ41 VREFC_VMA3 M8 E3 VMA_DQ61

VREFD_VMA1 H1 VREFCA DQL0 F7 VMA_DQ11 VREFD_VMA1 H1 VREFCA DQL0 F7 VMA_DQ16 VREFD_VMA3 H1 VREFCA DQL0 F7 VMA_DQ45 VREFD_VMA3 H1 VREFCA DQL0 F7 VMA_DQ56
VREFDQ DQL1 F2 VMA_DQ12 VREFDQ DQL1 F2 VMA_DQ20 VREFDQ DQL1 F2 VMA_DQ40 VREFDQ DQL1 F2 VMA_DQ63
N3 DQL2 F8 VMA_DQ9 FBA_CMD9 N3 DQL2 F8 VMA_DQ18 FBA_CMD9 N3 DQL2 F8 VMA_DQ46 FBA_CMD9 N3 DQL2 F8 VMA_DQ59
[17] FBA_CMD9 A0 DQL3 A0 DQL3 A0 DQL3 A0 DQL3
D P7 H3 VMA_DQ14 FBA_CMD11 P7 H3 VMA_DQ23 FBA_CMD11 P7 H3 VMA_DQ43 FBA_CMD11 P7 H3 VMA_DQ62 D
P3 H8 VMA_DQ10 FBA_CMD8 P3 H8 VMA_DQ19 FBA_CMD8 P3 H8 VMA_DQ47 FBA_CMD8 P3 H8 VMA_DQ57
N2 G2 VMA_DQ15 FBA_CMD25 N2 G2 VMA_DQ22 FBA_CMD25 N2 G2 VMA_DQ42 FBA_CMD25 N2 G2 VMA_DQ60
P8 H7 VMA_DQ8 FBA_CMD10 P8 H7 VMA_DQ17 FBA_CMD10 P8 H7 VMA_DQ44 FBA_CMD10 P8 H7 VMA_DQ58
P2 FBA_CMD24 P2 FBA_CMD24 P2 FBA_CMD24 P2
[17] FBA_CMD24 A5 A5 A5 A5
R8 FBA_CMD22 R8 FBA_CMD22 R8 FBA_CMD22 R8
[17] FBA_CMD22 A6 A6 A6 A6
R2 D7 VMA_DQ7 FBA_CMD7 R2 D7 VMA_DQ31 FBA_CMD7 R2 D7 VMA_DQ33 FBA_CMD7 R2 D7 VMA_DQ54
[17] FBA_CMD7 A7 DQU0 A7 DQU0 A7 DQU0 A7 DQU0
T8 C3 VMA_DQ0 FBA_CMD21 T8 C3 VMA_DQ24 FBA_CMD21 T8 C3 VMA_DQ37 FBA_CMD21 T8 C3 VMA_DQ48
R3 C8 VMA_DQ5 FBA_CMD6 R3 C8 VMA_DQ30 FBA_CMD6 R3 C8 VMA_DQ34 FBA_CMD6 R3 C8 VMA_DQ55
L7 C2 VMA_DQ3 FBA_CMD29 L7 C2 VMA_DQ26 FBA_CMD29 L7 C2 VMA_DQ39 FBA_CMD29 L7 C2 VMA_DQ50
[17] FBA_CMD29 A10/AP DQU3 A10/AP DQU3 A10/AP DQU3 A10/AP DQU3
R7 A7 VMA_DQ4 FBA_CMD23 R7 A7 VMA_DQ28 FBA_CMD23 R7 A7 VMA_DQ35 FBA_CMD23 R7 A7 VMA_DQ53
N7 A2 VMA_DQ2 FBA_CMD28 N7 A2 VMA_DQ27 FBA_CMD28 N7 A2 VMA_DQ36 FBA_CMD28 N7 A2 VMA_DQ51
[17] FBA_CMD28 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5
T3 B8 VMA_DQ6 FBA_CMD20 T3 B8 VMA_DQ29 FBA_CMD20 T3 B8 VMA_DQ32 FBA_CMD20 T3 B8 VMA_DQ52
T7 A3 VMA_DQ1 FBA_CMD4 T7 A3 VMA_DQ25 FBA_CMD4 T7 A3 VMA_DQ38 FBA_CMD4 T7 A3 VMA_DQ49
M7 FBA_CMD14 M7 FBA_CMD14 M7 FBA_CMD14 M7
[17] FBA_CMD14 A15 A15 A15 A15
M2 B2 FBA_CMD12 M2 B2 FBA_CMD12 M2 B2 FBA_CMD12 M2 B2

[17] FBA_CMD12 BA0 VDD#B2 +1.5V_GFX BA0 VDD#B2 BA0 VDD#B2 +1.5V_GFX BA0 VDD#B2
N8 D9 FBA_CMD27 N8 D9 FBA_CMD27 N8 D9 FBA_CMD27 N8 D9
[17] FBA_CMD27 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
M3 G7 FBA_CMD26 M3 G7 FBA_CMD26 M3 G7 FBA_CMD26 M3 G7
[17] FBA_CMD26 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2 K2
J7 VDD#N1 N9 VMA_CLK0 J7 VDD#N1 N9 J7 VDD#N1 N9 VMA_CLK1 J7 VDD#N1 N9
[17] VMA_CLK0 CK VDD#N9 CK VDD#N9 [17] VMA_CLK1 CK VDD#N9 CK VDD#N9
K7 R1 VMA_CLK0# K7 R1 K7 R1 VMA_CLK1# K7 R1
[17] VMA_CLK0# CK VDD#R1 CK VDD#R1 [17] VMA_CLK1# CK VDD#R1 CK VDD#R1 +1.5V_GFX
K9 R9 FBA_CMD3 K9 R9 K9 R9 FBA_CMD19 K9 R9
[17] FBA_CMD3 CKE VDD#R9 CKE VDD#R9 +1.5V_GFX [17] FBA_CMD19 CKE VDD#R9 CKE VDD#R9
K1 A1 FBA_CMD2 K1 A1 K1 A1 FBA_CMD18 K1 A1
[17] FBA_CMD2 ODT VDDQ#A1 ODT VDDQ#A1 [17] FBA_CMD18 ODT VDDQ#A1 ODT VDDQ#A1
L2 A8 FBA_CMD0 L2 A8 L2 A8 FBA_CMD16 L2 A8
[17] FBA_CMD0 CS VDDQ#A8 CS VDDQ#A8 [17] FBA_CMD16 CS VDDQ#A8 CS VDDQ#A8
C J3 C1 FBA_CMD30 J3 C1 FBA_CMD30 J3 C1 FBA_CMD30 J3 C1 C
[17] FBA_CMD30 RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1 RAS VDDQ#C1
K3 C9 FBA_CMD15 K3 C9 FBA_CMD15 K3 C9 FBA_CMD15 K3 C9
[17] FBA_CMD15 CAS VDDQ#C9 CAS VDDQ#C9 CAS VDDQ#C9 CAS VDDQ#C9
L3 D2 FBA_CMD13 L3 D2 FBA_CMD13 L3 D2 FBA_CMD13 L3 D2
[17] FBA_CMD13 WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2 WE VDDQ#D2
E9 E9 E9 E9
VMA_WDQS1 F3 VDDQ#F1 H2 VMA_WDQS2 F3 VDDQ#F1 H2 VMA_WDQS5 F3 VDDQ#F1 H2 VMA_WDQS7 F3 VDDQ#F1 H2
VMA_RDQS1 G3 DQSL VDDQ#H2 H9 VMA_RDQS2 G3 DQSL VDDQ#H2 H9 VMA_RDQS5 G3 DQSL VDDQ#H2 H9 VMA_RDQS7 G3 DQSL VDDQ#H2 H9
DQSL VDDQ#H9 DQSL VDDQ#H9 DQSL VDDQ#H9 DQSL VDDQ#H9
VMA_DM1 E7 A9 VMA_DM2 E7 A9 VMA_DM5 E7 A9 VMA_DM7 E7 A9

VMA_DM0 D3 DML VSS#A9 B3 VMA_DM3 D3 DML VSS#A9 B3 VMA_DM4 D3 DML VSS#A9 B3 VMA_DM6 D3 DML VSS#A9 B3
VMA_WDQS0 C7 VSS#G8 J2 VMA_WDQS3 C7 VSS#G8 J2 VMA_WDQS4 C7 VSS#G8 J2 VMA_WDQS6 C7 VSS#G8 J2
VMA_RDQS0 B7 DQSU VSS#J2 J8 VMA_RDQS3 B7 DQSU VSS#J2 J8 VMA_RDQS4 B7 DQSU VSS#J2 J8 VMA_RDQS6 B7 DQSU VSS#J2 J8
T2 VSS#P1 P9 FBA_CMD5 T2 VSS#P1 P9 FBA_CMD5 T2 VSS#P1 P9 FBA_CMD5 T2 VSS#P1 P9
[17] FBA_CMD5 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
VMA_ZQ1 L8 VSS#T1 T9 VMA_ZQ2 L8 VSS#T1 T9 VMA_ZQ3 L8 VSS#T1 T9 VMA_ZQ4 L8 VSS#T1 T9
B1 B1 B1 B1
VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9
R55 VSSQ#B9 D1 R365 VSSQ#B9 D1 R79 VSSQ#B9 D1 R384 VSSQ#B9 D1
Should be 240 VSSQ#D1 Should be 240 VSSQ#D1 Should be 240 VSSQ#D1 Should be 240 VSSQ#D1
Ohms +-1% EV@243/F_4 D8 Ohms +-1% EV@243/F_4 D8 Ohms +-1% EV@243/F_4 D8 Ohms +-1% EV@243/F_4 D8
J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8
B J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 B
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
ESP@VRAM _DDR3_HYNIX_256MX16 ESP@VRAM _DDR3_HYNIX_256MX16 ESP@VRAM _DDR3_HYNIX_256MX16 ESP@VRAM _DDR3_HYNIX_256MX16
+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX
VMA_CLK0
R374 R8 R76 R402
EV@1.33K/F_4 EV@1.33K/F_4 VMA_CLK1 EV@1.33K/F_4 EV@1.33K/F_4
R31
EV@162/F_4
VREFC_VMA1 VREFD_VMA1 R84 VREFC_VMA3 VREFD_VMA3
EV@162/F_4
VMA_CLK0#
R372 C388 R13 C14 R73 C87 R387 C406
EV@1.33K/F_4 EV@0.1U/10V_4 EV@1.33K/F_4 EV@0.1U/10V_4 VMA_CLK1# EV@1.33K/F_4 EV@0.1U/10V_4 EV@1.33K/F_4 EV@0.1U/10V_4
+1.5V_GFX
+1.5V_GFX
A C111 EV@10U/6.3V_6 C109 EV@10U/6.3V_6 +1.5V_GFX A
+1.5V_GFX C397 EV@1U/6.3V_4 C63 EV@10U/6.3V_6 C396 EV@10U/6.3V_6

C121 EV@1U/6.3V_4
+1.5V_GFX C379 EV@10U/6.3V_6 C53 EV@1U/6.3V_4 C387 EV@0.1U/10V_4 C410 EV@10U/6.3V_6
C50 EV@1U/6.3V_4 C382 EV@0.1U/10V_4
C403
C30
EV@1U/6.3V_4
EV@1U/6.3V_4
C401
C418
EV@1U/6.3V_4
EV@1U/6.3V_4
C413
C68
EV@1U/6.3V_4
EV@1U/6.3V_4
C385 EV@0.1U/10V_4
C120 EV@0.1U/10V_4
PROJECT :U82
C41
C27
EV@1U/6.3V_4
EV@1U/6.3V_4
C384
C399
EV@1U/6.3V_4
EV@1U/6.3V_4
C71
C400
EV@1U/6.3V_4
EV@1U/6.3V_4
C414
C78
EV@0.1U/10V_4
EV@0.1U/10V_4
C386
C108
EV@0.1U/10V_4
EV@0.1U/10V_4
Custom 1B
DGPU Memory (DDR3)
5 4 3 2 1
1 2 3 4
LED(UIF)
FFC SATA HDD
CN13
Layout Notes:
Place decoupling CAPs close to Connector
+3V_S5 +3VPCU
1
2 1
CN16
9
9
21
12 10 PWRLED# 3 2
11 9 [29] PWRLED# 4 3
SATA_TXP0_C C559 0.01u/16V_4 SATA_TXP0 [8] SUSLED#
A [29] SUSLED# 4 A
8 SATA_TXN0_C C560 0.01u/16V_4 SATA_TXN0 [8] BATLED0# 5
7 [29] BATLED0# 6 5
BATLED1#
6 [29] BATLED1# 7 6
SATA_RXN0_C C563 0.01u/16V_4
SATA_RXN0 [8] 7
5 SATA_RXP0_C C564 0.01u/16V_4 8 10
4 SATA_RXP0 [8] 8 10
DEVSLP0_R R603 *0_4 DEVSLP0 [10]
3 R600 *0_4 HDD protect [27]
2 R599 0_4 88511-0801
1 +5V_HDD R296 *short_8
+5V
SATA_CONN C342 C341 C343 C344 C335 C562 Change CN6 PN for ME request
+
0.01u/16V_4 0.01u/16V_4 *0.1u/10V_4 *0.1u/10V_4 10u/6.3V_6 *100u/6.3V_3528
120mil 3/5VPCU reset switch (CLG)
SW6 SWITCH_1.5
B B
2 3 SYS_SHDN# [10,31,35]
4 1
TP75
1
+3VPCU TP76
+3VPCU [7,8,11,13,22,23,28,29,30,31,35,36,37]
C376 D28
6
+3V_S5 +3V_S5 [5,7,8,9,10,11,13,24,27,28,29,31,34,36]
0.1u/10V_4 *14V/100p_4
2
+3V +3V [2,5,7,8,9,10,11,13,14,15,16,17,18,22,23,24,25,26,27,28,29,31,32,33,34,35,36]
+5V +5V [22,23,25,28,31,35]
Power tracking
TPM (TPM) TPM_VDD TPM_VSB
U8 R648 TPMI@0_4 TPM_VDD 4 x100nF

5 R649 TPMN@0_4 +3V
VDD[3] (place close to device VDD/GND pins)
1 2 TPM_GPIO 6
TPM_VDD GPIO
C R95 *20K_4 2 10 R88 TPM@2.2_6 C
TP121 NC2 VDD[4] 24
R93 TPMI@4.7K_4 TPM_PP 7 VDD[2] 19
PP VDD[1] near pin 21 as possible
C110 *10p/50V_4 C125 C126 C122 C124 C123
R96 *4.7K_4 13 TPM@0.1U/10V_4 TPM@0.1U/10V_4 TPM@0.1U/10V_4 TPM@0.1U/10V_4 TPM@10u/6.3V_6
TPM_VDD NC13 21
LCLK PCLK_TPM [9]
FAE : install R80 4K7, PIN7 wo interanl PD 22 LPC_LFRAME# LPC_LFRAME# [8,26,29]
14 LFRAME#
NC14 17 LPC_LAD3
LAD3 20 LPC_LAD3 [8,26,29]
LPC_LAD2
LAD2 23 LPC_LAD2 [8,26,29]
LPC_LAD1
LAD1 LPC_LAD1 [8,26,29]
26 LPC_LAD0
LAD0 LPC_LAD0 [8,26,29]
8 28 R650 TPMN@0_4 TPM_VSB +3V_S5 +3VSUS
NC8 NC28 LPCPD# [7]
16 PLTRST# R647 TPMN@0_4
LRESET#[1] PLTRST# [7,13,16,24,26,29]
9 TPM_RST_R R90 TPMI@0_4 R646 *0_4
12 TPM SLB9655 LRESET#[2]
NC12 27 SERIRQ_R R100 TPM@0_4
3 SERIRQ 15 IRQ_SERIRQ [10,29]
R758 TPMN@0_4 C584 C587
GND[1]
GND[2]
GND[3]
GND[4]
NC3 NC15 CLKRUN# [7,29]

1 TPM@0.1U/10V_4 TPM@10u/6.3V_6
TP122 NC1
FAE : a 0ohm between pin9 to LRESET signals
TPMS@NPCT620/650_TSSOP28
4
11
18
25
D D

PROJECT : ZQX
1B
SATA-HDD/ TPM
1 2 3 4
5 4 3 2 1
Codec(ADO) Grounding circuit(ADO)

HPR
HPL
HPR [27]
HPL [27]
Add by FAE suggest 10/31
INT_AMIC-VREFO
+3VPCU TBC 22
LINE1L-VREFO LINE1L-VREFO [27] R309 PIN1, PIN4, PIN3, PIN6 are ANALOG R311
100K_4
LINE1R-VREFO +3V
LINE1R-VREFO [27] Q26
MIC2-VREFO MIC2-VREFO [27] 100K_4
1 6 SLEEVE SLEEVE [27]
R316
CODEC_VREF C340 2.2U/6.3V_4 ADOGND ADOGND 2
D D
INT_AMIC-VREFO C349 10u/6.3V_4 +5VA
ADOGND
3
4 3
C307
C323
placed close to codec MIC2-VREFO RING2 RING2 [27] *100K_4
C303 R297 5
2
1u/10V_4
R313 10K_4 PCH_AZ_CODEC_RST#
10u/6.3V_4
100K_4
1u/10V_4 C348 ADOGND
C347 2N7002DW Q22
0.1u/10V_4 10u/6.3V_4 2N7002K C345
*1u/10V_4
1
+AZA_VDD
Place next to pin 26 ADOGND
Add by FAE suggest 10/24
36
35
34
33
32
31
30
29
28
27
26
25
+1.5VA
U17
ADOGND
HP-OUT-L
LINE1-VREFO-L
AVDD1
AVSS1
CPVDD
CBN
HP-OUT-R
LINE1-VREFO-R
VREF
MIC2-VREFO
CPVEE
LDO1-CAP
C301
C302
10u/6.3V_4 0.1u/10V_4
ADOGND 37 24
CBP LINE2-L
38 23
ADOGND AVSS2 LINE2-R
Place next to pin 40 C294 10u/6.3V_4 39 22 LINE1L_R LINE1L_R [27] +5V +5V [21,23,25,28,31,35]
LDO2-CAP LINE1-L
Analog 40 21 LINE1R_R LINE1R_R [27]
AVDD2 LINE1-R
Digital +5V
41 20 +3V +3V [2,5,7,8,9,10,11,13,14,15,16,17,18,21,23,24,25,26,27,28,29,31,32,33,34,35,36]
PVDD1 NC
L_SPK+ 42 19 C346 10u/6.3V_4
SPK-L+ MIC1-CAP ADOGND
C290 Power tracking
Add for FAE suggest
C289
10u/6.3V_6 0.1u/10V_4
L_SPK- 43
SPK-L-
ALC283 MIC2-R/SLEEVE
18 SLEEVE
R_SPK- 44 17 RING2
SPK-R- MIC2-L/RING2
near Codec R_SPK+ 45 16
C SPK-R+ MONO-OUT C
+5V
46 15 CODEC_JDREF R318 20K/F_4 ADOGND
PVDD2 JDREF
GPIO0/DMIC-DATA
Low is power down PD# 47 GPIO1/DMIC-CLK 14

C546 amplifier output PDB Sense B
C288 48 13 SENSEA R304 39.2K/F_4 HP_JD#
SDATA-OUT
TP72 SPDIFO/GPIO2 Sense A HP_JD# [27]
LDO3-CAP
10u/6.3V_6 0.1u/10V_4
SDATA-IN
DVDD-IO
PCBEEP
RESETB
BIT-CLK
Placement near Audio Codec
DVDD
SYNC
DVSS
49
DGND R310 *short_4
near Codec Analog R246 *short_4
R554 *short_4
1
10
11
12
Digital R251 *short_4
Add for FAE suggest R245 *short_4
R253 *short_4
C531 *1000p/50V_4
C322 1.6Vrms C532 *1000p/50V_4
+3V R267 *short_6 +AZA_VDD D17 RB500V-40
SPKR [8,10]
10u/6.3V_4 PCBEEP C339 1u/10V_4 BEEP_1 R299 47K_4
D18 RB500V-40
PCBEEP_EC [29]
C300 C338 R300 ADOGND
DMIC_DAT_L
DMIC_CLK_L
C299 4.7K_4
0.1u/10V_4 10u/6.3V_4 100p/50V_4
+3V +1.5V
Place next to pin 1

PCH_AZ_CODEC_RST# PCH_AZ_CODEC_RST# [8]
R294 *short_4
PCH_AZ_CODEC_SYNC [8]
DVDD_IO R292 *0_4
DMIC_DAT_L [27] DMIC_DAT_L
DMIC_CLK_L
ACZ_SDIN R287 33_4 PCH_AZ_CODEC_SDIN0 [8] C331 C330
[27] DMIC_CLK_L
C692 C693 PCH_AZ_CODEC_BITCLK [8] 0.1u/10V_4 10u/6.3V_4
B 27pf/50V_4 27pf/50V_4 B
C320 *22p/50V_4
PCH_AZ_CODEC_SDOUT [8] Place next to pin 9
+AZA_VDD
Codec PWR 5V(ADO) Mute(ADO) Codec PWR 3V/1.5V(ADO)

R256
Change D25,D49 to RB500V-40
*1K_4
+1.5VA
PD# PCH_AZ_CODEC_RST#
DIGITAL ANALOG RB500V-40 D15 DIGITAL ANALOG
L12 HCB2012KF220T60/6A/22ohm_8 AMP_MUTE# [29]
+5V +5VA R257 RB500V-40 D16 R252 *short_4
+1.5V
U18 *10K_4
3 4 C295
IN OUT
2 1U/6.3V_4
GND C360 C357
1 5 R322 *29.4K/F_4
SHDN SET *10u/6.3V_6 *0.1u/10V_4
*G923-330T1UF
C352 C358 R320
*10K/F_4
A
*0.1u/10V_4 *10u/6.3V_6
R315 *0_4
ADOGND
Internal Speaker A
40mil for each signal

ADOGND CN15
R_SPK+ R592 *Short_6 R_SPK+_1
R_SPK- R591 *Short_6 R_SPK-_1 1
L_SPK+ R589 *Short_6 L_SPK+_1 2
L_SPK- R590 *Short_6 L_SPK-_1 3 5
C730, C787 close U37 pin3 and L65 4 6
C568 C567 C566 C565 SPK_CONN_4P

Swap LSPK+,LSPK- 11/01
*68p/50V_4 *68p/50V_4 *68p/50V_4 *68p/50V_4 PROJECT : ZQX
1B
ALC283/HP/SPK
5 4 3 2 1
1 2 3 4 5 6 7 8
LCD CONNECTOR
VIN
+3V TP_PWR CCD_PWR
LCD Power
+3V
23
C11 C12 C13 C10
C6 C7 Touch Panel interrupt C82 U6
R371 0.1u/10V_4_X7R 0.1u/10V_4_X7R
2
4.7u/25V_8 1000p/50V_4 *10K_4 1000p/50V_4 1000p/50V_4 1u/6.3V_4 6 1 LCDVCC
IN OUT
A A
[10] TP_INT_PCH
3 1 TP_INT 4 2 C31 C81 C32 C33 C80
IN GND
Q35 R77 *short_4EDP_VDD_EN_R 3 5 *0.1u/10V_4 *2.2u/10V_8 0.1u/10V_4 0.01u/25V_4 22u/6.3V_8
[2] EDP_VDD_EN ON/OFF GND
*2N7002K
G5243AT11U
R382 *0_4 VIN
MAX 1.5A
VIN VIN [28,30,31,32,33,34,35,36,37] CN7 R78
R27 *Short_6
G_5
R28 *Short_6 V_BLIGHT
40 100K_4
+3VPCU 39
+3VPCU [7,8,11,13,21,22,28,29,30,31,35,36,37] 38
+3V C18 C17 37
+3V [2,5,7,8,9,10,11,13,14,15,16,17,18,21,22,24,25,26,27,28,29,31,32,33,34,35,36] *1u/6.3V_4 36
*1u/6.3V_4
LCDVCC 35
R6 *Short_6 CCD_PWR 34
Power tracking +3V 33
32
Del TP_PWR 5V, R22 *Short_6 TP_PWR 31 G_4
+5V 30
+3V Add pin31 connect to TP_PWR +3V R129 *0_6
29 +3V
PCH_BRIGHT 28 Touch screen level shift I2C(reserve)
[2] PCH_BRIGHT 27
BL_ON
R38 100K_4 EDP_AUX_C R369 *100K_4 EDP_HPD 26
[2] EDP_HPD 25
R42 *100K_4 EDP_AUX#_C R370 100K_4
C16 .1U/16V_4 EDP_AUX_C 24 R47 *0_4
[2] EDP_AUXP 23
B TP_RST# R366 10K_4 Add 10/31 C21 .1U/16V_4 EDP_AUX#_C R40 R39 B
[2] EDP_AUXN 22 *2.2K_4 *2.2K_4
21 Q6
[2] EDP_TXP1 C391 .1U/16V_4 EDP_TX1_C
C392 .1U/16V_4 EDP_TX1#_C 20
eDP [2] EDP_TXN1 19 1 6 I2C1_SDA_GPIO6_CONN
C393 .1U/16V_4 EDP_TX0_C 18
[2] EDP_TXP0 17
eDP only one channel C394 .1U/16V_4 EDP_TX0#_C 2 +3V
[2] EDP_TXN0 16
15 [10,28] I2C1_SDA_GPIO6
[9] USBP6+ R377 *short_4 USBP6+_R [10,28] I2C1_SCL_GPIO7
R378 *short_4 USBP6-_R 14 4 3 I2C1_SCL_GPIO7_CONN
CCD-USB [9] USBP6- 13
R379 *short_4 USBP5+_R 12 5
[9] USBP5+ 11
Touch Panel R380 *short_4 USBP5-_R
[9] USBP5- 10 G_1
I2C1_SCL_GPIO7_CONN 9 *2N7002DW
I2C1_SDA_GPIO6_CONN 8 Swap Cn22 pin7,8 follow ZQ0 R46 *0_4
R375 *short_4 7
[29] TS_EN 6
TP_INT R373 *0_4
TP_RST# 5
4
3
[10] GPIO8 2
G_0
1
GS12401-1011P-7H
40pins: lvd-a40sfyg-40p-r
C
Backlight Control +3VPCU
C
R49
*100K_4
+3V LID#
LID +3VPCU
LID591#,EC intrnal PU
LID# [29]
D8
R65 R48 *1N4148WS
10K_4 10K_4
+3VPCU BL_ON
BL#
R68 *short_4PCH_BLON_R
[2] PCH_BLON
3
R7 *100K_4
R67
2
EC_FPBACK# [29]
[29] PCH_BLON_EC R69 0_4 100K_4
R12 Q8
D6
*Short_6 Q10 DTC144EUA
*VPORT_6
1
2N7002DW
1 2 1 2 LID# 2013/11/28 Add BLON pin from PCH to lison.
1
2
C9 D7
D 4.7u/6.3V_6 *VPORT_6 D
3
MR6
AH9249NTR-G1
1
1st：AL009249000 -- BCD
2nd：AL001691000 -- OCS Quanta Computer Inc.
PROJECT : ZQX
1B
CRT/LVDS/CAMERA/LID
1 2 3 4 5 6 7 8
5 4 3 2 1
LAN
LAN_XTALI C549 12p/50V_4 24
1
2
Y9
25MHZ +-30PPM
VDD10
3
4
LAN_XTAL2 change to LANCC and add PU res for FAE suggest
C305 *10P/50V/COG_4 C548 12p/50V_4
R583 2.49K/F_4 RSET
10 mils TP71
TP73
TP118 LANVCC
D LANVCC S5 D
C547 *10P/50V/COG_4
R302 *10K/J_4
2
32
31
30
29
28
27
26
25
U36
3 1 PCIE_REQ_LAN#_R
AVDD33
AVDD10
CKXTAL2
CKXTAL1
LED0
RSET
LED1/GPO
LED2(LED1)
[9] CLK_PCIE_LAN_REQ#
33 Q25
GND 2N7002K
R622 *0/J_4
MDI_0+ 1 24
MDIP0 REGOUT REGOUT
MDI_0- 2 23 VDDREG/VDD33
3 MDIN0 VDDREG(VDD33) 22 LANVCC
VDD10 AVDD10(NC) DVDD10(NC) VDD10
MDI_1+ 4 21 PCIE_LAN_WAKE#_R
MDI_1- 5 MDIP1 LANWAKEB 20 ISOLATEB R291 *10K/J_4
MDI_2+ 6 MDIN1 ISOLATEB 19
MDIP2(NC) RTL8111GS-CG PERSTB PLTRST# [7,13,16,21,26,29]
2
MDI_2- 7 18 GPP_TX2N_LAN C574 0.1U/10V_4 PCIE_RX3-_LAN [9]
8 MDIN2(NC) HSON 17 GPP_TX2P_LAN C575 0.1U/10V_4
VDD10 AVDD10 HSOP PCIE_RX3+_LAN [9]
Q21
+3V DTC144EUA
AVDD33(NC)
3 1 PCIE_LAN_WAKE#_R
[7,26] PCIE_LAN_WAKE#
REFCLK_N
MDIN3(NC)
MDIP3(NC)
REFCLK_P
CLKREQB
LANVCC
+3V_S5 LANVCC R293 R593 *0_4
HSIN
HSIP
1K_4
40 mils (Iout=1A) 40 mils (Iout=1A) ISOLATEB
9
10
11
12
13
14
15
16
R584 *Short_6
R597
15K_4
MDI_3+
C350 C337 MDI_3- Power trace tracking
0.1U/10V_4 10U/6.3V_6 LANVCC
C C
CLK_PCIE_LANN [9] [5,7,8,9,10,11,13,21,27,28,29,31,34,36] +3V_S5

CLK_PCIE_LANP [9] [2,5,7,8,9,10,11,13,14,15,16,17,18,21,22,23,25,26,27,28,29,31,32,33,34,35,36] +3V
PCIE_TX3-_LAN [9]
PCIE_TX3+_LAN [9]
PCIE_REQ_LAN#_R
For RTL8111G(S)
* Place 1uF CAP close to each VDD10 pin-- 22 (reserve)
LANVCC
For RTL8111G(S)
VDDREG/VDD33 RTL8111GS * Place 0.1uF CAP close to each VDD10
40 mils (Iout=1A) C1 C2 REGOUT (SWR mode) support VDD10 pin-- 3, 8, 22, 30
R585 *SHORT_8
40 mils (Iout=1A) 40 mils (Iout=1A)
C550 C351 C544 C541 40 mils (Iout=1A) C309 C551 L20 4.7uH
0.1U/10V_4 0.1U/10V_4 4.7U/6.3V_6 4.7U/6.3V_6 0.1U/10V_4 4.7U/6.3V_6
C319 C324 C336 C328 C306 C329 C570 C325

4.7U/6.3V_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 1U/6.3V_4 0.1U/10V_4
For RTL8111GS For surge improvement,

* Place 0.1uF CAP close to each place C1 and C2 close to each Remove For Not Using SWR mode
VDD33 pin-- 11, 32 VDD33 pin11,32(optional) C824,C825 close to Pin23.
B
Tramsformer B
change 1 ohm to to shortpad for FAE suggest RJ45 Connector

U30
MDI_3+ 1 TD1+ MX1+ 24 LAN_MX3+
MDI_3- 2 TD1- MX1- 23 LAN_MX3-

CN12
3 TCT1 MCT1 22 R652 75/F_6
6/30 separate 75ohm

U34 LANVCC
MDI_0+ 1 6 MDI_0- 4 21 R653 75/F_6 LAN_MX0+ 1
2 IO1 IO4 5 TCT2 MCT2 LAN_MX0- 2 0+
MDI_1- 3 GND REF 4 MDI_1+ MDI_2+ 5 20 LAN_MX2+ LAN_MX1+ 3 0-
IO2 IO3 TD2+ MX2+ LAN_MX2+ 4 1+
*CM1293A-04SO MDI_2- 6 19 LAN_MX2- LAN_MX2- 5 2+
TD2- MX2- LAN_MX1- 6 2-
LAN_MX3+ 7 1- 9
LAN_MX3- 8 3+ GND 10
U35 LANVCC MDI_1+ 7 18 LAN_MX1+ 3- GND 11
MDI_2+ 1 6 MDI_2- TD3+ MX3+ GND 12
2 IO1 IO4 5 MDI_1- 8 17 LAN_MX1- GND
MDI_3- 3 GND REF 4 MDI_3+ TD3- MX3-
IO2 IO3 9 16 R654 75/F_6
*CM1293A-04SO TCT3 MCT3 RJ45
LGND
10 15 R655 75/F_6 LANCT3
TCT4 MCT4
Reserve for Surge 11 14
MDI_0+ LAN_MX0+
Line to GND TVS TD4+ MX4+
A MDI_0- 12 13 LAN_MX0- A
TD4- MX4- R241 Add 11/14
C292 C283 *1M_8
0.01U/50V/X7R_4 10p/3KV_1808
NS692417 R240 *Short_6
delete shortpad for layout 11/05
LGND LGND
PROJECT : ZQX
1B
LAN (RTL8111GS)
5 4 3 2 1
5 4 3 2 1
HDMI Cost Reduced level shift (HDM) HDMI connector (HDM)

[2] INT_HDMITX2N
[2] INT_HDMITX2P
C367
C368
C363
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
INT_HDMITX2N_C
INT_HDMITX2P_C
INT_HDMITX1N_C
INT_HDMITX2P_C
INT_HDMITX2N_C
INT_HDMITX1P_C
1
2
3
4
CN18
SHELL1
D2+SHELL3
D2 Shield
D2-
20
22 25
[2] INT_HDMITX1N D1+
C364 0.1u/10V_4 INT_HDMITX1P_C 5
D [2] INT_HDMITX1P D1 Shield D
INT_HDMITX1N_C 6
C365 0.1u/10V_4 INT_HDMITX0N_C INT_HDMITX0P_C 7 D1-
[2] INT_HDMITX0N D0+
C366 0.1u/10V_4 INT_HDMITX0P_C 8
[2] INT_HDMITX0P D0 Shield
INT_HDMITX0N_C 9
C362 0.1u/10V_4 INT_HDMICLK+_C INT_HDMICLK+_C 10 D0-
[2] INT_HDMICLK+ CK+
C361 0.1u/10V_4 INT_HDMICLK-_C 11
[2] INT_HDMICLK- CK Shield
INT_HDMICLK-_C 12
13 CK-
CE Remote
1
14
Layout Notes: R636 R637 R641 R640 R639 R638 R643 R642 +5V HDMI_DDCCLK_MB 15 NC
DDC CLK
Place decoupling CAPs close to Connector HDMI_DDCDATA_MB 16
DDC DATA
470_4 470_4 470_4 470_4 470_4 470_4 470_4 470_4 Q27 17
3 1 HDMI_5V 18 GND
2
IN OUT 2 HDMI_MB_HP R305 *short_4 HP_DET_CN 19 +5V 23
GND HP SHELL4
DET 21
SHELL2
3
AP2331SA-7
59075-01942-001
1
Q45
2 C356 D20 RV6 C353 C359
+3V
*1000p/50V_4
C *220p/50V_4 *14V/100p_4 C
*1000p/50V_4
2N7002K
*5V/0.2p_4
R633
2
*100K/F_4
1
HDMI DDC (HDM) +5V EMI (EMC) HDMI-detect (HDM)
D19
+3V +3V RB500V-40
INT_HDMITX2P_C +3V +3V
R327 *100/F_4
R307 Q24 R321
2
B B
2.2K_4 BSN20 2.2K_4 INT_HDMITX2N_C
R301
2
R314 *short_4 HDMI_DDCCLK_COM 1 3 HDMI_DDCCLK_MB INT_HDMITX1P_C 1M_4
[2] HDMI_DDCCLK_SW
Follow CRB 1.0 change to 2.2K R325 *100/F_4 [2] INT_HDMI_HPD 1 3 HDMI_MB_HP
+5V
1
INT_HDMITX1N_C Q23
2N7002K
D21 INT_HDMITX0P_C R306
RB500V-40 20K_4
R326 *100/F_4
2
+3V +3V
INT_HDMITX0N_C
+3V +3V [2,5,7,8,9,10,11,13,14,15,16,17,18,21,22,23,24,26,27,28,29,31,32,33,34,35,36]
Q28 INT_HDMICLK+_C
R319 R323 +5V +5V [21,22,23,28,31,35]
2
2.2K_4 BSN20 2.2K_4 R324 *100/F_4

Power tracking
R317 *short_4 HDMI_DDCDATA_COM 1 3 HDMI_DDCDATA_MB INT_HDMICLK-_C
[2] HDMI_DDCDATA_SW
A A
Follow CRB 1.0 change to 2.2K
PROJECT : ZQX
1B
HDMI (PS8101)
5 4 3 2 1
1 2 3 4 5 6 7 8
MINI-CARD WLAN(MPC)
+3.3V: 1000mA
+3.3Vaux:330mA
+1.5V:500mA
+WL_VDD
+WL_VDD
+WL_VDD R30 *short_8

+3V
26
A H=5.2mm C15 C19 C84 C20 A
CN8 *0.1u/10V_4 *0.1u/10V_4 0.1u/10V_4 10u/6.3V_6

R336 *short_4 51 52 R334
[29] BT_POWERON Reserved +3.3V +WL_VDD
TP74 CL_RST1#_WLAN 49 50 *4.7K_4
R335 *0_4 47 Reserved GND 48
[7,13,16,21,24,29] PLTRST# Reserved +1.5V +1.5V_MINI1_VDD
R9 *0_4 45 46
[9] CLK_PCI_LPC 43 Reserved LED_WPAN# 44 WLAN#
41 GND LED_WLAN# 42
+WL_VDD +3.3Vaux LED_WWAN# TP6
39 40
37 +3.3Vaux GND 38 +1.5V_MINI1_VDD +1.5V
GND USB_D+ USBP4+ [9]
35 36
33 GND USB_D- 34 USBP4- [9]
[9] PCIE_TX4+_WLAN PETp0 GND
31 32 WLAN_CLK_SDATA R10 *0_4
[9] PCIE_TX4-_WLAN
29 PETn0 SMB_DATA 30 WLAN_CLK_SCLK R11 *0_4
CLK_SDATA [8,13,14,15] 500mA for +1.5V R59 *0_8
GND SMB_CLK CLK_SCLK [8,13,14,15]
27 28 R1
GND +1.5V +1.5V_MINI1_VDD
[9] PCIE_RX4+_WLAN 25 26
23 PERp0 GND 24 C28 C23 C40
[9] PCIE_RX4-_WLAN PERn0 +3.3Vaux +WL_VDD
21 22 R340 *short_4 PLTRST# *1000p/50V_4 *0.1u/10V_4 *10u/6.3V_6
19 GND PERST# 20
17 UIM_C4 W_DISABLE# 18 RF_EN [29]
UIM_C8 GND Debug R3
15 16 A_LFRAME#_R R60 *short_4
13 GND UIM_VPP 14 LPC_LFRAME# [8,21,29]
A_LAD3_R R63 *short_4
[9] CLK_PCIE_WLANP REFCLK+ UIM_RESET LPC_LAD3 [8,21,29]
11 12 A_LAD2_R R66 *short_4
B [9] CLK_PCIE_WLANN 9 REFCLK- UIM_CLK 10 LPC_LAD2 [8,21,29] B
A_LAD1_R R71 *short_4
GND UIM_DATA LPC_LAD1 [8,21,29]
CLK_PCIE_WLAN_REQ#_R 7 8 A_LAD0_R R72 *short_4
5 CLKREQ# UIM_PWR 6 LPC_LAD0 [8,21,29]
Reserved +1.5V +1.5V_MINI1_VDD
3 4
GND
GND
PCIE_WAKE#_R 1 Reserved GND 2
WAKE# +3.3V +WL_VDD
53 MINI-CARD1
54
R70 *short_4 CLK_PCIE_WLAN_REQ#_R

[9] PCIE_CLKREQ_WLAN#
+3VPCU +3V
+3VPCU [7,8,11,13,21,22,23,28,29,30,31,35,36,37]
+1.5V +1.5V [11,22,35]
+3V_S5 +3V_S5 [5,7,8,9,10,11,13,21,24,27,28,29,31,34,36] R89
*4.7K_4
2
C Power tracking C
3 1 PCIE_WAKE#_R
[7,24] PCIE_LAN_WAKE#
Q13
*2N7002K
D D

PROJECT : ZQX
1B
Mini Card/mSATA
1 2 3 4 5 6 7 8
5 4 3 2 1
USB3.0
+5VPCU
C580 1u/6.3V_4
G Sensor 27
U40
2 8 USBPWR1
3 IN1 OUT3 7 +3V +3V3_SER
IN2 OUT2
1
6 C581
4 OUT1 C582 R781 0_8
D [29] USB_BC_ON EN# D
1 1000p/50V_4
GND 5 100u/6.3V_1206 +3V_S5
USB 3.0 Connector
2
OC#
UP7534ARA8-15 1 3
[9] USB_OC0#
CN19
1 Q54
VBUS
2
R330 *short_4 USBP1-_R 2 1 R782 *AO3413 C717 C716
[9] USBP1- 2 D-
[9] USBP1+ R331 *short_4 USBP1+_R 3 *100K_4 *1u/6.3V_4 *0.1u/10V_4
4 3 D+
R333 *short_4 USB3_RXN0_R 5 4 GND SENSOR_EN R780 *0_4
[9] USB3_RXN0 5 SSRX- [29] SENSOR_EN
[9] USB3_RXP0 R332 *short_4 USB3_RXP0_R 6
7 6 SSRX+
C370 0.1u/10V_4 USB3_TXN0_C R329 *short_4 USB3_TXN0_R 8 7 GND C715
[9] USB3_TXN0 8 SSTX-
[9] USB3_TXP0 C369 0.1u/10V_4 USB3_TXP0_C R328 *short_4 USB3_TXP0_R 9 *1000p/50V_4
9 SSTX+
13
12
11
10
13
12
11
10
Active High:
1st: AL007534001 (Promate) USB3.0 CONN
2nd: AL000547006 (GMT)
3rd: AL002511002 (DDS)
C C
USB3_TXN0_R C372 *1.6p/50V_4 USBP1-_R D24 1 2 *5V/0.2p_4 +3V3_SER
USB3_TXP0_R C371 *1.6p/50V_4 USBP1+_R D25 1 2 *5V/0.2p_4 U21
USB3_RXN0 C374 *1.6p/50V_4 USB3_RXN0_R D27 1 2 *5V/0.2p_4 R400 0_4 7 1 R406 *short_4
USB3_RXP0 C373 *1.6p/50V_4 USB3_RXP0_R D26 1 2 *5V/0.2p_4 VDD SDO
USB3_TXN0_R D23 1 2 *5V/0.2p_4 3 2 SDA_TO_EC_R R405 0_4 SDA_TO_EC [29]
USB3_TXP0_R D22 1 2 *5V/0.2p_4 C411 C408 VDDIO SDX
0.1u/10V_4 0.1u/10V_4 11 12 SCL_TO_EC_R R407 0_4 SCL_TO_EC [29]
PS SCX
8 5 G_INT R404 0_4 G_sen_INT [10,29]
GNDIO INT1
9 6
CSB
GND INT2 +3V
NC
USB2.0
10
4
BMA250E
I/O board C8
1000p/50V_4
For Universal Audio jack Function ADDR:0X18
5
2
4 HDD protect [21]
+3V +5V_S5 1
[10,29] Sensor_INT
CN11
1 U7
B B
3
2 *SN74AHC1G32DCKR
3
4
NBSWON# 5
[13,29] NBSWON# 6
[29] USBON# USBON#
USB_OC1# 7
[9] USB_OC1# 8
USBP2+ 9
[9] USBP2+
[9] USBP2- USBP2- 10
11 Sensor board
USBP3+ 12 +3V3_SER
[9] USBP3+ 13 +3V
[9] USBP3- USBP3- CN9
14
USBP7+ 15 10
[9] USBP7+ 16 9
[9] USBP7- USBP7-
17 SCL_TO_EC 8
18 SCL_TO_EC SDA_TO_EC 7
19 SDA_TO_EC 6
20 [22] DMIC_CLK_L 5
[22] HP_JD# HP_JD# [22] DMIC_DAT_L DMIC_DAT_L
21 4
HPL R630 56_4 HPL_C 22 C694 C695 3
[22] HPL 23 2 12
[22] HPR HPR R631 56_4 HPR_C *27pf/50V_4 *27pf/50V_4
24 1 11
SLEEVE 25
[22] SLEEVE 26
[22] MIC2-VREFO MIC2-VREFO Subboard_CONN
27
RING2 28
A [22] RING2 29 31 A
30 32
[22] LINE1L_R C355 4.7u/6.3V_6

[22] LINE1L-VREFO R629 4.7K_4 Sub_CONN +5VPCU +5VPCU [31,32,33]
ADOGND ADOGND
C354 4.7u/6.3V_6
+3V +3V [2,5,7,8,9,10,11,13,14,15,16,17,18,21,22,23,24,25,26,28,29,31,32,33,34,35,36] Quanta Computer Inc.
[22] LINE1R_R
R632 4.7K_4 +5V_S5
[22] LINE1R-VREFO +5V_S5 [4,8,31,32,34,36] PROJECT : ZQX
Power tracking
INT&EXT USB 1B

5 4 3 2 1
5 4 3 2 1
K/B (KBC) TOUCHPAD BOARD CONN (TPD I2C/PS2 co-lay)
MY0 26
CN14
7
5
3
1
CP10
7
8
6
4
2
*100p/50Vx4
8
MY16
MY17
MX7
MX6
MX5
Modify on 11/08,
add touchpad i2c PU RES
+TPVDD
R625 R635
28
[29] MY0 25 28 5 6 +3V_S5 +3V +3VSUS
MY1 MX4 2.2K_4 2.2K_4
[29] MY1 MY2 24 27 3 4 MX3 R776 0_6
[29] MY2 23 1 2
MY3 MX2 L23 *0_6
[29] MY3 MY4 22 I2C_TP_SDA_R
CP11 *100p/50Vx4 L21 *0_6
[29] MY4
MY5 21 7 8 MY0 I2C_TP_SCL_R L22 2.2_6 +TPVDD_R 1 3 +TPVDD
[29] MY5 20 5 6
MY6 MY1
D [29] MY6 MY7 19 3 4 MY2 D
[29] MY7
MY8 18 1 2 MY3 R626 *0_4 C576 Q53 + C714
2
[29] MY8 MY9 17 CP6 *100p/50Vx4 0.1u/10V_4 *AO3413 C712 0.1u/10V_4
[29] MY9 16 7 8 Q44
MY10 MY4 0.22u/25V_6
[29] MY10
MY11 15 5 6 MY5
[29] MY11 MY12 14 3 4 MY6 1 6
[29] PTP_PWR_EN# R775 *10K/J_4
[29] MY12 13 1 2
MY13 MY7
[29] MY13 12 2
MY14 CP7 *100p/50Vx4 [10,23] I2C1_SDA_GPIO6 I2C_TP_SDA_R
[29] MY14 11 7 8
MY15 MY8 [10,23] I2C1_SCL_GPIO7 I2C_TP_SCL_R C713
[29] MY15 10 5 6
MY16 MY9 *1000p/50V_4
[29] MY16 9 3 4 4 3
MY17 MY10
[29] MY17
MX7 8 1 2 MY11
[29] MX7 MX6 7 5
CP8 *100p/50Vx4
[29] MX6
MX5 6 7 8 MY12
[29] MX5 5 5 6
MX4 MY13 +TPVDD
[29] MX4 MX3 4 3 4 MY14 2N7002DW
[29] MX3
MX2 3 1 2 MY15 R634 *0_4
[29] MX2 MX1 2 CP9 *100p/50Vx4 R610 R611 50mil
[29] MX1 1
MX0
[29] MX0 C572 *100p/50V_4 MX1 +3V
MX0 10K_4 10K_4
C569 *100p/50V_4
KB_CONN CN17
+TPVDD 1
R618 *short_4 TPCLK_R 2
[29] TPCLK
+TPVDD R617 *short_4 TPDATA_R 3
[29] TPDATA
4
I2C_TP_SDA_R 5
+3VPCU I2C_TP_SCL_R 6
R621 C578 C577 7 9
[2,29] TPD_INT#
*10K_4 *0.1u/10V_4 *0.1u/10V_4 8 10
[29] TPD_EN
C RP7 C
10 1 MX0 TPD_EN
TP CN
MX7 9 2 MX1
MX6 8 3 MX2
MX5 7 4 MX3
MX4 6 5
*10K_10P8R
CPU FAN (THM)
+3V +5V +3V +5V
R119 R102 R103

1K_4 R101
+3VPCU 10K_4 10K_4 *short_8
+3VPCU [7,8,11,13,21,22,23,29,30,31,35,36,37]
+3V +3V [2,5,7,8,9,10,11,13,14,15,16,17,18,21,22,23,24,25,26,27,29,31,32,33,34,35,36] CN10
[29] FANSIG
+5V_FAN1 CPU
4 6
2
+5V
+5V [21,22,23,25,31,35] 3 5
1 3 FAN_PWM_CN1 2
[29] FAN1_PWM 1
Power tracking Q16 30mil FAN1
MMBT3904-7-F
B B
HOLE
EMI
HOLE17 HOLE14 HOLE12 HOLE16
*HG-C315D118P2 *HG-C315D158P2 *HG-C315D118P2 *HG-C315D118P2 HOLE8 HOLE6
7 6 7 6 7 6 7 6 EV@H-C236D140P2 EV@H-C236D140P2
8 5 8 5 8 5 8 5
9 4 9 4 9 4 9 4
1
2
3
1
2
3
1
2
3
1
2
3
LGND
VIN +1.35Vsus_Src +Vin_Gpu_Core +Vgpu_Core +1V_Src
HOLE9 HOLE13 HOLE11 HOLE15 HOLE10 HOLE7

*H-C146D146N *H-C146D146N *H-C146D146N *HG-C315D118P2 *HG-C315D146P2 *HG-C276D118P2 C583 C585 C586 C588 C589
7 6 7 6 7 6
8 5 8 5 8 5 1000p/50V_4 1000p/50V_4 1000p/50V_4 1000p/50V_4 1000p/50V_4
9 4 9 4 9 4
1
1
2
3
1
2
3
1
2
3
A A

PROJECT : ZQX
KB/TP/FAN 1B

5 4 3 2 1
5 4 3 2 1
L17 BLM15AG121SN1D/0.5A/120ohm_4 +A3VPCU +3VPCU

EC(KBC)
29
+3VPCU_ECPLL L15 BLM15AG121SN1D/0.5A/120ohm_4 +3VPCU_EC
C424
0.1u/10V_4 C407 (For PLL Power) S5_ON R394 10K_4
ECAGND 12 mils 0.1u/10V_4

+3V_RTC
12 mils HWPG
+3VPCU R413 2.2_6 +3VPCU_EC C412 SUSC# [7,13]
SUSB# [7,13]
C409 C405 C404 C145 C415 C431 0.1u/10V_4
+3VPCU_EC and +3V_RTC TP90
0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
minimum trace width 12mils. PTP_PWR_EN# [28]
TP84
TP82
R403 0_4 G_sen_INT [10,27] +3V_GFX
D R414 2.2_6 +3V_EC D
+3V
USB_BC_ON USB_BC_ON [27]
C419 CLKRUN# [7,21] dGPU_OPP# R424 *10K_4
0.1u/10V_4
114
121
127
MAINON R417 100K_4
11
26
50
92
74
84
83
82
19
20
99
98
97
96
93
3
U25
10 110 MBCLK SUSON R393 100K_4
VBAT
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
VCC
AVCC
EGCLK/WUI27/GPE3(Dn)
EGCS#/WUI26/GPE2(Dn)
EGAD/WUI25/GPE1(Dn)
L80HLAT/BAO/WUI24/GPE0(Dn)
L80LLAT/WUI7/GPE7(Up)
WUI42/GPH6/ID6(Dn)
WUI41/GPH5/ID5(Dn)
WUI40/GPH4/ID4(Dn)
WUI19/GPH3/ID3(Dn)
CLKRUN#/WUI16/GPH0/ID0(Dn)
[8,21,26] LPC_LAD0 LAD0/GPM0(X) SMCLK0/GPB3(X) MBCLK [30]
[8,21,26] LPC_LAD1 9 111 MBDATA MBDATA [30]
8 LAD1/GPM1(X) SMDAT0/GPB4(X) 115 2ND_MBCLK VRON R99 100K_4
[8,21,26] LPC_LAD2 LAD2/GPM2(X) SMCLK1/GPC1(X) 2ND_MBCLK [8,19]
[8,21,26] LPC_LAD3 7 116 2ND_MBDATA 2ND_MBDATA [8,19]
PLTRST# 22 LAD3/GPM3(X) SMDAT1/GPC2(X) 117 EC_PECR_R R392 43_4 PCH_SPI_SI_EC R395 *10K_4
+3VPCU [7,13,16,21,24,26] PLTRST# LPCRST#/WUI4/GPD2(Up) PECI/SMCLK2/WUI22/GPF6(Up) H_PECI [4]
13 118 PCH_SPI_SO_EC R396 *10K_4
SM BUS
[9] CLK_PCI_EC LPCCLK/GPM4(X) SMDAT2/WUI23/GPF7(Up) EC_FPBACK# [23]
[8,21,26] LPC_LFRAME# 6
LFRAME#/GPM5(X) 85 AC_Protect
PS2CLK0/TMB0/CEC/GPF0(Up) AC_Protect [30]
PROCHOT_EC 17 86 LID# [23]
LPCPD#/WUI6/GPE6(Dn) PS2DAT0/TMB1/GPF1(Up)
2
89 TPCLK [28]
6/30 add AC_protect for power request
D14 SIO_A20GATE 126 PS2CLK2/WUI20/GPF4(Up) 90
TP80 GA20/GPB5(X) PS2DAT2/WUI21/GPF5(Up) TPDATA [28]
R106 SDMK0340L-7-F 5
PS/2
100K_4
[10,21] IRQ_SERIRQ
[10] SIO_EXT_SMI# 15
23
SERIRQ/GPM6(X)
ECSMI#/GPD4(Up)
SM BUS PU(KBC)
[10] SIO_EXT_SCI# ECSCI#/GPD3(Up) LPC
1
WRST# 14 GPIO +3VPCU

4 WRST#
[10] SIO_RCIN# KBRST#/GPB6(X)
16 MBCLK R388 4.7K_4
[2,28] TPD_INT# PWUREQ#/BBO/SMCLK2ALT/GPC7(Up)/SMCLK2ALT
C139 MBDATA R389 4.7K_4
1u/6.3V_4 24 PWRLED# [21]
[23] PCH_BLON_EC 119

CRX0/GPC0(Dn)
IT8380 PWM0/GPA0(Up)
PWM1/GPA1(Up)
PWM2/GPA2(Up)
PWM3/GPA3(Up)
25
28
29
SUSLED#
BATLED1# [21]
SUSLED# [21]
BATLED0# [21]
+3V_S5
[31,32] SUSON 123 CIR 30 Sensor_PCH_CLK [10] 2ND_MBCLK R390 4.7K_4

CTX0/TMA0/GPB2(Dn) PWM4/GPA4(Up) 31 2ND_MBDATA R391 4.7K_4
PWM5/GPA5(Up) Sensor_PCH_DAT [10]
PWM
CLK_PCI_EC [32,35] MAINON 80
C DAC4/DCD0#/GPJ4(X) C
[26] BT_POWERON BT_POWERON 104 47
DSR0#/GPG6(X) TACH0A/GPD6(Dn) FANSIG [28]
[7] EC_PWROK 33 48 FAN2SIG TP15
SENSOR_EN 88 GINT/CTS0#/GPD5(Up) TACH1A/TMA1/GPD7(Dn)
R420 [27] SENSOR_EN Sensor_INT 81 PS2DAT1/RTS0#/GPF3(Up) 120
[10,27] Sensor_INT DAC5/RIG0#/GPJ5(X) TMRI0/WUI2/GPC4(Dn) DNBSWON# [7]
87 124 DPWROK [7]
*22_4 [28] TPD_EN E51_TXD 109 PS2CLK1/DTR0#/GPF2(Up) TMRI1/WUI3/GPC6(Dn) +3V
TP81 TXD/SOUT0/GPB1(Up)
108
[22] AMP_MUTE# RXD/SIN0/GPB0(Up) SCL_TO_EC R411 *4.7K_4
[7] PCH_SLP_SUS# 71 125 NBSWON# NBSWON# [13,27] SDA_TO_EC R408 *4.7K_4
C422 72 ADC5/DCD1#/WUI29/GPI5(X) PWRSW/GPE4(Up) 18 dGPU_OPP#
[30] ACIN
73 ADC6/DSR1#/WUI30/GPI6(X) UART port RI1#/WUI0/GPD0(Up) 21
dGPU_OPP# [19]
*10p/50V_4 [30] TEMP_MBAT SB_ACDC [30]
35 ADC7/CTS1#/WUI31/GPI7(X) RI2#/WUI1/GPD1(Up)
[23] TS_EN RTS1#/WUI5/GPE5(Dn) WAKE UP
[22] PCBEEP_EC PCBEEP_EC 34
107 PWM7/RIG1#/GPA7(Up) 112
[30] D/C# DTR1#/SBUSY/GPG1/ID7(Dn) RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7(Dn) RSMRST# [7]
[27] SDA_TO_EC SDA_TO_EC 95
SCL_TO_EC 94 CTX1/WUI18/SOUT1/GPH2/SMDAT3/ID2(Dn)
[27] SCL_TO_EC CRX1/WUI17/SIN1/SMCLK3/GPH1/ID1(Dn)
[8] PCH_SPI_CLK_EC 105
101 FSCK/GPG7
[8] SPI_CS0#_UR_ME FSCE#/GPG3 RF_EN [26]
[8] PCH_SPI_SI_EC 102 EXTERNAL SERIAL FLASH ICMNT ICMNT [30]
103 FMOSI/GPG4 66
[8] PCH_SPI_SO_EC FMISO/GPG5 ADC0/GPI0(X) H_PROCHOT# [4,30,34]
67 C423 10u/6.3V_6 ECAGND
ADC1/GPI1(X)
3
[28] MY16 56 68 APWORK [5,7]
57 KSO16/SMOSI/GPC3(Dn) ADC2/GPI2(X) 69 Q18
[28] MY17 KSO17/SMISO/GPC5(Dn) ADC3/GPI3(X) VRON [34]
[28] FAN1_PWM 32 70 FB_CLAMP_REQ# FB_CLAMP_REQ# [19]
PWM6/SSCK/GPA6(Up) ADC4/WUI28/GPI4(X) PROCHOT_EC 2
Please do not place any
S5_ON 100 A/D D/A
pull-up resistor [31,33,35] S5_ON
106 SSCE0#/GPG2(X)
on GPG0, GPG2, and GPG6 [8] ME_WR# SSCE1#/GPG0(X) SPI ENABLE
76 dGPU_OTP# [19] R105 2N7002K
TACH2/GPJ0(X)
(Reserved [28] MY0
36 77 EC_FB_CLAMP EC_FB_CLAMP [17,19]
1
37 KSO0/PD0 GPJ1(X) 78 100K_4
hardware strapping). [28] MY1
38 KSO1/PD1 DAC2/TACH0B/GPJ2(X) 79
PCH_PWROK [5,7]
[28] MY2 KSO2/PD2 DAC3/TACH1B/GPJ3(X) USBON# [27]
39
[28] MY3 KSO3/PD3
B 40 KBMX B
[28] MY4 KSO4/PD4
41
[28] MY5 KSO5/PD5
42
[28] MY6 KSO6/PD6
43
[28] MY7
44 KSO7/PD7 SWAP for EC request
[28] MY8 KSO8/ACK#
45
[28] MY9 KSO9/BUSY
46
[28] MY10
[28] MY11
51 KSO10/PE
KSO11/ERR# CK32KE/GPJ7
2 PCH_SUSACK# [7] HWPG(KBC)
KSI3/SLIN#
KSI1/AFD#
KSI0/STB#
KSI2/INIT#
52 128 PCH_SUSPWARN# [7] +3V

[28] MY12 KSO12/SLCT CK32K/GPJ6
53
VCORE
[28] MY13 KSO13

AVSS
54 CLOCK DDR=1.5V, D1 DNP and D2 POP

KSI4
KSI5
KSI6
KSI7
[28] MY14
VSS
VSS
VSS
VSS
VSS
VSS
55 KSO14
[28] MY15 KSO15 DDR=1.35V, D1 POP and D2 DNP R87
IT8380E-192/CX 10K_4
SM BUS ARRANGEMENT TABLE
58
59
60
61
62
63
64
65
27
49
91
113
122
75
12
D1
[35] HWPG_1.5V D12 RB500V-40 HWPG
[28] MX0 SM Bus 1 Battery D2
C421 [5] HWPG_1.05V D11 *RB500V-40
[28] MX1
ECAGND
[28] MX2
0.1u/10V_4 SM Bus 2 PCH/VGA [32] HWPG_VDDR D13 *RB500V-40
[28] MX3
[28] MX4
[5,13,33] HWPG_1.05V_S5 D10 RB500V-40
[28] MX5
[28] MX6 SM Bus 3 N/A
L16 [31] SYS_HWPG D9 RB500V-40
[28] MX7
BLM15AG121SN1D/0.5A/120ohm_4
SM Bus 4
For test only iRST

SW7
A 3 2 NBSWON# A
4 1
TP109 TP107
5
6
Power Switch

PROJECT : ZQX
1B
KBC IT8380
5 4 3 2 1
5 4 3 2 1
PJ6
1
VA1
1
2
3
PQ47
AOL1413
5
VA2
PD12
SBR1045SP5-13
1
2
3 1
PR185
0.02/F_0612
2
2/10 MODIFY
VIN
1
2
3
PQ32
AOL1413 30
5
2 PR186
3
1
*short 0_4
4 PC136 PC28 PR59 24737_ACN PC191 PC193 PR234
4
Power conn 0.1u/50V_6 0.1u/50V_6 220K_4 0.1u/50V_6 2200p/50V_6 33K/F_4
PD11
SMAJ20A 24737_ACP
2
D D
PC26 PC25 PR187
0.1u/50V_6 2200p/50V_6 1 6 *short 0_4
PD7 PR62 2 5 PR235

D/C# [29]
1N4148WS 220K_4 10K_4
recommend 200mA at least. 3 4 PR61
*short 0_4
PQ24
3
IMD2AT108
2
3,28,31,32,33,34,35,36,37] VIN 24737_ACP
PQ52
2N7002K
24737_ACN
1
PR125 VIN
*short 0_6 PC68 PC192 PC65
0.1u/50V_6 0.1u/50V_6 0.1u/50V_6
PR127
+3VPCU 63.4K/F_4 PC71 PC72
0.1u/25V_4
0.1u/25V_4
2
1
VIN
PR131 PC177
ACP
ACN
10K/F_4 1u/16V_6
C 24737_ACDET 6 16 24737_REGN C
ACDET REGN
PR220 PR233 PR229 PC189
*10K_4 100K_4 100K_4 0.1u/25V_4 PD13
24737_VCC 20 RB500V-40
VCC PR224 PC182 PC187
PR136 PC188 *short 0_6 2200p/50V_6 4.7u/25V_8 Add 11/14
20_1206 0.47u/25V_6 17 24737_BST
[29] ACIN BTST
5
PC184
47n/50V_6
[7] ACPRESENT
PQ51
PR227 18 24737_DH 4 MDV1528
HIDRV
6
*0_4 5
[29] SB_ACDC ACOK#
PR221 19 24707_LX
3
2
1
*short 0_4 PHASE PR208
0.01/F_0612
MBDATA 8 PU17 PL15
PQ53 SDA BQ24737RGRR 6.8uH_7X7X3
2N7002DW PR226 15 24737_DL 1 2 BAT-V
1
*short 0_4 LCDRV

PC194 MBCLK 9
SCL
5
0.1u/50V_6
+3VPCU PR222
PR213 *short 0_4 14 PR122
PC61 10K_4 PGND *4.7_6
*100p/50V_4 24737_BM# 11 4 PR211 PR209
BM# PQ50 *short 0_4
B *short 0_4 B
PR232 PC58 MDV1528
10K_4 24737_CMPOUT 3 PR212 10_6 0.1u/25V_4
3
2
1
BAT-V CMPOUT 13 24737_SRP 24737_SRP PC169 PC170 PC168
SRP PC53 2200p/50V_6 10u/25V_1206 10u/25V_1206
Delete Bat_EN 24737_ILIM 10 PC54 *680p/50V_6 24737_SRN
PJ7 ILIM 0.1u/25V_4
50458-00801-V01
PR142 *short 0_4 PR218 PR210 7.5_6

9 8 316K/F_4 24737_CMPIN 4 12 24737_SRN
7 CMPIN SRN
6 PR140 100_4 TEMP_MBAT
IOUT
GND
GND
GND
GND
GND
5 TEMP_MBAT [29]
PC171
4 0.1u/25V_4
3 PR214 PR230
+3VPCU
21
22
23
24
25
2 PR141 1M_4
10 1 100K/F_4
*100K_4
PC74 PC73
*47p/50V_4 *47p/50V_4 +1.05V
PR215 PC173
100K/F_4 0.01u/25V_4
REGN MAX voltage 6.5V
3
PR138
PR143 PR139
100_4 100_4 PR135
*100K_4 V_ILIM=20*(VSRP-VSRN)=20*Ichg*Rsr
24737_BM# 2 PR231
MBCLK [29]
SP@133K/F_4
*0_4
=0.793V for 3.965A current limit
H_PROCHOT# [4,29,34]
PQ31
3
*2N7002K Pin10 ILIM=0.793V
A [29] ICMNT A
MBDATA [29]
1
Rsr = 0.01ohm
PU18 24737_CMPOUT 2
*IP4223-CZ6
2014/06/18 modify
1 6 MBDATA PC186 PQ33
CH1 CH4 100p/50V_4 2N7002K
2 5
+3VPCU PR135 Value PR242 Quanta Computer Inc.
1
VN VP *short 0_4
TEMP_MBAT 3 4 MBCLK Delete SW6 for ACER request
CH2 CH3 No system power cut off mechanism 65W-DIS CS41332FB06 133K PROJECT : ZQX
Add ESD diode base on EC FAE suggestion Limit set on 65W(DIS)/40W(UMA) 1B
40W-UMA CS34022FB15 40.2K
[29] AC_Protect Charger(BQ24737RGRR)
5 4 3 2 1
5 4 3 2 1
SYS_SHDN#
31
SYS_SHDN# [10,21,35]
MAIND
MAIND [33,35]
1/13 Adding +3VSUS power for touch pad
(By acer request)
VIN +3VSUS +15V VIN +3VPCU
JP11
*short 0.001/F_3720
PR238 PR236 PR239 PR240
D SYS_SHDN# 1M_6 22_8 1M_6 *1M_6 D
3
3VPCU_VIN 1 2 VIN
2200p/50V_6
4.7u/25V_8
4.7u/25V_8
4.7u/25V_8
4.7u/25V_8
PR24 SUSD 2
*short 0_4
3
PR21
*499K/F_4 PR163 PQ67
1/F_6 2 AO3404
1
[29,32] SUSON
670_BST 670_BST1 2 2
PC98
PC97
+3VPCU
PC112
PC104
PC117
+3VSUS
PR237 PQ65 PQ64
1
PC110 PQ66 1M_6 2N7002K 2N7002K
*0.1U/10V_4 DTC144EU PC195
10
TDC : 0.038A
1
1
PR13 PC109 +3VPCU *2.2n/50V_4
100K/F_4 0.1u/50V_6 PL7 +3VPCU PEAK : 0.05A
VIN
BST
670_EN 13 8 670_SW
3.3uH_7X7X3
1 2
3.3 Volt +/- 5% Width : 20mil
EN SW1 TDC : 4.3A
SYS_HWPG PR7 *short 0_4 670PG 4 9
[29] SYS_HWPG PG SW2 PEAK : 5.8A
0.1u/50V_6
22u/6.3V_8
22u/6.3V_8
22u/6.3V_8
+3V_LDO
3
LP# SW3
15 JP6 Width : 180mil
PU10 PR11 *short 0.001/F_3720
220u/6.3V_6X4.2
PR25 *0_4 670_ENLDO 12 NB670GQ-Z 16 *4.7_6
ENLDO SW4 +
PC127
SYS_SHDN# 6 7
LDO VOUT
PR153 10K/F_4 14 2
AGND PGND
PC13
PC14
PC16
PC93 PC8
PC105
VCC
CLK
10u/6.3V_6 PC7 *680p/50V_6
*0.1u/16V_4
11
LDO(MAX)=100mA 670_CLK
C VIN +15V VIN +5VPCU +3VPCU C
+3V_S5 +5V_S5
PC111
1u/6.3V_4
PC83 PC87 PC86 PR121 PR56 PR117 PR120 PR119
5
0.1u/50V_6 0.1u/50V_6 0.1u/50V_6 1M_6 22_8 22_8 1M_6 *1M_6
3
PD8 PD9 PD10
3
1PS302 1PS302 1PS302 S5D 4 S5D 2

PQ25
3
PR14 MDV1528Q
PQ11
3
2
1
1
2 AO3404
1
[29,33,35] S5_ON
*short 0_6 2 2 2
+15V +5V_S5 +3V_S5
PR118 PQ21 PQ29 PQ28
1
PQ30 1M_6 2N7002K 2N7002K 2N7002K
PR147 PC82 PC76 PC88 DTC144EU PC52
TDC : 3A TDC : 0.6A
1
22_8 0.1u/50V_6 0.1u/50V_6 0.1u/50V_6 *2.2n/50V_4
PEAK : 4A PEAK : 0.81A
Width : 120mil Width : 40mil
JP18
*short 0.001/F_3720
+5VPCU +3VPCU
5VPCU_VIN 1 2 VIN
2200p/50V_6
4.7u/25V_8
4.7u/25V_8
4.7u/25V_8
4.7u/25V_8
3
B + B
PR228 PR216
2
*499K/F_4 1/F_6 PC167 MAIND 4 MAIND 2
671_BST 671_BST1 33U/25V_6x4.5 PQ26
PC70
PC66
PC64
PC190
PC185
MDV1528Q
PQ10
3
2
1
AO3404
1
10
1
PC175 +5VPCU
0.1u/50V_6 PL14 +5VPCU +5V +3V
VIN
BST
671_EN 13 8 671_SW
3.3uH_7X7X3
1 2
5 Volt +/- 5%
PR217 *short 0_4 EN SW1 TDC : 5.5A TDC : 2.41A TDC : 0.62A
SYS_HWPG 671PG 4
PG SW2
9
PEAK : 7.4A PEAK : 3.21A PEAK : 0.83A
0.1u/50V_6
22u/6.3V_8
22u/6.3V_8
22u/6.3V_8
3
LP# SW3
15 JP15 OCP : 9A Width : 100mil Width : 40mil
PR225 *short 0_4 PU16 PR123 *short 0.001/F_3720
*220u/6.3V_6X4.2
SYS_SHDN# 5 NB671 16 *4.7_6 Width : 220mil

NC1 SW4 +
PC166
6 7
NC2 VOUT
PC63 PR219 14 2
AGND PGND
PC57
PC51
*0.1U/10V_4 *short 0_4 PC59

PC172
PC179
VCC
PC178 *680p/50V_6
FB
0.1u/16V_4
11
12
VL
PC181 671_FB
1u/6.3V_4
VREF=0.604V PR126
A A
82K/F_4
PR129
11K/F_4
PR132

*short 0_6
PROJECT : ZQX
1B
SYSTEM 5V/3V (TPS51225)
5 4 3 2 1
5 4 3 2 1
TDC : 0.75A
PEAK : 1A
Width : 40mil
+DDR_VTT_RUN
32
PC38 PC37
10u/6.3V_6 10u/6.3V_6
D TDC : 0.38A D
PEAK : 0.5A DDR_VTTREF
Width : 20mil
Close to IC
Greater than or equal 40mil
PC36
0.22u/10V_4
+5V_S5
PR66 *SHORT_4 +5VPCU

+3V
PR65 *0_4 VIN
PC145
22
21
10u/6.3V_6
2
PR76 PC32
100K/F_4 1u/10V_4
PAD
PAD
VTTGND
VLDOIN
VTTSNS
VTTREF
VTT
+1.35V_SUS
5
20 12
1.35 Volt +/- 5%
C
[29] HWPG_VDDR PGOOD V5IN PC140 PC139 TDC : 4.8A C
PR69 51216_S3 17 14 51216_DRVH 4

2200p/50V_4 4.7u/25V_8
PEAK : 6.4A
[29,35] MAINON S3 DRVH
*0_4 PR64 PC31
+1.35VSUS_SRC JP14
OCP : 8A
2/F_6 0.1u/50V_6 PQ48
[29,31] SUSON
PR67 51216_S5 16 15 51216_VBST MDV1528 *short 0.001/F_3720 Width : 200mil
3
2
1
*short 0_4 S5 PU6 VBST PL11
TPS51216RUKR 2.2uH_7X7X3
PR72 51216_MODE 19 13 51216_SW +1.35VSUS_SRC 1 2 +1.35V_SUS
200K/F_4 MODE SW
5
PR71 51216_TRIP 18 11 51216_DRVL
TRIP DRVL +1.35V_SUS [4,5,14,15]
82K/F_4 PQ49
VDDQSNS
MDV1595S PR63
26 10 4 *4.7_6
PAD PGND
REFIN
GND
PAD
PAD
PAD
REF
+
PC137 PC138
3
2
1
VREF=1.8V PC29 0.1u/50V_6 330u/2.5V_6X4.2
6
25
24
23
7 *680p/50V_6
51216_REF
51216_REFIN
PC34 PR190
B 0.1u/10V_4 *short 0_6 B
RDSon=2.2mohm
PR68
51216_S3 PR188 51216_S5 10K/F_4 Close to output cap
*0_4
51216_S3 PR70 DDR_VTTT_PG_CTRL [4]

*short 0_4
PR189 PC33
30.1K/F_4 0.01u/25V_4 Mode Frequency Discharge mode
200K 400K Tracking Discharge
OCP=8A 100K 300K Tracking Discharge

L ripple current
=(19-1.35)*1.35/(2.2u*400k*19)
=1.425A
A DDR=1.35V A
Vtrip=8-(1.425/2)*14mohm S3 S5 +1.35VSUS REF VTT
=102.024mV PR84=10K/F_4
Rlimit=102.024mV/10uA*8=81.62Kohm PR86=30.1K/F_4 S0 1 1 ON ON ON Quanta Computer Inc.
S3 (mainon off) 0 1 ON ON OFF PROJECT : ZQX
S4/S5 0 0 OFF OFF OFF 1B
DDR 1.35V(TPS51216)
5 4 3 2 1
5 4 3 2 1
JP7
*short 0.001/F_3720
33
1 2 VIN
D D
+5VPCU
+3V
PC129 PC132 PC133

1u/10V_4 2200p/50V_6 4.7u/25V_8
5
PR172
100K/F_4
7
PQ40
MDV1528
V5IN
51211V_DRVH 4
1 9 PR176 PC130 +1.05V_S5
[5,13,29] HWPG_1.05V_S5 PGOOD DRVH +1V_SRC
*short 0_60.1u/50V_6
51211V_EN 3 10 51211V_VBST PL10
[29,31,35] S5_ON
3
2
1
PR34 *short 0_4 EN VBST 2.2uH_7X7X3
51211V_TRIP 2 PU12 8 51211V_SW +1V_SRC 1 2
PR173 82K/F_4 TRIP TPS51211DSCR SW
51211V_TST 5 6 51211V_DRVL
PR175 464K/F_4 TST DRVL
5
12 11 JP13
C PR174 GND GND PR45 PR37 *short 0.001/F_3720 C
GND
GND
GND
GND
*100K/F_4 *4.7_6 5.1K/F_4
+1.05V
FB
+
4 1.05 Volt +/- 5%
13
14
15
16
4
PC128 PC131
51211V_FB 0.1u/50V_6 330u/2.5V_6X4.2 TDC : 4.7A
PQ41 PC21
PEAK : 6.3A
3
2
1
MDV1595S *680p/50V_6 PR35
10K/F_4 OCP : 8A
Width : 200mil
OCP=8A VFB=0.7V
L ripple current
=(19-1.05)*1.05/(2.2u*290k*19)
=1.555A +1.05V_S5
Vtrip=8-(1.555/2)*14mohm
B =101.12mV B
5
Rlimit=101.12mV/10uA*8=80.89Kohm
MAIND 4 PQ42
[31,35] MAIND
MDV1528Q
VIN +1.05V_MODPHY +15V +1.05V_S5
3
2
1
+1.05V_MODPHY +1.05V
PR47 PR184 PR58
+1.05V
3
*1M_4 *22_8 *1M_4 PR60 *short 0_8
MODPHY_D 2 TDC : 2.31A

PEAK : 3.08A
3
Width : 100mil
3
PQ23
*AO3404
1
PR49 *0_4 2 PR46 2 2
A [10] MODPHY_EN PC27 +1.05V_MODPHY A
*1M_4 +1.05V_MODPHY
1
PQ14 PQ46 PQ15 *2.2n/50V_4

*PDTC143TT *2N7002K *2N7002K TDC : 1.43A
1
PC22 PR48
PEAK : 1.9A
1
*1u/10V_4 *100K_4
Width : 80mil PROJECT : ZQX
2

1B
+1.05V_S5 (TPS51211)
5 4 3 2 1
5 4 3 2 1
IMON offset
Place NTC close to the
VCORE Hot-Spot. +5V_S5
+VIN_VCCIN
1
JP16
*short 0.001/F_3720
2 VIN
34
+VIN_VCCIN +3V_S5 51624_VREF +5V_S5
2200p/50V_4
33U/25V_6x4.5
1
0.1u/50V_6
4.7u/25V_8
4.7u/25V_8
PC147
PC150
PC40
PC39
PC143
PC144 +
100K/F_4_4250NTC
1u/10V_4
2
665K/F_4
20/F_6
36.5K/F_4
*90.9K/F_4
*39.2K/F_4
2
PR105
PR77
PR78
PR79
PR200
PR203
PR110
10K/F_4
PR87
1_6
PR88
D 2M/F_4 D
VDD
51624_SKIP# 1 5 PL12
SKIP# VIN 0.15uH_7X7X4
8 4 1 2
DCR= 1mOhm
PR89 2M/F_4 51624_OCP-I 51624_VRON 51624_PWM1 PR196 *SHORT_4 51624_PWM1_R CS_SW1 +VCCIN
PWM VSW
CS_BSTR1 6 3
4
BOOT_R PGND
PC47
PR73
1n/50V_4
20K/F_4
100K/F_4
150K/F_4
39K/F_4
PC159
1u/6.3V_4
2.26K/F_4
0.33u/6.3V_4
PR86
PR85
PR199
CS_BST1 7 9
1000p/50V_6 2.2_6
PR83 2.2u/10V_6 +
9.09K/F_4
BOOT PAD
PC158
PR84
PR198
PC149
PR80
*330u/2V_7343
100K/F_4
30K/F_4
0.1u/10V_4
22u/6.3V_8
22u/6.3V_8
PR75 *short 0_4
PC30
PC141
PC142
PC146
PR197 PC148 PU14
PC35
2.2/F_6 0.22u/25V_6 CSD97374CQ4M
Add 11 GND VIAs
for thermal pad
PR74
51624_CSP1
2.94K/F_4
+1.05V
PR191
51624_B-RAMP
51624_SLEWA
51624_F-IMAX
51624_O-USR
Close to VR 51624_THERM PC151
51624_VREF
51624_VDD
*0.1u/25V_4
0.12u/10V_4
PC152
51624_V5A
16.9K/F_4
10K/F_4_3435KNTC
PR201
51624_VBAT
0.1u/10V_4
56_4
PC164
PR113
PR115
PR114
PR206
*56_4
130/F_4
*75/F_4
PR192
51624_CSN1
BW-U 15W(1 phase) BW-U 28W(1 phase)
27
10
11
15
14
28
16
2
9
PC153
*0.1u/25V_4
VDD
O-USR
VREF
VBAT
F-IMAX
B-RAMP
SLEWA
V5A
THERM
Icc TDC PL2：14A Icc TDC PL2：19A
30 6 51624_PWM1
C
[4,29,30] H_PROCHOT# VR_HOT PWM1 C
[5] VR_SVID_CLK VR_SVID_CLK PR107 51624_CLK

*short 0_4 31
VCLK PWM2
5 51624_PWM2 Icc Max：32A Close to the Close with Icc Max：40A
VR side. phase1 inductor
VR_SVID_ALERT# PR108 51624_ALERT# 32
*short 0_4 4 51624_MODE
[5] VR_SVID_ALERT# ALERT MODE OCP：37A OCP：47A
[5] VR_SVID_DATA VR_SVID_DATA PR109 51624_DATA
*short 0_4 1 17 51624_CSP1
VDIO CSP1
3
PGOOD
PU7
CSN1
18 51624_CSN1 Fsw：1.2MHz Fsw：800KHz
TPS51624RSM
+3V +3V +3V 51624_SKIP# 7 19 51624_CSN2
SKIP CSN2 PS3 OSR
51624_VRON 8
VR_ON CSP2
20 51624_CSP2 ：
VCORE L/L：：
VCORE L/L：
51624_VFB 24 21
*100K/F_4
*100K/F_4
*100K/F_4
VFB NC R_DC_LL：- 2.0mV/A Rmode 100K Ohm ON ON R_DC_LL：- 2.0mV/A

PR205
PR202
PR91
51624_GFB 23 22 PR101
GFB N/C 150K/F_4
DROOP
COMP
OCP-I
IMON
R_AC_LL：- 7.0mV/A 150K Ohm ON OFF R_AC_LL：- 7.0mV/A
GND
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
51624_VREF
26
25
12
13
29
33
34
35
36
37
38
39
40
41
42
[5,10] IMVP_PWRGD
PR103 *short 0_4
51624_DROOP
51624_OCP-I
51624_IMON
For BW-U 28W 2 phase

51624_COMP
[29] VRON
PR94 *0_4 PR193
*short 0_8 +VIN_VCCIN
4.7K/F_4
*short 0_4
*short 0_4
[5] VRON_CPU
PR82 *short 0_4
+VCCIN
+5V_S5
PC50
PR111
PR90
10K/F_4
365K/F_4
*100p/50V_4
*2200p/50V_4
B B
*0.1u/50V_6
*4.7u/25V_8
*4.7u/25V_8
PC160
PC161
PC45
PC48
PC154
4700p/25V_4
PC44 *1u/10V_4
PR102
PR100
PR106
PC41
PR104 *330p/50V_4
*10_4
2
1500p/50V_4
VDD
PR112
PR81
51624_SKIP# 1 5
39K/F_4
PL13
4.75K/F_4
[5] VCC_SENSE SKIP# VIN

PC46
*0.24uH_7X7X4 DCR= 1mOhm

51624_PWM2 8 4 CS_SW2 1 2
[12] VSS_SENSE +3V_S5 PWM VSW +VCCIN
CS_BSTR2 6 3
4
BOOT_R PGND
PR96
*1.82K/F_4
CS_BST2 7 9
*1000p/50V_6 *2.2_6
PR97
PC43 BOOT PAD
Parallel *10_4
*0_4
*0.01u/50V_4
*0.1u/10V_4
*22u/6.3V_8
*22u/6.3V_8
PC49
PC162
PC163
PR98 PR207 PC165 PU15
PC42
Close to the 0_4 *2.2/F_6 *0.22u/25V_6 *CSD97374CQ4M
CPU side. Add 11 GND VIAs
for thermal pad
PR92
PR93
BW-U 28W 2 phase 51624_CSP2 51624_CSP2
BW-U 28W 1 phase 15W
*10K/F_4_3435KNTC *2.67K/F_4
PR194
Location Value Location Value 51624_PWM2 PC157
*0.1u/25V_4
*0.15u/10V_4
Location Value Value
、PL8
PC156
PL7、 0.24uH_7X7X4 PR75 56.2K/F_4 51624_CSN2
*22.6K/F_4
PR204
PR63 CS22212FB11 CS22262FB05
PR63 1.82K/F_4 PR95 2.37K/F_4
PR195
51624_CSN2
A A
PR191 CS32262FB15 CS31692FB11
、PR194
PR191、 *22.6K/F_4 PR101 10K/F_4 PR95 PR99 PC155
PR67 CS45232FB00 CS46652FB10

PR182 2.67K/F_4 PR79 150K/F_4
0_4 *0_4
Block 1. *0.1u/25V_4
PR95 CS24752FB12 CS24992FB26

、PC148
PC144、 0.15u/10V_4 、PR87
PR84、 *0_4 Close to the Close with
VR side. phase1 inductor
PR70 CS35622FB10 CS33902FB16 、PC145
PC142、
PR67 294K/F_4 、PC149 *0.1u/25V_4
PC147、 PROJECT : ZQX
PR79 CS44122FB00 CS43652FB10 1B
Block 1. Stuff +VCCIN(TPS51624)
5 4 3 2 1
1 2 3 4 5
+3VPCU
1 2
+1.5V
1.5Volt +/- 5%
+1.5V
35
+3V
JP8 PC69 PC67 TDC : 0.56A
1
*short 0.001/F_3720 10u/6.3V_6 0.1u/25V_6
PU8 TPS54318RTER
PEAK : 0.75A JP17
PR130 16
VIN PH
10 Width : 40mil *short 0.001/F_3720
A
100K/F_4 A
1 11 PL16
VIN PH 1uH_7X7X3
2
2 12
VIN PH
14 13 PR124 *short 0_6
[29] HWPG_1.5V PW RGD BOOT
MAINON 15 6 PC56
EN VSNS 0.1u/50V_6 PR134
7 3
R1
PR133 100K/F_4
*short 0_4 COMP GND PC176 PC174 PC55
8 4 0.1u/10V_4 10u/6.3V_6 10u/6.3V_6
RT/CLK GND 1.5V_VSNS
PAD
PAD
PAD
PAD
PAD
PAD
PC183 9 5
1000p/50V_4 PR223 PR128 SS AGND
8.06K/F_4 121K/F_4 VFB=0.8V R2 PR137
22
21
20
19
18
17
113K/F_4
PC62 PC180 PC60

*100p/50V_4 1500p/50V_4 0.01u/25V_4
V0=0.8*(R1+R2)/R2
B B
VIN
Thermal protection
PD6
DA2J10100L
Need fine tune
for thermal protect point VIN +3V +5V +1.05V +15V
Note placement position
TEMP=85C
PR53 PR39 PR33 PR116 PR50 PR40
1M_6 1M_4 22_8 22_8 22_8 1M_4
1
PQ18
AO3409 MAINON_ON_G MAIND
2 MAIND [31,33]
3
3
3
PR38
2 PQ6 1M_4 2 2 2 2
3
S5_ON 2 [29,32] MAINON DTC144EU PC18

[29,31,33] S5_ON
PQ38 PQ27 PQ16 PQ7 *2200p/50V_4
2N7002K 2N7002K 2N7002K 2N7002K
1
PQ19 PR52 PR31
1
1
DTC144EU *short 0_6 *100K/F_6
C C
VL VL
SYS_SHDN# [10,21,31]
change PR164 to 1.47k
for power request 11/07 (85c)
PR178 PC23 PR51
PR179 200K/F_4 0.1u/50V_6 200K_6
3
1.58K/F_4
8
PR180
10K/F_4_3435NTC 2.469V 3
+ 1 2
LM393_PIN2 2
- PQ43
3
PU13A 2N7002K
4
AS393MTR-E1 PC134
1
0.1u/50V_6
S5_ON 2
PR177
PQ17 200K/F_4
2N7002K
1
D 5 D
+ 7
6
-
PU13B
AS393MTR-E1

For EC control thermal protection (output 3.3V) PROJECT : ZQX
1B
+1.5V/Thermal Protect
1 2 3 4 5
5 4 3 2 1
SP@ : GT@ GM@ UMA@ +5V_S5

36
JP12
PR27 *short_3720
*short_6 +VIN_GPU_CORE
1 2 VIN
D D
EV@2200p/50V_4
EV@0.1u/50V_6
EV@4.7u/25V_8
EV@4.7u/25V_8
EV@33U/25V_6x4.5
1
PR160
18 1658R-PVCC
PC20
PC126
PC121
PC122
PC106
PR22 EV@10K/F_4 PR23 EV@20K/F_4 EV@2.2/F_6 +
1
3V_MAIN_PWGD 1658R-VREF 1658R-BOOT1
PC9
2
EV@1U/10V_4
2
PC12 *0.01U/25V_4 PC99
5
PR8 1 2 EV@0.22u/25V_6
EV@100K/F_4 PU11
1 1658R-BOOT1
PVCC
+VIN_GPU_CORE PR29 *1/F_4 PR26 *499K/F_4 1658R-OCS/CB 9 BOOT1 1658R-UGATE1 4 PQ34
OCS/CB 2 1658R-UGATE1 EV@AON6414AL
PR155 *short_4 UGATE1
[18,37] 3V_MAIN_PWGD
1
2
3
20 1658R-PHASE1 PL6
VGPU_EN PR156 *0_4 1658R-EN 3 PHASE1 EV@0.24uH_7X7X3
[8] VGPU_EN EN 19 1658R-LGATE1 1658R-PHASE1
DCR=1.1m ohm
LGATE1 +VGPU_CORE
DGPU_PSI PR157 *short_4 1658R-PSI 4
[19] DGPU_PSI
5
PSI PR10
EV@UP1658RQKF EV@2.2/F_6
PWM-VID PR158 *short_4 1658R-VID 5 15 1658R-BOOT2 +
EV@330u/2V_7343
[19] PWM-VID VID BOOT2 1658R-LGATE1 4
EV@0.1u/10V_4
EV@10u/6.3V_8
14
PC17
PC101
PC119
1658R-UGATE2
1 2 1658R-VREF 8 UGATE2
1
2
3
PC107 EV@1U/10V_4 VREF 16 1658R-PHASE2 PQ36 PC6
PHASE2 EV@AON6752 EV@1000p/50V_6
1658R-REFADJ 6 17 1658R-LGATE2 PR169 EV@10K_4
REFADJ LGATE2 1 2 +3V
C C
+3V_S5 +3VPCU 7
R1 PR20 REFIN 13 1658R-PG PR28 *short_4
PR161 SP@20K/F_4
R2 PGOOD GPU_PWR_GD [17]
1658R-REFIN
*0.01U/25V_4
2
PC103
SP@20K/F_4 12 1658R-COMP
PR6 PR12 COMP
EV@4700P/25V_4
GND
EV@10K_4 *10K_4 10
FB
1
FBRTN +VIN_GPU_CORE
PC115
1
PR170
1
11
21
DGPU_PSI PR15 EV@2.2/F_6
EV@22P/50V_4
R3
2
1658R-FBRTN
PC100 SP@2K/F_4 1658R-BOOT2
2
PC116
SP@2700P/50V_4
EV@2200p/50V_4
EV@16K/F_6
EV@0.1u/50V_6
EV@4.7u/25V_8
EV@4.7u/25V_8
1658R-FB
PR9
PC92
PC91
PC78
PC77
PR171
*0_4 PC113
5
EV@0.22u/25V_6
1658R-UGATE2 4
PR17
SP@18.2K/F_4
R4
1
2
3
Phase Number of Operation *22P/50V_4 PQ39 PL9
1
EV@AON6414AL EV@0.24uH_7X7X3
*short_4
*short_4
DCR=1.1m ohm
PC114
PR166
PR165
PR16 1658R-PHASE2 +VGPU_CORE
*5.1K/F_4
2
5
PR18 PR30
SP@0_4
R5 +
EV@330u/2.5V_6X4.2
EV@2.2/F_6 +
EV@330u/2V_7343
3
1658R-LGATE2 4
EV@0.1u/10V_4
EV@10u/6.3V_8
PC123
PC102
PC90
PC108
PR159 *82.5/F_4
B B
1
2
3
VGA_STBY 2 1 2 PQ37 PC11
TP77
PQ35 EV@AON6752 EV@1000p/50V_6
*2N7002K
1
Standby PC95
1
Function *1U/10V_4
2
+VGPU_CORE
PR168 N15V-GM
*short_4
N15S-GT(840M) N15V-GM(820M)
+VGPU_CORE
PR167 *short_4
Location QCI P/N Value QCI P/N Value
[16] VGA_VCCSENSE Countinue current:A
[16] VGA_VSSSENSE PR161 CS32002FB29 20K CS32702FB16 27K Peak current:43A
PR164 *short_4
OCP:64A
PR162
PR20 CS32002FB29 20K CS27502FB11 7.5K
*short_4
FSW:300KHz
PR15 CS22002FB19 2K CS00002JB38 0 L/L=0mV/A
A
Parallel A
PR17 CS31822FB16 18K CS26202FB17 6.2K

PR18 CS00002JB38 0 CS21742FB00 1.74K
PC100 CH22706KB14 2.7N CH25604KB18 5.6N Quanta Computer Inc.
PROJECT : ZQX
1B
+VGPU_CORE(UP1642PQAG)
5 4 3 2 1
5 4 3 2 1
[16,17,18] +1.05V_GFX
[17,20] +1.5V_GFX
[16,17,18,19,29] +3V_GFX
2013/12/19 Change to converter JP9
*short_3720
37
1.5VGFX_VIN 1 2 VIN
PC85 EV@2200p/50V_6
PC80 EV@4.7u/25V_8
PC75 EV@4.7u/25V_8
PC81 EV@4.7u/25V_8
PC79 EV@4.7u/25V_8
D D
PR144 PR154
*499K/F_4 EV@1/F_6
2014/06/12 modify NB671_VCC 1.5VGFX_BST 1.5VGFX_BST1
10
+1.5V_GFX
1
PR148 PC96 +1.5V_GFX
EV@100K/F_4 EV@0.1u/50V_6 PL8 1.5 Volt +/- 5%
VIN
BST
EV@3.3uH_7X7X3
1.5VGFX_EN 13
EN SW1
8 1.5VGFX_SW 1 2 TDC : 3.2A
PEAK : 4.3A
EV@0.1u/50V_6
EV@22u/6.3V_8
EV@22u/6.3V_8
EV@22u/6.3V_8
[17] HWPG_1.5VGFX 1.5VGFX_PG 4 9
PG SW2
PR150 *short_4
3 15
Width : 130mil
PR241 JP10
EV@200K/F_4 LP# PU9 SW3 PR19 *short_3720
5 EV@NB671 16 *4.7_6
NC1 SW4
6 7
NC2 VOUT
PR145
*short_4
[17] FBVDDQ_EN PR149 *short_4 14 2
AGND PGND
PC118
PC125
PC120
PC124
PC10
VCC
PC84 PC94 *680p/50V_6
FB
*0.1U/10V_4 EV@0.1u/16V_4
C C
11
12
NB671_VCC
PC89 1.5VGFX_FB
EV@1u/6.3V_4
PR146 PR152
VREF=0.604V EV@82K/F_4
QCI P/N
*short_6 PR151
EV@64.9K/F_4
54.9K/F_4 CS35492FB14
64.9K/F_4 CS36492FB17
VIN +1.05V_GFX +15V +1.05V_S5
PR55 PR181 PR54
3
EV@1M_4 EV@22_8 EV@1M_4
dGPU_D1 2
B B
3
3
3
PR182 PQ20
*short_4 PR57 EV@AO3404 +1.05V_GFX
1
[18,36] 3V_MAIN_PWGD
2 EV@1M_4 2 2
PC24 +1.05V_GFX
TDC : 1.72A
PEAK : 2.29A
1
PQ45 PQ22 *2.2n/50V_4

PQ44 EV@2N7002K EV@2N7002K
Width : 80mil
1
PC135 PR183 EV@PDTC143TT

1
1
*1u/10V_4 EV@100K_4
2
VIN +3V_GFX +15V +3VPCU
PR43 PR44 PR41
3
EV@1M_4 EV@22_8 EV@1M_4
dGPU_D 2
3
3
3
PR36 PQ9
A
*short_4 PR42 EV@AO3404 +3V_GFX A
1
[10] DGPU_PWR_EN
2 EV@1M_4 2 2
PC19
+3V_GFX
TDC : 0.26A
PEAK : 0.35A
1
PQ12 PQ13 *2.2n/50V_4

PQ8 EV@2N7002K EV@2N7002K
Width : 20mil Quanta Computer Inc.
1
PC15 PR32 EV@PDTC143TT

1
*1u/10V_4 EV@100K_4
PROJECT : ZQX
2

1B
+1.5V_GFX/+1.05V_GFX/+3V_GFX
5 4 3 2 1
1 2 3 4 5 6 7 8
+3V_S5 +3V 38
SDRAM
2.2K 2.2K 4.7K 4.7K
+3V
AP2 SMB_PCH_CLK CLK_SCLK
2N7002DW
AH1 SMB_PCH_DAT Level shift CLK_SDATA Touch PAD
A A
+3V
XDP
4.7K 4.7K
+3V
WLAN_CLK_SCLK
2N7002DW
Haswell Level shift WLAN_CLK_SDATA WLAN
ULT
+3V_S5
2.2K 2.2K
AN1 SMB_ME0_CLK
AK1 SMB_ME0_DAT
B B
+3V_S5
*2.2K *2.2K
+3V_S5
AU3 SMB_ME1_CLK
*2N7002DW
AH3 SMB_ME1_DAT Level shift
+3V_S5 +3V_GFX
4.7K 4.7K 10K 10K
+3V_GFX
116 2ND_MBDATA
2N7002DW
115 2ND_MBCLK Level shift dGPU
C C
+3VPCU
100
10K 10K Battery

SIO 100
110 MBCLK
ITE8380 111 MBDATA Charger
+3V
4.7K 4.7K
19 LIGHT_SCL
20
LIGHT_SDA Light sensor
+3V
D
G-sensor D
4.7K 4.7K
94 SCL_TO_EC
95
SDA_TO_EC Gyro/Accelerometer
PROJECT : ZQX
Ecompass Size Document Number Rev
1B
Block Diagram
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
VGA power up sequence

39
+3VPCU
PCH MOSFET +3V_GFX

A A
dGPU_PWR_EN
VGA_VID
VIN
+VGPU_CORE
VGPU_EN VIN +1.5V_GFX

PWM
+1.05V_S5
PWM
VGPU_PWRGD
OR FBVDDQ_EN DGPU_PWROK
Gate MOSFET +1.05V_GFX
HWPG_1.5VGFX
1.05V_GFX_EN
VGPU_PWRGD
EC_FB_CLAMP
EC
B B
VGA Reset Power States

Thermal Follow Chart
CONTROL
POWER PLANE VOLTAGE DESCRIPTION SIGNAL ACTIVE IN
PLTRST# VIN +10V~+19V MAIN POWER ALWAYS ALWAYS

PEGX_RST# CPU NTC
PCH DGPU_HOLD_RST#
+3V_RTC +3V~+3.3V RTC POWER ALWAYS ALWAYS Thermal
+3VPCU +3.3V EC POWER ALWAYS ALWAYS Protection
PEX_RST timing +5VPCU +5V USB CHARGE POWER ALWAYS ALWAYS
+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS

CPU H_PROCHOT# PM_THRMTRIP# SYS_SHDN# 3V/5 V
I/O 3.3V +3V_S5 +3.3V LAN/BT POWER S5_ON S0-S5 CORE PWR H/W Throttling WIRE-AND SYS PWR
PEX_RST +5V_S5 +5V USB POWER S5_ON S0-S5
HSW ULT
+5V +5V HDD/SPK/HDMI POWER MAINON S0
C Trise >= 1uS Tfail <=500nS C
+3V +3.3V PCH/GPU/Peripheral component POWER MAINON S0
+1.35VSUS +1.35V CPU/SODIMM/MD POWER SUSON S0-S3
+DDR_VTT_RUN +0.675V SODIMM/MD Termination POWER MAINON S0 GPU NTC

SM-Bus1
Thermal
LCDVCC +3.3V LCD POWER LVDS_VDDEN S0 Protection CPU FAN
FAN1_PWM
+1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0
+1.05V +1.05V PCH CORE VCCST POWER MAINON S0
+VCCIN variation CPU CORE POWER VRON S0 EC

GPU FAN2_PWM GPU FAN
+VGPU_CORE variation External GPU POWER VGPU_EN S0 CORE PWR
+3V_GFX +3.3V External GPU POWER dGPU_PWR_EN S0
dGPU_OPP#
dGPU_OTP#
dGPU_ALT#
SM-Bus1
+1.5V_GFX +1.5V External GPU POWER FBVDDQ_EN S0
GPU_THAL#
+1.05V_GFX +1.05V External GPU POWER 1.05V_GFX_EN S0
GPIO12 HW throttle
over power protect
D GPIO12_ACIN D
dGPU

dGPU_OPP# EC notify HW throttle over power protect PROJECT : ZQX
dGPU_ALT# for ADPS circuit to infrom EC NV dGPU VPS Alert Size Document Number Rev
dGPU_OTP# VGA thrmtrip# => inform EC over temperature protect PWR Status & GPU PWR CRL & THRM 1B

1 2 3 4 5 6 7 8
5 4 3 2 1
Battery Mode
Support Deep Sx
3
+3VPCU
VIN 1
+5VPCU
VL
3 3
+3VPCU
5b
+3.3V_DSW
1
VIN BAT-V
40
3V_LDO 3V/5V 2
11 2 VR depend on A measure +3.3V_DSW
3 +5VPCU +5V_S5
+15V
result to implement EN CHARGER Battery
EN2
EN1
D
+3VPCU S5 PWR +3V_S5 10 4 for B test D
3
3
S5_ON 8 NBSWON# 5a DSW_ON +3VPCU or +3.3V_DSW
1 VIN Delay DSW power well 10ms DSW PWR

+3VCC_S5
PWR 6 DPWROK DPWROK
SUS PWR
DDR VDDQ +1.35V_SUS 18 BTN 13 RSMRST# +1.05V
RSMRST#
VR 7 14 SB_ACDC ASW PWR
DDR_VTTREF 19 EC ACPRESENT +3V_S5
30 DNBSWON#
15 PWRBTN#
HWPG SUSC# 16 SPI PWR
+DDR_VTT_RUN 23 SLP_S4# +V1.05DX_MODPHY
SUSB# 20 SLP_S3#
HSIO PWR
PCH_SUSACK# SUSACK +1.05V
HWPG_VDDR 24
PG PCH_SUSPWARN# SUSWRAN
PLL PWR
S5
S3
PCH_SLP_SUS# SLP_SUS# +1.05V

PCH
DDR_PG_CTRL APWROK CORE PWR
C
22 +3V C
31 EC_PWROK PCH_PWROK
MAINON
21 PCH_CLK SDIO PWR
35 +3V_S5
VRON
SUSON
S5_ON
MAINON
EC_PWROK
HWPG_1.05V_EC#
+0.75V_ON PLTRST#
+0.75V_ON
? PLTRST#
38 SYS_PWROK HDA PWR
SUSON SYS_PWROK
17 34 IMVP_PWRGD
+3VPCU 24 HWPG_VDDR
3 36
26 HWPG_1.05V 31 EC_PWROK 38
+1.5V 12 30a 31 32b 21 17 8
1.5V
PLTRST#
HWPG_1.5V
VR 29 29
HWPG_1.5V ?
PG
EN
+VCCIN
MAINON CORE PWR

21 +1.35V_SUS
RESET#
CPU
VDDQ PWR
+1.05V_VCCST
RUN PWR +1.05V
+1.05V_VCCST PROCPWRGD
B
3 +5VPCU +5V 28 VCCST PWR B
MOS1
SM_PG_CNTL1
VCCST_PWRGD
0 ohm
3 +3VPCU +3V 27
VR_READY
MOS2
VR_EN
10K ohm
SVID
+1.05V_S5 +1.05V
9 25
MOS3
G
HWPG_1.05V
1 VIN 12
MAINON
VRON_CPU
DDR_PG_CTRL
21
IMVP_PWRGD
VCCST_PWRGD_EN
SVID
33
+VCCIN EC_PWROK VCCST_PWRGD_EN
IMVP 31
VIN
1 9 VR
SYS_PWROK
+1.05V_S5 36
+1.05V_S5
VR 34
12 IMVP_PWRGD HWPG_1.05V_EC# 37 22 34 32a
HWPG_1.05V PG 30a
EN
PG
EN
A A
8 SVID VRON_CPU 32a HWPG+1ms

S5_ON
37 VRON 32b
PCH MAINON 21
CPU Quanta Computer Inc.
PROJECT : ZQX
1B
Power Sequence
5 4 3 2 1
5 4 3 2 1
實實實defult
虛實實reserve
SYS_HWPG S5D
MDV1528Q +5V_S5 41
2 VGPU_PWRGD
9
3V_LDO PWRGD
1 +5VPCU MDV1528Q +5V
D
PWR EN! PWRGD
D
S5_Vout
3V/5V MAIND
VIN Vin
VGPU Core Vout
+VGPU_CORE
4 uP1642
TPS51225
3V_LDO EN
1 EN2 VGPU_EN
Vin S3_Vout +3VPCU 7
AO3404 +3V_S5 PCH
VIN
S5D
2
HWPG_1.5VGFX
AO3404 +3V 10
MAIND PWRGD
4
VIN Vin
+1.5V_GFX Vout
TPS51211
+1.5V_GFX
EC_FB_CLAMP EN
C
AO3404 +3V_GFX EC OR Gate FBVDDQ_EN
C
VGPU_PWRGD
dGPU_PWR_EN 9
PCH
VGPU_EN
7
HWPG_1.05V
MDV1528Q +1.05V
PWRGD
VIN +1.05V_S5 MAIND

Vin Vout +1.05V_S5 4
TPS51211
IMVP_PWRGD
EN
S5_ON MDV1528Q +1.05V_GFX
2 EC PWRGD
HWPG_1.5VGFX
10 1.05V_GFX_EN VIN CPU VCCIN +VCCIN
B B
AND Gate Vin Vout
MAINON TPS51622
4 EC VGPU_PWRGD EN
9 VRON_CPU
VRON
HWPG_VDDR
HWPG_1.5V
SUSON PWRGD
3 EC S5 EN
+1.35V_SUS
S5_Vout
+1.35V_SUS DDR_VTTREF PWRGD
TPS51216
+3VPCU Vin
+1.5V Vout
DDR_VTTT_PG_CTRL TPS54318
+1.5V
PCH S3 EN EN
Vin S3_Vout +DDR_VTT_RUN
MAINON MAINON
A 4 A
+0.75V_ON
EC
VIN
PROJECT : ZQX
1B
ULT PWR CONTROL
5 4 3 2 1
5 4 3 2 1
Model Version CHANGE LIST

1A 1. Add TPM function. (page26)
ZQX 2. Modify Audio L/R connection. (page28)
3. Add 100k on MIC2-VREFO to AGND for FAE suggest (page22)
4. update CN31 footprint and PN (page29)
5. Add 0805 0 ohm on +1.35V_SUS. (page5)
6. Modify VCCST_PWRGD_EN connection. (page5)
7. Add LPCPD# for TPM function (page7)
8. Change SPI damping R fform 15 to 0 ohm (page8)
9. change USB2.0 mapping port (page9)
10. change GPIO0~7 mapping port (page10)
10/24 11. Add pull high res for GPIO pin (page10)
12. unmunt page13 debug item (page13)
13. Change +DDR_VTT_RUN res from 34.8 to 36 ohm
14. Change Q63 type (page19)
15. Reserve +3V for TP_PWR (page23)
16. Add 1.6P cap on USB3.0 for RF (page28)
17. reserver 0 ohm for Light_sensor I2C (page28)
D D
18. Modify M_A_CLK0,M_A_CLK1 connection. (page14)

19. Modify Block diagram (page1)
20. Change PC134,PC139 PN (page37)
21. Change TPM module to SLB9655 (page26)
10/25 22. Change G-sensor to BMA250E (page 29)
23. Add CN2 pin31 AGND
24. Add GPIO25 PU res (page10)
25. Change DGPU_SELECT# to PU10K (page2)
26. Modify BMA250E CSB pin for FAE suggestion. (page29)

27. Change USB3.0 mapping for WHCK (page9)
28. Change HDD conn type to FFC (page26)
10/28
29. Change C301,C9009 to 3.3p (page14)
30. Change Q5045 SW power to +3v (page29)
31. Modify LineL\R connection (page29)

10/29 32. Remove IOAC function (page24,page27,page30)
33. Add Mos for leakage (page27)
34. Change to LANCC and add PU res for FAE suggest (page24)
10/30 35. Change MDI0~MDI3 Res form 1 ohm to shortpad for FAE suggest (page24)
36. Swap GND and HP_JD# for FAE suggest (page28)
37. Add 10u Cap on +5v codec for FAE suggest (page22)
38. Modify USB port mapping (page10)
39. Swap DDR Data,DQS for layout request. (page14,15)

40. Swap Vram Data,DQS for layout request.(page21)
10/31 41. Add 100K on INT_AMIC-VREFO for FAE suggest (page22)
42. Reserve 0805 Res between +3V_MAIN and +3V_GFX for non GC6 function (page20)
43. SWAP PCH_SUSACK# and PCH_SUSPWARN# for EC request. (page30)
44. Change TP_INT_PCH port to GPIO83 (page10)
45. Add TPD_EN,TPD_INT# (page2,page29)
46. Modify EC GPIO pin, detail please see page30 mark (page30)
47. Mount PR183,unmount PR184 for power request (page37)
48. Change +1.35_SUS o ohm 0805 to1206
49. Add TP_RST# PU RES (page23)
50. Swap LSPK+,LSPK- 11/01 (page14,15)

51. Swap I2C port 0 and port1 (page10)
11/01 52. Swap USB2,3,7 +- for layout (page28)
53. Del TP_PWR 5V,Add pin31 connect to TP_PWR (page 23)
54 Change +3V to +WL_VDD Q5043 (page27)
55. Remove SMB_PCH_CLK and SMB_PCH_DAT (page30)
C 56. Reverse CN25 HDD(page26) C
57. Modify screw hole type (page29,31)

11/04 58. Swap Rin2,Sleeve,HPL_C,HPR_C (page28)
59. Modify surge sch follow ZQSA (page24)
60. Modify CN23 gnd and surge component PN.
61. Delete shortpad for layout 11/05 (page24)

11/05 62. Use MOS replace U40, +1.05V_MODPHY (page11)
63. Delete SW6 for ACER request No system power cut off mechanism.(page31)
64. Change CN6 PN for ME request (page26)

11/06 65. Add powe net name SP_PLLVDD (page18)
66. Add TP, update EC PN (page30)
67. Modify surge sch (page24)
68. Modify SMB_PCH_CLK/DAT for EC (page30)
69. Add sensor_INT (page10,30)
70. Chage pr164 to 1.47k for power request (page36)

11/07 71. Change Hole2 type (page29)
72. Use GPIO46 to be G-sen_INT (page10,29)
73. I2C0 connect to Sensor HUB,I2C1 connect touchpanle and touchpad for Acer request 11/08 (page10,30)
11/08 74. Modify on 11/08, add touchpad i2c PU RES(page29)
75. Change power cap 22u PN from CH6221M9A03 toCH6221M9A00
76. Reserve 0ohm on Sensor_PCH I2C (page10)
77. Change L45,L46,L47 PN for EOL issue (page30)

11/11 78. Change D25,D49 to RB500V-40 (page22)
79. Change L15,L19 to CX300T10000, L20 to CX5PX181000 For EOD issue( page15,page17)
80. Change power net 3V_MAIN_PWGD PL 100k for power request (page37)
81. Mount Q26,R227 unmount R226 for leakage issue (page19)
82. Change PC79,PC147,PC132 PN for EOD issue (page35,page37)
83. Change Hole7 type (page29)

11/12 84. Change L20 footprint (page18)
11/14 85. update power +VCCIN(TPS51624) sch (page35)

86. Swap net for layout request (DDR Dim,keyboard and usb filter) (page9,page15,page23)
87. Delete Hole10 (page29)
88. Add 0ohm between LAND and GND (page24)
89. Add 0.1u cap on VIn (page31)
90. Delete 2 pcs 0.1u cap on VIN (page31)
B
91. Rename. B
92. update titleblock; power description (page35)
11/15 93. Change power discription (page38)

94. Change PU4 PN for +1.5V_GFX for peak current to 4.3A(page38)
95. Change Rom PN to AKE3EFP0N07 (3.3V type) (page8)
96. Modify GC6 mount part (page17,19,20)

11/18 97. change PU4 PN to AL054318000 (page38)
A A
DOC NO.
PROJECT MODEL Quanta Computer Inc.
: ZQX APPROVED BY: DATE:
PROJECT : ZQX
1A
PART NUMBER: DRAWING BY: REVISON: Change list-1
5 4 3 2 1
5 4 3 2 1
Model Version CHANGE LIST
ZQX 1B
Change Item Reason for Change
1. Add HDD protect function. example : U7 (page28) 1. Reserve for HDD protect in machine rotate condition
2. Change Sensor board conn. (CN9) from 16 to 10 pin
Remove Gyro/Accelerometer & eCompass function (page27) 2. Remove sensors which aren't using on feature list
3. Add DEVSLP0_R & HDD protect to CN13.4 (page21) 3. Reserve for HDD protect in machine rotate condition
4. Add RTC charge circuit (page 8) 4. Cause of placement and PE requirement, ZQX need to use small size of RTC(1220)
5. Q13.2 connect change from +3V+S5 to +3V (page26) with charging circuit
6. Q44.2 & 5 connect change from +3V to +TPVDD (page28) 5. Remove IOAC function
7. R65 connect change from +3V to +3VPCU (page23) 6. Match touch pad support S5 power well
8. R22 connect change from +3V to +5V (page23) 7. Ite load code time to long, cause backlight has flicker when AC in.
9. Connect SWAP PCIE CLKOUT 2 & 3 (page28) 8. Touch screen voltgae change to 5V
D 10.TP_INT connect to CN7.5 & 6 (page23) 9. PCIE clock request mapping issue D
11. Add BLON pin (PCH_BLON_EC) to EC. (page23) 10. Reserve for touch screen interrupt control signal
12. Change GPU from 29*29 to 23*23 11. Fn+F6 function
Modify GPU circuit . 12. Acer feature change
Cahnge VRAM circuit.(page16 ~20)
2A 1. Add C583 C585 C586 C588 C589 C692 C693 C694 C695
Modify C8 from 0.1UF to 1000PF for EMI request
2. Change TPM circuit
Add. C584 C587 D35 R645 R646 R647 R649 R758 TP121 TP122 &
R648
Remove T28
3. Modify TP circuit
Add. L23
4. Change +3VSUS circuit
Add PQ66 PQ65 PQ64 PQ67 PR238 PR237 PR236 PR239 PR240 &
PC195
5. Add R644 for NV
6. R631 & R630 change from 56 to 47 ohm for vender request
2B 1. Add R651 & R645 for glitch of DDR_VTTT_PG_CTR

Modify C8 from 0.1UF to 1000PF for EMI request
2. Change TPM circuit
Add. C584 C587 D35 R645 R646 R647 R649 R758 TP121 TP122 &
R648
Remove T28
3. Modify TP circuit
Add. L23
4. Change +3VSUS circuit
Add PQ66 PQ65 PQ64 PQ67 PR238 PR237 PR236 PR239 PR240 &
PC195
5. Add R644 for NV
6. R631 & R630 change from 56 to 47 ohm for vender request
C C
B B
A A
DOC NO.
PROJECT MODEL Quanta Computer Inc.
: ZRQ APPROVED BY: DATE:
PROJECT : ZQX
1A
PART NUMBER: DRAWING BY: REVISON: Change list-2
Date: Thursday, September 04, 2014 Sheet 43 of 43
5 4 3 2 1

ZQX Ddr3 BDW Ult r1b 0903 Acer Aspire r3-471t

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ZQX Ddr3 BDW Ult r1b 0903 Acer Aspire r3-471t

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5 4 3 2 1

ZQX_DDR3 BDW ULT SYSTEM BLOCK DIAGRAM 01

MCP 1168pins PCI-E

Panel seosor board

Speaker*2 OCH1691WAD Image Sensor Fan Driver Gyro/eCompass/(Reserve)

Quanta Computer Inc.

SP@ : i3-4010U i3-4020U i5-4210U

[25] INT_HDMITX1N DDI1_TXN1 EDP_TXN1 EDP_TXN1 [23]

Change Data and DQS to interleave.

Quanta Computer Inc.

Date: Wednesday, September 03, 2014 Sheet 3 of 43

+1.05V_VCCST +1.05V_VCCST [5,10]

DRAM COMP XDP PU/PD DDR3L ODT GENERATION +1.35V_SUS

PU/PD of CPU DRAMRST

H_PROCHOT# R579 *62_4

CPU_DRAMRST# R217 *short_4 DDR3_DRAMRST# [14,15]

H_PWRGOOD_R R565 10K_4 C154

Size Document Number Rev

VDDQ Output Decoupling Recommendations

+3V VCCST PWRGD H_CPU_SVIDCLK R268 *short_4 VR_SVID_CLK [34]

VCCST_PW RGD R588 *short_4 VCCST_PW RGD_R 4 3

C535 *MMBT3904-7-F C534 Q40

*1000p/50V_4 *1000p/50V_4 *DTC144EU

Haswell ULT (CFG,RSVD)

B CFG3 DISABLED ENABLED B

CFG 8 DISABLED(DEFAULT); IN THIS CASE, NOA ENABLED; NOA WILL BE AVAILABLE

CFG9 NO VR SUPPORTING SVID IS PRESENT. THE CFG9 R560 *1K_4

CFG10 POWER FEATURES ACTIVATED POWER FEATURES (ESPECIALLY CLOCK

Quanta Computer Inc.

Haswell ULT PCH (PM)

SYSTEM POWER MANAGEMENT

EC_PWROK R606 *0_4 SYS_PWROK_R

PCH PM PU/PD PLTRST# Buffer Deep Sx Circuit Non Deep Sx

DPWROK_R R478 100K/F_4 TC7SH08FU R94 *0.33u/10V_6 *100K_4

+3V_S5 C561 *0.1u/10V_4 PCH_SLP_SUS# 2

PCH_ACPRESENT R165 10K_4 Q15

PCH_BATLOW# R505 8.2K_4 *2N7002K

R134 *10K_4 TC7SH08FU R616

Haswell ULT PCH (RTC/HDA/SATA/SPI) Haswell ULT PCH(LPC,SPI,SMBUS,C-LINK,THERMAL)

SMB_PCH_CLK 6 1 CLK_SCLK [13,14,15,26]

RTC Circuitry +3V_RTC_[0:2] +3V_RTC

[29] SPI_CS0#_UR_ME R415 *short_4 PCH_SPI_CS0# 1 8

MMBT3904 20K/F_4 R429 15_4 3 6 R425 15_4 PCH_SPI_CLK R97 R91

R576 IO2/WP# CLK Q14 *2.2K_4 *2.2K_4

68.1K/F_4 C436 C161 J7 5 R427 15_4 PCH_SPI_SI 5

ULT Strapping Table

C438 18p/50V_4 RTC_X2 0 = Default enable (iPD 20K)

0 = Default SPI (iPD 20K) [10] GPIO86

C450 *10p/50V_4 0 = Default enable w/o

[16] PEG_TX#1 C481 EV@0.22u/10V_4 R_PEG_TX#1 B23 DSW AR10

VGA WLAN LAN

[24] PCIE_RX3-_LAN PERN3 [26] CLK_PCIE_WLANP CLKOUT_PCIE_P3 CLKOUT_LPC_1 CLK_PCI_EC [29]

C491 0.1u/10V_4 PCIE_TX4- B29 USB3RP2 CLK_PCIE_REQ5# T2 CLKOUT_PCIE_P5

Swap for layou 11/14 CLK_PCIE_REQ4# R158 10K_4

+V1.05S_AUSB3PLL +V1.05S_AUSB3PLL [11]

Quanta Computer Inc.

PCH GPIO PU/PD

GPU power is control by PCH

Board ID RAM ID +3V_S5 CPU thermal trip

[2] BOARD_ID2 0001 GPIO24 R187 10K_4

+3V LAN_DISABLE# R209 10K_4

VCCAPLL power +1.05V +V1.05S_AXCK_DCB

C196 C184 C206

1000p/50V_4 1000p/50V_4 *DTC144EU

DPWROK_R R478 100K/F_4 TC7SH08FU R94 0.33u/10V_6 100K_4

R576 IO2/WP# CLK Q14 2.2K_4 2.2K_4

R172 1K_4 SPD_A2 R197 1K_4