Quanta FH2A Intel Calpella Arrandale REV 1A

1 2 3 4 5 6 7 8
Intel Calpella
Intel Calpella Arrandale 01
BlOCK DIAGRAM
FAN & THERMAL
A A
SYSTEM
POWER RESET CIRCUIT
gDDR3*4 gDDR3*4 CLOCK
AC/BATT BATT 512MB 512MB SLG8SP585VTR
CONNECTOR CHARGER (QFN-32)
RUN POWER SW 1600MHZ
+3V_S5/+5V_S5
+5V_SUS CPU CHA CHB
+5V_RUN/+3V_RUN/+1.8V_RUN
VGA HDMI
Arrandale 35W HDMI
PCIEx16
DDR3-SODIMM1 Option
CHA
37.5mm X 37.5mm <Madison LP(HD5650)> LVDS
Dual Channel DDR3 Panel Connector
1066 1.5V <M96 LP>
DDR3-SODIMM2 ( rPGA 989 ) VGA
B CRT CONN. B
CHB
FDI DMI X 4
USB conn x 3
SATA USB2.0 x 3
SATA-ODD PCH Card Reader SD MS CARD
RTS5159
SATA
82801IBM
SATA-HDD PCIEx1
(HM55) GLAN 10/100/1000 LAN
PCIEx1 Realtek RTL8111E-GR
27mm X 25mm
IHDA PCIEx1
MINI-CARD
C C
WLAN
AUDIO/AMP NEW CARD W83L351YG

ALC269
LPC SPI
SPK
Audio
conn Audio FLASH
Jacks EC 2Mbyts
ITE8502
18X8
Keyboard
SPI PS/2
FLASH Touchpad
D
2Mbyts D
Quanta Computer Inc.

PROJECT : FH2A
Size Document Number Rev
1A
BLOCK DIAGRAM
Date: Monday, July 26, 2010 Sheet 1 of 46
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Table of Contents
PAGE
01
02
DESCRIPTION
Schematic Block Diagram
Front Page ACIN
+3VPCU/+5VPCU
System Power Sequence
02
03 Clock Generator
04-07 Arrandale NBSWON#
08-13 Ibex Peak-M

14-15 DDRIII SO-DIMM(204P)
RVCC_ON
16-22 Madison T1
A 23 LCD/CCD ICH_RSMRST# A
T2
24 CRT/HDMI CONN DNBSWON#
25 Card Reader (RTS5159)

26 GLAN RTL8111E-GR/RJ45
27 HDD/ODD/HOLE SUSB#,SUSC#,SUSD#
28 USB/BLUE TOOTH
29 MINI-Card (WLAN) SUSON
30 KB/TOUCH PAD/LED
MAINON T3
31 CODEC (ALC269)
T5
32 EC_ ITE8502 MAINON2
33 FAN/SW/NEWCARD
+1.5VSUS/+3VSUS/+5VSUS
34 +5V/+3V (RT8206B)
35 +1.05V/ +1.8V (RT8204C) +1.5V_RUN/+1.8V_RUN
/+3V_RUN/+5V_RUN
36 CPU Core ( ADP3212)
37 +1.05V_VTT (VT358) +1.05V_PCH/+1.05V_VTT
/+0.75V_DDR_VTT
38 DIS_GFX_VCC (MAX8792)
39 DDR3 (RT8207)
HWPG
40 GFX_IO_VCC
41 DISCHARGE/3VS5/5VS5/LAN VRON
42 CHARGER (ISL88731)
B 43 Clock Distribution +VCC_CORE B
44 Power Tree
45 SMBUS Address VR_PWRGD_CLKEN# 3ms~20ms
46 Change History
IMVP_PWRGD
T4
System Power Sequence
MPWROK
T1: RVCCON TO RSMRST# = 30ms (spec:mini 10ms)
T2: RSMRST# TO-DNBSWON = 110ms (spec:mini 100ms)
T3: MAINON2 TO VRON = 110ms (spec:mini 99ms)
H_VTTPWRGD
T4: VRON TO MPWROK = 10ms (HWPG NEED TO BE HIGH at that time)
Note: IMVP_CLK_EN# (inverted) assertion to SYS_PWROK/PCH_PWROK assertion. DRAMPWROK
SPEC:3ms~20ms VCCPPWRGOOD
T5: MAINON to MAINON2 =500us PLTRST#

CPU_RST#
Madison VGA Power Sequence

M96 VGA Power Sequence
Note1:VDDR3 should ramp-up before or simultaneously with VDDC.
Note1:BBP must ramp up before or at the same time as VDDC but not after
Note2:For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18
Note2:1.8-V rails should ramp before the 3.3-V rails.
Note3:All the ASIC supplies must fully reach their respective nominal
Note3:VDDC must ramp before DPx_VDD10, DPx_VDD18 and DPx_PVDD.
voltages within 20 ms of the start of the ramp-up sequence.
C Note4:All the ASIC supplies must fully reach their respective nominal C
voltages within 20 ms of the start of the ramp-up sequence.
MadisonVGA Power Up/Down Sequence

MAINON
M96 VGA Power Up/Down Sequence
MAINON
DGPU_VRON
DGPU_VRON
+3V_GPU(VDDR3)
+VGPU_CORE(VDDC)
+VGPU_CORE(VDDC)
+1.5V_GPU
+1.5V_GPU
+1.1V_GPU(DPx_VDD10)
+1V_GPU(DPx_VDD10)
D D
+3V_GPU(VDDR3)

within 20ms within 20ms
within 20ms within 20ms
PROJECT : FH2A
1A
Frontpage
1 2 3 4 5 6 7 8
5 4 3 2 1
03
D D
+3V_RUN
L30 BLM21PG600SN1D 40mil +3.3V_CLK_VDD 1 VDD_USB CLK_BUF_BCLK_P

5 VDD_LCD CPU-0 23 CLK_BUF_BCLK_P (10)
17 22 CLK_BUF_BCLK_N
VDD_SRC CPU-0# CLK_BUF_BCLK_N (10)
C383 C344 C343 C366 C368 C352 +VDDIO_CLK 24 VDD_CPU
29 20
10U/10V_8 0.1U/16V_4 0.1U/16V_4 0.1U/16V_4 0.1U/16V_4 0.1U/16V_4 15
18
VDD_REF
VDD_SRC_IO CK505 CPU-1
CPU-1# 19
VDD_CPU_IO
9 VSS_SATA
QFN32 DOT96T_LPR 3 CLK_BUF_DREFCLKP
CLK_BUF_DREFCLKP (10)
0.1uF near the every power pin. 2 4 CLK_BUF_DREFCLKN
VSS_USB DOT96C_LPR CLK_BUF_DREFCLKN (10)
8 VSS_LCD
12 13 CLK_BUF_PCIE_3GPLLP
VSS_SRC SRC-2 CLK_BUF_PCIE_3GPLLP (10)
21 14 CLK_BUF_PCIE_3GPLLN
VSS_CPU SRC-2# CLK_BUF_PCIE_3GPLLN (10)
26 VSS_REF
10 CLK_BUF_DREFSSCLKP
SRC-1/SATA CLK_BUF_DREFSSCLKP (10)
11 CLK_BUF_DREFSSCLKN
SRC-1#/SATA# CLK_BUF_DREFSSCLKN (10)
+3V_RUN E-01
C C
R207 10K/J_4 16 6 CLK_27M_NONSS R199 *0_4_SHORT
CPU_STOP# 27MHz_nonSS CLK_VGA_27M_NONSS (17)
CK_PWRGD_R 25 7 CLK_27M_SS R198 *33/F_4
CK_PWRGD/PD#_3.3 27MHz_SS CLK_VGA_27M_SS (17)
CLK_PCH_14M R202 33/J_4 CPU_SEL 30
(10) CLK_PCH_14M REF_0/CPU_SEL
C346 XTAL_OUT 27
XTAL_IN XOUT
*10P/50V_4 28 XIN
EMI 31 33
(10,14,15) CGDAT_SMB SDATA GND
(10,14,15) CGCLK_SMB 32 SCLK
SLG8SP585VTR U12
C334 C335 Realtek: 0.1uFx3pcs, 22uFx1pcs
*33P/50V_4 *33P/50V_4 IDT: 0.1uFx2pcs, 10uFx1pcs
+3V_RUN +VDDIO_CLK
Place the 33 ohm
resistors close to the CK 505
Y2 L31 BLM21PG600SN1D
XTAL_IN 1 2 XTAL_OUT R212 *0/J_8 40mil
805
B 14.318MHZ +1.05V_PCH C384 C362 C367 B
2
C363
C360 33P/50V_4 10U/10V_8 0.1U/16V_4 0.1U/16V_4
+3V_S5 33P/50V_4 R223 *short_8
1
HP: 10u x2pcs

C382 SLG,IDT: +1.05V Place each 0.1uF cap as close as
0.1U/16V_4 Realtek: +3.3V possible to each VDD IO pin. Place
5
the 10uF caps on the VDD_IO plane.

(36) VR_PWRGD_CLKEN# 2 4 R213 CK_PWRGD_R
*0_4_SHORT
U13 +VDDIO_CLK:
TC7SZ04FU(T5L,F,T) SLG date sheet (V0.2) P15: Min 1.05V,Max3.465V.
3
Realtek date sheet(V1.2) P11: Min 1.05V,Max 3.3V.

IDT date sheet(V0.7) P10: Min 0.9975V,Max 3.465V.
+3V_RUN
CPU_SEL:
2
PIN 30 CPU_0 CPU_1 SLG date sheet (V0.2) P15:

R201
*4.7K/J_4
High Voltage: Min 0.7V, Max 1.5V.
A 0(default) 133MHz 133MHz Low Voltage: Min Vss-0.3V, Max 0.35V. A
Realtek date sheet(V1.2) P11:
1
CPU_SEL
High Voltage: Min 0.7V, Max 1.5V.
1(0.7V-1.5V) 100MHz 100MHz Low Voltage: Min Vss-0.3V, Max 0.35V.
2
R200 IDT date sheet(V0.7) P10: Quanta Computer Inc.

4.7K/J_4 C345 High Voltage: Min 0.7V, Max 1.5V.
*10P/50V_4 Low Voltage: Min Vss-0.3V, Max 0.35V. PROJECT : FH2A
1
EMI Capacitor Size Document Number Rev

1A
Clock Generator
5 4 3 2 1
5 4 3 2 1
04
U30A
PEG_ICOMPI B26 PEG_ICOMPI R383 49.9/F_4 U30B
A26 H_COMP3 AT23
PEG_ICOMPO COMP3
(8) DMI_TXN0 A24 DMI_RX#[0] PEG_RCOMPO B27 BCLK A16 CLK_CPU_BCLKP (11)
MISC
C23 A25 R385 750/F_4 H_COMP2 AT24 B16 CLK_CPU_BCLKN (11)
D (8) DMI_TXN1 DMI_RX#[1] PEG_RBIAS COMP2 BCLK# D
(8) DMI_TXN2 B22 DMI_RX#[2] PEG_RX#[0..15] (16)
CLOCKS
A21 K35 PEG_RX#15 H_COMP1 G16 AR30 CLK_BCLK_ITPP
(8) DMI_TXN3 DMI_RX#[3] PEG_RX#[0] COMP1 BCLK_ITP T28
J34 PEG_RX#14 AT30 CLK_BCLK_ITPN
PEG_RX#[1] BCLK_ITP# T27
B24 J33 PEG_RX#13 H_COMP0 AT26
(8) DMI_TXP0 DMI_RX[0] PEG_RX#[2] COMP0
D23 G35 PEG_RX#12 E16 CLK_PCIE_3GPLLP (10)
(8) DMI_TXP1 DMI_RX[1] PEG_RX#[3] PEG_CLK
DMI
B23 G32 PEG_RX#11 D16 CLK_PCIE_3GPLLN (10)
(8) DMI_TXP2 DMI_RX[2] PEG_RX#[4] PEG_CLK#
A22 F34 PEG_RX#10 T46 TP_SKT0CC# AH24
(8) DMI_TXP3 DMI_RX[3] PEG_RX#[5] SKTOCC#
F31 PEG_RX#9 A18
PEG_RX#[6] PEG_RX#8 DPLL_REF_SSCLK
(8) DMI_RXN0 D24 DMI_TX#[0] PEG_RX#[7] D35 DPLL_REF_SSCLK# A17
G24 E33 PEG_RX#7 H_CATERR# AK14
(8) DMI_RXN1 DMI_TX#[1] PEG_RX#[8] CATERR#
THERMAL
F23 C33 PEG_RX#6
(8) DMI_RXN2 DMI_TX#[2] PEG_RX#[9]
H23 D32 PEG_RX#5
(8) DMI_RXN3 DMI_TX#[3] PEG_RX#[10]
B32 PEG_RX#4 F6 DDR3_DRAMRST#_C for S3 power reduction
PEG_RX#[11] PEG_RX#3 R397 0/J_S H_PECI_ISO AT15 SM_DRAMRST#
(8) DMI_RXP0 D25 DMI_TX[0] PEG_RX#[12] C31 (11) H_PECI PECI
F24 B28 PEG_RX#2 AL1 SM_RCOMP_0
(8) DMI_RXP1 DMI_TX[1] PEG_RX#[13] SM_RCOMP[0]
E23 B30 PEG_RX#1 AM1 SM_RCOMP_1
G23 A31 PEG_RX#0 AN1 SM_RCOMP_2 +1.05V_VTT
PEG_RX[0..15] (16) (36) H_PROCHOT#_D H_PROCHOT#_D AN26
PEG_RX15 PROCHOT# R181 2
PEG_RX[0] J35 PM_EXT_TS#[0] AN15 1 10K/J_4
DDR3
MISC
H34 PEG_RX14 AP15 R185 2 1 10K/J_4
PEG_RX[1] PEG_RX13 PM_EXT_TS#[1] SR189 *0_4_SHORT
PEG_RX[2] H33 PM_EXTTS#0 (14)
E22 F35 PEG_RX12 (11) H_THERM H_THERM R140 0/J_S AK15 R195 *0_4_SHORT PM_EXTTS#1 (15)
FDI_TX#[0] PEG_RX[3] PEG_RX11 THERMTRIP#
D21 FDI_TX#[1] PEG_RX[4] G33
D19 E34 PEG_RX10
FDI_TX#[2] PEG_RX[5] PEG_RX9 XDP_PRDY# T84
D18 FDI_TX#[3] PEG_RX[6] F32 PRDY# AT28
G21 D34 PEG_RX8 AP27 XDP_PREQ# T51 R184
FDI_TX#[4] PEG_RX[7] PEG_RX7 PREQ#
PCI EXPRESS -- GRAPHICS
E19 F33 *12.4K/F_4
FDI_TX#[5] PEG_RX[8] PEG_RX6 XDP_TCLK
F21 FDI_TX#[6] PEG_RX[9] B33 TCK AN28
Intel(R) FDI
G18 D31 PEG_RX5 H_CPURST# AP26 AP28 XDP_TMS T34

FDI_TX#[7] PEG_RX[10] T45 RESET_OBS# TMS
PWR MANAGEMENT
A32 PEG_RX4 AT27 XDP_TRST# T83
PEG_RX[11] TRST#
JTAG & BPM

C30 PEG_RX3
PEG_RX[12] PEG_RX2 XDP_TDI_R T49
D22 FDI_TX[0] PEG_RX[13] A28 (8) PM_SYNC AL15 PM_SYNC TDI AT29
C21 B29 PEG_RX1 AR27 XDP_TDO_R T42
FDI_TX[1] PEG_RX[14] PEG_RX0 TDO XDP_TDI_M
D20 FDI_TX[2] PEG_RX[15] A30 TDI_M AR29
C C18 AN14 AP29 XDP_TDO_M C
FDI_TX[3] PEG_TX#[0..15] (16) VCCPWRGOOD_1 TDO_M
G22 L33 C_PEG_TX15 C561 0.1U/10V_4 PEG_TX15
FDI_TX[4] PEG_TX#[0] C_PEG_TX14 C559 0.1U/10V_4 PEG_TX14 H_DBR#_R R124 *0_4_SHORT
E20 FDI_TX[5] PEG_TX#[1] M35 DBR# AN25 XDP_DBRESET# (8)
F20 M33 C_PEG_TX13 C553 0.1U/10V_4 PEG_TX13 (11) H_PWRGOOD AN27
FDI_TX[6] PEG_TX#[2] C_PEG_TX12 C547 0.1U/10V_4 PEG_TX12 VCCPWRGOOD_0
G19 FDI_TX[7] PEG_TX#[3] M30
L31 C_PEG_TX11 C551 0.1U/10V_4 PEG_TX11 AJ22 XDP_OBS0_R
PEG_TX#[4] BPM#[0] T25
F17 K32 C_PEG_TX10 C543 0.1U/10V_4 PEG_TX10 PM_DRAM_PWRGD AK13 AK22 XDP_OBS1_R
FDI_FSYNC[0] PEG_TX#[5] (8) PM_DRAM_PWRGD SM_DRAMPWROK BPM#[1] T85
E17 M29 C_PEG_TX9 C549 0.1U/10V_4 PEG_TX9 AK24 XDP_OBS2_R
FDI_FSYNC[1] PEG_TX#[6] BPM#[2] T33
J31 C_PEG_TX8 C575 0.1U/10V_4 PEG_TX8 AJ24 XDP_OBS3_R
C17 K29 C_PEG_TX7 C555 0.1U/10V_4 PEG_TX7 H_VTTPWRGD AM15 AJ25 XDP_OBS4_R
FDI_INT PEG_TX#[8] VTTPWRGOOD BPM#[4] T29
H30 C_PEG_TX6 C574 0.1U/10V_4 PEG_TX6 AH22 XDP_OBS5_R
F18 H29 C_PEG_TX5 C569 0.1U/10V_4 PEG_TX5 AK23 XDP_OBS6_R
FDI_LSYNC[0] PEG_TX#[10] BPM#[6] T30
D17 F29 C_PEG_TX4 C578 0.1U/10V_4 PEG_TX4 H_PWRGD_XDP AM26 AH23 XDP_OBS7_R
FDI_LSYNC[1] PEG_TX#[11] T37 TAPPWRGOOD BPM#[7] T32
E28 C_PEG_TX3 C576 0.1U/10V_4 PEG_TX3
PEG_TX#[12] C_PEG_TX2 C582 0.1U/10V_4 PEG_TX2
PEG_TX#[13] D29
D27 C_PEG_TX1 C589 0.1U/10V_4 PEG_TX1 R186 1.5K/F_4 AL14
PEG_TX#[14] C_PEG_TX0 C586 0.1U/10V_4 PEG_TX0 (10,16,25,26,29,33) PLTRST# RSTIN#
PEG_TX#[15] C26
R131 R392 PEG_TX[0..15] (16) XDP_TDI_R R117 *0_4_SHORT
T41
1K/F_4 1K/F_4 L34 C_PEG_TX#15C562 0.1U/10V_4 PEG_TX#15 R182
PEG_TX[0] C_PEG_TX#14C560 0.1U/10V_4 PEG_TX#14 Clarksfield/Auburndale XDP_TDO_M
PEG_TX[1] M34 750/F_4 T52
M32 C_PEG_TX#13C554 0.1U/10V_4 PEG_TX#13 R123 *0/J_4
PEG_TX[2] C_PEG_TX#12C548 0.1U/10V_4 PEG_TX#12
PEG_TX[3] L30
M31 C_PEG_TX#11C552 0.1U/10V_4 PEG_TX#11 R122 +1.05V_VTT XDP_TRST#
PEG_TX[4] C_PEG_TX#10C544 0.1U/10V_4 PEG_TX#10
PEG_TX[5] K31 *0_4_SHORT
M28 C_PEG_TX#9 C546 0.1U/10V_4 PEG_TX#9 R388
PEG_TX[6]
B
H31 C_PEG_TX#8 C571 0.1U/10V_4 PEG_TX#8 51/J_4
PEG_TX[7] C_PEG_TX#7 C550 0.1U/10V_4 PEG_TX#7 XDP_TDI_M
PEG_TX[8] K28
C_PEG_TX#6 C570 0.1U/10V_4 PEG_TX#6 R118 *0/J_4
PEG_TX[9] G30
G29 C_PEG_TX#5 C557 0.1U/10V_4 PEG_TX#5 CPU THERMTRIP +1.05V_VTT XDP_TDO_R R128 *0_4_SHORT
PEG_TX[10] C_PEG_TX#4 C577 0.1U/10V_4 PEG_TX#4 R401 R127 51/J_4
PEG_TX[11] F28
E27 C_PEG_TX#3 C573 0.1U/10V_4 PEG_TX#3 (32,34,38) HWPG HWPG H_VTTPWRGD
PEG_TX[12]
3
D28 C_PEG_TX#2 C579 0.1U/10V_4 PEG_TX#2 2K/F_4
PEG_TX[13] C_PEG_TX#1 C588 0.1U/10V_4 PEG_TX#1 Q4
PEG_TX[14] C27
C25 C_PEG_TX#0 C584 0.1U/10V_4 PEG_TX#0 R399 For S3 power reduction
B PEG_TX[15] 1K/F_4 B
(8,36) IMVP_PWRGD 2
+1.5V_SUS
Clarksfield/Auburndale *2N7002E R459 *0/J_4
1
R171 *100K/J_4 2N7002W-7-F R461
Q16 1K/F_4
DDR3_DRAMRST#_C 1 3 DDR3_DRAMRST# (14,15)
R170
*1K/J_4 C632
100P/50V/NPO
2
R458
2
100K/J_4
Q3
H_THERM H_THERM_R R453 *0/J_4
Processor Pullups Processor Compensation Signals R159 *33/J_4
1 3
*MMBT3904
SYS_SHDN# (34) DDR3_CORL_EC (32)
DDR3 Compensation Signals
3
R444 *0_4_SHORT DDR3_CORL_PCH (11)
+1.05V_VTT R411 *4.7K_42 Q14
(17) TEMP_FAIL
*MMBT3904
H_COMP0 SM_RCOMP_2 +1.5V_RUN
1
C630
H_COMP1 SM_RCOMP_1 0.1U/10V_4
H_COMP2 SM_RCOMP_0 PM_THRMTRIP# STUP AS SHORT AS PASSPBLE

R143 R129 R133 R406
49.9/F_4 68/F_4 *68/J_4 H_COMP3 *1.1K/F_4
CPU THERM SENSOR PM_DRAM_PWRGD R404 1.5K/F_4 HWPG
H_CATERR# R183 R190 R188
R390 R135 R393 R396 130/F_4 24.9/F_4 100/F_4 +3V_RUN
H_PROCHOT#_D 49.9/F_4 49.9/F_4 20/F_4 20/F_4
U9 R407
H_CPURST# 4 5SYS_SHDN_1# SYS_SHDN# 750/F_4
VDD OS R139 *0/J_4
A 1 A
R136 CTRL
C283 *0_4 2 3
*0.1U/10V_4 GND Vtemp
*BDE0900G
T50 +1.05V_VTT
R134
XDP_TMS R126 *51/J_4
XDP_TDI_R R125 *51/J_4 *0_4 Quanta Computer Inc.
XDP_PREQ# R130 *51/J_4
XDP_TCLK R116 *51/J_4
T35 PROJECT : FH2A
1A
ARRANDALE 1/4
5 4 3 2 1
5 4 3 2 1
U30C
ARRANDALE PROCESSOR (DDR3)
U30D
05
(15) M_B_DQ[63:0] SB_CK[0] W8 M_B_CLKP0 (15)
SA_CK[0] AA6 M_A_CLKP0 (14) SB_CK#[0] W9 M_B_CLKN0 (15)
AA7 M_A_CLKN0 (14) M_B_DQ0 B5 M3 M_B_CKE0 (15)
D SA_CK#[0] M_B_DQ1 SB_DQ[0] SB_CKE[0] D
(14) M_A_DQ[63:0] SA_CKE[0] P7 M_A_CKE0 (14) A5 SB_DQ[1]
M_A_DQ0 A10 M_B_DQ2 C3
M_A_DQ1 SA_DQ[0] M_B_DQ3 SB_DQ[2]
C10 SA_DQ[1] B3 SB_DQ[3] SB_CK[1] V7 M_B_CLKP1 (15)
M_A_DQ2 C7 M_B_DQ4 E4 V6 M_B_CLKN1 (15)
M_A_DQ3 SA_DQ[2] M_B_DQ5 SB_DQ[4] SB_CK#[1]
A7 SA_DQ[3] SA_CK[1] Y6 M_A_CLKP1 (14) A6 SB_DQ[5] SB_CKE[1] M2 M_B_CKE1 (15)
M_A_DQ4 B10 Y5 M_A_CLKN1 (14) M_B_DQ6 A4
M_A_DQ5 SA_DQ[4] SA_CK#[1] M_B_DQ7 SB_DQ[6]
D10 SA_DQ[5] SA_CKE[1] P6 M_A_CKE1 (14) C4 SB_DQ[7]
M_A_DQ6 E10 M_B_DQ8 D1
A8 SA_DQ[7] D2 SB_DQ[9]
M_A_DQ8 D8 M_B_DQ10 F2 AB8 M_B_CS0# (15)
M_A_DQ9 SA_DQ[8] M_B_DQ11 SB_DQ[10] SB_CS#[0]
F10 SA_DQ[9] SA_CS#[0] AE2 M_A_CS0# (14) F1 SB_DQ[11] SB_CS#[1] AD6 M_B_CS1# (15)
M_A_DQ10 E6 AE8 M_A_CS1# (14) M_B_DQ12 C2
M_A_DQ11 SA_DQ[10] SA_CS#[1] M_B_DQ13 SB_DQ[12]
F7 SA_DQ[11] F5 SB_DQ[13]
M_A_DQ12 E9 M_B_DQ14 F3
B7 SA_DQ[13] G4 SB_DQ[15] SB_ODT[0] AC7 M_B_ODT0 (15)
M_A_DQ14 E7 AD8 M_A_ODT0 (14) M_B_DQ16 H6 AD1 M_B_ODT1 (15)
M_A_DQ15 SA_DQ[14] SA_ODT[0] M_B_DQ17 SB_DQ[16] SB_ODT[1]
C6 SA_DQ[15] SA_ODT[1] AF9 M_A_ODT1 (14) G2 SB_DQ[17]
M_A_DQ16 H10 M_B_DQ18 J6
G8 SA_DQ[17] J3 SB_DQ[19]
M_A_DQ18 K7 M_B_DQ20 G1 M_B_DM[7:0] (15)
M_A_DQ19 SA_DQ[18] M_B_DQ21 SB_DQ[20] M_B_DM0
J8 SA_DQ[19] G5 SB_DQ[21] SB_DM[0] D4
M_A_DQ20 G7 M_B_DQ22 J2 E1 M_B_DM1
M_A_DQ21 SA_DQ[20] M_B_DQ23 SB_DQ[22] SB_DM[1] M_B_DM2
G10 SA_DQ[21] M_A_DM[7:0] (14) J1 SB_DQ[23] SB_DM[2] H3
M_A_DQ22 J7 B9 M_A_DM0 M_B_DQ24 J5 K1 M_B_DM3
M_A_DQ23 SA_DQ[22] SA_DM[0] M_A_DM1 M_B_DQ25 SB_DQ[24] SB_DM[3] M_B_DM4
J10 SA_DQ[23] SA_DM[1] D7 K2 SB_DQ[25] SB_DM[4] AH1
M_A_DQ24 L7 H7 M_A_DM2 M_B_DQ26 L3 AL2 M_B_DM5
M_A_DQ25 SA_DQ[24] SA_DM[2] M_A_DM3 M_B_DQ27 SB_DQ[26] SB_DM[5] M_B_DM6
M6 SA_DQ[25] SA_DM[3] M7 M1 SB_DQ[27] SB_DM[6] AR4
M_A_DQ26 M8 AG6 M_A_DM4 M_B_DQ28 K5 AT8 M_B_DM7
M_A_DQ27 SA_DQ[26] SA_DM[4] M_A_DM5 M_B_DQ29 SB_DQ[28] SB_DM[7]
L9 SA_DQ[27] SA_DM[5] AM7 K4 SB_DQ[29]
C M_A_DQ28 L6 AN10 M_A_DM6 M_B_DQ30 M4 C
M_A_DQ29 SA_DQ[28] SA_DM[6] M_A_DM7 M_B_DQ31 SB_DQ[30]
K8 SA_DQ[29] SA_DM[7] AN13 N5 SB_DQ[31]
M_A_DQ30 N8 M_B_DQ32 AF3
P9 SA_DQ[31] AG1 SB_DQ[33] M_B_DQSN[7:0] (15)
M_A_DQ32 AH5 M_B_DQ34 AJ3 D5 M_B_DQSN0
M_A_DQ33 SA_DQ[32] M_B_DQ35 SB_DQ[34] SB_DQS#[0] M_B_DQSN1
AF5 SA_DQ[33] M_A_DQSN[7:0] (14) AK1 SB_DQ[35] SB_DQS#[1] F4
M_A_DQ34 AK6 C9 M_A_DQSN0 M_B_DQ36 AG4 J4 M_B_DQSN2
DDR SYSTEM MEMORY A
M_A_DQ35 SA_DQ[34] SA_DQS#[0] M_A_DQSN1 M_B_DQ37 SB_DQ[36] SB_DQS#[2] M_B_DQSN3

AK7 SA_DQ[35] SA_DQS#[1] F8 AG3 SB_DQ[37] SB_DQS#[3] L4
M_A_DQ36 AF6 J9 M_A_DQSN2 M_B_DQ38 AJ4 AH2 M_B_DQSN4
SA_DQ[36] SA_DQS#[2] SB_DQ[38] SB_DQS#[4]
DDR SYSTEM MEMORY - B

M_A_DQ37 AG5 N9 M_A_DQSN3 M_B_DQ39 AH4 AL4 M_B_DQSN5
M_A_DQ38 SA_DQ[37] SA_DQS#[3] M_A_DQSN4 M_B_DQ40 SB_DQ[39] SB_DQS#[5] M_B_DQSN6
AJ7 SA_DQ[38] SA_DQS#[4] AH7 AK3 SB_DQ[40] SB_DQS#[6] AR5
M_A_DQ39 AJ6 AK9 M_A_DQSN5 M_B_DQ41 AK4 AR8 M_B_DQSN7
M_A_DQ40 SA_DQ[39] SA_DQS#[5] M_A_DQSN6 M_B_DQ42 SB_DQ[41] SB_DQS#[7]
AJ10 SA_DQ[40] SA_DQS#[6] AP11 AM6 SB_DQ[42]
M_A_DQ41 AJ9 AT13 M_A_DQSN7 M_B_DQ43 AN2
M_A_DQ42 SA_DQ[41] SA_DQS#[7] M_B_DQ44 SB_DQ[43]
AL10 SA_DQ[42] AK5 SB_DQ[44]
M_A_DQ43 AK12 M_B_DQ45 AK2
AK8 SA_DQ[44] AM4 SB_DQ[46]
M_A_DQ45 AL7 M_B_DQ47 AM3
SA_DQ[45] M_A_DQSP[7:0] (14) SB_DQ[47] M_B_DQSP[7:0] (15)
M_A_DQ46 AK11 C8 M_A_DQSP0 M_B_DQ48 AP3 C5 M_B_DQSP0
M_A_DQ47 SA_DQ[46] SA_DQS[0] M_A_DQSP1 M_B_DQ49 SB_DQ[48] SB_DQS[0] M_B_DQSP1
AL8 SA_DQ[47] SA_DQS[1] F9 AN5 SB_DQ[49] SB_DQS[1] E3
M_A_DQ48 AN8 H9 M_A_DQSP2 M_B_DQ50 AT4 H4 M_B_DQSP2
AM10 SA_DQ[49] SA_DQS[3] M9 AN6 SB_DQ[51] SB_DQS[3] M5
M_A_DQ50 AR11 AH8 M_A_DQSP4 M_B_DQ52 AN4 AG2 M_B_DQSP4
AL11 SA_DQ[51] SA_DQS[5] AK10 AN3 SB_DQ[53] SB_DQS[5] AL5
M_A_DQ52 AM9 AN11 M_A_DQSP6 M_B_DQ54 AT5 AP5 M_B_DQSP6
AN9 SA_DQ[53] SA_DQS[7] AR13 AT6 SB_DQ[55] SB_DQS[7] AR7
M_A_DQ54 AT11 M_B_DQ56 AN7
AP12 SA_DQ[55] AP6 SB_DQ[57]
M_A_DQ56 AM12 M_B_DQ58 AP8
B
AN12 SA_DQ[57] M_A_A[15:0] (14) AT9 SB_DQ[59] B
M_A_DQ58 AM13 Y3 M_A_A0 M_B_DQ60 AT7
M_A_DQ59 SA_DQ[58] SA_MA[0] M_A_A1 M_B_DQ61 SB_DQ[60]
AT14 SA_DQ[59] SA_MA[1] W1 AP9 SB_DQ[61]
M_A_DQ60 AT12 AA8 M_A_A2 M_B_DQ62 AR10 M_B_A[15:0] (15)
M_A_DQ61 SA_DQ[60] SA_MA[2] M_A_A3 M_B_DQ63 SB_DQ[62] M_B_A0
AL13 SA_DQ[61] SA_MA[3] AA3 AT10 SB_DQ[63] SB_MA[0] U5
M_A_DQ62 AR14 V1 M_A_A4 V2 M_B_A1
M_A_DQ63 SA_DQ[62] SA_MA[4] M_A_A5 SB_MA[1] M_B_A2
AP14 SA_DQ[63] SA_MA[5] AA9 SB_MA[2] T5
V8 M_A_A6 V3 M_B_A3
SA_MA[6] M_A_A7 SB_MA[3] M_B_A4
SA_MA[7] T1 SB_MA[4] R1
Y9 M_A_A8 (15) M_B_BS0 AB1 T8 M_B_A5
SA_MA[8] M_A_A9 SB_BS[0] SB_MA[5] M_B_A6
(14) M_A_BS0 AC3 SA_BS[0] SA_MA[9] U6 (15) M_B_BS1 W5 SB_BS[1] SB_MA[6] R2
(14) M_A_BS1 AB2 AD4 M_A_A10 (15) M_B_BS2 R7 R6 M_B_A7
SA_BS[1] SA_MA[10] M_A_A11 SB_BS[2] SB_MA[7] M_B_A8
(14) M_A_BS2 U7 SA_BS[2] SA_MA[11] T2 SB_MA[8] R4
U3 M_A_A12 R5 M_B_A9
SA_MA[12] M_A_A13 SB_MA[9] M_B_A10
SA_MA[13] AG8 (15) M_B_CAS# AC5 SB_CAS# SB_MA[10] AB5
T3 M_A_A14 (15) M_B_RAS# Y7 P3 M_B_A11
SA_MA[14] M_A_A15 SB_RAS# SB_MA[11] M_B_A12
(14) M_A_CAS# AE1 SA_CAS# SA_MA[15] V9 (15) M_B_WE# AC6 SB_WE# SB_MA[12] R3
(14) M_A_RAS# AB3 AF7 M_B_A13
SA_RAS# SB_MA[13] M_B_A14
(14) M_A_WE# AE9 SA_WE# SB_MA[14] P5
N1 M_B_A15
SB_MA[15]
Clarksfield/Auburndale
A DGG^9000005 A
Channel A DQ[15,32,48,54], DM[5] Clarksfield/Auburndale
Requires minimum 12mils spacing
DGG^9000005
with all other signals, including data signals.
Channel B DQ[16,18,36,42,56,57,60,61,62]
Requires minimum 12mils spacing Quanta Computer Inc.
with all other signals, including data signals.
PROJECT : FH2A
1A
ARRANDALE 2/4
5 4 3 2 1
5 4 3 2 1
CPU Core Power

+VCC_CORE=4.8 max
+VCC_CORE
U30F
+1.05V_VTT=1.8 max +1.05V_VTT

ARRANDALE PROCESSOR (GRAPHICS POWER) 06
AG35 AH14 U30G
VCC1 VTT0_1
AG34 VCC2 VTT0_2 AH12
AG33 VCC3 VTT0_3 AH11 AT21 VAXG1
AG32 AH10 C614 C311 C313 C616 C608 AT19 AR22
VCC4 VTT0_4 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 *10U/6.3V_8 *10U/6.3V_8 VAXG2 VAXG_SENSE
SENSE
LINES
AG31 VCC5 VTT0_5 J14 AT18 VAXG3 VSSAXG_SENSE AT22
AG30 VCC6 VTT0_6 J13 AT16 VAXG4
D AG29 H14 AR21 D
VCC7 VTT0_7 VAXG5
AG28 VCC8 VTT0_8 H12 AR19 VAXG6
AG27 VCC9 VTT0_9 G14 AR18 VAXG7
AG26 VCC10 VTT0_10 G13 AR16 VAXG8 GFX_VID[0] AM22
AF35 VCC11 VTT0_11 G12 AP21 VAXG9 GFX_VID[1] AP22
GRAPHICS VIDs
AF34 G11 C310 C275 C618 C607 AP19 AN22
VCC12 VTT0_12 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 VAXG10 GFX_VID[2]
AF33 VCC13 VTT0_13 F14 AP18 VAXG11 GFX_VID[3] AP23
AF32 VCC14 VTT0_14 F13 AP16 VAXG12 GFX_VID[4] AM23
AF31 VCC15 VTT0_15 F12 AN21 VAXG13 GFX_VID[5] AP24
GRAPHICS
AF30 VCC16 VTT0_16 F11 AN19 VAXG14 GFX_VID[6] AN24
AF29 VCC17 VTT0_17 E14 AN18 VAXG15 For S3 power reduction
AF28 VCC18 VTT0_18 E12 AN16 VAXG16
AF27 VCC19 VTT0_19 D14 AM21 VAXG17 GFX_VR_EN AR25 Check to ensure that 4 stitching caps per SODIMM
AF26 VCC20 VTT0_20 D13 AM19 VAXG18 GFX_DPRSLPVR AT25 connector between SODIMM 1.5V and GND are placed as
1.1V RAIL POWER

AD35 D12 +1.05V_VTT AM18 AM24 R106 1K/F_4
AD34
VCC21 VTT0_21
D11 AM16
VAXG19 GFX_IMON close as possible to the connectors – caps should be
VCC22 VTT0_22 VAXG20 evenly distributed between the connectors
AD33 VCC23 VTT0_23 C14 AL21 VAXG21
AD30 C11 C292 C619 C602 AL16
VCC26 VTT0_26 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 VAXG24
AD29 VCC27 VTT0_27 B14 AK21 VAXG25 VDDQ1 AJ1 +1.5V_RUN
AD28 VCC28 VTT0_28 B12 AK19 VAXG26 VDDQ2 AF1
- 1.5V RAILS
AD27 VCC29 VTT0_29 A14 AK18 VAXG27 VDDQ3 AE7
AD26 A13 AK16 AE4 C342 C338 C339 C340 C341
VCC30 VTT0_30 VAXG28 VDDQ4 1U/6.3V_4 1U/6.3V_41U/6.3V_41U/6.3V_41U/6.3V_4
AC35 VCC31 VTT0_31 A12 AJ21 VAXG29 VDDQ5 AC1
AC34 VCC32 VTT0_32 A11 AJ19 VAXG30 VDDQ6 AB7
AC33 VCC33 AJ18 VAXG31 VDDQ7 AB4
AC32 +1.05V_VTT AJ16 Y1
VCC34 VAXG32 VDDQ8
AC31 VCC35 AH21 VAXG33 VDDQ9 W7
POWER
AC30 VCC36 VTT0_33 AF10 AH19 VAXG34 VDDQ10 W4
AC29 VCC37 VTT0_34 AE10 AH18 VAXG35 VDDQ11 U1
AC28 VCC38 VTT0_35 AC10 AH16 VAXG36 VDDQ12 T7
CPU CORE SUPPLY
C AC27 AB10 T4 + C331 C

VCC39 VTT0_36 +1.05V_VTT VDDQ13 330U/2.5V_7343 C336 C337
AC26 VCC40 VTT0_37 Y10 VDDQ14 P1
AA35 W10 C605 C299 N7 7343 22U/6.3V_8 22U/6.3V_8
VCC41 VTT0_38 22U/6.3V_8 22U/6.3V_8 VDDQ15 2.5
AA34 VCC42 VTT0_39 U10 VDDQ16 N4
DDR3
AA33 VCC43 VTT0_40 T10 VDDQ17 L1
AA32 VCC44 VTT0_41 J12 J24 VTT1_45 VDDQ18 H1
FDI
AA31 VCC45 VTT0_42 J11 J23 VTT1_46
AA30 J16 H25 +1.05V_VTT +VCC_CORE
VCC46 VTT0_43 C615 C309 VTT1_47
AA29 VCC47 VTT0_44 J15
AA28 22U/6.3V_8 22U/6.3V_8
VCC48
AA27 VCC49 VTT0_59 P10
AA26 VCC50 VTT0_60 N10
Y35 L10 + C593 C249 C594 C599 C241 C289
VCC51 VTT0_61 C312 C298 C303 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8
Y34 VCC52 VTT0_62 K10
Y33 10U/6.3V_8 10U/6.3V_8 *330U/2.5V_7343
VCC53
Y32 VCC54
Y31 VCC55
VTT0_43,VTT0_44:(Intel feedback)
Y30 VCC56 They are connected to hidden page for
1.1V
Y29 VCC57 intel validation purpose. VTT1_63 J22
Y28 VCC58 K26 VTT1_48 VTT1_64 J20
Y27 J27 J18 C291 C286 C251 C244 C290 C287
VCC59 VTT1_49 VTT1_65
PEG & DMI

Y26 J26 H21 C301 C610 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8
VCC60 H_PSI# C613 C612 VTT1_50 VTT1_66 22U/6.3V_8 22U/6.3V_8
V35 VCC61 PSI# AN33 H_PSI# (36) J25 VTT1_51 VTT1_67 H20
V34 22U/6.3V_8 22U/6.3V_8 H27 H19
POWER
VCC62 VTT1_52 VTT1_68

V33 VCC63 G28 VTT1_53
V32 AK35 VID0 G27 +1.8V_RUN
VCC64 VID[0] VID0 (36) VTT1_54
V31 AK33 VID1 VID1 (36) G26
VCC65 VID[1] VID2 VTT1_55
V30 VCC66 VID[2] AK34 VID2 (36) F26 VTT1_56
V29 AL35 VID3 VID3 (36) E26 L26 C261 C250 C604 C264 C242 C596
VCC67 VID[3] VTT1_57 VCCPLL1
CPU VIDS
1.8V
V28 AL33 VID4 VID4 (36) E25 L27 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8
VCC68 VID[4] VID5 VTT1_58 VCCPLL2
V27 VCC69 VID[5] AM33 VID5 (36) VCCPLL3 M26
V26 AM35 VID6 VID6 (36) C270 C611 C247 C590 C246 C248 C591
B VCC70 VID[6] DPRSLPVR 22U/6.3V_8 22U/6.3V_8 1U/6.3V_4 1U/6.3V_4 2.2U/6.3V_6 4.7U/6.3V_6 22U/6.3V_8 B
U35 VCC71 PROC_DPRSLPVR AM34 DPRSLPVR (36)
U34 VCC72
U33 VCC73
U32 VCC74
U31 G15 H_VTTVID1 (37) C598 C597 C288 C263 C609 C262
VCC75 VTT_SELECT 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8
U30 VCC76
U29 Clarksfield/Auburndale
VCC77 +VCC_CORE
U28 VCC78
U27 VCC79
U26 VCC80
R35 VCC81
R34 VCC82
R33 VCC_SENSE & VSS_SENSE: C243 C600 C603 C595
VCC83 R362 SC(V1.0)P19 +1.05V_VTT 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8
R32 VCC84 ISENSE AN35 I_MON (36)
R31 100/F_4 100- ±1% pull-down to GND near processor
VCC85
R30 VCC86
R29 VCC87
SENSE LINES
R28 VCC88 VCC_SENSE AJ34 VCCSENSE (36)

R27 VCC89 VSS_SENSE AJ35 VSSSENSE (36)
R26 R346 R345 R347 R348 R349 R353 R350 R351 R352
VCC90 1K/J_4 1K/J_4 1K/J_4 *1K/J_4 *1K/J_4 1K/J_4 *1K/J_4 1K/J_4 *1K/J_4 + C258 + C274
P35 VCC91
P34 B15 VTT_SENSE (37) *470U/6.3V_7343 *470U/6.3V_7343
VCC92 VTT_SENSE VID0
P33 VCC93 VSS_SENSE_VTT A15 VSS_SENSE_VTT (37)
P32 R363 VID1
VCC94 100/F_4 VID2
P31 VCC95
P30 VID3
VCC96 VID4
P29 VCC97
P28 VSS_SENSE_VTT: VID5
VCC98 SC(V1.0)P20 PROC_DPRSLPVR: VID6
P27 VCC99
P26 Connect VSS_SENSE_VTT to GND SC(V1.0)P19: DPRSLPVR
VCC100 or can be left floating. It is important to have the resistor stuffing options H_PSI#
Note: CRB has the VSS_SENSE_VTT floating. in the design for the Turbo functionality.
A The stuffing and no-stuffing of the resistors A
will depend on the POC configuration of AUB
and CFD Note: R365 R364 R366 R367 R368 R372 R369 R370 R371
CRB(V1.0)P67: For Validating IMVP VR R814 should be STUFF *1K/J_4 *1K/J_4 *1K/J_4 1K/J_4 1K/J_4 *1K/J_4 1K/J_4 *1K/J_4 1K/J_4
uses 1K pull-up and pull-down resistors and R827 NO_STUFF
CRB default setting is "1"
Clarksfield/Auburndale
AUBURNDALE/CLARKSFIELD PROCESSOR (POWER) Quanta Computer Inc.

PROJECT : FH2A
1A
ARRANDALE 3/4
5 4 3 2 1
5 4 3 2 1
ARRANDALE PROCESSOR (GND) ARRANDALE PROCESSOR( RESERVED, CFG)
AT20
AT17
U30H
VSS1 VSS81 AE34

AE33
U30I
AP25
U30E
RSVD32
RSVD33
AJ13
AJ12
07
VSS2 VSS82 RSVD1
AR31 VSS3 VSS83 AE32 K27 VSS161 AL25 RSVD2 RSVD34 AH25
AR28 VSS4 VSS84 AE31 K9 VSS162 AL24 RSVD3 RSVD35 AK26
AR26 VSS5 VSS85 AE30 K6 VSS163 AL22 RSVD4
AR24 VSS6 VSS86 AE29 K3 VSS164 AJ33 RSVD5 RSVD36 AL26
AR23 VSS7 VSS87 AE28 J32 VSS165 AG9 RSVD6 RSVD_NCTF_37 AR2
D AR20 AE27 J30 M27 D
VSS8 VSS88 VSS166 RSVD7
AR17 VSS9 VSS89 AE26 J21 VSS167 L28 RSVD8 RSVD38 AJ26
AR15 VSS10 VSS90 AE6 J19 VSS168 J17 SA_DIMM_VREF RSVD39 AJ27
AR12 VSS11 VSS91 AD10 H35 VSS169 H17 SB_DIMM_VREF
AR9 VSS12 VSS92 AC8 H32 VSS170 G25 RSVD11
AR6 VSS13 VSS93 AC4 H28 VSS171 G17 RSVD12
AR3 VSS14 VSS94 AC2 H26 VSS172 E31 RSVD13 RSVD_NCTF_40 AP1
AP20 VSS15 VSS95 AB35 H24 VSS173 E30 RSVD14 RSVD_NCTF_41 AT2
AP17 VSS16 VSS96 AB34 H22 VSS174
AP13 VSS17 VSS97 AB33 H18 VSS175 RSVD_NCTF_42 AT3
AP10 VSS18 VSS98 AB32 H15 VSS176 RSVD_NCTF_43 AR1
AN34 VSS22 VSS102 AB28 H5 VSS180 RSVD45 AL28
AN31 AB27 H2 CFG0 AM30 AL29
VSS23 VSS103 VSS181 CFG[0] RSVD46
AN23 VSS24 VSS104 AB26 G34 VSS182 AM28 CFG[1] RSVD47 AP30
AN20 VSS25 VSS105 AB6 G31 VSS183 AP31 CFG[2] RSVD48 AP32
AN17 AA10 G20 CFG3 AL32 AL27
VSS26 VSS106 VSS184 CFG4 CFG[3] RSVD49
AM29 VSS27 VSS107 Y8 G9 VSS185 AL30 CFG[4] RSVD50 AT31
AM27 VSS28 VSS108 Y4 G6 VSS186 AM31 CFG[5] RSVD51 AT32
AM25 VSS29 VSS109 Y2 G3 VSS187 AN29 CFG[6] RSVD52 AP33
AM20 W35 F30 CFG7 AM32 AR33
VSS30 VSS110 VSS188 CFG[7] RSVD53
AM17 VSS31 VSS111 W34 F27 VSS189 AK32 CFG[8] RSVD_NCTF_54 AT33
AM14 W33 F25 AK31 AT34
RESERVED
VSS32 VSS112 VSS190 CFG[9] RSVD_NCTF_55
AM11 VSS33 VSS113 W32 F22 VSS191 AK28 CFG[10] RSVD_NCTF_56 AP35
AM8 VSS34 VSS114 W31 F19 VSS192 AJ28 CFG[11] RSVD_NCTF_57 AR35
AM5 VSS35 VSS115 W30 F16 VSS193 AN30 CFG[12] RSVD58 AR32
C AM2 VSS36 VSS116 W29 E35 VSS194 AN32 CFG[13] C
AL34 W28 E32 AJ32
AL31
AL23
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
W27
W26
E29
E24
VSS195
VSS196
VSS197
VSS AJ29
AJ30
CFG[14]
CFG[15]
CFG[16]
RSVD_TP_59
RSVD_TP_60
E15
F15
AL20 VSS40 VSS120 W6 E21 VSS198 AK30 CFG[17] KEY A2
AL17 VSS41 VSS121 V10 E18 VSS199 H16 RSVD_TP_86 RSVD62 D15
AL12 VSS42 VSS122 U8 E13 VSS200 RSVD63 C15
AL9 VSS43 VSS123 U4 E11 VSS201 RSVD64 AJ15
AL6 VSS44 VSS124 U2 E8 VSS202 RSVD65 AH15
AL3 VSS45 VSS125 T35 E5 VSS203
AK29 VSS46 VSS126 T34 E2 VSS204 VSS_NCTF1 AT35 B19 RSVD15
AK27 VSS47 VSS127 T33 D33 VSS205 VSS_NCTF2 AT1 A19 RSVD16
AK25 VSS48 VSS128 T32 D30 VSS206 VSS_NCTF3 AR34
AK20 VSS49 VSS129 T31 D26 VSS207 VSS_NCTF4 B34 A20 RSVD17
AK17 T30 D9 B2 B20
NCTF
VSS50 VSS130 VSS208 VSS_NCTF5 RSVD18
AJ31 VSS51 VSS131 T29 D6 VSS209 VSS_NCTF6 B1 RSVD_TP_66 AA5
AJ23 VSS52 VSS132 T28 D3 VSS210 VSS_NCTF7 A35 U9 RSVD19 RSVD_TP_67 AA4
AJ20 VSS53 VSS133 T27 C34 VSS211 T9 RSVD20 RSVD_TP_68 R8
AJ17 VSS54 VSS134 T26 C32 VSS212 RSVD_TP_69 AD3
AJ14 VSS55 VSS135 T6 C29 VSS213 AC9 RSVD21 RSVD_TP_70 AD2
AJ11 VSS56 VSS136 R10 C28 VSS214
VSS_NCTF pins can be connected to GND or left as NC (floating). AB9 RSVD22 RSVD_TP_71 AA2
AJ8 VSS57 VSS137 P8 C24 VSS215 When tied to GND they should be routed as trace and RSVD_TP_72 AA1
AJ5 VSS58 VSS138 P4 C22 VSS216 not as a GND plane. RSVD_TP_73 R9
AJ2 VSS59 VSS139 P2 C20 VSS217 RSVD_TP_74 AG7
AH35 VSS60 VSS140 N35 C19 VSS218 C1 RSVD_NCTF_23 RSVD_TP_75 AE3
AH34 VSS61 VSS141 N34 C16 VSS219 A3 RSVD_NCTF_24
AH33 VSS62 VSS142 N33 B31 VSS220
AH32 VSS63 VSS143 N32 B25 VSS221 RSVD_TP_76 V4
B AH31 VSS64 VSS144 N31 B21 VSS222 RSVD_TP_77 V5 B
AH30 VSS65 VSS145 N30 B18 VSS223 RSVD_TP_78 N2
AH29 VSS66 VSS146 N29 B17 VSS224 J29 RSVD26 RSVD_TP_79 AD5
AH28 VSS67 VSS147 N28 B13 VSS225 J28 RSVD27 RSVD_TP_80 AD7
AH27 VSS68 VSS148 N27 B11 VSS226 RSVD_TP_81 W3
AH26 VSS69 VSS149 N26 B8 VSS227 A34 RSVD_NCTF_28 RSVD_TP_82 W2
AH20 VSS70 VSS150 N6 B6 VSS228 A33 RSVD_NCTF_29 RSVD_TP_83 N3
AH17 VSS71 VSS151 M10 B4 VSS229 RSVD_TP_84 AE5
AH13 VSS72 VSS152 L35 A29 VSS230 C35 RSVD_NCTF_30 RSVD_TP_85 AD9
AH9 VSS73 VSS153 L32 A27 VSS231 B35 RSVD_NCTF_31
AH6 VSS74 VSS154 L29 A23 VSS232
AH3 VSS75 VSS155 L8 A9 VSS233 VSS AP34
AG10 VSS76 VSS156 L5 Can be left NC is Intel CRM
AF8 L2 R373
VSS77 VSS157 implementation; ESD/DG
AF4 VSS78 VSS158 K34 *0_4_SHORT
AF2 K33 recommendation to GND
VSS79 VSS159 Clarksfield/Auburndale
AE35 VSS80 VSS160 K30
DGG^9000005
Clarksfield/Auburndale Clarksfield/Auburndale
DGG^9000005 DGG^9000005
1 0
CFG4 Enabled; An external Display port
CS23012FB16 (Display Port Disabled; No Physical Display Port device is connected to the Embedded
A
The Clarkfield processor's PCI Express interface may CFG0 R376 *3.01K/F_4 Presence) attached to Embedded Diplay Port Display port A
CS23012FB16
not meet PCI Express 2.0 jitter specifications. Intel CFG3 R105 3.01K/F_4 CFG0
recommends placing a 3.01K +/- 5% pull down resistor to
VSS on CFG[7] pin for both rPGA and BGA components. CFG4 R104 *3.01K/F_4 (PCI-Epress Single PEG Bifurcation enabled
CS23012FB16 Configuration Select)
This pull down resistor should be removed when this CFG7 R374 *3.01K/F_4 Quanta Computer Inc.
issue is fixed. CS23012FB16 CFG3
(PCI-Epress Static Normal Operation Lane Numbers Reversed PROJECT : FH2A
Lane Reversal) Size Document Number Rev
1A
ARRANDALE 4/4
5 4 3 2 1
5 4 3 2 1
IBEX PEAK-M (DMI,FDI,GPIO) IBEX PEAK-M (LVDS,DDI)

08
U31C
FDI_RXN0 BA18
(4) DMI_RXN0 BC24 DMI0RXN FDI_RXN1 BH17
BJ22 BD16 U31D
(4) DMI_RXN1 DMI1RXN FDI_RXN2
(4) DMI_RXN2 AW20 DMI2RXN FDI_RXN3 BJ16 T48 L_BKLTEN SDVO_TVCLKINN BJ46
(4) DMI_RXN3 BJ20 DMI3RXN FDI_RXN4 BA16 T47 L_VDD_EN SDVO_TVCLKINP BG46
FDI_RXN5 BE14
(4) DMI_RXP0 BD24 DMI0RXP FDI_RXN6 BA14 Y48 L_BKLTCTL SDVO_STALLN BJ48
D
(4) DMI_RXP1 BG22 DMI1RXP FDI_RXN7 BC12 SDVO_STALLP BG48 D
(4) DMI_RXP2 BA20 DMI2RXP AB48 L_DDC_CLK
(4) DMI_RXP3 BG20 DMI3RXP FDI_RXP0 BB18 Y45 L_DDC_DATA SDVO_INTN BF45
FDI_RXP1 BF17 SDVO_INTP BH45
(4) DMI_TXN0 BE22 DMI0TXN FDI_RXP2 BC16 AB46 L_CTRL_CLK
(4) DMI_TXN1 BF21 DMI1TXN FDI_RXP3 BG16 V48 L_CTRL_DATA
(4) DMI_TXN2 BD20 DMI2TXN FDI_RXP4 AW16
(4) DMI_TXN3 BE18 DMI3TXN FDI_RXP5 BD14 AP39 LVD_IBG SDVO_CTRLCLK T51
FDI_RXP6 BB14 AP41 LVD_VBG SDVO_CTRLDATA T53
(4) DMI_TXP0 BD22 DMI0TXP FDI_RXP7 BD12
(4) DMI_TXP1 BH21 DMI1TXP AT43 LVD_VREFH
(4) DMI_TXP2 BC20 DMI2TXP AT42 LVD_VREFL DDPB_AUXN BG44
(4) DMI_TXP3 BD18 DMI3TXP FDI_INT BJ14 DDPB_AUXP BJ44
AU38
DMI
FDI
DDPB_HPD
LVDS
FDI_FSYNC0 BF13 AV53 LVDSA_CLK#
BH25 DMI_ZCOMP AV51 LVDSA_CLK DDPB_0N BD42
FDI_FSYNC1 BH13 DDPB_0P BC42
+1.05V_PCH R138 49.9/F_4 DMI_ZCOMP BF25 BB47 BJ42
DMI_IRCOMP LVDSA_DATA#0 DDPB_1N
Digital Display Interface

FDI_LSYNC0 BJ12 BA52 LVDSA_DATA#1 DDPB_1P BG42
AY48 LVDSA_DATA#2 DDPB_2N BB40
FDI_LSYNC1 BG14 AV47 LVDSA_DATA#3 DDPB_2P BA40
DDPB_3N AW38
EMI BB48 BA38
LVDSA_DATA0 DDPB_3P
BA50 LVDSA_DATA1
AY49 LVDSA_DATA2
C318 *10P/50V_4 AV48 Y49
LVDSA_DATA3 DDPC_CTRLCLK
DDPC_CTRLDATA AB49
XDP_DBRESET# T6 J12 PCIE_WAKE# AP48

(4) XDP_DBRESET# SYS_RESET# WAKE# PCIE_WAKE# (26,33) LVDSB_CLK#
AP47 LVDSB_CLK DDPC_AUXN BE44
DDPC_AUXP BD44
R179 0/J_S SYS_PWROK M6 Y1 CLKRUN# AY53 AV40
<Part Number> SYS_PWROK CLKRUN# / GPIO32 LVDSB_DATA#0 DDPC_HPD
AT49 LVDSB_DATA#1
AU52 BE40
System Power Management

PCH_PWRGD R398 0/J_S PWROK LVDSB_DATA#2 DDPC_0N
C
B17 PWROK AT53 LVDSB_DATA#3 DDPC_0P BD40 C
<Part Number> BF41
DDPC_1N
AY51 LVDSB_DATA0 DDPC_1P BH41
C326 R165 0/J_S MEPWROK K5 P8 RSV_LPCPD# T54 AT48 BD38
<Part Number> MEPWROK SUS_STAT# / GPIO61 LVDSB_DATA1 DDPC_2N
*10P/50V_4 AU50 LVDSB_DATA2 DDPC_2P BC38
AT51 LVDSB_DATA3 DDPC_3N BB36
EMI LAN_RST# A10 F3 ICH_SUSCLK BA36
LAN_RST# SUSCLK / GPIO62 T61 DDPC_3P
(4) PM_DRAM_PWRGD D9 DRAMPWROK SLP_S5# / GPIO63 E4 SIO_SLP_S5# (32) AA52 CRT_BLUE DDPD_CTRLCLK U50
AB53 CRT_GREEN DDPD_CTRLDATA U52
AD53 CRT_RED
ICH_RSMRST# C16 H7
(32) ICH_RSMRST# RSMRST# SLP_S4# SIO_SLP_S4# (32,33)
DDPD_AUXN BC46
V51 CRT_DDC_CLK DDPD_AUXP BD46
(32) SUS_PWR_ACK SUS_PWR_ACK M1 P12 V53 AT38
SUS_PWR_DN_ACK / GPIO30 SLP_S3# SIO_SLP_S3# (32,33) CRT_DDC_DATA DDPD_HPD
DDPD_0N BJ40
P5 K8 SLP_M#_R T53 Y53 BG40
(32) DNBSWON# PWRBTN# SLP_M# CRT_HSYNC DDPD_0P
Y51 CRT_VSYNC DDPD_1N BJ38
DDPD_1P BG38
CRT
AC_PRESENT P7 N2 T93 BF37
(32) AC_PRESENT ACPRESENT / GPIO31 TP23 DDPD_2N
R111 1K/D_4 AD48 BH37
DAC_IREF DDPD_2P
AB51 CRT_IRTN DDPD_3N BE36
PM_BATLOW# A6 BJ10 BD36
BATLOW# / GPIO72 PMSYNCH PM_SYNC (4) DDPD_3P
IbexPeak-M_R1P0
PM_RI# F14 F6 PM_SLP_LAN#_R
RI# SLP_LAN# / GPIO29
IbexPeak-M_R1P0
B B
+3V_RUN
CLKRUN# R420 8.2K_4 PCH_PWRGD R180 10K/J_4
XDP_DBRESET# R175 1K/J_4 ICH_RSMRST# R402 10K/J_4
LAN_RST# R409 10K/J_4
+3V_S5 PM_SLP_LAN#_R R158 10K/J_4
PM_RI# R410 10K/J_4
PCIE_WAKE# R161 10K/J_4
PM_BATLOW# R415 8.2K/J_4
AC_PRESENT R193 8.2K/J_4
SUS_PWR_ACK R449 8.2K/J_4
+3V_RUN +3V_S5
C323 *0.1U/10V_4
R196 <Part Number>
*2K_4
<Part Number>
5
U10
A (4,36) IMVP_PWRGD 2 A
4 PCH_PWRGD
(23,32) MPWROK 1
C329 MC74VHC1G08DFT2G
3
*0.1U_4
<Part Number>

PROJECT : FH2A
1A
IBEX PEAK-M 1/6
5 4 3 2 1
5 4 3 2 1
+VCC_RTC
RTC BATTERY
+3VPCU
R486
2
D29
1
R403 20K/F_4
C620
15P/50V_4 IBEX PEAK-M (HDA,JTAG,SATA) 09
2
1
C617
1K/J_4 CH501H-40
1U/6.3V_4 Y5 R408
+VCCRTC3 32.768KHZ 10M/J_4
D30
C621
3
4
U31A
2 1
R395 20K/F_4 15P/50V_4 RP2
D D
CH501H-40 RTC_X1 B13 D33 1 2 *47X4-0402
RTCX1 FWH0 / LAD0 LAD0 (29,32)
C606 RTC_X2 D13 B33 3 4
RTCX2 FWH1 / LAD1 LAD1 (29,32)
R487 Cap values depend on Xtal C32 5 6
FWH2 / LAD2 LAD2 (29,32)
1K/J_4 R400 1U/6.3V_4 A32 7 8
FWH3 / LAD3 LAD3 (29,32)
1M/F_4 RTC_RST# C14 RTCRST# R_LFRAME# R120 47/F_4
FWH4 / LFRAME# C34 LFRAME# (29,32)
CON9 SRTC_RST# D17 SRTCRST# R455 10K/J_4
1 A34 +3V_RUN
RTC
LPC
1 SM_INTRUDER# LDRQ0#
2 2 A16 INTRUDER# LDRQ1# / GPIO23 F34
AAA-BAT-054-K01 +VCC_RTC R405 330K/J_4 PCH_INVRMEN A14 AB9

INTVRMEN SERIRQ IRQ_SERIRQ (32)
bat-23_2-4_2
INTVRMEN(Internal Voltage Regulator Enable) : ACZ_BIT_CLK A30 HDA_BCLK

This signal enables the internal 1.05 V regulators. SATA0RXN AK7 SATA_RXN0 (27) SATA HDD
This signal must be always pulled-up to VccRTC. ACZ_SYNC D29 AK6
HDA_SYNC SATA0RXP SATA_RXP0 (27)
SATA0TXN AK11 SATA_TXN0 (27)
(31) PCBEEP PCBEEP P1 AK9
SPKR SATA0TXP SATA_TXP0 (27)
ACZ_RST# C30 HDA_RST#
SATA1RXN AH6 SATA_RXN1 (27) SATA ODD
SATA1RXP AH5 SATA_RXP1 (27)
CODEC (31) ACZ_SDIN0 G30 HDA_SDIN0 SATA1TXN AH9 SATA_TXN1 (27)
SATA1TXP AH8 SATA_TXP1 (27)
F30 HDA_SDIN1
SATA2RXN AF11
E32 AF9
IHDA
HDA_SDIN2 SATA2RXP
SATA2TXN AF7
C F32 HDA_SDIN3 SATA2TXP AF6 C
SATA port 2/3 are not support in HM55 .
R389 33/J_4 ACZ_SYNC AH3
(31) ACZ_SYNC_R SATA3RXN
R386 33/J_4 ACZ_RST# Flash Descriptor Security Override ACZ_SDOUT B29 AH1
(31) ACZ_RST#_R HDA_SDO SATA3RXP
CODEC R391 33/J_4 ACZ_SDOUT AF3
(31) ACZ_SDOUT_R SATA3TXN
R387 33/J_4 ACZ_BIT_CLK AF1
(31) ACZ_BIT_CLK_R SATA3TXP
(32) MEFW_OVERRIDE ME_FW_OVERRIDE R197 1 2 1K/F_4 H32
SATA
HDA_DOCK_EN# / GPIO33
Low = Enabled AD9
F-04 GPIO33 High = Disabled GPIO13 J30 HDA_DOCK_RST# / GPIO13
SATA4RXN
SATA4RXP AD8
C592 PR33 10K/F_4 AD6
22P/50V_4 SATA4TXN
SATA4TXP AD5
(Internal 20K/F pull high to +3.3V_RUN)
50 T94 PCH_JTAG_TCK_BUF M3 AD3
JTAG_TCK SATA5RXN
SATA5RXP AD1
T99 PCH_JTAG_TMS K3 AB3
JTAG_TMS SATA5TXN
Note : GPIO33 is a signal used for Flash SATA5TXP AB1
T100 PCH_JTAG_TDI K1
Descriptor Security Override/ME Debug JTAG_TDI
JTAG
Mode.This signal should be only asserted T96 PCH_JTAG_TDO J2 AF16
JTAG_TDO SATAICOMPO
lowthrough an external pull-down in
manufacturing or debug environments T98 PCH_JTAG_RST# J4 AF15 SATA_COMP R142 37.4/F_4 +1.05V_PCH
TRST# SATAICOMPI
Place all series terms close to PCH except for SDIN input ONLY.
lines,which should be close to source.Placement of R773, R775, SPI_CLK BA2 SPI_CLK
R776 & R777 should equal distance to the T split trace point. R441 10K/J_4 +3V_RUN
Basically, keep the same distance from T for all series SPI_CS0# AV3 SPI_CS0#
termination resistors.
T58 SPI_CS1# AY3 T3
SPI_CS1# SATALED# SATA_LED# (30)
B B
SPI_SI AY1 Y9 R147 1 2 10K/J_4 +3V_RUN
SPI_MOSI SATA0GP / GPIO21
SPI
+3V_RUN SPI_SO AV1 V1 R418 1 2 10K/J_4
SPI_MISO SATA1GP / GPIO19
No Reboot strap.
1 2 PCBEEP Low = Default. IbexPeak-M_R1P0
R417 *1K/J_4 PCBEEP High = No Reboot.
RESET JUMP (Near ROOM DOOR)

JTAG
Test Pads are need to put on
the same side of mother board.
For PCH 32Mbit (4M Byte) RTC_RST#
+3V_S5 Res. of TDI near PCH
2 CL1
+3V_RUN +3V_RUN CL1_CL1
PAD
R450 R448 R437 R442 <Part Number>
CL2
R427
1
200/J_4 200/J_4 200/J_4 *20K/J_4 3.3K/J_4
R431
PCH_JTAG_TMS U32 3.3K/J_4 SRTC_RST#
PCH_JTAG_TDI SPI_CS0# R422 15/J_4 SPI_CS0#_R 1 8
PCH_JTAG_TDO R452 51/J_4 PCH_JTAG_TCK_BUF SPI_CLK R432 15/J_4 SPI_CLK_R CE# VDD G1
6 SCK
PCH_JTAG_RST# SPI_SI R436 15/J_4 SPI_SI_R 5 *
SPI_SO R424 15/J_4 SPI_SO_R SI *SHORT_ PAD
A 2 SO HOLD# 7 A
R451 R454 R434 R440 C629 3 4

22P/50V_4 WP# VSS C628
100/J_4 100/J_4 100/J_4 *10K/J_4 EN25F16 0.1U/10V_4
50
Note : Only pop when PCH is production 10
stage & need "JTAG boundary Scan". Quanta Computer Inc.
NC all Res. when Res. of TDO
Remember to depop XDP side Res.
PCH is PCH ES1 stage : NC PROJECT : FH2A
production stage. PCH ES2 stage : pop Size Document Number Rev
1A
IBEX PEAK-M 2/6
5 4 3 2 1
5 4 3 2 1
IBEX PEAK-M (PCI,USB,NVRAM)

Place TX DC blocking caps close PCH.
IBEX PEAK-M (PCI-E,SMBUS,CLK)
U31B
FOR DDR3 SPD/CLOCK GEN
+3V_S5
10
EXPRESS CARD/MINI CARD
U31E
H40 AY9 BG30 B9 RSV_SMBALERT# 10K/J_4 R412
AD0 NV_CE#0 PERN1 SMBALERT# / GPIO11
N34 AD1 NV_CE#1 BD1 BJ30 PERP1
C44 AD2 NV_CE#2 AP15 BF29 PETN1 SMBCLK H14 PCH_SMBCLK 2.2K/J_4 R439
A38 AD3 NV_CE#3 BD8 BH29 PETP1
C36 C8 PCH_SMBDATA 2.2K/J_4 R160
AD4 SMBDATA
J34 AD5 NV_DQS0 AV9 (29) PCIE_RXN2 AW30 PERN2
A40 AD6 NV_DQS1 BG8 MiniWLAN (29) PCIE_RXP2 BA30 PERP2
D45 C273 0.1U/10V_4 PCIE_TXN2_C BC30 J14 RSV_ICH_CL_RST1#
10K/J_4 R172
D AD7 (29) PCIE_TXN2 PETN2 SML0ALERT# / GPIO60 D
E36 AP7 C268 0.1U/10V_4 PCIE_TXP2_C BD30
AD8 NV_DQ0 / NV_IO0 (29) PCIE_TXP2 PETP2
H48 AP6 C6 SMB_CLK_ME0 2.2K/J_4 R414 0 FOR INTEL LAN
AD9 NV_DQ1 / NV_IO1 SML0CLK
E40 AT6 AU30
SMBus
AD10 NV_DQ2 / NV_IO2 PERN3 SMB_DATA_ME0 2.2K/J_4 R167
C40 AD11 NV_DQ3 / NV_IO3 AT9 AT30 PERP3 SML0DATA G8
M48 AD12 NV_DQ4 / NV_IO4 BB1 AU32 PETN3
M45 AD13 NV_DQ5 / NV_IO5 AV6 AV32 PETP3
F53 AD14 NV_DQ6 / NV_IO6 BB3 SML1ALERT# / GPIO74 M14 LPD_SPI_INTR# 10K/J_4 R146
M40 AD15 NV_DQ7 / NV_IO7 BA4 BA32 PERN4 SMB_CLK_ME1 2.2K/J_4 R446
NVRAM
M43 AD16 NV_DQ8 / NV_IO8 BE4 BB32 PERP4 SML1CLK / GPIO58 E10 1 FOR EC
J36 AD17 NV_DQ9 / NV_IO9 BB6 BD32 PETN4
K48 AD18 NV_DQ10 / NV_IO10 BD6 BE32 PETP4 SML1DATA / GPIO75 G12 SMB_DATA_ME1 2.2K/J_4 R445
F40 BB7
PCI-E*
AD19 NV_DQ11 / NV_IO11
C42 AD20 NV_DQ12 / NV_IO12 BC8 (33) PCIE_RXN5 BF33 PERN5
K46 BJ8 NEW CARD BH33 T13 SML0CLK/SML0DATA:
AD21 NV_DQ13 / NV_IO13 (33) PCIE_RXP5 PERP5 CL_CLK1
Controller
M51 BJ6 C277 0.1U/10V_4 PCIE_TXN5_C BG32 DG(V1.1) P255: The 82577 SMBus
AD22 NV_DQ14 / NV_IO14 (33) PCIE_TXN5 PETN5 signals
J52 BG6 C276 0.1U/10V_4 PCIE_TXP5_C BJ32 T11
AD23 NV_DQ15 / NV_IO15 (33) PCIE_TXP5 PETP5 CL_DATA1 (SMB_DATA and SMB_CLK) cannot be
K51
Link
AD24 connected to any other
L34 AD25 NV_ALE BD3 NV_ALE (11) (26) PCIE_RXN6 BA34 PERN6 CL_RST1# T9
devices other than the PCH.
F42 AD26 NV_CLE AY6 NV_CLE (11) LAN (26) PCIE_RXP6 AW34 PERP6 Connect the SMB_DATA and SMB_CLK
J40 C259 0.1U/10V_4 PCIE_TXN6_C BC34
AD27 (26) PCIE_TXN6 PETN6 pins
G46 C256 0.1U/10V_4 PCIE_TXP6_C BD34
AD28 (26) PCIE_TXP6 PETP6
F44 AU2 H1 PEG_CLKREQ# T89 to the PCH SML0DATA and SML0CLK
AD29 NV_RCOMP PEG_A_CLKRQ# / GPIO47 pins,
M47 AD30 AT34 PERN7 respectively.
PCI
H36 AD31 NV_RB# AV7 AU34 PERP7
AU36 AD43 CLK_PCIE_VGAN
PETN7 CLKOUT_PEG_A_N CLK_PCIE_VGAN (16)
J50 AY8 AV36 AD45 CLK_PCIE_VGAP
C/BE0# NV_WR#0_RE# PETP7 CLKOUT_PEG_A_P CLK_PCIE_VGAP (16)
G42 C/BE1# NV_WR#1_RE# AY5 PCIE port 7/8 are not support in HM55 .
H47 C/BE2# BG34 PERN8 CLKOUT_DMI_N AN4 CLK_PCIE_3GPLLN (4)
PEG
G34 C/BE3# NV_WE#_CK0 AV11 BJ34 PERP8 CLKOUT_DMI_P AN2 CLK_PCIE_3GPLLP (4)
NV_WE#_CK1 BF5 BG36 PETN8
T38 PCI_PIRQA# G38 BJ36
PCI_PIRQB# PIRQA# PETP8
H51 PIRQB# CLKOUT_DP_N / CLKOUT_BCLK1_N AT1
PCI_PIRQC# B37 H18 AT3
T81 PCI_PIRQD# PIRQC# USBP0N CLKOUT_DP_P / CLKOUT_BCLK1_P
A44 PIRQD# USBP0P J18 AK48 CLKOUT_PCIE0N
USBP1N A18 USBP1- (28) AK47 CLKOUT_PCIE0P
From CLK BUFFER

PCI_REQ0# F51 C18 USB PORT 1(DB) AW24
C REQ0# USBP1P USBP1+ (28) CLKIN_DMI_N CLK_BUF_PCIE_3GPLLN (3) C
HDMI_PWR_CTRL A46 N20 CLK_PEG0_REQ# P9 BA24
REQ1# / GPIO50 USBP2N USBP2- (28) PCIECLKRQ0# / GPIO73 CLKIN_DMI_P CLK_BUF_PCIE_3GPLLP (3)
T82 SB_WWAN_PCIE_RST# B45 P20 USB PORT 2(MB)
REQ2# / GPIO52 USBP2P USBP2+ (28)
USB_MCARD1_DET# M53 J20
REQ3# / GPIO54 USBP3N
USBP3P L20 (33) CLK_PCIE_MINI1N AM43 CLKOUT_PCIE1N CLKIN_BCLK_N AP3 CLK_BUF_BCLK_N (3)
PCI_GNT0# F48 F20 NEW CARD AM45 AP1
GNT0# USBP4N USBP4- (28) (33) CLK_PCIE_MINI1P CLKOUT_PCIE1P CLKIN_BCLK_P CLK_BUF_BCLK_P (3)
T39 GNT#1 K45 G20 USB PORT 4(MB)
GNT1# / GPIO51 USBP4P USBP4+ (28)
T48 GNT#2 F36 A20 R433 CLK_PCIE_REQ2#_R U4
GNT2# / GPIO53 USBP5N (33) NEWCARD1CLK_REQ# PCIECLKRQ1# / GPIO18
GNT3# H53 C20 *0_4_SHORT F18
(11) GNT3# GNT3# / GPIO55 USBP5P CLKIN_DOT_96N CLK_BUF_DREFCLKN (3)
USBP6N M22 CLKIN_DOT_96P E18 CLK_BUF_DREFCLKP (3)
PCH_IRQH_GPIO2 B41 N22 USB port 6/7 are not support in HM55 . AM47
PIRQE# / GPIO2 USBP6P (29) CLK_PCIE_MINI2N CLKOUT_PCIE2N
T79 SB_WLAN_PCIE_RST# K53 B21 MiniWLAN AM48
PIRQF# / GPIO3 USBP7N (29) CLK_PCIE_MINI2P CLKOUT_PCIE2P
BT_DET# A36 D21 AH13
PIRQG# / GPIO4 USBP7P CLKIN_SATA_N / CKSSCD_N CLK_BUF_DREFSSCLKN (3)
T80 PCH_IRQH_GPIO5 A48 H22 R462 MINI1CLK_REQ#_R N4 AH12
PIRQH# / GPIO5 USBP8N USBP8- (23) (29) MINI2CLK_REQ# PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P CLK_BUF_DREFSSCLKP (3)
J22 CAMERA *0_4_SHORT
USBP8P USBP8+ (23)
USB
PCI_RST# K6 E22
PCIRST# USBP9N USBP9- (28)
PCIRST#: T56 F22 BT AH42 P41
USBP9P USBP9+ (28) CLKOUT_PCIE3N REFCLK14IN CLK_PCH_14M (3)
DG(V1.0) P277 PCI_SERR# E44 A22 AH41
SERR# USBP10N USBP10- (33) CLKOUT_PCIE3P CLKIN_PCILOOPBACK:
Can be left unconnected. PCI_PERR# E50 C22 NEW CARD
PERR# USBP10P USBP10+ (33) PDG (V1.1): 22 ohm series resistor
G24 3G_CLK_REQ#_R A8 J42 CLK_PCI_FB
USBP11N USBP11- (29) PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK is recommend
PCI_IRDY# USBP11P H24 USBP11+ (29) WLAN
PAR: A42 IRDY# USBP12N L24 USBP12- (25) 0214
SC(V1.0) P36 H44 M24 CARD READER AM51 AH51 XTAL25_IN R380
PAR USBP12P USBP12+ (25) CLKOUT_PCIE4N XTAL25_IN
Can be left unconnected PCI_DEVSEL# F46 A24 AM53 AH53 XTAL25_OUT T78 *0_4_SHORT
PCI_FRAME# DEVSEL# USBP13N CLKOUT_PCIE4P XTAL25_OUT
if not using PCI. C46 FRAME# USBP13P C24
CARD_CLK_REQ#_R M9 AF38 XCLK_RCOMP +1.05V_PCH
PCI_PLOCK# PCIECLKRQ4# / GPIO26 XCLK_RCOMP R121 90.9/F_4
D49 PLOCK#
PME: B25 USB_BIAS
PCI_STOP# USBRBIAS# R394 22.6/F_4 CLK_FLEX0 T36
DG(V1.0) P277 D41 STOP# AJ50 CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64 T45
Can be left unconnected. PCI_TRDY# C48 D25 AJ52
TRDY# USBRBIAS CLKOUT_PCIE5P
PME# M7 CLK_PCIE_REQ5# H6 P43 CLK_FLEX1 T44
Clock Flex
T57 PME# PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65
N16 OC0#
PCI_PLTRST# OC0# / GPIO59 OC1#
0214 (32) PCI_PLTRST# D5 PLTRST# OC1# / GPIO40 J16
F16 OC2# AK53 T42 CLK_FLEX2 T40
OC2# / GPIO41 (26) CLK_PCIE_LOMN CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66
CLK_LPC_DEBUG R378 22/F_4 CLK_LPC_DEBUG_C N52 L16 OC3# LAN AK51
(29) CLK_LPC_DEBUG CLKOUT_PCI0 OC3# / GPIO42 (26) CLK_PCIE_LOMP CLKOUT_PEG_B_P
P53 E14 OC4#
B CLK_PCI_8502 R109 22/F_4 CLK_PCI_8502_C CLKOUT_PCI1 OC4# / GPIO43 OC5# R157 LOM_CLK_REQ#_R R379 33/J_4 B
(32) CLK_PCI_8502 P46 CLKOUT_PCI2 OC5# / GPIO9 G16 (26) CLK_LAN_REQ# P13 PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67 N50 CLK_48M_CR (25)
CLK_PCI_FB R107 22/F_4 CLK_PCI_FB_C P51 F12 OC6# *0_4_SHORT
CLKOUT_PCI3 OC6# / GPIO10 OC7#
CLKOUT_PCI[0..4]: P48 CLKOUT_PCI4 OC7# / GPIO14 T15 0214
22 ohm series resistor is recommend IbexPeak-M_R1P0
(single & double load) on PDG v1.1 OC0#~OC7#: CLKOUT_PEG_A_P/N,CLKOUT_PEG_B_P/N, C581
IbexPeak-M_R1P0 DG(V1.0)P214 CLKOUT_DMI_P/N,support GEN-1 and GEN-2 EMI USE *10P_4
Pin Default Port Mapping PCIE Clock Request
OC0# Port0,Port1 +3V_S5
Reserve capacitor pads for
OC1# Port2,Port3 Q18
improving WWAN. OC2# Port4,Port5 R413 10K/J_4 3G_CLK_REQ#_R 2N7002E
R178 10K/J_4 CARD_CLK_REQ#_R SMB_CLK_ME1 1 3 MBCLK_ME (32)
R166 10K/J_4 CLK_PCIE_REQ5# CLKOUTFLEX3:
+3V_RUN R177 10K/J_4 CLK_PEG0_REQ# EDS(V1.0) :support 48MHz
R153 10K/J_4 LOM_CLK_REQ#_R 33MHz and 14.31818MHz.
2
CLK_LPC_DEBUG 50 BT_DET# R384 8.2K/J_4 R425 10K/J_4 PEG_CLKREQ#
C580 *27P/50V_4 PCH_IRQH_GPIO2 R382 8.2K/J_4
CLK_PCI_8502 50 SB_WWAN_PCIE_RST# R381 8.2K/J_4 R429 *10K/J_4 +3V_S5 CLKOUTFLEX[0..3]:
C237 *27P/50V_4 SB_WLAN_PCIE_RST# R375 8.2K/J_4 PDG v1.1: 22 ohm series resistor is
+3V_RUN recommend (PCI & non PCI routing,
single & double load)
2
R176 10K/J_4 MINI1CLK_REQ#_R 2N7002E Q19
+3V_S5 R428 *10K/J_4 CLK_PCIE_REQ2#_R
RP3 SMB_DATA_ME1 1 3 MBDATA_ME (32)
OC7# 6 5 PCIECLKRQ{0,3,4,5,6,7}# should have a
OC5# 7 4 OC2# 10K pull-up to +V3.3A.PCIECLKRQ{1,2}
OC3# 8 3 OC6# should have a 10K pull-up to +3.3S
OC4# 9 2 OC1#
OC0#
Non-iAMT Add Buffers as needed for +3V_S5 10 1
Loading and fanout concerns. 10P8R-8.2K

C-05
+3V_RUN R113 1K/J_4 PCI_GNT0# Q17 2N7002E
RP4 R110 1K/J_4 GNT#1 PCH_SMBDATA 3 1 CGDAT_SMB (3,14,15)
+3V_RUN PCH_IRQH_GPIO5 6 5
A C330 *0.1U/16V_4 PCI_REQ0# 7 4 PCI_TRDY# A
PCI_PIRQB# 8 3 PCI_FRAME# R463
2
USB_MCARD1_DET# 9 2 HDMI_PWR_CTRL 2.2K/F_4
+3V_RUN 10 1 PCI_PIRQD#
5
U11 Boot BIOS Strap

PLTRST_EC# 2 10P8R-8.2K +3V_RUN
(32) PLTRST_EC#
4 PLTRST# (4,16,25,26,29,33) PCI_GNT0# GNT#1 Boot BIOS Location
PCI_PLTRST# 1
+3V_RUN 0 0 LPC
MC74VHC1G08DFT2G RP1 R447
3
PCI_STOP# 6 5 0 1 PCI 2.2K/F_4
2
PCI_PIRQA# 7 4 PCI_SERR#
PCI_PIRQC# 8 3 PCI_PERR# 1 0 Reserved (NAND) Q15 2N7002E
PCI_PLTRST# R252 0_4 PLTRST_EC# PCI_IRDY# 9 2 PCI_PLOCK# PCH_SMBCLK 3 1
PROJECT : FH2A
CGCLK_SMB (3,14,15)
+3V_RUN 10 1 PCI_DEVSEL# 1 1 SPI Size Document Number Rev
1A
10P8R-8.2K IBEX PEAK-M 3/6
5 4 3 2 1
5 4 3 2 1
S_GPIO Y3
U31F
IBEX PEAK-M (GPIO,VSS_NCTF,RSVD)
BMBUSY# / GPIO0 CLKOUT_PCIE6N AH45
11
CLKOUT_PCIE6P AH46
(32) SIO_EXT_SMI# SIO_EXT_SMI# C38 TACH1 / GPIO1
(32) SIO_EXT_SCI# SIO_EXT_SCI# D37 TACH2 / GPIO6

CLKOUT_PCIE7N AF48
MISC
T47 GPIO7 J32 AF47
TACH3 / GPIO7 CLKOUT_PCIE7P
D SWI# F10 D
(32) SWI# GPIO8
GPIO12 K9 U2 SIO_A20GATE
LAN_PHY_PWR_CTRL / GPIO12 A20GATE SIO_A20GATE (32)
PCH_GPIO15 T7 +3V_S5
GPIO15
SATA4GP AA2 AM3 +1.05V_VTT
SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLK_CPU_BCLKN (4)
GPIO45 R423 10K/J_4
T43 GPIO17 F38 AM1 TP_PCH_GPIO28 R145 10K/J_4
TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLK_CPU_BCLKP (4)
SWI# R174 10K/J_4
T55 GPIO22 Y7 BG10 PCH_GPIO15 R192 1K/J_4
SCLOCK / GPIO22 PECI H_PECI (4)
GPIO
BIOS_WP# R168 10K/J_4
GPIO24 register not cleared by CF9h reset event. H10 T1 SIO_RCIN# R149 GPIO12 R169 10K/J_4
GPIO24 RCIN# SIO_RCIN# (32)
GPIO27 reserve for internal VR. 56/J_4 DDR3_CORL_PCH R421 10K/J_4
R154 *10K/J_4 GPIO27 AB12 BE10
GPIO27 PROCPWRGD H_PWRGOOD (4)
CPU
TP_PCH_GPIO28 V13 BD10 PCH_THRMTRIP#_R R150 56/J_4
GPIO28 THRMTRIP# H_THERM (4) +3V_RUN
T60 GPIO34 M11 STP_PCI# / GPIO34 GPIO7 R119 10K/J_4
(Both these should be close to PCH)
GPIO35 V6 GPIO17 R112 10K/J_4
SATACLKREQ# / GPIO35 GPIO22 R162 10K/J_4
SATA2GP AB7 BA22 GPIO34 R164 10K/J_4
SATA2GP / GPIO36 TP1 GPIO38 R430 10K/J_4
SATA3GP AB13 AW22 GPIO39 R443 10K/J_4
SATA3GP / GPIO37 TP2 SIO_EXT_SMI# R115 10K/J_4
T91 GPIO38 V3 BB22 SIO_EXT_SCI# R114 10K/J_4
SLOAD / GPIO38 TP3 SIO_RCIN# R438 10K/J_4
T97 GPIO39 P3 AY45 SIO_A20GATE R435 10K/J_4
SDATAOUT0 / GPIO39 TP4 SATA2GP R151 10K/J_4
C GPIO45 H3 AY46 TEMP_ALERT# R416 10K/J_4 C
PCIECLKRQ6# / GPIO45 TP5 SATA3GP R148 10K/J_4
GPIO46 F1 AV43 SATA4GP R426 10K/J_4
(4) DDR3_CORL_PCH PCIECLKRQ7# / GPIO46 TP6
SV_SET_UP AB6 AV45
SDATAOUT1 / GPIO48 TP7
TEMP_ALERT# AA4 AF13
(32) TEMP_ALERT# SATA5GP / GPIO49 TP8
BIOS_WP# F8 M18
(32) BIOS_WP# GPIO57 TP9
TP10 N18
A4 VSS_NCTF_1 TP11 AJ24

A49
NCTF
VSS_NCTF_2 RSVD
A5 VSS_NCTF_3 TP12 AK41
A50 VSS_NCTF_4
DMI Termination Voltage
A52 VSS_NCTF_5 TP13 AK42
A53 VSS_NCTF_6
B2 VSS_NCTF_7 TP14 M32 Set to Vcc when LOW
B4 VSS_NCTF_8
NV_CLE
B52 N32 Set to Vcc/2 when HIGH +1.8V_RUN
VSS_NCTF_9 TP15
B53 VSS_NCTF_10
BE1 VSS_NCTF_11 TP16 M30
BE53 R156 *1K/J_4
VSS_NCTF_12 (10) NV_ALE
BF1 VSS_NCTF_13 TP17 N30
BF53 R152 *1K/J_4
VSS_NCTF_14 (10) NV_CLE
BH1 VSS_NCTF_15 TP18 H12
BH2 VSS_NCTF_16
BH52 VSS_NCTF_17 TP19 AA23 Danbury Technology Enabled
BH53 VSS_NCTF_18
B BJ1 VSS_NCTF_19 NC_1 AB45 High = Enable B
BJ2 VSS_NCTF_20
NV_ALE
BJ4 VSS_NCTF_21 NC_2 AB38 Low = Disable
BJ49 VSS_NCTF_22
BJ5 VSS_NCTF_23 NC_3 AB42
BJ50 VSS_NCTF_24
BJ52 VSS_NCTF_25 NC_4 AB41
BJ53 VSS_NCTF_26
D1 VSS_NCTF_27 NC_5 T39
D2 VSS_NCTF_28
D53 VSS_NCTF_29
E1 P6 T59
VSS_NCTF_30 INIT3_3V#
E53 VSS_NCTF_31
TP24 C10
IbexPeak-M_R1P0
+3V_RUN
R155 10K/J_4 GPIO35

R173 *1K/J_4 SWI# S_GPIO R419 10K/J_4 BMBUSY#:
If not used, require a weak pull-up (8.2- KΩ to 10 kΩ) to Vcc3_3.
R377 *1K/J_4 GNT3# (10) SV_SET_UP R163 10K/J_4 CRB(V1.0)P28: it has 1K PU and 100 ohm on this net for validation purpose.
A BMBUSY#:(Intel feedback) A
Follow CRB checklist, 1K is
for intel BIOS validation purpose.
A16 swap override Strap/Top-Block Integrated Clock Chip Enable
Swap Override jumper SV_SET_UP 1-X High = Strong (Default)
(Reserve to validate for future platforms)
Low = A16 swap Quanta Computer Inc.
override/Top-Block Enable when sampled low
GNT3# Swap Override enabled RSV_WOL_EN Disable when sampled high PROJECT : FH2A
High = Default (GPIO8)
1A
IBEX PEAK-M 4/6
5 4 3 2 1
5 4 3 2 1
IBEX PEAK-M (POWER) +1.05V_PCH

VCCCORE=1.524A max
AB24
AB26
AB28
U31G
VCCCORE[1]
VCCCORE[2]
POWER
VCCADAC[1] AE50
AE52
+VCCA_DAC_1_2
L40
HCB1608KF-181T15
+3V_RUN VCCADAC = 100mA max
12
C260 C295 VCCCORE[3] VCCADAC[2]
AD26 VCCCORE[4]
CRT
10U/10V_8 AD28 AF53
10 1U/6.3V_4 VCCCORE[5] VSSA_DAC[1]
AF26 VCCCORE[6]
VCC CORE
AF28 VCCCORE[7] VSSA_DAC[2] AF51
AF30
AF31
VCCCORE[8]
VCCCORE[9]
U31J POWER
AH26 VCCCORE[10]
D AH28 T77 VCCACLK AP51 V24 VCCIO = 3.208A max D
VCCCORE[11] VCCACLK[1] VCCIO[5] +1.05V_PCH
AH30 VCCCORE[12] VCCIO[6] V26
AH31 AH38 AP53 Y24 C278
VCCCORE[13] VCCALVDS VCCACLK[2] VCCIO[7] 1U/6.3V_4
AJ30 VCCCORE[14] VCCIO[8] Y26
AJ31 VCCCORE[15] VSSA_LVDS AH39
VCCTX_LVDS = 0.066A max AF23 VCCLAN[1] VCCSUS3_3[1] V28 +3V_S5 VCCSUS3_3 = 0.163A max
VCCSUS3_3[2] U28
VCCTX_LVDS[1] AP43 AF24 VCCLAN[2] VCCSUS3_3[3] U26
AP45 U24 C281 C279
VCCTX_LVDS[2] VCCSUS3_3[4]
AT46 P28
LVDS
VCCTX_LVDS[3] DCPSUSBYP VCCSUS3_3[5] 0.1U/16V_4 0.1U/16V_4
+1.05V_PCH AK24 VCCIO[24] VCCTX_LVDS[4] AT45 Y20 DCPSUSBYP VCCSUS3_3[6] P26
VCCAPLLEXP = 100mA max VCCSUS3_3[7] N28
C297 N26
T86 +1.05V_LAN_VCCAPLL_EXPBJ24 VCCSUS3_3[8]
VCCAPLLEXP AD38 VCCME[1] VCCSUS3_3[9] M28
AB34 +3V_RUN VCC3_3 = 0.357A max 0.1U/16V_4 M26
VCC3_3[2] VCCSUS3_3[10]
VCCAPLLEXP: AD39 L28
USB
C252 VCCME[2] VCCSUS3_3[11]
This pin can be left as no connect in AN20 VCCIO[25] VCC3_3[3] AB35 VCCSUS3_3[12] L26
AN22 AD41 J28
HVCMOS
On-Die VR enabled mode (default). VCCIO[26] VCCME[3] VCCSUS3_3[13]
AN23 AD35 0.1U/16V_4 J26
VCCIO[27] VCC3_3[4] VCCSUS3_3[14]
AN24 VCCIO[28] AF43 VCCME[4] VCCSUS3_3[15] H28
+1.05V_PCH AN26 H26
VCCIO[29] VCCSUS3_3[16]
AN28 VCCIO[30] AF41 VCCME[5] VCCSUS3_3[17] G28
BJ26 VCCIO[31] VCCSUS3_3[18] G26
BJ28 VCCIO[32] AF42 VCCME[6] VCCSUS3_3[19] F28
C282 AT26 F26
10U/10V_8 C296 C271 C293 C285 VCCIO[33] VCCSUS3_3[20]
AT28 VCCIO[34] V39 VCCME[7] VCCSUS3_3[21] E28
Clock and Miscellaneous

VCCIO = 3.208A max 10 1U/6.3V_41U/6.3V_41U/6.3V_41U/6.3V_4 AU26 E26
805 VCCIO[35] VCCSUS3_3[22]
AU28 VCCIO[36] +1.05V_PCH V41 VCCME[8] VCCSUS3_3[23] C28
AV26 VCCIO[37]
VCCVRM = 0.035A max VCCSUS3_3[24] C26
AV28 AT24 +1.8V_RUN C601 C245 C253 V42 B27
VCCIO[38] VCCVRM[2] VCCME[9] VCCSUS3_3[25]
AW26 VCCIO[39] VCCSUS3_3[26] A28
AW28 VCCDMI = 0.061A max 22U/6.3V_8 22U/6.3V_8 1U/6.3V_4 Y39 A26
VCCIO[40] VCCME[10] VCCSUS3_3[27]
DMI
C BA26 AT16 R144 C
VCCIO[41] VCCDMI[1] +1.05V_VTT
BA28 *0_4_SHORT Y41 U23
VCCIO[42] R141 *0/J_4 VCCME[11] VCCSUS3_3[28]
BB26 VCCIO[43] VCCDMI[2] AU16 +1.05V_PCH
BB28 VCCIO[44] Y42 VCCME[12] VCCIO[56] V23 +1.05V_PCH VCCIO = 3.208A max
BC26 C304
VCCIO[45]
PCI E*
BC28 1U/6.3V_4 F24 +V5REF_SUS R137 1 2 100/J_4 +5V_S5
VCCIO[46] V5REF_SUS
BD26 VCCIO[47]
V5REF_SUS>1mA
BD28 C317 0.1U/16V_4 DCPRTC V9 C294 D4 1 2 SDM10K45-7-F +3V_S5
VCCIO[48] DCPRTC 1U/6.3V_4
BE26 VCCIO[49] VCCPNAND[1] AM16
BE28 VCCIO[50] VCCPNAND[2] AK16
+3V_RUN BG26 AK20 VCCPNAND = 0.156A max K49 +V5REF R108 1 2 100/J_4 V5REF>1mA
VCCIO[51] VCCPNAND[3] V5REF +5V_RUN
BG28 AK19 AU24
PCI/GPIO/LPC
VCCIO[52] VCCPNAND[4] +1.8V_RUN +1.8V_RUN VCCVRM[3]
VCC3_3 = 0.357A max BH27 AK15 D3 1 2 SDM10K45-7-F +3V_RUN
VCCIO[53] VCCPNAND[5] C300 C238
VCCPNAND[6] AK13 VCCADPLLA = 0.072A max VCC3_3[8] J38
AN30 AM12 BB51 1U/6.3V_4
VCCIO[54] VCCPNAND[7] VCCADPLLA[1]
NAND / SPI
AN31 AM13 0.1U/16V_4 +1.1V_VCCADPLLA BB53 L38
C255 VCCIO[55] VCCPNAND[8] VCCADPLLA[2] VCC3_3[9]
VCCPNAND[9] AM15 VCCADPLLB = 0.073A max
0.1U/16V_4 VCC3_3[10] M36 +3V_RUN VCC3_3 = 0.357A max
AN35 +1.1V_VCCADPLLB BD51
VCC3_3[1] VCCADPLLB[1]
BD53 VCCADPLLB[2] VCC3_3[11] N36
VCCVRM = 0.035A max VCCIO = 3.208A max C266
VCCFDIPLL = 100mA max +1.8V_RUN AT22 +1.05V_PCH AH23 P36 0.1U/16V_4
VCCVRM[1] VCCIO[21] VCC3_3[12]
AJ35 VCCIO[22]
T87 +1.05V_VCCFDIPLL BJ18 AM8 VCCME3_3 = 0.085A max C284 C269 C305 AH35 U35
VCCFDIPLL VCCME3_3[1] VCCIO[23] VCC3_3[13]
VCCME3_3[2] AM9 +3V_RUN
FDI
+1.05V_PCH AM23 AP11 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 AF34

VCCIO[1] VCCME3_3[3] C265 VCCIO[2]
VCCME3_3[4] AP9 VCC3_3[14] AD13
AH34 VCCIO[3]
VCCIO = 3.208A max 0.1U/16V_4 C314
AF32 0.1U/16V_4
IbexPeak-M_R1P0 VCCIO[4]
VCCSATAPLL[1] AK3
C315 0.1U/16V_4 DCPSST V12 AK1 +1.05V_VCCSATAPLL
B VCCME3_3: DCPSST VCCSATAPLL[2] T88 B
EDS(V1.0)P84:supply for the Intel Management Engine.This is a separate power plane
that may or may not be powered in S3–S5 states. VCCIO = 3.208A max
This plane must be on in S0 C302 0.1U/16V_4 DCPSUS Y22
and other times the Intel Management Engine is used. DCPSUS
VCCIO[9] AH22 +1.05V_PCH
VCCVRM = 0.035A max
P18 AT20 +1.8V_RUN C272
VCCSUS3_3[29] VCCVRM[4] 1U/6.3V_4
VCCSUS3_3 = 0.163A max
+3V_S5 U19
SATA
VCCSUS3_3[30]
PCI/GPIO/LPC
VCCIO[10] AH19
C280 U20 VCCSUS3_3[31]
VCCIO[11] AD20
0.1U/16V_4 U22 VCCSUS3_3[32]
VCCIO[12] AF22
VCC3_3 = 0.357A max VCCIO[13] AD19

PCH EDS(V1.0) P84 +3V_RUN V15 VCC3_3[5] VCCIO[14] AF20
+NVRAM_VCCQ: VCCIO[15] AF19
1.8 V supply for Dual Channel NAND interface. C254 V16 AH20
VCC3_3[6] VCCIO[16]
This power is supplied by core 0.1U/16V_4 Y16 VCC3_3[7] VCCIO[17] AB19
well. If unused, this pin should AB20
be connected to Vcc3_3. VCCIO[18]
VCCIO[19] AB22
V_CPU>1mA VCCIO[20] AD22
+1.05V_VTT AT18 V_CPU_IO[1]
L27 10uH +1.1V_VCCADPLLA AA34 VCCME = 1.998A max
CPU
+1.05V_PCH VCCME[13] +1.05V_PCH
C308 C307 C306 Y34
VCCME[14]
AU18 V_CPU_IO[2] VCCME[15] Y35
+ C240 C239 4.7U/25V_8 0.1U/16V_4
0.1U/16V_4 AA35
VCCME[16]
*220U/2.5V_3528 3528 1U/6.3V_4
RTC
A A12 L30 0/J_4 R132 VCCSUSHDA = 6mA max A
+VCC_RTC VCCRTC VCCSUSHDA +3V_S5
HDA
C623 C624
C622 IbexPeak-M_R1P0 C267
L39 10uH +1.1V_VCCADPLLB 1U/6.3V_40.1U/16V_4
0.1U/16V_4 1U/6.3V_4
VCCRTC = 2mA max

+ C585 Quanta Computer Inc.
C587 C61 is required close the PCH ball
*220U/2.5V_3528 3528 1U/6.3V_4
PROJECT : FH2
1A
IBEX PEAK-M 5/6
5 4 3 2 1
5 4 3 2 1
13
U31I
AY7 H49
IBEX PEAK-M (GND) B11
B15
VSS[159]
VSS[160]
VSS[259]
VSS[260] H5
J24
VSS[161] VSS[261]
D B19 VSS[162] VSS[262] K11 D
B23 VSS[163] VSS[263] K43
B31 VSS[164] VSS[264] K47
B35 VSS[165] VSS[265] K7
B39 VSS[166] VSS[266] L14
B43 VSS[167] VSS[267] L18
B47 VSS[168] VSS[268] L2
B7 VSS[169] VSS[269] L22
BG12 VSS[170] VSS[270] L32
BB12 VSS[171] VSS[271] L36
U31H BB16 L40
VSS[172] VSS[272]
AB16 VSS[0] BB20 VSS[173] VSS[273] L52
BB24 VSS[174] VSS[274] M12
AA19 VSS[1] VSS[80] AK30 BB30 VSS[175] VSS[275] M16
AA22 VSS[3] VSS[82] AK32 BB38 VSS[177] VSS[277] N38
AM19 VSS[4] VSS[83] AK34 BB42 VSS[178] VSS[278] M34
AA28 VSS[7] VSS[86] AK43 BC10 VSS[181] VSS[281] M46
AB11 VSS[11] VSS[90] AK8 BC22 VSS[185] VSS[285] N24
AB15 VSS[12] VSS[91] AL2 BC32 VSS[186] VSS[286] P11
AB23 VSS[13] VSS[92] AL52 BC36 VSS[187] VSS[287] AD15
AB30 VSS[14] VSS[93] AM11 BC40 VSS[188] VSS[288] P22
AB31 VSS[15] VSS[94] BB44 BC44 VSS[189] VSS[289] P30
AB32 VSS[16] VSS[95] AD24 BC52 VSS[190] VSS[290] P32
AB39 VSS[17] VSS[96] AM20 BH9 VSS[191] VSS[291] P34
AB43 VSS[18] VSS[97] AM22 BD48 VSS[192] VSS[292] P42
C C
AB8 VSS[21] VSS[100] AM28 BE12 VSS[195] VSS[295] R2
AC2 VSS[22] VSS[101] BA42 BE16 VSS[196] VSS[296] R52
AC52 VSS[23] VSS[102] AM30 BE20 VSS[197] VSS[297] T12
AD11 VSS[24] VSS[103] AM31 BE24 VSS[198] VSS[298] T41
AD31 VSS[29] VSS[108] AM39 BE46 VSS[203] VSS[303] U30
AD32 VSS[30] VSS[109] AM42 BE48 VSS[204] VSS[304] U31
AD34 VSS[31] VSS[110] AU20 BE50 VSS[205] VSS[305] U32
AU22 VSS[32] VSS[111] AM46 BE6 VSS[206] VSS[306] U34
AD42 VSS[33] VSS[112] AV22 BE8 VSS[207] VSS[307] P38
AD46 VSS[34] VSS[113] AM49 BF3 VSS[208] VSS[308] V11
AD49 VSS[35] VSS[114] AM7 BF49 VSS[209] VSS[309] P16
AD7 VSS[36] VSS[115] AA50 BF51 VSS[210] VSS[310] V19
AE2 VSS[37] VSS[116] BB10 BG18 VSS[211] VSS[311] V20
AE4 VSS[38] VSS[117] AN32 BG24 VSS[212] VSS[312] V22
AF12 VSS[39] VSS[118] AN50 BG4 VSS[213] VSS[313] V30
Y13 VSS[40] VSS[119] AN52 BG50 VSS[214] VSS[314] V31
AH49 VSS[41] VSS[120] AP12 BH11 VSS[215] VSS[315] V32
AU4 VSS[42] VSS[121] AP42 BH15 VSS[216] VSS[316] V34
AF35 VSS[43] VSS[122] AP46 BH19 VSS[217] VSS[317] V35
AP13 VSS[44] VSS[123] AP49 BH23 VSS[218] VSS[318] V38
AN34 VSS[45] VSS[124] AP5 BH31 VSS[219] VSS[319] V43
AF45 VSS[46] VSS[125] AP8 BH35 VSS[220] VSS[320] V45
AF46 VSS[47] VSS[126] AR2 BH39 VSS[221] VSS[321] V46
AF49 VSS[48] VSS[127] AR52 BH43 VSS[222] VSS[322] V47
AF5 VSS[49] VSS[128] AT11 BH47 VSS[223] VSS[323] V49
AF8 VSS[50] VSS[129] BA12 BH7 VSS[224] VSS[324] V5
B AG2 AH48 C12 V7 B
VSS[51] VSS[130] VSS[225] VSS[325]
AG52 VSS[52] VSS[131] AT32 C50 VSS[226] VSS[326] V8
AH11 VSS[53] VSS[132] AT36 D51 VSS[227] VSS[327] W2
AH15 VSS[54] VSS[133] AT41 E12 VSS[228] VSS[328] W52
AH16 VSS[55] VSS[134] AT47 E16 VSS[229] VSS[329] Y11
AH24 VSS[56] VSS[135] AT7 E20 VSS[230] VSS[330] Y12
AH32 VSS[57] VSS[136] AV12 E24 VSS[231] VSS[331] Y15
AV18 VSS[58] VSS[137] AV16 E30 VSS[232] VSS[332] Y19
AJ19 VSS[62] VSS[141] AV34 E46 VSS[236] VSS[336] Y31
AJ23 VSS[66] VSS[145] AV49 F49 VSS[240] VSS[340] Y46
AJ26 VSS[67] VSS[146] AV5 F5 VSS[241] VSS[341] P49
AJ28 VSS[68] VSS[147] AV8 G10 VSS[242] VSS[342] Y5
AJ32 VSS[69] VSS[148] AW14 G14 VSS[243] VSS[343] Y6
AJ34 VSS[70] VSS[149] AW18 G18 VSS[244] VSS[344] Y8
AT5 VSS[71] VSS[150] AW2 G2 VSS[245] VSS[345] P24
AJ4 VSS[72] VSS[151] BF9 G22 VSS[246] VSS[346] T43
AK12 VSS[73] VSS[152] AW32 G32 VSS[247] VSS[347] AD51
AM41 VSS[74] VSS[153] AW36 G36 VSS[248] VSS[348] AT8
AN19 VSS[75] VSS[154] AW40 G40 VSS[249] VSS[349] AD47
AK26 VSS[76] VSS[155] AW52 G44 VSS[250] VSS[350] Y47
AK22 VSS[77] VSS[156] AY11 G52 VSS[251] VSS[351] AT12
AK23 VSS[78] VSS[157] AY43 AF39 VSS[252] VSS[352] AM6
AK28 VSS[79] VSS[158] AY47 H16 VSS[253] VSS[353] AT13
H20 VSS[254] VSS[354] AM5
IbexPeak-M_R1P0 H30 AK45
VSS[255] VSS[355]
A H34 VSS[256] VSS[356] AK39 A
AJSLGZS0T05 H38 VSS[257] VSS[366] AV14
H42 VSS[258]
IbexPeak-M_R1P0
AJSLGZS0T05
PROJECT : FH2A
1A
IBEX PEAK-M 6/6
5 4 3 2 1
5 4 3 2 1
(5) M_A_A[15:0]
M_A_A0
M_A_A1
M_A_A2
M_A_A3
98
97
96
JDIM1A
A0
A1
A2
DQ0
DQ1
DQ2
5
7
15
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ[63:0] (5)
+1.5V_SUS
75
76
81
JDIM1B
VDD1
VDD2
VDD3
VSS16
VSS17
VSS18
44
48
49
14
95 A3 DQ3 17 82 VDD4 VSS19 54
M_A_A4 92 4 M_A_DQ4 87 55
+3V_RUN M_A_A5 A4 DQ4 M_A_DQ5 VDD5 VSS20
91 A5 DQ5 6 88 VDD6 VSS21 60
M_A_A6 90 16 M_A_DQ6 93 61
M_A_A7 A6 DQ6 M_A_DQ7 VDD7 VSS22
86 A7 DQ7 18 94 VDD8 VSS23 65
M_A_A8 89 21 M_A_DQ8 99 66
D
85 A9 DQ9 23 100 VDD10 VSS25 71 D
PC2100 DDR3 SDRAM SO-DIMM

M_A_A10 107 33 M_A_DQ10 105 72
R220 R221 M_A_A11 A10/AP DQ10 M_A_DQ11 VDD11 VSS26
84 A11 DQ11 35 106 VDD12 VSS27 127
*10K *10K M_A_A12 83 22 M_A_DQ12 111 128
M_A_A13 A12/BC# DQ12 M_A_DQ13 VDD13 VSS28
119 A13 DQ13 24 112 VDD14 VSS29 133
SMbus address A0 M_A_A14 80 34 M_A_DQ14 117 134

78 A15 DQ15 36 118 VDD16 VSS31 138
M_A_DQ16
DIMM0_SA1
DIMM0_SA0
DQ16 39 123 VDD17 VSS32 139

109 41 M_A_DQ17 124 144
(5) M_A_BS0 BA0 DQ17 VDD18 VSS33
108 51 M_A_DQ18 145 Intel is requesting that customers implement
(5) M_A_BS1 BA1 DQ18 VSS34 all methods (M1 and M2 and M3
79 53 M_A_DQ19 199 150
(5) M_A_BS2 BA2 DQ19 +3V_RUN VDDSPD VSS35 described below) to generate and control
114 40 M_A_DQ20 151
(5) M_A_CS0# S0# DQ20 VSS36 Reference voltage for Data/Strobe inputs
121 42 M_A_DQ21 77 155
(5) M_A_CS1# S1# DQ21 NC1 VSS37 (VREFDQ) on Clarksfield based platforms.
101 50 M_A_DQ22 122 156
(5) M_A_CLKP0 CK0 DQ22 NC2 VSS38 for fine tuning of the VREFDQ levels to
R224 R225 103 52 M_A_DQ23 125 161
(5) M_A_CLKN0 CK0# DQ23 NCTEST VSS39 optimize the voltage and timing margins.
10K 10K 102 57 M_A_DQ24 162
(5) M_A_CLKP1 CK1 DQ24 VSS40
104 59 M_A_DQ25 PM_EXTTS#0 198 167
(5) M_A_CLKN1 CK1# DQ25 (4) PM_EXTTS#0 EVENT# VSS41 M1:Fixed voltage resistor divider or
73 67 M_A_DQ26 30 168
(5) M_A_CKE0 CKE0 DQ26 (4,15) DDR3_DRAMRST# RESET# VSS42 DDR Voltage Regulator drives the Vref
74 69 M_A_DQ27 172
(5) M_A_CKE1 CKE1 DQ27 VSS43 M2:A set of Digital potentiometers
115 56 M_A_DQ28 173
(5) M_A_CAS# CAS# DQ28 VSS44 and op amps are added on the motherboard (one pair
110 58 M_A_DQ29 1 178
(5) M_A_RAS# RAS# DQ29 +SMDDR_VREF_DQ0 VREF_DQ VSS45 for each channel). This circuit is controlled by
113 68 M_A_DQ30 126 179
(5) M_A_WE# WE# DQ30 +SMDDR_VREF_DIMM0 VREF_CA VSS46 SMBUS (SMB_CLK & SMB_DATA) on PCH.
DIMM0_SA0 197 70 M_A_DQ31 184
SA0 DQ31 VSS47 M3:Intel investigating future processor
DIMM0_SA1 201 129 M_A_DQ32 185 VREF_DQ generation to replace M1 and M2. This
CGCLK_SMB SA1 DQ32 M_A_DQ33 VSS48
(3,10,15) CGCLK_SMB 202 SCL DQ33 131 2 VSS1 VSS49 189 would require routing processor signal balls
CGDAT_SMB 200 141 M_A_DQ34 3 190 J17 and H17 to SO-DIMM connectors
(3,10,15) CGDAT_SMB SDA DQ34 VSS2 VSS50
(204P)
143 M_A_DQ35 8 195 directly.
DQ35 M_A_DQ36 +1.5V_SUS +DDR_VTTREF VSS3 VSS51
(5) M_A_ODT0 116 ODT0 DQ36 130 9 VSS4 VSS52 196
CGCLK_SMB 120 132 M_A_DQ37 13
(5) M_A_ODT1 ODT1 DQ37 VSS5
140 M_A_DQ38 14
(5) M_A_DM[7:0] DQ38 VSS6
C CGDAT_SMB M_A_DM0 11 142 M_A_DQ39 19 C
M_A_DM1 DM0 DQ39 M_A_DQ40 R211 R217 VSS7
28 DM1 DQ40 147 20 VSS8
(204P)
C361 M_A_DM2 46 149 M_A_DQ41 1K/J_4 *0/J_4 +SMDDR_VREF_DIMM0 25
C359 M_A_DM3 DM2 DQ41 M_A_DQ42 VSS9
63 DM3 DQ42 157 26 VSS10 VTT1 203 +0.75V_DDR_VTT
*33P/50V_4 *33P/50V_4 M_A_DM4 136 159 M_A_DQ43 31 204
M_A_DM5 DM4 DQ43 M_A_DQ44 VSS11 VTT2
153 DM5 DQ44 146 32 VSS12
M_A_DM6 170 148 M_A_DQ45 37 G1
M_A_DM7 DM6 DQ45 M_A_DQ46 VSS13 G1
187 DM7 DQ46 158 38 VSS14 G2 G2
1
160 M_A_DQ47 R216 43
(5) M_A_DQSP[7:0] DQ47 VSS15
M_A_DQSP0 12 163 M_A_DQ48 1K/J_4 C373
M_A_DQSP1 DQS0 DQ48 M_A_DQ49
29 165 0.1U/16V_4
2
47 DQS2 DQ50 175 16 2-2013311-1
M_A_DQSP3 64 177 M_A_DQ51
137 DQS4 DQ52 164
M_A_DQSP5 154 166 M_A_DQ53
171 DQS6 DQ54 174
M_A_DQSP7 188 176 M_A_DQ55
(5) M_A_DQSN[7:0] DQS7 DQ55
M_A_DQSN0 10 181 M_A_DQ56
M_A_DQSN1 DQS#0 DQ56 M_A_DQ57
27 DQS#1 DQ57 183
M_A_DQSN2 45 191 M_A_DQ58
62 DQS#3 DQ59 193
M_A_DQSN4 135 180 M_A_DQ60
152 DQS#5 DQ61 182
M_A_DQSN6 169 192 M_A_DQ62
186 DQS#7 DQ63 194
2-2013311-1
B B
ddr-600025fb204g108zl-204p-ruv
+1.5V_SUS
Place these Caps near So-Dimm1. +SMDDR_VREF_DIMM0 +SMDDR_VREF_DQ0
C356 C357 C378 C353 C376 C380 C375
10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 0.1U/10V_4 0.1U/10V_4 2.2U/6.3V_6 2.2U/6.3V_6
C379 + C430 C372 C371

10U/6.3V_6 *330U/2.5V_7343 0.1U/16V_4 +1.5V_SUS +DDR_VTTREF M1 VREF
7343 0.1U/16V_4
2.5
C370 C381 C377 C354 C355
10U/6.3V_6 10U/6.3V_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 R214 R222
1K/J_4 *0/J_6
+SMDDR_VREF_DQ0
+3V_RUN +0.75V_DDR_VTT R219 0_S

1
R218
C364 C365 C351 C348 C349 C350 C347 1K/J_4 C374
10U/10V_8 0.1U/16V_4
2
2.2U/6.3V_6 0.1U/16V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 10 16

805
A A

PROJECT : FH2A
1A
DDR3 DIMM-1
5 4 3 2 1
5 4 3 2 1
(5) M_B_A[15:0]
M_B_A0
M_B_A1
M_B_A2
M_B_A3
98
97
96
JDIM2A
A0
A1
A2
DQ0
DQ1
DQ2
5
7
15
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ[63:0] (5)
+1.5V_SUS
75
76
81
82
JDIM2B
VDD1
VDD2
VDD3
VDD4
VSS16
VSS17
VSS18
VSS19
44
48
49
54
15
95 A3 DQ3 17 87 VDD5 VSS20 55
M_B_A4 92 4 M_B_DQ4 88 60
M_B_A5 A4 DQ4 M_B_DQ5 VDD6 VSS21
91 A5 DQ5 6 93 VDD7 VSS22 61
M_B_A6 90 16 M_B_DQ6 94 65
86 A7 DQ7 18 99 VDD9 VSS24 66
M_B_A8 89 21 M_B_DQ8 100 71
A8 DQ8 VDD10 VSS25

M_B_A9 85 23 M_B_DQ9 105 72
D
M_B_A10 A9 DQ9 M_B_DQ10 VDD11 VSS26 D
107 A10/AP DQ10 33 106 VDD12 VSS27 127
M_B_A11 84 35 M_B_DQ11 111 128
83 A12/BC# DQ12 22 112 VDD14 VSS29 133
+3V_RUN M_B_A13 119 24 M_B_DQ13 117 134
SMbus address A4 M_B_A15
80 A14 DQ14 34
M_B_DQ15
118 VDD16 VSS31 138

78 A15 DQ15 36 123 VDD17 VSS32 139
39 M_B_DQ16 124 144
DQ16 M_B_DQ17 VDD18 VSS33
(5) M_B_BS0 109 BA0 DQ17 41 VSS34 145
108 51 M_B_DQ18 199 150
(5) M_B_BS1 BA1 DQ18 VDDSPD VSS35
R231 R232 79 53 M_B_DQ19 151
(5) M_B_BS2 BA2 DQ19 +3V_RUN VSS36
10K *10K 114 40 M_B_DQ20 77 155
(5) M_B_CS0# S0# DQ20 NC1 VSS37
121 42 M_B_DQ21 122 156
(5) M_B_CS1# S1# DQ21 NC2 VSS38
101 50 M_B_DQ22 125 161
(5) M_B_CLKP0 CK0 DQ22 NCTEST VSS39
103 52 M_B_DQ23 162
(5) M_B_CLKN0 CK0# DQ23 VSS40
M_B_DQ24 PM_EXTTS#1
DIMM1_SA1
DIMM1_SA0
(5) M_B_CLKP1 102 CK1 DQ24 57 (4) PM_EXTTS#1 198 EVENT# VSS41 167
104 59 M_B_DQ25 30 168
(5) M_B_CLKN1 CK1# DQ25 (4,14) DDR3_DRAMRST# RESET# VSS42
73 67 M_B_DQ26 172
(5) M_B_CKE0 CKE0 DQ26 VSS43
74 69 M_B_DQ27 173
(5) M_B_CKE1 CKE1 DQ27 VSS44
115 56 M_B_DQ28 1 178
(5) M_B_CAS# CAS# DQ28 VREF_DQ VSS45
110 58 M_B_DQ29 126 179
(5) M_B_RAS# RAS# DQ29 +SMDDR_VREF_DQ1 VREF_CA VSS46
113 68 M_B_DQ30 184
(5) M_B_WE# WE# DQ30 +SMDDR_VREF_DIMM1 VSS47
R240 R241 DIMM1_SA0 197 70 M_B_DQ31 185
*10K 10K DIMM1_SA1 SA0 DQ31 M_B_DQ32 VSS48
201 SA1 DQ32 129 2 VSS1 VSS49 189
CGCLK_SMB 202 131 M_B_DQ33 3 190
(3,10,14) CGCLK_SMB SCL DQ33 VSS2 VSS50
(204P)
CGDAT_SMB 200 141 M_B_DQ34 8 195
(3,10,14) CGDAT_SMB SDA DQ34 +1.5V_SUS +DDR_VTTREF VSS3 VSS51
143 M_B_DQ35 9 196
DQ35 M_B_DQ36 VSS4 VSS52
(5) M_B_ODT0 116 ODT0 DQ36 130 13 VSS5
120 132 M_B_DQ37 14
(5) M_B_ODT1 ODT1 DQ37 VSS6
140 M_B_DQ38 19
(5) M_B_DM[7:0] DQ38 VSS7
C M_B_DM0 11 142 M_B_DQ39 20 C
CGCLK_SMB M_B_DM1 DM0 DQ39 M_B_DQ40 R237 R239 VSS8
28 DM1 DQ40 147 25 VSS9
CGDAT_SMB
M_B_DM2
M_B_DM3
46
63
DM2
DM3
(204P) DQ41
DQ42
149
157
M_B_DQ41
M_B_DQ42
1K/J_4 *0/J_4
+SMDDR_VREF_DIMM1
26
31
VSS10
VSS11
VTT1
VTT2
203
204 +0.75V_DDR_VTT
M_B_DM4 136 159 M_B_DQ43 32
C398 M_B_DM5 DM4 DQ43 M_B_DQ44 VSS12
153 DM5 DQ44 146 37 VSS13 G1 G1
C397 M_B_DM6 170 148 M_B_DQ45 38 G2
*33P/50V_4 M_B_DM7 DM6 DQ45 M_B_DQ46 VSS14 G2
*33P/50V_4 187 DM7 DQ46 158 43 VSS15
1
160 M_B_DQ47 R236
(5) M_B_DQSP[7:0] DQ47
M_B_DQSP0 12 163 M_B_DQ48 1K/J_4 C417
M_B_DQSP1 DQS0 DQ48 M_B_DQ49 0.1U/16V_4
29 165 2-2013290-1
2
M_B_DQSP2 DQS1 DQ49 M_B_DQ50 16
47 DQS2 DQ50 175
M_B_DQSP3 64 177 M_B_DQ51
M_B_DQSP4 DQS3 DQ51 M_B_DQ52
137 DQS4 DQ52 164
M_B_DQSP5 154 166 M_B_DQ53
M_B_DQSP6 DQS5 DQ53 M_B_DQ54
171 DQS6 DQ54 174
M_B_DQSP7 188 176 M_B_DQ55
(5) M_B_DQSN[7:0] DQS7 DQ55
M_B_DQSN0 10 181 M_B_DQ56
M_B_DQSN1 DQS#0 DQ56 M_B_DQ57
27 DQS#1 DQ57 183
M_B_DQSN2 45 191 M_B_DQ58
62 DQS#3 DQ59 193
M_B_DQSN4 135 180 M_B_DQ60
152 DQS#5 DQ61 182
M_B_DQSN6 169 192 M_B_DQ62
186 DQS#7 DQ63 194
2-2013290-1
B B
ddr-600025fb204g103zl-204p-ruv
+1.5V_SUS
Place these Caps near So-Dimm2. +SMDDR_VREF_DIMM1 +SMDDR_VREF_DQ1
C392 C404 C403 C393 C394 C416 C410
10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 0.1U/16V_4 0.1U/16V_4 2.2U/6.3V_6 2.2U/6.3V_6
+1.5V_SUS +DDR_VTTREF M1 VREF
C406 + C419 C418
10U/6.3V_6 *330U/2.5V_7343 C411
7343 0.1U/16V_4 0.1U/16V_4
2.5 R238 R235
C407 C395 C405 C408 C391 1K/J_4 *0/J_6
10U/6.3V_6 10U/6.3V_6 0.1U/16V_4 0.1U/16V_4 0.1U/16V_4 +SMDDR_VREF_DQ1
R228 0_S
+3V_RUN +0.75V_DDR_VTT
1
R233
1K/J_4 C412
C401 C402 C389 C388 C387 C390 C386 0.1U/16V_4
2
10U/10V_8 16
2.2U/6.3V_6 0.1U/16V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 10
805
A A

PROJECT : FH2A
1A
DDR3 DIMM-2
5 4 3 2 1
5 4 3 2 1
16
(17,18,19,40) +1V_GPU
U26A
D (4) PEG_TX0 PEG_TX0 AA38 Y33 PEG_RXP0_C C117 0.1U/10V_4 D

PCIE_RX0P PCIE_TX0P PEG_RX0 (4)
(4) PEG_TX#0 PEG_TX#0 Y37 Y32 PEG_RXN0_C C125 0.1U/10V_4
PCIE_RX0N PCIE_TX0N PEG_RX#0 (4)
(4) PEG_TX1 PEG_TX1 Y35 W33 PEG_RXP1_C C100 0.1U/10V_4

(4) PEG_TX#1 PEG_TX#1 W36 W32 PEG_RXN1_C C93 0.1U/10V_4
(4) PEG_TX2 PEG_TX2 W38 U33 PEG_RXP2_C C131 0.1U/10V_4

(4) PEG_TX#2 PEG_TX#2 V37 U32 PEG_RXN2_C C144 0.1U/10V_4
(4) PEG_TX3 PEG_TX3 V35 U30 PEG_RXP3_C C124 0.1U/10V_4

(4) PEG_TX#3 PEG_TX#3 U36 U29 PEG_RXN3_C C116 0.1U/10V_4
(4) PEG_TX4 PEG_TX4 U38 T33 PEG_RXP4_C C154 0.1U/10V_4

(4) PEG_TX#4 PEG_TX#4 T37 T32 PEG_RXN4_C C163 0.1U/10V_4
PCI EXPRESS INTERFACE

(4) PEG_TX5 PEG_TX5 T35 T30 PEG_RXP5_C C134 0.1U/10V_4
(4) PEG_TX#5 PEG_TX#5 R36 T29 PEG_RXN5_C C146 0.1U/10V_4
(4) PEG_TX6 PEG_TX6 R38 P33 PEG_RXP6_C C173 0.1U/10V_4

C PCIE_RX6P PCIE_TX6P PEG_RX6 (4) C
(4) PEG_TX#6 PEG_TX#6 P37 P32 PEG_RXN6_C C181 0.1U/10V_4
(4) PEG_TX7 PEG_TX7 P35 P30 PEG_RXP7_C C162 0.1U/10V_4

(4) PEG_TX#7 PEG_TX#7 N36 P29 PEG_RXN7_C C169 0.1U/10V_4
(4) PEG_TX8 PEG_TX8 N38 N33 PEG_RXP8_C C186 0.1U/10V_4

(4) PEG_TX#8 PEG_TX#8 M37 N32 PEG_RXN8_C C193 0.1U/10V_4
(4) PEG_TX9 PEG_TX9 M35 N30 PEG_RXP9_C C178 0.1U/10V_4

(4) PEG_TX#9 PEG_TX#9 L36 N29 PEG_RXN9_C C183 0.1U/10V_4
(4) PEG_TX10 PEG_TX10 L38 L33 PEG_RXP10_C C195 0.1U/10V_4

(4) PEG_TX#10 PEG_TX#10 K37 L32 PEG_RXN10_C C198 0.1U/10V_4
(4) PEG_TX11 PEG_TX11 K35 L30 PEG_RXP11_C C194 0.1U/10V_4

(4) PEG_TX#11 PEG_TX#11 J36 L29 PEG_RXN11_C C191 0.1U/10V_4
(4) PEG_TX12 PEG_TX12 J38 K33 PEG_RXP12_C C204 0.1U/10V_4

B (4) PEG_TX#12 PEG_TX#12 H37 K32 PEG_RXN12_C C207 0.1U/10V_4 B
(4) PEG_TX13 PEG_TX13 H35 J33 PEG_RXP13_C C206 0.1U/10V_4

(4) PEG_TX#13 PEG_TX#13 G36 J32 PEG_RXN13_C C209 0.1U/10V_4
(4) PEG_TX14 PEG_TX14 G38 K30 PEG_RXP14_C C197 0.1U/10V_4

(4) PEG_TX#14 PEG_TX#14 F37 K29 PEG_RXN14_C C203 0.1U/10V_4
(4) PEG_TX15 PEG_TX15 F35 H33 PEG_RXP15_C C210 0.1U/10V_4

(4) PEG_TX#15 PEG_TX#15 E37 H32 PEG_RXN15_C C211 0.1U/10V_4
CLOCK
(10) CLK_PCIE_VGAP CLK_PCIE_VGAP AB35
CLK_PCIE_VGAN AA36 PCIE_REFCLKP
(10) CLK_PCIE_VGAN PCIE_REFCLKN
CALIBRATION
B AJ21 Y30 R60 1.27K/F_4

NC#1 PCIE_CALRP
AK21 NC#2
R12 MAD@10K/F_4AH16 Y29 R53 2K/F_4 +1V_GPU
A
CS31002FB26 PWRGOOD PCIE_CALRN A
(4,10,25,26,29,33) PLTRST# R49 0/F_4 AA30

PERSTB
1
F2 C711 Quanta Computer Inc.

*2200P/50V_4
Madison
2
PROJECT : FH2A
1A
Madison PCIE I/F
5 4 3 2 1
5 4 3 2 1
17
RAM_ RAM_ RAM_ RAM_
Memory Straps Msdison LP TYPE_CFG3 TYPE_CFG2 TYPE_CFG1 TYPE_CFG0 CONFIGURATION STRAPS
800 MHz 1GB(64M*16) Hynix_Orion die H5TQ1G63BFR-12C 0 0 0 0 ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
800 MHz 1GB(64M*16) Samsung_E die K4W1G1646E-HC12 0 0 0 1 U26B THEY MUST NOT CONFLICT DURING RESET
STRAPS Name DESCRIPTION OF DEFAULT SETTINGS

RAM_ RAM_ RAM_ RAM_ TXCAP_DPA3P AU24 EXT_HDMI_TXCP (24)
Memory Straps M96 LP AV23 TX_PWRS_ENB GPIO0 Transmitter Power Savings Enable
TYPE_CFG3 TYPE_CFG2 TYPE_CFG1 TYPE_CFG0 TXCAM_DPA3N EXT_HDMI_TXCN (24)
0: 50% Tx output swing for mobile mode
800 MHz 1GB(64M*16) Hynix_Orion die H5TQ1G63BFR-12C 0 0 1 0 AT25 EXT_HDMI_TXDP0 (24) 1: full Tx output swing (Default setting for Desktop)
MUTI GFX TX0P_DPA2P
TX0M_DPA2N AR24 EXT_HDMI_TXDN0 (24)
800 MHz 1GB(64M*16) Samsung_E die K4W1G1646E-HC12 0 0 1 1 DPA
AU26 EXT_HDMI_TXDP1 (24) TX_DEEMPH_EN GPIO1 PCI Express Transmitter De-emphasis Enable
TX1P_DPA1P 0: Tx de-emphasis disabled for mobile mode
RAM_ RAM_ RAM_ RAM_ TX1M_DPA1N AV25 EXT_HDMI_TXDN1 (24)
Memory Straps Caplinalo LP 1: Tx de-emphasis enabled (Default setting for Desktop)
TYPE_CFG3 TYPE_CFG2 TYPE_CFG1 TYPE_CFG0
AR8 DVPCNTL_MVP_0 TX2P_DPA0P AT27 EXT_HDMI_TXDP2 (24)
AU8 DVPCNTL_MVP_1 TX2M_DPA0N AR26 EXT_HDMI_TXDN2 (24)
800 MHz 1GB(64M*16) Hynix_Orion die H5TQ1G63BFR-12C 0 1 0 0 AP8 BIF_GEN2_EN_A GPIO2 0 = Advertises the PCI-E device as 2.5 GT/s capable at power-on.
D DVPCNTL_0 D
AW8 AR30 1 = Advertises the PCI-E device as 5.0 GT/s capable at power-on.
DVPCNTL_1 TXCBP_DPB3P Note:5.0 GT/s capability will be controlled by software.
800 MHz 1GB(64M*16) Samsung_E die K4W1G1646E-HC12 0 1 0 1 AR3 DVPCNTL_2 TXCBM_DPB3N AT29
AR1 DVPCLK
Note : Required Frequency = 800 MHz RAM_TYPE_CFG0 AU1 AV31
RAM_TYPE_CFG1 DVPDATA_0 TX3P_DPB2P BIF_VGA_DIS GPIO9 VGA Disable determines whether or not the card will
AU3 DVPDATA_1 TX3M_DPB2N AU30
RAM_TYPE_CFG2 AW3 DPB be recognized as the system's VGA controller
RAM_TYPE_CFG3 DVPDATA_2 0: VGA Controller capacity enabled
AP6 DVPDATA_3 TX4P_DPB1P AR32
AW5 AT31 1: The device will not be recognized as the system’s VGA controller
DVPDATA_4 TX4M_DPB1N
AU5 DVPDATA_5
AR6 DVPDATA_6 TX5P_DPB0P AT33
AW6 AU32 BIOS_ROM_EN GPIO22 ENABLE EXTERNAL BIOS ROM 1:enable 0:disable
DVPDATA_7 TX5M_DPB0N
AU6 DVPDATA_8
AT7 DVPDATA_9 TXCCP_DPC3P AU14
AV7 AV13 ROMIDCFG(2:0) GPIO[13:11] Primary Memory Aperture size requested
DVPDATA_10 TXCCM_DPC3N
AN7 DVPDATA_11
AV9 AT15 Size of the primary memory apertures CONFIG[2:0]
DVPDATA_12 TX0P_DPC2P 128 MB 000
AT9 DVPDATA_13 TX0M_DPC2N AR14
AR10 256 MB 001
DVPDATA_14 DPC 64 MB 010
AW10 DVPDATA_15 TX1P_DPC1P AU16
AU10 AV15 32 MB 011
DVPDATA_16 TX1M_DPC1N 512 MB Not Supported
AP10 DVPDATA_17
AV11 AT17 Note:For frame buffers larger than 256 MB (e.g. 512 MB, 1 GB) the aperture
+1.8V_GPU +AVDD DVPDATA_18 TX2P_DPC0P size should be 256 MB.
(1.8V @ 70mA AVDD) AT11 DVPDATA_19 TX2M_DPC0N AR16
AR12 DVPDATA_20 !!! NC when M92-M2
L21 BLM15BD121SN1D AW12 AU20
DVPDATA_21 TXCDP_DPD3P VIP_DEVICE_STRAP_ENA DAC2_VSY IGNORE VIP DEVICE STRAPS
AU12 DVPDATA_22 TXCDM_DPD3N AT19 1:enable 0:disable
120ohm, 300mA AP12 DVPDATA_23
C54 C85 C84 AT21
10U/6.3V_6 1U/10V_4 0.1U/10V_4 TX3P_DPD2P AUD[1] EXT_CRT_HSYNC AUD[1] AUD[0]
TX3M_DPD2N AR20
AUD[0] EXT_CRT_VSYNC 0 0 No audio function
DPD AU22 0 1 Audio for DisplayPort and HDMI if dongle is detected
TX4P_DPD1P 1 0 Audio for DisplayPort only
TX4M_DPD1N AV21
1 1 Audio for both DisplayPort and HDMI
I2C AT23
+1.8V_GPU R45 0/J_4 TX5P_DPD0P
+VDD2DI ( 1.8V @ 40mA VDD2DI) TX5M_DPD0N AR22
AK26 RSVD GPIO8 Internal use only.
L20 BLM15BD121SN1D SCL RSVD GPIO_21_BB_EN Internal use only.
+VDD1DI ( 1.8V @ 45mA VDD1DI) AJ26 SDA RSVD DAC2_HSY RESERVED
120ohm, 300mA R AD39 EXT_CRT_RED (24) RSVD GENERICC RESERVED
C55 C63 C96 GENERAL PURPOSE I/O AD37
10U/6.3V_6 1U/10V_4 0.1U/10V_4 GPIO0 RB
AH20 GPIO_0
GPIO1 AH18 AE36 +1.8V_GPU
F-05 GPIO2 AN16
GPIO_1
GPIO_2
G
GB AD35
EXT_CRT_GRE (24)
B
C GPIO3 R300 *10K/J_4 RAM_TYPE_CFG0 C
AH23 GPIO_3_SMBDATA
GPIO4 1008 R298 *10K/J_4 RAM_TYPE_CFG1
(32,42) BAT/AC# *D20 GPIO5
AJ23
AH17
GPIO_4_SMBCLK B AF37
AE38
EXT_CRT_BLU (24)
R299 *10K/J_4 RAM_TYPE_CFG2 VRAM TYPE
+1.8V_GPU +A2VDDQ 1N4148WS GPIO6 GPIO_5_AC_BATT DAC1 BB R297 *10K/J_4 RAM_TYPE_CFG3
(1.8V @ 20mA A2VDDQ) AJ17 GPIO_6
(23) PANEL_BKEN AK17 GPIO_7_BLON HSYNC AC36 EXT_CRT_HSYNC (24)
L13 BLM15BD121SN1D GPIO8 AJ13 AC38
GPIO_8_ROMSO VSYNC EXT_CRT_VSYNC (24) +3V_GPU
GPIO9 AH15
GPIO10 GPIO_9_ROMSI
120ohm, 300mA AJ16 GPIO_10_ROMSCK
C24 C95 RAM_CFG0 AK16 AB34 RSET R50 499/F_4 R10 10K/J_4 RAM_CFG0
1U/10V_4 0.1U/10V_4 RAM_CFG1 GPIO_11 RSET R9 *10K/J_4 RAM_CFG1
RAM_CFG2
AL16
AM16
GPIO_12
AD34 R8 *10K/J_4 RAM_CFG2 APERTURE SIZE
GPIO_13 AVDD +AVDD
T4 PAD AM14 AE34
GFX_CORE_CNTRL0 AM13 GPIO_14_HPD2 AVSSQ +3V_GPU
(38) GFX_CORE_CNTRL0 GPIO_15_PWRCNTL_0
CLK_VGA_27M_SS_R AK14 AC33
GPIO_16_SSIN VDD1DI +VDD1DI R22 *10K/J_4 GFX_CORE_CNTRL0
(20) THERMAL_INT# AG30 GPIO_17_THERMAL_INT VSS1DI AC34
T73 PAD AN14 R23 *10K/J_4 GFX_CORE_CNTRL1 MEMORY APERTURE SIZE SELECT
+1.8V_GPU +DPLL_PVDD TEMP_FAIL GPIO_18_HPD3 R37 10K/J_4 GPIO0
(1.8V @ 120mA DPLL_PVDD) (4) TEMP_FAIL AM17 GPIO_19_CTF
GFX_CORE_CNTRL1 AL13 AC30 R39 10K/J_4 GPIO1 MEMORY CFG2 CFG1 CFG0
T103 PAD GPIO_20_PWRCNTL_1 R2
L8 BLM15BD121SN1D AJ14 AC31 R7 *10K/J_4 GPIO2
T9 PAD GPIO_21_BB_EN R2B R41 *10K/J_4 GPIO3
SIZE GPIO13 GPIO12 GPIO11
T3 PAD AK13 GPIO_22_ROMCSB
120ohm, 300mA AN13 AD30 R33 *10K/J_4 GPIO4 128MB 0 0 0
T74 PAD GPIO_23_CLKREQB G2
C15 C20 C32 AM23 AD31 R38 10K/J_4 GPIO5
T7 PAD JTAG_TRSTB G2B
10U/6.3V_6 1U/10V_4 0.1U/10V_4 AN23 R11 *10K/J_4 GPIO6 256MB 0 0 1
T1 PAD JTAG_TDI
AK23 AF30 R34 *10K/J_4 GPIO8
T18 PAD JTAG_TCK B2
AL24 AF31 R35 *10K/J_4 GPIO9 64MB 0 1 0
T5 PAD JTAG_TMS B2B
AM24 R36 *10K/J_4 GPIO10
T2 PAD JTAG_TDO
AJ19 R328 10K/J_4 EXT_CRT_HSYNC
+1V_GPU +DPLL_VDDC T12 PAD GENERICA
AK19 AC32 R326 10K/J_4 EXT_CRT_VSYNC
T6 PAD GENERICB C
1.0V @ 150mA DPLL_VDDC AJ20 AD32 R44 *10K/J_4 VGAVSYNC2
T11 PAD GENERICC Y
L7 BLM15BD121SN1D AK20 AF32 R308 *10K/J_4 PANEL_BKEN
T10 PAD GENERICD COMP
T8 PAD AJ24 GENERICE_HPD4
120ohm, 300mA AH26 DAC2
T15 PAD GENERICF
C14 C22 C31 AH24 AD29
T14 PAD GENERICG H2SYNC
10U/6.3V_6 1U/10V_4 0.1U/10V_4 AC29 VGAVSYNC2 R307 *10K/J_4 TEMP_FAIL BIA_PWM R25 10K/J_4
V2SYNC
+1.8V_GPU PLACE AK24 ENVDD R295 10K/J_4
(24) EXT_HDMI_HPD HPD1
VREFG VDD2DI AG31 +VDD2DI
AG32 U26G PANEL_BKEN R309 10K/J_4
DIVIDER VSS2DI +3V_GPU
(3) CLK_VGA_27M_SS R13 *0/J_4 CLK_VGA_27M_SS_R AND CAP
R16 CLOSE TO AG33
499/F_4 A2VDD LVDS CONTROL BIA_PWM
AK27 BIA_PWM (23)
ASIC AD33
VARY_BL
AJ27 ENVDD
A2VDDQ +A2VDDQ DIGON ENVDD (23)
B R18 AH13 C60 B
*10K/J_4 VREFG 0.1U/10V_4
A2VSSQ AF33
R21 C43 AA29 R2SET R52 715/F_4 AK35

249/F_4 0.1U/10V_4 R2SET TXCLK_UP_DPF3P
+DPLL_PVDD AM32 DPLL_PVDD TXCLK_UN_DPF3N AL36
AN32 DPLL_PVSS
TXOUT_U0P_DPF2P AJ38
DDC/AUX AM26 AK37
F-03 +DPLL_VDDC AN31 PLL/CLOCK
DPLL_VDDC
DDC1CLK
DDC1DATA AN26
EXT_HDMI_SCL (24)
EXT_HDMI_SDA (24)
TXOUT_U0N_DPF2N
E-01 TXOUT_U1P_DPF1P AH35
AUX1P AM27 TXOUT_U1N_DPF1N AJ36
XTAIN AV33 AL27
XTAOUT XTALIN AUX1N
AU34 XTALOUT TXOUT_U2P_DPF0P AG38
R302 61.9/F_4 R304 33/F_4 AM19 AH37
(3) CLK_VGA_27M_NONSS DDC2CLK TXOUT_U2N_DPF0N
DDC2DATA AL19
R303 75/F_4 R311 *0_4_SHORT AW34 AF35
XO_IN TXOUT_U3P PAD T20
AUX2P AN20 TXOUT_U3N AG36 PAD T19
R312 *0_4_SHORT AW35 AM20
SS_IN AUX2N
AL30 LVTMDP
DDCCLK_AUX3P
DDCDATA_AUX3N AM30
!!! NC when M92-M2 TXCLK_LP_DPE3P AP34 TXLCLKOUT+ (23)
R305 R301 AL29 AR34
DDCCLK_AUX4P TXCLK_LN_DPE3N TXLCLKOUT- (23)
*0/J_4 *0/J_4 (20) VGA_THERMDP AF29 AM29
DPLUS THERMAL DDCDATA_AUX4N
(20) VGA_THERMDN AG29 DMINUS TXOUT_L0P_DPE2P AW37 TXLOUT0+ (23)
AN21 EXT_EDIDCLK AU35
DDCCLK_AUX5P LCD_DDCCLK (23) TXOUT_L0N_DPE2N TXLOUT0- (23)
AM21 EXT_EDIDDAT
DDCDATA_AUX5N LCD_DDCDAT (23)
AK32 TS_FDO TXOUT_L1P_DPE1P AR37 TXLOUT1+ (23)
DDC6CLK AJ30 CRT_DDCCLK (24) TXOUT_L1N_DPE1N AU39 TXLOUT1- (23)
AL31 TS_A DDC6DATA AJ31 CRT_DDCDAT (24)
+1.8V_GPU +TSVDD AP35
TXOUT_L2P_DPE0P TXLOUT2+ (23)
L11 (1.8V @ 20mA TSVDD) AK30 AR35
DDCCLK_AUX7P TXOUT_L2N_DPE0N TXLOUT2- (23)
AJ32 TSVDD DDCDATA_AUX7N AK29 DDC6CLK/DDC6DATA support
BLM15BD121SN1D AJ33 AN36
TSVSS internal HDCP(High-bandwidth TXOUT_L3P PAD T76
120ohm, 300mA TXOUT_L3N AP37 PAD T75
C12 C16 C52 Digital Content Protection) function.
10U/6.3V_6 1U/10V_4 0.1U/10V_4 Madison
Madison
A EXT_CRT_BLU A
EXT_CRT_GRE
EXT_CRT_RED
(18,19,40) +1.8V_GPU R317 R318 R324

(18,20,41) +3V_GPU 150/F_4 150/F_4 150/F_4
(16,18,19,40) +1V_GPU Layout Note:
Place 150 ohm
termination resistors
close to ATI CHIP.

PROJECT : FH2A
1A
Madison_IO&STRAP
5 4 3 2 1
5 4 3 2 1
+1.5V_GPU For DDR3, VDDR1 = 1.5V

(1.5V @ 2.9A VDDR1+VDDRHA+VDDRHB)
U26E
MEM I/O
PCIE (1.8V @ 210mA PCIE_VDDR)
+PCIE_VDDR
L17
+1.8V_GPU
BLM18PG471SN1D
U26F
18
AC7 VDDR1#1 PCIE_VDDR#1 AA31 AB39 PCIE_VSS#1 GND#1 A3
AD11 VDDR1#2 PCIE_VDDR#2 AA32 E39 PCIE_VSS#2 GND#2 A37
AF7 VDDR1#3 PCIE_VDDR#3 AA33 470ohm, 1A F34 PCIE_VSS#3 GND#3 AA16
C69 C78 C175 C202 C88 C77 AG10 AA34 C97 C115 C128 C45 F39 AA18
VDDR1#4 PCIE_VDDR#4 PCIE_VSS#4 GND#4 (16,17,19,40) +1V_GPU
1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 AJ7 V28 0.1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3V_6 G33 AA2
VDDR1#5 PCIE_VDDR#5 PCIE_VSS#5 GND#5 (20,21,22,40) +1.5V_GPU
AK8 VDDR1#6 PCIE_VDDR#6 W29 G34 PCIE_VSS#6 GND#6 AA21 (17,19,40) +1.8V_GPU
AL9 VDDR1#7 PCIE_VDDR#7 W30 H31 PCIE_VSS#7 GND#7 AA23 (38,41) +VGPU_CORE
G11 VDDR1#8 PCIE_VDDR#8 Y31 H34 PCIE_VSS#8 GND#8 AA26 (17,20,41) +3V_GPU
G14 VDDR1#9 H39 PCIE_VSS#9 GND#9 AA28
G17 (1.1V @ 1.4A PCIE_VDDC) +PCIE_VDDC +1V_GPU J31 AA6
VDDR1#10 PCIE_VSS#10 GND#10
D
G20 VDDR1#11 PCIE_VDDC#1 G30 J34 PCIE_VSS#11 GND#11 AB12 D
G23 G31 L25 BLM18PG121SN1D K31 AB15
VDDR1#12 PCIE_VDDC#2 PCIE_VSS#12 GND#12
G26 VDDR1#13 PCIE_VDDC#3 H29 K34 PCIE_VSS#13 GND#13 AB17
C147 C201 C185 C113 C112 G29 H30 120ohm, 2A K39 AB20
1U/10V_4 1U/10V_4 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 VDDR1#14 PCIE_VDDC#4 C166 C157 C159 C177 C182 C196 PCIE_VSS#14 GND#14
H10 VDDR1#15 PCIE_VDDC#5 J29 L31 PCIE_VSS#15 GND#15 AB22
J7 J30 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3V_6 L34 AB24
J9 VDDR1#17 PCIE_VDDC#7 L28 M34 PCIE_VSS#17 GND#17 AB27
1U = 20 pcs K11 VDDR1#18 PCIE_VDDC#8 M28 M39 PCIE_VSS#18 GND#18 AC11
K13 VDDR1#19 PCIE_VDDC#9 N28 N31 PCIE_VSS#19 GND#19 AC13
10U = 5pcs K8 R28 N34 AC16
L12 VDDR1#21 PCIE_VDDC#11 T28 P31 PCIE_VSS#21 GND#21 AC18
L16 VDDR1#22 PCIE_VDDC#12 U28 P34 PCIE_VSS#22 GND#22 AC2
L21 VDDR1#23 (1.2V @ 29.5A GFX_CORE) +VGPU_CORE P39 PCIE_VSS#23 GND#23 AC21
L23 VDDR1#24 R34 PCIE_VSS#24 GND#24 AC23
L26 VDDR1#25 VDDC#1 AA15 T31 PCIE_VSS#25 GND#25 AC26
L7 CORE AA17 T34 AC28
VDDR1#26 VDDC#2 PCIE_VSS#26 GND#26
M11 VDDR1#27 VDDC#3 AA20 T39 PCIE_VSS#27 GND#27 AC6
N11 AA22 C139 C168 C74 C70 C102 C106 U31 AD15
+1.8V_GPU +VDD_CT VDDR1#28 VDDC#4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 PCIE_VSS#28 GND#28
P7 VDDR1#29 VDDC#5 AA24 U34 PCIE_VSS#29 GND#29 AD17
(1.8V @ 136mA VDD_CT) R11 VDDR1#30 VDDC#6 AA27 V34 PCIE_VSS#30 GND#30 AD20
L15 BLM15BD121SN1D U11 AB16 V39 AD22
VDDR1#31 VDDC#7 PCIE_VSS#31 GND#31
U7 VDDR1#32 VDDC#8 AB18 W31 PCIE_VSS#32 GND#32 AD24
120ohm, 300mA Y11 VDDR1#33 VDDC#9 AB21 W34 PCIE_VSS#33 GND#33 AD27
C18 C71 C81 Y7 AB23 Y34 AD9
10U/6.3V_6 1U/10V_4 0.1U/10V_4 VDDR1#34 VDDC#10 PCIE_VSS#34 GND#34
VDDC#11 AB26 Y39 PCIE_VSS#35 GND#35 AE2
AB28 C110 C107 C143 C142 C160 C156 AE6
VDDC#12 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 GND#36
VDDC#13 AC17 GND#37 AF10
VDDC#14 AC20 GND#38 AF16
LEVEL AC22 AF18
TRANSLATION VDDC#15 GND#39
AC24 AF21
+3V_GPU VDDC#16
GND GND#40
POWER
AF26 VDD_CT#1 VDDC#17 AC27 GND#41 AG17
AF27 VDD_CT#2 VDDC#18 AD18 F15 GND#100 GND#42 AG2
(3.3V @ 60mA VDDR3) AG26 VDD_CT#3 VDDC#19 AD21 F17 GND#101 GND#43 AG20
AG27 AD23 C180 C165 C148 C161 C145 C155 F19 AG22
VDD_CT#4 VDDC#20 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 GND#102 GND#44
VDDC#21 AD26 F21 GND#103 GND#45 AG6
C66 C79 AF17 F23 AG9
10U/6.3V_6 1U/10V_4 I/O VDDC#22 GND#104 GND#46
VDDC#23 AF20 F25 GND#105 GND#47 AH21
AF23 VDDR3#1 VDDC#24 AF22 F27 GND#106 GND#48 AJ10
C AF24 VDDR3#2 VDDC#25 AG16 F29 GND#107 GND#49 AJ11 C
AG23 VDDR3#3 VDDC#26 AG18 F31 GND#108 GND#50 AJ2
AG24 VDDR3#4 VDDC#27 AG21 F33 GND#109 GND#51 AJ28
+1.8V_GPU +VDDR4 AH22 C120 C164 C136 C104 C90 C171 F7 AJ6 PowerXpress control signal for Madsion and Park only
VDDC#28 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 GND#110 GND#52
AH27 F9 AK11 If not used, can be disconnected. (AL21 pin)
L23 BLM15BD121SN1D VDDC#29 GND#111 GND#53
AF13 VDDR4#4 VDDC#30 AH28 G2 GND#112 GND#54 AK31
AF15 VDDR4#5 VDDC#31 M26 G6 GND#113 GND#55 AK7 PX_EN = LOW, turn on
120ohm, 300mA AG13 VDDR4#7 VDDC#32 N24 H9 GND#114 GND#56 AL11 PX_EN = HIGH, turn off
C80 C89 AG15 N27 J2 AL14
1U/10V_4 0.1U/10V_4 VDDR4#8 VDDC#33 GND#115 GND#57
VDDC#34 R18 J27 GND#116 GND#58 AL17
VDDC#35 R21 J6 GND#117 GND#59 AL2
AD12 R23 C101 J8 AL20
VDDR4#1 VDDC#36 C127 C158 C76 C126 GND#118 GND#60
AF11 VDDR4#2 VDDC#37 R26 K14 GND#119 GND#61 AL21
AF12 T17 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 1U/10V_4 K7 AL23
VDDR4#3 VDDC#38 GND#120 GND#62 R20
AG11 VDDR4#6 VDDC#39 T20 L11 GND#121 GND#63 AL26
+1.5V_GPU T22 L17 AL32 M96@0_4
VDDC#40 GND#122 GND#64
VDDC#41 T24 L2 GND#123 GND#65 AL6
VDDC#42 T27 L22 GND#124 GND#66 AL8
B L43
M96@BLM15BD121SN1D R499
M96@0/J_4
M20
M21
NC_VDDRHA
NC_VSSRHA
VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
U16
U18
U21
U23
U26
L24
L6
M17
M22
M24
GND#125
GND#126
GND#127
GND#128
GND#129
GND#67
GND#68
GND#69
GND#70
GND#71
AM11
AM31
AM9
AN11
AN2
!!!
Reserve for PX_EN
for Park and Madison
L48 R500 V12 V17 N16 AN30
+1.8V_GPU +PCIE_PVDD M96@BLM15BD121SN1D M96@0/J_4 U12 NC_VDDRHB VDDC#48 GND#130 GND#72
NC_VSSRHB VDDC#49 V20 N18 GND#131 GND#73 AN6
(1.8V @ 68mA PCIE_PVDD) VDDC#50 V22 N2 GND#132 GND#74 AN8
L22 BLM15BD121SN1D V24 N21 AP11
VDDC#51 GND#133 GND#75 Pin AL21 to Ground for Broadway
VDDC#52 V27 N23 GND#134 GND#76 AP7
120ohm, 300mA VDDC#53 Y16 N26 GND#135 GND#77 AP9
C82 C98 C75 PLL Y18 N6 AR5
VDDC#54 GND#136 GND#78
B
10U/6.3V_6 1U/10V_4 0.1U/10V_4 AB37 Y21 R15 B11
PCIE_PVDD VDDC#55 GND#137 GND#79
VDDC#56 Y23 R17 GND#138 GND#80 B13
+MPV18 H7 MPV18#1 VDDC#57 Y26 R2 GND#139 GND#81 B15
H8 MPV18#2 VDDC#58 Y28 R20 GND#140 GND#82 B17
R22 GND#141 GND#83 B19
+VGPU_CORE R24 B21
+1V_GPU +SPV10 GND#142 GND#84
(0.95-1.2V @ 136mA SPV10) +SPV18 AM10 SPV18 R27 GND#143 GND#85 B23
B VDDCI#1 AA13 R6 GND#144 GND#86 B25 B
L14 MAD@BLM15BD121SN1D AN9 AB13 T11 B27
SPV10 VDDCI#2 GND#145 GND#87
VDDCI#3 AC12 T13 GND#146 GND#88 B29
120ohm, 300mA AN10 AC15 C86 C176 C172 C135 C105 C170 C179 T16 B31
C25 C34 C41 SPVSS VDDCI#4 1U/10V_4 1U/10V_4 10U/6.3V_6 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 GND#147 GND#89
VDDCI#5 AD13 T18 GND#148 GND#90 B33
10U/6.3V_6 1U/10V_4 0.1U/10V_4 AD16 T21 B7
+VGPU_CORE VDDCI#6 GND#149 GND#91
VDDCI#7 M15 T23 GND#150 GND#92 B9
VDDCI#8 M16 T26 GND#151 GND#93 C1
VOLTAGE M18 U15 C39
L44 M96@BLM15BD121SN1D SENESE VDDCI#9 GND#153 GND#94
VDDCI#10 M23 U17 GND#154 GND#95 E35
VDDCI#11 N13 U2 GND#155 GND#96 E5
B
T17 AF28 N15 U20 F11
FB_VDDC VDDCI#12 C99 C151 C87 C167 C122 C133 GND#156 GND#97
VDDCI#13 N17 U22 GND#157 GND#98 F13
N20 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 1U/10V_4 1U/10V_4 1U/10V_4 U24
T13 VDDCI#14 CH6221M9A07CH6221M9A07CH6221M9A07 GND#158
AG28 FB_VDDCI N22 U27
ISOLATED VDDCI#15 R12 U6
GND#159
CORE I/O VDDCI#16 R13 V11
GND#160
R498 M96@0/J_4 VDDCI#17 GND#161
AH29 FB_GND VDDCI#18 R16 V16 GND#163
VDDCI#19 T12 V18 GND#164
VDDCI#20 T15 V21 GND#165
B
VDDC_SENSE/VSS_SENSE and VDDCI_SENSE/VSS_SENSE route as differetial pair V15 V23
VDDCI#21 GND#166
VDDCI#22 Y13 V26 GND#167
W2 GND#168
W6 GND#169
Madison Y15 GND#170
Y17 GND#171
Y20 GND#172
+1.8V_GPU +MPV18 Y22 A39
GND#173 VSS_MECH#1
(1.8V @ 40mA MPV18) Y24 GND#174 VSS_MECH#2 AW1
L26 MAD@BLM15BD121SN1D Y27 AW39
GND#175 VSS_MECH#3
U13 GND#152
120ohm, 300mA C208 C200 C199 V13 GND#162
MAD@10U/6.3V_6 MAD@0.1U/10V_4 MAD@0.1U/10V_4 Madison
A +SPV18 A
(1.8V @ 75mA SPV18)
L10 MAD@BLM15BD121SN1D
120ohm, 300mA C23 C39
MAD@10U/6.3V_6 MAD@0.1U/10V_4

PROJECT : FH2A
1A
Madison_POWER
5 4 3 2 1
5 4 3 2 1
19
(16,17,18,40) +1V_GPU
+1.8V_GPU (1.8V@130mA DPC_VDD18)

B B (1.8V @ 110mA DPA_VDD18)
+DPA_VDD18 +1.8V_GPU
(17,18,40) +1.8V_GPU
L46 !!! L12 MAD@BLM15BD121SN1D

MAD@BLM15BD121SN1D
For M96/92, DPx_VDD10 = 1.1V 120ohm, 300mA
C21 For M97 DPx_VDD10 = 1.0V C42 C36 C29
D *0.1U/10V_4 MAD@0.1U/10V_4 MAD@1U/10V_4 MAD@10U/6.3V_6 D
DPC & DPD U26H

aren't used. DP C/D POWER DP A/B POWER (1.1V @ 200mA DPA_VDD10)
+1V_GPU
AP20 AN24 +DPA_VDD10 +1V_GPU
DPC_VDD18#1 DPA_VDD18#1
AP21 DPC_VDD18#2 DPA_VDD18#2 AP24
L9 BLM15BD121SN1D
120ohm, 300mA
C28 DPA for HDMI
B
*0.1U/10V_4 AP13 AP31 C19 C30 C13
DPC_VDD10#1 DPA_VDD10#1 0.1U/10V_4 1U/10V_4 10U/6.3V_6
AT13 DPC_VDD10#2 DPA_VDD10#2 AP32
AN17 AN27 +1.8V_GPU (1.8V @ 110mA DPB_VDD18)

+1.8V_GPU DPC_VSSR#1 DPA_VSSR#1
(1.8V@130mA DPD_VDD18) AP16 DPC_VSSR#2 DPA_VSSR#2 AP27
AP17 AP28 L45
L47 DPC_VSSR#3 DPA_VSSR#3 MAD@BLM15BD121SN1D
AW14 DPC_VSSR#4 DPA_VSSR#4 AW24
MAD@BLM15BD121SN1D AW16 AW26
DPC_VSSR#5 DPA_VSSR#5 C17
C35 *0.1U/10V_4
B
*0.1U/10V_4
AP22 DPD_VDD18#1 DPB_VDD18#1 AP25
+1V_GPU +1V_GPU (1.1V @ 200mA DPB_VDD10)
C C
AP14 DPD_VDD10#1 DPB_VDD10#1 AN33
C38 C33
*0.1U/10V_4 *0.1U/10V_4
AN19 DPD_VSSR#1 DPB_VSSR#1 AN29 (1.8V @ 20 mA DPA_PVDD)
AP18 DPD_VSSR#2 DPB_VSSR#2 AP29
AP19 AP30 +DPA_PVDD +1.8V_GPU
DPD_VSSR#3 DPB_VSSR#3
AW20 DPD_VSSR#4 DPB_VSSR#4 AW30
AW22 AW32 L37 BLM15BD121SN1D
DPD_VSSR#5 DPB_VSSR#5
(1.8V @ 400mA DPE_VDD18; 120ohm, 300mA
C513 C509 C508
200mA for DPE/DPF respectively) R306 150/F_4 R296 150/F_4 0.1U/10V_4 1U/10V_4 10U/6.3V_6
AW18 DPCD_CALR DPAB_CALR AW28
+1.8V_GPU +DPE_VDD18
DP E/F POWER DP PLL POWER
L19 BLM18PG600SN1D AH34 AU28
DPE_VDD18#1 DPA_PVDD
AJ34 DPE_VDD18#2 DPA_PVSS AV27
60ohm, 500mA
C68 C62 C61 +DPE_VDD10 +1.8V_GPU (1.8V @ 20 mA DPB_PVDD)
10U/6.3V_6 1U/10V_4 0.1U/10V_4
AL33 DPE_VDD10#1 DPB_PVDD AV29
AM33 DPE_VDD10#2 DPB_PVSS AR28
DPC & DPD +1.8V_GPU C510

*0.1U/10V_4
B aren't used. B
AN34 DPE_VSSR#1 DPC_PVDD AU18
AP39 DPE_VSSR#2 DPC_PVSS AV17
AR39 DPE_VSSR#3
AU37 +1.8V_GPU C511
DPE_VSSR#4 *0.1U/10V_4
DPE & DPF for LVDS (1.8V @ 40mA DPE_PVDD; 20mA
DPD_PVDD AV19 for DPE/DPF respectively)
+DPE_VDD18 AR18
DPD_PVSS C512
(1.1V @ 200mA DPE_VDD10;
AF34 *0.1U/10V_4 +DPE_PVDD +1.8V_GPU
100mA for DPE/DPF respectively) DPF_VDD18#1
AG34 DPF_VDD18#2
AM37 L16 BLM15BD121SN1D
+1V_GPU +DPE_VDD10 DPE_PVDD
DPE_PVSS AN38
120ohm, 300mA
L18 BLM15BD121SN1D AK33 C44 C51 C40
DPF_VDD10#1 0.1U/10V_4 1U/10V_4 10U/6.3V_6
AK34 DPF_VDD10#2
120ohm, 300mA AL38 R496 MAD@0/J_4
C46 C50 C49 DPF_PVDD R497 MAD@0/J_4
DPF_PVSS AM35
*10U/6.3V_6 *1U/10V_4 *0.1U/10V_4 CS00002JB38
AF39 DPF_VSSR#1 CS00002JB38
AH39 DPF_VSSR#2
AK39 DPF_VSSR#3
AL34 DPF_VSSR#4
AM34 DPF_VSSR#5
A 150/F_4 R32 AM39 DPEF_CALR

B A
Madison

PROJECT : FH2A
1A
Madison_DP_POWER
5 4 3 2 1
5 4 3 2 1
20
(18,21,22,40) +1.5V_GPU
(17,18,41) +3V_GPU
(21) VMA_RAS#0 VMA_RAS#0 U26C U26D
(21) VMA_RAS#1 VMA_RAS#1 DDR2 DDR2 DDR2 DDR2
GDDR3/GDDR5 GDDR5/GDDR3 GDDR3/GDDR5 GDDR5/GDDR3
VMA_CAS#0 DDR3 DDR3 DDR3 DDR3
(21) VMA_CAS#0
(21) VMA_CAS#1 VMA_CAS#1 VMA_DQ0 C37 G24 VMA_MA0 VMC_DQ0 C5 P8 VMC_MA0
VMA_DQ1 DQA0_0/DQA_0 MAA0_0/MAA_0 VMA_MA1 VMC_RAS#0 VMC_DQ1 DQB0_0/DQB_0 MAB0_0/MAB_0 VMC_MA1
C35 DQA0_1/DQA_1 MAA0_1/MAA_1 J23 (22) VMC_RAS#0 C3 DQB0_1/DQB_1 MAB0_1/MAB_1 T9
VMA_WE#0 VMA_DQ2 VMA_MA2 VMC_RAS#1 VMC_DQ2 VMC_MA2
MEMORY INTERFACE A
(21) VMA_WE#0 A35 DQA0_2/DQA_2 MAA0_2/MAA_2 H24 (22) VMC_RAS#1 E3 DQB0_2/DQB_2 MAB0_2/MAB_2 P9
VMA_WE#1 VMA_DQ3 VMA_MA3 VMC_DQ3 VMC_MA3
MEMORY INTERFACE B
(21) VMA_WE#1 E34 DQA0_3/DQA_3 MAA0_3/MAA_3 J24 E1 DQB0_3/DQB_3 MAB0_3/MAB_3 N7
VMA_DQ4 G32 H26 VMA_MA4 (22) VMC_CAS#0 VMC_CAS#0 VMC_DQ4 F1 N8 VMC_MA4
VMA_CKE0 VMA_DQ5 DQA0_4/DQA_4 MAA0_4/MAA_4 VMA_MA5 VMC_CAS#1 VMC_DQ5 DQB0_4/DQB_4 MAB0_4/MAB_4 VMC_MA5
(21) VMA_CKE0 D33 DQA0_5/DQA_5 MAA0_5/MAA_5 J26 (22) VMC_CAS#1 F3 DQB0_5/DQB_5 MAB0_5/MAB_5 N9
(21) VMA_CKE1 VMA_CKE1 VMA_DQ6 F32 H21 VMA_MA6 VMC_DQ6 F5 U9 VMC_MA6
VMA_DQ7 DQA0_6/DQA_6 MAA0_6/MAA_6 VMA_MA7 VMC_WE#0 VMC_DQ7 DQB0_6/DQB_6 MAB0_6/MAB_6 VMC_MA7
E32 DQA0_7/DQA_7 MAA0_7/MAA_7 G21 (22) VMC_WE#0 G4 DQB0_7/DQB_7 MAB0_7/MAB_7 U8
(21) VMA_CS0#0 VMA_CS0#0 VMA_DQ8 D31 H19 VMA_MA8 (22) VMC_WE#1 VMC_WE#1 VMC_DQ8 H5 Y9 VMC_MA8
VMA_CS1#0 VMA_DQ9 DQA0_8/DQA_8 MAA1_0/MAA_8 VMA_MA9 VMC_DQ9 DQB0_8/DQB_8 MAB1_0/MAB_8 VMC_MA9
D (21) VMA_CS1#0 F30 DQA0_9/DQA_9 MAA1_1/MAA_9 H20 H6 DQB0_9/DQB_9 MAB1_1/MAB_9 W9 D
VMA_DQ10 C30 L13 VMA_MA10 (22) VMC_CKE0 VMC_CKE0 VMC_DQ10 J4 AC8 VMC_MA10
VMA_ODT0 VMA_DQ11 DQA0_10/DQA_10 MAA1_2/MAA_10 VMA_MA11 VMC_CKE1 VMC_DQ11 DQB0_10/DQB_10 MAB1_2/MAB_10 VMC_MA11
(21) VMA_ODT0 A30 DQA0_11/DQA_11 MAA1_3/MAA_11 G16 (22) VMC_CKE1 K6 DQB0_11/DQB_11 MAB1_3/MAB_11 AC9
(21) VMA_ODT1 VMA_ODT1 VMA_DQ12 F28 J16 VMA_MA12 VMC_DQ12 K5 AA7 VMC_MA12
VMA_DQ13 DQA0_12/DQA_12 MAA1_4/MAA_12 VMA_BA2 VMC_CS0#0 VMC_DQ13 DQB0_12/DQB_12 MAB1_4/MAB_12 VMC_BA2
C28 DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 H16 (22) VMC_CS0#0 L4 DQB0_13/DQB_13 MAB1_5/BA2 AA8
(21) VMA_CLKP0 VMA_CLKP0 VMA_DQ14 A28 J17 VMA_BA0 (22) VMC_CS1#0 VMC_CS1#0 VMC_DQ14 M6 Y8 VMC_BA0
VMA_CLKN0 VMA_DQ15 DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 VMA_BA1 VMC_DQ15 DQB0_14/DQB_14 MAB1_6/BA0 VMC_BA1
(21) VMA_CLKN0 E28 DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 H17 M1 DQB0_15/DQB_15 MAB1_7/BA1 AA9
VMA_DQ16 D27 (22) VMC_ODT0 VMC_ODT0 VMC_DQ16 M3
VMA_CLKP1 VMA_DQ17 DQA0_16/DQA_16 VMA_DM0 VMC_ODT1 VMC_DQ17 DQB0_16/DQB_16 VMC_DM0
(21) VMA_CLKP1 F26 DQA0_17/DQA_17 WCKA0_0/DQMA_0 A32 (22) VMC_ODT1 M5 DQB0_17/DQB_17 WCKB0_0/DQMB_0 H3
(21) VMA_CLKN1 VMA_CLKN1 VMA_DQ18 C26 C32 VMA_DM1 VMC_DQ18 N4 H1 VMC_DM1
VMA_DQ19 DQA0_18/DQA_18 WCKA0B_0/DQMA_1 VMA_DM2 VMC_CLKP0 VMC_DQ19 DQB0_18/DQB_18 WCKB0B_0/DQMB_1 VMC_DM2
A26 DQA0_19/DQA_19 WCKA0_1/DQMA_2 D23 (22) VMC_CLKP0 P6 DQB0_19/DQB_19 WCKB0_1/DQMB_2 T3
VMA_WDQS[7..0] VMA_DQ20 F24 E22 VMA_DM3 VMC_CLKN0 VMC_DQ20 P5 T5 VMC_DM3
(21) VMA_WDQS[7..0] DQA0_20/DQA_20 WCKA0B_1/DQMA_3 (22) VMC_CLKN0 DQB0_20/DQB_20 WCKB0B_1/DQMB_3
VMA_DQ21 C24 C14 VMA_DM4 VMC_DQ21 R4 AE4 VMC_DM4
VMA_RDQS[7..0] VMA_DQ22 DQA0_21/DQA_21 WCKA1_0/DQMA_4 VMA_DM5 VMC_CLKP1 VMC_DQ22 DQB0_21/DQB_21 WCKB1_0/DQMB_4 VMC_DM5
(21) VMA_RDQS[7..0] A24 DQA0_22/DQA_22 WCKA1B_0/DQMA_5 A14 (22) VMC_CLKP1 T6 DQB0_22/DQB_22 WCKB1B_0/DQMB_5 AF5
VMA_DQ23 E24 E10 VMA_DM6 (22) VMC_CLKN1 VMC_CLKN1 VMC_DQ23 T1 AK6 VMC_DM6
VMA_DM[7..0] VMA_DQ24 DQA0_23/DQA_23 WCKA1_1/DQMA_6 VMA_DM7 VMC_DQ24 DQB0_23/DQB_23 WCKB1_1/DQMB_6 VMC_DM7
(21) VMA_DM[7..0] C22 DQA0_24/DQA_24 WCKA1B_1/DQMA_7 D9 U4 DQB0_24/DQB_24 WCKB1B_1/DQMB_7 AK5
VMA_DQ25 A22 VMC_WDQS[7..0] VMC_DQ25 V6
DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 (22) VMC_WDQS[7..0] DQB0_25/DQB_25 GDDR5/DDR2/GDDR3
VMA_DQ[63..0] VMA_DQ26 F22 C34 VMA_RDQS0 VMC_DQ26 V1 F6 VMC_RDQS0
(21) VMA_DQ[63..0] VMA_DQ27 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 VMA_RDQS1 VMC_RDQS[7..0] VMC_DQ27 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 VMC_RDQS1
D21 DQA0_27/DQA_27 EDCA0_1/QSA_1/RDQSA_1 D29 (22) VMC_RDQS[7..0] V3 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1 K3
VMA_MA[13..0] VMA_DQ28 A20 D25 VMA_RDQS2 VMC_DQ28 Y6 P3 VMC_RDQS2
(21) VMA_MA[13..0] DQA0_28/DQA_28 EDCA0_2/QSA_2/RDQSA_2 DQB0_28/DQB_28 EDCB0_2/QSB_2/RDQSB_2
VMA_DQ29 F20 E20 VMA_RDQS3 VMC_DM[7..0] VMC_DQ29 Y1 V5 VMC_RDQS3
DQA0_29/DQA_29 EDCA0_3/QSA_3/RDQSA_3 (22) VMC_DM[7..0] DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3
VMA_DQ30 D19 E16 VMA_RDQS4 VMC_DQ30 Y3 AB5 VMC_RDQS4
VMA_BA0 VMA_DQ31 DQA0_30/DQA_30 EDCA1_0/QSA_4/RDQSA_4 VMA_RDQS5 VMC_DQ[63..0] VMC_DQ31 DQB0_30/DQB_30 EDCB1_0/QSB_4/RDQSB_4 VMC_RDQS5
(21) VMA_BA0 E18 DQA0_31/DQA_31 EDCA1_1/QSA_5/RDQSA_5 E12 Y5 DQB0_31/DQB_31 EDCB1_1/QSB_5/RDQSB_5 AH1
VMA_BA1 VMA_DQ32 C18 J10 VMA_RDQS6 (22) VMC_DQ[63..0] VMC_DQ32 AA4 AJ9 VMC_RDQS6
(21) VMA_BA1 DQA1_0/DQA_32 EDCA1_2/QSA_6/RDQSA_6 DQB1_0/DQB_32 EDCB1_2/QSB_6/RDQSB_6
VMA_BA2 VMA_DQ33 A18 D7 VMA_RDQS7 VMC_MA[13..0] VMC_DQ33 AB6 AM5 VMC_RDQS7
(21) VMA_BA2 DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 (22) VMC_MA[13..0] DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7
VMA_DQ34 F18 VMC_DQ34 AB1
VMA_DQ35 DQA1_2/DQA_34 VMA_WDQS0 VMC_DQ35 DQB1_2/DQB_34 VMC_WDQS0
D17 DQA1_3/DQA_35 DDBIA0_0/QSA_0B/WDQSA_0 A34 AB3 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 G7
VMA_DQ36 A16 E30 VMA_WDQS1 (22) VMC_BA0 VMC_BA0 VMC_DQ36 AD6 K1 VMC_WDQS1
VMA_DQ37 DQA1_4/DQA_36 DDBIA0_1/QSA_1B/WDQSA_1 VMA_WDQS2 VMC_BA1 VMC_DQ37 DQB1_4/DQB_36 DDBIB0_1/QSB_1B/WDQSB_1 VMC_WDQS2
F16 DQA1_5/DQA_37 DDBIA0_2/QSA_2B/WDQSA_2 E26 (22) VMC_BA1 AD1 DQB1_5/DQB_37 DDBIB0_2/QSB_2B/WDQSB_2 P1
VMA_DQ38 D15 C20 VMA_WDQS3 (22) VMC_BA2 VMC_BA2 VMC_DQ38 AD3 W4 VMC_WDQS3
VMA_DQ39 DQA1_6/DQA_38 DDBIA0_3/QSA_3B/WDQSA_3 VMA_WDQS4 VMC_DQ39 DQB1_6/DQB_38 DDBIB0_3/QSB_3B/WDQSB_3 VMC_WDQS4
E14 DQA1_7/DQA_39 DDBIA1_0/QSA_4B/WDQSA_4 C16 AD5 DQB1_7/DQB_39 DDBIB1_0/QSB_4B/WDQSB_4 AC4
VMA_DQ40 F14 C12 VMA_WDQS5 VMC_DQ40 AF1 AH3 VMC_WDQS5
VMA_DQ41 DQA1_8/DQA_40 DDBIA1_1/QSA_5B/WDQSA_5 VMA_WDQS6 VMC_DQ41 DQB1_8/DQB_40 DDBIB1_1/QSB_5B/WDQSB_5 VMC_WDQS6
C
D13 DQA1_9/DQA_41 DDBIA1_2/QSA_6B/WDQSA_6 J11 AF3 DQB1_9/DQB_41 DDBIB1_2/QSB_6B/WDQSB_6 AJ8 C
VMA_DQ42 F12 F8 VMA_WDQS7 VMC_DQ42 AF6 AM3 VMC_WDQS7
VMA_DQ43 DQA1_10/DQA_42 DDBIA1_3/QSA_7B/WDQSA_7 VMC_DQ43 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7
A12 DQA1_11/DQA_43 AG4 DQB1_11/DQB_43
VMA_DQ44 D11 J21 VMA_ODT0 VMC_DQ44 AH5 T7 VMC_ODT0
VMA_DQ45 DQA1_12/DQA_44 ADBIA0/ODTA0 VMA_ODT1 VMC_DQ45 DQB1_12/DQB_44 ADBIB0/ODTB0 VMC_ODT1
F10 DQA1_13/DQA_45 ADBIA1/ODTA1 G19 AH6 DQB1_13/DQB_45 ADBIB1/ODTB1 W7
VMA_DQ46 A10 VMC_DQ46 AJ4
VMA_DQ47 DQA1_14/DQA_46 VMA_CLKP0 VMC_DQ47 DQB1_14/DQB_46 VMC_CLKP0
C10 DQA1_15/DQA_47 CLKA0 H27 AK3 DQB1_15/DQB_47 CLKB0 L9
VMA_DQ48 G13 G27 VMA_CLKN0 VMC_DQ48 AF8 L8 VMC_CLKN0
VMA_DQ49 DQA1_16/DQA_48 CLKA0B VMC_DQ49 DQB1_16/DQB_48 CLKB0B
H13 DQA1_17/DQA_49 AF9 DQB1_17/DQB_49
+1.5V_GPU VMA_DQ50 J13 J14 VMA_CLKP1 +1.5V_GPU VMC_DQ50 AG8 AD8 VMC_CLKP1
VMA_DQ51 DQA1_18/DQA_50 CLKA1 VMA_CLKN1 VMC_DQ51 DQB1_18/DQB_50 CLKB1 VMC_CLKN1
PLACE MVREF
C-01 VMA_DQ52
H11
G10
DQA1_19/DQA_51 CLKA1B H14 C-01 VMC_DQ52
AG7
AK9
DQB1_19/DQB_51 CLKB1B AD7
VMA_DQ53 DQA1_20/DQA_52 VMA_RAS#0 VMC_DQ53 DQB1_20/DQB_52 VMC_RAS#0

DIVIDERS G8 DQA1_21/DQA_53 RASA0B K23 PLACE MVREF AL7 DQB1_21/DQB_53 RASB0B T10
Ra R81 VMA_DQ54 K9 K19 VMA_RAS#1 Ra R54 VMC_DQ54 AM8 Y10 VMC_RAS#1
AND CAPS 100/F_4 VMA_DQ55 DQA1_22/DQA_54 RASA1B DIVIDERS 100/F_4 VMC_DQ55 DQB1_22/DQB_54 RASB1B
K10 DQA1_23/DQA_55 AM7 DQB1_23/DQB_55
CLOSE TO ASIC VMA_DQ56 G9 K20 VMA_CAS#0 AND CAPS VMC_DQ56 AK1 W10 VMC_CAS#0
DQA1_24/DQA_56 CASA0B DQB1_24/DQB_56 CASB0B
VMA_DQ57 A8 DQA1_25/DQA_57 CASA1B K17 VMA_CAS#1 CLOSE TO ASIC VMC_DQ57 AL4 DQB1_25/DQB_57 CASB1B AA10 VMC_CAS#1
VMA_DQ58 C8 VMC_DQ58 AM6
+1.5V_GPU VMA_DQ59 DQA1_26/DQA_58 VMA_CS0#0 VMC_DQ59 DQB1_26/DQB_58 VMC_CS0#0
E8 DQA1_27/DQA_59 CSA0B_0 K24 AM1 DQB1_27/DQB_59 CSB0B_0 P10
Rb R82 C184 VMA_DQ60 +1.5V_GPU VMC_DQ60
C-01 100/F_4 0.1U/10V_4 VMA_DQ61
A6
C6
DQA1_28/DQA_60 CSA0B_1 K27
Rb R55 C123 VMC_DQ61
AN4
AP3
DQB1_28/DQB_60 CSB0B_1 L10
VMA_DQ62 DQA1_29/DQA_61 VMA_CS1#0 100/F_4 0.1U/10V_4 VMC_DQ62 DQB1_29/DQB_61 VMC_CS1#0

Ra R83 VMA_DQ63
E6
A5
DQA1_30/DQA_62 CSA1B_0 M13
K16
C-01 R51 VMC_DQ63
AP1
AP5
DQB1_30/DQB_62 CSB1B_0 AD10
AC10
100/F_4 DQA1_31/DQA_63 CSA1B_1 100/F_4 DQB1_31/DQB_63 CSB1B_1
Ra
MVREFDA L18 K21 VMA_CKE0 U10 VMC_CKE0
MVREFSA MVREFDA CKEA0 VMA_CKE1 MVREFDB Y12 CKEB0 VMC_CKE1
L20 MVREFSA CKEA1 J20 MVREFDB CKEB1 AA11
MVREFSB AA12 +1.5V_GPU
R84 MAD@243/F_4L27 VMA_WE#0 MVREFSB VMC_WE#0
+1.5V_GPU MEM_CALRN0 WEA0B K26 WEB0B N10
Rb R80 C192 R64 MAD@243/F_4
N12 L15 VMA_WE#1 AB11 VMC_WE#1
100/F_4 0.1U/10V_4 R48 MAD@243/F_4 MEM_CALRN1 WEA1B R57 C114 WEB1B
AG12 MEM_CALRN2 Rb
100/F_4 0.1U/10V_4 R314
R73 243/F_4 M12 H23 VMA_MA13 TESTEN AD28 T8 VMC_MA13 *2.2K/J_4
MEM_CALRP1 MAA0_8 TESTEN MAB0_8
GDDR5
GDDR5
R74 MAD@243/F_4
M27 J19 W8
R30 MAD@243/F_4 MEM_CALRP0 MAA1_8 MAB1_8
B AH12 MEM_CALRP2 AK10 CLKTESTA
B
AL10 AH11 R313 51/J_4 DDR3_RST (21,22)
CLKTESTB DRAM_RST
DDR3 Memory Stuff Option C53 C47 R315
B
*0.1U/10V_4 *0.1U/10V_4 C72 10K/J_4
Madison 68P/50V_4
(Capilano) M96 Madison
Madison R31 R29
DDR3 DDR3 *51.1/F_4 *51.1/F_4
MVDDQ 1.5V 1.5V

Ra 40.2R 100R +3V_GPU
Thermal Sensor 781-1_3V R62 200/F_6
Rb 100R 100R +3V_GPU
U3 C130 0.1U/10V_4
MBCLK_VGA 8 1 +3V_GPU
10K/F_4 SMCLK VCC VGA_THERMDP
R77 VGA_THERMDP (17)
MBDATA_VGA 7 2
SMDATA DXP C140 R42
(17) THERMAL_INT#
THERMAL_INT# 6
-ALT DXN 3 2200P/50V_4 w/s 10 / 10 *10K/F_4
5 4 VGA_THERMDN
GND -OVT VGA_THERMDN (17)
TESTEN
G781-1P8
-VGATHRM +3V_GPU
I2C ADDRESS: 9AH R63 10K/F_4
R47
10K/F_4
Q1 2N7002E
(32,42) MBCLK MBCLK 3 1 MBCLK_VGA
A A
R78
2.2K/F_4
2
+3V_GPU

2
R79
Q2 2.2K/F_4
(32,42) MBDATA MBDATA3 1 MBDATA_VGA PROJECT : FH2A
2N7002E 1A
Madison_MEMORY/THERM
5 4 3 2 1
1 2 3 4 5 6 7 8
21
(18,20,22,40) +1.5V_GPU
DDR3 64MX16, CH A : 512MB
U7 U28 U6 U29
VREF_A0 M8 E3 VMA_DQ6 VREF_A2 M8 E3 VMA_DQ10 VREF_A4 M8 E3 VMA_DQ40 VREF_A6 M8 E3 VMA_DQ54

VREF_A1 VREFCA DQL0 VMA_DQ0 VREF_A3 VREFCA DQL0 VMA_DQ11 VREF_A5 VREFCA DQL0 VMA_DQ42 VREF_A7 VREFCA DQL0 VMA_DQ53
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 VMA_DQ7 F2 VMA_DQ9 F2 VMA_DQ45 F2 VMA_DQ55
VMA_MA0 DQL2 VMA_DQ1 VMA_MA0 DQL2 VMA_DQ12 VMA_MA0 DQL2 VMA_DQ43 VMA_MA0 DQL2 VMA_DQ50
N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8
VMA_MA1 P7 H3 VMA_DQ4 VMA_MA1 P7 H3 VMA_DQ13 VMA_MA1 P7 H3 VMA_DQ46 VMA_MA1 P7 H3 VMA_DQ49
VMA_MA2 A1 DQL4 VMA_DQ2 VMA_MA2 A1 DQL4 VMA_DQ15 VMA_MA2 A1 DQL4 VMA_DQ41 VMA_MA2 A1 DQL4 VMA_DQ51
P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8
VMA_MA3 N2 G2 VMA_DQ5 VMA_MA3 N2 G2 VMA_DQ8 VMA_MA3 N2 G2 VMA_DQ47 VMA_MA3 N2 G2 VMA_DQ52
VMA_MA4 A3 DQL6 VMA_DQ3 VMA_MA4 A3 DQL6 VMA_DQ14 VMA_MA4 A3 DQL6 VMA_DQ44 VMA_MA4 A3 DQL6 VMA_DQ48
VMA_MA5 P2 VMA_MA5 P2 VMA_MA5 P2 VMA_MA5 P2
VMA_MA6 A5 VMA_MA6 A5 VMA_MA6 A5 VMA_MA6 A5
R8 A6 R8 A6 R8 A6 R8 A6
VMA_MA7 R2 D7 VMA_DQ25 VMA_MA7 R2 D7 VMA_DQ20 VMA_MA7 R2 D7 VMA_DQ32 VMA_MA7 R2 D7 VMA_DQ63
VMA_MA8 A7 DQU0 VMA_DQ31 VMA_MA8 A7 DQU0 VMA_DQ19 VMA_MA8 A7 DQU0 VMA_DQ36 VMA_MA8 A7 DQU0 VMA_DQ56
A
T8 A8 DQU1 C3 T8 A8 DQU1 C3 T8 A8 DQU1 C3 T8 A8 DQU1 C3 A
VMA_MA9 R3 C8 VMA_DQ26 VMA_MA9 R3 C8 VMA_DQ23 VMA_MA9 R3 C8 VMA_DQ33 VMA_MA9 R3 C8 VMA_DQ62
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
VMA_MA11 R7 A7 VMA_DQ24 VMA_MA11 R7 A7 VMA_DQ22 VMA_MA11 R7 A7 VMA_DQ35 VMA_MA11 R7 A7 VMA_DQ60
N7 A12/BC DQU5 A2 N7 A12/BC DQU5 A2 N7 A12/BC DQU5 A2 N7 A12/BC DQU5 A2
VMA_MA13 T3 B8 VMA_DQ27 VMA_MA13 T3 B8 VMA_DQ21 VMA_MA13 T3 B8 VMA_DQ34 VMA_MA13 T3 B8 VMA_DQ61
A13 DQU6 VMA_DQ29 A13 DQU6 VMA_DQ17 A13 DQU6 VMA_DQ38 A13 DQU6 VMA_DQ57
T7 A14 DQU7 A3 T7 A14 DQU7 A3 T7 A14 DQU7 A3 T7 A14 DQU7 A3
M7 A15 M7 A15 M7 A15 M7 A15
+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU
VMA_BA0 M2 B2 VMA_BA0 M2 B2 VMA_BA0 M2 B2 VMA_BA0 M2 B2

VMA_BA1 BA0 VDD#B2 VMA_BA1 BA0 VDD#B2 VMA_BA1 BA0 VDD#B2 VMA_BA1 BA0 VDD#B2
N8 BA1 VDD#D9 D9 N8 BA1 VDD#D9 D9 N8 BA1 VDD#D9 D9 N8 BA1 VDD#D9 D9
VMA_BA2 M3 G7 VMA_BA2 M3 G7 VMA_BA2 M3 G7 VMA_BA2 M3 G7
BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
VDD#K2 K2 VDD#K2 K2 VDD#K2 K2 VDD#K2 K2
VDD#N1 N1 VDD#N1 N1 VDD#N1 N1 VDD#N1 N1
VMA_CLKP0 J7 N9 VMA_CLKP0 J7 N9 VMA_CLKP1 J7 N9 VMA_CLKP1 J7 N9
(20) VMA_CLKP0 CK VDD#N9 CK VDD#N9 (20) VMA_CLKP1 CK VDD#N9 CK VDD#N9
VMA_CLKN0 K7 R1 VMA_CLKN0 K7 R1 VMA_CLKN1 K7 R1 VMA_CLKN1 K7 R1
(20) VMA_CLKN0 CK VDD#R1 CK VDD#R1 (20) VMA_CLKN1 CK VDD#R1 CK VDD#R1
VMA_CKE0 K9 R9 VMA_CKE0 K9 R9 VMA_CKE1 K9 R9 VMA_CKE1 K9 R9
(20) VMA_CKE0 CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU (20) VMA_CKE1 CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU
VMA_ODT0 K1 A1 VMA_ODT0 K1 A1 VMA_ODT1 K1 A1 VMA_ODT1 K1 A1

(20) VMA_ODT0 ODT VDDQ#A1 ODT VDDQ#A1 (20) VMA_ODT1 ODT VDDQ#A1 ODT VDDQ#A1
VMA_CS0#0 L2 A8 VMA_CS0#0 L2 A8 VMA_CS1#0 L2 A8 VMA_CS1#0 L2 A8
(20) VMA_CS0#0 CS VDDQ#A8 CS VDDQ#A8 (20) VMA_CS1#0 CS VDDQ#A8 CS VDDQ#A8
VMA_RAS#0 J3 C1 VMA_RAS#0 J3 C1 VMA_RAS#1 J3 C1 VMA_RAS#1 J3 C1
(20) VMA_RAS#0 RAS VDDQ#C1 RAS VDDQ#C1 (20) VMA_RAS#1 RAS VDDQ#C1 RAS VDDQ#C1
VMA_CAS#0 K3 C9 VMA_CAS#0 K3 C9 VMA_CAS#1 K3 C9 VMA_CAS#1 K3 C9
(20) VMA_CAS#0 CAS VDDQ#C9 CAS VDDQ#C9 (20) VMA_CAS#1 CAS VDDQ#C9 CAS VDDQ#C9
VMA_WE#0 L3 D2 VMA_WE#0 L3 D2 VMA_WE#1 L3 D2 VMA_WE#1 L3 D2
(20) VMA_WE#0 WE VDDQ#D2 WE VDDQ#D2 (20) VMA_WE#1 WE VDDQ#D2 WE VDDQ#D2
VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#E9 E9
VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1
VMA_RDQS0 F3 H2 VMA_RDQS1 F3 H2 VMA_RDQS5 F3 H2 VMA_RDQS6 F3 H2
VMA_RDQS3 DQSL VDDQ#H2 VMA_RDQS2 DQSL VDDQ#H2 VMA_RDQS4 DQSL VDDQ#H2 VMA_RDQS7 DQSL VDDQ#H2
C7 DQSU VDDQ#H9 H9 C7 DQSU VDDQ#H9 H9 C7 DQSU VDDQ#H9 H9 C7 DQSU VDDQ#H9 H9
VMA_DM0 E7 A9 VMA_DM1 E7 A9 VMA_DM5 E7 A9 VMA_DM6 E7 A9

VMA_DM3 DML VSS#A9 VMA_DM2 DML VSS#A9 VMA_DM4 DML VSS#A9 VMA_DM7 DML VSS#A9
D3 DMU VSS#B3 B3 D3 DMU VSS#B3 B3 D3 DMU VSS#B3 B3 D3 DMU VSS#B3 B3
VSS#E1 E1 VSS#E1 E1 VSS#E1 E1 VSS#E1 E1
VSS#G8 G8 VSS#G8 G8 VSS#G8 G8 VSS#G8 G8
VMA_WDQS0 G3 J2 VMA_WDQS1 G3 J2 VMA_WDQS5 G3 J2 VMA_WDQS6 G3 J2
VMA_WDQS3 DQSL VSS#J2 VMA_WDQS2 DQSL VSS#J2 VMA_WDQS4 DQSL VSS#J2 VMA_WDQS7 DQSL VSS#J2
B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8
B
VSS#M1 M1 VSS#M1 M1 VSS#M1 M1 VSS#M1 M1 B
VSS#M9 M9 VSS#M9 M9 VSS#M9 M9 VSS#M9 M9

VSS#P1 P1 VSS#P1 P1 VSS#P1 P1 VSS#P1 P1
DDR3_RST T2 P9 DDR3_RST T2 P9 DDR3_RST T2 P9 DDR3_RST T2 P9
(20,22) DDR3_RST RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
VSS#T1 T1 VSS#T1 T1 VSS#T1 T1 VSS#T1 T1
R95 240/F_4L8 T9 R361 240/F_4L8 T9 R92 240/F_4L8 T9 R358 240/F_4L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
VSSQ#B1 B1 VSSQ#B1 B1 VSSQ#B1 B1 VSSQ#B1 B1

VSSQ#D1 D1 VSSQ#D1 D1 VSSQ#D1 D1 VSSQ#D1 D1
VSSQ#E2 E2 VSSQ#E2 E2 VSSQ#E2 E2 VSSQ#E2 E2
J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8
L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9
J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1
L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9
100-BALL 100-BALL 100-BALL 100-BALL

SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12 K4W1G1646E-HC12 K4W1G1646E-HC12 K4W1G1646E-HC12
VMA_DQ[63..0]
(20) VMA_DQ[63..0]
VMA_MA[13..0]
(20) VMA_MA[13..0]
VMA_WDQS[7..0]
(20) VMA_WDQS[7..0] +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU
VMA_RDQS[7..0]
(20) VMA_RDQS[7..0]
VMA_DM[7..0]
(20) VMA_DM[7..0]
R93 R102 R354 R360 R91 R96 R356 R342
VMA_BA[2..0]
(20) VMA_BA[2..0]
4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4
VREF_A0 VREF_A1 VREF_A2 VREF_A3 VREF_A4 VREF_A5 VREF_A6 VREF_A7
Placement has to be close to VRAM R94 C226 R90 C234 R355 C563 R359 C566 R103 C233 R97 C229 R357 C565 R341 C545
C C
4.99K/F_4 0.1U/10V_4 4.99K/F_4 0.1U/10V_4 4.99K/F_4 0.1U/10V_4 4.99K/F_4 0.1U/10V_4 4.99K/F_4 0.1U/10V_4 4.99K/F_4 0.1U/10V/X7R_4 4.99K/F_4 0.1U/10V_4 4.99K/F_4 0.1U/10V_4
VMA_CLKP0 R101 56/J_4
C231 0.01U/16V_4
VMA_CLKN0 R100 56/J_4
VMA_CLKP1 R98 56/J_4

C230 0.01U/16V_4
VMA_CLKN1 R99 56/J_4 +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU
C224 C228 C227 C567 C225 C556 C220 C223 C222 C568 C217 C564
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
+1.5V_GPU +1.5V_GPU
C221 C558 C572 C218 C538 C232
10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6
D D

PROJECT : FH2A
1A
Madison/M96_DDR3_A_512M
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
22
(18,20,21,40) +1.5V_GPU
DDR3 64MX16, CH B : 512MB
U27 U5 U2 U25
VREF_B0 M8 E3 VMC_DQ16 VREF_B2 M8 E3 VMC_DQ4 VREF_B4 M8 E3 VMC_DQ52 VREF_B6 M8 E3 VMC_DQ37

VREF_B1 VREFCA DQL0 VMC_DQ20 VREF_B3 VREFCA DQL0 VMC_DQ3 VREF_B5 VREFCA DQL0 VMC_DQ50 VREF_B7 VREFCA DQL0 VMC_DQ38
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 VMC_DQ17 F2 VMC_DQ7 F2 VMC_DQ55 F2 VMC_DQ35
VMC_MA0 DQL2 VMC_DQ23 VMC_MA0 DQL2 VMC_DQ1 VMC_MA0 DQL2 VMC_DQ51 VMC_MA0 DQL2 VMC_DQ36
N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8
VMC_MA1 P7 H3 VMC_DQ19 VMC_MA1 P7 H3 VMC_DQ6 VMC_MA1 P7 H3 VMC_DQ53 VMC_MA1 P7 H3 VMC_DQ32
VMC_MA2 A1 DQL4 VMC_DQ22 VMC_MA2 A1 DQL4 VMC_DQ0 VMC_MA2 A1 DQL4 VMC_DQ48 VMC_MA2 A1 DQL4 VMC_DQ39
VMC_MA3 N2 G2 VMC_DQ18 VMC_MA3 N2 G2 VMC_DQ5 VMC_MA3 N2 G2 VMC_DQ54 VMC_MA3 N2 G2 VMC_DQ34
VMC_MA4 A3 DQL6 VMC_DQ21 VMC_MA4 A3 DQL6 VMC_DQ2 VMC_MA4 A3 DQL6 VMC_DQ49 VMC_MA4 A3 DQL6 VMC_DQ33
VMC_MA5 P2 VMC_MA5 P2 VMC_MA5 P2 VMC_MA5 P2
VMC_MA6 A5 VMC_MA6 A5 VMC_MA6 A5 VMC_MA6 A5
R8 A6 R8 A6 R8 A6 R8 A6
VMC_MA7 R2 D7 VMC_DQ15 VMC_MA7 R2 D7 VMC_DQ24 VMC_MA7 R2 D7 VMC_DQ44 VMC_MA7 R2 D7 VMC_DQ63
VMC_MA8 A7 DQU0 VMC_DQ8 VMC_MA8 A7 DQU0 VMC_DQ31 VMC_MA8 A7 DQU0 VMC_DQ45 VMC_MA8 A7 DQU0 VMC_DQ59
A
T8 A8 DQU1 C3 T8 A8 DQU1 C3 T8 A8 DQU1 C3 T8 A8 DQU1 C3 A
VMC_MA9 R3 C8 VMC_DQ14 VMC_MA9 R3 C8 VMC_DQ28 VMC_MA9 R3 C8 VMC_DQ40 VMC_MA9 R3 C8 VMC_DQ60
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
VMC_MA11 R7 A7 VMC_DQ12 VMC_MA11 R7 A7 VMC_DQ26 VMC_MA11 R7 A7 VMC_DQ43 VMC_MA11 R7 A7 VMC_DQ62
N7 A12/BC DQU5 A2 N7 A12/BC DQU5 A2 N7 A12/BC DQU5 A2 N7 A12/BC DQU5 A2
VMC_MA13 T3 B8 VMC_DQ13 VMC_MA13 T3 B8 VMC_DQ25 VMC_MA13 T3 B8 VMC_DQ41 VMC_MA13 T3 B8 VMC_DQ61
A13 DQU6 VMC_DQ10 A13 DQU6 VMC_DQ29 A13 DQU6 VMC_DQ46 A13 DQU6 VMC_DQ57
T7 A14 DQU7 A3 T7 A14 DQU7 A3 T7 A14 DQU7 A3 T7 A14 DQU7 A3
M7 A15 M7 A15 M7 A15 M7 A15
VMC_BA0 M2 B2 VMC_BA0 M2 B2 VMC_BA0 M2 B2 VMC_BA0 M2 B2

VMC_BA1 BA0 VDD#B2 VMC_BA1 BA0 VDD#B2 VMC_BA1 BA0 VDD#B2 VMC_BA1 BA0 VDD#B2
N8 BA1 VDD#D9 D9 N8 BA1 VDD#D9 D9 N8 BA1 VDD#D9 D9 N8 BA1 VDD#D9 D9
VMC_BA2 M3 G7 VMC_BA2 M3 G7 VMC_BA2 M3 G7 VMC_BA2 M3 G7
BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
VDD#N1 N1 VDD#N1 N1 VDD#N1 N1 VDD#N1 N1
VMC_CLKP0 J7 N9 VMC_CLKP0 J7 N9 VMC_CLKP1 J7 N9 VMC_CLKP1 J7 N9
(20) VMC_CLKP0 CK VDD#N9 CK VDD#N9 (20) VMC_CLKP1 CK VDD#N9 CK VDD#N9
VMC_CLKN0 K7 R1 VMC_CLKN0 K7 R1 VMC_CLKN1 K7 R1 VMC_CLKN1 K7 R1
(20) VMC_CLKN0 CK VDD#R1 CK VDD#R1 (20) VMC_CLKN1 CK VDD#R1 CK VDD#R1
VMC_CKE0 K9 R9 VMC_CKE0 K9 R9 VMC_CKE1 K9 R9 VMC_CKE1 K9 R9
(20) VMC_CKE0 CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU (20) VMC_CKE1 CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU
VMC_ODT0 K1 A1 VMC_ODT0 K1 A1 VMC_ODT1 K1 A1 VMC_ODT1 K1 A1

(20) VMC_ODT0 ODT VDDQ#A1 ODT VDDQ#A1 (20) VMC_ODT1 ODT VDDQ#A1 ODT VDDQ#A1
VMC_CS0#0 L2 A8 VMC_CS0#0 L2 A8 VMC_CS1#0 L2 A8 VMC_CS1#0 L2 A8
(20) VMC_CS0#0 CS VDDQ#A8 CS VDDQ#A8 (20) VMC_CS1#0 CS VDDQ#A8 CS VDDQ#A8
VMC_RAS#0 J3 C1 VMC_RAS#0 J3 C1 VMC_RAS#1 J3 C1 VMC_RAS#1 J3 C1
(20) VMC_RAS#0 RAS VDDQ#C1 RAS VDDQ#C1 (20) VMC_RAS#1 RAS VDDQ#C1 RAS VDDQ#C1
VMC_CAS#0 K3 C9 VMC_CAS#0 K3 C9 VMC_CAS#1 K3 C9 VMC_CAS#1 K3 C9
(20) VMC_CAS#0 CAS VDDQ#C9 CAS VDDQ#C9 (20) VMC_CAS#1 CAS VDDQ#C9 CAS VDDQ#C9
VMC_WE#0 L3 D2 VMC_WE#0 L3 D2 VMC_WE#1 L3 D2 VMC_WE#1 L3 D2
(20) VMC_WE#0 WE VDDQ#D2 WE VDDQ#D2 (20) VMC_WE#1 WE VDDQ#D2 WE VDDQ#D2
VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#E9 E9
VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1
VMC_RDQS2 F3 H2 VMC_RDQS0 F3 H2 VMC_RDQS6 F3 H2 VMC_RDQS4 F3 H2
VMC_RDQS1 DQSL VDDQ#H2 VMC_RDQS3 DQSL VDDQ#H2 VMC_RDQS5 DQSL VDDQ#H2 VMC_RDQS7 DQSL VDDQ#H2
C7 DQSU VDDQ#H9 H9 C7 DQSU VDDQ#H9 H9 C7 DQSU VDDQ#H9 H9 C7 DQSU VDDQ#H9 H9
VMC_DM2 E7 A9 VMC_DM0 E7 A9 VMC_DM6 E7 A9 VMC_DM4 E7 A9

VMC_DM1 DML VSS#A9 VMC_DM3 DML VSS#A9 VMC_DM5 DML VSS#A9 VMC_DM7 DML VSS#A9
D3 DMU VSS#B3 B3 D3 DMU VSS#B3 B3 D3 DMU VSS#B3 B3 D3 DMU VSS#B3 B3
VSS#E1 E1 VSS#E1 E1 VSS#E1 E1 VSS#E1 E1
VSS#G8 G8 VSS#G8 G8 VSS#G8 G8 VSS#G8 G8
VMC_WDQS2 G3 J2 VMC_WDQS0 G3 J2 VMC_WDQS6 G3 J2 VMC_WDQS4 G3 J2
VMC_WDQS1 DQSL VSS#J2 VMC_WDQS3 DQSL VSS#J2 VMC_WDQS5 DQSL VSS#J2 VMC_WDQS7 DQSL VSS#J2
B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8
B
VSS#M1 M1 VSS#M1 M1 VSS#M1 M1 VSS#M1 M1 B
VSS#M9 M9 VSS#M9 M9 VSS#M9 M9 VSS#M9 M9

VSS#P1 P1 VSS#P1 P1 VSS#P1 P1 VSS#P1 P1
DDR3_RST T2 P9 DDR3_RST T2 P9 DDR3_RST T2 P9 DDR3_RST T2 P9
(20,21) DDR3_RST RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
VSS#T1 T1 VSS#T1 T1 VSS#T1 T1 VSS#T1 T1
R337 240/F_4L8 T9 R87 240/F_4L8 T9 R69 240/F_4L8 T9 R321 240/F_4L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9

VSSQ#E2 E2 VSSQ#E2 E2 VSSQ#E2 E2 VSSQ#E2 E2
J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8
L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9
J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1
L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9
100-BALL 100-BALL 100-BALL 100-BALL

SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12 K4W1G1646E-HC12 K4W1G1646E-HC12 K4W1G1646E-HC12
+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU

VMC_DQ[63..0]
(20) VMC_DQ[63..0]
VMC_MA[13..0]
(20) VMC_MA[13..0]
R336 R339 R86 R75 R67 R26 R320 R333
VMC_WDQS[7..0]
(20) VMC_WDQS[7..0]
4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4
VMC_RDQS[7..0]
(20) VMC_RDQS[7..0]
VREF_B0 VREF_B1 VREF_B2 VREF_B3 VREF_B4 VREF_B5 VREF_B6 VREF_B7
VMC_DM[7..0]
(20) VMC_DM[7..0]
VMC_BA[2..0] R335 C536 R340 C539 R85 C214 R72 C190 R68 C174 R24 C37 R319 C523 R334 C534
C (20) VMC_BA[2..0] C
4.99K/F_4 0.1U/10V_4 4.99K/F_4 0.1U/10V_4 4.99K/F_4 0.1U/10V_4 4.99K/F_4 0.1U/10V_4 4.99K/F_4 0.1U/10V_4 4.99K/F_4 0.1U/10V_4 4.99K/F_4 0.1U/10V_4 4.99K/F_4 0.1U/10V_4
Placement has to be close to VRAM

VMC_CLKP0 R89 56/J_4

C215 0.01U/16V_4
VMC_CLKN0 R88 56/J_4 C216 C540 C537 C187 C213 C541 C515 C205 C153 C533 C531 C535
VMC_CLKP1 R27 56/J_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
C48 0.01U/16V_4
VMC_CLKN1 R28 56/J_4
+1.5V_GPU +1.5V_GPU
C219 C542 C212 C188 C529 C526
10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6 10U/6.3V_6
D D

PROJECT : FH2A
1A
Madison_DDR3_B_512M
1 2 3 4 5 6 7 8
5 4 3 2 1
Backlight Control(LDS) BACKLIGHT POWER LED Panel POWER SWITCH(LVDS) 23

80mils
+3V_RUN +VIN V_BLIGHT
D 2A/63VS_1206 D
F5
1 2
R316
10K C488+ + C663 C489 C490
+3V_RUN
4.7U/25V_0805 4.7U/25V_0805 1000P/50V_4 0.1U/25V/X5R
BAS316 D18 U23

(8,32) MPWROK
5
BAS316 D19 2
(32) DLID#
4 DISPON 80mils
(17) PANEL_BKEN 1
LCDVCC_1 LCDVCC
F6 2A/63VS_1206
3
MC74VHC1G08DFT2G 1 2
1
item19 +3VPCU C507 C498 C499 C501
*0.1u/10V_4 0.1u/10V_4 33p/50V_4 4.7U/10V_8
2
D01
1 2 LID#
C LID# (32) C
R501 0/J_4
MR1 +3V_RUN
C3 C2 C1
APX9132H AI-TRG
2.2U/6.3V_6 AL003661006 +3V_S5
3
0.1U/10V_4 220p/10V_4
C514 U21 LCDVCC_1
1u/10V_6 6 1
U22 IN OUT
5
4 IN GND 2
(17) ENVDD 2
4 INT_LVDS_DIGON_U 3 5
ON/OFF GND
(8,32) MPWROK 1
R310 G5243AT11U
LVDS/CCD
3
+3V_RUN *MC74VHC1G08DFT2G AL005243001
item19
100K/J_4
R288 V_BLIGHT LCDVCC
4.7K_4 LCD_DDCCLK
+5V_RUN F4 CCD_POWER R287 CON1
MINI_PS-HS1 4.7K_4 LCD_DDCDAT +3V_RUN
C492 10u/10V_8 40 39
+
2 1 38 37 +3VPCU LCDVCC
C493 1000p/50V_4 R290 LCD_DDCCLK_C
*0_4_SHORT 36 35 DISPON
(17) LCD_DDCCLK 34 33
B
(17) LCD_DDCDAT R289 LCD_DDCDAT_C
*0_4_SHORT LVDS_VADJ B
32 31
CAMERA
C500 0.1u/10V_4 DMIC_CLK C497
29 DMIC_DAT 0.1U R294
USBP8_C- 30 27 *100K R293
F-04 USBP8_C+ 28
26 25 CCD_POWER
L2 *22R/J/0603
3
WCM-2012-900T
USBP8_C- TXLOUT0- 24 23 TXLOUT1-
(10) USBP8- 1 1 2 2 (17) TXLOUT0- 22 21 TXLOUT1- (17)
3
4 3 USBP8_C+ TXLOUT0+ TXLOUT1+
(10) USBP8+ 4 3 (17) TXLOUT0+ 20 19 TXLOUT1+ (17)
2 Q12
TXLOUT2- 18 17 TXLCLKOUT- INT_LVDS_DIGON_U 2 Q13 *2N7002E-T1-E3
(17) TXLOUT2- 16 15 TXLCLKOUT- (17)
DMIC_CLK TXLOUT2+ TXLCLKOUT+ *DTC144EU
(31) DMIC_CLK (17) TXLOUT2+ 14 13 TXLCLKOUT+ (17)
C504 12 11
1
10 9
33p/50V_4 8 7
D-13 6
4
5
3
42
41
DMIC_DAT 2 1
(31) DMIC_DAT
C503 C496
*1000PF
33p/50V_4
D-13
LCD_CON40P
A 87241-4001-40P-LUV A
(17) BIA_PWM R291 *0/J_4 LVDS_VADJ DFWF40MR000
(32) CONTRAST R292

*0_4_SHORT
C495
0.1U/10V_4
PROJECT :FH2A
1A
LCD/LED Panel/CCD
5 4 3 2 1
5 4 3 2 1
CRT CONN/DDC LEVEL SHIFT

40mils TBD CN5500 FOOTPRINT
24
C5 0.1U/10V_4
F1
5V_CRT2 CN3
16
+5V_RUN 2 1 2 3
CH411DPT D1
1.1A/6V_POLY CRT
6
D EXT_CRT_RED L5 BLM15BA470SS1D_4 CRT_RED_L T72 D
(17) EXT_CRT_RED 1 11
7
EXT_CRT_GRE L3 BLM15BA470SS1D_4 CRT_GRE_L 2 12
(17) EXT_CRT_GRE
8
EXT_CRT_BLU L1 BLM15BA470SS1D_4 CRT_BLU_L 3 13
(17) EXT_CRT_BLU
9
4 14
R3 C10 R2 C8 R1 C7 C6 C9 C11 10
5 15
150/F_4 2.2P/50V_4 150/F_4 2.2P/50V_4 150/F_4 2.2P/50V_4 2.2P/50V_4 2.2P/50V_4 2.2P/50V_4
17
DFDS15FR039
DSUB-070546FR015S272-15P-V-SMT
U1
5V_CRT2 1 16 CRT_VSYNC_Q R4 27/F_4 CRT_VSYNC_R L4 BLM18BA220SN1D CRT_VSYNC_L
VCC_SYNC SYNC_OUT2 CRT_HSYNC_Q R5 27/F_4 CRT_HSYNC_R L6 BLM18BA220SN1D CRT_HSYNC_L
SYNC_OUT1 14
+3V_RUN 7 VCC_DDC
C26 0.22U/10V_4 8 BYP EXT_CRT_VSYNC C494 C502
SYNC_IN2 15 EXT_CRT_VSYNC (17)
5V_CRT2 2 13 EXT_CRT_HSYNC 5V_CRT2
VCC_VIDEO SYNC_IN1 EXT_CRT_HSYNC (17)
10P/50V_4 10P/50V_4
R19 R6
CRT_RED_L 3 10 CRT_DDCCLK
VIDEO_1 DDC_IN1 CRT_DDCCLK (17)
CRT_GRE_L 4 11 CRT_DDCDAT 2.2K/J_4 2.2K/J_4
VIDEO_2 DDC_IN2 CRT_DDCDAT (17)
CRT_BLU_L 5 VIDEO_3 CRTDCLK
DDC_OUT1 9
6 12 CRTDDAT
GND DDC_OUT2
CM2009 +3V_RUN
C491 C505
+5V_RUN +3V_RUN
C C
10P/50V_4 10P/50V_4
CRT_DDCCLK R14 2.2K/J_4

C4 C27 CRT_DDCDAT R15 2.2K/J_4
0.1U/10V_4 0.1U/10V_4
PLACE AC CAP
CLOSE TO CONNECTOR
HDMI
EXT_HDMI_TXCN C640 0.1U/10V_4 TXC_HDMI-
(17) EXT_HDMI_TXCN
EXT_HDMI_TXCP C641 0.1U/10V_4 TXC_HDMI+
(17) EXT_HDMI_TXCP
EXT_HDMI_TXDN0 C650 0.1U/10V_4 TX0_HDMI-
(17) EXT_HDMI_TXDN0
EXT_HDMI_TXDP0 C647 0.1U/10V_4 TX0_HDMI+
(17) EXT_HDMI_TXDP0
(17) EXT_HDMI_TXDN1
(17) EXT_HDMI_TXDP1
(17) EXT_HDMI_TXDN2
(17) EXT_HDMI_TXDP2
+5V_RUN
B B
MAKE SURE THE MOSFET IS OFF R474 100K_4 R477 R476 R471 R470 R478 R479 R469 R468
CS41002JB20
DURING SYSTEM IN STANDBY
2
499_4 499_4 499_4 499_4 499_4 499_4 499_4 499_4

1 3 CN5
CS14992FB24 CS14992FB24 CS14992FB24 CS14992FB24 20
CS14992FB24 CS14992FB24 CS14992FB24 CS14992FB24 TX2_HDMI+ SHELL1
1 D2+ SHELL2 21
PLACE PULL DOWN RESISTORS CLOSE TO TX2_HDMI- 3 22
Q22 TX1_HDMI+ D2- SHELL3
DIFFERENTIAL PAIRS CONNECTED TO SOLID 4 D1+ SHELL4 23
2N7002E TX1_HDMI- 6
D-11 GROUND FLOOD WHICH IS CONTROLLED TX0_HDMI+ 7
D1-
D0+
BY THE FET TX0_HDMI- 9 D0-
+5V_RUN 2
AVOID STUBS TO ALL DIFFERENTIAL TRACES D2 Shield
+5V_HDMIC 5
+5V_RUN +5V_RUN D1 Shield
D0 Shield 8
+3V_RUN TXC_HDMI+ 10 11
CK+ CK Shield
1
TXC_HDMI- 12 17
*BAV99W F8 CK- GND
*BAV99W HDMI_SCLK 1
1 3 FUSE1A6V_POLY
DP_AUX PULLUP HDMI_SDATA
3 HDMI_SCLK
POWER RAIL MUST 15 13
2
R203 R204 2 HDMI_SDATA DDC CLK CE Remote
2 16 DDC DATA NC 14
BE UP BEFORE 10K_4 2.2K/J_4 D6
2
CORE POWER RAIL D7

+3V_RUN +3V_RUN
(17) EXT_HDMI_SCL 1 3 HDMI_SCLK +5V_HDMIC 18 +5V
OPTIONAL ESD PROTECTION DIODES FOR DDC/AUX
R278
2N7002E Q5 4.7K_4 R215
R205 *0/J_4 100K_4 HDMI_DET 19
C639 C638 HP DET
A +3V_RUN *0.1U/10V_4 *1U_6 A
(17) EXT_HDMI_HPD
3
HDMI CONN
+5V_HDMIC Q29 DFHD19MR109
2N7002E HDMI-C12825-11908-L-19P-V
3
2 R466 40.2K/F_4
Q7 2 1 2 HDMI_DET
R206 R209 MMBT3904
1
10K_4 2.2K/J_4
1
2
R467 D22
1
200K_4
(17) EXT_HDMI_SDA 1 3 HDMI_SDATA CS42002FB12
UDZ6.2B
PROJECT :FH2A
2
2N7002E Q6 Size Document Number Rev

R210 *0/J_4 1A
CRT CONN/HDMI
5 4 3 2 1
A B C D E
Card Reader 25
XD_CLE/CF_D3 43
R253 10K/J_4 U18 42
XD_CE#/CF_D11
+3V_RUN 13 CF_CD# XD_ALE/CF_D4 41
14 GPIO0
15 40 SP16
CF_D10 SD_DAT2/XD_RE#/CF_D12 SP15
16 CF_D9 SD_DAT3/XD_WE#/CF_D5 39
17 CF_D2 XD_RDY/CF_D13 38
18 CF_D8/SM_CD# SD_DAT4/XD_WP#/CF_D6 37
19 CF_D1/XD_CD#
SD_WP 20 36 SD_CMD
SD_CD# CF_D0/SM_WPM#/SD_WP SD_CMD
21 CF_A0/SD_CD# SD_DAT5/XD_D0/CF_D14 35
22 34 SP11
XD-D4 CF_DMACK# SD_CLK/XD_D1/MS_CLK/CF_D7 SP10
23 CF_A1/XD_D4 SD_DAT6/XD_D7/MS_D3/CF_D15 31
24 CF_DMARQ CF_CS0# 30
29 MS_CD#
R269 6.19K/F_4 RREF MS_INS#/CF_IORD# MS_DATA2
2 RREF SD_DAT7/XD_D2/MS_D2/CF_IOWR# 28
27 SP7
SD_DAT0/XD_D6/MS_D0/CF_RST# SP6
SD_DAT1/XD_D3/MS_D1/CF_IORDY 26
L34 25 SP5
USBP12- XD_D5/MS_BS/CF_A2
(10) USBP12- 3 3 4 4 4 DM
USBP12+ 2 1 5 1 10mil at least
(10) USBP12+ 2 1 DP AV_PLL_IN C466 C445
*WCM-2012-900T 0.1u/10V_4
1U/6.3V_4
(10) CLK_48M_CR
C474 *18p/50V_4 XI R273 48 10 VREG
*0_4 XTLI VREG_OUT 20mil at least R257 *short_6
3V_IN 8 +3V_RUN
3 Vreg out 1.8V from Internal 3.3VLDO
Y4 R274 A3V3_ IN C455
*12MHz *270K_4 33 20mil at least C454
D3V3_ IN C458 0.1u/10V_4 4.7U/6.3V_6
47 XTLO
C473 *18p/50V_4 XO 0.1u/10V_4 C459 *0.1u/10V_4
D3V3_OUT 11
+3V_RUN
MODE_SEL 45 MODE_SEL 0.1u/10V_4 C439 C456
4.7U/6.3V_6
7 +3V_RUN +3VCARD
R275 C472 A3V3_OUT
0/F_4
CARD_3V3_OUT 9 20mil at least +3VCARD
*47P/50V_4
AG33 6
46 C464 C457 C665 C438 C437 C446
AG_PLL C441
DGND2 32
44 12 *0.1u/10V_4 *10U/10V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
PLTRST# RST# DGND1 *0.1u/10V_4
(4,10,16,26,29,33) PLTRST#
C471 0.1u/10V_4
Realtek RTS5159-GR
1U/6.3V_4
1 1
As close U8203 pin9 as possible
XD-D4 R255 short_4 SD_DAT1
For 5158E
+3VCARD
SP7 R265 short_4 MS_DATA0_SD_DAT0
CN7
14 SD-VCC
MS_DATA0_SD_DAT0 17
SD_DAT1 SD-DAT0
18 SD-DAT1
SD_DAT2 19
SP6 R264 short_4 MS_DATA1 SD_DAT3 SD-DAT2
11 SD-DAT3
SD_CLK 15
SD_CMD SD-CLK
12 SD-CMD
SD_CD# 20
SD_WP SD-C/D
22 SD-WP
13 SD-GND
16 SD-GND
SP16 R276 short_4 SD_DAT2
9 MS-VCC
MS_DATA0_SD_DAT0 4
MS_DATA1 MS-DATA0
3 MS-DATA1
SP5 R256 short_4 MS_BS MS_DATA2 5
MS_DATA3 MS-DATA2
7 MS-DATA3
MS_CLK 8
MS_CD# MS-SCLK
6 MS-INS
MS_BS 2 23
SP15 R272 short_4 SD_DAT3 MS-BS GND
1 MS-GND GND 21
10 MS-GND
R268 short_4 SD_CLK CARD_READER_PROCONN

DFHD23MS0B6
SP11 R270 short_4 MS_CLK 3IN1-SD-47265-001-23P
1
F-04 C460
22P +3VCARD +3VCARD
2
C465 C469 C470

SP10 R266 short_4 MS_DATA3 C467 R271 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
4.7U/6.3V_6 150K/F_4
PROJECT : FH2A
1A
Card Reader RTS5159
A B C D E
A B C D E
LAN
R43
+1.05V_LAN
2.49K/F
VDD33 +1.05V_LAN VDD33 VDD33
CLK_LAN_REQ# 1
VDD33
X'tal 25MHz
LAN_XTAL2
R17
LAN EEPROM
EECS_SCL
LED1_EESK
1
U4
CS VCC 8
VDD33
26
2 2 SK DC 7
R46 *10K 1M/F_4 Y1 EEDI_SDA 3 6 C189
LAN_XTALI LED3_EDO DI ORG
2 1 4 DO GND 5 *0.1u/10V_4
PCIE_WAKE# 1 2
LAN_XTAL2
VDD33
LAN_XTALI
R59 *10K 25MHz *HT93LC46A
4 R329 1K C58 C59
4
LED1_EESK 27P/50_4 27P/50_4
U24 Transformer
49
48
47
46
45
44
43
42
41
40
39
38
37
+1.05V_LAN_S L38
R323 75/F TXCT0 24 TXCT0
AVDD33
CKXTAL2
CKXTAL1
GND
AVDD33(NC)
RSET
AVDD1
AVDD3(AVDD1)
VDD1(NC)
LED0
VDD3
GPO/SMBALERT
LED1/EESK
VDD33 R325 75/F TXCT1 MCT0
1 TCT0
VDD33 R327 75/F TXCT2 23 RJ45-TX0+
+1.05V_LAN R330 75/F TXCT3 MDI0+ TX0+
2 TD0+
R58 22 RJ45-TX0-
MDI0+ MDI0- TX0-
1 MDIP0 SROUT1 36 *0_4_SHORT R58 For Enable Switch Regulator. 3 TD0-
MDI0- 2 35 C525 21 TXCT1
3
MDIN0 VDDSR
34 R56 For Disable Switch Regulator. 1000P 4
MCT1
MDI1+ AVDD1(NC) VDDSR Enable +1.05VLAN_S R56 *0_NC 3KV TCT1 RJ45-TX1+
4 MDIP1 ENSR 33 TX1+ 20
MDI1- 5 32 EEDI_SDA 2 1 1808 MDI1+ 5
MDIN1 EEDI/SDA LED3_EDO R66 10K TD1+ RJ45-TX1-
6 AVDD1(NC) LED3/EDO 31 TX1- 19
MDI2+ 7 RTL8111EL 30 EECS_SCL 2 1 MDI1- 6
MDI2- MDIP2(NC) EECS/SCL R76 10K TD1- TXCT2
8 MDIN2(NC) DVDD1 29 +1.05V_LAN MCT2 18
VDD33 9 28 C137 *6.8P_NC MDI3+ 7
AVDD1(NC) LANWAKEB PCIE_WAKE# (8,33) TCT2
MDI3+ 10 27 VDD33 C149 *6.8P_NC MDI3- 17 RJ45-TX2+
MDI3- MDIP3(NC) VDD3 ISOLATE# C109 *6.8P_NC MDI2+ MDI2+ TX2+
11 MDIN3(NC) ISOLATEB 26 8 TD2+
3 C119 *6.8P_NC MDI2- RJ45-TX2-
3
SMBDATA(NC)
12 AVDD3(NC) PERSTP 25 PLTRST# (4,10,16,25,29,33) TX2- 16

SMBCLK(NC)
C83 *6.8P_NC MDI1+ MDI2- 9

REFCLK_M
TD2-
REFCLK_P
C92 *6.8P_NC MDI1- TXCT3

CLKREQB
Check point: C56 *6.8P_NC MDI0+ MCT3 15

GNDTX
10
DVDD1
EVDD1
1. LOM_CLK_REQ# and PCIE_WAKE# needsto be pull up TCT3

HSON
HSOP
+3V_RUN C65 *6.8P_NC MDI0- RJ45-TX3+

HSIN
14
HSIP
+1.05V_LAN C73 MDI3+ TX3+

by PCH side 11 TD3+
Reserver for EMI 0.01U 13 RJ45-TX3-
2. PCIE_TX must have AC cap at PCH side 25 MDI3- 12
TX3-
13
14
15
16
17
18
19
20
21
22
23
24
R71 TD3-
1K/F LFE9276C-R
+1.05V_LAN
R61 *100/F RJ45
ISOLATE#
(10) CLK_LAN_REQ# LAN_PCIE_PWR_CTRL# (32) VDD33
PCIE_RXN6_R
PCIE_RXP6_R
R70
CON5
15K/F 2 1
(10) PCIE_TXP6
1
R40 RJ45-TX3-
(10) PCIE_TXN6 8
D2 *RB501V-40_NC RJ45-TX3+
10K C530 C138 RJ45-TX1- 7
(10) CLK_PCIE_LOMP 6
Isolate# is for power saving. 4.7U 0.1U RJ45-TX2-
(10) CLK_PCIE_LOMN 5
C527 0.1U 6.3 10 RJ45-TX2+
(10) PCIE_RXP6
2
10 It needs to pull low when system state in S3, S4, and S5. X5R X5R RJ45-TX1+ 4 12
3 11
2 (10) PCIE_RXN6
C528 0.1U
10
pull high when system at S0 state RJ45-TX0-
RJ45-TX0+ 2
1
10
9
2
GND_LAN
RJ45
LAN Power VDD33 R338 *short_8 +3V_S5

Place Close to LAN chip,
RJ45-100086FR008S103ZL-8P
DFTJ08FR197
pin 34 and 35
0603
VDD33 R322 0
+1.05V_LAN_S
+1.05V_LAN 0603
+1.05V_LAN R65 0
IND SMD 4.7UH 30% 1A( LQH32PN4R7NN0L) 0603

R332 0
L24
C519 C522 C129 C64 C532 C94 C520 C121 C57 C517 C518 C91 C521
C118 C141 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U C103 C108 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U GND_LAN
4.7U 0.1U 10 10 10 10 10 10 10 1U 0.1U 10 10 10 10 10 10
6.3 10 X7R X7R X7R X7R X7R X7R X7R 6.3 10 X5R X5R X5R X5R X5R X5R
1 X5R X7R X5R X5R 1
For L50, C420, C62 need to check layout guild Close to pin 3, 6, 9, 13, 29, 41 and 45 Place connect to Pin21 Place Close to LAN chip, pin 12, 27, 39, 42, 47 48
PROJECT : FH2A
1A
REQ by layout LAN_RTL8111E-GR/RJ45
A B C D E
5 4 3 2 1
2.5" SATA HDD

CN6
SATA ODD
27
1
GND1
TXP
TXN
2
3
SATA_TXP0_C C480
SATA_TXN0_C C479
0.01U/25V_4
0.01U/25V_4
SATA_TXP0 (9)
SATA_TXN0 (9)
ODD CONN
D GND2 4 D
5 SATA_RXN0_C C477 0.01U/25V_4 CON6
RXN SATA_RXN0 (9)
6 SATA_RXP0_C C475 0.01U/25V_4 1 8
RXP SATA_RXP0 (9) GND DP 3A/32VS_1206
F7
GND3 7
0.01U/25V_4 C333 SATA_TXP1_C 2 9 ODD_5V
80 mils 1 2
(9) SATA_TXP1 TX VCC5 +5V_RUN
8 Place these SATA AC Cap close to device , not SB 0.01U/25V_4 C332 SATA_TXN1_C 3 10
3.3V (9) SATA_TXN1 TX# VCC5
9 f3_18x1_52-2_665
3.3V C625 C626 C627
3.3V 10 4 GND MD 11
11 0.1U/10V 0.1U/10V 10U/10V_8
GND 0.01U/25V_4 C327 SATA_RXN1_C
GND 12 (9) SATA_RXN1 5 RX# GND 12
13 0.01U/25V_4 C324 SATA_RXP1_C 6 13
GND
5V 14 0.94A(80mils) +5V_SATA
(9) SATA_RXP1 RX GND
GND 14
5V 15 7 GND GND 15
5V 16 GND 16
GND 17 GND 17
25 XX RSVD 18
26 XX GND 19
20 +5V_SATA +5V_RUN
12V F10 2A/63VS_1206
23 XX 12V 21
24 XX 12V 22 1 2
C656 C655 C658

SATA_HDD
SLS-13DD1G
sata-127072fr022g212zr-22p-r *0.1u/10V_4 0.1u/10V_4 10u/10V_8
C DFHS22FR183 DFHS13FR026 C
bat-sls-13dd1g-13p-r-smt
Hole H32
CN15 CRT Bare Cu
Decoupling Cap
H14 H10 H24 H19 H7 H9 H33 H12 H30 H31 H3 H6
*FH2A *FH2A *FH2A *FH2A *FH2A *FH2A *FH2A *FH2A *FH2A *FH2A *FH2A *FH2A
EMI request
*FH2A
1
2
3
4
+VIN
B B
1
1
GND_LAN
H35 H21 H11 H23 H26 FAN C111 C657 C583 C358 C463 C476 C516 C670 C385
*FH2A *FH2A *FH2A *FH2A *FH2A H15 H36
*FH2A *FH2A 0.1U/25V_4 *.1U/25V_4 *.1U/25V_4 *.1U/25V_4 *.1U/25V_4 *.1U/25V_4 *.1U/25V_4 *.1U/25V_4 *.1U/25V_4
1
H1 H4 H17 H22 H18 H20 H28 H29

EMI(Decoupling Cap)
1 9 1 9 1 9 1 9 1 9 1 9 H34 1 9 1 9
2 8 2 8 2 8 2 8 2 8 2 8 2 8 2 8 +3V_RUN +3V_RUN +5VPCU
3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7
C316 C328 C257

4
5
6
4
5
6
4
5
6
4
5
6
4
5
6
4
5
6
4
5
6
4
5
6
1
*FH2A 0.1U/16V_4 0.1U/16V_4 0.1U/16V_4

A A
H2 H25 H5
1 9 1 9 H8 H16 H27
2 8 2 8 1 9 1 9 1 9
3 7 3 7 2 8 2 8 2 8 Quanta Computer Inc.
10 3 7 3 7 3 7
1
*FH2A PROJECT : FH2A
4
5
6
4
5
6
*FH2A
4
5
6
4
5
6
4
5
6

1A
HDD/ ODD/HOLE
5 4 3 2 1
5 4 3 2 1
B
+3V_RUN
1
300mA
3
VCC3_BT
VCC3_BT
BuleTooth (BTM) 28
VCC3_BT
Q69
2
R791 220K_4 AO3413 R490
RF_SW_R
D C708 22R/J/0603 D
0.1U_4
CON4
3
C-05 1
L35 *WCM-2012-900T 2
1
1 3 2 C669 C666 C482 2 2
(10) USBP9+ 1 1 3
(10) USBP9- 3 3 4 4 4
Q68 Q26 0.1U/10V 10U/6.3V_6 *10U/6.3V_6 5
2
2N7002E 6
DTC144EU
1
2
C709 Bluetooth CN
0.22uF_4 87213-0600-6p-l
P1 *1N4148WS
1 2
BT_ON R277 4.7K/J_4

(32) BT_ON
C710
0.1U_4
C C
USB Connector
+5VSUS +5V_USB +5V_USB CON8
L41
F9 DLW21HN900SQ2L 60mils 1 4
MINI_PS-HS1 USBP2- USBP2_R- 1 4
(10) USBP2- 3 3 4 4 2 2 GND 5
2 1 USBP2+ 2 USBP2_R+
(10) USBP2+ 2 1 1 3 3 GND 6
GND 7
GND 8
C659 + C653 U33 USB

C652 USBP2_R- 1 6 USBP2_R+ USB-020173MR004XX52ZR-4P-R-V
4.7u/10V_6 150U/10V 0.1u/10V_4 Z1 Z4 +5V_USB
2 GND VB 5
3 Z2 Z3 4
*IP4220CZ6
Place close to the CONN side
B B
+5V_USB2 CON10
+5VSUS +5V_USB2 L42
DLW21HN900SQ2L 60mils 1 4
F11 USBP4- USBP4_R- 1 4
(10) USBP4- 3 3 4 4 2 2 GND 5
MINI_PS-HS1 USBP4+ 2 2 USBP4_R+
(10) USBP4+ 1 1 3 3 GND 6
2 1 GND 7
GND 8
C664 + C661 USB

C662 U34 USB-020173MR004XX52ZR-4P-R-V
4.7u/10V_6 150U/10V 0.1u/10V_4 USBP4_R- 1 6 USBP4_R+
Z1 Z4 +5V_USB2
2 GND VB 5
3 Z2 Z3 4
*IP4220CZ6
+5V_USB3
L33 JP1
DLW21HN900SQ2L 60mils
+5VSUS +5V_USB3 USBP1- USBP1_R- 1
(10) USBP1- 2 2 1 1 2
USBP1+ 3 4 USBP1_R+
F3 (10) USBP1+ 3 4 3
MINI_PS-HS1 4
A 2 1 53048-0410 A
53398-0410-4P-L
C461 DFHD04MR701
C462
4.7u/10V_6 + U16
C660 0.1u/10V_4 USBP1_R- 1 6 USBP1_R+
150U/10V 2
Z1
GND
Z4
VB 5 +5V_USB3 Quanta Computer Inc.
3 Z2 Z3 4
*IP4220CZ6
PROJECT : FH2A
1A
USB/BLUE TOOTH
5 4 3 2 1
5 4 3 2 1
29
D D
MINI CARD (WLAN) +1.5V_RUN +1.5V_WLAN
R191 *0_8
+3V_RUN +3V_RUN
CON7
51 Reserved +3.3V 52
49 Reserved GND 50
47 Reserved +1.5V 48
45 Reserved LED_WPAN# 46
43 Reserved LED_WLAN# 44
41 Reserved LED_WWAN# 42
39 Reserved GND 40
37 38 R465 *0
Reserved USB_D+ R464 *0 USBP11+ (10)
35 GND USB_D- 36 USBP11- (10)
(10) PCIE_TXP2 33 PETp0 GND 34
(10) PCIE_TXN2 31 PETn0 SMB_DATA 32
29 30 PLTRST#_R R460
GND SMB_CLK PLTRST# (4,10,16,25,26,33)
27 28 *0_4_SHORT
GND +1.5V
(10) PCIE_RXP2 25 PERp0 GND 26
23 24 R457 *10K +3V_RUN
(10) PCIE_RXN2 PERn0 +3.3Vaux
21 GND PERST# 22
C
(10) CLK_LPC_DEBUG 19 Reserved Reserved 20 RF_EN# (32) C
17 18 item55 D21 BAS316
T101 Reserved GND
15 GND Reserved 16 LAD0 (9,32)
(10) CLK_PCIE_MINI2P 13 REFCLK+ Reserved 14 LAD1 (9,32)
(10) CLK_PCIE_MINI2N 11 REFCLK- Reserved 12 LAD2 (9,32)
9 GND Reserved 10 LAD3 (9,32)
(10) MINI2CLK_REQ# 7 CLKREQ# Reserved 8 LFRAME# (9,32)
T95 5 Reserved +1.5V 6
T92 3 Reserved GND 4
T90 1 WAKE# +3.3V 2
67910-0002
DFHD52MS049
R456 MIPCIEXP-AS0B22X-S80N-XX-52P
*22
C631
*10P
+3V_RUN
C636 C635 C319 C634 C637
*10u/10V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
B B
A A

PROJECT : FH2A
1A
MINI CARD(WLAN/3G)/XDP
5 4 3 2 1
5 4 3 2 1
Touch Pad
Keyboard(KBC)
+5V_TP 40mils
F2
+5V_RUN
SW2
DHP00533B00
sw-tme-532-v-6p
30
1 2 SWR# 3 1
4 2
C396 1.1A/6V_POLY C409 5
6
0.1u/10V_4 *0.1u/10V_4 +5V_RUN
D D
CON3 R187 R194

1 sw-tme-532-v-6p
2 SWL# 4.7K_4 4.7K_4 SW1 DHP00533B00
3 +5V_TP SWL# 3 1
CN1 4 TPDATA_8 L28 NHCB2012KF-131T10/1A/130ohm_8 4 2
TPDATA (32)
27 5 TPCLK_8 L29 NHCB2012KF-131T10/1A/130ohm_8 5
TPCLK (32)
MY0 1 6 SWR# 6
(32) MY0
MY1 2
(32) MY1
MY2 3 88501-0601-6P-L-AQ1 C321 C322
(32) MY2
MY3 4 88502-06XX-6P-L-SMT
(32) MY3
MY4 5 DFFC06FR022 C320 C325 10p/50V_4 10p/50V_4
(32) MY4
MY5 6 0.1u/10V_4 0.1u/10V_4
(32) MY5
MY6 7
(32) MY6
MY7 8
(32) MY7
MY8 9
(32) MY8
MY9 10
(32) MY9
MY10 11
(32) MY10
MY11 12
(32) MY11
MY12 13
(32) MY12
MY13 14
(32) MY13
MY14 15
(32) MY14
MY15 16
(32) MY15
MY16 17
(32) MY16
MY17 18
(32) MY17
MX0 19
(32) MX0
MX1 20
(32) MX1
MX2 21
(32) MX2
MX3 22
(32) MX3
MX4 23
(32) MX4
MX5 24
(32) MX5
MX6 25
(32) MX6
MX7 26
(32) MX7
28
KB_CONN
C 88513-2641-26P-L-smt C
DFFC26FR016
For EMI Reserve Caps for debug

+3V_RUN
MY3
CP4
7 8
CP3
8 7 MX7
LED
MY2 5 6 6 5 MX6
MY1 3 4 4 3 MX5 R279
MY0 1 2 2 1 MX4 10K
*100p_8P4R *100p_8P4R
CP1 CP6 SATA_LED

MY15 7 8 7 8 MY8
MY14 5 6 5 6 MY9
Blue
3
MY13 3 4 3 4 MY10
2
MY12 1 2 1 2 MY11 Q11 LTST-C190TBKT/BLUE
2 DDTC144EUA-7-F LED4
(9) SATA_LED#
*100p_8P4R *100p_8P4R 1 3 SATA_LED#_D 1 2 R286 2 1 220_6
HDD/ODD +5V_RUN
CP2 CP5 Q10 BEBL0088Z00
1
MX0 8 7 7 8 MY4 2N7002E
MX1 6 5 5 6 MY5
MX2 4 3 3 4 MY6
MX3 2 1 1 2 MY7 Blue
*100p_8P4R *100p_8P4R
R280
CAPSLED# 1N4148WS LTST-C190TBKT/BLUE LED5 1 2 2 1 220_6
CAPS LED (32) CAPSLED#
D17 BEBL0088Z00
+5V_RUN
B
Blue B
R281
NUMLED# 1N4148WS LTST-C190TBKT/BLUE LED6 1 2 2 1 220_6
NUM LED (32) NUMLED#
D16 BEBL0088Z00
+5V_RUN
Blue
R285
LED_WLAN#1N4148WS LTST-C190TBKT/BLUE LED3 1 2 2 1 220_6
WLAN (32) LED_WLAN#
D14 BEBL0088Z00
+5V_RUN
Blue
AMBER
BE0R0025Z00 R284
BAT_LED1# LTST-C191KFKT/AMBER LED1 1 2 2 1 220_6 +3VPCU
(32) BAT_LED1#
R283
Battery (32) BAT_LED0#
BAT_LED0# 1N4148WS LTST-C190TBKT/BLUE LED7 1 2 2 1 220_6 +5V_RUN
D15 BEBL0088Z00
Blue
Blue
R282 220_6
PWRLED0# 1N4148WS LTST-C190TBKT/BLUE LED2 1 2 PWRLED0_R# 2 1 +5VSUS
(32,33) PWRLED0#
D12 BEBL0088Z00
Power Status
A A

PROJECT : FH2A
1A
KB/TOUCH PAD/LED
5 4 3 2 1
A B C D E
ALG_LI_VR_R
MIC GNDAUD
ALG_LI_VR_L
Codec ALC269
C487
*10P/50V_4
ALG_MIC_SENSE
EMI
AR22
2.2K/F_4
AR24
2.2K/F_4 ALG_LI_VR_L AR15
Rc
*0/J_4 AR16
Re
0/J_4 GNDAUD
31
8 5
AC34 4.7U/10V/8
Cd
4
3 MICIN_JACK_R AL4 HCB1608KF-601T10 AR23 1K/F_4
1 2ALG_MAIN_IN_R ALG_LI_VR_L AR18
Rd 0/J_4
AC33 4.7U/10V/8 AC38 *10U/6.3V/X5R/0805
6
2 MICIN_JACK_L AL1 HCB1608KF-601T10 AR21 1K/F_4
1 2ALG_MAIN_IN_L
U23 Ra Rb Rc Rd Re Ca Cb Cc Cd Da La Ua
7 1 GND_MIC ALG_LI_VR_R
GNDAUD
ACON2
ALC269Q-VA
4
DFTJ06FR141 ALG_HP_L
C-02 4
phjk-2sj-s351-015-8p-v AR20
0 AC25 AC26
ALC269Q-VB ALG_HP_R AC19
0603 *100P/50V/NPO *100P/50V/NPO AC23
GNDAUD 0.1U/25V/X7R 2.2U/16V/X5R
AC27 ALG_VREF
AC28
GNDAUD GNDAUD GNDAUD 2.2U/16V/X5R
2.2U/16V/X5R AR12
PWR_AUD AC22 AC35
0_6 0.1U/25V/X7R 1U/6.3V_4
HP GNDAUD
U19
ALC269Q-VA6-GR
36
35
34
33
32
31
30
29
28
27
26
25
C486 EMI AL000269007
*10P/50V_4 GNDAUD
CBP
CPVEE
HP-OUT-L
AVSS1
AVDD1
CBN
HP-OUT-R
CPVREF
MIC1-VREFO-R
MIC2-VREFO
MIC1-VREFO-L
VREF
8 5 ALG_HP_SENSE
4 GNDAUD
3 HPOUTR_CN AL2 HCB1608KF-601T10ALG_HEADPHONE_RPR193 47R/F_4 ALG_HP_R
6 10U/6.3V/X5R/0805 37 24
HPOUTL_CN AL3 HCB1608KF-601T10ALG_HEADPHONE_LPR194 47R/F_4 ALG_HP_L PWR_5VAMP AC17 AVSS2 LINE1-R
2
7 1 GND_HP GNDAUD AC21 0.1U/25V/X7R 38 23
AVDD2 LINE1-L
ACON3 39 22 ALG_MAIN_IN_R
DFTJ06FR141 PVDD1 MIC1-R
AL000269007
phjk-2sj-s351-015-8p-v AC15 AC16 ALG_SPKOUTL+ 40 21 ALG_MAIN_IN_L
AC37 AC36 AR26 AR25 4.7U/25V/X5R/0805 0.1U/25V/X7R SPK-L+ MIC1-L
AR17 100P/50V/NPO 100P/50V/NPO *1K/F/4 *1K/F/4 ALG_SPKOUTL- 41 20
SPK-L- MONO-OUT PR64
*short
42 19 20K/F/4 GNDAUD
PVSS1 JDREF
43 PVSS2 Sense B 18 T71
GNDAUD GNDAUD GNDAUD GNDAUD GNDAUD
ALG_SPKOUTR- 44 17
SPK-R- MIC2-R
3 PWR_5VAMP 3
ALG_SPKOUTR+45 16
SPK-R+ MIC2-L
46 15
SPKR AC20 AC18 T70 EAPD# 47

PVDD2 LINE2-R
14
GPIO0/DMIC-DATA
SPDIFO2/EAPD LINE2-L
GPIO1/DMIC-CLK
4.7U/25V/X5R/0805 0.1U/25V/X7R
48 13 SENSE_A AR9 39.2K/F_4 ALG_HP_SENSE
ACON1 SPDIFO Sense A
SDATA-OUT
SPKOUTL-_CN *0_4_SHORT AR4 ALG_SPKOUTL-
SDATA-IN
4 49
DVDD-IO
4 PGND
PCBEEP
RESET#
BIT-CLK
5 3 SPKOUTL+_CN *0_4_SHORT AR3 ALG_SPKOUTL+
DVDD1
DVSS2
5 3
SYNC
6 2 SPKOUTR+_CN *0_4_SHORT AR2 ALG_SPKOUTR+ AR10 20K/F_4 ALG_MIC_SENSE
PD#
6 2 SPKOUTR-_CN *0_4_SHORT AR1 ALG_SPKOUTR-
1 1 A
TUNER-PWR AC2
AGND
10
11
12
DFHD04MR000 470P/50V/X7R
88263-040L-4P-L AC4
470P/50V/X7R AC1
DGND
470P/50V/X7R
GNDAUD
(23) DMIC_DAT
AC3 AMP_PD# AR19
470P/50V/X7R AR8 short
(23) DMIC_CLK
33/J_4
C-02
(9) ACZ_SDOUT_R +5V_RUN PWR_5VAMP
AR13 0/J_4 AR11
(9) ACZ_BIT_CLK_R
BEEP (9) ACZ_SDIN0
(9) ACZ_SYNC_R
short
F-04 (9) ACZ_RST#_R

AR6 18K/4 ALG_BEEPIN_B ALG_BEEP_IN
(9) PCBEEP
AC8 AC5 AC12 AC13 ALG_BEEP_IN
0.1U/25V/X7R 10p/50V_4 22P/50V_4 22P/50V_4
50 50 *0_4_SHORT AR7
2 D-13 +3V_RUN
2
AC9 AR5 AC10
100P/50V/NPO 1K/F_4 *0.01U/50V/X7R AC6 AC11
+3V_RUN*10P/50V/NPO *22P/50V/NPO
C481 AC7
0.1U/25V/X7R 10U/6.3V/X5R/0805
C478
0.1U/25V/X7R
VOLMUTE D02
D14
+5V_RUN +5V_RUN +3V_RUN
C-02 L36
R189
La
R502 *BLM18PG121SN
1
4.7K_4 *AO3413
*10K/J_4
Q70 +5V_RUN Da D13 PWR_AUD
3
EAPD ALG_HEADPHONE_R 1SS355

Q24 EAPD#AR28 *0/J_4 2 U20
2N7002E AMP_PD# 1 4
EAPD# AR27 0/J_4 EAPD AR29 *0/J_4 AC32 SHDN VO
2
1000P/50V/X7R 2 GND
3
Ra
3
VOLMUTE# AD3 *BAS316 Q27 AC14 3 5 PR195

(32) VOLMUTE# VIN SET
3
2N7002E R208 R503 *1K_4 1000P/50V/X7R

3 1
AR14 *0/J_4 2 2 Q28 C485 C484 G913-C 28K/F/4

*4.7K_4 AC29 0.1u/10V_4 10U/6.3V_8 ADJ C483
Q25
*MMBT3904
1000P/50V/X7R
Ua 10U/6.3V_8
Ca Cb
1
2N7002E
ACZ_RST#_R 2 AC30 PR196
Cc
1
1 1
C667 GNDAUD 1000P/50V/X7R
*10U/6.3V_6 Rb 10K/F/4
ALG_HEADPHONE_L AC31
1000P/50V/X7R Vo=1.25*(1+Ra/Rb)
1
R504 *1K_4 GNDAUD GNDAUD

2 Q30
*MMBT3904 GNDAUD
1

GNDAUD
PROJECT : FH2A
1A
CODEC (ALC269)
A B C D E
5 4 3 2 1
EC(KBC)
+3VPCU
Layout Note:
Place all capacitors close to IT8502.
C414
1000p/16V_4
C415
0.1u/10V_4
AVCC_EC L32
C451
HCB1608KF-121T20 +3VPCU
+3VPCU 32
C449 C431 C413 C399 C400 C450 0.1u/10V_4
0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 +3VPCU
SIO_SLP_S5# (8)
SUSD#
DGPU_VRON (38,40,41)
MBCLK_ME R485 4.7K_4
MY16 (30)
MBDATA_ME R484 4.7K_4
D MY17 (30) D
Layout Note: HWPG MBCLK R261 6.8K_4
HWPG (4,34,38)
net "3VPCU" and "RTC_VCC" VOLMUTE# MBDATA R262 6.8K_4
VOLMUTE# (31)
SUSC# NBSWON# R480 10K_4
minimum trace width 12mils. SIO_SLP_S4# (8,33)
MPWROK (8,23)
+VCC_RTC ACIN R244 *10K/F_4
ICH_RSMRST# (8)
BAT/AC# R226 *10K/F_4
VRON (36)
+3V_RUN +3VPCU R259 *0_4 LID# R242 10K_4
PCI_PLTRST# (10)
MAINON (35,41)
CLK_PCI_8502
SUSON (39,41)
R483 C427
MAINON2 (35,37,39,41)
C654 *22_4 R249 *0_4 DNBSWON#
PLTRST_EC# (10)
*10p/50V_4 0.1u/10V_4 MPWROK
SIO_SLP_S3#
C420 C452 C468
114
121
127
107
11
26
50
92
74
84
83
82
56
57
33
19
20
99
98
97
96
95
94
93
3
U14 IT8502 *39p/50V_4 *39p/50V_4 *39p/50V_4
10 110 MBCLK
VCC
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY
VBAT
AVCC
VSTBY
GPE3/ISCLK
GPE2/ISAS
GPE1/ISAD
KSO16/GPC3
KSO17/GPC5
GINT/GPD5
L80HLAT/GPE0
L80LLAT/GPE7
GPG1/ID7
GPH6/ID6
GPH5/ID5
GPH4/ID4
GPH3/ID3
GPH2/ID2/BADDR1
GPH1/ID1/BADDR0
GPH0/ID0/SHBM
(9,29) LAD0 LAD0 SMCLK0/GPB3 MBCLK (20,42)
9 111 MBDATA MBDATA (20,42)
(9,29) LAD1 LAD1 SMDAT0/GPB4
8 115 D9 DNBSWON#
(9,29) LAD2 LAD2 SMCLK1/GPC1 DNBSWON# (8)
7 116 1N4148WS T69
(9,29) LAD3 LAD3 SMDAT1/GPC2
SM BUS
LID# 22 117 MBCLK_ME MBCLK_ME (10)
(23) LID# LPCRST#/WUI4/GPD2 SMCLK2/GPF6
CLK_PCI_8502 13 118 MBDATA_ME MBDATA_ME (10)
(10) CLK_PCI_8502 LPCCLK SMDAT2/GPF7
(9,29) LFRAME# 6 LFRAME#
PS2CLK0/GPF0 85 RF_EN# (29)
(41) DGPU_VRON3 17 LPCPD#/WUI6/GPE6 PS2DAT0/GPF1 86 BAT_LED0# (30)
87 BAT_LED1#
PS2CLK1/GPF2 BAT_LED1# (30)
D11 1N4148WS 126 GPIO 88
(11) SIO_A20GATE GA20/GPB5 PS2DAT1/GPF3 PWRLED0# (30,33)
(9) IRQ_SERIRQ 5 SERIRQ PS2CLK2/GPF4 89 TPCLK (30)
PS/2
D23 1N4148WS 15 90 TPDATA (30)
(11) SIO_EXT_SMI# ECSMI#/GPD4 PS2DAT2/GPF5
D24 1N4148WS 23 LPC
(11) SIO_EXT_SCI# ECSCI#/GPD3
PCURST# 14
D28 1N4148WS WRST#
(11) SIO_RCIN# 4 KBRST#/GPB6
(30) LED_WLAN# 16 PWUREQ#/GPC7
PWM0/GPA0 24 T63
25 T102
C
(41)
(28)
S5_ON
BT_ON
BT_ON
119
123
GPC0/CRX
GPB2/CTX CIR
IT8502 PWM1/GPA1
PWM2/GPA2
PWM3/GPA3
PWM4/GPA4
28
29
30 AC_PRESENT_R
CAPSLED# (30)
NUMLED# (30)
AC_PRESENT (8)
C
31 D8 1N4148WS
PWM5/GPA5 DDR3_CORL_EC (4)
32 UI1
PWM6/GPA6
Note 1 : Since all GPIO belong to VSTBY power domain, and PWM PWM7/GPA7 34 CONTRAST (23)
+3VPCU there are some special considerations below:
47 FANSIG (33)
(1) If it is output to external VCC derived power domain TACH0/GPD6
48 BAT/AC#
circuit, this signal should be isolated by a diode such as TACH1/GPD7 BAT/AC# (17,42)
R247 KBRST# and GA20. 120 SWI#_R SWI#
TMR0/WUI2/GPC4 SWI# (11)
470K_6 124 D10 1N4148WS
(2) If it is input from external VCC derived power domain TMR1/WUI3/GPC6 DLID# (23)
circuit, this external circuit must consider not to float the item60
PCURST# GPIO input.
C422 PWRSW/GPE4
RI1#/WUI0/GPD0
125
18
NBSWON#
SIO_SLP_S3#
ACIN
SUSB#
NBSWON# (33) BIOS Write Protect
WAKE UP RI2#/WUI1/GPD1 21
0.1u/10V_4 Note 2 : +3VPCU
(1) Each input pin should be driven or pulled. 35 PCUHOLD#
WUI5/GPE5
112 DGPU_VRON2 (40)
(2) Each output-drain output pin should be pulled. RING#/PWRFAIL#/LPCRST#/GPB7
109 R495 R492

TXD/GPB1 LAN_PCIE_PWR_CTRL# (26)
UART RXD/GPB0 108 T104 10K/J_4 10K/J_4
U35
66 8512_SCE# 1 8
ADC0/GPI0 TEMP_MBAT (42) CE# VDD
R263 10K/F_4 106 67 T62 8512_SCK R493 47/F_4 8512_SCK_R 6
8512_SCK FLRST#/WUI7/GPG0/TM ADC1/GPI1 8512_SI R491 47/F_4 8512_SI_R SCK C668
105 FLCLK/SCK ADC2/GPI2 68 TEMP_ALERT# (11) 5 SI
T68 104 69 8512_SO R494 15/J_4 8512_SO_R 2 7
FLAD3/GPG6 ADC3/GPI3 ICM (42) SO HOLD#
8512_SO 103 FLASH 70 0.1u/10V_4
FLAD2/SO ADC4/GPI4 SUS_PWR_ACK (8)
8512_SI 102 71 MODEL_ID0 3 4
8512_SCE# FLAD1/SI ADC5/GPI5 MODEL_ID1 WP# VSS
101 FLAD0/SCE# ADC6/GPI6 72
R260 *100K/F_4 100 A/D D/A 73 KBC_HL1 W25X16AVSSIG
FLFRAME#/GPG2 ADC7/GPI7
36 +3VPCU
B
(30)
(30)
MY0
MY1 37
KSO0/PD0
KSO1/PD1 D25 1N4148WS
MEFW_OVERRIDE (9) 2MB B
(30) MY2 38 KSO2/PD2
(30) MY3 39 KSO3/PD3 DAC0/GPJ0 76
40 KBMX 77 R488 0/J_4 R481
(30) MY4 KSO4/PD4 DAC1/GPJ1 CPUFAN# (33)
41 78 R489 *0/J_4 *8.2K
(30) MY5 KSO5/PD5 DAC2/GPJ2
(30) MY6 42 KSO6/PD6 DAC3/GPJ3 79 T67
(30) MY7 43 KSO7/PD7 DAC4/GPJ4 80 T66
(30) MY8 44 KSO8/ACK# DAC5/GPJ5 81 T65
(30) MY9 45 KSO9/BUSY
R489--> IT8518
3
(30) MY10 46 KSO10/PE
3
51 2 PMUX2 R488--> IT8502 Q21 Q23
(30) MY11 KSO11/ERR#
KSI3/SLIN#
CK32KE
KSI1/AFD#
KSI0/STB#
KSI2/INIT#
52 CLOCK 128 PMUX1

(30) MY12 KSO12/SLCT CK32K
VCORE
(30) MY13 53 KSO13 (11) BIOS_WP# 2 2

AVSS
54 PMUX2
KSI4
KSI5
KSI6
KSI7
(30) MY14
VSS
VSS
VSS
VSS
VSS
VSS
KSO14
(30) MY15 55 KSO15
4 1 PMUX1 *2N7002E
1
3 2 *DTC144EU
58
59
60
61
62
63
64
65
1
12
27
49
91
113
122
75
1
(30) MX0 Y3
(30) MX1 C429 32.768KHZ/10PPM C436
(30) MX2 C436 change to 0ohm--> IT8518
(30) MX3 10p/50V_6 10p/50V_6
(30) MX4
(30) MX5
(30) MX6 Layout Note:
(30) MX7 C426 32.768kHz clock lines:
0.1u/10V_4
a. If possible, please avoid using any through-hole.
b. Please make the trace length short, and the trace width wide enough. Near ROOM DOOR
c. The spacing to the closest neighbor should be wide enough.
UI1 +3VPCU
PCB REV MODEL_ID0 MODEL_ID1 *1K R472 *100K R473
2
A 0 0 *0.1U/10V_4 *0.1U/10V_4
B
+3VPCU +3VPCU C644 C649
B 0 1
1
+3VPCU
A C A
D
1
R229 R227 R482

10K/F_4 *10K/F_4 *100K
NBSWON# 2 Q20
DTA124EUA
MODEL_ID0 KBC_HL1
MODEL_ID1
3
(42) ACIN ACIN D26 PCUHOLD#

2
*0.1U/10V_4
R234 R230
SIO_SLP_S3#
1SS355 C651 Quanta Computer Inc.
*10K/F_4 10K/F_4 (8,33) SIO_SLP_S3# D27 R475
1
1SS355
100K/J_4 PROJECT : FH2A
1A
EC_ITE8502
5 4 3 2 1
1 2 3 4 5 6 7 8
NEW CARD
U15 W83L351YG
SW BOARD CON
33
(8,32) SIO_SLP_S3# 1 STBY# SHDN# 20 SIO_SLP_S4# (8,32)
+3V_RUN 2 19 R250 2K +3V_S5 CON2 C152 0.1U

3.3VIN OC# 88501-0401 1 2
A TPS2231_CLKEN A
PWR_3.3VPEC 3 3.3VOUT RCLKEN 18
1 +5VSUS
C447 4 17 +3V_S5 PWRLED0# PWRLED0# (30,32)
3.3VIN AUXIN 2 NBSWON#
3 NBSWON# (32)
0.1U/10V 5 16
3.3VOUT NC 4 C132 0.1U
6 15 PWR_3.3VPECAUX DFFC04FR018 1 2
(4,10,16,25,26,29) PLTRST# SYSRST# AUXOUT 88502-040n-4p-l-smt
7 GND 1.5VIN 14
EXC_RST# 8 13
PERST# 1.5VOUT
CPUSB# 9 12 +1.5V_RUN
CPUSB# 1.5VIN
CPPE# 10 11 PWR_1.5VPEC
TML
CPPE# 1.5VOUT
qfn20-4x4-5-21p C433
CPU FAN CTRL
21
AL083351000 C421
0.1U/10V
0.1U/10V
B B
PWR_3.3VPECAUX
+5V_RUN
CN2 130805-1 FANPWR = 1.6*VSET
GND_1 1
2
USB- 2 USBP10- (10)
Q8 U8
VSET >= 1V, Enable FAN_CONN.
USB+ 3 USBP10+ (10)
4 CPUSB#_CN DTC144EUEUA-7-F 2 3 +5V_FAN
CPUSB# VIN VO 1
RSV_0 5 GND 5 2
RSV_1 6 1 3 1 FON# GND 6 3
1
7 SMB_CLK_EXC RC0402 R243 4.7K 7 C236 C235
SMBCLK SMB_DATA_EXC GND
8 PWR_3.3VPECAUX 4 8 CN4
SMBDATA RC0402 R246 4.7K (32) CPUFAN# VSET GND 10u/10V_8 0.1U/25V/X7R 53398-0310-3P-L
9
2
+1.5V PWR_1.5VPEC G995P1U DFWF03MS091
+1.5V 10
11 PWAKE# RC0402 R245 *10 AL000995004
WAKE# PCIE_WAKE# (8,26)
12 PWR_3.3VPECAUX
+3.3VAUX EXC_RST#
PERST# 13
14 PWR_3.3VPEC +3VPCU
+3.3V_1 PWR_3.3VPEC +3V_RUN
+3.3V_2 15
16 EXC_CLKREQ#
CLKREQ# CPPE#_CN
CPPE# 17
18 CLK_PCIE_MINI1N (10) R343
REFCLK- 100K/J_4
C
REFCLK+ 19 CLK_PCIE_MINI1P (10) C
20 R254
GND_2 R267
PERn0 21 PCIE_RXN5 (10)
22 PCIE_RXP5 (10) C453
PERp0
GND_3 23
24 PCIE_TXN5 (10) 100K 0.1U/10V
PETn0 100K R344
25 PCIE_TXP5 (10) (32) FANSIG
NC4
NC3
NC2
NC1
PETp0
5
26 U17 *0_4_SHORT
GND_4 EXC_CLKREQ# 1
PWR_1.5VPEC 4 NEWCARD1CLK_REQ# (10)
30
29
28
27
2
ncard-13180151-n-26p-l EXC_PLLEN#0
DFHD26MR014 NL17SZ32DFT2G
3
1
C425 C424 C423

10U/6.3V *10U/6.3V 0.1U/10V
2
Q9 CPPE#_CN 100_4/J CPPE#

PWR_3.3VPECAUX PWR_3.3VPEC R248
TPS2231_CLKEN 2
C428
1
C434 C432 C444 C442 C443 C440 C448 2N7002E-T1-E3 0.033U

*10U/6.3V 0.1U/10V *4.7U/10V *10U/6.3V 10U/6.3V 0.1U/10V R258 BAM70020001
1
D 1M_4 0.01U/16V CPUSB#_CN 100_4/J CPUSB# D

2
R251
C435
0.033U
PROJECT : FH2A
1A
FAN/SW/NEWCARD
1 2 3 4 5 6 7 8
5 4 3 2 1
DC/DC +3V_ALW/+5V_ALW/+5V_ALW2 /+15V_ALW

Place these CAPs
close to FETs
+VIN
Place these CAPs
close to FETs
34
PD8
PR54 PR160
1 2
8206ON_LDO
1K/F_4 150K/F_4 + PC175 + PC179
2
D D
PC176 PC173 PC88 PC168 PC169 UDZ5V6B-7-F *15U/25V_R6 *15U/25V PC166 PC87 PC174 PC85
2200P/50V_4
2200P/50V_4
4.7U/25V_8
4.7U/25V_8
0.1U/25V_4
0.1U/25V_4
4.7U/25V_8
4.7U/25V_8
+5V_VCC1
*4.7U/25V_8
1
2
PC73 +3VPCU +/- 5%
1
0.1U/25V_4
Countinue current:5.2A
1
PC71
1U/6.3V_4
Peak current:6A
2
+5VPCU +/- 5%
OCP minimum 7.5A
Countinue current:8A +5VALW
+2VREF +3VPCU
Peak current :9A
1
PC70
5
.1U/10V_4
OCP minimum :10.5A PC72 PQ19
2
PC160 AON7410
D-04
8
7
6
5
4.7U/6.3V_6 +5V_VCC1
+5VPCU 0.1U/10V_4 4
8
7
6
5
4
3
2
1
1
4
PR57 PL8
D-04
LDOREFIN
IN
N.C1
VCC
TON
LDO
ONLDO
REF
3
2
1
B-02
0_4 2.2UH/8A
PQ50
AO4496 PR58
2
B-01 9 32 150K/F_4
BYP REFIN2
5
PL9 1 10 31
2
3
OUT1 ILIM2
2
2.2UH/12A PR59 5V_FB1 11 30 3V_FB2 PR60
FB1 OUT2
330u/6.3V_6X5.7
1 2 12 PU3 29 *2.2_8
C 309K/F_4 PGOOD1 ILIM1 RT8206B SKIP PGOOD1 PR164 PC172 C
13 28
1
PGOOD1 PGOOD2
2
8
7
6
5
14 27 4 *0_4/S +
ON1 ON2
2
5V_DH 15 26 3V_DH
1
DH1 DH2
0.1U/10V_4
PR170 5V_LX 16 25 3V_LX PC81 PC171
LX1 LX2
10uF/25V_1206 PC207
PC186
*1500P/50V_4
PC187 PR161 *2.2_8 4 37
3
2
1
PC183 + *0_4 PAD1
36
PAD10
1
PAD2
AGND
PGND
PAD5
PAD6
PAD7
PAD8
PAD9
0.1U/10V_4
BST1
BST2
39
N.C2
VDD
1
PAD3
1
2
DL1
DL2
330u/6.3V_6X5.7
40 PAD4
2
10uF/25V_1206
PC177 PQ49 PC82 PQ48 PR165

2
*1500P/50V_4
0.1U/25V_4
AO4712 PC83 AON7702 *0_4
2
38
35
34
33
17
18
19
20
21
22
23
24
42
41
0.1U/25V_4
PR162
1
2
3
1
*0_4/S
1
PR61 PR62
1
1 2 5V_BST1 3V_BST2 1 2
2_6 2_6
5V_DL 3V_DL
1 +5VALW
PC79
PD10 3 2 1
BAV99
1
+10VALW 2 0.01U/25V_4
+3VPCU PC86
1U/6.3V_4
2
2
1
PR42 PC74 PC78
0.1U/25V_4
100K/F_4 PD17 PD9 3 1 2

1
+5VALW 1SS355 BAV99

B 1 2 2 0.01U/25V_4 B
PR41
PGOOD1 51427PG
PR163
1 2 +15VALW
*0_4/S 100K/F_4
1
PC162 PC75
2.2U/6.3V_6 1U/25V_6
2
PR166 *0R_4/S EN0

(4) SYS_SHDN#
EMI
+VIN
F1
+3VPCU
2
C633
2
2
C150 C648 C67 C524 C506 C369
PU1 *0.1U/25V_6
1
5
*0.1U/25V_6 *0.1U/25V_6 *0.1U/25V_6 1U/25V_6 *0.1U/25V_6 *0.1U/25V_6

1
1
(39) 51427PG 2
4 HWPG
HWPG (4,32,38)
(35,37) HWPG_1.05V 1
A A
3
MC74VHC1G08DFT2G

PROJECT : FH2A
1A
+5V/+3V (RT8206B)
5 4 3 2 1
5 4 3 2 1
35
D D
+VIN
+5V_S5 +1.05V _PCH+/- 5%
PD7
PR27
2 1 RTBST Countinue current:6.541A
RTVDD
10_6
PC157 Peak current:7.5A
RB501V-40
1U/6.3V_4
PC53 PC61 PC62 PC60
OCP minimum 9A
1U/6.3V_4
B
2200P/50V_4
.1U/25V_4
4.7U/25V_8
5
6
7
8
+3V_S5 +1.05V_PCH
RTBST_1 PR152 PC57
.1U/25V_4
PR144 10_6
(34,37) HWPG_1.05V PR145 4
13
1M_4
9
PR143 *0_4/S PU10
100K/F_4 12 RTDH PQ47 D-05
VDD
VDDP
BST
RTTON DH AO4496
16 TON
C C
HWPG_S2A 4 11 RTLX PL6
3
2
1
PGOOD LX 1.5UH/SIL-1040-10A
RT8204C PR154
PR146 *0_4/S HWPG_S2B 5 10 RTILIM
LPGOOD ILIM
6.8K/F_4
1
MAINON2 PR147 10_4 RTEN 15 8 RTDL
(32,37,39,41) MAINON2 EN/DEM DL
5
6
7
8
VOUT
+ + PC66
LDRI
LEN
2
LFB
17 3 PC65 PC63 PC159 PC64
PAD FB
10U/6.3V_8
10U/6.3V_8
.1U/10V_4
PR148
RTFB
2
*1M/F_4 4 PR155
14
1
2.2_8
PQ13
1
AO4712 330U_2.5V_7343 *390u/2.5V_R6_10
PR142 PR26
PC158
4700P/50V_4
PR151 4.02K/F_4 10K/F_4
3
2
1
MAINON RTLEN
(32,41) MAINON PC154
10_4
PR149 *100P/50V_4
*1M/F_4
+3V_S5
Vo=0.75(R1+R2)/R2
RTLDRI
+1.8V_RUN Volt +/- 5%
5
Countinue current:1A
6
7
8
PC59 PC58
.1U/10V_4
*10U/6.3V_8
B Peak current:2A B
PR28 4 OCP minimum 3A

100/F_4
PC155
33P/50V_4
PQ8
AO4496
+1.8V_RUN
3
2
1
PC56
.033U/10V_4
PC156 PR150
14K/F_4
*39P/50V_4 PC153 PC152 PC52
10U/6.3V_8
.1U/10V_4
*10U/6.3V_8
RTLFB
Vo=0.75(R1+R2)/R2 PR153
10K/F_4
A A

PROJECT : FH2A
1A
+1.05V/+1.8V (RT8204C)
5 4 3 2 1
5 4 3 2 1
+VIN
OSRSEL = GND 110mV
OSRSEL = REF
OSRSEL = 3.3V
145\mV
190\mV
+3V_S5 +3V_S5
F1
+VIN
36
1
OSRSEL = 5V OFF C721 C720
1
1U/25V_6
PC143 PC34 PC35 + PC140 + PC144 PC31 PC33
1U/25V_6
2200P/50V_4
4.7U/25V_8
4.7U/25V_8
0.1U/25V_4
*4.7U/25V_8
100U/25V L-F
100U/25V L-F
2
2
PR10 PR100
D 1.91K/F_4 1.91K/F_4 D
PQ40
5
(4,8) IMVP_PWRGD RJK03B9
D
(3) VR_PWRGD_CLKEN# 4
G Countinue current:48A
+3V_S5 S
+VCC_CORE
(32) VRON
1
2
3
PL4
51621_5VFILT
0.36UH PCMC104T-R36MN 30A
PC15 1 2
2.2U/6.3V_6 AGND_51621
2
AGND_51621 1 2 51621_5VFILT 3 4
PQ41 PQ6 PR21
5
249K_0402_1%
RJK03D3 RJK03D3 *2.2_8
51621_REF D D
1
16.2K/F_4
G G
PR131
PR97
PR96 5.9K/F_4 4 4 + +
S S PC148 PC44 PC42
0_4
PR101
*0_4
PR9
PC30
1
2
3
1
2
3
2
330U_2.5V_7343
330U_2.5V_7343
0.1U/10V_4
PC120 33P/50V_4
51621_ISLEW 2
*1500P/50V_4
*0_4/S
*0_4/S
2 1 51621_DROOP
+5V_S5 PR130
AGND_51621 1 2 511K/F_4
PC118
+5V_S5
PR98
PR99
0.22U/6.3V_6
PR132
F1 PR133
RB501V-40
28K/F_4 100K_6 NTC
41
40
39
38
37
36
35
34
33
32
31
PD13
1
C722 C723 C724 C725 C726 1 2
PAD
VREF
DROOP
V5FILT
ISLEW
TONSEL
VR_ON
CLK_EN#
PGOOD
OSRSEL
TRIPSEL
PC124
0.1U/25V_4
0.1U/25V_4
0.1U/25V_4
1U/25V_6 1U/25V_6 0.033U/16V_4
470F_4
470F_4
1 30 PC126
MODE DRVH2
PR104
PR105
AGND_51621 PR102 0.22U/25V_6
C C
2 GND VBST2 29 1 2
2_6
3 CSP2 LL2 28
AGND_51621 PC16 33P/50V_4 2 1 51621_CSP2
4 27 +VIN PC125
PC18 33P/50V_4 51621_CSN2 CSN2 DRVL2 51621_CSN2
AGND_51621 2 1 1 2
5 CSN1 V5IN 26 +5V_S5
AGND_51621 PC20 33P/50V_4 2 1 51621_CSN1 1 2 100p/25V_4
1
6 PU5 25
PC21 33P/50V_4 51621_CSP1 CSP1 TPS51621RHAR_QFN40_6X6 PGND PC19 4.7U/6.3V_6 PC32 PC28 PC27 PC26 PC29 51621_CSP2
AGND_51621 2 1
7 24
2
GNDSNS DRVL1
2200P/50V_4
4.7U/25V_8
4.7U/25V_8
0.1U/25V_4
*4.7U/25V_8
100_4 PR254 *0_4/S
AGND_51621 PR13 8 23 PC130
PR113 *0_4/S VSNS LL1 0.22U/25V_6
(6) VSSSENSE PR114
51621_THEM 9 22 1 2
THERM VBST1
2_6
DPRSLPVR
(6) VCCSENSE 10 21
PR116 VR_VTT# DRVH1 PQ43
5
IMON
10K_6 NTC RJK03B9

VID6
VID5
VID4
VID3
VID2
VID1
VID0
PSI#
+VCC_CORE D
RB501V-40
G
PR15 100_4 4
11
12
13
14
15
16
17
18
19
20
PD15
1
2
3
11K_4
PR117
PL5 +VCC_CORE
PROC_DPRSLPVR
0.36UH PCMC104T-R36MN 30A

1 2
+5V_S5 PQ44 PQ42 3 4
2
*0_4/S
AGND_51621 RJK03D3 RJK03D3

D D PR22
1
G G *2.2_8
(6) I_MON
16.2K/F_4
0.22U/6.3V_6
4 4 + +
S S
PR120
PR138
(4) H_PROCHOT#_D R331 *0_4/S PC149 PC43 PC41
1
2
11.8K_4
PC136
PR18
*0_4/S
B B
1
2
3
1
2
3
2
330U_2.5V_7343
330U_2.5V_7343
0.1U/10V_4
PC38
(6)
(6)
(6)
(6)
(6)
(6)
(6)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
1
*1500P/50V_4
PR118
PR119
PR141
68/F_4
511K/F_4
PR140
PR11 *0_4/S
(6)
(6)H_PSI#
+1.05V_VTT PR139
28K/F_4 100K_6 NTC
1 2
VSSSENSE
PC127
(6)
DPRSLPVR
0.033U/16V_4
AGND_51621
470F_4
470F_4
PR109
PR106
PC128
1 2 51621_CSN1
100p/25V_4
51621_CSP1
VID
VID5=1
A A
VID4=0
VID3=0

PROJECT : FH2A
1A
CPU Core (TPS51621)
5 4 3 2 1
5 4 3 2 1
PQ18 *DTC144EUA 37
3
PR43
*1K/F_4
2 H_VTTVID1 (6)
D D
PR44
1
PR45 *100K/F_4
PR47
*820K/F_4 *100K/F_4
PR156
*0_4
VTT_SENSE- VSS_SENSE_VTT (6)
OE_1.1 PR46 *0_4/S

MAINON2 (32,35,39,41)
PR48
PR49
PR50
PC67
1
2
PC68
+1.05V_VTT +/- 5%
.01U/16V_4
2
1
44.2K/F_4
6.49K/F_4
38.3K/F_4
2200P/50V_4
Countinue current:18.2A
VDES_1.1 2
R_SEL_1.1
C Peak current:20A C
BIAS_1.1
OCP minimum 22A
+1.05V_VTT
A1
A2
A3
A5
PR52 PU2
*0_4/S
BIAS
R_SEL
VDES
OE
PR51 D-06
1 2 IRIPL_1.1 B2
40.2K/F_4 IRIPL
B4 D1 PL7
TEMP VX1 0.22uH_MPL73-0R22
VX2 D2
PR55 *0_4/S STAT_1.1 B5 D3 LX_1.1 1 2
(34,35) HWPG_1.05V STAT VX3
VX4 D4
+5VPCU E5 D5 PR159 *0_4/S +1.05V_VTT
VDD4 VX5
C5 VDD3
C4 A4 PR158 *0_4 VTT_SENSE (6)
VDD2 VSENSE+
E4 VDD1
AGND
GND1
GND2
GND3
GND4
GND5
GND6
AVDD
PC76 PC90 PC170 PC77 PC89 PC84 PC80
6800P/25V_4
22U/6.3V/X5R_8
22U/6.3V/X5R_8
22U/6.3V/X5R_8
22U/6.3V/X5R_8
.1U/10V_4
*22U/6.3V/X5R_8
PC163 PC167 PC161 PC165 PC164 VTT_SENSE-
B VT357 B
B3
B1
C1
C2
C3
E1
E2
E3
PR157 *0_4/S
22U/6.3V/X5R_8
22U/6.3V/X5R_8
1U/6.3V_4
.1U/10V_4
.1U/10V_4
PR53
10/J_6
AVDD_1.1
PC69
.22U/6.3V_4
A A

PROJECT : FH2A
1A
+1.05V_VTT (VT358)
5 4 3 2 1
5 4 3 2 1
D D
+5VPCU
PR237
+VIN
22R_6
1
+VIN PC220 PC227 PC226 PC217
1U/6.3V_4 1U/6.3V_4 PD23 PC233 PC231 10uF/25V_1206 10uF/25V_1206
2200P/50V_4 0.1U/25V_4
2
RB500V
PR224 PQ67
17
16
5
1SS355/UMD2 PD26 8116GND1 RJK03B9
(4,32,34) HWPG
100K_4 8 8116BST1 D
GNDA
VDDA
VDDP
BST
G
8116HDR1 PR245 2.2R/F_6
PC215 0.01U/50V_6 8116VIN1 2 HDR 9 4
S DCR(max)=1.2 m ohm V: 1.0V
8116GND1 VIN
2
C
I: 17A +VGPU_CORE C
1
2
3
PC223 PL12
PR206 0R_4 8116PG1 4 PU15 0.22U/25V_6 0.36UH PCMC104T-R36MN 30A
(40) GPU_PWROK 18.5A 750mil OCP: 20.35A
1
PGD
LX 10 8116LX1 1 2
PR249 100K/F_4
+3VPCU OZ8116LN 3 4
1
8116GND1 PC222 *1000P/50V_4 8116EN1 3 7 8116LDR1 PQ66 PR123
ON/SKIP LDR
5
RJK03D3 + + +
13 D PD24 PC232 PC235 PC228 PC237
VSET
GNDP
330u_2V_7343ESR6
330u_2V_7343ESR6
*330u_2V_7343ESR6
0.1U/10V_4
8116REF1 14 11 8116CSP1 G 2.2R_6
OCT
2
VREF CSP 8116CSN1 *SSM24PT
15 TSET CSN 12 4
S
PR205 PR248
1
1
2
3
PR35 PC229 PC234 PC218
R1
2200P/50V_4
115K/F_4 0R_4 22P/50V/NPO_4
1000P/50V_4 F-04
8118VSET1 PC224 short 50
E-03
0.1U/25V_4
PC216 PR242 PR243 PC219 8116GND1
1000P/50V_4 68K/F_4
R2 *130K/F_4 1000P/50V_4 8116GND1 PR253
PR244 0R_4 Connect to output CAP.
*806K/F_4
PR252 *0R_4
8116GND1 8116GND1 8116GND1 8116GND1 8116GND1 PR251 100K/F_4 PR250 *200K/F_4 +VGPU_CORE
R3 PR241 Close to GPU side as possible.

PQ68 *1SS355/UMD2 PD25 51.1R/F_4
3
*2N7002K PC221 2200P/50V_4

1 2
2 PR227 *0R_4
GFX_CORE_CNTRL0 (17)
PC236
B
*1000P/50V_4 B
1
PR246
8116GND1 8116GND1 5.1K/F_4
8116GND1
E-02 PWRCNTL0 V-CORE
PD22 *1SS355/UMD2
L 0 1.0V M96 Vout=2.75*(R2/(R1+R2))
DGPU_VRON PR226 0R_4 8116EN1
(32,40,41) DGPU_VRON
PC225 *0.22U/10V_4
8116GND1 H 1 0.95V Madison
A A
Title
FH2A
C +VGPU_CORE (OZ8116) 1A

5 4 3 2 1
1 2 3 4 5
39
A A
+VIN
+5V_S5 +1.5V_SUS +/- 5%

+1.5V_SUS_1
Countinue current:12A
25
Peak current:13A
2
( VTT/1A ) PU11
1 24 PD19 PC194 PC197 PC200 PC195
OCP minimum 15A
GND
+0.75V_DDR_VTT VTTGND VTT
2200P/50V_4
0.1U/25V_4
4.7U/25V_8
4.7U/25V_8
PC198 *RB501V-40 PQ58
5
*10U/6.3V_8 RJK03B9
2 23 D +1.5V_SUS
1
VTTSNS VLDOIN
G
1
PC191 4
PC199 PC202 1116VBST PR182 S
3 22 1 2
+1.5V_SUS_1 GND VBST D-07
10U/6.3V_8
10U/6.3V_8
2_6
2
1
2
3
PR186 0.1U/25V_4
2 1 4 21 1116DRVH
MODE DRVH PL10
*0_4/S
CV-10L0MZ01/DC-10F0M102
+DDR_VTTREF 5 20 1116LL +1.5V_SUS_1
VTTREF LL
1
1
B ( 20mA ) B
1
PC201 6 19 1116DRVL PQ57 PR181 + PC188 + PC185 PC184
COMP DRVL
1
0.1U/10V_4
390u/2.5V_R6_10
*330U_2.5V_7343
0.1U/10V_4
*2.2_8 PR184 PC196
2
1
PC208
PC209
RJK03D3 D 18.7K/F_4
B
*100P/50V_4
7 18 G
1
NC PGND
4
2
1
1
S
2
10uF/25V_1206
10uF/25V_1206
8 17 PC192
1
2
3
VDDQSNS CS_GND
*1500P/50V_4
2
V5FILT PR185 1116VDDQSET 1116CS PR178
9 VDDQSET CS 16
*0_4 +5V_S5
7.5k/F_4
1
PC189
10 15 2 1 PR183
S3 V5IN 18K/F_4
1U/6.3V_4
PR177
B-06
(32,41) SUSON 11 14 V5FILT
2
S5 V5FILT
10_6
1
1116TONSET
12 NC 13 PC190
PGOOD 51427PG (34)
1U/6.3V_4
2
B-07
PD18 RT8207GQW
1 2 B
*1SS355 PR179
619K/F_4
MAINON2 PR180
0_4
+VIN
C C
1
PC193
*0.1U/10V_4
2
MAINON2
(32,35,37,41) MAINON2
D D

PROJECT : FH2A
1A
DDR3 (RT8207)
1 2 3 4 5
5 4 3 2 1
1 Volt +/- 5%
Countinue current:2A +VIN +1V_GPU
Peak current:3A
PR34
22/J_8
3
PR202 PQ12
+1.5V_SUS +1V_GPU MAX : 2A 1M_4 DMN601K-7
D 2 D
3 VIN NC 5 D-08
3
PC36 PC146
1
10U/6.3V_8
0.1U/10V_4
C-03 F1-01 (32,38,41) DGPU_VRON 2 PR201
PU8 1M_4
APL5920
C-04 VOUT 6
PQ65
1
PR127 3.01K/F_4 2 DTC144EUA
(32,38,41) DGPU_VRON EN
1
C727 C728 C729 +1V_GPU 1V 1.1V
+5VPCU 4 8 PC25 PC24 PC139
VDD GND
10U/6.3V_8
10U/6.3V_8
0.1U/10V_4
0.1U/25V_4
0.1U/25V_4
PC37 PR203 1U/25V_6
2
ADJ
0.22U/10V_4 100K_4 1 9 PR19 30.1K 40.2K
PGOOD GND1
1
PC145
7
1U/6.3V_4
P/N CS33012FB18 CS34322FB16
2
PR19
R1 40.2K/F_4
B-08 +3VPCU +1.8V_GPU MAX : 1.5A
2
PR126 *0_4/S VO=(0.8(R1+R2)/R2)
(38) GPU_PWROK
R2 PR20 R2<120Kohm
1 Volt +/- 5%
100K/F_4
3 5 D-08 Countinue current:1.5A
1
PC151 PC47 VIN NC
C
Peak current:3A C
10U/6.3V_8
0.1U/10V_4
PU9
C-04 APL5920 6 F-01
VOUT
2 EN
1
+5VPCU 4 8 PC40 PC39 PC147 PC210
VDD GND
1U/6.3V_4
10U/6.3V_8
10U/6.3V_8
0.1U/10V_4
1U/6.3V_4
PR204
2
ADJ
+VIN +1.8V_GPU 100K_4 1 9
PGOOD GND1
1
PC150
7
2
C-03 PR23
PR135 PR129 R1 127K/F_4
2
1M_4 22/J_8
PR137 *0_4/S VO=(0.8(R1+R2)/R2)
(38) GPU_PWROK
R2 PR24 R2<120Kohm
3
PD6 *1N4148WS 100K/F_4
1 2
1
3
2
PR136 PR134 PQ45
(32) DGPU_VRON2 2
0/J_4 1M_4 DMN601K-7
B B
1
PC46 PQ46
1
*0.22U/10V_4 DTC144EUA
PQ7
6.76A
FDMS7692
+1.5V_SUS BAM76920000 +1.5V_GPU
SOT669-5P3
+VIN +1.5V_GPU +15VALW 5 2
PC54 PC55 1
10U/6.3V_8
10U/6.3V_8
PC50 PC49 PC48
1
+
4
10U/6.3V_8
10U/6.3V_8
330U/2.5V_3528
PR32 PR29 PR30 PC45
1M_4 22/J_8 560K_4 *0.1U/10V_4
2
DGPU_VROND
3
PQ10 PQ9
DMN601K-7 DMN601K-7 PR25
2 1
2 2
E-02 PD21 *1N4148WS 0_4
1
1 2
PC51
3
A A
*2200P/50V_4
1
PR200 14K/F_4 2 PR31

(32,38,41) DGPU_VRON 1M_4
PC214 PQ11 Quanta Computer Inc.

1
0.22U/10V_4 DTC144EUA
PROJECT : FH2A
1A
GFX_IO_VCC
5 4 3 2 1
5 4 3 2 1
+VIN +5V_RUN +3V_RUN +1.8V_RUN +1.5V_RUN +15VALW +5VPCU

MAIND +3VPCU
PQ20
41
FDMS7692
BAM76920000
SOT669-5P3
3.65A
D D
PR65 PR172 +1.5V_SUS 5 2 +1.5V_RUN
5
6
7
8
560K_4 PC92 442K_4 1
5
6
7
8
.1U/10V_4
PC178
.1U/10V_4
PR70 PR71 PR69 PR68 PR67
1M_4 22_8 22_8 22_8 22_8 MAIND 4
4
MAIND-3VRUN 4
PR63
1
PQ28 PQ27 PQ26 PQ25 PQ24 PQ22 3.392A 3.794A MAIND
1
DMN601K-7 DMN601K-7 DMN601K-7 DMN601K-7 DMN601K-7 PC95 AO4496 PQ55
*2200P/50V_4
+5V_RUN PC180 AO4496 +3V_RUN 0_4
*2200P/50V_4
2 2 2 2 2 PC91
3
2
1
3
2
1
330P/50V_4 +5VPCU
3
PC93
1
.1U/10V_4 PC182
2 PR66 .1U/10V_4
(32,35) MAINON
1
2
5
6
1M_4
PQ21
PQ23 3 ME3424
1
DTC144EUA
+VIN +5V_S5 +3V_S5 +15VALW
4
+5V_S5
+VIN +1.05V_PCH +1.05V_VTT +0.75V_DDR_VTT +3VPCU

1mA
1
PR174
560K_4 PC94
1
2
5
6
.1U/10V_4
C C
2
PR173 PR168 PR169 PR187 442K_4 PQ59
1M_4 22_8 22_8 S5_OND 3 ME3424D
S5_OND
PR36 PR37 PR39 PR38
3
1M_4 22_8 22_8 22_8 PQ52 PQ53 PQ51 +3V_S5
4
DMN601K-7 DMN601K-7 DMN601K-7 PC181 0.539A
1
3
3
PQ15 PQ17 PQ16 2 2 2 PC204
*2200P/50V_4
*2200P/50V_4
DMN601K-7 DMN601K-7 DMN601K-7
1
2 2 2 PC203
.1U/10V_4
1
2
2 PR171
(32) S5_ON
3
1M_4
1
S5_ONG
2 PR40 PQ54
1
(32,35,37,39) MAINON2 1M_4 DTC144EUA
PQ14
1
DTC144EUA
+VIN
+VGPU_CORE
PR197
1M_4 PR87
22_8
B B
3
PQ36 +VIN +3V_GPU +15VALW
DMN601K-7
3
+VIN +1.5V_SUS +5VSUS +15VALW +5VPCU
2 +3VPCU
2 PR198 PR86
(32,38,40) DGPU_VRON 1M_4 PR88 22_8
1M_4 PR85
PR191 PR189 PR188 PQ64 1M_4
1
5
6
7
8
1
2
5
6
1M_4 22_8 1M_4 DTC144EUA
PR190 PR84 PC105
C-03
0.1U/10V_4
22_8 2 1 3
SUSD 4 PD20 *1N4148WS 0_4
3
1 2 PQ35 PQ37
3
PQ63 PQ60 PQ62 DMN601K-7 DMN601K-7 PQ31
4
3
1
DMN601K-7 DMN601K-7 DMN601K-7 PQ56 ME3424D
1
AO4496 2 2 PC101 0.19A

3
*2200P/50V_4
2 2 2 PR199 0/J_4 2 PR90 +3V_GPU
2
PC205 (32) DGPU_VRON3 1M_4
2
3
2
1
2 PR192 2200P/50V_4
(32,39) SUSON 1M_4 PQ34 PC104
1
1
0.1U/10V_4
DTC144EUA
1
PQ61 PC213
1
*2200P/50V_4
DTC144EUA 1.5A
2
SUSON_G +5VSUS
A A
PC206
.1U/10V_4

PROJECT :FH2A
1A
DISCHARGE/3VS5/5VS5/LAN
5 4 3 2 1
1 2 3 4 5
42
PR6 PQ2 PQ3
VA
PD4 0.01_3720
FDS6675BZ +VIN FDS6675BZ
SSM34PT 40V
1 2 VA2 1 8 1 8 BAT-V
2 7 2 7
A D-09 3 6 3 6 A
PC115 PR92 5 5
PC116 PC117 PR94
PL11
0.1u/50V_6 220K/F_6
PD1
4
HI0805R800R-10/5A/80ohm_8 0.1u/50V_6 2200p/50V_6 33K_6
1
SSM34PT 40V
PL1 PD5
HI0805R800R-10/5A/80ohm_8 1 6 PR93
P4SMAJ20A
PA1 PD14 10K_6
VA PR91
2
PJ1 2 5
1N4148WS 220K/F_6
1 3 4
3
2
3
PR7
F1-06 PQ38
2200p/50V_6
*0.1u/50V_6
0.1u/50V_6
0.1u/50V_6
10K_4
0.1u/50V_6
PC10
4
PC11
PC13
PC14
IMD2AT108
PC9
VA2 2
+3VPCU (17,32) BAT/AC#
DFHS04FR741
87501-0400-4P-L PQ39
CSIP_1 2N7002K
1
+VIN
PR125
PR110 PR107
10K/F_6 10/F_6 10/F_6 PC131 1U/6.3V_4
1 2
PC132
ACIN PC122 PC123 PC121
(32) ACIN 0.1u/50V_6
5
6
7
8
PR14 PQ5 2200p/50V_6 *0.1u/50V_6 10u/25V_1206
4.7_6 AO4496
PC23 1U/6.3V_4
B 88731_VDDP 1 2 4 B
+3VPCU CSIP CSIN

PR8
33
32
31
30
28
27
26
21
PC142
1
PD16 0.01_3720
0.1u/50V_6
PL3
NC
GND
GND
GND
GND
CSSP
CSSN
VCC
VDDP
RB500V-40
6.8uH/4.5A_7X7X3
3
2
1
PR108 1 2 BAT-V
2.7_6 PC129
5
6
7
8
(20,32) MBDATA 11 VDDSMB BOOT 25
PQ4
0.1u/50V_8 AO4712 PR103
9 24 88731_DH 4 2.2/F_6 PC113
(20,32) MBCLK SDA UGATE 0.01u/50V_6
10 23 88731_LX PC17
SCL PHASE PC119
*0.001U/_4
2
2200p/50V_6 PC8
13 20 88731_DL 2200p/50V_6
3
2
1
ACOK LGATE PC114 PC12
PC22
1
10u/25V_1206 10u/25V_1206
PR12 0.1u/50V_6
PGND 19
49.9/F_6
DCIN DCIN 22 DCIN
PR16
PR112
10/F_6
82.5K/F_6 18 CSOP CSOP_1
PU6 CSOP CSOP_1
2 ACIN ISL88731A PC134
0.1u/50V_6
3 BAT-V
PC6 PR115 VREF
17 CSON BAT-V
C CSON C
2 1 22K/F_6 PR17
4 ICOMP 10/F_6
PJP1 0.1u/50V_6 16
NC
1 MBAT+ BAT-V 5 PR122
BATT NC
Short_4
2 15 BAT-V
VS VBF
6 VCOMP PR121
SWT+ 3 GND 29
100_4
GND
*0.01u/50V_6
0.01u/50V_6
0.01u/50V_6
ICM
TEMP_MBAT_C
NC
NC
POWER 4 TEMP_MBAT (32)
PC133
PC135
5
PC137
14
12
CLOCK
PR124
DATA 6
2.21K/F_6
SC#T- 7
PC5 PC4 ICM (32)
8 +3VPCU PC138
GND 47p/50V_6 47p/50V_6
0.01u/50V_6
2
PR4 PR3 PR5 PC141

DFAD08MR001 100K/F_6
BAT-1746498-2-8P-L 100_4 100_4 3300p/50V_4
1
MBCLK
MBDATA
PU7
*CM1293A-04SO
1
D 1 6 MBCLK D
CH1 CH4
1
PD3 PD2 PR2

ZD5.6V ZD5.6V PC7
2 VN VP 5 +3VPCU
100K/F_6 0.01u/25V_4
2
TEMP_MBAT_C 3 4 MBDATA
2
CH2 CH3

PROJECT :FH2A
1A
CHARGER (ISL88731)
1 2 3 4 5
5 4 3 2 1
43
CK505 CLK_CPU_BCLKP CPU
CLKOUT_BCLK0_N/CLKOUT_PCIE8N BCLK
D
SLG8SP585VTR CLKOUT_BCLK0_P/CLKOUT_PCIE8P
133MHz BCLK BCLK# D
133MHz BCLK CLK_CPU_BCLKN

PLL1
CLKOUT_DMI_P
CLK_PCIE_3GPLLP PEG_CLK
100MHz DMI
CLKOUT_DMI_N
100MHz DMI PEG_CLK#
PLL2 CLK_PCIE_3GPLLN
100MHz SATA PCH
PLL3
96MHz DOT
PLL4
14.318MHz Ref
CLKOUT_PCIE6P
CLKOUT_PCIE6P
100MHz PCIE
REFCLK_P LAN
CLKOUT_PCIE6N REFCLK_N
CLKOUT_PCIE6N
C C
CLKOUT_PCIE2P
CLK_PCIE_MINI1P MiniWLAN
100MHz PCIE REFCLK+
REFCLK-
CLKOUT_PCIE2N CLK_PCIE_MINI1N
14.318
Xtal DEBUG CARD
CLK_LPC_DEBUG RESERVED
CLKOUT_PCI0 33MHz PCI
ITE EC8502
CLKOUT_PCI2
CLK_PCI_8502 LPCCLK
B
33MHz PCI B
Buffered
Card Reader
mode CLKOUTFLEX3
CLK_48M_CR
33MHz PCI
PE_REFCLKP
CLK_PCI_FB
CLKOUT_PCI3 33MHz PCI
CLKIN_PCIL00PBACK
A A
27MHz Ref
GPU
PROJECT : FH2A
1A
Clock Distribution
5 4 3 2 1
5 4 3 2 1
Power Tree Table PWM +5VPCU +-5%

AC/DC Insert enable
MOS SW
P.41
+5V_S5 +-5%
S5_OND enable
36
AC System
Charger +5V_RUN +-5%
RT8206B MAIND enable
ISL88731A
D MOS SW D
DC P.42 P.41
+3VPCU +-5%
AC/DC Insert enable
+5VSUS +-5%
SUSD enable
P.34 MOS SW
P.41
+3V_S5 +-5%
+1.05V_VTT +-2% S5_OND enable
MOS SW
PWM MAINON2 enable
VIN VT358 P.41
P.30 MAX 18.1A
+3V_GPU +-5%
C
MOS SW DGPU_VRON enable C
+1.05V_PCH +-5% P.41

PWM MAINON2 enable
RT8204C +3V_RUN +-5%
P.35 MAX 6.5A MOS SW MAIND enable
P.41
+1.8V_GPU +-3%
LDO +1.8V_RUN +-5% MOS SW DGPU_VRON enable
+VGPU_CORE MAINON enable
PWM (RT8204C)
RT8152C VGAON enable P.40
P.35
P.38 MAX 19.3A
VCC_CORE
± [VID*1.5%] VCC > 0.7500V
± [11.5mV] 0.5000V < VCC =0.7500V
PWM
ADP3212 VRON enable
B B
P.29 MAX 48A
+0.75V_DDR_VTT
MAINON2 enable
PWM LDO +1V_GPU
DGPU_VRON enable
+DDR_VTTREF P.40 MAX 2A
RT8207GQW SUSON enable
P.32
+1.5VSUS +-3% +1.5VRUN
MOS SW
SUSON enable MAIND enable
MAX 12A P.41 MAX 3A
A +1.5V_GPU A
MOS SW DGPU_VRON enable
P.40 MAX 6.76A

PROJECT :FH2A
1A
Power Tree
5 4 3 2 1
5 4 3 2 1
Slave ADDRESS :09H Slave ADDRESS :16H

45
CHARGER
BATTERY
+3VPCU +3VPCU ISL88731A +3VPCU +3VPCU
D D
+3V_GPU +3V_GPU
+3V_GPU
R R R R R R
Slave ADDRESS :9AH
G
MBCLK D S
NMOS
Thernal Sensor
EC
MBDATA D S
ITE NMOS
ITE8502 MBCLK_ME
(128 Pin LQFP)
16mm x 16 mm
MBCLK_ME
C C
+3V_S5 +3V_S5
+3V_S5 +3V_S5
SMB_CLK_ME0
PCH +3V_S5
+3VPCU +3VPCU
SMB_DATA_ME0
INTEL
R R R R
82801IBM G
SMB_CLK_ME1 S D
(HM55) NMOS
27mm X 25mm
SMB_DATA_ME1 S D
NMOS
B Slave ADDRESS :D2H B
CLOCK GEN
SLG
+3V_S5 +3V_S5 +3V_RUN +3V_RUN
SLG8SP585VTR
Slave ADDRESS :A0H Slave ADDRESS :A4H
(64-pin QFN) DDR3-SODIMM DDR3-SODIMM
+3V_RUN 9 mm x 9 mm CH.A(STD) CH.B(STD)
R R R R
G
PCH_SMBCLK D S CGCLK_SMB
NMOS
PCH_SMBDATA D S CGDAT_SMB
NMOS
A A

PROJECT : FH2A
1A
SM BUS
5 4 3 2 1
5 4 3 2 1
CHANGE HISTORY
A->B
PAGE04:Delete Q4,Q3,R170,R171,R159 for cost down
PAGE16:R12 delete it for M96 LP BOM

PAGE17:R297-300 can select GPU BOM type for VRAM strap
PAGE18:<1>Add L43,L48,R499,R500 for M96 LP BOM
<2>Add L44 for M96 LP BOM
<3>Add R498 for M96 LP BOM
<3>Delete L26,L10,C199,C200,C208,C23,C39 for M96 LP BOM
PAGE19:<1>Delete L45-47,L12,C42,C36,C29 for M96 LP BOM
<2>Delete R496,R497 for M96 LP BOM
D
PAGE20:Delete R74,R300,R84,R64,R48 for M96 LP BOM D
PAGE28:Delete Q24,C663,Add Q68,Q69,Q26,C708-710,R277,R791 for B/T power control cost down.

PAGE32:Delete R234,Add R229 for BID for RevB.
PAGE34: <1>Increase PC207 10uF/25V_1206 for +5VPCU stable.
<2>Change PR58 from 200k ohm to 150K ohm for OCP function.
PAGE38: <1>Increase PC210(390u/2.5V_R6_10), PC211(10U/6.3V_8) & PC212(10U/6.3V_8) for +VGPU_CORE stable.
<2>Change PR74 from 15k ohm to 88.7K ohm for Voltage selected function.
<3>Change PR82 from 5.6k ohm to 6.19K ohm for OCP function.
PAGE39: <1>Increase PC208(10U/25V_1206) & PC209(10U/25V_1206) for +1.5V_SUS stable.
<2>Change PR183 from 10K ohm to 18K ohm and PR184 from 10K ohm to 18.7K ohm for Voltage level modification.
PAGE40: <1>Change PR19 from 25.5K ohm to 30.1K ohm for Voltage level modification.
B->C
PAGE20: <C-01>R81,R83,R54,R51 change to 100ohm for M96 LP DDR3 reference voltage.
PAGE20: <C-02>Delete AR14,AU1,AU2,AC24,R278 for POP noise& add AR13 0ohm & add AD1.
PAGE31: <C-03>Change PR127 to 3.01K for M96 LP power sequence.
Change PR136 to 0 ohm&Delete PC46 for M96 LP power sequence.
Delete PD20,PC213&Change PR199 to 0 ohm for M96 LP power sequence.
PAGE40: <C-04>Add PR203,PR204 100k ohm.
PAGE10/28: <C-05>Delete C330,C482.
PAGE38: <C-06> Change PL2 from 0.56uH to 0.88uH&Delete PC3&Add PC96 for VGA CORE power quality.
C->D
PAGE23: <D-01> Delete U22 & Add R501(CS00002JB38).
C C
PAGE31: <D-02> AMP_PD# circuit change for current leakage issue.

1.Delete AD1,AD2&Add Q24,Q25,Q27(BAM70020001),AR27(CS00002JB38),R189(CS24702JB38).
PAGE38: <D-03> Change PR79 to 3.01K(CS23012FB16).
PAGE34: <D-04> Delete PR176 & PR167.
PAGE35: <D-05> Delete PR35.
PAGE40: <D-08> Delete PR123 & PR128.
PAGE42: <D-09> Add PL11.
PAGE39: <D-10> Change PU11 from RT8207A to UP6163AQAG for shortage.
PAGE24: <D-11>Delete D5,R210,R205&Add Q5,Q6(BAM70020001),R203,R206(CS31002JB28) for HDMI 7-13 issue.
PAGE36: <D-12> Add PD13 & PD15 to save power.
PAGE23/31: <D-13> Add AC12,AC13,C503,C504 for EMI
PAGE 31: <D-14> Add de-pop noise circuit.
D->E
<E-01> For ATI DIAG fail issue.
PAGE 17: <E-01>Change R302 from CS11002FB22 to CS06192FB02.
PAGE 17: <E-01>Change R303 from P/N CS11622FB15 to P/N CS07502FB17.
PAGE 17: <E-01>Delete R304(Change to short pad)
PAGE 17: <E-01>Delete R199(Change to short pad)
B <E-02> For VGA power sequence re-tuning. B
PAGE 38: <E-02>Delete PC225 P/N CH4222K9B04.

PAGE 38: <E-02>Change PR PR226 from P/N CS23012FB16 to CS00002JB38
PAGE 40: <E-02>Change PR200 from P/N CS00002JB38 to P/N CS31402FB12.
PAGE 40: <E-02>Add PC214 P/N CH4222K9B04.
<E-03> For VGA power ripple reduction.
PAGE 38: <E-02>Change PR242 from CS36652FB16 to CS36802FB00.
E->F
<F-01> For OS hang up issue
PAGE 34,36,40: <F-01>Add C720, C721, C723, C725, C729&C524 change to 1uF
PAGE 36,40: <F-01>Add C722, C724, C726&C728 change to 0.1uF
PAGE 40: <F-01>Add PC210 1uf(0402) for +1.8V_GPU.
PAGE 16: <F-02>Add 0ohm for R49.
<F-03> Reduce 27Mhz for overshoot.
PAGE 17: <F-03>Change R304 to 33ohm from 0ohm.
<F-04> EMI suggestion.
PAGE 23: <F-04>Add L2 for USB common choke.
PAGE 09: <F-04>Add C592 22P.
PAGE 38: <F-04>Add PC218 2200P & PR123 2.2R.
PAGE 25: <F-04>Add C460 22P.
PAGE 31: <F-04>Add AC5 10P.
PAGE 17: <F-05>Delete D20.
<F-06> PAGE 42: Add PD5 to prevent from surge voltage.
A A

PROJECT : FH2A
1A
CHANGE HISTORY
5 4 3 2 1

Quanta FH2A Intel Calpella Arrandale REV 1A

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Quanta FH2A Intel Calpella Arrandale REV 1A

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1 2 3 4 5 6 7 8

AUDIO/AMP NEW CARD W83L351YG

Quanta Computer Inc.

08-13 Ibex Peak-M

25 Card Reader (RTS5159)

T5: MAINON to MAINON2 =500us PLTRST#

Madison VGA Power Sequence

voltages within 20 ms of the start of the ramp-up sequence.

MadisonVGA Power Up/Down Sequence

Quanta Computer Inc.

L30 BLM21PG600SN1D 40mil +3.3V_CLK_VDD 1 VDD_USB CLK_BUF_BCLK_P

HP: 10u x2pcs

the 10uF caps on the VDD_IO plane.

Realtek date sheet(V1.2) P11: Min 1.05V,Max 3.3V.

PIN 30 CPU_0 CPU_1 SLG date sheet (V0.2) P15:

R200 IDT date sheet(V0.7) P10: Quanta Computer Inc.

EMI Capacitor Size Document Number Rev

G18 D31 PEG_RX5 H_CPURST# AP26 AP28 XDP_TMS T34

JTAG & BPM

Clarksfield/Auburndale *2N7002E R459 *0/J_4

H_COMP2 SM_RCOMP_0 PM_THRMTRIP# STUP AS SHORT AS PASSPBLE

M_A_DQ35 SA_DQ[34] SA_DQS#[0] M_A_DQSN1 M_B_DQ37 SB_DQ[36] SB_DQS#[2] M_B_DQSN3

DDR SYSTEM MEMORY - B

CPU Core Power

+1.05V_VTT=1.8 max +1.05V_VTT

1.1V RAIL POWER

C AC27 AB10 T4 + C331 C

PEG & DMI

VCC62 VTT1_52 VTT1_68

R28 VCC88 VCC_SENSE AJ34 VCCSENSE (36)

AUBURNDALE/CLARKSFIELD PROCESSOR (POWER) Quanta Computer Inc.

ARRANDALE PROCESSOR (GND) ARRANDALE PROCESSOR( RESERVED, CFG)

VSS1 VSS81 AE34

IBEX PEAK-M (DMI,FDI,GPIO) IBEX PEAK-M (LVDS,DDI)

Digital Display Interface

XDP_DBRESET# T6 J12 PCIE_WAKE# AP48

System Power Management

CLKRUN# R420 8.2K_4 PCH_PWRGD R180 10K/J_4

XDP_DBRESET# R175 1K/J_4 ICH_RSMRST# R402 10K/J_4

LAN_RST# R409 10K/J_4

+3V_S5 PM_SLP_LAN#_R R158 10K/J_4

PM_RI# R410 10K/J_4

PCIE_WAKE# R161 10K/J_4

PM_BATLOW# R415 8.2K/J_4

AC_PRESENT R193 8.2K/J_4

SUS_PWR_ACK R449 8.2K/J_4

Quanta Computer Inc.

AAA-BAT-054-K01 +VCC_RTC R405 330K/J_4 PCH_INVRMEN A14 AB9

INTVRMEN(Internal Voltage Regulator Enable) : ACZ_BIT_CLK A30 HDA_BCLK

RESET JUMP (Near ROOM DOOR)

R451 R454 R434 R440 C629 3 4

IBEX PEAK-M (PCI,USB,NVRAM)

From CLK BUFFER

Loading and fanout concerns. 10P8R-8.2K

U11 Boot BIOS Strap

PCI_STOP# 6 5 0 1 PCI 2.2K/F_4

(32) SIO_EXT_SCI# SIO_EXT_SCI# D37 TACH2 / GPIO6

A4 VSS_NCTF_1 TP11 AJ24

R155 10K/J_4 GPIO35

IBEX PEAK-M (POWER) +1.05V_PCH

Clock and Miscellaneous

+1.05V_PCH AM23 AP11 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 AF34

VCC3_3 = 0.357A max VCCIO[13] AD19

VCCRTC = 2mA max

Clarksfield/Auburndale 2N7002E R459 0/J_4