Acer Aspire 4738G (Quanta ZQ9) Laptop Schematics

5 4 3 2 1
VER : 1A
BOM P/N Description ZQ9 SYSTEM BLOCK DIAGRAM
D D
Channel B
64Mb * 16 *4 pc
P22
Arrandale ATI-Park
rPGA 989 VRAM DDRIII EXT_HDMI
Dual Channel DDR III P4, 5, 6, 7 PCI-E x16 512MB
DDRIII-SODIMM1
800/1066 MHZ IMC GFX
DDRIII-SODIMM2 EXT_CRT
P14,15
CRT Con.
EXT_LVDS P23
P16, 17, 18, 21, 22, 23
FDI DMI
X'TAL SLG8LV595 DMI(x4)

14.318MHz CLOCK USB-8
LVDS/CCD/MIC
INT_CRT
GENERATOR P3 FDI DMI Con.
INT_LVDS Int. MIC P23
CLK
Display
C C
SATA 0
SATA - HDD
P28 INT_HDMI PS8101
SATA
LS P24 HDMI Con.
SATA - ODD SATA 1
P28 EXT_HDMI P24
PCIE-6
PCI-E x1
USB Port USB-1 MINI CARD
USB Ibex Peak-M USB-13
P33 WLAN
P27
USB-3/9/11 PCH
USB/B Con. P33 P8, 9, 10, 11, 12, 13
(USB Port x2) PCIE-1 BRM 57780
RJ45
USB-4
GIGA LAN P26
Bluetooth Con. X'TAL P26
32.768KHz
P33
X'TAL
B 25MHz B
Cardreader AU6437-GBL USB-12 X'TAL 25MHz
P31
Cardreader control
P31
P9 BATTERY RTC
Azalia SPI SPI ROM

IHDA
P9
LPC
ISL88731A UP6111AQDD ISL62881HRZ-T
LPC Batery Charger P36 +1.05V P39 +VGFX_AXG P41
Int. MIC ALC272X NPCE781 X'TAL RT8206B RT8207A HPA00835RTER

AUDIO CODEC P30 EC P37 32.768KHz 3V/5V P37 +1.5V_SUS P40 +1.8V P43
ADP3212 MAX8792ETD+T Discharger

CPU core P38 +VGPU_CORE P42 P43
BOM Option Table

GMT 1453L amp Touch Pad
A MIC JACK P29 A
P30 Board Con. RT9018A Thermal Protection

Reference Description
P34 +1V P44 P44
IV@ for UMA only SKU
for Discrete Graphic only SKU Speaker W25X40BVSSIG
EV@
P30 SPI FLASH P35
for different VRAM parts K/B Con. Fan Driver Quanta Computer Inc.
VRAM@
HP P30 P34 (PWM Type) P34
* do not stuff PROJECT : ZQ9
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Size Document Number Rev
1A
Block Diagram
Date: Tuesday, June 22, 2010 Sheet 1 of 45
5 4 3 2 1
1 2 3 4 5 6 7 8
GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)

+3.3V VIN VIN +1.5V +1.5V_SUS +1.8V +5V
VDDR3 +3V_D VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 PG_1.5V_EN VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
MOS (AO3413) ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO6402) AO3413
P22 P44 P45 P47 P43 P43 P22 P22
A
+3_D (0.5A) +VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +1.8V_GPU (3A) +5_GPU A
GPU PWR CTRL Option 2 (VDDR3 after VDDR1)

VIN VIN +1.5V +1.5V_SUS +3.3V +1.8V +5V
VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 +1.5V_GPU VDDR3 +3V_D VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO3413) MOS (AO6402) AO3413
P44 P45 P47 P43 P22 P43 P22 P22
+VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +3_D (0.5A) +1.8V_GPU (3A) +5_GPU
Thermal Follow Chart

Power States
CONTROL
POWER PLANE VOLTAGE DESCRIPTION ACTIVE IN
SIGNAL
B VIN +10V~+19V MAIN POWER ALWAYS ALWAYS B
+VCCRTC +3V~+3.3V RTC POWER ALWAYS ALWAYS NTC

Thermal
+3VPCU +3.3V EC POWER ALWAYS ALWAYS
Protection
+5VPCU +5V CHARGE POWER ALWAYS ALWAYS
+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS
+3V_S5 +3.3V LAN/BT/CIR POWER S5_ON S0-S5 CPU 3V/5 V

H_ORICHOT# PM_THRMTRIP# SYS_SHDN#
CORE PWR
CPU WIRE-AND SYS PWR
+5V_S5 +5V USB POWER S5_ON S0-S5 H/W Throttling
+5V +5V HDD/ODD/Codec/TP/CRT/HDMI POWER MAINON S0
+3V +3.3V PCH/GPU/Peripheral component POWER MAINON S0

SML1ALERT#
+1.5VSUS +1.5V CPU/SODIMM CORE POWER SUSON S0-S3
PCH FAN Driver FAN
+0.75V_DDR_VTT +0.75V SODIMM Termination POWER MAINON S0
+VGFX_AXG variation Internal GPU POWER GFX_ON S0

SM-Bus
+1.8V +1.8V CPU/PCH/Braidwood POWER MAINON S0
C C
+1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0

EC
+1.1V_VTT +1.05V or +1.1V CPU VTT POWER MAINON S0 CPUFAN#
+1.05V +1.05V PCH CORE POWER MAINON S0
+VCC_CORE variation CPU CORE POWER VRON S0
LCDVCC +3.3V LCD POWER LVDS_VDDEN S0
+5V_GPU +5V SWITCHABLE PWM IC POWER dGPU_PWR_EN# Discrete enable
+GPU_CORE +0.9V~+1.1V GPU CORE POWER +3V_D Discrete enable
+GPU_IO +0.9V~+1.1V GPU I/O POWER PG_GPUIO_EN Discrete enable
+1.5V_GPU +1.5V VRAM CORE POWER PG_1.5V_EN Discrete enable
+1.8V_GPU +1.8V GPU_CRE/LVDS/PLL POWER +1.5V_GPU Discrete enable
+1V +1V DP/PEG POWER PG_1V_EN Discrete enable
D D
Quanta Computer Inc.
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PROJECT : ZQ9
1A
PWR Status & GPU PWR CRL & THRM
1 2 3 4 5 6 7 8
5 4 3 2 1
D
6/21 unstuff D
150mA(30mil)
+1.5V L50 *PBY160808T-181Y-N/2A/180ohm_6 +1.5V_CLK 80mA(20mil)
+VDDIO_CLK L48 PBY160808T/2A/180ohm_6 +1.05V
C243 C627 C246 6/21 add for 3V CLK gen
C613 C244 C607 C609
.1u/16V_4 .1u/16V_4 .1u/16V_4
R565 .1u/16V_4 .1u/16V_4 10u/Y5V_8 10u/Y5V_8
0_6 U20
Place each 0.1uF cap as close as
1 VDD_DOT possible to each VDD IO pin. Place
17 VDD_SRC VDD_SRC_I/O 15 the 10uF caps on the VDD_IO plane.
24 VDD_CPU VDD_CPU_I/O 18
20mil 5 VDD_27
+3V L23 BLM18AG601SN1D/200mA/600ohm_6 +3V_CLK 29 3
VDD_REF DOT_96 CLK_BUF_DREFCLK <10>
DOT_96# 4 CLK_BUF_DREFCLK# <10>
CLK_SDATA 31
C238 C267 C251 CLK_SCLK SDA R448 *EV@33_4
32 SCL 27M 6 27M_CLK <17>
7 R447 *EV@33_4 27M_CLK_SS <17>
4.7u/10V_8 .1u/16V_4 .1u/16V_4 27M_SS C270 *EV@10p/50V_4
R455 33_4 CPU_SEL 30 10 5/13 add for cost down solution
<10> CLK_ICH_14M REF_0/CPU_SEL SRC_1/SATA CLK_BUF_DREFSSCLK <10>
SRC_1#/SATA# 11 CLK_BUF_DREFSSCLK# <10>
C614 33p/50V_4 13
SRC_2 CLK_BUF_PCIE_3GPLL <10>
C SRC_2# 14 CLK_BUF_PCIE_3GPLL# <10> C
XTAL_IN 28 6/21 change the order
Y6 XTAL_IN +3V
14.318MHz XTAL_OUT 27 16 R130 10K_4
XTAL_OUT *CPU_STOP#
C612 33p/50V_4 2 20
VSS_DOT CPU_1 TP23
8 VSS_27 CPU_1# 19 TP24
9 VSS_SATA CPU_0 23 CLK_BUF_BCLK <10>
12 VSS_SRC CPU_0# 22 CLK_BUF_BCLK# <10>
21 VSS_CPU
IDT: AL003197001 (ICS9LVS3197AKLFT) 26 25 CK_PWRGD_R
VSS_REF CKPWRGD/PD#
33
Realtek: AL000890000 (RTM890N-632-GRT) GND
Silego: AL000595000 (SLG8LV595VTR)
ICS9LRS3197AKLFT
+3V
CPU_CLK select SMBus
B
+1.05V
CLK Enable +3V B
R543
R545
2
R451 2.2K_4 1K/F_4
*10K_4
3 1 CLK_SDATA CLK_SDATA <14,15,27>
<10> ICH_SMBDATA
CK_PWRGD_R
CPU_SEL Q18
3
2N7002K Q19
2N7002K
R446 C617
+3V <38> VR_PWRGD_CK505# 2 R544
10K_4 *10p/50V/COG_4 100K/F_4
1
R542
2
2.2K_4
0 1
3 1 CLK_SCLK CLK_SCLK <14,15,27>
<10> ICH_SMBCLK
A CPU_SEL CPU0/1=133MHz CPU0/1=100MHz Q17 A
2N7002K
(default)

PROJECT : ZQ9
1A
Clock Generator
5 4 3 2 1
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5 4 3 2 1
AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)

DPLL_REF_SSCLK and DPLL_REF_SSCLK# can be connected to GND on Arrandale
directly if motherboard only supports discrete graphics. If motherboard supports
integrated graphics but without eDP, these pins can also be connected to GND directly.
Processor Compensation Signals
U22A U22B T20
B26 R436 49.9/F_4 R444 20/F_4 H_COMP3 AT23
PEG_ICOMPI COMP3
A26 A16 CLK_CPU_BCLK <11>
PEG_ICOMPO BCLK
MISC
A24 B27 R442 20/F_4 H_COMP2 AT24 B16 CLK_CPU_BCLK# <11>
<8> DMI_TXN0 DMI_RX#[0] PEG_RCOMPO COMP2 BCLK#
C23 A25 R437 750/F_4
<8> DMI_TXN1 DMI_RX#[1] PEG_RBIAS R173 49.9/F_4 H_COMP1 T62 T21
CLOCKS
<8> DMI_TXN2 B22 PEG_RXN[0..15] <16> G16 AR30
DMI_RX#[2] PEG_RXN0 COMP1 BCLK_ITP T67
<8> DMI_TXN3 A21 K35 AT30
D DMI_RX#[3] PEG_RX#[0] PEG_RXN1 R440 49.9/F_4 H_COMP0 BCLK_ITP# D
J34 AT26
PEG_RX#[1] PEG_RXN2 COMP0
<8> DMI_TXP0 B24 J33 E16 CLK_PCIE_3GPLL <10>
DMI_RX[0] PEG_RX#[2] PEG_RXN3 PEG_CLK
<8> DMI_TXP1 D23 G35 D16 CLK_PCIE_3GPLL# <10>
DMI_RX[1] PEG_RX#[3] PEG_CLK#
DMI
B23 G32 PEG_RXN4 T10 AH24
<8> DMI_TXP2 DMI_RX[2] PEG_RX#[4] SKTOCC#
A22 F34 PEG_RXN5 A18 DPLL_REF_SSCLK_R R465 *IV@0_4 DPLL_REF_SSCLK <10>
<8> DMI_TXP3 DMI_RX[3] PEG_RX#[5] DPLL_REF_SSCLK
F31 PEG_RXN6 A17 DPLL_REF_SSCLK#_R R471 *IV@0_4 DPLL_REF_SSCLK# <10>
PEG_RX#[6] PEG_RXN7 H_CATERR# DPLL_REF_SSCLK# R472 0_4
D24 D35 AK14
<8> DMI_RXN0 DMI_TX#[0] PEG_RX#[7] Use reverse type CATERR#
THERMAL
G24 E33 PEG_RXN8 R463 0_4
<8> DMI_RXN1 DMI_TX#[1] PEG_RX#[8]
F23 C33 PEG_RXN9 Layout Note: Place
<8>
<8>
DMI_RXN2
DMI_RXN3 H23
DMI_TX#[2]
DMI_TX#[3]
PEG_RX#[9]
PEG_RX#[10]
D32
B32
PEG_RXN10
PEG_RXN11
(at GPU side) AT15
SM_DRAMRST#
F6 DDR3_DRAMRST# <14,15> these resistors
PEG_RX#[11] <11> H_PECI PECI
<8> DMI_RXP0 D25
DMI_TX[0] PEG_RX#[12]
C31 PEG_RXN12
SM_RCOMP[0]
AL1 SM_RCOMP_0 R254 100/F_4 near Processor
F24 B28 PEG_RXN13 AM1 SM_RCOMP_1 R253 24.9/F_4
<8> DMI_RXP1 DMI_TX[1] PEG_RX#[13] SM_RCOMP[1]
E23 B30 PEG_RXN14 AN1 SM_RCOMP_2 R252 130/F_4
<8> DMI_RXP2 DMI_TX[2] PEG_RX#[14] SM_RCOMP[2]
G23 A31 PEG_RXN15 <38> H_PROCHOT# H_PROCHOT# AN26
<8> DMI_RXP3 DMI_TX[3] PEG_RX#[15] PROCHOT#
PEG_RXP[0..15] <16> AN15 PM_EXTTS#0 <14>
PM_EXT_TS#[0]
DDR3
MISC
J35 PEG_RXP0 AP15 R187 10K_4
PEG_RX[0] PEG_RXP1 PM_EXT_TS#[1] R183 10K_4
H34 +1.05V
PEG_RX[1] PEG_RXP2
H33 <11> PM_THRMTRIP# AK15 PM_EXTTS#1 <15>
PEG_RX[2] PEG_RXP3 THERMTRIP#
<8> FDI_TXN0 E22 F35
FDI_TX#[0] PEG_RX[3] PEG_RXP4
<8> FDI_TXN1 D21 G33
FDI_TX#[1] PEG_RX[4] PEG_RXP5 T68
<8> FDI_TXN2 D19 E34 AT28
FDI_TX#[2] PEG_RX[5] PEG_RXP6 PRDY# XDP_PREQ# T69
<8> FDI_TXN3 D18 F32 AP27
FDI_TX#[3] PEG_RX[6] PEG_RXP7 PREQ#
<8> FDI_TXN4 G21 D34
FDI_TX#[4] PEG_RX[7] PEG_RXP8 XDP_TCLK T8
<8> FDI_TXN5 E19 F33 AN28
FDI_TX#[5] PEG_RX[8] TCK
PCI EXPRESS -- GRAPHICS
F21 B33 PEG_RXP9 H_CPURST# AP26 AP28 XDP_TMS T9
<8> FDI_TXN6 FDI_TX#[6] PEG_RX[9] RESET_OBS# TMS
Intel(R) FDI
PWR MANAGEMENT
G18 D31 PEG_RXP10 AT27 XDP_TRST# T71
<8> FDI_TXN7 FDI_TX#[7] PEG_RX[10] TRST#
PEG_RXP11
JTAG & BPM

A32
PEG_RX[11] PEG_RXP12 XDP_TDI_R T70
C30 <8> PM_SYNC AL15 AT29
PEG_RX[12] PEG_RXP13 PM_SYNC TDI XDP_TDO_R T66
<8> FDI_TXP0 D22 A28 AR27
FDI_TX[0] PEG_RX[13] PEG_RXP14 TDO XDP_TDI_M T65
<8> FDI_TXP1 C21 B29 PEG_TXN[0..15] <16> AR29
FDI_TX[1] PEG_RX[14] PEG_RXP15 TDI_M XDP_TDO_M T64
<8> FDI_TXP2 D20 A30 AN14 AP29
FDI_TX[2] PEG_RX[15] VCCPWRGOOD_1 TDO_M
<8> FDI_TXP3 C18
FDI_TX[3] CPEG_TXN0 C587 EV@0.1u/10V_4_X7R PEG_TXN0 H_DBR#_R R149 *Short_4
<8> FDI_TXP4 G22 L33 AN25 XDP_DBRST# <8>
C FDI_TX[4] PEG_TX#[0] CPEG_TXN1 C565 EV@0.1u/10V_4_X7R PEG_TXN1 DBR# C
<8> FDI_TXP5 E20 M35 <11> H_PWRGOOD AN27
FDI_TX[5] PEG_TX#[1] CPEG_TXN2 C585 EV@0.1u/10V_4_X7R PEG_TXN2 VCCPWRGOOD_0
<8> FDI_TXP6 F20 M33
FDI_TX[6] PEG_TX#[2] CPEG_TXN3 C563 EV@0.1u/10V_4_X7R PEG_TXN3 XDP_OBS0 T19
<8> FDI_TXP7 G19 M30 AJ22
FDI_TX[7] PEG_TX#[3] CPEG_TXN4 C583 EV@0.1u/10V_4_X7R PEG_TXN4 BPM#[0] XDP_OBS1 T18
L31 <8> PM_DRAM_PWRGD AK13 AK22
FDI_FSYNC0_R PEG_TX#[4] CPEG_TXN5 C561 EV@0.1u/10V_4_X7R PEG_TXN5 SM_DRAMPWROK BPM#[1] XDP_OBS2 T17
F17 K32 AK24
FDI_FSYNC1_R FDI_FSYNC[0] PEG_TX#[5] CPEG_TXN6 C581 EV@0.1u/10V_4_X7R PEG_TXN6 BPM#[2] XDP_OBS3 T13
E17 M29 AJ24
FDI_FSYNC[1] PEG_TX#[6] CPEG_TXN7 C559 EV@0.1u/10V_4_X7R PEG_TXN7 H_VTTPWRGD BPM#[3] XDP_OBS4 T11
J31 AM15 AJ25
FDI_INT_R PEG_TX#[7] CPEG_TXN8 C579 EV@0.1u/10V_4_X7R PEG_TXN8 VTTPWRGOOD BPM#[4] XDP_OBS5 T15
C17 K29 AH22
FDI_INT PEG_TX#[8] CPEG_TXN9 C557 EV@0.1u/10V_4_X7R PEG_TXN9 BPM#[5] XDP_OBS6 T16
H30 AK23
FDI_LSYNC0_R PEG_TX#[9] CPEG_TXN10 C577 EV@0.1u/10V_4_X7R PEG_TXN10 T14 BPM#[6] XDP_OBS7 T12
F18 H29 AM26 AH23
FDI_LSYNC1_R FDI_LSYNC[0] PEG_TX#[10] CPEG_TXN11 C555 EV@0.1u/10V_4_X7R PEG_TXN11 TAPPWRGOOD BPM#[7]
D17 F29
FDI_LSYNC[1] PEG_TX#[11] CPEG_TXN12 C575 EV@0.1u/10V_4_X7R PEG_TXN12
E28
PEG_TX#[12] CPEG_TXN13 C594 EV@0.1u/10V_4_X7R PEG_TXN13 R193 1.5K/F_4 CPU_PLTRST# AL14
D29 <10,11,25,27,31,35> PLTRST#
PEG_TX#[13] CPEG_TXN14 C602 EV@0.1u/10V_4_X7R PEG_TXN14 RSTIN#
D27 PEG_TXP[0..15] <16>
PEG_TX#[14] CPEG_TXN15 C608 EV@0.1u/10V_4_X7R PEG_TXN15 R196
C26
PEG_TX#[15] 750/F_4
L34 CPEG_TXP0 C586 EV@0.1u/10V_4_X7R PEG_TXP0 Clarksfield/Auburndale
PEG_TX[0] CPEG_TXP1 C564 EV@0.1u/10V_4_X7R PEG_TXP1
M34
M32
L30
M31
PEG_TX[4] CPEG_TXP5 C560 EV@0.1u/10V_4_X7R PEG_TXP5 R157 IV@0_4 FDI_FSYNC0_R
K31 <8> FDI_FSYNC0
PEG_TX[5] CPEG_TXP6 C580 EV@0.1u/10V_4_X7R PEG_TXP6 R161 IV@0_4 FDI_FSYNC1_R
M28 <8> FDI_FSYNC1
H31
PEG_TX[7] CPEG_TXP8 C578 EV@0.1u/10V_4_X7R PEG_TXP8 R171 IV@0_4 FDI_INT_R
K28 <8> FDI_INT
G30
PEG_TX[9] CPEG_TXP10 C576 EV@0.1u/10V_4_X7R PEG_TXP10 R152 IV@0_4 FDI_LSYNC0_R
G29 <8> FDI_LSYNC0
PEG_TX[10] CPEG_TXP11 C554 EV@0.1u/10V_4_X7R PEG_TXP11 R167 IV@0_4 FDI_LSYNC1_R
F28 <8> FDI_LSYNC1
E27
PEG_TX[12] CPEG_TXP13 C596 EV@0.1u/10V_4_X7R PEG_TXP13 R156 EV@1K_4
D28
C27
C25
PEG_TX[15] R151 EV@1K_4
R166 EV@1K_4
B B
Clarksfield/Auburndale
<The GFX_IMON, FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and FDI_INT>Note that if these signals are left as no connect, there are no functional impacts, but a small amount of power (~15 mW) maybe wasted.
Processor pull-up JTAG MAPPING 5/13 follow ZR7B setting

Thermaltrip protect VTT PWR_Good 5/13 follow ZR7B setting
XDP_TDI_R XDP_TDI
+1.05V R433 0_4
XDP_TDO_M XDP_TDO
XDP_TDO R420 51/F_4 R429 *0_4
+1.05V H_CATERR# R192 49.9/F_4
6/14 change the P/N H_PROCHOT# R137 68_4 R431
H_CPURST# R438 *68_4
3
XDP_TMS R135 *51_4 0_4

+3V XDP_TDI_R R435 *51_4
XDP_PREQ# R434 *51_4 XDP_TDI_M
2 Q16 XDP_TCLK R133 *51_4 R432 *0_4
<8,38> DELAY_VR_PWRGOOD
XDP_TRST# R439 51/F_4 XDP_TDO_R
FDV301N C309 R430 0_4
0.1u/10V_4
1
Scan Chain STUFF -> R469, R491, R507

5
R209 (Default) NO STUFF -> R489, R490

1K_4 <35> MPWROK 2 R176 +1.5VSUS
4 H_VTTPWRGD
1 CPU Only STUFF -> R490, R491
2K/F_4 Use a voltage divider with VDDQ NO STUFF -> R469, R489, R507
U5 R205 (1.5V) rail (ON in S3) and
3
2
A R179 1.1K/F_4 A
resistor combination of 4.75K (to
Q15 TC7SH08FU 1K_4 GMCH Only STUFF -> R489, R507
PM_THRMTRIP# 1 3 MMBT3904 PM_DRAM_PWRGD VDDQ)/12K(to GND) to generate the NO STUFF -> R491, R490, R469
<11> PM_THRMTRIP# SYS_SHDN# <37,44> required voltage.
R199 Note: CRB uses a 3.3V (always ON)
3K/F_4 rail with 2K and 1K combination.

PROJECT : ZQ9
1A
AUBURNDA 1/4
5 4 3 2 1
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5 4 3 2 1
AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3) U22D
U22C
<15> M_B_DQ[63:0] SB_CK[0] W8 M_B_CLK0 <15>

SB_CK#[0] W9 M_B_CLK0# <15>
M_B_DQ0 B5 M3
SB_DQ[0] SB_CKE[0] M_B_CKE0 <15>
M_B_DQ1 A5
M_B_DQ2 SB_DQ[1]
SA_CK[0] AA6 M_A_CLK0 <14> C3 SB_DQ[2]
AA7 M_A_CLK0# <14> M_B_DQ3 B3 V7 M_B_CLK1 <15>
SA_CK#[0] M_B_DQ4 SB_DQ[3] SB_CK[1]
<14> M_A_DQ[63:0] SA_CKE[0] P7 M_A_CKE0 <14> E4 SB_DQ[4] SB_CK#[1] V6 M_B_CLK1# <15>
D M_A_DQ0 M_B_DQ5 D
A10 SA_DQ[0] A6 SB_DQ[5] SB_CKE[1] M2 M_B_CKE1 <15>
M_A_DQ1 C10 M_B_DQ6 A4
M_A_DQ2 SA_DQ[1] M_B_DQ7 SB_DQ[6]
C7 SA_DQ[2] C4 SB_DQ[7]
M_A_DQ3 A7 Y6 M_B_DQ8 D1
SA_DQ[3] SA_CK[1] M_A_CLK1 <14> SB_DQ[8]
M_A_DQ4 B10 Y5 M_B_DQ9 D2
SA_DQ[4] SA_CK#[1] M_A_CLK1# <14> SB_DQ[9]
M_A_DQ5 D10 P6 M_A_CKE1 <14> M_B_DQ10 F2 AB8 M_B_CS#0 <15>
M_A_DQ6 SA_DQ[5] SA_CKE[1] M_B_DQ11 SB_DQ[10] SB_CS#[0]
E10 F1 AD6 M_B_CS#1 <15>
M_A_DQ7 SA_DQ[6] M_B_DQ12 SB_DQ[11] SB_CS#[1]
A8 SA_DQ[7] C2 SB_DQ[12]
M_A_DQ8 D8 M_B_DQ13 F5
F10 AE2 M_A_CS#0 <14> F3
M_A_DQ10 SA_DQ[9] SA_CS#[0] M_B_DQ15 SB_DQ[14]
E6 SA_DQ[10] SA_CS#[1] AE8 M_A_CS#1 <14> G4 SB_DQ[15] SB_ODT[0] AC7 M_B_ODT0 <15>
M_A_DQ11 F7 M_B_DQ16 H6 AD1
SA_DQ[11] SB_DQ[16] SB_ODT[1] M_B_ODT1 <15>
M_A_DQ12 E9 M_B_DQ17 G2
B7 J6
E7 AD8 M_A_ODT0 <14> J3
M_A_DQ15 SA_DQ[14] SA_ODT[0] M_B_DQ20 SB_DQ[19]
C6 AF9 M_A_ODT1 <14> G1 M_B_DM[7:0] <15>
M_A_DQ16 SA_DQ[15] SA_ODT[1] M_B_DQ21 SB_DQ[20] M_B_DM0
H10 SA_DQ[16] G5 SB_DQ[21] SB_DM[0] D4
M_A_DQ17 G8 M_B_DQ22 J2 E1 M_B_DM1
M_A_DQ18 SA_DQ[17] M_B_DQ23 SB_DQ[22] SB_DM[1] M_B_DM2
K7 SA_DQ[18] J1 SB_DQ[23] SB_DM[2] H3
M_A_DQ19 J8 M_B_DQ24 J5 K1 M_B_DM3
G7 K2 AH1
G10 M_A_DM[7:0] <14> L3 AL2
M_A_DQ22 SA_DQ[21] M_A_DM0 M_B_DQ27 SB_DQ[26] SB_DM[5] M_B_DM6
J7 SA_DQ[22] SA_DM[0] B9 M1 SB_DQ[27] SB_DM[6] AR4
M_A_DQ23 J10 D7 M_A_DM1 M_B_DQ28 K5 AT8 M_B_DM7
M_A_DQ24 SA_DQ[23] SA_DM[1] M_A_DM2 M_B_DQ29 SB_DQ[28] SB_DM[7]
L7 H7 K4
M_A_DQ25 SA_DQ[24] SA_DM[2] M_A_DM3 M_B_DQ30 SB_DQ[29]
M6 SA_DQ[25] SA_DM[3] M7 M4 SB_DQ[30]
M_A_DQ26 M8 AG6 M_A_DM4 M_B_DQ31 N5
L9 AM7 AF3
L6 SA_DQ[28] SA_DM[6] AN10 AG1 SB_DQ[33] M_B_DQS#[7:0] <15>
M_A_DQ29 K8 AN13 M_A_DM7 M_B_DQ34 AJ3 D5 M_B_DQS#0
M_A_DQ30 SA_DQ[29] SA_DM[7] M_B_DQ35 SB_DQ[34] SB_DQS#[0] M_B_DQS#1
N8 AK1 F4
M_A_DQ31 SA_DQ[30] M_B_DQ36 SB_DQ[35] SB_DQS#[1] M_B_DQS#2
P9 AG4 J4
C M_A_DQ32 SA_DQ[31] M_B_DQ37 SB_DQ[36] SB_DQS#[2] M_B_DQS#3 C
AH5 SA_DQ[32] AG3 SB_DQ[37] SB_DQS#[3] L4
M_A_DQ33 AF5 M_B_DQ38 AJ4 AH2 M_B_DQS#4
SA_DQ[33] M_A_DQS#[7:0] <14> SB_DQ[38] SB_DQS#[4]
DDR SYSTEM MEMORY - B

M_A_DQ34 AK6 C9 M_A_DQS#0 M_B_DQ39 AH4 AL4 M_B_DQS#5
SA_DQ[34] SA_DQS#[0] SB_DQ[39] SB_DQS#[5]
DDR SYSTEM MEMORY A
M_A_DQ35 AK7 F8 M_A_DQS#1 M_B_DQ40 AK3 AR5 M_B_DQS#6

M_A_DQ36 SA_DQ[35] SA_DQS#[1] M_A_DQS#2 M_B_DQ41 SB_DQ[40] SB_DQS#[6] M_B_DQS#7
AF6 SA_DQ[36] SA_DQS#[2] J9 AK4 SB_DQ[41] SB_DQS#[7] AR8
M_A_DQ37 AG5 N9 M_A_DQS#3 M_B_DQ42 AM6
M_A_DQ38 SA_DQ[37] SA_DQS#[3] M_A_DQS#4 M_B_DQ43 SB_DQ[42]
AJ7 SA_DQ[38] SA_DQS#[4] AH7 AN2 SB_DQ[43]
M_A_DQ39 AJ6 AK9 M_A_DQS#5 M_B_DQ44 AK5
M_A_DQ40 SA_DQ[39] SA_DQS#[5] M_A_DQS#6 M_B_DQ45 SB_DQ[44]
AJ10 SA_DQ[40] SA_DQS#[6] AP11 AK2 SB_DQ[45]
M_A_DQ41 AJ9 AT13 M_A_DQS#7 M_B_DQ46 AM4
M_A_DQ42 SA_DQ[41] SA_DQS#[7] M_B_DQ47 SB_DQ[46]
AL10 SA_DQ[42] AM3 SB_DQ[47] M_B_DQS[7:0] <15>
M_A_DQ43 AK12 M_B_DQ48 AP3 C5 M_B_DQS0
M_A_DQ44 SA_DQ[43] M_B_DQ49 SB_DQ[48] SB_DQS[0] M_B_DQS1
AK8 SA_DQ[44] AN5 SB_DQ[49] SB_DQS[1] E3
M_A_DQ45 AL7 M_B_DQ50 AT4 H4 M_B_DQS2
M_A_DQ46 SA_DQ[45] M_A_DQS0 M_A_DQS[7:0] <14> M_B_DQ51 SB_DQ[50] SB_DQS[2] M_B_DQS3
AK11 C8 AN6 M5
M_A_DQ47 SA_DQ[46] SA_DQS[0] M_A_DQS1 M_B_DQ52 SB_DQ[51] SB_DQS[3] M_B_DQS4
AL8 F9 AN4 AG2
AN8 H9 AN3 AL5
AM10 M9 AT5 AP5
AR11 AH8 AT6 AR7
M_A_DQ51 SA_DQ[50] SA_DQS[4] M_A_DQS5 M_B_DQ56 SB_DQ[55] SB_DQS[7]
AL11 SA_DQ[51] SA_DQS[5] AK10 AN7 SB_DQ[56]
M_A_DQ52 AM9 AN11 M_A_DQS6 M_B_DQ57 AP6
M_A_DQ53 SA_DQ[52] SA_DQS[6] M_A_DQS7 M_B_DQ58 SB_DQ[57]
AN9 AR13 AP8
M_A_DQ54 SA_DQ[53] SA_DQS[7] M_B_DQ59 SB_DQ[58]
AT11 AT9
AP12 AT7
AM12 AP9
AN12 M_A_A[15:0] <14> AR10 M_B_A[15:0] <15>
M_A_DQ58 SA_DQ[57] M_A_A0 M_B_DQ63 SB_DQ[62] M_B_A0
AM13 SA_DQ[58] SA_MA[0] Y3 AT10 SB_DQ[63] SB_MA[0] U5
M_A_DQ59 AT14 W1 M_A_A1 V2 M_B_A1
M_A_DQ60 SA_DQ[59] SA_MA[1] M_A_A2 SB_MA[1] M_B_A2
AT12 AA8 T5
AL13 AA3 V3
AR14 V1 R1
AP14 AA9 <15> M_B_BS#0 AB1 T8
B SA_DQ[63] SA_MA[5] M_A_A6 SB_BS[0] SB_MA[5] M_B_A6 B
SA_MA[6] V8 <15> M_B_BS#1 W5 SB_BS[1] SB_MA[6] R2
T1 M_A_A7 R7 R6 M_B_A7
SA_MA[7] <15> M_B_BS#2 SB_BS[2] SB_MA[7]
Y9 M_A_A8 R4 M_B_A8
SA_MA[8] M_A_A9 SB_MA[8] M_B_A9
<14> M_A_BS#0 AC3 SA_BS[0] SA_MA[9] U6 SB_MA[9] R5
<14> M_A_BS#1 AB2 AD4 M_A_A10 <15> M_B_CAS# AC5 AB5 M_B_A10
SA_BS[1] SA_MA[10] M_A_A11 SB_CAS# SB_MA[10] M_B_A11
<14> M_A_BS#2 U7 T2 <15> M_B_RAS# Y7 P3
SA_BS[2] SA_MA[11] M_A_A12 SB_RAS# SB_MA[11] M_B_A12
U3 <15> M_B_WE# AC6 R3
SA_MA[12] M_A_A13 SB_WE# SB_MA[12] M_B_A13
AG8 AF7
T3 P5
<14> M_A_CAS# AE1 SA_CAS# SA_MA[15] V9 SB_MA[15] N1
<14> M_A_RAS# AB3 SA_RAS#
<14> M_A_WE# AE9
SA_WE#
Clarksfield/Auburndale Clarksfield/Auburndale
Channel A DQ[15,32,48,54], DM[5] Channel B DQ[16,18,36,42,56,57,60,61,62]

Requires minimum 12mils spacing Requires minimum 12mils spacing
with all other signals, including data signals. with all other signals, including data signals.
A A

PROJECT : ZQ9
www.vinafix.vn
1A
AUBURNDA 2/4
5 4 3 2 1
5 4 3 2 1
CPU Core Power U22F
VTT Rail Values are AUBURNDALE/CLARKSFIELD PROCESSOR (GRAPHICS POWER)

ARD:48A Auburndal VTT=1.05V
+VCC_CORE Clarksfield VTT=1.1V
5/27 cost down CFD:52A
18A
C568 10U/6.3V_8 AG35 AH14 +1.05V U22G
C626 22U/6.3V_8 VCC1 VTT0_1 T72
AG34 AH12
C234 10U/6.3V_8 AG33
VCC2 VTT0_2
AH11 +VGFX_AXG
22A AT21
C589 22U/6.3V_8 VCC3 VTT0_3 C658 10U/6.3V_8 VAXG1
AG32 AH10 AT19 AR22 VCC_AXG_SENSE <41>
D C623 22U/6.3V_8 VCC4 VTT0_4 C657 10U/6.3V_8 VAXG2 VAXG_SENSE D
SENSE
LINES
AG31 J14 AT18 AT22 VSS_AXG_SENSE <41>
C643 10U/6.3V_8 VCC5 VTT0_5 C634 10U/6.3V_8 VAXG3 VSSAXG_SENSE
AG30 J13 AT16
C642 10U/6.3V_8 VCC6 VTT0_6 C327 10U/6.3V_8 VAXG4 T73
AG29
VCC7 VTT0_7
H14 5/27 cost down AR21
VAXG5
C590 22U/6.3V_8 AG28 H12 C648 10U/6.3V_8 AR19
C567 22U/6.3V_8 VCC8 VTT0_8 C649 10U/6.3V_8 + VAXG6
AG27
VCC9 VTT0_9
G14 5/27 cost down AR18
VAXG7
C640 10U/6.3V_8 AG26 G13 C644 10U/6.3V_8 C635 C281 C280 AR16 AM22 GFX_VID0 <41>
C230 10U/6.3V_8 VCC10 VTT0_10 C659 10U/6.3V_8 *IV@330U/2V_7343 IV@22u/6.3V_8 IV@22u/6.3V_8 VAXG8 GFX_VID[0]
AF35 G12 AP21 AP22 GFX_VID1 <41>
VCC11 VTT0_11 VAXG9 GFX_VID[1]
GRAPHICS VIDs
C588 22U/6.3V_8 AF34 G11 C652 10U/6.3V_8 AP19 AN22 GFX_VID2 <41>
C235 10U/6.3V_8 VCC12 VTT0_12 C331 10U/6.3V_8 VAXG10 GFX_VID[2]
AF33 F14 AP18 AP23 GFX_VID3 <41>
C569 10U/6.3V_8 VCC13 VTT0_13 VAXG11 GFX_VID[3]
AF32 F13 AP16 AM23 GFX_VID4 <41>
AF31 F12 C316 AN21 AP24 GFX_VID5 <41>
VCC15 VTT0_15 VAXG13 GFX_VID[5]
GRAPHICS
C624 10U/6.3V_8 AF30 F11 AN19 AN24 GFX_VID6 <41>
+
AF29 E14 AN18
C638 10U/6.3V_8 VCC17 VTT0_17 VAXG15
AF28 E12 AN16
C625 10U/6.3V_8 VCC18 VTT0_18 VAXG16
AF27 D14 AM21 AR25 GFX_ON <41>
C566 10U/6.3V_8 VCC19 VTT0_19 330u/2V_7343 VAXG17 GFX_VR_EN
AF26
VCC20 VTT0_20
D13 5/27 cost down AM19
VAXG18 GFX_DPRSLPVR
AT25 GFX_DPRSLPVR <41>
C622 10U/6.3V_8 AD35 D12 AM18 AM24
1.1V RAIL POWER

VCC21 VTT0_21 + VAXG19 GFX_IMON GFX_IMON <41>
C266 10U/6.3V_8 AD34 D11 AM16
C265 10U/6.3V_8 VCC22 VTT0_22 C651 C298 C299 VAXG20 R147 EV@1K_4
AD33 C14 AL21
C236 10U/6.3V_8 VCC23 VTT0_23 *IV@330U/2V_7343 IV@10u/6.3V_8 IV@10u/6.3V_8 VAXG21
C641 10U/6.3V_8
AD32
VCC24 VTT0_24
C13 AL19
VAXG22 ARD:3A
AD31 C12 AL18
C287 10U/6.3V_8 VCC25 VTT0_25 VAXG23 CFD:6A
AD30 C11 AL16
C232 10U/6.3V_8 VCC26 VTT0_26 VAXG24
AD29 B14 AK21 AJ1 +1.5VSUS
C633 10U/6.3V_8 VCC27 VTT0_27 VAXG25 VDDQ1
AD28 B12 AK19 AF1
C275 0.1u/10V_4_X7R VCC28 VTT0_28 VAXG26 VDDQ2
- 1.5V RAILS
AD27 A14 AK18 AE7
C271 0.1u/10V_4_X7R VCC29 VTT0_29 VAXG27 VDDQ3 C358 C356 C355 C352
AD26 A13 AK16 AE4
VCC30 VTT0_30 VAXG28 VDDQ4
AC35 A12 AJ21 AC1
+
C284 330u/2V_7343 AC34 A11 AJ19 AB7 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
AC33 AJ18 AB4
VCC33 VAXG31 VDDQ7
+
C285 330u/2V_7343 AC32 +1.05V AJ16 Y1

VCC34 VAXG32 VDDQ8
AC31 AH21 W7
VCC35 VAXG33 VDDQ9
POWER
AC30 AF10 AH19 W4
C VCC36 VTT0_33 VAXG34 VDDQ10 C417 C360 C357 + C363 C
6/21 stuff AC29
VCC37 VTT0_34
AE10 AH18
VAXG35 VDDQ11
U1
AC28 AC10 R153 AH16 T7
CPU CORE SUPPLY

AC27 AB10 C313 22U/6.3V_8 EV@1K_4 T4 1U/6.3V_4 22U/6.3V_8 22U/6.3V_8 330U/2V_7343
VCC39 VTT0_36 VDDQ13
AC26 Y10 P1
VCC40 VTT0_37 C326 22U/6.3V_8 VDDQ14
AA35 W10 N7
AA34 U10 N4
VCC42 VTT0_39 +1.05V VDDQ16
DDR3
AA33 T10 L1
AA32 J12 J24 H1
VCC44 VTT0_41 VTT1_45 VDDQ18
FDI
AA31
VCC45 VTT0_42
J11 5/27 cost down J23
VTT1_46
AA30 J16 H25
VCC46 VTT0_43 VTT1_47
AA29 J15
VCC47 VTT0_44
AA28
VCC48 C311 C655
AA27 P10 +1.05V
VCC49 10U/6.3V_8 22u/6.3V_8 VTT0_59
AA26 N10
VCC50 VTT0_60 C660 10U/6.3V_8
Y35 L10
VCC51 VTT0_61 C654 10U/6.3V_8
Y34 K10
VCC52 VTT0_62
Y33
VCC53
Y32
VCC54
Y31
VCC55 5/27 cost down
Y30
VCC56
1.1V
Y29
VCC57 5/27 cost down VTT1_63
J22
Y28 K26 J20 10U/6.3V_8 C618
VCC58 VTT1_48 VTT1_64 10U/6.3V_8 C630
Y27 J27 J18
PEG & DMI

Y26 J26 H21
VCC60 H_PSI# C332 C656 C312 C330 VTT1_50 VTT1_66
V35 AN33 H_PSI# <38> J25 H20
VCC61 PSI# 10U/6.3V_8 10U/6.3V_8 22u/6.3V_8 22u/6.3V_8 VTT1_51 VTT1_67
V34 H27 H19
POWER

V33 G28
VCC63 H_VID0 VTT1_53
V32 AK35 H_VID0 <38> G27
VCC64 VID[0] H_VID1 VTT1_54
V31
VCC65 VID[1]
AK33
H_VID2
H_VID1 <38> G26
VTT1_55 0.6A
V30 AK34 H_VID2 <38> F26
VCC66 VID[2] H_VID3 VTT1_56
V29 AL35 H_VID3 <38> E26 L26 +1.8V
VCC67 VID[3] VTT1_57 VCCPLL1
CPU VIDS
1.8V
V28 AL33 H_VID4 H_VID4 <38> E25 L27
B VCC68 VID[4] H_VID5 VTT1_58 VCCPLL2 22U/6.3V_8 C258 B
V27 AM33 H_VID5 <38> M26
VCC69 VID[5] H_VID6 VCCPLL3 4.7U/6.3V_6 C274
V26 AM35 H_VID6 <38>
VCC70 VID[6] H_DPRSLPVR 2.2U/6.3V_6 C231
U35 AM34 H_DPRSLPVR <38>
VCC71 PROC_DPRSLPVR 1U/6.3V_4 C233
U34
VCC72 1U/6.3V_4 C239
U33
VCC73
U32
VCC74
U31 G15
VCC75 VTT_SELECT
U30
VCC76 Clarksfield/Auburndale
U29
VCC77 H_VTTVID1=Low, 1.1V
U28
VCC78 H_VTTVID1=High, 1.05V
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32 AN35 I_MON <38>
VCC84 ISENSE
R31
VCC85
R30
VCC86 R104 100/F_4
R29 +VCC_CORE
VCC87
R28 AJ34
SENSE LINES
VCC88 VCC_SENSE VCCSENSE <38>

R27 AJ35 VSSSENSE <38>
1 H_VID0 R388 1K_4 +1.05V
VCC89 VSS_SENSE R395 *1K/F_4
R26
VCC90 R103 100/F_4 1 H_VID1 R387 1K_4
P35
VCC91 VTT_SENSE R394 *1K/F_4
P34 B15 T75
VCC92 VTT_SENSE VSS_SENSE_VTT 1 H_VID2 R389 1K_4
P33 A15 T74
VCC93 VSS_SENSE_VTT R396 *1K/F_4
P32
VCC94 0 H_VID3 R400 *1K/F_4
P31
VCC95 R409 1K_4
P30
VCC96 0 H_VID4 R401 *1K/F_4
P29
VCC97 R410 1K_4
P28
VCC98 1 H_VID5 R404 1K_4
P27
VCC99 R413 *1K/F_4
P26
A VCC100 0 H_VID6 R402 *1K/F_4 A
R411 1K_4
1 H_DPRSLPVR R403 1K_4
R412 *1K/F_4
0 H_PSI# R419 *1K/F_4
R418 1K_4
Note:
For Validating IMVP VR R6451 should be STUFF
HFM_VID : Max 1.4V
and R2N1 NO_STUFF LFM_VID : Min 0.65V PROJECT : ZQ9
AUBURNDALE/CLARKSFIELD PROCESSOR (POWER) Size Document Number Rev
1A
AUBURNDA 3/4 (PWR)
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
AUBURNDALE/CLARKSFIELD PROCESSOR (GND) AUBURNDALE/CLARKSFIELD PROCESSOR( RESERVED, CFG)

U22H U22I U22E
AT20 VSS1 VSS81 AE34 RSVD32 AJ13

AT17 VSS2 VSS82 AE33 RSVD33 AJ12
AR31 VSS3 VSS83 AE32 K27 VSS161
AR28 VSS4 VSS84 AE31 K9 VSS162 AP25 RSVD1
AR26 VSS5 VSS85 AE30 K6 VSS163 AL25 RSVD2 RSVD34 AH25
AR24 VSS6 VSS86 AE29 K3 VSS164 AL24 RSVD3 RSVD35 AK26
AR23 VSS7 VSS87 AE28 J32 VSS165 AL22 RSVD4
AR20 VSS8 VSS88 AE27 J30 VSS166 AJ33 RSVD5 RSVD36 AL26
AR17 VSS9 VSS89 AE26 J21 VSS167 AG9 RSVD6 RSVD_NCTF_37 AR2
AR15 VSS10 VSS90 AE6 J19 VSS168 M27 RSVD7
D AR12 VSS11 VSS91 AD10 H35 VSS169 L28 RSVD8 RSVD38 AJ26 D
AR9 VSS12 VSS92 AC8 H32 VSS170 <14> VREF_DQ_DIMM0 J17 SA_DIMM_VREF RSVD39 AJ27
AR6 VSS13 VSS93 AC4 H28 VSS171 <15> VREF_DQ_DIMM1 H17 SB_DIMM_VREF
AR3 VSS14 VSS94 AC2 H26 VSS172 G25 RSVD11
AP20 VSS15 VSS95 AB35 H24 VSS173 G17 RSVD12
AP17 VSS16 VSS96 AB34 H22 VSS174 E31 RSVD13 RSVD_NCTF_40 AP1
AP13 VSS17 VSS97 AB33 H18 VSS175 E30 RSVD14 RSVD_NCTF_41 AT2
AP10 VSS18 VSS98 AB32 H15 VSS176
AP7 VSS19 VSS99 AB31 H13 VSS177 RSVD_NCTF_42 AT3
AP4 VSS20 VSS100 AB30 H11 VSS178 RSVD_NCTF_43 AR1
AP2 VSS21 VSS101 AB29 H8 VSS179
AN34 VSS22 VSS102 AB28 H5 VSS180
AN31 VSS23 VSS103 AB27 H2 VSS181
AN23 VSS24 VSS104 AB26 G34 VSS182 RSVD45 AL28
AN20 AB6 G31 CFG0 AM30 AL29
VSS25 VSS105 VSS183 CFG[0] RSVD46
AN17 VSS26 VSS106 AA10 G20 VSS184 AM28 CFG[1] RSVD47 AP30
AM29 VSS27 VSS107 Y8 G9 VSS185 AP31 CFG[2] RSVD48 AP32
AM27 Y4 G6 CFG3 AL32 AL27
VSS28 VSS108 VSS186 CFG4 CFG[3] RSVD49
AM25 VSS29 VSS109 Y2 G3 VSS187 AL30 CFG[4] RSVD50 AT31
AM20 VSS30 VSS110 W 35 F30 VSS188 AM31 CFG[5] RSVD51 AT32
AM17 VSS31 VSS111 W 34 F27 VSS189 AN29 CFG[6] RSVD52 AP33
AM14 W 33 F25 CFG7 AM32 AR33
VSS32 VSS112 VSS190 CFG[7] RSVD53
AM11 VSS33 VSS113 W 32 F22 VSS191 AK32 CFG[8] RSVD_NCTF_54 AT33
AM8 W 31 F19 AK31 AT34
RESERVED
VSS34 VSS114 VSS192 CFG[9] RSVD_NCTF_55
AM5 VSS35 VSS115 W 30 F16 VSS193 AK28 CFG[10] RSVD_NCTF_56 AP35
AM2 VSS36 VSS116 W 29 E35 VSS194 AJ28 CFG[11] RSVD_NCTF_57 AR35
AL34 W 28 E32 AN30 AR32
AL31
AL23
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
W 27
W 26
E29
E24
VSS195
VSS196
VSS197
VSS AN32
AJ32
CFG[12]
CFG[13]
CFG[14]
RSVD58
AL20 VSS40 VSS120 W6 E21 VSS198 AJ29 CFG[15] RSVD_TP_59 E15

AL17 VSS41 VSS121 V10 E18 VSS199 AJ30 CFG[16] RSVD_TP_60 F15
C AL12 U8 E13 AK30 A2 C
VSS42 VSS122 VSS200 CFG[17] KEY
AL9 VSS43 VSS123 U4 E11 VSS201 H16 RSVD_TP_86 RSVD62 D15
AL6 VSS44 VSS124 U2 E8 VSS202 RSVD63 C15
AL3 VSS45 VSS125 T35 E5 VSS203 RSVD64 AJ15 TP8
AK29 VSS46 VSS126 T34 E2 VSS204 VSS_NCTF1 AT35 RSVD65 AH15 TP9
AK27 VSS47 VSS127 T33 D33 VSS205 VSS_NCTF2 AT1
AK25 VSS48 VSS128 T32 D30 VSS206 VSS_NCTF3 AR34 TP20 B19 RSVD15
AK20 VSS49 VSS129 T31 D26 VSS207 VSS_NCTF4 B34 TP22 A19 RSVD16
AK17 T30 D9 B2 TP34
NCTF
VSS50 VSS130 VSS208 VSS_NCTF5
AJ31 VSS51 VSS131 T29 D6 VSS209 VSS_NCTF6 B1 TP25 A20 RSVD17
AJ23 VSS52 VSS132 T28 D3 VSS210 VSS_NCTF7 A35 TP26 B20 RSVD18
AJ20 VSS53 VSS133 T27 C34 VSS211 RSVD_TP_66 AA5
AJ17 VSS54 VSS134 T26 C32 VSS212 U9 RSVD19 RSVD_TP_67 AA4
AJ14 VSS55 VSS135 T6 C29 VSS213 T9 RSVD20 RSVD_TP_68 R8
AJ11 VSS56 VSS136 R10 C28 VSS214 RSVD_TP_69 AD3
AJ8 VSS57 VSS137 P8 C24 VSS215 AC9 RSVD21 RSVD_TP_70 AD2
AJ5 VSS58 VSS138 P4 C22 VSS216 AB9 RSVD22 RSVD_TP_71 AA2
AJ2 VSS59 VSS139 P2 C20 VSS217 RSVD_TP_72 AA1
AH35 VSS60 VSS140 N35 C19 VSS218 RSVD_TP_73 R9
AH34 VSS61 VSS141 N34 C16 VSS219 RSVD_TP_74 AG7
AH33 VSS62 VSS142 N33 B31 VSS220 C1 RSVD_NCTF_23 RSVD_TP_75 AE3
AH32 VSS63 VSS143 N32 B25 VSS221 A3 RSVD_NCTF_24
AH31 VSS64 VSS144 N31 B21 VSS222
AH30 VSS65 VSS145 N30 B18 VSS223 RSVD_TP_76 V4
AH29 VSS66 VSS146 N29 B17 VSS224 RSVD_TP_77 V5
AH28 VSS67 VSS147 N28 B13 VSS225 RSVD_TP_78 N2
AH27 VSS68 VSS148 N27 B11 VSS226 J29 RSVD26 RSVD_TP_79 AD5
AH26 VSS69 VSS149 N26 B8 VSS227 J28 RSVD27 RSVD_TP_80 AD7
AH20 VSS70 VSS150 N6 B6 VSS228 RSVD_TP_81 W3
AH17 VSS71 VSS151 M10 B4 VSS229 A34 RSVD_NCTF_28 RSVD_TP_82 W2
AH13 VSS72 VSS152 L35 A29 VSS230 A33 RSVD_NCTF_29 RSVD_TP_83 N3
B B
AH9 VSS73 VSS153 L32 A27 VSS231 RSVD_TP_84 AE5
AH6 VSS74 VSS154 L29 A23 VSS232 C35 RSVD_NCTF_30 RSVD_TP_85 AD9
AH3 VSS75 VSS155 L8 A9 VSS233 B35 RSVD_NCTF_31
AG10 VSS76 VSS156 L5
AF8 VSS77 VSS157 L2 VSS AP34 TP19
AF4 VSS78 VSS158 K34
AF2 K33 AP34 can be NC on CRB; EDS/DG suggestion to GND
VSS79 VSS159
AE35 VSS80 VSS160 K30
Clarksfield/Auburndale Clarksfield/Auburndale
Processor Strapping
1 0 DEFAULT
CFG0 CFG0 R128 *3.01K_NC
(PCI-Epress Single PEG Bifurcation enabled 1
Configuration Select)
CFG3
(PCI-Epress Static Normal Operation Lane Numbers Reversed CFG3 R125
1 3.01K/F_4
Lane Reversal)
A CFG4 Enabled; An external Display port A
(Embended Disabled; No Physical Display Port device is connected to the Embedded CFG4 R127
1 *3.01K
Display Port Presence) attached to Embedded Diplay Port Display port
Ts
hI
CFG7 R126 *3.01K/F_4

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PROJECT : ZR7B
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Co

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1A
AUBURNDA 4/4
l
f
ap
www.vinafix.vn
B
5 4 3 2 1
i
roG
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c
knA
e
5 4 3 2 1
IBEX PEAK-M (DMI,FDI,GPIO) AC-coupling CAP place close to PCH
0-ohm resistor place close to PCH IBEX PEAK-M (LVDS,DDI)

U21C
BA18 FDI_TXN0_R R454 IV@0_4
FDI_RXN0 FDI_TXN0 <4>
BC24 BH17 FDI_TXN1_R R470 IV@0_4 U21D
<4> DMI_RXN0 DMI0RXN FDI_RXN1 FDI_TXN1 <4>
BJ22 BD16 FDI_TXN2_R R481 IV@0_4 T48 BJ46
<4> DMI_RXN1 DMI1RXN FDI_RXN2 FDI_TXN2 <4> <23> INT_LVDS_BLON L_BKLTEN SDVO_TVCLKINN
D AW20 BJ16 FDI_TXN3_R R487 IV@0_4 T47 BG46 D
<4> DMI_RXN2 DMI2RXN FDI_RXN3 FDI_TXN3 <4> <23> INT_LVDS_DIGON L_VDD_EN SDVO_TVCLKINP
BJ20 BA16 FDI_TXN4_R R464 IV@0_4
<4> DMI_RXN3 DMI3RXN FDI_RXN4 FDI_TXN4 <4>
BE14 FDI_TXN5_R R480 IV@0_4 Y48 BJ48
FDI_RXN5 FDI_TXN5 <4> <23> INT_LVDS_BRIGHT L_BKLTCTL SDVO_STALLN
BD24 BA14 FDI_TXN6_R R500 IV@0_4 BG48
<4> DMI_RXP0 DMI0RXP FDI_RXN6 FDI_TXN6 <4> SDVO_STALLP
BG22 BC12 FDI_TXN7_R R495 IV@0_4 AB48
<4> DMI_RXP1 DMI1RXP FDI_RXN7 FDI_TXN7 <4> <23> INT_LVDS_EDIDCLK L_DDC_CLK
<4> DMI_RXP2 BA20 <23> INT_LVDS_EDIDDATA Y45 BF45
DMI2RXP FDI_TXP0_R R459 IV@0_4 L_DDC_DATA SDVO_INTN
<4> DMI_RXP3 BG20 BB18 FDI_TXP0 <4> BH45
DMI3RXP FDI_RXP0 FDI_TXP1_R R475 IV@0_4 R119 IV@10K_4 SDVO_INTP
BF17 FDI_TXP1 <4> +3V AB46
FDI_RXP1 FDI_TXP2_R R478 IV@0_4 R120 IV@10K_4 L_CTRL_CLK
<4> DMI_TXN0 BE22 BC16 FDI_TXP2 <4> V48
DMI0TXN FDI_RXP2 FDI_TXP3_R R491 IV@0_4 L_CTRL_DATA
<4> DMI_TXN1 BF21 BG16 FDI_TXP3 <4>
DMI1TXN FDI_RXP3 FDI_TXP4_R R461 IV@0_4 R144 IV@2.37K/F_4 AP39
<4> DMI_TXN2 BD20 AW16 FDI_TXP4 <4> T51 SDVO_CTRLCLK <24>
DMI2TXN FDI_RXP4 FDI_TXP5_R R484 IV@0_4 LVD_IBG SDVO_CTRLCLK
<4> DMI_TXN3 BE18 BD14 FDI_TXP5 <4> AP41 T53 SDVO_CTRLDAT <24>
DMI3TXN FDI_RXP5 FDI_TXP6_R R498 IV@0_4 LVD_VBG SDVO_CTRLDATA
BB14 FDI_TXP6 <4>
FDI_RXP6 FDI_TXP7_R R493 IV@0_4 R111 IV@0_4
<4> DMI_TXP0 BD22 BD12 FDI_TXP7 <4> AT43
DMI0TXP FDI_RXP7 R112 IV@0_4 LVD_VREFH
<4> DMI_TXP1 BH21 AT42 BG44
DMI1TXP LVD_VREFL DDPB_AUXN
<4> DMI_TXP2 BC20 BJ44
DMI2TXP DDPB_AUXP
<4> DMI_TXP3 BD18 BJ14 FDI_INT <4> AU38 INT_HDMI_HPD <24>
DMI3TXP FDI_INT DDPB_HPD
LVDS
<23> INT_TXLCLKOUT- INT_TXLCLKOUT- AV53
DMI
FDI
INT_TXLCLKOUT+ AV51 LVDSA_CLK# INT_HDMITX2N_R C249 IV@0.1u/10V_4_X7R
BF13 FDI_FSYNC0 <4> <23> INT_TXLCLKOUT+ BD42 INT_HDMITX2N <24>
FDI_FSYNC0 LVDSA_CLK DDPB_0N INT_HDMITX2P_R C247 IV@0.1u/10V_4_X7R
BH25 BC42 INT_HDMITX2P <24>
DMI_ZCOMP INT_TXLOUT0- DDPB_0P INT_HDMITX1N_R C242 IV@0.1u/10V_4_X7R
BH13 FDI_FSYNC1 <4> <23> INT_TXLOUT0- BB47 BJ42 INT_HDMITX1N <24>
R441 49.9/F_4 FDI_FSYNC1 INT_TXLOUT1- LVDSA_DATA#0 DDPB_1N INT_HDMITX1P_R C245 IV@0.1u/10V_4_X7R
BF25 BA52 BG42
Digital Display Interface

+1.05V DMI_IRCOMP <23> INT_TXLOUT1- LVDSA_DATA#1 DDPB_1P INT_HDMITX1P <24>
BJ12 INT_TXLOUT2- AY48 BB40 INT_HDMITX0N_R C253 IV@0.1u/10V_4_X7R
FDI_LSYNC0 FDI_LSYNC0 <4> <23> INT_TXLOUT2- LVDSA_DATA#2 DDPB_2N INT_HDMITX0N <24>
AV47 BA40 INT_HDMITX0P_R C250 IV@0.1u/10V_4_X7R
LVDSA_DATA#3 DDPB_2P INT_HDMITX0P <24>
BG14 AW38 INT_HDMICLK-_R C237 IV@0.1u/10V_4_X7R
FDI_LSYNC1 FDI_LSYNC1 <4> DDPB_3N INT_HDMICLK- <24>
<23> INT_TXLOUT0+ INT_TXLOUT0+ BB48 BA38 INT_HDMICLK+_R C241 IV@0.1u/10V_4_X7R
LVDSA_DATA0 DDPB_3P INT_HDMICLK+ <24>
<23> INT_TXLOUT1+ INT_TXLOUT1+ BA50
INT_TXLOUT2+ LVDSA_DATA1
C <23> INT_TXLOUT2+ AY49 C
LVDSA_DATA2
AV48 Y49
LVDSA_DATA3 DDPC_CTRLCLK
AB49
DDPC_CTRLDATA
AP48
XDP_DBRST# LVDSB_CLK#
<4> XDP_DBRST# T6 J12 PCIE_WAKE# <25,27> AP47 BE44
SYS_RESET# WAKE# LVDSB_CLK DDPC_AUXN
BD44
DDPC_AUXP
AY53 AV40
SYS_PWROK LVDSB_DATA#0 DDPC_HPD
M6 Y1 CLKRUN# <35> AT49
SYS_PWROK CLKRUN# / GPIO32 LVDSB_DATA#1
AU52 BE40
LVDSB_DATA#2 DDPC_0N
AT53 BD40
LVDSB_DATA#3 DDPC_0P
System Power Management
B17 BF41
PWROK DDPC_1N
AY51 BH41
LVDSB_DATA0 DDPC_1P
AT48 BD38
LVDSB_DATA1 DDPC_2N
K5 P8 AU50 BC38
MEPWROK SUS_STAT# / GPIO61 LVDSB_DATA2 DDPC_2P
AT51 BB36
LVDSB_DATA3 DDPC_3N
BA36
RSV_ICH_LAN_RST# A10 R234 *Short_4 DDPC_3P
F3 ICH_SUSCLK <35>
LAN_RST# SUSCLK / GPIO62
INT_CRT_BLU AA52 U50
<23> INT_CRT_BLU CRT_BLUE DDPD_CTRLCLK
D9 E4 INT_CRT_GRN AB53 U52
<4> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 <23> INT_CRT_GRN CRT_GREEN DDPD_CTRLDATA
INT_CRT_RED AD53
<23> INT_CRT_RED CRT_RED
<35> ICH_RSMRST# C16 H7 SUSC# <35> BC46

RSMRST# SLP_S4# DDPD_AUXN
<23> INT_CRT_DDCCLK V51
CRT_DDC_CLK DDPD_AUXP
BD46 R place close to PCH
<23> INT_CRT_DDCDAT V53 AT38
SUS_PWR_ACK_R CRT_DDC_DATA DDPD_HPD R425 IV@150_4 INT_CRT_BLU
M1 P12 SUSB# <35>
SUS_PWR_DN_ACK / GPIO30 SLP_S3#
B BJ40 B
DDPD_0N R426 IV@150_4 INT_CRT_GRN
<23> INT_HSYNC Y53 BG40
SLP_M# R225 *0_4 CRT_HSYNC DDPD_0P
<35> DNBSWON# P5 K8 <23> INT_VSYNC Y51 BJ38
PWRBTN# SLP_M# CRT_VSYNC DDPD_1N R427 IV@150_4 INT_CRT_RED
BG38
DDPD_1P
CRT
BF37
R246 *0_4 ACIN_R DAC_IREF DDPD_2N
<35> PCH_ACIN P7 N2 TP32 AD48 BH37
ACPRESENT / GPIO31 TP23 DAC_IREF DDPD_2P
AB51 BE36
CRT_IRTN DDPD_3N
BD36
PM_BATLOW# R134 DDPD_3P
A6 BJ10 PM_SYNC <4>
BATLOW# / GPIO72 PMSYNCH 1K/F_4 IbexPeak-M_R1P0
PM_RI# F14 F6 PM_SLP_LAN# TP18

RI# SLP_LAN# / GPIO29
IbexPeak-M_R1P0
PCH Pull-high/low +3V_S5

System PWR_OK
+3V
PM_RI# R184 10K_4

CLKRUN# R523 8.2K_4 +3V_S5
PM_BATLOW# R514 10K_4 DELAY_VR_PWRGOOD need PU 2K to +3V.
XDP_DBRST# R226 1K_4 C636 *.1u_4
A
PCIE_WAKE# R230 10K_4
PU at power side A
5
ICH_RSMRST# R482 10K_4 PM_SLP_LAN# R248 *10K_4 1 DELAY_VR_PWRGOOD <4,38>
SYS_PWROK 4
RSV_ICH_LAN_RST# R499 10K_4 SUS_PWR_ACK_R R530 10K_4 2
U24
PWROK_EC <35>
3
SYS_PWROK R477 10K_4 ACIN_R R227 10K_4 R538 100K_4
TC7SH08FU
PROJECT : ZQ9
1A
IBEX PEAK-M 1/6
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
RTC Circuitry C335

15p/50V_4
2
1
+VCCRTC
CR1 Y1
R195
+3VPCU U21A
R483 20K/F_4 RTC_RST# 32.768KHZ 10M_4
VCCRTC_1
3
4
C328
1
RTC_X1 B13 D33
RTCX1 FWH0 / LAD0 LPC_LAD0 <27,35>
BAT54C C662 J2 15p/50V_4 RTC_X2 D13 B33
RTCX2 FWH1 / LAD1 LPC_LAD1 <27,35>
R473 1u/10V_4 *SHORT_ PAD1 C32
FWH2 / LAD2 LPC_LAD2 <27,35>
1K_4 A32 LPC_LAD3 <27,35>
2
RTC_RST# FWH3 / LAD3
C14
RTCRST#
C34 LPC_LFRAME# <27,35>
SRTC_RST# FWH4 / LFRAME#
BT1 D17
D
R474 20K/F_4 SRTC_RST# SRTCRST# D
1 A34
RTC
LPC
1 R479 1M_4 SM_INTRUDER# LDRQ0#
2 +VCCRTC A16 F34
2 INTRUDER# LDRQ1# / GPIO23
1
R222 10K_4 +3V
RTC_CONN C663 C650 J1 PCH_INVRMEN A14 AB9
INTVRMEN SERIRQ IRQ_SERIRQ <35>
1u/10V_4 1u/10V_4 *SHORT_ PAD1
2
HDA_SYNC (PCH strap pin) ACZ_BIT_CLK A30
HDA_BCLK SATA_RXN0_C
AK7 SATA_RXN0_C <28>
ACZ_SYNC SATA0RXN SATA_RXP0_C
Internal weak pull-down D29 AK6 SATA_RXP0_C <28>
HDA_SYNC SATA0RXP
VCCVRM=>+1.8V (default) AK11 SATA_TXN0 <28>
SPKR SATA0TXN
external pull-up <29> SPKR P1 AK9 SATA_TXP0 <28>
SPKR SATA0TXP
VCCVRM=>+1.5V ACZ_RST# C30
HDA_RST# SATA_RXN1_C
AH6 SATA_RXN1_C <28>
SATA1RXN SATA_RXP1_C
AH5 SATA_RXP1_C <28>
SATA1RXP
<29> PCH_AZ_CODEC_SDIN0 G30 AH9 SATA_TXN1 <28>
HDA_SDIN0 SATA1TXN
AH8 SATA_TXP1 <28>
SATA1TXP
F30
HDA_SDIN1
AF11
SATA2RXN
E32 AF9
IHDA
HDA_SDIN2 SATA2RXP
AF7
SATA2TXN
F32
HDA_SDIN3 SATA2TXP
AF6 Note:
SATA port2/3 may not be available on all PCH sku
AH3
ACZ_SDOUT B29
SATA3RXN
AH1
(HM55 support 3 port only)
HDA_SDO SATA3RXP
AF3
SATA3TXN
AF1
PCH_GPIO33 SATA3TXP
H32
SATA
HDA_DOCK_EN# / GPIO33
AD9
R460 *10K_4 PCH_GPIO13 SATA4RXN
+3V_S5 J30 AD8
HDA_DOCK_RST# / GPIO13 SATA4RXP
AD6
SATA4TXN
AD5
HDA Bus <24> HDMI_HPD_PCH#
SATA4TXP
M3 AD3
JTAG_TCK SATA5RXN
AD1
SATA5RXP
K3 AB3
R453 33_4 ACZ_SYNC JTAG_TMS SATA5TXN
C
<29> PCH_AZ_CODEC_SYNC AB1 C
SATA5TXP
K1
JTAG_TDI
JTAG
R449 33_4 ACZ_RST# J2 AF16
<29> PCH_AZ_CODEC_RST# JTAG_TDO SATAICOMPO
J4 AF15 R182 37.4/F_4 +1.05V
R456 33_4 ACZ_SDOUT TRST# SATAICOMPI
<29> PCH_AZ_CODEC_SDOUT
SPI_CLK_R BA2
SPI_CLK
R450 33_4 ACZ_BIT_CLK SPI_CS0#_R AV3
<29> PCH_AZ_CODEC_BITCLK SPI_CS0# SATA_ACT# <32>
+3VPCU R525 *10K_4 SPI_CS1# AY3 T3

C628 SPI_CS1# SATALED# TP13
*27p_4
SPI_SI_R AY1 Y9 R240 43K/F_4 +3V
SPI_MOSI SATA0GP / GPIO21
SPI
SPI_SO_R AV1 V1 R521 43K/F_4 +3V
SPI_MISO SATA1GP / GPIO19
IbexPeak-M_R1P0
PCH Strap Pin Configuration Table-1

INTVRMEN Integrated 1.05V VRM Enable / 1 = Integrated VRM is enabled
R489 330K_6 PCH_INVRMEN
Disable 0 = Integrated VRM is disabled +VCCRTC
SPI_MOSI TPM Functionality 1 = Enabled

Disable R540 *1K_4 SPI_SI_R
0 = Disable +3V
PCH SPI
SPKR Reboot option at power-up 0 = Default Mode (Internal weak Pull-down)
R532 *1K/F_4 SPKR
1 = No Reboot Mode with TCO Disabled +3V
B 0 = Flash Descriptor Security will be overridden B

HDA_DOCK_EN Flash Descriptor 1 = Security measure defined in the Flash
PCH_GPIO33 R164 *1K/F_4
#/GPIO33 Security Override Descriptor will be enabled.
R145 *10K_4 +3V
+3V
U25
SPI_CS0#_R 1 8 R129 1K_4 +3V
SPI_CLK_R CE# VDD R122 1K_4
6
SCK GNT0#, (0,0) = LPC (0,1) = Reserved NAND
SPI_SI_R 5 Boot BIOS Strap R123 *1K_4
SPI_SO_R 2
SI
7 R539 3.3K/F_4 GNT1# (1,0) = PCI (1,1) = SPI <10> PCI_GNT0#
R131 *1K_4
SO HOLD# <10> PCI_GNT1#
3
WP# VSS
4 GNT2#/ ESI compatible mode is for server
C671 ESI Strap
W25Q32BVSSIG .1u/10V_4 GPIO53 platforms only R158 *1K/F_4
(Server Only) <10> PWM_SELECT#
GNT3#/ Top-Block 0 = Top Block Swap Mode

R541 3.3K/F_4 R421 *10K/F_4
+3V
GPIO55 Swap Override 1 = Default Mode (Internal pull-up) <10> PCI_GNT3#
IntelR Anti-Theft Technology

HDD Data Protection 1 = Enabled
NV_ALE R202 *1K/F_4
(Intel AT-d) Enable 0 = Disabled (Default) <10> NV_ALE +1.8V
NV_CLE DMI Termination DMI termination voltage. Weak

R206 *1K/F_4
Voltage internal pull-up. Do not pull low. <10> NV_CLE +1.8V
GPIO8 Reserved This signal has a weak internal pull up.

R204 10K_4
NOTE: This signal should not be pulled low<11> RSV_GPIO8 +3V_S5
R203 *1K_4
0 = Intel ME Crypto Transport Layer Security

(TLS) cipher suite with no confidentiality
GPIO15 Reserved
A 1 = Intel ME Crypto Transport Layer Security<11> CR_WAKE# R244 1K_4 +3V_S5 A
(TLS) cipher suite with confidentiality
GPIO27 On-Die PLL Voltage 0 = Disables the VccVRM.

Regulator 1 = Enables the internal VccVRM to have
<internal weak pull-up> a clean supply for analog rails. <11> PCH_GPIO27 R221 *10K_4

PROJECT : ZQ9
www.vinafix.vn
1A
IBEX PEAK-M 2/6
5 4 3 2 1
5 4 3 2 1
U21B
U21E
H40 AY9 BG30 B9 RSV_SMBALERT#
AD0 NV_CE#0 <25> PCIE_RX1- PERN1 SMBALERT# / GPIO11
N34 BD1 <25> PCIE_RX1+ BJ30
AD1 NV_CE#1 C615 0.1u/10V_4_X7R PCIE_TXN1_C PERP1 ICH_SMBCLK
C44 AP15 Wireless <25> PCIE_TX1- BF29 H14 ICH_SMBCLK <3>
AD2 NV_CE#2 C616 0.1u/10V_4_X7R PCIE_TXP1_C PETN1 SMBCLK
A38 BD8 <25> PCIE_TX1+ BH29
AD3 NV_CE#3 PETP1 ICH_SMBDATA
C36 C8 ICH_SMBDATA <3>
AD4 SMBDATA
J34 AV9 AW30
AD5 NV_DQS0 PERN2
A40 BG8 BA30
AD6 NV_DQS1 PERP2 RSV_SML0ALERT#
D45 BC30 J14
D AD7 PETN2 SML0ALERT# / GPIO60 D
E36 AP7 BD30
AD8 NV_DQ0 / NV_IO0 PETP2 SMB_CLK_ME0
H48 AP6 C6
AD9 NV_DQ1 / NV_IO1 SML0CLK
E40 AT6 AU30
SMBus
AD10 NV_DQ2 / NV_IO2 PERN3 SMB_DATA_ME0
C40 AT9 AT30 G8
AD11 NV_DQ3 / NV_IO3 PERP3 SML0DATA
M48 BB1 AU32
AD12 NV_DQ4 / NV_IO4 PETN3
M45 AV6 AV32
AD13 NV_DQ5 / NV_IO5 PETP3 RSV_SML1ALERT# R242 *0_4
F53 BB3 M14 SML1ALERT# <11,34,35>
AD14 NV_DQ6 / NV_IO6 SML1ALERT# / GPIO74
M40 BA4 BA32
AD15 NV_DQ7 / NV_IO7 PERN4 SMB_CLK_ME1
NVRAM
M43 BE4 BB32 E10
AD16 NV_DQ8 / NV_IO8 PERP4 SML1CLK / GPIO58
J36 BB6 BD32
AD17 NV_DQ9 / NV_IO9 PETN4 SMB_DATA_ME1
K48 BD6 BE32 G12
AD18 NV_DQ10 / NV_IO10 PETP4 SML1DATA / GPIO75
F40 BB7
PCI-E*
AD19 NV_DQ11 / NV_IO11
C42 BC8 BF33
AD20 NV_DQ12 / NV_IO12 PERN5 CL_CLK1
K46 BJ8 BH33 T13 CL_CLK1 <27>
AD21 NV_DQ13 / NV_IO13 PERP5 CL_CLK1
Controller
M51 BJ6 BG32
AD22 NV_DQ14 / NV_IO14 PETN5 CL_DATA1
J52 BG6 BJ32 T11 CL_DATA1 <27>
AD23 NV_DQ15 / NV_IO15 PETP5 CL_DATA1
K51
Link
AD24 NV_ALE CL_RST1#
L34 BD3 NV_ALE <9> <27> PCIE_RX6- BA34 T9 CL_RST1# <27>
AD25 NV_ALE NV_CLE PERN6 CL_RST1#
F42 AY6 NV_CLE <9> <27> PCIE_RX6+ AW34
AD26 NV_CLE C259 0.1u/10V_4_X7R PCIE_TXN6_C PERP6
J40 LAN <27> PCIE_TX6- BC34
AD27 C268 0.1u/10V_4_X7R PCIE_TXP6_C PETN6 5/25 add net
G46 <27> PCIE_TX6+ BD34
AD28 PETP6
F44 AU2 NV_RCOMP R508 *32.4/F_4 H1 PEG_CLKREQ#_R
AD29 NV_RCOMP PEG_A_CLKRQ# / GPIO47
M47 AT34
AD30 PERN7
PCI
H36 AV7 AU34
AD31 NV_RB# PERP7
AU36 AD43 CLK_PCIE_VGA# <16>
PETN7 CLKOUT_PEG_A_N
J50 AY8 AV36 AD45 CLK_PCIE_VGA <16>
C/BE0# NV_WR#0_RE# PETP7 CLKOUT_PEG_A_P
G42 AY5
C/BE1# NV_WR#1_RE#
H47 BG34 AN4 CLK_PCIE_3GPLL# <4>
C/BE2# PERN8 CLKOUT_DMI_N
PEG
G34 AV11 BJ34 AN2 CLK_PCIE_3GPLL <4>
C/BE3# NV_WE#_CK0 PERP8 CLKOUT_DMI_P
BF5 BG36
PCI_PIRQA# NV_WE#_CK1 PETN8
G38 BJ36
PCI_PIRQB# PIRQA# PETP8
H51 AT1 DPLL_REF_SSCLK# <4>
PCI_PIRQC# PIRQB# CLKOUT_DP_N / CLKOUT_BCLK1_N
B37
PIRQC# USBP0N
H18 Port1 and port9 can be used on debug mode CLKOUT_DP_P / CLKOUT_BCLK1_P
AT3 DPLL_REF_SSCLK <4>
PCI_PIRQD# A44 J18 AK48
PIRQD# USBP0P CLKOUT_PCIE0N
A18 USBP1- <33> AK47
USBP1N CLKOUT_PCIE0P
From CLK BUFFER

PCI_REQ0# F51 C18 MB USB AW24
C PCI_REQ1# REQ0# USBP1P USBP1+ <33> CLK_PCIE_REQ0# CLKIN_DMI_N CLK_BUF_PCIE_3GPLL# <3> C
A46 N20 P9 BA24 CLK_BUF_PCIE_3GPLL <3>
dGPU_SELECT# REQ1# / GPIO50 USBP2N PCIECLKRQ0# / GPIO73 CLKIN_DMI_P
TP1 B45 P20
PCI_REQ3# REQ2# / GPIO52 USBP2P
M53 J20
REQ3# / GPIO54 USBP3N
TP3 L20 AM43 AP3 CLK_BUF_BCLK# <3>
PCI_GNT0# USBP3P CLKOUT_PCIE1N CLKIN_BCLK_N
<9> PCI_GNT0# F48
GNT0# USBP4N
F20 USBP4- <33> EHCI1 AM45
CLKOUT_PCIE1P CLKIN_BCLK_P
AP1 CLK_BUF_BCLK <3>
PCI_GNT1# K45 G20 BLUETOOTH 3.0
<9> PCI_GNT1# PWM_SELECT# GNT1# / GPIO51 USBP4P USBP4+ <33> CLK_PCIE_REQ1#_R
<9> PWM_SELECT# F36 A20 TP29 U4
PCI_GNT3# GNT2# / GPIO53 USBP5N PCIECLKRQ1# / GPIO18
<9> PCI_GNT3# H53 C20 TP30 F18 CLK_BUF_DREFCLK# <3>
GNT3# / GPIO55 USBP5P CLKIN_DOT_96N
M22 E18 CLK_BUF_DREFCLK <3>
PCI_PIRQE# USBP6N USB port6/7 may not be available on all PCH sku CLKIN_DOT_96P
B41 N22 <27> CLK_PCH_SRC2# AM47
PCI_PIRQF# PIRQE# / GPIO2 USBP6P CLKOUT_PCIE2N
K53 B21 (HM55 support 12port only) <27> CLK_PCH_SRC2 AM48
PCI_PIRQG# PIRQF# / GPIO3 USBP7N CLKOUT_PCIE2P
A36 D21 AH13 CLK_BUF_DREFSSCLK# <3>
PCI_PIRQH# PIRQG# / GPIO4 USBP7P R531 *Short_4 CLK_PCIE_REQ2#_R CLKIN_SATA_N / CKSSCD_N
A48 H22 USBP8- <23> <27> PCIE_CLK_REQ2# N4 AH12 CLK_BUF_DREFSSCLK <3>
PIRQH# / GPIO5 USBP8N PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P
USBP8P
J22 USBP8+ <23> Camera
USB
PCI_RST# K6 E22
<27> PCI_RST# PCIRST# USBP9N USBP9- <33>
USBP9P
F22 USBP9+ <33> USB/B-USB1-2 AH42
CLKOUT_PCIE3N REFCLK14IN
P41 CLK_ICH_14M <3>
PCI_SERR# E44 A22 AH41
SERR# USBP10N TP28 CLKOUT_PCIE3P
PCI_PERR# E50 C22 C600 18p/50V_4
PERR# USBP10P TP27
G24 EHCI2 CLK_PCIE_REQ3# A8 J42 CLK_PCI_FB
USBP11N USBP11- <33> PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK
USBP11P
H24 USBP11+ <33> USB/B-USB1-1
1
PCI_IRDY# A42 L24
IRDY# USBP12N USBP12- <31> XTAL25_IN R428 Y5
PCI_DEVSEL#
H44
PAR USBP12P
M24 USBP12+ <31> Card Reader AM51
CLKOUT_PCIE4N XTAL25_IN
AH51
XTAL25_OUT
F46 A24 AM53 AH53 1M_4 25MHz
PCI_FRAME# DEVSEL# USBP13N USBP13- <27,33> CLKOUT_PCIE4P XTAL25_OUT
C46 C24 <27,33>Mini Card (WLAN & BT 2.0)
2
FRAME# USBP13P USBP13+ CLK_PCIE_REQ4# M9 AF38 XCLK_RCOMP R141 90.9/F_4 +1.05V C599 18p/50V_4
PCI_PLOCK# PCIECLKRQ4# / GPIO26 XCLK_RCOMP
D49
PLOCK#
B25 USB_BIAS R466 22.6/F_4
PCI_STOP# USBRBIAS# BOARD_ID1
D41 AJ50 T45
PCI_TRDY# STOP# CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64
C48 D25 AJ52
TRDY# USBRBIAS TP4 CLKOUT_PCIE5P
ICH_PME# M7 CLK_PCIE_REQ5# H6 P43 BOARD_ID2
Clock Flex
TP15 PME# PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65
N16 USB_OC0#
PCI_PLTRST# OC0# / GPIO59 USB_OC1# USB_OC0# <33>
D5 J16 TP5
PLTRST# OC1# / GPIO40 USB_OC2# BOARD_ID3
F16 TP11 <25> CLK_PCIE_LOM# AK53 T42
R423 22_4 CLK_LPC_DEBUG_C OC2# / GPIO41 USB_OC3# CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66
<27> CLK_LPC_DEBUG N52 L16 TP10 <25> CLK_PCIE_LOM AK51
TP21 CLK_PCI_PCCARD CLKOUT_PCI0 OC3# / GPIO42 USB_OC4_5# CLKOUT_PEG_B_P
P53 E14 USB_OC4_5# <33>
B CLK_PCI_775_C CLKOUT_PCI1 OC4# / GPIO43 PCIE_CLK_REQB# B
<35> CLK_PCI_775
R105 22_4 P46 G16 <25> CLK_PCIE_LAN_REQ# R233 *Short_4 P13 N50 dGPU_EDIDSEL# R121 *10K_4 +3V
CLK_PCI_FB R117 22_4 CLK_PCI_FB_C CLKOUT_PCI2 OC5# / GPIO9 USB_OC6# PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67
P51 F12 TP6
CLKOUT_PCI3 OC6# / GPIO10 USB_OC7#
P48 T15 TP7
CLKOUT_PCI4 OC7# / GPIO14 IbexPeak-M_R1P0
IbexPeak-M_R1P0
6/9 set for board ID

+3V +3V_S5
+3V_S5
+3V_S5 R406 *10K_4 BOARD_ID1 R132 10K_4
RP2 R245 10K_4 CLK_PCIE_REQ0#
USB_OC3# 6 5 R513 10K_4 CLK_PCIE_REQ3# R407 10K_4 BOARD_ID2 R136 *10K_4 R180
USB_OC2# 7 4 USB_OC1# R229 10K_4 CLK_PCIE_REQ4#
2
USB_OC4_5# 8 3 USB_OC0# R247 10K_4 CLK_PCIE_REQ5# R408 *10K_4 BOARD_ID3 R414 10K_4 2.2K_4
9 2 USB_OC6# R232 10K_4 PCIE_CLK_REQB#
+3V_S5 10 1 USB_OC7# R517 IV@10K_4 PEG_CLKREQ#_R 1 3 SMB_CLK_ME1
+3V_S5 <35> 2ND_MBCLK
Q4
8.2K_10P8R +3V 2N7002K
C353 R534 10K_4 CLK_PCIE_REQ1#_R +3V_S5

+3V BOARD_ID1 Not Defined
.1u/10V_4 RP4 +3V
PCI_PIRQD# 6 5
5
PCI_REQ1# 7 4 PCI_REQ3# High = 80port output to LPC

PCI_PLTRST# 2 PCI_FRAME# 8 3 PCI_PIRQB# BOARD_ID2 R181
4 PCI_TRDY# 9 2 PCI_REQ0# R138 10K_4 dGPU_SELECT# Low = 80port output to PCI
PLTRST# <4,11,25,27,31,35>
2
1 10 1 PCI_PIRQH# R139 8.2K_4 PCI_PIRQE# 2.2K_4
A
+3V A
R422 8.2K_4 PCI_PIRQF# High = Reserved
U7 R251 8.2K_10P8R R143 8.2K_4 PCI_PIRQG# BOARD_ID3 1 3 SMB_DATA_ME1
3
CLK_PCIE_REQ2#_R <35> 2ND_MBDATA

TC7SH08FU R518 10K_4 Low = Reserved (Default) Q5
100K_4 2N7002K
+3V R529 EV@10K/F_4 PEG_CLKREQ#_R
RP1
PCI_PIRQC# 6 5
R249 *0_4 PCI_PIRQA# 7 4 PCI_DEVSEL#
PCI_STOP# 8 3 PCI_PLOCK# +3V_S5
PCI_IRDY# 9 2 PCI_PERR#
+3V 10 1 PCI_SERR# R504
R211
10K_4
10K_4
RSV_SMBALERT#
RSV_SML0ALERT#
8.2K_10P8R R243 10K_4 RSV_SML1ALERT#
R512 2.2K_4 ICH_SMBCLK PROJECT : ZQ9
R511 2.2K_4 ICH_SMBDATA Size Document Number Rev
R214 2.2K_4 SMB_CLK_ME0 1A
R212 2.2K_4 SMB_DATA_ME0 IBEX PEAK-M 3/6
5 4 3 2 1
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5 4 3 2 1
GPU RST#
5/18 change for discrete only
D R73 EV@0_4 D
IBEX PEAK-M (GPIO,VSS_NCTF,RSVD)
U21F
+3V
TP31 BMBUSY# Y3 AH45 *EV@.1u_4
BMBUSY# / GPIO0 CLKOUT_PCIE6N C137
CLKOUT_PCIE6P AH46 <4,10,25,27,31,35> PLTRST#
<35> SIO_EXT_SMI# SIO_EXT_SMI# C38 GPU_RST# <16>
TACH1 / GPIO1
5
1
<35> SIO_EXT_SCI# SIO_EXT_SCI# D37 4
TACH2 / GPIO6
CLKOUT_PCIE7N AF48 2dGPU_HOLD_RST#
MISC
TP2 BOARD_ID0 J32 AF47
3
TACH3 / GPIO7 CLKOUT_PCIE7P U3
RSV_GPIO8 F10 *EV@TC7SH08FU R70
<9> RSV_GPIO8 GPIO8
*EV@100K_4
TP14 LAN_DISABLE# K9 U2
LAN_PHY_PWR_CTRL / GPIO12 A20GATE SIO_A20GATE <35>
CR_WAKE# T7
<9> CR_WAKE# GPIO15
dGPU_HOLD_RST# AA2 AM3
SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLK_CPU_BCLK# <4>
<19> dGPU_PWROK F38 TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P AM1 CLK_CPU_BCLK <4>
GPIO22 Y7 BG10
SCLOCK / GPIO22 PECI H_PECI <4>
GPIO
H10 T1
GPIO Pull-up/Pull-down
GPIO24 RCIN# SIO_RCIN# <35>
PCH_GPIO27 AB12 BE10
<9> PCH_GPIO27 GPIO27 PROCPWRGD H_PWRGOOD <4>
CPU
+3V_S5
TP_PCH_GPIO28 V13 BD10 PCH_THRMTRIP#_R R197 56/F_4
GPIO28 THRMTRIP# PM_THRMTRIP# <4>
C C
STP_PCI# M11 R200 56/F_4 +1.05V
STP_PCI# / GPIO34 TP_PCH_GPIO28 R239 10K_4
TP16
V6 GPIO45 R516 10K_4
<19,42> dGPU_VRON SATACLKREQ# / GPIO35 RST_GATE# R515 10K_4
TP17 dGPU_PWR_EN# AB7 BA22 GPIO57 R208 *10K_4
SATA2GP / GPIO36 TP1 LAN_DISABLE# R231 10K_4
TP12 dGPU_PRSNT# AB13 AW22
SATA3GP / GPIO37 TP2 +3V
dGPU_PWR_EN# should be stable GPIO38 V3 BB22
before dGPU_VRON enable SLOAD / GPIO38 TP3 SIO_EXT_SMI# R146 10K_4
SAVE_LED# P3 AY45 SIO_EXT_SCI# R445 10K_4
SDATAOUT0 / GPIO39 TP4 dGPU_PWR_EN# R223 10K_4
GPIO45 H3 AY46 dGPU_PWROK R154 *10K_4
PCIECLKRQ6# / GPIO45 TP5
TP33 RST_GATE# F1 AV43

PCIECLKRQ7# / GPIO46 TP6
SV_SET_UP AB6 AV45 +3V
SDATAOUT1 / GPIO48 TP7
<10,34,35> SML1ALERT# R524 *Short_4 SATA5GP AA4 AF13 SIO_RCIN# R533 10K_4
SATA5GP / GPIO49 TP8 SIO_A20GATE R520 10K_4
EC suggestion use GPIO49 for FAN control GPIO57 F8 M18 dGPU_HOLD_RST# R536 *10K_4
GPIO57 TP9 SATA5GP R537 10K_4
N18 GPIO22 R224 10K_4
TP10
A4 AJ24 SAVE_LED# R519 10K_4
VSS_NCTF_1 TP11 STP_PCI# R228 10K_4
A49
NCTF
VSS_NCTF_2
RSVD
SATA5GP / GPIO49 / TEMP_ALERT# is used to A5

VSS_NCTF_3 TP12
AK41
A50 GPIO38 R535 10K_4
alert for EC when CPU or Graph/Memory A52
VSS_NCTF_4
AK42
VSS_NCTF_5 TP13
B
controllers' temperature go out of limit. A53
VSS_NCTF_6
BMBUSY# R522 8.2K_4
B
So connecting GPIO49 to EC and avoid this B2 M32
VSS_NCTF_7 TP14 SV_SET_UP R241 10K_4
B4
pin to be used for other purpose VSS_NCTF_8
B52 N32
VSS_NCTF_9 TP15
B53 VSS_NCTF_10
BE1 M30 SV_SET_UP 1-X High = Strong (Default)
VSS_NCTF_11 TP16
BE53
VSS_NCTF_12
BF1 VSS_NCTF_13 TP17 N30
BF53
VSS_NCTF_14 GPIO57 stuff PD and not stuff PU for Intel suggestion at 6/1
BH1 H12
VSS_NCTF_15 TP18
BH2
VSS_NCTF_16 GPIO57 R207 10K_4
BH52 VSS_NCTF_17 TP19 AA23
BH53 VSS_NCTF_18
BJ1 AB45
VSS_NCTF_19 NC_1
BJ2
VSS_NCTF_20
BJ4 VSS_NCTF_21 NC_2 AB38
BJ49
VSS_NCTF_22 R148 *10K_4 BOARD_ID0 R155 10K_4
BJ5 VSS_NCTF_23 NC_3 AB42 +3V
BJ50 VSS_NCTF_24
BJ52 AB41 R238 IV@10K_4dGPU_PRSNT# R220 EV@10K_4
VSS_NCTF_25 NC_4
BJ53 VSS_NCTF_26
D1 T39 dGPU always exist
VSS_NCTF_27 NC_5
D2
VSS_NCTF_28 5/18 separate for 14" & 15"
D53
VSS_NCTF_29
E1 P6
VSS_NCTF_30 INIT3_3V# High = 15"
E53
VSS_NCTF_31 BOARD_ID0
C10
TP24
Low = 14"
IbexPeak-M_R1P0
High = Disable
RSV_GPIO8
A Low = Enable A

PROJECT : ZQ9
www.vinafix.vn
1A
IBEX PEAK-M 4/6
5 4 3 2 1
5 4 3 2 1
3.3 V. This rail should be powered up during S0 system state.
IBEX PEAK-M (POWER) U21G POWER VCCADAC= 69mA(15mils)
Note that Thermal Sensor shares the same power supply rail with DAC.
The external filters on this pin are not needed in case internal graphic is
R116 *SHORT0805 +1.05V_VCCCORE_ICH AB24 AE50 +VCCA_DAC_1_2 L44 disabled so only 3.3-V connection is required.
+1.05V VCCCORE[1] VCCADAC[1] +3V
AB26 PBY160808T/2A/180ohm_6
R124 *SHORT0805 VCCCORE[2] 6/14 change the P/N
AB28 AE52
C291 C283 VCCCORE[3] VCCADAC[2] C604 C572 C598
AD26
VCCCORE[4]
CRT
AD28 AF53
10u/6.3V_8 1u/6.3V_4 AF26
VCCCORE[5]
VCCCORE[6]
VSSA_DAC[1] IV@.01u/25V_4 IV@10u/10V_6 IV@0.1u/10V_4_X7R U21J POWER VCCIO = 3.208A(150mils)
VCC CORE
AF28
VCCCORE[7] VSSA_DAC[2]
AF51 VCCACLK= 52mA(15mils)
AF30 VCCALVDS= 1mA +1.05V L47 *10uh_8 +V1.1LAN_VCCA_CLK AP51 V24 +1.05V
VCCCORE[8] C597 *10u/6.3V_6 VCCACLK[1] VCCIO[5]
AF31 V26
VCCCORE[9] VCCALVDS R114 IV@0_4 C603 *1u/6.3V_4 VCCIO[6] C295 1U/6.3V_4
AH26 +3V AP53 Y24
VCCCORE[10] VCCACLK[2] VCCIO[7]
VCCCORE(+1.05V) = 1.432A(80mils) AH28 Y26
VCCCORE[11] R118 VCCIO[8]
AH30
VCCCORE[12]
VCCLAN = 320mA(30mils)
AH31 AH38 +1.05V R175 *0_6 +1.05V_VCCAUX AF23 V28 +3V_S5_VCCPUSB R162 *SHORT0805 +3V_S5
D VCCCORE[13] VCCALVDS EV@0_4 VCCLAN[1] VCCSUS3_3[1] D
AJ30 U28
VCCCORE[14] VCCSUS3_3[2] C303 0.1u/10V_4_X7R
AJ31 AH39 AF24 U26
VCCCORE[15] VSSA_LVDS VCCLAN[2] VCCSUS3_3[3] C290 0.1u/10V_4_X7R
U24
SP@ C300 VCCSUS3_3[4] C302 0.022U/16V_4
VCCTX_LVDS= 59mA(15mils) VCCSUS3_3[5]
P28
AP43 UMA=CH31004KB17<0.01u> 1U/6.3V_4 TP_PCH_VCCDSW Y20 P26
VCCTX_LVDS[1] MXM=CS00002JB38<0_ohm> VCCTX_LVDS L24 IV@0.1UH_8/250mA DCPSUSBYP VCCSUS3_3[6]
AP45 +1.8V N28
VCCTX_LVDS[2] VCCSUS3_3[7]
AT46 N26
LVDS
R174 *SHORT0603 +1.05V_PCH_VCCDPLL_EXP VCCTX_LVDS[3] C256 C255 C248 C307 VCCSUS3_3[8]
+1.05V AK24 AT45 AD38 M28
VCCIO[24] VCCTX_LVDS[4] C482 change to 0 ohm resistor. VCCME[1] VCCSUS3_3[9]
1u/6.3V_4 M26
SP@.01u/25V_4 IV@.01u/25V_4 IV@22u/6.3V_8 VCCSUS3_3[10]
AD39 L28
VCCSUS3_3 = 0.163A(20mils)
USB
L49 *1uh_6 +V1.1LAN_VCCAPLL_EXP VCCME[2] VCCSUS3_3[11]
40mA(15mils) +1.05V BJ24 L26
VCCAPLLEXP VCCSUS3_3[12]
AB34 AD41 J28
C629 *10u/6.3V_6 VCC3_3[2] VCCME[3] VCCSUS3_3[13]
J26
VCCSUS3_3[14] R172 *SHORT0603
AN20
VCCIO[25] VCC3_3[3]
AB35 VCC3_3 = 357mA(30mils) AF43
VCCME[4] VCCSUS3_3[15]
H28 +1.05V
AN22 H26
HVCMOS
VCCIO[26] +3V_VCC_GIO R417 *SHORT0603 VCCSUS3_3[16]
AN23 AD35 VCCME(+1.05V) = 1.849A(100mils) AF41 G28
AN24
VCCIO[27]
VCCIO[28]
VCC3_3[4] +3V VCCME[5] VCCSUS3_3[17]
VCCSUS3_3[18]
G26 V5REF_SUS< 1mA
AN26 C279 +1.05V R140 *SHORT0805 +1.05V_VCCEPW AF42 F28 R468 100/F_4 +5V_S5
VCCIO[29] VCCME[6] VCCSUS3_3[19]
VCCIO = 3.062A(150mils) AN28
VCCIO[30] VCCSUS3_3[20]
F26
+1.05V BJ26 .1u/16V_4 R150 0_8 V39 E28 D17 RB500V-40 +3V_S5
Clock and Miscellaneous

BJ28 E26
VCCIO[32] VCCSUS3_3[22] C639 1U/6.3V_4
AT26 V41 C28
AT28 C26
VCCIO[34] C257 22U/6.3V_8 VCCSUS3_3[24]
AU26 V42 B27
AU28
VCCIO[36]
VCCVRM= 196mA(15mils) VCCSUS3_3[26]
A28
C289 10U/6.3V_8 AV26 C269 22U/6.3V_8 Y39 A26
C292 1U/6.3V_4 VCCIO[37] +VCCVRM R178 *SHORT0603 VCCME[10] VCCSUS3_3[27]
AV28 AT24
C305 1U/6.3V_4 AW26
VCCIO[38]
VCCIO[39]
VCCVRM[2] +V1.5S_1.8S
C277 1U/6.3V_4 Y41
VCCME[11] VCCSUS3_3[28]
U23 V5REF< 1mA
C294 1U/6.3V_4 AW28 R115 100/F_4 +5V
VCCIO[40]
DMI
C282 1U/6.3V_4 BA26 AT16 +VCCDMI R194 *Short_4 +1.05V VCCDMI= 61mA(15mils) C278 1U/6.3V_4 Y42 V23
VCCIO[41] VCCDMI[1] VCCME[12] VCCIO[56] D4 RB500V-40
BA28 +3V
VCCIO[42] V5REF_SUS
BB26 AU16 F24
C VCCIO[43] VCCDMI[2] V5REF_SUS C240 1U/6.3V_4 C
BB28
VCCIO[44] +VCCRTCEXT
BC26 V9
VCCIO[45] DCPRTC
PCI E*
BC28 C324 C334 0.1u/10V_4_X7R
VCCIO[46] 1u/10V_4
BD26
VCCIO[47] V5REF
BD28 K49
VCCIO[48] V5REF
BE26 AM16 +V1.5S_1.8S AU24
PCI/GPIO/LPC
VCCIO[49] VCCPNAND[1] VCCVRM[3]
BE28
VCCIO[50] VCCPNAND[2]
AK16 VCCPNAND= 156mA(15mils)
BG26 AK20 J38 +3V_VCCPPCI R142 *SHORT0603 +3V
VCCIO[51] VCCPNAND[3] VCCPNAND R210 *SHORT0805 VCC3_3[8]
BG28 AK19 +1.8V BB51
VCCIO[52] VCCPNAND[4] +V1.1LAN_VCCA_A_DPL VCCADPLLA[1]
BH27
VCCIO[53] VCCPNAND[5]
AK15 68mA(15mils) BB53
VCCADPLLA[2] VCC3_3[9]
L38 VCC3_3 = 0.357A(30mils)
AK13 C319 C261 0.1u/10V_4_X7R
VCCPNAND[6]
AN30 AM12 M36
VCCIO[54] VCCPNAND[7] VCC3_3[10]
NAND / SPI
AN31 AM13 .1u/16V_4 69mA(15mils) +V1.1LAN_VCCA_B_DPL BD51
VCCIO[55] VCCPNAND[8] VCCADPLLB[1]
AM15 BD53 N36
VCCPNAND[9] VCCADPLLB[2] VCC3_3[11] C260 0.1u/10V_4_X7R
+3V R113 *SHORT0603 +3V_VCCA3GBG AN35 +1.05V AH23 P36
VCC3_3[1] VCCIO[21] VCC3_3[12]
AJ35
VCCIO[22]
37mA(15mils) VCCIO = 3.062A(150mils) AH35
VCCIO[23] VCC3_3[13]
U35
+V1.5S_1.8S R185 *SHORT0603 +VCCAFDI_VRM AT22
VCCVRM[1] C288 1U/6.3V_4
VCCME3_3= 85mA(15mils) AF34
VCCIO[2]
+1.05V L51 *1uH_6 +V1.1LAN_VCCAPLL_FDI BJ18 AM8 C286 1U/6.3V_4 AD13
VCCFDIPLL VCCME3_3[1] +3V_VCCME_SPIR201 *SHORT0603 C273 1U/6.3V_4 VCC3_3[14]
AM9 +3V AH34
VCCME3_3[2] VCCIO[3]
FDI
+1.05V_VCCDPLL_FDI AM23 AP11 31mA(15mils)

C645 VCCIO[1] VCCME3_3[3] C329
AP9 AF32
*10u/6.3V_6 VCCME3_3[4] VCCIO[4] +V1.1LAN_VCCAPLL L28 *10uh_8
AK3 +1.05V
.1u/16V_4 +VCCSST VCCSATAPLL[1]
V12 AK1
C325 0.1u/10V_4_X7R DCPSST VCCSATAPLL[2] C668 C351
IbexPeak-M_R1P0 *1u/6.3V_4 *10u/6.3V_6
+V1.1LAN_INT_VCCSUS Y22 VCCIO = 3.062A(150mils)

C306 0.1u/10V_4_X7R DCPSUS +V1.1LAN_VCC_SATA R526 *SHORT1206+1.05V
AH22
R169 *SHORT0603 VCCIO[9]
B
+1.05V B
P18 AT20 +V1.5S_1.8S C320
VCCSUS3_3[29] VCCVRM[4] 1u/10V_4
VCCSUS3_3 = 163mA(20mils)
VCCVRM=196mA(15mils) HDA_SYNC (PCH strap pin) +3V_S5 R168 *SHORT0603 +3V_S5_VCCPSUS U19
SATA
VCCSUS3_3[30]
PCI/GPIO/LPC
AH19
R213 *SHORT0603 VCCIO[10]
+1.8V +V1.5S_1.8S Internal weak pull-down U20
VCCSUS3_3[31]
VCCVRM=>+1.8V (default) AD20
C314 0.1u/10V_4_X7R U22 VCCIO[11]
C344 C345
external pull-up VCCSUS3_3[32]
AF22
.1u/16V_4 .1u/16V_4 VCCVRM=>+1.5V VCCIO[12]
VRM enable by strap pin GPIO27 VCC3_3 = 0.357A(30mils) VCCIO[13]
AD19
+3V R186 *SHORT0603 +3V_VCCPCORE V15 AF20
which supply clean 1.05V for VCC3_3[5] VCCIO[14]
AF19
[VCCACLK,VCCAPLLEXP,VCCFDIPLL,VCCSATAPLL] VCCIO[15]
V16 AH20
VCC3_3[6] VCCIO[16]
5/27 cost down
C318 0.1u/10V_4_X7R Y16 AB19
VCC3_3[7] VCCIO[17]
AB20
L45 *10uh_8 +V1.1LAN_VCCA_A_DPL VCCIO[18]
+1.05V AB22
R198 0_6 VCCIO[19]
V_CPU_IO >1mA(15mils) AD22
C592 + +VTT_VCCPCPU VCCIO[20]
+1.05V AT18
V_CPU_IO[1]
VCCME = 1.849A(100mils)
*220u_3528 R424 AA34 +1.05V_VCCEPW
CPU
C342 4.7U/6.3V_6 VCCME[13]
0_8 Y34
C338 0.1u/10V_4_X7R VCCME[14]
AU18 Y35
L46 10uh_8 +V1.1LAN_VCCA_B_DPL C336 0.1u/10V_4_X7R V_CPU_IO[2] VCCME[15]
AA35
VCCME[16]
C601 + VCCRTC= 2mA(15mils)
RTC
+VCCRTC A12 L30 +V3.3A_1.5A_HDA_IO R163 *Short_4 +3V_S5
VCCRTC VCCSUSHDA
HDA
220u_3528
C664 0.1u/10V_4_X7R VCCSUSHDA= 6mA(15mils)
C665 0.1u/10V_4_X7R IbexPeak-M_R1P0 C276
1u/10V_4
A A

PROJECT : ZQ9
1A
IBEX PEAK-M 5/6
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
U21I
AY7 H49
IBEX PEAK-M (GND) B11
B15
VSS[159]
VSS[160]
VSS[259]
VSS[260] H5
J24
VSS[161] VSS[261]
D B19 VSS[162] VSS[262] K11 D
B23 VSS[163] VSS[263] K43
B31 VSS[164] VSS[264] K47
B35 VSS[165] VSS[265] K7
B39 VSS[166] VSS[266] L14
B43 VSS[167] VSS[267] L18
B47 VSS[168] VSS[268] L2
B7 VSS[169] VSS[269] L22
BG12 VSS[170] VSS[270] L32
BB12 VSS[171] VSS[271] L36
U21H BB16 L40
VSS[172] VSS[272]
AB16 VSS[0] BB20 VSS[173] VSS[273] L52
BB24 VSS[174] VSS[274] M12
AA19 VSS[1] VSS[80] AK30 BB30 VSS[175] VSS[275] M16
AA22 VSS[3] VSS[82] AK32 BB38 VSS[177] VSS[277] N38
AM19 VSS[4] VSS[83] AK34 BB42 VSS[178] VSS[278] M34
AA28 VSS[7] VSS[86] AK43 BC10 VSS[181] VSS[281] M46
AB11 VSS[11] VSS[90] AK8 BC22 VSS[185] VSS[285] N24
AB15 VSS[12] VSS[91] AL2 BC32 VSS[186] VSS[286] P11
AB23 VSS[13] VSS[92] AL52 BC36 VSS[187] VSS[287] AD15
AB30 VSS[14] VSS[93] AM11 BC40 VSS[188] VSS[288] P22
AB31 VSS[15] VSS[94] BB44 BC44 VSS[189] VSS[289] P30
AB32 VSS[16] VSS[95] AD24 BC52 VSS[190] VSS[290] P32
AB39 VSS[17] VSS[96] AM20 BH9 VSS[191] VSS[291] P34
AB43 VSS[18] VSS[97] AM22 BD48 VSS[192] VSS[292] P42
C C
AB8 VSS[21] VSS[100] AM28 BE12 VSS[195] VSS[295] R2
AC2 VSS[22] VSS[101] BA42 BE16 VSS[196] VSS[296] R52
AC52 VSS[23] VSS[102] AM30 BE20 VSS[197] VSS[297] T12
AD11 VSS[24] VSS[103] AM31 BE24 VSS[198] VSS[298] T41
AD31 VSS[29] VSS[108] AM39 BE46 VSS[203] VSS[303] U30
AD32 VSS[30] VSS[109] AM42 BE48 VSS[204] VSS[304] U31
AD34 VSS[31] VSS[110] AU20 BE50 VSS[205] VSS[305] U32
AU22 VSS[32] VSS[111] AM46 BE6 VSS[206] VSS[306] U34
AD42 VSS[33] VSS[112] AV22 BE8 VSS[207] VSS[307] P38
AD46 VSS[34] VSS[113] AM49 BF3 VSS[208] VSS[308] V11
AD49 VSS[35] VSS[114] AM7 BF49 VSS[209] VSS[309] P16
AD7 VSS[36] VSS[115] AA50 BF51 VSS[210] VSS[310] V19
AE2 VSS[37] VSS[116] BB10 BG18 VSS[211] VSS[311] V20
AE4 VSS[38] VSS[117] AN32 BG24 VSS[212] VSS[312] V22
AF12 VSS[39] VSS[118] AN50 BG4 VSS[213] VSS[313] V30
Y13 VSS[40] VSS[119] AN52 BG50 VSS[214] VSS[314] V31
AH49 VSS[41] VSS[120] AP12 BH11 VSS[215] VSS[315] V32
AU4 VSS[42] VSS[121] AP42 BH15 VSS[216] VSS[316] V34
AF35 VSS[43] VSS[122] AP46 BH19 VSS[217] VSS[317] V35
AP13 VSS[44] VSS[123] AP49 BH23 VSS[218] VSS[318] V38
AN34 VSS[45] VSS[124] AP5 BH31 VSS[219] VSS[319] V43
AF45 VSS[46] VSS[125] AP8 BH35 VSS[220] VSS[320] V45
AF46 VSS[47] VSS[126] AR2 BH39 VSS[221] VSS[321] V46
AF49 VSS[48] VSS[127] AR52 BH43 VSS[222] VSS[322] V47
AF5 VSS[49] VSS[128] AT11 BH47 VSS[223] VSS[323] V49
AF8 VSS[50] VSS[129] BA12 BH7 VSS[224] VSS[324] V5
B AG2 AH48 C12 V7 B
VSS[51] VSS[130] VSS[225] VSS[325]
AG52 VSS[52] VSS[131] AT32 C50 VSS[226] VSS[326] V8
AH11 VSS[53] VSS[132] AT36 D51 VSS[227] VSS[327] W2
AH15 VSS[54] VSS[133] AT41 E12 VSS[228] VSS[328] W52
AH16 VSS[55] VSS[134] AT47 E16 VSS[229] VSS[329] Y11
AH24 VSS[56] VSS[135] AT7 E20 VSS[230] VSS[330] Y12
AH32 VSS[57] VSS[136] AV12 E24 VSS[231] VSS[331] Y15
AV18 VSS[58] VSS[137] AV16 E30 VSS[232] VSS[332] Y19
AJ19 VSS[62] VSS[141] AV34 E46 VSS[236] VSS[336] Y31
AJ23 VSS[66] VSS[145] AV49 F49 VSS[240] VSS[340] Y46
AJ26 VSS[67] VSS[146] AV5 F5 VSS[241] VSS[341] P49
AJ28 VSS[68] VSS[147] AV8 G10 VSS[242] VSS[342] Y5
AJ32 VSS[69] VSS[148] AW14 G14 VSS[243] VSS[343] Y6
AJ34 VSS[70] VSS[149] AW18 G18 VSS[244] VSS[344] Y8
AT5 VSS[71] VSS[150] AW2 G2 VSS[245] VSS[345] P24
AJ4 VSS[72] VSS[151] BF9 G22 VSS[246] VSS[346] T43
AK12 VSS[73] VSS[152] AW32 G32 VSS[247] VSS[347] AD51
AM41 VSS[74] VSS[153] AW36 G36 VSS[248] VSS[348] AT8
AN19 VSS[75] VSS[154] AW40 G40 VSS[249] VSS[349] AD47
AK26 VSS[76] VSS[155] AW52 G44 VSS[250] VSS[350] Y47
AK22 VSS[77] VSS[156] AY11 G52 VSS[251] VSS[351] AT12
AK23 VSS[78] VSS[157] AY43 AF39 VSS[252] VSS[352] AM6
AK28 VSS[79] VSS[158] AY47 H16 VSS[253] VSS[353] AT13
H20 VSS[254] VSS[354] AM5
IbexPeak-M_R1P0 H30 AK45
VSS[255] VSS[355]
A H34 VSS[256] VSS[356] AK39 A
H38 VSS[257] VSS[366] AV14
H42 VSS[258]
IbexPeak-M_R1P0
PROJECT : ZQ9
www.vinafix.vn
1A
IBEX PEAK-M 6/6
5 4 3 2 1
5 4 3 2 1
+1.5VSUS
JDIM1B
JDIM1A M_A_DQ[63:0] <5>
<5> M_A_A[15:0] 75 VDD1 VSS16 44
M_A_A0 98 5 M_A_DQ4 76 48
M_A_A1 A0 DQ0 M_A_DQ0 VDD2 VSS17
97 A1 DQ1 7 81 VDD3 VSS18 49
M_A_A2 96 15 M_A_DQ2 82 54
95 A3 DQ3 17 87 VDD5 VSS20 55
M_A_A4 92 4 M_A_DQ1 88 60
91 A5 DQ5 6 93 VDD7 VSS22 61
M_A_A6 90 16 M_A_DQ6 94 65
M_A_A7 86
A6 DQ6
18 M_A_DQ7
2.48A 99
VDD8 VSS23
66
D 89 A8 DQ8 21 100 VDD10 VSS25 71 D
M_A_A9 85 23 M_A_DQ13 105 72
PC2100 DDR3 SDRAM SO-DIMM

107 A10/AP DQ10 33 106 VDD12 VSS27 127
M_A_A11 84 35 M_A_DQ10 111 128
83 A12/BC# DQ12 22 112 VDD14 VSS29 133
M_A_A13 119 24 M_A_DQ9 117 134
80 A14 DQ14 34 118 VDD16 VSS31 138
M_A_A15 78 36 M_A_DQ15 123 139
A15 DQ15 M_A_DQ17 VDD17 VSS32

DQ16 39 124 VDD18 VSS33 144
109 41 M_A_DQ20 145
<5> M_A_BS#0 BA0 DQ17 VSS34
108 51 M_A_DQ18 199 150
<5> M_A_BS#1 BA1 DQ18 +3V VDDSPD VSS35
79 53 M_A_DQ19 151
<5> M_A_BS#2 BA2 DQ19 VSS36
114 40 M_A_DQ16 77 155
<5> M_A_CS#0 S0# DQ20 NC1 VSS37
121 42 M_A_DQ21 122 156
<5> M_A_CS#1 S1# DQ21 NC2 VSS38
101 50 M_A_DQ22 125 161
<5> M_A_CLK0 CK0 DQ22 NCTEST VSS39
103 52 M_A_DQ23 162
<5> M_A_CLK0# CK0# DQ23 VSS40
102 57 M_A_DQ24 198 167
<5> M_A_CLK1 CK1 DQ24 <4> PM_EXTTS#0 EVENT# VSS41
104 59 M_A_DQ28 30 168
<5> M_A_CLK1# CK1# DQ25 <4,15> DDR3_DRAMRST# RESET# VSS42
M_A_DQ25
<5> M_A_CKE0 73
74
CKE0 DQ26 67
69 M_A_DQ26
M3 solution VSS43 172
173
<5> M_A_CKE1 CKE1 DQ27 VSS44
115 56 M_A_DQ27 R266 *M3@0_6 +SMDDR_VREF_DQ0 1 178
<5> M_A_CAS# CAS# DQ28 <7> VREF_DQ_DIMM0 VREF_DQ VSS45
110 58 M_A_DQ29 +SMDDR_VREF_DIMM 126 179
<5> M_A_RAS# RAS# DQ29 +SMDDR_VREF_DIMM VREF_CA VSS46
113 68 M_A_DQ31 184
<5> M_A_WE# WE# DQ30 VSS47
R270 10K_4 DIMM0_SA0 197 70 M_A_DQ30 185
R269 10K_4 DIMM0_SA1 SA0 DQ31 M_A_DQ36 VSS48
201 SA1 DQ32 129 2 VSS1 VSS49 189
CLK_SCLK 202 131 M_A_DQ33 3 190
<3,15,27> CLK_SCLK CLK_SDATA SCL DQ33 M_A_DQ35 VSS2 VSS50
200 141 8 195
(204P)
<3,15,27> CLK_SDATA SDA DQ34 M_A_DQ34 VSS3 VSS51
C DQ35 143 9 VSS4 VSS52 196 C
116 130 M_A_DQ32 13
<5> M_A_ODT0 ODT0 DQ36 VSS5
120 132 M_A_DQ37 14
<5> M_A_ODT1 ODT1 DQ37 VSS6
140 M_A_DQ38 19
<5> M_A_DM[7:0] DQ38 VSS7
M_A_DM0 11 142 M_A_DQ39 20
M_A_DM1 DM0 DQ39 M_A_DQ45 VSS8
28 DM1 DQ40 147 25 VSS9
M_A_DM2 46 149 M_A_DQ44 26 203 +0.75V_DDR_VTT
M_A_DM3 63
DM2
DM3
(204P) DQ41
DQ42 157 M_A_DQ47 31
VSS10
VSS11
VTT1
VTT2 204
M_A_DM4 136 159 M_A_DQ42 +1.5VSUS 32
M_A_DM5 DM4 DQ43 M_A_DQ41 VSS12
153 DM5 DQ44 146 37 VSS13 GND 205
M_A_DM6 170 148 M_A_DQ40 38 206
M_A_DM7 DM6 DQ45 M_A_DQ46 VSS14 GND
187 DM7 DQ46 158 43 VSS15
160 M_A_DQ43 R276
<5> M_A_DQS[7:0] DQ47
M_A_DQS0 12 163 M_A_DQ48 *10K_4
M_A_DQS1 DQS0 DQ48 M_A_DQ49
29 DQS1 DQ49 165 DDR3-DIMM1_H=8.0_Reverse
M_A_DQS2 47 175 M_A_DQ50
M_A_DQS3 DQS2 DQ50 M_A_DQ51 R275 *SHORT0603+SMDDR_VREF_DIMM
64 DQS3 DQ51 177 +SMDDR_VREF
M_A_DQS4 137 164 M_A_DQ52
154 DQS5 DQ53 166
M_A_DQS6 171 174 M_A_DQ54 R264 C403
<5> M_A_DQS#[7:0] 188 DQS7 DQ55 176 *10K_4 470p/X7R_4
M_A_DQS#0 10 181 M_A_DQ56
M_A_DQS#1 DQS#0 DQ56 M_A_DQ57
27 DQS#1 DQ57 183
M_A_DQS#2 45 191 M_A_DQ62
62 DQS#3 DQ59 193
M_A_DQS#4 135 180 M_A_DQ60
152 DQS#5 DQ61 182
M_A_DQS#6 169 192 M_A_DQ63 +1.5VSUS
B DQS#6 DQ62 B
M_A_DQS#7 186 194 M_A_DQ58
DQS#7 DQ63
R259
DDR3-DIMM1_H=8.0_Reverse *10K/F_4
M1 solution
+SMDDR_VREF R268 *SHORT0603+SMDDR_VREF_DQ0
Place these Caps near So-Dimm0.
R260 C380
*10K/F_4 470p/X7R_4
+1.5VSUS
+SMDDR_VREF_DIMM +SMDDR_VREF_DQ0
C366 C381 C369 C377 C387 5/27 cost down
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4
C365 + C367 C379 C378 C385 C383

*330u/2V_7343
10u/6.3V_6 .1u/16V_4 .1u/16V_4
C391 C372 C370 C371 C376 2.2u/6.3V_6 2.2u/6.3V_6

10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4 .1u/16V_4
A A
+3V +0.75V_DDR_VTT
5/27 cost down
C393 C375 C374 C389 C373 C396 C412

C397
2.2u/6.3V_6
C394
.1u/16V_4
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6
PROJECT : ZQ9
www.vinafix.vn
1A
DDRIII SO-DIMM-0
5 4 3 2 1
5 4 3 2 1
+1.5VSUS
JDIM2A M_B_DQ[63:0] <5> 5/26 change the footprint JDIM2B
<5> M_B_A[15:0]
M_B_A0 98 5 M_B_DQ5 75 44
M_B_A1 A0 DQ0 M_B_DQ1 VDD1 VSS16
97 A1 DQ1 7 76 VDD2 VSS17 48
M_B_A2 96 15 M_B_DQ2 81 49
95 A3 DQ3 17 82 VDD4 VSS19 54
M_B_A4 92 4 M_B_DQ0 87 55
91 A5 DQ5 6 88 VDD6 VSS21 60
M_B_A6 90 16 M_B_DQ6 93 61
86 A7 DQ7 18 94 VDD8 VSS23 65
M_B_A8 89 21 M_B_DQ8 99 66
D
M_B_A9 85
A8 DQ8
23 M_B_DQ9
2.48A 100
VDD9 VSS24
71
D

107 A10/AP DQ10 33 105 VDD11 VSS26 72
M_B_A11 M_B_DQ11

84 A11 DQ11 35 106 VDD12 VSS27 127
M_B_A12 83 22 M_B_DQ12 111 128
M_B_A13 A12/BC# DQ12 M_B_DQ13 VDD13 VSS28
119 A13 DQ13 24 112 VDD14 VSS29 133
M_B_A14 80 34 M_B_DQ14 117 134
78 A15 DQ15 36 118 VDD16 VSS31 138
M_B_DQ18

DQ16 39 123 VDD17 VSS32 139
109 41 M_B_DQ17 124 144
<5> M_B_BS#0 BA0 DQ17 VDD18 VSS33
108 51 M_B_DQ16 145
<5> M_B_BS#1 BA1 DQ18 VSS34
79 53 M_B_DQ19 199 150
<5> M_B_BS#2 BA2 DQ19 +3V VDDSPD VSS35
114 40 M_B_DQ20 151
<5> M_B_CS#0 S0# DQ20 VSS36
121 42 M_B_DQ21 77 155
<5> M_B_CS#1 S1# DQ21 NC1 VSS37
101 50 M_B_DQ22 122 156
<5> M_B_CLK0 CK0 DQ22 NC2 VSS38
103 52 M_B_DQ23 125 161
<5> M_B_CLK0# CK0# DQ23 NCTEST VSS39
102 57 M_B_DQ26 162
<5> M_B_CLK1 CK1 DQ24 VSS40
104 59 M_B_DQ25 198 167
<5> M_B_CLK1# CK1# DQ25 <4> PM_EXTTS#1 EVENT# VSS41
73 67 M_B_DQ30 30 168
<5> M_B_CKE0 CKE0 DQ26 <4,14> DDR3_DRAMRST# RESET# VSS42
M_B_DQ27
<5> M_B_CKE1 74
115
CKE1 DQ27 69
56 M_B_DQ29
M3 solution VSS43 172
173
<5> M_B_CAS# CAS# DQ28 VSS44
110 58 M_B_DQ24 R302 *M3@0_6 +SMDDR_VREF_DQ1 1 178
<5> M_B_RAS# RAS# DQ29 <7> VREF_DQ_DIMM1 VREF_DQ VSS45
113 68 M_B_DQ28 126 179
<5> M_B_WE# WE# DQ30 +SMDDR_VREF_DIMM VREF_CA VSS46
R295 10K_4 DIMM1_SA0 197 70 M_B_DQ31 184
R298 10K_4 DIMM1_SA1 SA0 DQ31 M_B_DQ32 VSS47
+3V 201 SA1 DQ32 129 VSS48 185
202 131 M_B_DQ33 2 189
<3,14,27> CLK_SCLK SCL DQ33 M_B_DQ34 VSS1 VSS49
200 SDA DQ34 141 3 VSS2 VSS50 190
<3,14,27> CLK_SDATA 143 M_B_DQ35 8 195
(204P)
C DQ35 VSS3 VSS51 C
116 130 M_B_DQ36 9 196
<5> M_B_ODT0 ODT0 DQ36 VSS4 VSS52
120 132 M_B_DQ37 13
<5> M_B_ODT1 ODT1 DQ37 VSS5
140 M_B_DQ38 14
<5> M_B_DM[7:0] DQ38 VSS6
M_B_DM0 11 142 M_B_DQ39 19
M_B_DM1 DM0 DQ39 M_B_DQ40 VSS7
28 DM1 DQ40 147 20 VSS8
M_B_DM2 46 149 M_B_DQ45 +1.5VSUS 25
M_B_DM3 63
DM2
DM3
(204P) DQ41
DQ42 157 M_B_DQ47 26
VSS9
VSS10 VTT1 203 +0.75V_DDR_VTT
M_B_DM4 136 159 M_B_DQ43 31 204
M_B_DM5 DM4 DQ43 M_B_DQ44 VSS11 VTT2
153 DM5 DQ44 146 32 VSS12
M_B_DM6 M_B_DQ41 R301
M_B_DM7
170
187
DM6 DQ45 148
158 M_B_DQ46
M1 solution *10K/F_4
37
38
VSS13 GND 205
206
DM7 DQ46 M_B_DQ42 VSS14 GND
<5> M_B_DQS[7:0] DQ47 160 43 VSS15
M_B_DQS0 12 163 M_B_DQ48
M_B_DQS1 DQS0 DQ48 M_B_DQ53 R299 *SHORT0603+SMDDR_VREF_DQ1
29 DQS1 DQ49 165 +SMDDR_VREF
M_B_DQS2 47 175 M_B_DQ50 DDR3-DIMM1_H=4.0_Reverse
M_B_DQS3 DQS2 DQ50 M_B_DQ54
64 DQS3 DQ51 177
M_B_DQS4 137 164 M_B_DQ52 R304 C452
M_B_DQS5 DQS4 DQ52 M_B_DQ49 *10K/F_4
154 DQS5 DQ53 166 470p/X7R_4
M_B_DQS6 171 174 M_B_DQ51
M_B_DQS7 DQS6 DQ54 M_B_DQ55
<5> M_B_DQS#[7:0] 188 DQS7 DQ55 176
M_B_DQS#0 10 181 M_B_DQ60
M_B_DQS#1 DQS#0 DQ56 M_B_DQ57
27 DQS#1 DQ57 183
M_B_DQS#2 45 191 M_B_DQ63
62 DQS#3 DQ59 193
M_B_DQS#4 135 180 M_B_DQ59
152 DQS#5 DQ61 182
B M_B_DQS#6 169 192 M_B_DQ62 B
186 DQS#7 DQ63 194
DDR3-DIMM1_H=4.0_Reverse
+1.5VSUS Place these Caps near So-Dimm1.

+SMDDR_VREF_DIMM +SMDDR_VREF_DQ1
C438 C435 C437 C434 C405
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4
C439 + C450 C413 C416 C440 C444

330u/2V_7343
10u/6.3V_6 .1u/16V_4 .1u/16V_4
C436 C408 C407 C406 C433 2.2u/6.3V_6 2.2u/6.3V_6

10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4 .1u/16V_4
+3V +0.75V_DDR_VTT
5/27 for cost down
A C425 C414 C424 C415 C411 C421 C402 A

C443 C427 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
2.2u/6.3V_6 .1u/16V_4 4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6

PROJECT : ZQ9
www.vinafix.vn
1A
DDRIII SO-DIMM-1
5 4 3 2 1
5 4 3 2 1
GPU_1(VGA) U15A
PEG_TXP[0..15] 0518 SWAP PCIE for VGA side

<4> PEG_TXP[0..15]
PEG_TXN[0..15] 0518 SWAP PCIE for VGA side
<4> PEG_TXN[0..15]
PEG_RXP[0..15] PEG_TXP15 AA38 Y33 CPEG_RXP15 C116 EV@0.1u/10V_4

<4> PEG_RXP[0..15] <4> PEG_TXP15 PCIE_RX0P PCIE_TX0P PEG_RXP15 <4>
PEG_TXN15 Y37 Y32 CPEG_RXN15 C107 EV@0.1u/10V_4
D PEG_RXN[0..15] <4> PEG_TXN15 PCIE_RX0N PCIE_TX0N PEG_RXN15 <4> D
<4> PEG_RXN[0..15]
PEG_TXP14 Y35 W33 CPEG_RXP14 C122 EV@0.1u/10V_4
<4> PEG_TXP14 PCIE_RX1P PCIE_TX1P PEG_RXP14 <4>
PEG_TXN14 W36 W32 CPEG_RXN14 C117 EV@0.1u/10V_4
<4> PEG_TXN14 PCIE_RX1N PCIE_TX1N PEG_RXN14 <4>
PEG_TXP13 W38 U33 CPEG_RXP13 C126 EV@0.1u/10V_4

PEG_TXN13 V37 U32 CPEG_RXN13 C123 EV@0.1u/10V_4
PEG_TXP12 V35 U30 CPEG_RXP12 C127 EV@0.1u/10V_4

PEG_TXN12 U36 U29 CPEG_RXN12 C135 EV@0.1u/10V_4
PEG_TXP11 U38 T33 CPEG_RXP11 C136 EV@0.1u/10V_4

PEG_TXN11 T37 T32 CPEG_RXN11 C151 EV@0.1u/10V_4
PCI EXPRESS INTERFACE

PEG_TXP10 T35 T30 CPEG_RXP10 C150 EV@0.1u/10V_4
PEG_TXN10 R36 T29 CPEG_RXN10 C159 EV@0.1u/10V_4
PEG_TXP9 R38 P33 CPEG_RXP9 C160 EV@0.1u/10V_4

PEG_TXN9 P37 P32 CPEG_RXN9 C172 EV@0.1u/10V_4
C <4> PEG_TXN9 PCIE_RX6N PCIE_TX6N PEG_RXN9 <4> C
PEG_TXP8 P35 P30 CPEG_RXP8 C181 EV@0.1u/10V_4

PEG_TXN8 N36 P29 CPEG_RXN8 C180 EV@0.1u/10V_4
PEG_TXP7 N38 N33 CPEG_RXP7 C190 EV@0.1u/10V_4

PEG_TXN7 M37 N32 CPEG_RXN7 C189 EV@0.1u/10V_4
PEG_TXP6 M35 N30 CPEG_RXP6 C198 EV@0.1u/10V_4

PEG_TXN6 L36 N29 CPEG_RXN6 C197 EV@0.1u/10V_4
PEG_TXP5 L38 L33 CPEG_RXP5 C207 EV@0.1u/10V_4

PEG_TXN5 K37 L32 CPEG_RXN5 C206 EV@0.1u/10V_4
PEG_TXP4 K35 L30 CPEG_RXP4 C205 EV@0.1u/10V_4

PEG_TXN4 J36 L29 CPEG_RXN4 C204 EV@0.1u/10V_4
PEG_TXP3 J38 K33 CPEG_RXP3 C202 EV@0.1u/10V_4

B PEG_TXN3 H37 K32 CPEG_RXN3 C203 EV@0.1u/10V_4 B
PEG_TXP2 H35 J33 CPEG_RXP2 C212 EV@0.1u/10V_4

PEG_TXN2 G36 J32 CPEG_RXN2 C213 EV@0.1u/10V_4
PEG_TXP1 G38 K30 CPEG_RXP1 C209 EV@0.1u/10V_4

PEG_TXN1 F37 K29 CPEG_RXN1 C208 EV@0.1u/10V_4
PEG_TXP0 F35 H33 CPEG_RXP0 C211 EV@0.1u/10V_4

PEG_TXN0 E37 H32 CPEG_RXN0 C210 EV@0.1u/10V_4
CLOCK
<10> CLK_PCIE_VGA AB35 PCIE_REFCLKP
<10> CLK_PCIE_VGA# AA36 PCIE_REFCLKN Madison AJ007720T02
For Broadway, Madison and Park CALIBRATION Park AJ077400T08

AJ21 Y30 R72 EV@1.27K/F_4
the PWRGOOD ball must be conneccted to ground NC#1 PCIE_CALRP
AK21 NC#2
A R52 EV@10K_4 R74 EV@2K/F_4 A
AH16 PWRGOOD PCIE_CALRN Y29 +1V +1.0V
<11> GPU_RST# AA30 PERSTB For M97, Broadway, Madison and Park PCIE_VDDC is 1.0V Quanta Computer Inc.
EV@Park_M2
PROJECT : ZQ9
1A
Madison/Park M2-PCIE I/F
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
U15B U15G
GPU_2(VGA)
AU24 LVDS CONTROL AK27
TXCAP_DPA3P HDMICLK+ <24> VARY_BL EV_LVDS_BRIGHT <23>
AV23 HDMICLK- <24> AJ27 EV_LVDS_VDDEN <23>
TXCAM_DPA3N DIGON
AT25 HDMITX0P <24>
MUTI GFX TX0P_DPA2P
AR24 HDMITX0N <24>
DPA TX0M_DPA2N
AU26 HDMITX1P <24> AK35
TX1P_DPA1P TXCLK_UP_DPF3P
AV25 HDMITX1N <24> AL36
TX1M_DPA1N TXCLK_UN_DPF3N
AR8 AT27 HDMITX2P <24> AJ38
DVPCNTL_MVP_0 TX2P_DPA0P TXOUT_U0P_DPF2P
AU8 AR26 HDMITX2N <24> AK37
D DVPCNTL_MVP_1 TX2M_DPA0N TXOUT_U0N_DPF2N D
AP8
NC on Park AW8
DVPCNTL_0
DVPCNTL_1 TXCBP_DPB3P
AR30
TXOUT_U1P_DPF1P
AH35
AR3 AT29 AJ36
DVPCNTL_2 TXCBM_DPB3N TXOUT_U1N_DPF1N
AR1
GPU Power-on sequence <21> RAM_STRAP0 AU1
AU3
DVPCLK
DVPDATA_0 TX3P_DPB2P
AV31
AU30
TXOUT_U2P_DPF0P
AG38
AH37
<21> RAM_STRAP1 DVPDATA_1 DPB TX3M_DPB2N TXOUT_U2N_DPF0N
AW3
1 => MAINON <21> RAM_STRAP2
AP6
DVPDATA_2
AR32
TXOUT_U3P
AF35
T32 AW5 AT31 AG36
2 => +VGPU_CORE AU5
DVPDATA_4
DVPDATA_5
TX4M_DPB1N TXOUT_U3N
AR6 AT33
3 => +1V 1.8V GPIO AW6
AU6
DVPDATA_7 TX5M_DPB0N
AU32 LVTMDP
DVPDATA_8
4 => +1.5V_GPU AT7
AV7
DVPDATA_9
DVPDATA_10
TXCCP_DPC3P
TXCCM_DPC3N
AU14
AV13
TXCLK_LP_DPE3P
TXCLK_LN_DPE3N
AP34
AR34
EV_TXLCLKOUT+ <23>
EV_TXLCLKOUT- <23>
AN7
5 => +1.8V_GPU AV9
DVPDATA_11
DVPDATA_12 TX0P_DPC2P
AT15
TXOUT_L0P_DPE2P
AW37 EV_TXLOUT0+ <23>
AT9 AR14 AU35
6 => GPU_RST# AR10
DVPDATA_13
DVPDATA_14 DPC
TX0M_DPC2N TXOUT_L0N_DPE2N EV_TXLOUT0- <23>
AW10 AU16 AR37 EV_TXLOUT1+ <23>
DVPDATA_15 TX1P_DPC1P TXOUT_L1P_DPE1P
AU10 AV15 AU39 EV_TXLOUT1- <23>
DVPDATA_16 TX1M_DPC1N TXOUT_L1N_DPE1N
AP10
DVPDATA_17
AV11 AT17 AP35 EV_TXLOUT2+ <23>
DVPDATA_18 TX2P_DPC0P TXOUT_L2P_DPE0P
AT11 AR16 AR35 EV_TXLOUT2- <23>
DVPDATA_19 TX2M_DPC0N TXOUT_L2N_DPE0N
AR12
NC on Park AW12
DVPDATA_20
DVPDATA_21 TXCDP_DPD3P
AU20
TXOUT_L3P
AN36
AU12 AT19 AP37
DVPDATA_22 TXCDM_DPD3N TXOUT_L3N
AP12
+3V_D DVPDATA_23
AT21
TX3P_DPD2P
AR20
TX3M_DPD2N
DPD
Channel D N.C for Park-M2
AU22
TX4P_DPD1P EV@Park_M2
AV21
R47 R49 TX4M_DPD1N
EV@10K_4 EV@10K_4 I2C AT23
TX5P_DPD0P
AR22
TX5M_DPD0N
AK26
SCL
C AJ26 C
SDA
AD39 EV_CRT_RED <23>
GENERAL PURPOSE I/O R
AD37
RB
<21> GPU_GPIO0 AH20
GPIO_0
<21> GPU_GPIO1 AH18 AE36 EV_CRT_GRN <23>
GPIO_1 G
<21> GPU_GPIO2 AN16 AD35
GPIO_2 GB
<21> GPIO3_SMBDAT AH23
GPIO_3_SMBDATA
<21> GPIO4_SMBCLK AJ23 AF37 EV_CRT_BLU <23>
GPIO_4_SMBCLK B
AH17 AE38
1/21 ramp remove IO_VID0 GPIO_5_AC_BATT DAC1 BB
AJ17
GPIO_6 R60 R62 R65
<23> EV_LVDS_BLON AK17 AC36 EV_HSYNC <21,23>
GPIO_7_BLON HSYNC EV@150/F_4 EV@150/F_4 EV@150/F_4
T33 AJ13 AC38 EV_VSYNC <21,23>
GPIO_8_ROMSO VSYNC
T35 AH15
GPIO_9_ROMSI
+3V_D
5/17 change to test pad AJ16
GPIO_10_ROMSCK
AK16 AB34 R71 EV@499/F_4
<21> GPU_GPIO11 GPIO_11 RSET
<21> GPU_GPIO12 AL16
GPIO_12 AVDD
<21> GPU_GPIO13 AM16 AD34
GPIO_13 AVDD +1.8V_GPU
AM14 AE34
R347 GPIO_14_HPD2 AVSSQ
3.3V GPIO <42> VID1 AM13
GPIO_15_PWRCNTL_0 (1.8V@70mA AVDD)
AK14 AC33 VDD1DI
*EV@10K_4 GPIO_16_SSIN VDD1DI AVDD L16 EV@SBY100505T-121Y-N/300mA/120ohm_4
<21> ALT#_GPIO17 AG30 AC34
GPIO_17_THERMAL_INT VSS1DI
AN14
GPIO_18_HPD3
AM17
GPIO_19_CTF C99 C89 C90
<42> VID2 AL13 AC30
+3V_D GPIO_20_PWRCNTL_1 R2 R67 EV@0_4 EV@0.1u/10V_4 EV@1u/6.3V_4 EV@10u/6.3V_6
AJ14 AC31
R352 GPIO_21_BB_EN R2B
5/17 change to test pad T34 AK13
GPIO_22_ROMCSB
AN13 AD30
EV@10K_4 5/17 delete workaround GPIO_23_CLKREQB G2 R56 EV@0_4
AM23
JTAG_TRSTB G2B
AD31 (1.8V@100mA VDD1DI)
R358 AN23
27M_CLK JTAG_TDI VDD1DI L15 EV@SBY100505T-121Y-N/300mA/120ohm_4
<3> 27M_CLK AK23 AF30
*EV@10K/F_4 R41 *EV@10K_4 JTAG_TCK B2 R57 EV@0_4
+3V_D AL24 AF31
5/17 delete JTAG_TMS B2B
AM24
D3D JTAG_TDO C72 C75 C70
AJ19
GENERICA DAC2 will be NC on future ASIC
AK19 AC32 EV@0.1u/10V_4 EV@1u/6.3V_4 EV@10u/6.3V_6
GENERICB C
AJ20 AD32
R359 GENERICC Y
AK20 AF32
GENERICD COMP
AJ24
B
*EV@10K/F_4 GENERICE_HPD4 DAC2 B
AH26
GENERICF
AH24 AD29 T4
GENERICG H2SYNC
AC29 V2SYNC <21>
V2SYNC
<24> HDMI_HP_EV
AK24
+1.8V_GPU HPD1 VDD1DI
AG31
VDD2DI R58 EV@0_4
AG32
VSS2DI
R29 AG33 R59 EV@0_4 +3V_D (3.3V@130mA A2VDD)

A2VDD
EV@499/F_4
AD33 A2VDDQ
VREFG A2VDDQ C80
AH13
VREFG EV@0.1u/10V_4
AF33
C60 A2VSSQ
R35
EV@249/F_4 EV@0.1u/10V_4 AA29 R69 EV@715/F_4
R2SET
+1.8V(75mA)
+1.8V_GPU L12 EV@SBY100505T-121Y-N/300mA/120ohm_4 DPLL_PVDD DDC/AUX AM26 MXM_DDCCK <24>

PLL/CLOCK DDC1CLK
5/13 add for cost down solution AN26
C57 C58 C65 DPLL_PVDD AM32
DPLL_PVDD
DDC1DATA MXM_DDCDAT <24>
HDMI
AN32 AM27 +1.8V_GPU
EV@10u/6.3V_6 EV@1u/6.3V_4 EV@0.1u/10V_4 R357 *EV@0_4 DPLL_PVSS AUX1P
<3> 27M_CLK_SS AUX1N
AL27 (1.8V@2mA A2VDDQ)
DPLL_VDDC AN31 AM19 A2VDDQ L41 EV@SBY100505T-121Y-N/300mA/120ohm_4
C502 EV@27p/50V_4 DPLL_VDDC DDC2CLK
AL19
DDC2DATA
+1.0V(125mA)
2
XTALI_27M AV33 AN20 C100 C103

L9 EV@SBY100505T-121Y-N/300mA/120ohm_4 DPLL_VDDC Y3 R360 XTALO_27M XTALIN AUX2P EV@0.1u/10V_4 EV@1u/6.3V_4
+1V AU34 AM20
EV@1M/F_4 XTALOUT AUX2N
EV@27MHZ
C41 C50 C62 AL30 T2
1
DDCCLK_AUX3P
AM30
EV@10u/6.3V_6 EV@1u/6.3V_4 EV@0.1u/10V_4 C501 EV@27p/50V_4 DDCDATA_AUX3N
AL29
DDCCLK_AUX4P
AF29 AM29
A
<21>
<21>
GPU_D+
GPU_D- AG29
DPLUS
DMINUS
THERMAL DDCDATA_AUX4N DDC AUX4 NC for Park_M2 A
+1.8V(5mA) DDCCLK_AUX5P
AN21 EV_LVDS_DDCCLK <23>
AM21
+1.8V_GPU L14 EV@SBY100505T-121Y-N/300mA/120ohm_4 TS_VDD
T36
TS_VDD
AK32
TS_FDO
DDCDATA_AUX5N EV_LVDS_DDCDAT <23> LVDS
AJ32 AJ30 EV_CRTDCLK <23>
C63 C71 TSVDD DDC6CLK
AJ33 AJ31
TSVSS DDC6DATA EV_CRTDDAT <23> CRT
EV@10u/6.3V_6 EV@0.1u/10V_4 AK30
NC_DDCCLK_AUX7P
AK29
NC_DDCDATA_AUX7N DDC AUX7 NC for Park_M2
EV@Park_M2
PROJECT : ZQ9
www.vinafix.vn
1A
Madison/Park M2-HOST I/F
5 4 3 2 1
5 4 3 2 1
GPU_3(VGA)
Park M2-channel B used(S3 package use Channel A)
VMB_DQ[63..0]
<22> VMB_DQ[63..0]
VMB_DM[7..0]
<22> VMB_DM[7..0]
U15C U15D
DDR2 DDR2 VMB_RDQS[7..0] DDR2 DDR2
GDDR3/GDDR5 GDDR5/GDDR3 <22> VMB_RDQS[7..0] GDDR3/GDDR5 GDDR5/GDDR3
DDR3 DDR3 VMB_WDQS[7..0] DDR3 DDR3
<22> VMB_WDQS[7..0]
C37 G24 VMB_DQ0 C5 P8 VMB_MA0
DQA0_0/DQA_0 MAA0_0/MAA_0 VMB_DQ1 DQB0_0/DQB_0 MAB0_0/MAB_0 VMB_MA1
C35 J23 C3 T9
MEMORY INTERFACE A
D DQA0_1/DQA_1 MAA0_1/MAA_1 VMB_MA[13..0] VMB_DQ2 DQB0_1/DQB_1 MAB0_1/MAB_1 VMB_MA2 D
A35 H24 E3 P9
MEMORY INTERFACE B
DQA0_2/DQA_2 MAA0_2/MAA_2 <22> VMB_MA[13..0] DQB0_2/DQB_2 MAB0_2/MAB_2
E34 J24 VMB_DQ3 E1 N7 VMB_MA3
G32 H26 F1 N8
DQA0_4/DQA_4 MAA0_4/MAA_4 VMB_BA0 VMB_DQ5 DQB0_4/DQB_4 MAB0_4/MAB_4 VMB_MA5
D33 J26 <22> VMB_BA0 F3 N9
F32 H21 <22> VMB_BA1 F5 U9
E32 G21 <22> VMB_BA2 G4 U8
D31 H19 H5 Y9
F30 H20 H6 W9
C30 L13 J4 AC8
A30 G16 K6 AC9
F28 J16 K5 AA7
DQA0_12/DQA_12 MAA1_4/MAA_12 VMB_DQ13 DQB0_12/DQB_12 MAB1_4/MAB_12 VMB_BA2
C28 H16 L4 AA8
DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 VMB_DQ14 DQB0_13/DQB_13 MAB1_5/BA2 VMB_BA0
A28 J17 M6 Y8
DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 VMB_DQ15 DQB0_14/DQB_14 MAB1_6/BA0 VMB_BA1
E28 H17 M1 AA9
DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 VMB_DQ16 DQB0_15/DQB_15 MAB1_7/BA1
D27 M3
DQA0_16/DQA_16 VMB_DQ17 DQB0_16/DQB_16 VMB_DM0
F26 A32 M5 H3
DQA0_17/DQA_17 WCKA0_0/DQMA_0 VMB_DQ18 DQB0_17/DQB_17 WCKB0_0/DQMB_0 VMB_DM1
C26 C32 N4 H1
DQA0_18/DQA_18 WCKA0B_0/DQMA_1 VMB_DQ19 DQB0_18/DQB_18 WCKB0B_0/DQMB_1 VMB_DM2
A26 D23 P6 T3
F24 E22 P5 T5
C24 C14 R4 AE4
A24 A14 T6 AF5
E24 E10 T1 AK6
C22 D9 U4 AK5
DQA0_24/DQA_24 WCKA1B_1/DQMA_7 VMB_DQ25 DQB0_24/DQB_24 WCKB1B_1/DQMB_7
A22 V6
DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 VMB_DQ26 DQB0_25/DQB_25 GDDR5/DDR2/GDDR3 VMB_RDQS0
F22 C34 V1 F6
DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 VMB_DQ27 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 VMB_RDQS1
D21 D29 V3 K3
+1.5V_GPU DQA0_27/DQA_27 EDCA0_1/QSA_1/RDQSA_1 VMB_DQ28 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1 VMB_RDQS2
A20 D25 Y6 P3
F20
DQA0_29/DQA_29 EDCA0_3/QSA_3/RDQSA_3
E20 Y1
DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3
V5 QSB[7..0]
D19 E16 VMB_DQ30 Y3 AB5 VMB_RDQS4
E18 E12 Y5 AH1
C18 J10 AA4 AJ9
R83 DQA1_0/DQA_32 EDCA1_2/QSA_6/RDQSA_6 VMB_DQ33 DQB1_0/DQB_32 EDCB1_2/QSB_6/RDQSB_6 VMB_RDQS7
A18 D7 AB6 AM5
EV@40.2/F_4 DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 VMB_DQ34 DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7
F18 AB1
DQA1_2/DQA_34 VMB_DQ35 DQB1_2/DQB_34 VMB_WDQS0
D17 A34 AB3 G7
MVREFDA DQA1_3/DQA_35 DDBIA0_0/QSA_0B/WDQSA_0 VMB_DQ36 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 VMB_WDQS1
A16 E30 AD6 K1
DQA1_4/DQA_36 DDBIA0_1/QSA_1B/WDQSA_1 VMB_DQ37 DQB1_4/DQB_36 DDBIB0_1/QSB_1B/WDQSB_1 VMB_WDQS2
F16 E26 AD1 P1
D15
DQA1_6/DQA_38 DDBIA0_3/QSA_3B/WDQSA_3
C20 AD3
DQB1_6/DQB_38 DDBIB0_3/QSB_3B/WDQSB_3
W4 QSB#[7..0]
C C200 E14 C16 VMB_DQ39 AD5 AC4 VMB_WDQS4 C
R84 EV@0.1u/10V_4 DQA1_7/DQA_39 DDBIA1_0/QSA_4B/WDQSA_4 VMB_DQ40 DQB1_7/DQB_39 DDBIB1_0/QSB_4B/WDQSB_4 VMB_WDQS5
F14 C12 AF1 AH3
EV@100/F_4 DQA1_8/DQA_40 DDBIA1_1/QSA_5B/WDQSA_5 VMB_DQ41 DQB1_8/DQB_40 DDBIB1_1/QSB_5B/WDQSB_5 VMB_WDQS6
D13 J11 AF3 AJ8
F12 F8 AF6 AM3
DQA1_10/DQA_42 DDBIA1_3/QSA_7B/WDQSA_7 VMB_DQ43 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7
A12 AG4
DQA1_11/DQA_43 VMB_DQ44 DQB1_11/DQB_43
D11 J21 AH5 T7 VMB_ODT0 <22>
DQA1_12/DQA_44 ADBIA0/ODTA0 VMB_DQ45 DQB1_12/DQB_44 ADBIB0/ODTB0
F10 G19 AH6 W7 VMB_ODT1 <22>
DQA1_13/DQA_45 ADBIA1/ODTA1 VMB_DQ46 DQB1_13/DQB_45 ADBIB1/ODTB1
A10 AJ4
+1.5V_GPU DQA1_14/DQA_46 VMB_DQ47 DQB1_14/DQB_46 VMB_CLKP0
C10 H27 AK3 L9 VMB_CLKP0 <22>
DQA1_15/DQA_47 CLKA0 VMB_DQ48 DQB1_15/DQB_47 CLKB0 VMB_CLKN0
G13 G27 AF8 L8 VMB_CLKN0 <22>
DQA1_16/DQA_48 CLKA0B VMB_DQ49 DQB1_16/DQB_48 CLKB0B
H13 AF9
DQA1_17/DQA_49 VMB_DQ50 DQB1_17/DQB_49 VMB_CLKP1
J13 J14 AG8 AD8 VMB_CLKP1 <22>
DQA1_18/DQA_50 CLKA1 VMB_DQ51 DQB1_18/DQB_50 CLKB1 VMB_CLKN1
H11 H14 AG7 AD7 VMB_CLKN1 <22>
R81 DQA1_19/DQA_51 CLKA1B VMB_DQ52 DQB1_19/DQB_51 CLKB1B
G10 AK9
EV@40.2/F_4 DQA1_20/DQA_52 VMB_DQ53 DQB1_20/DQB_52 VMB_RAS0#
G8 K23 AL7 T10 VMB_RAS0# <22>
DQA1_21/DQA_53 RASA0B VMB_DQ54 DQB1_21/DQB_53 RASB0B VMB_RAS1#
K9 K19 AM8 Y10 VMB_RAS1# <22>
MVREFSA DQA1_22/DQA_54 RASA1B VMB_DQ55 DQB1_22/DQB_54 RASB1B
K10 AM7
DQA1_23/DQA_55 VMB_DQ56 DQB1_23/DQB_55 VMB_CAS0#
G9 K20 AK1 W10 VMB_CAS0# <22>
DQA1_24/DQA_56 CASA0B VMB_DQ57 DQB1_24/DQB_56 CASB0B VMB_CAS1#
A8 K17 AL4 AA10 VMB_CAS1# <22>
C199 DQA1_25/DQA_57 CASA1B +1.5V_GPU VMB_DQ58 DQB1_25/DQB_57 CASB1B
C8 AM6
R82 EV@0.1u/10V_4 DQA1_26/DQA_58 VMB_DQ59 DQB1_26/DQB_58 VMB_CS0#
E8 K24 AM1 P10 VMB_CS0# <22>
EV@100/F_4 DQA1_27/DQA_59 CSA0B_0 VMB_DQ60 DQB1_27/DQB_59 CSB0B_0
A6 K27 AN4 L10
DQA1_28/DQA_60 CSA0B_1 VMB_DQ61 DQB1_28/DQB_60 CSB0B_1
C6 AP3
DQA1_29/DQA_61 VMB_DQ62 DQB1_29/DQB_61 VMB_CS1#
E6 M13 AP1 AD10 VMB_CS1# <22>
DQA1_30/DQA_62 CSA1B_0 R61 VMB_DQ63 DQB1_30/DQB_62 CSB1B_0
A5 K16 AP5 AC10
DQA1_31/DQA_63 CSA1B_1 EV@40.2/F_4 DQB1_31/DQB_63 CSB1B_1
MVREFDA L18 K21 U10 VMB_CKE0
MVREFDA CKEA0 CKEB0 VMB_CKE0 <22>
R80 EV@243/F_4 MVREFSA L20 J20 MVREFDB Y12 AA11 VMB_CKE1
MVREFSA CKEA1 MVREFDB CKEB1 VMB_CKE1 <22>
MVREFSB AA12
R79 EV@243/F_4 MVREFSB VMB_WE0#
L27 K26 N10 VMB_WE0# <22>
MEM_CALRN0 WEA0B C102 D3D WEB0B VMB_WE1#
N12 L15 AB11 VMB_WE1# <22>
R53 EV@243/F_4 MEM_CALRN1 WEA1B R66 EV@0.1u/10V_4 WEB1B
+1.5V_GPU AG12
MEM_CALRN2 EV@100/F_4 R46 *EV@10K_4
+3V_D
R77 EV@243/F_4 R63 EV@10K_4 AD28 VMB_MA13
GDDR5
M12 H23 T8
GDDR5
MEM_CALRP1 MAA0_8 TESTEN MAB0_8
M27 J19 W8
R78 EV@243/F_4 MEM_CALRP0 MAA1_8 MAB1_8
AH12 AK10
R51 EV@243/F_4 MEM_CALRP2 CLKTESTA R37 EV@10/F_4 R36 EV@51_4
AL10 AH11 MEM_RST# <22>
CLKTESTB DRAM_RST
B B
Note by AN_M96_C1 +1.5V_GPU
AL31 R31 R32 R50
RSVD *EV@0_4 *EV@0_4 EV@5.1K_4 C45
EV@120P/50V_4
6/9 stuff all for Park by AMD's suggestion EV@Park_M2 R68 EV@Park_M2
EV@40.2/F_4 5/17 Change the design
Place all these components very close to GPU

C82
R55 EV@0.1u/10V_4
EV@100/F_4
A A

PROJECT : ZQ9
www.vinafix.vn
1A
Madison/Park M2-MEM I/F
5 4 3 2 1
5 4 3 2 1
GPU_4(VGA)
U15F
U15E
For DDR3, MVDDQ = 1.5V (7.5A)
+1.5V_GPU MEM I/O +1.8V_GPU
PCIE (1.8V@400mA PCIE_VDDR) AB39 A3
PCIE_VDDR L43 EV@HCB1608KF-181T15/1.5A/180ohm_6 PCIE_VSS#1 GND#1
AC7 AA31 E39 A37
VDDR1#1 PCIE_VDDR#1 PCIE_VSS#2 GND#2
AD11 AA32 F34 AA16
AF7 AA33 F39 AA18
C195 C179 C194 C59 C148 VDDR1#3 PCIE_VDDR#3 C115 C523 C121 C125 C101 C522 C526 C518 PCIE_VSS#4 GND#4
AG10 AA34 G33 AA2
EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 VDDR1#4 PCIE_VDDR#4 EV@0.1u/10V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 PCIE_VSS#5 GND#5
AJ7 V28 G34 AA21
EV@10u/6.3V_6 EV@10u/6.3V_6 VDDR1#5 PCIE_VDDR#5 EV@0.1u/10V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@10u/6.3V_6 PCIE_VSS#6 GND#6
AK8 W29 H31 AA23
D VDDR1#6 PCIE_VDDR#6 PCIE_VSS#7 GND#7 D
AL9 W30 H34 AA26
G11 Y31 H39 AA28
G14 J31 AA6
VDDR1#9 PCIE_VSS#10 GND#10
G17 J34 AB12
VDDR1#10 +1V PCIE_VSS#11 GND#11
G20 G30 K31 AB15
C176 C141 C18 C64 C86 C184 VDDR1#11 PCIE_VDDC#1 PCIE_VSS#12 GND#12
G23
VDDR1#12 PCIE_VDDC#2
G31 (1.0V@1.1A PCIE_VDDC) K34
PCIE_VSS#13 GND#13
AB17
EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 G26 H29 K39 AB20
EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 VDDR1#13 PCIE_VDDC#3 PCIE_VSS#14 GND#14
G29 H30 L31 AB22
VDDR1#14 PCIE_VDDC#4 PCIE_VSS#15 GND#15
H10 J29 L34 AB24
VDDR1#15 PCIE_VDDC#5 C158 C167 C182 C187 C138 C178 C161 C188 PCIE_VSS#16 GND#16
J7 J30 M34 AB27
VDDR1#16 PCIE_VDDC#6 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 PCIE_VSS#17 GND#17
J9 L28 M39 AC11
VDDR1#17 PCIE_VDDC#7 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@10u/6.3V_6 PCIE_VSS#18 GND#18
K11 M28 N31 AC13
K13 N28 N34 AC16
K8 R28 P31 AC18
C191 C183 C144 C171 C192 C177 VDDR1#20 PCIE_VDDC#10 PCIE_VSS#21 GND#21
L12 T28 P34 AC2
EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 VDDR1#21 PCIE_VDDC#11 PCIE_VSS#22 GND#22
L16 U28 P39 AC21
EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 VDDR1#22 PCIE_VDDC#12 +VGPU_CORE PCIE_VSS#23 GND#23
L21 R34 AC23
VDDR1#23 PCIE_VSS#24 GND#24
L23
VDDR1#24 (30A or more) T31
PCIE_VSS#25 GND#25
AC26
L26 AA15 T34 AC28
VDDR1#25 CORE VDDC#1 PCIE_VSS#26 GND#26
L7 AA17 T39 AC6
VDDR1#26 VDDC#2 PCIE_VSS#27 GND#27
M11 AA20 U31 AD15
VDDR1#27 VDDC#3 C154 C147 C120 C118 C153 C92 C98 C157 C156 C108 PCIE_VSS#28 GND#28
N11 AA22 U34 AD17
C145 C186 C175 C170 C185 VDDR1#28 VDDC#4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 PCIE_VSS#29 GND#29
P7 AA24 V34 AD20
EV@1u/6.3V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 VDDR1#29 VDDC#5 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 PCIE_VSS#30 GND#30
R11 AA27 V39 AD22
EV@0.1u/10V_4 EV@0.1u/10V_4 VDDR1#30 VDDC#6 PCIE_VSS#31 GND#31
U11 AB16 W31 AD24
U7 AB18 W34 AD27
Y11 AB21 Y34 AD9
Y7 AB23 Y39 AE2
AB26 AE6
VDDC#11 GND#36
AB28 AF10
VDDC#12 C77 C74 C96 C114 C79 C85 C94 C133 C105 C84 GND#37
AC17 AF16
VDDC#13 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 GND#38
AC20 AF18
LEVEL VDDC#14 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 GND#39
AC22 AF21
(1.8V@110mA VDD_CT) TRANSLATION VDDC#15
VDDC#16
AC24 GND GND#40
GND#41
AG17
POWER
L5 EV@SBY100505T-121Y-N/300mA/120ohm_4 VDDC_CT AF26 AC27 F15 AG2
+1.8V_GPU VDD_CT#1 VDDC#17 GND#100 GND#42
AF27 AD18 F17 AG20
VDD_CT#2 VDDC#18 GND#101 GND#43
AG26 AD21 F19 AG22
C32 C81 C91 VDD_CT#3 VDDC#19 GND#102 GND#44
C AG27 AD23 F21 AG6 C
EV@10u/6.3V_6 EV@0.1u/10V_4 VDD_CT#4 VDDC#20 GND#103 GND#45
AD26 F23 AG9 PowerXpress control signal for Madsion and Park only
EV@1u/6.3V_4 VDDC#21 C106 C110 C112 C88 C95 C131 C134 C109 C124 C139 GND#104 GND#46
AF17 F25 AH21 If not used, can be disconnected.
I/O VDDC#22 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 GND#105 GND#47
(3.3V@60mA)) VDDC#23
AF20 F27
GND#106 GND#48
AJ10 PX_EN = LOW, turn on
+3V_D AF23 AF22 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 F29 AJ11
VDDR3#1 VDDC#24 GND#107 GND#49 PX_EN = HIGH, turn off
AF24 AG16 F31 AJ2
VDDR3#2 VDDC#25 GND#108 GND#50 PX_EN is used to turn ON/OFF some
AG23 AG18 F33 AJ28
C68 C76 C83 C73 VDDR3#3 VDDC#26 GND#109 GND#51 regulators for PowerXpress mode. An
AG24 AG21 F7 AJ6
EV@10u/6.3V_6 EV@1u/6.3V_4 VDDR3#4 VDDC#27 GND#110 GND#52 output high ‘3.3V’ will turn the regulators
AH22 F9 AK11
EV@1u/6.3V_4 EV@1u/6.3V_4 VDDC#28 GND#111 GND#53 OFF. An output low ‘0V’ will turn the
AH27 G2 AK31
VDDC#29 C111 C130 C113 C129 C164 C128 GND#112 GND#54
AF13 AH28 G6 AK7 regulators ON. PX_EN outputs low (0V)
VDDR4#4 VDDC#30 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 GND#113 GND#55
AF15 M26 H9 AL11 by default.
VDDR4#5 VDDC#31 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 GND#114 GND#56
AG13 N24 J2 AL14 If this signal is unused, it can be NC (not
L6 EV@SBY100505T-121Y-N/300mA/120ohm_4 VDDR4 VDDR4#7 VDDC#32 GND#115 GND#57
+1.8V_GPU AG15 N27 J27 AL17 connected) or connected to ground.
VDDR4#8 VDDC#33 GND#116 GND#58
R18 J6 AL2
VDDC#34 GND#117 GND#59
VDDC#35
R21 BIF_VDDC should be connected to VDDC if BACO feature not used. J8
GND#118 GND#60
AL20
C87 C97 AD12 R23 K14 AL21 R21 *EV@0_4
EV@1u/6.3V_4 VDDR4#1 VDDC#36 For BACO, refer to the databook GND#119 GND#61 +3V_D
AF11 R26 K7 AL23
EV@0.1u/10V_4 VDDR4#2 VDDC#37 GND#120 GND#62
AF12 T17 L11 AL26
VDDR4#3 VDDC#38 GND#121 GND#63 R15
AG11 T20 L17 AL32
VDDR4#6 VDDC#39 GND#122 GND#64 *EV@0_4
T22 L2 AL6
T24 L22 AL8
VDDC#41 PIN different between Broadway and Madison GND#124 GND#66
T27 L24 AM11
U16 L6 AM31
PCIE_PVDD VDDC#43 Pin Broadway Madison GND#126 GND#68
M20 U18 M17 AM9
NC_VDDRHA VDDC#44 GND#127 GND#69 Pin AL21 to Ground for Broadway
M21 U21 M22 AN11
R371 NC_VSSRHA VDDC#45 N27 VDDC BIF_VDDC GND#128 GND#70
U23 M24 AN2
U26 N16 AN30
*EV@0_4 VDDC#47 GND#130 GND#72
V12 V17 N18 AN6
PCIE_VDDR NC_VDDRHB VDDC#48 AL31 TS_A NC_TS_A GND#131 GND#73
U12 V20 N2 AN8
NC_VSSRHB VDDC#49 GND#132 GND#74
V22 N21 AP11
V24 N23 AP7
VDDC#51 AL21 GND PX_EN GND#134 GND#76
V27 N26 AP9
Y16 N6 AR5
PLL VDDC#53 GND#136 GND#78
(1.8V@40mA PCIE_PVDD) VDDC#54
Y18 R15
GND#137 GND#79
AW34
L42 EV@SBY100505T-121Y-N/300mA/120ohm_4 PCIE_PVDD AB37 Y21 R17 B11
+1.8V_GPU PCIE_PVDD VDDC#55 GND#138 GND#80
Y23 R2 B13
MPV18 VDDC#56 GND#139 GND#81
H7 Y26 R20 B15
B
C515 C519 C520 MPV18#1 VDDC#57 GND#140 GND#82 B
H8 Y28 R22 B17
EV@10u/6.3V_6 EV@0.1u/10V_4 MPV18#2 VDDC#58 GND#141 GND#83
R24 B19
EV@1u/6.3V_4 +VGPU_CORE GND#142 GND#84
R27 B21
SPV18 GND#143 GND#85
AM10
SPV18 (DDR3 1.12V@4A VDDCI) or more R6
GND#144 GND#86
B23
(1.8V@150mA MPV18) VDDCI#1
AA13 T11
GND#145 GND#87
B25
L17 EV@SBY100505T-121Y-N/300mA/120ohm_4 SPV10 AN9 AB13 T13 B27
+1.8V_GPU SPV10 VDDCI#2 GND#146 GND#88
AC12 T16 B29
VDDCI#3 C162 C119 C152 C169 C104 C163 C165 C155 C166 C168 GND#147 GND#89
AN10 AC15 T18 B31
C201 C196 C193 SPVSS VDDCI#4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 GND#148 GND#90
AD13 T21 B33
EV@10u/6.3V_6 EV@0.1u/10V_4 VDDCI#5 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 GND#149 GND#91
AD16 T23 B7
EV@1u/6.3V_4 VDDCI#6 GND#150 GND#92
M15 T26 B9
VDDCI#7 GND#151 GND#93
M16 U15 C1
VOLTAGE VDDCI#8 GND#153 GND#94
M18 U17 C39
SENESE VDDCI#9 GND#154 GND#95
(1.8V@75mA SPV18) VDDCI#10
M23 U2
GND#155 GND#96
E35
L7 EV@SBY100505T-121Y-N/300mA/120ohm_4 N13 +3V U20 E5
+1.8V_GPU VDDCI#11 GND#156 GND#97
T1 AF28 N15 U22 F11
FB_VDDC VDDCI#12 C93 C174 C132 GND#157 GND#98
N17 U24 F13
VDDCI#13 GND#158 GND#99
C44 C56
VDDCI#14
N20 EV@10u/6.3V_6 EV@10u/6.3V_6 5/24 stuff U27
GND#159
1
EV@10u/6.3V_6 AG28 N22 EV@10u/6.3V_6 U6
EV@0.1u/10V_4 FB_VDDCI ISOLATED VDDCI#15 GND#160
R12 V11
CORE I/O VDDCI#16 R13 R54 V16
GND#161
VDDCI#17 EV@0_6 GND#163
T3 AH29 R16 2 V18
120 ohm/300mA FB_GND VDDCI#18 GND#164
(1.0V@120mA SPV10) VDDCI#19
T12 V21
GND#165
+1V L10 EV@SBY100505T-121Y-N/300mA/120ohm_4 T15 V23
VDDCI#20 *EV@AO3413 GND#166
VDDCI#21
V15 0.5A V26
GND#167
Y13 Q3 W2
3
C46 C53 VDDCI#22 GND#168
+3V_D_S W6
EV@10u/6.3V_6 GND#169
Y15
EV@0.1u/10V_4 VDDC_SENSE/VSS_SENSE and EV@Park_M2 C66 C69 C78 GND#170
Y17
Spec: 0.15A GND#171
VDDCI_SENSE/VSS_SENSE route as differetial pair Y20
*EV@10u/6.3V_6 *EV@0.1u/10V_4 GND#172
Rating: 3A Y22 A39
*EV@1u/6.3V_4 GND#173 VSS_MECH#1
Y24 AW1
+3V GND#174 VSS_MECH#2
Y27 AW39
GPU all PWROK U13
GND#175 VSS_MECH#3
GND#152
V13
+3V +3V GND#162
R361 GPU +3V power EV@Park_M2
A EV@10K_4 R343 A
5/24 stuff *EV@0_6
1
R40
dGPU_PWROK <11> 5/13 change the enable signal *EV@4.7K_4
R363 R23 B-test
3
EV@10K_4 Fine-tune Power-on sequence 2 EV@0_6

3
2 Q7 *EV@AO3413 0.5A
EV@2N7002K Q2
3
3
R26 *EV@0_4 2 Q1
<35,39,40,43> MAINON
*EV@DTC144EUA
+3V_D
+1.8V_GPU 2 Q8 R22 *EV@0_4 C24 C26 C31 Spec: 0.15A
1
<11,42> dGPU_VRON
EV@DTC144EUA C30 Rating: 3A PROJECT :ZQ9
1
C3C *EV@1u/6.3V_4 *EV@10u/6.3V_6 *EV@0.1u/10V_4

*EV@1u/6.3V_4 Size Document Number Rev
1
1A
Madison/Park M2 (PWR/GND)
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
GPU_5(VGA) +1V
U15H (1.0V@110mA DPA_VDD10)
DPA_VDD10 L11 EV@SBY100505T-121Y-N/300mA/120ohm_4
DP C/D POWER DP A/B POWER
DPA_VDD18 AP20 AN24 DPA_VDD18 C47 C55 C49

DPC_VDD18#1 DPA_VDD18#1 EV@10u/6.3V_6 EV@0.1u/10V_4
AP21 DPC_VDD18#2 DPA_VDD18#2 AP24
EV@1u/6.3V_4
D D
DPA_VDD10 AP13 AP31 DPA_VDD10
DPC_VDD10#1 DPA_VDD10#1
AT13 DPC_VDD10#2 DPA_VDD10#2 AP32
AN17 AN27 DPA_VDD18 DPE_VDD18

+1.8V_GPU DPC_VSSR#1 DPA_VSSR#1
AP16 DPC_VSSR#2 DPA_VSSR#2 AP27
(1.8V@130mA DPA_VDD18) AP17 AP28 R28 R34 R366
DPC_VSSR#3 DPA_VSSR#3
AW14 DPC_VSSR#4 DPA_VSSR#4 AW24
L2 EV@SBY100505T-121Y-N/300mA/120ohm_4 DPA_VDD18 AW16 AW26 *EV@0_4 *EV@0_4 *EV@0_4
DPC_VSSR#5 DPA_VSSR#5 DPA_PVDD DPC_PVDD DPE_PVDD
C35 C43 C51 R25 R33

EV@10u/6.3V_6 EV@0.1u/10V_4 DPA_VDD18 AP22 AP25 DPA_VDD18
EV@1u/10V_6 DPD_VDD18#1 DPB_VDD18#1 *EV@0_4 *EV@0_4
AP23 DPD_VDD18#2 DPB_VDD18#2 AP26
DPB_PVDD DPD_PVDD
DPA_VDD10 AP14 AN33 DPA_VDD10

DPD_VDD10#1 DPB_VDD10#1
AP15 DPD_VDD10#2 DPB_VDD10#2 AP33
C AN19 DPD_VSSR#1 DPB_VSSR#1 AN29 C

AP18 DPD_VSSR#2 DPB_VSSR#2 AP29
AP19 DPD_VSSR#3 DPB_VSSR#3 AP30
AW20 DPD_VSSR#4 DPB_VSSR#4 AW30
AW22 DPD_VSSR#5 DPB_VSSR#5 AW32
R27 EV@150/F_4 DPCD_CALR AW18 AW28 DPAB_CALR R351 EV@150/F_4 +1.8V_GPU

DPCD_CALR DPAB_CALR
(1.8V@20mA DPA_PVDD)
DPA_PVDD L3 EV@SBY100505T-121Y-N/300mA/120ohm_4
DP E/F POWER DP PLL POWER
AH34 DPE_VDD18#1 DPA_PVDD AU28
DPE_VDD18 AJ34 AV27 C29 C38 C40
DPE_VDD18#2 DPA_PVSS EV@10u/6.3V_6 EV@0.1u/10V_4
EV@1u/6.3V_4
+1.8V_GPU
AL33 AV29 DPB_PVDD (1.8V@20mA DPB_PVDD)
DPE_VDD10 DPE_VDD10#1 DPB_PVDD L4 EV@SBY100505T-121Y-N/300mA/120ohm_4
AM33 DPE_VDD10#2 DPB_PVSS AR28
+1.8V_GPU (1.8V@400mA DPE/F_VDD18)
L40 EV@HCB1608KF-181T15/1.5A/180ohm_6 DPE_VDD18 C25 C28 C34
AN34 AU18 EV@10u/6.3V_6 EV@0.1u/10V_4
DPE_VSSR#1 DPC_PVDD EV@1u/6.3V_4
AP39 DPE_VSSR#2 DPC_PVSS AV17
B C511 C509 C510 AR39 +1.8V_GPU B
EV@0.1u/10V_4 EV@10u/6.3V_6 DPE_VSSR#3 DPC_PVDD
AU37 DPE_VSSR#4 (1.8V@20mA DPC_PVDD)
EV@1u/6.3V_4 AW35 L8 EV@SBY100505T-121Y-N/300mA/120ohm_4
DPE_VSSR#5
DPD_PVDD AV19
DPD_PVSS AR18
C36 C37 C503
AF34 EV@10u/6.3V_6 EV@0.1u/10V_4
DPE_VDD18 DPF_VDD18#1 EV@1u/6.3V_4
AG34 DPF_VDD18#2
+1V (1.0V@400mA DPE/F_VDD10) AM37 +1.8V_GPU
180 ohm/1.5A DPE_PVDD DPD_PVDD
DPE_PVSS AN38 (1.8V@20mA DPD_PVDD)
L13 EV@HCB1608KF-181T15/1.5A/180ohm_6 DPE_VDD10 L38 EV@SBY100505T-121Y-N/300mA/120ohm_4
AK33 DPF_VDD10#1
DPE_VDD10 AK34
C54 C67 C48 DPF_VDD10#2 C494 C504 C495
NC_DPF_PVDD AL38
EV@0.1u/10V_4 EV@10u/6.3V_6 AM35 EV@10u/6.3V_6 EV@0.1u/10V_4
EV@1u/6.3V_4 NC_DPF_PVSS EV@1u/6.3V_4
AF39 DPF_VSSR#1
AH39 (1.8V@40mA DPE/F_PVDD) +1.8V_GPU
DPF_VSSR#2 DPE_PVDD L39 EV@SBY100505T-121Y-N/300mA/120ohm_4
AK39 DPF_VSSR#3
AL34 DPF_VSSR#4
AM34 DPF_VSSR#5 C507 C505 C508
EV@10u/6.3V_6 EV@0.1u/10V_4
EV@1u/6.3V_4
A R362 EV@150/F_4 DPEF_CALR AM39 A
DPEF_CALR
EV@Park_M2
PROJECT : ZQ9
1A
<Doc>
5 4 3 2 1
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5 4 3 2 1
PIN STRAPS(VGA)
CONFIGURATION STRAPS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
+3V_D THEY MUST NOT CONFLICT DURING RESET
Size of the primary memory apertures GPIO[13:11]
R42 *EV@10K_4 STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS DEFAULT REMARK
<17> GPU_GPIO0
R39 *EV@10K_4
128 MB 000 0 = 50% TX OUTPUT SWING
<17> GPU_GPIO1
TX_PWRS_ENB GPIO0 1 = FULL TX OUTPUT SWING 0
D D
256MB 001 PCIE TRANSMITTER DE-EMPHASIS ENABLED

TX_DEEMPH_EN GPIO1 0 = TX DE-EMPHASIS DISABLED 0
R45 *EV@10K_4 1 = TX DE-EMPHASIS ENABLED
<17> GPIO3_SMBDAT
R48 *EV@10K_4 64 MB 010 Enable external BIOS ROM device
<17> GPIO4_SMBCLK
BIOS_ROM_EN GPIO_22_ROMCSB 0 - Disable external BIOS ROM device 0
5/17 Change for ROM table 1 - Enable external BIOS ROM device
R24 *EV@10K_4 32 MB 011

<17> GPU_GPIO13
ROMIDCFG[2:0] GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT 001 See ROM table
R20 *EV@10K_4
<17> GPU_GPIO12
R30 EV@10K_4 BIF_GEN2_EN_A GPIO2 0 = PCIE DEVICE AS 2.5GT/S CAPABLE 0
<17> GPU_GPIO11 More than 512 MB Not Supported 1 = PCIE DEVICE AS 5GT/S CAPABLE
R38 *EV@10K_4 GPIO_8_ROMSO GPIO8

<17> GPU_GPIO2
H2SYNC H2SYNC Reserved Only 0
GPIO_21_BB_EN GPIO21
R368 EV@10K_4
<17,23> EV_HSYNC
AUD[1:0]
R367 EV@10K_4 AUD[1] HSYNC 00: NO AUDIO FUNCTION.
<17,23> EV_VSYNC
01: AUDIO FOR DISPLAYPORT AND HDMI IF
AUD[0] VSYNC ADAPTER IS DETECTED. 11 See Audio table
R356 *EV@10K_4 10: AUDIO FOR DISPLAYPORT ONLY.
<17> V2SYNC
11: AUDIO FOR BOTH DISPLAYPORT AND HDMI.
GPIO_9_ROMSI GPIO9 0 = VGA controller capacity enable 0

C C
VIP_DEVICE_STRAP_ENA V2SYNC 0 = DRIVER would ignore the value sample on VHAD_0 during RESET. 0
EEPROM(VGA) 5/17 delete EEPROM DDR3 Memory Aperture size(GPU)
DDR3 Memory size

RAM_STRAP2 RAM_STRAP1 RAM_STRAP0
Vendor Vendor P/N STN B/S P/N
DVPDATA_2 DVPDATA_1 DVPDATA_0
1 1 0
Hynix
H5TQ1G63BFR-12C AKD5LZGTW04 (64M*16)
1 0 0
H5TQ2G63BFR-12C AKD5MGGTW03 (128M*16)
B 1 0 1 B
Thermal Sensor(VGA)
K4W1G1646E-HC12 AKD5LGGT506 (64M*16)
Vendor P/N Samsung 0 0 0
WINDBOND AL83L771K01
K4W2G1646B-HC12 AKD5MGGT500 (128m*16)
GMT AL000780000 USD0.16 0 0 1
23EY2387MA12-SZ AKD5LGGT700
0 1 0
+3V_D_S
AMD
+3V_D_S
R365 R364 ADDRESS: 98H C512 EV@0.1u/10V_4

EV@10K_4 *EV@10K_4
U13 Samsung - 1Gb +1.8V_GPU
<35> MXM_SMCLK12 8 SCLK VCC 1 GPU_D+ <17>

R345 *EV@10K_4
<17> RAM_STRAP2
C513
A
<35> MXM_SMDATA12 7 SDA DXP 2
R354 EV@10K_4 RAM_STRAP2 SET DDR3 Vendor A
EV@2200p/50V_4
<17> ALT#_GPIO17 6
ALERT# DXN
3
GPU_D- <17>
RAM_STRAP[1:0] SET SIZE.
<35> VGA_THERM# 4 5
OVERT# GND R344 *EV@10K_4
<17> RAM_STRAP1
EV@G780P81U R353 EV@10K_4
ADDRESS: 98H Quanta Computer Inc.
R346 *EV@10K_4
PROJECT :ZQ9
R355 EV@10K_4 Size Document Number Rev
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<17> RAM_STRAP0
1A
Strip/Thermal
5 4 3 2 1
5 4 3 2 1
<18> VMB_DQ[63..0]
VMB_DQ[63..0] CHANNEL B: 512MB DDR3 (16*64M*4pcs)
<18> VMB_DM[7..0]
VMB_DM[7..0]
VMB_RDQS[7..0]
Park, M92M Use Channel B Memory Interface Only
<18> VMB_RDQS[7..0] QSA[7..0]
VMB_WDQS[7..0] QSA#[7..0]
<18> VMB_WDQS[7..0]
U4 U16 U14 U2
VREFC_VMB1 M8 E3 VMB_DQ24 VREFC_VMB2 M8 E3 VMB_DQ20 VREFC_VMB3 M8 E3 VMB_DQ32 VREFC_VMB4 M8 E3 VMB_DQ46

VREFD_VMB1 VREFCA DQL0 VMB_DQ26 VREFD_VMB2 VREFCA DQL0 VMB_DQ18 VREFD_VMB3 VREFCA DQL0 VMB_DQ37 VREFD_VMB4 VREFCA DQL0 VMB_DQ42
H1 F7 H1 F7 H1 F7 H1 F7
VREFDQ DQL1 VMB_DQ31 VREFDQ DQL1 VMB_DQ16 VREFDQ DQL1 VMB_DQ35 VREFDQ DQL1 VMB_DQ47
F2 F2 F2 F2
VMB_MA0 DQL2 VMB_DQ27 VMB_MA0 DQL2 VMB_DQ21 VMB_MA0 DQL2 VMB_DQ36 VMB_MA0 DQL2 VMB_DQ41
N3 F8 N3 F8 N3 F8 N3 F8
<18>
<18>
<18>
VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA1
VMB_MA2
VMB_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMB_DQ30
VMB_DQ28
VMB_DQ29
3 VMB_MA1
VMB_MA2
VMB_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMB_DQ19
VMB_DQ22
VMB_DQ17
2 VMB_MA1
VMB_MA2
VMB_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMB_DQ33
VMB_DQ38
VMB_DQ34
4 VMB_MA1
VMB_MA2
VMB_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMB_DQ45
VMB_DQ40
VMB_DQ44
5
<18> VMB_MA3 N2 G2 N2 G2 N2 G2 N2 G2
D
VMB_MA4 A3 DQL6 VMB_DQ25 VMB_MA4 A3 DQL6 VMB_DQ23 VMB_MA4 A3 DQL6 VMB_DQ39 VMB_MA4 A3 DQL6 VMB_DQ43 D
<18> VMB_MA4 P8 H7 P8 H7 P8 H7 P8 H7
VMB_MA5 A4 DQL7 VMB_MA5 A4 DQL7 VMB_MA5 A4 DQL7 VMB_MA5 A4 DQL7
<18> VMB_MA5 P2 P2 P2 P2
VMB_MA6 A5 VMB_MA6 A5 VMB_MA6 A5 VMB_MA6 A5
<18> VMB_MA6 R8 R8 R8 R8
VMB_MA7 A6 VMB_DQ3 VMB_MA7 A6 VMB_DQ15 VMB_MA7 A6 VMB_DQ63 VMB_MA7 A6 VMB_DQ50
<18> VMB_MA7 R2 D7 R2 D7 R2 D7 R2 D7
VMB_MA8 A7 DQU0 VMB_DQ6 VMB_MA8 A7 DQU0 VMB_DQ10 VMB_MA8 A7 DQU0 VMB_DQ59 VMB_MA8 A7 DQU0 VMB_DQ55
<18> VMB_MA8 T8 C3 T8 C3 T8 C3 T8 C3
VMB_MA9 A8 DQU1 VMB_DQ0 VMB_MA9 A8 DQU1 VMB_DQ14 VMB_MA9 A8 DQU1 VMB_DQ60 VMB_MA9 A8 DQU1 VMB_DQ48
R3 C8 R3 C8 R3 C8 R3 C8
<18>
<18>
<18>
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA10
VMB_MA11
VMB_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMB_DQ4
VMB_DQ2
VMB_DQ5
0 VMB_MA10
VMB_MA11
VMB_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMB_DQ9
VMB_DQ12
VMB_DQ8
1 VMB_MA10
VMB_MA11
VMB_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMB_DQ56
VMB_DQ62
VMB_DQ57
7 VMB_MA10
VMB_MA11
VMB_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMB_DQ52
VMB_DQ51
VMB_DQ54
6
<18> VMB_MA12 N7 A2 N7 A2 N7 A2 N7 A2
VMB_MA13 A12/BC DQU5 VMB_DQ1 VMB_MA13 A12/BC DQU5 VMB_DQ13 VMB_MA13 A12/BC DQU5 VMB_DQ61 VMB_MA13 A12/BC DQU5 VMB_DQ49
<18> VMB_MA13 T3 B8 T3 B8 T3 B8 T3 B8
A13 DQU6 VMB_DQ7 A13 DQU6 VMB_DQ11 A13 DQU6 VMB_DQ58 A13 DQU6 VMB_DQ53
T7 A3 T7 A3 T7 A3 T7 A3
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 M7 M7 M7
A15 +1.5V_GPU A15 +1.5V_GPU A15 +1.5V_GPU A15 +1.5V_GPU
VMB_BA0 M2 B2 VMB_BA0 M2 B2 VMB_BA0 M2 B2 VMB_BA0 M2 B2

<18> VMB_BA0 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2
VMB_BA1 N8 D9 VMB_BA1 N8 D9 VMB_BA1 N8 D9 VMB_BA1 N8 D9
<18> VMB_BA1 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
VMB_BA2 M3 G7 VMB_BA2 M3 G7 VMB_BA2 M3 G7 VMB_BA2 M3 G7
<18> VMB_BA2 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2 K2
VDD#K2 VDD#K2 VDD#K2 VDD#K2
K8 K8 K8 K8
VDD#K8 VDD#K8 VDD#K8 VDD#K8
N1 N1 N1 N1
VMB_CLKP0 VDD#N1 VMB_CLKP0 VDD#N1 VMB_CLKP1 VDD#N1 VMB_CLKP1 VDD#N1
<18> VMB_CLKP0 J7 N9 J7 N9 <18> VMB_CLKP1 J7 N9 J7 N9
VMB_CLKN0 CK VDD#N9 VMB_CLKN0 CK VDD#N9 VMB_CLKN1 CK VDD#N9 VMB_CLKN1 CK VDD#N9
<18> VMB_CLKN0 K7 R1 K7 R1 <18> VMB_CLKN1 K7 R1 K7 R1
VMB_CKE0 CK VDD#R1 VMB_CKE0 CK VDD#R1 VMB_CKE1 CK VDD#R1 VMB_CKE1 CK VDD#R1
<18> VMB_CKE0 K9 R9 K9 R9 <18> VMB_CKE1 K9 R9 K9 R9
CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU
VMB_ODT0 K1 A1 VMB_ODT0 K1 A1 VMB_ODT1 K1 A1 VMB_ODT1 K1 A1

<18> VMB_ODT0 ODT VDDQ#A1 ODT VDDQ#A1 <18> VMB_ODT1 ODT VDDQ#A1 ODT VDDQ#A1
VMB_CS0# L2 A8 VMB_CS0# L2 A8 VMB_CS1# L2 A8 VMB_CS1# L2 A8
<18> VMB_CS0# CS VDDQ#A8 CS VDDQ#A8 <18> VMB_CS1# CS VDDQ#A8 CS VDDQ#A8
VMB_RAS0# J3 C1 VMB_RAS0# J3 C1 VMB_RAS1# J3 C1 VMB_RAS1# J3 C1
<18> VMB_RAS0# RAS VDDQ#C1 RAS VDDQ#C1 <18> VMB_RAS1# RAS VDDQ#C1 RAS VDDQ#C1
VMB_CAS0# K3 C9 VMB_CAS0# K3 C9 VMB_CAS1# K3 C9 VMB_CAS1# K3 C9
<18> VMB_CAS0# CAS VDDQ#C9 CAS VDDQ#C9 <18> VMB_CAS1# CAS VDDQ#C9 CAS VDDQ#C9
VMB_WE0# L3 D2 VMB_WE0# L3 D2 VMB_WE1# L3 D2 VMB_WE1# L3 D2
<18> VMB_WE0# WE VDDQ#D2 WE VDDQ#D2 <18> VMB_WE1# WE VDDQ#D2 WE VDDQ#D2
E9 E9 E9 E9
VDDQ#E9 VDDQ#E9 VDDQ#E9 VDDQ#E9
F1 F1 F1 F1
VMB_RDQS3 VDDQ#F1 VMB_RDQS2 VDDQ#F1 VMB_RDQS4 VDDQ#F1 VMB_RDQS5 VDDQ#F1
F3 H2 F3 H2 F3 H2 F3 H2
VMB_RDQS0 DQSL VDDQ#H2 VMB_RDQS1 DQSL VDDQ#H2 VMB_RDQS7 DQSL VDDQ#H2 VMB_RDQS6 DQSL VDDQ#H2
C7 H9 C7 H9 C7 H9 C7 H9
DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9
VMB_DM3 E7 A9 VMB_DM2 E7 A9 VMB_DM4 E7 A9 VMB_DM5 E7 A9

VMB_DM0 DML VSS#A9 VMB_DM1 DML VSS#A9 VMB_DM7 DML VSS#A9 VMB_DM6 DML VSS#A9
C D3 B3 D3 B3 D3 B3 D3 B3 C
DMU VSS#B3 DMU VSS#B3 DMU VSS#B3 DMU VSS#B3
E1 E1 E1 E1
VSS#E1 VSS#E1 VSS#E1 VSS#E1
G8 G8 G8 G8
VMB_WDQS3 VSS#G8 VMB_WDQS2 VSS#G8 VMB_WDQS4 VSS#G8 VMB_WDQS5 VSS#G8
G3 J2 G3 J2 G3 J2 G3 J2
VMB_WDQS0 DQSL VSS#J2 VMB_WDQS1 DQSL VSS#J2 VMB_WDQS7 DQSL VSS#J2 VMB_WDQS6 DQSL VSS#J2
B7 J8 B7 J8 B7 J8 B7 J8
DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8
M1 M1 M1 M1
VSS#M1 VSS#M1 VSS#M1 VSS#M1
M9 M9 M9 M9
VSS#M9 VSS#M9 VSS#M9 VSS#M9
P1 P1 P1 P1
MEM_RST# VSS#P1 MEM_RST# VSS#P1 MEM_RST# VSS#P1 MEM_RST# VSS#P1
T2 P9 T2 P9 T2 P9 T2 P9
<18> MEM_RST# RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
VMB_ZQ1 VSS#T1 VMB_ZQ2 VSS#T1 VMB_ZQ3 VSS#T1 VMB_ZQ4 VSS#T1
L8 T9 L8 T9 L8 T9 L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
B1 B1 B1 B1
VSSQ#B1 VSSQ#B1 VSSQ#B1 VSSQ#B1
B9 B9 B9 B9
R85 VSSQ#B9 R374 VSSQ#B9 R348 VSSQ#B9 R64 VSSQ#B9
D1 D1 D1 D1
VSSQ#D1 VSSQ#D1 VSSQ#D1 VSSQ#D1
EV@240/F_4 D8 EV@240/F_4 D8 EV@240/F_4 D8 EV@240/F_4 D8
VSSQ#D8 VSSQ#D8 VSSQ#D8 VSSQ#D8
E2 E2 E2 E2
VSSQ#E2 VSSQ#E2 VSSQ#E2 VSSQ#E2
J1 E8 J1 E8 J1 E8 J1 E8
NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8
L1 F9 L1 F9 L1 F9 L1 F9
NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9
J9 G1 J9 G1 J9 G1 J9 G1
NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1
L9 G9 L9 G9 L9 G9 L9 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
EV@VRAM _DDR3 EV@VRAM _DDR3 EV@VRAM _DDR3 EV@VRAM _DDR3
BOT Down TOP Down TOP Up BOT Up
Group-B0 VREF Group-B1 VREF

+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU
B B
R379 R76 R372 R383 R17 R369 R43 R19

EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4
VREFC_VMB1 VREFD_VMB1 VREFC_VMB2 VREFD_VMB2 VREFC_VMB3 VREFD_VMB3 VREFC_VMB4 VREFD_VMB4
R384 C542 R75 C140 R373 C535 R382 C540 R16 C21 R370 C521 R44 C61 R18 C22
EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4
EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4
Group-B0 decoupling CAP Group-B1 decoupling CAP MEM_B1 CLK

MEM_B0 CLK
+1.5V_GPU +1.5V_GPU
VMB_CLKP1
VMB_CLKP0 VMB_CLKN1
C532 C525 C536 C533 C531 C215 C20 C530 C16 C216 C214 C23 C516 C143 C39 C499
VMB_CLKN0 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4
EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 R350 R349
EV@56.2/F_4
R381 R380 EV@56.2/F_4
EV@56.2/F_4 +1.5V_GPU +1.5V_GPU
EV@56.2/F_4
A C493 A
C534 C17 C217 C146 C524 C142 C218 C19 C541 C27 C500 C33 C517 C529 C42 C537 EV@0.01u/16V_4
C545 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4
EV@0.01u/16V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4
+1.5V_GPU +1.5V_GPU
C527 C173 C543 C544 C528 C498 C149 C52 C496 C497
EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6
PROJECT : ZQ9
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EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6
1A
MEMORY 2 channel B
5 4 3 2 1
1 2 3 4 5 6 7 8
CRT Switch CRT

C272 0.1u/10V_4_X7R
IV@ 0_ohm Resistor place close to Joint-Point F2

D16 SSM22LLPT CRTVDD5
16
2 1
EV@ INT_CRT_RED R95 IV@0_4 VGA_RED
+5V
SMD1206P110TFT
CN8
CRT-CONN
<8> INT_CRT_RED
INT_CRT_GRN R94 IV@0_4 VGA_GRN 6
<8> INT_CRT_GRN
INT_CRT_BLU R93 IV@0_4 VGA_BLU VGA_RED L27 BLM18BA750SN1D/0.3A/75ohm_6 CRT_R1 1 11 CRT_11 T22
<8> INT_CRT_BLU
7
RN7 IV@0_4P2R VGA_GRN L26 BLM18BA750SN1D/0.3A/75ohm_6 CRT_G1 2 12 DDCDAT_1
INT_VSYNC 1 2 VSYNC 8
<8> INT_VSYNC
INT_HSYNC 3 4 HSYNC VGA_BLU L25 BLM18BA750SN1D/0.3A/75ohm_6 CRT_B1 3 13 CRTHSYNC
<8> INT_HSYNC
9
RN8 IV@0_4P2R 4 14 CRTVSYNC
A A
INT_CRT_DDCDAT 1 2 CRTDDATA R189 R177 R165 C322 C308 C293 C637 C647 C653 10
<8> INT_CRT_DDCDAT
INT_CRT_DDCCLK 3 4 CRTDCLK 5 15 DDCCLK_1
<8> INT_CRT_DDCCLK
150/F_4 150/F_4 150/F_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4
17
EV_CRT_BLU R391 EV@0_4 VGA_BLU
<17> EV_CRT_BLU
EV_CRT_GRN R397 EV@0_4 VGA_GRN
<17> EV_CRT_GRN
EV_CRT_RED R399 EV@0_4 VGA_RED
<17> EV_CRT_RED
RN15 EV@0_4P2R
EV_HSYNC 1 2 HSYNC
<17,21> EV_HSYNC
EV_VSYNC 3 4 VSYNC
<17,21> EV_VSYNC
RN16 EV@0_4P2R 6/21 change to 0 ohm
+3V
EV_CRTDCLK 1 2 CRTDCLK
<17> EV_CRTDCLK
EV_CRTDDAT 3 4 CRTDDATA C301 U23
<17> EV_CRTDDAT
CRTVDD5 1 16 CRT_VSYNC2 R458 0_4 CRTVSYNC C661 *.1u/10V_4 CRTVDD5
0.1u/10V_4_X7R VCC_SYNC SYNC_OUT2 CRT_HSYNC2 R457 0_4 CRTHSYNC
14
SYNC_OUT1 C620 *10p/50V_4 CRTVSYNC
7
C632 .22u/25V_6 CRT_BYP VCC_DDC
8
BYP VSYNC CRTVDD5 C619 *10p/50V_4 CRTHSYNC
15
SYNC_IN2 HSYNC +3V
+3V 2 13
VCC_VIDEO SYNC_IN1 C631 10p/50V_4 DDCCLK_1
C315 R452 R476
CRT_R1 3 10 CRTDCLK R462 2.7K_4 C646 10p/50V_4 DDCDAT_1
0.1u/10V_4_X7R CRT_G1 VIDEO_1 DDC_IN1 CRTDDATA R469 2.7K_4 2.7K_4 2.7K_4
4 11
CRT_B1 VIDEO_2 DDC_IN2
5
VIDEO_3 DDCCLK_1
9
DDC_OUT1 DDCDAT_1
6 12
GND DDC_OUT2
CM2009-02QR
B B
LVDS LVDS LCD Power

+3V VIN
+3V
C8 C7
C2 C3
0.1u/10V_4_X7R C1 U1
1000p/50V_4 4.7u/25V_8 1000p/50V_4
1U/6.3V_4 6 1 LCDVCC
IN OUT
5/7 add 4
IN GND
2
C6 C5 C9 C10 C4
C14
C11 LVDS_VDDEN 3 5
*1u/6.3V_4 *1u/6.3V_4 VIN ON/OFF GND *.1u/10V_4 *2.2u/10V_8 0.1u/10V_4_X7R.01u/25V_4 22u/6.3V_8
0.8A AAT4280-4
R8 *SHORT0805 CN5
R14 *SHORT0805 INVCC0 1
R11 1 R4
2
LCDVCC 0_6 2
3
3
4
4 100K_4
5
5
0_ohm Resistor place close to Joint-Point R9 2.2K_4 LCD_EDIDCLK
6
7
6
+3V 7
R10 2.2K_4 LCD_EDIDDATA 8
RN1 EV@0_4P2R 8
9
EV_LVDS_DDCCLK LCD_EDIDCLK TXLOUT0- 9
<17> EV_LVDS_DDCCLK 1 2 10
EV_LVDS_DDCDAT LCD_EDIDDATA TXLOUT0+ 10
<17> EV_LVDS_DDCDAT 3 4 11
RN14 EV@0_4P2R 11
12
EV_LVDS_VDDEN LVDS_VDDEN TXLOUT1- 12
<17> EV_LVDS_VDDEN 1 2 13
EV_LVDS_BLON LVDS_BLON TXLOUT1+ 13
<17> EV_LVDS_BLON 3 4 14
14
15
TXLOUT2- 15
16
RN9 IV@0_4P2R TXLOUT2+ 16
C
INT_LVDS_EDIDCLK 1 2 LCD_EDIDCLK
5/7 add 17
18
17 Backlight Control C
<8> INT_LVDS_EDIDCLK 18
INT_LVDS_EDIDDATA 3 4 LCD_EDIDDATA TXLCLKOUT- 19
<8> INT_LVDS_EDIDDATA 19
RN6 IV@0_4P2R TXLCLKOUT+ 20
C12 C13 20
INT_LVDS_DIGON 1 2 LVDS_VDDEN 21
<8> INT_LVDS_DIGON 21
INT_LVDS_BLON 3 4 LVDS_BLON *1u/6.3V_4 *1u/6.3V_4 CCD-USB USBP8-_R 22 +3VPCU
<8> INT_LVDS_BLON 22
USBP8+_R 23
23
24
24
+3V 25
EV_TXLCLKOUT- RN5 EV@0_4P2R TXLCLKOUT- R5 0_6 CCD_PWR 25 R375
<17> EV_TXLCLKOUT- 1 2 26
EV_TXLCLKOUT+ TXLCLKOUT+ 26 *100K_4
<17> EV_TXLCLKOUT+ 3 4 27 34
EV_TXLOUT0- RN2 EV@0_4P2R TXLOUT0- 27 34
<17> EV_TXLOUT0- 1 2 28 LID591# <35>
EV_TXLOUT0+ TXLOUT0+ LVDS_BRIGHT R6 28
<17> EV_TXLOUT0+ 3 4 29 31
EV_TXLOUT1- RN3 EV@0_4P2R TXLOUT1- BL_ON BLM15AG121SS1/0.5A/120ohm_4 29 31
<17> EV_TXLOUT1- 1 2 30
EV_TXLOUT1+ TXLOUT1+ 30
3 4
<17> EV_TXLOUT1+
<17> EV_TXLOUT2-
EV_TXLOUT2- RN4 1 2 EV@0_4P2R TXLOUT2- LVDS LID591#,EC intrnal PU
EV_TXLOUT2+ TXLOUT2+ +3V
<17> EV_TXLOUT2+ 3 4 CCD +3V-current budget 0.2A
1
INT_TXLCLKOUT+ RN10 1 2 IV@0_4P2R TXLCLKOUT+
<8> INT_TXLCLKOUT+
INT_TXLCLKOUT- 3 4 TXLCLKOUT- 5/21 Change the LVDS connector and swap D14
<8> INT_TXLCLKOUT-
INT_TXLOUT0+ RN13 1 2 IV@0_4P2R TXLOUT0+ BAS316
<8> INT_TXLOUT0+
INT_TXLOUT0- 3 4 TXLOUT0-
<8> INT_TXLOUT0-
INT_TXLOUT1+ RN12 1 2 IV@0_4P2R TXLOUT1+ R2 *0_4 R376
<8> INT_TXLOUT1+
2
INT_TXLOUT1- 3 4 TXLOUT1-
<8> INT_TXLOUT1-
INT_TXLOUT2+ RN11 1 2 IV@0_4P2R TXLOUT2+ L1 R377 10K_4
<8> INT_TXLOUT2+
INT_TXLOUT2- 3 4 TXLOUT2- 2 1 USBP8+_R BL_ON
<8> INT_TXLOUT2- <10> USBP8+ 2 1
3 4 USBP8-_R 10K_4
<10> USBP8-
3
3 4
RFCMF1632100M3T/200mA/90ohm
3
R7 EV@0_4 LVDS_BRIGHT R3 *0_4
<35> CONTRAST
R12 *0_4 BL# 2
<17> EV_LVDS_BRIGHT
2 EC_FPBACK# <35>
3
R13 IV@0_4 Q10
<8> INT_LVDS_BRIGHT
2N7002K Q9
DTC144EUA
1
+3VPCU LVDS_BLON 2
Q11
D R378 2N7002K D
1
C491 0.1u/10V_4_X7R 100K_4
1
2 LID591#
HE1
2
PT3661-BB
3
PT3661-BB : AL003661003 D13

EM-6781-T3 : AL006781000 *VPORT_6
PROJECT : ZQ9
www.vinafix.vn
1

1A
Lid Switch (Hall sensor) CRT/LVDS/CAMERA/LID
1 2 3 4 5 6 7 8
5 4 3 2 1
SW@HDMI-detect
+3V +3V
I@ HDMI LEVEL SHIFTER
<9> HDMI_HPD_PCH#
R282 *0_4 To MXM
R278 R277
+3V 10K_4 EV@10K_4
HDMI_MB_HP
HDMI_DDCDATA_MB HDMI_HPD_EC# HDMI_HP_EV <17>
<35> HDMI_HPD_EC#
HDMI_DDCCLK_MB
IV@
3
C346 C667 C349 C350 C666 +3V R219 *4.7K_4 HDMI_HPD_EC# +5V
IV@2.2u/6.3V_6 IV@.1u/10V_4 IV@.1u/10V_4 IV@.1u/10V_4 IV@.1u/10V_4 DDCBUF_EN

D
EV@ CFG
+3V +3V R283
2
6/11 change the P/N
D
3
Active Buffer *10K_4 Q21
close to pin2/11/15/21/26/33/40/46 EV@2N7002D
+3V
1
HDMI_MB_HP
36
35
34
33
32
31
30
29
28
27
26
25
U6 2
CCT2
CCT1
OE#
HPD_SINK
SDA_SINK
SCL_SINK
GND
VCC
DDC_EN
GND
GND
VCC
C341 C321 Q20
2N7002D
from PCH
1
IV@.1u/10V_4 *IV@.1u/10V_4 37 24 6/11 change the P/N
5/19 stuff GND GND MB_HDMITX0N
<8> INT_HDMITX0N 38 23
IN_D1- OUT_D1- MB_HDMITX0P
<8> INT_HDMITX0P 39 22
IN_D1+ OUT_D1+
+3V 40 21 +3V
VCC VCC MB_HDMITX2N
IN_D2- OUT_D2- MB_HDMITX2P
42 19
<8> INT_HDMITX2P
43
IN_D2+
GND
OUT_D2+
GND
18
MB_HDMITX1P
I2C
<8> INT_HDMITX1P 44 17
IN_D3- OUT_D3- MB_HDMITX1N
IN_D3+ OUT_D3+
+3V 46
VCC VCC
15 +3V 5/14 change design
47 14 MB_HDMICLK+
<8> INT_HDMICLK+ IN_D4- OUT_D4-
48 13 MB_HDMICLK-
<8> INT_HDMICLK- IN_D4+ OUT_D4+ D19 2 1RB501V-40
HPDEN
49
HPD_S
SDA_S
SCL_S
GND +5V
REXT
TRIM
GND
GND
GND
VCC
VCC
NC
5/24 change to +3V +3V +3V
1
2
3
4
5
6
7
8
9
10
11
12
IV@PS8101 R528
+3V R236 1.5K_4
EV@1.5K_4
2
R547 4.7K_4 PC0 Q14 EV@BSN20
R548 *4.7K_4 +3V +3V
LS_REXT
PC0 1 3 HDMI_DDCCLK_MB
<17> MXM_DDCCK
R549 *4.7K_4 PC1 PC1
C C
R510 *4.7K_4 DDCBUF_EN from PCH R215 *EV@0_4
R217 *4.7K_4 R188 IV@499/F_4 6/18 stuff & unstuff
R509 *4.7K_4 CFG Control by pin4 HPDEN_R

R218 *4.7K_4 +5V D18 2 1RB501V-40
<8> INT_HDMI_HPD +3V
5/24 change to +3V +3V
R191 IV@0_4 HDMI_DDCDATA_SW R237 R527
<8> SDVO_CTRLDAT
EV@1.5K_4 1.5K_4
2
R190 IV@0_4 HDMI_DDCCLK_SW Q13 EV@BSN20
<8> SDVO_CTRLCLK
Equalization Control
PC0 internal PD 1 3 HDMI_DDCDATA_MB
<17> MXM_DDCDAT
PC1 PC0 PC1 internal PD
PIN4 PIN3 EQ Control DDCBUF_EN internal PD R486 IV@2.2K_4 R216 *EV@0_4
L L 8dB CFG internal PD +3V R485 IV@2.2K_4
L H 4dB 6/18 stuff & unstuff
H L 12dB DDC_EN internal PU
H H 0dB
B
AC-coupling CAP place close to HDMI-connector B
Switchable Graphic HDMI source EMI

HDMI connector
From GPU MB_HDMITX2P CN11
C347 EV@0.1u/10V_4_X7R MB_HDMITX0N 20
<17> HDMITX0N SHELL1
C348 EV@0.1u/10V_4_X7R MB_HDMITX0P R502 *100/F_4 MB_HDMITX2P 1
<17> HDMITX0P D2+
2
C343 EV@0.1u/10V_4_X7R MB_HDMITX2N MB_HDMITX2N MB_HDMITX2N D2 Shield
<17> HDMITX2N 3
C340 EV@0.1u/10V_4_X7R MB_HDMITX2P MB_HDMITX1P D2-
<17> HDMITX2P 4
MB_HDMITX1P D1+
5
C339 EV@0.1u/10V_4_X7R MB_HDMITX1P MB_HDMITX1N D1 Shield
<17> HDMITX1P 6
C337 EV@0.1u/10V_4_X7R MB_HDMITX1N R496 *100/F_4 MB_HDMITX0P D1-
<17> HDMITX1N 7
D0+
8
C333 EV@0.1u/10V_4_X7R MB_HDMICLK+ MB_HDMITX1N MB_HDMITX0N D0 Shield
<17> HDMICLK+ 9 23
C323 EV@0.1u/10V_4_X7R MB_HDMICLK- MB_HDMICLK+ D0- GND
<17> HDMICLK- 10
MB_HDMITX0P CK+
11 22
MB_HDMICLK- CK Shield GND
12
R488 R492 R494 R497 R501 R503 R505 R506 R507 *100/F_4 +5V CK-
13
EV@499/F_4 EV@499/F_4 EV@499/F_4 EV@499/F_4 CE Remote
14
EV@499/F_4 EV@499/F_4 EV@499/F_4 EV@499/F_4 MB_HDMITX0N F1 HDMI_DDCCLK_MB NC
15
SMD1206P110TFT HDMI_DDCDATA_MB DDC CLK
16
MB_HDMICLK+ D20 SSM22LLPT DDC DATA
2 1 17
3
5/7 change GND

18
R490 *100/F_4 HDMI_MB_HP R271 *Short_4 +5V
19
Q12 HP DET
21
MB_HDMICLK- SHELL2
+5V 2
R546 HDMI
R467 EV@2N7002D 100K_4
*EV@1M_4
1
6/11 change the P/N

A A

PROJECT : ZQ9
www.vinafix.vn
1A
HDMI (PS8101)
5 4 3 2 1
5 4 3 2 1
Giga-LAN BCM57780
+3V_S5
U8
15mil
+3V_S5 42 25 BIASVDD L30 BLM18AG601SN1_6
VDDO BIASVDDH C382 0.1u/10V_4_X7R
VAUX_12 6
VDDC XTALVDD L56 BLM18AG601SN1_6
15 14
VDDC XTALVDDH C685 0.1u/10V_4_X7R
D 41 D
L53 VDDC
15mil AVDDL 27 30 AVDDH L52 BLM18AG601SN1_6
VAUX_12 AVDDL AVDDH
C673 4.7U/6.3V_6 33
BLM18AG601SN1_6 C677 0.1u/10V_4_X7R 39
AVDDL
AVDDL
BCM57780
7mm X 7mm AVDDH
36 C674 0.1u/10V_4_X7R
48-Pin QFN C675 0.1u/10V_4_X7R

L54
15mil GPHY_PLLVDD 24 37
GPHY_PLLVDDL TRD3_N LAN_TRD3N <26>
C390 4.7U/6.3V_6 38
TRD3_P LAN_TRD3P <26>
BLM18AG601SN1_6 C388 0.1u/10V_4_X7R
35 LAN_TRD2N <26>
L55 TRD2_N
34
15mil PCIE_PLLVDD 18
TRD2_P LAN_TRD2P <26>
PCIE_PLLVDDL
31 LAN_TRD1N <26>
BLM18AG601SN1_6 C679 4.7U/6.3V_6 TRD1_N
32 LAN_TRD1P <26>
C681 0.1u/10V_4_X7R TRD1_P
21
PCIE_PLLVDDL
29 LAN_TRD0N <26>
TRD0_N
28 LAN_TRD0P <26>
TRD0_P
48 LAN_LINKLED#
LINKLED# LAN_LINKLED# <26>
47
SPD100LED#
46
SPD1000LED# LAN_ACTLED#
45 LAN_ACTLED# <26>
C404 0.1u/10V_4_X7R PCIE_RXP1_LAN_R 17 TRAFFICLED#
<10> PCIE_RX1+ PCIE_TXDP
C410 0.1u/10V_4_X7R PCIE_RXN1_LAN_R 16
<10> PCIE_RX1- PCIE_TXDN
22 5
<10> PCIE_TX1+ PCIE_RXDP MODE
23
<10> PCIE_TX1- PCIE_RXDN
<8,27> PCIE_WAKE# 4
C WAKE# C
2
<4,10,11,27,31,35> PLTRST# PERST#
20
<10> CLK_PCIE_LOM PCIE_REFCLK_P
19
<10> CLK_PCIE_LOM# PCIE_REFCLK_N
44 BCM_EEC
EECLK
43 BCM_EED
R272 1K/F_4 VMA_PRES EEDATA VAUX_12
+3V 40
R290 4.7K_4 LOW_PWR VMAIN_PRSNT
1
LOW_PWR
L32 4.7uh
SR_LX
11
8
Don't route under Choke.
SR_VFB
C420 33p_4 R286 200_4 XTALO 13
XTALI XTALO
12 10 +3V_S5
1
XTALI SR_VDDP
9
RDAC SR_VDD
1.2H Y2 R267 1.24K/F_4 26
RDAC
C687 C686 C418 C422
25MHz 10u/6.3V_6
4.7U/6.3V_6 0.1u/10V_4_X7R 0.1u/10V_4_X7R
2
C419 33p_4
R291 *4.7K_4 3 7
+3V_S5 CLK_REQ# NC
R292 *Short_4BCM_CLKREQ#
<10> CLK_PCIE_LAN_REQ#
GND
BCM57780
49
B B
6/18 change to use internal ROM

EEPROM
LAN POWER
+3V_S5
+3V_S5 VAUX_12 20mil

R287 R289
*1K_4 1K_4
C683 4.7U/6.3V_6 C680 4.7U/6.3V_6 U27
BCM_EED 5 1
C401 0.1u/10V_4_X7R C682 0.1u/10V_4_X7R BCM_EEC SDA A0
6 2
SCL A1
3
C678 0.1u/10V_4_X7R A2
7
R284 R294 WP
C399 0.1u/10V_4_X7R 4 8 +3V_S5
1K_4 *1K_4 GND VCC
*24LC02 C423
*0.1u/10V_4_X7R
A A
EEPROM Strapping
A version Still mount the EEPROM
EEPROM Type EECLK EEDATA
24LC02 1 1
Internal 1 0 PROJECT : ZQ9
www.vinafix.vn
1A
GLAN BCM57780
5 4 3 2 1
1 2 3 4 5 6 7 8
TRANSFORMER
U26
A A
1 TCT1 MCT1 24
2 23 X-TX0P
<25> LAN_TRD0P TD1+ MX1+
3 22 X-TX0N
<25> LAN_TRD0N TD1- MX1-
C361 C362
4 21 LAN_ACTLED# CN9
TCT2 MCT2 <25> LAN_ACTLED#
0.1u/10V_4_X7R 0.1u/10V_4_X7R 5 20 X-TX1P 9
<25> LAN_TRD1P TD2+ MX2+ YELLOW_N
6 19 X-TX1N +3V_S5 R250 220_8 LAN_ACT_LED_PWR 10
<25> LAN_TRD1N TD2- MX2- YELLOW_P
7 18 14 R265 *0_6
TCT3 MCT3 X-TX2P X-TX0P GND2 R235 *0_6
<25> LAN_TRD2P 8 TD3+ MX3+ 17 1 0+ GND1 13
9 16 X-TX2N X-TX0N 2
<25> LAN_TRD2N TD3- MX3- 0-
C364 C368 X-TX1P 3
X-TX2P 1+
10 TCT4 MCT4 15 4 2+
0.1u/10V_4_X7R 0.1u/10V_4_X7R 11 14 X-TX3P X-TX2N 5
<25> LAN_TRD3P TD4+ MX4+ 2-
12 13 X-TX3N X-TX1N 6
<25> LAN_TRD3N TD4- MX4- 1-
X-TX3P 7
X-TX3N 3+
8 3-
TRANSFORMER
<25> LAN_LINKLED#
R255 R256 R257 R258 LAN_LINKLED# 11
R263 220_8 LAN_LNK_LED_PWR GREEN_N
75/F_8 75/F_8 75/F_8 75/F_8 +3V_S5 12 GREEN_P
Delta LFE9276D-R (DB0ZY8LAN00) RJ45
B B
C672
1500p/3KV_18
LAN_ACTLED#
LAN_LINKLED#
C354 C384
*0.1u//50V_8 *0.1u//50V_8
C C
D D

PROJECT : ZQ9
www.vinafix.vn
1A
LAN Transformer and RJ45
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
MINI-CARD WLAN(MPC)
Debug Check LED signal. (active high or low) +3V +WL_VDD
+3.3V: 1000mA R556 *Short_4 CL_DATA1_WLAN
+3.3Vaux:330mA <10> PCI_RST#
<10> CLK_LPC_DEBUG
R306 *Short_4 CL_CLK1_WLAN H=7.0mm R303 *SHORT0805 +WL_VDD
CN13 LTS_AAA-PCI-046-K01
+1.5V:500mA
51 52 +WL_VDD
R561 *0_4 CL_RST1#_WLAN Reserved +3.3V C457 C458 C697 C432
<10> CL_RST1# 49 Reserved GND 50
R555 *0_4 CL_DATA1_WLAN 47 48 +1.5V 10u/6.3V_8 0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4
<10> CL_DATA1 Reserved +1.5V
R307 *0_4 CL_CLK1_WLAN 45 46
<10> CL_CLK1 Reserved LED_WPAN#
43 44 RF_LED#
Reserved LED_WLAN# RF_LED# <32>
+WL_VDD 41 42
Reserved LED_WWAN#
39 40
Reserved GND USB_Wifi+
A 37 38 A
Reserved USB_D+ USB_Wifi-
35 GND USB_D- 36
<10> PCIE_TX6+ 33 PETp0 GND 34 5/13 change to 6.3V
<10> PCIE_TX6- 31 PETn0 SMB_DATA 32
29 30 CLK_SDATA <3,14,15>
GND SMB_CLK CLK_SCLK <3,14,15>
27 GND +1.5V 28 +1.5V
25 26 +1.5V
<10> PCIE_RX6+ PERp0 GND
<10> PCIE_RX6- 23 PERn0 +3.3Vaux 24 +WL_VDD
21 22 PLTRST#
GND PERST# PLTRST# <4,10,11,25,31,35>
19 20 RF_EN <35>
UIM_C4 W_DISABLE#
17 18
UIM_C8 GND
A_LFRAME#_R R293 0_4
Debug
15 GND UIM_VPP 16 LPC_LFRAME# <9,35>
13 14 A_LAD3_R R288 0_4 C695 C684 C688
<10> CLK_PCH_SRC2 REFCLK+ UIM_RST LPC_LAD3 <9,35>
11 12 A_LAD2_R R285 0_4 1000p/50V_4 0.1u/10V_4 10u/6.3V_8
<10> CLK_PCH_SRC2# REFCLK- UIM_CLK LPC_LAD2 <9,35>
9 10 A_LAD1_R R281 0_4
GND UIM_DATA LPC_LAD1 <9,35>
7 8 A_LAD0_R R280 0_4
<10> PCIE_CLK_REQ2# CLKREQ# UIM_PWR LPC_LAD0 <9,35>
5 6 +1.5V
Reserved +1.5V
3 4 6/9 stuff all for debug
GND
GND
PCIE_WAKE#_R Reserved GND
1 WAKE# +3.3V 2 +WL_VDD
+WL_VDD
53
54
2
Q6 modify 10/19
*DTC144EUA
3 1 PCIE_WAKE#_R
<8,25> PCIE_WAKE#
B B
USB_Wifi+ R575 *0_4

USBP13+ <10,33>
USB_Wifi- R576 *0_4
USBP13- <10,33>
C C
D D

PROJECT : ZQ9
1A
MINI PCI-E card/TV
www.vinafix.vn
1 2 3 4 5 6 7 8
1 2 3 4
EE RETURN-PATH CAPACITORS
MAIN SATA HDD VIN +VGPU_CORE +5V
CN12 5/13 update the P/N and F/P

C426 0.1u/25V_4_X5R C514
23 *.1u/10V_4 C711 *.1u/10V_4
GND23 6/18 stuff for EMI
A A
GND1 1
2 SATA_TXP0_C C461 .01u/25V_4 SATA_TXP0 <9> C224 *0.1u/25V_4_X5R C670 *.1u/10V_4
RXP SATA_TXN0_C C459 .01u/25V_4
RXN 3 SATA_TXN0 <9>
GND2 4
5 SATA_RXN0 C456 .01u/25V_4 C718 .1u/10V_4
TXN SATA_RXN0_C <9>
6 SATA_RXP0 C453 .01u/25V_4 C669 *0.1u/25V_4_X5R
TXP SATA_RXP0_C <9>
GND3 7
C719 .1u/10V_4
8 C15 0.1u/25V_4_X5R
3.3V C720 .1u/10V_4
3.3V 9
10 6/18 stuff for EMI
3.3V 6/18 add for EMI
GND 11
12 +3V
GND +1.05V +5V_S5
GND 13
14 +5V_HDD
5V C506 .1u/10V_4
5V 15
16 C553 C704 *.1u/10V_4
5V 6/18 stuff for EMI
GND 17 *.1u/10V_4
RSVD 18
19 C359 *.1u/10V_4
B GND C479 .1u/10V_4 B
12V 20
12V 21
22 R550 *SHORT0805 6/18 stuff for EMI
12V +5V_HDD C462 *.1u/10V_4
+5V
GND24 24
C676 C386 C400 C398 C395 C392
MAIN_SATA + C489 *.1u/10V_4
5/25 reserve for EMI
*100u/6.3V_3528 10u/10V_6 *.1u/16V_4 *.1u/16V_4 .01u/25V_4 .01u/25V_4
6/21 add
5/27 cost down
ODD (SATA)
CN7
GND14 14
C C
GND 1
2 SATA_TXP1_C C317 .01u/25V_4 SATA_TXP1 <9>
A+ SATA_TXN1_C C310 .01u/25V_4
A- 3 SATA_TXN1 <9>
GND 4
5 SATA_RXN1 C304 .01u/25V_4
B- SATA_RXN1_C <9>
6 SATA_RXP1 C296 .01u/25V_4
B+ SATA_RXP1_C <9>
GND 7
+5V
8 SATA_DP R159 *1K_4
DP +5V_ODD R443 *SHORT0805
5V 9
5V 10
C263 C262 C254 C264 C252 C611
+
MD 11
GND 12
13 .01u/25V_4 .01u/25V_4 *.1u/16V_4 *.1u/16V_4 10u/10V_6 *100u/6.3V_3528
GND
GND15 15
5/27 cost down
SATA_ODD_H=7.7
D D

5/26 change the footprint
PROJECT : ZQ9
1A
SATA-HDD/ODD/USB-ESATA
1 2 3 4
www.vinafix.vn
5 4 3 2 1
Codec(ADO) HP <30> HP-R MUTE(AMP)

<30> HP-L
SENSEB
<30> HPOUT_JD
R313 5.1K/F_4
MIC1-VREFO <30>
ADOGND
D FRONT-L= (L+R)/2 Place next to pin 27 D
5/11 Del FRONT-R 5/11 update 6/21 change the P/N
Speaker C478 C477 C473 C476

ADOGND
FRONT-L
+ +
0.1u/10V_4 10u/6.3V_6 +5VA C474 U11 +5VA
2.2u/6.3V_6 2.2u/6.3V_6 MONO-OUT C471 0.47u/10V_6 ADOGND 4.7U/6.3V_6 2 8
Bypass VO2 INSPKR+ <30>
Place next to pin 25
FRONT-L C480 *0.47u/10V_6 FRONT-R-1 R315 22K/F_6 FRONT-R-2 4 7 ADOGND
IN- GND
C472 C475 C483 0.47u/10V_6 FRONT-R+1 R319 22K/F_6 FRONT-R+2
36
35
34
33
32
31
30
29
28
27
26
25
ADOGND 3 IN+ VDD 6
U10 C469 C470 C490
5/10 Add 1 5
FRONT-L
Sense B
HPOUT-L
CPVEE
CBP
MIC1-VREFO
AVSS1
AVDD1
FRONT-R
HPOUT-R
CBN
VREF
Change to 0.47U to reduce popping noise SHUTDOWN VO1 INSPKR- <30>
0.1u/10V_4 10u/6.3V_6 0.1u/10V_4 0.1u/10V_4 4.7U/6.3V_6
G1442P81U
MONO-OUT 37 24 ADOGND
MONO-OUT LINE1-R T29
ADOGND 6/18 change AMP & modify the circuit
+5VA 38 AVDD2 LINE1-L 23 T28
39 22 MIC1-R +3V R320 *100K_4
SURR-L MIC1-R MIC1-R <30>
C468 C466
10u/6.3V_6 0.1u/10V_4
ADOGND R309 20K/F_4 40 JDREF MIC1-L 21 MIC1-L
MIC1-L <30>
MIC R314 0_4
41 20 +3V_S5
SURR-R LINE2-VREFO
42 19 MIC2-VREFO
ADOGND
ADOGND AVSS2
ALC272X<LQFP-48> MIC2-VREFO
U29
5
Place next to pin 38 ANALOG 43
NC LINE1-VREFO
18 <35> AMP_MUTE# 1
4 R323 *10K_4
HP_MUTE# <30>
T27 44 17 MIC2_INT_R C463 1u/10V_6 MIC2_INTL1_R R308 1K_4 MIC2_INTL1 EAPD# 2
DMIC-CLK3/4 MIC2-R *TC7SH08FU C485
DIGITAL
3
C C
45 16 MIC2_INT_L C460 1u/10V_6
SPDIFO2 MIC2-L R316 *0_4 *4.7u/10V_6
46 15
DMIC-CLK1/2 LINE2-R
Split by DGND 47
EAPD
14
DMIC-1/2/GPIO0
DMIC-3/4/GPIO1
LINE2-L
48 13 SENSEA R305 20K/F_4 MIC1_JD
SDATA-OUT
SPDIFO1 Sense A MIC1_JD <30>
EAPD#
SDATA-IN
DVDD-IO
PCBEEP
RESET#
BIT-CLK
DVDD1
DVSS1
DVSS2
SYNC
Split by DGND
ANALOG
1
10
11
12
DIGITAL
1.6Vrms
+3V
PCBEEP C451 1u/10V_6 BEEP_1 R297 47K/F_4
SPKR <9>
C448 C447 C428 R296
4.7K_4
10u/6.3V_6 0.1u/10V_4 100p/50V_4
Place next to pin 1 5/24 Delete

+3V
C431 C441
PCH_AZ_CODEC_RST# <9>
B 0.1u/10V_4 10u/6.3V_6 B
C429
PCH_AZ_CODEC_SYNC <9>
C430 *22p/50V_4 *100p/50V_4
ACZ_SDIN0_R R551 22_4 Place next to pin 9

PCH_AZ_CODEC_SDIN0 <9>
PCH_AZ_CODEC_SDOUT <9>
PCH_AZ_CODEC_BITCLK <9>
C445 22p/50V_4
Power (ADO) INT MIC array

DIGITAL ANALOG Place in Bottom of codec
+5V L58 UPB201209T-310Y-N/6A/31ohm_8 CN4 R337
+5VA R553 0_4 1 MIC2_INTL1 MIC2-VREFO
U30 1
2
2
3
IN OUT
4 6/18 stuff for EMI C492 2.2K_4
R564 0_4
2 R563 0_4 INT_MIC *22P_4
GND R571 0_4
A A
1 5 R569 *29.4K/F_4 R311 *0_4
SHDN SET C464 *1000p/50V_4 5/12 update Mic Partnumber & Footprint
*G923-330T1UF C689 *1000p/50V_4
R566 + C709 C710 ADOGND
*10K/F_4
*10u/10V_3216 *0.1u/10V_4
C707 C708 ADOGND C467 .1U_4
+ R331 *0_4
Tied at one point only under Quanta Computer Inc.
*0.1u/10V_4 *10u/10V_3216 5/27 cost down the codec or near the codec
5/27 cost down ADOGND ADOGND PROJECT : ZQ9
ADOGND cap place close to MIC-connector 1A
C730, C787 close U37 pin3 and L65 REALTEK ALC663&888/MDC
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
MIC D10 BAS316
D11 BAS316
<29> MIC1-VREFO
Internal Speaker
Normal OPEN Jack
R325 R324
4.7K/F_4 4.7K/F_4
CN18 BLACK
1 7 CN16
D C482 4.7u/6.3V_6 MIC1_L2 R318 1K/F_4 MIC1_L3 L35 MIC1_L D
<29> MIC1-L 2
BLM15AG121SS1/0.5A/120ohm_4 6 <29> INSPKR- R572 *SHORT0603 R_SPK-_1 2
C481 4.7u/6.3V_6 MIC1_R2 R317 1K/F_4 MIC1_R3 L34 MIC1_R R570 *SHORT0603 R_SPK+_1 2
<29> MIC1-R 3 <29> INSPKR+ 1 1
BLM15AG121SS1/0.5A/120ohm_4 MIC1_JD 4
<29> MIC1_JD 8
INT_Speaker
5
MIC
C486 C484 C713 C714
Max. 100mVrms input for Mic-IN 470p/50V_4 470p/50V_4 *0.22u/25V_6 *0.22u/25V_6
MIC1_JD ADOGND
1
ADOGND
D21
*VPORT_6
ADOGND
C C
HP/SPDIF
<29> HP_MUTE#
BLACK
1 CN17 7
2
HP-L-2 R328 56/F_4 HPL-1 L37 BLM15AG121SS1/0.5A/120ohm_4 HPL_SYS 2

HP-R-2 R327 56/F_4 HPR-1 L36 BLM15AG121SS1/0.5A/120ohm_4 HPR_SYS 6
<29> HP-L 3 1 HP-L-2 3
4
Q23 R326 R329 C487 C488 <29> HPOUT_JD 8
*FDV301N 5
*1K_4 *1K_4 2200p/50V_4 2200p/50V_4 JA6331-0230T3B-8H
R322 0_6
ADOGND
ADOGND
HP_MUTE#
B B
2
<29> HP-R 3 1 HP-R-2
Q24
*FDV301N
R321 0_6
HPOUT_JD
1
D12
A *VPORT_6 A
2
ADOGND Quanta Computer Inc.
PROJECT : ZQ9
1A
AMP /AUDIO JACK CONN
5 4 3 2 1
www.vinafix.vn
A B C D E
CARD READER Controller 2 IN 1 CARD READER (SD/MMC) SD_WP
SD_CD#
11
12
4
CN3
SW COM
CD/SW
WP/SW
SD_DAT1 10
SD_DAT0 DATA1
9 DATA0
8 VSS2
4 SD_CLK 4
7 CLK
VCC_XD 6 VDD
5 VSS1
SD_CMD 3 CMD
GND1
SD_DAT3 2
GND
SD_DAT2 DATA3
1 DATA2
SD-CARD
13
14
5/10 Del R40001
VCC_XD
C442 C454
Clock input selection 4.7u/10V_6 0.1u/16V_4

'1' for 48MHz input [Default,Internal PU]
'0' for 12MHz input Main DFHS11FR011
C743 close PIN46, 47 Close to CN14 pin 14 & pin23
+1.8V_VDD
C708 close PIN48, 47 Second DFHS11FR033 4.7u CAP close to pin23
+3V_VDD T97
R554 *Short_4 XTALSEL C692 C694 T95 5/10 change Card Redaer conn
0.1u/16V_4 0.1u/16V_4 footpirnt sdcard-sdsn09-08-xa-11p-smt
3 3
XTALSEL
CRMD_N
DATA1
DATA0
CTRL1
CTRL3
NBMD
8/14 ZH7 remove R136, R591 and C775 5/10 Modify
R559 *100K_4
48
47
46
45
44
43
42
41
40
39
38
37
+3V_VDD U28
R562 *Short_4
<4,10,11,25,27,35> PLTRST#
CTRL0, CRTL 1 trace length shorter ,
GND
VDD
NBMD
VDDHM
TRIST
XTALSEL
CTRL1
CTRL3
DATA1
DATA0
DATA7
DATA6
C700 *0.47u/10V_6 and surround with GND. DATA0 SD_DAT0
+3V R557 *SHORT0603 +3V_VDD

C701 1 36 CTRL0 DATA1 SD_DAT1
GPON7 CTRL0
2 EXT48IN DATA5 35
4.7u/10V_6 3 34 CTRL2
R560 330_4 RSTN CTRL2 GPI4 DATA2 SD_DAT2
4 REXT GPI4 33
5 32 T89
VD33P DATA4 DATA3
<10> USBP12+ 6 DP DATA3 31
7 AU6437-GBL 30 DATA2 DATA3 SD_DAT3
<10> USBP12- DM DATA2
8 VS33P XDWPN 29
C698 C699 XI 9 28 GPI2
XO XI GPI2 T90
10 XO XDCEN 27
*5p/50V_4 *5p/50V_4 +1.8V_VDD 11 26 EEPDATA
VDD EEPDATA GPI1 T91
8/14 C707 close PIN11, 12
12 VDD GPI1 25
T92
Close to connector
SDWPEN
AGND5V
EEPCLK
CF_V33
VDDHM
XDCDN
VCC33
CTRL4
GND
VDD
V18
V33
2 2
13
14
15
16
17
18
19
20
21
22
23
24
crystal trace width needs at least 10 mils. 8/14 pin13 output 20mils
EEPCLK T94
C696
VCC_XD
C702 18p/50V_4 XI CTRL0 R300 SD_CLK

4.7u/10V_6 BLM15AG121SS1/0.5A/120ohm_4
Y7 R558 CTRL1 SD_WP C449

12MHz 270K_4 *10p/50V_4
*0_4 R552
VCC_XD
C703 18p/50V_4 XO CTRL2 SD_CMD

SD write protect
+1.8V_VDD 1:decided by SDWP[Default]
0:letting SD always CTRL3 SD_CD#
+3V_VDD +3V_VDD write-able
C690 C691
4.7u/10V_6 0.1u/16V_4
1 1
PROJECT : ZQ5
www.vinafix.vn
1A
AU6433 CardReader
A B C D E
5 4 3 2 1
LED
+3V_S5
D D
POWER Amber
5/13 Delete CAP & NUM LED +3V
LED3
R340 715/F_4 4 2
<35> SUSLED#
R342 20/F_4 3 1
<35> PWRLED#
Power LED LED1 Bule R1 182/F_4
LED_A/B
Blue
R339 *1M_4 +3VPCU
R336 *1M_4
+3VPCU
Battery Amber
LED4
R338 715/F_4 4 2
<35> BATLED1#
R335 20/F_4 3 1
C <35> BATLED0# C
LED_A/B
Blue
+3V
+3V
HDD WIFI LED
+3V
Amber
R333
LED5
5
10K/F_4 1
4 SATA_LED#_R LED2 Bule R341 182/F_4 R334 715/F_4
<27> RF_LED#
<9> SATA_ACT# 2
U12
3
*TC7SH08FU LED_AMBER
R332 *Short_4
B B
A A

PROJECT : ZQ9
1A
POWER/MMB/LAUNCH/LED
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
BLUETOOTH CONNECTOR for 2.0

USB +5V_S5
6/18 add
CN19
+3V_S5 1 3 BT_POWER_2
5
Q25 USB_BT+_R 4
C455 + C717 C715 USB_BT-_R 3
2
U9 AO3413 1000p/50V_4 BT_LED_2 2 7
2.2u/6.3V_6 T102 1 6
1U/6.3V_4 2 8 USBPWR1
IN1 OUT3 <35> BT_POWERON#
3 7 BT_CONN
IN2 OUT2 C693 C465 R574 0_4
OUT1 6
D + L59 C716 D
4 EN#
<35> USBON# 1000p/50V_4 USB_BT+_R *.01u/16V_4
1 GND 3 3 4 4
5 <10,27> USBP13+ 2 2 1 USB_BT-_R
OC# 330u/6.3V_6X5.7 <10,27> USBP13- 1
G547F2P81U *RFCMF1632100M3T/200mA/90ohm
R573 0_4
<10> USB_OC0#
CN14 BLUETOOTH CONNECTOR for 3.0
1 8 CN15
USBP1-_R 1 8 BT_POWER
2 2 7 7 +3V_S5 1 3 5
USBP1+_R 3 6
3 6 Q22 USBP4+_R 4
4 4 5 5 3
+ C705 C706 USBP4-_R
2
R310 *0_4 USB_MB_Turbo AO3413 1000p/50V_4 BT_LED 2 7
2.2u/6.3V_6 T101 1 6
<35> BT_POWERON#
L33 BT_CONN
2 1 USBP1-_R
<10> USBP1- 2 1
1
3 4 USBP1+_R C712
<10> USBP1+ 3 4 RV2 RV1 R567 0_4 *.01u/16V_4
DLW21HN900SQ2L/300mA/90ohm L57
R312 *0_4 *EGA-0402 *EGA-0402 3 3 4 USBP4+_R
<10> USBP4+
2
4 USBP4-_R
<10> USBP4- 2 2 1 1
C C
*RFCMF1632100M3T/200mA/90ohm
R568 0_4
+5V_S5
USB/B 5/13 reserve pi-filter
C446
*1u/6.3V_4
R279
0_1206
C409
*1u/6.3V_4
USB_DB FFC CONN

16
R261 *0_4 15
B B
14
L29 13
USBP9+_R 12
<10> USBP9+ 2 2 1 1 <10> USB_OC4_5# 11
3 4 USBP9-_R
<10> USBP9- 3 4 10
DLW21HN900SQ2L/300mA/90ohm USBP11-_R 9
R262 *0_4 USBP11+_R 8
7
6
R274 *0_4 USBP9-_R 5
USBP9+_R 4
L31 3
USBP11+_R 2 17
<10> USBP11+ 2 2 1 1 1 18
USBP11-_R <35> USBON#
<10> USBP11- 3 3 4 4
CN10
DLW21HN900SQ2L/300mA/90ohm
R273 *0_4
5/11 update the footprint

A A

PROJECT : ZQ9
1A
USB/ BT
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
+3V
K/B CN2 CPU FAN
MY0 1
<35> MY0
7 8 MX3 MY1 2 R385
<35> MY1
5 6 MX2 MY2 3
<35> MY2 +5V
3 4 MX4 MY3 4 10K_4
<35> MY3
1 2 MX5 MY4 5
<35> MY4
CP6 *100p/50Vx4 MY5 6
<35> MY5 6/20 change th P/N
7 8 MX6 MY6 7
<35> MY6
2
5 6 MX7 MY7 8 C549
D <35> MY7 <35> FANSIG D
3 4 MY17 MY8 9 2.2U_6
<35> MY8
1 2 MY16 MY9 10 U17 CN6
<35> MY9
1
CP5 *100p/50Vx4 MY10 11 2 3 TH_FAN_POWER 1
<35> MY10 VIN VO
7 8 MY3 MY11 12 5 2
<35> MY11 GND
5 6 MY2 MY12 13 1 6 3
<35> MY12 <10,11,35> SML1ALERT# /FON GND
2
3 4 MY1 MY13 14 7 C547 C548 C546
<35> MY13 GND
1 2 MY0 MY14 15 4 8 FAN_CONN
<35> MY14 <35> CPUFAN# VSET GND
CP4 *100p/50Vx4 MY15 16 2.2U_6 .01U_4 *.01U_4
<35> MY15
1
7 8 MY7 MY16 17 G995P1U
<35> MY16
5 6 MY6 MY17 18
<35> MY17
MY5 MX7
3
1
4
2 MY4
<35> MX7
MX6
19
20
FANPWR = 1.6*VSET
<35> MX6
CP3 *100p/50Vx4 MX5 21
<35> MX5
7 8 MY11 MX4 22
<35> MX4
5 6 MY10 MX3 23
<35> MX3
3 4 MY9 MX2 24 27
<35> MX2
1 2 MY8 MX1 25 28
<35> MX1
CP2 *100p/50Vx4 MX0 26
<35> MX0
7 8 MY15
5 6 MY14 KB
3 4 MY13 +3VPCU
1 2 MY12
CP1 *100p/50Vx4
C
C222 *100p/50V_4 MX1
MX0
RP3 10K_10P8R TOUCHPAD & Switch CONN. C
C221 *100p/50V_4 10 1 MX3
MX4 9 2 MX2
MX5 8 3 MX1
MX6 7 4 MX0
MX7 6 5 +5V +5V
L20 0_6 +TPVDD
C223
HOLE R86
10K_4
R87
10K_4
0.1u/10V_4_X7R
CN1
HOLE2 HOLE18 HOLE19 HOLE21 HOLE3 HOLE5 1
*hg-c315d110p2 *HG-C315D154P2 *H-C256D161P2 *H-C197D87P2 *H-C94D94N *h-c1417d1417na1457 L18 0_6 2
<35> TPDATA
7 6 7 6 TPDATA_R 3
8 5 8 5 L19 0_6 TPCLK_R 4
<35> TPCLK
9 4 9 4 5
C219 C220 6
RIGHT# 7
1
2
3
1
2
3
*.01u/25V_4 8
*.01u/25V_4 9
10 13
B 5/12 add 11 14 B
HOLE13 HOLE14 HOLE15 HOLE4 HOLE9 LEFT# 12
*hg-c315d118p2 *hg-c315d118p2 *hg-c315d118p2 *hg-c315d118p2 *hg-c315d118p2
7 6 7 6 7 6 7 6 7 6 Aces 88501-120N
8 5 8 5 8 5 8 5 8 5
9 4 9 4 9 4 9 4 9 4 HOLE8 HOLE11 HOLE12
*H-TC256BC165D165P2 *H-TC256BC165D165P2 *H-TC256BC165D165P2
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
6/18 change SW3 SW2

RIGHT# 3 2 LEFT# 3 2
HOLE6 HOLE17 HOLE10 HOLE16 HOLE7 1 4 1 4
*hg-c315d118p2 *hg-c315d118p2 *hg-c315d118p2 *hg-c315d118p2 *hg-c315d118p2
1
7 6 7 6 7 6 7 6 7 6 SWITCH_1.5 SWITCH_1.5
8 5 8 5 8 5 8 5 8 5
9 4 9 4 9 4 9 4 9 4
HOLE20
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
*H-C256D161P2
5/24 add
HOLE1 6/21 add
1
*HG-C315D118P2 5/21 add PAD1 PAD2 PAD3

A 7 6 *SPAD-C200NP *SPAD-C200NP *SPAD-C200NP A
8 5
9 4

1
1
1
2
3
5/27 Delete HOLE4, HOLE22

PROJECT : ZQ9
1A
KB/FAN/TP+FP
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
EC(KBC) L22 PBY160808T-250Y-N/3A/25ohm_6 +A3VPCU

+3V
I/O ADDRESS SETTING(KBC)
C226 C227
30mil
0.1u/10V_4_X7R
10u/10V_6
+3VPCU E775AGND
R108 2.2_6 D15 C570 C571
1 2 +3VPCU_EC 0.03A(30mils)
BAS316 4.7U/6.3V_6 0.1u/10V_4_X7R
C573 C538 C593 C551 C229 C225
115
102
19
46
76
88
4
4.7U/6.3V_6 0.1u/10V_4_X7R
*.1u/16V_4 0.1u/10V_4_X7R
*.1u/16V_4 0.1u/10V_4_X7R U18
AVCC
VDD
VCC1
VCC2
VCC3
VCC4
VCC5
E775AGND C595 10u/6.3V_8 ICMNT SHBM=0: Enable shared memory with host BIOS
D D
C605 0.01u/16V_4
<9,27> LPC_LFRAME# 3 LFRAME GPIO90/AD0 97 TEMP_MBAT <36>
126 98 WL_SW T58
<9,27> LPC_LAD0 LAD0 GPIO91/AD1
127 99 SHBM SHBM_R R405 10K_4
<9,27> LPC_LAD1 LAD1 GPIO92/AD2 SML1ALERT# <10,11,34>
<9,27> LPC_LAD2 128 LAD2 A/D GPIO93/AD3 100 ICMNT <36>
<9,27> LPC_LAD3 1 LAD3 GPIO05 108
CLK_PCI_775 CLK_PCI_775 2 96 1/13 Comfirm by vendor mail :
<10> CLK_PCI_775 LCLK GPIO04 VGA_THERM# <21>
Disabled ('1') if using FWH device on LPC.
<8> CLKRUN# 8 GPIO11/CLKRUN
101
Enabled ('0') if using SPI flash for both system BIOS and EC firmware
GPIO94/DA0 T6
R106 121 105 T7
<11> SIO_A20GATE GPIO85/GA20 GPI95/DA1
*22_4
D/A GPI96/DA2 106 CPUFAN# <34>
<11> SIO_RCIN# 122 KBRST/GPIO86 GPI97 107
<11> SIO_EXT_SCI#
D3 BAS316 29
ECSCI/GPIO54 LPC SM BUS PU(KBC) +3VPCU
64 ACIN <36>
C228 EC_FPBACK# GPIO01/TB2 NBSWON#
<23> EC_FPBACK# 6 95
GPIO24/LDRQ GPIO03 MBCLK R92 10K_4
*10p/50V_4 93 LID591# <23>
NOCIR# GPIO06/IOX_DOUT MBDATA R91 10K_4
T60 124 94 SUSB# <8>
GPIO10/LPCPD GPIO07
119 MXM_SMCLK12 <21>
PLTRST# GPIO23/SCL3 +3V_D_S
<4,10,11,25,27,31> PLTRST# 7 109 T61
LREST GPIO30/CIRTX2 MXM_SMCLK12 R100 EV@2.2K_4
120 MXM_SMDATA12 <21>
USBON# GPIO31/SDA3 MXM_SMDATA12 R98 EV@2.2K_4
<33> USBON# 123 65 BATLED0# <32>
GPIO67/PWUREQ GPIO32/D_PWM
GPIO33/H_PWM 66 BATLED1# <32>
IRQ_SERIRQ 125 15 +3V
<9> IRQ_SERIRQ SERIRQ GPIO36 VRON <38>
16 SUSLED# <32>
GPIO40/F_PWM AC_OFF
<11> SIO_EXT_SMI# 9 17 T52
GPIO65/SMI GPIO42/TCK 2ND_MBCLK R88 10K_4
GPIO GPIO43/TMS
20
3G_SW
AMP_MUTE# <29>
2ND_MBDATA R89 10K_4
21 T49
MX0 GPIO44/TDI
<34> MX0 54 22 T48
MX1 KBSIN0 GPIO45/E_PWM VGA_THERM# R416 EV@10K_4
<34> MX1 55 KBSIN1 GPIO46/CIRRXM/TRST 23 T47
MX2 56 24 T46
<34> MX2 KBSIN2 GPO47/SCL4
MX3 57 25
C <34> MX3 KBSIN3 GPIO50/TDO D/C# <36> C
MX4 58 26
<34> MX4 KBSIN4 GPIO51 S5_ON <37,44>
MX5 59 27
<34> MX5 KBSIN5 GPIO52/CIRTX2/RDY HDMI_HPD_EC# <24>
MX6 60 28 T44
<34> MX6 KBSIN6 GPIO53/SDA4
MX7 61 91
<34> MX7 KBSIN7 GPIO81 DNBSWON# <8>
GPO82/TEST 110
MY0 53 112
<34> MY0 KBSOUT0/JENK GPO84/TRIST
MY1 52 80 T50
<34> MY1 KBSOUT1/TCK GPIO41
MY2 51
<34> MY2 KBSOUT2/TMS
MY3 50
<34> MY3 KBSOUT3/TDI
MY4 49 KB 31 ODDLED T45
<34> MY4 KBSOUT4/JEN0 GPIO56/TA1
MY5 48 117
<34> MY5 KBSOUT5/TDO GPIO20/TA2/IOX_DIN SUSON <40>
MY6 47 63
<34> MY6 KBSOUT6/RDY GPIO14/TB1 FANSIG <34>
MY7 43
<34> MY7 KBSOUT7
MY8 42 TIMER 32
<34> MY8 KBSOUT8 GPIO15/A_PWM CONTRAST <23>
MY9 41 118 T63
<34> MY9 KBSOUT9/SDP_VIS GPIO21/B_PWM
MY10 40 62
<34> MY10 KBSOUT10/P80_CLK GPIO13/C_PWM PWRLED# <32>
MY11 39 81 T5
<34> MY11 KBSOUT11/P80_DAT GPIO66/G_PWM
MY12 38
<34> MY12 KBSOUT12/GPIO64 5/17 Change to test pad
MY13 37
<34>
<34>
MY13
MY14
MY14
MY15
36
KBSOUT13/GPIO63
KBSOUT14/GPIO62 GPIO77/SPI_DI
84
SHBM_R
T54 SPI FLASH(KBC) +3VPCU
<34> MY15
MY16
35
KBSOUT15/GPIO61/XOR_OUT SPI GPO76/SPI_DO/SHBM
83 T51
U19
<34> MY16 34 82
MY17 GPIO60/KBSOUT16 GPIO75/SPI_SCK SPI_SDI_uR R99 22_4 SPI_SDI_uR_R
<34> MY17 33 2 8
GPIO57/KBSOUT17 SO VDD
75 RSMRST#_uR R90 *Short_4 R96 *100K_4 SPI_SDO_uR 5 7 C591
GPIO72/IRRX1/SIN2 ICH_RSMRST# <8> SI HOLD
MBCLK 70 73
<36> MBCLK GPIO17/SCL1 GPIO70/IRRX2_IRSL0 SUSC# <8> 7/24 modify
MBDATA 69 74 PWROK_EC_uR R386 *Short_4 SPI_SCK_uR 6 3 0.1u/10V_4
<36> MBDATA GPIO22/SDA1 GPIO71/IRTX/SOUT2 PWROK_EC <8> SCK WP
<10> 2ND_MBCLK 2ND_MBCLK 67 SMB IR 113
GPIO73/SCL2 GPIO87/CIRRXM/SIN_CR RF_EN <27>
<10> 2ND_MBDATA 2ND_MBDATA 68 14 T53 +3VPCU R101 10K_4 SPI_CS0#_uR 1 4
GPIO74/SDA2 GPIO34/CIRRXL HWPG CE VSS
114
GPIO16/CIRTX P_SAVE_LED# W25X40BVSSIG
111 T59
TPCLK GPO83/SOUT_CR/XORTR
<34> TPCLK 72 GPIO37/PSCLK1
TPDATA 71 1/13 Comfirm by vendor mail :
<34> TPDATA GPIO35/PSDAT1
B PCH_ACIN 10 86 SPI_SDI_uR If the Southbridge enables 'Long Wait Abort' by B
<8> PCH_ACIN GPIO26/PSCLK2 F_SDI
11 PS/2 87 SPI_SDO_uR_R R97 22_4 SPI_SDO_uR
<33> BT_POWERON# GPIO27PSDAT2 F_SDO default, the flash device should be 50MHz (or faster)
12 FIU 90 SPI_CS0#_uR
<19,39,40,43> MAINON GPIO25/PSCLK3 F_CS0
T55 MAINOND 13 92 SPI_SCK_uR_R R102 22_4 SPI_SCK_uR
GPIO12/PSDAT3 F_SCK
<8> ICH_SUSCLK R390 *Short_4 E775_32KX1 77 30 ECDB_CLOCK T43
GPIO00/32KCLKIN GPIO55/CLKOUT/IOX_DIN
VCC_POR
85 VCC_POR# R415 47K/F_4 +3VPCU HWPG(KBC) +3V
VCORF
AGND
GND1
GND2
GND3
GND4
GND5
GND6
R392 *20M_6 E775_32KX2 79 104 VREF_uR R107 *Short_4 +A3VPCU

GPIO02 VREF
R398 NPCE781 R110

5
18
45
78
89
116
103
VCORF_uR 44
10K_4
Y4 *33K/F_4 SM BUS ARRANGEMENT TABLE
1 4 D9 BAS316 HWPG
<43> HWPG_1.8V
SM Bus 1 Battery
L21 PBY160808T-250Y-N/3A/25ohm_6 D7 BAS316
<39> HWPG_1.05V
C550 *32.768KHz C552 C539 SM Bus 2 PCH D8 BAS316 R109
<40> HWPG_1.5V
*15p/50V_4 *15p/50V_4 *Short_4
1u/6.3V_4 D6 BAS316
<37> SYS_HWPG
E775AGND E775AGND SM Bus 3 GPU-I2C MPWROK <4>
D5 IV@BAS316
<41> HWPG_GFX
SM Bus 4 N/A
POWER-ON Switch(KBC) INTERNAL KEYBOARD STRIP SET(KBC)

6/21 unstuff
A SW1 A
*MSK:NTC031-AC1G-A120T +3VPCU
NBSWON# D2 BAS316 1 2 MY0 R393 10K_4

3 4
2
5
D1 6
*VPORT_6

1
PROJECT : ZQ9
5/13 change the location 1A
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WPCE781 & FLASH
5 4 3 2 1
5 4 3 2 1
POWER_JACK
dcjk-2dc2003-000111-3p-v VA1 PD6 6/9 change the P/N to 3720
PJ1 PL2 SBR1045SP5-13 PQ27 VIN PQ29
1 HI0805R800R-00_8 1 FDD6685 FDD6685
2 VA 3 VA2 3 4 1 2 3 4
2
3 5/14 add short PAD
1
PC81 PC82 PR147 PR145 PR144 PC6 PC1 PR156
7
6
5
4
PL1 0.1u/50V_6 0.1u/50V_6 220K_4 0.01_3720 SHORT_PAD_4 0.1u/50V_6 2200p/50V_6 33K/F_4

HI0805R800R-00_8 PD5 PR146
SMAJ20A SHORT_PAD_4 CSIN_1
2
D D
PC78 PC79 PC80 CSIP_1
0.1u/50V_6 2200p/50V_6*47u/25V_6.3*6 1 6
PD1 PR157
5/12 EMI RESERVE SW1010CPT PR148 2 5 D/C# <35>
10K_4
5/14 add short PAD 220K_4
3 4 PR149
3
*SHORT_PAD_4
PQ28
IMD2AT108
CSIN_1 2
PQ32
CSIP_1 DMN601K-7
1
VIN
PC11
PR9 PR8 1u/16V_6
10/F_4 10/F_4
PC14
0.1u/50V_6 PR159
4.7_6 PC7
1u/16V_6
27 CSIN
28 CSIP
ISL88731_VDDP
5
6
7
8
PC84
10u/25V_1206
33
32
31
30
26
21
C C
1
+3VPCU PD7 PC83
*RB500V-40 4 2200p/50V_6
CSSP
VDDP
NC
GND
GND
GND
GND
CSSN
VCC
PC12 PR6 PC10
0.1u/50V_6 2.7_6 0.1u/50V_8
+3VPCU 11 25 88731B_2 88731B_1 PQ31 0.01_3720
VDDSMB BOOT AO4468 PR158
PL5
3
2
1
<35> MBDATA 9 24 ISL88731_UGATE 6.8uH
PR7 SDA UGATE BAT-V
1 2
100K_4
5
6
7
8
<35> MBCLK 10 23 ISL88731_PHASE
SCL PHASE
13 20 ISL88731_LGATE 4 PR155
<35> ACIN ACOK LGATE *4.7_6
PR5 PC9 19
49.9/F_6 0.1u/50V_6 PGND PQ30
DCIN 22 AO4468 CSOP_1
DCIN PR3 PC85 PC86
3
2
1
PR11 10/F_4 PC88 BAT-V 2200p/50V_6 10u/25V_1206
82.5K/F_4 PU1
CSOP 18 CSOP CSOP_1 *680p/50V_6 PC87
PC3 88731ACSET 2 ISL88731A 10u/25V_1206
0.1u/50V_6 ACIN PC8
2 1 0.1u/50V_6
3
B
PC2 PR12 VREF
CSON 17 CSON BAT-V 0618 change to AO4468 B
100p/50V_6 PL4 22K/F_4
HI0805R800R-00_8 4 PR1
ICOMP 10/F_4
NC 16
MBAT+ BAT-V
C114F3-108A1-L_Batt_Conn 5 PR4
PL3 NC *SHORT0402
HI0805R800R-00_8 15 BAT-V
10 1 PR153 VBF
2 6 VCOMP
100_4 29 PR2
3 TEMP_MBAT GND 100_4
GND
4 TEMP_MBAT <35>
ICM
NC
NC
5
6 PR152 PR10
7
14
12
7 100K_4 2.21K/F_4
9 8
+3VPCU
PJ2
PC5 PC4
47p/50V_6 47p/50V_6 PC13
0.01u/50V_6
ISL88731 thermal pad
ICMNT
tie to Pin12
ICMNT <35>
PR154
*SHORT_PAD_4 PR150 PR151
100_4 100_4 PC15 PC16 PC17
*1u/16V_6 0.01u/50V_6 *0.01u/50V_6
MBCLK <35>
A MBDATA <35> A
PU6
CM1293A-04SO
1 6 MBDATA
CH1 CH4
2 VN VP 5 +3VPCU Quanta Computer Inc.
TEMP_MBAT MBCLK
3 CH2 CH3 4
PROJECT : ZQ9
Add ESD diode base on EC FAE suggestion 1A
Charger(ISL88731A)
5 4 3 2 1
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5 4 3 2 1
MAIND
MAIND <40,43>
VL
6/14 remove JP2 , T25 and T26
<4,44> SYS_SHDN# 6/14 remove JP14 , T88 and T93
PR112
*SHORT_PAD_4
1
D VIN VIN D
PR111
39K/F_4 VL
1
PC70 PC171
2
+ PC170 PC169 3V5V_EN 4.7u/10V_8
PR110 PR232 PC165 4.7u/25V_0805
2
PC173 4.7u/25V_0805 4.7u/25V_0805 *SHORT_PAD_4 PR108 PR133 *SHORT_PAD_4 2.2n/50V_4
1
100u/25V_6X5.7 *SHORT_PAD_4 *SHORT_PAD_4 OCP:9A
1
PC74 PR234
6.8A
PC63 PR135 PC72 1u/16V_6 *0_4 +3VPCU
5V_EN
3V_EN
2.2n/50V_6 390K_4 0.1u/50V_6
OCP:6.5A
5
6
7
8
PC71 6/14 remove JP16 , T100 and T96
2
0.01u/16V_4 PC73
5A 0.1u/50V_6
1
+5VPCU 8206_ONLDO REF 4
3V_DH
8
7
6
5
6/14 remove JP15 , T98 and T99
PR233 PQ14
PR134 *0_6 AO4468
8
7
6
5
4
3
2
1
4 5V_DH 150K_4
PL14
LDOREFIN
LDO
VIN
NC
ONLDO
VCC
TON
REF
3
2
1
2.2uH
PQ13
AO4468 PR130 3V_LX
5
6
7
8
+5VPCU 9 32 REFIN2 220K/F_4
PL13 BYP REFIN2
10 31 1 2
1
2
3
2.2uH OUT1 ILIM2 PR98
C 11 FB1 OUT2 30 C
5V_LX 1 2 12 PU5 29 SKIP 4 PD10 *4.7_6
ILIM1 SKIP#
2
PR116 DDPWRGD_R 13 RT8206B 28 DDPWRGD_R *SX34
PGOOD1 PGOOD2
8
7
6
5
147K/F_4 5V_EN 14 27 3V_EN PR126 +
PR125 EN1 EN2
15 DH1 DH2 26 *0_4
*0_4 PR97 16 25 PC59 PC178 PC175
*4.7_6 5V_DL LX1 LX2 *680p/50V_6 0.1u/50V_6 330u/6.3V_6X5.7
4 37
1
+ PC177 PD9 PAD 6/9 unstuff
36
3
2
1
PAD
PGND
PVCC
*SX34 PQ12
BST1
BST2
GND
PAD
PAD
PAD
DL1
DL2
PC174 0.1u/50V_6 PC66 PC65 AO4710
NC
330u/6.3V_6X5.7 PC58 0.1u/50V_6 0.1u/50V_6 PR124 *SHORT_PAD_4
*680p/50V_6 PQ11 PR106
35
34
33
17
18
19
20
21
22
23
24
PC176 PR117 AO4710 PR107 1/F_6 +3VPCU_OUT 1 2
1
2
3
*10u/25V_1206 *SHORT_PAD_4 6/9 unstuff 1/F_6 1 2 PR129 *0_4

1 2 3V_DL
2
PR103 VL SKIP 1 2 REF PR131
+5VPCU_FB *0_6 PR231 *0_4
PC77 *SHORT_PAD_6 PR113
2 0.1u/50V_6 PC64 *0_4
1
PD3 1u/16V_6
CHN217 3 *SHORT_PAD_4
PR235 PR115
1 *SHORT_PAD_4 +3VPCU
PC67
0.1u/50V_6
2
PD4
OCP:6.5A CHN217 3 PR104 OCP:9A PR109
B B
L(ripple current) PC76 *SHORT_PAD_6 L(ripple current) *100K/F_4
1 0.1u/50V_6
=(9-5)*5/(2.2u*0.4M*9)=2.525A =(9-3.3)*3.3/(2.2u*0.5M*9)
Iocp=6.5-(2.525/2)=5.24A +15V_ALWP 1 2 =1.9A
+15V
DDPWRGD_R
Vth=5.24A*14.2mOhm=0.074V SYS_HWPG <35>
1
PR132 PR137 Iocp=9-(1.9/2)=8.05A
R(Ilim)=(0.07437V*10)/5uA=148.74K 22_8 *200K/F_4 PR105 PR114
PC69 *39K/F_4 Vth=8.05A*14.2mOhm=114.31mV *SHORT_PAD_4
Ipeak(choke)=10.687A 0.1u/50V_6 R(Ilim)=(114.31mV*10)/5uA=228.62K
Ipeak(choke)=11.479A
2
VIN +3V_S5 +5V_S5 +15V VIN +5VPCU +5VPCU +3VPCU +3VPCU
PR140 PR138 PR139 PR143 PR142
3
1M_6 22_8 22_8 1M_6 *1M_6
5
6
7
8
5
6
7
8
5
6
7
8
S5D 2
S5D 4 MAIND 4 MAIND 4
3
PQ57
A PQ15 PQ56 PQ58 AO3404 A
1
2 AO4468 AO4468 AO4468
<35,44> S5_ON
2 2 2 +3V_S5 0.23A
3
2
1
3
2
1
3
2
1
PR141 PQ17 PQ18

1
PQ16 1M_6 DMN601K-7 DMN601K-7

DTC144EU PQ19 PC75
+5V_S5
1
DMN601K-7 *2.2n/50V_4
+5V +3V
2.85A PROJECT : ZQ9
2.171A 2.66A Size Document Number Rev
www.vinafix.vn
1A
SYSTEM 5V/3V (RT8206)
5 4 3 2 1
5 4 3 2 1
VID 1.2875V
+3VPCU PR199 *0_4 H_VID0 DELAY_VR_PWRGOOD <4,8>
PR200 *0_4 H_VID1 Connect to input caps

VIN +VCC_CORE
Countinue current:36A
1
+ +
PR198 *0_4 H_VID2
6/14 remove JP7,T56 and T57 Peak current:48A
2
PQ41
OCP minimum 55A
5
PR197 *0_4 H_VID3 AOL1448
PR55
1K/F_4
Loadline=1.9mV/A (IMVP 6.5)
+3VPCU PR196 *0_4 H_VID4 4 PC179 PC118 PC121 PC120 PC122 PC124 Rilm=1.69K
D *100u/25V_6X5.7
0.1u/50V_6 4.7u/25V_8 4.7u/25V_8 4.7u/25V_8 100u/25V_6X5.7 D
1
2
3
PR195 *0_4 H_VID5 +5VPCU +3VPCU 6/9 preserved PL8 +VCC_CORE
0.36uH
PR193 *0_4 H_VID6 1 2 6/21 unstuff

PC130
1000p/50V_4 PQ43 PQ42
4
5
1
PR236 *SHORT_PAD_4 AOL1718 AOL1718 + +
+5VPCU PR52 PR39 PR35 PC136 PC22
PR203 649K/F_4 1.91K/F_4 *2.2/F_6 0.1u/50V_6 330u/2V_7343
2
4 4
6/21 stuff
16 3212_RAMP
*SHORT_PAD_8 PR34
1
2
3
1
2
3
10_6 PC123
PC24 *330u/2V_7343
*1000P/50V_6
3212_VCC
PR33
37
39
38
2
PR30 10/F_6
+1.05V PC23 *SHORT_PAD_4
PH0
PH1
VCC
PWRGD
RAMP
2.2U/6.3V_6
5/19 change to 0603
PR50 12 35 3212_DH1
*499/F_4 AGND DRVH1
49 36 3212_BOOT1
AGND BST1 PR38 2.2_6
<4> H_PROCHOT#
PC25
PSI#_1 41 0.22u/25V_6
<6> H_PSI# PSI#
3
PQ9 34 3212_SW1 6/14 remove JP8,T76 and T77

*DMN601K-7 PR31 SW1
*SHORT_PAD_4
2 10 VIN
VR_TT
C C
This NTC Close to Phase 1 Inductor
1
PR207 31 3212_DL1 +
DRVL1
+5VPCU
1
7.32K/F_4 PC137
PR191
2
11 100u/25V_6X5.7
TTSNS
*220K_6 NTC +5VPCU
+5VPCU PR47 5.1K/F_4 8 PU2
PC129 TRDET# PC29
1 2 9 VARFR
5
Panasonic *0.01U/16V_4 ADP3212 32 1 2 PQ48 PC135 PC133 PC134 PC132
CPU_VID0 PVCC AOL1448 0.1u/50V_6 4.7u/25V_8 4.7u/25V_8 4.7u/25V_8
<6> H_VID0 48
ERT-J0EV474J VID0 4.7U/6.3V_6
CPU_VID1 47 26 3212_DH2 4
<6> H_VID1 VID1 DRVH2
CPU_VID2 46 25 3212_BOOT2
<6> H_VID2
1
2
3
VID2 BOOT2
CPU_VID3 45 PR49 PL9 +VCC_CORE
<6> H_VID3 VID3 2.2_6 PC31 0.36uH
CPU_VID4 44 0.22u/25V_6
<6> H_VID4 VID4
27 3212_SW2 1 2
CPU_VID5 SW2
<6> H_VID5 43
VID5
5
PQ46 PQ47 6/21 stuff 6/21 unstuff
4
5
CPU_VID6 42 AOL1718 AOL1718
<6> H_VID6 VID6 PR54
1
PR37 *SHORT_PAD_4 VR_ON 1 29 3212_DL2 4 *2.2/F_6 + +
<35> VRON EN DRVL2
4 PC117 PC128
2
PR32 499/F_4 DPRSLPVR_R 40 0.1u/50V_6 *330u/2V_7343

<6> H_DPRSLPVR
1
2
3
2
PR36 DPRSLPVR
30
1
2
3
100K/F_4 PGND PC32
<3> VR_PWRGD_CK505# 4
CLK_EN# *1000P/50V_6 PR60
+3VPCU PR43 1.91K/F_4 PR59 10/F_6 PC30
1
*SHORT_PAD_4 330u/2V_7343
28 PR48 100/F_4 3212_CS_PH2
SWFB2
22
OD3# 5/19 change to 0603
23 33 PR44 100/F_4 3212_CS_PH1
PWM3 SWFB1
B B
24
PC27 SWFB3 3212_CSSUM PR61
19
150p/50V_4 CSSUM 127K/F_6
PC34
3212_FB 6 1000p/50V_4 PR58 PR56
FB
1
165K/F_4 127K/F_6
1
PC26
2
12p/50V_4 PC33 Short the net trace

PC28 PR45 560P/50V_4 PR190
2
150p/50V_4 39.2K/F_4 220K_6 NTC

PR46 3212_COMP 7 20
COMP CSCOMP
1.65K/F_4
17 3212_CSCOMP
3212_FBRTN PC127 1000p/50V_4 LLINE PR57
5
FBRTN Close to Phase 1 Inductor
73.2K/F_4
21 3212_ILIM
ILIM
3
CSREF
IMON PR51
IREF
RPM
PR204 1.69K/F_4
RT
4.75K/F_4
1 2
13
14
15
18
PC126 3212_CSREF CSREF

0.082u/16V_4
PR53
<6> I_MON
*SHORT_PAD_4
PC131
PR202 1u/6.3V_4 Peak :40A ; OCP:53A (1.69K/F_4)
PR206 *0_4
*27.4_4 Peak :48A ; OCP:55A (1.74K/F_4)
PR210 PR208
+1.05V 80.6K/F_4 162K/F_4
A PR209 A
69.8K/F_4
PR42
*SHORT_PAD_4
VSSSENSE <6>
VCCSENSE <6>
PR41
*SHORT_PAD_4 Quanta Computer Inc.
PR40
*27.4_4
PROJECT : ZQ9
www.vinafix.vn
+VCC_CORE
1A
+VCC_CORE ADP3212
5 4 3 2 1
5 4 3 2 1
6/14 Remove JP13 ,T84,T85
[PWM]
VIN
D +5V_S5 6/9 preserved D
OCP: 23A
5/19 add
19A
1
PR71 + + PC57 PC163 +1.05V
10_6 5/19 change location
5
PR96 PD2 4.7u/25V_08054.7u/25V_0805
PC144
2
2.2/F_6 RB500V-40
PR79
PC56
+
1M/F_4 4
4.7u/6.3V_6
PR95 PC180 PC168 PC164 560u/2.5V
1
2
3
PU4 0_6 100u/25V_6X5.7
PQ55 100u/25V_6X5.7 2.2n/50V_4
PR91 UP6111AQDD-B3 PC54 AOL1448
*SHORT_PAD_4 0.1u/50V_6
<19,35,40,43> MAINON 15 EN/DEM BOOT 13
6/14 Remove JP11 ,T83,T82
+3V 16 12 UGATE-1.05V PL12
PC48 TON UGATE 0.56uH
*0.1u/50V_6 1 11 PHASE-1.05V
VOUT PHASE
PR74 2 10 PR94
VDD OC
5
C *10K/F_4 2.15K/F_4 C
3 9 PC55 PR86
FB VDDP 1u/16V_6 *4.7_6 +
4 8 LGATE-1.05V 4 4
<35> HWPG_1.05V PGOOD LGATE
6 7 PC47
1
2
3
1
2
3
GND PGND PQ54 PQ52 *680p/50V_6
5 17 AOL1718 AOL1718
NC TPAD
14 NC PC146 PC145
PC42 PC46 *10u/10V_8 0.1u/50V_6
1u/16V_6 *1000p/50V_6 PC153
560u/2.5V
PR75
B 4.02K/F_4 PC41 B
R1 *33p/50V_6
1.05V_FB
PR73
10K/F_4
R2
PR237 *SHORT_PAD_4
AO1718 Rdson=3~4.3mOhm
TON=3.85p*RTON*Vout/(Vin-0.5)
L(ripple current) PR222
Frequency=Vout/(Vin*TON) =(19-1.05)*1.05/(0.56u*272k*19) *SHORT_PAD_6
~6.512A
A A
TON=3.85p*1M*1/(Vin-0.5) RILIM=2.15mohm*23-3.256/20uA=2.122Kohm
I(choke)peak=29.512A Quanta Computer Inc.
Frequency=1/(0.0036767)=272K
PROJECT : ZQ9
1A
+VTT (UP6111A)
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
[PWM]
D D
PC162
10u/10V_8
6/14 Remove JP12 , T86 and T87

PR223 PC161
*SHORT_PAD_6 0.1u/50V_6
8207A_VBST
+0.75V_DDR_VTT
VIN
8207A_DH
PC167 PC166 5/19 add
2.25A 10u/10V_8 10u/10V_8 8207A_LX
1
PC49 + PC158
5
8207A_DL
4.7u/25V_0805 4.7u/25V_0805
2
4
OCP:20A
25
24
23
22
21
20
19
PC159 PC160
1
2
3
PQ53 2200p/50V_6 100u/25V_6X5.7
16.84A
LL
DRVL
VTT
VBST
GND
VLDOIN
DRVH
AOL1448
1 18 +1.5VSUS
VTTGND PGND
PL11
2 17 0.56uH
VTTSNS CS_GND
6/14 Remove JP1 , T23 and T24
5
3 RT8207A 16 PR99
GND PU11 CS 7.15K/F_4
PR84
+1.5VSUS 4 15 4 *4.7_6 +
C MODE V5IN +5V_S5 C
PQ51
1
2
3
5 14 AOL1718
+SMDDR_VREF VTTREF V5FILT
1
PR100
VDDQSNS
VDDQSET
PC62 +5V_S5 6 13 PC61 5.1/F_6 PC60 PC45

0.15A 0.033u/50V_6 COMP PGOOD 1u/6.3V_4 1u/6.3V_4 *680p/50V_6 PC150 PC39
2
560u/2.5V 10u/10V_8
NC
NC
S3
S5
PR102 +3V
100K/F_4
7
10
11
12
FOR DDR III

HWPG_1.5V <35>
PR225 (For RT8207A 400KHZ ) close to pc2008

VIN
620K/F_4
S5_1.8V PR230
SUSON <35>
*SHORT_PAD_4
PR238 *SHORT_PAD_4 S3_1.8V PR229

MAINON <19,35,39,43>
*SHORT_PAD_4
PR228 +5V_S5
*0_4
PR101
*SHORT_PAD_6
PC172 PR226
*33p/50V_6 10K/F_4
Vout = (PR150/PR149) X 0.75 + 0.75
B B
AO1718 Rdson=3.8~4.3mOhm
8207A_SET
L(ripple current)
=(19-1.5)*1.5/(0.56u*400k*19)
PR227 S5_1.8V PR224 S3_1.8V ~6.168A
10K/F_4 *0_4
Vtrip= (20-6.168/2)*4.3mohm=0.072739V
+1.5VSUS RILIM=Vtrip/10u=7.273K
5
6
7
8
MAIND 4
<37,43> MAIND
PQ59
AO4468 S3 S5 +1.5VSUS REF VTT
3
2
1
S0 1 1 ON ON ON
+1.5V
2.03A S3 0 1 ON ON OFF
A
S4/S5 0 0 OFF OFF OFF A

PROJECT : ZQ9
www.vinafix.vn
1A
DDR 1.5V(RT8207A)
5 4 3 2 1
A B C D E F G H
Int_VGA [PWM]
<6> GFX_VID0
<6> GFX_VID1 +1.05V +1.05V

<6> GFX_VID2
OCP:25A
<6> GFX_VID3
Ri=2.49K
1 PR78 PR76 PR70 PR69 PR67 PR65 PR64 1
<6> GFX_VID4
*IV@0_4 *IV@0_4 *IV@0_4 *IV@0_4 *IV@0_4 *IV@0_4 *IV@0_4
Change Ri can adjust OCP point
<6> GFX_VID5 LL=7.03mv/A
<6> GFX_VID6 Rdroop=8.87K
PC149
*IV@0.01u/25V_4 GFX_VID6 GFX_VID5 GFX_VID4 GFX_VID3 GFX_VID2 GFX_VID1 GFX_VID0 Change Rdroop can adjust loadline
62881_GND 2 1
PR215 IV@100K_4
PR217
<6> GFX_ON
*IV@SHORT_PAD_4
PR81
<6> GFX_DPRSLPVR
*IV@SHORT_PAD_4 6/14 Remove JP10,T80,T81
VIN
PR221
62881_GND
*IV@SHORT_PAD_6
62881DPRSLPVR
62881_GND
62881VR_ON
1
PC138 PC140
GFX_VID6
GFX_VID5
GFX_VID4
GFX_VID3
GFX_VID2
IV@4.7u/25V_0805 IV@4.7u/25V_0805
2
+3V PC139 PC141
IV@0.1u/50V_6 IV@2.2n/50V_4
5/26 modify power budget
30
31
29
28
27
26
25
24
23
22
5
PR89
VID6
VID5
VID4
VID3
VID2
GND
GND
GND
DPRSLPVR
VR_ON
GFX_VID1
GFX_VID0
*IV@100K_4
1
OCP:25A
PR90 *IV@SHORT_PAD_4 CLK_EN#
2
62881PGOOD 2 21 +5V_S5
4 22A 2
<35> HWPG_GFX PGOOD VID1
1
2
3
PQ50 +VGFX_AXG
PR219 IV@47K/F_4 62881RBIAS 3 20 IV@AOL1448
62881_GND RBIAS VID0
PR218
*IV@150K/F_4 PC37
PR87 IV@8.06K/F_4 62881VW 4 19 1 2 5/26 modify power budget
62881_GND VW VCCP
PC53 IV@4.7u/6.3V_6
18 62881LGATE 5/26 modify power budget PL10 6/14 Remove JP9,T79,T78
5/26 modify power budget IV@1000P/50V_4 62881COMP 5 LGATE IV@0.56uH
COMP PU3
PR92 PC50 IV@ISL62881HRTZ-T 17 1 2
IV@820K/F_4 IV@22p/50V_4 VSSP
62881FB 6
4
FB
16 62881PHASE
PC51 PHASE PQ49 PQ10
5/26 modify power budget IV@100P/50V_4 PR88 IV@AOL1718 IV@AOL1718 PR62
5
IV@8.87K/F_4 15 62881UGATE *IV@2.2/F_4
62881VSEN UGATE PR213 + +
7
VSEN IV@3.65K/F_4
ISUM+
BOOT
ISUM-
IMON PC36
Rdroop 4 4
VDD
RTN
VIN
PR93 PC52 5/26 modify power budget PC142 PC143 IV@10u/6.3V_8

PR66 PR211 IV@560u/2.5V IV@560u/2.5V
1
2
3
1
2
3
PR63 PC38 IV@2.61K/F_4 IV@10K_6_NTC
8
10
11
12
13
14
IV@17.8K/F_4 IV@150P/50V_4 PC157 IV@1_6 IV@0.22u/25V_6 PC35
PC156 IV@330p/50V_4 62881BOOT 1 2 Close to Phase
62881VDD
62881ISUM+
62881ISUM-
62881VIN
IV@330p/50V_4 *IV@2.2n/50V_4
5/26 modify power budget 62881RTN PR68 Inductor
GFX_IMON
GFX_IMON <6>
PC155 IV@11K/F_4
2
62881_GND PR77 5/26 modify power budget
IV@1000P/50V_4 *IV@10K/F_4 PC44
*IV@0.22u/10V_4
1
PC40 PC151
3 IV@0.15U/10V_4 IV@0.1u/10V_4 3
VSS_AXG_SENSE <6>
62881_GND
PR214 VIN
*IV@SHORT_PAD_4 PC147 62881_GND
PC148 *IV@0.1u/10V_4
IV@0.22u/25V_6
5/26 modify power budget
62881_GND
+5V_S5
Ri
PC154
*IV@180P/50V_4
PR216
PR212 IV@2.49K/F_4
IV@10_6
PC152
IV@1u/6.3V_4 PR220
*IV@100/F_4
62881_GND
2 1
PR72 PC43
IV@82.5/F_4 IV@0.01u/25V_4
Close to Pin9 and Pin10
Parallel
PR82 IV@10/F_4
PR80
*IV@SHORT_PAD_4
VSS_AXG_SENSE <6>
4 4
PR85 IV@10/F_4
PR83
*IV@SHORT_PAD_4
VCC_AXG_SENSE <6>

PROJECT : ZQ9
1A
1.Level 1 Environment-related Substances Should NEVER be Used. +VGFX_AXG (ISL62881)
2.Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners. Date: Tuesday, June 22, 2010 Sheet 41 of 9
www.vinafix.vn
A B C D E F G H
1 2 3 4 5
6/14 Remove JP3,T38,T37
+5V_S5
VIN
OCP=15A
6/9 preserved +VGPU_CORE 12A
1
PR18 PC94 PC95
A +3V_D_S *EV@0_4 + A
PR164 EV@4.7u/25V_0805
EV@4.7u/25V_0805
2
5
EV@200K/F_4
PC99 EV@1u/10V_6 2 7 8792TON
VDD TON PQ35
PR169 5 8792DH 4 EV@AOL1448
EV@10K_4 PC98 EV@1u/10V_6 8792VCC DH PC93
13 VCC
5/12 change PC181 EV@2200p/50V_4
1
2
3
6 8792BST 100u/25V_6X5.7 6/14 Remove JP4,T40,T39
BST PR166
<44> PG_1V_EN 14 PGOOD EV@1_6 PC96
8792EN 1 PU7 EV@0.22u/25V_6
<11,19> dGPU_VRON EN 8792LX
4
PR171 EV@MAX8792ETD+T LX
*EV@0_4 8792SKIP# 12 PL6
SKIP# 8792DL EV@1uH
DL 3
5
PC100 PR16 *EV@0_4
<19,21,35> +3V_D_S EV@0.1u/10V_4 8792REFIN 10
PR170 REFIN PR17
FB 8
*EV@0_4SHORT_PAD_4 4 *EV@2.2_6 + +
PR172 REF-2V
EV@100K_4 8792REF 11 9 8792ILIM
1
2
3
REF ILIM
PQ36 PC19
EP
EV@AOL1718 *EV@1000p/50V_4
B B
R1 PR168 PR240 *SHORT_PAD_4
15
EV@39.2K/F_4
PR174 PR165 PC18
EV@73.2K/F_4 PC20 EV@330u/2V_7343
*EV@SHORT_PAD_6 *EV@4700P/25V_4 PC90 PC92
R3 EV@0.1u/50V_6 EV@330u/2V_7343
5/24 change to 73.2K Place near GND pin15
PR162 PC97
3
EV@332K/F_4 EV@1000P/50V_4
PR173
EV@100K_4
<17> VID1 2
Frequency(PR220=200K) 300K
PQ34
PR161 EV@DMN601K-7 VIN +VGPU_CORE
EV@3K_4 PR167
1
R2 EV@49.9K/F_4
AMD Park VID Table PR13 PR15

PC91 EV@1M_6 EV@22_8
EV@0.01u/16V_4 GPU_VID1 (GPIO15) GPU_VID2 (GPIO20) +VGPU_CORE
C R4 C
0 0 1.12V
3
1 0 1.05V
3
PR163
3
EV@130K/F_4 0 1 0.95V 2
8792EN 2
1 1 0.9V PQ2
2 PR14 EV@DMN601K-7
<17> VID2 PQ1 EV@1M_6
1
PQ33 EV@DTC144EU
PR160 EV@DMN601K-7
EV@3K_4
1
PC89
EV@0.01u/16V_4
D D

PROJECT : ZQ9
1A
GPU CORE(MAX8792)
1 2 3 4 5
www.vinafix.vn
5 4 3 2 1
2.17A
+1.8V
+3VPCU
6/14 Remove JP5 PC105

PC104 0.1u/25V_4
10u/10V_8
PU8 HPA00835RTER
6/9 change the P/N 16 10
VIN PH
1 11 PL7
VIN PH 1uH_7X7X3 6/14 Remove JP6,T41,T42
D PR176 D
2 12
*SHORT_PAD_4 VIN PH
15 13 PR175
<19,35,39,40> MAINON EN BOOT *SHORT_PAD_6
54418-1_VFB 6 14 PC101
VSNS PWRGD 0.1u/50V_6
PR177 PC102 7 3 5/12 change
100K/F_4 COMP GND
1000p/50V_4
8 4 R1 PR180
RT/CLK GND 100K/F_4
PAD
PAD
PAD
PAD
PAD
PAD
HWPG_1.8V <35>
9 5 PR178
PR181 PR182 SS AGND
100K/F_4
15K/F_4 182K/F_4 +3V_S5
22
21
20
19
18
17
PC109
PC110 PC107 10u/10V_8 PC108
*100P/50V_4 PC106 10u/10V_8 10u/10V_8
0.01u/25V_4 54418-1_VFB
6/9 change the P/N
PC111
V0=0.8*(R1+R2)/R2
1200p/50V_4
PR179
R2 78.7K/F_4
VIN +1.5V_GPU +15V +1.5VSUS
C PR23 PR24 PR25 C
5
6
7
8
EV@1M_4 *EV@22_8 EV@1M_4
PQ38
EV@AO4468
dGPU_D 4
3
3
3
PR26 3.94A
2 EV@1M_4 2 2
<44> PG_1.5V_EN PC21 +1.5V_GPU
3
2
1
1
PQ7 PQ8 *EV@2.2n/50V_4

PR29 PQ6 *EV@DMN601K-7 EV@DMN601K-7
1
*EV@100K_4 EV@DTC144EUA
1
1
2
VIN +1.8V_GPU +15V +1.8V
PR20 PR19 PR21
3
+1.5V_GPU EV@1M_4 EV@22_8 EV@1M_4
dGPU_D1 2
PR22
3
EV@1K_4
3
PQ37
B PR28 EV@AO3404 B
1.41A
1
2 EV@1M_4 2 2
PC103
+1.8V_GPU
1
PQ5 PQ4 *EV@2.2n/50V_4

PR27 PQ3 EV@DMN601K-7 EV@DMN601K-7
1
EV@100K_4 EV@PDTC143TT
1
1
2
VIN +3V +5V +0.75V_DDR_VTT +1.5V +1.8V +15V
PR128 PR118 PR119 PR121 PR120 PR122 PR123

1M_4 22_8 22_8 22_8 22_8 *22_8 1M_4
MAINON_ON_G MAIND
MAIND <37,40>
3
3
3
PR136
2 PQ26 1M_4 2 2 2 2 2 2
<19,35,39,40> MAINON DTC144EU PC68
PQ20 PQ21 PQ23 PQ22 PQ24 PQ25 *2200p/50V_4
DMN601K-7 DMN601K-7 DMN601K-7 DMN601K-7 *DMN601K-7 DMN601K-7
1
PR127
1
A *100K/F_6 A
7/7 modify

PROJECT : ZQ9
www.vinafix.vn
1A
Discharge/1.8V)
5 4 3 2 1
5 4 3 2 1
+3V_S5
1
+5VPCU PR186
10K_4
PC113 PU9
2
0.1u/50V_6 RT9018A
4 VPP PGOOD 1 PG_1.5V_EN <43>
D D
2 VEN VO 6 +1V
<42> PG_1V_EN
+1.5VSUS 3
8
VIN
GND
1.5A
1
ADJ
9 GND NC 5
1
PR183
PR185 9.1K/F_4
7
100K_4 PC112
2
22u/10V_1206
2
0.8V
PC115 PC114 PC116
10u/10V_8 0.1u/50V_6 0.1u/50V_6
PR184
34K/F_4
6/9 change the P/N
Vout =0.8(1+R1/R2)
=1V
C C
VIN
PU10B
LM393
5
PD8 +
7
SW1010CPT 6
-
PR205
For EC control thermal protection (output 3.3V)
Thermal protection 1M_6
1
PQ45
AO3409
2
3
B B
3
S5_ON 2
<35,37> S5_ON
PQ44 PR201
1
DTC144EU 0_6
VL VL
SYS_SHDN# <4,37>
Need fine tune
for thermal protect point PR194
200K_6
PR189 PC125
PR188 200K/F_4 0.1u/50V_6
3
1.74K/F_4
8
PR187
10K_6_NTC 2.469V 3 +
1 2
2 - PQ39
3
PU10A DMN601K-7
4
Note placement position LM393 PC119

1
A 0.1u/50V_6 A
S5_ON 2
PR192
PQ40 200K/F_4
DMN601K-7 Quanta Computer Inc.
1
PROJECT : ZQ9
1A

5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
MODEL
ZQ9
Model REV CHANGE LIST FRO M To
5/20 delet TP for modify Q23 X 1A
1A T7000 TP7010 TP7011 TP7012 TP44 X 1A
ZQ9 TP7013 TP7025 TP7022 TP7017 TP7028 X 1A
TP39 TP7020 TP7023 T3502 T3503
T3500 T3501 T3506 T3510 T3518
T3511 T3517 T3519 T3513 T3515
T3516 T3505 1A B 2A
1A B 2A
1A B 2A
5/21 swap RP7000 by following layout house's ask
1A B 2A
add HOLE18 HOLE19 HOLE20 HOLE21 HOLE22
change the LVDS connector and swap pin define 1A B 2A
delete PC4026 1A B 2A
1A B 2A
5/24 delete R30019 1A B 2A
change PR3011 to 73.2K 1A B 2A
stuff R3624 & R3527 and unstuff other components for changing +3V_D and +3V_D_S to +3V
1A B 2A
swap RN5 & RN10 pin defines
change footprints of HOLE2, HOLE3, HOLE5, HOLE21 and add HOLE23 1A B 2A
change Q45 & Q46 left side pull-high voltage to +3V 1A B 2A
5/25 reserve C1, C2, C3, C4, C507, C508, C509, C503, C511, C515, C516, C519, C520 for EMI 1A B 2A
1A B 2A
5/26 update JDIM7001 & CN14 footprint 1A B 2A
add PQ4000 change P/N of PL4000, PR4005, PC4022, PR4026, PR4006, PC4020, PR4024, PR4007, PC4018 1A B 2A
1A B 2A
5/27 Delete HOLE4, HOLE22 1A B 2A
1A B 2A
1A B 2A
1A B 2A
1A B 2A
1A B 2A
1A B 2A
1A B 2A
1A B 2A
2A 6/9 stuff PC128, unstuff PC22 1A B 2A
change the footprints C187, C178, C74, R144 to Std. 1A B 2A
stuff R80, R79, R53 & R77, R78, R51 for Park
1A B 2A
stuff R132, R407, R414 for board ID
stuff R293, R288, R285, R281, R280 for debug 1A B 2A
D change PR145 P/N to 3720 1A B 2A D
preserved PC179, PC180, PC181 1A B 2A

unstuff PD9, PD10 for cost down 1A B 2A
change PC104, PC107, PC109 P/N
1A B 2A
change PR184 P/N
1A B 2A
6/11 change the P/N of Q12, Q20, Q21 1A B 2A
1A B 2A
6/14 change Q16, PC124, PC137, PC160, PC168, PC173 C572 P/N for EOD parts
1A B 2A
6/18 unstuff U27, C423, R287 and stuff R284 for using internal ROM for LAN
1A B 2A
change the AMP P/N and footprint
add CN19, C715, C717, Q25, R574, R573 reserve L57, C716 for adding another BT 1A B 2A
stuff Q13, Q14, R236, R237 & unstuff R215, R216 1A B 2A
change U11 P/N delete C489, R565, R330 1A B 2A
reserve R575 & R576
1A B 2A
stuff R563, R564, R571, C15, C426, C506, C479 & add C718, C719, C720 for EMI's request
1A B 2A
6/14 Remove Page37 JP2,JP15,JP16,JP14
1A B 2A
Page38 JP7,JP8
Page39 JP13,JP11 1A B 2A
Page42 JP3,JP4
1A B 2A
Page43 JP5,JP6
Power parts 1A B 2A
6/18 Change to Shortpad 0603 1A B 2A
PR231,PR104,PR222,PR223,PR101,PR221,PR165,PR175 1A B 2A
Change to Shortpad 0402
1A B 2A
PR149,PR4,PR154,PR124,PR115,PR114,PR232,PR133,PR108,PR110,PR112
PR117,PR30,PR59,PR31,PR37,PR53,PR42,PR41,PR91,PR230,PR229,PR217,PR81,PR90,PR214,PR80,PR83,PR170,PR176
Change to Shortpad 0805 1A B 2A
PR203 1A B 2A
1A B 2A
6/18 Change PQ30 to AO4468 PN:BAM44680003
1A B 2A
1A B 2A
1A B 2A
6/19 modify R90, R386, R107, R390, R109, R149, R163, R194, R233, R531, R234, R271, R556, R306, R292, R332,
R554, R562, R524 to 0402 shortpad
1A B 2A
6/19 modify R142, R172, R186, R168, R417, R178, R201, R113, R185, R169, R213, R174, R275, R268, R299, R557, R572, R570 1A B 2A
to 0603 shortpad 1A B 2A
6/19 modify R162, R140, R210, R116, R124, R303, R8, R14 to 0805 shortpad B 2A C 3A
B 2A C 3A
6/19 modify R526 to 1206 shortpad B 2A C 3A
B 2A C 3A
6/20 change C474 P/N, delete R565, R330, C489 for AMP change , change U11 P/N B 2A C 3A
change U17 P/N B 2A C 3A
6/21 stuff R565, unstuff L50 for 3V CLK gen and change CLK gen 100MHz signals order B 2A C 3A
add PR235, PR236, PR237, PR238, PR240 shortpads B 2A C 3A
change R458, R457 back to 0 ohm
B 2A C 3A
unstuff SW1
B 2A C 3A
modify R443, R550 to Shortpad 0805
add PAD1, PAD2, PAD3 B 2A C 3A
change U11, U20 P/N B 2A C 3A
change R315, R319 P/N B 2A C 3A
reserve C489 for EMI's request
B 2A C 3A
stuff PC180, PC181
B 2A C 3A
stuff C285, C284
stuff PC22, PC30 unstuff PC123, PC128 B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
C C
4A
B B

DOC NO.
PROJECT MODEL : ZR7B APPROVED BY: DATE: 2009/12/24
PROJECT : ZQ9
1A
Change list2 PART NUMBER: DRAWING BY: REVISON: C3A
A A
5 4 3 2 1
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Acer Aspire 4738G (Quanta ZQ9) Laptop Schematics

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Acer Aspire 4738G (Quanta ZQ9) Laptop Schematics

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5 4 3 2 1

X'TAL SLG8LV595 DMI(x4)

Cardreader AU6437-GBL USB-12 X'TAL 25MHz

Azalia SPI SPI ROM

Int. MIC ALC272X NPCE781 X'TAL RT8206B RT8207A HPA00835RTER

ADP3212 MAX8792ETD+T Discharger

BOM Option Table

P30 Board Con. RT9018A Thermal Protection

GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)

GPU PWR CTRL Option 2 (VDDR3 after VDDR1)

Thermal Follow Chart

+VCCRTC +3V~+3.3V RTC POWER ALWAYS ALWAYS NTC

+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS

+3V_S5 +3.3V LAN/BT/CIR POWER S5_ON S0-S5 CPU 3V/5 V

+5V +5V HDD/ODD/Codec/TP/CRT/HDMI POWER MAINON S0

+3V +3.3V PCH/GPU/Peripheral component POWER MAINON S0

+VGFX_AXG variation Internal GPU POWER GFX_ON S0

+1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0

+1.05V +1.05V PCH CORE POWER MAINON S0

+VCC_CORE variation CPU CORE POWER VRON S0

LCDVCC +3.3V LCD POWER LVDS_VDDEN S0

+5V_GPU +5V SWITCHABLE PWM IC POWER dGPU_PWR_EN# Discrete enable

+GPU_CORE +0.9V~+1.1V GPU CORE POWER +3V_D Discrete enable

+GPU_IO +0.9V~+1.1V GPU I/O POWER PG_GPUIO_EN Discrete enable

+1.5V_GPU +1.5V VRAM CORE POWER PG_1.5V_EN Discrete enable

+1.8V_GPU +1.8V GPU_CRE/LVDS/PLL POWER +1.5V_GPU Discrete enable

+1V +1V DP/PEG POWER PG_1V_EN Discrete enable

Quanta Computer Inc.

Quanta Computer Inc.

AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)

JTAG & BPM

Processor pull-up JTAG MAPPING 5/13 follow ZR7B setting

XDP_TMS R135 *51_4 0_4

Scan Chain STUFF -> R469, R491, R507

R209 (Default) NO STUFF -> R489, R490

Quanta Computer Inc.

AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3) U22D

<15> M_B_DQ[63:0] SB_CK[0] W8 M_B_CLK0 <15>

DDR SYSTEM MEMORY - B

M_A_DQ35 AK7 F8 M_A_DQS#1 M_B_DQ40 AK3 AR5 M_B_DQS#6

Channel A DQ[15,32,48,54], DM[5] Channel B DQ[16,18,36,42,56,57,60,61,62]

Quanta Computer Inc.

CPU Core Power U22F

VTT Rail Values are AUBURNDALE/CLARKSFIELD PROCESSOR (GRAPHICS POWER)

1.1V RAIL POWER

C285 330u/2V_7343 AC32 +1.05V AJ16 Y1

CPU CORE SUPPLY

PEG & DMI

VCC62 VTT1_52 VTT1_68

VCC88 VCC_SENSE VCCSENSE <38>

AUBURNDALE/CLARKSFIELD PROCESSOR (GND) AUBURNDALE/CLARKSFIELD PROCESSOR( RESERVED, CFG)

AT20 VSS1 VSS81 AE34 RSVD32 AJ13

AL20 VSS40 VSS120 W6 E21 VSS198 AJ29 CFG[15] RSVD_TP_59 E15

CFG7 R126 *3.01K/F_4

Quanta Computer Inc.

Size Document Number Rev

IBEX PEAK-M (DMI,FDI,GPIO) AC-coupling CAP place close to PCH

0-ohm resistor place close to PCH IBEX PEAK-M (LVDS,DDI)

Digital Display Interface

<35> ICH_RSMRST# C16 H7 SUSC# <35> BC46

PM_RI# F14 F6 PM_SLP_LAN# TP18

PCH Pull-high/low +3V_S5

PM_RI# R184 10K_4

RTC Circuitry C335

C3C EV@1u/6.3V_4 EV@10u/6.3V_6 *EV@0.1u/10V_4