Quanta ZRC

5 4 3 2 1
Maintenance and Service Guide,Service Manual,Motherboard Schematics for Laptop/notebook http://mycomp.su/x/
BOM Option Table

ZRC SYSTEM BLOCK DIAGRAM
Reference Description
IV@ for UMA only SKU
SW@ for Switchable Graphic only SKU AMD GPU 64Mb x 16 IO x 4 pcs
Arrandale Channel A 64Mb x 16 IO x 8 pcs
D
Robson_XT & D
rPGA 989 Park_XT Channel B 128Mb x 16 IO x 8 pcs

( 512M ) P19, 20
Dual Channel DDR III P4, 5, 6, 7 PCI-E x16 EXT_HDMI
DDRIII-SODIMM1 Capilano-Pro &
800/1066 MHZ IMC GFX Madison-Pro
DDRIII-SODIMM2 EXT_CRT
P14,15 ( 1G or 2G ) CRT Con.
EXT_LVDS P24
P16, 17, 18, 21, 22, 23
FDI DMI
X'TAL SLG8LV595 DMI(x4)

14.318MHz CLOCK USB-8
LVDS/CCD/MIC
INT_CRT
GENERATOR P3 FDI DMI Con.
INT_LVDS Int. MIC P24
CLK
Display
SATA 0
SATA - HDD
C C
P29
SATA
HDMI Con.
SATA - ODD SATA 1 INT_HDMI PS8101
P29 LS P25
P25
PCIE-6
PCI-E x1
USB Port USB-1 MINI CARD
USB Ibex Peak-M USB-13
P34 WLAN
P28
USB-3/9/11 PCH
USB/B Con. P34 P8, 9, 10, 11, 12, 13
(USB Port x3) PCIE-1 BRM 57780
RJ45
USB-4
GIGA LAN P26
Bluetooth Con. X'TAL P27
32.768KHz
P34
X'TAL
B 25MHz B
Cardreader AU6437-GBL USB-12 X'TAL 25MHz
P32
Cardreader control
P32
P8 BATTERY RTC
Azalia SPI SPI ROM

IHDA ISL88731A UP6111AQDD ISL62881HRZ-T
P8
LPC Batery Charger P38 +1.05V P42 +VGFX_AXG P46
LPC RT8206B RT8207A TPS54418RTE x2

3V/5V P39 +1.5V_SUS P43 +1.8V/+1V P47
Int. MIC ALC272X NPCE781 X'TAL
AUDIO CODEC P30 EC P37 32.768KHz ISL62882 MAX8792ETD+T Discharger
CPU core P40 +VGPU_CORE P44 P47
A
UP6111AQDD ISL62872 Thermal Protection A
GMT 1453L amp +1.1V_VTT P41 +VGPU_IO P45 P48
MIC JACK Power SW/B Touch Pad
P35 Board Con. Board Con.
P31
P33 P33 P35
Speaker Quanta Computer Inc.
P31
W25X16VSS1G EM-6781-T3 Fan Driver PROJECT : ZRC
HP/SPDIF K/B Con. HALL SENSOR (PWM Type) Size Document Number Rev
P31 P35
SPI FLASH P37 P24 P35 1A
Block Diagram
Date: Wednesday, July 21, 2010 Sheet 1 of 46
5 4 3 2 1
1 2 3 4 5 6 7 8
Maintenance
GPU PWR CTRL Option 1 (Default/ and Service
VDDR3 before VDDC) Guide,Service Manual,Motherboard Schematics for Laptop/notebook http://mycomp.su/x/
+3.3V VIN VIN +1.5V +1.5V_SUS +1.8V +5V
VDDR3 +3V_D VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 PG_1.5V_EN VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
MOS (AO3413) ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO6402) AO3413
P22 P44 P45 P47 P43 P43 P22 P22
A +3_D (0.5A) +VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +1.8V_GPU (3A) +5_GPU A
GPU PWR CTRL Option 2 (VDDR3 after VDDR1)

VIN VIN +1.5V +1.5V_SUS +3.3V +1.8V +5V
VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 +1.5V_GPU VDDR3 +3V_D VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO3413) MOS (AO6402) AO3413
P44 P45 P47 P43 P22 P43 P22 P22
+VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +3_D (0.5A) +1.8V_GPU (3A) +5_GPU
Thermal Follow Chart

Power States
CONTROL
POWER PLANE VOLTAGE DESCRIPTION ACTIVE IN
SIGNAL
B VIN +10V~+19V MAIN POWER ALWAYS ALWAYS B
+VCCRTC +3V~+3.3V RTC POWER ALWAYS ALWAYS NTC

Thermal
+3VPCU +3.3V EC POWER ALWAYS ALWAYS
Protection
+5VPCU +5V CHARGE POWER ALWAYS ALWAYS
+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS
+3V_S5 +3.3V LAN/BT/CIR POWER S5_ON S0-S5 CPU 3V/5 V

H_ORICHOT# PM_THRMTRIP# SYS_SHDN#
CORE PWR
CPU WIRE-AND SYS PWR
+5V_S5 +5V USB POWER S5_ON S0-S5 H/W Throttling
+5V +5V HDD/ODD/Codec/TP/CRT/HDMI POWER MAINON S0
+3V +3.3V PCH/GPU/Peripheral component POWER MAINON S0

SML1ALERT#
+1.5VSUS +1.5V CPU/SODIMM CORE POWER SUSON S0-S3
PCH FAN Driver FAN
+0.75V_DDR_VTT +0.75V SODIMM Termination POWER MAINON S0
+VGFX_AXG variation Internal GPU POWER GFX_ON S0

SM-Bus
+1.8V +1.8V CPU/PCH/Braidwood POWER MAINON S0
C C
+1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0

EC
+1.1V_VTT +1.05V or +1.1V CPU VTT POWER MAINON S0 CPUFAN#
+1.05V +1.05V PCH CORE POWER MAINON S0
+VCC_CORE variation CPU CORE POWER VRON S0
LCDVCC +3.3V LCD POWER LVDS_VDDEN S0
+5V_GPU +5V SWITCHABLE PWM IC POWER dGPU_PWR_EN# Discrete enable
+GPU_CORE +0.9V~+1.1V GPU CORE POWER +3V_D Discrete enable
+GPU_IO +0.9V~+1.1V GPU I/O POWER PG_GPUIO_EN Discrete enable
+1.5V_GPU +1.5V VRAM CORE POWER PG_1.5V_EN Discrete enable
+1.8V_GPU +1.8V GPU_CRE/LVDS/PLL POWER +1.5V_GPU Discrete enable
+1V +1V DP/PEG POWER PG_1V_EN Discrete enable
D D
Quanta Computer Inc.

PROJECT : ZRC
Size Document Number Rev
1A
PWR Status & GPU PWR CRL & THRM
1 2 3 4 5 6 7 8
5 4 3 2 1
6/21 add R586 for 3V CLK gen

D
Un-stuff L54 D
U31 Change P/N
150mA(30mil)
+1.5V L54 *PBY160808T-181Y-N/2A/180ohm_6 +1.5V_CLK 80mA(20mil)
+VDDIO_CLK L53 PBY160808T/2A/180ohm_6 +1.05V
C434 C740 C437
C734 C435 C731 C732
.1u/16V_4 .1u/16V_4 .1u/16V_4
.1u/16V_4 .1u/16V_4 10u/Y5V_8 10u/Y5V_8
R586 U31
0_6 Place each 0.1uF cap as close as
1 VDD_DOT possible to each VDD IO pin. Place
17 VDD_SRC VDD_SRC_I/O 15 the 10uF caps on the VDD_IO plane.
24 VDD_CPU VDD_CPU_I/O 18
20mil 5 VDD_27
+3V L29 BLM18AG601SN1D/200mA/600ohm_6 +3V_CLK 29 3
VDD_REF DOT_96 CLK_BUF_DREFCLK [10]
DOT_96# 4 CLK_BUF_DREFCLK# [10]
CLK_SDATA 31
C432 C464 C442 CLK_SCLK SDA R561 *33_4
32 SCL 27M 6 27M_CLK [17]
7 R562 *33_4 27M_CLK_SS [17]
4.7u/10V_8 .1u/16V_4 .1u/16V_4 27M_SS C467 *10p/50V_4
R564 33_4 CPU_SEL 30 10
[10] CLK_ICH_14M REF_0/CPU_SEL SRC_1/SATA CLK_BUF_DREFSSCLK [10]
SRC_1#/SATA# 11 CLK_BUF_DREFSSCLK# [10]
C735 33p/50V_4 13 REV: B Switch CLK_BUF_DREFSSCLK and
SRC_2 CLK_BUF_PCIE_3GPLL [10]
C SRC_2# 14 CLK_BUF_PCIE_3GPLL# [10] CLK_BUF_PCIE_3GPLL C
XTAL_IN 28
Y6 XTAL_IN +3V
14.318MHz XTAL_OUT 27 16 R287 10K_4
XTAL_OUT *CPU_STOP#
C733 33p/50V_4 2 20
VSS_DOT CPU_1 TP19
8 VSS_27 CPU_1# 19 TP20
9 VSS_SATA CPU_0 23 CLK_BUF_BCLK [10]
12 VSS_SRC CPU_0# 22 CLK_BUF_BCLK# [10]
21 VSS_CPU
IDT: AL003197000 (ICS9LRS3197AKLFT) 26 25 CK_PWRGD_R REALTEK AL000890000
VSS_REF CKPWRGD/PD#
33
Realtek: AL000875002 (RTM875N-632-VB-GRT) GND
Silego: AL8SP585000 (SLG8SP585VTR) SLG AL000595000
SLG8LV585V
+3V
CPU_CLK select SMBus
B
+1.05V
CLK Enable +3V B
R555
R558
2
R560 2.2K_4 1K/F_4
*10K_4
3 1 CLK_SDATA CLK_SDATA [14,15,28]
[10] ICH_SMBDATA
CK_PWRGD_R
CPU_SEL Q20
3
2N7002K Q21
2N7002K
R559 C737
+3V [39] VR_PWRGD_CK505# 2 R556
10K_4 *10p/50V/COG_4 100K/F_4
1
R554
2
2.2K_4
0 1
3 1 CLK_SCLK CLK_SCLK [14,15,28]
[10] ICH_SMBCLK
A CPU_SEL CPU0/1=133MHz CPU0/1=100MHz Q19 A
(default) 2N7002K

PROJECT : ZRC
1A
Clock Generator
5 4 3 2 1
5 4 3 2 1
Maintenance and Service

AUBURNDALE/CLARKSFIELD Guide,Service
PROCESSOR Manual,Motherboard SchematicsAUBURNDALE/CLARKSFIELD
(DMI,PEG,FDI) for Laptop/notebook http://mycomp.su/x/
PROCESSOR (CLK,MISC,JTAG)
DPLL_REF_SSCLK and DPLL_REF_SSCLK# can be connected to GND on Arrandale
directly if motherboard only supports discrete graphics. If motherboard supports
Processor Compensation Signals integrated graphics but without eDP, these pins can also be connected to GND directly.
U24A U24B
B26 R424 49.9/F_4 R439 20/F_4 H_COMP3 AT23
PEG_ICOMPI COMP3
PEG_ICOMPO A26 BCLK A16 CLK_CPU_BCLK [11]
MISC
A24 B27 R435 20/F_4 H_COMP2 AT24 B16 CLK_CPU_BCLK# [11]
[8] DMI_TXN0 DMI_RX#[0] PEG_RCOMPO COMP2 BCLK#
C23 A25 R426 750/F_4
[8] DMI_TXN1 DMI_RX#[1] PEG_RBIAS
CLOCKS
B22 PEG_RXN[0..15] [16] R131 49.9/F_4 H_COMP1 G16 AR30 T57
[8] DMI_TXN2 DMI_RX#[2] COMP1 BCLK_ITP
A21 K35 PEG_RXN0 AT30 T58 Layout Note: Place
D [8] DMI_TXN3 DMI_RX#[3] PEG_RX#[0] BCLK_ITP# D
J34 PEG_RXN1 R432 49.9/F_4 H_COMP0 AT26
B24
PEG_RX#[1]
J33 PEG_RXN2 COMP0
E16
these resistors
[8] DMI_TXP0 DMI_RX[0] PEG_RX#[2] PEG_CLK CLK_PCIE_3GPLL [10]
[8] DMI_TXP1 D23 DMI_RX[1] PEG_RX#[3] G35 PEG_RXN3
PEG_CLK# D16 CLK_PCIE_3GPLL# [10]
near Processor
DMI
B23 G32 PEG_RXN4 T14 AH24
[8] DMI_TXP2 DMI_RX[2] PEG_RX#[4] SKTOCC#
A22 F34 PEG_RXN5 A18 DPLL_REF_SSCLK_R R453 *0_4 DPLL_REF_SSCLK [10]
[8] DMI_TXP3 DMI_RX[3] PEG_RX#[5] DPLL_REF_SSCLK
F31 PEG_RXN6 A17 DPLL_REF_SSCLK#_R R457 *0_4 DPLL_REF_SSCLK# [10]
PEG_RX#[6] PEG_RXN7 H_CATERR# DPLL_REF_SSCLK# R458 *Short_4
D24 D35 AK14
[8] DMI_RXN0 DMI_TX#[0] PEG_RX#[7] Use reverse type CATERR#
THERMAL
G24 E33 PEG_RXN8 R452 *Short_4
[8] DMI_RXN1 DMI_TX#[1] PEG_RX#[8]
F23 C33 PEG_RXN9 REV : B R458 & R452
[8]
[8]
DMI_RXN2
DMI_RXN3 H23
DMI_TX#[2]
DMI_TX#[3]
PEG_RX#[9]
PEG_RX#[10] D32 PEG_RXN10
PEG_RXN11
(at GPU side) SM_DRAMRST# F6 DDR3_DRAMRST# [14,15] Change to short pad
PEG_RX#[11] B32 [11] H_PECI AT15 PECI
D25 C31 PEG_RXN12 AL1 SM_RCOMP_0 R195 100/F_4
[8] DMI_RXP0 DMI_TX[0] PEG_RX#[12] SM_RCOMP[0]
F24 B28 PEG_RXN13 AM1 SM_RCOMP_1 R194 24.9/F_4
E23 B30 PEG_RXN14 AN1 SM_RCOMP_2 R193 130/F_4
G23 A31 PEG_RXN15 [39] H_PROCHOT# H_PROCHOT# AN26
[8] DMI_RXP3 DMI_TX[3] PEG_RX#[15] PROCHOT#
PEG_RXP[0..15] [16] PM_EXT_TS#[0] AN15 PM_EXTTS#0 [14]
DDR3
MISC
J35 PEG_RXP0 AP15 R137 10K_4
PEG_RX[0] PEG_RXP1 PM_EXT_TS#[1] R134 10K_4
PEG_RX[1] H34 +1.05V
H33 PEG_RXP2 [11] PM_THRMTRIP# AK15 PM_EXTTS#1 [15]
PEG_RX[2] PEG_RXP3 THERMTRIP#
[8] FDI_TXN0 E22 FDI_TX#[0] PEG_RX[3] F35
D21 G33 PEG_RXP4
[8] FDI_TXN1 FDI_TX#[1] PEG_RX[4]
D19 E34 PEG_RXP5 AT28 T60
[8] FDI_TXN2 FDI_TX#[2] PEG_RX[5] PRDY#
D18 F32 PEG_RXP6 AP27 XDP_PREQ#
[8] FDI_TXN3 FDI_TX#[3] PEG_RX[6] PREQ#
G21 D34 PEG_RXP7
[8] FDI_TXN4 FDI_TX#[4] PEG_RX[7]
E19 F33 PEG_RXP8 AN28 XDP_TCLK
PCI EXPRESS -- GRAPHICS
[8] FDI_TXN5 FDI_TX#[5] PEG_RX[8] TCK
F21 B33 PEG_RXP9 H_CPURST# AP26 AP28 XDP_TMS
[8] FDI_TXN6 FDI_TX#[6] PEG_RX[9] RESET_OBS# TMS
Intel(R) FDI
PWR MANAGEMENT
G18 D31 PEG_RXP10 AT27 XDP_TRST#
[8] FDI_TXN7 FDI_TX#[7] PEG_RX[10] TRST#
JTAG & BPM

A32 PEG_RXP11
PEG_RX[11] PEG_RXP12 XDP_TDI_R
PEG_RX[12] C30 [8] PM_SYNC AL15 PM_SYNC TDI AT29
D22 A28 PEG_RXP13 AR27 XDP_TDO
[8] FDI_TXP0 FDI_TX[0] PEG_RX[13] TDO
C21 B29 PEG_RXP14 PEG_TXN[0..15] [16] AR29 XDP_TDI_M
[8] FDI_TXP1 FDI_TX[1] PEG_RX[14] TDI_M
D20 A30 PEG_RXP15 AN14 AP29 XDP_TDO_M R402 *0_4
[8] FDI_TXP2 FDI_TX[2] PEG_RX[15] VCCPWRGOOD_1 TDO_M
[8] FDI_TXP3 C18 FDI_TX[3]
G22 L33 CPEG_TXN0 C603 EV@0.1u/10V_4 PEG_TXN0 AN25 XDP_DBRST# [8]
C [8] FDI_TXP4 FDI_TX[4] PEG_TX#[0] DBR# C
E20 M35 CPEG_TXN1 C586 EV@0.1u/10V_4 PEG_TXN1 [11] H_PWRGOOD AN27
[8] FDI_TXP5 FDI_TX[5] PEG_TX#[1] VCCPWRGOOD_0
F20 M33 CPEG_TXN2 C601 EV@0.1u/10V_4 PEG_TXN2 REV : B R116 SHORT
[8] FDI_TXP6 FDI_TX[6] PEG_TX#[2]
G19 M30 CPEG_TXN3 C584 EV@0.1u/10V_4 PEG_TXN3 AJ22 XDP_OBS0 T23
[8] FDI_TXP7 FDI_TX[7] PEG_TX#[3] BPM#[0]
L31 CPEG_TXN4 C599 EV@0.1u/10V_4 PEG_TXN4 AK13 AK22 XDP_OBS1 T22
PEG_TX#[4] [8] PM_DRAM_PWRGD SM_DRAMPWROK BPM#[1]
FDI_FSYNC0_R F17 K32 CPEG_TXN5 C582 EV@0.1u/10V_4 PEG_TXN5 AK24 XDP_OBS2 T21
FDI_FSYNC1_R FDI_FSYNC[0] PEG_TX#[5] CPEG_TXN6 C597 EV@0.1u/10V_4 PEG_TXN6 BPM#[2] XDP_OBS3 T17
E17 FDI_FSYNC[1] PEG_TX#[6] M29 BPM#[3] AJ24
J31 CPEG_TXN7 C580 EV@0.1u/10V_4 PEG_TXN7 H_VTTPWRGD AM15 AJ25 XDP_OBS4 T15
FDI_INT_R PEG_TX#[7] CPEG_TXN8 C595 EV@0.1u/10V_4 PEG_TXN8 VTTPWRGOOD BPM#[4] XDP_OBS5 T19
C17 FDI_INT PEG_TX#[8] K29 BPM#[5] AH22
H30 CPEG_TXN9 C578 EV@0.1u/10V_4 PEG_TXN9 AK23 XDP_OBS6 T20
FDI_LSYNC0_R PEG_TX#[9] CPEG_TXN10 C593 EV@0.1u/10V_4 PEG_TXN10 T18 BPM#[6] XDP_OBS7 T16
F18 FDI_LSYNC[0] PEG_TX#[10] H29 AM26 TAPPWRGOOD BPM#[7] AH23
FDI_LSYNC1_R D17 F29 CPEG_TXN11 C576 EV@0.1u/10V_4 PEG_TXN11
FDI_LSYNC[1] PEG_TX#[11] CPEG_TXN12 C591 EV@0.1u/10V_4 PEG_TXN12
PEG_TX#[12] E28
D29 CPEG_TXN13 C611 EV@0.1u/10V_4 PEG_TXN13 R143 1.5K/F_4 CPU_PLTRST# AL14
PEG_TX#[13] CPEG_TXN14 C615 EV@0.1u/10V_4 PEG_TXN14 [10,11,26,28,32,36] PLTRST# RSTIN#
PEG_TX#[14] D27 PEG_TXP[0..15] [16]
C26 CPEG_TXN15 C623 EV@0.1u/10V_4 PEG_TXN15 R147
PEG_TX#[15] 750/F_4
L34 CPEG_TXP0 C602 EV@0.1u/10V_4 PEG_TXP0 Clarksfield/Auburndale
PEG_TX[0] CPEG_TXP1 C585 EV@0.1u/10V_4 PEG_TXP1
PEG_TX[1] M34
M32 CPEG_TXP2 C600 EV@0.1u/10V_4 PEG_TXP2
PEG_TX[3] L30
PEG_TX[5] K31
PEG_TX[7] H31
K28 CPEG_TXP8 C594 EV@0.1u/10V_4 PEG_TXP8
PEG_TX[9] G30
G29 CPEG_TXP10 C592 EV@0.1u/10V_4 PEG_TXP10
PEG_TX[11] F28 LTS DGG^9000005
E27 CPEG_TXP12 C590 EV@0.1u/10V_4 PEG_TXP12
PEG_TX[13] D28
C27 CPEG_TXP14 C617 EV@0.1u/10V_4 PEG_TXP14 SUY DGG^9000016
PEG_TX[15] C25
B
FOX DGG^9000023 B
Clarksfield/Auburndale
Processor pull-up
Thermaltrip protect VTT PWR_Good [8] FDI_FSYNC0
R121
R123
IV@0_4
IV@0_4
FDI_FSYNC0_R
FDI_FSYNC1_R
[8] FDI_FSYNC1
+1.05V
R128 IV@0_4 FDI_INT_R
[8] FDI_INT
XDP_TDO R414 51/F_4
+1.05V H_CATERR# R141 49.9/F_4 R119 IV@0_4 FDI_LSYNC0_R
[8] FDI_LSYNC0
REV :B Change P/N for EOD H_PROCHOT# R113 68_4 R126 IV@0_4 FDI_LSYNC1_R
[8] FDI_LSYNC1
H_CPURST# R428 *68_4
3
XDP_TMS R112 *51_4 R120 EV@1K_4

+3V XDP_TDI_R R425 *51_4 R122 EV@1K_4
XDP_PREQ# R417 *51_4 R127 EV@1K_4
2 Q16 XDP_TCLK R111 *51_4 R118 EV@1K_4
[8,39] DELAY_VR_PWRGOOD
XDP_TRST# R429 51/F_4 R125 EV@1K_4
FDV301N C295
0.1u/10V_4
1
R162
1K_4 [36] MPWROK 2 R129 +1.5VSUS <The GFX_IMON, FDI_FSYNC[0],
4 H_VTTPWRGD
1
FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1],
2K/F_4 Use a voltage divider with VDDQ and FDI_INT>Note that if these signals
U6 R156 (1.5V) rail (ON in S3) and are left as no connect, there are no
3
2
A R133 1.1K/F_4 A
resistor combination of 4.75K (to functional impacts, but a small amount of
Q15 TC7SH08FU 1K_4
PM_THRMTRIP# 1 3 MMBT3904 PM_DRAM_PWRGD VDDQ)/12K(to GND) to generate the power (~15 mW) maybe wasted.
SYS_SHDN# [38,45] required voltage.
R154 Note: CRB uses a 3.3V (always ON)
3K/F_4 rail with 2K and 1K combination.

PROJECT : ZRB
1A
AUBURNDA 1/4
5 4 3 2 1
5 4 3 2 1

AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3) U24D
U24C
[15] M_B_DQ[63:0] SB_CK[0] W8 M_B_CLK0 [15]

SB_CK#[0] W9 M_B_CLK0# [15]
M_B_DQ0 B5 M3 M_B_CKE0 [15]
M_B_DQ1 SB_DQ[0] SB_CKE[0]
A5 SB_DQ[1]
AA6 M_A_CLK0 [14] M_B_DQ2 C3
SA_CK[0] M_B_DQ3 SB_DQ[2]
SA_CK#[0] AA7 M_A_CLK0# [14] B3 SB_DQ[3] SB_CK[1] V7 M_B_CLK1 [15]
P7 M_A_CKE0 [14] M_B_DQ4 E4 V6 M_B_CLK1# [15]
D [14] M_A_DQ[63:0] SA_CKE[0] SB_DQ[4] SB_CK#[1] D
M_A_DQ0 A10 M_B_DQ5 A6 M2 M_B_CKE1 [15]
M_A_DQ1 SA_DQ[0] M_B_DQ6 SB_DQ[5] SB_CKE[1]
C10 SA_DQ[1] A4 SB_DQ[6]
M_A_DQ2 C7 M_B_DQ7 C4
M_A_DQ3 SA_DQ[2] M_B_DQ8 SB_DQ[7]
A7 SA_DQ[3] SA_CK[1] Y6 M_A_CLK1 [14] D1 SB_DQ[8]
M_A_DQ4 B10 Y5 M_A_CLK1# [14] M_B_DQ9 D2
M_A_DQ5 SA_DQ[4] SA_CK#[1] M_B_DQ10 SB_DQ[9]
D10 SA_DQ[5] SA_CKE[1] P6 M_A_CKE1 [14] F2 SB_DQ[10] SB_CS#[0] AB8 M_B_CS#0 [15]
M_A_DQ6 E10 M_B_DQ11 F1 AD6 M_B_CS#1 [15]
M_A_DQ7 SA_DQ[6] M_B_DQ12 SB_DQ[11] SB_CS#[1]
A8 SA_DQ[7] C2 SB_DQ[12]
M_A_DQ8 D8 M_B_DQ13 F5
F10 SA_DQ[9] SA_CS#[0] AE2 M_A_CS#0 [14] F3 SB_DQ[14]
M_A_DQ10 E6 AE8 M_A_CS#1 [14] M_B_DQ15 G4 AC7 M_B_ODT0 [15]
M_A_DQ11 SA_DQ[10] SA_CS#[1] M_B_DQ16 SB_DQ[15] SB_ODT[0]
F7 SA_DQ[11] H6 SB_DQ[16] SB_ODT[1] AD1 M_B_ODT1 [15]
M_A_DQ12 E9 M_B_DQ17 G2
B7 SA_DQ[13] J6 SB_DQ[18]
M_A_DQ14 E7 AD8 M_A_ODT0 [14] M_B_DQ19 J3
M_A_DQ15 SA_DQ[14] SA_ODT[0] M_B_DQ20 SB_DQ[19]
C6 SA_DQ[15] SA_ODT[1] AF9 M_A_ODT1 [14] G1 SB_DQ[20] M_B_DM[7:0] [15]
M_A_DQ16 H10 M_B_DQ21 G5 D4 M_B_DM0
M_A_DQ17 SA_DQ[16] M_B_DQ22 SB_DQ[21] SB_DM[0] M_B_DM1
G8 SA_DQ[17] J2 SB_DQ[22] SB_DM[1] E1
M_A_DQ18 K7 M_B_DQ23 J1 H3 M_B_DM2
J8 SA_DQ[19] J5 SB_DQ[24] SB_DM[3] K1
M_A_DQ20 G7 M_B_DQ25 K2 AH1 M_B_DM4
G10 SA_DQ[21] M_A_DM[7:0] [14] L3 SB_DQ[26] SB_DM[5] AL2
M_A_DQ22 J7 B9 M_A_DM0 M_B_DQ27 M1 AR4 M_B_DM6
M_A_DQ23 SA_DQ[22] SA_DM[0] M_A_DM1 M_B_DQ28 SB_DQ[27] SB_DM[6] M_B_DM7
J10 SA_DQ[23] SA_DM[1] D7 K5 SB_DQ[28] SB_DM[7] AT8
M_A_DQ24 L7 H7 M_A_DM2 M_B_DQ29 K4
M_A_DQ25 SA_DQ[24] SA_DM[2] M_A_DM3 M_B_DQ30 SB_DQ[29]
M6 SA_DQ[25] SA_DM[3] M7 M4 SB_DQ[30]
M_A_DQ26 M8 AG6 M_A_DM4 M_B_DQ31 N5
M_A_DQ27 SA_DQ[26] SA_DM[4] M_A_DM5 M_B_DQ32 SB_DQ[31]
L9 SA_DQ[27] SA_DM[5] AM7 AF3 SB_DQ[32]
M_A_DQ28 L6 AN10 M_A_DM6 M_B_DQ33 AG1
SA_DQ[28] SA_DM[6] SB_DQ[33] M_B_DQS#[7:0] [15]
M_A_DQ29 K8 AN13 M_A_DM7 M_B_DQ34 AJ3 D5 M_B_DQS#0
M_A_DQ30 SA_DQ[29] SA_DM[7] M_B_DQ35 SB_DQ[34] SB_DQS#[0] M_B_DQS#1
N8 SA_DQ[30] AK1 SB_DQ[35] SB_DQS#[1] F4
M_A_DQ31 P9 M_B_DQ36 AG4 J4 M_B_DQS#2
C M_A_DQ32 SA_DQ[31] M_B_DQ37 SB_DQ[36] SB_DQS#[2] M_B_DQS#3 C
AH5 SA_DQ[32] AG3 SB_DQ[37] SB_DQS#[3] L4
M_A_DQ33 AF5 M_B_DQ38 AJ4 AH2 M_B_DQS#4
SA_DQ[33] M_A_DQS#[7:0] [14] SB_DQ[38] SB_DQS#[4]
DDR SYSTEM MEMORY - B

M_A_DQ34 AK6 C9 M_A_DQS#0 M_B_DQ39 AH4 AL4 M_B_DQS#5
DDR SYSTEM MEMORY A
M_A_DQ35 SA_DQ[34] SA_DQS#[0] M_A_DQS#1 M_B_DQ40 SB_DQ[39] SB_DQS#[5] M_B_DQS#6

AK7 SA_DQ[35] SA_DQS#[1] F8 AK3 SB_DQ[40] SB_DQS#[6] AR5
M_A_DQ36 AF6 J9 M_A_DQS#2 M_B_DQ41 AK4 AR8 M_B_DQS#7
M_A_DQ37 SA_DQ[36] SA_DQS#[2] M_A_DQS#3 M_B_DQ42 SB_DQ[41] SB_DQS#[7]
AG5 SA_DQ[37] SA_DQS#[3] N9 AM6 SB_DQ[42]
M_A_DQ38 AJ7 AH7 M_A_DQS#4 M_B_DQ43 AN2
M_A_DQ39 SA_DQ[38] SA_DQS#[4] M_A_DQS#5 M_B_DQ44 SB_DQ[43]
AJ6 SA_DQ[39] SA_DQS#[5] AK9 AK5 SB_DQ[44]
M_A_DQ40 AJ10 AP11 M_A_DQS#6 M_B_DQ45 AK2
M_A_DQ41 SA_DQ[40] SA_DQS#[6] M_A_DQS#7 M_B_DQ46 SB_DQ[45]
AJ9 SA_DQ[41] SA_DQS#[7] AT13 AM4 SB_DQ[46]
M_A_DQ42 AL10 M_B_DQ47 AM3
SA_DQ[42] SB_DQ[47] M_B_DQS[7:0] [15]
M_A_DQ43 AK12 M_B_DQ48 AP3 C5 M_B_DQS0
M_A_DQ44 SA_DQ[43] M_B_DQ49 SB_DQ[48] SB_DQS[0] M_B_DQS1
AK8 SA_DQ[44] AN5 SB_DQ[49] SB_DQS[1] E3
M_A_DQ45 AL7 M_B_DQ50 AT4 H4 M_B_DQS2
SA_DQ[45] M_A_DQS[7:0] [14] SB_DQ[50] SB_DQS[2]
M_A_DQ46 AK11 C8 M_A_DQS0 M_B_DQ51 AN6 M5 M_B_DQS3
M_A_DQ47 SA_DQ[46] SA_DQS[0] M_A_DQS1 M_B_DQ52 SB_DQ[51] SB_DQS[3] M_B_DQS4
AL8 SA_DQ[47] SA_DQS[1] F9 AN4 SB_DQ[52] SB_DQS[4] AG2
M_A_DQ48 AN8 H9 M_A_DQS2 M_B_DQ53 AN3 AL5 M_B_DQS5
M_A_DQ49 SA_DQ[48] SA_DQS[2] M_A_DQS3 M_B_DQ54 SB_DQ[53] SB_DQS[5] M_B_DQS6
AM10 SA_DQ[49] SA_DQS[3] M9 AT5 SB_DQ[54] SB_DQS[6] AP5
M_A_DQ50 AR11 AH8 M_A_DQS4 M_B_DQ55 AT6 AR7 M_B_DQS7
M_A_DQ51 SA_DQ[50] SA_DQS[4] M_A_DQS5 M_B_DQ56 SB_DQ[55] SB_DQS[7]
AL11 SA_DQ[51] SA_DQS[5] AK10 AN7 SB_DQ[56]
M_A_DQ52 AM9 AN11 M_A_DQS6 M_B_DQ57 AP6
M_A_DQ53 SA_DQ[52] SA_DQS[6] M_A_DQS7 M_B_DQ58 SB_DQ[57]
AN9 SA_DQ[53] SA_DQS[7] AR13 AP8 SB_DQ[58]
M_A_DQ54 AT11 M_B_DQ59 AT9
AP12 SA_DQ[55] AT7 SB_DQ[60]
M_A_DQ56 AM12 M_B_DQ61 AP9
AN12 SA_DQ[57] M_A_A[15:0] [14] AR10 SB_DQ[62] M_B_A[15:0] [15]
M_A_DQ58 AM13 Y3 M_A_A0 M_B_DQ63 AT10 U5 M_B_A0
M_A_DQ59 SA_DQ[58] SA_MA[0] M_A_A1 SB_DQ[63] SB_MA[0] M_B_A1
AT14 SA_DQ[59] SA_MA[1] W1 SB_MA[1] V2
M_A_DQ60 AT12 AA8 M_A_A2 T5 M_B_A2
M_A_DQ61 SA_DQ[60] SA_MA[2] M_A_A3 SB_MA[2] M_B_A3
AL13 SA_DQ[61] SA_MA[3] AA3 SB_MA[3] V3
M_A_DQ62 AR14 V1 M_A_A4 R1 M_B_A4
M_A_DQ63 SA_DQ[62] SA_MA[4] M_A_A5 SB_MA[4] M_B_A5
AP14 SA_DQ[63] SA_MA[5] AA9 [15] M_B_BS#0 AB1 SB_BS[0] SB_MA[5] T8
B M_A_A6 M_B_A6 B
SA_MA[6] V8 [15] M_B_BS#1 W5 SB_BS[1] SB_MA[6] R2
T1 M_A_A7 [15] M_B_BS#2 R7 R6 M_B_A7
SA_MA[7] M_A_A8 SB_BS[2] SB_MA[7] M_B_A8
SA_MA[8] Y9 SB_MA[8] R4
[14] M_A_BS#0 AC3 U6 M_A_A9 R5 M_B_A9
SA_BS[0] SA_MA[9] M_A_A10 SB_MA[9] M_B_A10
[14] M_A_BS#1 AB2 SA_BS[1] SA_MA[10] AD4 [15] M_B_CAS# AC5 SB_CAS# SB_MA[10] AB5
[14] M_A_BS#2 U7 T2 M_A_A11 [15] M_B_RAS# Y7 P3 M_B_A11
SA_BS[2] SA_MA[11] M_A_A12 SB_RAS# SB_MA[11] M_B_A12
SA_MA[12] U3 [15] M_B_WE# AC6 SB_WE# SB_MA[12] R3
AG8 M_A_A13 AF7 M_B_A13
SA_MA[13] M_A_A14 SB_MA[13] M_B_A14
SA_MA[14] T3 SB_MA[14] P5
[14] M_A_CAS# AE1 V9 M_A_A15 N1 M_B_A15
SA_CAS# SA_MA[15] SB_MA[15]
[14] M_A_RAS# AB3 SA_RAS#
[14] M_A_WE# AE9 SA_WE#
Clarksfield/Auburndale Clarksfield/Auburndale
Channel A DQ[15,32,48,54], DM[5] Channel B DQ[16,18,36,42,56,57,60,61,62]

Requires minimum 12mils spacing Requires minimum 12mils spacing
with all other signals, including data signals. with all other signals, including data signals.
A A

PROJECT : ZRB
1A
AUBURNDA 2/4
5 4 3 2 1
5 4 3 2 1

CPU Core Power U24F
VTT Rail Values are AUBURNDALE/CLARKSFIELD PROCESSOR (GRAPHICS POWER)

Auburndal VTT=1.05V
ARD:48A +VCC_CORE Clarksfield VTT=1.1V
CFD:52A
C604 10U/6.3V_8
18A +VGFX_AXG U24G
C653 22U/6.3V_8
AG35
AG34
VCC1 VTT0_1 AH14
AH12
+1.05V 22A
C249 10U/6.3V_8 VCC2 VTT0_2
AG33 VCC3 VTT0_3 AH11 AT21 VAXG1
C607 22U/6.3V_8 AG32 AH10 C694 10U/6.3V_8 AT19 AR22 VCC_AXG_SENSE [42]
D C650 22U/6.3V_8 VCC4 VTT0_4 C693 10U/6.3V_8 VAXG2 VAXG_SENSE D
SENSE
LINES
AG31 VCC5 VTT0_5 J14 AT18 VAXG3 VSSAXG_SENSE AT22 VSS_AXG_SENSE [42]
C673 10U/6.3V_8 AG30 J13 C664 10U/6.3V_8 + C665 C283 C282 AT16
C672 10U/6.3V_8 VCC6 VTT0_6 C306 10U/6.3V_8 VAXG4
AG29 VCC7 VTT0_7 H14 AR21 VAXG5
C196 22U/6.3V_8 AG28 H12 C678 10U/6.3V_8 *330U/2V_7343 IV@22u/6.3V_8 IV@22u/6.3V_8 AR19
C606 22U/6.3V_8 VCC8 VTT0_8 C685 10U/6.3V_8 VAXG6
AG27 VCC9 VTT0_9 G14 AR18 VAXG7
C670 10U/6.3V_8 AG26 G13 C675 10U/6.3V_8 AR16 AM22 GFX_VID0 [42]
C217 10U/6.3V_8 VCC10 VTT0_10 C695 10U/6.3V_8 VAXG8 GFX_VID[0]
AF35 VCC11 VTT0_11 G12 AP21 VAXG9 GFX_VID[1] AP22 GFX_VID1 [42]
GRAPHICS VIDs
C181 22U/6.3V_8 AF34 G11 C696 10U/6.3V_8 AP19 AN22 GFX_VID2 [42]
C250 10U/6.3V_8 VCC12 VTT0_12 C308 10U/6.3V_8 VAXG10 GFX_VID[2]
AF33 VCC13 VTT0_13 F14 AP18 VAXG11 GFX_VID[3] AP23 GFX_VID3 [42]
C195 10U/6.3V_8 AF32 F13 AP16 AM23 GFX_VID4 [42]
C288 10U/6.3V_8 VCC14 VTT0_14 VAXG12 GFX_VID[4]
AF31 VCC15 VTT0_15 F12 AN21 VAXG13 GFX_VID[5] AP24 GFX_VID5 [42]
GRAPHICS
C651 10U/6.3V_8 AF30 F11 AN19 AN24 GFX_VID6 [42]
C648 10U/6.3V_8 VCC16 VTT0_16 C301 330u/2V_7343 VAXG14 GFX_VID[6]
+
AF29 VCC17 VTT0_17 E14 AN18 VAXG15
C669 10U/6.3V_8 AF28 E12 AN16
C652 10U/6.3V_8 VCC18 VTT0_18 + C686 C289 C290 VAXG16
AF27 VCC19 VTT0_19 D14 AM21 VAXG17 GFX_VR_EN AR25 GFX_ON [42]
C605 10U/6.3V_8 AF26 D13 AM19 AT25 GFX_DPRSLPVR [42]
C649 10U/6.3V_8 VCC20 VTT0_20 *330U/2V_7343 IV@10u/6.3V_8 IV@10u/6.3V_8 VAXG18 GFX_DPRSLPVR
1.1V RAIL POWER

AD35 VCC21 VTT0_21 D12 AM18 VAXG19 GFX_IMON AM24 GFX_IMON [42]
C274 10U/6.3V_8 AD34 D11 AM16
C273 10U/6.3V_8 VCC22 VTT0_22 VAXG20 R115 EV@1K_4
AD33 VCC23 VTT0_23 C14 AL21 VAXG21
C251 10U/6.3V_8 AD32 C13 AL19 ARD:3A
C671 10U/6.3V_8 VCC24 VTT0_24 VAXG22
AD31 VCC25 VTT0_25 C12 AL18 VAXG23
C286 10U/6.3V_8 AD30 C11 AL16 CFD:6A
C248 10U/6.3V_8 VCC26 VTT0_26 VAXG24
AD29 VCC27 VTT0_27 B14 AK21 VAXG25 VDDQ1 AJ1 +1.5VSUS
C662 10U/6.3V_8 AD28 B12 AK19 AF1
C280 0.1u/10V_4 VCC28 VTT0_28 VAXG26 VDDQ2 C347 C342 C341 C338
- 1.5V RAILS
AD27 VCC29 VTT0_29 A14 AK18 VAXG27 VDDQ3 AE7
C276 0.1u/10V_4 AD26 A13 AK16 AE4
VCC30 VTT0_30 VAXG28 VDDQ4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
AC35 VCC31 VTT0_31 A12 AJ21 VAXG29 VDDQ5 AC1
+
C284 330u/2V_7343 AC34 A11 AJ19 AB7

VCC32 VTT0_32 VAXG30 VDDQ6
AC33 VCC33 AJ18 VAXG31 VDDQ7 AB4
+
C285 330u/2V_7343 AC32 +1.05V AJ16 Y1

VCC34 VAXG32 VDDQ8
AC31 VCC35 AH21 VAXG33 VDDQ9 W7
POWER
AC30 VCC36 VTT0_33 AF10 AH19 VAXG34 VDDQ10 W4
C AC29 AE10 AH18 U1 C415 C352 C343 + C358 C
VCC37 VTT0_34 R117 EV@1K_4 VAXG35 VDDQ11
AC28 VCC38 VTT0_35 AC10 AH16 VAXG36 VDDQ12 T7
CPU CORE SUPPLY

AC27 AB10 C298 22U/6.3V_8 T4 1U/6.3V_4 22U/6.3V_8 22U/6.3V_8 *330U/2V_7343
VCC39 VTT0_36 VDDQ13
AC26 VCC40 VTT0_37 Y10 VDDQ14 P1
AA35 W10 C305 22U/6.3V_8 N7
VCC41 VTT0_38 VDDQ15
AA34 VCC42 VTT0_39 U10 VDDQ16 N4
+1.05V
DDR3
AA33 VCC43 VTT0_40 T10 VDDQ17 L1
AA32 VCC44 VTT0_41 J12 J24 VTT1_45 VDDQ18 H1
FDI
AA31 VCC45 VTT0_42 J11 J23 VTT1_46
AA30 VCC46 VTT0_43 J16 H25 VTT1_47
AA29 VCC47 VTT0_44 J15
AA28 VCC48
AA27 C296 C691 P10 +1.05V
VCC49 10U/6.3V_8 22u/6.3V_8 VTT0_59
AA26 VCC50 VTT0_60 N10
Y35 L10 C697 10U/6.3V_8
VCC51 VTT0_61 C690 10U/6.3V_8
Y34 VCC52 VTT0_62 K10
Y33 VCC53
Y32 VCC54
Y31 VCC55
Y30 VCC56
1.1V
Y29 VCC57 VTT1_63 J22
Y28 K26 J20 C644 10U/6.3V_8
VCC58 VTT1_48 VTT1_64 C658 10U/6.3V_8
Y27 VCC59 J27 VTT1_49 VTT1_65 J18
PEG & DMI

Y26 VCC60 J26 VTT1_50 VTT1_66 H21
V35 AN33 H_PSI# H_PSI# [39] C309 C692 C297 C307 J25 H20
VCC61 PSI# 10U/6.3V_8 10U/6.3V_8 22u/6.3V_8 22u/6.3V_8 VTT1_51 VTT1_67
V34 H27 H19
POWER
VCC62 VTT1_52 VTT1_68

V33 VCC63 G28 VTT1_53
V32 AK35 H_VID0 H_VID0 [39] G27
VCC64 VID[0] H_VID1 VTT1_54
V31 VCC65 VID[1] AK33
H_VID2
H_VID1 [39] G26 VTT1_55 0.6A
V30 VCC66 VID[2] AK34 H_VID2 [39] F26 VTT1_56
V29 AL35 H_VID3 H_VID3 [39] E26 L26 +1.8V
VCC67 VID[3] VTT1_57 VCCPLL1
CPU VIDS
1.8V
V28 AL33 H_VID4 H_VID4 [39] E25 L27
B VCC68 VID[4] H_VID5 VTT1_58 VCCPLL2 C271 22U/6.3V_8 B
V27 VCC69 VID[5] AM33 H_VID5 [39] VCCPLL3 M26
V26 AM35 H_VID6 H_VID6 [39] C278 4.7U/6.3V_6
VCC70 VID[6] H_DPRSLPVR C223 2.2U/6.3V_6
U35 VCC71 PROC_DPRSLPVR AM34 H_DPRSLPVR [39]
U34 C225 1U/6.3V_4
VCC72 C226 1U/6.3V_4
U33 VCC73
U32 VCC74
U31 VCC75 VTT_SELECT G15
U30 VCC76
U29 H_VTTVID1=Low, 1.1V Clarksfield/Auburndale
VCC77
U28
U27
VCC78 H_VTTVID1=High, 1.05V
VCC79
U26 VCC80
R35 VCC81
R34 VCC82
R33 VCC83
R32 VCC84 ISENSE AN35 I_MON [39]
R31 VCC85
R30 VCC86
R29 R71 100/F_4 +VCC_CORE
VCC87
SENSE LINES
R28 VCC88 VCC_SENSE AJ34 VCCSENSE [39]

R27 AJ35 1 H_VID0 R381 1K_4
VCC89 VSS_SENSE VSSSENSE [39] +1.05V
R26 R70 100/F_4 R386 *1K/F_4
VCC90 1 H_VID1 R380 1K_4
P35 VCC91
P34 B15 VTT_SENSE T64 R385 *1K/F_4
VCC92 VTT_SENSE VSS_SENSE_VTT 1 H_VID2 R382 1K_4
P33 VCC93 VSS_SENSE_VTT A15 T63
P32 R387 *1K/F_4
VCC94 0 H_VID3 R389 *1K/F_4
P31 VCC95
P30 R395 1K_4
VCC96 0 H_VID4 R390 *1K/F_4
P29 VCC97
P28 R396 1K_4
VCC98 1 H_VID5 R393 1K_4
P27 VCC99
P26 R399 *1K/F_4
A VCC100 0 H_VID6 R391 *1K/F_4 A
R397 1K_4
1 H_DPRSLPVR R392 1K_4
R398 *1K/F_4
0 H_PSI# R407 *1K/F_4
R401 1K_4
Note:
For Validating IMVP VR R6451 should be STUFF
HFM_VID : Max 1.4V
and R2N1 NO_STUFF LFM_VID : Min 0.65V PROJECT : ZRB
AUBURNDALE/CLARKSFIELD PROCESSOR (POWER) Size Document Number Rev
1A
AUBURNDA 3/4 (PWR)
Date: Thursday, July 22, 2010 Sheet 6 of 46
5 4 3 2 1
5 4 3 2 1
MaintenancePROCESSOR
AUBURNDALE/CLARKSFIELD and Service(GND)
Guide,Service Manual,Motherboard Schematics for Laptop/notebook
AUBURNDALE/CLARKSFIELD http://mycomp.su/x/
PROCESSOR( RESERVED, CFG)
U24H U24I U24E
AT20 VSS1 VSS81 AE34 RSVD32 AJ13

AT17 VSS2 VSS82 AE33 RSVD33 AJ12
AR31 VSS3 VSS83 AE32 K27 VSS161
AR28 VSS4 VSS84 AE31 K9 VSS162 AP25 RSVD1
AR26 VSS5 VSS85 AE30 K6 VSS163 AL25 RSVD2 RSVD34 AH25
AR24 VSS6 VSS86 AE29 K3 VSS164 AL24 RSVD3 RSVD35 AK26
AR23 VSS7 VSS87 AE28 J32 VSS165 AL22 RSVD4
AR20 VSS8 VSS88 AE27 J30 VSS166 AJ33 RSVD5 RSVD36 AL26
AR17 VSS9 VSS89 AE26 J21 VSS167 AG9 RSVD6 RSVD_NCTF_37 AR2
AR15 VSS10 VSS90 AE6 J19 VSS168 M27 RSVD7
D AR12 VSS11 VSS91 AD10 H35 VSS169 L28 RSVD8 RSVD38 AJ26 D
AR9 VSS12 VSS92 AC8 H32 VSS170 J17 SA_DIMM_VREF RSVD39 AJ27
AR6 VSS13 VSS93 AC4 H28 VSS171 H17 SB_DIMM_VREF
AR3 VSS14 VSS94 AC2 H26 VSS172 G25 RSVD11
AP20 VSS15 VSS95 AB35 H24 VSS173 G17 RSVD12
AP17 VSS16 VSS96 AB34 H22 VSS174 E31 RSVD13 RSVD_NCTF_40 AP1
AP13 VSS17 VSS97 AB33 H18 VSS175 E30 RSVD14 RSVD_NCTF_41 AT2
AP10 VSS18 VSS98 AB32 H15 VSS176
AP7 VSS19 VSS99 AB31 H13 VSS177 RSVD_NCTF_42 AT3
AP4 VSS20 VSS100 AB30 H11 VSS178 RSVD_NCTF_43 AR1
AP2 VSS21 VSS101 AB29 H8 VSS179
AN34 VSS22 VSS102 AB28 H5 VSS180
AN31 VSS23 VSS103 AB27 H2 VSS181
AN23 VSS24 VSS104 AB26 G34 VSS182 RSVD45 AL28
AN20 AB6 G31 CFG0 AM30 AL29
VSS25 VSS105 VSS183 CFG[0] RSVD46
AN17 VSS26 VSS106 AA10 G20 VSS184 AM28 CFG[1] RSVD47 AP30
AM29 VSS27 VSS107 Y8 G9 VSS185 AP31 CFG[2] RSVD48 AP32
AM27 Y4 G6 CFG3 AL32 AL27
VSS28 VSS108 VSS186 CFG4 CFG[3] RSVD49
AM25 VSS29 VSS109 Y2 G3 VSS187 AL30 CFG[4] RSVD50 AT31
AM20 VSS30 VSS110 W35 F30 VSS188 AM31 CFG[5] RSVD51 AT32
AM17 VSS31 VSS111 W34 F27 VSS189 AN29 CFG[6] RSVD52 AP33
AM14 W33 F25 CFG7 AM32 AR33
VSS32 VSS112 VSS190 CFG[7] RSVD53
AM11 VSS33 VSS113 W32 F22 VSS191 AK32 CFG[8] RSVD_NCTF_54 AT33
AM8 W31 F19 AK31 AT34
RESERVED
VSS34 VSS114 VSS192 CFG[9] RSVD_NCTF_55
AM5 VSS35 VSS115 W30 F16 VSS193 AK28 CFG[10] RSVD_NCTF_56 AP35
AM2 VSS36 VSS116 W29 E35 VSS194 AJ28 CFG[11] RSVD_NCTF_57 AR35
AL34 W28 E32 AN30 AR32
AL31
AL23
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
W27
W26
E29
E24
VSS195
VSS196
VSS197
VSS AN32
AJ32
CFG[12]
CFG[13]
CFG[14]
RSVD58
AL20 VSS40 VSS120 W6 E21 VSS198 AJ29 CFG[15] RSVD_TP_59 E15

AL17 VSS41 VSS121 V10 E18 VSS199 AJ30 CFG[16] RSVD_TP_60 F15
C AL12 U8 E13 AK30 A2 C
VSS42 VSS122 VSS200 CFG[17] KEY
AL9 VSS43 VSS123 U4 E11 VSS201 H16 RSVD_TP_86 RSVD62 D15
AL6 VSS44 VSS124 U2 E8 VSS202 RSVD63 C15
AL3 VSS45 VSS125 T35 E5 VSS203 RSVD64 AJ15 TP1
AK29 VSS46 VSS126 T34 E2 VSS204 VSS_NCTF1 AT35 RSVD65 AH15 TP2
AK27 VSS47 VSS127 T33 D33 VSS205 VSS_NCTF2 AT1
AK25 VSS48 VSS128 T32 D30 VSS206 VSS_NCTF3 AR34 TP7 B19 RSVD15
AK20 VSS49 VSS129 T31 D26 VSS207 VSS_NCTF4 B34 TP9 A19 RSVD16
AK17 T30 D9 B2 TP13
NCTF
VSS50 VSS130 VSS208 VSS_NCTF5
AJ31 VSS51 VSS131 T29 D6 VSS209 VSS_NCTF6 B1 TP10 A20 RSVD17
AJ23 VSS52 VSS132 T28 D3 VSS210 VSS_NCTF7 A35 TP11 B20 RSVD18
AJ20 VSS53 VSS133 T27 C34 VSS211 RSVD_TP_66 AA5
AJ17 VSS54 VSS134 T26 C32 VSS212 U9 RSVD19 RSVD_TP_67 AA4
AJ14 VSS55 VSS135 T6 C29 VSS213 T9 RSVD20 RSVD_TP_68 R8
AJ11 VSS56 VSS136 R10 C28 VSS214 RSVD_TP_69 AD3
AJ8 VSS57 VSS137 P8 C24 VSS215 AC9 RSVD21 RSVD_TP_70 AD2
AJ5 VSS58 VSS138 P4 C22 VSS216 AB9 RSVD22 RSVD_TP_71 AA2
AJ2 VSS59 VSS139 P2 C20 VSS217 RSVD_TP_72 AA1
AH35 VSS60 VSS140 N35 C19 VSS218 RSVD_TP_73 R9
AH34 VSS61 VSS141 N34 C16 VSS219 RSVD_TP_74 AG7
AH33 VSS62 VSS142 N33 B31 VSS220 C1 RSVD_NCTF_23 RSVD_TP_75 AE3
AH32 VSS63 VSS143 N32 B25 VSS221 A3 RSVD_NCTF_24
AH31 VSS64 VSS144 N31 B21 VSS222
AH30 VSS65 VSS145 N30 B18 VSS223 RSVD_TP_76 V4
AH29 VSS66 VSS146 N29 B17 VSS224 RSVD_TP_77 V5
AH28 VSS67 VSS147 N28 B13 VSS225 RSVD_TP_78 N2
AH27 VSS68 VSS148 N27 B11 VSS226 J29 RSVD26 RSVD_TP_79 AD5
AH26 VSS69 VSS149 N26 B8 VSS227 J28 RSVD27 RSVD_TP_80 AD7
AH20 VSS70 VSS150 N6 B6 VSS228 RSVD_TP_81 W3
AH17 VSS71 VSS151 M10 B4 VSS229 A34 RSVD_NCTF_28 RSVD_TP_82 W2
AH13 VSS72 VSS152 L35 A29 VSS230 A33 RSVD_NCTF_29 RSVD_TP_83 N3
B B
AH9 VSS73 VSS153 L32 A27 VSS231 RSVD_TP_84 AE5
AH6 VSS74 VSS154 L29 A23 VSS232 C35 RSVD_NCTF_30 RSVD_TP_85 AD9
AH3 VSS75 VSS155 L8 A9 VSS233 B35 RSVD_NCTF_31
AG10 VSS76 VSS156 L5
AF8 VSS77 VSS157 L2 VSS AP34 TP8
AF4 VSS78 VSS158 K34
AF2 K33 AP34 can be NC on CRB; EDS/DG suggestion to GND
VSS79 VSS159
AE35 VSS80 VSS160 K30
Clarksfield/Auburndale Clarksfield/Auburndale
Processor Strapping
1 0 DEFAULT
CFG0 CFG0 R110 *3.01K_NC
(PCI-Epress Single PEG Bifurcation enabled 1
Configuration Select)
CFG3
(PCI-Epress Static Normal Operation Lane Numbers Reversed
1 CFG3 R102 3.01K/F_4
Lane Reversal)
A CFG4 Enabled; An external Display port A
(Embended Disabled; No Physical Display Port device is connected to the Embedded 1 CFG4 R109 *3.01K
Display Port Presence) attached to Embedded Diplay Port Display port
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PROJECT : ZRB
1A
AUBURNDA 4/4
5 4 3 2 1
5 4 3 2 1

IBEX PEAK-M (DMI,FDI,GPIO) AC-coupling CAP place close to PCH
0-ohm resistor place close to PCH IBEX PEAK-M (LVDS,DDI)

U26C
BA18 FDI_TXN0_R R491 IV@0_4
FDI_RXN0 FDI_TXN0 [4]
BC24 BH17 FDI_TXN1_R R499 IV@0_4 U26D
[4] DMI_RXN0 DMI0RXN FDI_RXN1 FDI_TXN1 [4]
BJ22 BD16 FDI_TXN2_R R506 IV@0_4 T48 BJ46
[4] DMI_RXN1 DMI1RXN FDI_RXN2 FDI_TXN2 [4] [24] INT_LVDS_BLON L_BKLTEN SDVO_TVCLKINN
D AW20 BJ16 FDI_TXN3_R R510 IV@0_4 T47 BG46 D
[4] DMI_RXN2 DMI2RXN FDI_RXN3 FDI_TXN3 [4] [24] INT_LVDS_DIGON L_VDD_EN SDVO_TVCLKINP
BJ20 BA16 FDI_TXN4_R R496 IV@0_4
[4] DMI_RXN3 DMI3RXN FDI_RXN4 FDI_TXN4 [4]
BE14 FDI_TXN5_R R505 IV@0_4 Y48 BJ48
FDI_RXN5 FDI_TXN5 [4] [24] INT_LVDS_BRIGHT L_BKLTCTL SDVO_STALLN
BD24 BA14 FDI_TXN6_R R517 IV@0_4 BG48
[4] DMI_RXP0 DMI0RXP FDI_RXN6 FDI_TXN6 [4] SDVO_STALLP
BG22 BC12 FDI_TXN7_R R514 IV@0_4 AB48
[4] DMI_RXP1 DMI1RXP FDI_RXN7 FDI_TXN7 [4] [24] INT_LVDS_EDIDCLK L_DDC_CLK
[4] DMI_RXP2 BA20 DMI2RXP [24] INT_LVDS_EDIDDATA Y45 L_DDC_DATA SDVO_INTN BF45
BG20 BB18 FDI_TXP0_R R493 IV@0_4 BH45
[4] DMI_RXP3 DMI3RXP FDI_RXP0 FDI_TXP0 [4] SDVO_INTP
BF17 FDI_TXP1_R R500 IV@0_4 +3V R149 IV@10K_4 AB46
FDI_RXP1 FDI_TXP1 [4] L_CTRL_CLK
BE22 BC16 FDI_TXP2_R R503 IV@0_4 R150 IV@10K_4 V48
[4] DMI_TXN0 DMI0TXN FDI_RXP2 FDI_TXP2 [4] L_CTRL_DATA
BF21 BG16 FDI_TXP3_R R512 IV@0_4
[4] DMI_TXN1 DMI1TXN FDI_RXP3 FDI_TXP3 [4]
BD20 AW16 FDI_TXP4_R R495 IV@0_4 R170 IV@2.37K/F_4 AP39 T51 SDVO_CTRLCLK R49 IV@0_4
[4] DMI_TXN2 DMI2TXN FDI_RXP4 FDI_TXP4 [4] LVD_IBG SDVO_CTRLCLK HDMI_DDCCLK_SW [17,25]
BE18 BD14 FDI_TXP5_R R509 IV@0_4 AP41 T53 SDVO_CTRLDAT R48 IV@0_4
[4] DMI_TXN3 DMI3TXN FDI_RXP5 FDI_TXP5 [4] LVD_VBG SDVO_CTRLDATA HDMI_DDCDATA_SW [17,25]
BB14 FDI_TXP6_R R515 IV@0_4
FDI_RXP6 FDI_TXP6 [4]
BD22 BD12 FDI_TXP7_R R513 IV@0_4 R132 IV@0_4 AT43
[4] DMI_TXP0 DMI0TXP FDI_RXP7 FDI_TXP7 [4] LVD_VREFH
BH21 R135 IV@0_4 AT42 BG44
[4] DMI_TXP1 DMI1TXP LVD_VREFL DDPB_AUXN
[4] DMI_TXP2 BC20 DMI2TXP DDPB_AUXP BJ44
BD18 BJ14 AU38 INT_HDMI_HPD R171 IV@0_4
[4] DMI_TXP3 DMI3TXP FDI_INT FDI_INT [4] DDPB_HPD HDMI_HP [17,25]
LVDS
[24] INT_TXLCLKOUT- INT_TXLCLKOUT- AV53
DMI
FDI
INT_TXLCLKOUT+ AV51 LVDSA_CLK# INT_HDMITX2N_R C275 IV@0.1u/10V_4_X7R
FDI_FSYNC0 BF13 FDI_FSYNC0 [4] [24] INT_TXLCLKOUT+ LVDSA_CLK DDPB_0N BD42 INT_HDMITX2N [25]
BH25 BC42 INT_HDMITX2P_R C272 IV@0.1u/10V_4_X7R
DMI_ZCOMP DDPB_0P INT_HDMITX2P [25]
BH13 INT_TXLOUT0- BB47 BJ42 INT_HDMITX1N_R C269 IV@0.1u/10V_4_X7R
FDI_FSYNC1 FDI_FSYNC1 [4] [24] INT_TXLOUT0- LVDSA_DATA#0 DDPB_1N INT_HDMITX1N [25]
Digital Display Interface

+1.05V R480 49.9/F_4 BF25 INT_TXLOUT1- BA52 BG42 INT_HDMITX1P_R C270 IV@0.1u/10V_4_X7R
DMI_IRCOMP [24] INT_TXLOUT1- LVDSA_DATA#1 DDPB_1P INT_HDMITX1P [25]
BJ12 INT_TXLOUT2- AY48 BB40 INT_HDMITX0N_R C281 IV@0.1u/10V_4_X7R
FDI_LSYNC0 FDI_LSYNC0 [4] [24] INT_TXLOUT2- LVDSA_DATA#2 DDPB_2N INT_HDMITX0N [25]
AV47 BA40 INT_HDMITX0P_R C279 IV@0.1u/10V_4_X7R
LVDSA_DATA#3 DDPB_2P INT_HDMITX0P [25]
BG14 AW38 INT_HDMICLK-_R C257 IV@0.1u/10V_4_X7R
FDI_LSYNC1 FDI_LSYNC1 [4] DDPB_3N INT_HDMICLK- [25]
[24] INT_TXLOUT0+ INT_TXLOUT0+ BB48 BA38 INT_HDMICLK+_R C266 IV@0.1u/10V_4_X7R
LVDSA_DATA0 DDPB_3P INT_HDMICLK+ [25]
[24] INT_TXLOUT1+ INT_TXLOUT1+ BA50
INT_TXLOUT2+ LVDSA_DATA1
C [24] INT_TXLOUT2+ AY49 LVDSA_DATA2 C
AV48 LVDSA_DATA3 DDPC_CTRLCLK Y49
DDPC_CTRLDATA AB49
AP48 LVDSB_CLK#
XDP_DBRST# T6 J12 AP47 BE44
[4] XDP_DBRST# SYS_RESET# WAKE# PCIE_WAKE# [26,28] LVDSB_CLK DDPC_AUXN
DDPC_AUXP BD44
AY53 LVDSB_DATA#0 DDPC_HPD AV40
SYS_PWROK M6 Y1 AT49
SYS_PWROK CLKRUN# / GPIO32 CLKRUN# [36] LVDSB_DATA#1
AU52 LVDSB_DATA#2 DDPC_0N BE40
AT53 BD40
System Power Management
LVDSB_DATA#3 DDPC_0P
B17 PWROK DDPC_1N BF41
AY51 LVDSB_DATA0 DDPC_1P BH41
AT48 LVDSB_DATA1 DDPC_2N BD38
K5 MEPWROK SUS_STAT# / GPIO61 P8 AU50 LVDSB_DATA2 DDPC_2P BC38
AT51 LVDSB_DATA3 DDPC_3N BB36
DDPC_3P BA36
RSV_ICH_LAN_RST# A10 F3
LAN_RST# SUSCLK / GPIO62 ICH_SUSCLK [36]
REV : B R244 SHORT INT_CRT_BLU AA52 U50
[24] INT_CRT_BLU CRT_BLUE DDPD_CTRLCLK
D9 E4 INT_CRT_GRN AB53 U52
[4] PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 [24] INT_CRT_GRN CRT_GREEN DDPD_CTRLDATA
INT_CRT_RED AD53
[24] INT_CRT_RED CRT_RED
[36] ICH_RSMRST# C16 RSMRST# SLP_S4# H7 SUSC# [36] DDPD_AUXN BC46

[24] INT_CRT_DDCCLK V51 CRT_DDC_CLK DDPD_AUXP BD46 R place close to PCH
[24] INT_CRT_DDCDAT V53 CRT_DDC_DATA DDPD_HPD AT38
SUS_PWR_ACK_R M1 P12 R465 IV@150_4INT_CRT_BLU
SUS_PWR_DN_ACK / GPIO30 SLP_S3# SUSB# [36]
B DDPD_0N BJ40 B
Y53 BG40 R466 IV@150_4INT_CRT_GRN
[24] INT_HSYNC CRT_HSYNC DDPD_0P
P5 K8 SLP_M# R235 *0_4 Y51 BJ38
[36] DNBSWON# PWRBTN# SLP_M# [24] INT_VSYNC CRT_VSYNC DDPD_1N
BG38 R467 IV@150_4INT_CRT_RED
DDPD_1P
CRT
DDPD_2N BF37
R258 *0_4 ACIN_R P7 N2 TP18 DAC_IREF AD48 BH37
[36] PCH_ACIN ACPRESENT / GPIO31 TP23 DAC_IREF DDPD_2P
AB51 CRT_IRTN DDPD_3N BE36
DDPD_3P BD36
PM_BATLOW# A6 BJ10 R161
BATLOW# / GPIO72 PMSYNCH PM_SYNC [4]
1K/F_4 IbexPeak-M_R1P0
PM_RI# F14 F6 PM_SLP_LAN# TP6

RI# SLP_LAN# / GPIO29
IbexPeak-M_R1P0
PCH Pull-high/low System PWR_OK

+3V_S5
+3V
PM_RI# R200 10K_4

CLKRUN# R532 8.2K_4 +3V_S5
PM_BATLOW# R523 10K_4 DELAY_VR_PWRGOOD need PU 2K to +3V.
XDP_DBRST# R236 1K_4 C703 *.1u_4
A
PCIE_WAKE# R240 10K_4
PU at power side A
5
ICH_RSMRST# R507 10K_4 PM_SLP_LAN# R260 *10K_4 1 DELAY_VR_PWRGOOD [4,39]
SYS_PWROK 4
RSV_ICH_LAN_RST# R516 10K_4 SUS_PWR_ACK_R R536 10K_4 2
U28
PWROK_EC [36]
3
SYS_PWROK R502 10K_4 ACIN_R R237 10K_4 R546 100K_4
TC7SH08FU
PROJECT : ZRB
1A
IBEX PEAK-M 1/6
5 4 3 2 1
5 4 3 2 1

RTC Circuitry C364 15p/50V_4
2
1
+VCCRTC
CR1 Y1 R207
+3VPCU U26A
R508 20K/F_4 RTC_RST# 32.768KHZ 10M_4
VCCRTC_1
3
4
1
RTC_X1 B13 D33
RTCX1 FWH0 / LAD0 LPC_LAD0 [28,36]
BAT54C C709 J3 C362 15p/50V_4 RTC_X2 D13 B33
RTCX2 FWH1 / LAD1 LPC_LAD1 [28,36]
R478 1u/10V_4 *SHORT_ PAD1 C32
FWH2 / LAD2 LPC_LAD2 [28,36]
1K_4 A32 LPC_LAD3 [28,36]
2
RTC_RST# FWH3 / LAD3
C14 RTCRST#
FWH4 / LFRAME# C34 LPC_LFRAME# [28,36]
BT1 SRTC_RST# D17
D
R501 20K/F_4 SRTC_RST# SRTCRST# D
1 A34
RTC
LPC
1 R504 1M_4 SM_INTRUDER# A16 LDRQ0#
2 2 +VCCRTC INTRUDER# LDRQ1# / GPIO23 F34
1
R232 10K_4 +3V
RTC_CONN C710 C708 J2 PCH_INVRMEN A14 AB9
INTVRMEN SERIRQ IRQ_SERIRQ [36]
1u/10V_4 1u/10V_4 *SHORT_ PAD1
2
HDA_SYNC (PCH strap pin) ACZ_BIT_CLK A30 HDA_BCLK SATA_RXN0_C
SATA0RXN AK7 SATA_RXN0_C [29]
Internal weak pull-down ACZ_SYNC D29 AK6 SATA_RXP0_C SATA_RXP0_C [29]
HDA_SYNC SATA0RXP
VCCVRM=>+1.8V (default) SATA0TXN AK11 SATA_TXN0 [29]
external pull-up SPKR P1 AK9 SATA_TXP0 [29]
[30] SPKR SPKR SATA0TXP
VCCVRM=>+1.5V ACZ_RST# C30 HDA_RST#
AH6 SATA_RXN1_C SATA_RXN1_C [29]
SATA1RXN SATA_RXP1_C
SATA1RXP AH5 SATA_RXP1_C [29]
[30] PCH_AZ_CODEC_SDIN0 G30 HDA_SDIN0 SATA1TXN AH9 SATA_TXN1 [29]
SATA1TXP AH8 SATA_TXP1 [29]
F30 HDA_SDIN1
SATA2RXN AF11
E32 AF9
IHDA
HDA_SDIN2 SATA2RXP
SATA2TXN AF7
F32 HDA_SDIN3 SATA2TXP AF6 Note:
SATA port2/3 may not be available on all PCH sku
AH3
ACZ_SDOUT B29
SATA3RXN
AH1
(HM55 support 3 port only)
HDA_SDO SATA3RXP
SATA3TXN AF3
SATA3TXP AF1
PCH_GPIO33 H32
SATA
HDA_DOCK_EN# / GPIO33
SATA4RXN AD9
+3V_S5 R494 *10K_4 J30 AD8
HDA_DOCK_RST# / GPIO13 SATA4RXP
SATA4TXN AD6
AD5
HDA Bus SATA4TXP
M3 JTAG_TCK SATA5RXN AD3
SATA5RXP AD1
K3 JTAG_TMS SATA5TXN AB3
C R490 33_4 ACZ_SYNC AB1 C
[30] PCH_AZ_CODEC_SYNC SATA5TXP
K1 JTAG_TDI
JTAG
R484 33_4 ACZ_RST# J2 AF16
[30] PCH_AZ_CODEC_RST# JTAG_TDO SATAICOMPO
J4 AF15 R199 37.4/F_4 +1.05V
R492 33_4 ACZ_SDOUT TRST# SATAICOMPI
[30] PCH_AZ_CODEC_SDOUT
R487 33_4 ACZ_BIT_CLK SPI_CLK_R BA2

[30] PCH_AZ_CODEC_BITCLK SPI_CLK
SPI_CS0#_R AV3
C704 SPI_CS0#
*27p_4 +3VPCU R553 *10K_4 SPI_CS1# AY3 T3
SPI_CS1# SATALED# SATA_ACT# [33]
SPI_SI_R AY1 Y9 R252 43K/F_4 +3V

SPI_MOSI SATA0GP / GPIO21
SPI
SPI_SO_R AV1 V1 R530 43K/F_4 +3V
SPI_MISO SATA1GP / GPIO19
IbexPeak-M_R1P0
PCH Strap Pin Configuration Table-1

INTVRMEN Integrated 1.05V VRM 1 = Integrated VRM is enabled
R511 330K_6 PCH_INVRMEN
Enable / Disable 0 = Integrated VRM is disabled +VCCRTC
SPI_MOSI TPM Functionality 1 = Enabled

R551 *1K_4 SPI_SI_R
Disable 0 = Disable +3V
PCH SPI 0 = Default Mode (Internal weak Pull-down)
SPKR Reboot option at 1 = No Reboot Mode with TCO Disabled
+3V R538 *1K/F_4 SPKR
power-up
0 = Flash Descriptor Security will be overridden
B B
HDA_DOCK_EN Flash Descriptor 1 = Security measure defined in the Flash
Descriptor will be enabled. PCH_GPIO33 J1 1 2 *SHORT_ PAD1
#/GPIO33 Security Override
+3V
U29
SPI_CS0#_R 1 8 R158 1K_4 +3V
SPI_CLK_R CE# VDD R152 1K_4
6 SCK GNT0#, (0,0) = LPC (0,1) = Reserved NAND
SPI_SI_R 5 Boot BIOS Strap [10] PCI_GNT0# R153 *1K_4
SPI_SO_R 2
SI
7 R547 3.3K/F_4 GNT1# (1,0) = PCI (1,1) = SPI R159 *1K_4
SO HOLD# [10] PCI_GNT1#
+3V R552 3.3K/F_4 3 4 GNT2#/ ESI compatible mode is for server

WP# VSS C721 ESI Strap platforms only
W25Q32BVSSIG .1u/10V_4 GPIO53 [10] PWM_SELECT# R182 *1K/F_4
(Server Only)
GNT3#/ Top-Block 0 = Top Block Swap Mode

[10] PCI_GNT3# R462 *10K/F_4
GPIO55 Swap Override 1 = Default Mode (Internal pull-up)
IntelR Anti-Theft Technology
HDD Data Protection 1 = Enabled
NV_ALE [10] NV_ALE R213 *1K/F_4 +1.8V
(Intel AT-d) Enable 0 = Disabled (Default)
NV_CLE DMI Termination DMI termination voltage. Weak

[10] NV_CLE R216 *1K/F_4 +1.8V
Voltage internal pull-up. Do not pull low.
GPIO8 Reserved This signal has a weak internal pull up.

[11] RSV_GPIO8 R215 10K_4 +3V_S5
NOTE: This signal should not be pulled low
R214 *1K_4
0 = Intel ME Crypto Transport Layer Security

GPIO15 Reserved (TLS) cipher suite with no confidentiality
A [11] CR_WAKE# R256 1K_4 +3V_S5 A
1 = Intel ME Crypto Transport Layer Security
(TLS) cipher suite with confidentiality
GPIO27 On-Die PLL Voltage 0 = Disables the VccVRM.

Regulator 1 = Enables the internal VccVRM to have
<internal weak pull-up> a clean supply for analog rails. [11] PCH_GPIO27 R231 *10K_4

PROJECT : ZRB
1A
IBEX PEAK-M 2/6
5 4 3 2 1
5 4 3 2 1
U26B
U26E
H40 AY9 BG30 B9 RSV_SMBALERT#
AD0 NV_CE#0 [26] PCIE_RX1- PERN1 SMBALERT# / GPIO11
N34 AD1 NV_CE#1 BD1 [26] PCIE_RX1+ BJ30 PERP1
C44 AP15 C701 0.1u/10V_4_X7R PCIE_TXN1_C BF29 H14 ICH_SMBCLK
A38
AD2 NV_CE#2
BD8
Wireless [26] PCIE_TX1-
C702 0.1u/10V_4_X7R PCIE_TXP1_C BH29
PETN1 SMBCLK ICH_SMBCLK [3]
AD3 NV_CE#3 [26] PCIE_TX1+ PETP1
C36 C8 ICH_SMBDATA
AD4 SMBDATA ICH_SMBDATA [3]
J34 AD5 NV_DQS0 AV9 AW30 PERN2
A40 AD6 NV_DQS1 BG8 BA30 PERP2
D45 BC30 J14 RSV_SML0ALERT#
D AD7 PETN2 SML0ALERT# / GPIO60 D
E36 AD8 NV_DQ0 / NV_IO0 AP7 BD30 PETP2
H48 AP6 C6 SMB_CLK_ME0
AD9 NV_DQ1 / NV_IO1 SML0CLK
E40 AT6 AU30
SMBus
AD10 NV_DQ2 / NV_IO2 PERN3 SMB_DATA_ME0
C40 AD11 NV_DQ3 / NV_IO3 AT9 AT30 PERP3 SML0DATA G8
M48 AD12 NV_DQ4 / NV_IO4 BB1 AU32 PETN3
M45 AD13 NV_DQ5 / NV_IO5 AV6 AV32 PETP3
F53 BB3 M14 RSV_SML1ALERT# R254 *0_4
AD14 NV_DQ6 / NV_IO6 SML1ALERT# / GPIO74 SML1ALERT# [11,35,36]
M40 AD15 NV_DQ7 / NV_IO7 BA4 BA32 PERN4 SMB_CLK_ME1
NVRAM
M43 AD16 NV_DQ8 / NV_IO8 BE4 BB32 PERP4 SML1CLK / GPIO58 E10
J36 AD17 NV_DQ9 / NV_IO9 BB6 BD32 PETN4
K48 BD6 BE32 G12 SMB_DATA_ME1
AD18 NV_DQ10 / NV_IO10 PETP4 SML1DATA / GPIO75
F40 BB7
PCI-E*
AD19 NV_DQ11 / NV_IO11
C42 AD20 NV_DQ12 / NV_IO12 BC8 BF33 PERN5
K46 BJ8 BH33 T13 CL_CLK1
AD21 NV_DQ13 / NV_IO13 PERP5 CL_CLK1 CL_CLK1 [28]
Controller
M51 AD22 NV_DQ14 / NV_IO14 BJ6 BG32 PETN5
J52 BG6 BJ32 T11 CL_DATA1
AD23 NV_DQ15 / NV_IO15 PETP5 CL_DATA1 CL_DATA1 [28]
K51
Link
AD24 NV_ALE CL_RST1#
L34 AD25 NV_ALE BD3 NV_ALE [9] [28] PCIE_RX6- BA34 PERN6 CL_RST1# T9 CL_RST1# [28]
F42 AY6 NV_CLE AW34
AD26 NV_CLE NV_CLE [9] [28] PCIE_RX6+ PERP6
J40 C316 0.1u/10V_4_X7R PCIE_TXN6_C BC34
G46
AD27 LAN [28] PCIE_TX6-
C320 0.1u/10V_4_X7R PCIE_TXP6_C BD34
PETN6
AD28 [28] PCIE_TX6+ PETP6
F44 AD29 NV_RCOMP AU2 NV_RCOMP R519 *32.4/F_4
PEG_A_CLKRQ# / GPIO47 H1 PEG_CLKREQ#_R
M47 AD30 AT34 PERN7
PCI
H36 AD31 NV_RB# AV7 AU34 PERP7
AU36 PETN7 CLKOUT_PEG_A_N AD43 CLK_PCIE_VGA# [16]
J50 C/BE0# NV_WR#0_RE# AY8 AV36 PETP7 CLKOUT_PEG_A_P AD45 CLK_PCIE_VGA [16]
G42 C/BE1# NV_WR#1_RE# AY5
H47 C/BE2# BG34 PERN8 CLKOUT_DMI_N AN4 CLK_PCIE_3GPLL# [4]
PEG
G34 C/BE3# NV_WE#_CK0 AV11 BJ34 PERP8 CLKOUT_DMI_P AN2 CLK_PCIE_3GPLL [4]
NV_WE#_CK1 BF5 BG36 PETN8
PCI_PIRQA# G38 BJ36
PCI_PIRQB# PIRQA# PETP8
H51 PIRQB# CLKOUT_DP_N / CLKOUT_BCLK1_N AT1 DPLL_REF_SSCLK# [4]
PCI_PIRQC# B37 H18 Port1 and port9 can be used on debug mode AT3 DPLL_REF_SSCLK [4]
PCI_PIRQD# PIRQC# USBP0N CLKOUT_DP_P / CLKOUT_BCLK1_P
A44 PIRQD# USBP0P J18 AK48 CLKOUT_PCIE0N
USBP1N A18 USBP1- [34] AK47 CLKOUT_PCIE0P
From CLK BUFFER

PCI_REQ0# F51 C18 MB USB AW24
C REQ0# USBP1P USBP1+ [34] CLKIN_DMI_N CLK_BUF_PCIE_3GPLL# [3] C
PCI_REQ1# A46 N20 CLK_PCIE_REQ0# P9 BA24
REQ1# / GPIO50 USBP2N PCIECLKRQ0# / GPIO73 CLKIN_DMI_P CLK_BUF_PCIE_3GPLL [3]
dGPU_SELECT# B45 P20
PCI_REQ3# REQ2# / GPIO52 USBP2P
M53 REQ3# / GPIO54 USBP3N J20
USBP3P L20 AM43 CLKOUT_PCIE1N CLKIN_BCLK_N AP3 CLK_BUF_BCLK# [3]
PCI_GNT0# F48 F20 EHCI1 AM45 AP1
[9] PCI_GNT0# GNT0# USBP4N USBP4- [34] CLKOUT_PCIE1P CLKIN_BCLK_P CLK_BUF_BCLK [3]
PCI_GNT1# K45 G20 BLUETOOTH
[9] PCI_GNT1# GNT1# / GPIO51 USBP4P USBP4+ [34]
PWM_SELECT# F36 A20 TP16 CLK_PCIE_REQ1#_R U4
[9] PWM_SELECT# GNT2# / GPIO53 USBP5N PCIECLKRQ1# / GPIO18
PCI_GNT3# H53 C20 TP17 F18
[9] PCI_GNT3# GNT3# / GPIO55 USBP5P CLKIN_DOT_96N CLK_BUF_DREFCLK# [3]
USBP6N M22 CLKIN_DOT_96P E18 CLK_BUF_DREFCLK [3]
PCI_PIRQE# B41 N22 USB port6/7 may not be available on all PCH sku AM47
PIRQE# / GPIO2 USBP6P [28] CLK_PCH_SRC2# CLKOUT_PCIE2N
PCI_PIRQF# K53 B21 (HM55 support 12port only) AM48
PIRQF# / GPIO3 USBP7N [28] CLK_PCH_SRC2 CLKOUT_PCIE2P
PCI_PIRQG# A36 D21 AH13
PIRQG# / GPIO4 USBP7P CLKIN_SATA_N / CKSSCD_N CLK_BUF_DREFSSCLK# [3]
PCI_PIRQH# A48 H22 [28] PCIE_CLK_REQ2# R537 *Short_4 CLK_PCIE_REQ2#_R N4 AH12
PIRQH# / GPIO5 USBP8N USBP8- [24] PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P CLK_BUF_DREFSSCLK [3]
USBP8P J22 USBP8+ [24] Camera
USB
PCI_RST# K6 E22 REV : B Change to short pad

[28] PCI_RST# PCIRST# USBP9N USBP9- [34]
USBP9P F22 USBP9+ [34] USB/B-USB1-2 AH42 CLKOUT_PCIE3N REFCLK14IN P41 CLK_ICH_14M [3]
PCI_SERR# E44 A22 TP15 AH41
PCI_PERR# SERR# USBP10N CLKOUT_PCIE3P C683 27p/50V_4
E50 PERR# USBP10P C22 TP14
G24 EHCI2 CLK_PCIE_REQ3# A8 J42 CLK_PCI_FB
USBP11N USBP11- [34] PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK
USBP11P H24 USBP11+ [34] USB/B-USB1-1
1
PCI_IRDY# A42 L24
IRDY# USBP12N USBP12- [32]
H44 M24 Card Reader AM51 AH51 XTAL25_IN R468 Y5
PAR USBP12P USBP12+ [32] CLKOUT_PCIE4N XTAL25_IN
PCI_DEVSEL# F46 A24 AM53 AH53 XTAL25_OUT 1M_4 25MHz
DEVSEL# USBP13N USBP13- [28] CLKOUT_PCIE4P XTAL25_OUT
PCI_FRAME# C46 C24 Mini Card (WLAN)
USBP13+ [28]
2
FRAME# USBP13P CLK_PCIE_REQ4# M9 PCIECLKRQ4# / GPIO26 XCLK_RCOMP AF38 XCLK_RCOMP R167 90.9/F_4 +1.05V C682 27p/50V_4
PCI_PLOCK# D49 PLOCK#
USBRBIAS# B25 USB_BIAS R497 22.6/F_4
PCI_STOP# D41 AJ50 T45 BOARD_ID1
PCI_TRDY# STOP# CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64
C48 TRDY# USBRBIAS D25 AJ52 CLKOUT_PCIE5P
ICH_PME# M7 CLK_PCIE_REQ5# H6 P43 BOARD_ID2
Clock Flex
TP5 PME# PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65
N16 USB_OC0#
OC0# / GPIO59 USB_OC0# [34]
PCI_PLTRST# D5 J16 USB_OC1#
PLTRST# OC1# / GPIO40 USB_OC2# BOARD_ID3
OC2# / GPIO41 F16 [26] CLK_PCIE_LOM# AK53 CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66 T42
R464 22_4 CLK_LPC_DEBUG_C N52 L16 USB_OC3# AK51
[28] CLK_LPC_DEBUG CLKOUT_PCI0 OC3# / GPIO42 [26] CLK_PCIE_LOM CLKOUT_PEG_B_P
TP12 CLK_PCI_PCCARD P53 E14 USB_OC4_5#
B CLKOUT_PCI1 OC4# / GPIO43 USB_OC4_5# [34] B
R157 22_4 CLK_PCI_775_C P46 G16 [26] CLK_PCIE_LAN_REQ# P13 N50 dGPU_EDIDSEL# R151 *10K_4 +3V
[36] CLK_PCI_775 CLKOUT_PCI2 OC5# / GPIO9 PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67
CLK_PCI_FB R146 22_4 CLK_PCI_FB_C P51 F12 USB_OC6#
CLKOUT_PCI3 OC6# / GPIO10 USB_OC7#
P48 CLKOUT_PCI4 OC7# / GPIO14 T15 REV : B R243 SHORT
IbexPeak-M_R1P0
IbexPeak-M_R1P0
R163 stuff/R442 non stuff for SMT debug

+3V +3V_S5
+3V_S5
+3V_S5 R441 SP@10K_4 BOARD_ID1 R160 SP@10K_4
RP2 R257 10K_4 CLK_PCIE_REQ0#
USB_OC3# 6 5 R522 10K_4 CLK_PCIE_REQ3# R442 *10K_4 BOARD_ID2 R163 10K_4 R203
USB_OC2# 7 4 USB_OC1# R239 10K_4 CLK_PCIE_REQ4#
2
USB_OC4_5# 8 3 USB_OC0# R259 10K_4 CLK_PCIE_REQ5# R443 *10K_4 BOARD_ID3 R444 10K_4 2.2K_4
+3V_S5 9 2 USB_OC6# R242 10K_4 CLK_PCIE_LAN_REQ#
10 1 USB_OC7# R526 IV@10K_4 PEG_CLKREQ#_R 1 3 SMB_CLK_ME1
+3V_S5 [36] 2ND_MBCLK
Q1
8.2K_10P8R +3V 2N7002K
C395 R540 10K_4 CLK_PCIE_REQ1#_R High = Capilano +3V_S5

+3V BOARD_ID1
.1u/10V_4 RP4 +3V Low = Madsion or other GPUs
PCI_PIRQD# 6 5
5
PCI_REQ1# 7 4 PCI_REQ3# High = 80port output to LPC

PCI_PLTRST# 2 PCI_FRAME# 8 3 PCI_PIRQB# BOARD_ID2 R204
4 PCI_TRDY# 9 2 PCI_REQ0# R164 10K_4 dGPU_SELECT# Low = 80port output to PCI
PLTRST# [4,11,26,28,32,36]
2
R261 *0_4 1 +3V 10 1 PCI_PIRQH# R165 8.2K_4 PCI_PIRQE# 2.2K_4
A R463 8.2K_4 PCI_PIRQF# High = Reserved A
U8 R262 8.2K_10P8R R169 8.2K_4 PCI_PIRQG# BOARD_ID3 1 3 SMB_DATA_ME1
[36] 2ND_MBDATA
3
TC7SH08FU R527 10K_4 CLK_PCIE_REQ2#_R Low = Reserved (Default) Q2

100K_4 EC1 2N7002K
+3V *0.1u/10V_4 R535 EV@10K/F_4 PEG_CLKREQ#_R
RP1
R265 *0_4 PCI_PIRQC# 6 5
PCI_PIRQA# 7 4 PCI_DEVSEL#
PCI_STOP# 8 3 PCI_PLOCK# +3V_S5
R264 PCI_IRDY# 9 2 PCI_PERR#
10K_4 +3V 10 1 PCI_SERR# R518
R220
10K_4
10K_4
RSV_SMBALERT#
RSV_SML0ALERT#
8.2K_10P8R R255 10K_4 RSV_SML1ALERT#
R521 2.2K_4 ICH_SMBCLK PROJECT : ZRB
R520 2.2K_4 ICH_SMBDATA Size Document Number Rev
+3V R225 2.2K_4 SMB_CLK_ME0 1A
R222 2.2K_4 SMB_DATA_ME0 IBEX PEAK-M 3/6
Date: Friday, July 23, 2010 Sheet 10 of 46
5 4 3 2 1
5 4 3 2 1

GPU RST#
D R267 EV@0_4 D
IBEX PEAK-M (GPIO,VSS_NCTF,RSVD)
U26F
+3V
[24] LCD_DETECT LCD_DETECT Y3 AH45 *.1u_4
BMBUSY# / GPIO0 CLKOUT_PCIE6N C408
CLKOUT_PCIE6P AH46 [4,10,26,28,32,36] PLTRST#
[36] SIO_EXT_SMI# SIO_EXT_SMI# C38 GPU_RST# [16]
TACH1 / GPIO1
5
1
[36] SIO_EXT_SCI# SIO_EXT_SCI# D37 4
TACH2 / GPIO6
CLKOUT_PCIE7N AF48 2dGPU_HOLD_RST#
MISC
BOARD_ID0 J32 AF47
3
TACH3 / GPIO7 CLKOUT_PCIE7P U9
RSV_GPIO8 F10 *TC7SH08FU R246
[9] RSV_GPIO8 GPIO8
*100K_4
LAN_DISABLE# K9 U2
LAN_PHY_PWR_CTRL / GPIO12 A20GATE SIO_A20GATE [36]
CR_WAKE# T7
[9] CR_WAKE# GPIO15
dGPU_HOLD_RST# AA2 AM3
SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLK_CPU_BCLK# [4]
[19] dGPU_PWROK F38 TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P AM1 CLK_CPU_BCLK [4]
GPIO22 Y7 BG10
SCLOCK / GPIO22 PECI H_PECI [4]
GPIO
H10 T1
GPIO Pull-up/Pull-down
GPIO24 RCIN# SIO_RCIN# [36]
PCH_GPIO27 AB12 BE10
[9] PCH_GPIO27 GPIO27 PROCPWRGD H_PWRGOOD [4]
CPU
+3V_S5
TP_PCH_GPIO28 V13 BD10 PCH_THRMTRIP#_R R208 56/F_4
GPIO28 THRMTRIP# PM_THRMTRIP# [4]
C C
STP_PCI# M11 R211 56/F_4 +1.05V
STP_PCI# / GPIO34 TP_PCH_GPIO28 R251 10K_4
V6 GPIO45 R525 10K_4
[19,43] dGPU_VRON SATACLKREQ# / GPIO35 RST_GATE# R524 10K_4
dGPU_PWR_EN# AB7 BA22 GPIO57 R218 *10K_4
SATA2GP / GPIO36 TP1 LAN_DISABLE# R241 10K_4
dGPU_PRSNT# AB13 AW22
SATA3GP / GPIO37 TP2 +3V
dGPU_PWR_EN# should be stable GPIO38 V3 BB22
before dGPU_VRON enable SLOAD / GPIO38 TP3 SIO_EXT_SMI# R172 10K_4
SAVE_LED# P3 AY45 SIO_EXT_SCI# R483 10K_4
SDATAOUT0 / GPIO39 TP4 dGPU_PWR_EN# R233 10K_4
GPIO45 H3 AY46 dGPU_PWROK R175 *10K_4
PCIECLKRQ6# / GPIO45 TP5
RST_GATE# F1 AV43
PCIECLKRQ7# / GPIO46 TP6
REV : B Change to short pad
SV_SET_UP AB6 AV45 +3V
SDATAOUT1 / GPIO48 TP7
[10,35,36] SML1ALERT# R533 *Short_4 SATA5GP AA4 AF13 SIO_RCIN# R539 10K_4
SATA5GP / GPIO49 TP8 SIO_A20GATE R529 10K_4
EC suggestion use GPIO49 for FAN control GPIO57 F8 M18 dGPU_HOLD_RST# R542 *10K_4
GPIO57 TP9 SATA5GP R543 10K_4
N18 GPIO22 R234 10K_4
TP10
A4 AJ24 SAVE_LED# R528 10K_4
VSS_NCTF_1 TP11 STP_PCI# R238 10K_4
A49
NCTF
VSS_NCTF_2
RSVD
SATA5GP / GPIO49 / TEMP_ALERT# is used to A5 VSS_NCTF_3 TP12 AK41

A50 GPIO38 R541 10K_4
alert for EC when CPU or Graph/Memory A52
VSS_NCTF_4
AK42
controllers' temperature go out of limit. VSS_NCTF_5 TP13 LCD_DETECT R531 *8.2K_4
B A53 VSS_NCTF_6 B
So connecting GPIO49 to EC and avoid this B2 VSS_NCTF_7 TP14 M32
B4 SV_SET_UP R253 10K_4
pin to be used for other purpose B52
VSS_NCTF_8
N32
VSS_NCTF_9 TP15
B53 VSS_NCTF_10
BE1 VSS_NCTF_11 TP16 M30 SV_SET_UP 1-X High = Strong (Default)
BE53 VSS_NCTF_12
BF1 VSS_NCTF_13 TP17 N30
BF53 VSS_NCTF_14
BH1 H12 GPIO57 stuff PD and not stuff PU for Intel suggestion at 6/1
VSS_NCTF_15 TP18
BH2 VSS_NCTF_16
BH52 AA23 GPIO57 R217 10K_4
VSS_NCTF_17 TP19
BH53 VSS_NCTF_18
BJ1 VSS_NCTF_19 NC_1 AB45
BJ2 VSS_NCTF_20
BJ4 VSS_NCTF_21 NC_2 AB38
BJ49 VSS_NCTF_22
BJ5 AB42 +3V R173 10K_4 BOARD_ID0 R181 *10K_4
VSS_NCTF_23 NC_3
BJ50 VSS_NCTF_24
BJ52 AB41 R250 IV@10K_4dGPU_PRSNT# R230 EV@10K_4
VSS_NCTF_25 NC_4
BJ53 VSS_NCTF_26
D1 T39 dGPU always exist
VSS_NCTF_27 NC_5
D2 VSS_NCTF_28
D53 VSS_NCTF_29
E1 VSS_NCTF_30 INIT3_3V# P6
E53 VSS_NCTF_31
High = 15"
TP24 C10 BOARD_ID0
Low = 14"
IbexPeak-M_R1P0
A A

PROJECT : ZRB
1A
IBEX PEAK-M 4/6
5 4 3 2 1
5 4 3 2 1

3.3 V. This rail should be powered up during S0 system state.
IBEX PEAK-M (POWER) POWER U26G
VCCADAC= 69mA(15mils)
Note that Thermal Sensor shares the same power supply rail with DAC.
The external filters on this pin are not needed in case internal graphic is
R144 *Short_8 +1.05V_VCCCORE_ICH AB24 AE50 +VCCA_DAC_1_2 L42 disabled so only 3.3-V connection is required.
+1.05V VCCCORE[1] VCCADAC[1] +3V
AB26 SP@PBY160808T/3A/60ohm_6
R155 *Short_8 VCCCORE[2]
AB28 VCCCORE[3] VCCADAC[2] AE52
C335 C330 AD26 C688 C655 C681 REV: B change P/N for EOD
VCCCORE[4]
CRT
AD28 AF53
REV : B Change to short pad 10u/6.3V_8 1u/6.3V_4 AF26
VCCCORE[5]
VCCCORE[6]
VSSA_DAC[1] IV@.01u/25V_4IV@22u/6.3V_8IV@0.1u/10V_4_X7R REV C:C655 change footprint from 0603 to 0805 U26J POWER VCCIO = 3.208A(150mils)
VCC CORE
AF28 VCCCORE[7] VSSA_DAC[2] AF51 VCCACLK= 52mA(15mils)
AF30 VCCALVDS= 1mA +1.05V L45 *10uh_8+V1.1LAN_VCCA_CLK AP51 V24 +1.05V
VCCCORE[8] C680 *10u/6.3V_6 VCCACLK[1] VCCIO[5]
AF31 VCCCORE[9] VCCIO[6] V26
AH26 VCCALVDS R142 IV@0_4 +3V C687 *1u/6.3V_4 AP53 Y24 C340 1U/6.3V_4
VCCCORE[10] VCCACLK[2] VCCIO[7]
VCCCORE(+1.05V) = 1.432A(80mils) AH28 VCCCORE[11] VCCIO[8] Y26
AH30 R148 VCCLAN = 320mA(30mils)
VCCCORE[12] R196 *0_6 +1.05V_VCCAUX +3V_S5_VCCPUSB R184 *Short_8
AH31 VCCCORE[13] VCCALVDS AH38 +1.05V AF23 VCCLAN[1] VCCSUS3_3[1] V28 +3V_S5
D AJ30 EV@0_4 U28 D
VCCCORE[14] VCCSUS3_3[2] C346 0.1u/10V_4_X7R
AJ31 VCCCORE[15] VSSA_LVDS AH39 AF24 VCCLAN[2] VCCSUS3_3[3] U26
U24 C334 0.1u/10V_4_X7R REV : B Change to short pad
SP@ C344 VCCSUS3_3[4] C345 0.022U/16V_4
VCCTX_LVDS= 59mA(15mils) VCCSUS3_3[5] P28
REV : B Change to short pad AP43 UMA=CH31004KB17<0.01u> 1U/6.3V_4 TP_PCH_VCCDSW Y20 P26
VCCTX_LVDS[1] MXM=CS00002JB38<0_ohm> VCCTX_LVDS L26 IV@0.1UH_8/250mA DCPSUSBYP VCCSUS3_3[6]
VCCTX_LVDS[2] AP45 +1.8V VCCSUS3_3[7] N28
AT46 N26
LVDS
R191 *Short_6 +1.05V_PCH_VCCDPLL_EXP VCCTX_LVDS[3] C314 C313 C311 C350 VCCSUS3_3[8]
+1.05V AK24 VCCIO[24] VCCTX_LVDS[4] AT45 AD38 VCCME[1] VCCSUS3_3[9] M28
C482 change to 0 ohm resistor. 1u/6.3V_4 M26
SP@.01u/25V_4 IV@.01u/25V_4 IV@22u/6.3V_8 VCCSUS3_3[10]
AD39 L28
VCCSUS3_3 = 0.163A(20mils)
USB
L46 *1uh_6 +V1.1LAN_VCCAPLL_EXP VCCME[2] VCCSUS3_3[11]
40mA(15mils) +1.05V BJ24 VCCAPLLEXP VCCSUS3_3[12] L26
VCC3_3[2] AB34 AD41 VCCME[3] VCCSUS3_3[13] J28
C705 *10u/6.3V_6 J26
VCCSUS3_3[14]
AN20 VCCIO[25] VCC3_3[3] AB35 VCC3_3 = 357mA(30mils) AF43 VCCME[4] VCCSUS3_3[15] H28
AN22 H26
HVCMOS
VCCIO[26] +3V_VCC_GIO R136 *Short_6 VCCSUS3_3[16]
AN23 AD35 VCCME(+1.05V) = 1.849A(100mils) AF41 G28
AN24
VCCIO[27]
VCCIO[28]
VCC3_3[4] +3V VCCME[5] VCCSUS3_3[17]
VCCSUS3_3[18] G26 V5REF_SUS< 1mA
AN26 C328 +1.05V R166 *Short_8 +1.05V_VCCEPW AF42 F28 R498 100/F_4 +5V_S5
VCCIO[29] VCCME[6] VCCSUS3_3[19]
VCCIO = 3.062A(150mils) AN28 VCCIO[30] VCCSUS3_3[20] F26
+1.05V BJ26 .1u/16V_4 R174 *Short_8 V39 E28 D17 RB500V-40 +3V_S5
Clock and Miscellaneous

BJ28 VCCIO[32] VCCSUS3_3[22] E26
AT26 V41 C28 C706 1U/6.3V_4
AT28 VCCIO[34]
REV : B Change to short pad VCCSUS3_3[24] C26
AU26 REV : B Change to short pad C315 22U/6.3V_8 V42 B27
AU28 VCCIO[36] VCCSUS3_3[26] A28
C333 10U/6.3V_8 AV26 C321 22U/6.3V_8 Y39 A26
C336 1U/6.3V_4 VCCIO[37] +VCCVRM R197 *Short_6 VCCME[10] VCCSUS3_3[27]
AV28 AT24 VCCVRM= 196mA(15mils) REV : B
C348 1U/6.3V_4 AW26
VCCIO[38]
VCCIO[39]
VCCVRM[2] +V1.5S_1.8S
C326 1U/6.3V_4 Y41 VCCME[11] VCCSUS3_3[28] U23 Short R190 V5REF< 1mA
C337 1U/6.3V_4 AW28 R145 100/F_4 +5V
VCCIO[40]
DMI
C329 1U/6.3V_4 BA26 AT16 +VCCDMI R206 *Short_4 +1.05V VCCDMI= 61mA(15mils) C327 1U/6.3V_4 Y42 V23 +1.05V
VCCIO[41] VCCDMI[1] VCCME[12] VCCIO[56] D8 RB500V-40
BA28 VCCIO[42] +3V
BB26 AU16 REV : B Change to short pad F24 V5REF_SUS
C VCCIO[43] VCCDMI[2] V5REF_SUS C310 1U/6.3V_4 C
BB28 VCCIO[44]
BC26 +VCCRTCEXT V9
VCCIO[45] DCPRTC
PCI E*
BC28 C359 C363 0.1u/10V_4_X7R
VCCIO[46] 1u/10V_4
BD26 VCCIO[47]
BD28 K49 V5REF
VCCIO[48] V5REF
BE26 AM16 +V1.5S_1.8S AU24 REV : B Change to short pad
PCI/GPIO/LPC
VCCIO[49] VCCPNAND[1] VCCVRM[3]
BE28 VCCIO[50] VCCPNAND[2] AK16 VCCPNAND= 156mA(15mils)
BG26 AK20 J38 +3V_VCCPPCI R168 *Short_6 +3V
VCCIO[51] VCCPNAND[3] VCCPNAND R219 *Short_8 +1.8V VCC3_3[8]
BG28 VCCIO[52] VCCPNAND[4] AK19 BB51 VCCADPLLA[1]
BH27 AK15 68mA(15mils) +V1.1LAN_VCCA_A_DPL BB53 L38 VCC3_3 = 0.357A(30mils)
VCCIO[53] VCCPNAND[5] C355 VCCADPLLA[2] VCC3_3[9] C318 0.1u/10V_4_X7R
VCCPNAND[6] AK13 REV : B Change to short pad
AN30 VCCIO[54] VCCPNAND[7] AM12 VCC3_3[10] M36
NAND / SPI
REV : B Short R140 & R201 AN31 AM13 .1u/16V_4 69mA(15mils) +V1.1LAN_VCCA_B_DPL BD51
VCCIO[55] VCCPNAND[8] VCCADPLLB[1]
VCCPNAND[9] AM15 BD53 VCCADPLLB[2] VCC3_3[11] N36
C317 0.1u/10V_4_X7R
+3V AN35 VCC3_3[1] +1.05V AH23 VCCIO[21] VCC3_3[12] P36
AJ35 VCCIO[22]
37mA(15mils) VCCIO = 3.062A(150mils) AH35 VCCIO[23] VCC3_3[13] U35
+V1.5S_1.8S AT22 VCCVRM[1]
C332 1U/6.3V_4 AF34
L47 *1uH_6 +V1.1LAN_VCCAPLL_FDI C331 1U/6.3V_4 VCCIO[2]
+1.05V BJ18 VCCFDIPLL VCCME3_3[1] AM8 VCC3_3[14] AD13
AM9 +3V_VCCME_SPI R212 *Short_6 +3V C322 1U/6.3V_4 AH34
VCCME3_3[2] VCCIO[3]
FDI
+1.05V AM23 VCCIO[1] VCCME3_3[3] AP11 31mA(15mils)

C707 AP9 C361 VCCME3_3= 85mA(15mils) AF32
*10u/6.3V_6 VCCME3_3[4] EC8 VCCIO[4] +V1.1LAN_VCCAPLL L28 *10uh_8
VCCSATAPLL[1] AK3 +1.05V
.1u/16V_4 *0.1u/10V_4 +VCCSST V12 AK1
C360 0.1u/10V_4_X7R DCPSST VCCSATAPLL[2] C714 C388
REV : B Short R189
IbexPeak-M_R1P0 *1u/6.3V_4 *10u/6.3V_6
+V1.1LAN_INT_VCCSUS Y22 VCCIO = 3.062A(150mils)

C349 0.1u/10V_4_X7R DCPSUS
VCCIO[9] AH22 +1.05V
B REV : B Short R534 B
P18 AT20 +V1.5S_1.8S C356
VCCSUS3_3[29] VCCVRM[4] 1u/10V_4
VCCVRM=196mA(15mils) VCCSUS3_3 = 163mA(20mils)
HDA_SYNC (PCH strap pin) +3V_S5 R188 *Short_6 +3V_S5_VCCPSUS U19
SATA
VCCSUS3_3[30]
PCI/GPIO/LPC
VCCIO[10] AH19
+1.8V R224 *Short_6 +V1.5S_1.8S Internal weak pull-down U20 VCCSUS3_3[31]
VCCVRM=>+1.8V (default) REV : B Change to short pad VCCIO[11] AD20
REV : B Change to short pad external pull-up C353 0.1u/10V_4_X7RU22
C376 C379 VCCSUS3_3[32]
VCCVRM=>+1.5V VCCIO[12] AF22
.1u/16V_4 .1u/16V_4
VRM enable by strap pin GPIO27 VCC3_3 = 0.357A(30mils) VCCIO[13] AD19
R202 *Short_6 +3V_VCCPCORE V15 AF20
which supply clean 1.05V for +3V VCC3_3[5] VCCIO[14]
AF19
[VCCACLK,VCCAPLLEXP,VCCFDIPLL,VCCSATAPLL] VCCIO[15]
V16 VCC3_3[6] VCCIO[16] AH20
REV : B Change to short pad C354 0.1u/10V_4_X7R Y16 AB19

VCC3_3[7] VCCIO[17]
VCCIO[18] AB20
+1.05V L44 *10uh_8 +V1.1LAN_VCCA_A_DPL AB22
VCCIO[19]
V_CPU_IO >1mA(15mils) VCCIO[20] AD22
+ C667 R209 *Short_6 +VTT_VCCPCPU AT18 VCCME = 1.849A(100mils)
+1.05V V_CPU_IO[1]
R461 REV : B Change to short pad AA34 +1.05V_VCCEPW
CPU
*220u_3528 C375 4.7U/6.3V_6 VCCME[13]
*Short_8 VCCME[14] Y34
C370 0.1u/10V_4_X7R AU18 Y35
C366 0.1u/10V_4_X7R V_CPU_IO[2] VCCME[15]
VCCME[16] AA35
L43 10uh_8 +V1.1LAN_VCCA_B_DPL
VCCRTC= 2mA(15mils)
RTC
+ C684 A12 L30 +V3.3A_1.5A_HDA_IO R185 *Short_4
+VCCRTC VCCRTC VCCSUSHDA +3V_S5
HDA
220u_3528 C711 0.1u/10V_4_X7R REV : B Change to short pad
C712 0.1u/10V_4_X7R IbexPeak-M_R1P0 C325 VCCSUSHDA= 6mA(15mils)
1u/10V_4
A A

PROJECT : ZRB
1A
IBEX PEAK-M 5/6
5 4 3 2 1
5 4 3 2 1
U26I
AY7 H49
IBEX PEAK-M (GND) B11
B15
VSS[159]
VSS[160]
VSS[259]
VSS[260] H5
J24
VSS[161] VSS[261]
D B19 VSS[162] VSS[262] K11 D
B23 VSS[163] VSS[263] K43
B31 VSS[164] VSS[264] K47
B35 VSS[165] VSS[265] K7
B39 VSS[166] VSS[266] L14
B43 VSS[167] VSS[267] L18
B47 VSS[168] VSS[268] L2
B7 VSS[169] VSS[269] L22
BG12 VSS[170] VSS[270] L32
BB12 VSS[171] VSS[271] L36
U26H BB16 L40
VSS[172] VSS[272]
AB16 VSS[0] BB20 VSS[173] VSS[273] L52
BB24 VSS[174] VSS[274] M12
AA19 VSS[1] VSS[80] AK30 BB30 VSS[175] VSS[275] M16
AA22 VSS[3] VSS[82] AK32 BB38 VSS[177] VSS[277] N38
AM19 VSS[4] VSS[83] AK34 BB42 VSS[178] VSS[278] M34
AA28 VSS[7] VSS[86] AK43 BC10 VSS[181] VSS[281] M46
AB11 VSS[11] VSS[90] AK8 BC22 VSS[185] VSS[285] N24
AB15 VSS[12] VSS[91] AL2 BC32 VSS[186] VSS[286] P11
AB23 VSS[13] VSS[92] AL52 BC36 VSS[187] VSS[287] AD15
AB30 VSS[14] VSS[93] AM11 BC40 VSS[188] VSS[288] P22
AB31 VSS[15] VSS[94] BB44 BC44 VSS[189] VSS[289] P30
AB32 VSS[16] VSS[95] AD24 BC52 VSS[190] VSS[290] P32
AB39 VSS[17] VSS[96] AM20 BH9 VSS[191] VSS[291] P34
AB43 VSS[18] VSS[97] AM22 BD48 VSS[192] VSS[292] P42
C C
AB8 VSS[21] VSS[100] AM28 BE12 VSS[195] VSS[295] R2
AC2 VSS[22] VSS[101] BA42 BE16 VSS[196] VSS[296] R52
AC52 VSS[23] VSS[102] AM30 BE20 VSS[197] VSS[297] T12
AD11 VSS[24] VSS[103] AM31 BE24 VSS[198] VSS[298] T41
AD31 VSS[29] VSS[108] AM39 BE46 VSS[203] VSS[303] U30
AD32 VSS[30] VSS[109] AM42 BE48 VSS[204] VSS[304] U31
AD34 VSS[31] VSS[110] AU20 BE50 VSS[205] VSS[305] U32
AU22 VSS[32] VSS[111] AM46 BE6 VSS[206] VSS[306] U34
AD42 VSS[33] VSS[112] AV22 BE8 VSS[207] VSS[307] P38
AD46 VSS[34] VSS[113] AM49 BF3 VSS[208] VSS[308] V11
AD49 VSS[35] VSS[114] AM7 BF49 VSS[209] VSS[309] P16
AD7 VSS[36] VSS[115] AA50 BF51 VSS[210] VSS[310] V19
AE2 VSS[37] VSS[116] BB10 BG18 VSS[211] VSS[311] V20
AE4 VSS[38] VSS[117] AN32 BG24 VSS[212] VSS[312] V22
AF12 VSS[39] VSS[118] AN50 BG4 VSS[213] VSS[313] V30
Y13 VSS[40] VSS[119] AN52 BG50 VSS[214] VSS[314] V31
AH49 VSS[41] VSS[120] AP12 BH11 VSS[215] VSS[315] V32
AU4 VSS[42] VSS[121] AP42 BH15 VSS[216] VSS[316] V34
AF35 VSS[43] VSS[122] AP46 BH19 VSS[217] VSS[317] V35
AP13 VSS[44] VSS[123] AP49 BH23 VSS[218] VSS[318] V38
AN34 VSS[45] VSS[124] AP5 BH31 VSS[219] VSS[319] V43
AF45 VSS[46] VSS[125] AP8 BH35 VSS[220] VSS[320] V45
AF46 VSS[47] VSS[126] AR2 BH39 VSS[221] VSS[321] V46
AF49 VSS[48] VSS[127] AR52 BH43 VSS[222] VSS[322] V47
AF5 VSS[49] VSS[128] AT11 BH47 VSS[223] VSS[323] V49
AF8 VSS[50] VSS[129] BA12 BH7 VSS[224] VSS[324] V5
B AG2 AH48 C12 V7 B
VSS[51] VSS[130] VSS[225] VSS[325]
AG52 VSS[52] VSS[131] AT32 C50 VSS[226] VSS[326] V8
AH11 VSS[53] VSS[132] AT36 D51 VSS[227] VSS[327] W2
AH15 VSS[54] VSS[133] AT41 E12 VSS[228] VSS[328] W52
AH16 VSS[55] VSS[134] AT47 E16 VSS[229] VSS[329] Y11
AH24 VSS[56] VSS[135] AT7 E20 VSS[230] VSS[330] Y12
AH32 VSS[57] VSS[136] AV12 E24 VSS[231] VSS[331] Y15
AV18 VSS[58] VSS[137] AV16 E30 VSS[232] VSS[332] Y19
AJ19 VSS[62] VSS[141] AV34 E46 VSS[236] VSS[336] Y31
AJ23 VSS[66] VSS[145] AV49 F49 VSS[240] VSS[340] Y46
AJ26 VSS[67] VSS[146] AV5 F5 VSS[241] VSS[341] P49
AJ28 VSS[68] VSS[147] AV8 G10 VSS[242] VSS[342] Y5
AJ32 VSS[69] VSS[148] AW14 G14 VSS[243] VSS[343] Y6
AJ34 VSS[70] VSS[149] AW18 G18 VSS[244] VSS[344] Y8
AT5 VSS[71] VSS[150] AW2 G2 VSS[245] VSS[345] P24
AJ4 VSS[72] VSS[151] BF9 G22 VSS[246] VSS[346] T43
AK12 VSS[73] VSS[152] AW32 G32 VSS[247] VSS[347] AD51
AM41 VSS[74] VSS[153] AW36 G36 VSS[248] VSS[348] AT8
AN19 VSS[75] VSS[154] AW40 G40 VSS[249] VSS[349] AD47
AK26 VSS[76] VSS[155] AW52 G44 VSS[250] VSS[350] Y47
AK22 VSS[77] VSS[156] AY11 G52 VSS[251] VSS[351] AT12
AK23 VSS[78] VSS[157] AY43 AF39 VSS[252] VSS[352] AM6
AK28 VSS[79] VSS[158] AY47 H16 VSS[253] VSS[353] AT13
H20 VSS[254] VSS[354] AM5
IbexPeak-M_R1P0 H30 AK45
VSS[255] VSS[355]
A H34 VSS[256] VSS[356] AK39 A
H38 VSS[257] VSS[366] AV14
H42 VSS[258]
IbexPeak-M_R1P0
PROJECT : ZRB
1A
IBEX PEAK-M 6/6
5 4 3 2 1
5 4 3 2 1

+1.5VSUS
JDIM1B
JDIM1A M_A_DQ[63:0] [5]
[5] M_A_A[15:0] 75 VDD1 VSS16 44
M_A_A0 98 5 M_A_DQ4 76 48
M_A_A1 A0 DQ0 M_A_DQ0 VDD2 VSS17
97 A1 DQ1 7 81 VDD3 VSS18 49
M_A_A2 96 15 M_A_DQ2 82 54
95 A3 DQ3 17 87 VDD5 VSS20 55
M_A_A4 92 4 M_A_DQ1 88 60
LTK DGMK4000087 91 A5 DQ5 6 93 VDD7 VSS22 61
M_A_A6 M_A_DQ6
M_A_A7
90
86
A6 DQ6 16
18 M_A_DQ7
2.48A 94
99
VDD8 VSS23 65
66
D SUY DGMK4000073 89 A8 DQ8 21 100 VDD10 VSS25 71 D
M_A_A9 85 23 M_A_DQ13 105 72
PC2100 DDR3 SDRAM SO-DIMM

107 A10/AP DQ10 33 106 VDD12 VSS27 127
M_A_A11 84 35 M_A_DQ10 111 128
83 A12/BC# DQ12 22 112 VDD14 VSS29 133
M_A_A13 119 24 M_A_DQ9 117 134
80 A14 DQ14 34 118 VDD16 VSS31 138
M_A_A15 78 36 M_A_DQ15 123 139
A15 DQ15 VDD17 VSS32

39 M_A_DQ17 124 144
DQ16 M_A_DQ20 VDD18 VSS33
[5] M_A_BS#0 109 BA0 DQ17 41 VSS34 145
108 51 M_A_DQ18 199 150
[5] M_A_BS#1 BA1 DQ18 +3V VDDSPD VSS35
79 53 M_A_DQ19 151
[5] M_A_BS#2 BA2 DQ19 VSS36
114 40 M_A_DQ16 77 155
[5] M_A_CS#0 S0# DQ20 NC1 VSS37
121 42 M_A_DQ21 122 156
[5] M_A_CS#1 S1# DQ21 NC2 VSS38
101 50 M_A_DQ22 125 161
[5] M_A_CLK0 CK0 DQ22 NCTEST VSS39
103 52 M_A_DQ23 162
[5] M_A_CLK0# CK0# DQ23 VSS40
102 57 M_A_DQ24 198 167
[5] M_A_CLK1 CK1 DQ24 [4] PM_EXTTS#0 EVENT# VSS41
104 59 M_A_DQ28 30 168
[5] M_A_CLK1# CK1# DQ25 [4,15] DDR3_DRAMRST# RESET# VSS42
73 67 M_A_DQ25 172
[5] M_A_CKE0 CKE0 DQ26 VSS43
74 69 M_A_DQ26 173
[5] M_A_CKE1 CKE1 DQ27 VSS44
115 56 M_A_DQ27 +SMDDR_VREF_DQ 1 178
[5] M_A_CAS# CAS# DQ28 +SMDDR_VREF_DQ VREF_DQ VSS45
110 58 M_A_DQ29 +SMDDR_VREF_DIMM 126 179
[5] M_A_RAS# RAS# DQ29 +SMDDR_VREF_DIMM VREF_CA VSS46
113 68 M_A_DQ31 184
[5] M_A_WE# WE# DQ30 VSS47
R249 10K_4 DIMM0_SA0 197 70 M_A_DQ30 185
R248 10K_4 DIMM0_SA1 SA0 DQ31 M_A_DQ36 VSS48
201 SA1 DQ32 129 2 VSS1 VSS49 189
CLK_SCLK 202 131 M_A_DQ33 3 190
[3,15,28] CLK_SCLK CLK_SDATA SCL DQ33 M_A_DQ35 VSS2 VSS50
200 141 8 195
(204P)
[3,15,28] CLK_SDATA SDA DQ34 M_A_DQ34 VSS3 VSS51
C DQ35 143 9 VSS4 VSS52 196 C
116 130 M_A_DQ32 13
[5] M_A_ODT0 ODT0 DQ36 VSS5
120 132 M_A_DQ37 14
[5] M_A_ODT1 ODT1 DQ37 VSS6
140 M_A_DQ38 19
[5] M_A_DM[7:0] DQ38 VSS7
M_A_DM0 11 142 M_A_DQ39 20
M_A_DM1 DM0 DQ39 M_A_DQ45 VSS8
28 DM1 DQ40 147 25 VSS9
M_A_DM2 46 149 M_A_DQ44 26 203 +0.75V_DDR_VTT
M_A_DM3 63
DM2
DM3
(204P) DQ41
DQ42 157 M_A_DQ47
+1.5VSUS
31
VSS10
VSS11
VTT1
VTT2 204
M_A_DM4 136 159 M_A_DQ42 32
M_A_DM5 DM4 DQ43 M_A_DQ41 VSS12
153 DM5 DQ44 146 37 VSS13 GND 205
M_A_DM6 170 148 M_A_DQ40 38 206
M_A_DM7 DM6 DQ45 M_A_DQ46 VSS14 GND
187 DM7 DQ46 158 43 VSS15
160 M_A_DQ43 R269
[5] M_A_DQS[7:0] DQ47
M_A_DQS0 12 163 M_A_DQ48 10K/F_4
M_A_DQS1 DQS0 DQ48 M_A_DQ49
29 DQS1 DQ49 165 DDR3-DIMM1_H=8.0_Reverse
M_A_DQS2 47 175 M_A_DQ50
M_A_DQS3 DQS2 DQ50 M_A_DQ51 +SMDDR_VREF_DIMM
64 DQS3 DQ51 177
M_A_DQS4 137 164 M_A_DQ52
154 DQS5 DQ53 166
M_A_DQS6 171 174 M_A_DQ54 R229 C412
[5] M_A_DQS#[7:0] 188 DQS7 DQ55 176 10K/F_4 470p/X7R_4
M_A_DQS#0 10 181 M_A_DQ56
M_A_DQS#1 DQS#0 DQ56 M_A_DQ57
27 DQS#1 DQ57 183
M_A_DQS#2 45 191 M_A_DQ62
62 DQS#3 DQ59 193
M_A_DQS#4 135 180 M_A_DQ60
152 DQS#5 DQ61 182
M_A_DQS#6 169 192 M_A_DQ63 +1.5VSUS
B DQS#6 DQ62 B
M_A_DQS#7 186 194 M_A_DQ58
DQS#7 DQ63
R223
DDR3-DIMM1_H=8.0_Reverse 10K/F_4
+SMDDR_VREF_DQ
Place these Caps near So-Dimm0.
R226 C387
10K/F_4 470p/X7R_4
+1.5VSUS
+SMDDR_VREF_DIMM +SMDDR_VREF_DQ0
C369 C382 C377 C385 C394
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4
C367 + C372 C386 C384 C392 C390

330u/2V_7343
10u/6.3V_6 .1u/16V_4 .1u/16V_4
C398 C371 C378 C373 C368 2.2u/6.3V_6 2.2u/6.3V_6

10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4 .1u/16V_4
A A
+3V +0.75V_DDR_VTT
C401 C383 C381 C397 C380 C404 C421

C405
2.2u/6.3V_6
C402
.1u/16V_4
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
4.7U/6.3V_64.7U/6.3V_64.7U/6.3V_6
PROJECT : ZRB
1A
DDRIII SO-DIMM-0
5 4 3 2 1
5 4 3 2 1

+1.5VSUS
JDIM2A M_B_DQ[63:0] [5] JDIM2B
[5] M_B_A[15:0]
M_B_A0 98 5 M_B_DQ5 75 44
M_B_A1 A0 DQ0 M_B_DQ1 VDD1 VSS16
97 A1 DQ1 7 76 VDD2 VSS17 48
M_B_A2 96 15 M_B_DQ2 81 49
95 A3 DQ3 17 82 VDD4 VSS19 54
LTK DGMK4000005 M_B_A4 92 4 M_B_DQ0 87 55
91 A5 DQ5 6 88 VDD6 VSS21 60
M_B_A6 90 16 M_B_DQ6 93 61
MOLEX DGMK4000010 86 A7 DQ7 18 94 VDD8 VSS23 65
M_B_A8 M_B_DQ8
D
M_B_A9
89
85
A8 DQ8 21
23 M_B_DQ9
2.48A 99
100
VDD9 VSS24 66
71
D

107 33 105 72

M_B_A11 A10/AP DQ10 M_B_DQ11 VDD11 VSS26
84 A11 DQ11 35 106 VDD12 VSS27 127
M_B_A12 83 22 M_B_DQ12 111 128
M_B_A13 A12/BC# DQ12 M_B_DQ13 VDD13 VSS28
119 A13 DQ13 24 112 VDD14 VSS29 133
M_B_A14 80 34 M_B_DQ14 117 134
78 A15 DQ15 36 118 VDD16 VSS31 138

39 M_B_DQ18 123 139
DQ16 M_B_DQ17 VDD17 VSS32
[5] M_B_BS#0 109 BA0 DQ17 41 124 VDD18 VSS33 144
108 51 M_B_DQ16 145
[5] M_B_BS#1 BA1 DQ18 VSS34
79 53 M_B_DQ19 199 150
[5] M_B_BS#2 BA2 DQ19 +3V VDDSPD VSS35
114 40 M_B_DQ20 151
[5] M_B_CS#0 S0# DQ20 VSS36
121 42 M_B_DQ21 77 155
[5] M_B_CS#1 S1# DQ21 NC1 VSS37
101 50 M_B_DQ22 122 156
[5] M_B_CLK0 CK0 DQ22 NC2 VSS38
103 52 M_B_DQ23 125 161
[5] M_B_CLK0# CK0# DQ23 NCTEST VSS39
102 57 M_B_DQ26 162
[5] M_B_CLK1 CK1 DQ24 VSS40
104 59 M_B_DQ25 198 167
[5] M_B_CLK1# CK1# DQ25 [4] PM_EXTTS#1 EVENT# VSS41
73 67 M_B_DQ30 30 168
[5] M_B_CKE0 CKE0 DQ26 [4,14] DDR3_DRAMRST# RESET# VSS42
74 69 M_B_DQ27 172
[5] M_B_CKE1 CKE1 DQ27 VSS43
115 56 M_B_DQ29 173
[5] M_B_CAS# CAS# DQ28 VSS44
110 58 M_B_DQ24 +SMDDR_VREF_DQ 1 178
[5] M_B_RAS# RAS# DQ29 +SMDDR_VREF_DQ VREF_DQ VSS45
113 68 M_B_DQ28 126 179
[5] M_B_WE# WE# DQ30 +SMDDR_VREF_DIMM VREF_CA VSS46
R286 10K_4 DIMM1_SA0 197 70 M_B_DQ31 184
R290 10K_4 DIMM1_SA1 SA0 DQ31 M_B_DQ32 VSS47
+3V 201 SA1 DQ32 129 VSS48 185
202 131 M_B_DQ33 2 189
[3,14,28] CLK_SCLK SCL DQ33 M_B_DQ34 VSS1 VSS49
200 SDA DQ34 141 3 VSS2 VSS50 190
[3,14,28] CLK_SDATA 143 M_B_DQ35 8 195
(204P)
C DQ35 VSS3 VSS51 C
116 130 M_B_DQ36 9 196
[5] M_B_ODT0 ODT0 DQ36 VSS4 VSS52
120 132 M_B_DQ37 13
[5] M_B_ODT1 ODT1 DQ37 VSS5
140 M_B_DQ38 14
[5] M_B_DM[7:0] DQ38 VSS6
M_B_DM0 11 142 M_B_DQ39 19
M_B_DM1 DM0 DQ39 M_B_DQ40 VSS7
28 DM1 DQ40 147 20 VSS8
M_B_DM2 46 149 M_B_DQ45 25
M_B_DM3 63
DM2
DM3
(204P) DQ41
DQ42 157 M_B_DQ47 26
VSS9
VSS10 VTT1 203 +0.75V_DDR_VTT
M_B_DM4 136 159 M_B_DQ43 31 204
M_B_DM5 DM4 DQ43 M_B_DQ44 VSS11 VTT2
153 DM5 DQ44 146 32 VSS12
M_B_DM6 170 148 M_B_DQ41 37 205
M_B_DM7 DM6 DQ45 M_B_DQ46 VSS13 GND
187 DM7 DQ46 158 38 VSS14 GND 206
160 M_B_DQ42 43
[5] M_B_DQS[7:0] DQ47 VSS15
M_B_DQS0 12 163 M_B_DQ48
M_B_DQS1 DQS0 DQ48 M_B_DQ53
29 DQS1 DQ49 165
M_B_DQS2 47 175 M_B_DQ50 DDR3-DIMM1_H=4.0_Reverse
64 DQS3 DQ51 177
M_B_DQS4 137 164 M_B_DQ52
154 DQS5 DQ53 166
M_B_DQS6 171 174 M_B_DQ51
[5] M_B_DQS#[7:0] 188 DQS7 DQ55 176
M_B_DQS#0 10 181 M_B_DQ60
M_B_DQS#1 DQS#0 DQ56 M_B_DQ57
27 DQS#1 DQ57 183
M_B_DQS#2 45 191 M_B_DQ63
62 DQS#3 DQ59 193
M_B_DQS#4 135 180 M_B_DQ59
152 DQS#5 DQ61 182
B M_B_DQS#6 169 192 M_B_DQ62 B
186 DQS#7 DQ63 194
DDR3-DIMM1_H=4.0_Reverse
+1.5VSUS Place these Caps near So-Dimm1.

+SMDDR_VREF_DIMM +SMDDR_VREF_DQ1
C450 C447 C449 C446 C416
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4
C451 + C459 C422 C425 C452 C455

330u/2V_7343
10u/6.3V_6 .1u/16V_4 .1u/16V_4
C448 C418 C417 C414 C445 2.2u/6.3V_6 2.2u/6.3V_6

10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4 .1u/16V_4
+3V +0.75V_DDR_VTT
A C436 C423 C433 C424 C420 C429 C411 A

C454 C438 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
2.2u/6.3V_6 .1u/16V_4 4.7U/6.3V_64.7U/6.3V_6 4.7U/6.3V_6

PROJECT : ZRB
1A
DDRIII SO-DIMM-1
5 4 3 2 1
5 4 3 2 1

GPU_1(VGA) U21A
PEG_TXP[0..15] 0518 SWAP PCIE for VGA side

[4] PEG_TXP[0..15]
PEG_TXN[0..15] 0518 SWAP PCIE for VGA side
[4] PEG_TXN[0..15]
PEG_RXP[0..15] PEG_TXP15 AA38 Y33 CPEG_RXP15 C155 EV@0.1u/10V_4

[4] PEG_RXP[0..15] [4] PEG_TXP15 PCIE_RX0P PCIE_TX0P PEG_RXP15 [4]
PEG_TXN15 Y37 Y32 CPEG_RXN15 C164 EV@0.1u/10V_4
D PEG_RXN[0..15] [4] PEG_TXN15 PCIE_RX0N PCIE_TX0N PEG_RXN15 [4] D
[4] PEG_RXN[0..15]
PEG_TXP14 Y35 W33 CPEG_RXP14 C147 EV@0.1u/10V_4
[4] PEG_TXP14 PCIE_RX1P PCIE_TX1P PEG_RXP14 [4]
PEG_TXN14 W36 W32 CPEG_RXN14 C154 EV@0.1u/10V_4
[4] PEG_TXN14 PCIE_RX1N PCIE_TX1N PEG_RXN14 [4]
PEG_TXP13 W38 U33 CPEG_RXP13 C141 EV@0.1u/10V_4

PEG_TXN13 V37 U32 CPEG_RXN13 C146 EV@0.1u/10V_4
PEG_TXP12 V35 U30 CPEG_RXP12 C136 EV@0.1u/10V_4

PEG_TXN12 U36 U29 CPEG_RXN12 C131 EV@0.1u/10V_4
PEG_TXP11 U38 T33 CPEG_RXP11 C130 EV@0.1u/10V_4

PEG_TXN11 T37 T32 CPEG_RXN11 C116 EV@0.1u/10V_4
PCI EXPRESS INTERFACE

PEG_TXP10 T35 T30 CPEG_RXP10 C109 EV@0.1u/10V_4
PEG_TXN10 R36 T29 CPEG_RXN10 C106 EV@0.1u/10V_4
PEG_TXP9 R38 P33 CPEG_RXP9 C105 EV@0.1u/10V_4

PEG_TXN9 P37 P32 CPEG_RXN9 C92 EV@0.1u/10V_4
C [4] PEG_TXN9 PCIE_RX6N PCIE_TX6N PEG_RXN9 [4] C
PEG_TXP8 P35 P30 CPEG_RXP8 C91 EV@0.1u/10V_4

PEG_TXN8 N36 P29 CPEG_RXN8 C87 EV@0.1u/10V_4
PEG_TXP7 N38 N33 CPEG_RXP7 C86 EV@0.1u/10V_4

PEG_TXN7 M37 N32 CPEG_RXN7 C80 EV@0.1u/10V_4
PEG_TXP6 M35 N30 CPEG_RXP6 C79 EV@0.1u/10V_4

PEG_TXN6 L36 N29 CPEG_RXN6 C75 EV@0.1u/10V_4
PEG_TXP5 L38 L33 CPEG_RXP5 C72 EV@0.1u/10V_4

PEG_TXN5 K37 L32 CPEG_RXN5 C69 EV@0.1u/10V_4
PEG_TXP4 K35 L30 CPEG_RXP4 C67 EV@0.1u/10V_4

PEG_TXN4 J36 L29 CPEG_RXN4 C63 EV@0.1u/10V_4
PEG_TXP3 J38 K33 CPEG_RXP3 C59 EV@0.1u/10V_4

B PEG_TXN3 H37 K32 CPEG_RXN3 C61 EV@0.1u/10V_4 B
PEG_TXP2 H35 J33 CPEG_RXP2 C56 EV@0.1u/10V_4

PEG_TXN2 G36 J32 CPEG_RXN2 C58 EV@0.1u/10V_4
PEG_TXP1 G38 K30 CPEG_RXP1 C50 EV@0.1u/10V_4

PEG_TXN1 F37 K29 CPEG_RXN1 C48 EV@0.1u/10V_4
PEG_TXP0 F35 H33 CPEG_RXP0 C55 EV@0.1u/10V_4

PEG_TXN0 E37 H32 CPEG_RXN0 C52 EV@0.1u/10V_4
CLOCK
[10] CLK_PCIE_VGA AB35 PCIE_REFCLKP
[10] CLK_PCIE_VGA# AA36 PCIE_REFCLKN Madison AJ007720T02
For Broadway, Madison and Park CALIBRATION Park AJ077400T08

the PWRGOOD ball must be conneccted to ground AJ21 Y30 R47 EV@1.27K/F_4
NC#1 PCIE_CALRP
AK21 NC#2
A R67 EV@10K_4 R46 EV@2K/F_4 A
AH16 PWRGOOD PCIE_CALRN Y29 +1V +1.0V
[11] GPU_RST# AA30 PERSTB For M97, Broadway, Madison and Park PCIE_VDDC is 1.0V Quanta Computer Inc.
SP@Capilano/Robson
PROJECT :ZRB
1A
Capilano/Robson -PCIE I/F
5 4 3 2 1
5 4 3 2 1

U21B U21G
GPU_2(VGA)
AU24 LVDS CONTROL AK27
TXCAP_DPA3P HDMICLK+ [25] VARY_BL EV_LVDS_BRIGHT [24]
TXCAM_DPA3N AV23 HDMICLK- [25] DIGON AJ27 EV_LVDS_VDDEN [24]
TX0P_DPA2P AT25 HDMITX0P [25]

MUTI GFX AR24
TX0M_DPA2N HDMITX0N [25]
DPA
TX1P_DPA1P AU26 HDMITX1P [25] TXCLK_UP_DPF3P AK35
TX1M_DPA1N AV25 HDMITX1N [25] TXCLK_UN_DPF3N AL36
AR8 DVPCNTL_MVP_0 TX2P_DPA0P AT27 HDMITX2P [25] TXOUT_U0P_DPF2P AJ38

D
AU8 DVPCNTL_MVP_1 TX2M_DPA0N AR26 HDMITX2N [25] TXOUT_U0N_DPF2N AK37 D
AP8
NC on Park AW8
DVPCNTL_0
DVPCNTL_1 TXCBP_DPB3P AR30 TXOUT_U1P_DPF1P AH35
AR3 DVPCNTL_2 TXCBM_DPB3N AT29 TXOUT_U1N_DPF1N AJ36
AR1
GPU Power-on sequence [21] RAM_STRAP0 AU1
AU3
DVPCLK
DVPDATA_0 TX3P_DPB2P AV31
AU30
TXOUT_U2P_DPF0P AG38
AH37
[21] RAM_STRAP1 DVPDATA_1 DPB TX3M_DPB2N TXOUT_U2N_DPF0N
AW3
1 => +VGPU_CORE [21] RAM_STRAP2
AP6
DVPDATA_2
DVPDATA_3 TX4P_DPB1P AR32 TXOUT_U3P AF35
T59 AW5 AT31 AG36
2 => +VGPU_IO AU5
DVPDATA_4
DVPDATA_5
TX4M_DPB1N TXOUT_U3N
AR6 DVPDATA_6 TX5P_DPB0P AT33
3 => +1V 1.8V GPIO AW6
AU6
DVPDATA_7 TX5M_DPB0N AU32 LVTMDP
DVPDATA_8
4 => +1.5V_GPU AT7
AV7
DVPDATA_9
DVPDATA_10
TXCCP_DPC3P
TXCCM_DPC3N
AU14
AV13
TXCLK_LP_DPE3P
TXCLK_LN_DPE3N
AP34
AR34
EV_TXLCLKOUT+ [24]
EV_TXLCLKOUT- [24]
AN7
5 => +3V_D AV9
DVPDATA_11
DVPDATA_12 TX0P_DPC2P AT15 TXOUT_L0P_DPE2P AW37 EV_TXLOUT0+ [24]
AT9 AR14 AU35
6 => +1.8V_GPU AR10
DVPDATA_13
DVPDATA_14 DPC
TX0M_DPC2N TXOUT_L0N_DPE2N EV_TXLOUT0- [24]
AW10 DVPDATA_15 TX1P_DPC1P AU16 TXOUT_L1P_DPE1P AR37 EV_TXLOUT1+ [24]
7 => dGPU_PWROK AU10
AP10
DVPDATA_16 TX1M_DPC1N AV15 TXOUT_L1N_DPE1N AU39 EV_TXLOUT1- [24]
DVPDATA_17
AV11 DVPDATA_18 TX2P_DPC0P AT17 TXOUT_L2P_DPE0P AP35 EV_TXLOUT2+ [24]
AT11 DVPDATA_19 TX2M_DPC0N AR16 TXOUT_L2N_DPE0N AR35 EV_TXLOUT2- [24]
AR12
NC on Park AW12
DVPDATA_20
DVPDATA_21 TXCDP_DPD3P AU20 TXOUT_L3P AN36
AU12 DVPDATA_22 TXCDM_DPD3N AT19 TXOUT_L3N AP37
AP12 DVPDATA_23
+3V_D AT21
TX3P_DPD2P
TX3M_DPD2N AR20
Channel D N.C for Park-M2
DPD AU22
TX4P_DPD1P SP@Capilano/Robson
TX4M_DPD1N AV21
R78 R75
EV@10K_4 EV@10K_4 I2C AT23
TX5P_DPD0P
TX5M_DPD0N AR22
AK26 SCL
C AJ26 SDA
C
R AD39 EV_CRT_RED [24]

GENERAL PURPOSE I/O AD37
RB
[21] GPU_GPIO0 AH20 GPIO_0
[21] GPU_GPIO1 AH18 GPIO_1 G AE36 EV_CRT_GRN [24]
[21] GPU_GPIO2 AN16 GPIO_2 GB AD35
[21] GPIO3_SMBDAT AH23 GPIO_3_SMBDATA
[21] GPIO4_SMBCLK AJ23 GPIO_4_SMBCLK B AF37 EV_CRT_BLU [24]
AH17 GPIO_5_AC_BATT BB AE38
1/21 ramp remove IO_VID0 AJ17 DAC1
GPIO_6 R60 R57 R55
[24] EV_LVDS_BLON AK17 GPIO_7_BLON HSYNC AC36 EV_HSYNC [21,24]
AJ13 AC38 EV@150/F_4 EV@150/F_4 EV@150/F_4
T56 GPIO_8_ROMSO VSYNC EV_VSYNC [21,24]
T9 AH15 GPIO_9_ROMSI
AJ16 GPIO_10_ROMSCK
+3V_D AK16 AB34 R50 EV@499/F_4
[21] GPU_GPIO11 GPIO_11 RSET
[21] GPU_GPIO12 AL16 GPIO_12
REV C: C188 change footprint from 0603 to 0805
AM16 AD34 AVDD
[21] GPU_GPIO13 GPIO_13 AVDD
AM14 AE34 +1.8V_GPU
R419 GPIO_14_HPD2 AVSSQ
3.3V GPIO [43] VID1 AM13 GPIO_15_PWRCNTL_0 (1.8V@70mA AVDD)
AK14 AC33 VDD1DI
*10K_4 GPIO_16_SSIN VDD1DI AVDD L8 EV@SBY100505T-800Y-N/500mA/80ohm_4
[21] ALT#_GPIO17 AG30 GPIO_17_THERMAL_INT VSS1DI AC34
AN14 GPIO_18_HPD3
AM17 GPIO_19_CTF
AL13 AC30 C172 C182 C188
+3V_D [43] VID2 GPIO_20_PWRCNTL_1 R2
AJ14 AC31 R54 EV@0_4 EV@0.1u/10V_4 EV@1u/6.3V_4 EV@22u/6.3V_8
R412 GPIO_21_BB_EN R2B
T12 AK13 GPIO_22_ROMCSB
AN13 GPIO_23_CLKREQB G2 AD30
EV@10K_4 AM23 AD31 R62 EV@0_4 (1.8V@100mA VDD1DI)
R405 JTAG_TRSTB G2B
AN23 JTAG_TDI
27M_CLK AK23 AF30 VDD1DI L9 EV@SBY100505T-121Y-N/300mA/120ohm_4
[3] 27M_CLK JTAG_TCK B2
*10K/F_4 +3V_D R83 *10K_4 AL24 AF31 R61 EV@0_4
JTAG_TMS B2B
AM24 JTAG_TDO
AJ19 DAC2 will be NC on future ASIC C200 C199 C205
GENERICA EV@0.1u/10V_4 EV@1u/6.3V_4 EV@10u/6.3V_6
AK19 GENERICB C AC32
AJ20 GENERICC Y AD32
R404 AK20 AF32
GENERICD COMP
B
AJ24 GENERICE_HPD4 B
*10K/F_4 AH26 DAC2
GENERICF
AH24 GENERICG H2SYNC AD29 T8
V2SYNC AC29 V2SYNC [21]
R84 EV@0_4
[8,25] HDMI_HP
HDMI_HP_EV AK24
+1.8V_GPU HPD1 VDD1DI
VDD2DI AG31
AG32 R63 EV@0_4
VSS2DI
R95 AG33 R65 EV@0_4 +3V_D (3.3V@130mA A2VDD)

A2VDD
EV@499/F_4
AD33 A2VDDQ
VREFG AH13 A2VDDQ C202
VREFG EV@0.1u/10V_4
A2VSSQ AF33
C209
R90
EV@249/F_4 EV@0.1u/10V_4 AA29 R51 EV@715/F_4
R2SET
+1.8V(75mA)
L11 EV@SBY100505T-121Y-N/300mA/120ohm_4 DPLL_PVDD DDC/AUX AM26 MXM_DDCCK R373 EV@0_4
+1.8V_GPU DDC1CLK HDMI_DDCCLK_SW [8,25]
PLL/CLOCK AN26 MXM_DDCDAT R374 EV@0_4
C214 C211 C213 DPLL_PVDD AM32 DPLL_PVDD
DDC1DATA HDMI_DDCDATA_SW [8,25]
HDMI
AN32 AM27 +1.8V_GPU
EV@10u/6.3V_6 EV@1u/6.3V_4 EV@0.1u/10V_4 R406 *0_4 DPLL_PVSS AUX1P
[3] 27M_CLK_SS AUX1N AL27 (1.8V@2mA A2VDDQ)
DPLL_VDDC AN31 AM19 A2VDDQ L38 EV@SBY100505T-121Y-N/300mA/120ohm_4
C624 EV@27p/50V_4 DPLL_VDDC DDC2CLK
DDC2DATA AL19
+1.0V(125mA)
2
XTALI_27M AV33 AN20 C171 C168

L14 EV@SBY100505T-121Y-N/300mA/120ohm_4 DPLL_VDDC Y4 R403 XTALO_27M XTALIN AUX2P EV@0.1u/10V_4 EV@1u/6.3V_4
+1V AU34 XTALOUT AUX2N AM20
EV@27MHZ EV@1M/F_4
C234 C221 C208 AL30 T11
1
DDCCLK_AUX3P
DDCDATA_AUX3N AM30
EV@10u/6.3V_6 EV@1u/6.3V_4 EV@0.1u/10V_4 C625 EV@27p/50V_4
DDCCLK_AUX4P AL29
AF29 AM29
A
[21] GPU_D+
[21] GPU_D- AG29
DPLUS
DMINUS
THERMAL DDCDATA_AUX4N DDC AUX4 NC for Park_M2 A
+1.8V(5mA) DDCCLK_AUX5P AN21 EV_LVDS_DDCCLK [24]
AM21
+1.8V_GPU L10 EV@SBY100505T-121Y-N/300mA/120ohm_4 TS_VDD
T55 AK32 TS_FDO
DDCDATA_AUX5N EV_LVDS_DDCDAT [24] LVDS
TS_VDD AJ32 AJ30
TSVDD DDC6CLK EV_CRTDCLK [24]
C212 C201 AJ33 AJ31
TSVSS DDC6DATA EV_CRTDDAT [24] CRT
EV@10u/6.3V_6 EV@0.1u/10V_4 AK30
NC_DDCCLK_AUX7P
AK29
NC_DDCDATA_AUX7N DDC AUX7 NC for Park_M2
SP@Capilano/Robson
PROJECT : ZRB
1A
5 4 3 2 1
5 4 3 2 1
GPU_3(VGA) Maintenance and Service Guide,Service Manual,Motherboard Schematics for Laptop/notebook http://mycomp.su/x/
Park M2-channel B used(S3 package use Channel A)
VMA_DQ[63..0] VMB_DQ[63..0]
[22] VMA_DQ[63..0] [23] VMB_DQ[63..0]
VMA_DM[7..0] VMB_DM[7..0]
[22] VMA_DM[7..0] [23] VMB_DM[7..0]
U21C U21D
VMA_RDQS[7..0] DDR2 DDR2 VMB_RDQS[7..0] DDR2 DDR2
[22] VMA_RDQS[7..0] GDDR3/GDDR5 GDDR5/GDDR3 [23] VMB_RDQS[7..0] GDDR3/GDDR5 GDDR5/GDDR3
VMA_WDQS[7..0] DDR3 DDR3 VMB_WDQS[7..0] DDR3 DDR3
[22] VMA_WDQS[7..0] [23] VMB_WDQS[7..0]
VMA_DQ0 C37 G24 VMA_MA0 VMB_DQ0 C5 P8 VMB_MA0
VMA_DQ1 DQA0_0/DQA_0 MAA0_0/MAA_0 VMA_MA1 VMB_DQ1 DQB0_0/DQB_0 MAB0_0/MAB_0 VMB_MA1
C35 J23 C3 T9
MEMORY INTERFACE A
D
VMA_DQ2 DQA0_1/DQA_1 MAA0_1/MAA_1 VMA_MA2 VMB_MA[13..0] VMB_DQ2 DQB0_1/DQB_1 MAB0_1/MAB_1 VMB_MA2 D
A35 H24 E3 P9
MEMORY INTERFACE B
VMA_MA[13..0] DQA0_2/DQA_2 MAA0_2/MAA_2 [23] VMB_MA[13..0] DQB0_2/DQB_2 MAB0_2/MAB_2
VMA_DQ3 E34 J24 VMA_MA3 VMB_DQ3 E1 N7 VMB_MA3
[22] VMA_MA[13..0] DQA0_3/DQA_3 MAA0_3/MAA_3 DQB0_3/DQB_3 MAB0_3/MAB_3
VMA_DQ4 G32 H26 VMA_MA4 VMB_DQ4 F1 N8 VMB_MA4
VMA_DQ5 DQA0_4/DQA_4 MAA0_4/MAA_4 VMA_MA5 VMB_BA0 VMB_DQ5 DQB0_4/DQB_4 MAB0_4/MAB_4 VMB_MA5
D33 DQA0_5/DQA_5 MAA0_5/MAA_5 J26 [23] VMB_BA0 F3 DQB0_5/DQB_5 MAB0_5/MAB_5 N9
VMA_BA0 VMA_DQ6 F32 H21 VMA_MA6 VMB_BA1 VMB_DQ6 F5 U9 VMB_MA6
[22] VMA_BA0 DQA0_6/DQA_6 MAA0_6/MAA_6 [23] VMB_BA1 DQB0_6/DQB_6 MAB0_6/MAB_6
VMA_BA1 VMA_DQ7 E32 G21 VMA_MA7 VMB_BA2 VMB_DQ7 G4 U8 VMB_MA7
[22] VMA_BA1 DQA0_7/DQA_7 MAA0_7/MAA_7 [23] VMB_BA2 DQB0_7/DQB_7 MAB0_7/MAB_7
VMA_BA2 VMA_DQ8 D31 H19 VMA_MA8 VMB_DQ8 H5 Y9 VMB_MA8
[22] VMA_BA2 DQA0_8/DQA_8 MAA1_0/MAA_8 DQB0_8/DQB_8 MAB1_0/MAB_8
VMA_DQ9 F30 H20 VMA_MA9 VMB_DQ9 H6 W9 VMB_MA9
C30 DQA0_10/DQA_10 MAA1_2/MAA_10 L13 J4 DQB0_10/DQB_10 MAB1_2/MAB_10 AC8
VMA_DQ11 A30 G16 VMA_MA11 VMB_DQ11 K6 AC9 VMB_MA11
F28 DQA0_12/DQA_12 MAA1_4/MAA_12 J16 K5 DQB0_12/DQB_12 MAB1_4/MAB_12 AA7
VMA_DQ13 C28 H16 VMA_BA2 VMB_DQ13 L4 AA8 VMB_BA2
VMA_DQ14 DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 VMA_BA0 VMB_DQ14 DQB0_13/DQB_13 MAB1_5/BA2 VMB_BA0
A28 DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 J17 M6 DQB0_14/DQB_14 MAB1_6/BA0 Y8
VMA_DQ15 E28 H17 VMA_BA1 VMB_DQ15 M1 AA9 VMB_BA1
VMA_DQ16 DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 VMB_DQ16 DQB0_15/DQB_15 MAB1_7/BA1
D27 DQA0_16/DQA_16 M3 DQB0_16/DQB_16
VMA_DQ17 F26 A32 VMA_DM0 VMB_DQ17 M5 H3 VMB_DM0
VMA_DQ18 DQA0_17/DQA_17 WCKA0_0/DQMA_0 VMA_DM1 VMB_DQ18 DQB0_17/DQB_17 WCKB0_0/DQMB_0 VMB_DM1
C26 DQA0_18/DQA_18 WCKA0B_0/DQMA_1 C32 N4 DQB0_18/DQB_18 WCKB0B_0/DQMB_1 H1
VMA_DQ19 A26 D23 VMA_DM2 VMB_DQ19 P6 T3 VMB_DM2
F24 DQA0_20/DQA_20 WCKA0B_1/DQMA_3 E22 P5 DQB0_20/DQB_20 WCKB0B_1/DQMB_3 T5
VMA_DQ21 C24 C14 VMA_DM4 VMB_DQ21 R4 AE4 VMB_DM4
A24 DQA0_22/DQA_22 WCKA1B_0/DQMA_5 A14 T6 DQB0_22/DQB_22 WCKB1B_0/DQMB_5 AF5
VMA_DQ23 E24 E10 VMA_DM6 VMB_DQ23 T1 AK6 VMB_DM6
C22 DQA0_24/DQA_24 WCKA1B_1/DQMA_7 D9 U4 DQB0_24/DQB_24 WCKB1B_1/DQMB_7 AK5
VMA_DQ25 A22 VMB_DQ25 V6
VMA_DQ26 DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 VMA_RDQS0 VMB_DQ26 DQB0_25/DQB_25 GDDR5/DDR2/GDDR3 VMB_RDQS0
F22 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 C34 V1 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 F6
VMA_DQ27 D21 D29 VMA_RDQS1 VMB_DQ27 V3 K3 VMB_RDQS1
VMA_DQ28 DQA0_27/DQA_27 EDCA0_1/QSA_1/RDQSA_1 VMA_RDQS2 VMB_DQ28 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1 VMB_RDQS2
A20 DQA0_28/DQA_28 EDCA0_2/QSA_2/RDQSA_2 D25 Y6 DQB0_28/DQB_28 EDCB0_2/QSB_2/RDQSB_2 P3
VMA_DQ29 F20 E20 VMA_RDQS3 QSA[7..0] VMB_DQ29 Y1 V5 VMB_RDQS3 QSB[7..0]
D19 DQA0_30/DQA_30 EDCA1_0/QSA_4/RDQSA_4 E16 Y3 DQB0_30/DQB_30 EDCB1_0/QSB_4/RDQSB_4 AB5
VMA_DQ31 E18 E12 VMA_RDQS5 VMB_DQ31 Y5 AH1 VMB_RDQS5
C18 DQA1_0/DQA_32 EDCA1_2/QSA_6/RDQSA_6 J10 AA4 DQB1_0/DQB_32 EDCB1_2/QSB_6/RDQSB_6 AJ9
VMA_DQ33 A18 D7 VMA_RDQS7 VMB_DQ33 AB6 AM5 VMB_RDQS7
VMA_DQ34 DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 VMB_DQ34 DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7
F18 DQA1_2/DQA_34 AB1 DQB1_2/DQB_34
VMA_DQ35 D17 A34 VMA_WDQS0 VMB_DQ35 AB3 G7 VMB_WDQS0
VMA_DQ36 DQA1_3/DQA_35 DDBIA0_0/QSA_0B/WDQSA_0 VMA_WDQS1 VMB_DQ36 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 VMB_WDQS1
A16 DQA1_4/DQA_36 DDBIA0_1/QSA_1B/WDQSA_1 E30 AD6 DQB1_4/DQB_36 DDBIB0_1/QSB_1B/WDQSB_1 K1
VMA_DQ37 F16 E26 VMA_WDQS2 VMB_DQ37 AD1 P1 VMB_WDQS2
D15 DQA1_6/DQA_38 DDBIA0_3/QSA_3B/WDQSA_3 C20 QSA#[7..0] AD3 DQB1_6/DQB_38 DDBIB0_3/QSB_3B/WDQSB_3 W4 QSB#[7..0]
C VMA_DQ39 E14 C16 VMA_WDQS4 VMB_DQ39 AD5 AC4 VMB_WDQS4 C
F14 DQA1_8/DQA_40 DDBIA1_1/QSA_5B/WDQSA_5 C12 AF1 DQB1_8/DQB_40 DDBIB1_1/QSB_5B/WDQSB_5 AH3
VMA_DQ41 D13 J11 VMA_WDQS6 VMB_DQ41 AF3 AJ8 VMB_WDQS6
F12 DQA1_10/DQA_42 DDBIA1_3/QSA_7B/WDQSA_7 F8 AF6 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7 AM3
VMA_DQ43 A12 VMB_DQ43 AG4
VMA_DQ44 DQA1_11/DQA_43 VMB_DQ44 DQB1_11/DQB_43
D11 DQA1_12/DQA_44 ADBIA0/ODTA0 J21 VMA_ODT0 [22] AH5 DQB1_12/DQB_44 ADBIB0/ODTB0 T7 VMB_ODT0 [23]
VMA_DQ45 F10 G19 VMB_DQ45 AH6 W7
DQA1_13/DQA_45 ADBIA1/ODTA1 VMA_ODT1 [22] DQB1_13/DQB_45 ADBIB1/ODTB1 VMB_ODT1 [23]
VMA_DQ46 A10 VMB_DQ46 AJ4
VMA_DQ47 DQA1_14/DQA_46 VMA_CLK0 VMB_DQ47 DQB1_14/DQB_46 VMB_CLKP0
C10 DQA1_15/DQA_47 CLKA0 H27 VMA_CLK0 [22] AK3 DQB1_15/DQB_47 CLKB0 L9 VMB_CLKP0 [23]
VMA_DQ48 G13 G27 VMA_CLK0# VMB_DQ48 AF8 L8 VMB_CLKN0
DQA1_16/DQA_48 CLKA0B VMA_CLK0# [22] DQB1_16/DQB_48 CLKB0B VMB_CLKN0 [23]
VMA_DQ49 H13 VMB_DQ49 AF9
VMA_DQ50 DQA1_17/DQA_49 VMA_CLK1 VMB_DQ50 DQB1_17/DQB_49 VMB_CLKP1
J13 DQA1_18/DQA_50 CLKA1 J14 VMA_CLK1 [22] AG8 DQB1_18/DQB_50 CLKB1 AD8 VMB_CLKP1 [23]
VMA_DQ51 H11 H14 VMA_CLK1# VMB_DQ51 AG7 AD7 VMB_CLKN1
DQA1_19/DQA_51 CLKA1B VMA_CLK1# [22] DQB1_19/DQB_51 CLKB1B VMB_CLKN1 [23]
VMA_DQ52 G10 VMB_DQ52 AK9
VMA_DQ53 DQA1_20/DQA_52 VMA_RAS0# VMB_DQ53 DQB1_20/DQB_52 VMB_RAS0#
G8 DQA1_21/DQA_53 RASA0B K23 VMA_RAS0# [22] AL7 DQB1_21/DQB_53 RASB0B T10 VMB_RAS0# [23]
VMA_DQ54 K9 K19 VMA_RAS1# VMB_DQ54 AM8 Y10 VMB_RAS1#
DQA1_22/DQA_54 RASA1B VMA_RAS1# [22] DQB1_22/DQB_54 RASB1B VMB_RAS1# [23]
VMA_DQ55 K10 VMB_DQ55 AM7
VMA_DQ56 DQA1_23/DQA_55 VMA_CAS0# VMB_DQ56 DQB1_23/DQB_55 VMB_CAS0#
G9 DQA1_24/DQA_56 CASA0B K20 VMA_CAS0# [22] AK1 DQB1_24/DQB_56 CASB0B W10 VMB_CAS0# [23]
+1.5V_GPU VMA_DQ57 A8 K17 VMA_CAS1# VMB_DQ57 AL4 AA10 VMB_CAS1#
DQA1_25/DQA_57 CASA1B VMA_CAS1# [22] DQB1_25/DQB_57 CASB1B VMB_CAS1# [23]
VMA_DQ58 C8 +1.5V_GPU VMB_DQ58 AM6
VMA_DQ59 DQA1_26/DQA_58 VMA_CS0# VMB_DQ59 DQB1_26/DQB_58 VMB_CS0#
E8 DQA1_27/DQA_59 CSA0B_0 K24 VMA_CS0# [22] AM1 DQB1_27/DQB_59 CSB0B_0 P10 VMB_CS0# [23]
VMA_DQ60 A6 K27 VMB_DQ60 AN4 L10
VMA_DQ61 DQA1_28/DQA_60 CSA0B_1 VMB_DQ61 DQB1_28/DQB_60 CSB0B_1
C6 DQA1_29/DQA_61 AP3 DQB1_29/DQB_61
R34 VMA_DQ62 E6 M13 VMA_CS1# VMB_DQ62 AP1 AD10 VMB_CS1#
DQA1_30/DQA_62 CSA1B_0 VMA_CS1# [22] DQB1_30/DQB_62 CSB1B_0 VMB_CS1# [23]
EV@40.2/F_4 VMA_DQ63 A5 K16 R59 VMB_DQ63 AP5 AC10
DQA1_31/DQA_63 CSA1B_1 EV@40.2/F_4 DQB1_31/DQB_63 CSB1B_1
MVREFDA L18 K21 VMA_CKE0 U10 VMB_CKE0
MVREFDA CKEA0 VMA_CKE0 [22] CKEB0 VMB_CKE0 [23]
MVREFSA L20 J20 VMA_CKE1 MVREFDB Y12 AA11 VMB_CKE1
MVREFSA CKEA1 VMA_CKE1 [22] MVREFDB CKEB1 VMB_CKE1 [23]
MVREFSB AA12
C65 R36 EV@243/F_4 VMA_WE0# MVREFSB VMB_WE0#
L27 MEM_CALRN0 WEA0B K26 VMA_WE0# [22] WEB0B N10 VMB_WE0# [23]
R38 EV@0.1u/10V_4 R39 EV@243/F_4 N12 L15 VMA_WE1# C169 AB11 VMB_WE1#
MEM_CALRN1 WEA1B VMA_WE1# [22] WEB1B VMB_WE1# [23]
EV@100/F_4 +1.5V_GPU R66 EV@243/F_4 AG12 R53 EV@0.1u/10V_4
MEM_CALRN2 EV@100/F_4 R74 *10K_4
+3V_D
R41 EV@243/F_4 VMA_MA13 R58 EV@10K_4 AD28 VMB_MA13
GDDR5
M12 H23 T8
GDDR5
R40 EV@243/F_4 MEM_CALRP1 MAA0_8 TESTEN MAB0_8
M27 MEM_CALRP0 MAA1_8 J19 MAB1_8 W8
R68 EV@243/F_4 AH12 AK10
MEM_CALRP2 CLKTESTA R87 EV@10/F_4 R89 EV@51_4
AL10 CLKTESTB DRAM_RST AH11 MEM_RST# [22,23]
+1.5V_GPU Note by AN_M96_C1
B B
+1.5V_GPU
AL31 R93 R91 R72
RSVD *0_4 *0_4 EV@5.1K_4 C230
EV@120P/50V_4
R33
EV@40.2/F_4 SP@Capilano/Robson R52 SP@Capilano/Robson
EV@40.2/F_4
C64 Place all these components very close to GPU

R37 EV@0.1u/10V_4 C190
EV@100/F_4 R64 EV@0.1u/10V_4
EV@100/F_4
Used for Park-M2
A A

PROJECT : ZRB
1A
5 4 3 2 1
5 4 3 2 1

GPU_4(VGA)
U21F
U21E
For DDR3, MVDDQ = 1.5V (7.5A)
+1.5V_GPU close GPU MEM I/O +1.8V_GPU
PCIE (1.8V@400mA PCIE_VDDR) AB39 A3
PCIE_VDDR L36 EV@HCB1608KF-181T15/1.5A/180ohm_6 PCIE_VSS#1 GND#1
AC7 VDDR1#1 PCIE_VDDR#1 AA31 E39 PCIE_VSS#2 GND#2 A37
Near CN11, rev B add AD11 VDDR1#2 PCIE_VDDR#2 AA32 F34 PCIE_VSS#3 GND#3 AA16
C608
+
AF7 VDDR1#3 PCIE_VDDR#3 AA33 F39 PCIE_VSS#4 GND#4 AA18
C62 C83 C51 C210 C119 AG10 AA34 C156 C569 C149 C142 C170 C570 C568 C571 G33 AA2
EV@100u/6.3V_3528
EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 VDDR1#4 PCIE_VDDR#4 EV@0.1u/10V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 PCIE_VSS#5 GND#5
AJ7 VDDR1#5 PCIE_VDDR#5 V28 G34 PCIE_VSS#6 GND#6 AA21
+1.5VSUS EV@10u/6.3V_6 EV@10u/6.3V_6 AK8 W29 EV@0.1u/10V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@10u/6.3V_6 H31 AA23
D VDDR1#6 PCIE_VDDR#6 PCIE_VSS#7 GND#7 D
AL9 VDDR1#7 PCIE_VDDR#7 W30 H34 PCIE_VSS#8 GND#8 AA26
G11 VDDR1#8 PCIE_VDDR#8 Y31 H39 PCIE_VSS#9 GND#9 AA28
G14 VDDR1#9 J31 PCIE_VSS#10 GND#10 AA6
G17 VDDR1#10 J34 PCIE_VSS#11 GND#11 AB12
C767 +1V
+
G20 VDDR1#11 PCIE_VDDC#1 G30 K31 PCIE_VSS#12 GND#12 AB15

C81 C126 C263 C206 C185 C148 G23 G31 (1.0V@1.1A PCIE_VDDC) K34 AB17
*100u/6.3V_3528 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 VDDR1#12 PCIE_VDDC#2 PCIE_VSS#13 GND#13
G26 VDDR1#13 PCIE_VDDC#3 H29 K39 PCIE_VSS#14 GND#14 AB20
EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 G29 H30 L31 AB22
VDDR1#14 PCIE_VDDC#4 PCIE_VSS#15 GND#15
H10 VDDR1#15 PCIE_VDDC#5 J29 L34 PCIE_VSS#16 GND#16 AB24
J7 J30 C108 C94 C78 C70 C129 C84 C104 C73 M34 AB27
VDDR1#16 PCIE_VDDC#6 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 PCIE_VSS#17 GND#17
J9 VDDR1#17 PCIE_VDDC#7 L28 M39 PCIE_VSS#18 GND#18 AC11
K11 M28 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@10u/6.3V_6 N31 AC13
VDDR1#18 PCIE_VDDC#8 PCIE_VSS#19 GND#19
K13 VDDR1#19 PCIE_VDDC#9 N28 N34 PCIE_VSS#20 GND#20 AC16
K8 VDDR1#20 PCIE_VDDC#10 R28 P31 PCIE_VSS#21 GND#21 AC18
C71 C77 C123 C95 C66 C85 L12 T28 P34 AC2
EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 VDDR1#21 PCIE_VDDC#11 PCIE_VSS#22 GND#22
L16 VDDR1#22 PCIE_VDDC#12 U28 P39 PCIE_VSS#23 GND#23 AC21
EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 L21 +VGPU_CORE R34 AC23
VDDR1#23 PCIE_VSS#24 GND#24
L23 VDDR1#24 (30A or more) T31 PCIE_VSS#25 GND#25 AC26
L26 VDDR1#25 VDDC#1 AA15 T34 PCIE_VSS#26 GND#26 AC28
L7 CORE AA17 T39 AC6
VDDR1#26 VDDC#2 PCIE_VSS#27 GND#27
M11 VDDR1#27 VDDC#3 AA20 U31 PCIE_VSS#28 GND#28 AD15
N11 AA22 C113 C120 C151 C153 C114 C179 C173 C110 C111 C163 U34 AD17
C122 C82 C89 C96 C76 VDDR1#28 VDDC#4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 PCIE_VSS#29 GND#29
P7 VDDR1#29 VDDC#5 AA24 V34 PCIE_VSS#30 GND#30 AD20
EV@1u/6.3V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 R11 AA27 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 V39 AD22
EV@0.1u/10V_4 EV@0.1u/10V_4 VDDR1#30 VDDC#6 PCIE_VSS#31 GND#31
U11 VDDR1#31 VDDC#7 AB16 W31 PCIE_VSS#32 GND#32 AD24
U7 VDDR1#32 VDDC#8 AB18 W34 PCIE_VSS#33 GND#33 AD27
Y11 VDDR1#33 VDDC#9 AB21 Y34 PCIE_VSS#34 GND#34 AD9
Y7 VDDR1#34 VDDC#10 AB23 Y39 PCIE_VSS#35 GND#35 AE2
VDDC#11 AB26 GND#36 AE6
VDDC#12 AB28 GND#37 AF10
AC17 C193 C197 C175 C157 C192 C186 C177 C133 C166 C187 AF16
VDDC#13 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@10u/6.3V_6 EV@1u/6.3V_4 EV@1u/6.3V_4 GND#38
VDDC#14 AC20 GND#39 AF18
LEVEL AC22 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 AF21
(1.8V@110mA VDD_CT) TRANSLATION VDDC#15
VDDC#16 AC24 GND GND#40
GND#41 AG17
POWER
+1.8V_GPU L19 EV@SBY100505T-121Y-N/300mA/120ohm_4 VDDC_CT AF26 AC27 F15 AG2
VDD_CT#1 VDDC#17 GND#100 GND#42
AF27 VDD_CT#2 VDDC#18 AD18 F17 GND#101 GND#43 AG20
AG26 VDD_CT#3 VDDC#19 AD21 F19 GND#102 GND#44 AG22
C C244 C191 C180 AG27 AD23 F21 AG6 C
EV@10u/6.3V_6 EV@0.1u/10V_4 VDD_CT#4 VDDC#20 GND#103 GND#45
VDDC#21 AD26 F23 GND#104 GND#46 AG9 PowerXpress control signal for Madsion and Park only
EV@1u/6.3V_4 AF17 C165 C161 C159 C183 C176 C137 C132 C162 C145 C128 F25 AH21 If not used, can be disconnected.
I/O VDDC#22 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 GND#105 GND#47
(3.3V@60mA)) VDDC#23 AF20 F27 GND#106 GND#48 AJ10 PX_EN = LOW, turn on
+3V_D AF23 AF22 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 F29 AJ11
VDDR3#1 VDDC#24 GND#107 GND#49 PX_EN = HIGH, turn off
AF24 VDDR3#2 VDDC#25 AG16 F31 GND#108 GND#50 AJ2
PX_EN is used to turn ON/OFF some
AG23 VDDR3#3 VDDC#26 AG18 F33 GND#109 GND#51 AJ28
C203 C194 C189 C198 AG24 AG21 F7 AJ6 regulators for PowerXpress mode. An
EV@10u/6.3V_6 EV@1u/6.3V_4 VDDR3#4 VDDC#27 GND#110 GND#52 output high ‘3.3V’ will turn the regulators
VDDC#28 AH22 F9 GND#111 GND#53 AK11
EV@1u/6.3V_4 EV@1u/6.3V_4 AH27 G2 AK31 OFF. An output low ‘0V’ will turn the
VDDC#29 C160 C138 C158 C139 C101 C140 GND#112 GND#54 regulators ON. PX_EN outputs low (0V)
AF13 VDDR4#4 VDDC#30 AH28 G6 GND#113 GND#55 AK7
AF15 M26 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 H9 AL11 by default.
VDDR4#5 VDDC#31 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 GND#114 GND#56
AG13 VDDR4#7 VDDC#32 N24 J2 GND#115 GND#57 AL14 If this signal is unused, it can be NC (not
+1.8V_GPU L18 EV@SBY100505T-121Y-N/300mA/120ohm_4 VDDR4 AG15 N27 J27 AL17 connected) or connected to ground.
VDDR4#8 VDDC#33 GND#116 GND#58
VDDC#34 R18 J6 GND#117 GND#59 AL2
VDDC#35 R21 BIF_VDDC should be connected to VDDC if BACO feature not used. J8 GND#118 GND#60 AL20
C184 C174 AD12 R23 K14 AL21 R99 *0_4 +3V_D
EV@1u/6.3V_4 VDDR4#1 VDDC#36 For BACO, refer to the databook GND#119 GND#61
AF11 VDDR4#2 VDDC#37 R26 K7 GND#120 GND#62 AL23
EV@0.1u/10V_4 AF12 T17 L11 AL26
VDDR4#3 VDDC#38 GND#121 GND#63 R98
AG11 VDDR4#6 VDDC#39 T20 L17 GND#122 GND#64 AL32
T22 L2 AL6 *0_4
VDDC#40 GND#123 GND#65
VDDC#41 T24 L22 GND#124 GND#66 AL8
T27 PIN different between Broadway and Madison L24 AM11
VDDC#43 U16 L6 GND#126 GND#68 AM31
PCIE_PVDD M20 U18 Pin Broadway Madison M17 AM9
NC_VDDRHA VDDC#44 GND#127 GND#69 Pin AL21 to Ground for Broadway
M21 NC_VSSRHA VDDC#45 U21 M22 GND#128 GND#70 AN11
R375 U23 N27 VDDC BIF_VDDC M24 AN2
VDDC#47 U26 N16 GND#130 GND#72 AN30
*0_4 V12 V17 N18 AN6
PCIE_VDDR NC_VDDRHB VDDC#48 AL31 TS_A NC_TS_A GND#131 GND#73
U12 NC_VSSRHB VDDC#49 V20 N2 GND#132 GND#74 AN8
VDDC#50 V22 N21 GND#133 GND#75 AP11
VDDC#51 V24 N23 GND#134 GND#76 AP7
V27 AL21 GND PX_EN N26 AP9
VDDC#53 Y16 N6 GND#136 GND#78 AR5
(1.8V@40mA PCIE_PVDD) PLL Y18 R15 AW34
L37 EV@SBY100505T-121Y-N/300mA/120ohm_4 PCIE_PVDD VDDC#54 GND#137 GND#79
+1.8V_GPU AB37 PCIE_PVDD VDDC#55 Y21 R17 GND#138 GND#80 B11
VDDC#56 Y23 R2 GND#139 GND#81 B13
MPV18 H7 Y26 R20 B15
B
C588 C589 C587 MPV18#1 VDDC#57 GND#140 GND#82 B
H8 MPV18#2 VDDC#58 Y28 R22 GND#141 GND#83 B17
EV@10u/6.3V_6 EV@0.1u/10V_4 R24 B19
EV@1u/6.3V_4 +VGPU_CORE GND#142 GND#84
R27 GND#143 GND#85 B21
SPV18 AM10 (DDR3 1.12V@4A VDDCI) or more R6 B23
SPV18 GND#144 GND#86
(1.8V@150mA MPV18) VDDCI#1 AA13 T11 GND#145 GND#87 B25
+1.8V_GPU L4 EV@SBY100505T-121Y-N/300mA/120ohm_4 SPV10 AN9 AB13 T13 B27
SPV10 VDDCI#2 GND#146 GND#88
VDDCI#3 AC12 T16 GND#147 GND#89 B29
AN10 AC15 C103 C152 C115 C97 C167 C102 C100 C112 C99 C98 T18 B31
C54 C57 C60 SPVSS VDDCI#4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 GND#148 GND#90
VDDCI#5 AD13 T21 GND#149 GND#91 B33
EV@10u/6.3V_6 EV@0.1u/10V_4 AD16 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 T23 B7
EV@1u/6.3V_4 VDDCI#6 GND#150 GND#92
VDDCI#7 M15 T26 GND#151 GND#93 B9
VDDCI#8 M16 U15 GND#153 GND#94 C1
VOLTAGE M18 U17 C39
SENESE VDDCI#9 GND#154 GND#95
(1.8V@75mA SPV18) VDDCI#10 M23 U2 GND#155 GND#96 E35
L17 EV@SBY100505T-121Y-N/300mA/120ohm_4 N13 +3V U20 E5
+1.8V_GPU VDDCI#11 GND#156 GND#97
T13 AF28 FB_VDDC VDDCI#12 N15 U22 GND#157 GND#98 F11
N17 C178 C88 C134 U24 F13
C231 C215 VDDCI#13 EV@10u/6.3V_6 EV@10u/6.3V_6 GND#158 GND#99
VDDCI#14 N20 U27 GND#159
1
EV@10u/6.3V_6 AG28 N22 EV@10u/6.3V_6 U6
EV@0.1u/10V_4 FB_VDDCI ISOLATED VDDCI#15 GND#160
R12 V11
CORE I/O VDDCI#16 R13 R456 V16
GND#161
VDDCI#17 EV@0_6 GND#163
T10 AH29 FB_GND VDDCI#18 R16 2 V18 GND#164
120 ohm/300mA
(1.0V@120mA SPV10) T12 V21
L15 EV@SBY100505T-121Y-N/300mA/120ohm_4 VDDCI#19 GND#165
+1V VDDCI#20 T15 V23 GND#166
V15 *AO3413 0.5A V26
VDDCI#21 Q9 GND#167
Y13 W2
3
C229 C218 VDDCI#22 GND#168
+3V_D_S W6 GND#169
EV@10u/6.3V_6 Y15
EV@0.1u/10V_4 VDDC_SENSE/VSS_SENSE and SP@Capilano/Robson C679 C674 C668 GND#170
Y17 GND#171
VDDCI_SENSE/VSS_SENSE route as differetial pair Spec: 0.15A Y20
*10u/6.3V_6 *0.1u/10V_4 Rating: 3A GND#172
Y22 GND#173 VSS_MECH#1 A39
*1u/6.3V_4 Y24 AW1
+3V GND#174 VSS_MECH#2
GPU all PWROK R590
Y27
*0_4 U13 GND#175 VSS_MECH#3 AW39
R591 *0_4 V13 GND#152

+3V +3V GND#162
R459 GPU +3V power SP@Capilano/Robson
A EV@10K_4 R427 A
*0_6
1
R431
dGPU_PWROK [11] *4.7K_4
R449 R434 REV C: Add R590/591 footprint for AMD sch
3
EV@10K_4 Fine-tune Power-on sequence 2 EV@0_6

3
2 Q11 *AO3413 0.5A

EV@2N7002K Q7
3
3
R446 *0_4 2 Q6
Q10
[36,40,41,44] MAINON
R450 *0_4
*DTC144EUA
C663 C659 C645
+3V_D
Spec: 0.15A
+1.8V_GPU 2 [11,43] dGPU_VRON
1
EV@DTC144EUA C656 Rating: 3A

PROJECT :ZRB
1
*1u/6.3V_4 *10u/6.3V_6 *0.1u/10V_4

*1u/6.3V_4 Size Document Number Rev
1
1A
5 4 3 2 1
5 4 3 2 1

GPU_5(VGA) +1V
U21H (1.0V@110mA DPA_VDD10)
DPA_VDD10 L13 EV@SBY100505T-121Y-N/300mA/120ohm_4
DP C/D POWER DP A/B POWER
DPA_VDD18 AP20 AN24 DPA_VDD18 C224 C216 C222

DPC_VDD18#1 DPA_VDD18#1 EV@10u/6.3V_6 EV@0.1u/10V_4
AP21 DPC_VDD18#2 DPA_VDD18#2 AP24
EV@1u/6.3V_4
D D
DPA_VDD10 AP13 AP31 DPA_VDD10
DPC_VDD10#1 DPA_VDD10#1
AT13 DPC_VDD10#2 DPA_VDD10#2 AP32
AN17 AN27 DPA_VDD18 DPE_VDD18

+1.8V_GPU DPC_VSSR#1 DPA_VSSR#1
AP16 DPC_VSSR#2 DPA_VSSR#2 AP27
(1.8V@130mA DPA_VDD18) AP17 AP28 R96 R92 R394
DPC_VSSR#3 DPA_VSSR#3
AW14 DPC_VSSR#4 DPA_VSSR#4 AW24
L22 EV@SBY100505T-121Y-N/300mA/120ohm_4 DPA_VDD18 AW16 AW26 *0_4 *0_4 *0_4
DPC_VSSR#5 DPA_VSSR#5 DPA_PVDD DPC_PVDD DPE_PVDD
C241 C232 C220 R100 R88

EV@10u/6.3V_6 EV@0.1u/10V_4 DPA_VDD18 AP22 AP25 DPA_VDD18
EV@1u/10V_6 DPD_VDD18#1 DPB_VDD18#1 *0_4 *0_4
AP23 DPD_VDD18#2 DPB_VDD18#2 AP26
DPB_PVDD DPD_PVDD
DPA_VDD10 AP14 AN33 DPA_VDD10

DPD_VDD10#1 DPB_VDD10#1
AP15 DPD_VDD10#2 DPB_VDD10#2 AP33
C AN19 DPD_VSSR#1 DPB_VSSR#1 AN29 C

AP18 DPD_VSSR#2 DPB_VSSR#2 AP29
AP19 DPD_VSSR#3 DPB_VSSR#3 AP30
AW20 DPD_VSSR#4 DPB_VSSR#4 AW30
AW22 DPD_VSSR#5 DPB_VSSR#5 AW32
R97 EV@150/F_4 DPCD_CALR AW18 AW28 DPAB_CALR R413 EV@150/F_4 +1.8V_GPU

DPCD_CALR DPAB_CALR
(1.8V@20mA DPA_PVDD)
DPA_PVDD L21 EV@SBY100505T-121Y-N/300mA/120ohm_4
DP E/F POWER DP PLL POWER
AH34 DPE_VDD18#1 DPA_PVDD AU28
DPE_VDD18 AJ34 AV27 C247 C238 C235
DPE_VDD18#2 DPA_PVSS EV@10u/6.3V_6 EV@0.1u/10V_4
EV@1u/6.3V_4
+1.8V_GPU
AL33 AV29 DPB_PVDD (1.8V@20mA DPB_PVDD)
DPE_VDD10 DPE_VDD10#1 DPB_PVDD L20 EV@SBY100505T-121Y-N/300mA/120ohm_4
AM33 DPE_VDD10#2 DPB_PVSS AR28
+1.8V_GPU (1.8V@400mA DPE/F_VDD18)
L39 EV@HCB1608KF-181T15/1.5A/180ohm_6 DPE_VDD18 C253 C246 C242
AN34 AU18 EV@10u/6.3V_6 EV@0.1u/10V_4
DPE_VSSR#1 DPC_PVDD EV@1u/6.3V_4
AP39 DPE_VSSR#2 DPC_PVSS AV17
B C610 C614 C609 AR39 +1.8V_GPU B
EV@0.1u/10V_4 EV@10u/6.3V_6 DPE_VSSR#3 DPC_PVDD
AU37 DPE_VSSR#4 (1.8V@20mA DPC_PVDD)
EV@1u/6.3V_4 AW35 L16 EV@0_4
DPE_VSSR#5
DPD_PVDD AV19
DPD_PVSS AR18
C240 C239 C621
AF34 *10u/6.3V_6 *1u/6.3V_4 *0.1u/10V_4
DPE_VDD18 DPF_VDD18#1
AG34 DPF_VDD18#2
+1V (1.0V@400mA DPE/F_VDD10) AM37 +1.8V_GPU
180 ohm/1.5A DPE_PVDD DPD_PVDD
DPE_PVSS AN38 (1.8V@20mA DPD_PVDD)
L12 EV@HCB1608KF-181T15/1.5A/180ohm_6 DPE_VDD10 L41 EV@0_4
AK33 DPF_VDD10#1
DPE_VDD10 AK34 DP C/D_PVDD : AMD request. if no
C228 C204 C227 DPF_VDD10#2 C635 C620 C631
NC_DPF_PVDD AL38 use, need to conect to +1.8V_GPU
EV@0.1u/10V_4 EV@10u/6.3V_6 AM35 *10u/6.3V_6 *1u/6.3V_4 *0.1u/10V_4
EV@1u/6.3V_4 NC_DPF_PVSS
AF39 DPF_VSSR#1
AH39 (1.8V@40mA DPE/F_PVDD) +1.8V_GPU
DPF_VSSR#2 DPE_PVDD L40 EV@SBY100505T-121Y-N/300mA/120ohm_4
AK39 DPF_VSSR#3
AL34 DPF_VSSR#4
AM34 DPF_VSSR#5 C612 C619 C616
EV@10u/6.3V_6 EV@0.1u/10V_4
EV@1u/6.3V_4
A R400 EV@150/F_4 DPEF_CALR AM39 A
DPEF_CALR
SP@Capilano/Robson
PROJECT :ZRB
1A
5 4 3 2 1
5 4 3 2 1
PIN STRAPS(VGA) Maintenance and Service Guide,Service Manual,Motherboard Schematics for Laptop/notebook http://mycomp.su/x/
CONFIGURATION STRAPS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
+3V_D THEY MUST NOT CONFLICT DURING RESET
Size of the primary memory apertures GPIO[13:11]
R82 *10K_4 STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS DEFAULT REMARK
[17] GPU_GPIO0
R85 *10K_4
128 MB 000 0 = 50% TX OUTPUT SWING
[17] GPU_GPIO1
TX_PWRS_ENB GPIO0 1 = FULL TX OUTPUT SWING 0
D D
PCIE TRANSMITTER DE-EMPHASIS ENABLED
256MB 001 TX_DEEMPH_EN GPIO1 0 = TX DE-EMPHASIS DISABLED 0
R77 *10K_4 1 = TX DE-EMPHASIS ENABLED
[17] GPIO3_SMBDAT
R76 *10K_4 Enable external BIOS ROM device
[17] GPIO4_SMBCLK 64 MB 010 BIOS_ROM_EN GPIO_22_ROMCSB 0 - Disable external BIOS ROM device 0
1 - Enable external BIOS ROM device
R101 *10K_4
[17] GPU_GPIO13 32 MB 011 ROMIDCFG[2:0] GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT See ROM table
001
R105 *10K_4
[17] GPU_GPIO12
R94 EV@10K_4 BIF_GEN2_EN_A GPIO2 0 = PCIE DEVICE AS 2.5GT/S CAPABLE 0
[17] GPU_GPIO11 More than 512 MB Not Supported 1 = PCIE DEVICE AS 5GT/S CAPABLE
R86 *10K_4 GPIO_8_ROMSO GPIO8

[17] GPU_GPIO2
H2SYNC H2SYNC Reserved Only 0
GPIO_21_BB_EN GPIO21
R378 EV@10K_4
[17,24] EV_HSYNC
AUD[1:0]
R379 EV@10K_4 AUD[1] HSYNC 00: NO AUDIO FUNCTION.
[17,24] EV_VSYNC
01: AUDIO FOR DISPLAYPORT AND HDMI IF
AUD[0] VSYNC ADAPTER IS DETECTED. 11 See Audio table
10: AUDIO FOR DISPLAYPORT ONLY.
R408 *10K_4 11: AUDIO FOR BOTH DISPLAYPORT AND HDMI.

[17] V2SYNC
GPIO_9_ROMSI GPIO9 0 = VGA controller capacity enable 0

C C
VIP_DEVICE_STRAP_ENA V2SYNC 0 = DRIVER would ignore the value sample on VHAD_0 during RESET. 0
DDR3 Memory Aperture size(GPU)
DDR3 Memory size

RAM_STRAP2 RAM_STRAP1 RAM_STRAP0
Vendor Vendor P/N STN B/S P/N
DVPDATA_2 DVPDATA_1 DVPDATA_0
1 1 0
Hynix
H5TQ1G63BFR-12C AKD5LZGTW04 (64M*16)
1 0 0
H5TQ2G63BFR-12C AKD5MGGTW03 (128M*16)
B 1 0 1 B
Thermal Sensor(VGA)
K4W1G1646E-HC12 AKD5LGGT506 (64M*16)
Vendor P/N Samsung 0 0 0
WINDBOND AL83L771K01
K4W2G1646B-HC12 AKD5MGGT500 (128m*16)
GMT AL000780000 USD0.16 0 0 1
23EY2387MA12-SZ AKD5LGGT700
0 1 0
+3V_D_S
AMD
+3V_D_S
R433 R423 ADDRESS: 98H C642 EV@0.1u/10V_4

EV@10K_4 *10K_4
U23 Samsung - 1Gb +1.8V_GPU
[36] MXM_SMCLK12 8 SCLK VCC 1 GPU_D+ [17]

R421 SP@10K_4
[17] RAM_STRAP2
C638
A
[36] MXM_SMDATA12 7 SDA DXP 2
R410 SP@10K_4 RAM_STRAP2 SET DDR3 Vendor A
EV@2200p/50V_4
[17] ALT#_GPIO17 6 ALERT# DXN 3
GPU_D- [17]
RAM_STRAP[1:0] SET SIZE.
[36] VGA_THERM# 4 OVERT# GND 5
R422 *10K_4
[17] RAM_STRAP1
EV@G780P81U R411 EV@10K_4
ADDRESS: 98H Quanta Computer Inc.
R420 SP@10K_4
PROJECT :ZRB
R409 SP@10K_4 Size Document Number Rev
[17] RAM_STRAP0
1A
Strip/Thermal
5 4 3 2 1
5 4 3 2 1
[18] VMA_DQ[63..0]
VMA_DQ[63..0] Maintenance and Service Guide,Service Manual,Motherboard Schematics for Laptop/notebook http://mycomp.su/x/
[18] VMA_DM[7..0]
VMA_DM[7..0] CHANNEL A: 512MB DDR3 (64M*16*4pcs)
VMA_RDQS[7..0] QSA[7..0]
[18] VMA_RDQS[7..0]
VMA_WDQS[7..0] QSA#[7..0]
[18] VMA_WDQS[7..0]
U2 U18 U17 U3
VREFC_VMA1 M8 E3 VMA_DQ9 VREFC_VMA2 M8 E3 VMA_DQ1 VREFC_VMA3 M8 E3 VMA_DQ57 VREFC_VMA4 M8 E3 VMA_DQ55

VREFD_VMA1 VREFCA DQL0 VMA_DQ8 VREFD_VMA2 VREFCA DQL0 VMA_DQ5 VREFD_VMA3 VREFCA DQL0 VMA_DQ62 VREFD_VMA4 VREFCA DQL0 VMA_DQ48
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 VMA_DQ13 F2 VMA_DQ2 F2 VMA_DQ59 F2 VMA_DQ54
VMA_MA0 DQL2 VMA_DQ11 VMA_MA0 DQL2 VMA_DQ7 VMA_MA0 DQL2 VMA_DQ60 VMA_MA0 DQL2 VMA_DQ51
[18] VMA_MA0 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8
VMA_MA1 P7 H3 VMA_DQ15 VMA_MA1 P7 H3 VMA_DQ0 VMA_MA1 P7 H3 VMA_DQ58 VMA_MA1 P7 H3 VMA_DQ52
[18] VMA_MA1 A1 DQL4 A1 DQL4 A1 DQL4 A1 DQL4
VMA_MA3 N2 G2 VMA_DQ14 VMA_MA3 N2 G2 VMA_DQ3 VMA_MA3 N2 G2 VMA_DQ56 VMA_MA3 N2 G2 VMA_DQ53
D [18] VMA_MA3 A3 DQL6 A3 DQL6 A3 DQL6 A3 DQL6 D
VMA_MA5 P2 VMA_MA5 P2 VMA_MA5 P2 VMA_MA5 P2
[18] VMA_MA5 A5 A5 A5 A5
VMA_MA6 R8 VMA_MA6 R8 VMA_MA6 R8 VMA_MA6 R8
[18] VMA_MA6 A6 A6 A6 A6
VMA_MA7 R2 D7 VMA_DQ19 VMA_MA7 R2 D7 VMA_DQ31 VMA_MA7 R2 D7 VMA_DQ39 VMA_MA7 R2 D7 VMA_DQ44
[18] VMA_MA7 A7 DQU0 A7 DQU0 A7 DQU0 A7 DQU0
VMA_MA8 T8 C3 VMA_DQ22 VMA_MA8 T8 C3 VMA_DQ25 VMA_MA8 T8 C3 VMA_DQ35 VMA_MA8 T8 C3 VMA_DQ45
VMA_MA9 R3 C8 VMA_DQ17 VMA_MA9 R3 C8 VMA_DQ30 VMA_MA9 R3 C8 VMA_DQ37 VMA_MA9 R3 C8 VMA_DQ40
VMA_MA10 L7 C2 VMA_DQ20 VMA_MA10 L7 C2 VMA_DQ26 VMA_MA10 L7 C2 VMA_DQ32 VMA_MA10 L7 C2 VMA_DQ47
[18] VMA_MA10 A10/AP DQU3 A10/AP DQU3 A10/AP DQU3 A10/AP DQU3
VMA_MA11 R7 A7 VMA_DQ18 VMA_MA11 R7 A7 VMA_DQ28 VMA_MA11 R7 A7 VMA_DQ36 VMA_MA11 R7 A7 VMA_DQ42
VMA_MA12 N7 A2 VMA_DQ21 VMA_MA12 N7 A2 VMA_DQ27 VMA_MA12 N7 A2 VMA_DQ33 VMA_MA12 N7 A2 VMA_DQ46
[18] VMA_MA12 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5
VMA_MA13 T3 B8 VMA_DQ16 VMA_MA13 T3 B8 VMA_DQ29 VMA_MA13 T3 B8 VMA_DQ38 VMA_MA13 T3 B8 VMA_DQ41
T7 A3 VMA_DQ23 T7 A3 VMA_DQ24 T7 A3 VMA_DQ34 T7 A3 VMA_DQ43
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 A15 M7 A15 M7 A15 M7 A15
+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU
VMA_BA0 M2 B2 VMA_BA0 M2 B2 VMA_BA0 M2 B2 VMA_BA0 M2 B2

[18] VMA_BA0 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2
VMA_BA1 N8 D9 VMA_BA1 N8 D9 VMA_BA1 N8 D9 VMA_BA1 N8 D9
[18] VMA_BA1 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
VMA_BA2 M3 G7 VMA_BA2 M3 G7 VMA_BA2 M3 G7 VMA_BA2 M3 G7
[18] VMA_BA2 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
VDD#K2 K2 VDD#K2 K2 VDD#K2 K2 VDD#K2 K2
VDD#N1 N1 VDD#N1 N1 VDD#N1 N1 VDD#N1 N1
VMA_CLK0 J7 N9 VMA_CLK0 J7 N9 VMA_CLK1 J7 N9 VMA_CLK1 J7 N9
[18] VMA_CLK0 CK VDD#N9 CK VDD#N9 [18] VMA_CLK1 CK VDD#N9 CK VDD#N9
VMA_CLK0# K7 R1 VMA_CLK0# K7 R1 VMA_CLK1# K7 R1 VMA_CLK1# K7 R1
[18] VMA_CLK0# CK VDD#R1 CK VDD#R1 [18] VMA_CLK1# CK VDD#R1 CK VDD#R1
VMA_CKE0 K9 R9 VMA_CKE0 K9 R9 VMA_CKE1 K9 R9 VMA_CKE1 K9 R9
[18] VMA_CKE0 CKE VDD#R9 CKE VDD#R9 [18] VMA_CKE1 CKE VDD#R9 CKE VDD#R9
VMA_ODT0 K1 A1 VMA_ODT0 K1 A1 VMA_ODT1 K1 A1 VMA_ODT1 K1 A1

[18] VMA_ODT0 ODT VDDQ#A1 ODT VDDQ#A1 [18] VMA_ODT1 ODT VDDQ#A1 ODT VDDQ#A1
VMA_CS0# L2 A8 VMA_CS0# L2 A8 VMA_CS1# L2 A8 VMA_CS1# L2 A8
[18] VMA_CS0# CS VDDQ#A8 CS VDDQ#A8 [18] VMA_CS1# CS VDDQ#A8 CS VDDQ#A8
VMA_RAS0# J3 C1 VMA_RAS0# J3 C1 VMA_RAS1# J3 C1 VMA_RAS1# J3 C1
[18] VMA_RAS0# RAS VDDQ#C1 RAS VDDQ#C1 [18] VMA_RAS1# RAS VDDQ#C1 RAS VDDQ#C1
VMA_CAS0# K3 C9 VMA_CAS0# K3 C9 VMA_CAS1# K3 C9 VMA_CAS1# K3 C9
[18] VMA_CAS0# CAS VDDQ#C9 CAS VDDQ#C9 [18] VMA_CAS1# CAS VDDQ#C9 CAS VDDQ#C9
VMA_WE0# L3 D2 VMA_WE0# L3 D2 VMA_WE1# L3 D2 VMA_WE1# L3 D2
[18] VMA_WE0# WE VDDQ#D2 WE VDDQ#D2 [18] VMA_WE1# WE VDDQ#D2 WE VDDQ#D2
VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#E9 E9
VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1
VMA_RDQS1 F3 H2 VMA_RDQS0 F3 H2 VMA_RDQS7 F3 H2 VMA_RDQS6 F3 H2
VMA_RDQS2 DQSL VDDQ#H2 VMA_RDQS3 DQSL VDDQ#H2 VMA_RDQS4 DQSL VDDQ#H2 VMA_RDQS5 DQSL VDDQ#H2
C7 DQSU VDDQ#H9 H9 C7 DQSU VDDQ#H9 H9 C7 DQSU VDDQ#H9 H9 C7 DQSU VDDQ#H9 H9
VMA_DM1 E7 A9 VMA_DM0 E7 A9 VMA_DM7 E7 A9 VMA_DM6 E7 A9

VMA_DM2 DML VSS#A9 VMA_DM3 DML VSS#A9 VMA_DM4 DML VSS#A9 VMA_DM5 DML VSS#A9
C D3 DMU VSS#B3 B3 D3 DMU VSS#B3 B3 D3 DMU VSS#B3 B3 D3 DMU VSS#B3 B3 C
VSS#E1 E1 VSS#E1 E1 VSS#E1 E1 VSS#E1 E1

VSS#G8 G8 VSS#G8 G8 VSS#G8 G8 VSS#G8 G8
VMA_WDQS1 G3 J2 VMA_WDQS0 G3 J2 VMA_WDQS7 G3 J2 VMA_WDQS6 G3 J2
VMA_WDQS2 DQSL VSS#J2 VMA_WDQS3 DQSL VSS#J2 VMA_WDQS4 DQSL VSS#J2 VMA_WDQS5 DQSL VSS#J2
B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8
VSS#M1 M1 VSS#M1 M1 VSS#M1 M1 VSS#M1 M1
VSS#P1 P1 VSS#P1 P1 VSS#P1 P1 VSS#P1 P1
MEM_RST# T2 P9 MEM_RST# T2 P9 MEM_RST# T2 P9 MEM_RST# T2 P9
[18,23] MEM_RST# RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
VSS#T1 T1 VSS#T1 T1 VSS#T1 T1 VSS#T1 T1
VMA_ZQ1 L8 T9 VMA_ZQ2 L8 T9 VMA_ZQ3 L8 T9 VMA_ZQ4 L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
VSSQ#B1 B1 VSSQ#B1 B1 VSSQ#B1 B1 VSSQ#B1 B1

R22 D1 R347 D1 R345 D1 R27 D1
VSSQ#D1 VSSQ#D1 VSSQ#D1 VSSQ#D1
SP@243/F_4 VSSQ#D8 D8 SP@243/F_4 VSSQ#D8 D8 SP@243/F_4 VSSQ#D8 D8 SP@243/F_4 VSSQ#D8 D8
VSSQ#E2 E2 VSSQ#E2 E2 VSSQ#E2 E2 VSSQ#E2 E2
J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8
L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9
J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1
L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9
100-BALL 100-BALL 100-BALL 100-BALL

SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
SP@VRAM _DDR3 SP@VRAM _DDR3 SP@VRAM _DDR3 SP@VRAM _DDR3
TOP Left BOT Left BOT Right TOP Right

Group-A0 VREF Group-A1 VREF
+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU
B B
R339 R356 R340 R346 R30 R354 R24 R32
SP@4.99K/F_4 SP@4.99K/F_4 SP@4.99K/F_4 SP@4.99K/F_4 SP@4.99K/F_4 SP@4.99K/F_4 SP@4.99K/F_4 SP@4.99K/F_4
VREFC_VMA1 VREFD_VMA1 VREFC_VMA2 VREFD_VMA2 VREFC_VMA3 VREFD_VMA3 VREFC_VMA4 VREFD_VMA4
R341 R360 R344 R353 R29 R357 R23 R31

SP@4.99K/F_4C517 SP@4.99K/F_4C534 SP@4.99K/F_4C525 SP@4.99K/F_4C532 SP@4.99K/F_4 C35 SP@4.99K/F_4 C535 SP@4.99K/F_4C17 SP@4.99K/F_4C36
SP@.1u/10V_4 SP@.1u/10V_4 SP@.1u/10V_4 SP@.1u/10V_4 SP@.1u/10V_4 SP@.1u/10V_4 SP@.1u/10V_4 SP@.1u/10V_4
Group-A0 decoupling CAP Group-A1 decoupling CAP MEM_A1 CLK

MEM_A0 CLK
+1.5V_GPU
+1.5V_GPU
VMA_CLK1
VMA_CLK0
VMA_CLK1#
VMA_CLK0# C512 C523 C513 C526 C34 C21 C20 C22
C43 C44 C16 C38 C543 C524 C540 C531 SP@1u/6.3V_4SP@1u/6.3V_4SP@1u/6.3V_4SP@1u/6.3V_4SP@1u/6.3V_4SP@1u/6.3V_4SP@1u/6.3V_4SP@1u/6.3V_4
SP@1u/6.3V_4SP@1u/6.3V_4SP@1u/6.3V_4SP@1u/6.3V_4SP@1u/6.3V_4SP@1u/6.3V_4SP@1u/6.3V_4SP@1u/6.3V_4 R355 R359
R358 R361 SP@56.2/F_4 SP@56.2/F_4
SP@56.2/F_4 SP@56.2/F_4
+1.5V_GPU
+1.5V_GPU
C530
C536 C509 C520 C516 C41 C528 C31 C19 C18 SP@.01u/16V_4
SP@.01u/16V_4 C39 C37 C544 C537 C539 C538 C42 C40 SP@1u/6.3V_4SP@1u/6.3V_4SP@1u/6.3V_4SP@1u/6.3V_4SP@1u/6.3V_4SP@1u/6.3V_4SP@1u/6.3V_4SP@1u/6.3V_4
A SP@1u/6.3V_4SP@1u/6.3V_4SP@1u/6.3V_4SP@1u/6.3V_4SP@1u/6.3V_4SP@1u/6.3V_4SP@1u/6.3V_4SP@1u/6.3V_4 A
+1.5V_GPU
+1.5V_GPU
C515 C519 C25 C26 C30 Quanta Computer Inc.

C33 C24 C29 C510 C511 SP@10u/6.3V_6 SP@10u/6.3V_6 SP@10u/6.3V_6 SP@10u/6.3V_6 SP@10u/6.3V_6
SP@10u/6.3V_6 SP@10u/6.3V_6 SP@10u/6.3V_6 SP@10u/6.3V_6 SP@10u/6.3V_6
PROJECT : ZRB
1A
MEMORY 1 channel A
5 4 3 2 1
5 4 3 2 1

[18] VMB_DQ[63..0]
VMB_DQ[63..0] CHANNEL B: 512MB DDR3 (16*64M*4pcs)
[18] VMB_DM[7..0]
VMB_DM[7..0]
VMB_RDQS[7..0]
Park, M92M Use Channel B Memory Interface Only
[18] VMB_RDQS[7..0] QSA[7..0]
VMB_WDQS[7..0] QSA#[7..0]
[18] VMB_WDQS[7..0]
U4 U19 U22 U5
VREFC_VMB1 M8 E3 VMB_DQ24 VREFC_VMB2 M8 E3 VMB_DQ20 VREFC_VMB3 M8 E3 VMB_DQ32 VREFC_VMB4 M8 E3 VMB_DQ46

VREFD_VMB1 VREFCA DQL0 VMB_DQ26 VREFD_VMB2 VREFCA DQL0 VMB_DQ18 VREFD_VMB3 VREFCA DQL0 VMB_DQ37 VREFD_VMB4 VREFCA DQL0 VMB_DQ42
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 VMB_DQ31 F2 VMB_DQ16 F2 VMB_DQ35 F2 VMB_DQ47
VMB_MA0 DQL2 VMB_DQ27 VMB_MA0 DQL2 VMB_DQ21 VMB_MA0 DQL2 VMB_DQ36 VMB_MA0 DQL2 VMB_DQ41
N3 F8 N3 F8 N3 F8 N3 F8
[18] VMB_MA0
[18] VMB_MA1
[18] VMB_MA2
VMB_MA1
VMB_MA2
VMB_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMB_DQ30
VMB_DQ28
VMB_DQ29
3 VMB_MA1
VMB_MA2
VMB_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMB_DQ19
VMB_DQ22
VMB_DQ17
2 VMB_MA1
VMB_MA2
VMB_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMB_DQ33
VMB_DQ38
VMB_DQ34
4 VMB_MA1
VMB_MA2
VMB_MA3
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMB_DQ45
VMB_DQ40
VMB_DQ44
6
D [18] VMB_MA3 N2 A3 DQL6 G2 N2 A3 DQL6 G2 N2 A3 DQL6 G2 N2 A3 DQL6 G2 D
VMB_MA4 P8 H7 VMB_DQ25 VMB_MA4 P8 H7 VMB_DQ23 VMB_MA4 P8 H7 VMB_DQ39 VMB_MA4 P8 H7 VMB_DQ43
[18] VMB_MA4 A4 DQL7 A4 DQL7 A4 DQL7 A4 DQL7
VMB_MA5 P2 VMB_MA5 P2 VMB_MA5 P2 VMB_MA5 P2
[18] VMB_MA5 A5 A5 A5 A5
VMB_MA6 R8 VMB_MA6 R8 VMB_MA6 R8 VMB_MA6 R8
[18] VMB_MA6 A6 A6 A6 A6
VMB_MA7 R2 D7 VMB_DQ3 VMB_MA7 R2 D7 VMB_DQ15 VMB_MA7 R2 D7 VMB_DQ63 VMB_MA7 R2 D7 VMB_DQ50
[18] VMB_MA7 A7 DQU0 A7 DQU0 A7 DQU0 A7 DQU0
VMB_MA8 T8 C3 VMB_DQ6 VMB_MA8 T8 C3 VMB_DQ10 VMB_MA8 T8 C3 VMB_DQ59 VMB_MA8 T8 C3 VMB_DQ55
VMB_MA9 R3 C8 VMB_DQ0 VMB_MA9 R3 C8 VMB_DQ14 VMB_MA9 R3 C8 VMB_DQ60 VMB_MA9 R3 C8 VMB_DQ48
[18] VMB_MA9
[18] VMB_MA10
[18] VMB_MA11
VMB_MA10
VMB_MA11
VMB_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMB_DQ4
VMB_DQ2
VMB_DQ5
0 VMB_MA10
VMB_MA11
VMB_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMB_DQ9
VMB_DQ12
VMB_DQ8
1 VMB_MA10
VMB_MA11
VMB_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMB_DQ56
VMB_DQ62
VMB_DQ57
7 VMB_MA10
VMB_MA11
VMB_MA12
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMB_DQ52
VMB_DQ51
VMB_DQ54
5
[18] VMB_MA12 N7 A12/BC DQU5 A2 N7 A12/BC DQU5 A2 N7 A12/BC DQU5 A2 N7 A12/BC DQU5 A2
VMB_MA13 T3 B8 VMB_DQ1 VMB_MA13 T3 B8 VMB_DQ13 VMB_MA13 T3 B8 VMB_DQ61 VMB_MA13 T3 B8 VMB_DQ49
T7 A3 VMB_DQ7 T7 A3 VMB_DQ11 T7 A3 VMB_DQ58 T7 A3 VMB_DQ53
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 A15 M7 A15 M7 A15 M7 A15
VMB_BA0 M2 B2 VMB_BA0 M2 B2 VMB_BA0 M2 B2 VMB_BA0 M2 B2

[18] VMB_BA0 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2
VMB_BA1 N8 D9 VMB_BA1 N8 D9 VMB_BA1 N8 D9 VMB_BA1 N8 D9
[18] VMB_BA1 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
VMB_BA2 M3 G7 VMB_BA2 M3 G7 VMB_BA2 M3 G7 VMB_BA2 M3 G7
[18] VMB_BA2 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
VDD#N1 N1 VDD#N1 N1 VDD#N1 N1 VDD#N1 N1
VMB_CLKP0 J7 N9 VMB_CLKP0 J7 N9 VMB_CLKP1 J7 N9 VMB_CLKP1 J7 N9
[18] VMB_CLKP0 CK VDD#N9 CK VDD#N9 [18] VMB_CLKP1 CK VDD#N9 CK VDD#N9
VMB_CLKN0 K7 R1 VMB_CLKN0 K7 R1 VMB_CLKN1 K7 R1 VMB_CLKN1 K7 R1
[18] VMB_CLKN0 CK VDD#R1 CK VDD#R1 [18] VMB_CLKN1 CK VDD#R1 CK VDD#R1
VMB_CKE0 K9 R9 VMB_CKE0 K9 R9 VMB_CKE1 K9 R9 VMB_CKE1 K9 R9
[18] VMB_CKE0 CKE VDD#R9 CKE VDD#R9 [18] VMB_CKE1 CKE VDD#R9 CKE VDD#R9
VMB_ODT0 K1 A1 VMB_ODT0 K1 A1 VMB_ODT1 K1 A1 VMB_ODT1 K1 A1

[18] VMB_ODT0 ODT VDDQ#A1 ODT VDDQ#A1 [18] VMB_ODT1 ODT VDDQ#A1 ODT VDDQ#A1
VMB_CS0# L2 A8 VMB_CS0# L2 A8 VMB_CS1# L2 A8 VMB_CS1# L2 A8
[18] VMB_CS0# CS VDDQ#A8 CS VDDQ#A8 [18] VMB_CS1# CS VDDQ#A8 CS VDDQ#A8
VMB_RAS0# J3 C1 VMB_RAS0# J3 C1 VMB_RAS1# J3 C1 VMB_RAS1# J3 C1
[18] VMB_RAS0# RAS VDDQ#C1 RAS VDDQ#C1 [18] VMB_RAS1# RAS VDDQ#C1 RAS VDDQ#C1
VMB_CAS0# K3 C9 VMB_CAS0# K3 C9 VMB_CAS1# K3 C9 VMB_CAS1# K3 C9
[18] VMB_CAS0# CAS VDDQ#C9 CAS VDDQ#C9 [18] VMB_CAS1# CAS VDDQ#C9 CAS VDDQ#C9
VMB_WE0# L3 D2 VMB_WE0# L3 D2 VMB_WE1# L3 D2 VMB_WE1# L3 D2
[18] VMB_WE0# WE VDDQ#D2 WE VDDQ#D2 [18] VMB_WE1# WE VDDQ#D2 WE VDDQ#D2
VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#E9 E9 VDDQ#E9 E9
VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1 VDDQ#F1 F1
VMB_RDQS3 F3 H2 VMB_RDQS2 F3 H2 VMB_RDQS4 F3 H2 VMB_RDQS5 F3 H2
VMB_RDQS0 DQSL VDDQ#H2 VMB_RDQS1 DQSL VDDQ#H2 VMB_RDQS7 DQSL VDDQ#H2 VMB_RDQS6 DQSL VDDQ#H2
C7 DQSU VDDQ#H9 H9 C7 DQSU VDDQ#H9 H9 C7 DQSU VDDQ#H9 H9 C7 DQSU VDDQ#H9 H9
VMB_DM3 E7 A9 VMB_DM2 E7 A9 VMB_DM4 E7 A9 VMB_DM5 E7 A9

VMB_DM0 DML VSS#A9 VMB_DM1 DML VSS#A9 VMB_DM7 DML VSS#A9 VMB_DM6 DML VSS#A9
C D3 DMU VSS#B3 B3 D3 DMU VSS#B3 B3 D3 DMU VSS#B3 B3 D3 DMU VSS#B3 B3 C
VSS#E1 E1 VSS#E1 E1 VSS#E1 E1 VSS#E1 E1

VSS#G8 G8 VSS#G8 G8 VSS#G8 G8 VSS#G8 G8
VMB_WDQS3 G3 J2 VMB_WDQS2 G3 J2 VMB_WDQS4 G3 J2 VMB_WDQS5 G3 J2
VMB_WDQS0 DQSL VSS#J2 VMB_WDQS1 DQSL VSS#J2 VMB_WDQS7 DQSL VSS#J2 VMB_WDQS6 DQSL VSS#J2
B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8 B7 DQSU VSS#J8 J8
VSS#P1 P1 VSS#P1 P1 VSS#P1 P1 VSS#P1 P1
MEM_RST# T2 P9 MEM_RST# T2 P9 MEM_RST# T2 P9 MEM_RST# T2 P9
[18,22] MEM_RST# RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
VSS#T1 T1 VSS#T1 T1 VSS#T1 T1 VSS#T1 T1
VMB_ZQ1 L8 T9 VMB_ZQ2 L8 T9 VMB_ZQ3 L8 T9 VMB_ZQ4 L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9

R35 D1 R370 D1 R418 D1 R56 D1
VSSQ#D1 VSSQ#D1 VSSQ#D1 VSSQ#D1
EV@240/F_4 VSSQ#D8 D8 EV@240/F_4 VSSQ#D8 D8 EV@240/F_4 VSSQ#D8 D8 EV@240/F_4 VSSQ#D8 D8
VSSQ#E2 E2 VSSQ#E2 E2 VSSQ#E2 E2 VSSQ#E2 E2
J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8 J1 NC#J1 VSSQ#E8 E8
L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9 L1 NC#L1 VSSQ#F9 F9
J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1 J9 NC#J9 VSSQ#G1 G1
L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9 L9 NC#L9 VSSQ#G9 G9
100-BALL 100-BALL 100-BALL 100-BALL

SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
SP@VRAM _DDR3 SP@VRAM _DDR3 SP@VRAM _DDR3 SP@VRAM _DDR3
BOT Down TOP Down TOP Up BOT Up
Group-B0 VREF Group-B1 VREF

+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU
B B
R368 R42 R372 R367 R107 R377 R80 R106

EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4
VREFC_VMB1 VREFD_VMB1 VREFC_VMB2 VREFD_VMB2 VREFC_VMB3 VREFD_VMB3 VREFC_VMB4 VREFD_VMB4
R363 C547 R43 C127 R371 C554 R364 C549 R108 C260 R376 C572 R79 C207 R104 C259
EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4 EV@4.99K/F_4
EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4 EV@0.1u/10V_4
Group-B0 decoupling CAP Group-B1 decoupling CAP MEM_B1 CLK

MEM_B0 CLK
+1.5V_GPU +1.5V_GPU
VMB_CLKP1
VMB_CLKP0 VMB_CLKN1
C557 C565 C550 C556 C558 C49 C261 C559 C265 C47 C53 C258 C574 C124 C236 C630
VMB_CLKN0 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4
EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 R415 R416
EV@56.2/F_4
R365 R366 EV@56.2/F_4
EV@56.2/F_4 +1.5V_GPU +1.5V_GPU
EV@56.2/F_4
A C637 A
C555 C264 C46 C121 C566 C125 C45 C262 C548 C252 C629 C243 C573 C560 C233 C546 EV@0.01u/16V_4
C545 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4
EV@0.01u/16V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4 EV@1u/6.3V_4
+1.5V_GPU +1.5V_GPU
C564 C90 C551 C552 C561 C632 C118 C219 C634 C633
EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6
EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 EV@10u/6.3V_6 PROJECT : ZRB
1A
MEMORY 2 channel B
5 4 3 2 1
1 2 3 4 5 6 7 8
CRT Switch Maintenance and Service Guide,Service Manual,Motherboard Schematics for Laptop/notebook http://mycomp.su/x/
CRT
C277 0.1u/10V_4
F2
D15 SSM22LLPT CRTVDD5
16
+5V 2 1
CN8
0_ohm Resistor place close to Joint-Point SMD1206P110TFT CRT-CONN
6
VGA_RED L25 BLM18BA750SN1D/0.3A/75ohm_6 CRT_R1 1 11 CRT_11 T24
7
VGA_GRN L24 BLM18BA750SN1D/0.3A/75ohm_6 CRT_G1 2 12 DDCDAT_1
8
INT_CRT_RED R73 IV@0_4 VGA_RED VGA_BLU L23 BLM18BA750SN1D/0.3A/75ohm_6 CRT_B1 3 13 CRTHSYNC
[8] INT_CRT_RED
INT_CRT_GRN R81 IV@0_4 VGA_GRN 9
[8] INT_CRT_GRN
INT_CRT_BLU R69 IV@0_4 VGA_BLU 4 14 CRTVSYNC
A [8] INT_CRT_BLU A
R139 R130 R124 C304 C294 C287 C666 C677 C689 10
5 15 DDCCLK_1
INT_VSYNC RN1 1 2 IV@0_4P2R VSYNC 150/F_4 150/F_4 150/F_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4
[8] INT_VSYNC
INT_HSYNC HSYNC
IV@ [8] INT_HSYNC 3 4
17
INT_CRT_DDCDAT RN3 1 2 IV@0_4P2R CRTDDATA
[8] INT_CRT_DDCDAT
INT_CRT_DDCCLK 3 4 CRTDCLK
[8] INT_CRT_DDCCLK
EV_CRT_BLU R383 EV@0_4 VGA_BLU REV : C Change to 0402 R

[17] EV_CRT_BLU
EV_CRT_GRN R388 EV@0_4 VGA_GRN
[17] EV_CRT_GRN
EV_CRT_RED R384 EV@0_4 VGA_RED REV : B Change to short pad
[17] EV_CRT_RED +3V
C291 U25
EV_HSYNC RN9 1 2 EV@0_4P2R HSYNC CRTVDD5 1 16 CRT_VSYNC2 R448 SP@10/F_4 CRTVSYNC C698 *.1u/10V_4 CRTVDD5
[17,21] EV_HSYNC VCC_SYNC SYNC_OUT2
EV_VSYNC VSYNC 0.1u/10V_4_X7R CRT_HSYNC2 R447 SP@10/F_4 CRTHSYNC
EV@ [17,21] EV_VSYNC 3 4
7
SYNC_OUT1 14
C647 IV@15p/50V_4 CRTVSYNC
C661 .22u/25V_6 CRT_BYP VCC_DDC
8 BYP
EV_CRTDCLK RN11 1 2 EV@0_4P2R CRTDCLK 15 VSYNC CRTVDD5 C646 IV@15p/50V_4 CRTHSYNC
[17] EV_CRTDCLK SYNC_IN2 +3V
EV_CRTDDAT 3 4 CRTDDATA 2 13 HSYNC
[17] EV_CRTDDAT +3V VCC_VIDEO SYNC_IN1 C660 10p/50V_4 DDCCLK_1
C299 R445 R460
CRT_R1 3 10 CRTDCLK R451 2.7K_4 C676 10p/50V_4 DDCDAT_1
0.1u/10V_4_X7R CRT_G1 VIDEO_1 DDC_IN1 CRTDDATA R455 2.7K_4 2.7K_4 2.7K_4
4 VIDEO_2 DDC_IN2 11
CRT_B1 5 VIDEO_3 DDCCLK_1
DDC_OUT1 9
6 12 DDCDAT_1
GND DDC_OUT2
CM2009-02QR
B B
LVDS LVDS LCD Power

+3V VIN
+3V
0_ohm Resistor place close to Joint-Point
C8 C7
C3 C2
INT_LVDS_EDIDCLK RN15 3 4 IV@0_4P2R LCD_EDIDCLK 0.1u/10V_4_X7R C1 U1
[8] INT_LVDS_EDIDCLK
INT_LVDS_EDIDDATA 1 2 LCD_EDIDDATA 1000p/50V_4 4.7u/25V_8 1000p/50V_4
[8] INT_LVDS_EDIDDATA
1U/6.3V_4 6 1 LCDVCC
INT_LVDS_DIGON RN8 LVDS_VDDEN IN OUT
[8] INT_LVDS_DIGON 1 2 IV@0_4P2R
INT_LVDS_BLON 3 4 LVDS_BLON 4 2
[8] INT_LVDS_BLON IN GND C6 C5 C9 C10 C4
LVDS_VDDEN 3 5
INT_TXLCLKOUT+ RN12 1 IV@0_4P2R TXLCLKOUT+ VIN ON/OFF GND *.1u/10V_4 *2.2u/10V_8 0.1u/10V_4 .01u/25V_4 22u/6.3V_8
IV@ [8] INT_TXLCLKOUT+ 2 0.8A REV : B Change to short pad
INT_TXLCLKOUT- 3 4 TXLCLKOUT-
[8] INT_TXLCLKOUT-
INT_TXLOUT0+ RN13 1 2 IV@0_4P2R TXLOUT0+ C11 C14 AAT4280-4
[8] INT_TXLOUT0+
INT_TXLOUT0- 3 4 TXLOUT0- *1u/6.3V_4 *1u/6.3V_4 R5 *Short_8 CN5
[8] INT_TXLOUT0-
INT_TXLOUT1+ RN14 1 2 IV@0_4P2R TXLOUT1+ R10 *Short_8 INVCC0 1
[8] INT_TXLOUT1+ 1
INT_TXLOUT1- 3 4 TXLOUT1- 2 R4
[8] INT_TXLOUT1- 2
INT_TXLOUT2+ RN10 1 2 IV@0_4P2R TXLOUT2+ LCDVCC R9 *Short_6 3
[8] INT_TXLOUT2+ 3
INT_TXLOUT2- 3 4 TXLOUT2- 4
[8] INT_TXLOUT2- 4
REV : B Change to short pad +3V 5 100K_4
R13 10K_4 LCD_DETECT_C 5
[11] LCD_DETECT 6 6
LCD_DETECT +3V R7 2.2K_4 LCD_EDIDCLK 7
R8 2.2K_4 LCD_EDIDDATA 7
H --> CCFL 8 8
L --> LED 9 9
EV_LVDS_DDCCLK RN7 1 2 EV@0_4P2R LCD_EDIDCLK TXLOUT0- 10
[17] EV_LVDS_DDCCLK 10
EV_LVDS_DDCDAT 3 4 LCD_EDIDDATA TXLOUT0+ 11
[17] EV_LVDS_DDCDAT 11
12 12
EV_LVDS_VDDEN RN16 1 2 EV@0_4P2R LVDS_VDDEN TXLOUT1- 13
[17] EV_LVDS_VDDEN 13
EV_LVDS_BLON 3 4 LVDS_BLON TXLOUT1+ 14
[17] EV_LVDS_BLON 14
15 15
TXLOUT2- 16
EV_TXLCLKOUT- RN6 EV@0_4P2R TXLCLKOUT- TXLOUT2+ 16
C EV@ [17] EV_TXLCLKOUT-
EV_TXLCLKOUT+
1
3
2
4 TXLCLKOUT+
17
18
17 Backlight Control C
[17] EV_TXLCLKOUT+ 18
EV_TXLOUT0- RN5 1 2 EV@0_4P2R TXLOUT0- TXLCLKOUT- 19
[17] EV_TXLOUT0- 19
EV_TXLOUT0+ 3 4 TXLOUT0+ TXLCLKOUT+ 20
[17] EV_TXLOUT0+ 20
EV_TXLOUT1- RN4 1 2 EV@0_4P2R TXLOUT1- 21
[17] EV_TXLOUT1- 21
EV_TXLOUT1+ 3 4 TXLOUT1+ USBP8-_R 22 +3VPCU
[17] EV_TXLOUT1+ 22
EV_TXLOUT2- RN2 1 2 EV@0_4P2R TXLOUT2- USBP8+_R 23
[17] EV_TXLOUT2- 23
EV_TXLOUT2+ 3 4 TXLOUT2+ REV : B Change to short pad 24
[17] EV_TXLOUT2+ 24
+3V 25 25
R6 *Short_6 CCD_PWR 26 R440
26 *100K_4
27 27 34 34
28 28 LID591# [36]
R12 EV@0_4 LVDS_BRIGHT LVDS_BRIGHT R11 BLM15AG121SS1/0.5A/120ohm_4 29 31
[36] CONTRAST 29 31
R14 *0_4 BL_ON
LVDS_BRIGHT [17] EV_LVDS_BRIGHT
R15 IV@0_4
30 30
[8] INT_LVDS_BRIGHT
C12 C13 LVDS LID591#,EC intrnal PU
+3V
*1u/6.3V_4 *1u/6.3V_4
1
D16
BAS316
R2 *0_4 R438
2
L1 R430 10K_4
USBP8+_R BL_ON
CCD-USB [10] USBP8+ 2
3
2 1 1
4 USBP8-_R 10K_4
[10] USBP8- 3 4
3
RFCMF1632100M3T/200mA/90ohm Lid Switch (Hall sensor)
3
R3 *0_4
BL# 2
2 EC_FPBACK# [36]
3
Q4
+3VPCU 2N7002K Q8
CCD +3V-current budget 0.2A
DTC144EUA
1
LVDS_BLON 2
C503 0.1u/10V_4 Q5
D R437 2N7002K D
1
1
100K_4
2 LID591#
HE1
2
PT3661-BB
3
PT3661-BB : AL003661003 D12

EM-6781-T3 : AL006781000 *VPORT_6

1
PROJECT : ZRB
1A
CRT/LVDS/CAMERA/LID
1 2 3 4 5 6 7 8
5 4 3 2 1

U13 : LV
HDMI LEVEL SHIFTER HDMI-detect +3V +3V
R271 R270
+3V 10K_4 EV@10K_4
HDMI_MB_HP
HDMI_DDCDATA_MB HDMI_HPD_EC# HDMI_HP
HDMI_DDCCLK_MB
3
C319 C700 C323 C324 C699 +3V R180 IV@4.7K_4 HDMI_HPD_EC# +5V
IV@2.2u/6.3V_6 IV@.1u/10V_4 IV@.1u/10V_4 IV@.1u/10V_4 IV@.1u/10V_4 DDCBUF_EN

CFG
EV@
D 2 D
+3V +3V R274 REV : B Change P/N
3
Active Buffer *10K_4 Q18 for ESD
close to pin2/11/15/21/26/33/40/46 EV@2N7002E
+3V
1
HDMI_MB_HP
36
35
34
33
32
31
30
29
28
27
26
25
U7 2
GND
VCC
DDC_EN
GND
GND
VCC
HPD_SINK
SDA_SINK
SCL_SINK
CCT2
CCT1
OE#
C312 C303 Q17
2N7002E
from PCH
1
IV@.1u/10V_4 *.1u/10V_4 37 24
GND GND MB_HDMITX0N
[8] INT_HDMITX0N 38 IN_D1- OUT_D1- 23
39 22 MB_HDMITX0P
[8] INT_HDMITX0P IN_D1+ OUT_D1+
+3V 40 VCC VCC 21 +3V
41 20 MB_HDMITX2N
[8] INT_HDMITX2N IN_D2- OUT_D2-
42 19 MB_HDMITX2P
[8] INT_HDMITX2P
43
IN_D2+
GND
OUT_D2+
GND 18
MB_HDMITX1P
I2C
[8] INT_HDMITX1P 44 IN_D3- OUT_D3- 17
45 16 MB_HDMITX1N
[8] INT_HDMITX1N IN_D3+ OUT_D3+
46 15
IV@ [8] INT_HDMICLK+
+3V
47
VCC
IN_D4-
VCC
OUT_D4- 14
+3V
MB_HDMICLK+
MB_HDMICLK-
+5V
[8] INT_HDMICLK- 48
49
IN_D4+ OUT_D4+ 13
EV@ U13 : LV
HPDEN
HPD_S
SDA_S
SCL_S
GND
2
REXT
TRIM
GND
GND
GND
VCC
VCC
HDMI_PASS
D19
NC
+3V RB501V-40 REV: B add Q25 for HDMI detect switch
1
2
3
4
5
6
7
8
9
10
11
12
IV@SN75DP139RGZR
1
+3V +3V
R186 Q14
R548 *4.7K_4 PC0 2.2K_4 R489
2
R549 *4.7K_4 +3V +3V EV@BSN20 1.5K_4
LS_REXT
PC0
R550 IV@4.7K_4 PC1 PC1 HDMI_DDCCLK_SW 1 3 HDMI_DDCCLK_MB
C C
from PCH
3
R486 *4.7K_4 DDCBUF_EN
R178 IV@4.7K_4 R138 IV@3.9K/F_4 R176 *0_4 Q25
R189
R485 *4.7K_4 CFG Control by pin4 HPDEN_R +5V HDMI_MB_HP 2
R179 *4.7K_4
[8,17] HDMI_HP EV@0_4
HDMI_PASS
2
*FDV301N
D18
1
+3V RB501V-40
[8,17] HDMI_DDCDATA_SW
[8,17] HDMI_DDCCLK_SW
1
Equalization Control R187 Q13
PC0 internal PD 2.2K_4 R488
2
PC1 PC0 EV@BSN20 1.5K_4
HDMI_PASS
PC1 internal PD
PIN4 PIN3 EQ Control
DDCBUF_EN internal PD HDMI_DDCDATA_SW 1 3 HDMI_DDCDATA_MB
L L 8dB CFG internal PD
L H 4dB
H L 12dB DDC_EN internal PU R177 *0_4
H H 0dB
B
Switchable Graphic HDMI source EMI HDMI connector B
REV : C Location :D20 Change
U13 : LV Footprint & P/N
MB_HDMITX2P CN10
C657 EV@0.1u/10V_4 INT_HDMITX0N RN20 3 4 EV@0_4P2R MB_HDMITX0N 20
[17] HDMITX0N SHELL1
C654 EV@0.1u/10V_4 INT_HDMITX0P 1 2 MB_HDMITX0P R476 *100/F_4 MB_HDMITX2P 1
[17] HDMITX0P D2+
2 D2 Shield
C643 EV@0.1u/10V_4 INT_HDMITX2N RN19 3 4 EV@0_4P2R MB_HDMITX2N MB_HDMITX2N MB_HDMITX2N 3
[17] HDMITX2N D2-
C641 EV@0.1u/10V_4 INT_HDMITX2P 1 2 MB_HDMITX2P MB_HDMITX1P 4
[17] HDMITX2P D1+
MB_HDMITX1P 5
EV@ [17] HDMITX1P
C640
C639
EV@0.1u/10V_4
EV@0.1u/10V_4
INT_HDMITX1P
INT_HDMITX1N
RN18 3 4 EV@0_4P2R MB_HDMITX1P
MB_HDMITX1N R473 *100/F_4
MB_HDMITX1N
MB_HDMITX0P
6
D1 Shield
D1-
[17] HDMITX1N 1 2 7 D0+
8 D0 Shield
C636 EV@0.1u/10V_4 INT_HDMICLK+ RN17 3 4 EV@0_4P2R MB_HDMICLK+ MB_HDMITX1N MB_HDMITX0N 9 23
[17] HDMICLK+ D0- GND
C628 EV@0.1u/10V_4 INT_HDMICLK- 1 2 MB_HDMICLK- MB_HDMICLK+ 10
[17] HDMICLK- CK+
MB_HDMITX0P 11 22
MB_HDMICLK- CK Shield GND
12 CK-
R469 R471 R472 R474 R475 R477 R479 R482 R481 *100/F_4 13
EV@499/F_4 EV@499/F_4 EV@499/F_4 EV@499/F_4 +5V CE Remote
14 NC
EV@499/F_4 EV@499/F_4 EV@499/F_4 EV@499/F_4 MB_HDMITX0N HDMI_DDCCLK_MB 15
HDMI_DDCDATA_MB DDC CLK
AC-coupling CAP place close to HDMI-connector MB_HDMICLK+ F1 2 1 SMD1206P110TFT D20 2 1RSX101M-30
16
17
DDC DATA
GND
3
18 +5V
R470 *100/F_4 HDMI_MB_HP R263 *Short_4 19
Q12 HP DET
SHELL2 21
+5V 2 MB_HDMICLK-
R545 HDMI
REV C: Change D20 footprint for HDMI C480
R454 EV@2N7002E REV : B Change P/N for ESD 100K_4 *.1u/10V_4
1
*1M_4
A SUY DFHD19MR053 A
REV : B Change to short pad and add C480

LTS DFHD19MR085

PROJECT : ZRB
1A
HDMI (PS8101)
5 4 3 2 1
5 4 3 2 1

Giga-LAN BCM57780
U10 +3V_S5
15mil
+3V_S5 42 25 BIASVDD L27 BLM18AG601SN1_6
VDDO BIASVDDH C389 0.1u/10V_4
VAUX_12 6 VDDC
15 14 XTALVDD L52 BLM18AG601SN1_6
VDDC XTALVDDH C728 0.1u/10V_4
D 41 VDDC
D
L49
15mil AVDDL 27 30 AVDDH L48 BLM18AG601SN1_6
VAUX_12 AVDDL AVDDH
C715 10U/6.3V_6 33 C717 0.1u/10V_4
BLM18AG601SN1_6 C718 0.1u/10V_4 39
AVDDL
AVDDL
BCM57780
7mm X 7mm AVDDH 36 C716
C766
0.1u/10V_4
*10U/6.3V_6
AVDDL 48-Pin QFN
L50
15mil GPHY_PLLVDD 24 37
GPHY_PLLVDDL TRD3_N LAN_TRD3N [27]
C400 4.7U/6.3V_6 38
TRD3_P LAN_TRD3P [27]
C769 BLM18AG601SN1_6 C396 0.1u/10V_4
TRD2_N 35 LAN_TRD2N [27]
0.1u/10V_4 L51
15mil PCIE_PLLVDD 18
TRD2_P 34 LAN_TRD2P [27]
PCIE_PLLVDDL
BLM18AG601SN1_6 C722 4.7U/6.3V_6 32
TRD1_P LAN_TRD1P [27]
C724 0.1u/10V_4 21 PCIE_PLLVDDL
TRD0_P 28 LAN_TRD0P [27]
Rev C: Add for LAN, near C720

48 LAN_LINKLED#
LINKLED# LAN_LINKLED# [27]
SPD100LED# 47
SPD1000LED# 46
45 LAN_ACTLED#
TRAFFICLED# LAN_ACTLED# [27]
C413 0.1u/10V_4 PCIE_RXP1_LAN_R 17
[10] PCIE_RX1+ PCIE_TXDP
C419 0.1u/10V_4 PCIE_RXN1_LAN_R 16
[10] PCIE_RX1- PCIE_TXDN
[10] PCIE_TX1+ 22 PCIE_RXDP MODE 5
[10] PCIE_TX1- 23 PCIE_RXDN
C [8,28] PCIE_WAKE# 4 WAKE# C
[4,10,11,28,32,36] PLTRST# 2 PERST#
[10] CLK_PCIE_LOM 20 PCIE_REFCLK_P
[10] CLK_PCIE_LOM# 19 PCIE_REFCLK_N
44 BCM_EEC
EECLK
43 BCM_EED
R266 1K/F_4 VMA_PRES EEDATA VAUX_12
+3V 40 VMAIN_PRSNT
R281 4.7K_4 LOW_PWR 1 LOW_PWR
11 L30 4.7uh
SR_LX
8
Don't route under Choke.
SR_VFB
C428 33p_4 R277 200/F_4 XTALO 13
XTALI XTALO
12 XTALI SR_VDDP 10 +3V_S5
1
SR_VDD 9
1.2H Y2 R245 1.24K/F_4 RDAC 26 C730 C729 C426 C430
25MHz RDAC
4.7U/6.3V_6
0.1u/10V_4 0.1u/10V_4
10u/6.3V_6
2
C427 33p_4
R282 *4.7K_4 3 7
+3V_S5 CLK_REQ# NC
R283 *Short_4 BCM_CLKREQ#

[10] CLK_PCIE_LAN_REQ#
GND

BCM57780
49
B B
EEPROM
LAN POWER +3V_S5
+3V_S5 VAUX_12 20mil

R278 R280
*1K_4 1K_4
C726 4.7U/6.3V_6 C723 4.7U/6.3V_6 U30
BCM_EED 5 1
C410 0.1u/10V_4 C725 0.1u/10V_4 BCM_EEC SDA A0
6 SCL A1 2
A2 3
C720 0.1u/10V_4 7
R275 R285 WP
C407 0.1u/10V_4 4 8 +3V_S5
1K_4 *1K_4 GND VCC
*24LC02 C431
*0.1u/10V_4
A A
EEPROM Strapping
EEPROM Type EECLK EEDATA
24LC02 1 1
Internal 1 0 PROJECT : ZRB
1A
GLAN BCM57780
5 4 3 2 1
1 2 3 4 5 6 7 8

TRANSFORMER
SUY DFTJ12FR109
AEC DFTJ12FR135
U27
A A
1 TCT1 MCT1 24
2 23 X-TX0P
[26] LAN_TRD0P TD1+ MX1+
3 22 X-TX0N
[26] LAN_TRD0N TD1- MX1-
C351 C357
4 21 CN9
0.1u/10V_4 0.1u/10V_4 TCT2 MCT2 X-TX1P LAN_ACTLED#
[26] LAN_TRD1P 5 TD2+ MX2+ 20 [26] LAN_ACTLED# 9 YELLOW_N
6 19 X-TX1N +3V_S5 R192 220_8 LAN_ACT_LED_PWR 10
[26] LAN_TRD1N TD2- MX2- YELLOW_P
7 18 14 R227 *0_6
TCT3 MCT3 X-TX2P X-TX0P GND2 R183 *0_6
[26] LAN_TRD2P 8 TD3+ MX3+ 17 1 0+ GND1 13
9 16 X-TX2N X-TX0N 2
[26] LAN_TRD2N TD3- MX3- 0-
C365 C374 X-TX1P 3
X-TX2P 1+
10 TCT4 MCT4 15 4 2+
0.1u/10V_4 0.1u/10V_4 11 14 X-TX3P X-TX2N 5
[26] LAN_TRD3P TD4+ MX4+ 2-
12 13 X-TX3N X-TX1N 6
[26] LAN_TRD3N TD4- MX4- 1-
X-TX3P 7
X-TX3N 3+
8 3-
TRANSFORMER
R198 R205 R210 R221 LAN_LINKLED# 11

[26] LAN_LINKLED# GREEN_N
75/F_8 75/F_8 75/F_8 75/F_8 +3V_S5 R228 220_8 LAN_LNK_LED_PWR 12
GREEN_P
Delta LFE9276D-R (DB0ZY8LAN00) RJ45
B B
C713
1500p/3KV_18
LAN_ACTLED#
LAN_LINKLED#
C339 C391
LAN_TRD0P EC2 *.1u/16V_4 *.1u/16V_4 *.1u/16V_4
LAN_TRD0N EC3 *.1u/16V_4
LAN_TRD1P EC5 *.1u/16V_4
LAN_TRD3N EC9 *.1u/16V_4 REV : B Change to 0402 for ESD
C C
D D

PROJECT : ZRB
1A
LAN Transformer and RJ45
Date: Thursday, July 22, 2010 Sheet 27 of 46
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8

MINI-CARD WLAN(MPC) REV : B Unstuff +3V
Debug +WL_VDD
+3.3V: 1000mA R566 *0_4 CL_DATA1_WLAN
+3.3Vaux:330mA [10] PCI_RST#
[10] CLK_LPC_DEBUG
R294 *0_4 CL_CLK1_WLAN H=7.0mm
LTS_AAA-PCI-046-K01
R291 *Short_8 +WL_VDD
+1.5V:500mA CN13
51 Reserved +3.3V 52 +WL_VDD
R567 *0_4 CL_RST1#_WLAN 49 50 C466 C469 C743 C444
[10] CL_RST1# Reserved GND
R565 *0_4 CL_DATA1_WLAN 47 48 +1.5V REV : B Change to short pad 10u/6.3V_8 0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4
[10] CL_DATA1 Reserved +1.5V
R295 *0_4 CL_CLK1_WLAN 45 46
[10] CL_CLK1 Reserved LED_WPAN#
43 44 RF_LED#
Reserved LED_WLAN# RF_LED# [33]
+WL_VDD 41 Reserved LED_WWAN# 42
39 Reserved GND 40
A PTI DFHS52FR028 37 Reserved USB_D+ 38 USBP13+ [10] A
35 GND USB_D- 36 USBP13- [10]
[10] PCIE_TX6+ 33 PETp0 GND 34
LTS DFHS52FR038 [10] PCIE_TX6- 31 PETn0 SMB_DATA 32
CLK_SDATA [3,14,15]
29 GND SMB_CLK 30
27 28 CLK_SCLK [3,14,15]
GND +1.5V +1.5V
[10] PCIE_RX6+ 25 PERp0 GND 26
[10] PCIE_RX6- 23 PERn0 +3.3Vaux 24 +WL_VDD
21 22 PLTRST# +1.5V
GND PERST# PLTRST# [4,10,11,26,32,36]
19 UIM_C4 W_DISABLE# 20 RF_EN [36]
17 UIM_C8 GND 18
A_LFRAME#_R R284 0_4

Debug
15 GND UIM_VPP 16 LPC_LFRAME# [9,36]
13 14 A_LAD3_R R279 0_4 C742 C727 C736
[10] CLK_PCH_SRC2 REFCLK+ UIM_RST LPC_LAD3 [9,36]
11 12 A_LAD2_R R276 0_4 *1000p/50V_4 *0.1u/10V_4 *10u/6.3V_8
[10] CLK_PCH_SRC2# REFCLK- UIM_CLK LPC_LAD2 [9,36]
9 10 A_LAD1_R R273 0_4
GND UIM_DATA LPC_LAD1 [9,36]
7 8 A_LAD0_R R272 0_4
[10] PCIE_CLK_REQ2# CLKREQ# UIM_PWR LPC_LAD0 [9,36]
5 Reserved +1.5V 6 +1.5V
3 4 REV B: Unstuff
GND
GND
PCIE_WAKE#_R Reserved GND
1 WAKE# +3.3V 2 +WL_VDD
+WL_VDD REV C: stuff for SMT debug
53
54
2
Q3
*DTC144EUA
3 1 PCIE_WAKE#_R
[8,26] PCIE_WAKE#
B B
C C
D D

PROJECT : ZRB
1A
MINI PCI-E card/TV
1 2 3 4 5 6 7 8
1 2 3 4
EE RETURN-PATH CAPACITORS
MAIN SATA HDD
REV : B Change footprint +VGPU_CORE
CN11
GND23 23
A A
1 C68 C74 C93 C135 C117 C107
GND1 SATA_TXP0_C C473 .01u/25V_4
RXP 2 SATA_TXP0 [9]
3 SATA_TXN0_C C471 .01u/25V_4 SATA_TXN0 [9] EV@.1u/10V_4 EV@.1u/10V_4 EV@.1u/10V_4 EV@.1u/10V_4 EV@.1u/10V_4 EV@.1u/10V_4
RXN
GND2 4
5 SATA_RXN0 C463 .01u/25V_4
TXN SATA_RXN0_C [9]
6 SATA_RXP0 C461 .01u/25V_4
TXP SATA_RXP0_C [9]
GND3 7
3.3V 8
3.3V 9
10 REV : B Change to short pad
3.3V
GND 11
12 +5V
GND
GND 13 VIN
14 +5V_HDD R544 *Short_8
5V
5V 15
16 C399 C403 C406 C409 C393 C719 4.7u/25V_8 0.1u/25V_4
5V +
GND 17
18 .01u/25V_4 .01u/25V_4 *.1u/16V_4 *.1u/16V_4 10u/6.3V_6 *100u/6.3V_3528 C245 C237
RSVD
GND 19
B B
12V 20
12V 21
12V 22 REV: B change P/N for EOD
GND24 24
SATA-HDD(C166S4-12205-L)
ODD (SATA)
CN7 SUY DFHS22FR214

GND14 14
C C
GND 1 AOP DFHS22FR232

2 SATA_TXP1_C C302 .01u/25V_4 SATA_TXP1 [9]
A+ SATA_TXN1_C C300 .01u/25V_4
A- 3 SATA_TXN1 [9]
GND 4 AEC DFHS22FR216
5 SATA_RXN1 C293 .01u/25V_4
B- SATA_RXN1_C [9]
6 SATA_RXP1 C292 .01u/25V_4
B+ SATA_RXP1_C [9]
GND 7 REV : B Change to short pad
+5V
8 SATA_DP R114 *1K_4
DP +5V_ODD R436 *Short_8
5V 9
5V 10
C267 C256 C255 C268 C254 C626
+
MD 11
GND 12
13 .01u/25V_4 .01u/25V_4 *.1u/16V_4 *.1u/16V_4 10u/6.3V_6 *100u/6.3V_3528
GND
GND15 15
SATA_ODD_H=7.7
REV: B change P/N for EOD
D D
AOP DFHS13FR011
OTK DFHS13FR010 PROJECT : ZRB
1A
SATA-HDD/ODD/RETURN-PATH
1 2 3 4
5 4 3 2 1
Codec(ADO) Maintenance and Service Guide,Service Manual,Motherboard Schematics for

HP [31] HP-R
Laptop/notebook http://mycomp.su/x/
MUTE(AMP)
[31] HP-L
R301 5.1K/F_4 SENSEB

[31] HPOUT_JD
REV : B Change AMP circuit

MIC1-VREFO [31]
FRONT-L= (L+R)/2 ADOGND
D Place next to pin 27 D
Speaker FRONT-R C482 *0.47u/10V_6

U13
C490 C489 C485 C488 MONO-OUT C483 0.47u/10V_6 ADOGND C486 4.7U/6.3V_6 2 8
ADOGND Bypass VO2 INSPKR+ [31] +5VA
FRONT-L + +
0.1u/10V_4 10u/6.3V_6 +5VA FRONT-L C491 *0.47u/10V_6 FRONT-R-1 R303 22K/F_6 FRONT-R-2 4 7
IN- GND ADOGND
FRONT-R 2.2u/6.3V_6 2.2u/6.3V_6
Place next to pin 25 ADOGND C494 0.47u/10V_6 FRONT-R+1 R307 22K/F_6 FRONT-R+2 3 6
IN+ VDD
Change to 0.47U to reduce popping noise 1 5 C500 C481
SHUTDOWN VO1 INSPKR- [31]
C484 C487 REV:B Change P/N C501
36
35
34
33
32
31
30
29
28
27
26
25
U12 G1442P81U 0.1u/10V_4 0.1u/10V_4 4.7U/6.3V_6
5/10 Add
FRONT-R
MIC1-VREFO
Sense B
HPOUT-R
CPVEE
CBN
CBP
FRONT-L
HPOUT-L
VREF
AVSS1
AVDD1
0.1u/10V_4 10u/6.3V_6 +3V R308 *100K_4
R302 *0_4 ADOGND

MONO-OUT 37 24
MONO-OUT LINE1-R T30 +3V_S5 +5V_S5
ADOGND
+5VA 38 AVDD2 LINE1-L 23 T29
R140 *0_6 R116 *Short_6 REV : B Change to short pad
39 22 MIC1-R
SURR-L MIC1-R MIC1-R [31] U33
5
1
C479 C477
10u/6.3V_6 0.1u/10V_4
ADOGND R297 20K/F_4 40 JDREF MIC1-L 21 MIC1-L
MIC1-L [31]
MIC [36] AMP_MUTE#
EAPD#
4 R311 *Short_4
HP_MUTE# [31]
2 TC7SH08FU
41 20 C496
3
SURR-R LINE2-VREFO
42 19 MIC2-VREFO R304 *0_4 *4.7u/10V_6
ADOGND
Place next to pin 38
ADOGND AVSS2
ALC272X<LQFP-48> MIC2-VREFO
ANALOG 43 NC LINE1-VREFO 18
T28 44 17 MIC2_INT_R C474 1u/10V_6 MIC2_INTL1_R R296 1K_4 MIC2_INTL1

DMIC-CLK3/4 MIC2-R
C DIGITAL C
45 16 MIC2_INT_L C472 1u/10V_6
SPDIFO2 MIC2-L
46 DMIC-CLK1/2 LINE2-R 15
Split by DGND 47 14
DMIC-1/2/GPIO0
DMIC-3/4/GPIO1
EAPD LINE2-L
SENSEA R293 20K/F_4 MIC1_JD
SDATA-OUT
48 SPDIFO1 Sense A 13 MIC1_JD [31]
EAPD#
SDATA-IN
DVDD-IO
PCBEEP
RESET#
BIT-CLK
DVDD1
DVSS1
DVSS2
SYNC
Split by DGND
ANALOG
1
10
11
12
DIGITAL
1.6Vrms
+3V
PCBEEP C460 1u/10V_6 BEEP_1 R289 47K/F_4
SPKR [9]
C458 C457 C439 R288
4.7K_4
10u/6.3V_6 0.1u/10V_4 100p/50V_4
Place next to pin 1

+3V
C443 C453
PCH_AZ_CODEC_RST# [9]
B 0.1u/10V_4 10u/6.3V_6 B
C440
PCH_AZ_CODEC_SYNC [9]
C441 *22p/50V_4 *100p/50V_4
ACZ_SDIN0_R R557 22_4 Place next to pin 9

PCH_AZ_CODEC_SDIN0 [9]
PCH_AZ_CODEC_SDOUT [9]
PCH_AZ_CODEC_BITCLK [9]
C456 22p/50V_4
REV : B C478 Change to short pad and

Stuff R563 ,R570 ,R569 ,R584 ,R299 ,C738
Power (ADO) INT MIC array
DIGITAL ANALOG Place in Bottom of codec
+5V L56 UPB201209T-310Y-N/6A/31ohm_8 CN4 R320
+5VA R563 *Short_4 1 MIC2_INTL1 MIC2-VREFO
U34 1
2 2
3 4 C502 2.2K_4
IN OUT R570 *Short_4
2 R569 *Short_4 *INT_MIC *22P_4
GND R584 *Short_4
A A
1 5 R581 *29.4K/F_4 R299 *Short_4
SHDN SET C475 *1000p/50V_4
*G923-330T1UF C738 *Short_4
R574 + C755 C759 ADOGND
*10K/F_4
*10u/10V_3216 *0.1u/10V_4
C753 C754 ADOGND
+ R319 *0_4 C478 *0.1u/10V_4 REV : B C478 Unstuff
*0.1u/10V_4 *10u/10V_3216
Tied at one point only under Quanta Computer Inc.
the codec or near the codec
ADOGND ADOGND PROJECT : ZRB
ADOGND cap place close to MIC-connector 1A
C730, C787 close U37 pin3 and L65 REALTEK ALC663&888/MDC
5 4 3 2 1
5 4 3 2 1

MIC D9 BAS316
D10 BAS316
[30] MIC1-VREFO
Internal Speaker
Normal OPEN Jack
R313 R312
4.7K/F_4 4.7K/F_4
CN18 BLACK
1 7 REV : B Change to short pad CN16
D C493 4.7u/6.3V_6 MIC1_L2 R306 1K/F_4 MIC1_L3 L33 MIC1_L D
[30] MIC1-L 2
BLM15AG121SS1/0.5A/120ohm_4 6 [30] INSPKR- R585 *Short_6 R_SPK-_1 2
C492 4.7u/6.3V_6 MIC1_R2 R305 1K/F_4 MIC1_R3 L32 MIC1_R R583 *Short_6 R_SPK+_1 2
[30] MIC1-R 3 [30] INSPKR+ 1 1
BLM15AG121SS1/0.5A/120ohm_4 MIC1_JD 4
[30] MIC1_JD 8 INT_Speaker
5
MIC
C497 C495 C764 C765
Max. 100mVrms input for Mic-IN 470p/50V_4 470p/50V_4 *0.22u/25V_6 *0.22u/25V_6
MIC1_JD ADOGND
1
ADOGND
D21
ACS DFHD02MR311
*VPORT_6
2 FOX DFTJ08FR130 PTI DFHD02MR508
SIT DFTJ08FR128
ADOGND
C C
BLACK
1 CN17 7
HP/SPDIF HP-L-2 R316
HP-R-2 R315
56/F_4
56/F_4
HPL-1
HPR-1
L35
L34
BLM15AG121SS1/0.5A/120ohm_4
BLM15AG121SS1/0.5A/120ohm_4
HPL_SYS
HPR_SYS
2
6
[30] HP_MUTE# REV :B Change P/N for EOD 3
4
R314 R317 C498 C499 [30] HPOUT_JD 8
5
*1K_4 *1K_4 2200p/50V_4 2200p/50V_4 JA6331-0230T3B-8H
2
ADOGND
[30] HP-L 3 1 HP-L-2
ADOGND
Q22
FDV301N
R310 *0_6
De-pop noise REV : B Add
REV :B Change P/N for EOD
HP_MUTE# +3V
B B
2
[30] HP-R 3 1 HP-R-2
1
Q23 R579 HPL-1
FDV301N *220K_4
*MMBT3906
R576
R309 *0_6 HPR-1
[30] HP_MUTE# 2
Q28
*10K/F_4
R589 R587
3
3
HPOUT_JD 2 Q26
*MMBT3904
1
*1K/F_4 *1K/F_4
1
D11
R588
3
*VPORT_6 2 Q27
2
*MMBT3904
C768
1
*1K/F_4
A ADOGND *10u/10V_6 A

ADOGND PROJECT : ZRB
ADOGND Size Document Number Rev
1A
AMP /AUDIO JACK CONN
5 4 3 2 1
A B C D E

CARD READER Controller 2 IN 1 CARD READER (SD/MMC) SD_WP
SD_CD#
11
12
4
CN3
Close to connector
CD/SW
WP/SW
SW COM
SD_DAT1 10
SD_DAT0 DATA1
9 DATA0
8 VSS2
4 CTRL0 R292 BLM15AG121SS1/0.5A/120ohm_4 SD_CLK 4
7 CLK
VCC_XD 6 VDD
5 VSS1
C468 SD_CMD 3 CMD
GND1
*10p/50V_4 SD_DAT3 2
GND
SD_DAT2 DATA3
1 DATA2
SD-CARD
13
14
VCC_XD
C465 C470
Clock input selection 4.7u/10V_6 0.1u/16V_4

'1' for 48MHz input [Default,Internal PU]
'0' for 12MHz input
C743 close PIN46, 47
+1.8V_VDD Close to CN14 pin 14 & pin23
PNT DFHS11FR011
C708 close PIN48, 47 4.7u CAP close to pin23
+3V_VDD T88
R571 *Short_4 XTALSEL C748 C750 T86 PLA DFHS11FR033
REV : B Change to short pad 0.1u/16V_4 0.1u/16V_4
SD_DAT1
SD_DAT0
3 3
XTALSEL
CRMD_N
SD_CD#
SD_WP
NBMD
5/10 Modify
R578 100K_4 +3V_VDD
48
47
46
45
44
43
42
41
40
39
38
37
R582 *0_4 U32
[4,10,11,26,28,36] PLTRST#
CTRL0, CRTL 1 trace length shorter ,
TRIST
GND
VDD
NBMD
VDDHM
XTALSEL
CTRL1
CTRL3
DATA1
DATA0
DATA7
DATA6
C758 10u/6.3V_6 and surround with GND.
+3V R575 *Short_6 +3V_VDD
C760 1 36 CTRL0
GPON7 CTRL0
2 EXT48IN DATA5 35
REV : B Change to 4.7u/10V_6 3 34 SD_CMD
R580 330_4 RSTN CTRL2 GPI4
short pad 4 REXT GPI4 33
5 32 T85
VD33P DATA4 SD_DAT3
[10] USBP12+ 6 DP DATA3 31
7 AU6437-GBL 30 SD_DAT2
[10] USBP12- DM DATA2
8 VS33P XDWPN 29
C756 C757 XI 9 28 GPI2
XO XI GPI2 T82
10 XO XDCEN 27
*5p/50V_4 *5p/50V_4 +1.8V_VDD 11 26 EEPDATA
VDD EEPDATA GPI1 T83
12 VDD GPI1 25
8/14 C707 close PIN11, 12 T84
SDWPEN
AGND5V
EEPCLK
CF_V33
VDDHM
XDCDN
VCC33
CTRL4
GND
VDD
V18
V33
2 2
13
14
15
16
17
18
19
20
21
22
23
24
crystal trace width needs at least 10 mils. 8/14 pin13 output 20mils
EEPCLK T87
VCC_XD
C752
C761 18p/50V_4 XI
4.7u/10V_6
Y7 R577
12MHz 270K_4
*0_4 R568
VCC_XD
C762 18p/50V_4 XO
SD write protect
+1.8V_VDD 1:decided by SDWP[Default]
0:letting SD always
+3V_VDD +3V_VDD write-able
C745 C747
4.7u/10V_6 0.1u/16V_4
1 1
PROJECT : ZQ5
1A
AU6433 CardReader
A B C D E
5 4 3 2 1
LED
+3V_S5
D D
POWER Amber
+3V
LED2
R329 300/F_4 4 2
[36] SUSLED#
R330 100/F_4 3 1
[36] PWRLED#
Power LED LED1 Bule R1 100/F_4
LED_A/B
Blue
R327 *1M_4 +3VPCU
R323 *1M_4
+3VPCU
Battery Amber
LED3
R326 300/F_4 4 2
[36] BATLED1#
R322 100/F_4 3 1
C [36] BATLED0# C
LED_A/B
Blue
+3V
+3V
HDD WIFI LED
+3V
Amber
R324
LED5
5
10K/F_4 1
4 SATA_LED#_R LED4 Bule R328 100/F_4 R325 220/F_4
[28] RF_LED#
[9] SATA_ACT# 2
U14
3
*TC7SH08FU LED_AMBER
B R321 *Short_4 B
A A

PROJECT : ZRB
1A
POWER/MMB/LAUNCH/LED
Date: Monday, July 26, 2010 Sheet 33 of 46
5 4 3 2 1
5 4 3 2 1

USB +5V_S5
C462
1U/6.3V_4
U11
USBPWR1
BLUETOOTH CONNECTOR
2 IN1 OUT3 8
3 IN2 OUT2 7
6 C476
OUT1 + C741
[36] USBON# 4 EN# +3V_S5 1 3
D 1000p/50V_4 D
1 GND
5 330u/6.3V_6X5.7 Q24
OC# + C749 C751
2
G547F2P81U R572 4.7K_4 AO3413 2.2u/6.3V_6 1000p/50V_4
[36] BT_POWERON#
C746 *1000p_4
[10] USB_OC0#
R298 *0_4
CN14 CN15
L31 1 8 BT_POWER
USBP1-_R 1 8 5
[10] USBP1- 2 2 1 1 2 2 7 7 4
3 4 USBP1+_R 3 6
[10] USBP1+ 3 4 3 6 [10] USBP4+ 3
4 4 5 5 ACS DFWF05MR027 [10] USBP4- 2 7
DLW21HN900SQ2L/300mA/90ohm BT_LED
T89 1 6
R300 *0_4 USB_MB_Turbo
SCY DFWF05MR012 REV : B Change to short BT_CONN
& Del L55
C763
1
*.01u/16V_4
FOX DFHS04FR201 RV2 RV1
*EGA-0402 *EGA-0402
2
SUY DFHD04MR096
C C
USB/B +5V_S5
USB_DB FFC CONN

C739
16
*1u/6.3V_4 15
14
13
12
[10] USB_OC4_5# 11
10
9
[10] USBP11- 8
[10] USBP11+ 7
B B
6
5
[10] USBP9- 4
[10] USBP9+ 3
USBON# 2 17
1 18
CN12
A A

PROJECT : ZRC
1A
USB/ BT
5 4 3 2 1
5 4 3 2 1
Maintenance and Service Guide,Service Manual,Motherboard Schematics for Laptop/notebook http://mycomp.su/x/+3V

K/B
PTI DFFC26FR155
MY0
CN1 CPU FAN
[36] MY0 1
7 8 MX3 MY1 2 R369
[36] MY1
5 6 MX2 ACS DFFC26FR014 MY2 3
[36] MY2 +5V
3 4 MX4 MY3 4 10K_4
[36] MY3
1 2 MX5 MY4 5
[36] MY4
CP1 *100p/50Vx4 MY5 6
[36] MY5
7 8 MX6 MY6 7
[36] MY6
2
5 6 MX7 MY7 8 C567
D [36] MY7 [36] FANSIG D
3 4 MY17 MY8 9 2.2U_6
[36] MY8
1 2 MY16 MY9 10 U20 CN6
[36] MY9
1
CP2 *100p/50Vx4 MY10 11 2 3 TH_FAN_POWER 1
[36] MY10 VIN VO
7 8 MY3 MY11 12 5 2
[36] MY11 GND
5 6 MY2 MY12 13 1 6 3
[36] MY12 [10,11,36] SML1ALERT# /FON GND
2
3 4 MY1 MY13 14 7 C562 C563 C553
[36] MY13 GND
1 2 MY0 MY14 15 4 8 FAN_CONN
[36] MY14 [36] CPUFAN# VSET GND
CP6 *100p/50Vx4 MY15 16 2.2U_6 .01U_4 *.01U_4
[36] MY15
1
7 8 MY7 MY16 17 G995
[36] MY16
5 6 MY6 MY17 18
[36] MY17
MY5 MX7 ACS DFWF03MS091
3
1
4
2 MY4
[36] MX7
MX6
19
20
FANPWR = 1.6*VSET
[36] MX6
CP5 *100p/50Vx4 MX5 21
[36] MX5
7 8 MY11 MX4 22 SCY DFWF03MS000
[36] MX4
5 6 MY10 MX3 23
[36] MX3
3 4 MY9 MX2 24 27
[36] MX2
1 2 MY8 MX1 25 28
[36] MX1
CP4 *100p/50Vx4 MX0 26
[36] MX0
7 8 MY15
5 6 MY14 KB
3 4 MY13 +3VPCU
1 2 MY12
CP3 *100p/50Vx4
C
C541 *100p/50V_4
C542 *100p/50V_4
MX1
MX0
RP3 10K_10P8R TOUCHPAD & Switch CONN. ACS DFFC12FR017 C
10 1 MX3
MX4 9 2 MX2
MX5 8 3 MX1 SCY DFFC12FR015
MX6 7 4 MX0 +5V
MX7 6 5 +5V
PTI DFFC12FR234
L5 *Short_6 +TPVDD
C150
HOLE4 HOLE10 HOLE24 HOLE5 HOLE7 HOLE31 HOLE26 HOLE30
H-C315i154D154P2 H-TC197BC122D122P2 *h-c315in158d118p2
*h-c315d118p2 *h-c315d118p2 *h-c315d118p2 *h-c315d118p2 *h-c315d118p2 R44 R45 REV : B Change to 0.1u/10V_4
10K_4 10K_4 short pad
CN2
1
L6 *Short_6 2
[36] TPDATA
TPDATA_R 3
1
1
L7 *Short_6 TPCLK_R 4
[36] TPCLK
5
C143 C144 6
HOLE11 HOLE17 HOLE13 HOLE32 HOLE3 HOLE16 HOLE29 HOLE22 RIGHT# 7
H-TC197BC122D122P2 H-TC197BC122D122P2 *h-c315d118p2 *h-c315d118p2 *h-c315d118p2 *h-c315d118p2 *h-c315d118p2 *h-c315d118p2 *.01u/25V_4 8
*.01u/25V_4 9
10 13
B 11 14 B
LEFT# 12
1
1
Aces 88501-120N
HOLE18 HOLE25 HOLE14 HOLE21 HOLE20

h-c315d146p2 H-TC315BC146D146P2 *H-TC165BC256D165P2 *H-TC165BC256D165P2 *H-TC165BC256D165P2
SW3 SW2
RIGHT# 3 2 LEFT# 3 2
1 4 1 4
SWITCH_1.5 SWITCH_1.5
1
HOLE27 HOLE9
h-c197d87p2 HOLE1 HOLE2 *h-o315x354d315x354n
h-tc197bc79d79p2 h-tc197bc102d102p2
+1.05V +1.05V
1
1
1
A A
HOLE12 HOLE6 HOLE8
HOLE19 HOLE15 HOLE23 HOLE28 *h-c315d118p2 *h-c94d94n *h-c1417d1417na1457
1
*H-TC91BC197D91P2 *H-TC91BC197D91P2 *H-TC91BC197D91P2 *H-TC91BC197D91P2

*SPAD1 *SPAD3
PAD1 PAD3 PROJECT : ZRB
1
1
1
1A
KB/FAN/TP+FP
5 4 3 2 1
5 4 3 2 1
EC(KBC) L3
PBY160808T-250Y-N/3A/25ohm_6 I/O ADDRESS SETTING(KBC)
+A3VPCU
+3V
C28 C27 REV: B change
30mil P/N for EOD
0.1u/10V_4 10u/6.3V_6
+3VPCU E775AGND
R28 2.2_6 D14 C514 C518
1 2 +3VPCU_EC 0.03A(30mils)
BAS316 4.7U/6.3V_6 0.1u/10V_4
C23 C504 C529 C507 C32 C15
115
102
19
46
76
88
4
4.7U/6.3V_6 0.1u/10V_4 *.1u/16V_4 0.1u/10V_4 *.1u/16V_4 0.1u/10V_4 U15
VCC1
VCC2
VCC3
VCC4
VCC5
AVCC
VDD
E775AGND C533 10u/6.3V_8 ICMNT SHBM=0: Enable shared memory with host BIOS
D D
C527 0.01u/16V_4
[9,28] LPC_LFRAME# 3 LFRAME GPIO90/AD0 97 TEMP_MBAT [37]
126 98 WL_SW T45
[9,28] LPC_LAD0 LAD0 GPIO91/AD1
127 99 SHBM SHBM_R R336 *10K_4
[9,28] LPC_LAD1 LAD1 GPIO92/AD2 SML1ALERT# [10,11,35]
[9,28] LPC_LAD2 128 LAD2 A/D GPIO93/AD3 100 ICMNT [37]
[9,28] LPC_LAD3 1 LAD3 GPIO05 108
CLK_PCI_775 CLK_PCI_775 2 96 1/13 Comfirm by vendor mail :
[10] CLK_PCI_775 LCLK GPIO04 VGA_THERM# [21]
Disabled ('1') if using FWH device on LPC.
[8] CLKRUN# 8 GPIO11/CLKRUN
101 Enabled ('0') if using SPI flash for both system BIOS and EC firmware
GPIO94/DA0 T49
R343 121 105 T50
[11] SIO_A20GATE GPIO85/GA20 GPI95/DA1
*22_4
D/A GPI96/DA2 106 CPUFAN# [35]
[11] SIO_RCIN# 122 KBRST/GPIO86 GPI97 107
[11] SIO_EXT_SCI#
D13 BAS316 29 ECSCI/GPIO54 LPC SM BUS PU(KBC) +3VPCU
GPIO01/TB2 64 ACIN [37]
C521 EC_FPBACK# 6 95 NBSWON#
[24] EC_FPBACK# GPIO24/LDRQ GPIO03
*10p/50V_4 93 MBCLK R19 10K_4
GPIO06/IOX_DOUT LID591# [24]
T44 NOCIR# 124 94 MBDATA R18 10K_4
GPIO10/LPCPD GPIO07 SUSB# [8]
GPIO23/SCL3 119 MXM_SMCLK12 [21]
PLTRST# 7 109 +3V_D_S
[4,10,11,26,28,32] PLTRST# LREST GPIO30/CIRTX2 T46
GPIO31/SDA3 120 MXM_SMDATA12 [21]
USBON# 123 65 MXM_SMCLK12 R350 EV@2.2K_4
[34] USBON# GPIO67/PWUREQ GPIO32/D_PWM BATLED0# [33]
66 MXM_SMDATA12 R351 EV@2.2K_4
GPIO33/H_PWM BATLED1# [33]
IRQ_SERIRQ 125 15
[9] IRQ_SERIRQ SERIRQ GPIO36 VRON [39]
GPIO40/F_PWM 16 SUSLED# [33]
9 17 AC_OFF T43 +3V
[11] SIO_EXT_SMI# GPIO65/SMI GPIO42/TCK
GPIO GPIO43/TMS 20
3G_SW
AMP_MUTE# [30]
2ND_MBCLK R16 10K_4
GPIO44/TDI 21 T39
MX0 54 22 T38 2ND_MBDATA R17 10K_4
[35] MX0 KBSIN0 GPIO45/E_PWM
MX1 55 23 T37
[35] MX1 KBSIN1 GPIO46/CIRRXM/TRST
MX2 56 24 T36 VGA_THERM# R342 EV@10K_4
[35] MX2 KBSIN2 GPO47/SCL4
MX3 57 25
C [35] MX3 KBSIN3 GPIO50/TDO D/C# [37] C
MX4 58 26
[35] MX4 KBSIN4 GPIO51 S5_ON [38,45]
MX5 59 27 T1
[35] MX5 KBSIN5 GPIO52/CIRTX2/RDY
MX6 60 28 T35
[35] MX6 KBSIN6 GPIO53/SDA4
MX7 61 91
[35] MX7 KBSIN7 GPIO81 DNBSWON# [8]
GPO82/TEST 110
MY0 53 112
[35] MY0 KBSOUT0/JENK GPO84/TRIST
MY1 52 80 T2
[35] MY1 KBSOUT1/TCK GPIO41
MY2 51
[35] MY2 KBSOUT2/TMS
MY3 50
[35] MY3 KBSOUT3/TDI
MY4 49 KB 31 ODDLED T33
[35] MY4 KBSOUT4/JEN0 GPIO56/TA1
MY5 48 117
[35] MY5 KBSOUT5/TDO GPIO20/TA2/IOX_DIN SUSON [41]
MY6 47 63
[35] MY6 KBSOUT6/RDY GPIO14/TB1 FANSIG [35]
MY7 43
[35] MY7 KBSOUT7
MY8 42 TIMER 32
[35] MY8 KBSOUT8 GPIO15/A_PWM CONTRAST [24]
MY9 41 118 T48
[35] MY9 KBSOUT9/SDP_VIS GPIO21/B_PWM
MY10 40 62
[35] MY10 KBSOUT10/P80_CLK GPIO13/C_PWM PWRLED# [33]
MY11 39 81 T3
[35] MY11 KBSOUT11/P80_DAT GPIO66/G_PWM
MY12 38
[35] MY12 KBSOUT12/GPIO64
MY13 37
[35]
[35]
MY13
MY14
MY14
MY15
36
KBSOUT13/GPIO63
KBSOUT14/GPIO62 GPIO77/SPI_DI 84
SHBM_R
T40 SPI FLASH(KBC) +3VPCU
[35] MY15
MY16
35 KBSOUT15/GPIO61/XOR_OUT SPI GPO76/SPI_DO/SHBM 83
U16
[35] MY16 34 GPIO60/KBSOUT16 GPIO75/SPI_SCK 82
MY17 33 SPI_SDI_uR R25 22_4 SPI_SDI_uR_R 2 8
[35] MY17 GPIO57/KBSOUT17 SO VDD
75 RSMRST#_uR R332 *Short_4 R21 100K_4 SPI_SDO_uR 5 7 C522
GPIO72/IRRX1/SIN2 ICH_RSMRST# [8] SI HOLD
MBCLK 70 73
[37] MBCLK GPIO17/SCL1 GPIO70/IRRX2_IRSL0 SUSC# [8]
MBDATA 69 74 PWROK_EC_uR R331 *Short_4 7/24 modify SPI_SCK_uR 6 3 0.1u/10V_4
[37] MBDATA GPIO22/SDA1 GPIO71/IRTX/SOUT2 PWROK_EC [8] SCK WP
[10] 2ND_MBCLK 2ND_MBCLK 67 SMB IR 113
GPIO73/SCL2 GPIO87/CIRRXM/SIN_CR RF_EN [28]
[10] 2ND_MBDATA 2ND_MBDATA 68 14 T42 +3VPCU R26 10K_4 SPI_CS0#_uR 1 4
GPIO74/SDA2 GPIO34/CIRRXL HWPG CE VSS
GPIO16/CIRTX 114
111 P_SAVE_LED# T47 REV : B Change to short pad W25X40BVSSIG
TPCLK GPO83/SOUT_CR/XORTR
[35] TPCLK 72 GPIO37/PSCLK1
TPDATA 71 1/13 Comfirm by vendor mail :
[35] TPDATA GPIO35/PSDAT1
PCH_ACIN 10 86 SPI_SDI_uR
B [8] PCH_ACIN GPIO26/PSCLK2 F_SDI If the Southbridge enables 'Long Wait Abort' by B
11 PS/2 87 SPI_SDO_uR_R R337 22_4 SPI_SDO_uR
[34] BT_POWERON# GPIO27PSDAT2 F_SDO default, the flash device should be 50MHz (or faster)
12 FIU 90 SPI_CS0#_uR
[19,40,41,44] MAINON GPIO25/PSCLK3 F_CS0
T41 MAINOND 13 92 SPI_SCK_uR_R R338 22_4 SPI_SCK_uR
GPIO12/PSDAT3 F_SCK
[8] ICH_SUSCLK R333 *Short_4 E775_32KX1 77 30 ECDB_CLOCK T34
GPIO00/32KCLKIN GPIO55/CLKOUT/IOX_DIN
VCC_POR 85 VCC_POR# R20 47K/F_4 +3VPCU HWPG(KBC)

REV : B Change to +3V
VCORF
AGND
GND1
GND2
GND3
GND4
GND5
GND6
short pad R334 *20M_6 E775_32KX2 79 104 VREF_uR R352 *Short_4 +A3VPCU REV : B Change to
GPIO02 VREF
short pad
R335 NPCE781 R348
5
18
45
78
89
116
103
VCORF_uR 44
10K_4
Y3 *33K/F_4 SM BUS ARRANGEMENT TABLE
1 4 D7 BAS316 HWPG
[44] HWPG_1.8V
SM Bus 1 Battery
L2 PBY160808T-250Y-N/3A/25ohm_6 D5 BAS316
[40] HWPG_1.05V
C506 *32.768KHz C508 C505 SM Bus 2 PCH D6 BAS316 R349
[41] HWPG_1.5V
*15p/50V_4 *15p/50V_4 *Short_4
1u/6.3V_4 D4 BAS316
[38] SYS_HWPG
E775AGND E775AGND SM Bus 3 GPU-I2C MPWROK [4]
D3 IV@BAS316
[42] HWPG_GFX
SM Bus 4 N/A
POWER-ON Switch(KBC) INTERNAL KEYBOARD STRIP SET(KBC)

SW1
A A
SWITCH_1.5 +3VPCU
NBSWON# D2 BAS316 1 2 MY0 R362 10K_4

3 4
2
5
D1 6
*VPORT_6

1
PROJECT : ZRB
5/13 change the location 1A
WPCE781 & FLASH
5 4 3 2 1
5 4 3 2 1
SP@POWER_JACK
Maintenance and Service Guide,Service Manual,Motherboard Schematics for Laptop/notebook
0.01_3720
http://mycomp.su/x/
dcjk-2dc2003-000111-3p-v VA1 PD5 PR151
PJ1 PL2 SBR1045SP5-13 PQ17 VIN PQ20
HI0805R800R-00_8 FDD6685 FDD6685
1
2 VA
1
3 VA2
200mil 3 4 1 2
300mil 3 4
2
3 5/14 add short PAD
1
PC91 PC1 PR3 PR150 PC99 PC98 PR155
7
6
5
4
PL1 0.1u/50V_6 0.1u/50V_6 220K_4 SHORT_PAD_4 0.1u/50V_6 2200p/50V_6 33K/F_4

HI0805R800R-00_8 PD6 PR152
SMAJ20A SHORT_PAD_4 CSIN_1
2
D D
PC88 PC89 PC90 CSIP_1
0.1u/50V_6 2200p/50V_6*47u/25V_6.3*6 1 6
PD1 PR1 *Short_4 PR154
5/12 EMI RESERVE SW1010CPT PR2 2 5 10K_4
5/14 add short PAD D/C# [36]
220K_4
3 4
3
PQ1
IMD2AT108
CSIN_1 2
PQ21
CSIP_1 DMN601K-7
1
VIN
PC4
PR5 PR6 1u/16V_6
10/F_4 10/F_4
PC7
0.1u/50V_6 PR14 PC8
4.7_6 PC9 4.7u/25V_8
1u/16V_6
27 CSIN
28 CSIP
ISL88731_VDDP
5
6
7
8
PC96
33
32
31
30
26
21
C C
1
+3VPCU PD7 PC95 *0.1u/50V_6
*RB500V-40 4 2200p/50V_6
NC
GND
GND
GND
GND
CSSP
VDDP
CSSN
VCC
PC15 PR7 PC3
0.1u/50V_6 2.7_6 0.1u/50V_8
+3VPCU 11 25 88731B_2 88731B_1 PQ18 0.01_3720
VDDSMB BOOT AO4468 PR156
PL3
3
2
1
MBDATA ISL88731_UGATE 6.8uH
PR22
9 SDA UGATE 24
1 2
140mil BAT-V
100K_4
5
6
7
8
MBCLK 10 23 ISL88731_PHASE
SCL PHASE
13 20 ISL88731_LGATE 4 PR153
[36] ACIN ACOK LGATE *4.7_6
PR4 PC2 19
49.9/F_6 0.1u/50V_6 PGND PQ19
DCIN 22 AO4468 CSOP_1
DCIN PR19 PC97 PC101 PC100
3
2
1
PR13 10/F_4 PC93 BAT-V 2200p/50V_6 10u/25V_1206 10u/25V_1206
82.5K/F_4 PU2 18 CSOP CSOP_1 *680p/50V_6
PC92 88731ACSET ISL88731A CSOP
2 ACIN
0.1u/50V_6 PC11
2 1 0.1u/50V_6
3 VREF
B
PC94 PR15 17 CSON BAT-V B
100p/50V_6 PL4 22K/F_4 CSON
HI0805R800R-00_8 4 PR158 *Short_4 PR20
ICOMP 10/F_4
NC 16
MBAT+ BAT-V
C114F3-108A1-L_Batt_Conn 5
PL5 NC
HI0805R800R-00_8 15 BAT-V
10 1 PR9 VBF
2 6 VCOMP
100_4 29 PR157
3 TEMP_MBAT GND 100_4
GND
4 TEMP_MBAT [36]
ICM
NC
NC
5
6 PR12 PR21
7
14
12
7 100K_4 2.21K/F_4
9 8
+3VPCU
PJ2
PC5 PC6
47p/50V_6 47p/50V_6 PC14
0.01u/50V_6
ISL88731 thermal pad
ICMNT
tie to Pin12
ICMNT [36]
PR8
*Short_4 PR11 PR10
100_4 100_4 PC10 PC12 PC13
*1u/16V_6 0.01u/50V_6 *0.01u/50V_6
MBCLK [36]
A MBDATA [36] A
PU1
CM1293A-04SO
1 6 MBDATA
CH1 CH4
2 VN VP 5 +3VPCU Quanta Computer Inc.
TEMP_MBAT MBCLK
3 CH2 CH3 4 PROJECT : ZRB
Add ESD diode base on EC FAE suggestion 1A
Charger(ISL88731A)
5 4 3 2 1
5 4 3 2 1

MAIND
MAIND [41,44]
PR74 *Short_4 VL
[4,45] SYS_SHDN#
1
D VIN VIN D
PR75
39K/F_4 VL
2
PC63
2
+ 3V5V_EN 4.7u/10V_8
PC156 PC158
PC166 PR220 *Short_4 2.2n/50V_4 4.7u/25V_8
1
100u/25V_6X5.7 PR81 PR109 PR100
*Short_4 *Short_4 *Short_4
1
PC66 PR219
PC149 PC49 PC53 PR94 PC57 1u/16V_6 *0_4
5V_EN
3V_EN
*4.7u/25V_8 4.7u/25V_8 2.2n/50V_6 390K_4 0.1u/50V_6
5
6
7
8
PC59
2
0.01u/16V_4 PC68 280mil
0.1u/50V_6
1
8206_ONLDO REF 4 OCP:9A
3V_DH
8
7
6
5
PR218 PQ52
7A
200mil PR96 *0_6 AO4468
8
7
6
5
4
3
2
1
5V_DH 150K_4 +3VPCU
OCP:6.5A 4
PL13
LDOREFIN
LDO
ONLDO
VIN
NC
VCC
TON
REF
3
2
1
2.2uH
5A PQ46
AO4468 PR115 3V_LX
5
6
7
8
+5VPCU +5VPCU 9 32 REFIN2 220K/F_4
PL10 BYP REFIN2
10 31 1 2
1
2
3
2.2uH OUT1 ILIM2 PR228
C 11 FB1 OUT2 30 C
5V_LX 1 2 12 PU5 29 SKIP 4 *4.7_6
ILIM1 SKIP#
2
PR83 DDPWRGD_R 13 RT8206B 28 DDPWRGD_R
PGOOD1 PGOOD2
8
7
6
5
147K/F_4 5V_EN 14 27 3V_EN PR120 +
PR84 EN1 EN2
15 DH1 DH2 26 *0_4
*0_4 PR209 16 25 PC163 PC171 PC174
*4.7_6 5V_DL LX1 LX2 *680p/50V_6 0.1u/50V_6 330u/6.3V_6X5.7
4 37
1
+ PAD
36
3
2
1
PAD
PGND
PVCC
PC137 PQ51
BST1
BST2
GND
PAD
PAD
PAD
DL1
DL2
PC43 330u/6.3V_6X5.7 PC51 PC71 AO4710 PR113 *Short_4
NC
0.1u/50V_6 PC145 0.1u/50V_6 0.1u/50V_6
*680p/50V_6 PQ47 PR108
35
34
33
17
18
19
20
21
22
23
24
PR76 AO4710 PR80 1/F_6 +3VPCU_OUT 1 2
1
2
3
*Short_4 1/F_6 1 2 PR114 *0_4

1 2 3V_DL
2
PR119 *Short_4
PR92 VL SKIP 1 2 REF PR122
+5VPCU_FB *0_6 *0_4
PC45 PR98 *Short_4 PR111
2 0.1u/50V_6 PC61 *0_4
1
PD2 1u/16V_6
CHN217 3
PR112 *Short_4
1 +3VPCU
PC46
0.1u/50V_6 PR102 *Short_6
2
PD3
OCP:6.5A CHN217 3 OCP:9A PR110
B B
L(ripple current) PC47 L(ripple current) *100K/F_4
1 0.1u/50V_6
=(9-5)*5/(2.2u*0.4M*9)=2.525A =(9-3.3)*3.3/(2.2u*0.5M*9)
Iocp=6.5-(2.525/2)=5.24A +15V_ALWP 1 2 =1.9A
+15V
DDPWRGD_R
Vth=5.24A*14.2mOhm=0.074V SYS_HWPG [36]
1
PR73 PR72 Iocp=9-(1.9/2)=8.05A
R(Ilim)=(0.07437V*10)/5uA=148.74K 22_8 *200K/F_4 PR95 PR82 *Short_4
PC48 *39K/F_4 Vth=8.05A*14.2mOhm=114.31mV
Ipeak(choke)=10.687A 0.1u/50V_6 R(Ilim)=(114.31mV*10)/5uA=228.62K
2
Ipeak(choke)=11.479A
VIN +3V_S5 +5V_S5 +15V VIN +5VPCU +5VPCU +3VPCU +3VPCU
PR210 PR196 PR205 PR208 PR207
3
1M_6 22_8 22_8 1M_6 *1M_6
5
6
7
8
5
6
7
8
5
6
7
8
S5D 2
S5D 4 MAIND 4 MAIND 4
3
PQ58
A PQ54 PQ34 PQ59 AO3404 10mil A
1
2 AO4468 AO4468 AO4468
[36,45] S5_ON
2 2 2 +3V_S5 0.23A
3
2
1
3
2
1
3
2
1
PR206 PQ39 PQ41

1
PQ40 1M_6 DMN601K-7 DMN601K-7

DTC144EU PQ44 PC144
+5V_S5 +5V +3V
1
DMN601K-7 *2.2n/50V_4
1
C622 C744
2.85A PROJECT : ZRB
*22u/10V_1206
2.171A *22u/10V_1206
3A Size Document Number Rev
114mil
2
87mil 107mil 1A
SYSTEM 5V/3V (RT8206)
5 4 3 2 1
5 4 3 2 1
VID 1.2875V
+3VPCU PR191 *0_4 H_VID0 DELAY_VR_PWRGOOD [4,8]
VIN
5/20 add
PR192 *0_4 H_VID1 Connect to input caps
+VCC_CORE
1
+ +
Countinue current:36A
PR190 *0_4 H_VID2
Peak current:48A
2
PQ32
OCP minimum 55A
5
PR189 *0_4 H_VID3 AOL1448
PR64
1K/F_4 PC27 PC28 PC129 PC128 PC29 PC126 PC127 Loadline=1.9mV/A (IMVP 6.5)
PR188 *0_4 H_VID4 2200p/50V_4 0.1u/50V_6 4.7u/25V_8 4.7u/25V_8 4.7u/25V_8 100u/25V_6X5.7 100u/25V_6X5.7
D +3VPCU 4 Rilm=1.69K D
6/3 add for EMI
1
2
3
PR187 *0_4 H_VID5 +5VPCU +3V PL8 +VCC_CORE
0.36uH
PR184 *0_4 H_VID6 1 2

750mil
PC138
1000p/50V_4 PQ37 PQ35
4
5
1
PR201 *Short_4 AOL1718 AOL1718 + +
+5VPCU PR62 PR49 PR45 PC135 PC30
649K/F_4 1.91K/F_4 *2.2/F_6 0.1u/50V_6 330u/2V_7343
2
4 4
PR197 *Short_4
16 3212_RAMP
PR44
1
2
3
1
2
3
10_6 PC26
PC32 *330u/2V_7343
*1000P/50V_6
3212_VCC
PR43
37
39
38
2
PR40 10/F_6
+1.05V PC31 *Short_4
VCC
PH0
PH1
PWRGD
RAMP
2.2U/6.3V_6
5/19 change to 0603
PR60 12 35 3212_DH1
*499/F_4 AGND DRVH1
49 36 3212_BOOT1
AGND BST1 PR48 2.2_6
[4] H_PROCHOT#
PR41 *Short_4 PC33
PSI#_1 41 0.22u/25V_6
[6] H_PSI# PSI#
3
PQ6 34 3212_SW1
*DMN601K-7 SW1
6/3 add for EMI
2 10 VR_TT VIN
C C
This NTC Close to Phase 1 Inductor
1
PR200 31 3212_DL1 +
DRVL1
+5VPCU
1
7.32K/F_4 PC146
PR181
2
11 100u/25V_6X5.7
TTSNS
*220K_6 NTC +5VPCU
+5VPCU PR57 5.1K/F_4 8 PU3
PC136 TRDET# PC37
1 2 9 VARFR
5
Panasonic *.01U/16V_4 ADP3212 32 1 2 PQ45 PC44 PC143 PC141 PC142 PC140
PVCC AOL1448 2200p/50V_4 0.1u/50V_6 4.7u/25V_8 4.7u/25V_8 4.7u/25V_8
[6] H_VID0 48
ERT-J0EV474J VID0 4.7U/6.3V_6
47 26 3212_DH2 4
[6] H_VID1 VID1 DRVH2
[6] H_VID2 46 25 3212_BOOT2
1
2
3
VID2 BOOT2
45 PR59 PL9 +VCC_CORE
[6] H_VID3 VID3 2.2_6 PC39 0.36uH
44 0.22u/25V_6 750mil
[6] H_VID4 VID4
27 3212_SW2 1 2
SW2
[6] H_VID5 43 VID5
5
PQ42 PQ43
4
5
42 AOL1718 AOL1718
[6] H_VID6 VID6
PR47 *Short_4 PR65
1
VR_ON 1 29 3212_DL2 4 *2.2/F_6 + +
[36] VRON EN DRVL2
4 PC25 PC134
2
PR42 499/F_4 DPRSLPVR_R 40 0.1u/50V_6 *330u/2V_7343

[6] H_DPRSLPVR
1
2
3
2
PR46 DPRSLPVR
30
1
2
3
100K/F_4 PGND PC41
[3] VR_PWRGD_CK505# 4 CLK_EN# *1000P/50V_6 PR69 PR70
+3V PR53 1.91K/F_4 *Short_4 10/F_6 PC38
1
330u/2V_7343
28 PR58 100/F_4 3212_CS_PH2
SWFB2
22 OD3# 5/19 change to 0603
23 33 PR54 100/F_4 3212_CS_PH1
PWM3 SWFB1
B B
24 SWFB3
PC35 19 3212_CSSUM PR71
150p/50V_4 CSSUM 150K/F_6
PC42
3212_FB 6 1000p/50V_4 PR68 PR66
FB
1
165K/F_4 150K/F_6
1
PC34
2
12p/50V_4 PC40
PC36 PR55 820P/50V_4 PR180
2
150p/50V_4 39.2K/F_4 220K_6 NTC

PR56 3212_COMP 7
COMP CSCOMP 20
1.65K/F_4
17 3212_CSCOMP
3212_FBRTN PC133 1000p/50V_4 LLINE PR67
5 FBRTN Close to Phase 1 Inductor
73.2K/F_4
21 3212_ILIM
ILIM
3
CSREF
IMON PR61
IREF
RPM
PR198 1.69K/F_4
RT
4.99K/F_4
1 2
13
14
15
18
PR63 *Short_4
PC132 3212_CSREF CSREF
0.082u/16V_4
[6] I_MON
PC139
PR194 1u/6.3V_4 Peak :40A ; OCP:53A (1.69K/F_4)
PR199 *0_4
*27.4_4 Peak :48A ; OCP:55A (1.74K/F_4)
PR204 PR202
+1.05V 80.6K/F_4 162K/F_4
A PR203 A
69.8K/F_4
PR51 *Short_4
VSSSENSE [6]
VCCSENSE [6]
PR52 *Short_4
PR50
*27.4_4 PROJECT : ZRB
+VCC_CORE Size Document Number Rev
1A
+VCC_CORE ADP3212
5 4 3 2 1
5 4 3 2 1
[PWM]
VIN 760mil
D +5V_S5 D
EC11
OCP:23A
5/19 add 0.1u/50V_6 19A
PR130 + +1.05V
10_6 5/19 change location
5
PR133 PD4
PC165
2.2/F_6 RB500V-40
PR128
PC80
+
1M/F_4 4
4.7u/6.3V_6
PC179 PC178 PC180 PC86 560u/2.5V
1
2
3
PU6 100u/25V_6X5.7 2.2n/50V_4 4.7u/25V_8 4.7u/25V_8
G5602 PC83
PR129 *Short_4 PR127 0.1u/50V_6
15 13 *Short_6 PQ55
[19,36,41,44] MAINON EN/DEM BOOT AOL1448
+3V 16 12 UGATE-1.05V PL14
PC82 TON UGATE 0.56uH
*0.1u/50V_6 1 11 PHASE-1.05V
VOUT PHASE
PR135 2 10 PR131
VDD OC
5
C *10K/F_4 2.15K/F_4 C
3 9 PC85 PR238
FB VDDP 1u/16V_6 *4.7_6 +
4 8 LGATE-1.05V 4 4
[36] HWPG_1.05V PGOOD LGATE
6 7 PC181
1
2
3
1
2
3
GND PGND PQ56 PQ57 *680p/50V_6
5 17 AOL1718 AOL1718
NC TPAD
14 NC PC172 PC176
PC84 PC81 560u/2.5V_6X5.7 0.1u/50V_6
1u/16V_6 *1000p/50V_6
PR132
B 4.02K/F_4 PC177 B
R1 *33p/50V_6
1.05V_FB
PR134
10K/F_4
R2
PR136 *Short_4
PR239 *Short_4
AO1718 Rdson=3~4.3mOhm
TON=3.85p*RTON*Vout/(Vin-0.5)
L(ripple current)
=(19-1.05)*1.05/(0.56u*272k*19)
Frequency=Vout/(Vin*TON)
~6.512A
A A
TON=3.85p*1M*1/(Vin-0.5) RILIM=2.15mohm*23-3.256/20uA=2.122Kohm
I(choke)peak=29.512A Quanta Computer Inc.
Frequency=1/(0.0036767)=272K
PROJECT : ZRB
1A
+VTT (UP6111A)
5 4 3 2 1
5 4 3 2 1
[PWM] Maintenance and Service Guide,Service Manual,Motherboard Schematics for Laptop/notebook http://mycomp.su/x/
D D
PC167
10u/10V_8
PC168
PR229 *Short_6 0.1u/50V_6
8207A_VBST 6/3 add for EMI
+0.75V_DDR_VTT
VIN
8207A_DH
PC170 PC169 5/19 add
0.75A 10u/10V_8 10u/10V_8 8207A_LX PC75
0.1u/50V_6 +
5
8207A_DL
PC73 PC74
4.7u/25V_8 4.7u/25V_8
4
720mil
25
24
23
22
21
20
19
PC76 PC164
OCP:20A
1
2
3
PQ50 2200p/50V_6 *100u/25V_6X5.7
18A
GND
VLDOIN
DRVH
LL
DRVL
VTT
VBST
AOL1448
1 18 +1.5VSUS
VTTGND PGND
PL12
2 17 0.56uH
VTTSNS CS_GND
5
3 RT8207A 16 PR123
GND PU11 CS 7.5K/F_4
PR121
+1.5VSUS 4 15 4 *4.7_6 +
C MODE V5IN +5V_S5 C
PQ53 PC157 PC64
1
2
3
5 14 AOL1718 560u/2.5V 0.1u/50V_6
+SMDDR_VREF VTTREF V5FILT
1
PR230
VDDQSNS
PC79 +5V_S5 PC173 5.1/F_6 PC78 PC77

VDDQSET
6 13
0.15A 0.033u/50V_6 COMP PGOOD 1u/6.3V_4 1u/6.3V_4 *680p/50V_6
2
NC
NC
S3
S5
PR126 +3V
100K/F_4
7
10
11
12
FOR DDR III

HWPG_1.5V [36]
PR233 (For RT8207A 400KHZ ) close to pc2008

VIN
620K/F_4
PR236 *Short_4
S5_1.8V
SUSON [36]
PR124 *Short_4
PR237 *Short_4
S3_1.8V
MAINON [19,36,40,44]
PR125 *Short_4
PR235 +5V_S5
*0_4
PC175 PR232
*33p/50V_6 10.2K/F_4
Vout = (PR150/PR149) X 0.75 + 0.75
B B
AO1718 Rdson=3.8~4.3mOhm
8207A_SET
L(ripple current)
=(19-1.5)*1.5/(0.56u*400k*19)
PR234 S5_1.8V PR231 S3_1.8V ~6.168A
10K/F_4 *0_4
Vtrip= (20-6.168/2)*4.3mohm=0.072739V
+1.5VSUS RILIM=Vtrip/10u=7.273K
5
6
7
8
MAIND 4
[38,44] MAIND
PQ60
AO4468 S3 S5 +1.5VSUS REF VTT
3
2
1
S0 1 1 ON ON ON
+1.5V
2.03A S3 0 1 ON ON OFF
82mil S4/S5 0 0 OFF OFF OFF
A A

PROJECT : ZRB
1A
DDR 1.5V(RT8207A)
5 4 3 2 1
A B C D E F G H
Int_VGA [PWM]
[6] GFX_VID0
[6] GFX_VID1 +1.05V +1.05V

[6] GFX_VID2
OCP:14.1A
[6] GFX_VID3
1 Ri=2.87K 1
PR86 PR87 PR79 PR88 PR89 PR212 PR213
[6] GFX_VID4 Change Ri can adjust OCP point
*0_4 *0_4 *0_4 *0_4 *0_4 *0_4 *0_4
[6] GFX_VID5 LL=7.08mv/A
[6] GFX_VID6
PC150
Rdroop=4.99K
*0.01u/25V_4 GFX_VID6 GFX_VID5 GFX_VID4 GFX_VID3 GFX_VID2 GFX_VID1 GFX_VID0 Change Rdroop can adjust loadline
62881_GND 2 1
PR217 IV@100K_4
PR214 *Short_4
[6] GFX_ON
PR85 *Short_4
[6] GFX_DPRSLPVR
PR215 *Short_4
VIN
62881_GND
PR216 *Short_4
62881DPRSLPVR
62881VR_ON
GFX_VID6
GFX_VID5
GFX_VID4
GFX_VID3
GFX_VID2
62881_GND
+3V
30
31
29
28
27
26
25
24
23
22
PC56 PC54 PC55
5
PR90 IV@2.2n/50V_4 IV@4.7u/25V_8 IV@4.7u/25V_8
GFX_VID1
GFX_VID0
GND
GND
GND
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
*100K_4
2 1 CLK_EN# 2
PR78 *Short_4 4
62881PGOOD 2 21 +5V_S5
[36] HWPG_GFX PGOOD VID1
1
2
3
PQ49
PR221 IV@47K/F_4 62881RBIAS IV@AOL1448
PR223
62881_GND 3 RBIAS VID0 20 660mil
*150K/F_4 PC151
DCR= 1.6 ~1.8 mohm OCP:22A
PR91 IV@8.06K/F_4 62881VW 4 19 1 2
62881_GND VW VCCP
PC58 IV@4.7u/6.3V_6
16.5A
LGATE 18 62881LGATE PL11
IV@1000P/50V_4 62881COMP 5 IV@0.56uH +VGFX_AXG
COMP PU4
PR93 PC60 IV@ISL62881HRTZ-T 17 1 2
IV@820K/F_4 IV@22p/50V_4 VSSP
62881FB 6
4
FB
PHASE 16 62881PHASE
PC62 PQ48 PQ7
IV@100P/50V_4 PR97 IV@AOL1718 IV@AOL1718 PR77
5
IV@8.87K/F_4
UGATE 15 62881UGATE *2.2/F_4 DCR=1.6~1.8mOhm
62881VSEN 7 PR225 + +
VSEN IV@3.65K/F_4 Load Line=7mV/A
ISUM+
1.6m*0.6168=0.986m
ISUM-
BOOT
IMON PC52
Rdroop 4 4
VDD
RTN
VIN
PR99 PC67 IV@10u/6.3V_8 0.986m/.49K=396p

PR107 PR211
392p*2*8.87K=7.03m
1
2
3
1
2
3
PR101 PC65 IV@2.61K/F_4 IV@10K_6_NTC
8
62881ISUM+ 10
62881VDD 11
12
13
14
IV@17.8K/F_4 IV@150P/50V_4 PC161 IV@1_6 IV@0.22u/25V_6 PC50 OCP
PC153 IV@330p/50V_4 62881BOOT 1 2 Close to Phase 20u/2*2.49K=24.9m
62881ISUM-
62881VIN
IV@330p/50V_4 *2.2n/50V_4
62881RTN PR106 Inductor PC147 PC148 24.9m/0.6168=40.3m
GFX_IMON IV@560u/2.5V_6X5.7 IV@560u/2.5V_6X5.7 40.3m/1.6m=25.2A
GFX_IMON [6]
PC155 IV@11K/F_4
2
62881_GND PR117
IV@1000P/50V_4 *10K/F_4 PC72
*0.22u/10V_4
1
3 PC70 PC160 3
IV@0.15U/10V_4 IV@0.1u/10V_4
VSS_AXG_SENSE [6]
62881_GND PR222 *Short_4
VIN
PC159 62881_GND
PC152 *0.1u/10V_4
IV@0.22u/25V_6
62881_GND
+5V_S5 Ri
PC162
*180P/50V_4
PR226
PR224 IV@2.49K/F_4
IV@10_6
PC154
IV@1u/6.3V_4 PR227
*100/F_4
62881_GND
2 1
PR105 PC69
IV@82.5/F_4 IV@0.01u/25V_4
Close to Pin9 and Pin10
Parallel
PR118 IV@10/F_4
PR104 *Short_4
4 VSS_AXG_SENSE 4
PR116 IV@10/F_4
PR103 *Short_4
VCC_AXG_SENSE [6]

PROJECT : ZQ9
1A
+VGFX_AXG (ISL62881)
1.Level 1 Environment-related Substances Should NEVER be Used. Date: Wednesday, July 21, 2010 Sheet 42 of 9
A B C D 2.Purchase
E ink, paint, wire rods, and Molding resins only Ffrom the business Partners that Sony approves as Green Partners.
G H
1 2 3 4 5
A +5V_S5 A
VIN
PR32
+3V_D_S *0_4
PR164
5
EV@200K/F_4 PC20 PC19
PC105 EV@1u/10V_6 2 7 8792TON EV@4.7u/25V_8
VDD TON EV@2200p/50V_4
PR169 5 8792DH 4 4
EV@10K_4 PC107 EV@1u/10V_6 8792VCC DH PC18
13 VCC
5/12 change EV@4.7u/25V_8
1
2
3
1
2
3
6 8792BST +VGPU_CORE
BST PR165 PQ26 PQ25
[45] PG_1V_EN 14 PGOOD EV@1_6 PC103 EV@AOL1448 EV@AOL1448
8792EN 1 PU7 EV@0.22u/25V_6
1050mil
[11,19] dGPU_VRON EN 8792LX
PR160 EV@MAX8792ETD+T LX
4 OCP=35A
*0_4 8792SKIP# 12 PL6
SKIP#
3 8792DL EV@0.68uH_13X13X5 26.25A
DL
5
PC106 PR35 *0_4
[19,21,36] +3V_D_S EV@0.1u/10V_4 8792REFIN 10
PR28 *Short_4 REFIN PR36
FB 8
4 4 *2.2_6 + + +
PR30 REF-2V
EV@100K_4 8792REF 11 9 8792ILIM
1
2
3
1
2
3
REF ILIM
PQ28 PC21
EP
B B
EV@AOL1718 *1000p/50V_4
R1 PR168
15
EV@39.2K/F_4
PR166 PC111
EV@51K/F_4 PC22 EV@330u/2V_7343
*4700P/25V_4 PQ27 PC108 PC24 PC23
R3 EV@AOL1718 EV@0.1u/50V_6 EV@330u/2V_7343 *330u/2V_7343
PR27 PC104
3
EV@332K/F_4 EV@1000P/50V_4
PR167
EV@100K_4
[17] VID1 2
Frequency(PR220=200K) 300K
PQ4
PR25 EV@DMN601K-7 VIN +VGPU_CORE
EV@3K_4 PR31
1
R2 EV@49.9K/F_4
AMD Park VID Table PR161 PR159

PC16 EV@1M_6 EV@22_8
EV@0.01u/16V_4 GPU_VID1 (GPIO15) GPU_VID2 (GPIO20) +VGPU_CORE
R4
0 0 1.12V
3
1 0 1.05V
3
C C
PR29
3
EV@130K/F_4 0 1 0.95V 2
8792EN 2
1 1 0.9V PQ22
2 PR162 EV@DMN601K-7
[17] VID2 PQ23 EV@1M_6
1
PQ5 EV@DTC144EU
PR26 EV@DMN601K-7 PR33 *Short_4
EV@3K_4
1
PR34 *Short_4
PC17
EV@0.01u/16V_4
Place near GND pin15
D D

PROJECT : ZQ9
1A
GPU CORE(MAX8792)
1 2 3 4 5
5 4 3 2 1

+3VPCU
PC118
PC119 0.1u/25V_4
10u/10V_8 2.17A 87mil
PU8 HPA00835RTER
16 10 +1.8V
VIN PH
1 11 PL7
VIN PH 1uH_7X7X3
D D
2 VIN PH 12
PR37 *Short_4 PR170 *Short_6
[19,36,40,41] MAINON 15 EN BOOT 13
54418-1_VFB 6 14 PC113
VSNS PWRGD 0.1u/50V_6
PR39 PC116 7 3 5/12 change
*100K/F_4 COMP GND
1000p/50V_4
8 4 R1 PR173
RT/CLK GND 100K/F_4
PAD
PAD
PAD
PAD
PAD
PAD
HWPG_1.8V [36]
9 SS AGND 5 PR38
PR172 PR171
100K/F_4
15K/F_4 182K/F_4 +3V_S5
22
21
20
19
18
17
PC109
PC117 PC112 10u/10V_8 PC110
*100P/50V_4 PC114 0.1u/25V_4 10u/10V_8
0.01u/25V_4 54418-1_VFB
PC115
V0=0.8*(R1+R2)/R2
1200p/50V_4
PR174
R2 78.7K/F_4
+1.5VSUS
VIN +1.5V_GPU +15V
C618
+
C PQ29 C
5
PR145 PR149 PR240 EV@AOL1718 EV@100u/6.3V_3528 close PQ9030
EV@1M_4 EV@22_8 EV@1M_4
dGPU_D 4
342mil
3
1
2
3
3
8.55A
[45] PG_1.5V_EN 2 2 2
PR148 PC125 +1.5V_GPU
1
EV@1M_4 PQ16 PQ61 *2.2n/50V_4

PR147 PQ14 EV@DMN601K-7 EV@DMN601K-7
1
*100K_4 EV@DTC144EUA
1
1
2
VIN +1.8V_GPU +15V +1.8V
3
+1.5V_GPU PR24 PR23 PR163
EV@1M_4 EV@22_8 EV@1M_4
dGPU_D1 2
PR16
3
EV@1K_4
57mil
3
PQ38
B EV@AO3404 B
1.41A
1
2 2 2
PC102
+1.8V_GPU
1
PR17 PQ2 PQ24 *2.2n/50V_4

PR18 PQ3 EV@1M_4 EV@DMN601K-7 EV@DMN601K-7
1
EV@100K_4 EV@PDTC143TT
1
1
2
VIN +3V +5V +0.75V_DDR_VTT +1.5V +1.8V +15V
PR143 PR140 PR141 PR146 PR142 PR139 PR138

1M_4 22_8 22_8 22_8 22_8 *22_8 1M_4
MAINON_ON_G MAIND
MAIND [38,41]
3
3
3
PR144
MAINON 2 PQ8 1M_4 2 2 2 2 2 2
DTC144EU PC87
PQ11 PQ12 PQ15 PQ13 PQ9 PQ10 *2200p/50V_4
DMN601K-7 DMN601K-7 DMN601K-7 DMN601K-7 *DMN601K-7 DMN601K-7
1
PR137
1
A *100K/F_6 A
7/7 modify

PROJECT : ZRB
1A
Discharge/1.8V)
5 4 3 2 1
5 4 3 2 1

+3V_S5
1
+5VPCU PR176
EV@10K_4
PC123 PU9
2
EV@0.1u/50V_6 EV@G966A
4 VPP PGOOD 1 PG_1.5V_EN [44]
D D
[43] PG_1V_EN 2 VEN VO 6 +1V
+1.5VSUS 3
8
VIN
GND
1.5A
1
ADJ
9 GND NC 5
1
PR177
PR175 EV@9.1K/F_4
7
EV@100K_4 PC124
2
EV@22u/10V_1206
2
0.8V
PC121 PC122 PC120
EV@10u/10V_8EV@0.1u/50V_6
EV@0.1u/50V_6
PR178
EV@34K/F_4
Vout =0.8(1+R1/R2)
=1V
C C
VIN
PU10B
LM393
5 +
PD8 7
SW1010CPT 6 -
PR179
For EC control thermal protection (output 3.3V)
1M_6
Thermal protection
1
PQ33
AO3409
2
3
B B
3
S5_ON 2
[36,38] S5_ON
PQ30 PR193
1
DTC144EU *Short_6
VL VL
SYS_SHDN# [4,38]
Need fine tune
for thermal protect point PR195
200K_6
PR183 PC131
PR185 200K/F_4 0.1u/50V_6
3
1.74K/F_4
8
PR186
10K_6_NTC 2.469V 3 +
1 2
2 - PQ36
3
PU10A DMN601K-7
4
Note placement position LM393 PC130

1
A 0.1u/50V_6 A
S5_ON 2
PR182
PQ31 200K/F_4
DMN601K-7 Quanta Computer Inc.
1
PROJECT : ZRB
1A

5 4 3 2 1
5 4 3 2 1

ZY9B MODEL
Model REV CHANGE LIST FROM To

X 1A
FIRST RELEASED
1A X 1A
ZY9B MB Page 3 : Unstuff L54 & stuff R586 & change U31 P/N for 3V CLK gen and Switch CLK_BUF_DREFSSCLK and CLK_BUF_PCIE_3GPLL
Page 4 : Q16 Change P/N for EOD part & short R116 (Del.) for 0 ohm
1A 2A
Page 8 : Short R244 (Del.) for 0 ohm 1A 2A
Page 10 :Short R243 (Del.) for 0 ohm
Page 12 :Short R189 ,R190 & R534 (Del.) for 0 ohm & C655 change P/N for EOD part 1A 2A
Page 14 :Del. R268 & R247 for M3 solution & stuff R269 ,R229 ,R223 & R226 for M1 solution,Stuff C372 for +1.5VSUS leakage
Page 15 :Stuff C459 for +1.5VSUS leakage 1A 2A
Page 25 :Q12 ,Q17 & Q18 Change P/N for ESD , CN10 Change P/N ,Q14.2 & Q13.2 Change from +5V to +3V
Page 27 :C339 & C391 of footprint Change from 0805 to 0402 for ESD 1A 2A
Page 28 :Unstuff R566 ,R294 ,R284 ,R279 ,R276 ,R273 ,R272 for disable debug card function
2A Page 29 :C393 & C254 Change P/N for EOD , CN11 Change footprint for ME design request. 1A 2A
Page 30 :U13 Change AMP circuit
D
Page 31 :Q22 & Q23 Change P/N for EOD part. 1A 2A D
Page 34 :Del. L55 , CN12 Change P/N
Page 36 :C27 Change P/N for EOD part 1A 2A
Page All : Change to short pad : Location : R458 ,R452 ,R537 ,R533 ,R144 ,R155 ,R191 ,R140 ,R201 ,R224 ,R461 ,R136 ,R197
,R206 ,R219 ,R212 ,R166 ,R174 ,R188 ,R202 ,R209 ,R184 ,R168 ,R185 ,R448 ,R447 ,R5 ,R10 ,R9 ,R6 ,R263 ,R288 ,R544 ,R436 ,R563 1A 2A
,R570 ,R569 ,R584 ,R299 ,C738 ,R311 ,R585 ,R583 ,R571 ,R582 ,R575 ,R576 ,R579 ,R333 ,R352 ,R331 ,R332 & R349 1A 2A
1A 2A
1A 2A
1A 2A
1A 2A
1A 2A
1A 2A
1A 2A
1A 2A
1A 2A
1A 2A
1A 2A
1A 2A
1A 2A
1A 2A
1A 2A
2A 3A
2A 3A
2A 3A
3A 2A 3A
2A 3A
2A 3A
C
2A 3A C
2A 3A
2A 3A
2A 3A
2A 3A
2A 3A
2A 3A
2A 3A
2A 3A
2A 3A
2A 3A
2A 3A
2A 3A
2A 3A
2A 3A
2A 3A
2A 3A
2A 3A
2A 3A
2A 3A
2A 3A
2A 3A
2A 3A
2A 3A
2A 3A
B
2A 3A B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
3A 3B
A
3A 3B A
3A 3B
3A 3B
3A 3B
3A 3B
3C

PROJECT : ZYA DOC NO. PROJECT MODEL : ZY9B APPROVED BY: DATE: 2009/05/??
1A
Change list PART NUMBER: DRAWING BY: REVISON: 1A
5 4 3 2 1

Quanta ZRC

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5 4 3 2 1

Maintenance and Service Guide,Service Manual,Motherboard Schematics for Laptop/notebook http://mycomp.su/x/

BOM Option Table

rPGA 989 Park_XT Channel B 128Mb x 16 IO x 8 pcs

X'TAL SLG8LV595 DMI(x4)

Cardreader AU6437-GBL USB-12 X'TAL 25MHz

Azalia SPI SPI ROM

LPC RT8206B RT8207A TPS54418RTE x2

GPU PWR CTRL Option 2 (VDDR3 after VDDR1)

Thermal Follow Chart

+VCCRTC +3V~+3.3V RTC POWER ALWAYS ALWAYS NTC

+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS

+3V_S5 +3.3V LAN/BT/CIR POWER S5_ON S0-S5 CPU 3V/5 V

+5V +5V HDD/ODD/Codec/TP/CRT/HDMI POWER MAINON S0

+3V +3.3V PCH/GPU/Peripheral component POWER MAINON S0

+VGFX_AXG variation Internal GPU POWER GFX_ON S0

+1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0

+1.05V +1.05V PCH CORE POWER MAINON S0

+VCC_CORE variation CPU CORE POWER VRON S0

LCDVCC +3.3V LCD POWER LVDS_VDDEN S0

+5V_GPU +5V SWITCHABLE PWM IC POWER dGPU_PWR_EN# Discrete enable

+GPU_CORE +0.9V~+1.1V GPU CORE POWER +3V_D Discrete enable

+GPU_IO +0.9V~+1.1V GPU I/O POWER PG_GPUIO_EN Discrete enable

+1.5V_GPU +1.5V VRAM CORE POWER PG_1.5V_EN Discrete enable

+1.8V_GPU +1.8V GPU_CRE/LVDS/PLL POWER +1.5V_GPU Discrete enable

+1V +1V DP/PEG POWER PG_1V_EN Discrete enable

Quanta Computer Inc.

Maintenance and Service Guide,Service Manual,Motherboard Schematics for Laptop/notebook http://mycomp.su/x/

6/21 add R586 for 3V CLK gen

Quanta Computer Inc.

Maintenance and Service

JTAG & BPM

XDP_TMS R112 *51_4 R120 EV@1K_4

Quanta Computer Inc.

Maintenance and Service Guide,Service Manual,Motherboard Schematics for Laptop/notebook http://mycomp.su/x/

[15] M_B_DQ[63:0] SB_CK[0] W8 M_B_CLK0 [15]

DDR SYSTEM MEMORY - B

M_A_DQ35 SA_DQ[34] SA_DQS#[0] M_A_DQS#1 M_B_DQ40 SB_DQ[39] SB_DQS#[5] M_B_DQS#6

Channel A DQ[15,32,48,54], DM[5] Channel B DQ[16,18,36,42,56,57,60,61,62]

Quanta Computer Inc.

Maintenance and Service Guide,Service Manual,Motherboard Schematics for Laptop/notebook http://mycomp.su/x/

VTT Rail Values are AUBURNDALE/CLARKSFIELD PROCESSOR (GRAPHICS POWER)

1.1V RAIL POWER

C284 330u/2V_7343 AC34 A11 AJ19 AB7

C285 330u/2V_7343 AC32 +1.05V AJ16 Y1

CPU CORE SUPPLY

PEG & DMI

VCC62 VTT1_52 VTT1_68

R28 VCC88 VCC_SENSE AJ34 VCCSENSE [39]

AT20 VSS1 VSS81 AE34 RSVD32 AJ13

AL20 VSS40 VSS120 W6 E21 VSS198 AJ29 CFG[15] RSVD_TP_59 E15

CFG7 R103 *3.01K/F_4

Maintenance and Service Guide,Service Manual,Motherboard Schematics for Laptop/notebook http://mycomp.su/x/

0-ohm resistor place close to PCH IBEX PEAK-M (LVDS,DDI)

Digital Display Interface

[36] ICH_RSMRST# C16 RSMRST# SLP_S4# H7 SUSC# [36] DDPD_AUXN BC46

PM_RI# F14 F6 PM_SLP_LAN# TP6

PCH Pull-high/low System PWR_OK

PM_RI# R200 10K_4

Maintenance and Service Guide,Service Manual,Motherboard Schematics for Laptop/notebook http://mycomp.su/x/

R487 33_4 ACZ_BIT_CLK SPI_CLK_R BA2

SPI_SI_R AY1 Y9 R252 43K/F_4 +3V