TE1M motherboard part numbers and diagram

1 2 3 4 5 6 7 8
VER : E3D
BOM P/N
31TE1MB0010
Description
TE1M MB(PM45/RB/MS)WO CPU

TE1M Block Diagram
31TE1MB0120 TE1M MB(PM45/MAIN/RB/HDMI/CIR)WO CPU
31TE1MB0130 TE1M MB(GM45/EXP/NO CIR/MS)WO CPU
31TE1MB0140 TE1M MB(GM45/GS/EXP/MS)WO CPU

A
31TE1MB0170 TE1M MB(GM45/GS/EXP/LC)WO CPU PENRYN EXT_CRT
A
Azalia
31TE1MB01N0 TE1M MB(GM45/HDMI/EXP/MS)WO CPU 478P uFCPGA
31TE1MB01M0 TE1M MB(GM45/HDMI/GS/CIR/MS)WO CPU VGA Con. EXT_LVDS CRT Con. P20
31TE1MB01P0 TE1M MB ASY(GL40/PC/GS/FE/HD/KI,MS)WOCPU FSB P3,4 (FOX) EXT_HDMI
31TE1MB01Q0 TE1M MB ASY(GM45/PC/GS/FE/HD/KI,MS)WOCPU P18
31TE1MB01S0 TE1M MB(PM45/HDMI/NO CIR/MS)WO CPU
LCD/CCD Con.
FSB(667/800/1066MHZ) P19
PCI-E x16 PI3VDP411LST INT_HDMI

FSB USB-3
Dual Channel DDR II PCI-E PCIE HDMI level shift LED/CCD Con.
DDRII-SODIMM1 P21 P19
667/800 MHZ
DDRII-SODIMM2 CANTIGA
P16,17 INT_CRT
NB
INT_LVDS
P5,7,8,9,10,11 HDMI Con.
R5F211A4SP
PCB STACK UP SATA - HDD
I2C
CEC
CEC_I2C P21
DMI P21
P22
LAYER 1 : TOP
DMI(x2/x4)
LAYER 2 : GND1 SATA - ODD
P22 PCIE-1 ICS9LPR365 CK505
B
LAYER 3 : IN1 SATA 0 NEW CARD Con. B
USB-9 CLOCK GENERATOR

LAYER 4 : VCC SATA 1 DMI
P27 P2
SATA MINI CARD-3
LAYER 5 : IN2 PCI-E PCI-Express PCIE-2
PI2EQX3201B U 9H_HD-DVD
SATA 4
LAYER 6 : IN3 Re-driver P27 P25 POWER SYSTEM
USB/ESATA PCIE-3 ISL88731 P31
LAYER 7 : GND2 USB-7 MINI CARD-2
P32
P27 USB-8 U 5.6H_TV/ROBSON ISL6237
LAYER 8 : BOT D 7.5H_HD-DVD
P25
ISL6266A P33
USB-1 USB 2.0 (Port0~9) MINI CARD-4 (FTB) RT8202 P34
Finger Printer USB PCIE-4
D ROBSON TPS51116 P35
(FTB) P26 Intel I/O Controller Hub 9 P25 APL5913 P36
BOM Option Table
(ICH9M) PCIE-5
USB-2 G909 P36
Reference Description Bluetooth Con. USB-0 LAN/ USB/ FM
P26
NB LED POWER DRIVER
IV@ INT VGA
RTC
Con.
ISL97636 P19
EV@ EXT VGA Port-C (FM)
USB-4 P12, 13, 14, 15
Felica Con. P26
(FTB) P26 BATTERY PCIE-6
MINI CARD-1
USB-6 P12 USB-5 U&D 5.6H_WLAN VCC_CORE
USB Port P25
C C
P27
W25X16VSS1G SPI PCI PCI Bus CB1410 PCMCIA SOCKET +1.5V

SPI
SPI FLASH PCMCIA Controller
P13 P23 P23
Azalia +1.05V
MDC Con. IHDA
P30 LPC
Cardreader Con.
OZ129T P24
5 IN 1
Cardreader/1394 Controller +1.8VSUS
LPC P24 1394 Con. +1.8V
P24
INT_ MIC +1.5V_S5

P19 CX20561-12Z WPC8763LDG +3VPCU
AUDIO CODEC EC P28 +3V_S5
INT_ MIC P29 +3VSUS
P29 +3V
+5VPCU
+5V_S5
VR Kill SW CIR LIS3L02AQ3 MMB Board Touch Pad Power +5V
Con. Board Con. Board Con.
D
MIC JACK HP AMP SPK AMP G-Sensor +SMDDR_VTERM
D
P30 P30 P29 P30 P27 P28 P22 P26 P26 P26 +SMDDR_VREF
FM HP/SPDIF SPK Con. FAN K/B Con. W25X16VSS1G EC2648 Low Cost LED Board
P29 P30 P29 HALL SENSOR Board Con. Con.
SPI FLASH
P3 P26 P28 P19 P26 P26 Quanta Computer Inc.
PROJECT : TE1M
Size Document Number R ev
E3D
Block Diagram
Date: Monday, May 26, 2008 Sheet 1 of 40
1 2 3 4 5 6 7 8
5 4 3 2 1
Clock Generator +1.05V_VDD

BOM Option Table
PBY160808 T-301 Y-N_6 L 17

Reference Description
+1.05V
IV@ INT VGA
L518 PBY160808 T-301 Y-N_6 C700 0.1u/10V_4 C204 C205 C685 C206 C207 C677 C211 C208
+3V EV@ EXT VGA
*10u/10V_8 10 u/1 0V_8 0.1 u/1 0V _4 0.1u/10V_4 0.1 u/1 0V _4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
C704
C695 0.1u/10V_4
10u/10V_8
C706 10 u/1 0V _8
D C694 0.1u/10V_4 U12 D

VDD_CK_V DD_PCI 2 48
C676 0.1u/10V_4 VDD_CK_V DD_48 VDD_PCI IO_VOUT
9
VDD_CK_V DD_PCI VDD_48
16 64 CG CLK_S MB
VDD_ CK_VDD_ REF VDD_PLL3 SCLK CG DA T_S MB
61 63
+3V VDD_REF SDA
C643 0.1u/10V_4 VDD_CK_V DD_PCI 39
CK505 38 PM_S TPPCI#
VDD_SRC SRC5/PCI_STOP# PM_S TPP CI# 14
VDD_CK_V DD_ CPU 55
VDD_CPU SRC5#/CPU_STOP#
37 PM_S TPCP U#
PM_S TPCPU# 14 To SB
PM_S TPP CI# R219 2.2 K_ 4
12 54 CLK_CP U_B CLK_R RP52 1 2 0 X2
+1.05V_VDD VDD_96_IO CPU0 CLK_CP U_B CLK 3
C699 0.1u/10V_4 20
VDD_PLL3_IO CPU0#
53 CLK_CP U_B CLK#_R 3 4 CLK_CP U_B CLK# 3 To CPU
PM_S TPCPU# R218 2.2 K_ 4 26
VDD_SRC_IO_1 CLK_MCH_B CLK_ R RP50 0 X2
45 51 1 2 CLK_MCH_B CLK 5
VDD_SRC_IO_3 CPU1
36
VDD_SRC_IO_2 CPU1#
50 CLK_MCH_B CLK#_ R 3 4 CLK_MCH_B CLK# 5 To NB
NEW _CLK REQ #_R R215 10K_4 49
VDD_CPU_IO
47 C LK_PCIE_ MINI2&4_R
SRC8/ITP
B2A SRC8#/ITP#
46 CLK_PCIE_ MINI2&4#_R
B2A
PCLK_DEB UG R252 47_4 PCLK_ DEBUG_R 1 35 CLK_PCIE_3 GPLL#_R RP42 1 2 0 X2
2 5 PCLK_DEBUG PCI0/CR#_A SRC10# CLK_PCIE_3GPLL# 6
SRC10
34 CLK_PCIE_3 GPLL_R 3 4 CLK_PCIE_3GPLL 6 To NB
R249 33_4 PCLK_PCM_ R 3
23 PCLK_PCM PCI1/CR#_B
33 CLK_MCH_ OE#_R R217 4 75/F_4
SRC11/CR#_H CLK_MCH_ OE# 6
PCLK_ OZ129 R247 33_4 PCLK_O Z129_R 4 32 NEW _CL KREQ #_R R216 4 75/F_4
24 PCLK_ O Z129 PCI2/TME SRC11#/CR#_G NEW _CLK REQ # 27
C 22 6 27p/ 5 0V_4 CG_XIN R244 10K_4 PCI_ CLK_SIO_R 5 30 CLK_PCIE_ NEW _R RP43 3 4 0 X2
PCI3 SRC9 CLK_PCIE_ NEW 27
SRC9#
31 CLK_PCIE_ NEW _R# 1 2 CLK_PCIE_ NEW # 27 To New Card
Y3 PCLK_591 R238 33_4 PCLK_591_R 6
28 PCLK_591 PCI4/SRC5_EN
CL=20p SRC7/CR#_F
44 C LK_PCIE_ MINI3_ R B2A RP47 1 2 0 X2
CLK_PCIE_ MINI3 2 5
14.318MHZ
13 PCLK_ICH
PCLK_ICH R235 33_4 PCLK_ ICH_ R 7
PCIF5/ITP_EN SRC7#/CR#_E
43 CLK_PCIE_ MINI3#_R 3 4 CLK_PCIE_ MINI3# 25 To MINI3
C 23 9 27p/ 5 0V_4 CG_XO UT CG_XIN 60 41 CLK_PCIE_ MINI_R RP45 1 2 0 X2
XTAL_IN SRC6 CLK_PCIE_ MINI 2 5
SRC6#
40 CLK_PCIE_ MINI#_R 3 4 CLK_PCIE_ MINI# 2 5 To MINI1
B2A CG_XO UT 59
XTAL_OUT
B2A SRC4
27 CLK_PCIE_LA N_ R RP44 3 4 0 X2
CLK_PCIE_LAN 26
14 CLKUSB_48
R234 47_4 FSA 10
USB_48/FSA SRC4#
28 CLK_PCIE_LA N#_R 1 2 CLK_PCIE_LA N# 26 To LAN
C CLK_BSEL0 R227 2.2 K_ 4 FSB CLK_PCIE_ ICH_R RP46 0 X2 C
57 24 3 4 CLK_PCIE_ ICH 1 3
FSB/TEST/MODE SRC3/CR#_C
SRC3#/CR#_D
25 CLK_PCIE_ ICH#_R 1 2 CLK_PCIE_ ICH# 13 To SB
FSC 62
CLK_BSEL1 REF0/FSC/TESTSEL CLK_PCIE_SA TA_R RP48
21 3 4 0 X2 CLK_PCIE_SA TA 12
SRC2/SATA
8
VSS_PCI SRC2#/SATA#
22 CLK_PCIE_SA TA#_R 1 2 CLK_PCIE_SA TA# 1 2 To SB
11
CLK_BSEL2 R243 10K_4 VSS_48 DREFSS CLK_R
15 17
VSS_IO SRC1/SE1 DREFSS CLK#_R
19 18
R237 47_4 VSS_PLL3 SRC1#/SE2
14 14M_ICH 52
VSS_CPU DRE FCLK_R RP53
23 13 3 4 IV @0X2
VSS_SRC1 SRC0/DOT96 DRE FCLK 6
B2A 29
VSS_SRC2 SRC0#/DOT96#
14 DREFCLK#_R 1 2 DRE FCLK# 6 To NB
42
VSS_SRC3
58 56 CK_PW RG D 14
VSS_REF CKPWRGD/PWRDWN#
ICS9LP RS365B GL FT
<MAIN>:ICS9LPRS365BGLFT QCI:ALPRS365K13
C3B <SECOND>:SLG8SP512TTR: QCI:AL8SP512K05
ICS9LPRS365 R TM875T-606 R250 10 K_ 4 PCLK_ O Z129
+3V
(ALPRS365K13) (AL000875K06) PULL HIGH PULL DOWN
P CI2/TME
Pin 4 PCI2/TME internal PD NO OVERCLOCKING (default) NORMAL RUN
R246 *1 0K _4
B2A CLK_PCIE_ MINI2&4_ R RP49 1 2 IV @0X2 CLK_PCIE_ MINI2 2 5 To MINI2
CLK_PCIE_ MINI2&4#_R 3 4 CLK_PCIE_ MINI2# 25
P CI-3/SRC5_EN PIN37/38 IS
Pin 5 PCI-3 internal PD PIN37/38 IS SRC5 PCI_STOP/CPU_STOP (default) R242 *1 0K _4 P CLK _591 RP514 3 4 EV @0X2
+3V CLK_PCIE_ MINI4 2 5
HIGH 27MHz 1 2 To MINI4
CLK_PCIE_ MINI4# 25
PCI-4/27M_SEL PIN 17/18 LOW SRC
Pin 6 PCI-4/27M_SEL internal PD PIN 17/18 IS 27MHz IS SRC/DOT (default) R241 10 K_ 4 DRE FSSCLK_R RP512 1 2 IV @0X2
DREFSS CLK 6
DRE FSSCLK#_R 3 4 DREFSS CLK# 6 To NB
P CIF-5/ITP_EN
Pin 7 PCIF-5/ITP_EN internal PD PIN 46/47 IS CPUITP PIN 46/47 IS SRC8 (default) R230 *1 0K _4 PCLK_ICH
+3V
3 4 CLK_MXM 18
RP51
1 2
EV @0X2 CLK_MXM# 18 To VGA Card
R229 10 K_ 4
B B
FREQ. SEL TABLE Clock Gen I2C +3V
Q507 R245
R601 0_4 CLK_BSEL0 RHU002N06 10K_4

3 CPU_BSEL0 MCH_BSEL0 6
3 1 CGDA T_S MB PCLK_PCM C225 *33 p/50V_4

14,21,25,27 SDATA CG DA T_S MB 17
+1.05V R600 *56 _4
BSEL Frequency Select Table R602 1K_4 +3V

PCLK_591 C219 *33 p/50V_4
CLKUSB_48 C214
FSC FSB FSA Frequency B2A 15p /50 V_ 4
0 0 0 266Mhz R228 0_4 CLK_BSEL1

Q509 R248 14M_ICH C216 *33 p/50V_4
3 CPU_BSEL1 MCH_BSEL1 6
RHU002N06 10K_4
0 0 1 133Mhz PCLK_ICH C215 *33 p/50V_4
R226 *0_ 4 3 1 CG CLK_S MB
14,21,25,27 SCLK CG CLK_SMB 17
A A
0 1 1 166Mhz R225 1K_4
PCLK_DEB UG C224 *33 p/50V_4
+1.05V
0 1 0 200Mhz
CLK_BSEL2
1 1 0 400Mhz 3 CPU_BSEL2
R598 0_4
MCH_BSEL2 6
1 1 1 Reserved R232 *0_ 4

Quanta Computer Inc.
1 0 1 100Mhz +1.05V
R593 1K_4
PROJECT : TE1M
Size Docum ent Num ber Rev
1 0 0 333Mhz Clock Gen E3D

5 4 3 2 1
5 4 3 2 1
H_D# [0..63]
BOM Option Table
H_ D#[0 ..63] 5
5 H_A#[3..1 6]
U501A
U501B
N/A N/A
H_A#3 J4 H1 H_ADS#
A[3]# ADS# H_A DS# 5
H_A#4 L5 E2 H_BNR#
A[4]# BNR# H_B NR# 5
H_A#5 L4 G5 H_BPRI# H_D#0 E22 Y22 H_D#32
A[5]# BPRI# H_BPRI# 5 D[0]# D[32]#
H_A#6 K5 H_D#1 F24 AB24 H_D#33
H_A#7 A[6]# H_DE FER# H_D#2 D[1]# D[33]# H_D#34
M3 H5 H_ DEFE R# 5 E26 V24
H_A#8 A[7]# DEFER# H_DRDY# H_D#3 D[2]# D[34]# H_D#35
N2 F21 H_ DRDY# 5 G22 V26
H_A#9 A[8]# DRDY# H_DBSY# H_D#4 D[3]# D[35]# H_D#36
J1 E1 H_ DBSY# 5 F23 V23
H_A#10 A[9]# DBSY# H_D#5 D[4]# D[36]# H_D#37
N3 G25 T22
H_A#11 A[10]# H_BRE Q# ZS2 Default no use this function H_D#6 D[5]# D[37]# H_D#38
P5 F1 H_B REQ# 5 E25 U25
H_A#12 A[11]# BR0# H_D#7 D[6]# D[38]# H_D#39
P2 E23 U23
H_A#13 A[12]# H_IE RR# R46 56_ 4 H_D#8 D[7]# D[39]# H_D#40
L2 D20 +1.05V K24 Y25
H_A#14 A[13]# IERR# H_INIT# H_D#9 D[8]# D[40]# H_D#41
P4 B3 H_INIT# 12 G24 W 22
D
H_A#15 A[14]# INIT# H_D#10 D[9]# D[41]# H_D#42
D
P1 J24 Y23
A[15]# D[10]# D[42]#
H_A#16
H_ADS TB#0
R1
A[16]# LOCK#
H4 H_LO CK#
H_LO CK# 5 C3A H_D#11
H_D#12
J23
D[11]# D[43]#
W 24 H_D#43
H_D#44
5 H_ADS TB#0 M1 H22 W 25
ADSTB[0]# L54 BK1608LM252-T_6 H_CP URS T# H_D#13 D[12]# D[44]# H_D#45
5 H_REQ #[0 ..4] C1 H_CP URS T# 5 F26 AA23
H_RE Q#0 RESET# H_RS#0 H_D#14 D[13]# D[45]# H_D#46
K3 F3 H_ RS#0 5 K22 AA24
H_RE Q#1 REQ[0]# RS[0]# H_RS#1 near CPU side H_D#15 D[14]# D[46]# H_D#47
H2 F4 H_ RS#1 5 H23 AB25
H_RE Q#2 REQ[1]# RS[1]# H_RS#2 H_DS TB N#0 D[15]# D[47]# H_DS TB N#2
K2 G3 H_ RS#2 5 5 H_DS TB N#0 J26 Y26 H_DS TB N#2 5
H_RE Q#3 REQ[2]# RS[2]# H_TRDY# H_DS TBP#0 DSTBN[0]# DSTBN[2]# H_DS TBP#2
J3 G2 H_TRDY# 5 5 H_DS TBP#0 H26 AA26 H_DS TBP#2 5
H_RE Q#4 REQ[3]# TRDY# H_DINV#0 DSTBP[0]# DSTBP[2]# H_DINV#2
L1 5 H_DINV#0 H25 U22 H_ DINV#2 5
REQ[4]# H_HIT# DINV[0]# DINV[2]#
5 H_A#[17..35] G6 H_HIT# 5
H_A#17 HIT# H_HITM#
Y2 E4 H_HITM# 5
H_A#18 A[17]# HITM# H_D#16 H_D#48
U5 N22 AE24
H_A#19 A[18]# XDP_BPM#0 T12 H_D#17 D[16]# D[48]# H_D#49
R3 AD4 K25 AD24
H_A#20 A[19]# BPM[0]# XDP_BPM#1 T11 H_D#18 D[17]# D[49]# H_D#50
W6 AD3 P26 AA21
H_A#21 A[20]# BPM[1]# XDP_BPM#2 T3 H_D#19 D[18]# D[50]# H_D#51
U4 AD1 R23 AB22
H_A#22 A[21]# BPM[2]# XDP_BPM#3 T13 C onnect it to CPU DBR# is for ITP debug port H_D#20 D[19]# D[51]# H_D#52
Y5 AC4 L23 AB21
H_A#23 A[22]# BPM[3]# XDP_BPM#4 T2 or CPU interposer (like ICE) to reset the system H_D#21 D[20]# D[52]# H_D#53
U1 AC2 M24 AC26
H_A#24 A[23]# PRDY# XDP_BPM#5 T1 H_D#22 D[21]# D[53]# H_D#54
R4 AC1 L22 AD20
H_A#25 A[24]# PREQ# XDP_ TCK H_D#23 D[22]# D[54]# H_D#55
T5 AC5 M23 AE22
H_A#26 A[25]# TCK XDP_ TDI H_D#24 D[23]# D[55]# H_D#56
T3 AA6 P25 AF23
H_A#27 A[26]# TDI XDP_ TDO H_D#25 D[24]# D[56]# H_D#57
W2 AB3 P23 AC25
H_A#28 A[27]# TDO XDP_ TMS H_D#26 D[25]# D[57]# H_D#58
W5 AB5 P22 AE21
H_A#29 A[28]# TMS XDP_ TRS T# H_D#27 D[26]# D[58]# H_D#59
Y4 AB6 T24 AD21
H_A#30 A[29]# TRST# XDP_ DB RESE T# R44 0_4 SYS_RS T# +1.05V H_D#28 D[27]# D[59]# H_D#60
U2 C20 SYS_RS T# 14 R24 AC22
H_A#31 A[30]# DBR# H_D#29 D[28]# D[60]# H_D#61
V4 L25 AD23
H_A#32 A[31]# H_D#30 D[29]# D[61]# H_D#62
W3 T25 AF22
H_A#33 A[32]# H_D#31 D[30]# D[62]# H_D#63
AA4
A[33]#
THERMAL N25
D[31]# D[63]#
AC23
H_A#34 AB2 R81 H_DS TB N#1 L26 AE25 H_DS TB N#3
A[34]# 5 H_DS TB N#1 DSTBN[1]# DSTBN[3]# H_DS TB N#3 5
H_A#35 AA3 D21 H_PRO CHO T#_D 1K/F_4 H_DS TBP#1 M26 AF24 H_DS TBP#3
A[35]# PROCHOT# 5 H_DS TBP#1 DSTBP[1]# DSTBP[3]# H_DS TBP#3 5
H_ADS TB#1 V1 A24 H_THE RMDA H_DINV#1 N24 AC20 H_DINV#3
5 H_ADS TB#1 ADSTB[1]# THERMDA 5 H_DINV#1 DINV[1]# DINV[3]# H_ DINV#3 5
B25 H_THE RMDC
H_A20M# THERMDC H_G TLREF CO MP0 R80 2 7.4 /F_6
12 H_A20 M# A6
A20M#
AD26
GTLREF COMP[0]
R26 Layout note:
H_FE RR# A5 C7 CPU_PM_ THRMTRIP# CPU_TES T1 C23 MISC U26 CO MP1 R74 5 4.9 /F_4
12 H_FE RR# FERR# THERMTRIP# T15 TEST1 COMP[1] comp0,2: Zo=27.4ohm, L<0.5"
H_IG NNE# C4 CPU_TES T2 D25 AA1 CO MP2 R22 2 7.4 /F_6
12 H_ IG NNE# IGNNE# T17 TEST2 COMP[2] comp1,3: Zo=55ohm, L<0.5"
R75 CPU_TES T3 C24 Y1 CO MP3 R21 5 4.9 /F_4
T16 TEST3 COMP[3]
C R32 0 _4 D5 2K/F_4 CPU_TES T4 AF26 C
12 H_S TP CLK# STPCLK# T21 TEST4
H_INTR C6 H CLK CPU_TES T5 AF1 E5 ICH_ DP RS TP#
12 H_INTR LINT0 T4 TEST5 DPRSTP# ICH_ DP RS TP# 6,1 2,3 3
H_NMI B4 A22 CLK_CP U_BCLK CPU_TES T6 A26 B5 H_ DPSLP #
12 H_NMI LINT1 BCLK[0] CLK_CP U_BCLK 2 T20 TEST6 DPSLP# H_ DPSLP# 12
H_SMI# A3 A21 CLK_CP U_BCLK# CPU_TES T7 C3 D24 H_ DPW R#
12 H_S MI# SMI# BCLK[1] CLK_CP U_BCLK# 2 T5 TEST7 DPWR# H_ DPW R# 5
CP U_BSEL0 B22 D6 H_PW RG D
2 CPU_BS EL0 BSEL[0] PWRGOOD H_PW RG D 12
T6 M4 CP U_BSEL1 B23 D7 H_ CPUSLP #
RSVD[01] 2 CPU_BS EL1 BSEL[1] SLP# H_ CPUSLP# 5
T7 N5 Layout note: CP U_BSEL2 C21 AE6 PS I#
RSVD[02] 2 CPU_BS EL2 BSEL[2] PSI# PS I# 33
T8 T2 H_GTLREF: Zo=55 ohm,L<0.5"
RSVD[03]
T9 V3
RSVD[04]
2/3*VCCP+-2% Penryn_1p0 B2A
T502 B2
T501 RSVD[05]
D2
T14 RSVD[06] Layout note:
D22
T500 RSVD[07]
D3 ICH_DPRSTP# , Daisy Chain
T10 RSVD[08]
F6 (SB>PowerIC>NB>CPU)
RSVD[09]
Penryn_1p0
Thermal Trip +1.05V +1.05V

XDP CPU Thermal monitor
+1.05V
+3V +3V +3V
2 Q5 R40 D2 Reserve 1K for XDP function +1.05V

6,14,33 DELAY_VR_PW RG OO D
R31 R50 2 00_6 LM86VCC C68 0 .1u /10V_ 4
FDV301N *1 0K _4 *BAS316 XDP_ TDO R23 *51/F_4
*51/F_4 XDP_ TDI R24 5 6_4
B B
XDP_ TMS R19 5 4.9 /F_4 Q11 R92 R91 C3A MSOP8
22,28 2ND_ MBCLK 3 1
B2A XDP_ TCK R25 5 6_4 10K_4 10K_4
+1.05V C3A R39 H_CPURS T# XDP_ TRS T# R20 5 6_4 RHU002N06 U503
R41 H_ THE RMDA
1K_4 2ND_ MB CLK# 8 1
10 0K _4 SCLK VCC
R37 Reserve 1K for XDP function 3 1 2ND_MB DA TA# 7 2 C560
22,28 2ND_ MBDA TA SDA DXP
Q6
56.2/F_4 MMB T3904 Q10 RHU002N06 6 3 22 00p/50V_4
ALERT# DXN
CPU_P M_ THRMTRIP# 1 3 SYS _ SHDN# 4 5 H_THE RMDC
SYS_S HDN# 32 OVERT# GND
B2A
NS LM95245 PU this pin L M95 245
R38 *0_4 PM_ THRMTRIP# R93 1 0K _4
PM_THRMTRIP# 6,12 +3V
ADDRESS: 98H
CPU FAN CTRL LM95245 : AL095245000

R97 *0_4 THERM_ALERT#_R
14 THERM_ALERT#
No use Thermal trip CPU side still PU 56ohm.
Use Thermal trip can share PU at SB side
R49 1 0K _4
+3V
R79 3 30_4
+3V
Processor hot +3V
3 1 TH ER _SHD#
32 SYS_SHDN#
Q7 MMB T3904
+1.05V R95
B2A
No use PROCHOT CPU side still PU 56ohm. 10K_4
Use PROCHOT to optional receiver CPU side PU C62
+5V CN504
R48 68ohm and through isolat 2.2K ohm to receiver 28 FANS IG FA NSIG *1 u/1 6V _6
A side U502 A
5 6_4 C89 2.2u/6.3V _6 2 3 TH_FA N_POW ER
VIN VO 1
5
GND 2
R51 *2.2K_4 R94 0_4 1 6
18 SYS FANO N# /FON GND C87 C90 C91 3
7
H_PRO CHO T#_D R57 *0_ 4 GND
4 8
H_P ROCHO T# 33 28 VFAN VSET GND 10u/10V_8 0.0 1u/16V_ 4 *0 .01 u/16V _ 4
G995 FA N_CON
FANPW R = 1.6*VSET B2A

PROJECT : TE1M
S ize Docum ent Num ber R ev
E3D
CPU(1/2)- Host Bus
D ate: Monday, May 26, 2008 S heet 3 of 40
5 4 3 2 1
5 4 3 2 1
BOM Option Table

N/A N/A
Need NC 20PCS 10u before A1 BOM released(A0 all stuff)
Place these parts reference Layout Note:

D to Intel demo board. VCC_CORE D
Inside CPU center cavity in 2 rows
U501D
A4 P6 VCC_CORE VCC_CORE
VSS[001] VSS[082]
A8 P21
VSS[002] VSS[083] U501C
A11 P24
VSS[003] VSS[084] +1.05V
A14 R2 A7 AB20
VSS[004] VSS[085] VCC[001] VCC[068]
A16 R5 A9 AB7
VSS[005] VSS[086] C548 C530 C37 C529 C42 C533 C536 C51 C61 VCC[002] VCC[069]
A19 R22 A10 AC7
VSS[006] VSS[087] VCC[003] VCC[070]
A23 R25 A12 AC9
VSS[007] VSS[088] 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 VCC[004] VCC[071]
AF2 T1 A13 AC12
VSS[008] VSS[089] VCC[005] VCC[072] C33 C65 C64
B6 T4 A15 AC13
VSS[009] VSS[090] VCC[006] VCC[073]
B8 T23 A17 AC15
VSS[010] VSS[091] VCC[007] VCC[074] 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
B11 T26 A18 AC17
VSS[011] VSS[092] VCC_CORE VCC[008] VCC[075]
B13 U3 A20 AC18
VSS[012] VSS[093] VCC[009] VCC[076]
B16 U6 B7 AD7
VSS[013] VSS[094] VCC[010] VCC[077]
B19 U21 B9 AD9
VSS[014] VSS[095] VCC[011] VCC[078]
B21 U24 B10 AD10
VSS[015] VSS[096] VCC[012] VCC[079]
B24 V2 B12 AD12
VSS[016] VSS[097] VCC[013] VCC[080] +1.05V
C5 V5 B14 AD14
VSS[017] VSS[098] VCC[014] VCC[081]
C8 V22 B15 AD15
C11 V25 B17 AD17
VSS[019] VSS[100] VCC[016] VCC[083]
C14 W1 B18 AD18
VSS[020] VSS[101] 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 VCC[017] VCC[084]
C16 W4 B20 AE9
VSS[021] VSS[102] VCC[018] VCC[085] C35 C34 C66
C19 W23 C9 AE10
VSS[022] VSS[103] VCC[019] VCC[086]
C2 W26 C10 AE12
VSS[023] VSS[104] VCC[020] VCC[087] 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
C22 Y3 C12 AE13
VSS[024] VSS[105] VCC_CORE VCC[021] VCC[088]
C25 Y6 C13 AE15
VSS[025] VSS[106] VCC[022] VCC[089]
D1 Y21 C15 AE17
VSS[026] VSS[107] VCC[023] VCC[090]
D4 Y24 C17 AE18
VSS[027] VSS[108] VCC[024] VCC[091]
D8 AA2 C18 AE20
VSS[028] VSS[109] VCC[025] VCC[092]
C
D11 AA5 D9 AF9 C
VSS[029] VSS[110] VCC[026] VCC[093]
D13 AA8 D10 AF10
VSS[030] VSS[111] VCC[027] VCC[094]
D16 AA11 D12 AF12
D19 AA14 D14 AF14
VSS[032] VSS[113] VCC[029] VCC[096]
D23 AA16 D15 AF15
VSS[033] VSS[114] 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 VCC[030] VCC[097] +1.05V
D26 AA19 D17 AF17
VSS[034] VSS[115] VCC[031] VCC[098]
E3 AA22 D18 AF18
VSS[035] VSS[116] VCC[032] VCC[099]
E6
VSS[036] VSS[117]
AA25 E7
VCC[033] VCC[100]
AF20 +1.04V
E8 AB1 E9
VSS[037] VSS[118] VCC_CORE VCC[034] CPU_G21 R42 0_4
E11 AB4 E10 G21
VSS[038] VSS[119] VCC[035] VCCP[01]
E14 AB8 E12 V6
VSS[039] VSS[120] VCC[036] VCCP[02]
E16 AB11 E13 J6
VSS[040] VSS[121] VCC[037] VCCP[03] + C58
E19 AB13 E15 K6
E21
VSS[041] VSS[122]
AB16 E17
VCC[038] VCCP[04]
M6 VCCP Bulk CAP
VSS[042] VSS[123] VCC[039] VCCP[05]
E24 AB19 E18 J21 330u/2.5V_7343 close to Pin
VSS[043] VSS[124] VCC[040] VCCP[06]
F5 AB23 E20 K21
VSS[044] VSS[125] C540 C538 C531 C549 C541 C537 C542 C539 C550 VCC[041] VCCP[07]
F8 AB26 F7 M21
VSS[045] VSS[126] VCC[042] VCCP[08]
F11 AC3 F9 N21
VSS[046] VSS[127] 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 VCC[043] VCCP[09]
F13 AC6 F10 N6
VSS[047] VSS[128] VCC[044] VCCP[10]
F16 AC8 F12 R21
VSS[048] VSS[129] VCC[045] VCCP[11]
F19 AC11 F14 R6
VSS[049] VSS[130] VCC[046] VCCP[12]
F2 AC14 F15 T21
VSS[050] VSS[131] VCC[047] VCCP[13] +1.5V
F22 AC16 F17 T6
VSS[051] VSS[132] VCC[048] VCCP[14]
F25 AC19 F18 V21
VSS[052] VSS[133] VCC[049] VCCP[15]
+1.04V
G4 AC21 VCC_CORE F20 W21
VSS[053] VSS[134] VCC[050] VCCP[16]
G1 AC24 AA7
VSS[054] VSS[135] VCC[051] +VCCA_PROC R76 0_6
G23 AD2 AA9 B26
VSS[055] VSS[136] VCC[052] VCCA[01]
G26 AD5 AA10 C26
VSS[056] VSS[137] VCC[053] VCCA[02]
H3 AD8 AA12
VSS[057] VSS[138] C54 C55 VCC_CORE Bulk CAPs place VCC[054] C71 C79
H6 AD11 AA13 AD6 H_VID0 33
VSS[058] VSS[139] VCC[055] VID[0]
H21 AD13 + + to BOT of CPU centeral AA15 AF5
VSS[059] VSS[140] VCC[056] VID[1] H_VID1 33
B H24 AD16 330u/2V_7343 330u/2V_7343 AA17 AE5 0.01u/16V_4 10u/10V_8 B
VSS[060] VSS[141] VCC[057] VID[2] H_VID2 33 Place 0.01u
J2 AD19 AA18 AF4 H_VID3 33
VSS[061] VSS[142] VCC[058] VID[3]
J5 AD22 AA20 AE3 H_VID4 33
near pin-B26
VSS[062] VSS[143] VCC[059] VID[4]
J22 AD25 AB9 AF3 H_VID5 33
VSS[063] VSS[144] VCC[060] VID[5]
J25
VSS[064] VSS[145]
AE1 Power require C3A AC10
VCC[061] VID[6]
AE2 H_VID6 33
K1 AE4 AB10
VSS[065] VSS[146] VCC[062]
K4 AE8 AB12
VSS[066] VSS[147] VCC[063]
K23 AE11 AB14 AF7
VSS[067] VSS[148] VCC[064] VCCSENSE
K26 AE14 AB15
VSS[068] VSS[149] VCC[065]
L3 AE16 AB17
VSS[069] VSS[150] VCC[066]
L6 AE19 AB18 AE7
VSS[070] VSS[151] VCC[067] VSSSENSE VCC_CORE
L21 AE23
VSS[071] VSS[152] Penryn_1p0
L24 AE26
VSS[072] VSS[153] Layout Note:
M2 A2 .
VSS[073] VSS[154] R512 Route VCCSENSE and VSSSENSE traces at
M5 AF6
Penryn CPU Power Status and max current table
VSS[074] VSS[155] 27.4 Ohms with 50 mil spacing.
M22 AF8
VSS[075] VSS[156] 100/F _6
M25 AF11 Place PU and PD within 1 inch of CPU.
VSS[076] VSS[157]
N1 AF13 POWER PLANE S0
N4
VSS[077] VSS[158]
AF16
S3 S4/S5 Voltage I(max) Note
VSS[078] VSS[159]
N23 AF19 VCC_CORE O X X VID 47A Standard Voltage CPU VCCSENSE 33
VSS[079] VSS[160]
N26 AF21
VSS[080] VSS[161]
P3 A25 VCC_CORE O X X VID 50A SV Design Target VSSSENSE 33
VSS[081] VSS[162]
AF25
VSS[163]
VCC_CORE O X X VID TBD Extreme Edition CPU
Penryn_1p0 R511
. VCC_CORE O X X VID 67A EE Design Target
100/F _6
VCCA O X X +1.5V 130mA
VCCP O X X +1.05V 4.5A Before VCC Stable

A A
VCCP O X X +1.05V 2.5A After VCC Stable
(See Penryn EMTS Rev:1.0 Table7,8 for voltage and current)

(See Penryn EMTS Rev:1.0 Table-3 for VID table)
PROJECT : TE1M
Size Document Number Rev
E3D
CPU(2/2)- Power
D ate: Monday, May 26, 2008 Sheet 4 of 40
5 4 3 2 1
5 4 3 2 1
BOM Option Table

EV_IV@ EV&IV diff. BOM
H_A#[35..3] 3
U504A
3 H_D#[63..0]
A14 H_A#3
H_D#0 H_A#_3 H_A#4
F2 C15
H_D#1 H_D#_0 H_A#_4 H_A#5
G8 F16
H_D#2 H_D#_1 H_A#_5 H_A#6
F8 H13
D H_D#3 H_D#_2 H_A#_6 H_A#7 D
E6 H_D#_3 H_A#_7 C18
H_D#4 G2 M16 H_A#8
H_D#5 H_D#_4 H_A#_8 H_A#9
H6 H_D#_5 H_A#_9 J13
H_D#6 H2 P16 H_A#10
H_D#7 H_D#_6 H_A#_10 H_A#11
F6 R16
H_D#8 H_D#_7 H_A#_11 H_A#12
D4 N17
H_D#9 H_D#_8 H_A#_12 H_A#13
H3 H_D#_9 H_A#_13 M13
H_D#10 M9 E17 H_A#14
H_D#11 H_D#_10 H_A#_14 H_A#15
M11 H_D#_11 H_A#_15 P17
H_D#12 J1 F17 H_A#16
H_D#13 H_D#_12 H_A#_16 H_A#17
J2 H_D#_13 H_A#_17 G20
H_D#14 N12 B19 H_A#18
H_D#15 H_D#_14 H_A#_18 H_A#19
J6 H_D#_15 H_A#_19 J16
H_D#16 P2 E20 H_A#20
H_D#17 H_D#_16 H_A#_20 H_A#21
L2 H_D#_17 H_A#_21 H16
+1.05V_VCCP_GMCH 0.3125*VCCP H_D#18 R2 J20 H_A#22
H_D#19 H_D#_18 H_A#_22 H_A#23
W:10,S:20 , L<0.5" N9 H_D#_19 H_A#_23 L17
H_D#20 L6 A17 H_A#24
H_D#21 H_D#_20 H_A#_24 H_A#25
M5 B17
H_D#22 H_D#_21 H_A#_25 H_A#26
J3 L16
R532 H_D#23 H_D#_22 H_A#_26 H_A#27
N2 H_D#_23 H_A#_27 C21
H_D#24 R1 J17 H_A#28
221/F_4 H_D#25 H_D#_24 H_A#_28 H_A#29
N5 H20
H_D#26 H_D#_25 H_A#_29 H_A#30
N6 B18
H_SW ING H_D#27 H_D#_26 H_A#_30 H_A#31
P13 K17
H_D#28 H_D#_27 H_A#_31 H_A#32
N8 H_D#_28 H_A#_32 B20
C H_D#29 H_A#33 C
L7 H_D#_29 H_A#_33 F21
R531 C568 H_D#30 N10 K21 H_A#34
H_D#31 H_D#_30 H_A#_34 H_A#35
M3 L20
100/F_4 0.1u/10V_4 H_D#32 H_D#_31 H_A#_35
Y3 H_D#_32
H_D#33 AD14 H12 H_ADS#
H_D#_33 H_ADS# H_ADS# 3
H_D#34 Y6 B16 H_ADSTB#0
H_D#_34 H_ADSTB#_0 H_ADSTB#0 3
H_D#35 Y10 G17 H_ADSTB#1
H_D#_35 H_ADSTB#_1 H_ADSTB#1 3
H_D#36 Y12 A9 H_BNR#
H_D#_36 H_BNR# H_BNR# 3
H_D#37 Y14 F11 H_BPRI#
H_D#_37 H_BPRI# H_BPRI# 3
H_D#38 Y7 G12 H_BREQ#
H_D#_38 H_BREQ# H_BREQ# 3
H_D#39 W2 E9 H_DEFER#
H_D#_39 H_DEFER# H_DEFER# 3
H_D#40 AA8 B10 H_DBSY#
H_D#_40 H_DBSY# H_DBSY# 3
H_D#41 Y9 AH7 CLK_MCH_BCLK
H_D#_41 HPLL_CLK CLK_MCH_BCLK 2
W:10,S:20 , L<0.5" H_D#42 AA13 AH6 CLK_MCH_BCLK#
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# 2
H_D#43 AA9 J11 H_DPW R#
H_D#_43 H_DPWR# H_DPW R# 3
H_D#44 AA11 F9 H_DRDY#
H_D#_44 H_DRDY# H_DRDY# 3
H_D#45 AD11 H9 H_HIT#
H_D#_45 H_HIT# H_HIT# 3
H_D#46 AD10 E12 H_HITM#
H_D#_46 H_HITM# H_HITM# 3
H_RCOMP H_D#47 AD13 H11 H_LOCK#
H_D#_47 H_LOCK# H_LOCK# 3
H_D#48 AE12 C9 H_TRDY#
H_D#_48 H_TRDY# H_TRDY# 3
H_D#49 AE9
R108 H_D#50 H_D#_49
AA2 H_D#_50
H_D#51 AD8
24.9/F_4 H_D#52 H_D#_51
AA3 H_DINV#[3..0] 3
H_D#53 H_D#_52 H_DINV#0
AD3 J8
H_D#54 H_D#_53 H_DINV#_0 H_DINV#1
AD7 H_D#_54 H_DINV#_1 L3
B H_D#55 H_DINV#2 B
AE14 Y13
H_D#56 H_D#_55 H_DINV#_2 H_DINV#3
AF3 H_D#_56 Y1
H_D#57 H_DINV#_3
AC1 H_DSTBN#[3..0] 3
H_D#58 H_D#_57 H_DSTBN#0
AE3 H_D#_58 H_DSTBN#_0 L10
H_D#59 AC3 M7 H_DSTBN#1
H_D#60 H_D#_59 H_DSTBN#_1 H_DSTBN#2
AE11 H_D#_60 H_DSTBN#_2 AA5
H_D#61 AE8 AE6 H_DSTBN#3
H_D#62 H_D#_61 H_DSTBN#_3
AG2 H_D#_62 H_DSTBP#[3..0] 3
H_D#63 AD6 L9 H_DSTBP#0
+1.05V_VCCP_GMCH H_D#_63 H_DSTBP#_0 H_DSTBP#1
2/3*VCCP H_DSTBP#_1 M8
AA6 H_DSTBP#2
W:10,S:20 , L<0.5" H_SW ING H_DSTBP#_2 H_DSTBP#3
C5 AE5
H_RCOMP H_SWING H_DSTBP#_3
E3 H_REQ#[4..0] 3
R534 H_RCOMP H_REQ#0
H_REQ#_0 B15
K13 H_REQ#1
1K/F_4 H_REQ#_1 H_REQ#2
F13
H_REQ#_2 H_REQ#3
B13
H_AVREF H_CPURST# H_REQ#_3 H_REQ#4
3 H_CPURST# C12 H_CPURST# H_REQ#_4 B14
H_CPUSLP# E11
3 H_CPUSLP# H_CPUSLP# H_RS#[2..0] 3
B6 H_RS#0
R536 R535 0_4 H_DVREF H_RS#_0 H_RS#1
F12
H_RS#_1 H_RS#2
H_RS#_2 C8
2K/F_4 H_AVREF A11
H_DVREF H_AVREF
B11 H_DVREF
EV_IV@CANTIGA_1p2
A A
H_CPURST#
GM PN=> AJSLB940T05
C802
PM PN=> AJSLB970T03 Quanta Computer Inc.
*0.1u/10V_4
B2A PROJECT : TE1M
E3D
NB (1/7)- HOST
5 4 3 2 1
5 4 3 2 1
BOM Option Table
U504B Reference Description

IV@ INT VGA
MCH_RSVD1 M36
T69 RSVD1
MCH_RSVD2 N36 AP24 M_CLK_DDR0
T76 RSVD2 SA_CK_0 M_CLK_DDR0 17 EV@ EXT VGA
MCH_RSVD3 R33 AT21 M_CLK_DDR1
T73 RSVD3 SA_CK_1 M_CLK_DDR1 17
MCH_RSVD4 T33 AV24 M_CLK_DDR3
T67 RSVD4 SB_CK_0 M_CLK_DDR3 17 IHM@ INT HDMI
MCH_RSVD5 AH9 AU20 M_CLK_DDR4 GM PN=> AJSLB940T05
T38 RSVD5 SB_CK_1 M_CLK_DDR4 17
MCH_RSVD6 AH10 EV_IV@ EV&IV diff. BOM
T39 RSVD6 PM PN=> AJSLB970T03
MCH_RSVD7 AH12 AR24 M_CLK_DDR#0
T41 RSVD7 SA_CK#_0 M_CLK_DDR#0 17
MCH_RSVD8 AH13 AR21 M_CLK_DDR#1
T43 RSVD8 SA_CK#_1 M_CLK_DDR#1 17
MCH_RSVD9 K12 AU24 M_CLK_DDR#3
T40 RSVD9 SB_CK#_0 M_CLK_DDR#3 17
AV20 M_CLK_DDR#4
SB_CK#_1 M_CLK_DDR#4 17
BC28 M_CKE0
SA_CKE_0 M_CKE0 16,17
AY28 M_CKE1 U504C
SA_CKE_1 M_CKE1 16,17
MCH_RSVD14 T24 AY36 M_CKE3 L<0.5" , If PCIE not support
T52 RSVD14 SB_CKE_0 M_CKE3 16,17 +1.05V_VCC_PEG
BB36 M_CKE4 LVDS I/F still connect to +VCC_PEG
SB_CKE_1 M_CKE4 16,17
D MCH_RSVD15 B31 D
T60 RSVD15
BA17 M_CS#0 INT_LVDS_PWM L32
SA_CS#_0 M_CS#0 16,17 19 INT_LVDS_PWM L_BKLT_CTRL
MCH_RSVD17 M1 AY16 M_CS#1 INT_LVDS_BLON G32 T37 EXP_A_COMPX R204 49.9/F_4
T24 RSVD17 SA_CS#_1 M_CS#1 16,17 19 INT_LVDS_BLON L_BKLT_EN PEG_COMPI
AV16 M_CS#2 L_CTRL_CLK M32 T36
SB_CS#_0 M_CS#2 16,17 L_CTRL_CLK PEG_COMPO
AR13 M_CS#3
SB_CS#_1 M_CS#3 16,17
MCH_RSVD20 AY21 L_CTRL_DATA M33
T50 RSVD20 L_CTRL_DATA PEG_RXN[15:0] 18
BD17 M_ODT0 INT_LVDS_EDIDCLK K33 H44 PEG_RXN0
SA_ODT_0 M_ODT0 16,17 19 INT_LVDS_EDIDCLK L_DDC_CLK PEG_RX#_0
AY17 M_ODT1 INT_LVDS_EDIDDATA J33 J46 PEG_RXN1
SA_ODT_1 M_ODT1 16,17 11,19 INT_LVDS_EDIDDATA L_DDC_DATA PEG_RX#_1
MCH_RSVD21 B2 BF15 M_ODT2 L44 PEG_RXN2
T27 RSVD21 SB_ODT_0 M_ODT2 16,17 PEG_RX#_2
MCH_RSVD22 BG23 AY13 M_ODT3 L40 PEG_RXN3
T54 RSVD22 SB_ODT_1 M_ODT3 16,17 PEG_RX#_3
MCH_RSVD23 BF23 INT_LVDS_DIGON M29 N41 PEG_RXN4
T51 RSVD23 19 INT_LVDS_DIGON L_VDD_EN PEG_RX#_4
MCH_RSVD24 BH18 BG22 M_RCOMP LVDS_IBG C44 P48 PEG_RXN5
T506 RSVD24 SM_RCOMP LVDS_IBG PEG_RX#_5
MCH_RSVD25 BF18 BH21 M_RCOMP# LVDS_VBG B43 N44 PEG_RXN6
T42 RSVD25 SM_RCOMP# T85 LVDS_VBG PEG_RX#_6
LVDS_VREFH E37 T43 PEG_RXN7
SM_RCOMP_VOH LVDS_VREFL LVDS_VREFH PEG_RX#_7 PEG_RXN8
BF28 E38 U43
SM_RCOMP_VOH SM_RCOMP_VOL INT_TXLCLKOUT- LVDS_VREFL PEG_RX#_8 PEG_RXN9
BH28 19 INT_TXLCLKOUT- C41 Y43
SM_RCOMP_VOL INT_TXLCLKOUT+ LVDSA_CLK# PEG_RX#_9 PEG_RXN10
19 INT_TXLCLKOUT+ C40 Y48
SM_VREF INT_TXUCLKOUT- LVDSA_CLK PEG_RX#_10 PEG_RXN11
AV42 T65 B37 Y36
SM_VREF SM_PW ROK INT_TXUCLKOUT+ LVDSB_CLK# PEG_RX#_11 PEG_RXN12
AR36 T71 A37 AA43
SM_PW ROK SM_REXT SM_DRAMRST# only for LVDSB_CLK PEG_RX#_12 PEG_RXN13
BF17 AD37
SM_REXT MCH_SM_DRAMRST# DDR3.(DDR2 NC). INT_TXLOUT0- PEG_RX#_13 PEG_RXN14
BC36 T77 19 INT_TXLOUT0- H47 AC47
SM_DRAMRST# INT_TXLOUT1- LVDSA_DATA#_0 PEG_RX#_14 PEG_RXN15
19 INT_TXLOUT1- E46 AD39
DREFCLK INT_TXLOUT2- LVDSA_DATA#_1 PEG_RX#_15
B38 DREFCLK 2 19 INT_TXLOUT2- G40 PEG_RXP[15:0] 18
DPLL_REF_CLK DREFCLK# INT_TXLOUT3- LVDSA_DATA#_2 PEG_RXP0
A38 DREFCLK# 2 T74 A40 H43
DPLL_REF_CLK# DREFSSCLK LVDSA_DATA#_3 PEG_RX_0 PEG_RXP1
E41 DREFSSCLK 2 J44
DPLL_REF_SS CLK DREFSSCLK# INT_TXLOUT0+ PEG_RX_1 PEG_RXP2
F41 DREFSSCLK# 2 19 INT_TXLOUT0+ H48 L43
DPLL_REF_SSCLK# INT_TXLOUT1+ LVDSA_DATA_0 PEG_RX_2 PEG_RXP3
19 INT_TXLOUT1+ D45 L41
CLK_PCIE_3GPLL INT_TXLOUT2+ LVDSA_DATA_1 PEG_RX_3 PEG_RXP4
F43 CLK_PCIE_3GPLL 2 19 INT_TXLOUT2+ F40 N40
JTAG_TCK PEG_CLK CLK_PCIE_3GPLL# INT_TXLOUT3+ LVDSA_DATA_2 PEG_RX_4 PEG_RXP5
T68 AL34 E43 CLK_PCIE_3GPLL# 2 T78 B40 P47
ME_JTAG_TCK PEG_CLK# LVDSA_DATA_3 PEG_RX_5 PEG_RXP6
N43
JTAG_TDI INT_TXUOUT0- PEG_RX_6 PEG_RXP7
T70 AK34 T84 A41 T42
ME_JTAG_TDI INT_TXUOUT1- LVDSB_DATA#_0 PEG_RX_7 PEG_RXP8
DMI_TXN[3:0] 13 T83 H38 U42
JTAG_TDO DMI_TXN0 INT_TXUOUT2- LVDSB_DATA#_1 PEG_RX_8 PEG_RXP9
T66 AN35 AE41 T75 G37 Y42
ME_JTAG_TDO DMI_RXN_0 DMI_TXN1 INT_TXUOUT3- LVDSB_DATA#_2 PEG_RX_9 PEG_RXP10
AE37 T86 J37 W47
JTAG_TMS DMI_RXN_1 DMI_TXN2 LVDSB_DATA#_3 PEG_RX_10 PEG_RXP11
T80 AM35 AE47 Y37
ME_JTAG_TMS DMI_RXN_2 DMI_TXN3 INT_TXUOUT0+ PEG_RX_11 PEG_RXP12
AH39 T79 B42 AA42
DMI_RXN_3 INT_TXUOUT1+ LVDSB_DATA_0 PEG_RX_12 PEG_RXP13
DMI_TXP[3:0] 13 T82 G38 AD36
DMI_TXP0 INT_TXUOUT2+ LVDSB_DATA_1 PEG_RX_13 PEG_RXP14
AE40 T72 F37 AC48
MCH_BSEL0 DMI_RXP_0 DMI_TXP1 INT_TXUOUT3+ LVDSB_DATA_2 PEG_RX_14 PEG_RXP15
2 MCH_BSEL0 T25 AE38 T81 K37 AD40
MCH_BSEL1 CFG_0 DMI_RXP_1 DMI_TXP2 LVDSB_DATA_3 PEG_RX_15
2 MCH_BSEL1 R25 AE48 PEG_TXN[15:0] 18
MCH_BSEL2 CFG_1 DMI_RXP_2 DMI_TXP3 C_PEG_TXN0 C690 EV@0.1u/10V_4 PEG_TXN0
2 MCH_BSEL2 P25 AH40 J41
MCH_CFG_3 CFG_2 DMI_RXP_3 PEG_TX#_0 C_PEG_TXN1 C692 EV@0.1u/10V_4 PEG_TXN1
T46 P20 DMI_RXN[3:0] 13 M46
MCH_CFG_4 CFG_3 DMI_RXN0 INT_TV_COMP PEG_TX#_1 C_PEG_TXN2 C688 EV@0.1u/10V_4 PEG_TXN2
T58 P24 AE35 TV IF (Disable) F25 M47
C
MCH_CFG_5 CFG_4 DMI_TXN_0 DMI_RXN1 INT_TV_Y/G TVA_DAC PEG_TX#_2 C_PEG_TXN3 C686 EV@0.1u/10V_4 PEG_TXN3 C
11 MCH_CFG_5 C25 AE43 H25 M40
MCH_CFG_6 CFG_5 DMI_TXN_1 DMI_RXN2 INT_TV_C/R TVB_DAC PEG_TX#_3 C_PEG_TXN4 C654 EV@0.1u/10V_4 PEG_TXN4
11 MCH_CFG_6 N24 AE46 K25 M42
MCH_CFG_7 CFG_6 DMI_TXN_2 DMI_RXN3 TVC_DAC PEG_TX#_4 C_PEG_TXN5 C681 EV@0.1u/10V_4 PEG_TXN5
11 MCH_CFG_7 M24 AH42 R48
MCH_CFG_8 CFG_7 DMI_TXN_3 INT_TV_RNT PEG_TX#_5 C_PEG_TXN6 C663 EV@0.1u/10V_4 PEG_TXN6
T48 E21 DMI_RXP[3:0] 13 H24 N38
MCH_CFG_9 CFG_8 DMI_RXP0 TV_RTN PEG_TX#_6 C_PEG_TXN7 C656 EV@0.1u/10V_4 PEG_TXN7
11 MCH_CFG_9 C23 AD35 T40
MCH_CFG_10 CFG_9 DMI_TXP_0 DMI_RXP1 PEG_TX#_7 C_PEG_TXN8 C644 EV@0.1u/10V_4 PEG_TXN8
11 MCH_CFG_10 C24 AE44 U37
MCH_CFG_11 CFG_10 DMI_TXP_1 DMI_RXP2 PEG_TX#_8 C_PEG_TXN9 C646 EV@0.1u/10V_4 PEG_TXN9
T45 N21 AF46 U40
MCH_CFG_12 CFG_11 DMI_TXP_2 DMI_RXP3 TV_DCONSEL_0 PEG_TX#_9 C_PEG_TXN10 C673 EV@0.1u/10V_4 PEG_TXN10
11 MCH_CFG_12 P21 AH43 C31 Y40
MCH_CFG_13 CFG_12 DMI_TXP_3 TV_DCONSEL_1 TV_DCONSEL_0 PEG_TX#_10 C_PEG_TXN11 C649 EV@0.1u/10V_4 PEG_TXN11
11 MCH_CFG_13 T21 E32 AA46
MCH_CFG_14 CFG_13 TV_DCONSEL_1 PEG_TX#_11 C_PEG_TXN12 C678 EV@0.1u/10V_4 PEG_TXN12
T47 R20 AA37
MCH_CFG_15 CFG_14 PEG_TX#_12 C_PEG_TXN13 C651 EV@0.1u/10V_4 PEG_TXN13
T44 M20 AA40
11 MCH_CFG_16 L21 AD43
T49 H21 AC46
MCH_CFG_18 CFG_17 PEG_TX#_15
T59 P29 PEG_TXP[15:0] 18
MCH_CFG_19 CFG_18 INT_CRT_BLU C_PEG_TXP0 C691 EV@0.1u/10V_4 PEG_TXP0
11 MCH_CFG_19 R28 CRT I/F 20 INT_CRT_BLU E28 J42
MCH_CFG_20 CFG_19 CRT_BLUE PEG_TX_0 C_PEG_TXP1 C693 EV@0.1u/10V_4 PEG_TXP1
11 MCH_CFG_20 T28 B33 L46
CFG_20 GFX_VID_0 INT_CRT_GRN PEG_TX_1 C_PEG_TXP2 C689 EV@0.1u/10V_4 PEG_TXP2
B32 20 INT_CRT_GRN G28 M48
GFX_VID_1 CRT_GREEN PEG_TX_2 C_PEG_TXP3 C687 EV@0.1u/10V_4 PEG_TXP3
G33 M39
GFX_VID_2 INT_CRT_RED PEG_TX_3 C_PEG_TXP4 C655 EV@0.1u/10V_4 PEG_TXP4
F33 20 INT_CRT_RED J28 M43
R126 0_4 PM_SYNC#_R GFX_VID_3 CRT_RED PEG_TX_4 C_PEG_TXP5 C682 EV@0.1u/10V_4 PEG_TXP5
14 PM_SYNC# R29 E33 R47
R533 0_4 ICH_DPRSTP#_R PM_SYNC# GFX_VID_4 CRT_IRTN PEG_TX_5 C_PEG_TXP6 C664 EV@0.1u/10V_4 PEG_TXP6
3,12,33 ICH_DPRSTP# B7 G29 N37
PM_EXTTS#0 R183 0_4 PM_EXTTS#0_1_EC_R PM_DPRSTP# CRT_IRTN PEG_TX_6 C_PEG_TXP7 C657 EV@0.1u/10V_4 PEG_TXP7
17 PM_EXTTS#0 N33 T39
PM_EXTTS#1 R178 0_4 TS#DIMM0_1_R PM_EXT_TS#_0 INT_CRT_DDCCLK PEG_TX_7 C_PEG_TXP8 C645 EV@0.1u/10V_4 PEG_TXP8
17 PM_EXTTS#1 P32 20 INT_CRT_DDCCLK H32 U36
R207 0_4 PM_EXT_TS#_1 INT_CRT_DDCDAT CRT_DDC_CLK PEG_TX_8 C_PEG_TXP9 C642 EV@0.1u/10V_4 PEG_TXP9
3,14,33 DELAY_VR_PWRGOOD AT40 C34 20 INT_CRT_DDCDAT J32 U39
R114 100_4 RST_IN#_MCH PW ROK GFX_VR_EN INT_HSYNCR163 IV@30.1/F_4 HSYNC_G CRT_DDC_DATA PEG_TX_9 C_PEG_TXP10 C674 EV@0.1u/10V_4 PEG_TXP10
13 PLT_RST#_NB AT11 20 INT_HSYNC J29 Y39
R120 *0_4 THRMTRIP#_R RSTIN# CRTIREF CRT_HSYNC PEG_TX_10 C_PEG_TXP11 C650 EV@0.1u/10V_4 PEG_TXP11
3,12 PM_THRMTRIP# T20 E29 Y46
R138 0_4 DPRSLPVR_R THERMTRIP# INT_VSYNCR165 IV@30.1/F_4 VSYNC_G CRT_TVO_IREF PEG_TX_11 C_PEG_TXP12 C679 EV@0.1u/10V_4 PEG_TXP12
14,33 PM_DPRSLPVR R32 20 INT_VSYNC L29 AA36
DPRSLPVR CRT_VSYNC PEG_TX_12 C_PEG_TXP13 C652 EV@0.1u/10V_4 PEG_TXP13
AA39
CL_CLK0 PEG_TX_13 C_PEG_TXP14 C662 EV@0.1u/10V_4 PEG_TXP14
CL_CLK
AH37 CL_CLK0 14 For IV @ Connect to 30.1ohm PEG_TX_14
AD42
AH36 CL_DATA0 HSYNC/VSYNC serial R place close to NB AD46 C_PEG_TXP15 C684 EV@0.1u/10V_4 PEG_TXP15
CL_DATA CL_DATA0 14 For EV@ NC PEG_TX_15
T512 TP_MCH_NC1 BG48 AN36 MPW ROK
NC_1 CL_PW ROK MPW ROK 14
NB Thermal trip pin T513 TP_MCH_NC2 BF48 AJ35 CL_RST#0
NC_2 CL_RST# CL_RST#0 14
No use Thermal trip NB side can T516 TP_MCH_NC3 BD48 AH34 MCH_CLVREF_R EV_IV@CANTIGA_1p2
NC.(NB has ODT) T515 TP_MCH_NC4 NC_3 CL_VREF
BC48
TP_MCH_NC5 NC_4
T511 BH47
TP_MCH_NC6 NC_5 DDPC_CTRL f or HDMI port C
T89 BG47
PM_DPRSTP# TP_MCH_NC7 NC_6 DDPC_CTRLCLK SDVO_CTRL for HDMI port B
T514 BE47 N28 T57
The Daisy chain topology should TP_MCH_NC8 NC_7 DDPC_CTRLCLK DDPC_CTRLDATA
T510 BH46 M28 DDPC_CTRLDATA 11
be routed from ICH9M to IMVP , T88 TP_MCH_NC9 NC_8 DDPC_CTRLDATA SDVO_CTRLCLK
BF46 G36 SDVO_CTRLCLK 21
then to (G)MCH and CPU, in that TP_MCH_NC10 NC_9 SDVO_CTRLCLK SDVO_CTRLDATA
T509 BG45 E36 SDVO_CTRLDATA 11,21
order. TP_MCH_NC11 NC_10 SDVO_CTRLDATA CLK_MCH_OE#
T508 BH44 K36 CLK_MCH_OE# 2
TP_MCH_NC12 NC_11 CLKREQ# MCH_ICH_SYNC#
T507 BH43 H36 MCH_ICH_SYNC# 14
TP_MCH_NC13 NC_12 ICH_SYNC#
B T34 BH6 B
T37 TP_MCH_NC14 NC_13
BH5
TP_MCH_NC15 NC_14 TSATN#
T32 BG4 B12
TP_MCH_NC16 NC_15 TSA TN#
T36 BH3 UM A iHDMI I/F
TP_MCH_NC17 NC_16
T35 BF3
NC_17 RAMP2
T30 TP_MCH_NC18 BH2 NOTE:
T33 TP_MCH_NC19 NC_18 HDA_BIT_CLK_HDMI If (G)MCH's HD Audio signals are connected to ICH9M for
BG2 B28 HDA_BIT_CLK_HDMI 12
TP_MCH_NC20 NC_19 HDA_B CLK HDA_RST#_HDMI iHDMI, VCCHDA and VCCSUSHDA on ICH9M should be PEG_RXP3 R200 IV@0_4 Port-B_HPD#
T22 BE2 B30 HDA_RST#_HDMI 12 Port-B_HPD# 21
TP_MCH_NC21 NC_20 HDA_RST# HDA_SDIN_HDMI only on 1.5V. These power pins on ICH9M can be supplied
T28 BG1 B29 HDA_SDIN_HDMI 12
TP_MCH_NC22 NC_21 HDA_S DI HDA_SDOUT_HDMI with 3.3V if and only if (G)MCH's HDA is not connected to
T31 BF1 C29 HDA_SDOUT_HDMI 12
TP_MCH_NC23 NC_22 HDA_S DO HDA_SYNC_HDMI ICH9M. Consequently, only 1.5V audio/modem codecs can
T29 BD1 A28 HDA_SYNC_HDMI 12
T26 TP_MCH_NC24 NC_23 HDA_SYNC be used on the platform. C_PEG_TXP0 C680 IHM@0.1u/10V_4 TMDSB_DATA2
BC1 TMDSB_DATA2 21
TP_MCH_NC25 NC_24 C_PEG_TXN0 C672 IHM@0.1u/10V_4 TMDSB_DATA2#
T23 F1 TMDSB_DATA2# 21
NC_25
C_PEG_TXP1 C671 IHM@0.1u/10V_4 TMDSB_DATA1
TMDSB_DATA1 21
EV_IV@CANTIGA_1p2 C_PEG_TXN1 C670 IHM@0.1u/10V_4 TMDSB_DATA1#
TMDSB_DATA1# 21
C_PEG_TXP2 C669 IHM@0.1u/10V_4 TMDSB_DATA0
TMDSB_DATA0 21
C_PEG_TXN2 C668 IHM@0.1u/10V_4 TMDSB_DATA0#
TMDSB_DATA0# 21
C_PEG_TXP3 C667 IHM@0.1u/10V_4 TMDSB_CLK
TMDSB_CLK 21
C_PEG_TXN3 C666 IHM@0.1u/10V_4 TMDSB_CLK#
TMDSB_CLK# 21
<Checklist ver0.8> IV&EV Dis/Enable LVDS setting(See DG 1.0 P190 Table 103)
Check list note : CL_REF=0.35V SM_VREF.Default use voltage divider for poor layout cause +SMDDR_VREF not If TSATN# is not used, then it must be terminated
+1.05V
meet spec.And Intel circuit PU/PD is 1K,But Check list PU/PD is 10K. with a 56- pull-up resistor to VCCP. +1.05V R190 IV@0_4 LVDS_VREFH For IV @ 0ohm
LVDS_VREFL
For EV@ NC
TSATN# 56_4 R537
R180 R206 *0_6 +SMDDR_VREF
For IV @ 2.37K/F
1K/F_4 +3V R563 IV@2.37K/F_4 LVDS_IBG For EV@ NC
MCH_CLVREF_R SM_VREF R191 10K/F_4 +1.8VSUS_GMCH CLK_MCH_OE# 10K_4 R172
+3V R154 IV@10K_4 L_CTRL_CLK For IV @ 10K
PM_EXTTS#0 10K_4 R184 For EV@ NC
C164 R181 R155 IV@10K_4 L_CTRL_DATA
R205 PM_EXTTS#1 10K_4 R179
0.1u/10V_4 511/F_6 10K/F_4
IV&EV Dis/Enable CRT setting(See DG 1.0 P190 Table 103) Dis TV/En CRT( See DG1.0 P208 Table 118)
SM_REXT R132 499/F_4
R176 *EV@0_4 INT_CRT_DDCCLK For IV @ NC R142 EV_IV@75_4 INT_TV_COMP For IV @ 75ohm to GND
A A
R177 *EV@0_4 INT_CRT_DDCDAT For EV@ 0ohm to GND or NC R143 EV_IV@75_4 INT_TV_Y/G For EV@ 0ohm to GND
SM_PW ROK only for DDR3.(DDR2 PD only) R144 EV_IV@75_4 INT_TV_C/R
+1.8VSUS_GMCH +1.8VSUS_GMCH R553 1K/F_4 SM_RCOMP_VOH R162 EV@0_4 HSYNC_G For IV @ NC

+1.8VSUS_GMCH HW PG_1.8V 28,35
R164 EV@0_4 VSYNC_G For IV @ 0ohm to GND
For EV@ 0ohm to GND
C585 C589 R158 0_4 TV_DCONSEL_0
For EV@ 0ohm to GND
R551 R194 R175 0_4 TV_DCONSEL_1
R547 R545 0.01u/16V_4 2.2u/6.3V_6 *12K/F_4
3.01K/F_4 R159 EV_IV@150/F_4 INT_CRT_BLU For IV @ Connect to 150ohm/F
80.6/F_4 *20/F_4 R160 EV_IV@150/F_4 INT_CRT_GRN
For EV@ Connect to 0ohm GND
SM_PW ROK R161 EV_IV@150/F_4 INT_CRT_RED
M_RCOMP M_RCOMP# SM_RCOMP_VOL IV&EV Dis/Enable PLL setting(See DG 1.0 P190 Table 103)
R186 Quanta Computer Inc.
R548 R546 R550 C583 C584 10K/F_6 DREFCLK R561 EV@0_4
DREFCLK# R562 EV@0_4
*20/F_4 80.6/F_4 1K/F_4 0.01u/16V_4 2.2u/6.3V_6 R157 EV_IV@1K/F_4 CRTIREF
For IV @ Connect to 1.02K/F
For EV@ Connect to 0ohm GND DREFSSCLK R197 EV@0_4
For IV @ NC
For EV@ 0ohm to GND
PROJECT : TE1M
DREFSSCLK# R198 EV@0_4 Size Document Number Rev
Layout Note :See DG1.0 P180 E3D
NB (2/7)- VGA, MDI
D ate: Friday, June 13, 2008 S heet 6 of 40
5 4 3 2 1
5 4 3 2 1
BOM Option Table

GM PN=> AJSLB940T05
PM PN=> AJSLB970T03
17 M_B_DQ[63:0]
17 M_A_DQ[63:0]
D D
U504D U504E
M_A_DQ0 AJ38 BD21 M_A_BS#0 M_B_DQ0 AK47 BC16 M_B_BS#0
SA_DQ_0 SA_BS_0 M_A_BS#0 16,17 SB_DQ_0 SB_BS_0 M_B_BS#0 16,17
M_A_DQ1 AJ41 BG18 M_A_BS#1 M_B_DQ1 AH46 BB17 M_B_BS#1
M_A_DQ2 AN38 AT25 M_A_BS#2 M_B_DQ2 AP47 BB33 M_B_BS#2
M_A_DQ3 AM38 M_B_DQ3 AP46
M_A_DQ4 SA_DQ_3 M_A_RAS# M_B_DQ4 SB_DQ_3
AJ36 BB20 M_A_RAS# 16,17 AJ46
M_A_DQ5 SA_DQ_4 SA_RAS# M_A_CAS# M_B_DQ5 SB_DQ_4 M_B_RAS#
AJ40 BD20 M_A_CAS# 16,17 AJ48 AU17 M_B_RAS# 16,17
M_A_DQ6 SA_DQ_5 SA_CAS# M_A_WE# M_B_DQ6 SB_DQ_5 SB_RAS# M_B_CAS#
AM44 AY20 M_A_WE# 16,17 AM48 BG16 M_B_CAS# 16,17
M_A_DQ7 SA_DQ_6 SA_WE# M_B_DQ7 SB_DQ_6 SB_CAS# M_B_WE#
AM42 AP48 BF14 M_B_W E# 16,17
M_A_DQ8 SA_DQ_7 M_B_DQ8 SB_DQ_7 SB_WE#
AN43 AU47
M_A_DQ9 SA_DQ_8 M_B_DQ9 SB_DQ_8
AN44 AU46
AU40 M_A_DM[7:0] 17 BA48
M_A_DQ11 SA_DQ_10 M_A_DM0 M_B_DQ11 SB_DQ_10
AT38 AM37 AY48 M_B_DM[7:0] 17
M_A_DQ12 SA_DQ_11 SA_DM_0 M_A_DM1 M_B_DQ12 SB_DQ_11 M_B_DM0
AN41 AT41 AT47 AM47
M_A_DQ13 SA_DQ_12 SA_DM_1 M_A_DM2 M_B_DQ13 SB_DQ_12 SB_DM_0 M_B_DM1
AN39 AY41 AR47 AY47
AU44 AU39 BA47 BD40
AU42 BB12 BC47 BF35
AV39 AY6 BC46 BG11
AY44 AT7 BC44 BA3
BA40 AJ5 BG43 AP1
M_A_DQ19 SA_DQ_18 SA_DM_7 M_B_DQ19 SB_DQ_18 SB_DM_6 M_B_DM7
BD43 M_A_DQS[7:0] 17 BF43 AK2
M_A_DQ20 SA_DQ_19 M_A_DQS0 M_B_DQ20 SB_DQ_19 SB_DM_7
AV41 AJ44 BE45 M_B_DQS[7:0] 17
M_A_DQ21 SA_DQ_20 SA_DQS_0 M_A_DQS1 M_B_DQ21 SB_DQ_20 M_B_DQS0
C AY43 AT44 BC41 AL47 C
M_A_DQ22 SA_DQ_21 SA_DQS_1 M_A_DQS2 M_B_DQ22 SB_DQ_21 SB_DQS_0 M_B_DQS1
BB41 BA43 BF40 AV48
BC40 BC37 BF41 BG41
AY37 AW12 BG38 BG37
BD38 BC8 BF38 BH9
AV37 AU8 BH35 BB2
AT36 AM7 M_A_DQS#[7:0] 17 BG35 AU1
M_A_DQ28 SA_DQ_27 SA_DQS_7 M_A_DQS#0 M_B_DQ28 SB_DQ_27 SB_DQS_6 M_B_DQS7
AY38 AJ43 BH40 AN6 M_B_DQS#[7:0] 17
M_A_DQ29 SA_DQ_28 SA_DQS#_0 M_A_DQS#1 M_B_DQ29 SB_DQ_28 SB_DQS_7 M_B_DQS#0
BB38 AT43 BG39 AL46
M_A_DQ30 SA_DQ_29 SA_DQS#_1 M_A_DQS#2 M_B_DQ30 SB_DQ_29 SB_DQS#_0 M_B_DQS#1
AV36 BA44 BG34 AV47
AW36 BD37 BH34 BH41
BD13 AY12 BH14 BH37
AU11 BD8 BG12 BG9
BC11 AU9 BH11 BC2
BA12 AM8 BG8 AT2
M_A_DQ36 SA_DQ_35 SA_DQS#_7 M_B_DQ36 SB_DQ_35 SB_DQS#_6 M_B_DQS#7
AU13 M_A_A[14:0] 16,17 BH12 AN5
M_A_DQ37 SA_DQ_36 M_A_A0 M_B_DQ37 SB_DQ_36 SB_DQS#_7
AV13 BA21 BF11 M_B_A[14:0] 16,17
M_A_DQ38 SA_DQ_37 SA_MA_0 M_A_A1 M_B_DQ38 SB_DQ_37 M_B_A0
BD12 BC24 BF8 AV17
M_A_DQ39 SA_DQ_38 SA_MA_1 M_A_A2 M_B_DQ39 SB_DQ_38 SB_MA_0 M_B_A1
BC12 BG24 BG7 BA25
BB9 BH24 BC5 BC25
BA9 BG25 BC6 AU25
AU10 BA24 AY3 AW25
AV9 BD24 AY1 BB28
BA11 BG27 BF6 AU28
BD9 BF25 BF5 AW28
AY8 AW24 BA1 AT33
BA6 BC21 BD3 BD33
AV5 BG26 AV2 BB16
B
B
AV7 BH26 AU3 AW33
AT9 BH17 AR3 AY33
AN8 AY25 AN2 BH15
M_A_DQ52 SA_DQ_51 SA_MA_14 M_B_DQ52 SB_DQ_51 SB_MA_13 M_B_A14
AU5 AY2 AU33
M_A_DQ53 SA_DQ_52 M_B_DQ53 SB_DQ_52 SB_MA_14
AU6 AV1
AT5 AP3
AN10 AR1
AM11 AL1
AM5 AL2
AJ9 AJ1
AJ8 AH1
AN12 AM2
AM13 AM3
AJ11 AH3
AJ12 AJ3
SA_DQ_63 SB_DQ_63
EV_IV@CANTIGA_1p2 EV_IV@CANTIGA_1p2
A A

PROJECT : TE1M
E3D
NB (3/7)- DDRII
5 4 3 2 1
5 4 3 2 1
BOM Option Table

IV@ INT VGA
GM PN=> AJSLB940T05 EV@ EXT VGA
PM PN=> AJSLB970T03
+1.8VSUS_GMCH +1.8VSUS
+1.8VSUS_GMCH +VGFX_CORE_INT
R149 0_1206
U504F U504G
+1.05V_VCC_GMCH
D AP33 W 28 C598 C594 C122 + C156 D

VCC_SM_1 VCC_AXG_NCTF_1
AG34 AN33 V28 Close to GMCH
VCC_1 VCC_SM_2 VCC_AXG_NCTF_2 10u/6.3V_8 10u/6.3V_8 0.1u/10V_4 330u/2.5V_7343
AC34 BH32 W 26
VCC_2 VCC_SM_3 VCC_AXG_NCTF_3
AB34 BG32 V26
AA34 BF32 W 25
Y34 BD32 V25
V34 BC32 W 24
U34 BB32 V24
VCC_7 VCC_SM_8 VCC_AXG_NCTF_8 +1.05V_VCC_GMCH +1.05V
AM33 BA32 W 23
AK33 AY32 V23
VCC_9 VCC_SM_10 VCC_AXG_NCTF_10 R113 0_1206
AJ33 AW 32 AM21
AG33 VCC_11 AV32 VCC_SM_12 VCC_AXG_NCTF_12 AL21
AF33 AU32 AK21
VCC_12 VCC_SM_13 VCC_AXG_NCTF_13 C148 C162 C143 C157 + C126
AT32 W 21
AE33 AR32 V21
VCC_13 VCC_SM_15 VCC_AXG_NCTF_15 0.22u/6.3V_4 0.22u/6.3V_4 22u/6.3V_8
AC33 AP32 U21 0.1u/10V_4 330u/2.5V_7343
AA33 AN32 AM20
Y33 BH31 AK20
W 33 BG31 W 20
V33 BF31 U20
U33 VCC_19 BG30 VCC_SM_21 VCC_AXG_NCTF_21 AM19 Close to GMCH
AH28 BH29 AL19
AF28 BG29 AK19
VCC_21 VCC_SM_23 VCC_AXG_NCTF_23 +VGFX_CORE_INT +1.05V
AC28 BF29 AJ19
AA28 BD29 AH19
AJ26
VCC_24
BC29
AG19 See Page 9 EV&IV table
AG26 BB29 AF19 R111 IV@0_1206
AE26 BA29 AE19
AC26 AY29 AB19
VCC_27 VCC_SM_29 VCC_AXG_NCTF_29 C137 C131 C128 C132 C124 C130
AH25 AW 29 AA19
AG25 AV29 Y19 R136 R137 R148
VCC_29 VCC_SM_31 VCC_AXG_NCTF_31 IV@0.47u/6.3V_4
AF25 AU29 W 19 IV@1u/16V_6 IV@10u/10V_8 IV@10u/6.3V_8 IV@0.1u/10V_4 IV@0.1u/10V_4
VCC_30 VCC_SM_32 VCC_AXG_NCTF_32 EV@0_6 EV@0_6 EV@0_6
AG24 AT29 V19
AJ23 AR29 U19
VCC_32 +1.05V_VCC_GMCH VCC_SM_34 VCC_AXG_NCTF_34
AH23 AP29 AM17 DR8
C VCC_33 VCC_SM_35 VCC_AXG_NCTF_35 C
AF23 AK17 DR9
VCC_34 VCC_AXG_NCTF_36
AM32 BA36 AH17
VCC_NCTF_1 VCC_SM_36/NC VCC_AXG_NCTF_37
T32 VCC_35 AL32 BB24 AG17
AK32 BD16 AF17
R174 VCC_NCTF_3 VCC_SM_38/NC VCC_AXG_NCTF_39
VCC_NCTF_4 AJ32 BB21 VCC_SM_39/NC VCC_AXG_NCTF_40 AE17 Place close to the GMCH
AH32 AW 16 AC17 +VGFX_CORE_INT
0_4 VCC_NCTF_5 VCC_SM_40/NC VCC_AXG_NCTF_41 and different location
AG32 AW 13 AB17
AE32 AT13 Y17
AC32 W 17
VCC_NCTF_8 +VGFX_CORE_INT VCC_AXG_NCTF_44
AA32 V17
VCC_NCTF_9 VCC_AXG_NCTF_45
Y32 AM16
VCC_NCTF_10 VCC_AXG_NCTF_46 + C104 + C103
W 32 Y26 AL16
VCC_NCTF_11 VCC_AXG_1 VCC_AXG_NCTF_47
U32 AE25 AK16
VCC_NCTF_12 VCC_AXG_2 VCC_AXG_NCTF_48 IV@330u/2.5V_7343 IV@330u/2.5V_7343
AM30 AB25 AJ16
AL30 AA25 AH16
AK30 AE24 AG16
VCC_NCTF_16
AH30 AC24
VCC_AXG_6 VCC_AXG_NCTF_52
AF16 Close to GMCH
AG30 AA24 AE16
AF30 Y24 AC16
AE30 AE23 AB16
AC30 AC23 AA16
AB30 AB23 Y16
AA30 AA23 W 16
VCC_NCTF_23 Y30
W 30
AJ21
AG21
VCC_AXG_13 VCC_AXG_NCTF_59 V16
U16 NB Power Status and max current table(1/3)
V30 AE21 POWER PLANE
VCC_NCTF_25 VCC_AXG_15 S0 S3 S4/S5 Voltage I(max) Note
U30 AC21
VCC_NCTF_26 VCC_AXG_16
AL29 AA21 VCC(EXT_VGA) O X X +1.05V 2178mA
AK29 Y21
AJ29 AH20 VCC(INT_VGA) O X X +1.05V 2899mA
AH29 AF20
AG29 AE20 VCC_AXG O X X +1.05V 8700mA Graphics Core
AE29 AC20
AC29 AB20 VCC_SM(800) O O X +1.8VSUS 3A (DDRII-667) 2.6A
VCC_NCTF_34 AA29 AA20 VCC_AXG_24
B B
Y29 T17 VCC_SM(Standby) O O X +1.8VSUS 1mA Self Refresh during S3
W 29 T16
V29 AM15
VCC_NCTF_38
AL28 AL15
VCC_AXG_28 (See NB EDS Rev:1.0 Section 10.1 for max current)
AK28 AE15
VCC_NCTF_40
AL26 AJ15
VCC_AXG_30 (See NB EDS Rev:1.0 Section 12.2 for DC voltage)
AK26 AH15
VCC_NCTF_42 AK25 AG15 VCC_AXG_32
VCC_NCTF_43 AK24 AF15 VCC_AXG_33
VCC_NCTF_44 AK23 AB15 VCC_AXG_34
AA15
VCC_AXG_35
Y15
VCC_AXG_36
V15
VCC_AXG_37
U15
VCC_AXG_38 Close to each pins
AN14
VCC_AXG_39 1.8V Internal connect to power
AM14
EV_IV@CANTIGA_1p2 VCC_AXG_40
U14 AV44
VCC_AXG_41 VCC_SM_LF1
T14 BA37
VCC_AXG_42 VCC_SM_LF2
VCC_SM_LF3 AM40
VCC_SM_LF4 AV21
AY5
VCC_SM_LF5
AM10
+VGFX_CORE_INT VCC_SM_LF6
BB13
VCC_SM_LF7
C123 C117 C114 C135 C170 C153 C175
R119 IV@10/F_6 AJ14 VCC_AXG_SENSE 0.1u/10V_4 0.1u/10V_4 0.22u/6.3V_4 0.22u/6.3V_4 0.47u/10V_6 1u/16V_6 1u/16V_6
R116 IV@10/F_6 AH14 VSS_AXG_SENSE
1. Route VCC_AXG_SENSE and VSS_AXG_SENSE differentially

2. VCC_AXG_SENSE PU to +VGFX_CORE_INT with 10ohm
A and VSS_AXG_SENSE PD with 10ohm for Intel suggest A
EV_IV@CANTIGA_1p2

PROJECT : TE1M
E3D
NB (4/7)- VCC, NCTF
5 4 3 2 1
5 4 3 2 1
BOM Option Table
+3V_A_TV_CRT +3V_A_TV_CRT
IV@ INT VGA
+3V
L506 IV@BLM18PG181SN1D_6 +3V_A_DAC_BG +3V_A_CRT_DAC EV@ EXT VGA
C575 C580 C579 R549 C581 C582
IHM@ INT HDMI
IV@10u/10V_8 IV@0.1u/10V_4 IV@0.01u/16V_4 EV@0_4 IV@0.1u/10V_4 IV@0.01u/16V_4
DR1
DR7
D GM PN=> AJSLB940T05 D
+1.05V
L513 IV@10uh_8
+1.05V
L15 IV@10uh_8 +1.05VM_DPLLA PM PN=> AJSLB970T03
R565 R203
C629 + C619 C166 + C187
EV@0_4 EV@0_4
IV@220u/2.5V_734 3 IV@0.1u/10V_ 4 IV@220u/2.5V_7343 IV@0 .1u/10V_ 4
DR11 DR10
+1.05V_VCCP_GMCH
U504H
+1.05VM_DPLLB
U13 +1.05V_VCCP_GMCH R528 0_8 +1.05V
VTT_1
T13
+1.05VM_MCH_PLL2 +1.05VM_HPLL VTT_2
+1.05V
R104 0_6 R103 0_6 +3V_A_CRT_DAC B27 U12 C115 C564 C566 C562 + C565
VCCA_CRT_DA C_1 VTT_3
A26 T12
VCCA_CRT_DA C_2 VTT_4
C108 C112 U11 0.47u/6.3V_4 2.2u/6.3V_6 4.7u/10V_6 4.7u/10V_6 330u/2.5V_7343
VTT_5
T11
4.7u/10V_6 0.1u/10V_4 +3V_A_DA C_BG VTT_6
A25 U10
VCCA_DAC_BG VTT_7
B25 T10
VSSA_DAC_BG VTT_8
U9
VTT_9
T9
VTT_10
U8
+1.05VM_MPLL +1.05VM_DPLLA VTT_11
L9 BLM18PG181SN1D_6 F47 T8
VCCA_DPLLA VTT_12
U7
VTT_13 +1.05VM_AXF
+1.05VM_DPLLB L48 T7 L503 0.1uh_8
VCCA_DPLLB VTT_14 +1.05V
U6
+1.05VM_HPLL VTT_15
AD1 T6 C569 C572
VCCA_HPLL VTT_16
U5
R100 *0.5/F_6 +1.05VM_MPLL_RC +1.05VM_MPLL VTT_17 1u/6.3V_4 *10u/10V_8
AE1 T5
VCCA_MPLL VTT_18
V3
VTT_19
C110 C96 U3
+1.8VSUS_TXLVDS VTT_20
J48 V2
VCCA_LVDS VTT_21
0.1u/10V_4 *22u/6.3V_ 8 U2
VTT_22
C621 J47 T2
VSSA_LVDS VTT_23
V1
IV@1000p/50V_4 VTT_24 +1.8VSUS_VCC_SM_CK L504 1uh_8
U1 +1.8VSUS_GMCH
VTT_25
B2A +1.5V R566 0_8 +1.5V_VCCA_PEG_BG AD48

VCCA_PEG_BG C576
+1.05V R102 0_6 +1.05VM_A_SM C617 1/F_4 R538 +1.8VSUS_SMCK_RC
0.1u/10V_4
C134 C129 C125 C121 0.1u/10V_4
C C
+ C95 +1.05VM_PEGPLL AA48 C570
VCCA_PEG_PLL
*10u/6.3V_8 10u/6.3V_8 4.7u/10V_6 1u/6.3V_4 10u/10V_8
100u/6.3V_ 35 28
+1.05VM_A_SM AR20
VCCA_SM_1
AP20
VCCA_SM_2 B2A
POWER
AN20
VCCA_SM_3
AR17
VCCA_SM_4 +1.8VSUS_TXLVDS
AP17 L511 IV@0.1uh_8
VCCA_SM_5 +1.8VSUS
AN17
+1.05VM_A_SM_CK VCCA_SM_6
+1.05V R153 0_6 AT16
VCCA_SM_7
AR16 R564 C622 C626
VCCA_SM_8
AP16
VCCA_SM_9
C139 C138 C136 EV@0_4 IV@1000p/50V_4 IV@10u/6.3V_8
+1.05V
*2.2u/6.3V_6 10u/6.3V_8 0.1u/10V_4 DR3
DR4
B2A
+1.05VM_A_SM_CK AP28 D502
VCCA_SM_CK_1 +1.05VM_AXF
AN28 B22
VCCA_SM_CK_2 VCC_AXF_1
+3V
R543 IV@0_6 +3V_TV_DAC AP25 B21 CH751H-40PT
AN25 A21
AN24
VCCA_SM_CK_5
C578 C577 R544 AM28
VCCA_SM_CK_NCTF_1
AM26 R557 10_4 +1.05V_SD
IV@0.01u/16V_4 VCCA_SM_CK_NCTF_2
IV@0.1u/10V_4 EV@0_4 AM25
VCCA_SM_CK_NCTF_3 +1.8VSUS_VCC_SM_CK
AL25 BF21
VCCA_SM_CK_NCTF_4 VCC_SM_CK_1 +3V_VCC_HV 0_6
DR5 AM24
VCCA_SM_CK_NCTF_5 VCC_SM_CK_2
BH20 R558
+3V
AL24 BG20
AM23 BF20 C599
AL23
VCCA_SM_CK_NCTF_8
0.1u/10V_4
+1.5V
R555 IHM@0_6 +1.5V_VCC_HDA K47 +1.8VSUS_TXLVDS +1.05V_VCC_PEG
+3V_TV_DAC VCC_TX_LVDS
B24
VCCA_TV_DAC_1
C596 FOR iHDMI HDA I/F only R556 IF iHDMI not used,HDA A24 C35 +3V_VCC_HV
VCCA_TV_DAC_2 VCC_HV_1 +1.05V_VCC_PEG R568 0_8
B35 +1.05V
IHM@0.1u/10V_4 EV@0_4 connect ot GND(DG1.0 P277) VCC_HV_2
A35
VCC_HV_3
C620 C627
DR12 +1.5V_VCC_HDA A32 + C200
VCC_HDA +1.05V_VCC_PEG
V48 4.7u/10V_6 10u/6.3V_8
VCC_PEG_1
U48 220u/2.5V_7343
VCC_PEG_2
B V47 B
VCC_PEG_3
U47
VCC_PEG_4
+1.5V R552 0_6 +1.5V_TVDAC +1.5V_TVDAC M25 U46
VCCD_TVDAC VCC_PEG_5
+1.5V_QDAC L28
C587 C588
VCCD_QDAC
AH48 +1.05V_VCC_DMI +1.05V_VCC_DMI R211 0_8
+1.05V_VCC_PEG
VCC_DMI_1
+1.05VM_MCH_PLL2 AF1 AF48
VCCD_HPLL VCC_DMI_2
0.1u/10V_4 0.01u/16V_4 AH47 C616 C625
+1.05VM_PEGPLL VCC_DMI_3
AA47 AG47
VCCD_PEG_PLL VCC_DMI_4
0.1u/10V_4 *10u/10V_8
C102
+1.8VSUS_DLVDS M38
VCCD_LVDS_1
0.1u/10V_4 L37 A8
VCCD_LVDS_2 VTTLF1
L1
VTTLF2
+1.5V
L510 IV@BLM18PG181SN1D_6 +1.5V_QDAC AB2 B2A
VTTLF3
C107 C105 C113
C586 C592 C591 R554
EV_IV@CANTIGA_1p2 0.47u/6.3V_4 0.47u/6.3V_4 0.47u/6.3V_4
IV@10u/6.3V_8 IV@0.1u/10V_4 IV@0.01u/16V_4 EV@0_4
DR6
NB Power Status and max current table(2/3)(NB left side) EXT&INT VGA Power Plane Option table NB Power Status and max current table(3/3)(NB Right side)
POW ER PLANE S0 S3 S4/S5 Voltage I(max) Note POW ER PLANE EXT VGA INT VGA MARK POW ER PLANE S0 S3 S4/S5 Voltage I(max) Note
+1.05V L512 BLM18PG181SN1D_6 +1.05VM_PEGPLL VCCA_CRT_DAC O X X +3.3V 73mA VCCA_CRT_DAC GND +3V DR1 VTT O X X +1.05V 852mA FSB at 1067MHz
C623 C618
VCCA_DAC_BG O X X +3.3V 5mA VCCD_LVDS GND +1.8VSUS DR2 VCCA_AXF O X X +1.05V 322mA
0.1u/10V_4 0.1u/10V_4
VCCA_DPLLA O X X +1.05V 64.8mA VCC_TX_LVDS GND +1.8VSUS DR3 VCC_SM_CK(800) O O X +1.8VSUS 124mA (DDRII-667) 120mA
VCCA_DPLLB O X X +1.05V 64.8mA VCCA_LVDS GND +1.8VSUS DR4 VCC_TX_LVDS O O X +1.8VSUS 119mA
VCCA_HPLL O X X +1.05V 24mA VCCD_TVDAC +1.5V +1.5V VCC_HV O X X +3V 106mA
R567 1/F_4 +1.05VM_PEGPLL_RC VCCA_MPLL O X X +1.05V 139.2mA VCCA_TV_DAC GND +3V DR5 VCC_PEG O X X +1.05V 1782mA
C628 O O X GND DR6 O X X
VCCA_LVDS +1.8VSUS 13.2mA VCCD_QDAC +1.5V VCC_DMI +1.05V 456mA
10u/10V_8
VCCA_PEG_BG O X X +1.5V 414uA VCCA_DAC_BG GND +3V DR7
A
(See NB EDS Rev:1.0 Section 10.1 for max current) A
VCCA_PEG_PLL O X X +1.05V 50mA VCC_AXG GND +1.05V DR8 Page 8
(See NB EDS Rev:1.0 Section 12.2 for DC voltage)
VCCA_SM(DDRII-800) O X X +1.05V 720mA (DDRII-667) 480mA VCC_AXG_NCTF GND +1.05V DR9 Page 8
+1.8VSUS
R560 IV@0_6 +1.8VSUS_DLVDS VCCA_SM_CK(800) O X X +1.05V 26mA (DDRII-667) 24mA VCCA_DPLLA GND +1.05V DR10
VCCA_TV_DAC O X X +3.3V 79mA VCCA_DPLLB GND +1.05V DR11

C602 R559
VCC_HDA O X X +1.5V 50mA VCC_HDA GND +1.5V DR12 For iHDMI
IV@1u/6.3V_4 EV@0_4
VCCD_TVDAC O X X +1.5V 35mA
DR2 EXT VGA->Disable TV/CRT/LVDS/HDMI(See DG 1.0 P190 Table 103)
VCCD_QDAC O X X +1.5V 125uA
INT VGA->Disable TV/Enable CRT( See DG1.0 P208 Table 118) Quanta Computer Inc.
VCCD_HPLL O X X +1.05V 157mA
VCCD_PEG_PLL O X X +1.05V 50mA
INT VGA->Disable HDMI(See DG 1.0 P277 section 3.10.4)
PROJECT : TE1M
S ize Document Num ber R ev
VCCD_LVDS O O X +1.8VSUS 60mA NB (5/7)- POWER E3D

5 4 3 2 1
5 4 3 2 1
BOM Option Table
U504I U504J
BG21
VSS_199 VSS_297
AH8 EV_IV@ EV&IV diff. BOM
AU48 AM36 L12 Y8
VSS_1 VSS_100 VSS_200 VSS_298
AR48 AE36 AW21 L8
AL48 P36 AU21 E8
BB47 L36 AP21 B8
AW47 J36 AN21 AY7
AN47 F36 AH21 AU7
AJ47 B36 AF21 AN7
AF47 AH35 AB21 AJ7
AD47 AA35 R21 AE7
D VSS_9 VSS_108 VSS_208 VSS_306 D
AB47 Y35 M21 AA7
Y47 U35 J21 N7
T47 T35 G21 J7
N47 BF34 BC20 BG6
L47 AM34 BA20 BD6
G47 AJ34 AW20 AV6
BD46 AF34 AT20 AT6
BA46 AE34 AJ20 AM6
AY46 W 34 AG20 M6
AV46 B34 Y20 C6
AR46 A34 N20 BA5
AM46 BG33 K20 AH5
V46 BC33 F20 AD5
R46 BA33 C20 Y5
P46 AV33 A20 L5
H46 AR33 BG19 J5
F46 AL33 A18 H5
BF44 AH33 BG17 F5
AH44 AB33 BC17 BE4
AD44 P33 AW17
VSS_29 VSS_128 VSS_228
VSS
AA44 L33 AT17 BC3
Y44
VSS_31 VSS_130
H33 R17
VSS_230 VSS_328
AV3 GM PN=> AJSLB940T05
U44 N32 M17 AL3 PM PN=> AJSLB970T03
VSS
T44 K32 H17 R3
M44 F32 C17 P3
F44 C32 F3
BC43 A31 BA16 BA2
AV43 AN29 AW2
AU43 T29 AU16 AU2
C AM43 N29 AN16 AR2 C
J43 K29 N16 AP2
C43 H29 K16 AJ2
BG42 F29 G16 AH2
AY42 A29 E16 AF2
AT42 BG28 BG15 AE2
AN42 BD28 AC15 AD2
AJ42 BA28 W 15 AC2
AE42 AV28 A15 Y2
N42 AT28 BG14 M2
L42 AR28 AA14 K2
BD41 AJ28 C14 AM1
AU41 AG28 BG13 AA1
AM41 AE28 BC13 P1
AH41 AB28 BA13 H1
AD41 Y28
VSS_54 VSS_153 MCH_VSS_351 R152 0_4
AA41 P28 U24
VSS_55 VSS_154 VSS_351 MCH_VSS_352 R156 0_4
Y41 K28 AN13 U28
VSS_56 VSS_155 VSS_255 VSS_352 MCH_VSS_353 R147 0_4
U41 H28 AJ13 U25
T41 F28 AE13 U29
M41 C28 N13 AJ6
G41 BF26 L13
B41 AH26 G13 AF32
VSS_61 VSS_160 VSS_260 VSS_NCTF_1
BG40 AF26 E13 AB32
BB40 AB26 BF12 V32
AV40 AA26 AV12 AJ30
AN40 C26 AT12 AM29
H40 B26 AM12 AF29
E40 BH25 AA12 AB29
AT39 BD25 J12 U26
B VSS_68 VSS_167 VSS_267 VSS_NCTF_8 B
AM39 BB25 A12 U23
AJ39 AV25 BD11 AL20
AE39 AR25 BB11 V20
N39 AJ25 AY11 AC19
L39 AC25 AN11 AL17
B39 Y25 AH11 AJ17
BH38 N25 AA17
VSS_75 VSS_174 VSS_NCTF_15
BC38 L25 Y11 U17
BA38 J25 N11
AU38 G25 G11 BH48
VSS_78 VSS_177 VSS_277 VSS_SCB_1
AH38 E25 C11 BH1
AD38 BF24 BG10 A48
AA38 AD12 AV10 C1
Y38 AY24 AT10
U38 AT24 AJ10 A3
T38 AJ24 AE10
J38 AH24 AA10 E1
VSS_85 VSS_184 VSS_284 NC_26
F38 AF24 M10 D2
VSS_86 VSS_185 VSS_285 NC_27
C38 AB24 BF9 C3
VSS_87 VSS_186 VSS_286 NC_28
BF37 R24 BC9 B4
VSS_88 VSS_187 VSS_287 NC_29
BB37 L24 AN9 A5
VSS_89 VSS_188 VSS_288 NC_30
AW37 K24 AM9 A6
VSS_90 VSS_189 VSS_289 NC_31
AT37 J24 AD9 A43
VSS_91 VSS_190 VSS_290 NC_32
AN37 G24 G9 A44
VSS_92 VSS_191 VSS_291 NC_33
AJ37 F24 B9 B45
VSS_93 VSS_192 VSS_292 NC_34
H37 E24 BH8 C46
VSS_94 VSS_193 VSS_293 NC_35
C37 BH23 BB8 D47
VSS_95 VSS_194 VSS_294 NC_36
BG36 AG23 AV8 B47
VSS_96 VSS_195 VSS_295 NC_37
BD36 Y23 AT8 A46
VSS_97 VSS_196 VSS_296 NC_38
A AK15 B23 F48 A
VSS_98 VSS_197 NC_39
AU36 A23 E48
VSS_99 VSS_198 NC_40
C48
NC_41
B48
EV_IV@ CANTIGA_1p2 NC_42
A47
NC_43
EV_IV@ CANTIGA_1p2
PROJECT : TE1M
E3D
NB (6/7)- VSS
5 4 3 2 1
5 4 3 2 1
North Bridge Strap Pin Configuration Table BOM Option Table

(See DG 1.0 P295 Table 184) iTPM@ Internal TPM
(See NB EDS 1.0 P187 Table 74)
Pin Name Strap description Configuration PU<4.02K> PD <2.21K> Note
D CFG[2:0] FSB Frequency Select [000]= FSB 1066MHz [010] = FSB 800MHz [011] = FSB 667MHz See Page 2 FSB selection table D
CFG[4:3] Reserved
DMI X2 Select 0 = DMI X2 R141 *4.02K/F_4

CFG5 6 MCH_CFG_5
1 = DMI X4(Default)
CFG6 iTPM Host Interface 0 = iTPM Host Interface is enabled R146 *iTPM@10K/F_4
6 MCH_CFG_6
1 = iTPM Host Interface is disabled(Default)
0 = AMT Firmware will use TLS cipher suite with no confidentiality R145 *4.02K/F_4
CFG7 ME TLS Confidentiality 6 MCH_CFG_7
1 = AMT Firmware will use TLS cipher suite with confidentiality(Default)
CFG8 Reserved
PCI Express Graphics 0 = Reverse Lanes R540 *4.02K/F_4

CFG9 6 MCH_CFG_9
Lane Reversal 1 = Normal operation(Default)
PCIE Loopback enable 0 = Enabled R542 *4.02K/F_4

C CFG10 6 MCH_CFG_10 C
1 = Disabled (Default)
CFG11 Reserved
CFG12 ALLZ 0 = ALLZ mode enable R130 *4.02K/F_4

6 MCH_CFG_12
1 = disable(Default)
XOR 0 = XOR mode enable R131 *4.02K/F_4

CFG13 6 MCH_CFG_13
1 = disable(Default)
CFG[15:14] Reserved
CFG16 FSB Dynamic ODT 0 = Dynamic ODT disable R129 *4.02K/F_4

6 MCH_CFG_16
1 = Dynamic ODT Enable(Default)
CFG[18:17] Reserved
B CFG19 DMI Lane Reversal 0 = Normal (Default) R124 *4.02K/F_4 B

6 MCH_CFG_19 +3V
1 = Lanes Reversed
0 = Only Digital Display port (SDVO/DP/iHDMI) or PCIE is

Digital Display Port
operational (Default) R125 *4.02K/F_4
CFG20 (SDVO/DP/iHDMI) 6 MCH_CFG_20 +3V
1 = Digital Display port (SDVO/DP/iHDMI) and PCIE are operating
Concurrent with PCIE
simultaneously via PEG port
0 = No SDVO/HDMI/DP Device Present(Default)

SDVO_CTRLDATA SDVO Present 6,21 SDVO_CTRLDATA
R170 *2.2K/F_4 +3V Reference PAGE21 R185
1 = SDVO/HDMI/DP Device present
L_DDC_DATA Local Flat Panel(LFP) Present 0 = LFP Disable(Default) R168 *2.2K/F_4 +3V
6,19 INT_LVDS_EDIDDATA
1 = LFP Card Present;PCIE disable
DDPC_CTRLDATA Digital Display Present 0 = Digital display(HDMI/DP) device absent(Default) R123 *2.2K/F_4
6 DDPC_CTRLDATA +3V
1 = Digital display(HDMI/DP) device present
Enable iTPM Table

A A
PAGE Net Name PU & PD NOTE

11 MCH_CFG_6 PD 10K to GND NB Strap pin
13 SPI_MOSI PU 20K to +3V_S5 SB Strap pin
14 CLGPIO5 PU 10K to +3V_S5 SB Strap pin
PROJECT : TE1M
E3D
NB (7/7)- STRAP PIN
5 4 3 2 1
5 4 3 2 1
RTC CRYSTAL Layout note:

BOM Option Table
DPRSTP# , Daisy Chain
(SB>Power>NB>CPU)
B2A LDRQ0/1# : Internal PU IHM@ INT HDMI
CLK_32KX1 U512A
C24 3 15p/50V_4
CLK_32KX1 C23 K5 LAD0
RTCX1 FW H0/LAD0 LAD0 25,28
CLK_32KX2 C24 K4 LAD1
RTCX2 FW H1/LAD1 LAD1 25,28
R268 L6 LAD2
32. 7 68KHZ FW H2/LAD2 LAD2 25,28 +1.05V_ICH_IO
RTC_RST# A25 K2 LAD3
Y6 RTCRST# FW H3/LAD3 LAD3 25,28
10M_6 SRTC_RST# F20
SM_INTRUDER# SRTCRST#
C22 K3 LFRAME#
INTRUDER# FW H4/LF RAME# LFRAME# 25,28
C25 1 15p/50V_4 CLK_32KX2
B22 J3 LDRQ#0
D INTVRMEN LDRQ 0# T528 +1.05V_ICH_IO D
ICH_INTVRMEN A22 J1 LDRQ#1 R647 R285
LAN100_SLP LDRQ 1#/G PIO 23 LDRQ#1 25
*56_4 *56_4
E25 N7 GATEA20 GATEA20 28
GLAN_CLK A20GATE H_A20M#
AJ27 H_A20M# 3
A20M# R640
C13
LAN_RSTSYNC
RESET JUMP RAMP F14
DPRSTP#
AJ25
AE23
H_DPRSTP#_R
H_DPSLP#_R
R645
R275
0_4
0_4
ICH_DPRSTP# 3,6,33 56_4
LAN_RXD0 DPSLP# H_DPSLP# 3
G13
LAN_RXD1 H_FERR#_R R642 56_4 H_FERR#
D14 AJ26 H_FERR# 3
+VCCRTC An RC delay circuit with a ti me delay in the range LAN_RXD2 FERR#
of 18 ms to 25 ms should be provided D13 AD22 H_PWRGD
LAN_TXD0 CPUPW RGD H_PWRGD 3
D12
R577 20K_6 RTC _RST# LAN_TXD1 H_IGNNE#
E13 AF25 H_IGNNE# 3
LAN_TXD2 IGNNE#
C640 ICH_GPIO56 B10 AE22 H_INIT#
GPIO56 INIT# H_INIT# 3 +1.05V_ICH_IO
G1 AG 25 H_INTR
INTR H_INTR 3
1u/6.3V _4 *SHORT_ P AD B28 L3 RCIN# RCIN# 28
GLAN_COMP GLAN_COMPI RCIN#
B27
GLAN_COMPO H_NMI
AF23 H_NMI 3
HDA_BIT_CLK_R NMI H_SMI#_R R270 0_4 H_SMI# R266
AF 6 AF24 H_SMI# 3
HDA_SYNC_R HDA_BIT_CLK SMI#
AH4 56_4
+VCCRTC HDA_SYNC H_STPCLK#
AH27 H_STPCLK# 3
STPCLK#
HDA_RST#_R AE7
HDA_RST# H_THERMTRIP_R R639 56_4 H_THERMTRIP_RR R263 *0_4 PM_THRMTRIP#
AG 26 PM_THRMTRIP# 3,6
R291 20K_6 SRTC _RST# ACZ_SDIN0 THRMTRIP#
29 ACZ_SDIN0 AF 4
HDA_SDIN1 HDA_SDIN0 ICH_TP12
AG4 AG 27 T517
HDA_SDIN2 HDA_SDIN1 TP12
AH3 Layout note:
C259 G2 HDA_SDIN2
HDA_SDIN3 AE5 PU R needs to placed within 2" of ICH9-M,
1u/6.3V _4 T105 HDA_SDIN3 SATA_RXN4_C
*SHORT_ P AD AH11 series R must be placed within 2"of PU R w/o stub.
HDA_SDOUT_R SATA4RXN SATA_RXP4_C
AG5 AJ11
HDA_SDO UT SATA4RXP SATA_TXN4_C
AG 12
ICH_GPIO33 SATA4TXN SATA_TXP4_C
AG7 AF12
C T522 HDA_DOCK_EN#/GPIO33 SATA4TXP C
ICH_GPIO34 AE8
T102 HDA_DOCK_RST#/GPIO 34 SATA_RXN5 +3V
AH9 T524
SATA_LED# SATA5RXN SATA_RXP5
26 SATA_LED# AG8 AJ9 T525
SATALED# SATA5RXP
AE10 SATA_TXN5
SATA5TXN T520
SATA_RXN0_C AJ16 AF10 SATA_TXP5 GATEA20 R343 8.2K_4
SATA0RXN SATA5TXP T519
SATA_RXP0_C AH16
SATA_TXN0_C SATA0RXP CLK_PCIE_SATA# RCIN# R370 10K_4
AF17 AH18 CLK_PCIE_SATA# 2
+VCCRTC SATA_TXP0_C SATA0TXN SATA_CLKN CLK_PCIE_SATA
AG17 AJ18 CLK_PCIE_SATA 2
SATA0TXP SATA_CLKP
(DG 1.0 Table-292)
R576 1M_4 SM_INTRUDER# SATA_RXN1_C AH13 AJ7
Internal VRM enabled for SATA_RXP1_C SATA1RXN SATARBIAS# SATA_RBIAS_PN
AJ13 AH7
R295 332K/F_4 ICH_INTVRMEN VccSus1_05, VccSus1_5, SATA_TXN1_C SATA1RXP SATARBIAS
AG14
SATA1TXN
SATA I/F
VccCL1_5, VccLAN1_05 and SATA_TXP1_C AF14
VccCL1_05. SATA1TXP R675
ICH9M REV 1.0 SATA_RXN0 C738 3900p/25V_4 SATA_RXN0_C
22 SATA_RXN0
SATA_RBIAS_PN<0.5".Avoid routing 24.9/F_4 SATA_RXP0 C737 3900p/25V_4 SATA_RXP0_C
22 SATA_RXP0
+3V_S5
next to clock/high speed signals To SATA HDD 22 SATA_TXN0 SATA_TXN0 C734 3900p/25V_4 SATA_TXN0_C
SATA_TXP0 C735 3900p/25V_4 SATA_TXP0_C
22 SATA_TXP0
R338 10K_4 ICH_GPIO56
SATA_RXN1 C746 3900p/25V_4 SATA_RXN1_C

22 SATA_RXN1
SATA_RXP1 C743 3900p/25V_4 SATA_RXP1_C
22 SATA_RXP1
To SATA ODD 22 SATA_TXN1
SATA_TXN1 C739 3900p/25V_4 SATA_TXN1_C
SATA_TXP1 C740 3900p/25V_4 SATA_TXP1_C
22 SATA_TXP1
+1.5V_PCIE_ICH
C3A
R257 24.9/F_4 GLAN_COMP 24.9 Ohm pull up to 1.5V for SATA_RXN4 C613 3900p/25V_4 SATA_RXN4_C
27 SATA_RXN4
GLAN_COMPI/O is required, no 27 SATA_RXP4 SATA_RXP4 C611 3900p/25V_4 SATA_RXP4_C
matter intel LAN is used or not.
B
To E-SATA 27 SATA_TXN4
SATA_TXN4
SATA_TXP4
C799
C798
3900p/25V_4 SATA_TXN4_C
SATA_TXP4_C B
3900p/25V_4
27 SATA_TXP4
HD Audio I/F(CODEC& iHDMI) RTC BATTERY
R693 IHM@33_4 +3VPCU +VCCRTC

HDA_SDOUT_HDMI 6
HDA_SDIN2 R705 *IH M@0_4
HDA_SDOUT_R R691 33_4 D508 CH500H-40
ACZ_SDOUT_AUDIO 29
HDA_SDIN1 R706 IHM@0_4
HDA_SDIN_HDMI 6
R708 IHM@33_4 R_3VRTC D512 CH500H-40
HDA_SYNC_HDMI 6
R676 IHM@33_4
HDA_RST#_HDMI 6
HDA_SYNC_R R707 33_4 C648
ACZ_SYNC_AUDIO 29
HDA_RST#_R R680 33_4
ACZ_RST#_AUDIO 29
1u/10V_6
R683 IHM@33_4 R588
HDA_BIT_CLK_HDMI 6
HDA_BIT_CLK_R R679 33_4 1K_4 +5VPCU
BIT_CLK_AUDIO 29
South Bridge Strap Pin (1/3) B2A
RTC_N02 1 3 R59 1 2K/F_4 R597 2K/F_4
C3A
Pin Name Strap description Sampled Configuration PU/PD Q505
MMBT3904
R589
0 = The Flash Descriptor Security will be overridden.
HDA_DOCK_EN/ Flash Descriptor Security This strap should only be enabled in manufacturing
PW ROK 1 = The security measures defined CN510 6.8K/F_4
Override Strap environments using an external pull-up resistor.
GPIO33 in the Flash Descriptor will be in effect 1
1
2
A 2 RTC_N03 R587 15K_4 A
PCI Express Lane Reversal Internal PU

RTC_CONN
SATALED# PW ROK
(Lanes 1-4)
ICH_TP3 HDA_SDOUT Description

TP3 XOR Chain Entrance PW ROK ICH_TP3 R280 *1K_4
0 0 RSVD
14 ICH_TP3
XOR Chain Entrance /PCI Express*
0 1 Enter XOR Chain PROJECT : TE1M
HDA_SDOUT Port Config 1 bit 1(Port 1-4) PW ROK 1 0 Normal opration(Default) HDA_SDOUT_R R697 *1K_4 +3V_HDA_IO_ICH Size Document Number Rev
E3D
1 1 Set PCIE port config bit 1 PU +1.5V SB (1/4)- HOST
5 4 3 2 1
5 4 3 2 1
BOM Option Table Reference Description

PCI/PCI-E/USB/DMI/SPI IV@ INT VGA
EV@ EXT VGA
23,24 AD[0..31]
iTPM@ Internal TPM
U512B U512D
AD0 D11 F1 REQ0# N29 V27 DMI_RXN0
AD0 REQ0# REQ0# 24 27 PCIE_RXN1 PERN1 DMI0RXN DMI_RXN0 6
AD1
AD2
C8
D9
AD1 PCI GNT0# G4
B6
GNT0#
REQ1# GNT0# 24 27 PCIE_RXP1
C249 0.1u/10V_4 PCIE_TXN1_C
N28
P27
PERP1 DMI0RXP V26
U29
DMI_RXP0
DMI_TXN0 DMI_RXP0 6
AD2 REQ1#/GPIO50 REQ1# 23 27 PCIE_TXN1 PETN1 DMI0TXN DMI_TXN0 6
AD3 E12 A7 GNT1# C248 0.1u/10V_4 PCIE_TXP1_C P26 U28 DMI_TXP0
AD3 GNT1#/GPIO51 GNT1# 23 27 PCIE_TXP1 PETP1 DMI0TXP DMI_TXP0 6
AD4 E9 F13 REQ2#
AD5 AD4 REQ2#/GPIO52 GNT2# T103 DMI_RXN1
C9 F12 25 PCIE_RXN2 L29 Y27 DMI_RXN1 6
D AD6 AD5 GNT2#/GPIO53 REQ3# PERN2 DMI1RXN DMI_RXP1 D
E10 E6 25 PCIE_RXP2 L28 Y26 DMI_RXP1 6
AD7 AD6 REQ3#/GPIO54 GNT3# C229 IV@0.1u/10V_4 PCIE_TXN2_C PERP2 DMI1RXP DMI_TXN1
B7 F6 25 PCIE_TXN2 M27 W 29 DMI_TXN1 6
AD8 AD7 GNT3#/GPIO55 IV@0.1u/10V_4 PCIE_TXP2_C PETN2 DMI1TXN DMI_TXP1
C7 25 PCIE_TXP2 C228 M26 W 28
AD8 PETP2 DMI1TXP DMI_TXP1 6
AD9 C5 D8 CBE0#
AD9 C/BE0# CBE0# 23,24
AD10 G11 B4 CBE1# J29 AB27 DMI_RXN2
AD10 C/BE1# CBE1# 23,24 25 PCIE_RXN3 PERN3 DMI2RXN DMI_RXN2 6
AD11 F8 D6 CBE2# CBE2# 23,24 J28 AB26 DMI_RXP2
AD12 AD11 C/BE2# CBE3# 25 PCIE_RXP3 PCIE_TXN3_C PERP3 DMI2RXP DMI_TXN2 DMI_RXP2 6
F11 A5 CBE3# 23,24 25 PCIE_TXN3 C231 0.1u/10V_4 K27 AA29
AD13 AD12 C/BE3# PCIE_TXP3_C PETN3 DMI2TXN DMI_TXP2 DMI_TXN2 6
E7 25 PCIE_TXP3 C230 0.1u/10V_4 K26 AA28
AD13 PETP3 DMI2TXP DMI_TXP2 6
AD14 A3 D3 IRDY#
AD14 IRDY# IRDY# 23,24 +1.5V_PCIE_ICH
AD15 D2 E3 PAR G29 AD27 DMI_RXN3
AD15 PAR PAR 23,24 25 PCIE_RXN4 PERN4 DMI3RXN DMI_RXN3 6
AD16 F10 R1 PCIRST# G28 AD26 DMI_RXP3
AD17 AD16 PCIRST# DEVSEL# PCIRST# 23,24 25 PCIE_RXP4 PERP4 DMI3RXP DMI_TXN3 DMI_RXP3 6
D5 C6 25 PCIE_TXN4 C232 EV@0.1u/10V_4 PCIE_TXN4_C H27 AC29
AD18 AD17 DEVSEL# PERR# DEVSEL# 23,24 EV@0.1u/10V_4 PCIE_TXP4_C PETN4 DMI3TXN DMI_TXP3 DMI_TXN3 6
D10 E4 25 PCIE_TXP4 C233 H26 AC28
AD18 PERR# PERR# 23 PETP4 DMI3TXP DMI_TXP3 6
AD19 B3 C2 LOCK# R258
AD20 AD19 PLOCK# SERR# CLK_PCIE_ICH#
F7 J4 SERR# 23 26 PCIE_RXN5 E29 T26 CLK_PCIE_ICH# 2 24.9/F_4
AD21 AD20 SERR# STOP# PERN5 DMI_CLKN CLK_PCIE_ICH
C3 A4 STOP# 23,24 26 PCIE_RXP5 E28 T25 CLK_PCIE_ICH 2
AD22 AD21 STOP# TRDY# C234 0.1u/10V_4 PCIE_TXN5_C PERP5 DMI_CLKP
F3 F5 TRDY# 23,24 26 PCIE_TXN5 F27
AD23 AD22 TRDY# FRAME# PCIE_TXP5_C PETN5
F4 D7 26 PCIE_TXP5 C235 0.1u/10V_4 F26 AF29
AD23 FRAME# FRAME# 23,24 PETP5 DMI_ZCOMP
AD24 C1 AF28 DMI_IRCOMP_R
AD25 AD24 PLT_RST-R# D MI_IRCOMP
G7 C14 25 PCIE_RXN6 C29
AD26 AD25 PLTRST# PCLK_ICH PERN6/GLAN_RXN USBP0-
H7 AD26 PCICLK D4 PCLK_ICH 2 25 PCIE_RXP6 C28 PERP6/GLAN_RXP USBP0N AC5 USBP0- 26
AD27 D1 R2 PCI_PME# C237 0.1u/10V_4 PCIE_TXN6_C D27 AC4 USBP0+
AD27 PME# PCI_PME# 23,24 25 PCIE_TXN6 PETN6/GLAN_TXN USBP0P USBP0+ 26
AD28 G5 C236 0.1u/10V_4 PCIE_TXP6_C D26 AD3 USBP1-
AD28 25 PCIE_TXP6 PETP6/GLAN_TXP USBP1N USBP1- 26
AD29 H6 AD2 USBP1+
AD29 USBP1P USBP1+ 26
AD30 G1 SPI_CLK D23 AC1 USBP2-
AD30 SPI_CLK USBP2N USBP2- 26
AD31 H3 SPI_CS0# D24 AC2 USBP2+
AD31 SPI_CS1# SPI_CS0# USBP2P USBP3- USBP2+ 26
F23 AA5 USBP3- 19
SPI_CS1#/GPIO58/CLGPIO6 USBP3N
R373 0_4 INTA#_R J5
Interrupt I/F H4 INTE# SPI_MOSI D25
USBP3P
AA4
AB2
USBP3+
USBP4-
USBP3+ 19
24 INTA# PIRQA# PIRQE#/GPIO2 SPI_MOSI USBP4N USBP4- 26
R374 *0_4 INTB#_R E1 K6 INTF# SPI_MISO E23 AB3 USBP4+
PIRQB# PIRQF#/GPIO3 SPI_MISO USBP4P USBP4+ 26
23 INTC# R372 0_4 INTC#_R J6 F2 INTG# AA1 USBP5-
PIRQC# PIRQG#/GPIO4 USBOC#0 USBP5N USBP5+ USBP5- 25
R387 *0_4 INTD#_R C4 G2 INTH# CRT_SENSE# 20,28 26,28 USBOC#0 N4 AA2
C PIRQD# PIRQH#/GPIO5 USBOC#1 OC0#/GPIO59 USBP5P USBP6- USBP5+ 25 C
N5 W5 USBP6- 27
OC1#/GPIO40 USBP6N
ICH9M REV 1.0 R389 *0_4 USBOC#2
USBOC#3
N6
P6
OC2#/GPIO41 USB USBP6P
W4
Y3
USBP6+
USBP7-
USBP6+ 27
OC3#/GPIO42 USBP7N USBP7- 27
B2A USBOC#4
USBOC#5
M1
OC4#/GPIO43 USBP7P
Y2 USBP7+
USBP8- USBP7+ 27
N2 W1 USBP8- 25
R731 0_4 USBOC#6 OC5#/GPIO29 USBP8N USBP8+
27,28 USBOC#6_7 M4 W2 USBP8+ 25
OC6#/GPIO30 USBP8P
B2A R732 0_4 USBOC#7 M3
OC7#/GPIO31 USBP9N
V2 USBP9-
USBP9- 27
USBOC#8 N3 V3 USBP9+
OC8#/GPIO44 USBP9P USBP9+ 27
R297 EV@0_4 GFXRST# USBOC#9 N1 U5 USBP10- T533
GFXRST# 18 USBOC#10 OC9#/GPIO45 USBP10N USBP10+
P5 U4 T534
USBOC#11 OC10#/GPIO46 USBP10P USBP11- T530
P3 U1
OC11#/GPIO47 USBP11N
PLT_RST-R# R298 0_4 PLT_RST#_NB
PLT_RST#_NB 6 PCI ROUTING USBP11P U2 USBP11+ T531
TABLE IDSEL INTERUPT DEVICE USBRBIAS_PN AG2

USBRBIAS
AG1 USBRBIAS#
+3V_S5
REQ0# / GNT0# AD17 INTA#/INTB# OZ129T R356 ICH9M REV 1.0
REQ1# / GNT1# AD20 INTC#/INTD# CB1410 22.6/F_4
C736
0.1u/50V_6 iTPM SERIAL EEPROM +3V_SPI

+3V_SPI
U18 C3B
R231 *IHM_iTPM@0_6
+3VPCU
2 U13
4 PLTRST# SPI_MISO R251 IHM_iTPM@15_4SPI_MS IO_R 2 8 R233 IHM__iTPM@0_4
PLTRST# 21,25,26,27,28 SO VDD +3V_S5
1
R299 SPI_MOSI R262 IHM_iTPM@15_4SPI_MO S I_R 5 7 C218
TC7SH08FU R650 SI HOLD
SPI_CLK R259 IHM_iTPM@15_4SPI_CL K_R 6 3 IHM_iTPM@0.1u/10V_4
SCK WP
100K_4 *100K_6
SPI_CS0# R264 IHM_iTPM@15_4SPI_CS 0# _R 1 4
B CE VSS B
IHM__iTPM@W 25X1 6 VSSIG
South Bridge Strap Pin (2/3) PCI PULL-UP USBOC# PULL-UP
Pin Name Strap description Sampled Configuration PU/PD RP516

+3V
RP519
IRDY# 6 5 USBOC#7 6 5 +3V_S5
PCI Express Port LOCK# REQ2# USBOC#4 USBOC#2
HDA_SYNC PWROK 0 = Default STOP#
7 4
FRAME# USBOC#5
7 4
USBOC#1
8 3 8 3
Config 1 bit 0 (Port 1-4) 1 = Setting bit 0 INTB#_R 9 2 REQ1# USBOC#6 9 2 USBOC#0
10 1 DEVSEL# 10 1 USBOC#3
+3V +3V_S5
PCI Express Port 0 = Setting bit 2 8.2K_10P8R

10K_10P8R
GNT2# / GPIO53 PWROK
Config 2 bit 2 (Port 5-6) 1 = Default
0 = DMI for ESI-compatible +3V RP55

GNT1# / GPIO51 ESI Strap(Server Only) PWROK RP517 USBOC#8 8 7 +3V_S5
1 = Default REQ0# 6 5 USBOC#10 6 5
INTG# 7 4 INTD#_R USBOC#9 4 3
8 3 REQ3# USBOC#11 2 1
0 = "top-block swap" mode 9 2 INTH#
GNT3# / GPIO55 Top-Block Swap Override PWROK GNT3# R376 *1K_4
+3V 10 1 PERR# 10K_8P4R
1 = Default
8.2K_10P8R
A A
Integrated TPM Enable 0 = INT TPM disable(Default)
SPI_MOSI CLPWROK SPI_MOSI R607 *iTPM@20K_4 +3V_S5
1 = INT TPM enable
+3V
RP518
PCI_GNT#0 SPI_CS#1 Boot Location TRDY# 6 5
GNT0# Boot BIOS Selection 0 PWROK GNT0# R375 *1K_4 7 4 SERR#
INTF# 8 3 INTE#
0 1 SPI(Default) 9 2 INTA#_R
INTC#_R
+3V 10 1
1 0 PCI 8.2K_10P8R PROJECT : TE1M

SPI_CS1# / SPI_CS1# R267 *1K_4 Size Document Number Rev
Boot BIOS Selection 1 CLPWROK
GPIO58 / CLGPIO6 SB (2/4)- PCIE/PCI/USB E3D
1 1 LPC
5 4 3 2 1
5 4 3 2 1
BOM Option Table

+3V_S5
iTPM@ Internal TPM
R316 2.2K_4 SCLK
U512C
R325 2.2K_4 SDATA SCLK G16 AH23 BOARD_ID3
2,21,25,27 SCLK SMBCLK SATA0GP/GPIO21
SDATA A13 AF19 BOARD_ID2
2,21,25,27 SDATA SMBDATA SATA1GP/GPIO19
R324 10K_4 ICH_GPIO60 ICH_GPIO60 E17 AE21 ICH_GPIO36
SMB_CLK_ME LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36 ICH_GPIO37
C17 AD20
R323 10K_4 SMB_CLK_ME SMB_DATA_ME SMLINK0 SATA5GP/GPIO37
B18
SMLINK1 14M_ICH
H1 14M_ICH 2
R315 10K_4 SMB_DATA_ME RI# CLK14 CLKUSB_48 +3V
F19 AF3 CLKUSB_48 2
RI# CLK48
R313 10K_4 RI# T529 SUS_STAT# R4 P1 SUSCLK T527
D SUS_STAT#/LPCPD# SUSCLK D
SYS_RST# G19 ICH_GPIO36 R304 10K_4
3 SYS_RST# SYS_RESET#
R312 10K_4 SYS_RST# C16 SUSBR# R332 0_4 SUSB#
SLP_S3# SUSB# 28
PM_SYNC# M6 E16 SUSCR# R334 0_4 SUSC# ICH_GPIO37 R300 10K_4
6 PM_SYNC# PMSYNC#/GPIO0 SLP_S4# SUSC# 28
R322 10K_4 SMB_ALERT# G17 SLP_S5#
SLP_S5# +3V_S5
SMB_ALERT# A17 T96
SMBALERT#/GPIO11 ICH_GPIO26
C10
+3V PM_STPPCI# S4_STATE#/GPIO26 T104 PM_BATLOW# R333 8.2K_4
2 PM_STPPCI# A14
PM_STPCPU# STP_PCI# ICH_PWROK
2 PM_STPCPU# E19 G20
R317 *10K_4 PM_STPPCI# STP_CPU# PW ROK DNBSWON# R368 *10K_4
CLKRUN# L4 M2 PM_DPRSLPVR_R R371 0_4 PM_DPRSLPVR
24,28 CLKRUN# CLKRUN# DPRSLPVR/GPIO16 PM_DPRSLPVR 6,33
R321 *10K_4 PM_STPCPU#
PCIE_WAKE# E20 B13 PM_BATLOW# PM_LAN_ENABLE_R R284 0_4
25,26,27 PCIE_WAKE# W AKE# BATLOW #
R703 8.2K_4 CLKRUN# SERIRQ M5
23,25,28 SERIRQ SERIRQ
THERM_ALERT# AJ23 R3 DNBSWON#
+3V_S5 3 THERM_ALERT# THRM# PW RBTN# DNBSWON# 28
VR_PWRGD_CLKEN D21 D20 PM_LAN_ENABLE_R R282 *0_4 PM_RSMRST#_R
10K_4 PCIE_WAKE# VRMPWRGD LAN_RST#
R288
ICH_TP11 A20 D22 PM_RSMRST#_R
+3V T93 TP11 RSMRST#
KBSMI#_ICH AG19 R5 CK_PWRGD
GPIO1 CK_PW RGD CK_PWRGD 2
R342 10K_4 SERIRQ Port_C# AH21
29 Port_C# GPIO6
SB_GPIO7 AG21 R6 ECPWROK R369 0_4
26 SB_GPIO7 GPIO7 CLPW ROK MPWROK 6
R274 8.2K_4 THERM_ALERT# SCI# A21 +3V +3V
28 SCI# GPIO8
FM_DET C12 B16 SLP_M#
GPIO12 SLP_M#
R314 10K_4 KBSMI#_ICH B2A T94
ICH_GPIO13
BOARD_ID0
C21
GPIO13 CL_CLK0
T97
AE18 F24 CL_CLK0 6
GPIO17 CL_CLK0 R613 R287
BOARD_ID1 K1 B19 CL_CLK1
GPIO18 CL_CLK1 CL_CLK1 25
LOW_DET AF8 GPIO20
R303 *10K_4 SCI# BOARD_ID4 AJ22 F22 CL_DATA0 3.24K/F_6 *3.24K/F_6
SCLOCK/GPIO22 CL_DATA0 CL_DATA0 6
SB_GPIO27 A9 C19 CL_DATA1
26 SB_GPIO27 GPIO27 CL_DATA1 CL_DATA1 25
R704 10K_4 ICH_GPIO35 FM_INT D19 CL_VREF0_SB CL_VREF1_SB
26 FM_INT GPIO28
ICH_GPIO35 L1 C25 CL_VREF0_SB
R307 10K_4 ICH_GPIO38 ICH_GPIO38 SATACLKREQ#/GPIO35 CL_VREF0 CL_VREF1_SB
AE19 A19
C ICH_GPIO39 SLOAD/GPIO38 CL_VREF1 C705 R608 C277 R294 C
AG22
R277 10K_4 ICH_GPIO39 ICH_GPIO48 SDATAOUT0/GPIO39 CL_RST#0
T90 AF21 F21 CL_RST#0 6
DMI_TERM_SEL SDATAOUT1/GPIO48 CL_RST0# CL_RST#1 0.1u/10V_4 453/F_4 *0.1u/10V_4 *453/F_4
AH24 D18 CL_RST#1 25
CLGPIO5 GPIO49 CL_RST1#
A8
GPIO57/CLGPIO5 ICH_GPIO24
A16
MEM_LED/GPIO24
SCI#(PU to MAIN or S5) 27 SPKR
SPKR M7
SPKR GPIO10/SUS_PW R_ACK C18 HDPACT
HDPACT 22
+3V_S5 R278 0_4 MCH_ICH_SYNC#_R AJ24 C11 ICH_GPIO14
leakage issue 6 MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT
ICH_TP3 B21 C20 HDPINT
12 ICH_TP3 TP3 WOL_EN/GPIO9 HDPINT 22
R302 10K_4 SCI# ICH_TP8 AH20
T92 TP8
ICH_TP9 AJ20
T91 TP9
ICH_TP10 AJ21
T518 TP10
+3V_S5 ICH9M REV 1.0 +3V_S5
Enable iTPM(PU to PCU or S5?)
R347 *iTPM@10K_4 CLGPIO5
R344 *iTPM@100/F_4 +3V_S5 ICH_GPIO24 R320 *10K_4

C264
HDPACT R319 *10K_4
DELAY_VR_PWRGOOD need PU 2K to +3V.
0.1u/16V_4 ICH_GPIO14 R335 10K_4
+3V ZS2 PU at power side(NEED CHECK PWR CKT)
HDPINT R289 *10K_4
R271 *10K_4 MCH_ICH_SYNC#_R
DELAY_VR_PWRGOOD 1 U17 R290 *10K_4
3,6,33 DELAY_VR_PWRGOOD
4 ICH_PWROK
ECPWROK 2
28 ECPWROK
TC7SH08FU
R310
10K_4
R309 100K_4
B B
+3V
C260
Board ID ID4 ID3 ID2 ID1 ID0 M/L FM

+3V_S5 R713 *0_4
0.1u/10V_4
NEW CARD H
CARD BUS L B2A
CCFL Panel H R729 Q515
U16 LED Panel L R729 Always mount MMBT3906
1 5 10K_4
33 VR_PWRGD_CK410#
VR_PWRGD_CK410# 2 W/ G-SENSOR H PM_RSMRST#_R 3 1 RSMRST# 28
3 4 VR_PWRGD_CLKEN W/O G-SENSOR L FM_DET
FM_DET 26
NC7SZ04 Main stream ID H
R260 Low Cost ID L R714
100K_4 R730 10K_4 R712 4.7K_4 +3V_S5
B2A W/ HDMI H
W/O HDMI L *10K_4
D521
W/O Low Cost board H 3 BAV99
W Low Cost L
W/O FM H
W FM L
South Bridge Strap Pin (3/3) 3

D517
BAV99
+3V RAMP1 + 3V +3V +3V +3V B2A +3V RAMP1
A Pin Name Strap description Sampled Configuration PU/PD R711 A

2.2K_4
R281 R649 R306 R701 R311 R671 R671 Always mount
GPIO20 Reserved PWROK HDMI@10K _4 MAIN@10K_4 GS@10K_4 LCD@10K_4 NEW@10K_4 10K_4
BOARD_ID4 BOARD_ID3 BOARD_ID2 BOARD_ID1 BOARD_ID0 LOW_DET

LOW_DET 26
0 = Default
SPKR No Reboot PWROK
1 = No Reboot mode
SPKR R341 *1K_4 +3V Quanta Computer Inc.
R276 R648 R305 R702 R308 R670
*HDMI@10K _4 LOW@10K_4 *GS@10K_4 LED@10K_4 CB@10K_4 *10K_4 PROJECT : TE1M

0 = for desktop applications Size Document Number Rev
DMI Termination 1 = for mobile applications
GPIO49 PWROK DMI_TERM_SEL R269 *1K_4
SB (3/4)- GPIO E3D
Voltage Internal PU
Date: Monday, July 28, 2008 Sheet 14 of 40
5 4 3 2 1
5 4 3 2 1
BOM Option Table

N/A N/A
U512F
+VCCRTC A23 A15 +1.05V_ICH R293 0_8
+VCCRTC VCCRTC VCC1_05[1] +1.05V
B15
+SB_V5REF VCC1_05[2]
C266 C257 A6 C15 C288 C297
V5REF VCC1_05[3]
D15 U512E
+5VPCU_ICH_V5REF_SUS VCC1_05[4]
0.1u/10V_4 0.1u/10V_4 AE1 E15 0.1u/10V_4 0.1u/10V_4 AA26 H5
V5REF_SUS VCC1_05[5] VSS[1] VSS[107]
F15 AA27 J23
VCC1_05[6] VSS[2] VSS[108]
AA24 L11 AA3 J26
VCC1_5_B[1] VCC1_05[7] VSS[3] VSS[109]
AA25 L12 AA6 J27
VCC1_5_B[2] VCC1_05[8] +1.5V_ICH_VCCDMIPLL VSS[4] VSS[110]
C2B AB24
VCC1_5_B[3] VCC1_05[9]
L14 L21 1uh_6 +1.5V AB1
VSS[5] VSS[111]
AC22
AB25 L16 AA23 K28
VCC1_5_B[4] VCC1_05[10] C227 C222 VSS[6] VSS[112]
AC24 L17 AB28 K29
D VCC1_5_B[5] VCC1_05[11] VSS[7] VSS[113] D
D518 2 CH751H-40PT
1 AC25 L18 AB29 L13
+3V VCC1_5_B[6] VCC1_05[12] VSS[8] VSS[114]
AD24 M11 0.01u/16V_4 10u/10V_8 AB4 L15
C323 VCC1_5_B[7] VCC1_05[13] VSS[9] VSS[115]
AD25 M18 AB5 L2
VCC1_5_B[8] VCC1_05[14] VSS[10] VSS[116]
AE25 P11 AC17 L26
VCC1_5_B[9] VCC1_05[15] VSS[11] VSS[117]
+5V R718 100/F_6 1uF/10V_4 AE26 P18 AC26 L27
VCC1_5_B[10] VCC1_05[16] VSS[12] VSS[118]
AE27 T11 AC27 L5
VCC1_5_B[11] VCC1_05[17] +1.05V_ICH_DMI VSS[13] VSS[119]
AE28 T18 R301 0_6 +1.05V_ICH AC3 L7
VCC1_5_B[12] VCC1_05[18] VSS[14] VSS[120]
AE29 U11 AD1 M12
VCC1_5_B[13] VCC1_05[19] C274 C263 VSS[15] VSS[121]
F25 U18 AD10 M13
VCC1_5_B[14] VCC1_05[20] VSS[16] VSS[122]
G25 V11 AD12 M14
VCC1_5_B[15] VCC1_05[21] VSS[17] VSS[123]
+3V_S5 D17 2 CH751H-40PT
1 H24 V12 4.7u/10V_6 10u/6.3V_8 AD13 M15
VCC1_5_B[16] VCC1_05[22] VSS[18] VSS[124]
H25 V14 AD14 M16
C324 VCC1_5_B[17] VCC1_05[23] VSS[19] VSS[125]
J24 V16 AD17 M17
VCC1_5_B[18] VCC1_05[24] +1.05V_ICH_IO VSS[20] VSS[126]
J25 V17 AD18 M23
VCC1_5_B[19] VCC1_05[25] VSS[21] VSS[127]
+5V_S5 R363 100/F_6 1uF/10V_4 K24 V18 AD21 M28
VCC1_5_B[20] VCC1_05[26] +1.05V_ICH_IO VSS[22] VSS[128]
K25 R279 0_6 +1.05V AD28 M29
VCC1_5_B[21] VSS[23] VSS[129]
L23 R29 AD29 N11
VCC1_5_B[22] VCCDMIPLL VSS[24] VSS[130]
L24 AD4 N12
VCC1_5_B[23] C271 C272 C269 VSS[25] VSS[131]
L25 W 23 AD5 N13
VCC1_5_B[24] VCC_DMI[1] VSS[26] VSS[132]
C3A +1.5V_PCIE_ICH
M24
VCC1_5_B[25] VCC_DMI[2]
Y23
0.1u/10V_4 0.1u/10V_4 4.7u/10V_6
AD6
VSS[27] VSS[133]
N14
M25 AD7 N15
VCC1_5_B[26] VSS[28] VSS[134]
N23 AB23 AD9 N16
+1.5V_PCIE_ICH VCC1_5_B[27] V_CPU_IO[1] VSS[29] VSS[135]
+1.5V L24 1 2 BLM21PG221SN1D_8 N24 AC23 AE12 N17
VCC1_5_B[28] V_CPU_IO[2] VSS[30] VSS[136]
N25 AE13 N18
VCC1_5_B[29] +3V_DMI_ICH R603 0_6 VSS[31] VSS[137]
P24 AG29 +3V AE14 N26
VCC1_5_B[30] VCC3_3[1] VSS[32] VSS[138]
+ C250 C244 C254 C253 P25 AE16 N27
VCC1_5_B[31] +3V_SATA_ICH C701 VSS[33] VSS[139]
R24 AJ6 AE17 P12
VCC1_5_B[32] VCC3_3[2] VSS[34] VSS[140]
*220u/2. 5 V_7343 10u/6.3V_8 10u/6.3V_8 2.2u/6.3V_6 R25 AE2 P13
VCC1_5_B[33] VSS[35] VSS[141]
R26 AC10 0.1u/10V_4 AE20 P14
VCC1_5_B[34] VCC3_3[7] VSS[36] VSS[142]
R27 AE24 P15
VCC1_5_B[35] VSS[37] VSS[143]
T24 AD19 AE3 P16
VCC1_5_B[36] VCC3_3[3] VSS[38] VSS[144]
T27 AF20 R687 0_6 +3V AE4 P17
VCC1_5_B[37] VCC3_3[4] VSS[39] VSS[145]
T28 AG24 AE6 P2
VCC1_5_B[38] VCC3_3[5] +3V_VCCPCORE_ICH C763 VSS[40] VSS[146]
T29 AC20 AE9 P23
VCC1_5_B[39] VCC3_3[6] VSS[41] VSS[147]
U24 AF13 P28
VCC1_5_B[40] VSS[42] VSS[148]
U25 B9 0.1u/10V_4 AF16 P29
VCC1_5_B[41] VCC3_3[8] VSS[43] VSS[149]
V24 F9 AF18 P4
VCC1_5_B[42] VCC3_3[9] VSS[44] VSS[150]
V25 G3 AF22 P7
VCC1_5_B[43] VCC3_3[10] +3V_PCI_ICH VSS[45] VSS[151]
U23 G6 AH26 R11
VCC1_5_B[44] VCC3_3[11] VSS[46] VSS[152]
W 24 J2 R296 0_6 +3V AF26 R12
C VCC1_5_B[45] VCC3_3[12] VSS[47] VSS[153] C
W 25 J7 AF27 R13
VCC1_5_B[46] VCC3_3[13] +3V_HDA_IO_ICH C278 VSS[48] VSS[154]
K23 K7 AF5 R14
VCC1_5_B[47] VCC3_3[14] VSS[49] VSS[155]
Y24 AF7 R15
VCC1_5_B[48] +3V_HDA_IO_ICH VSS[50] VSS[156]
Y25 AJ4 0.1u/10V_4 AF9 R16
VCC1_5_B[49] VCCHDA VSS[51] VSS[157]
AG13 R17
0_8 +1.5V_SATA_ICH L25 10uh_8 +1.5V_APLL_ICH +3V_VCCSUSHDA VSS[52] VSS[158]
+1.5V R328 AJ19 AJ3 AG16 R18
VCCSATAPLL VCCSUSHDA VSS[53] VSS[159]
AG18 R28
C281 R345 VSS[54] VSS[160]
C280 AC16 AC8 +TP_VCCSUS1_05_ICH_1 T98 0_8 +3V AG20 T12
VCC1_5_A[1] VCCSUS1_05[1] +TP_VCCSUS1_05_ICH_2 T95 VSS[55] VSS[161]
AD15 F17 AG23 T13
VCC1_5_A[2] VCCSUS1_05[2] VSS[56] VSS[162]
10u/10V_8 1u/6.3V_4 AD16 C315 C318 C316 AG3 T14
VCC1_5_A[3] +TP_VCCSUS1_5_ICH_1 T100 VSS[57] VSS[163]
AE15 AD8 AG6 T15
AF15 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 AG9 T16
VCC1_5_A[5] +VCCSUS1_5_INT_ICH VSS[59] VSS[165]
AG15 F18 AH12 T17
+1.5V_SATA_ICH VCC1_5_A[6] VCCSUS1_5[2] VSS[60] VSS[166]
AH15 AH14 T23
VCC1_5_A[7] VSS[61] VSS[167]
AJ15 AH17 B26
VCC1_5_A[8] +3VPCU_ICH VSS[62] VSS[168]
C308 A18 C292 R409 0_6 +1.5V AH19 U12
VCCSUS3_3[1] VSS[63] VSS[169]
AC11 D16 AH2 U13
VCC1_5_A[9] VCCSUS3_3[2] C331 VSS[64] VSS[170]
1u/6.3V_4 AD11 D17 0.1u/10V_4 AH22 U14
AE11 E22 AH25 U15
AF11 0.1u/10V_4 AH28 U16
VCC1_5_A[12] VSS[67] VSS[173]
AG10 AH5 U17
+1.5V_SATA_ICH VCC1_5_A[13] VSS[68] VSS[174]
AG11 AF1 AH8 AD23
AH10 R360 0_6 +1.5V_S5 AJ12 U26
C290 VCC1_5_A[15] VSS[70] VSS[176]
AJ10 T1 AJ14 U27
T2 C319 AJ17 U3
1u/6.3V_4 AC9 T3 AJ8 V1
T4 0.1u/10V_4 B11 V13
AC18 T5 B14 V15
+1.5V_SATA_ICH VCC1_5_A[18] VCCSUS3_3[10] VSS[75] VSS[181]
AC19 T6 B17 V23
U6 R318 0_6 +3V_S5 B2 V28
AC21 U7 B20 V29
VCC1_5_A[20] VCCSUS3_3[13] +3VPCU_USB_ICH VSS[78] VSS[184]
V6 R355 0_8 B23 V4
G10 V7 B5 V5
+1.5V_USB_ICH VCC1_5_A[21] VCCSUS3_3[15] C320 C313 C317 VSS[80] VSS[186]
+1.5V R337 0_8 G9 W6 B8 W 26
W7 C26 W 27
C311 AC12 Y6 0.022u/16V_4 0.022u/16V_4 0.1u/10V_4 C27 W3
AC13 Y7 Check list: E11 Y1
0.1u/10V_4 AC14 T7 0.1U for Pin AF1 E14 Y28
E18 Y29
+VCCCL1_05_INT_ICH VSS[86] VSS[192]
AJ5 G22 E2 Y4
B VCCUSBPLL VCCCL1_05 VSS[87] VSS[193] B
E21 Y5
+1.5V_USB_ICH +VCCCL1_5_INT_ICH VSS[88] VSS[194]
AA7 G23 E24 AG28
VCC1_5_A[26] VCCCL1_5 VSS[89] VSS[195]
AB6 E5 AH6
C314 VCC1_5_A[27] C273 C265 C255 VSS[90] VSS[196]
AB7 A24 E8 AF2
VCC1_5_A[28] VCCCL3_3[1] VSS[91] VSS[197]
AC6 B24 F16 B25
VCC1_5_A[29] VCCCL3_3[2] VSS[92] VSS[198]
0.1u/10V_4 AC7 *0.1u/10V_4 *0.1u/10V_4 0.1u/10V_4 F28
VCC1_5_A[30] VSS[93]
F29 A1
VSS[94] VSS_NCTF[1]
A10 G12 A2
VCCLAN1_05[1] VSS[95] VSS_NCTF[2]
C309 0.1u/10V_4 +VCCLAN1_05_INT_ICH A11 G14 A28
G18 A29
VSS[97] VSS_NCTF[4]
A12 G21 AH1
0_6 +3VM_VCCPAUX VCCLAN3_3[1] +3VM_VCCCL3_ICH VSS[98] VSS_NCTF[5]
+3V R339 B12 R273 0_6 +3V G24 AH29
G26 AJ1
C305 +1.5V_ICH_GLANPLL_R VSS[100] VSS_NCTF[7]
A27 G27 AJ2
VCCGLANPLL VSS[101] VSS_NCTF[8]
G8 AJ28
0.1u/10V_4 VSS[102] VSS_NCTF[9]
D28 H2 AJ29
VCCGLAN1_5[1] VSS[103] VSS_NCTF[10]
D29 H23 B1
VCCGLAN1_5[2] VSS[104] VSS_NCTF[11]
E26 H28 B29
+1.5V_PCIE_ICH VCCGLAN1_5[3] VSS[105] VSS_NCTF[12]
E27 H29
VCCGLAN1_5[4] VSS[106]
+SB_VCCGLAN3_3 A26 ICH9M REV 1.0
VCCGLAN3_3
L22 1uh_6 ICH9M REV 1.0
+1.5V
C238 C245
10u/10V_8 2.2u/6.3V_6
SB Power Status and max current table(1/2)(SB left side) SB Power Status and max current table(2/2)(SB right side)
POWER PLANE S0 S3 S4/S5 Voltage I(max) Note POWER PLANE S0 S3 S4/S5 Voltage I(max) Note
+1.5V_PCIE_ICH VCCRTC X X X +VCCRTC 6uA 6uA@G3 VCC1_05 O X X +1.05V 1.634A
C252 O X X O X X
V5REF +5V 2mA VCCDMIPLL +1.5V 23mA
4.7u/10V_6 O O O 2mA O X X
V5REF_SUS +5V_S5 1mA@S3/S4/S5 VCC_DMI +1.05V 48mA
VCC1_5_B O X X +1.5V 646mA V_CPU_IO O X X +1.05V 2mA
A VCCSATAPLL O X X +1.5V 47mA VCC3_3 O X X +3V 308mA A

R605 0_6 O X X O X X
+3V VCC1_5_A +1.5V 1.342A VCCHDA +1.5V 11mA
VCCUSBPLL O X X +1.5V 11mA VCCSUSHDA O O O +1.5V_S5 11mA 1mA@S3/S4/S5
VCCLAN1_05 O X X +1.05V X Powered by Vcc1_05 in S0 VCCSUS1_05 O O O +1.05V X Powered by Vcc1_05 in S0
VCCLAN3_3 O X X +3V 19mA Tied to +3V,not +3VSUS VCCSUS1_5 O O O +1.5V X Powered by Vcc1_5_A in S0
VCCGLANPLL O X X +1.5V 23mA VCCSUS3_3 O O O +3VSUS 212mA 52mA@S3/S4/S5
VCCGLAN1_5 O X X +1.5V 80mA VCCCL1_05 O X X +1.05V X Powered by Vcc1_05 in S0

VCCGLAN3_3 O X X +3V 1mA VCCCL1_5 O X X +1.5V X Powered by Vcc1_5_A in S0
VCCCL3_3 O X X +3V 19mA Tied to +3V,not +3VSUS

PROJECT : TE1M
S ize Document Number R ev
E3D
Note:VCCSUS1_05 , VCCSUS1_5 are powered by VccSus3_3 in S3/S4/S5 SB (4/4)- POWER
5 4 3 2 1
1 2 3 4 5 6 7 8
DDR2 Dual channel A/B PULL UP BOM Option Table

N/A N/A
A A
M_A_A[14..0]
M_A_A[14..0] 7,17
M_B_A[14..0]
M_B_A[14..0] 7,17
DDRII A CHANNEL DDRII B CHANNEL
+SMDDR_VTERM +SMDDR_VTERM
C160 C171 C140 C144 C184 C176 C168 C159 C155 C190 C189 C191 C145 C196 C174 C141 C154 C142 C192 C198 C173 C167 C158 C178 C194 C163
0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_ 4
Place one cap close to every 2 pull-up resistor terminated to SMDDR_VTERM
B B
M_A_A3 RP28 1 2 56X2 +SMDDR_VTERM

M_A_A1 3 4
M_A_A9 RP33 1 2 56X2 M_A_A7 RP36 1 2 56X2 +SMDDR_VTERM

M_A_A5 3 4 M_A_A6 3 4
M_A_A2 RP31 1 2 56X2 RP41 1 2 56X2

6,17 M_CKE3
M_A_A4 3 4 7,17 M_B_BS#2 3 4
M_A_A11 RP38 1 2 56X2 RP18 1 2 56X2

6,17 M_ODT1
6,17 M_CKE1 3 4 6,17 M_CS#1 3 4
RP37 1 2 56X2
6,17 M_CKE0
M_A_A8 3 4 RP19 1 2 56X2
6,17 M_ODT3
7,17 M_B_BS#0 3 4
M_A_A12 RP39 1 2 56X2

3 4 M_A_A10 RP24 1 2 56X2
7,17 M_A_BS#2
7,17 M_A_BS#0 3 4
RP25 1 2 56X2
7,17 M_A_BS#1
M_A_A0 3 4 RP21 1 2 56X2
7,17 M_A_CAS#
7,17 M_A_WE# 3 4
C C
RP23 1 2 56X2
6,17 M_CS#0
7,17 M_A_RAS# 3 4
M_B_A10 RP26 1 2 56X2 +SMDDR_VTERM

3 4 RP22 1 2 56X2
7,17 M_B_WE# 7,17 M_B_CAS#
6,17 M_CS#3 3 4
M_B_A3 RP29 1 2 56X2

M_B_A1 3 4 M_B_A6 RP40 1 2 56X2
6,17 M_CKE4 3 4
RP27 1 2 56X2
7,17 M_B_BS#1
M_B_A0 3 4 RP20 1 2 56X2
6,17 M_ODT2
7,17 M_B_RAS# 3 4
M_B_A7 RP34 1 2 56X2

M_B_A11 3 4 6,17 M_ODT0 RP16 1 2 56X2
M_A_A13 3 4
M_B_A8 RP32 1 2 56X2

M_B_A5 3 4 M_B_A13 RP17 1 2 56X2
6,17 M_CS#2 3 4
M_B_A2 RP30 1 2 56X2

M_B_A4 3 4
M_B_A9 RP35 1 2 56X2

D M_B_A12 3 4 M_B_A14 R201 56_4 +SMDDR_VTERM D
M_A_A14 R202 56_4 +SMDDR_VTERM

PROJECT : TE1M
E3D
DDR RES. ARRAY
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
BOM Option Table

DDR II DIMM Socket Reference Description
M_A_DM[0..7] 7
M_A_DQ[0..63] 7 M_B_DM[0..7] 7 N/A N/A
M_A_DQS[0..7] 7 M_B_DQ[0..63] 7
M_A_DQS#[0..7] 7 M_B_DQS[0..7] 7
M_A_A[0..14] 7,16 M_B_DQS#[0..7] 7
M_B_A[0..14] 7,16
SMDDR_VREF_DIMM SMDDR_VREF_DIMM
+1.8VSUS +1.8VSUS
+1.8VSUS +1.8VSUS
CN507 CN506
1 2 1 2
VREF VSS46 VREF VSS46
3 4 M_A_DQ4 3 4 M_B_DQ4
A
M_A_DQ1 VSS47 DQ4 M_A_DQ0 M_B_DQ1 VSS47 DQ4 M_B_DQ5
A
5 6 5 6 +1.8VSUS
M_A_DQ5 DQ0 DQ5 M_B_DQ0 DQ0 DQ5
7 8 7 8
DQ1 VSS15 DQ1 VSS15
9 10 M_A_DM0 9 10 M_B_DM0
M_A_DQS#0 VSS37 DM0 M_B_DQS#0 VSS37 DM0
11 12 11 12
DQS#0 VSS5 DQS#0 VSS5
M_A_DQS0 13 14 M_A_DQ7 M_B_DQS0 13 14 M_B_DQ6
DQS0 DQ6 DQS0 DQ6
15 16 M_A_DQ6 15 16 M_B_DQ3
M_A_DQ2 VSS48 DQ7 M_B_DQ2 VSS48 DQ7 + C612
17 18 17 18 C603 C609 C595 C600 C597
DQ2 VSS16 DQ2 VSS16
M_A_DQ3 19 20 M_A_DQ13 M_B_DQ7 19 20 M_B_DQ12
DQ3 DQ12 M_A_DQ9 DQ3 DQ12 M_B_DQ13
21 22 21 22 330u/2.5V_3528 2.2u/6.3V_6 2.2u/6.3V_6 2.2u/6.3V_6 2.2u/6.3V_6 2.2u/6.3V_6
VSS38 DQ13 VSS38 DQ13
M_A_DQ8 23 24 M_B_DQ9 23 24
M_A_DQ12 DQ8 VSS17 M_A_DM1 M_B_DQ8 DQ8 VSS17 M_B_DM1
25 26 25 26
DQ9 DM1 DQ9 DM1
27 28 27 28
VSS49 VSS53 VSS49 VSS53
M_A_DQS#1 29 30 M_CLK_DDR0 M_B_DQS#1 29 30 M_CLK_DDR3
DQS#1 CK0 M_CLK_DDR0 6 DQS#1 CK0 M_CLK_DDR3 6 +3V
M_A_DQS1 31 32 M_CLK_DDR#0 M_B_DQS1 31 32 M_CLK_DDR#3 +1.8VSUS
DQS1 CK0# M_CLK_DDR#0 6 DQS1 CK0# M_CLK_DDR#3 6
33 34 33 34
M_A_DQ14 VSS39 VSS41 M_A_DQ10 M_B_DQ11 VSS39 VSS41 M_B_DQ15
35 36 35 36
DQ10 DQ14 DQ10 DQ14
DQ11 DQ15 DQ11 DQ15
39 40 39 40 C149 C181 C604 C172 C97 C99
41 42 41 42 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 2.2u/6.3V_6 0.1u/10V_4

43 44 43 44
M_A_DQ20 DQ16 DQ20 M_A_DQ21 M_B_DQ16 DQ16 DQ20 M_B_DQ17
45 46 45 46
DQ17 DQ21 DQ17 DQ21
47 48 47 48
M_A_DQS#2 VSS1 VSS6 PM_EXTTS#0 M_B_DQS#2 VSS1 VSS6 PM_EXTTS#1
49 50 PM_EXTTS#0 6 49 50 PM_EXTTS#1 6
DQS#2 NC3 DQS#2 NC3
M_A_DQS2 51 52 M_A_DM2 M_B_DQS2 51 52 M_B_DM2
DQS2 DM2 DQS2 DM2
53 54 53 54 SMDDR_VREF_DIMM
55 56 55 56
DQ18 DQ22 DQ18 DQ22
DQ19 DQ23 DQ19 DQ23
59 60 59 60
M_A_DQ25 61 62 M_A_DQ29 M_B_DQ28 61 62 M_B_DQ25 C210 C213
63 64 63 64
DQ25 DQ29 DQ25 DQ29
65 66 65 66 0.1u/10V_4 2.2u/6.3V_6
M_A_DM3 67 68 M_A_DQS#3 M_B_DM3 67 68 M_B_DQS#3
DM3 DQS#3 DM3 DQS#3
69 70 M_A_DQS3 69 70 M_B_DQS3
NC4 DQS3 NC4 DQS3
71 72 71 72
73 74 73 74
75 76 75 76
DQ27 DQ31 DQ27 DQ31
B 77 78 77 78 B
M_CKE0 VSS4 VSS8 M_CKE1 M_CKE3 VSS4 VSS8 M_CKE4
6,16 M_CKE0 79 80 M_CKE1 6,16 6,16 M_CKE3 79 80 M_CKE4 6,16
CKE0 CKE1 CKE0 CKE1
81 82 81 82
VDD7 VDD8 VDD7 VDD8
83 84 83 84
M_A_BS#2 NC1 A15 M_A_A14 M_B_BS#2 NC1 A15 M_B_A14
7,16 M_A_BS#2 85 86 7,16 M_B_BS#2 85 86
A16_BA2 A14 A16_BA2 A14
87 88 87 88
M_A_A12 VDD9 VDD11 M_A_A11 M_B_A12 VDD9 VDD11 M_B_A11
89 90 89 90
A12 A11 A12 A11
M_A_A9 91 92 M_A_A7 M_B_A9 91 92 M_B_A7
M_A_A8 A9 A7 M_A_A6 M_B_A8 A9 A7 M_B_A6
93 94 93 94
A8 A6 A8 A6
95 96 95 96 +1.8VSUS
VDD5 VDD4 VDD5 VDD4
M_A_A5 97 98 M_A_A4 M_B_A5 97 98 M_B_A4
M_A_A3 A5 A4 M_A_A2 M_B_A3 A5 A4 M_B_A2
99 100 99 100
A3 A2 A3 A2
M_A_A1 101 102 M_A_A0 M_B_A1 101 102 M_B_A0
A1 A0 A1 A0
103 104 103 104
VDD10 VDD12 VDD10 VDD12
M_A_A10 105 106 M_A_BS#1 M_B_A10 105 106 M_B_BS#1 + C152 C593 C606 C605 C590 C607
A10/AP BA1 M_A_BS#1 7,16 A10/AP BA1 M_B_BS#1 7,16
M_A_BS#0 107 108 M_A_RAS# M_B_BS#0 107 108 M_B_RAS#
7,16 M_A_BS#0 BA0 RAS# M_A_RAS# 7,16 7,16 M_B_BS#0 BA0 RAS# M_B_RAS# 7,16
M_A_W E# 109 110 M_CS#0 M_B_W E# 109 110 M_CS#2 330u/2.5V_3528 2.2u/6.3V_6 2.2u/6.3V_6 2.2u/6.3V_6 2.2u/6.3V_6 2.2u/6.3V_6
7,16 M_A_W E# W E# S0# M_CS#0 6,16 7,16 M_B_WE# W E# S0# M_CS#2 6,16
111 112 111 112
M_A_CAS# VDD2 VDD1 M_ODT0 M_B_CAS# VDD2 VDD1 M_ODT2
7,16 M_A_CAS# 113 114 M_ODT0 6,16 7,16 M_B_CAS# 113 114 M_ODT2 6,16
M_CS#1 CAS# ODT0 M_A_A13 M_CS#3 CAS# ODT0 M_B_A13
6,16 M_CS#1 115 116 115 116
S1# A13 6,16 M_CS#3 S1# A13
117 118 117 118
M_ODT1 VDD3 VDD6 M_ODT3 VDD3 VDD6
6,16 M_ODT1 119 120 6,16 M_ODT3 119 120
ODT1 NC2 ODT1 NC2 +3V
121 122 121 122 +1.8VSUS
123 124 123 124
DQ32 DQ36 DQ32 DQ36
DQ33 DQ37 DQ33 DQ37
127 128 127 128
M_A_DQS#4 VSS26 VSS28 M_A_DM4 M_B_DQS#4 VSS26 VSS28 M_B_DM4
129 130 129 130 C188 C165 C169 C161 C98 C101
DQS#4 DM4 DQS#4 DM4
M_A_DQS4 131 132 M_B_DQS4 131 132
DQS4 VSS42 M_A_DQ39 DQS4 VSS42 M_B_DQ39
133 134 133 134 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 2.2u/6.3V_6 0.1u/10V_4
M_A_DQ35 VSS2 DQ38 M_B_DQ38 VSS2 DQ38
135 136 M_A_DQ38 135 136 M_B_DQ35
DQ34 DQ39 DQ34 DQ39
M_A_DQ34 137 138 M_B_DQ34 137 138
DQ35 VSS55 M_A_DQ44 DQ35 VSS55 M_B_DQ45
139 140 139 140
VSS27 DQ44 VSS27 DQ44
DQ40 DQ45 DQ40 DQ45
M_A_DQ41 143 144 M_B_DQ40 143 144
DQ41 VSS43 M_A_DQS#5 DQ41 VSS43 M_B_DQS#5
145 146 145 146
VSS29 DQS#5 VSS29 DQS#5
M_A_DM5 147 148 M_A_DQS5 M_B_DM5 147 148 M_B_DQS5 SMDDR_VREF_DIMM
DM5 DQS5 DM5 DQS5
149 150 149 150
C
C
153 154 153 154
DQ43 DQ47 DQ43 DQ47
155 156 155 156 C209 C212
DQ48 DQ52 DQ48 DQ52
M_A_DQ48 159 160 M_A_DQ52 M_B_DQ49 159 160 M_B_DQ53 0.1u/10V_4 2.2u/6.3V_6
DQ49 DQ53 DQ49 DQ53
161 162 161 162
VSS52 VSS57 M_CLK_DDR1 VSS52 VSS57 M_CLK_DDR4
163 164 M_CLK_DDR1 6 163 164 M_CLK_DDR4 6
NCTEST CK1 M_CLK_DDR#1 NCTEST CK1 M_CLK_DDR#4
165 166 M_CLK_DDR#1 6 165 166 M_CLK_DDR#4 6
VSS30 CK1# VSS30 CK1#
M_A_DQS#6 167 168 M_B_DQS#6 167 168
M_A_DQS6 DQS#6 VSS45 M_A_DM6 M_B_DQS6 DQS#6 VSS45 M_B_DM6
169 170 169 170
DQS6 DM6 DQS6 DM6
171 172 171 172
173 174 173 174
DQ50 DQ54 DQ50 DQ54
DQ51 DQ55 DQ51 DQ55
177 178 177 178
179 180 179 180
DQ56 DQ60 DQ56 DQ60
M_A_DQ60 181 182 M_A_DQ57 M_B_DQ57 181 182 M_B_DQ61 SMDDR_VREF_DIMM
DQ57 DQ61 DQ57 DQ61
183 184 183 184
M_A_DM7 VSS3 VSS7 M_A_DQS#7 M_B_DM7 VSS3 VSS7 M_B_DQS#7
185 186 185 186
DM7 DQS#7 DM7 DQS#7
187 188 M_A_DQS7 187 188 M_B_DQS7
M_A_DQ58 VSS34 DQS7 M_B_DQ59 VSS34 DQS7
189 190 189 190
DQ58 VSS36 DQ58 VSS36
M_A_DQ59 191 192 M_A_DQ62 M_B_DQ62 191 192 M_B_DQ63 R221 0_6
DQ59 DQ62 DQ59 DQ62 +SMDDR_VREF
193 194 M_A_DQ63 193 194 M_B_DQ58
DDRDAT_SMB VSS14 DQ63 DDRDAT_SMB VSS14 DQ63
195 196 2 CGDA T_SMB 195 196
SDA VSS13 SDA VSS13
DDRCLK_SMB 197 198 R99 10K_4 DDRCLK_SMB 197 198 R530 10K_4 R224 *10K_4 R223 *10K_4
SCL SA0 2 CGCLK_S MB SCL SA0 +1.8VSUS
+3V 199 200 R98 10K_4 +3V 199 200 R529 10K_4
+3V VDD(SPD) SA1 +3V VDD(SPD) SA1
DDR2_6H DDR2_10.5H
+3V
CH-A SPD ADDRESS:??????

CH-A SPD ADDRESS:??????
D D

PROJECT : TE1M
E3D
DDR SO-DIMM
1 2 3 4 5 6 7 8
5 4 3 2 1
VGA BOARD CONNECOTR BOM Option Table

EV@ EXT VGA
EMI De-coupling CAP

CN513
PEG_TXN15 2 1 PEG_RXN15 +3V
6 PEG_TXN15 2 1 PEG_RXN15 6
6 PEG_TXP15
PEG_TXP15 4
4 3
3 PEG_RXP15
PEG_RXP15 6 B2A
6 5
PEG_TXN14 6 5 PEG_RXN14
PEG_TXP14 8 7 PEG_RXP14 C247 C85 C601 C82 C509 C721 C197 C516 C524
6 PEG_TXP14 10 9 PEG_RXP14 6
D 10 9 D
12 11
PEG_TXN13 12 11 PEG_RXN13 *0.1u/50V_6 *0.1u/50V_6 *0.1u/50V_6 *0.1u/50V_6 *0.1u/50V_6 *0.1u/50V_6 0.1u/50V_6 *0.1u/50V_6 *0.1u/50V_6
PEG_TXP13 14 13 PEG_RXP13
16 15
18 17
PEG_TXN12 18 17 PEG_RXN12 +5V
22 21
24 23
PEG_TXP11 26 25 PEG_RXP11 C519 C513 C518 C561 C202 C567 C563 C93 C510 C177
28 27
30 29
PEG_TXN10 30 29 PEG_RXN10 *0.1u/50V_6 *0.1u/50V_6 *0.1u/50V_6 *0.1u/50V_6 *0.1u/50V_6 *0.1u/50V_6 *0.1u/50V_6 *0.1u/50V_6 *0.1u/50V_6 *0.1u/50V_6
34 33
36 35
40 39
42 41
46 45 C675 C88 C660
48 47
PEG_TXN7 48 47 PEG_RXN7 *0.1u/50V_6 *0.1u/50V_6 *0.1u/50V_6
52 51
54 53
PEG_TXN6 54 53 PEG_RXN6 VIN
58 57
60 59
64 63 C80 C84 C118 C702 C127 C70 C47 C186 C185
66 65
PEG_TXN4 66 65 PEG_RXN4 0.1u/50V_6 0.1u/50V_6 0.1u/50V_6 0.1u/50V_6 0.1u/50V_6 0.1u/50V_6 *0.1u/50V_6 *0.1u/50V_6 *0.1u/50V_6
C
C
70 69
72 71
PEG_TXN3 72 71 PEG_RXN3 +3VPCU
76 75
78 77
82 81 C557 C515 C18 C517 C49 C559 C756 C183 C133
84 83
PEG_TXN1 84 83 PEG_RXN1 *0.1u/50V_6 *0.1u/50V_6 *0.1u/50V_6 *0.1u/50V_6 *0.1u/50V_6 *0.1u/50V_6 *0.1u/50V_6
86 85 *0.1u/50V_6 0.1u/50V_6
90 89
PEG_TXN0 90 89 PEG_RXN0 +5VPCU
94 93
96 95
EXT_CRT_DDCCLK 96 95 CLK_MXM#
20 EXT_CRT_DDCCLK 98 97 CLK_MXM# 2
EXT_CRT_DDCDAT 98 97 CLK_MXM C795 C94 C19 C15 C28 C25 C571
20 EXT_CRT_DDCDAT 100 99 CLK_MXM 2
100 99
102 101
EXT_HDMI_DDCCLK 102 101 GFXRST# *0.1u/50V_6 *0.1u/50V_6 *0.1u/50V_6 *0.1u/50V_6 *0.1u/50V_6 0.1u/50V_6 *0.1u/50V_6
21 EXT_HDMI_DDCCLK 104 103 GFXRST# 13
EXT_HDMI_DDCDATA 104 103 SYSFANON#
21 EXT_HDMI_DDCDATA 106 105 SYSFANON# 3
106 105 MAINON
108 107 MAINON 22,28,34,35,36
EXT_LVDS_PNLCLK 108 107 GFXPG +1.8VSUS
19 EXT_LVDS_PNLCLK 110 109 GFXPG 28
EXT_LVDS_PNLDAT 110 109 3ND_MBDATA
19 EXT_LVDS_PNLDAT 112 111 3ND_MBDATA 21,26,28
112 111 3ND_MBCLK
114 113 3ND_MBCLK 21,26,28
EXT_VGA_RED 114 113 EXT_LVDS_BLON
20 EXT_VGA_RED 116 115 EXT_LVDS_BLON 19
116 115 EXT_DISP_ON
118 117 C808 C809 C810 C811 C812 C813 C814
118 117 EXT_DISP_ON 19
EXT_VGA_GRN 120 119 DVI_HPD
20 EXT_VGA_GRN 120 119 DVI_HPD 21
122 121 33p/50V_4 33p/50V_4 33p/50V_4 33p/50V_4 33p/50V_4 33p/50V_4 33p/50V_4
EXT_VGA_BLU 122 121 EXT_HSYNC C3A
20 EXT_VGA_BLU 124 123 EXT_HSYNC 20
124 123 EXT_VSYNC
126 125 EXT_VSYNC 20
EXT_LVDS_TXL#2 126 125
19 EXT_LVDS_TXL#2 128 127
B
EXT_LVDS_TXL2 128 127 B
19 EXT_LVDS_TXL2 130 129
130 129
132 131
EXT_LVDS_TXL#1 132 131
EXT_LVDS_TXL1 134 133
136 135 C815 C816 C817 C818
138 137
EXT_LVDS_TXL#0 138 137 33p/50V_4
140 139 33p/50V_4 33p/50V_4 33p/50V_4
EXT_LVDS_TXL0 142 141
144 143
EXT_LVDS_TXLCK# 144 143
19 EXT_LVDS_TXLCK# 146 145
EXT_LVDS_TXLCK 146 145
19 EXT_LVDS_TXLCK 148 148 147 147
150 149
150 149
152 151
152 151
154 154 153 153
156 155
156 155 +3V +5V
158 157
158 157 VIN
160 160 159 159
162 161
EXT_HDMICLK- 162 161
21 EXT_HDMICLK- 164 163 +5V
EXT_HDMICLK+ 164 163
21 EXT_HDMICLK+ 166 166 165 165
168 167 C696 C697 C717 C716 C665
EXT_HDMITX2N 168 167
21 EXT_HDMITX2N 170 169
EXT_HDMITX2P 170 169 EV@0.1u/16V_4 EV@10u/10V_8
172 171 EV@0.1u/16V_4 EV@10u/10V_8 EV@0.1u/50V_6
21 EXT_HDMITX2P 172 171
174 173 +3V
EXT_HDMITX1P 176 175
178 177
180 179
EXT_HDMITX0P 182 181
184 183
186 185
186 185
A 188 187 A
R596 EV@0_4 VIN_VGA 188 187 VIN_VGA R606 EV@0_4
190 189
C3A 190 189 EXT_HDMICLK- R592 *EV@100/F_4 EXT_HDMICLK+
192 191
192 191
VIN 194 193 VIN
194 193
196 195
196 195 EXT_HDMITX2N R594 *EV@100/F_4 EXT_HDMITX2P VIN(ALW) 4A
198 198 197 197
200 199 VDD_5V(RUN) 0.5A
200 199
EXT_HDMITX1N EXT_HDMITX1P
VDD_3.3V(RUN) 2.5A Quanta Computer Inc.
EV@FOXCONN-HOUSING R590 *EV@100/F_4
PROJECT : TE1M
EXT_HDMITX0N R595 *EV@100/F_4 EXT_HDMITX0P Size Document Number Rev
E3D
VGA CONNECTOR
Date: Friday, June 13, 2008 Sheet 18 of 40
5 4 3 2 1
5 4 3 2 1
LVDS SIGNALS HALL SENSOR&BACK LIGHT SWITCH BOM Option Table
RP503 IV@0X2 TXLCLKOUT- RP11 LCD@0X2 LCD_TXLCLKOUT-

6 INT_TXLCLKOUT-
4 3 3 4
2 1 TXLCLKOUT+ 1 2 LCD_TXLCLKOUT+ R726 100K_4
6 INT_TXLCLKOUT+ +3VPCU IV@ INT VGA
+3V
LED_TXLCLKOUT+
EV@ EXT VGA
RP509 2 1 EV@0X2 RP5 3 4 LED@0X2
18 EXT_LVDS_TXLCK#
4 3 1 2 LED_TXLCLKOUT-
18 EXT_LVDS_TXLCK LCD@ CCLF TYPE PANEL
R571
1 2 LID591#
LED@ LED TYPE PANEL
1K_4
RP501 4 3 IV@0X2 TXLOUT2- RP8 3 4 LCD@0X2 LCD_TXLOUT2- MR1
6 INT_TXLOUT2-
2 1 TXLOUT2+ 1 2 LCD_TXLOUT2+ C351
6 INT_TXLOUT2+
EC2648-B3-F_EC S
0.1u/10V_4
18 EXT_LVDS_TXL#2
RP507 2 1 EV@0X2 RP2 3 4 LED@0X2 LED_TXLOUT2+
LED_TXLOUT2-
C3A DISPON 28
D 18 EXT_LVDS_TXL2 4 3 1 2 D
RP500 4 3 IV@0X2 TXLOUT1- RP9 3 4 LCD@0X2 LCD_TXLOUT1-

6 INT_TXLOUT1-
2 1 TXLOUT1+ 1 2 LCD_TXLOUT1+ DISPON D507 BAS316
6 INT_TXLOUT1+ LID591# 28
RP506 2 1 EV@0X2 RP3 3 4 LED@0X2 LED_TXLOUT1+

18 EXT_LVDS_TXL#1
4 3 1 2 LED_TXLOUT1- D509 IV@BAS316 R574 IV@0_4
18 EXT_LVDS_TXL1 INT_LVDS_BLON 6
+3V R581 EV@0_4
EXT_LVDS_BLON 18
RP504 4 3 IV@0X2 TXLOUT0- RP10 3 4 LCD@0X2 LCD_TXLOUT0-
6 INT_TXLOUT0-
2 1 TXLOUT0+ 1 2 LCD_TXLOUT0+
6 INT_TXLOUT0+
R736 R583
RP510 2 1 EV@0X2 RP4 3 4 LED@0X2 LED_TXLOUT0+ EV@10K _4
18 EXT_LVDS_TXL#0
4 3 1 2 LED_TXLOUT0- 100K_4
18 EXT_LVDS_TXL0
B2A Q31
EV@ME2N7002E
2
RP502 4 3 IV@0X2 EDIDCLK RP7 3 4 LCD@0X2 LCD_EDIDCLK

6 INT_LVDS_EDIDCLK
2 1 EDIDDATA 1 2 LCD_EDIDDATA
6,11 INT_LVDS_EDIDDATA
2 Q30
EC_FPBACK# 28
2
RP508 2 1 EV@0X2 EV@ME2N7002E
18 EXT_LVDS_PNLCLK
4 3 RP1 3 4 LED@0X2 LED_EDIDDATA Q50 2
18 EXT_LVDS_PNLDAT
1 2 LED_EDIDCLK
DTC 1 44EU
R5 2.2K_4 EDIDDATA
+3V
R4 2.2K_4 EDIDCLK
CCD POWER SWITCH LCD POWER SWITCH

+15V
B2A
C
+3V C
USBP3-_LCD L 50 2 4 3 *LCD@DLW21HN900SQ2L_C USBP3-
4 3 LCDVCC : 1.5A(Rush current) 0.45A(max )
USBP3+_LCD 1
1 2
2 USBP3+ R17 65mil 0.4A(Typ)
330K_6 Q4
R507 0_8
+5V +3VPCU LCDONG 2 AO3404 LCDVCC
USBP3-_LED L4 1 2 *LED@DLW21HN900SQ2L_C
USBP3+_LED 1 2 L6
4 3
4 3
+5V 1 3 CCD_POWER
LCDVCC1
0_6 65mil
R15 C14
Q500
C507 10u/10V_8
R505 100K_4 0.01u/25V_4
65mil
C506 *1000p/50V_4 *4.7K_4 R18 C21 C20 C22
*AO3413 USBP3-_LCD RP505 2 1 LCD@0X2 USBP3- 2 Q3
USBP3- 13
C504 *0.1u/10V_4 USBP3+_LCD 4 3 USBP3+ 22_8 0.1u/16V_4 0.01u/16V_4 10u/6.3V_6
USBP3+ 13
ME2N7002E
Q1 LCDDISCHG
USBP3-_LED RP6 4 3 LED@0X2
USBP3+_LED 2 1 R8 IV@0_4 2 PDTC143TT
6 INT_LVDS_DIGON
R9 EV@0_4
18 EXT_DISP_ON
2 LCDON# 2 Q2
CCD_POWERON 28
ME2N7002E
Q501 R11
*DTC144EU
100K_4
LED PANEL POWER DRIVER IC LCD_VADJ R6 *LED@0_4 LCD_VADJ_O2 LCD Panel Module
C11 *LED@1n_4
VIN
B
TOSHIBA LED Panel Module B
B2A +3V
F2 C801
LED@LITTLE-0603-2A-32V CCD_POWER INVCC0 : 0.67A for E/E Reference only
LED@0.1u/10V_ 4
44 40
43 39 +3V
42 38 LCDVCC
R29 LCD@0_8 INVCC0
41 37 VIN
DISPON 2
LED_VIN LCD_VADJ_O2 36 USBP3-_LED LED_VDD(from LCD_VCC) :
L5 LED@10UH-88mR 4
LCD_VADJ 35 USBP3+_LED 4A(Rush current) C36 C31
1 34 +
0.31A(Typ) C23
C16 LED@33n_4 R16 LED@499/F_4 U44
33 LED_TXLOUT2+ LCD@10u/25V_1210 LCD@1000p/50V_4 LCD@0.1u/50V_6
LED@TC7SH08FU
32 LED_TXLOUT2-
31
30 LED_TXLOUT1+
LED PWR : 0.015A 29 LED_TXLOUT1- CN5
C30
D1 28 CN9
27 1 1 2 2 LCDVCC
LEDAGND
LED@10U/X6S-25V_1206
LED_SW LED_PWR
26
LED_TXLOUT0+
LED_TXLOUT0- INT MIC 2
ADOGND
MIC_DATA
3
5
3 4
4
6
C13 C12
25 1 5 6
+3V 7 8
PC11
LED@B140 24 LED_TXLCLKOUT+ *INT_MIC CCD_POWER
7 8 LCD_TXLCLKOUT+
9 10
23 9 10
LED@1U/16V_6
P C9
L ED@0.1U/50V_6
C3A R14
LED@10U/Y5V-35V_1210 LED@10U/Y5V-35V_1210
22
LED_TXLCLKOUT-
ADOGND
ADOGND
MIC_DATA
11
11 12
12 LCD_TXLCLKOUT-
R34 0_4 13 14
21 29 INT_MIC 13 14
U1 LED_EDIDDATA DISPON 15 16 LCD_TXLOUT0+
LED@1M _ 6
20 LED_EDIDCLK R27 *0_4 LCD_VADJ 15 16 LCD_TXLOUT0-
19 6 INT_LVDS_PWM 17 17 18 18
C3A 18 LED_GND1
28 CONTRAST
R26 0_4 LCD_EDIDCLK
LCD_EDIDDATA
19 19 20 20
LCD_TXLOUT1+
18 21 22
C182 *47P/50V_4 PGND 17 LED_GND2
21 22 LCD_TXLOUT1-
1 17 23 24
GND PGND LED _ OVP 16 LED_GND3 C512 C511 USBP3+_LCD 23 24
2 GND OVP 16 15 25 25 26 26
R12 1 2 LED@200K_4 3 15 LED_GND4 USBP3-_LCD 27 28 LCD_TXLOUT2+
R13
FPW M IIN0 14 27 28
1 2 *200K_4 4 Vlevel IIN1 14 R10
13
LED_GND5 *LED@1000p/50V_6 *LED@1000p/50V_6 29 29 30 30 LCD_TXLOUT2-
5 13 LED_GND6 31 32
GND IIN2 12 31 32
RAMP1 6 PW MI/EN PAD 25 LED@37 K/ F_4
11 LED_PWR LCD@LCD_PANEL
PAD 26 10
PAD
27 9 C3A
A L EDAGND LED A GN D A
LCD_VADJ_O2 LED_GND1
8 C44 C10 C9
LEDAGND
LED_GND2 7
LED_GND3 6
*100p/50V_4 LCD@1000p/50V_6 LCD@1000p/50V_6
LED_GND4 5
LED@ISL97636
4
R7
3 ADOGND
2 MIC_DATA
1
SW4 C3A LED@35.7K/F_4
2 1
CN1
SHORT PAD
LED@LED_PANEL C50
LEDAGND LEDAGND LED_GND5
LED_GND6 *LED@100p/50V_6 PROJECT : TE1M
E3D
LCD/LED Panel/CCD
5 4 3 2 1
5 4 3 2 1
CRT CONN & DDC LEVEL SHIFT IC BOM Option Table

IV@ INT VGA
EV@ EXT VGA
C500 0.1u/10V_4
D501 SSM14 F1
2 1 2 1 FUSE1A6V_POLY-1A-6V 5V_CRT2 CN500
+5V
B2A CRT_CONN
6
CRT_R L3 BK1608LL680_6 CRT_R1 1 11 D500 MTW355
CRT_SENSE# 13,28
R62 IV@0_4 CRT_R 7
6 INT_CRT_RED
D CRT_G L2 BK1608LL680_6 CRT_G1 2 12 D
R60 IV@0_4 CRT_G 8
6 INT_CRT_GRN
CRT_B L1 BK1608LL680_6 CRT_B1 3 13
R56 IV@0_4 CRT_B 9
6 INT_CRT_BLU
4 14
R3 C8 R2 C5 R1 C2 C1 C4 C6 10
R61 EV@0_4 5 15
18 EXT_VGA_RED
150/F_4 4.7p/50V_4 150/F_4 4.7p/50V_4 150/F_4 4.7p/50V_4 4.7p/50V_4 4.7p/50V_4 4.7p/50V_4
R59 EV@0_4
18 EXT_VGA_GRN
R55 EV@0_4
18 EXT_VGA_BLU
R87 IV@0_4 DDCCLK

6 INT_CRT_DDCCLK
U500
R85 IV@0_4 DDCDAT 5V_CRT2 1 16 VSYNC1 R506 39/F_4 VSYNC1_CRT L500 BLM18BA220SN1_6 CRTVSYNC
6 INT_CRT_DDCDAT VCC_SYNC SYNC_OUT2
14 HSYNC1 R504 39/F_4 HSYNC1_CRT L501 BLM18BA220SN1_6 CRTHSYNC
+5V SYNC_OUT1
R78 IV@0_4 HSYNC 7
6 INT_HSYNC VCC_DDC
C3 0.22u/10V_6 8 C502 C503
BYP
R72 IV@0_4 VSYNC 15 VSYNC
6 INT_VSYNC SYNC_IN2
2 13 HSYNC 5V_CRT2 10p/50V_4 10p/50V_4
+3V VCC_VIDEO SYNC_IN1
R86 EV@0_4 R500 R501
18 EXT_CRT_DDCCLK
CRT_R1 3 10 DDCCLK
CRT_G1 VIDEO_1 DDC_IN1 DDCDAT
R84 EV@0_4 4 11 2.7K_4 2.7K_4
18 EXT_CRT_DDCDAT VIDEO_2 DDC_IN2
CRT_B1 5
VIDEO_3
R77 EV@0_4 9 CRTDCLK
18 EXT_HSYNC DDC_OUT1
6 12 CRTDDAT
R71 EV@0_4 GND DDC_OUT2
18 EXT_VSYNC
CM2009
C501 C505
10p/50V_4 10p/50V_4
C +5V +3V C
DDCCLK R502 2.2K_4
+3V
DDCDAT R503 2.2K_4
C508 C7
0.1u/10V_4 0.1u/10V_4
HOLE & NUTS
NUTS NEED RATING TOP or BOT (NUT don't use *)

RAMP1
HOLE20 HOLE22 HOLE21 HOLE23 B2A
h-c189d118p2 h-c189d118p2 EV_IV@h-c189d118p2 EV_IV@h-c189d118p2
HOLE13 HOLE17 HOLE1 HOLE2 HOLE3 HOLE10 HOLE12
h-tc79bc165d63p2 h-tc79bc165d63p 2 7 6 7 6 7 6 7 6 7 6
8 5 8 5 8 5 8 5 8 5
9 4 9 4 9 4 9 4 9 4
B B
B2A H-C295D98P2-8 h-c295d98p2-8 h-c295d98p2-8 h-te344x 295bc295d98p2-8 h-c295d98p2-8
HOLE14 HOLE25 HOLE27 HOLE4

7 6 7 6 7 6 7 6
8 5 8 5 8 5 8 5
9 4 9 4 9 4 9 4
H-C295D98P2-8 h-c295d98p2-8 h-c295d98p2-8 H-TC256BC217D98P2-8
HOLE5 HOLE6 HOLE8

7 6 7 6 7 6
8 5 8 5 8 5
9 4 9 4 9 4 HOLE9 HOLE24 C3A
H-C98D98N H-C98D98N HOLE15
7 6 HOLE26
8 5 7 6
9 4 8 5
H-TC157BC197D118P2-8 H-TC157BC197D118P2-8 H-TC157BC197D118P2-8 4
*h-te32 7 x313bc295d98p2-7
C3A
HOLE11 HOLE18 HOLE19 H-C295D98P2-8
A A
7 6 7 6 7 6 HOLE7
8 5 8 5 8 5 h-c189d118p2 ADOGND
9 4 9 4 9 4 C3A RAMP1
HOLE16 PAD1 PAD2
7 6 *EMI_PAD *EMI_PAD
8 5
EV@H-C236D146P2-8 EV@H- C236D146P2-8 EV@H-C236D146P2-8 9 4
PROJECT : TE1M
*H-TC157BC197D118P2-8 Size Document Number Rev
E3D
CRT/HOLE
5 4 3 2 1
5 4 3 2 1
+3V
RAMP2 RAMP1 HDMI CEC CEC_POWER BOM Option Table
HDMI IC
U11
6 TMDSB_DATA2 39 22 IV_ HDMITX2P
IN_D+ OUT_D1+ CEC_POW ER
6 TMDSB_DATA2# 38 23 IV_ HDMITX2N IV@ INT VGA
IN_D1- OUT_D1-
R182 R185 R393 R398 42 19 IV_ HDMITX1P R83 R90
6 TMDSB_DATA1 IN_D2+ OUT_D2+ EV@ EXT VGA
6 TMDSB_DATA1# 41
IN_D2- OUT_D2-
20 IV_ HDMITX1N C3A
IV@1.5K/F_4 IHM@1.5K/F_4 C92 C106
CEC@ HDMI CEC
IV@1.5 K /F_4 *IHM@ 1. 5K/F_4 45 16 IV_ HDMITX0P U9 CEC@2.2K_4 CEC@2.2K_4
6 TMDSB_DATA0 IN_D3+ OUT_D3+
44 17 IV_ HDMITX0N CEC@1u/10V_6 CEC@0.1u/10V_4
6 TMDSB_DATA0# IN_D3- OUT_D3- IHM@ INT HDMI
7 1 CEC_SCLK
6 SDVO_CTRLCLK VCC SCL
TMDSB_CLK 48 13 IV_ HDMICLK+ 16 20 CEC_SDATA
6,11 SDVO_CTRLDATA 6 TMDSB_CLK IN_D4+ OUT_D4+ VCC SDA EHM@ EXT HDMI
T MDSB_CLK 6 TMDSB_CLK# TMDSB_CLK# 47 14 IV_ HDMICLK- CEC_POW ER 18 HDMI_CEC_DDCDATA
6 TMDSB_CLK IN_D4- OUT_D4- DDCSDA
T MDSB_CLK# R82 CEC@47K_4 XIN_CEC 4 17 HDMI_CEC_DDCCLK
6 TMDSB_CLK# XOUT DDCSCL
SDVO_CTRLCLK 9 28 IV_ HDMI_DDCCLK R105 CEC@47K_4 XOUT_CEC 6
SCL SCL_SINK XIN RP14
SDVO_CTRLDATA 8 29 IV_ HDMI_DDCDATA 13 N36306471 2 1
SDA SDA_SINK TEST1
HDMI_LF_HPOUT
RAMP1 +3V
RP15 1 2 T18
T25
CEC-RESET#
CEC-MODE
3
RESET TEST0
12 N36306469 4 3 CEC_POW ER
7 30 HTPLG 3 4 8
HPD HPD_SINK MODE
D Close to Cap. 10 CEC_OUT CEC@4.7KX2 D
CEC@4.7KX2 CEC OUT
IHM@PI3VDP411LS 2 5 9 CEC_IN
VCC[1] VSS CEC IN
11 15
VCC[2] NC
OE# 25 15 14 19 HPDET
+3V OE# VCC[3] NC HPDET
C3A DDC_EN VCC[4]
21 11
NC NC
2
+3V
32 26
R199 DDC_EN VCC[5]
*IHM@4.7K_4 OC_0 33
VCC[6]
R377 IHM@0_4
OC_3 10
OC_3 VCC[7]
40 CEC@R5F211A4SP RAMP2
46
VCC[8] R166
R196 *IHM@4.7K_4 OC_1 OC_0 3
OC_1 OC_0 IV@20 K _4
4 1
R378 IHM@0_4 OC_1 GND[1]
5
R193 *IHM@499/F_4 GND[2]
6 12
OC_2(REXT) GND[3]
R173 *IHM@4.7K_4 OC_3 C3A GND[4]
18 Port-B_HPD#
Port-B_HPD# 6
27 24
GND GND[5]
R379 IHM@0_4 CH7318 use 1.2k ohm 31
GND[6]
36
GND[7]
EQ_0 34 37
+3V EQ_1 EQ_0 GND[8]
35 43
EQ_1 GND[9]
49 HDMI_LF_HPOUT R188 IHM@0_4 2 R167
IHM@4.7K_4 GND[10]
R192 EQ_0
Q18 IHM@7.5K/F_6
R195 *IHM@4.7K_4 EQ_1 IHM@2 N7002
R350 IHM@4.7K_4 CEC_POWER R189

EQUALIZATION SETTING +3V IHM@100K_4
R187
EQ_0 EQ_1 EQUALIZATION U4
IHM@4.7K_4 DDC_EN
C59 CEC@0.1u/10V_4
0 0 3dB 5 1
R265 *IHM@4.7K_4 OE# 2
C179 C151 C180 C150 HPDET
R171 *IHM@4.7K_4
0 1 6dB 4 3
For CH7 318 use IHM@0.1u/10V_4 IHM@0.01u/16V_4 IHM@0.1u/10V_4 IHM@0.01u/16V_4

1 0 9dB
CEC@NL 1 7SZ17
1 1 12dB +3V P CU
To EC C67
U6
CEC@0.1u/10V_4 5 1
2 R541 IEHM@1.2K/F_4 HDMI_CON_ HP
CEC_EC_HP 4 3
28 CEC_EC_HP
IV_ HDMITX2P RN6 2 1 IHM@0X2
IV_ HDMITX2 N 4 3 R539
C C
IEHM@470K_4
+3V
L14 *IHM@W CM2012-90_C
B2A
IEHM@N L17SZ17
4 3
1 2
C72 CEC@0.1u/10V_4 CEC_POW ER
U7
RN504 EHM@0X2
B2A EV@1K_4
1
C69 *CEC@0.1u/10V_4
2 1 DVI_HPD R52 4
18 EXT_HDMITX2P 18 DVI_HPD
4 3 2 PLTRST#
18 EXT_HDMITX2N PLTRST# 13,25,26,27,28
ESD502 IEHM@TC7SH08FU
HDMITX2P 1 10 HDMITX2P HTPLG R53 IV@1K_4 U8
1 10
L509 4 3 *EHM@W CM2012-90_C HDMITX2N 2 9 HDMITX2N 3
2 9 Vcc
1 2 3 8 1 CEC-RESET#
VCC GND Reset#
HDMITX1P 4 7 HDMITX1P 2
HDMITX1N 4 7 HDMITX1N GND
5 6
RN5 IHM@0X2 5 6 CEC_POW ER *CEC@G691L308T73 UF
IV_ HDMITX1P 2 1
IV_ HDMITX1 N 4 3 *IEHM@RCIa mp0514M
U10
C120 *CEC@0.1u/10V_4 5 1
L13 4 3 *IHM@W CM2012-90_C 2
1 2 4 3
C86 *CEC@22p/50V_6 XIN_CEC
RN503 2 1 EHM@0X2 Y2
18 EXT_HDMITX1P
4 3 *CEC@TC7SET14FU
18 EXT_HDMITX1N
*CEC@8 MHz
CEC_POWER +3VPCU
L508 *EHM@W CM2012-90_C +3V_S5 +3VPCU C100 *CEC@22p/50V_6 XOUT_CEC
4 3
1 2
R110 D10
CEC@0_4
IV_ HDMITX0P RN4 2 1 IHM@0X2 CEC@10K_4 CEC@CH500 H-40 *CEC@0_4
IV_ HDMITX0 N 4 3 R89 R73
CEC_IN
L12 4 3 *IHM@W CM2012-90_C R112
1 2 Q12 CEC@27K_4
CEC@2SK3541 CEC_P
RN502 2 1 EHM@0X2 1 HDMI_CON_CEC Q8

18 EXT_HDMITX0P
4 3 CEC@2 N7002
18 EXT_HDMITX0N
ESD501
HDMITX0P 1 10 HDMITX0P CEC_SCLK 3 1
1 10
L507 4 3 *EHM@W CM2012-90_C HDMITX0N 2 9 HDMITX0N
2 9 RP13 *CEC@0X2
B 1 2 3 8 4 3 B
VCC GND SCLK 2,14,25,27
HDMICLK+ 4 7 HDMICLK+ Q13 2 1
4 7 SDATA 2,14,25,27
HDMICLK- 5 6 HDMICLK- CEC@2SK3541
RN3 IHM@0X2 5 6
IV_ HDMICLK+ 2 1 CEC_P
IV_ HDMICLK- 4 3 *IEHM@RCIa mp0514M CEC_OUT R106 CEC@27K_4 1 Q9
CEC@2 N7002 RP12 4 3 CEC@0X2
3ND_MBCLK 18,26,28
2 1 3ND_MBDATA 18,26,28
L11 4 3 *IHM@W CM2012-90_C R107 CEC_SDATA 3 1
1 2
CEC@100K_4
RN501 2 1 EHM@0X2
18 EXT_HDMICLK+
18 EXT_HDMICLK- 4 3
L505
USE RN500, R400, R401, R134, R139, Q14,
4 3 *EHM@W CM2012-90_C
1 2 +5VPCU R118 *CEC@0_6 CEC_POW ER IV Q16
R117 CEC@0_6
+3VPCU DNI RN2, R135, R140, R122, Q15, Q17,
R127, R151, R128, R150
CEC_POW ER +3V
+5VPCU
ESD500 RAMP2
HDMI_CON_DDCCLK 1 10 HDMI_CON_DDCCLK USE RN2, R135, R140, R122, Q15, Q17,
1 10
HDMI_CON_DDCDATA 2 9 HDMI_CON_DDCDATA
2 9 R134, R139, Q14, Q16
D11 IEHM@RSX101M F3 IEHM@POLY SWITCH 1.1A DDC5V
3
VCC GND
8 EV
2 1 4 7 DDC5V
4 7
HDMI_CON_HP 5 6 HDMI_CON_HP R122 R140 R135 DNI RN500, R400, R401, R127, R151,
5 6
C573 *IEHM@RCIa mp0514 M EHM@0_4 EHM@4.7K_4 EHM@4.7K _4 R128, R150
*IEHM@10u/10V_8
B2A C574 R134 R139
IEHM@0.1u/10V_4 IEHM@4.7K_4 IEHM@4.7K_4

C3A Q14
IEHM@2SK354 1 Q15
B2A
CN505
EHM@2SK3541
20 HDMI_CON_DDCDATA 3 2 HDM I_CEC_DDCDATA 3 2 H DMI_ CON_D DCDATA_R RN50 0 2 1 IHM@0X2 IV_ HDMI_DDCDATA
HDMITX2P SHELL1 HDMI_CON_D D CCLK_R
1 4 3 IV_HDMI_DDCCLK
D2+
2
D2 Shield
HDMITX2 N 3
D2- R128 *IEHM@0_4 R127 *IEHM@0_4
HDMITX1P 4 4 3 EXT_ HDMI_DDCDAT EXT_ HDMI_DDCDATA 18
D1+
5
D1 Shield To HDMI CON N 2
R N2
1
EHM@0X2
EXT_HDMI_DDCCLK EXT_HDMI_DDCCLK 18
HDMITX1 N 6 Q16
D1- IEHM@2SK3541 Q17
HDMITX0P 7
D0+ EHM@ 2 SK3541
8
D0 Shield
HDMITX0 N 9 23 HDMI_CON_DDCCLK 3 2 HDMI_CEC_DDCCLK 3 2
A +5VPCU HDMICLK+ D0- GND A
10
CK+
11 22
CK Shield GND
HDMICLK- 12
HDMI_CON_CEC CK- R150 *IEHM@0_4 R151 *IEH M@0_4
13
CE Remote
14
R133 IEHM@2.2K_4 HDMI_CON_DDCCLK NC
15
R121 IEHM@2.2K_4 HDMI_CON_DDCDATA DDC CLK
16
DDC DATA
17
GND R400 IHM@0_4
DDC5V 18
+5V
HDMI_CON_HP 19
HP DET
21
SHELL2
R401 IHM@0_4
IEHM@HDMI CON

PROJECT : TE1M
E3D
HDMI/CEC
5 4 3 2 1
5 4 3 2 1
SATA ODD G SENSOR

BOM Option Table
GS@ G-SENSOR SEL
+3V_HDP
U505
18,28,34,35,36 MAINON 1
SHDN VO
4 RAMP1
U508
CN518 +5V_S5 2 C631
GND
14
GND14 GS@10u/10V_8
3 5
VIN SET
1
GND1 C634
D 2 SATA_TXP1 12 GS@G913-C 33 1 D
RXP NC NC
3 SATA_TXN1 12
RXN GS@0.1u/10V_4
4 32 2
GND2 NC NC
5 SATA_RXN1 12
TXN
6 SATA_RXP1 12 31 3
TXP NC NC
GND3 7
30 4
NC GND
8 R326 1K_4 Device Present 29 5 +3V_HDP
DP NC VDD
+5V
9 FS (Full Scale) selection
10 +5VSATA_ODD R292 0_8 +5V 28 GS@LIS3L02AQ3 6 ACCELY
+5V Reserved Vouty C633
RSVD
11 0 1
12 FS 27 7 AXSTST
GND +3V_HDP Reserved ST
13 C270 C258 C285 C291 C289 2g Full-Scale 6g Full-Scale GS@0.1u/10V_4
GND ACCELX
26 8
0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 10u/10V_8 Reserved Voutx
15
GND15
PD (Power Down) selection 25
NC NC
9
SATA ODD
0 1 24
NC NC
10
PD
Normal Mode Power-down mode 23
Reserved NC
11
SATA HDD
+3V_HDP
R575
*GS@10K_4
C
C3A CN501
C
FS FS ACCELZ
GND23 23
R579
1 GS@10K_4
GND1 SATA_TXP0
2 SATA_TXP0 12
RXP SATA_TXN0
3 SATA_TXN0 12
RXN
GND2 4
5 SATA_RXN0 SATA_RXN0 12
TXN SATA_RXP0
6 SATA_RXP0 12
TXP
7
GND3
8 +3.3VSATA R510 *0_8 +3V

3.3V
9
3.3V
10
3.3V C523 C525
11
GND +3V_HDP +3V_HDP
12
GND *10u/10V_8 *0.1u/10V_4
13
GND
5V 14 HDPPD selection
15
5V
5V
16 0 1 U509
+3V_HDP
GND
17 H=0.85 need under 1mm, HDPPD
18 C638 C632 Normal Mode Power-down mode 16 1 KXP84_SCL
RSVD Do not change P/N VCC HDPSCL
KXP84_SDA
19 7 20
GND GS@0.1u/10V_4 GS@0.1u/10V_4 VCC HDPSDA
20
12V +5VSATA R509 0_8 ACCELX G-RESET# R585 GS@10K_4
21 +5V 18 3
12V ACCELY ACCELX RESET R569 GS@10K_4
22 17 8
12V ACCELZ ACCELY MODE
15
+ C39 ACCELZ XIN_G
GND24
24 C32 C29 C522 B2A AXSTST 2
AXSTST Reserved
4 R582 GS@10K_4
6 XOUT_G R578 GS@10K_4
Serial_ATA 0.1u/10V_4 0.1u/10V_4 10u/10V_8L *100u/6.3V_3528 Reserved
Close to Pin 7 14 HDPACT 11
HDPACT Reserved
12
GND 10 13
and Pin 16 R570 GS@1K_4 HD_PINT 9
HDPPD Reserved
14
B 14 HDPINT HDPINT Reserved B
19
Reserved
5
VSS
R573
GS@R5F21174
GS@47K/F_6
+3V_HDP
ACCELX
U506
3 ACCELY
Vcc
1 G-RESET#
Reset#
+3V_HDP 2 ACCELZ
GND
GS@G691L308T73UF-SOT23 C659 C658 C647
GS@33n/16V_4 GS@33n/16V_4 GS@33n/16V_4
RP513
Q504
ADDRESS: 32H GS@4.7KX2 Close Chipset
GS@2N7002E
3 1 R740 GS@0_4 KXP84_SDA XIN_G C653 *GS@22p/50V_6

3,28 2ND_MBDATA
Y500
C822
*GS@8 MHz
+3V_HDP *GS @33n/16V_4
XOUT_G C641 *GS@22p/50V_6
A
Q503
C3A A
GS@2N7002E
3 1 R741 GS@0_4 KXP84_SCL

3,28 2ND_MBCLK
C821
*GS @33n/16V_4
PROJECT : TE1M
E3D
HDD/ODD/G-SENSOR
5 4 3 2 1
5 4 3 2 1
Cardbus +3V PCLK_PCM R329 *CB@22_4 PCLK_PCM_M C293 *CB@10p/50V_4 +3V

BOM Option Table
ENE1410 AJ014100T41 C282 C300 C283 C761 C322 C287 C758 C303 C759 C296
CB@ CARDBUS SEL
CB_RSMRST# R652 *CB@0_6 PCIRST#
CB@0.1u/10V_4 CB@0.1u/10V_4 CB@0.1u/10V_4 CB@0.1u/10V_4 CB@0.1u/10V_4 CB@0.1u/10V_4 CB@0.1u/10V_4 CB@0.1u/10V_4 CB@0.1u/10V_4 CB@0.1u/10V_4
delay 10ms at least C741 R654 CB@100K_6
+3V
ID Select : AD18 CB@0.22u/10V_6

A_CCD1#
Interrupt Pin : INTC# A_CCD2#
Request Indicate : REQ1# C284 C747

D D
Grant Indicate : GNT1# INTC# VCCD1# CB@10p/50V_4 CB@10p/50V_4
13 INTC#
SERIRQ VCCD0#
14,25,28 SERIRQ
13,24 PCI_PME#
PCI_PME#
PCMSPK
R331 CB@0_4 PCM_PME#
VPPD1
CN16 PCMCIA SOCKET
27 PCMSPK
CB_RSMRST# VPPD0 1
REQ1# +3V AVCC A_CAD0 GND
13 REQ1# 2
GNT1# A_CRSVD/D2 A_CAD1 D3 - CAD0
13 GNT1# 3
AD18 R330 CB@47_4 PCM_IDSEL A_CRSVD/D14 A_CAD3 D4 - CAD1
4
PCIRST# A_CRSVD/A18 R236 A_CAD5 D5 - CAD3
13,24 PCIRST# 5
PCLK_PCM A_CAD7 D6 - CAD5
2 PCLK_PCM 6
A_CCD1# CB@43K_6 A_CC/BE0# D7 - CAD7
7 CE1- CCBE0
FRAME# A_CCD2# A_CAD9 8
13,24 FRAME# A10- CAD9
IRDY# A_CAD11 9
13,24 IRDY# OE - CAD11
TRDY# A_CVS1# A_CAD12 10
13,24 TRDY# A11- CAD12
DEVSEL# A_CVS2# A_CAD14 11
13,24 DEVSEL# A9 - CAD14
STOP# A_CC/BE1# 12
13,24 STOP# A8 - CCBE1
PERR# A_CPAR 13
13 PERR# A13- CPAR
SERR# A_CPERR# 14
13 SERR# A14- CPERR
A_CGNT# 15
A_CINT# WE/PGM - CGNT
16
RDY/BSY,IRQ*INT
AVCC 17
VCC
AVPP 18
A_CCLK VPP1
19
A_CIRDY# A16- CCLK
20
A_CC/BE2# A15- CIRDY
21
A12- CCBE2
A_CAD18 22
A7 - CAD18
U513 A_CAD20 23
AD[31..0] A6 - CAD20
A_CAD21 24
13,24 AD[31..0] A5 - CAD21
A_CAD22 25
AD0 A_CAD31 A_CAD23 A4 - CAD22
N8 B2 26
AD0 CAD31/D10 A3 - CAD23
AD1 K7 C3 A_CAD30 A_CAD24 27
C
AD2 AD1 CAD30/D9 A_CAD29 A_CAD25 A2 - CAD24 C
L7 B3 28
AD3 AD2 CAD29/D1 A_CAD28 A_CAD26 A1 - CAD25
N7 A3 29
AD4 AD3 CAD28/D8 A_CAD27 A_CAD27 A0 - CAD26
M7 C4 30
AD5 AD4 CAD27/D0 A_CAD26 A_CAD29 D0 - CAD27
N6 A6 31
AD6 AD5 CAD26/A0 A_CAD25 A_CRSVD/D2 D1 - CAD29
M6 D7 32
AD7 AD6 CAD25/A1 A_CAD24 A_CCLKRUN# D2 - RFU
K6 C7 33
AD8 AD7 CAD24/A2 A_CAD23 WP,IOIS16-CKRUN
M5 AD8 CAD23/A3 A8 34 GND
AD9 L5 D8 A_CAD22
AD10 AD9 CAD22/A4 A_CAD21
K5 A9 35
AD10 CAD21/A5 GND
AD11 M4 C9 A_CAD20 A_CCD1# 36
AD11 CAD20/A6 CD1- CCD1
AD12 K4 A10 A_CAD19 A_CAD2 37
AD13 AD12 CAD19/A25 A_CAD18 A_CAD4 D11- CAD2
N3 B10 38
AD13 CAD18/A7 D12- CAD4
AD14 M3 D10 A_CAD17 A_CAD6 39
AD15 AD14 CAD17/A24 A_CAD16 A_CRSVD/D14 D13- CAD6
N2 E12 40
AD16 AD15 CAD16/A17 A_CAD15 A_CAD8 D14- RFU
J2 F10 41
AD17 AD16 CAD15/IOWR# A_CAD14 A_CAD10 D15- CAD8
J1 E13 42
AD18 AD17 CAD14/A9 A_CAD13 A_CVS1# CE2- CAD10
H4 F13 43
AD19 AD18 CAD13/IORD# A_CAD12 A_CAD13 RFSH,VS*1-CVS1
H3 F11 44
AD19 CAD12/A11 IORD-CAD13
AD20 G3 G10 A_CAD11 A_CAD15 45
AD20 CAD11/OE# IOW R-CAD15
AD21 G2 G11 A_CAD10 A_CAD16 46
AD21 CAD10/CE2# A17- CAD16
AD22 F1 G12 A_CAD9 A_CRSVD/A18 47
AD22 CAD9/A10 A18- RFU
AD23 F2 H12 A_CAD8 A_CBLOCK# 48
AD23 CAD8/D15 A19- CBLOCK
AD24 E2 H10 A_CAD7 A_CSTOP# 49
AD24 CAD7/D7 A20- CSTOP
AD25 E3 J11 A_CAD6 A_CDEVSEL# 50
AD26 AD25 CAD6/D13 A_CAD5 A21- CDEVSEL
E4 J12 AVCC 51
AD27 AD26 CAD5/D6 A_CAD4 VCC
D1 K13
AD28 AD27 CAD4/D12 A_CAD3
D2 J10 AVPP 52
AD29 AD28 CAD3/D5 A_CAD2 A_CTRDY# VPP2
D4 K10 53
AD30 AD29 CAD2/D11 A_CAD1 A_CFRAME# A22- CTRDY
C1 K12 54
AD31 AD30 CAD1/D4 A_CAD0 A_CAD17 A23- CFRAME
C2 AD31 CAD0/D3 L13 55 A24- CAD17
A_CAD19 56
A_CVS2# A25- CAD19
57
A_CRST# NC - CVS2
B 58 B
CBE0# A_CSERR# RESET-CRST
13,24 CBE0# N5 59
CBE0# WAIT-CSERR
CBE1# N1 A_CREQ# 60
13,24 CBE1# CBE1# INPACK-CREQ
CBE2# J3 H13 A_CC/BE0# A_CC/BE3# 61
13,24 CBE2# CBE2# CCBE0#/CE1# REG- CCBE3
CBE3# E1 E11 A_CC/BE1# A_CAUDIO 62
13,24 CBE3# CBE3# CCBE1#/A8 BVD2,SP-CAUDIO
PAR M2 A11 A_CC/BE2# A_CSTSCHG 63
13,24 PAR PAR CCBE2#/A12 BVD1,STSCHG-C*
B7 A_CC/BE3# A_CAD28 64
CCBE3#/REG# A_CPAR A_CAD30 D8 - CAD28
D13 65
CPAR/A13 A_CAD31 D9 - CAD30
66
+3V A_CCD2# D10- CAD31
U15 67
CD2- CCD2
68
VCCD0# GND
1 16 CB@CB1410
VCCD0# SHDN#
VCCD1# 2 15 VPPD0
VCCD1# VPPD0
+3V 3 14 VPPD1 CB@CARDBUS
3.3V VPPD1
4 3.3V AVCC 13
+5V 5 12 AVCC
5V AVCC
6 11
5V AVCC
7 10 AVPP
GND AVPP
8 9
OC# 12V
CB@ENE CP-2211 +3V AVCC +3V
+5V
AVCC
C240 C242
C723 C294 C728 C725 R_A_CCLK R272 CB@10_4 A_CCLK
CB@4.7u/10V_6 CB@0.1u/10V_4 A_CRST#
CB@4.7u/10V_6 CB@0.1u/10V_4 CB@0.1u/10V_4 CB@0.1u/10V_4 A_CCLKRUN#
A_CFRAME#
A +3V A
A_CIRDY#
AVPP A_CTRDY#
A_CDEVSEL#
A_CSTOP#
C755 A_CPERR#
C299 C256 C715 A_CSERR#
CB@4.7u/10V_6 A_CREQ#
CB@0.1u/10V_4 CB@4.7u/10V_6 CB@0.1u/10V_4 A_CGNT#
A_CBLOCK# Quanta Computer Inc.
A_CINT#
A_CSTSCHG
A_CAUDIO PROJECT : TE1M
E3D
PCMCIA(CB1410)
5 4 3 2 1
A B C D E
5 IN 1 Card reader
OZ129 for Cardreader+1394
ID Select : AD17
Interrupt Pin : INTA#
Request Indicate : REQ0# 30mil
U510
Grant Indicate : GNT0# RT9711BPF
+3V 2 8 VCC_XD
IN1 OUT 3 VCC_XD
3 7
IN2 OUT 2
6
MC_PW R_3V# OUT 1 +3V
4
EN#
C703 1
4 GND 4
9 5 R604 *10K_4
GND-C OC#
1u/16V_8
VCC_XD
+3VARUN
C708 C720 C718 C719
RAMP1 4.7u/6.3V_6 0.01u/16V_4 0.01u/16V_4 0.01u/16V_4
C724 C726 C729 XD_W PO#_C R491 10K_4
4.7u/6.3V_6 0.1u/10V_4 0.1u/10V_4
+3V L519 BK1608HS220_6 +1.8V
VCC_XD
B2A VCC_X D
C709 C714 C713 C712 C710 C711
C3A
CN519
4.7u/6.3V_6 0.1u/10V_4 0.1u/10V_4 4.7u/6.3V_6 0.1u/10V_4 0.1u/10V_4
SD_D0 R634 33_4 SD_D0_C
21
SD-VCC B2A
31
SD_D1 SD_D1_C SD-DAT 0
R635 33_4 34
SD-DAT 1
SD_D2 R626 33_4 SD_D2_C 9 38
SD_D3 SD_D3_C SD-DAT 2 XD-VCC
R627 33_4 11
SD-DAT 3
SD/MS_CLK R633 33_4 SD/MS_CLK_C 25 2 X D_CD#_C XD_CD#
SD-CLK XD-CD
AD[31..0]
U511 B2A SD_CMD
SD_CD#
SD_CMD_C
SD_CD#_C
15
SD-CMD XD-R/B
3 XD_R/B#_C
XD_RE#_C
XD_R/B#
XD_RE#
13,23 AD[31..0] 39 4
SD-C/D XD-RE
SM_WPI#/SD_W P SM_W PI#/SD_W P_C 41 5 XD_CE#_C XD_CE#
SD-W P XD-CE
AD31 19 6 X D_CLE_C XD_CLE
AD30 AD31 XD-CLE
20 C 733 18p_ 4 19 7 X D_ALE_C XD_ALE
AD30 SD-VSS1 XD-ALE
3 AD29 21 78 R646 5.9K/F_4 29 8 X D_W E#_C XD_W E# 3
AD28 AD29 REF SD-VSS2 XD-W E
22 Y 501 40 13 X D_W PO#_C XD_W PO#
AD28 SD-GND XD-W P
AD27 23 83 1394_XIN
AD27 XI MS_D3/XD_D0_C
AD26 24 84 1394_XOUT 2 4.576MHz 12 23
AD26 XO MS_D0/XD_D2 MS_D0/XD_D 2_ C MS-VCC XD-D0
AD25 25 22 27 MS_D2/XD_D1_C
AD25 MS-DATA0 XD-D1
AD24 27 76 TPBIAS0 C 730 18p_ 4 MS_D1/XD_D7 MS_D1/XD_D7_C 24 30 MS_D0/XD_D2_C
AD24 TPBIAS MS-DATA1 XD-D2
AD23 29 75 TPA0P MS_D2/XD_D1 MS_D2/XD_D1_C 20 32 MS_BS/XD_D3_C
AD23 TPA+ Bett er than 50ppm MS-DATA2 XD-D3
AD22 30 74 TPA0N MS_D3/XD_D0 MS_D3/XD_D 0_ C 16 33 X D_D4_C XD_D4
AD21 AD22 TPA- TPB0P SD/MS_CLK_ C MS-DATA3 XD-D4
31 72 14 35 X D_D5_C XD_D5
AD20 AD21 TPB+ TPB0N MS_CD# MS_CD#_C MS-SCLK XD-D5
32 71 18 36 X D_D6_C XD_D6
AD20 TPB- MS-INS XD-D6
AD19 34 MS_BS/XD_D3 MS_BS/XD_D 3_ C 26 37 MS_D1/XD_D7_C
AD17 R619 100/F_4 OZ129_IDSEL AD18 AD19 MS-BS XD-D7
35
AD18
AD17 36 4 MC_PW R_3V# 10 1
AD17 MC_3V# MS-VSS1 XD-GND1
AD16
AD15
37
AD16 SD/MS_CLK
113 SD/MS_CLK
SD_D3
C3A C707 *22p/50V_4 SD/MS_CLK_C
28
MS-VSS2 XD-GND2
17
47 111 42 43
AD15 SD_D3 GND1 GND2
AD14 48 112 SD_D2
AD13 AD14 SD_D2 SD_D1
49 107
AD13 SD_D1
AD12 50 108 SD_D0 CARD_READER
AD11 AD12 SD_D0 SD_CMD
51 110
AD10 AD11 SD_CMD SM_W PI#/SD_W P
52 117
AD10 SM_WPI#/SD_WP
AD9 53 114 SD_CD#
AD9 SD_CD#
AD8 54
AD8
AD7 57 95 MS_D1/XD_D7
AD7 MS_D1/XD_D7
AD6 58 93 XD_D6
AD6 XD_D6
AD5 59 89 XD_D5
AD5 XD_D5
AD4 60 87 XD_D4
AD3 AD4 XD_D4 MS_BS/XD_D3
61 88
AD3 MS_BS/XD_D3
AD2 62 90 MS_D0/XD_D2
AD1 AD2 MS_D0/XD_D2 MS_D2/XD_D1
63 94
AD1 MS_D2/XD_D1
AD0 64 96 MS_D3/XD_D0
AD0 MS_D3/XD_D0
28
XD_CE#
119
100
XD_CE#
XD_R/B#
1394
13,23 CBE3# C/BE3# XD_R/B#
38 118 XD_CLE
13,23 CBE2# C/BE2# XD_CLE
46 109 XD_ALE
13,23 CBE1# C/BE1# XD_ALE
55 105 XD_W E#
13,23 CBE0# C/BE0# XD_W E#
101 XD_RE#
OZ129_IDSEL XD_RE# XD_W PO#
5 98
IDSEL XD_W PO#
PCLK_OZ129 45 99 MS_CD#
2 2 PCLK_OZ129 PCI_CLK MS_CD# 2
42 97 XD_CD#
13,23 DEVSEL# DEVSEL# XD_CD#
13,23 FRAME# 39
FRAME#
13,23 IRDY# 40
IRDY# TPBIAS0
R665 41 2 C745 1u/10V_4
13,23 TRDY# TRDY# NC1
13,23 STOP# 43 8
STOP# NC2
*22_4 44 9
13,23 PAR PAR NC6
13 REQ0# 17 10
REQ# NC7
13 GNT0# 18 13
GNT# NC5
1 126 R658 R657
13,23 PCIRST# PCI_RST# NC3
C748 11 127 L516
13 INTA# INTA# NC4
13,23 PCI_PME# 3 128 2 1
PME# NC8 2 1
*22p/50V_4 6 56.2/F_4 56.2/F_4 3 4
14,28 CLKRUN# CLKRUN# 3 4
106 85 *CL-2M2012-121J T
26 TP_XD_LED MEDIA_ACTV TEST0
86 CN514
TEST1 TPA0P RN505 4 3 0X2 5
TPA0N 2 1 L1394_TPA0+ 4
L1394_TPA0- 3 6
OZ129T
C3A L1394_TPB0+
L1394_TPB0-
2
1 7
TPB0P RN506 3 4 0X2 8

TPB0N 1 2 1394_CONN
L523 0_6
L517
R655 R656 1 2
1 2
4 3
4 3
56.2/F_4 56.2/F_4
*CL-2M2012-121J T
1394_COM
C744
R661
270p/25V_4
5.1K/F_4
1 1

PROJECT : TE1M
E3D
OZ129T(5in1/1394)
A B C D E
5 4 3 2 1
1.5V_VCC(RUN) 0.5A
MINI Card 1 U&D 5.6H_WIMAX 3.3V_VCC(RUN) 1A +1.5V W IMAX_P
BOM Option Table
3.3V_AUX(S5) 0.005A +3V +1.5V
IV@ INT VGA
C3A C773 C780 C267 C307 C779

EV@ EXT VGA
0.1u/10V_4 10u/6.3V_8 0.01u/16V_4 0.1u/10V_4 10u/6.3V_8
W IMAX_P
+3V_S5 +3V W IMAX_P WiFi Link
C3B CN517 W IFI@
51 52
R 359 *0_4 CL_R S T#1_W LAN NC +3.3Vaux WiMAX/WiFi Link
14 CL_RST#1 49 50 WIMAX@
C-Link_RST GND
C306 C301 R 357 *0_4 PLTR ST #_PCIE 47 48
14 CL_DATA1 C-Link_DAT NC
R 353 *0_4 CL_CLK 1_W LAN 45 46
14 CL_CLK1 C-Link_CLK NC
R739 R738 C3B 0.1u/10V_4 10u/6.3V_8 43
GND LED_WLAN#
44
W iMAX_LED#_B R719
41 42 0_4
+3.3Vaux LED_WWAN# W iMAX_LED# 27
W IMAX@0 _6 *0_6 39 40 R354 W IMAX@0_4
+3.3Vaux USB_ GND
37 38 USBP5+_C R352 0_4
D +3V_S5 +3V GND USB_D+ USBP5+ 13 D
35 36 USBP5-_C R351 0_4
GND USB_ D- USBP5- 13
1 3 33 34 +3V
13 PCIE_TXP6 PETp0 GND
31 32 W L_SMDATA
13 PCIE_TXN6 PETn0 NC
29 30 W L_SMCLK
GND NC
Q516 C3B 27
GND NC
28
AO3413 R742 R743 25 26
13 PCIE_RXP6 PERp0 GND
W IMAX@4.7K_4 *4.7K_4 23 24 +3V_S5
13 PCIE_RXN6 PERn0 NC
21 22 RP54
GND PERS T# PLTRST# 13,21,26,27,28
19 20 RF_EN_W LAN R327 0_4
NC W_DISABLE# RF_EN 28
17 18 4.7KX2
NC GND
IntelR Wireless WiFi IntelR WiMAX/WiFi Link Q24
15 16 Link 4965AGN, 4965AG 5050 Series Rev. 1.0 2N7002E
GND NC
2 CLK_PCIE_MINI 13 14
REFCLK+ NC
2 11 12 Pin 2,52 +3.3V +3.3Vaux 3 1 W L_SMDATA
W MAX_P 28 2 CLK_PCIE_MINI# REFCLK- NC 2,14,21,27 SDATA
9 10
GND NC
7 8 Pin 6,28,48 +1.5V NC
W CS_CLK R256 0_4 W CS_CLKR CLKREQ# NC
Q517 5 6
26 W CS_CLK BT_CHCLK NC
DTC144EU To BT 26 W CS_DAT
W CS_DAT R255 0_4 W CS_DATR 3
BT_DATA GND
4 Pin 24 +3.3Vaux NC
W LAN_W AK E# 1 2 +3V
W AKE# +3.3Vaux
Pin 39,40, NC Pin 39,41 +3.3Vaux
2N7002E 41,42 Pin 40 USB_GND
C3A Q508
W LAN_MINIPCI
Pin 42 LED_WWAN#
3 1 Pin 46 LED_WPAN# NC Q26
14,26,27 PCIE_W AKE#
2N7002E
Pin 30,32 Pin 30 SMB_CLK NC
Pin 32 SMB_DATA 3 1 W L_SMCLK
2,14,21,27 SCLK
R254 10K_4
+3V_S5
+3V
1.5V_VCC(RUN) 0.5A
MINI Card 3 U 9H_HD-DVD 3.3V_VCC(RUN) 1A
+3V +1.5V
+1.5V
CN509 C610 C698 C635 C614 C639

51 52
Reserved +3.3V
49 50 IV@0.1u/10V_4 10u/6.3V_8 IV@0.01u/16V_4 IV@0.1u/10V_4 10u/6.3V_8
C Reserved GND C
47 48
Reserved +1.5V
45 46
Reserved LED_WPAN#
43 44
Reserved LED_WLAN#
41 42
Reserved LED_WWAN#
39 40
Reserved GND
37 38
Reserved USB_D+
35 36
GND USB _D-
13 PCIE_TXP2 33 34
PETp0 GND
13 PCIE_TXN2 31 32
PETn0 SMB_DA TA
29 30
GND SMB_ CLK
27 28
GND +1.5V
13 PCIE_RXP2 25 26
PERp0 GND
13 PCIE_RXN2 23 24
PERn0 +3.3Vaux PLTRST#
21 22
GND PERST# PLTRST# 13,21,26,27,28
19 20
Reserved W_DISABLE#
17 18
Reserved GND
15 16
GND UIM_VPP
2 CLK_PCIE_MINI2 13 14
REFCL K+ UIM_RESET
11 12
2 CLK_PCIE_MINI2# REFCLK- UIM_ CLK
9 10
GND UIM_DATA
7 8
CLKRE Q# UIM_PWR
5 6
Reserved +1.5V
3 4
Reserved GND
1 2
WAKE# +3.3V
IV@MINIPCI_ 2
+1.5V +3V
+3V +1.5V
1.5V_VCC(RUN) 0.5A
MINI Card 2 3.3V_VCC(RUN) 1A CN516
B
U 5.6H_TV/ROBOSON 14,23,28 SERIRQ
R618
R617
0_4
0_4
SERIRQ_debug
LDRQ#1__debug
51
49
NC +3.3V
52
50
C722 C762 C727 C757 C630 B
D 7.5H_HD-DVD 12 LDRQ#1
13,21,26,27,28 PLTRST#
R616 0_4 PLTRST#_debug 47
C-Link_RST
C-Link_DAT
GND
+1.5V
48 0.1u/10V_4 10u/6.3V_8 0.001u_4 0.1u/10V_4 10u/6.3V_8
R653 0_4 PCLK__debug 45 46
2 PCLK_DEBUG C-Link_CLK LED_WPAN#
43 44
GND LED_WLAN#
41
NC NC
42 B2A
39 40
NC NC USBP8+_C
37 38 R662 *0_4
GND USB_D+ USBP8+ 13
35 36 USBP8-_C R660 *0_4
GND USB _D- USBP8- 13
13 PCIE_TXP3 33 34
PETp0 GND
13 PCIE_TXN3 31 32
PETn0 SMB_DA TA
29 30
GND SMB_ CLK
27 28
GND +1.5V
13 PCIE_RXP3 25 26
PERp0 GND
13 PCIE_RXN3 23 24
PERn0 +3.3Vaux PLTRST#
21 22 PLTRST# 13,21,26,27,28
GND PERST#
19 20
NC W _DISABLE#
17 18
NC GND
15 16 LFRAME#_PCIE R664 0_4
GND NC LAD3_PCIE LFRAME# 12,28
13 14 R663 0_4
2 CLK_PCIE_MINI3 REFCL K+ NC LAD3 12,28
11 12 LAD2_PCIE R669 0_4
2 CLK_PCIE_MINI3# REFCLK- NC
9 10 LAD1_PCIE R668 0_4 LAD2 12,28
GND NC LAD0_PCIE LAD1 12,28
7 8 R673 0_4
CLKRE Q# NC LAD0 12,28
5 6
BT_CHCLK +1.5V
3 4
BT_DATA GND
1 2
WAKE# +3.3V
EV_IV@MINIPCI_2
For IV @ H=5.6 <DFHS52FR010>
For EV@ H=7.5 <DFHS52FR011>
C3B
MINI Card 4-D/Robson CN8 Remark1:TV+Robson or HD-DVD+Robson or
TV+HD-DVD for UMA SKU
UMA Discrete
A A
PLTRST# Remark2:TV is just for UMA(13")
2 CLK_PCIE_MINI4#
1
2
3
4
1 WLAN WLAN
2
2 CLK_PCIE_MINI4 5
13 PCIE_RXN4
6
7
TV or Robson HD-DVD
13 PCIE_RXP4 8
13
13
PCIE_TXN4
PCIE_TXP4
9
10
11
12
3 HD-DVD or Robson N.C
4
+1.5V 13
+3V 14 Robson PROJECT : TE1M
N.C Size Document Number Rev
*MINIPCI_4 E3D
MINI CARD
5 4 3 2 1
5 4 3 2 1
INT KeyBoard TP Board

RJ45/USB board
+3VPCU RAMP1 C3A CN6
MY16/MY17 for 17"only 1 +5VPCU
RP511 CN7 RAMP2 2
10 1 10KX8 MX6 USB_LANboard(ALW) +5VPCU 1.5A
MX5 MX4 36 3
9 2
MX0 MX7 4
8 3 C109 4.7u/10V_8 R399 27_8
+5V 5 USB_EN#0 28
MX1 7 4 MX3 K_LED_P
1 6 USBOC#0 13,28
MX2 6 5 MY16 C111 0.1u/10V_4 +3V_S5
2 MY16 28 7
3 8
RAMP2 4
MY17
MY17 28 9 FM_RIGHT 29
CN11
5 10 FM_LEFT 29
CP4 7 8 220px4 MX7 K_LED_P +5V_TP
6 1 11 SB_GPIO7 14
D 5 6 MX2 MY2 TPDATA D
7 MY2 28 28 TPDATA 2 12 FM_INT 14
3 4 MX3 MY1 TPCLK
8 MY1 28 28 TPCLK 3 13 SB_GPIO27 14
1 2 MX4 MY0 TP_LED_ON_r
9 MY0 28 4 14 LOM_DISABLE# 28
MY4
10 MY4 28 5 15
MY3 R115 0_4
11 MY3 28 28 TP_LED_ON 6 16 USBP0- 13
MY5 C116 C119
12 MY5 28 17 USBP0+ 13
CP5 7 8 220px4 MX0 MY14 TP_CONN
13 MY14 28 18
5 6 MX5
14
MY6
MY6 28
*10p_4 *10p_4 B2A 19 CLK_PCIE_LAN 2
3 4 MX6
15
MY7
MY7 28 C3A 20 CLK_PCIE_LAN# 2
1 2 MX1 MY13 CN18
16 MY13 28 TP_LED_ON A-test no use for TP 21
MY8 +5V_TP
17 MY8 28 Module shorterm solution. 1 22 PCIE_TXN5 13
MY9 TPDATA
18 MY9 28 Vendor sample A-test this pin 2 23 PCIE_TXP5 13
MY10 TPCLK
19 MY10 28 is 4-way button not LED. 3 24
CP3 7 8 220px4 MY7 MY11 TP_LED_ON_r
20 MY11 28 4 25 PCIE_RXP5 13
5 6 MY13 MY12
21 MY12 28 5 26 PCIE_RXN5 13
3 4 MY12 MY15
22 MY15 28 6 27
1 2 MY15 MX7
23 MX7 28 28 PLTRST# 13,21,25,27,28
MX2 *TP_CONN_ACS
24 MX2 28 29 PCIE_WAKE# 14,25,27
MX3
25 MX3 28 30 +3V
MX4
26 MX4 28 31 FM_DET 14
MX0
27 MX0 28 32
C P2 7 8 220px4 MY3 MX5
28 MX5 28
5
3
6
4
MY5
MY14 29
MX6
MX1
MX6 28 LED Board LAN_CONN_32P
30 MX1 28
1 2 MY6 K_LED_P
31 CAPSLED
32 CAPSLED 28
FN_F10
33 FN_F10 28
NUMLED
34 NUMLED 28 +5V
CP1 7 8 220px4 MY2
5 6 MY1
3 4 MY0 CN13
35
1 2 MY4 R261 1
1
KEYBOARD_CONN 2
C 2 C
10K_4
Q506 C3A 3
3
D14 4
+5VPCU 4
C27 100p/50V_4 MY17 IDE_LED# 2 1 HDDLED# MMBT3906 5
+5V 5
28 BATLED1# 6
R28 150_4 6
K_LED_P BAS316 7
+3V 28 BATLED0# 7
28 PW RLED# 8
MY16 8
C26 100p/50V_4 9
28 SUSLED_EC 9
R599 10K_4 IDE_LED# 10
+3V SATA_LED# 12 10
24 TP_XD_LED 11
11
28,31 ACIN 12
12
LED_CONN
Power board Bluetooth Module Conn Felica FP Board

B2A
CN10
C3A
1 C3A
13 USBP2+ 2 +5V
RAMP2 13 USBP2- 3
CN4
25 WCS_CLK 4 RAMP1
R212 *FA@0_8
+5VPCU 4 5 +5V
BT_RESET R209 0_6
28 NBSWON# 3 6
28 PW RLED# 2 25 W CS_DAT 7
1 +3V 8
C826 USB_DETACH 1 3 +5V_Felica R396 *0_6 1 3 +3V_Fingerprint
9 +3V
PB_CONN
10
1.5n/50V_4 C201 FA@10u/10V_8 C195 10u/6.3V_8
C82 5 C8 27 Q20 R214 R397 0_6 Q19
+3V_S5
USB_DETACH: Low USB connect FA@AO3413 C193 FA@1000p/50V_ 4 FA@4.7K_4 C147 *1000p/50V_4
B 1.5n /5 0V_4 1. 5n/ 5 0V_4 High USB disconnect BT_CONN *AO341 3 B
C199 FA@0.1u/10V_4 C146 *0.1u/10V_4
R96 *0_4 BT_RESET

28 BT_EN
RAMP1
R101 0_4 USB_DETACH R213 *4.7K_4 +3V
2 R392 *4.7K_4
FELICA_PWRO N 28 +3V_S5
MMB BOM Option Table Q21

FA@DTC144EU
Reference 2
Description FP_PWRON 28
LO@ LOW COST

Q22
*DTC144EU
MAIN@ MAINSTREM
CN14
+5V_Felica CN12
1 +3V_Fingerprint
13 USBP4- 2 1
RAMP1 Low cost RAMP1 13 USBP4+ 3 13 USBP1- 2
CN2 13 USBP1+
4 3
5 4
+3VPCU Main strem CN3 T87
1 11 6
FP_CONN
28 MX5 2
FA@FELICA_CONN
28 MX2 3 7
A 28 MY1 4 +3VPCU 1 A
5 +5VPCU 2
28 MX3 6 28 KEY_INT 3
14 LOW_DET 7 4
28 MX4 8 18,21,28 3ND_MBDATA 5
28 FN0# 9 18,21,28 3ND_MBCLK 6
28 FN1# 1012 8
MAIN@MMB_6PIN
LO@MMB_10PIN Quanta Computer Inc.
PROJECT : TE1M
E3D
New Card/Keyboard/WTB
5 4 3 2 1
5 4 3 2 1
New card (BTO) +NEW _3V

BOM Option Table C3A
CN15
CB@ CARDBUS SEL 26 27
GND1 GND27
RP515 C3A 13 PCIE_TXP1
25
PETp0 GND28
28
24 29
13 PCIE_TXN1 PETn0 GND29
Q514 NEW @4.7KX2 U19 23 30
GND2 GND30
2 3 +NEW _3V VDD_3.3V(S5) 0.275A 22
+3V 3.3VIN 3.3VOUT 13 PCIE_RXP1 PERp0
NEW @2N7002E 4 5 VDD_3.3V(RUN) 1.3A 21
3.3VIN 3.3VOUT 13 PCIE_RXN1 PERn0
VDD_1.5V(RUN) 0.65A 20
+3V_S5 GND3
3 1 NEW _SMDATA 17 15 +NEW _3VAUX 19
2,14,21,25 SDATA +3V_S5 AUXIN AUXOUT 2 CLK_PCIE_NEW REFCLK+
2 CLK_PCIE_NEW # 18
+NEW _1.5V REFCLK-
12 11 CPPE# 17
+1.5V 1.5VIN 1.5VOUT CPPE#
14 13 R253 NEW @0_4 NEW _CLKREQ#_RR 16
1.5VIN 1.5VOUT 2 NEW_CLKREQ# CLKREQ#
+NEW _3V 15
+3.3V1
+NEW _3V PLTRST# 6 1 Q23 14
D
13,21,25,26,28 PLTRST# SYSRST# STBY# +3.3V2 D
20
SHDN# CPPE#
10 CPPE#
CPUSB#
C3A *NEW @DTC144EU
PERST#
+NEW _3VAUX
13
PERST#
9 12
CPUSB# +3.3VAUX
Q513 RCLKEN 18 3 1 11
RCLKEN PERST# 14,25,26 PCIE_W AKE# +NEW _1.5V W AKE#
16 8 PERST#_R R28 6 NEW @0_4 10
NC PERST# +1.5V1
NEW @2N7002E 7 19 9
GND OC# NEW _SMDATA +1.5V2
8
NEW _SMCLK SMB_DATA
3 1 NEW @TPS2231MRGPR R336 NEW @47K_4 C262 R239 NEW @0_4 NEW _SMCLK 7
2,14,21,25 SCLK +3V_S5 SMB_CLK
6
RESERVED1
*3300P_4 5
RESERVED2
CPUSB# 4
CPUSB#
R222 NEW @0_4 USBP9+_ R 3
+3V 13 USBP9+ USB_D+
R220 NEW @0_4 USBP9-_ R 2
13 USBP9- USB_D-
1
GND4
1 NEW _CLKREQ#_RR R240 *NEW @10K_4

+3V_S5
NEW _CLKREQ# 4 NEW @NEW CARD
+3V_S5 +3V +1.5V 2 R346 *NEW @10K_4 +3V_S5
U14
+NEW _3VAUX +NEW _3V +NEW _1.5V *NEW @NC7SZ32 P 5X
C304 C295 C310 C312

C302 C275 B2A C286 C279 C276 B2A C268
NEW @0.1u/10V_4 NEW @0.1u/10V_4 NEW @0.1u/10V_4 NEW @0.1u/10V_4 2 RCLKEN
NEW @0.1u/10V_4 NEW @4.7u/6.3V_6 NEW @0.1u/10V_4 NEW @0.1u/10V_4 NEW @4.7u/6.3V_6 NEW @0.1u/10V_4
Q25
*NEW @2N7002E
USB
U507
RT9711BPF USB_system1(ALW) 0.75A CN511
+5VPCU F500 POLY SW ITCH 1.5A/6V_1206 USBPW RIN 2 8 USBPW R
IN1 OUT3
3 7 +1.8V
IN2 OUT2 USBPW R
6 U25
OUT1 +5VPCU 4
C 4 BUSBP6- C
28 USB_EN#1 EN# 3
1 + C637 BUSBP6+ 12 1
GND 2 CLKIN- VDD
9 5 R580 *10K_4 100u/6.3V_3528 11 6
GND-C OC# 1 CLKIN+ VDD
C636 R584 0_6 10
VDD
R388 *1K_4 18 23
OUT- VDD
1u/16V_8 R391 *1K_4 17 28
OUT+ VDD
USB_CONN
L515 5
USBP6- BUSBP6- AVDD
3 4 BSATA_RXP4 C819 4700p/50V_4 22 RP56
13 USBP6- 3 4 BI+
B2A 13 USBP6+
USBP6+ 2
2 1
1 BUSBP6+
E-SATA BSATA_RXN4 C820 4700p/50V_4 21
BI- EN_A
30 4 3
*RFCM1632100M3_C
RAMP1 BSATA_TXP4 C615 4700p/ 50V_4
RAMP1 EN_B
29 2 1
13,28 USBOC#6_7 27
AO+ 4.7KX2
26
Close IC, no stub at high-spee d trace AO-
CN508 7 SATA_RXP4
on PCB layout. BO+ SATA_RXP4 12
R586 0_6 USBPW R USB_system2(ALW) 0. 75A R 380 8 SATA_RXN4
BO- SATA_RXN4 12
221/F _4
+ C608 BSATA_TXN4 C624 4700p/ 50V_4 2 SATA_TXP4
SATA_TXP4 1 2
AI+
C3A 100u/6.3V_3528 1
VCC GND
11
B S ATA_RXP4 AI-
3 SATA_TXN4
SATA_TXN4 1 2
10
BUSBP6- BSATA_RXN4 BUSB P 7- B+ BS ATA_RXN4
D511 *EGA D504 *EGA R208 0_6 2 9 R283 475/F_4 19
D- B- IREF
8 R394 *1K_4 36 R348 0_4
BUSBP6+ BSATA_RXP4 BUSB P7 + GND BS ATA_TXN4 SIG_A
D513 *EGA D503 *EGA 3 7 R395 *1K_4 35 34 R349 0_4
D+ A- SIG_B SEL0_A
L16 6 BSATA_TXP4 33
BUSBP7- BSATA_TXN4 USBP7- BUSBP7- A+ SEL1_A
D12 *EGA D505 *EGA 2 1 4 5 4 32 R381 0_4
13 USBP7- 2 1 GND GND GND SEL2_A
USBP7+ 3 4 BUSBP7+ 9 31 R382 0_4
13 USBP7+ 3 4 GND SEL3_A
BUSBP7+ D13 *EGA BSATA_TXP4 D506 *EGA 20
GND
*RFCM1632100M3_C 25 13 R383 0_4
GND SEL0_B
USBPW R D510 *VPORT 37 14 R384 0_4
GND SEL1_B
R210 0_6 USB/ESATA 15
SEL2_B
24 16 R385 0_4
AGND SEL3_B
R386 0_4
PI2EQX3201B
RAMP1
Option SB to ESATA directly

PC-Beep
Satellite LED R744 *0_4
B B
BOM Option Table BSATA_RXP4 1 2 SATA_RXP4
W-LAN&BT LED R745 *0_4

Reference Description C3A BSATA_RXN4 1
R746
2
*0_4
SATA_RXN4
BSATA_TXP4 1 2 SATA_TXP4
LO@ LOW COST
+5V +5V R747 *0_4
BSATA_TXN4 1 2 SATA_TXN4
MAIN@ MAINSTREM
Mainstream --> Orange C3A C3A
Low Cost --> Orange White Right angle type R466 R442
MAIN@150_4 MAIN@150_4
LED501 1 2 LED_Y_LTST-C190KFKT RF_LED_R R451 390_4

RF_LED 28
+3V
LED2 LED1 +3V
MAIN@99-113UNC/V90/ TR8 MAIN@99-113UNC/V90/TR8 +3V
23 PCMSPK
WiMAX LED LED_B_LTS T-C190TBKT C343
R411 C3B
D18 CB@0_4
R727 100_4 LED500 2 1 WiMAX_R 1 3 CB@0.1u/10V_ 4 C342 CB@0.1u/10V_4
+5V
Mainstream --> White 2
CB@CHN217 C334 CB@0.1u/10V_4
Low Cost --> N/A
Q44 PCM-2 C325 1
BSS84 3 CB@0.1u/50V_6 PCMSPK_DELAY
4 1
PCM-1 2 4
1 PCBEEP 29
R716 U20 2
25 WiMAX_LED# +5V
D19 C335 R366 U21
10K_4 CB@TC7SH08FU CB@S N 74LVC1G8 6DCKR
B2A C344
CB@0.1u/50V_6 2
CB@CHN217 CB@0.1u/10V_4 CB@10K_4
LED_LOGO 2 Q33 LED_LOGO 2 Q27 PCM-3 C326

28 LED_LOGO 3 CB@0.1u/50V_6
D20
MAIN@2N7002 MAIN@2N7002
RF_LED_R 1
1 C345
+3VPCU
3 *MAIN@0.1u/10V _ 4 PCM-4 R362 CB@200K/F_4 PCM-5 PCM-5
C3B 14 SPKR
SPKR R390 NEW @0_4
WiMAX_R
A 2 R724
A
*BZ5V6 R367
Kill SW 10K_ 4
SW500 D515
C332
CB@0.1u/50 V _6 CB@86.6K/F_4
2
LOGO_1
1
28 KILL_SW 1
3
+3VPCU 3
1 LOGO_2
KILL_SW 2
3
B2A *MAIN@BZ5V6 Quanta Computer Inc.
D522
2
*DA204U PROJECT : TE1M
E3D
TP/SW/LED
5 4 3 2 1
5 4 3 2 1
SM BUS PU BOM Option Table
EC +3VPCU Reference Description

MBCLK R516 4.7K_4
EV@ EXT VGA
MBDATA R515 4.7K_4
+3VPCU 2ND_MBCLK R514 4.7K_4
CIR@ CIR FUNC.
+3V DNBSW ON#_uR 2ND_MBDATA R513 4.7K_4
R527 DIGVOL_UP FN0# R65 4.7K_4
+A3VPCU EC_VDD DIGVOL_DN FN1#
W OFP@ Debug switch
L7 0_6 R64 4.7K_4
BLM18AG601SN1_6 3ND_MBCLK R69 4.7K_4
C74 C81 C554 C558 3ND_MBDATA R70 4.7K_4
C76 C77 C75
0.1u/10V_4 10u/10V_8 0 .1u/10V_4 10u/10V_8L +3V
*0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4
H=0.85 need under 1mm,
CRT_SENSE# R519 4.7K_4
8769AGND Do not change P/N
D D
C534 C543 C514 C78 C532 C552
10u/10V_8L 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 U5
B2A I/O Base Address
H=0.85 need under 1mm, H=1.6mm R66 100K/F_4
+3VPCU
R63 *10K_4
Do not change P/N 3 97
12,25 LFRAME# LFRAME AD0/GPI90 MTEMP 31
12,25 LAD0 126
LAD0 AD1/GPI91
98 EC_AD1
USBOC#0 13,26 I/O Address
12,25 LAD1 127 99 FN0# 26
LAD1 AD2/GPI92
PCLK_591
12,25 LAD2 128
LAD2 A/D AD3/GPI93
100 FN1# 26 BADDR1-0 Index Data
12,25 LAD3 1 108 DIGVOL_UP 30
LAD3 AD4/GPIO05
2 PCLK_591 2
LCLK AD5/GPIO04
96 DIGVOL_DN 30 00 XOR TREE TEST MODE
95 NBSW ON#
AD6/GPIO03 NBSW ON# 26
R58
14,24 CLKRUN# 8
CLKRUN/GPIO11 AD7/GPIO07
94 SUSB# 14 01 CORE DEFINED
*22_4
12 GATEA20 121
GA20
10 2Eh 2Fh
101
DA0/GPI94
12 RCIN# 122
KBRST DA1/GPI95
105 VFAN 3 11 164Eh 164Fh
D/A DA2/GPI96
106
SHBM=0: Enable shared memory with host BIOS
C73
14 SCI#
D4 SCI#_uR 29
ECSCI/GPIO54 LPC DA3/GPI97
107 SUSLED_EC 26
*10p_4
BAS316 6
19 EC_FPBACK# LDRQ/GPIO24
GPIO41(VBAT)
80 EC_VBAT BADDR0 BADDR0 R68 *10K_4
B2A
21 CEC_EC_HP 124
LPCPD/GPIO10
GPIO GPIO42/TCK
17 RF_LED 27 BADDR1 BT_EN R508 10K_4
13,21,25,26,27 PLTRST# 7 20 AMP_MUTE# 29
LRESET GPIO43/TMS RF_EN
wake-up GPIO44/TDI
21 ID 31 SHBM R517 10K_4
26 USB_EN#0 123
PW UREQ/GPIO67
capability GPIO50/TDO
25
D/C# 31
CIRTX2/GPIO52/RDY
27
T503 DISPON 19 C3A
14,23,25 SERIRQ 125
SERIRQ Disabled ('1') if using FW H device on LPC.
no wake-up GPO82/TRIS
110 LED_LOGO 27
BADDR0 Enabled ('0') if using SPI flash for both system BIOS and EC firmware
27 USB_EN#1 9
SMI/GPIO65
capability GPO84/BADDR0 112
111 BT_EN 26
SOUT_CR/GPO83/BADDR1
26
26
MX0
MX1
54
55
KBSIN0
KBSIN1 SER SIN_CR/CIRRX/GPIO87
GPIO06
113
93
CRT_SENSE#
LID591# 19
13,20 ID
26 MX2 56
KBSIN2
C
26 MX3 57 32 CONTRAST 19
C
KBSIN3 A_PWM/GPIO15
58 118 +3VPCU
26 MX4 KBSIN4 B_PWM/GPIO21 KILL_SW 27 U3
26 MX5 59 62 BATLED0# 26
KBSIN5 C_PW M/GPIO13
SMBUS Table 60 65 2ND_MBCLK 6 1
26 MX6 KBSIN6 D_PW M/GPIO32 BATLED1# 26 SCL A0
26 MX7 61
KBSIN7 PW M E_PWM/GPIO45
22 SUSON 35,36
2ND_MBDATA 5
SDA A1
2
16 MAINON 18,22,34,35,36 3
F_PWM/GPIO40/CLKIN48 A2
SMBUS Devices 26 MY0 53
KBSOUT0/JENK G_PW M/GPIO66
81 TP_LED_ON 26
26 MY1 52 66 PW RLED# 26 7 8
KBSOUT1/TCK H_PW M/GPIO33 WP VCC
1 Battery 26 MY2 51
KBSOUT2/TMS GND
4
50 C83
26 MY3 KBSOUT3/TDI
2 CPU Thermal Sensor 26 MY4 49
KBSOUT4/JEN0 KB TA1/GPIO56
31 24LC08BT-I
3D Sensor 26 MY5 48
KBSOUT5/TDO TB1/GPIO14
63 FANSIG 3
0.1u/10V_4
EC EEPROM 26 MY6 47
KBSOUT6/RDY TA2/GPIO20
117 LOM_DISABLE# 26
26 MY7 43
KBSOUT7 TIMER TB2/GPIO01
64 ACIN 26,31 ADDRESS: A0H
3 VGA Board Thermal Sensor 26 MY8 42
KBSOUT8 TA3/GPIO51
26 S5_ON 32,36
Touch Sensor 26 MY9 41
KBSOUT9 TB3/GPIO36
15 VRON 33
26
26
MY10
MY11
40
39
KBSOUT10
KBSOUT11
SPI FLASH
38 84 +3VPCU
26 MY12 KBSOUT12/GPIO64 SPI_DI/GPIO77 T505
26 MY13 37
KBSOUT13/GPIO63 SPI SPI_DO/GPO76/SHBM
83 RF_EN 25 C3AU2
26 MY14 36 82
KBSOUT14/GPIO62 SPI_SCK/GPIO75 SPI_SDI_uR R522
35 91 DNBSW ON#_uR D3 BAS316 33_4 SPI _ SDI 2 8
26 MY15 KBSOUT15/GPIO61/XOR_OUT GPIO81 DNBSW ON# 14 SO VDD
26 MY16 34
KBSOUT16/GPIO60 SPI_SDO_uR R524 33_4 SPI _ SDO
33 75 RSMRST#_uR R54 0_6 5 7 C551
26 MY17 KBSOUT17/GPIO57 IRRX1/GPIO72/SIN2 RSMRST# 14 SI HOLD
FIR IRRX2_IRSL0/GPIO70
73 SUSC# 14
74 PW ROK_EC R47 0_4 SPI_SCK_uR R526 33_4 SPI _ SCK 6 3 0.1u/10V_4
IRTX/GPIO71/SOUT2 ECPW ROK 14 SCK WP
31 MBCLK 70 23 KEY_INT 26
SCL1/GPIO17 CIRRXM/GPIO46/TRST
To: Battery connector 69 14 CIRRX2 SPI_CS0#_uR 1 4
31 MBDATA SDA1/GPIO22 GPIO34/CIRRXL CE VSS
To: CPU Thermal Sensor, 3D Sensor, EC EEPROM
3,22 2ND_MBCLK 67
SCL2/GPIO73 SMB CIR CIRTX1/GPIO16
114 NUMLED 26
68 109 R521 10K_4 W25X16VSSIG
3,22 2ND_MBDATA SDA2/GPIO74 CIRTX2/GPIO30 CAPSLED 26 +3VPCU
18,21,26 3ND_MBCLK 119
SCL3/GPIO23
To: VGA Board Thermal Sensor, Touch Sensor 120
18,21,26 3ND_MBDATA SDA3/GPIO31
24 86 SPI_SDI_uR
25 W MAX_P SCL4/GPO47 F_SDI/F_SDIO1
HW PG 28 87 SPI_SDO_uR
SDA4/GPIO53 F_SDO/SDIO0
FIU F_CS0
90 SPI_CS0#_uR
92 SPI_SCK_uR
F_SCK
26 TPCLK 72
PSCLK1/GPIO37
+5V 71
B 26 TPDATA PSDAT1/GPIO35 B
LED0# 10
T19 PSCLK2/GPIO26
R45
R43
10K_4 TPCLK
10K_4 TPDATA
26 FP_PW RON 11
PSDAT2/GPIO27 PS/2 CLKOUT/GPIO55
30 EC_CLKOUT
USBOC#6_7 13,27 B2A
26 FN_F10 12
PSCLK3/GPIO25 VCC_POR# R520
13 85 4.7K_4 +3VPCU
26 FELICA_PW RON PSDAT3/GPIO12 VCC_POR
8768_32KX1 77 104 VREF_uR R67 0_4 +A3VPCU
32KX1/32KCLKIN VREF
R36 20M_6 8768_32KX2 79 INTERNAL KEYBOARD STRIP SET
32KX2
EC +3VPCU
R35
Y1 33K/F_4 MY0 R518 10K_4
W PC8763LDG: AL008763B00 (w/o CIR)
1 4 W PC8769LDG: AJ087690F08 (w/CIR)
2 3
L8 0_6 WPCE775L: AJ007750F00 (w/o CIR)
W PCE775C: AJ007750F01 (w/CIR)
32.768KHZ
C56
18p_4
C57
18p_4
C535
CIR +3VPCU +5VPCU
1u/10V_6 For W PC8763 +A3VPCU
R722 CIR@0_4 C786 CIR@0.1u/10V_4
8769AGND 8769AGND C553
EC_VBAT R525 *0_4 R721 *CIR@0_4
B2A *0.1u/10V_4
+5VPCU
R523 0_4
CCD_POW ERON 19
U517
+3V R723 CIR_VCC 2
VCC
For W PCE775 *CIR@10K_4
CIRRX2 1
OUT
R88
10K_4 3
GND
4
GND
B2A +3VPCU 20 mlis
BATLED1# R733 10K_4 CIR@IR-IRM-V538-TR1
A BATLED0# R734 10K_4 A
PW RLED# R735 10K_4
D21
CIRRX2 2 1 *VPORT
D7 EV@BAS316 HW PG
18 GFXPG
D8 BAS316
B2A
32 SYS_HW PG
D5 BAS316
B2A
34 HW PG_1.05V
D9 BAS316 NBSW ON# SW1 *SHORT PAD
6,35 HW PG_1.8V 2 1
D6 BAS316
36 HW PG_1.5V
PROJECT : TE1M
E3D
EC-PC8763
Date: Saturday, June 14, 2008 Sheet 28 of 40
5 4 3 2 1
5 4 3 2 1
Codec(CX20561) +5V BOM Option Table

B2A INT SPK AMP U515 *G961-18ADJTEU(SOT 89-5)
R641 0_4 R643 0_4 R699 *0_6 4 3
VEN VOUT Reference Description
R692 0_4 R677 0_4 5
VIN 1412@ AMP HP
R427
R672 0_4 R695 0_4 *36K/F_4
R651 0_4 R413 0_4

C774
*1u/16V_6
ADOGND ADOGND
+3V_S5 L525 PBY160808T -301Y-N_6 R728

+3AVDD *12K/F_4
L524 *PBY160808T-301Y-N_6 +AZA_VDD L526 PBY160808T-301Y-N_6

D +3VSUS +3V D
C750 C760 C753 C769 C788 C350

+3AVDD
B2A
10u/6.3V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 10u/6.3V_8
+5V R443 0_6 +5V_VDD C797 1412@0.1u/10V_4 ADOGND
C792 C793
ADOGND
SECNT L 30
10u/10V_8 0.1u/10V_4
HPL 30
HPR 30
C749 C752 C784 C791 ADOGND
0.1u/10V_4 10u/6.3V_8
C3A U516
10u/6.3V_8 0.1u/10V_4
SPKR-L C330 2.2u/6.3V _6 SPKR-L-1 R365 10.5K/F_6 SPKR-L-2 1 20
LIN1 VOL
R720 0_4 MIC1-VREFO SPKR-R C333 2.2u/6.3V _6 SPKR-R-1 R410 10.5K/F_6 SPKR-R-2 18
MIC1-VREFO 30 RIN1
R666 0_4 ADOGND INSPKL+ R709 16K/F_6 2 13
+1.5V_S5 MIC1-L 30 LIN2 IN1/IN2 ADOGND
C778 330p/25V_4 17
MIC1-R 30 RIN2
Determining HDA use +1.5V/+3V INSPKR+ R715 16K/F_6 19 INSPKR+
C783 330p/25V_4 ROUT+ INSPKR-
12
ROUT- INSPKL+
C751 24
U514 R725 *0_4 MIC1-VREFO C794 4.7u/6.3V_6 G1441_RBY LOUT+ INSPKL-
ADOGND 16 LOUT- 7
0.1u/10V_4 C785 4.7u/6.3V_6 G1441_PBY RBYPASS
3
LBYPASS
34 R424 *0_4 MIC1-R G1441_SHDN 5

PORTA_L SHDN
12 ACZ_RST#_AUDIO 11 35 R423 *0_4 MIC1-L
RESET# PORTA_R G1441_SE/BT L
ADOGND R450 0_4 11 SE/BTL
12 BIT_CLK_AUDIO 6 19
BIT_CLK MICBIASB MIC1-LL C781 2.2u/6.3V_6 G1441
12 ACZ_SYNC_AUDIO 10 14
R667 33_4 ACZ_SDIN20561 SYNC PORTB_L MIC1-RR C782
8 15 2.2u/6.3V_6
12 ACZ_SDIN0 SDATA_IN PORTB_R
C 12 ACZ_SDOUT _AUDIO 5 C
SDATA_OUT
18
Reserve for EMI MICBIASC FM_linein_L C771 2.2u/6.3V_6 FM_linein_LL FM_linein_LLL
16 R694 *10K_4
DIB_P_L PORTC_L FM_linein_RRR
30 DIB_P R689
R690
0_4
0_4 DIB_N_L
43
42
DIB_P PORTC_R
17 FM_linein_R C775 2.2u/6.3V_6 FM_linein_RR R710 *10K_4
INT SPEAKER
30 DIB_N DIB_N
R698 10K_4
FM_LEFT 26
27 R700 10K_4 ADOGND
PORTD_L FM_RIGHT 26
C754 0.1u/10V_4 PCBEEP_C 12 28
27 PCBEEP PC_BEEP PORTD_R
R361 4.7K_4 R364 1K_4 +3AVDD
R678 0_4 48 20 MIC2_INT_L C327 2.2u/6.3V_6 INT_MIC_R R358 0_4
30 SPDIF_OUT S/PDIF MIC_L INT_MIC 19
21 MIC2_INT_R C328 2.2u/6.3V_6
MIC_R
C329
29 R684 5.1K/F_4
MONO +3AVDD
GPIO2 45 30 SPKR-L 10u/10V_8
GPIO1 GPIO2 STEREO_L SPKR-R R685 5.11K/F_4
46 31 Port_A# 30
EAPD# GPIO1 STEREO_R
47
EAPD#/GPIO0 R686 10K/F_4 If Int Mic change
Port_B# 30
to Port C, and ADOGND
13 SENSEA R688 20K/F_4 remove FM. than NC
SENSEA Port_C# 14
R686
1 24 CX20561_VILT
DMIC_CLOCK VREF
2
DMIC_1/2 B2A
FLY_P
39 CX20561_FLY_P C3A
CX20561-12Z Not 37 CX20561_FLY_N C341 1u/6.3V_4
support digital MIC FLY_N CN512
CX20561-13Z support CX20561_RVD22 C796 C787 INSPKR- L23 BK1608LL121_6 INSPKR-N
PC Beep GAIN CONTROL digital MIC VREF_LO
22
1
23 CX20561_RVD23 INSPKR+ L20 BK1608LL121_6 INSPKR+N
VREF_HI 10u/6.3V_8 0.1u/10V_4 INSPKL- L19 BK1608LL121_6 INSPKL-N 25
GAIN GPIO1 GPIO2 RESERVED_32
32
36
33 INSPKL+ L18 BK1608LL121_6 INSPKL+N
RESERVED_33 C777 C772 4
0dB 10K 10K CX20561-12Z C217 C220 C221 C223 INT_SPK

R674 *10K_4 GPIO1 1u/6.3V_4 1u/6.3V_ 4 ADOGND
-6dB omit omit R681 *10K_4 GPIO2

B
ESD DIODE_6 ESD DIODE_6 ESD DIODE_6 ESD DIODE_6 B
-12dB 10K omit ADOGND
-18dB omit 10K

ADOGND
+5V_VDD
Reserve FM
B2A
Reserve INTMIC B2A B2A R428
MIC1-LL FM_linein_L MIC2_INT_L
CN17 CN521 MIC1-RR FM_linein_R MIC2_INT_R +3AVDD 100K_4
INT_MIC_R
2 1 ADOGND
ADOGND FM_linein_LLL G1441_SHDN
1 52 FM_linein_RRR R456
63 C766 C765 C776 C770 C767 C764 D519 MTW 355
*INT_MIC ADOGND 1 2
4 28 AMP_MUTE#
0.1u/10V_4 0.1u/10 V_4 *100p/50V_4 *100p/50V_4 *100p/50V_4 *100p/50V_4 10K_4
*FM_LINEIN
EAPD# D520 1 2 *MTW 355 MUTE# 2 Q38
ADOGND ADOGND ADOGND ADOGND ADOGND ADOGND H : AMP turn on B2A 2N7002E
L : AMP power do w n
ADOGND
MUTE# 30
A A

PROJECT : TE1M
E3D
Conexant CX205601
5 4 3 2 1
5 4 3 2 1
VR R420 10K_4
FM Tuner MDC
+3AVDD
BOM Option Table
R422 10K_4 C2A
DIGVOL_UP R421 VR_UP
VR500 B2A
0_4 2 1
28 DIGVOL_UP A COM 1412@ AMP HP
CN502
4 1 2 CDCHP@ CODEC HP
4 SB_GPIO7 +3V
3 4
DIGVO L _DN R449 0_4 VR_DN SB_GPIO27 GND
28 DIGVOL_DN 3 5 5 6
B 5 FM_INT NC
29 DIB_P 7
DIB_P FM_L
8 TE1M REV:A Stuff both for test
B2A 29 DIB_N 9
DIB_N FM_R
10
C340 C339 11 12
FM_SUSCLK NC
D 0.1u/10V_4 0.1u/10V_4 B2A MDC/FM D
VR_XRE094_NOBLE
B2A C556 C555
*10p/50V_4 *10p/50V_4
+3V
B2A
+3V
SYSTEM MIC
C800
*0.1u/10V_4 U40
C349 U24 5 1
2 VR_DN
*0.1u/10V_4 5 2 4 3
Vcc CLK
D
1 VR_UP
29 MIC1-VREFO
R717 4.7K_4 RAMP1 B2A CN515
1 7
DIGVOL_UP 4 3 *NL17SZ17 MIC1-L L 52 0 BK1608LL121_6 MIC1-L1 2
Q GND 29 MIC1-L
6
C347 *SN74LVC1G79DBVR MIC1-R L 52 1 BK1608LL121_6 MIC1-R1 3
29 MIC1-R
Port_B# 4
29 Port_B #
*0.1u/10V_4 8
5
+3AVDD C824 C82 3 C732 C731 MIC_JACK
DIGVOL_DN D514 *100p/50V_4 *100 p/ 50V_4 0.1u/10V_4 0.1u/10V_4 Normal OPEN Jack
C336 1
Port_B#
*0.1u/10V_4 3 CNXT suggestion can not over 100P
C C
2
B2A ADOGND
*DA204U
ADOGND
HP HP Amplifier
G1412_HPL R419 *1412@0_4 RAMP1

R415 *1412@0_4 CN520
C3A R426 *1412@10K_6
G1412_HPR
C3A HP_JD 5 9 C337 *1412@47P/50V_4
C3A 0_6 HPL_1 L527 BK1608LL121_6 HPL_SYS
4
R621 10
29 HPL
3 U22
R620 0_6 HPR_1 L522 BK1608LL121_6 HPR_SYS 2 ADOGN D
29 HPR
1
C804 C803
C805 C806 C742 C768 7 HPL_2 R412 *1412@10K_6 4 5 G1412_HPL
0.1u/6.3V_4 0.1u/6.3V_4
+3V_SPD
Drive
LED INL - OUTL
C789 *1412@10u/10V_8 HPL_2 0.1u/6.3V_4 0.1u/6. 3 V_4 *100p/50V_4 *100p/50V_4 29 8
SPDIF_ OUT 6 IC + 9
*1412@10u/10V_8 HPR_2 NC1
C790 +3AVDD 3 11
SVDD NC2
HP_JACK 15 12
R425 *1412@100K_4 PVDD NC3
+3AVDD 14
NC4
6 2
ADOGND AD OGND SVSS SGND
B +NVDD 10 13 B
D15 NVDD PGND
29 MUTE# 1 2 *1412@MTW 355 17
TPAD
29 SECNTL
D16 1 2 *1412@MTW 355 1412MUTE# 1
SHDNR# ADOGND
16
SHDNL#
+ OUTR 7
HPR_2 R429 *1412@10K_6 8 INR -
*1412@G1412
+5V C346 *1412@47P/50V_4
Port_A#
29 Port_A# +5V
Q510 R615 R430 *1412@10K_6 G1412_HPR
2N7002 10K_4 C352 *1412@4.7U/6.3V_6

C3A
R644
2 +NVDD U23
Q511 22K_4 1 3 +3AVDD +3AVDD
+3V + 3V_SPD
D516 1 6
2N7002 Q512 VOUT C+ +NVDD
1 +3AVDD
ME2347 2 5 1412MUTE#
HP_JD HP_JD VIN /SHDN
2 C364
3 C348 C338
3 4
C- GND
C807 2 *1412@4.7U/6.3V_6 *1412@.1U/10V_4
*1412@4.7U/6.3V_6
*DA20 4U *1412@G5930
ADOGND
0.1u/6.3V_4 ADOGND
ADOGND ADOGND ADOGND
A A
ADOGND

PROJECT : TE1M
E3D
Audio JACK/VR/FM
5 4 3 2 1
5 4 3 2 1
0.01_7520
VA PD1 PR14 PQ501 VIN PQ500
C3A PF1 PL1 PDS1040S-13
FDD6685 FDD6685
PJ500 LITTLE-7A_1206 HI0805R800R-00_8 1
1 1 2 3 1 2 VA2 3 4 3 4
2 2
3
4 PC28 PR7
PC5 PC6 PC12 PR11 PC501 PC500
33K_6
POW ER JACK 2200p/50V_6 PL2 0.1u/50V_6 0.1u/50V_6 0.1u/50V_6 220K/F_6 0.1u/50V_6 2200p/50V_6
HI0805R800R-00_8
D D
PC27 PC29 PD3
MLVS0603K2 0 0.1u/50V_6 P4SMAJ20A
1 6 PR6
PD501 PR9 0_6 10K_6
SW 1010CPT PR8 2 5 D/C# 28
220K/F_6
C3A PR12 PD500 3 4
*10K/F_6
ACIN_1 2 1 PQ2
26,28 ACIN
IMD2AT108
CSIN_1 2
*ZD12V
PR13 PQ1
PR16 *10K/F_6 CSIP_1 DMN601K-7
*6.8K/F_6
PL500 VIN
HI0805R800R-00_8
PC13 VA3
1u/16V_6
PR4 PR5
10/F_6 10/F_6
PR10
PC8 4.7_6 PC20
0.1u/50V _ 6 1u/16V_6
ISL88731_VDDP
C CSIP CSIN PC19 PC503 C
0.1u/50V_6 10u/25V_1206
+3VPCU PD2 PC18
RB500V 2200p/50V_6
PC14 PR15 PC15 4

+3VPCU 0.1u/50V_6 2.7_6 .1u/25V_8 PQ502
11
VDDSMB BOOT
2588731B_2 8 8 731B_1 FDS8878 C3A
PR500
PR120 28 MBDATA 9 24 ISL88731_UGATE PL501 0.01_3720
SDA UGATE
10K/F_6 PCMC063T-6R8MN
88731LR 1 2 BAT-V
28 MBCLK 10 23 ISL88731_PHASE
SCL PHASE
RAMP2
13 20 ISL88731_LGATE PR17
ACOK LGATE PC22
4
P Q503 2.2/F_6 .01u/50V_6
PR22 PC16 19 FDS6690AS
49.9/F_6 0.1u/50V_6 PGND
DCIN 22
DCIN PR23 PC17 PC23
+3VPCU PR3 10/F_6 1000p/50V_ 6 2200p/50V_6
82.5K/F_6 18 CSOP CSOP_1 CSOP_1 PC7 PC24
88731ACSET CSOP 10u/25V_1206 10u/25V_1206
2
PR 524 PR 5 25 ACIN
*10 0 K_4 10K_6 PC21
B
PR2 3 0.1u/50V_6 B
PC25 VREF CSON_1 CSON_1
22K/F_6 17 CSON
CSON PR21
HI0805R800R-00_8 4 0_4 PR19
14 ICOMP 10/F_6
PL4 16
13 MBAT+ BAT-V NC
100p/50V_6
12 PR20
5
11 NC
PD504 *RB500V-40 PL3 100_4
10 ID BAT-V
ID 28 15
9 HI0805R800R-00_8 VBF
8 6
TEMP_MBAT PR29 *100K/F_6 VCOMP
7 +3VP CU 29
GND
6 PC26 PR43 0_4 C3A
5 PC41 PU1
4 PC45 0.1u/50V_6 PR1 ISL88731 +3VPCU +3VPCU
3 2.21K/F_6
2 MTEMP 28
47p/50V_6
1 PR518 47p/50V_6
CN503 100_4
ISL88731 thermal pad ID TEMP_M BAT
PR522 PC4 3 3
B2A 100_4 MBDA TA 28 PR28 .01u/50V_6
MBCLK
*100K/F_6 PC36
.01u/50V_6 ICM
tie to Pin12 PD502 PD503
MBCL K 28 DA204U DA204U
ICM
PD5 PD4 PC3 PC1

B2A *1u/16V_6 PC2 *.01u/50V_6 A:(9/7) Add ESD diode base on EC FAE suggestion
ZD3.6V ZD3.6V .01u/50V_6
A A
PC10
*3300p/50V_6

PROJECT : TE1M
E3D
CHARGER (ISL88731)
5 4 3 2 1
5 4 3 2 1
MAIND
MAIND 35,36
SUSD
SUSD 36
3 SYS_SHDN# 1 2
PR86
0_4
D VIN VIN D
VL
+ VL PC520
0.1u/50V_6
PC59
PR56 4.7u/10V_8
390K_4
PR90 PR68
39K/F_4 PC62 0_4 PC83
PC541 PC521 PC522 PC524 PC61 PC64 1u/16V_6 10u/25V_1206
100U/25V_6X7.7 0.1u/50V_6 2200p/50V_6 10u/25V_1206 0.1u/50V_6*.01u/16V_4 PC518
PC523 2200p50V_4
*10u/25V_1206 PR66 P R 67 PC63
REFIN2 *0_6 0_4 0.1u/50V_6
3V5V_EN 4
RAMP1 REF 3V_DH PQ509
9/6 update FDS8878
PR55
OCP : 8A
115K_ 4
4 5V_DH +3VPCU
PQ510 PL507
FDS8878 2R2uH-5.8mR
OCP: 10A PR72
+3VPCU
3V_LX
+5VPCU
RAMP2 +5VPCU
9
BYP REFIN2
32 REFIN2 196K/F_6
PL506 10 31 1 2
2R2uH-5.8mR OUT1 ILIM2 PR87
C 11 PU4 30 C
+5VPCU 5V_LX FB1 OUT2 SKIP 2.2_6
1 2 12 29 4
PR82 237K/F_6 DDPWRGD_R 13 ILIM1 SKIP# DDPWRGD_R PQ512
ISL6237 28
3V5V_EN PGOOD1 PGOOD2 3V5V_EN
PR95 14 27 FDS6690AS PR75 +
PR78 EN1 EN2 0_6
15 26 PC530
63.4K/F 2.2_6 DH1 DH2 0.1u/50V_6
16 25 PC527
+ LX1 LX2
+ 4 5V_DL 37 PC75
PAD 2200p/50V_6
36
PC534 P C529 PQ511 PAD
1 0u/25V_1206 PC533 FDS6690AS PC80
PC535 330u/6.3V_6X 5.7 PC82 PC72 0.1u/50V_6
* 330u/6.3V _7343 PR77 2200p/50V_6 0.1u/50V_6 PR94
10K/F_4 1/F_6
1 2
3V_DL PR80
PR85 1/F_6 330u/6.3V_6X5.7
1 2 *0_6
0.1u/50V_6
VL PR88 SKIP PR81 *0_6 REF
0_6
2
PC78
3V_DL PC79 PR84 0_6
3 0.1u/50V_6 1u/16V_6
PD7
1 CHN217
OCP:8A PC81
0.1u/50V_6 OCP:8A
L(ripple current) PC71
0.1u/50V_6 2
=(19-5)*5/(2.2u*0.4M*19) L(ripple current) +3VPCU
~4.18A
3 PR93 *0_6 REFIN2 =(19-3.3)*3.3/(2.2u*0.5M*19)
B B
1
PD8 ~2.48A
Iocp=8-(4.18/2)=5.91A CHN217
Vth=5.91A*15mOhm=88.65mV PR91 Iocp=8-(2.48/2)=6.67A PR71

9/6 update Vth=6.67A*15mOhm=100.05mV
*10K_4 PR73
R(Ilim)=(88.65mV*10)/5uA +15V
+15V_ALWP 1 2 0_4
~177.3K R(Ilim)=(100.05mV*10)/5uA DDPWRGD_R 1 2

SYS_HWPG 28
PR92 PR89
22_8 ~200.1K
PC77
0.1u/50V_6
*200K_4 *39K_4
9/6 update
VIN +15V +5VPCU
+3VPCU
+5VPCU +3VPCU +3VPCU

PR18 PR97
1M_6 1M_6
S5D 2
PQ519 SUSD 2
DMN601K-7 S5D 3 PQ517
2 MAIND 3 PQ515 MAIND 4 FDC653N_NL PQ516
28,36 S5_ON
2 FDC653N_NL DMN601K-7
PR24
1M_6 PQ9 PQ518
PQ3 DMN601K-7 FDS8884
+3V_S5
DTC144EU
+5V_S5
A +3VSUS A
+5V +3V

C2A:(12/10) change S5_ON control circuit
B1C:(11/29)Change PQ26 from FDS6690AS (BAM66900022) to FDS8884 (BAM88840006) PROJECT : TE1M

E3D
SYSTEM 5V/3V (ISL6237)
5 4 3 2 1
5 4 3 2 1
+3VPCU +3VPCU PC515

2200p/50V_6
VIN_6262A
VIN
D D
PR64 PR63 PR62 PR61 PR60 PR59 PR58 + PC502
*0_6 *0_6 *0_6 *0_6 *0_6 *0_6 *0_6 PC51 100u/25V_6X7.7
0.1u/50V_6
DELAY_VR_PW RGOOD 3,6,14

PC54
H_VID6 H_VID5 H_VID4 H_VID3 H_VID2 H_VID1 H_VID0 10u/25V_1206 PC55
6262A_UG1 4 10u/25V_1206
VCC_CORE
PR42 4.99K/F_6 VIN_6262A +3V PQ507
PW R_MON 2 1 PGD_IN TPS8023-H
PL503 0.36uH
6262A_PH1 1 2
PC53 PR507
0.1u/50V_6 10/F_6 PR45 PR41
10_4 1.91K/F_4 PR526 + PC44 + PC34
+5V_S5 *560U/2 V_7
2.2_6
330u/2V_ 7 343
6262A_LG1 4
3 PSI# PSI# PC505
PR502 0.1u/50V_6
10/F_6 PC52
0.1u/50V_ 6
PQ508
TPS8019-H
PC516
2200p/100V_6
C3A
PR503 PR501
PR27 0_8 C3A 0_6 0_6
PC504
1u/25V_8
PR509 3.65K/F_6
VSUM
21 35
GND UGATE1
PR38 2.2_6 PR510 10K/F_6
Close to Phase 1 Inductor 49
GND_T BOOT 1
36 1 2
+3V_S5
Throttling temp. PC 49
PR506 1/F_6
C C
105 degree C 0.22u/25V_8
34 PR513 *0_6
PSI# PSI #_1 PHASE1 ISEN2
PR44 0_4 2
PSI#
32
LGATE1
PR36 VR_ON PR40 *0_4 PGD _ IN 3
PGD_IN VIN
*10K/F_4 33
PGND1
PR39 147K/F_6 4
RBIAS ISEN1
24 PC31
ISEN1
5 2200p/50V_6
3 H_PROCHOT# VR_T T#
PR528 470K_4 NTC PR37 4.02K/F_4 6 PC512
NTC
0.22u/25V_6
+5V_S5
2 1 PC4 6 7
SOFT PC47
PC48 1 2 0.022u/ 5 0V_6 PC30 PC33 PC32
PSI#_1 .01u/16V_4 31 1 2 10u/25V_1206 10u/25V_1206 0.1u/50V_6
H_VID0 PVCC
37
VID0
Panasonic 4 H_VID0
H_VID1 PU2
4.7u/25V_8
6262A_UG2
38 27 4
ERT-J0EV474J 4 H_VID1 VID1 UGATE2
PR33 2.2_6
PR46 H_VID2 39 26 1 2
4 H_VID2 VID2 BOOT 2
*0_6 ISL6262AHRZ-T
H_VID3 40 PQ504
4 H_VID3 VID3
PC 43 TPS8023-H
H_VID4 41 0.22u/25V_8 PL502 0.36uH
4 H_VID4 VID4
28 6262A_PH2 1 2
DPRSLPVR H_VID5 PHASE2
4 H_VID5 42
VID5
30 6262A_LG2
H_VID6 LGATE2
43 PR30
4 H_VID6 VID6
29 2.2_6
PGND2 + PC56 + PC50
PR51 0_4 VR_ON 44 4
28 VRON VR_ON
23 ISEN2 *560U/2V_7
ISEN2
PR52 499/F_4 DPRSLP VR 45 PC42 330u/2V_7343
6,14 PM_DPRSLPVR DPRSLPVR
PR50
10K_4 PR53 0_4 46 PC508 PQ505 2200p/100V_6
3,6,12 ICH_DPRSTP# DPRSTP#
0.22u/25V_6 TPS8019-H
PR47 0_4 CLKEN# 47 PR517 PR512
14 VR_PW RGD_CK410# CLK_EN#
B
PC38 1000p/50V_4 0_6 0_6
C3A B
PR26 1K/F_4 25 2 1
NC
PR25 255/F_4 8
OCSET
1 2 13 PR35 13.3K/F_4
VDIFF
C3A PC35 V S UM
19
VSUM
1000p/50V_6
PR31 1K/F _4
12
FB2
PR508 PR505
11K/F_4 2.7K/F_4
11 PC506
FB
68 n /25V_6 PR516 3.65K/F_6
PR32 97.6K/F_4 PC40 470p/50V_4 VSUM
2 1 PC510
0.22u/1 0 V_6 PR527 PR519 10K/F_6
10 10K _6 NTC
COMP
PC37 220p/50V_4
2 1 PR504 1/F_6
18
VO
PR34 6.81K/F_4
Panasonic PR511 *0_6
9
VW ERT-J1VR103J ISEN1
1 2 PR521
1K/F_4 PC507
PC39 1000p/50V_6 0.22u/25V_6 Close to Phase 1 Inductor
PC514 2 1
.01u/16V_4
PR515 3.48K/F_4
PC509 180p/50V_4
C3A 2 1 ISL6262_VO
PC513 PC511
A .01u/16V_4 .01u/16V_4 A
PR514 0_4
Parallel
VCCSENSE 4
VSSSENSE 4
PR523 0_4

PROJECT : TE1M
E3D
CPU CORE(ISL6262A)
5 4 3 2 1
1 2 3 4 5
A A
VIN-1.05V
VIN
+5V_S5
PR49
10_6
P D6
RAMP2 PC76
R B 500V 0.1u/50V_6
PC67 RAMP2
PR57 PC68
B 1M_6 *.1u/50V_6 4 B
4.7u/0V_8 P Q6
PR74 AO4468 PC70 PC74
2.2_6 10u/25V_1206 10u/25V_1206
P C69
PR70 47K_6 . 1u/25V_8 C3A OCP=12.17A
18,22,28,35,36 MAINON 15 13
EN/DEM BOOT PL504
+3V 16 12 UGATE-1.05V 2R2uH-5.8mR
PC66 TON UGATE
0.1u/50V_6 1 11 PHASE-1.05V
VOUT PHASE +1.05V
2 10 PR79 2.8K/F_6 PQ7
PR65 VDD PU3 OC AOL1412
*10K_6 3 RT8202 9 PR83
FB VDDP LGATE-1.05V 2.2_6 +
4
4 8 PR48
28 HW PG_1.05V PGOOD LGATE PC58
6 7 PC73 4.02K/F_6 33p/50V_6
GND PGND
B2A B2A
5 17 2200p/50V_6
NC TPAD
PC57 PC60 PC65

14
NC Rds*OCP=RILIM*20uA PC526 PC525 PR54
1u/16V_6 560u/2.5V_6X5.7 22u/6.3V_8 10K/F_6
C
*1000p/50V_6 .01u/50V_6
1.05V_FB
VOUT=(1+R2/R3)*0.75 C
TON=3.85p*RTON*Vout/(Vin-0.5) AO1412 Rds=4.6mOhm

12.17A OCP --- OC=2.8K(CS22803F914)
Frequency=Vout/(Vin*TON)
D D

PROJECT :TE1M
E3D
VTT 1.05V (RT8202)
1 2 3 4 5
5 4 3 2 1
D D
VIN
+1.8VSUS
PC536
PQ514
10u/10V_1206 4 AOL1414
PU500
TPS51116 PC531 PC528 PC532
1
VLDOIN DRVH 19 RAMP2 2200p/50V_6 10u/25V_1206 10u/25V_1206
OCP=15.8A
+SMDDR_VTERM 2
VTT VBST
20 PC537 0.1u/50V_6 C3A
PL505
4 18 +1.8VSUS
PC91 PC90 VTTSNS LL
10u/10V_8 10u/10V_8 5 17 1.0uH-3.0mR
GND DRVL
3 16 +
VTTGND PGND PR96
DIS_MODE 6 11 S3_1.8V PR533
C MODE S3 0_6 MAINON 18,22,28,34, 36 C
*2.2/F_6
7 12 S5_1.8V PR531
+SMDDR_VREF VTTREF S5 0_6 SUSON 28,36
4
PR529 5VIN 8 14 5VIN
0_6 PC539 COMP V5IN PR530 PC84 PC517 PC519
0.033u/50V_6 9
VDDSNS PGOOD
13 100K/F_6 +3VPCU
+3VPCU RAMP2 P Q513 *2200p/50V_6 560u/2.5V_6X5.7 10u/10V_8L
A OL1412
5VIN 10 15
VDDQSET CS
PR532
0_6 PC98 (10u*PR35)/Rdson+Delta_I/2=Iocp
PR116
*1000p/50V_6 5.1K/D _ 6
PR115 *0_6 DIS_MODE FOR DDR II

5VIN
+5VPCU HW PG_1.8V 6,28
PR117 PC99
0_6
+1.8VSUS PR113 0_6 4.7u/6.3V_6
PR118
R2 *110K/F_6
S3_1.8V S5_1.8V
B R1 PR119
*76.8K/F_6 PC540 PC538 B
*0.1u/50V_6 *0.1u/50V_6
+1.8VSUS
R1=(100*Vout-R2)K
if tune Vout PR38 un-mount, PR156 PR165 mount
3 PQ520
32,36 MAIND FDC653N_NL
+1.8V
A A

PROJECT : TE1M
E3D
DDR 1.8V(TPS51116)
Date: Monday, July 28, 2008 Sheet 35 of 40
5 4 3 2 1
5 4 3 2 1
+1.8VSUS
+3V_S5
PR105
100K_4
PU5
D D
5 7 HW PG_1.5V 28
VIN POK
9 1
PC94 PC89 VIN1 GND
10u/6.3V_8 0.1u/10V_4 +1.5V
2.6A
18,22,28,34,35 MAINON 8 3
EN VOUT
PR107 +5V_S5
0_6 6 4 PC92 PC95 PC93
PR106 VCNTL VOUT
100K_4 10u/6.3V_8 10u/6.3V_8 0.1u/10V_4
APL5913 PR112
88.7K/F_4
PC87 PC88 1 2
*0.1u/50V_6 1uF/10V_4 PR111
100K/F_4 PC96
47nF/50V_4
Vout =0.8(1+R1/R2)
=1.25V
C C
VIN +SMDDR_VREF +1.8VSUS +3VSUS +15V
PR69 PR109 PR110 PR98 PR102

PU6 0.15A
1M_6 22_8 22_8 22_8 1M_6 PR114
28,32 S5_ON 2 1 3 5 +1.5V_S5
SHDN VO
SUS_ON_G SUSD 0_6 2
SUSD 32 GND
1 4 PC100
VIN NC 1u/16V_6
+3VPCU
PR76 G909
2 1M_6 2 2 2 2 PC101
28,35 SUSON PC86 2.2u/10V_6
PQ17 PQ16 PQ8 PQ13 *2200p/50V_4
PQ5 DMN601K-7 DMN601K-7 DMN601K-7 DMN601K-7
D TC144EU
B PR170 PC97 B
*100K_4 *0.1u/50V_6
B2A
VIN +3V +5V +SMDDR_VTERM +1.8V +15V
PR100 PR101 PR104 PR108 PR103 PR99

1M_6 22_8 22_8 22_8 22_8 1M_6
MAINON_ON_G MAIND
MAIND 32,35
A PR520 A
2 1M_6 2 2 2 2 2
18,22,28,34,35 MAINON PC85
PQ14 PQ11 PQ15 PQ12 PQ10 *2200p/50V_4
PQ506 DMN601K-7 DMN601K-7 DMN601K-7 DMN601K-7 DMN601K-7
DTC144EU

PROJECT : TE1M
E3D
Discharge/1.25/1.5
5 4 3 2 1
5 4 3 2 1
Power Tree Table
ISL6262A
D
PU2 VCC_CORE D
P33 VRON enable

AC DMN601K-7 G909
System +1.5V_S5
+5V_S5 PU6
PQ519 S5_ON enable
Charger P32 S5_ON enable P36
DC +5VPCU
AC/DC Insert enable FDC653N_NL APL5913
+1.5V
+5V PU5
ISL6237 PQ515 MAINON enable
MAINON enable P36
P32
PU4
FDS8884
+3VPCU +3V
AC/DC Insert enable PQ518 MAINON enable
P32 P32
FDS653N_NL
RT8202
+3V_S5
PU3 +1.05V PQ517
C
S5_ON enable C
MAINON enable P32

P34
DMN601K-7
+3VSUS
PQ516 SUSON enable
+SMDDR_VTERM
SUSON enable P32
TPS51116
PU7
+SMDDR_VREF
SUSON enable FDS653N_NL
+1.8V
+1.8VSUS PQ520
P35 MAINON enable
SUSON enable P35
B
Power Distribution List B
Power Distribution
VCC_CORE CPU
+5VPCU ICH9M, HDMI, MMB, Power Board, RJ45/USB Board, LED Board, USB, CIR
+3VPCU ICH9M, HALL SENSOR, LCD/LED Panel, KB, MMB, Kill SW, EC, SPI Flash, CIR, ID
+1.5V CPU, GMCH, ICH9M, Mini Card, New Card
+1.8VSUS GMCH, DDR
+SMDDR_VREF GMCH, DDR
+SMDDR_VTERM DDR
+1.05V CPU, CLK, Thermal Trip, GMCH, ICH9M
+5V_S5 ICH9M, G-SENSOR
+5V CPU, ICH9M, VGA, Camera, CRT, HDMI, SATA HDD, SATA ODD, PCMCIA, TP/LED Board, Felica, WiMAX LED, EC, INT SPK AMP, HP
CLK, CPU Thermal Monitor, FAN, GMCH, DDR, ICH9M, VGA, LCD/LED Panel, HALL SENSOR, CRT, HDMI, SATA HDD, PCMCIA, Cardreader(OZ129T)
A
+3V A
Mini Card, KB, FP/LED Board, RJ45/USB Board, Bluetooth, New Card, PC Beep, EC, Codec(CX20561), HP, FM Tuner/MDC
+3V_S5 ICH9M, HDMI, Mini Card, RJ45/USB Board, New Card, Codec(CX20561)
+3VSUS Codec(CX20561)
+1.8V Cardreader(OZ129T) Quanta Computer Inc.
PROJECT : TE1M
+1.5V_S5 ICH9M, Codec(CX20561) Size Document Number R ev
E3D
Power Tree Table
5 4 3 2 1

TE1M motherboard part numbers and diagram

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TE1M motherboard part numbers and diagram

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1 2 3 4 5 6 7 8

TE1M MB(PM45/RB/MS)WO CPU

31TE1MB0130 TE1M MB(GM45/EXP/NO CIR/MS)WO CPU

31TE1MB0140 TE1M MB(GM45/GS/EXP/MS)WO CPU

PCI-E x16 PI3VDP411LST INT_HDMI

USB-9 CLOCK GENERATOR

W25X16VSS1G SPI PCI PCI Bus CB1410 PCMCIA SOCKET +1.5V

INT_ MIC +1.5V_S5

Clock Generator +1.05V_VDD

PBY160808 T-301 Y-N_6 L 17

D C694 0.1u/10V_4 U12 D

FREQ. SEL TABLE Clock Gen I2C +3V

R601 0_4 CLK_BSEL0 RHU002N06 10K_4

3 1 CGDA T_S MB PCLK_PCM C225 *33 p/50V_4

BSEL Frequency Select Table R602 1K_4 +3V

0 0 0 266Mhz R228 0_4 CLK_BSEL1

1 1 1 Reserved R232 *0_ 4

Date: Monday, May 26, 2008 Sheet 2 of 40

Thermal Trip +1.05V +1.05V

2 Q5 R40 D2 Reserve 1K for XDP function +1.05V

CPU FAN CTRL LM95245 : AL095245000

Processor hot +3V

Quanta Computer Inc.

BOM Option Table

Need NC 20PCS 10u before A1 BOM released(A0 all stuff)

Place these parts reference Layout Note:

VCCP O X X +1.05V 4.5A Before VCC Stable

(See Penryn EMTS Rev:1.0 Table7,8 for voltage and current)

BOM Option Table

BOM Option Table

U504B Reference Description

+1.8VSUS_GMCH +1.8VSUS_GMCH R553 1K/F_4 SM_RCOMP_VOH R162 EV@0_4 HSYNC_G For IV @ NC

BOM Option Table

Quanta Computer Inc.

BOM Option Table

D AP33 W 28 C598 C594 C122 + C156 D

1. Route VCC_AXG_SENSE and VSS_AXG_SENSE differentially

Quanta Computer Inc.

BOM Option Table

B2A +1.5V R566 0_8 +1.5V_VCCA_PEG_BG AD48

VCCA_TV_DAC O X X +3.3V 79mA VCCA_DPLLB GND +1.05V DR11

VCCD_LVDS O O X +1.8VSUS 60mA NB (5/7)- POWER E3D

D ate: Monday, May 26, 2008 S heet 9 of 40

BOM Option Table

North Bridge Strap Pin Configuration Table BOM Option Table

Pin Name Strap description Configuration PU<4.02K> PD <2.21K> Note

DMI X2 Select 0 = DMI X2 R141 *4.02K/F_4

PCI Express Graphics 0 = Reverse Lanes R540 *4.02K/F_4

PCIE Loopback enable 0 = Enabled R542 *4.02K/F_4

CFG12 ALLZ 0 = ALLZ mode enable R130 *4.02K/F_4

XOR 0 = XOR mode enable R131 *4.02K/F_4

CFG16 FSB Dynamic ODT 0 = Dynamic ODT disable R129 *4.02K/F_4

B CFG19 DMI Lane Reversal 0 = Normal (Default) R124 *4.02K/F_4 B

0 = Only Digital Display port (SDVO/DP/iHDMI) or PCIE is

0 = No SDVO/HDMI/DP Device Present(Default)

Enable iTPM Table

PAGE Net Name PU & PD NOTE

RTC CRYSTAL Layout note:

SATA_RXN1 C746 3900p/25V_4 SATA_RXN1_C

HD Audio I/F(CODEC& iHDMI) RTC BATTERY

R693 IHM@33_4 +3VPCU +VCCRTC

PCI Express Lane Reversal Internal PU

R344 iTPM@100/F_4 +3V_S5 ICH_GPIO24 R320 10K_4

HDMI@10K _4 LOW@10K_4 GS@10K_4 LED@10K_4 CB@10K_4 *10K_4 PROJECT : TE1M

Cardbus +3V PCLK_PCM R329 CB@22_4 PCLK_PCM_M C293 CB@10p/50V_4 +3V