System DC/DC converter diagram

5 4 3 2 1
SYSTEM DC/DC
JM41 Block
Project code: 91.4CQ01.001 TPS51125 36
PCB P/N : 48.4CQ01.011 INPUTS OUTPUTS
REVISION : 08266-1 5V_S5(6A)
3D3V_S5(5A)
Diagram
DCBATOUT
5V_AUX_S5
D
PCB STACKUP D
3D3V_AUX_S5
TOP L1
Thermal Sensor
Intel
CLK GEN. CPU SMSC S L2
RT8202 37
ICS9LPRS365B Penryn SFF EMC2103 32 VCC/GND L3

INPUTS OUTPUTS
3
S L4 DCBATOUT 1D05V_S0(10A)
4,5,6
VCC/GND L5
HOST BUS 667/800/1066MHz@1.05V RT8202 38
GND/VCC L6
DDR3 Cantiga-GS SFF LVDS LCD S L7

INPUTS OUTPUTS
19
800/1066 17,18
MHz AGTL+ CPU I/F BOTTOM L8
DCBATOUT 1D5V_S3(11A)
DDR Memory I/F RGB CRT CRT

C
DDR3 INTEGRATED GRAHPICS
20 RT9026 39
C
800/1066 17,18
MHz LVDS, CRT I/F
7,8,9,10,11,12
PCIex16 HDMI
21
INPUTS OUTPUTS
X4 DMI 5V_S5 DDR_VREF_S3

C-Link0
400MHz (1.2A)
Int MIC
CHARGER
29 ICH9M SFF MAX8731A 41
6 PCIe ports
PCIe LAN
Giga LAN TXFM RJ45 INPUTS OUTPUTS
Line Out 27 27
PCI/PCI BRIDGE Atheros AR8131 26
Codec AZALIA ACPI 2.0 CHG_PWR
29 Realtek PCIe DCBATOUT
4 SATA 18V 6.0A
ALC269Q 28
Mini 1 Card
12 USB 2.0/1.1 ports
WLAN 31
MIC In ETHERNET (10/100/1000MbE) CPU DC/DC
ADP3207A
High Definition Audio USB 35
B 29 Mini 2 Card B
LPC I/F
Serial Peripheral I/F 3G 31 INPUTS OUTPUTS
Matrix Storage Technology(DO)
DCBATOUT
VCC_CORE
Active Managemnet Technology(DO) 0~1.3V
29 64A
LPC BUS VGA

INT.SPKR 13,14,15,16 ISL6263A
1.5W 40
USB SPI BIOS LPC INPUTS OUTPUTS
SATA Mini USB KBC (2MB)
Winbond 34 DEBUG
HDD SATA Blue Tooth
24
Camera WPCE773LA0DG CONN. DCBATOUT
VCC_GFXCORE
22 (7A)
33
MEDIA
SATA USB KEY
<Core Design>
36
A ODD SATA 4 Port 25 Wistron Corporation A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

23 Touch INT. Taipei Hsien 221, Taiwan, R.O.C.
SATA Cardreader Pad 35 KB 33 MS/MS Pro/xD Title
RTS5159 BLOCK DIAGRAM

SSD SATA 30 /MMC/SD Size Document Number Rev
Custom
22 30 JM41_UMA -1
Date: Monday, March 09, 2009 Sheet 1 of 40
Dr-Bios.com
5 4 3 2 1
A B C D E
ICH9M Integrated Pull-up Cantiga chipset and ICH9M I/O controller
ICH9M Functional Strap Definitions Hub strapping configuration
ICH9 EDS 642879 Rev.1.5 page 92
and Pull-down Resistors Montevina Platform Design guide 22339
page 218
0.5
Signal Usage/When Sampled Comment ICH9 EDS 642879 Rev.1.5
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 Pin Name Strap Description Configuration
PCIE Port Config1 bit1, pulled low.When TP3 not pulled low at rising edge SIGNAL Resistor Type/Value
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers: CL_CLK[1:0] PULL-UP 20K CFG[2:0] FSB Frequency 000 = FSB1067
offset 224h). This signal has weak internal pull-down Select 011 = FSB667
CL_DATA[1:0] PULL-UP 20K 010 = FSB800
others = Reserved
4 HDA_SYNC PCIE config1 bit0,
Rising Edge of PWROK.
This signal has a weak internal pull-down.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
CL_RST0# PULL-UP 20K
CFG[4:3] Reserved
4
DPRSLPVR/GPIO16 PULL-DOWN 20K CFG8
GNT2#/ PCIE config2 bit2, This signal has a weak internal pull-up. CFG[15:14]
GPIO53 Rising Edge of PWROK. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) ENERGY_DETECT PULL-UP 20K CFG[18:17]
GPIO20 Reserved This signal should not be pulled high. HDA_BIT_CLK PULL-DOWN 20K
CFG5 DMI x2 Select 0 = DMI x2
GNT1#/ ESI Strap (Server Only) ESI compatible mode is for server platforms only. HDA_DOCK_EN#/GPIO33 PULL-UP 20K 1 = DMI x4 (Default)
GPIO51 Rising Edge of PWROK This signal should not be pulled low for desttop CFG6 iTPM Host 0= The iTPM Host Interface is enabled(Note2)
and mobile. HDA_RST# PULL-DOWN 20K Interface 1=The iTPM Host Interface is disalbed(default)
HDA_SDIN[3:0] PULL-DOWN 20K 0 = Transport Layer Security (TLS) cipher
Top-Block Sampled low:Top-Block Swap mode(inverts A16 for CFG7 Intel Management suite with no confidentiality
GNT3#/ Swap Override. all cycles targeting FWH BIOS space). HDA_SDOUT PULL-DOWN 20K engine Crypto strap 1 = TLS cipher suite with
GPIO55 Rising Edge of PWROK. Note: Software will not be able to clear the confidentiality (default)
Top-Swap bit until the system is rebooted HDA_SYNC PULL-DOWN 20K
0 = Reverse Lanes,15->0,14->1 ect..
without GNT3# being pulled down. GLAN_DOCK# The pull-up or pull-down active when configured for native CFG9 PCIE Graphics Lane 1= Normal operation(Default):Lane
GLAN_DOCK# functionality and determined by LAN controller Numbered in order
GNT0#: Boot BIOS Destination Controllable via Boot BIOS Destination bit GNT[3:0]#/GPIO[55,53,51] PULL-UP 20K
SPI_CS1#/ Selection 0:1. (Config Registers:Offset 3410h:bit 11:10). 0 = Enable (Note 3)
GPIO58 Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. GPIO[20] PULL-DOWN 20K CFG10 PCIE Loopback enable 1= Disabled (default)
Integrated TPM Enable, Sample low: the Integrated TPM will be disabled. GPIO[49] PULL-UP 20K 00 = Reserve
Rising Edge of CLPWROK Sample high: the MCH TPM enable strap is sampled CFG[13:12] XOR/ALL 10 = XOR mode Enabled
SPI_MOSI low and the TPM Disable bit is clear, the LDA[3:0]#/FHW[3:0]# PULL-UP 20K 01 = ALLZ mode Enabled (Note 3)
Integrated TPM will be enable. 11 = Disabled (default)
LAN_RXD[2:0] PULL-UP 20K
3 DMI Termination Voltage, The signal is required to be low for desktop LDRQ[0] PULL-UP 20K
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default) 3
Rising Edge of PWROK. applications and required to be high for
GPIO49 mobile applications. LDRQ[1]/GPIO23 PULL-UP 20K 0 = Normal operation(Default):
CFG19 DMI Lane Reversal Lane Numbered in Order
PME# PULL-UP 20K
1 = Reverse Lanes
PCI Express Lane Signal has weak internal pull-up. Sets bit 27 PWRBTN# PULL-UP 20K DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)
SATALED# Reversal. Rising Edge of MPC.LR(Device 28:Function 0:Offset D8) DMI x2 mode[MCH -> ICH]:(3->0,2->1)
of PWROK. SATALED# PULL-UP 15K
SPKR No Reboot. If sampled high, the system is strapped to the SPI_CS1#/GPIO58/CLGPIO6 PULL-UP 20K Digital Display Port 0 = Only Digital Display Port
Rising Edge of PWROK. "No Reboot" mode(ICH9 will disable the TCO Timer (SDVO/DP/iHDMI) or PCIE is operational (Default)
system reboot feature). The status is readable SPI_MOSI PULL-DOWN 20K CFG20 Concurrent with PCIe 1 =Digital display Port and PCIe are
via the NO REBOOT bit. operting simulataneously via the PEG port
SPI_MISO PULL-UP 20K
0 =No SDVO Card Present (Default)
TP3 XOR Chain Entrance. This signal should not be pull low unless using SPKR PULL-DOWN 20K SDVO_CTRLDATA SDVO Present
Rising Edge of PWROK. XOR Chain testing. 1 = SDVO Card Present
TACH_[3:0] PULL-UP 20K
0 = LFP Disabled (Default)
GPIO33/ Flash Descriptor Sampled low:the Flash Descriptor Security will be TP[3] PULL-UP 20K Local Flat Panel
HDA_DOCK Security Override Strap overridden. If high,the security measures will be L_DDC_DATA (LFP) Present 1= LFP Card Present; PCIE disabled
_EN# Rising Edge of PWROK in effect.This should only be enabled in manufacturing USB[11:0][P,N] PULL-DOWN 15K
environments using an external pull-up resister. NOTE:
1. All strap signals are sampled with respect to the leading edge of
the (G)MCH Power OK (PWROK) signal.
2. iTPM can be disabled by a 'Soft-Strap' option in the
2 Flash-decriptor section of the Firmware. This 'Soft-Strap' is 2
activated only after enabling iTPM via CFG6.
Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.
1 <Core Design>
1
Dr-Bios.com
Wistron Corporation
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reference
Size Document Number Rev
A3
JM41_UMA -1
Date: Sunday, March 01, 2009 Sheet 2 of 40
A B C D E
1D05V_S0 3D3V_S0
3D3V_S0
1 R61 2 1D05V_CLK_S0
R195 2 3D3V_48MPWR_S0 0R0603-PAD C404 C401 C394 C397 C400 C412 3D3V_CLK_S0 R197 2
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1 1
1
0R0603-PAD C407 C420 C393 C411 C417 C406 C418 0R0603-PAD
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1
1
C405 C226
SC1U10V3KX-3GP
SC4D7U10V5ZY-3GP
SC4D7U6D3V3KX-GP
2
2
2
4 4
3D3V_CLK_S0 1D05V_CLK_S0
3D3V_48MPWR_S0
U27
16
46
62
23
19
27
43
52
33
56
4
9 VDDPCI
VDDREF
VDD48
VDD96_IO
VDDPLL3_IO
VDDSRC_IO
VDDSRC_IO
VDDSRC_IO
VDDCPU_IO
VDDSRC
VDDCPU
VDDPLL3
CL=20pF±0.2pF
C416 SC10P50V2JN-4GP
1 2 GEN_XTAL_IN CPUT0 61
60
CLK_CPU_BCLK 4 CPU
CPUC0 CLK_CPU_BCLK# 4
GEN_XTAL_OUT 3 X1 CPUT1_F 58 CLK_MCH_BCLK 7 NB
1
2 X2 CPUC1_F 57 CLK_MCH_BCLK# 7
X2
PCLKCLK4
X-14D31818M-50GP
82.30005.A51 33R2J-2-GP CPUT2_ITP/SRCT8 54
53
CLK_PCIE_ICH 14 SB DMI
2 CPUC2_ITP/SRCC8 CLK_PCIE_ICH# 14
C419 SC10P50V2JN-4GP 14 CLK48_ICH 2 1CLK_48 17
R203 USB_48MHZ/FSLA
1 2
1
R207 51
R201 2 SRCT7/CR#_F
4,8 CPU_SEL0 1 2K2R2J-2-GP SRCC7/CR#_E 50 CR#_E
10KR2J-3-GP
14 PM_STPPCI# 45 PCI_STOP#
3D3V_S0 14 PM_STPCPU# 44 CPU_STOP# SRCT6 48
47
CLK_PCIE_MINI1 25 Wireless
SRCC6 CLK_PCIE_MINI1# 25
2
3 3 2 PCLKCLK2 41 CLK_PCIE_LAN 25
3
PCLKCLK5 SRCT10
4 1 16,17,18 SMBC_ICH 7
6
SCLK SRCC10 42 CLK_PCIE_LAN# 25 LAN
RN30 16,17,18 SMBD_ICH SDATA
40 CR#_H
SRN10KJ-5-GP 3D3V_S0 SRCT11/CR#_H
14 CLK_PWRGD 63 CK_PWRGD/PD# SRCC11/CR#_G 39
10KR2J-3-GP 2
SB_20090205 R200
DY 1 SRCT9
SRCC9
37
38
8 PCI0/CR#_A
1
RN29
4 PCLKCLK4 2 1 PCLKCLK2
10
11
PCI1/CR#_B SRCT4 34
35
CLK_MCH_3GPLL 8 NB CLK
28 PCLK_KBC 29 PCLK_FWH PCI2/TME SRCC4 CLK_MCH_3GPLL# 8
14 PCLK_ICH 2 3 PCLKCLK5 R204 22R2J-2-GP 12
PCLKCLK4 PCI3 CR#_C
13 PCI4/27_SELECT SRCT3/CR#_C 31
SRN33J-5-GP-U PCLKCLK5 14 32 CR#_D
PCI_F5/ITP_EN SRCC3/CR#_D
SRCT2/SATAT 28
29
CLK_PCIE_SATA 13 SB SATA
SRCC2/SATAC CLK_PCIE_SATA# 13
CLK_ICH14
DY 4,8 CPU_SEL1 64 FSLB/TEST_MODE
1 2 4,8 CPU_SEL2 2 1 10KR2J-3-GP CPU_SEL2_R 5 REF0/FSLC/TEST_SEL
PCLK_ICH
DY EC48 SC22P50V2JN-4GP R205
R2062 27MHZ_NONSS/SRCT1/SE1 24 DREFSSCLK 8
1 2 14 CLK_ICH14 1 33R2J-2-GP 55 NC#55 27MHZ_SS/SRCC1/SE2 25 DREFSSCLK# 8
PCLK_KBC
DY EC49 SC22P50V2JN-4GP
1 2 20 DREFCLK 8
GNDSRC
GNDSRC
GNDSRC
GNDCPU
SRCT0/DOTT_96
GNDREF
GNDPCI
DY EC52 SC22P50V2JN-4GP 21 DREFCLK# 8
GND48
CLK48_ICH SRCC0/DOTC_96
1 2
GND
GND
GND
EC47 SC22P50V2JN-4GP
3D3V_S0
ICS9LPRS365BKLFT-GP-U
18
15
1
22
30
36
49
59
26
65
2 2
EMI capacitor for Antenna team suggestion 71.09365.A03
4
3
2
1
2nd = 71.08513.003 RN23
3RD = 71.00875.C03 SRN10KJ-6-GP
ICS9LPRS365YGLFT setting table
PIN NAME DESCRIPTION
5
6
7
8
RN22
8 CLK_MCH_OE# 1 8 CR#_D
Byte 5, bit 7
14 SATACLKREQ# 2 7 CR#_C
CR#_H
0 = PCI0 enabled (default)
25 LAN_CLKREQ# 3 6
CR#_E SEL2 SEL1 SEL0
PCI0/CR#_A 1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
25 WLAN_CLKREQ# 4 5
CPU FSB
0 = CR#_A controls SRC0 pair (default), SRN470J-3-GP FSC FSB FSA
1= CR#_A controls SRC2 pair
Byte 5, bit 5 PIN NAME DESCRIPTION 1 0 1 100M X

0 = PCI1 enabled (default)
0 0 1 133M 533M
PCI1/CR#_B 1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 1
Byte 5, bit 4 0 = SRC3 enabled (default)
0 1 1 166M 667M
0 = CR#_B controls SRC1 pair (default)
SRCC3/CR#_D 1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair
1= CR#_B controls SRC4 pair Byte 5, bit 0
0 = CR#_D controls SRC1 pair (default) 0 1 0 200M 800M
PCI2/TME 0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed
1= CR#_D controls SRC4 pair
0 0 0 266M 1067M
Byte 6, bit 7
1
PCI3 SRCC7/CR#_E 0 = SRC7# enabled (default)
1= CR#_F controls SRC6 <Core Design> 1
PCI4/27M_SEL 0 = Pin17 as SRC-1, Pin18 as SRC-1#, Pin13 as DOT96, Pin14 as DOT96# Byte 6, bit 6
Wistron Corporation
Dr-Bios.com
1 = Pin17 as 27MHz, Pin 18 as 27MHz_SS, Pin13 as SRC-0, Pin14 as SRC-0#
SRCT7/CR#_F 0 = SRC7 enabled (default)
1= CR#_F controls SRC8
PCI_F5/ITP_EN 0 =SRC8/SRC8#
1 = ITP/ITP# Byte 6, bit 5 Taipei Hsien 221, Taiwan, R.O.C.
Byte 5, bit 3 SRCC11/CR#_G 0 = SRC11# enabled (default)

1= CR#_G controls SRC9 Title
0 = SRC3 enabled (default)
Clock Generator
SRCT3/CR#_C 1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair Byte 6, bit 4
Byte 5, bit 2
0 = CR#_C controls SRC0 pair (default), SRCT11/CR#_H 0 = SRC11 enabled (default)
1= CR#_H controls SRC10
JM41_UMA -1
1= CR#_C controls SRC2 pair
Date: Thursday, March 05, 2009 Sheet 3 of 40
A B C D E
A B C D E
H_A#[35..3]
7 H_A#[35..3]
H_DINV#[3..0]
H_DINV#[3..0] 7
1 H_DSTBN#[3..0]
H_DSTBN#[3..0] 7
CPU1A 1 OF 6 TP5 TPAD14-GP
H_A#3 P2 M4 1D05V_S0 H_DSTBP#[3..0]
A3# ADS# H_ADS# 7 H_DSTBP#[3..0] 7
H_A#4 V4 J5 H_BNR# 7
H_A#5 A4# BNR# Place testpoint on H_D#[63..0]
4 W1 A5# BPRI# L5 H_BPRI# 7 H_D#[63..0] 7 4
H_A#6 T4 H_IERR# with a GND
A6#
1
H_A#7 0.1" away
ADDR GROUP 0
AA1 A7# DEFER# N5 H_DEFER# 7
H_A#8 AB4 F38 H_DRDY# 7 R157
H_A#9 A8# DRDY# 56R2J-4-GP
T2 A9# DBSY# J1 H_DBSY# 7
H_A#10 AC5
H_A#11 A10#
CONTROL
AD2 A11# BR0# M2 H_BREQ#0 7
2
H_A#12 AD4
H_A#13 A12# H_IERR#
AA5 A13# IERR# B40
H_A#14 AE5 D8 H_INIT# 13
H_A#15 A14# INIT#
AB2 A15#
H_A#16 AC1 N1 H_LOCK# 7
A16# LOCK#
7 H_ADSTB#0 Y4 ADSTB0# H_CPURST# 7
G5 CPU1B 2 OF 6
7 H_REQ#[4..0] RESET# H_RS#[2..0] 7
H_REQ#0 R1 K2 H_RS#0 H_D#0 F40 AP44 H_D#32
H_REQ#1 REQ0# RS0# H_RS#1 H_D#1 G43 D0# D32# H_D#33
R5 REQ1# RS1# H4 D1# D33# AR43
H_REQ#2 U1 K4 H_RS#2 H_D#2 E43 AH40 H_D#34
H_REQ#3 REQ2# RS2# H_D#3 J43 D2# D34# H_D#35
P4 REQ3# TRDY# L1 H_TRDY# 7 D3# D35# AF40
H_REQ#4 H_D#4 H40 H_D#36
DATA GROUP 0
W5 REQ4# D4# D36# AJ43
H2 H_HIT# 7 H_THERMDA H_D#5 H44 AG41 H_D#37
H_A#17 HIT# H_D#6 G39 D5# D37# H_D#38
AN1 A17# HITM# F2 H_HITM# 7 D6# D38# AF44
1
H_A#18 AK4 H_D#7 E41 AH44 H_D#39
A18# D7# D39#
DATA GROUP 2
H_A#19 AG1 AY8 C307 H_D#8 L41 AM44 H_D#40
H_A#20 A19# BPM0# SC2200P50V2KX-2GP H_D#9 K44 D8# D40# H_D#41
AT4 BA7 AN43
ADDR GROUP 1
A20# BPM1# D9# D41#
2
H_A#21 AK2 BA5 H_THERMDC DY H_D#10 N41 AM40 H_D#42
H_A#22 A21# BPM2# H_D#11 T40 D10# D42# H_D#43
AT2 A22# BPM3# AY2 D11# D43# AK40
H_A#23 H_D#12 M40 H_D#44
AH2 AV10
Close to NB AG43
XDP/ITP SIGNALS
H_A#24 A23# PRDY# XDP_BPM#5 H_D#13 G41 D12# D44# H_D#45

AF4 A24# PREQ# AV2 D13# D45# AP40
H_A#25 AJ5 AV4 XDP_TCK H_D#14 M44 AN41 H_D#46
3 H_A#26 A25# TCK XDP_TDI 1D05V_S0 H_D#15 L43 D14# D46# H_D#47 3
AH4 A26# TDI AW7 D15# D47# AL41
H_A#27 AM4 AU1 XDP_TDO K40 AK44 H_DSTBN#2 7
A27# TDO 7 H_DSTBN#0 DSTBN0# DSTBN2#
H_A#28 AP4 AW5 XDP_TMS J41 AL43 H_DSTBP#2 7
A28# TMS 7 H_DSTBP#0 DSTBP0# DSTBP2#
H_A#29 AR5 AV8 XDP_TRST# P40 AJ41 H_DINV#2 7
A29# TRST# 7 H_DINV#0 DINV0# DINV2#
1
H_A#30 AJ1 J7 XDP_DBRESET#
H_A#31 A30# DBR# R160
AL1 A31#
H_A#32 AM2 56R2J-4-GP H_D#16 P44 AV38 H_D#48
H_A#33 A32# H_D#17 D16# D48# H_D#49
AU5 A33# THERMAL V40 D17# D49# AT44
H_A#34 AP2 H_D#18 V44 AV40 H_D#50
A34# D18# D50#
2
H_A#35 AR1 D38 CPU_PROCHOT#_1 H_D#19 AB44 AU41 H_D#51
A35# PROCHOT# H_D#20 D19# D51# H_D#52
7 H_ADSTB#1 AN5 ADSTB1# THRMDA BB34 H_THERMDA 27 R41 D20# D52# AW41
H_D#21 H_D#53
DATA GROUP 1
THRMDC BD34 H_THERMDC 27 W41 D21# D53# AR41
13 H_A20M# C7 H_D#22 N43 BA37 H_D#54
A20M# H_D#23 D22# D54# H_D#55
13 H_FERR# D4 FERR# THERMTRIP# B10 PM_THRMTRIP-A# 8,13,32 U41 D23# D55# BB38
DATA GROUP 3
H_D#24 H_D#56
ICH
13 H_IGNNE# F10 IGNNE# AA41 D24# D56# AY36

PM_THRMTRIP# should connect to H_D#25 AB40 AT40 H_D#57
ICH9 and MCH without T-ing H_D#26 D25# D57# H_D#58
13 H_STPCLK# F8 STPCLK# AD40 D26# D58# BC35
C9 H CLK PH @ page48 H_D#27 AC41 BC39 H_D#59
13 H_INTR LINT0 D27# D59#
13 H_NMI C5 A35 CLK_CPU_BCLK 3 H_D#28 AA43 BA41 H_D#60
LINT1 BCLK0 H_D#29 D28# D60# H_D#61
13 H_SMI# E5 SMI# BCLK1 C35 CLK_CPU_BCLK# 3 Y40 D29# D61# BB40
1D05V_S0 H_D#30 Y44 BA35 H_D#62
H_D#31 D30# D62# H_D#63
V2 RSVD#V2 T44 D31# D63# AU43
2
RESERVED
Y2 RSVD#Y2 7 H_DSTBN#1 U43 DSTBN1# DSTBN3# AY40 H_DSTBN#3 7

AG5 RSVD#AG5 7 H_DSTBP#1 W43 DSTBP1# DSTBP3# AY38 H_DSTBP#3 7
AL5 Layout Note: 1KR2F-3-GP R43 BC37
RSVD#AL5 7 H_DINV#1 DINV1# DINV3# H_DINV#3 7
J9 "CPU_GTLREF0" R133
RSVD#J9 0.5" max length. CPU_GTLREF0
F4 RSVD#F4 AW43 GTLREF COMP0 AE43 COMP0 R1391 2 27D4R2F-L1-GP
1 1
H8 C311 TEST1 E37 MISC AD44 COMP1 R1411 2 54D9R2F-L1-GP
RSVD#H8 TEST1 COMP1
1
DY TPAD14-GP TEST2 AE1 COMP2 R1431 27D4R2F-L1-GP
SC1KP50V2KX-1GP
D40 TEST2 COMP2 2
2 R134 TP42 RSVD_CPU_12 2
1 C43 TEST3 COMP3 AF2 COMP3 R1421 2 54D9R2F-L1-GP
2KR2F-3-GP TEST4 AE41 TEST4
2
TPAD14-GP TP2 1RSVD_CPU_13AY10 G7 H_DPRSTP# 8,13,34
TPAD14-GP TP31 TEST5 DPRSTP#
1RSVD_CPU_14
AC43 TEST6 DPSLP# B8 H_DPSLP# 13
2
DPWR# C41 H_DPWR# 7
PENRYN-SFF-GP-U1-NF 3,8 CPU_SEL0 A37 E7 H_PWRGD 13,32
BSEL0 PWRGOOD
3,8 CPU_SEL1 C37 BSEL1 SLP# D10 H_CPUSLP# 7
3,8 CPU_SEL2 B38 BD10 PSI# 1
BSEL2 PSI# TP3 TPAD14-GP
1
PENRYN-SFF-GP-U1-NF C118
SC100P50V2JN-3GP
DY
2
Layout Note:
1D05V_S0 1 DY 2 TEST1 Comp0, 2 connect with Zo=27.4 ohm, make
R162 1KR2J-1-GP trace length shorter than 0.5" .
Net "TEST4" as short as possible, Comp1, 3 connect with Zo=55 ohm, make
H_FERR# 1 2 1 DY 2 TEST2 trace length shorter than 0.5" .
H_STPCLK# C329 1DY 2 SC100P50V2JN-3GP XDP_TMS R119 1 2 51R2F-2-GP R153 1KR2J-1-GP make sure "TEST4" routing is
C314
H_IGNNE# C113 1DY 2 SC100P50V2JN-3GP reference to GND and away other
H_INTR C323 1DY 2 SC100P50V2JN-3GP XDP_TDI R120 1 2 51R2F-2-GP 2DY 1 TEST4
H_DPSLP# C327 1DY 2 SC100P50V2JN-3GP SCD1U10V2KX-4GP noisy signals
H_PWRGD C324 1DY 2 SC100P50V2JN-3GP XDP_BPM#5 R122 1 2 51R2F-2-GP
H_A20M# C92 1DY 2 SC100P50V2JN-3GP
H_SMI# C322 1DY 2 SC100P50V2JN-3GP XDP_TDO R121 1 2 51R2F-2-GP
H_NMI C317 1DY 2 SC100P50V2JN-3GP DY
H_INIT# C318 1DY 2 SC100P50V2JN-3GP
C316 SC100P50V2JN-3GP
1
DY
SB_20090205 3D3V_S0 H_DPRSTP#
H_DPSLP#
1 TP10
TP46
TPAD14-GP
TPAD14-GP
<Core Design> 1
1
H_DPWR# 1 TP41 TPAD14-GP
Wistron Corporation
Dr-Bios.com
XDP_DBRESET# R39 1 2 1KR2J-1-GP H_PWRGD 1 TP13 TPAD14-GP
DY H_CPUSLP# 1 TP45 TPAD14-GP
H_INIT# 1 TP14 TPAD14-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
H_CPURST# 1 TP9 TPAD14-GP Taipei Hsien 221, Taiwan, R.O.C.
XDP_TCK R124 1 2 51R2F-2-GP
Place these TP on button-side, Title
XDP_TRST# R123 1 2 51R2F-2-GP
easy to measure. CPU (1 of 3)
All place within 2" to CPU Size Document Number Rev
JM41_UMA -1
A B C D E
A B C D E
VCC_CORE
VCC_CORE CPU1D 4 OF 6
4 B42 VSS VSS AU35 4
F44 VSS VSS AV34
CPU1C 3 OF 6 D42 AW35
VSS VSS
F32 VCC VCC AB28 F42 VSS VSS AW33
G33 VCC VCC AD30 H42 VSS VSS AY34
H32 VCC VCC AD28 K42 VSS VSS AT36
J33 VCC VCC Y26 M42 VSS VSS AV36
K32 VCC VCC AB26 P42 VSS VSS BA33
L33 VCC VCC AD26 T42 VSS VSS BC33
M32 VCC VCC AF30 V42 VSS VSS BB36
N33 VCC VCC AF28 Y42 VSS VSS BD36
P32 VCC VCC AH30 AB42 VSS VSS C27
R33 VCC VCC AH28 AD42 VSS VSS C29
T32 VCC VCC AF26 AF42 VSS VSS C31
U33 VCC VCC AH26 AH42 VSS VSS E29
V32 VCC VCC AK30 AK42 VSS VSS E27
W33 VCC VCC AK28 AM42 VSS VSS G29
Y32 VCC VCC AM30 AP42 VSS VSS G27
AA33 VCC VCC AM28 AV44 VSS VSS E31
AB32 VCC VCC AP30 AT42 VSS VSS G31
AC33 VCC VCC AP28 AV42 VSS VSS J29
AD32 VCC VCC AK26 AY42 VSS VSS J27
AE33 VCC VCC AM26 BA43 VSS VSS L29
AF32 VCC VCC AP26 BB42 VSS VSS L27
AG33 VCC VCC AT30 C39 VSS VSS N29
AH32 VCC VCC AT28 E39 VSS VSS N27
AJ33 VCC VCC AV30 G37 VSS VSS J31
AK32 VCC VCC AV28 H38 VSS VSS L31
AL33 VCC VCC AY30 J39 VSS VSS N31
3 AM32 AY28 L39 R29 3
VCC VCC VSS VSS
AN33 VCC VCC AT26 M38 VSS VSS R27
AP32 VCC VCC AV26 N39 VSS VSS U29
AR33 VCC VCC AY26 R39 VSS VSS U27
AT34 VCC VCC BB30 T38 VSS VSS R31
AT32 VCC VCC BB28 U39 VSS VSS U31
AU33 BD30 1D05V_S0 W39 W29
VCC VCC VSS VSS
AV32 VCC Y38 VSS VSS W27
AY32 VCC VCCP J11 AA39 VSS VSS W31
BB32 VCC VCCP E11 AC39 VSS VSS AA29
BD32 VCC VCCP G11 AD38 VSS VSS AA27
B28 J37 2ND = 80.3371V.12L AE39 AC29
VCC VCCP 77.C3371.10L VSS VSS
B30 VCC VCCP K38 AG39 VSS VSS AC27
1
B26 L37 C35 C46 DY AH38 AA31

VCC VCCP VSS VSS
1
TC7
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
D28 VCC VCCP N37 AJ39 VSS VSS AC31

ST330U2D5VDM-13GP
D30 VCC VCCP P38 AL39 VSS VSS AE29

2
F30 VCC VCCP R37 AM38 VSS VSS AE27

2
F28 VCC VCCP U37 layout note: "1D5V_VCCA_S0" AN39 VSS VSS AG29
H30 VCC VCCP V38 as short as possible AR39 VSS VSS AG27
H28 VCC VCCP W37 AR37 VSS VSS AJ29
D26 VCC VCCP AA37 AT38 VSS VSS AJ27
F26 VCC VCCP AB38 AU39 VSS VSS AE31
H26 AC37 1D5V_S0 AU37 AG31
VCC VCCP 1D5V_VCCA_S0 VSS VSS
K30 VCC VCCP AE37 L10 AW39 VSS VSS AJ31
K28 VCC AW37 VSS VSS AL29
M30 VCC VCCA B34 1 2 BA39 VSS VSS AL27
M28 VCC VCCA D34 BC41 VSS VSS AN29
1
K26 H_VID[6..0] 34 C339 C347 BD38 AN27

VCC H_VID0 0R0805-PAD VSS VSS
SC10U6D3V5MX-3GP
SCD01U16V2KX-3GP
M26 VCC VID0 BD8 B36 VSS VSS AL31

2 H_VID1 2
P30 VCC VID1 BC7 H34 VSS VSS AN31
2
P28 BB10 H_VID2 D36 AR29

VCC VID2 H_VID3 VSS VSS
T30 VCC VID3 BB8 K34 VSS VSS AR27
T28 BC5 H_VID4 M34 AR31
VCC VID4 H_VID5 VSS VSS
V30 VCC VID5 BB4 M36 VSS VSS AU29
V28 AY4 H_VID6 P34 AU27
VCC VID6 VSS VSS
P26 VCC T34 VSS VSS AW29
T26 VCC V34 VSS VSS AW27
V26 VCC VCCSENSE BD12 VCORE_VCCSENSE 34 T36 VSS VSS AU31
Y30 VCC Y34 VSS VSS AW31
Y28 VCC AB34 VSS VSS BA29
AB30 VCC VSSSENSE BC13 VCORE_VSSSENSE 34 AD34 VSS VSS BA27
Y36 VSS VSS BC29
PENRYN-SFF-GP-U1-NF Layout Note: AD36 BC27
RN11 VSS VSS
AF34 VSS VSS BA31
2 3 VCCSENSE and VSSSENSE lines AH34 BC31
VCC_CORE VSS VSS
1 4 should be of equal length. AH36 C21
VSS VSS
AK34 VSS VSS C23
SRN100J-3-GP AM34 C25
Layout Note: VSS VSS
AM36 VSS VSS E25
Provide a test point (with AP34 E23
no stub) to connect a VSS VSS
AR35 VSS VSS E21
differential probe
between VCCSENSE and
VSSSENSE at the location PENRYN-SFF-GP-U1-NF
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.
1 1
Wistron Corporation
Dr-Bios.com
Title
CPU (2 of 3)
JM41_UMA -1
A B C D E
5 4 3 2 1
VCC_CORE 1D05V_S0
CPU1E 5 OF 6 6 OF 6
Place these inside socket CPU1F
cavity on L8(North side Secondary) G25 VSS VSS AD10 BD28 VCC VCCP AL37
G23 VSS VSS AH12 BB26 VCC VCCP AN37
G21 VSS VSS AE15 BD26 VCC VCCP AP38
VCC_CORE VCC_CORE J25 AG15 B22 B32
VSS VSS VCC VCCP
J23 VSS VSS AJ15 B24 VCC VCCP C33
J21 VSS VSS AH10 D22 VCC VCCP D32
D L25 VSS VSS AM12 D24 VCC VCCP E35 D
L23 VSS VSS AL15 F24 VCC VCCP E33
1
1
C298 C1 C5 C8 C297 C7 C25 C6 C17 C300 C31 C37 C45 C36 C28 C50 L21 AN15 F22 F34
VSS VSS VCC VCCP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
N25 VSS VSS AR15 H24 VCC VCCP G35
N23 VSS VSS AM10 H22 VCC VCCP F36
2
2
N21 VSS VSS AT12 K24 VCC VCCP H36
R25 VSS VSS AV12 K22 VCC VCCP J35
R23 VSS VSS AW13 M24 VCC VCCP L35
R21 VSS VSS AW11 M22 VCC VCCP N35
U25 VSS VSS AY12 P24 VCC VCCP K36
U23 VSS VSS AU15 P22 VCC VCCP R35
U21 VSS VSS AW15 T24 VCC VCCP U35
W25 VSS VSS AT10 T22 VCC VCCP P36
W23 VSS VSS BA13 V24 VCC VCCP V36
W21 VSS VSS BA11 V22 VCC VCCP W35
AA25 VSS VSS BB12 Y24 VCC VCCP AA35
VCC_CORE VCC_CORE AA23 BC11 Y22 AC35
VSS VSS VCC VCCP
AA21 VSS VSS BA15 AB24 VCC VCCP AB36
AC25 VSS VSS BC15 AB22 VCC VCCP AE35
AC23 VSS VSS B6 AD24 VCC VCCP AG35
AC21 VSS VSS D6 AD22 VCC VCCP AJ35
1
1
C58 C52 C41 C4 C26 C22 C23 C65 C42 C47 C3 C33 C301 C299 C39 C2 AE25 E9 AF24 AF36
VSS VSS VCC VCCP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
AE23 VSS VSS F6 AF22 VCC VCCP AL35
AE21 VSS VSS G9 AH24 VCC VCCP AN35
2
2
AG25 VSS VSS H6 AH22 VCC VCCP AK36
AG23 VSS VSS K8 AK24 VCC VCCP AP36
AG21 VSS VSS K6 AK22 VCC VCCP B12
AJ25 VSS VSS M8 AM24 VCC VCCP B14
AJ23 VSS VSS M6 AM22 VCC VCCP C13
AJ21 VSS VSS P8 AP24 VCC VCCP D12
AL25 VSS VSS P6 AP22 VCC VCCP D14
AL23 VSS VSS T8 AT24 VCC VCCP E13
AL21 VSS VSS T6 AT22 VCC VCCP F14
VCC_CORE VCC_CORE AN25 V8 AV24 F12
VSS VSS VCC VCCP
AN23 VSS VSS V6 AV22 VCC VCCP G13
AN21 VSS VSS U5 AY24 VCC VCCP H14
AR25 VSS VSS Y8 AY22 VCC VCCP H12
AR23 VSS VSS Y6 BB24 VCC VCCP J13
1
1
C76 C91 C84 C102 C105 C112 C101 C83 C64 C57 C53 C44 C40 C100 C103 C107 AR21 AB8 BB22 K14
VSS VSS VCC VCCP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
AU25 VSS VSS AB6 BD24 VCC VCCP K12
AU23 VSS VSS AD8 BD22 VCC VCCP L13
2
2
C AU21 VSS VSS AD6 B16 VCC VCCP L11 C
AW25 VSS VSS AF8 B18 VCC VCCP M14
AW23 VSS VSS AF6 B20 VCC VCCP N13
AW21 VSS VSS AH8 D16 VCC VCCP N11
BA25 VSS VSS AH6 D18 VCC VCCP K10
BA23 VSS VSS AK8 F18 VCC VCCP P14
BA21 VSS VSS AK6 F16 VCC VCCP P12
BC25 VSS VSS AM8 H18 VCC VCCP R13
BC23 VSS VSS AM6 H16 VCC VCCP R11
VCC_CORE VCC_CORE BC21 AP8 D20 T14
VSS VSS VCC VCCP
C17 VSS VSS AP6 F20 VCC VCCP U13
C19 VSS VSS AT8 H20 VCC VCCP U11
E19 VSS VSS AT6 K18 VCC VCCP V14
E17 VSS VSS AU9 K16 VCC VCCP V12
1
1
C80 C71 C66 C59 C73 C78 C69 C87 C75 C67 C116 C55 C51 C32 C115 C99 G19 AV6 M18 W13
VSS VSS VCC VCCP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
G17 VSS VSS AU7 M16 VCC VCCP W11
J19 VSS VSS AW9 K20 VCC VCCP P10
2
J17 VSS VSS AY6 M20 VCC VCCP V10

L19 VSS VSS BA9 P18 VCC VCCP Y14
L17 VSS VSS BB6 P16 VCC VCCP AA13
N19 VSS VSS BC9 T18 VCC VCCP AA11
N17 VSS VSS BD6 T16 VCC VCCP AB14
R19 VSS VSS B4 V18 VCC VCCP AB12
R17 VSS VSS C3 V16 VCC VCCP AC13
U19 VSS VSS E3 P20 VCC VCCP AC11
U17 VSS VSS G3 T20 VCC VCCP AD14
Place these inside socket W19 VSS VSS J3 V20 VCC VCCP AB10
cavity on L8(North side Secondary) W17 VSS VSS L3 Y18 VCC VCCP AE13
AA19 VSS VSS N3 Y16 VCC VCCP AE11
AA17 VSS VSS R3 AB18 VCC VCCP AF14
AC19 VSS VSS U3 AB16 VCC VCCP AF12
1D05V_S0 AC17 W3 AD18 AG13
VSS VSS VCC VCCP
AE19 VSS VSS AA3 AD16 VCC VCCP AG11
AE17 VSS VSS AC3 Y20 VCC VCCP AH14
AG19 VSS VSS AE3 AB20 VCC VCCP AJ13
AG17 VSS VSS AG3 AD20 VCC VCCP AJ11
AJ19 VSS VSS AJ3 AF18 VCC VCCP AF10
1
C82 C63 C114 C81 C49 C56 AJ17 AL3 AF16 AK14
VSS VSS VCC VCCP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
AL19 VSS VSS AN3 AH18 VCC VCCP AK12

AL17 VSS VSS AR3 AH16 VCC VCCP AL13
2
AN19 VSS VSS AU3 AF20 VCC VCCP AL11

B AN17 AW3 AH20 AN13 B
VSS VSS VCC VCCP
AR19 VSS VSS BA3 AK18 VCC VCCP AN11
AR17 VSS VSS BC3 AK16 VCC VCCP AP12
AU19 VSS VSS D2 AM18 VCC VCCP AR13
AU17 VSS VSS G1 AM16 VCC VCCP AR11
AW19 VSS VSS AW1 AP18 VCC VCCP AK10
AW17 VSS VSS BB2 AP16 VCC VCCP AP10
BA19 VSS VSS A39 AK20 VCC VCCP AU13
BA17 VSS VSS A29 AM20 VCC VCCP AU11
BC19 VSS VSS A27 AP20 VCC VCCP L9
BC17 VSS VSS A31 AT18 VCC VCCP L7
C11 VSS VSS A25 AT16 VCC VCCP N9
C15 VSS VSS A23 AV18 VCC VCCP N7
E15 VSS VSS A21 AV16 VCC VCCP R9
G15 VSS VSS A19 AY18 VCC VCCP R7
H10 VSS VSS A17 AY16 VCC VCCP U9
M12 VSS VSS A11 AT20 VCC VCCP U7
J15 VSS VSS A15 AV20 VCC VCCP W9
L15 VSS VSS A7 AY20 VCC VCCP W7
N15 VSS VSS A9 BB18 VCC VCCP AA9
M10 VSS BB16 VCC VCCP AA7
T12 VSS BD18 VCC VCCP AC9
R15 A5 NCTF_VSS#A5 1 TP62 TPAD14-GP BD16 AC7
VSS NCTF_VSS#A5 VCC VCCP
U15 VSS NCTF_VSS#A41 A41 NCTF_VSS#A41 1 TP63 TPAD14-GP BB20 VCC VCCP AE9
W15 VSS NCTF_VSS#AY44 AY44 NCTF_VSS#AY44 1 TP64 TPAD14-GP BD20 VCC VCCP AE7
T10 VSS NCTF_VSS#BA1 BA1 NCTF_VSS#BA1 1 TP65 TPAD14-GP AM14 VCC VCCP AG9
BD4 NCTF_VSS#BD4 TP66 TPAD14-GP
A5,A41,AY44,BA1,BD4,BD40,D44,E1
Y10 VSS NCTF_VSS#BD4 1 AP14 VCC VCCP AG7
Y12 VSS NCTF_VSS#BD40 BD40 NCTF_VSS#BD40 1 TP67 TPAD14-GP AT14 VCC VCCP AJ9
AA15 VSS NCTF_VSS#D44 D44 NCTF_VSS#D44 1 TP68 TPAD14-GP AV14 VCC VCCP AJ7
AC15 E1 NCTF_VSS#E1 1 TP69 TPAD14-GP AY14 AL9
VSS NCTF_VSS#E1 VCC VCCP
AD12 VSS BB14 VCC VCCP AL7
BD14 VCC VCCP AN9
1D05V_S0 AN7
PENRYN-SFF-GP-U1-NF VCCP
AF38 VCCP VCCP AR9
AG37 AR7
NCTF TEST PIN:

VCCP VCCP
AJ37 VCCP VCCP A33
AK38 VCCP VCCP A13
PENRYN-SFF-GP-U1-NF
A A
5
Dr-Bios.com 4 3 2
Title
Size Document Number
Date: Sunday, March 01, 2009

1
Wistron Corporation
CPU (3 of 3)
JM41_UMA
Sheet 6 of 40
Rev
-1
5 4 3 2 1
NB1A 1 OF 10 H_A#[35..3]
H_A#[35..3] 4
H_D#[63..0] L15 H_A#3
4 H_D#[63..0] H_A#_3
H_D#0 J7 B14 H_A#4
H_D#1 H_D#_0 H_A#_4 H_A#5
H6 H_D#_1 H_A#_5 C15
H_D#2 L11 D12 H_A#6
H_D#3 H_D#_2 H_A#_6 H_A#7
J3 H_D#_3 H_A#_7 F14
1D05V_S0 H_D#4 H4 G17 H_A#8
H_D#5 H_D#_4 H_A#_8 H_A#9
D H_SWING routing Trace width and G3 H_D#_5 H_A#_9 B12 D
H_D#6 K10 J15 H_A#10
Spacing use 10 / 20 mil H_D#_6 H_A#_10
1
H_D#7 K12 D16 H_A#11
R172 H_D#8 H_D#_7 H_A#_11 H_A#12
L1 H_D#_8 H_A#_12 C17
221R2F-2-GP H_D#9 M10 D14 H_A#13
H_D#10 H_D#_9 H_A#_13 H_A#14
H_SWING Resistors and M6 H_D#_10 H_A#_14 K16
H_D#11 N11 F16 H_A#15
Capacitors close MCH H_D#_11 H_A#_15
2
H_D#12 L7 B16 H_A#16
H_D#_12 H_A#_16
500 mil ( MAX ) H_SWING H_D#13 K6 H_D#_13 H_A#_17 C21 H_A#17
H_D#14 M4 D18 H_A#18
H_D#_14 H_A#_18
1
H_D#15 H_A#19
SCD1U10V2KX-4GP
K4 H_D#_15 H_A#_19 J19
1 R173 H_D#16 H_A#20
C385
P6 H_D#_16 H_A#_20 J21
100R2F-L1-GP-U H_D#17 W9 B18 H_A#21
H_D#18 H_D#_17 H_A#_21 H_A#22
V6 H_D#_18 H_A#_22 D22
2
H_D#19 V2 G19 H_A#23

H_D#_19 H_A#_23
2
H_D#20 P10 J17 H_A#24
H_D#21 H_D#_20 H_A#_24 H_A#25
W7 H_D#_21 H_A#_25 L21
H_D#22 N9 L19 H_A#26
H_D#23 H_D#_22 H_A#_26 H_A#27
P4 H_D#_23 H_A#_27 G21
H_D#24 U9 D20 H_A#28
H_D#25 H_D#_24 H_A#_28 H_A#29
V4 H_D#_25 H_A#_29 K22
H_D#26 U1 F18 H_A#30
H_D#27 H_D#_26 H_A#_30 H_A#31
W3 H_D#_27 H_A#_31 K20
H_D#28 V10 F20 H_A#32
H_D#29 H_D#_28 H_A#_32 H_A#33
U7 H_D#_29 H_A#_33 F22
H_D#30 W11 B20 H_A#34
H_D#31 H_D#_30 H_A#_34 H_A#35
U11 H_D#_31 H_A#_35 A19
H_D#32 AC11
H_D#33 H_D#_32
AC9 H_D#_33 H_ADS# F10 H_ADS# 4
C H_D#34 Y4 A15 H_ADSTB#0 4
C
HOST
H_D#35 H_D#_34 H_ADSTB#_0
Y10 H_D#_35 H_ADSTB#_1 C19 H_ADSTB#1 4
H_D#36 AB6 C9 H_BNR# 4
H_D#37 H_D#_36 H_BNR#
AA9 H_D#_37 H_BPRI# B8 H_BPRI# 4
H_D#38 AB10 C11 H_BREQ#0 4
H_D#39 H_D#_38 H_BREQ#
AA1 H_D#_39 H_DEFER# E5 H_DEFER# 4
H_D#40 AC3 D6 H_DBSY# 4
H_D#41 H_D#_40 H_DBSY#
AC7 H_D#_41 HPLL_CLK AH10 CLK_MCH_BCLK 3
H_D#42 AD12 AJ11 CLK_MCH_BCLK# 3
H_D#43 H_D#_42 HPLL_CLK#
AB4 H_D#_43 H_DPWR# G11 H_DPWR# 4
H_D#44 Y6 H2 H_DRDY# 4
H_D#45 H_D#_44 H_DRDY#
H_RCOMP routing Trace width and AD10 H_D#_45 H_HIT# C7 H_HIT# 4
H_D#46 AA11 F8 H_HITM# 4
Spacing use 10 / 20 mil H_D#47 AB2
H_D#_46 H_HITM#
A11 H_LOCK# 4
H_D#48 H_D#_47 H_LOCK#
AD4 H_D#_48 H_TRDY# D8 H_TRDY# 4
H_D#49 AE7 H_D#_49
1 2 H_RCOMP H_D#50 AD2 H_D#_50
R170 24D9R2F-L-GP H_D#51 AD6
H_D#52 H_D#_51 H_DINV#[3..0]
AE3 H_D#_52 H_DINV#[3..0] 4
H_D#53 AG9 L9 H_DINV#0
H_D#54 H_D#_53 H_DINV#_0 H_DINV#1
AG7 H_D#_54 H_DINV#_1 N7
H_D#55 AE11 AA7 H_DINV#2
H_D#56 H_D#_55 H_DINV#_2 H_DINV#3
Place them near to the chip ( < 0.5") H_D#57
AK6
AF6
H_D#_56 H_DINV#_3 AG3
H_DSTBN#[3..0]
H_D#_57 H_DSTBN#[3..0] 4
H_D#58 AJ9 K2 H_DSTBN#0
H_D#59 H_D#_58 H_DSTBN_0 H_DSTBN#1
AH6 H_D#_59 H_DSTBN_1 N3
H_D#60 AF12 AA3 H_DSTBN#2
H_D#61 H_D#_60 H_DSTBN_2 H_DSTBN#3
AH4 H_D#_61 H_DSTBN_3 AF4
H_D#62 AJ7 H_DSTBP#[3..0]
B H_D#_62 H_DSTBP#[3..0] 4 B
H_D#63 AE9 L3 H_DSTBP#0
H_D#_63 H_DSTBP_0 H_DSTBP#1
H_DSTBP_1 M2
Y2 H_DSTBP#2
H_SWING H_DSTBP_2 H_DSTBP#3
B6 H_SWING H_DSTBP_3 AF2
H_RCOMP D4 H_REQ#[4..0] 4
H_RCOMP H_REQ#0
H_REQ#_0 J13
1D05V_S0 L13 H_REQ#1
H_REQ#_1 H_REQ#2
H_REQ#_2 C13
G13 H_REQ#3
H_REQ#_3
2
4 H_CPURST# J11 G15 H_REQ#4

R58 H_CPURST# H_REQ#_4
4 H_CPUSLP# G9 H_CPUSLP# H_RS#[2..0] 4
1KR2F-3-GP F4 H_RS#0
H_RS#_0 H_RS#1
H_RS#_1 F2
G7 H_RS#2
H_RS#_2
1
H_AVREF L17 H_AVREF

K18 H_DVREF
CANTIGA-GS-GP-NF
1
1
SC1KP50V2KX-1GP
R59 C177
2KR2F-3-GP
2
2
A <Core Design> A
Wistron Corporation
Dr-Bios.com
Title
Cantiga (1 of 6)
JM41_UMA -1
5 4 3 2 1
5 4 3 2 1
NB1C 3 OF 10
NB1B 2 OF 10
1D05V_S0
J43 RSVD#J43
L43
J41
RSVD#L43
RSVD#J41
SA_CK_0
SA_CK_1
BB32
BA25
M_CLK_DDR0 17
M_CLK_DDR1 17
19
28
L_BKLTCTL
GMCH_BL_ON
D38
C37
L_BKLT_CTRL
L_BKLT_EN PEG_COMPI U45 PEG_CMP 2 1
Close to GMCH as 500 mils.
L41 BA33 M_CLK_DDR2 18 LCTLA_CLK K38 T44 R70 49D9R2F-GP
RSVD#L41 SB_CK_0 L_CTRL_CLK PEG_COMPO
AN11 BA23
DDR CLK/ CONTROL/COMPENSATION

RSVD#AN11 SB_CK_1 M_CLK_DDR3 18
AM10 LCTLB_DATA L37
RSVD#AM10 CLK_DDC_EDID L_CTRL_DATA
AK10 RSVD#AK10 SA_CK#_0 BA31 M_CLK_DDR#0 17 19 CLK_DDC_EDID J37 L_DDC_CLK PEG_RX#_0 D52
AL11 BC25 M_CLK_DDR#1 17 19 DAT_DDC_EDID DAT_DDC_EDID L35 G49
RSVD#AL11 SA_CK#_1 L_DDC_DATA PEG_RX#_1
F12 RSVD#F12 SB_CK#_0 BC33 M_CLK_DDR#2 18 PEG_RX#_2 K54
RSVD
AN45 RSVD#AN45 SB_CK#_1 BB24 M_CLK_DDR#3 18 PEG_RX#_3 H50
AP44 19 GMCH_LCDVDD_ON GMCH_LCDVDD_ON B36 M52
RSVD#AP44 LIBG L_VDD_EN PEG_RX#_4
AT44 RSVD#AT44 SA_CKE_0 BC35 M_CKE0 17 F50 LVDS_IBG PEG_RX#_5 N49
AN47 RSVD#AN47 SA_CKE_1 BE33 M_CKE1 17 TPAD14-GP TP27 1 L_LVBG H46 LVDS_VBG PEG_RX#_6 P54
C27 RSVD#C27 SB_CKE_0 BE37 M_CKE2 18 P44 LVDS_VREFH PEG_RX#_7 V46
LVDS
D D30 RSVD#D30 SB_CKE_1 BC37 M_CKE3 18 K46 LVDS_VREFL PEG_RX#_8 Y50 D
19 GMCH_TXACLK- D46 LVDSA_CLK# PEG_RX#_9 V52
J9 RSVD#J9 SA_CS#_0 BK18 M_CS0# 17 19 GMCH_TXACLK+ B46 LVDSA_CLK PEG_RX#_10 W49
SA_CS#_1 BK16 M_CS1# 17 D44 LVDSB_CLK# PEG_RX#_11 AB54
SB_CS#_0 BE23 M_CS2# 18 B44 LVDSB_CLK PEG_RX#_12 AD46
AW42 RSVD#AW42 SB_CS#_1 BC19 M_CS3# 18 PEG_RX#_13 AC55
19 GMCH_TXAOUT0- G45 LVDSA_DATA#_0 PEG_RX#_14 AE49
SA_ODT_0 BJ17 M_ODT0 17 19 GMCH_TXAOUT1- F46 LVDSA_DATA#_1 PEG_RX#_15 AF54
GRAPHICS
SA_ODT_1 BJ19 M_ODT1 17 19 GMCH_TXAOUT2- G41 LVDSA_DATA#_2
BB20 RSVD#BB20 SB_ODT_0 BC17 M_ODT2 18 C45 LVDSA_DATA#_3 PEG_RX_0 E51
BE19 RSVD#BE19 SB_ODT_1 BE17 M_ODT3 18 PEG_RX_1 F48
BF20 RSVD#BF20 19 GMCH_TXAOUT0+ F44 LVDSA_DATA_0 PEG_RX_2 J55
BF18 BL25 M_RCOMPP 19 GMCH_TXAOUT1+ G47 J49 PEG_RXP3 1 R72 2
RSVD#BF18 SM_RCOMP M_RCOMPN LVDSA_DATA_1 PEG_RX_3 0R0402-PAD HDMI_DETECT# 20
SM_RCOMP# BK26 SM_PWROK 32 19 GMCH_TXAOUT2+ F40 LVDSA_DATA_2 PEG_RX_4 M54
A45 LVDSA_DATA_3 PEG_RX_5 M50
BK32 SM_RCOMP_VOH P52
SM_RCOMP_VOH SM_RCOMP_VOL DDR_VREF_S3_1 PEG_RX_6
SM_RCOMP_VOL BL31 B40 LVDSB_DATA#_0 PEG_RX_7 U47
0.75V A41 LVDSB_DATA#_1 PEG_RX_8 AA49
SM_VREF BC51 F42 LVDSB_DATA#_2 PEG_RX_9 V54
AY37 DDR2 : connect to GND D48 V50
SM_PWROK SM_REXT R1801 499R2F-2-GP LVDSB_DATA#_3 PEG_RX_10
SM_REXT BH20 2 PEG_RX_11 AB52
1
BA37 DDR3_DRAMRST# 17,18 C241 D40 AC47
SM_DRAMRST# LVDSB_DATA_0 PEG_RX_12
SCD1U10V2KX-4GP
C41 AC53
PCI-EXPRESS
LVDSB_DATA_1 PEG_RX_13
DPLL_REF_CLK B42 DREFCLK 3 G43 LVDSB_DATA_2 PEG_RX_14 AD50
2
DPLL_REF_CLK# D42 DREFCLK# 3 B48 LVDSB_DATA_3 PEG_RX_15 AF52
DPLL_REF_SSCLK B50 DREFSSCLK 3
DPLL_REF_SSCLK# D50 DREFSSCLK# 3 PEG_TX#_0 L47 GTXN0 1 2 C235 SCD1U10V2KX-5GP HDMI_DATA2- 20
PEG_TX#_1 F52 GTXN1 1 2 C243 SCD1U10V2KX-5GP HDMI_DATA1- 20
R49 CLK_MCH_3GPLL 3 TV_DACA J27 P46 GTXN2 1 2 C237 SCD1U10V2KX-5GP HDMI_DATA0- 20
PEG_CLK TV_DACB TVA_DAC PEG_TX#_2
PEG_CLK# P50 CLK_MCH_3GPLL# 3 E27 TVB_DAC PEG_TX#_3 H54 GTXN3 1 2 C248 SCD1U10V2KX-5GP HDMI_CLK- 20
TV_DACC
TV
G27 TVC_DAC PEG_TX#_4 L55
PEG_TX#_5 T46
F26 R53
CLK
TVA_RTN PEG_TX#_6
DMI_RXN_0 AG55 DMI_TXN0 14 PEG_TX#_7 U49
DMI_RXN_1 AL49 DMI_TXN1 14 PEG_TX#_8 T54
SB_20090205 DMI_RXN_2
DMI_RXN_3
AH54
AL47
DMI_TXN2
DMI_TXN3
14
14 3D3V_S0
B34 TV_DCONSEL_0
PEG_TX#_9
PEG_TX#_10
Y46
AB46
D34 TV_DCONSEL_1 PEG_TX#_11 W53
DMI_RXP_0 AG53 DMI_TXP0 14 PEG_TX#_12 Y54
3,4 CPU_SEL0 K26 CFG_0 DMI_RXP_1 AK50 DMI_TXP1 14 PEG_TX#_13 AC49
3,4 CPU_SEL1 G23 CFG_1 DMI_RXP_2 AH52 DMI_TXP2 14 PEG_TX#_14 AF46
C 3,4 CPU_SEL2 G25 CFG_2 DMI_RXP_3 AL45 DMI_TXP3 14 PEG_TX#_15 AD54 C
J25 CFG_3
L25 AG49 20 GMCH_BLUE GMCH_BLUE J29 J47 GTXP0 1 2 C234 SCD1U10V2KX-5GP HDMI_DATA2+ 20
CFG_4 DMI_TXN_0 DMI_RXN0 14 CRT_BLUE PEG_TX_0
4
3
L27 CFG_5 DMI_TXN_1 AJ49 DMI_RXN1 14 PEG_TX_1 F54 GTXP1 1 2 C245 SCD1U10V2KX-5GP HDMI_DATA1+ 20
F24 AJ47 RN24 20 GMCH_GREEN GMCH_GREEN G29 N47 GTXP2 1 2 C236 SCD1U10V2KX-5GP HDMI_DATA0+ 20
1D5V_S3 CFG_6 DMI_TXN_2 DMI_RXN2 14 CRT_GREEN PEG_TX_2
D24 CFG_7 DMI_TXN_3 AG47 DMI_RXN3 14 SRN2K2J-1-GP PEG_TX_3 H52 GTXP3 1 2 C247 SCD1U10V2KX-5GP HDMI_CLK+ 20
GMCH_RED
VGA
D26 CFG_8 20 GMCH_RED F30 CRT_RED PEG_TX_4 L53
CFG9
CFG
J23 CFG_9 DMI_TXP_0 AF50 DMI_RXP0 14 PEG_TX_5 R47
B26 CFG_10 DMI_TXP_1 AH50 DMI_RXP1 14 E29 CRT_IRTN PEG_TX_6 R55
1
2
1
A23 CFG_11 DMI_TXP_2 AJ45 DMI_RXP2 14 PEG_TX_7 T50

R187 GMCH_DDCCLK
GRAPHICS VID DMI

C23 CFG_12 DMI_TXP_3 AG45 DMI_RXP3 14 20 GMCH_DDCCLK D36 CRT_DDC_CLK PEG_TX_8 T52
80D6R2F-L-GP B24 20 GMCH_DDCDATA GMCH_DDCDATA C35 W47
CFG_13 GMCH_HSYNC_C CRT_DDC_DATA PEG_TX_9
B22 CFG_14 J33 CRT_HSYNC PEG_TX_10 AA47
K24 CFG_15 20 GMCH_HSYNC 1 4 D32 CRT_TVO_IREF PEG_TX_11 W55
2
M_RCOMPP TPAD14-GP TP52 1 CFG16 C25 20 GMCH_VSYNC 2 3 GMCH_VSYNC_C G31 Y52

CFG_16 CRT_VSYNC PEG_TX_12
L23 CFG_17 PEG_TX_13 AB50
L33 RN8 AE47
M_RCOMPN CFG_18 SRN33J-5-GP-U PEG_TX_14
K32 CFG_19 PEG_TX_15 AD52
3D3V_S0 CFG20 K34 G33 GFX_VID0
CFG_20 GFX_VID_0
1
G37 GFX_VID1 1 2 CRT_IREF

R190 GFX_VID_1 GFX_VID2 R188 976R2F-3-GP CANTIGA-GS-GP-NF
GFX_VID_2 F38
80D6R2F-L-GP F36 GFX_VID3
GFX_VID_3 GFX_VID4
14 PM_SYNC# J35 PM_SYNC# GFX_VID_4 G35 GFX_VID[4..0] 38
4,13,34 H_DPRSTP# F6 PM_DPRSTP#
2
R67 1 DY 2 4K02R2F-GP CFG20 17,18 PM_EXTTS#0 PM_EXTTS#0 J39 PM_EXT_TS#_0

FOR Cantiga: 1.02k_1% ohm
PM_EXTTS#1
PM
L39 PM_EXT_TS#_1 Teenah: 1.3k ohm

AY39 G39 GFXVR_EN
14,32 PWROK PWROK GFX_VR_EN GFXVR_EN 38
R57
PLT_RST1#_Cantiga BB18 RSTIN#
1D05V_S0 CRT_IREF routing Trace
R60 1 DY 2 2K21R2F-GP CFG9 PM_THRMTRIP-A#_R K28 THERMTRIP# width use 20 mil
2
14,24,25,28,29 PLT_RST1# 2 1 K36 DPRSLPVR
150R2J-L1-GP-U R210
AK52 1KR2F-3-GP
CL_CLK CL_CLK0 14
1
C175 AK54
CL_DATA CL_DATA0 14
SB_20090205 SC100P50V2JN-3GP A7 NC#A7 CL_PWROK AW40 PWROK 14,32
1
DY A49 AL53
ME
NC#A49 CL_RST# CL_RST#0 14

2
A52 AL55 MCH_CLVREF 3D3V_S0

NC#A52 CL_VREF
A54 NC#A54 Cantiga RN25
1
B54 GMCH_LCDVDD_ON 1 4
NC#B54
1
4,13,32 PM_THRMTRIP-A# 1 R186 2 D55 NC#D55 for HDMI port C C422 R211 GMCH_BL_ON 2 3
4
3
0R0402-PAD 511R2F-2-GP
SCD1U10V2KX-4GP
G55 NC#G55 DDPC_CTRLCLK F34
NC
14,34 PM_DPRSLPVR BE55 F32 RN26 SRN100KJ-6-GP

NC#BE55 DDPC_CTRLDATA
2
B BH55 B38 SRN1K5J-GP B
NC#BH55 SDVO_CTRLCLK GMCH_HDMI_CLK 20
2
BK55 A37
MISC
NC#BK55 SDVO_CTRLDATA GMCH_HDMI_DATA 20

BK54 C31 CLK_MCH_OE# 3 LIBG 1 2
NC#BK54 CLKREQ# R199 2K4R2F-GP
BL54 NC#BL54 ICH_SYNC# K42 MCH_ICH_SYNC# 14
1
2
BL52 NC#BL52
FOR Cantiga:500 ohm
BL49 NC#BL49 Teenah: 392 ohm
BL7 D10 MCH_TSATN# GMCH_HDMI_DATA
NC#BL7 TSATN# GMCH_HDMI_CLK
BL4 NC#BL4
BL2 NC#BL2
BK2 NC#BK2
BK1 NC#BK1
BH1 NC#BH1
BE1 NC#BE1
G1 NC#G1 HDA_BCLK C29 HDA_BCLK_NB 13 SRN150F-1-GP
B30 RN20
HDA_RST# HDA_SDI HDA_RST#_NB 13 GMCH_BLUE
HDA_SDI D28 1 2 33R2J-2-GP ACZ_SDIN3 13 1 8
A27 R185 GMCH_GREEN 2 7
HDA_SDO HDA_SDO_NB 13 GMCH_RED
HDA_SYNC B28 HDA_SYNC_NB 13 3 6
4 5
HDA
DIS = 66.R0036.A8L
CANTIGA-GS-GP-NF
1D05V_S0 1D5V_S3
R196 1KR2F-3-GP
2 1 FOR Discrete change RN to 0 ohm
1
(66.R0036.A8L)
R179 SM_RCOMP_VOH
56R2J-4-GP
1
C402 C403
R194
2
3D3V_S0 MCH_TSATN# 3K01R2F-3-GP SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP SRN150F-1-GP

2
RN18
SRN10KJ-5-GP 1 8 TV_DACC
2
PM_EXTTS#0 3 2 SM_RCOMP_VOL 2 7 TV_DACB

PM_EXTTS#1 4 1 3 6
2
C399 C398 4 5 TV_DACA

RN27 R193
1KR2F-3-GP SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP
2
A 3D3V_S0 DIS = 66.R0036.A8L A

FOR Discrete,change to 0 ohm
1
RN7 (66.R0036.A8L)
LCTLA_CLK 4 1
LCTLB_DATA 3 2
Dr-Bios.com
SRN10KJ-5-GP layout take note
Wistron Corporation
Title
Cantiga (2 of 6)
JM41_UMA -1
5 4 3 2 1
5 4 3 2 1
M_A_DQ[63..0] NB1D 4 OF 10 M_B_DQ[63..0] NB1E 5 OF 10

17 M_A_DQ[63..0] 18 M_B_DQ[63..0]
M_A_DQ0 AP46 BC21 M_A_BS#0 17 M_B_DQ0 AP54 BJ13 M_B_BS#0 18
M_A_DQ1 SA_DQ_0 SA_BS_0 M_B_DQ1 SB_DQ_0 SB_BS_0
AU47 SA_DQ_1 SA_BS_1 BJ21 M_A_BS#1 17 AM52 SB_DQ_1 SB_BS_1 BK12 M_B_BS#1 18
M_A_DQ2 AT46 BJ41 M_A_BS#2 17 M_B_DQ2 AR55 BK38 M_B_BS#2 18
M_A_DQ3 SA_DQ_2 SA_BS_2 M_B_DQ3 SB_DQ_2 SB_BS_2
AU49 SA_DQ_3 AV54 SB_DQ_3
M_A_DQ4 AR45 BH22 M_A_RAS# 17 M_B_DQ4 AM54
M_A_DQ5 SA_DQ_4 SA_RAS# M_B_DQ5 SB_DQ_4
AN49 SA_DQ_5 SA_CAS# BK20 M_A_CAS# 17 AN53 SB_DQ_5 SB_RAS# BE21 M_B_RAS# 18
M_A_DQ6 AV50 BL15 M_A_WE# 17 M_B_DQ6 AT52 BH14 M_B_CAS# 18
M_A_DQ7 SA_DQ_6 SA_WE# M_B_DQ7 SB_DQ_6 SB_CAS#
AP50 SA_DQ_7 AU53 SB_DQ_7 SB_WE# BK14 M_B_WE# 18
D M_A_DQ8 AW47 M_B_DQ8 AW53 D
M_A_DQ9 SA_DQ_8 M_B_DQ9 SB_DQ_8
BD50 SA_DQ_9 AY52 SB_DQ_9
M_A_DQ10 AW49 M_A_DM[7..0] M_B_DQ10 BB52
SA_DQ_10 M_A_DM[7..0] 17 SB_DQ_10
M_A_DQ11 BA49 AT50 M_A_DM0 M_B_DQ11 BC53 M_B_DM[7..0]
SA_DQ_11 SA_DM_0 SB_DQ_11 M_B_DM[7..0] 18
M_A_DQ12 BC49 BB50 M_A_DM1 M_B_DQ12 AV52 AP52 M_B_DM0
M_A_DQ13 SA_DQ_12 SA_DM_1 M_A_DM2 M_B_DQ13 SB_DQ_12 SB_DM_0 M_B_DM1
AV46 SA_DQ_13 SA_DM_2 BB46 AW55 SB_DQ_13 SB_DM_1 AY54
M_A_DQ14 BA47 BE39 M_A_DM3 M_B_DQ14 BD52 BJ49 M_B_DM2
AY50 SA_DQ_15 SA_DM_4 BB12 BC55 SB_DQ_15 SB_DM_3 BJ43
A
M_A_DQ16 BF46 BE7 M_A_DM5 M_B_DQ16 BF54 BH12 M_B_DM4
BC47 SA_DQ_17 SA_DM_6 AV10 BE51 SB_DQ_17 SB_DM_5 BD2
M_A_DQ18 BF50 AR9 M_A_DM7 M_B_DQ18 BH48 AY2 M_B_DM6
B
M_A_DQ19 SA_DQ_18 SA_DM_7 M_A_DQS[7..0] M_B_DQ19 SB_DQ_18 SB_DM_6 M_B_DM7
BF48 SA_DQ_19 M_A_DQS[7..0] 17 BK48 SB_DQ_19 SB_DM_7 AJ3
M_A_DQ20 BC43 AR47 M_A_DQS0 M_B_DQ20 BE53 M_B_DQS[7..0]
SA_DQ_20 SA_DQS_0 SB_DQ_20 M_B_DQS[7..0] 18
MEMORY
M_A_DQ21 BE49 BA45 M_A_DQS1 M_B_DQ21 BH52 AR53 M_B_DQS0
M_A_DQ22 SA_DQ_21 SA_DQS_1 M_A_DQS2 M_B_DQ22 SB_DQ_21 SB_DQS_0 M_B_DQS1
BA43 SA_DQ_22 SA_DQS_2 BE45 BK46 SB_DQ_22 SB_DQS_1 BA53
M_A_DQ23 BE47 BC41 M_A_DQS3 M_B_DQ23 BJ47 BH50 M_B_DQS2
MEMORY
BF42 SA_DQ_24 SA_DQS_4 BC13 BL45 SB_DQ_24 SB_DQS_3 BK42
M_A_DQ25 BC39 BB10 M_A_DQS5 M_B_DQ25 BJ45 BH8 M_B_DQS4
BF44 SA_DQ_26 SA_DQS_6 BA7 BL41 SB_DQ_26 SB_DQS_5 BB2
M_A_DQ27 BF40 AN7 M_A_DQS7 M_B_DQ27 BH44 AV2 M_B_DQS6
M_A_DQ28 SA_DQ_27 SA_DQS_7 M_A_DQS#[7..0] M_B_DQ28 SB_DQ_27 SB_DQS_6 M_B_DQS7
BB40 SA_DQ_28 M_A_DQS#[7..0] 17 BH46 SB_DQ_28 SB_DQS_7 AM2
M_A_DQ29 BE43 AR49 M_A_DQS#0 M_B_DQ29 BK44 M_B_DQS#[7..0]
SA_DQ_29 SA_DQS#_0 SB_DQ_29 M_B_DQS#[7..0] 18
M_A_DQ30 BF38 AW45 M_A_DQS#1 M_B_DQ30 BK40 AT54 M_B_DQS#0
M_A_DQ31 SA_DQ_30 SA_DQS#_1 M_A_DQS#2 M_B_DQ31 SB_DQ_30 SB_DQS#_0 M_B_DQS#1
BE41 SA_DQ_31 SA_DQS#_2 BC45 BJ39 SB_DQ_31 SB_DQS#_1 BB54
M_A_DQ32 BA15 BA41 M_A_DQS#3 M_B_DQ32 BK10 BJ51 M_B_DQS#2
BE11 SA_DQ_33 SYSTEM SA_DQS#_4 BA13 BH10 SB_DQ_33 SB_DQS#_3 BH42
M_A_DQ34 BE15 BA11 M_A_DQS#5 M_B_DQ34 BK6 BK8 M_B_DQS#4
BF14 SA_DQ_35 SA_DQS#_6 BA9 BH6 SB_DQ_35 SB_DQS#_5 BC3
M_A_DQ36 BB14 AN9 M_A_DQS#7 M_B_DQ36 BJ9 AW3 M_B_DQS#6
SYSTEM
C M_A_DQ37 SA_DQ_36 SA_DQS#_7 M_A_A[14..0] M_B_DQ37 SB_DQ_36 SB_DQS#_6 M_B_DQS#7 C
BC15 SA_DQ_37 M_A_A[14..0] 17 BL11 SB_DQ_37 SB_DQS#_7 AN3
M_A_DQ38 BE13 BC23 M_A_A0 M_B_DQ38 BG5 M_B_A[14..0]
SA_DQ_38 SA_MA_0 SB_DQ_38 M_B_A[14..0] 18
M_A_DQ39 BF16 BF22 M_A_A1 M_B_DQ39 BJ5 BJ15 M_B_A0
M_A_DQ40 SA_DQ_39 SA_MA_1 M_A_A2 M_B_DQ40 SB_DQ_39 SB_MA_0 M_B_A1
BF10 SA_DQ_40 SA_MA_2 BE31 BG3 SB_DQ_40 SB_MA_1 BJ33
M_A_DQ41 BC11 BC31 M_A_A3 M_B_DQ41 BF4 BH24 M_B_A2
BF8 SA_DQ_42 SA_MA_4 BH26 BD4 SB_DQ_42 SB_MA_3 BA17
M_A_DQ43 BG7 BJ35 M_A_A5 M_B_DQ43 BA3 BF36 M_B_A4
BC7 SA_DQ_44 SA_MA_6 BB34 BE5 SB_DQ_44 SB_MA_5 BH36
M_A_DQ45 BC9 BH32 M_A_A7 M_B_DQ45 BF2 BF34 M_B_A6
BD6 BB26 BB4 BK34
DDR

BF12 SA_DQ_47 SA_MA_9 BF32 AY4 SB_DQ_47 SB_MA_8 BJ37
M_A_DQ48 AV6 BA21 M_A_A10 M_B_DQ48 BA1 BH40 M_B_A9
DDR
BB6 SA_DQ_49 SA_MA_11 BG25 AP2 SB_DQ_49 SB_MA_10 BH16
M_A_DQ50 AW7 BH34 M_A_A12 M_B_DQ50 AU1 BK36 M_B_A11
AY6 SA_DQ_51 SA_MA_13 BH18 AT2 SB_DQ_51 SB_MA_12 BH38
M_A_DQ52 AT10 BE25 M_A_A14 M_B_DQ52 AT4 BJ11 M_B_A13
M_A_DQ53 SA_DQ_52 SA_MA_14 M_B_DQ53 SB_DQ_52 SB_MA_13 M_B_A14
AW11 SA_DQ_53 AV4 SB_DQ_53 SB_MA_14 BL37
M_A_DQ54 AU11 M_B_DQ54 AU3
AW9 SA_DQ_55 AR3 SB_DQ_55
M_A_DQ56 AR11 M_B_DQ56 AN1
AT6 SA_DQ_57 AP4 SB_DQ_57
M_A_DQ58 AP6 M_B_DQ58 AL3
AL7 SA_DQ_59 AJ1 SB_DQ_59
M_A_DQ60 AR7 M_B_DQ60 AK4
AT12 SA_DQ_61 AM4 SB_DQ_61
M_A_DQ62 AM6 M_B_DQ62 AH2
AU7 SA_DQ_63 AK2 SB_DQ_63
CANTIGA-GS-GP-NF CANTIGA-GS-GP-NF
B B
A A
Wistron Corporation
Dr-Bios.com
Title
Cantiga (3 of 6)
JM41_UMA -1
5 4 3 2 1
5 4 3 2 1
NB1G 7 OF 10
VCC_GFXCORE
1D5V_S3
6 OF 10
VCC_AXG_NCTF T32 -1_20090301 NB1F
BB36 VCC_SM VCC_AXG_NCTF U31

BE35 VCC_SM VCC_AXG_NCTF T31
1D05V_S0
AW34
AW32
VCC_SM VCC_AXG_NCTF R31
U29 VCC_GFXCORE 1D05V_S0 FOR VCC CORE
VCC_SM VCC_AXG_NCTF R268
BK30 VCC_SM VCC_AXG_NCTF T29 DY
BH30 VCC_SM VCC_AXG_NCTF R29 1 2 AT41 VCC
BF30 U28 0R3-0-U-GP AR41
VCC_SM VCC_AXG_NCTF VCC
BD30 VCC_SM VCC_AXG_NCTF U27 AN41 VCC
BB30 T27 C219 C223 C239 C213 C212 C218 C207 AJ41
VCC_SM VCC_AXG_NCTF R269 VCC
1
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SC22U6D3V5MX-2GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
AW30 VCC_SM VCC_AXG_NCTF R27 DY AH41 VCC
BL29 VCC_SM VCC_AXG_NCTF U25 1 2 AD41 VCC
BJ29 T25 0R3-0-U-GP AC41
2
BG29 VCC_SM VCC_AXG_NCTF R25 Y41 VCC
D BE29 VCC_SM VCC_AXG_NCTF U24 R270 W41 VCC D
BC29 VCC_SM VCC_AXG_NCTF U22 DY AT40 VCC
BA29 T22 1 2 AM40
POWER
VCC_SM VCC_AXG_NCTF 0R3-0-U-GP VCC
AY29 VCC_SM VCC_AXG_NCTF R22 AL40 VCC
BK28 VCC_SM VCC_AXG_NCTF U21
BH28 VCC_SM VCC_AXG_NCTF T21 Coupling CAP 370 mils from the Edge AJ40 VCC
VCC CORE
BF28 VCC_SM VCC_AXG_NCTF R21 AH40 VCC
BD28 VCC_SM VCC_AXG_NCTF AM19 AG40 VCC
BB28 VCC_SM VCC_AXG_NCTF AL19 AE40 VCC
BL27 VCC_SM VCC_AXG_NCTF AH19 AD40 VCC
BJ27 VCC_SM VCC_AXG_NCTF AG19 AC40 VCC
BG27 VCC_SM VCC_AXG_NCTF AE19 AA40 VCC
VCC SM
BE27 VCC_SM VCC_AXG_NCTF AD19 Y40 VCC
BC27 AC19 VCC_GFXCORE AN35
VCC GFX NCTF

BA27 VCC_SM VCC_AXG_NCTF W19 AM35 VCC
1
AY27 U19 C238 C211 AJ35
AW26 VCC_SM VCC_AXG_NCTF AM18 AH35 VCC
BF24 AL18 SCD1U10V2KX-4GP AD35
2
1
1
BL19 AJ18 C182 C199 C172 C176 C184 C178 C191 1 C186 C169 C171 BC1 C180 C181 AC35
1
SC10U6D3V5MX-3GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC1U10V3KX-3GP
SC10U6D3V5MX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
BB16 AH18 W35
SCD47U6D3V2KX-GP
VCC_SM VCC_AXG_NCTF 2 VCC
VCC_AXG_NCTF AG18 AM34 VCC
2
VCC_GFXCORE AE18 AL34
VCC_AXG_NCTF VCC
2
VCC_AXG_NCTF AD18 AJ34 VCC
VCC_AXG_NCTF AC18 AH34 VCC
W32 VCC_AXG VCC_AXG_NCTF AA18 Coupling CAP AG34 VCC
AG31 Y18 AE34 1D05V_S0
VCC_AXG VCC_AXG_NCTF VCC
AE31 W18 AD34
POWER
VCC_AXG VCC_AXG_NCTF VCC
AD31 VCC_AXG VCC_AXG_NCTF U18 VCC_NCTF AT38
AC31 VCC_AXG VCC_AXG_NCTF T18 Coupling CAP AC34 VCC VCC_NCTF AR38
AA31 VCC_AXG VCC_AXG_NCTF R18 AA34 VCC VCC_NCTF AN38
Y31 VCC_AXG VCC_NCTF AM38
W31 VCC_AXG
Place on the Edge Y34 VCC VCC_NCTF AL38
AH29 VCC_GFXCORE W34 AG38
VCC_AXG VCC VCC_NCTF
AG29 VCC_AXG AM32 VCC VCC_NCTF AE38
AE29 VCC_AXG AL32 VCC VCC_NCTF AA38
AD29 VCC_AXG VCC_AXG AJ16 AJ32 VCC VCC_NCTF Y38
AC29 VCC_AXG VCC_AXG AH16 AH32 VCC VCC_NCTF W38
AA29 VCC_AXG VCC_AXG AD16 AE32 VCC VCC_NCTF U38
Y29 VCC_AXG VCC_AXG AC16 AD32 VCC VCC_NCTF T38
W29 VCC_AXG VCC_AXG AA16 AA32 VCC VCC_NCTF R38
AH28 VCC_AXG VCC_AXG U16 AM31 VCC VCC_NCTF AT37
C AG28 VCC_AXG VCC_AXG T16 AL31 VCC VCC_NCTF AR37 C
VCC GFX
AE28 VCC_AXG VCC_AXG R16 AJ31 VCC VCC_NCTF AN37

AA28 VCC_AXG VCC_AXG AM15 AH31 VCC VCC_NCTF AM37
AH27 VCC_AXG VCC_AXG AL15 AM29 VCC VCC_NCTF AL37
AG27 VCC_AXG VCC_AXG AJ15 Place CAP where AL29 VCC VCC_NCTF AJ37
AE27 VCC_AXG VCC_AXG AH15 LVDS and DDR3 taps AM28 VCC VCC_NCTF AH37
AD27 VCC_AXG VCC_AXG AG15 AL28 VCC VCC_NCTF AG37
AC27 VCC_AXG VCC_AXG AE15 AJ28 VCC VCC_NCTF AE37
AA27 VCC_AXG VCC_AXG AA15 AM27 VCC VCC_NCTF AD37
Y27 VCC_AXG VCC_AXG Y15 FOR VCC SM AL27 VCC VCC_NCTF AC37
VCC NCTF
W27 VCC_AXG VCC_AXG W15 AM25 VCC VCC_NCTF AA37
AH25 U15 1D5V_S3 AL25 Y37
VCC_AXG VCC_AXG VCC VCC_NCTF
AD25 VCC_AXG VCC_AXG T15 AJ25 VCC VCC_NCTF W37
AC25 VCC_AXG AM24 VCC VCC_NCTF U37
W25 1 R66 2 VCC_GMCH_35 N36 T37
VCC_AXG VCC VCC_NCTF
1
AJ24 C195 DY TC9 0R0402-PAD R37
VCC_AXG VCC_NCTF
ST330U2D5VBM-GP
AH24 C198 C194 AT35
VCC_AXG VCC_NCTF
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
AG24 SCD1U10V2KX-4GP AR35
VCC_AXG VCC_NCTF
2
AE24 VCC_AXG VCC_NCTF U35
AD24 VCC_AXG VCC_NCTF AT34
AC24 VCC_AXG VCC_NCTF AR34
AA24 VCC_AXG VCC_NCTF U34
Y24 VCC_AXG VCC_NCTF T34
W24 VCC_AXG VCC_NCTF R34
AM22 VCC_AXG
AL22 VCC_AXG
AJ22 VCC_AXG
Place on the Edge
VCC GFX
AH22 VCC_AXG
AG22 VCC_AXG
AE22 VCC_AXG
AD22 VCC_AXG
AC22 VCC_AXG
AA22 VCC_AXG VCC_SM_LF AU45 SM_LF1_GMCH
BF52 SM_LF2_GMCH
VCC SM LF
AM21 VCC_AXG VCC_SM_LF

AL21 VCC_AXG VCC_SM_LF BB38 SM_LF3_GMCH
AJ21 VCC_AXG VCC_SM_LF BA19 SM_LF4_GMCH
AH21 VCC_AXG VCC_SM_LF BE9 SM_LF5_GMCH
AD21 VCC_AXG VCC_SM_LF AU9 SM_LF6_GMCH
AC21 VCC_AXG VCC_SM_LF AL9 SM_LF7_GMCH CANTIGA-GS-GP-NF
C217
C421
C240
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
AA21
SCD47U16V3ZY-3GP
VCC_AXG
1
C156 C183
C155
C153
Y21 VCC_AXG
B W21 B
VCC_AXG
AM16 VCC_AXG
2
AL16 VCC_AXG
38 VCC_AXG_SENSE VCC_AXG_SENSE AG13

VSS_AXG_SENSE VCC_AXG_SENSE
38 VSS_AXG_SENSE AE13 VSS_AXG_SENSE
place near Cantiga

U60(ISL6263ACRZ-T-GP) place near Cantiga
CANTIGA-GS-GP-NF
A A
5
Dr-Bios.com 4 3 2
Title
Size Document Number
Date: Tuesday, March 17, 2009

1
Wistron Corporation
Cantiga (4 of 6)
JM41_UMA
Sheet 10 of
Rev
40
-1
5 4 3 2 1
5V_S0 3D3V_S0_DAC 1D05V_S0

Imax = 300 mA
3D3V_S0_DAC 852mA
U26 R65 2 80mA 3D3V_CRTDAC_S0 NB1H 8 OF 10
SC2D2U6D3V3MX-1-GP
1
0R0603-PAD C215 C216
SCD01U16V2KX-3GP
SCD1U10V2KX-4GP
ST220U2D5VDM-13GP
SCD47U6D3V2KX-GP
SC4D7U6D3V3KX-GP
SCD47U6D3V2KX-GP
1
1
1 1 TC11
C233
C222
C187
C200
1 VIN VOUT 5 VTT R13
2 GND VTT T12
1
3 4 J31 R11 2 2
EN NC#4 VCCA_CRT_DAC VTT
2
BC2 C396 T10 DY
VTT
SC1U16V3ZY-GP
SC1U16V3ZY-GP
SC10U6D3V5MX-3GP VTT R9
2
1
1
G9091-330T11U-GP T8
BC3 M_VCCA_DAC_BG VTT
L31 R7
CRT
3D3V_S0_DAC VCCA_DAC_BG VTT
M33 T6
74.09091.J3F VSSA_DAC_BG VTT
2
2
D
2ND = 74.09198.G7F 1 R62 2 10mA VTT
VTT
R5
T4
D
0R0603-PAD C209 C208
SCD01U16V2KX-3GP
SCD1U10V2KX-4GP
VTT R3
1
M_VCCA_DPLLA J45 T2 3D3VTVDAC 3D3V_S0_DAC
1D05V_S0 VCCA_DPLLA VTT
R1
VTT
M_VCCA_DPLLB VTT L5
L49 VCCA_DPLLB 1 2
2
0R0603-PAD
65mA SB_20090205
PLL
1
1 R198 2 M_VCCA_DPLLA M_VCCA_HPLL AF10 180ohm 100MHz
0R0603-PAD VCCA_HPLL C201
1
1
C410 C409 C408 M_VCCA_MPLL
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U10V2KX-4GP
AE1 VCCA_MPLL VCCA_TV_DAC K30
2
SCD1U10V2KX-4GP
TV
1D8V_TXLVDS_S0
2
1D5V_S0
DY DY
A PEG A LVDS
1
C225 13.2mA U43 VCCA_LVDS VCC_HDA R189 2
U41 A31 1
SB_20090203
D TV/CRT HDA
SC1KP50V2KX-1GP VCCA_LVDS VCC_HDA 0R0603-PAD
2
65mA 1D5V_S0
V44 VSSA_LVDS
1
1 R202 2 M_VCCA_DPLLB C391
0R0603-PAD 1D5VRUN_TVDAC
SCD1U10V2KX-4GP
VCCD_QDAC N34
1
C414 C413 C415 R74 2 VCCA_PEG_BG

SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U10V2KX-4GP
1 AJ43 VCCA_PEG_BG
2
0R0603-PAD N32 1D5VRUN_QDAC I=300mA NB:180mA
VCCD_TVDAC
1
C244
50mA
2
DY DY SCD1U10V2KX-4GP 3D3V_S0 U11

1D05V_RUN_PEGPLL AG43 VCCA_PEG_PLL
2
1D05V_S0
2
1 VIN VOUT 5 1D8V_NB_S0
C450 2
1D05V_S0 GND
2
R53 2 1D05V_SM
SC1U10V2ZY-GP
1 AW24 VCCA_SM 3 EN/EN# NC#4 4
1
1D05V_S0
POWER
0R0603-PAD AU24 C449
C158 C173 C163 VCCA_SM
480mA 350mA
SC1U10V2ZY-GP
AW22 VCCA_SM
1
2
1
SC4D7U6D3V3KX-GP
SC1U10V3KX-3GP
C
R166 SB_20090205 AU22 VCCA_SM
RT9198-18PBR-GP C
SC10U6D3V5MX-3GP
AU21 VCCA_SM 74.09198.C7F
SC10U6D3V5MX-3GP
0R0603-PAD AW20 VCCA_SM 74.09091.G3F
2
1D05V_SUS_MCH_PLL2
1
C210
SC1U10V3KX-3GP
C229
AU19 VCCA_SM
AW18
A SM
VCCA_SM
1
AU18 VCCA_SM DY
2
FCM1608KF-1-GP 24mA AW16
AU16
VCCA_SM
VCCA_SM
1 2 M_VCCA_HPLL AT16
L4 VCCA_SM
SC4D7U6D3V3KX-GP
AR16 VCCA_SM
1
68.00217.161 C154 C161 AU15

SCD1U10V2KX-4GP VCCA_SM VCC_SM_CK 1D5V_S3
2ND = 68.00248.061 AT15
AR15
VCCA_SM
VCCA_SM
200mA
2
AW14 M25 1 R182 2

VCCA_SM VCC_AXF 0R0603-PAD
N24
AXF
FCM1608KF-1-GP VCC_AXF C451 C189
139.2mA
SCD1U10V2KX-4GP
AT24 VCCA_SM_NCTF VCC_AXF M23
1
M_VCCA_MPLL 1 R184 1D5V_SM_CK_R 2
C390
1 2 AR24 VCCA_SM_NCTF 2 1
L11 1R2F-GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
AT22 VCCA_SM_NCTF DY
1
68.00217.161 C368 C369 AR22 VCCA_SM_NCTF DY SC10U6D3V5MX-3GP
2
2ND = 68.00248.061 SCD1U10V2KX-4GP AT21 VCCA_SM_NCTF
DY AR21 VCCA_SM_NCTF VCC_SM_CK BK24
2
AT19 BL23
SM CK
VCCA_SM_NCTF VCC_SM_CK
120ohm 100MHz AR19 VCCA_SM_NCTF VCC_SM_CK BJ23
1D8V_TXLVDS_S0 1D8V_NB_S0
AT18 VCCA_SM_NCTF VCC_SM_CK BK22
1D05V_S0 1D05V_S0
AR18 VCCA_SM_NCTF 100mA 1 R69 2
C227 0R0603-PAD
3D3V_HV_S0
1
R63 2 1D05V_SM_CK
C224
SC1KP50V2KX-1GP
SC10U6D3V5MX-3GP
L7 1 VCC_TX_LVDS T41
0R0603-PAD C188 AU27 VCCA_SM_CK 106mA
1
B 1D05V_RUN_PEGPLL C190 C205 B

24mA
SC2D2U6D3V3MX-1-GP
SCD1U10V2KX-4GP
1 2 AU28 VCCA_SM_CK VCC_HV C33
2
FCM1608CF-221T02-GP
SC10U6D3V5MX-3GP
AU29 VCCA_SM_CK VCC_HV A33 DY

220ohm 100MHz AU31
HV
VCCA_SM_CK
2
2
1
C246 C249 DY AT31

68.00217.521 SCD1U10V2KX-4GP VCCA_SM_CK_NCTF 1D05V_S0
SC10U6D3V5MX-3GP
AR31 VCCA_SM_CK_NCTF
2ND = 68.00119.111 DY AT29 VCCA_SM_CK_NCTF VCC_PEG AB44
1782mA
2
AR29 VCCA_SM_CK_NCTF VCC_PEG Y44

C196
SC4D7U6D3V3KX-GP
AT28 AC43
PEG
VCCA_SM_CK_NCTF VCC_PEG
1
AR28 AA43 C197 DY C214
VCCA_SM_CK_NCTF VCC_PEG
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
AT27 VCCA_SM_CK_NCTF
AR27 VCCA_SM_CK_NCTF
2
1D5V_S0
VCC_DMI AM44
1D05V_SUS_MCH_PLL2 AN43 1D05V_S0
VCC_DMI
58.7mA AL43
456mA
DMI
R64 2 1D5VRUN_TVDAC VCC_DMI
1 AH12 VCCD_HPLL
0R0603-PAD
157.2mA
SCD1U10V2KX-4GP
1
1
C221 C220 1D05V_RUN_PEGPLL C192
SCD1U10V2KX-4GP
ST150U6D3VBM-GP
AE43 VCCD_PEG_PLL
1
C162
SCD022U16V2KX-3GP
SCD1U10V2KX-4GP
TC10
1
C242 K14 VTTLF1
VTTLF
VTTLF
2
2
VTTLF2
50mA
SCD1U10V2KX-4GP
M46 VCCD_LVDS VTTLF Y12

2
VTTLF3
LVDS
L45 VCCD_LVDS VTTLF P2

2
DY
SCD47U6D3V2KX-GP
SCD47U6D3V2KX-GP
SCD47U6D3V2KX-GP
CANTIGA-GS-GP-NF 1 1 1
C364
C160
C164
L6
1D5VRUN_QDAC 1D8V_NB_S0
A
1
HCB1608K-181T20GP
2
R68 2 1D8V_SUS_DLVDS
SB_20090205 2 2 2
A
1
1
C203 C204 0R0603-PAD

68.00214.101
1
Wistron Corporation
Dr-Bios.com
C231
60.3mA
SCD01U16V2KX-3GP
SCD1U10V2KX-4GP
3D3V_S0 3D3V_HV_S0
SCD1U10V2KX-4GP
2ND = 68.00206.041 R192

2
180ohm 100MHz 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

2

SCD1U10V2KX-4GP
1 2
1
Title
C395
0R0603-PAD
Cantiga (5 of 6)
2
JM41_UMA -1
5 4 3 2 1
5 4 3 2 1
NB1J 10 OF 10
NB1I 9 OF 10
AN25 VSS VSS AM8
BA55 VSS VSS C43 AG25 VSS VSS AK8
AU55 VSS VSS A43 AE25 VSS VSS AH8
AN55 VSS VSS BD42 AA25 VSS VSS AF8
AJ55 VSS VSS H42 Y25 VSS VSS AD8
AE55 VSS VSS BG41 E25 VSS VSS AB8
AA55 VSS VSS AY41 A25 VSS VSS Y8
U55 VSS VSS AU41 BD24 VSS VSS V8
N55 VSS VSS AM41 AN24 VSS VSS P8
BD54 VSS VSS AL41 AL24 VSS VSS M8
BG53 VSS VSS AG41 H24 VSS VSS K8
D AJ53 VSS VSS AE41 BG23 VSS VSS H8 D
AE53 VSS VSS AA41 AY23 VSS VSS BJ7
AA53 VSS VSS R41 E23 VSS VSS E7
U53 VSS VSS M41 BD22 VSS VSS BF6
N53 VSS VSS E41 BB22 VSS VSS BC5
J53 VSS VSS BD40 AN22 VSS VSS BA5
G53 VSS VSS AU40 Y22 VSS VSS AW5
E53 VSS VSS AR40 W22 VSS VSS AU5
K52 VSS VSS AN40 H22 VSS VSS AR5
BG51 VSS VSS W40 BL21 VSS VSS AN5
BA51 VSS VSS U40 BG21 VSS VSS AL5
AW51 VSS VSS T40 AY21 VSS VSS AJ5
AU51 VSS VSS R40 AN21 VSS VSS AG5
AR51 VSS VSS K40 AG21 VSS VSS AE5
AN51 VSS VSS H40 AE21 VSS VSS AC5
AL51 VSS VSS BL39 M21 VSS VSS AA5
AJ51 VSS VSS BG39 E21 VSS VSS W5
AG51 VSS VSS BA39 A21 VSS VSS U5
AE51 VSS VSS E39 BD20 VSS VSS N5
AC51
AA51
W51
VSS
VSS
VSS
VSS
VSS
VSS
C39
A39
BD38
H20
BG19
AY19
VSS
VSS
VSS
VSS VSS
VSS
VSS
L5
J5
G5
U51
R51
N51
VSS
VSS
VSS
VSS VSS
VSS
VSS
AU38
H38
BG37
M19
E19
BD18
VSS
VSS
VSS
VSS
VSS
VSS
C5
BH4
BE3
L51 VSS VSS AU37 N18 VSS VSS U3
J51 VSS VSS M37 H18 VSS VSS E3
G51 VSS VSS E37 BL17 VSS VSS BC1
C51 VSS VSS BD36 BG17 VSS VSS AW1
C BK50 AW36 AY17 AR1 C
VSS VSS VSS VSS
AM50 VSS VSS H36 M17 VSS VSS AL1
K50 VSS VSS BL35 E17 VSS VSS AG1
BG49 VSS VSS BG35 A17 VSS VSS AC1
E49 VSS VSS AY35 BD16 VSS VSS W1
C49 VSS VSS AU35 AN16 VSS VSS N1
BD48 VSS VSS AL35 AG16 VSS VSS J1
BB48 VSS VSS AG35 AE16 VSS VSS AU43
AY48 VSS VSS AE35 Y16 VSS VSS BB42
AV48 VSS VSS AA35 W16 VSS VSS AW38
AT48 VSS VSS Y35 N16 VSS VSS BA35
AP48 VSS VSS M35 H16 VSS VSS L29
AM48 VSS VSS E35 BG15 VSS VSS N28
AK48 VSS VSS A35 AY15 VSS VSS N22
AH48 VSS VSS BD34 AN15 VSS VSS N20
AF48 VSS VSS AU34 AD15 VSS VSS N14
AD48 VSS VSS AN34 AC15 VSS VSS AL13
AB48 VSS VSS H34 R15 VSS VSS B10
Y48 VSS VSS BL33 M15 VSS VSS AN13
V48 VSS VSS BG33 E15 VSS
T48 VSS VSS AY33 BD14 VSS VSS N42
P48 VSS VSS E33 H14 VSS VSS N40
M48 VSS VSS BD32 BL13 VSS VSS N38
K48 VSS VSS AU32 BG13 VSS VSS M39
H48 VSS VSS AN32 AY13 VSS
BL47 VSS VSS AG32 AU13 VSS
BG47 VSS VSS AC32 AR13 VSS VSS_NCTF AJ38
E47 VSS VSS Y32 AJ13 VSS VSS_NCTF AH38
C47 VSS VSS H32 AC13 VSS VSS_NCTF AD38
B B
A47 VSS VSS B32 AA13 VSS VSS_NCTF AC38
BD46 VSS VSS BJ31 W13 VSS VSS_NCTF T35
AY46 BG31 U13 R35
VSS NCTF
VSS VSS VSS VSS_NCTF
AM46 VSS VSS AY31 M13 VSS VSS_NCTF AT32
AK46 VSS VSS AN31 E13 VSS VSS_NCTF AR32
AH46 VSS VSS M31 A13 VSS VSS_NCTF U32
BG45 VSS VSS E31 BD12 VSS VSS_NCTF R32
AE45 VSS VSS N30 AV12 VSS VSS_NCTF T28
AC45 VSS VSS H30 AP12 VSS VSS_NCTF R28
AA45 VSS VSS AN29 AM12 VSS VSS_NCTF AT25
W45 VSS VSS AJ29 AK12 VSS VSS_NCTF AR25
R45 VSS VSS M29 AB12 VSS VSS_NCTF T24
N45 VSS VSS A29 V12 VSS VSS_NCTF R24
E45 VSS VSS AW28 P12 VSS VSS_NCTF AN19
BD44 VSS VSS AN28 H12 VSS VSS_NCTF AJ19
BB44 VSS VSS AD28 BG11 VSS VSS_NCTF AA19
AV44 VSS VSS AC28 AG11 VSS VSS_NCTF Y19
AK44 VSS VSS Y28 E11 VSS VSS_NCTF T19
AH44 VSS VSS W28 BD10 VSS VSS_NCTF R19
AF44 VSS VSS H28 AY10 VSS VSS_NCTF AN18
AD44 VSS VSS F28 AP10 VSS
K44 VSS VSS AN27 H10 VSS
H44 VSS VSS AJ27 BL9 VSS RSVD#B55 B55
BL43
BG43
VSS VSS M27
BF26
BG9
E9
VSS VSS SCB VSS_SCB B2 VSS_SCB#B2 1 TP50 TPAD14-GP
VSS VSS VSS
BL55,BL1,A55,D1,A4
AY43 VSS VSS BD26 A9 VSS NCTF_VSS_SCB#BL55 TP55 TPAD14-GP

NCTF TEST PIN:
AR43 VSS VSS N26 BD8 VSS NCTF_VSS_SCB#BL55 BL55 1

W43 H26 BB8 BL1 NCTF_VSS_SCB#BL1 1 TP49 TPAD14-GP
VSS VSS VSS NCTF_VSS_SCB#BL1 NCTF_VSS_SCB#A55 TP53 TPAD14-GP
A R43 VSS VSS BJ25 AY8 VSS NCTF_VSS_SCB#A55 A55 1 A
M43 AY25 AV8 D1 NCTF_VSS_SCB#D1 1 TP48 TPAD14-GP
VSS VSS VSS NCTF_VSS_SCB#D1 NCTF_VSS_SCB#A4 TP51 TPAD14-GP
E43 VSS VSS AU25 AT8 VSS NCTF_VSS_SCB#A4 A4 1
Wistron Corporation
Dr-Bios.com
AP8 VSS
CANTIGA-GS-GP-NF 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
CANTIGA-GS-GP-NF Taipei Hsien 221, Taiwan, R.O.C.
Title
Cantiga (6 of 6)
JM41_UMA -1
5 4 3 2 1
5 4 3 2 1
C136 SC7P50V2DN-2GP
1 2 RTC_X1
3RD = 83.00016.F11
4
2ND = 83.00016.K11
1
83.00016.B11 X1
3D3V_AUX_S5 D4 X-32D768KHZ-40GPU R50
1 RTC_AUX_S5 82.30001.841 10MR2J-L-GP
2ND = 82.30001.A41
SC1U16V3ZY-GP
3
2
1
D D
2 C384
SB1A
2
BAS16-1-GP C133 SC7P50V2DN-2GP 1 OF 6
1 2
F25 RTCX1 FWH0/LAD0 H3 LPC_LAD0 28,29
RTC_X2 G25 J3
SRN20KJ-GP-U RTCX2 FWH1/LAD1 LPC_LAD1 28,29
FWH2/LAD2 K5 LPC_LAD2 28,29
2 3 RTC_RST# G24 L3 1D05V_S0 1D05V_S0
RTCRST# FWH3/LAD3 LPC_LAD3 28,29
1 4 SRTC_RST# C24
RTC
LPC
SRTCRST#
1
1 2 INTRUDER# C23 J2 LPC_LFRAME# 28,29
RTC_BAT 1 RN6 R171 1MR2J-1-GP INTRUDER# FWH4/LFRAME#
24,28 RTC_BAT 2
1
R114 1KR2J-1-GP G62 C143 C148 INTVRMEN E25 H1 LDRQ0# 1 TP16 TPAD14-GP R36 R37
INTVRMEN LDRQ0# 3D3V_LDRQ1_S0 TP15 TPAD14-GP 56R2J-4-GP 56R2J-4-GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
D25 LAN100_SLP LDRQ1#/GPIO23 J1 1
1D05V_S0 DY DY
GAP-OPEN
2
G22 GLAN_CLK A20GATE N3 KA20GATE 28
AB23 H_A20M# 4 H_DPRSTP#
A20M#
1
TPAD14-GP TP20 1ICH9_LAN_RSTSYNC D14 H_PWRGD
LAN_RSTSYNC H_DPRSTP#
DPRSTP# AE23 H_DPRSTP# 4,8,34
A14 AE24 H_DPSLP# 4 RN4
LAN_RXD0 DPSLP#
LAN / GLAN
D12 LAN_RXD1 1 4
B14 AD25 H_FERR#_R 2 3 H_FERR# 4
LAN_RXD2 FERR#
GLAN_COMP place D13 LAN_TXD0 CPUPWRGD AE22 H_PWRGD H_PWRGD 4,32 SRN56J-4-GP
within 500 mil of ICH9M C13 LAN_TXD1
RTC_AUX_S5 A13 AD23 H_IGNNE# 4
LAN_TXD2 IGNNE#
CPU
1D5V_S0 HDMI_EN D15 AE21
GPIO56 INIT# H_INIT# 4
1
INTR AD24 H_INTR 4

C R51 1 2 GLAN_COMP H22 L1 KBRCIN# 28
C
R165 24D9R2F-L-GP GLAN_COMPI RCIN#
330KR2F-L-GP H21 GLAN_COMPO
AD21 H_NMI 4 1D05V_S0
ACZ_BIT_CLK NMI R41
AE7 HDA_BIT_CLK SMI# AC21 H_SMI# 4
2
ACZ_SYNC_R AB7 1 2
INTVRMEN HDA_SYNC 56R2J-4-GP
STPCLK# AC25 H_STPCLK# 4
ACZ_RST#_R AA7 HDA_RST# H_THERMTRIP_R
THRMTRIP# AC23 1 2 PM_THRMTRIP-A# 4,8,32
22 ACZ_SDATAIN0 AB6 R40 54D9R2F-L1-GP
TPAD14-GP TP11 ACZ_SDIN1 HDA_SDIN0 ICH_TP11 TP36 TPAD14-GP
1 AE6 HDA_SDIN1 TP11 AC22 1
TPAD14-GP TP35 1 ACZ_SDIN2 AC6 HDA_SDIN2
IHDA
8 ACZ_SDIN3 AA5 HDA_SDIN3
AD12 SATA_RXN4_C SCD01U50V2KX-1GP 2 1 C94 SATA_RXN4 24
ACZ_SDATAOUT_R SATA4RXN SATA_RXP4_C SCD01U50V2KX-1GP C93
3D3V_S5
TPAD14-GP
TPAD14-GP
TP33
TP44
1 HDA_DOCK_EN#
HDA_DOCK_RST#
AC7
AD8
HDA_SDOUT
HDA_DOCK_EN#/GPIO33
SATA4RXP
SATA4TXN
SATA4TXP
AE12
AB12
AA12
SATA_TXN4_C
SATA_TXP4_C
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
2
2
2
1
1
1
C95
C96
SATA_RXP4 24
SATA_TXN4 24
SATA_TXP4 24
ODD
1 AB8 HDA_DOCK_RST#/GPIO34
SATA5RXN AC11
1
31 MEDIA_LED# AC9 SATALED# SATA5RXP AD11

R175 AB10
C89 SCD01U50V2KX-1GP SATA_RXN0_C SATA5TXN
HDMI_EN 10KR2J-3-GP 21 SATA_RXN0
C90
1 2
SCD01U50V2KX-1GP SATA_RXP0_C
AE14 SATA0RXN SATA5TXP AA10
SSD 21 SATA_RXP0
C86
1 2
SCD01U50V2KX-1GP SATA_TXN0_C
AD14 SATA0RXP
SATA
21 SATA_TXN0 1 2 AC15 SATA0TXN SATA_CLKN AC16 CLK_PCIE_SATA# 3
2
21 SATA_TXP0 C85 1 2 SCD01U50V2KX-1GP SATA_TXP0_C AD15 AB16 CLK_PCIE_SATA 3

SATA0TXP SATA_CLKP
HDMI_EN 20 SATA_RXN1 C108 1 2 SCD01U50V2KX-1GP SATA_RXN1_C AD13 AD10 SATARBIAS
C109 SCD01U50V2KX-1GP SATA_RXP1_C SATA1RXN SATARBIAS#
HDD 20
20
SATA_RXP1
SATA_TXN1 C111
1
1
2
2 SCD01U50V2KX-1GP SATA_TXN1_C
AC13
AA14
SATA1RXP
SATA1TXN
SATARBIAS AE10 2
24D9R2F-L-GP R33
1
1
20 SATA_TXP1 C110 1 2 SCD01U50V2KX-1GP SATA_TXP1_C AB14

B SATA1TXP B
HDMI_DIS R174 Place within 500 mils of
10KR2J-3-GP ICH9 ball
ICH9M-1-GP
2
R151
3D3V_S0 1 2 MEDIA_LED#
RN13
10KR2J-3-GP 8 HDA_RST#_NB 1 8 ACZ_RST#_R
8 HDA_SDO_NB 2 7 ACZ_SDATAOUT_R
8 HDA_SYNC_NB 3 6 ACZ_SYNC_R
8 HDA_BCLK_NB 4 5 ACZ_BIT_CLK
SRN33J-7-GP
RN3
22 ACZ_RST# 1 8 ACZ_RST#_R <Core Design>
A 22 ACZ_SDATAOUT 2 7 ACZ_SDATAOUT_R A
22 ACZ_SYNC 3 6 ACZ_SYNC_R
22 ACZ_BITCLK 4 5 ACZ_BIT_CLK
Wistron Corporation
Dr-Bios.com
integrated VccSus1_05,VccSus1_5,VccCL1_5 SRN0J-7-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1
C97 Taipei Hsien 221, Taiwan, R.O.C.

INTVRMEN
SCD1U10V2KX-4GP
High=Enable Low=Disable DY Title

2
integrated VccLan1_05VccCL1_05
ICH9-M (1 of 4)
LAN100_SLP High=Enable Low=Disable Size Document Number Rev
JM41_UMA -1
5 4 3 2 1
5 4 3 2 1
SB1C 3 OF 6
RN2
SMB
SB1B 2 OF 6 3D3V_S5 C18 AE19 SATA0GP 8 1
16 SMB_CLK SMBCLK SATA0GP/GPIO21
C15 AA18 SATA1GP 7 2
RN17 16 SMB_DATA SMBDATA SATA1GP/GPIO19
A11 G4 PCI_REQ#0 SMB_LINK_ALERT# B21 AE20 ICH_GPIO36 6 3
AD0 REQ0# LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36
SATA
GPIO
SMLINK0 ICH_GPIO37
B12
A10
AD1 PCI GNT0# E1
A9 PCI_REQ#1
1
2
4
3 SMLINK1
E18
A24
SMLINK0 SATA5GP/GPIO37 AA20 5 4
AD2 REQ1#/GPIO50 SMLINK1 SRN10KJ-6-GP
C12 AD3 GNT1#/GPIO51 E12 CLK14 K1 CLK_ICH14 3
A8 B11 PCI_REQ#2 PM_RI# C20 AB5 CLK48_ICH 3
AD4 REQ2#/GPIO52 SRN10KJ-5-GP RI#
Clocks
CLK48
A12 AD5 GNT2#/GPIO53 C10
E10 D6 PCI_REQ#3 T5 R3
AD6 REQ3#/GPIO54 DBRESET# SUS_STAT#/LPCPD# SUSCLK
C11 AD7 GNT3#/GPIO55 C6 C25 SYS_RESET#
B9 AD8
BOOT BIOS Strap SLP_S3# D18 PM_SLP_S3# 28,32,35
D8 AD9 C/BE0# D10 8 PM_SYNC# L2 PMSYNC#/GPIO0 SLP_S4# B20 PM_SLP_S4# 28,32,36,37
PCI_GNT#0 and SPI_CS1# A4 A5 PCI_GNT#0 SPI_CS#1 BOOT BIOS Location D16 PM_SLP_S5# 1 TP47
D AD10 C/BE1# SMB_ALERT# SLP_S5# TPAD14-GP D
have weak internal Pull up E8 AD11 C/BE2# E6 A23 SMBALERT#/GPIO11
A3 C9 0 1 SPI E14 S4_STATE# 1 TP18
AD12 C/BE3# S4_STATE#/GPIO26 TPAD14-GP
D9 AD13 1 0 PCI 3 PM_STPPCI# B15 STP_PCI#/GPIO15
C8 C3 PCI_IRDY# 1 1 LPC(Default) A20 D23
SYS GPIO
AD14 IRDY# 3 PM_STPCPU# STP_CPU#/GPIO25 PWROK PWROK 8,32
C2 AD15 PAR B1 A16 swap override strap
D7 T3 M5 M1 PM_DPRSLPVR_1 R48 2 100R2J-2-GP
1 PM_DPRSLPVR 8,34
AD16 PCIRST# 28 PM_CLKRUN# CLKRUN#/GPIO32 DPRSLPVR/GPIO16
B3 AD17 DEVSEL# A7 PCI_DEVSEL# low = A16 swap override enable R44 1 2DY
PCI_PERR# PCI_GNT#3 PM_BATLOW#_R 100KR2J-1-GP
Power MGT
D11 AD18 PERR# D4 high = default 25 PCIE_WAKE# C21 WAKE# BATLOW# C16
B6 C5 PCI_LOCK# L4 D1
AD19 PLOCK# 28 INT_SERIRQ SERIRQ
D5 H5 PCI_SERR# 1 THRM# AD20 U4 PWRBTN#_ICH 1 BAS16-1-GP PM_PWRBTN# 28
AD20 SERR# PCI_STOP# 3D3V_S0 TPAD14-GP TP6 THRM# PWRBTN#
D3 AD21 STOP# A6
PCI_TRDY# LAN_RST#_SB
F4
E3
AD22
AD23
TRDY#
FRAME#
A2
B8 PCI_FRAME# SB_20090205 28,32,34 VR_PWRGD B24 VRMPWRGD LAN_RST# D22 3
83.00016.B11
E4 A19 D19 RSMRST#_SB 2 2ND = 83.00016.K11
AD24 TP12 RSMRST#
1
B2 A21 PLT_RST#_R 1 R177 2 PLT_RST# 3RD = 83.00016.F11
AD25 PLTRST# 0R0402-PAD R146
C4 AD26 PCICLK B5 AE16 GPIO1 CK_PWRGD U1 CLK_PWRGD 3 3D3V_S0
10KR2J-3-GP
C1 AD27 PME# T1 1 2DY 28 EC_TMR AE18 GPIO6
D1 C388 SC100P50V2JN-3GP 28 ECSCI#_1 AD18 T4 PWROK 8,32
AD28 GPIO7 CLPWROK
E2 AD29 28 ECSWI# B25 GPIO8
2
J4 AD30 PCLK_ICH 3 C14 GPIO12 SLP_M# B23 PM_SLP_M# 1 TP22
1
H2 D20 TPAD14-GP
AD31 PSW_CLR# GPIO13 R168
AE17 GPIO17 CL_CLK0 C22 CL_CLK0 8
3K24R2F-GP
INT_PIRQA# F1
Interrupt I/F G3 INT_PIRQE# TPAD14-GP TP39 1ICH9_GPIO20
K3
AC8
GPIO18 CL_CLK1 A18
INT_PIRQB# PIRQA# PIRQE#/GPIO2 INT_PIRQF# TPAD14-GP TP8 GPIO20

F5 PIRQB# PIRQF#/GPIO3 G1 1CLK_SEL1 AC19 SCLOCK/GPIO22 CL_DATA0 E22 CL_DATA0 8
2
2
INT_PIRQC# INT_PIRQG# G61
Controller Link
F2 F3 D17 B18
GPIO
INT_PIRQD# PIRQC# PIRQG#/GPIO4 INT_PIRQH# GPIO27 CL_DATA1
C7 PIRQD# PIRQH#/GPIO5 H4 E20 GPIO28
3 SATACLKREQ# M4 F21 CL_VREF0_ICH
SATACLKREQ#/GPIO35 CL_VREF0
GAP-OPEN
AB18 SLOAD/GPIO38 CL_VREF1 A17
1
ICH9M-1-GP AC18 SDATAOUT0/GPIO39
1
C MIC_SEL_1 AB19 C17 R169 C
SDATAOUT1/GPIO48 CL_RST0# CL_RST#0 8
RP3 RP2 AC20 B17 453R2F-1-GP
SCD1U10V2KX-4GP
GPIO49 CL_RST1#
1
PCI_REQ#3 NO_iTPM
C372
1 10 3D3V_S0 1 10 3D3V_S0 A16 GPIO57/CLGPIO5
PCI_STOP# 2 9 PCI_LOCK# PCI_PERR# 2 9 PCI_TRDY# A22 ICH_GPIO24 1 TP23
MEM_LED/GPIO24
2
PCI_FRAME# 3 8 PCI_DEVSEL# INT_PIRQB# 3 8 PCI_IRDY# 22 ACZ_SPKR K4 E16 SUSPWRACK TPAD14-GP
SPKR GPIO10/SUS_PWR_ACK
2
PCI_REQ#1 4 7 INT_PIRQD# INT_PIRQG# 4 7 PCI_SERR# GPIO49 should be pulled down to 8 MCH_ICH_SYNC# AB20 A15 AC_PRESENT
PCI_REQ#2 PCI_REQ#0 ICH_TP3 MCH_SYNC# GPIO14/AC_PRESENT ICH_GPIO91 TP24
3D3V_S0 5 6 3D3V_S0 5 6 GND only when using Teenah. When 1 C19 TP3 WOL_EN/GPIO9 D21
TPAD14-GPTP21
TPAD14-GP TP21 ICH_TP8 TPAD14-GP
MISC
using Cantiga, this ball should 1 AB17 TP8
1
SRN8K2J-2-GP-U SRN8K2J-2-GP-U TPAD14-GP TP43
TPAD14-GPTP43 1 ICH_TP9 AC17
be left as No Connect. TPAD14-GP TP40
TPAD14-GPTP40 ICH_TP10 TP9 R178
1 AD17 TP10
TPAD14-GP TP37
TPAD14-GPTP37 100KR2J-1-GP
INT_PIRQH# 1
RP1
10 3D3V_S0
-1_20090305
ECSCI#_1 2 9 INT_PIRQC# ICH9M-1-GP
2
INT_PIRQF# 3 8 INT_PIRQE# LAN_RST#_SB
PM_CLKRUN# 4 7 INT_PIRQA#
1
5 6 INT_SERIRQ RP4 3D3V_S5
3D3V_S0 4 OF 6 3D3V_S5
SB1D ECSWI# 1 10 R276
SRN8K2J-2-GP-U PM_RI# 2 9 DBRESET# 100R2F-L1-GP-U
25 PCIE_RXN1 T25 V25 DMI_RXN0 8 3 8 SMB_LINK_ALERT#
PERN1 DMI0RXN PCIE_WAKE# SUSPWRACK
T24 V24 4 7
Direct Media Interface
25 PCIE_RXP1 PERP1 DMI0RXP DMI_RXP0 8
2
25 PCIE_TXN1 C127 SCD1U10V2KX-5GP 2 1 TXN1 R24 U24 DMI_TXN0 8 5 6 SMB_ALERT#
PETN1 DMI0TXN 3D3V_S5
25 PCIE_TXP1 C126 SCD1U10V2KX-5GP 2 1 TXP1 R23 U23 DMI_TXP0 8
PETP1 DMI0TXP
LAN P25 W23
SRN10KJ-L3-GP
25 PCIE_RXN2 PERN2 DMI1RXN DMI_RXN1 8
25 PCIE_RXP2 P24 PERP2 DMI1RXP W24 DMI_RXP1 8
C132 SCD1U10V2KX-5GP 2 1 TXN2 P21 V21 3D3V_S5
25 PCIE_TXN2 PETN2 DMI1TXN DMI_TXN1 8
25 PCIE_TXP2 C130 SCD1U10V2KX-5GP 2 1 TXP2 P22 V22 DMI_TXP1 8
PETP2 DMI1TXP PM_BATLOW#_R 1
MINICARD1 N23 Y24 R176
2
8K2R2J-3-GP
PERN3 DMI2RXN DMI_RXN2 8
N24 Y25 DMI_RXP2 8 PLT_RST# 1 R56 2 PLT_RST1# PLT_RST1# 8,24,25,28,29
PCI-Express
B PERP3 DMI2RXP 0R0402-PAD B

M21 PETN3 DMI2TXN Y21 DMI_TXN2 8
1
M22 PETP3 DMI2TXP Y22 DMI_TXP2 8
No Reboot Strap R55
M25 AB24 SPKR LOW = Defaule 100KR2J-1-GP
3D3V_S5 PERN4 DMI3RXN DMI_RXN3 8 1D5V_S0
RN5 M24 PERP4 DMI3RXP AB25 DMI_RXP3 8 High=No Reboot
L24 PETN4 DMI3TXN AA23 DMI_TXN3 8
2
5 4 USB_OC#0 L23 AA24 DMI_TXP3 8
PETP4 DMI3TXP
1
6 3 USB_OC#2
7 2 USB_OC#3~11 K24 T21 R35 3D3V_S0
PERN5 DMI_CLKN CLK_PCIE_ICH# 3
8 1 USB_OC#1 K25 T22 24D9R2F-L-GP
PERP5 DMI_CLKP CLK_PCIE_ICH 3 3D3V_S5
K21 MIC_SEL_1 1 2
PETN5 R149 10KR2J-3-GP
SRN10KJ-6-GP K22 PETP5 DMI_ZCOMP AB21
2
AB22 DMI_IRCOMP_R ACZ_SPKR 1 2 RN19

DMI_IRCOMP R49 1KR2J-1-GP AC_PRESENT
H24 PERN6/GLAN_RXN DY 1 8
H25 AE2 USB THRM# 1 2 2 7
PERP6/GLAN_RXP USBP0N USBPN0 25
J24 AD1 R38 10KR2J-3-GP 3 6 NO_iTPM
PETN6/GLAN_TXN USBP0P USBPP0 25
J23 AD3 USBPN1 20 Pair Device 4 5 PWROK
PETP6/GLAN_TXP USBP1N
USBP1P AD4 USBPP1 20
E24 SPI_CLK USBP2N AC2 USBPN2 26 0 USB2 SRN10KJ-6-GP
E23 SPI_CS0# USBP2P AC3 USBPP2 26
F23 SPI_CS1#/GPIO58/CLGPIO6 USBP3N AC5 USBPN3 25 1 USB3 D3
AB4 1 RSMRST#_SB
USBP3P USBPP3 25
F22 SPI_MOSI USBP4N AB2 USBPN4 19 2 USB4
SB_20090205
SPI
G23 SPI_MISO USBP4P AB1 USBPP4 19 28 RSMRST#_KBC 3
1
AA3 3 WiMAX R54
USB_OC#0 USBP5N
25 USB_OC#0 P4 OC0#/GPIO59 USBP5P AA2 2
USB_OC#1
100KR2J-1-GP
20 USB_OC#1 N4 OC1#/GPIO40 USBP6N Y1 4 WEBCAM
USB_OC#2
TP70
1 N1
P5
OC2#/GPIO41 USB USBP6P Y2
W2 5 NC
BAT54-5-GP
83.BAT54.D81
OC3#/GPIO42 USBP7N USBPN7 24
2
TPAD14-GP P1 OC4#/GPIO43 USBP7P W3 USBPP7 24 2ND = 83.BAT54.X81
A P2 OC5#/GPIO29 USBP8N V1 6 NC 3RD = 83.00054.S81
<Core Design>
A
M3 OC6#/GPIO30 USBP8P V2
M2 OC7#/GPIO31 USBP9N Y5 USBPN9 20 7 BLUETOOTH
USB_OC#3~11 P3
R1
OC8#/GPIO44 USBP9P Y4
U3
USBPP9 20
8 NC Wistron Corporation
Dr-Bios.com
OC9#/GPIO45 USBP10N USBPN10 25
R4 U2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
OC10#/GPIO46 USBP10P USBPP10 25
R2 OC11#/GPIO47 USBP11N V4 USBPN11 24 9 USB1 Taipei Hsien 221, Taiwan, R.O.C.
These R need close SB USBP11P V5 USBPP11 24
within 600 mils USB_RBIAS_PN AE5 10 MINIC2 Title
USBRBIAS
2 1
R156 22D6R2F-L1-GP
AD5 USBRBIAS#
11 Cardreader ICH9-M (2 of 4)
ICH9M-1-GP -1
JM41_UMA
5 4 3 2 1
5 4 3 2 1
SB1F 6 OF 6
RTC_AUX_S5
6uA in G3 G17 VCCRTC VCC1_05 L11 Layout Note:Place near ICH9M
1D05V_S0
V5REF_S0 VCC1_05 L12
1.13A
SB_20090205 G7 V5REF VCC1_05 L13
1
C382 C381 L14
V5REF_S5 VCC1_05
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
U7 V5REF_SUS VCC1_05 L15
1
M11 C359 C348 C352 C358 C351
VCC1_05
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC39P50V2JN-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
J19 VCC1_5_B VCC1_05 M15 DY
K18 VCC1_5_B VCC1_05 N11 DY
2
657mA K19
L18
VCC1_5_B
VCC1_5_B
VCC1_05
VCC1_05
N15
P11
1D5V_S0 1D5V_PCIE_S0 L19 P15
VCC1_5_B VCC1_05
M18 VCC1_5_B VCC1_05 R11
M19 VCC1_5_B VCC1_05 R12
2 R266 ST220U2D5VDM-13GP
D
0R0603-PAD
1 N18
N19
VCC1_5_B
VCC1_5_B
VCC1_05
VCC1_05
R13
R14 L3
23mA D
1
C355 C354 TC4 C353 P18 R15 1D5V_S0
VCC1_5_B VCC1_05 1D5V_DMIPLL_ICH_S0
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC2D2U10V3KX-1GP
DY R18 VCC1_5_B 1 2
T18 IND-1D2UH-10-GP
VCC1_5_B
1
T19 VCC1_5_B 68.1R220.10D
U18 C119 C121 2ND = 68.1R220.10B
CORE
VCC1_5_B SCD01U16V2KX-3GP SC10U6D3V5MX-3GP
U19 VCC1_5_B
2
1D05V_S0
1D05V_DMI_ICH_S0 1 R42 2
0R0603-PAD
50mA
1
C346 C124 C125
SC39P50V2JN-1GP
SC10U6D3V5MX-3GP
SC4D7U6D3V3KX-GP
VCCDMIPLL P19
*Within a given well, 5VREF needs to be up before the
corresponding 3.3V rail VCC_DMI T17 DY
2
U17 1D05V_S0
VCC_DMI
1mA
47mA V_CPU_IO
V_CPU_IO
V16
U16
3D3V_S0 5V_S0 1D5V_S0 1D5V_APLL_S0 3D3V_S0
L1
1
D11 V18 C336 C337
VCC3_3
1
RB751V-40-2-GP C332
C340
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1 2 DY C344
A
83.R2004.B8F SC1U10V2KX-1GP
VCCA3GP
AE9 SCD1U10V2KX-4GP
VCC3_3
2
1
1
2ND = 83.R0304.A8F R167 IND-10UH-66-GP SCD1U10V2KX-4GP
2
3RD = 83.R3004.A8F 100R2J-2-GP C60 C70
2mA 3D3V_S0
SC10U6D3V5MX-3GP
SC1U10V3ZY-6GP
2
2
VCC3_3 AA9
VCC3_3=278mA
K
V5REF_S0 V14
VCC3_3
1
C W14 C328 C
VCC3_3 3D3V_S0
1
C376
SCD1U16V2ZY-2GP SCD1U10V2KX-4GP
2
G8 1D5V_S0
VCC3_3
VCCP_CORE
2
1
C365 C374 C375
VCC3_3 H7
32mA
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
VCC3_3 H8
1
Layout Note: C331
2
Place near ICH9 3D3V_S5 5V_S5 SCD1U10V2KX-4GP
D10
2
RB751V-40-2-GP
A
83.R2004.B8F
2ND = 83.R0304.A8F R161 AD7
VCCHDA
PCI
3RD = 83.R3004.A8F 100R2J-2-GP
2mA 1D5V_S0 VCCSUSHDA_ICH 32mA
SATA+USB=1.56A W17 VCCSATAPLL VCCSUSHDA V10
K
1
V5REF_S5 U13 T7 VCC_SUS_1_05 C345
VCC1_5_A VCCSUS1_05
SCD1U10V2KX-4GP
V13 VCC1_5_A VCCSUS1_05 H15
1
C338 W13 VCC1_5_A
2
SCD1U16V2ZY-2GP C334 C335
ARX
VCCSUS1_5 H16
SC1U10V2KX-1GP SC1U10V2KX-1GP
2
VCCSUS1_5 V7
1
C341
SCD1U10V2KX-4GP
G14 3D3V_S5
VCCSUS3_3
2
U12 VCC1_5_A VCCSUS3_3 G15
V12 VCC1_5_A VCCSUS3_3 H14
W12 VCC1_5_A
1
ATX
C350 C361
SC33P50V2JN-3GP
VCCPSUS
SCD1U10V2KX-4GP
SC39P50V2JN-1GP
DY C360
VCCSUS3_3 W8
2
B B
1D5V_S0 J7
VCCSUS3_3
VCCSUS3_3 J8
W10 K7 3D3V_S5
VCC1_5_A VCCSUS3_3
SCD1U10V2KX-4GP
VCCSUS3_3 K8
177mA
1
C377 U15 L7
C366 VCC1_5_A VCCSUS3_3
SCD1U10V2KX-4GP
V15 VCC1_5_A VCCSUS3_3 L8
1
M7 C356 C357 C349
VCCSUS3_3
2
SCD1U10V2KX-4GP
SCD1U16V2KX-3GP
SCD022U16V2KX-3GP
W18 VCC1_5_A VCCSUS3_3 M8
VCCSUS3_3 N7
2
G9 VCC1_5_A VCCSUS3_3 N8
H9 P7
VCCPUSB
VCC1_5_A VCCSUS3_3
VCCSUS3_3 P8
V11 VCC1_5_A
U11 VCC1_5_A
1D5V_S0
USBPLL=10mA U8 VCCUSBPLL VCCCL1_05 G18 VCCCL1D05V_INT_ICH

1
1
C79 C342 C343 T9 H17 VCCCL1D5V_INT_ICH C371
VCC1_5_A VCCCL1_5
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
USB CORE
SCD1U10V2KX-5GP
DY U9 VCC1_5_A
J14 VCCCL3D3V_INT_ICH
VCCCL3_3
2
2
1
1
VCCCL3_3 K14
3D3V_S0 3D3V_S0 C379 C380
SCD1U10V2KX-5GP
19mA in S0;78mA in S3/S4/S5 DY DY
SC1U6D3V2ZY-GP
2
2
VCCLAN_1D05V_INT_ICH G11
VCCLAN1_05 18mA
1
C378 H11 1 R164 2

VCCLAN1_05
1
C362 SCD1U10V2KX-4GP 0R0603-PAD

SCD1U10V2KX-4GP
C363 G12 VCCLAN3_3

2
1D5V_S0
SC33P50V2JN-3GP
L2 H13 VCCLAN3_3
2
A
2 1 23mA 1D5VGLANPLL_ICH J17 VCCGLANPLL
A
Dr-Bios.com
1
C370
SC10U6D3V5MX-3GP
C88
GLAN POWER
0R0805-PAD H19 VCCGLAN1_5

Wistron Corporation
SC2D2U10V3KX-1GP
J18 VCCGLAN1_5
2
1D5V_S0 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

SC39P50V2JN-1GP
80mA K16 VCCGLAN3_3 Title

1
3D3V_S0
C333
C367
1mA ICH9M-1-GP ICH9-M (3 of 4)
SC1U10V2KX-1GP Size Document Number Rev
2
JM41_UMA -1
Date: Saturday, March 07, 2009 Sheet 15 of 40
5 4 3 2 1
A B C D E
SB1E 5 OF 6
B4 VSS VSS U5
B7 VSS VSS U10
B10 VSS VSS W11
B13 VSS VSS U14
B16 VSS VSS W16
B19 VSS VSS U21
B22 VSS VSS U22
D2 VSS VSS U25
D24 VSS VSS V3
E5 VSS VSS V8
E7 VSS VSS V19
4 E9 VSS VSS V23 4
E11 VSS VSS W1
E13 VSS VSS W4
E15 VSS VSS W5
E17 VSS VSS W7
E19 VSS VSS W9
E21 VSS VSS W15
F24 VSS VSS W19
G2 VSS VSS W21
G5 VSS VSS W22
G10 VSS VSS W25
G13 VSS VSS Y3
G16 VSS VSS Y23
G19 VSS VSS AA1
G21 VSS VSS AA4
H10 VSS VSS AA6
H12 VSS VSS AA8
H18 VSS VSS AA11
H23 VSS VSS AA13
J5 VSS VSS AA15
J9 VSS VSS AA16
J10 VSS VSS AA17
J11 VSS VSS AA19
J12 VSS VSS AA21
J13 VSS VSS AA22
J15 VSS VSS AA25
J21 VSS VSS AB3
J22 VSS VSS AB9
J25 VSS VSS AB11
3 K2 AB13 3
VSS VSS
K9 VSS VSS AB15
K10 AC24 3D3V_S5 3D3V_S0
VSS VSS
K11 VSS VSS AC1
K12 VSS VSS AC4
K13 VSS VSS AC10
K15 VSS VSS AC12
K17 VSS VSS AC14
8
7
6
5
K23 VSS VSS AD2
L5 AD6 RN21
VSS VSS
L9 VSS VSS AD9 SRN2K2J-2-GP
L10 VSS VSS AD16
L16 VSS VSS AD19
L17 VSS VSS AD22
1
2
3
4
L21 VSS VSS AE3
L22 VSS VSS AE4
L25 VSS VSS AE11
M9 VSS VSS AE13
M10 AE15 3D3V_S0
VSS VSS
M12 VSS VSS V17
M13 VSS VSS AE8
M14 VSS VSS V9
M16 VSS VSS J16
M17 VSS Q5
M23 VSS
N2 VSS
N5 VSS 14 SMB_CLK 3 4 SMBC_ICH 3,17,18
N9 VSS
N10 VSS 2 5
2 2
N12 VSS
N13 VSS 1 6 2N7002DW-1-GP
N14 84.27002.D3F
VSS 2ND = 84.27002.E3F
N16 VSS
N17 VSS 14 SMB_DATA
N21 VSS SMBD_ICH 3,17,18
N22 VSS
N25 VSS
P9
P10
VSS
VSS
SMBUS
P12 VSS
P13 VSS
P14 VSS
P16 VSS
P17 VSS
P23 VSS
R5 VSS
R7 VSS
R8 VSS
R9 VSS
R10 VSS
R16 VSS
R17 VSS
R19 VSS
R21 A1 ICH0_NCTF#A1 1 TP19 TPAD14-GP
VSS VSS_NCTF ICH0_NCTF#A25 TP17 TPAD14-GP
R22 VSS VSS_NCTF A25 1
R25 AE1 ICH0_NCTF#AE1 1 TP12 TPAD14-GP
VSS VSS_NCTF ICH0_NCTF#AE25 TP7 TPAD14-GP
T2 VSS VSS_NCTF AE25 1
1 T8 VSS 1
T10 NCTF PIN
VSS
T11 VSS
Wistron Corporation
Dr-Bios.com
T12 VSS
T13 VSS
T14 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
VSS Taipei Hsien 221, Taiwan, R.O.C.
T15 VSS
T16 VSS
T23 Title
VSS
ICH9-M (4 of 4)
ICH9M-1-GP Size Document Number Rev
JM41_UMA -1
A B C D E
A B C D E
DDR3 SOCKET_1
4 4
DM1
9 M_A_A[14..0]
M_A_A0 98 NP1
M_A_A1 A0 NP1
97 A1 NP2 NP2
M_A_A2 96
M_A_A3 A2
95 A3 RAS# 110 M_A_RAS# 9
M_A_A4 92 113 M_A_WE# 9
M_A_A5 A4 WE#
91 A5 CAS# 115 M_A_CAS# 9
M_A_A6 90
M_A_A7 A6
86 A7 CS0# 114 M_CS0# 8
M_A_A8 89 121 M_CS1# 8
M_A_A9 A8 CS1#
85 A9
M_A_A10 107 73 M_CKE0 8
M_A_A11 A10/AP CKE0
84 A11 CKE1 74 M_CKE1 8
M_A_A12 83
M_A_A13 A12
119 A13 CK0 101 M_CLK_DDR0 8
M_A_A14 80 103 M_CLK_DDR#0 8
A14 CK0#
TPAD14-GP TP25 1 M_A_A15 78 A15
9 M_A_BS#2 79 A16/BA2 CK1 102 M_CLK_DDR1 8
CK1# 104 M_CLK_DDR#1 8
9 M_A_BS#0 109 BA0 M_A_DM[7..0] 9
9 M_A_BS#1 108 11 M_A_DM0
BA1 DM0 M_A_DM1
DM1 28
M_A_DQ0 5 46 M_A_DM2
M_A_DQ1 DQ0 DM2 M_A_DM3
9 M_A_DQ[63..0] 7 DQ1 DM3 63
M_A_DQ2 15 136 M_A_DM4
17 DQ3 DM5 153
M_A_DQ4 4 170 M_A_DM6
6 DQ5 DM7 187
M_A_DQ6 16
M_A_DQ7 DQ6 SMBD_ICH
18 DQ7 SDA 200 SMBD_ICH 3,16,18
M_A_DQ8 21 202 SMBC_ICH SMBC_ICH 3,16,18
M_A_DQ9 DQ8 SCL
23 DQ9
M_A_DQ10 33 198 PM_EXTTS#0 8,18
M_A_DQ11 DQ10 EVENT#
35 DQ11
M_A_DQ12 22 199 3D3V_S0
M_A_DQ13 DQ12 VDDSPD
24 DQ13
3 M_A_DQ14 34 197 3
DQ14 SA0
1
M_A_DQ15 36 201 C74
M_A_DQ16 DQ15 SA1
39 DQ16
SCD1U16V2ZY-2GP
M_A_DQ17 41 77
DQ17 NC#1
2
M_A_DQ18 51 122
M_A_DQ19 DQ18 NC#2 1D5V_S3
53 DQ19 NC#/TEST 125
M_A_DQ20 40
M_A_DQ21 DQ20
42 DQ21 VDD1 75
M_A_DQ22 50 76
M_A_DQ23 DQ22 VDD2
52 DQ23 VDD3 81
M_A_DQ24 57 82
M_A_DQ25 DQ24 VDD4
59 DQ25 VDD5 87
M_A_DQ26 67 88
M_A_DQ27 DQ26 VDD6 1D5V_S3
69 DQ27 VDD7 93
M_A_DQ28 56 94
M_A_DQ29 DQ28 VDD8
58 DQ29 VDD9 99
M_A_DQ30 68 100
DQ30 VDD10
1
M_A_DQ31 70 105 C157 C170 C151 C166 C141 C146 TC8
M_A_DQ32 DQ31 VDD11
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
129 DQ32 VDD12 106
ST330U6VDM-2-GP
M_A_DQ33 131 111
DQ33 VDD13
2
M_A_DQ34 141 112
M_A_DQ35 DQ34 VDD14
143 DQ35 VDD15 117
M_A_DQ36 130 118 DY DY DY
M_A_DQ37 DQ36 VDD16
132 DQ37 VDD17 123
M_A_DQ38 140 124
M_A_DQ39 DQ38 VDD18
142 DQ39
M_A_DQ40 147 2
M_A_DQ41 DQ40 VSS
149 DQ41 VSS 3
M_A_DQ42 157 8
M_A_DQ43 DQ42 VSS
159 DQ43 VSS 9
M_A_DQ44 146 13
DQ44 VSS
1
M_A_DQ45
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
148 14 C144 C150 C174 C165
M_A_DQ46 DQ45 VSS
158 DQ46 VSS 19
M_A_DQ47 160 20
DQ47 VSS
2
M_A_DQ48 163 25
M_A_DQ49 DQ48 VSS
165 DQ49 VSS 26
M_A_DQ50 175 31
M_A_DQ51 DQ50 VSS
177 DQ51 VSS 32
M_A_DQ52 164 37
M_A_DQ53 DQ52 VSS
166 DQ53 VSS 38
M_A_DQ54 174 43
M_A_DQ55 DQ54 VSS
2
Layout Note：Near Pin 126 M_A_DQ56
176
181
DQ55 VSS 44
48
2
M_A_DQ57 DQ56 VSS

183 DQ57 VSS 49
M_A_DQ58 191 54
DDR_VREF_S3_1 M_A_DQ59 DQ58 VSS
193 DQ59 VSS 55
M_A_DQ60 180 60
M_A_DQ61 DQ60 VSS
182 DQ61 VSS 61
M_A_DQ62 192 65
C139 M_A_DQ63 DQ62 VSS
194 DQ63 VSS 66
1
VSS 71
M_A_DQS#0
SC1U10V3KX-3GP
C140 10 72
SCD1U16V2ZY-2GP M_A_DQS#1 DQS0# VSS
9 M_A_DQS#[7..0] 27 DQS1# VSS 127
2
M_A_DQS#2 45 128
M_A_DQS#3 DQS2# VSS
62 DQS3# VSS 133
M_A_DQS#4 135 134
M_A_DQS#5 DQS4# VSS
152 DQS5# VSS 138
M_A_DQS#6 169 139
M_A_DQS#7 DQS6# VSS
186 DQS7# VSS 144
VSS 145
M_A_DQS0 12 150
M_A_DQS1 DQS0 VSS
9 M_A_DQS[7..0] 29 DQS1 VSS 151
M_A_DQS2
Layout Note：Near Pin 1 M_A_DQS3
47
64
DQS2 VSS 155
156
M_A_DQS4 DQS3 VSS
137 DQS4 VSS 161
M_A_DQS5 154 162
DDR_VREF_S3_1 M_A_DQS6 DQS5 VSS
171 DQS6 VSS 167
M_A_DQS7 188 168
DQS7 VSS
VSS 172
8 M_ODT0 116 ODT0 VSS 173
C255 8 M_ODT1 120 178
ODT1 VSS
1
VSS 179
SC1U10V3KX-3GP
C254 DDR_VREF_S3_1 126 184

SCD1U16V2ZY-2GP DDR_VREF_S3_1 VREF_CA VSS
1 VREF_DQ VSS 185
2
VSS 189
8,18 DDR3_DRAMRST# 30 RESET# VSS 190
VSS 195
VSS 196
DDR_VREF_S3 203 VTT1 VSS 205
204 VTT2 VSS 206
1
C68 C77
SC10U6D3V5MX-3GP
1 1
SC1U10V3ZY-6GP
2
DDR3-204P-46-GP
62.10017.P11
Dr-Bios.com
2ND = 62.10017.P31
Wistron Corporation
Title
DDR3 Socket1
JM41_UMA -1
A B C D E
A B C D E
DDR3 SOCKET_2
DM2
9 M_B_A[14..0]
M_B_A0 98 NP1
M_B_A1 A0 NP1
4 97 A1 NP2 NP2 4
M_B_A2 96
M_B_A3 A2
95 A3 RAS# 110 M_B_RAS# 9
M_B_A4 92 113 M_B_WE# 9
M_B_A5 A4 WE#
91 A5 CAS# 115 M_B_CAS# 9
M_B_A6 90
M_B_A7 A6
86 A7 CS0# 114 M_CS2# 8
M_B_A8 89 121 M_CS3# 8
M_B_A9 A8 CS1#
85 A9
M_B_A10 107 73 M_CKE2 8
M_B_A11 A10/AP CKE0
84 A11 CKE1 74 M_CKE3 8
M_B_A12 83
M_B_A13 A12
119 A13 CK0 101 M_CLK_DDR2 8
M_B_A14 80 103 M_CLK_DDR#2 8
A14 CK0#
TPAD14-GP TP26 1M_B_A15 78 A15
9 M_B_BS#2 79 A16/BA2 CK1 102 M_CLK_DDR3 8
CK1# 104 M_CLK_DDR#3 8
9 M_B_BS#0 109 BA0 M_B_DM[7..0] 9
9 M_B_BS#1 108 11 M_B_DM0
BA1 DM0 M_B_DM1
DM1 28
M_B_DQ0 5 46 M_B_DM2
M_B_DQ1 DQ0 DM2 M_B_DM3
9 M_B_DQ[63..0] 7 DQ1 DM3 63
M_B_DQ2 15 136 M_B_DM4
17 DQ3 DM5 153
M_B_DQ4 4 170 M_B_DM6
6 DQ5 DM7 187
M_B_DQ6 16
M_B_DQ7 DQ6
18 DQ7 SDA 200 SMBD_ICH 3,16,17
M_B_DQ8 21 202 SMBC_ICH 3,16,17
M_B_DQ9 DQ8 SCL
23 DQ9
M_B_DQ10 33 198 3D3V_S0
DQ10 EVENT# PM_EXTTS#0 8,17
M_B_DQ11 35
M_B_DQ12 DQ11
22 DQ12 VDDSPD 199
M_B_DQ13 24
M_B_DQ14 DQ13
34 DQ14 SA0 197
1
M_B_DQ15 36 201 DDRB_SA1 2 1
M_B_DQ16 DQ15 SA1 R26 C72
39 DQ16
SCD1U16V2ZY-2GP
M_B_DQ17 41 77 10KR2J-3-GP DY
DQ17 NC#1
2
M_B_DQ18 51 122
M_B_DQ19 DQ18 NC#2 1D5V_S3
53 DQ19 NC#/TEST 125
1D5V_S3 M_B_DQ20 40
M_B_DQ21 DQ20
3 42 DQ21 VDD1 75 3
M_B_DQ22 50 76
M_B_DQ23 DQ22 VDD2
52 DQ23 VDD3 81
1
1
C193 C179 C168 C185 C159 C149 M_B_DQ24 57 82
DQ24 VDD4
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
M_B_DQ25 59 87
M_B_DQ26 DQ25 VDD5
67 DQ26 VDD6 88
2
2
M_B_DQ27 69 93
M_B_DQ28 DQ27 VDD7
DY DY M_B_DQ29
56 DQ28 VDD8 94
58 DQ29 VDD9 99
M_B_DQ30 68 100
M_B_DQ31 DQ30 VDD10
70 DQ31 VDD11 105
M_B_DQ32 129 106
M_B_DQ33 DQ32 VDD12
131 DQ33 VDD13 111
M_B_DQ34 141 112
M_B_DQ35 DQ34 VDD14
143 DQ35 VDD15 117
M_B_DQ36 130 118
DQ36 VDD16
1
1
M_B_DQ37
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C392 C206 C145 C383 132 123
M_B_DQ38 DQ37 VDD17
140 DQ38 VDD18 124
M_B_DQ39 142 DQ39
2
2 M_B_DQ40 147 DQ40 VSS 2

M_B_DQ41 149 3
M_B_DQ42 DQ41 VSS
157 DQ42 VSS 8
M_B_DQ43 159 9
M_B_DQ44 DQ43 VSS
146 DQ44 VSS 13
M_B_DQ45 148 14
M_B_DQ46 DQ45 VSS
158 DQ46 VSS 19
M_B_DQ47 160 20
M_B_DQ48 DQ47 VSS
163 DQ48 VSS 25
M_B_DQ49 165 26
M_B_DQ50 DQ49 VSS
175 DQ50 VSS 31
M_B_DQ51
Layout Note：Near Pin 126 M_B_DQ52
177
164
DQ51 VSS 32
37
M_B_DQ53 DQ52 VSS
166 DQ53 VSS 38
M_B_DQ54 174 43
DDR_VREF_S3_1 M_B_DQ55 DQ54 VSS
176 DQ55 VSS 44
M_B_DQ56 181 48
M_B_DQ57 DQ56 VSS
183 DQ57 VSS 49
M_B_DQ58 191 54
C134 M_B_DQ59 DQ58 VSS
193 DQ59 VSS 55
1
M_B_DQ60 180 60
DQ60 VSS
SC1U10V3KX-3GP
C135 M_B_DQ61 182 61

2 SCD1U16V2ZY-2GP M_B_DQ62 DQ61 VSS 2
192 DQ62 VSS 65
2
M_B_DQ63 194 66
DQ63 VSS
VSS 71
M_B_DQS#0 10 72
M_B_DQS#1 DQS0# VSS
9 M_B_DQS#[7..0] 27 DQS1# VSS 127
M_B_DQS#2 45 128
M_B_DQS#3 DQS2# VSS
62 DQS3# VSS 133
M_B_DQS#4 135 134
M_B_DQS#5 DQS4# VSS
152 DQS5# VSS 138
M_B_DQS#6 169 139
M_B_DQS#7 DQS6# VSS
Layout Note：Near Pin 1 186 DQS7# VSS 144
145
M_B_DQS0 VSS
12 DQS0 VSS 150
DDR_VREF_S3_1 M_B_DQS1 29 151
9 M_B_DQS[7..0] DQS1 VSS
M_B_DQS2 47 155
M_B_DQS3 DQS2 VSS
64 DQS3 VSS 156
M_B_DQS4 137 161
C251 M_B_DQS5 DQS4 VSS
154 DQS5 VSS 162
1
M_B_DQS6 171 167

DQS6 VSS
SC1U10V3KX-3GP
C252 M_B_DQS7 188 168

SCD1U16V2ZY-2GP DQS7 VSS
VSS 172
2

VSS 179
DDR_VREF_S3_1 126 184
DDR_VREF_S3_1 VREF_CA VSS
1 VREF_DQ VSS 185
VSS 189
8,17 DDR3_DRAMRST# 30 RESET# VSS 190
VSS 195
VSS 196
DDR_VREF_S3 203 VTT1 VSS 205
204 VTT2 VSS 206
1
C98 C106
SC1U10V3ZY-6GP
SC10U6D3V5MX-3GP
2
DDR3-204P-7-GP-U1
62.10017.F81
2ND = 62.10017.N41
1 1
Dr-Bios.com
Wistron Corporation
Title
DDR3 Socket2
JM41_UMA -1
A B C D E
5 4 3 2 1
LCD/CCD CONN Internal MIC

F1
2 1 DCBATOUT
POLYSW-1D1A24V-GP
DCBATOUT_LCD1 69.50007.A31
2ND = 69.50007.A41
D LCD1 D
1
48 C61 C48
SCD1U16V2ZY-2GP
SC10U35V0ZY-GP
DY
41 50
2
1 F2
1 2 3D3V_S0
2
1
3 C330 C326 FUSE-1D1A6V-4GP-U
SC4D7U10V5ZY-3GP
SCD1U16V2ZY-2GP
4 DBC_EN 28
5 BLON_OUT_R DY 69.50007.691
2
42 6 BRIGHTNESS_CN
7 CCD_PWR 2ND = 69.50007.771
8 USBPN4 14
9 USBPP4 14
10
11
12
43 13 DMIC_CLK 22
14 DMIC_DAT 22
15 3D3V_S0
16
17
18
19
44 20
21
22
23 3D3V_S0
24 GMCH_TXAOUT0- 8
C 25 C
GMCH_TXAOUT0+ 8
26
2
1
45 27 GMCH_TXAOUT1- 8
28 GMCH_TXAOUT1+ 8
29 SRN2K2J-1-GP
30 GMCH_TXAOUT2- 8
31 RN15
GMCH_TXAOUT2+ 8
32
3
4
33 GMCH_TXACLK- 8
46 34 GMCH_TXACLK+ 8
35
36 LCD_EDID_DAT
37 LCD_EDID_CLK
38 3D3V_S0
39 LCDVDD
40 3 2 CLK_DDC_EDID 8
SCD1U16V2ZY-2GP
47 51 4 1 DAT_DDC_EDID 8
SRN0J-10-GP-U
RN16
49
1
C373 C138
IPEX-CONN40-2R-GP
SC10U35V0ZY-GP
DY
2
20.F1093.040
2ND = 20.F1289.040
B B
Layout 40 mil
LCDVDD 3D3V_S0
U9
8 GMCH_LCDVDD_ON 1 R52 2 GMCH_LCDVDD_ON_R 1 5 DY

0R0402-PAD EN IN#5
2 GND 2 1 BRIGHTNESS 28
3 4 R75 0R2J-2-GP
OUT IN#4
1
BLON_OUT_R DY C137
1
C142
SCD1U16V2ZY-2GP
G5285T11U-GP
SB_20090205
2
1
2
1
SC4D7U6D3V3KX-GP
C147
2
RN12 BRIGHTNESS_CN 2 1 L_BKLTCTL 8

74.05285.07F
SC4D7U6D3V3KX-GP
SRN10KJ-5-GP R34 33R2J-2-GP

2
4
3
BLON_OUT_R 2 1 BLON_OUT 28
R148 1KR2F-3-GP
1
C104 C319
SC100P50V2JN-3GP
SC100P50V2JN-3GP
DY DY
2
A <Core Design> A
Wistron Corporation
Dr-Bios.com
Title
LCD CONN
JM41_UMA -1
5 4 3 2 1
A B C D E
CN2
33
22 SPDIF 1
4 2 4
8 HDMI_DATA2+ 3
8 HDMI_DATA2- 4
5
8 HDMI_DATA1+ 6
8 HDMI_DATA1- 7
8
8 HDMI_DATA0+ 9
8 HDMI_DATA0- 10
11
8 HDMI_CLK+ 12
8 HDMI_CLK- 13
14
8 GMCH_RED 15
8 GMCH_GREEN 16
8 GMCH_BLUE 17
18
8 GMCH_HSYNC 19
8 GMCH_VSYNC 20
21
13 SATA_TXP1 22
13 SATA_TXN1 23
24
13 SATA_RXP1 25
13 SATA_RXN1 26
27
14 USBPN1 28
14 USBPP1 29
30
3 31 3
14 USBPN9
14 USBPP9 32
34
ACES-CON32-GP
20.K0289.032
CN3
41
1
8 GMCH_DDCCLK 2
8 GMCH_DDCDATA 3
4
28 CRT_DEC# 5
8 GMCH_HDMI_DATA 6
8 GMCH_HDMI_CLK 7
8 HDMI_DETECT# 8
9
14 USB_OC#1 10
25,26,28 USB_PWR_EN# 11
28 MODEL_ID0 12
28 MODEL_ID1 13
5V_S0 14
15
16
2 2
17
5V_S5 18
19
20
21
28 HDD_PWR_EN# 22
3D3V_S0 23
24
1
EC81 EC43 EC13

SC33P50V2JN-3GP
SC33P50V2JN-3GP
SC33P50V2JN-3GP
25
DY DY DY 26
22 MIC1_JD# 27
2
22 HP_JD# 28
29
30
31
32
33
34
22 HP_OUT_L 35
22 HP_OUT_R 36
37
22 MIC1_IN_L 38
22 MIC1_IN_R 39
AGND 40
42
PTWO-CON40-2-GP
1
-1_20090301 <Core Design> 1
Wistron Corporation
Dr-Bios.com
20.K0410.040
2ND = 20.K0420.040 Taipei Hsien 221, Taiwan, R.O.C.
Title
CRT BD CONN
JM41_UMA -1
A B C D E
SSD SATA Connector
SSD1
16 SB_20090114
S1
S2 SATA_TXP0 13
13 SATA_TXN0 S3
S4
13 SATA_RXN0 S5
S6 SATA_RXP0 13
S7
3D3V_S0
3D3V_S0
P1
P2
P3
1
P4
5V_S0 TC18
DY C447
DY
P5
5V_S0
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
P6
2
P7
P8
P9
P10
1
P11
P12 TC19 C452
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
P13
2
P14
P15
17
SB_20090205
SKT-SATA7P+15P-30-GP
62.10065.911
-1_20090301
<Core Design>
Wistron Corporation
Dr-Bios.com
Title
HDD CONN
JM41_UMA -1
5 4 3 2 1
SB_20090205
5V_S0
U12
1D5V_S0 3D3V_VDDIO_S0
1 5 5VA_S0
EN NC#5 R258 2
2 GND 1
3 4 0R0402-PAD
VIN VOUT
1
C256
D SC1U10V3KX-3GP G9091-475T12U-GP C250 Put C735 Close To CODEC D
SC10U10V5KX-2GP
2
AGND 2 1 AUD_CPVEE
C432 SC2D2U6D3V3MX-1-GP
AGND AGND 5VA_S0 5VP_S0 MIC1_R 1 2 MIC1_IN_R 20

74.09091.F3F C436 SC4D7U10V5ZY-3GP
2ND = 74.09198.A7F 3D3V_VDDIO_S0 MIC1_L 1 2 MIC1_IN_L 20
R110 C438 SC4D7U10V5ZY-3GP
3D3V_S0 1 2 3D3V_AUDIO_S0
0R0603-PAD
25
38
34
39
46
22
21
1
9
U29
SB_20090205 SB_20090205
CPVEE
DVDD_IO
AVDD1
AVDD2
PVDD1
PVDD2
DVDD
MIC1_L
MIC1_R
MIC2_R 17
20 HP_OUT_R 33 HP-OUT_R MIC2_L 16

20 HP_OUT_L 32 HP-OUT_L
LINE2-R 15
LINE2-L 14
20 SPDIF 48 SPDIFO RN35

30 MIC1_VREFO_R 4 1
MIC1_VREFO_R MIC1_VREFO_L
MIC1_VREFO_L 28 3 2
C SENSE_A 13 29 C
SENSE_A MIC2_VREFO
SRN2K2J-1-GP
20 HP_JD# 1 2 18 SENSE_B
R246 39K2R2F-L-GP Alnalog signal 24
LINEOUT1-R
20 MIC1_JD# 2 1 LINEOUT1-L 23
R243 20KR2F-L-GP
19 DMIC_CLK 2 3 DMIC_CLK_R 3
DMIC_DAT_R GPIO1/DMIC-CLK
19 DMIC_DAT 1 4 2 GPIO0/DMIC_DATA SPKL- 41 SPKR_L- 23
Digital signal SPKL+ 40 SPKR_L+ 23
EC74 EC76 RN34 44 SPKR_R- 23
SRN0J-6-GP SPKR-
47 SPDIFO2/EAPD SPKR+ 45 SPKR_R+ 23
1
1
SC22P50V2JN-4GP
SC22P50V2JN-4GP
DY DY
AUD_CBP 36 CBP
2
SDATA_OUT
MONO-OUT
2
C431 AUD_CBN
SDATA_IN
35 CBN
CPVREF
RESET#
BIT-CLK
JDREF
AVSS1
AVSS2
PVSS1
PVSS2
SYNC
SC2D2U10V3ZY-1GP
DVSS
VREF
BEEP
GND
1
PD#
Put C736 Close To CODEC
ALC269X-GR-GP
12
10
6
11
5
8
31
4
20
19
27
26
37
7
49
42
43
RN33
1 4 AUDIO_BEEP 1 2 PCBEEP PGND
14 ACZ_SPKR C443 SCD1U10V2KX-4GP
2 3
ACZ_BITCLK_R
ACZ_SDATAIN0_R
28 EC_BEEP
AUD_PD#
SRN10KJ-5-GP
SC100P50V2JN-3GP
1
1
10KR2J-3-GP
R248 C444
B B
AGND
-1_20090301
2
13 ACZ_SYNC
AGND AUD_VREF
2
13 ACZ_BITCLK 2 R259 1 AUD_JDREF
1
0R0402-PAD DY R228
1
1 2 2 R260 1 ACZ_RST# 13 R239 C430 C433
AGND C445 SC22P50V2JN-4GP 0R2J-2-GP 20KR2F-L-GP
SC10U10V5KX-2GP
SCD1U10V2KX-4GP
1 2
13 ACZ_RST# 1 2 ACZ_SDATAIN0 13 0R3-0-U-GP
2
33R2J-2-GP R257
2
1 2 ACZ_SDATAOUT 13 AGND
AGND AGND
R271
1 2
5V_S0 5VP_S0 3D3V_S0 0R3-0-U-GP
R91
PGND
1 2
0R0603-PAD
1
C281 C273 C286 1 C285

SC10U10V5KX-2GP
SC10U10V5KX-2GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
2
A <Core Design> A
PGND
Wistron Corporation
Dr-Bios.com
Close Pim.39 Close Pim.1 Title
and Pin.46 and Pin.9 AUDIO CODEC REALTEK ALC269
JM41_UMA -1
Date: Tuesday, March 17, 2009 Sheet 22 of 40
5 4 3 2 1
5 4 3 2 1
D D
Internal Speaker
C SPK1 C
5
22 SPKR_L- 1
22 SPKR_L+ 2
22 SPKR_R- 3
22 SPKR_R+ 4
6
ACES-CON4-5-GP
1
1
20.F0866.004
2ND = 20.F1261.004
2
B B
A <Core Design> A
Wistron Corporation
Dr-Bios.com
Title
AUDIO JACK
JM41_UMA -1
5 4 3 2 1
5 4 3 2 1
D D
20.K0289.032
ACES-CON32-GP
34
C 32 C
28 TP_LOCK_LED TP_LOCK_LED 31
13,28 RTC_BAT 30
28 DC_BATFULL DC_BATFULL 29
28 CHARGE_LED CHARGE_LED 28
3D3V_AUX_S5 27
26
14 USBPN7 25
14 USBPP7 24
23
8,14,25,28,29 PLT_RST1# 22
5V_ODD_S0 21
20
19
30 TP_BTN_L 18
30 TP_BTN_R 17
28 TP_LOCK_BTN# 16
15
28 BLUETOOTH_EN 14
3D3V_S0
13
28 LID_CLOSE# 12
1
EC42 EC69 EC16

SC33P50V2JN-3GP
SC33P50V2JN-3GP
SC33P50V2JN-3GP
11
DY DY DY 13 SATA_RXP4 10
13 SATA_RXN4 9
2
8
13 SATA_TXN4 7
13 SATA_TXP4 6
5
14 USBPN11 4
B B
14 USBPP11 3
2
1
33
CN1
<Core Design>
A A
Wistron Corporation
Dr-Bios.com
Title
CARDREADER BD CONN
JM41_UMA -1
5 4 3 2 1
A B C D E
4 4
3D3V_S0
SB_20090115
1
EC15
SC33P50V2JN-3GP
DY
2
BTB1
NP1
5V_S5 2 1
4 3
1
EC44 6 5
SC33P50V2JN-3GP DY 8 7
10 9 3D3V_AUX_S5
2
12 11 RUN_POWER_ON
14 USBPN3 14 13 SMBC_THERM 27,28
1
16 15 EC41
14 USBPP3 SMBD_THERM 27,28
18 17 BAT_IN# 28 DY SC33P50V2JN-3GP
14 USBPN10
14 USBPP10 20 19 BAT_SDA 28
2
22 21 BAT_SCL 28
14 USBPN0 24 23 E51_RxD 28
3 26 25 3
14 USBPP0 E51_TxD 28
28 27 AD_IA 28
3 CLK_PCIE_MINI1# 30 29 AC_IN# 28
3 CLK_PCIE_MINI1 32 31 AD_ON 28
34 33 USB_OC#0 14
14 PCIE_TXN2 36 35 USB_PWR_EN# 20,26,28
14 PCIE_TXP2 38 37 PLT_RST1# 8,14,24,28,29
40 39 WLAN_CLKREQ# 3
14 PCIE_RXN2 42 41 ALL_LED_OFF# 28,31
14 PCIE_RXP2 44 43 MEDIA_INT# 28
46 45 WLAN_TEST_LED 28
14 PCIE_RXN1 48 47 WIRELESS_EN 28
14 PCIE_RXP1 50 49 3G_EN 28
52 51 EJECT_BTN 28
14 PCIE_TXN1 54 53 3V/5V_EN 28,32
14 PCIE_TXP1 56 55 PCIE_WAKE# 14
58 57
31 MEDIA_LED#_R 60 59 CLK_PCIE_LAN 3
3 LAN_CLKREQ# 62 61 CLK_PCIE_LAN# 3
64 63
66 65 3D3V_S5
68 67 1D5V_S0
DCBATOUT 70 69 DCBATOUT
NP2
1
1
EC39 STC-CONN70D-GP-U EC10 EC11
SC33P50V2JN-3GP
SC33P50V2JN-3GP
SC33P50V2JN-3GP DY DY DY
62.10080.031
2
2
2 2
1 <Core Design> 1
Wistron Corporation
Dr-Bios.com
Title
MINI BD CONN
A3 JM41_UMA -1
A B C D E
5 4 3 2 1
D D
-1_20090301
C BTB2 C
11
5V_S5 1
1
EC45
SC33P50V2JN-3GP
31 FRONT_PWRLED#_R 3
DY 28 KBC_PWRBTN#_L 4
5
2
14 USBPN2 6
14 USBPP2 7
8
31 STDBY_LED#_R 9
20,25,28 USB_PWR_EN# 10
12
ACES-CON10-7-GP
20.F0866.010
2ND = 20.F1261.010
B B
A <Core Design> A
Wistron Corporation
Dr-Bios.com
Title
POWER BUTTON CONN

A3 JM41_UMA -1
5 4 3 2 1
5 4 3 2 1
CPU TEMP:
H_THERMDA and H_THERMDC routing 10mil trace width

and spacing. Locate Capacity near thermal diode
for CPU thermal diode 5V_S0
C587 for EMI and
solve acoustic noise
C387
1
4 H_THERMDA H_THERMDA C386
SC4D7U10V5ZY-3GP
SCD1U16V2ZY-2GP
2
2
D D
H_THERMDA C321 1 2 H_THERMDC
SC100P50V2JN-3GP
4 H_THERMDC H_THERMDC
FAN1
EMC2102_DP2 C325 1 2 EMC2102_DN2 5
SC100P50V2JN-3GP 3RD = 84.03904.H11
EMC2102_DP2 2ND = 84.03904.L06 1
CLOSE TO EMC2103 84.T3904.C11
E
FAN_PWM 2
SC22P50V2JN-4GP MMBT3904-4-GP SC22P50V2JN-4GP
1
Q1 B B FAN_TACH 3
MMBT3904-4-GP C62 Q4 C152 4
84.T3904.C11 DY DY
2
C
6
2ND = 84.03904.L06 EMC2102_DN2
3RD = 84.03904.H11 PTWO-CON4-8-GP
for T8 thermal diode for system thermal diode
R144 20.F1396.004
2103_VDD 5V_S0
3D3V_S0 1 2 2ND = 20.F0411.004
1
49D9R2F-GP
C320
SCD1U16V2KX-3GP
2
1
C U25 RN14 C
SRN10KJ-5-GP
3 4 2103_GPIO1 1 TP32 TPAD14-GP
VDD GPIO1 2103_GPIO2 1 TP34 TPAD14-GP
GPIO2 5
H_THERMDA 2 DP1
3
4
H_THERMDC 1 10 FAN_TACH
EMC2102_DP2 DN1 TACH FAN_PWM
16 DP2/DN3 PWM 11 ps. FAN1 POWER TRACE WIDTH MAY BE IN 25 MIL
EMC2102_DN2 15 ND2/DP3 TRIP_SET R1541
TRIP_SET 14 2 787R2F-GP
PURE_HW_SHUTDOWN# 7 13
TPAD14-GP TP38 ALERT# SYS_SHDN# SHDN_SEL SHDN_SEL
1 6 ALERT# 1 2
R159 22KR2F-GP
R158 2 1 0R0402-PAD SMBC_THERM_1 9 12
25,28 SMBC_THERM SMCLK GND
R155 2 1 0R0402-PAD SMBD_THERM_1 8 17
25,28 SMBD_THERM SMDATA GND
SB_20090205 EMC2103-2-AP-GP
SA
Channel 1: CPU 74.02103.A73
Channel 2: Palmrest
3D3V_S0 3D3V_S0
Channel 3: T8
1
R43 Q3
G
10KR2J-3-GP
B B
2
PURE_HW_SHUTDOWN#
SHDN_SEL TRIP_SET S D RSMRST# 28,32
PULL UP Ttrip(degree) RSET(1%)

RESISTOR MODE OF OPERATION 2N7002-11-GP
84.27002.W31
2ND = 84.27002.Y31
<=4.7K OHM EXTERNAL DIODE 1 SIMPLE MODE-BETA 85 562
COMPENSATION DISABLED,REC DISABLED
86 604
6.8K OHM EXTERNAL DIODE 1 DIODE MODE-BETA 87 649
COMPENSATION DISABLED,REC ENABLED
88 698
10K OHM EXTERNAL DIODE 1 TRANSISTOR MODE-BETA 89 750
COMPENSATION ENABLED,REC ENABLED
90 787
15K OHM INTERNAL DIODE 91 845
92 909
22K OHM EXTERNAL DIODE 2 TRANSISTOR MODE-BETA 93 953
COMPENSATION ENABLED,REC ENABLED
94 1020
>=33K OHM EXTERNAL DIODE 1 TRANSISTOR MODE-BETA 95 1100
A
COMPENSATION ENABLED,REC ENABLED <Core Design> A
Wistron Corporation
Dr-Bios.com
Title
Thermal/Fan Controllor
JM41_UMA -1
5 4 3 2 1
A
3D3V_AUX_S5 3D3V_S0 3D3V_S0 3D3V_AUX_S5
DY
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1
1
EC21 C263 C260 C257 C427 C282 C278 C426
1
SRN4K7J-10-GP
SCD1U16V2ZY-2GP
8
7
6
5
2
RN9
2
DY
3D3V_AUX_S5
1
2
3
4
C555,C556 colse to Pin VDD R98
3D3V_AUX_S5_KBC 2 1
BAT_SCL SMBC_THERM
BAT_SDA SMBD_THERM 0R0402-PAD
SCD1U16V2ZY-2GP
SC1U16V3ZY-GP
1
4
C277 EC25 4
C283 DY
SCD1U16V2ZY-2GP
DY
2
3D3V_S0
R226
1 2 PLT_RST1#_1
8,14,24,25,29 PLT_RST1#
100R2J-2-GP
3D3V_S0
25 BAT_IN# X3
SC27P50V2JN-2-GP
1
C428
102
115
U13A
80
19
46
76
88
4
1
1 OF 2 3 2
2
C258 C253
GPIO41
VDD
AVCC
VCC
VCC
VCC
VCC
VCC
10KR2J-3-GP 1 R101 2 E51_RxD SC7P50V2DN-2GP SC7P50V2DN-2GP
1KBC_XO_R2
2
DY
4 1
124 GPIO10/LPCPD# VREF 104 2 R217 1 10KR2J-3-GP
10KR2J-3-GP 1 R100 2 E51_TxD 7 LRESET#
DY 3 PCLK_KBC 2 LCLK A/D GPI90/AD0 97 AD_IA 25 X-32D768KHZ-40GPU 82.30001.841 DY
3 98 TP_LOCK_BTN# 24 2ND = 82.30001.A41
13,29 LPC_LFRAME# LFRAME# GPI91/AD1
2
2 OF 2
33KR2J-3-GP
126 99 U13B
13,29 LPC_LAD0 LAD0 GPI92/AD2
R87 127 100 VR_PWRGD 14,32,34 R77
13,29 LPC_LAD1 LAD1 GPI93/AD3
10KR2J-3-GP 1 R99 2 E51_TxD SC4D7P50V2CN-1GP DY 0R2J-2-GP 13,29 LPC_LAD2 128 108 MEDIA_INT# 25 R76
LAD2 GPIO05 KBC_XI KCOL1
C269 13,29 LPC_LAD3 1 LAD3 LPC GPIO04 96 S0_PWR_GOOD 32 1 2 77 32KX1/32KCLKIN KBSOUT0/JENK# 53
2
14 INT_SERIRQ 125 52 KCOL2
SERIRQ KBSOUT1/TCK
1 2PCLK_KBC_RC 1
14 PM_CLKRUN# 8 GPIO11/CLKRUN#
20MR3-GP
KBSOUT2/TMS 51 KCOL3
DY 13 KBRCIN# 122 50 KCOL4
KBRST# KBC_XO KBSOUT3/TDI KCOL5
13 KA20GATE 121 GA20 GPI94 101 79 32KX2 KBSOUT4/JEN0# 49
R219 ECSCI#_KBC 29 105 PCB_VER0 30 48 KCOL6
BLON_IN ECSCI#/GPIO54 GPI95 PCB_VER1 GPIO55/CLKOUT KBSOUT5/TDO KCOL7
8 GMCH_BL_ON
2 1 9
ECSWI#_KBC 123 GPIO65/SMI# D/A GPI96 106
107 63
KBSOUT6/RDY# 47
43 KCOL8
GPIO67/PWUREQ# GPI97 CRT_DEC# 20 25,31 ALL_LED_OFF# GPIO14/TB1 KBSOUT7 KCOL9
0R0402-PAD
TP28 1
14 PM_PWRBTN#
CHG_ON#
117
31
GPIO20/TA2 KBC KBSOUT8 42
41 KCOL10
GPIO56/TA1 KBSOUT9 KCOL11
22 EC_BEEP
32 GPIO15/A_PWM KBSOUT10 40
KCOL12
THERMAL-----> 25,27 SMBD_THERM 68 GPIO74/SDA2 GPIO01/TB2 64
KBC_PWRBTN#
PM_SLP_S3# 14,32,35 TPAD14-GP 14 EC_TMR 118 GPIO21/B_PWM KBSOUT11 39
KCOL13
25,27 SMBC_THERM 67
69
GPIO73/SCL2 SMB GPIO03 95
93
19 BRIGHTNESS 62 GPIO13/C_PWM KBSOUT12/GPIO64 38
37 KCOL14
25 BAT_SDA GPIO22/SDA1 GPIO06 AC_IN# 25 KBSOUT13/GPIO63
LID_CLOSE# KCOL15
BATTERY-----> 25 BAT_SCL 70 GPIO17/SCL1 GPIO07 94
119 SB_ID LID_CLOSE# 24 KBSOUT14/GPIO62 36
35 KCOL16
GPIO23 KBSOUT15/GPIO61/XOR_OUT
GPIO24 6 TPAD14-GP TP29 1ENERGY_DET_KBC 13 GPIO12/PSDAT3 GPIO60/KBSOUT16 34 KCOL17
109 3D3V_AUX_S5 12 33 KCOL18
GPIO30 3G_EN 25 GPIO25/PSCLK3 GPIO57/KBSOUT17
3
81 GPIO66/G_PWM SP GPIO31 120
65
MODEL_ID0 20 32 ODD_PWR_EN# 11
10
GPIO27/PSDAT2
3
GPIO32/D_PWM PWRLED 31 25 EJECT_BTN GPIO26/PSCLK2

66 STDBY_LED 31 30 TPDATA 71 54 KROW1
GPIO33/H_PWM GPIO35/PSDAT1 KBSIN0
1
10KR2J-3-GP
KROW2
3D3V_S0 84
GPIO40/F_PWM 16
17 AD_OFF R267
30 TPCLK 72 GPIO37/PSCLK1 PS/2 KBSIN1 55
56 KROW3
R227 24 BLUETOOTH_EN GPIO77 GPIO42/TCK KBSIN2 KROW4
DBC_EN 19 DBC_EN 83 GPIO76/SHBM SPI GPIO43/TMS 20 RSMRST#_KBC 14 KBSIN3 57
KROW5
1 2
KA20GATE 1
R163
2
25 WIRELESS_EN 82
91
GPIO75 GPIO GPIO44/TDI 21
22
PM_SLP_S4# 14,32,36,37
86
KBSIN4 58
59 KROW6
25 WLAN_TEST_LED GPIO81 GPIO45/E_PWM CHARGE_LED 24 29 SPIDI F_SDI KBSIN5
2
23 HDD_PWR_EN# 20 29 SPIDO 87 60 KROW7
10KR2J-3-GP GPIO46/TRST# F_SDO KBSIN6 KROW8
8K2R2J-3-GP
GPIO47 24
25
MODEL_ID1 20 29 SPICS# 90
92
F_CS0# FIU KBSIN7 61
3D3V_AUX_S5 GPIO50/TDO SPI_WP# 29 29 SPICLK F_SCK
E51_TxD 111 26 TP_LOCK_LED 24
R95 25 E51_TxD GPO83/SOUT_CR/BADDR1 GPIO51
E51_RxD 113 27 BLON_OUT 19 LID_CLOSE# 85 ECRST#
SB_ID 25 E51_RxD GPIO87/SIN_CR GPIO52/RDY# UMA_DISCRETE# VCC_POR#
1 2 112 GPO84/BADDR0 GPIO53 28
GPIO70 73
10KR2J-3-GP 24 DC_BATFULL 114 GPIO16 GPIO71 74
BAT_IN# 1 R223
100KR2J-1-GP
2
25,32 3V/5V_EN 2 1 S5_ENABLE
14
15
GPIO34
GPIO36
GPIO72
GPO82/TRIS#
75
110 USB_PWR_EN# 20,25,26
-1_20090303 WPCE773LA0DG-GP
BLON_IN 1 R222 2 UMA_DISCRETE# 1 R218 2

R214 10KR2J-3-GP
SER/IR
3D3V_S0 RN32
100KR2J-1-GP 10KR2J-3-GP
VCORF 44 3D3V_AUX_S5 5 4 ECRST#
DY VCORF S5_ENABLE 6 3
1
MEDIA_INT#
-1_20090303 7 2 C265
1
AGND
10KR2J-3-GP
3D3V_S0 8 1 KBRCIN#
GND
GND
GND
GND
GND
GND
SC1U10V3KX-3GP
C425 R274
2
SCD1U16V2ZY-2GP Q11
SRN10KJ-6-GP
2
WPCE773LA0DG-GP 3D3V_S0 MMBT3906-4-GP
103
5
18
45
78
89
116
3D3V_AUX_S5 B
27,32 RSMRST#
2
71.00773.00G
84.T3906.A11
C
1
1
10KR2J-3-GP
2ND = 84.03906.F11
R272 R275 3D3V_AUX_S5 3RD = 84.03906.P11
100KR2J-1-GP EJECT_BTN
D5
A
2
2
6 1 ECSCI#_KBC
AD_OFF 14 ECSCI#_1 D14
RB751V-40-2-GP
5 2 83.R2004.B8F
1
TP_LOCK_BTN#
AD_ON_R1 K
R225 2ND = 83.R0304.A8F 3D3V_S0
SC1U10V2KX-1GP ECSWI#_KBC
2 2
14 ECSWI# 4 3
2
GREEN ADAPTER CIRCUIT
1
10KR2J-3-GP
10KR2J-3-GP
SDM03MT40A-7-F-GP R254 R252
PlanarID
83.R3004.A8E
-1_20090303 DY
SA: 0,0
2
2ND = 83.R2002.B8E 2ND = 84.00610.C31
83.2R004.081 SB: 0,1
2
84.S0610.B31 470R2J-2-GP PCB_VER0
Q7 SDM20E40C-7-F-GP R221 PCB_VER1
NDS0610-NL-GP R220
-1: 1,0
Internal KeyBoard
2
1
AD_ON_R AD_ON
10KR2J-3-GP
10KR2J-3-GP
13,24 RTC_BAT S D AD_ON_RD 1
3 1 2 AD_ON 25
R255 R253 -1M: 1,1
470R2J-2-GP DY
Connector
1
D16
D
1
1
R209 C423
G
2
47KR2J-2-GP SC1U10V3KX-3GP Q9 R212
2N7002-11-GP 100KR2J-1-GP
2
AD_OFF G 84.27002.W31
2
2ND = 84.27002.Y31
2
KB1
S
ACES-CON26-3GP
20.K0256.026 3D3V_AUX_S5 3D3V_AUX_S5 3D3V_AUX_S5
2ND = 20.K0331.026
27
28
D13
R216
2
2 1 KBC_PWRBTN#_L1 K A
47KR2J-2-GP
1
R90 1 2
RB751V-40-2-GP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
R89 47KR2J-2-GP R224 0R2J-2-GP

47KR2J-2-GP 83.R2004.B8F
DY
1
Q13 2ND = 83.R0304.A8F

KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7
KROW8
1 6 KBC_PWRBTN#
2
2 5 KBC_PWRBTN#_L
KBC_PWRBTN#_L 26
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KCOL17
KCOL18
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KBC_PWRBTN_L 3 4
1
1
2N7002EDW-GP G47
84.27002.F3F EC24 GAP-OPEN
2ND = 84.27002.G3F SC1KP50V2KX-1GP
2
DY
1 1
2
1
C272
SC1KP50V2KX-1GP
2
MB PIN DEFINE 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 DY
Dr-Bios.com
KB PIN DEFINE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 <Core Design>
Wistron Corporation
K/B
Title
24 1 KBC WPC773
A2
JM41_UMA -1
Date: Monday, March 16, 2009 Sheet 28 of 40
A
A B C D E
3D3V_AUX_S5
SCD1U16V2ZY-2GP
1
EC46
8
7
6
5
DY
RN28
2
4 SRN3K3J-1-GP 3D3V_AUX_S5 4
1
2
3
4
SPI_HOLD#
U28
28 SPICS# 1 CS# VCC 8

28 SPIDI 2 R213 1 SPI_DI 2 7 SPI_HOLD#
33R2J-2-GP SPI_WP# SO/SIO1 HOLD#
28 SPI_WP# 3 WP#/ACC SCLK 6 SPICLK 28
4 GND SI/SIO0 5 SPIDO 28
1
EC53
DY MX25L1605DM2I-12G-GP
1
EC54 EC55
SC4D7P50V2CN-1GP
72.25165.A01
2
2ND = 72.25X16.A01 DY DY
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
3RD = 72.25016.A01
2
3 3
16M Bits
SPI FLASH ROM
GOLDEN FINGER FOR DEBUG BOARD
2 2
LPC_LAD0 1 TP58 TPAD30-1-GP

13,28 LPC_LAD0
13,28 LPC_LAD1
13,28 LPC_LAD2
13,28 LPC_LAD3
13,28 LPC_LFRAME# LPC_LFRAME# 1 TP56 TPAD30-1-GP
PLT_RST1# 1 TP54 TPAD30-1-GP
8,14,24,25,28 PLT_RST1# PCLK_FWH TP57 TPAD30-1-GP
3 PCLK_FWH 1
PCLK_FWH
<Core Design>
1
1
DY EC50
SC5P50V2CN-2GP Wistron Corporation 1
2
A
Dr-Bios.com B C
Title
Size
Date:
Document Number
BIOS
JM41_UMA
Thursday, March 05, 2009
D
Sheet 29
E
of
Rev
40
-1
5 4 3 2 1
TOUCH PAD
5V_S0 5V_S0
1
1
2
EC64 EC65
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
D RN31 DY DY D
2
SRN10KJ-5-GP
TP1
4
3
7
28 TPCLK 2 3 TP_CLK 2
28 TPDATA 1 4 TP_DATA 3
24 TP_BTN_L 4
RN10 24 TP_BTN_R 5
SRN33J-5-GP-U 6
8
ACES-CON6-12-GP
1
20.K0358.006
EC62 EC61
2
SC100P50V2JN-3GP
SC100P50V2JN-3GP
DY DY
C C
B B
<Core Design>
A A
Wistron Corporation
Dr-Bios.com
Title
Touch PAD
JM41_UMA -1
5 4 3 2 1
5 4 3 2 1
D D
3
Q14
DTC143ZUB-GP
84.00143.G1K
R2
2ND = 84.00143.E1K
1R1
1 2 FRONT_PWRLED#_R FRONT_PWRLED#_R 26
28 PWRLED R112
FRONT_PWRLED# 150R2F-1-GP
-1_20090301
3
Q15
DTC143ZUB-GP
84.00143.G1K
R2
2ND = 84.00143.E1K
1R1
C C
1 R273 2 STDBY_LED#_R STDBY_LED#_R 26

28 STDBY_LED
STDBY_LED# 150R2F-1-GP
13 MEDIA_LED#
3D3V_S0
1
R73
10KR2J-3-GP
Q6
2
R2
2
25,28 ALL_LED_OFF# 1
MEDIA_LED#_Q MEDIA_LED#_R
R1
3 1 2 MEDIA_LED#_R 25
R71 100R2J-2-GP
B DTC143ZUB-GP B
84.00143.G1K
2ND = 84.00143.E1K
A <Core Design> A
Wistron Corporation
Dr-Bios.com
Title
LED
JM41_UMA -1
5 4 3 2 1
ODD Power
Run Power
5V_S0 5V_S5
3D3V_AUX_S5 5V_S0 5V_ODD_S0 DCBATOUT U23
1 S D 8
2ND = 84.00610.C31 2 S D 7
84.S0610.B31 3 S D 6
Q12 G D
4 5
2
NDS0610-NL-GP RUN_POWER_ON
R117 R104 AO4468-GP
100KR2J-1-GP U22 1 2 Z_12V S D
84.04468.037
1
5 1 10KR2J-3-GP
IN OUT
K
1
1
2 R88 C262
GND
G
R85 D7
SCD22U25V3KX-GP
4 3
10KR2J-3-GP
28 ODD_PWR_EN# EN# NC#3 R103 PDZ9D1B-GP
2
Z_12V_G3 83.9R103.C3F
330KR2J-L1-GP
1 2
2
1
G5240B2T1U-GP-U 2ND = 83.9R103.F3F
A
2
1
C294 74.05240.B7F 330KR2J-L1-GP
DUMMY-C3 2ND = 74.09711.07F R83
100KR2J-1-GP
Z_12V_D4
2
2
1D5V_S3
1D5V_S0
Q10
U6
1 S D 8
Z_12V_D3
4 3 2 S D 7
3 S D 6
5 2 4 G D 5
PM_SLP_S3# 14,28,35
6 1 AO4468-GP
84.04468.037
2N7002DW-1-GP
84.27002.D3F
2ND = 84.27002.E3F
3D3V_AUX_S5
3
R47 D2
10KR2J-3-GP BAS16-1-GP
DY 2ND = 83.00016.K11
3RD = 83.00016.F11
2
83.00016.B11
3D3V_S5 U18
B 1 S3_PWRGD 36
5 VCC
A 2 PM_SLP_S4# 14,28,36,37 RSMRST# 27,28
8 SM_PWROK 1 2 SM_PWROK_R 4 Y
GND 3
2
1
R93 12K1R2F-L1-GP
74LVC1G08GW-1-GP DY C128
R96 73.01G08.L04 SCD1U16V2ZY-2GP
2
10KR2J-3-GP 2nd = 73.01G08.L03
1D05V_S0
1
2
DY R215
56R2J-4-GP
1
PM_THRMTRIP-A# 4,8,13
3D3V_S5 U19
B 1 S0_PWR_GOOD 28
5 VCC
E
2 VR_PWRGD_R 2 1
A R97 VR_PWRGD 14,28,34 H_PWRGD#
8,14 PWROK 4 Y 4,13 H_PWRGD 1 2 B
3 10KR2J-3-GP Q8
GND R32 MMBT2222A-3-GP
D8
C
1
74LVC1G08GW-1-GP 1 BAS16-1-GP 1KR2J-1-GP 84.02222.V11
73.01G08.L04 C424 2ND = 84.02222.R11
2nd = 73.01G08.L03 3 SC2D2U16V3KX-GP 3RD = 84.02222.S11
PM_SLP_S3# 14,28,35
2
2 83.00016.B11
2ND = 83.00016.K11
3RD = 83.00016.F11
2
3 RSMRST# 27,28
25,28 3V/5V_EN 1
<Core Design>
D6 BAS16-1-GP
Dr-Bios.com
83.00016.B11
2ND = 83.00016.K11
3RD = 83.00016.F11 Wistron Corporation
Title
RUN & ODD POWER
JM41_UMA -1
5 4 3 2 1
CPU_CORE
ISL6261A RT8202 RT8202
1D05V_S0 1D5V_S3
VID Setting Output Signal
VID0
VID0(I / 3.3V) VR_PWROK DCBATOUT_8202_1D05V 1D05V_S0 (10A) DCBATOUT_8202_1D5V 1D5V_S3 (11A)
PGOOD VIN 1D5V(O) VIN 1D5V(O)
D
VID1 D
VID1(I / 3.3V)
VID2 PM_SLP_S3# CPUCORE_ON PM_SLP_S4# CPUCORE_ON
VID2(I / 3.3V) EN PGOOD EN PGOOD
VID3
VID3(I / 3.3V)
Output Power
VID4
VID4(I / 3.3V) VCC_CORE(Imax=18A)
VCC_CORE_PWR(O)
VID5
VID5(I / 3.3V)
VID6 GFX_CORE
VID6(I / 3.3V) RT9026 0D9V_S0
ISL6263A 5V_S5
Input Signal VIN
CPUCORE_ON VID Setting Output Signal 1D5V_S3 0D75V_S3 (1.2A)
EN (I / 3.3V) VID0 CPUCORE_ON VLDOIN VTT
VID0(I / 3.3V) PGOOD
C C
VID1 PM_SLP_S4#
Voltage Sense VID1(I / 3.3V) S3 0D75V_S3_1
VTTREF
VCC_SENSE VID2
VSEN(I / Vcore) VID2(I / 3.3V) S5
VSS_SENSE VID3
RGND(I / Vcore) VID3(I / 3.3V)
VID4
VID4(I / 3.3V)
Input Power
Input Power Output Power
DCBATOUT_6261A 5V_S0
VCC(I) VDD Charger MAX8731A
VCC_GFXCORE(7A)
5V_S0 DCBATOUT_6263A VGFXCORE (O)
VCC(I) VIN
Input Signal Output Signal
3D3V_S0
VCC(I) CHG_ON# AC_IN#
B Input Signal CHGEN# ACGOOD# B
PM_SLP_S3#
VR_ON AD_IA
24750_CELLS SRSET
GFXVR_EN CELLS
TPS51125 VCC_AXG_SENSE
Voltage Sense
VSEN(I / Vcore) Input Power Output Power
5V/3D3V
VSS_AXG_SENSE
RGND(I / Vcore) AD+ BT+
Input Power Output Power ACN VOUT (O)
DCBATOUT_51125 5V_S5 (6A)
VIN 5V(O) VOUT (O) DCBATOUT
Adapter
Input Signal 3D3V_S5 (5A) Input Signal Output Signal
S5_ENABLE 3D3V(O) AD_IN# <Core Design>
EN0 AD_OFF (I) (O)
5V_AUX_S5
Wistron Corporation
A A
5V(O)
Output Signal 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
ALW_PWRGD_3V_5V Input Power Output Power Taipei Hsien 221, Taiwan, R.O.C.
PGOOD 3D3V_AUX_S5
3D3V(O) AD_JK AD+ Title
VCC(I) VCC(O)
Power Sequence Logic
Dr-Bios.com
5V_AUX_S5 Size Document Number Rev
VCC(I) B
JM41_UMA -1
5 4 3 2 1
5 4 3 2 1
SB_20090205
3D3V_S0
D D
DCBATOUT DCBATOUT_6261A 1 R23 2 0R0402-PAD H_DPRSTP# 4,8,13
G4 1 R31 2 499R2F-2-GP PM_DPRSLPVR 8,14
1 2
1
1 R30 2 0R0402-PAD CPUCORE_ON 35
GAP-CLOSE-PWR R24
G6 10R2F-L-GP
1 2
2
GAP-CLOSE-PWR
H_VID[6..0] 5
1
G8 6261A_VID0 0R0402-PAD 2 R18 1 H_VID0
1 2 R25 6261A_VID1 0R0402-PAD 2 R20 1 H_VID1
1
1
1K91R2F-1-GP C54 6261A_VID2 0R0402-PAD 2 R22 1 H_VID2
TC16 GAP-CLOSE-PWR 6261A_VID3 0R0402-PAD 2 R21 1 H_VID3
DCBATOUT_6261A
ST15U25VDM-1-GP
G10 6261A_VID4 0R0402-PAD 2 R27 1 H_VID4
SCD1U10V2KX-5GP
2
6261A_PWRGOOD 2
2
1 2 6261A_VID5 0R0402-PAD 2 R28 1 H_VID5
6261A_VID6 0R0402-PAD 2 R29 1 H_VID6
GAP-CLOSE-PWR
G2
6261A_AGND
1
1 2 C310 C309 C27 C29
5
6
7
8
6261A_CORE_ON
6261A_DPRSTP#
6261A_DPRSLP
GAP-CLOSE-PWR U2 84.08692.037
SC4D7U25V5MX-1GP
SC4D7U25V5MX-1GP
6261A_3V3
SC4D7U25V5MX-1GP
D
D
D
D
SCD1U50V3KX-GP
2
2
R19 FDMS8692-GP
6261A_VID6
6261A_VID5
6261A_VID4
6261A_VID3
14,28,32 VR_PWRGD 1 2 2ND = 84.01426.037
0R0402-PAD
G
S
S
S
4
3
2
1
40
39
38
37
36
35
34
33
32
31
U4 84.07672.037
3V3
CLK_EN#
DPRSTP#
VID6
VID5
VID4
VID3
PGOOD
DPRSLPVR
VR_ON
2ND = 84.01712.037
6261A_AGND 41 GND_T
C 30 6261A_VID2 C
VID2
5
6
7
8
5
6
7
8
6261A_DPRSLP 1 84.07672.037
FDE
D
D
D
D
D
D
D
D
29 6261A_VID1 U7 U5
VID1
DY C43 R17
FDMS7672-GP
FDMS7672-GP
6261A_PMON_R 6261A_PMON
2ND = 84.01712.037
6261A_AGND 1 2 1 DY 2 2 PMON 6261A_VID0
VID0 28
SC1KP50V2KX-1GP 40K2R2F-GP
2 6261A_RBIAS
G
S
S
S
G
S
S
S
1 3 RBIAS 5V_S0
6261A_AGND R16 147KR2F-GP
4
3
2
1
4
3
2
1
VCCP 27 1 2
C38
4 VR_TT# SC4D7U10V5ZY-3GP Iomax=18A
6261A_LGATE
5 NTC
LGATE 26
OCP>=27A
C34 VCC_CORE
SB_20090114 6261A_AGND 1 2 6261A_SOFT 6 SOFT
VSSP 25
L9 R118
SCD015U25V3KX-GP 24 6261A_PHASE 1 2 VCC_CORE_R 1 2
6261A_VO PHASE
1 R15 2 6261A_OCSET 7 OCSET
14K7R2F-L-GP
IND-D36UH-9-GP D003R3720F-1-GP-U
1
1 R14 2 6261A_VW 8 VW UGATE 23 6261A_UGATE 68.R3610.20C TC1 TC3
2ND = 68.R3610.20A
C30
2
6K81R2F-1-GP R13
SE330U2VDM-L-GP
SE330U2VDM-L-GP
CYNTEC 1.5uH 79.33719.L01
2
C24 6261A_COMP 9 22 BOOT 1 2BOOT_R 1 2 2ND = 77.C3371.051
1 2
COMP BOOT Idc=9A 6.5*6.9*3 G58 G59
0R5J-6-GP SCD22U50V5KX-3GP DCR=14mOhm
GAP-CLOSE-PWR
GAP-CLOSE-PWR
SC1KP50V2KX-1GP 79.33719.L01
DROOP
10 FB NC#21 21 6261A_AGND
1
VDIFF
VSUM
2ND = 77.C3371.051
VSEN
VDD
RTN
DFB
VSS
VIN
VO
ISL6261ACRZ-T-GP
11
6261A_VSEN 12
13
6261A_DROOP 14
15
16
17
18
19
20
B 6261A_FB R7 B
6261A_RTN
5V_S0_ISL6261 1
6261A_DFB
1 2 2
6261A_VO
5V_S0
C19 R11 R12 C16 2D2R5F-2-GP
6261A_SUM_R
1 26261A_FB_R 1 2 1 2 SC1U10V3KX-3GP
U33_VDIFF_1
1
1KR2F-3-GP
SC120P50V3JN-GP 330KR2F-L-GP 1 2 6261A_AGND TC5 TC6
C14 SCD1U25V3ZY-1GP
2
C21 R10 C18
SE330U2VDM-L-GP
SE330U2VDM-L-GP
1 2 1 2U33_VDIFF_2 1 2 6261A_VIN 2 1 DCBATOUT_6261A 79.33719.L01
R8 10R3J-3-GP 2ND = 77.C3371.051
SC82P50V2JN-3GP 1K58R3F-GP SC1200P50V2KX-1GP
R4
79.33719.L01
6261A_SUM 1 2 2ND = 77.C3371.051
5 VCORE_VCCSENSE 1 R1 2 100R2F-L1-GP-U
1
0R0603-PAD
C10
1
SC180P50V2JN-1GP
R2
2
C15
SCD01U25V2KX-3GP 1 2 6261A_VO_R
2
5 VCORE_VSSSENSE 1 R3 2 0R2J-2-GP
0R0603-PAD R6
1
SCD01U25V2KX-3GP
1KR2F-3-GP C302
SCD1U25V3ZY-1GP
2
G60
2
2
1
R5 C13 C11 C12 1 2

1
100R2J-2-GP SCD01U25V2KX-3GP
SC330P50V2KX-3GP
GAP-CLOSE-PWR
2
6261A_AGND
1
R9
249R2F-GP 6261A_AGND
2
A 6261A_AGND 6261A_AGND A
Dr-Bios.com
<Core Design>
Wistron Corporation
SB_20090203 Taipei Hsien 221, Taiwan, R.O.C.
Title
ISL6261A_CPU CORE
Custom
JM41_UMA -1
Date: Wednesday, March 11, 2009 Sheet 34 of 40
5 4 3 2 1
5 4 3 2 1
DCBATOUT DCBATOUT_8202_1D05V
G55
1 2 1D05V_PWR 1D05V_S0
D G44 D
GAP-CLOSE-PWR 1 2
G56
1 2 GAP-CLOSE-PWR
G43
GAP-CLOSE-PWR 1 2
G57
1 2 GAP-CLOSE-PWR
G45
1
TC14 DY GAP-CLOSE-PWR 1 2
G54
GAP-CLOSE-PWR
ST15U25VDM-1-GP
1 2
2 G46
GAP-CLOSE-PWR 1 2
G53 DCBATOUT_8202_1D05V
1 2 GAP-CLOSE-PWR
G41
GAP-CLOSE-PWR 1 2
G52
1 2 GAP-CLOSE-PWR
1
G39
GAP-CLOSE-PWR C442 C280 C276 1 2
5
6
7
8
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
1
2
U20 GAP-CLOSE-PWR
D
D
D
D
FDMS8692-GP G38
1 2
84.08692.037 GAP-CLOSE-PWR
G37
G
S
S
S
5V_S5
C
Iomax=10A 1 2 C
4
3
2
1
OCP>15A GAP-CLOSE-PWR
1
G42
R113 RT8202_DH_1D05V 1D05V_PWR
10R2F-L-GP L13 Vout=1.0515V 1 2
RT8202_LX_1D05V 1 2 GAP-CLOSE-PWR
5V_S5 IND-1D5UH-34-GP G40
2
68.1R510.10J 1 2
2ND = 68.1R51A.10G
DCBATOUT_8202_1D05V
1
1
C274 GAP-CLOSE-PWR
RT8202_VDD_1D05V
5
6
7
8
1
C292 83.00521.01F D15 TC13
SCD1U10V2KX-4GP
1
D
D
D
D
SC1U10V3KX-3GP 2ND = 83.R2003.F8F CH521S-30-GP-U1 U14 R109
2
2
3D3V_S5 R115 3RD = 83.R2003.J8F C291 4K02R3F-GP
SE330U2VDM-L-GP
FDMS7672-GP
1 2 RT8202_TON_1D05V 5V_S5 SC47P50V2JN-3GP 79.33719.L01
2
84.07672.037 2ND = 77.C3371.051
RT8202_BST_1D05V
2
1
820KR2F-GP C293
R107 SC1KP50V2KX-1GP RT8202_FB_1D05V
G
S
S
S
1
10KR2J-3-GP
SB_20090203
2
4
3
2
1
1
C287
SC1U10V3KX-3GP RT8202_DL_1D05V R111
2
2 R108 1 10KR3F-L-GP
34 CPUCORE_ON
2
0R0402-PAD U21 1 2 RT8202_LX_1D05V

1
VDDP
VDD
2
C288 DY R265 C448
SC100P50V2JN-3GP 16 13 RT8202_BST_1D05V_L1 2 SCD1U25V3KX-GP
TON BOOT
2
RT8202_PGOOD_1D05V 4 12 RT8202_DH_1D05V 1R2F-GP

PGOOD UGATE RT8202_LX_1D05V
PHASE 11
8 RT8202_DL_1D05V
B LGATE R264 B
14,28,32 PM_SLP_S3# 1 R116 2 RT8202_EN_1D05V 15 EN/DEM
OC 10 RT8202_OC_1D05V 1 2 RT8202_LX_1D05V Vout=0.75*(1+Rh/Rl)
1
0R0402-PAD 3 RT8202_FB_1D05V
C295 FB
5 NC#5 4K02R2F-GP
SCD1U25V3KX-GP 1D05V_PWR
DY 14 NC#14 VOUT 1
2
PGND
GND
GND
SB_20090205 SB_20090203
RT8202APQW-GP
7
17
6
A <Core Design> A
Wistron Corporation
Dr-Bios.com
Title
RT8202_1D05V
A3
JM41_UMA -1
5 4 3 2 1
5 4 3 2 1
DCBATOUT DCBATOUT_8202_1D5V 1D5V_PWR 1D5V_S3

G20
D G1 1 2 D
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR G19
G3 1 2
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR G15
G5 1 2
1 2
1 GAP-CLOSE-PWR
TC15 DY GAP-CLOSE-PWR G13
G7 DCBATOUT_8202_1D5V 1 2
ST15U25VDM-1-GP
1 2
2
GAP-CLOSE-PWR
GAP-CLOSE-PWR G12
G9 1 2
1 2
1
GAP-CLOSE-PWR
GAP-CLOSE-PWR C296 C303 C20 G16
5
6
7
8
G11
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
1 2
2
1 2 U1
D
D
D
D
FDMS8692-GP GAP-CLOSE-PWR
GAP-CLOSE-PWR G17
1 2
84.08692.037 GAP-CLOSE-PWR
G
S
S
S
5V_S5 G18
Iomax=11A
4
3
2
1
1 2
C
SB_20090203 OCP>16A C
1
GAP-CLOSE-PWR
R129 RT8202_DH_1D5V 1D5V_PWR G21
10R2F-L-GP L8 Vout=1.500V
1 2
RT8202_LX_1D5V 1 2
5V_S5 IND-1D5UH-34-GP GAP-CLOSE-PWR
2
68.1R510.10J G22
2ND = 68.1R51A.10G 1 2
RT8202_VDD_1D5V
DCBATOUT_8202_1D5V
1
C9
5
6
7
8
1
C305 83.00521.01F D9 TC2 GAP-CLOSE-PWR
SCD1U10V2KX-4GP
1
D
D
D
D
SC1U10V3KX-3GP 2ND = 83.R2003.F8F CH521S-30-GP-U1 U3 R137 G14
2
2
3D3V_S5 R130 3RD = 83.R2003.J8F C313 21K5R3F-GP
SE330U2VDM-L-GP
FDMS7672-GP 1 2
1 2 RT8202_TON_1D5V 5V_S5 SC47P50V2JN-3GP 79.33719.L01
2
84.07672.037 2ND = 77.C3371.051
GAP-CLOSE-PWR
RT8202_BST_1D5V
2
1
820KR2F-GP C306
R140 SC1KP50V2KX-1GP RT8202_FB_1D5V
G
S
S
S
10KR2J-3-GP 1
2
4
3
2
1
1
C312
SC1U10V3KX-3GP RT8202_DL_1D5V R136
2
32 S3_PWRGD 2 R138 1 21K5R3F-GP

2
0R0402-PAD U24 1 2 RT8202_LX_1D5V

1
VDDP
VDD
2
C315 DY R132 C308
SC100P50V2JN-3GP RT8202_BST_1D5V_L 1 SCD1U25V3KX-GP
16 TON BOOT 13 2
SB_20090203
2
RT8202_PGOOD_1D5V 4 12 RT8202_DH_1D5V 1R2F-GP

PGOOD UGATE RT8202_LX_1D5V
PHASE 11
8 RT8202_DL_1D5V
R131 2RT8202_EN_1D5V LGATE
14,28,32,37 PM_SLP_S4# 1 15 EN/DEM
OC 10 RT8202_OC_1D5V 1 R135 2 RT8202_LX_1D5V
Vout=0.75*(1+Rh/Rl)
1
B 0R0402-PAD RT8202_FB_1D5V B
FB 3
C304
DY SCD1U25V3KX-GP
5
14
NC#5
1 1D5V_PWR 4K32R2F-GP
NC#14 VOUT
2
SB_20090203
PGND
GND
GND
SB_20090205 RT8202APQW-GP
7
17
6
A <Core Design> A
Wistron Corporation
Dr-Bios.com
Title
RT8202_1D5V
A3
JM41_UMA -1
5 4 3 2 1
5 4 3 2 1
Iomax=1.2A
OCP>2A
5V_S5 1D5V_S3 DDR_VREF_PWR DDR_VREF_S3
D D
2
C131 C123 DY C122 G23
SC1U10V2KX-1GP SC10U10V5KX-2GP SCD1U10V2KX-4GP 1 2
1
GAP-CLOSE-PWR
G24
U8 1 2
10 1 GAP-CLOSE-PWR
0R0402-PAD R46 9026_S5 VIN VDDQSNS G25
14,28,32,36 PM_SLP_S4# 1 2 9 S5 VLDOIN 2
8 GND VTT 3 1 2
0R0402-PAD 1 R45 2 9026_S3 7 4
S3 PGND GAP-CLOSE-PWR
DDR_VREF_S3_1 6 VTTREF VTTSNS 5
GND
1
1
C129 C120 C117
SC1U10V2KX-1GP RT9026PFP-GP SC10U10V5KX-2GP SC10U10V5KX-2GP
11
74.09026.079
SB_20090205
2
C C
B B
A <Core Design> A
Wistron Corporation
Dr-Bios.com
Title
RT9026_0D75V
A3
JM41_UMA -1
5 4 3 2 1
5 4 3 2 1
D
DCBATOUT_6263A DCBATOUT D
C446
1 R261 2 0R0402-PAD POWER_MONITOR 1 2 VGFXCORE VCC_GFXCORE
8 GFXVR_EN
GFX_VID[4..0] 8
1
SCD01U50V2KX-1GP G26
R263 1 2
G51 10KR2J-3-GP
1 2 1 2 GAP-CLOSE-PWR
R262 100KR2J-1-GP G27
2
GAP-CLOSE-PWR 6236A_VID4 1 R249 2 GFX_VID4 1 2
G48 TC17 0R0402-PAD
1
1 2 DY 6236A_VID3 1 R250 2 GFX_VID3 GAP-CLOSE-PWR
0R0402-PAD G28
ST15U25VDM-1-GP
GAP-CLOSE-PWR 6236A_VID2 1 R251 2 GFX_VID2 1 2
2
G50 0R0402-PAD
1 2 6236A_VID1 1 R106 2 GFX_VID1 GAP-CLOSE-PWR
1 2 0R0402-PAD G32
3D3V_S0
GAP-CLOSE-PWR R256 10KR2J-3-GP 6236A_VID0 1 R102 2 GFX_VID0 1 2
G49 0R0402-PAD
1 2 GAP-CLOSE-PWR
GAP-CLOSE-PWR
TPAD14-GP TP30 1
SB_20090205 1
G29
2
GAP-CLOSE-PWR
5V_S0 G33
6236A_VR_ON
6236A_AF_EN
6236A_GOOD
6236A_PMON
1 2
1
GAP-CLOSE-PWR
R245 G30
0R2J-2-GP 1 2
DCBATOUT_6263A
GAP-CLOSE-PWR
2
C290 C284 G34
33
32
31
30
29
28
27
26
25
U17 C289 1 2
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
GND_T
FDE
PGOOD
AF_EN
VR_ON
PMON
VID4
VID3
VID2
1
5
6
7
8
150KR2F-L-GP DY GAP-CLOSE-PWR
U15
VGFXCORE Iomax=7A G31
D
D
D
D
C R2471 2 6236A_RBIAS 1 24 FDMS8692-GP 1 2 C
RBIAS VID1
C4411 6236A_SOFT
OCP>10.5A GAP-CLOSE-PWR
2 2 SOFT VID0 23 84.08692.037
SCD01U50V2KX-1GP C279 Cyntec 7*7*3
6263A_VCC_PRM 1 R242 6236A_OCSET 6236A_PVCC Id=7A
G
S
S
S
2 3 22 1 2
8K06R2F-GP
C275 OCSET PVCC DCR=8mohm, Irating=13A
C439 Qg=8.7~13nC
4
3
2
1
1 2 6236A_VW 4 VW LGATE 21 6236A_LGATE SC2D2U10V3KX-1GP Isat=24A
1 2 Rdson=23~30mohm
SC1KP50V2KX-1GP 6236A_COMP 5 20
SC68P50V2JN-1GP COMP PGND
1 R94 2 L12
C440 6K98R3F-GP 6 19 6236A_PHASE 1 2 VGFXCORE
6236A_COMP_R FB PHASE
1 R244 2 1 2 6236A_FB COIL-1UH-34-GP-U
374KR3-GP 7 18 6236A_UGATE 68.1R01A.20B
SC180P50V2JN-1GP VDIFF UGATE
6236A_BOOT 2ND = 68.1R01B.10N
DROOP
8 VSEN BOOT 17 1 2 1 2
VSUM
R237
6236A_BOOT_R
VDD
RTN
DFB
VSS
VIN
2D2R3J-2-GP C437
VO
5
6
7
8
R2381 22K21R3F-L-GP 6236A_VDIFF SCD22U16V3KX-2-GP
D
D
D
D
9 U16
6236A_DROOP 10
11
12
13
14
15
16
R92 C271 ISL6263ACRZ-T-GP FDMS7672-GP
1 2 6236A_FB_R 6236A_VSEN 84.07672.037
1
4K99R2F-L-GP
1
6236A_VSUM
6263A_VCC_PRM
SC560P50V2KX-2GP 6236A_DFB G66 G65
6236A_VIN
R235
6236A_VDD
6236A_RTN
G
S
S
S
GAP-CLOSE-PWR GAP-CLOSE-PWR
1 2 5V_S0
4
3
2
1
2
SB_20090203 10R2F-L-GP
R233
C434 Id=7.7A
1 2 1 2 5V_S5
C270 Qg=8.5~13nC
1 2 SC1U16V3KX-2GP 10R2F-L-GP Rdson=16.5~21mohm
2
DY
1
SC1KP50V2KX-1GP R86
R236
C268 C267
1 2
2K2R2F-GP
SC1KP50V2KX-1GP SC1KP50V2KX-1GP DCBATOUT

2
DY DY
1
10R2F-L-GP
1
1 R105 2
1
B C264 C435 TC12 B
1
SCD01U25V2KX-3GP 0R0402-PAD
SC330P50V2KX-3GP
SE220U2VDM-8GP
79.22719.20L
2
1
2ND = 80.2271V.A9L
2
G63 GAP-CLOSE-PWR R84

10 VCC_AXG_SENSE 1 2 1KR3F-GP
R78
2
G64 GAP-CLOSE-PWR C266

10 VSS_AXG_SENSE 1 2 1 2 1 2 6236A_VSUM_R
1
C259 SCD033U25V3KX-GP
C261 7K68R2F-GP
SCD1U25V3KX-GP
1 2
2
1
1
R81 R80 G36 G35
10R3F-GP 10R3F-GP SCD022U25V2KX-GP
GAP-CLOSE-PWR GAP-CLOSE-PWR
1 R79 2
2
2
4K53R2F-1-GP 6236A_VSUM_R_VCC_PRM
Close to choke 1 R229 2 1 R82 2

3K57R2F-GP
and on the same layer NTC-10K-27-GP
Parallel
VSS_AXG_SENSE_OUTCAP
VCC_AXG_SENSE_OUTCAP
A A
Dr-Bios.com
<Core Design>
Wistron Corporation
Title
ISL6263A_GFX CORE
A2
JM41_UMA -1
5 4 3 2 1
D
-1
Wistron Corporation
Rev
40
of
EMI/Spring/Boss
39
JM41_UMA
Sheet
1
1
Saturday, March 07, 2009
Document Number
<Core Design>
Date:
Size
Title
Dr-Bios.com
2
2
EC57
SCD1U16V2ZY-2GP
1 2
DY
EC56
SCD1U16V2ZY-2GP
1 2
DY
EC29
EC66
SCD1U50V3ZY-GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

EC4
1 2
1 2 1 2
DY
DY
EC1
SCD1U50V3ZY-GP
EC67
1 2
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
EC5
1 2 1 2
EC2
DY
DY
1 SCD1U50V3ZY-GP
2
EC40
EC14
1D05V_S0
H10
EC79
1
1 2 1 2
SCD1U50V3ZY-GP
DY
DY
1 2 HOLE355X355R111-S1-GP
ZZ.00PAD.571
EC20
SCD1U16V2ZY-2GP
EC80
3
3
SCD1U50V3ZY-GP
EC58
1 2 1 2
SCD1U16V2ZY-2GP
VGFXCORE
DY
EC71
EC22
1 2
SCD1U16V2ZY-2GP
1 SCD1U50V3ZY-GP
2
1 2
DY
EC27
H9
1 SCD1U50V3ZY-GP
2 HOLET237B315X315R91-S-GP
ZZ.00PAD.591
EC68
EC82
SCD1U16V2ZY-2GP
1 SCD1U50V3ZY-GP
2 1
H8
1 2
EC26
EC51
SCD1U16V2ZY-2GP
STFT256BR75H81-GP
SB_20090115
34.4CQ05.001
1 SCD1U50V3ZY-GP
2
EC60
1 2
SCD1U16V2ZY-2GP 1
H7
VCC_GFXCORE
EC18
EC59
1 2
SCD1U50V3ZY-GP SCD1U16V2ZY-2GP
DY
1 2 STFT256BR75H81-GP
34.4CQ05.001
EC63
1 2
SCD1U16V2ZY-2GP
DCBATOUT
EC28
1
SCD1U50V3ZY-GP
H6
1 2 1 2
DY
4
4
STFT256BR75H81-GP
34.4CQ05.001
EC17
EC23
1 2 1 2 1
H5
DY
DY
EC19
EC72
STFT256BR75H81-GP
34.4CQ05.001
3D3V_S0
EC6
1 2 1 2
SCD1U50V3ZY-GP
DY
DY
1 2
1
H4
EC73
EC77
SC33P50V3JN-GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
EC8
HOLE355X355R111-S1-GP
ZZ.00PAD.571
1 2 1 2 1 2
DY
DY
SP3
EC75
EC78
1 1
H3
EC7
1 SCD1U50V3ZY-GP
2 SPRING-62-GP HOLE389X394R166-S-GP
5V_S5
1 2 1 2 34.39S07.003 ZZ.0HOLE.XXX
DY
DY
EC36
SCD1U50V3ZY-GP
SP2
1 2 1 1
H2
DY
EC37
EC12
SC33P50V3JN-GP SCD1U16V2ZY-2GP
SPRING-5-GP HOLE355X355R111-S1-GP
34.41Y01.001 ZZ.00PAD.571
1 2 1 2
5
5
DY
SP1
1 1
SCD1U16V2ZY-2GP
H1
DCBATOUT
DY
EC9
EC38
SCD1U16V2ZY-2GP
1D5V_S0
EC3
SCD1U50V3ZY-GP
SPRING-5-GP HOLE355X355R111-S1-GP
1D5V_S3
1 2 1 2 34.41Y01.001 ZZ.00PAD.571
DY
DY
1 2
DY
D
A
5 4 3 2 1
D D
C C
B B
A A
Dr-Bios.com
<Core Design>
Wistron Corporation
Title
HISTORY
A2
JM41_UMA -1
5 4 3 2 1

System DC/DC converter diagram

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System DC/DC converter diagram

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5 4 3 2 1

ICS9LPRS365B Penryn SFF EMC2103 32 VCC/GND L3

DDR3 Cantiga-GS SFF LVDS LCD S L7

DDR Memory I/F RGB CRT CRT

X4 DMI 5V_S5 DDR_VREF_S3

LPC BUS VGA

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

SATA Cardreader Pad 35 KB 33 MS/MS Pro/xD Title

RTS5159 BLOCK DIAGRAM

Byte 5, bit 5 PIN NAME DESCRIPTION 1 0 1 100M X

Byte 5, bit 3 SRCC11/CR#_G 0 = SRC11# enabled (default)

A20# BPM1# D9# D41#

H_A#24 A23# PRDY# XDP_BPM#5 H_D#13 G41 D12# D44# H_D#45

13 H_IGNNE# F10 IGNNE# AA41 D24# D56# AY36

Y2 RSVD#Y2 7 H_DSTBN#1 U43 DSTBN1# DSTBN3# AY40 H_DSTBN#3 7

B26 L37 C35 C46 DY AH38 AA31

D28 VCC VCCP N37 AJ39 VSS VSS AC31

D30 VCC VCCP P38 AL39 VSS VSS AE29

F30 VCC VCCP R37 AM38 VSS VSS AE27

K26 H_VID[6..0] 34 C339 C347 BD38 AN27

M26 VCC VID0 BD8 B36 VSS VSS AL31

P28 BB10 H_VID2 D36 AR29

J17 VSS VSS AY6 M20 VCC VCCP V10

AL19 VSS VSS AN3 AH18 VCC VCCP AK12

AN19 VSS VSS AU3 AF20 VCC VCCP AL11

NCTF TEST PIN:

Size Document Number

Date: Sunday, March 01, 2009

H_D#19 V2 G19 H_A#23

4 H_CPURST# J11 G15 H_REQ#4

H_AVREF L17 H_AVREF

DDR CLK/ CONTROL/COMPENSATION

A23 CFG_11 DMI_TXP_2 AJ45 DMI_RXP2 14 PEG_TX_7 T50

GRAPHICS VID DMI

M_RCOMPP TPAD14-GP TP52 1 CFG16 C25 20 GMCH_VSYNC 2 3 GMCH_VSYNC_C G31 Y52

G37 GFX_VID1 1 2 CRT_IREF

R67 1 DY 2 4K02R2F-GP CFG20 17,18 PM_EXTTS#0 PM_EXTTS#0 J39 PM_EXT_TS#_0

L39 PM_EXT_TS#_1 Teenah: 1.3k ohm

NC#A49 CL_RST# CL_RST#0 14

A52 AL55 MCH_CLVREF 3D3V_S0

14,34 PM_DPRSLPVR BE55 F32 RN26 SRN100KJ-6-GP

NC#BK55 SDVO_CTRLDATA GMCH_HDMI_DATA 20

3D3V_S0 MCH_TSATN# 3K01R2F-3-GP SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP SRN150F-1-GP

PM_EXTTS#0 3 2 SM_RCOMP_VOL 2 7 TV_DACB

C399 C398 4 5 TV_DACA

A 3D3V_S0 DIS = 66.R0036.A8L A

M_A_DQ[63..0] NB1D 4 OF 10 M_B_DQ[63..0] NB1E 5 OF 10

M_A_DQ47 SA_DQ_46 SA_MA_8 M_A_A9 M_B_DQ47 SB_DQ_46 SB_MA_7 M_B_A8

BB36 VCC_SM VCC_AXG_NCTF U31

VCC GFX NCTF

AE28 VCC_AXG VCC_AXG R16 AJ31 VCC VCC_NCTF AN37

AM21 VCC_AXG VCC_SM_LF

38 VCC_AXG_SENSE VCC_AXG_SENSE AG13

place near Cantiga

Size Document Number

Date: Tuesday, March 17, 2009

5V_S0 3D3V_S0_DAC 1D05V_S0

0R0603-PAD C209 C208

AE1 VCCA_MPLL VCCA_TV_DAC K30

C414 C413 C415 R74 2 VCCA_PEG_BG

DY DY SCD1U10V2KX-4GP 3D3V_S0 U11

68.00217.161 C154 C161 AU15