5 4 3 2 1

D D

Hellcat 15 Upsell Schematics

Tiger Lake - U/ LPPDR4X
2020-08-03
C C

REV : A00

B B

A DY : None Installed <Core Design> A

UMA: UMA only installed Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

OPS: DISCRTE OPTIMUS installed Title

Taipei Hsien 221, Taiwan, R.O.C.

Cover Page
Size Document Number Rev
A3
Hellcat 15'' Upsell TGL -1
Date: Monday, August 03, 2020 Sheet 1 of 105
5 4 3 2 1
 5 4 3 2 1

Project code: 4PD0HC010001

Hellcat 15 Upsell CPU 15W + GPU 25W Block Diagram PCB P/N: 19828
Revision: X00

MD x32
LPDDR4/4x Channel A Type-3: 3200 8GB

GPU PCIE x 4 GEN4 12

D LPDDR4X 4267MT/s D
LPDDR4X
4GB Intel DG1 25W Flash ROM Intel CPU MD x32
78-79 76-77 SPI
8 MB LPDDR4/4x Channel B Type-3: 3200 8GB
Tiger LAKE-U 4+2
13

15.6" DisplayPort to HDMI Converter

(FHD/UHD)
eDP TGL PCH-LP DDI Parade HDMI HDMI V2.0
PS8409AQFN 57 57
55 I2C 4 TCSS Lanes
12 PCIe*3.0 Lanes (SATA*2, USB31*4)
Touch panel 71
1 PCIE4.0x4 Lanes
TCSS Re-Timer THUNDERBOLT
10 USB2.0
BURNSIDE-BRIDGE
M.2 SSD 63 SATA/PCIex2(Optane)/PCIEx4 CNVi2.0
(KEY M) ESPI / SPI Type C Connector
HDA/SNDW USB 2.0
I2C
CSI
ALS 73
(Remove SD/EMMC) CC control pin
C USB2.0 USB2.0 LANE4
CCG6SF C

Proximity Sensor I2C 72

USB2.0 LANE5
USB3.0
USB2.0 LANE1

CAMERA(HD) USB2.0 x 1 USB3.1 Gen1 Port1

USB2.0
USB2.0 LANE1

Free fall
INT2 Gsensor
ST
LNG2DM 70 Finger Print
USB2.0
USB2.0 LANE5

Gyro+G
2-1 ST
LSM6DS3
I2C

E-compass
USB 3.1 Gen1
ST
LIS2MDL
USB3.1 Gen1
USB3.0 LANE2 Re-driver USB3.1 Gen1
IO Board
PARADE USB3.1 Gen1 Port2
PS8719B

B USB2.0 USB2.0 LANE2

B

WLAN SIP USB2.0 LANE10

USB2.0
CardReader
(M.2 1216 Harrison peak2) SD 3.0 Micro SD Card Slot
USB2.0
CNVi GEN2 Realtak
RTS5144

DMIC
D-MIC 55
MIC_IN/GND
Bluetooth eSPI debug port eSPI BUS Universal Jack
Hellcat Pen 68
HDA HP_R/L

Thermal KBC
NUVOTON SMBUS MICROCHIP SPI
NCT7718W 26 MEC1515 HDA
2CH SPEAKER
24 CODEC (2CH 2W/4ohm)
Realtek
Fan Control ALC3254-VA3
A
I2C A
PWM 26 Flash ROM 27

16 + 8 MB
Quad Read 25
<Core Design>

Int. Touch PAD

FAN Image sensor Wistron Corporation
KB I2C 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Block Diagram
Size Document Number Rev
Custom
Hellcat 15'' Upsell TGL -1
Date: Monday, August 03, 2020 Sheet 2 of 105
5 4 3 2 1
 5 4 3 2 1

D D

1D05V_VCCSTG

1D05V_VCCSTG_TERM
R301 1 2 1KR2F-3-GP EAR_N_TEST_NCTF
R311 1 2 51R2J-2-GP XDP_TDO_CPU

1D05V_VCCSTG_TERM R308 1 DY 2 51R2J-2-GP XDP_PREQ# 2020.02.04 Intel feedback

no pull-up required on net XDP_PREQ#

R302 1 2 1KR2F-3-GP PROCHOT_N_CPU

10/09 R309 Delete,Charon
1D05V_VCCST
R312 1 DY 2 51R2J-2-GP XDP_TDI
R304 1 2 1KR2F-3-GP THERMTRIP#_CPU R313 1 DY 2 51R2J-2-GP XDP_TMS
CPU_CATERR CPU_CATERR
R307 1 2 1KR2F-3-GP
77 THERMTRIP#_CPU XDP_TCLK R310 1 XDP 2 51R2J-2-GP
CPU_POPI_RCOMP R305 1 2 49D9R2F-GP
C C
24,77 PECI_CPU PCH_OPI_RCOMP XDP_TRST#
R306 1 2 49D9R2F-GP R314 1 DY 2 51R2J-2-GP
PCH_TCK R315 1 2 51R2J-2-GP
15 DBG_PMODE DY
22,24,44,46,72 PROCHOT_N_CPU

24,65 TOUCH_PAD_INTR# 21 OF 21
CPU1U

XDP_TCLK CPU_CATERR XDP_TRST#

M7 K4 1
XDP_TDI PECI_CPU CATERR# PROC_TRST# XDP_TMS TP309
BK9 B9 1
XDP_TDO_CPU PROCHOT_N_CPU R303 1 PROCHOT_N_CPU_R E2 PECI PROC_TMS XDP_TDO_CPU TP310
2 499R2F-2-GP D12 1
XDP_TMS THERMTRIP#_CPU PROCHOT# PROC_TDO XDP_TDI TP311
M5 A12 1
XDP_TRST# THRMTRIP# PROC_TDI XDP_TCLK TP312
B6 1
XDP_PRDY# CPU_POPI_RCOMP CT39 PROC_TCK TP313
XDP_PREQ# PCH_OPI_RCOMP PROC_POPIRCOMP
CB9 D8
PCH_TCK PCH_OPIRCOMP PCH_JTAGX
CW12 A9
CM39 TP#CW12
TP#CM39
PCH_TMS
PCH_TDO
E12 XDP
B12
21 MEM_CONFIG4 DB42: TOUCH_PANEL_DET# DBG_PMODE DF4 PCH_TDI A7 PCH_TCK 1
DF8: TOUCH_PANEL_PD# DBG_PMODE PCH_TCK TP314
H4
EAR_N_TEST_NCTF DB42 PCH_TRST#
TOUCH_PAD_INTR# DB41 GPP_B4/CPU_GP3 C11 XDP_PREQ#
TOUCH_PANEL_PD# DF8 GPP_B3/CPU_GP2 PROC_PREQ# D11 XDP_PRDY# 1
55 TOUCH_PANEL_PD# GPP_E7/CPU_GP1 PROC_PRDY# TP302
DU5
GPP_E3/CPU_GP0 G1 EAR_N_TEST_NCTF
DF31 EAR_N/EAR_N_TEST_NCTF
B DV32 GPP_H2 DT15 GPP_F7 1 B
GPP_H1 GPP_F7 TP315
DW32 DR15
GPP_H0 GPP_F9 DT14 GPP_F10 1
MEM_CONFIG4 DJ27 GPP_F10 TP316
GPP_H19/TIME_SYNC0

TGL-U-1-GP-U2

A A
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU (THML/JTAG)
Size Document Number Rev
A3
Hellcat 15'' Upsell TGL -1
Date: Monday, August 03, 2020 Sheet 3 of 105
5 4 3 2 1
 5 4 3 2 1

eDP
55 eDP_TX_CPU_N0
55 eDP_TX_CPU_P0
55 eDP_TX_CPU_N1
55 eDP_TX_CPU_P1
55 eDP_TX_CPU_N2
55 eDP_TX_CPU_P2
55 eDP_TX_CPU_N3
55 eDP_TX_CPU_P3
D 55 eDP_AUX_CPU_N D
55 eDP_AUX_CPU_P
55 EDP_HPD 1 OF 21
CPU1A
24 L_BKLT_EN
55 eDP_VDD_EN
55 L_BKLT_CTRL
eDP_TX_CPU_P3 AC2 AY2 USB1_TCSS_RX_P1
eDP_TX_CPU_N3 AC1 DDIA_TXP3 TCP0_TXRX_P1 AY1 USB1_TCSS_RX_N1
eDP_TX_CPU_P2 AD2 DDIA_TXN3 TCP0_TXRX_N1 BB1 USB1_TCSS_RX_P0
HDMI eDP_TX_CPU_N2 AD1 DDIA_TXP2
DDIA_TXN2
TCP0_TXRX_P0
TCP0_TXRX_N0
BB2 USB1_TCSS_RX_N0
eDP_TX_CPU_P1 AF1 AM5 USB1_TCSS_TX_P1
57 HDMI_DDI_TX_P3
eDP_TX_CPU_N1 AF2 DDIA_TXP1 TCP0_TX_P1 AM7 USB1_TCSS_TX_N1 TBT
57
57
HDMI_DDI_TX_N3
HDMI_DDI_TX_P0
eDP eDP_TX_CPU_P0 AG2 DDIA_TXN1
DDIA_TXP0
TCP0_TX_N1
TCP0_TX_P0
AT7 USB1_TCSS_TX_P0
eDP_TX_CPU_N0 AG1 AT5 USB1_TCSS_TX_N0
57 HDMI_DDI_TX_N0 DDIA_TXN0 TCP0_TX_N0 AP7 USB1_TCSS_AUX_P
57 HDMI_DDI_TX_P1 TCP0_AUX_P
eDP_AUX_CPU_P AJ2 AP5 USB1_TCSS_AUX_N
57 HDMI_DDI_TX_N1 DDIA_AUX_P TCP0_AUX_N
eDP_AUX_CPU_N AJ1
57 HDMI_DDI_TX_P2 DDIA_AUX_N
57 HDMI_DDI_TX_N2 AT2
DN4 TCP1_TXRX_P1 AT1
TP401 1GPP_E23 DT6 GPP_E22/DDPA_CTRLCLK/DNX_FORCE_RELOAD TCP1_TXRX_N1 AU1
57 CPU_DPB_CTRL_CLK GPP_E23/DDPA_CTRLDATA TCP1_TXRX_P0 AU2
57 CPU_DPB_CTRL_DATA EDP_HPD TCP1_TXRX_N0
DR5 AD5
57 CPU_DISP_HPDB
eDP GPP_E14/DDSP_HPDA/DISP_MISCA TCP1_TX_P1
TCP1_TX_N1
AD7
HDMI_DDI_TX_P3 T12 AH7
HDMI_DDI_TX_N3 T11 DDIB_TXP3 TCP1_TX_P0 AH5
HDMI_DDI_TX_P0 Y11 DDIB_TXN3 TCP1_TX_N0 AF7
HDMI_DDI_TX_N0 Y9 DDIB_TXP2 TCP1_AUX_P AF5
HDMI_DDI_TX_P1 T9 DDIB_TXN2 TCP1_AUX_N
C HDMI_DDI_TX_N1 P9 DDIB_TXP1 BF1 C
TBT HDMI_DDI_TX_P2 V11 DDIB_TXN1
DDIB_TXP0
TCP2_TXRX_P1
TCP2_TXRX_N1
BF2
HDMI_DDI_TX_N2 V9 BE2
71 USB1_TCSS_TX_N0 DDIB_TXN0 TCP2_TXRX_P0 BE1
71
71
USB1_TCSS_TX_P0
USB1_TCSS_TX_N1
HDMI AB9
DDIB_AUX_P
TCP2_TXRX_N0
TCP2_TX_P1
BD7
AD9 BD5
71 USB1_TCSS_TX_P1 DDIB_AUX_N TCP2_TX_N1 AY5
71 USB1_TCSS_RX_N0 CPU_DPB_CTRL_CLK TCP2_TX_P0
DM29 AY7
71 USB1_TCSS_RX_P0 CPU_DPB_CTRL_DATA GPP_H16/DDPB_CTRLCLK/PCIE_LNK_DOWN TCP2_TX_N0
DK27 BB5
71 USB1_TCSS_RX_N1 GPP_H17/DDPB_CTRLDATA TCP2_AUX_P BB7
71 USB1_TCSS_RX_P1 CPU_DISP_HPDB TCP2_AUX_N
DG43
GPP_A18/DDSP_HPDB/DISP_MISCB/I2S4_RXD BK1
DG47 TCP3_TXRX_P1 BK2
71 TBT_LSX0_TXD KB_DET# GPP_A21/DDPC_CTRLCLK/I2S5_TXD TCP3_TXRX_N1
DJ47 BJ2
15,71 TBT_LSX0_RXD GPP_A22/DDPC_CTRLDATA/I2S5_RXD TCP3_TXRX_P0 BJ1
TBT_LSX0_TXD DU8 TCP3_TXRX_N0 BM7
71
71
USB1_TCSS_AUX_P
USB1_TCSS_AUX_N
TBT TBT_LSX0_RXD DV8 GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD
GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD
TCP3_TX_P1
TCP3_TX_N1
BM5
BH5
DF6 TCP3_TX_P0 BH7
GPP_E21 DD6 GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD TCP3_TX_N0 BK5
GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD TCP3_AUX_P BK7
DN23 TCP3_AUX_N
GPP_D10 DM23 GPP_D9/ISH_SPI_CS#/DDP3_CTRLCLK/TBT_LSX2_TXD/GSPI2_CS0# AN2 TCSS_RCOMP_P
DN4: WWAN_GPO_PEREST# GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/TBT_LSX2_RXD/GSPI2_CLK TC_RCOMP_P AN1 TCSS_RCOMP_N R402 1 2 150R2F-1-GP
Other DT6: WWAN_CARD_PWR_OFF# DK23
GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/TBT_LSX3_TXD/GSPI2_MISO
TC_RCOMP_N
DG47: 3.3V_CAM_EN GPP_D12 DN21 M8
DF6: TBT_LSX1_TXD GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/TBT_LSX3_RXD/GSPI2_MOSI DSI_DE_TE_2
15 GPP_E21 DN23: SENSOR_DB_DET# DISP_RCOMP
DF43 AB1 R401 1 2 150R2F-1-GP
DD6: TBT_LSX1_RXD CPU_DISP_HPD1 DF45 GPP_A17/DISP_MISCC/I2S4_TXD DDI_RCOMP
B 15 GPP_D12 DK23: CPU_DDP4_CTRL_CLK TBT DF47 GPP_A19/DDSP_HPD1/DISP_MISC1/I2S5_SCLK
GPP_A20/DDSP_HPD2/DISP_MISC2/I2S5_SFRM DISP_UTILS/DSI_DE_TE_1
CE4 B
DN21: CPU_DDP4_CTRL_DATA
15 GPP_D10 DF47: CPU_DISP_HPD2 USB_OC1# DH52
DH52: USB_OC1# 20200318 SOC_OC_FAULT_R DK45 GPP_A14/USB_OC1#/DDSP_HPD3/I2S3_RXD/DISP_MISC3/DMIC_CLK_B1
65 KB_DET# change net name GPP_A15/USB_OC2#/DDSP_HPD4/DISP_MISC4/I2S4_SCLK
DK45: CPU_DISP_HPD4
eDP_VDD_EN DM8
72 SOC_OC_FAULT_R EDP_VDDEN
L_BKLT_EN DN8
eDP L_BKLT_CTRL DG10 EDP_BKLTEN
EDP_BKLTCTL

TGL-U-1-GP-U2
USB3.2 Type-A Port2 (IO)

35 USB_OC1#
R404
2 1 CPU_DISP_HPD1
DY
100KR2J-1-GP

3D3V_S5_VCCPRIM
R403
2 1 USB_OC1#
A A
20191224 10KR1J-GP <Core Design>
Follow Internal review

3D3V_S0
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
R405 Taipei Hsien 221, Taiwan, R.O.C.
2 1 KB_DET#
Title
10KR2J-3-GP CPU (DDI/EDP/TBT/TPC/)
Size Document Number Rev
A3
Hellcat 15'' Upsell TGL -1
Date: Monday, August 03, 2020 Sheet 4 of 105
5 4 3 2 1
 5 4 3 2 1

CPU1B 2 OF 21

LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL) DDR4/LP4/LP5/LP5 CMD Flip

M_A_DQ7 CP53 BT42 M_B_CLK1
12 M_A_DQ[31:0] M_A_DQ0 13 M_C_DQ[31:0] M_C_DQ0 M_A_DQ6 DDR0_DQ0_7/DDR0_DQ0_7/DDR0_DQ0_7 DDR0_CLK_P1/DDR3_CLK_P/DDR3_CLK_P/DDR3_CLK_P M_B_CLK1#
CP52 BT41
M_A_DQ1 M_C_DQ1 M_A_DQ5 CP50 DDR0_DQ0_6/DDR0_DQ0_6/DDR0_DQ0_6 DDR0_CLK_N1/DDR3_CLK_N/DDR3_CLK_N/DDR3_CLK_N BP52 M_B_CLK0
M_A_DQ2 M_C_DQ2 M_A_DQ4 CP49 DDR0_DQ0_5/DDR0_DQ0_5/DDR0_DQ0_5 NC/DDR2_CLK_P/DDR2_CLK_P/DDR2_CLK_P BP53 M_B_CLK0#
M_A_DQ3
M_A_DQ4
M_C_DQ3
M_C_DQ4
M_A_DQ[7:0] M_A_DQ3
M_A_DQ2
CU53 DDR0_DQ0_4/DDR0_DQ0_4/DDR0_DQ0_4
DDR0_DQ0_3/DDR0_DQ0_3/DDR0_DQ0_3
NC/DDR2_CLK_N/DDR2_CLK_N/DDR2_CLK_N
NC/DDR1_CLK_P/DDR1_CLK_P/DDR1_CLK_P
CD42 M_A_CLK1
M_A_CLK1#
CU52 CD41
M_A_DQ5 M_C_DQ5 M_A_DQ1 CU50 DDR0_DQ0_2/DDR0_DQ0_2/DDR0_DQ0_2 NC/DDR1_CLK_N/DDR1_CLK_N/DDR1_CLK_N CC52 M_A_CLK0
M_A_DQ6 M_C_DQ6 M_A_DQ0 CU49 DDR0_DQ0_1/DDR0_DQ0_1/DDR0_DQ0_1 DDR0_CLK_P0/DDR0_CLK_P/DDR0_CLK_P/DDR0_CLK_P CC53 M_A_CLK0#
M_A_DQ7 M_C_DQ7 M_A_DQ15 CH53 DDR0_DQ0_0/DDR0_DQ0_0/DDR0_DQ0_0 DDR0_CLK_N0/DDR0_CLK_N/DDR0_CLK_N/DDR0_CLK_N
M_A_DQ8 M_C_DQ8 M_A_DQ14 CH52 DDR0_DQ1_7/DDR0_DQ1_7/DDR0_DQ1_7 BT45 M_B_CKE2
M_A_DQ9 M_C_DQ9 M_A_DQ13 CH50 DDR0_DQ1_6/DDR0_DQ1_6/DDR0_DQ1_6 NC/DDR3_CKE0/DDR3_WCK_P/DDR3_WCK_P BT47 M_B_CKE3
M_A_DQ10 M_C_DQ10 M_A_DQ12 CH49 DDR0_DQ1_5/DDR0_DQ1_5/DDR0_DQ1_5 NC/DDR3_CKE1/DDR3_WCK_N/DDR3_WCK_N BN51 M_B_CKE0
M_A_DQ11
M_A_DQ12
M_C_DQ11
M_C_DQ12
M_A_DQ[15:8] M_A_DQ11
M_A_DQ10
CL53 DDR0_DQ1_4/DDR0_DQ1_4/DDR0_DQ1_4
DDR0_DQ1_3/DDR0_DQ1_3/DDR0_DQ1_3
NC/DDR2_CKE0/DDR2_WCK_P/DDR2_WCK_P
NC/DDR2_CKE1/DDR2_WCK_N/DDR2_WCK_N
BN53 M_B_CKE1
M_A_CKE2
CL52 CD45
M_A_DQ13 M_C_DQ13 M_A_DQ9 CL50 DDR0_DQ1_2/DDR0_DQ1_2/DDR0_DQ1_2 NC/DDR1_CKE0/DDR1_WCK_P/DDR1_WCK_P CD47 M_A_CKE3
M_A_DQ14 M_C_DQ14 M_A_DQ8 CL49 DDR0_DQ1_1/DDR0_DQ1_1/DDR0_DQ1_1 NC/DDR1_CKE1/DDR1_WCK_N/DDR1_WCK_N CA51 M_A_CKE0
M_A_DQ15 M_C_DQ15 M_A_DQ23 CT47 DDR0_DQ1_0/DDR0_DQ1_0/DDR0_DQ1_0 NC/DDR0_CKE0/DDR0_WCK_P/DDR0_WCK_P CA53 M_A_CKE1
M_A_DQ16 M_C_DQ16 M_A_DQ22 CV47 DDR1_DQ0_7/DDR0_DQ2_7/DDR1_DQ0_7 NC/DDR0_CKE1/DDR0_WCK_N/DDR0_WCK_N
M_A_DQ17 M_C_DQ17 M_A_DQ21 CT45 DDR1_DQ0_6/DDR0_DQ2_6/DDR1_DQ0_6 BU52 M_B_A4
D D
M_A_DQ18 M_C_DQ18 M_A_DQ20 CV45 DDR1_DQ0_5/DDR0_DQ2_5/DDR1_DQ0_5 DDR0_CKE1/DDR2_CA4/DDR2_CA5/DDR2_CA1 BL50 M_B_A5
M_A_DQ19
M_A_DQ20
M_C_DQ19
M_C_DQ20
M_A_DQ[23:16] M_A_DQ19
M_A_DQ18
CT42 DDR1_DQ0_4/DDR0_DQ2_4/DDR1_DQ0_4
DDR1_DQ0_3/DDR0_DQ2_3/DDR1_DQ0_3
DDR0_CKE0/DDR2_CA5/DDR2_CA6/DDR2_CA0
M_A_B1
CV42 CF42
M_A_DQ21 M_C_DQ21 M_A_DQ17 CT41 DDR1_DQ0_2/DDR0_DQ2_2/DDR1_DQ0_2 DDR0_CS1/DDR1_CA1/DDR1_CA1/DDR1_CA5 CF47
M_A_DQ22 M_C_DQ22 M_A_DQ16 CV41 DDR1_DQ0_1/DDR0_DQ2_1/DDR1_DQ0_1 DDR0_CS0/NC/DDR1_CS1/DDR1_CA4
M_A_DQ23 M_C_DQ23 M_A_DQ31 CK47 DDR1_DQ0_0/DDR0_DQ2_0/DDR1_DQ0_0 CE53 M_A_A0
M_A_DQ24 M_C_DQ24 M_A_DQ30 CM47 DDR1_DQ1_7/DDR0_DQ3_7/DDR1_DQ1_7 NC/DDR0_CA0/DDR0_CA0/DDR0_CA6 CE50 M_A_A1
M_A_DQ25 M_C_DQ25 M_A_DQ29 CK45 DDR1_DQ1_6/DDR0_DQ3_6/DDR1_DQ1_6 NC/DDR0_CA1/DDR0_CA1/DDR0_CA5 BL53 M_B_CS#0
M_A_DQ26 M_C_DQ26 M_A_DQ28 CM45 DDR1_DQ1_5/DDR0_DQ3_5/DDR1_DQ1_5 NC/DDR2_CS0/DDR2_CA2/DDR2_CA2 BP47 M_B_B5
M_A_DQ27
M_A_DQ28
M_C_DQ27
M_C_DQ28
M_A_DQ[31:24] M_A_DQ27
M_A_DQ26
CK42 DDR1_DQ1_4/DDR0_DQ3_4/DDR1_DQ1_4
DDR1_DQ1_3/DDR0_DQ3_3/DDR1_DQ1_3
NC/DDR3_CA5/DDR3_CA6/DDR3_CA0
NC/DDR3_CA4/DDR3_CA5/DDR3_CA1
BP42 M_B_B4
M_B_B3
CM42 BP45
M_A_DQ29 M_C_DQ29 M_A_DQ25 CM41 DDR1_DQ1_2/DDR0_DQ3_2/DDR1_DQ1_2 NC/DDR3_CA3/DDR3_CA4/DDR3_CS1 BP44 M_B_B2
M_A_DQ30 M_C_DQ30 M_A_DQ24 CK41 DDR1_DQ1_1/DDR0_DQ3_1/DDR1_DQ1_1 NC/DDR3_CA2/DDR3_CA3/DDR3_CS0
M_A_DQ31 M_C_DQ31 M_B_DQ7 BF53 DDR1_DQ1_0/DDR0_DQ3_0/DDR1_DQ1_0 BB44 M_B_DQS_DP3
M_B_DQ6 BF52 DDR2_DQ0_7/DDR0_DQ4_7/DDR0_DQ2_7 DDR3_DQSP_1/DDR0_DQSP_7/DDR1_DQSP_3 BD44 M_B_DQS_DN3
M_B_DQ5 BF50 DDR2_DQ0_6/DDR0_DQ4_6/DDR0_DQ2_6 DDR3_DQSN_1/DDR0_DQSN_7/DDR1_DQSN_3 BK44 M_B_DQS_DP2
12 M_A_DQS_DN[3:0] M_A_DQS_DN0 13 M_C_DQS_DN[3:0] M_C_DQS_DN0 M_B_DQ4 DDR2_DQ0_5/DDR0_DQ4_5/DDR0_DQ2_5 DDR3_DQSP_0/DDR0_DQSP_6/DDR1_DQSP_2 M_B_DQS_DN2
BF49 BH44
M_A_DQS_DN1
M_A_DQS_DN2
M_C_DQS_DN1
M_C_DQS_DN2
M_B_DQ[7:0] M_B_DQ3
M_B_DQ2
BH53 DDR2_DQ0_4/DDR0_DQ4_4/DDR0_DQ2_4
DDR2_DQ0_3/DDR0_DQ4_3/DDR0_DQ2_3
DDR3_DQSN_0/DDR0_DQSN_6/DDR1_DQSN_2
DDR2_DQSP_1/DDR0_DQSP_5/DDR0_DQSP_3
BA51 M_B_DQS_DP1
M_B_DQS_DN1
BH52 BA50
M_A_DQS_DN3 M_C_DQS_DN3 M_B_DQ1 BH50 DDR2_DQ0_2/DDR0_DQ4_2/DDR0_DQ2_2 DDR2_DQSN_1/DDR0_DQSN_5/DDR0_DQSN_3 BG51 M_B_DQS_DP0
M_B_DQ0 BH49 DDR2_DQ0_1/DDR0_DQ4_1/DDR0_DQ2_1 DDR2_DQSP_0/DDR0_DQSP_4/DDR0_DQSP_2 BG50 M_B_DQS_DN0
M_B_DQ15 AY53 DDR2_DQ0_0/DDR0_DQ4_0/DDR0_DQ2_0 DDR2_DQSN_0/DDR0_DQSN_4/DDR0_DQSN_2 CK44 M_A_DQS_DP3
12 M_A_DQS_DP[3:0] M_A_DQS_DP0 13 M_C_DQS_DP[3:0] M_C_DQS_DP0 M_B_DQ14 DDR2_DQ1_7/DDR0_DQ5_7/DDR0_DQ3_7 DDR1_DQSP_1/DDR0_DQSP_3/DDR1_DQSP_1 M_A_DQS_DN3
AY52 CM44
M_A_DQS_DP1 M_C_DQS_DP1 M_B_DQ13 AY50 DDR2_DQ1_6/DDR0_DQ5_6/DDR0_DQ3_6 DDR1_DQSN_1/DDR0_DQSN_3/DDR1_DQSN_1 CT44 M_A_DQS_DP2
M_A_DQS_DP2 M_C_DQS_DP2 M_B_DQ12 AY49 DDR2_DQ1_5/DDR0_DQ5_5/DDR0_DQ3_5 DDR1_DQSP_0/DDR0_DQSP_2/DDR1_DQSP_0 CV44 M_A_DQS_DN2
M_A_DQS_DP3 M_C_DQS_DP3 M_B_DQ[15:8] M_B_DQ11
M_B_DQ10
BC53 DDR2_DQ1_4/DDR0_DQ5_4/DDR0_DQ3_4
DDR2_DQ1_3/DDR0_DQ5_3/DDR0_DQ3_3
DDR1_DQSN_0/DDR0_DQSN_2/DDR1_DQSN_0
DDR0_DQSP_1/DDR0_DQSP_1/DDR0_DQSP_1
CK51 M_A_DQS_DP1
M_A_DQS_DN1
BC52 CK50
M_B_DQ9 BC50 DDR2_DQ1_2/DDR0_DQ5_2/DDR0_DQ3_2 DDR0_DQSN_1/DDR0_DQSN_1/DDR0_DQSN_1 CR51 M_A_DQS_DP0
M_B_DQ8 BC49 DDR2_DQ1_1/DDR0_DQ5_1/DDR0_DQ3_1 DDR0_DQSP_0/DDR0_DQSP_0/DDR0_DQSP_0 CR50 M_A_DQS_DN0
12 M_A_CLK0# 13 M_C_CLK0# M_B_DQ23 BK47 DDR2_DQ1_0/DDR0_DQ5_0/DDR0_DQ3_0 DDR0_DQSN_0/DDR0_DQSN_0/DDR0_DQSN_0
12 M_A_CLK0 13 M_C_CLK0 M_B_DQ22 BK45 DDR3_DQ0_7/DDR0_DQ6_7/DDR1_DQ2_7 CF44 M_A_B0
12 M_A_CLK1# 13 M_C_CLK1# M_B_DQ21 DDR3_DQ0_6/DDR0_DQ6_6/DDR1_DQ2_6 DDR0_ODT1/DDR1_CA0/DDR1_CA0/DDR1_CA6 M_A_CS#2
BH47 CF45
12 M_A_CLK1 13 M_C_CLK1 M_B_DQ20 DDR3_DQ0_5/DDR0_DQ6_5/DDR1_DQ2_5 DDR1_ODT0/DDR1_CS0/DDR1_CA2/DDR1_CA2
BH45
12 M_A_CKE0 13 M_C_CKE0
M_B_DQ[23:16] M_B_DQ19
M_B_DQ18
BH42 DDR3_DQ0_4/DDR0_DQ6_4/DDR1_DQ2_4
DDR3_DQ0_3/DDR0_DQ6_3/DDR1_DQ2_3 DDR0_MA16/DDR1_CA4/DDR1_CA5/DDR1_CA1
CB47 M_A_B4
M_A_B3
BK42 CB44
12 M_A_CKE1 13 M_C_CKE1 M_B_DQ17 DDR3_DQ0_2/DDR0_DQ6_2/DDR1_DQ2_2 DDR0_MA15/DDR1_CA3/DDR1_CA4/DDR1_CS1 M_A_B2
BK41 CB45
12 M_A_CKE2 13 M_C_CKE2 M_B_DQ16 BH41 DDR3_DQ0_1/DDR0_DQ6_1/DDR1_DQ2_1 DDR0_MA14/DDR1_CA2/DDR1_CA3/DDR1_CS0 CF41 M_A_CS#3
12 M_A_CKE3 13 M_C_CKE3 M_B_DQ31 DDR3_DQ0_0/DDR0_DQ6_0/DDR1_DQ2_0 DDR0_MA13/DDR1_CS1/DDR1_CS0/DDR1_CA3 M_B_A1
BD47 BU53
M_B_DQ30 BB47 DDR3_DQ1_7/DDR0_DQ7_7/DDR1_DQ3_7 DDR0_MA12/DDR2_CA1/DDR2_CA1/DDR2_CA5 BT51
12 M_A_CS#0 13 M_C_CS#0 M_B_DQ29 DDR3_DQ1_6/DDR0_DQ7_6/DDR1_DQ3_6 DDR0_MA11/NC/DDR2_CS1/DDR2_CA4 M_B_B1
BD45 BV42
12 M_A_CS#1 13 M_C_CS#1 M_B_DQ28 BB45 DDR3_DQ1_5/DDR0_DQ7_5/DDR1_DQ3_5 DDR0_MA10/DDR3_CA1/DDR3_CA1/DDR3_CA5 BU50 M_B_A0
12
12
M_A_CS#2
M_A_CS#3
13
13
M_C_CS#2
M_C_CS#3
M_B_DQ[31:24] M_B_DQ27
M_B_DQ26
BB42 DDR3_DQ1_4/DDR0_DQ7_4/DDR1_DQ3_4
DDR3_DQ1_3/DDR0_DQ7_3/DDR1_DQ3_3
DDR0_MA9/DDR2_CA0/DDR2_CA0/DDR2_CA6
DDR0_MA8/DDR0_CA2/DDR0_CA3/DDR0_CS0
BY53 M_A_A2
M_A_A4
BB41 CA50
M_B_DQ25 BD42 DDR3_DQ1_2/DDR0_DQ7_2/DDR1_DQ3_2 DDR0_MA7/DDR0_CA4/DDR0_CA5/DDR0_CA1 BY52 M_A_A3
12 M_A_A0 13 M_C_A0 M_B_DQ24 DDR3_DQ1_1/DDR0_DQ7_1/DDR1_DQ3_1 DDR0_MA6/DDR0_CA3/DDR0_CA4/DDR0_CS1 M_A_A5
BD41 BY50
12 M_A_A1 13 M_C_A1 DDR3_DQ1_0/DDR0_DQ7_0/DDR1_DQ3_0 DDR0_MA5/DDR0_CA5/DDR0_CA6/DDR0_CA0 M_A_CS#0
CD51
12 M_A_A2 13 M_C_A2 DDR0_MA4/DDR0_CS0/DDR0_CA2/DDR0_CA2 M_A_CS#1
CD53
12 M_A_A3 13 M_C_A3 DDR0_MA3/DDR0_CS1/DDR0_CS0/DDR0_CA3 BV47 M_B_CS#2
C 12 M_A_A4 13 M_C_A4 DDR0_MA2/DDR3_CS0/DDR3_CA2/DDR3_CA2 CE52 C
12 M_A_A5 13 M_C_A5 DDR0_MA1/NC/DDR0_CS1/DDR0_CA4 BV41
DDR0_MA0/NC/DDR3_CS1/DDR3_CA4
12 M_A_B0 13 M_C_B0 M_B_A2
BN50
12 M_A_B1 13 M_C_B1 DDR0_BG1/DDR2_CA2/DDR2_CA3/DDR2_CS0 M_B_A3
BL52
12 M_A_B2 13 M_C_B2 DDR0_BG0/DDR2_CA3/DDR2_CA4/DDR2_CS1
12 M_A_B3 13 M_C_B3 CB42 M_A_B5
12 M_A_B4 13 M_C_B4 DDR0_BA1/DDR1_CA5/DDR1_CA6/DDR1_CA0 M_B_B0
BV44
12 M_A_B5 13 M_C_B5 DDR0_BA0/DDR3_CA0/DDR3_CA0/DDR3_CA6 1D1V_S3
BT53 M_B_CS#1 20200410
DDR0_ACT#/DDR2_CS1/DDR2_CS0/DDR2_CA3 change part for part number update

1
BV45 M_B_CS#3 R503
DDR0_PAR/DDR3_CS1/DDR3_CS0/DDR3_CA3
12 M_B_DQ[31:0] M_B_DQ0 13 M_D_DQ[31:0] M_D_DQ0 M_A_ALERT_N
AU50 R501 1 2 0R0402-PAD-2-GP
M_B_DQ1 M_D_DQ1 DDR0_ALERT# AU49
M_B_DQ2 M_D_DQ2 DDR0_VREF_CA 470R2F-GP

2
M_B_DQ3 M_D_DQ3 E52
M_B_DQ4 M_D_DQ4 DDR_VTT_CTL DV47 SM_DRAMRST#_CPU R505 1 2 0R0402-PAD-1-GP SM_DRAMRST#
M_B_DQ5 M_D_DQ5 DRAM_RESET# C49 SM_RCOMP R502 1 2 100R2F-L1-GP-U
M_B_DQ6 M_D_DQ6 DDR_RCOMP
M_B_DQ7 M_D_DQ7
M_B_DQ8 M_D_DQ8 TGL-U-1-GP-U2
M_B_DQ9 M_D_DQ9
M_B_DQ10 M_D_DQ10 CPU1C 3 OF 21
M_B_DQ11 M_D_DQ11
M_B_DQ12 M_D_DQ12
M_B_DQ13 M_D_DQ13 LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL) DDR4/LP4/LP5/LP5 CMD
M_B_DQ14 M_D_DQ14 M_C_DQ7 AL53 Flip R41 M_D_CLK1
M_B_DQ15 M_D_DQ15 M_C_DQ6 AL52 DDR4_DQ0_7/DDR1_DQ0_7/DDR0_DQ4_7 DDR1_CLK_P1/DDR7_CLK_P/DDR7_CLK_P/DDR7_CLK_P R42 M_D_CLK1#
M_B_DQ16 M_D_DQ16 M_C_DQ5 AL50 DDR4_DQ0_6/DDR1_DQ0_6/DDR0_DQ4_6 DDR1_CLK_N1/DDR7_CLK_N/DDR7_CLK_N/DDR7_CLK_N M52 M_D_CLK0
M_B_DQ17 M_D_DQ17 M_C_DQ4 AL49 DDR4_DQ0_5/DDR1_DQ0_5/DDR0_DQ4_5 NC/DDR6_CLK_P/DDR6_CLK_P/DDR6_CLK_P M53 M_D_CLK0#
M_B_DQ18 M_D_DQ18 M_C_DQ3 AP53 DDR4_DQ0_4/DDR1_DQ0_4/DDR0_DQ4_4 NC/DDR6_CLK_N/DDR6_CLK_N/DDR6_CLK_N AC42 M_C_CLK1
M_B_DQ19 M_D_DQ19 M_C_DQ[7:0] M_C_DQ2 AP52 DDR4_DQ0_3/DDR1_DQ0_3/DDR0_DQ4_3
DDR4_DQ0_2/DDR1_DQ0_2/DDR0_DQ4_2
NC/DDR5_CLK_P/DDR5_CLK_P/DDR5_CLK_P
NC/DDR5_CLK_N/DDR5_CLK_N/DDR5_CLK_N
AC41 M_C_CLK1#
M_B_DQ20 M_D_DQ20 M_C_DQ1 AP50 Y52 M_C_CLK0
M_B_DQ21 M_D_DQ21 M_C_DQ0 AP49 DDR4_DQ0_1/DDR1_DQ0_1/DDR0_DQ4_1 DDR1_CLK_P0/DDR4_CLK_P/DDR4_CLKP/DDR4_CLK_P Y53 M_C_CLK0#
M_B_DQ22 M_D_DQ22 M_C_DQ15 AF53 DDR4_DQ0_0/DDR1_DQ0_0/DDR0_DQ4_0 DDR1_CLK_N0/DDR4_CLK_N/DDR4_CLK_N/DDR4_CLK_N
M_B_DQ23 M_D_DQ23 M_C_DQ14 AF52 DDR4_DQ1_7/DDR1_DQ1_7/DDR0_DQ5_7 R47 M_D_CKE2
M_B_DQ24 M_D_DQ24 M_C_DQ13 AF50 DDR4_DQ1_6/DDR1_DQ1_6/DDR0_DQ5_6 NC/DDR7_CKE0/DDR7_WCK_P/DDR7_WCK_P R45 M_D_CKE3
M_B_DQ25 M_D_DQ25 M_C_DQ12 AF49 DDR4_DQ1_5/DDR1_DQ1_5/DDR0_DQ5_5 NC/DDR7_CKE1/DDR7_WCK_N/DDR7_WCK_N K51 M_D_CKE0
M_B_DQ26 M_D_DQ26 M_C_DQ[15:8] M_C_DQ11 AH53 DDR4_DQ1_4/DDR1_DQ1_4/DDR0_DQ5_4
DDR4_DQ1_3/DDR1_DQ1_3/DDR0_DQ5_3
NC/DDR6_CKE0/DDR6_WCK_P/DDR6_WCK_P
NC/DDR6_CKE1/DDR6_WCK_N/DDR6_WCK_N
K53 M_D_CKE1
M_B_DQ27 M_D_DQ27 M_C_DQ10 AH52 AC47 M_C_CKE2
M_B_DQ28 M_D_DQ28 M_C_DQ9 AH50 DDR4_DQ1_2/DDR1_DQ1_2/DDR0_DQ5_2 NC/DDR5_CKE0/DDR5_WCK_P/DDR5_WCK_P AC45 M_C_CKE3
M_B_DQ29 M_D_DQ29 M_C_DQ8 AH49 DDR4_DQ1_1/DDR1_DQ1_1/DDR0_DQ5_1 NC/DDR5_CKE1/DDR5_WCK_N/DDR5_WCK_N W51 M_C_CKE0
M_B_DQ30 M_D_DQ30 M_C_DQ23 AR41 DDR4_DQ1_0/DDR1_DQ1_0/DDR0_DQ5_0 NC/DDR4_CKE0/DDR4_WCK_P/DDR4_WCK_P W53 M_C_CKE1
M_B_DQ31 M_D_DQ31 M_C_DQ22 AV42 DDR5_DQ0_7/DDR1_DQ2_7/DDR1_DQ4_7 NC/DDR4_CKE1/DDR4_WCK_N/DDR4_WCK_N
M_C_DQ21 AR42 DDR5_DQ0_6/DDR1_DQ2_6/DDR1_DQ4_6 P52 M_D_A4
M_C_DQ20 AV41 DDR5_DQ0_5/DDR1_DQ2_5/DDR1_DQ4_5 DDR1_CKE1/DDR6_CA4/DDR6_CA5/DDR6_CA1 J50 M_D_A5
12 M_B_DQS_DN[3:0] M_B_DQS_DN0 13 M_D_DQS_DN[3:0] M_D_DQS_DN0 M_C_DQ[23:16] M_C_DQ19 AR45 DDR5_DQ0_4/DDR1_DQ2_4/DDR1_DQ4_4
DDR5_DQ0_3/DDR1_DQ2_3/DDR1_DQ4_3
DDR1_CKE0/DDR6_CA5/DDR6_CA6/DDR6_CA0
M_B_DQS_DN1 M_D_DQS_DN1 M_C_DQ18 AV45 AE42 M_C_B1
B M_B_DQS_DN2 M_D_DQS_DN2 M_C_DQ17 AR47 DDR5_DQ0_2/DDR1_DQ2_2/DDR1_DQ4_2 DDR1_CS1/DDR5_CA1/DDR5_CA1/DDR5_CA5 AE47 B
M_B_DQS_DN3 M_D_DQS_DN3 M_C_DQ16 AV47 DDR5_DQ0_1/DDR1_DQ2_1/DDR1_DQ4_1 DDR1_CS0/NC/DDR5_CS1/DDR5_CA4
M_C_DQ31 AJ41 DDR5_DQ0_0/DDR1_DQ2_0/DDR1_DQ4_0 N42 M_D_B5
M_C_DQ30 AJ42 DDR5_DQ1_7/DDR1_DQ3_7/DDR1_DQ5_7 NC/DDR7_CA5/DDR7_CA6/DDR7_CA0 N45 M_D_B4
12 M_B_DQS_DP[3:0] M_B_DQS_DP0 13 M_D_DQS_DP[3:0] M_D_DQS_DP0 M_C_DQ29 DDR5_DQ1_6/DDR1_DQ3_6/DDR1_DQ5_6 NC/DDR7_CA4/DDR7_CA5/DDR7_CA1 M_D_B3
AL41 N44
M_B_DQS_DP1 M_D_DQS_DP1 M_C_DQ28 AL42 DDR5_DQ1_5/DDR1_DQ3_5/DDR1_DQ5_5 NC/DDR7_CA3/DDR7_CA4/DDR7_CS1 N47 M_D_B2
M_B_DQS_DP2 M_D_DQS_DP2 M_C_DQ[31:24] M_C_DQ27 AJ45 DDR5_DQ1_4/DDR1_DQ3_4/DDR1_DQ5_4
DDR5_DQ1_3/DDR1_DQ3_3/DDR1_DQ5_3
NC/DDR7_CA2/DDR7_CA3/DDR7_CS0
NC/DDR6_CS0/DDR6_CA2/DDR6_CA2
J53 M_D_CS#0
M_B_DQS_DP3 M_D_DQS_DP3 M_C_DQ26 AJ47 AC50 M_C_A1
M_C_DQ25 AL45 DDR5_DQ1_2/DDR1_DQ3_2/DDR1_DQ5_2 NC/DDR4_CA1/DDR4_CA1/DDR4_CA5 AC53 M_C_A0
M_C_DQ24 AL47 DDR5_DQ1_1/DDR1_DQ3_1/DDR1_DQ5_1 NC/DDR4_CA0/DDR4_CA0/DDR4_CA6
13 M_D_CLK0# M_D_DQ7 A43 DDR5_DQ1_0/DDR1_DQ3_0/DDR1_DQ5_0 K36 M_D_DQS_DP3
12 M_B_CLK0# 13 M_D_CLK0 M_D_DQ6 B43 DDR6_DQ0_7/DDR1_DQ4_7/DDR0_DQ6_7 DDR7_DQSP_1/DDR1_DQSP_7/DDR1_DQSP_7 K38 M_D_DQS_DN3
12 M_B_CLK0 13 M_D_CLK1# M_D_DQ5 DDR6_DQ0_6/DDR1_DQ4_6/DDR0_DQ6_6 DDR7_DQSN_1/DDR1_DQSN_7/DDR1_DQSN_7 M_D_DQS_DP2
D43 G44
12 M_B_CLK1# 13 M_D_CLK1 M_D_DQ4 DDR6_DQ0_5/DDR1_DQ4_5/DDR0_DQ6_5 DDR7_DQSP_0/DDR1_DQSP_6/DDR1_DQSP_6 M_D_DQS_DN2
E44 J44
12 M_B_CLK1 M_D_DQ3 A46 DDR6_DQ0_4/DDR1_DQ4_4/DDR0_DQ6_4 DDR7_DQSN_0/DDR1_DQSN_6/DDR1_DQSN_6 D39 M_D_DQS_DP1
12 M_B_CKE0
13
13
M_D_CKE0
M_D_CKE1
M_D_DQ[7:0] M_D_DQ2 B46 DDR6_DQ0_3/DDR1_DQ4_3/DDR0_DQ6_3
DDR6_DQ0_2/DDR1_DQ4_2/DDR0_DQ6_2
DDR6_DQSP_1/DDR1_DQSP_5/DDR0_DQSP_7
DDR6_DQSN_1/DDR1_DQSN_5/DDR0_DQSN_7
C39 M_D_DQS_DN1
M_D_DQ1 D46 C45 M_D_DQS_DP0
12 M_B_CKE1 13 M_D_CKE2 M_D_DQ0 DDR6_DQ0_1/DDR1_DQ4_1/DDR0_DQ6_1 DDR6_DQSP_0/DDR1_DQSP_4/DDR0_DQSP_6 M_D_DQS_DN0
E47 D45
12 M_B_CKE2 13 M_D_CKE3 M_D_DQ15 E38 DDR6_DQ0_0/DDR1_DQ4_0/DDR0_DQ6_0 DDR6_DQSN_0/DDR1_DQSN_4/DDR0_DQSN_6 AJ44 M_C_DQS_DP3
12 M_B_CKE3 M_D_DQ14 DDR6_DQ1_7/DDR1_DQ5_7/DDR0_DQ7_7 DDR5_DQSP_1/DDR1_DQSP_3/DDR1_DQSP_5 M_C_DQS_DN3
D38 AL44
13 M_D_CS#0 M_D_DQ13 DDR6_DQ1_6/DDR1_DQ5_6/DDR0_DQ7_6 DDR5_DQSN_1/DDR1_DQSN_3/DDR1_DQSN_5 M_C_DQS_DP2
B38 AV44
12 M_B_CS#0 13 M_D_CS#1 M_D_DQ12 A38 DDR6_DQ1_5/DDR1_DQ5_5/DDR0_DQ7_5 DDR5_DQSP_0/DDR1_DQSP_2/DDR1_DQSP_4 AR44 M_C_DQS_DN2
12
12
M_B_CS#1
M_B_CS#2
13
13
M_D_CS#2
M_D_CS#3
M_D_DQ[15:8] M_D_DQ11 E41 DDR6_DQ1_4/DDR1_DQ5_4/DDR0_DQ7_4
DDR6_DQ1_3/DDR1_DQ5_3/DDR0_DQ7_3
DDR5_DQSN_0/DDR1_DQSN_2/DDR1_DQSN_4
DDR4_DQSP_1/DDR1_DQSP_1/DDR0_DQSP_5
AG51 M_C_DQS_DP1
M_D_DQ10 D40 AG50 M_C_DQS_DN1
12 M_B_CS#3 M_D_DQ9 DDR6_DQ1_2/DDR1_DQ5_2/DDR0_DQ7_2 DDR4_DQSN_1/DDR1_DQSN_1/DDR0_DQSN_5 M_C_DQS_DP0
B40 AN51
13 M_D_A0 M_D_DQ8 A40 DDR6_DQ1_1/DDR1_DQ5_1/DDR0_DQ7_1 DDR4_DQSP_0/DDR1_DQSP_0/DDR0_DQSP_4 AN50 M_C_DQS_DN0
12 M_B_A0 13 M_D_A1 M_D_DQ23 G42 DDR6_DQ1_0/DDR1_DQ5_0/DDR0_DQ7_0 DDR4_DQSN_0/DDR1_DQSN_0/DDR0_DQSN_4
12 M_B_A1 13 M_D_A2 M_D_DQ22 DDR7_DQ0_7/DDR1_DQ6_7/DDR1_DQ6_7 M_C_B0
G41 AE44
12 M_B_A2 13 M_D_A3 M_D_DQ21 DDR7_DQ0_6/DDR1_DQ6_6/DDR1_DQ6_6 DDR1_ODT1/DDR5_CA0/DDR5_CA0/DDR5_CA6 M_C_CS#2
J41 AE45
12 M_B_A3 13 M_D_A4 M_D_DQ20 J42 DDR7_DQ0_5/DDR1_DQ6_5/DDR1_DQ6_5 DDR1_ODT0/DDR5_CS0/DDR5_CA2/DDR5_CA2
12
12
M_B_A4
M_B_A5
13 M_D_A5 M_D_DQ[23:16] M_D_DQ19 G45 DDR7_DQ0_4/DDR1_DQ6_4/DDR1_DQ6_4
DDR7_DQ0_3/DDR1_DQ6_3/DDR1_DQ6_3 DDR1_MA16/DDR5_CA4/DDR5_CA5/DDR5_CA1
AA47 M_C_B4
M_D_DQ18 J45 AA44 M_C_B3
13 M_D_B0 M_D_DQ17 DDR7_DQ0_2/DDR1_DQ6_2/DDR1_DQ6_2 DDR1_MA15/DDR5_CA3/DDR5_CA4/DDR5_CS1 M_C_B2
G47 AA45
12 M_B_B0 13 M_D_B1 M_D_DQ16 DDR7_DQ0_1/DDR1_DQ6_1/DDR1_DQ6_1 DDR1_MA14/DDR5_CA2/DDR5_CA3/DDR5_CS0 M_C_CS#3
J47 AE41
12 M_B_B1 13 M_D_B2 M_D_DQ31 DDR7_DQ0_0/DDR1_DQ6_0/DDR1_DQ6_0 DDR1_MA13/DDR5_CS1/DDR5_CS0/DDR5_CA3 M_D_A1
G38 P53
12 M_B_B2 13 M_D_B3 M_D_DQ30 DDR7_DQ1_7/DDR1_DQ7_7/DDR1_DQ7_7 DDR1_MA12/DDR6_CA1/DDR6_CA1/DDR6_CA5
G36 N51
12 M_B_B3 13 M_D_B4 M_D_DQ29 H36 DDR7_DQ1_6/DDR1_DQ7_6/DDR1_DQ7_6 DDR1_MA11/NC/DDR6_CS1/DDR6_CA4 U42 M_D_B1
12 M_B_B4 13 M_D_B5 M_D_DQ28 DDR7_DQ1_5/DDR1_DQ7_5/DDR1_DQ7_5 DDR1_MA10/DDR7_CA1/DDR7_CA1/DDR7_CA5 M_D_A0
H38 P50
12 M_B_B5 M_D_DQ[31:24] M_D_DQ27 N36 DDR7_DQ1_4/DDR1_DQ7_4/DDR1_DQ7_4
DDR7_DQ1_3/DDR1_DQ7_3/DDR1_DQ7_3
DDR1_MA9/DDR6_CA0/DDR6_CA0/DDR6_CA6
DDR1_MA8/DDR4_CA2/DDR4_CA3/DDR4_CS0
U53 M_C_A2
M_D_DQ26 L36 W50 M_C_A4
M_D_DQ25 L38 DDR7_DQ1_2/DDR1_DQ7_2/DDR1_DQ7_2 DDR1_MA7/DDR4_CA4/DDR4_CA5/DDR4_CA1 U52 M_C_A3
M_D_DQ24 N38 DDR7_DQ1_1/DDR1_DQ7_1/DDR1_DQ7_1 DDR1_MA6/DDR4_CA3/DDR4_CA4/DDR4_CS1 U50 M_C_A5
DDR7_DQ1_0/DDR1_DQ7_0/DDR1_DQ7_0 DDR1_MA5/DDR4_CA5/DDR4_CA6/DDR4_CA0 AA51 M_C_CS#0
DDR1_MA4/DDR4_CS0/DDR4_CA2/DDR4_CA2 AA53 M_C_CS#1
DDR1_MA3/DDR4_CS1/DDR4_CS0/DDR4_CA3 U47 M_D_CS#2
DDR1_MA2/DDR7_CS0/DDR7_CA2/DDR7_CA2 AC52
DDR1_MA1/NC/DDR4_CS1/DDR4_CA4 U41
DDR1_MA0/NC/DDR7_CS1/DDR7_CA4
12,13 SM_DRAMRST# M_D_A2
A K50 A
DDR1_BG1/DDR6_CA2/DDR6_CA3/DDR6_CS0 J52 M_D_A3
DDR1_BG0/DDR6_CA3/DDR6_CA4/DDR6_CS1
AA42 M_C_B5
DDR1_BA1/DDR5_CA5/DDR5_CA6/DDR5_CA0 U44 M_D_B0
DDR1_BA0/DDR7_CA0/DDR7_CA0/DDR7_CA6
N53 M_D_CS#1 20200410
DDR1_ACT#/DDR6_CS1/DDR6_CS0/DDR6_CA3 change part for part number update
U45 M_D_CS#3
DDR1_PAR/DDR7_CS1/DDR7_CS0/DDR7_CA3
AU53 M_B_ALERT_N R504 1 2 0R0402-PAD-2-GP
DDR1_ALERT# AU52 <Core Design>
DDR1_VREF_CA

TGL-U-1-GP-U2 Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU (DDR)
Size Document Number Rev
Custom Hellcat 15'' Upsell TGL -1
Date: Monday, August 03, 2020 Sheet 5 of 105
5 4 3 2 1