Professional Documents
Culture Documents
D D
2010-02-10
REV : A00
B B
DY : Nopop Component
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 1 of 88
5 4 3 2 1
5 4 3 2 1
RGB CRT
Intel DDRIII 800/1066 Channel A DDRIII Slot 0 SYSTEM DC/DC
CRT 55 18
800/1066 TPS51116
GM45 50
INPUTS OUTPUTS
AGTL + CPU I/F
DDRIII 800/1066 Channel B +1.5V_SUS
DDR Memory I/F
DDRIII Slot 1 +PWR_SRC +0.75V_DDR_VTT
19 +V_DDR_REF
800/1066
LCD 54
LVDS(Dual Channel) External Graphics
10,11,12,13,14,15 MAXIM CHARGER
C BQ24745 C
INPUTS OUTPUTS
DMIx4 C-LINK +DC_IN +PWR_SRC
10/100 NIC +PBATT
RJ45 26
Atheros
AR8132 CONN SYSTEM DC/DC
Switches 42
PCIE x 2 26
SATA INPUTS OUTPUTS
Intel
I/O Board
Connector
Mini-Card +1.5V_SUS +1.5V_RUN
802.11a/b/g +5V_ALW +5V_RUN
ICH9-M +3.3V_ALW +3.3V_RUN
KBC
SPI
NUVOTON
SATA
SATA
NPCE781BA0DX 37
A DJ1 A
2CH SPEAKER
Flash ROM Touch Int. Thermal
HDD ODD
2MB 62 PAD KB EMC2102 Wistron Corporation
59 59 39 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
67 67 25 Taipei Hsien 221, Taiwan, R.O.C.
60
Title
Block Diagram
Size Document Number Rev
Fan 58
www.vinafix.vn
A3 A00
DJ1 Montevina UMA
Date: W ednesday, February 24, 2010 Sheet 2 of 88
5 4 3 2 1
5 4 3 2 1
+PWR_SRC
Adapter
Charger
BQ24745 +VCC_CORE +1.05V_VCCP
47 49 +V_DDR_REF +0.75V_DDR_VTT
Battery +VCHGR +1.5V_SUS 50
50 50
C C
FSD8880
G9091
G5285T11U RTS5159 RT9198 RTL8103T
+3.3V_CRT_LDO
15 +LCDVDD +3.3V_RUN_CARD +1.8V_NB_S0 +1.2V_LOM
54
32 15
A DJ1 A
Power Shape
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Regulator LDO Switch Title
Size
Power Block Diagram
Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 3 of 88
5 4 3 2 1
A B C D E
‧ ‧ ‧
+3.3V_RUN
SRN4K7J-8-GP
‧ SRN4K7J-8-GP SRN10KJ-5-GP
+KBC_PWR
SMBus Address:A0
‧
2N7002SPT
DIMM 2
‧
‧
ICH_SMBCLK
SCL
ICH_SMBDATA SRN4K7J-8-GP
SDA
SMBus Address:A4
SCL1 BAT_SCL
SRN100J-3-GP
PBAT_SMBCLK1
Battery Conn.
CLK_SMB
2
ICH_SMBCLK
WLAN
SMB_CLK +KBC_PWR
‧ 2
‧ SRN4K7J-8-GP
‧ SRN4K7J-8-GP
Thermal
‧
‧
THERM_SCL SCL
SMBus address:7A
THERM_SDA SDA
GPIO61/SCL2 KBC_SCL1
2N7002DW-1-GP
GPIO62/SDA2 KBC_SDA1
+3.3V_RUN
‧
SRN2K2J-1-GP
3 3
‧
‧
DDC1CLK LDDC_CLK
‧ ‧
+3.3V_RUN
VGA
SRN2K2J-1-GP
‧ SRN2K2J-1-GP
‧ ‧
‧ ‧
DDC2CLK GMCH_DDCCLK DDC_CLK_CON
DDC2DATA GMCH_DDCDATA DDC_DATA_CON CRT CONN
2N7002DW-1-GP
4 4
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
www.vinafix.vn
A2 DJ1 Montevina UMA A00
Date: Wednesday, February 24, 2010 Sheet 4 of 88
A B C D E
A B C D E
THRMDC
Codec
Thermal
92HD79B1
EMC2102
DP2 EMC2102_DP2
HP0_PORT_A_L
MIC
PMBS3904-1-GP
SC470P50V3JN-2GP HP0_PORT_A_R
3 3
DP3 EMC2102_DP3
PMBS3904-1-GP
SC470P50V3JN-2GP
DN3 EMC2102_DN3
HW T8 sensor PORTC_L
PORTC_R
Analog
VREFOUT_C MIC
4 4
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
www.vinafix.vn
Size Document Number Rev
Custom
DJ1 Montevina UMA A00
Date: Wednesday, February 24, 2010 Sheet 5 of 88
A B C D E
A B C D E
ICH9M Functional Strap Definitions ICH9 Integrated pull-up Cantiga chipset and ICH9M I/O controller
ICH9 EDS 642879 Rev.2.3 and pull-down Resistors Hub strapping configuration
Signal Usage/When Sampled Comment ICH9 EDS 642879 Rev.2.3 Montevina Platform Design guide 355648 Rev.2.3
HDA_SDOUT XOR Chain Entrance / Allows entrance to XOR Chain testing when TP3 SIGNAL Resistor Type/Value Pin Name Strap Description Configuration
PCI Express* pulled low at rising edge of PWROK. When TP3
Port Config 1 bit 1 not pulled low at rising edge of PWROK, sets CL_CLK[1:0] PULL-UP 20K CFG2:0 FSB Frequency 000 = FSB1066
1 (Port 1-4), bit 1 of RPC.PC (Chipset Config Registers: Offset 010 = FSB800 1
CL_DATA[1:0] PULL-UP 20K 011 = FSB667
Rising Edge of PWROK 224h).This signal has a weak internal pull-down.
CL_RST0# PULL-UP 10K Others = Reserved
HDA_SYNC PCI Express Port Config This signal has a weak internal pull-down.
1 bit 0 (Port 1-4), Sets bit 0 of RPC.PC (Chipset Config Registers: DPRSLPVR/GPIO16 PULL-DOWN 20K
Rising Edge of PWROK. Offset 224h) CFG5 DMI x2 Select 0 = DMI x2
HDA_BIT_CLK PULL-DOWN 20K 1 = DMI x4 (Default)
GNT2#/ PCI Express Port This signal has a weak internal pull-up.
GPIO53 Config 2 bit 2 Sets bit 2 of RPC.PC2 (Chipset Config HDA_DOCK_EN#/GPIO33 PULL-UP 20K
(Port 5-6), Rising Edge Registers:Offset 0224h) when sampled low. CFG6 ITPM Host Interface 0 = The iTPM Host Interface is enabled (Note 2)
HDA_RST# PULL-DOWN 20K 1 = The iTPM Host Interface is disabled (default)
of PWROK
GPIO20 Reserved, Rising Edge This signal has a weak internal pull-down. HDA_SDIN[3:0] PULL-DOWN 20K 0 = Intel Management Engine Crypto Transport
of PWROK NOTE: This signal should not be pulled high CFG7 Intel Management Layer Security (TLS) cipher suite with no
HDA_SDOUT PULL-DOWN 20K engine crypto strap confidentiality
GNT1#/ ESI Strap (Server Only), Tying this strap low configures DMI for ESIcompatible
GPIO51 Rising Edge of PWROK. operation. This signal has a weak internal HDA_SYNC PULL-DOWN 20K 1 = Intel Management Engine Crypto TLS cipher
pull-up. suite with confidentiality (default)
GNT0#, GNT[3:1]#/ PULL-UP 20K
NOTE: ESI compatible mode is for server platforms GPIO[55,53,51] 0 = Reverse Lanes, 15->0, 14->1 etc.
only. This signal should not be pulled low for CFG9 PCIE Graphics Lane 1 = Normal operation (default): Lane Numbered
desktop and mobile. GPIO20 PULL-DOWN 20K in Order
GNT3#/ Top-Block Swap Sampled low: this indicates that the GPIO49 PULL-UP 20K
GPIO55 override. Rising Edge system is strapped to the “top-block swap”
of PWROK. mode (IntelR ICH9 inverts A16 for all LAD[3:0]# / FHW[3:0]# PULL-UP 20K CFG10 PCIE Loopback enable 0 = Enable (Note 3)
1 = Disable (Default)
cycles targeting BIOS space). The status of LAN_RXD[2:0] PULL-UP 20K
this strap is readable via the Top Swap bit
2 (Chipset Config Registers:Offset 3414h: LDRQ0 PULL-UP 20K 2
bit 0). Note that software will not be able CFG12 ALLZ 0 =ALLZ mode enabled (Note 3)
to clear the Top-Swap bit until the system LDRQ1 / GPIO23 PULL-UP 20K
1 = Disable (Default)
is rebooted without GNT3# being pulled down. PME# PULL-UP 20K
0 = XOR mode enabled (Note 3)
Boot BIOS Destination Controllable via Boot BIOS Destination PWRBTN# PULL-UP 20K CFG13 XOR 1 = Disable (Default)
GNT0# Selection 1, bit (Chipset Config Registers:Offset 3410h:bit 11).
Rising Edge of PWROK. This strap is used in conjunction with Boot BIOS SATALED# PULL-UP 15K
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
Destination Selection 0 strap. SPI_CS1# / 1 = Dynamic ODT Enabled (Default)
GPIO58 (Desktop Only) / PULL-UP 20K
Bit11 Bit 10 Boot BIOS CLGPIO6 (Digital Office Only)
(GNT0#) (SPI_CS1#) Destination CFG19 DMI Lane Reversal 0 = Normal operation (Default): Lane Numbered in
Order
0 1 SPI SPI_MOSI PULL-DOWN 20K 1 = Reverse Lanes
1 0 PCI DMI x4 mode [MCH->ICH]: (3->0, 2->1, 1->2 and 0->3)
1 1 LPC DMI x2 mode [MCH->ICH]: (3->0, 2->1)
0 0 Reserved SPI_MISO PULL-UP 20K
Digital Display Port 0 = Only digital DisplayPort (SDVO/DP/HDMI) or
CFG20 (SDVO/DP/HDMI) PCIe is operational (default)
SPI_CS1#/ Boot BIOS Destination Controllable via Boot BIOS Destination SPKR PULL-DOWN 20K Concurrent with PCIe 1 = Digital DisplayPort (SDVO/DP/HDMI) and
GPIO58 Selection 0, bit (Chipset Config Registers:Offset 3410h:bit 10).
Rising Edge of CLPWROK. This strap is used in conjunction with Boot BIOS PCIe are operating simultaneously via the PEG port
Destination Selection 1 strap. TACH[3:0] PULL-UP 20K
SDVO
_CTRLDATA SDVO Present 0 = No SDVO/HDMI/DP interface disabled (default)
Bit11 Bit 10 Boot BIOS TP3 PULL-UP 20K (Note4) 1 = SDVO/HDMI/DP interface enabled
(GNT0#) (SPI_CS1#) Destination
3 0 1 SPI USB[11:0][P,N] PULL-DOWN 15K 0 = LFP Disabled (Default) 3
1 0 PCI L_DDC_DATA Local Flat Panel
(LFP) Present 1 = LFP Card Present; PCIE disabled
1
0
1
0
LPC
Reserved PCIE Routing
DDPC Digital Display 0 = Digital display (HDMI/DP) device absent
SATALED# PCI Express Lane Signal has weak internal pull-up. Sets bit 27 of _CTRLDATA Present (default)
Reversal (Lanes 1-4).
Rising Edge of PWROK.
MPC.LR (Device 28: Function 0: Offset D8) LANE1 (Note4) 1 = Digital display (HDMI/DP) Device Present
CFG4:3
Sampled high: this indicates that the system
is strapped to the “No Reboot” mode (ICH9 will LANE2 MiniCard WLAN CFG8
CFG11
No Reboot, disable the TCO Timer system reboot feature). The CFG14 Reserved
SPKR Rising Edge of PWROK. status of this strap is readable via the NO REBOOT LANE3 LAN CFG15
bit (Chipset Config Registers:Offset 3410h:bit 5). CFG17
USB Table CFG18
USB Pair Device
TP3 XOR Chain Entrance. This signal should not be pull low unless using NOTE:
Rising Edge of PWROK. XOR Chain testing. 0 USB0 (I/O Board)
1. All strap signals are sampled with respect to the leading edge of the GMCH Power OK
GPIO33 / 1 USB1 (I/O Board 17") (PWROK) signal.
HDA_DOCK_ Flash Descriptor Sampled low: the Flash Descriptor Security will be 2. iTPM can be disabled by a ‘Soft-Strap’ option in the Flash-descriptor section of the
EN# Security Override Strap. overridden. Sampled high: the security measures will be 2 USB2 Firmware. This ‘Soft-Strap’ is activated only after enabling iTPM via CFG6.
(Mobile Rising Edge of PWROK. in effect. This strap should only be enabled in 3. Only one of the CFG10/CFG12/CFG13 straps can be enabled at any time.
manufacturing environments. 3 USB3
Only) 4. DDPC_CTRL_DATA & SDVO_CTRL_DATA straps should both be high to enable Display Port.
4 BLUETOOTH
DMI Termination The signal is required to be high for mobile
4 GPIO49 4
Voltage. Rising Edge applications. 5 RESERVED DJ1
of CLPWROK.
6 WLAN
Sampled low: the Integrated TPM will be disabled. 7 RESERVED Wistron Corporation
SPI_MOSI Integrated TPM 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Sampled high: the MCH TPM enable strap is sampled low Taipei Hsien 221, Taiwan, R.O.C.
(Moble Enable. Rising Edge and the TPM Disable bit is clear, the Integrated TPM 8 RESERVED
Only) of CLPWROK. will be enabled. Title
9 RESERVED
NOTE: This signal is required to be floating or pulled
low for desktop applications. 10 Card Reader Table of Content
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Size Document Number Rev
Custom
11 CAMERA DJ1 Montevina UMA A00
Date: Wednesday, February 24, 2010 Sheet 6 of 88
A B C D E
5 4 3 2 1
SSID = CLOCK
3D3V_S0_CK505 1D05V_CK505_IO MINI1_CLKREQ# R702 1 2 10KR2J-3-GP
1D05V_CK505_IO +3.3V_RUN
+1.05V_VCCP
R704
1 2
SC1U10V3KX-3GP
CLK_XTAL_IN
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
Do Not Stuff
1
1
C702
C704
C705
C706
C707
C708
C709
X701
1 2 CLK_XTAL_OUT
2
2
D X-14D31818M-37GP D
1
C710 C711
16
46
62
23
19
27
43
52
33
56
U701
9
SC15P50V2JN-2-GP
2
SC15P50V2JN-2-GP
VDD_REF
VDD_48
VDD_SRC
VDD_CPU
VDD_PLL3
VDD_IO
VDD_PLL3_IO
VDD_SRC_IO
VDD_SRC_IO
VDD_SRC_IO
VDD_CPU_IO
VDD_PCI
61 CLK_CPU_BCLK CLK_CPU_BCLK 8
CPUT0 CLK_CPU_BCLK#
CPUC0 60 CLK_CPU_BCLK# 8
+3.3V_RUN 3D3V_S0_CK505 3 58 CLK_MCH_BCLK
XN CPUT1 CLK_MCH_BCLK 10
32 CLK_48M_CARD R705 1 2 22R2J-2-GP 2 57 CLK_MCH_BCLK# CLK_MCH_BCLK# 10
R706 XOUT CPUC1
1 2 SRCT8/CPU2_ITPT 54
R701 2 FSA
SC1U10V3KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SC10U6D3V5KX-1GP
22 CLK_48M_ICH 1 17 53
Do Not Stuff
22R2J-2-GP USB_48/FSA SRCC8/CPU2_ITPC
Do Not Stuff
1
1
C713
C714
C715
C716
C701
C717
C718
C719
1
C712 DY2Do Not Stuff 51 CLK_PCIE_LAN
DY 45
SRCT7/CR#_F
50 CLK_PCIE_LAN#
CLK_PCIE_LAN 76
CLK_PCIE_LAN# 76
2
2
22 H_STP_PCI# PC_STOP# SRCC7/CR#_E
22 H_STP_CPU#
44 CPU_STOP#
48 CLK_PCIE_ICH CLK_PCIE_ICH 21
SRCT6 CLK_PCIE_ICH#
SRCC6 47 CLK_PCIE_ICH# 21
28 CLK_PCIE_SATA CLK_PCIE_SATA 20
SRCT2/SATAT CLK_PCIE_SATA#
SRCC2/SATAC 29 CLK_PCIE_SATA# 20
FSB 64
R711 1 FSB/TEST_MODE
22 CLK_14M_ICH 2 33R2J-2-GP FSC 5 REF0/FSC/TEST_SEL
24 MCH_SSCDREFCLK MCH_SSCDREFCLK 11
Do Not Stuff
Do Not Stuff
Do Not Stuff
SRCT1/LCDT_100/27M_NSS MCH_SSCDREFCLK#
55 NC#55 SRCC1/LCDT_100/27M_SS 25 MCH_SSCDREFCLK# 11
1
1
C720
C721
C722
CLK_MCH_DREFCLK
VSS_PLL3
20
DY DY DY
VSS_SRC
VSS_SRC
VSS_SRC
VSS_CPU
VSS_REF
SRCT0/DOT96T CLK_MCH_DREFCLK 11
VSS_PCI
CLK_MCH_DREFCLK#
VSS_48
21
VSS_IO
CLK_MCH_DREFCLK# 11
2
SRCC0/DOT96C
GND
SLG8SP513VTR-GP
18
15
1
22
30
36
49
59
26
65
Main = 71.08513.003(SLG)
Second = 71.09356.00W(ICS)
B B
3D3V_S0_CK505 3D3V_S0_CK505
1
27_SEL
R712 ITP_EN Output R713
2
10KR2J-3-GP 10KR2J-3-GP
PCI2_TME Output R714
0 SRC8
10KR2J-3-GP
2
1
1
R715 R716
DY Do Not Stuff Do Not Stuff 1 Overclocking of CPU and SRC not allowed
DY
2
0 96M 100M
1 100M 27M
SEL2 SEL1 SEL0
CPU FSB R717 1 2 10KR2J-3-GP FSC
A FSC FSB FSA 8 CPU_BSEL2
DJ1
A
R718 1 2 Do Not Stuff FSB
8 CPU_BSEL1
1 0 1 100M X
133M 533M
8 CPU_BSEL0
R719 1 2 2K2R2J-2-GP FSA
Wistron Corporation
0 0 1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
R720 1 2 1KR2J-1-GP Taipei Hsien 221, Taiwan, R.O.C.
0 1 1 166M 667M MCH_CLKSEL0 11
R721 1 2 1KR2J-1-GP Title
0 1 0 200M 800M MCH_CLKSEL1 11
www.vinafix.vn
Size Document Number Rev
Custom
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 7 of 88
5 4 3 2 1
5 4 3 2 1
SSID = CPU
CPU1A 1 OF 4 1 TP801
H_A#3 J4 H1 H_ADS# 10
D H_A#4 A3# ADS# D
L5 A4# BNR# E2 H_BNR# 10
H_A#5 L4 G5 H_BPRI# 10
A5# BPRI#
ADDR GROUP 0
H_A#6 K5
H_A#[35..3] H_A#7 A6#
10 H_A#[35..3] M3 A7# DEFER# H5 H_DEFER# 10
H_A#8 N2 F21
CONTROL
A8# DRDY# H_DRDY# 10
H_A#9 J1 E1 H_DBSY# 10
H_A#10 A9# DBSY#
N3 A10#
H_A#11 P5 F1 H_BREQ#0 10
H_A#12 A11# BR0# H_DINV#[3..0]
P2 A12# H_DINV#[3..0] 10
H_A#13 L2 D20 CPU_IERR# R802 1 2 56R2J-4-GP +1.05V_VCCP
H_A#14 A13# IERR# H_DSTBN#[3..0]
P4 A14# INIT# B3 H_INIT# 20 H_DSTBN#[3..0] 10
H_A#15 P1
H_A#16 A15# H_DSTBP#[3..0]
R1 A16# LOCK# H4 H_LOCK# 10 H_DSTBP#[3..0] 10
10 H_ADSTB#0 M1 ADSTB0# H_CPURST# 10
C1 H_CPURST# H_D#[63..0]
10 H_REQ#[4..0] RESET# H_RS#[2..0] 10 H_D#[63..0] 10
H_REQ#0 K3 F3 H_RS#0
H_REQ#1 REQ0# RS0# H_RS#1
H2 REQ1# RS1# F4
H_REQ#2 K2 G3 H_RS#2
H_REQ#3 REQ2# RS2#
J3 REQ3# TRDY# G2 H_TRDY# 10
H_REQ#4 L1 REQ4# CPU1B 2 OF 4
HIT# G6 H_HIT# 10
H_A#17 Y2 E4 H_HITM# 10 H_THERMDA
H_A#18 A17# HITM# H_D#0 H_D#32
U5 A18# E22 D0# D32# Y22
1
H_A#19 R3 AD4 H_D#1 F24 AB24 H_D#33
H_A#20 A19# BPM0# C849 H_D#2 D1# D33# H_D#34
W6 AD3 E26 V24
DY
XDP/ITP SIGNALS
H_A#21 A20# ADDR GROUP 1 BPM1# Do Not Stuff H_D#3 D2# D34# H_D#35
U4 AD1 G22 V26
2
H_A#22 A21# BPM2# H_THERMDC H_D#4 D3# D35# H_D#36
Y5 A22# BPM3# AC4 F23 D4# D36# V23
DATA GRP0
DATA GRP2
H_A#23 U1 AC2 H_D#5 G25 T22 H_D#37
H_A#24 A23# PRDY# ITP_BPM#5 H_D#6 D5# D37# H_D#38
R4 A24# PREQ# AC1 H_THERMDA, H_THERMDC routing together, E25 D6# D38# U25
C
H_A#25 T5 AC5 ITP_TCK H_D#7 E23 U23 H_D#39
H_A#26 T3
A25# TCK
AA6 ITP_TDI Trace width / Spacing = 10 / 10 mil H_D#8 K24
D7# D39#
Y25 H_D#40
C
DATA GRP3
DATA GRP1
20 H_SMI# A3 H_D#22 L22 AD20 H_D#54
SMI# H_D#23 D22# D54# H_D#55
M23 D23# D55# AE22
RSVD_CPU_1 M4 H_D#24 P25 AF23 H_D#56
TP802 RSVD#M4 D24# D56#
RSVD_CPU_2 N5 H_D#25 P23 AC25 H_D#57
TP803 RSVD#N5 D25# D57#
RSVD_CPU_3 T2 H_D#26 P22 AE21 H_D#58
RESERVED
2
RSVD_CPU_8 D22 H_D#31 N25 AC23 H_D#63
TP809 RSVD#D22 D31# D63#
B RSVD_CPU_9 D3 R806 L26 AE25 H_DSTBN#3 10 B
TP810 RSVD#D3 10 H_DSTBN#1 DSTBN1# DSTBN3#
RSVD_CPU_10 F6 1KR2F-3-GP M26 AF24 H_DSTBP#3 10
TP811 RSVD#F6 10 H_DSTBP#1 DSTBP1# DSTBP3#
10 H_DINV#1 N24 DINV1# DINV3# AC20 H_DINV#3 10
RSVD_CPU_11 B1
TP812
1
KEY_NC CPU_GTLREF0 COMP0 R807 27D4R2F-L1-GP
AD26 GTLREF COMP0 R26 1 2
BGA479-SKT6-GPU7 R808 1 2 Do Not Stuff TEST1 C23 MISC U26 COMP1 R809 1 2 54D9R2F-L1-GP
DY TEST1 COMP1
1
1
62.10079.001 R810 1 2 Do Not Stuff TEST2 D25 AA1 COMP2 R811 1 2 27D4R2F-L1-GP
R812 C801 R813 1 DY 2 Do Not Stuff CPU_TEST3 C24
TEST2 COMP2
Y1 COMP3 R814 1 2 54D9R2F-L1-GP
2KR2F-3-GP SC1KP50V2KX-1GP DY AF26
TEST3 COMP3
2 R815 1 TEST4
2 Do Not Stuff CPU_TEST5 AF1 E5
DY A26
TEST5 DPRSTP#
B5
H_DPRSTP# 11,20,47
H_DPSLP# 20
2
TEST6 DPSLP#
DPW R# D24 H_DPWR# 10
7 CPU_BSEL0 B22 BSEL0 PW RGOOD D6 H_PWRGOOD 20,42
7 CPU_BSEL1 B23 BSEL1 SLP# D7 H_CPUSLP# 10
+1.05V_VCCP C21 AE6
7 CPU_BSEL2 BSEL2 PSI# PSI# 47
A ITP_DBRESET# R825 1 A
2 Do Not Stuff
DY DJ1
www.vinafix.vn
Size Document Number Rev
Custom
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 8 of 88
5 4 3 2 1
5 4 3 2 1
SSID = CPU
+VCC_CORE
CPU1D 4 OF 4
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
A4 VSS VSS P6
1
C902
C901
C920
C903
C904
C905
C906
C907
C908
C909
A8 VSS VSS P21
C910 A11 P24
DY DY DY DY DY DY DY DY SC10U6D3V5KX-1GP A14
VSS VSS
R2
2
VSS VSS
A16 VSS VSS R5
A19 VSS VSS R22
D D
A23 VSS VSS R25
+VCC_CORE +VCC_CORE AF2 T1
VSS VSS
B6 VSS VSS T4
B8 VSS VSS T23
CPU1C3 OF 4 B11 T26
+VCC_CORE VSS VSS
B13 VSS VSS U3
A7 VCC VCC AB20 B16 VSS VSS U6
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
A9 AB7 B19 U21
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
VCC VCC VSS VSS
A10 VCC VCC AC7 B21 VSS VSS U24
A12 VCC VCC AC9 B24 VSS VSS V2
1
C921
C911
C912
C913
C914
C915
C916
C922
C917
C918
A13 VCC VCC AC12 C5 VSS VSS V5
A15 AC13 C919 C8 V22
A17
VCC VCC
AC15
DY DY DY DY DY DY SC10U6D3V5KX-1GP C11
VSS VSS
V25
2
VCC VCC VSS VSS
A18 VCC VCC AC17 C14 VSS VSS W1
A20 VCC VCC AC18 C16 VSS VSS W4
B7 VCC VCC AD7 C19 VSS VSS W 23
B9 VCC VCC AD9 C2 VSS VSS W 26
B10 VCC VCC AD10 C22 VSS VSS Y3
B12 VCC VCC AD12 C25 VSS VSS Y6
B14 AD14 +VCC_CORE D1 Y21
VCC VCC VSS VSS
B15 VCC VCC AD15 D4 VSS VSS Y24
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
B17 AD17 D8 AA2
Do Not Stuff
Do Not Stuff
VCC VCC VSS VSS
B18 VCC VCC AD18 D11 VSS VSS AA5
B20 VCC VCC AE9 D13 VSS VSS AA8
1
C923
C924
C925
C926
C927
C928
C929
C930
C931
C9 VCC VCC AE10 D16 VSS VSS AA11
C10 AE12 C932 D19 AA14
C12
VCC VCC
AE13
DY DY SC22U6D3V5MX-2GP D23
VSS VSS
AA16
2
VCC VCC VSS VSS
C13 VCC VCC AE15 D26 VSS VSS AA19
C15 VCC VCC AE17 E3 VSS VSS AA22
C C17 VCC VCC AE18 E6 VSS VSS AA25 C
C18 VCC VCC AE20 E8 VSS VSS AB1
D9 VCC VCC AF9 E11 VSS VSS AB4
D10 VCC VCC AF10 E14 VSS VSS AB8
D12 VCC VCC AF12 E16 VSS VSS AB11
D14 VCC VCC AF14 E19 VSS VSS AB13
D15 VCC VCC AF15 E21 VSS VSS AB16
D17 VCC VCC AF17 E24 VSS VSS AB19
D18 VCC VCC AF18 F5 VSS VSS AB23
E7 AF20 +1.05V_VCCP F8 AB26
VCC VCC VSS VSS
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
SCD1U16V2KX-3GP
SCD1U10V2KX-5GP
SCD1U16V2KX-3GP
SCD1U10V2KX-5GP
E10 G21 F13 AC6
Do Not Stuff
VCC VCCP VSS VSS
E12 VCC VCCP V6 F16 VSS VSS AC8
1
1
C933
C934
C935
C936
C938
C937
E13 VCC VCCP J6 F19 VSS VSS AC11
TC901
E15 K6 F2 AC14
E17
VCC VCCP
M6
DY F22
VSS VSS
AC16
2
2
VCC VCCP VSS VSS
E18 J21 F25 AC19
2
VCC VCCP VSS VSS
E20 VCC VCCP K21 G4 VSS VSS AC21
F7 VCC VCCP M21 G1 VSS VSS AC24
F9 VCC VCCP N21 G23 VSS VSS AD2
F10 VCC VCCP N6 G26 VSS VSS AD5
F12 VCC VCCP R21 H3 VSS VSS AD8
F14 VCC VCCP R6 H6 VSS VSS AD11
F15 VCC VCCP T21 H21 VSS VSS AD13
F17 VCC VCCP T6 layout note: "+1.5V_VCCA" H24 VSS VSS AD16
F18 VCC VCCP V21
as short as possible +1.5V_VCCA +1.5V_RUN
J2 VSS VSS AD19 NCTF
F20 W 21 J5 AD22
AA7
VCC VCCP
J22
VSS VSS
AD25
PIN
VCC VSS VSS CPU_GND1
AA9 VCC VCCA B26 1 R901 2 J25 VSS VSS AE1 TP902
AA10 C26 Do Not Stuff K1 AE4
VCC VCCA VSS VSS
B AA12 VCC CPU_VID[6..0] 47 K4 VSS VSS AE8 B
AA13 AD6 CPU_VID0 K23 AE11
VCC VID0 VSS VSS
1
A A
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CPU-Power(2/2)
www.vinafix.vn
Size Document Number Rev
Custom
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 9 of 88
5 4 3 2 1
5 4 3 2 1
SSID = MCH
NB1A 1 OF 10 H_A#[35..3]
D H_A#[35..3] 8 D
H_D#[63..0] A14 H_A#3
8 H_D#[63..0] H_A#_3
H_D#0 F2 C15 H_A#4
H_D#1 H_D#_0 H_A#_4 H_A#5
G8 H_D#_1 H_A#_5 F16
H_D#2 F8 H13 H_A#6
H_D#3 H_D#_2 H_A#_6 H_A#7
E6 H_D#_3 H_A#_7 C18
H_D#4 G2 M16 H_A#8
H_D#5 H_D#_4 H_A#_8 H_A#9
H6 H_D#_5 H_A#_9 J13
H_D#6 H2 P16 H_A#10
H_D#7 H_D#_6 H_A#_10 H_A#11
F6 H_D#_7 H_A#_11 R16
H_D#8 D4 N17 H_A#12
H_D#9 H_D#_8 H_A#_12 H_A#13
H3 H_D#_9 H_A#_13 M13
H_D#10 M9 E17 H_A#14
H_D#11 H_D#_10 H_A#_14 H_A#15
M11 H_D#_11 H_A#_15 P17
H_D#12 J1 F17 H_A#16
H_D#13 H_D#_12 H_A#_16 H_A#17
J2 H_D#_13 H_A#_17 G20
H_D#14 N12 B19 H_A#18
H_D#15 H_D#_14 H_A#_18 H_A#19
J6 H_D#_15 H_A#_19 J16
H_D#16 P2 E20 H_A#20
H_D#17 H_D#_16 H_A#_20 H_A#21
L2 H_D#_17 H_A#_21 H16
H_D#18 R2 J20 H_A#22
H_D#19 H_D#_18 H_A#_22 H_A#23
N9 H_D#_19 H_A#_23 L17
H_D#20 L6 A17 H_A#24
H_D#21 H_D#_20 H_A#_24 H_A#25
M5 H_D#_21 H_A#_25 B17
H_D#22 J3 L16 H_A#26
H_D#23 H_D#_22 H_A#_26 H_A#27
N2 H_D#_23 H_A#_27 C21
H_D#24 R1 J17 H_A#28
H_D#25 H_D#_24 H_A#_28 H_A#29
N5 H_D#_25 H_A#_29 H20
H_D#26 N6 B18 H_A#30
H_D#27 H_D#_26 H_A#_30 H_A#31
P13 H_D#_27 H_A#_31 K17
C
H_D#28 N8 B20 H_A#32 C
H_D#29 H_D#_28 H_A#_32 H_A#33
L7 H_D#_29 H_A#_33 F21
+1.05V_VCCP H_D#30 N10 K21 H_A#34
H_D#31 H_D#_30 H_A#_34 H_A#35
H_SWING routing Trace width and M3 H_D#_31 H_A#_35 L20
H_D#32 Y3
Spacing use 10 / 20 mil H_D#_32
1
HOST
H_D#_38 H_BREQ# H_BREQ#0 8
500 mil ( MAX ) H_SWING H_D#39 W2 H_D#_39 H_DEFER# E9 H_DEFER# 8
H_D#40 AA8 B10 H_DBSY# 8
H_D#_40 H_DBSY#
1
CANTIGA-GM-GP-U-NF
1
R1005
2KR2F-3-GP C1001
DY Do Not Stuff
2
2
A A
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cantiga-Host(1/6)
www.vinafix.vn
Size Document Number Rev
Custom
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 10 of 88
5 4 3 2 1
5 4 3 2 1
+1.5V_SUS
NB1B 2 OF 10
SSID = MCH M36 RESERVED#M36
2
N36 AP24
1
RESERVED#AH10
1
CFG Strap Low High AH12 RESERVED#AH12 SA_CK#_0 AR24 M_CLK_DDR#0 18
AH13 AR21 M_CLK_DDR#1 18 R1103 SM_RCOMP_VOH
RESERVED#AH13 SA_CK#_1
CFG 5 DMI X 2 DMI X 4
* K12 RESERVED#K12 SB_CK#_0 AU24 M_CLK_DDR#2 19 80D6R2F-L-GP
1
AL34 AV20 C1103
3K01R2F-3-GP
RESERVED#AL34 SB_CK#_1 M_CLK_DDR#3 19
* C1102 SCD01U16V2KX-3GP
R1104
CFG 6 ITPM enable ITPM disable AK34
2
RESERVED#AK34 SC2D2U6D3V3KX-GP
D AN35 BC28 M_CKE0 18 D
2
RESERVED#AN35 SA_CKE_0
CFG 7
TLS cipher suite with
no confidentiality
TLS cipher suite with
confidentiality * AM35
T24
RESERVED#AM35 SA_CKE_1 AY28
AY36
M_CKE1
M_CKE2
18
19
2
RESERVED#T24 SB_CKE_0
1
SB_CKE_1 BB36 M_CKE3 19
RSVD
numbered in oder *
PCIE GFX lane B31 R1105 SM_RCOMP_VOL
RESERVED#B31 80D6R2F-L-GP
CFG 9 PCIE GFX lane reversed B2 RESERVED#B2 SA_CS#_0 BA17 M_CS#0 18
2
M1 RESERVED#M1 SA_CS#_1 AY16 M_CS#1 18
1
AV16 M_CS#2 19 C1104 C1101 R1106
2
SB_CS#_0
CFG 10 PCIE loopback enable PCIE loopback disable
* AY21
SB_CS#_1
AR13 M_CS#3 19
SC2D2U6D3V3KX-GP
SCD01U16V2KX-3GP 1KR2F-3-GP
2
RESERVED#AY21
CFG 12 ALLZ mode enable ALLZ mode disable
* BD17 M_ODT0 18
1
SA_ODT_0
AY17 M_ODT1 18
SA_ODT_1
CFG 13 XOR mode enable XOR mode disable
* BG23
RESERVED#BG23
SB_ODT_0
SB_ODT_1
BF15
AY13
M_ODT2
M_ODT3
19
19
+V_DDR_REF
CFG 19
CFG 16 FSB dynamic ODT disable FSB Dynamic ODT enable
* BF23
BH18
BF18
RESERVED#BF23
RESERVED#BH18 SM_RCOMP BG22
BH21
M_RCOMPP
M_RCOMPN
RESERVED#BF18 SM_RCOMP#
DMI Lane Reserved
CFG 20
Normal operation
* Reverse DMI lanes
PCIE and SDVO are SM_RCOMP_VOH
BF28
BH28
SM_RCOMP_VOH
SM_RCOMP_VOL
DDR3_DRAMRST# 18,19
Do Not Stuff
Do Not Stuff
BF17 SM_REXT 1 2 Do Not Stuff
SM_REXT DDR3_DRAMRST# R1109
SDVO_CTRLDATA SDVO interface disable SDVO interface enable BC36
* SM_DRAMRST#
1
499R2F-2-GP
C1105
C1106
L_DDC_DATA LFP disable
* LFP card present DPLL_REF_CLK
B38
A38
CLK_MCH_DREFCLK
CLK_MCH_DREFCLK# CLK_MCH_DREFCLK 7 DY DY
2
DPLL_REF_CLK# CLK_MCH_DREFCLK# 7
DDPC_CTRLDATA SDVO/iHDMI/DP
interface disabled * SDVO/iHDMI/DP
interface enabled
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
E41
F41
MCH_SSCDREFCLK
MCH_SSCDREFCLK# MCH_SSCDREFCLK 7
MCH_SSCDREFCLK# 7
C F43 CLK_MCH_3GPLL C
PEG_CLK CLK_MCH_3GPLL# CLK_MCH_3GPLL 7
CLK
PEG_CLK# E43 CLK_MCH_3GPLL# 7
+3.3V_RUN
DMI
4 1 PM_EXTTS#0 TP1102 CFG4 P24 AE35 DMI_IRXN0_MTXN0
PM_EXTTS#1 TP1103 CFG_4 DMI_TXN_0 DMI_IRXN1_MTXN1 DMI_IRXN0_MTXN0 21
3 2 C25 AE43 DMI_IRXN1_MTXN1 21
CFG_5 DMI_TXN_1 DMI_IRXN2_MTXN2
N24 AE46
SRN10KJ-5-GP CFG_6 DMI_TXN_2 DMI_IRXN3_MTXN3 DMI_IRXN2_MTXN2 21
M24 CFG_7 DMI_TXN_3 AH42 DMI_IRXN3_MTXN3 21
CFG
E21 CFG_8
CFG9 C23 AD35 DMI_IRXP0_MTXP0
CFG10 CFG_9 DMI_TXP_0 DMI_IRXP1_MTXP1 DMI_IRXP0_MTXP0 21
C24 AE44 DMI_IRXP1_MTXP1 21
CFG_10 DMI_TXP_1 DMI_IRXP2_MTXP2 +1.05V_VCCP +3.3V_RUN
N21 AF46
CFG_11 DMI_TXP_2 DMI_IRXP3_MTXP3 DMI_IRXP2_MTXP2 21
P21 CFG_12 DMI_TXP_3 AH43 DMI_IRXP3_MTXP3 21
T21 CFG_13
TP1104 CFG14 R20 CFG_14
1
TP1105 CFG15 M20
CFG16 CFG_15 R1122 R1123
L21
CFG_16 DY Do Not Stuff
GRAPHICS VID
TP1101 CFG17 H21 56R2J-4-GP
R1118 1 CFG_17
2 Do Not Stuff CFG9
DY CFG19
P29
R28
CFG_18
2
B
R1119 1 CFG_19 B
2 Do Not Stuff CFG10 CFG20
DY T28 CFG_20 GFX_VID_0 B33
B32 TSATN#_KBC TSATN#_KBC 37
GFX_VID_1
G33
C
GFX_VID_2
GFX_VID_3 F33
R29 E33 TSATN# B Q1101
22 PM_SYNC#
8,20,47 H_DPRSTP# B7
PM_SYNC# GFX_VID_4 DY Do Not Stuff
R1124 1 CFG16 PM_DPRSTP#
2 Do Not Stuff
DY 18 PM_EXTTS#0 N33
E
PM_EXT_TS#_0
19 PM_EXTTS#1 P32 PM_EXT_TS#_1
PM
2
C1107
Do Not Stuff DY R32 DPRSLPVR R1126
2
AH37 1KR2F-3-GP
CL_CLK CL_CLK0 22 +3.3V_RUN
CL_DATA AH36 CL_DATA0 22
8,20,37,42 H_THRMTRIP# BG48 AN36 M_PW ROK 22
ME
1
NC#BG48 CL_PWROK R1129
BF48 NC#BF48 CL_RST# AJ35 CL_RST#0 22
BD48 AH34 MCH_CLVREF CLKREQ#_B 1 2
SCD1U10V2KX-5GP
22,47 DPRSLPVR NC#BD48 CL_VREF
BC48
NC#BC48
1
BH47 MCH_CLVREF ~= 0.35V 10KR2J-3-GP
NC#BH47
C1108
BG47 R1128
NC#BG47 499R2F-2-GP
BE47 N28
NC#BE47 DDPC_CTRLCLK
BH46 M28
2
NC#BH46 DDPC_CTRLDATA
BF46 G36
2
NC#BF46 SDVO_CTRLCLK
NC
NC#BG45 SDVO_CTRLDATA
BH44 NC#BH44 CLKREQ# K36 CLKREQ#_B 7
BH43 H36 MCH_ICH_SYNC# 22
NC#BH43 ICH_SYNC#
BH6 NC#BH6
BH5
NC#BH5 TSATN#
BG4 B12
NC#BG4 TSATN#
A BH3 A
NC#BH3
BF3 DJ1
NC#BF3
BH2
NC#BH2
BG2 NC#BG2 HDA_BCLK B28
BE2
BG1
NC#BE2
NC#BG1
HDA_RST#
HDA_SDI
B30
B29 Wistron Corporation
BF1 C29 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
NC#BF1 HDA_SDO Taipei Hsien 221, Taiwan, R.O.C.
HDA
BD1 A28
NC#BD1 HDA_SYNC
BC1
NC#BC1 Title
F1 NC#F1
A47
NC#A47 Cantiga-DMI/CFG(2/6)
www.vinafix.vn
CANTIGA-GM-GP-U-NF Size Document Number Rev
Custom
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 11 of 88
5 4 3 2 1
5 4 3 2 1
SSID = MCH
A
M_A_DQ18 BA40 AJ5 M_A_DM7 M_B_DQ18 BG43 AP1 M_B_DM6
B
M_A_DQ19 SA_DQ_18 SA_DM_7 M_A_DQS[7..0] M_B_DQ19 SB_DQ_18 SB_DM_6 M_B_DM7
BD43 SA_DQ_19 M_A_DQS[7..0] 18 BF43 SB_DQ_19 SB_DM_7 AK2
M_A_DQ20 AV41 AJ44 M_A_DQS0 M_B_DQ20 BE45 M_B_DQS[7..0]
SA_DQ_20 SA_DQS_0 SB_DQ_20 M_B_DQS[7..0] 19
M_A_DQ21 AY43 AT44 M_A_DQS1 M_B_DQ21 BC41 AL47 M_B_DQS0
M_A_DQ22 SA_DQ_21 SA_DQS_1 M_A_DQS2 M_B_DQ22 SB_DQ_21 SB_DQS_0 M_B_DQS1
BB41 BA43 BF40 AV48
MEMORY
M_A_DQ23 SA_DQ_22 SA_DQS_2 M_A_DQS3 M_B_DQ23 SB_DQ_22 SB_DQS_1 M_B_DQS2
MEMORY
BC40 SA_DQ_23 SA_DQS_3 BC37 BF41 SB_DQ_23 SB_DQS_2 BG41
M_A_DQ24 AY37 AW 12 M_A_DQS4 M_B_DQ24 BG38 BG37 M_B_DQS3
M_A_DQ25 SA_DQ_24 SA_DQS_4 M_A_DQS5 M_B_DQ25 SB_DQ_24 SB_DQS_3 M_B_DQS4
BD38 SA_DQ_25 SA_DQS_5 BC8 BF38 SB_DQ_25 SB_DQS_4 BH9
M_A_DQ26 AV37 AU8 M_A_DQS6 M_B_DQ26 BH35 BB2 M_B_DQS5
M_A_DQ27 SA_DQ_26 SA_DQS_6 M_A_DQS7 M_A_DQS#[7..0] M_B_DQ27 SB_DQ_26 SB_DQS_5 M_B_DQS6
AT36 SA_DQ_27 SA_DQS_7 AM7 M_A_DQS#[7..0] 18 BG35 SB_DQ_27 SB_DQS_6 AU1
M_A_DQ28 AY38 AJ43 M_A_DQS#0 M_B_DQ28 BH40 AN6 M_B_DQS7 M_B_DQS#[7..0]
SA_DQ_28 SA_DQS#_0 SB_DQ_28 SB_DQS_7 M_B_DQS#[7..0] 19
C
M_A_DQ29 BB38 AT43 M_A_DQS#1 M_B_DQ29 BG39 AL46 M_B_DQS#0 C
M_A_DQ30 SA_DQ_29 SA_DQS#_1 M_A_DQS#2 M_B_DQ30 SB_DQ_29 SB_DQS#_0 M_B_DQS#1
AV36 SA_DQ_30 SA_DQS#_2 BA44 BG34 SB_DQ_30 SB_DQS#_1 AV47
M_A_DQ31 AW 36 BD37 M_A_DQS#3 M_B_DQ31 BH34 BH41 M_B_DQS#2
M_A_DQ32 SA_DQ_31 SA_DQS#_3 M_A_DQS#4 M_B_DQ32 SB_DQ_31 SB_DQS#_2 M_B_DQS#3
BD13 SA_DQ_32 SA_DQS#_4 AY12 BH14 SB_DQ_32 SB_DQS#_3 BH37
M_A_DQ33 AU11 BD8 M_A_DQS#5 M_B_DQ33 BG12 BG9 M_B_DQS#4
M_A_DQ34 SA_DQ_33 SA_DQS#_5 M_A_DQS#6 M_B_DQ34 SB_DQ_33 SB_DQS#_4 M_B_DQS#5
BC11 SA_DQ_34 SA_DQS#_6 AU9 BH11 SB_DQ_34 SB_DQS#_5 BC2
M_A_DQ35 BA12 AM8 M_A_DQS#7 M_B_DQ35 BG8 AT2 M_B_DQS#6
SYSTEM
SYSTEM
AU13 SA_DQ_36 M_A_A[14..0] 18 BH12 SB_DQ_36 SB_DQS#_7 AN5
M_A_DQ37 AV13 BA21 M_A_A0 M_B_DQ37 BF11 M_B_A[14..0]
SA_DQ_37 SA_MA_0 SB_DQ_37 M_B_A[14..0] 19
M_A_DQ38 BD12 BC24 M_A_A1 M_B_DQ38 BF8 AV17 M_B_A0
M_A_DQ39 SA_DQ_38 SA_MA_1 M_A_A2 M_B_DQ39 SB_DQ_38 SB_MA_0 M_B_A1
BC12 SA_DQ_39 SA_MA_2 BG24 BG7 SB_DQ_39 SB_MA_1 BA25
M_A_DQ40 BB9 BH24 M_A_A3 M_B_DQ40 BC5 BC25 M_B_A2
M_A_DQ41 SA_DQ_40 SA_MA_3 M_A_A4 M_B_DQ41 SB_DQ_40 SB_MA_2 M_B_A3
BA9 SA_DQ_41 SA_MA_4 BG25 BC6 SB_DQ_41 SB_MA_3 AU25
M_A_DQ42 AU10 BA24 M_A_A5 M_B_DQ42 AY3 AW 25 M_B_A4
M_A_DQ43 SA_DQ_42 SA_MA_5 M_A_A6 M_B_DQ43 SB_DQ_42 SB_MA_4 M_B_A5
AV9 SA_DQ_43 SA_MA_6 BD24 AY1 SB_DQ_43 SB_MA_5 BB28
M_A_DQ44 BA11 BG27 M_A_A7 M_B_DQ44 BF6 AU28 M_B_A6
M_A_DQ45 SA_DQ_44 SA_MA_7 M_A_A8 M_B_DQ45 SB_DQ_44 SB_MA_6 M_B_A7
BD9 SA_DQ_45 SA_MA_8 BF25 BF5 SB_DQ_45 SB_MA_7 AW 28
M_A_DQ46 AY8 AW 24 M_A_A9 M_B_DQ46 BA1 AT33 M_B_A8
M_A_DQ47 SA_DQ_46 SA_MA_9 M_A_A10 M_B_DQ47 SB_DQ_46 SB_MA_8 M_B_A9
BA6 SA_DQ_47 SA_MA_10 BC21 BD3 SB_DQ_47 SB_MA_9 BD33
M_A_DQ48 M_A_A11 M_B_DQ48 M_B_A10
DDR
DDR
M_A_DQ49 AV7 BH26 M_A_A12 M_B_DQ49 AU3 AW 33 M_B_A11
M_A_DQ50 SA_DQ_49 SA_MA_12 M_A_A13 M_B_DQ50 SB_DQ_49 SB_MA_11 M_B_A12
AT9 SA_DQ_50 SA_MA_13 BH17 AR3 SB_DQ_50 SB_MA_12 AY33
M_A_DQ51 AN8 AY25 M_A_A14 M_B_DQ51 AN2 BH15 M_B_A13
M_A_DQ52 SA_DQ_51 SA_MA_14 M_B_DQ52 SB_DQ_51 SB_MA_13 M_B_A14
AU5 SA_DQ_52 AY2 SB_DQ_52 SB_MA_14 AU33
M_A_DQ53 AU6 M_B_DQ53 AV1
M_A_DQ54 SA_DQ_53 M_B_DQ54 SB_DQ_53
AT5 SA_DQ_54 AP3 SB_DQ_54
M_A_DQ55 AN10 M_B_DQ55 AR1
M_A_DQ56 SA_DQ_55 M_B_DQ56 SB_DQ_55
AM11 SA_DQ_56 AL1 SB_DQ_56
M_A_DQ57 AM5 M_B_DQ57 AL2
M_A_DQ58 SA_DQ_57 M_B_DQ58 SB_DQ_57
AJ9 SA_DQ_58 AJ1 SB_DQ_58
B M_A_DQ59 AJ8 M_B_DQ59 AH1 B
M_A_DQ60 SA_DQ_59 M_B_DQ60 SB_DQ_59
AN12 SA_DQ_60 AM2 SB_DQ_60
M_A_DQ61 AM13 M_B_DQ61 AM3
M_A_DQ62 SA_DQ_61 M_B_DQ62 SB_DQ_61
AJ11 SA_DQ_62 AH3 SB_DQ_62
M_A_DQ63 AJ12 M_B_DQ63 AJ3
SA_DQ_63 SB_DQ_63
CANTIGA-GM-GP-U-NF CANTIGA-GM-GP-U-NF
A A
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cantiga-DDR(3/6)
www.vinafix.vn
Size Document Number Rev
Custom
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 12 of 88
5 4 3 2 1
5 4 3 2 1
SSID = MCH
NB1I 9 OF 10 NB1J 10 OF 10 +1.05V_VCCP
BG21 AH8
VSS VSS
AU48 AM36 L12 Y8
VSS VSS VSS VSS
2
AR48
VSS VSS
AE36 AW21
VSS VSS
L8
3 OF 10
Place R1303
AL48 P36 AU21 E8 54 LBKLT_CTL NB1C R1303
BB47
VSS VSS
L36 AP21
VSS VSS
B8 37 GMCH_BL_ON 49D9R2F-GP close to
VSS VSS VSS VSS
AW47
VSS VSS
J36 AN21
VSS VSS
AY7 MCH within
AN47 F36 AH21 AU7
1
AJ47
VSS VSS
B36 AF21
VSS VSS
AN7 RN1302 L32 500 mils.
VSS VSS VSS VSS L_CTRL_CLK L_BKLT_CTRL PEG_CMP
AF47 AH35 AB21 AJ7 +3.3V_RUN 4 1 G32 T37
VSS VSS VSS VSS L_CTRL_DATA L_BKLT_EN PEG_COMPI
AD47 AA35 R21 AE7 3 2 M32 T36
VSS VSS VSS VSS +3.3V_RUN L_CTRL_CLK PEG_COMPO
AB47 Y35 M21 AA7
VSS VSS VSS VSS SRN10KJ-5-GP
Y47 U35 J21 N7 RN1301 M33
D VSS VSS VSS VSS LDDC_CLK L_CTRL_DATA D
T47 T35 G21 J7 1 4 54 LDDC_CLK K33 H44
VSS VSS VSS VSS LDDC_DATA L_DDC_CLK PEG_RX#_0
N47 BF34 BC20 BG6 2 3 54 LDDC_DATA J33 J46
VSS VSS VSS VSS L_DDC_DATA PEG_RX#_1
L47 AM34 BA20 BD6 L44
VSS VSS VSS VSS PEG_RX#_2
G47 AJ34 AW20 AV6 L40
VSS VSS VSS VSS SRN2K2J-1-GP PEG_RX#_3
BD46 AF34 AT20 AT6 54 LCDVDD_EN M29 N41
VSS VSS VSS VSS LIBG L_VDD_EN PEG_RX#_4
BA46 AE34 AJ20 AM6 2 R1302 1 C44 P48
VSS VSS VSS VSS 2K37R2F-GPTP1302 LVDS_VBG LVDS_IBG PEG_RX#_5
AY46 W34 AG20 M6 1 B43 N44
VSS VSS VSS VSS Do Not Stuff LVDS_VBG PEG_RX#_6
AV46 B34 Y20 C6 E37 T43
VSS VSS VSS VSS LVDS_VREFH PEG_RX#_7
AR46 A34 N20 BA5 E38 U43
VSS VSS VSS VSS LVDS_VREFL PEG_RX#_8
AM46 BG33 K20 AH5 54 VGA_TXACLK- C41 Y43
VSS VSS VSS VSS LVDSA_CLK# PEG_RX#_9
V46 BC33 F20 AD5 54 VGA_TXACLK+ C40 Y48
VSS VSS VSS VSS LVDSA_CLK PEG_RX#_10
R46 BA33 C20 Y5 B37 Y36
VSS VSS VSS VSS LVDSB_CLK# PEG_RX#_11
P46 AV33 A20 L5 A37 AA43
VSS VSS VSS VSS LVDSB_CLK PEG_RX#_12
LVDS
H46 AR33 BG19 J5 AD37
VSS VSS VSS VSS PEG_RX#_13
F46 AL33 A18 H5 54 VGA_TXAOUT0- H47 AC47
VSS VSS VSS VSS LVDSA_DATA#_0 PEG_RX#_14
BF44 AH33 BG17 F5 54 VGA_TXAOUT1- E46 AD39
VSS VSS VSS VSS LVDSA_DATA#_1 PEG_RX#_15
AH44 AB33 BC17 BE4 54 VGA_TXAOUT2- G40
VSS VSS VSS VSS LVDSA_DATA#_2
AD44 P33 AW17 A40 H43
VSS VSS VSS LVDSA_DATA#_3 PEG_RX_0
GRAPHICS
AA44 L33 AT17 BC3 J44
Y44
U44
VSS
VSS
VSS
VSS
VSS
VSS
H33
N32
R17
M17
VSS
VSS
VSS
VSS VSS
VSS
VSS
AV3
AL3
54 VGA_TXAOUT0+
54 VGA_TXAOUT1+
H48
D45
LVDSA_DATA_0
LVDSA_DATA_1
PEG_RX_1
PEG_RX_2
PEG_RX_3
L43
L41
T44 K32 H17 R3 F40 N40
M44
F44
VSS
VSS
VSS
VSS VSS
VSS
VSS
F32
C32
C17
VSS
VSS
VSS
VSS
VSS
P3
F3
54 VGA_TXAOUT2+
B40
LVDSA_DATA_2
LVDSA_DATA_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
P47
N43
BC43 A31 BA16 BA2 A41 T42
VSS VSS VSS VSS LVDSB_DATA#_0 PEG_RX_7
AV43 AN29 AW2 H38 U42
VSS VSS VSS LVDSB_DATA#_1 PEG_RX_8
AU43 T29 AU16 AU2 G37 Y42
VSS VSS VSS VSS LVDSB_DATA#_2 PEG_RX_9
AM43 N29 AN16 AR2 J37 W47
VSS VSS VSS VSS LVDSB_DATA#_3 PEG_RX_10
J43 K29 N16 AP2 Y37
VSS VSS VSS VSS PEG_RX_11
C43 H29 K16 AJ2 B42 AA42
VSS VSS VSS VSS LVDSB_DATA_0 PEG_RX_12
BG42 F29 G16 AH2 G38 AD36
VSS VSS VSS VSS LVDSB_DATA_1 PEG_RX_13
AY42 A29 E16 AF2 F37 AC48
VSS VSS VSS VSS LVDSB_DATA_2 PEG_RX_14
PCI-EXPRESS
AT42 BG28 BG15 AE2 K37 AD40
VSS VSS VSS VSS LVDSB_DATA_3 PEG_RX_15
AN42 BD28 AC15 AD2
VSS VSS VSS VSS
AJ42 BA28 W15 AC2 J41
VSS VSS VSS VSS PEG_TX#_0
AE42 AV28 A15 Y2 M46
VSS VSS VSS VSS R1301 1 TV_DACA PEG_TX#_1
N42 AT28 BG14 M2 2 75R2F-2-GP F25 M47
VSS VSS VSS VSS R1305 1 TVA_DAC PEG_TX#_2
C L42 AR28 AA14 K2 2 75R2F-2-GP TV_DACB H25 M40 C
VSS VSS VSS VSS R1306 1 TV_DACC TVB_DAC PEG_TX#_3
BD41 AJ28 C14 AM1 2 75R2F-2-GP K25 M42
VSS VSS VSS VSS TVC_DAC PEG_TX#_4
AU41 AG28 BG13 AA1 R48
VSS VSS VSS VSS PEG_TX#_5
AM41 AE28 BC13 P1 H24 N38
VSS VSS VSS VSS TV_RTN PEG_TX#_6
TV
AH41 AB28 BA13 H1 T40
VSS VSS VSS VSS PEG_TX#_7
AD41 Y28 U37
VSS VSS PEG_TX#_8
AA41 P28 U24 U40
VSS VSS VSS PEG_TX#_9
Y41 K28 AN13 U28 C31 Y40
VSS VSS VSS VSS TV_DCONSEL_0 PEG_TX#_10
U41 H28 AJ13 U25 E32 AA46
VSS VSS VSS VSS TV_DCONSEL_1 PEG_TX#_11
T41 F28 AE13 U29 AA37
VSS VSS VSS VSS PEG_TX#_12
M41 C28 N13 AA40
VSS VSS VSS PEG_TX#_13
G41 BF26 L13 AD43
VSS VSS VSS PEG_TX#_14
B41 AH26 G13 AF32 AC46
VSS VSS VSS VSS_NCTF PEG_TX#_15
BG40 AF26 E13 AB32
VSS VSS VSS VSS_NCTF M_BLUE
BB40 AB26 BF12 V32 55 M_BLUE E28 J42
VSS VSS VSS VSS_NCTF CRT_BLUE PEG_TX_0
AV40 AA26 AV12 AJ30 1 R1307 2 150R2F-1-GP L46
VSS VSS VSS VSS_NCTF M_GREEN PEG_TX_1
AN40 C26 AT12 AM29 55 M_GREEN G28 M48
VSS VSS VSS VSS_NCTF CRT_GREEN PEG_TX_2
H40 B26 AM12 AF29 1 R1308 2 150R2F-1-GP M39
VSS VSS VSS VSS_NCTF M_RED PEG_TX_3
E40 BH25 AA12 AB29 55 M_RED J28 M43
VSS NCTF
VGA
AM39 BB25 A12 U23 G29 N37
VSS VSS VSS VSS_NCTF CRT_IRTN PEG_TX_6
AJ39 AV25 BD11 AL20 T39
VSS VSS VSS VSS_NCTF GMCH_DDCCLK PEG_TX_7
AE39
VSS VSS
AR25 BB11
VSS VSS_NCTF
V20 CRT_IREF H32
CRT_DDC_CLK PEG_TX_8
U36
N39 AJ25 AY11 AC19 GMCH_DDCDATA J32 U39
L39
VSS VSS
AC25 AN11
VSS VSS_NCTF
AL17 routing Trace 55 GMCH_HSYNC 33R2J-2-GP 1 R1310 2 GMCH_HS J29
CRT_DDC_DATA PEG_TX_9
Y39
VSS VSS VSS VSS_NCTF 1K02R2F-1-GP1 R1311 CRT_IREF CRT_HSYNC PEG_TX_10
B39
VSS VSS
Y25 AH11
VSS VSS_NCTF
AJ17 width use 20 mil. 2 E29
CRT_TVO_IREF PEG_TX_11
Y46
BH38 N25 AA17 55 GMCH_VSYNC 33R2J-2-GP 1 R1312 2 GMCH_VS L29 AA36
VSS VSS VSS_NCTF CRT_VSYNC PEG_TX_12
BC38 L25 Y11 U17 AA39
VSS VSS VSS VSS_NCTF PEG_TX_13
BA38 J25 N11 AD42
VSS VSS VSS PEG_TX_14
AU38 G25 G11 AD46
VSS VSS VSS GMCH_GND1 PEG_TX_15
AH38 E25 C11 BH48
VSS SCB
DDC_CLK_CON 6 1 GMCH_DDCCLK
55 DDC_CLK_CON
2N7002EDW-GP
A A
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cantiga-GND/LVDS/VGA(4/6)
www.vinafix.vn
Size Document Number Rev
Custom
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 13 of 88
5 4 3 2 1
5 4 3 2 1
SSID = MCH
NB1F 6 OF 10
+1.05V_VCCP
+1.05V_VCCP
SC10U6D3V5KX-1GP
AG34 VCC
NB1G 7 OF 10
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
AC34 VCC
+1.5V_SUS AB34 VCC
AA34 VCC
1
C1427
C1402
C1405
C1403
AP33 VCC_SM VCC_AXG_NCTF W 28 Y34 VCC
AN33 VCC_SM VCC_AXG_NCTF V28 V34 VCC
D D
BH32 W 26 U34
2
VCC_SM VCC_AXG_NCTF VCC
SC1U6D3V2KX-GP
3060mA
AY32 VCC_SM VCC_AXG_NCTF V23 AE33 VCC
VCC CORE
AW 32 VCC_SM VCC_AXG_NCTF AM21 AC33 VCC
Close to (G)MCH AV32 VCC_SM VCC_AXG_NCTF AL21 AA33 VCC
AU32 VCC_SM VCC_AXG_NCTF AK21 Y33 VCC
SC10U6D3V5KX-1GP
AT32 VCC_SM VCC_AXG_NCTF W 21 W 33 VCC
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
AR32 VCC_SM VCC_AXG_NCTF V21 V33 VCC
3000mA
Coupling CAP
POWER
AP32 VCC_SM VCC_AXG_NCTF U21 U33 VCC
AN32 VCC_SM VCC_AXG_NCTF AM20 AH28 VCC
1
C1424
C1425
C1423
C1426
BH31 VCC_SM VCC_AXG_NCTF AK20 AF28 VCC
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
BG31 VCC_SM VCC_AXG_NCTF W 20 AC28 VCC
SC1U10V3KX-3GP
BF31 U20 AA28
Do Not Stuff
2
VCC_SM VCC_AXG_NCTF VCC
TC1401
C1411
C1413
C1412
BG30 VCC_SM VCC_AXG_NCTF AM19 AJ26 VCC
1
C1414
BH29 VCC_SM VCC_AXG_NCTF AL19 AG26 VCC
BG29 VCC_SM VCC_AXG_NCTF AK19 DY AE26 VCC
BF29 AJ19 AC26
2
VCC_SM VCC_AXG_NCTF VCC
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
VCC SM
BC29 VCC_SM VCC_AXG_NCTF AG19 Coupling CAP AG25 VCC
C1415
C1416
POWER
AY29 VCC_SM VCC_AXG_NCTF AB19 AJ23 VCC
AW 29 AA19 AH23 +1.05V_VCCP
2
SC4D7U6D3V5KX-3GP
1
C1429
C1428
C1430
VCC NCTF
AC23 VCC_AXG VCC_AXG_NCTF AA16 +1.05V_VCCP VCCA_MPLL 139.2mA VCC_NCTF V30
AB23 VCC_AXG VCC_AXG_NCTF Y16 VCC_NCTF U30
AA23 VCC_AXG VCC_AXG_NCTF W 16 +1.05V_VCCP VCCD_HPLL 157.2mA VCC_NCTF AL29
AJ21 VCC_AXG VCC_AXG_NCTF V16 VCC_NCTF AK29
AG21 VCC_AXG VCC_AXG_NCTF U16 +1.05V_VCCP VCCA_PEG_PLL 50mA VCC_NCTF AJ29
AE21 VCC_AXG VCC_NCTF AH29
B AC21 VCC_AXG +1.05V_VCCP VCCD_PEG_PLL 50mA VCC_NCTF AG29 B
AA21 VCC_AXG VCC_NCTF AE29
Y21 VCC_AXG +1.05V_VCCP VCC_AXF 321.35mA VCC_NCTF AC29
AH20 VCC_AXG VCC_NCTF AA29
8700mA
Y15 VCC_AXG
V15 VCC_AXG
U15 VCC_AXG
AN14 VCC_AXG
AM14 VCC_AXG
U14 VCC_AXG VCC_SM_LF AV44 SM_LF1_GMCH
BA37 SM_LF2_GMCH
VCC SM LF
SCD22U10V2KX-1GP
SCD47U6D3V2KX-GP
VCC_SM_LF
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1
1
C1401
C1419
C1420
C1421
C1422
1
Wistron Corporation
C1417
C1418
Title
CANTIGA-GM-GP-U-NF
Cantiga-Power(5/6)
www.vinafix.vn
Size Document Number Rev
Custom
DJ1 Montevina UMA A00
Date: Wednesday, February 24, 2010 Sheet 14 of 88
5 4 3 2 1
5 4 3 2 1
+1.05V_VCCP
R1502
SSID = MCH
1 2 M_VCCA_DPLLA
C1502
C1503
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1
1
Do Not Stuff C1504 +3.3V_CRT_LDO
DY Do Not Stuff R1503
SCD01U16V2KX-3GP
2
2
1 2 3D3V_CRTDAC_S0 +1.05V_VCCP
1
C1505
NB1H 8 OF 10
Do Not Stuff
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
C1506
SCD1U16V2KX-3GP
Do Not Stuff
D SCD1U10V2KX-5GP D
TC1501
C1507
C1508
C1509
C1510
EC1501
R1504 U13
2
VTT
1
VTT T13
1 2 M_VCCA_DPLLB B27 U12
VCCA_CRT_DAC VTT DY
C1511
C1512
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
A26 T12
2
VCCA_CRT_DAC VTT
1
1
+3.3V_CRT_LDO U11
Do Not Stuff R1505 VTT
C1513
SCD01U16V2KX-3GP
DY Do Not Stuff M_VCCA_DAC_BG VTT T11
1 2 A25 U10 NB:180mA
CRT
2
2
VCCA_DAC_BG VTT
B25 VSSA_DAC_BG VTT T10
1
+3.3V_RUN +1.8V_NB_S0
C1514
Do Not Stuff VTT U9 I=300mA
C1515
SC1U6D3V2KX-GP
T9
852mA
SCD1U10V2KX-5GP VTT U1501
U8
2
VTT
64.8mA
M_VCCA_DPLLA F47 T8
VCCA_DPLLA VTT
2
+1.05V_VCCP
SC1U6D3V2KX-GP
U7 1
VTT
VTT VIN
C1557
M_VCCA_DPLLB L48 T7 2
VCCA_DPLLB VTT GND
2
U6 3
1
1D8V_TXLVDS_S3 VTT EN
C1558
M_VCCA_HPLL AD1 T6 4
VCCA_HPLL 24mA
PLL
VTT NC#4
U5 5
1
M_VCCA_MPLL VTT VOUT
AE1 VCCA_MPLL 139.2mA VTT T5
L1502 V3
VTT
1
1 2 M_VCCA_HPLL U3 G9091-180T11U-GP
VTT
C1516
A LVDS
2
C1517 VTT
J47 VSSA_LVDS VTT T2
SCD1U10V2KX-5GP V1
2
+1.5V_RUN VTT
R1508 VTT U1
1
414uA 1D05V_VCC_AXF 1 2
Do Not Stuff
SC1U10V3KX-3GP
L1501 C1519
A PEG
C C
1 2 M_VCCA_MPLL SCD1U10V2KX-5GP
2
Do Not Stuff
1
C1522
BLM18PG121SN1D-GP 1D05V_RUN_PEGPLL AA48 VCCA_PEG_PLL 50mA
1
+1.05V_VCCP
C1521
R1510
Do Not Stuff
Do Not Stuff
C1520
DY
2
1 2 1D05V_SM AR20
2
VCCA_SM
SC1U10V3KX-3GP
SC22U6D3V5MX-2GP
SC4D7U6D3V3KX-GP
Do Not Stuff AP20
Do Not Stuff
VCCA_SM
TC1502
C1501
C1524
C1525
C1526
AN20
Do Not Stuff VCCA_SM
POWER
1
1
AR17
720mA
VCCA_SM
AP17
DY DY AN17
VCCA_SM +1.5V_SUS
R1511
2
2
VCCA_SM
AT16 VCCA_SM
AR16 1D8V_VCC_SM_CK 1 2
A SM
VCCA_SM
AP16 VCCA_SM
2
Do Not Stuff
+1.05V_VCCP +1.05V_VCCP
SCD1U10V2KX-5GP
R1513
R1512
1
C1532
L1503 1D05V_SM_CK 1R3F-GP
SC22U6D3V5MX-2GP
1 2
C1534
1D05V_RUN_PEGPLL
SCD1U10V2KX-5GP
1 2
Do Not Stuff
1 1
1
1
C1530
BLM18BB221SN1D-GP C1531
2
Do Not Stuff
1
SCD1U10V2KX-5GP
DY AP28 VCCA_SM_CK
321.35mA
37.5mA
C1529
VCCA_SM_CK VCC_AXF
AP25 B21
AXF
2
2
VCCA_SM_CK VCC_AXF
AN25 VCCA_SM_CK VCC_AXF A21
AN24 VCCA_SM_CK
AM28 VCCA_SM_CK_NCTF
AM26 +1.8V_NB_S0
A CK
VCCA_SM_CK_NCTF R1514
AM25 VCCA_SM_CK_NCTF
+3.3V_CRT_LDO +3.3V_TV_DAC
SC1KP50V2KX-1GP
AL25 BF21 1D8V_TXLVDS_S3 1 2
R1515 VCCA_SM_CK_NCTF VCC_SM_CK
AM24 BH20
124mA
SM CK
Do Not Stuff
Do Not Stuff
1
C1538
C1536
L1504 AM23 VCCA_SM_CK_NCTF VCC_SM_CK BF20 R1523
1
1
C1537
AL23 C1539
1D5VRUN_QDAC Do Not Stuff VCCA_SM_CK_NCTF SC22U6D3V5MX-2GP
1 2 DY DY 1 2
2
C1540
SCD01U16V2KX-3GP
2
1
K47 +3.3V_VCC_HV
PBY160808T-181Y-GP C1541
118.8mA VCC_TX_LVDS Do Not Stuff
79mA
B24 VCCA_TV_DAC
SCD1U10V2KX-5GP +1.5V_RUN A24 C35
105.3mA
TV
R1516
2
VCCA_TV_DAC VCC_HV
SCD1U10V2KX-5GP
B35
HV
VCCD_TVDAC VCC_HV
1 2 VCC_HV A35
1
1
+1.05V_VCCP
C1560
C1542
SCD1U10V2KX-5GP
SCD01U16V2KX-3GP
C1559
VCC_HDA A32
Do Not Stuff VCC_HDA 50mA HDA V48
2
2
VCC_PEG
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC4D7U6D3V3KX-GP
U48
1782mA
VCC_PEG
V47
PEG
VCC_PEG
1
C1543
C1544
C1545
C1546
U47
D TV/CRT
VCC_PEG
M25 VCCD_TVDAC 35mA VCC_PEG U46
2
+1.05V_VCCP 1D5VRUN_QDAC L28
+5V_RUN R1520 VCCD_QDAC 2mA
VCC_DMI AH48
1 2 1D05V_RUN_HPLL AF1 AF48
456mA
DMI
VCCD_HPLL 157.2mA VCC_DMI
VCC_DMI AH47
1D05V_RUN_PEGPLL AA47 AG47 +1.05V_VCCP
Do Not Stuff VCCD_PEG_PLL 50mA VCC_DMI R1501
1
C1548
1D05V_VCC_DMI
SCD1U10V2KX-5GP
1 2
C1549 C1547 M38
VTTLF
SCD1U10V2KX-5GP VCCD_LVDS
LVDS
1
L1 VTTLF2
VTTLF VTTLF3 C1550
1 EN
60.31mA VTTLF AB2
2 SCD1U10V2KX-5GP
2
A GND A
3 VIN DJ1
+3.3V_CRT_LDO 4 VOUT +1.8V_NB_S0 CANTIGA-GM-GP-U-NF
SCD47U6D3V2KX-GP
SCD47U6D3V2KX-GP
SCD47U6D3V2KX-GP
5 NC#5 R1521
Wistron Corporation
1
C1551
C1552
C1553
1 2 1D8V_SUS_DLVDS 1 1 1
R1522 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
C1554 G9091-330T12U-GP
SC10U6D3V5KX-1GP 1 2 VCC_HDA 2 2 2 Taipei Hsien 221, Taiwan, R.O.C.
2
Do Not Stuff
1
www.vinafix.vn
Size Document Number Rev
Reserved for CRT ripple Custom
DJ1 Montevina UMA A00
Date: Wednesday, February 24, 2010 Sheet 15 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 16 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 17 of 88
5 4 3 2 1
5 4 3 2 1
M_A_DM[7..0] 12
M_A_DQS#[7..0] 12
M_A_DQS[7..0] 12
DM1
M_A_A[14..0] 12
M_A_A0 98 NP1 Note:
M_A_A1 A0 NP1
97 A1 NP2 NP2
M_A_A2 96 If SA0 DIM0 = 0, SA1_DIM0 = 0
M_A_A3 A2 SA0_DIM0
95 110 M_A_RAS# 12 SO-DIMMA SPD Address is 0xA0
M_A_A4 A3 RAS#
92 A4 WE# 113 M_A_WE# 12
M_A_A5 91
A5 CAS#
115 M_A_CAS# 12 SA1_DIM0 SO-DIMMA TS Address is 0x30
M_A_A6 90
D M_A_A7 A6 D
86 A7 CS0# 114 M_CS#0 11
1
M_A_A8 89
A8 CS1#
121 M_CS#1 11 If SA0 DIM0 = 1, SA1_DIM0 = 0
M_A_A9 85 R1802 R1803
M_A_A10 107
A9
73 10KR2J-3-GP 10KR2J-3-GP SO-DIMMA SPD Address is 0xA2
A10/AP CKE0 M_CKE0 11
M_A_A11 84
A11 CKE1
74 M_CKE1 11 SO-DIMMA TS Address is 0x32
M_A_A12 83
2
M_A_A13 A12
119 A13 CK0 101 M_CLK_DDR0 11
M_A_A14 80 103 M_CLK_DDR#0 11
TP1801 M_A_A15 A14 CK0#
1 78
A15
79 102 M_CLK_DDR1 11
12 M_A_BS2 A16/BA2 CK1
104 M_CLK_DDR#1 11
CK1#
12 M_A_BS0 109 BA0
108 11 M_A_DM0
12 M_A_BS1 BA1 DM0 M_A_DM1
12 M_A_DQ[63..0] 28
M_A_DQ0 DM1 M_A_DM2
5 46
M_A_DQ1 DQ0 DM2 M_A_DM3
7 63
M_A_DQ2 DQ1 DM3 M_A_DM4
15 136
M_A_DQ3 DQ2 DM4 M_A_DM5
17 153
M_A_DQ4 DQ3 DM5 M_A_DM6
4 DQ4 DM6 170
M_A_DQ5 6 187 M_A_DM7
M_A_DQ6 DQ5 DM7
16 DQ6
M_A_DQ7 18 200
DQ7 SDA ICH_SMBDATA 7,19,22,76
M_A_DQ8 21 202
DQ8 SCL ICH_SMBCLK 7,19,22,76
M_A_DQ9 23
M_A_DQ10 DQ9 +3.3V_RUN
33 198 PM_EXTTS#0 11
M_A_DQ11 DQ10 EVENT#
35
M_A_DQ12 DQ11
22 DQ12 VDDSPD 199
M_A_DQ13 24
M_A_DQ14 DQ13 SA0_DIM0
34 DQ14 SA0 197
1
M_A_DQ15 36 201 SA1_DIM0
M_A_DQ16 DQ15 SA1 C1801 C1802
M_A_DQ17
39
DQ16 SCD1U10V2KX-5GP
DY Do Not Stuff
41 77
2
M_A_DQ18 DQ17 NC#1
51 122
M_A_DQ19 DQ18 NC#2 +1.5V_SUS
53 DQ19 NC#/TEST 125
C M_A_DQ20 C
40
M_A_DQ21 DQ20
42 75
M_A_DQ22 DQ21 VDD1
50 76
M_A_DQ23 DQ22 VDD2
52 81
M_A_DQ24 DQ23 VDD3
57 82
M_A_DQ25 DQ24 VDD4
59 87
M_A_DQ26 DQ25 VDD5
M_A_DQ27
67
DQ26 VDD6
88 SODIMM A DECOUPLING
69 93
M_A_DQ28 DQ27 VDD7 +1.5V_SUS
56 94
M_A_DQ29 DQ28 VDD8
58 99
M_A_DQ30 DQ29 VDD9
68 DQ30 VDD10 100
M_A_DQ31 70 105
M_A_DQ32 DQ31 VDD11
129 106
M_A_DQ33 DQ32 VDD12
131 111
M_A_DQ34 DQ33 VDD13 TC1801 C1803 C1804 C1805 C1806 C1807 C1808
141 112
DQ34 VDD14
1
Do Not Stuff
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
M_A_DQ35 143 117
M_A_DQ36 DQ35 VDD15
M_A_DQ37
130
132
DQ36 VDD16
118
123
DY
2
M_A_DQ38 DQ37 VDD17
140 DQ38 VDD18 124
M_A_DQ39 142
M_A_DQ40 DQ39
147 2
+V_DDR_REF M_A_DQ41 DQ40 VSS
R1806 149 DQ41 VSS 3
M_A_DQ42 157 8
M_VREF_CA_DIMM0 M_A_DQ43 DQ42 VSS
1 2 159 9
M_A_DQ44 DQ43 VSS
146 13
DQ44 VSS
1
M_A_DQ45 148 14
Do Not Stuff C1811 C1812 M_A_DQ46 DQ45 VSS
158 DQ46 VSS 19
1
SCD1U16V2KX-3GP
C1813
SCD1U16V2KX-3GP
C1814
SCD1U16V2KX-3GP
C1815
SCD1U10V2KX-5GP SC2D2U6D3V3KX-GP M_A_DQ47 160 20 Layout Note:
2
2
M_A_DQ50 DQ49 VSS
175 31 SO-DIMMA.
M_A_DQ51 DQ50 VSS
177 32
M_A_DQ52 DQ51 VSS
164 37
M_A_DQ53 DQ52 VSS
166 38
B
M_A_DQ54 DQ53 VSS B
174 43
+V_DDR_REF M_A_DQ55 DQ54 VSS
R1807 176 DQ55 VSS 44
M_A_DQ56 181 48
M_VREF_DQ_DIMM0 M_A_DQ57 DQ56 VSS
1 2 183 49
Do Not Stuff M_A_DQ58 DQ57 VSS
191 DQ58 VSS 54
1
M_A_DQ59 193 55
C1817 C1818 M_A_DQ60 DQ59 VSS
180 DQ60 VSS 60
SCD1U10V2KX-5GP SC2D2U6D3V3KX-GP M_A_DQ61 182 61
2
DDR3-SODIMM1
5 4 www.vinafix.vn 3 2
Size
Date:
Document Number
DJ1 Montevina UMA
Friday, February 26, 2010
1
Sheet 18 of
Rev
88
A00
5 4 3 2 1
DM2
1
M_B_A5 91 115 M_B_CAS# 12 M_B_DQS[7..0] 12
M_B_A6 A5 CAS# R1901
90
M_B_A7 A6 10KR2J-3-GP
86 A7 CS0# 114 M_CS#2 11 M_B_A[14..0] 12
M_B_A8 89 121 M_CS#3 11
M_B_A9 A8 CS1#
85
2
M_B_A10 A9
107 A10/AP CKE0 73 M_CKE2 11
M_B_A11 84 74 M_CKE3 11
M_B_A12 A11 CKE1 SA1_DIM1
83
D M_B_A13 A12 D
119 A13 CK0 101 M_CLK_DDR2 11
M_B_A14 80 103 M_CLK_DDR#2 11 SA0_DIM1
TP1901 M_B_A15 A14 CK0#
1 78
A15
12 M_B_BS2 79 A16/BA2 CK1 102 M_CLK_DDR3 11
1
104 M_CLK_DDR#3 11
CK1# R1902
12 M_B_BS0 109 BA0
108 11 M_B_DM0 10KR2J-3-GP
12 M_B_BS1 BA1 DM0 M_B_DM1
12 M_B_DQ[63..0] DM1 28
M_B_DQ0 5 46 M_B_DM2
2
M_B_DQ1 DQ0 DM2 M_B_DM3
7 63
M_B_DQ2 DQ1 DM3 M_B_DM4
15 136
M_B_DQ3 DQ2 DM4 M_B_DM5
17 DQ3 DM5 153
M_B_DQ4 4 170 M_B_DM6
M_B_DQ5 DQ4 DM6 M_B_DM7
6 187
M_B_DQ6 DQ5 DM7
16
M_B_DQ7 DQ6
18 200 ICH_SMBDATA 7,18,22,76
M_B_DQ8 DQ7 SDA
21 202 ICH_SMBCLK 7,18,22,76
M_B_DQ9 DQ8 SCL
M_B_DQ10
23
DQ9 +3.3V_RUN Note:
33 DQ10 EVENT# 198 PM_EXTTS#1 11
M_B_DQ11 35 SO-DIMMB SPD Address is 0xA4
M_B_DQ12 DQ11
22 DQ12 VDDSPD 199 SO-DIMMB TS Address is 0x34
M_B_DQ13 24 DQ13
1
M_B_DQ14 34 197 SA0_DIM1 SO-DIMMB is placed farther from
M_B_DQ15 DQ14 SA0 SA1_DIM1 C1901 C1902
M_B_DQ16
36 DQ15 SA1 201
SCD1U10V2KX-5GP
DY Do Not Stuff the Processor than SO-DIMMA
39
2
M_B_DQ17 DQ16
41 77
M_B_DQ18 DQ17 NC#1
51 DQ18 NC#2 122
M_B_DQ19 53 125 +1.5V_SUS
M_B_DQ20 DQ19 NC#/TEST
40 DQ20
M_B_DQ21 42 75
M_B_DQ22 DQ21 VDD1
50 76
M_B_DQ23 DQ22 VDD2
52 DQ23 VDD3 81
M_B_DQ24 57 82
M_B_DQ25 DQ24 VDD4
59 DQ25 VDD5 87
C M_B_DQ26 C
67 88
M_B_DQ27 DQ26 VDD6
69 93
M_B_DQ28 DQ27 VDD7
56 94
M_B_DQ29 DQ28 VDD8
58 99
M_B_DQ30 DQ29 VDD9
68 100
M_B_DQ31 DQ30 VDD10
70 105
M_B_DQ32 DQ31 VDD11
129 106
M_B_DQ33 DQ32 VDD12
131 111
M_B_DQ34 DQ33 VDD13
141 112
M_B_DQ35 DQ34 VDD14
143 117
M_B_DQ36 DQ35 VDD15
M_B_DQ37
130 DQ36 VDD16 118 SODIMM B DECOUPLING
132 123
M_B_DQ38 DQ37 VDD17 +1.5V_SUS
140 124
M_B_DQ39 DQ38 VDD18
142
M_B_DQ40 DQ39
147 2
M_B_DQ41 DQ40 VSS
149 3
M_B_DQ42 DQ41 VSS
157 8
M_B_DQ43 DQ42 VSS
159 9
M_B_DQ44 DQ43 VSS TC1901 C1810 C1906 C1907 C1908 C1809 C1911
146 DQ44 VSS 13
1
Do Not Stuff
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U6D3V5KX-1GP
M_B_DQ45 148 14
M_B_DQ46 DQ45 VSS
M_B_DQ47
158
160
DQ46 VSS
19
20
DY
2
M_B_DQ48 DQ47 VSS
163 25
M_B_DQ49 DQ48 VSS
165 26
M_B_DQ50 DQ49 VSS
175 31
M_B_DQ51 DQ50 VSS
177 DQ51 VSS 32
M_B_DQ52 164 37
M_B_DQ53 DQ52 VSS
166 38
M_B_DQ54 DQ53 VSS
174 DQ54 VSS 43
M_B_DQ55 176 44
M_B_DQ56 DQ55 VSS C1915 C1916 C1917 C1918
181 48
DQ56 VSS
1
+V_DDR_REF
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
Do Not Stuff
M_B_DQ57 183 49 Layout Note:
R1906 DQ57 VSS
M_B_DQ58
1 2 M_VREF_CA_DIMM1 M_B_DQ59
191
193
DQ58 VSS
54
55 Place these Caps near DY
2
B
M_B_DQ60 DQ59 VSS B
180 60 SO-DIMMB.
DQ60 VSS
1
M_B_DQ61 182 61
Do Not Stuff
C1903 C1904 M_B_DQ62 DQ61 VSS
192 65
SCD1U10V2KX-5GP SC2D2U6D3V3KX-GP M_B_DQ63 DQ62 VSS
194 66
2
DQ63 VSS
VSS 71
M_B_DQS#0 10 72
M_B_DQS#1 DQS0# VSS
27 DQS1# VSS 127
M_B_DQS#2 45 128
M_B_DQS#3 DQS2# VSS
62 133
M_B_DQS#4 DQS3# VSS
135 DQS4# VSS 134
M_B_DQS#5 152 138
+V_DDR_REF M_B_DQS#6 DQS5# VSS
R1907 169 139
M_B_DQS#7 DQS6# VSS
186 DQS7# VSS 144
1 2 M_VREF_DQ_DIMM1 145
M_B_DQS0 VSS
12 150
DQS0 VSS
1
M_B_DQS1 29 151
Do Not Stuff
C1913 C1914 M_B_DQS2 DQS1 VSS
47 DQS2 VSS 155
SCD1U10V2KX-5GP SC2D2U6D3V3KX-GP M_B_DQS3 64 156
2
62.10017.N11
C1919 C1920 C1921 C1922
VTT2. SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
Wistron Corporation
2
Title
DDR3-SODIMM2
5 4 www.vinafix.vn 3 2
Size
Date:
Document Number
DJ1 Montevina UMA
Friday, February 26, 2010
1
Sheet 19 of
Rev
88
A00
5 4 3 2 1
SSID = ICH
ICH_RTCX1
X2001
4 1
SC15P50V2JN-2-GP
SC15P50V2JN-2-GP
1
1
C2002 C2001
D D
3 2
2
X-32D768KHZ-46GP
2
20KR2F-L-GP ICH_RTCRST# A25 K2 LPC_LAD3
RTCRST# FW H3/LAD3
RTC
LPC
C2003 SRTCRST# F20
SC1U10V3KX-3GP G2001 SM_INTRUDER# SRTCRST# +3.3V_RUN
C22 K3 LPC_LFRAME# 37,58
2
Do Not Stuff INTRUDER# FW H4/LFRAME# R2001
ICH_INTVRMEN B22 J3 1 2
DY
1
LAN100_SLP INTVRMEN LDRQ0#
A22 LAN100_SLP LDRQ1#/GPIO23 J1
Do Not Stuff
+RTC_CELL E25 N7
GLAN_CLK A20GATE KA20GATE 37 +1.05V_VCCP
A20M# AJ27 H_A20M# 8
R2004 C13 R2005
LAN_RSTSYNC H_DPRSTP#
1 2 DPRSTP# AJ25 H_DPRSTP# 8,11,47 1 2
LAN / GLAN
F14 LAN_RXD0 DPSLP# AE23 H_DPSLP# 8
1
20KR2F-L-GP G13 56R2J-4-GP
C2004 LAN_RXD1 H_FERR#_R
D14 LAN_RXD2 FERR# AJ26 1 2 H_FERR# 8
SC1U10V3KX-3GP R2006 56R2J-4-GP
2
D13 LAN_TXD0 CPUPW RGD AD22 H_PWRGOOD 8,42
D12 +3.3V_RUN
C LAN_TXD1 C
E13 AF25 H_IGNNE# 8 R2008
LAN_TXD2 IGNNE#
CPU
R2007 1 2
+1.5V_RUN
Place within 500 mil of SB. 1 2GPIO56 B10 AE22
DY
DY GLAN_DOCK#/GPIO56 INIT#
AG25
H_INIT# 8
H_INTR 8 Do Not Stuff
R2009 1 INTR
2 24D9R2F-L-GP Do Not Stuff GLAN_COMP B28 GLAN_COMPI RCIN# L3 KBRCIN# 37
B27 GLAN_COMPO
AF23 H_NMI 8 +1.05V_VCCP
R2010 33R2J-2-GP ACZ_BIT_CLK_R NMI R2011
30 ICH_AZ_CODEC_BITCLK
1 2 AF6 HDA_BIT_CLK SMI# AF24 H_SMI# 8
ACZ_SYNC_R AH4 1 2
HDA_SYNC 56R2J-4-GP
STPCLK# AH27 H_STPCLK# 8
R2012 1 2 33R2J-2-GP ACZ_RST#_R AE7
30 ICH_AZ_CODEC_SYNC HDA_RST# H_THERMTRIP_R
THRMTRIP# AG26 1 2 H_THERMTRIP_1 1 R2014 2 H_THRMTRIP# 8,11,37,42
30 ICH_SDIN_CODEC AF4 R2013 54D9R2F-L1-GP Do Not Stuff
R2015 33R2J-2-GP HDA_SDIN0
30 ICH_AZ_CODEC_RST#
1 2 AG4 HDA_SDIN1 PECI AG27 Placed Within 2" from SB.
IHDA
AH3
AE5
HDA_SDIN2 A00
HDA_SDIN3
SATA4RXN AH11
R2016 1 2 33R2J-2-GP ACZ_SDATAOUT_R AG5 AJ11
30 ICH_SDOUT_CODEC HDA_SDOUT SATA4RXP
SATA4TXN AG12
AG7 HDA_DOCK_EN#/GPIO33 SATA4TXP AF12
AE8 HDA_DOCK_RST#/GPIO34
SATA5RXN AH9
SATA_LED# AG8 AJ9
66 SATA_LED# SATALED# SATA5RXP
SATA5TXN AE10
59 SATA_RXN0_C AJ16 SATA0RXN SATA5TXP AF10
HDD 59 SATA_RXP0_C AH16
SATA
C2005 1 SATA0RXP
59 SATA_TXN0 2 SCD01U50V2KX-1GP SATA_TXN0_C AF17 SATA0TXN SATA_CLKN AH18 CLK_PCIE_SATA# 7
59 SATA_TXP0 C2006 1 2 SCD01U50V2KX-1GP SATA_TXP0_C AG17 AJ18 CLK_PCIE_SATA 7
SATA0TXP SATA_CLKP
B 59 SATA_RXN1_C AH13 AJ7 SATARBIAS B
SATA1RXN SATARBIAS#
ODD 59
59
SATA_RXP1_C
SATA_TXN1 C2007 1 2 SCD01U50V2KX-1GP SATA_TXN1_C
AJ13
AG14
SATA1RXP
SATA1TXN
SATARBIAS AH7 1
R2017
2
24D9R2F-L-GP
59 SATA_TXP1 C2008 1 2 SCD01U50V2KX-1GP SATA_TXP1_C AF14 Place within 500 mils from SB.
SATA1TXP
ICH9M-GP-NF
2010/01/04
+RTC_CELL
R2018
1 2 ICH_INTVRMEN integrated VccSus1_05,VccSus1_5,VccCL1_5
A 330KR2J-L1-GP
INTVRMEN High=Enable Low=Disable A
ICH_AZ_CODEC_BITCLK DJ1
R2019 integrated VccLan1_05VccCL1_05
LAN100_SLP
1 2 LAN100_SLP High=Enable Low=Disable Wistron Corporation
1
R2020 Title
2 1 SM_INTRUDER#
ICH9-LAN/HDA/SATA/LPC(1/4)
www.vinafix.vn
1MR2J-1-GP Size Document Number Rev
Lay Out Close SB1 Custom
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 20 of 88
5 4 3 2 1
5 4 3 2 1
2 OF 6 +3.3V_RUN
SSID = ICH D11
SB1B
AD0 REQ0# F1 PCI_REQ0# RN2102
PCI_GNT0# PCI_REQ1#
5 OF 6
C8
D9
AD1 PCI GNT0# G4
B6 PCI_REQ1# PCI_DEVSEL#
8
7
1
2
SB1E AD2 REQ1#/GPIO50 PCI_GNT1# PCI_REQ3#
E12 AD3 GNT1#/GPIO51 A7 TP2102 6 3
AA26 H5 E9 F13 PCI_REQ2# PCI_TRDY# 5 4
VSS VSS AD4 REQ2#/GPIO52 PCI_GNT2#
AA27 VSS VSS J23 C9 AD5 GNT2#/GPIO53 F12 TP2103
AA3 J26 E10 E6 PCI_REQ3# SRN8K2J-4-GP
VSS VSS AD6 REQ3#/GPIO54 PCI_GNT3#
AA6 VSS VSS J27 B7 AD7 GNT3#/GPIO55 F6
AB1 AC22 C7 RN2101
VSS VSS AD8 PCI_SERR#
AA23 VSS VSS K28 C5 AD9 C/BE0# D8 8 1
AB28 K29 G11 B4 PCI_PIRQE# 7 2
D VSS VSS AD10 C/BE1# PCI_PIRQH# D
AB29 VSS VSS L13 F8 AD11 C/BE2# D6 6 3
AB4 L15 11,37,58,76 PLT_RST# PLT_RST# R2102 1 2 Do Not Stuff PCI_PLTRST# F11 A5 PCI_PIRQB# 5 4
VSS VSS AD12 C/BE3#
AB5 VSS VSS L2 E7 AD13
AC17 L26 A3 D3 PCI_IRDY# SRN8K2J-4-GP
VSS VSS AD14 IRDY#
AC26 VSS VSS L27 D2 AD15 PAR E3
AC27 L5 F10 R1 PCIRST1# RN2103
VSS VSS AD16 PCIRST# TP2104
AC3 L7 D5 C6 PCI_DEVSEL# PCI_REQ0# 8 1
VSS VSS AD17 DEVSEL# PCI_PERR# PCI_PLOCK#
AD1 VSS VSS M12 D10 AD18 PERR# E4 7 2
AD10 M13 B3 C2 PCI_PLOCK# PCI_PIRQG# 6 3
VSS VSS AD19 PLOCK# PCI_SERR# PCI_IRDY#
AD12 VSS VSS M14 F7 AD20 SERR# J4 5 4
AD13 M15 C3 A4 PCI_STOP#
VSS VSS AD21 STOP# PCI_TRDY# SRN8K2J-4-GP
AD14 VSS VSS M16 F3 AD22 TRDY# F5
AD17 M17 F4 D7 PCI_FRAME#
VSS VSS AD23 FRAME# RN2104
AD18 VSS VSS M23 C1 AD24
AD21 M28 G7 C14 PCI_PLTRST# PCI_FRAME# 8 1
VSS VSS AD25 PLTRST# PCI_PIRQC#
AD28 VSS VSS M29 H7 AD26 PCICLK D4 CLK_PCI_ICH 7 7 2
AD29 N11 D1 R2 ICH_PME# PCI_PIRQF# 6 3
VSS VSS AD27 PME# TP2105
AD4 N12 G5 PCI_REQ2# 5 4
VSS VSS AD28
AD5 VSS VSS N13 H6 AD29
AD6 N14 G1 SRN8K2J-4-GP
VSS VSS AD30
AD7 VSS VSS N15 H3 AD31
AD9 VSS VSS N16
RN2105
AE12
AE13
VSS VSS N17
N18 PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE# PCI_STOP# 8 1
VSS VSS PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF# PCI_PIRQD#
AE14 VSS VSS N26 E1 PIRQB# PIRQF#/GPIO3 K6 7 2
AE16 N27 PCI_PIRQC# J6 F2 PCI_PIRQG# PCI_PERR# 6 3
VSS VSS PCI_PIRQD# PIRQC# PIRQG#/GPIO4 PCI_PIRQH# PCI_PIRQA#
AE17 VSS VSS P12 C4 PIRQD# PIRQH#/GPIO5 G2 5 4
AE2 VSS VSS P13
ICH9M-GP-NF SRN8K2J-4-GP
AE20
AE24
VSS VSS P14
P15
Layout Note:
C VSS VSS C
AE3 VSS VSS P16 Place as close as possible
AE4 VSS VSS P17
AE6 VSS VSS P2 to the ICH Pin PCI_GNT0#
R2103
1
DY 2
Do Not Stuff
AE9 VSS VSS P23
AF13 P28 SPI_CS#1 1 2
AF16
VSS VSS
P29 R2104 DY Do Not Stuff
VSS VSS RP2101 RN2106 PCI_GNT3#
AF18 P4 1 2
AF22
VSS
VSS
VSS
VSS P7 USB_OC#7 1 10 +3.3V_ALW +3.3V_ALW 8 1 USB_OC#9 R2105 DY Do Not Stuff
AH26 R11 USB_OC#11 2 9 USB_OC#0_1 7 2 USB_OC#8
VSS VSS USB_OC#5 USB_OC#1 USB_OC#10
AF26 VSS VSS R12 3 8 6 3
AF27 R13 USB_OC#4 4 7 USB_OC#6 5 4 USB_OC#3
VSS VSS USB_OC#2_3
AF5 VSS VSS R14 +3.3V_ALW 5 6
AF7 R15 SRN8K2J-4-GP BOOT BIOS Strap
VSS VSS SRN10KJ-L3-GP
AF9 VSS VSS R16
AG13 R17 PCI_GNT#0 SPI_CS#1 BOOT BIOS Location
VSS VSS 4 OF 6
AG16 VSS VSS R18
AG18 R28 SB1D 0 1 SPI
VSS VSS
AG20 VSS VSS T12 N29 PERN1 DMI0RXN V27 DMI_IRXN0_MTXN0 11
AG23 T13 N28 V26 1 0 PCI
PCI-Express
VSS VSS 76 PCIE_RXP3 PERP3 DMI2RXP DMI_IRXP2_MTXP2 11
C2105 1 2 PCIE_C_TXN3
B AH28
AH5
VSS VSS U16
U17
LAN 76 PCIE_TXN3 C2106 1 2 PCIE_C_TXP3
K27
K26
PETN3 DMI2TXN AA29
AA28
DMI_ITXN2_MRXN2 11 B
2
B11 VSS VSS V13
B14 V15 E29 T26 CLK_PCIE_ICH# 7 R2106 1 RESERVED
VSS VSS PERN5 DMI_CLKN 24D9R2F-L-GP
B17 VSS VSS V23 E28 PERP5 DMI_CLKP T25 CLK_PCIE_ICH 7
B2 VSS VSS V28 F27 PETN5 2 USB2
B20 V29 F26 AF29
1
VSS VSS PETP5 DMI_ZCOMP DMI_IRCOMP_R
B23 VSS VSS V4 DMI_IRCOMP AF28 3 USB3
B5 VSS VSS V5 C29 PERN6/GLAN_RXN
B8 W 26 C28 AC5 USB_PN0 4 BLUETOOTH
VSS VSS PERP6/GLAN_RXP USBP0N USB_PN0 76
USB_PP0
C26
C27
VSS VSS W 27
W3
D27
D26
PETN6/GLAN_TXN USBP0P AC4
AD3
USB_PP0 76 USB0 5 RESERVED
VSS VSS PETP6/GLAN_TXP USBP1N
E11 VSS VSS Y1 USBP1P AD2
E14 Y28 D23 AC1 USB_PN2 6 WLAN
VSS VSS TP2106 SPI_CLK USBP2N USB_PN2 63
USB_PP2
E18
E2
VSS VSS Y29
Y4
TP2107
SPI_CS#1
D24
F23
SPI_CS0# USBP2P AC2
AA5 USB_PN3
USB_PP2 63 USB2 7 RESERVED
VSS VSS SPI_CS1#/GPIO58/CLGPIO6 USBP3N USB_PN3 63
USB_PP3
E21
E24
VSS VSS Y5
AG28 D25
USBP3P AA4
AB2 USB_PN4
USB_PP3 63 USB3 8 RESERVED
VSS VSS TP2110 SPI_MOSI USBP4N USB_PN4 73
SPI
www.vinafix.vn
ICH9M-GP-NF R2101 ICH9M-GP-NF Size Document Number
22D6R2F-L1-GP Custom
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 21 of 88
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
SATA
LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36
GPIO
SMB
RN2203 ME_EC_CLK1 C17 AD20 SATA3GP
SMB_CLK ME_EC_DATA1 SMLINK0 SATA5GP/GPIO37
4 1 B18 SMLINK1
3 2 SMB_DATA H1 CLK_14M_ICH 7
ICH_RI# CLK14
F19 AF3
Clocks
RI# CLK48 CLK_48M_ICH 7
SRN4K7J-8-GP 1 R2221 2 ICH_SUSCLK_2102 39 PM_PWROK R2203 1 2 10KR2J-3-GP
D SUS_STAT# ICH_SUSCLK Do Not Stuff DPRSLPVR R2205 1 Do Not Stuff D
R4 P1 2
TP2204
SYS_RESET# G19
SUS_STAT#/LPCPD# SUSCLK
1 2 ICH_SUSCLK_KBC 37 LAN_RST#1 R2204 1 DY 2 Do Not Stuff
R2202 1 LINKALERT# SYS_RESET# SB_SLP_S3# R2220 RSMRST#_KBC
2 10KR2J-3-GP SLP_S3# C16 22R2J-2-GP R2206 1 2 10KR2J-3-GP
11 PM_SYNC# M6 PMSYNC#/GPIO0 SLP_S4# E16 PM_SLP_S4# 37,41,50
G17 PM_SLP_S5# TP2202
RN2201 SMB_ALERT# SLP_S5#
TP2203 A17 SMBALERT#/GPIO11 R2209
3 2 ME_EC_DATA1 C10 GPIO26 TP2205
ME_EC_CLK1 H_STP_PCI# S4_STATE#/GPIO26 M_PWROK
4 1 7 H_STP_PCI# A14 STP_PCI# 1 2 PM_PWROK 11,37
H_STP_CPU# PM_PWROK Do Not Stuff
SYS GPIO
7 H_STP_CPU# E19 STP_CPU# PW ROK G20
SRN10KJ-5-GP
R2226
37 PM_CLKRUN# L4 CLKRUN# DPRSLPVR/GPIO16 M2 DPRSLPVR 11,47
SB_SLP_S3# 1 2 PM_SLP_S3# 37,42,49,50
R2207 1 2 10KR2J-3-GP PCIE_WAKE# PCIE_WAKE# PM_BATLOW#_R
Power MGT
76 PCIE_WAKE# E20 W AKE# BATLOW # B13
37 INT_SERIRQ INT_SERIRQ M5 Do Not Stuff
THERM_SCI# SERIRQ
AJ23 THRM# PW RBTN# R3 PM_PWRBTN# 37
RN2204
8 1 37,47 VGATE_PWRGD VGATE_PWRGD D21 D20 LAN_RST#1
SMB_ALERT# VRMPW RGD LAN_RST#
7 2
6 3 ICH_RI# R2208 1 2 Do Not Stuff ICH_TP7 A20 D22
5 4 PM_BATLOW#_R DY SST RSMRST# RSMRST#_KBC 37
1
GPIO18 K1 B19
TP2210 GPIO18 CL_CLK1
AF8 GPIO20
C AJ22 F22 R2212 C
SCLOCK/GPIO22 CL_DATA0 CL_DATA0 11
3K24R2F-GP
Controller Link
A9 C19
GPIO
GPIO27 CL_DATA1
D19
2
+3.3V_RUN GPIO28 CL_VREF0_ICH
7 CLKSATAREQ# L1 SATACLKREQ#/GPIO35 CL_VREF0 C25
AE19 SLOAD/GPIO38 CL_VREF1 A19
RN2205 AG22
H_STP_CPU# SDATAOUT0/GPIO39
SCD1U10V2KX-5GP
4 1 AF21 SDATAOUT1/GPIO48 CL_RST0# F21 CL_RST#0 11
1
H_STP_PCI#
453R2F-1-GP
3 2 AH24 D18
DY GPIO49 CL_RST1#
1
C2201
R2213
iTPM_EN A8
Do Not Stuff GPIO57/CLGPIO5
GPIO24/MEM_LED A16
30 ACZ_SPKR M7 C18
2
SPKR GPIO10/SUS_PW R_ACK
11 MCH_ICH_SYNC# AJ24 C11
2
R2214 2 10KR2J-3-GP PM_CLKRUN# ICH_TP3 MCH_SYNC# GPIO14/AC_PRESENT
1 TP2219 B21 TP3 GPIO9/W OL_EN C20
MISC
R2215 2 1 10KR2J-3-GP INT_SERIRQ AH20
R2201 2 10KR2J-3-GP GPIO18 PW M0
1 AJ20 PW M1
R2216 2 1 10KR2J-3-GP ECSCI# AJ21
R2217 1 10KR2J-3-GP ECSWI# PW M2
2
R2218 2 1 10KR2J-3-GP CLKSATAREQ# ICH9M-GP-NF
R2219 1 2 8K2R2J-3-GP THERM_SCI#
iTPM Select(Not
Strap Pin)
B B
iTPM_EN iTPM_EN
1
R2223 0 = Disable
100KR2J-1-GP
1 = Enable
2
+3.3V_RUN
RN2206
4 1
3 2
SRN4K7J-8-GP
A A
DJ1
U2202
2N7002EDW-GP ICH9-GPIO/PM/CL(3/4)
www.vinafix.vn
Size Document Number Rev
Custom
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 22 of 88
5 4 3 2 1
5 4 3 2 1
+RTC_CELL 6 OF 6
SB1F +1.05V_VCCP
SSID = ICH A23 VCCRTC VCC1_05 A15
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
VCC1_05 B15
V5REF_S0
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
A6 V5REF 2mA C15
Do Not Stuff
Do Not Stuff
VCC1_05
1
C2302
C2309
C2304
C2310
VCC1_05 D15
1
C2303
C2305
V5REF_S5 AE1 E15
V5REF_SUS 2mA VCC1_05 C2306
F15 DY DY
2
VCC1_05 SC1U6D3V2KX-GP
AA24 L11
2
VCC1_5_B VCC1_05
AA25 VCC1_5_B VCC1_05 L12
AB24 VCC1_5_B VCC1_05 L14
AB25 VCC1_5_B VCC1_05 L16
AC24 VCC1_5_B VCC1_05 L17
*Within a given well, 5VREF needs to
1634mA
AC25 VCC1_5_B VCC1_05 L18
D 1D5V_DMIPLL_ICH_S0 +1.5V_RUN D
be up before the corresponding 3.3V rail AD24 VCC1_5_B VCC1_05 M11
AD25 M18 L2301
VCC1_5_B VCC1_05 1D5V_DMIPLL_ICH_S0
SCD01U16V2KX-3GP
AE25 VCC1_5_B VCC1_05 P11 2 1
AE26 P18 COIL-1UH-31-GP
+3.3V_RUN +5V_RUN +3.3V_ALW +5V_ALW VCC1_5_B VCC1_05
AE27 VCC1_5_B VCC1_05 T11
1
C2308
AE28 VCC1_5_B VCC1_05 T18
AE29 U11 C2307
VCC1_5_B VCC1_05
2
2
D2302 F25 U18 SC10U6D3V5KX-1GP
CORE
2
D2301 R2304 R2302 VCC1_5_B VCC1_05
G25 VCC1_5_B VCC1_05 V11
CH751H-40PT-GP 10R2J-2-GP CH751H-40PT-GP 10R2J-2-GP H24 V12
VCC1_5_B VCC1_05
H25 VCC1_5_B VCC1_05 V14
J24 V16 +1.05V_VCCP
1
1
V5REF_S0 V5REF_S5 VCC1_5_B VCC1_05 R2305
J25 VCC1_5_B VCC1_05 V17
VCCDMI
SC4D7U6D3V3KX-GP
K24 VCC1_5_B VCC1_05 V18 1 2
1
1
C2311
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
K25 VCC1_5_B
SC1U6D3V2KX-GP C2312 L23 R29 Do Not Stuff
VCC1_5_B 23mA VCCDMIPLL
1
SCD1U16V2KX-3GP
C2313
C2314
C2315
646mA
L24
2
2
VCC1_5_B +1.05V_VCCP
L25 VCC1_5_B W 23
M24 50mA VCCDMI Y23 R2306
2
VCC1_5_B VCCDMI
M25 VCC1_5_B
N23 AB23 SB_V_CPU_IO 1 2
VCC1_5_B 2mA V_CPU_IO SB_V_CPU_IO
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
N24 AC23
Do Not Stuff
VCC1_5_B V_CPU_IO
C2318
N25 VCC1_5_B Do Not Stuff
1
+1.5V_RUN +3.3V_RUN
C2316
C2317
P24 VCC1_5_B VCC3_3 AG29
P25 VCC1_5_B DY
VCCA3GP
R24 AJ6
2
VCC1_5_B VCC3_3
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP SCD1U10V2KX-5GP
SCD1U10V2KX-5GP SCD1U10V2KX-5GP
R25 VCC1_5_B
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC2D2U6D3V3KX-GP
R26 AC10
Do Not Stuff
Do Not Stuff
Do Not Stuff
VCC1_5_B VCC3_3
1
TC2301
C2324
C2325
C2326
R27 VCC1_5_B
1
1
C2319
C2320
C2321
C2322
C2323
C T24 VCC1_5_B VCC3_3 AD19 C
DY DY DY T27 AF20
2
VCC1_5_B VCC3_3 +3.3V_RUN
T28 AG24
2
2
VCC1_5_B VCC3_3
T29 AC20
VCCP_CORE
VCC1_5_B VCC3_3
308mA
U24 VCC1_5_B
U25 VCC1_5_B VCC3_3 B9
SCD1U10V2KX-5GP
V24 VCC1_5_B VCC3_3 F9
V25 VCC1_5_B VCC3_3 G3 +3.3V_RUN
1
C2328
C2329
C2330
U23 VCC1_5_B VCC3_3 G6
1
+1.5V_RUN +VCCSATAPLL W 24 J2
VCC1_5_B VCC3_3 C2327
L2302 W 25 J7
2
+3.3V_RUN VCC1_5_B VCC3_3 SCD1U10V2KX-5GP
K23 K7
PCI
2
VCC1_5_B VCC3_3
R2308 1 2 Y24 VCC1_5_B
SC1U10V3KX-3GP Y25 AJ4 +3.3V_ALW
SB_VCCLAN3_3 VCC1_5_B 11mA VCCHDA
1 2 IND-10UH-215-GP
1
C2332
Do Not Stuff
Do Not Stuff
1
SC10U6D3V5KX-1GP
C2333
C2334
VCC1_5_A VCCSUS1_05
2
DY AD15 F17 VCCSUS1_05[2] 1
VCC1_5_A VCCSUS1_05 TP2301
AD16 R2316 C2355
2
VCC1_5_A
ARX
AE15 AD8 VCCSUS1_5[1] 1 2 SCD1U10V2KX-5GP
DY +1.5V_RUN
1
VCC1_5_A VCCSUS1_5
AF15 VCC1_5_A
+1.5V_RUN AG15 F18 VCCSUS1_5[2] Do Not Stuff
VCC1_5_A VCCSUS1_5
AH15 VCC1_5_A
AJ15 VCC1_5_A
VCCSUS3_3 A18
2
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
+1.5V_RUN
C2336
C2337
C2338
VCCPSUS
AD11 VCC1_5_A VCCSUS3_3 D17
AE11 E22 SCD1U10V2KX-5GP
R2311
1
VCC1_5_A VCCSUS3_3
ATX
AF11
2
VCC_GLAN_PLL VCC1_5_A
B 1 2 AG10 VCC1_5_A
B
AG11 VCC1_5_A VCCSUS3_3 AF1
1342mA
SC2D2U6D3V3KX-GP
1
C2339
SCD1U10V2KX-5GP
AC19 T6
Do Not Stuff
Do Not Stuff
VCC1_5_A VCCSUS3_3 Do Not Stuff
1
C2341
C2342
C2343
212mA
VCCSUS3_3 U6
AC21 VCC1_5_A VCCSUS3_3 U7 DY DY
V6
VCCPUSB
2
VCCSUS3_3
G10 VCC1_5_A VCCSUS3_3 V7
G9 VCC1_5_A VCCSUS3_3 W6
+1.5V_RUN W7
R2313 VCCSUS3_3 +3.3V_ALW
AC12 VCC1_5_A VCCSUS3_3 Y6
1 2 1D5V_USB_S0 AC13 Y7 R2314
VCC1_5_A VCCSUS3_3 ICH9_SUS3_3
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
AC14 T7 1 2
Do Not Stuff
VCC1_5_A VCCSUS3_3
C2344
C2345
C2346
SCD1U10V2KX-5GP
SCD1U16V2KX-3GP
SCD022U16V2KX-3GP
Do Not Stuff
1
1
C2347
C2348
C2349
DY
AA7 G23
2
VCC1_5_A VCCCL1_5
USB CORE
AB6
2
VCC1_5_A
AB7 A24
73mA
VCC1_5_A VCCCL3_3
AC6 VCC1_5_A VCCCL3_3 B24
AC7 VCC1_5_A
VCCLAN1D05 A10 VCCLAN1_05
A11
Do Not Stuff
VCCLAN1_05
1
C2350
VCCSUS1_05[3]
A A
DY SB_VCCLAN3_3
A12 VCCLAN3_3 78mA DJ1
B12
2
VCCLAN3_3 VCCSUS1_5[3]
+1.5V_RUN VCC_GLAN_PLL
Wistron Corporation
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
A27 VCCGLANPLL 23mA
Do Not Stuff
1
1
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
GLAN POWER
C2351
C2354
C2301
D28 VCCGLAN1_5 Taipei Hsien 221, Taiwan, R.O.C.
C2353
80mA
D29
DY
Do Not Stuff
VCCGLAN1_5
1
E26 +3.3V_RUN
R2315
2
2
C2352 +3.3V_RUN VCCGLAN1_5 Title
SC4D7U6D3V3KX-GP
DY E27 VCCGLAN1_5 SB_VCCCL3_3 1 2
ICH9-Power(4/4)
2
www.vinafix.vn
Size Document Number Rev
ICH9M-GP-NF Do Not Stuff Custom
DJ1 Montevina UMA A00
Date: Wednesday, February 24, 2010 Sheet 23 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
www.vinafix.vn
Size Document Number Rev
Custom
DJ1 Montevina UMA A00
Date: Wednesday, February 24, 2010 Sheet 24 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
www.vinafix.vn
Size Document Number Rev
Custom
DJ1 Montevina UMA A00
Date: Wednesday, February 24, 2010 Sheet 25 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
www.vinafix.vn
Size Document Number Rev
Custom
DJ1 Montevina UMA A00
Date: Wednesday, February 24, 2010 Sheet 26 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
www.vinafix.vn
Size Document Number Rev
Custom
DJ1 Montevina UMA A00
Date: Wednesday, February 24, 2010 Sheet 27 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
www.vinafix.vn
Size Document Number Rev
Custom
DJ1 Montevina UMA A00
Date: Wednesday, February 24, 2010 Sheet 28 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 29 of 88
5 4 3 2 1
5 4 3 2 1
SSID = AUDIO
+AVDD +5V_RUN
D +3.3V_RUN +3.3V_RUN D
Close to codec Close to codec R3021
1 2
SC1U10V3KX-3GP
ICH_AZ_CODEC_BITCLK
SCD1U10V2KX-5GP
AUD_DVDDCORE +5V_RUN
SCD1U10V2KX-5GP
Do Not Stuff
C3005
1
1
C3003
C3006
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
1
1
C3001
C3002
SC1U10V3KX-3GP
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
C3010 C3004
DY
2
Do Not Stuff SC10U6D3V5KX-1GP U3001
2
C3007
C3008
C3009
1
1
1 27
DVDD_CORE AVDD
38
AVDD AUD_AGND
9
2
DVDD
39
PVDD
3 45
DVDD_IO PVDD
13 AUD_SENSE_A
ICH_AZ_CODEC_BITCLK SENSE_A AUD_SENSE_B AUD_AGND
20 ICH_AZ_CODEC_BITCLK
6 HDA_BITCLK SENSE_B 14
ICH_AZ_CODEC_RST# 11 32 AUD_HP1_JACK_R
R3005 20 ICH_AZ_CODEC_RST# HDA_RST# HP1_PORT_B_R AUD_HP1_JACK_R 60
10KR2J-3-GP 19 AUD_INT_MIC_R_L C3011 1 2 SC1U10V3KX-3GP
PORT_C_L INT_MIC_L_R 60
PORT_C_R 20
24 AUD_VREFOUT_C R3004 1 2 2K2R2J-2-GP
2
VREFOUT_C
2 DMIC_CLK/GPIO1
AMP_MUTE# 4 40 AUD_SPK_L+ R3006 From SB
DMIC0/GPIO2 SPKR_PORT_D_L+ AUD_SPK_L- AUD_SPK_L+ 60 120KR2F-L-GP
SPKR_PORT_D_L- 41 AUD_SPK_L- 60
46 2 1 C3012 SB_SPKR_R 1 2 ACZ_SPKR 22
DMIC1/GPIO0/SPDIF_OUT_1 AUD_SPK_R- SCD1U10V2KX-5GP
C 43 C
SPKR_PORT_D_R- AUD_SPK_R+ AUD_SPK_R- 60 KBC_BEEP_R 1
48 44 2 1 C3013 2 KBC_BEEP 37
SPDIF_OUT_0 SPKR_PORT_D_R+ AUD_SPK_R+ 60 SCD1U10V2KX-5GP R3007
2
AMP_MUTE# 47 15 499KR2F-1-GP From EC
37 AMP_MUTE# EAPD PORT_E_L G3001
16
PORT_E_R
Do Not Stuff
PUMP_CAPN 17
PORT_F_L AUD_PC_BEEP
35 CAP- PORT_F_R 18
1
C3014
SC2D2U25V5KX-1GP 36
PC_BEEP 12 AUD_PC_BEEP
2
CAP+
PUMP_CAPP
MONO_OUT
25 Trace width>15 mils
7
DVSS
33 22 AUD_CAP2
AVSS CAP2
30
AVSS AUD_VREFFLT
26 21
AVSS VREFFILT
42 34 AUD_V_B
PVSS V-
49 37 AUD_VREG
GND VREG
SC4D7U6D3V5KX-3GP
SC1U6D3V2KX-GP
C3015
C3018
92HD79B1A5NLGXTAX-GP
1
71.92H79.003
AUD_AGND C3016 C3017
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
2
AUD_AGND AUD_AGND
AUD_AGND AUD_AGND
B
Close to codec B
R3013
Do Not Stuff
DY +AVDD R3015 +AVDD R3012
20KR2F-L-GP 1 2
2
1 2
AUD_HP1_JD# 60
1
Do Not Stuff
ICH_AZ_CODEC_SDOUT1
R3016 R3017
2K49R2F-GP 2K49R2F-GP R3014
A 1 2 A
2
EXT_MIC_JD# 60
1
AUD_AGND
Close to Pin13
Close to Pin14 A00 Size Document Number Rev
Custom A00
Date:
DJ1 Montevina UMA
Friday, February 26, 2010
Sheet 30 of 88
5 4 3 2 1
www.vinafix.vn
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 31 of 88
5 4 3 2 1
5 4 3 2 1
SSID = SDIO
D D
XD_D7 XD_D7 71
7 CLK_48M_CARD XD_D6/MS_BS XD_D6/MS_BS 71
XD_D5/SD_D2/MS_D5 XD_D5/SD_D2/MS_D5 71
XD_D4/SD_D3/MS_D1 XD_D4/SD_D3/MS_D1 71
XD_D3/SD_D4/MS_D4 XD_D3/SD_D4/MS_D4 71
C301
1 2 RREF
DY
Do Not Stuff
24
23
22
21
20
19
+3.3V_RUN U301
R301
1 2
CLK_IN
XD_D7
SP14
SP13
SP12
SP11
6K2R2F-GP
1 18 XD_D2/SD_CMD XD_D2/SD_CMD 71
USB_PN10_1 RREF SP10 CR_GPIO0
2 DM GPIO0 17 1 TP2 Do Not Stuff
USB_PP10_1 3 16 XD_D1/SD_D5/MS_D0 XD_D1/SD_D5/MS_D0 71
DP SP9 XD_D0/SD_CLK/MS_D2
4 3V3_IN SP8 15 XD_D0/SD_CLK/MS_D2 71
XD_WP/SD_D6/MS_D6
SCD1U10V2KX-5GP
V18 SP6
2
XD_CD#
C302
C303
DY
1
SP1
SP2
SP3
SP4
SP5
C304 25
1
SC1U6D3V2KX-GP GND
2
C
RTS5138-GR-GP C
7
8
9
10
11
12
XD_ALE/SD_D7/MS_D3 XD_ALE/SD_D7/MS_D3 71
XD_CLE/SD_D0/MS_D7 XD_CLE/SD_D0/MS_D7 71
XD_CE#/SD_D1 XD_CE#/SD_D1 71
XD_RE#/MS_INS# XD_RE#/MS_INS# 71 R302
XD_RDY/SD_WP/MS_CLK_R 2 1 XD_RDY/SD_WP/MS_CLK 71
XD_CD# XD_CD# 71 22R2J-2-GP
Close U27
Close to U301
+3.3V_RUN_CARD
B B
2
C305
SCD1U10V2KX-5GP
1
Do Not Stuff
XD_CLE/SD_D0/MS_D7
1
Do Not Stuff
Do Not Stuff
Do Not Stuff
2
A A
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Card Reader-RTS5138
www.vinafix.vn
Size Document Number Rev
Custom
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 32 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 33 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 34 of 88
5 4 3 2 1
A B C D E
4 4
3 3
(Blanking)
2 2
1 DJ1 1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
(Reserved)
Size Document Number Rev
A B
www.vinafix.vn
C D
Date:
DJ1 Montevina UMA
W ednesday, February 24, 2010 Sheet
E
35 of 88
A00
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 36 of 88
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN +KBC_PWR
CAP close to VCC-GND pin pair
+KBC_PWR
1
DY 2 KBC_PWRBTN_EC# 2
R3745
1
SSID = KBC
+KBC_PWR R3747 Do Not Stuff R3746 Do Not Stuff 100KR2J-1-GP
1
DY 2 +3.3V_RTC_LDO +3.3V_RTC_LDO
SCD1U10V2KX-5GP
1
1
+3.3V_RTC_LDO
C3702
L3701 1 2 BLM18AG601SN-3GP VBAT
DY C3703
Do Not Stuff KBC_PWRBTN#
SC2D2U6D3V3KX-GP
76 KBC_PWRBTN# 3
2
BAT54C-U-GP
2
C3704
C3710
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC2D2U6D3V3KX-GP
Do Not Stuff
1
1
D3705
C3701
R3744
C3705
C3706
C3707
C3708
C3709
DY 10KR2J-3-GP Q3704
2
2
S
115
102
+KBC_PWR
88
76
46
19
80
1
4
U3701A 1 OF 2 BAT_IN# 76 R3751 KBC_ON# 1 R3754 2 G
R3752 10KR2J-3-GP
SCD1U16V2KX-3GP
1 2
VCC
VCC
VCC
VCC
VCC
AVCC
VDD
GPIO41
D SI2301CDS-T1-GE3-GP D
1
DY 2
1
C3718
10KR2J-3-GP
+KBC_PWR AC_IN#_KBC Do Not Stuff
D
104 124 +KBC_PWR
2
VREF GPIO10/LPCPD# PLT_RST1#_1 D3704
7
LRESET#
1
+KBC_PWR BAT54C-U-GP
76 AD_IA 97 GPI90/AD0 A/D LCLK 2 PCLK_KBC 7
1
2
GPIO04 LAD3
125 INT_SERIRQ 22 G
. .
SERIRQ
8 PM_CLKRUN# 22
R3753 GPIO11/CLKRUN# KBC_ON#
122 KBRCIN# 20 D
.
.
.
Do Not Stuff KBRST#
DJ3 11 TSATN#_KBC
KB_DET_KBC
101
105
GPI94 GA20
121
29 ECSCI#_KBC
KA20GATE 20
EC_ENABLE# S 2N7002E-1-GP +3.3V_RUN
GPI95 ECSCI#/GPIO54
1SUBWOOFER_MUTE# 106 D/A 9 GMCH_BL_ON 13
2
1
+KBC_PWR 94 70 KBC_SCL1 4 1
69 LID_CLOSE# GPIO07 GPIO17/SCL1 BAT_SCL 76
PCB_VER0 119 R3705 KBC_SDA1 3 2
KBC_BIOS_ID GPIO23 2K2R2J-2-GP
2 1 6
Do Not Stuff
R3710 2K2R2J-2-GP GPIO24 SRN4K7J-8-GP
109
GPIO30
EC3701
PCB_VER1 KBC_GPIO66 1 RN3701
120 SP 81
2
GPIO31 GPIO66/G_PWM TP3706 H_THERMTRIP_R# 2 BAT_SDA
66 PWR_LED# 65
66
GPIO32/D_PWM DY1 BAT_SCL
4
3
1
2
DY
2
GPIO33/H_PWM C3711 Do Not Stuff
66 BATCHG 16 GPIO40/F_PWM
17 84 ECSMI#_KBC SRN4K7J-8-GP
GPIO42/TCK GPIO77
1
C 22 RSMRST#_KBC 20 GPIO43/TMS SPI GPIO76/SHBM 83 BLUETOOTH_EN_L 73,76 C
22,41,50 PM_SLP_S4# 21
22
GPIO44/TDI GPIO GPIO75
82
91
WIFI_RF_EN 76
2 3 KBC_THERMTRIP# LCD_CBL_DET# 1 2
GPIO45/E_PWM GPIO81 8,11,20,42 H_THRMTRIP# R3713 100KR2J-1-GP
23
46 3V_5V_POK R3718 1 PM_PWROK_R GPIO46/TRST# Q3703 KB_DET#
11,22 PM_PWROK 2 24 1 2
Do Not Stuff GPIO47 PMBS3904-1-GP R3714 100KR2J-1-GP
25
62 EC_SPI_WP#_R EC_ENABLE# GPIO50/TDO E51_TxD
26 111 E51_TxD 76
GPIO51 GPO83/SOUT_CR/BADDR1 E51_RxD D3702
54 BLON_OUT 27 113 E51_RxD 76 22 ECSWI# 1
R3719 1 CPUCORE_ON_R GPIO52/RDY# GPIO87/SIN_CR KBC_THERMTRIP# 1
47 CPUCORE_ON 2 28 112 2
Do Not Stuff GPIO53 GPO84/BADDR0 ECSWI#_KBC R3717 100KR2J-1-GP
76 PSID_DISABLE# 73 3
GPIO70
74 114 PM_LAN_ENABLE 76
GPIO71 GPIO16 RUNPWROK_R 1 R3711 2 BAS16-6-GP
75 GPIO72 GPIO34 14 RUNPWROK 49 2
63 USB_PWR_EN# 110 15 Do Not Stuff S5_ENABLE 42 S5_ENABLE 1 2
GPO82/TRIS# GPIO36 R3720 10KR2J-3-GP
SER/IR D3701
KCOL0
22 ECSCI# 1
R3721
1
DY 2
Do Not Stuff
76 PSID_EC 44 KBC_VCORF 3 ECSCI#_KBC
VCORF BAS16-6-GP
1
2 CPUCORE_ON 1 2
D
AGND
. SC1U10V3KX-3GP D3703
2
22 ECSMI# 1
. DY NPCE781BA0DX-GP
. .
116
89
78
45
18
5
103
. 3 ECSMI#_KBC BLUETOOTH_EN_L 1 2
R3742 10KR2J-3-GP
Do Not Stuff KBC_AGND 2
S
G
A00
Do Not Stuff
R3725
B B
R3722
Do Not Stuff
R3723
10KR2J-3-GP
R3724
Do Not Stuff
79 49 KCOL4
32KX2 KBSOUT4/JEN0# KCOL5
30 AMP_MUTE# 30 48
DY DY MB VERSION ID +3.3V_RUN
63
GPIO55/CLKOUT KBSOUT5/TDO
KBSOUT6/RDY#
47
43
KCOL6
KCOL7
22,47 VGATE_PWRGD GPIO14/TB1 KBSOUT7 KCOL8
VER2 VER1 VER0 22 PM_PWRBTN# 117 KBC 42
2
1
R3727
10KR2J-3-GP
R3728
Do Not Stuff
R3729
10KR2J-3-GP
36 KCOL14
A00 0 1 0 39 THERM_SDA 4 3 KBC_SDA1 KBSOUT14/GPIO62
KBSOUT15/GPIO61/XOR_OUT
35 KCOL15
KCOL16
DY A01 0 1 1 5 2
68 KB_DET#
54 LCD_CBL_DET#
13
12
GPIO12/PSDAT3 GPIO60/KBSOUT16 34
33 KCOL17 1 TP3703 Do Not Stuff
GPIO25/PSCLK3 GPIO57/KBSOUT17
11 KROW[0..7] 68
2
KBC_SCL1 GPIO27/PSDAT2
6 1 THERM_SCL 39 54 LCD_TST 10
GPIO26/PSCLK2 KROW0
68 TPDATA 71 GPIO35/PSDAT1 KBSIN0 54
KROW1
2N7002EDW-GP 68 TPCLK 72 GPIO37/PSCLK1 PS/2 KBSIN1 55
56 KROW2
KBSIN2 KROW3
KBSIN3 57
R3704 1 KROW4
DY 2
EC_SPI_DI 86
KBSIN4
58
59 KROW5
62 EC_SPI_DI F_SDI KBSIN5
Do Not Stuff EC_SPI_DO_R R3750 1 2 33R2J-2-GP EC_SPI_DO 87 60 KROW6
E51_TxD KBC CLK 62
62
EC_SPI_DO_R
EC_SPI_CS#
EC_SPI_CS# 90
F_SDO
F_CS0# FIU
KBSIN6
KBSIN7
61 KROW7
EC_SPI_CLK 1 2 EC_SPI_CLK_C 92
62 EC_SPI_CLK F_SCK
2
85 ECRST#
R3734 VCC_POR#
DY R3735
Do Not Stuff R3732 PLT_RST1#_1
DY Do Not Stuff
1 2
PLT_RST# 11,21,58,76
1
NPCE781BA0DX-GP
1
Do Not Stuff
1
PCLK_KBC_RC
C3714
DY Do Not Stuff
2
A A
+KBC_PWR
Wistron Corporation
76 AD_IA DY C3716 1 GND
4K7R2J-2-GP
1
R3737 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Do Not Stuff
DY VCC 3
1
2
ECRST#_C C3715 Taipei Hsien 221, Taiwan, R.O.C.
2
RESET#
39,42 PURE_HW_SHUTDOWN#
1
1
2
2 ECRST#_C 1
DY Do Not Stuff
2
1
Title
DY
www.vinafix.vn
C3721 R3738 Q3701
Do Not Stuff Do Not Stuff Do Not Stuff PMBS3906-GP 3 KBC Nuvoton NPCE781BA0DX
2
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 38 of 88
5 4 3 2 1
5 4 3 2 1
+5V_RUN +3.3V_RUN
SSID = Thermal
1
1
1
R3902
C3908 C3905 10KR2J-3-GP
SC10U6D3V5KX-1GP
SCD1U16V2KX-3GP
2
EMC2102_FAN_TACH_1 EMC2102_FAN_TACH_1 58
D D
EMC2102_FAN_DRIVE EMC2102_FAN_DRIVE 58
RN3901
3 2 +3.3V_RUN
4 1
SRN4K7J-8-GP
THERM_SCL 37
THERM_SDA 37
R3907
+3.3V_RUN 49D9R2F-GP
2 1 EMC2102_VDD_3D3
29
28
27
26
25
24
23
22
U3901
C3910
GND
TACH
VDD_5Va
FANa
FANb
VDD_5Vb
SMCLK
SMDATA
2
SCD1U16V2KX-3GP +3.3V_RUN
1.For CPU Sensor
1
8 H_THERMDC
C3901
1 VDD_3V NC#21 21
1
8 H_THERMDA H_THERMDA 3 19
DP1 ALERT#
EMC2102_DN2 4 EMC2102 18 CLK_32K
Layout notice : DN2 CLK_IN
C
Both DN2 and DP2 routing 10 mil
GND = Internal Oscillator Selected C
EMC2102_DP2 5 17 EMC2102_CLK_SEL 1 R3911 2
C388 must be near Q18 trace width and 10 mil spacing. DP2 CLK_SEL +3.3V = External 32.768kHz Clock Selected
EMC2102_DN3 6 16 Do Not Stuff
DN3 RESET#
C3903
1
EMC2102_DP3 7 15
DP3 NC#15
2
THERMTRIP#
POWER_OK#
Q3904 Do Not Stuff
SYS_SHDN#
1
FAN_MODE
2
SHDN_SEL
PMBS3904-1-GP C61 must be
TRIP_SET
near EMC2102 1st SMSC 74.02102.A73
3
NC#8
2.System Sensor, Put between CPU and NB. 2nd GMT 74.07922.0B3
GND = Channel 1
EMC2102-DZK-GP
OPEN = Channel 3
10
11
12
13
14
C3907 must be near Q3902
+3.3V = Disabled SRN10KJ-5-GP
THERM_POWER_OK# 3 2 +3.3V_RUN
C3909
R3914 THERMTRIP# 4 1
2
84.03904.L06 2 1 EMC2102_SHDN
DY
THERM_SYS_SHDN#
Q3903 1 C3902 SC470P50V2JN-GP +3.3V_RUN +3.3V_RTC_LDO RN3959
PMBS3904-1-GP DY Do Not Stuff Do Not Stuff
2
C63 must be
3
2
1
+3.3V_RUN +3.3V_RUN
near EMC2102
R3909 RN3960
3.HW T8 sensor 2 1 EMC2102_FAN_mode SRN10KJ-5-GP
DY THERMAL_P_HW_SHT
Do Not Stuff
Layout notice :
Q3901
3
4
1
Both DN3 and DP3 routing 10 mil
1
trace width and 10 mil spacing. G C3906 R3905
. .
B 1 R3906 2 SCD1U16V2KX-3GP 10KR2F-2-GP B
D PURE_HW_SHUTDOWN# 37,42
.
.
.
2
Do Not Stuff
2
GND = Fan is OFF S 2N7002E-1-GP
OPEN = Fan is at 60% full-scale TRIP_SET Pin Voltage
V_DEGREE
+3.3V = Fan is at 75% full-scale V_DEGREE=(((Degree-75)/21)
1
1
C3911 R3915
SCD1U16V2KX-3GP 2K37R2F-GP
2
T8 shutdown is set 88 deg-C.
42 RUN_ENABLE
2N7002E-1-GP
G
. .
22 ICH_SUSCLK_2102 D
.
.
.
DY C3912
Do Not Stuff Wistron Corporation
2
Title
www.vinafix.vn
Size Document Number Rev
Custom A00
DJ1 Montevina UMA
Date: Friday, February 26, 2010 Sheet 39 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 40 of 88
5 4 3 2 1
5 4 3 2 1
SSID = Reset.Suspend
+3.3V_ALW U4101
C C
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Power On Logic
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 41 of 88
5 4 3 2 1
5 4 3 2 1
E
R4202
H_PW RGD_R
8,20 H_PW RGOOD 1
DY 2 B
DY Q4202
Do Not Stuff
Do Not Stuff Do Not Stuff
C4202
C
DY
D D
2
2
46 3V_5V_EN 1 BAS16-6-GP
1
1 2 S5_ENABLE 37
R4201 1KR2J-1-GP
R4203
Do Not Stuff
DY
2
AO4468 MAX 11.6A
Run Power +15V_ALW RDS(ON) < 14mΩ (VGS = 10V)
C C
+3.3V_ALW _2 +5V_ALW +5V_RUN
2
U4202
R4204 8 D
D
S
S
1 MAX Current 2313.3 mA
1 2 RUN_ON_5V# R4205 7 2
100KR2J-1-GP 6 D S 3
Design Current 1619.3 mA +3.3V_RUN
100KR2J-1-GP D G S 5 D G 4
1
1
R4206 AO4468-GP C4203
6
1 2 5V_RUN_ENABLE SC10U6D3V5KX-1GP
1
Q4203
2N7002EDW -GP 10KR2J-3-GP R4211
1 100R2J-2-GP
C4201
1
SC6800P25V2KX-1GP
2
2
Q4205_D
Q4205
RUN_ENABLE
22,37,49,50 PM_SLP_S3#
RUN_ON_5V# G
. .
39 RUN_ENABLE
D
.
.
.
+3.3V_ALW +3.3V_RUN S
U4203
8 D
D
S
S
1 MAX Current 5395.1 mA 2N7002E-1-GP
7 2
6 D S 3
Design Current 3776.5 mA
B D G B
2010/01/07 5 4
1
R4210 AO4468-GP C4204
1 2 3.3V_RUN_ENABLE SC10U6D3V5KX-1GP
2
10KR2J-3-GP
1 2
1
D4203
CH751H-40PT-GP C4205
SCD01U50V2KX-1GP
2
+1.5V_SUS +1.5V_RUN
U4201
8 D S 1 MAX Current 2911.1 mA
7 D S 2
6 D S 3
Design Current 2037.8 mA
5 D G 4
1
R4215
AO4468-GP C4207
1 2 1.5V_RUN_ENABLE SC10U6D3V5KX-1GP
2
A DJ1 A
100KR2J-1-GP
1
C4208
SCD1U25V2KX-GP Wistron Corporation
2
Title
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 42 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 43 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 44 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 45 of 88
5 4 3 2 1
A B C D E
+3.3V_ALW +3D3V_PWR
PG4603 +3.3V_ALW_2
2 1
51125_VCLK
1
Do Not Stuff
1
PG4604 PR4602 PC4603 PC4604
SC1KP50V2KX-1GP
PC4602
2 1 100KR2J-1-GP SCD1U25V3KX-GP SCD1U25V3KX-GP
2
Do Not Stuff
2
PG4607
PD3903_1
PD3904_1
2 1 51125_ENTRIP
+PWR_SRC +PWR_SRC_3V
Do Not Stuff
PG4609
D
2 1 PG4634 PQ4602 51125_ENTIP1
1 2 .
3
4 Do Not Stuff 4
PG4601 Do Not Stuff . PC4605
DY PR4603 PD4602 PD4601
2 1 PG4611 . .
. Do Not Stuff 130KR2F-GP BAT54S-5-GP BAT54S-5-GP
4
2 1
Do Not Stuff 2N7002E-1-GP PQ4601
2
PG4612 Do Not Stuff 2N7002EDW-GP
1
2 1 PG4614 +15V_ALW +5V_PWR
42 3V_5V_EN
2 1 PG4615
3
Do Not Stuff Do Not Stuff
PD3903_04
PG4613 Do Not Stuff
1 2 PG4617 1 2 PD3903_2
2 1 51125_ENTIP2
Do Not Stuff
1
PG4616 Do Not Stuff PC4607
1
Do Not Stuff
1 2 PR4604 SC1U25V3KX-1-GP PC4608
160KR2F-GP SCD1U25V3KX-GP
PC4606
DY
2
1
Do Not Stuff
2
PC4609
2
SCD1U25V3KX-GP
2
+PWR_SRC_3V
+PWR_SRC
Do Not Stuff
SCD01U50V2KX-1GP
PG4602
1
PC4610 PC4611 +5V_PWR +5V_ALW 1 2
DY
1
1
SCD01U50V2KX-1GP
PG4618
SC10U25V6KX-1GP
1 2 Do Not Stuff
2
D D PC4614 PC4618 PC4615 PG4605
2
8
7
6
5
5
6
7
8
1
Do Not Stuff 1 2
D
D
D
D
D
D
D
D
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD01U50V2KX-1GP
Design Current =7.6A PU4602 PU4604 PG4621
Do Not Stuff
16
FDS8884-GP FDS8884-GP 1 2
11.95A<OCP<14.12A
2
PU4603 PG4606
PC4616 PR4606 Design Current = 7A Do Not Stuff 1 2
VIN
SCD1U25V3KX-GP PR4605 0R3J-0-U-GP PG4619
11A<OCP< 13A
G
S
S
S
0R3J-0-U-GP SCD1U25V3KX-GP 1 2 Do Not Stuff
S
S
S
G
PC4617 G S PG4608
1
2
3
4
4
3
2
1
51125_VBST2_1 251125_VBST2 51125_VBST1 51125_VBST1_1
3
S G 2 1 1 9
VBST2 VBST1
22 1 2 1 2 Do Not Stuff
PG4620
1 2 3
Do Not Stuff
1
D
PC4619
8
7
6
5
5
6
7
8
Do Not Stuff
Do Not Stuff
ST220U6D3VDM-15GP
ST220U6D3VDM-15GP
D
D
D
D
Do Not Stuff
D
D
D
D
PC4620
PTC4602
7 24 PG4625
2
VO2 VO1
1
1
PG4623 FDS6690AS-GP 2D2R5F-2-GP PG4624 1 2
2
51125_FB2 51125_FB1
5 2 DY
2
VFB2 VFB1
FDS6690AS-GP
Do Not Stuff
2
1
PG4626
2
2
1
G
S
S
S
20100118 PC4622 1 2 51125_EN 13 23 3V_5V_POK 1 2
DY
S
S
S
G
1
2
3
4
4
3
2
1
51125_ENTIP2 6 51125_ENTIP1 SC680P-GP
S G 1 Do Not Stuff
2
51125_VREF ENTRIP2 ENTRIP1
PG4627
3 15 1 2
VREF GND
1
SCD22U10V2KX-1GP
PC4623
1
PR4611
2
1
1
PR4610 SKIPSEL VCLK
51125_SKIPSEL DY
PR4601 DY Do Not Stuff PR4612
VREG3
VREG5
6K65R2F-GP 33KR2F-GP
1 2
TPS51125RGER-GP 51125_FB1_R
2
1 2
51125_FB2_R 74.51125.073
2
PC4601 PC4624 DY
3D3V_AUX_S5_5_51125 8
17
2
+3.3V_ALW_2
PG4628
2
1
1 2
1
2
+3.3V_ALW_2 1 PR4617 2 3V_5V_POK 37
2
PC4626
2 1 PR4618 2 SC22U6D3V5MX-2GP 2
51125_VREF
1
1
SC10U6D3V5KX-1GP
Do Not Stuff
SC4D7U10V5KX-4GP
1 1
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
www.vinafix.vn
A2
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 46 of 88
A B C D E
5 4 3 2 1
SSID = CPU.Regulator
+3.3V_RUN 2 DY 1 51620_TRIPSEL 51620_PWRMON 1
Do Not Stuff PR4704 TP4702
V5FILT 1 2
Do Not Stuff PR4706
51620_VR_ON 1 2 CPUCORE_ON 37
Do Not Stuff PR4705 +PWR_SRC
VREF 1 2 51620_TONSEL
Do Not Stuff PR4707
D 51620_CLKEN# D
1
TP4701
PR4708
PC4702
PC4706
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U25V3KX-GP
2 1 51620_OSRSEL 51620_DPRSLPVR 1 2
V5FILT
DY DPRSLPVR 11,22
5
6
7
8
5
6
7
8
1
Do Not Stuff PR4710 499R2F-2-GP
PC4703
PC4704
PC4705
D
D
D
D
D
D
D
D
PU4702 PU4703
VREF 1 2 1 PR4709 2 +3.3V_RUN
2
SI7686DP-T1-GP
SI7686DP-T1-GP
Do Not Stuff PR4726
1K91R2F-1-GP
VGATE_PWRGD 22,37
G
S
S
S
G
S
S
S
84.07686.037
1 2 51620_ISLEW 84.07686.037
4
3
2
1
4
3
2
1
124KR2F-GP PR4711
PR4712
V5FILT 1 2 +5V_RUN +VCC_CORE
VREF 51620_V5IN
2D2R3-1-U-GP
1
PC4701
PL4701
PC4707 SC1U10V3KX-3GP PC4709
1 2 2 1 PC4708 51620_VBST1_R 1 2 1 2
2
SC68P50V2JN-1GP L-D36UH-1-GP
SC2D2U6D3V3KX-GP SC1U25V3KX-1-GP PTC4703 PTC4701 PTC4702
5
6
7
8
5
6
7
8
1
1 PR4713 2 51620_DROOP PU4701 PU4704 PR4772 PG4632
1
D
D
D
D
D
D
D
D
SIR460DP-T1-GE3-GP
SIR460DP-T1-GE3-GP
Do Not Stuff
Do Not Stuff
ST330U2VDM-4-GP
ST330U2VDM-4-GP
5K1R2F-2-GP
DY
1
Do Not Stuff
2 DY 1 1DY 2 PG4633
DY
2
Do Not Stuff
PR4714 PC4710
2
Do Not Stuff Do Not Stuff
41
40
39
38
37
36
35
34
33
32
31
1 2
14KR2F-GP
VREF PU4705 PR4742
2
PR4716
S
S
S
S
S
S
G
G
0R3J-0-U-GP
OSRSEL
TONSEL
TRIPSEL
CLK_EN#
GND
PWRMON
VR_ON
DPRSLPVR
PGOOD
V5FILT
ISLEW
PC4711
1
4
3
2
1
4
3
2
1
1 2 DY PC4740 PR4715
1
1 30 51620_DRVH1
Do Not Stuff
2
SCD22U10V3KX-2GP DROOP DRVH1 51620_VBST1
2 29 1 2
2
VREF VBST1 51620_LL1
3 28
51620_CSP1 GND LL1 51620_DRVL1 56K2R2F-2-GP +PWR_SRC
4 27
51620_CSN1 CSP1 DRVL1
5 26 PR4717
51620_CSN2 CSN1 V5IN PR4718
6 25
PR4719 51620_CSP2 CSN2 PGND 51620_DRVL2
7 24 1 2PR4717_R
1 2
C
51620_GNDS CSP2 DRVL2 51620_LL2 C
9 VSS_SENSE 1 2 8 23
Do Not Stuff 51620_VSNS GNDSNS LL2 51620_VBST2 NTC-100K-10-GP 20K5R2F-GP
9 22
VSNS VBST2
1
51620_THERM 51620_DRVH2
DPRSTP#
10 21
THERM DRVH2
1
VR_TT#
PC4713
2K7R2J-GP
2
DY DY
VID6
VID5
VID4
VID3
VID2
VID1
VID0
PSI#
2
2
PR4743
TPS51620RHAR-GP SCD033U16V2KX-GP
11
12
13
14
15
16
17
18
19
20
51620_CSP1 1 2 51620_CSP1_R
470R2F-GP
0R3J-0-U-GP
1
9 VCC_SENSE 1 PR4724 2 PC4715 PC4714
1
SC100P50V2JN-3GP SC100P50V2JN-3GP
51620_VBST2_R
8D2R2J-GP PR4723
2
1
2
SC100P50V2JN-3GP 470R2F-GP
PeakCurrent = 47A
1
PC4716
2
2
PG4711
PR4725 1 2
1 2 SC1U25V3KX-1-GP
Do Not Stuff
20KR2F-L-GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U25V3KX-GP
SCD1U25V3KX-GP
PC4719
PC4720
PC4721
PC4722
PC4723
PC4724
5
6
7
8
5
6
7
8
1
PR4727
D
D
D
D
D
D
D
D
+1.05V_VCCP 1 2 51620AGND PU4706 PU4707
2
SI7686DP-T1-GP
SI7686DP-T1-GP
56R2J-4-GP
8 CPU_PROCHOT#
G
S
S
S
G
S
S
S
1 2 51620_DPRSTP#
8,11,20 H_DPRSTP#
PR4728 Do Not Stuff
4
3
2
1
4
3
2
1
1 2 51620_PSI# 84.07686.037 84.07686.037
8 PSI#
PR4729 Do Not Stuff
+VCC_CORE
B 9 CPU_VID[6..0] B
CPU_VID6 PR47301 2Do Not Stuff VID6
PL4702
CPU_VID5 PR47311 2Do Not Stuff VID5
CPU_VID4 PR47321 2Do Not Stuff VID4 1 2
CPU_VID3 PR47331 2Do Not Stuff VID3 L-D36UH-1-GP
PTC4708 PTC4707
5
6
7
8
5
6
7
8
1
CPU_VID2 PR47011 2Do Not Stuff VID2 PU4708 PU4709
D
D
D
D
D
D
D
D
SIR460DP-T1-GE3-GP
SIR460DP-T1-GE3-GP
Do Not Stuff
ST330U2VDM-4-GP
ST330U2VDM-4-GP
CPU_VID1 PR47341 2Do Not Stuff VID1 PR4773
1
CPU_VID0 PR47361 2Do Not Stuff VID0 PG4629 PG4630
DYDo Not Stuff
2
Do Not Stuff
2
2
S
S
S
S
S
S
G
1
4
3
2
1
4
3
2
1
DY PC4741
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Do Not Stuff
2
Inductor: 0.36UH ETQP4LR36WFC Irat =24Arms PANASONIC 1.1mohm/ 68.R3610.20A
1
O/P cap: 330U 2V EEFSX0D331XE 6mOhm 3.0Arms Panasonic/79.33719.20L PR4735
14KR2F-GP
H/S: SI7686DP/ POWERPAK-8/ 11mOhm/14mOhm @4.5Vgs/ 84.07686.037
L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/6.1mohm@4.5Vgs/ 84.00460.037 PR4737
2
NTC:TH11-3H103FT Mitsubishi 10Kohm /B-vaLue 3370K / 69.60026.001 1 2
Freq=300KHz@PER PHASE 56K2R2F-2-GP
PR4738
PR4739
1 2PR4738_R
1 2
NTC-100K-10-GP 20K5R2F-GP
PC4725
1 2
PC4727 SC100P50V2JN-3GP
SC100P50V2JN-3GP PR4741 DJ1
2
51620_CSN2 1 2 51620_CSN2_R
2
470R2F-GP
1
www.vinafix.vn
Date: Friday, February 26, 2010 Sheet 47 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 48 of 88
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p05v 1
PG4902
2 1
PG4903
2
Do Not Stuff Do Not Stuff
PG4904 PG4905
1 2 1 2
1
PG4908
2
TPS51218 for +1.05V_VCCP +1.05V_VTT_PWR_SRC
Do Not Stuff
1
PG4909
2
Do Not Stuff
1
PG4910
2
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
SC4D7U25V5KX-GP
PG4913 3 PG4914 PG4916
1 2
DY 1 2 1 2
2
+5V_RUN 2
PC4902
PC4904
PC4905
PC4903
Do Not Stuff Do Not Stuff Do Not Stuff
PG4915 PD4901 PG4917 PG4918
1
5
6
7
8
1 2 1 2 1 2
D
D
D
D
PU4902
Do Not Stuff 100KR2J-1-GP Do Not Stuff Do Not Stuff
SI7686DP-T1-GP
+3.3V_RUN 2 1
PR4901
G
S
S
S
37 RUNPWROK Design Current = 13.7A
PU4903 PC4906
A00 21.55A<OCP<25.47A
4
3
2
1
SCD1U25V3KX-GP
PR4902 84K5R2F-GP 1 11
51218_1.05VTT_TRIP PGOOD GND 51218_VBST_VTT
1 2 2 TRIP VBST 10 1 PR4903 2 51117B_LL1_VTT 2 1 PL4901
1 2 +1.05V_EN 3 9 1R3F-GP 51218_DRVH_VTT +1.05VTT_PWR
22,37,42,50 PM_SLP_S3# EN DRVH
PR4907 120KR2J-GP VTT_SENSE 4 8 51218_SW_VTT 1 2
VFB SW
SC4D7U6D3V5KX-3GP
51218_1.05VTT_CCM +5V_ALW IND-1UH-80-GP
SCD1U10V2KX-5GP
5 RF V5IN 7
Do Not Stuff
PC4908
PC4909
C 1 2 6 51218_DRVL_VTT C
DRVL
1
1
PC4901
PG4919
PR4904 PC4907
CH751H-40PT-GP
1
SCD1U16V2KX-3GP
SE220U2VDM-8GP
SE220U2VDM-8GP
2
2
2
51218_SW_GND_VTT 2
1
PTC4902
PTC4901
PU4901
2
2
51218_DRVL_VTT 4 5
2
G D
3 S D 6
2 S D 7
1 S D 8 1.05V_VTT
1
10KR2F-2-GP
SIR460DP-T1-GE3-GP
PR4906
R1
2
PC4910
SC330P50V2KX-3GP
2
VTT_SENSE
20KR2F-L-GP
1
PR4908
R2
Frequency setting Vout=0.704V*(R1+R2)/R2
2
470K -->290KHz
B B
200K -->340KHz
100K -->380KHz
39K -->430KHz I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Inductor: 1uH FDUE1040D-1R0M=P3 TOKO DCR:2.35mohm Isat =17.9Arms 68.1R01B.10A
O/P cap: 220U 2V EEFCX0D221R 15mOhm 2.7Arms PANASONIC/ 79.22719.20L
H/S: SI7686DP-T1-E3/11mohm/ 14mOhm@4.5Vgs/ 84.07686.037
L/S: SIR460DP-T1-GE3-GP/4.5mOhm/6.1mohm@4.5Vgs/ 84.00460.037
A A
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
TPS51218_+1.05V_VCCP
www.vinafix.vn
Size Document Number Rev
Custom
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 49 of 88
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p5v0p75v
+5V_ALW
PR5002
1
5D1R3J-GP
+5V_ALW
PR5015
2
1 2 51116_VDD
D 11KR2F-L-GP +5V_ALW D
1
1 2 PC5004
1
SC1U10V3KX-3GP
1
PC5002 PC5003
2
+3.3V_ALW SC1KP50V2KX-1GP SC1U10V3KX-3GP PD5001
DY Do Not Stuff
2
2
16
14
15
PR5005 PU5002
20KR2J-L2-GP RT: Non_ASM
ILIM
VDDP
VDDP
TI: ASM PR5007
+5116_PWR_SRC 22 TPS51116_VBST1 1 2 TPS51116_VBST
1
BST
41 S3_PWRGD 13 PGD 0R3J-0-U-GP
PR5006 1 2 Do Not Stuff 12 21 TPS51116_UGT
DY NC#12 DH
SCD1U16V2KX-3GP
R5017
1 2 11
22,37,41 PM_SLP_S4# EN/PSV +1.5V_SUS_P +1.5V_SUS
1
+1.5V_SUS_P 1 2
23 +PWR_SRC +5116_PWR_SRC
2
22,37,41 PM_SLP_S4#
1
1 2 Do Not Stuff TPS51116RGER-GP-U PG5001 Do Not Stuff
DY 1 18 DY PC5001 2 1 PG5005
+1.5V_SUS_P PGND2 PGND1 Do Not Stuff
C 17 1 2 C
2
PGND1
1 PR5009 2 4 TON
Do Not Stuff
8 TPS51116_VDDQSNS PG5006 Do Not Stuff
VDDQS
2
1 2
GND
REF
Do Not Stuff Do Not Stuff
1
Do Not Stuff
DY PC5007 PG5010
25
PC5012
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
SC4D7U25V5KX-GP
PC5009
PC5010
PC5011
1 PR5011 2 Do Not Stuff
1
Do Not Stuff PG5011
1
1 2
5
6
7
8
PC5008 Design Current = 9.82A
2
D
D
D
D
Design Current = 0.7A SCD033U16V3KX-GP Do Not Stuff
15.43A<OCP< 18.24A
2
PU5003 PG5012
FDS8880-NL-GP 1 2
+0D75V_DDR_P Do Not Stuff
G
S
S
S
PG5013
1 2
4
3
2
1
+0D75V_DDR_P +0.75V_DDR_VTT +1.5V_SUS_P Do Not Stuff
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
PC5013
1
PC5014
PC5015
1 2 1 2
PC5016
TPS51116_VBST 1 2 TPS51116_PHS 1 2
Do Not Stuff IND-1D5UH-55-GP Do Not Stuff
SC4D7U6D3V5KX-3GP
B B
2
PG5016 PC5017
1
SCD1U25V3KX-GP
SCD1U10V2KX-5GP
1 2
Do Not Stuff
Do Not Stuff
PTC5002
PC5018
PC5019
5
6
7
8
1
Do Not Stuff PR5012
DY DY
D
D
D
D
PU5001 FDS6676AS-GP
PG5017
Do Not Stuff PTC5001
SE220U2VDM-8GP
2
1
TPS51116_PHS_SET 20100118
1
G
S
S
S
State S3 S5 VDDR VTTREF VTT
DY PC5020
4
3
2
1
S0 Hi Hi On On On Do Not Stuff
2
S3 Lo Hi On On Off(Hi-Z)
TPS51116_VDDQSNS
1
S4/S5 Lo Lo Off Off Off
1
TPS51116_LGT
PR5013 DY PC5021
30KR2F-GP Do Not Stuff
2
2
51116_VDDQSET
1
VDDQSET VDDQ (V) VTTREF and VTT NOTE
PR5014
GND 2.5 VVDDQSNS/2 DDR 30KR2F-GP
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
2
Inductor: 1.5UH FDVE1040-1R5M=P3 DCR:4.6mohm Isat =13.7Arms TOKO/ 68.1R51A.10G Close to VFB Pin (pin5)
V5IN 1.8 VVDDQSNS/2 DDR2
A O/P cap: 330U 2.5V EEFCX0E331QR 15mOhm 2.7Arms PANASONIC/ 79.3371V.20L DJ1
A
Title
TPS51116_+1.5V_SUS
www.vinafix.vn
Size Document Number Rev
Custom
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 50 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
(Reserved)
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 51 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 52 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 53 of 88
5 4 3 2 1
5 4 3 2 1
LVDS CONNECTOR
GFX_PW R_SRC +LCDVDD
INVERTER POWER
RN5401
LCD1 LCD_CBL_DET#_C 1 8
LCD_TST_C LCD_CBL_DET# 37
D 49 2 7 LCD_TST 37 D
BLON_OUT_C 3 6
SC1U6D3V2KX-GP
SCD1U10V2KX-5GP
BLON_OUT 37
2
LCD_DET_G GFX_PW R_SRC +PW R_SRC
C5401
47 51 4 5
C5404
40
39 SRN100J-4-GP F5401
1
38 2 1
37
2
36 POLYSW -1D1A24V-GP-U
35 C5402 C5403
46 34 SC1KP50V2KX-1GP SCD1U50V3KX-GP
1
33 +3.3V_RUN
32 LCD_BRIGHTNESS R5417 1 2 100R2J-2-GP LBKLT_CTL 13
31 LCD_CBL_DET#_C
30 BLON_OUT_C
29 LCD_TST_C
28
1
45 27 LDDC_CLK 13
26 LDDC_DATA 13 R5418
25 LCD_DET_G 100KR2J-1-GP
24
23 VGA_TXAOUT0- 13
2
22 VGA_TXAOUT0+ 13
21
44 20 VGA_TXAOUT1- 13
19 VGA_TXAOUT1+ 13
18
17 VGA_TXAOUT2- 13
16 VGA_TXAOUT2+ 13
15
C 14 C
VGA_TXACLK- 13
43 13 VGA_TXACLK+ 13
12
11 USB_CAMERA# Do Not Stuff 1 R5409 2 USB_PN11 21
10 USB_CAMERA 1 R5412 2 USB_PP11 21
9 Do Not Stuff
8 +3.3V_CAMERA 2010/01/05
7
42 6
5
4
3
2
SSID = VIDEO
1
41 50
48 +3.3V_RUN
IPEX-CONN40-2R-GP-U
LCD POWER
20.F1093.040 Q5401
1 D D 6 +LCDVDD
2 D D 5
3 G S 4
330KR2J-L1-GP
1
2 R5414 1 SI3456DDV-T1-GE3-GP
SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP
+15V_ALW
R5413
1
2 FPVCC_CTL1 120R3J-2-GP
C5405
C5406
1
C5411 SCD068U50V-GP
B B
2
1
R5415 DY 2
Do Not Stuff
Q5402
4 3 LCDVDD_1
5 2
6 1
2N7002EDW -GP
13 LCDVDD_EN
D4102 +3.3V_ALW 1 2
R5416 47KR2J-2-GP
1
BAT54C-U-GP Q4103
3 OUT FPVCC_CTL3
3 ENVDD_D 2 R1
IN 1 GND
R2
2
DDTC144EUA-7F-GP
37 LCD_TST_EN
X01
LBKLT_CTL
Camera Power
A DJ1 A
LCD_TST
+3.3V_RUN +3.3V_CAMERA
R5411
Do Not Stuff
Do Not Stuff
Wistron Corporation
1
1
EC5405
EC5406
1 2
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Do Not Stuff DY DY Taipei Hsien 221, Taiwan, R.O.C.
2
2
1
www.vinafix.vn
For EMI request A3
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 54 of 88
5 4 3 2 1
5 4 3 2 1
1
2
CRT_R 1 11
RN5501 7
SRN2K2J-1-GP CRT_G 2 12 DDC_DATA_CON
8
CRT_B 3 13 JVGA_HS
4
3
+5V_CRT_RUN 9
D JVGA_VS D
Layout Note: DDC_DATA_CON
4
10
14
13 DDC_DATA_CON
DDC_CLK_CON 5 15 DDC_CLK_CON
13 DDC_CLK_CON
Do Not Stuff
Do Not Stuff
1
1
*Pi-filter & 150 Ohm pull-down 17
1
1
C5515
C5516
resistors should be as close C5514 C5513 AFTP5502 1 VIDEO-15-127-GP-U DY DY
2
SC22P50V2JN-4GP SC22P50V2JN-4GP 20.20401.015
as to CRT CONN.
2
2
* RGB signal will hit 75 Ohm
first, then pi-filter, finally
CRT CONN. AFTP5501 1 +5V_CRT_RUN
AFTP5508 1 DDC_DATA_CON
AFTP5503 1 DDC_CLK_CON
AFTP5506 1 CRT_R
AFTP5507 1 CRT_G
L5501
BLM15BB220SS1D-GP AFTP5504 1 CRT_B
13 M_RED 1 2 CRT_R
TP5505 1 JVGA_HS
L5502
BLM15BB220SS1D-GP TP5509 1 JVGA_VS
13 M_GREEN 1 2 CRT_G
L5503
2010/01/15
BLM15BB220SS1D-GP
13 M_BLUE 1 2 CRT_B
SC8P250V2CC-GP
SC8P250V2CC-GP
SC8P250V2CC-GP
C C
Do Not Stuff
Do Not Stuff
Do Not Stuff
1
C5504
C5505
C5506
150R2F-1-GP
150R2F-1-GP
150R2F-1-GP
1
R5501
R5502
R5503
C5507
C5508
C5509
DY DY DY
2
2
2
B B
+5V_CRT_RUN +5V_RUN
D5502
1 R5505 2
Do Not Stuff K A
+5V_RUN +5V_CRT_RUN
1
+5V_CRT_RUN
A00 D5501 C5511 RB551V-30-2GP
2 SCD01U16V2KX-3GP
14
2
1
1
CRT_R 3
C5512 DY 2 3
DY Do Not Stuff DY
Hsync & Vsync level shift 1
2
7
Do Not Stuff
D5503
14
13
U5501D 2
12 11 HSYNC_5 CRT_G 3
13 GMCH_HSYNC DY DY
1 +5V_CRT_RUN
Do Not Stuff
14
7
4
10
5 6 VSYNC_5 4 DY 1 JVGA_VS
A 13 GMCH_VSYNC DY D5504 DJ1
A
Do Not Stuff 2 9 8
Do Not Stuff DY
7
CRT_B 3
DY U5501C Wistron Corporation
7
www.vinafix.vn
Size Document Number Rev
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 55 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 10, 2010 Sheet 56 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
HDMI
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 57 of 88
5 4 3 2 1
5 4 3 2 1
SSID = User.Interface
ITP Connector
D H_CPURST# use pull-up Resistor close D
9 PCLK_FW H 7
10
11
12
Do Not Stuff
Do Not Stuff CPU ITP Connector
TCK(PIN 5)
TCK(PIN AC5)
FBO(PIN 11)
C C
SSID = Thermal
Fan Connector
B B
3 1
FAN1
5
39 EMC2102_FAN_TACH_1 EMC2102_FAN_TACH_1 3
AFTP5801 1 2
39 EMC2102_FAN_DRIVE EMC2102_FAN_DRIVE 1
4
*Layout* 20 mil
FOX-CON3-6-GP-U
K
D5801
C5801 RB551V-30-2GP AFTP5803 1 EMC2102_FAN_DRIVE
SC10U6D3V5KX-1GP
2
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 58 of 88
5 4 3 2 1
5 4 3 2 1
SSID = SATA
SATA HDD Connector
D D
+3.3V_RUN
1
C5903 C5901 HDD1
SC10U6D3V5KX-1GP DY Do Not Stuff
2
P1 V33 23 23
P2 V33 24 24
P3 V33
NP1 NP1
+5V_RUN P7 V5 NP2 NP2
P8 V5
1
C5902 C5906 P9
SC10U6D3V5KX-1GP SCD1U16V2KX-3GP V5
P13 S1
2
V12 GND
P14 V12 GND S4
P15 V12 GND S7
GND P4
GND P5
20 SATA_TXP0 S2 A+ GND P6
20 SATA_TXN0 S3 A- GND P10
GND P12
20 SATA_RXP0_C SCD01U50V2KX-1GP 1 2 C5904 SATA_RXP0 S6
SCD01U50V2KX-1GP B+
20 SATA_RXN0_C 1 2 C5905 SATA_RXN0 S5 B- DAS/DSS P11
C C
SKT-SATA7P-15P-23-GP
ODD Connector
B B
ODD1
8
NP1
A00
S1
Do Not Stuff
S2 SATA_TXP1_DJ2 1 R5901 2 SATA_TXP1 20
S3 SATA_TXN1_DJ2 1 R5902 2 SATA_TXN1 20 SATA_RX- and SATA_RX+ Trace
S4 Do Not Stuff
S5 SATA_RXN1 SCD01U50V2KX-1GP 1 2 C5907
Length match within 20 mil
SATA_RXN1_C 20
S6 SATA_RXP1 SCD01U50V2KX-1GP 1 2 C5908 SATA_RXP1_C 20
S7
+5V_RUN
P1
P2
P3
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1
1
C5909
C5910
P4
P5
P6
2
NP2
9
SKT-SATA7P-6P-4-GP
22.10300.811
2010/01/05
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 59 of 88
5 4 3 2 1
5 4 3 2 1
SSID = AUDIO
LINE1
Speaker OUT
Connector
D D
5
SPK1
1 LINEOUT1
30 AUD_SPK_L-
8
2 AUD_HP1_JD# 7
30 AUD_SPK_L+ 30 AUD_HP1_JD# L6001
30 AUD_SPK_R- 3 3
30 AUD_SPK_R+ 4 30 AUD_HP1_JACK_L 1 R6012 2 AUD_HP1_JACK_L2 1 BLM15BD601SS1D-GP
2 AUD_HP1_JACK_L1 1
60D4R2F-GP 4
Do Not Stuff
Do Not Stuff
Do Not Stuff
30 AUD_HP1_JACK_R 1 R6011 2 AUD_HP1_JACK_R2 1 BLM15BD601SS1D-GP
2 AUD_HP1_JACK_R1
Do Not Stuff
FOX-CON4-19-GP 60D4R2F-GP L6002 2
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
6
1
1
20.F0711.004
EC6001
EC6002
EC6003
EC6004
EC6005
EC6006
5
DY DY DY DY 6
1
1
2
2
EC6010 EC6011 PHONE-JK383-GP
SC1KP50V2KX-1GP SC1KP50V2KX-1GP AFTP6009 22.10133.K31
2
1
AFTP6013
1 AUD_SPK_L- 1 AUD_HP1_JD#
AFTP6002 1 AUD_SPK_L+ AFTP6010 600ohm 100MHz 2010/01/08
AFTP6003 1 AUD_SPK_R- 1 AUD_HP1_JACK_L1
AFTP6004 1 AUD_SPK_R+ AFTP6011 200mA 0.5ohm DC
AFTP6005 1 AUD_HP1_JACK_R1
AFTP6012
C C
Internal MIC IN
Microphone
30 AUD_VREFOUT_B
SC1U10V3KX-3GP
2
1
1
RN6001
C6001
SRN4K7J-8-GP
2
3
4
1 MIC1 A00
B 30 INT_MIC_L_R Do Not Stuff B
Do Not Stuff MICIN1
2
1
8
EC6007 R6009 7
SC1KP50V2KX-1GP AUD_EXT_MIC_L C6002 2 1 SC1U10V3KX-3GP MIC_IN_L_2 1 2 MIC_IN_L_C 3
2
SC100P50V2JN-3GP
SC100P50V2JN-3GP
EC6008
EC6009
1
1
1 AFTP6001
2
1 MIC_IN_L_C
AFTP6006
G6001 1 MIC_IN_R_C
AFTP6007
2 1 1 EXT_MIC_JD#
AFTP6008
Do Not Stuff
A DJ1 A
AUD_AGND
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Audio Jack/Mic/Speaker
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 60 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 61 of 88
5 4 3 2 1
5 4 3 2 1
SSID = Flash.ROM
+KBC_PW R
+KBC_PW R
SCD1U16V2KX-3GP
C6203
1
1
DY
4
3
C6202
R6202 RN6201 Do Not Stuff
2
SRN100KJ-6-GP
Do Not Stuff
DY
1
2
C EC_SPI_HOLD# C
U6201 +KBC_PW R
37 EC_SPI_CS# EC_SPI_CS# 1 8
R6201 1 CS# VCC
37 EC_SPI_DI 2 33R2J-2-GP EC_SPI_DI_R 2 SO/SIO1 HOLD# 7
37 EC_SPI_W P#_R R6203 1 2 EC_SPI_W P# 3 6 EC_SPI_CLK 37
WP#/ACC SCLK EC_SPI_DO_R
4 GND SI/SIO0 5 EC_SPI_DO_R 37
1
1
Do Not Stuff
1
1
Do Not Stuff
Do Not Stuff
EC6201 R6209 R6210 MX25L1605DM2I-12G-GP
EC6202
EC6203
Do Not Stuff DY 100KR2J-1-GP 10KR2J-3-GP
DY DY
2
2
72.25165.A01
2nd 72.25016.D01
A00
B B
SSID = RBATT
RTC Connector
+3.3V_RTC_LDO
D6203
+RTC_CELL
2
+RTC_VCC
RTC1
3
R6208
A 1 RTC_PW R 1 2 1 DJ1 A
PWR
1
1 2 GND
C6207 1KR2J-1-GP TP6201 NP1
SC1U10V3KX-3GP SDMG0340LC7F-GP-U NP1
NP2
Wistron Corporation
2
NP2
Width=20mils
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2010/01/15 BAT-CON2-1-GP-U
Taipei Hsien 221, Taiwan, R.O.C.
Title
62.70001.011
TP6202 1 +RTC_VCC 2010/01/05 Size Document Number
Flash/RTC Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 62 of 88
5 4 3 2 1
5 4 3 2 1
SSID = USB
1
4 5 C6304
37 USB_PW R_EN# EN# OC# USB_OC#0_1 21
1
SC1U10V3KX-3GP
C6306
2
SCD1U10V2KX-5GP UP7534BRA8-15-GP
2
74.07534.079
2nd 74.09715.079
20100111
USB Socket
+5V_USB2 USB1
5 7
1
C
Right USB Power USB_P2- C
2
+5V_ALW +5V_USB2 USB_P2+ 3
U6301 4
at least 80 mil 6 8
at least 80 mil 1 8
ST100U6D3VBML1GP
GND VOUT#8 SKT-USB8-29-GP
2 7
SC1U10V3KX-3GP
SCD1U10V2KX-5GP
VIN VOUT#7
Do Not Stuff
TC6301
22.10254.451
R6301
C6302
3 VIN VOUT#6 6
1
C6301
37 USB_PW R_EN# 4 EN# OC# 5 USB_OC#2_3 21
1
C6303 DY
2
SCD1U10V2KX-5GP UP7534BRA8-15-GP
2
2
74.07534.079
2nd 74.09715.079 +5V_USB2 USB3
20100111 5
1
7
USB_P3- 2
USB_P3+ 3
4
6 8
Do Not Stuff
USB_PN2 1 R6302 2 USB_P2- SKT-USB8-29-GP
21 USB_PN2
+5V_USB2 22.10254.451
USB_PP2 1 R6303 2 USB_P2+
21 USB_PP2
Do Not Stuff D6301
1 4
B 2010/01/05 B
AFTP6304 1 +5V_USB2
Do Not Stuff AFTP6302 USB_P2-
21 USB_PN3 USB_PN3 1 R6304 2 USB_P3- DY AFTP6301
1
1 USB_P2+
AFTP6306 1 USB_P3-
21 USB_PP3 USB_PP3 1 R6305 2 USB_P3+ USB_P2+ 2 3 USB_P2- AFTP6305 1 USB_P3+
Do Not Stuff
Do Not Stuff
+5V_USB2
D6302
1 4
DY
USB_P3+ 2 3 USB_P3-
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
USB
Size Document Number Rev
5 4
www.vinafix.vn 3 2
Date:
DJ1 Montevina UMA
Friday, February 26, 2010 Sheet
1
63 of 88
A00
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 64 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 65 of 88
5 4 3 2 1
5 4 3 2 1
PDTA144VT-GP +5V_ALW
D
Power button LED PW R_LED# B
R2
E
R6605 LED-W -27-GP
D
37 PW R_LED# R1
PW R_LED_R PW R_LED_B
C 2 1 1 A K2
3
83.01221.R70
C C
Battery LED
White +5V_ALW
LED-OW -3-GP
Q6601 R6601
C LED_BATCHG# 1 2 BATCHG_LED_B 3
B R1
37 BATCHG 330R2J-3-GP
E 1
1
R2
PDTC124EU-1-GP EC6601
DY Do Not Stuff
2
83.00326.G70
2
LED1
R6602 Amber
Q6602
C LED_BAT# 1 2 BAT_LED_B
B R1 B
37 BATLOW _LED B
E 330R2J-3-GP
1
R2
PDTC124EU-1-GP EC6602
DY Do Not Stuff
2
HDD LED
PDTA144VT-GP +5V_RUN
R2
E
SATA_LED# R6604 LED-W -27-GP
20 SATA_LED# B R1
A C SATA_LED_R 2 1 SATA_LED_B 1 2 DJ1 A
A K
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
83.01221.R70
Title
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 66 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 67 of 88
5 4 3 2 1
5 4 3 2 1
D
Internal KeyBoard Connector TouchPad Connector D
KB1 +5V_RUN
1
31 AFTP6831
1
SCD1U16V2KX-3GP
KB_DET# 37
1
KROW 7
C6802
2 1
3 KROW 6 1 AFTP6827
4 KROW 4 1 AFTP6825
2
5 KROW 2 1 AFTP6824 +5V_RUN
6 KROW 5 1 AFTP6822
7 KROW 1 1 AFTP6823
8 KROW 3 1 AFTP6820
9 KROW 0 1 AFTP6821
1
2
10 KCOL5 1 AFTP6819
11 KCOL4 1 AFTP6817 RN6801
12 KCOL7 1 AFTP6818 KROW [0..7] 37 SRN10KJ-5-GP TP1
13 KCOL6 1 AFTP6816 5
14 KCOL8 1 AFTP6814
15 KCOL3 1 AFTP6812 KCOL[0..16] 37 1
4
3
16 KCOL1 1 AFTP6813
17 KCOL2 1 AFTP6815 37 TPCLK 2
18 KCOL0 1 AFTP6810 37 TPDATA 3
19 KCOL12 1 AFTP6808 1 4
C 20 KCOL16 1 AFTP6809 AFTP6811 C
1
1
21 KCOL15 1 AFTP6806 6
22 KCOL13 1 AFTP6807 C6803 C6804
23 KCOL14 1 AFTP6804 SC33P50V2JN-3GP SC33P50V2JN-3GP ACES-CON4-10-GP-U
2
2
24 KCOL9 1 AFTP6805 20.K0320.004
25 KCOL11 1 AFTP6803
26 KCOL10 1 AFTP6801
27 AFTP6802
28
29
30 1
32 AFTP6829
1 +5V_RUN
ACES-CON30-3-GP AFTP6826 1 TPCLK
AFTP6828 1 TPDATA
AFTP6830
20.K0421.030
2nd 20.K0461.030
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 68 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
+3.3V_ALW
2 VDD
SCD1U10V2KX-5GP
VSS 1
1
LID_CLOSE#_1
C6902
3 OUT
2
S-5711ACDL-M3T1S-GP
20100114
+3.3V_ALW
A00
1
DY R6902
100KR2J-1-GP
2
C6901
SCD047U16V2KX-1-GP
2
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Hall Sensor
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 69 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 70 of 88
5 4 3 2 1
5 4 3 2 1
D D
+3.3V_RUN_CARD
SCD1U16V2KX-3GP
SC2D2U6D3V3KX-GP
Do Not Stuff
Do Not Stuff
Do Not Stuff
C7105
1
1
C7101
C7102
C7103
C7104
DY 2
DY DY
2
C C
+3.3V_RUN_CARD CARD1
2010/01/15
23 SD_VCC SD_DAT0 25 XD_CLE/SD_D0/MS_D7 32
14 MS_VCC SD_DAT1 29 XD_CE#/SD_D1 32
1 33 XD_VCC SD_DAT2 10 XD_D5/SD_D2/MS_D5 32
TP7112 11 XD_D4/SD_D3/MS_D1 32
XD_CD# SD_DAT3
TP402
XD_RDY/SD_W P/MS_CLK 32 XD_D0/SD_CLK/MS_D2 8 12 XD_D2/SD_CMD 32
TP403 XD_D0 SD_CMD
XD_RE#/MS_INS# 32 XD_D1/SD_D5/MS_D0 9 24 XD_D0/SD_CLK/MS_D2 32
TP404 XD_D1 SD_CLK
XD_CE#/SD_D1 32 XD_D2/SD_CMD 26 36 XD_W E#/SD_CD# 32
TP405 XD_D2 SD_CD_SW
XD_CLE/SD_D0/MS_D7 32 XD_D3/SD_D4/MS_D4 27 35 XD_RDY/SD_W P/MS_CLK 32
TP406 XD_D3 SD_WP_SW
XD_ALE/SD_D7/MS_D3 32 XD_D4/SD_D3/MS_D1 28
TP407 XD_D4
XD_W E#/SD_CD# 32 XD_D5/SD_D2/MS_D5 30
TP408 XD_D5
XD_W P/SD_D6/MS_D6 32 XD_D6/MS_BS 31 19 XD_D1/SD_D5/MS_D0 32
TP409 XD_D6 MS_DATA0
XD_D0/SD_CLK/MS_D2 32 XD_D7 32 20 XD_D4/SD_D3/MS_D1 32
TP410 XD_D7 MS_DATA1
XD_D1/SD_D5/MS_D0 18 XD_D0/SD_CLK/MS_D2 32
TP411 MS_DATA2
XD_D2/SD_CMD 32 XD_RDY/SD_W P/MS_CLK 1 16 XD_ALE/SD_D7/MS_D3 32
TP412 XD_R/B MS_DATA3
XD_D3/SD_D4/MS_D4 32 XD_RE#/MS_INS# 2
TP413 XD_RE
XD_D4/SD_D3/MS_D1 32 XD_CE#/SD_D1 3 21 XD_D6/MS_BS 32
TP414 XD_CE MS_BS
XD_D5/SD_D2/MS_D5 32 XD_CLE/SD_D0/MS_D7 4 17 XD_RE#/MS_INS# 32
TP415 XD_CLE MS_INS
XD_D6/MS_BS 32 XD_ALE/SD_D7/MS_D3 5 15 XD_RDY/SD_W P/MS_CLK 32
TP416 XD_ALE MS_SCLK
XD_D7 32 XD_W E#/SD_CD# 6
TP417 XD_WE
32 XD_W P/SD_D6/MS_D6 7 XD_WP
32 XD_CD# 34 XD_CD_SW 4IN1_GND 13
4IN1_GND 22
NP1 NP1 4IN1_GND 38
NP2 NP2 4IN1_GND 37 1
B TP7124 B
CARDBUS36P-1-GP
2010/01/15
20.I0109.001 2010/01/15
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 71 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
RESERVED
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 72 of 88
5 4 3 2 1
5 4 3 2 1
SSID = User.Interface
D D
BT1
15 +3.3V_RUN
NP1
AFTP7319 1 BLUETOOTH_DET# 1 2 BT_ACT 76
76 W LAN_ACT 3 4
AFTP7311 1 5 6 USB_PP4 21
37,76 BLUETOOTH_EN_L 7 8 USB_PN4 21
AFTP7308 1 BT_LED 9 10
AFTP7318 1 BLUETOOTH_GPIO3 11 12
1
AFTP7316 1 BLUETOOTH_GPIO5 13 14
NP2 C7303
16 1 AFTP7313 SC2D2U6D3V3KX-GP
2
C C
HRS-CONN14D-GP-U
20.F0987.014
AFTP7314 1 W LAN_ACT
AFTP7309 1 BLUETOOTH_EN_L
76 BT_ACT BT_ACT AFTP7315 1 BT_ACT
37,76 BLUETOOTH_EN_L BLUETOOTH_EN_L AFTP7312 1 +3.3V_RUN
76 W LAN_ACT W LAN_ACT AFTP7310 1 USB_PP4
AFTP7317 1 USB_PN4
10KR2J-3-GP
1
1
Do Not Stuff
Do Not Stuff
1
B B
R7305
R7304
EC7306
DY DY
2
2
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Bluetooth
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 73 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 74 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 75 of 88
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Support
D D
IOBD1
NP2
65
+PW R_SRC
+PW R_SRC 64 66
31 30
32 29
33 28
BATT SMBUS 37 BAT_SDA 34
35
27
26
37 BAT_SCL
WLAN SMBUS 7,18,19,22 ICH_SMBDATA 36
37
25
24
7,18,19,22 ICH_SMBCLK +5V_ALW
CLK_PCIE_MINI1# 38 23 +KBC_PW R
7 CLK_PCIE_MINI1# CLK_PCIE_MINI1
WLAN CLK 7 CLK_PCIE_MINI1 39
40
22
21
+3.3V_ALW
E51_RXD 37
21 PCIE_RXN2 PCIE_RXN2 41 20 E51_TXD 37
PCIE_RXP2
C
WLAN PCIE 21 PCIE_RXP2 42
43
19
18
BAT_IN# 37
C
AC_IN# 37
PCIE_TXN2 44 17 PSID_DISABLE# 37
21 PCIE_TXN2 PCIE_TXP2
WLAN PCIE 21 PCIE_TXP2 45
46
16
15
PSID_EC 37
AD_IA 37
USB_PN6 47 14 W IFI_RF_EN 37
21 USB_PN6
USB_PP6
WLAN USB 21 USB_PP6 48
49
13
12
MINI1_CLKREQ# 7
PCIE_W AKE# 22
7 CLK_PCIE_LAN# 50 11 PLT_RST# 11,21,37,58
LAN CLK 7 CLK_PCIE_LAN 51
52
10
9
PM_LAN_ENABLE 37
KBC_PW RBTN# 37
21 PCIE_RXN3 53 8 BT_ACT 73
LAN PCIE 21 PCIE_RXP3 54
55
7
6
BLUETOOTH_EN_L 37,73
W LAN_ACT 73
21 PCIE_TXN3 56 5 +3.3V_RUN
LAN PCIE 21 PCIE_TXP3 57
58
4
3 +1.5V_RUN
USB_PN0 59 2 +5V_USB1
21 USB_PN0
USB_PP0
USB Port 21 USB_PP0 60 1
63 61
62
NP1
ACES-CONN60C-1-GP-U
20.F1563.060
B B
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1
1
C7601
C7603
C7604
C7605
C7606
C7607
C7609
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
2
Title
www.vinafix.vn
A3 DJ1 Montevina UMA A00
Date: Friday, February 26, 2010 Sheet 76 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 77 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Reserved
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 78 of 88
5 4 3 2 1
5 4 3 2 1
SSID = Mechanical
H21 H22 H23
Do Not Stuff Do Not Stuff Do Not Stuff
SPR1 HBT1 HMI2
SPRING-51-GP STF237R115H123-GP STF217R128H83-GP
+PW R_SRC +PW R_SRC +PW R_SRC +PW R_SRC +PW R_SRC +PW R_SRC
34.4F822.002 34.4A902.001 34.4Y702.001
1
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
D D
2nd 34.4H103.201
2
EC7901
EC7902
EC7903
EC7904
EC7905
EC7906
1
1
H3 H2 H6 H1 H7 +PW R_SRC +PW R_SRC +PW R_SRC +PW R_SRC +PW R_SRC +PW R_SRC +PW R_SRC +PW R_SRC +PW R_SRC +PW R_SRC
Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
Do Not Stuff
Do Not Stuff
2
2
EC7907
EC7908
EC7909
EC7910
EC7911
EC7925
EC7926
EC7922
EC7923
EC7924
DY DY
1
1
1
Do Not Stuff
1
SCD1U50V3KX-GP
SCD1U50V3KX-GP
Do Not Stuff
C C
2
H20
EC7912
EC7913
EC7914
H4 H13
H18 H8
Do Not Stuff DY
Do Not Stuff Do Not Stuff
1
Do Not Stuff Do Not Stuff
1
1
1
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
1
2
EC7915
EC7916
EC7917
EC7927
EC7928
EC7929
DY EC7921 DY DY DY
1
+3.3V_RUN +3.3V_RUN +3.3V_RUN +3.3V_RUN +3.3V_RUN +3.3V_RUN
B B
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
2010/01/07
2
EMI Request
EC7918
EC7919
EC7920
EC7936
EC7937
EC7938
G6002 G6003 G6004
1
1 2 1 2 1 2
Do Not Stuff Do Not Stuff Do Not Stuff +5V_ALW +5V_ALW +5V_ALW +5V_ALW +5V_ALW
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
SCD1U50V3KX-GP
Do Not Stuff
2
2
EC7930
EC7931
EC7932
EC7933
EC7934
DY
1
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 79 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
(Reserved)
Size Document Number Rev
www.vinafix.vn
A3 DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 80 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
(Reserved)
www.vinafix.vn
Size Document Number Rev
C DJ1 Montevina UMA A00
Date: Wednesday, February 24, 2010 Sheet 81 of 88
5 4 3 2 1
5 4 3 2 1
D D
C (Blanking) C
B B
A A
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
(Reserved)
Size Document Number Rev
www.vinafix.vn
A2 DJ1 Montevina UMA A00
Date: Wednesday, February 24, 2010 Sheet 82 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
(Reserved)
www.vinafix.vn
Size Document Number Rev
C DJ1 Montevina UMA A00
Date: Wednesday, February 24, 2010 Sheet 83 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
(Reserved)
www.vinafix.vn
Size Document Number Rev
Custom DJ1 Montevina UMA A00
Date: Wednesday, February 24, 2010 Sheet 84 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A A
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
(Reserved)
www.vinafix.vn
Size Document Number Rev
Custom
DJ1 Montevina UMA A00
Date: Wednesday, February 24, 2010 Sheet 85 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
(Reserved)
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 86 of 88
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A DJ1 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
(Reserved)
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: W ednesday, February 24, 2010 Sheet 87 of 88
5 4 3 2 1
5 4 3 2 1
X01
D
2 54 2010/01/04 Wistron D4102 Change D4102 change to 83.00054.Q81 D
3 37 2010/01/04 Wistron MB version chang to X01 Change R3722 pop,R3727 dummy. X01
4 59 2009/01/06 Wistron ME change ODD&RTC Conn Change ODD Conn to 22.10300.811 X01
Change RTC Conn to 62.70001.011
7 42 2010/01/07 Wistron Change R4210 for POP noise Change R4210 to 10K 63.10334.1DL X01
8 60 2010/01/08 IDT IDT Request change EMI CAP to 0.01u EC6005 EC6006 change to 0.01u 78.10321.2FL X01
9 63 2010/01/11 Wistron USB power switch change Change U6301 U6302 to 74.07534.079 X01
11 37 2010/01/12 DELL Add one capacitor for IPCC function Add C3721 close KBC Pin AD_IA X01
12 69 2010/01/14 Wistron SMT issue Change HSC1 layout symbol to Seiko 74.05711.07B X01
B B
13 47 49 50 2010/01/16 Wistron Power team request change PC4740 PC4741 PC4910 PC5020to 78.33124.2FL X01
16 37 2010/02/10 Wistron Change PCB version from X01 to A00 DY R3722 and R3728, stuff R3727 and R3723 A00
A
19 69 2010/02/25 Wistron Do not stuff R6902 Reserve R6902 DJ1
A00 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Change History
Size Document Number Rev
www.vinafix.vn
A3
DJ1 Montevina UMA A00
Date: Thursday, February 25, 2010 Sheet 88 of 88
5 4 3 2 1