A B C D E

CPU DC/DC
Compal Confidential TPS51622ARSMR 50~51
Model Name : INPUTS OUTPUTS
Intel Broadwell U / Haswell Block Diagram B+ VCC_VORE
Project Name : SYSTEM DC/DC
1 1

eDP to LVDS Converter RT8243AZQW 47

LVDS Panel Conn. (RTD2136N) eDP
page19 page18
204pin DDRIII-SO-DIMM X2 INPUTS OUTPUTS
Memory Bus
page15, 16
B+ 3VDS/5VDS
1.35V DDR3L 1600MHz

DP to VGA Converter SYSTEM DC/DC

CRT Conn. (IT6513FN) DDI
page31 page31 RT8207MZQW 48
USB20 USB20 USB30 USB30 INPUTS OUTPUTS
Right Right Left Left Touch CMOS
FingerPrint
HDMI Conn. Camera 1.35V_VDDQ
DDI Broadwell page25 page25 page25 page25 page19 page43 page19 B+
page20
0.675VS
( Haswell )
USB2.0 SYSTEM DC/DC
AMD Topaz VGA PCIEx4 USB3.0 SY8206DQNC
2
128Mx16 / 256Mx16
49 2
Option
DDR3 x4 VRAM SATA
page33
INPUTS OUTPUTS
B+ 1.05VS
WWAN / SSD
PCIeMini Card (Half)
SATA HDD 2.5" SATA ODD NGFF M2 Conn. WLAN & BT Combo SYSTEM DC/DC
Int. Speaker page21
page22 page22 page21
AUDIO CODEC
SY8003DFC 52
HD Audio
Audio Jack (Realtek ALC3227) INPUTS OUTPUTS
( HeadPhone, MIC)
PCIE x1 B+ 1.5VS
page26
Digital MIC x2 SYSTEM DC/DC
LAN(GbE) Card Reader
RT8880BGQW 54~55
Realtek RTL8161GSH-CG RT5237-GR
page23 page24 INPUTS OUTPUTS
3 3
Wifi on/off & B+ +VGA_CORE
Audio Mute / B
page4~14
page43

LPC Bus SPI SYS BIOS ROM SYSTEM DC/DC

Power/B page33
8MB SY8003DFC 56
page29 page32
KBC
SMSC MEC1322-NU INPUTS OUTPUTS
Fan Control TPM
SLB9660TT1.2 B+ +1.8VS_VGA
page29 page30
PS/2
LPC Debug
Conn. page32

RTC CKT. Thermal Touch Pad Int.KBD Accelerometer SYSTEM DC/DC

page7 page43 page28 ST HP3DC2 CPU XDP
page6 page30 SY8003DFC 57
Conn. page6

DC/DC interface CKT. INPUTS OUTPUTS

4
PCH XDP 4
page40 Conn. page6 B+ +0.95VS_VGA
Power Circuit

page44~57

Issued Date

A B C D E
 A B C D E

@ is NO SMT part (empty) LVDS@ : Support LVDS panel. WWAN@ : For WWAN function. PX@ : GPU BOM config.
short@ : short pad , don't pop. eDP@ : Support eDP panel.
@EMI@,@ESD@,@RF@ : Reserve , don't pop.
RF@ : RF team request, must add.
1 1
EMI@ : EMI team request, must add.
ESD@ : ESD team request, must add.

+3VS
UCPU1
R=10K

F3 I2C_0_SCL
F2 I2C_0_SDA

+3VS

R=10K
2 2

F1 I2C_1_SCL
G4 I2C_1_SDA

TouchPad

<USB2.0 port>
+3V_PCH +3VS
CPU XDP
DESTINATION
USB2.0 port
CS
R=2.2K R=10K 0 USB 2.0(Right side)
AP2 SMBCLK PCH_SMBCLK
AH1 SMBDATA 2N7002 PCH_SMBDATA SO-DIMM A 1 USB 2.0(Right side)
2 USB 2.0(Left side)
+3V_PCH
3 WLAN/BT
R=1K
SO-DIMM B
4 Finger Print
AN1 SML0CLK WWAN
AK1 SML0DATA 5 (Option)
Touch
6 Camera

3
USB 2.0(Left side) 3
7
ACCELEROMETER

+3V_PCH
+3VGS
PX@
R=2.2K R=10K
AU3 SML1CLK
AH3 SML1DATA
<PCI-E,SATA,USB3.0>
2N7002 R=0ohm 2N7002 GPU
SML1CLK_R VGA_SMB_DA3
0x96 PX@ DESTINATION
SML1DATA_R VGA_SMB_CK3 PX@
Lane# PCI-E SATA USB3.0
@ R=0ohm CS
+3VDS 1 0 USB3.0
U17:+3VDS 2 1 USB3.0
R=10K 3 1 2 WWAN (M.2)
KBC_I2CLK 4 2 3 Card reader(PCI-E)
125
KBC_I2CDAT
126 5 3 10/100/1000 LAN
+3VDS
+3VS 6 4 WLAN (M.2)
7 GPU(DIS only)
PCH_KBC_I2CLK R=10K +3VS R=10K +3VS
8 GPU(DIS only)
88 PCH_KBC_I2CDAT 5
EC 2N7002 9 GPU(DIS only)
89 Thermal Sensor 10 GPU(DIS only)
+3VDS
11 L3 3 2.5"HDD
R=4.7K 12 L2 2 ODD
6
4 I2C_MAIN_DAT 13 L1 1 4
111 BAT
I2C_MAIN_CLK R=100
112 14 L0 0 SSD(NGFF)

R=0 Charger

Issued Date

A B C D E
 5 4 3 2 1

HASWELL_MCP_E CC97~CC102 must closed to connector not CPU

<eDP>
D D

DDI EDP

<eDP>

DG V0.9 PEG_COMP
Trace width=20mil and spacing=25mil

1
Max length=100mil
HASWELL_MCP_E

1
C C
MISC

2
JTAG
THERMAL

1
PWR

3
DDR3

DG V0.5 Trace width=12~15 mil

Max length=500mil
DDR3 COMPENSATION SIGNALS
B B

1
2
A A

Issued Date

5 4 3 2 1

Compal Electronics, Inc.

 5 4 3 2 1

HASWELL_MCP_E

HASWELL_MCP_E <DDR3L>
<DDR3L>
D D

C C

DDR CHANNEL B

DDR CHANNEL A

B B

A A

Issued Date

5 4 3 2 1

Compal Electronics, Inc.

 5 4 3 2 1

INTVRMEN RTC BAT conn

Integrated VRM enable

1
* HLIntegrated VRM disable
CMOS

2
15mils 15mils
15mils

1
ME CMOS

2
2
D D

C124

2
5
1

G
G
1
HASWELL_MCP_E

S
D
S
D
0.1U_0402_10V6K

2
VBIOS ID TALBE
2

RTC

1
2.5" SSD/HDD

3
1

ODD
1

AUDIO
2

SATA
WWAN (M.2 slot)
2
1

<Page 12>
JTAG
C
DG V0.9 SATA_COMP C

1
1

Width=12mil
Max length=500mil

2
2

2
G
S
D
<CPU site>

CC125
CC126

0.1U_0402_16V4Z
2.2U_0402_6.3V6M

<PCH site>
<XDP>
B B

1
<XDP> <PCH site>

2
<CPU>

<PCH site> <XDP>

<CPU,XDP,XDP Switch>
<EC output>
<XDP>

<PCH site>
Resistors Resistors
Topolog Description Be st Use for Stuffed ufStuffed
<PCH site>
<XDP> Default Setting: Dual In this topology, the - Run control oper. R1d,R2,R3d, J1s, J2s,
TCK S can Chains CPU JTAG chain will be - ME/Sx debug R4,R5,J1d J3s
(also known as controlled by TCK0 and J2d,J3d* R6,R7,R8,R9
"Shared JTAG" in TCK1 will control J4d and Rs5*
other docum ent) the PCH JTAG chain.
XDP_TCK:XDP contact with CPU No 0ohm(RS5)

A In th is topolog y, PCH -B oundary Scan/ J1s,J2s,J3s** R1d,r3d,J1d,J2d A

Single TCK scan chain TDI- TDO and CPU TDI-TDO Manufacturing est R2,R4,R5,R5s** J3d**,J4d,
<PCH site>
(also known as "Com m on R6,R7,R8,R9
will be chained to form
JTAG" in other docum one JTAG scan chain
ent) controlled by TCK0
<CPU and XDP>

<PCH site>

Compal Electronics, Inc.

Issued Date
<XDP>
<PCH site>

5 4 3 2 1
 5 4 3 2 1

HASWELL_MCP_E

D D
PCIE Card reader <Page12>
CLOCK
SIGNALS
PCIE LAN
<EC>

WLAN
<LPC Debug>
GPU
<XDP CLK reserve TP>

HASWELL_MCP_E

LPC
C SMBUS C

SPI C-LINK
2
2

2
1
1

PCH KBC
5

2
2
B B

2
1
1

5
2

CPU THERMAL SENSOR

5

1
3
A A

Compal Electronics, Inc.

Issued Date

5 4 3 2 1
 5 4 3 2 1

DSWODVREN - On Die DSW VR Enable

C121
C128
C127
Non Deep S3 RC91-->SMT H• Enable
Deep S3 RC93-->SMT *
HASWELL_MCP_E
L• Disable
SYSTEM POWER MANAGEMENT

0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
D D

C129
Deep S3

0.1U_0402_10V6K
Non Deep S3 RC286-->@
Deep S3 RC286-->SMT

C114
1

2
2

0.1U_0402_10V6K
C123
Pinout on customer's board,
as in the PDG, CDI #514849

0.1U_0402_10V6K
Pin Pin
C
1 VccSus3_3 10 GND C
2 SLP_S3# 11 PWRBTN#
3 VccDSW3_3 12 GND
4 SLP_S5# 13 SYS_RESET#
5 SLP_S4# 14 GND
6 SLP_A# 15 SLP_S0#
7 +3.3DS 16 NC
8 GND 17 NC
9 RTCRST# 14 NC

HASWELL_MCP_E

PANEL_BKEN_CPU PD 100K on Page20

eDP SIDEBAND
<HDMI>

DISPLAY

5
B B

<HDMI>

<eDP HPD>

0.1

0.2
0.3

1
1
1
1

0.4
2
2
2
2

0.5

5
1
1
1
1

P
<CPU>

G
2
2
2
2

3
A A

Compal Electronics, Inc.

Issued Date

5 4 3 2 1
 5 4 3 2 1

1
HASWELL_MCP_E

2
CPU/
DG V0.9 PCH_OPIRCOMP
MISC Width=12mil,spacing=12mil
D Max length=500mil D

Boot BIOS Strap

PCH_GPIO86 Boot BIOS Location

0 SPI
GPIO
*

2
1
LPIO

2
1

1
C C

2
6
1

5
B B

P
G
3

C116
0.1U_0402_10V6K
PCH Strap Platform ID
1
2
1

*
2

A A

Issued Date

5 4 3 2 1
 5 4 3 2 1

HASWELL_MCP_E

D D

C C

USB

DG V0.9 USBRBIAS
Trace width=50ohm and spacing=15mil
Max length=500mil

Card Reader

B B

<Page12>

DG V0.9 PCIE_RCOMP
Width=12mil,spacing=12mil
Max length=500mil

A A

Issued Date

5 4 3 2 1
 5 4 3 2 1

+VCC_CORE@10000mA

HASWELL_MCP_E

2500mA

D D

1
DG V0.5 H_CPU_SVIDALRT#
RC154 close to CPU<300mil

1
Max length=1000~2000mil

1
HSW ULT POWER

2
C C

600mA

DG V0.5 VIDSOUT
RC156 close to CPU<500mil
Max length=1000~2000mil

B B

1
RC166
2

150_0402_5%
2
1
@
1 7 CC
2 7 CC

RC167
10K_0402_5%
2
K6 V3. 6_20 40_ U1

M6 V3. 6 _508 0_ U22

CC20
CC21
CC22
CC23
CC26
CC27
CC28
CC29
CC30
CC31

10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M

2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M

A A

Compal Electronics, Inc.

Issued Date

5 4 3 2 1
 A
B
C
D

5
5

36 CC 75 CC
M6 V3. 6_ 50 80 _ U74 M6 V3. 6_ 50 80 _ U22
85 CC
46 CC K6 V3. 6 _2 04 0_ U1 24 CC 53 CC
K6 V3. 6 _2 04 0_ U1 M6 V3. 6_ 50 80 _ U74 M6 V3. 6_ 50 80 _ U74
16 CC
K6 V3. 6 _2 04 0_ U1
34 CC 63 CC
77 CC K6 V3. 6 _2 04 0_ U1 K6 V3. 6 _2 04 0_ U1
M6 V3. 6_ 50 80 _ U74
26 CC 55 CC
K6 V3. 6 _2 04 0_ U1 M6 V3. 6_ 50 80 _ U22
4
4

15 CC
K6 V3. 6 _2 04 0_ U1
86 CC
M6 V3. 6_ 50 80 _ U74
96 CC
K6 V3. 6 _2 04 0_ U1 14 CC
95 CC K6 V3. 6 _2 04 0_ U1 33 CC
M6 V3. 6_ 50 80 _ U22 K6 V3. 6 _2 04 0_ U1
87 CC
M6 V3. 6_ 50 80 _ U74
43 CC
97 CC K6 V3. 6 _2 04 0_ U1
M6 V3. 6_ 20 40 _ U01
07 CC
K6 V3. 6 _2 04 0_ U1

3
3

Issued Date
ICC
OPI
mPHY

USB3

GPIO/LCC
AXALIA/HDA

LPT LP POWER
VRM/USB2/AZALIA
HASWELL_MCP_E

SPI
RTC

CORE

Deep S3 RC285-->SMT
USB2
SDIO/PLSS

Non Deep S3 RC182-->SMT

THERMAL SENSOR

SUS OSCILLATOR

Total 3VS=0mA
Total 1.8VS=7mA
Total 1.5VS=3mA

Total 3V_PCH=99mA

2
2

Total 1.05V=540+109=649mA
Total 3VALW=200+62=262mA
Total 1.05VS=1838+2274=4111mA
56 CC
K6 V3. 6 _2 04 0_ U1
06 CC 23 CC
0.1U_0402_16V7K
K6 V3. 6 _2 04 0_ U1 K6 V3. 6 _2 04 0_ U1
CC37
35 CC
K6 V3. 6 _2 04 0_ U1
45 CC
K6 V3. 6 _2 04 0_ U1 M6 V3. 6_ 50 80 _ U22 93 CC
66 CC K6 V3. 6 _2 04 0_ U1
84 CC
K6 V3. 6 _2 04 0_ U1
76 CC 94 CC
K6 V3. 6 _6 02 1_ U0 01 K6 V3. 6 _2 04 0_ U1

1
1

05 CC
M6 V3. 6_ 30 60 _ U01

SDIO power rail

SPI ROM power rail

A
B
C
D
 5 4 3 2 1

HASWELL_MCP_E

HASWELL_MCP_E

HASWELL_MCP_E
D D

C C
1

B B
2

A A

Issued Date

5 4 3 2 1
 5 4 3 2 1

HASWELL_MCP_E

1
2
D D

HASWELL_MCP_E
*

C C
2

HASWELL_MCP_E

B B

RESERVED

DG V0.9 PROC_OPI_COMP
Width=12mil,spacing=12mil
Max length=500mil

A A

Issued Date

5 4 3 2 1
 D

A
10U_0603_6.3V6M
1

1
CD24

CD21
0.1U_0402_16V7K

CD19
S 0.1U_0402_16V7K
G
2
D

1 2 1 2
2

2
CD3
0.1U_0402_16V7K
DDR_A_MA11

DDR_A_MA6

Issued Date
3

3
DDR_A_MA8

1 2
CD1
0.1U_0402_16V7K CD17
0.1U_0402_16V7K
4

CD13 CD66
10U_0603_6.3V6M 1U_0402_6.3V6K

CD12 CD65
10U_0603_6.3V6M 1U_0402_6.3V6K

CD11 CD64
10U_0603_6.3V6M 1U_0402_6.3V6K

CD10 CD63
10U_0603_6.3V6M 1U_0402_6.3V6K

CD9 CD58
10U_0603_6.3V6M 1U_0402_6.3V6K

CD8 CD57
10U_0603_6.3V6M 1U_0402_6.3V6K

CD7 CD56
5

10U_0603_6.3V6M 1U_0402_6.3V6K

CD6 CD55
10U_0603_6.3V6M 1U_0402_6.3V6K
D

A
 D

A
1

1
10U_0603_6.3V6M

CD50

CD46
0.1U_0402_16V7K

CD45
0.1U_0402_16V7K
2

2
CD29
0.1U_0402_16V7K
DDR_B_MA11

DDR_B_MA6

Issued Date
3

3
DDR_B_MA8

CD27
0.1U_0402_16V7K CD44
0.1U_0402_16V7K
4

CD40 CD70
10U_0603_6.3V6M 1U_0402_6.3V6K

CD39 CD69
10U_0603_6.3V6M 1U_0402_6.3V6K

CD38 CD68
10U_0603_6.3V6M 1U_0402_6.3V6K

CD37 CD67
10U_0603_6.3V6M 1U_0402_6.3V6K

CD36 CD62
10U_0603_6.3V6M 1U_0402_6.3V6K

CD35 CD61
10U_0603_6.3V6M 1U_0402_6.3V6K
5

CD34 CD60
10U_0603_6.3V6M 1U_0402_6.3V6K

CD33 CD59
10U_0603_6.3V6M 1U_0402_6.3V6K
D

A
 5 4 3 2 1

DDR3L VREF
D D

1
1

2
2
<CPU> <DDR3L_A> <DDR3L_A_CA>
<CPU>
<DDR3L_B_CA>

1
1

1
1

2
2

2
2
C C

1
2
<CPU> <DDR3L_B>

1
2

2
B B

A A

Issued Date

5 4 3 2 1
 5 4 3 2 1

80mil 80mil
• • •

2
2

CT29
CT30
CT31
CT32
CT33
CT34
CT35
CT36
CT37
D D

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1

CT38
CT39
CT40
2
2

0.1U_0402_16V4Z
0.1U_0402_16V4Z

10U_0603_6.3V6M
1
1

PIN47 PIN48

SWR / LDO Mode select

40mil
LDO SWR
80mil 100mil
40mil
2132S Do not support mount LT7
40mil

PWR
40mil
2132R Use 0 ohm mount LT7
40mil
C C
40mil
• If use 2132R, please select LDO mode as default.

DP
SD VL

1
<to connector>

2
OTHERS
B B

D NG
PIN15 PIN16 Accept voltage input (high level)

2132S TL_ENVDD 2132S 3.3V

<LVDS panel>
2132R +LCD_VDD * 2132R 1.5~3.3V

* Version R internal Power Switch, can * Version R has internal level shifter, remove
output 1A, Rds(on)=0.2 ohm level shifter circuit on AMD platform

Different between 2132S and 2132R

1

2132S 2132R
2

5
100K_0402_5%

1. Support SWR mode 1. Support LDO mode and SWR mode

2. Internal ROM
A A
<RTS2132> <LVDS Panel>

CCV
3. Support LCD_VDD(internal Power switch)
<PCH CTRL> 4. Integrates Level shifter

DN G
3
Issued Date

5 4 3 2 1
 5 4 3 2 1

W=60mils W=60mils

D SM010014520 3000ma D
220ohm@100mhz
DCR 0.04

0.1U_0402_16V7K

4.7U_0603_6.3V6K
LCD/LED PANEL Conn.

C C

Touch

1
2
3
2
B B

1
3
2

GPIO92 GPIO93
1

PLT_ID2 PLT_ID3

A Rolo 14" 0 1 A

Reeses 15" 1 0
Issued Date
Raisinet 17" 1 1
LA-B181P

5 4 3 2 1
 5 4 3 2 1

1
2
D D

5
6
7
8
5
6
7
8
1

5
5V Level

4
3
2
1
4
3
2
1
2

%5_2040_ K02

C C
5
2

5V PULL UP IN CONNECTER SIDE

B B
HDMI Conn.

W=40mils
10P_0402_50V8J
10P_0402_50V8J

A A

Issued Date

5 4 3 2 1
 D

A
39P_0402_50V8J

39P_0402_50V8J
1

1
39P_0402_50V8J

4.7U_0805_10V4Z
6 1

C74 WWAN@

0.1U_0402_10V6K

C73 WWAN@

0.01U_0402_16V7K

C72 WWAN@

18P_0402_50V8J
2

2
4.7U_0805_10V4Z

C77

0.1U_0402_10V6K

C78

1 2
WWAN

3 1

0.1U_0402_10V6K
1 3

C79

Issued Date
2 1

1 2
3

3
1 2
S
G
1 2 2
D

S
G
2
D
4

1 2

S
1 2 2
G 1 2 3 4
D

1 2

3 4

CN3
0.1U_0402_16V7K

2 1 6 1
5

5
WLAN

A
 D

A
1

1
Pleace near ODD Connector
CS12
10U_0805_10V6K

CS13
2

2
0.1U_0402_25V6K

CS16
1000P_0402_50V7K
3

3
Issued Date
1U_0603_10V6K

C150
0.1U_0402_16V7K
2 1 3 4
10U_0603_6.3V6M

C149
10U_0603_6.3V6M
D

2
G
S
4

4
2.5" SATA HDD connector

1 2

C4820

0.1U_0402_16V7K

6 1
5

5
D

A
 A
B
C
D

S
5
5

G
2 1 2
D
S
2 1 G
2 1 2
TSL1

D
SP050005L00 Footprint

4
4

22
01 D DV D
03 K6 V3. 6_3060_ U7. 4 8L C
3 01 D DV A
1 3 K6 V3. 6_3060_ U7. 4
2 01 D DV A
8
01 D DV A
9L C
11 K6 V3. 6_3060_ U7. 4 K7 V61_2040_ U1. 0
33 D DV A
23
33 D DV A
CL25 close to UL1: Pin 11
CL24 close to UL1: Pin 32

32
QE R DDV
CL8& CL9 close to UL1: Pin 23

K7 V61_2040_ U1. 0
CL22 & CL23 close to UL1: Pin 11,32

K7 V61_2040_ U1. 0
2 1 2 1

3
3

3 1
2 1

Issued Date
+VDDREG=40mil
+LAN_REGOUT=60mil
+LAN_VDD_3V3=40mil

D
2
CL12 & CL13 close LL2

G 21L C
S
K6 V3. 6_3060_ U7. 4
31L C
K7 V61_2040_ U1. 0
2 1
10K_0402_5%
RL37
K7 V61_2040_ U1. 0

2
2

K7 V61_2040_ U1. 0
3
1 K7 V61_2040_ U1. 0
2
1 2
27P_0402_50V8J
K7 V61_2040_ U1. 0
Place CL14~CL16 close UL1 Pin 3, 8 , 22

2 1
DN G CS O
4 3
DN G CS O
1U_0402_6.3V6K
27P_0402_50V8J
K7 V61_2040_ U1. 0
1U_0402_6.3V6K

RJ-45 CONN.

1
1

CL19 & CL20 close UL1 Pin30

CL17 & CL18 close UL1 Pin22

A
B
C
D
 5 4 3 2 1

D D

C C

B B

A A

Issued Date

5 4 3 2 1
 A B C D E

USB3.0

1 1

USB3.0 need support 2.5A

change USB PWR SW SA00003TV00
low active

W=100mils W=100mils

9
DAP E
0.1U_0402_16V7K

1000P_0402_50V7K
2 2

3 3

USB2.0

4 4

Issued Date

A B C D E
 D

A
AZ2015-02S_SOT23-3
2
1
3

I ME @ 2594 C
@
680P_0603_50V7K
1 2 K7 V05_2040_ P022
I ME @ 1594 C
@
10U_0805_10V6K
1

1
K7 V05_2040_ P022
I ME @ 0594 C
@
0.1U_0402_25V6
K7 V05_2040_ P022
CA53
I ME @ 9494 C
@
4.7U_0603_6.3V6K 8
P G
4
P G
K7 V05_2040_ P022
CA52 8 4
.1U_0402_16V7K

600ohms @100MHz 2A
0.1U_0402_16V7K

P/N: SM01000EE00
2.2U_0402_6.3V6M

2
1 1 2
W=40Mil

MIC Pre-AMP
CA44
10U_0603_6.3V6M

CA41
.1U_0402_16V7K 1 2

2
1
2

2
3

CA40
10U_0603_6.3V6M CA63
10U_0603_6.3V6M

CA43 CA62
.1U_0402_16V7K 10U_0603_6.3V6M
22K_0402_5%
1 2 CA61
.1U_0402_16V7K

22K_0402_5%
CA60
1 2
.1U_0402_16V7K

Issued Date
1 2 1 2
<INT SPK>

1 2

6 1
3

3
1 2
MIC SENSE

3 4 1 2
Power down (PD#) power stage for save power
0V: Power down power stage
3.3V: Power up power stage

0.1U_0402_25V6

1U_0402_6.3V6K
4

1 2

1 2

1 2 1 2

C
1 2 2
B
E
1 2 6 1

1 2

1 2
5

10P_0402_50V8J

10P_0402_50V8J

1 2
D

A
 5 4 3 2 1

D D

C C

B B

A A

Issued Date

LA-B181P

5 4 3 2 1
 100P_0402_50V8J
C596

100P_0402_50V8J
C595

100P_0402_50V8J
C594
Keyboard conn

Issued Date

1 2 1 3

C295
0.047U_0402_16V7K
KB backlight Conn

3 1
 A B C D E

Power Button Connector Fan Control Circuit

2
2
1 1

1
1
2
PJ9 place Top layer,
PJ6 place Bottom layer
Close to Connector
1A 40 mils
1000P_0402_50V7K

2 2

3 3

4 4

Issued Date

A B C D E
 D

A
100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J
C576 C574 C588

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

C108 C106 C137

100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J

C579 C577 C587
1

1
6 1

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

C111 C109 C136
1 2 3 4

1 1 2 3
100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J
C578 C580 C586
1 2

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

C110 C112 C135

100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J

C569 C571 C585

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

C95 C96 C134

100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J

C567 C568 C584
1 2
2

2
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
C93 C94 C133

100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J

C566 C563 C583

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

C92 C89 C132

100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J

C565 C562 C582

Issued Date
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
C91 C86 C131

100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J

1 2 1 2
C564 C561 C581
3

3
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
C90 C84 C130

100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J

C558 C560 C573
RF CAP

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

C81 C83 C105

100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J

C556 C559 C572 C589

1 2

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

C80 C82 C97 C138

DDV DN G
4

5 DDV 4DN G
01 DDV 11 DN G
91 DDV 81 DN G
42 52

1 1 1

1 1 1

1 2
1 1 1

1 1 1

1 1 1

1 1 1
PP:default set to low

1 1 1
5

1 1
1 1 1

1 1 1

1 1 1 1 1 1
D

A
 5 4 3 2 1

1
Note: Depend on

2
Project, if Vp-p small Note: Depend on
the 50mV change to 0 Project, if Vp-p small
the 50mV change to 0

0.1U_0402_16V4Z
0.1U_0402_16V4Z
ohm

10U_0603_6.3V6M
4.7U_0603_6.3V6K
ohm

0.1U_0402_16V4Z
D D

1U_0402_6.3V6K
1U_0402_6.3V6K

0.1U_0402_16V4Z
0.1U_0402_16V4Z
For Power consumption
Measurement

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3VS TO +3VS_6513

0.1U_0402_16V4Z

1
1

R4100
R4101
0.1U_0402_16V4Z

2
2

22_0402_5%
22_0402_5%

1U_0402_6.3V6K
1
2
31
84
53
63
83
93
21
41
44
64
18P_0402_50V8J
18P_0402_50V8J

DDVI
DDVI
DDVI
DDVI
C C

D DV O
D DV O
ODDVI
ODDVI

33 DDVI
33 DDVI

L CS CD D
A DS CD D
4
3
2
1
CPU DDI1
(2-Lane only)

5
6
7
8

Note: ISPSCL/ISPSDA for F/W update

2
G
<8> DDI1_HPD

S
D
1
2
B B

DA P

73
94

B ND WP
CRT Connector

5
1
631 R
731 R
731 R

91
01
11

P
W=40mils

G
# EO

3
2
2
2

A A
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
0.1U_0402_16V4Z

5
1
P
G
# EO
%5_2040_57
%5_2040_57
%5_2040_57

3
Security Classification Compal Secret Data
Issued Date Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sheet of
5 4 3 2 1
 A
B
C
D

20mils

0.1U_0402_16V4Z
22P_0402_50V8J
22P_0402_50V8J
5
5

8 6N IP o t es ol C :e to n tu oy aL
971 C
Z4 V61_2040_ U1. 0
4 1N IP o t es ol C :e to n tu oy aL
081 C
Z4 V61_2040_ U1. 0
7 3N IP o t es ol C :e to n tu oy aL
181 C
Z4 V61_2040_ U1. 0
8 5N IP o t es ol C :e to n tu oy aL
281 C
Z4 V61_2040_ U1. 0
4 8N IP o t es ol C :e to n tu oy aL
381 C
Z4 V61_2040_ U1. 0
60 1N IP o t es ol C :e to n tu oy aL
481 C
Z4 V61_2040_ U1. 0
91 1N IP o t es ol C :e to n tu oy aL
581 C
4
4

Z4 V61_2040_ U1. 0
Bus
LPC

86
TA BV*
Keyboard/Mouse Interface
27
D GR WP*
11
74 SSV 85
Power Mgmt/SIRQ

65 SSV 1 CCV 48
401 SSV P8 21 -P FQ T_ UN -2 23 1_ CS MS 1 CCV 601
28 SSV 1 CCV 41
100mA

711 SSV 1 CCV 73

63 SSV 1 CCV 911
SSV 1 CCV
54
S SVA e ca fr et nI O /I e so pr uP l ar en eG
s uo en al le cs iM
2mA

94
#TS R_ GATJ*
Access Bus Interface

Z4 V61_2040_ U1. 0
D
2
D21

G
S

3
3

Z4 V61_2040_ U1. 0
Layout note: 2vias to GND

SA00006PD00 : 128M EN25QH128A-104HIP SOP 8P

Layout note: ADC nets are spaced at least 20mils from any high speed switching signals to prevent cross talk that could add noise

: 64M EN25QH64-104HIP
: 64M N25Q064A13ESEC0F
SA000039A30 : 64M W25Q64FVSSIQ SOIC 8P SPI ROM
SA00005VV10 : 128M W25Q128FVSIQ SOIC8P SPI ROM
RB751V-40_SOD323-2

1 2
2 1 1 2

Issued Date
C115
0.1U_0402_10V6K

2
2

1
1

Compal Electronics, Inc.

A
B
C
D
 1 2 3 4 5

AC Coupling Capacitor
PCIe Gen3: Recommended value is 220 nF
A A
PCIe Gen1 and Gen2 only: Recommended value is 100 nF

B B

TMDP

PCI EXPRESS INTERFACE

C CLOCK C

CALIBRATION

1
1
1

2
2
2

5
5

P
P

G
1
1

3
3

D D

2
2

Issued Date

1 2 3 4 5
 1 2 3 4 5

1
1
1

2
2
2
2
1
DPA

5
2
A A

DVO

1
1
DPB

2
2
2
1
2
DPC

I2C

B B
1

+1.8VS_VGA
2

2
2
2
VGA_AC_BATT pull up

10K_0402_5%
10K_0402_5%
10K_0402_5%

1
1
1
DAC1

1
2
2
2
1

2
1
1
1
2

10K_0402_5%
10K_0402_5%
10K_0402_5%
1

FutureASIC/SEYMOUR/PARK
2

0.1U_0402_16V4Z
C C

2
1
2

3
1
(Default)

4
DDC/AUX

PLL/CLOCK

2
2

D D
1 SEYMOUR/FutureASIC
1

10K_0402_5% THERMAL

Issued Date

1 2 3 4 5
 B
A

D
C

1 6
0.1U_0402_16V7K
1
1

2 1
2 1
4
+3VS to +3VS_VGA (25mA)

2 1
10K_0402_5%
10U_0603_6.3V6M
S
G 1U_0402_6.3V4Z
2
0.1U_0402_16V7K
D
4 3 1 2
10_0603_5%
3 1 2 1
2
2

60mA

2 1
4 3 1 2
+1.5VS to +1.5VS_VGA (2.096A)

6- 36 3 T OS_ N2 G- WK1 D20 0 7 N2 E M

3
3

Issued Date
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_10V6K 10U_0603_6.3V6M
2 1
DP POWER

4
4

4 3 1 2
6- 36 3 T OS_ N2 G- WK1 D20 0 7 N2 E M
NC/DP POWER

6- 36 3 T OS_ N2 G- WK1 D20 0 7 N2 E M

1 6 1 2

GND

5
5

B
A

D
C
 B
A

D
C

1
1

2
2

M6 V3. 6_ 30 60 _ U01 568 4 C

@XP
Z4 V3. 6 _2 04 0_ U1 668 4 C
@XP
1U_0402_6.3V4Z
K6 V0 1_ 20 40 _ U1. 0 768 4 C
@XP
M6 V3. 6_ 30 60 _ U01 928 4 C
K6 V0 1_ 20 40 _ U1. 0 748 4 C
10U_0603_6.3V6M
K7 V61 _2 04 0_ U10. 0 548 4 C
1U_0402_6.3V4Z
1U_0402_6.3V4Z
M5 V3. 6_ 20 40 _ U2. 2 238 4 C
M5 V3. 6_ 20 40 _ U2. 2 338 4 C
M5 V3. 6_ 20 40 _ U2. 2 438 4 C

3
3

M5 V3. 6_ 20 40 _ U2. 2 538 4 C

M5 V3. 6_ 20 40 _ U2. 2 638 4 C
1U_0402_6.3V4Z

Issued Date
0.1U_0402_10V6K
PLL
PCIE
CORE

POWER

CORE I/O
ISOLATED

4
4

M6 V3. 6_ 30 60 _ U01 359 4 C

M6 V3. 6_ 30 60 _ U01 459 4 C M6 V3. 6_ 30 60 _ U01 058 4 C
Z4 V3. 6 _2 04 0_ U1 559 4 C M6 V3. 6_ 30 60 _ U01 158 4 C
+PCIE_VDDC:

2.5A (PCIE3.0)
+PCIE_PVDD:

1.88A (PCIE2.0)

Z4 V3. 6 _2 04 0_ U1 659 4 C
80mA (PCIE3.0)
50mA (PCIE2.0)

10U_0603_6.3V6M
Z4 V3. 6 _2 04 0_ U1 258 4 C
Z4 V3. 6 _2 04 0_ U1 759 4 C
Z4 V3. 6 _2 04 0_ U1 358 4 C
1U_0402_6.3V4Z
K6 V0 1_ 20 40 _ U1. 0 859 4 C
Z4 V3. 6 _2 04 0_ U1 458 4 C
K6 V0 1_ 20 40 _ U1. 0 959 4 C
Z4 V3. 6 _2 04 0_ U1 558 4 C
Z4 V3. 6 _2 04 0_ U1 658 4 C
10U_0603_6.3V6M

5
5

K6 V3. 6 _2 04 0_ U1 758 4 C
1U_0402_6.3V4Z
K6 V3. 6 _2 04 0_ U1 858 4 C
1U_0402_6.3V4Z

B
A

D
C
 1 2 3 4 5

A A

GDDR5/DDR3 GDDR5/DDR3

1
1

2
2

1
1

2
2
B B

E CAF RET NI Y RO ME M

1
2
C C

D D

Issued Date

1 2 3 4 5
 B
A

D
C

2 1
2 1
1
1

2 1 2 1 2 1 2 1
M6 V3. 6_ 30 60 _ U01 588 4 C
@XP
Z4 V3. 6 _2 04 0_ U1 688 4 C
@XP
Z4 V3. 6 _2 04 0_ U1 788 4 C
@XP 2 1
Z4 V3. 6 _2 04 0_ U1 888 4 C
2
2

@XP
Z4 V3. 6 _2 04 0_ U1 988 4 C
@XP
Z4 V3. 6 _2 04 0_ U1 098 4 C
@XP
Z4 V3. 6 _2 04 0_ U1 198 4 C
@XP
Z4 V3. 6 _2 04 0_ U1 298 4 C
@XP
Memory Partition A - Lower 32 bits

K6 V0 1_ 20 40 _ U1. 0 398 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 498 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 598 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 698 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 798 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 898 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 998 4 C
@XP

3
3

2 1 2 1 2 1 2 1

Issued Date
M6 V3. 6_ 30 60 _ U01 009 4 C
@XP
Z4 V3. 6 _2 04 0_ U1 109 4 C
@XP
Z4 V3. 6 _2 04 0_ U1 209 4 C 2 1
@XP
Z4 V3. 6 _2 04 0_ U1 309 4 C
@XP
Z4 V3. 6 _2 04 0_ U1 409 4 C
@XP
Z4 V3. 6 _2 04 0_ U1 509 4 C
@XP
Z4 V3. 6 _2 04 0_ U1 609 4 C

4
4

@XP
Z4 V3. 6 _2 04 0_ U1 709 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 809 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 909 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 019 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 119 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 219 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 319 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 419 4 C
@XP

5
5

B
A

D
C
 B
A

D
C

2 1
2 1
1
1

2 1 2 1 2 1 2 1
M6 V3. 6_ 30 60 _ U01 819 4 C
@XP
Z4 V3. 6 _2 04 0_ U1 919 4 C
@XP
Z4 V3. 6 _2 04 0_ U1 029 4 C
@XP
2
2

Z4 V3. 6 _2 04 0_ U1 129 4 C
@XP
Z4 V3. 6 _2 04 0_ U1 229 4 C
@XP 2 1
Z4 V3. 6 _2 04 0_ U1 329 4 C
@XP
Z4 V3. 6 _2 04 0_ U1 429 4 C
@XP
Memory Partition A - Upper 32 bits

Z4 V3. 6 _2 04 0_ U1 529 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 629 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 729 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 829 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 929 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 039 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 139 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 239 4 C
@XP

3
3

2 1 2 1
2 1 2 1

Issued Date
M6 V3. 6_ 30 60 _ U01 339 4 C
@XP
Z4 V3. 6 _2 04 0_ U1 439 4 C
@XP
Z4 V3. 6 _2 04 0_ U1 539 4 C 2 1
@XP
Z4 V3. 6 _2 04 0_ U1 639 4 C
@XP
Z4 V3. 6 _2 04 0_ U1 739 4 C
@XP
Z4 V3. 6 _2 04 0_ U1 839 4 C
@XP

4
4

Z4 V3. 6 _2 04 0_ U1 939 4 C
@XP
Z4 V3. 6 _2 04 0_ U1 049 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 149 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 249 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 349 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 449 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 549 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 649 4 C
@XP
K6 V0 1_ 20 40 _ U1. 0 749 4 C
@XP

5
5

B
A

D
C
 A B C D E

C575
10U_0603_6.3V6M
1 1

6
3

1
4

C570
CC56
22U_0805_6.3V6M

10U_0603_6.3V6M
2 2

CPU +V1.05DX_MODPHY
Max Rdson <6m ohm
1840mA

1
5
3 3

1
6

2
3
2
1

3
1
1

4
2
1
3
4 4

Issued Date

A B C D E
 5 4 3 2 1

D D

2
2

1
1

8
P
G
4

1
2
8
P
C C

G
4
B B

A A

Issued Date

5 4 3 2 1
 4
3
2
1

A
A

29 5 C
Y5 V0 1_2 04 0_ U7 4. 0
3 1 1 2
B
B

S
2
G
19 5 C D
K7 V61 _20 40 _ U1. 0
20mils

C
C

Issued Date

D
D

E
E

4
3
2
1
 A B C D E

Audio Board
Card Reader Board

C113
1 1

0.1U_0402_10V6K
Card Reader
USB CONN

Finger printer

Touch Pad
Combo Jack

2 2
1
2
3
2
1

1
S
D

3 3
G
2

2
1
3
0.047U_0402_16V7K

4 4

Issued Date

A B C D E
 A
B
C
D

5
5

2
1
3
PD2

2
1
3
ADP_SIGNAL

PD1

<32> AMBER_BATLED#

2 1
8 CP @
I ME
4
4

K7 V05_3060_ U220. 0
2 1
1 CP @
I ME
J 8 V05_2040_ P001
1 6 2 1 4 3
2 1
+5VL

2 1
5 CP @
I ME
J 8 V05_2040_ P001

Issued Date
2 1 1 3 2 1
5A/0.02ohm

+5VL

6 CP @
I ME
K7 V05_2040_ P0001
2 1
VIN

9 CP @
I ME

3
3

K7 V05_3060_ U220. 0
2 1
161 CP
K7 V05_2040_ P0022
@I ME @
<6,32> BAT_GRNLED#
3 1 2 1

2
2

+5VL

1
1

A
B
C
D
 5 4 3 2 1

1
1
5A/0.02ohm

2
3
2
3
D D

1
1

1
2
2

2
I ME 7 CP
@

1
1
1

2
2
2
K7 V05_2040_ U10. 0
C C

MAIN_BAT_DET# <32>

B B

A A

Issued Date

5 4 3 2 1
 5 4 3 2 1

VIN P1
30V/50A/0.0105 ohm/Vgs=2.5V
kelvin connection
30V/14.6A/0.0153 ohm/Vgs=-2.6V
P2 Ilimit=8A B+
8/8

1
1
4
4

1
1
1
1
1
1
1
1
PC102

1
1
D D

I ME
I ME
0.1U_0402_25V6

@
@

2
2
@F R @
@F R @

2
2
2
2
2
2
2
2
2

1
1

101 RP
101 CP
301 RP
2
2
301 CP
401 CP
501 CP

801 CP
061 CP
701 CP
921 CP

@I ME @

1 DP
031 CP
131 CP

6
10@
2
2
1
1

%5_2040_ K022
%5_2040_ K022
401 RP
501 RP

6 V52_2040_ U1. 0
2
2
K6 V52_5080_ U01
K6 V52_5080_ U01
K6 V52_5080_ U01
J 8 V05_2040_ P86
J 8 V05_2040_ P28

901 CP
011 CP

1
30V/14.6A/0.0153 ohm/Vgs=-2.6V

K7 V52_2040_ U220. 0
K7 V52_2040_ U220. 0

J 8 V52_2040_ P0001
K7 V05_2040_ P0022

%1_3060_ K21. 4
%1_3060_ K21. 4
5
B+ P2

3
1
+3VDS 30V/12A/0.024 ohm
ACDET>1.8V(ACPRES open)

6 V52_2040_ U1. 0
ACP_CHG
6 V52_2040_ U1. 0

2- 323 D OS_ F- 7- S W45 T A B

ACN_CHG
ACDET<1.8V(ACPRES close)
P1

ACDRV_CHG
CMSRC_CHG

2
1

4
4

CHRG_ADP_DET

701 RP
PR109

B301 QP
5
4
3
2
1
12
10_1206_1%

3
2
1
ACDET<0.6V(UVLO)
PC111

2
ACDET<3.15V(OVP) 3265mA(max)charge 3S2P BATT
ADP_EN <32> 1U_0603_25V6K Ilimit=4A

DA P

P CA
NCA
6000mA(mzx)discharge 3S2P

%5_2040_ K001
PL102
4.7U 20% VMPI0703AR-4R7M-Z01 5.5A

V R DCA
CRS MC
LX_CHG CHG

S E RP CA
1
PC112
0.047U_0402_25V7K
BST_CHG

5
@I ME

2
1
C C

111 RP

6- 363 T OS N2 G- WK D2007 N2 E M
1 P OS C
1
1
1
1

1 N OS C
+3VDS <53> SRSET LDO=6V
4/11 PD103

2
2
2
2
2
2

1
%5_6021_7. 4
RB751V-40_SOD323-2

601 QP
2
511 CP
611 CP
711 CP

311 CP
411 CP
201 DP
811 CP

1
I ME @

ILD
NRS
P RS
DN G
@

M
PR113

1
+5VS VIN

V R D OL
22K_0402_1%

11
21
31
41
51
I ME

PC120
@

2
2
3
2
1
1U_0603_25V6K

2
2 GHC_1B NS
CHRG_ADP_DET <32>

I ME

911 CP
@

1
1
1
121 CP
6 V52_2040_ U1. 0
K6 V52_5080_ U01

PR114 PR115

6 V52_2040_ U1. 0
PR116
18.2K_0402_1% 127K_0402_1%
1M_0402_5%

GHC_ L D
2- 323 D OS_03- V155 B R

2
2
2
<53> V_3.9K

GHC_ N RS
GHC_ P RS
CI ot esolc
CI ot esolc
K6 V52_5080_ U01

30V/16A/0.0165 ohm

K7 V05_2040_ U10. 0
K7 V05_2040_ U10. 0

K7 V05_2040_ P0022

1
1
1
PR120

1
10_0402_5%

K7 V05_2040_ P086
PR118 PR119

2
10K_0402_1% 20K_0402_1% noitcennoc nivlek

2
1

321 CP

2
2
221 CP
PR121 PC124
6.8_0402_5% 0.1U_0603_25V7K

2
5- 8 KAP RE WOP_3 E G- 1 T- NDA6177I S
PR122
VIN Vacdet Vchag_adp_det Vvoltage_adc 46.4K_0402_1%

K7 V05_2040_ U10. 0

J 8 V05_2040_ P001
CURRENT_ADC <32>

H 2.58V 2.99V 1.4V

1
1
PC126
B B
0.22U_0402_16V7K

2
2
L 1.07V 0V

521 CP
VIN

J 8 V05_2040_ P001
PR124 PR125
49.9K_0402_1% 576K_0402_1%

VOLTAGE_ADC <32>

1
1
PR126 PC128
49.9K_0402_1% 0.22U_0402_6.3V6K

2
2

721 CP
Ilimit=20*(Vsrp-Vsrn)=20*Ich*Rch

J 8 V05_2040_ P001
up to Ilimit=1.6V(disable)
R=10m ohm I=8A
R=20m ohm I=4A
fs=750k
Iripple=Vin*D(1-D)/(fs*L),
A
D=0.5 (worst) A
Iripple=1.418A
Isat(L)=Ichg+0.5*Iripple=4+0.5*1.418=4.709A
ILIM>1.6V disable
ILIM<75mV disable
ILIM>105mV enable

DLIM>1.1V disable
DLIM<870mV disable
DLIM>896mV enable(buck to boost) Issued Date
default dischager current limit 4.096A

5 4 3 2 1
 5 4 3 2 1

D D

Leave ENTRIP1(2) floating or drive it

above 4.5V to shut down channel 1(2)

+5VDSP
+3VDSP
B+ B++ B++

1
2
1
Vfb=2v

2
1
2
1
1
1

1
1
1
0 1 3 RP
1
2
2
2

2
2
2
5
6 0 3 CP
7 0 3 CP
8 0 3 CP

5 0 3 CP
4 0 3 CP
3 0 3 CP
5V3 _ BF
3
1V5 _ BF

I ME @
I ME @

@
@

2 P4I RT NE
1 P2I RT NE
<8> 3V_PG

%1 _ 2 04 0 _ K6 9 1 8 0 3 RP
%5 _ 3 06 0 _ K8 6
%1 _ 2 04 0 _ K4 7 1 9 0 3 RP
C C

2 BF
1 BF

N OT
K6 V52 _ 5 08 0 _ U0 1
K6 V52 _ 5 08 0 _ U0 1
K7 V0 5 _2 0 4 0_ P00 2 2

K6 V52 _ 5 08 0 _ U0 1
K6 V52 _ 5 08 0 _ U0 1
1
2
3

K7 V0 5 _2 0 4 0_ P00 2 2
3
2
1

Rdc=22m ohm

2 PI RT NE
1 PI RT NE
Rdc=15.5m ohm
8785mA(max)
+3VDSP
+5VDSP

1
5
1

7308mA+1000=8308mA
5

I ME
@
2
I ME

4 1 3 RP
3 0 3 QP
@
2

NI V
MNE
5 1 3 RP

1
5 ODL
3 ODL
+3VLP +3VL

ODL NE

11
21
31
41
51
1

4 0 3 QP

4 7 Z CP
2
1
2
3

%5 _ 60 2 1 _7. 4
PC106

4 1 3 CP
2
5 7 Z CP

%5 _ 60 2 1 _7. 4

0.1U_0402_25V6
5 1 3 CP

1
3
2
1

I ME3 1 3 CP
2 1 3 CP

@
1
1
B++

M_ V3. 6 _ U0 2 2
2
M_ V3. 6 _ U0 2 2

I ME
@

1
2

1
1
Rds(on)=16.5m-13.5 ohm(low side)

2
Ventrip=Ientrp*Rentrip=0.5-2.7V,Ientrp=10uA

M7 1 R_ Y V3. 6 _ 2 D_ U0 5 1
2
2
M7 1 R_ Y V3. 6 _ 2 D_ U0 5 1

B +5VLP +5VL B

2
OVP=3.3*1.16=3.83V(max) Rds(on)=16.5m-13.5 ohm(low side)

K7 V0 5_ 2 0 40 _ P0 8 6
9 1 3 CP
6 1 3 CP
MNE
D=VO/Vin=3.3/19=0.174
K7 V0 5_ 2 0 40 _ P0 8 6

5 2 3 RP
>35<
Ventrip=Ientrp*Rentrip=0.5-2.7V,Ientrp=10uA

4 2 3 RP
I=(Vin-Vo)*ton/L=(Vin-Vo)*DT/L=2.21A
Ilimit=7.3-2.21/2=6.195A settting OCP=8.785*1.2=10.54A
Iocp=6.195*1.2=7.434A Rlimit=(Ron*Ilimit)*10/10u=(13.5m*10.54)*10/10u=143k
1

%1_ 2 0 40 _ K0 0 1
Rlimit=(Ron*Ilimit)*10/10u=(13.5m*7.434)*10/10u=100k OVP=5*1.16=5.8V(max)

5- 8 K A P RE WOP_ 3 E G- 1 T- NDA6 1 77I S

K6 V0 1 _ 20 4 0 _ U1
PL V3 +
2

K7 V52 _ 3 06 0 _ U1. 0
OVP=5*1.16=5.8V(max)
5- 8 K A P RE WOP_ 3 E G- 1 T- NDA6 1 77I S

D=VO/Vin=5/19=0.263
%1_ 2 0 40 _ K0 0 1

I=(Vin-Vo)*ton/L=(Vin-Vo)*DT/L=5.21A
Ilimit=8.785-5.21/2=6.18A
Iocp=6.195*1.2=7.416A
Rlimit=(Ron*Ilimit)*10/10u=(13.5m*7.416)*10/10u=100k

<1>5V=283KHz 3V=330KHz (Vin=6.5 ~ 12v)

<2>5V=321KHz 3V=375KHz (Vin=12 ~ 25v)
(By Rton= 68K ohm)

A A

Issued Date
3VDSP/5VDSP
LA-B181P

5 4 3 2 1
 5 4 3 2 1

B+
D D

1
1
1

2
2
2
+1.35VP

5
+0.675VSP
400mA

1
1

2
2

6R1DD_ XL
R1DD_ HD
7
91
02

R8D1D_T SB
4 MCP
5 MCP

1
2
3
TT V

T OOB

ESA HP
ET A GU
NI ODL V
+1.35VP

1
5
K6 V3. 6_5080_ U01
K6 V3. 6_5080_ U01

6296mA
+5VDS

2
2 MQP
C C

+1.35VP

67 Z CP
1
2
3

1S
1
1
1

6 MCP
+5VDS

BF

5S
3S

2DD_ B N
2
2
2

R
N OT
9
8
7
6
Rds(on)0.0165-0.0135 ohm

M_ V5. 2_ U033
01
D OOGP
Vfb=0.75V

M9 R_ YV2_ XS 2 D_ U022
Vop=1.2*1.35=1.62V
Rilim=limit*Rds(on)/10uA,limit=13300/0.0165*10u=8.06A(min) +1.35VP

RDD_5 S
RDD_3 S
1 RDD_ BF

RDD_ N OT
ton=3.85p*Rton*Vddq/(Vin-0.5)=3.85p*887k*1.35/(19-0.5)=249n
f=Vddq/(Vin*ton)=285.3Khz

5- 8 KAPRE WOP_3 E G- 1 T- NDA6177I S

2

+1.35VP +1.35V_VDDQ
B B

<8,25,32,40,43> SLP_S4#
+0.675VSP +0.675VS

<4,15> SM_PG_CTRL
1
1

2
2

A A

Compal Electronics, Inc.

Issued Date

LA-B181P

5 4 3 2 1
 5 4 3 2 1

D D

SLP_S3# <8,26,32,35,40,41,52>

1
1
2

1
1
1

2
2
2
1
TDC 6A

6 H CP
1
1
1
1
1

4738mA

2
2
2
2
2
2

C C

K6 V5 2_ 50 80 _ U01
1

2
1S
+3VLDO_1.05V

V520. 1_ B N
<41> +1.05V_PGD

1
2
low:6A floating:8A High:12A
OCP:8A

1
fs=800Khz
Ipk=Vo*(1-Vo/Vin,max)/(fs*L)=19*(1-3.3/19)/(800k*1u)=1.24A
Imax=Io,max+Ipk/2=7.64A

2
B B

A A

Issued Date

5 4 3 2 1
 5 4 3 2 1

PRZ5:Vo-usr=1.7*(150/(150+9.53))=1.598V
Vusr=540mV
PRZ11:disable OSR&PT,Rosr=150k
PRZ10:setting fs R=150==>1Mhz
Ramp setting:
PRZ9=100K type:160mV PHZ1 is between PUZ2 and PUZ3
PRZ9>=150K type:40mV
B+

1
D boot voltage setting: D
Vb-ram=1V==>2V

1
1
1
1
1
1
Vb-ram=0V==>1.7V

1
1
1
1
PCZ3

1
Vb-ram>1.525V==>0V 2200P_0402_50V7K

2
2
2
2
2
2

1 Z HP
2
2
Iccmax=32A(15w),Iccmax=40A(28w)

1 Z CP
2 Z RP
2
3 Z RP
2
4 Z RP
2
5 Z RP
2

1
@W51
@W51
IccTDC=10A(15w),IccTDC=16A(28w)
IccDyn=27A(15w),IccDyn=32A(28w)

@W51

1
1
%1_2040_ M1

1
1
1
OCP voatge seeting:

2
1
PRZ8=39K ==>18.9mV

%1_2040_ K093
%1_2040_ K001
%1_2040_ K35. 9
Vimon=1.7V

2040_ K001
2
8 Z RP
2
9 Z RP
2

_P
@W51

K7 V61_2040_ P0074

Z1C

7 Z RP
2
2
2
Rp_n=10.74k Rcs(eff)=0.6m ohm

_1%
01 Z RP
11 Z RP
1.7V=10*(1+Rimon/39k)*0.6m*32,Rimon=345k

ALERT goes low,THERM=1.08V

%1_2040_ K93

%1_2040_ K1. 9
VR_HOT goes low,THERM=1.1V

%1_2040_ K051
%1_2040_ K051
%1_2040_ K051
CPU_B+

K7 V61_2040_ U1.
MAR- B

I- P CO

CR30F401F W51 P CN2

slew rate(15w,150K)=96mV/uS,slew rate(28w,100K)=84mV/uS

9
address selection(15w):1.7*100/(100+150)=0.68V

61
51
41
31
21
11
01
9
address selection(28w):1.7*100/(100+100)=0.85V
C C

I
On-tome(ton):ON-time is fixed based on +VCC_CORE

I- F
VR12.5_VR_ON <11>

N OM

T ABV
the input voltage (at the VBAT pin) +5VS

I- PCO
RS U- O

XA M

MRE HT

A WEL S
P MAR- B
1

Vssense and Vccsense need to

1
be difference pair 1
2

Droop:Error amplifier output.

2

1
1
1

+3VS
71 Z RP @W51

2
1

<13> VSSSENSE VR12.6PG_MCP <11>

2
2

%1_2040_ K3
61 Z CP
71 Z CP

2
2

<11> VCCSENSE

A5 V
DAP

DN G
2 Z HP

KL CV
1

F E RV
K6 V01_2040_ U51. 0
K6 V01_2040_ U51. 0

P MOC

P OORD
52
62
72
82
92
03
13
23
33
1

# T REL A
12 Z RP

# T OH_ RV
PHZ2 is next to PLZ2

2
%5_2040_1
+3VS NTC
B value=3435 K
DCR=0.72m ohm
B B

1
Z R1 D43 F301 A0 MST_ %1_2040_ K01

KL C_ DI VS_ RV

2
# T RL A_ DI VS_ RV
+VCC_CORE

# T OH_ CORP_ CBK

+5VS 40000mA
+5VS +1.05VS_VCCST

1
1
1
1

ALERT between VCLK and VDIO to reduce cross-talk.

2
2
1
@

2
1
1
1

1
@W82

13 Z RP @W82
1 2
2
2

2
2

@W82
%1_2040_ K3

23 Z RP
72 Z CP
82 Z CP

1
2

33 Z RP
43 Z RP
2

<11> VR_SVID_CLK
@W82

%1_2040_9. 45
3 Z HP

%1_2040_ K9. 16
K6 V01_2040_ U51. 0
K6 V01_2040_ U51. 0

<11> VR_SVID_ALRT#
%1_2040_031

<11> VR_SVID_DAT PHZ3 is next to PLZ3

<4> KBC_PROC_HOT#
1

A A
2
Z R1 D43 F301 A0 MST_ %1_2040_ K01

Issued Date

not mount (15w@,28w@)

5 4 3 2 1
 A
B
C
D

2 1 2 1
5
5

2 1 2 1
2 1 2 1
2 1 2 1
4
4

2 1 2 1
2 1 2 1

Issued Date
2 1 2 1

3
3

2 1 2 1
2 1 2 1
2 1 2 1

2
2

3@
7 Z CP
9. 1 H XS M9 RSE 2 D M V2 U051

1
1

A
B
C
D
 A B C D

SLP_S3# <8,26,32,35,40,41,49>

1
2
2
1 1
<41> PGD_1.5V

+1.5VSP +1.5VS

+3VDS
Short@UMA

1
1
3mA

1
1
1

2
OCP:3A

2
2
2

2
Rup
FB=0.6V

1
Vout=0.6V*(1+Rup/Rdown)

1
2
2
Rdown

2 2

SLP_S3# <8,26,32,35,40,41,49>

1
1
2

2
@

1
1
1

2
2
2
1
1

1
1
1
1
1

3 3

2
2
2
2
2
2

6000mA
2

+3VLDO_VRP

1
1

2
1S
2 RV_ B N
2

P
<41> PGD_1.5V

1 2
2
low:6A floating:8A High:12A
OCP:8A

4 4

Issued Date

LA-8551P
A B C D
 A
B
C
D

<32> ADP_ID_CHK

2 1 2 1
5
5

2 1
3 1 2 1
MEMO:PRA4 and PQA5 are not mount

2 1
2 1 2 1 2 1 2 1
4 8
G P
E
B
2
C
4
4

S
G
2
2 1
D
2 1
2 1 2 1
2 1

Issued Date

3
3

2 1 2 1
61 CP
K7 V61_5080_ U22. 0
2 1
2 1 2 1
62 RP
%1_2040_ K4. 71 2 1
2 1
51 CP
K7 V05_2040_ P0001
2 1
2 1

2
2

4 8
G P
1 3
1 2
3 1 2 1
3 1

1
1

A
B
C
D
 4
3
2
1

A
A

2 1
2 1
+1.8 VS_ VGA

2 1
+1.8 VS_ VGA +3VS

PHV2 is next to PLV2

2 1
Vset1=0.11V

@A GV 2 V HP
Z R1524 F 401 B0 MST _ %1 _204 0_ K001
@A GV
%1_20 40_ K23. 7
55 V RP 74 V RP
2 1 2 1 2 1
1 2 1 2 @A GV89 V CP %1_20 40_ K41
Z4 V61_ 2040 _ U74. 0 @A GV 2 1
<34> VG A_V SSS ENSE

+5VS

1 2 1 2 2 1 2 1
<34> GP U_SVT

2 1
2 1
VG A_V CCS ENSE
<34 >

B
B

@A GV @
%1_20 40_ K01
23 V RP
2 1 2 1
@A GV @
Vset2=0.018V
+VGA _CORE

68 V CP
K7 V52_ 3060 _ U22. 0
EC_THERM# <3 4>

@A GV 72 P3M
1OC_ A GV
L_ PC O P MOC
%1 _204 0_ K001 C CV_ A GV 82 21 BF_ A GV
06 V RP CCV BF
2 SAI BI _ A 1GV 92 11
SAI BI NE SV
03 01
A P MOC N3 NESI
13 9
ABF P3 NESI
+5VS

23 P1 NE S
8I _ A GV @A GV @ 53 V RP
A NE SV P1 NESI %1_20 40_ K01
97 V RP 33 N1 NE S
7I _ A GV 2 1
%1_20 40_ K01 P2 A NESI N1 NESI
+5VS

APU_core

@A GV @A GV @ 43 6 @A GV @ 63 V RP
N2 A NESI N2 NESI VG A_ IS EN2 N
%1_20 40_ K01
+5VS

2 %11_2 040_ K1
FSW=300kHz

2 1 53 5 2 1
N1 A NESI P2 NESI VG A_ IS EN2 P
@A GV 08 V RP
201 V CP 63 T E4S N OT _ A GV
6 V52 _204 0_ U1. 0 P1 A NESI TE S NOT
2 1 73 3
NE 3 M WP
83 2
DCR 1.4mohm +/-5%

A D OOGP 2 T OOB VG A_ BO OT2

93 1
Peak Current 46.5A

D OOGP 2 ETA GU VG A_ UGA TE2

TDC 31A(1H1L) *2phase

3 1
<9,3 3> GP U_PG D
GP U_B+

@A GV

C
C

49 V CP
K7 V01 _306 0_ U2. 2
2 1
GP U_B+

K7 V01 _306 0_ U2. 2

2 1
@A GV59 V CP
H/S Rds(on) :11A/15mohm(FDMS7698) ,36A/3.3mohm(MDU1511RH)
+5VS

2 1
2 1 2 1 2 1
3 5 3 5
3 5 2 3 5 2

D
D

2 1 2 1
1 1
1 2 V QP @A GV 1 V QP @A GV
@A GV 2 2 V QP 552-581
- 3V3DNM
F D P_ H R U @A GV 0 2 V QP 52
5-581- V
33DNMF D P_ H R U
5- 8- 65 NF D R E WOP_ H R1 151 U D M 5- 8- 65 NF D R E WOP_ H R1 151 U D M
@A GV @
2 1 2 1 2 1 2 1

Issued Date
701 V CP 07 V RP 21 V CP 9 V RP
K7 V05 _306 0_ P086 %5 _602 1_7. 4 K7 V05 _306 0_ P086 %5 _602 1_7. 4
@A GV @ @A GVI ME @ @A GVI ME @ @A GV
@A G3V
01 V CP 2 V CP
K6 V52_ 5080 _ U01 K6 V52_ 5080 _ U01
2 1 2 1
@A G0V
01 V CP 3 V CP @A GV
K6 V52_ 5080 _ U01 K6 V52_ 5080 _ U01
2 1 2 1

GP U_B+
GP U_B+

@A GV @ @A GV @
801 V CP 79 V CP
2 1 2 1
6 V52 _204 0_ U1. 0 6 V52 _204 0_ U1. 0
@A GVI ME @
2- N1 NE SI _ A GV 1- N1 NE SI _ A GV
19 V CP
6 V52 _204 0_ U1. 0
2 1
4 V CP
K7 V05_ 2040 _ P0 022
2 1
@A GVI ME @

31000mA(TDC)
load line:1m ohm
slew rate:50mV/uS
B+

E
E

LA-B181P
4
3
2
1
 5 4 3 2 1

+VGA_CORE

D D

+VGA_CORE

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
+VGA_CORE

1
1
1
1
1
1
1
1
C C

2
2
2
2
2
2
2
2
+VGA_CORE

1
1
1
1
1
1
1

2
2
2
2
2
2
2
B +VGA_CORE B

1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2

A A

Issued Date

5 4 3 2 1
 5 4 3 2 1

jump

+1.8VGSP +1.8VS_VGA

D <9,54> 1.8V_PWRGD D

1
1
1
1
1
1
1

2
2
2
331mA

2
2

2
2
2
OCP:3A

1S
<35,57> 0.95V_1.8V_VGA_EN

1
V28. 1_ B N

1
2
2
C C

B B

A A

Issued Date

5 4 3 2 1
 5 4 3 2 1

jump
D +0.95VGSP +0.95VS_VGA D

<54> +0.95VS_PWRGD

1
1
1
1
1
1
1
1
1932mA

2
2
2
2

2
2
2

2
OCP:3A

1S
<35,56> 0.95V_1.8V_VGA_EN

V529. 0_ B N

1
C C

2
2
B B

A A

Issued Date

5 4 3 2 1
 5 4 3 2 1

D D

AC
Adapter CPU DC/DC
P.44 RT8243AZQW TPS51622ARSMR 50~51
INPUTS OUTPUTS
B+ VCC_VORE

+3VDS/+5VDS DC/DC SYSTEM DC/DC

+3VLP +3VS/+5VS
EN (+5VS/+3VS) RT8243AZQW 47
INPUTS OUTPUTS
AOZ1331DI B+ 3VDS/5VDS
B+
DC Vin SYSTEM DC/DC
Battery RT8207MZQW 48
P.45 DC/DC DC/DC INPUTS OUTPUTS
+3V_PCH 1.35V_VDDQ
Charger (+5VDS/+3VDS) (+3V_PCH) B+
0.675VS
BQ24736RGRR
AO3413L SYSTEM DC/DC
SY8206DQNC 49
P.46
INPUTS OUTPUTS
B+ 1.05VS
PGOOD P.47 SYSTEM DC/DC
3V_PG SY8003DFC 52
INPUTS OUTPUTS
+1.35V_VDDQ B+ 1.5VS

+0.675VS SYSTEM DC/DC

C Vin DDR RT8880BGQW 54~55 C

SLP_S4# RT8027MZQW DDR_PGD INPUTS OUTPUTS

EN B+ +VGA_CORE
SLP_S3# P.48
SYSTEM DC/DC
+1.05VS SY8003DFC 56
Vin SY8206DQNC INPUTS OUTPUTS
SLP_S3# +1.05V_PGD B+ +1.8VS_VGA
EN
P.49
SYSTEM DC/DC
+1.5VS SY8003DFC 57
+3VS INPUTS OUTPUTS
Vin SY8003DFC B+ +0.95VS_VGA
SLP_S3#
EN
P.52 PGD_1.5V

+VCC_CORE
Vin TPS51622ARSM
VR12.5_VR_ON DC/DC VGATE
VR_ON
(CPU_CORE)
P.50,51
B B

+VGA_CORE
Vin RT8880BGQW
DC/DC VDDC_PWRGD
EN (VGA_CORE)
P.54,55

+1.8VS_VGA
+3VS
Vin SY8003DFC
DC/DC
EN (VGA_RAM)
SLP_S3#
P.56

+0.95VS_VGA
+3VS
Vin SY8003DFC
DC/DC
A EN (VGA_RAM) A
SLP_S3#
P.57

Issued Date

5 4 3 2 1
 5 4 3 2 1

Power ON Sequence

D D

C C

B B

A A

Issued Date

5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List)

Delete
1.PQ307 1.customer request
D 2.charger air line power circuit 2.customer request D

3.change AON7506 to SI7716(PQ106) 3.customer common part

4.change NDS0610 to LBSS84L 4.compal change
5.change AON7506 to SI7716 5.customer common part
20131030 6.change 47U 6.3V to 22U 6.3V (PCH8,PCH9) 6.vender reveiw
7.PR9512 mount

1.10U_0805_25V==>2200p_0402_50V not mount(PC160) 1.EMI feedback

20131031 2.PC107,PR111,PC121,PC305,PR314 2.EMI feedback
PC313,PC308,PR315,PC312,PCH4,PCZ3,PRZ13,PCZ13 3.power vender feedback
PCZ20,PCZ26,PCW1,PCV4,PRV70,PCV107 4.power change fb sense
3.change 147K_0402_1% to 237K_0402_1% (PRV34) 5.for compal module design
change 560P_0402_50V7K to 470P_0402_50V7 (PCV88) 6.current limit design
change 10.7K_0402_1% to 22.6K_0402_1%(PRV47)

C C

change 9.76K_0402_1% to 5.6K_0402_1%(PRV51)

change 15K_0402_1% to 19.1K_0402_1%(PRV55)
change 910K_0402_5% to 20.5K_0402_1%(PRV75)
change 910k_0402_1% to 910_0402_1%(PRV53)
change 3.48K_0402_1% to 3.4K_0402_1%(PRV69)
change 910k_0402_1% to 910_0402_1%(PRV77)
4.remove PR9510,PR9512,PR9514,PR9513
5.remove PC318,PRH10,PRW10,PCW13
6. PRH8,PRW8 not mount
7.22u/0805 6.3V to 22u/0603 6.3V PC1504,PC1501
PC1505,PC1802,PC1803,PC1805,PC1806,PC9502,PC9503,
PC9505,PC9506,PCH9,PCH10,PCH11,PCH8
B B
8.0.22U_0402_6.3V6K to 0.22U_0603_50V7K (PC128)

20131101 1.remove PRW11 1.HW request

20131112 1.not mount PRW7 2.AMD request

2.change 0_0402_1% to 0_0402_5%(PR1502,PR1804,
PR9504,PR9508,PR9511,PR9515)

20131202 1.not mount PRZ36,PRV32 and PCV86 1.PWR request

2.PC128 change 0.22U_0603_25V to 0.22U_0402_6.3V6K 2.PWR request
3.add PD16,PRV43
3. customer request
4.add PRV45,PRV48,PCV99 and PRV50
4.richtek request

A A

Security Classification Compal Secret Data

Issued Date Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sheet of
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List)

add
20131210 PRV78 1K_0402_1% RITCHTEK issue request
D PRV62 5.76K_0402_1% D

PRV64 10K_0402_1%
PRV80 1K_0402_1%
PRV79 10K_0402_1%
PRV52 137K_0402_1%

PRM2 Change 4.7_1206_5% to 0_1206_5%

20131221 PCM7 Change 680P_0603_50V7K to 1000P_0603_50V7K EMI request
PR314 not mount==>mount
PC313 not mount==>mount
PR315 not mount==>mount
PC312 not mount==>mount
PCZ13 not mount==>mount
PRZ13 not mount==>mount
PCZ20 not mount==>mount(28W)
PRZ26 not mount==>mount(28W)
C C

PRV31 Change 10_0402_1% to 1_0402_1% RITCHTEK issue request

20131226 PRV34 Change 127K_0402_1% to 84.5K_0402_1%
PRV47 Change 22.6K_0402_1% to 7.32K_0402_1%
PRV51 Change 5.6K_0402_1% to 12.4K_0402_1%
PRV55 Change 19.1K_0402_1% to 14K_0402_1%
PRV75 Change 20.5K_0402_1% to 2.8K_0402_1%
PRV77 Change 910_0402_1% to 1.3K_0402_1%
PRV53 Change 910_0402_1% to 1.3K_0402_1%
PC128 Change 0.22U_0603_6.3V to 0.22U_0402_6.3V

PRM2 Change 0_1206_5% to 4.7_1206_5%

20140102 PCM7 Change 1000P_0603_50V7K to 680P_0603_50V7K EMI request
PUV1 change RT8880BGQW to RT8880CGQW RITCHTEK request

B PR14,PQ2 and PR13 are not mount. B

20140103 PR11 Change 330_0402_1% to 680_0402_1% Customer request

PRV80 mount==>not mount RITCHTEK issue request

20140106 PRV79 not mount==>mount

20140213 add PC8,PC9 and PC10 EMC request

mount PR111,PC121,PC107 and PC129 EMC request
PC107 2200P_0402_50V7K==>0.022_0402 25V
PC129 0.1U_0402_50V7K==>0.022_0402_25V
20140214
add PC161 2200P_0402_50V7K not mount EMC request

A A

Security Classification Compal Secret Data

Issued Date Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sheet of
5 4 3 2 1
 5 4 3 2 1

ZPL40/50/70 from DB to DB-R LA-B181P REV:0.1 -> 0.2 Modify <2013.11.28.~ 2013.12.03>
Rev. Item Date Impact Page Change Cause Modify Description
0.2 1 11/28 CKT, LAYOUT 6 -Design issue -Change RC222 pin 1 connection from +3VS to +5VS
0.2 2 11/28 CKT, LAYOUT 7 -Follow CHICLET -Move TPM LPC CLK from port 0 to port 1
0.2 3 11/28 CKT 8 -DGPU_PWR_EN voltage level uncorrect issue -Uninstall RC125
0.2 4 11/28 CKT, LAYOUT 9 -DGPU power on sequence -Change RC121 to 100K and add CC127 to timing delay.
0.2 5 11/28 CKT, LAYOUT 18 -Footprint uncorrect issue -Modify UT6 footprint to SC70-5
0.2 6 11/28 CKT, LAYOUT 21 -No used. -Remove CLK_PCI_DEBUG from JMINI1 pin 19
0.2 7 11/28 CKT 23 -Q35 can't turn on issue -Uninstall RL26
0.2 8 11/28 CKT 30 -Follow HP BIOS code request -Uninstall R124
0.2 9 11/28 CKT, LAYOUT 32 -Aviod leakage issue. -Swap Q88 pin 1 and pin 3
0.2 10 11/28 CKT, LAYOUT 32 -Footprint uncorrect issue -Modify C187 footprint to 0402 package
0.2 11 11/28 CKT, LAYOUT 33 -Design issue -Swap GPU PEG RX bus P/N signal and CV1~CV8 change to 0.22u
0.2 12 11/29 CKT, LAYOUT 28 -Current limit -Add R660
0.2 13 11/29 CKT, LAYOUT 30 -Vendor request -U13 pin 6 add external 4.7K PU to +3VS_TPM
D 0.2 14 11/29 CKT 32 -Follow CHICLET -Change R255, R257, and R493 to 10Kohm D

-Delete QC12 and add buffer U20 and U21.

0.2 15 12/02 CKT, LAYOUT 6 -Follow CHICLET QC8.3 net name from HDA_SDOUT_AUDIO change to HDA_SDOUT
0.2 16 12/02 CKT, LAYOUT 32 -Follow CHICLET add R101, R102, R104, R105, R106
1.swap QL2 pin 1 and pin 3
0.2 17 12/02 CKT, LAYOUT 23 -leakage issue and FAR suggest 2.Install RL40
3.Reserve 2 resistor (RL48, RL49) connection QL2.2 to +3VS and +LAN_VDD_3V3.
0.2 18 12/02 CKT, LAYOUT 34 -Follow 2013 RRR -Add D14
0.2 19 12/02 CKT 35 -DGPU power on sequence -Uninstall R5076, R5074
0.2 20 12/03 CKT, LAYOUT 40 -Follow CHICLET -change +1.05VS_MODPHY switch circuit

ZPL40/50/70 from DB-R to SI LA-B181P REV:0.2 -> 0.3 Modify <2013.12.04~ 2013.12.17>
0.3 1 12/04 CKT, LAYOUT 29 -Follow 2013 RRR -update FAN control circuit delete Q4108, R5080 and add U2, C31
0.3 2 12/05 CKT 35 -DGPU power on sequence -C4816 from 0.01u change to 0.022u
0.3 3 12/05 CKT 9 -DGPU power on sequence -Change RC121 to 0ohm and uninstall CC127 (BIOS code control timing)
0.3 4 12/05 CKT 10, 33 -For PCIe Gen2 -change CC89, CC90, CC91, CC92, CC93, CC94, CC95, CC96, CV1, CV2, CV3, CV4, CV5, CV6, CV7, CV8 from 0.22u to 0.1u
0.3 5 12/06 CKT 12 -Follow CHICLET -Change RC174 from 5.11ohm to 0ohm
0.3 6 12/06 CKT 11 -Follow INTEL schematic -Change RC156 from 110ohm to 130ohm install
0.3 7 12/06 CKT, LAYOUT 29 -Platform ID identify -add R82, R86
0.3 8 12/06 CKT, LAYOUT 32 -reserve R136, R137 co-lay with U20, U21
0.3 9 12/06 CKT, LAYOUT 40 -reserve R135 co-lay with Q185
0.3 10 12/09 CKT, LAYOUT 43 -No leakage issue -remove Q57
0.3 11 12/09 CKT 26 -Follow CHICLET -RA36 from 22ohm change to 33ohm
0.3 12 12/09 CKT, LAYOUT 17 -Follow INTEL schematic -Install CD52, CD53, CD54, RD11, RD12, RD19 and re-placement RD7, RD8, RD15
0.3 13 12/09 CKT, LAYOUT 11 -Follow INTEL schematic -Re-placement RC154
0.3 14 12/09 CKT, LAYOUT 12 -Follow INTEL schematic -Add RC183, CC47, RC189, CC75
0.3 15 12/10 CKT, LAYOUT 10 -For WWAN , Touch share USB port -Add R138, R139
0.3 16 12/10 CKT, LAYOUT 4 -Follow CHICLET -Add C32
0.3 17 12/11 CKT, LAYOUT 8 -Follow INTEL schematic -reserve RC330
0.3 18 12/11 CKT, LAYOUT 21 -solve SIM card cann't detect issue -delete R5079 , Q4107 and add C2
0.3 19 12/13 CKT, LAYOUT 9 -Follow Runt -R103 change to test point T184
0.3 20 12/13 CKT 8 -solve DGPU power issue -Install RC125
C C
0.3 21 12/13 CKT, LAYOUT 21 -Follow Runt -Q90 , Q4113 from two single MOS change to daul MOS (Q90)
0.3 22 12/13 CKT, LAYOUT 22 -ODD power issue -Add Q63
0.3 23 12/13 CKT, LAYOUT 23 -LAN power issue -delete JHW1 , RL26
0.3 24 12/13 CKT, LAYOUT 21 -no need -delete R205 , C292
0.3 25 12/13 CKT 25 -For V drop test -C1572 from 100u change to 150u
0.3 26 12/13 CKT, LAYOUT 9 -Hp request -ODD_DA# form GPIO14 change to GPIO3
0.3 27 12/13 CKT, LAYOUT 21 -For GPIO initial status -add R91
0.3 28 12/14 CKT, LAYOUT 12 -solve power ripple -add CC77 , CC78 , CC79
0.3 29 12/16 CKT, LAYOUT 9 -reserve for MPHY sequence -add RC377

ZPL40/50/70 from DB-R to SI LA-B181P REV:0.3 -> 0.4 Modify <2013.12.18~ 2013.12.25>
0.4 1 12/20 CKT 9 -Follow HP request -Install RC272, RC273
0.4 2 12/20 CKT, LAYOUT 15 -Follow Intel PDG -Remove RD26, Install RD21
0.4 3 12/20 CKT, LAYOUT 16 -Follow Intel PDG -Unnstall CD52, CD53, CD54, RD11, RD12, RD19 and re-placement RD7, RD8, RD15
0.4 4 12/20 CKT, LAYOUT 19 -Follow Vendor request -Reserve RG5
0.4 5 12/20 CKT 19 -Follow HP request -Change R82, R86 to 0 ohm
0.4 6 12/20 CKT 20 -Follow Intel PDG -Change RP3 and RP4 to 470 ohm
0.4 7 12/20 CKT 21 -Compal Request -Install R91
0.4 8 12/20 CKT, LAYOUT 22 -Customer modify GPIO table. -Remove Q84, R954. Change JODD1 pin 11 netname to ODD_DA#
0.4 9 12/20 CKT 23 -Prepare leakage issue when S3, S5 -Uninstall RL40, QL2, RL49, RL48 install RL34
0.4 10 12/20 CKT 24 -Vendor Request -Reserve RA40, U4101 pin 37 add RT57 10K PU to +5VS
0.4 11 12/20 CKT 31 -Vendor Request -Remove R1363, R1365, R1367, C421, C423, C414, L31, L32, L34, R1364, R1366, and R1368. Modify CRT pi filter
0.4 12 12/20 CKT, LAYOUT 40 -Follow Compal common design -Modify MPHY Power circuit
-Install C80, C556, C81, C558
0.4 13 12/23 CKT, LAYOUT 30 -Follow RF team request -Reserve C90, C564, C91, C565, C92, C566, C93, C567, C95, C569, C110, C578, C111, C579, C108, C576, C82, C559, C83, C560, C84, C561, C86, C562, C89, C563, C94, C568, C96, C571,
C112, C580, C109, C577, C106, C574, C97, C572, C105, C573, C130, C581, C131, C582, C132, C583, C133, C584, C134, C585, C135, C586, C136, C587, C137, C588, C138, C589
-Install C113, C127
0.4 14 12/24 CKT, LAYOUT -Follow ESD team request -Reserve C114, C115, C116, C121, C123, C124, C128, C129

ZPL40/50/70 from SI to PV-1 LA-B181P REV:0.3 -> 0.4 Modify <2014.02.05~2014.>

0.5 1 02/05 CKT 21 -Double pull hugh -RN3 change to @
0.5 2 02/05 CKT 18, 19 -For LVDS SKU -R163, RG3 change to LVDS@
B B
0.5 3 02/05 CKT 19 -For eDP SKU -R172 change to eDP@
0.5 4 02/05 CKT 19 -For Lid Switch issue -R166, R175 change to 3.3K
0.5 5 02/05 CKT, LAYOUT 22 -For ODD issue -add R448, reserve C151
-1. QA2, QA3 combine to dual mos QA2A, QA2B
2. Q91, Q182 combine to dual mos Q91A, Q91B
0.5 6 02/05 CKT, LAYOUT 3. Q86, Q87 combine to dual mos Q86A, Q86B
4. Q63 change to Q63A, Q63B
5. Q4112, Q4114 combine to dual mos Q4112A, Q4112B
0.5 7 02/10 CKT, LAYOUT 35 -For GPU Power Sequence -add D15 and move R5075, C4819
0.5 8 02/10 CKT, LAYOUT 28 -Follow ESD team request -add C594, C595, C596
0.5 9 02/10 LAYOUT 31 -Move U4101 circuit close to JCRT
0.5 10 02/11 CKT, LAYOUT 40 -SLG59M1470VTR is single source issue -modify U44 circuit
0.5 11 02/12 CKT 33 -Improve VGA_PWRGD signal quality -R5094 from 8.25K change to 0ohm
0.5 12 02/13 CKT, LAYOUT 11, 19 -Follow RF team request -add C139, C140, C421
-1. FPR_OFF from GPIO11 change to GPIO65
2. change JAUDIO1.16 from +3V_PCH to +3VS
3. disconnect EC pin125 and CPU pinAJ5
rename EC pin125 "PCH_PCIE_WAKE#" to "EC_GPIO25" and add R249 pull up to +3VDS
4. RN13 un-install
0.5 13 02/14 CKT, LAYOUT -Follow HP request 5. connector EC pin103 to JMINI1 pin1 (WLAN_WAKE#), JMINI2 pin15 change to NC
6. connector EC pin105 to CPU pinAJ5 (PCH_PCIE_WAKE#)
7. change RN3 pull up power rail from +3VS_WLAN to +3VDS and install RN3
8. add JP4102 between +3VDS and +3V_WWAN

A A

Security Classification Compal Secret Data

Issued Date Title
Deciphered Date
T HIS SH EET OF ENGINEER ING D RAWIN G I S TH E PROPRIET ARY PR OPERT Y OF C OM PAL ELEC TR ON ICS, IN C. AN D C ONT AINS C ON FID ENT IAL
Size Document Number Rev
AND TR ADE SEC RET INF ORMAT ION. T HIS SHEET MAY NOT BE TR ANSF ERED FR OM TH E CU STOD Y OF T HE C OM PETEN T D IVISION OF R&D
DEPAR TM ENT EXCEPT AS AUT HORI ZED BY COMPAL EL ECT RONIC S, INC . NEIT HER TH IS SHEET NOR TH E INF ORMAT ION IT CON TAIN S
MAY BE U SED BY OR DISC LOSED T O ANY T HIRD PART Y WIT HOUT PRI OR WRIT T EN CON SENT OF C OM PAL ELEC TR ON ICS, IN C.
Date: Sheet of
5 4 3 2 1