Dell Latitude E6440

A B C D E
COMPAL CONFIDENTIAL
MODEL NAME : VAL90
1
PCB NO : DA6000WZ010 1
GPIO P/N: 2012.8.1 Rev 2.7
BOM P/N :
X76 of SPI:
SALADO 14 HSW UMA
X7650731L03 HASWELL + LYNX POINT
SA000039A30 (64M W25Q64FVSSIQ)
SA00003K820 (32M W25Q32FVSSIQ) 2013‐07‐04
X7650731L04
SA00006N000 (32M MX25L3273EM2I‐10G)
REV : 1.0 (A00)
2 SA00006N100 (64M MX25L6473EM2I‐10G) @ : Nopop Component 2
CONN@ : Connector Component
SPI@ : For X76 SPI
14UMA
EMC@: EMI/RF/ESD ask to add V
CXDP@ : CPU XDP
PXDP@ : PCH XDP
3 3
4 4
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
Compal Electronics, Inc.
Title
MB PCB THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Part Number Description
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATIC,MB LA-9931P
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
B
DA6000WZ000 PCB 0YG LA-9931P REV0 M/B UMA 6 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 4019MV
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Date: Wednesday, July 17, 2013 Sheet 1 of 62
A B C D E
A B C D E
Block Diagram
Intel DDR3L‐DIMM X2
1
LVDS CONN Dual‐Channel LVDS eDP to LVDS iEDP 2Lane Memory BUS (DDR3L) 1
RTD2136R
HasWell 1333/1600 MHz BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
P13‐14
P28
P27
rPGA CPU
DPB
HDMI CONN 947 Pins
P26
USB2.0[12] Camera Through LVDS Cable

DPC P28
DPD P6‐12
DOCKING Dock VGA
P44 FDI DMI
USB3.0[1]
LANEX2 LANEX4
USB2.0[0] JUSB1
DAI SLG55584AVTR USB P40
USB2.0[0]
USB2.0 [3,6] Power Share P40
SATA2
DOCK LAN
Intel USB3.0[2]
USB2.0[1] JUSB2
(PERN1/USBRN3) Lynx Point USB P41
iVGA
VGA Video Switch BGA USB3.0[5]
CRT CONN TS3V713ELRTGR USB2.0[2] JUSB3 P42
2
P25
695 Pins 2
on IO board
P15‐23 USB3.0[6] USB3.0 Repeater USB3.0[6]
Card Reader PS8713 USB2.0[9]
on IO/B
SD4.0/MMC PCIE2 JUSB4

OZ777FJ2LN
P36 P36
(PERN2/USBRN4)
HD Audio I/F
PCIE
SPI
Intel Clarkville
PCIE7 PCIE6 PCIE3 S‐ATA 0/1/2/3/4/5 6GB/s
I217LM
P33
EXPRESS 1/2 Mini Card 1/2 Mini Card Full Mini Card
SATA1
SATA0
Card Pink Pather WLAN/BT,WiGig WWAN/mSATA
SATA3
W25Q64FV DOCK LAN LAN SWITCH
P39 P37 P37 P38 SATA_TXN4/PETN1 P18 To Docking side PI3L720 P33
USB2.0[10] USB2.0[8] USB2.0[4] USB2.0[5] 64M 4K sector
W25Q32FV RJ45
3 3
P18 P34
Smart Card TDA8034HN USH
32M 4K sector
BCM5882
RFID HDD HDA Codec INT.Speaker

P31
Fingerprint FP_USB USB2.0[7] ALC3226 P30
CONN USH Module P30
CPU XDP Port LPC BUS PCIE4 E‐Module FFS

P7 33MHz P32
LNG3DM P31
SMSC SIO Combo Jack
BC BUS P30
PCH XDP Port
P15
MEC5048
P45
DAI
To Docking side
WiFi ON/OFF SMSC KBC
on SNIFFER board
MEC5075 Discrete TPM
P46 Dig. MIC
DC/DC Interface AT97SC3204
P48
P35
4 Through LVDS Cable 4
LED P24
TP CONN KB CONN
P47 P47
PWM FAN DELL CONFIDENTIAL/PROPRIETARY
P46
PROPRIETARY NOTE:
Title
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
B
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 4019MV
A B C D E
5 4 3 2 1
USB 2.0 USB 3.0

PORT# PORT# DESTINATION
POWER STATES
0 1 Rear Side (JUSB1)
Signal SLP SLP SLP SLP ALWAYS M SUS RUN CLOCKS
State S3# S4# S5# A# PLANE PLANE PLANE PLANE
1 2 Right Side TOP (JUSB2)
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON
D 2 5 Right Side bottom (JUSB3) D
S3 (Suspend to RAM) / M3 LOW HIGH HIGH HIGH ON ON ON OFF OFF

3 3 (PERN1/USBRN3) DOCKING (JDOCK1)
S4 (Suspend to DISK) / M3 LOW LOW HIGH HIGH ON ON OFF OFF OFF
4 WLAN (JMINI2)
S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF
5 WWAN (JMINI1)
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON OFF ON OFF OFF PCH 6 DOCKING (JDOCK1)
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF
7 USH (JUSH1)
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF
8 Pink Pather (JMINI3)
9 6 Left Side (JUSB4)

PM TABLE
10 Express card (JEXP1)
+PWR_SRC +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M
C C
+PWR_SRC_S +1.35V_MEM +3.3V_RUN +1.05V_M +1.05V_M
11 None
+5V_ALW +1.5V_RUN (M-OFF)
power
+3.3V_ALW +0.675V_DDR_VTT
plane 12 CAMERA (JCAM1)
+3.3V_ALW_PCH +VCC_CORE
+3.3V_RTC_LDO +1.05V_RUN
13 LCD Touch
State
PCI EXPRESS DESTINATION SATA DESTINATION
Lane 1 (SATA_TXN4/PETN1) WWAN (JMINI1)SATA by default
SATA 0 HDD (JSATA1)
Lane 2 (SATA_RXN5/PERN2) None
SATA 1 ODD (JSATA2)
S0 ON ON ON ON
ON Lane 2 (PERN2/USBRN4) 10/100/1G LOM SATA 2 Dock (JDOCK1)
S3 ON ON OFF ON OFF
Lane 3 WLAN (JMINI2)
SATA 3 NA
B S5 S4/AC ON OFF OFF ON OFF B
Lane 4 E3 Module Bay (JSATA2) SATA 4 (SATA_TXN4/PETN1) WWAN (JMINI1)
S5 S4/AC don't exist OFF OFF OFF OFF OFF SATA by default
Lane 5 None
Lane 6 Pink Pather (JMINI3)
Lane 7 Express card (JEXP1)
Lane 8 MMI
DISPLAY Ports
Connetion
On CPU
DDIB MB HDMI (JHDMI1)
A
DDIC Dock DP port 1 A
DDID Dock DP port 2

PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
EN_INVPWR FDC654P
D +BL_PWR_SRC D
Q21
BATTERY
MODC_EN
+PWR_SRC
RUN_ON
ADAPTER
TPS22966
(U37)
+5V_RUN
CHARGER
BQ24717 +5V_MOD
C (PU700) ALWON C
TPS51225
+5V_ALW
(PU100) +5V_HDD Pop option
+5V_RUN
0.75V_DDR_VTT_ON
RUN_ON SYN470DBC
+1.5V_RUN
PU400
IMVP_VR_ON
SUS_ON
A_ON
+3.3V_ALW
MCARD_WWAN_PWREN
MCARD_MISC_PWREN
AUX_EN_WOWL
EN_LCDPWR
SIO_SLP_LAN#
ISL95812 RT8207MZQW TPS51212DSCR
RUN_ON
B (PU500) (PU200) (PU300) SUS_ON B
PCH_ALW_ON
A_ON
APL3512 TPS22966 TPS22966 TPS22966 TPS22966

+VCC_CORE +1.35V_MEM +0.675V_DDR_VTT +1.05V_M
(U148) (U57) (U36) (U146) (U145)
RUN_ON
DGPU_PWR_EN#
+3.3V_ALW +3.3V_PCIE +3.3V_PCIE
+LCDVDD +3.3V_WLAN +3.3V_LAN +3.3V_SUS +3.3V_M +3.3V_RUN
_PCH _FLASH _WWAN
SI4164
SI4164 (Q63)
(QV1)
A A
+1.05V_RUN DELL CONFIDENTIAL/PROPRIETARY

+1.35V_MEM_GFX PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
2.2K
SMBUS Address [0x9a]
2.2K
+3.3V_ALW_PCH
R10 MEM_SMBCLK 202
MEM_SMBDATA
2N7002
U11 200 DIMMA SMBUS Address [A0]
2N7002
2.2K
D 202 D
PCH
+3.3V_LAN 200 DIMMB
2.2K SMBUS Address [A4]
U8 LAN_SMBCLK 28
LAN_SMBDATA 31 LOM SMBUS Address [C8]
R7
N11 K6 53
51 XDP1 SMBUS Address [TBD]
2.2K
SML1_SMBDATA
SML1_SMBCLK
+3.3V_ALW_PCH
2.2K 53
51 XDP2
A5 B6 2.2K SMBUS Address [TBD]
SMBUS Address
3A 3A APR_EC: 0x48
2.2K +3.3V_ALW SPR_EC: 0x70 10K
MSLICE_EC: 0x72
B4 DOCK_SMB_CLK 127
1A USB: 0x59
129 AUDIO: 0x34 10K
+3.3V_RUN
1A A3 DOCK_SMB_DAT DOCKING
SLICE_BATTERY: 0x17
SLICE_CHARGER: 0x13 4
G Sensor
@ 2.2K 6 SMBUS Address [0x3B]
C C
+LCD_VDD
@ 2.2K
B5 LCD_SMBCLK
1B
1B A4 LCD_SMDATA
13
2.2K 14 eDP to LVDS CONVERTER SMBUS Address TBD
KBC 2.2K
+3.3V_ALW
100 ohm 7
1C A56 PBAT_SMBCLK
6 BATTERY SMBUS Address [0x16]
1C B59 PBAT_SMBDAT 100 ohm
CONN
2.2K
+3.3V_SUS
2.2K
USH_SMBCLK M9
1E A50
B53 USH_SMBDAT L9 USH SMBUS Address [0xa4]
1E
2.2K
B B
+3.3V_SUS
2.2K
MEC 5075 7
2B A49 CARD_SMBCLK
8 Express card SMBUS Address [TBD]
2B B52 CARD_SMBDAT
2.2K
+3.3V_ALW
2.2K
B50 CHARGER_SMBCLK
1G 9
A47 CHARGER_SMBDAT Charger SMBUS Address [0x12]
1G 8
2.2K
+3.3V_ALW
2.2K
B7 BAY_SMBDAT 29
2D
30 E3 Module Bay
A7 BAY_SMBCLK SMBUS Address [0xd2]
2D
100 2
A 100 3 MBATT A
2A
2A
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
+VCOMP_OUT
PEG_COMP 2 1
D 24.9_0402_1% RC1 D
CAD Note:
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils.
JCPU1A Haswell rPGA EDS
E23 PEG_COMP
PEG_RCOMP M29
D21 PEG_RXN_0 K28
<16> DMI_CRX_PTX_N0 DMI_RXN_0 PEG_RXN_1
C21 M31
B21 L30
A21 M33
<16> DMI_CRX_PTX_N3 DMI_RXN_3 PEG_RXN_4 L32
D20 PEG_RXN_5 M35
<16> DMI_CRX_PTX_P0 DMI_RXP_0 PEG_RXN_6
C20 L34
B20 E29
A20 D28
<16> DMI_CRX_PTX_P3
DMI
DMI_RXP_3 PEG_RXN_9 E31
D18 PEG_RXN_10 D30
<16> DMI_CTX_PRX_N0 DMI_TXN_0 PEG_RXN_11
<16> DMI_CTX_PRX_N1 C17 E35
B17 DMI_TXN_1 PEG_RXN_12 D34
<16> DMI_CTX_PRX_N2 DMI_TXN_2 PEG_RXN_13
<16> DMI_CTX_PRX_N3 A17 E33
DMI_TXN_3 PEG_RXN_14 E32
D17 PEG_RXN_15 L29
<16> DMI_CTX_PRX_P0 DMI_TXP_0 PEG_RXP_0
<16> DMI_CTX_PRX_P1 C18 L28
B18 DMI_TXP_1 PEG_RXP_1 L31
<16> DMI_CTX_PRX_P2 DMI_TXP_2 PEG_RXP_2
C A18 K30 C
<16> DMI_CTX_PRX_P3 DMI_TXP_3 PEG_RXP_3 L33
PEG_RXP_4 K32
PEG_RXP_5 L35
PEG_RXP_6 K34
PEG_RXP_7 F29
PEG_RXP_8
PEG
H29 E28
<16> FDI_CSYNC
FDI
J29 FDI_CSYNC PEG_RXP_9 F31
<16> FDI_INT DISP_INT PEG_RXP_10 E30
PEG_RXP_11 F35
PEG_RXP_12 E34
PEG_RXP_13 F33
PEG_RXP_14 D32
PEG_RXP_15 H35
PEG_TXN_0 H34
PEG_TXN_1 J33
PEG_TXN_2 H32
PEG_TXN_3 J31
PEG_TXN_4 G30
PEG_TXN_5 C33
PEG_TXN_6 B32
PEG_TXN_7 B31
PEG_TXN_8 A30
PEG_TXN_9 B29
PEG_TXN_10 A28
PEG_TXN_11 B27
PEG_TXN_12 A26
PEG_TXN_13 B25
PEG_TXN_14 A24
PEG_TXN_15 J35
PEG_TXP_0 G34
PEG_TXP_1 H33
B PEG_TXP_2 G32 B
PEG_TXP_3 H31
PEG_TXP_4 H30
PEG_TXP_5 B33
PEG_TXP_6 A32
PEG_TXP_7 C31
PEG_TXP_8 B30
PEG_TXP_9 C29
PEG_TXP_10 B28
PEG_TXP_11 C27
PEG_TXP_12 B26
PEG_TXP_13 C25
PEG_TXP_14 B24
PEG_TXP_15
1 OF 9
LOTES_AZIF0012-P002B_HASWELL
CONN@
A A
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
SM_DRAMPWROK with DDR Power Gating Topology
+PCH_VCCDSW3_3 +VCCIO_OUT
1 2 PM_DRAM_PWRGD_A +1.35V_MEM
+PCH_VCCDSW3_3
0.1U_0402_25V6
0.1U_0402_25V6
RC12 100K_0402_5%
EMC@ CC17
EMC@ CC18
1 1
1
1.8K_0402_1%
CC19 @
1 2 +VCCIO_OUT +VCCIO_OUT
RC6
1 2 RUNPWROK_R
@ RC5 100K_0402_5% 0.1U_0402_25V6 2 2
1 2 1.35V_SUS_PWRGD JXDP1
2
5
@ RC9 6.8K_0402_5% 1 2
2 1 RUNPWROK_R 1 XDP_PREQ# 3 GND0 GND1 4 CFG17 CFG17 <10>
P
D <46> RUNPWROK B OBSFN_A0 OBSFN_C0 D
@ RC7 0_0402_5% 4 RUNPWROK_AND 2 1 PM_DRAM_PWRGD_CPU XDP_PRDY# 5 6 CFG16 CFG16 <10>
2 1PM_DRAM_PWRGD_A 2 O @ RC10 0_0402_5% 7 OBSFN_A1 OBSFN_C1 8
<16> PM_DRAM_PWRGD A GND2 GND3
G
@ RC13 0_0402_5% UC1 CFG0 9 10 CFG8
Place near JXDP1 <10> CFG0 OBSDATA_A0 OBSDATA_C0 CFG8 <10>
3.3K_0402_1%
74AHC1G09GW_TSSOP5 CFG1 11 12 CFG9
39_0402_5%
<10> CFG1 CFG9 <10>
3
OBSDATA_A1 OBSDATA_C1
1
@ RC15
13 14
GND4 GND5
RC16
<10> CFG2 CFG2 15 16 CFG10 CFG10 <10>
17 OBSDATA_A2 OBSDATA_C2 18 CFG11
<10> CFG3 OBSDATA_A3 OBSDATA_C3 CFG11 <10>
19 20
XDP_OBS0 21 GND6 GND7 22 CFG19 CFG19 <10>
2
OBSFN_B0 OBSFN_D0
L2N7002WT1G_SC-70-3
XDP_OBS1 23 24 CFG18 CFG18 <10>
1 1
OBSFN_B1 OBSFN_D1
@ QC1
25 26
D CFG4 27 GND8 GND9 28 CFG12
@ QC5 <10> CFG4 OBSDATA_B0 OBSDATA_D0 CFG12 <10>
2 <10> CFG5 CFG5 29 30 CFG13 CFG13 <10>
<46,48> RUN_ON_ENABLE# OBSDATA_B1 OBSDATA_D1
L2N7002WT1G_SC-70-3 G 31 32
CFG6 33 GND10 GND11 34 CFG14
S <10> CFG6 CFG14 <10>
3
RUNPWROK_AND 1 3 PM_DRAM_PWRGD_CPU CFG7 35 OBSDATA_B2 OBSDATA_D2 36 CFG15
S
<10> CFG7 OBSDATA_B3 OBSDATA_D3 CFG15 <10>
RC20 need to close to JCPU1 37 38
H_CPUPWRGD CXDP@ RC20 1 2 1K_0402_1% H_CPUPWRGD_XDP 39 GND12 GND13 40
CXDP@ RC21 1 2 0_0402_5% CFD_PWRBTN#_XDP 41 PWRGOOD/HOOK0 ITPCLK/HOOK4 42
G
<15,16> SIO_PWRBTN#_R
2
43 HOOK1 ITPCLK#/HOOK5 44
2 1 RUNPWROK_R CXDP@ RC22 1 2 0_0402_5% CPU_PWR_DEBUG_R 45 VCC_OBS_AB VCC_OBS_CD 46 XDP_RST#_R 2 1CPU_PLTRST#_R
<13,14,18> DDR_HVREF_RST_PCH <11> CPU_PWR_DEBUG HOOK2 RESET#/HOOK6
@ RC104 0_0402_5% @ RC24 1 2 0_0402_5% SYS_PWROK_XDP 47 48 XDP_DBRESET#CXDP@ RC23 1K_0402_1%
<16,45> SYS_PWROK HOOK3 DBR#/HOOK7
2 1 49 50
<46,51> 1.35V_SUS_PWRGD GND14 GND15
@ RC103 0_0402_5% 1 CXDP@ RC25 1 2 0_0402_5% DDR_XDP_SMBDAT_R1 51 52 XDP_TDO
<13,14,15,18,27,31> DDR_XDP_WAN_SMBDAT SDA TD0
CXDP@ RC26 1 2 0_0402_5% DDR_XDP_SMBCLK_R1 53 54 XDP_TRST#
<13,14,15,18,27,31> DDR_XDP_WAN_SMBCLK SCL TRST#
CC138 55 56 XDP_TDI
Refer CRB 1.5 XDP_TCLK 57 TCK1 TDI 58 XDP_TMS
0.01U_0402_16V7K TCK0 TMS
2 59 60 CFG3_R 1 2 CFG3
GND16 GND17 CXDP@ RC8 1K_0402_1%
SAMTE_BSH-030-01-L-D-A CONN@
1
RC100 @
C 1K_0402_1% C
Refer CRB 1.0
JCPU1B
2
Haswell rPGA EDS
Refer CRB 1.5
+1.05V_RUN CPU_DETECT# AP32 MISC AP3 SM_RCOMP0
DDR3L
+VCCST <45> CPU_DETECT# SKTOCC SM_RCOMP_0 AR3 SM_RCOMP1
Refer CRB 1.5 H_CATERR# AN32 SM_RCOMP_1 AP2 SM_RCOMP2
CATERR SM_RCOMP_2
THERMAL
1 2 H_THERMTRIP# PECI_EC AR27 AN3 DDR3_DRAMRST#_CPU DDR3_DRAMRST#_CPU <13>
<46> PECI_EC PECI SM_DRAMRST
@ RC27 100_0402_1% AK31
RC30 1 2 56_0402_5% H_PROCHOT#_R AM30 FC_AK31 AR29 XDP_PRDY#
<46,54,55,56> H_PROCHOT# PROCHOT PRDY
H_THERMTRIP# @ RC31 1 2 0_0402_5% H_THERMTRIP#_R AM35 AT29 XDP_PREQ#
<46> H_THERMTRIP# THERMTRIP PREQ AM34 XDP_TCLK
TCK AN33 XDP_TMS +3.3V_ALW_PCH
+VCCIO_OUT place RC31 near CPU TMS AM33 XDP_TRST#
H_PM_SYNC AT28 TRST AM31 XDP_TDI_R CXDP@ RC32 1 2 0_0402_5% XDP_TDI 1 2 SYS_PWROK_XDP
JTAG
<16> H_PM_SYNC PM_SYNC TDI
PWR
@ RC33 1 2 0_0402_5% VCCPWRGOOD_0_R AL34 AL33 XDP_TDO_R CXDP@ RC34 1 2 0_0402_5% XDP_TDO @ RC11 1K_0402_1%
<20> H_CPUPWRGD PWRGOOD TDO
1 2 H_CATERR# PM_DRAM_PWRGD_CPU AC10 AP33 XDP_DBRESET#_R @ RC35 2 1 0_0402_5% XDP_DBRESET# XDP_DBRESET# <15,16>
@ RC28 49.9_0402_1% CPU_PLTRST#_R AT26 SM_DRAMPWROK DBR
1 2 H_PROCHOT# PLTRSTIN AR30 XDP_OBS0_R CXDP@ RC36 1 2 0_0402_5% XDP_OBS0
RC29 62_0402_5% BPM_N_0 AN31 XDP_OBS1_R CXDP@ RC37 1 2 0_0402_5% XDP_OBS1
@ RC38 2 1 0_0402_5% CPU_DPLL# G28 BPM_N_1 AN29 XDP_OBS2
<17> CLK_CPU_DPLL# DPLL_REF_CLKN BPM_N_2 PAD~D
CLOCK
@ RC40 2 1 0_0402_5% CPU_DPLL H28 AP31 XDP_OBS3 @ T88
<17> CLK_CPU_DPLL DPLL_REF_CLKP BPM_N_3 PAD~D
@ RC42 2 1 0_0402_5% CPU_SSC_DPLL# F27 AP30 XDP_OBS4 @ T89
<17> CLK_CPU_SSC_DPLL# SSC_DPLL_REF_CLKN BPM_N_4 PAD~D
@ RC44 2 1 0_0402_5% CPU_SSC_DPLL E27 AN28 XDP_OBS5 @ T90
<17> CLK_CPU_SSC_DPLL SSC_DPLL_REF_CLKP BPM_N_5 PAD~D
@ RC46 2 1 0_0402_5% CPU_DMI# D26 AP29 XDP_OBS6 @ T116
<17> CLK_CPU_DMI# BCLKN BPM_N_6 PAD~D
@ RC48 2 1 0_0402_5% CPU_DMI E26 AP28 XDP_OBS7 @ T117
Refer CRB 1.5 <17> CLK_CPU_DMI BCLKP BPM_N_7 PAD~D
@ T118
+1.05V_RUN +VCCST 2 OF 9
2 1 CONN@
22U_0805_6.3V6M
22U_0805_6.3V6M
B @ RC99 0_0603_5% B
1 1
@ CC47
@ CC48
2 2 PU/PD for JTAG signals
XDP_DBRESET# XDP_RST#_R H_THERMTRIP#_R +3.3V_RUN
1
EMC@ 1 1 XDP_DBRESET# RC52 2 1 1K_0402_1%
@
C1553 EMC@
0.1U_0402_25V6 C1567 C1566
2 0.047U_0402_16V4Z 0.047U_0402_16V4Z +1.05V_RUN
close CPU 2 2
XDP_TMS @ RC53 2 1 51_0402_1%
VCCPWRGOOD_0_R XDP_TDI @ RC54 2 1 51_0402_1%

ESD Request
10K_0402_5%
XDP_PREQ# @ RC55 2 1 51_0402_1%
Buffered reset to CPU
1
+3.3V_RUN
RC56
XDP_TDO CXDP@ RC57 2 1 51_0402_1%
+1.05V_RUN DDR3 COMPENSATION SIGNALS
0.1U_0402_25V6
2
1
1K_0402_1%
@ SM_RCOMP0 RC58 1 2 100_0402_1% XDP_TCLK RC59 2 1 51_0402_1%

CC21
RC60
SM_RCOMP1 RC61 1 2 75_0402_1% XDP_TRST# RC62 2 1 51_0402_1%

2
UC2 @ @ SM_RCOMP2 RC63 1 2 100_0402_1%
CAD Note:
2
1 5
2 NC VCC Avoid stub in the PWRGD path
A <15,16> PCH_PLTRST#
3 A 4 PCH_PLTRST#_BUF 1 2 CPU_PLTRST#_R
CAD Note: A
GND Y @ RC64 43_0402_5%
while placing resistors RC33 & RC56 Trace width=12~15 mil, Spcing=20 mils
SN74LVC1G07DCKR_SC70-5~D
2 1 Max trace length= 500 mil
<20> CPU_PLTRST#
20K_0402_5%
@ RC66 0_0402_5%
@
1
RC67
PROPRIETARY NOTE:
Title
2
CAD Note: TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATIC,MB LA-9931P

PLACE PULL‐UP RESISTOR WITHIN 2 INCH OF THE CPU BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
B
5 4 3 2 1
5 4 3 2 1
D D
JCPU1C Haswell rPGA EDS
<13> DDR_A_D[0..63]
DDR_A_D0 AR15 AC7 @ T2 PAD~D JCPU1D Haswell rPGA EDS
SA_DQ_0 RSVD <14> DDR_B_D[0..63]
DDR_A_D1 AT14 U4 M_CLK_DDR#0
SA_DQ_1 SA_CKN0 M_CLK_DDR#0 <13>
DDR_A_D2 AM14 V4 M_CLK_DDR0 DDR_B_D0 AR18 AG8 @ T3 PAD~D
SA_DQ_2 SA_CKP0 M_CLK_DDR0 <13> SB_DQ_0 RSVD
DDR_A_D3 AN14 AD9 DDR_CKE0_DIMMA DDR_B_D1 AT18 Y4 M_CLK_DDR#2
SA_DQ_3 SA_CKE_0 DDR_CKE0_DIMMA <13> SB_DQ_1 SB_CKN0 M_CLK_DDR#2 <14>
DDR_A_D4 AT15 U3 M_CLK_DDR#1 DDR_B_D2 AM17 AA4 M_CLK_DDR2
SA_DQ_4 SA_CKN1 M_CLK_DDR#1 <13> SB_DQ_2 SB_CKP0 M_CLK_DDR2 <14>
DDR_A_D5 AR14 V3 M_CLK_DDR1 DDR_B_D3 AM18 AF10 DDR_CKE2_DIMMB
SA_DQ_5 SA_CKP1 M_CLK_DDR1 <13> SB_DQ_3 SB_CKE_0 DDR_CKE2_DIMMB <14>
DDR_A_D6 AN15 AC9 DDR_CKE1_DIMMA DDR_B_D4 AR17 Y3 M_CLK_DDR#3
SA_DQ_6 SA_CKE_1 DDR_CKE1_DIMMA <13> SB_DQ_4 SB_CKN1 M_CLK_DDR#3 <14>
DDR_A_D7 AM15 U2 DDR_B_D5 AT17 AA3 M_CLK_DDR3
SA_DQ_7 SA_CKN2 SB_DQ_5 SB_CKP1 M_CLK_DDR3 <14>
DDR_A_D8 AM9 V2 DDR_B_D6 AN17 AG10 DDR_CKE3_DIMMB
SA_DQ_8 SA_CKP2 SB_DQ_6 SB_CKE_1 DDR_CKE3_DIMMB <14>
DDR_A_D9 AN9 AD8 DDR_B_D7 AN18 Y2
DDR_A_D10 AM8 SA_DQ_9 SA_CKE_2 U1 DDR_B_D8 AT12 SB_DQ_7 SB_CKN2 AA2
DDR_A_D11 AN8 SA_DQ_10 SA_CKN3 V1 DDR_B_D9 AR12 SB_DQ_8 SB_CKP2 AG9
DDR_A_D12 AR9 SA_DQ_11 SA_CKP3 AC8 DDR_B_D10 AN12 SB_DQ_9 SB_CKE_2 Y1
DDR_A_D13 AT9 SA_DQ_12 SA_CKE_3 DDR_B_D11 AM11 SB_DQ_10 SB_CKN3 AA1
DDR_A_D14 AR8 SA_DQ_13 M7 DDR_CS0_DIMMA# DDR_B_D12 AT11 SB_DQ_11 SB_CKP3 AF9
SA_DQ_14 SA_CS_N_0 DDR_CS0_DIMMA# <13> SB_DQ_12 SB_CKE_3
DDR_A_D15 AT8 L9 DDR_CS1_DIMMA# DDR_B_D13 AR11
SA_DQ_15 SA_CS_N_1 DDR_CS1_DIMMA# <13> SB_DQ_13
DDR_A_D16 AJ9 M9 DDR_B_D14 AM12 P4 DDR_CS2_DIMMB#
SA_DQ_16 SA_CS_N_2 SB_DQ_14 SB_CS_N_0 DDR_CS2_DIMMB# <14>
DDR_A_D17 AK9 M10 DDR_B_D15 AN11 R2 DDR_CS3_DIMMB#
SA_DQ_17 SA_CS_N_3 SB_DQ_15 SB_CS_N_1 DDR_CS3_DIMMB# <14>
DDR_A_D18 AJ6 M8 M_ODT0 DDR_B_D16 AR5 P3
SA_DQ_18 SA_ODT_0 M_ODT0 <13> SB_DQ_16 SB_CS_N_2
DDR_A_D19 AK6 L7 M_ODT1 DDR_B_D17 AR6 P1
SA_DQ_19 SA_ODT_1 M_ODT1 <13> SB_DQ_17 SB_CS_N_3
DDR_A_D20 AJ10 L8 DDR_B_D18 AM5
DDR_A_D21 AK10 SA_DQ_20 SA_ODT_2 L10 DDR_B_D19 AM6 SB_DQ_18 R4 M_ODT2
SA_DQ_21 SA_ODT_3 SB_DQ_19 SB_ODT_0 M_ODT2 <14>
DDR_A_D22 AJ7 V5 DDR_A_BS0 DDR_B_D20 AT5 R3 M_ODT3
SA_DQ_22 SA_BS_0 DDR_A_BS0 <13> SB_DQ_20 SB_ODT_1 M_ODT3 <14>
DDR_A_D23 AK7 U5 DDR_A_BS1 DDR_B_D21 AT6 R1
SA_DQ_23 SA_BS_1 DDR_A_BS1 <13> SB_DQ_21 SB_ODT_2
DDR_A_D24 AF4 AD1 DDR_A_BS2 DDR_B_D22 AN5 P2
SA_DQ_24 SA_BS_2 DDR_A_BS2 <13> SB_DQ_22 SB_ODT_3
DDR_A_D25 AF5 DDR_B_D23 AN6 R7 DDR_B_BS0
SA_DQ_25 SB_DQ_23 SB_BS_0 DDR_B_BS0 <14>
DDR_A_D26 AF1 V10 DDR_B_D24 AJ4 P8 DDR_B_BS1
SA_DQ_26 VSS SB_DQ_24 SB_BS_1 DDR_B_BS1 <14>
DDR_A_D27 AF2 U6 DDR_A_RAS# DDR_B_D25 AK4 AA9 DDR_B_BS2
C SA_DQ_27 SA_RAS DDR_A_RAS# <13> SB_DQ_25 SB_BS_2 DDR_B_BS2 <14> C
DDR_A_D28 AG4 U7 DDR_A_WE# DDR_B_D26 AJ1
SA_DQ_28 SA_WE DDR_A_WE# <13> SB_DQ_26
DDR_A_D29 AG5 U8 DDR_A_CAS# DDR_B_D27 AJ2 R10
SA_DQ_29 SA_CAS DDR_A_CAS# <13> SB_DQ_27 VSS
DDR_A_D30 AG1 DDR_B_D28 AM1 R6 DDR_B_RAS#
SA_DQ_30 DDR_A_MA[0..15] <13> SB_DQ_28 SB_RAS DDR_B_RAS# <14>
DDR_A_D31 AG2 V8 DDR_A_MA0 DDR_B_D29 AN1 P6 DDR_B_WE#
SA_DQ_31 SA_MA_0 SB_DQ_29 SB_WE DDR_B_WE# <14>
DDR_A_D32 J1 AC6 DDR_A_MA1 DDR_B_D30 AK2 P7 DDR_B_CAS#
SA_DQ_32 SA_MA_1 SB_DQ_30 SB_CAS DDR_B_CAS# <14>
DDR_A_D33 J2 V9 DDR_A_MA2 DDR_B_D31 AK1
SA_DQ_33 SA_MA_2 SB_DQ_31 DDR_B_MA[0..15] <14>
DDR_A_D34 J5 U9 DDR_A_MA3 DDR_B_D32 L2 R8 DDR_B_MA0
DDR_A_D35 H5 SA_DQ_34 SA_MA_3 AC5 DDR_A_MA4 DDR_B_D33 M2 SB_DQ_32 SB_MA_0 Y5 DDR_B_MA1
DDR_A_D36 H2 SA_DQ_35 SA_MA_4 AC4 DDR_A_MA5 DDR_B_D34 L4 SB_DQ_33 SB_MA_1 Y10 DDR_B_MA2
DDR_A_D37 H1 SA_DQ_36 SA_MA_5 AD6 DDR_A_MA6 DDR_B_D35 M4 SB_DQ_34 SB_MA_2 AA5 DDR_B_MA3
DDR_A_D38 J4 SA_DQ_37 SA_MA_6 AC3 DDR_A_MA7 DDR_B_D36 L1 SB_DQ_35 SB_MA_3 Y7 DDR_B_MA4
DDR_A_D39 H4 SA_DQ_38 SA_MA_7 AD5 DDR_A_MA8 DDR_B_D37 M1 SB_DQ_36 SB_MA_4 AA6 DDR_B_MA5
DDR_A_D40 F2 SA_DQ_39 SA_MA_8 AC2 DDR_A_MA9 DDR_B_D38 L5 SB_DQ_37 SB_MA_5 Y6 DDR_B_MA6
DDR_A_D41 F1 SA_DQ_40 SA_MA_9 V6 DDR_A_MA10 DDR_B_D39 M5 SB_DQ_38 SB_MA_6 AA7 DDR_B_MA7
DDR_A_D42 D2 SA_DQ_41 SA_MA_10 AC1 DDR_A_MA11 DDR_B_D40 G7 SB_DQ_39 SB_MA_7 Y8 DDR_B_MA8
DDR_A_D43 D3 SA_DQ_42 SA_MA_11 AD4 DDR_A_MA12 DDR_B_D41 J8 SB_DQ_40 SB_MA_8 AA10 DDR_B_MA9
DDR_A_D44 D1 SA_DQ_43 SA_MA_12 V7 DDR_A_MA13 DDR_B_D42 G8 SB_DQ_41 SB_MA_9 R9 DDR_B_MA10
DDR_A_D45 F3 SA_DQ_44 SA_MA_13 AD3 DDR_A_MA14 DDR_B_D43 G9 SB_DQ_42 SB_MA_10 Y9 DDR_B_MA11
DDR_A_D46 C3 SA_DQ_45 SA_MA_14 AD2 DDR_A_MA15 DDR_B_D44 J7 SB_DQ_43 SB_MA_11 AF7 DDR_B_MA12
DDR_A_D47 B3 SA_DQ_46 SA_MA_15 DDR_B_D45 J9 SB_DQ_44 SB_MA_12 P9 DDR_B_MA13
DDR_A_D48 B5 SA_DQ_47 DDR_B_D46 G10 SB_DQ_45 SB_MA_13 AA8 DDR_B_MA14
SA_DQ_48 DDR_A_DQS#[0..7] <13> SB_DQ_46 SB_MA_14
DDR_A_D49 E6 AP15 DDR_A_DQS#0 DDR_B_D47 J10 AG7 DDR_B_MA15
DDR_A_D50 A5 SA_DQ_49 SA_DQS_N_0 AP8 DDR_A_DQS#1 DDR_B_D48 A8 SB_DQ_47 SB_MA_15
DDR_A_D51 D6 SA_DQ_50 SA_DQS_N_1 AJ8 DDR_A_DQS#2 DDR_B_D49 B8 SB_DQ_48
SA_DQ_51 SA_DQS_N_2 SB_DQ_49 DDR_B_DQS#[0..7] <14>
DDR_A_D52 D5 AF3 DDR_A_DQS#3 DDR_B_D50 A9 AP18 DDR_B_DQS#0
DDR_A_D53 E5 SA_DQ_52 SA_DQS_N_3 J3 DDR_A_DQS#4 DDR_B_D51 B9 SB_DQ_50 SB_DQS_N_0 AP11 DDR_B_DQS#1
DDR_A_D54 B6 SA_DQ_53 SA_DQS_N_4 E2 DDR_A_DQS#5 DDR_B_D52 D8 SB_DQ_51 SB_DQS_N_1 AP5 DDR_B_DQS#2
DDR_A_D55 A6 SA_DQ_54 SA_DQS_N_5 C5 DDR_A_DQS#6 DDR_B_D53 E8 SB_DQ_52 SB_DQS_N_2 AJ3 DDR_B_DQS#3
DDR_A_D56 E12 SA_DQ_55 SA_DQS_N_6 C11 DDR_A_DQS#7 DDR_B_D54 D9 SB_DQ_53 SB_DQS_N_3 L3 DDR_B_DQS#4
SA_DQ_56 SA_DQS_N_7 DDR_A_DQS[0..7] <13> SB_DQ_54 SB_DQS_N_4
DDR_A_D57 D12 AP14 DDR_A_DQS0 DDR_B_D55 E9 H9 DDR_B_DQS#5
DDR_A_D58 B11 SA_DQ_57 SA_DQS_P_0 AP9 DDR_A_DQS1 DDR_B_D56 E15 SB_DQ_55 SB_DQS_N_5 C8 DDR_B_DQS#6
DDR_A_D59 A11 SA_DQ_58 SA_DQS_P_1 AK8 DDR_A_DQS2 DDR_B_D57 D15 SB_DQ_56 SB_DQS_N_6 C14 DDR_B_DQS#7
B SA_DQ_59 SA_DQS_P_2 SB_DQ_57 SB_DQS_N_7 DDR_B_DQS[0..7] <14> B
DDR_A_D60 E11 AG3 DDR_A_DQS3 DDR_B_D58 A15 AP17 DDR_B_DQS0
DDR_A_D61 D11 SA_DQ_60 SA_DQS_P_3 H3 DDR_A_DQS4 DDR_B_D59 B15 SB_DQ_58 SB_DQS_P_0 AP12 DDR_B_DQS1
DDR_A_D62 B12 SA_DQ_61 SA_DQS_P_4 E3 DDR_A_DQS5 DDR_B_D60 E14 SB_DQ_59 SB_DQS_P_1 AP6 DDR_B_DQS2
DDR_A_D63 A12 SA_DQ_62 SA_DQS_P_5 C6 DDR_A_DQS6 DDR_B_D61 D14 SB_DQ_60 SB_DQS_P_2 AK3 DDR_B_DQS3
AM3 SA_DQ_63 SA_DQS_P_6 C12 DDR_A_DQS7 DDR_B_D62 A14 SB_DQ_61 SB_DQS_P_3 M3 DDR_B_DQS4
+SM_VREF SM_VREF SA_DQS_P_7 SB_DQ_62 SB_DQS_P_4
+SA_DIMM_VREFDQ F16 DDR_B_D63 B14 H8 DDR_B_DQS5
F13 SA_DIMM_VREFDQ SB_DQ_63 SB_DQS_P_5 C9 DDR_B_DQS6
+SB_DIMM_VREFDQ SB_DIMM_VREFDQ SB_DQS_P_6 C15 DDR_B_DQS7
SB_DQS_P_7
3 OF 9 4 OF 9
LOTES_AZIF0012-P002B_HASWELL LOTES_AZIF0012-P002B_HASWELL
CONN@ CONN@
A A
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
D D
COMPENSATION PU FOR eDP
+VCOMP_OUT
EDP_COMP 2 1
24.9_0402_1% RC73
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
JCPU1H Haswell rPGA EDS
T28 M27
<26> TMDSB_CPU_N2 DDIB_TXN0 EDP_AUXN EDP_CPU_AUX# <27>
U28 N27
<26> TMDSB_CPU_P2 DDIB_TXP0 EDP_AUXP EDP_CPU_AUX <27>
T30 P27 EDP_HPD#
C <26> TMDSB_CPU_N1 U30 DDIB_TXN1 EDP_HPD E24 EDP_COMP C
<26> TMDSB_CPU_P1 U29 DDIB_TXP1 EDP_RCOMP R27
<26> TMDSB_CPU_N0 V29 DDIB_TXN2 EDP_DISP_UTIL PAD~D T4 @
<26> TMDSB_CPU_P0 U31 DDIB_TXP2
<26> TMDSB_CPU_CLK# V31 DDIB_TXN3 eDP
<26> TMDSB_CPU_CLK DDIB_TXP3 P35
T34 EDP_TXN_0 R35 EDP_CPU_LANE_N0 <27>
<44> DPC_CPU_LANE_N0 DDIC_TXN0 EDP_TXP_0 EDP_CPU_LANE_P0 <27>
U34 N34
<44> DPC_CPU_LANE_P0 DDIC_TXP0 EDP_TXN_1 EDP_CPU_LANE_N1 <27>
U35 P34
<44> DPC_CPU_LANE_N1 DDIC_TXN1 EDP_TXP_1 EDP_CPU_LANE_P1 <27>
V35 P33
<44> DPC_CPU_LANE_P1 DDIC_TXP1 DDI FDI_TXN_0 FDI_CTX_PRX_N0 <16>
U32 R33
<44> DPC_CPU_LANE_N2 DDIC_TXN2 FDI_TXP_0 FDI_CTX_PRX_P0 <16>
T32 N32
<44> DPC_CPU_LANE_P2 DDIC_TXP2 FDI_TXN_1 FDI_CTX_PRX_N1 <16>
U33 P32
<44> DPC_CPU_LANE_N3 DDIC_TXN3 FDI_TXP_1 FDI_CTX_PRX_P1 <16>
V33
<44> DPC_CPU_LANE_P3 DDIC_TXP3
P29
<44> DPD_CPU_LANE_N0 DDID_TXN0
R29
<44> DPD_CPU_LANE_P0 DDID_TXP0
N28
P28
<44> DPD_CPU_LANE_P1
P31 DDID_TXP1 Question:
R31 JCPU1H.P27 pinout is EDP_HPD. is it high active when Plug in eDP device?
N30
P30
8 OF 9
+VCCIO_OUT
10K_0402_5%
2
CONN@
RC74
HPD INVERSION FOR EDP
B B
1
EDP_HPD#
1
D
2 QC3
<27> CPU_EDP_HPD
G L2N7002WT1G_SC-70-3
S
3
100K_0402_5%
1
RC75
2
QC3 change PN to SB50138003L S TR BSS138-7-F 1N SOT23-3
A A
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
CFG STRAPS for CPU
CFG2
1K_0402_1%
1
@ RC76
D D
2
PEG Static Lane Reversal ‐ CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
CFG2 definition matches socket pin map definition
0:Lane Reversed
JCPU1I Haswell rPGA EDS
CFG4
@ T11 PAD~D AT1
@ T5 PAD~D AT2 RSVD_TP C23 PAD~D T12 @
1K_0402_1%
RSVD_TP RSVD_TP
1
@ T6 PAD~D AD10 B23 PAD~D T7 @
RSVD RSVD_TP
RC77
D24 PAD~D T13 @
@ T8 PAD~D A34 RSVD_TP D23 PAD~D T14 @
@ T9 PAD~D A35 RSVD_TP RSVD_TP
RSVD_TP
2
@ T10 PAD~D W29
@ T15 PAD~D W28 RSVD_TP AT31 CFG_RCOMP
H_CPU_RSVD G26 RSVD_TP CFG_RCOMP AR21 CFG16
TESTLO_G26 CFG_16 CFG16 <7>
W33 AR23 CFG18
VSS CFG_18 CFG18 <7>
@ T16 PAD~D AL30 AP21 CFG17
RSVD CFG_17 CFG17 <7>
@ T17 PAD~D AL29 AP23 CFG19
C
+VCC_CORE F25 RSVD CFG_19 CFG19 <7> Display Port Presence Strap C
VCC
@ T18 PAD~D C35 AR33 PAD~D T19 @
@ T20 PAD~D B35 RSVD_TP RSVD G6 FC_G6 1 : Disabled; No Physical Display Port
RSVD_TP FC_G6 AM27 PAD~D T22 @
@ T23 PAD~D AL25 RSVD AM26 PAD~D T24 @ CFG4 attached to Embedded Display Port
RSVD_TP RSVD F5 PAD~D T25 @
@ T26 PAD~D W30 RSVD AM2 PAD~D T27 @ 0 : Enabled; An external Display Port device is
@ T28 PAD~D W31 RSVD_TP RSVD K6 PAD~D T29 @
H_CPU_TESTLO W34 RSVD_TP RSVD connected to the Embedded Display Port
TESTLO_W34 E18 PAD~D T30 @
CFG0 AT20 RSVD
<7> CFG0 CFG_0
CFG1 AR20 U10 PAD~D T31 @ CFG6
<7> CFG1 CFG_1 RSVD
CFG2 AP20 P10 PAD~D T32 @
<7> CFG2 CFG_2 RSVD
CFG3 AP22 CFG5
<7> CFG3 CFG_3
CFG4 AT22 B1
1K_0402_1%
<7> CFG4 CFG_4 NC
1
1K_0402_1%
CFG5 AN22 A2 PAD~D T33 @
<7> CFG5 CFG_5 RSVD
@ RC78
@ RC79
CFG6 AT25 AR1 PAD~D T34 @
<7> CFG6 CFG_6 RSVD_TP
CFG7 AN23
<7> CFG7 CFG_7
CFG8 AR24 E21 PAD~D T35 @
<7> CFG8 CFG_8 RSVD_TP
CFG9 AT23 E20 PAD~D T36 @
<7> CFG9
2
CFG10 AN20 CFG_9 RSVD_TP
<7> CFG10 CFG_10
CFG11 AP24 AP27
<7> CFG11 CFG_11 VSS
CFG12 AP26 AR26
CFG13 AN25
<7> CFG13 CFG_13
CFG14 AN26 AL31
CFG15 AP25 AL32
PCIE Port Bifurcation Straps
9 OF 9 Refer 1.2 CRB
2 1 H_CPU_TESTLO 11: (Default) x16 ‐ Device 1 functions 1 and 2 disabled
RC80 49.9_0402_1% LOTES_AZIF0012-P002B_HASWELL
B 2 1 CFG_RCOMP CONN@ 10: x8, x8 ‐ Device 1 function 1 enabled ; function 2 B
RC81 49.9_0402_1%
2 1 H_CPU_RSVD CFG[6:5] disabled
RC82 49.9_0402_1% 01: Reserved ‐ (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 ‐ Device 1 functions 1 and 2 enabled
CFG7
1
1K_0402_1%
@ RC83
2
Note: Reserve this circuit
for future compatibility
RESET_OUT# <15,16,46>
PEG DEFER TRAINING
1
@ RC69
6.04K_0402_1% 1: (Default) PEG Train immediately
CFG7 following xxRESETB de assertion
2
FC_G6 0: PEG Wait for BIOS for training
A A
1
@ RC68
2.67K_0402_1%
2
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
+VCC_CORE
JCPU1E Haswell rPGA EDS
AA26
VCC AA28
@ T39 PAD~D K27 VCC AA34
@ T40 PAD~D L27 RSVD VCC AA30
@ T41 PAD~D T27 RSVD VCC AA32
@ T42 PAD~D V27 RSVD VCC AB26
RSVD VCC AB29
D D
+1.35V_MEM VCC AB25
VCC AB27
VCC AB28
AB11 VCC AB30
AB2 VDDQ VCC AB31
AB5 VDDQ VCC AB33
AB8 VDDQ VCC AB34
AE11 VDDQ VCC AB32
AE2 VDDQ VCC AC26
AE5 VDDQ VCC AB35
AE8 VDDQ VCC AC28
AH11 VDDQ VCC AD25
K11 VDDQ VCC AC30
N11 VDDQ VCC AD28
N8 VDDQ VCC AC32
T11 VDDQ VCC AD31
T2 VDDQ VCC AC34
T5 VDDQ VCC AD34
T8 VDDQ VCC AD26
W11 VDDQ VCC AD27
W2 VDDQ VCC AD29
W5 VDDQ VCC AD30
W8 VDDQ VCC AD32
VDDQ VCC AD33
@ T43 PAD~D N26 VCC AD35
K26 RSVD VCC AE26
+VCC_CORE VCC VCC
AL27 AE32
@ T44 PAD~D AK27 RSVD VCC AE28
+1.05V_RUN @ T45 PAD~D RSVD VCC AE30
VCC AG28
VCC AG34
+VCCIO_OUT max. current VCC
150_0402_1%
AE34
VCC
1
is 300mA, 20mil AF25
VCC
RC85
AF26
C +1.05V_RUN +VCCIO_OUT VCCSENSE_R AL35 VCC AF27 C
@ T46 PAD~D E17 VCC_SENSE VCC AF28
AN35 RSVD VCC AF29
+VCCIO_OUT
2
2 1 A23 VCCIO_OUT VCC AF30
+VCCIO2PCH_R FC_A23 VCC
@ RC86 0_0603_5% +VCOMP_OUT F22 AF31
CPU_PWR_DEBUG W32 VCOMP_OUT VCC AF32
@ T48 PAD~D AL16 RSVD VCC AF33
RSVD VCC
10K_0402_5%
RESISTOR STUFFING OPTIONS ARE @ T49 PAD~D J27 AF34
RSVD VCC
1
@ T50 PAD~D AL13 AF35
PROVIDED FOR TESTING PURPOSES RSVD VCC
@
@ T51 PAD~D AG26
VCC
RC89
AH26
H_CPU_SVIDALRT# AM28 VCC AH29
VIDSCLK AM29 VIDALERT VCC AG30
<54> VIDSCLK
2
VIDSOUT AL28 VIDSCLK VCC AG32
VIDSOUT VCC AH32
+VCCIO_OUT AP35 VCC AH35
SVID ALERT <7> CPU_PWR_DEBUG
H27
AP34
VSS
PWR_DEBUG
VSS
VCC
VCC
VCC
AH25
AH27
75_0402_1%
AT35 AH28
RSVD_TP VCC
1
@ T52 PAD~D AR35 AH30

RSVD_TP VCC
RC87
@ T53 PAD~D AR32 AH31

CAD Note: Place the PU resistors close to CPU @ T54 PAD~D AL26 RSVD_TP VCC AH33
RC87 close to CPU 300 ‐ 1500mils +1.05V_RUN +VCCIO2PCH +VCCIO2PCH_R @ T55 PAD~D AT34 RSVD_TP VCC AH34
AL22 VSS VCC AJ25
2
AT33 VSS VCC AJ26

2 1 H_CPU_SVIDALRT# 2 1 2 1 AM21 VSS VCC AJ27
<54> VIDALERT_N VSS VCC
@ T72
4.7U_0603_6.3V6K
RC88 43_0402_5% @ RC105 0_0603_5% @ RC106 0_0603_5% AM25 AJ28
PAD~D AM22 VSS VCC AJ29
1 VSS VCC
CC137
AM20 AJ30
AM24 VSS VCC AJ31
+VCCIO_OUT AL19 VSS VCC AJ32
SVID DATA 2
@
AM23 VSS
VSS
VCC
VCC
AJ33
130_0402_1%
AT32 AJ34
VSS VCC
1
CAD Note: Place the PU resistors close to CPU AJ35
VCC
RC90
B Place T72 close to G25 B

RC90 close to CPU 300 ‐ 1500mils VCC H25
T55 for iFDIM test VCC J25
VCC K25
2
+VCC_CORE VCC L25

VIDSOUT VCC M25
<54> VIDSOUT VCC
+1.35V_MEM Y25 N25
VDDQ DECOUPLING Y26 VCC VCC P25
Y27 VCC VCC R25
Y28 VCC VCC T25
Y29 VCC VCC
VCC
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M
1 1 Y30 U25
VCC VCC
@ CC34
1 1 1 1 1 1 1 1 1 1 Y31 U26
+VCC_CORE VCC VCC
@ CC24
@ CC25
@ CC26
@ CC27
@ CC28
@ CC29
@ CC30
@ CC31
CC35
+ + Y32 V25
VCC VCC
CC32
CC33
Y33 V26
VCC_SENSE 2 2 2 2 2 2 2 2 2 2 2 2
Y34 VCC
VCC
VCC
100_0402_1%
Y35 W26
VCC VCC
1
W27
VCC
RC91
5 OF 9
CAD Note: RC92 SHOULD BE PLACED CLOSE TO CPU CONN@
2
VCCSENSE 2 1 VCCSENSE_R
<54> VCCSENSE
@ RC92 0_0402_5%
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
CAD Note: RC93 SHOULD BE PLACED CLOSE TO CPU 1 1 1 1 1 1 1 1 1 1 1
@ CC41
@ CC37
@ CC42
@ CC43
@ CC38
@ CC44
@ CC39
@ CC45
@ CC46
CC40
CC36
VSSSENSE 2 1 VSSSENSE_R
<54> VSSSENSE VSSSENSE_R <12> 2 2 2 2 2 2 2 2 2 2 2
@ RC93 0_0402_5%
1
100_0402_1%
A A
RC94
2
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
JCPU1F JCPU1G
Haswell rPGA EDS Haswell rPGA EDS
A10 AK34 B34 K10

A13 VSS VSS AK5 B4 VSS VSS K2
D A16 VSS VSS AL1 B7 VSS VSS K29 D
A19 VSS VSS AL10 C1 VSS VSS K3
A7 VSS VSS AL21 C28 VSS VSS L11
AA11 VSS VSS AL23 C30 VSS VSS L26
AA25 VSS VSS E22 C32 VSS VSS L6
AA27 VSS VSS AL3 C34 VSS VSS M11
AB1 VSS VSS AL6 D10 VSS VSS M30
AB10 VSS VSS AL7 D13 VSS VSS M32
AA33 VSS VSS AL8 D16 VSS VSS M34
AA35 VSS VSS AL9 D19 VSS VSS M6
AB3 VSS VSS AM10 D22 VSS VSS N1
AC25 VSS VSS AM13 D25 VSS VSS N10
AB6 VSS VSS E25 D31 VSS VSS N3
AD11 VSS VSS AN10 D7 VSS VSS N4
AC29 VSS VSS AN13 E1 VSS VSS N5
C AC35 VSS VSS AN2 E16 VSS VSS N9 C
AD7 VSS VSS AN21 E4 VSS VSS P11
AE1 VSS VSS AN24 E7 VSS VSS P26
AE10 VSS VSS AN27 F10 VSS VSS P5
AE25 VSS VSS AN30 F11 VSS VSS R11
AE35 VSS VSS AP1 F17 VSS VSS R32
AE7 VSS VSS AP16 F21 VSS VSS T1
AE9 VSS VSS AP19 F23 VSS VSS T10
AF11 VSS VSS AP4 F24 VSS VSS T29
AF6 VSS VSS AP7 F26 VSS VSS T3
AF8 VSS VSS W25 F28 VSS VSS T31
AG11 VSS VSS AR10 F30 VSS VSS T33
AE31 VSS VSS AR16 F34 VSS VSS T4
AE33 VSS VSS AR2 F6 VSS VSS T7
AH1 VSS VSS AR25 F8 VSS VSS U11
AH10 VSS VSS AR28 F9 VSS VSS U27
AH2 VSS VSS AR31 G1 VSS VSS V11
AG27 VSS VSS AR34 G11 VSS VSS V28
AG29 VSS VSS AR4 G2 VSS VSS V30
AH3 VSS VSS AR7 G27 VSS VSS V32
AG33 VSS VSS AT10 G29 VSS VSS V34
AG35 VSS VSS AT13 G3 VSS VSS W1
AH4 VSS VSS AT16 G31 VSS VSS W10
B AH6 VSS VSS AT21 G35 VSS VSS W35 B
AH9 VSS VSS AT3 H10 VSS VSS W7
AJ11 VSS VSS AT30 H26 VSS VSS W9
AJ5 VSS VSS AT4 H6 VSS VSS Y11
AK11 VSS VSS AT7 H7 VSS VSS H11
AK25 VSS VSS B10 J11 VSS VSS AL24
AK26 VSS VSS B13 J26 VSS VSS F19
AK28 VSS VSS B16 J28 VSS VSS T26
AK29 VSS VSS B19 J30 VSS VSS AK35
AK30 VSS VSS B2 J32 VSS VSS_SENSE AK33 VSSSENSE_R <11>
AK32 VSS VSS B22 J34 VSS RSVD PAD~D T56 @
E19 VSS VSS J6 VSS
VSS K1 VSS
VSS
6 OF 9 7 OF 9
LOTES_AZIF0012-P002B_HASWELL LOTES_AZIF0012-P002B_HASWELL
CONN@ CONN@
A A
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
+SA_DIMM_VREFDQ +SA_DIMM_VREFDQ_Q +1.35V_MEM
1
1K_0402_1%
Populate RD1, De‐Populate RD3 for Intel DDR3
@ RD26 1 2 0_0402_5% VREFDQ multiple methods M1
RD19
+SA_DIMM1_VREFDQ Populate RD7, De‐Populate RD1 for Intel DDR3
JDIMM1 H=5.2mm
2
@ QD6A VREFDQ multiple methods M3
DMN66D0LDW-7_SOT363-6
1 6 RD17 1 2 2_0402_1%
+DIMM1_VREF_DQ
1K_0402_1%
1
1
+1.35V_MEM +1.35V_MEM
1K_0402_1%
+SA_DIMM1_VREFDQ @ RD1 1 2 0_0402_5%
1
RD27
D CD47 JDIMM1 D
RD18
0.022U_0402_16V7K +V_DDR_REF @ RD3 1 2 0_0402_5% 1 2
2 3 VREF_DQ VSS1 4 DDR_A_D4
VSS2 DQ4
2.2U_0402_6.3V6M
0.1U_0402_25V6
@ DDR_A_D0 5 6 DDR_A_D5
2
DDR_A_D1 7 DQ0 DQ5 8
1 1
2
DQ1 VSS3
1
9 10 DDR_A_DQS#0
VSS4 DQS#0
CD1
CD2
RC109 11 12 DDR_A_DQS0
13 DM0 DQS0 14
24.9_0402_1% VSS5 VSS6
2 @ 2 DDR_A_D2 15 16 DDR_A_D6
DDR_HVREF_RST_PCH DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7
<7,14,18> DDR_HVREF_RST_PCH
2
19 DQ3 DQ7 20
DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
25 DQ9 DQ13 26
+V_DDR_REF, +SA_DIMM1_VREFDQ, +SA_DIMM_VREFDQ, +DIMM1_VREF_DQ DDR_A_DQS#1 27 VSS9 VSS10 28
traces should be at least 20 mils wide and 20 mils spacing to other signals /planes. DDR_A_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#_R
31 DQS1 RESET# 32
+SM_VREF +SM_VREF_Q 37 DQ11 DQ15 38
+1.35V_MEM DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20
DQ17 DQ21
1
1K_0402_1%
@ RD29 1 20_0402_5% 43 44
DDR_A_DQS#2 45 VSS15 VSS16 46
DDR_A_DQS2 47 DQS#2 DM2 48
RD22
@ QD7 49 DQS2 VSS17 50 DDR_A_D22
+SM_VREF_DIMM DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23
2
L2N7002WT1G_SC-70-3 DDR_A_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_A_D28
VSS20 DQ28
S
3 1 RD20 1 2 2_0402_1% DDR_A_D24 57 58 DDR_A_D29

DDR_A_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_A_DQS#3
VSS22 DQS#3
1K_0402_1%
1K_0402_1%
63 64 DDR_A_DQS3
G
2
DM3 DQS3
1
1
1 65 66
VSS23 VSS24
RD28
RD21
DDR_A_D26 67 68 DDR_A_D30
CD48 DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
71 DQ27 DQ31 72
0.022U_0402_16V7K VSS25 VSS26
@ 2
C C
2
2
1
73 74 DDR_CKE1_DIMMA
<8> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <8>
RC110 75 76
DDR_HVREF_RST_PCH 77 VDD1 VDD2 78 DDR_A_MA15
24.9_0402_1% NC1 A15
DDR_A_BS2 79 80 DDR_A_MA14
<8> DDR_A_BS2 BA2 A14
81 82
2
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11

DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
Layout Note: 87 A9 A7 88
Place near JDIMM1 DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
+1.35V_MEM M_CLK_DDR0 101 VDD9 VDD10 102 M_CLK_DDR1
<8> M_CLK_DDR0 CK0 CK1 M_CLK_DDR1 <8>
M_CLK_DDR#0 103 104 M_CLK_DDR#1
<8> M_CLK_DDR#0 CK0# CK1# M_CLK_DDR#1 <8>
105 106
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <8>
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
DDR_A_BS0 109 110 DDR_A_RAS#

<8> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <8>
1 1 1 1 111 112
DDR_A_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMA#
<8> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <8>
CD3
CD4
CD5
CD6
DDR_A_CAS# 115 116 M_ODT0

<8> DDR_A_CAS# CAS# ODT0 M_ODT0 <8>
117 118
2 2 2 2 DDR_A_MA13 119 VDD15 VDD16 120 M_ODT1 +DIMM1_VREF_CA
A13 ODT1 M_ODT1 <8>
121 122
<8> DDR_CS1_DIMMA# S1# NC2
123 124
125 VDD17 VDD18 126 2 1
NCTEST VREF_CA +V_DDR_REF
127 128 @ RD5 0_0402_5%
DDR_A_D33 131 DQ32 DQ36 132 DDR_A_D37 2 1
DQ33 DQ37 +SM_VREF_DIMM
133 134 @ RD13 0_0402_5%
DDR_A_DQS#4 135 VSS29 VSS30 136
+1.35V_MEM Layout Note: DDR_A_DQS4 137 DQS#4 DM4 138
Place near JDIMM1.203,204 DQS4 VSS31
2.2U_0402_6.3V6M
0.1U_0402_25V6
139 140 DDR_A_D38
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39
B DQ34 DQ39 B
@ CD15
DDR_A_D35 143 144 1 1
DQ35 VSS33
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD16
145 146 DDR_A_D44
VSS34 DQ44
330U_2.5V_M
DDR_A_D40 147 148 DDR_A_D45

DDR_A_D41 149 DQ40 DQ45 150
1 DQ41 VSS35 2 2
@ CD13
1 1 1 1 1 1 1 151 152 DDR_A_DQS#5

VSS36 DQS#5
CD7
CD8
CD9
CD10
CD11
CD12
CD14
+ 153 154 DDR_A_DQS5

155 DM5 DQS5 156
+0.675V_DDR_VTT DDR_A_D42 157 VSS37 VSS38 158 DDR_A_D46
2 2 2 2 2 2 2 2 DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
161 DQ43 DQ47 162
DQ48 DQ52
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
DDR_A_D49 165 166 DDR_A_D53

167 DQ49 DQ53 168
1 1 1 1 VSS41 VSS42
DDR_A_DQS#6 169 170
DQS#6 DM6
CD17
CD18
CD19
CD20
DDR_A_DQS6 171 172

173 DQS6 VSS43 174 DDR_A_D54
2 2 2 2 DDR_A_D50 175 VSS44 DQ54 176 DDR_A_D55
DDR_A_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_A_D60
DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D61
<8> DDR_A_DQS#[0..7] DQ56 DQ61
DDR_A_D57 183 184
185 DQ57 VSS47 186 DDR_A_DQS#7
<8> DDR_A_D[0..63] VSS48 DQS#7
All VREF traces should 187 188 DDR_A_DQS7
189 DM7 DQS7 190
<8> DDR_A_DQS[0..7] VSS49 VSS50
have 10 mil trace width DDR_A_D58 191
DQ58 DQ62
192 DDR_A_D62
DDR_A_D59 193 194 DDR_A_D63
<8> DDR_A_MA[0..15] +3.3V_RUN DQ59 DQ63
195 196
DIMM1_SA0 197 VSS51 VSS52 198
199 SA0 EVENT# 200
+1.35V_MEM VDDSPD SDA DDR_XDP_WAN_SMBDAT <7,14,15,18,27,31>
DIMM1_SA1 201 202
SA1 SCL DDR_XDP_WAN_SMBCLK <7,14,15,18,27,31>
0.1U_0402_25V6
2.2U_0402_6.3V6M
1 +0.675V_DDR_VTT 203 204 +0.675V_DDR_VTT

VTT1 VTT2
1
1
CD22
205 206
G1 G2
CD21
@ RD4 2 10_0402_5% @ RD2

2 TYCO_2-2013290-1
1K_0402_5%
2 CONN@
A @ QD9 +V_DDR_REF, +SM_VREF_DIMM, +DIMM1_VREF_CA,+SM_VREF, +DIMM1_VREF_CA A
2
L2N7002WT1G_SC-70-3
traces should be at least 20 mils wide and 20 mils spacing to other signals /planes.
S
3 1 1 2
<7> DDR3_DRAMRST#_CPU DDR3_DRAMRST#_R <14>
@ RD25 0_0402_5%
G
2
1
@ RD24
4.99K_0402_1%
DDR_HVREF_RST_PCH
1 2 DIMM1_SA0
1
@ RD6 0_0402_5%
@ CD45 1 2 DIMM1_SA1 PROPRIETARY NOTE:
2
0.047U_0402_16V4Z @ RD7 0_0402_5% Title

2 THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
B
5 4 3 2 1
5 4 3 2 1
VREFDQ multiple methods M1
VREFDQ multiple methods M3
JDIMM2 H=9.2mm
+DIMM2_VREF_DQ
@ RD8 1 2 0_0402_5% +1.35V_MEM +1.35V_MEM
+SB_DIMM_VREFDQ +SB_DIMM_VREFDQ_Q +SB_DIMM2_VREFDQ
JDIMM2
+V_DDR_REF @ RD9 1 2 0_0402_5% 1 2
3 VREF_DQ VSS1 4 DDR_B_D4
+1.35V_MEM VSS2 DQ4
2.2U_0402_6.3V6M
0.1U_0402_25V6
D DDR_B_D0 5 6 DDR_B_D5 D
DDR_B_D1 7 DQ0 DQ5 8
DQ1 VSS3
1
1K_0402_1%
@ RD31 2 10_0402_5% 1 1 9 10 DDR_B_DQS#0
VSS4 DQS#0
CD24
CD23
11 12 DDR_B_DQS0
13 DM0 DQS0 14
RD15
DDR_B_D2 15 VSS5 VSS6 16 DDR_B_D6
@ QD6B +SB_DIMM2_VREFDQ 2 @ 2 DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D7
2
19 DQ3 DQ7 20
DMN66D0LDW-7_SOT363-6 DDR_B_D8 21 VSS7 VSS8 22 DDR_B_D12
4 3 RD14 1 2 2_0402_1% DDR_B_D9 23 DQ8 DQ12 24 DDR_B_D13
DQ9 DQ13
0.022U_0402_16V7K
25 26
VSS9 VSS10
1K_0402_1%
DDR_B_DQS#1 27 28
DQS#1 DM1
1
1K_0402_1%
DDR_B_DQS1 29 30 DDR3_DRAMRST#_R
DDR3_DRAMRST#_R <13>
5
DQS1 RESET#
1
RD30
1 31 32
VSS11 VSS12
RD16
DDR_B_D10 33 34 DDR_B_D14
DQ10 DQ14
CD46
@ 37 DQ11 DQ15 38
2
2 DDR_B_D16 39 VSS13 VSS14 40 DDR_B_D20
2
DDR_B_D17 41 DQ16 DQ20 42 DDR_B_D21
43 DQ17 DQ21 44
DDR_B_DQS#2 45 VSS15 VSS16 46
DQS#2 DM2
1
24.9_0402_1%
DDR_B_DQS2 47 48
DQS2 VSS17
RC108
49 50 DDR_B_D22
<7,13,18> DDR_HVREF_RST_PCH VSS18 DQ22
DDR_B_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D28
2
DDR_B_D24 57 VSS20 DQ28 58 DDR_B_D29

+V_DDR_REF, +SB_DIMM2_VREFDQ, +SB_DIMM_VREFDQ, +DIMM2_VREF_DQ DDR_B_D25 59 DQ24 DQ29 60
traces should be at least 20 mils wide and 20 mils spacing to other signals /planes. 61 DQ25 VSS21 62 DDR_B_DQS#3
63 VSS22 DQS#3 64 DDR_B_DQS3
65 DM3 DQS3 66
DDR_B_D27 69 DQ26 DQ30 70 DDR_B_D31
71 DQ27 DQ31 72
VSS25 VSS26
C DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB C
<8> DDR_B_DQS#[0..7] <8> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <8>
75 76
77 VDD1 VDD2 78 DDR_B_MA15
<8> DDR_B_D[0..63] NC1 A15
DDR_B_BS2 79 80 DDR_B_MA14
<8> DDR_B_BS2 BA2 A14
81 82
<8> DDR_B_DQS[0..7] VDD3 VDD4
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
<8> DDR_B_MA[0..15] A9 A7
87 88
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
Layout Note: M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3
<8> M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 <8>
Place near JDIMM2 <8> M_CLK_DDR#2
M_CLK_DDR#2 103
CK0# CK1#
104 M_CLK_DDR#3
M_CLK_DDR#3 <8>
105 106
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <8>
DDR_B_BS0 109 110 DDR_B_RAS#
<8> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <8>
111 112
DDR_B_WE# 113 VDD13 VDD14 114 DDR_CS2_DIMMB#
<8> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <8>
DDR_B_CAS# 115 116 M_ODT2
<8> DDR_B_CAS# CAS# ODT0 M_ODT2 <8>
117 118
+1.35V_MEM DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3 +DIMM2_VREF_CA
A13 ODT1 M_ODT3 <8>
DDR_CS3_DIMMB# 121 122
<8> DDR_CS3_DIMMB# S1# NC2
123 124
125 VDD17 VDD18 126 2 1
NCTEST VREF_CA +V_DDR_REF
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
127 128 @ RD10 0_0402_5%

1 1 1 1 DQ32 DQ36
DDR_B_D33 131 132 DDR_B_D37 2 1 +SM_VREF_DIMM
DQ33 DQ37
CD25
CD26
CD27
CD28
133 134 @ RD23 0_0402_5%

DDR_B_DQS#4 135 VSS29 VSS30 136
2 2 2 2 DQS#4 DM4
2.2U_0402_6.3V6M
0.1U_0402_25V6
DDR_B_DQS4 137 138
139 DQS4 VSS31 140 DDR_B_D38
VSS32 DQ38
@ CD37
DDR_B_D34 141 142 DDR_B_D39 1 1
DQ34 DQ39
CD38
DDR_B_D35 143 144
145 DQ35 VSS33 146 DDR_B_D44
B DQ40 DQ45 2 2 B
DDR_B_D41 149 150
151 DQ41 VSS35 152 DDR_B_DQS#5
+1.35V_MEM 153 VSS36 DQS#5 154 DDR_B_DQS5
155 DM5 DQS5 156
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47
161 DQ43 DQ47 162
VSS39 VSS40
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_B_D48 163 164 DDR_B_D52

DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53
1 DQ49 DQ53
@ CD35
330U_2.5V_M
1 1 1 1 1 1 1 167 168
VSS41 VSS42
CD29
CD30
CD31
CD32
CD33
CD34
CD36
+ DDR_B_DQS#6 169 170

DDR_B_DQS6 171 DQS#6 DM6 172
+V_DDR_REF, +SM_VREF_DIMM, +DIMM1_VREF_CA,+SM_VREF, +DIMM1_VREF_CA
173 DQS6 VSS43 174 DDR_B_D54 traces should be at least 20 mils wide and 20 mils spacing to other signals /planes.
2 2 2 2 2 2 2 2 DDR_B_D50 175 VSS44 DQ54 176 DDR_B_D55
DDR_B_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_B_D60
DDR_B_D57 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDR_B_DQS#7
187 VSS48 DQS#7 188 DDR_B_DQS7
189 DM7 DQS7 190
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63
+3.3V_RUN 195 DQ59 DQ63 196
DIMM2_SA0 197 VSS51 VSS52 198
Layout Note: 199 SA0 EVENT# 200
VDDSPD SDA DDR_XDP_WAN_SMBDAT <7,13,15,18,27,31>
Place near JDIMM2.203,204 DIMM2_SA1 201
SA1 SCL
202
DDR_XDP_WAN_SMBCLK <7,13,15,18,27,31>
0.1U_0402_25V6
2.2U_0402_6.3V6M
+0.675V_DDR_VTT 203 204 +0.675V_DDR_VTT

VTT1 VTT2
1 1
CD43
CD44
205 206
G1 G2
TYCO_2-2013311-1
2 2 CONN@
+0.675V_DDR_VTT
A A
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1
2 1 DIMM2_SA0
CD39
CD40
CD41
CD42
@ RD11 0_0402_5%
2 2 2 2 DELL CONFIDENTIAL/PROPRIETARY
+3.3V_RUN PROPRIETARY NOTE:
Title
2 1 DIMM2_SA1 THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
@ RD12 0_0402_5% TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATIC,MB LA-9931P
B
5 4 3 2 1
5 4 3 2 1
+RTC_CELL
PCH XDP
PXDP@ RH3 1 2 0_0402_5% XDP_FN0 +3.3V_ALW_PCH JXDP2
<19,40,41,42> USB_OC0#
330K_0402_1%
PXDP@ RH4 1 2 0_0402_5% XDP_FN1 1 2
<19,42> USB_OC1# GND0 GND1
1
PXDP@ RH6 1 2 0_0402_5% XDP_FN2 +3.3V_ALW_PCH 3 4 XDP_FN16
<19> USB_OC2# OBSFN_A0 OBSFN_C0
RH5
PXDP@ RH7 1 2 0_0402_5% XDP_FN3 5 6 XDP_FN17
<19> USB_OC3# OBSFN_A1 OBSFN_C1
0.1U_0402_25V6
PXDP@ RH8 1 2 0_0402_5% XDP_FN4 7 8
<19,43> USB_OC4# PXDP@ RH9 1 2 0_0402_5% XDP_FN5 XDP_FN0 9 GND2 GND3 10 XDP_FN8
<19> USB_OC5# 1 OBSDATA_A0 OBSDATA_C0
PXDP@
PXDP@ RH17 1 2 0_0402_5% XDP_FN6 XDP_FN1 11 12 XDP_FN9
2
<19> USB_OC6# OBSDATA_A1 OBSDATA_C1
CH2
PXDP@ RH10 1 2 0_0402_5% XDP_FN7 13 14
<19,46> SIO_EXT_SMI# HDD_DET# PXDP@ RH11 1 2 0_0402_5% XDP_FN8 XDP_FN2 15 GND4 GND5 16 XDP_FN10
PCH_INTVRMEN <15,17,31> HDD_DET# BBS_BIT0_R PXDP@ RH13 1 2 0_0402_5% XDP_FN9 2 XDP_FN3 17 OBSDATA_A2 OBSDATA_C2 18 XDP_FN11
D D
PCH_GPIO36 PXDP@ RH12 1 2 0_0402_5% XDP_FN10 19 OBSDATA_A3 OBSDATA_C3 20
<20> PCH_GPIO36 PCH_GPIO37 PXDP@ RH14 1 2 0_0402_5% XDP_FN11 21 GND6 GND7 22
<20> PCH_GPIO37 MCARD_PCIE_SATA# PXDP@ RH16 1 2 0_0402_5% XDP_FN12 23 OBSFN_B0 OBSFN_D0 24
INTVRMEN ‐ INTEGRATED SUS 1.05V VRM <20,45> MCARD_PCIE_SATA# PCH_GPIO49 PXDP@ RH19 1 2 0_0402_5% XDP_FN13 25 OBSFN_B1 OBSFN_D1 26
<20> PCH_GPIO49 GND8 GND9
ENABLE <17,33> LANCLK_REQ#
LANCLK_REQ# PXDP@ RH20 1 2 0_0402_5% XDP_FN14 XDP_FN4 27
OBSDATA_B0 OBSDATA_D0
28 XDP_FN12
MMICLK_REQ# PXDP@ RH22 1 2 0_0402_5% XDP_FN15 XDP_FN5 29 30 XDP_FN13
High ‐ Enable Internal VRs <17,36> MMICLK_REQ# SIO_EXT_WAKE# PXDP@ RH24 1 2 0_0402_5% XDP_FN16 31 OBSDATA_B1 OBSDATA_D1 32 +3.3V_ALW_PCH_JTAG
Low ‐ Enable External VRs <17,20,45> SIO_EXT_WAKE# PCH_GPIO35 PXDP@ RH25 1 2 0_0402_5% XDP_FN17 XDP_FN6 33 GND10 GND11 34 XDP_FN14
<20> PCH_GPIO35 PCH_RSMRST#_Q PXDP@ RH26 1 2 1K_0402_1% RSMRST#_XDP XDP_FN7 35 OBSDATA_B2 OBSDATA_D2 36 XDP_FN15
<16,47> PCH_RSMRST#_Q OBSDATA_B3 OBSDATA_D3
RESET_OUT# PXDP@ RH27 1 2 1K_0402_1% RESET_OUT#_R 37 38
<10,16,46> RESET_OUT# GND12 GND13
1
RSMRST#_XDP 39 40 +1.05V_RUN
1 2 PCH_PWRBTN#_XDP 41 PWRGOOD/HOOK0 ITPCLK/HOOK4 42 RH52
<7,16> SIO_PWRBTN#_R HOOK1 ITPCLK#/HOOK5
PXDP@ RH28 0_0402_5% 43 44 +3.3V_ALW_PCH 210_0402_1%
45 VCC_OBS_AB VCC_OBS_CD 46 RESET_OUT#_R
47 HOOK2 RESET#/HOOK6 48 XDP_DBRESET#
2
PXDP@ RH30 0_0402_5% 49 HOOK3 DBR#/HOOK7 50 XDP_DBRESET# <7,16>
1 2 DDR_XDP_WAN_SMBDAT_R2 51 GND14 GND15 52 PCH_JTAG_TDO
<7,13,14,18,27,31> DDR_XDP_WAN_SMBDAT SDA TD0
1 2 DDR_XDP_WAN_SMBCLK_R2 53 54 PCH_JTAG_RST_R 1 2 PCH_JTAG_RST
<7,13,14,18,27,31> DDR_XDP_WAN_SMBCLK SCL TRST#
PXDP@ RH31 0_0402_5% 55 56 PCH_JTAG_TDI @ RH32 0_0402_5%
PCH_JTAG_TCK 57 TCK1 TDI 58 PCH_JTAG_TMS
TCK0 TMS
1
+3.3V_RUN +3.3V_ALW_PCH 59 60 PXDP@
GND16 GND17 RH56
SAMTE_BSH-030-01-L-D-A CONN@ 100_0402_1%
1 2 SPKR 1 2 PCH_AZ_SDOUT
@ RH34 10K_0402_5% @ RH35 1K_0402_1%
2
+3.3V_RUN
NO REBOOT STRAP FLASH DESCRIPTOR SECURITY OVERRIDE
DISABLED WHEN LOW (DEFAULT) LOW = DESABLED (DEFAULT) BBS_BIT0_R 2 1
4.7K_0402_5% RH37
ENABLED WHEN HIGH HIGH = ENABLED CH4
1 2 PCH_RTCX1_R 1 2 PCH_RTCX1
@ RH38 0_0402_5%
C C
18P_0402_50V8J
1
YH1 RH39 UH1A DH82LPMS-QCG1-B0_FCBGA695~D
+3.3V_RUN 32.768KHZ_12.5PF_Q13FC1350000 10M_0402_5%
BC8 PSATA_PRX_DTX_N0_C
PSATA_PRX_DTX_N0_C <31>
2
1 2 PCH_GPIO33 B5 SATA_RXN_0 BE8 PSATA_PRX_DTX_P0_C
PSATA_PRX_DTX_P0_C <31>
2
@ RH40 10K_0402_5% CH5 RTCX1 SATA_RXP_0
HDD
1 2 PCH_RTCX2 B4 AW8 PSATA_PTX_DRX_N0_C
Follow Check list 1.0 RTCX2 SATA_TXN_0 AY8 PSATA_PTX_DRX_P0_C PSATA_PTX_DRX_N0_C <31>
RTC
RH42 1 2 20K_0402_1% 18P_0402_50V8J SRTCRST# B9 SATA_TXP_0 PSATA_PTX_DRX_P0_C <31>
+RTC_CELL SRTCRST# BC10 SATA_ODD_PRX_DTX_N1_C
SATA_RXN_1 SATA_ODD_PRX_DTX_N1_C <32>
RH43 1 2 1M_0402_5% INTRUDER# A8 BE10 SATA_ODD_PRX_DTX_P1_C
INTRUDER# SATA_RXP_1 SATA_ODD_PRX_DTX_P1_C <32>
ODD/ E Module Bay
PCH_INTVRMEN G10 AV10 SATA_ODD_PTX_DRX_N1_C
INTVRMEN SATA_TXN_1 AW10 SATA_ODD_PTX_DRX_P1_C SATA_ODD_PTX_DRX_N1_C <32>
RH44 1 2 20K_0402_1% PCH_RTCRST# D9 SATA_TXP_1 SATA_ODD_PTX_DRX_P1_C <32>
RTCRST# BB9 SATA_PRX_DKTX_N2_C
SATA_RXN_2 SATA_PRX_DKTX_N2_C <44>
BD9 SATA_PRX_DKTX_P2_C
<35> PCH_RTCRST# SATA_RXP_2 SATA_PRX_DKTX_P2_C <44>
CMOS_CLR1 CMOS setting PCH_AZ_BITCLK B25 DOCK
HDA_BCLK AY13 SATA_PTX_DKRX_N2_C
1 2 1 2 PCH_AZ_SYNC A22 SATA_TXN_2 AW13 SATA_PTX_DKRX_P2_C SATA_PTX_DKRX_N2_C <44>
Shunt Clear CMOS 1 2 1 2 HDA_SYNC SATA_TXP_2 SATA_PTX_DKRX_P2_C <44>
Open Keep CMOS SPKR AL10 BC12

<30> SPKR SPKR SATA_RXN_3 BE12
@ @ PCH_AZ_RST# C24 SATA_RXP_3
ME1 SHORT PADS~D CMOS1 SHORT PADS~D HDA_RST# AR13
ME_CLR1 TPM setting SATA_TXN_3
AZALIA
1 2 1 2 PCH_AZ_CODEC_SDIN0 L22 AT13
SATA
1U_0402_6.3V6K <30> PCH_AZ_CODEC_SDIN0 HDA_SDI0 SATA_TXP_3
Shunt Clear ME RTC Registers CH6 1U_0402_6.3V6K CH7
CMOS place near DIMM K22
HDA_SDI1 BD13 PCIE_SATA_PRX_WANTX_N4
Open Keep ME RTC Registers G22 SATA_RXN4/PERN1 BB13 PCIE_SATA_PRX_WANTX_P4
PCIE_SATA_PRX_WANTX_N4 <38>
HDA_SDI2 SATA_RXP4/PERP1 PCIE_SATA_PRX_WANTX_P4 <38>
WWAN (JMINI1)
F22 AV15 PCIE_SATA_PTX_WANRX_N4
HDA_SDI3 SATA_TXN4/PETN1 AW15 PCIE_SATA_PTX_WANRX_P4 PCIE_SATA_PTX_WANRX_N4 <38>
SATA_TXP4/PETP1 PCIE_SATA_PTX_WANRX_P4 <38> SATA by default
B <45> ME_FWP 1 2 PCH_AZ_SDOUT A24 B
RH45 1K_0402_1% HDA_SDO BC14
PCH_GPIO33 B17 SATA_RXN5/PERN2 BE14
DOCKEN#/GPIO33 SATA_RXP5/PERP2
+3.3V_ALW_PCH USB30_SMI# C22 AP15
<32,45> USB30_SMI# HDA_DOCK_RST#/GPIO13 SATA_TXN5/PETN2 AR15
SATA_TXP5/PETP2
1
0_0603_5%
RH46
PXDP@
AY5 SATA_COMP
SATA_RCOMP
AP3 SATA_ACT#
SATALED# SATA_ACT# <24>
2
RH47 2 1 51_0402_1% PCH_JTAG_TCK AB3 AT1 HDD_DET#

JTAG_TCK SATA0GP/GPIO21 HDD_DET# <15,17,31>
+3.3V_ALW_PCH_JTAG RH48 1 2 210_0402_1% PCH_JTAG_TMS AD1 AU2 BBS_BIT0_R 1 3
S
JTAG_TMS SATA1GP/GPIO19 PCH_SATA_MOD_EN# <46>
RH50 1 2 210_0402_1% PCH_JTAG_TDI AE2 BD4 SATA_IREF 2 1
JTAG
JTAG_TDI SATA_IREF +1.5V_RUN
@ RH51 0_0402_5% QH2
G
2
PCH_JTAG_TDO AD3 BA2 BSS138W-7-F_SOT323-3~D
JTAG_TDO TP9
PXDP@ RH54
PXDP@ RH55
PAD~D T57 @
<7,16> PCH_PLTRST#
1 2 PCH_TP25 F8 BB2
TP25 TP8
100_0402_1%
100_0402_1%
@ RH53 0_0402_5% PAD~D T58 @

1
C26
@ T59 PAD~D TP22
PCH_JTAG_RST AB6
TP20
SATA Impedance Compensation
2
1 OF 11
HDA for Codec RPH10
DH82LPMS-QCG1-B0_FCBGA695~D
SATA_COMP 1 2
+1.5V_RUN
7.5K_0402_1% RH57
1 8 PCH_AZ_BITCLK
UH1 change PN to SA00005NE2L IC A31 DH82LPMS QCG1 B0 FCBGA 695P PCH
<30> PCH_AZ_CODEC_BITCLK
2 7 PCH_AZ_SDOUT CAD note:
<30> PCH_AZ_CODEC_SDOUT
3 6 PCH_AZ_RST#
A <30> PCH_AZ_CODEC_RST#
4 5 PCH_AZ_SYNC Place the resistor within 500 mils of the PCH. Avoid A
<30> PCH_AZ_CODEC_SYNC routing next to clock pins.
33_8P4R_5%
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
@ RH66 1 2 0_0402_5% RPH4
PCI_PIRQA# 1 8
+3.3V_RUN +RTC_CELL PCI_PIRQB# 2 7
+PCH_VCCDSW3_3 @ CH10 PCI_PIRQC# 3 6
330K_0402_1%
1 2 PCI_PIRQD# 4 5
2
5
RH67
1 2 PCH_PCIE_WAKE# 0.1U_0402_25V6 8.2K_8P4R_5%
RH92 10K_0402_5% 1
P
<7,15> XDP_DBRESET# B
1 2 SIO_SLP_LAN# 4 SYS_RESET#
@ RH80 10K_0402_5% 2 1 ME_RESET# 2 O SYS_RESET# <35>
1
A
G
@ RH70 8.2K_0402_5% @ UC3 RPH6
74AHC1G09GW_TSSOP5 LCD_CBL_DET# 4 5
3
+3.3V_ALW_PCH +3.3V_ALW2 PCH_GPIO55 XFR_ID# 3 6
@ CH11 DSWODVREN CAM_MIC_CBL_DET# 2 7
D 1 2 1 8 D
1
330K_0402_1%
1K_0402_1%
1 2 PCH_PCIE_WAKE#
@ RH81
@ RH76
@ RH78 10K_0402_5% 0.1U_0402_25V6 10K_8P4R_5%
2
1 2 SUS_STAT#/LPCPD# PCH_DPWROK 1 2 PCH_RSMRST#_R
@ RH73 10K_0402_5% @ RH79 0_0402_5%
VCC
1 2 ME_SUS_PWR_ACK SIO_SLP_A# 1 PCH_CRT_DDC_CLK 2 1
2
RH75 10K_0402_5% IN B 4 PM_APWROK_R 2.2K_0402_5% RH88
PM_APWROK 2 OUT Y PCH_CRT_DDC_DAT 2 1
GND
<46> PM_APWROK
1
+3.3V_RUN RESET_OUT# 1 2 SYS_PWROK IN A UH2 2.2K_0402_5% RH89
@ RH85 0_0402_5%
1 2 CLKRUN# NL17SZ08DFT2G_SC70-5
3
RH90 8.2K_0402_5%
1 2 ME_RESET#
@ RH93 8.2K_0402_5% ME_SUS_PWR_ACK_R 1 2 SUSACK#_R DSWODVREN ‐ ON DIE DSW VR ENABLE A16 SWAP OVERRIDE STRAP
@ RH91 0_0402_5%
1 2 HIGH = ENABLED (DEFAULT)
@ RH87 0_0402_5% STP_A16OVR LOW = A16 SWAP OVERRIDE
1 2 PCH_DPWROK LOW = DISABLED PCH_DDPB_CTRLCLK 2 1
RH120 100K_0402_5% HIGH = DEFAULT 2.2K_0402_5% RH255
PCH_DDPB_CTRLDATA 2 1
2.2K_0402_5% RH256
UH1B LPT_PCH_M_EDS
AW22
<6> DMI_CTX_PRX_N0 DMI_RXN_0
AR20
<6> DMI_CTX_PRX_N1 DMI_RXN_1 AJ35
FDI_RXN_0 FDI_CTX_PRX_N0 <9>
AP17
<6> DMI_CTX_PRX_N2 DMI_RXN_2
AV20 AL35
<6> DMI_CTX_PRX_N3 DMI_RXN_3 FDI_RXN_1 FDI_CTX_PRX_N1 <9>
AY22 AJ36 UH1E LPT_PCH_M_EDS
<6> DMI_CTX_PRX_P0 DMI_RXP_0 FDI_RXP_0 FDI_CTX_PRX_P0 <9>
AP20
<6> DMI_CTX_PRX_P1 DMI_RXP_1 AL36 PCH_CRT_BLU T45 R40 PCH_DDPB_CTRLCLK PCH_DDPB_CTRLCLK <26>
FDI_RXP_1 FDI_CTX_PRX_P1 <9> <25> PCH_CRT_BLU VGA_BLUE DDPB_CTRLCLK
AR17
<6> DMI_CTX_PRX_P2 DMI_RXP_2
AW20 AV43 PAD~D T62 @ PCH_CRT_GRN U44 R39 PCH_DDPB_CTRLDATA
C <6> DMI_CTX_PRX_P3 DMI_RXP_3 TP16 <25> PCH_CRT_GRN VGA_GREEN DDPB_CTRLDATA PCH_DDPB_CTRLDATA <26> C
BD21 AY45 PAD~D T63 @ PCH_CRT_RED V45 R35 PCH_DDPC_CTRLCLK <29>
<6> DMI_CRX_PTX_N0 DMI_TXN_0 TP5 <25> PCH_CRT_RED VGA_RED DDPC_CTRLCLK
BE20
<6> DMI_CRX_PTX_N1 DMI_TXN_1 DMI FDI AV45 PAD~D T60 @ PCH_CRT_DDC_CLK M43 R36
TP15 <25> PCH_CRT_DDC_CLK VGA_DDC_CLK DDPC_CTRLDATA PCH_DDPC_CTRLDATA <29>
BD17
<6> DMI_CRX_PTX_N2 DMI_TXN_2
BE18 AW44 PAD~D T61 @ PCH_CRT_DDC_DAT M45 N40
CRT
<6> DMI_CRX_PTX_N3 DMI_TXN_3 TP10 <25> PCH_CRT_DDC_DAT VGA_DDC_DATA DDPD_CTRLCLK PCH_DDPD_CTRLCLK <29>
BB21 AL39 FDI_CSYNC 1 2 HSYNC N42 N38
<6> DMI_CRX_PTX_P0 DMI_TXP_0 FDI_CSYNC FDI_CSYNC <6> <25> PCH_CRT_HSYNC VGA_HSYNC DDPD_CTRLDATA PCH_DDPD_CTRLDATA <29>
BC20 RH94 20_0402_1%
<6> DMI_CRX_PTX_P1 DMI_TXP_1 AL40 FDI_INT 1 2 VSYNC N44
FDI_INT FDI_INT <6> <25> PCH_CRT_VSYNC VGA_VSYNC
BB17 RH95 20_0402_1% H45
<6> DMI_CRX_PTX_P2 DMI_TXP_2 DDPB_AUXN
BC18 AT45 FDI_IREF 2 1 1 2 CRT_IREF U40
DISPLAY
<6> DMI_CRX_PTX_P3 DMI_TXP_3 FDI_IREF +1.5V_RUN DAC_IREF
@ RH96 0_0402_5% RH97 649_0402_1% K43
2 1 DMI_IREF BE16 AU42 PAD~D T64 @ U39 DDPC_AUXN DPC_PCH_DOCK_AUX# <29>
+1.5V_RUN DMI_IREF TP17 VGA_IRTN
@ RH98 0_0402_5% J42
AW17 AU44 PAD~D T66 @ DDPD_AUXN DPD_PCH_DOCK_AUX# <29>
@ T65 PAD~D TP12 TP13 BIA_PWM_PCH N36 H43
<27> BIA_PWM_PCH EDP_BKLTCTL DDPB_AUXP
AV17 AR44 FDI_RCOMP 2 1
LVDS
TP7 FDI_RCOMP +1.5V_RUN
@ T67 PAD~D 7.5K_0402_1% RH99 PANEL_BKEN_PCH K36 K45
<28> PANEL_BKEN_PCH EDP_BKLTEN DDPC_AUXP DPC_PCH_DOCK_AUX <29>
+1.5V_RUN 1 2 DMI_RCOMP AY17
RH100 7.5K_0402_1% DMI_RCOMP ENVDD_PCH G36 J44
<45> ENVDD_PCH EDP_VDDEN DDPD_AUXP DPD_PCH_DOCK_AUX <29>
K40
1 2 SUSACK#_R R6 C8 DSWODVREN PCI_PIRQA# H20 DDPB_HPD HDMIB_PCH_HPD <26>
<45> SUSACK# SUSACK# DSWVRMEN PIRQA#
@ RH101 0_0402_5% K38
SYS_RESET# AM1 L13 PCH_DPWROK PCI_PIRQB# L20 DDPC_HPD DPC_PCH_DOCK_HPD <44>
SYS_RESET# DPWROK PCH_DPWROK <45> PIRQB# H39
1 2 SYS_PWROK_R AD7 K3 PCH_PCIE_WAKE# PCI_PIRQC# K17 DDPD_HPD DPD_PCH_DOCK_HPD <44>
<7,45> SYS_PWROK SYS_PWROK WAKE# PCH_PCIE_WAKE# <46> PIRQC#
@ RH102 0_0402_5%
1 2 PCH_PWROK F10 AN7 CLKRUN# PCI_PIRQD# M20
<10,15,46> RESET_OUT# PWROK System Power CLKRUN# CLKRUN# <35,45,46> PIRQD#
@ RH103 0_0402_5% G17 LCD_CBL_DET#
Management PIRQE#/GPIO2 LCD_CBL_DET# <28>
PM_APWROK_R AB7 U7 SUS_STAT#/LPCPD# A12
APWROK SUS_STAT#/GPIO61 SUS_STAT#/LPCPD# <35> GPIO50 F17 XFR_ID#
PCI PIRQF#/GPIO3 XFR_ID# <43>
1 2 PM_DRAM_PWRGD_R H3 Y6 SUSCLK PAD~D T68 @ B13
<7> PM_DRAM_PWRGD DRAMPWROK SUSCLK/GPIO62 <37> CPPE# GPIO52
B @ RH104 0_0402_5% L15 CAM_MIC_CBL_DET# B
PIRQG#/GPIO4 CAM_MIC_CBL_DET# <28>
1 2 PCH_RSMRST#_R J2 Y7 C12
<15,47> PCH_RSMRST#_Q RSMRST# SLP_S5#/GPIO63 SIO_SLP_S5# <35,46> GPIO54
@ RH105 0_0402_5% M15 FFS_PCH_INT 2 1
PIRQH#/GPIO5 HDD_FALL_INT <31>
1 2 ME_SUS_PWR_ACK_R J4 C6 SIO_SLP_S4# BBS_BIT1 C10 0_0402_5% @ RH106
<46> ME_SUS_PWR_ACK SUSWARN#/SUSPWRNACK/GPIO30 SLP_S4# SIO_SLP_S4# <35,45,51> GPIO51
@ RH107 0_0402_5% AD10 @ T71 PAD~D
<7,15> SIO_PWRBTN#_R PME#
1 2 SIO_PWRBTN#_R K1 H1 SIO_SLP_S3# A10
<46> SIO_PWRBTN# PWRBTN# SLP_S3# SIO_SLP_S3# <35,39,40,45,53> <37> USB_MCARD1_DET# GPIO53
@ RH108 0_0402_5% Y11 PCH_PLTRST# @ RH109 2 1 0_0402_5%
PLTRST# PLTRST_USH# <35>
E6 F3 SIO_SLP_A# PCH_GPIO55 AL6 @ RH110 2 1 0_0402_5%
<46> AC_PRESENT ACPRESENT/GPIO31 SLP_A# SIO_SLP_A# <35,45,52> GPIO55 PLTRST_MMI# <36>
@ RH111 2 1 0_0402_5%
5 OF 11 PLTRST_LAN# <33>
+PCH_VCCDSW3_3 1 2 PCH_BATLOW# K7 F1 @ RH113 2 1 0_0402_5%
BATLOW#/GPIO72 SLP_SUS# SIO_SLP_SUS# <45> PLTRST_EMB# <32>
RH112 8.2K_0402_5%
PCH_RI# N4 AY3 H_PM_SYNC DH82LPMS-QCG1-B0_FCBGA695~D
<17> PCH_RI# RI# PMSYNCH H_PM_SYNC <7>
@ T75 PAD~D AB10 G5 SIO_SLP_LAN# RPH17
TP21 SLP_LAN# SIO_SLP_LAN# <39,45>
D2 1 8 PCH_CRT_RED +3.3V_RUN
<45> SIO_SLP_WLAN# SLP_WLAN#/GPIO29 2 7 PCH_CRT_GRN @ CH12
4 OF 11 3 6 PCH_CRT_BLU 1 2
4 5
DH82LPMS-QCG1-B0_FCBGA695~D 0.1U_0402_25V6
150_0804_8P4R_1%
UH3
5
1 2 ENVDD_PCH NL17SZ08DFT2G_SC70-5
RH118 100K_0402_5%
VCC
PCH_PLTRST# 1
Boot BIOS Strap <7,15> PCH_PLTRST# IN B
OUT Y
4
PCH_PLTRST#_EC <35,37,38,39,45,46>
2
GND
IN A
SATA_SLPD
BBS_BIT1
BBS_BIT1 (BBS_BIT0) Boot BIOS Location PCH_PLTRST#
3
1K_0402_1%
0 0 LPC
1
1
@ RH119
@
0 1 Reserved (NAND) C1564
A 0.047U_0402_16V4Z A
2
2
1 0 PCI
ESD Request
* 1 1 SPI DELL CONFIDENTIAL/PROPRIETARY
GPIO51 has internal pull up.
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW_PCH
RPH8
PEG_B_CLKRQ# 4 5
PCIECLKRQ6# 3 6
MINI3CLK_REQ# 2 7
RPH20 PCH_RI# 1 8
<16> PCH_RI#
+3.3V_RUN 4 5 MMICLK_REQ#
3 6 HDD_DET# 10K_8P4R_5%
2 7 CLK_BUF_CKSSCD# HDD_DET# <15,31>
1 8 CLK_BUF_CKSSCD
RPH9
10K_8P4R_5% EXPCLK_REQ# 4 5
SIO_EXT_WAKE# 3 6
<15,20,45> SIO_EXT_WAKE#
MINI2CLK_REQ# 2 7
D RPH21 EMBCLK_REQ# 1 8 D
+3.3V_ALW_PCH 4 5 MINI1CLK_REQ#
3 6 PCH_SMB_ALERT# 10K_8P4R_5%
2 7 TEMP_ALERT# PCH_SMB_ALERT# <18> +3.3V_ALW_PCH
TEMP_ALERT# <18,45>
+PCH_VCCDSW3_3 1 8 PM_LANPHY_ENABLE PM_LANPHY_ENABLE <20,33>
10K_8P4R_5% RPH18
PEG_A_CLKRQ# 4 5
LANCLK_REQ# 3 6 +3.3V_RUN
IRQ_SERIRQ 2 7
UH1C LPT_PCH_M_EDS <18,35,45,46> IRQ_SERIRQ
1 8
10K_8P4R_5%
Y43 AB35
<38> CLK_PCIE_MINI1# CLKOUT_PCIE_N_0 CLKOUT_PEG_A RPH19
WWAN (Mini Card 1)---> Y45 AB36 CLK_BUF_DOT96# 4 5
<38> CLK_PCIE_MINI1 CLKOUT_PCIE_P_0 CLKOUT_PEG_A_P CLK_BUF_DOT96 3 6
MINI1CLK_REQ# AB1 AF6 PEG_A_CLKRQ# PCH_GPIO06 2 7
<38> MINI1CLK_REQ# PCIECLKRQ0#/GPIO73 PEGA_CLKRQ#/GPIO47 <20> PCH_GPIO06
CONTACTLESS_DET# 1 8 +3.3V_RUN
<20,35> CONTACTLESS_DET#
AA44 Y39
<33> CLK_PCIE_LAN# AA42 CLKOUT_PCIE_N_1 CLKOUT_PEG_B 10K_8P4R_5%
<33> CLK_PCIE_LAN CLKOUT_PCIE_P_1 Y38
10/100/1G LAN ---> CLKOUT_PEG_B_P
LANCLK_REQ# AF1
<15,33> LANCLK_REQ# PCIECLKRQ1#/GPIO18 U4 PEG_B_CLKRQ#
AB43 PEGB_CLKRQ#/GPIO56
<36> CLK_PCIE_MMI# CLKOUT_PCIE_N_2 AF39 CLK_CPU_DMI#
AB45 CLKOUT_DMI CLK_CPU_DMI# <7>
MMI---> <36> CLK_PCIE_MMI CLKOUT_PCIE_P_2 AF40 CLK_CPU_DMI RPH5
MMICLK_REQ# AF3 CLKOUT_DMI_P CLK_CPU_DMI <7> CLK_BUF_DMI# 4 5
<15,36> MMICLK_REQ# PCIECLKRQ2#/GPIO20/SMI# AJ40 CLK_CPU_SSC_DPLL# CLK_BUF_DMI 3 6
AD43 CLKOUT_DP AJ39 CLK_CPU_SSC_DPLL CLK_CPU_SSC_DPLL# <7> CLK_BUF_BCLK# 2 7
<37> CLK_PCIE_MINI3# CLKOUT_PCIE_N_3 CLKOUT_DP_P CLK_CPU_SSC_DPLL <7>
PP (Mini Card 3)---> AD45 CLK_BUF_BCLK 1 8
C <37> CLK_PCIE_MINI3 CLKOUT_PCIE_P_3 C
MINI3CLK_REQ# T3 AF35 CLK_CPU_DPLL#
<37> MINI3CLK_REQ# PCIECLKRQ3#/GPIO25 CLKOUT_DPNS CLK_CPU_DPLL# <7>
AF36 CLK_CPU_DPLL 10K_8P4R_5%
AF43 CLKOUT_DPNS_P CLK_CPU_DPLL <7>
<39> CLK_PCIE_EXP# CLKOUT_PCIE_N_4
AF45 AY24 CLK_BUF_DMI# CLK_PCH_14M RH1461 2 10K_0402_5%
<39> CLK_PCIE_EXP CLKOUT_PCIE_P_4 CLKIN_DMI
Express card---> EXPCLK_REQ# V3 AW24 CLK_BUF_DMI
<39> EXPCLK_REQ# PCIECLKRQ4#/GPIO26 CLOCK SIGNAL CLKIN_DMI_P
AE44 AR24 CLK_BUF_BCLK#
<37> CLK_PCIE_MINI2# CLKOUT_PCIE_N5 CLKIN_GND
AE42 AT24 CLK_BUF_BCLK
<37> CLK_PCIE_MINI2 CLKOUT_PCIE_P_5 CLKIN_GND_P
MINI2CLK_REQ# AA2
<37> MINI2CLK_REQ# PCIECLKRQ5#/GPIO44
WLAN (Mini Card 2)---> H33 CLK_BUF_DOT96#
AB40 CLKIN_DOT96N G33 CLK_BUF_DOT96
AB39 CLKOUT_PCIE_N_6 CLKIN_DOT96P CLOCK TERMINATION for FCIM and need close to PCH
PCIECLKRQ6# AE4 CLKOUT_PCIE_P_6 BE6 CLK_BUF_CKSSCD#
PCIECLKRQ6#/GPIO45 CLKIN_SATA BC6 CLK_BUF_CKSSCD
AJ44 CLKIN_SATA_P
<32> CLK_PCIE_EMB# CLKOUT_PCIE_N_7 F45 CLK_PCH_14M
AJ42 REFCLK14IN D17 CLK_PCI_LOOPBACK
eModule Bay---> <32> CLK_PCIE_EMB CLKOUT_PCIE_P_7 CLKIN_33MHZLOOPBACK
EMBCLK_REQ# Y3 AM43 XTAL25_IN 2 1
<32> EMBCLK_REQ# PCIECLKRQ7#/GPIO46 XTAL25_IN AL44 XTAL25_OUT @ RH152 1 2 0_0402_5%
AH43 XTAL25_OUT EMC@ RH153 1M_0402_5%
XTAL25_IN_R
CLKOUT_ITPXDP C40 PCI_TPM_TCM RH155 2 1 22_0402_5%
CLKOUTFLEX0/GPIO64 CLK_PCI_TPM <35>
AH45
CLKOUT_ITPXDP_P F38 SIO_14M RH157 2 1 22_0402_5%
CLKOUTFLEX1/GPIO65 CLK_SIO_14M <45>
EMC@ RH158 2 1 22_0402_5% PCI_5048 D44
<45> CLK_PCI_5048 CLKOUT_33MHZ0 F36 CLK_80H RH159 2 1 22_0402_5% YH2
CLKOUTFLEX2/GPIO66 PCLK_80H <37>
EMC@ RH160 2 1 22_0402_5% PCI_MEC E44 25MHZ 10PF +-20PPM 7V25000014
<46> CLK_PCI_MEC CLKOUT_33MHZ1 F39 3 1
EMC@ RH162 2 1 22_0402_5% PCI_DOCK B42 CLKOUTFLEX3/GPIO67 OUT IN
<44> CLK_PCI_DOCK CLKOUT_33MHZ2 AM45 ICLK_IREF 1 2 +1.5V_RUN 4 2
ICLK_IREF GND GND
12P_0402_50V8J
12P_0402_50V8J
F41 @ RH163 0_0402_5% 2 2
CLKOUT_33MHZ3
CH13
CH14
AD39
B CLK_PCI_LOOPBACK EMC@ RH164 2 1 22_0402_5% PCI_LOOPBACKOUT A40 TP19 AD38 PAD~D T76 @ B
CLKOUT_33MHZ4 TP18 PAD~D T77 @
AN44 PCH_CLK_BIASREF 1 2 1 1
DIFFCLK_BIASREF +1.5V_RUN
7.5K_0402_1% RH165
2 OF 11
PCIECLK REQ Pull UP Power Rail: DH82LPMS-QCG1-B0_FCBGA695~D
SUS Rail : 0 3 4 5 6 7
Core Rail: 1 2
CLK_PCI_DOCK
1
@ RH330
33_0402_5%
10P_0402_50V8J
2
1
@
CH76
2
A A
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
2
MEM_SMBCLK 6 1
DDR_XDP_WAN_SMBCLK <7,13,14,15,27,31>
QH4A
5
D +3.3V_ALW_PCH D
MEM_SMBDATA 3 4
DDR_XDP_WAN_SMBDAT <7,13,14,15,27,31>
QH4B
DMN66D0LDW-7_SOT363-6 DDR_HVREF_RST_PCH 2 1
1K_0402_1% RH170
RPH12
SML1_SMBCLK 1 8
SML1_SMBDATA 2 7
MEM_SMBCLK 3 6
UH1D LPT_PCH_M_EDS
MEM_SMBDATA 4 5
2.2K_8P4R_5%
N7 PCH_SMB_ALERT#
SMBALERT#/GPIO11 PCH_SMB_ALERT# <17>
A20
<35,37,45,46> LPC_LAD0 LAD_0
SMBus R10 MEM_SMBCLK
C20 SMBCLK
<35,37,45,46> LPC_LAD1 LAD_1 U11 MEM_SMBDATA
A18 SMBDATA
LPC
<35,37,45,46> LPC_LAD2 LAD_2 N8 DDR_HVREF_RST_PCH
C18 SML0ALERT#/GPIO60 DDR_HVREF_RST_PCH <7,13,14>
<35,37,45,46> LPC_LAD3 LAD_3 U8 LAN_SMBCLK
B21 SML0CLK LAN_SMBCLK <33>
<35,37,45,46> LPC_LFRAME# LFRAME# R7 LAN_SMBDATA
SML0DATA LAN_SMBDATA <33> +3.3V_LAN
@ T87 PAD~D LPC_LDRQ0# D21
LDRQ0# H6 TEMP_ALERT#
SML1ALERT#/PCHHOT#/GPIO74 TEMP_ALERT# <17,45>
G20 LAN_SMBCLK 2 1
<45> LPC_LDRQ1# LDRQ1#/GPIO23 K6 SML1_SMBCLK 2.2K_0402_5% RH174
SML1CLK/GPIO58 SML1_SMBCLK <46>
IRQ_SERIRQ AL11 LAN_SMBDATA 2 1
<17,35,45,46> IRQ_SERIRQ SERIRQ N11 SML1_SMBDATA 2.2K_0402_5% RH175
SML1DATA/GPIO75 SML1_SMBDATA <46>
C C
AF11 PCH_CL_CLK1
CL_CLK PCH_CL_CLK1 <37>
PCH_SPI_CLK AJ11
SPI_CLK AF10 PCH_CL_DATA1
C-Link CL_DATA PCH_CL_DATA1 <37>
PCH_SPI_CS0# AJ7
SPI_CS0# AF7 PCH_CL_RST1#
PCH_SPI_CS1# AL7 CL_RST# PCH_CL_RST1# <37>
SPI_CS1#
AJ10
SPI_CS2#
SPI
BA45 PAD~D T78 @
PCH_SPI_DO AH1 TP1
SPI_MOSI BC45 PAD~D T79 @
PCH_SPI_DIN AH3 Thermal TP2
SPI_MISO BE43 PAD~D T80 @
PCH_SPI_DO2 AJ4 TP4
SPI_IO2 BE44 PAD~D T81 @
PCH_SPI_DO3 AJ2 TP3
SPI_IO3 AY43 PCH_TD_IREF 1 2
TD_IREF RH176 8.2K_0402_1%
3 OF 11
+3.3V_SPI
1 2 SPI_PCH_DO2_64 +3.3V_SPI
R3664 1K_0402_5%
1 2 SPI_PCH_DO3_64 C746
R3668 1K_0402_5% 200 MIL SO8 1 2
1 2 SPI_PCH_DO2_32
B R3665 1K_0402_5% 64Mb Flash ROM 0.1U_0402_25V6 B
1 2 SPI_PCH_DO3_32 U52
R3666 1K_0402_5% SPI_PCH_CS0# R7 1 2 47_0402_5% SPI_PCH_CS0#_R 1 8 JSPI1
SPI_DIN64 2 /CS VCC 7 SPI_PCH_DO3_64 R3669 1 2 33_0402_5% SPI_PCH_DO3 2 1 SPI_PCH_CS1# 1
SPI_PCH_DO2_64 3 DO(IO1) /HOLD(IO3) 6 SPI_CLK64 0_0402_5% RH177 @ PCH_SPI_CS1# 2 1
4 /WP(IO2) CLK 5 SPI_DO64 2 1 SPI_PCH_DO 3 2
SPI_WP#_SEL 2 1 GND DI(IO0) 0_0402_5% RH178 @ PCH_SPI_DO 4 3
<45> SPI_WP#_SEL 4
@ RH180 0_0402_5% W25Q64FVSSIQ_SO8 2 1 SPI_PCH_DIN 5
0_0402_5% RH179 @ PCH_SPI_DIN 6 5
SPI@ 6
RPH7 2 1 SPI_PCH_CLK 7
SPI_CLK64 1 8 SPI_PCH_CLK 0_0402_5% RH181 @ PCH_SPI_CLK 8 7
SPI_DO64 2 7 SPI_PCH_DO 2 1 SPI_PCH_CS0# 9 8
SPI_PCH_DO3_323 6 SPI_PCH_DO3 0_0402_5% RH182 @ PCH_SPI_CS0# 10 9
RPH11 SPI_CLK32 4 5 SPI_PCH_CLK 2 1 SPI_PCH_DO2 11 10
SPI_PCH_DIN 1 8 SPI_DIN64 0_0402_5% RH183 @ PCH_SPI_DO2 12 11
SPI_PCH_DO2 2 7 SPI_PCH_DO2_64 33_8P4R_5% 2 1 SPI_PCH_DO3 13 12
SPI_PCH_DIN 3 6 SPI_DIN32 0_0402_5% RH184 @ PCH_SPI_DO3 14 13
SPI_PCH_DO2 4 5 SPI_PCH_DO2_32 15 14
+3.3V_SPI 15
+3.3V_M 16
33_8P4R_5% +3.3V_SPI 17 16
2 1 18 17
C1216 0_0402_5% RH185 @ 19 18
200 MIL SO8 1 2 20 19
20
32Mb Flash ROM 0.1U_0402_25V6 21
U53 22 GND1
SPI_PCH_CS1# R936 1 2 47_0402_5% SPI_PCH_CS1#_R 1 8 GND2
SPI_DIN32 2 /CS VCC 7 SPI_PCH_DO3_32 TYCO_2-2041070-0
SPI_PCH_DO2_32 3 DO/IO1 /HOLD/IO3 6 SPI_CLK32 CONN@
4 /WP/IO2 CLK 5 SPI_DO32 1 2 SPI_PCH_DO
SPI_WP#_SEL 2 1 GND DI/IO0 R901 33_0402_5%
@ RH186 0_0402_5% W25Q32FVSSIQ_SO8
A A
SPI@
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
D D
UH1I LPT_PCH_M_EDS
AW31 B37
<44> USB3RN3 PERN1/USB3RN3 USB2N0 USBP0- <40>
<44> USB3RP3
AY31
PERP1/USB3RP3 USB2P0
D37
USBP0+ <40> ----->Rear Side
MLK DOCK -----> USB2N1
A38
USBP1- <41>
<44> USB3TN3
BE32
PETN1/USB3TN3 USB2P1
C38
USBP1+ <41> ----->Right Side Top
BC32 A36
<44> USB3TP3 PETP1/USB3TP3 USB2N2 USBP2- <42>
USB2P2
C36
USBP2+ <42> ----->Right Side bottom
AT31 A34
<33> PCIE_PRX_GLANTX_N2 PERN2/USB3RN4 USB2N3 USBP3- <44>
<33> PCIE_PRX_GLANTX_P2
AR31
PERP2/USB3RP4 USB2P3
C34
USBP3+ <44> ----->DOCK
10/100/1G LAN ---> B33
USB2N4 USBP4- <37>
<33> PCIE_PTX_GLANRX_N2
BD33
PETN2/USB3TN4 USB2P4
D33
USBP4+ <37> ----->WLAN/WIMAX
BB33 F31
<33> PCIE_PTX_GLANRX_P2 PETP2/USB3TP4 USB2N5 G31
USBP5- <38> ----->WWAN/UWB
USB2P5 USBP5+ <38>
K31
AW33 USB2N6 L31
USBP6- <44> ----->DOCK
<37> PCIE_PRX_WLANTX_N3 PERN_3 USB2P6 USBP6+ <44>
AY33 G29
WLAN (JMINI2)--->
<37> PCIE_PRX_WLANTX_P3 PERP_3 USB2N7 H29
USBP7- <35> ----->USH
USB2P7 USBP7+ <35>
BE34 A32
<37> PCIE_PTX_WLANRX_N3 BC34 PETN_3 USB2N8 C32
USBP8- <37> ----->WPAN
<37> PCIE_PTX_WLANRX_P3 PETP_3 USB2P8 USBP8+ <37>
A30
AT33 USB2N9 C30
USBP9- <43> ----->Left Side USBRBIAS
C <32> PCIE_PRX_EMBTX_N4 PERN_4 USB2P9 USBP9+ <43> C
AR33 B29
<32> PCIE_PRX_EMBTX_P4 PERP_4 USB2N10 USBP10- <39>
----->Express Card
22.6_0402_1%
E3 Module Bay---> D29
USB2P10 USBP10+ <39>
1
BE36 A28
<32> PCIE_PTX_EMBRX_N4 PETN_4 USB2N11
RH187
BC36 C28
<32> PCIE_PTX_EMBRX_P4 PETP_4 USB2P11 G26
USB2N12 USBP12- <28>
----->Camera
PCIe
AW36
USB
F26
PERN_5 USB2P12 USBP12+ <28>
AV36 F24
USBP13- <28>
2
PERP_5 USB2N13
USB2P13
G24
USBP13+ <28> ----->Touch
BD37
BB37 PETN_5
PETP_5 AR26
USB3RN1 USB3RN1 <40>
AY38 AP26 CAD NOTE:
<37> PCIE_PRX_WPANTX_N6 PERN_6 USB3RP1 USB3RP1 <40>
AW38 BE24
Pink Pather (JMINI3)--->
<37> PCIE_PRX_WPANTX_P6 PERP_6 USB3TN1 BD23
USB3TN1 <40> ----->Rear Side Route single‐end 50‐ohms and max 500‐mils length.
USB3TP1 USB3TP1 <40> Avoid routing next to clock pins or under stitching capacitors.
BC38 AW26
<37> PCIE_PTX_WPANRX_N6 PETN_6 USB3RN2 USB3RN2 <41>
BE38 AV26 Recommended minimum spacing to other signal traces is 15 mils.
<37> PCIE_PTX_WPANRX_P6 PETP_6 USB3RP2 USB3RP2 <41>
BD25
AT40 USB3TN2 BC24
USB3TN2 <41> ----->Right Side Top
<39> PCIE_PRX_EXPTX_N7 PERN_7 USB3TP2 USB3TP2 <41>
AT39 AW29
<39> PCIE_PRX_EXPTX_P7 PERP_7 USB3RN5 USB3RN5 <42>
EXPRESS Card---> AV29
USB3RP5 USB3RP5 <42>
<39> PCIE_PTX_EXPRX_N7
BE40
PETN_7 USB3TN5
BE26
USB3TN5 <42> ----->Right Side bottom
BC40 BC26
<39> PCIE_PTX_EXPRX_P7 PETP_7 USB3TP5 USB3TP5 <42>
AR29
USB3RN6 USB3RN6 <43>
AN38 AP29
<36> PCIE_PRX_MMITX_N8
AN39 PERN_8 USB3RP6 BD27
USB3RP6 <43> ----->Left Side
<36> PCIE_PRX_MMITX_P8 PERP_8 USB3TN6 USB3TN6 <43>
BE28
USB3TP6 USB3TP6 <43>
MMI ---> BD42
<36> PCIE_PTX_MMIRX_N8 BD41 PETN_8 K24 USBRBIAS
<36> PCIE_PTX_MMIRX_P8 PETP_8 USBRBIAS# K26
USBRBIAS
+1.5V_RUN 1 2 PCH_PCIE_IREF BE30 M33 PAD~D T82 @

@ RH188 0_0402_5% PCIE_IREF TP24 L33 PAD~D T83 @
B TP23 +3.3V_ALW_PCH B
@ T84 PAD~D BC30 P3 USB_OC0#
TP11 OC0#/GPIO59 USB_OC0# <15,40,41,42>
V1 USB_OC1# RPH3
OC1#/GPIO40 USB_OC1# <15,42>
U2 USB_OC2# USB_OC0# 4 5
OC2#/GPIO41 USB_OC2# <15>
@ T85 PAD~D BB29 P1 USB_OC3# USB_OC1# 3 6
TP6 OC3#/GPIO42 USB_OC3# <15>
M3 USB_OC4# USB_OC3# 2 7
OC4#/GPIO43 USB_OC4# <15,43>
T1 USB_OC5# USB_OC4# 1 8
OC5#/GPIO9 USB_OC5# <15>
+1.5V_RUN 1 2 PCH_PCIE_RCOMP BD29 N2 USB_OC6#
PCIE_RCOMP OC6#/GPIO10 USB_OC6# <15>
RH192 7.5K_0402_1% M1 SIO_EXT_SMI# 10K_8P4R_5%
OC7#/GPIO14 SIO_EXT_SMI# <15,46>
9 OF 11 RPH1
USB_OC5# 4 5
DH82LPMS-QCG1-B0_FCBGA695~D USB_OC6# 3 6
SIO_EXT_SMI# 2 7
USB_OC2# 1 8
10K_8P4R_5%
A A
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
+PCH_VCCDSW3_3 Support Deep S3 mode
2 1 EC_WAKE# 1 2
LANWAKE# <33,46>
RH216 10K_0402_5% @ RH196 0_0402_5%
+3.3V_RUN UH1F LPT_PCH_M_EDS
2 1 AT8
<46> SIO_EXT_SCI# BMBUSY#/GPIO0
@ RH195 0_0402_5% +3.3V_RUN
USH_DET# F13
<35> USH_DET# TACH1/GPIO1
2 1 USH_DET# RPH14
RH202 100K_0402_5% PCH_GPIO06 A14 SIO_A20GATE 1 8
<17> PCH_GPIO06 TACH2/GPIO6
D 1 2 PCH_GPIO22 SIO_RCIN# 2 7 D
G15 CPU/Misc 3 6
RH331 10K_0402_5% PCH_GPIO07 TPM_ID0
TACH3/GPIO7 TPM_ID1 4 5
RPH16 SIO_EXT_WAKE# Y1
<15,17,45> SIO_EXT_WAKE# GPIO8
8 1 10K_8P4R_5%
7 2 SIO_EXT_SCI# PM_LANPHY_ENABLE K13
<17,33> PM_LANPHY_ENABLE LAN_PHY_PWR_CTRL/GPIO12
6 3 PCH_GPIO34 AN10 SIO_A20GATE
TP14 SIO_A20GATE <46>
5 4 PCH_GPIO35 PCH_GPIO15 AB11
GPIO15 AY1 PAD~D T86 @
10K_8P4R_5% MCARD_PCIE_SATA# AN2 PECI
<15,45> MCARD_PCIE_SATA# SATA4GP/GPIO16 AT6 SIO_RCIN#
GPIO RCIN# SIO_RCIN# <46>
DGPU_PWROK C14
TACH0/GPIO17 AV3 H_CPUPWRGD +1.05V_RUN
PROCPWRGD H_CPUPWRGD <7>
RPH13 PCH_GPIO22 BB4
<35> PCH_GPIO22 SCLOCK/GPIO22
8 1 PCH_GPIO07 AV1 PCH_THRMTRIP#_R 2 1
7 2 PCH_GPIO69 PCH_GPIO24 Y10 THRMTRIP# RH206 56_0402_5%
GPIO24
0.1U_0402_25V6
6 3 PCH_GPIO71 AU4 CPU_PLTRST#
PLTRST_PROC# CPU_PLTRST# <7>
5 4 PCH_GPIO70 EC_WAKE# R11 1
<46> EC_WAKE# GPIO27 N10
VSS
CH17
10K_8P4R_5% SLP_ME_CSW_DEV# AD11
<45> SLP_ME_CSW_DEV# GPIO28
PCH_GPIO34 AN6 2
GPIO34
PCH_GPIO35 AP1
<15> PCH_GPIO35 GPIO35/NMI#
1 2 PCH_GPIO22 PCH_GPIO36 AT3
<15> PCH_GPIO36 SATA2GP/GPIO36
RH332 @ 100K_0402_5%
PCH_GPIO37 AK1
<15> PCH_GPIO37 SATA3GP/GPIO37
TPM_ID0 AT7
SLOAD/GPIO38
TPM_ID1 AM3 A2
SDATAOUT0/GPIO39 VSS A41
AN4 VSS A43
<31> FFS_INT2 SDATAOUT1/GPIO48 VSS A44
C
PCH_GPIO49 AK3 VSS B1 C
<15> PCH_GPIO49 SATA5GP/GPIO49 VSS B2
KB_DET# U12 VSS B44
<47> KB_DET# GPIO57 VSS CRB1.2 already change to GND directly at UH1.A44, B45, BD1 pins
B45
+3.3V_ALW_PCH CONTACTLESS_DET# C16 VSS BA1
<17,35> CONTACTLESS_DET# TACH4/GPIO68 VSS BC1
PCH_GPIO69 D13 VSS BD1
TACH5/GPIO69 VSS BD2
RPH15 PCH_GPIO70 G13 VSS BD44
8 1 PCH_GPIO15 TACH6/GPIO70 VSS BD45
7 2 KB_DET# PCH_GPIO71 H15 VSS BE2
6 3 PCH_GPIO24 TACH7/GPIO71 VSS BE3
5 4 DGPU_PWROK VSS D1
BE41 VSS E1
10K_8P4R_5% BE5 VSS NCTF VSS E45
C45 VSS VSS A4
A5 VSS VSS
VSS
6 OF 11
+3.3V_ALW_PCH
+3.3V_RUN
2
4.7K_0402_5%
1 2 MCARD_PCIE_SATA#
RH222
RH224 10K_0402_5%
2 1 PCH_GPIO49
RH225 10K_0402_5%
1
SLP_ME_CSW_DEV# 2 1 MCARD_PCIE_SATA#
@ RH226 10K_0402_5%
B 2 1 PCH_GPIO49 B
1
1K_0402_1%
@ RH227 10K_0402_5%
@ RH223
2
+3.3V_RUN
Config GPIO16,49 2 1 PCH_GPIO36
PLL ON DIE VR ENABLE @ RH228 1K_0402_1%
1 2 PCH_GPIO37
USB X4,PCIEX8,SATAX6 11 RH229 1K_0402_1%
ENABLED ‐ HIGH(DEFAULT) 2 1 PCH_GPIO36
DISABLED ‐ LOW * USB X6,PCIEX8,SATAX4 01 RH230 10K_0402_5%
2 1 PCH_GPIO37
@ RH231 10K_0402_5%
SATA2GP/GPIO36 , SATA3GP/GPIO37 SAMPLED AT RISING EDGE OF PWROK.
WEAK INTERNAL PULL‐DOWN.(WEAK INTERNAL PULL‐DOWN IS DISABLED AFTER
PLRST_N DE‐ASSERTS).
NOTE: THIS SIGNAL SHOLD NOT BE PULLED HIGH WHEN STRAP IS SAMPLED.
A A
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
LH1
+VCCADAC 2 1 +1.5V_RUN
BLM18PG181SN1D_2P
0.01U_0402_16V7K
0.1U_0402_25V6
10U_0603_6.3V6M
D D
1 1 1
CH18
CH19
CH20
2 2 2
PCH Power Rail Table
UH1G LPT_PCH_M_EDS
+1.05V_RUN P45 Voltage Rail Voltage S0 Iccmax Current (A)

VCCADAC1_5
AA24 P43 +1.5V_RUN
AA26 VCC CRT DAC VSS
VCC VCC 1.05V 1.138 A
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 AD20 M31 +3.3V_RUN
AD22 VCC VCCADACBG3_3 +1.05V_RUN
VCC
CH21
CH22
CH23
CH24
AD24 VCCIO 1.05V 3.629 A
VCC
1U_0402_6.3V6K
AD26 BB44
2 2 2 2 AD28 VCC VCCVRM
VCC FDI 1
AE18 AN34 VCCADAC1_5 1.5V 0.070 A
VCC VCCIO +3.3V_RUN
CH25
AE20
AE22 VCC AN35
AE24 VCC VCCIO 2
VCC VCCADAC3_3 3.3V 0.0133 A
AE26 R30
VCC HVCMOS VCC3_3_R30
0.1U_0402_25V6
AG18 R32
AG20 VCC VCC3_3_R32
VCC 1 VCCCLK 1.05V 0.306 A
AG22 Y12 +3.3V_ALW_PCH
VCC DCPSUS1
CH27
AG24
Y26 VCC AJ30
VCC VCCSUS3_3 2
VCCCLK3_3 3.3V 0.055 A
Core
AJ32
VCCSUS3_3
+1.05V_M AJ26 VCCVRM 1.5V 0.183 A
C +PCH_VCCDSW U14 USB3 DCPSUS3 AJ28 C
AA18 DCPSUSBYP DCPSUS3 AK20
VCCASW VCCIO +1.05V_RUN
U18 AK26 VCC3_3 3.3V 0.133 A
VCCASW VCCVRM
22U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
U20 AK28 +1.5V_RUN

U22 VCCASW VCCVRM
1 1 1 VCCASW
U24 BE22 +1.5V_RUN VCCASW 1.05V 0.67 A
VCCASW VCCVRM
CH28
CH29
CH30
V18 PCIe/DMI
V20 VCCASW AK18
2 2 2 VCCASW VCCIO +1.05V_RUN
V22 VCCSUSHDA 3.3V 0.01 A
V24 VCCASW AN11
VCCASW VCCVRM +1.5V_RUN
Y18
Y20 VCCASW SATA
AK22
VCCASW VCCIO VCCSPI 3.3V 0.022 A
Y22 +1.05V_RUN
VCCASW AM18
VCCIO AM20
VCCIO VCCSUS3_3 3.3V 0.261 A
AM22
VCCMPHY VCCIO AP22
VCCIO
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
AR22 1 1 1 1 1 VCCDSW3_3 3.3V 0.015 A
VCCIO AT22
VCCIO
CH34
CH35
CH36
CH37
CH38
7 OF 11
2 2 2 2 2
V_PROC_IO 1.05V 0.004 A
1 2 +PCH_VCCDSW
RH232 5.11_0402_1%
+PCH_VCCDSW_R
B B
1U_0402_6.3V6K
1
CH40
A A
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
Support DEEP SX: populated RH238, de-populated RH237
+3.3V_ALW_PCH
+PCH_VCCDSW3_3
0.1U_0402_25V6
2 1
UH1H LPT_PCH_M_EDS
0_0603_5% RH237 @
+3.3V_ALW_PCH
0.1U_0402_25V6
1 2 1 +3.3V_ALW
+3.3V_ALW_PCH
CH43
0_0603_5% RH238 @
1
CH44
R24 R20
R26 VCCSUS3_3 VCCSUS3_3 R22 2
D D
VCCSUS3_3 VCCSUS3_3
0.1U_0402_25V6
R28
+1.05V_RUN U26 VCCSUS3_3 GPIO/LPC 2
1 VCCSUS3_3 A16 +PCH_VCCDSW3_3
CH45 M24 VCCDSW3_3 +3.3V_RUN
VSS AA14 +PCH_VCCSST 1 2
2 +3.3V_RUN DCPSST
0.1U_0402_25V6
U35 CH46 0.1U_0402_25V6
VCCUSBPLL AE14
1 PCH Power Rail Table
USB
L24 VCC3_3 AF12
VCC3_3 VCC3_3
CH47
0.1U_0402_25V6
AG14
VCC3_3 +3.3V_ALW_PCH
0.1U_0402_25V6
U30 1
2 +1.05V_RUN V28 VCCIO
1 VCCIO Voltage Rail Voltage S0 Iccmax Current (A)
CH48
CH49
V30 U36 +1.05V_RUN
Y30 VCCIO VCCIO
VCCIO 2
2
VCC 1.05V 1.138 A
0.1U_0402_25V6
+1.5V_RUN Y35 Azalia
DCPSUS2
1U_0402_6.3V6K
1 A26 1
AF34 VCCSUSHDA
VCCVRM VCCIO 1.05V 3.629 A
CH50
CH51
+RTC_CELL
10U_0603_6.3V6M
1 +PCH_VCC AP45 K8 +3.3V_VCCPRTCSUS
2 VCC VCCSUS3_3 2
VCCADAC1_5 1.5V 0.070 A
CH52
+PCH_VCCCLK Y32 A6
VCCCLK VCCRTC
2 RTC
0.1U_0402_25V6
0.1U_0402_25V6
1U_0402_6.3V6K
+PCH_VCCCLK3_3 M29 P14 +PCH_DCPRTC CH54 VCCADAC3_3 3.3V 0.0133 A
VCCCLK3_3 DCPRTC P16 1 2
DCPRTC 1 1 1
L29
VCCCLK3_3
CH55
CH56
CH57
0.1U_0402_25V6 VCCCLK 1.05V 0.306 A
L26 AJ12 +VCCIO2PCH
M26 VCCCLK3_3 V_PROC_IO AJ14 +3.3V_M 2 2 2
CPU
VCCCLK3_3 V_PROC_IO
VCCCLK3_3 3.3V 0.055 A
U32
VCCCLK3_3
1U_0402_6.3V6K
ICC
V32 AD12
VCCCLK3_3 SPI VCCSPI
VCCVRM 1.5V 0.183 A
+PCH_VCCCLK AD34 1
VCCCLK P18 +PCH_VCCCFUSE
C VCC C
CH59
AA30 P20 VCC3_3 3.3V 0.133 A
AA32 VCCCLK VCC
VCCCLK L17 2
VCCASW +1.05V_M
AD35 VCCASW 1.05V 0.67 A
VCCCLK R18
AG30 VCCASW +VCCIO2PCH
AG32 VCCCLK
VCCCLK VCCSUSHDA 3.3V 0.01 A
AW40 +1.5V_RUN
AD36 VCCVRM
+1.05V_RUN VCCCLK +3.3V_RUN
0.1U_0402_25V6
0.1U_0402_25V6
1U_0402_6.3V6K
AK30 VCCSPI 3.3V 0.022 A
AE30 VCC3_3
Thermal 1 1 1
AE32 VCCCLK AK32
VCCCLK VCC3_3
0.1U_0402_25V6
CH60
CH61
CH62
1 2 +PCH_VCC VCCSUS3_3 3.3V 0.261 A
@ RH246 0_0603_5% 1 2 2 2
10U_0603_6.3V6M
1U_0402_6.3V6K
8 OF 11
@ CH63
CH65
1 1 DH82LPMS-QCG1-B0_FCBGA695~D VCCDSW3_3 3.3V 0.015 A
CH64
2 2
V_PROC_IO 1.05V 0.004 A
Place near pin AP45
+PCH_VCCCFUSE 2 1 +3.3V_RUN
+1.05V_RUN +PCH_VCCCLK @ RH242 0_0805_5%
1U_0402_6.3V6K
1 2 1
@ RH244 0_0805_5%
1U_0402_6.3V6K
1U_0402_6.3V6K
CH66
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2
@ CH68
1 1 1 1 1
CH67
CH69
CH70
CH71
B B
2 2 2 2 2
Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36

Place near pin AG30,AG32,AE30,AE32
+3.3V_VCCPRTCSUS 2 1 +3.3V_ALW_PCH
+3.3V_RUN +PCH_VCCCLK3_3 @ RH240 0_0603_5%
2 1 +3.3V_ALW
1U_0402_6.3V6K
1 @ RH241 0_0603_5%
1 2
CH53
@ RH245 0_0805_5%
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1
CH72
CH73
CH74
CH75
2 2 2 2
Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32
A A
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
D D
UH1J LPT_PCH_M_EDS
AL34 K39 UH1K LPT_PCH_M_EDS

AL38 VSS VSS L2
AL8 VSS VSS L44 AA16 B19
AM14 VSS VSS M17 AA20 VSS VSS B23
AM24 VSS VSS M22 AA22 VSS VSS B27
AM26 VSS VSS N12 AA28 VSS VSS B31
AM28 VSS VSS N35 AA4 VSS VSS B35
AM30 VSS VSS N39 AB12 VSS VSS B39
AM32 VSS VSS N6 AB34 VSS VSS B7
AM16 VSS VSS P22 AB38 VSS VSS BA40
AN36 VSS VSS P24 AB8 VSS VSS BD11
AN40 VSS VSS P26 AC2 VSS VSS BD15
AN42 VSS VSS P28 AC44 VSS VSS BD19
AN8 VSS VSS P30 AD14 VSS VSS AY36
AP13 VSS VSS P32 AD16 VSS VSS AT43
C AP24 VSS VSS R12 AD18 VSS VSS BD31 C
AP31 VSS VSS R14 AD30 VSS VSS BD35
AP43 VSS VSS R16 AD32 VSS VSS BD39
AR2 VSS VSS R2 AD40 VSS VSS BD7
AK16 VSS VSS R34 AD6 VSS VSS D25
AT10 VSS VSS R38 AD8 VSS VSS AV7
AT15 VSS VSS R44 AE16 VSS VSS F15
AT17 VSS VSS R8 AE28 VSS VSS F20
AT20 VSS VSS T43 AF38 VSS VSS F29
AT26 VSS VSS U10 AF8 VSS VSS F33
AT29 VSS VSS U16 AG16 VSS VSS BC16
AT36 VSS VSS U28 AG2 VSS VSS D4
AT38 VSS VSS U34 AG26 VSS VSS G2
D42 VSS VSS U38 AG28 VSS VSS G38
AV13 VSS VSS U42 AG44 VSS VSS G44
AV22 VSS VSS U6 AJ16 VSS VSS G8
AV24 VSS VSS V14 AJ18 VSS VSS H10
BB25 VSS VSS V43 AJ24 VSS VSS H22
AV40 VSS VSS W2 AJ34 VSS VSS H24
AV6 VSS VSS W44 AJ38 VSS VSS H26
AW2 VSS VSS Y14 AJ6 VSS VSS H31
F43 VSS VSS Y16 AJ8 VSS VSS H36
AY10 VSS VSS Y24 AK14 VSS VSS H40
AY15 VSS VSS Y28 AK24 VSS VSS H7
AY20 VSS VSS Y34 AK43 VSS VSS K10
AY26 VSS VSS Y36 AK45 VSS VSS K15
AY29 VSS VSS Y40 AL12 VSS VSS K20
AY7 VSS VSS Y8 AL2 VSS VSS K29
B11 VSS VSS BC22 VSS VSS K33
B15 VSS BB42 VSS VSS BC28
B VSS VSS VSS B
10 OF 11 11 OF 11
DH82LPMS-QCG1-B0_FCBGA695~D DH82LPMS-QCG1-B0_FCBGA695~D
A A
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW Q83B Battery LED

HDD LED solution for White LED DMN66D0LDW-7_SOT363-6
10K_0402_5%
+5V_ALW 4 3 BAT2_LED#_Q 1 2 BATT_WHITE# <47>
<45> BAT2_LED#
1
R949 1.8K_0402_5%
R932
BATT_YELLOW# <47>
5
MASK_BASE_LEDS#
3
Q74B
2
DMN66D0LDW-7_SOT363-6 Q74A
D59 DMN66D0LDW-7_SOT363-6
4 3 1 2 1 6 2
<15> SATA_ACT#
RB751V40_SC76-2 Q75 1 2 BATT_WHITE_LED# <28>
PDTA114EU_SC70-3 R958 680_0402_5%
2
<45> MASK_SATA_LED# BATT_YELLOW_LED# <28>
1
D D
D62 1 2
1 2 MASK_BASE_LEDS# R934 1.8K_0402_5% SATA_LED <47>
<45> LED_SATA_DIAG_OUT#
RB751V40_SC76-2 Q83A
1 6 BAT1_LED#_Q 1 2
<45> BAT1_LED#
R951 330_0402_5%
PANEL_HDD_LED <28>
2
MASK_BASE_LEDS#
3
Q84B
4 3 2
1 2
Q81 R953 330_0402_5%
PDTA114EU_SC70-3
1
1 2 Q84A LED1 +5V_ALW
SYS_LED_MASK# R938 680_0402_5% Breath LED DMN66D0LDW-7_SOT363-6
1 6 BREATH_LED#_Q 1 2 BREATH_WHITE_LED_SNIFF 1 2
<44,45> BREATH_LED#
R957 220_0402_5%
LTW-193ZDS5_WHITE
Place LED1 close to SW1
2
MASK_BASE_LEDS#
+3.3V_ALW
WLAN LED solution for White LED
100K_0402_5%
+5V_ALW
1
1 2 BREATH_WHITE_LED# <28>
R937
R955 680_0402_5%
3
Q100
L2N7002WT1G_SC-70-3
2
C C
S
D
3 1 2
<37,38,45> WIRELESS_LED#
PWR SW
SW1
POWER_SW#_MB 2 1
G
2
Q79 <35,46> POWER_SW#_MB

MASK_BASE_LEDS# PDTA114EU_SC70-3
1
4 3
SKRBAAE010_4P
1 2
R3671 1.8K_0402_5% WLAN_LED <47> POWER & INSTANT ON SWITCH
+3.3V_ALW
@ C778
1 2
0.1U_0402_25V6
5
VCC
SYS_LED_MASK# 1
<32,33,45> SYS_LED_MASK# IN B 4 MASK_BASE_LEDS#
LID_CL# 2 OUT Y
GND
<45,47> LID_CL# IN A
U58
NL17SZ08DFT2G_SC70-5
3
B B
LED Circuit Control Table

SYS_LED_MASK# LID_CL#
Mask All LEDs (Sniffer Function) 0 X

Mask Base MB LEDs (Lid Closed) 1 0
Do not Mask LEDs (Lid Opened) 1 1
@ H1 @ H2 @ H3 @ H4 @ H5 @ H6 @ H7 @ H8 @ H9 @ H10 @ H11 @ H12

H_3P8 H_3P8 H_3P3 H_3P0 H_3P3 H_3P3 H_3P0 H_3P0 H_3P3 H_3P0 H_3P0 H_3P0
1
@ H13 @ H14 @ H17 @ H18 @ H19 @ H20 @ H21 @ H22
H_3P0 H_3P2 H_2P0N H_2P3 H_2P3 H_3P0 H_3P1X2P1N H_3P3
1
A
Fiducial Mark A
@ FD1 @ FD2 @ FD3 @ FD4

1 1 1 1
FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
2 1
B
SW for MB/DOCK B
+5V_RUN +3.3V_RUN
U6
PCH_CRT_RED 1 16
<16> PCH_CRT_RED R 5V VDD
PCH_CRT_GRN 2
<16> PCH_CRT_GRN G
PCH_CRT_BLU 5 4
<16> PCH_CRT_BLU B VDD
PCH_CRT_HSYNC 6 23
<16> PCH_CRT_HSYNC H_SOURCE VDD
PCH_CRT_VSYNC 7 32
<16> PCH_CRT_VSYNC V_HOURCE VDD
PCH_CRT_DDC_DAT 9
<16> PCH_CRT_DDC_DAT SDA_SOURCE
PCH_CRT_DDC_CLK 10 27 RED_CRT
<16> PCH_CRT_DDC_CLK SCL_SOURCE R1 RED_CRT <43>
25 GREEN_CRT
G1 22 BLUE_CRT GREEN_CRT <43>
CRT_SWITCH 30 B1 20 HSYNC_BUF BLUE_CRT <43>
<45> CRT_SWITCH SEL H1_OUT HSYNC_BUF <43>
18 VSYNC_BUF
V1_OUT 12 DAT_DDC2_CRT VSYNC_BUF <43>
29 SDA1 14 CLK_DDC2_CRT DAT_DDC2_CRT <43>
+3.3V_RUN TEST SCL1 CLK_DDC2_CRT <43>
+3.3V_RUN 1 2 8 26 RED_DOCK
R61 4.7K_0402_5% Reserved R2 24 GREEN_DOCK RED_DOCK <44>
3 G2 21 BLUE_DOCK GREEN_DOCK <44>
11 GND B2 19 HSYNC_DOCK BLUE_DOCK <44>
28 GND H2_OUT 17 VSYNC_DOCK HSYNC_DOCK <44>
31 GND V2_OUT 13 DAT_DDC2_DOCK VSYNC_DOCK <44>
33 GND SDA2 15 CLK_DDC2_DOCK DAT_DDC2_DOCK <44>
GPAD SCL2 CLK_DDC2_DOCK <44>
TS3V713ELRTGR_TQFN32_6X3
+3.3V_RUN +5V_RUN
0.01U_0402_16V7K
0.01U_0402_16V7K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
SEL1/SEL2 Chanel Source
1 1 1 1 1 1
0 A=B1 MB @ @
C25
C26
C27
C28
C29
C30
1 A=B2 APR/SPR 2 2 2 2 2 2
A A
PROPRIETARY NOTE:
Title
B
2 1
2 1
1 2
@ R62 0_0402_5%
EMC@ L1
2 1 TMDSB_CPU_CLK#_C 4 3 TMDSE_CON_CLK#
<9> TMDSB_CPU_CLK# 4 3
C353 0.1U_0402_25V6
TMDSB_CPU_P2_C R452 1 2 470_0402_5% HDMI_OB 2 1 TMDSB_CPU_CLK_C 1 2 TMDSE_CON_CLK

<9> TMDSB_CPU_CLK 1 2
TMDSB_CPU_N2_C R450 1 2 470_0402_5% C352 0.1U_0402_25V6
TMDSB_CPU_P1_C R448 1 2 470_0402_5% CMMI21T-900Y-N_0805_4P
1.8P_0402_50V8
1.8P_0402_50V8
TMDSB_CPU_N1_C R449 1 2 470_0402_5% 1 @ 1 @
TMDSB_CPU_P0_C R454 1 2 470_0402_5% 1 2
CE7
CE5
TMDSB_CPU_N0_C R453 1 2 470_0402_5% @ R63 0_0402_5%
TMDSB_CPU_CLK_C R456 1 2 470_0402_5%
TMDSB_CPU_CLK#_C R455 1 2 470_0402_5% 2 2
1 2
1
D @ R64 0_0402_5%
+3.3V_RUN R458 1 2 10K_0402_5% 2 Q26
G L2N7002WT1G_SC70-3 EMC@ L2
S 2 1 TMDSB_CPU_P0_C 1 2 TMDSE_CON_P0
<9> TMDSB_CPU_P0
3
C351 0.1U_0402_25V6 1 2
2 1 TMDSB_CPU_N0_C 4 3 TMDSE_CON_N0
<9> TMDSB_CPU_N0 4 3
C350 0.1U_0402_25V6
CMMI21T-900Y-N_0805_4P
1.8P_0402_50V8
1.8P_0402_50V8
B @ @ B
1 1
1 2
CE17
CE16
@ R68 0_0402_5%
2 2
1 2
@ R71 0_0402_5%
EMC@ L3
2 1 TMDSB_CPU_P1_C 1 2 TMDSE_CON_P1
<9> TMDSB_CPU_P1 1 2
C347 0.1U_0402_25V6
C346 0.1U_0402_25V6
CMMI21T-900Y-N_0805_4P
1.8P_0402_50V8
1.8P_0402_50V8
1 @ 1 @
1 2
CE13
CE18
@ R74 0_0402_5%
2 2
1 2
+3.3V_RUN @ R77 0_0402_5%
EMC@ L4
HDMI_CEC 2 1 2 1 TMDSB_CPU_P2_C 1 2 TMDSE_CON_P2
<9> TMDSB_CPU_P2 1 2
10K_0402_5% R73 C349 0.1U_0402_25V6
C348 0.1U_0402_25V6
CMMI21T-900Y-N_0805_4P
1.8P_0402_50V8
1.8P_0402_50V8
1 @ 1 @
1 2
CE15
CE14
@ R78 0_0402_5%
2 2
+5V_RUN +5V_RUN
+VDISPLAY_VCC
+3.3V_RUN 2
1
RB751V40_SC76-2
@ D65
0.1U_0402_25V6
10U_0603_6.3V6M
R1163 @
IN
0_0402_5%
EMC@ U89 1 1
@ C46
C47
Q120A AP2330W-7_SC59-3
1
2
2
1 6 PCH_DDPB_CTRLCLK_R 1 2 +5V_HDMI_DDC 2 2
GND
OUT
<16> PCH_DDPB_CTRLCLK
R1153 2.2K_0402_5%
5
3
JHDMI1
4 3 PCH_DDPB_CTRLDATA_R 1 2 HDMI_HPD_SINK 19
<16> PCH_DDPB_CTRLDATA HP_DET
R1152 2.2K_0402_5% 18
Q120B 17 +5V
DMN66D0LDW-7_SOT363-6 PCH_DDPB_CTRLDATA_R 16 DDC/CEC_GND
PCH_DDPB_CTRLCLK_R 15 SDA
14 SCL
A +3.3V_RUN HDMI_CEC 13 Reserved A
TMDSE_CON_CLK# 12 CEC 20
11 CK- GND 21
TMDSE_CON_CLK 10 CK_shield GND 22
CK+ GND
1M_0402_5%
TMDSE_CON_N0 9 23
D0- GND
2
8
D0_shield
R1168
TMDSE_CON_P0 7
TMDSE_CON_N1 6 D0+
5 D1-
D1_shield
2
G
TMDSE_CON_P1 4
1
TMDSE_CON_N2 3 D1+
3 1 HDMI_HPD_SINK 1 2 2 D2-
<16> HDMIB_PCH_HPD R1128 20K_0402_5% TMDSE_CON_P2 1 D2_shield
S
D2+
CONCR_099ATAC19NBLCNF
Q121 CONN@
L2N7002WT1G_SC70-3
PROPRIETARY NOTE:
Title
B
2 1
5 4 3 2 1
+3.3V_RUN_EDP +3.3V_RUN_EDP
D Power Consumption: D
2
2
R105
4.7K_0402_5% EEPROM
R107 @
4.7K_0402_5% EEPROM
Pin5 (DPV33) < 20mA
Pin 11 (DPV12) < 100mA
1
1
MIIC_SCL0 MIIC_SDA0
Pin 15 (SWR_VCCK) < 100mA (layout trace > 60 mil)
Pin 17 (SWR_LX) < 600mA (layout trace > 60 mil)
2
2
R106 @ R108 Pin 18 (SWR_VDD) < 200mA (layout trace > 40 mil)
4.7K_0402_5% ROMLESS 4.7K_0402_5% ROMLESS
Pin 22 (PVCC) < 50 mA
Pin 43 (VCCK) < 50mA
1
+3.3V_RUN +3.3V_RUN_EDP
30mil @ PJP67
30mil
1 2
C U27 C
PAD-OPEN1x1m
RTD2136S
+AVCC33 35
+3.3V_RUN_EDP 22 TXOC+ 36 CVT_LVDS_ACLK+ <28>
PVCC TXOC- CVT_LVDS_ACLK- <28>
10U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
1 1 1 @ R3881 2 10_0805_5% +DVCC33 40 mils 18 41

SWR_VDD TXO0+ 42 CVT_LVDS_A0+ <28>
TXO0- CVT_LVDS_A0- <28>
C106
C107
C108
PWR
@ R3882 2 10_0805_5% +AVCC33 5
DP_V33 39
2 2 2 +SWR_V12 @ R3883 1 20_0805_5% +SW_LX 60 mils 17 TXO1+ 40 CVT_LVDS_A1+ <28>
SWR_LX TXO1- CVT_LVDS_A1- <28>
60 mils 15 37
SWR_VCCK TXO2+ 38 CVT_LVDS_A2+ <28>
43 TXO2- CVT_LVDS_A2- <28>
Close to 5 pin VCCK
60 mils 33
11 TXO3+ 34
+SWR_V12 DP_V12 TXO3-
LVDS
10U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
25
C100 2 1 0.1U_0402_25V6 EDP_CPU_LANE_P0_C 7 TXEC+ 26 CVT_LVDS_BCLK+ <28>
1 1 1 1 <9> EDP_CPU_LANE_P0 LANE0P TXEC- CVT_LVDS_BCLK- <28>
C101 2 1 0.1U_0402_25V6 EDP_CPU_LANE_N0_C 8
<9> EDP_CPU_LANE_N0 LANE0N
C109
C110
C111
C112
31
C103 2 1 0.1U_0402_25V6 EDP_CPU_LANE_P1_C 9 TXE0+ 32 CVT_LVDS_B0+ <28>
2 2 2 2 <9> EDP_CPU_LANE_P1 LANE1P TXE0- CVT_LVDS_B0- <28>
C118 2 1 0.1U_0402_25V6 EDP_CPU_LANE_N1_C 10
<9> EDP_CPU_LANE_N1 LANE1N
DP
29
C104 2 1 0.1U_0402_25V6 EDP_CPU_AUX_C 4 TXE1+ 30 CVT_LVDS_B1+ <28>
<9> EDP_CPU_AUX AUX-CH_P TXE1- CVT_LVDS_B1- <28>
C105 2 1 0.1U_0402_25V6 EDP_CPU_AUX#_C 3
<9> EDP_CPU_AUX# AUX-CH_N
Close to 11 pin Close to 43 pin 27
CPU_EDP_HPD 1 TXE2+ 28 CVT_LVDS_B2+ <28>
<9> CPU_EDP_HPD DP_HPD TXE2- CVT_LVDS_B2- <28>
B 23 B
1 2 TXE3+ 24
+DVCC33 R114 100K_0402_5% TXE3-
21
<16> BIA_PWM_PCH PWMIN
10U_0603_6.3V6M
0.1U_0402_25V6
22U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
1 2 2 46 LCD_EDID_CLK
@ R100 1 2 0_0402_5% 12 TESTMODE MIICSCL1 45 LCD_EDID_DATA LCD_EDID_CLK <28>
1 1 1 1 1 DP_REXT MIICSDA1 LCD_EDID_DATA <28>
OTHERS
R101 12K_0402_1%
C113
C114
C115
C116
C117
20 LCD_ENVDD_CVT
PANEL_VCC 19 BIA_PWM_CVT LCD_ENVDD_CVT <28>
2 2 2 2 2 MIIC_SCL0 48 PWMOUT 44 PANEL_BKEN_CVT BIA_PWM_CVT <28>
MIIC_SDA0 47 MIICSCL0 BL_EN PANEL_BKEN_CVT <28>
MIICSDA0
Close to 18 pin Close to 22 pin DDR_XDP_WAN_SMBCLK 13 6

<7,13,14,15,18,31> DDR_XDP_WAN_SMBCLK CIICSCL1 DP_GND
DDR_XDP_WAN_SMBDAT 14
<7,13,14,15,18,31> DDR_XDP_WAN_SMBDAT CIICSDA1
GND
16 +UTLGND 1 2
GND @ R104 0_0402_5%
49
PAD
RTD2136S-CG_QFN48_6X6
Symbol need to update

1. RTD2136S:SA00004NW10 Populated R102, R103, R107; De-populated R108
*** 2. RTD2136R SA000067100 : De-Populated R102, R103, R107; Populate R108;
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SCHEMATIC,MB LA-9931P
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. B
4019MV
Date: Wednesday, July 17, 2013 Sheet 27 of 62
5 4 3 2 1
5 4 3 2 1
LCD Power
+LCDVDD
+3.3V_ALW
JLVDS1
+5V_ALW for panel side LED power @ C455
10U_0603_6.3V6M U148
1 +5V_ALW 1 2 1
GND 2 VOUT 5
BATT_WHITE_LED BATT_WHITE_LED# <24> VIN
3
BATT_YELLOW_LED BATT_YELLOW_LED# <24>
4 D7 2
BREATH_WHITE_LED BREATH_WHITE_LED# <24> GND
5 +BL_PWR_SRC 4
VR_SRC 6 1 2 2 SS
D VR_SRC <27> LCD_ENVDD_CVT D
7 @ C246 0.1U_0603_50V7K 1 3
VR_SRC 8 EN
NC PANEL_HDD_LED <24>
9 DISP_ON 3 APL3512ABI-TRG_SOT23-5
DISP_ON/OFF# <45> LCD_VCC_TEST_EN
100K_0402_5%
10 1 2 BIA_PWM_LVDS
PWM
1
11 @ R3762 0_0603_5%
CONNTST_GND 12 BAT54CW_SOT323-3
VR_GND
R3737
13
VR_GND 14
VR_GND 15
CVT_LVDS_BCLK+ <27>
2
LCD_B_CLK+ 16
LCD_B_CLK- CVT_LVDS_BCLK- <27>
17
GND 18
LVDS_B2+ CVT_LVDS_B2+ <27>
19
LVDS_B2- CVT_LVDS_B2- <27>
20
21
22
23
24
GND 25
LVDS_A_CLK+ CVT_LVDS_ACLK+ <27>
26
LVDS_A_CLK- CVT_LVDS_ACLK- <27>
27
GND 28
LVDS_A2+ CVT_LVDS_A2+ <27>
29
LVDS_A2- CVT_LVDS_A2- <27>
30
31
32
33
34 LCD_EDID_DATA
EDID_DATA LCD_EDID_DATA <27>
46 35 LCD_EDID_CLK
MGND6 EDID_CLK LCD_EDID_CLK <27>
45 36 LCD_TST
MGND5 BIST LCD_TST <45>
44 37 +3.3V_RUN
43 MGND4 V_EDID 38
42 MGND3 LCD_VDD 39
MGND2 LCD_VDD +LCDVDD
41 40
MGND1 CONNTST LCD_CBL_DET# <16>
C ACES_59003-04006-001 +LCDVDD FDC654P: P CHANNAL C
CONN@
@ U56
5 @ C727
1 2 LCD Backlight +PWR_SRC
Q21
FDC654P-G_SSOT-6 +BL_PWR_SRC
0.1U_0402_25V6 6
0.1U_0603_50V7K
NL17SZ08DFT2G_SC70-5 D9 4 5
S
1
VCC
1 2
IN B
1000P_0402_50V7K
C296
BIA_PWM_LVDS 4 2 1
OUT Y BIA_PWM_CVT <27>
100K_0402_5%
G
2 1 1
GND
IN A
1
2
3
10K_0402_5%
C297
3
BIA_PWM_EC <46>
R422
3
R1137
+3.3V_RUN BAT54CW_SOT323-3
2
1 2 LCD_EDID_DATA 2
R159 2.2K_0402_5%
1 2 LCD_EDID_CLK 1 2 PWR_SRC_ON
R160 2.2K_0402_5% @ R429 0_0402_5% Q22
+3.3V_RUN L2N7002WT1G_SC-70-3
Place near to JLVDS1
@ C725 1 2 1 3
S
1 2 R423 47K_0402_5%
0.1U_0402_25V6 R1139
G
2
5
+LCDVDD +BL_PWR_SRC 1 2
D10 100K_0402_5%
VCC
0.1U_0402_25V6
0.1U_0603_50V7K
1
IN B PANEL_BKEN_CVT <27> <46> EN_INVPWR
1 2 4
OUT Y
@ C298
@ C247
1 DISP_ON 1 2 Panel backlight power control by EC
GND
IN A PANEL_BKEN_PCH <16>
100K_0402_5%
3
PANEL_BKEN_EC <45>
1
2 U54
3
2
R1138
BAT54CW_SOT323-3
B Close to JLVDS1.42,43 Close to JLVDS1.42,43 B
2
+5V_RUN +5V_TSP +5V_RUN

Touch Screen Connector
@ Q32
10K_0402_5%
@ R431
PMV65XP_SOT23-3~D
1
For Webcam
0.1U_0402_25V6
1 3
@ C306
1
Place close JTCH1
1 2
G
2
2
@ R427 0_0402_5% +5V_TSP
DLW21HN900SQ2L_0805_4P 2 JTCH1 +5V_TSP

USBP12+ 4 3 USBP12_D+ 1
<19> USBP12+ 4 3 1
0.1U_0402_25V6
2
2
@ C302
3 1
USBP12- 1 2 USBP12_D- USBP13_D- 4 3
<19> USBP12- 1 2 4
1
+CAMERA_VDD D USBP13_D+ 5
EMC@ L10 2 @ Q24 6 5
<45> TOUCH_SCREEN_PD# 6 2
JCAM1 G L2N7002WT1G_SC-70-3
1 2 1 S 7
<16> CAM_MIC_CBL_DET#
3
@ R428 0_0402_5% USBP12_D+ 2 1 8 GND
2 GND
2
USBP12_D- 3
4 3 ACES_50228-0067N-001
5 4
<30> DMIC_CLK 5
6 L11 @ CONN@
7 6 USBP13- 4 3 USBP13_D-
<30> DMIC0 7 <19> USBP13- 4 3
8
9 8 @ D86
Webcam PWR CTRL 10 G1
G2 <19> USBP13+
USBP13+ 1
1 2
2 USBP13_D+ PESD5V0U2BT_SOT23-3~D
1
E-T_3702K-Q08C-07L DLW21SN900SQ2L_0805_4P
CONN@ 1 2
+CAMERA_VDD Q23 +3.3V_RUN @ R433 0_0402_5%
A A
DMG2301U-7_SOT23-3
1 2
1 3 @ R432 0_0402_5%
D
S
0.1U_0402_25V6
10U_0603_6.3V6M
0.1U_0402_25V6
G
2
@ C300
1 1 1
C299
C301
<45> CCD_OFF
2 2 2
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
AUX/DDC GPU for DPC to E‐DOCK
+3.3V_RUN
C356
1 2
D 0.1U_0402_25V6 D
U20
1 14
2 1 DPC_PCH_DOCK_AUX_C 2 BE0 VCC 13
<16> DPC_PCH_DOCK_AUX A0 BE3
C357 0.1U_0402_25V6
3 12 PCH_DDPC_CTRLCLK
<44> DPC_DOCK_AUX B0 A3 PCH_DDPC_CTRLCLK <16>
4 11
2 1 DPC_PCH_DOCK_AUX#_C 5 BE1 B3 10
<16> DPC_PCH_DOCK_AUX# A1 BE2
C360 0.1U_0402_25V6
6 9 PCH_DDPC_CTRLDATA
<44> DPC_DOCK_AUX# B1 A2 PCH_DDPC_CTRLDATA <16>
7 8
GND B2
PI3C3125LEX_TSSOP14
+3.3V_RUN
10K_0402_5%
1
R415
2
DPC_CA_DET#
6
C C
Q331A
DPC_CA_DET 2 DMN66D0LDW-7_SOT363-6
+3.3V_RUN <44> DPC_CA_DET
1
RP1
+5V_RUN
1 8 PCH_DDPC_CTRLCLK C365 @
2 7 PCH_DDPC_CTRLDATA 1 2
3 6 PCH_DDPD_CTRLCLK
4 5 PCH_DDPD_CTRLDATA 0.1U_0402_25V6
1
2.2K_8P4R_5%
NC
2 4
A Y
G
U21 @
TC7SET04FU_SSOP5~D
3
+3.3V_RUN
R491
1
1
2
2
DPD_CA_DET
1M_0402_5%
DPC_CA_DET
AUX/DDC GPU for DPD to E‐DOCK 1
C366
2
R492 1M_0402_5% 0.1U_0402_25V6
U23
1 14
2 1 DPD_PCH_DOCK_AUX_C 2 BE0 VCC 13
<16> DPD_PCH_DOCK_AUX A0 BE3
C367 0.1U_0402_25V6
B 3 12 PCH_DDPD_CTRLCLK B
<44> DPD_DOCK_AUX B0 A3 PCH_DDPD_CTRLCLK <16>
4 11
2 1 DPD_PCH_DOCK_AUX#_C 5 BE1 B3 10
<16> DPD_PCH_DOCK_AUX# A1 BE2
C368 0.1U_0402_25V6
6 9 PCH_DDPD_CTRLDATA
<44> DPD_DOCK_AUX# B1 A2 PCH_DDPD_CTRLDATA <16>
7 8
GND B2
PI3C3125LEX_TSSOP14
+3.3V_RUN
10K_0402_5%
1
R416
2
DPD_CA_DET#
3
Q331B
DPD_CA_DET 5 DMN66D0LDW-7_SOT363-6
<44> DPD_CA_DET
+5V_RUN
4
C369 @
1 2
A A
0.1U_0402_25V6
5
1
P
NC
2 4
A Y U24 @ DELL CONFIDENTIAL/PROPRIETARY
G
TC7SET04FU_SSOP5~D
3
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
2 1
INT_SPK_L+, INT_SPKL_L+ :40 mils trace, keep 10mils spacing
Internal Speakers Header INT_SPK_L‐, INT_SPKL_L‐ :40 mils trace, keep 10mils spacing
INT_SPK_R+, INT_SPKR_R+ :40 mils trace, keep 10mils spacing
INT_SPK_R‐, INT_SPKR_R‐ :40 mils trace, keep 10mils spacing place close to pin27
L77
INT_SPK_L‐, INT_SPKL_L‐ with INT_SPK_R+, INT_SPKR_R+ keep 20mils spacing
JSPK1 CONN@ +VDDA_AVDD 1 2 +5V_RUN
+5V_RUN
10U_0603_6.3V6M
INT_SPK_L+ EMC@ L702 1 2 BLM18PG330SN1D_2P INT_SPKL_L+ 1 BLM15PX600SN1D_2P
1
0.1U_0402_25V6
INT_SPK_L- EMC@ L703 1 2 BLM18PG330SN1D_2P INT_SPKL_L- 2
2
1
INT_SPK_R+ EMC@ L704 1 2 BLM18PG330SN1D_2P INT_SPKR_R+ 3 5 +3.3V_RUN +3.3V_RUN_DVDD 1 C968, C956 place close to pin38
3 G1
C955
INT_SPK_R- EMC@ L705 1 2 BLM18PG330SN1D_2P INT_SPKR_R- 4 6 +DVDD_CORE 1 2 +3.3V_RUN R1095 @
4 G2
C957
10U_0603_6.3V6M
@ PJP60 @ R1658 0_0603_5% 0_0805_5%
10U_0603_6.3V6M
0.1U_0402_25V6
ACES_50273-0040N-001 1 2
2
1 2 2
1
2
1
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
1U_0603_10V7K
0.1U_0402_25V6
C956
JUMP_43X79 1 C959, C958 place close to pin39
C954
C968
C952
C994
0.1U_0402_25V6
10U_0805_10V6K
0.1U_0402_25V6
10U_0805_10V6K
2
2
@ C973
@ C974
@ C975
@ C976
1 1 1 1 1 1
1
2
C958
C960
U74
C959
C961
1 27
DREG_OUT AVDD1 38 +VDDA_AVDD2
2
2 2 2 2 AVDD2/HVDD(3.3) 2 2
3 45 +VDDA_PVDD C961, C960 place close to pin45
DVDD-IO PVDD2 39 +VREFOUT
PVDD1
9 13 AUD_SENSE_A
DVDD Sense A 14 AUD_SENSE_B SLEEVE R1145 1 2 2.2K_0402_5%
Sense B
28 RING2 SLEEVE and RING2 Routing 40 mils. RING2 R1146 1 2 2.2K_0402_5%
PCH_AZ_CODEC_BITCLK 6 LINE1-L/RING2 29 SLEEVE
<15> PCH_AZ_CODEC_BITCLK BIT-CLK LINE1-R/SLEEVE 23 +VREFOUT +VREFOUT
PCH_AZ_CODEC_SDOUT 5 LINE1-VREFO
<15> PCH_AZ_CODEC_SDOUT SDATA-OUT 31 C969 1 2 10U_0603_6.3V6M
10 HPOUT-L/MIC-CAP 33 AUD_HP_OUT_L
<15> PCH_AZ_CODEC_SYNC SYNC AVSS2/HPOUT-L
Place R1096 close to codec 32 AUD_HP_OUT_R
B 1 2 PCH_AZ_SDIN0_R 8 HP-OUT-R B
<15> PCH_AZ_CODEC_SDIN0 R1096 22_0402_5% SDATA-IN 40 INT_SPK_L+
PCH_AZ_CODEC_RST# 11 SPK-L+ 41 INT_SPK_L-
<15> PCH_AZ_CODEC_RST# RESET# SPK-L-
44 INT_SPK_R+ 2 1 1 2
SPK-R+ SPKR <15>
43 INT_SPK_R- C1105 0.1U_0402_25V6 R1119 100K_0402_5%
DAI_12MHZ# 1 2 I2S_MCLK 15 SPK-R- 2 1 1 2
<44> DAI_12MHZ# I2S_MCLK BEEP <46>
R1654 22_0402_5% 12 AUD_PC_BEEP C1106 0.1U_0402_25V6 R1120 100K_0402_5%
DAI_BCLK# 1 2 I2S_BCLK 16 PCBEEP
<44> DAI_BCLK# R1668 22_0402_5% I2S_SCLK 2 DMIC_CLK_L 1 2 1 2
DAI_DO# 1 2 I2S_DO 17 GPIO0/DMIC-CLK 4 EMC@ L13 BLM15BB221SN1D_0402 DMIC_CLK <28> @ R1141 10K_0402_5%
<44> DAI_DO# I2S_DOUT GPIO1/DMIC-DATA DMIC0 <28>
R1097 33_0402_5% 46 1 2
DAI_LRCK# 18 DMIC1/GPIO2 48
Place L13 close to codec @ R1142 10K_0402_5%
SLEEVE <44> DAI_LRCK# I2S_LRCK GPIO3
DAI_DI 24 37 1 EN_I2S_NB_CODEC#
<44> DAI_DI I2S_DIN MONO-OUT/CBP EN_I2S_NB_CODEC# <45>
C962
+RTC_CELL 2.2U_0603_16V6K
19 35 2
MIC1-L CBN
BCLK: Audio serial data bus bit clock input/output
LRCK: Audio serial data bus word clock 20
MIC1-R
100K_0402_5%
input/output 36
CBP/AVSS2
1
AUD_NB_MUTE# 47
<45> AUD_NB_MUTE# EAPD/PD
R1703
21 +ALC3226_LDO_CAP
LDO-CAP
1U_0603_10V6K
1 2 22
+3.3V_RUN JDREF
3
Q330B R1099 10K_0402_5% 1 7 34 +ALC3226_CPVEE

DVSS CPVEE 25 +ALC3226_VREF
2
VREF
C967 @
10U_0603_6.3V6M
42
PVSS
1
0.1U_0402_25V6
20K_0402_1%
2.2U_0603_16V6K
5 2 1 PCH_AZ_CODEC_RST# 30
2.2U_0603_16V6K
MIC1-VREFO 1
2
2 49 26
C1107
C1214
C965
GND AVSS1
R1642
C963
R39 @
4
Q330A 0_0402_5% ALC3226-CG_QFN48_7X7
1
2
2
2 2 1 AUD_NB_MUTE#
R40 @
1
0_0402_5% place at Codec bottom side

@ PJP62
1 2
Close to U74 pin6
PAD-OPEN1x1m
PCH_AZ_CODEC_BITCLK
1
@ R1076 place at AGND and DGND plane

33_0402_5%
1 2
1 2
R5 @
Place closely to Pin 13. 0_0402_5%
@ C977 1 2
10P_0402_50V8J
2
AUD_SENSE_A R6 @
0_0402_5%
1 2 +3.3V_RUN
1
39.2K_0402_1%
Combo Jack
R1086
R15 @
10K_0402_5%
0_0402_5%
1
2
R1100
Normal
L2N7002WT1G_SC-70-3
D Open
2
2 AUD_HP_NB_SENSE
10U_0603_6.3V6M
G JHP1
0.1U_0402_25V6
@@@@
S Q324 SLEEVE R3731 1 2 0_0402_5% EXT_MIC 4
3
@ C1247
1 1 RING2 R3732 1 2 0_0402_5% RING2_L 3

AUD_HP_OUT_R 2 1 AUD_HP_OUT_R1 R3733 1 2 0_0402_5% AUD_HP_OUT_R2 2
C972
AUD_HP_OUT_L R1679 2 19.1_0402_1%AUD_HP_OUT_L1 R3734 1 2 0_0402_5% AUD_HP_OUT_L2 1

base E-team detect issue , R1677 9.1_0402_1%
2 2
A
reserve RC to delay time 5 A
G 7
AUD_HP_NB_SENSE 6 8
G
SINGA_2SJ3082-000111F
CONN@
Add for solve pop noise and detect issue
0_0402_5%
2
L03ESDL5V0CC3-2_SOT23-3
L03ESDL5V0CC3-2_SOT23-3
AUD_HP_NB_SENSE
AUD_HP_NB_SENSE <45>
EMC@ D82
EMC@ D81
Notes:
1
Place closely to Pin 14
AUD_SENSE_B Keep PVDD supply and speaker traces routed on the DGND plane.
Keep away from AGND and other analog signals
@ R1676
1
2
1
+3.3V_RUN R1088
+3.3V_RUN
Resistor SENSE_A SENSE_B
R1079 R1080 100K_0402_5%
1
39.2K_0402_1% 20K_0402_1%
1
39.2K PORT A PORT E
2
1
R1081
2
100K_0402_5%
R1082 20K PORT B PORT F PORT A External MIC
100K_0402_5%
2
10K NA DMIC0 PORT B HeadPhone Out

2 5 PROPRIETARY NOTE:
<45> DOCK_HP_DET DOCK_MIC_DET <45> Title
5.11K SPDIFOUT0 SPDIFOUT1 (DMIC1) PORT C Dock Audio THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Q106A Q106B
SCHEMATIC,MB LA-9931P
1
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT

2.49K Pull‐up to AVDD PORT D Internal SPK BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
B
2 1
5 4 3 2 1
D D
HDD PWR
+5V_HDD +5V_RUN
@ PJP3
1 2
1 2
JUMP_43X79
SHORT DEFAULT
@ PJP53
+3.3V_RUN 1 2 +3.3V_RUN_FFS
Free Fall Sensor
10U_0603_6.3V6M
0.1U_0402_25V6
PAD-OPEN1x1m
1 1
U88
C387
C388
LNG3DM 10
2 2 1
14 VDD_IO
VDD
RES
RES
RES
13
15
16
HDD CONN
JSATA1
11 RES 1
<16> HDD_FALL_INT FFS_INT2 9 INT 1 5 C383 2 1 0.01U_0402_16V7K SATA_PTX_DRX_P0 2 GND
INT 2 GND <15> PSATA_PTX_DRX_P0_C RX+
12 C384 2 1 0.01U_0402_16V7K SATA_PTX_DRX_N0 3
GND <15> PSATA_PTX_DRX_N0_C RX-
7 4
6 SDO/SA0 C385 2 1 0.01U_0402_16V7K SATA_PRX_DTX_N0 5 GND
<7,13,14,15,18,27> DDR_XDP_WAN_SMBDAT SDA / SDI / SDO <15> PSATA_PRX_DTX_N0_C TX-
4 C386 2 1 0.01U_0402_16V7K SATA_PRX_DTX_P0 6
<7,13,14,15,18,27> DDR_XDP_WAN_SMBCLK SCL/SPC <15> PSATA_PRX_DTX_P0_C TX+
2 7
8 NC 3 @ PJP64 GND
CS NC 1 2 +3.3V_RUN_HDD 8
C
+3.3V_RUN 3.3V C
LNG3DMTR_LGA16_3X3 9
PAD-OPEN1x1m 1 2 +3.3V_RUN_HDD_R 10 3.3V
@ R1635 0_0402_5% 11 3.3V
12 GND
<15,17> HDD_DET# 13 GND
14 GND
+5V_HDD 5V
15
16 5V
+5V_HDD 17 5V
FFS_INT2_Q 18 GND 23
Reserved GND1
100K_0402_5%
19 24
GND GND2
1
20
12V
@ R506
21
+3.3V_RUN +5V_HDD +3.3V_RUN_HDD 22 12V
+3.3V_RUN 12V
100K_0402_5%
CONN@
2
1
1000P_0402_50V7K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
SANTA_196003-1
R508
1 2 DDR_XDP_WAN_SMBDAT
R501 10K_0402_5% FFS_INT2_Q 1 1 1 1
C395
C396
C402
C399
1 2 DDR_XDP_WAN_SMBCLK
3
R502 10K_0402_5% Main SATA +5V Default
2
1 2 HDD_FALL_INT
2 2 2 2
Q29B
R503 100K_0402_5%
5
6
4
Q29A
FFS_INT2 2
<20> FFS_INT2
Place near HDD CONN
1
B B
A A
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
+5V_MOD/+5V_RUN source
D D
+5V_MOD +5V_RUN
@ PJP4
1 2
1 2
JUMP_43X79
+5V_ALW
U37
1 14 1 2
2 1 2 VIN1 VOUT1 13 @ C765 10U_0603_6.3V6M
100K_0402_5% R512 VIN1 VOUT1
+3.3V_ALW2 3 12 1 2
<45> MODC_EN ON1 CT1 C438 470P_0402_50V7K
4 11
VBIAS GND
1
R517 5 10 1 2
<39,45,48,53> RUN_ON ON2 CT2
100K_0402_5% C436 470P_0402_50V7K
6 9
7 VIN2 VOUT2 8
2
VIN2 VOUT2 +5V_RUN
1
10U_0603_6.3V6M
@ C764
MODC_EN# 15
GPAD
6
TPS22966DPUR_SON14_2X3
2
Q76A
MODC_EN 2
1
C C
ODD CONN
JSATA2
1
C407 2 1 0.01U_0402_16V7K SATA_ODD_PTX_DRX_P1 2 GND
<15> SATA_ODD_PTX_DRX_P1_C A+
C406 2 1 0.01U_0402_16V7K SATA_ODD_PTX_DRX_N1 3
<15> SATA_ODD_PTX_DRX_N1_C A-
4
C405 2 1 0.01U_0402_16V7K SATA_ODD_PRX_DTX_N1 5 GND
<15> SATA_ODD_PRX_DTX_N1_C C404 2 1 0.01U_0402_16V7K SATA_ODD_PRX_DTX_P1 6 B-
<15> SATA_ODD_PRX_DTX_P1_C 7 B+
GND
8
<46> DEVICE_DET# DP
+5V_MOD 9
10 +5V
Q76B MOD_MD 11 +5V
DMN66D0LDW-7_SOT363-6 12 MD
MOD_MD 4 3 ZODD_WAKE# 13 GND
ZODD_WAKE# <45> GND
14
15 GND
<17> CLK_PCIE_EMB
5
MODC_EN# 16 REFCLK+
<17> CLK_PCIE_EMB# REFCLK-
17
B 18 GND B
<19> PCIE_PRX_EMBTX_P4 PETX+
19
<19> PCIE_PRX_EMBTX_N4 PETX-
Q123B 20
DMN66D0LDW-7_SOT363-6 21 GND
4 3 USB30_SMI# 0.1U_0402_25V6 2 1 C409 PCIE_PTX_EMBRX_P4_C 22 GND
USB30_SMI# <15,45> <19> PCIE_PTX_EMBRX_P4 PERX+
0.1U_0402_25V6 2 1 C408 PCIE_PTX_EMBRX_N4_C 23
<19> PCIE_PTX_EMBRX_N4 PERX-
24
GND
5
USB30_EN +5V_MOD 25
26 +5V
<17> EMBCLK_REQ# CLKREQ#
27
<36,37,38,39,46> PCIE_WAKE# WAKE#
28
<16> PLTRST_EMB# PERST#
29 32
+3.3V_ALW_PCH <46> BAY_SMBDAT SMB_DATA GND1
30 33
<46> BAY_SMBCLK SMB_CLK GND2
31
<45> MOD_SATA_PCIE#_DET HPD
RP18 +3.3V_ALW
1 8 ZODD_WAKE#
100K_0402_5%
2 7 MOD_MD TYCO_2-2129116-3
1
+3.3V_ALW 3 6 MOD_SATA_PCIE#_DET CONN@

4 5 SYS_LED_MASK#
SYS_LED_MASK# <24,33,45>
R515
+5V_MOD PLTRST_EMB#
10K_8P4R_5%
2
1000P_0402_50V7K
0.1U_0402_25V6
@
USB30_EN
1 1 C1565
0.047U_0402_16V4Z
2
C397
C398
6
2 2
ESD Request
Q123A
MOD_SATA_PCIE#_DET 2
A A
1
Place near ODD CONN DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
+3.3V_LAN
1 2 TP_LAN_JTAG_TMS
@ R545 10K_0402_5%
1 2 TP_LAN_JTAG_TCK
@ R546 10K_0402_5% +0.9V_LAN
U31
1 2 LANCLK_REQ#_R 48 13 LAN_TX0+ REGCTL_PNP10 1 2

<15,17> LANCLK_REQ# @ R1187 0_0402_5% 36 CLK_REQ_N MDI_PLUS0 14 LAN_TX0- 4.7UH_CBC2012T4R7M_20% L29
+3.3V_LAN <16> PLTRST_LAN# PE_RST_N MDI_MINUS0
10U_0603_6.3V6M
0.1U_0402_25V6
CLK_PCIE_LAN 44 17 LAN_TX1+ 1 1
<17> CLK_PCIE_LAN PE_CLKP MDI_PLUS1
C462
C463
1 2 LANWAKE# CLK_PCIE_LAN# 45 18 LAN_TX1-
<17> CLK_PCIE_LAN#
PCIE
PE_CLKN MDI_MINUS1
MDI
@ R558 4.7K_0402_5% 2 1 PCIE_PRX_GLANTX_P2_C
<19> PCIE_PRX_GLANTX_P2
D C458 0.1U_0402_25V6 38 20 LAN_TX2+ D
+PCH_VCCDSW3_3 Support Deep S3 mode 2 1 PCIE_PRX_GLANTX_N2_C 39 PETp MDI_PLUS2 21 LAN_TX2- 2 2
<19> PCIE_PRX_GLANTX_N2 PETn MDI_MINUS2 Place R548, C462, C463 and L29 close to U31
C459 0.1U_0402_25V6
2 1 LANWAKE# +3.3V_LAN 1 2 PCIE_PTX_GLANRX_P2_C 41 23 LAN_TX3+
<19> PCIE_PTX_GLANRX_P2 PERp MDI_PLUS3
@ R566 10K_0402_5% C460 0.1U_0402_25V6 42 24 LAN_TX3- Pin 6 is SVR_EN in Clarkville
PERn MDI_MINUS3
10K_0402_5%
1 2 PCIE_PTX_GLANRX_N2_C
<19> PCIE_PTX_GLANRX_N2
1
@ R549
C461 0.1U_0402_25V6
1 2 LAN_SMBCLK_R 28 6 VCT_LAN_R1 @ R152 2 1 0_0402_5%
<18> LAN_SMBCLK
SMBUS
@ R551 0_0402_5% 31 SMB_CLK SVR_EN_N +0.9V_LAN +3.3V_LAN_OUT
1 2 LAN_SMBDATA_R SMB_DATA 1 +RSVD_VCC3P3_1 R553 2 1 4.7K_0402_5%
<18> LAN_SMBDATA RSVD_VCC3P3_1 +3.3V_LAN
@ R552 0_0402_5%
2
LANWAKE# 2 5
<20,46> LANWAKE# LANWAKE_N VDD3P3_IN
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
22U_0805_6.3V6M
22U_0805_6.3V6M
1 2 LAN_DISABLE#_R 3
<17,20> PM_LANPHY_ENABLE LAN_DISABLE_N
@ R555 0_0402_5% SMBus Device Address 0xC8 4 +3.3V_LAN_OUT @ R154 2 1 0_0603_5% +3.3V_LAN 1 1 1 1 1 1
VDD3P3_4
C1177
C1178
<45> LAN_DISABLE#_R
10K_0402_5%
1U_0603_10V6K
C466
C467
C468
C469
15 1
VDD3P3_15
1
@ R557
LOM_ACTLED_YEL# 26 19
LED0 VDD3P3_19 2 2 2 2 2 2
C464
LOM_SPD100LED_ORG# 27 29
LED1 VDD3P3_29
LED
LOM_SPD10LED_GRN# 25 +0.9V_LAN
LED2 2
47
2
VDD0P9_47 46
@ T142 PAD~D TP_LAN_JTAG_TDI 32 VDD0P9_46 37
JTAG_TDI VDD0P9_37 Note:
@ T143 PAD~D TP_LAN_JTAG_TDO 34 Place C1178 close to pin5
JTAG_TDO +1.0V_LAN will work at 0.95V to 1.15V
JTAG
TP_LAN_JTAG_TMS 33 43 Pin 2 is WAKE_EN in Clarkville
TP_LAN_JTAG_TCK 35 JTAG_TMS VDD0P9_43
JTAG_TCK 11
VDD0P9_11
@ R1144 1 2 0_0402_5% XTALO 9 40 0.9Vdc POWER OPTIONS
XTALI 10 XTAL_OUT VDD0P9_40 22
XTAL_IN VDD0P9_22
Internal SRV
Y3 16 Shared with PCH
25MHZ_18PF_X3G025000DI1H-H VDD0P9_16 8
VDD0P9_8 1.05V SVR *
1 3 LAN_TEST_EN 30
IN OUT TEST_EN
27P_0402_50V8J
27P_0402_50V8J
2 4 RES_BIAS 12 7 REGCTL_PNP10 STUFF: R548 STUFF: L29

C GND GND RBIAS CTRL0P9 C
2 2 NO STUFF: L29 NO STUFF: R548
C470
49
VSS_EPAD
1
C471
1K_0402_5%
3.01K_0402_1%
WGI217LM-QQ4R-A3_QFN48_6X6~D
1 1
R561
R562
Need update symbol by pin 5
LAN ANALOG SWITCH
+3.3V_LAN
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1 1 1
C472
C473
C474
2 2 2
Layout Notice : Place bead as
close PI3L500 as possible
39
30
21
14
8
4
1
U32
VDD
VDD
VDD
VDD
VDD
VDD
VDD
38 SW_LAN_TX0+ +3.3V_LAN
B0+ SW_LAN_TX0+ <34>
B 37 SW_LAN_TX0- B
B0- SW_LAN_TX0- <34>
LAN_TX0+ @ R3763 1 20_0603_5% LAN_TX0+R 2 @ C478
A0+ 34 SW_LAN_TX1+ 1 2
B1+ SW_LAN_TX1+ <34>
LAN_TX0- @ R3764 1 20_0603_5% LAN_TX0-R 3 33 SW_LAN_TX1-
A0- B1- SW_LAN_TX1- <34>
0.1U_0402_25V6
5
29 SW_LAN_TX2+
LAN_TX1+ @ R3765 1 20_0603_5% LAN_TX1+R 6 B2+ 28 SW_LAN_TX2- SW_LAN_TX2+ <34> U15
VCC
A1+ B2- SW_LAN_TX2- <34> LOM_SPD100LED_ORG# 1 NL17SZ08DFT2G_SC70-5
LAN_TX1- @ R3766 1 20_0603_5% LAN_TX1-R 7 25 SW_LAN_TX3+ IN B 4
A1- B3+ SW_LAN_TX3+ <34> OUT Y WLAN_LAN_DISB# <45>
24 SW_LAN_TX3- LOM_SPD10LED_GRN# 2
GND
B3- SW_LAN_TX3- <34> IN A
LAN_TX2+ @ R3767 1 20_0603_5% LAN_TX2+R 9 17 LAN_ACTLED_YEL#
A2+ LEDB0 18 LED_100_ORG#
3
LAN_TX2- @ R3768 1 20_0603_5% LAN_TX2-R 10 LEDB1 41 LED_10_GRN#
A2- LEDB2
36 DOCK_LOM_TRD0+
C0+ DOCK_LOM_TRD0+ <44>
LAN_TX3+ @ R3769 1 20_0603_5% LAN_TX3+R 11 35 DOCK_LOM_TRD0-
A3+ C0- DOCK_LOM_TRD0- <44>
Q326
LAN_TX3- @ R3770 1 20_0603_5% LAN_TX3-R 12 32 DOCK_LOM_TRD1+ Q325A L2N7002WT1G_SC-70-3
A3- C1+ DOCK_LOM_TRD1+ <44>
31 DOCK_LOM_TRD1- DMN66D0LDW-7_SOT363-6
C1- DOCK_LOM_TRD1- <44>
D
LAN_ACTLED_YEL# 1 6 LED_10_GRN# 3 1
LAN_ACTLED_YEL#_Q <34> LED_10_GRN#_Q <34>
DOCKED 13 27 DOCK_LOM_TRD2+
<45> DOCKED SEL C2+ 26 DOCK_LOM_TRD2- DOCK_LOM_TRD2+ <44>
C2- DOCK_LOM_TRD2- <44>
G
2
2
LOM_ACTLED_YEL# 15 23 DOCK_LOM_TRD3+
LEDA0 C3+ DOCK_LOM_TRD3+ <44>
LOM_SPD100LED_ORG# 16 22 DOCK_LOM_TRD3- SYS_LED_MASK#
LEDA1 C3- DOCK_LOM_TRD3- <44> SYS_LED_MASK# <24,32,45>
LOM_SPD10LED_GRN# 42 SYS_LED_MASK#
LEDA2 19 DOCK_LOM_ACTLED_YEL#
LEDC0 DOCK_LOM_ACTLED_YEL# <44>
5 20 DOCK_LOM_SPD100LED_ORG#
PD LEDC1 DOCK_LOM_SPD100LED_ORG# <44>
40 DOCK_LOM_SPD10LED_GRN#
LEDC2 DOCK_LOM_SPD10LED_GRN# <44>
43 Q325B
1: TO DOCK PAD_GND DMN66D0LDW-7_SOT363-6
DOCKED LED_100_ORG# 4 3
LED_100_ORG#_Q <34>
0: TO RJ45
A A
PI3L720ZHEX_TQFN42_9X3P5
5
SYS_LED_MASK#
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
D D
SW_LAN_TX0+_R 1 2 SW_LAN_TX0-_R
@ C500 10P_0402_50V8J
SW_LAN_TX1+_R 1 2 SW_LAN_TX1-_R
@ C501 10P_0402_50V8J
T156
1 1:1 24 NB_LAN_TX0+
@ R575 1 20_0402_5% SW_LAN_TX0+_R TD1+ TX1+
<33> SW_LAN_TX0+
@ R576 1 20_0402_5% SW_LAN_TX0-_R +3.3V_LAN
<33> SW_LAN_TX0-
2
TD1- 23 NB_LAN_TX0-
TX1- JLOM1
C479 0.47U_0603_10V7K
2 1 +TRM_CT1 3 22 Z2805 9
TDCT1 TXCT1 Yellow LED+
C480 0.47U_0603_10V7K 1 2 10
C <33> LAN_ACTLED_YEL#_Q Yellow LED- C
2 1+TRM_CT2 4 21 Z2807 R1166 150_0402_5%
5 TDCT2 TXCT2 20 NB_LAN_TX1+ NB_LAN_TX3- 8
TD2+ 1:1 TX2+ PR4-
@ R577 1 20_0402_5% SW_LAN_TX1+_R NB_LAN_TX3+ 7
<33> SW_LAN_TX1+ PR4+
@ R578 1 20_0402_5% SW_LAN_TX1-_R NB_LAN_TX1- 6
<33> SW_LAN_TX1- PR2-
6 19 NB_LAN_TX1-
TD2- TX2- NB_LAN_TX2- 5
PR3-
NB_LAN_TX2+ 4
PR3+
NB_LAN_TX1+ 3
SW_LAN_TX2+ 7 1:1 18 NB_LAN_TX2+ PR2+
<33> SW_LAN_TX2+ TD3+ TX3+ NB_LAN_TX0- 2
PR1- 15
NB_LAN_TX0+ 1 GND
SW_LAN_TX2- 8 PR1+ 14
<33> SW_LAN_TX2- TD3- GND
17 NB_LAN_TX2- 1 2 11
TX3- <33> LED_10_GRN#_Q Green LED-
R1653 150_0402_5%
1 2 13
<33> LED_100_ORG#_Q Orange LED-
+TRM_CT3 9 16 Z2806 R1167 150_0402_5%
TDCT3 TXCT3 12
Green-Orange LED+
+TRM_CT4 10 15 Z2808
TDCT4 TXCT4
75_0402_1%
75_0402_1%
75_0402_1%
75_0402_1%
SW_LAN_TX3+ 11 1:1 14 NB_LAN_TX3+ J-L_TNBNRBC80002008
<33> SW_LAN_TX3+ TD4+ TX4+ +3.3V_LAN
0.47U_0603_10V7K
0.47U_0603_10V7K
CONN@
1 1
C483
C484
SW_LAN_TX3- 12 13 NB_LAN_TX3-
2 2 <33> SW_LAN_TX3- TD4- TX4-
1U_0603_10V6K
0.1U_0402_25V6
470P_0402_50V7K
1 1 1
1
B B
C481
C482
C1167
350uH_IH-115-F~D
2 2 2
T156 change PN to SP050006Y00 S X'FORM_ NS692417 LAN
GND
R571 2
R572 2
R573 2
R574 2
CHASSIS
1 2 EMC@ C485 GND_CHASSIS
150P_1808_3KV8J
Close to JLOM1
A A
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN_TPM
+3.3V_RUN +3.3V_RUN_TPM
@ PJP61 +3.3V_RUN_TPM
0.1U_0402_25V6
4700P_0402_25V7K
D 1 2 D
1 1
ATMEL TPM for E4
C44
C45
PAD-OPEN1x1m
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0402_25V6
2 2
1 1 1 1
U39
C550
C551
C552
C553
10
5 VCC_0 19 2 2 2 2
SB3V VCC_1 24
1 2 VCC_2
<16> SUS_STAT#/LPCPD#
@ R1667 0_0402_5%
1 2
<20> PCH_GPIO22
@ R3771 0_0402_5%
1 2 SP_TPM_LPC_EN_R 28 12
<45> SP_TPM_LPC_EN LPCPD# V_BAT
@ R1169 0_0402_5% 13
26 NBO_13 14
<18,37,45,46> LPC_LAD0 LAD0 NBO_14
23
<18,37,45,46> LPC_LAD1 LAD1
20
<18,37,45,46> LPC_LAD2 LAD2
17
<18,37,45,46> LPC_LAD3 LAD3 6
GPIO6
21 9 1 2
<17> CLK_PCI_TPM LCLK TESTBI
22 8 R657 4.7K_0402_5%
<18,37,45,46> LPC_LFRAME# LFRAME# TESTI
16
<16,37,38,39,45,46> PCH_PLTRST#_EC LRESET#
27
<17,18,45,46> IRQ_SERIRQ SERIRQ
15
<16,45,46> CLKRUN# CLKRUN# 7
NC_7
1 4
C 2 ATEST_1 GND_4 11 C
3 ATEST_2 GND_11 18
ATEST_3 GND_18 25
GND_25
AT97SC3204-DX4A12-AB_TSSOP28
JUSH1 pin reverse between IVY and

HSW to support E4 13 USH board
JUSH1
22
21 GND2
GND1
20
19 20
<19> USBP7- 19
18
USH CONN <19>
<46> USH_SMBCLK
USBP7+
17
16
15
18
17
16
<46> USH_SMBDAT 15
14
<45> BCM5882_ALERT# 13 14
+3.3V_SUS +3.3V_SUS 13
12
11 12
USH_SMBCLK 2 1 10 11
2.2K_0402_5% R589 9 10
USH_SMBDAT 2 1 8 9
B
+3.3V_RUN 8 B
2.2K_0402_5% R585 +5V_RUN 7
6 7
USH_PWR_STATE# 1 2 <16> PLTRST_USH# 5 6
1M_0402_5% R1640 <45> USH_PWR_STATE# 4 5
<17,20> CONTACTLESS_DET# 4
3
JAPS1 2 3
1 1 2
+3.3V_ALW_PCH 1 <20> USH_DET# 1
2
<16,39,40,45,53> SIO_SLP_S3# 2
+PCH_VCCDSW3_3 3 HB_A522020-SCHR22
4 3
<16,46> SIO_SLP_S5# 4 CONN@
5
<16,45,51> SIO_SLP_S4# 5
6
<16,45,52> SIO_SLP_A# 6
+3.3V_ALW 7
8 7
9 8
<15> PCH_RTCRST# 9 +3.3V_SUS +3.3V_RUN +5V_RUN
10
11 10
<24,46> POWER_SW#_MB 11
12
12
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
13
<16> SYS_RESET# 13
14
15 14
15 1 1 1
C53
C51
C52
16
16
17 @ @ @
18 GND 2 2 2
GND
TYCO_1-2041070-6~D
CONN@
Close to JUSH1
A A
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
A B C D E
C575 must close to U38.27 within 50mils

C576 must close to U38.9 within 50mils
C577 must close to U38.9 with 100mils
+3.3V_RUN L45 must close to U38.9 within 200mils Close to U38.11
+3.3V_RUN +3.3V_RUN_OZVCC trace width 30mils
L45 +3.3V_RUN
2 1 +3.3V_RUN_OZVCC
BLM15BD601SN1D_2P
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
close to U38.23
close to U38.42
4.7U_0603_6.3V6K
0.1U_0402_25V6
1
1
C581
C574
C578
C577
C576
C575
2
2
C1502
C1503
2
1 1
1
+1.2V_OZ_AUX_LDO
+3.3V_OZ_IO_LDO
0.1U_0402_25V6
4.7U_0603_6.3V6K
1U_0603_10V7K
+1.2V_LDO +3.3V_RUN
2
2
C800
C566
C564
U38
Close to U38.13
4.7U_0603_6.3V6K
1
1
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
0.1U_0402_25V6
9 12
PE_33VCCAIN
OZ777FJ2LN AUX_LDO_CAP
close to U38.10
close to U38.41
close to U38.10
2
27
2 UHSII_33VCCAIN/NC
2
C1507
C1506
C1505
25
SD_IO_LDO_CAP
C1504
C1501
1
42
1
1
SD_33VCCD
trace width 30mils 23 Close to U38.25 Close to U38.12
SD_SKT_33VIN
trace width 30mils 13 22
AUX _33VIN SD_SKT_33VOUT +3.3V_RUN_CARD
+3.3V_RUN 11 24 +1.8V_RUN_CARD
+1.2V_LDO MAIN_LDO_VIN SD_SKT_18VOUT
L47 close to U38.31 within 200mils 10 C559 1 2 1U_0603_10V7K
L47 2 1 +1.2V_LDO, +1.2V_LDO_OZ trace width 30mils MAIN_LDO_12VOUT C560 1 2 4.7U_0603_6.3V6K
BLM15BD601SN1D_2P
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
41
CORE_12VCCD
close to U38.31
close to U38.26
close to U38.31
close to U38.34
close to U38.1
20 SD_WPI
SD_WPI
2
+1.2V_LDO_OZ 36 21 SD_CD#
UHSII_12VCCAIN/NC SD_CD#
C561
C1510
C1509
C1508
31
2 28 UHSII_12VCCAIN/NC 43 SD_CLK_R EMC@ R676 1 2 10_0402_1% SD_CLK 2
1
UHSII_12VCCAIN/NC SD_CLK 45 SD_CMD

1 SD_CMD
PE_12VCCAIN 39
MMC_D7 40
R677 must be close to U38 less than 100mils MMC_D6 44
1 2 OZ_PE_REXT 4 MMC_D5 46
R677 191_0402_1% PE_REXT MMC_D4 47 SD_D3
C567 1 2 0.1U_0402_25V6 PCIE_PTX_MMIRX_P8_C 6 SD_D3 48 SD_D2
<19> PCIE_PTX_MMIRX_P8 PE_RXP SD_D2
C568 1 2 0.1U_0402_25V6 PCIE_PTX_MMIRX_N8_C 5 37
<19> PCIE_PTX_MMIRX_N8 PE_RXM SD_D1 38
C569 1 2 0.1U_0402_25V6 PCIE_PRX_MMITX_P8_C 7 SD_D0 @ LE5
<19> PCIE_PRX_MMITX_P8 C571 1 2 0.1U_0402_25V6 PCIE_PRX_MMITX_N8_C 8 PE_TXP 29 SD_D1_RCLKR_N 1 2 SD_D1_RCLK_N
<19> PCIE_PRX_MMITX_N8 PE_TXM SD_RCLK_M/NC 30 SD_D0_RCLKR_P 1 2
2 SD_RCLK_P/NC 32 SD_UHS2_D1P_R
<17> CLK_PCIE_MMI# PE_REFCLKM SD_D1P/NC
3 33 SD_UHS2_D1N_R 4 3 SD_D0_RCLK_P_MMC_D0
<17> CLK_PCIE_MMI PE_REFCLKP SD_D1M/NC 4 3
34 SD_UHS2_D0N_R
15 SD_D0M/NC 35 SD_UHS2_D0P_R DLW21SN900HQ2L_0805_4P
<16> PLTRST_MMI# PE_RST#_GATE# SD_D0P/NC @ RE27 1 2 0_0402_5%
OZ_LDO_EN 14 26 R1702 1 2 4.7K_0402_1%
MAIN_LDO_EN SD_REXT/NC
16 R1702 must be close to U38 less than 100mils @ RE28 1 2 0_0402_5%
<32,37,38,39,46> PCIE_WAKE# DEV_WAKE#
17 19
<15,17> MMICLK_REQ# CLKREQ# LED# please routing daisy chain
MULTIO_0 18 49 1. from U38.38 (SD_D0) -> U38.32 (SD_RCLK_P) -> LE5.4
IO0_LDOSEL GND 2. From U38.37 (SD_D1) -> U38.33 (SD_RCLK_N) -> LE5.1
OZ777FJ2LN_QFN48_6X6
+3.3V_RUN_CARD
LE2 @ JSD1
3 SD_UHS2_D1P_R 1 2 SD_UHS2_D1P 4 3
1 2 14 VDD/VDD1
SD_CMD 2 VDD2
4.7U_0603_6.3V6K
SD_UHS2_D1N_R 4 3 SD_UHS2_D1N SD_CLK 5 CMD
4 3 CLK
@ C572
DLW21SN900HQ2L_0805_4P SD_CD# 17
@ RE3 1 2 0_0402_5% SD_WPI 18 CARD DETECT
WRITE PROTEC
0.1U_0402_25V6
2
1
+3.3V_RUN
1M_0402_5%
SD_D0_RCLK_P_MMC_D0 7
DAT0/RCLK+
2
R3884
@ RE4 1 2 0_0402_5% SD_D1_RCLK_N 8
DAT1/RCLK-
C802
SD_D2 9
SD_D3 1 DAT2
1
1 2 OZ_LDO_EN SD_UHS2_D0P 11 CD/DAT3
2
R894 10K_0402_5% LE4 @ SD_UHS2_D0N 12 D0+
SD_UHS2_D0N_R 1 2 SD_UHS2_D0N +1.8V_RUN_CARD SD_UHS2_D1P 16 D0- 19
1 2 SD_UHS2_D1N 15 D1+ GND 20
1 2 MULTIO_0 D1- GND 21
R1700 100K_0402_5% SD_UHS2_D0P_R 4 3 SD_UHS2_D0P 3 GND 22
0.1U_0402_25V6
4 3 O2 request 6 VSS1 GND 23
VSS2 GND
@ C580
DLW21SN900HQ2L_0805_4P 10 24
VSS3 GND
1
@ RE25 1 2 0_0402_5% 13 25
VSS4 GND
ALPS_SCDACA0101
2
@ RE26 1 2 0_0402_5% CONN@
4 4
only for MMC/SD

PROPRIETARY NOTE:
Title
B
A B C D E
5 4 3 2 1
1 2
@ R693 0_0402_5%
<45> WLAN_RADIO_DIS#
D31
1 2 WLAN_RADIO_DIS#_R
RB751V40_SC76-2
Mini WLAN/WIMAX/60GHz H=9 +3.3V_WLAN
1 2
@ R694 0_0402_5%
2 1 WIGIG60GHZ_DIS#_R
1 2 WIGIG60GHZ_DIS#_R @ R725 100K_0402_5%
<45> WIGIG60GHZ_DIS#
D35 RB751V40_SC76-2
1 2
@ R695 0_0402_5% 2 1 WLAN_RADIO_DIS#_R
@ R3885 100K_0402_5%
1 2 BT_RADIO_DIS#_R
<45> BT_RADIO_DIS#
D36 RB751V40_SC76-2
+3.3V_WLAN +3.3V_WLAN 2 1 BT_RADIO_DIS#_R
@ R3886 100K_0402_5%
D JMINI2 D
<32,36,38,39,46> PCIE_WAKE# PCIE_WAKE# 1 2
3 1 2 4
5/24 confirmed with Sean can remove 3 4
COEX2_WLAN_ACTIVE and pin4 COEX1_BT_ACTIVE 5 6
7 5 6 8 C595
<17> MINI2CLK_REQ# 9 7 8 10 1 2 +3.3V_RUN
11 9 10 12
<17> CLK_PCIE_MINI2# 11 12
13 14 MSDATA 4700P_0402_25V7K RP20
<17> CLK_PCIE_MINI2 13 14
15 16 1 8 USB_MCARD1_DET#
15 16 HOST_DEBUG_TX <46>
17 18 2 7 CPPE#
<45,46> EC5048_TX 19 17 18 20 WLAN_RADIO_DIS#_R 3 6
<46> MSCLK 21 19 20 22 2 1 PCH_PLTRST#_EC 4 5 AUX_EN_WOWL
21 22 PCH_PLTRST#_EC <16,35,38,39,45,46> AUX_EN_WOWL <39,45>
PCIE_PRX_WLANTX_N3 23 24 @ R703 0_0402_5%
<19> PCIE_PRX_WLANTX_N3 PCIE_PRX_WLANTX_P3 25 23 24 26 100K_0804_8P4R_5%
<19> PCIE_PRX_WLANTX_P3 27 25 26 28
C596 0.1U_0402_25V6 29 27 28 30
1 2 PCIE_PTX_WLANRX_N3_C 31 29 30 32 WIGIG60GHZ_DIS#_R
<19> PCIE_PTX_WLANRX_N3 31 32
1 2 PCIE_PTX_WLANRX_P3_C 33 34
<19> PCIE_PTX_WLANRX_P3 33 34
C598 0.1U_0402_25V6 35 36 USBP4-
35 36 USBP4- <19>
CPPE# 37 38 USBP4+
<16> CPPE# 37 38 USBP4+ <19>
39 40 USB_MCARD1_DET#
39 40 USB_MCARD1_DET# <16>
41 42 WIGIG_LED#
43 41 42 44 WLAN_LED#
45 43 44 46 BT_LED#
<18> PCH_CL_CLK1 45 46
47 48 1 2
<18> PCH_CL_DATA1 47 48 MSDATA <46>
@ R707 2 1 0_0402_5% 49 50 @ R706 0_0402_5%
<18> PCH_CL_RST1# 49 50
BT_RADIO_DIS#_R 51 52 WIMAX_LED# STUDY FOR DEBUG
51 52
53 54
GND1 GND2
BELLW_80003-8041
CONN@
+3.3V_WLAN
C C
8
7
6
5
RP13
100K_0804_8P4R_5%
5
+3.3V_WLAN
1
2
3
4
WIGIG_LED# 4 3 WIRELESS_LED#
WIRELESS_LED# <24,38,45>
Q124B
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
0.1U_0402_25V6
2
1 1 1 2 2 1
@ C603
WLAN_LED# 1 6
C604
C605
C606
C607
C608
Q124A
2 2 2 1 1 2 DMN66D0LDW-7_SOT363-6
2
G
BT_LED# 3 1
D
Q89
L2N7002WT1G_SC-70-3
1/2 Minicard Pink Pather Card H=9
+3.3V_PCIE_FLASH +3.3V_PCIE_FLASH
B JMINI3 B
PCIE_WAKE# 1 2
3 1 2 4
5 3 4 6
7 5 6 8
<17> MINI3CLK_REQ# 7 8 LPC_LFRAME# <18,35,45,46>
9 10
9 10 LPC_LAD3 <18,35,45,46>
CLK_PCIE_MINI3# 11 12
<17> CLK_PCIE_MINI3# 11 12 LPC_LAD2 <18,35,45,46>
CLK_PCIE_MINI3 13 14
<17> CLK_PCIE_MINI3 13 14 LPC_LAD1 <18,35,45,46>
15 16
15 16 LPC_LAD0 <18,35,45,46>
PCH_PLTRST#_EC 17 18
PCLK_80H 19 17 18 20
<17> PCLK_80H 19 20
21 22 PCH_PLTRST#_EC
PCIE_PRX_WPANTX_N6 23 21 22 24
<19> PCIE_PRX_WPANTX_N6 PCIE_PRX_WPANTX_P6 25 23 24 26
<19> PCIE_PRX_WPANTX_P6 27 25 26 28
C617 0.1U_0402_25V6 29 27 28 30
1 2 PCIE_PTX_WPANRX_N6_C 31 29 30 32
<19> PCIE_PTX_WPANRX_N6 31 32
1 2 PCIE_PTX_WPANRX_P6_C 33 34
<19> PCIE_PTX_WPANRX_P6 33 34
C618 0.1U_0402_25V6 35 36 USBP8-
35 36 USBP8- <19>
37 38 USBP8+
37 38 USBP8+ <19>
39 40
41 39 40 42
43 41 42 44
45 43 44 46
47 45 46 48
49 47 48 50
51 49 50 52
51 52
+3.3V_PCIE_FLASH 53 54
GND1 GND2
BELLW_80003-1121
CONN@
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
0.1U_0402_25V6
1 1 1 2 2 1
@ C621
C622
C623
C624
C625
C626
A A
2 2 2 1 1 2
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
Mini WWAN/GPS/LTE/UWB H=9 (1) Wake Enabled and Active

+3.3V_PCIE_WWAN +3.3V_PCIE_WWAN (2) Wake NOT Enabled nor Active
JMINI1
<32,36,37,39,46> PCIE_WAKE# PCIE_WAKE# 1 2 D0-D2&D3 hot Power D3 cold Power
3 1 2 4
3 4 PWR Rail Voltage
5 6
7 5 6 8 Tolerance Peak(mA) Typ(mA) Peak(mA) Typ(mA)
<17> MINI1CLK_REQ# 7 8 +SIM_PWR
9 10 UIM_DATA
CLK_PCIE_MINI1# 11 9 10 12 UIM_CLK
<17> CLK_PCIE_MINI1# CLK_PCIE_MINI1 13 11 12 14 UIM_RESET
<17> CLK_PCIE_MINI1 13 14 +3.3V_PCIE_WWAN +-9% 2750 800 800 (1) 150 (1)
15 16 +UIM_VPP
MSATA TX/RX pin out 17 15 16 18 5 (2)
19 17 18 20
D 19 20 WWAN_RADIO_DIS# <45> D
21 22 2 1
21 22 PCH_PLTRST#_EC <16,35,37,39,45,46>
23 24 @ R704 0_0402_5%
<15> PCIE_SATA_PRX_WANTX_P4 25 23 24 26
<15> PCIE_SATA_PRX_WANTX_N4 27 25 26 28
29 27 28 30
2 1 PCIE_SATA_PTX_WANRX_N4_C 31 29 30 32
<15> PCIE_SATA_PTX_WANRX_N4 31 32
C417 0.1U_0402_10V7K 33 34
2 1 PCIE_SATA_PTX_WANRX_P4_C 35 33 34 36 USBP5-
<15> PCIE_SATA_PTX_WANRX_P4 35 36 USBP5- <19>
C416 0.1U_0402_10V7K 37 38 USBP5+
37 38 USBP5+ <19>
39 40
41 39 40 42 LED_WWAN_OUT#
43
45
47
41
43
45
42
44
46
44
46
48
+SIM_PWR SIM Card Push‐Push
49 47 48 50 JSIM1
HW_GPS_DISABLE2# 51 49 50 52 1
<45> HW_GPS_DISABLE2# 51 52 UIM_RESET 2 VCC 11
RST GND_2
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
53 54 UIM_CLK 3 12
GND1 GND2 +3.3V_PCIE_WWAN 4 CLK GND_3 13
+3.3V_PCIE_WWAN 5 D+ GND_4 14
1 1 1 GND_1 GND_5
@ C639
@ C636
BELLW_80003-8041 +UIM_VPP 6 15
VPP GND_6
C616
CONN@ UIM_DATA 7 16
I/O GND_7
150U_D2_6.3VY_R15M
100K_0402_5%
8 17
2 2 2 D- GND_8
0.047U_0402_16V4Z
0.047U_0402_16V4Z
33P_0402_50V8J
22U_0805_6.3V6M
33P_0402_50V8J
9 18
DET GND_9
2
1 10
COM
R719
33P_0402_50V8J
33P_0402_50V8J
33P_0402_50V8J
33P_0402_50V8J
1 1 1 1 1
C615
+
1 1 1 1
C610
C611
C612
C613
C614
@ C631
@ C630
@ C628
@ C629
T-SOL_159-1000302602
2
G
CONN@
1
2 2 2 2 2 2
LED_WWAN_OUT# 3 1 2 2 2 2
WIRELESS_LED# <24,37,45>
D
Q77
L2N7002WT1G_SC-70-3
C C
B B
A A
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD B
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 4019MV
5 4 3 2 1
5 4 3 2 1
+3.3V_PCIE_WWAN/+3.3V_PCIE_FLASH
D
+1.5V_RUN +3.3V_RUN +3.3V_SUS

Express Card PWR S/W +3.3V_CARDAUX +3.3V_CARD +1.5V_CARD
D
+3.3V_PCIE_WWAN
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
10U_0603_6.3V6M
0.1U_0402_25V6
10U_0603_6.3V6M
0.1U_0402_25V6
10U_0603_6.3V6M
@ C446
U145 10U_0603_6.3V6M
2 1 +3.3V_ALW 1 14 1 2 1 1 1 1 1 1 1 1 1
R726 100K_0402_5% 2 VIN1 VOUT1 13
VIN1 VOUT1
C635
C634
C633
C642
C643
C640
C641
C637
C638
3 12 1 2
<45> MCARD_WWAN_PWREN ON1 CT1 2 2 2 2 2 2 2 2 2
C445 470P_0402_50V7K
+5V_ALW 4 11
VBIAS GND U41
5 10 1 2 17 15
<45> MCARD_MISC_PWREN ON2 CT2 AUXIN AUXOUT
C450 470P_0402_50V7K 2 3
6 9 12 3.3VIN 3.3VOUT 11
2 1 7 VIN2 VOUT2 8 1.5VIN 1.5VOUT
VIN2 VOUT2 +3.3V_PCIE_FLASH
R733 100K_0402_5% 1 @ R734 1 2 0_0402_5% 20 8 CARD_RESET#
<16,35,40,45,53> SIO_SLP_S3# SHDN# PERST#
15 1 2 EXPRCRD_STBY_R# 1 10 EXPRCRD_CPPE#
GPAD <32,45,48,53> RUN_ON STBY# CPPE#
@ C449 <16,35,37,38,45,46> PCH_PLTRST#_EC @ R717 0_0402_5% 6 9 CPUSB#
TPS22966DPUR_SON14_2X3 19 SYSRST# CPUSB#
10U_0603_6.3V6M OC#
2
0.1U_0402_25V6
EMC@ CE10
0.1U_0402_25V6
EMC@ CE11
EMC@ CE12
0.1U_0402_25V6
+3.3V_RUN 4 1 1 1
5 NC 18
+3.3V_CARD NC RCLKEN
+1.5V_CARD 13
14 NC 7
+1.5V_RUN NC GND 2 2 2
16 21
NC PAD
TPS2231MRGPR-2_QFN20_4X4
C C
Note: Add connection on pin4, pin5, pin 13
and pin14 to support GMT 2nd source part
Express Card Conn.
+3.3V_WLAN/+3.3V_LAN source
+3.3V_WLAN
U57
+3.3V_ALW 1 14 1 2
2 VIN1 VOUT1 13 @ C423 10U_0603_6.3V6M
VIN1 VOUT1
3 12 1 2
<37,45> AUX_EN_WOWL ON1 CT1 C444 470P_0402_50V7K
+5V_ALW 4 11
VBIAS GND
5 10 1 2
<16,45> SIO_SLP_LAN# ON2 CT2 C448 470P_0402_50V7K
6 9 +3.3V_SUS
7 VIN2 VOUT2 8
VIN2 VOUT2 +3.3V_LAN
1
15
GPAD
2.2K_0402_5%
2.2K_0402_5%
B @ C447 B
1
TPS22966DPUR_SON14_2X3 10U_0603_6.3V6M
2
R732
R731
JEXP1
2
1 2 CPUSB#
3 1 2 4
<19> USBP10- 3 4
5 6
<19> USBP10+ 5 6 CARD_SMBCLK <46>
7 8
7 8 CARD_SMBDAT <46>
9 10 +1.5V_CARD
<17> CLK_PCIE_EXP# 9 10
11 12
<17> CLK_PCIE_EXP 11 12
0.1U_0402_25V6
13 14 1
15 13 14 16 PCIE_WAKE# <32,36,37,38,46>
<19> PCIE_PRX_EXPTX_N7 15 16 +3.3V_CARDAUX
C645
<19> PCIE_PRX_EXPTX_P7 17 18 CARD_RESET#
17 18
0.1U_0402_25V6
19 20
21 19 20 22 2
<19> PCIE_PTX_EXPRX_N7 21 22 +3.3V_CARD 1 @
23 24
<19> PCIE_PTX_EXPRX_P7 23 24
C646
25 26
27 25 26 28 EXPRCRD_CPPE#
<17> EXPCLK_REQ# 27 28 2
0.1U_0402_25V6
29 30 @
29 30
1
31 32
GND GND
C649
2
@
E-T_1001K-F30C-03L
CONN@
A A
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
Rear Side (JUSB1)
D D
1 2
@ R1605 0_0402_5%
EMC@ L95
1 2 USB3RN1_D-
<19> USB3RN1 1 2
4 3 USB3RP1_D+
<19> USB3RP1 4 3
CMMI21T-900Y-N_0805_4P
1 2
@ R1604 0_0402_5%
1 2
@ R1606 0_0402_5%
C C
EMC@ L96
1 2 USB3TN1_C 1 2 USB3TN1_D-
<19> USB3TN1 1 2
C1533 0.1U_0402_25V6
1 2 USB3TP1_C 4 3 USB3TP1_D+
<19> USB3TP1 4 3
C1534 0.1U_0402_25V6
CMMI21T-900Y-N_0805_4P
1 2
@ R1603 0_0402_5%
1 2
@ R736 0_0402_5%
EMC@ D78
USB3TP1_D+ 1 9 USB3TP1_D+
EMC@ L51
USB3TN1_D- 2 8 USB3TN1_D- USBP0_D- 1 2 USBP0_R_D- +5V_USB_CHG_PWR
1 2 JUSB1
USB3RP1_D+ 4 7 USB3RP1_D+ 1
USBP0_D+ 4 3 USBP0_R_D+ USBP0_R_D- 2 VBUS
4 3 D-
0.1U_0402_25V6
USB3RN1_D- 5 6 USB3RN1_D- 1 USBP0_R_D+ 3
D+
47U_0805_6.3V6M
220U_6.3V_M
DLW21HN900SQ2L_0805_4P 1 1 4
GND
@ C1552
C651
B + USB3RN1_D- 5 B
StdA-SSRX-
2
C654
L30ESDL5V0C3-2_SOT23-3
EMC@ D72
USB3RP1_D+ 6 10
3 1 2 7 StdA-SSRX+ GND 11
@ R740 0_0402_5% 2 2 2 USB3TN1_D- 8 GND-DRAIN GND 12
TVWDF1004AD0_DFN9 USB3TP1_D+ 9 StdA-SSTX- GND 13
StdA-SSTX+ GND
SANTA_373130-1
+5V_ALW CONN@
1
100K_0402_5%
2
R816
1
PWRSHARE_EN#
<45> USB_PWR_SHR_VBUS_EN
<16,35,39,45,53> SIO_SLP_S3#
@ R153 1 2 0_0402_5%
U2
+5V_ALW 2.5A +5V_USB_CHG_PWR
1
D U48
@ R1626 1 2 0_0402_5% SB# 8 1 2 Q48 1 8
<45> USB_PWR_SHR_EN# CB CEN GND VOUT
7 2 USBP0_D- G L2N7002WT1G_SC-70-3 2 7
<19> USBP0- TDM DM VIN VOUT
10U_0603_6.3V6M
0.1U_0402_25V6
6 3 USBP0_D+ +5V_ALW S 3 6
<19> USBP0+
3
5 TDP DP 4 SEL PWRSHARE_EN# 4 VIN VOUT 5

VDD SELCDP EN FLG USB_OC0# <15,19,41,42>
+5V_ALW 9 1 1
Thermal Pad
2
10K_0402_5%
@ C676
G547I2P81U_MSOP8
C675
SLG55594AVTR_TDFN8_2X2
R1614
2 2
0.1U_0402_25V6
1
A A
1
C715
2
L2N7002WT1G_SC-70-3
1
D
@
Q59
USB_PWR_SHR_EN# 2
G
S
3
Title
5 4 3 2 1
5 4 3 2 1
Right Side Top (JUSB2)
D D
C C
EMC@ L107 EMC@ D88

1 2 USBP1_D- USB3RN2_D- 1 9 USB3RN2_D-
<19> USBP1- 1 2
USB3RP2_D+ 2 8 USB3RP2_D+
4 3 USBP1_D+
<19> USBP1+ 4 3 USB3TN2_D- 4 7 USB3TN2_D-
DLW21HN900SQ2L_0805_4P
1 2 USB3TP2_D+ 5 6 USB3TP2_D+
@ R3689 0_0402_5%
1 2
@ R3690 0_0402_5% 3
TVWDF1004AD0_DFN9
EMC@ L108
1 2 USB3RP2_D+
<19> USB3RP2 1 2
4 3 USB3RN2_D-
<19> USB3RN2 4 3 EMC@ D89
CMMI21T-900Y-N_0805_4P USBP1_D- 2
1 2 1
@ R3691 0_0402_5% USBP1_D+ 3
B B
1 2
@ R3696 0_0402_5% L30ESDL5V0C3-2_SOT23-3
D88, D89 must be as close as
EMC@ L109 possible to JUSB2
1 2 USB3TP2_C 1 2 USB3TP2_D+
<19> USB3TP2 1 2
C1519 0.1U_0402_25V6
1 2 USB3TN2_C 4 3 USB3TN2_D-
<19> USB3TN2 4 3
C1518 0.1U_0402_25V6
CMMI21T-900Y-N_0805_4P
1 2
@ R3697 0_0402_5%
1 2
@ R3698 0_0402_5%
+5V_USB_PWR2
JUSB2
USB3TP2_D+ 9
1 SSTX+
USB3TN2_D- 8 VBUS
1 SSTX-
150U_B2_6.3VM_R35M
0.1U_0402_25V6
1 USBP1_D- 2
+5V_USB_PWR2 + 7 D-
GND
C1523
C1524
+5V_ALW U91 USBP1_D+ 3 10
1 8 USB3RP2_D+ 6 D+ GND 11
2 GND VOUT 7 2 2 4 SSRX+ GND 12
3 VIN VOUT 6 USB3RN2_D- 5 GND GND 13
VIN VOUT SSRX- GND
10U_0603_6.3V6M
0.1U_0402_25V6
4 5 USB_OC0#
<42,45> ESATA_USB_PWR_EN# EN FLG USB_OC0# <15,19,40,42>
1 1 LOTES_ABA-USB-116-P04
@ C1525
G547I2P81U_MSOP8 CONN@
C1526
A 2 2 A
place C1523 between JUSB2 and JUSB3
Title
5 4 3 2 1
5 4 3 2 1
Right Side bottom (JUSB3)
D D
C C
EMC@ L111
USB3RP5 1 2 USB3RP5_D+
<19> USB3RP5 1 2
EMC@ D91
USB3RN5 4 3 USB3RN5_D- USB3RN5_D- 1 9 USB3RN5_D-
<19> USB3RN5 4 3
CMMI21T-900Y-N_0805_4P USB3RP5_D+ 2 8 USB3RP5_D+
1 2
@ R3721 0_0402_5% USB3TN5_D- 4 7 USB3TN5_D-
1 2 USB3TP5_D+ 5 6 USB3TP5_D+
@ R3722 0_0402_5%
EMC@ L112 3
C418 1 2 0.1U_0402_25V6 USB3TP5_C 1 2 USB3TP5_D+
<19> USB3TP5 1 2 TVWDF1004AD0_DFN9
C419 1 2 0.1U_0402_25V6 USB3TN5_C 4 3 USB3TN5_D-

<19> USB3TN5 4 3
CMMI21T-900Y-N_0805_4P EMC@ D90
1 2 USBP2_D+ 2
@ R3727 0_0402_5% 1 +5V_USB_PWR3
USBP2_D- 3 JUSB3
1 2 USB3TP5_D+ 9
@ R3728 0_0402_5% 1 SSTX+
L30ESDL5V0C3-2_SOT23-3 USB3TN5_D- 8 VBUS
1 SSTX-
150U_B2_6.3V-M~D
0.1U_0402_25V6
1 USBP2_D- 2
D-
@ C1538
+ 7
GND
C1539
D90, D91 must be as close as USBP2_D+ 3 10
USB3RP5_D+ 6 D+ GND 11
possible to JUSB3 2 2 4 SSRX+ GND 12
EMC@ L110 USB3RN5_D- 5 GND GND 13
USBP2+ 4 3 USBP2_D+ SSRX- GND
<19> USBP2+ 4 3
B LOTES_ABA-USB-116-P04 B
CONN@
USBP2- 1 2 USBP2_D-
<19> USBP2- 1 2
DLW21HN900SQ2L_0805_4P
1 2
@ R3710 0_0402_5%
1 2
@ R3711 0_0402_5% +5V_USB_PWR3 +5V_USB_PWR2
@
+5V_ALW U93 PJP702
1 8 1 2
2 GND VOUT 7 1 2
3 VIN VOUT 6 JUMP_43X79
VIN VOUT
10U_0603_6.3V6M
0.1U_0402_25V6
<41,45> ESATA_USB_PWR_EN# 4 5 USB_OC1#

EN FLG USB_OC1# <15,19>
1 1
@ C1540
@ C1541
G547I2P81U_MSOP8 1 2
@ R3773 0_0402_5% USB_OC0# <15,19,40,41>
2 2
A A
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
D D
C C
I/O board CONN.
JIO1
2 1
<16> XFR_ID# 4 2 1 3
<25> VSYNC_BUF 4 3 RED_CRT <25>
6 5
<25> HSYNC_BUF 6 5 GREEN_CRT <25>
8 7
B 8 7 BLUE_CRT <25> B
10 9
<25> DAT_DDC2_CRT 10 9
12 11
<25> CLK_DDC2_CRT 12 11
14 13
+5V_ALW 16 14 13 15 +5V_ALW
+5V_RUN 16 15
18 17 +3.3V_RUN
20 18 17 19
20 19
0.1U_0402_25V6
22 21
24 22 21 23
24 23 1
@ C50
1 26 25
28 26 25 27 @ C998
<15,19> USB_OC4# 30 28 27 29
30 29 USB3RN6 <19> 0.1U_0402_25V6
32 31 2
2 <19> USBP9+ 32 31 USB3RP6 <19>
34 33
<19> USBP9- 34 33
36 35
36 35 USB3TN6 <19>
38 37
<45> USB_SIDE_EN# 38 37 USB3TP6 <19>
40 39
40 39
DETECT_GND
42 41
G2 G1
E&T_1000K-Y40E-02L
CONN@
+5V_RUN
0.1U_0402_25V6
1
@ C1001
A A
Close to JIO1.16/18
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
JDOCK1 CONN@
DOCK_DET_1 1 2 DOCK_AC_OFF
3 1 2 4 DOCK_AC_OFF <56>
<33> DOCK_LOM_SPD10LED_GRN# DPD_CA_DET 5 3 4 6 DPC_CA_DET DOCK_LOM_SPD100LED_ORG# <33>
<29> DPD_CA_DET 7 5 6 8 DPC_CA_DET <29>
C690 2 1 0.1U_0402_25V6 DPD_CPU_LANE_P0_C EMC@ 2 RE7 133_0402_5% DPD_DOCK_LANE_P0 9 7 8 10 DPC_DOCK_LANE_P0 EMC@ 1 RE17 2 33_0402_5% DPC_CPU_LANE_P0_C C691 2 1 0.1U_0402_25V6
D <9> DPD_CPU_LANE_P0 9 10 DPC_CPU_LANE_P0 <9> D
C679 2 1 0.1U_0402_25V6 DPD_CPU_LANE_N0_C EMC@ 2 RE8 133_0402_5% DPD_DOCK_LANE_N0 11 12 DPC_DOCK_LANE_N0 EMC@ 1 RE18 2 33_0402_5% DPC_CPU_LANE_N0_C C680 2 1 0.1U_0402_25V6
<9> DPD_CPU_LANE_N0 11 12 DPC_CPU_LANE_N0 <9>
13 14
<9> DPD_CPU_LANE_P1 15 16 DPC_CPU_LANE_P1 <9>
19 20
25 26
31 32
DPD_DOCK_AUX 33 31 32 34 DPC_DOCK_AUX
<29> DPD_DOCK_AUX 33 34 DPC_DOCK_AUX <29>
DPD_DOCK_AUX# 35 36 DPC_DOCK_AUX#
<29> DPD_DOCK_AUX# 35 36 DPC_DOCK_AUX# <29>
37 38
DPD_PCH_DOCK_HPD 39 37 38 40 DPC_PCH_DOCK_HPD
<16> DPD_PCH_DOCK_HPD 39 40 DPC_PCH_DOCK_HPD <16>
+NBDOCK_DC_IN_SS 41 42
41 42 ACAV_DOCK_SRC# <56>
0.033U_0402_16V7K
0.033U_0402_16V7K
1 43 44 1
BLUE_DOCK 45 43 44 46
<25> BLUE_DOCK 45 46 DAT_DDC2_DOCK <25>
47 48
47 48 CLK_DDC2_DOCK <25>
@ C695
@ C696
49 50 Close to DOCK
2 51 49 50 52 2
RED_DOCK 53 51 52 54 SATA_PRX_DKTX_P2 2 1 Its for Enhance ESD on dock issue.
<25> RED_DOCK 53 54 SATA_PRX_DKTX_P2_C <15>
Close to DOCK 55 56 SATA_PRX_DKTX_N2 C697 2 1 0.01U_0402_16V7K
55 56 SATA_PRX_DKTX_N2_C <15>
57 58 C698 0.01U_0402_16V7K
Its for Enhance ESD on dock issue. GREEN_DOCK 59 57 58 60 SATA_PTX_DKRX_P2 1 2
<25> GREEN_DOCK 59 60 SATA_PTX_DKRX_P2_C <15>
61 62 SATA_PTX_DKRX_N2 C699 1 2 0.01U_0402_16V7K
63 61 62 64 C700 0.01U_0402_16V7K SATA_PTX_DKRX_N2_C <15> L99 @
65 63 64 66 USBP6_R_D+ 3 4
<25> HSYNC_DOCK 65 66 3 4 USBP6+ <19>
67 68 USBP6_R_D-
<25> VSYNC_DOCK 67 68
69 70
DPD_PCH_DOCK_HPD 71 69 70 72 2 1
<46> CLK_MSE 71 72 USBP3+ <19> 2 1 USBP6- <19>
73 74
C <46> DAT_MSE 73 74 USBP3- <19> C
75 76 DLW21SN900HQ2L_0805_4P
77 75 76 78 @ R1672 1 2 0_0402_5%
<30> DAI_BCLK# 77 78 CLK_KBD <46>
1
79 80
<30> DAI_LRCK# 79 80 DAT_KBD <46>
81 82
R757 83 81 82 84 @ R1673 1 2 0_0402_5%
<30> DAI_DI 83 84 USB3RN3 <19>
100K_0402_5% 85 86
<30> DAI_DO# 85 86 USB3RP3 <19>
87 88
2
89 87 88 90
<30> DAI_12MHZ# 89 90 USB3TN3 <19>
91 92
91 92 USB3TP3 <19>
93 94
95 93 94 96
97 95 96 98 DPC_PCH_DOCK_HPD
<45> D_LAD0 97 98 BREATH_LED# <24,45>
99 100
<45> D_LAD1 99 100 DOCK_LOM_ACTLED_YEL# <33>
101 102
101 102
100K_0402_5%
103 104
<45> D_LAD2 103 104 DOCK_LOM_TRD0+ <33>
1
105 106
<45> D_LAD3 105 106 DOCK_LOM_TRD0- <33>
R758
107 108
109 107 108 110
<45> D_LFRAME# 109 110 DOCK_LOM_TRD1+ <33> +LOM_VCT
111 112
<45> D_CLKRUN# 111 112 DOCK_LOM_TRD1- <33>
113 114
2
113 114
1U_0402_6.3V6K
115 116 1
<45> D_SERIRQ 115 116
@ C701
117 118 +LOM_VCT
<45> D_DLDRQ1# 117 118
119 120
CLK_PCI_DOCK 121 119 120 122
<17> CLK_PCI_DOCK 121 122 DOCK_LOM_TRD2+ <33> 2
123 124
123 124 DOCK_LOM_TRD2- <33>
125 126
127 125 126 128 +3.3V_ALW
<46> DOCK_SMB_CLK 127 128 DOCK_LOM_TRD3+ <33>
129 130
<46> DOCK_SMB_DAT 129 130 DOCK_LOM_TRD3- <33>
131 132
133 131 132 134 DOCK_DET# 1 2
<45,49,56> DOCK_SMB_ALERT# 133 134 DOCK_DCIN_IS+ <55>
135 136 10K_0402_5% R755
<49> DOCK_PSID 135 136 DOCK_DCIN_IS- <55>
137 138
B 139 137 138 140 D32 B
<46> DOCK_PWR_BTN# 139 140 DOCK_POR_RST# <46>
141 142 RB751V40_SC76-2
143 141 142 144 DOCK_DET_R# 1 2
<45,49,56> SLICE_BAT_PRES# 143 144 DOCK_DET# <45,56>
145 149 +DOCK_PWR_BAR
146 GND1 PWR2 150
+DOCK_PWR_BAR PWR1 PWR2
0.1U_0603_50V7K
147 151
PWR1 PWR2
0.1U_0603_50V7K
148 152
PWR1 GND2
3
2
4.7U_0805_25V6-K
L30ESD24VC3-2_SOT23-3
C703
1 1 153 159
Shield_G Shield_G
@
C702
@ D33
154 160
Shield_G Shield_G
CE6
155 161
156 Shield_G Shield_G 162 2 @
2 2 @ 157 Shield_G Shield_G 163
158 Shield_G Shield_G 164
Shield_G Shield_G
1
JAE_WD2F144WB1R300~D
CLK_PCI_DOCK
1
@ R3761
33_0402_5%
10P_0402_50V8J
2
A A
1
@
C1551
2
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
@ PJP63
+3.3V_ALW_5048 1 2
+3.3V_ALW
10U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
PAD-OPEN1x1m
1 2 DYN_TURB_PWR_ALRT#
@ R796 10K_0402_5% 1 1 1 1 1 1
C705
C706
C707
C708
C709
C710
RP4
1 8 PROCHOT_GATE
D 2 7 USB_PWR_SHR_EN# 2 2 2 2 2 2 D
3 6 ESATA_USB_PWR_EN#
4 5 SLICE_BAT_PRES#
A17
B30
A43
A54
B5
100K_0804_8P4R_5% U46 SMSC feedback disconnect LPC_LDRQ0# at A23 pin
VCC1
VCC1
VCC1
VCC1
VCC1
RP3 A23 PAD~D T147 @
1 8 USB_PWR_SHR_VBUS_EN B52 GPIOI0 B63
<25> CRT_SWITCH GPIOA0 GPIOI1 SIO_SLP_A# <16,35,52>
2 7 WWAN_RADIO_DIS# A49 A60 0.75V_DDR_VTT_ON
3 6 CPU_DETECT# B53 GPIOA1 GPIOI2/TACH0 A61 0.75V_DDR_VTT_ON <51>
<39> MCARD_MISC_PWREN GPIOA2 GPIOI3 SIO_SLP_S4# <16,35,51>
4 5 WIRELESS_ON#/OFF <55> PROCHOT_GATE PROCHOT_GATE A50 B65
GPIOA3 GPIOI4 SIO_SLP_S3# <16,35,39,40,53>
LID_CL_SIO# B54 A62
GPIOA4 GPIOI5 IMVP_PWRGD <54>
100K_0804_8P4R_5% DOCK_SMB_ALERT# A51 B66
<44,49,56> DOCK_SMB_ALERT# GPIOA5 GPIOI6 IMVP_VR_ON <54>
TOUCH_SCREEN_PD# B55 A63
RP2 <28> TOUCH_SCREEN_PD# A52 GPIOA6 GPIOI7 DOCK_AC_OFF_EC <56>
1 8 HW_GPS_DISABLE2# GPIOA7 B67
2 7 USB_SIDE_EN# USB_SIDE_EN# A33 GPIOJ0 A64 AUX_EN_WOWL <37,39>
<43> USB_SIDE_EN# GPIOB0 GPIOJ1/TACH1 WLAN_LAN_DISB# <33>
3 6 TOUCH_SCREEN_PD# B36 A5 SIO_SLP_LAN#
<30> EN_I2S_NB_CODEC# GPIOB1 GPIOJ2/TACH2 SIO_SLP_LAN# <16,39>
4 5 DOCK_SMB_ALERT# A34 B6
<35> USH_PWR_STATE# GPOC2 GPIOJ3 SIO_SLP_SUS# <16>
<56> EN_DOCK_PWR_BAR B37 A6
10K_8P4R_5% A35 GPOC3 GPIOJ4 B7 GPIO_PSID_SELECT <49>
<28> PANEL_BKEN_EC GPOC4 GPIOJ5 MODC_EN <32>
+3.3V_RUN B38 A7
<16> ENVDD_PCH GPOC5 GPIOJ6 DOCK_HP_DET <30>
LCD_TST A36 B8
<28> LCD_TST GPOC6/TACH4 GPIOJ7 DOCK_MIC_DET <30>
1 2 SP_TPM_LPC_EN A37
@ R772 10K_0402_5% <49> PSID_DISABLE# B40 GPIOC7 A8 ME_FWP
<49,56> PBAT_PRES# GPIOD0 GPIOK0 ME_FWP <15>
A38 B9
<33> DOCKED GPIOC1 GPIOK1/TACH3 MASK_SATA_LED# <24>
B41 B10 USB_PWR_SHR_EN#
<44,56> DOCK_DET# GPIOC0 GPIOK2 USB_PWR_SHR_EN# <40>
1 2 DP_HDMI_HPD A39 A10 +3.3V_RUN
<30> AUD_NB_MUTE# GPIOB7 GPIOK3 LED_SATA_DIAG_OUT# <24>
@ R1154 100K_0402_5% B42 B11 TEMP_ALERT#_R 1 2
<39> MCARD_WWAN_PWREN GPIOB6 GPIOK4 TEMP_ALERT# <17,18>
A40 A11 RUN_ON @ R738 0_0402_5% RP5
<28> LCD_VCC_TEST_EN GPIOB5 GPIOK5 RUN_ON <32,39,48,53>
B43 B12 D_CLKRUN# 4 5
<28> CCD_OFF GPIOB4 GPIOK6 AC_DIS <49,56>
A41 A12 D_SERIRQ 3 6
<30> AUD_HP_NB_SENSE GPIOB3 GPIOK7 SPI_WP#_SEL <18>
ESATA_USB_PWR_EN# B44 D_DLDRQ1# 2 7
<41,42> ESATA_USB_PWR_EN# GPIOB2 B60 SUS_ON SLICE_BAT_ON 1 8
GPIOL0/PWM7 SUS_ON <48,51>
A57
C
B32 GPIOL1/PWM8 B64 100K_0804_8P4R_5% C
GPIOD1 GPIOL2/PWM0 BAT1_LED# <24> trace width 10 mils
<56> SLICE_BAT_ON A31 B68
B33 GPIOD2 GPIOL3/PWM1 A9
<44,49,56> SLICE_BAT_PRES# GPIOD3 GPIOL4/PWM3 BAT2_LED# <24> trace width 10 mils
MODULE_BATT_PRES# B15 B1
<55> MODULE_BATT_PRES# A15 GPIOD4 GPIOL5/PWM2 A18 USH_PWR_ON
GPIOD5 GPIOL6 USH_PWR_ON <48>
B16 A44 PAD~D T146 @ RP6
A16 GPIOD6 GPIOL7/PWM5 RUN_ON 1 8
GPIOD7 B34 HW_GPS_DISABLE2# CPU_VTT_ON 2 7
GPIOM1 HW_GPS_DISABLE2# <38>
B39 0.75V_DDR_VTT_ON 3 6
GPIOM3/PWM4 BREATH_LED# <24,44>
A1 B51 SUS_ON 4 5
<37> WIGIG60GHZ_DIS# GPIOE0/RXD GPIOM4/PWM6 DIS_BAT_PROCHOT# <56>
B2
<37,45,46> EC5048_TX GPIOE1/TXD
A2 100K_0804_8P4R_5%
B3 GPIOE2/RTS# A27
<15,20> MCARD_PCIE_SATA# GPIOE3/DSR# LAD0 LPC_LAD0 <18,35,37,46>
CPU_DETECT# A3 A26
<7> CPU_DETECT# GPIOE4/CTS# LAD1 LPC_LAD1 <18,35,37,46>
B45 B26
GPIOE5/DTR# LAD2 LPC_LAD2 <18,35,37,46>
A42 B25
<32> MOD_SATA_PCIE#_DET GPIOE6/RI# LAD3 LPC_LAD3 <18,35,37,46>
DP_HDMI_HPD B4 A21 LPC_LFRAME# RP19
GPIOE7/DCD# LFRAME# LPC_LFRAME# <18,35,37,46>
B22 PCH_PLTRST#_EC LID_CL_SIO# 1 8 +3.3V_ALW
LRESET# PCH_PLTRST#_EC <16,35,37,38,39,46>
A28 <15,32> USB30_SMI# USB30_SMI# 2 7 +3.3V_ALW_PCH
PCICLK CLK_PCI_5048 <17>
A59 B20 CLKRUN# CHARGE_EN 3 6
<32> ZODD_WAKE# GPIOF0 CLKRUN# CLKRUN# <16,35,46>
B62 LCD_TST 4 5
<35> BCM5882_ALERT# GPIOF1
A58 A22 LPC_LDRQ1#
<16> SUSACK# GPIOF2 LDRQ1# LPC_LDRQ1# <18>
B61 B21 100K_0804_8P4R_5%
GPIOF3/TACH8 SER_IRQ IRQ_SERIRQ <17,18,35,46>
A56 A32
GPIOF4/TACH7 14.318MHZ/GPIOM0 CLK_SIO_14M <17>
VGA_ID B59 B35 EC_32KHZ_ECE5048 <46>
A55 GPIOF5 CLK32/GPIOM2
B58 GPIOF6
<20> SLP_ME_CSW_DEV# GPIOF7 B29
DLAD0 B28 D_LAD0 <44>
B47 DLAD1 A25 D_LAD1 <44>
<33> LAN_DISABLE#_R GPIOG0/TACH5 DLAD2 D_LAD2 <44>
CHARGE_EN A45 A24
SYS_LED_MASK# B48 GPIOG1 DLAD3 B23 D_LAD3 <44>
<24,32,33> SYS_LED_MASK# GPIOG2 DLFRAME# D_LFRAME# <44>
DYN_TURB_PWR_ALRT# A46 A19 D_CLKRUN#
GPIOG3 DCLKRUN# D_CLKRUN# <44>
<15,17,20> SIO_EXT_WAKE# B49 B24 D_DLDRQ1#
GPIOG4 DLDRQ1# D_DLDRQ1# <44>
B A47 A20 D_SERIRQ B
<24,37,38> WIRELESS_LED# GPIOG5 DSER_IRQ D_SERIRQ <44>
USB_PWR_SHR_VBUS_EN B50
<40> USB_PWR_SHR_VBUS_EN A48 GPIOG6
<37> WLAN_RADIO_DIS# GPIOG7/TACH6 A29
BC_INT# BC_INT#_ECE5048 <46>
B31
+3.3V_ALW BC_DAT BC_DAT_ECE5048 <46>
WIRELESS_ON#/OFF B13 A30
<47> WIRELESS_ON#/OFF GPIOH0 BC_CLK BC_CLK_ECE5048 <46>
A13
<37> BT_RADIO_DIS# GPIOH1
WWAN_RADIO_DIS# A53
<38> WWAN_RADIO_DIS# SYSOPT1/GPIOH2
1 2 VGA_ID B57 A4
<7,16> SYS_PWROK SYSOPT0/GPIOH3 PWRGD AND_PWRGD <46>
R800 100K_0402_5% @ T122 PAD~D B14
A14 GPIOH4 B56 SP_TPM_LPC_EN
<16> SIO_SLP_WLAN# GPIOH5 OUT65 SP_TPM_LPC_EN <35>
2 1 VGA_ID CPU_VTT_ON B17
@ R803 100K_0402_5% 1 2 B18 GPIOH6
<16> PCH_DPWROK GPIOH7
@ R802 0_0402_5% B19 1 2
TEST_PIN R804 1K_0402_5%
B46 +CAP_LDO
CAP_LDO
4.7U_0603_6.3V6K
1
B27
VSS
C714
C1
EP
VGA_ID0 DB Version 0.4 2 CLK_SIO_14M
Discrete 0 ECE5048-LZY_DQFN132_11X11~D
10_0402_1%
1
UMA 1 LID_CL_SIO# 2 1
LID_CL# <24,47>
@ R794
R807 10_0402_1%
0.047U_0402_16V4Z
1
+CAP_LDO trace width 20 mils
1 2 USB_PWR_SHR_EN#
<37,45,46> EC5048_TX
C716
@ R806 0_0402_5%
2
4.7P_0402_50V8C
ME_FWP PCH has internal 20K PD.
1
@ C712
ME_FWP
1
A 2 A
1K_0402_5%
@ R793
2
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
@ C721 @ C733
@ C720 1 2 1 2
1 2
1U_0402_6.3V6K 1U_0402_6.3V6K
0.1U_0402_25V6
5
+RTC_CELL POWER_SW_IN# 1 2 DOCK_PWR_SW# 1 2
POWER_SW#_MB <24,35> DOCK_PWR_BTN# <44>
R811 10K_0402_5% R825 10K_0402_5%
VCC
1U_0402_6.3V6K
1U_0402_6.3V6K
ECE5048_PWRGD 1 1 2 +RTC_CELL_VBAT 1 1
IN B 4 @ R830 0_0402_5%
OUT Y AND_PWRGD <45> remove unstuff components??
0.1U_0402_25V6
C722
C734
RUNPWROK 2
GND
IN A
@ U50 2 2
1
C724
+1.05V_RUN
10K_0402_5%
1 2
1
@ R1179
@ R1180 0_0402_5%
D D
U51
1 2 +3.3V_ALW 1 2 +3.3V_VTR
@ R3772 0_0402_5% @ R834 0_0402_5% B64 A10 SYSTEM_ID
VBAT GPIO021/RC_ID1 H_PROCHOT# <7,54,55,56>
0.1U_0402_25V6
1U_0402_6.3V4Z
B10 BOARD_ID
2
GPIO020/RC_ID2
L2N7002WT1G_SC-70-3
1 1 B8 R888 1 2 1K_0402_5%
GPIO014/GPTP-IN7/RC_ID3 VOL_UP# <47>
1
@ R8391 2 0_0402_5% A22 B27 D
+3.3V_ALW H_VTR GPIO025/UART_CLK LANWAKE# <20,33>
C739
C775
Q47
B44 HOST_DEBUG_TX PROCHOT#_EC 2
GPIO120/UART_TX HOST_DEBUG_TX <37>
0.1U_0402_25V6
1U_0402_6.3V4Z
+3.3V_ALW B46 HOST_DEBUG_RX G
2 2 +3.3V_VTR_ADC A58 GPIO124/GPTP-OUT5/UART_RX B26 RUNPWROK
@
1 1 S
3
VTR_ADC VCC_PWRGD RUNPWROK <7>
100K_0402_5%
A25 EN_INVPWR
GPIO060/KBRST/BCM_B_INT# EN_INVPWR <28>
2
C736
C757
1 2 BC_DAT_ECE1117 B36
GPIO101/ECGP_SCLK/GANG_DATA5 PCH_SATA_MOD_EN# <15>
@ R812
R817 100K_0402_5% B3 B37
RP7 2 2 A11 VTR GPIO103/ECGP_MISO/GANG_DATA7 B38 PCIE_WAKE# SLICE_PERF_EN <56>
VTR GPIO105/ECGP_MOSI PCIE_WAKE# <32,36,37,38,39>
1 8 PCIE_WAKE# A26 A34 ECE5048_PWRGD
2 7 HOST_DEBUG_RX +3.3V_ALW B35 VTR GPIO102/BCM_C_INT#/GANG_DATA6 A35 DYN_TUR_CURRNT_SET#
1
3 6 CHARGER_SMBDAT @ PJP65 A41 VTR GPIO104 A36 DYN_TUR_CURRNT_SET# <55>
4 5 CHARGER_SMBCLK 1 2 +3.3V_ALW_VTR A52 VTR GPIO106 A40 MSDATA
VTR GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP MSDATA <37>
B43 MSCLK
GPIO117/MSCLK/V2P_COUT_HI MSCLK <37>
10U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
10K_8P4R_5% PAD-OPEN1x1m A45
GPIO127/A20M SIO_A20GATE <20>
1 1 1 1 1 1 1 B65 FWP#
A5 NFWP
<18> SML1_SMBDATA GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA/GANG_BUSY
C781
C759
C774
C776
C777
C780
C782
B6
<18> SML1_SMBCLK GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_ERROR
+5V_RUN A37 B57 R887 1 2 1K_0402_5%
2 2 2 2 2 2 2 <47> CLK_TP_SIO GPIO110/PS2_CLK2/GPTP-IN6 GPIO156/LED0 VOL_DOWN# <47>
B40 B1 @ R1070 1 2 0_0402_5% DEVICE_DET#
<47> DAT_TP_SIO GPIO111/PS2_DAT2/GPTP-OUT6 GPIO157/LED1 DEVICE_DET# <32>
CLK_KBD A38 A55 PS_ID +RTC_CELL
<44> CLK_KBD GPIO112/PS2_CLK1A GPIO153/LED2 PS_ID <49>
RP8 DAT_KBD B41 A1
1 8 <44> DAT_KBD A39 GPIO113/PS2_DAT1A GPIO027/GPTP-OUT1 B28 ALW_PWRGD_3V_5V <50>
CLK_KBD CLK_MSE RP15
<44> CLK_MSE GPIO114/PS2_CLK0A GPIO026/GPTP-IN1 1.05V_A_PWRGD <52>
2 7 DAT_KBD DAT_MSE B42 B2 1 2 VCI_IN3# 1 8
<44> DAT_MSE GPIO115/PS2_DAT0A GPIO001/ECSPI_CS1 VOL_MUTE# <47>
3 6 CLK_MSE PBAT_SMBDAT B59 A8 R884 1K_0402_5% DOCK_PWR_SW# 2 7
<49> PBAT_SMBDAT GPIO154/I2C1C_DATA/PS2_CLK1B GPIO015/GPTP-OUT7/GANG_DATA3 ME_SUS_PWR_ACK <16>
4 5 DAT_MSE PBAT_SMBCLK A56 B9 1.35V_SUS_PWRGD POWER_SW_IN# 3 6
<49> PBAT_SMBCLK GPIO155/I2C1C_CLK/PS2_DAT1B GPIO016/GPTP-IN8/GANG_DATA4 1.35V_SUS_PWRGD <7,51>
A9 LAT_ON_SW# 4 5
A51 GPIO017/GPTP-OUT8 B39 PM_APWROK <16>
4.7K_8P4R_5% JTAG_TDI RESET_OUT#
GPIO145/I2C1K_DATA/JTAG_TDI GPIO107/NRESET_OUT RESET_OUT# <10,15,16>
JTAG_TDO B55 A44 100K_0804_8P4R_5%
+3.3V_ALW JTAG_CLK B56 GPIO146/I2C1K_CLK/JTAG_TDO GPIO125/GPTP-IN5 B47 PCH_RSMRST# PCH_PCIE_WAKE# <16>
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK GPIO126 PCH_RSMRST# <47>
JTAG_TMS A53 A54 AC_PRESENT
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS GPIO151/GPTP-IN4 AC_PRESENT <16>
RP14 JTAG_RST# A57 B58
1 8 JTAG_RST# GPIO152/GPTP-OUT4 SIO_PWRBTN# <16>
PBAT_SMBDAT
2 7 PBAT_SMBCLK DOCK_POR_RST# FAN1_TACH_FB B22 A3 DOCK_SMB_DAT
GPIO050/FAN_TACH1/GTACH GPIO003/I2C1A_DATA/GANG_MODE DOCK_SMB_DAT <44>
3 6 GPU_SMBDAT DOCK_POR_RST# A21 B4 DOCK_SMB_CLK
<44> DOCK_POR_RST# GPIO051/FAN_TACH2 GPIO004/I2C1A_CLK/GANG_START DOCK_SMB_CLK <44>
4 5 GPU_SMBCLK B23 A4 LCD_SMBDAT +3.3V_ALW
<20> EC_WAKE# GPIO052/FAN_TACH3 GPIO005/I2C1B_DATA/BCM_B_DAT/GANG_STROBE
A_ON B24 B5 LCD_SMBCLK
<48,52> A_ON GPIO053/PWM0 GPIO006/I2C1B_CLK/BCM_B_CLK/GANG_FULL
0.1U_0402_25V6
2.2K_0804_8P4R_5% PCH_ALW_ON A23 B7 BAY_SMBDAT LCD_SMBCLK 2 1
<48> PCH_ALW_ON GPIO054/PWM1 GPIO012/I2C1H_DATA/I2C2D_DATA/GANG_DATA1 BAY_SMBDAT <32>
+3.3V_RUN 1 <28> BIA_PWM_EC B25 A7 BAY_SMBCLK 2.2K_0402_5% R418 @
C737 GPIO055/PWM2 GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA2 BAY_SMBCLK <32>
FAN1_PWM A24 B48 GPU_SMBDAT LCD_SMBDAT 2 1
GPIO056/PWM3/GPWM GPIO130/I2C2A_DATA/BCM_C_DAT B49 GPU_SMBCLK 2.2K_0402_5% R420 @
+3.3V_RUN GPIO131/I2C2A_CLK/BCM_C_CLK A47 CHARGER_SMBDAT RP10
2 GPIO132/I2C1G_DATA B50 CHARGER_SMBDAT <55>
CHARGER_SMBCLK
GPIO140/I2C1G_CLK CHARGER_SMBCLK <55>
RP17 A43 B52 DOCK_SMB_DAT 1 8
<45> BC_CLK_ECE5048 GPIO123/BCM_A_CLK GPIO141/I2C1F_DATA/I2C2B_DATA CARD_SMBDAT <39>
1 8 RUNPWROK BC_DAT_ECE5048 B45 A49 DOCK_SMB_CLK 2 7
<45> BC_DAT_ECE5048 GPIO122/BCM_A_DAT GPIO142/I2C1F_CLK/I2C2B_CLK CARD_SMBCLK <39>
C +PCH_VCCDSW3_3 2 7 AC_PRESENT A42 B53 BAY_SMBDAT 3 6 C
<45> BC_INT#_ECE5048 GPIO121/BCM_A_INT# GPIO143/I2C1E_DATA USH_SMBDAT <35>
3 6 MSDATA B20 A50 BAY_SMBCLK 4 5
<55,56> ACAV_IN_NB GPIO032/BCM_E_CLK GPIO144/I2C1E_CLK USH_SMBCLK <35>
4 5 PCH_RSMRST# A18
Place close pin A21 <16,35> SIO_SLP_S5#
B19 GPIO031/GPTP-OUT2/BCM_E_DAT A59 SYSPWR_PRES 1 2 2.2K_8P4R_5%
<30> BEEP GPIO030/GPTP-IN2/BCM_E_INT# SYSPWR_PRES +3.3V_ALW2
10K_8P4R_5% A20 R874 1K_0402_5%
<47> BC_CLK_ECE1117 BC_DAT_ECE1117 B21 GPIO047/LSBCM_D_CLK A64 DYN_TUR_CURRNT_SET# 2 1
<47> BC_DAT_ECE1117 GPIO046/LSBCM_D_DAT VCI_OVRD_IN ACAV_IN <55,56>
A19 A60 100K_0402_5% R1171
<47> BC_INT#_ECE1117 GPIO045/LSBCM_D_INT# VCI_OUT B67 ALWON <50>
POWER_SW_IN#
A6 VCI_IN0# A63 DOCK_PWR_SW# +3.3V_ALW
<15,19> SIO_EXT_SMI# GPIO011/nSMI/GANG_DATA0 VCI_IN1#
RP9 A27 B63 LAT_ON_SW# R866 close to U51 at least 250mils
1 8 <20> SIO_RCIN# A28 GPIO061/LPCPD# VCI_IN2# B68 VCI_IN3# RP16
2 7 EN_INVPWR <17,18,35,45> IRQ_SERIRQ B30 SER_IRQ VCI_IN3# BC_DAT_ECE5048 1 8
3 6 <16,35,37,38,39,45> PCH_PLTRST#_EC A29 LRESET# B51 1 2 2 7
PCH_ALW_ON +PECI_VREF +1.05V_RUN JTAG_RST#
<17> CLK_PCI_MEC PCI_CLK VREF_PECI
4 5 DOCK_POR_RST# B31 A48 PECI_EC_R 1 2 @ R866 0_0402_5% DEVICE_DET# 3 6
<18,35,37,45> LPC_LFRAME# LFRAME# PECI_DAT PECI_EC <7>
0.1U_0402_25V6
A30 R952 43_0402_5% 1 SYSPWR_PRES 4 5
<18,35,37,45> LPC_LAD0 LAD0
100K_0804_8P4R_5% B32
<18,35,37,45> LPC_LAD1 LAD1
C740
A31 B13 REM_DIODE1_N C285 1 2 2200P_0402_50V7K 100K_0804_8P4R_5%
<18,35,37,45> LPC_LAD2 LAD2 DN1-THERM
1 2 RESET_OUT# B33 A13 REM_DIODE1_P
<18,35,37,45> LPC_LAD3 LAD3 DP1-VREF_T 2
@ R843 8.2K_0402_5% A32 B14 REM_DIODE2_N C283 1 2 2200P_0402_50V7K
<16,35,45> CLKRUN# CLKRUN# DN2
A33 A14 REM_DIODE2_P
<20> SIO_EXT_SCI# GPIO100/NEC_SCI DP2 A15
1 2 A_ON MEC_XTAL1 A61 DN3 B16
R424 47K_0402_5% MEC_XTAL2 2 1 MEC_XTAL2_R A62 XTAL1 DP3 A16 REM_DIODE4_N C286 1 2 2200P_0402_50V7K
@ R1068 0_0402_5% B62 XTAL2 DN4 B17 REM_DIODE4_P
<45> EC_32KHZ_ECE5048 GPIO160/32KHZ_OUT DP4
GPIO MAP 1.8 B15
VIN A17 VSET_5075
C283, C285, C286 Place near U51
VSET A12 VCP
VCP VCP <55>
B34 THERMATRIP2#
THERMTRIP2# A2 THERMATRIP3#
GPIO002/THERMTRIP3# B29 THSEL_STRAP
VSS_ADC
GPIO024/THSEL_STRAP
VSS_RO
VR_CAP
A46 PROCHOT#_EC
32 KHz Clock
H_VSS
PROCHOT_IN#/PROCHOT_IO#
AGND
B61 V_SYS_R 1 2 +3.3V_ALW
V_SYS <55>
VSS
V_ISYS R392 4.7K_0402_5%
EP
MEC5075-LZY_DQFN132_11X11~D
B66
B11
B60
+VR_CAP B12
B54
B18
C1
JTAG_RST# MEC_XTAL1 1 2 MEC_XTAL2
C290 Place near U51.A48
1
15mil PECI_EC_R 1 2
33P_0402_50V8J
33P_0402_50V8J
Y6 @ C290 47P_0402_50V8J R52

1
1 32.768KHZ_12.5PF_Q13FC1350000 1 8.2K_0402_5%
1U_0402_6.3V6K
4.7U_0603_6.3V6K
1
1
JTAG1 CONN@
@SHORT PADS~D
100_0402_1%
C743
C741
1 1
2
@
2 2
C735
R836
C779
THSEL_STRAP 1 2 THERMATRIP3#
2 2
0.1U_0402_25V6
R1069 1K_0402_5%
2
2
ESR <2ohms 1
C1563
2
B B
1: Channel 1 will provide Thermistor Readings 2
0: Channel 1 will provide Diode Readings
+3.3V_ALW
R875 C744 REV +3.3V_ALW +3.3V_ALW +3.3V_ALW Channel Location
+3.3V_ALW
240K 4700p X00 DP1/DN1 CPU
1K_0402_5%
10K_0402_5%
1
1
1K_0402_5%
49.9_0402_1%
130K 4700p X01

1
8
7
6
5
R875
R871
R872
DP2/DN2 DIMM
R864
VSET_5075 RP11
33K 4700p X02
0.1U_0402_25V6
10K_8P4R_5%
1.24K_0402_1%
4.3K 4700p *** DP3/DN3 VGA

2
2
1
8
7
6
5
1
100K_0402_5%
1 RUNPWROK
2
1
2
3
4
R407
@ R850
4700P_0402_25V7K
JDEG2 BOARD_ID SYSTEM_ID FWP#
2K 4700p ***
C284
L2N7002WT1G_SC-70-3
1
1 DP4/DN4 V.R
1
2 JTAG_TDI 4700P_0402_25V7K D
2
* 1K 4700p A00 1
2
2
10K_0402_5%
Q45
3 JTAG_TMS 1 2
<7,48> RUN_ON_ENABLE#
2
1
2
3
4
C742
4 JTAG_CLK RP12 G
4
C744
@ R879
5 JTAG_TDO 10K_8P4R_5% S
3
11 5 6 MSCLK 2
12 G1 6 7 MSDATA 2
1
G2 7 8 HOST_DEB_TX 1 2 HOST_DEBUG_TX
8 9 @ R853 0_0402_5%
9 EC5048_TX <37,45>
10
Rest=1.24k , Tp=92 degree 10
HB_A531015-SCHR21 BOARD_ID rise time is measured from 5%~68%. CHIPSET_ID for BID function
CONN@
+3.3V_ALW
Place under CPU DP4/DN4 for Skin on Q3, place Q3 close to Vcore VR choke. JFAN1
Place C8 close to the Q1 as possible REM_DIODE4_N +5V_RUN 1
1
100P_0402_50V8J
8.2K_0402_5%
REM_DIODE1_P +3.3V_RUN R30 1 2 10K_0402_5% FAN1_TACH_FB 2

2
1
100P_0402_50V8J
R51
1 R38 1 2 10K_0402_5% FAN1_PWM 3

3
1
3
@ C8
@ C16
RB751V40_SC76-2
22U_0805_6.3V6M
E
2 C 4
4
1
B
2 2 1 5
G5
D1
C7
B 6
E 2 C G6
3
1 Q1 ACES_50273-0040N-001
PMST3904_SOT323-3 2 CONN@
2
REM_DIODE1_N REM_DIODE4_P THERMATRIP2#
A Q3 A
+VCCIO_OUT
PMST3904_SOT323-3
PMST3904_SOT323-3
0.1U_0402_25V6
1
C
DP2/DN2 for SODIMM on Q2, place Q2 close to SODIMM and C9 close to Q2 1 2 2 1
Q4
C18
R55 2.2K_0402_5% B
REM_DIODE2_P E When 5075 solution use PWM FAN
3
2
100P_0402_50V8J
1
1
@ C9
C
2
B
2 <7> H_THERMTRIP#
E
3
Q2
PMST3904_SOT323-3
REM_DIODE2_N
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
Touch Pad +3.3V_TP
+3.3V_RUN
@ R1161
1 2
0_0603_5%
Media Board
+3.3V_ALW 1 2
+3.3V_TP @ R1162 0_0603_5% +5V_ALW
JTP1
4.7K_0402_5%
4.7K_0402_5%
1
1
1
D TP_CLK 2 D
2
R903
R902
TP_DATA 3 1
4 3
5 4 @ C1002
+3.3V_TP
PS2_DAT_TS 6 5 9
Close to JMDIA1
0.1U_0402_25V6
2
PS2_CLK_TS 7 6 G1 10 2
1 2 TP_DATA 8 7 G2 JMDIA1
<46> DAT_TP_SIO 8
@ R3735 0_0603_5% 1
1 2 TP_CLK 2 1
<46> CLK_TP_SIO 2
@ R3736 0_0603_5% HB_A520820-SCHR22 3
<46> VOL_MUTE# 3
CONN@ 4
<46> VOL_DOWN# 4
5
<46> VOL_UP# 5
6
+3.3V_TP 7 6
8 G1
G2
0.1U_0402_25V6
HB_A520620-SCHR22
1 CONN@
C755
2 @
Place close to JTP1
1 2
C
+5V_ALW RSMRST# +3.3V_ALW_PCH +3.3V_ALW
@ R1623 0_0402_5%
+3.3V_ALW_PCH
C
+3.3V_ALW
Keyboard Pitch: 1.0
10K_0402_5%
10K_0402_5%
8.2K_0402_5%
1
2
33_0402_5%
@ R1622
@ R1624
@ C288
R1629
R1630
1 2 JKB1
1
0.1U_0402_25V6 <20> KB_DET# PS2_CLK_TS 2 1
2
5
PS2_DAT_TS 3
2
1
U8 +3.3V_ALW +5V_RUN 4 3
VCC
+3.3V_ALW 4
<46> PCH_RSMRST# 1 +5V_RUN 5
IN B 5
0.1U_0402_25V6
0.1U_0402_25V6
1 4 PCH_RSMRST#_Q <15,16> 6
VCC 3 RSMRST# 2 OUT Y <46> BC_INT#_ECE1117 7 6
1 1
GND
RESET# IN A <46> BC_DAT_ECE1117 7
0.01U_0402_16V7K
C756
C758
2 8
GND 8
10K_0402_5%
1 U9 9
<46> BC_CLK_ECE1117 9
2
10
3
2 2 10
C289
R1636
RT9818A-44GU3_SC70-3 NL17SZ08DFT2G_SC70-5 @ @
11
2 GND 12
GND
1
HB_A091020-SAHR22
CONN@
Place close to JKB1
B B
SNIFFER /Hall SENSOR BOARD
JSF1
1
2 1
+3.3V_ALW <24,45> LID_CL# 3 2
+3.3V_ALW 3
4
<45> WIRELESS_ON#/OFF 4
0.1U_0402_25V6
5 7
5 G1
@ C1184
1 6 8
6 G2
HB_A090620-SAHR21
2 CONN@
WIRELESS_ON/OFF#:
LOW: ON (Default)
Close to JSF1 HIGH: OFF
+5V_ALW (PITCH 0.5) Right side LED JLED1

1
1
0.1U_0402_25V6
BATT_YELLOW# 2
<24> BATT_YELLOW# 2
1 BATT_WHITE# 3
<24> BATT_WHITE# 3
C1004
SATA_LED 4
<24> SATA_LED 4
WLAN_LED 5
<24> WLAN_LED 5
6
@ 2 7 6
8 G1
A G2 A
HB_A520620-SCHR22
Close to JLED2 CONN@
PROPRIETARY NOTE:
Title
B
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW_PCH/+3.3V_RUN Source
SI4164DY
VDS RDS(on) ID(A)
D +3.3V_ALW_PCH 30 0.0032ohm at VGS=10V 30A D
@ C452
U146 10U_0603_6.3V6M
30 0.0039ohm at VGS=4.5V 26.3A
+3.3V_ALW 1 14 1 2
2 VIN1 VOUT1 13
VIN1 VOUT1
3 12 1 2
<46> PCH_ALW_ON ON1 CT1 C451 470P_0402_50V7K
+5V_ALW 4
VBIAS GND
11
+1.05V_RUN Source
5 10 1 2
<32,39,45,48,53> RUN_ON ON2 CT2 C454 2200P_0402_50V7K
6 9
7 VIN2 VOUT2 8 +3.3V_ALW2 +PWR_SRC
VIN2 VOUT2 +3.3V_RUN
1 +1.05V_M Q63
15 AO4354_SOIC-8 +1.05V_RUN
GPAD @ C453 8 1
1
TPS22966DPUR_SON14_2X3 10U_0603_6.3V6M 7 2
1
2
10U_0603_6.3V6M
R930 6 3
1
R909 330K_0402_5% 5 1
C772
100K_0402_5% R931
20K_0402_5%
4
1.05V_RUN_ENABLE
2
2
2
3
1M_0402_5%
100P_0402_50V8J
1
Q52B
R1611
1
RUN_ON_ENABLE# 5
<7,46,48> RUN_ON_ENABLE#
C773
6
2
2
Q52A
C C
2
<32,39,45,48,53> RUN_ON
1
+3.3V_M/+3.3V_SUS source
+3.3V_M
@ C439
U36 10U_0603_6.3V6M
1 14 1 2
Discharge Circuit +1.35V_MEM
+3.3V_ALW
2 VIN1
VIN1
VOUT1
VOUT1
13
3 12 1 2
B <46,52> A_ON ON1 CT1 B
+1.05V_RUN +0.675V_DDR_VTT C437 470P_0402_50V7K
+5V_ALW 4 11
VBIAS GND
1
1
@ R926 1 2 5 10 1 2
<45,51> SUS_ON ON2 CT2
@ R925 220_0402_5% @ R927 @ R1607 0_0402_5% C435 470P_0402_50V7K
39_0402_5% 22_0603_5% 6 9
7 VIN2 VOUT2 8 +3.3V_SUS
2
VIN2 VOUT2
+1.35V_MEM_CHG
2
15
+1.05V_RUN_CHG
GPAD 1
1 2
<45> USH_PWR_ON
+DDR_CHG
@ R1620 0_0402_5% TPS22966DPUR_SON14_2X3 @ C443

10U_0603_6.3V6M
2
<7,46,48> RUN_ON_ENABLE#
L2N7002WT1G_SC-70-3
L2N7002WT1G_SC-70-3
1
D D
L2N7002WT1G_SC-70-3
@ Q72
Q70 @
RUN_ON_ENABLE# 2 2
1
D
@ Q71
G G
S 2 S
3
G
S
3
A A
4019MV
5 4 3 2 1
5 4 3 2 1
+COINCELL
COIN RTC Battery
1
PR1
1K_0402_5%~D
+3.3V_RTC_LDO
2
JRTC1
Z4012
+COINCELL 1
2 1
3 2
D
4 G1 D
G2
2
+RTC_CELL ACES_50273-0020N-001
PD3
1
ESD Diodes
BAS40-05W_SC70-3~D 1
PC3
1
1U_0603_10V4Z~D
EMC@ PD2 EMC@ PD4
2
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
3
EMC@ PL2
FBMJ4516HS720NT_2P~D +3.3V_ALW
1 2
Primary Battery Connector

EMC@ PL3
1
FBMJ4516HS720NT_2P~D
100K_0402_5%~D
PBATT1
+PBATT_C 1 2 +PBATT
PR6
11
GND 10
GND 9
2
9 8 PRP2
8 7 Z4304 8 1
2200P_0402_50V7K~D
7 PBAT_SMBCLK <46>
6 Z4305 7 2
6 PBAT_SMBDAT <46>
5 Z4306 6 3
5 PBAT_PRES# <45,56>
1
EMC@ PC5
4 5 4
4 3
3 2 100_0804_8P4R_5%
2
2 1 PQ7
C C
1 DMG2301U-7 1P SOT23-3
OCTEK_BTJ-09WKFB 1 2 1 3
3
DOCK_SMB_ALERT# <44,45,56>
PD7
SDMK0340L-7-F_SOD323-2~D
2
2
GND @ PR26
0_0402_5%~D
1 2
<44,45,56> SLICE_BAT_PRES#
1500P_0402_7K~D
1
PC17
2
+3.3V_ALW
@ PR10 PU1
2.2K_0402_5%~D
2
1 2 <44> DOCK_PSID 1 6 GPIO_PSID_SELECT <45>
0_0402_5%~D NO IN
PR11
2 5 +5V_ALW
EMC@ PL4 PR12 GND V+
1
BLM15AG102SN1D_2P 33_0402_5%~D
NB_PSID 2 1 1 3 1 2 NB_PSID_TS5A63157 3 4
D
S
NC COM PS_ID <46>
100K_0402_1%~D
PQ1 74LVC1G3157GW_SC-88-6
2
FDV301N_G_NL_SOT23-3~D
G
2
PR13
+5V_ALW
10K_0402_1%~D
1
1
B C B
PR14
2 PQ2
B MMST3904-7-F_SOT323~D
E
15K_0402_1%~D
3
2
2
PR15
PR16
1 2
PSID_DISABLE# <45>
1
@ 10K_0402_5%~D
DC_IN+ Source
+DC_IN +DC_IN_SS
EMC@ PL5 PQ4
FBMA-L11-453215-800LMA90T_1812~D FDS6679AZ_G_SO8~D
1 2 +DC_IN 1 8
2 S D 7
3 S D 6
3
IMD2AT-108_SC74-6~D
4 S D 5
G D
0.022U_0805_50V7K~D
2
1
PQ6B
1M_0402_5%~D
2
PC8
100K_0402_5%~D
10U_0805_25V6K
1
PR18
1
1
100P_0603_50V8
PR20
PC13
2
1
@EMC@ PC14
PR23
1000P_0603_50V7K~D
4.7K_0805_5%~D
IMD2AT-108_SC74-6~D
2
1
JESS_UCNR2451M005-0
EMC@ PC12
1 2
SOFT_START_GC <56>
2
5
2
5 4 -DCIN_JACK
@ PR22
10K_0402_5%~D
2
4 3
1
1M_0402_5%~D
3 2 +DCIN_JACK
PQ6A
5
AC_DIS <45,56>
2
2 1
PR25
A A
1
@ PJPDC1
2
6
PJP1
1 2
PAD-OPEN 1x3m
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D SCHEMATIC,MB LA-9931P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B
4019MV
5 4 3 2 1
A B C D E
VFB2=2V,PR100=(Vout-0.5*Vripple-2)/2*PR102 +3.3V_ALW2
+3.3V_RTC_LDO VFB1=2V,PR101=(Vout-0.5*Vripple-2)/2*PR104
PR100
6.49K_0402_1%~D
1 2 PR101
15K_0402_1%
1 2 1 1
0_0402_5%~D
1U_0603_10V5K
PR102 PR104
2
PR103
10K_0402_1% 10K_0402_1%
1
PC114
1 2 2 1
2
1
110K_0402_1%~D
2
88.7K_0402_1%~D
2
+3V5V_PWR_SRC
PR106
PR105
+3V5V_PWR_SRC +3.3V_ALW
1
<46> ALW_PWRGD_3V_5V
1
110K_0402_1%~D
EMC@ PL103
2
1UH +-20% MMD-05CZ-1R0M-M7L 7A
PR119
2 1 PU100
10U_0805_25V6K
0.1U_0402_25V6
1
1
PC109
+PWR_SRC
CS2
VFB2
VREG3
VFB1
CS1
2200P_0402_50V7K
10U_0805_25V6K
@EMC@ PC103
0.1U_0402_25V6
21
SIS412DN-T1-GE3_POWERPAK8-5~D
1
PAD
1
1
PC110
3V_5V_EN 6
2
EN2
5
@EMC@ PC105
@EMC@ PC106
@ PR118 14
VO1
5
0_0402_5%~D @ PR111
2
1 2 7 200_0402_1%
PGOOD
PQ101
19 2 1
VCLK
PQ102
4 UG_3V 10 TPS51225CRUKR_QFN20_3X3
PC112 PR108 DRVH2 16 UG_5V 4
0.1U_0603_25V7K 2.2_0603_5% DRVH1 PR107 PC111
1 2 1 2 BST_3V 9 2.2_0603_5% 0.1U_0603_25V7K
VBST2 17 BST_5V 1 2 1 2
1
2
3
2 VBST1 2
3
2
1
SW2 8
SW2 18 SW1
VREG5
DRVL2
DRVL1
PL101 SW1 PL102
+3VALWP +5VALWP
EN1
VIN
2.2UH_VMPI0703AR-2R2M-Z01_8.3A_20% 3.3UH_ETQP3W3R3WFN-H-3R3M_6.6A_20%
1 2 1 2
11
12
13
3V_5V_EN 20
15
680P_0603_50V7K
680P_0603_50V7K
SIS472DN-T1-GE3_POWERPAK8-5
5
1
220U_6.3V_M_R18M
@EMC@ PC119
LG_3V LG_5V
1
@EMC@ PC116
220U_6.3V_M_R18M
2
PC101
+
1
SNUB_3V 2
PQ103
PQ104
1SNUB_5V
PC102
4 4 +
2
1U_0603_10V5K
0.1U_0603_25V7K
4.7_1206_5%
1
2
3
3
2
1
1
1
4.7_1206_5%
PC117
PC118
@EMC@ PR112
@EMC@ PR109
2
2
+3V5V_PWR_SRC +5V_ALW2
3 3
3V_5V_EN
@ PR110
0_0402_5%~D
1 2
<46> ALWON
5VALWP
3VALWP Ripple voltage -
Ripple voltage - Static load 3% / Dynamic load 5%
Static load 3% / Dynamic load 5% Frequency 300kHz
1U_0603_10V6K
Frequency 350kHz PJP100 TDC 6.075A

1
PJP101
PC120
1 2 1 2
TDC 5.099A +3VALWP +3.3V_ALW +5VALWP +5V_ALW Peak Current 8.679A
2
@ OCP current 10.415A

Peak Current 7.285A PAD-OPEN 1x2m~D PAD-OPEN 4x4m
PJP102 PJP103
OCP current 8.742A 1 2 1 2
TYP MAX
TYP MAX H/S Rds(on) 24mohm , 30mohm
PAD-OPEN 4x4m PAD-OPEN 4x4m L/S Rds(on) 10.3mohm , 12.4mohm
H/S Rds(on) 24mohm , 30mohm
L/S Rds(on) 10.3mohm , 12.4mohm Choke DCR Max:28mohm
Choke DCR Max:17mohm Choke Ityp:6.6A / Isat:8.2A
4
Choke Ityp:8.3A / Isat:10.8A Bulk cap ESR 18mohm 4
Bulk cap ESR 18mohm

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SCHEMATIC,MB LA-9931P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019MV
A B C D E
5 4 3 2 1
0.675Volt +/- 5%
PJP201
VLDOIN_1.35V 2 1 +1.35V_MEN_P TDC 0.525A
Peak Current 0.75A
+PWR_SRC PJP200
PR200
PAD-OPEN1x1m OCP Current 0.9A
2 1 1.35V_B+ 1 2 BOOT_1.35V
2 1
2.2_0603_5%
JUMP_43X118
2200P_0402_50V7K
D DH_1.35V D
+0.675V_P
10U_0805_25V6K
10U_0805_25V6K
SIR472DP-T1-GE3_POWERPAK8-5~D
10U_0805_6.3V6M
10U_0805_6.3V6M
1
1
PC206 SW_1.35V
PJP202
5
PC202
PC203
@EMC@ PC205
0.22U_0603_10V7K
1
2 1
1
PC207
PC208
DL_1.35V
16
17
18
19
20
@ PU200 +0.675V_DDR_VTT
PQ201
PAD-OPEN1x1m
PHASE
UGATE
BOOT
VTT
VLDOIN
2
4 21
PAD
15 1
LGATE VTTGND
1
2
3
PR201 14 2
+1.35V_MEN_P PL201 6.98K_0402_1% PGND VTTSNS +V_DDR_REF
1UH_PCMC104T-1R0MN-P3_21.3A_20%~D 1 2 CS_1.35V
1 2 13 3
PC213 CS RT8207MZQW_WQFN20_3X3 GND
5
680P_0603_50V7K
330U_SX_2VY_R9M
1U_0603_10V6K
SIRA10DP-T1-GE3_POWERPAK-SO8-5~D
390U_2.5V_M
PR203 2 1VDDP_1.35V 12 4 +V_DDR_REF

VDDP VTTREF
1
1 1 5.1_0603_5%
+ + @EMC@ PC212
PC216
PC201
1 2 VDD_1.35V 11 5 PC209
SNUB_1.35V 2 VDD VDDQ +1.35V_MEN_P
PQ203
PGOOD
4 0.033U_0402_16V7~D
TON
2 2 +5V_ALW PC210
FB
S5
S3
2
@ 1U_0603_10V6K
2
@ PR211
3
2
1
10
6
C 0_0402_5%~D C
+3.3V_ALW
1
4.7_1206_5%
1
PC211 220P_0402_50V8J~D
@EMC@ PR202
1 2
1
PR209 +5V_ALW
2
100K_0402_1%~D PR204
8.06K_0402_1%~D
1.35V_FB 1 2
2
<7,46> 1.35V_SUS_PWRGD
PR205
1M_0402_1%
2
@ PR206 1.35V_B+ 1 2
1
200K_0402_5% PR207
1 2 S5_1.35V 10K_0402_1% PC214
<16,35,45> SIO_SLP_S4#
@.1U_0402_16V7K
2
1
@ PC215 @ PR208
1
@ PR210 0_0402_5%~D
0_0402_5%~D 1U_0402_6.3VX5R 1 2 S3_1.35V
<45> 0.75V_DDR_VTT_ON
1 2 2
<45,48> SUS_ON
1.35VP
Ripple voltage -
B
Static load 3% / Dynamic load 5% +1.35V_MEN_P
B
Frequency kHz
TDC 5.206A PJP203
VFB=0.75V, 1.35= 0.75*(1+PR204/PR207)
Peak Current 7.438A 2
2 1
1 FB sense trace
OCP current 8.926A JUMP_1x3m
TYP MAX PJP204

+1.35V_MEN_P 2 1 +1.35V_MEM
H/S Rds(on) :12.2mohm , 15mohm 2 1
JUMP_1x3m
L/S Rds(on) :4.1mohm , 5mohm
Choke DCR 2.35mohm
Choke Ityp:21.3 / Isat:22.4A
Bulk cap ESR 10mohm
A A
Title
5 4 3 2 1
5 4 3 2 1
PJP300
+1.05VSP_B+ 2 1
+PWR_SRC
PAD-OPEN 1x2m~D
+3.3V_ALW
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
0.1U_0402_25V6
1
1
@EMC@ PC302
@EMC@ PC303
PC304
PC305
2
D D
2
5
PR300
100K_0402_5% @
PQ301
1
<46> 1.05V_A_PWRGD
4
PC306
PU300 .1U_0603_25V7K
PR301
1 10 BST_+1.05VSP 1 2 2 1
3
2
1
PGOOD VBST
PR302 2.2_0603_5%
1 2 TRIP_+1.05VSP 2 9 UG_+1.05VSP PL301
TRIP DRVH 1UH_ETQP3W1R0WFN-H-1R0M_11A_20%
93.1K_0402_1%
@ PR303 EN_+1.05VSP 3 8 SW_+1.05VSP 1 2
150K_0402_5% EN SW @ PR309 +1.05V_MP
1 2 FB_+1.05VSP 4 7 +1.05VSP_5V 1 2
<16,35,45> SIO_SLP_A# VFB V5IN
+5V_ALW
10U_0805_6.3V6M
220U_6.3V_M_R18M
1000P_0603_50V7K
@ PR308 RF_+1.05VSP 5 6 LG_+1.05VSP 0_0402_5%~D
TST DRVL 1
@EMC@ PC309
0_0402_5%~D 1 2
1
+
PC301
PC310
1 2 11
<46,48> A_ON TP
1
PC308
1SNUB_1.05V 2
1
@ PC307 TPS51212DSCR_SON10_3X3 1U_0603_10V6K
2
2
PQ303
0.22U_0402_16V7K
2
PR305 4
470K_0402_1%
2
4.7_1206_5%
3
2
1
@EMC@ PR304
C C
2
PR306
4.99K_0402_1%
2 1
Vout=0.7*(1+PR306/PR307)
2
PR307
10K_0402_1%
1
PJP301
+1.05V_MP 2
2 1
1 +1.05V_M
B JUMP_43X118 B
+1.05VSP
Ripple voltage -
Static load 3% / Dynamic load 5%
Frequency 290kHz
TDC 4.659A
Peak Current 6.523A
OCP current 7.828A
TYP MAX
H/S Rds(on) 24mohm , 30mohm
L/S Rds(on) 10.3mohm ,12.4mohm
Choke DCR 11mohm
Choke Ityp:11A / Isat:14.5A
Bulk cap ESR 18mohm
A A
Title
5 4 3 2 1
A B C D
+1.5VSP
Ripple voltage -
Static load 3% / Dynamic load 5%
1
Frequency 1MHz 1
TDC 1.329A
Peak Current 1.899A
OCP current 2.279A
Choke DCR 27mohm
Choke Ityp:3.2A / Isat:4A
PU400 PL401
4
PJP400 1UH +-30% NRS4018T1R0NDGJ 3.2A
+3.3V_ALW 2 1 1.5VSP_VIN 10 2 1.5VSP_LX 1 2
PG
PVIN LX
+1.5V_RUNP
22P_0402_50V8J
PAD-OPEN 1x2m~D 9 3
PVIN LX
1
680P_0402_50V7K
22U_0603_6.3V6M
0.1U_0402_25V6
1
1
2 2
PC400
@EMC@ PC401
@EMC@ PC407
PC402
8
SVIN PR402
SNUB_1.5VSP 2
6 1.5VSP_FB 30.1K_0402_1%
2
FB
22U_0603_6.3V6M
22U_0603_6.3V6M
47P_0402_50V8J
5
2
EN
1
PC403
PC404
@EMC@ PC405
NC
NC
TP
11
2
1 2 EN_1.5VSP
<16,35,39,40,45> SIO_SLP_S3#
1
@ PR403
.1U_0402_16V7K
1
PC406
0_0402_5% SYN470DBC_DFN10_3X3 PR405
4.7_0805_5%
20K_0402_1%
@EMC@ PR401
2
1 2 @
<32,39,45,48> RUN_ON
2
@ PR406
0_0402_5%~D
<Vo=1.5V> VFB=0.6V
3
Vo=VFB*(1+PR402/PR405)=0.6*(1+30.1K/20K)=1.5V 3
PJP401
2 1
+1.5V_RUNP +1.5V_RUN
PAD-OPEN 1x2m~D
4
DELL CONFIDENTIAL/PROPRIETARY 4

Title
A B C D
5 4 3 2 1
+VCCIO_OUT PR500 130_0402_1%~D

2 1
@ PR503 75_0402_5%
2 1
VCC_core (Base on PDDG rev 1.1)
TYP MAX
D PC548
1U_0402_6.3V6K PR504 54.9_0402_1%
TDC 26A D
H/S Rds(on) :12.2mohm , 15mohm
1 2 2 1 Peak Current 55A
PR507=49.9k,Vboot=1.7V L/S Rds(on) :2.75mohm , 3.5mohm
DC Load line -1.5mV/A
<11> VIDSOUT PR507 Icc_Dyn_VID1 35A
21K_0402_1%~D
<11> VIDALERT_N 1 2 OCP current 64A
PR509
Choke DCR 0.97m ohm
<11> VIDSCLK
3.24K_0402_1%~D
1 2
@ PR511 PR512
0_0402_5%~D 16.9K_0402_1%
<45> IMVP_VR_ON 1 2 1 2
+5V_ALW
BOOT2
UGATE2
2
PR519 1.91K_0402_1% PHASE2
2 1 @ PR520
+3.3V_RUN 0_0402_5%~D +PWR_SRC
<45> IMVP_PWRGD PC509 PJP500
1U_0603_10V6K PAD-OPEN 4x4m
32
31
30
29
28
27
26
25
VCORE_VDDP 1
1 2 1 2
PC500
ALERT#
SDA
SLOPE/PROG1
PROG3
PROG2
BOOT2
UGATE2
PHASE2
1 2
1000P_0402_50V7K @EMC@ PL504
1 24 LGATE2 FBMA-L11-453215-800LMA90T_1812
PR521 VR_ON 2 SCLK LGATE2 23 CPU_B+ 1 2
VR_ON VDDP
470P_0402_50V7K~D
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
97.6K_0402_1% 3 22
0.1U_0402_25V6K~D
PGOOD PWM3
5
2 1 IMON 4 21 LGATE1
C
@ PR524 0_0402_5%~D 5 IMON LGATE1 20 PHASE1 PQ505 C
VR_HOT# PHASE1
1
PC512
PC513
PC514
EMC@ PC516
@EMC@ PC515
1 2 VR_HOT# NTC 6 19 UGATE1
PR525 COMP 7 NTC UGATE1 18 BOOT1
3.83K_0402_1% FB 8 COMP BOOT1 17
<7,46,55,56> H_PROCHOT#
2
2 1 1 2 FB VIN @ PR526 UGATE2 4
FB2/VSEN
0_0402_5%~D
ISUMN
ISUMP
ISEN3
ISEN2
ISEN1
Pull high put on HW site PH500 33 1 2CPU_B+
VDD
RTN
470K_0402_5%_ TSM0B474J4702RE PAD PL502
0.22UH_PCME064T-R22MS0R985_25A_20%~D
0.22U_0603_25V7K
3
2
1
2 1 9 PU500
10
11
12
13
14
15
16
1
4 1
47P_0402_50V8J~D
PR528 PR529 ISL95812HRZ-T_QFN32_4x4 PHASE2

+VCC_CORE
PC510
680P_0603_50V7K
27.4K_0402_1% 1 2
1
PC511
PR536 3 2
@EMC@ PC524
6.04K_0402_1%~D PR534 PQ508 3.65K_0603_1% P2_SW
SIRA06DP-T1-GE3_POWERPAK8-5
V2N
BOOT2 2 1 1 2 1 2
2
2.2_0603_5% PR538
2
PR530 PC522 100K_0603_1%
1_0402_1%~D +5V_ALW 0.22U_0603_16V7K 1 2
SNUB_V2
FB2/VSEN 1 2 LGATE2 4
1
ISUMP
ISEN2
4700P_0402_50V7K~D
PR546 PR544
1
PC520 100K_0402_1%~D 10_0402_1%
PR533 390PF_0402_50V7K~D PC518 V1N 1 2
3
2
1
1
4.7_1206_5%
FB 2 1 2 1 0.1U_0603_25V7K~D
2
1
PC521
@EMC@ PR541
10_0402_1%~D
ISUMN
453_0402_1%
2
PR537
2
PR535
COMP 2 1
2
4700P_0402_50V7K~D 909_0402_1%
1.65K_0402_1%
2
PR539
2
2
1.5K_0402_1%
PR543
2
PR545
2K_0402_1%
B PC525 B
2 1
56P_0402_50V8J
1
2 1
CPU_B+
1
PC526
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6K~D
1 1 1
100U_25V_M
100U_25V_M
100U_25V_M
PC527
1
+ + +
PC530
PC531
PC532
330P_0402_50V7K~D PQ509
1
1
4.99M_0402_1%
PC533
PC534
PC535
@EMC@ PC536
2 2 2
PR558
PC528
2
0.1U_0402_10V6K~D UGATE1 4
1 2
2
PL503
PC529 0.22UH_PCME064T-R22MS0R985_25A_20%~D~D
3
2
1
.1U_0603_16V7K~D
ISEN2 @ PR548 1 2 PHASE1 4 1
+VCC_CORE
680P_0603_50V7K
0_0402_5%~D
1 2 3 2
5
@EMC@ PC543
ISEN1 @ PC538 PR550 PQ512 P1_SW V1N
0.033U_0603_16V6K~D BOOT1 2 1 1 2
PC539 1 2 2.2_0603_5% PR552 PR553
SNUB_V1 2
0.022U_0402_25V7K PC542 3.65K_0603_1% 100K_0603_1%
<11> VCCSENSE
2 1 0.22U_0603_16V7K 1 2 1 2
PR549 LGATE1 4
PC540 11K_0402_1% ISEN1
1
ISUMP
0.022U_0402_25V7K @ PC541 1 2 PR555
2 1 ISUMN 1 2 100K_0402_1%~D PR556
1
PR551
4.7_1206_5%
V2N 1 2
0.082U_0402_16V7K
10_0402_1%
3
2
1
PC545
@EMC@ PR554
330P_0402_50V7K PH501
1
10KB_0402_5%_ERTJ0ER103J 2.61K_0402_1%
ISUMN 2
1 2 1 2
2
2
PC546 @
1 2
.1U_0402_16V7K
ISUMP
1
A A
0.01U_0402_50V7K
PC547
ISUMN
2
<11> VSSSENSE
Local sense put on HW site
Title
5 4 3 2 1
5 4 3 2 1
@ PD700
2 1 EMC@ PL701
1UH +-20% MMD-05CZ-1R0M-M7L 7A
ES2AA-13-F 2 1
PQ700 PR701 +PWR_SRC_AC CHAGER_SRC TYP MAX
+SDC_IN
SI4835DDY-T1-GE3_SO8~D
8 1
0.01_1206_1%~D H/S Rds(on) 12.2mohm , 15mohm
22U_0805_25V6K
22U_0805_25V6K
@ PJP700
+DC_IN_SS
7 2 4 1 1 2 L/S Rds(on) 2.7mohm , 3.5mohm
6 3
0.1U_0603_25V7K~D
Choke DCR 6.8mohm
1
@ PC724
@ PC728
5 3 2 PAD-OPEN 4x4m
@
Choke Itye:14.2A / Isat:15A
1
@ PR700
2
PC700
0_0402_5%~D
1 2 @ PR702
DC_BLOCK_GC <56>
1
0_0402_5%~D D
@ PR710 1 2 2 PQ701
<56> CSS_GC
0_0402_5%~D G NTR4502PT1G_SOT23-3~D
1
D <46> VCP D
1 2 D S
3
2 PQ703A
G SI3993CDV-T1-GE3_TSOP6~D
PD701
PQ702 S
S
2 NTR4502PT1G_SOT23-3~D 5 6
D
+DOCK_PWR_BAR DOCK_DCIN_IS+ <44>
PU703
1 6 1
CSSN_1
REF Out
G
CSSP_1
1
CSSN_1 3 PQ703B
+DC_IN_SS @ PR703 SI3993CDV-T1-GE3_TSOP6~D
PR744 10K_0402_5%~D
BAT54CW_SOT323~D
S
0_0402_5%~D
2 1 2 4
100K_0402_1%~D
44.2_0402_1%~D
D
DOCK_DCIN_IS- <44>
PR704
@ PR705
0_0402_5%~D
2 5 2 1
GND IN-
PR706
100K_0402_1%~D
1
1
3 4
G
+SDC_IN
3
V+ IN+ @
PR707
2 1 CSSP_1 PC703 PC704
1
INA199A1DCKR_SC70-6~D 1U_0603_25V6K 0.1U_0402_25V6K PC705 @ PR709

0.1U_0603_25V7K~D
2
1
PC720
59_0402_1% PR742 1 2 1 2 1 2 0_0402_5%~D
2
PR736 10_1206_5%~D 1 2
DK_CSS_GC <56>
2
0.1U_0402_25V6K
GNDA_CHG
+PWR_SRC
+SDC_IN GNDA_CHG PC706
1
1 2
316K_0402_1%~D
PC707 PU700
sense adapter Discrete current monitor circuit 10U_0805_25V6K Near PL700
ACP
ACN
2
2
PR713
2 1 +DCIN 20 16 BQ24715_REGN 1U_0603_10V6K~D
VCC REGN PD702
BAT54HT1G_SOD323-2~D
5
PR714
49.9K_0402_1%~D 3 17 BOOT PR715
22U_0805_25V6K
22U_0805_25V6K
22U_0805_25V6K
22U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
22U_0805_25V6K
22U_0805_25V6K
22U_0805_25V6K
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
SIR472DP-T1-GE3_POWERPAK8-5
1
1
2 1 CMSRC BTST 2.2_0603_1%
1 2
1
PQ704
@EMC@ PC710
@EMC@ PC711
PC712
PC713
PC714
PC734
PC731
PC732
PC737
PC738
PC739
PC708
2 1 4 18 CHG_UGATE 4
ACDRV HIDRV
PC709
0.047U_0603_25V7K~D
2
1
BQ24715_REGN
0.1U_0402_10V6K @ @ @
C GNDA_CHG CHARGER_SMBCLK C
CHARGER_SMBDAT 6 19
3
2
1
ACDET PHASE CHG_PHASE
pull up 10K in HW side (R827 R828)
<46> CHARGER_SMBDAT 8 15 CHG_LGATE

SDA LODRV +PWR_SRC
1
PR741
100K_0402_1% <46> CHARGER_SMBCLK 9 14 PL700 PR716
SCL GND 0.01_1206_1%~D +VCHGR
@ PR717 2.2UH_PCMB104E-2R2MS_14.2A_20%~D
2
0_0402_5%~D 2 1 4 1
1 2 5 13
<46,55,56> ACAV_IN ACOK SRP 3 2
1000P_0603_50V7K~D
5
1
@EMC@ PC715
10U_0805_25V6K
10U_0805_25V6K
0.1U_0603_25V7K~D
1
7 12
PR743 <46> V_SYS IOUT SRN
2SNUB_Charger 2
1
121K_0402_1% sense battery @ PR720
PQ706
@EMC@ PC717
PC718
PC719
0_0402_5%~D
2
1 2 10 11 4
+3.3V_ALW
2
2
PC716 CELL /BATDRV
TP
680P_0603_50V7K
100P_0402_50V8J~D
1
PR746 BQ24717
21
10K_0402_1%~D
4.7_1206_5%~D
3
2
1
2
PC735
BQ24715_REGN 1 2 @ PC721 PC722 PC723
@EMC@ PR721
GNDA_CHG 0.1U_0402_25V6K 0.1U_0402_25V6K 0.1U_0402_25V6K
GNDA_CHG 1 2 1 2 1 2
1
@
<56> CHARGER_CELL_PIN
1
@ PR747 PJP701 @ PR718 GNDA_CHG GNDA_CHG
10K_0402_1%~D 1 2 0_0402_5%~D
+3.3V_ALW2 1 2 1 2
PAD-OPEN1x1m @ PR719
GNDA_CHG 0_0402_5%~D
1 2
B B
@ PR745
0_0402_5%~D +5V_ALW
H_PROCHOT# <7,46,54,56>
2 1 OP_5V PR722
0.01U_0402_25V7K~D
+5V_ALW
DYN_TUR_CURRENT_SET# 4.02K_0402_1%~D
1 2 BATDRV# <56>
1
PC725
221K_0402_1%~D
2
PR723
65W High (4.08A)
2
+3.3V_ALW2 @ @ PR724
PR725 0_0402_5%~D
1.8M_0402_1% Judge AC form NB side not DOCK side
1
1 2
90W Low (5.36A)
1
1
PR726
150K_0402_1% PR728
8
DMN66D0LDW-7 2N SOT363-6
DMN66D0LDW-7 2N SOT363-6
20K_0402_1%~D PU701A
VCP 1 2 3
P
2
+
6
3
PQ707A
PQ707B
1 +3.3V_ALW2
2 O
-
G
1200P_0402_50V7K
LM393DR_SO8~D 2 5
220P_0402_50V8J~D
4
255K_0402_1%
97.6K_0402_1%
0.775V (65W)
1
+DC_IN
PC727
PR734
100P_0402_50V8J~D
1.0136V (90W)
1
4
1
+3.3V_ALW
PC736
10K_0402_1%~D
1M_0402_1%~D
1
PR730
PR731
PC726
1 2 BQ24715_REGN
48.7K_0402_1%
232K_0402_1%~D
2
1
2
PR732
PR733
PR735
2
OP_5V
2
PR748
2
1
D +3.3V_ALW 100K_0402_5%~D
8
2 PC733 1.73V PU701B @ PR737
<46> DYN_TUR_CURRNT_SET#
G @ PR727 0.1U_0402_25V4Z~D 5 0_0402_5%~D
P
2
0_0402_5%~D + 7 1 2
S
3
2 1 2 1 6 O ACAV_IN_NB <46,56>
10K_0402_1%~D
PQ709
22.6K_0402_1%~D
42.2K_0402_1%~D
100P_0402_50V8J~D
<45> MODULE_BATT_PRES# -
G
DMN65D8LW-7_SOT323-3~D
100P_0402_50V8J~D
1
1
1.47V LM393DR_SO8~D
4
5
1
PC729
PR738
PR739
PC730
PR740
A PU704 A
1
1 D
P
4 B 2
ACAV_IN <46,55,56>
2
2
O 2 G
PROCHOT_GATE <45>
2
2
A
G
S
3
To preset system to throtlle PQ710

Adapter Protection Circuit for Turbo Mode
3
74AHC1G08GW_SSOP5~D switching from AC to DC DMN65D8LW-7_SOT323-3~D

Title
SCHEMATIC,MB LA-9931P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4019MV
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 17, 2013 Sheet 55 of 62
5 4 3 2 1
5 4 3 2 1
PD807 PQ801
PD806 SDMK0340L-7-F_SOD323-2~D NTR4502PT1G_SOT23-3~D +3.3V_ALW
PDS5100H-13_POWERDI5-3~D PC801 PR801
1
3 +PBATT_IN_SS 2 1 3 1 0.1U_0402_10V7K~D 100K_0402_5%~D
1 +NBDOCK_DC_IN_SS 1 2 2 1
2
Purpose: Trigger PROCHOT# when +3.3V_ALW
240K_0402_5%
2
active battery is removed from
2
2
5
PR802
PQ809 PU801
system.
1
SLICE_BAT_PRES# 1 D
SI4835DDY-T1-GE3_SO8~D
P
1 8 B 4 2 DMN65D8LW-7_SOT323-3~D
2 7 Allows EC to re-establish SLICE_BAT_ON 2 O G PQ802
+BATT_SUM
1
A
G
3 6 +3.3V_ALW
system performance for battery S H_PROCHOT# <7,46,54,55>
3
5
3
1
next in line.
100K_0402_5%~D
2
+3.3V_ALW2
47K_0402_5%
4
1
PR813
PR804
74AHC1G08GW_SOT353~D PR807
3
100K_0402_5%~D
6 2
PR808
1
PD800 100K_0402_5%~D
2
PDS5100H-13_POWERDI5-3~D 5 DMN66D0LDW-7 2N_SOT363-6~D
D 3 PQ805B D
2
1 +3.3V_ALW2 DMN66D0LDW-7 2N_SOT363-6~D 2
10K_0402_5%~D
4
1
+VCHGR 2 PQ807A
PR815
3
PQ800 PQ811 PR817
2
SI4835DDY-T1-GE3_SO8~D FDS6679AZ_G_SO8~D 330K_0402_5%~D
1 8 PR816 1 8
+PBATT
2 2
2 S D 7
6
2 7 100K_0402_5%~D 1 2 DMN66D0LDW-7 2N_SOT363-6~D 5 +3.3V_ALW
3 6 3 S D 6 PQ807B SLICE_BAT_PRES# <44,45,49,56>
4 S D 5
PD811
4
G D
1
2 DMN66D0LDW-7 2N_SOT363-6~D
PR810 PQ805A
4
100K_0402_5%~D
6 1
1
<55> BATDRV# PR821 @ PR892 +PWR_SRC_AC
DMN66D0LDW-7 2N_SOT363-6~D
3
820_0603_1%~D 0_0402_5%~D
2
PQ812B @ PR890 1 2 1 2 3301_DSCHRG_FET_GC
+3.3V_ALW
PQ806B
0_0402_5%~D
PQ806A
2 5 1 2 PC805
SLICE_BAT_ON <45,56>
6
PQ812A
0.1U_0402_10V7K~D
1
@ PR888 1 2
PD818
1
PC811 0_0402_5%~D
0.01U_0603_25V7K~D 1 2 5 2 1 2
<45,56> SLICE_BAT_ON CHARGER_CELL_PIN <55>
5
PU804
@ PR811 PBAT_PRES# 1
P
4
1
PC807 0_0402_5%~D B 4 SDMK0340L-7-F_SOD323-2~D
1 2 2 1 2 O
A
G
PBAT_PRES# <45,49>
0.47U_0805_25V7K~D
STSTART_DCBLOCK_GC
3
@ PR812
PDS5100H-13_POWERDI5-3~D
0_0402_5%~D 74AHC1G08GW_SOT353~D
1
2
3
4
1 2
<45> DIS_BAT_PROCHOT#
PQ810
S
S
S
G
FDS6679AZ_G_SO8~D
PD808
D
D
D
D
+3.3V_ALW2
8
7
6
5
2
3
PR814
330K_0402_5%~D PC808 Purpose: Turn on the PQ817
2 1 0.1U_0402_10V7K~D
2 1 for primary or module bay
PU805
+3.3V_ALW2 74AHC1G08GW_SOT353~D battery to provide power to
5
PC810
100K_0402_5%~D
dock side without AC exist.
2
C C
0.1U_0402_10V7K~D 1
P
+DOCK_PWR_BAR B
1
SLICE_BAT_PRES# <44,45,49,56>
PR818
@ PC809 2 1 4
PU806 O 2 1 2
1500P_0402_7K~D A +3.3V_ALW2
G
74AHC1G08GW_SOT353~D PR819
5
PD810 100K_0402_5%~D
1
1 D
BAT54CW_SOT323~D
P
3 4 B 2
FDS6679AZ_G_SO8~D
O DOCK_DET# <44,45,56>
2 ACAV_IN# G
A
5
6
7
8
G
1 PQ817
10K_0402_5%~D
S
3
1
2
3
4
1
D
D
D
D
3
PQ826
PR822
PQ815 2
S
S
S
G
FDS6679AZ_G_SO8~D
G
S
S
S
2
D
D
D
D
AO3418_SOT323-3
4
3
2
1
Purpose: Turn on the PQ815
8
7
6
5
1
D
PQ816
@ PR894
0_0402_5%~D 2 +3.3V_ALW2 +3.3V_ALW2 for Slice battery discharge
1 2 G +3.3V_ALW2
+3.3V_ALW2
PQ828 S Vth: 0.5~1.5 PC812 without AC exist
2
@ PR895 DMG2301U-7 1P SOT23-3 0.1U_0402_10V7K~D
0_0402_5%~D 2 1 PR823 PR824 @
3
1 2 3 1 PU807 100K_0402_5%~D 100K_0402_5%~D

+3.3V_ALW
74AHC1G08GW_SOT353~D
1
1
1
1
2
P
2
PR830 PD813 4 B
O
3
100K_0402_5%~D BAT54CW_SOT323~D 2
NTR4502PT1G_SOT23-3~D
A
PQ819B
PD820
2
1
D 5 ACAV_IN#
1 2
3
1 2 PQ813A 2
<44,45,49,56> SLICE_BAT_PRES# 1
PQ814
DMN66D0LDW-7 2N_SOT363-6~D PD819 G @
4
PQ818
1 6 2 1 2 SDMK0340L-7-F_SOD323-2~D S
3
1
D 1 2
PR828 2
<45,49> AC_DIS 1 2 2 DOCK_SMB_ALERT# <44,45,49>
PR826 3
6
10K_0402_5%~D G PQ813B 240K_0402_5% PR827
2
S DMN66D0LDW-7 2N_SOT363-6~D 47K_0402_5% @ PR882 @ PR881
3
PQ829 4 3 1 2 0_0402_5%~D 0_0402_5%~D

DMN65D8LW-7_SOT323-3~D 2 1 1 2 2 1 2
+3.3V_ALW2 <44,45,49,56> SLICE_BAT_PRES# SLICE_PERF_EN <46,56>
PR829 +NBDOCK_DC_IN_SS @ PQ819A
5
1
100K_0402_5%~D DMN66D0LDW-7 2N_SOT363-6~D
1
1
B @ PR831 B
0_0805_5%~D @ PR832 @ PR884 @ PR886
2
G
1 2 0_0402_5%~D 0_0402_5%~D 0_0402_5%~D PQ827
+DC_IN_SS 2 1 DMN65D8LW-7_SOT323-3~D
+DOCK_PWR_BAR
3 1
2
D
0.1U_0603_50V4Z~D
@ PC820
3301_DSCHRG_FET_GC
1
PD815
DK_PWRBAR
1 2 CD3301_DCIN BAT54CW_SOT323~D <44,45,56> DOCK_DET# PQ821A

DC_IN_SS
+DC_IN
PR835 47_0805_5%~D @ PR838 2 <46,56> SLICE_PERF_EN DMN66D0LDW-7 2N_SOT363-6~D
2
1
0_0402_5%~D 1 6 1 2
1
PC813 2 1 1 PR839 PD821

+PBATT DOCK_AC_OFF <44>
240K_0402_5% SDMK0340L-7-F_SOD323-2~D
0.1U_0603_50V4Z~D @ PR843 3 PQ821B
2
2
1
1
1
PQ822
0_0402_5%~D DMN66D0LDW-7 2N_SOT363-6~D
+5V_ALW
2
P50ALW 1 2 PR844 4 3 2
36
35
34
33
32
31
30
29
28
PU800 10K_0402_5%~D 2 1 2
<49> SOFT_START_GC +3.3V_ALW2 PQ831
1 2 @ PR850 3
DC_IN_SS
NC
BLK_MOSFET_GC
DSCHRG_MOSFET_GC
PBatt+
CHARGERVR_DCIN
DK_PWRBAR
GND
NC
+3.3V_ALW2
3
@ PR847 1
CD_PBATT_OFF 2 PR849 DMN65D8LW-7_SOT323-3~D
2
1
1
PQ830
PR846 100K_0402_5%~D 0_0402_5%~D 100K_0402_5%~D
1 2ACAVDK_SRC 0_0402_5%~D 2 1 2 2 1 1 3 +3.3V_ALW2
S
<44> ACAV_DOCK_SRC#
1
2
@ PR854 1 27 @ PR885 @ PR887 PR840 3 PR834 PC814
3
0_0805_5%~D 2 DC_IN P50ALW 26 0_0402_5%~D 47K_0402_5% 100K_0402_5%~D 0.1U_0402_10V7K~D
0_0402_5%~D
G
2
1 2 ERC1 3 SS_GC PBATT_OFF 25 DK_AC_OFF 2 1
+SDC_IN ERC1 DK_AC_OFF_EN
4 24 +DC_IN_SS 2 1
ACAV_IN_NB <46,55>
2
5 ACAVDK_SRC ACAV_IN_NB 23
GND GND
5
CD3301_SDC_IN 6 22 DK_AC_OFF_EN 1 2 PR833
SDC_IN DK_AC_OFF_EN DOCK_AC_OFF_EC <45>
7 21 PR858 100K_0402_5%~D 1
0.1U_0603_50V4Z~D
P
<55> DC_BLOCK_GC DC_BLK_GC SL_BAT_PRES# B SLICE_BAT_PRES# <44,45,49,56>
@ PC818
8 20 @ PR857 1M_0402_5%~D <46,56> SLICE_PERF_EN

<44,45,56> DOCK_DET# 4
ACAV_IN BLKNG_MOSFET_GC O
1
P33ALW2 9 19 0_0402_5%~D 1 2 +PBATT 2 DOCK_DET# <44,45,56>

P33ALW2 NBDK_DCINSS A
G
EN_DK_PWRBAR
<46,55,56> ACAV_IN
SS_DCBLK_GC
PU808 +3.3V_ALW2
2
3
DK_CSS_GC
74AHC1G08GW_SOT353~D
PWR_SRC
@ PR862 @ PQ823
CSS_GC
P33ALW
0_0402_5%~D 37 NTR4502PT1G_SOT23-3~D
TP
1
ERC3
ERC2
1 2 @ PR863
GND
+3.3V_ALW2
3
1 2 3 1 PR864
+NBDOCK_DC_IN_SS
0_0402_5%~D @ PR866 100K_0402_5%~D
CD3301BRHHR_QFN36_6X6~D 0_0402_5%~D
10
11
12
13
14
15
16
17
18
@ PR868 2 1 @ PQ824A
2
EN_DOCK_PWR_BAR <45>
2
2
0_0402_5%~D @ PR869DMN66D0LDW-7 2N_SOT363-6~D
0.1U_0603_25V7K~D
<55> CSS_GC P33ALW 1 2 1 2 1 2 6 1 ACAV_IN#

ERC2
<55> DK_CSS_GC +3.3V_ALW

@ PR870
1
PC815
ERC3 240K_0402_5%~D 47K_0402_5%~D
1
@ PQ824B
A D A
2
EN_DK_PWRBAR DMN66D0LDW-7 2N_SOT363-6~D 2

0.047U_0603_25V7K~D
<46,55,56> ACAV_IN
2
1 2 3 4 G
0.1U_0402_25V4Z~D
+3.3V_ALW2
1 2 S
3
PC816
@ PR875 PQ825
1
1M_0402_5%~D
PC817
STSTART_DCBLOCK_GC 100K_0402_5%~D DMN65D8LW-7_SOT323-3~D

5
PR874
1 2
<46,56> SLICE_PERF_EN
2
@ 3301_PWRSRC 1 2
+PWR_SRC_AC
@ PR883
@ PR877 0_0402_5%~D
0.1U_0603_50V4Z~D
@ PC819
0_0805_5%~D
1

2
4019MV
5 4 3 2 1
5 4 3 2 1
Based on PDDG rev 1.1 Table 5-1.
+VCC_CORE +VCC_CORE
Bottom inside socket
1 1 1 1
D 1 1 1 1 1 D
+ @ PC905 + PC906 + @ PC907 + PC908
PC900 PC901 PC902 PC903 PC904 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M
10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM
2 2 2 2 2 2 2 2 2
1 1 1 1 1 1
1
PC909 PC910 PC911 PC912 PC913 PC914
10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM + @ PC916
2 2 2 2 2 2 330U_D2_2.5VY_R9M
2
+VCC_CORE Top near socket edge
1 1 1 1 1
PC917 PC918 PC919 PC920 PC921
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2 2
Top inside socket

C 1 1 1 1 1 C
PC922 PC923 PC924 PC925 PC926

2 2 2 2 2
1 1 1 1 1
PC935 PC936 PC937 PC938 PC939
2 2 2 2 2
1 1 1 1
PC940 PC941 PC942 PC943
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2
Bottom near socket edge

B B
A A
Title
5 4 3 2 1
5 4 3 2 1
Version ChangeList ( P. I . R. List )

Request
I tem Page# Title Date Owner I ssueDescription Solution Description Rev.
D D
1 55 Charger 1/8 TI Change cell pin pull high reference voltage from Depop PR720 and pop PR746
X01
+3.3V_ALW to BQ24715_REGN
2 55 Charger 1/8 Compal Reduce adapter current ripple PC724,PC728,PC712,PC713,PC714,PC734 pop 22uF cap X01
3 54 VCC_CORE 1/8 Compal Reduce adapter current ripple Add input jump PJP500 and unpop PL504, PC516 pop 470pF X01
4 55 Charger 1/8 Compal Fine tune H_PROCHOT# response time. Add 0402 cap PC736(1.2nF) on PU701 pin1 X01
55 Charger 1/8 Compal Control H_PROCHOT# when AC removed. Add PR727(0 ohm) and MODULE_BATT_PRES# connect to PU701 pin1
5 X01
54 VCC_CORE 1/8 Compal Reduce noise on +VCCIO_OUT. Add 1uF cap (PC548) on +VCCIO_OUT
6 X01
HW
55 Charger 1/8 Compal For Input current sense stabilize. PC703 change from 0402 0.1uF to 0603 1uF
7 X01
C C
56 Selector 1/8 Compal For undock shutdown issue. Add PQ827 and gate connect to SLICE_BAT_PRES#.
8 X01
55 Charger 1/8 Compal To prevent charger into sleep mode when PC707 change from 1uF to 10uF.
9 X01
dual AC transient.
55 Charger 1/8 Compal Improve ACAV_IN_NB ref voltage accuracy. PR733 connect to +3.3V_ALW2. PR740 change from 12K to 10K
10 X01
PR733 change from 130k to 48.8k
54 VCC_CORE 1/8 Intersil Fine tune IMON,OCP, Iout offset. Add PR558 4.99M on ISUMP to GND. PR535 change from 432 to 499.
11 X01
PR521 change from 95.3k to 97.6k. PC500 change from 0.01u to 1000p
12 55 Charger 1/9 Compal Fine tune ACOK response time. PC708 change from 0.01uF to 0.1uF
X01
49 DCIN GPIO net - AC_DIS# is high active. X01

13 1/9 Compal AC_DIS# cahnge to AC_DIS.
56 selector Corrent net name.
B B
14 55 Charger 1/9 Compal Improve current sense accuracy. PR744=44.2ohm PR736=59ohm X01
AC_DIS circuit modify to improve

16 56 Selector 1/9 Compal Add PD820,PQ828,PQ829,PR895. X01
output voltage level.
17 52 1.05V_VM 1/11 Compal Improve output ripple voltage. Add 10uF(PC310) on output. X01
To prevent PD2 damage issue, PD2 pin5 connect to +3.3V_ALW, Add PR27 0 ohm
18 56 DCIN 1/14 Compal X01
ESD team suggest pin5 connect to VCC. PD2 change from NXP(SC300001100) to AMC(SC300001G00)
PR730 change from 150k to 249k

19 55 Charger 1/17 Compal Adapter protect from rating+0.75A to 2A. PR731 change from 66.5K to 162K X01
unpop PR727
A A
Title
5 4 3 2 1
5 4 3 2 1

Request
D D
1 49 DCIN 4/2 Compal PD2 ESD diode damange issue. ESD diode change from dual package to single
X02
ESD package(PD2,PD4)
2 All All 4/8 Compal 0 ohm resistor change to short pad.

PR26,PR103,PR110,PR118,PR208,PR210,PR211,PR308,PR309,PR406,PR511,PR520,
X02
PR866,PR868,PR882,PR886,PR887,PR888,PR890,PR892,PR895
3 49 DCIN 4/11 Compal Saving space. PL4 change from 0603 to 0402. X02
C C
B B
A A
Title
5 4 3 2 1
5 4 3 2 1

Request
D D
1 37,45,46 HW 12/10/2012 Compal Change R-Pak package. Change RP3,RP4,RP5,RP6,RP9,RP13 P/N to SD309100380
X01
(Change Package from 1206 to 0804)
Change RP8 P/N to SD309470180
2 46 HW 12/10/2012 Compal Change R-Pak package. X01
(Change Package from 1206 to 0804)
3 35 HW 12/10/2012 Compal Change New TPM Chip Change U39 P/N to SA00004WQ40 (AT97SC3204-DX4A12-ABF) X01
4 28 HW 12/18/2012 Compal Impact SMT DFX stilt and solder risk. Change JLVDS1 P/N from SP01001BS00 to SP01001BT00 X01
Reserve PCH GPIO 22 for moving SP_TPM_LPC_EN from OUT65

5 20,35 HW 12/21/2012 DELL Update GPIO map to rev 3.0C X01
and add PD 100k(RH332)
6 30 HW 12/21/2012 Compal Remove non-pop item Remove R3730 X01
7 46 HW 12/21/2012 DELL Update GPIO map to rev 3.0C Add a 0ohm resistor R3772 to short RUNPWROK and AND_PWRGD X01
C C
8 28 HW 12/21/2012 DELL ATG droop Remove ATG config 1@,2@ X01
9 40 HW 12/26/2012 Compal Support Samsung Galaxy Tab charger in S3. Change USB charger P/N from SLGC55584AVTR to SLG55594AVTR X01
10 38 ME 01/02/2013 Compal JSIM1 BOSS hole update from 3.55mm to 1.7mm. Change JSIM1 P/N from 159-1000302600 to 159-1000302602 X01
11 47 ME 01/03/2013 Compal JSF1 pitch change from 0.5mm to 1.0mm Change JSF1 P/N from A520620-SCHR22 to A090620-SAHR21 X01
1.Change R1119 ,R1120 to 100K

12 30 HW 01/03/2012 COMPAL Follow Realtek recommend circuit 2.Change R1677 R1679 to 9.1 ohm X01
3.Change C958,C960 from 0603 to 0805
B B
13 28 HW 01/04/2013 COMPAL Import U148 of 2nd source U148 pin4 connect to +3.3V_ALW and remove C33 X01
R820,R818,R829,R822 change to RP14

R1125,R810,R1156,R819 change to RP15
15,17,18, R814,R920,R870,R876 change to RP16
14 HW 01/04/2013 COMPAL Import R-Pak RH168,RH329,RH125 change to RPH18
20,46 X01
RH138,RH136,RH257,RH201 change to RPH19
15 46 HW 01/07/2013 COMPAL Change Board ID from X00 to X01 Change R875 from 240K to 130K X01
A A
Title
5 4 3 2 1
5 4 3 2 1

Request
D D
16 30 HW 01/08/2013 Compal Follow EMI request Change 0 ohm to 33 ohm bead for internal SPK (L702~L705) X01
Change C470,471 from 33pF to 27pF

17 17,33,46 HW 01/08/2013 Compal Follow Crystal EA result. Change CH13,CH14 from 18pF to 12pF
Change CH743,CH741 from 22pF to 33pF X01
18 38 HW 01/10/2013 Compal W/O WWAN reapeter EA test pass. Remove WWAN repeater X01
Change RC35 from 0hom to 0ohm short

19 7,16 HW 01/11/2013 Compal Follow ESD result. Pop RC52 1K X01
Reserve C1553 0.047u
C C
20 28 HW 01/14/2013 Compal To avoid +3.3V Camera inrush De-populate C300 10U_0805 CAP X01
The RTD2136R ripple is better than

21 27 HW 01/15/2013 Compal Change C109 from 22uF to 10uF. X01
S version. The cap can be use small.
22 7 HW 03/11/2013 Compal Follow Intel DG Rev.1.5 Change RC12 from 10k to 100k. X01
Change 0 ohm resistor to short pad

23 6~45 HW 04/01/2013 Compal For Vender recommend circuit
Change Q63 P/N from SB00000RV00 to SB00000ZN00 X02
Change L77 P/N from SM010022010 to SM01000MO00
24 26 HW 04/01/2013 Compal Follow Intel MOW Rev.1.0 Change R452,R450,R448,R449,R454,R453,R456,R455 from 680 ohm to 470 ohm. X02
B B
25 27 HW 04/01/2013 Compal Follow Realtek recommend circuit L60,L61,L62 change to R3881,R3882,R3883(Short 0ohm) X02
26 39 HW 04/01/2013 Dell Dell don't want EXP@ config on MB. Remove EXP@ config X02
R955 from 1.8k to 680 ohm

R938 from 1.8k to 680 ohm
Follow Icon Brightness result. R958 from 620 to 680 ohm
27 24 HW 04/01/2013 Compal X02
Change LED resistance. R934 from 1K to 1.8k ohm
R3671 from 1.4k to 1.8k ohm
R949 from 680 to 1.8k ohm
OZ777FJ2 enters into test mode unexpectedly

28 36 HW 04/01/2013 Compal Add R3884 1M ohm to GND on SD_CD# X02
with SD card inserted incompletely.
A A
Title
5 4 3 2 1
5 4 3 2 1

Request
D D
29 15~23,33 HW 04/01/2013 Compal Intel ChipSet update. Change PCH C1 version to C2 version. P/N from SA00006P30L to SA00006P33L X02
Change 330uF OSCON P/N from SF000002Z00 to SF000003100 (CD14,CD36)

30 13,14,40 HW 04/01/2013 Compal Update OSCON P/N for DFX issue X02
Change 220uF OSCON P/N from SF000002Y00 to SF000003000 (C651)
31 7 HW 04/01/2013 Compal No support CPU XDP JTAG PU/PD issue Pop RC59, RC62,RH52 for Intel recommend X02
32 46 HW 04/01/2013 COMPAL Change Board ID from X01 to X02 Change R875 from 130K to 33K X02
Change R725 PU Net from WIGIG60GHZ_DIS# to WIGIG60GHZ_DIS#_R

33 37 HW 04/08/2013 COMPAL Schematic synchronous X02
Add R3885 to WLAN_RADIO_DIS#_R
Add R3886 to BT_RADIO_DIS#_R
Pop C1553, CC17,CC18,CH2
The system running DVD will hand
C 34 7,16,32 HW 04/12/2013 COMPAL Add C1564 on PCH_PLTRST# (Non-pop) X02 C
when doing ESD test.
Add C1565 on PLTRST_EMB# (Non-pop)
Add C1566 on H_THERMTRIP#_R (Non-pop)
Add C1567 on XDP_RST#_R (Non-pop)
35 24 HW 04/12/2013 COMPAL Sleeve / Ring2 have EMI noise. H20 connect from GND to NC for ESD request. (EMI AGND and DGND noise) X02
Change TMP version from DX4A12 to X4A12.

36 35 HW 04/23/2013 COMPAL TPM Chip Update. X02
P/N from SA00004WQ40 to SA00004WQ50
Change PCH from R1 to R3.

P/N from SA00006P33L to SA00006P35L A00
37 15~23,33 HW 06/04/2013 COMPAL Change chip P/N to R3 Change PHY from R1 to R3.
P/N from SA00005OO3L to SA00005OO5L
38 46 HW 06/04/2013 COMPAL Change Board ID from X02 to A00 Change R875 from 33K to 1K A00
B B
Change RH177,RH178,RH179,RH181,RH182,RH183,
39 18 HW 06/04/2013 COMPAL Change 0 0hm to short 0 ohm A00
RH184,RH185 to short 0 ohm
A A
Title
5 4 3 2 1

Dell Latitude E6440

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Dell Latitude E6440

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A B C D E

USB2.0[12] Camera Through LVDS Cable

SD4.0/MMC PCIE2 JUSB4

RFID HDD HDA Codec INT.Speaker

CPU XDP Port LPC BUS PCIE4 E‐Module FFS

USB 2.0 USB 3.0

S3 (Suspend to RAM) / M3 LOW HIGH HIGH HIGH ON ON ON OFF OFF

9 6 Left Side (JUSB4)

Lane 7 Express card (JEXP1)

DDID Dock DP port 2

APL3512 TPS22966 TPS22966 TPS22966 TPS22966

+1.05V_RUN DELL CONFIDENTIAL/PROPRIETARY

JCPU1A Haswell rPGA EDS

VCCPWRGOOD_0_R XDP_TDI @ RC54 2 1 51_0402_1%

@ SM_RCOMP0 RC58 1 2 100_0402_1% XDP_TCLK RC59 2 1 51_0402_1%

SM_RCOMP1 RC61 1 2 75_0402_1% XDP_TRST# RC62 2 1 51_0402_1%

CAD Note: TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SCHEMATIC,MB LA-9931P

JCPU1C Haswell rPGA EDS

@ T52 PAD~D AR35 AH30

@ T53 PAD~D AR32 AH31

AT33 VSS VCC AJ26

B Place T72 close to G25 B

+VCC_CORE VCC L25

A10 AK34 B34 K10

+SA_DIMM_VREFDQ +SA_DIMM_VREFDQ_Q +1.35V_MEM

3 1 RD20 1 2 2_0402_1% DDR_A_D24 57 58 DDR_A_D29

DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11

DDR_A_BS0 109 110 DDR_A_RAS#

DDR_A_CAS# 115 116 M_ODT0

DDR_A_D40 147 148 DDR_A_D45

1 1 1 1 1 1 1 151 152 DDR_A_DQS#5

+ 153 154 DDR_A_DQS5

DDR_A_D49 165 166 DDR_A_D53

DDR_A_DQS6 171 172

1 +0.675V_DDR_VTT 203 204 +0.675V_DDR_VTT

@ RD4 2 10_0402_5% @ RD2

0.047U_0402_16V4Z @ RD7 0_0402_5% Title

2 DDR_B_D16 39 VSS13 VSS14 40 DDR_B_D20

DDR_B_D24 57 VSS20 DQ28 58 DDR_B_D29

127 128 @ RD10 0_0402_5%

133 134 @ RD23 0_0402_5%

DDR_B_D48 163 164 DDR_B_D52

+ DDR_B_DQS#6 169 170

+0.675V_DDR_VTT 203 204 +0.675V_DDR_VTT

Open Keep CMOS SPKR AL10 BC12

RH47 2 1 51_0402_1% PCH_JTAG_TCK AB3 AT1 HDD_DET#

@ RH53 0_0402_5% PAD~D T58 @

+1.5V_RUN 1 2 PCH_PCIE_IREF BE30 M33 PAD~D T82 @

+PCH_VCCDSW3_3 Support Deep S3 mode

+3.3V_RUN UH1F LPT_PCH_M_EDS

+1.05V_RUN P45 Voltage Rail Voltage S0 Iccmax Current (A)

U20 AK28 +1.5V_RUN

Support DEEP SX: populated RH238, de-populated RH237

Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36

Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32

AL34 K39 UH1K LPT_PCH_M_EDS

+3.3V_ALW Q83B Battery LED

Q79 <35,46> POWER_SW#_MB

LED Circuit Control Table

Mask All LEDs (Sniffer Function) 0 X

@ H1 @ H2 @ H3 @ H4 @ H5 @ H6 @ H7 @ H8 @ H9 @ H10 @ H11 @ H12

@ FD1 @ FD2 @ FD3 @ FD4

FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D