COMPAL LA 3301P IBQ00 REV 1.0 (ComunidadeTecnica - Com.br)

A B C D E
COMPAL CONFIDENTIAL
MODEL NAME : IBQ00
1 1
PCB NO : LA-3301P (DA80000771L)

BOM P/N : 45144631L01
M08 (UMA) Briscoe 2
uFCPGA Mobile Merom

Intel Crestline + ICH8M
2007-03-07
3
REV : 1.0 (A00) 3
DAZ P/N:DAZZGX0010L
MB PCB
Part Number Description
DA80000771L PCB ZGX LA-3301P BOM NO. 45144631L01

REV1 M/B UMA
PCB P/N: DA80000771L
PCB1
IBQ00
LS-3301P REV1
LED/B
LS-3301P REV1 LED/B
PCB1
IBQ00
LS-3302P REV1
IO/B
om
LS-3302P I/O Board
4 4
l.c
ai
tm
DELL CONFIDENTIAL/PROPRIETARY
ho
Compal Electronics, Inc.
f@
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Cover Sheet
in
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
xa
Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-3301P
he
Date: Wednesday, March 07, 2007 Sheet 1 of 58
A B C D E
A B C D E
Block Diagram
Compal confidential
Model : IBQ00
FAN Thermal Pentium-M
+FAN1_VOUT GUARDIAN III Merom -4MB (Socket P)
page 18
1 EMC4001 uFCPGA CPU CPU ITP Port Clock Generator 1
+3.3V_SUS page 18 +1.05V_VCCP
CK505
+VCC_CORE 478pin page 7,8,9 +1.05V_VCCP page 7 +3.3V_RUN page6
H_A#(3..35) H_D#(0..63)
System Bus
FSB 800 MHz
RGB CRT CONN
+5V_RUN page 20 RGB INTEL Memory BUS DDRII-DIMM X2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8
LVDS CONN +1.25V_RUN Crestline (DDR2) +1.8V_SUS 533 / 667MHz
page 16,17
on M/B Board page 19 LVDS +1.5V_RUN +0.9V_DDR_VTT
DVI DVI Bridge DVO +1.8V_SUS 1299pin BGA +1.8V_SUS
+1.05V_VCCP
SI1362A page 51
TV +3.3V_RUN USB[4] Smart Card
+1.8V_RUN page 10,11,12,13,14,15 OZ77CR6 SLOT
+5V_RUN page 31
USB[2,3] REAR USB2 : Rear Left as viewed from the back,

2 DMI USB Ports X2 USB3 Rear Right as viewed from the back
2
+3VRUN 33MHz
PCI BUS +1.5V_RUN +5V_SUS page 32
PCI_PIRQA# 100MHz
REQ#0 IDSEL:AD17
GNT#0 (PIRQD#,GNT#1,REQ#1)
48MHz USB[0,1] SIDE USB Ports X2 USB0 : side pair top,
DOCKING DOCKING CardBus +1.25V_RUN
INTEL +5V_SUS IO/Board USB1 : side pair bottom
+RTC_CELL
PORT BUFFER OZ711 LQFP ICH8-M
+3.3V_RUN
page 36 +5V_RUN page 35 +3.3V_RUN page 30 IEEE1394 +3.3V_SUS
Azalia I/F
USB[6]
page 30 676pin BGA PATA
DOCK LPC BUS USB[8] +1.5V_RUN
+1.05V_VCCP SATA
PCI Express BUS (+1.5V_RUN 100MHz) page 21,22,23,24
SPI
+3VRUN SC_USB
Mini Card2 Mini Card 1 GIGA Enthernet 33MHz LPC BUS M DC
BCM5755M +3.3V_SUS
WLAN WWAN +3.3V_LAN page 33
+2.5V_LAN
3
+3.3V_WLAN +3.3V_RUN +1.2V_LAN 3
+1.5V_RUN page 34 +1.5V_RUN page 34 Cable
page 28,29 SMSC SIO Azalia Codec
USB[9] DOCK LPC BUS
S-HDD D Moudle STAC9205
ECE5028 +3.3V_RUN
RJ45 +5V_HDD +5V_MOD RJ11
+3.3V_ALW page 38 page 25 page 25 +VDDA page 26 IO/B
IO/B
COM
+3.3V_SUS
PWR Sequence 1.8V / 0.9V/1.25V page 37 SPI
page 42 page 46
MEC5025
+RTC_CELL
ME & LED 1.5V / 1.05V ECE1077 +3.3V_ALW page 39
AMP & INT. INT MIC HeadPhone
+3.3V_ALW
page 37 +VDDA
page 43 page 47 Speaker page 27 & MIC Jack
+3.3V_RUN
+5V_RUN page 27 page 27
DC IN Vccore Int.KBD & ST M25P16

+3.3V_SUS page 39
page 44 page 48 Stick page 40
4 4
Battery IN Charger Bluetooth Stick Touch Pad Biometric

page 44 page 49 DELL CONFIDENTIAL/PROPRIETARY
+3.3V_RUN page 40 +5V_RUN page 40 +3.3V_RUN page 40
USB[7] USB[5] Title
3V / 5V /15V Battery Select Trough Cable Block Diagram
page 45 page 50 Size Document Number Rev
1.0
LA-3301P
Date: Wednesday, February 14, 2007 Sheet 2 of 58
A B C D E
5 4 3 2 1
POWER STATES
Signal SLP SLP SLP S4 SLP ALWAYS M SUS RUN CLOCKS
USB PORT# DESTINATION
State S3# S4# S5# STATE# M# PLANE PLANE PLANE PLANE
0 Side Top
D
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH HIGH ON ON ON ON ON D
1 Side Bottom
S3 (Suspend to RAM) / M1 LOW HIGH HIGH HIGH HIGH ON ON ON OFF ON
2 Rear Left
S4 (Suspend to DISK) / M1 LOW HIGH HIGH LOW HIGH ON ON ON OFF ON
3 Rear Right
S5 (SOFT OFF) / M1 LOW HIGH LOW LOW HIGH ON ON ON OFF ON
ICH8-M
4 Smart Card
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH HIGH LOW ON OFF ON OFF OFF
5 Biometric
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW LOW ON OFF OFF OFF OFF
6 Card Bus
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW LOW ON OFF OFF OFF OFF
7 Bluetooth
8 Docking
C
PM TABLE C
+15V_ALW +5V_SUS +5V_RUN 9 WWAN

+5V_ALW +3.3V_SUS +3.3V_RUN
+3.3V_ALW +1.8V_SUS +2.5V_RUN 1 None
power
plane +3.3V_RTC_LDO +1.8V_RUN
+1.5V_RUN 2 None
+0.9V_DDR_VTT
ECE 5028
+VCC_CORE 3 None
+1.05V_VCCP
State 4 None
+1.25V_RUN
S0 ON ON ON
S3 ON ON OFF
B
S5 S4/AC ON OFF OFF B
S5 S4/AC don't exist OFF OFF OFF

PCI EXPRESS DESTINATION
Lane 1 MINI CARD-1 WWAN
Lane 2 MINI CARD-2 WLAN

PCI TABLE
Lane 3 None
PCI DEVICE IDSEL REQ#/GNT# PIRQ Lane 4 None
Lane 5 None
OZ711 AD17 REQ#1 / GNT#1 PIRQD
Lane 6 GIGA LAN
om
A
Docking AD24 REQ#0 / GNT#0 PIRQA A
l.c
ai
tm
ho
f@
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Index and Config.
in
xa
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-3301P
he
5 4 3 2 1
5 4 3 2 1
RUN_ON FDS4435
+INV_PWR_SRC
(Q24)
ADAPTER
D D
+15V_ALW
ALWON
+5V_ALW RUN_ON
ISL6260 ISL6236 ISL6236 ISL6236 SI4810DY +5V_RUN
+PWR_SRC (PU11) (PU22) (PU21) (PU20) ALWON (Q52)
BATTERY +3.3V_ALW
RUNPWROK
1.05V_RUN_ON
1.5V_RUN_ON
DDR_ON
M_ON
ENAB_3VLAN
RUN_ON
CHARGER +VCC_CORE +1.8V_SUS +1.25V_RUN +1.05V_VCCP +1.5V_RUN
SI3456BDV SI4810DY
0.9V_DDR_VTT_ON
C (Q69) (Q58) C
RUN_ON
SUS_ON
+3.3V_LAN +3.3V_RUN
TPS51100 SI3456BDV
REGCTL_PNP25
REGCTL_PNP12
+5V_SUS +3.3V_SUS
(PU24) (Q54)
AUDIO_AVDD_ON
B BCP69 MMJT9435T1G B
HDDC_EN#
MODC_EN#
(Q70) (Q71)
SI3456BDV SI3456 MAX9789A
(Q56) (Q48) (U37)
+0.9V_DDR_VTT +1.8VRUN
+2.5V_LAN +1.2V_LAN
+5V_HDD +5V_MOD +VDDA
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Rail
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
LA-3301P
5 4 3 2 1
5 4 3 2 1
2.2K 2.2K
+3.3V_SUS +3.3V_RUN
2.2K 2.2K
AJ26 ICH_SMBCLK MEM_SCLK 197
2N7002 MEM_SDATA
AD19 ICH_SMBDATA 195 DIMMA SMBUS Address [TBD]
ICH8-M 2N7002
32 30 C7 C8 32 30
197
WWAN Intel LAN 2.2K 195
D D
DIMMB SMBUS Address [TBD]
+3.3V_WLAN
2.2K
SMBUS Address [TBD] SMBUS Address [TBD]
WLAN_SMBCLK @ 0 CLK_SCLK
2N7002 WLAN_SMBDATA WLAN @ 0 CLK_SDATA
2N7002
SMBUS Address [TBD]
8.2K
8.2K
+3.3V_ALW
8 LCD_SMBCLK 6
INVERTER
7 LCD_SMDATA SMBUS Address [TBD]
(JLVDS)
C 4.7K 5 C
10
+3.3V_ALW Charger SMBUS Address [TBD]
4.7K 9
100 THRM_SMBCLK 12
99 THRM_SMBDAT 11 EMC4001 SMBUS Address [TBD]
2.2K
+3.3V_ALW
2.2K
10 SBAT_SMBCLK 100 ohm 3
2'nd
SBAT_SMBDAT 100 ohm 4 BATTERY SMBUS Address [TBD]
9
SIO 2.2K
2.2K
+3.3V_ALW
111 PBAT_SMBCLK 100 ohm 3
PBAT_SMBDAT
BATTERY SMBUS Address [TBD]
112 100 ohm 4
CONN
B B
9
10 CHARGER SMBUS Address [TBD]
8.2K
8.2K +5V_ALW
6 DOCK_SMB_CLK 6
MEC 5025 5 DOCK_SMB_DAT 5 DOCKING SMBUS Address [TBD]
2.2K
+3.3V_RUN
2.2K
12 CKG_SMBDAT CLK_SDATA 17
2N7002
13 CKG_SMBCLK CLK_SCLK 16 CLK GEN SMBUS Address [TBD]
2N7002
om
A A
l.c
ai
tm
ho
f@
Title
SMBUS TOPOLOGY
in
xa
1.0
LA-3301P
he
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN +CK_VDD_MAIN
Non-iAMT
+3.3V_RUN +CK_VDD_MAIN
1 2
2.2K_0402_5%~D
2.2K_0402_5%~D
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
L28
Non-iAMT
1
BLM21PG600SN1D_0805~D +3.3V_RUN
1 1 1 1 1 1 1
C471
R265
R266
C472
C473
C474
C475
C476
C477
@ R435
1 2 MINI1CLK_REQ# 1 2
0_0402_5%~D 2 +CK_VDD_MAIN2 2 2 2 2 2 2 R315 10K_0402_5%~D
2
MINI2CLK_REQ# 1 2
CLK_SDATA R310 10K_0402_5%~D
S
39 CKG_SMBDAT 1 3 1 2
Q34 L87 CLK_3GPLLREQ# 1 2
2N7002W-7-F_SOT323-3~D BLM21PG600SN1D_0805~D R297 10K_0402_5%~D
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
SATA_CLKREQ# 1 2
G
2
+3.3V_RUN 1 1 1 R283 10K_0402_5%~D
D LOM_CLKREQ# D
1 2
C480
C481
C482
Q35 R301 10K_0402_5%~D
G
2N7002W-7-F_SOT323-3~D +CK_VDD_48 +CK_VDD_REF
CLK_SCLK 2 2 2
39 CKG_SMBCLK 1 3
4.7U_0603_6.3V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V7K~D
D
S
1 1 1
1 2
C99
C799
C189
@ R440
0_0402_5%~D R759
2 2 2 +CK_VDD_A
1 2
4.7U_0603_6.3V4Z~D
0.047U_0402_16V4Z~D
2.2_0603_5%~D
FSC FSB FSA CPU SRC PCI 1 1
C478
C479
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz U28 CLK_ICH_14M
2 2
0 0 0 266 100 33.3 CLK_ICH_48M CLK_SMC_48M 1
3.3P_0402_50V8C~D
3.3P_0402_50V8C~D
1 VDD_SRC VDD_A 7
49 C775
VDD_SRC 3.3P_0402_50V8C~D
0 0 1 133 100 33.3 1 1 54 VDD_SRC SLG8LP550 VSS_A 8
2
65 @
VDD_SRC
C708
C774
0 1 0 200 100 33.3 25 H_STP_PCI# CLK_SIO_14M
* 2 2
30 VDD_PCI
PCI_STP#
H_STP_CPU#
H_STP_PCI# 23
36 VDD_PCI CPU_STP# 24 H_STP_CPU# 23 1
0 1 1 166 100 33.3
12 C776
C483 X1 R760 VDD_CPU MCH_BCLK CLK_MCH_BCLK 3.3P_0402_50V8C~D
CPU_1 11 1 2 CLK_MCH_BCLK 10
27P_0402_50V8J~D 14.31818MHz_20P_1BX14318CC1A~D 2
1 0 0 333 100 33.3 1 2 +CK_VDD_REF 18 VDD_REF
R267 33_0402_5%~D @
2 1 1_0603_5%~D 10 MCH_BCLK# 1 2 CLK_MCH_BCLK#
CPU_1# CLK_MCH_BCLK# 10
1 2 +CK_VDD_48 40 VDD_48
R268 33_0402_5%~D CLK_PCI_TPM
1
1 0 1 100 100 33.3 R758 2.2_0603_5%~D
C CPU_BCLK CLK_CPU_BCLK C
CPU_0 14 1 2 CLK_CPU_BCLK 7 1
Place crystal within CLK_XTAL_IN 20 R269 33_0402_5%~D
C484 R271 XTAL_IN CPU_BCLK# CLK_CPU_BCLK# C777
1 1 0 400 100 33.3 500 mils of CK410 13 1 2 CLK_CPU_BCLK# 7
2
33P_0402_50V8J~D 0_0402_5%~D CPU_0# R270 33_0402_5%~D 3.3P_0402_50V8C~D
CLK_XTAL_OUT 2 @
2 1 1 2 19 XTAL_OUT
1 1 1 200 100 33.3 6 CPU_ITP 1 2 CLK_CPU_ITP
CPU_ITP/SRC_10 CLK_CPU_ITP 7
CLK_ICH_48M 2 1 R272 33_0402_5%~D CLK_PCI_DOCK
23 CLK_ICH_48M
CLK_SMC_48M R273 1 2 15_0402_5%~D FSA 41 5 CPU_ITP# 1 2 CLK_CPU_ITP#
31 CLK_SMC_48M USB_48MHz/FSLA CPU_ITP#/SRC_10# CLK_CPU_ITP# 7
Table : ICS954305AK 8,10 CPU_MCH_BSEL0 R275 1 2 15_0402_5%~D R274 33_0402_5%~D 1
8,10 CPU_MCH_BSEL1 R309 2.2K_0402_5%~D 45 FSL_B/TEST_MODE PCIE_MINI1 CLK_PCIE_MINI1 C778
SRC_9 3 1 2 CLK_PCIE_MINI1 34
1 2 FSC 23 R311 33_0402_5%~D 3.3P_0402_50V8C~D
8,10 CPU_MCH_BSEL2 REF_0/FSL_C/TEST_SEL 2
R314 8.2K_0402_5%~D 2 PCIE_MINI1# 1 2 CLK_PCIE_MINI1# @
SRC_9# R313 33_0402_5%~D CLK_PCIE_MINI1# 34
CPU_BSEL CPU_BSEL2(FSC) CPU_BSEL1(FSB)
CLK_PCI_TPM 2 1 PCI_LOM 34 72 MINI1CLK_REQ# 34 CLK_PCI_PCM
28 CLK_PCI_TPM PCICLK4/FCT_SEL CLKREQ_9#
CLK_PCI_DOCK R277 2 1 33_0402_5%~D
36 CLK_PCI_DOCK
R596 33_0402_5%~D PCI_DOCK 33 70 PCIE_MINI2 1 2 CLK_PCIE_MINI2 1
PCICLK3 SRC_8 CLK_PCIE_MINI2 34
133 0 0 CLK_PCI_PCM 2 1 R306 33_0402_5%~D
30 CLK_PCI_PCM
R280 33_0402_5%~D PCI_PCM 32 69 PCIE_MINI2# 1 2 CLK_PCIE_MINI2# C779
PCICLK2/TME SRC_8# CLK_PCIE_MINI2# 34 3.3P_0402_50V8C~D
CLK_PCI_5025 2 1 R307 33_0402_5%~D
39 CLK_PCI_5025 2
CLK_PCI_5018 R282 1 2 15_0402_5%~D PCI_SIO 27 71 MINI2CLK_REQ# 34 @
38 CLK_PCI_5018 PCICLK1 CLKREQ_8#
166 0 1 R333 15_0402_5%~D
CLK_ICH_14M 1 2 66 PCIE_ICH 1 2 CLK_PCIE_ICH CLK_PCI_5025
23 CLK_ICH_14M SRC_7 CLK_PCIE_ICH 23
R284 15_0402_5%~D CLKREF 22 R288 33_0402_5%~D
CLK_SIO_14M REF_1 PCIE_ICH# CLK_PCIE_ICH#
38 CLK_SIO_14M 1 2 SRC_7# 67 1 2 CLK_PCIE_ICH# 23 1
R285 15_0402_5%~D R289 33_0402_5%~D
MCH_DREFCLK 1 2 DOT96 43 38 C780
+3.3V_RUN 10 MCH_DREFCLK DOT_96/27M CLKREQ_7# 3.3P_0402_50V8C~D
R286 33_0402_5%~D
MCH_DREFCLK# DOT96# PCIE_LOM CLK_PCIE_LOM 2 @
10 MCH_DREFCLK# 1 2 44 DOT_96#/27M_SS SRC_6 63 1 2 CLK_PCIE_LOM 28
R287 33_0402_5%~D R299 33_0402_5%~D
2
64 PCIE_LOM# 1 2 CLK_PCIE_LOM# CLK_PCIE_LOM# 28 CLK_PCI_5018

R290 CLK_PCI_ICH PCI_ICH SRC_6# R168 33_0402_5%~D
21 CLK_PCI_ICH 2 1 37 PCICLK_F0/ITP_EN
B 10K_0402_5%~D R291 33_0402_5%~D B
CLKREQ_6# 62 LOM_CLKREQ# 28 1
23 CLK_PWRGD CLK_PWRGD 39 60 C781

1
PCI_PCM @ R295 CKPWRGD/PD# SRC_5 3.3P_0402_50V8C~D

10K_0402_5%~D 2 @
SRC_5# 61
1 2 PGMODE 9
Non-iAMT +3.3V_RUN
@ R298 PGMODE
CLKREQ_5# 29 CLK_PCI_ICH
1 2
10K_0402_5%~D 58 1
CLK_SCLK SRC_4
34 CLK_SCLK 16 SMBCLK
59 C785
SRC_4# 3.3P_0402_50V8C~D
2
+3.3V_RUN
PGMODE PIN 9 CLKREQ_4# 57 @
34 CLK_SDATA CLK_SDATA 17 SMBDAT MCH_3GPLL CLK_MCH_3GPLL
0 VTT_PWRGD#/PD SRC_3 55 1 2 CLK_MCH_3GPLL 10
R293 33_0402_5%~D
Non-iAMT
1
1 CKPWRGD/PD# 4 56 MCH_3GPLL# 1 2 CLK_MCH_3GPLL# CLK_MCH_3GPLL# 10

R304 VSS_SRC SRC_3# R294 33_0402_5%~D
10K_0402_5%~D 15 VSS_CPU CLKREQ_3# 28 1 2 CLK_3GPLLREQ# 10
R419 475_0402_1%~D
ITP_EN PIN 37 21 52
2
PCI_ICH VSS_REF SRC_2

0 Pin 5/6 as SRC_10 31 VSS_PCI SRC_2# 53
1 Pin 5/6 as CPU_ITP 35 26

+3.3V_RUN +3.3V_RUN * VSS_PCI CLKREQ_2#
PCIE_SATA CLK_PCIE_SATA
42 VSS_48 SRC_1/SATA 50 1 2 CLK_PCIE_SATA 22
R279 33_0402_5%~D
1
TME PIN 32 68 51 PCIE_SATA# 1 2 CLK_PCIE_SATA# CLK_PCIE_SATA# 22

R318 @ R329 VSS_SRC SRC_1#/SATA# R281 33_0402_5%~D
10K_0402_5%~D 10K_0402_5%~D 0 Normal Operation 46 SATA_CLKREQ# 23
CLKREQ_1#
@ 73 THRM_PAD
A DOT96_SSC A
1 Trusted Mode Enabled 74 47 1 2
* DREF_SSCLK 10
2
PCI_LOM FSA THRM_PAD LCD_CLK/SRC_0 R316 33_0402_5%~D

75 THRM_PAD
76 48 DOT96_SSC# 1 2
THRM_PAD LCD_CLK#/SRC_0# DREF_SSCLK# 10
1
R317 33_0402_5%~D
R319 @ R391
10K_0402_5%~D 10K_0402_5%~D FCTSEL1 PIN43 PIN44 PIN47 PIN48
SLG8LP550_QFN72~D
2
0=UMA DOT96T DOT96C 96/100M_T 96/100M_C

* PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Title
0=UMA 1=DIS 27M_out 27M SSout SRCT0 SRCC0 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Clock Generator
1=Disc. GRFX down PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-3301P
Date: Monday, February 26, 2007 Sheet 6 of 58
5 4 3 2 1
5 4 3 2 1
JCPUA +1.05V_VCCP
29
10 H_A#[3..35]
JITP
H_A#3 J4 H1 H_ADS#
GND6
H_A#4 A[3]# ADS# H_BNR# H_ADS# 10
L5 A[4]# BNR# E2 H_BNR# 10 28 VTT1
H_A#5 L4 G5 H_BPRI# 27
A[5]# BPRI# H_BPRI# 10 VTT0
H_A#6 K5 26
A[6]# VTAP JCPUD
ADDR GROUP 0
H_A#7 M3 ITP_DBRESET# 25
H_A#8 A[7]# H_DEFER# DBR#
N2 A[8]# DEFER# H5 H_DEFER# 10 24 DBA# A4 VSS[001] VSS[082] P6
H_A#9 J1 F21 H_DRD Y# 23 A8 P21
D A[9]# DRDY# H_DRDY# 10 BPM0# VSS[002] VSS[083] D
H_A#10 N3 E1 H_DBSY# 22 A11 P24
A[10]# DBSY# H_DBSY# 10 GND5 VSS[003] VSS[084]
H_A#11 P5 21 A14 R2
H_A#12 A[11]# H_BR0# BPM1# VSS[004] VSS[085]
P2 A[12]# BR0# F1 H_BR0# 10 20 GND4 A16 VSS[005] VSS[086] R5
H_A#13 L2 R320 19 A19 R22
H_A#14 A[13]# H_IERR# BPM2# VSS[006] VSS[087]
P4 A[14]# IERR# D20 2 1 +1.05V_VCCP 18 GND3 A23 VSS[007] VSS[088] R25
H_A#15 P1 B3 H_INIT# 17 AF2 T1
A[15]# INIT# H_INIT# 22 BPM3# VSS[008] VSS[089]
CONTROL
H_A#16 R1 56_0402_5%~D 16 B6 T4
H_ADSTB#0 A[16]# H_LOCK# GND2 VSS[009] VSS[090]
10 H_ADSTB#0 M1 ADSTB[0]# LOCK# H4 H_LOCK# 10 15 BPM4# B8 VSS[010] VSS[091] T23
R321 14 B11 T26
H_REQ#0 H_RESET# 22.6_0402_1%~D GND1 VSS[011] VSS[092]
10 H_REQ#0 K3 REQ[0]# RESET# C1 H_RESET# 10 13 BPM5# B13 VSS[012] VSS[093] U3
H_REQ#1 H2 F3 H_RS#0 H_RESET# 1 2 12 B16 U6
10 H_REQ#1 REQ[1]# RS[0]# H_RS#0 10 RESET# VSS[013] VSS[094]
H_REQ#2 K2 F4 H_RS#1 11 B19 U21
10 H_REQ#2 REQ[2]# RS[1]# H_RS#1 10 FBO VSS[014] VSS[095]
H_REQ#3 J3 G3 H_RS#2 10 B21 U24
10 H_REQ#3 REQ[3]# RS[2]# H_RS#2 10 GND0 VSS[015] VSS[096]
H_REQ#4 L1 G2 H_TRDY# CLK_CPU_ITP 9 B24 V2
10 H_REQ#4 REQ[4]# TRDY# H_TRDY# 10 6 CLK_CPU_ITP BCLKP VSS[016] VSS[097]
CLK_CPU_ITP# 8 C5 V5
6 CLK_CPU_ITP# BCLKN VSS[017] VSS[098]
H_A#17 Y2 G6 H_HIT# 7 C8 V22
A[17]# HIT# H_HIT# 10 TDO VSS[018] VSS[099]
H_A#18 U5 E4 H_HITM# 6 C11 V25
A[18]# HITM# H_HITM# 10 NC2 VSS[019] VSS[100]
H_A#19 R3 5 C14 W1
A[19]# TCK VSS[020] VSS[101]
ADDR GROUP 1
H_A#20 W6 AD4 ITP_BPM#0 T47 PAD~D 4 C16 W4
H_A#21 A[20]# BPM[0]# ITP_BPM#1 NC1 VSS[021] VSS[102]
U4 A[21]# BPM[1]# AD3 T48 PAD~D 3 TRST# C19 VSS[022] VSS[103] W23
XDP/ITP SIGNALS
H_A#22 Y5 AD1 ITP_BPM#2 T49 PAD~D 2 C2 W26
A[22]# BPM[2]# TMS VSS[023] VSS[104]
GND7
H_A#23 U1 AC4 ITP_BPM#3 T50 PAD~D 1 C22 Y3
H_A#24 A[23]# BPM[3]# ITP_BPM#4 +1.05V_VCCP TDI VSS[024] VSS[105]
R4 A[24]# PRDY# AC2 T51 PAD~D C25 VSS[025] VSS[106] Y6
H_A#25 T5 AC1 ITP_BPM#5 T52 PAD~D D1 Y21
H_A#26 A[25]# PREQ# ITP_TCK @ MOLEX_52435-2891_28P~D VSS[026] VSS[107]
T3 AC5 D4 Y24
30
A[26]# TCK VSS[027] VSS[108]
1
H_A#27 W2 AA6 ITP_TDI D8 AA2
H_A#28 A[27]# TDI ITP_TDO R323 VSS[028] VSS[109]
W5 A[28]# TDO AB3 D11 VSS[029] VSS[110] AA5
H_A#29 Y4 AB5 ITP_TMS 56_0402_5%~D D13 AA8
H_A#30 A[29]# TMS ITP_TRST# VSS[030] VSS[111]
U2 A[30]# TRST# AB6 D16 VSS[031] VSS[112] AA11
H_A#31 V4 C20 ITP_DBRESET# ITP_DBRESET# 23,38 D19 AA14
2
H_A#32 A[31]# DBR# VSS[032] VSS[113]
W3 A[32]# D23 VSS[033] VSS[114] AA16
H_A#33 AA4 EC_CPU_PROCHOT# D26 AA19
C H_A#34 A[33]# THERMAL EC_CPU_PROCHOT# 39 VSS[034] VSS[115] C
AB2 A[34]# E3 VSS[035] VSS[116] AA22
H_A#35 AA3 D21 H_THERMDA E6 AA25
H_ADSTB#1 A[35]# PROCHOT# H_THERMDA 18 VSS[036] VSS[117]
10 H_ADSTB#1 V1 ADSTB[1]# THERMDA A24 1 E8 VSS[037] VSS[118] AB1
THERMDC B25 E11 VSS[038] VSS[119] AB4
H_A20M# A6 C417 +1.05V_VCCP E14 AB8
22 H_A20M# A20M# VSS[039] VSS[120]
ICH
H_FERR# A5 C7 2200P_0402_50V7K~D E16 AB11

22 H_FERR# H_IGNNE# FERR# THERMTRIP# H_THERMDC 2 VSS[040] VSS[121]
22 H_IGNNE# C4 IGNNE# H_THERMDC 18 @ @ E19 VSS[041] VSS[122] AB13
E21 VSS[042] VSS[123] AB16
H_STPCLK# D5 H_THERMTRIP# H_THERMDA, H_THERMDC routing together, 1 1 E24 AB19
22 H_STPCLK# STPCLK# H_THERMTRIP# 18 VSS[043] VSS[124]
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
H_INTR C6 H CLK F5 AB23
22 H_INTR LINT0 Trace width / Spacing = 10 / 10 mil VSS[044] VSS[125]
C485
C486
H_NMI B4 A22 CLK_CPU_BCLK F8 AB26
22 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 6 VSS[045] VSS[126]
H_SMI# A3 A21 CLK_CPU_BCLK# F11 AC3
22 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 6 2 2 VSS[046] VSS[127]
F13 VSS[047] VSS[128] AC6
F16 VSS[048] VSS[129] AC8
M4 RSVD[01] F19 VSS[049] VSS[130] AC11
N5 RSVD[02] F2 VSS[050] VSS[131] AC14
T2 RSVD[03] F22 VSS[051] VSS[132] AC16
V3 RSVD[04] F25 VSS[052] VSS[133] AC19
Place near JITP
RESERVED
B2 RSVD[05] G4 VSS[053] VSS[134] AC21

C3 RSVD[06] G1 VSS[054] VSS[135] AC24
D2 RSVD[07] G23 VSS[055] VSS[136] AD2
D22 RSVD[08] G26 VSS[056] VSS[137] AD5
D3 RSVD[09] H3 VSS[057] VSS[138] AD8
F6 +3.3V_SUS H6 AD11
RSVD[10] R324 VSS[058] VSS[139]
H21 VSS[059] VSS[140] AD13
150_0402_5%~D H24 AD16
ITP_DBRESET# VSS[060] VSS[141]
1 2 J2 VSS[061] VSS[142] AD19
TYCO_1-1674770-2_Merom~D J5 AD22
VSS[062] VSS[143]
J22 VSS[063] VSS[144] AD25
+1.05V_VCCP J25 AE1
R325 VSS[064] VSS[145]
K1 VSS[065] VSS[146] AE4
51_0402_5%~D K4 AE8
B ITP_TDO VSS[066] VSS[147] B
K23 VSS[067] VSS[148] AE11
K26 VSS[068] VSS[149] AE14
R326 L3 AE16
51_0402_1%~D VSS[069] VSS[150]
L6 VSS[070] VSS[151] AE19
R327 H_RESET# L21 AE23
56_0402_5%~D VSS[071] VSS[152]
L24 VSS[072] VSS[153] AE26
+1.05V_VCCP 1 2 H_THERMTRIP# R328 M2 VSS[073] VSS[154] A2
39_0402_1%~D M5 AF6
ITP_TMS VSS[074] VSS[155]
M22 VSS[075] VSS[156] AF8
M25 VSS[076] VSS[157] AF11
R330 N1 AF13
150_0402_5%~D VSS[077] VSS[158]
N4 VSS[078] VSS[159] AF16
ITP_TDI N23 AF19
VSS[079] VSS[160]
This shall place near CPU N26 VSS[080] VSS[161] AF21
P3 VSS[081] VSS[162] A25
VSS[163] AF25
R331
649_0402_1%~D
1 2 ITP_TRST# TYCO_1-1674770-2_Merom~D
R332
27_0402_1%~D
ITP_TCK
om
A A
l.c
ai
tm
ho
f@
Title
Merom Processor(1/2)
in
xa
1.0
he
5 4 3 2 1
5 4 3 2 1
+VCC_CORE +VCC_CORE
JCPUC
A7 VCC[001] VCC[068] AB20
A9 VCC[002] VCC[069] AB7
A10 VCC[003] VCC[070] AC7
A12 VCC[004] VCC[071] AC9
A13 VCC[005] VCC[072] AC12
A15 VCC[006] VCC[073] AC13
A17 VCC[007] VCC[074] AC15
A18 VCC[008] VCC[075] AC17
A20 VCC[009] VCC[076] AC18
B7 VCC[010] VCC[077] AD7
D D
B9 VCC[011] VCC[078] AD9
10 H_D#[0..63] B10 VCC[012] VCC[079] AD10
JCPUB B12 VCC[013] VCC[080] AD12
B14 VCC[014] VCC[081] AD14
H_D#0 E22 Y22 H_D#32 B15 AD15
H_D#1 D[0]# D[32]# H_D#33 VCC[015] VCC[082]
F24 D[1]# D[33]# AB24 B17 VCC[016] VCC[083] AD17
H_D#2 E26 V24 H_D#34 B18 AD18
H_D#3 D[2]# D[34]# H_D#35 VCC[017] VCC[084]
G22 D[3]# D[35]# V26 B20 VCC[018] VCC[085] AE9
H_D#4 F23 V23 H_D#36 C9 AE10
H_D#5 D[4]# D[36]# H_D#37 VCC[019] VCC[086]
G25 D[5]# D[37]# T22 C10 VCC[020] VCC[087] AE12
DATA GRP 0
H_D#6 E25 U25 H_D#38 C12 AE13
H_D#7 D[6]# D[38]# H_D#39 VCC[021] VCC[088]
DATA GRP 2
E23 D[7]# D[39]# U23 C13 VCC[022] VCC[089] AE15
H_D#8 K24 Y25 H_D#40 C15 AE17
H_D#9 D[8]# D[40]# H_D#41 VCC[023] VCC[090]
G24 D[9]# D[41]# W22 C17 VCC[024] VCC[091] AE18
H_D#10 J24 Y23 H_D#42 C18 AE20
H_D#11 D[10]# D[42]# H_D#43 VCC[025] VCC[092]
J23 D[11]# D[43]# W24 D9 VCC[026] VCC[093] AF9
H_D#12 H22 W25 H_D#44 D10 AF10
H_D#13 D[12]# D[44]# H_D#45 VCC[027] VCC[094]
F26 D[13]# D[45]# AA23 D12 VCC[028] VCC[095] AF12
H_D#14 K22 AA24 H_D#46 D14 AF14
H_D#15 D[14]# D[46]# H_D#47 VCC[029] VCC[096]
H23 D[15]# D[47]# AB25 D15 VCC[030] VCC[097] AF15
10 H_DSTBN#0 H_DSTBN#0 J26 Y26 H_DSTBN#2 H_DSTBN#2 10 D17 AF17
H_DSTBP#0 DSTBN[0]# DSTBN[2]# H_DSTBP#2 VCC[031] VCC[098]
10 H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 10 D18 VCC[032] VCC[099] AF18
H_DINV#0 H25 U22 H_DINV#2 E7 AF20
10 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 10 VCC[033] VCC[100]
E9 VCC[034]
E10 VCC[035] VCCP[01] G21 +1.05V_VCCP
H_D#16 N22 AE24 H_D#48 E12 V6
H_D#17 D[16]# D[48]# H_D#49 VCC[036] VCCP[02]
K25 D[17]# D[49]# AD24 E13 VCC[037] VCCP[03] J6
220U_D2_4VY_R15M~D
H_D#18 P26 AA21 H_D#50 E15 K6 1
H_D#19 D[18]# D[50]# H_D#51 VCC[038] VCCP[04]
R23 D[19]# D[51]# AB22 E17 VCC[039] VCCP[05] M6
C487
H_D#20 L23 AB21 H_D#52 E18 J21 +
H_D#21 D[20]# D[52]# H_D#53 VCC[040] VCCP[06]
M24 D[21]# D[53]# AC26 E20 VCC[041] VCCP[07] K21
H_D#22 L22 AD20 H_D#54 F7 M21
D[22]# D[54]# VCC[042] VCCP[08] 2
DATA GRP 1
C H_D#23 H_D#55 C
M23 AE22 F9 N21
H_D#24 P25
D[23]#
D[24]#
DATA GRP 3 D[55]#
D[56]# AF23 H_D#56 F10
VCC[043]
VCC[044]
VCCP[09]
VCCP[10] N6 CRB was 270uF
H_D#25 P23 AC25 H_D#57 F12 R21
H_D#26 D[25]# D[57]# H_D#58 VCC[045] VCCP[11]
P22 D[26]# D[58]# AE21 F14 VCC[046] VCCP[12] R6
H_D#27 T24 AD21 H_D#59 F15 T21
H_D#28 D[27]# D[59]# H_D#60 VCC[047] VCCP[13]
R24 D[28]# D[60]# AC22 F17 VCC[048] VCCP[14] T6
H_D#29 L25 AD23 H_D#61 F18 V21
H_D#30 D[29]# D[61]# H_D#62 VCC[049] VCCP[15]
T25 D[30]# D[62]# AF22 F20 VCC[050] VCCP[16] W21
H_D#31 N25 AC23 H_D#63 AA7
H_DSTBN#1 D[31]# D[63]# H_DSTBN#3 VCC[051]
10 H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 10 AA9 VCC[052] VCCA[1] B26 +1.5V_RUN
0.01U_0402_16V7K~D
10U_0805_10V4Z~D
10 H_DSTBP#1 H_DSTBP#1 M26 AF24 H_DSTBP#3 H_DSTBP#3 10 AA10 C26
H_DINV#1 DSTBP[1]# DSTBP[3]# H_DINV#3 VCC[053] VCCA[2]
10 H_DINV#1 N24 DINV[1]# DINV[3]# AC20 H_DINV#3 10 AA12 VCC[054]
AA13 AD6 VID0
VCC[055] VID[0] VID0 48
AA15 AF5 VID1 1 1
VCC[056] VID[1] VID1 48
C488
C489
V_CPU_GTLREF AD26 R26 COMP0 AA17 AE5 VID2
GTLREF COMP[0] VCC[057] VID[2] VID2 48
MISC U26 COMP1 AA18 AF4 VID3
COMP[1] VCC[058] VID[3] VID3 48
TEST1 C23 AA1 COMP2 AA20 AE3 VID4
TSET1 COMP[2] VCC[059] VID[4] VID4 48 2 2
TEST2 D25 Y1 COMP3 AB9 AF3 VID5
TEST2 COMP[3] VCC[060] VID[5] VID5 48
TEST3 C24 AC10 AE2 VID6
TEST3 VCC[061] VID[6] VID6 48
54.9_0402_1%~D
27.4_0402_1%~D
54.9_0402_1%~D
27.4_0402_1%~D
TEST4 AF26 E5 H_DPRSTP# AB10
TEST4 DPRSTP# H_DPRSTP# 10,22,48 VCC[062]
1
TEST5 AF1 B5 H_DPSLP# AB12
TEST5 DPSLP# H_DPSLP# 22 VCC[063]
R337
R338
R339
R340
TEST6 A26 D24 H_DPWR# AB14 AF7 VCCSENSE
TEST6 DPWR# H_DPWR# 10 VCC[064] VCCSENSE VCCSENSE 48
D6 H_PW RGOOD AB15
CPU_MCH_BSEL0 B22 PWRGOOD H_CPUSLP# H_PWRGOOD 22 VCC[065]
6,10 CPU_MCH_BSEL0 BSEL[0] SLP# D7 H_CPUSLP# 10 AB17 VCC[066]
CPU_MCH_BSEL1 B23 AE6 H_PSI# AB18 AE7 VSSSENSE
H_PSI# 48 VSSSENSE 48
2
6,10 CPU_MCH_BSEL1 CPU_MCH_BSEL2 C21 BSEL[1] PSI# VCC[067] VSSSENSE
6,10 CPU_MCH_BSEL2 BSEL[2] TYCO_1-1674770-2_Merom~D
TYCO_1-1674770-2_Merom~D
Resistor placed within 0.5" of Length match within 25 mils Z0=27.4 ohm
CPU pin.Trace should be at least
B B
25 mils away from any other
TEST1 toggling signal. COMP0, COMP2 Place R342 and R343 near CPU
TEST2
TEST4
trace should be 27.4 ohm.
TEST6 PAD~D T30 TEST3 COMP1, COMP3 should be 55
0.1U_0402_16V4Z~D
TEST5
PAD~D T31 ohm. +VCC_CORE
0_0402_5%~D
1K_0402_5%~D
1K_0402_5%~D
2
2
@R335
2 For the purpose of testability, route these signals R342

@R336
C490
R394
1 2 VCCSENSE
through a ground referenced Z0 = 55ohm trace that
@ @ ends in a via that is near a GND via and is 100_0402_1%~D
1
accessible through an oscilloscope connection.
1
R343
1 2 VSSSENSE
100_0402_1%~D
Place C close to the FSB BCLK BSEL2 BSEL1 BSEL0

CPU_TEST4 pin. Make sure
CPU_TEST4 routing is Route VCCSENSE and VSSSENSE trace at
533 133 0 0 1 27.4 ohms, 7 mils spacing and 1 inch (max)
reference to GND and away
+1.05V_VCCP
from other noisy signal.
667 166 0 1 1
1
800 200 0 1 0 R341

V_CPU_GTLREF 1K_0402_1%~D
2
A A
1
R344
2K_0402_1%~D DELL CONFIDENTIAL/PROPRIETARY

2

Title
Layout close CPU PIN AD26 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Merom Processor(2/2)
55 ohm, 0.5 inch (max) NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1.0
5 4 3 2 1
5 4 3 2 1
+VCC_CORE
Place these inside 1 1 1 1 1 1 1 1 1 1

socket cavity on L8
(North side C329 C330 C331 C332 C333 C334 C335 C336 C55 C190
Secondary) 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
2 2 2 2 2 2 2 2 2 2
D D
+VCC_CORE
Place these inside 1 1 1 1 1 1 1 1 1 1

socket cavity on L8
(Sorth side C222 C223 C224 C225 C227 C226 C228 C229 C69 C185
Secondary) 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
2 2 2 2 2 2 2 2 2 2
+VCC_CORE
Place these inside 1 1 1 1 1 1

socket cavity on L8
(North side C363 C64 C65 C66 C67 C68
Primary) 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
2 2 2 2 2 2
+VCC_CORE
Place these inside 1 1 1 1 1 1 10uF 0805 X6S -> 85 degree C

socket cavity on L8
(Sorth side C364 C50 C51 C52 C53 C54
Primary) 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
C 2 2 2 2 2 2 C
High Frequence Decoupling
Near VCORE regulator.

+VCC_CORE
+VCC_CORE
1 1 1 1
220U_X_2VM_R7M~D
220U_X_2VM_R7M~D
220U_X_2VM_R7M~D
220U_X_2VM_R7M~D
220U_X_2VM_R7M~D
220U_X_2VM_R7M~D
C870 C871 C872 C873

South Side Secondary 1 1 1 1 1 1 North Side Secondary 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D
2 @ 2 @ 2 @ 2 @
ESR <= 1.5m ohm
C177
C179
@ C178
C366
@ C338
C365
+ + + + + +
2 2 2 2 2 2 Capacitor > 1980uF

BITs WI97840
B B
+1.05V_VCCP
1 1 1 1 1 1
Place these inside
C312 C256 C293 C250 C310 C264 socket cavity on L8
0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D (North side
2 2 2 2 2 2 Secondary)
om
A A
l.c
ai
tm
ho
f@
CPU Bypass
in
xa
LA-3301P
he
5 4 3 2 1
5 4 3 2 1
U29B
RSVD1 P36
M_CLK_DDR0 AV29 P37
16 M_CLK_DDR0 SM_CK_0 RSVD2
M_CLK_DDR1 BB23 R35
M_CLK_DDR2 BA25 N35
M_CLK_DDR3 AV23 AR12
RSVD6 AR13
M_CLK_DDR#0 AW30 AM12
16 M_CLK_DDR#0 SM_CK#_0 RSVD7
M_CLK_DDR#1 BA23 AN13
M_CLK_DDR#2 AW25 J12
M_CLK_DDR#3 AW23 AR37
D 8 H_D#[0..63] H_A#[3..35] 7 17 M_CLK_DDR#3 SM_CK#_4 RSVD10 D
U29A AM36
RSVD11
MUXING
H_D#0 E2 J13 H_A#3 DDR_CKE0_DIMMA BE29 AL36
H_D#_0 H_A#_3 16 DDR_CKE0_DIMMA SM_CKE_0 RSVD12
H_D#1 G2 B11 H_A#4 DDR_CKE1_DIMMA AY32 AM37
H_D#_1 H_A#_4 16 DDR_CKE1_DIMMA SM_CKE_1 RSVD13
H_D#2 G7 C11 H_A#5 DDR_CKE2_DIMMB BD39 D20
H_D#_2 H_A#_5 17 DDR_CKE2_DIMMB SM_CKE_3 RSVD14
H_D#3 M6 M11 H_A#6 DDR_CKE3_DIMMB BG37
H_D#_3 H_A#_6 17 DDR_CKE3_DIMMB SM_CKE_4
H_D#4 H7 C15 H_A#7
H_D#5 H_D#_4 H_A#_7 H_A#8 DDR_CS0_DIMMA#
H3 H_D#_5 H_A#_8 F16 16 DDR_CS0_DIMMA# BG20 SM_CS#_0
H_D#6 G4 L13 H_A#9 DDR_CS1_DIMMA# BK16
H_D#_6 H_A#_9 16 DDR_CS1_DIMMA# SM_CS#_1
H_D#7 F3 G17 H_A#10 DDR_CS2_DIMMB# BG16
H_D#_7 H_A#_10 17 DDR_CS2_DIMMB# SM_CS#_2
H_D#8 N8 C14 H_A#11 DDR_CS3_DIMMB# BE13 H10
H_D#_8 H_A#_11 17 DDR_CS3_DIMMB# SM_CS#_3 RSVD20
DDR RSVD
H_D#9 H2 K16 H_A#12 B51
H_D#10 H_D#_9 H_A#_12 H_A#13 M_ODT0 RSVD21
M10 H_D#_10 H_A#_13 B13 16 M_ODT0 BH18 SM_ODT_0 RSVD22 BJ20
H_D#11 N12 L16 H_A#14 M_ODT1 BJ15 BK22
H_D#_11 H_A#_14 16 M_ODT1 SM_ODT_1 RSVD23
H_D#12 N9 J17 H_A#15 M_ODT2 BJ14 BF19
H_D#_12 H_A#_15 +1.8V_SUS 17 M_ODT2 SM_ODT_2 RSVD24
H_D#13 H5 B14 H_A#16 R345 M_ODT3 BE16 BH20
H_D#_13 H_A#_16 17 M_ODT3 SM_ODT_3 RSVD25
H_D#14 P13 K19 H_A#17 20_0402_1%~D BK18
H_D#15 H_D#_14 H_A#_17 H_A#18 SMRCOMP RSVD26
K9 H_D#_15 H_A#_18 P15 1 2 BL15 SM_RCOMP RSVD27 BJ18
H_D#16 M2 R17 H_A#19 1 2 SMRCOMP# BK14 BF23
H_D#17 H_D#_16 H_A#_19 H_A#20 SM_RCOMP# RSVD28
W10 H_D#_17 H_A#_20 B16 RSVD29 BG23
H_D#18 Y8 H20 H_A#21 R346 SMRCOMP_VOH BK31 BC23
H_D#19 H_D#_18 H_A#_21 H_A#22 20_0402_1%~D SMRCOMP_VOL SM_RCOMP_VOH RSVD30
V4 H_D#_19 H_A#_22 L19 BL31 SM_RCOMP_VOL RSVD31 BD24
H_D#20 M3 D17 H_A#23 BH39
H_D#21 H_D#_20 H_A#_23 H_A#24 RSVD32
J1 H_D#_21 H_A#_24 M17 AR49 SM_VREF_0 RSVD33 AW20
H_D#22 N5 N16 H_A#25 V_DDR_MCH_REF V_DDR_MCH_REF AW4 BK20
H_D#23 H_D#_22 H_A#_25 H_A#26 SM_VREF_1 RSVD34
N3 H_D#_23 H_A#_26 J19 RSVD35 C48
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
H_D#24 W6 B18 H_A#27 D47
H_D#25 H_D#_24 H_A#_27 H_A#28 RSVD36
W9 H_D#_25 H_A#_28 E19 1 1 RSVD37 B44
H_D#26 N2 B17 H_A#29 6 MCH_DREFCLK MCH_DREFCLK B42 C44
H_D#_26 H_A#_29 DPLL_REF_CLK RSVD38
C491
C492
H_D#27 Y7 B15 H_A#30 6 MCH_DREFCLK# MCH_DREFCLK# C42 A35
H_D#28 H_D#_27 H_A#_30 H_A#31 DREF_SSCLK DPLL_REF_CLK# RSVD39
Y9 H_D#_28 H_A#_31 E17 6 DREF_SSCLK H48 DPLL_REF_SSCLK RSVD40 B37
2 2
CLK
H_D#29 P4 C18 H_A#32 DREF_SSCLK# H47 B36
H_D#_29 H_A#_32 6 DREF_SSCLK# DPLL_REF_SSCLK# RSVD41
H_D#30 W3 A19 H_A#33 B34
C H_D#31 H_D#_30 H_A#_33 H_A#34 CLK_MCH_3GPLL RSVD42 C
N1 H_D#_31 H_A#_34 B19 6 CLK_MCH_3GPLL K44 PEG_CLK RSVD43 C34
H_D#32 AD12 N19 H_A#35 6 CLK_MCH_3GPLL# CLK_MCH_3GPLL# K45
H_D#33 H_D#_32 H_A#_35 PEG_CLK#
AE3 H_D#_33
H_D#34 AD9 G12 H_ADS# H_ADS# 7
H_D#35 H_D#_34 H_ADS# H_ADSTB#0
AC9 H_D#_35 H_ADSTB#_0 H17 H_ADSTB#0 7
HOST
H_D#36 AC7 G20 H_ADSTB#1 DMI_MRX_ITX_N0 AN47

H_D#_36 H_ADSTB#_1 H_ADSTB#1 7 23 DMI_MRX_ITX_N0 DMI_RXN_0
H_D#37 AC14 C8 H_BNR# H_BNR# 7 DMI_MRX_ITX_N1 AJ38
H_D#_37 H_BNR# 23 DMI_MRX_ITX_N1 DMI_RXN_1
H_D#38 AD11 E8 H_BPRI# H_BPRI# 7 DMI_MRX_ITX_N2 AN42
H_D#_38 H_BPRI# 23 DMI_MRX_ITX_N2 DMI_RXN_2
H_D#39 AC11 F12 H_BR0# DMI_MRX_ITX_N3 AN46
H_D#_39 H_BREQ# H_BR0# 7 23 DMI_MRX_ITX_N3 DMI_RXN_3
H_D#40 AB2 D6 H_DEFER# H_DEFER# 7
H_D#41 H_D#_40 H_DEFER# H_DBSY# DMI_MRX_ITX_P0
AD7 H_D#_41 H_DBSY# C10 H_DBSY# 7 23 DMI_MRX_ITX_P0 AM47 DMI_RXP_0
H_D#42 AB1 AM5 CLK_MCH_BCLK DMI_MRX_ITX_P1 AJ39 P27 CPU_MCH_BSEL0 6,8
H_D#_42 HPLL_CLK CLK_MCH_BCLK 6 23 DMI_MRX_ITX_P1 DMI_RXP_1 CFG_0
H_D#43 Y3 AM7 CLK_MCH_BCLK# CLK_MCH_BCLK# 6 DMI_MRX_ITX_P2 AN41 N27 CPU_MCH_BSEL1 6,8
H_D#_43 HPLL_CLK# 23 DMI_MRX_ITX_P2 DMI_RXP_2 CFG_1
H_D#44 AC6 H8 H_DPWR# H_DPWR# 8 DMI_MRX_ITX_P3 AN45 N24 CPU_MCH_BSEL2 6,8
H_D#_44 H_DPWR# 23 DMI_MRX_ITX_P3 DMI_RXP_3 CFG_2
DMI
H_D#45 AE2 K7 H_DRD Y# C21 T63 PAD~D
H_D#_45 H_DRDY# H_DRDY# 7 CFG_3
H_D#46 AC5 E4 H_HIT# H_HIT# 7 DMI_MTX_IRX_N0 AJ46 C23 T64 PAD~D
H_D#_46 H_HIT# 23 DMI_MTX_IRX_N0 DMI_TXN_0 CFG_4
H_D#47 AG3 C6 H_HITM# H_HITM# 7 DMI_MTX_IRX_N1 AJ41 F23 CFG5 CFG5 12
H_D#_47 H_HITM# 23 DMI_MTX_IRX_N1 DMI_TXN_1 CFG_5
H_D#48 AJ9 G10 H_LOCK# H_LOCK# 7 DMI_MTX_IRX_N2 AM40 N23 T65 PAD~D
H_D#_48 H_LOCK# 23 DMI_MTX_IRX_N2 DMI_TXN_2 CFG_6
H_D#49 AH8 B7 H_TRDY# H_TRDY# 7 DMI_MTX_IRX_N3 AM44 G23 T66 PAD~D
H_D#_49 H_TRDY# 23 DMI_MTX_IRX_N3 DMI_TXN_3 CFG_7
H_D#50 AJ14 J20 T67 PAD~D
H_D#51 H_D#_50 DMI_MTX_IRX_P0 CFG_8 CFG9
AE9 H_D#_51 23 DMI_MTX_IRX_P0 AJ47 DMI_TXP_0 CFG_9 C20 CFG9 12
CFG
H_D#52 AE11 DMI_MTX_IRX_P1 AJ42 R24 T68 PAD~D
H_D#_52 23 DMI_MTX_IRX_P1 DMI_TXP_1 CFG_10
H_D#53 AH12 K5 H_DINV#0 DMI_MTX_IRX_P2 AM39 L23 T69 PAD~D
+1.05V_VCCP H_D#_53 H_DINV#_0 H_DINV#0 8 23 DMI_MTX_IRX_P2 DMI_TXP_2 CFG_11
H_D#54 AJ5 L2 H_DINV#1 DMI_MTX_IRX_P3 AM43 J23 T70 PAD~D
H_D#_54 H_DINV#_1 H_DINV#1 8 23 DMI_MTX_IRX_P3 DMI_TXP_3 CFG_12
H_D#55 AH5 AD13 H_DINV#2 E23 T71 PAD~D
H_D#_55 H_DINV#_2 H_DINV#2 8 CFG_13
H_D#56 AJ6 AE13 H_DINV#3 E20 T72 PAD~D
H_D#_56 H_DINV#_3 H_DINV#3 8 CFG_14
H_D#57 AE7 K23 T73 PAD~D
H_D#58 H_D#_57 H_DSTBN#0 CFG_15 CFG16
AJ7 H_D#_58 H_DSTBN#_0 M7 H_DSTBN#0 8 CFG_16 M20 CFG16 12
H_D#59 AJ2 K3 H_DSTBN#1 H_DSTBN#1 8 M24
GRAPHICS VID
H_D#_59 H_DSTBN#_1 CFG_17 T74 PAD~D
54.9_0402_1%~D
H_D#60 AE5 AD2 H_DSTBN#2 H_DSTBN#2 8 L32 T75 PAD~D

H_D#_60 H_DSTBN#_2 CFG_18
1
H_D#61 AJ3 AH11 H_DSTBN#3 H_DSTBN#3 8 N33 CFG19 CFG19 12

H_D#_61 H_DSTBN#_3 CFG_19
R347
R348 H_D#62 AH2 PAD~D T42 E35 L35 CFG20 CFG20 12

B H_D#63 H_D#_62 H_DSTBP#0 GFX_VID_0 CFG_20 B
AH13 H_D#_63 H_DSTBP#_0 L7 H_DSTBP#0 8 PAD~D T43 A39 GFX_VID_1
54.9_0402_1%~D K2 H_DSTBP#1 H_DSTBP#1 8 PAD~D T44 C38
H_DSTBP#_1 H_DSTBP#2 GFX_VID_2
AC2 H_DSTBP#2 8 PAD~D T45 B39
2
H_SWNG H_DSTBP#_2 H_DSTBP#3 GFX_VID_3 PM_BMBUSY#

B3 H_SWING H_DSTBP#_3 AJ10 H_DSTBP#3 8 PM_BM_BUSY# G41 PM_BMBUSY# 23
H_RCOMP C2 PAD~D T46 E36 L39 H_DPRSTP# H_DPRSTP# 8,22,48
H_RCOMP H_REQ#0 GFX_VR_EN PM_DPRSTP# PM_EXTTS#0
H_REQ#_0 M14 H_REQ#0 7 PM_EXT_TS#_0 L36 PM_EXTTS#0 16
PM
H_SCOMP W1 E13 H_REQ#1 J36 PM_EXTTS#1 PM_EXTTS#1 17
H_SCOMP H_REQ#_1 H_REQ#1 7 PM_EXT_TS#_1
H_SCOMP# W2 A11 H_REQ#2 AW49 ICH_PWRGD
H_SCOMP# H_REQ#_2 H_REQ#2 7 +1.25V_RUN PWROK ICH_PWRGD 23,42
H13 H_REQ#3 AV20 PLTRST1#_R
H_REQ#_3 H_REQ#3 7 RSTIN#
7 H_RESET# H_RESET# B6 B12 H_REQ#4 N20 THERMTRIP_MCH# THERMTRIP_MCH# 18
H_CPURST# H_REQ#_4 H_REQ#4 7 THERMTRIP#
H_CPUSLP# E5 G36 DPRSLPVR DPRSLPVR 23,48
8 H_CPUSLP# H_CPUSLP# DPRSLPVR
1
E12 H_RS#0
H_RS#_0 H_RS#0 7
1
D7 H_RS#1 CL_CLK0 AM49

H_RS#_1 H_RS#1 7 23 CL_CLK0 CL_CLK
R350 B9 D8 H_RS#2 R349 CL_DATA0 AK50 +3.3V_RUN
H_AVREF H_RS#_2 H_RS#2 7 23 CL_DATA0 CL_DATA
H_VREF A9 1K_0402_1%~D ICH_CL_PWROK AT43 BJ51 R352
ME
H_DVREF 23,39 ICH_CL_PWROK CL_PWROK NC_1
24.9_0402_1%~D ICH_CL_RST0# AN49 BK51 10K_0402_5%~D
23 ICH_CL_RST0#
2
CL_VREF CL_RST# NC_2 PM_EXTTS#0

AM50 BK50 2 1
2
LE88CLGM A0 QM20_FCBGA1299~D CL_VREF NC_3

NC_4 BL50
1
+1.8V_SUS BL49 R354

1 NC_5
C493 BL3 10K_0402_5%~D
R351 0.1U_0402_16V4Z~D NC_6 PM_EXTTS#1
NC_7 BL2 2 1
1
NC
392_0402_1~D BK1
R353 2 SDVO_CTRLCLK NC_8
51 SDVO_CTRLCLK H35 BJ1
2
1K_0402_1%~D SDVO_CTRLDATA SDVO_CTRL_CLK NC_9

51 SDVO_CTRLDATA K36 SDVO_CTRL_DATA NC_10 E1
+1.05V_VCCP +1.05V_VCCP CLK_3GPLLREQ# G39 A5
MISC
6 CLK_3GPLLREQ# CLK_REQ# NC_11
Layout Note: 23 MCH_ICH_SYNC# MCH_ICH_SYNC# G40 C51
2
SMRCOMP_VOH ICH_SYNC# NC_12

NC_13 B50
H_RCOMP trace width
0.01U_0402_16V7K~D
2.2U_0603_6.3V6K~D
R774 0_0402_5%~D A50 R589

NC_14
1
2 1 A37 A49 @ 0_0402_5%~D

and spacing is 10/20 R355 R356
1 1 TEST_1 NC_15
2 1 R32 TEST_2 NC_16 BK2 2 1 SB_NB_PCIE_RST# 21
1
C494
C495
1K_0402_1%~D 221_0402_1%~D R357 R36 R583

A R359 2 2 20K_0402_5%~D LE88CLGM A0 QM20_FCBGA1299~D 100_0402_5%~D 0_0402_5%~D A
2
3.01K_0402_1%~D PLTRST1#_R 1 2 2 1PLTRST1# PLTRST1# 21,51

H_VREF H_SWNG
2
R358
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
THERMTRIP_MCH# 1 2 +1.05V_VCCP
1
1
100_0402_1%~D
1 1 SMRCOMP_VOL
R362
0.01U_0402_16V7K~D
2.2U_0603_6.3V6K~D
R361 56_0402_5%~D
1
C496
C497
2K_0402_1%~D R363
1 1 Compal Electronics, Inc.
2 2
C498
C499
1K_0402_1%~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
2
2 2 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Crestline(1 of 6)
2
LA-3301P
5 4 3 2 1
5 4 3 2 1
D D
DDR_A_D[0..63] 16 DDR_B_D[0..63] 17
U29D U29E
DDR_A_BS0 BB19 AR43 DDR_A_D0 DDR_B_BS0 AY17 AP49 DDR_B_D0
16 DDR_A_BS0 SA_BS_0 SA_DQ_0 17 DDR_B_BS0 SB_BS_0 SB_DQ_0
DDR_A_BS1 BK19 AW44 DDR_A_D1 DDR_B_BS1 BG18 AR51 DDR_B_D1
DDR_A_BS2 BF29 BA45 DDR_A_D2 DDR_B_BS2 BG36 AW50 DDR_B_D2
AY46 DDR_A_D3 AW51 DDR_B_D3
16 DDR_A_DM[0..7] SA_DQ_3 17 DDR_B_DM[0..7] SB_DQ_3
AR41 DDR_A_D4 AN51 DDR_B_D4
DDR_A_DM0 SA_DQ_4 DDR_A_D5 DDR_B_DM0 SB_DQ_4 DDR_B_D5
AT45 SA_DM_0 SA_DQ_5 AR45 AR50 SB_DM_0 SB_DQ_5 AN50
DDR_A_DM1 BD44 AT42 DDR_A_D6 DDR_B_DM1 BD49 AV50 DDR_B_D6
DDR_A_DM2 SA_DM_1 SA_DQ_6 DDR_A_D7 DDR_B_DM2 SB_DM_1 SB_DQ_6 DDR_B_D7
BD42 SA_DM_2 SA_DQ_7 AW47 BK45 SB_DM_2 SB_DQ_7 AV49
DDR_A_DM3 AW38 BB45 DDR_A_D8 DDR_B_DM3 BL39 BA50 DDR_B_D8
AW13 SA_DM_4 SA_DQ_9 BF48 BH12 SB_DM_4 SB_DQ_9 BB50
DDR_A_DM5 BG8 BG47 DDR_A_D10 DDR_B_DM5 BJ7 BA49 DDR_B_D10
AY5 SA_DM_6 SA_DQ_11 BJ45 BF3 SB_DM_6 SB_DQ_11 BE50
DDR_A_DM7 AN6 BB47 DDR_A_D12 DDR_B_DM7 AW2 BA51 DDR_B_D12
SA_DM_7 SA_DQ_12 DDR_A_D13 SB_DM_7 SB_DQ_12 DDR_B_D13
16 DDR_A_DQS[0..7] SA_DQ_13 BG50 17 DDR_B_DQS[0..7] SB_DQ_13 AY49
BH49 DDR_A_D14 BF50 DDR_B_D14
DDR_A_DQS0 SA_DQ_14 DDR_A_D15 DDR_B_DQS0 SB_DQ_14 DDR_B_D15
AT46 SA_DQS_0 SA_DQ_15 BE45 AT50 SB_DQS_0 SB_DQ_15 BF49
DDR_A_DQS1 BE48 AW43 DDR_A_D16 DDR_B_DQS1 BD50 BJ50 DDR_B_D16
DDR_A_DQS2 SA_DQS_1 SA_DQ_16 DDR_A_D17 DDR_B_DQS2 SB_DQS_1 SB_DQ_16 DDR_B_D17
BB43 BE44 BK46 BJ44
B
SA_DQS_2 SA_DQ_17 SB_DQS_2 SB_DQ_17
A
DDR_A_DQS3 BC37 BG42 DDR_A_D18 DDR_B_DQS3 BK39 BJ43 DDR_B_D18
DDR_A_DQS4 SA_DQS_3 SA_DQ_18 DDR_A_D19 DDR_B_DQS4 SB_DQS_3 SB_DQ_18 DDR_B_D19
BB16 SA_DQS_4 SA_DQ_19 BE40 BJ12 SB_DQS_4 SB_DQ_19 BL43
DDR_A_DQS5 BH6 BF44 DDR_A_D20 DDR_B_DQS5 BL7 BK47 DDR_B_D20
C DDR_A_DQS6 SA_DQS_5 SA_DQ_20 DDR_A_D21 DDR_B_DQS6 SB_DQS_5 SB_DQ_20 DDR_B_D21 C
BB2 SA_DQS_6 SA_DQ_21 BH45 BE2 SB_DQS_6 SB_DQ_21 BK49
MEMORY
DDR_A_DQS7 DDR_A_D22 DDR_B_DQS7 DDR_B_D22
MEMORY
AP3 SA_DQS_7 SA_DQ_22 BG40 AV2 SB_DQS_7 SB_DQ_22 BK43
BF40 DDR_A_D23 BK42 DDR_B_D23
16 DDR_A_DQS#[0..7] SA_DQ_23 17 DDR_B_DQS#[0..7] SB_DQ_23
AR40 DDR_A_D24 BJ41 DDR_B_D24
DDR_A_DQS#0 SA_DQ_24 DDR_A_D25 DDR_B_DQS#0 SB_DQ_24 DDR_B_D25
AT47 SA_DQS#_0 SA_DQ_25 AW40 AU50 SB_DQS#_0 SB_DQ_25 BL41
DDR_A_DQS#1 BD47 AT39 DDR_A_D26 DDR_B_DQS#1 BC50 BJ37 DDR_B_D26
DDR_A_DQS#2 SA_DQS#_1 SA_DQ_26 DDR_A_D27 DDR_B_DQS#2 SB_DQS#_1 SB_DQ_26 DDR_B_D27
BC41 SA_DQS#_2 SA_DQ_27 AW36 BL45 SB_DQS#_2 SB_DQ_27 BJ36
DDR_A_DQS#3 BA37 AW41 DDR_A_D28 DDR_B_DQS#3 BK38 BK41 DDR_B_D28
BA16 SA_DQS#_4 SA_DQ_29 AY41 BK12 SB_DQS#_4 SB_DQ_29 BJ40
DDR_A_DQS#5 BH7 AV38 DDR_A_D30 DDR_B_DQS#5 BK7 BL35 DDR_B_D30
BC1 SA_DQS#_6 SA_DQ_31 AT38 BF2 SB_DQS#_6 SB_DQ_31 BK37
SYSTEM
SYSTEM
DDR_A_DQS#7 AP2 AV13 DDR_A_D32 DDR_B_DQS#7 AV3 BK13 DDR_B_D32

SA_DQS#_7 SA_DQ_32 DDR_A_D33 SB_DQS#_7 SB_DQ_32 DDR_B_D33
16 DDR_A_MA[0..14] SA_DQ_33 AT13 17 DDR_B_MA[0..14] SB_DQ_33 BE11
AW11 DDR_A_D34 BK11 DDR_B_D34
DDR_A_MA0 SA_DQ_34 DDR_A_D35 DDR_B_MA0 SB_DQ_34 DDR_B_D35
BJ19 SA_MA_0 SA_DQ_35 AV11 BC18 SB_MA_0 SB_DQ_35 BC11
DDR_A_MA1 BD20 AU15 DDR_A_D36 DDR_B_MA1 BG28 BC13 DDR_B_D36
DDR_A_MA2 SA_MA_1 SA_DQ_36 DDR_A_D37 DDR_B_MA2 SB_MA_1 SB_DQ_36 DDR_B_D37
BK27 SA_MA_2 SA_DQ_37 AT11 BG25 SB_MA_2 SB_DQ_37 BE12
DDR_A_MA3 BH28 BA13 DDR_A_D38 DDR_B_MA3 AW17 BC12 DDR_B_D38
BL24 SA_MA_4 SA_DQ_39 BA11 BF25 SB_MA_4 SB_DQ_39 BG12
DDR_A_MA5 BK28 BE10 DDR_A_D40 DDR_B_MA5 BE25 BJ10 DDR_B_D40
BJ27 BD10 BA29 BL9
DDR
SA_MA_6 SA_DQ_41 SB_MA_6 SB_DQ_41
DDR
DDR_A_MA7 BJ25 BD8 DDR_A_D42 DDR_B_MA7 BC28 BK5 DDR_B_D42

BL28 SA_MA_8 SA_DQ_43 AY9 AY28 SB_MA_8 SB_DQ_43 BL5
DDR_A_MA9 BA28 BG10 DDR_A_D44 DDR_B_MA9 BD37 BK9 DDR_B_D44
BC19 SA_MA_10 SA_DQ_45 AW9 BG17 SB_MA_10 SB_DQ_45 BK10
DDR_A_MA11 BE28 BD7 DDR_A_D46 DDR_B_MA11 BE37 BJ8 DDR_B_D46
BG30 SA_MA_12 SA_DQ_47 BB9 BA39 SB_MA_12 SB_DQ_47 BJ6
DDR_A_MA13 BJ16 BB5 DDR_A_D48 DDR_B_MA13 BG13 BF4 DDR_B_D48
BJ29 SA_MA_14 SA_DQ_49 AY7 BE24 SB_MA_14 SB_DQ_49 BH5
AT5 DDR_A_D50 BG1 DDR_B_D50
SA_DQ_50 DDR_A_D51 SB_DQ_50 DDR_B_D51
SA_DQ_51 AT7 SB_DQ_51 BC2
DDR_A_CAS# BL17 AY6 DDR_A_D52 DDR_B_CAS# BE17 BK3 DDR_B_D52
B 16 DDR_A_CAS# SA_CAS# SA_DQ_52 17 DDR_B_CAS# SB_CAS# SB_DQ_52 B
DDR_A_RAS# BE18 BB7 DDR_A_D53 DDR_B_RAS# AV16 BE4 DDR_B_D53
16 DDR_A_RAS# SA_RAS# SA_DQ_53 17 DDR_B_RAS# SB_RAS# SB_DQ_53
DDR_A_WE# BA19 AR5 DDR_A_D54 DDR_B_WE# BC17 BD3 DDR_B_D54
16 DDR_A_WE# SA_WE# SA_DQ_54 17 DDR_B_WE# SB_WE# SB_DQ_54
AR8 DDR_A_D55 BJ2 DDR_B_D55
SA_DQ_56 AR9 SB_DQ_56 BA3
AN3 DDR_A_D57 BB3 DDR_B_D57
SA_RCVEN# SA_DQ_57 DDR_A_D58 SB_RCVEN# SB_DQ_57 DDR_B_D58
AY20 SA_RCVEN# SA_DQ_58 AM8 AY18 SB_RCVEN# SB_DQ_58 AR1
T10 DDR_A_D59 T11 DDR_B_D59
SA_DQ_59 AN10 SB_DQ_59 AT3
AT9 DDR_A_D60 AY2 DDR_B_D60
SA_DQ_61 AN9 SB_DQ_61 AY3
AM9 DDR_A_D62 AU2 DDR_B_D62
SA_DQ_63 AN11 SB_DQ_63 AT2
LE88CLGM A0 QM20_FCBGA1299~D LE88CLGM A0 QM20_FCBGA1299~D
om
A A
l.c
ai
tm
ho
f@
Crestline(2 of 6)
in
xa
LA-3301P
he
5 4 3 2 1
5 4 3 2 1
U29C
Strap Pin Table
R366
BIA_PWM J40 24.9_0402_1%~D Low = DMI x 2
19 BIA_PWM L_BKLT_CTRL
PANEL_BKEN H39 N43 PEGCOMP 1 2 +VCC_PEG CFG5 DMI X2 Select
38 PANEL_BKEN L_BKLT_EN PEG_COMPI
D
E39 L_CTRL_CLK PEG_COMPO M43 High = DMI x 4 (Default) D
E40 L_CTRL_DATA
LCD_DDCCLK C37
19 LCD_DDCCLK L_DDC_CLK
LCD_DDCDATA D35 J51 CFG9 PCI Express Low = Reverse Lane
19 LCD_DDCDATA L_DDC_DATA PEG_RX#_0
ENVDD K40 L51
19 ENVDD L_VDD_EN PEG_RX#_1
N47
SDVOB_INT- 51 Graphic Lane High = Normal Operation (Default)
L_IBG PEG_RX#_2
1 2 L41 LVDS_IBG PEG_RX#_3 T45
R369 L43 T50
3.3K_0402_1%~D LVDS_VBG PEG_RX#_4
N41 LVDS_VREFH PEG_RX#_5 U40 CFG16 FSB Dynamic Low=Dynamic ODT Disable
N40 Y44
LVDS_VREFL PEG_RX#_6 ODT
R369 = 2.4k ohm value is PEG_RX#_7 Y40 High=Dynamic ODT Enable(default)
LCD_ACLK-_C D46 AB51
recommended per Intel LCD_ACLK+_C LVDSA_CLK# PEG_RX#_8
C45 LVDSA_CLK PEG_RX#_9 W49
LCD_BCLK-_C D44 AD44 CFG19 DMI Lane Low=Normal (default)
LVDSB_CLK# PEG_RX#_10
LVDS
LCD_BCLK+_C E42 AD40 R365 1 2 @ 4.02K_0402_1%~D
LVDSB_CLK PEG_RX#_11
AG46
Reversal High=Lane Reversed
10 CFG5
PEG_RX#_12
19 LCD_A0- G51 LVDSA_DATA#_0 PEG_RX#_13 AH49
19 LCD_A1- E51 LVDSA_DATA#_1 PEG_RX#_14 AG45
19 LCD_A2- F49 AG41 SDVO/PCIE Low=Only SDVO or PCIEx1 is 10 CFG9
R368 1 2 @ 4.02K_0402_1%~D
LVDSA_DATA#_2 PEG_RX#_15
CFG20 Concurrent operational (defaults)
PEG_RX_0 J50
G50 L50 Operation
GRAPHICS
19 LCD_A0+ LVDSA_DATA_0 PEG_RX_1 SDVOB_INT+ 51 High=SDVO and PCIEx1 are operating R372 1
19 LCD_A1+ E50 LVDSA_DATA_1 PEG_RX_2 M47 10 CFG16 2 @ 4.02K_0402_1%~D
19 LCD_A2+ F48 U44 simultaneously via PEG port
LVDSA_DATA_2 PEG_RX_3
PEG_RX_4 T49
PEG_RX_5 T41
19 LCD_B0- G44 LVDSB_DATA#_0 PEG_RX_6 W45 Low=No SDVO Device Present CFG[3:17] have internal pullup
19 LCD_B1- B47 LVDSB_DATA#_1 PEG_RX_7 W41
19 LCD_B2- B45 LVDSB_DATA#_2 PEG_RX_8 AB50 SDVO_CRTL_DATA
PEG_RX_9 Y48
PEG_RX_10 AC45 High=SDVO Device Present (default)
19 LCD_B0+ E44 LVDSB_DATA_0 PEG_RX_11 AC41
19 LCD_B1+ A47 LVDSB_DATA_1 PEG_RX_12 AH47
C C
A45 AG49
PCI-EXPRESS
19 LCD_B2+ LVDSB_DATA_2 PEG_RX_13 +3.3V_RUN
PEG_RX_14 AH45
PEG_RX_15 AG42
N45 SDVOB_RED-_C C500 1 2 0.1U_0402_10V7K~D

PEG_TX#_0 SDVOB_RED- 51
U39 SDVOB_GREEN-_C C501 1 2 0.1U_0402_10V7K~D
PEG_TX#_1 SDVOB_GREEN- 51
TV_CVBS E27 U47 SDVOB_BLUE-_C C502 1 2 0.1U_0402_10V7K~D
36 TV_CVBS TVA_DAC PEG_TX#_2 SDVOB_BLUE- 51
TV_Y G27 N51 SDVOB_CLK-_C C503 1 2 0.1U_0402_10V7K~D R373 1 2 @ 4.02K_0402_1%~D
36 TV_Y TVB_DAC PEG_TX#_3 SDVOB_CLK- 51 10 CFG19
TV_C K27 R50
36 TV_C TVC_DAC PEG_TX#_4
150_0402_1%~D
150_0402_1%~D
150_0402_1%~D
PEG_TX#_5 T42
1
TV
F27 Y43 R374 1 2 @4.02K_0402_1%~D

TVA_RTN PEG_TX#_6 10 CFG20
J27 TVB_RTN PEG_TX#_7 W46
R375
R376
R377
L27 TVC_RTN PEG_TX#_8 W38

PEG_TX#_9 AD39 CFG[18:19] have internal pulldown
M35 AC46
2
TV_DCONSEL_0 PEG_TX#_10
P33 TV_DCONSEL_1 PEG_TX#_11 AC49
PEG_TX#_12 AC42
PEG_TX#_13 AH39
PEG_TX#_14 AE49
PEG_TX#_15 AH44
H32 M45 SDVOB_RED+_C C504 1 2 0.1U_0402_10V7K~D

20,36 CRT_BLU CRT_BLUE PEG_TX_0 SDVOB_RED+ 51
G32 T38 SDVOB_GREEN+_C C505 1 2 0.1U_0402_10V7K~D
CRT_BLUE# PEG_TX_1 SDVOB_GREEN+ 51
K29 T46 SDVOB_BLUE+_C C506 1 2 0.1U_0402_10V7K~D
20,36 CRT_GRN CRT_GREEN PEG_TX_2 SDVOB_BLUE+ 51
J29 N50 SDVOB_CLK+_C C507 1 2 0.1U_0402_10V7K~D
CRT_GREEN# PEG_TX_3 SDVOB_CLK+ 51
VGA
20,36 CRT_RED F29 CRT_RED PEG_TX_4 R51

E29 CRT_RED# PEG_TX_5 U43
PEG_TX_6 W42
PEG_TX_7 Y47
G_CLK_DDC2 K33 Y39
G_DAT_DDC2 CRT_DDC_CLK PEG_TX_8
G35 CRT_DDC_DATA PEG_TX_9 AC38
150_0402_1%~D
150_0402_1%~D
150_0402_1%~D
CRT_HSYNC F33 AD47

20 CRT_HSYNC CRT_HSYNC PEG_TX_10
2
2
R378
R379
R380
B CRT_VSYNC B
20 CRT_VSYNC E33 CRT_VSYNC PEG_TX_11 AC50
PEG_TX_12 AD43
2 1 CRT_IREF C32 AG39
R382 1.3K_0402_1%~D CRT_TVO_IREF PEG_TX_13
PEG_TX_14 AE50
AH43
1
PEG_TX_15
+3.3V_RUN
Trace CRT_IREF should be at LE88CLGM A0 QM20_FCBGA1299~D
least 20 miles away from any NO CONNECT FOR DISCRETE
other toggling signal. R686
1
0_0402_5%~D
LCD_ACLK-_C 1 2 R383 R384
LCD_ACLK- 19
1
1 2.2K_0402_5%~D 2.2K_0402_5%~D
@ C39 @ R667
2
3.3P_0402_50V8C~D 0_0402_5%~D Q36
D
G_CLK_DDC2 3 1 CLK_DDC2
2 CLK_DDC2 20,36
LCD_A0+ 1 2 LCD_A0-
2
@ C181 3.3P_0402_50V8C~D LCD_ACLK+_C 1 2 BSS138_SOT23~D

LCD_ACLK+ 19
LCD_A1+ LCD_A1-
G
1 2
2
@ C192 3.3P_0402_50V8C~D R685 +3.3V_RUN
LCD_A2+ 1 2 LCD_A2- 0_0402_5%~D
2
G
@ C193 3.3P_0402_50V8C~D
LCD_B0+ 1 2 LCD_B0- Q37
@ C196 3.3P_0402_50V8C~D R689 G_DAT_DDC2 3 1 DAT_DDC2 DAT_DDC2 20,36
LCD_B1+ LCD_B1- 0_0402_5%~D
D
1 2
@ C207 3.3P_0402_50V8C~D LCD_BCLK-_C 1 2 BSS138_SOT23~D
LCD_BCLK- 19
LCD_B2+ 1 2 LCD_B2-
1
+3.3V_RUN @ C209 3.3P_0402_50V8C~D 1

@ C43 @ R687
3.3P_0402_50V8C~D 0_0402_5%~D
A LCD_DDCCLK A
1 2
R41 2.2K_0402_5%~D 2
Keep stub for
2
LCD_BCLK+_C 1 2
1 2 LCD_DDCDATA caps as small LCD_BCLK+ 19
R110 2.2K_0402_5%~D as possible R688
0_0402_5%~D DELL CONFIDENTIAL/PROPRIETARY
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Crestline(3 of 6)
LA-3301P
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
1
+1.05V_VCCP U29H
C532 +3.3V_RUN_DAC_BG +3.3V_RUN
CRB 270uF J32 0.1U_0402_16V4Z~D L29
VCCSYNC 2 +3.3V_RUN_TVDACA +3.3V_RUN_TVDAC +3.3V_RUN
0.47U_0402_10V4Z~D
U13 BLM18PG181SN1_0603~D
VTT_1 +3.3V_RUN
220U_D2_4VY_R15M~D
1 U12 VTT_2 VCCA_CRT_DAC_1 A33 1 2 2 1

1 U11 B33 L31 1 2 2 1
VTT_3 VCCA_CRT_DAC_2
22n_0805_25V
C535
+ U9 +3.3V_CRT_DAC 1 2 2 1 L30
VTT_4 3 1
22n_0805_25V
0.1U_0402_16V4Z~D
C537
U8 BLM18PG181SN1_0603~D BLM18PG181SN1_0603~D
CRT
VTT_5 3
0.022U_0402_16V7K~D
0.1U_0402_16V4Z~D
C533
U7 C538 1 1
2 2 VTT_6 3
C534
U5 A30 1 1 0.1U_0402_16V4Z~D
VTT_7 VCCA_DAC_BG +3.3V_RUN_DAC_BG 2
22n_0805_25V
C536
C539
U3 C540
VTT_8
C723
C541
U2 B32 10U_0805_10V4Z~D
D VTT_9 VSSA_DAC_BG 2 2 D
U1 VTT_10 2 @ 2
T13 VTT_11
VTT
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
2.2U_0603_6.3V6K~D
T11 VTT_12
1 1 1
T10
T9
VTT_13 VCCA_DPLLA B49 +1.25V_RUN_DPLLA C533,C534,C536,C545,C553,C579 are being
VTT_14
C542
C543
C544
T7 VTT_15 VCCA_DPLLB H49 +1.25V_RUN_DPLLB replaced by 0-ohm 0805 resistor
PLL
T6 +3.3V_RUN_TVDACB
VTT_16
T5 VTT_17 VCCA_HPLL AL2 +1.25V_RUN_HPLL
2 2 2 +VCC_TX_LVDS
T3 VTT_18 1 2
T2 VTT_19 VCCA_MPLL AM2 +1.25V_RUN_MPLL
22n_0805_25V
0.1U_0402_16V4Z~D
R3 VTT_20 3
R2 VTT_21 1
+VCC_PEG
C545
LVDS
R1 A41 +VCC_TX_LVDS L32
VTT_22 VCCA_LVDS
C546
1000P_0402_50V7K~D
+1.25V_RUN_AXD 1 BLM18PG181SN1_0603~D
B41 +3.3V_RUN 2 1
VSSA_LVDS +1.05V_VCCP 2
220U_D2_4VY_R15M~D
10U_0805_4VAM~D
C547
+1.25V_RUN AT23 1
L33 VCC_AXD_1
AU28 VCC_AXD_2 1
2 +
2 1 AU24 VCC_AXD_3 VCCA_PEG_BG K50
0.1U_0402_16V4Z~D
C548
C549
BLM18AG121SN1D_0603~D AT29 K49 1
VCC_AXD_4 VSSA_PEG_BG
AXD
PEG
AT25 VCC_AXD_5 2 2
22U_0805_6.3V6M~D
1U_0603_10V4Z~D
AT30 VCC_AXD_6 +3.3V_RUN_TVDACC
C550
1 1 VCCA_PEG_PLL U51 +1.25V_RUN_PEGPLL 2
C551
C552
AR29 VCC_AXD_NCTF
+1.25V_RUN 1 2
2 2 +1.25V_RUN_A_SM
22n_0805_25V
0.1U_0402_16V4Z~D
B23 VCC_AXF_1 +VCC_RXR_DMI L34 3
B21 VCC_AXF_2 1
C553
AXF
A21 AW18 BLM18PG181SN1_0603~D

VCC_AXF_3 VCCA_SM_1 +1.25V_RUN
220U_D2_4VY_R15M~D
C555
VCCA_SM_2 AV19 2 1 +1.05V_VCCP
+1.25V_RUN
100U_D2E_6.3VM_R18M~D
10U_0805_4VAM~D
VCCA_SM_3 AU19 1
R406 2
AJ50 VCC_DMI VCCA_SM_4 AU18 1
C556
AU17 1 2 +
+1.8V_SM_CK VCCA_SM_5
0.1U_0402_16V4Z~D
SM
1U_0603_10V4Z~D
4.7U_0603_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
C557
C C
VCCA_SM_7 AT22 1
1 BK24 AT21 0_0805_5%~D
VCC_SM_CK_1 VCCA_SM_8 2 2
C591
C558
BK23 AT19 +
VCC_SM_CK_2 VCCA_SM_9 1 1 1 1
CLK
C560
BJ24 VCC_SM_CK_3 VCCA_SM_10 AT18
C559
C561
C562
BJ23 VCC_SM_CK_4 VCCA_SM_11 AT17
2 2
VCCA_SM_NCTF_1 AR17
2 2 2 2
VCCA_SM_NCTF_2 AR16
A43 +1.25V_RUN_SM_CK +1.25V_RUN

+VCC_TX_LVDS VCC_TX_LVDS +1.25V_RUN +1.25V_RUN_PEGPLL
BC29 L35
VCCA_SM_CK_1 BLM21PG221SN1D_0805~D
BB29 1 2
POWER VCCA_SM_CK_2
0.1U_0402_16V4Z~D
22U_0805_6.3V6M~D
1U_0603_10V4Z~D
1U_0603_10V4Z~D
R408 1 2
+3.3V_RUN C40 0_0603_5%~D
VCC_HV_1
0.1U_0402_16V4Z~D
B40 1 1 1 1 C567
VCC_HV_2
0.1U_0402_16V4Z~D
C563
C564
C565
C566
C25 +3.3V_RUN_TVDACA 10U_0805_4VAM~D R409 1
+VCC_PEG VCCA_TVA_DAC_1
C568
1 VCCA_TVA_DAC_2 B25 2 1
C597
VCCA_TVB_DAC_1 C27 +3.3V_RUN_TVDACB

TV
2 2 2 2 1_0402_5%~D
AD51 VCC_PEG_1 VCCA_TVB_DAC_2 B27
2
W50 VCC_PEG_2 VCCA_TVC_DAC_1 B28 +3.3V_RUN_TVDACC
2
PEG
W51 VCC_PEG_3 VCCA_TVC_DAC_2 A28

V49 VCC_PEG_4
V50 VCC_PEG_5 +1.5V_RUN
TV/CRT
M32 +1.5V_RUN_QDAC R815

VCCD_CRT 100_0603_5%~D
VCCD_TVDAC L29 +1.5V_RUN_TVDAC
+VCC_RXR_DMI AH50 VCC_RXR_DMI_1 1 2
0.022U_0402_16V7K~D
1U_0603_10V4Z~D
0.1U_0402_16V4Z~D
DMI
AH51 VCC_RXR_DMI_2 VCCD_QDAC N28 +1.5V_RUN_QDAC +1.25V_RUN +1.25V_RUN_HPLL +1.25V_RUN_MPLL

+1.25V_RUN +1.25V_RUN
1 1 1
Non-iAMT
C570
AN2 L37 L38
VCCD_HPLL C722
C569
+1.25V_RUN_PEGPLL 45mA Max. 2 1 45mA Max. 2 1
0.1U_0402_16V4Z~D
A7 U48 1 BLM18AG121SN1D_0603~D BLM18AG121SN1D_0603~D

VTTLF1 VCCD_PEG_PLL 2 2 2
VTTLF
0.1U_0402_16V4Z~D
B B
F2 VTTLF2
22U_0805_6.3VAM~D
C642
AH1 VTTLF3 1 1 1 1 1 1
C571 C574 C575
2
0.47U_0402_10V4Z~D
0.47U_0402_10V4Z~D
0.47U_0402_10V4Z~D
C554
C572
LVDS
J41 C573
VCCD_LVDS_1 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 22U_0805_6.3VAM~D
1 1 1 VCCD_LVDS_2 H42
2 +1.5V_RUN_TVDAC 2 2 2 2 2
C576
C577
C578
1 2
2 2 2 0.022U_0402_16V7K~D
0.1U_0402_16V4Z~D
LE88CLGM A0 QM20_FCBGA1299~D
@ R116 1 1
3
22n_0805_25V
C584
0_0603_5%~D
C720
2 1 +1.8V_RUN
C579
2 2
1U_0603_10V4Z~D
2 1 +1.8V_SUS
R579 @ 1 R152 @
0_0603_5%~D 0_0603_5%~D +1.25V_RUN_DPLLA +1.25V_RUN_DPLLB
+1.25V_RUN +1.25V_RUN
C581
+1.8V_RUN 1 2 +VCC_TX_LVDS
L42 L39 L40
+VCC_TX_LVDS_R 2 2
+1.8V_SUS 1 2
R578
1 40mA Max. 2 1
10U_MLZ2012E100PTAIN_60mA_25%_0805~D
40mA Max. 2 1
10U_MLZ2012E100PTAIN_60mA_25%_0805~D
1000P_0402_50V7K~D
220U_D2_4VY_R15M~D
0_0603_5%~D BLM18AG121SN1D_0603~D 1 1 1
1 1 1
+ C587 + C585 C588 + C586
C596
C595
470U_D2_2.5VM_R15~D 470U_D2_2.5VM_R15~D
+1.8V_SUS +1.8V_SM_CK 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
2 2 L41 2 2 2 2
2 1
+1.25V_RUN
1_0603_5%~D
0.1U_0402_16V4Z~D
22U_0805_6.3VAM~D
BLM18AG121SN1D_0603~D
1
1 1
R416
C592
om
1U_0603_10V4Z~D
10U_0805_4VAM~D
C593
A C594 A
1 1
l.c
2 2
C589
10U_0805_4VAM~D
2
C590
2 1
ai
2 2 DELL CONFIDENTIAL/PROPRIETARY
tm
ho
Place caps close
f@
+1.05V_VCCP +3.3V_RUN PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
to VCC_AXF (Pin TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Crestline(4 of 6)
in
A21, B21, B23) 2 1 1 2 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
xa
D16
RB751V_SOD323~D R417 PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-3301P
he
10_0603_5%~D
5 4 3 2 1
5 4 3 2 1
+1.05V_VCCP +1.05V_VCCP
U29G +1.05V_VCCP
+3.3V_RUN D17
R420 2 AT35
10_0603_5%~D VCC_1
AT34 VCC_2 VCC_AXG_NCTF_1 T17
1 2 1 AH28 VCC_3 VCC_AXG_NCTF_2 T18
AC32 VCC_4 VCC_AXG_NCTF_3 T19
3 AC31 VCC_5 VCC_AXG_NCTF_4 T21
AK32 T22
VCC CORE
VCC_6 VCC_AXG_NCTF_5
220U_D2_4VY_R15M~D
220U_D2_4VY_R15M~D
BAT54CW_SOT323~D AJ31 VCC_7 VCC_AXG_NCTF_6 T23
+1.05V_VCCP AJ28 T25 Layout Note:
VCC_8 VCC_AXG_NCTF_7 1 1
AH32 VCC_9 VCC_AXG_NCTF_8 U15
C598
C599
U29F AH31 U16 + + 370 mils from edge.
D VCC_10 VCC_AXG_NCTF_9 D
AB33 VCC_NCTF_1 AH29 VCC_11 VCC_AXG_NCTF_10 U17
AB36 VCC_NCTF_2 AF32 VCC_12 VCC_AXG_NCTF_11 U19
2 2
AB37 VCC_NCTF_3 VCC_AXG_NCTF_12 U20
AC33 VCC_NCTF_4 VSS_NCTF_1 T27 VCC_AXG_NCTF_13 U21
AC35 VCC_NCTF_5 VSS_NCTF_2 T37 VCC_AXG_NCTF_14 U23
AC36 VCC_NCTF_6 VSS_NCTF_3 U24 R30 VCC_13 VCC_AXG_NCTF_15 U26
AD35 VCC_NCTF_7 VSS_NCTF_4 U28 VCC_AXG_NCTF_16 V16
AD36 VCC_NCTF_8 VSS_NCTF_5 V31 VCC_AXG_NCTF_17 V17
AF33 VCC_NCTF_9 VSS_NCTF_6 V35 VCC_AXG_NCTF_18 V19
AF36 VCC_NCTF_10 VSS_NCTF_7 AA19 VCC_AXG_NCTF_19 V20
220U_D2_4VY_R15M~D
22U_0805_6.3VAM~D
0.22U_0402_10V4Z~D
AH33 AB17 V21
1 AH35
VCC_NCTF_11
VCC_NCTF_12
VSS_NCTF_8
VSS_NCTF_9 AB35 POWER VCC_AXG_NCTF_20
VCC_AXG_NCTF_21 V23
AH36 AD19 +1.8V_SUS V24
1 1 VCC_NCTF_13 VSS_NCTF_10 VCC_AXG_NCTF_22
C602
C603
C604
+ AH37 AD37 Y15
VCC_NCTF_14 VSS_NCTF_11 VCC_AXG_NCTF_23
AJ33 VCC_NCTF_15 VSS_NCTF_12 AF17 AU32 VCC_SM_1 VCC_AXG_NCTF_24 Y16
AJ35 VCC_NCTF_16 VSS_NCTF_13 AF35 AU33 VCC_SM_2 VCC_AXG_NCTF_25 Y17
2 2 2
0.1U_0402_10V7K~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
AK33 VCC_NCTF_17 VSS_NCTF_14 AK17 AU35 VCC_SM_3 VCC_AXG_NCTF_26 Y19
330U_D2E_2.5VM~D
0.47U_0402_10V4Z~D
1U_0603_10V4Z~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
10U_0805_10V4Z~D
22U_0805_6.3VAM~D
AK35 VCC_NCTF_18 VSS_NCTF_15 AM17 AV33 VCC_SM_4 VCC_AXG_NCTF_27 Y20
AK36 VCC_NCTF_19 VSS_NCTF_16 AM24 2 1 1 1 AW33 VCC_SM_5 VCC_AXG_NCTF_28 Y21
AK37 VCC_NCTF_20 VSS_NCTF_17 AP26 AW35 VCC_SM_6 VCC_AXG_NCTF_29 Y23 1 1 1 1 1 1
C605
C606
C607
C609
C610
C611
C612
AD33 AP28 + AY35 Y24
VCC_NCTF_21 VSS_NCTF_18 VCC_SM_7 VCC_AXG_NCTF_30
C608
C600
C601
AJ36 VCC_NCTF_22 VSS_NCTF_19 AR15 BA32 VCC_SM_8 VCC_AXG_NCTF_31 Y26
1 2 2
AM35 VCC_NCTF_23 VSS_NCTF_20 AR19 BA33 VCC_SM_9 VCC_AXG_NCTF_32 Y28
2 2 2 2 2 2 2
Layout Note: AL33 VCC_NCTF_24 VSS_NCTF_21 AR28 BA35 VCC_SM_10 VCC_AXG_NCTF_33 Y29
370 mils from edge AL35 VCC_NCTF_25 BB33 VCC_SM_11 VCC_AXG_NCTF_34 AA16
AA33 VCC_NCTF_26 BC32 VCC_SM_12 VCC_AXG_NCTF_35 AA17
AA35 VCC_NCTF_27 BC33 VCC_SM_13 VCC_AXG_NCTF_36 AB16
AA36 VCC_NCTF_28 BC35 VCC_SM_14 VCC_AXG_NCTF_37 AB19
Layout Note:
VCC GFX NCTF

AP35 VCC_NCTF_29 BD32 VCC_SM_15 VCC_AXG_NCTF_38 AC16
0.22U_0402_10V4Z~D
VCC SM
AP36 VCC_NCTF_30 VSS_SCB1 A3 Place C901 where Layout Note: BD35 VCC_SM_16 VCC_AXG_NCTF_39 AC17
0.1U_0402_10V7K~D
AR35 VCC_NCTF_31 VSS_SCB2 B2 Place on the edge BE32 VCC_SM_17 VCC_AXG_NCTF_40 AC19 Layout Note: Inside GMCH
1 1 AR36 C1 LVDS and DDR2 taps. BE33 AD15
VCC_NCTF_32 VSS_SCB3 VCC_SM_18 VCC_AXG_NCTF_41 cavity for VCC_AXG.
C613
C614
C C
Y32 VCC_NCTF_33 VSS_SCB4 BL1 BE35 VCC_SM_19 VCC_AXG_NCTF_42 AD16
Y33 VCC_NCTF_34 VSS_SCB5 BL51 BF33 VCC_SM_20 VCC_AXG_NCTF_43 AD17
Y35 VCC_NCTF_35 VSS_SCB6 A51 BF34 VCC_SM_21 VCC_AXG_NCTF_44 AF16
2 2
Y36 VCC_NCTF_36 BG32 VCC_SM_22 VCC_AXG_NCTF_45 AF19
Y37 VCC_NCTF_37 BG33 VCC_SM_23 VCC_AXG_NCTF_46 AH15
T30 VCC_NCTF_38 BG35 VCC_SM_24 VCC_AXG_NCTF_47 AH16
T34 BH32 AH17
T35
VCC_NCTF_39
VCC_NCTF_40
POWER BH34
VCC_SM_25
VCC_SM_26
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49 AH19
U29 VCC_NCTF_41 BH35 VCC_SM_27 VCC_AXG_NCTF_50 AJ16
U31 VCC_NCTF_42 BJ32 VCC_SM_28 VCC_AXG_NCTF_51 AJ17
Layout Note: U32 VCC_NCTF_43 BJ33 VCC_SM_29 VCC_AXG_NCTF_52 AJ19
Inside GMCH cavity. U33 VCC_NCTF_44 BJ34 VCC_SM_30 VCC_AXG_NCTF_53 AK16
U35 VCC_NCTF_45 BK32 VCC_SM_31 VCC_AXG_NCTF_54 AK19
U36 VCC_NCTF_46 BK33 VCC_SM_32 VCC_AXG_NCTF_55 AL16
V32 VCC_NCTF_47 BK34 VCC_SM_33 VCC_AXG_NCTF_56 AL17
V33 VCC_NCTF_48 BK35 VCC_SM_34 VCC_AXG_NCTF_57 AL19
V36 VCC_NCTF_49 BL33 VCC_SM_35 VCC_AXG_NCTF_58 AL20
V37 +1.05V_VCCP AU30 AL21
VCC_NCTF_50 VCC_SM_36 VCC_AXG_NCTF_59
VCC_AXG_NCTF_60 AL23
VCC_AXG_NCTF_61 AM15
VCC_AXG_NCTF_62 AM16
VCC_AXM_1 AT33 VCC_AXG_NCTF_63 AM19
+1.05V_VCCP AT31 AM20
VCC_AXM_2 VCC_AXG_NCTF_64
VCC_AXM_3 AK29 +1.05V_VCCP R20 VCC_AXG_1 VCC_AXG_NCTF_65 AM21
AL24 VCC_AXM_NCTF_1 VCC_AXM_4 AK24 T14 VCC_AXG_2 VCC_AXG_NCTF_66 AM23
AL26 VCC_AXM_NCTF_2 VCC_AXM_6 AK23 W13 VCC_AXG_3 VCC_AXG_NCTF_67 AP15
22U_0805_6.3V6M~D
0.22U_0402_10V4Z~D
0.22U_0402_10V4Z~D
AL28 VCC_AXM_NCTF_3 VCC_AXM_5 AJ26 W14 VCC_AXG_4 VCC_AXG_NCTF_68 AP16

1 1 1 AM26 VCC_AXM_NCTF_4 VCC_AXM_7 AJ23 Y12 VCC_AXG_5 VCC_AXG_NCTF_69 AP17
C615
C616
C617
AM28 VCC_AXM_NCTF_5 AA20 VCC_AXG_6 VCC_AXG_NCTF_70 AP19

2 2 2
B B
AM33 VCC_AXM_NCTF_9 AB21 VCC_AXG_10 VCC_AXG_NCTF_74 AP24
AP29 VCC_AXM_NCTF_10 AB24 VCC_AXG_11 VCC_AXG_NCTF_75 AR20
AP31 VCC_AXM_NCTF_11 AB29 VCC_AXG_12 VCC_AXG_NCTF_76 AR21
AP32 VCC_AXM_NCTF_12 AC20 VCC_AXG_13 VCC_AXG_NCTF_77 AR23
Layout Note: AP33 VCC_AXM_NCTF_13 AC21 VCC_AXG_14 VCC_AXG_NCTF_78 AR24
VCC GFX
Place close to GMCH edge. AL29 VCC_AXM_NCTF_14 AC23 VCC_AXG_15 VCC_AXG_NCTF_79 AR26
AL31 VCC_AXM_NCTF_15 AC24 VCC_AXG_16 VCC_AXG_NCTF_80 V26
AL32 VCC_AXM_NCTF_16 AC26 VCC_AXG_17 VCC_AXG_NCTF_81 V28
AR31 VCC_AXM_NCTF_17 AC28 VCC_AXG_18 VCC_AXG_NCTF_82 V29
0.1U_0402_10V7K~D
AR32 VCC_AXM_NCTF_18 AC29 VCC_AXG_19 VCC_AXG_NCTF_83 Y31

0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
AR33 VCC_AXM_NCTF_19 AD20 VCC_AXG_20

1 1 1 AD23 VCC_AXG_21
C618
C619
C620
AD24 VCC_AXG_22
AD28 VCC_AXG_23
LE88CLGM A0 QM20_FCBGA1299~D VCCSM_LF1
VCC SM LF
AF21 VCC_AXG_24 VCC_SM_LF1 AW45
2 2 2 VCCSM_LF2
AF26 VCC_AXG_25 VCC_SM_LF2 BC39
AA31 BE39 VCCSM_LF3
VCC_AXG_26 VCC_SM_LF3 VCCSM_LF4
AH20 VCC_AXG_27 VCC_SM_LF4 BD17
AH21 BD4 VCCSM_LF5
VCC_AXG_28 VCC_SM_LF5 VCCSM_LF6
AH23 VCC_AXG_29 VCC_SM_LF6 AW8
Layout Note: Inside GMCH cavity. AH24 AT6 VCCSM_LF7
VCC_AXG_30 VCC_SM_LF7
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.22U_0402_10V4Z~D
0.22U_0402_10V4Z~D
0.47U_0402_10V4Z~D
1U_0402_6.3V4Z~D
1U_0402_6.3V4Z~D
AH26 VCC_AXG_31
AD31 VCC_AXG_32
AJ20 VCC_AXG_33 1 1 1 1 1 1 1
C621
C622
C623
C624
C625
C626
C627
AN14 VCC_AXG_34
2 2 2 2 2 2 2
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Crestline(5 of 6)
LA-3301P
5 4 3 2 1
5 4 3 2 1
U29I
A13 VSS_1 VSS_100 AW24

AA21 VSS_5 VSS_104 AW7
AA24 VSS_6 VSS_105 AY10
AA29 VSS_7 VSS_106 AY24
AB20 AY37 U29J
VSS_8 VSS_107
AB23 VSS_9 VSS_108 AY42
D D
AB26 VSS_10 VSS_109 AY43 C46 VSS_199 VSS_287 W11
AC10 VSS_13 VSS_112 AY50 D13 VSS_202 VSS_290 W47
AC13 VSS_14 VSS_113 B10 D24 VSS_203 VSS_291 W5
AC3 VSS_15 VSS_114 B20 D3 VSS_204 VSS_292 W7
AC39 VSS_16 VSS_115 B24 D32 VSS_205 VSS_293 Y13
AD1 VSS_19 VSS_118 B35 D49 VSS_208 VSS_296 Y45
AD21 VSS_20 VSS_119 B38 E10 VSS_209 VSS_297 Y49
AD41 VSS_24 VSS_123 B8 E32 VSS_213 VSS_301 P29
AD45 VSS_25 VSS_124 BA1 E47 VSS_214 VSS_302 T29
AD49 VSS_26 VSS_125 BA17 F19 VSS_215 VSS_303 T31
AD5 VSS_27 VSS_126 BA18 F36 VSS_216 VSS_304 T33
AD50 VSS_28 VSS_127 BA2 F4 VSS_217 VSS_305 R28
AD8 VSS_29 VSS_128 BA24 F40 VSS_218
AE10 VSS_30 VSS_129 BB12 F50 VSS_219
AE14 VSS_31 VSS_130 BB25 G1 VSS_220
AE6 VSS_32 VSS_131 BB40 G13 VSS_221 VSS_306 AA32
AF20 VSS_33 VSS_132 BB44 G16 VSS_222 VSS_307 AB32
AF23 VSS_34 VSS_133 BB49 G19 VSS_223 VSS_308 AD32
AF24 VSS_35 VSS_134 BB8 G24 VSS_224 VSS_309 AF28
AF31 VSS_36 VSS_135 BC16 G28 VSS_225 VSS_310 AF29
AG2 VSS_37 VSS_136 BC24 G29 VSS_226 VSS_311 AT27
AG38 VSS_38 VSS_137 BC25 G33 VSS_227 VSS_312 AV25
AG43 VSS_39 VSS_138 BC36 G42 VSS_228 VSS_313 H50
AG47 VSS_40 VSS_139 BC40 G45 VSS_229
AG50 VSS_41 VSS_140 BC51 G48 VSS_230
C C
AH3
AH40
VSS_42
VSS_43
VSS VSS_141
VSS_142
BD13
BD2
G8
H24
VSS_231
VSS_232
AH41
AH7
VSS_44
VSS_45
VSS_143
VSS_144
BD28
BD45
H28
H4
VSS_233
VSS_234
VSS
AH9 VSS_46 VSS_145 BD48 H45 VSS_235
AJ11 VSS_47 VSS_146 BD5 J11 VSS_236
AJ13 VSS_48 VSS_147 BE1 J16 VSS_237
AJ24 VSS_50 VSS_149 BE23 J24 VSS_239
AJ29 VSS_51 VSS_150 BE30 J28 VSS_240
AJ32 VSS_52 VSS_151 BE42 J33 VSS_241
AJ43 VSS_53 VSS_152 BE51 J35 VSS_242
AJ49 VSS_55 VSS_154 BF12
AK20 VSS_56 VSS_155 BF16 K12 VSS_245
AK21 VSS_57 VSS_156 BF36 K47 VSS_246
AK26 VSS_58 VSS_157 BG19 K8 VSS_247
AK28 VSS_59 VSS_158 BG2 L1 VSS_248
AK31 VSS_60 VSS_159 BG24 L17 VSS_249
AK51 VSS_61 VSS_160 BG29 L20 VSS_250
AL1 VSS_62 VSS_161 BG39 L24 VSS_251
AM11 VSS_63 VSS_162 BG48 L28 VSS_252
AM13 VSS_64 VSS_163 BG5 L3 VSS_253
AM3 VSS_65 VSS_164 BG51 L33 VSS_254
AM4 VSS_66 VSS_165 BH17 L49 VSS_255
AM41 VSS_67 VSS_166 BH30 M28 VSS_256
AM45 VSS_68 VSS_167 BH44 M42 VSS_257
AN1 VSS_69 VSS_168 BH46 M46 VSS_258
AN38 VSS_70 VSS_169 BH8 M49 VSS_259
AN39 VSS_71 VSS_170 BJ11 M5 VSS_260
AN43 VSS_72 VSS_171 BJ13 M50 VSS_261
AN5 VSS_73 VSS_172 BJ38 M9 VSS_262
B B
AN7 VSS_74 VSS_173 BJ4 N11 VSS_263
AP4 VSS_75 VSS_174 BJ42 N14 VSS_264
AP48 VSS_76 VSS_175 BJ46 N17 VSS_265
AP50 VSS_77 VSS_176 BK15 N29 VSS_266
AR11 VSS_78 VSS_177 BK17 N32 VSS_267
AR2 VSS_79 VSS_178 BK25 N36 VSS_268
AR39 VSS_80 VSS_179 BK29 N39 VSS_269
AR44 VSS_81 VSS_180 BK36 N44 VSS_270
AR47 VSS_82 VSS_181 BK40 N49 VSS_271
AR7 VSS_83 VSS_182 BK44 N7 VSS_272
AT10 VSS_84 VSS_183 BK6 P19 VSS_273
AT14 VSS_85 VSS_184 BK8 P2 VSS_274
AT41 VSS_86 VSS_185 BL11 P23 VSS_275
AT49 VSS_87 VSS_186 BL13 P3 VSS_276
AU1 VSS_88 VSS_187 BL19 P50 VSS_277
AU23 VSS_89 VSS_188 BL22 R49 VSS_278
AU29 VSS_90 VSS_189 BL37 T39 VSS_279
AU3 VSS_91 VSS_190 BL47 T43 VSS_280
AU36 VSS_92 VSS_191 C12 T47 VSS_281
AU49 VSS_93 VSS_192 C16 U41 VSS_282
AU51 VSS_94 VSS_193 C19 U45 VSS_283
AV39 VSS_95 VSS_194 C28 U50 VSS_284
AV48 VSS_96 VSS_195 C29 V2 VSS_285
AW1 VSS_97 VSS_196 C33 V3 VSS_286
AW12 VSS_98 VSS_197 C36
AW16 VSS_99 VSS_198 C41
om
A A
l.c
ai
tm
ho
f@
Crestline(6 of 6)
in
xa
LA-3301P
he
5 4 3 2 1
5 4 3 2 1
+1.8V_SUS +1.8V_SUS V_DDR_MCH_REF

11 DDR_A_DQS#[0..7] ON TOP SIDE V_DDR_MCH_REF
11 DDR_A_D[0..63]
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
JDIM2
11 DDR_A_DM[0..7] 1 VREF VSS 2
3 4 DDR_A_D4 1 1
DDR_A_D0 VSS DQ4 DDR_A_D6
11 DDR_A_DQS[0..7] Layout Note: 5 DQ0 DQ5 6
C114
C112
DDR_A_D5 7 8
Place near JDIM1 9
DQ1 VSS
10 DDR_A_DM0
11 DDR_A_MA[0..14] VSS DM0 2 2
DDR_A_DQS#0 11 12
DDR_A_DQS0 DQS0# VSS DDR_A_D1
13 DQS0 DQ6 14
15 16 DDR_A_D2
DDR_A_D3 VSS DQ7
17 DQ2 VSS 18
D DDR_A_D7 DDR_A_D9 D
19 DQ3 DQ12 20
21 22 DDR_A_D8
DDR_A_D13 VSS DQ13
23 DQ8 VSS 24
+1.8V_SUS DDR_A_D12 25 26 DDR_A_DM1
DQ9 DM1
27 VSS VSS 28
DDR_A_DQS#1 29 30 M_CLK_DDR0
DQS1# CK0 M_CLK_DDR0 10
DDR_A_DQS1 31 32 M_CLK_DDR#0
DQS1 CK0# M_CLK_DDR#0 10
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
33 VSS VSS 34
1 1 1 1 1 DDR_A_D10 35 36 DDR_A_D15
DQ10 DQ14
C133
C132
C437
C117
C116
DDR_A_D11 37 38 DDR_A_D14
DQ11 DQ15
39 VSS VSS 40
2 2 2 2 2
41 VSS VSS 42
DDR_A_D21 DQ16 DQ20 DDR_A_D16
45 DQ17 DQ21 46
47 VSS VSS 48
DDR_A_DQS#2 49 50 PM_EXTTS#0 PM_EXTTS#0 10
DDR_A_DQS2 DQS2# NC DDR_A_DM2
51 DQS2 DM2 52
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
53 VSS VSS 54
1 1 1 1 DDR_A_D22 55 56 DDR_A_D18
DQ18 DQ22
C130
C131
C119
C118
DQ19 DQ23
59 VSS VSS 60
2 2 2 2 DDR_A_D25 DQ24 DQ28 DDR_A_D24
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 VSS VSS 72
75 DQ27 DQ31 76
77 VSS VSS 78
C DDR_CKE0_DIMMA DDR_CKE1_DIMMA C
10 DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA 10
81 VDD VDD 82
83 NC NC/A15 84
DDR_A_BS2 85 86 DDR_A_MA14
11 DDR_A_BS2 BA2 NC/A14
87 VDD VDD 88
DDR_A_MA12 89 90 DDR_A_MA11
DDR_A_MA9 A12 A11 DDR_A_MA7
Layout Note: 91 A9 A7 92
Place one cap close to every 2 pullup 95
A8 A6
96
DDR_A_MA5 VDD VDD DDR_A_MA4
resistors terminated to +0.9V_DDR_VTT 97 A5 A4 98
DDR_A_MA1 A3 A2 DDR_A_MA0
101 A1 A0 102
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS1 DDR_A_BS1 11
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
11 DDR_A_BS0 107 BA0 RAS# 108 DDR_A_RAS# 11
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
11 DDR_A_WE# WE# S0# DDR_CS0_DIMMA# 10
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
11 DDR_A_CAS# CAS# ODT0 M_ODT0 10
+0.9V_DDR_VTT DDR_CS1_DIMMA# 115 116 DDR_A_MA13
10 DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
M_ODT1 119 120
10 M_ODT1 NC/ODT1 NC
121 VSS VSS 122
DDR_A_D33 123 124 DDR_A_D36
125 DQ33 DQ37 126
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
127 VSS VSS 128

DDR_A_DQS#4 129 130 DDR_A_DM4
DDR_A_DQS4 DQS4# DM4
1 1 1 1 1 1 1 1 1 1 1 1 1 1 131 DQS4 VSS 132
133 134 DDR_A_D35
DDR_A_D34 VSS DQ38 DDR_A_D38
135 DQ34 DQ39 136
DDR_A_D39 137 138
2 2 2 2 2 2 2 2 2 2 2 2 2 2 DQ35 VSS DDR_A_D44
139 VSS DQ44 140
C136
C137
C138
C139
C140
C141
C104
C105
C106
C107
C108
C109
C110
C707
DDR_A_D41 141 142 DDR_A_D45

B DDR_A_D40 DQ40 DQ45 B
143 DQ41 VSS 144
145 146 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 DM5 DQS5 148
149 VSS VSS 150
DDR_A_D46 151 152 DDR_A_D42
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D49 157 158 DDR_A_D48
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 M_CLK_DDR1
NC,TEST CK1 M_CLK_DDR1 10
+0.9V_DDR_VTT 165 166 M_CLK_DDR#1
VSS CK1# M_CLK_DDR#1 10
DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
RN4 RN6 169 170
DDR_A_MA1 DQS6 DM6
1 4 4 1 DDR_A_MA9 171 VSS VSS 172
DDR_A_MA3 2 3 3 2 DDR_A_MA12 DDR_A_D51 173 174 DDR_A_D50
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D DDR_A_D54 DQ50 DQ54 DDR_A_D55
175 DQ51 DQ55 176
RN3 RN12 Layout Note: 177 VSS VSS 178
DDR_A_BS0 1 4 4 1 DDR_A_MA7 Place these resistor DDR_A_D60 179 180 DDR_A_D61
DDR_A_MA10 DQ56 DQ60
2 3 3 2 DDR_A_MA6 closely DIMM0,all DDR_A_D56 181 DQ57 DQ61 182 DDR_A_D57
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D 183 184
RN9 RN5 trace length<750 mil DDR_A_DM7 VSS VSS DDR_A_DQS#7
185 DM7 DQS7# 186
DDR_A_RAS# 1 4 4 1 DDR_A_MA5 187 188 DDR_A_DQS7
DDR_CS0_DIMMA# 2 VSS DQS7
3 3 2 DDR_A_MA8 DDR_A_D58 189 DQ58 VSS 190
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D DDR_A_D62 191 192 DDR_A_D59
RN11 DQ59 DQ62 DDR_A_D63
RN2 193 194
DDR_A_CAS# VSS DQ63
1 4 4 1 DDR_A_MA4 17,23 MEM_SDATA
MEM_SDATA 195 SDA VSS 196
DDR_A_WE# 2 3 3 2 DDR_A_MA2 MEM_SCLK 197 198 R122 1 2 10K_0402_5%~D
17,23 MEM_SCLK SCL SAO
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D +3.3V_RUN 199 200 R127 1 2 10K_0402_5%~D
RN10 VDDSPD SA1
RN1
0.1U_0402_16V4Z~D
M_ODT1 2.2U_0603_6.3V6K~D
1 4 4 1 DDR_A_MA0 201 GND GND 202
DDR_CS1_DIMMA# 2 3 3 2 DDR_A_BS1 1 1
C113
C115
A 56_0404_4P2R_5%~D 56_0404_4P2R_5%~D TYCO_1470815-2~D A
RN8
Non-iAMT
DDR_CKE1_DIMMA 2 1 4 1 M_ODT0
2 2
DIMMA
R223 3 2 DDR_A_MA13
56_0402_5%~D 56_0404_4P2R_5%~D RESERVE
RN13
RN7 Layout Note:
DDR_CKE0_DIMMA 2 1 DDR_A_MA14
DDR_A_BS2 1
3
4
4
3 2 DDR_A_MA11
Place these resistor
closely DIMM0,all
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
trace length TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Max=1.3" BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRII-SODIMM SLOT1
LA-3301P
5 4 3 2 1
5 4 3 2 1
+1.8V_SUS +1.8V_SUS V_DDR_MCH_REF

11 DDR_B_DQS#[0..7]
V_DDR_MCH_REF
11 DDR_B_D[0..63]
ON BOTTOM SIDE
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
JDIM1
11 DDR_B_DM[0..7] Layout Note: 1 VREF VSS 2
3 4 DDR_B_D5 1 1
Place near JDIM2 DDR_B_D1 5
VSS DQ4
6 DDR_B_D4
11 DDR_B_DQS[0..7] DQ0 DQ5
C447
C436
DDR_B_D0 7 8
DQ1 VSS DDR_B_DM0
11 DDR_B_MA[0..14] 9 VSS DM0 10
DDR_B_DQS#0 2 2
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D2
DQS0 DQ6 DDR_B_D3
15 VSS DQ7 16
DDR_B_D6 17 18
DDR_B_D7 DQ2 VSS DDR_B_D13
19 DQ3 DQ12 20
D +1.8V_SUS 21 22 DDR_B_D12 D
DDR_B_D8 VSS DQ13
23 DQ8 VSS 24
DDR_B_D9 25 26 DDR_B_DM1
DQ9 DM1
27 VSS VSS 28
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
DDR_B_DQS#1 29 30 M_CLK_DDR2
DQS1# CK0 M_CLK_DDR2 10
1 1 1 1 1 DDR_B_DQS1 31 32 M_CLK_DDR#2
DQS1 CK0# M_CLK_DDR#2 10
C439
C440
C412
C438
C411
33 VSS VSS 34
DDR_B_D14 35 36 DDR_B_D10
DDR_B_D15 DQ10 DQ14 DDR_B_D11
37 DQ11 DQ15 38
2 2 2 2 2
39 VSS VSS 40
41 VSS VSS 42
45 DQ17 DQ21 46
47 VSS VSS 48
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
DDR_B_DQS#2 49 50 PM_EXTTS#1 PM_EXTTS#1 10
DDR_B_DQS2 DQS2# NC DDR_B_DM2
1 1 1 1 51 DQS2 DM2 52
C434
C433
C413
C414
53 VSS VSS 54
57 DQ19 DQ23 58
2 2 2 2
59 VSS VSS 60
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
71 VSS VSS 72
75 DQ27 DQ31 76
77 VSS VSS 78
DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB
C 10 DDR_CKE2_DIMMB CKE0 NC/CKE1 DDR_CKE3_DIMMB 10 C
81 VDD VDD 82
83 NC NC/A15 84
Layout Note: DDR_B_BS2 85 86 DDR_B_MA14
11 DDR_B_BS2 BA2 NC/A14
87 88
Place one cap close to every 2 pullup DDR_B_MA12 89
VDD VDD
90 DDR_B_MA11
DDR_B_MA9 A12 A11 DDR_B_MA7
resistors terminated to +0.9V_DDR_VTT 91 A9 A7 92
DDR_B_MA8 93 94 DDR_B_MA6
A8 A6
95 VDD VDD 96
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS1 DDR_B_BS1 11
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
11 DDR_B_BS0 107 BA0 RAS# 108 DDR_B_RAS# 11
+0.9V_DDR_VTT DDR_B_WE# 109 110 DDR_CS2_DIMMB#
11 DDR_B_WE# WE# S0# DDR_CS2_DIMMB# 10
111 VDD VDD 112
DDR_B_CAS# 113 114 M_ODT2
11 DDR_B_CAS# CAS# ODT0 M_ODT2 10
DDR_CS3_DIMMB# 115 116 DDR_B_MA13
10 DDR_CS3_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
M_ODT3 119 120

10 M_ODT3 NC/ODT1 NC
121 VSS VSS 122
1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_B_D32 123 124 DDR_B_D33
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_B_DQS#4 129 130 DDR_B_DM4
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
C456
C455
C454
C453
C452
C451
C450
C410
C409
C408
C407
C406
C405
133 134 DDR_B_D38

DDR_B_D35 VSS DQ38 DDR_B_D39
135 DQ34 DQ39 136
DDR_B_D34 137 138
DQ35 VSS DDR_B_D44
139 VSS DQ44 140
DDR_B_D40 141 142 DDR_B_D45
DDR_B_D41 DQ40 DQ45
143 DQ41 VSS 144
B DDR_B_DQS#5 B
145 VSS DQS5# 146
DDR_B_DM5 147 148 DDR_B_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_B_D46 151 152 DDR_B_D43
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_B_D53 157 158 DDR_B_D52
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 M_CLK_DDR3
NC,TEST CK1 M_CLK_DDR3 10
+0.9V_DDR_VTT 165 166 M_CLK_DDR#3
VSS CK1# M_CLK_DDR#3 10
DDR_B_DQS#6 167 168
RN21 DDR_B_DQS6 DQS6# VSS DDR_B_DM6
RN23 169 170
DDR_B_MA1 DDR_B_MA9 DQS6 DM6
1 4 4 1 171 VSS VSS 172
DDR_B_MA3 2 3 3 2 DDR_B_MA12 DDR_B_D55 173 174 DDR_B_D54
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D DDR_B_D50 DQ50 DQ54 DDR_B_D51
175 DQ51 DQ55 176
RN24 RN14 177 178
DDR_B_BS0 DDR_B_MA14 DDR_B_D56 VSS VSS DDR_B_D57
1 4 4 1 179 DQ56 DQ60 180
DDR_B_MA10 2 3 3 2 DDR_B_MA11 DDR_B_D60 181 182 DDR_B_D61
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D DQ57 DQ61
Layout Note: 183 VSS VSS 184
RN17 RN22 Place these resistor DDR_B_DM7 185 186 DDR_B_DQS#7
DDR_B_MA0 DDR_B_MA5 DM7 DQS7# DDR_B_DQS7
1 4 4 1 closely DIMM0,all 187 VSS DQS7 188
DDR_B_BS1 2 3 3 2 DDR_B_MA8 DDR_B_D58 189 190
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D trace length<750 mil DDR_B_D59 DQ58 VSS DDR_B_D62
191 DQ59 DQ62 192 Non-iAMT
RN18 RN15 193 194 DDR_B_D63 +3.3V_RUN
DDR_B_RAS# DDR_B_MA7 MEM_SDATA VSS DQ63
1 4 4 1 16,23 MEM_SDATA 195 SDA VSS 196
DDR_CS2_DIMMB# 2 3 3 2 DDR_B_MA6 MEM_SCLK 197 198
16,23 MEM_SCLK SCL SAO
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D +3.3V_RUN 199 200 2 1
VDDSPD SA1
10K_0402_5%~D
RN25 RN16
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
DDR_B_CAS# 1 4 4 1 DDR_B_MA4 201 202 R243

GND GND
1
DDR_B_WE# DDR_B_MA2 10K_0402_5%~D
om
2 3 3 2
R241
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D TYCO_1565917-4~D
Non-iAMT 1 1
C431
C429
A RN19 A
DIMMB
l.c
DDR_CKE3_DIMMB 2 1 4 1 M_ODT2
R312 3 2 DDR_B_MA13
STANDARD
ai
2
56_0402_5%~D 56_0404_4P2R_5%~D 2 2
tm
RN20
ho
RN26 Layout Note:
DDR_CS3_DIMMB# 2 DDR_B_BS2
M_ODT3
3 4 1
DDR_CKE2_DIMMB
Place these resistor Compal Electronics, Inc.
f@
1 4 3 2 closely DIMM0,all
56_0404_4P2R_5%~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
56_0404_4P2R_5%~D trace length TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
DDRII-SODIMM SLOT2
in
Max=1.3" BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
xa
LA-3301P
he
5 4 3 2 1
5 4 3 2 1
FAN1 Control and Tachometer

R438
+3.3V_SUS +3.3V_RUN
VSET= x 3.3V =0.865V
R436+R438
1
R423
8.2K_0402_5%~D
R424
Tp-70
10K_0402_5%~D
VSET = => Tp = 88.2 C
2
+1.05V_VCCP THERMATRIP1#
21
2
R425
1
2.2K_0402_5%~D C 1
D FAN1_TACH 39 D
1 2 2
B C628
Q38 E 0.1U_0402_16V4Z~D
1
MMST3904-7-F_SOT323-3~D 2
R414 +5V_SUS
7 H_THERMTRIP#
0_0402_5%~D
+3.3V_SUS
1
2
R772
JFAN1 R771
1
+3.3V_SUS +FAN1_VOUT 1 2.21K_0603_1%~D 10K_0603_1%_TSM1A103F34D3RZ~D
FAN1_TACH_FB 1 R773
2
2
2
22U_0805_6.3VAM~D
3 VCP2 10K_0402_5%~D
3
1
1
1 Q102
1
D
C630
R426 @ D19 MOLEX_53398-0371~D 1 2N7002W-7-F_SOT323-3~D
2
8.2K_0402_5%~D RB751S40T1_SOD523-2~D 2 5V_CAL_SIO#
G
2 C750 S
2
3
+1.05V_VCCP THERMATRIP2# 2 2200P_0402_50V7K~D
R427
This thermistor circuit is located near
1
2.2K_0402_5%~D C 1 Top side DDR connector.

1 2 2
B C632
Q39 E 0.1U_0402_16V4Z~D
PWR_MON 48
3
MMST3904-7-F_SOT323-3~D 2
10 THERMTRIP_MCH#
Place under CPU Place cap close to the REM_DIODE3_N, REM_DIODE3_P routing together.
1 Guardian pins as possible. Trace width / Spacing = 10 / 10 mil
C C 2200P_0402_50V7K~D C
2 2
1
@ C633 2 C634 C
1 1
2200P_0402_50V7K~D B 2 Q41
E Q40 C649 B MMST3904-7-F_SOT323-3~D C650
3
1 MMST3904-7-F_SOT323-3~D 1 2200P_0402_50V7K~D E 2200P_0402_50V7K~D

Place C634 close to the
3
2 2 @
Place C633 close to the Q40 as possible Guardian pins as possible Q41 Place near the Place C650
U31
bottom SODIMM close to Q41
Place C636 close to the Guardian pins as possible 39,49 THRM_SMBDAT 11 SMDATA VCP1 43
39,49 THRM_SMBCLK 12 46 VCP2
SMBCLK VCP2
7 H_THERMDA
1
1 REM_DIODE1_P 38 45 REM_DIODE3_P 1 C 1
REM_DIODE1_N DP1 DP3 REM_DIODE3_N Q19
37 DN1 DN3 44 2
C636 C418 B MMST3904-7-F_SOT323-3~D @C904
470P_0402_50V7K~D 41 48 REM_DIODE4_P E 2200P_0402_50V7K~D
3
2 DP2 DP4 REM_DIODE4_N 2 2200P_0402_50V7K~D 2
7 H_THERMDC 40 DN2 DN4 47
R428 2 Diode circuit at DP4/DN4 is

+3VSUS_THRM DP5
+3.3V_SUS 1 2 35 1
3V_SUS DN5 used for skin temp sensor
49.9_0603_1%~D 1 +RTC_CELL 21 ATF_INT# 2 1 +3.3V_SUS (placed optimally between
RTC_PWR3V
0.1U_0402_16V4Z~D
1 20 ATF_INT# 38 R96
C637 1 2 23
ATF_INT# 10K_0402_5%~D CPU, MCH and MEM).
42 SUSPWROK VSUS_PWRGD
C638
0.1U_0402_16V4Z~D R429 1K_0402_5%~D 3 POWER_SW# 39,40

2 POWER_SW# R430
42 ICH_PWRGD# 1 2 16 3V_PWROK#
2 R432 1K_0402_5%~D 10K_0402_5%~D
ACAVAIL_CLR 4 ACAV_IN 39,49,50
THERMATRIP1# 17 2 1 +3.3V_ALW
THERMTRIP1#
THERMTRIP_SIO 25 THERMTRIP_SIO
THERMATRIP2# 18 THERMTRIP2#
SYS_SHDN# 24 THERM_STP# 45
+3.3V_SUS THERMATRIP3# 19 R434 2 1 +RTC_CELL
B THERMTRIP3# @ R431 B
LDO_SHDN#/ADDR 27 2 1 +3.3V_SUS
1
1 42 7.5K_0402_5%~D 10K_0402_5%~D
VSET
LDO_POK 33 2.5V_RUN_PWRGD 42
C639 R436 26
0.1U_0402_16V4Z~D 332K_0402_1%~D XEN LDO_SET
LDO_SET 28
2
34
2
VSS
2
+2.5V_RUN
1K_0402_5%~D
LDO_OUT 32 +2.5V_RUN
10U_0805_10V4Z~D 1U_0603_10V4Z~D 10U_0805_10V4Z~D

R437
+FAN1_VOUT 7 31
FAN_OUT LDO_OUT
8 FAN_OUT 1 1
1
31.6K_0402_1%~D
@ C640
2 @
1
C100 39 30 +3V_LDOIN @ C641
1
FAN_DAC1 LDO_IN
R485
2200P_0402_50V7K~D R438 29 0.1U_0402_16V4Z~D
118K_0402_1%~D LDO_IN 2 2
1
33 MDC_RST_DIS# MDC_RST_DIS# 10
Ra
2
SIO_GFX_PWR GPIO1 R439

13
2
+3.3V_SUS 5V_CAL_SIO# GPIO2
14 GPIO3 VDD_3V 9 2 1 +3.3V_RUN
15 LDO_SET
AUDIO_AVDD_ON GPIO4 0_1210_5%~D
27 AUDIO_AVDD_ON 22 GPIO5 VDD_5V 5 1 1
1K_0402_1%~D
C643
@ R196 36 6
GPIO6/FAN_DAC2 VDD_5V
1
1 2 MDC_RST_DIS# 49 C644
PAD_GND
R441
0.1U_0402_16V4Z~D
10K_0402_5%~D EMC4001_QFN48~D 2 2
+3.3V_SUS SMBUS ADDRESS : 2F Rb
@ R194
2
10U_0805_10V4Z~D
1 2 SIO_GFX_PWR +3.3V_RUN
0.1U_0402_16V4Z~D
1
10K_0402_5%~D C645 1 1 +5V_RUN 1 1 Voltage margining

R433 C648
circuit for LDO output.
C646
C647
8.2K_0402_5%~D 0.1U_0402_16V4Z~D
2 2 2 2
For Vmargin, stuff
Ra=31.6K and Rb=30K.
2
A THERMATRIP3# Rb=1K for production A
1
C203
2
0.1U_0402_16V4Z~D DELL CONFIDENTIAL/PROPRIETARY
@
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, FAN & Thermal Sensor
LA-3301P
5 4 3 2 1
5 4 3 2 1
D D
Q11
JLVDS SI3456BDV-T1-E3_TSOP6~D
45 44 LCD_BCLK- +15V_ALW +LCDVDD +3.3V_RUN
D
MGND1 TXUCLKUT- LCD_BCLK- 12
LCD_BCLK+
S
46 MGND2 TXUCLKUT+ 43 LCD_BCLK+ 12 6
47 42 +15V_ALW 4 5
MGND3 GND1 LCD_B2- +LCDVDD
48 MGND4 TXUOUT2- 41 LCD_B2- 12 2
1
49 40 LCD_B2+ 1
MGND5 TXUOUT2+ LCD_B2+ 12
0.1U_0402_16V4Z~D
R24
G
50 MGND6 GND2 39
1
51 38 LCD_B1- R23 100K_0402_5%~D
LCD_B1- 12
3
MGND7 TXUOUT1- LCD_B1+ R26 100K_0402_5%~D
52 MGND8 TXUOUT1+ 37 LCD_B1+ 12 1
C42
53 36 470_0402_5%~D
2
MGND9 GND3 LCD_B0-
54 35 LCD_B0- 12
2
MGND10 TXUOUT0-
2N7002W-7-F_SOT323-3~D
55 34 LCD_B0+
LCD_B0+ 12
2
MGND11 TXUOUT0+ 2
2N7002W-7-F_SOT323-3~D
0.1U_0603_50V4Z~D
56 NC GND4 33
1
57 32 LCD_ACLK-
NC TXLCLKOUT- LCD_ACLK- 12
1
D D
Q9
31 LCD_ACLK+ 1 @ R25
TXLCLKOUT+ LCD_ACLK+ 12
Q8
C30
30 2 2 100K_0402_5%~D
GND5 LCD_A2- G G
TXLOUT2- 29 LCD_A2- 12
28 LCD_A2+ S S
LCD_A2+ 12
2
TXLOUT2+ 2
GND6 27
1
26 LCD_A1-
TXLOUT1- LCD_A1- 12 D24
25 LCD_A1+
O
TXLOUT1+ LCD_A1+ 12
GND7 24 39 LCD_VCC_TEST_EN 3
23 LCD_A0-
TXLOUT0- LCD_A0- 12
22 LCD_A0+ 1 2
TXLOUT0+ LCD_A0+ 12 I
GND8 21
C R808 1 C
PANEL_I2C_CLK 20 2 0_0603_5%~D LCD_DDCCLK 12 12 ENVDD 2 Q7
G
19 R809 1 2 0_0603_5%~D DDTC124EUA-7-F_SOT323-3~D
PANEL_I2C_DAT LCD_DDCDATA 12
18 BAT54CW_SOT323~D
3
GND9
VEDID 17 +3.3V_RUN
16 +3.3V_RUN 1 2
GND10 @ R527
LCDVDD1 15 +LCDVDD
14 C45 1 1 0_0402_5%~D
LCDVDD2
1
13 LCD_TST
PNL_SLFTST LCD_TST 38
12 C44 @ R155
LCDPWR_SRC 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 10K_0402_5%~D
LCDPWR_SRC 11
2 2
LCDPWR_SRC 10
9
2
GND11
FPBACK 8 1 2 BIA_PWM 12
7 R156 0_0402_5%~D
GND12 R810 1
PBAT_SMBCLK 6 2 0_0603_5%~D LCD_SMBCLK 39
5 R811 1 2 0_0603_5%~D
PBAT_SMBDAT LCD_SMBDAT 39
GND13 4
3
Populate R156 for DPST,
+5V_ALWF +5V_ALW
LAMP_START 2 LAMP_STAT# T28 PAD~D implementation only.
GND14 1 1
IPEX_20330-044E-11F~D C176
0.1U_0402_16V4Z~D
2
Q24 +INV_PWR_SRC
+PWR_SRC FDS4435BZ_SO8~D
Populate R155 for platform 40mil
without DPST support. No 40mil 8
+INV_PWR_SRC 1 7
B Stuff for Discrete DSPT 2 6 B
1 support due to back up 3 5
0.1U_0603_50V4Z~D
2200P_0402_50V7K~D
1000P_0402_50V7K~D
1
1
C180 plan. 1 1 1
C173
0.1U_0603_50V4Z~D R154 C174
4
2
C427
C463
200K_0402_5%~D 0.1U_0603_50V4Z~D
2
2 2 2
2
R153 Q25
3 2N7002W-7-F_SOT323-3~D
S
1 2 1
100K_0402_5%~D
G
2
37,39,41,42 RUN_ON
FDS4435: P CHANNAL
om
A A
l.c
ai
tm
ho
f@
Internal LVDS
in
xa
LA-3301P
he
5 4 3 2 1
5 4 3 2 1
D D
D11 D10 D9 +5V_RUN
SDM10U45-7_SOD523-2~D
DA204U_SOT323~D DA204U_SOT323~D DA204U_SOT323~D
1
@ @ @
2
+3.3V_RUN
CRT_VCC
1
D8
0.01U_0402_16V7K~D
L11
BLM18BB750SN1D_0603~D
CRT_RED 1 2 1
12,36 CRT_RED
L10
0.12A_48V_NANOSMDC012F~D
C151
CRT_GRN 1 2
12,36 CRT_GRN 2
L9
1
F3
CRT_BLU 1 2 R792
12,36 CRT_BLU
0_1206_5%~D
150_0402_1%~D
150_0402_1%~D
150_0402_1%~D
22P_0402_50V8J~D
22P_0402_50V8J~D
22P_0402_50V8J~D
@
C C
1 1 1 1 1 1
1
2
C162
C161
C165
C149 C148 C147
R141
R142
R143
10P_0402_50V8J~D 10P_0402_50V8J~D 10P_0402_50V8J~D

2 2 2 2 @ 2 @ 2 @
@ @ @
2
JCRT
6
+5V_RUN_SYNC 11
RED 1
7
DAT_DDC2 12
T5 PAD~D GREEN 2
8 16
2
1 JVGA_HS 13 17
2.2K_0402_5%~D
1K_0402_5%~D
1K_0402_5%~D
R2 BLUE 3
R137
R3
2.2K_0402_5%~D C160 9
R5
0.1U_0402_16V4Z~D JVGA_VS
@
14
2 M_ID2#
Evaluate Package 4
1
10
CLK_DDC2 15
5
12,36 DAT_DDC2 SUYIN_070915FR015S201CU~D
12,36 CLK_DDC2
D6 +5V_RUN_SYNC R144
SDM10U45-7_SOD523-2~D 1K_0402_5%~D
+5V_RUN 2 1 1 2
5
U15 L1
R60 BLM18AG121SN1D_0603~D
P
OE#
B B
12 CRT_HSYNC 1 2 2 A Y 4 1 2 1 2
R146
G
30_0402_1%~D
10_0402_5%~D HSYNC_R 36
3
SN74AHCT1G125GW_SC70-5~D
VSYNC_R 36
5
L2
R59 BLM18AG121SN1D_0603~D
P
OE#
12 CRT_VSYNC 1 2 2 A Y 4 1 2 1 2
R138
G
10P_0402_50V8J~D
10P_0402_50V8J~D
10P_0402_50V8J~D
10P_0402_50V8J~D
30_0402_1%~D 10_0402_5%~D
U14 1 1 1 1
3
C719
C712
C5
C4
SN74AHCT1G125GW_SC70-5~D
2 2 @ 2 @ 2
A
DA204U A
K1 A2
A1 K2 Compal Electronics, Inc.
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CRT
LA-3301P
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
1 2 PCI_DEVSEL# 30,35 PCI_AD[0..31]

D R442 8.2K_0402_5%~D U32B D
1 2 PCI_STOP# PCI_AD0 D20 A4 PCI_REQ0#
AD0 REQ0# PCI_REQ0# 36
R443 8.2K_0402_5%~D PCI_AD1 E19 D7 PCI_GNT0#
AD1 GNT0# PCI_GNT0# 35,36
PCI_TRDY# PCI_AD2 PCI_REQ1#
1
R444
2
8.2K_0402_5%~D PCI_AD3
D19
A20
AD2 PCI REQ1#/GPIO50 E18
C18 PCI_GNT1#
PCI_REQ1# 30
AD3 GNT1#/GPIO51 PCI_GNT1# 30
1 2 PCI_FRAME# PCI_AD4 D17 B19 SB_WWAN_PCIE_RST#
AD4 REQ2#/GPIO52 SB_WWAN_PCIE_RST# 34 +3.3V_SUS
R445 8.2K_0402_5%~D PCI_AD5 A21 F18 T1 PAD~D
PCI_AD6 AD5 GNT2#/GPIO53 SB_LOM_PCIE_RST# C651
A19 AD6 REQ3#/GPIO54 A11 SB_LOM_PCIE_RST# 28
1 2 PCI_PLOCK# PCI_AD7 C19 C10 PCI_GNT3# T2 PAD~D 0.1U_0402_16V4Z~D
R446 8.2K_0402_5%~D PCI_AD8 AD7 GNT3#/GPIO55
A18 AD8
1 2 PCI _IRDY# PCI_AD9 B16 C17 PCI_C_BE0# PCI_C_BE0# 30,35
R447 8.2K_0402_5%~D PCI_AD10 AD9 C/BE0# PCI_C_BE1#
A12 AD10 C/BE1# E15 PCI_C_BE1# 30,35
1 2 PCI_SERR# PCI_AD11 E16 F16 PCI_C_BE2# PCI_C_BE2# 30,35
R448 8.2K_0402_5%~D PCI_AD12 AD11 C/BE2# PCI_C_BE3#
14
A14 AD12 C/BE3# E17 PCI_C_BE3# 30,35
1 2 PCI_PERR# PCI_AD13 G16 U33A
R449 8.2K_0402_5%~D PCI_AD14 AD13 PCI _IRDY# PCI_PCIRST#
A15 C8 1
P
AD14 IRDY# PCI_IRDY# 30,35,36 IN1
PCI_AD15 B6 D9 PCI_PAR 3 PCI_RST#
AD15 PAR PCI_PAR 30,35 OUT PCI_RST# 30,31,35
PCI_AD16 C11 G6 PCI_PCIRST# 2
AD16 PCIRST# IN2
G
PCI_AD17 A9 D16 PCI_DEVSEL#
AD17 DEVSEL# PCI_DEVSEL# 30,35
PCI_AD18 D11 A7 PCI_PERR# 74VHC08MTCX_NL_TSSOP14~D
PCI_PERR# 30,35
7
PCI_AD19 AD18 PERR# PCI_PLOCK#
B12 AD19 PLOCK# B7 PCI_PLOCK# 35
PCI_AD20 C12 F10 PCI_SERR#
+3.3V_RUN AD20 SERR# PCI_SERR# 30,35
PCI_AD21 D10 C16 PCI_STOP#
AD21 STOP# PCI_STOP# 30,35
PCI_AD22 C7 C9 PCI_TRDY#
AD22 TRDY# PCI_TRDY# 30,35 +3.3V_SUS
PCI_AD23 F13 A17 PCI_FRAME#
AD23 FRAME# PCI_FRAME# 30,35,36
1 2 PCI_PIRQA# PCI_AD24 E11
R450 8.2K_0402_5%~D PCI_AD25 AD24 PCI_PLTRST#
14
E13 AD25 PLTRST# AG24
1 2 PCI_PIRQB# PCI_AD26 E12 B10 CLK_PCI_ICH U33B
AD26 PCICLK CLK_PCI_ICH 6
R451 8.2K_0402_5%~D PCI_AD27 D8 G7 ICH_PME# PCI_PLTRST# 4
P
AD27 PME# ICH_PME# 38 IN1
1 2 PCI_PIRQC# PCI_AD28 A6 6 PLTRST1#
AD28 OUT PLTRST1# 10,51
R452 8.2K_0402_5%~D PCI_AD29 E8 5
AD29 IN2
G
1 2 PCI_PIRQD# PCI_AD30 D6
C R453 8.2K_0402_5%~D PCI_AD31 AD30 74VHC08MTCX_NL_TSSOP14~D C
A3
7
AD31
ICH_GPIO2_PIRQE#
1
R454
2
8.2K_0402_5%~D PCI_PIRQA# F9
Interrupt I/F F8 ICH_GPIO2_PIRQE#
35 PCI_PIRQA# PIRQA# PIRQE#/GPIO2 +3.3V_SUS
PCI_PIRQB# B5 G11 SB_WLAN_PCIE_RST#
PIRQB# PIRQF#/GPIO3 SB_WLAN_PCIE_RST# 34
PCI_PIRQC# C5 F12 SB_NB_PCIE_RST#
PIRQC# PIRQG#/GPIO4 SB_NB_PCIE_RST# 10
PCI_PIRQD#
14
30 PCI_PIRQD# A10 PIRQD# PIRQH#/GPIO5 B3 PCIE_MCARD2_DET# 34
U33C
ICH8M_BGA676~D 10
P
IN1 PLTRST2#
OUT 8 PLTRST2# 38,39
9 IN2
G
1 2 PCI_REQ0# 74VHC08MTCX_NL_TSSOP14~D
7
R458 8.2K_0402_5%~D
1 2 PCI_REQ1#
R459 8.2K_0402_5%~D
+3.3V_SUS
14
1 2 SB_LOM_PCIE_RST# U33D
R461 20K_0402_5%~D 13
P
SB_WWAN_PCIE_RST# IN1 PLTRST3#
1 2 OUT 11 PLTRST3# 28,34
R460 20K_0402_5%~D 12 IN2
G
1 2 SB_WLAN_PCIE_RST#
R601 20K_0402_5%~D 74VHC08MTCX_NL_TSSOP14~D
7
1 2 SB_NB_PCIE_RST#
R631 20K_0402_5%~D
PCI_GNT0# ICH_SPI_CS1#
23 ICH_SPI_CS1#
BIOS should not enable the internal
1
B PCI_GNT3# B
GPIO pull up resistor R462 R463
1
1K_0402_5%~D @ 1K_0402_5%~D
R477 2
2
1K_0402_5%~D
@
2
Place closely pin U19.A9

CLK_PCI_ICH
2
A16 away override strap. Boot BIOS Strap R464
@ 10_0402_5%~D
Low = A16 swap override enabled.
PCI_GNT3# PCI_GNT0# SPI_CS1# Boot BIOS Location
CLK_ICH_TERM 1
High = Default.
* 0 1 SPI
1 0 PCI 1
C652
@ 8.2P_0402_50V8J~D
2
om
1 1 LPC
A A
l.c
ai
tm
ho
f@
Title
ICH8(1/4)
in
xa
1.0
he
5 4 3 2 1
5 4 3 2 1
+RTC_CELL +RTC_CELL
1
R472 R475
332K_0402_1%~D 332K_0402_1%~D
2
ICH_INTVRMEN LAN100_SLP
2
@
R478 @ R476
0_0402_1% 0_0402_5%~D
D D
1
Package
9.6X4.06 mm
ICH8M Internal VR Enable Strap ICH8M LAN100 SLP Strap
C653
15P_0402_50V8J~D (Internal VR for VccSus1.05, VccSus1.5, VccCL1.5) (Internal VR for VccLAN1.05 and VccCL1.05)
2 1 ICH_RTCX1
ICH_INTVRMEN Low = Internal VR Disabled ICH_LAN100_SLP Low = Internal VR Disabled
1
High = Internal VR Enabled(Default) High = Internal VR Enabled(Default)
3
R467
Y4
32.768K_12.5P_1TJS125DJ4A420P~D 10M_0402_5%~D
2
+3.3V_RUN C654 U32A
15P_0402_50V8J~D R469 AG25 E5 LPC_LAD0
RTCX1 FWH0/LAD0 LPC_LAD0 28,38,39
2 1 1 2 ICH_RTCX2 AF24 F5 LPC_LAD1
RTCX2 FWH1/LAD1 LPC_LAD1 28,38,39
0_0402_5%~D G8 LPC_LAD2 +1.05V_VCCP
FWH2/LAD2 LPC_LAD2 28,38,39
+RTC_CELL 1 2 ICH_RTCRST# AF23 F6 LPC_LAD3
RTCRST# FWH3/LAD3 LPC_LAD3 28,38,39
R470 20K_0402_5%~D
IDE_IRQ INTRUDER# LPC_LFRAME#
RTC
1 2 1 2 AD22 C4
LPC
INTRUDER# FWH4/LFRAME# LPC_LFRAME# 28,38,39
56_0402_1%~D
56_0402_1%~D
R490 8.2K_0402_5%~D R471 1M_0402_5%~D
1
ICH_INTVRMEN AF25 G9 LPC_LDRQ0#
INTVRMEN LDRQ0# LPC_LDRQ0# 38
R473
R474
LAN100_SLP AD21 E6 LPC_LDRQ1#
LAN100_SLP LDRQ1#/GPIO23 LPC_LDRQ1# 38
1 2 B24 AF13 SIO_A20GATE @
1 2 GLAN_CLK A20GATE SIO_A20GATE 39
AG26 H_A20M# @
H_A20M# 7
2
A20M#
D22 LAN_RSTSYNC
AF26 H_DPRSTP#
DPRSTP# H_DPRSTP# 8,10,48
C21 AE26 H_DPSLP#
C LAN_RXD0 DPSLP# H_DPSLP# 8 C
Close to U19 CMOS_CLR @SHORT PADS~D B21
LAN / GLAN
LAN_RXD1 H_FERR#
C22 LAN_RXD2 FERR# AD24 H_FERR# 7
26 ICH_AZ_CODEC_SDOUT 1 2 ICH_AZ_SDOUT C655
R493 33_0402_5%~D 1 2 D21 AG29 H_PW RGOOD
LAN_TXD_0 CPUPWRGD/GPIO49 H_PWRGOOD 8
E20 LAN_TXD_1
1U_0603_10V4Z~D +1.5V_RUN_PCIE_ICH C20 AF27 H_IGNNE#
LAN_TXD_2 IGNNE# H_IGNNE# 7
26 ICH_AZ_CODEC_SYNC 1 2 I CH_AZ_SYNC
R494 33_0402_5%~D R480 AH21 AE24 H_INIT#
CPU
GLAN_DOCK#/GPIO13 INIT# H_INIT# 7
C656 24.9_0402_1%~D AC20 H_INTR +1.05V_VCCP
INTR H_INTR 7
27P_0402_50V8J~D 1 2 D25 AH14 SIO_RCIN#
GLAN_COMPI RCIN# SIO_RCIN# 39
26 ICH_AZ_CODEC_RST# 1 2 ICH_AZ_RST# 2 1 C25 GLAN_COMPO
1
R495 33_0402_5%~D R481 33_0402_5%~D AD23 H_NMI
NMI H_NMI 7
33 ICH_AZ_MDC_BITCLK 1 2 ICH_AZ_BITCLK AJ16 HDA_BIT_CLK SMI# AG28 H_SMI#
H_SMI# 7
R482
R496
33 ICH_AZ_MDC_SYNC 1 2 I CH_AZ_SYNC AJ15 HDA_SYNC 56_0402_5%~D
1 2 ICH_AZ_BITCLK R483 33_0402_5%~D AA24 H_STPCLK#
26 ICH_AZ_CODEC_BITCLK STPCLK# H_STPCLK# 7
33 ICH_AZ_MDC_RST# 1 2 ICH_AZ_RST# AE14 +3.3V_RUN
2
33_0402_5%~D R484 33_0402_5%~D HDA_RST# THRMTRIP_ICH#
1 THRMTRIP# AE27
C660 ICH_AZ_CODEC_SDIN0 AJ17
26 ICH_AZ_CODEC_SDIN0 HDA_SDIN0
0.1U_0402_16V4Z~D
ICH_AZ_MDC_SDIN1 AH17 AA23 ICH_TP8 T12PAD~D R465
33 ICH_AZ_MDC_SDIN1 HDA_SDIN1 TP8
27P_0402_50V8J~D AH15 SIO_A20GATE 2 1
IHDA
2 HDA_SDIN2 1
AD13 V1 IDE_DD0
HDA_SDIN3 DD0
C470
U2 IDE_DD1 10K_0402_5%~D
DD1
33 ICH_AZ_MDC_SDOUT 1 2 ICH_AZ_SDOUT AE13 HDA_SDOUT DD2 V3 IDE_DD2
R487 33_0402_5%~D IDE_DD3 2 R466
DD3 T1
AE10 V4 IDE_DD4 SIO_RCIN# 2 1
HDA_DOCK_EN#/GPIO33 DD4 IDE_DD5
AG14 HDA_DOCK_RST#/GPIO34 DD5 T5
AB2 IDE_DD6 10K_0402_5%~D
SATA_ACT#_R DD6 IDE_DD7
43 SATA_ACT#_R AF10 SATALED# DD7 T6
T3 IDE_DD8
PSATA_IRX_DTX_N0_C DD8 IDE_DD9
25 PSATA_IRX_DTX_N0_C AF6 SATA0RXN DD9 R2
PSATA_IRX_DTX_P0_C AF5 T4 IDE_DD10 +1.05V_VCCP
25 PSATA_IRX_DTX_P0_C SATA_TX0-_N0 SATA0RXP DD10 IDE_DD11 R468
AH5 SATA0TXN DD11 V6
B SATA_TX0+_P0 IDE_DD12 H_FERR# B
AH6 SATA0TXP DD12 V5 2 1
2 1 U1 IDE_DD13
25 PSATA_ITX_DRX_N0 DD13
C658 3900P_0402_50V7K~D AG3 V2 IDE_DD14 56_0402_5%~D
IDE
SATA1RXN DD14 IDE_DD15
25 PSATA_ITX_DRX_P0 2 1 AG4 SATA1RXP DD15 U6
C659 3900P_0402_50V7K~D AJ4 IDE_DD[0..15] 25
SATA1TXN IDE_DA0
AJ3 SATA1TXP DA0 AA4 IDE_DA0 25
SATA
AA1 IDE_DA1
DA1 IDE_DA2 IDE_DA1 25
AF2 SATA2RXN DA2 AB3 IDE_DA2 25
AF1 SATA2RXP
AE4 Y6 IDE_DCS1#
SATA2TXN DCS1# IDE_DCS1# 25
AE3 Y5 IDE_DCS3#
SATA2TXP DCS3# IDE_DCS3# 25
CLK_PCIE_SATA# AB7 W4 IDE_DIOR#
6 CLK_PCIE_SATA# SATA_CLKN DIOR# IDE_DIOR# 25
CLK_PCIE_SATA AC6 W3 IDE_DIOW#
6 CLK_PCIE_SATA SATA_CLKP DIOW# IDE_DIOW# 25
Y2 IDE_DDACK#
DDACK# IDE_DDACK# 25
AG1 Y3 IDE_IRQ
SATARBIAS# IDEIRQ IDE_IRQ 25
1 2 AG2 Y1 IDE_ DIORDY
SATARBIAS IORDY IDE_DIORDY 25
R491 24.9_0402_1%~D W5 IDE_DDREQ
DDREQ IDE_DDREQ 25
Within 500 mils ICH8M_BGA676~D
+3.3V_RUN
1
XOR Chain Entrance Strap

R385
1K_0402_5%~D
ICH RSVD HDA SDOUT Description @
2
A ICH_AZ_SDOUT A
0 0 RSVD
ICH_RSVD 23
1
0 1 Enter XOR Chain

R386
1K_0402_5%~D DELL CONFIDENTIAL/PROPRIETARY
1 0 Normal Operation (Default) @
2
1 1 Set PCIE port config bit 1 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ICH8(2/4)
LA-3301P
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN +3.3V_SUS +3.3V_RUN

ICH_CL_PWROK 1 2
8.2K_0402_5%~D
1 2 IMVP_PWRGD 1 2 ICH_CL_RST1# R42 1M_0402_1%~D
1
R411 @ 2.2K_0402_5%~D @ R514 10K_0402_5%~D
1 2 MCH_ICH_SYNC# 1 2 ICH_SMLINK0 ICH_LAN_RST# 1 2
R500
R524 @ 10K_0402_5%~D R503 10K_0402_5%~D R834 10K_0402_5%~D
2 1 RSV_THRM# 2 1 ICH_SMLINK1
@
R497 10K_0402_5%~D R502 10K_0402_5%~D DPRSLPVR 1 2
2
IRQ_SERIRQ U32C
2 1 1 2 I CH_RI# R501 100K_0402_5%~D
R504 10K_0402_5%~D R506 10K_0402_5%~D ICH_SMBCLK AJ26 AJ12 SATA0GP
28,34 ICH_SMBCLK SMBCLK SATA0GP/GPIO21
1 2 RSVD_GPIO38 1 2 SIO_EXT_SCI# ICH_SMBDATA AD19 AJ10
SATA
GPIO
SMB
R517 10K_0402_5%~D R516 10K_0402_5%~D 28,34 ICH_SMBDATA ICH_CL_RST1# SMBDATA SATA1GP/GPIO19
AG21 LINKALERT# SATA2GP/GPIO36 AF11
1 2 RSVD_GPIO39 1 2 ICH_PCIE_WAKE# ICH_SMLINK0 AC17 AG11
R523 10K_0402_5%~D R521 1K_0402_5%~D ICH_SMLINK1 SMLINK0 SATA3GP/GPIO37 ICH_PWRGD
AE19 SMLINK1 1 2
D RSVD_GPIO48 D
1 2 1 2 ICH_SMBCLK CLK14 AG9 CLK_ICH_14M
CLK_ICH_14M 6
R512 10K_0402_5%~D
R528 10K_0402_5%~D R498 2.2K_0402_5%~D I CH_RI# CLK_ICH_48M
1 2 SPKR 1 2 ICH_SMBDATA
AF17 RI# clocks CLK48 G5 CLK_ICH_48M 6
ICH_RSMRST# 1 2
R115 @ 1K_0402_5%~D R499 2.2K_0402_5%~D F4 D3 ICH_SUSCLK T13 PAD~D R515 10K_0402_5%~D
SUS_STAT#/LPCPD# SUSCLK
1 2 EC_ME_ALERT 7,38 ITP_DBRESET#
ITP_DBRESET# AD15 SYS_RESET#
R690 8.2K_0402_5%~D AG23 SIO_SLP_S3# SIO_SLP_S3# 39
SLP_S3#
1 2 LOM_ICH_SMBALERT# PM_BMBUSY# AG12 AF21
SYS / GPIO
10 PM_BMBUSY# BMBUSY#/GPIO0 SLP_S4#
R807 10K_0402_5%~D AD18 SIO_SLP_S5#
SLP_S5# SIO_SLP_S5# 39
28,39 LOM_SMB_ALERT# 1 2LOM_ICH_SMBALERT# AG22 SMBALERT#/GPIO11
No Reboot Strap @ R793 0_0402_5%~D AH27 Place closely pin U19.AC1
H_STP_PCI# S4_STATE#/GPIO26
6 H_STP_PCI# AE20 STP_PCI#/GPIO15
H_STP_CPU# AG18 AE23 ICH_PWRGD
6 H_STP_CPU# STP_CPU#/GPIO25 PWROK ICH_PWRGD 10,42
Low = Default CLK_ICH_14M
Power MGT
SPKR 30,38,39 CLKRUN# CLKRUN# AH11 AJ14 DPRSLPVR
CLKRUN#/GPIO32 DPRSLPVR/GPIO16 DPRSLPVR 10,48
1
High = No Reboot ICH_PCIE_WAKE#AE17 AE21 ICH_BATLOW# 2 1 +3.3V_SUS
38 ICH_PCIE_WAKE# WAKE# BATLOW#
IRQ_SERIRQ AF12 R518 8.2K_0402_5%~D R510
28,30,38,39 IRQ_SERIRQ SERIRQ
Filters are to supress RSV_THRM# AC13 C2 SIO_PWRBTN#
THRM# PWRBTN# SIO_PWRBTN# 39
@ 10_0402_5%~D
+3.3V_SUS 14MHz noise sourced IMVP_PWRGD AJ20 AH20 ICH_LAN_RST#
39,42,48 IMVP_PWRGD
2
VRMPWRGD LAN_RST#
from the ICH
R816 ICH_TP7 ICH_RSMRST#
1 2 SIO_EXT_SMI# 0_0603_5%~D
PAD~D T15 AJ22 TP7 RSMRST# AG27 ICH_RSMRST# 39 Non-iAMT 1
C661
R509 10K_0402_5%~D 1 2 AJ8 E1 CLK_PWRGD
25 USB_IDE# TACH1/GPIO1 CK_PWRGD CLK_PWRGD 6
AJ9 @ 4.7P_0402_50V8C~D
+3.3V_RUN TACH2/GPIO6 ICH_CL_PWROK 2
38 SIO_EXT_WAKE# 1 2 AH9 TACH3/GPIO7 CLPWROK E3 ICH_CL_PWROK 10,39
R817 0_0603_5%~D SIO_EXT_SMI# AE16
39 SIO_EXT_SMI# GPIO8
R819 0_0603_5%~D SIO_EXT_SCI# AC19 AJ25
39 SIO_EXT_SCI# GPIO12 SLP_M#
1
34 PCIE_MCARD1_DET# 1 2 AG8 TACH0/GPIO17

R505 1 2 AH12 F23 CL_CLK0
GPIO
Controller Link
34 USB_MCARD1_DET# GPIO18 CL_CLK0 CL_CLK0 10
8.2K_0402_5%~D R820 4.7K_0603_5%~D AE11 AE18
GPIO20 CL_CLK1
34 USB_MCARD2_DET# 1 2 AG10 SCLOCK/GPIO22
C R818 0_0603_5%~D RSVD_GPIO27 CL_DATA0 C
PAD~D T24 AH25 F22 CL_DATA0 10 Place closely pin U19.B2
2
IDE_RST_MOD QRT_STATE0/GPIO27 CL_DATA0

25 IDE_RST_MOD AD16 QRT_STATE1/GPIO28 CL_DATA1 AF19
C875 47P_0402_50V8J~D
C876 47P_0402_50V8J~D
C878 47P_0402_50V8J~D
C877 47P_0402_50V8J~D
CLKRUN# SATA_CLKREQ# AG13

6 SATA_CLKREQ# SATACLKREQ#/GPIO35
PAD~D T3 RSVD_GPIO38 AF9 D24 CL_VREF0_ICH CLK_ICH_48M
SLOAD/GPIO38 CL_VREF0
47P_0402_50V8J~D
Option to " Disable " PAD~D T14 RSVD_GPIO39 AJ11 AH23 T86 PAD~D
SDATAOUT0/GPIO39 CL_VREF1
1
10_0402_5%~D
RSVD_GPIO48 AD10
clkrun. Pulling it SDATAOUT1/GPIO48
1
R508
AJ23 ICH_CL_RST0#
SPKR CL_RST# ICH_CL_RST0# 10 R520
down 26 SPKR AD9 SPKR
1 1 1 1 1 AJ27
MISC
will keep the clks MEM_LED/GPIO24
C874
@ MCH_ICH_SYNC# AJ13 AJ24 @ 10_0402_5%~D

10 MCH_ICH_SYNC#
2
MCH_SYNC# ME_EC_ALERT/GPIO10
running. AF22 EC_ME_ALERT
2
ICH_RSVD EC_ME_ALERT/GPIO14
22 ICH_RSVD AJ21 TP3 WOL_EN/GPIO9 AG19
@ 2 2 2 2 2
1
ICH8M_BGA676~D C663
@ @ @ @
@ 4.7P_0402_50V8C~D
2
U32D
PCIE_IRX_WANTX_N1 P27 V27 DMI_MTX_IRX_N0
34 PCIE_IRX_WANTX_N1 PERN1 DMI0RXN DMI_MTX_IRX_N0 10
PCIE_IRX_WANTX_P1 P26 V26 DMI_MTX_IRX_P0
Direct Media Interface

34 PCIE_IRX_WANTX_P1 PERP1 DMI0RXP DMI_MTX_IRX_P0 10
MiniWWAN (Mini Card 1)---> C664 1 2 0.1U_0402_10V7K~D PCIE_ITX_WANRX_N1 N29 U29 DMI_MRX_ITX_N0
34 PCIE_ITX_WANRX_N1_C PETN1 DMI0TXN DMI_MRX_ITX_N0 10
PCIE_ITX_WANRX_P1 N28 U28 DMI_MRX_ITX_P0
PETP1 DMI0TXP DMI_MRX_ITX_P0 10
C666 1 2 0.1U_0402_10V7K~D
34 PCIE_ITX_WANRX_P1_C PCIE_IRX_WLANTX_N2 DMI_MTX_IRX_N1
34 PCIE_IRX_WLANTX_N2 M27 PERN2 DMI1RXN Y27 DMI_MTX_IRX_N1 10
+3.3V_SUS PCIE_IRX_WLANTX_P2 M26 Y26 DMI_MTX_IRX_P1
34 PCIE_IRX_WLANTX_P2 PERP2 DMI1RXP DMI_MTX_IRX_P1 10
MiniWLAN (Mini Card 2)---> C667 1 2 0.1U_0402_10V7K~D PCIE_ITX_WLANRX_N2 L29 W29 DMI_MRX_ITX_N1
34 PCIE_ITX_WLANRX_N2_C PCIE_ITX_WLANRX_P2 L28
PETN2 DMI1TXN
W28 DMI_MRX_ITX_P1
DMI_MRX_ITX_N1 10 Non-iAMT +3.3V_RUN
PCI - Express
1 2 USB_OC2_3# C668 1 2 0.1U_0402_10V7K~D
R702 10K_0402_5%~D 34 PCIE_ITX_WLANRX_P2_C DMI_MTX_IRX_N2
K27 PERN3 DMI2RXN AB26 DMI_MTX_IRX_N2 10
1
1 2 USB_OC4# K26 AB25 DMI_MTX_IRX_P2
PERP3 DMI2RXP DMI_MTX_IRX_P2 10
R703 10K_0402_5%~D J29 AA29 DMI_MRX_ITX_N2 R519
PETN3 DMI2TXN DMI_MRX_ITX_N2 10
1 2 USB_OC0_1# J28 AA28 DMI_MRX_ITX_P2 3.24K_0402_1%~D
B PETP3 DMI2TXP DMI_MRX_ITX_P2 10 B
R704 10K_0402_5%~D
1 2 USB_OC5# H27 AD27 DMI_MTX_IRX_N3
DMI_MTX_IRX_N3 10
2
R705 10K_0402_5%~D PERN4 DMI3RXN DMI_MTX_IRX_P3 CL_VREF0_ICH
H26 PERP4 DMI3RXP AD26 DMI_MTX_IRX_P3 10
0.1U_0402_16V4Z~D
453_0402_1%~D
G29 AC29 DMI_MRX_ITX_N3
PETN4 DMI3TXN DMI_MRX_ITX_N3 10
1
1 2 USB_OC6# G28 AC28 DMI_MRX_ITX_P3
R522
R706 10K_0402_5%~D 1
C662
1 2 USB_OC8# F27 T26 CLK_PCIE_ICH#
PERN5 DMI_CLKN CLK_PCIE_ICH# 6
R707 10K_0402_5%~D F26 T25 CLK_PCIE_ICH Within 500 mils
PERP5 DMI_CLKP CLK_PCIE_ICH 6
1 2 USB_OC9# E29
2
R708 10K_0402_5%~D PETN5 R529 24.9_0402_1%~D 2
E28 PETP5 DMI_ZCOMP Y23
1 2 USB_OC7# Y24 DMI_IRCOMP 1 2 +1.5V_RUN_PCIE_ICH
R709 10K_0402_5%~D PCIE_RX6-/GLAN_RX- DMI_IRCOMP
28 PCIE_RX6-/GLAN_RX- D27 PERN6/GLAN_RXN
PCIE_RX6+/GLAN_RX+ USBP0-
GIGA LAN --->
28 PCIE_RX6+/GLAN_RX+
C669 1 2 0.1U_0402_10V7K~D GLAN_TXN_C
D26
C29
PERP6/GLAN_RXP USBP0N G3
G2 USBP0+
USBP0- 32 ----->Side Top
28 PCIE_TX6-/GLAN_TX- PETN6/GLAN_TXN USBP0P USBP0+ 32
C670 1 2 0.1U_0402_10V7K~D GLAN_TXP_C USBP1-
28 PCIE_TX6+/GLAN_TX+ C28 PETP6/GLAN_TXP USBP1N H5
H4 USBP1+
USBP1- 32 ----->Side Bottom
USBP1P USBP1+ 32
ICH_EC_SPI_CLK R530 2 15_0402_5%~D USBP2-
39 ICH_EC_SPI_CLK ICH_SPI_CS0# R531
1
1 2 15_0402_5%~D
C23
B23
SPI_CLK USBP2N H2
H1 USBP2+
USBP2- 32 ----->Rear Left
39 ICH_SPI_CS0# SPI_CS0# USBP2P USBP2+ 32
ICH_SPI_CS1# R532 2 15_0402_5%~D USBP3-
1 E22 J3 ----->Rear Right
SPI
21 ICH_SPI_CS1# SPI_CS1# USBP3N USBP3- 32

J2 USBP3+
USBP3P USBP3+ 32
ICH_EC_SPI_DO R763 2 15_0402_5%~D USBP4-
39 ICH_EC_SPI_DO ICH_EC_SPI_DIN
1 D23
F21
SPI_MOSI USBP4N K5
K4 USBP4+
USBP4- 31 ----->Smart Card
39 ICH_EC_SPI_DIN SPI_MISO USBP4P USBP4+ 31
USBP5-
USB_OC0_1# AJ19
USBP5N K2
K1 USBP5+
USBP5- 40 ----->Biometric
32 USB_OC0_1# OC0# USBP5P USBP5+ 40
USBP6-
USB_OC2_3#
AG16 OC1#/GPIO40 USBP6N L3
USBP6+
USBP6- 30 ----->Card Bus
32 USB_OC2_3# AG15 OC2#/GPIO41 USB USBP6P L2
USBP7-
USBP6+ 30
+3.3V_RUN Non-iAMT AE15 OC3#/GPIO42 USBP7N M5 USBP7- 40 ----->Blue Tooth
2.2K_0402_5%~D
2.2K_0402_5%~D
USB_OC4# AF15 M4 USBP7+

OC4#/GPIO43 USBP7P USBP7+ 40
1
USB_OC5# USBP8-
AG17 OC5#/GPIO29 USBP8N M2 USBP8- 36 ----->Dock
R99
USB_OC6# AD12 M1 USBP8+

OC6#/GPIO30 USBP8P USBP8+ 36
R278
USB_OC7# USBP9-
om
USB_OC8#
AJ18
AD14
OC7#/GPIO31 USBP9N N3
N2 USBP9+
USBP9- 34 ----->WWAN
A OC8# USBP9P USBP9+ 34 A
USB_OC9# AH18
2
OC9#
l.c
F2 USBRBIAS 1 2
ICH_SMBDATA MEM_SDATA USBRBIAS# R533 22.6_0402_1%~D
D
1 3 MEM_SDATA 16,17 F3
ai
USBRBIAS
tm
Q21 ICH8M_BGA676~D Within 500 mils
2N7002W-7-F_SOT323-3~D DELL CONFIDENTIAL/PROPRIETARY
G
2
ho
+3.3V_RUN
2
G
f@
ICH_SMBCLK MEM_SCLK TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
1 3 MEM_SCLK 16,17 ICH8(3/4)
in
D
Q27 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
xa
2N7002W-7-F_SOT323-3~D PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-3301P
he
Date: Friday, March 02, 2007 Sheet 23 of 58
5 4 3 2 1
5 4 3 2 1
+RTC_CELL +1.05V_VCCP
D4
1U_0603_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2 +1.5V_RUN
+5V_RUN +3.3V_RUN R182
1 1 1 U32E
C200
C671
C672
+1.05V_VCCP 1 1 2
U32F A23 VSS[001] VSS[099] K7
1
2
3 10_0805_5%~D A5 L1
R534 D20 2 2 2 VSS[002] VSS[100]
AD25 VCCRTC VCC1_05[01] A13 AA2 VSS[003] VSS[101] L13
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
VCC1_05[02] B13 AA7 VSS[004] VSS[102] L15
100_0402_5%~D RB751V_SOD323~D ICH_V5REF_RUN A16 C13 A25 L26
V5REF[1] VCC1_05[03] MMBD4148-7-F_SOT23-3~D VSS[005] VSS[103]
T7 C14 1 1 AB1 L27
2
1 V5REF[2] VCC1_05[04] VSS[006] VSS[104]

+1.5V_RUN +1.5V_RUN_PCIE_ICH
C673
C674
ICH_V5REF_RUN D14 AB24 L4
D ICH_V5REF_SUS VCC1_05[05] VSS[007] VSS[105] D
1 G4 V5REF_SUS VCC1_05[06] E14 AC11 VSS[008] VSS[106] L5
C675 L43 F14 AC14 M12
+1.5V_RUN_PCIE_ICH VCC1_05[07] 2 2 VSS[009] VSS[107]
1 2 AA25 VCC1_5_B[01] VCC1_05[08] G14 AC25 VSS[010] VSS[108] M13
0.1U_0402_16V4Z~D BLM21PG600SN1D_0805~D AA26 L11 AC26 M14
2 VCC1_5_B[02] VCC1_05[09] VSS[011] VSS[109]
AA27 VCC1_5_B[03] VCC1_05[10] L12 AC27 VSS[012] VSS[110] M15
+1.5V_RUN
220U_D2_4VY_R15M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
2.2U_0603_6.3V6K~D
1 AB27 L14 L44 AD17 M16
VCC1_5_B[04] VCC1_05[11] BLM18PG181SN1_0603~D VSS[013] VSS[111]
1 1 1 AB28 VCC1_5_B[05] VCC1_05[12] L16 AD20 VSS[014] VSS[112] M17
C677
C678
C679
C676
+ AB29 L17 1 2 2 1 AD28 M23
VCC1_5_B[06] VCC1_05[13] VSS[015] VSS[113]
0.01U_0402_16V7K~D
10U_0805_4VAM~D
D28 L18 R535 AD29 M28
CORE
VCC1_5_B[07] VCC1_05[14] 1_0603_1%~D VSS[016] VSS[114]
D29 VCC1_5_B[08] VCC1_05[15] M11 1 1 AD3 VSS[017] VSS[115] M29
2 2 2 2
C680
C681
E25 VCC1_5_B[09] VCC1_05[16] M18 AD4 VSS[018] VSS[116] M3
+5V_SUS +3.3V_SUS
E26 VCC1_5_B[10] VCC1_05[17] P11 AD6 VSS[019] VSS[117] N1
E27 P18 AE1 N11
Non-iAMT F24
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_05[18]
VCC1_05[19] T11
2 2
AE12
VSS[020]
VSS[021]
VSS[118]
VSS[119] N12
1
F25 VCC1_5_B[13] VCC1_05[20] T18 AE2 VSS[022] VSS[120] N13

R536 D21 G24 U11 AE22 N14
VCC1_5_B[14] VCC1_05[21] VSS[023] VSS[121]
H23 VCC1_5_B[15] VCC1_05[22] U18 AD1 VSS[024] VSS[122] N15
10_0402_5%~D RB751V_SOD323~D H24 V11 +1.25V_RUN AE25 N16
VCC1_5_B[16] VCC1_05[23] VSS[025] VSS[123]
0.1U_0402_16V4Z~D
22U_0805_6.3V6M~D
J23 V12 AE5 N17
2
ICH_V5REF_SUS VCC1_5_B[17] VCC1_05[24] +1.05V_VCCP VSS[026] VSS[124]

J24 VCC1_5_B[18] VCC1_05[25] V14 1 1 AE6 VSS[027] VSS[125] N18
VCCA3GP
C202
C682
1 K24 VCC1_5_B[19] VCC1_05[26] V16 AE9 VSS[028] VSS[126] N26
C683 K25 V17 AF14 N27
VCC1_5_B[20] VCC1_05[27] VSS[029] VSS[127]
4.7U_0603_6.3V6M~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
L23 VCC1_5_B[21] VCC1_05[28] V18 AF16 VSS[030] VSS[128] N4
0.1U_0402_16V4Z~D 2 2
L24 VCC1_5_B[22] AF18 VSS[031] VSS[129] N5
2
L25 VCC1_5_B[23] VCCDMIPLL R29 1 1 1 AF3 VSS[032] VSS[130] N6
C684
C685
C686
M24 VCC1_5_B[24] AF4 VSS[033] VSS[131] P12
M25 VCC1_5_B[25] VCC_DMI[1] AE28 AG5 VSS[034] VSS[132] P13
N23 VCC1_5_B[26] VCC_DMI[2] AE29 AG6 VSS[035] VSS[133] P14
2 2 2
N24 VCC1_5_B[27] AH10 VSS[036] VSS[134] P15
N25 VCC1_5_B[28] V_CPU_IO[1] AC23 AH13 VSS[037] VSS[135] P16
P24 VCC1_5_B[29] V_CPU_IO[2] AC24 AH16 VSS[038] VSS[136] P17
P25 VCC1_5_B[30] AH19 VSS[039] VSS[137] P23
C +1.5V_RUN R24 AF29 AH2 P28 C
+1.5V_RUN_SATAPLL VCC1_5_B[31] VCC3_3[01] +3.3V_RUN VSS[040] VSS[138]
L45 R25 AF28 P29
VCC1_5_B[32] VSS[041] VSS[139]
0.1U_0402_16V4Z~D
R537 10UH_LB2012T100MR_20%_0805~D R26 AD2 +3.3V_RUN 1 AH22 R11
+VCCSATAPLLR 1 VCC1_5_B[33] VCC3_3[02] VSS[042] VSS[140]
1 2 2 R27 VCC1_5_B[34] AH24 VSS[043] VSS[141] R12
0.1U_0402_16V4Z~D
C687
T23 VCC1_5_B[35] VCC3_3[03] AC8 +3.3V_RUN 1 AH26 VSS[044] VSS[142] R13
10U_0805_4VAM~D
1U_0603_10V4Z~D
VCCP_CORE
0_0603_5%~D T24 AD8 AH3 R14
VCC1_5_B[36] VCC3_3[04] 2 VSS[045] VSS[143]
C688
1 1 T27 VCC1_5_B[37] VCC3_3[05] AE8 AH4 VSS[046] VSS[144] R15
C689
C690
T28 VCC1_5_B[38] VCC3_3[06] AF8 AH8 VSS[047] VSS[145] R16

+3.3V_RUN 2
T29 VCC1_5_B[39] AJ5 VSS[048] VSS[146] R17
U24 VCC1_5_B[40] VCC3_3[07] AA3 B11 VSS[049] VSS[147] R18
2 2
U25 VCC1_5_B[41] VCC3_3[08] U7 B14 VSS[050] VSS[148] R28
V23 V7 B17 R4
IDE
VCC1_5_B[42] VCC3_3[09] 1 VSS[051] VSS[149]
V24 W1 C691 B2 T12
VCC1_5_B[43] VCC3_3[10] 0.1U_0402_16V4Z~D VSS[052] VSS[150]
V25 VCC1_5_B[44] VCC3_3[11] W6 B20 VSS[053] VSS[151] T13
W25 VCC1_5_B[45] VCC3_3[12] W7 B22 VSS[054] VSS[152] T14
2 +3.3V_RUN +3.3V_RUN
Y25 VCC1_5_B[46] VCC3_3[13] Y7 B8 VSS[055] VSS[153] T15
C24 VSS[056] VSS[154] T16
AJ6 VCCSATAPLL VCC3_3[14] A8 C26 VSS[057] VSS[155] T17
VCC3_3[15] B15 C27 VSS[058] VSS[156] T2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
AE7 VCC1_5_A[01] VCC3_3[16] B18 1 1 1 1 C6 VSS[059] VSS[157] U12
AF7 B4 C695 D12 U13
VCC1_5_A[02] VCC3_3[17] VSS[060] VSS[158]
ARX
C692
C693
C694
1 AG7 VCC1_5_A[03] VCC3_3[18] B9 D15 VSS[061] VSS[159] U14
AH7 C15 0.1U_0402_16V4Z~D D18 U15
PCI
C696 VCC1_5_A[04] VCC3_3[19] 2 2 2 2 VSS[062] VSS[160]
AJ7 VCC1_5_A[05] VCC3_3[20] D13 D2 VSS[063] VSS[161] U16
1U_0603_10V4Z~D D5 D4 U17
2 VCC3_3[21] VSS[064] VSS[162]
AC1 VCC1_5_A[06] VCC3_3[22] E10 E21 VSS[065] VSS[163] U23
AC2 VCC1_5_A[07] VCC3_3[23] E7 E24 VSS[066] VSS[164] U26
ATX
AC3 F11 E4 U27
C697
1
AC4
VCC1_5_A[08]
VCC1_5_A[09]
VCC3_3[24] Non-iAMT E9
VSS[067]
VSS[068]
VSS[165]
VSS[166] U3
1U_0603_10V4Z~D AC5 AC12 +3.3V_SUS F15 U5
VCC1_5_A[10] VCCHDA VSS[069] VSS[167]
E23 VSS[070] VSS[168] V13
2
AC10 VCC1_5_A[11] VCCSUSHDA AD11 F28 VSS[071] VSS[169] V15
B B
AC9 VCC1_5_A[12] 1 F29 VSS[072] VSS[170] V28
J6 TP_VCCSUS1.05_INT_ICH1 T17PAD~D C698 F7 V29
VCCSUS1_05[1] TP_VCCSUS1.05_INT_ICH2 VSS[073] VSS[171]
1 AA5 VCC1_5_A[13] VCCSUS1_05[2] AF20 T18PAD~D G1 VSS[074] VSS[172] W2
C699 AA6 0.1U_0402_16V4Z~D E2 W26
VCC1_5_A[14] VCCSUS1_5_ICH_1 2 VSS[075] VSS[173]
VCCSUS1_5[1] AC16 G10 VSS[076] VSS[174] W27
0.1U_0402_16V4Z~D T19
G12 VCC1_5_A[15] G13 VSS[077] VSS[175] Y28
2 VCCSUS1_5_ICH_2
G17 VCC1_5_A[16] VCCSUS1_5[2] J7 G19 VSS[078] VSS[176] Y29
T20
H7 VCC1_5_A[17] G23 VSS[079] VSS[177] Y4
VCCSUS3_3[01] C3 +3.3V_SUS G25 VSS[080] VSS[178] AB4
AC7 VCC1_5_A[18] G26 VSS[081] VSS[179] AB23
0.022U_0402_16V7K~D
0.022U_0402_16V7K~D
1 AD7 VCC1_5_A[19] VCCSUS3_3[02] AC18 1 1 G27 VSS[082] VSS[180] AB5
C700
VCCPSUS
VCCSUS3_3[03] AC21 H25 VSS[083] VSS[181] AB6
C701
C702
D1 VCCUSBPLL VCCSUS3_3[04] AC22 H28 VSS[084] VSS[182] AD5
0.1U_0402_16V4Z~D AG20 H29 U4
2 VCCSUS3_3[05] 2 2 VSS[085] VSS[183]
USB CORE
F1 AH28 H3 W24
Non-iAMT L6
VCC1_5_A[20]
VCC1_5_A[21]
VCCSUS3_3[06]
H6
VSS[086]
VSS[087]
VSS[184]
L7 VCC1_5_A[22] VCCSUS3_3[07] P6 J1 VSS[088] VSS_NCTF[01] A1
M6 P7 +3.3V_SUS J25 A2
+3.3V_RUN VCC1_5_A[23] VCCSUS3_3[08] VSS[089] VSS_NCTF[02]
M7 VCC1_5_A[24] VCCSUS3_3[09] C1 J26 VSS[090] VSS_NCTF[03] A28
1 VCCSUS3_3[10] N7 J27 VSS[091] VSS_NCTF[04] A29
W23 P1 J4 AH1
VCCPUSB
+1.5V_RUN VCC1_5_A[25] VCCSUS3_3[11] VSS[092] VSS_NCTF[05]
0.1U_0402_16V4Z~D
C703 P2 1 J5 AH29
0.1U_0402_16V4Z~D TP_VCCLAN1.05_INT_ICH1 F17 VCCSUS3_3[12] VSS[093] VSS_NCTF[06]
P3 K23 AJ1
2 PAD~DT21 VCCLAN1_05[1] VCCSUS3_3[13] Non-iAMT VSS[094] VSS_NCTF[07]
C704
PAD~DT22 TP_VCCLAN1.05_INT_ICH2 G18 P4 K28 AJ2
VCCLAN1_05[2] VCCSUS3_3[14] VSS[095] VSS_NCTF[08]
VCCSUS3_3[15] P5 K29 VSS[096] VSS_NCTF[09] AJ28
2
F19 R1 K3 AJ29
Non-iAMT G20
VCCLAN3_3[1]
VCCLAN3_3[2]
VCCSUS3_3[16]
VCCSUS3_3[17] R3 K6
VSS[097]
VSS[098]
VSS_NCTF[10]
VSS_NCTF[11] B1
VCCSUS3_3[18] R5 VSS_NCTF[12] B29
+1.5V_RUN A24 VCCGLANPLL VCCSUS3_3[19] R6
0.1U_0402_16V4Z~D
GLAN POWER
1 ICH8M_BGA676~D
Place Cap as close A26 G22 VCCCL1_05_ICH
VCCGLAN1_5[1] VCCCL1_05 T23
C705
to A24 as possible A27 VCCGLAN1_5[2]

A +1.5V_RUN_PCIE_ICH B26 A22 A
2 VCCGLAN1_5[3] VCCCL1_5
B27 VCCGLAN1_5[4]
B28 VCCGLAN1_5[5] VCCCL3_3[1] F20 +3.3V_RUN
VCCCL3_3[2] G21
B25
1
+3.3V_RUN VCCGLAN3_3 Non-iAMT DELL CONFIDENTIAL/PROPRIETARY
ICH8M_BGA676~D
C709
4.7U_0603_6.3V6M~D Compal Electronics, Inc.
2 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ICH8(4/4)
LA-3301P
5 4 3 2 1
5 4 3 2 1
+5V_ALW
1 +15V_ALW
1
+3.3V_ALW2
R619
100K_0402_5%~D
1
2
5
6
2 JMOD R618 D Q48
71
72
2
+5V_MOD 100K_0402_5%~D G SI3456BDV-T1-E3_TSOP6~D
2 MOD_EN 3
G
S
2
+5V_MOD
3 1
4
1
10U_0805_10V4Z~D
0.1U_0603_50V4Z~D
2 Q50
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
D 2N7002W-7-F_SOT323-3~D D
3 3 1
1
D
0.01U_0402_16V7K~D
100K_0402_5%~D
6 4 4 1 1 1
1
C60
C812
4 5 5 2 1 1
C268
C262
C813
R622
C211
6 G
6 2
7 S
3
7
1
2 2 2 D
8 8 Q68 2 2
9 38 MODC_EN 2
2
9 G 2N7002W-7-F_SOT323-3~D
5 10 10
1
11 S
3
11 R691
12 12
WF1F068N1A
8.3 13 100K_0402_5%~D
13
14 14
15
+5VMOD Source
2
15
16 16
17 17
18 18
19 SC_USBP+
19 SC_USBP+ 31
20 20
21 SC_USBP-
21 SC_USBP- 31
22 22
23 23
24 24
25 DASP#
22 IDE_DCS3#
IDE_DCS3# 26 26
25 HDD PWR
27 IDE_DCS1#
27 IDE_DCS1# 22
IDE_DA2 28
22 IDE_DA2 28
29 29
IDE_DA0 30
22 IDE_DA0 30 PDIAG#
31 +5V_ALW
IDE_DA1 31 +15V_ALW
22 IDE_DA1 32 32
33 IDE_IRQ
R205 33 IDE_IRQ 22 +3.3V_RUN
34 34
C 470_0402_5%~D IDE_DDACK#_R +3.3V_ALW2 C
35 35 1 2 IDE_DDACK# 22
1
1 2 CSEL2 36 R392 0_0402_5%~D
36 IDE_ DIORDY R627
TOP VIEW 37 37 2 1
1
2
5
6
IDE_DIOR# 38 100K_0402_5%~D
22 IDE_DIOR# 38 IDE_DIORDY 22
1
39 R206 D Q56
IDE_DIOW# 39 4.7K_0402_5%~D R626 G SI3456BDV-T1-E3_TSOP6~D
22 IDE_DIOW# 40
2
40 IDE_DDREQ HDD_EN_5V
41 41 IDE_DDREQ 22 3
IDE_DD15 42 100K_0402_5%~D S
42 IDE_DD0 +5V_HDD +5V_RUN
43
4
43 Q57 PJP2003
44 44
0.1U_0603_50V4Z~D
10U_0805_10V4Z~D
45 IDE_DD14 2N7002W-7-F_SOT323-3~D 1 2
45
1
IDE_DD1 D
46 46
100K_0402_5%~D
47 IDE_DD13 2 1 1 @ PAD-OPEN 4x4m
47
1
C817
C818
IDE_DD2 48 G Open
48
R629
49 S
3
49
1
IDE_DD[0..15] IDE_DD12 D
22 IDE_DD[0..15] 50 50 IDE_DD3 Q69 2 2
51 51 38 HDDC_EN 2
IDE_DD11 52 G 2N7002W-7-F_SOT323-3~D
2
52
1
53 IDE_DD4 S
3
53 R692
54 54
55 IDE_DD10 100K_0402_5%~D
IDE_DD5 55
56 56
57 IDE_DD9
2
IDE_DD6 57
58 58
59 59 +5V_HDD Source
R209 IDE_DD8 60
56_0402_5%~D 60 IDE_DD7
61 61
IDE_RST_MOD 1 2 MOD_RST 62
23 IDE_RST_MOD 62
63 63
USB_IDE# 64
23 USB_IDE# 64 JSATA
65 65
R230 66 1
B 100K_0402_5%~D 66 C461 PSATA_ITX_DRX_P0 GND B
67 67 22 PSATA_ITX_DRX_P0 2 RX+
1 2 MODPRES# 68 3900P_0402_50V7K~D PSATA_ITX_DRX_N0 3
+3.3V_RUN 38 MODPRES# 68 22 PSATA_ITX_DRX_N0 RX-
22 PSATA_IRX_DTX_N0_C 2 1 4 GND
PSATA_IRX_DTX_N0 5 TX-
G
2 1 PSATA_IRX_DTX_P0 6
TYCO_1770530-1~D 22 PSATA_IRX_DTX_P0_C TX+
7
69
70
C462 +3.3V_RUN GND

+3.3V_ALW 1 2
3900P_0402_50V7K~D 8
R217 3.3V
9 3.3V
10K_0402_5%~D 10 3.3V
11 GND
+5V_HDD 12 GND
13 GND
14 5V
close SATA connector 15 5V
16 5V
17 GND
18 Reserved GND1 23
19 GND GND2 24
20 12V
+5V_HDD +3.3V_RUN 21 12V
22 12V
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_10V7K~D
1000P_0402_50V7K~D
0.1U_0402_16V4Z~D
TYCO_1775191-1_RV~D
C465
@ C466
C464
1 1 1 1 1
C145
C469
@ @
2 2 2 2 2
om
A
Main SATA +5V Default A
Pleace near HD CONN Pleace near HD CONN
l.c
ai
tm
ho
f@
Title
DVD MODULE
in
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
xa
he
5 4 3 2 1
5 4 3 2 1
5 4
+VDDA
1
1 2 3
C710
D 0.1U_0402_16V4Z~D D
2 single gate TTL
5
U34 R540 C711
1 20K_0402_5%~D 0.1U_0402_10V6K~D
P
23 SPKR B
4 BEEP1 1 2 BEEP2 1 2 AUD_PC_BEEP
Y
39 BEEP 2 A
1
74AHCT1G86GW_SOT353-5~D
TRACE>15 mil
3
R541 +VDDA
10K_0402_5%~D
R542
2
5.11K_0402_1%~D
U34 place as close to CODEC as possible AUD_SENSE_A 2 1
1000P_0402_50V7K~D
39.2K_0402_1%~D
20K_0402_1%~D
1
1
1
C713
R711
R710
+3.3V_RUN R821 +3.3V_RUN
100K_0402_5%~D W=30 mil 2
1 2
2
+VDDA
1U_0603_10V4Z~D
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
1000P_0402_50V7K~D
1
D D
0.1U_0402_16V4Z~D
1U_0603_10V4Z~D
0.1U_0402_10V7K~D
10U_0805_10V6K~D
1 1 1 1 1 AUD_HP_NB_SENSE 2 2
27,38 AUD_HP_NB_SENSE AUD_MIC_SWITCH 27
C714
C759
C715
C716
C172
1 1 1 G G
Q74 S S Q75
3
C726
C717
C718
U35 2N7002W-7-F_SOT323~D 2N7002W-7-F_SOT323~D
2 2 2 2 @ 2
2 2 2 @
1 DVDD_CORE AVDD1 25
9 DVDD_CORE AVDD2 38
C C
40 DVDD_CORE/VPP
3 DVDD_IO
13 AUD_SENSE_A
SENSE_A AUD_SENSE_B
SENSE_B 34
ICH_AZ_CODEC_BITCLK 6 39
22 ICH_AZ_CODEC_BITCLK HDA_BIT_CLK PORT_A_L AUD_HP_OUT_L 27
1 2 ICH_AC_SDIN0_R 8 41
22 ICH_AZ_CODEC_SDIN0 HDA_SDI_CODEC PORT_A_R AUD_HP_OUT_R 27 +VDDA
R544 33_0402_5%~D
37 R543
VREFOUT_A 10K_0402_5%~D
ICH_AZ_CODEC_SDOUT 5 AUD_SENSE_B 2 1
22 ICH_AZ_CODEC_SDOUT HDA_SDO
PORT_B_L 21 AUD_EXT_MIC_L 27
22 ICH_AZ_CODEC_SYNC 10 HDA_SYNC
22 DOCK_HP_MUTE# 2 1
PORT_B_R AUD_EXT_MIC_R 27
11 R546 10K_0402_5%~D
22 ICH_AZ_CODEC_RST# HDA_RST#
VREFOUT_B 28 VREFOUT
ICH_AZ_CODEC_BITCLK AUD_SPDIF_SHDN 2 1
R547 10K_0402_5%~D
STAC9205 PORT_C_L 23
1
R545 24
PORT_C_R AUD_INT_MIC_IN 27
10_0402_5%~D 43 NC1
VREFOUT_C 29
44
2
NC2
Close to Pin 6 45 35 AUD_LINE_OUT_L
NC3 PORT_D_L AUD_LINE_OUT_L 27
1
36 AUD_LINE_OUT_R
PORT_D_R AUD_LINE_OUT_R 27
C721
10P_0402_50V8J~D
B 2 B
PORT_E_L 14
46 DMIC_CLK
PORT_E_R 15
2 VOL_UP/DMIC0/GPIO1
31 DOCK_HP_MUTE#
VREFOUT_E/GPIO4 DOCK_HP_MUTE# 38
4 VOL_DN/DMIC1/GPIO2
ICH_AZ_CODEC_SDOUT
PORT_F_L 16
1
R479 17
47_0402_5%~D PORT_F_R
@ VREFOUT_F/GPIO3 30 AUD_SPDIF_SHDN 38
2
Close to Pin 5 AUD_EAPD 47 18

27 AUD_EAPD SPDIF_ IN//GPIO0/EAPD CD_L
1 CD_GND 19
AUD_SPDIF_OUT 48 20
36 AUD_SPDIF_OUT SPDIF _OUT CD_R
C782
0.1U_0402_16V4Z~D 12 AUD_PC_BEEP
PC_BEEP
1
2 @
R823 7 32
10K_0402_5%~D DVSS MONO_OUT
26 AVSS1
42 33
2
AVSS2 CAP2
49 Thermal PAD GND VREFFILT 27
10U_0805_10V4Z~D
10U_0805_10V4Z~D
QFN 7x7 & LQFP 9x9 colay footprint. 1 1
STAC9205X5NBEB1XR_QFN48_COMON~D
C724
C725
2 2
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Azalia (HD) Codec
LA-3301P
5 4 3 2 1
5 4 3 2 1
C727
VREFOUT 1 2 VREFOUT_R 1 2
R580
10U_0805_10V4Z~D
4.7K_0402_5%~D
4.7K_0402_5%~D
0_0402_5%~D
1
+VDDA
R551
R552
1
+VDDA
2
R553 R554
+VDDA 1K_0402_5%~D 0_0402_5%~D R555 C728 L47
C729 1 2 AUD_MIC_BIAS 5.1_0402_1%~D 1U_0603_10V6K~D BLM18BD601SN1D_0603~D
1
2.2U_0805_10V6K~D 2 1 MIC_L1 1 2 MIC_L2 2 1 2 1 JMIC
2
R556 26 AUD_EXT_MIC_L R796 0_0402_5%~D
2 1 1
D 100K_0402_5%~D D
2
1
U36A 2 1 MIC_R1 1 2 MIC_R2 2 1 2 1 6
26 AUD_EXT_MIC_R
8
LM358DR2G_SOIC8~D R558 R557 R797 0_0402_5%~D L48 3
2
3 1K_0402_5%~D +VDDA 5.1_0402_1%~D C730 BLM18BD601SN1D_0603~D
P
AUD_MIC_BIAS 1 IN+ 1U_0603_10V6K~D
O 4
2
2
IN-
G
100P_0402_50V8J~D
100P_0402_50V8J~D
C731 R560 U36B 5
8
+3.3V_RUN
100K_0402_5%~D
20K_0402_1%~D
20K_0402_1%~D
1 0.1U_0402_10V6K~D 10K_0402_5%~D LM358DR2G_SOIC8~D 1 1 7
4
1
R559
C734
C735
1 2 1 2 5 8
P
32 AUD_INT_MIC+ IN+
R561
R562
C732 7 1 2
O AUD_INT_MIC_IN 26
100K_0402_5%~D
2.2U_0805_10V6K~D 1 2 1 2 6 FOX_JA9033L-B1N6-7F~D
32 AUD_INT_MIC- IN-
1
2 C733 @ @ 2 2
2
R564
C736 R563 0.1U_0805_25V7K~D
2
0.1U_0402_10V6K~D 10K_0402_5%~D
1 2
2
1
R566 R565
1K_0402_5%~D 100K_0402_5%~D 26 AUD_MIC_SWITCH
C737 +3.3V_RUN
2.2U_0805_10V6K~D
2
2 1
1
1
R567
R568 100K_0402_5%~D
1K_0402_5%~D
L49 JAUDIO
2
BLM18BD121SN1D_0603~D 1
2
HP_SPK_L1 2 1 HP_SPK_L2 2
6
HP_SPK_R1 2 1 HP_SPK_R2 3
100P_0402_50V8J~D
100P_0402_50V8J~D
L50
C BLM18BD121SN1D_0603~D C
26,38 AUD_HP_NB_SENSE 4
Speaker Connector 1 1 5
C738
C739
7
JSPK L51 8
INT_SPK_R1 1 BLM21PG600SN1D_0805~D
INT_SPK_R2 1 +5V_SPK+AMP 2 2 FOX_JA9033L-B1N6-7F~D
2 2 1 2 +5V_RUN
15 mils trace MOLEX_53398-0271~D Place Close to Audio Chip Place Close to Audio Chip
100P_0402_50V8J~D
100P_0402_50V8J~D
W=40mils
+5V_SPK+AMP
1U_0603_10V4Z~D
1U_0603_10V4Z~D
0.1U_0402_16V4Z~D
1U_0603_10V4Z~D
10U_0805_10V4Z~D
1U_0603_10V4Z~D
10U_0805_10V4Z~D
1 1 1 1 1 1 1 1 1
C740
C741
C742
C743
C783
C744
C745
C746
C747
@ 2 @ 2 2 2 2 2 2 2 2
30
18
8
U37
VDD
PVDD1
PVDD2
C77 0.033U_1206_50V7K~D
2 1 SPKR_INL_C 3 6 INT_SPK_R1
26 AUD_LINE_OUT_L SPKR_INL OUTL+
C748 0.033U_1206_50V7K~D +5V_SPK+AMP
2 1 SPKR_INR_C 2 7
Gain Setting
26 AUD_LINE_OUT_R SPKR_INR OUTL-
C749 1U_1206_25V7K~D
1 2 HP_INL_C 27 20
26 AUD_HP_OUT_L HP_INL OUTR+
1
+5V_SPK+AMP
1
C751 1U_1206_25V7K~D R569
1 2 HP_INR_C 26 19 INT_SPK_R2 100K_0402_5%~D R570
26 AUD_HP_OUT_R HP_INR OUTR-
1
B @ 100K_0402_5%~D B
MAX9789A
47P_0402_50V8J~D
47P_0402_50V8J~D
47P_0402_50V8J~D
47P_0402_50V8J~D
For TPA6040A,pop R713
2
100K_0402_5%~D 1 1 1 1 2 1 24 16 HP_SPK_L1
R714,depop R713
2
C752 1U_0603_10V4Z~D BIAS HPL AUD_GAIN1
C96
C905
C906
C907
2
+5V_SPK+AMP ADU_SPK_ENABLE# 23 15 HP_SPK_R1 AUD_GAIN2

AUDIO_AVDD_ON 1 AUD_AMP_MUTE# @ 2 @ 2 @ 2 2 @ SPKR_EN# HPR
2
@ R714 22 HP_EN
5
1
0_0402_5%~D U40
AUD_HP_NB_SENSE 2 AUD_AMP_MUTE# 25 31 AUD_GAIN1 R572 R573
P
A MUTE# GAIN1 @ 100K_0402_5%~D 100K_0402_5%~D

Y 4
NB_MUTE# 1 32 AUD_GAIN2
B GAIN2
G
+5V_SPK+AMP +5V_SPK+AMP 17
2
HPVDD
10U_0805_10V4Z~D
74AHCT1G08GW_SOT353-5~D For TPA6040A,pop C301,depop R585

3
R585 0_0402_5%~D
1 1 C754 9 CPVDD REGEN 4 REGEN 1 2 AUDIO_AVDD_ON 18
2
C753
1U_0603_10V4Z~D 1 2
R571 R712 @ C301
100K_0402_5%~D 100K_0402_5%~D C1P 10 0.033U_1206_50V7K~D
2 2 C1P
1U_0603_10V4Z~D
VOUT 29 +VDDA
1
1M_0402_1%~D
1U_0603_10V4Z~D
1U_0603_10V4Z~D
C1N 12 GAIN1 GAIN2 AV(inv) INPUT
1
C1N
R822
ADU_SPK_ENABLE# 1 1 1 IMPEDANCE
C755
11 CPGND MINIMAM 150 mA
C756
C757
1 SET
PGND1
PGND2
CPVSS
SET
0.033U_1206_50V7K~D
PVSS
0 0 6dB 82K ohm

GND
2
1
1
D 2 2 2
0_0402_5%~D
EP
R584
C304
2 AUD_EAPD
26 AUD_EAPD MAX9789A_TQFN32~D
G 0 1 10dB 66K ohm
14
13
33
28
5
21
S
3
Q43 2 @
C758
2N7002W-7-F_SOT323-3~D R790 2
om
1 0 15.6dB 45K ohm
@
A
10_0402_5%~D 2 1 * A
For
l.c
1U_0603_10V4Z~D 1 1 21.6dB 26K ohm
TPA6040A,
2
ai
1
D pop
1
@
tm
2 C232
38 NB_MUTE# G
Q42
10P_0402_50V8J~D
C304,depop
R584
ho
S
3
2N7002W-7-F_SOT323-3~D 2
f@
AMP and PHONE JACK
in
xa
LA-3301P
he
5 4 3 2 1
5 4 3 2 1
MMJT9435 +3.3V_LAN
Layout Notice : Place as close C Layout Notice : 1.2V filter. Place as close
chip as possible. chip as possible.
+3.3V_ALW 2
+3.3V_LAN
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
B C E 1 1
+1.2V_LAN
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
Q44
C824
C825
1 4 3
0.1U_0402_16V4Z~D
2 2 SI3456BDV-T1-E3_TSOP6~D
4.7U_0603_6.3V4Z~D
Q70
4
D
2 2
2_1210_5%~D
2_1210_5%~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C309
C316
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
6 MBT35200MT1G_TSOP6~D
S
5 4 +3.3V_LAN 1 1 1 2 2 2 2 2 2 2 2
1 1
R643
R644
C826
C827
2
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C629
C828
C829
C830
C831
C832
C833
C834
C835
D REGCTL_PNP25 D
1 3
G 2 2 2 2 2 R7, R9 are 1/2 W rating
2
2 2 2 1 1 1 1 1 1 1 1
0.047U_0402_16V4Z~D
3 @
C836
C837
C838
C839
C840
+2.5V_LAN
41 ENAB_3VLAN
1
2
5
6
L63 1
3
1 1 1 1 1 +2.5V_LAN
2 1 +XTALVDD
C771
BK2125LM182-T_0805~D 1
0.1U_0402_16V4Z~D
Place closely pin J8 REGCTL_PNP12 Q71
10U_0805_10V4Z~D
1
PBSS5540Z_SOT223-3~D C849 2 @
CLK_PCI_TPM 1 1000P_0402_50V7K~D 1 1
2
C842
C843
2
4
@ C772 +1.2V_LAN
1
0.047U_0402_16V4Z~D L64
R654 2 2 2
2 1 +BIASVDD
+3.3V_LAN
0.1U_0402_16V4Z~D
33_0402_5%~D BK1608LM182-T_0603~D
10U_0805_10V4Z~D
1
@ R415
4.7K_0402_5%~D C850
1 1
2
1 GPIO1_SERIAL_DI 47P_0402_50V8J~D
C845
C846
2
2
1
2 1 LOM_LOW_PWR
C854 R421 2 2 L65 +2.5V_LAN +1.2V_LAN U38B
22P_0402_50V8J~D 4.7K_0402_5%~D 2 1
2 BK2125LM182-T_0805~D 1
+AVDD
D5 BCM5755M B2
@
VDDC_0 VSS_0
D6 VDDC_1 VSS_1 B10
C852
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
U38A D7 E4
47P_0402_50V8J~D VDDC_2 VSS_2
D8 E5
BCM5755M 2 1 1 VDDC_3 VSS_3
C847
C848
H5 VDDC_4 VSS_4 E6
CLK_PCI_TPM J8 B11 LAN_TX3+ H6 E7
6 CLK_PCI_TPM LCLK TRD3+ LAN_TX3+ 29 VDDC_5 VSS_5
B12 LAN_TX3- H8 E8
22,38,39 LPC_LAD[0..3] TRD3- LAN_TX3- 29 2 2 VDDC_6 VSS_6
LPC_LAD0 J7 C11 LAN_TX2+ J4 E9
LAD0 TRD2+ LAN_TX2+ 29 +3.3V_LAN VDDC_7 VSS_7
LPC_LAD1 L10 C12 LAN_TX2- F4
Media
LAD1 TRD2- LAN_TX2- 29 VSS_8
LPC/TPM
LPC_LAD2 J5 D11 LAN_TX1+ Logic High Voltage must Digial power F5

C LAD2 TRD1+ LAN_TX1+ 29 VSS_9 C
LPC_LAD3 K9 D12 LAN_TX1- A3 F6
LAD3 TRD1-
E11 LAN_TX0+
LAN_TX1- 29 be 0.7V to 2.75V C2
VDDIO_0 VSS_10
F7
TRD0+ LAN_TX0+ 29 VDDIO_1 VSS_11
LPC_LFRAME# J9 E12 LAN_TX0- +1.2V_LAN D10 F8
22,38,39 LPC_LFRAME# LFRAME TRD0- LAN_TX0- 29 VDDIO_2 VSS_12
PLTRST3# M10 L66 F1 F9
21,34 PLTRST3# LRESET VDDIO_3 VSS_13
IRQ_SERIRQ H7 @ 0_0402_5%~D R647 2 1 +AVDDL G10 G5
23,30,38,39 IRQ_SERIRQ SERIRQ VDDIO_4 VSS_14
H4 R488 1 2 20K_0402_5%~D BK1608LM182-T_0603~D1 1 J2 GND G6
LOW_PWR LOM_LOW_PWR 38 VDDIO_5 VSS_15
@@@
1 10K_0402_5%~D TPM_GPIO0 G4 R646 2 K5 2 1 L1 G7

Control
TPM_GPIO0 Super_Low_PWR LOM_SUPER_IDDQ 38 C855 C856 VDDIO_6 VSS_16

1 10K_0402_5%~D TPM_GPIO1 J3 R648 2 G8
TPM_GPIO1 +2.5V_LAN VSS_17
1 10K_0402_5%~D TPM_GPIO2 H3 R649 2 G11 2 1 4.7U_0603_6.3V4Z~D 47P_0402_50V8J~D L2
Power
TPM_GPIO2/TPM_STATUS VMAINPRSNT +3.3V_RUN VSS_18
1
R650 1K_0402_5%~D 2 2
38 LOM_TPM_EN# 1 J6 2 TPM_EN VSS_19 L6
0_0402_5%~D R651 B6 2 1 +3.3V_LAN R276 A5 M6
VAUXPRSNT R652 1K_0402_5%~D 39K_0402_5%~D L67 VDDP_0 VSS_20
2 1 G3 VDDP_1
@ R653 4.7K_0402_5%~D 2 1 +GPHY_PLLVDD L11 A1
LOM_SMB_ALERT# BK1608LM182-T_0603~D1 VDDP_2 DC_0
H9 K12 +3.3V_LAN 1 A6
2
23,39 LOM_SMB_ALERT# GPIO1_SERIAL_DI GPIO0 REGSUP12 REGCTL_PNP12 DC_1
H11 GPIO1_SERIAL_DI REGCTL12 J11 DC_2 A7
LOM_LOW_PWR 1 2 GPIO2_SERIAL_DO C5 C857 C858 H12 B7
Regulator
GPIO2_SERIAL_DO +XTALVDD XTALVDD DC_3

R422 C4 J12 4.7U_0603_6.3V4Z~D 47P_0402_50V8J~D C1
Control
EnergyDet REGSEN12 +1.2V_LAN 2 2 DC_4

1K_0402_5%~D L12 +3.3V_LAN +PCIE_SDS_VDD K4 C3
38 LOM_CABLE_DETECT REGSUP25 PCIE_SDSVDD DC_5
GPIO M11 REGCTL_PNP25 D1
REGCTL25 L68 DC_6
R646, R648, R649 Reserved for DC_7 D2
M12 +2.5V_LAN 2 1 +PCIE_PLLVDD D3
BCM5752 as back-up solution REGSEN25 BK1608LM182-T_0603~D1 A12 BIAS
DC_8
E1
1 +BIASVDD BIASVDD DC_9
SMBUS
23,34 ICH_SMBCLK C8 SMB_CLK DC_10 G2

C7 C851 C859 C860 H2
23,34 ICH_SMBDATA SMB_DATA DC_11
0.1U_0402_10V7K~D 4.7U_0603_6.3V4Z~D 0.1U_0402_16V4Z~D +AVDDL F10 K1
GLAN_RXN_C 2 2 AVDDL_0 DC_12
PCIE_TXDN M3 1 2 PCIE_RX6-/GLAN_RX- 23 F11 AVDDL_1 Analog DC_13 K2
K3
L3 GLAN_RXP_C 1 2 L88 A11 power DC_14
K7
PCIE_TXDP PCIE_RX6+/GLAN_RX+ 23 +AVDD AVDD_0 DC_15
C853 2 1 +PCIE_SDS_VDD F12 K8
LOM_SCLK 0.1U_0402_10V7K~D BK1608LM182-T_0603~D1 AVDD_1 DC_16
C9 SCLK PCIE_RXDN L7 PCIE_TX6-/GLAN_TX- 23 1 DC_17 L4
+3.3V_LAN LOM_SI E10 L8
SI C864 DC_18
SPI
@ R655 LOM_SO D9 M7 C863 M8

PCI-E
B SO PCIE_RXDP PCIE_TX6+/GLAN_TX+ 23 DC_19 B

4.7K_0402_5%~D LOM_CS# C10 4.7U_0603_6.3V4Z~D 0.1U_0402_16V4Z~D K6 A2
CS 2 2 +PCIE_PLLVDD PCIE_PLLVDD NC_0
1 2 NV_STRAP0 M2 A4 PCIE_WAKE# PLL E2
NV_STRAP0 WAKE PCIE_WAKE# 34,38 NC_1
M1 L5 CLK_PCIE_LOM# +GPHY_PLLVDD G12 G1
NV_STRAP1 REFCLK- CLK_PCIE_LOM# 6 GPHY_PLLVDD NC_2
M5 CLK_PCIE_LOM G9
REFCLK+ CLK_PCIE_LOM 6 NC_3
CLKREQ# F2 1 2 LOM_CLKREQ# 6 NC_4 H1
B3 R656 0_0402_5%~D H10
REFCLK_SEL NC_5
PERST B1 1 2 NC_6 J10
@ R657 4.7K_0402_5%~D +3.3V_LAN K10
LOM_SPD10LED_GRN# A9 NC_7
29 LOM_SPD10LED_GRN# LINKLED 2 1 SB_LOM_PCIE_RST# 21 NC_8 K11
LED
LOM_SPD100LED_ORG# B9 0_0402_5%~D @ R582

29 LOM_SPD100LED_ORG# SPD100LED
4.7K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
A10 B5 LOM_RST_R# 2 1 PLTRST3#
SPD1000LED TCK PLTRST3# 21,34
LOM_ACTLED_YEL# B8 F3 0_0402_5%~D R581 BCM5755M_FBGA144~D
29 LOM_ACTLED_YEL# TRAFFICLED TDI
1
B4 @ R658 Reserved for BCM5752
TDO
R665
R664
R670
E3 4.7K_0402_5%~D 1 2
TEST
TMS as back-up solution +3.3V_LAN

R659 D4 1 2 @ R661
XTALO TRST 4.7K_0402_5%~D
2 1 M9 XTALO GPHY_TVCOI C6
Clock
200_0402_1%~D J1 PHYTVCOI 1 2 @ @ @
2
NC @ R666 0_0402_5%~D
NC M4 Place R666 as
Monitor GPHY PLL Clk +3.3V_LAN U44
1 2 XTALI L9
close to the ASIC 8 1 LOM_SO NV_STRAP1 NV_STRAP0 SO SI CS# SCLK
XTALI Q D
22P_0402_50V8J~D
1 2 as possible. Pad 7 2 LOM_SCLK

Bias
+3.3V_LAN VSS C
22P_0402_50V8J~D
Y5 A8 @ R663 6 3
25MHZ_18PF_1BX25000CK1D~D RDAC 4.7K_0402_5%~D
is needed to VCC RESET# LOM_CS# Auto-Sense Mode 0 0 0 0 0 0
2 2 5 W# S# 4
measure 125MHz
C861
C862
1.13K_0402_1%~D
clock for M45PE20-VMN6TP_SO8~D (Default)

2
Need to ensure BCM5755M_FBGA144~D

1 1 debugging
R669
@ U45
crystal at least Layout Notice : No high LOM_SI 8 1 Atmel AT45BCM021B 0 0 1 0 1 1
SO SI
300uW max power speed signal should be 7 GND SCK 2
0.1U_0402_16V4Z~D
6 3
drive-level
1
routed near RDAC or on VCC RESET# ST M45PE20 0 1 1 0 0 1

5 WP# CS# 4
adjacent layer to RDAC 2
C865
A AT45BCM021B-SU_SO8~D A
LOM_CABLE_DETECT goes to an input on a system microcontroller that can DELL CONFIDENTIAL/PROPRIETARY

poll this signal periodically and can de-assert the LOM_LOW_PWR when
LOM_CABLE_DETECT signal is high. Connect to an EC GPIOC defined by the
Title
GPIO mapping. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BCM5755M
5 4 3 2 1
5 4 3 2 1
+3.3V_LAN
LAN ANALOG
SWITCH
56
50
38
27
18
10
4
@ C866 1 2 0.1U_0402_16V4Z~D R671 1 2 @49.9_0402_1%~D LAN_TX0- U46
R672 1 2 @ 49.9_0402_1%~D LAN_TX0+
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
VDD0
@ C867 1 2 0.1U_0402_16V4Z~D R673 1 2 @ 49.9_0402_1%~D LAN_TX1- 48 SW_LAN_TX0-
0B1 SW_LAN_TX0- 32
R674 1 2 @ 49.9_0402_1%~D LAN_TX1+ 47 SW_LAN_TX0+
1B1 SW_LAN_TX0+ 32
@ C868 1 2 0.1U_0402_16V4Z~D R675 1 2 @ 49.9_0402_1%~D LAN_TX2- LAN_TX0- 1 2 LAN_TX0-R 2
28 LAN_TX0- A0
R676 1 2 @ 49.9_0402_1%~D LAN_TX2+ L69 36NH_0603CS-360EJTS_5%_0603~D 43 SW_LAN_TX1-
2B1 SW_LAN_TX1- 32
@ C869 1 2 0.1U_0402_16V4Z~D R677 1 2 @ 49.9_0402_1%~D LAN_TX3- LAN_TX0+ 1 2 LAN_TX0+R 3 42 SW_LAN_TX1+
28 LAN_TX0+ A1 3B1 SW_LAN_TX1+ 32
R678 1 2 @ 49.9_0402_1%~D LAN_TX3+ L70 36NH_0603CS-360EJTS_5%_0603~D
D SW_LAN_TX2- D
4B1 37 SW_LAN_TX2- 32
LAN_TX1- 1 2 LAN_TX1-R 7 36 SW_LAN_TX2+
28 LAN_TX1- A2 5B1 SW_LAN_TX2+ 32
L71 36NH_0603CS-360EJTS_5%_0603~D
LAN_TX1+ 1 2 LAN_TX1+R 8 32 SW_LAN_TX3-
28 LAN_TX1+ A3 6B1 SW_LAN_TX3- 32
L72 36NH_0603CS-360EJTS_5%_0603~D 31 SW_LAN_TX3+
7B1 SW_LAN_TX3+ 32
Layout Notice : Place LAN_TX2- 1 2 LAN_TX2-R 11 22 LAN_LEDACT#
28 LAN_TX2- A4 0LED1
L73 36NH_0603CS-360EJTS_5%_0603~D 23 LINK_LED10#
termination as close as LAN_TX2+ 1 LAN_TX2+R 1LED1 LINK_LED100#
28 LAN_TX2+ 2 12 A5 2LED1 52
ASIC as possible L74 36NH_0603CS-360EJTS_5%_0603~D
46 DOCK_LAN_TX0-
0B2 DOCK_LAN_TX0- 36
The resistors need at LAN_TX3- 1 2 LAN_TX3-R 14 45 DOCK_LAN_TX0+
28 LAN_TX3- A6 1B2 DOCK_LAN_TX0+ 36
L75 36NH_0603CS-360EJTS_5%_0603~D
least 1/16W LAN_TX3+ 1 LAN_TX3+R DOCK_LAN_TX1-
28 LAN_TX3+ 2 15 A7 2B2 41 DOCK_LAN_TX1- 36
L76 36NH_0603CS-360EJTS_5%_0603~D 40 DOCK_LAN_TX1+
3B2 DOCK_LAN_TX1+ 36
DOCKED 17 35 DOCK_LAN_TX2-
36,38 DOCKED SEL 4B2 DOCK_LAN_TX2+ DOCK_LAN_TX2- 36
5B2 34 DOCK_LAN_TX2+ 36
19 30 DOCK_LAN_TX3-
28 LOM_ACTLED_YEL# LED0 6B2 DOCK_LAN_TX3- 36
20 29 DOCK_LAN_TX3+
28 LOM_SPD10LED_GRN# LED1 7B2 DOCK_LAN_TX3+ 36
Layout Notice : Place bead as 28 LOM_SPD100LED_ORG# 54 LED2
25 DOCK_LOM_ACTLED_YEL#
close PI3L500 as possible 0LED2 DOCK_LOM_SPD10LED_GRN#
DOCK_LOM_ACTLED_YEL# 36
5 NC 1LED2 26 DOCK_LOM_SPD10LED_GRN# 36
51 DOCK_LOM_SPD100LED_ORG#
2LED2 DOCK_LOM_SPD100LED_ORG# 36
57 PAD_GND
GND10
GND11
GND12
GND13
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
PI3L500-AZFEX_TQFN56~D
1
6
9
13
16
21
24
28
33
39
44
49
53
55
C
1: TO DOCK TO C
FROM NIC DOCKED DOCK
0: TO RJ45
+3.3V_LAN
@
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
1
1
R679
R680
R681
2
2
LOM_ACTLED_YEL#
LOM_SPD10LED_GRN#
LOM_SPD100LED_ORG#
B B
R682
LAN_LEDACT# 1 2 LAN_ACTLED_YEL_R#
LAN_ACTLED_YEL_R# 32
150_0402_5%~D
R683
LINK_LED10# 1 2 LED_10_GRN_R#
LED_10_GRN_R# 32
110_0402_5%~D
R684
LINK_LED100# 1 2 LED_100_ORG_R#
LED_100_ORG_R# 32
200_0402_5%~D
om
A A
l.c
ai
tm
ho
f@
Title
LAN TRANSFOMER
in
xa
he
5 4 3 2 1
8 7 6 5 4 3 2 1
+5V_RUN +3.3V_RUN
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
4.7U_0603_6.3V4Z~D
1 1 1 1
C790
C791
C792
C793
2 2 2 2
U41
CLK_PCI_PCM 2 16
PCI_PERR# CLK +5V
21,35 PCI_PERR# 7 PERR# +5V 15
D PCI_SERR# 8 +CBS_VCC D
+3.3V_RUN +OZ1.8V_RUN 21,35 PCI_SERR# SERR#
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
PCI_RST# 10 18
CLKRUN# RST# +3.3V
1 1 1 1 1 23,38,39 CLKRUN# 6 CLKRUN# +3.3V 17
PCI_PIRQD# 3
21 PCI_PIRQD# INTA#
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
C794
C795
C796
C800
C801
9 SKT_LED VCC/VPP 5
1 1 VCC/VPP 4
2 2 2 2 2
19 1.8VOUT
R602 33_0402_5%~D
C797
C798
1 14 USBP6-
EPSI USB_A0 USBP6- 23
13 CBS_CAD15
2 2 USB_B0 USBP6+
20 GND USB_A1 12 USBP6+ 23
11 CBS_CAD13
USB_B1
C806 OZ2532SN_SSOP20~D
L60 12P_0402_50V8J~D
BLM18AG121SN1D_0603~D
16
82
1 2
8
+3.3V_RUN 1 2 U42 R603
2
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
5.9K_0402_1%~D
CORE_1.8
CORE_1.8
EPSI
1 1 1 11 72 1 2 X2 24.576MHz_16P_1BG24576CKIA~D
CORE_3.3 REF
97 CORE_3.3 C823
C802
C803
C804
74
1
XI R604
26 PCI_VCC XO 75 1 2 1 2
2 2 2 R114 0_0402_5%~D 0_0402_5%~D
56 PCI_VCC
71 TPBIAS0 12P_0402_50V8J~D 1 2
BIAS R606
65 CORE_3.3A TPA+ 70
68 69 0_0402_5%~D
CORE_3.3A TPA-
73 CORE_3.3A TPB+ 67 1 2
TPB- 66
L61 @ DLW21SN121SQ2_0805~D
21,35 PCI_AD[0..31]
PCI_AD31 19 3 CBS_CAD31 TPA0+ 4 TPA0_D+
PCI_AD30 AD31 CAD31 CBS_CAD30 4 3 3 J1394
20 AD30 CAD30 1
PCI_AD29 21 128 CBS_CAD29 4 5
PCI_AD28 AD29 CAD29 CBS_CAD28 TPA0- TPA0_D- TPA+ GND
22 AD28 CAD28 127 1 1 2 2 3 TPA- GND 6
C PCI_AD27 CBS_CAD27 C
23 AD27 CAD27 126 2 TPB+ GND 7
PCI_AD26 24 125 CBS_CAD26 TPB0+ 4 3 TPB0_D+ 1 8
PCI_AD25 AD26 CAD26 CBS_CAD25 4 3 TPB- GND
Place closely pin 45 25 AD25 CAD25 124
PCI_AD24 27 122 CBS_CAD24 TYCO_2-1775815-2~D
AD24 CAD24
56.2_0402_1%~D
CLK_PCI_PCM PCI_AD23 29 120 CBS_CAD23 TPB0- 1 2 TPB0_D-
AD23 CAD23 1 2
56.2_0402_1%~D
56.2_0402_1%~D
PCI_AD22 30 118 CBS_CAD22
AD22 CAD22
1
PCI_AD21 31 116 CBS_CAD21 L62 @ DLW21SN121SQ2_0805~D
AD21 CAD21
1
R608
R609
PCI_AD20 32 115 CBS_CAD20 R642 R611
AD20 CAD20
R607
R610 PCI_AD19 34 114 CBS_CAD19 56.2_0402_1%~D 0_0402_5%~D
PCI_AD18 AD19 CAD19 CBS_CAD18
10_0402_5%~D 35 AD18 CAD18 113 1 2
PCI_AD17 36 112 CBS_CAD17 R612
@
2
PCI_AD16 AD17 CAD17 CBS_CAD16 0_0402_5%~D
37 96
2

47 AD15 CAD15 94 2 1 2
2
5.11K_0402_1%~D
270P_0402_50V7K~D
1 PCI_AD14 48 93 CBS_CAD14
AD14 CAD14
1U_0603_10V4Z~D
C807
R613
PCI_AD13 49 92 CBS_CAD13 1 Layout Note: Place close to 1394 connector
AD13 CAD13
C805
C808 PCI_AD12 50 91 CBS_CAD12
PCI_AD11 AD12 CAD12 CBS_CAD11 1
4.7P_0402_50V8C~D 51 90
2 PCI_AD10 52
AD11 OZ711EZ1 CAD11
89 CBS_CAD10
@
1
PCI_AD9 AD10 CAD10 CBS_CAD9 2
53 AD9 CAD9 88
PCI_AD8 54 87 CBS_CAD8
57 AD7 CAD7 84
PCI_AD6 58 83 CBS_CAD6 JCBUS
59 AD5 CAD5 81 1 GND1 GND9 41
PCI_AD4 60 80 CBS_CAD4 CBS_CAD0 2 42 CBS_CCD1#
PCI_AD3 AD4 CAD4 CBS_CAD3 CBS_CAD1 A_CAD0 A_CCD1# CBS_CAD2
61 AD3 CAD3 79 3 A_CAD1 A_CAD2 43
PCI_AD2 62 78 CBS_CAD2 CBS_CAD3 4 44 CBS_CAD4
PCI_AD1 AD2 CAD2 CBS_CAD1 CBS_CAD5 A_CAD3 A_CAD4 CBS_CAD6
63 AD1 CAD1 77 5 A_CAD5 A_CAD6 45
PCI_AD0 64 76 CBS_CAD0 CBS_CAD7 6 46 CBS_RSVD/D14
AD0 CAD0 CBS_CC/BE0# A_CAD7 CB_A_D14 CBS_CAD8
7 A_PCI_C/BE0# A_CAD8 47
PCI_C_BE3# R614 0_0402_5%~D CBS_CCLK
21,35 PCI_C_BE3# 28 C/BE3# 8 GND2 GND10 48
21,35 PCI_C_BE2# PCI_C_BE2# 38 106 CBS_CAD9 9 49 CBS_CAD10
PCI_C_BE1# C/BE2# CCLK CBS_CFRAME# CBS_CAD11 A_CAD9 A_CAD10 CBS_CVS1
21,35 PCI_C_BE1# 46 C/BE1# CFRAME# 110 10 A_CAD11 A_CVS1 50
B R615 PCI_C_BE0# C BS_CIRDY# CBS_CAD12 CBS_CAD13 B
21,35 PCI_C_BE0# 55 C/BE0# CIRDY# 109 11 A_CAD12 A_CAD13 51
100_0402_5%~D 107 CBS_CTRDY# 12 52
PCI_AD17 CBS_IDSEL CTRDY# CBS_CDEVSEL# CBS_CAD14 GND3 GND11 CBS_CAD15
1 2 9 IDSEL CDEVSEL# 105 13 A_CAD14 A_CAD15 53
CLK_PCI_PCM 45 103 CBS_CSTOP# CBS_CC/BE1# 14 54 CBS_CAD16
6 CLK_PCI_PCM PCI_CLK CSTOP# A_PCI_C/BE1# A_CAD16
PCI_DEVSEL# 42 98 CBS_CPAR CBS_CPAR 15 55 CBS_RSVD/A18
21,35 PCI_DEVSEL# DEVSEL# CPAR A_CPAR CB_A_A18
PCI_FRAME# 39 100 CBS_CPERR# 16 56
21,35,36 PCI_FRAME# FRAME# CPERR# GND4 GND12
PCI _IRDY# 40 119 CBS_CSERR# CBS_CPERR# 17 57 CBS_CBLOCK#
21,35,36 PCI_IRDY# IRDY# CSERR# A_CPERR# A_CBLOCK#
PCI_TRDY# 41 121 CBS_CREQ# CBS_CGNT# 18 58 CBS_CSTOP#
21,35 PCI_TRDY# TRDY# CREQ# A_CGNT# A_CSTOP#
PCI_STOP# 43 102 CBS_CGNT# CBS_CINT# 19 59 CBS_CDEVSEL#
21,35 PCI_STOP# STOP# CGNT# A_CINT# A_CDEVSEL#
PCI_PAR 44 104 CBS_CINT# +CBS_VCC 20 60 +CBS_VCC
21,35 PCI_PAR PAR CINT# +AVCC0 +AVCC1
PCI_REQ1# 17 101 CBS_CBLOCK# 21 61
21 PCI_REQ1# REQ# CBLOCK# +AVPP0 +AVPP1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
PCI_GNT1# 18 4 CBS_CCLKRUN# CBS_CCLK 22 62 CBS_CTRDY#
21 PCI_GNT1# GNT# CCLKRUN# A_CCLK A_CTRDY#
PCI_RST# 5 117 CBS_CRST# 1 C BS_CIRDY# 23 63 CBS_CFRAME# 1
21,31,35 PCI_RST# PCI_RST# CRST# A_CIRDY A_CFRAME#
7 2 CBS_RSVD/D2 CBS_CC/BE2# 24 64 CBS_CAD17
35,38 SYS_PME# PME# R2_D2 A_PCI_C/BE2# A_CAD17
C809
C810
IRQ_SERIRQ 6 85 CBS_RSVD/D14 CBS_CAD18 25 65 CBS_CAD19
23,28,38,39 IRQ_SERIRQ SERIRQ R2_D14 CBS_RSVD/A18 CBS_CAD20 A_CAD18 A_CAD19 CBS_CVS2
R2_A18 99 26 A_CAD20 A_CVS2 66
CBS_CVS1 2 2
CVS1 12 27 GND5 GND13 67
15 CBS_CVS2 CBS_CAD21 28 68 CBS_CRST#
CVS2 CBS_CCD1# CBS_CAD22 A_CAD21 A_CRST# CBS_CSERR#
CCD1# 10 29 A_CAD22 A_CSERR# 69
14 CBS_CCD2# CBS_CAD23 30 70 CBS_CREQ#
CCD2# CBS_CAD24 A_CAD23 A_CREQ# CBS_CC/BE3#
31 A_CAD24 A_PCI_C/BE3# 71
13 CBS_CSTSCHNG 32 72
CSTSCHG CBS_CAD25 GND6 GND14
33 A_CAD25 A_CAUDIO 73
123 CBS_CC/BE3# CBS_CAD26 34 74 CBS_CSTSCHNG
CC/BE3# CBS_CC/BE2# CBS_CAD27 A_CAD26 A_CSTSCHG CBS_CAD28
CC/BE2# 111 35 A_CAD27 A_CAD28 75
95 CBS_CC/BE1# 36 76
GND
GND
GND
CC/BE1# CBS_CC/BE0# CBS_CAD29 GND7 GND15 CBS_CAD30

CC/BE0# 86 37 A_CAD29 A_CAD30 77
CBS_RSVD/D2 38 78 CBS_CAD31
OZ711EZ1TN C_E-LQFP128_16X16~D CBS_CCLKRUN# CB_A_D2 A_CAD31 CBS_CCD2#
39 79
33
108
129
A_CCLKRUN# A_CCD2#
40 GND8 GND16 80
TYCO_1734648-1~D
A A
Ground pin 129 exposed die pad, dimension

5.72mm x 5.72mm, should connect to PCB solder DELL CONFIDENTIAL/PROPRIETARY
pad of same dimension Compal Electronics, Inc.
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Cardbus and 1394 OZ711EZ1 Controller
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
USB SMARTCARD READER.

D TYPE A (5V), B (3V), AB (5V/3V) D
& USB SMARTCARDS ARE SUPPORTED.
+5V_RUN +3.3V_RUN
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
15K_0402_5%~D
15K_0402_5%~D
1 1 1 1
1
C428
C443
C441
C435
R256
R257
2 2 2 2
+3.3V_RUN
2
+SC_PWR
1.5K_0402_1%~D
U26
1
0.1U_0402_16V4Z~D
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
1U_0603_10V4Z~D
C425
R252
47K_0402_5%~D
1U_0603_10V4Z~D 1 1 1 1
1
C442
C446
C448
C129
10K_0402_5%~D
8 3.3VCC VR_CPR0 6 1 2
R263
R129
VR_CPR1 10
5 29 1 2
2
C VCC5V_IN0 3V_CPR C305 1U_0603_10V4Z~D 2 2 2 2 JSC C

28 VCC5V_IN1
21 SCCD- 12
2
USBP4- EGATED- SCCD+ GND
23 USBP4- 17 UPD- EGATED+ 20 11 GND
USBP4+ 16
23 USBP4+ UPD+
19 27 +SC_PWR 10
25 SC_USBP- DPD- SC_VCC 10
18 24 SC_RST# R125 2 1 220_0402_5%~D 9
25 SC_USBP+ DPD+ SC_RST# 9
23 SC_CLK R126 2 1 33_0402_5%~D 8
PCI_RST# SC_CLK SC_C4 R260 8
21,30,35 PCI_RST# 12 RST# SC_C4 22 2 1 220_0402_5%~D SCCD+ 7 7
25 SC_IO 6
SC_IO SC_DET# 6
PAD~D T40 14 RFIO0 SC_DET# 13 5 5
PAD~D T41 15 R130 2 1 220_0402_5%~D 4
RFIO1 SCCD- 4
NC1 7 3 3
15K_0402_5%~D
15K_0402_5%~D
15K_0402_5%~D
15K_0402_5%~D
CLK_SMC_48M 3 30 2
6 CLK_SMC_48M XI/48M_IN NC2 2
4 XO NC3 31 1 1
1
0.1U_0402_16V4Z~D
R255
R251
SC_DET# 38
R264
R296
MD0 32 9 1 MOLEX_52207-1085~D
MODE0/LED# GND0
C91
1 MODE1 GND1 11
4.7K_0402_5%~D
2 MODE2 GND2 26
1
2
2
R259
OZ77CR6LN_QFN32~D
2
B B
Place closely pin 3

CLK_SMC_48M
1
@
R258
10_0402_5%~D
2
@ 1
C432
4.7P_0402_50V8C~D
2
om
A A
l.c
ai
tm
ho
f@
Smart Card OZ77CR6
in
xa
LA-3301P
he
8 7 6 5 4 3 2 1
5 4 3 2 1
@ FUSE4
L0603
D D
1 2
@ FUSE1
LF453 +USB_BACK_PWR
1 2
+USB_SIDE_PWR
0.1U_0402_16V4Z~D
+5V_ALW
PJP4 U4
C3
PAD-OPEN1x1m 1 8 USB_OC2_3# 1
GND OC1# USB_OC2_3# 23
1 2 2 IN OUT1 7
3 6 JIO
USB_BACK_EN# EN1# OUT2 LAN_ACTLED_YEL_R#
38 USB_BACK_EN# 4 EN2# OC2# 5 1 1 2 2 LAN_ACTLED_YEL_R# 29
2
3 3 4 4 +3.3V_LAN
1 1 TPS2062DR_SO8~D 5 6 SW_LAN_TX0+
5 6 SW_LAN_TX0+ 29
C169 C170 USBP0- 7 8 SW_LAN_TX0-
23 USBP0- 7 8 SW_LAN_TX0- 29
0.1U_0402_16V4Z~D 10U_0805_10V4Z~D USBP0+ 9 10 SW_LAN_TX1+
23 USBP0+ 9 10 SW_LAN_TX1+ 29
@ 11 12 SW_LAN_TX1-
2 2 11 12 SW_LAN_TX1- 29
USBP1- 13 14 +2.5V_LAN
23 USBP1- 13 14
USBP1+ 15 16 SW_LAN_TX2+
23 USBP1+ 15 16 SW_LAN_TX2+ 29
@ FUSE5 BREATH_GREEN_LED 17 18 SW_LAN_TX2-
43 BREATH_GREEN_LED 17 18 SW_LAN_TX2- 29
L0603 BATT_GREEN_LED 19 20 SW_LAN_TX3+
43 BATT_GREEN_LED 19 20 SW_LAN_TX3+ 29
1 2 BATT_AMBER_LED 21 22 SW_LAN_TX3-
43 BATT_AMBER_LED 21 22 SW_LAN_TX3- 29
R_BT_ACT 23 24
43 R_BT_ACT 23 24
@ FUSE2 R_MPCI_ACT 25 26 LED_10_GRN_R#
+USB_SIDE_PWR 43 R_MPCI_ACT 25 26 LED_10_GRN_R# 29
LF453 27 28 LED_100_ORG_R#
27 AUD_INT_MIC+ 27 28 LED_100_ORG_R# 29
1 2 29 30 HDD_LED
27 AUD_INT_MIC- 29 30 HDD_LED 43
+5V_ALW
PJP3 U1 31 34
PAD-OPEN1x1m USB_OC0_1# GND GND
1 GND OC1# 8 USB_OC0_1# 23 32 GND GND 35
1 2 2 IN OUT1 7 33 GND GND 36
3 EN1# OUT2 6
C USB_SIDE_EN# TYCO_3-1775014-0~D C
38 USB_SIDE_EN# 4 EN2# OC2# 5
1 1 TPS2062DR_SO8~D
C2 C1
0.1U_0402_16V4Z~D 10U_0805_10V4Z~D
@
2 2
+USB_SIDE_PWR +USB_BACK_PWR
@ U16
@ U2 USBP3- 1 4 USBP2-
USBP0+ USBP1+ D1+ D2+
1 D1+ D2+ 4
2 GND VCC 5
2 GND VCC 5
USBP2+ 3 6 USBP3+
USBP1- USBP0- D2- D1-
3 D2- D1- 6
IP4220CZ6_SO6~D
IP4220CZ6_SO6~D
Place ESD diodes as close as USB connector.
B B
@ L12 DLW21SN900SQ2_0805~D +USB_BACK_PWR
0.1U_0402_16V4Z~D
150U_D2_6.3VM~D
4 3 USBP2_D-
23 USBP2- 4 3
1 1
C9
C168
1 2 USBP2_D+ + JUSB1
23 USBP2+ 1 2
R149 1
0_0402_5%~D 2 USBP3_D- A_VCC
2 A_D-
2 USBP3_D+
1 2 3 A_D+
R147 4
0_0402_5%~D A_GND
1 2 5 B_VCC
USBP2_D- 6
USBP2_D+ B_D-
7 B_D+
0.1U_0402_16V4Z~D
8 B_GND
@ L13 DLW21SN900SQ2_0805~D 1 9 G1
C8
10 G2
4 3 USBP3_D- 11
23 USBP3- 4 3 G3
12 G4
2
1 2 USBP3_D+ FOX_UB9112C-SB201-4F~D
23 USBP3+ 1 2
R148
0_0402_5%~D
1 2
R150
0_0402_5%~D
1 2 USB Port
A
Rear USB Ports A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USB 2.0 Port
LA-3301P
5 4 3 2 1
5 4 3 2 1
D D
C C
@ R235
0_0402_5%~D
1 2 New MDC connector.
1 GND RES 2
ICH_RST_MDC_R#
S
22 ICH_AZ_MDC_RST# 1 3
Q31
BSS138W-7-F_SOT323~D
3 IAC_SDATA0 RES 4
1
+5V_SUS
G
2
R233
100K_0402_5%~D
5 GND 3.3V 6
1
R239
7 IAC_SYNC GND 8
2
10K_0402_5%~D
9 IAC_SDATAIN GND 10
2
18 MDC_RST_DIS#
11 IAC_RESET# IAC_BITCLK 12
B B
JMDC ICH_AZ_MDC_SDOUT
+3.3V_SUS 22 ICH_AZ_MDC_BITCLK ICH_AZ_MDC_BITCLK
1 2
GND1 RES0 W=20 mil
10_0402_5%~D
22 ICH_AZ_MDC_SDOUT ICH_AZ_MDC_SDOUT 3 4
IAC_SDATA_OUT RES1
2
@ 10_0402_5%~D
5 GND2 3.3V 6
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
R123
22 ICH_AZ_MDC_SYNC ICH_AZ_MDC_SYNC 7 8
IAC_SYNC GND3
R124
1 2 MDC_SDIN 9 10 1 1
22 ICH_AZ_MDC_SDIN1 IAC_SDATA_IN GND4
C126
C125
ICH_RST_MDC_R# 11 12 ICH_AZ_MDC_BITCLK
R128 IAC_RESET# IAC_BITCLK
1
33_0402_5%~D
2 2
ICH_AC_SDOUT_MDCTERM
GND
GND
GND
GND
GND
GND
MDC_AC_BITCLK_TERM
TYCO_1-1775149-2~D
13
14
15
16
17
18
Connector for MDC Rev1.5
1 1
C128
10P_0402_50V8J~D C127
om
10P_0402_50V8J~D
A 2 2 A
l.c
ai
tm
ho
f@
BT PORT and MDC
in
xa
LA-3301P
he
5 4 3 2 1
5 4 3 2 1
L8 DLW21SN900SQ2_0805~D
1 USBP9_D-
23 USBP9- 1 @ 2 2 JCLIP1
1 GND1
4 3 USBP9_D+ 2
23 USBP9+ 4 3 GND2
R120 3 @ R598
0_0402_5%~D GND3 0_0402_5%~D
4 GND4
1 2 SB_WWAN_PCIE_RST# 2 1
21 SB_WWAN_PCIE_RST#
R121 TYCO_1775837-1~D
0_0402_5%~D
1 2
D Mini-Card Latch Mini WWAN D
+3.3V_RUN +3.3V_RUN
R18 @ JMINI1
1 2 PCIE_WAKE# 1 2
28,38 PCIE_WAKE# 1 2
+PWR_SRC +3.3V_ALW 3 4
0_0402_5%~D +3.3V_WLAN 3 4
5 5 6 6 +1.5V_RUN
100K_0402_5%~D
MINI1CLK_REQ# 7 8 +SIM_PWR
6 MINI1CLK_REQ# 7 8
D
6 9 10 UIM_DATA
S
9 10
1
100K_0402_5%~D
1 2 WLAN_RADIO_DIS#_R 5 4 CLK_PCIE_MINI1# 11 12 UIM_CLK
38 WLAN_RADIO_DIS# 6 CLK_PCIE_MINI1# 11 12
R785
R784
2 CLK_PCIE_MINI1 13 14 UIM_RESET
D1 Q94 6 CLK_PCIE_MINI1 13 14 UIM_VPP
1 15 15 16 16
RB751S40T1_SOD523-2~D SI3456BDV-T1-E3_TSOP6~D 17 18 R597
G
17 18 WWAN_RADIO_DIS# 0_0402_5%~D
19 20 WWAN_RADIO_DIS# 38
3
19 20 PLTRST3#_R PLTRST3#
21 21 22 22 2 1 PLTRST3# 21,28
PCIE_IRX_WANTX_N1 23 24 +3.3V_RUN
23 PCIE_IRX_WANTX_N1 23 24
2N7002W-7-F_SOT323-3~D
PCIE_IRX_WANTX_P1 25 26
23 PCIE_IRX_WANTX_P1 25 26
1
D
27 27 28 28
Q95
470K_0402_5%~D
2 1 29 30 ICH_SMBCLK
29 30 ICH_SMBCLK 23,28
1
Q96 G PCIE_ITX_WANRX_N1_C 31 32 ICH_SMBDATA
23 PCIE_ITX_WANRX_N1_C 31 32 ICH_SMBDATA 23,28
R782
2N7002W-7-F_SOT323-3~D S C270 PCIE_ITX_WANRX_P1_C 33 34
23 PCIE_ITX_WANRX_P1_C
3
33 34
1
JCLIP2 D 4700P_0402_25V7K~D USBP9_D-
35 35 36 36
2
R783
200K_0402_5%~D
1 2 PCIE_MCARD2_DET# 37 38 USBP9_D+
GND1 39 WLAN_3V_ENABLE 21 PCIE_MCARD2_DET# 37 38
2 G 39 40 USB_MCARD2_DET# 23
2
GND2 39 40
1
3 S +3.3V_RUN 1 2 41 42 T16 PAD~D
3
GND3 R786 R550 100K_0402_5%~D 41 42
4 43 44 2 1 +3.3V_RUN
2
GND4 100K_0402_5%~D 43 44 R574
45 45 46 46
TYCO_1775837-1~D 47 48 100K_0402_5%~D
47 48
49 50
2
49 50
51 51 52 52
C C
53 54
Mini-Card Latch GND1 GND2
@ R599 TYCO_1775838-1~D
0_0402_5%~D
SB_WLAN_PCIE_RST# 2 1
21 SB_WLAN_PCIE_RST# U53
+SIM_PWR
Mini WLAN 1
JSIM
VCC GND 4
UIM_RESET 1 6 UIM_VPP
UIM_RESET 2 5 UIM_VPP
UIM_CLK RST VPP UIM_DATA
3 CLK I/O 6 2 5 +SIM_PWR
1U_0603_10V4Z~D
+3.3V_WLAN +3.3V_WLAN
1 7 NC NC 8
JMINI2 +1.5V_RUN UIM_CLK 3 4 UIM_DATA
33P_0402_50V8J~D
33P_0402_50V8J~D
33P_0402_50V8J~D
33P_0402_50V8J~D
C459
1 2 SUYIN_254020MA006G502ZL~D
28,38 PCIE_WAKE# 1 2
R91 1 2 0_0402_5%~D 3 4
40 COEX2_WLAN_ACTIVE 3 4 2
R27 1 2 0_0402_5%~D 5 6 1 1 1 1
40 COEX1_BT_ACTIVE 5 6
7 8 SRV05-4.TCT_SOT23-6~D
6 MINI2CLK_REQ# 7 8
C123
C124
C460
C122
9 9 10 10
6 CLK_PCIE_MINI2# 11 11 12 12
2 2 2 2
6 CLK_PCIE_MINI2 13 13 14 14
15 16 HOST_DEBUG_TX
15 16 HOST_DEBUG_TX 39
HOST_DEBUG_RX 17 18
39 HOST_DEBUG_RX 8051_TX 17 18 WLAN_RADIO_DIS#_R
39 8051_TX 19 19 20 20
21 22 WLAN_PLTRST3#_R 2 1PLTRST3#
21 22 PLTRST3# 21,28
PCIE_IRX_WLANTX_N2 23 24 R600
23 PCIE_IRX_WLANTX_N2 PCIE_IRX_WLANTX_P2 23 24 0_0402_5%~D
23 PCIE_IRX_WLANTX_P2 25 25 26 26
27 27 28 28
29 30 WLAN_SMBCLK +3.3V_RUN
B PCIE_ITX_WLANRX_N2_C 29 30 WLAN_SMBDATA B
23 PCIE_ITX_WLANRX_N2_C 31 31 32 32
PCIE_ITX_WLANRX_P2_C 33 34 +1.5V_RUN
23 PCIE_ITX_WLANRX_P2_C 33 34
35 36 R549 100K_0402_5%~D
35 36
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
33P_0402_50V8J~D
22U_0805_6.3VAM~D
33P_0402_50V8J~D
23 PCIE_MCARD1_DET# 37 37 38 38 1 2 +3.3V_RUN
330U_D2E_6.3VM_R25~D
33P_0402_50V8J~D
0.047U_0402_16V4Z~D
39 39 40 40 USB_MCARD1_DET# 23 1
+3.3V_RUN 1 2 41 42 8051_RX 1 1 1 1 1
41 42 8051_RX 39
C449
C416
C444
C111
R548 43 44 LED_WLAN_OUT# +
43 44 LED_WLAN_OUT# 43 1 1
C773
C445
C120
100K_0402_5%~D 45 46 1 2
45 46 BT_ACTIVE 40,43
C121
47 48 @ R11 0_0402_5%~D
47 48 2 2 2 2 2 2
49 49 50 50
2 2
51 51 52 52
+3.3V_WLAN
53 GND1 GND2 54
2.2K_0402_5%~D
2.2K_0402_5%~D
TYCO_1775838-1~D
1
1
R640
R645
Primary Power Aux Power

PWR Voltage
@ Q45
2
Rail Tolerance
2
G
2N7002W-7-F_SOT323-3~D Peak Normal Normal

WLAN_SMBCLK 3 1 ICH_SMBCLK 23,28
S
+3.3V +-9% 1000 750

1 R660 2 CLK_SCLK 6 250 (Wake enable)
@ 0_0402_5%~D +3.3Vaux +-9% 330 250 5 (Not wake enable)
2
G
WLAN_SMBDATA 3 1 +1.5V +-5% 500 375 NA

+1.5V_RUN ICH_SMBDATA 23,28
+3.3V_WLAN
S
A @ Q46 A
2N7002W-7-F_SOT323-3~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
4.7U_0603_6.3V4Z~D
1 2 CLK_SDATA 6
1 @ R662
0_0402_5%~D
1 1 1 1 1 1 1 1
C15
C41
C36
C166
C164
C163
+ C283
@
C34
C16
330U_D2E_6.3VM_R25~D
2 2 2 2 2 2 2 2 2 Compal Electronics, Inc.
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Mini Card
LA-3301P
5 4 3 2 1
5 4 3 2 1
+5V_RUN
+VCC_QBUF
D2 D3
RB751S40T1_SOD523-2~D RB751S40T1_SOD523-2~D
2 1 +VCC_QBUFD 2 1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.047U_0402_16V4Z~D
1
1 1 1
R19
C28
C32
C33
1K_0402_5%~D
2 2 2
2
D D
QUIETE#
C29
U19 0.1U_0402_16V4Z~D
1 NC1 VCC4 80 1 2
PCI_AD31 2 79
PCI_AD30 A1 OE1# DOCK_AD31
3 A2 B1 78
PCI_AD29 4 77 DOCK_AD30
PCI_AD28 A3 B2 DOCK_AD29
5 A4 B3 76
7 A6 B5 74
9 A8 B7 72
10 71 DOCK_AD24
GND1 B8
11 NC2 VCC3 70
PCI_AD23 12 69
13 A10 B9 68
15 A12 B11 66
17 A14 B13 64
19 A16 B15 62
20 61 DOCK_AD16
GND2 B16
21 NC3 VCC2 60
PCI_AD15 22 59
23 A18 B17 58
25 A20 B19 56
27 A22 B21 54
C PCI_AD8 DOCK_AD10 C
28 A23 B22 53
A24 B23 DOCK_AD9
30 GND3 B24 51
31 NC4 VCC1 50
PCI_AD7 32 49
33 A26 B25 48
35 A28 B27 46
37 A30 B29 44
39 A32 B31 42
40 41 DOCK_AD0
GND4 B32
PI5C34X2245BE_BQSOP80~D
DOCK_AD[0..31] 36
21,30 PCI_AD[0..31]
+3.3V_RUN
C31
0.047U_0402_16V4Z~D
1 2
1
2
C26 C35
U18 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
QUIETE# 47 36 1 2 R22
OE1 VCC1 100K_0402_5%~D 2
35 OE2 VCC2 48
B B
1
PCI_PIRQA# 2 46 DOCK_PIRQA#
21 PCI_PIRQA# A0 B0 DOCK_PIRQA# 36
5
PCI_GNT0# 3 45 DOCK_GNT0# U5
21,36 PCI_GNT0# A1 B1 DOCK_GNT0# 36
PCI_RST# 4 44 DOCK_PCIRST# DOCK_PCI_EN# 1
P
21,30,31 PCI_RST# A2 B2 DOCK_PCIRST# 36 36 DOCK_PCI_EN# INB
SYS_PME# 5 43 DOCK_SPME# 4 QUIETE#
30,38 SYS_PME# A3 B3 DOCK_SPME# 36 O
PCI_C_BE3# 6 42 DOCK_C_BE3# QBUFEN# 2
21,30 PCI_C_BE3# A4 B4 DOCK_C_BE3# 36 38 QBUFEN# INA
G
PCI_C_BE2# 7 41 DOCK_C_BE2#
21,30 PCI_C_BE2# A5 B5 DOCK_C_BE2# 36
PCI_C_BE1# 8 40 DOCK_C_BE1# TC7SH32FU_SSOP5~D
21,30 PCI_C_BE1# DOCK_C_BE1# 36
3
PCI_C_BE0# A6 B6 DOCK_C_BE0#
21,30 PCI_C_BE0# 9 A7 B7 39 DOCK_C_BE0# 36
PCI _IRDY# 10 38 DOCK_IRDY#
21,30,36 PCI_IRDY# A8 B8 DOCK_IRDY# 36
PCI_FRAME# 11 37 DOCK_FRAME#
21,30,36 PCI_FRAME# A9 B9 DOCK_FRAME# 36
PCI_TRDY# 14 34 DOCK_TRDY#
21,30 PCI_TRDY# A10 B10 DOCK_TRDY# 36
PCI_STOP# 15 33 DOCK_STOP#
21,30 PCI_STOP# A11 B11 DOCK_STOP# 36
PCI_PLOCK# 16 32 DOCK_LOCK#
21 PCI_PLOCK# A12 B12 DOCK_LOCK# 36
PCI_DEVSEL# 17 31 DOCK_DEVSEL#
21,30 PCI_DEVSEL# A13 B13 DOCK_DEVSEL# 36
PCI_PERR# 18 30 DOCK_PERR#
21,30 PCI_PERR# A14 B14 DOCK_PERR# 36
PCI_SERR# 19 29 DOCK_SERR#
21,30 PCI_SERR# A15 B15 DOCK_SERR# 36
PCI_PAR 20 28 DOCK_PAR
21,30 PCI_PAR A16 B16 DOCK_PAR 36
PCI_AD24 21 27 DOCK_PCI_IDSEL
A17 B17 DOCK_PCI_IDSEL 36
22 A18 B18 26
23 A19 B19 25
1 NC1 GND1 12
13 NC2 GND2 24
PI5C162861BE_BQSOP48~D
om
A A
l.c
ai
tm
ho
f@
Title
DOCKING BUFFER
in
xa
he
5 4 3 2 1
5 4 3 2 1
+DC_IN
+DOCK_PWR_SRC
JDOCKA JDOCKB JDOCKC
1 69 DOCK_DET# 137 205 DOCK_DET# P1 P5 +DC_IN
S1 S69 CRT_RED CRT_GRN S137 S205 P1 P5
2 S2 S70 70 138 S138 S206 206 DAT_DDC2 12,20
51 DVI_CLK- 3 S3 S71 71 139 S139 S207 207 CLK_DDC2 12,20 P2 P2 P6 P6
4 72 CRT_BLU 140 208
51 DVI_CLK+ S4 S72 S140 S208
0.1U_0603_50V4Z~D
1000P_0402_50V7K~D
5 73 141 209 HSYNC_R P3 P7
S5 S73 D_SERIRQ 38 S141 S209 HSYNC_R 20 P3 P7
6 74 D_LAD1 142 210 VSYNC_R 2 1
S6 S74 DOCK_PCI_IDSEL 35 38 D_LAD1 S142 S210 VSYNC_R 20
C13
C14
DVI_TX4- 7 75 D_LAD2 143 211 P4 P8
S7 S75 38 D_LAD2 S143 S211 P4 P8
0.1U_0603_50V4Z~D
DVI_TX4+ 8 76 D_LAD3 144 212
D S8 S76 38 D_LAD3 S144 S212 D_CLKRUN# 38 D
9 77 145 213 D_LAD0
S9 S77 D_DLRQ1# 38 S145 S213 D_LAD0 38 1 2
10 78 DOCK_AD1 146 214 DOCK_SMB_ALERT# 2 MH1 MH2
S10 S78 D_LFRAME# 38 S146 S214 DOCK_SMB_ALERT# 39 MH1 MH2
C20
DVI_TX3+ 11 79 DOCK_AD0 147 215
DVI_TX3- S11 S79 S147 S215 DOCK_AD2
12 S12 S80 80 148 S148 S216 216 MH5 SHLD1 SHLD3 MH7
13 81 DOCK_AD3 149 217 DOCK_AD5
S13 S81 DVI_SCLK 51 S149 S217 1
82 DOCK_AD4 150 218 DOCK_AD6 MH6 MH8
S82 DVI_SDATA 51 S150 S218 SHLD2 SHLD4
15 83 DOCK_AD7 151
44 DOCK_PSID S15 S83 DVI_DETECT 51 S151
84 DOCK_AD8 152 220 MH9 MH11
S84 DOCK_C_BE0# DOCK_AD9 S152 S220 SHLD5 SHLD7
17 S17 S85 85 DOCK_C_BE0# 35 153 S153
DVI_TX5+ 18 86 DOCK_AD10 154 222 DOCK_AD12 MH10 MH12
DVI_TX5- S18 S86 DOCK_AD11 S154 S222 DOCK_AD13 SHLD6 SHLD8
19 S19 S87 87 155 S155 S223 223
20 88 DOCK_AD14 156 224 DOCK_C_BE1#
S20 S88 S156 S224 DOCK_C_BE1# 35
21 89 DOCK_AD15 157 225
S21 S89 35 DOCK_PAR S157 S225 DOCK_PERR#
51 DVI_TX2+ 22 S22 S90 90 35 DOCK_SERR# 158 S158 S226 226 DOCK_PERR# 35
23 91 159 227 DOCK_STOP# MH13 MH14
51 DVI_TX2- S23 S91 35 DOCK_LOCK# S159 S227 DOCK_STOP# 35 MH13 MH14
24 92 160 228 DOCK_TRDY# MH15 MH16
S24 S92 DOCK_DEVSEL# 35 S160 S228 DOCK_TRDY# 35 MH15 MH16
25 S25 S93 93 DOCK_IRDY# 35 35 DOCK_FRAME# 161 S161 S229 229
26 94 DOCK_C_BE2# 162 230 DOCK_AD17
51 DVI_TX1+ S26 S94 35 DOCK_C_BE2# S162 S230
27 95 DOCK_AD16 163 231 DOCK_AD18 TYCO_2-1612415-1~D
51 DVI_TX1- S27 S95 S163 S231
28 96 DOCK_AD19 164 232 DOCK_AD21
S28 S96 DOCK_AD20 DOCK_AD22 S164 S232
29 S29 S97 97 165 S165 S233 233
30 98 DOCK_AD23 166 234 DOCK_C_BE3#
51 DVI_TX0+ S30 S98 S166 S234 DOCK_C_BE3# 35
31 99 DOCK_AD24 167 235 DOCK_AD25
51 DVI_TX0- S31 S99 S167 S235
32 100 DOCK_AD27 168 236 DOCK_AD26
S32 S100 DOCK_AD28 DOCK_AD29 S168 S236 DOCK_AD0
33 S33 S101 101 169 S169 S237 237
DOCK_AD31 34 102 DOCK_AD30 170 238 PCI_REQ0# DOCK_AD1
S34 S102 35 DOCK_SPME# S170 S238 DOCK_PCIRST# PCI_REQ0# 21 DOCK_AD2
6 CLK_PCI_DOCK 35 S35 S103 103 DOCK_GNT0# 35 171 S171 S239 239 DOCK_PCIRST# 35
36 104 TV_C 172 240 DOCK_AD3
35 DOCK_PIRQA# S36 S104 USBP8- S172 S240 TV_CVBS DOCK_AD4
37 S37 S105 105 USBP8- 23 173 S173 S241 241
38 106 USBP8+ 174 242 DOCK_AD5
S38 S106 USBP8+ 23 35 DOCK_PCI_EN# S174 S242
39 107 175 243 TV_Y DOCK_AD6
39 DOCK_SMB_CLK S39 S107 26 AUD_SPDIF_OUT S175 S243 DOCK_AD7
39 DOCK_SMB_DAT 40 S40 S108 108 DOCK_SMB_PME# 38 176 S176 S244 244
C DOCK_AD8 C
39 CLK_DOCK 41 S41 S109 109 CLK_KBD 39 29 DOCK_LOM_SPD10LED_GRN# 177 S177 S245 245
42 110 178 246 DOCK_AD9
39 DAT_DOCK S42 S110 DAT_KBD 39 29 DOCK_LOM_SPD100LED_ORG# S178 S246 DOCK_LOM_ACTLED_YEL# 29
43 111 179 247 DOCK_AD10
S43 S111 DOCK_OWNS_PCI S179 S247 R_PIDEACT DOCK_AD11
S112 112 180 S180 S248 248 R_PIDEACT 43
45 113 +2.5V_LAN 181 DOCK_AD12 TV_C 1 2
S45 S113 S181 DOCK_AD13 R12 150_0402_1%~D
S114 114 182 S182 S250 250
47 115 183 DOCK_AD14 TV_CVBS 1 2
S47 S115 C23 C21 S183 DOCK_AD15 R13 150_0402_1%~D
48 S48 S116 116 184 S184 S252 252
CLK_PCI_DOCK 49 117 0.01U_0402_16V7K~D 0.01U_0402_16V7K~D 185 253 DOCK_AD16 TV_Y 1 2
S49 S117 S185 S253 AUD_SPDIF_OUT DOCK_AD17 R14 150_0402_1%~D
50 S50 S118 118 1 2 2 1 186 S186 S254 254
51 119 187 255 DOCK_AD18
S51 S119 C24 C22 S187 S255 DOCK_AD19
52 S52 S120 120 188 S188 S256 256
1
1
@ 53 121 0.01U_0402_16V7K~D 0.01U_0402_16V7K~D 189 257 DOCK_AD20
S53 S121 S189 S257
@
R20 54 122 1 2 2 1 190 258 R791 DOCK_AD21
10_0402_5%~D S54 S122 S190 S258 10_0402_5%~D DOCK_AD22
55 S55 S259 259
125 193 DOCK_AD23
S125 DOCK_LAN_TX3- 29 29 DOCK_LAN_TX1- S193
126 194 DOCK_AD24
DOCK_LAN_TX3+ 29
2
2
S126 29 DOCK_LAN_TX1+ S194 DOCK_AD25
1 S127 127 DOCK_LAN_TX2- 29 29 DOCK_LAN_TX0- 195 S195
@ 128 196 1 DOCK_AD26
S128 DOCK_LAN_TX2+ 29 29 DOCK_LAN_TX0+ S196
@
C25 C267 DOCK_AD27
4.7P_0402_50V8C~D 136 DOCK_RING DOCK_TIP 204 10P_0402_50V8J~D DOCK_AD28
2 M136 M204 DOCK_AD29
TYCO_2-1612415-1~D TYCO_2-1612415-1~D 2 DOCK_AD30
DOCK_AD31
PLACE TERMINATIONS CLOSE TO DOCK CONNECTOR Q6
DOCK_AD[0..31] 35
FDS4435BZ_SO8~D
+3.3V_RUN 8 +DOCK_PWR_SRC
+PWR_SRC 1 7
2 6 1
1 2 3 5
2
+3.3V_RUN C11 R10 C18
B C37 0.47U_0805_25V7K~D 200K_0402_5%~D 1000P_0402_50V7K~D B
0.1U_0402_16V4Z~D 2
4
2 +3.3V_ALW 1
1
5
1
C40 G_DOC_PWRSRC
P
NC
2
PCI_GNT0# 2 4 0.1U_0402_16V4Z~D
21,35 PCI_GNT0# A Y 2 R4
G
U6 U8 100K_0402_5%~D
1
NC7SZ04P5X_NL_SC70-5~D Z3305 1 +5V_ALW
P
3
IN1 DOCK_OWNS_PCI R17

4
1
+3.3V_RUN O 100K_0402_5%~D
2 IN2 DOCKED 29,38
G
C38 NB no power dock

1 2 74AHC1G08GW_SOT353-5~D R16
3
2
1
100K_0402_5%~D
5
U7 0.1U_0402_16V4Z~D
PCI _IRDY# 1
P
21,30,35 PCI_IRDY#
1
IN1 Z3306
O 4
PCI_FRAME# 2 DOCK_DET#
Z3307
21,30,35 PCI_FRAME# IN2 2
G
74AHC1G08GW_SOT353-5~D
3
Q3
3
DDTC144EUA-7-F_SOT323-3~D PWR_SRC self power dock

TV_C U13
12 TV_C
3
74AHC1G08GW_SOT353-5~D
1
D
2
G
TV_Y IN2 Z3308 Q2
12 TV_Y O 4 2
DOCK_PWR_EN 1 G 2N7002W-7-F_SOT323-3~D
38 DOCK_PWR_EN IN1
P
S
3
100K_0402_5%~D
TV_CVBS
12 TV_CVBS
2
C150
JW IRE +3.3V_SUS
A CRT_RED A
12,20 CRT_RED 1 1 2 1
R8
DOCK_RING 2 2
3 3
1
CRT_GRN DOCK_TIP 4 4 0.1U_0402_10V7K~D
12,20 CRT_GRN
1 2
CRT_BLU
MOLEX_53398-0471~D
R7
12,20 CRT_BLU
@ 0_0402_5%~D
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DOCKING CONN
Date: Tuesday, February 27, 2007 Sheet 36 of 58
5 4 3 2 1
5 4 3 2 1
+3.3V_SUS
1
D C167 D
0.1U_0402_16V4Z~D
C10
2 0.47U_0402_10V4Z~D
1 2
C12
26
0.1U_0402_10V7K~D U3 JSIO
1 2 3243C1+ 28 DCD0 1
VCC
C1+ 3243V+ C7 DSR0 DCD0
V+ 27 6 DSR0
C6 0.47U_0402_10V4Z~D RXD0# 2
0.1U_0402_10V7K~D 3243C1- 3243V- RTS0 RXD0#
24 C1- V- 3 1 2 7 RTS0F
1 2 3243C2+ 1 TXD0# 3
C2+ CTS0 TXD0F#
8 CTS0
DTR0 4
3243C2- R I0 DTR0F
2 C2- 9 RI0
TXD0 14 9 TXD0# 5
38 TXD0 T1IN T1OUT GND0
RTS0# 13 10 RTS0
38 RTS0# T2IN T2OUT
DTR0# 12 11 DTR0 10
38 DTR0# T3IN T3OUT GND1
DCD0# 19 4 DCD0 11
38 DCD0# R1OUT R1IN GND2
270P_0402_50V7K~D
270P_0402_50V7K~D
270P_0402_50V7K~D
270P_0402_50V7K~D
270P_0402_50V7K~D
270P_0402_50V7K~D
270P_0402_50V7K~D
270P_0402_50V7K~D
RI0# 18 5 R I0
38 RI0# R2OUT R2IN
RXD0 17 6 RXD0#
38 RXD0 CTS0# R3OUT R3IN CTS0 SUYIN_070921MR009S203BR~D
38 CTS0# 16 R4OUT R4IN 7 1 1 1 1 1 1 1 1
DSR0# 15 8 DSR0
38 DSR0# R5OUT R5IN
C152
C153
C154
C155
C156
C157
C158
C159
20 R2OUTB
INVALID# 21
2 2 2 2 2 2 2 2
+3.3V_SUS 23 FORCEON
GND 25
19,39,41,42 RUN_ON 22 FORCEOFF#
MAX3243ECUI+T_TSSOP28~D
C C
+3.3V_ALW
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 1 U39
KSO[0..17] 40
C175
C171
30 9 KSO0
VCC1 KSO0 KSO1
10 VCC1 KSO1 11
2 2 KSO2
KSO2 12
39 KSO3
NC3 ECE1077 KSO3
KSO4
13
14 KSO4
15 KSO5
KSO5 KSO6
KSO6 16
+3.3V_ALW 17 KSO7
KSO7 KSO8
37 NC1 KSO8 18
38 19 KSO9
NC2 KSO9
1
20 KSO10
@ R131 KSO10 KSO11
KSO11 21
100K_0402_5%~D 22 KSO12
KSO12 KSO13
KSO13 23
24 KSO14
2
KSO14 KSO15
KSO15 25
BC_A_DAT 34 26 KSO16
39 BC_A_DAT BC_DATA KSO16/GPIO_0 KSO17
KSO17/GPIO_1 27
BC_A_CLK 35 28
39 BC_A_CLK BC_CLK KSO18/GPIO_2
KSO19/GPIO_3 29
BC_A_INT# 36 31 KYBD_DET# 40
39 BC_A_INT# BC_INT# KSO20/GPIO_4
KSO21/GPIO_5 32
KSO22/GPIO_6 33
B B
KSI0 KSI[0..7] 40
KSI0 1
2 KSI1
KSI1 KSI2
KSI2 3
R28 4 KSI3
1K_0402_5%~D KSI3 KSI4
KSI4 5
2 1 40 6 KSI5
TEST_PIN KSI5 KSI6
KSI6 7
41 8 KSI7
GND_PAD KSI7
ECE1077-FZG_QFN40~D
om
A A
l.c
ai
tm
ho
f@
Serial & FIR
in
xa
LA-3301P
he
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW +3.3V_ALW
1 2 SYS_PME#
R248 10K_0402_5%~D
+5V_ALW
1 2 PCIE_WAKE# 1 2 DOCK_SMB_PME# 1 1 1 1
R247 10K_0402_5%~D R245 10K_0402_5%~D
C101 C420 C403 C95
+3.3V_RUN 0.1U_0402_16V4Z~D 0.1U_0402_10V7K~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
2 2 2 2
1 2 IMVP6_PROCHOT#
D R1 100K_0402_5%~D D
108
1 PANEL_BKEN
34
57
85
2
R237 U25 C98 +3.3V_ALW
100K_0402_5%~D 0.1U_0402_16V4Z~D
VCC1
VCC1
VCC1
VCC1
2
PBAT_PRES# 97
44 PBAT_PRES# GPIOA[0]
SBAT_PRES# 98 R814
44,50 SBAT_PRES# GPIOA[1]
CHG_PBATT 99 8 SIO_VDDA 1 2
50 CHG_PBATT GPIOA[2] VCC1(VDDA33)
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
4.7U_0603_6.3V4Z~D
Place closely pin 64 CHG_SBATT 100 14
50 CHG_SBATT GPIOA[3] GPIOJ[7](VDDA33) 0_0603_5%~D
50 PBAT_DSCHG 101 GPIOA[4] GPIOK[4](VDDA33) 20
CLK_SIO_14M SYS_PME# 102 1 1 1 1 1
30,35 SYS_PME#
28,34 PCIE_WAKE#
PCIE_WAKE# 103
GPIOA[5]
GPIOA[6]
ECE5028-NU GPIOI[1](VCC1) 119
C90
C94
C88
C93
USB_BACK_EN# 104 @ C89
32 USB_BACK_EN# GPIOA[7]
1
9 4.7U_0603_6.3V4Z~D
R246
10_0402_5%~D
43 WIRELESS_ON/OFF#
WIRELESS_ON/OFF#
BT_RADIO_DIS#
24
25
GPIOH[0]
(ECE5018) GPIOJ[2](USBDP0)
GPIOJ[3](USBDN0) 10
13
2 @ 2 2 @ 2 @ 2
40 BT_RADIO_DIS# GPIOH[1] GPIOJ[6](USBDP1)
@ 26 GPIOH[4] GPIOJ[5](USBDN1) 12
27 15 +3.3V_RUN
2
BC_INT# GPIOH[5] GPIOK[0](USBDP2)

58 16
1 +3.3V_SUS
39
39 BC_INT#
BC_DAT
BC_DAT 59
BC_INT#
BC_DAT
USB GPIOK[1](USBDN2)
GPIOK[3](USBDP3) 19
BC_CLK 60 18 D_CLKRUN# 2 1
39 BC_CLK BC_CLK GPIOK[2](USBDN3)
C415 21 R231 100K_0402_5%~D
4.7P_0402_50V8C~D RXD0 GPIOK[5](USBDP4) D_SERIRQ
37 RXD0 1 GPIOE[0]/RXD GPIOK[6](USBDN4) 22 2 1
1
@ 2 TXD0 R232 100K_0402_5%~D

37 TXD0 2 GPIOE[1]/TXD
R250 RTS0# 3 125 D_DLRQ1# 2 1
37 RTS0# GPIOE[2]/RTS# GPIOI[6](VDDA33PLL)
10K_0402_5%~D DSR0# 4 124 R234 100K_0402_5%~D
37 DSR0# GPIOE[3]/DSR# GPIOI[5](VDDA18PLL)
CTS0# 5 120
37 CTS0# GPIOE[4]/CTS# GPIOI[2](VDD18) +3.3V_ALW
DTR0# 84 86
37 DTR0#
2
RI0# GPIOE[5]/DTR# CAP_LDO RBIAS

37 RI0# 83 GPIOE[6]/RI# GPIOJ[0](RBIAS) 127
DCD0# 6
37 DCD0# GPIOE[7]/DCD#
1
12K_0402_1%~D
R227
C USB_SIDE_EN# TEST_PIN is a No Connect @ R221 C
32 USB_SIDE_EN# 65 GPIOB[0]/INIT#
66 Route RBIAS and its 10K_0402_5%~D
QBUFEN# GPIOB[1]/SLCTIN# @ return to pin 128 very
35 QBUFEN# 67 GPIOC[2]/SCLT TEST_PIN 35
DOCK_PWR_EN 68 short.
36 DOCK_PWR_EN TEST
2
ADAPT_OC GPIOC[3]/PE
69
49 ADAPT_OC
49 ADAPT_TRIP_SET
ADAPT_TRIP_SET 70
GPIOC[4]/BUSY
GPIOC[5]/ACK#
GPIO +3.3V_ALW
1 2 ITP_DBRESET#_R 71 126 REG_EN
7,23 ITP_DBRESET# GPIOC[6]/ERROR# GPIOI[7](ATEST)
@ R806 0_0402_5%~D PSID_DISABLE# 73
44 PSID_DISABLE# PANEL_BKEN GPIOC[7]/ALF#
12 PANEL_BKEN 74 GPIOD[0]/STROBE# GPIOI[4](XTAL1/CLKIN) 123 1 2
1
DOCKED 75 122 @ R72
29,36 DOCKED
36 DOCK_SMB_PME#
DOCK_SMB_PME# 76
GPIOC[1]/PD7
GPIOC[0]/PD6
CLK GPIOI[3](XTAL2) 10K_0402_5%~D R95
NB_MUTE# 77 1M_0402_5%~D
27 NB_MUTE# GPIOB[7]/PD5
78 GPIOB[6]/PD4 LPC_LAD[0..3] 22,28,39
AUD_SPDIF_SHDN 79 54 LPC_LAD0 R94
26 AUD_SPDIF_SHDN
2
DOCK_HP_MUTE# GPIOB[5]/PD3 LAD0 LPC_LAD1 10_0402_5%~D
26 DOCK_HP_MUTE# 80 GPIOB[4]/PD2 LAD1 52
AUD_HP_NB_SENSE 81 49 LPC_LAD2 LID_CL_SIO# 2 1 LID_CL#
26,27 AUD_HP_NB_SENSE GPIOB[3]/PD1 LAD2 LID_CL# 40
82 47 LPC_LAD3
GPIOB[2]/PD0 LAD3 LPC_LFRAME#
LFRAME# 42 LPC_LFRAME# 22,28,39 1
LID_CL_SIO# 61 41 PLTRST2# C84
47 1.05V_RUN_ON
1.05V_RUN_ON 62
GPIOD[1]
GPIOD[2]
LPC LRESET#
PCICLK 56 CLK_PCI_5018
PLTRST2# 21,39
CLK_PCI_5018 6
0.047U_0402_16V4Z~D
37 CLKRUN#
CLKRUN# CLKRUN# 23,30,39 2
63 46 LPC_LDRQ0#
GPIOD[3]/VBUS_DET LDRQ0# LPC_LDRQ0# 22
MODPRES# 28 44 LPC_LDRQ1#
25 MODPRES# GPIOD[4]/OCS1_N LDRQ1# LPC_LDRQ1# 22
29 39 IRQ_SERIRQ
GPIOD[5]/OCS2_N SER_IRQ IRQ_SERIRQ 23,28,30,39
HD DC_EN 30
25 HDDC_EN GPIOD[6]/OCS3_N
MODC_EN 31 64 CLK_SIO_14M
25 MODC_EN GPIOD[7]/OCS4_N CLKI (14.318 MHz) CLK_SIO_14M 6
48 IMVP6_PROCHOT# 32 GPIOH[6] VSS 96

42 5V_3V_1.8V_1.25V_RUN_PWRGD 33 GPIOH[7] D_LAD0
Place closely pin 56
DLAD0 55 D_LAD0 36
LOM_LOW_PWR 88 53 D_LAD1 CLK_PCI_5018
28 LOM_LOW_PWR GPIOG[0] DLAD1 D_LAD1 36
VGA_IDENTIFY SC_DET# 89 50 D_LAD2
B 31 SC_DET# GPIOG[1] DLAD2 D_LAD2 36 B
LED_MASK# 90 48 D_LAD3
43 LED_MASK# GPIOG[2] DLPC DLAD3 D_LAD3 36
1
91 43 D_LFRAME#
GPIOG[3] DLFRAME# D_LFRAME# 36
1
23 SIO_EXT_WAKE# R242 1 2 0_0402_5%~D 92 38 D_CLKRUN# R240

GPIOG[4] DCLK_RUN# D_CLKRUN# 36
R220 ICH_PME# 93 45 D_DLRQ1# 10_0402_5%~D
21 ICH_PME# GPIOG[5] DLDRQ1# D_DLRQ1# 36
100K_0402_5%~D ICH_PCIE_WAKE# 94 40 D_SERIRQ
@
23 ICH_PCIE_WAKE# GPIOG[6] DSER_IRQ D_SERIRQ 36
WLAN_RADIO_DIS# 95
34 WLAN_RADIO_DIS#
2
GPIOG[7]
2
WWAN_RADIO_DIS# 106 1
34 WWAN_RADIO_DIS# SYSOPT1/GPIOH[2]
28 LOM_CABLE_DETECT 1 2 107 SYSOPT0/GPIOH[3]
R308 0_0402_5%~D 7 RUNPWROK C402
PWRGD RUNPWROK 39,42,48
1 = Discrete Gfx LOM_TPM_EN# 109 4.7P_0402_50V8C~D
28 LOM_TPM_EN# GPIOF[7] 2
LOM_SUPER_IDDQ 110 105 LCD_TST
@
28 LOM_SUPER_IDDQ GPIOF[6] OUT65 LCD_TST 19
0 = UMA VGA_IDENTIFY 111
CHIPSET_ID GPIOF[5]
112 GPIOF[4]
R112 11
10K_0402_5%~D GPIOJ[4](VSS)
113 IRTX VSS 17
2 1 114 IRRX GPIOK[7](VSS) 23
VSS 36
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
4.7U_0603_6.3V4Z~D
4.7U_0603_6.3V4Z~D
BID1 115 51
BID0 GPIOF[3]/IRMODE/IRRX3B VSS
116 GPIOF[2]/IRTX2 VSS 72
ATF_INT# 117 87 1 1 1 1
18 ATF_INT# GPIOF[1]/IRRX2 VSS
118 GPIOF[0]/IRMODE/IRRX3A VSS 121
@ C97
C92
C421
C401
GPIOJ[1](VSS) 128
2 2 @ 2 2 @
ECE5028-NU_VTQFP128_14X14~D
+3.3V_ALW
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
2
2
R108
R107
R238
A
REV BID1 BID0 A
1
@ @ @ X00 0 0
BID0 R106 1 2 10K_0402_5%~D
X01 0 1
BID1 R109 1 2 10K_0402_5%~D
X02 1 0 DELL CONFIDENTIAL/PROPRIETARY
CHIPSET_ID R236 10K_0402_5%~D
1 2
X03 1 1 Compal Electronics, Inc.
A00 0 0 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ECE5028
LA-3301P
5 4 3 2 1
5 4 3 2 1
+RTC_CELL
+3.3V_ALW +3.3V_ALW
1
+RTC_CELL
1 2 SNIFFER_GREEN# 2 1 SUS_ON R211
@ R77 100K_0402_5%~D R387 2.7K_0402_5%~D 100K_0402_5%~D
2 1 M_ON
1 2 SNIFFER_YELLOW# R388 1M_0402_5%~D 1 2 R210
2
@ R104 100K_0402_5%~D 2 1 RUN_ON R70 1 1 1 1 1 1 10K_0402_5%~D
R389 2.7K_0402_5%~D 0_0402_5%~D POWER_SW_IN# 1 2 POWER_SW#
C75 POWER_SW# 18,40
1U_0603_10V4Z~D
1 2 CKG_SMBDAT 1 2 DDR_ON C83 C79 C76 C82 C369 1
R105 2.2K_0402_5%~D R526 100K_0402_5%~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 10U_0805_10V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
2 2 2 2 2 2
C368
1 2 AUX_ON
1 2 CKG_SMBCLK R788 2.7K_0402_5%~D
R111 2.2K_0402_5%~D A C_OFF 2
1 2
@ R789 2.7K_0402_5%~D
121
116
2 BC_DAT
21
44
65
83
1
R401 100K_0402_5%~D U22 +RTC_CELL
D D
VCC0
VCC1
VCC1
VCC1
VCC1
VCC1
2 1 ATI_ Intel_IDENTIFY POWER_SW_IN1# 2 1
R795 CKG_SMBDAT 12 R69 100K_0402_5%~D
6 CKG_SMBDAT KSO17/GPIOA1/AB1H_DATA
0_0402_5%~D CKG_SMBCLK 13
6 CKG_SMBCLK KSO16/GPIOA0/AB1H_CLK
ATI_ Intel_IDENTIFY 14
3.3V_M_PWRGD GPIO5/KSO15 +5V_ALW
PAD~D T36 15 GPIO4/KSO14
1.8V_SUS_PWRGD 16 120 A LWON
46 1.8V_SUS_PWRGD KSO13/GPIO18 ALWON ALWON 45
EC_CPU_PROCHOT# 17 119 S NIFFER_PWR_SW# DOCK_SMB_DAT 2 1
7 EC_CPU_PROCHOT# KSO12/OUT8 POWER_ SW_IN2#/GPIO23 SNIFFER_PWR_SW# 43
18 126 POWER_SW_IN1# R67 8.2K_0402_5%~D
+5V_RUN I CH_CL_PWROK KSO11/GPIOC7 POWER_ SW_IN1#/GPIO22 POWER_SW_IN# DOCK_SMB_CLK
10,23 ICH_CL_PWROK 19 KSO10/GPIOC6 POWER_ SW_IN0# 127 2 1
20 128 ACAV_IN R66 8.2K_0402_5%~D
KSO9/GPIOC5 ACAV_IN ACAV_IN 18,49,50
ICH_RSMRST# 23 118 SNIFFER_RTC_GPO T37 PAD~D
23 ICH_RSMRST# KSO8/GPIOC4 BGPO0/GPIOA5
1 2 CLK_KBD PAD~D T33 M_ON 24
R88 4.7K_0402_5%~D SIO_SLP_M# KSO7/GPIO3 LCD_SMBCLK
PAD~D T34 25 KSO6/GPIO2 AB1B_CLK/GPIOA4 8 LCD_SMBCLK 19
DDR_ON 27 7 LCD_SMBDAT +3.3V_ALW
46 DDR_ON KSO5/GPIO1 AB1B_DATA/GPIOA2 LCD_SMBDAT 19
1 2 DAT_KBD TP_DET# 28 6 DOCK_SMB_CLK
40 TP_DET# KSO4/GPIO0 AB1A_CLK DOCK_SMB_CLK 36
R87 4.7K_0402_5%~D ALW_PWRGD_3V_5V 29 5 DOCK_SMB_DAT DOCK_SMB_ALERT# 2 1
45 ALW_PWRGD_3V_5V KSO3/GPIOC3 AB1A_DATA DOCK_SMB_DAT 36
SIO_SLP_S3# 30 93 R794 10K_0402_5%~D
23 SIO_SLP_S3# KSO2/GPIOC2 GPIO11/AB2_DATA
1 2 CLK_DOCK SIO_SLP_S5# 31 94 LCD_VCC_TEST_EN LCD_SMBCLK 1 2
23 SIO_SLP_S5# KSO1/GPIOC1 GPIO12/AB2_CLK LCD_VCC_TEST_EN 19
R86 4.7K_0402_5%~D 3.3V_RUN_ON 32 95 T87 PAD~D R161 8.2K_0402_5%~D
41 3.3V_RUN_ON KSO0/GPIOC0 GPIO13/AB1G_DATA
96 T88 PAD~D LCD_SMBDAT 1 2
DAT_DOCK AUX_ON GPIO14/AB1G_CLK PBAT_SMBDAT R162 8.2K_0402_5%~D
1 2 41 AUX_ON 33 KSI7/GPIO19 GPIO87/AB1C_DATA 111 PBAT_SMBDAT 44
R85 4.7K_0402_5%~D SUS_ON 34 112 PBAT_SMBCLK THRM_SMBDAT 1 2
41,42 SUS_ON KSI6/GPIO17 GPIO86/AB1C_CLK PBAT_SMBCLK 44
RUN_ON 35 9 SBAT_SMBDAT R64 4.7K_0402_5%~D
19,37,41,42 RUN_ON KSI5/GPIO10 GPIO85/AB1D_DATA SBAT_SMBDAT 44
A C_OFF 36 10 SBAT_SMBCLK THRM_SMBCLK 1 2
44 AC_OFF KSI4/GPIO9 GPIO84/AB1D_CLK SBAT_SMBCLK 44
PAD~D T35 1.05V_1.25V_M_PWRGD 37 97 1.5V_RUN_ON R65 4.7K_0402_5%~D
KSI3/GPIO8 GPIO93/AB1F_DATA 1.5V_RUN_ON 47
BC_A_INT# 38 98 1.25V_RUN_ON SBAT_SMBDAT 1 2
37 BC_A_INT# KSI2/GPIO7/BC_A_INT# GPIO92/AB1F_CLK 1.25V_RUN_ON 46
BC_A_DAT 39 99 R75 2.2K_0402_5%~D
+3.3V_ALW 37 BC_A_DAT KSI1/GPIO6/BC_A_DAT GPIO91/AB1E_DATA THRM_SMBDAT 18,49
BC_A_CLK 40 100 SBAT_SMBCLK 1 2
37 BC_A_CLK KSI0/SGPIO30/BC_A_CLK GPIO90/AB1E_CLK THRM_SMBCLK 18,49
R81 2.2K_0402_5%~D
SIO_A20GATE 92 43 IMVP_PWRGD PBAT_SMBDAT 1 2
22 SIO_A20GATE SGPIO34/A20M GPIO82/FAN_TACH3 IMVP_PWRGD 23,42,48
10K_0402_5%~D
10K_0402_5%~D
SNIFFER_GREEN# 50 42 R62 2.2K_0402_5%~D

43 SNIFFER_GREEN# OUT5/KBRST GPIO16/FAN_TACH2
1
1
1M_0402_5%~D
41 FAN1_TACH PBAT_SMBCLK 1 2
GPIO15/FAN_TACH1 FAN1_TACH 18
CLK_TP_SIO 75 R63 2.2K_0402_5%~D
40 CLK_TP_SIO GPIO94/IMCLK
R395
R100
R90
DAT_TP_SIO 76 48 1 2 HOST_DEBUG_RX 1 2
40 DAT_TP_SIO GPIO95/IMDAT OUT2/PWM3 IMVP_VR_ON 48
CLK_KBD 77 47 R176 0_0402_5%~D R400 1M_0402_5%~D
36 CLK_KBD KCLK OUT9/PWM2 WLAN_3V_ENABLE 34
C DAT_KBD 78 46 C
36 DAT_KBD 3.3V_SUS_ON 41
2
CLK_DOCK KDAT OUT11/PWM1 BREATH_LED +3.3V_ALW

36 CLK_DOCK 79 GPIOA6/EMCLK OUT10/PWM0 45 BREATH_LED 43
5 DAT_DOCK 80 @ C146 +3.3V_LAN
5 36 DAT_DOCK GPIOA7/EMDAT
4 8051_RX 81 66 SIO_EXT_SCI# 0.1U_0402_16V4Z~D
4 34 8051_RX GPIO20/PS2CLK/8051RX nEC_SCI/SPDIN2 SIO_EXT_SCI# 23
3 8051_TX 82 55 PS_ID 1 2
Molex_53261 3 34 8051_TX GPIO21/PS2DAT/8051TX SGPIO45/MSDATA/SPDOUT2 PS_ID 44
2 1 2 DEBUG_ENABLE# 54 S IO_RCIN# LOM_SMB_ALERT# 1 2
@ JDEBUG 2 R101 0_0402_5%~D SGPIO44/MSCLK/SPCLK2 BEEP SIO_RCIN# 22 R730 4.7K_0402_5%~D
1 1 SGPIO46/SPDIN1 69 BEEP 26
5
68 RSV_1.25V_GFX_PCIE_ON T38 PAD~D @ U30 @ R396
PLTRST2# SGPIO47/SPDOUT1 DEBUG_ENABLE# SIO_SPI_CS# 15_0402_5%~D
57 67 1
P
21,38 PLTRST2# LRESET# SGPIO31/TIN1/SPCLK1 IN1
R1752 no stuff when doing CLK_PCI_5025 58 4 1 2 SPI_CS0#
6 CLK_PCI_5025 PCICLK O
LPC_LFRAME# 59 70 HOST_DEBUG_TX 2
flash recovery 22,28,38 LPC_LFRAME# LFRAME# SYSOPT0/SGPIO32/LPC_TX HOST_DEBUG_TX 34 23 ICH_SPI_CS0# IN2
G
LPC_LAD0 60 71 HOST_DEBUG_RX
22,28,38 LPC_LAD0 LAD0 SYSOPT1/SGPIO33/LPC_RX HOST_DEBUG_RX 34
LPC_LAD1 61 74AHC1G08GW_SOT353-5~D +3.3V_ALW
22,28,38 LPC_LAD1
3
LPC_LAD2 LAD1 CAP_LED#
22,28,38 LPC_LAD2 62 LAD2 SGPIO40 91 CAP_LED# 43
LPC_LAD3 63 90 SCRL_LED#
22,28,38 LPC_LAD3 LAD3 SGPIO41 SCRL_LED# 43
CLK RUN# 64 89 NUM_LED# 1 2
23,30,38 CLKRUN# CLKRUN# SGPIO42 NUM_LED# 43
IRQ_SERIRQ 56 4 SIO_SPI_CS# R397
23,28,30,38 IRQ_SERIRQ SER_IRQ SGPIO43
1
0_0402_5%~D
1 LOM_SMB_ALERT#
1
SGPIO35 LOM_SMB_ALERT# 23,28
Place closely pin 58 ICH_EC_SPI_CLK 102 2 SFPI_EN
23 ICH_EC_SPI_CLK HSTCLK SGPIO36 (SFPI_EN)
ICH_EC_SPI_DIN 105 3 DOCK_SMB_ALERT#
CLK_PCI_5025 23 ICH_EC_SPI_DIN ICH_EC_SPI_DO HSTDATAIN SGPIO37 DOCK_SMB_ALERT# 36
23 ICH_EC_SPI_DO 107 HSTDATAOUT
52 0.9V_DDR_VTT_ON
GPIO96/TOUT1 0.9V_DDR_VTT_ON 46
EC_FLASH_SPI_CLK 103 EC_FLASH_PAD
FLCLK
1
EC_FLASH_SPI_DIN 106 11 SIO_EXT_SMI# @SHORT PADS~D

FLDATAIN OUT7/nSMI SIO_EXT_SMI# 23
2
R83 EC_FLASH_SPI_DO 108 115 BAT2_LED# Bat2 = Amber LED
FLDATAOUT nPWR_LED BAT2_LED# 43
10_0402_5%~D 114 BAT1_LED# Bat1 = Green LED
BAT1_LED# 43
2
SIO_PWRBTN# nBAT_LED
109
@
23 SIO_PWRBTN# GPIO80 R76

43 SNIFFER_YELLOW# SNIFFER_YELLOW# 110 84 FW P# 20mA drive pins
2
GPIO81 nFWP SFPI_EN 2 1

1 GPIOA3/WINDMON 73
1
BC_CLK 87 1K_0402_5%~D
38 BC_CLK BC_CLK
C81 BC_DAT 86 117 R80
38 BC_DAT BC_DAT GPIO83/32KHZ_OUT
4.7P_0402_50V8C~D BC_INT# 85 1K_0402_5%~D
2 38 BC_INT# BC_INT#
49 RUNPW ROK
@
PWRGD RUNPWROK 38,42,48
2
MEC5004_XTAL1 122 53 RESET_OUT#
XTAL1 nRESET_OUT/OUT6 RESET_OUT# 42
MEC5004_XTAL2 2 1 124
B
R214 0_0402_5%~D XTAL2 MEC_TEST_PIN B
TEST_PIN 72 T39 PAD~D 1=Flash Recovery Enabled
MEC5004_XOSEL 123 0=Flash Recovery Disabled
VCC_PLL
VSS_PLL
XOSEL
1
VR_CAP
0_0402_5%~D
Populate
1
AGND
R222
for flash
VSS
VSS
VSS
VSS
VSS
R213
10K_0402_5%~D
corruption Non-iAMT
32 KHz Clock MEC5025-NU_VTQFP128~D issue. +3.3V_SUS
1 125
26
51
74
88
113
22
101
104
2
+3.3V_SUS
2
4.7U_0603_6.3V4Z~D
C398
Sam e as Laguna 1 2
L24 1 C80
C74
BLM18AG121SN1D_0603~D 2 1 1 2+3.3V_ALW +3.3V_ALW 0.1U_0402_16V4Z~D
1
L6
MEC5004_XTAL1 0.1U_0402_16V4Z~D BLM18AG121SN1D_0603~D R219 R218
2 10K_0402_5%~D 10K_0402_5%~D
2
1
1 2
L3 R92
2
Y1 BLM18AG121SN1D_0603~D 100K_0402_5%~D U23
32.768K_12.5P_1TJS125DJ4A420P~D @ SPI_CS0# 1 8 R398
MEC5004_XTAL2 EC_FLASH_SPI_DIN 1 CS# VCC 15_0402_5%~D
4 1 2 2 7
2
FW P# SO HOLD#
low=write protected R84 3 WP# SCLK 6 1 2 EC_FLASH_SPI_CLK
3 2 15_0402_5%~D 4 GND SI 5 1 2 EC_FLASH_SPI_DO
1
33P_0402_50V8J~D
22P_0402_50V8J~D
1 1 R399
C379
R93 M25P16-VMW6TP_SO8~D 15_0402_5%~D

Net & Part AMT Intel Non-AMT Broacom
C385
100K_0402_5%~D
Non-iAMT Flash ROM Non-iAMT
2 2
200 MIL SO8
2
3.3V_M_PWRGD Pin15 of 5025 NC
CH_RSMRST# Pin23 of 5025 NC Flash write protect bottom 4K
of internal bootblock flash
M_ON Pin24 of 5025 NC Layout Note:
om
Place R84 within 500 mils from SPI flash.
A
SIO_SLP_M# Pin25 of 5025 NC Place R398 & R399 within 500 mils of the A
l.c
MEC5025.
1.05V_1.25V_M_PWRGD Pin37 of 5025 NC
ai
tm
R238 Pin24 of 5025 NC
ho
LOM_SUPER_IDDQ NC Refer to UMA DELL CONFIDENTIAL/PROPRIETARY
f@
LOM_LOW_PWR NC Refer to UMA PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
in
EMC5025
xa
LOM_CABLE_DETECT NC Refer to UMA NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
he
LA-3301P
Date: Thursday, March 01, 2007 Sheet 39 of 58
5 4 3 2 1
5 4 3 2 1
Touch PAD
JTPAD +3.3V_RUN
1 1 2 2
34 COEX1_BT_ACTIVE 3 3 4 4
5 5 6 6
USBP7- 7 8 BT_RADIO_DIS#
23 USBP7- 7 8 BT_RADIO_DIS# 38
USBP7+ 9 10 COEX3 T4 PAD~D
23 USBP7+ 9 10
11 11 12 12 BT_ACTIVE 34,43
100P_0402_50V8J~D
COEX2_WLAN_ACTIVE 13 14
34 COEX2_WLAN_ACTIVE 13 14
10K_0402_5%~D
15 16 SP_GND 1 1
15 16
C103
USBP5_D- 17 18 SP_X
17 18
33P_0402_50V8J~D
R119
10K_0402_5%~D
USBP5_D+ 19 20 SP_Y C102
19 20
1
+3.3V_RUN 21 22 SP_V+ 0.1U_0402_16V4Z~D
21 22 2 2
R249
D D
1 23 24
2
23 24
C419
25 26 TP_CLK
39 TP_DET# 25 26 TP_DATA
38 LID_CL# 27 27 28 28
29 30 FAN
+3.3V_ALW +5V_RUN
2
2 29 30
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
31 G1 G2 32 Part Number Description
0.047U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 1 1
FOX_HT1315F-P2~D 1 1 DC28A000800 FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
C426
C424
C423
C210
C430
37 KSO[0..17]
+3.3V_RUN
KSO17 2 2 2 Speak
KSO16 2 2
Part Number Description
KSO15 SP_GND
KSO14 SP_X PK230003Q0L SPK PACK ZJX 2.0W 4 OHM FG
KSO13 SP_V+
KSO12 SP_Y
KSO11
1
DA204U_SOT323~D
DA204U_SOT323~D
DA204U_SOT323~D
KSO10 @ D37 SM CARD BODY
KSO9 DA204U_SOT323~D Part Number Description
@ D38
@ D39
@ D40
KSO8
KSO7 SP070007V0L S SOCKET TYCO 1770551-1
KSO6 10P H5.9 SMART
KSO5
3
KSO4 @ L4 PCMCIA BODY
KSO3 DLW21SN900SQ2_0805~D Part Number Description
KSO2 4 4 USBP5_D-
KSO1
23 USBP5- 3 3 PCMCIA TYCO
DC000001Q0L
KSO0 1759096-1
1 2 USBP5_D+
37 KSI[0..7] 23 USBP5+ 1 2
R407 +5V_RUN
KSI7 0_0402_5%~D MDC wire set cable
KSI6 1 2 Part Number Description
KSI5 R410
4.7K_0402_5%~D
4.7K_0402_5%~D
C KSI4 0_0402_5%~D C
DC02000CS0L H-CONN SET ZGX
1
KSI3 1 2 MB-MDC
KSI2
R228
R229
KSI1 T/P wire set cable
KSI0 Part Number Description
L25
2
+3.3V_ALW BLM18AG601SN1D_0603~D H-CONN SET ZJX
DC02000840L
TP_DATA 1 2 DAT_TP_SIO MB-B/T-TP-FP
DAT_TP_SIO 39
TP_CLK 1 2 CLK_TP_SIO LVDS cable
CLK_TP_SIO 39
10P_0402_50V8J~D
10P_0402_50V8J~D
L26 Part Number Description
R575 BLM18AG601SN1D_0603~D
10P_0402_50V8J~D
10P_0402_50V8J~D
100K_0402_5%~D 1 1 1 1 DC020003Y0L H-CONN SET ZJX MB-LCD
C86
C87
14 WXGA+(-1ch)
C400
C399
JKYBRD
2
37 KYBD_DET# KYBD_DET# 1 LVDS cable
KSO10 1 2 2 2 2
2 2 Part Number Description
KSO11 3
KSO9 3 H-CONN SET ZJX
4 4 DC02000870L
KSO14 5 MB-LCD 14 WXGA+(-2ch)
KSO13 5
6 6
KSO15 7 RTC BATT
KSO16 7
8 8 Part Number Description
KSO12 9
KSO0 9
10 10 GC20323MX00 BATT CR2032 3V
KSO2 11 220MAH MAXELL
KSO1 11
12 12
KSO3 13
KSO8 13
14 14
KSO6 15
KSO7 15
16 16 35 35
KSO4 17 36
B KSO5 17 36 SP_GND B
18 18 37 37
KSI0 19 38 SP_X
KSI3 19 38 SP_V+
20 20 39 39
KSI1 21 40 SP_Y
KSI5 21 40
22 22
KSI2 23
KSI4 24
23
24
Power Switch
KSI6 25
KSI7 25
26 26
POWER_SW# 27
18,39 POWER_SW# R_NUM_LED# 27
43 R_NUM_LED# 28 28
R_CAP_LED# 29 POWER_SW# 1 2
43 R_CAP_LED# 29 1 2
R_SCRL_LED# 30 41
43 R_SCRL_LED# 30 GND
KSO17 31 42 1
31 GND
+3.3V_ALW 32 32
33 @ C367
33 100P_0402_50V8J~D PWR_SW
34 34 2
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D @SHORT PADS~D
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FOX_GS12403-0001K-8F~D
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
C387
C382
C392
C381
C395
C383
C394
C384
C390
C386
C397
C393
C380
C371
C372
C389
C378
C376
C374
C373
C396
C391
C377
C375
C388
C78
@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, INT KB
LA-3301P
5 4 3 2 1
5 4 3 2 1
DC/DC Interface
+15V_ALW
+3.3V_ALW Q47 +3VSUS Source
SI4810BDY-T1-E3_SO8~D +3.3V_SUS
1
+3.3V_ALW2 8 1
R764 7 2
100K_0402_5%~D 6 3
20K_0402_5%~D
+15V_ALW 5 1
10U_0805_10V4Z~D
R620
2
C811
+3.3V_ALW2 +5V_ALW Q52 R765
+5VRUN Source
4
SI4810BDY-T1-E3_SO8~D 100K_0402_5%~D
+5V_RUN 2
2
1
D D
8 1
1
R624 D
7 2
1
100K_0402_5%~D 6 3 1 2 Q88
10U_0805_10V4Z~D
R623 5 R625 G 2N7002W-7-F_SOT323-3~D 1
C814
100K_0402_5%~D 20K_0402_5%~D S
3
1
D C195
4
2 Q87 4700P_0402_25V7K~D
39 3.3V_SUS_ON 2
2
G 2N7002W-7-F_SOT323-3~D 2 @
1
D
2200P_0402_50V7K~D
S
3
RUN_ON_5V# 2
G
Q53 S 1
C815
2N7002W-7-F_SOT323-3~D
1
D 2
19,37,39,42 RUN_ON 2
G
S Q55
3
2N7002W-7-F_SOT323-3~D
+1.8V_RUN Source
+1.8V_SUS +1.8V_RUN
Q54
SI4336DY-T1-E3_SO8~D
8 1 +3.3V_RUN Source
7 2
6 3 +3.3V_ALW
10U_0805_10V4Z~D
20K_0402_5%~D
5 @ Q10
1
1 SI4810DY-T1-E3_SO8~D
R628
C @ D35 C
8 1
C816
1 2 7 2
6 3
RB751V_SOD323~D 2
5
2
1 2
4
R305 1
0_0402_5%~D
C194
0.047U_0402_16V4Z~D +15V_ALW Q58 +3.3V_RUN
2 @ SI4336DY-T1-E3_SO8~D
8 1
7 2
20K_0402_5%~D
+3.3V_ALW2 6 3 1
10U_0805_10V4Z~D
R630
R641 5
C819
100K_0402_5%~D
+15V_ALW +5V_ALW Q80 +5VSUS Source
4
1
SI3456BDV-T1-E3_TSOP6~D +5V_SUS @ D36 2
2
R766 RB751V_SOD323~D
D
+3.3V_ALW2 6 100K_0402_5%~D 1 2
S
1
5 4
1
R617 D
2
2
1
20K_0402_5%~D
100K_0402_5%~D 1 1 2 1 2
1
R762
G R413
G
1
D
10U_0805_10V4Z~D
R621 S 0_0402_5%~D
2
3
100K_0402_5%~D 2 Q90 Q89 1
2 39 3.3V_RUN_ON
C143
SUS_ENABLE G 2N7002W-7-F_SOT323-3~D 2N7002W-7-F_SOT323-3~D

2
S C144
2
3
1
D
4700P_0402_25V7K~D
470P_0402_50V7K~D
SUS_ON_5V# Q49 2 @
2
G 2N7002W-7-F_SOT323-3~D 1
1
D
C142
S
3
B Q51 B
39,42 SUS_ON 2
G 2N7002W-7-F_SOT323-3~D
S 2 @
3
Discharg Circuit
+1.8V_SUS +5V_SUS +3.3V_SUS +5V_RUN +3.3V_RUN +1.5V_RUN +0.9V_DDR_VTT +1.8V_RUN +1.25V_RUN
1K_0402_5%~D
1K_0402_5%~D
1K_0402_5%~D
1
1
75_0603_5%~D
1K_0402_5%~D
1K_0402_5%~D
1K_0402_5%~D
1K_0402_5%~D
1K_0402_5%~D
R151
R118
R117
R633
R634
R635
R636
R729
@ R113
@ @
@ @ @ @ @ @
2
2
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
1
1
D D D D D D D D D
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
+PWR_SRC +PWR_SRC
Q91
Q92
Q93
Q30
SUS_ON_5V# 2 2 2 RUN_ON_5V# 2 2 2 2 2 2
Q61
Q62
Q63
Q64
Q81
G G G G G G G G G
1
S @ S @ S @ S S S S S S @
3
3
R698 @ @ @ @ @
1
100K_0402_5%~D
R699
100K_0402_5%~D
2
ENAB_3VLAN 28
2
D
2N7002W-7-F_SOT323-3~D
om
1
N21917830 2 R700
Q72
200K_0402_5%~D
A G C208 470K_0402_5%~D A
l.c
1
D 4700P_0402_25V7K~D
S
3
2
R701
39 AUX_ON 2
ai
2
tm
Q73 S
3
2N7002W-7-F_SOT323-3~D
2
ho
f@
POWER CONTROL
in
xa
LA-3301P
he
5 4 3 2 1
5 4 3 2 1
1 2
Non-iAMT 46 1.25V_RUN_PWRGD
R486 0_0402_5%~D +3.3V_ALW
18 2.5V_RUN_PWRGD 2 1
8
@ R216 0_0402_5%~D +3.3V_SUS U12C
+3.3V_ALW C135
P
47 1.5V_RUN_PWRGD 2 1 0.1U_0402_16V4Z~D 3 5
A Y
1
R207 0_0402_5%~D 1 2
G
R132
47 1.05V_RUN_PWRGD 2 1 20K_0402_5%~D +3.3V_ALW 74LVC3G14DC_VSSOP8~D
4
R208 0_0402_5%~D
8
+5V_ALW U12A U12B
P
D +5V_RUN 3VRUNRC +3.3V_ALW C458 D
1 A Y 7 6 A Y 2
R334 1 0.1U_0402_16V4Z~D
G
E
D25 10K_0402_5%~D Q77 1 2
2 1 1 2
B
2 MMBT3906WT1G_SC70-3~D C134 74LVC3G14DC_VSSOP8~D 74LVC3G14DC_VSSOP8~D
4
0.01U_0402_16V7K~D
1
RB751V_SOD323~D 200K_0402_5%~D
C 2
14
1 1
1
R68
R133 U27A
1
C46 C17 4.7K_0402_5%~D C 1 74VHC08MTCX_NL_TSSOP14~D
P
0.1U_0402_16V4Z~D 2200P_0402_50V7K~D Q84 IN1
1 2 2 OUT 3
2 2 B MMST3904-7-F_SOT323-3~D 19,37,39,41 RUN_ON 1 2 2
2
IN2
G
E R418 +3.3V_ALW
3
+1.8V_SUS 0_0402_5%~D
14
+1.8V_RUN R364 U27D
3
E
D26 10K_0402_5%~D Q78 13
P
B MMBT3906WT1G_SC70-3~D IN1 RUNPWROK
2 1 1 2 2 5V_3V_1.8V_1.25V_RUN_PWRGD 38 OUT 11 RUNPWROK 38,39,48
200K_0402_5%~D
12 IN2
1
G
C
1 RB751V_SOD323~D 1
1
R616
R134 74VHC08MTCX_NL_TSSOP14~D
7
1
C47 C19 4.7K_0402_5%~D C
0.1U_0402_16V4Z~D 2200P_0402_50V7K~D 1 2 2 Q85
2 2 B MMST3904-7-F_SOT323-3~D 39,41 SUS_ON
2
3
+3.3V_ALW
+3.3V_ALW
+3.3V_RUN R367
3
E
D27 10K_0402_5%~D Q79
14
2 1 1 2
B
2 MMBT3906WT1G_SC70-3~D U27C
10
P
IN1
1
200K_0402_5%~D
C
1 RB751V_SOD323~D 1 8 SUSPWROK 18
1
OUT
R82
R164 9 IN2
G
C49 C27 4.7K_0402_5%~D C
C 0.1U_0402_16V4Z~D 2200P_0402_50V7K~D 1 2 2 Q86 74VHC08MTCX_NL_TSSOP14~D C
7
2 2 B MMST3904-7-F_SOT323-3~D
2
E
3
+3.3V_SUS
1
R79
100K_0402_5%~D
2
ICH_PWRGD# ICH_PWRGD# 18
1
D
+3.3V_ALW 2 Q17
G 2N7002W-7-F_SOT323-3~D
S
3
14
U27B
IMVP_PWRGD 4
P
23,39,48 IMVP_PWRGD IN1
OUT 6 ICH_PWRGD 10,23
+3.3V_ALW +3.3V_ALW RESET_OUT# 5
39 RESET_OUT# IN2
G
+3.3V_SUS C186
D23 R159 0.1U_0402_16V4Z~D 74VHC08MTCX_NL_TSSOP14~D
7
3
E
RB751V_SOD323~D 10K_0402_5%~D B 1 2
2 1 1 2 2 Q20
MMBT3906WT1G_SC70-3~D
1
8
200K_0402_5%~D
2200P_0402_50V7K~D
C
1 1 U48A
1
R139
D32
P
C422
B C457 B
2 1 1 A Y 7 3.3V_5V_SUS_PWRGD
200K_0402_5%~D
0.1U_0402_16V4Z~D
1
2 2 RB751V_SOD323~D
2
+COINCELL
R135
74LVC3G14DC_VSSOP8~D
COIN RTC Battery
4
2
1
R21
1K_0402_5%~D
+5V_ALW +3.3V_RTC_LDO
2
+5V_SUS
D31 R160 JCOIN
Z4012
3
E
RB751V_SOD323~D 10K_0402_5%~D +COINCELL COINCELL 1
B
Q26 1
2 1 1 2 2 2 2
1
2200P_0402_50V7K~D
200K_0402_5%~D
C
1 1 D33 MOLEX_53398-0271~D
1
3
R158
RB751V_SOD323~D
+RTC_CELL
C404
C199 2 1
200K_0402_5%~D
0.1U_0402_16V4Z~D
1
2 2
2
R157
R136
200K_0402_5%~D D13
1
BAT54CW_SOT323~D
1
2
C370
1U_0603_10V4Z~D
2
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Good
LA-3301P
5 4 3 2 1
5 4 3 2 1
H1 H2 H3 H4 H5 H6 H7 H8 H9 Fiducial Mark
H_C146B217D91 H_C146B217D91 @H_C315D110 H_C256B63D47 @H_C236B315D110 @H_C236B256D110 @H_C236B315D110 @H_C217B276D98 @H_C236B315D110
EMI CLIP FD1 FD2 FD5 FD10 FD12

1
1
1 1 1 1 1
CLIP4 CLIP5 FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D
EMI_CLIP EMI_CLIP
H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 1 1 FD13 FD11 FD14 FD25 FD15 FD21
@H_C236B315D110 @H_C315B236D118 @H_C315D118 @H_C315D118 @H_C291B236D118 @H_C295D118 @H_C217B276D98@H_C217B276D98@H_C217D91 @H_C217D91 GND GND
1 1 1 1 1 1
CLIP6 CLIP3 FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D
EMI_CLIP EMI_CLIP
1
1
1 1 FD9 FD20 FD19 FD16
GND GND
D
1 1 1 1 D
CLIP1 CLIP2 FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D
EMI_CLIP EMI_CLIP
H20 H26 H27 H28 H29 H30
@H_C217B276D98 @H_C472D376 @H_C472D431X376 @H_O115X31D115X31N @H_O115X31D115X31N @H_O115X31D115X31N 1 1 FD17 FD18 FD3 FD4 FD6 FD8
GND GND
1 1 1 1 1 1
FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D
1
1
R226 FD7
330_0402_5%~D 1
2 1 R_CAP_LED# R_CAP_LED# 40
39 CAP_LED#
FIDUCIAL MARK~D
R224
330_0402_5%~D
2 1 R_NUM_LED# R_NUM_LED# 40
39 NUM_LED#
R225
330_0402_5%~D
2 1 R_SCRL_LED# R_SCRL_LED# 40
39 SCRL_LED#
This circuit is +3.3V_RUN

only needed if the +3.3V_RUN
platform has the +5V_RUN
1
+3.3V_RUN
SNIFFER.
1
R78
10K_0402_5%~D R181
R140 100K_0402_5%~D
3
@ 0_0402_5%~D @
2
1 2 Q28
2
3
PDTA114EU_SC70-3~D
Q22 2
C PDTA114EU_SC70-3~D C
S
SATA_ACT#_R 3 1 SATA_ACT# 1 2 2
22 SATA_ACT#_R
R179
Q23 0_0402_5%~D
+3.3V_ALW BSS138W-7-F_SOT323~D
G
2
1
R74 R212
1
R145 10K_0402_5%~D D 1K_0402_5%~D
1
1
330_0402_5%~D BT_ACTIVE 1 2 2 1 2 R_BT_ACT R_BT_ACT 32

34,40 BT_ACTIVE
R97 1 2 HDD_LED 32 G Q29
10K_0402_5%~D S BSS138W-7-F_SOT323~D
3
@
2
3
E
38 LED_MASK# B
38 LED_MASK# 2 Q18
R_PIDEACT 36
C
1
+3.3V_SUS
1
U43 R71
100_0402_5%~D
NC
39 BREATH_LED 2 A Y 4 1 2 BREATH_GREEN_LED 32
+3.3V_WLAN
G
+3.3V_RUN NC7SZ04P5X_NL_SC70-5~D
3
1
R638
47K_0402_5%~D
2
3
E
B
1 2 2 Q5 +3.3V_ALW
B 34 LED_WLAN_OUT# B
R639 MMBT3906WT1G_SC70-3~D
C
10K_0402_5%~D
1
3
Q1
R15 PDTA114EU_SC70-3~D
1 2 R_MPCI_ACT R_MPCI_ACT 32 BAT1_LED# 2
39 BAT1_LED#
150_0402_5%~D
+3.3V_SUS
1
R6
+RTC_CELL +3.3V_RUN 1 2 BATT_GREEN_LED BATT_GREEN_LED 32
100K_0402_5%~D
220_0402_5%~D
3
+3.3V_ALW
1
Q32
R180
PDTA114EU_SC70-3~D R102
SNIFFER_YELLOW# 2 100K_0402_5%~D
39 SNIFFER_YELLOW#
3
JSNIFF
6
Q4
2
PDTA114EU_SC70-3~D
6
38 WIRELESS_ON/OFF# 4 BAT2_LED# 2
4 39 BAT2_LED#
1
3 3
2 2
1
39 SNIFFER_PWR_SW# 1 1 R9
5
1 2 BATT_AMBER_LED BATT_AMBER_LED 32
1BS008-13130-7F_4P~D 220_0402_5%~D
5
+3.3V_SUS
om
A A
l.c
3
Q33
ai
PDTA114EU_SC70-3~D
SNIFFER_GREEN# 2
tm
39 SNIFFER_GREEN#
ho
D14 DELL CONFIDENTIAL/PROPRIETARY
1 2 SNIFFE R_Y 3 Y
f@
1
R261 220_0402_5%~D
1 2 SNIFFER_G 2
1
R262 220_0402_5%~D G PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
in
12-22AUYSYGC/530-A2/TR8_G/Y~D TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
PAD and Standoff
xa
he
LA-3301P
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
ESD Diodes
2
+3.3V_ALW
PL32
D D
FBMA-L18-453215-900LMA90T_1812~D
Secondary Battery Connector PD42 PD43 PD44 PD45 1 2
10K_0402_5%~D
@ DA204U_SOT323~D @ DA204U_SOT323~D @ DA204U_SOT323~D @ DA204U_SOT323~D
1
PJP60
PR300
1 2 SBATT+
0.1U_0603_25V7K~D
1
PC230
PJP1 PAD-OPEN 4x4m
1 PR301
2
BATT1+
2200P_0402_50V7K~D
2 100_0402_5%~D PR302
2
BATT2+ Z4301 100_0402_5%~D PR303
SMB_CLK 3 1 2 SBAT_SMBCLK 39
4 Z4302 1 2 100_0402_5%~D
SMB_DAT SBAT_SMBDAT 39
1
PC231
5 Z4303 1 2 PR304
BATT_PRES# SBAT_PRES# 38,50
6 100_0402_5%~D
SYSPRES#
7 1 2 SBAT_ALARM#
2
BATT_VOLT
10 GND BATT1- 8
11 GND BATT2- 9
TYCO_1734077-1~D
+3.3V_ALW
ESD Diodes
2
PL6 +3.3V_ALW
FBMA-L18-453215-900LMA90T_1812~D
1 2
Primary Battery Connector PD9 1 PD10 PD11 PD12
1
@ DA204U_SOT323~D @ DA204U_SOT323~D @ DA204U_SOT323~D @ DA204U_SOT323~D
1
10K_0402_1%~D
C PJP61 C
1 2 PBATT+
PR19
0.1U_0603_25V7K~D
1
PBATT1 PAD-OPEN 4x4m
PC9
1 PR20
2
BATT1+ 100_0402_5%~D PR21
2
2
BATT2+
2200P_0402_50V7K~D
3 Z4304 1 2 100_0402_5%~D PR22

SMB_CLK PBAT_SMBCLK 39
4 Z4305 1 2 100_0402_5%~D
SMB_DAT PBAT_SMBDAT 39
5 Z4306 1 2 PR23
BATT_PRES# PBAT_PRES# 38
1
PC10
6 100_0402_5%~D
SYSPRES#
BATT_VOLT 7 1 2 PBAT_ALARM#
10 8
2
GND BATT1-
11 GND BATT2- 9
SUYIN_200277MR009G506ZR~D
+5V_ALW
+3.3V_ALW
DA204U_SOT323~D
2
B B
PD2
2
2.2K_0402_5%~D
PR2
@ PR346
1 2
0_0402_5%~D
1
PR184
GPIO Input from EC 33_0402_5%~D
S
1 3 1 2 PS_ID 39
PL1 36 DOCK_PSID
BLM18BD102SN1D_0603~D PQ1 +5V_ALW
100K_0402_1%~D
2 1 +5V_ALW
G
2
2
DA204U_SOT323~D
FDV301N_SOT23~D
PR6
PQ3
DC_IN+ Source
10K_0402_1%~D
+DC_IN FDS6679AZ_SO8~D +DC_IN_SS
2
PD41
PR7
Z-series AC Adaptor 1 8 @
1
1
2 7 PD53
1
Connctor PL2 3 6 SM24_SOT23 C @
FBMJ4516HS720NT 1806~D 5 2 PQ2
2
1 2 +D C_IN B MMST3904-7-F_SOT323~D
1
240K_0402_5%~D
PJPDC1 E
3
1
0.47U_0805_25V7K~D
15K_0402_1%~D
VZ0603M260APT_0603
TYCO_1566065-2~D PR299
2
2
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
4.7K_0805_5%~D
10U_1206_25V6M~D
1 1 2
4
Low_PWR
1
PSID_DISABLE# 38
PR11
PR10
PC2
9 GND_4 PQ100B
1
PD58
2 + DCIN_JACK 1 @ 10K_0402_5%~D
1
DC+_1 IMD2AT-108_SC74-6~D
PR12
PC3
PC4
PC5
PC6
8
2
GND_3 @
3
2
1
DC+_2
0.1U_0603_25V7K~D
@ 3 4
2
1
7 4 -D CIN_JACK
GND_2 DC-_1
1
2
0_0402_5%~D
47K_0402_1%~D
PC397
6 5
2
GND_1 DC-_2
1
MH1
MH2
PR13
2
PR495
A A
2
@
1 2 @
PL34
1
PD59
VZ0603M260APT_0603
1 FBMJ4516HS720NT 1806~D
@ PQ100A
IMD2AT-108_SC74-6~D
@ DELL CONFIDENTIAL/PROPRIETARY
5
39 AC_OFF
2 THESE CAPS MUST BE Compal Electronics, Inc.
NEXT TO JCHG Title
+DCIN
6
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-3301P
5 4 3 2 1
5 4 3 2 1
+3.3V_ALWP/ +5V_ALWP/ +5V_ALW2 / +15V_ALWP
+DC1_PWR_SRC
D D
PJP33
+PWR_SRC 1 2
PAD-OPEN 4x4m
2
0_0805_5%
0_0805_5%
PJP63 +5V_VCC1
2200P_0402_50V7K~D
0.1U_0805_50V7K
+5V_ALW2 1 2
2200P_0402_50V7K~D
10U_1206_25V6M~D
10U_1206_25V6M~D
PR374
PR375
0.1U_0805_50V7K
@ PR376
1
10U_1206_25V6M~D
10U_1206_25V6M~D
PAD-OPEN1x1m 10_0603_5%~D
1
1
4.7U_0805_6.3V6K
PC274
PC275
PC276
PC277
2 1
PC278
PC279
PC280
PC281
2
2
1
PC282
+3.3V_ALW2
2
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
1
PC284
1U_0603_10V6K~D
PR379
1
PC285
@ 0_0402_5%~D
1
PC283
1 2
2
PR380
2
0_0402_5%~D
EN_3V_5V
1 2
PC286
0.1U_0603_25V7K~D
1
GNDA_3V5V 1 2 GNDA_3V5V 0_0402_5%~D
5 Volt +/-5% 1@ PR500 2 PR499 3.3 Volt +/-5%
0.1U_0402_10V7K~D
Thermal Design Current:6.2A Thermal Design Current: 8.6A
0.1U_0402_10V7K~D
0_0402_5%~D
2
8
7
6
5
PC385
Peck current: 8.8A @ PR501 Peak current: 12.3A
8
7
6
5
4
3
2
1
5
PQ82 GNDA_3V5V 2 1
D
D
D
D
1
+5V_ALWP
PC386
OCP min: 9.05A FDS8880_NL_SO8~D PQ83 OCP min:13.08A
REF
LDO
VREF3
EN_LDO
LDOREFIN
VIN
VCC
TON
D
C 0_0402_5%~D @ BSC079N03S G_PG-TDSON-8~D C
2
2
4 @ PR382
G 267K_0402_1%~D
9 BYP REFIN2 32 4 G
+5V_ALWP PR383 10 31 1 2 GNDA_3V5V
OUT1 ILIM2
S
S
S
PL36 150K_0402_1%~D 11 30 PL37

FB1 OUT2
S
S
S
4.7U_HMU1356-4R7-R_10A~D GNDA_3V5V 1 2 12 PU20 29 2 PR517 0_0402_5%~D
1 +3.3V_ALWP
1
2
3
POK1 ILIM1 ISL6236IRZA_QFN32~D SKIP# POK2

13 28
3
2
1
EN_3V_5V POK1 POK2 EN_3V_5V
14 EN1 EN2 27
+5V_ALW_UGATE 15 26 +3.3V_ALW_UGATE
+5V_ALW_PHASE UGATE1 UGATE2 +3.3V_ALW_PHASE
1 2 16 PHASE1 PHASE2 25 2 1
0_0402_5%~D
0.1U_0603_25V7K~D
LGATE1
LGATE2
3.0U_HMP1362-3R0-R_17A~D
BOOT1
BOOT2
SECFB
2
8
7
6
5
PGND
PVCC
0.1U_0603_25V7K~D
0_0402_5%~D
GNDA_3V5V
GND
PAD
5
6
7
8
1
330U_D3L_6.3VM_R25~D
330U_D3L_6.3VM_R25~D
PR384
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
PR385
1
1
PC287
PC288
1 PQ84 1
33
17
18
19
20
21
22
23
24
@ PQ85
1
1
1
PC289
PC291
PC292
PC290
+ FDS6676AS_NL_SO8~D 4 GNDA_3V5V +
2
4 FDS6676AS_NL_SO8~D
PR386 PR387
2
2
2 1_0603_5%~D 1_0603_5%~D 2
0_0402_5%~D
0_0402_5%~D
1 2 +5V_ALW_BOOT +3.3V_ALW_BOOT1 2
1
2
3
2
1
3
2
1
PR389
+5V_ALW_LGATE +3.3V_ALW_LGATE
PR388
@
1
2
GNDA_3V5V
GNDA_3V5V
1U_0603_10V6K~D
GNDA_3V5V PC293 PJP34
1
+5V_ALWP 2 0.1U_0603_25V7K~D 1 2
+3.3V_ALWP +3.3V_ALWP
PC403
1 1 2
0.1U_0603_25V7K~D
+5V_ALW2
3
2
PAD-OPEN1x1m
1
B B
100K_0402_1%~D
100K_0402_1%~D
PD55 GNDA_3V5V
PC294
BAT54SW-7-F_SOT323-3~D
2
2
PR391
PR390
PC295
2 0.1U_0603_25V7K~D PD57
1
1 1 2 BAT54CW_SOT323~D
3 @
1
PR392 PD56 POK2
2K_0402_5%~D
2 1 BAT54SW-7-F_SOT323-3~D
39 ALWON
3
0_0402_5%~D
1
200K_0402_5%
2
PR393
PR395
PR394
0_0402_5%~D
18 THERM_STP# 2 1
2
1
POK1
ALW_PWRGD_3V_5V 39
PR397
PJP35 200K_0402_1%~D
+15V_ALW 2 1 +15V_ALWP 2 1
0.1U_0603_25V7K~D
39.2K_0402_1%~D
PAD-OPEN1x1m
2
(100mA,20mils ,Via NO.=1)

1
PC296
PR398
2
PJP36
om
+5V_ALWP 1 2 +5V_ALW
A PAD-OPEN 4x4m A
l.c
GNDA_3V5V
ai
PJP37
tm
+3.3V_ALWP 1 2 +3.3V_ALW
ho
PAD-OPEN 4x4m
f@
Title
in
DC/DC +3V/ +5V
xa
LA-3301P
he
5 4 3 2 1
5 4 3 2 1
1.8V/1.25V/0.9V VTT
PJP44
+PWR_SRC 1 2 +1P8V_1P23V_PWRSRC
PAD-OPEN 4x4m
2
0_0805_5%
0_0805_5%
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
2200P_0402_50V7K~D
D D
PR418
PR419
1
1
1
1
PC318
PC319
PC320
PC321
PC322
PC323
PC324
1
PC325
@
2
2
2
+5V_VCC3
0.1U_0603_25V7K~D
2
PC326
0_0402_5%~D
Place these CAPs
close to FETs Place these CAPs
1
2
close to FETs
PR420
10K_0402_1%~D
@
1
1 2 VGA_ISL6236_REF
1.8 Volt +/-5% 1.25 Volt +/-5%
8
7
6
5
PR422
PR421
2
0.1U_0603_25V7K~D
PQ90 0_0402_5%~D
Thermal Design Current: 5.7A Thermal Design Current: 1A
D
D
D
D
FDS8880_NL_SO8~D
1
Peak current: 8.1A Peak current: 1.4A
0.1U_0402_10V7K~D
16.9K_0402_1%~D
PC329
OCP min:8.6A 4 OCP min:1.72A
1
G
1 2
@ PR423 PQ91
6
S
S
S
+1.8V_SUSP
PC405
0_0402_5%~D FDS6982AS_NL_SO8~D
PR424
D1
D1
1
2
3
8
7
6
5
4
3
2
1
GNDA_DC2 +1.25V_RUNP
2
PL42 @ 4
LDOREFIN
VIN
VCC
TON
LDO
VREF3
EN_LDO
REF
1.4UH_HMU1350-1R4PF_15A_20%~D GNDA_DC2 G1 PL43
3
1
C S1 3.3UH_MPL73-3R3_6A_20%~D C
1 2
PR425 7 2 1
51.1K_0402_1%~D GNDA_DC2 D2
9 BYP REFIN2 32
PR426 10 31 1 2 8
3
OUT1 ILIM2 D2
8
7
6
5
330U_D2E_2.5VM_R15~D
330U_D2E_2.5VM_R15~D
0.1U_0402_10V7K~D
130K_0402_1%~D 11 30 2 G2
S2
FB1 OUT2
220U_D2E_2.5VM_R15~D
0.1U_0402_10V7K~D
1 1 GNDA_DC2 1 2 12 ILIM1 SKIP# 29 1 PR518 2
2 1
13 PU22 28 @
0_0402_5%~D 1
1
POK1 ISL6236IRZA_QFN32~DPOK2
1
39 DDR_ON
PC331
PC332
PC333
+ + PQ92 1 2 14 27 PC406 GNDA_DC2

EN1 EN2
1
PC334
PC335
PR427 1.8V_UGATE 15 26 1.25V_UGATE 0.1U_0402_10V7K~D +
FDS6676AS_NL_SO8~D 0_0402_5%~D 1.8V_PHASE 16 UGATE1 UGATE2 1.25V_PHASE
4 25
2
2 2 PHASE1 PHASE2
27.4K_0603_1%~D
0.1U_0603_25V7K~D
2
2
0.1U_0603_25V7K~D
1000P_0402_50V7K~D
LGATE1
LGATE2
BOOT1
BOOT2
SECFB
PGND
PVCC
GND
PAD
1
2
PC336
1
2
3
1
2
PR428
PC401
PC337
33
17
18
19
20
21
22
23
24
1
2
1
@ PR429
2
PR430 1_0603_5%~D
0_0603_5%~D 1 2
1 2 GNDA_DC2
1.25V_LGATE @ PR431
1.8V_LGATE 100K_0402_1%~D
+3.3V_SUS 2 1
+3.3V_ALW
+5V_ALW +5V_VCC3 1.25V_RUN_PWRGD 42
17.4K_0402_1%~D
@ PR432 GNDA_DC2 PR484

10_0603_5%~D 100K_0402_1%~D
1
20K_0402_5%~D
2 1 +3.3V_ALW 2 1
2
PR433
PJP45
PR434
1.25V_RUN_ON 39
1U_0603_10V6K~D
1U_0603_10V6K~D
B B
2 1
1
1
2
PC338
PC339
1
PAD-OPEN1x1m
2
2
39 1.8V_SUS_PWRGD PJP66
+1.25V_RUNP 1 2 +1.25V_RUN
GNDA_DC2
PAD-OPEN 4x4m
GNDA_DC2 GNDA_DC2
+0.9V_P 0.9 Volt +/-5%
+5V_ALW
Thermal Design Current: 0.7A
V_DDR_MCH_REF
Peak current: 1A
PU24
10 VIN VTT 3
PJP47
+1.8V_SUS 2 1 2 5
VLDOIN VTTSNS
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
PAD-OPEN 2x2m~D 1 6
VDDQSNS VTTREF
1U_0603_10V6K~D
7 S3 PGND 4
2
39 0.9V_DDR_VTT_ON
PC342
PC343
GND 8
2
10U_0805_6.3V6M~D
0.1U_0603_25V7K~D
PC345
9 S5 BP 11
39 DDR_ON
1
TPS51100DGQRG4_MSOP10~D
1
2
1
PC348
PC410
1
GND
PJP48
1 2
A A
PGND and GND sholud be tied
PAD-OPEN 4x4m
together at one point near the GND Pin
PJP49
1 2 +1.8V_SUS
+1.8V_SUSP
PAD-OPEN 4x4m
PJP50 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
+0.9V_P 2 1 +0.9V_DDR_VTT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, P47-PWR_1.25V/1.8V/LDO Vtt 0.9V
PAD-OPEN 2x2m~D PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.0
LA-3301P
5 4 3 2 1
5 4 3 2 1
+1.5V_RUN / +1.05V_VCCP / +3.3V_ALW / +3.3V_RTC_LDO

+DC2_PWR_SRC
PJP38
+PWR_SRC 1 2
D D
2
10U_1206_25V6M~D
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
0_0805_5%~D
0.1U_0603_25V7K~D0_0805_5%~D
PAD-OPEN 4x4m
10U_1206_25V6M~D
0.1U_0603_25V7K~D
PR399
PR400
2200P_0402_50V7K~D
1
10U_1206_25V6M~D
PC297
PC299
PC300
1
PC301
PC302
2
PC303
PC304
2
2
2
PC305
+5V_VCC2
1
+3.3V_RTC_LDO
2
PR401
0_0402_5%~D
PC306
0_0402_5%~D
0.1U_0603_25V7K~D
1.5 Volt +/-5% 1.05 Volt +/-5%
2
0.01U_0402_25V7K~D
REF 1 2
PR496
Thermal Design Current: 2A PR405 2 1
Thermal Design Current: 10.8A
5
6
7
8
0_0402_5%~D
Peak current: 2.8A GNDA_1P5V_1P05V @ 0_0402_5%~D Peack current: 15.3A
PC308
1 2 @ PR503
D
D
D
D
1
0.1U_0402_10V7K~D
PR497
PQ86
OCP min: 2.83A 0_0402_5%~D OCP min: 16.4A
0.1U_0402_10V7K~D
SI4800BDY-T1_SO8~D
2 1
8
7
6
5
PR504 GNDA_1P5V_1P05V
G
S
S
S
@ 0_0402_5%~D
1
+1.05V_VCCP_P
PC404
4
3
2
1
8
7
6
5
4
3
2
1
PQ87
PC387
C C
1
PL39
LDOREFIN
VIN
VCC
TON
LDO
VREF3
EN_LDO
REF
1
4 GNDA_1P5V_1P05V 0.88UH_MPC1040LR88_17A_20%~D
+1.5V_RUN_P 1 2
2
GNDA_1P5V_1P05V @
2
PL40 9 32 REFIN2_1_05 @
3.3UH_MPL73-3R3_6A_20%~D BYP REFIN2
10 31 1 2
1
2
3
OUT1 ILIM2
0.1U_0402_10V7K~D
2 1 PR408 11 30 PR407 249K_0402_1%~D GNDA_1P5V_1P05V
FB1 OUT2
5
6
7
8
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
1 2 12 29 PR5192 0_0402_5%~D
1 GNDA_1P5V_1P05V
ILIM1 SKIP#
8
7
6
5
10U_1206_6.3V7K
SI4810BDY-T1-E3_SO8~D
100K_0402_1%~D POK1 13 PU21 28 POK2 1 1

POK1 ISL6236IRZA_QFN32~DPOK2
0.1U_0402_10V7K~D
EN1 14 27 EN2
D
D
D
D
GNDA_1P5V_1P05V EN1 EN2
2
2
10U_1206_6.3V7K
330U_D2E_2.5VM_R9
PC310
PC309
PC311
PC388
0_0402_5%~D
1.5V_UGATE 15 26 1.05V_UGATE + +
UGATE1 UGATE2
PQ88
1 1.5V_PHASE 16 25 1.05V_PHASE
PHASE1 PHASE2
PR409
1
1
2 2
0.1U_0603_25V7K~D
PC312
PC313
PC389
PQ89
LGATE1
LGATE2
4
BOOT1
BOOT2
SECFB
G
PGND
0.1U_0603_25V7K~D
PVCC
GND
PAD
1
2
2
S
S
S
3
2
1
2
2
PC314
PC315
1
2
3
33
17
18
19
20
21
22
23
24
0_0402_5%~D
2
1
PR410
GNDA_1P5V_1P05V
PR411 PR412
1
@ 1_0603_5%~D 1_0603_5%~D
1 2 1 2
1.5V_LGATE GNDA_1P5V_1P05V
+3.3V_SUS
GNDA_1P5V_1P05V 1.05V_LGATE
EN1
B 1.5V_RUN_ON 39 B
+5V_ALW @ PR413 +5V_VCC2 PR478
100K_0402_1%~D
100K_0402_1%~D
10_0603_5%~D 0_0402_5%~D
2 1 EN2 1 2
2
1.05V_RUN_ON 38
1U_0603_10V6K~D
PR416
PR415
1
1U_0603_10V6K~D
1
PC316
PC317
@ @
1
2
POK2 1.05V_RUN_PWRGD 42
GNDA_1P5V_1P05V
POK1 1.5V_RUN_PWRGD 42
PJP39
1 2
PJP40
1 2 PAD-OPEN 4x4m
PJP41
PAD-OPEN 4x4m PJP42
2 1 +1.05V_VCCP_P 1 2 +1.05V_VCCP
PJP43
+1.5V_RUN_P 1 2 +1.5V_RUN PAD-OPEN 4x4m
PAD-OPEN1x1m
PAD-OPEN 4x4m
om
GNDA_1P5V_1P05V
A A
l.c
OK to Short if CAD
ai
System can Support
tm
ho
f@
+1.5V_RUN / +1.05V_VCCP
in
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
xa
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.0
LA-3301P
he
5 4 3 2 1
8 7 6 5 4 3 2 1
+CPU_PWR_SRC PL44@
FBMA-L18-453215-900LMA90T_1812~D
1 2 +PWR_SRC
PJP30
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
10U_1206_25V6M~D
10U_1206_25V6M~D
100U_25V_M~D
H H
1 1 2
PC380
1
1
PC249
PC223
PC176
PC270
+ PAD-OPEN 4x4m
PC224
PJP31
2
2
IRF7821TRPBF_SO8~D
1 2
8
7
6
5
+CPU_PWR_SRC PAD-OPEN 4x4m
D
D
D
D
PQ42
+5V_ALW
Iccmax=44A
I_TDC=35A
G
S
S
S
1U_0603_10V6K~D
PR228 OCP=65A, Intel spec=50A
1
2
3
4
1
PC178
10_0603_5%~D
0.01U_0402_25V7K~D
PR229 PC179
2
PU10 0_0603_5%~D 0.22U_0603_10V7K~D
G 5 1 2 1 1 2 G
VCC BOOT PL29
6 8 UGATE1 0.45UH_ETQP4LR45XFC_25A_20%~D
FCCM UGATE
1
PC180
2 7 PHASE1 4 1 +VCC_CORE
PWM PHASE
3 4 3 2
2
GND LGATE
FDS7088SN3_SO8~D
ISL6208CRZ-T_QFN8~D
2
+5V_ALW
PQ56
PR232
+3.3V_RUN
1U_0603_10V6K~D 10_0603_5%~D
GNDA_VCORE 10_0402_1%~D
2
LGATE1 2 PR230 PC181

G 10K_0402_1%~D 0.22U_0603_10V7K~D
1
1500P_0603_25V7K~D
PR233
1 2 2 1
2
1
1
PC246
PR231
2
7.68K_0805_1%~D PR513
1
F PR234 F
0_0402_5%~D
2
PC182
1.91K_0603_1%~D @
1
PR238 VSUM
2
2
147K_0402_1%~D
1
2 1 IMVP_PWRGD 23,39,42
0_0603_5%~D
VO
1
+CPU_PWR_SRC
PR290
@ PR284
1
13K_0402_5%~D
0_0402_5%~D GNDA_VCORE +5V_ALW

PR485
2 1
19
20
18
39
40
2
IRF7821TRPBF_SO8~D
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
10U_1206_25V6M~D
10U_1206_25V6M~D
@
VSS
3V3
VDD
VIN
PGOOD
2
8
7
6
5
@ PC409
1
1U_0603_10V6K~D
PC239
2200P_0402_50V7K~D
D
D
D
D
PQ57
PC240
PC177
PC271
2 1 38 IMVP6_PROCHOT# 4 VR_TT#
PC241
2
3 RBIAS PWM1 27
G
S
S
S
@ PH1
2
E E
PC187 2 1 5
1
2
3
4
0.015U_0402_16V7K~D NTC PR328 PC242
2 1 470KB_0402_5%_NCP15WM474J03RB~D 6 23 PU16 0_0603_5%~D 0.22U_0603_10V7K~D
SOFT ISEN1
5 VCC BOOT 1 2 1 1 2
GNDA_VCORE PU11 PL33
2 PR239 1 28 6 8 UGATE2 0.45UH_ETQP4LR45XFC_25A_20%~D
8 VID0 VID0 FCCM UGATE
8 VID1 2 PR240 1 0_0402_5%~D 29 VID1
0_0402_5%~D 2 PR241 1 30 26 2 7 PHASE2 4 1 +VCC_CORE
8 VID2 VID2 PWM2 PWM PHASE
8 VID3 2 PR242 1 0_0402_5%~D 31 VID3
0_0402_5%~D 2 PR243 1 32 3 4 3 2
8 VID4 VID4 GND LGATE
FDS7088SN3_SO8~D
8 VID5 2 PR244 1 0_0402_5%~D 33 VID5
0_0402_5%~D 2 PR245 1 34 22 ISL6208CRZ-T_QFN8~D
D
8 VID6 VID6 ISEN2
0_0402_5%~D
PQ60
2
8,10,22 H_DPRSTP# 37 DPRSTP#
PR248 PR329
2 1 36 LGATE2 2 10_0402_1%~D
10,23 DPRSLPVR DPRSLPVR G PC243
PR249 499_0402_1%~D PR330
1500P_0603_25V7K~D
2 1 1 ISL6260CCRZ_QFN40~D 10K_0402_1%~D 0.22U_0603_10V7K~D
8 H_PSI#
1
PSI#
S
D PR252 0_0402_5%~D 1 2 2 1 D
2 1 2 24
1
PMON FCCM
2
18 PWR_MON
PC247
10K_0402_5%~D CLK_ENABLE#
2
1
@ PR479 38 PR331
PC391 0_0402_5%~D CLK_EN# 7.68K_0805_1%~D PR514
2
1U_0603_10V6K~D 2 1 35 0_0402_5%~D
1
PR509 0_0402_5%~D VR_ON
1
GNDA_VCORE @ PR254 0_0402_5%~D 2 1 12 25 @ VSUM
2
VSEN PWM3
38,39,42 RUNPWROK 2 8 1 VCCSENSE
13 RTN VO
21 @ PR508 +CPU_PWR_SRC
ISEN3 226K_0402_1%~D
39 IMVP_VR_ON 11 VDIFF
2 1 GNDA_VCORE +5V_ALW
0.1U_0603_25V7K~D
2 1 10 PR260
FB
IRF7821TRPBF_SO8~D
10U_1206_25V6M~D
2200P_0402_50V7K~D
11.5K_0402_1%~D
10U_1206_25V6M~D
@ PH3 PC213 1000P_0402_50V7K~D 7 2 1
OCSET
8
7
6
5
1
PC227
10KB_0603_1%_ERTJ1VG103FA~D 2 1 9 COMP
1
1U_0603_10V6K~D
PC272
PC193
C C
D
D
D
D
PQ50
PC228
PR486 PC214 1000P_0402_50V7K~D 17 VSUM
2
VSUM
1
PC196
2 1 2 1 8
2
VW
0.033U_0402_16V7K~D
2.43K_0402_1%~D
@ 4.99K_0402_1%
1
G
S
S
S
DROOP
41 PR262 PC198
2
GND
4.53K_0402_1%~D
PR261
GNDA_VCORE PR512 PU13 0_0603_5%~D 0.22U_0603_10V7K~D

DFB
1
2
3
4
1
VO
8 VSSSENSE 2 1 5 VCC BOOT 1 2 1 1 2

2
PC215
0_0402_5%~D PL31
PR263
6 8 UGATE3 0.45UH_ETQP4LR45XFC_25A_20%~D
14
15
16
PR257 PR287 FCCM UGATE

1
0.33U_0603_10V7K
0_0402_5%~D
2 1 1 2 2 1 2 2 7 PHASE3 1 4 +VCC_CORE
2
PWM PHASE
1
PR480
332_0402_1%~D
6.8KB_0603_5%_ERTJ1VR682J~D
PC191
PC190 PR258 0_0603_5%~D 3 4 2 3

GND LGATE
FDS7088SN3_SO8~D
680P_0402_50V7K~D 2 1 VO
1
0.01U_0402_16V7K~D
1.69K_0402_1%~D @ ISL6208CRZ-T_QFN8~D
PQ61
2
2
2 1 1
PR487 GNDA_VCORE PR271
1500P_0603_25V7K~D
PC229
0_0402_5%~D LGATE3 2 10_0402_1%~D

G
1
B B
15K_0402_1%~D
PR267 PR268 PR269 PC200

10.5K_0402_1% 1K_0402_1%~D 2 10K_0402_1%~D 0.22U_0603_10V7K~D
1 2 2 1
1
1
S
PH2
PR266
PC248
PC250 PR259 2 1 2 1 1 2 2 1
1500P_0402_50V7K~D 82.5K_0402_1%~D
2
PWR_MON 18
2
1
PC195 PR270
220P_0402_50V8J~D PC197 PC201 @ 7.68K_0805_1%~D PR515
1 2 2 1 2 1 0_0402_5%~D
1K_0402_1%~D
1
0_0402_5%~D
0.1U_0402_16V7K~D
30K_0402_5%~D
1000P_0402_50V7K~D 330P_0402_50V7K~D VSUM
2
1
4700P_0402_25V7K~D
1
1
1
0.1U_0402_16V7K~D
PR516
4700P_0402_25V7K~D
2 1
PR481
PC392
PR482
VO
1
1
PC411
PC412
PR264 2 2
PC260
6.34K_0402_1%~D
2
@ @ @
2
2
0.01U_0402_16V7K~D
@ @
1 @ DELL CONFIDENTIAL/PROPRIETARY
A 1 A
GNDA_VCORE
PC413
GNDA_VCORE Title
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +VCORE
GNDA_VCORE MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-3301P
8 7 6 5 4 3 2 1
5 4 3 2 1
+DC_IN discharge path
+SDC_IN
PR138 CHAGER_SRC
0.01_2512_1%~D PJP62
+DC_IN_SS 1 4 1 2
0.1U_0603_25V7K~D
2 3 PAD-OPEN 4x4m
2200P_0402_50V7K~D
D D
1
1
PC127
PC128
10_0402_1%~D
PC99
1
10U_1206_25V6M~D
2
2
@ @
PR472
2
PR142
2
215K_0402_1%
PC383
1 2
1
0.22U_0402_6.3V6K
ISL88731_VDDP
10K_0402_1%~D
PC202
1U_0603_10V6K~D
1
GNDA_CHG
28
27
1 2 GNDA_CHG
1
PR149
PC102 PU8
1U_0805_25V4Z~D
CSSP
NC
CSSN
2
PR143 2 1 22 26
49.9K_0402_1%~D DCIN VCC PR275 PR274
2
RB751V_SOD323~D
2 1 2 0_0603_5%~D 33_0603_1%~D
PR146 ACIN
BOOT 25 1 2
15.8K_0402_1%~D
PC110 1 2 13
1
18,39,50 ACAV_IN ACOK
1
0.1U_0603_25V7K~D
PC203
0_0402_5%~D
1
PD40
C C
2 1 11 VDDSMB
PR341
SI4800BDY-T1_SO8~D
SI4800BDY-T1_SO8~D
5
6
7
8
5
6
7
8
0.01U_0402_25V7K~D 10 PC204
2
SCL
10U_1206_25V6M~D
10U_1206_25V6M~D
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
@ 1U_0603_10V6K~D
2
GNDA_CHG 9 21 ISL88731_VDDP 1 2
2
+5V_ALW SDA VDDP +5V_ALW
PQ75
PQ79
1
PC103
PC104
PC105
PC106
GNDA_CHG 14 NC
Vin Detector 24 CHG_UGATE 4 4
UGATE
1SS355_SOD323~D
ISL88731_ICM 8
2
ICM
1
High 17.9 V 23 2 PR360 1

PHASE
2
PC221 6 0_0603_1%~D
Low 17.24 V VCOMP
3300PF_0402_50V7K~D
PD54
0.1U_0402_10V7K~D
2
3
2
1
3
2
1
2.2K_0402_5%~D
5 @ PC253
NC
1
220P_0402_50V7K~D
2
0.01U_0402_25V7K~D
PR148
4 20 CHG_LGATE PL20 @
1
ICOMP LGATE
1
+VCHGR
0.01U_0402_25V7K~D
18,39 THRM_SMBCLK GNDA_CHG PR145

1
1
PC212
PC119
PC267
0.01_2512_1%~D
@ PR373
2
2
18,39 THRM_SMBDAT ISL88731_VREF 3 19 +VCHGR_B 2 1+VCHGR_L1 4 2 1
2
@ VREF PGND @
CSOP 18
5
6
7
8
0.1U_0402_10V7K~D
5.6U_HMU1356-5R6_8.8A_20%~D 2 3 1K_0603_1%~D
0.01U_0402_25V7K~D
1U_0603_10V6K~D
0.1U_0603_25V7K~D
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
7 17
D
D
D
D
NC CSON
1
1
16.2K_0402_1%~D
0.1U_0402_10V7K~D
1
1
PC122
PC120
PC112
PC113
PC114
PC379
VFB 15 1 PR368 2 +VCHGR
1
1
PR150
PC121
PC118
10_0402_1%~D
12
2
2
GND
PQ76
16 0_0603_5%~D 4
2
NC G
1
@ @ 29
2
@ @ GND
2
S
S
S
PR473
ISL88731_TQFN28~D
3
2
1
PC384
2
B 0.22U_0402_6.3V6K B
1 2
GNDA_CHG
PJP65
ISL88731_VREF 1 2
Maximum charging current is 6.24A
+5V_ALW +3.3V_ALW
PAD-OPEN1x1m
100K_0402_5%~D
PR365
1M_0402_1%~D GNDA_CHG
1
57.6K_0402_1%~D
1 2
1
PR362
PR367
PR361
100K_0402_1%~D
ISL88731_ICM 1 2
1
8.45K_0402_5%~D
2
2
PR366
GNDA_CHG ADAPT_OC 38
4
PU19A
2
@ PR475 LM393DR_SO8~D D
2
G
IN-
1K_0402_5%~D
33.2K_0402_1%~D
38 ADAPT_TRIP_SET O 1 2
G
1 2 3 IN+ 1
P
13K_0402_1%
10P_0402_50V8J~D
S +5V_ALW
3
1
0.1U_0402_25V7K~D
PC259
@ PR474
PQ81
8
1
100P_0402_50V8K
100P_0402_50V8K
0.01U_0402_25V7K~D
PR363
RHU002N06_SOT323
1
8
100P_0402_50V8K
0.01U_0402_25V7K~D
om
PC254
@ 5
P
2
IN+
1
1
PC393
PC255
PC256
A A
7
2
l.c
1
1
PC257
PC258
6 IN-
G
PU19B
ai
2
2
105_0402_1%~D
LM393DR_SO8~D
2
4
1
tm
+5V_ALW GNDA_CHG GNDA_CHG GNDA_CHG DELL CONFIDENTIAL/PROPRIETARY
PR364
ho
GNDA_CHG GNDA_CHG GNDA_CHG GNDA_CHG GNDA_CHG GNDA_CHG
GNDA_CHG Compal Electronics, Inc.
f@
2
Title
Charger
in
xa
GNDA_CHG GNDA_CHG
LA-3301P
he
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2 1
5 4 3 2 1
+DC_IN discharge path
PQ62
+PWR_SRC
8 1
100U_25V_M~D
100U_25V_M~D
+SDC_IN 7 2
0.1U_0603_25V7K~D
10K_0402_5%~D
6 3 1 1
2200P_0402_50V7K~D
PC382
PC381
D D
5
1
PR305
PC232
PC233
+ +
4
PR306 PR307
2
10K_0402_5%~D 100K_0402_5%~D 2 2
1
2 1 2 1
1
D D
2 PQ63 2 PQ64
18,39,49 ACAV_IN
@ PR308 G RHU002N06_SOT323 G RHU002N06_SOT323
PQ65 100K_0402_5%~D S S PD47
3
8 D2 S2 1CHG_SBAT 2 1 B540C~D
7 D2 G2 2CHG_SBATT_N 2 1
+VCHGR 6 D1 S1 3
5 D1 G1 4
PQ66
FDS4935BZ_SO8~D SI4835BDY-T1-E3_SO8~D
8 1
PR309 PR310 SBATT+ 7 2 +PWR_SRC
10K_0402_5%~D 100K_0402_5%~D 6 3
CHG_SBAT_N 2 1 2 1 5
1
D PC234 PD48
4
2 PQ67 0.1U_0603_25V7K~D 2
38 CHG_SBATT
G RHU002N06_SOT323 1 2 1 SBAT_G
S 3
3
CHG_SBATT_N RB715F_SOT323
33K_0402_5%~D
2
PR311
C C
1
CHG_PBATT_N
PC235
0.1U_0603_25V7K~D PBATT+
3
S
1 2 PD49
RHU002N06_SOT323
G
2 B540C~D
38 CHG_PBATT PQ68 PR312 PR313 2 1
D 10K_0402_5%~D 100K_0402_5%~D
1
CHG_PBAT_N 2 1 2 1
PQ69 PQ70
PQ71 PQ72 SI4835BDY-T1-E3_SO8~D SI4835BDY-T1-E3_SO8~D
4
SI4835BDY-T1-E3_SO8~D SI4835BDY-T1-E3_SO8~D 1 8 8 1
5 5 2 7 7 2
+VCHGR 6 3 CHG_PBAT 3 6 3 6 6 3
7 2 2 7 5 5
8 1 1 8
4
470K_0402_5%~D
470K_0402_5%~D
PR316
1
47K_0402_1%~D
PR314
PR315
1 2
PD50
2
1 PBAT_G
1
10K_0402_5%~D
B B
3
33K_0402_5%~D
PR317
2
RB715F_SOT323
PR318
2
PBATT+
1
PR319 PU14A
8
SBATT+ 47K_0402_1%~D LM393DR_SO8~D
1
D
1 2 3
P
IN+ PQ73
O 1 2
2 G RHU002N06_SOT323
IN-
1
470K_0402_5%~D
S
3
4
PR320
1 PR321
2
147K_0402_1%~D PR322
0.1U_0603_25V7K~D
100K_0402_5%~D
2
2
42.2K_0402_1%~D
PBATT+ 1 2
2
0.1U_0603_25V7K~D
PC236
PR323
1
@
1
2
PC237
+3.3V_ALW
+3.3V_ALW
1
PR324
8
10K_0402_5%~D PD51
1 2 5 2
P
PU15 IN+
O 7 1
5
TC7SH32FU_SSOP5~D 1 2 6 3
IN-
1
D LM393DR_SO8~D
32.4K_0402_1%~D
2
P
38 PBAT_DSCHG I0
2
A
4 2 PR325 PU14B RB715F_SOT323 A
4
O
PR326
1 G 100K_0402_5%~D
38,44 SBAT_PRES# I1
G
PQ74 S +3.3V_ALW
3
RHU002N06_SOT323
3
1

Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Selector
5 4 3 2 1
5 4 3 2 1
D D
DVI_TX2-
DVI_TX2- 36
2 1 C968 1 2 R715
0.1U_0402_16V4Z~D 110_0402_1%~D
DVI_TX2+
DVI_TX2+ 36
DVI_TX1-
DVI_TX1- 36
2 1 C969 1 2 R716
0.1U_0402_16V4Z~D 110_0402_1%~D
DVI_TX1+
DVI_TX1+ 36
DVI_TX0-
DVI_TX0- 36
2 1 C970 1 2 R717
0.1U_0402_16V4Z~D 110_0402_1%~D
DVI_TX0+
DVI_TX0+ 36
DVI_CLK-
DVI_CLK- 36
2 1 C971 1 2 R718
0.1U_0402_16V4Z~D 110_0402_1%~D
DVI_CLK+
DVI_CLK+ 36
+AVCC
L77 L78
BLM18PG181SN1_0603~D BLM18PG181SN1_0603~D
+3.3V_RUN 2 1 +AVCC +SVCC 2 1 +1.8V_RUN
10U_0805_10V4Z~D
100P_0402_50V8J~D
1000P_0402_50V7K~D
0.1U_0402_16V4Z~D
C C
1 2 1
1 1 1 1 2 C972 C973 C974
C975
C976
C977
C978
C979
0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 10U_0805_10V4Z~D
0.1U_0402_16V4Z~D 2 1 2
2 2 @ 2 @ 2 1
L79 +3.3V_RUN
+3.3V_RUN BLM18PG181SN1_0603~D
1 1 +SPVCC 2 1
10U_0805_10V4Z~D
100P_0402_50V8J~D
0.1U_0402_16V4Z~D
1000P_0402_50V7K~D
C980 C981
1 1 1 1
C982
C983
C984
C985
0.1U_0402_16V4Z~D 10U_0805_10V4Z~D
2 2 L80
BLM18PG181SN1_0603~D
L81 2 2 @ 2 @ 2 +PVCC1 2 1
10U_0805_10V4Z~D
100P_0402_50V8J~D
1000P_0402_50V7K~D
+1.8V_RUN 2 1 +VCC 1 1 1 1
C986
C987
C988
1 1 1 1
C990 C991 C992 C993 C989
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 2 2 @ 2 @ 2
2 2 2 2
L82
+PVCC2
10
34
28
15
21
36
42
48
11
26
2 1
10U_0805_10V4Z~D
100P_0402_50V8J~D
1000P_0402_50V7K~D
U47
0.1U_0402_16V4Z~D
1 1 1 1
VCC
VCC
VCC
OVCC
AVCC
AVCC
SVCC
SVCC
SPVCC
PVCC1
PVCC2
C995
C996
C997
C998
C994 0.1U_0402_10V7K~D
B INT+ DVI_CLK- B
12 SDVOB_INT+ 1 2 32 SDI+ TXC- 13
1 2 INT- 33 14 DVI_CLK+
12 SDVOB_INT- SDI- TXC+ 2 2 @ 2 @ 2
+5V_RUN C999 0.1U_0402_10V7K~D
SDVOB_RED+ 37 16 DVI_TX0-
12 SDVOB_RED+ SDR+ TX0-
SDVOB_RED- 38 17 DVI_TX0+
12 SDVOB_RED- SDR- TX0+
SDVOB_GREEN+ 40 19 DVI_TX1-
12 SDVOB_GREEN+ SDG+ TX1-
1
1
2.2K_0402_5%~D
2.2K_0402_5%~D
SDVOB_GREEN- 41 20 DVI_TX1+
12 SDVOB_GREEN- SDG- TX1+
R719
R720
SDVOB_BLUE+ 43 22 DVI_TX2-
12 SDVOB_BLUE+ SDB+ TX2-
SDVOB_BLUE- 44 23 DVI_TX2+
12 SDVOB_BLUE- SDB- TX2+
2
12 SDVOB_CLK+ 46 SDC+ SDADDC 9 DVI_SDATA 36

DVI_SCLK 47 8
12 SDVOB_CLK- SDC- SCLDDC DVI_SCLK 36
DVI_SDATA 2
10,21 PLTRST1# RESET#
SDSCL 5 SDVO_CTRLCLK 10
+AVCC 2 1 +VSWING 25 4 SDVO_CTRLDATA 10
R721 220_0402_5%~D EXT_SWING SDSDA
35 EXT_RES A1 6 1 2 +3.3V_RUN
@ R722 1K_0402_5%~D
2
+3.3V_RUN 30 TEST
36 DVI_DETECT 1 2 29 HTPLG
R412 R723 A1 LOW: Address = 0x70
SPGND
PGND2
AGND
AGND
AGND
SGND
SGND
0_0402_5%~D 1K_0402_5%~D
GND
GND
1
HIGH: Address = 0x72
1
R253 R254
1
5.23K_0402_1%~D 5.23K_0402_1%~D SII1362ACTU_LQFP48~D

7
31
27
18
24
12
39
45
3
R724
1K_0402_5%~D
2
SDVO_CTRLCLK
om
SDVO_CTRLCLK, SDVO_CTRLDATA
2
A SDVO_CTRLDATA level is 2.5V A
l.c
1
ai
R812 R813
tm
16.5K_0402_1%~D 16.5K_0402_1%~D
ho
2
f@
Internal LVDS
in
xa
LA-3301P
he
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D D
1 38 HW 08/2/2006 Compal BID change to X01 Pop R108, depop R106 X01
2 18 HW 08/10/2006 Compal Change SOT23 package to SOT323 package Change Q102, to SOT323 package X01
3 7 HW 08/21/2006 Compal BITS issue WI86517 (S5 state back driver issue) Change R324 pin1 connect from +3.3V_ALW to +3.3V_SUS X01
4 41 HW 08/21/2006 Compal Bits issue WI84312 (Derating issue) Change R151 from 30 ohm to 75 ohm X01
Populate R761 and change value from 100k to 10k.
5 23 HW 08/21/2006 Compal Bits issue WI86509 X01
Change R761 pin1 connect from +3.3V_ALW to +3.3V_SUS
Remove R390, R393. Connect LCTLA_CLK and LCTLB_DATA to
GND
7 39 HW 08/21/2006 Compal Bits issue WI86511 Add R401 (100K) for signal BC_DAT pull up to +3.3V_ALW X01
8 37 HW 08/21/2006 Compal Bits issue WI86512 Change R131 to no-stuff and from 4.7k to 100k per SMSC X01
C R509 PU for SIO_EXT_SMI# change from +3.3V_ALW to C
+3.3V_SUS to prevent backdrive through the ICH in S4/S5
Swap PSID GPIO from ECE5018 pin 71 with MEC5025
10 38,39 HW 08/21/2006 Compal Bits issue WI86518 X01
ITP_DBRESET#/HDT_RESET# pin 55
11 38,39 HW 08/21/2006 Compal Bits issue WI86531 Move BEEP (ECE5018 GPIOB[6]) to SGPIO46 of MEC5025 X01
12 18 HW 08/21/2006 Compal Bits issue WI86752 Change pull-up rail for R773 from +5V_SUS to +3.3V_SUS X01
Move SB_NB_PCIE_RST# to GPIO4/PIRQG# pinF12 per M08
design, add R631 (20K ohm) for pull down
Move SB_WLAN_PCIE_RST# to GPIO3/PIRQF# U32 pin G11 per
M08 direction, add test point T1 on pin F18
Bits issue WI86376. Due to increase in number of Change U23 from ( ST M25P80 8M bit ) to ) MXIC
15 39 HW 09/7/2006 Compal X01
payloads the BIOS is carrying MX25L1605AM2C 16M bit )
Change Q5 to MMBT3906WT1G, R15 to 150 ohm. Add R638 on
16 43 HW 09/11/2006 Compal Bits issue WI90535 LED_WLAN_OUT# pull up to +3.3V_WLAN. Add R639 (10K ohm) X01
B
in series on LED_WLAN_OUT# B
17 7 HW 09/14/2006 Compal Briscoe ESD/EMI Improvement Requests on PT Remove ITP port and just keep ITP test point X01
18 43 HW 09/14/2006 Compal Bits issue WI90709 Remove R73, R178, C192, and C193 X01
Add SMBus isolation circuit for WLAN,
R640,R645,R660,R662,Q45,Q46
20 34 HW 09/14/2006 Compal Bits issue WI90691 JMINI1 connect to +3.3V_RUN. Removed C427 X01
Add C181,C192,C193,C196,C207,C209,R667,R685,R686,
21 12 HW 09/14/2006 Compal Shunt caps on LVDS for improving WWAN X01
R687,R688 cross LVDS signals
22 27 HW 09/14/2006 Compal Bits issue WI90516 Remove C759 from mic amp bias circuit X01
23 26 HW 09/14/2006 Compal Bits issue WI90487 Populate R541to cut BEEP level in half X01
populate EMI Clips Clip1, Clip2, Clip3, Clip4, Clip5,
A Clip6 A
Title
Changed-List History
1.0
5 4 3 2 1
5 4 3 2 1

Request
D No stuff R516, add R690 (8.2K ohm) for pull up ICH8 pin D
AF22 to +3.3V_SUS
Add Q68, Q69, R691, R692 for HDDC_EN and MODC_EN
circuits
Change connect R765 pin1, R623 pin1, R621 pin1, R766
pin1 from +5V_ALW to +5V_ALW2
Change R387,R389 from 1M to 2.7K. Add R778,R779 for
AUX_ON,AC_OFF
29 34 HW 09/15/2006 Compal Bits issue WI90698 No stuff C16 X01
30 39 HW 09/15/2006 Compal Bits issue WI92249 Change R730 from 100K to 4.7K ohm X01
31 34 HW 09/15/2006 Compal Bits issue WI92288,WI90714 R660 and R662 connected to CLK_SCLK and CLK_SDATA. X01
32 37,22, HW 09/15/2006 Compal EMI solutions Populate RS232 C152,153,154,155,156,157,158,159. Resume X01
33,28, ICH_AZ_MDC_BITCLK C656,R123,C128. Add R790,R791,C232,
C C
19,20 C267. Change L63,L65 from 0603size to 0805size. Add
C309,C316 for LOM. Add C427,C463 for LVDS. Add fuse F3,
R792 for CRT. Populate C660, R545 (10 ohm),C721 (10P)
Move SIO_EXT_SCI# from to ICH8 GPIO11/SMBALERT# pin AG22
to GPO12 pin AC19. Remove D22 and R761 and net DOCK_DET#
ICH8 Pin AG22 tie to LOM_ICH_SMBALERT#. Add R793 (0 ohm)
X01
series on LOM_ICH_SMBALERT# and LOM_SMB_ALERT#. Change
R730 pull up rail from +3.3V_ALW to +3.3V_LAN. Add R807
34 23 HW 09/18/2006 Compal Bits issue WI92299 pull up to +3.3V_SUS for LOM_ICH_SMBALERT#
Move ALW_PWRGD_3V_5V from MEC5025 pin 18 to MEC5025
pin 29. Remove 3.3V_5V_SUS_PWRGD from MEC5025 pin 29
Swap DOCK_SMB_PME and DOCK_SMB_ALERT# from MEC5025 pin3
and ECE5028 pin76
Removed 3.3V_LAN_PWRGD from MEC5025 KSO15/GPIO5.
Remove U52,Q83,D29,R89,R98,R381,C784,C182,C183,C184
B B
38 39 HW 09/18/2006 Compal Bits issue WI92312 Add R795 (0 ohm) pull down for MEC5025 pin 14 X01
Populate R671~R678 and C866~C869. Change L69~L76 from
39 29 HW 09/19/2006 Compal EMI issue X01
24NH to 36NH inductor
40 27 HW 09/19/2006 Compal Bits issue WI90510 Add R796,R797 (0ohm) between L47/L48 and C728/C730 X01
NC JITP pin 1,2,3,5,7,11,12,13,15,17,19,21,23. Add test
point T47~T52 for ITP_BPM#0~ITP_BPM#5. Remove R322
Change R669 to from 1.15K to 1.13K. Depop C771 & C772.
Change C861 and C862 to 22pF
43 38 HW 09/20/2006 Compal Bits issue WI92857 Add no-stuff series 0-ohm for ITP_DBRESET# on ECE5028 X01
Add R808,R809,R810,R811 series for LCD_DDCCLK,
44 19 HW 09/20/2006 Compal WWAN noise issue X01
LCD_DDCDATA, LCD_SMBCLK, LCD_SMBDAT
45 33 HW 09/21/2006 Compal Bits issue WI93157 Remove R586 and make JMDC pin2 NC X01
om
A A
l.c
ai
tm
ho
f@
Title
in
xa
1.0
he
5 4 3 2 1
5 4 3 2 1

Request
D D
46 34 HW 09/21/2006 Compal Bits issue WI93158 Depop Q45, Q46 X01
Add R812,R813 (9.09K ohm) and chagne R253,R254 to 2.94K
ohm for SDVO_CTRLCLK /DAT voltage divider
48 6 HW 09/25/2006 Compal Bits issue WI93403 C484 change to 33pF, C861/C862 change to 22pF X01
49 29 HW 09/26/2006 Compal Bits issue DF86424 No Populate C866-C869/R671-R678 X01
50 40 HW 09/26/2006 Compal EMI request Add D37-D40 for stick point signals X01
51 32 HW 09/27/2006 Compal EMI request Add FUSE4,FUSE5 X01
52 18 HW 10/05/2006 Compal Bits issue WI94892 Populate R771, C750, R772, Q102, R773 X01
Change R603 from 6.2k to 5.9k.
Change C805 from 820pF to 270pF
C No stuff R227, R221, C89, C93, C97, c401, C92, r72, C
38,23 X01
54 HW 10/05/2006 Compal Bits issue WI95932 C90, C88. Change R369 to 3.3K 1%. No stuff C775-C781,
12,27,6
C785. No stuff R514 (no iAMT). Populate R515.
Added signal DOCK_DET# to JDOCKBpin137, pin205 and
55 36 HW 10/14/2006 Dell Bits issue WI97539 X02
Q3pin2
Add 0.1 uf (0402) caps on +Vcc_Core to Gnd. Four
total, bottom of board. (C870 ~ C873)
1. No stuff R502, R503
57 23 HW 10/18/2006 Dell Bits issue WI98222 (Change for ASF2.0 due to ICH8M errata ) X02
2. Connect the pad of R503.2 to the pad of R498.2
3. Connect the pad of R502.1 to the pad of R499.2
58 38 HW 10/24/2006 Dell Board ID Changed to X02 Populated R106, R107. Depopulated R108, R109. X02
Change L36 to 100 ohm resistor and change C722 to 22nF.
59 13 HW 10/27/2006 Dell Bits issue WI100037. Intel CRT noise issue X02
Replace C569 with a 0603 1uF cap
Add R816,C874 for USB_IDE#. R817,C875 for SIO_EXT_WAKE#.
R819,C876 for PCIE_MCARD1_DET#. R820,C878 for
B B
USB_MCARD1_DET#. R818,C877 for USB_MCARD2_DET#. Remove
net RSVD_GPIO6 and R513
Change Change R812, R813 from 9.09K_1% to 13.7K_1%.
Change R253, R254 from 2.94K_1% to 4.32K_1%
Change L64,L66,L67,L68 from BLM18AG601SN1D to
BK1608LM182. Change R668 to L88 BK1608LM182.Change L63,
L65 from BLM21AG601SN1D to BK2125LM182. Chagne
C850,C852,C856,C858 to 47pF caps. Change C849 to 1000pF.
Populate C863, C864
Change R309 from 8.2K to 2.2K. No stuff R820.
63 6,23,34 HW 11/8/2006 Dell Bits issue WI103311 X02
No stuff R550
64 2 HW 11/8/2006 Dell Correct Block diagram Correct block diagram X02
65 39 HW 11/14/2006 Dell Bits issue WI103986 Change C379 from 22pF to 33pF per KDS X'tal report X02
A A
Title
1.0
5 4 3 2 1
5 4 3 2 1

Request
D D
89 19 HW 2/28/2007 Compal Bits issue WI125145.DPST enablement for UMA Populate R156 (0_0402_5%) A00
90 39 HW 3/1/2007 Compal Bits issue WI125577 Populate R92. Depop R93 A00
91 13 HW 3/1/2007 Compal Bits issue WI125883 Add note "C533,C534,C536,C545,C553,C579 are being A00
replaced by 0-ohm 0805 resistor" on page 13
92 18 HW 3/7/2007 Compal Bits issue WI127297 Populate R441 A00
93 27 HW 3/7/2007 Dell Bits issue WI127300 Change U40 from 74AHC1G08 to 74AHCT1G08 A00
C C
B B
om
A A
l.c
ai
tm
ho
f@
Title
in
xa
1.0
he
5 4 3 2 1
5 4 3 2 1

Request
D Change net name from +5V_ALW2 to +3.3V_ALW2 at R618.1, D
R626.1, R623.1, R621.1, R766.1, R765.1
Change R794 pin1 from +5V_ALW to +3.3V_ALW.
67 38,39 HW 11/21/2006 Dell Bits issue WI105754 X03
Change R245 pin1 from +3.3V_ALW to +5V_ALW
Add 100kohm resistor R721 between U35 pin 40 and
68 26 HW 11/21/2006 Dell Bits issue WI105758. Updates for potential Back Drive X03
+3.3V_RUN and 1000pF cap C759
Change R253, R254 from 2.94K_1% to 5.23K_1%.
Change R812, R813 from 9.09K_1% to 16.5K_1%
Please populate R820 with a 4.7k-ohm resistor. Move
70 21,23,34 HW 12/1/2006 Dell Bits issue WI106999 X03
signal PCIE_MCARD2_DET# from ICH8m GPIO20 pinAE11 to
PIRQH#/GPIO5 pinB3. Delete R457 and net
ICH_GPIO5_PIRQH#. Populate R550
71 41 HW 12/1/2006 Dell Bits issue WI107466. +2.5V_LAN in-rush current test fai. Populate C208 X03
72 27 HW 12/6/2006 Dell Bits issue WI107896 Change R554 from 10K to 0 ohm X03
C C
73 36,38 HW 12/6/2006 Dell Bits issue WI108259. Per M08 GPIO map rev A15 Change list Change net DOCK_SMB_PME to DOCK_SMB_PME# X03
Change C177,C179,C178,C366,C338,C365 to
EEFSX0D221E7 220uF
75 38 HW 12/11/2006 Dell Change Board ID from X02 to X03 Populate R108, Depop R106 X03
Add EC_FLASH_PAD pin1 connect to +3.3V_ALW,pin2 connect
to R76 pin1 and R80 pin1
Add R822 (1M_0402) from Pin 10 (C1P) pin of MAX9789A
to ground
78 13,14 HW 12/15/2006 Dell Bits issue WI109712 Change C544,C560,C615,C551,C564,C593 to X6S SPEC X03
Add R823 (10K_0402) to ground on pin 47 of STAC9205
(U37)
Change R683 from 150ohms to 110 ohms, R684from
150ohms to 200ohms
B 12,23 Change C500~C507,C664,C666~C670,C851,C853,C994,C999 B
81 HW 12/25/2006 Dell Change AC Coupling Cap SPEC for PCIE X03
28 from 0.1uF Y5V to 0.1uF X7R
82 38 HW 1/26/2007 Dell Bits issue WI115658. M08 GPIO map rev A16 change Change ECE5028 GPIOF4 from BID2 to CHIPSET_ID. A00
83 38 HW 1/26/2007 Dell Change BID to from X03 to A00 Depop R107,R108. Populate R106,R109 A00
84 23 HW 2/12/2007 Dell Bits issue WI121957 Add R834 (1M_0402_1%) for ICH_LAN_RST# A00
85 27 HW 2/12/2007 Dell Bits issue WI121438 Change R565 from 10K to 100k ohm A00
86 41 HW 2/12/2007 Dell Bits issue DF116813 Depop C194, changed C815 from 4700pF to 2200pF A00
87 13 HW 2/27/2007 Dell Bits issue WI109712. Because can't find 2nd source Change C560 and (C615, C551, C564) Back to X5R A00
88 23 HW 2/27/2007 Dell Bits issue WI125173. Per Intel's latest recommendation Change R834 from 1M to 10K A00
A A
Title
1.0
5 4 3 2 1
5 4 3 2 1

Request
D D
change PC380 from SF10004M08L to SF000000S8L.
1 48/50 PWR Elick change the AL CAP to 2000hr change PC381 from SF10004M08L to SF000000S8L. 0.1
9/14
change PC382 from SF10004M08L to SF000000S8L.
BITS-WI91007 change PD55 from SCSB717F08L to SCS00001U8L.

2 45 PWR 9/14 DELL change to correct part for 15ALW. change PD56 from SCSB717F08L to SCS00001U8L. 0.1
3 48 PWR change to PSL of DELL

9/14 DELL change PH2 from SL20000030L to SL200000F8L 0.1
4 44 PWR 9/14 DELL change to PSL of DELL change PL1 from SM01001680L to SM010008U0L. 0.1
5 44 PWR change PL2 from SM01001418L to SM010009C8L.

9/14 DELL change to PSL of DELL change PL34 from SM01001418L to SM010009C8L. 0.1
BITS-WI89364
C
The 0.9V_DDR_VTT_PWRGD net is not used at C
6 46 the MEC5025. remove PR437, PR438, PR441, PQ93 and PQ94. 0.1
PWR 9/14 DELL
The 0.9V_DDR_VTT_PWRGD net should be no
connect at the MEC5025 pin 73.
7 BITS-WI90985 Change PC285 pin 2 pad connection

45 PWR 9/14 DELL following DELL rule from PGND to AGND. 0.1
8 BITS-WI90999
Change PQ83 from FDS8880 to Change PQ83 from SB000004U8L to SB000004D8L. 0.1
45 PWR 9/14 DELL
BSC079N03SG PPAK
BITS-WI91012 Change PR383 from 124k(SD03412438L) to

9 45 PWR 9/14 DELL change to correct current limits 150K(SD03415038L). 0.1
Change PR382 from 187k(SD03418738L) to
226K(SD03422638L).
10 47 BITS-WI91287
PWR 9/14 DELL following DELL rule Depopulate PR415 and PR416 resistors. 0.1
B B
BITS-WI91288 change PQ86 from SB54392008L to SB000006N0L 0.1

47 PWR 9/14 DELL Change PQ86 from SI4392DY to SI4682DY.
11
BITS-WI91291 Change PR274 from 4.7 ohm(SD000006T8L) to 33 ohm(SD014330A8L).

12 49 PWR 9/14 DELL be compliant with the reference schematic. Populate PR373 and PD54. 0.1
BITS-WI91374 0.1
13 47 PWR 9/14 DELL following DELL rule Change PR408 from 75K(SD03475028L) to 82.5K(SD00000278L).
BITS-WI91672 Change the node name connected to pin 2 of PR431from +3.3V_ALW

14 46 PWR 9/14 DELL Change in 1.25V_RUN_PWRGD circuit. to +3.3V_SUS. 0.1
Depopulate PR431.
Change PL1 from SM01001680L to SM010008U0L.

15 44 PWR 9/14 DELL BITS-WI91689 Change PQ100 from SI2301BDS(SB923010020) to
DC IN schematic changes.
om
PQ100A depopulated IMD2A(SB000009N8L).
A A
Change PQ101 from SI2301BDS(SB923010020) to
l.c
PQ100B depopulated IMD2A(SB000009N8L). 0.1
ai
Change PR12 from 10K,0603(SD01310028L) to 4.7K,0805(SD00247018L).
tm
ho
f@
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Changed-List History 1
in
xa
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD LA-3301P 0.6
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
he
5 4 3 2 1
5 4 3 2 1

Request
D D
16 46 PWR 9/15 DELL BITS-WI92156
correct the current limit on 1.25V 0.1
change PR425 from 39.2K(SD03439228L) to 51.1K (SD03451128L)
output
BITS-WI91655
17 46 PWR 9/15 DELL Add 0.1uF connected to the pins 1 and 2 Add PC410(SE042104K8L). One pad connected to the pins 1 and 2 of PU24 . 0.1
of PU24 The other pad is connected to PGND.
BITS-WI91929
18 46 PWR 9/15 DELL correct the current limit on 1.8V change PR426 from 110K(SD03411038L) to 130K (SD03413038L) 0.1
output
BITS-WI92465 Add depopulate PR516(SD03410018L) and depopulate PC413(SE076103K8L)

19 48 PWR 9/18 DELL improve transients at load dump. between pin 9 of PU11 and AGND. 0.1
and reduce jittering. Add depopulated PC411(SE075472K8L),4700pF between pin 14 of PU11 and AGND .
Add depopulated PC412(SE075472K8L),4700pF between pin 15 of PU11 and AGND
C C
BITS-WI91689
20 44 PWR 9/21 DELL change PL1 from BK1608HM to BLM18BD102SN1D. change PL1 from SM010008U0L to SM010007C8L. 0.1
BITS-WI87563
21 48/50 PWR 9/21 DELL change populate PC380 from 25CE100AX change populate PC380 from SF000000S8L to SF000000T8L.
to 25CE100LS change PC381 from SF000000S8L to SF000000T8L. 0.1
change PC381 from 25CE100AX to 25CE100LS change PC382 from SF000000S8L to SF000000T8L.
change PC382 from 25CE100AX to 25CE100LS
match Maxim's response time of ICM input change PR361 from 0 Ohm (SD02800008L) to 8.45K (SD00000068L).
22 49 PWR 9/29 DELL to comparator. change PC254 from 0.01uF 25V (SE068103K8L) to 0.1uF 16V (SE076104K8L). 0.1
B B
ICM is voltage source and does not

DELL need this component.
23 49 PWR 9/29 depopulate PR150. 0.1
Increase BW from 20kHz to 25kHz while

24 49 PWR 9/29 DELL maintaining 80degrees phase margin. change PR148 from 4.7K (SD03447018L) to 10K (SD03410028L). 0.1
25 49 PWR 9/29 DELL following DELL rule depopulate PD54 and PR373 0.1
Add bead to connect +PWR_SRC to

26 48 PWR 10/27 DELL +CPU_PWR_SRC Add PL44(SM01002078L) to parallel PJP30. 0.2
BITS-WI99902
This is to add an optional ultrasonic mode Add PR517(SD02800008L) between pin 29 of PU20 and AGND .
27 45,46,47 PWR 10/27 DELL in case the regulators experience an audible Add PR518(SD02800008L) between pin 29 of PU22 and AGND . 0.2
noise. Add PR519(SD02800008L) between pin 29 of PU21 and AGND .
A A
28 46 PWR 10/31 DELL BITS-WI100140 0.2

Change PR429 from 0 ohm to 1 ohm change PR429 from 0 Ohm (SD01300008L ) to 1 Ohm(SD013100B8L).
Title
Changed-List History 2
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-3301P 0.6
5 4 3 2 1
5 4 3 2 1

Request
D D
BITS: WI102613
29 49 PWR 11/16 DELL Change PR148 from 10K_0402_1% to 2.2K_0402 change PR148 from 10K 0402 1% (SD03410028L ) to 2.2k 0402 5%(SD02822018L) 0.3
_5%
BITS-WI105401
30 45 PWR 11/20 DELL Add node name +3.3V_ALW2 for the trace Add node name +3.3V_ALW2 between pin5 of PU20 and PC285.
connected to the pin 5 (VREF3) of PU20. Populate PC285. 0.3
Populate PC285 with 0.1uF cap.
BITS-WI106278
31 49 PWR 12/06 DELL make sure that PC113, PC114 and PC379 are
X5R/X75 caps, need to stuff PC379. change PC379 is populated. 0.3
BITS-WI108223
Change PC187 from 10nF to 15nF. change PR187 from 10nF(SE076103K8L) to 15nF(SE076153K8L).
C Change PR258 from 2.21K to 1.69K. change PR258 from 2.21K(SD03422118L) to 1.69K(SD00000JB8L). 0.3 C
32 48 PWR 12/06 DELL populate PC413.
Populate PR516 with 1K resistor.
Populate C413 with 0.01uF. populate PR516.
delete
not to
change PR138 from SD021100D8L to SD021100D3L(S RES 1W .01 +-1% 2512

33 49 PWR 01/25 ELICK change to new part number for PSL FOR M08 PROJECTS)
change PR145 from SD021100D8L to SD021100D3L(S RES 1W .01 +-1% 2512 0.4
FOR M08 PROJECTS)
BITS-WI119945 change PR382 from 226K to 267k (SD02822018L).

34 45/47 PWR 02/05 DELL Increase current limits for 3.3V and 1.5V Change PR408 from 82.5K to 100K(SD03410038L). 0.4
regulators.
35 49 PWR 02/06 DELL additional 1206 resistor on +VCHGR for add an unpopulation PR520 (1.8K 1206 1%(SD00000JN8L))between
B
Maxim solution. +VCHGR to PGND. 0.4 B
36 49 PWR 02/12 DELL delete 1206 resistor on +VCHGR delete an unpopulate PR520 (1.8K 1206 1%(SD00000JN8L))between
not to implement for Maxim solution. +VCHGR to PGND. 0.4
om
A A
l.c
ai
tm
ho
f@
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Changed-List History 3
in
xa
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-3301P 0.6
he
5 4 3 2 1

COMPAL LA 3301P IBQ00 REV 1.0 (ComunidadeTecnica - Com.br)

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

COMPAL LA 3301P IBQ00 REV 1.0 (ComunidadeTecnica - Com.br)

Uploaded by

Copyright:

Available Formats

A B C D E

PCB NO : LA-3301P (DA80000771L)

M08 (UMA) Briscoe 2

uFCPGA Mobile Merom

DA80000771L PCB ZGX LA-3301P BOM NO. 45144631L01

USB[2,3] REAR USB2 : Rear Left as viewed from the back,

DC IN Vccore Int.KBD & ST M25P16

Battery IN Charger Bluetooth Stick Touch Pad Biometric

+15V_ALW +5V_SUS +5V_RUN 9 WWAN

S5 S4/AC don't exist OFF OFF OFF

Lane 1 MINI CARD-1 WWAN

Lane 2 MINI CARD-2 WLAN

64 PCIE_LOM# 1 2 CLK_PCIE_LOM# CLK_PCIE_LOM# 28 CLK_PCI_5018

23 CLK_PWRGD CLK_PWRGD 39 60 C781

PCI_PCM @ R295 CKPWRGD/PD# SRC_5 3.3P_0402_50V8C~D

1 CKPWRGD/PD# 4 56 MCH_3GPLL# 1 2 CLK_MCH_3GPLL# CLK_MCH_3GPLL# 10

PCI_ICH VSS_REF SRC_2

1 Pin 5/6 as CPU_ITP 35 26

TME PIN 32 68 51 PCIE_SATA# 1 2 CLK_PCIE_SATA# CLK_PCIE_SATA# 22

PCI_LOM FSA THRM_PAD LCD_CLK/SRC_0 R316 33_0402_5%~D

0=UMA DOT96T DOT96C 96/100M_T 96/100M_C

H_FERR# A5 C7 2200P_0402_50V7K~D E16 AB11

B2 RSVD[05] G4 VSS[053] VSS[134] AC21

2 For the purpose of testability, route these signals R342

Place C close to the FSB BCLK BSEL2 BSEL1 BSEL0

800 200 0 1 0 R341

2K_0402_1%~D DELL CONFIDENTIAL/PROPRIETARY

Compal Electronics, Inc.

Place these inside 1 1 1 1 1 1 1 1 1 1

Place these inside 1 1 1 1 1 1 1 1 1 1

Place these inside 1 1 1 1 1 1

Place these inside 1 1 1 1 1 1 10uF 0805 X6S -> 85 degree C

High Frequence Decoupling

Near VCORE regulator.

C870 C871 C872 C873

2 2 2 2 2 2 Capacitor > 1980uF

H_D#36 AC7 G20 H_ADSTB#1 DMI_MRX_ITX_N0 AN47

H_D#60 AE5 AD2 H_DSTBN#2 H_DSTBN#2 8 L32 T75 PAD~D

H_D#61 AJ3 AH11 H_DSTBN#3 H_DSTBN#3 8 N33 CFG19 CFG19 12

R348 H_D#62 AH2 PAD~D T42 E35 L35 CFG20 CFG20 12

H_SWNG H_DSTBP#_2 H_DSTBP#3 GFX_VID_3 PM_BMBUSY#

D7 H_RS#1 CL_CLK0 AM49

CL_VREF CL_RST# NC_2 PM_EXTTS#0

LE88CLGM A0 QM20_FCBGA1299~D CL_VREF NC_3

+1.8V_SUS BL49 R354

1K_0402_1%~D SDVO_CTRLDATA SDVO_CTRL_CLK NC_9

SMRCOMP_VOH ICH_SYNC# NC_12

R774 0_0402_5%~D A50 R589

2 1 A37 A49 @ 0_0402_5%~D

1K_0402_1%~D 221_0402_1%~D R357 R36 R583

3.01K_0402_1%~D PLTRST1#_R 1 2 2 1PLTRST1# PLTRST1# 21,51

DDR_A_DQS#7 AP2 AV13 DDR_A_D32 DDR_B_DQS#7 AV3 BK13 DDR_B_D32

DDR_A_MA7 BJ25 BD8 DDR_A_D42 DDR_B_MA7 BC28 BK5 DDR_B_D42

LE88CLGM A0 QM20_FCBGA1299~D LE88CLGM A0 QM20_FCBGA1299~D

N45 SDVOB_RED-_C C500 1 2 0.1U_0402_10V7K~D

F27 Y43 R374 1 2 @4.02K_0402_1%~D

L27 TVC_RTN PEG_TX#_8 W38

H32 M45 SDVOB_RED+_C C504 1 2 0.1U_0402_10V7K~D

20,36 CRT_RED F29 CRT_RED PEG_TX_4 R51

CRT_HSYNC F33 AD47

@ C181 3.3P_0402_50V8C~D LCD_ACLK+_C 1 2 BSS138_SOT23~D

+3.3V_RUN @ C209 3.3P_0402_50V8C~D 1

1 U12 VTT_2 VCCA_CRT_DAC_1 A33 1 2 2 1