Dell Alienware 13 R2 LA-C901P Rev1.0 (A00) PDF

A B C D E
MODEL NAME : AAP01

PROJECT CODE : ANRAAP0100
PCB NO :
DAA000AK000 LA-C901P M/B
DA400237000 LS-C901P SSD/B
1 1
DA40023X000 LS-C902P SSD/B (w/o redriver)

DA40023Y000 LS-C904P LOGO/B
ZZZ PCB@
PCB 1FU LA-C901P REV0 M/B MLK 3

DAA000AK000
ZZZ PCBR1@
2
PCB 1FU LA-C901P REV1 M/B MLK 3
Echo MLK 13" SKL-U 2
DAA000AK010
ZZZ PCBR3@
Skylake U-type (1 chip_DSC)
PCB 1FU LA-C901P REV1 MB MLK TRIP 3 A31!

REV : 1.0 (A00)
DAA000AK011
ZZZ DAZR1@
2015.07.14
@ : Nopop Component
PCB AAP01 LA-C901P LS-A302P/A303P/C904P 02
DAZ1FU00100
EMI@,ESD@ : EMI/ESD/RF part
CONN@ : Connector Component
CMC@ : Total debug Component
3 3
HDMI@ ROYALTY HDMI W/LOGO

Part Number Description
RO0000002HM HDMI W/Logo:RO0000002HM
Layout Dell logo
COPYRIGHT 2015
ALL RIGHT RESERVED
4 REV: X00 4
PWB: XXXXX
DATE: 1450-06
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/01/06 Deciphered Date 2016/01/06 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C901P
Date: Tuesday, August 04, 2015 Sheet 1 of 63
A B C D E
A B C D E
P.20 P.06~17
P.36
eDP eDP 1.3 FFS Fan control P.40 CMC connector
P.06
panel KXCNL-1010 NCT7718W (Reserve)

W83L771AWG-2
1 1
P.47 P.44,45 P.18,19

DP 1.2 (DDI1)
USB3 Memory Bus Dual Channel
P.46 ThunderBolt DP 1.2 (DDI2) 204pin SO-DIMM x2
TypeC 1.35V,DDR3L,1600 MHz
TPS65982 Alpine Ridge-SP PCI-E x2(port9,port10)
USB PD I2C/USB2
P.21
P.33
HDMI USB3.0 port2 USB connector 1 , Left side
connector USB2.0 port2 USB power share
P.33
USB3.0 port1
HDMI 2.0 USB connector 2 , Right side 1
USB2.0 port1
P.22~29 P.34
dGPU
nVIDIA PCI-E x4 (Gen3) PCI-E(Gen3)x4
port1~port4
N16P-GX,50W
4pcs GDDR5
PCIE MUX
PERICOM Skylake U USB2.0 port5 P.20
2 P.34
PI3PCIE3415 + Touch screen 2
PCI-E x4 (Gen3)
Skylake PCH-LP (MCP) USB2.0 port6
Digital camera(with digital MIC)
P.20
Video
Docking
USB3.0 port3 (SKL-U_2+2)
P.37
Caldera USB2.0 port3
15W BGA 1356 balls USB2.0 port7
AlienFX / ELC , C8051F383-GQ
CDR_I2C
P.38,39
CDR_I2C
ELC PWM expander , TLC59116F
P.32
PCI-E3.0 port5 P.38,39
NGFF (M.2)WLAN+BT LED SET
QCA killer 1535(A Key) USB2.0 port8
P.36
P.30 P.30 SATA3.0 port0 ; option
RJ45 LAN(Gigabit) PCI-E3.0 port6 2.5”HDD
connector Killer E2400
Storage Option1
3
NGFF (M.2) PCI-E3.0 port7,8 3
SSD 1 SATA3.0 port0,1

P.31
PCI-E3.0 port11,12 digital MIC
NGFF (M.2)
Storage Option2 SSD 2 SATA3.0 port1,2
P.31
Dual M.2 DB Speaker
P.08
SPI ROM SPI Audio codec
16MB HD Audio Realtek P.31
ALC3234 Headphone/MIC Global headset
DC in 1.0V dGPU combo JACK
Battery Core P.31
LPC Bus
I2C(400KHz) Headphone/MIC Retaskable
3V/5V 1.5V Charger combo JACK
P.40 P.41
Int. KBD
P.38
PS2
System CPU dGPU ENE KB9022 Touch pad
P.41
4
1.35V Vcore 1.35V ENE KC3810 4

Block diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
A B C D E
A
Power on sequence
EC_ON AC DC
VCCDSW(+3VALW) AC DC
PCH_PWR_EN(SLP_SUS#) AC DC
+3V/+1.8V_PRIM AC DC
SUSACK# AC DC
Power Button
DPWROK_EC
EC_RSMRST#
AC_Present
Power Button Out

1 1
PM_SLP_S4# (Input)
PM_SLP_S3# (Input)
SYSON
SUP#
VCCST_PG_EC
VR_ON
VR_PWRGD
PCH_PWROK
SYS_PWROK
PLT_RST#
Power on sequence
A
A
Board ID Table for AD channel

Vcc 3.3V
Ra 100K +/- 1% USB3.0
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3
0 0 0.000V 0.300V 0x00 - 0x13 Port1 Right side 1
1 12K +/- 1% 0.347V 0.354V 0.360V 0x14 - 0x1E
2 15K +/- 1% 0.423V 0.430V 0.438V 0x1F - 0x25 Port2 Left side (power share)
3 20K +/- 1% 0.541V 0.550V 0.559V 0x26 - 0x30
4 27K +/- 1% 0.691V 0.702V 0.713V 0x31 - 0x3A Port3 Caldera
5 33K +/- 1% 0.807V 0.819V 0.831V 0x3B - 0x45
6 43K +/- 1% 0.978V 0.992V 1.006V 0x46 - 0x54 Port4
7 56K +/- 1% 1.169V 1.185V 1.200V 0x55 - 0x64
8 75K +/- 1% 1.398V 1.414V 1.430V 0x65 - 0x76 USB2.0
9 100K +/- 1% 1.634V 1.650V 1.667V 0x77 - 0x87
10 130K +/- 1% 1.849V 1.865V 1.881V 0x88 - 0x96 Port1 Right side 1
11 160K +/- 1% 2.015V 2.031V 2.046V 0x97 - 0xA4
12 200K +/- 1% 2.185V 2.200V 2.215V 0xA5 - 0xAF Port2 Left side (power share)
13 240K +/- 1% 2.316V 2.329V 2.343V 0xB0 - 0xB7
14 270K +/- 1% 2.395V 2.408V 2.421V 0xB8 - 0xBF Port3 Caldera
15 330K +/- 1% 2.521V 2.533V 2.544V 0xC0 - 0xC9
16 430K +/- 1% 2.667V 2.677V 2.687V 0xCA - 0xD4 Port4
17 560K +/- 1% 2.791V 2.800V 2.808V 0xD5 - 0xDD
18 750K +/- 1% 2.905V 2.912V 2.919V 0xDE - 0xF0 Port5 Touch screen
19 NC 3.000V 3.000V 0xF1 - 0xFF
Port6 Camera
Board ID table and PCB version ULT Port7 ELC
ID Rb
0 0 EVT(R0.1) Port8 BT
1
1 12K DVT-1(R0.2) 1
2 15K DVT-1.1(R0.3) PCI EXPRESS

3 20K DVT-2(R0.4)
4 27K Pilot(R1.0) Lane 1~4 MUX for dGPU & Caldera
5 33K
6 43K Lane 5 WLAN(M.2 Card)
7 56K
Lane 6 10/100/1000 LAN
Lane 7~8 M.2 SATA+PCIeX2

CLOCK SIGNAL
Symbol Note :
Lane 9~10 Alpine Ridge SP
CLKOUT_PCIE0 N16P-GX +Caldera
: means Digital Ground Lane 11~12 M.2 SATA+PCIeX2
CLKOUT_PCIE1 M.2 Card WLAN+BT
SATA
: means Analog Ground CLKOUT_PCIE2 Giga LAN
SATA0 HDD or SSD1
CLKOUT_PCIE3 M.2 NGFF SSD
SATA1 SSD2
CLKOUT_PCIE4 Thunderbolt
SATA2 SSD2
CLKOUT_PCIE5 M.2 NGFF SSD
SATA3

Notes list
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
A
5 4 3 2 1
1K 10K
D D
1K
+3V_PRIM 10K
+3VS
N-MOS
R7 MEM_SMBCLK SOC_SMBCLK 202 DIMMA SMBUS Address [0x00]
N-MOS
R8 MEM_SMBDATA SOC_SMBDATA 200
2.2K
202 DIMMB SMBUS Address [0x01]
2.2K
+3VS
200
SKYLAKE R9 SOC_SML0CLK 11 CLK BUFFER 4 FFS SMBUS Address [0x1D]

ULT W2 SOC_SML0DATA 10 6
1K
1K
+3V_PRIM
N-MOS
W3 SOC_SML1CLK EC_SMB_CK2
N-MOS
C V3 SOC_SML1DATA EC_SMB_DA2 C
2.2K 1.8K
2.2K
+3VS 1.8K
+3VS_VGA
N-MOS UV1
79 EC_SMB_CK2 VGA_SMB_CK2 T4 GPU SMBUS Address [0x9E]
N-MOS
80 EC_SMB_DA2 VGA_SMB_DA2 T3
8 UF1 SMBUS Address [0x98]

7
8 UF2 SMBUS Address [0x9A]

KBC 7
B
KB9022QD B
2.2K UF3
8 SMBUS Address [0X98]
(On SSD/B)
2.2K
+3VALW_EC 7 <Reserve>
0 ohm PU700
77 EC_SMB_CK1 SCL 12 Charger SMBUS Address [0x12]
0 ohm
78 EC_SMB_DA1 SDA 11
100 ohm
CLK_SMB 7 PBATT1 SMBUS Address [0x16]
100 ohm
DAT_SMB 6
PCI-E
EC_SMB_CK1 50 Re-Driver SMBUS Address [RX:0xB2 / TX:0xB6]
EC_SMB_DA1 49
0 ohm Power
A TBTA_I2C_SCL1_R B5 Deliver SMBUS Address [0x70] A
0 ohm
TBTA_I2C_SDA1_R A5

SMBus block diagram
Size
1.0
5 4 3 2 1
A B C D E
UC1 UC1 UC1A SKL-U

Rev_1.0
E55 C47
<44> SOC_DP1_N0 F55 DDI1_TXN[0] EDP_TXN[0] C46 EDP_TXN0 <20>
<44> SOC_DP1_P0 E58 DDI1_TXP[0] EDP_TXP[0] D46 EDP_TXP0 <20>
<44> SOC_DP1_N1 DDI1_TXN[1] EDP_TXN[1] EDP_TXN1 <20> <eDP_FHD>
F58 C45 <eDP_4K2K>
<44> SOC_DP1_P1 F53 DDI1_TXP[1] EDP_TXP[1] A45 EDP_TXP1 <20>
S IC A31 FJ8066201924932 QHMG C0 1.6G S IC A31 FJ8066201924925 QHMF C0 2.3G <44> SOC_DP1_N2 DDI1_TXN[2] EDP_TXN[2] EDP_TXN2 <20>
SA00008M30L SA00008M40L G53 B45
<44> SOC_DP1_P2 F56 DDI1_TXP[2] EDP_TXP[2] A47 EDP_TXP2 <20>
1.6GES@ 2.3GES@
<44> SOC_DP1_N3 G56 DDI1_TXN[3] EDP_TXN[3] B47 EDP_TXN3 <20>
<44> SOC_DP1_P3 DDI1_TXP[3] EDP_TXP[3] EDP_TXP3 <20>
<Thunderbolt>
UC1 I5-6200U UC1 I7-6500U C50 E45
<44> SOC_DP2_N0 DDI2_TXN[0] DDI EDP EDP_AUXN EDP_AUXN <20>
D50 F45
<44> SOC_DP2_P0 DDI2_TXP[0] EDP_AUXP EDP_AUXP <20>
C52
1 <44> SOC_DP2_N1 D52 DDI2_TXN[1] B52 1
EDP_DISP_UTIL
<44> SOC_DP2_P1 A50 DDI2_TXP[1] EDP_DISP_UTIL TP@ T9
<44> SOC_DP2_N2 B50 DDI2_TXN[2] G50
<44> SOC_DP2_P2 DDI2_TXP[2] DDI1_AUXN SOC_DP1_AUXN <44>
S IC A31 FJ8066201930409 QJ8N D0 2.3G S IC A31 FJ8066201930408 QJ8L D0 2.5G D51 F50
<44> SOC_DP2_N3 DDI2_TXN[3] DDI1_AUXP SOC_DP1_AUXP <44>
SA000092O0L SA000092P0L C51 E48
<44> SOC_DP2_P3 DDI2_TXP[3] DDI2_AUXN SOC_DP2_AUXN <44>
i5QS@ i7QS@ F48
DDI2_AUXP SOC_DP2_AUXP <44>
G46
UC1 UC1 DISPLAY SIDEBANDS RSVD F46 TP@ T7 Thunderbolt
I5-6200U I7-6500U RSVD TP@ T8
SOC_DP1_CTRL_CLK L13
<44> SOC_DP1_CTRL_CLK L12 GPP_E18/DDPB_CTRLCLK L9
SOC_DP1_CTRL_DATA SOC_DP1_HPD SOC_DP1_HPD <44>
Thunderbolt <44> SOC_DP1_CTRL_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7 SOC_DP2_HPD
GPP_E14/DDPC_HPD1 SOC_DP2_HPD <44>
SOC_DP2_CTRL_CLK N7 L6 HDMI_HPD
<44> SOC_DP2_CTRL_CLK GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 HDMI_HPD <21> From dGPU
Pull High at TBT side SOC_DP2_CTRL_DATA N8 N9 EC_SCI#
<44> SOC_DP2_CTRL_DATA GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 EC_SCI# <41>
S IC A31 FJ8066201930409 QJKP D1 2.3G S IC A31 FJ8066201930408 QJKK D1 2.5G L10 EDP_HPD
GPP_E17/EDP_HPD EDP_HPD <20> From eDP
SA000092O1L SA000092P1L N11
i5QS'@ i7QS'@ +1.0VS_VCCIO N12 GPP_E22 R12 EDP_BKLTEN
GPP_E23 EDP_BKLTEN R11 EDP_BKLT_PWM EDP_BKLTEN <41> 2 1
EDP_BKLTCTL EDP_BIA_PWM <20>
UC1 I5-6200U UC1 I7-6500U RC1 1 2 EDP_COMP E52 1 OF 20 U13 EDP_VDDEN RC10 0_0402_5%
EDP_RCOMP EDP_VDDEN EDP_VDDEN <20>
24.9_0402_1%
CAD note: @ SKL-U_BGA1356
Trace width=20 mils,Spacing=25mil,Max length=100mils
+3VS
S IC FJ8066201930409 SR2EY D1 2.3G A31!S IC FJ8066201930408 SR2EZ D1 2.5G A31! UC1D SKL-U RPC16
SA000092O3L SA000092P3L Rev_1.0 EC_SCI# 1 8
i5R3@ i7R3@ H_CATERR# D63 EDP_HPD 2 7
T26 TP@ CATERR#
H_PECI A54 EDP_VDDEN 3 6
<41> H_PECI PECI
1 2 H_PROCHOT#_R C65 JTAG 4 5
<41,51,52> H_PROCHOT# PROCHOT#
RC4 499_0402_1% H_THERMTRIP# C63
SOC_OCC# A65 THERMTRIP# 100K_8P4R_5%
T25 TP@ SKTOCC#
CPU MISC B61 CPU_XDP_TCK0
+1.0V_VCCST XDP_BPM#0 C55 PROC_TCK D60 SOC_XDP_TDI
2 +3VS T16 TP@ BPM#[0] PROC_TDI 2
XDP_BPM#1 D55 A61 SOC_XDP_TDO
T19 TP@ BPM#[1] PROC_TDO
For BIOS Verify UMA/DIS SKU XDP_BPM#2 B54 C60 SOC_XDP_TMS
T10 TP@ BPM#[2] PROC_TMS
1 2 H_THERMTRIP# XDP_BPM#3 C56 B59 SOC_XDP_TRST#
T11 TP@ BPM#[3] PROC_TRST#
RC2 1K_0402_5%
1 UMA@ 2 DGPU_PRSNT# DGPU_PRSNT# A6 B56 PCH_JTAG_TCK1 SOC_XDP_TDO
GPP_E3/CPU_GP0 PCH_JTAG_TCK
RC212 10K_0402_5% +1.0VS_VCCSTG TS_INT# is not Used at Echo A7
GPP_E7/CPU_GP1 PCH_JTAG_TDI
D59 SOC_XDP_TDI SOC_XDP_TDI
SOC_XDP_TRST# As Short As Possible
1 DIS@ 2 PCH_TP_INT# BA5 A56 SOC_XDP_TDO
<41> PCH_TP_INT# AY5 GPP_B3/CPU_GP2 PCH_JTAG_TDO C59
RC213 10K_0402_5% T40 TP@ SOC_GPIOB4 SOC_XDP_TMS
GPP_B4/CPU_GP3 PCH_JTAG_TMS
1
RC3
2 H_PROCHOT#
1K_0402_5% RC5 2 1 49.9_0402_1% CPU_POPIRCOMP AT16 PCH_TRST#
C61
A59
SOC_XDP_TRST#
CPU_XDP_TCK0
CPU_XDP_TCK0
GPP_E15 DGPU_PRSNT# PROC_POPIRCOMP JTAGX
RC6 2 1 49.9_0402_1% PCH_OPIRCOMP AU16
RC7 2 1 49.9_0402_1% EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP SOC_XDP_TDI 1 2
DIS,Optimus 0 OPCE_RCOMP
RC8 2 1 49.9_0402_1% EOPIO_RCOMP H65 SOC_XDP_TDO @ESD@ CC64 1 20.1U_0402_16V7K
OPC_RCOMP SOC_XDP_TRST# @ESD@
CC65 1 20.1U_0402_16V7K
UMA 1
4 OF 20 CPU_XDP_TCK0 @ESD@CC69 1 20.1U_0402_16V7K
@ SKL-U_BGA1356 @ESD@
CC70 0.1U_0402_16V7K
+3V_PRIM Change from +3VALW to +3V_PRIM to fix leakage on S5

PRIMARY CMC CONN
APS CONN 1
RC9
2 XDP_SPI_SI
1K_0402_5%
+1.0V_PRIM +1.0V_XDP
RC12 1 @ 2 0_0603_1%
@
+3VALW +3V_PRIM RPC2
+1.0VS_VCCSTG Place to CPU side SOC_XDP_TDO 1 8 XDP_TDO
3 JAPS1 SOC_XDP_TDI 2 7 XDP_TDI 3
1 SOC_XDP_TMS 3 6 XDP_TMS
2 1 RC11 2 CMC@ 1 51_0402_5% SOC_XDP_TMS CPU_XDP_TCK0 4 5 XDP_TCK0
<10,13,37,41> PM_SLP_S3# 2
3 CFG0
4 3 <17> CFG0
<10,37,41> PM_SLP_S5# RC13 2 CMC@ 1 51_0402_5% SOC_XDP_TDI 0_0804_8P4R_5% CFG1
5 4 <17> CFG1 CFG2 TP@ T37
<10,13,37,41,54> PM_SLP_S4# 5 <17> CFG2 TP@ T38
6 RC15 2 CMC@ 1 51_0402_5% SOC_XDP_TDO @ CFG3
<10> PM_SLP_A# 6 <17> CFG3
7 RPC4 CFG4 XDP_TRST#
7 <17> CFG4 T13 TP@
8 SOC_XDP_TRST# 1 8 XDP_TRST# CFG5 XDP_TDI
8 <17> CFG5 TP@ T47 T20 TP@
9 PCH_JTAG_TCK1 2 7 XDP_TCK1 CFG6 XDP_TMS
<10> SOC_RTCRST#_R 9 <17> CFG6 TP@ T48 T21 TP@
10 CFG3 3 6 XDP_PRSENT_CPU CFG7 XDP_TCK0
10 <17> CFG7 TP@ T49 T24 TP@
11 XDP_SPI_IO2 4 5 XDP_PRSENT_PCH XDP_TCK1
<10,41> PBTN_OUT# 11 <8> XDP_SPI_IO2 T27 TP@
12 CFG17 XDP_TDO
12 +1.0V_XDP <17> CFG17 TP@ T50 T28 TP@
13 0_0804_8P4R_5% CFG16
<10> SYS_RESET# 13 <17> CFG16 TP@ T51
14 XDP_PREQ#
14 T29 TP@ XDP_PREQ# <12>
15 CFG8 XDP_PRDY#
<10,41> PM_SLP_S0# 15 <17> CFG8 TP@ T52 T30 TP@ XDP_PRDY# <12>
16 RC31 1 CMC@ 2 1K_0402_5% XDP_ITP_PMODE @ CFG9
17 16 <17> CFG9 CFG10 TP@ T53 XDP_HOOK0
RPC15 T31 TP@
18 17 <17> CFG10 TP@ T54
RC32 1 @ 2 1K_0402_5% CFG0
<8> XDP_SPI_SI
XDP_SPI_SI 1 8 XDP_HOOK3 CFG11
T32 TP@
XDP_HOOK3
19 18 XDP_ITP_PMODE 2 7 XDP_HOOK6 <17> CFG11 CFG12 TP@ T55 XDP_HOOK6
GND <17> XDP_ITP_PMODE <17> CFG12 TP@ T56 T33 TP@
20 RC43 2 @ 1 0_0402_5% XDP_PRSENT_CPU 3 6 CFG13
GND 4 5 <17> CFG13 TP@ T57
CFG14
<17> CFG14 TP@ T58
ACES_50506-01841-P01 RC46 2 @ 1 0_0402_5% XDP_PRSENT_PCH CFG15
<17> CFG15 TP@ T59
CONN@ 0_0804_8P4R_5%
CFG19
<17> CFG19 TP@ T60
RC35 2 CMC@ 1 51_0402_1% CPU_XDP_TCK0 CFG18
1 CMC@ 2 <17> CFG18 TP@ T61
EC_RSMRST# XDP_HOOK0
<10,41> EC_RSMRST#
RC37 2 @ 1 51_0402_5% PCH_JTAG_TCK1 RC158 1K_0402_5%
Place to CPU side

CFG4 1 2
4 RC193 1K_0402_1% 4
Security Classification
2015/01/06
Compal Secret Data
2016/01/06 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
SKL-U(1/12)DDI,MSIC,XDP,EDP
Size
A B C D E
5 4 3 2 1
Non-Interleaved Memory
D D
SKL-U
UC1C
UC1B SKL-U Rev_1.0
Rev_1.0
<18> DDR_A_D[0..15] AL71 AU53 <18> DDR_A_D[16..31] AF65
Interleave / Non-Interleaved
AN45
DDR_A_D0 DDR_A_CLK#0 DDR_A_CLK#0 <18> DDR_A_D16 DDR_B_CLK#0 DDR_B_CLK#0 <19>
DDR_A_D1 AL68 DDR0_DQ[0] DDR0_CKN[0] AT53 DDR_A_CLK0 DDR_A_D17 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46 DDR_B_CLK#1
DDR0_DQ[1] DDR0_CKP[0] DDR_A_CLK0 <18> DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] DDR_B_CLK#1 <19>
DDR_A_D2 AN68 AU55 DDR_A_CLK#1 DDR_A_D18 AK65 AP45 DDR_B_CLK0
DDR0_DQ[2] DDR0_CKN[1] DDR_A_CLK#1 <18> DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] DDR_B_CLK0 <19>
DDR_A_D3 AN69 AT55 DDR_A_CLK1 DDR_A_D19 AK64 AP46 DDR_B_CLK1
DDR0_DQ[3] DDR0_CKP[1] DDR_A_CLK1 <18> DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 <19>
DDR_A_D4 AL70 DDR_A_D20 AF66
DDR_A_D5 AL69 DDR0_DQ[4] BA56 DDR_A_CKE0 DDR_A_D21 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 DDR_B_CKE0
DDR0_DQ[5] DDR0_CKE[0] DDR_A_CKE0 <18> DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] DDR_B_CKE0 <19>
DDR_A_D6 AN70 BB56 DDR_A_CKE1 DDR_A_CKE1 <18> DDR_A_D22 AK67 AP55 DDR_B_CKE1 DDR_B_CKE1 <19>
DDR_A_D7 AN71 DDR0_DQ[6] DDR0_CKE[1] AW56 DDR_A_D23 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55
DDR0_DQ[7] DDR0_CKE[2] TP@ T14 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] TP@ T17
DDR_A_D8 AR70 AY56 DDR_A_D24 AF70 AP53
DDR0_DQ[8] DDR0_CKE[3] TP@ T15 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3] TP@ T18
DDR_A_D9 AR68 DDR_A_D25 AF68
DDR_A_D10 AU71 DDR0_DQ[9] AU45 DDR_A_CS#0 DDR_A_D26 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42 DDR_B_CS#0
DDR0_DQ[10] DDR0_CS#[0] DDR_A_CS#0 <18> DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] DDR_B_CS#0 <19>
DDR_A_D11 AU68 AU43 DDR_A_CS#1 DDR_A_CS#1 <18> DDR_A_D27 AH68 AY42 DDR_B_CS#1 DDR_B_CS#1 <19>
DDR_A_D12 AR71 DDR0_DQ[11] DDR0_CS#[1] AT45 DDR_A_ODT0 DDR_A_D28 AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42 DDR_B_ODT0
DDR0_DQ[12] DDR0_ODT[0] DDR_A_ODT0 <18> DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] DDR_B_ODT0 <19>
DDR_A_D13 AR69 AT43 DDR_A_ODT1 DDR_A_D29 AF69 AW42 DDR_B_ODT1
DDR0_DQ[13] DDR0_ODT[1] DDR_A_ODT1 <18> DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDR_B_ODT1 <19>
DDR_A_D14 AU70 DDR_A_D30 AH70
DDR_A_D15 AU69 DDR0_DQ[14] DDR_A_D31 AH69 DDR1_DQ[14]/DDR0_DQ[30]
DDR0_DQ[15] DDR3L / LPDDR3 / DDR4 <18> DDR_A_D[48..63] DDR1_DQ[15]/DDR0_DQ[31] DDR3L / LPDDR3 / DDR4
BA51 DDR_A_MA5 DDR_A_MA5 <18> DDR_A_D48 AT66 AY48 DDR_B_MA5 DDR_B_MA5 <19>
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 DDR_A_MA9 DDR_A_D49 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50 DDR_B_MA9
<18> DDR_A_D[32..47] Interleave / Non-Interleaved DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR_A_MA9 <18> DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR_B_MA9 <19>
DDR_A_D32 BB65 BA52 DDR_A_MA6 DDR_A_D50 AP65 BA48 DDR_B_MA6
DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR_A_MA6 <18> DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR_B_MA6 <19>
DDR_A_D33 AW65 AY52 DDR_A_MA8 DDR_A_MA8 <18> DDR_A_D51 AN65 BB48 DDR_B_MA8 DDR_B_MA8 <19>
DDR_A_D34 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52 DDR_A_MA7 DDR_A_D52 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDR_B_MA7
DDR_A_D35 AY63 AY55 DDR_A_BS2 DDR_A_BS2 <18> DDR_A_D53 AP66 AP52 DDR_B_BS2 DDR_B_BS2 <19>
DDR_A_D36 BA65 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AW54 DDR_A_MA12 DDR_A_D54 AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDR_B_MA12
DDR_A_D37 AY65 BA54 DDR_A_MA11 DDR_A_D55 AU65 AN48 DDR_B_MA11
DDR_A_D38 BA63 BA55 DDR_A_MA15 DDR_A_MA15 <18> DDR_A_D56 AT61 AN53 DDR_B_MA15 DDR_B_MA15 <19>
C DDR_A_D39 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 DDR_A_MA14 DDR_A_D57 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52 DDR_B_MA14 C
DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_MA14 <18> DDR1_DQ[25]/DDR0_DQ[57] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR_B_MA14 <19>
DDR_A_D40 BA61 AU46 DDR_A_MA13 DDR_A_MA13 <18> DDR_A_D58 AP60 BA43 DDR_B_MA13 DDR_B_MA13 <19>
DDR_A_D41 AW61 DDR0_DQ[24]/DDR0_DQ[40] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDR_A_CAS# DDR_A_D59 AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 DDR_B_CAS#
DDR0_DQ[25]/DDR0_DQ[41] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR_A_CAS# <18> DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR_B_CAS# <19>
DDR_A_D42 BB59 AT46 DDR_A_WE# DDR_A_D60 AN61 AY44 DDR_B_WE#
DDR0_DQ[26]/DDR0_DQ[42] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR_A_WE# <18> DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR_B_WE# <19>
DDR_A_D43 AW59 AU50 DDR_A_RAS# DDR_A_RAS# <18> DDR_A_D61 AP61 AW44 DDR_B_RAS# DDR_B_RAS# <19>
DDR_A_D44 BB61 DDR0_DQ[27]/DDR0_DQ[43] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 DDR_A_BS0 DDR_A_D62 AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44 DDR_B_BS0
DDR0_DQ[28]/DDR0_DQ[44] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR_A_BS0 <18> DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR_B_BS0 <19>
DDR_A_D45 AY61 AY51 DDR_A_MA2 DDR_A_MA2 <18> DDR_A_D63 AU60 AY47 DDR_B_MA2 DDR_B_MA2 <19>
DDR0_DQ[29]/DDR0_DQ[45] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] <19> DDR_B_D[16..31] DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR_A_D46 BA59 AT48 DDR_A_BS1 DDR_B_D16 AU40 BA44 DDR_B_BS1
DDR0_DQ[30]/DDR0_DQ[46] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR_A_BS1 <18> DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR_B_BS1 <19>
DDR_A_D47 AY59 AT50 DDR_A_MA10 DDR_B_D17 AT40 AW46 DDR_B_MA10
<19> DDR_B_D[0..15] DDR0_DQ[31]/DDR0_DQ[47] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR_A_MA10 <18> DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR_B_MA10 <19>
DDR_B_D0 AY39 BB50 DDR_A_MA1 DDR_A_MA1 <18> DDR_B_D18 AT37 AY46 DDR_B_MA1 DDR_B_MA1 <19>
DDR_B_D1 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 DDR_A_MA0 DDR_B_D19 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 DDR_B_MA0
DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR_A_MA0 <18> DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR_B_MA0 <19>
DDR_B_D2 AY37 DDR_B_D20 AR40
DDR_B_D3 AW37 DDR0_DQ[34]/DDR1_DQ[2] BA50 DDR_A_MA3 DDR_B_D21 AP40 DDR1_DQ[36]/DDR1_DQ[20] BB46 DDR_B_MA3
DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] DDR_A_MA3 <18> DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[3] DDR_B_MA3 <19>
DDR_B_D4 BB39 BB52 DDR_A_MA4 DDR_B_D22 AP37 BA47 DDR_B_MA4
DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDR_A_MA4 <18> DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[4] DDR_B_MA4 <19>
DDR_B_D5 BA39 AM70 DDR_A_DQS#0 DDR_A_DQS#0 <18> DDR_B_D23 AR37
DDR_B_D6 BA37 DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQSN[0] AM69 DDR_A_DQS0 DDR_B_D24 AT33 DDR1_DQ[39]/DDR1_DQ[23]
DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSP[0] DDR_A_DQS0 <18> DDR1_DQ[40]/DDR1_DQ[24] Interleave / Non-Interleaved
DDR_B_D7 BB37 AT69 DDR_A_DQS#1 DDR_A_DQS#1 <18> DDR_B_D25 AU33 AH66 DDR_A_DQS#2 DDR_A_DQS#2 <18>
DDR_B_D8 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSN[1] AT70 DDR_A_DQS1 DDR_B_D26 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDR_A_DQS2
DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSP[1] DDR_A_DQS1 <18> DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[0]/DDR0_DQSP[2] DDR_A_DQS2 <18>
DDR_B_D9 AW35 DDR_B_D27 AT30 AG69 DDR_A_DQS#3
DDR0_DQ[41]/DDR1_DQ[9] DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[1]/DDR0_DQSN[3] DDR_A_DQS#3 <18>
DDR_B_D10 AY33 DDR_B_D28 AR33 AG70 DDR_A_DQS3 DDR_A_DQS3 <18>
DDR0_DQ[42]/DDR1_DQ[10] Interleave / Non-Interleaved DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[1]/DDR0_DQSP[3]
DDR_B_D11 AW33 BA64 DDR_A_DQS#4 DDR_A_DQS#4 <18> DDR_B_D29 AP33 AR66 DDR_A_DQS#6 DDR_A_DQS#6 <18>
DDR_B_D12 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR_A_DQS4 DDR_B_D30 AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDR_A_DQS6
DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSP[2]/DDR0_DQSP[4] DDR_A_DQS4 <18> DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[2]/DDR0_DQSP[6] DDR_A_DQS6 <18>
DDR_B_D13 BA35 AY60 DDR_A_DQS#5 DDR_B_D31 AP30 AR61 DDR_A_DQS#7
DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSN[3]/DDR0_DQSN[5] DDR_A_DQS#5 <18> DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[3]/DDR0_DQSN[7] DDR_A_DQS#7 <18>
DDR_B_D14 BA33 BA60 DDR_A_DQS5 AR60 DDR_A_DQS7
DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSP[3]/DDR0_DQSP[5] DDR_A_DQS5 <18> <19> DDR_B_D[48..63] DDR1_DQSP[3]/DDR0_DQSP[7] DDR_A_DQS7 <18>
DDR_B_D15 BB33 BA38 DDR_B_DQS#0 DDR_B_DQS#0 <19> DDR_B_D48 AU27 AT38 DDR_B_DQS#2 DDR_B_DQS#2 <19>
<19> DDR_B_D[32..47] DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSN[4]/DDR1_DQSN[0] DDR1_DQ[48] DDR1_DQSN[4]/DDR1_DQSN[2]
DDR_B_D32 AY31 AY38 DDR_B_DQS0 DDR_B_DQS0 <19> DDR_B_D49 AT27 AR38 DDR_B_DQS2 DDR_B_DQS2 <19>
DDR_B_D33 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDR_B_DQS#1 DDR_B_D50 AT25 DDR1_DQ[49] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDR_B_DQS#3
DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSN[5]/DDR1_DQSN[1] DDR_B_DQS#1 <19> DDR1_DQ[50] DDR1_DQSN[5]/DDR1_DQSN[3] DDR_B_DQS#3 <19>
DDR_B_D34 AY29 BA34 DDR_B_DQS1 DDR_B_D51 AU25 AR32 DDR_B_DQS3
DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSP[5]/DDR1_DQSP[1] DDR_B_DQS1 <19> DDR1_DQ[51] DDR1_DQSP[5]/DDR1_DQSP[3] DDR_B_DQS3 <19>
DDR_B_D35 AW29 BA30 DDR_B_DQS#4 DDR_B_D52 AP27
DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSN[6]/DDR1_DQSN[4] DDR_B_DQS#4 <19> DDR1_DQ[52]
DDR_B_D36 BB31 AY30 DDR_B_DQS4 DDR_B_DQS4 <19> DDR_B_D53 AN27 AR25 DDR_B_DQS#6 DDR_B_DQS#6 <19>
DDR_B_D37 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDR_B_DQS#5 DDR_B_D54 AN25 DDR1_DQ[53] DDR1_DQSN[6] AR27 DDR_B_DQS6
DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSN[7]/DDR1_DQSN[5] DDR_B_DQS#5 <19> DDR1_DQ[54] DDR1_DQSP[6] DDR_B_DQS6 <19>
DDR_B_D38 BA29 BA26 DDR_B_DQS5 DDR_B_DQS5 <19> DDR_B_D55 AP25 AR22 DDR_B_DQS#7 DDR_B_DQS#7 <19>
DDR_B_D39 BB29 DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_B_D56 AT22 DDR1_DQ[55] DDR1_DQSN[7] AR21 DDR_B_DQS7
DDR0_DQ[55]/DDR1_DQ[39] DDR1_DQ[56] DDR1_DQSP[7] DDR_B_DQS7 <19>
DDR_B_D40 AY27 AW50 DDR_B_D57 AU22 AN43
DDR_B_D41 AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_ALERT# AT52 DDR_B_D58 AU21 DDR1_DQ[57] DDR1_ALERT# AP43
DDR0_DQ[57]/DDR1_DQ[41] DDR0_PAR TP@ T22 DDR1_DQ[58] DDR1_PAR TP@ T23
B DDR_B_D42 AY25 DDR_B_D59 AT21 AT13 DDR_DRAMRST# DDR_DRAMRST# <18,19>
B
DDR_B_D43 AW25 DDR0_DQ[58]/DDR1_DQ[42] DDR CH - A AY67 +0.675V_VREFCA DDR_B_D60 AN22 DDR1_DQ[59] DDR CH - B DRAM_RESET# AR18
DDR0_DQ[59]/DDR1_DQ[43] DDR_VREF_CA +0.675V_VREFCA DDR1_DQ[60] DDR_RCOMP[0]
DDR_B_D44 BB27 AY68 +0.675V_A_VREFDQ DDR_B_D61 AP22 AT18
DDR0_DQ[60]/DDR1_DQ[44] DDR0_VREF_DQ +0.675V_A_VREFDQ DDR1_DQ[61] DDR_RCOMP[1]
DDR_B_D45 BA27 BA67 +0.675V_B_VREFDQ Trace width/Spacing >= 20mils DDR_B_D62 AP21 AU18 SM_RCOMP0 RC38 1 2 121_0402_1%
DDR0_DQ[61]/DDR1_DQ[45] DDR1_VREF_DQ +0.675V_B_VREFDQ DDR1_DQ[62] DDR_RCOMP[2]
DDR_B_D46 BA25 DDR_B_D63 AN21 3 OF 20 SM_RCOMP1 RC39 1 2 80.6_0402_1%
DDR_B_D47 BB25 DDR0_DQ[62]/DDR1_DQ[46] 2 OF 20 AW67 DDR1_DQ[63] SM_RCOMP2 RC40 1 2 100_0402_1%
DDR0_DQ[63]/DDR1_DQ[47] DDR_VTT_CNTL @ SKL-U_BGA1356
@ SKL-U_BGA1356
Buffer with Open Drain Output

For VTT power control
+1.35V_VDDQ +3VALW +3VS
0.1U_0201_10V6K 2 1 CC57
1
UC7 RC123 RC129
1 5 100K_0402_5% 100K_0402_5%
NC VCC @
DDR_PG_CTRL 2
2
2
A 4
Y 0.675V_DDR_VTT_ON <54>
3
GND
74AUP1G07GW_TSSOP5
A A

SKL-U(2/12)DDRIII
Custom 1.0
5 4 3 2 1
5 4 3 2 1
+3VS
RC21/44 place to within 1100 mil of SPIO_MOSI/SPI0_IO2 pin for CMC

SOC_SMBALERT# SOC_SML0ALERT# SML1 Bus : EC/dGPU/THERMAL
2 CMC@ 1 SOC_SPI_SI
TLS CONFIDENTIALITY EC interface
<6> XDP_SPI_SI
2
RC44 1K_0402_1% HIGH ENABLE HIGH ESPI ----->For KB9032 Only.
2 CMC@ 1 SOC_SPI_IO2
G
<6> XDP_SPI_IO2
RC21 1K_0402_1% LOW(DEFAULT) DISABLE LOW(DEFAULT) LPC ----->For KB9022/9032 Use SOC_SML1CLK 6 1 EC_SMB_CK2 <22,40,41,46>
5
QC2B
DMN66D0LDW -7_SOT363-6
G
D
+3VS SOC_SML1DATA 3 4 D
EC_SMB_DA2 <22,40,41,46>
S
2 1 FFS_INT2 QC2A
10K_0402_5% RC324 UC1E SKL-U DMN66D0LDW -7_SOT363-6
2 1 FFS_INT1 Rev_1.0
SPI - FLASH +3V_PRIM
10K_0402_5% RC325 SMBUS, SMLINK
2 1 EC_KBRST# SOC_SPI_CLK AV2 R7 MEM_SMBCLK +3VS
10K_0402_5% @ RC326 SOC_SPI_SO AW3 SPI0_CLK GPP_C0/SMBCLK R8 MEM_SMBDATA
SMB -> DDR , WLAN , FFS SOC_SMBALERT# 1 2
SOC_SPI_SI AV3 SPI0_MISO GPP_C1/SMBDATA R10 SOC_SMBALERT# RC130 8.2K_0402_5%
SOC_SPI_IO2 AW2 SPI0_MOSI GPP_C2/SMBALERT# RPC12
SOC_SPI_IO3 AU4 SPI0_IO2 R9 SOC_SML0CLK
SML0 -> PCIE CLK BUFFER MEM_SMBCLK 1 8
SPI0_IO3 GPP_C3/SML0CLK SOC_SML0CLK <34>
SOC_SPI_CS#0 AU3 W2 SOC_SML0DATA SOC_SML0DATA <34> MEM_SMBDATA 2 7
SOC_SPI_CS#1 AU2 SPI0_CS0# GPP_C4/SML0DATA W1 SOC_SML0ALERT# 2 1 SOC_SML1CLK 3 6
T41 TP@ SPI0_CS1# GPP_C5/SML0ALERT#
AU1 RC202 4.7K_0402_5% SOC_SML1DATA 4 5
SPI0_CS2# W3 SOC_SML1CLK
GPP_C6/SML1CLK V3 SOC_SML1DATA 1K_0804_8P4R_5%
SPI - TOUCH GPP_C7/SML1DATA AM7 SOC_SML1ALERT#
SML1 -> EC , dGPU , THERMAL , TBT SOC_SML1ALERT# 1 2
FFS_INT1 M2 GPP_B23/SML1ALERT#/PCHHOT# RC41 @ 150K_0402_1%
<36> FFS_INT1 GPP_D1/SPI1_CLK
M3
FFS_INT2 J4 GPP_D2/SPI1_MISO
<36> FFS_INT2 GPP_D3/SPI1_MOSI
V1 RPC8
V2 GPP_D21/SPI1_IO2 AY13 ESPI_IO0 ESPI_IO0 1 8 ESPI_IO0_R
GPP_D22/SPI1_IO3 GPP_A1/LAD0/ESPI_IO0 ESPI_IO0_R <41>
M1 LPC BA13 ESPI_IO1 ESPI_IO2 2 7 ESPI_IO2_R ESPI / LPC Bus
GPP_D0/SPI1_CS# GPP_A2/LAD1/ESPI_IO1 ESPI_IO2_R <41>
BB13 ESPI_IO2 To EC ESPI_IO1 3 6 ESPI_IO1_R
GPP_A3/LAD2/ESPI_IO2 ESPI_IO1_R <41> ESPI : +1.8V
AY12 ESPI_IO3 ESPI_IO3 4 5 ESPI_IO3_R
C LINK GPP_A4/LAD3/ESPI_IO3 ESPI_IO3_R <41>
BA12 ESPI_CS#
ESPI_CS# <41>
LPC : +3.3V
G3 GPP_A5/LFRAME#/ESPI_CS# BA11 SUS_STAT# 0_0804_8P4R_5%
T42 TP@ CL_CLK GPP_A14/SUS_STAT#/ESPI_RESET# Echo MLK use LPC
T43 TP@ G2 <Echo13> LPC@ RC45 RPC8
G1 CL_DATA LPC@
T44 TP@ CL_RST#
C LPC Mode AW9 ESPI_CLK 1 2 C
GPP_A9/CLKOUT_LPC0/ESPI_CLK ESPI_CLK_R <41> To EC
AY9 RC45 22_0402_5%
EC_KBRST# AW13 GPP_A10/CLKOUT_LPC1 AW11 PM_CLKRUN#
<41> EC_KBRST# GPP_A0/RCIN# GPP_A8/CLKRUN# PM_CLKRUN# <41> For TPM
SERIRQ AY11 +3V_PRIM 15_0402_5% 15_0804_8P4R_5%
<41> SERIRQ GPP_A6/SERIRQ 5 OF 20 ESPI@ ESPI@
@ SKL-U_BGA1356
SUS_STAT# 1 @ 2 +3V_SPI
+3VS RC36 10K_0402_5% Reserve For EC Auto Load Code
SMB Bus : DDR/WLAN/FFS SOC_SPI_IO2 RC47 1 @ 2 1K_0402_1%
2 1 SERIRQ
8.2K_0402_5% RC122 +3VS +3VS SOC_SPI_IO3 RC48 1 @ 2 1K_0402_1%
SOC_SPI_CS#0 RC53 1 @ 2 1K_0402_1%

Follow 543016_SKL_U_Y_PDG_0_9
SOC_SPI_IO3 RC51 1 @ 2 1K_0402_1%
1
RC66 RC67 *****ONLY*****
10K_0402_5% 10K_0402_5%
From WW36 MOW for SKL-U ES sample
2
+3VS
G
MEM_SMBCLK 6 1
SOC_SMBCLK <18,19,36>
S
QC3B PM_CLKRUN# 1 2
5
DMN66D0LDW -7_SOT363-6 RC107 8.2K_0402_5%
G
B
Follow TD team B
MEM_SMBDATA 3 4
SOC_SMBDATA <18,19,36>
S
QC3A
DMN66D0LDW -7_SOT363-6
Single SPI ROM_CS0#

RPC5 and RC52 are close UC2 16M SPI ROM(Support ISH)
RPC5 +3V_SPI
SOC_SPI_SO_0_R 1 8 SOC_SPI_SO
SOC_SPI_SI_0_R 2 7 SOC_SPI_SI UC2 CC8 1 2 0.1U_0201_10V6K
SOC_SPI_CLK_0_R 3 6 SOC_SPI_CLK SOC_SPI_CS#0 1 8
SOC_SPI_IO3_0_R 4 5 SOC_SPI_IO3 SOC_SPI_SO_0_R 2 /CS VCC 7 SOC_SPI_IO3_0_R
To SPI ROM SOC_SPI_IO2_0_R 3 DO(IO1) /HOLD(IO3) 6 SOC_SPI_CLK_0_R 1 2
15_0804_8P4R_5% 4 /WP(IO2) CLK 5 SOC_SPI_SI_0_R CC9
GND DI(IO0) 10P_0402_50V8J
W 25Q128FVSIQ_SO8 @EMI@
A
RC52 A
SOC_SPI_IO2_0_R 2 1 SOC_SPI_IO2
15_0402_5%
2015/01/06
Compal Secret Data
2016/01/06 Title
SKL-U(3/12)SPI,ESPI,SMB,LPC
5 4 3 2 1
5 4 3 2 1
#545659 SKL_PCH_EDS_R0.7 P.84 UC1G SKL-U

Rev_1.0
HDA for AUDIO
AUDIO
RPC9
D <31> HDA_BIT_CLK_R 1 8 HDA_BIT_CLK HDA_SYNC BA22 D
2 7 HDA_RST# HDA_BIT_CLK AY22 HDA_SYNC/I2S0_SFRM
<31> HDA_RST#_R HDA_BLK/I2S0_SCLK
<31> HDA_SDOUT_R 3 6 HDA_SDOUT HDA_SDOUT BB22 SDIO / SDXC
4 5 HDA_SYNC HDA_SDIN0 BA21 HDA_SDO/I2S0_TXD
<31> HDA_SYNC_R HDA_SDI0/I2S0_RXD
AY21 AB11
33_0804_8P4R_5% HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12
HDA_SDIN0 AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
<31> HDA_SDIN0 I2S1_SFRM GPP_G3/SD_DATA2
AW20 W11
I2S1_TXD GPP_G4/SD_DATA3 W10
AK7 GPP_G5/SD_CD# W8
HDA_BIT_CLK_R AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7
Functional Strap Definitions AK9 GPP_F0/I2S2_SCLK
GPP_F2/I2S2_TXD
GPP_G7/SD_WP
1 AK10 BA9
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
CC53 GPP_A16/SD_1P8_SEL
SPKR / GPP_B14 (Internal Pull Down): 22P_0402_50V8J H5 AB7 SD_RCOMP RC76 2 1 200_0402_1%
2 D7 GPP_D19/DMIC_CLK0 SD_RCOMP
(Sampled:Rising edge of PCH_PWROK) GPP_D20/DMIC_DATA0
Close to RPC9 D8 AF13
C8 GPP_D17/DMIC_CLK1 GPP_F23
TOP Swap Override GPP_D18/DMIC_DATA1
0 = Disable TOP Swap mode. -->AAX05 use SPKR AW5
<31> SPKR GPP_B14/SPKR
1 = Enable TOP Swap Mode.
7 OF 20
@ SKL-U_BGA1356
C
TOP Swap Override C
To Enable ME Override Reserve RC229 follow TD team dat.04/23
+3VS TD Team Solution ABO Solution

<9,41> ME_EN 1 @ 2
RC229 100K_0402_5%
2
RC117 1 @ 2 2.2K_0402_5% SPKR
G
+3V_PRIM 1 2 1 3 HDA_SDOUT <9,41> ME_EN 1 @ 2 HDA_SDOUT
RC77 1K_0402_1% RC313 0_0402_5%
S
QC1
BSS138W -7-F_SOT323-3
UC1I SKL-U
Rev_1.0
CSI-2
A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
B C36 CSI2_DP1 CSI2_CLKP1 C29 B
D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
B38 CSI2_DN3 CSI2_CLKN3 A26
CSI2_DP3 CSI2_CLKP3
C31 E13 CSI2_COMP RC80 2 1 100_0402_1%
D31 CSI2_DN4 CSI2_COMP B7
C33 CSI2_DP4 GPP_D4/FLASHTRIG
D33 CSI2_DN5
A31 CSI2_DP5 EMMC
B31 CSI2_DN6 AP2
A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
9 OF 20 AT1 EMMC_RCOMP 2 1
EMMC_RCOMP RC89 200_0402_1%
@ SKL-U_BGA1356
A A
2015/01/06
Compal Secret Data
2016/01/06 Title
SKL-U(4/12)HDA,EMMC,SDIO,CSI2
5 4 3 2 1
5 4 3 2 1
UC1J SKL-U
Rev_1.0
**Avoid Sub-trace**
CLOCK SIGNALS Closed to CPU
CLK_PCIE_N0 D42 XTAL@
<34> CLK_PCIE_N0 CLKOUT_PCIE_N0
DGPU CLK_PCIE_P0 C42 SOC_XTAL24_IN 15P_0402_50V8J1 2
<34> CLK_PCIE_P0 CLKOUT_PCIE_P0
<22,34> CLKREQ_PCIE#0 CLKREQ_PCIE#0 AR10 1 CC13
GPP_B5/SRCCLKREQ0#
CLK_PCIE_N1 B42
<32> CLK_PCIE_N1 CLKOUT_PCIE_N1 1
NGFF WALN+BT CLK_PCIE_P1 A42 F43 CLK_CPU_ITP# TP@T89
<32> CLK_PCIE_P1 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N
<32> CLKREQ_PCIE#1 CLKREQ_PCIE#1 AT7 E43 CLK_CPU_ITP TP@T90 2 YC1 XTAL@
GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P GND
2
24MHZ_12PF_7V24000020
CLK_PCIE_N2 D41 BA17 SUSCLK RC92
<30> CLK_PCIE_N2 CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK <32,36>
D LAN CLK_PCIE_P2 C41 1M_0402_5% D
<30> CLKREQ_PCIE#2 CLKREQ_PCIE#2 AT8 E37 SOC_XTAL24_IN XTAL@ 4
GPP_B7/SRCCLKREQ2# XTAL24_IN E35 SOC_XTAL24_OUT GND
1
CLK_PCIE_N3 D40 XTAL24_OUT
<36> CLK_PCIE_N3 CLKOUT_PCIE_N3 3
NGFF SSD CLK_PCIE_P3 C40 E42 XCLK_BIASREF
<36> CLK_PCIE_P3 CLKOUT_PCIE_P3 XCLK_BIASREF
<36> CLKREQ_PCIE#3 CLKREQ_PCIE#3 AT10 XTAL@
GPP_B8/SRCCLKREQ3# AM18 SOC_RTCX1 SOC_XTAL24_OUT 3 1 2
CLK_PCIE_N4 B40 RTCX1 AM20 SOC_RTCX2 15P_0402_50V8J CC12
<44> CLK_PCIE_N4 CLKOUT_PCIE_N4 RTCX2
Thunderbolt CLK_PCIE_P4 A40
<44> CLKREQ_PCIE#4 CLKREQ_PCIE#4 AU8 AN18 SOC_SRTCRST#
GPP_B9/SRCCLKREQ4# SRTCRST# AM16 SOC_RTCRST# 1 @ 2
RTCRST# SOC_RTCRST#_R <6>
CLK_PCIE_N5 E40 RC104 0_0201_1%
<36> CLK_PCIE_N5 CLKOUT_PCIE_N5
NGFF SSD CLK_PCIE_P5 E38
<36> CLKREQ_PCIE#5 CLKREQ_PCIE#5 AU7
GPP_B10/SRCCLKREQ5#
10 OF 20
@ SKL-U_BGA1356
**Avoid Sub-trace**
+3VS
+3VL_RTC
RC105 1 2 10K_0402_5% CLKREQ_PCIE#5 +1.0V_CLK5_F24NS Closed to CPU

SOC_SRTCRST# 20K_0402_5% 2 1 RC91 XTAL@
SOC_RTCX2 4.7P_0402_50V8C 1 2 CC16
RPC10
RC96 1 2 2.7K_0402_1% 1U_0402_6.3V6K 2 1 CC10
8 1 CLKREQ_PCIE#1
2
7 2 CLKREQ_PCIE#2 XCLK_BIASREF RC124 1 @ 2 60.4_0402_1% CLR ME SHORT PADS 2 1 CLRP1
2
6 3 CLKREQ_PCIE#3 RC98
C 5 4 CLKREQ_PCIE#0 Follow 546765_2014WW48_Skylake_MOW_Rev_1_0 10M_0402_5% YC2 XTAL@ C
SOC_RTCRST# 20K_0402_5% 2 1 RC93 XTAL@ 32.768KHZ 9PF 20PPM 9H03280012
10K_0804_8P4R_5% Stuff 2.7k ohm(RC96) PH for Skylake U
1
From 545659_SKL_PCH_U_Y_EDS_R0_7 1U_0402_6.3V6K 2 1 CC11
Stuff 60.4 ohm(RC124) PD for Cannonlake U SHORT PADS 2 1 CLRP2 SOC_RTCX1 1 2
CLR CMOS
+3VALW _DSW 4.7P_0402_50V8C CC15
XTAL@
SM_INTRUDER# 1M_0402_5% 2 1RC94
+3V_PRIM From 543016_SKL_PDG_UY_v1.0

RPC11
8 1 PCH_PW ROK
7 2 LAN_W AKE#
6 3 EC_RSMRST#
5 4 SYS_RESET# PCH PLTRST Buffer +3VS
CC14
10K_0804_8P4R_5% 1 2
+3V_PRIM
5
UC3 0.1U_0201_10V6K
CLRP3 2 1 SHORT PADS SYS_RESET# SOC_PLTRST# 1 SOC_VRALERT# 10K_0402_5%2 @ 1RC115
P
<22,34> SOC_PLTRST# B 4
O PLT_RST# <30,32,36,41,44>
RC101 2 1 100K_0402_5% PCH_DPW ROK 2
A
G
+3VALW _DSW
TC7SH08FU_SSOP5~D
3
PM_BATLOW # 8.2K_0402_5% 2 1 RC103
AC_PRESENT_R 10K_0402_5% 2 1 RC106
+3VALW _DSW PBTN_OUT#_R 100K_0402_5% 1 @ 2 RC111
RC99 1 @ 2 0_0402_5%
B 1 2 W AKE_PCH#_R B
RC108 10K_0402_5%
UC1K SKL-U
Rev_1.0
EC_VCCST_PG SYSTEM POWER MANAGEMENT
H_CPUPWRGD As Short As Possible GPP_B12/SLP_S0#

AT11
AP15
PM_SLP_S0#
PM_SLP_S3#
PM_SLP_S0# <6,41>
SYS_RESET# SOC_PLTRST# AN10
GPP_B13/PLTRST#
GPD4/SLP_S3#
GPD5/SLP_S4#
BA16 PM_SLP_S4#
PM_SLP_S3#
PM_SLP_S4#
<6,13,37,41>
<6,13,37,41,54>
<6> SYS_RESET# SYS_RESET# B5 AY16 PM_SLP_S5#
SYS_RESET# GPD10/SLP_S5# PM_SLP_S5# <6,37,41>
<6,41> EC_RSMRST# EC_RSMRST# AY17
RSMRST# AN15 SLP_SUS#
SLP_SUS# SLP_SUS# <14,41>
T95 TP@ H_CPUPW RGD_R 1 2 H_CPUPW RGD A68 AW15 SLP_LAN# TP@ T87
RC102 @ 1K_0402_5% EC_VCCST_PG B65 PROCPWRGD SLP_LAN# BB17 SLP_W LAN#
VCCST_PWRGD GPD9/SLP_WLAN# TP@ T88
H_CPUPW RGD SYS_RESET# Only For Power Sequence Debug AN16 PM_SLP_A# PM_SLP_A# <6>
SYS_PW ROK B6 GPD6/SLP_A#
1 1 <41> SYS_PW ROK SYS_PWROK
CC60 CC63 <41> PCH_PW ROK PCH_PW ROK BA20 BA15 PBTN_OUT#_R RC109 1 @ 2 0_0402_1% PBTN_OUT# <6,41>
100P_0402_50V8J 0.1U_0402_16V7K 1 @ 2 PCH_DPW ROK BB20 PCH_PWROK GPD3/PWRBTN# AY15 AC_PRESENT_R 2 1
@ESD@ @ESD@
<41> DPW ROK_EC
EC_RSMRST# RC112 1 @ 2 0_0402_1% DSW_PWROK GPD1/ACPRESENT AU13 PM_BATLOW # DC2 RB751V-40_SOD323-2
ACIN <22,37,41,51,52>
PM_BATLOW # <44>
Follow Echo
2 2 RC114 0_0402_5% SUSW ARN# AR13 GPD0/BATLOW#
<41> SUSW ARN# GPP_A13/SUSWARN#/SUSPWRDNACK
<41> SUSACK# 1 @ 2 SUSACK#_R AP11
RC110 1 @ 2 0_0402_1% GPP_A15/SUSACK# AU11
GPP_A11/PME# TP@ T91
RC100 1 @ 2 1K_0402_5% W AKE_PCH#_R BB15 AP16 SM_INTRUDER#
<41> W AKE_PCH# WAKE# INTRUDER#
RC68 0_0402_1% LAN_W AKE# AM15
+3V_PRIM AW17 GPD2/LAN_WAKE# AM10 EXT_PW R_GATE#
T92 TP@ GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# EXT_PW R_GATE# <14>
CC83 T94 TP@ AT15 AM11 SOC_VRALERT#
1 2 +1.0V_VCCST GPD7/RSVD 11 OF 20 GPP_B2/VRALERT#
A
0.1U_0201_10V6K UC9 @ SKL-U_BGA1356 A
5
TC7SH08FU_SSOP5~D
PM_SLP_S3# 1 RC113 From EC(open-drain)
P
B 4 1K_0402_5%
O VR_ON <58>
<41> VR_ON_EC 2
A
G
RC116
2
1 2 EC_VCCST_PG
<41> VCCST_PG_EC Security Classification Compal Secret Data Compal Electronics, Inc.
3
60.4_0402_1% 1 2015/01/06 2016/01/06 Title

1 @ 2 CC54
RC127 0_0402_5% 100P_0402_50V8J
SKL-U(5/12)CLK,GPIO
For meet tPLT17 & tCPU28 power down sequence. @ESD@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
2 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
tPLT17 : 1us (Max) MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C901P
tCPU28 : 1us (Max) Date: Tuesday, August 04, 2015 Sheet 10 of 63
5 4 3 2 1
5 4 3 2 1
+3VS
+3V_1.8V_PGPPD +3V_1.8V_PGPPD
RC203 2 1 10K_0402_5% SOC_GPIOB21

RC205 2 1 10K_0402_5% EC_SMI# VGA_ID RC321 1 @ 2 10K_0402_5% PROJECT_ID0 RC318 2 @ 1 10K_0402_5%
RC316 1 2 10K_0402_5% RC315 1 2 10K_0402_5%
RC62 2 1 49.9K_0402_1% UART_2_CRXD_DTXD +3V_PRIM RANK_ID RC320 1 SR@ 2 10K_0402_5% PROJECT_ID1 RC314 2 @ 1 10K_0402_5%
RC63 2 1 49.9K_0402_1% UART_2_CTXD_DRXD RC317 1 DR@ 2 10K_0402_5% RC319 1 2 10K_0402_5%
RC207 2 @ 1 100K_0402_5% RTD3_USB_PW R_EN
D RPC7 D
8 1 I2C_1_SDA VGA_ID GPP_D9 RANK_ID GPP_D10 Project_ID1 Project_ID0

7 2 I2C_1_SCL Project ID
6 3 I2C_0_SDA GL 0 DR 0 GPP_D12 GPP_D11
5 4 I2C_0_SCL
GM 1 SR 1 *Project code 0 0
10K_0804_8P4R_5%
Reserved 0 1
2 @ 1 W L_OFF# Echo13
Reserved 1 0
RC126 8.2K_0402_5%
UC1F SKL-U Reserved 1 1
Rev_1.0
LPSS ISH
<44> RTD3_CIO_PW R_EN RTD3_CIO_PW R_EN AN8 P2 VGA_ID

RTD3_USB_PW R_EN AP7 GPP_B15/GSPI0_CS# GPP_D9 P3 RANK_ID
<44> RTD3_USB_PW R_EN GPP_B16/GSPI0_CLK GPP_D10
SOC_GPIOB17 AP8 P4 PROJECT_ID0
GSPI0_MOSI AR7 GPP_B17/GSPI0_MISO GPP_D11 P1 PROJECT_ID1
B17 for GPU_GC6_FB_EN GPP_B18/GSPI0_MOSI GPP_D12
AM5 M4 ISH_I2C_0_SDA T111 TP@
PCIE_SEL AN7 GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA N3 ISH_I2C_0_SCL
<34> PCIE_SEL GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL T112 TP@
SOC_GPIOB21 AP5 I2C for ISH sensor HUB
GSPI1_MOSI AN5 GPP_B21/GSPI1_MISO N1 ISH_I2C_1_SDA
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA T104 TP@
N2 ISH_I2C_1_SCL T103 TP@
W L_OFF# AB1 GPP_D8/ISH_I2C1_SCL
<32> W L_OFF# GPP_C8/UART0_RXD
1 @ 2 PD_PW R_EN_R AB2 AD11 I2C_5_SDA T105 TP@
<41,46> PD_PW R_EN GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA
RC128 0_0201_5% SOC_GPIOC10 W4 AD12 I2C_5_SCL T106 TP@ Unused
C BT_OFF# AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL C
C10 for GC6_EVENT# <32> BT_OFF# GPP_C11/UART0_CTS#
UART_2_CRXD_DTXD AD1 U1 SOC_GPIOD13 T107 TP@
<32> UART_2_CRXD_DTXD GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
UART_2_CTXD_DRXD AD2 U2 SOC_GPIOD14 T108 TP@
<32> UART_2_CTXD_DRXD GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
<41> EC_SMI# EC_SMI# AD3 U3 SOC_GPIOD15 T109 TP@
TBT_CIO_PLUG_EVENT#AD4 GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# U4 SOC_GPIOD16
<44> TBT_CIO_PLUG_EVENT# GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT# T110 TP@
AC1 DGPU_PW R_EN
GPP_C12/UART1_RXD/ISH_UART1_RXD DGPU_PW R_EN <24>
I2C_0_SDA U7 AC2 DGPU_HOLD_RST#
GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD DGPU_HOLD_RST# <22>
Sensor I2C_0_SCL U6 AC3 SOC_GPIOC14 T254 TP@
GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4 SOC_GPIOC15
GPP_C15/UART1_CTS#/ISH_UART1_CTS# T256 TP@
I2C_1_SDA U8
<38> I2C_1_SDA GPP_C18/I2C1_SDA
Touch PAD/Panel I2C_1_SCL U9 AY8 SOC_GPIOA18 T250 TP@
<38> I2C_1_SCL GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 BA8 SOC_GPIOA19 T251 TP@
AH9 GPP_A19/ISH_GP1 BB7 SOC_GPIOA20
GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 T252 TP@
NFC AH10 BA7 SOC_GPIOA21 T253 TP@
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 AY7 SOC_GPIOA22
GPP_A22/ISH_GP4 T255 TP@
AH11 AW7 SOC_GPIOA23 T120 TP@
AH12 GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 AP13 SOC_GPIOA12
Unused GPP_F7/I2C3_SCL Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6 T122 TP@
AF11
AF12 GPP_F8/I2C4_SDA
Unused GPP_F9/I2C4_SCL 6 OF 20
@ SKL-U_BGA1356
B
Strap Pin B
+3VS
RC118 1 @ 2 2.2K_0402_5% GSPI0_MOSI
RC201 1 @ 2 2.2K_0402_5% GSPI1_MOSI
GSPI0_MOSI (Internal Pull Down):
No Reboot
0 = Disable No Reboot mode. --> AAX05 Use
1 = Enable No Reboot Mode. (PCH will disable the TCO

Timer system reboot feature). This function is useful
when running ITP/XDP.
For
GSPI1_MOSI (Internal Pull TO DGPU
Down):
Boot BIOS Strap Bit SOC_GPIOC10 RC204 1 @ 2 0_0402_1% GC6_EVENT# GC6_EVENT# <22>
SOC_GPIOB17 RC195 1 @ 2 0_0402_1% GPU_GC6_FB_EN GPU_GC6_FB_EN <22,25>
A A
0 = SPI Mode --> AAX05 Use
GC6
1 = LPC Mode--> AAP01 Use
2015/01/06
Compal Secret Data
2016/01/06 Title
SKL-U(6/12)GPIO
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2 LA-C901P
5 4 3 2 1
5 4 3 2 1
UC1H SKL-U
Rev_1.0
SSIC / USB3
PCIE / USB3 / SATA
H8
USB3_1_RXN USB3_CRX_DTX_N1 <33>
G8
USB3_1_RXP USB3_CRX_DTX_P1 <33>
<34> PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N1 H13 C13 USB3.0 MB_PORT1(Conn2 + OTG support)
PCIE1_RXN/USB3_5_RXN USB3_1_TXN USB3_CTX_DRX_N1 <33>
<34> PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P1 G13 D13
PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3_CTX_DRX_P1 <33>
CC17 DIS@ 1 2 0.22U_0402_16V7K PCIE_CTX_GRX_N1 B17
<34> PCIE_CTX_C_GRX_N1 PCIE1_TXN/USB3_5_TXN
<34> PCIE_CTX_C_GRX_P1 CC21 DIS@ 1 2 0.22U_0402_16V7K PCIE_CTX_GRX_P1 A17 J6
USB3_CRX_DTX_N2 <33>
PCIE1_TXP/USB3_5_TXP USB3_2_RXN / SSIC_RXN H6
USB3_2_RXP / SSIC_RXP USB3_CRX_DTX_P2 <33>
PCIE_CRX_GTX_N2 G11 B13 USB3.0 MB_PORT2(Conn1 + Charge)
<34> PCIE_CRX_GTX_N2 PCIE2_RXN/USB3_6_RXN USB3_2_TXN / SSIC_TXN USB3_CTX_DRX_N2 <33>
PCIE_CRX_GTX_P2 F11 A13
<34> PCIE_CRX_GTX_P2 PCIE2_RXP/USB3_6_RXP USB3_2_TXP / SSIC_TXP USB3_CTX_DRX_P2 <33>
CC18 DIS@ 1 2 0.22U_0402_16V7K PCIE_CTX_GRX_N2 D16
<34> PCIE_CTX_C_GRX_N2 CC19 DIS@ 1 2 0.22U_0402_16V7K PCIE_CTX_GRX_P2 C16 PCIE2_TXN/USB3_6_TXN J10
<34> PCIE_CTX_C_GRX_P2 PCIE2_TXP/USB3_6_TXP USB3_3_RXN USB3_CRX_DTX_N3 <34>
H10
USB3_3_RXP USB3_CRX_DTX_P3 <34>
DGPU PCIE_CRX_GTX_N3 H16 B15 3D CAMERA / Caldera
D <34> PCIE_CRX_GTX_N3 PCIE3_RXN USB3_3_TXN USB3_CTX_DRX_N3 <34> D
PCIE_CRX_GTX_P3 G16 A15
(x4 Lane) <34> PCIE_CRX_GTX_P3 CC20 DIS@ 1 2 0.22U_0402_16V7K PCIE_CTX_GRX_N3 D17 PCIE3_RXP USB3_3_TXP USB3_CTX_DRX_P3 <34>
<34> PCIE_CTX_C_GRX_N3 PCIE3_TXN
CC22 DIS@ 1 2 0.22U_0402_16V7K PCIE_CTX_GRX_P3 C17 E10
<34> PCIE_CTX_C_GRX_P3 PCIE3_TXP USB3_4_RXN F10
PCIE_CRX_GTX_N4 G15 USB3_4_RXP C15
<34> PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P4 F15 PCIE4_RXN USB3_4_TXN D15
<34> PCIE_CRX_GTX_P4 CC23 DIS@ 1 2 0.22U_0402_16V7K PCIE_CTX_GRX_N4 B19 PCIE4_RXP USB3_4_TXP
<34> PCIE_CTX_C_GRX_N4 PCIE4_TXN
CC24 DIS@ 1 2 0.22U_0402_16V7K PCIE_CTX_GRX_P4 A19 AB9 USB20_N1
<34> PCIE_CTX_C_GRX_P4 PCIE4_TXP USB2N_1 USB20_N1 <33>
AB10 USB20_P1 USB2.0 MB_PORT1 (Conn2)
USB2P_1 USB20_P1 <33>
PCIE_CRX_DTX_N5 F16
<32> PCIE_CRX_DTX_N5 PCIE_CRX_DTX_P5 E16 PCIE5_RXN AD6 USB20_N2
<32> PCIE_CRX_DTX_P5 PCIE5_RXP USB2N_2 USB20_N2 <33>
NGFF WLAN+BT PCIE_CTX_DRX_N5 C19 AD7 USB20_P2 USB2.0 MB_PORT2 (Conn1 + Power Share)
<32> PCIE_CTX_DRX_N5 PCIE5_TXN USB2P_2 USB20_P2 <33>
PCIE_CTX_DRX_P5 D19
**** Swap Port **** <32> PCIE_CTX_DRX_P5 PCIE5_TXP AH3 USB20_N3
Follow Customer design USB2N_3 USB20_N3 <34>
<30> PCIE_CRX_DTX_N6 PCIE_CRX_DTX_N6 G18 AJ3 USB20_P3 NC / Caldera NC port for 3D Camera sku
(Different with TD Team) PCIE6_RXN USB2P_3 USB20_P3 <34>
<30> PCIE_CRX_DTX_P6 PCIE_CRX_DTX_P6 F18
CC25 1 2 0.1U_0402_10V7K PCIE_CTX_DRX_N6 D20 PCIE6_RXP AD9
LAN <30> PCIE_CTX_C_DRX_N6 PCIE6_TXN USB2N_4
CC26 1 2 0.1U_0402_10V7K PCIE_CTX_DRX_P6 C20 AD10 USB2.0 IO_PORT3 / NC NC port for Gaming
<30> PCIE_CTX_C_DRX_P6 PCIE6_TXP USB2P_4
F20 AJ1 USB20_N5
<36> SATA_CRX_DTX_N0 PCIE7_RXN/SATA0_RXN USB2N_5 USB20_N5 <20>
E20 AJ2 USB20_P5 TOUCH SCREEN
<36> SATA_CRX_DTX_P0 PCIE7_RXP/SATA0_RXP USB2P_5 USB20_P5 <20>
HDD B21 USB2
<36> SATA_CTX_DRX_N0 A21 PCIE7_TXN/SATA0_TXN AF6 USB20_N6
<36> SATA_CTX_DRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 USB20_N6 <20>
For selected technology SATA Express AF7 USB20_P6 USB2.0 Camera
please use 100nF for PCIe Gen3. USB2P_6 USB20_P6 <20>
G21 **** Swap Port ****
please use 10nF for SATA. <36> SATA_CRX_DTX_N1 F21 PCIE8_RXN/SATA1A_RXN AH1 USB20_N7 Follow Customer design
<36> SATA_CRX_DTX_P1 PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_N7 <37> (Different with TD Team)
D21 AH2 USB20_P7 ELC
<36> SATA_CTX_DRX_N1 PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 <37>
C21
<36> SATA_CTX_DRX_P1 PCIE8_TXP/SATA1A_TXP AF8 USB20_N8
USB2N_8 USB20_N8 <32>
PCIE_CRX_DTX_N9 E22 AF9 USB20_P8 NGFF WLAN+BT
<44> PCIE_CRX_DTX_N9 PCIE9_RXN USB2P_8 USB20_P8 <32>
PCIE_CRX_DTX_P9 E23
<44> PCIE_CRX_DTX_P9 PCIE_CTX_DRX_N9 B23 PCIE9_RXP AG1 USB20_N9
<44> PCIE_CTX_DRX_N9 PCIE9_TXN USB2N_9 T151 TP@
PCIE_CTX_DRX_P9 A23 AG2 USB20_P9 T150 TP@
<44> PCIE_CTX_DRX_P9 PCIE9_TXP USB2P_9
ThunderBolt
PCIE_CRX_DTX_N10 F25 AH7 USB20_N10 T141 TP@
C <44> PCIE_CRX_DTX_N10 PCIE_CRX_DTX_P10 E25 PCIE10_RXN USB2N_10 AH8 USB20_P10 C
<44> PCIE_CRX_DTX_P10 PCIE10_RXP USB2P_10 T143 TP@
PCIE_CTX_DRX_N10 D23
<44> PCIE_CTX_DRX_N10 PCIE_CTX_DRX_P10 C23 PCIE10_TXN AB6 USB2_COMP RC119 1 2 113_0402_1%
<44> PCIE_CTX_DRX_P10 PCIE10_TXP USB2_COMP AG3 USB2_ID RC121 1 2 1K_0402_5%
RC120 1 2 100_0402_1% PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE RC125 1 2 1K_0402_5%
PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE
PCIE_RCOMPP A9 USB_OC0#
GPP_E9/USB2_OC0# USB_OC0# <33>
XDP_PRDY# D56 C9 USB_OC1#
<6> XDP_PRDY# PROC_PRDY# GPP_E10/USB2_OC1# USB_OC1# <33>
XDP_PREQ# D61 D9 USB_OC2# T148 TP@
<6> XDP_PREQ# BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC3#
GPP_A7/PIRQA# GPP_E12/USB2_OC3# T238 TP@
<36> PCIE_CRX_DTX_N11
E28 J1 TBT_FORCE_PWR TBT_FORCE_PWR <44>
E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2 DEVSLP1
<36> PCIE_CRX_DTX_P11 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 DEVSLP1 <36> SATA1
D24 J3 DEVSLP2 SATA2
<36> PCIE_CTX_DRX_N11 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 DEVSLP2 <36>
For selected technology SATA Express C24
please use 220nF for PCIe Gen3. <36> PCIE_CTX_DRX_P11 PCIE11_TXP/SATA1B_TXP +3VS +3V_PRIM
<36> PCIE_CRX_DTX_N12
E30 H2 SATA_GP0 SATA_GP0 <36> IFDET_SATAEX0(Reserve)
please use 10nF for SATA. F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3 SATA_GP1
<36> PCIE_CRX_DTX_P12 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 SATA_GP1 <36> IFDET_SATAEX1
A25 G4 SATA_GP2 IFDET_SATAEX2
<36> PCIE_CTX_DRX_N12 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 SATA_GP2 <36>
B25
<36> PCIE_CTX_DRX_P12 PCIE12_TXP/SATA2_TXP H1 SOC_SATALED# SOC_SATALED# <36,38> SOC_SATALED# 1 RC211 2
8 OF 20 GPP_E8/SATALED#
Follow 545659_SKL_PCH_LP_EDS_Rev1_0 10K_0402_5%
@ SKL-U_BGA1356 Default
RPC13
DEVSLP1 1 8
SATA_GP0 1 IFDET_SATAEX0(HDD) 0=SATA NA DEVSLP2 2 7
USB_OC0# 3 6
When PCIE8/SATA1A is used USB_OC1# 4 5
as SATA Port 1 (ODD), then SATA_GP1 1 IFDET_SATAEX1 0=SATA 1=PCI-E
10K_0804_8P4R_5%
PCIE11/SATA1B (M.2 SSD)
cannot be used as SATA SATA_GP2 1 IFDET_SATAEX2 0=SATA 1=PCI-E
Port 1.
B B
Follow 545659_SKL_PCH_LP_EDS_Rev1_0
A A

SKL-U(7/12)PCIE,USB,SATA
1.0
5 4 3 2 1
5 4 3 2 1
For Power consumption Measurement +1.35V_VDDQ +1.35V_VDDQ_CPU +1.0VS_VCCIO

UC1N SKL-U
Rev_1.0
CPU POWER 3 OF 4
+1.0V_PRIM TO +1.0V_VCCSTU RC145 1 @ 2 0_0805_1% AU23
AU28 VDDQ_AU23 VCCIO
AK28
AK30
+5VALW +1.0V_PRIM +1.0V_VCCSTU AU35 VDDQ_AU28 VCCIO AL30
AU42 VDDQ_AU35 VCCIO AL42
BB23 VDDQ_AU42 VCCIO AM28
For Power consumption BB32 VDDQ_BB23 VCCIO AM30
VDDQ_BB32 VCCIO
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 Measurement BB41 AM42
VDDQ_BB41 VCCIO
CC98
CC97
0.1U_0402_25V6
1 BB47
VDDQ_BB47
CC96
D I (Max) : 0.04 A(+1.0V_VCCSTU) BB51 AK23 +VCC_SA D
@ VDDQ_BB51 VCCSA AK25
2 2 RON(Max) : 25 mohm VCCSA G23
V drop : 0.001 V 2 AM40 VCCSA G25
+1.35V_VDDQC VDDQC VCCSA G27
UC5 A18 VCCSA G28
+1.0V_VCCST VCCST VCCSA
1 14 J22
RC142 1 @ 2 0_0402_1% 2 VIN1 VOUT1 13 A22 VCCSA J23
VIN1 VOUT1
Follow 543977_SKL_PDDG_Rev0_91 +1.0VS_VCCSTG VCCSTG_A22 VCCSA
<13,41,54> SYSON J27
CC95 10PF ->22us(Spec:<= 65us) VCCSA
RC144 1 @ 2 0_0402_5% EN_1.0V_VCCSTU 3 12 1 2 +1.35V_VCCSFR_OC AL23 K23
<6,10,37,41,54> PM_SLP_S4# ON1 CT1 CC95 VCCPLL_OC VCCSA K25
RC168 1 @ 2 0_0402_1% 4 11 10P_0402_50V8J K20 VCCSA K27
<41,42,44> SUSP# VBIAS GND +1.0V_VCCSFR VCCPLL_K20 VCCSA
K21 K28
RC194 1 @ 2 0_0402_5% EN_1.8VS 5 10 1 2 VCCPLL_K21 VCCSA K30
<6,10,37,41> PM_SLP_S3# ON2 CT2 CC94 VCCSA
6 9 1000P_0402_50V7K AM23 VCCIO_SENSE T124 TP@
+1.8V_PRIM 7 VIN2 VOUT2 8 VCCIO_SENSE AM22 VSSIO_SENSE
VIN2 VOUT2 VSSIO_SENSE T125 TP@
+1.8VS +1.0V_VCCSTU +1.0V_VCCST
15 H21 VSA_SEN-
GPAD VSSSA_SENSE VSA_SEN- <58>
H20 VSA_SEN+
VCCSA_SENSE VSA_SEN+ <58>
EM5209VF_DFN14_2X3 1 @ 2 14 OF 20
1U_0402_6.3V6K
1 1 RC140 0_0402_1%
CC99
@ SKL-U_BGA1356
CC100
I (Max) : 0.536 A(+1.8VS) PSC Side
0.1U_0402_25V6
1U_0402_6.3V6K
@ RON(Max) : 25 mohm 1
For Power consumption 2 2
V drop : 0.013 V
CC48
Measurement
2 +5VALW +1.35V_VDDQ_CPU +1.35V_VDDQ_CPU +1.35V_VCCSFR_OC

C +1.8V_PRIM TO +1.8VS C
RC141
1 2
Imax : 2.77 A
1U_0201_6.3V6M
1 @ 0_0402_5%
CC101
UC10
+1.0V_VCCSFR 1
2 2 VIN1
+1.0V_PRIM TO +1.0VS_VCCSTG / +1.0VS_VCCIO 1 2 0_0402_1% 7
VIN2
6
RC143 @ BSC Side
VIN thermal VOUT
3
+5VALW VBIAS
1U_0402_6.3V6K
0.1U_0201_10V6K
+1.0V_PRIM PSC Side 1
I (Max) : 3 A(+1.0VS_VCCIO) 4 5 1
<13,41,54> SYSON ON GND
CC55
CC49
RON(Max) : 6.2 mohm +1.0VS_VCCSTG
Imax : 0.04 A
V drop : 0.019 V 2
0.1U_0402_25V6
1U_0402_6.3V6K
1 1 @ TPS22961DNYR_W SON8
2
CC88
CC117
RC188 1 @ 2 0_0402_1% CC89 1 2 0.1U_0402_25V6

UC6
+3V_PRIM 1 +1.0VS_VCCIO
CC92 2@ 2 2 VIN1
1 2 VIN2 MP@ @
7 6 +1.0VS_VCCSTG_IO RC189 1 2 0_0805_5% CC90 1 2 0.1U_0402_25V6 +1.0VS_VCCSTG
0.1U_0201_10V6K VIN thermal VOUT
5
UC12 3 Imax : 3 A BSC Side

PM_SLP_S3# 1 VBIAS
P
B 4 EN_VCCSTG_IO 4 5
O ON GND
1U_0201_6.3V6M
SUSP# 2 1
A
G
B B
CC56
TC7SH08FU_SSOP5~D TPS22961DNYR_W SON8
3
2
1 2
RC187 @ 0_0402_5%
RC208 Follow 544669_SKL_U__DDR3L_RVP7_Schematic_Rev1.0
For meet tPLT18 power down sequence. RC208 Follow 544669_SKL_U__DDR3L_RVP7_Schematic_Rev0_53
tPLT18 : 1us (Max)
+1.35V_VDDQ_CPU +1.35V_VDDQC +1.35V_VDDQ_CPU
BSC Side PSC Side PSC Side BSC Side

+1.0VS_VCCIO RC208 1 @ 2 0_0603_1%
BSC Side PSC Side 1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0201_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1
CC47
CC93
CC37
CC38
CC39
CC40
CC41
CC42
CC43
CC44
CC45
CC46
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2
CC27
CC28
CC29
CC30
CC31
CC32
CC33
CC34
CC35
CC36
2 2 2 2 2 2 2 2 2 2
+1.35V_VDDQ_CPU : 10UF/6.3V/0603 *6
A CC47 Follow 543016_SKL_U_Y_PDG_0_9 1UF/6.3V/0402 * 4 A
CC93 Follow 543016_SKL UY PDG_rev1_3
2015/01/06
Compal Secret Data
2016/01/06 Title
SKL-U(8/12)Power
5 4 3 2 1
5 4 3 2 1
+1.0V_PRIM +1.0V_APLL
+1.0V_PRIM
Follow 543016_SKL_U_Y_PDG_1_0 +1.0V_MPHYPLL +1.0V_AMPHYPLL UC1O SKL-U
Rev_1.0
RC148 1 @ 2 0_0603_1% CPU POWER 4 OF 4
22U_0603_6.3V6M
22U_0603_6.3V6M
AB19
RC149 1 @ 2 0_0603_1% AB20 VCCPRIM_1P0 AK15
1 1 VCCPRIM_1P0 VCCPGPPA +3V_1.8V_PGPPA
CC123
CC124
1U_0402_6.3V6K
22U_0603_6.3V6M
22U_0603_6.3V6M
P18 AG15
VCCPRIM_1P0 VCCPGPPB +3V_PGPPBCE
1 1 1 Y16
VCCPGPPC
CC61
CC118
CC119
@ @ +3V_1.8V_PGPPA AF18 Y15
2 2 +1.0V_PRIM VCCPRIM_CORE VCCPGPPD +3V_1.8V_PGPPD
AF19 T16
VCCPRIM_CORE VCCPGPPE +3V_PGPPBCE
@ @ @ V20 AF16
2 2 2 VCCPRIM_CORE VCCPGPPF +1.8V_PRIM
V21 AD15
VCCPRIM_CORE VCCPGPPG +3V_PGPPBCE For SD CARD
AL1 V19
+1.0VO_DSW DCPDSW_1P0 VCCPRIM_3P3_V19 +3V_PRIM
D K17 T1 D
+1.0V_MPHYAON VCCMPHYAON_1P0 VCCPRIM_1P0_T1 +1.0V_DTS
+3V_PRIM L1
+1.0V_CLK5_F24NS VCCMPHYAON_1P0 AA1
VCCATS_1P8 +1.8V_PRIM
Follow 543016_SKL_U_Y_PDG_1_0 N15
+1.0V_MPHYGT VCCMPHYGT_1P0_N15
+1.0V_APLLEBB N16 AK17
VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3 +3V_PRIM_RTC
RC152 1 @ 2 0_0603_1% N17
RC197 1 @ 2 0_0402_1% P15 VCCMPHYGT_1P0_N17 AK19
VCCMPHYGT_1P0_P15 VCCRTC_AK19 +3VL_RTC
22U_0603_6.3V6M
22U_0603_6.3V6M
RC156 1 @ 2 0_0402_1% P16 BB14
VCCMPHYGT_1P0_P16 VCCRTC_BB14
1 1
CC129
CC130
K15 BB10 CC71 1 2 0.1U_0402_10V7K
+1.0V_AMPHYPLL VCCAMPHYPLL_1P0 DCPRTC
1U_0201_6.3V6M
1 L15
@ @ VCCAMPHYPLL_1P0 A14
2 2 VCCCLK1 +1.0V_CLK6_24TBT
CC68
+3V_SPI V15
+1.0V_APLL VCCAPLL_1P0 K19
2 AB17 VCCCLK2
+1.0V_PRIM VCCPRIM_1P0_AB17
Y18 L21
VCCPRIM_1P0_Y18 VCCCLK3 +1.0V_APLL
RC154 1 @ 2 0_0402_1%
AD17 N20
+3VALW_DSW VCCDSW_3P3_AD17 VCCCLK4 +1.0V_CLK4_F100OC
AD18
+1.0V_CLK4_F100OC AJ17 VCCDSW_3P3_AD18 L19
RC163 close to UC1 pinAJ19 VCCDSW_3P3_AJ17 VCCCLK5 +1.0V_CLK5_F24NS
Follow 543016_SKL_U_Y_PDG_1_0 +3V_PGPPBCE
+1.0V_SRAM 1 RF@ 2 AJ19 A10
+3V_PRIM VCCHDA VCCCLK6 +1.0V_CLK6_24TBT
RC190 1 @ 2 0_0603_1% RC163 0_0402_5%
AJ16 AN11 PRIMCORE_VID0 T130 TP@
+3V_SPI VCCSPI GPP_B0/CORE_VID0
22U_0603_6.3V6M
22U_0603_6.3V6M
RC161 1 @ 2 0_0402_1% RC176 1 @ 2 0_0603_1% AN13 PRIMCORE_VID1 T131 TP@

AF20 GPP_B1/CORE_VID1
1 1 +1.0V_SRAM VCCSRAM_1P0
CC127
CC128
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 AF21
T19 VCCSRAM_1P0
VCCSRAM_1P0
CC102
CC73
CC74
CC122
@ @ @ @ @ T20
2 2 @ VCCSRAM_1P0
2 2 2 2 AJ21
+3V_PRIM VCCPRIM_3P3_AJ21
AK20
+1.0V_PRIM VCCPRIM_1P0_AK20
N18
+1.0V_APLLEBB VCCAPLLEBB_1P0 15 OF 20
+1.0V_PRIM +1.0V_MPHYGT
@ SKL-U_BGA1356
RC209 1 @ 2 0_0603_1%
C C
1U_0201_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1 1 1
RTC Battery
1U_0402_6.3V6K
CC81
CC82
Imax : 2.57A 1
CC80
CC76
MAX. 8000mil
@ 2 2 2 CC79.CC84 Close UC1.AK19.
2 @ @ Per 543016_SKL_U_Y_PDG_0_9
W=20mils DC1
VCCRTC does not exceed 3.2 V From PDG
+3V_1.8V_PGPPD +1.8V_PRIM 1 2 2
+RTCBATT
Power Rail Voltage RC192 1K_0402_5% W=20mils
+1.0V_MPHYAON 1
+3VL_RTC
1U_0201_6.3V6M
0.1U_0201_10V6K
RC172 1 @ 2 0_0402_1% RC206 1 @ 2 0_0402_5% +CHGRTC 3.383V(MAX) 3
+3VLP
1 1
1U_0402_6.3V6K
CC84
CC79
RC175 1 @ 2 0_0402_1% 1 W=20mils BAT54C-7-F_SOT23-3
BAT54C(VF) 240 mV
CC103
2 2
1U_0402_6.3V6K
1
2 +3VL_RTC 3.143V
+3V_PRIM +1.0V_PRIM
CC87
+1.0VO_DSW +1.8V_PRIM
2 Result : Pass
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 CC85 1 1 1
+3VALW TO +3V_PRIM
CC72
CC67
CC91
@ @
+1.0V_CLK6_24TBT For NON-DS3
2 2 2 2 +3VALW +3V_PRIM
RC153 1 @ 2 0_0805_5%
RC169 1 @ 2 0_0603_1% +3VALW I (Max) : 0.46 A(+3V_PRIM)
RDS(Typ) : 65 mohm
22U_0603_6.3V6M
22U_0603_6.3V6M
V drop : 0.03 V
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1
CC125
CC126
+3V_PRIMJP 1 2
CC86
CC75
RC159 0_0805_5%
1U_0402_6.3V6K
4.7U_0603_6.3V6K
@ @ @ @ Note : Stuff UC8 RC191,RC159,CC50,PR809 for meet 1 For DS3 1
2 2 2 2
CC50
CC51
+3V_PRIM_RTC energy star power consumption under AC S5 mode UC8
B B
5 1
2 IN OUT 2
2
RC171 1 @ 2 0_0402_1% GND
0.1U_0201_10V6K
4 3
EN OC
1U_0402_6.3V6K
1 1 RC1911 @ 2 0_0402_1%
<41,56> PCH_PWR_EN
CC78
+1.0V_DTS SY6288C20AAC_SOT23-5 +3VALW

CC77
RC1741 @ 2 0_0402_5% EN_3V_PRIM

<10,41> SLP_SUS# 3V_PRIM_OC 1 @ 2
2 2 RC166 10K_0402_5%
1
RC162 1 @ 2 0_0402_1%
RC167
100K_0402_5%
2
+1.0V_PRIM +3V_PRIM +1.8V_PRIM
+1.0V_PRIM TO +1.0V_MPHYPLL
+5VALW +1.0V_PRIM
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
I (Max) : 2.766 A(+1.0V_MPHYPLL)

1 1 1 1 1 1 RON(Max) : 6.2 mohm
CC111
CC112
CC113
CC114
CC116
CC115
V drop : 0.017 V
0.1U_0402_25V6
1U_0402_6.3V6K
1 1
CC52
CC59
@ @ @ @ @ @
2 2 2 2 2 2 @ @ UC4
1 +1.0V_MPHYPLL
2 2 2 VIN1
VIN2
For Premium
7 6 +1.0V_MPHYJP 1 @ 2
VIN thermal VOUT RC164 0_0805_5%
3
VBIAS
RC210 1 @ 2 0_0402_1% EXT_PWR_GATE#_R 4 5 Imax : 2.766A
<10> EXT_PWR_GATE# ON GND +1.0V_PRIM For Volume 1
CC58
1
TPS22961DNYR_WSON8 MP@
A 1 2 0.1U_0402_25V6 A
RC170 @ @
RC160 0_0805_5% 2
100K_0402_5%
@
2
2015/01/06
Compal Secret Data
2016/01/06 Title
SKL-U(9/12)Power
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
5 4 3 2 1
5 4 3 2 1
+VCC_GT +VCC_GT
+VCC_CORE +VCC_CORE UC1M SKL-U
Rev_1.0
UC1L SKL-U CPU POWER 2 OF 4
CPU POWER 1 OF 4
Rev_1.0 N70
A48 VCCGT N71
A30 G32 A53 VCCGT VCCGT R63
A34 VCC_A30 VCC_G32 G33 A58 VCCGT VCCGT R64
D D
AK33 VCC_A44 VCC_G37 G38 AA63 VCCGT VCCGT R67
AK35 VCC_AK33 VCC_G38 G40 AA64 VCCGT VCCGT R68
AK37 VCC_AK35 VCC_G40 G42 AA66 VCCGT VCCGT R69
AK38 VCC_AK37 VCC_G42 J30 AA67 VCCGT VCCGT R70
AK40 VCC_AK38 VCC_J30 J33 AA69 VCCGT VCCGT R71
AL33 VCC_AK40 VCC_J33 J37 AA70 VCCGT VCCGT T62
AL37 VCC_AL33 VCC_J37 J40 AA71 VCCGT VCCGT U65
AL40 VCC_AL37 VCC_J40 K33 AC64 VCCGT VCCGT U68
AM32 VCC_AL40 VCC_K33 K35 AC65 VCCGT VCCGT U71
AM33 VCC_AM32 VCC_K35 K37 AC66 VCCGT VCCGT W63
G30 VCC_AM38 VCC_K42 K43 AC70 VCCGT VCCGT W67
VCC_G30 VCC_K43
Trace Length < 25 mils VCCGT VCCGT
AC71 W68
K32 E32 J43 VCCGT VCCGT W69
T123 TP@ RSVD VCC_SENSE VCCSENSE <58> VCCGT VCCGT
E33 J45 W70
VSS_SENSE VSSSENSE <58> VCCGT VCCGT
T121 TP@ AK32 +1.0VS_VCCSTG J46 W71
RSVD B63 SOC_SVID_ALERT# J48 VCCGT VCCGT Y62
AB62 VIDALERT# A63 SOC_SVID_CLK J50 VCCGT VCCGT +VCC_GTX
+1.0VS_VCCOPC VCCOPC_AB62 VIDSCK SOC_SVID_CLK <58> VCCGT
P62 D64 SOC_SVID_DAT J52
V62 VCCOPC_P62 VIDSOUT J53 VCCGT AK42
For CPU2+3e SKU VCCOPC_V62 VCCGT VCCGTX_AK42
G20 J55 AK43
H63 VCCSTG_G20 J56 VCCGT VCCGTX_AK43 AK45
+1.8V_VCCOPC VCC_OPC_1P8_H63 VCCGT VCCGTX_AK45
J58 AK46
G61 J60 VCCGT VCCGTX_AK46 AK48
VCC_OPC_1P8_G61 K48 VCCGT VCCGTX_AK48 AK50
C VCCOPC_SENSE AC63 K50 VCCGT VCCGTX_AK50 AK52 C
T132 TP@ VCCOPC_SENSE VCCGT VCCGTX_AK52
T133 TP@ VSSOPC_SENSE AE63 K52 AK53
VSSOPC_SENSE K53 VCCGT VCCGTX_AK53 AK55
AE62 K55 VCCGT VCCGTX_AK55 AK56
+1.0VS_VCCEOPIO VCCEOPIO VCCGT VCCGTX_AK56
AG62 K56 AK58
VCCEOPIO K58 VCCGT VCCGTX_AK58 AK60
VCCEOPIO_SENSE AL63 K60 VCCGT VCCGTX_AK60 AK70
T137 TP@ VCCEOPIO_SENSE VCCGT VCCGTX_AK70
T139 TP@ VSSEOPIO_SENSE AJ62 L62 AL43
VSSEOPIO_SENSE 12 OF 20 L63 VCCGT VCCGTX_AL43 AL46
L64 VCCGT VCCGTX_AL46 AL50
For CPU2+3e SKU
@ SKL-U_BGA1356 L65 VCCGT VCCGTX_AL50 AL53
L68 VCCGT VCCGTX_AL60 AM48
L69 VCCGT VCCGTX_AM48 AM50
M62 VCCGT VCCGTX_AM53 AM56
N63 VCCGT VCCGTX_AM56 AM58
N64 VCCGT VCCGTX_AM58 AU58
N66 VCCGT VCCGTX_AU58 AU63
N67 VCCGT VCCGTX_AU63 BB57
N69 VCCGT VCCGTX_BB57 BB66
VCCGT VCCGTX_BB66
VCCGT_SENSE J70 AK62 VCCGTX_SENSE T155 TP@
<58> VCCGT_SENSE VCCGT_SENSE VCCGTX_SENSE
VSSGT_SENSE J69 AL61 VSSGTX_SENSE T219 TP@
<58> VSSGT_SENSE VSSGT_SENSE 13 OF 20VSSGTX_SENSE
Trace Length < 25 mils @ SKL-U_BGA1356

B B
SVID ALERT
+1.0V_VCCST
Place the PU
resistors close to CPU
1
RC179 For 2+3e Solution

56_0402_5%
2
+1.0VS_VCCEOPIO +1.0VS_VCCOPC
BSC Side BSC Side
SOC_SVID_ALERT# 1 2 (To VR)
SOC_SVID_ALERT#_R <58>
RC180 220_0402_5%
1 1
CC66 CC62
10U_0603_6.3V6M
1U_0402_6.3V6K
2 2
+1.0V_VCCST
23E@
23E@
SVID DATA Place the PU
resistors close to CPU
1
RC181
A 100_0402_1% A
2
SOC_SVID_DAT
SOC_SVID_DAT <58> (To VR) Security Classification
2015/01/06
Compal Secret Data
2016/01/06 Title
SKL-U(10/12)Power,SVID
5 4 3 2 1
5 4 3 2 1
D D
UC1P SKL-U UC1Q SKL-U
Rev_1.0 Rev_1.0 UC1R SKL-U
GND 1 OF 3 GND 2 OF 3 Rev_1.0
GND 3 OF 3
A5 AL65 AT63 BA49 F8 L18
A67 VSS VSS AL66 AT68 VSS VSS BA53 G10 VSS VSS L2
A70 VSS VSS AM13 AT71 VSS VSS BA57 G22 VSS VSS L20
AA2 VSS VSS AM21 AU10 VSS VSS BA6 G43 VSS VSS L4
AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8
AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10
AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13
AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19
AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21
AD13 VSS VSS AM68 AV71 VSS VSS BB43 G63 VSS VSS P17
AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
C AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10 C
AF1 VSS VSS AN42 AW36 VSS VSS D18 J8 VSS VSS U63
AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17
AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
AH64 VSS VSS AR15 AY66 VSS VSS E11
AH67 VSS VSS AR16 B10 VSS VSS E15 18 OF 20
AJ15 VSS VSS AR20 B14 VSS VSS E18
AJ18 VSS VSS AR23 B18 VSS VSS E21 SKL-U_BGA1356
AK11 VSS VSS AR42 B34 VSS VSS E53
B AK27 VSS VSS AR5 B58 VSS VSS F1 B
AK63 VSS VSS AR50 B62 VSS VSS F13
AK8 VSS VSS AR55 BA1 VSS VSS F23
AL2 VSS VSS AR58 BA10 VSS VSS F27
AL35 VSS VSS AT2 BA2 VSS VSS F33
AL52 VSS VSS AT4 F68 VSS VSS F40
AL58 VSS VSS AT56 VSS VSS BA41
AL64 VSS VSS AT58 VSS
VSS VSS
16 OF 20 17 OF 20
@ SKL-U_BGA1356 @ SKL-U_BGA1356
A A
2015/01/06
Compal Secret Data
2016/01/06 Title
SKL-U(11/12)GND
5 4 3 2 1
5 4 3 2 1
1 : Disabled; No Physical Display Port

CFG4 attached to Embedded Display Port
0 : Enabled; An external Display Port device is

connected to the Embedded Display Port
D D
UC1S SKL-U
Rev_1.0
RESERVED SIGNALS-1
<6> CFG0 CFG0 E68 BB68 T156 TP@

CFG1 B67 CFG[0] RSVD_TP_BB68 BB69
<6> CFG1 CFG[1] RSVD_TP_BB69 T157 TP@
<6> CFG2 CFG2 D65
CFG3 D67 CFG[2] AK13
<6> CFG3 CFG[3] RSVD_TP_AK13 T158 TP@
<6> CFG4 CFG4 E70 AK12 T159 TP@
CFG5 C68 CFG[4] RSVD_TP_AK12
<6> CFG5 CFG[5]
<6> CFG6 CFG6 D68 BB2
CFG7 C67 CFG[6] RSVD_BB2 BA3
<6> CFG7 CFG[7] RSVD_BA3
<6> CFG8 CFG8 F71
CFG9 G69 CFG[8]
CFG Signals <6> CFG9 CFG[9]
<6> CFG10 CFG10 F70 AU5 T162 TP@
(For Strap & XDP) CFG11 G68 CFG[10] TP5 AT5
<6> CFG11 CFG[11] TP6 T163 TP@
<6> CFG12 CFG12 H70
CFG13 G71 CFG[12]
<6> CFG13 CFG[13]
<6> CFG14 CFG14 H69 D5
CFG15 G70 CFG[14] RSVD_D5 D4
<6> CFG15 CFG[15] RSVD_D4 B2
CFG16 E63 RSVD_B2 C2
<6> CFG16 CFG[16] RSVD_C2
<6> CFG17 CFG17 F63
CFG[17] B3
CFG18 E66 RSVD_B3 A3
<6> CFG18 CFG[18] RSVD_A3
<6> CFG19 CFG19 F66
CFG[19] AW1
49.9_0402_1% 2 1 RC185 CFG_RCOMP E60 RSVD_AW1
C CFG_RCOMP E1 C
XDP_ITP_PMODE E8 RSVD_E1 E2
<6> XDP_ITP_PMODE ITP_PMODE RSVD_E2
AY2 BA4
AY1 RSVD_AY2 RSVD_BA4 BB4
RSVD_AY1 RSVD_BB4
D1 A4
D3 RSVD_D1 RSVD_A4 C4
RSVD_D3 RSVD_C4
K46 BB5 T199 TP@
K45 RSVD_K46 TP4
RSVD_K45 A69
AL25 RSVD_A69 B69
AL27 RSVD_AL25 RSVD_B69
RSVD_AL27 AY3 RC182 1 @ 2 0_0402_1%
C71 RSVD_AY3
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70
F60 RSVD_C70
RSVD_F60 C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54
BA70 AY4
T213 TP@
BA68 RSVD_TP_BA70 TP1 BB3
T214 TP@
T216 TP@
For 2+3e Solution
T215 TP@ RSVD_TP_BA68 TP2
J71 AY71 RC183 1 @ 2 0_0402_1%
J68 RSVD_J71 VSS_AY71 AR56 PM_ZVM# PM_ZVM#
RSVD_J68 ZVM# T225 TP@
Zero Voltage Mode: Control Signal to OPC
F65 AW71
B T220 TP@
G65 VSS_F65 RSVD_TP AW70
T221 TP@
+1.0V_VCCST
VR, when low OPC VR output is 0V. B
T222 TP@ VSS_G65 RSVD_TP T223 TP@
F61 AP56 PM_MSM#
E61 RSVD_F61 MSM# C64 SKL_CNL#
T230 TP@
RC184 1 @ 2 100K_0402_5%
PM_MSM#
RSVD_E61 PROC_SELECT# Minimum Speed Mode: Control signal to
19 OF 20
Follow 546765_2014WW48_Skylake_MOW_Rev_1_0
VccEOPIO VR (connected only in 2 VR
SKL-U_BGA1356 solution for OPC).
Stuff 100k(RC184) for Cannonlake.
Un-stuff 100k(RC184) for Skylake
UC1T SKL-U
Rev_1.0
SPARE
PROC_SELECT#
AW69
RSVD_AW69 RSVD_F6
F6 Processor Select: This pin is for
AW68 E3
AU56 RSVD_AW68 RSVD_E3 C11 compatibility with future platforms. It should
AW48 RSVD_AU56 RSVD_C11 B11 NC with Skylake
C7 RSVD_AW48 RSVD_B11 A11
U12 RSVD_C7 RSVD_A11 D12
U11 RSVD_U12 RSVD_D12 C12
H11 RSVD_U11 RSVD_C12 F52
RSVD_H11 RSVD_F52
20 OF 20
A
SKL-U_BGA1356 A
2015/01/06
Compal Secret Data
2016/01/06 Title
SKL-U(12/12)RSVD
5 4 3 2 1
A B C D E
<7>
<7>
DDR_A_DQS#[0..7]
DDR_A_D[0..63]
+0.675V_DDRA_VREFDQ
10mils JDIMM1
Reverse Type
D/DQ Signals link to CPU 1 2
3 VREF_DQ VSS 4 DDR_A_D24
<7> DDR_A_DQS[0..7] VSS DQ4 2-3A to 1 DIMMs/channel
2.2U_0402_6.3V6M
0.1U_0402_25V6K
DDR_A_D29 5 6 DDR_A_D25
DDR_A_D28 7 DQ0 DQ5 8
1 1 DQ1 VSS
CD1
CD2
9 10 DDR_A_DQS#3 +1.35V_VDDQ
<7> DDR_A_MA[0..15] 11 VSS DQS0# 12 DDR_A_DQS3
DDR_A_BS0 13 DM0 DQS0 14
<7> DDR_A_BS0 DDR_A_BS1 2 2 DDR_A_D30 15 VSS VSS 16 DDR_A_D26
<7> DDR_A_BS1 DQ2 DQ6
1
DDR_A_BS2 CMD Signals from CPU DDR_A_D31 17 18 DDR_A_D27
<7> DDR_A_BS2 19 DQ3 DQ7 20
DDR_A_WE# RD1
<7> DDR_A_WE# 21 VSS VSS 22
DDR_A_CAS# DDR_A_D8 DDR_A_D12 470_0402_5%
1 <7> DDR_A_CAS# 23 DQ8 DQ12 24 1
DDR_A_RAS# DDR_A_D9 DDR_A_D13
<7> DDR_A_RAS# 25 DQ9 DQ13 26
2
DDR_A_DQS#1 27 VSS VSS 28
DDR_A_CLK0 DDR_A_DQS1 29 DQS1# DM1 30 DDR_DRAMRST#
<7> DDR_A_CLK0 DDR_A_CLK#0 Clock Signals from CPU 31 DQS1 RESET# 32 DDR_DRAMRST# <7,19> From CPU to CHB
<7> DDR_A_CLK#0 VSS VSS
0.1U_0402_25V6K
DDR_A_CLK1 DDR_A_D11 33 34 DDR_A_D14
<7> DDR_A_CLK1 DDR_A_CLK#1 DDR_A_D10 35 DQ10 DQ14 36 DDR_A_D15 @1
<7> DDR_A_CLK#1 DQ11 DQ15
CD3
37 38
DDR_A_D50 39 VSS VSS 40 DDR_A_D52
DDR_A_CKE0 DDR_A_D51 41 DQ16 DQ20 42 DDR_A_D53
<7> DDR_A_CKE0 DQ17 DQ21
CAD NOTE
DDR_A_CKE1 CTL Signals from CPU 43 44 2
<7> DDR_A_CKE1 VSS VSS PLACE THE CAP NEAR TO
DDR_A_CS#0 DDR_A_DQS#6 45 46
<7> DDR_A_CS#0 DDR_A_CS#1 DDR_A_DQS6 47 DQS2# DM2 48 DIMM RESET PIN
<7> DDR_A_CS#1 49 DQS2 VSS 50 DDR_A_D54
DDR_A_D49 51 VSS DQ22 52 DDR_A_D55
SOC_SMBDATA SMBUS Signals link to CPU DDR_A_D48 53 DQ18 DQ23 54
<8,19,36> SOC_SMBDATA SOC_SMBCLK 55 DQ19 VSS 56 DDR_A_D40
<8,19,36> SOC_SMBCLK DDR_A_D45 57 VSS DQ28 58 DDR_A_D41
DDR_A_D44 59 DQ24 DQ29 60
DDR_A_ODT0 61 DQ25 VSS 62 DDR_A_DQS#5
<7> DDR_A_ODT0 63 VSS DQS3# 64
DDR_A_ODT1 From SOC ODT Signals to CH A DDR_A_DQS5
<7> DDR_A_ODT1 65 DM3 DQS3 66
M_THERMAL# DDR_A_D43 69 DQ26 DQ30 70 DDR_A_D46
<19,41> M_THERMAL# DQ27 DQ31
Thermal link to EC 71 72
+1.35V_VDDQ VSS VSS +1.35V_VDDQ
Note:
Layout Note: DDR_A_CKE0 73 74 DDR_A_CKE1
Check voltage tolerance of 75 CKE0 CKE1 76
Place near JDIMM1 VREF_DQ at the DIMM socket 77 VDD VDD 78 DDR_A_MA15
DDR_A_BS2 79 NC A15 80 DDR_A_MA14
81 BA2 A14 82
2 DDR_A_MA12 83 VDD VDD 84 DDR_A_MA11 2
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
+1.35V_VDDQ DDR_A_MA8 89 VDD VDD 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD VDD 96 DDR_A_MA2
A3 A2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
DDR_A_MA1 97 98 DDR_A_MA0
99 A1 A0 100
1 1 1 1 1 1 VDD VDD
@ @ @ @ DDR_A_CLK0 101 102 DDR_A_CLK1
CK0 CK1
CD4
CD5
CD6
CD7
CD8
CD9
DDR_A_CLK#0 103 104 DDR_A_CLK#1

105 CK0# CK1# 106
2 2 2 2 2 2 DDR_A_MA10 107 VDD VDD 108 DDR_A_BS1
DDR_A_BS0 109 A10/AP BA1 110 DDR_A_RAS#
111 BA0 RAS# 112
DDR_A_WE# 113 VDD VDD 114 DDR_A_CS#0
DDR_A_CAS# 115 WE# S0# 116 DDR_A_ODT0
117 CAS# ODT0 118
DDR_A_MA13 119 VDD VDD 120 DDR_A_ODT1 +0.675V_DDRA_VREFCA +0.675V_DDR_VREFCA
DDR_A_CS#1 121 A13 ODT1 122
+1.35V_VDDQ 123 S1# NC 124
VDD VDD 10mils
125 126 RD8 1 @ 2 0_0402_1%
127 TEST VREF_CA 128
VSS VSS
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2.2U_0402_6.3V6M
0.1U_0402_25V6K
DDR_A_D5 129 130 DDR_A_D0
DDR_A_D4 131 DQ32 DQ36 132 DDR_A_D1
DQ33 DQ37 1 1
330U_D3_2.5VY_R6M
CD17
CD18
@ @ 1 133 134
1 1 1 1 1 1 1 1 DQS4# DM4
CD10
CD11
CD12
CD13
CD14
CD19
CD15
CD20
CD16
+ DDR_A_DQS0 137 138

139 DQS4 VSS 140 DDR_A_D2 2 2
DDR_A_D7 141 VSS DQ38 142 DDR_A_D6
2 2 2 2 2 2 2 2 2 DDR_A_D3 143 DQ34 DQ39 144
145 DQ35 VSS 146 DDR_A_D37
3 DDR_A_D36 147 VSS DQ44 148 DDR_A_D35 3
DDR_A_D32 149 DQ40 DQ45 150
151 DQ41 VSS 152 DDR_A_DQS#4
153 VSS DQS5# 154 DDR_A_DQS4
155 DM5 DQS5 156 +1.35V_VDDQ
DDR_A_D39 159 DQ42 DQ46 160 DDR_A_D38
DQ43 DQ47
1
1.8K_0402_1%
Layout Note: Layout Note: 161 162
VSS VSS
RD9
DDR_A_D21 163 164 DDR_A_D20
Place near JDIMM1.203,204 Place near JDIMM1.199 DDR_A_D17 165 DQ48 DQ52 166 DDR_A_D16
167 DQ49 DQ53 168 +0.675V_DDRA_VREFDQ +0.675V_A_VREFDQ
2
DDR_A_DQS2 171 DQS6# DM6 172
173 DQS6 VSS 174 DDR_A_D22 RD10 1 2
DDR_A_D18 175 VSS DQ54 176 DDR_A_D19 2_0402_1%
DQ50 DQ55 1
+0.675VS_VTT +3VS DDR_A_D23 177 178
179 DQ51 VSS 180 DDR_A_D61 CD21
VSS DQ60
1
1.8K_0402_1%
DDR_A_D56 181 182 DDR_A_D60 0.022U_0402_16V7K
DQ56 DQ61 2
RD11
DDR_A_D57 183 184
DQ57 VSS
0.1U_0402_25V6K
0.1U_0402_25V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2.2U_0402_6.3V6M
185 186 DDR_A_DQS#7

VSS DQS7#
1
@1 @1 1 1 1 187 188 DDR_A_DQS7
DM7 DQS7
1
CD22
CD23
0.1U_0402_25V6K
189 190 RD12
2
VSS VSS
CD24
CD25
CD26
DDR_A_D63 191 192 DDR_A_D58 24.9_0402_1%

DQ58 DQ62
CD27
@ DDR_A_D62 193 194 DDR_A_D59

2
2 2 2 2 2 +0.675VS_VTT +3VS 195 DQ59 DQ63 196 +0.675VS_VTT
2
DDR_A_SA0 197 VSS VSS 198 M_THERMAL#
199 SA0 EVENT# 200 SOC_SMBDATA
DDR_A_SA1 201 VDDSPD SDA 202 SOC_SMBCLK
+0.675VS_VTT 203 SA1 SCL 204 +0.675VS_VTT
VTT VTT Place near to SO-DIMM connector.
205 206
207 GND1 GND2 208
4 BOSS1 BOSS2 4
Address : FOX_AS0A621-J4RB-7H
00 1
RC220
1
2
2
10K_0402_5%
DDR_A_SA0
DDR_A_SA1
CONN@
Non- Interleaved Memory
RC221 10K_0402_5%
2015/01/06
Compal Secret Data
2016/01/06 Title
DDR3L_DIMMA
Size
1.0
A B C D E
A B C D E
<7> DDR_B_DQS#[0..7] +0.675V_DDRB_VREFDQ Reverse Type

10mils JDIMM2
<7> DDR_B_D[0..63] D/DQ Signals link to CPU 1 2
3 VREF_DQ VSS 4 DDR_B_D13
2-3A to 1 DIMMs/channel
<7> DDR_B_DQS[0..7] VSS DQ4
2.2U_0402_6.3V6M
0.1U_0402_25V6K
DDR_B_D8 5 6 DDR_B_D12
DDR_B_D9 7 DQ0 DQ5 8
1 1 DQ1 VSS
CD28
9 10 DDR_B_DQS#1
<7> DDR_B_MA[0..15] VSS DQS0#
CD29
11 12 DDR_B_DQS1
DDR_B_BS0 13 DM0 DQS0 14
<7> DDR_B_BS0 DDR_B_BS1 2 2 DDR_B_D10 15 VSS VSS 16 DDR_B_D15
<7> DDR_B_BS1 DDR_B_BS2 CMD Signals from CPU DDR_B_D11 17 DQ2 DQ6 18 DDR_B_D14
<7> DDR_B_BS2 19 DQ3 DQ7 20
DDR_B_WE#
<7> DDR_B_WE# 21 VSS VSS 22
DDR_B_CAS# DDR_B_D29 DDR_B_D25
1 <7> DDR_B_CAS# 23 DQ8 DQ12 24 1
DDR_B_RAS# DDR_B_D28 DDR_B_D24
<7> DDR_B_RAS# 25 DQ9 DQ13 26
DDR_B_DQS#3 27 VSS VSS 28
DDR_B_CLK0 DDR_B_DQS3 29 DQS1# DM1 30 DDR_DRAMRST# From CPU
<7> DDR_B_CLK0 DDR_B_CLK#0 Clock Signals from CPU 31 DQS1 RESET# 32 DDR_DRAMRST# <7,18>
<7> DDR_B_CLK#0 VSS VSS
0.1U_0402_25V6K
DDR_B_CLK1 DDR_B_D26 33 34 DDR_B_D30 1
<7> DDR_B_CLK1 DQ10 DQ14
CD30
DDR_B_CLK#1 DDR_B_D27 35 36 DDR_B_D31 @
<7> DDR_B_CLK#1 37 DQ11 DQ15 38
DDR_B_D41 39 VSS VSS 40 DDR_B_D45
DDR_B_CKE0 DDR_B_D40 41 DQ16 DQ20 42 DDR_B_D44 2
<7> DDR_B_CKE0 DDR_B_CKE1 CTL Signals from CPU 43 DQ17 DQ21 44
<7> DDR_B_CKE1 DDR_B_CS#0 DDR_B_DQS#5 45 VSS VSS 46
<7> DDR_B_CS#0 DDR_B_CS#1 DDR_B_DQS5 47 DQS2# DM2 48
<7> DDR_B_CS#1 49 DQS2 VSS 50 DDR_B_D47
DDR_B_D43 51 VSS DQ22 52 DDR_B_D46
DQ18 DQ23
CAD NOTE
SOC_SMBDATA SMBUS Signals link to CPU DDR_B_D42 53 54 PLACE THE CAP NEAR TO
<8,18,36> SOC_SMBDATA SOC_SMBCLK 55 DQ19 VSS 56 DDR_B_D61
<8,18,36> SOC_SMBCLK DDR_B_D56 57 VSS DQ28 58 DDR_B_D60
DIMM RESET PIN
DDR_B_D57 59 DQ24 DQ29 60
DDR_B_ODT0 61 DQ25 VSS 62 DDR_B_DQS#7
<7> DDR_B_ODT0 63 VSS DQS3# 64
DDR_B_ODT1 From SOC ODT Signals to CH B DDR_B_DQS7
<7> DDR_B_ODT1 65 DM3 DQS3 66
M_THERMAL# DDR_B_D58 69 DQ26 DQ30 70 DDR_B_D63
<18,41> M_THERMAL# DQ27 DQ31 +1.35V_VDDQ
Thermal link to EC 71 72
+1.35V_VDDQ VSS VSS +1.35V_VDDQ
1
1.8K_0402_1%
Layout Note: DDR_B_CKE0 73 74 DDR_B_CKE1
CKE0 CKE1
RD13
75 76
Place near JDIMM2 77 VDD VDD 78 DDR_B_MA15
DDR_B_BS2 79 NC A15 80 DDR_B_MA14 +0.675V_DDRB_VREFDQ +0.675V_B_VREFDQ
81 BA2 A14 82
2
2 DDR_B_MA12 83 VDD VDD 84 DDR_B_MA11 2
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7 RD14 1 2
87 A9 A7 88 2_0402_1%
VDD VDD 1
+1.35V_VDDQ DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4 CD31
A5 A4
1
1.8K_0402_1%
93 94 0.022U_0402_16V7K
VDD VDD 2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
RD15
DDR_B_MA3 95 96 DDR_B_MA2
@1 @1 @1 @1 DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
1 1 A1 A0
1
99 100
VDD VDD
CD32
CD33
CD34
CD35
CD36
CD37
DDR_B_CLK0 101 102 DDR_B_CLK1 RD16
2
DDR_B_CLK#0 103 CK0 CK1 104 DDR_B_CLK#1
CK0# CK1# 24.9_0402_1%
2 2 2 2 2 2 105 106
DDR_B_MA10 107 VDD VDD 108 DDR_B_BS1
2
DDR_B_BS0 109 A10/AP BA1 110 DDR_B_RAS#
111 BA0 RAS# 112
DDR_B_WE# 113 VDD VDD 114 DDR_B_CS#0
DDR_B_CAS# 115 WE# S0# 116 DDR_B_ODT0
117 CAS# ODT0 118
Place near to SO-DIMM connector.
DDR_B_MA13 119 VDD VDD 120 DDR_B_ODT1
+1.35V_VDDQ DDR_B_CS#1 121 A13 ODT1 122 +0.675V_DDRB_VREFCA +0.675V_DDR_VREFCA
123 S1# NC 124
VDD VDD 10mils
125 126 RD17 1 @ 2 0_0402_1%
TEST VREF_CA
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
127 128
VSS VSS
2.2U_0402_6.3V6M
0.1U_0402_25V6K
DDR_B_D2 129 130 DDR_B_D0
DQ32 DQ36
330U_D3_2.5VY_R6M
1 DDR_B_D5 131 132 DDR_B_D4

@1 @1 @ 133 DQ33 DQ37 134
1 1 1 1 1 1 VSS VSS 1 1
CD38
CD39
CD40
CD41
CD42
CD43
CD44
CD45
CD46
CD47
CD48
+ DDR_B_DQS#0 135 136
DDR_B_DQS0 137 DQS4# DM4 138
139 DQS4 VSS 140 DDR_B_D3
2 2 2 2 2 2 2 2 2 DDR_B_D6 141 VSS DQ38 142 DDR_B_D1 2 2
DDR_B_D7 143 DQ34 DQ39 144
145 DQ35 VSS 146 DDR_B_D16
3 DDR_B_D21 147 VSS DQ44 148 DDR_B_D17 3
DDR_B_D20 149 DQ40 DQ45 150
151 DQ41 VSS 152 DDR_B_DQS#2
153 VSS DQS5# 154 DDR_B_DQS2
155 DM5 DQS5 156
DDR_B_D18 159 DQ42 DQ46 160 DDR_B_D23 +1.35V_VDDQ
161 DQ43 DQ47 162
Layout Note: Layout Note: VSS VSS
DDR_B_D37 163 164 DDR_B_D32
Place near JDIMM2.203,204 Place near JDIMM2.199 DQ48 DQ52
1
1.8K_0402_1%
DDR_B_D36 165 166 DDR_B_D34
DQ49 DQ53
RD18
167 168
DDR_B_DQS#4 169 VSS VSS 170
DDR_B_DQS4 171 DQS6# DM6 172 +0.675V_DDR_VREFCA +0.675V_VREFCA
173 DQS6 VSS 174 DDR_B_D39
2
DDR_B_D33 175 VSS DQ54 176 DDR_B_D38
+0.675VS_VTT +3VS DDR_B_D35 177 DQ50 DQ55 178 RD19 1 2
179 DQ51 VSS 180 DDR_B_D53 2_0402_1%
VSS DQ60 1
DDR_B_D48 181 182 DDR_B_D52
DDR_B_D49 183 DQ56 DQ61 184 CD49
DQ57 VSS
1
0.1U_0402_25V6K
0.1U_0402_25V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_25V6K
1.8K_0402_1%
2.2U_0402_6.3V6M
185 186 DDR_B_DQS#6 0.022U_0402_16V7K

VSS DQS7# 2
RD20
@1 @1 1 1 1 187 188 DDR_B_DQS6
DM7 DQS7
1
CD50
CD51
CD54
189 190
VSS VSS
1
CD52
CD53
CD55
DDR_B_D51 191 192 DDR_B_D54

@ DDR_B_D50 193 DQ58 DQ62 194 DDR_B_D55 RD21
2
2
2 2 2 2 2 +0.675VS_VTT +3VS 195 DQ59 DQ63 196 +0.675VS_VTT
VSS VSS 24.9_0402_1%
DDR_B_SA0 197 198 M_THERMAL#
199 SA0 EVENT# 200 SOC_SMBDATA
2
DDR_B_SA1 201 VDDSPD SDA 202 SOC_SMBCLK
+0.675VS_VTT 203 SA1 SCL 204 +0.675VS_VTT
VTT VTT
205 206
207 GND1 GND2 208
4 BOSS1 BOSS2 Place near to SO-DIMM connector. 4
Address : 01 FOX_AS0A621-J4RB-7H
+3VS
1 2 DDR_B_SA1
CONN@
Non-Interleaved Memory
RD22 10K_0402_5%
1
RD23
2
10K_0402_5%
DDR_B_SA0 Security Classification
2015/01/06
Compal Secret Data
2016/01/06 Title
DDR3L_DIMMB
Size
1.0
A B C D E
5 4 3 2 1
eDP connector
LCD power control 0.1U_0402_16V7K 2 1 CV15 EDP_TXP0_C 1
JEDP
<6> EDP_TXP0 2 1 CV12 2 1 41
0.1U_0402_16V7K EDP_TXN0_C
+3VS +LCDVDD_CONN <6> EDP_TXN0 3 2 G1 42
LV1
FBMA-L11-201209-221LMA30T_0805 0.1U_0402_16V7K 2 1 CV17 EDP_TXP1_C 4 3 G2 43
D <6> EDP_TXP1 4 G3 D
UV3 0.1U_0402_16V7K 2 1 CV16 EDP_TXN1_C 5 44
W=60mils 5
IN OUT
1 +LCDVDD 1 2 W=60mils <41> BKOFF#
2 1 DISPOFF#
<6> EDP_TXN1 6 5
6
G4
0.1U_0402_16V7K 2 1 CV198 EDP_TXP2_C 7
<6> EDP_TXP2 7
1
2 DV1 0.1U_0402_16V7K 2 1 CV199 EDP_TXN2_C 8
GND <6> EDP_TXN2 8
0.1U_0402_10V7K
CV14
4.7U_0805_10V4Z
CV21
1 RB751V-40_SOD323-2 9
ENVDD_R 4 3 1 2 10K_0402_5% 0.1U_0402_16V7K 2 1 CV200 EDP_TXP3_C 10 9
EN OC +3VS 1 1 <6> EDP_TXP3 10
CV19 RV5 0.1U_0402_16V7K 2 1 CV201 EDP_TXN3_C 11
<6> EDP_TXN3 12 11
4.7U_0805_10V4Z SY6288C20AAC_SOT23-5 RV28
2
2 10K_0402_5% 0.1U_0402_16V7K 2 1 CV13 EDP_AUXP_C 13 12
2 2 <6> EDP_AUXP 13
0.1U_0402_16V7K 2 1 CV18 EDP_AUXN_C 14
<6> EDP_AUXN 14
15
EDP_HPD 16 15
<6> EDP_HPD 16
1 @ 2 17
<6> EDP_VDDEN +VDD_TOUCH 17
RV6 0_0402_1% CE_EN_R 18
DBC_EN_R 19 18
MCM1012B900F06BP_4P 20 19
4 3 USB20_L_P6 21 20
<12> USB20_P6 21
22
USB20_L_P6 23 22
1 2 USB20_L_N6 USB20_L_N6 24 23
<12> USB20_N6
+LCDVDD_CONN W=60mils 25 24
25
LV2 EMI@ 26
TS_EN 27 26
<41> TS_EN 28 27
1 2 For Camera +3VS
29 28
29
RV9 0_0402_5% MIC_CLK_R 30
@EMI@ MIC_GND 31 30
1 2 MIC_DATA 32 31
<31> MIC_DATA 33 32
RV10 0_0402_5% <41> LCD_TEST LCD_TEST
@EMI@ USB20_N5 34 33
USB20_P5 35 34
36 35
<6> EDP_BIA_PWM 37 36
DISPOFF#
38 37
38
1
39
RV11 +INV_PWR_SRC W=60mils 40 39
40
C 100K_0402_5% C
<12> USB20_N5 USB20_N5 ACES_50473-0400M-P01
CONN@
LCD backlight power control
2
<12> USB20_P5 USB20_P5
3
QV6
SI3457CDV-T1-GE3_TSOP6
DV2
B+ 6 W=60mils +INV_PWR_SRC PESD5V0U2BT_SOT23-3 +3VS +LCDVDD_CONN
5 @ESD@
2
W=60mils
0.1U_0402_10V7K
0.1U_0402_10V7K
10U_0805_10V6K
4 1
S
1
1 1 1 1
1000P_0402_50V7K
CV22
100K_0402_5%
RV12
CV24
CV25
CV26
1
CV23
G
1
0.1U_0603_25V7K
3
2 2 2 2
2
2
PWR_SRC_ON
Place close to JEDP
1
RV15
100K_0402_5%
2
1
D
2 QV7
<41> EN_INVPWR
G 2N7002KW_SOT323-3
B
S
Touch screen panel power control B
3
1
RV29
100K_0402_5%
2
+5VS +VDD_TOUCH CE_EN_R

@
J512 DBC_EN 1 @ 2 DBC_EN_R
1 2 <41> DBC_EN
RV20 0_0402_1%
1 2
1
JUMP_43X39
0.1U_0402_10V7K
CV28
@
1 1 RV16 @ RV17
0_0402_1% 0_0402_5%
CV27
2
2
4.7U_0805_10V4Z
2 2
MIC_CLK 1 @ 2 MIC_CLK_R
<31> MIC_CLK
RV21 0_0402_1%
1
CV420
15P_0402_50V8J
2
A A

eDP/webcam/touch
1.0
5 4 3 2 1
5 4 3 2 1
Place close to JHDMI

TMDS_TXCN RV23 1 2 5.1_0402_1% TMDS_L_TXCN
EMI@ +5VS +VDISPLAY_VCC
UV5
LV3 @EMI@
W=60mils
2
1 2 3
RV22 VOUT
10U_0603_6.3V6M
0.1U_0402_16V7K
1 1
CV33
150_0402_1% 1
4 3 VIN CV34
EMI@
2
1
HCM1012GH900BP_4P GND +3VS 2 2
TMDS_TXCP RV24 1 2 5.1_0402_1% TMDS_L_TXCP APL3517AI-TRG_SOT23-3

D EMI@ D
1
TMDS_TX0N RV26 1 2 5.1_0402_1% TMDS_L_TX0N
EMI@ @
RV19
LV4 @EMI@ 10K_0402_5%
2
1 2
2
RV25 JHDMI
150_0402_1% HDMI_HPLUG 19
4 3 18 HP_DET
Near Connector EMI@
17 +5V
1
HCM1012GH900BP_4P HDMI_CTRLDAT 16 DDC/CEC_GND
CV40 2 1 0.1U_0402_10V7K TMDS_TX2P HDMI_CTRLCLK 15 SDA
<23> DDI1_LANE_P0 SCL
CV39 2 1 0.1U_0402_10V7K TMDS_TX2N TMDS_TX0P RV30 1 2 5.1_0402_1% TMDS_L_TX0P 14
<23> DDI1_LANE_N0 13 Reserved
EMI@
CV38 2 1 0.1U_0402_10V7K TMDS_TX1P TMDS_L_TXCN RV46 1 2 TMDS_L_R_TXCN 12 CEC 20
<23> DDI1_LANE_P1 CK- GND
CV37 2 1 0.1U_0402_10V7K TMDS_TX1N TMDS_TX1N RV32 1 2 5.1_0402_1% TMDS_L_TX1N 6.04_0402_1% 11 21
<23> DDI1_LANE_N1 CK_shield GND
From GPU EMI@ TMDS_L_TXCP RV48 1 6.04_0402_1%
2 TMDS_L_R_TXCP 10 22
CV36 2 1 0.1U_0402_10V7K TMDS_TX0P TMDS_L_TX0N RV53 1 2 TMDS_L_R_TX0N 9 CK+ GND 23
<23> DDI1_LANE_P2 D0- GND
CV35 2 1 0.1U_0402_10V7K TMDS_TX0N LV5 @EMI@ 6.04_0402_1%% 8
<23> DDI1_LANE_N2 D0_shield
2
1 2 TMDS_L_TX0P RV54 1 6.04_0402_1%
2 TMDS_L_R_TX0P 7
CV32 2 1 0.1U_0402_10V7K TMDS_TXCP RV31 TMDS_L_TX1N RV59 1 2 TMDS_L_R_TX1N 6 D0+
<23> DDI1_LANE_P3 D1-
CV31 2 1 0.1U_0402_10V7K TMDS_TXCN 150_0402_1% 6.04_0402_1% 5
<23> DDI1_LANE_N3 4 3 D1_shield
EMI@ TMDS_L_TX1P RV61 1 6.04_0402_1%
2 TMDS_L_R_TX1P 4
TMDS_L_TX2N RV65 1 2 TMDS_L_R_TX2N 3 D1+
1
D2-
1
RV533
499_0402_1%
RV534
499_0402_1%
RV535
499_0402_1%
RV536
499_0402_1%
RV537
499_0402_1%
RV538
499_0402_1%
RV539
499_0402_1%
RV540
499_0402_1%
HCM1012GH900BP_4P 6.04_0402_1% 2
TMDS_L_TX2P RV67 1 6.04_0402_1%
2 TMDS_L_R_TX2P 1 D2_shield
TMDS_TX1P RV33 1 2 5.1_0402_1% TMDS_L_TX1P D2+
EMI@ FUTUR_061-HA18-0001
CONN@
2
2
TMDS_TX2N RV43 1 2 5.1_0402_1% TMDS_L_TX2N
EMI@
LV6 @EMI@
2
1 2
RV36
ROYALTY HDMI W/LOGO
1
D
150_0402_1%
2 QV3 4 3
C +3VS_VGA EMI@ C
G BSS138-G_SOT23-3
CPN:RO0000002HM
1
1
S HCM1012GH900BP_4P
3
RV13
100K_0402_5% TMDS_TX2P RV44 1 2 5.1_0402_1% TMDS_L_TX2P
EMI@
+VDISPLAY_VCC
SDM10U45-7_SOD523-2~D
SDM10U45-7_SOD523-2~D
2
DV3 DV4
+3VS_VGA
1
1
1 RV101
10K_0402_5%
10K_0402_5%
2
1RV100
RV543 RV544
+3VS
<6> HDMI_HPD
2K_0402_5%
2K_0402_5%
B QV5 B
1
1
LV14,LV15 follow Echo MLK 15/17 dat.02/11 C RV547
2 1 2 HDMI_HPLUG
5
QV89A B 150K_0402_5%
2
LV14 E
RV545
G
3
HDMI_SCL 4 3HDMI_SCLF 2 1 HDMI_SCLR 1 2 HDMI_CTRLCLK RV14 1 @ 2 0_0402_5% HDMI_HPD 1
<23> HDMI_SCL
S
33_0402_1% 27NH_LQG15HS27NJ02D_300MA_5% MMST3904-7-F_SOT323~D

DMN66D0LDW-7_SOT363-6 CV2
2
1
+3VS 0.1U_0402_16V7K
LV15 2
QV89B RV546 CV3 RV553
G
HDMI_SDA 1 6 HDMI_SDAF 2 1 HDMI_SDAR 1 2 HDMI_CTRLDAT 1 2 100K_0402_5%

<23> HDMI_SDA
S
33_0402_1% 27NH_LQG15HS27NJ02D_300MA_5%
10P_0402_50V8J
10P_0402_50V8J
DMN66D0LDW-7_SOT363-6 0.1U_0402_16V7K
2
5
1 1 UV16
Place closed to JHDMI1 CV441 CV442 1 HDMI_HPD
P
HDMI_DET 4 B
<22> HDMI_DET O 2 DGPU_PEX_RST#
A DGPU_PEX_RST# <22>
G
2 2
2
TC7SH08FU_SSOP5~D
3
RV18
100K_0402_5%
1
A A

HDMI conn
1.0
5 4 3 2 1
5 4 3 2 1
UV1A
UV1 UV1
AN12 Part 1 of 7
<34> PEG_CTX_GRX_P0_GPU AM12 PEX_RX0 P6 GPU_GC6_FB_EN
<34> PEG_CTX_GRX_N0_GPU AN14 PEX_RX0_N GPIO0 M3 GPU_GC6_FB_EN <11,25> GC6_EVENT#_D 2 1 GC6_EVENT#
<34> PEG_CTX_GRX_P1_GPU AM14 PEX_RX1 GPIO1 L6 GC6_EVENT# <11>
<34> PEG_CTX_GRX_N1_GPU AP14 PEX_RX1_N GPIO2 P5 DV9
<34> PEG_CTX_GRX_P2_GPU AP15 PEX_RX2 GPIO3 P7
S IC CL8064701477802 SR1EF D0 1.7G A31! S IC CL8064701477802 SR1EF D0 1.7G A31! SDM10U45-7_SOD523-2~D
<34> PEG_CTX_GRX_N2_GPU AN15 PEX_RX2_N GPIO4 L7 3V3_MAIN_EN
SA000084Q0L SA000084Q1L <34> PEG_CTX_GRX_P3_GPU PEX_RX3 GPIO5 3V3_MAIN_EN <25,56,57>
R1N16P@ R3N16P@ AM15 M7 GC6_EVENT#_D
<34> PEG_CTX_GRX_N3_GPU AN17 PEX_RX3_N GPIO6 N8
AM17 PEX_RX4 GPIO7 L3 SYS_PEX_RST_MON# +3.3V_GFX_AON
AP17 PEX_RX4_N GPIO8 M2 THERMAL_ALERT#
D AP18 PEX_RX5 GPIO9 L1 MEM_VREF D
AN18 PEX_RX5_N GPIO10 M5 NVVDD PWM_VID MEM_VREF <27,28> THERMAL_ALERT# 1 2
AM18 PEX_RX6 GPIO11 N3 GPU_LEVEL NVVDD PWM_VID <57>
RV526 10K_0402_5%
GPIO
PEX_RX6_N GPIO12
2
AN20 M4 NVVDD PSI SYS_PEX_RST_MON# 1 @ 2
AM20 PEX_RX7 GPIO13 N4 NVVDD PSI <57>
RV27 RV532 10K_0402_5%
AP20 PEX_RX7_N GPIO14 P2 HDMI_DET GPU_PEX_RST_HOLD# 1 2
PEX_RX8 GPIO15 HDMI_DET <21> 100K_0402_5%~D
AP21 R8 RV41 10K_0402_5%
AN21 PEX_RX8_N GPIO16 M6 3V3_MAIN_EN 1 2
1
AM21 PEX_RX9 GPIO17 R1 RV55 10K_0402_1%
AN23 PEX_RX9_N GPIO18 P3 GC6_EVENT#_D 1 2
AM23 PEX_RX10 GPIO19 P4 RV42 10K_0402_5%
AP23 PEX_RX10_N GPIO20 P1 GPU_PEX_RST_HOLD# GPU_LEVEL 2 @ 1
AP24 PEX_RX11 GPIO21 RV60 100K_0402_5%~D
AN24 PEX_RX11_N NVVDD PSI 1 2
AM24 PEX_RX12 RV35 10K_0402_1%
AN26 PEX_RX12_N SYS_PEX_RST_MON#
AM26 PEX_RX13
AP26 PEX_RX13_N +3VS_VGA
PEX_RX14 <Dell's requirement>
5
AP27
AN27 PEX_RX14_N AK9
AM27 PEX_RX15 DACA_RED AL10 THERMAL_ALERT# 4 3 VGA_SMB_CK2 1 2
PEX_RX15_N DACA_GREEN AL9 GPU_ALERT# <41>
RV191 1.8K_0402_5%
DACA_BLUE 2N7002DW-T/R7_SOT363-6 VGA_SMB_DA2 1 2
DACs
CV54 1 2 0.22U_0402_10V6K PEG_CRX_GTX_C_P0 AK14 QV2B RV192 1.8K_0402_5%
<34> PEG_CRX_GTX_P0_GPU 1 2 PEG_CRX_GTX_C_N0 AJ14 PEX_TX0 AM9 SYS_PEX_RST_MON#
CV55 0.22U_0402_10V6K
<34> PEG_CRX_GTX_N0_GPU 1 2 PEG_CRX_GTX_C_P1 AH14 PEX_TX0_N DACA_HSYNC AN9
CV56 0.22U_0402_10V6K
<34> PEG_CRX_GTX_P1_GPU 1 2 PEG_CRX_GTX_C_N1 AG14 PEX_TX1 DACA_VSYNC GPU_GC6_FB_EN 1 2
CV57 0.22U_0402_10V6K
<34> PEG_CRX_GTX_N1_GPU PEX_TX1_N
2
CV58 1 2 0.22U_0402_10V6K PEG_CRX_GTX_C_P2 AK15 RV37 10K_0402_5%
<34> PEG_CRX_GTX_P2_GPU 1 2 PEG_CRX_GTX_C_N2 AJ15 PEX_TX2 AG10 MEM_VREF 2 1
CV59 0.22U_0402_10V6K
<34> PEG_CRX_GTX_N2_GPU 1 2 PEG_CRX_GTX_C_P3 AL16 PEX_TX2_N DACA_VDD AP9 OVERT# 1 6
CV60 0.22U_0402_10V6K RV38 @ 100K_0402_5%~D
PCI EXPRESS
<34> PEG_CRX_GTX_P3_GPU 1 2 PEG_CRX_GTX_C_N3 AK16 PEX_TX3 DACA_VREF AP8 <23> OVERT# GPU_OVERT# <41>
CV61 0.22U_0402_10V6K
<34> PEG_CRX_GTX_N3_GPU AK17 PEX_TX3_N DACA_RSET 2N7002DW-T/R7_SOT363-6
C AJ17 PEX_TX4 QV2A C
AH17 PEX_TX4_N
AG17 PEX_TX5 +3.3V_GFX_AON
AK18 PEX_TX5_N
AJ18 PEX_TX6 GPU_PWR_LEVEL
PEX_TX6_N
0.1U_0402_10V7K
AL19
PEX_TX7 Low Low Performace
10K_0402_5%
AK19 R4 VGA_CRT_CLK 1 2
PEX_TX7_N I2CA_SCL
1
0.1U_0402_10V7K
+3VALW AK20 R5 VGA_CRT_DATA RV510 1 2 1.8K_0402_5%

PEX_TX8 I2CA_SDA 1 High High Performace
RV70
CV421
AJ20 RV511 1.8K_0402_5%
AH20 PEX_TX8_N R7 I2CB_SCL 1 2 @
1 PEX_TX9 I2CB_SCL
CV212
1 @ 2 AG20 R6 I2CB_SDA RV512 1 2 1.8K_0402_5%

RV58 10K_0402_5% AK21 PEX_TX9_N I2CB_SDA RV513 1.8K_0402_5% 2@
2
PEX_TX10
5
I2C
AJ21 R2 VGA_EDID_CLK 1 2
2@ AL22 PEX_TX10_N I2CC_SCL R3 VGA_EDID_DATA RV514 1 2 1.8K_0402_5% 1 GPU_PWR_LEVEL
G VCC
AK22 PEX_TX11 I2CC_SDA GPU_LEVEL 4 B GPU_PWR_LEVEL <41>
RV515 1.8K_0402_5% @
PEX_TX11_N Y
5
AK23 T4 VGA_SMB_CK2 2 1 2
DGPU_HOLD_RST# 1 AJ23 PEX_TX12 I2CS_SCL T3 VGA_SMB_DA2 A ACIN <10,37,41,51,52>
CV422 0.1U_0402_10V7K
P
<11> DGPU_HOLD_RST# B 4 SYS_PEX_RST_MON# AH23 PEX_TX12_N I2CS_SDA
3
SOC_PLTRST# 2 O AG23 PEX_TX13 UV15
<10,34> SOC_PLTRST# A PEX_TX13_N
G
AK24 MC74VHC1G09DFT2G_SC70-5
UV14 RV187 AJ24 PEX_TX14 @
W=78mils
3
TC7SH08FU_SSOP5~D AL25 PEX_TX14_N @

10K_0402_5% PEX_TX15
AK25 +PLLVDD RV45
PEX_TX15_N 0_0402_5% GPU_LEVEL 1 2 GPU_PWR_LEVEL
2
AD8 1 2 RV71 0_0402_5%

AJ11 PLLVDD LV7
+3.3V_GFX_AON +3.3V_GFX_AON NC
SP_PLLVDD
AE8 W=71mils BLM18PG181SN1D_2P
AL13
<34> CLK_PEG_N15P PEX_REFCLK W=41mils 150mA
1
0_0402_5%
AK13 AD7 +SP_PLLVDD 1 2 +SP_PLLVDD

<34> CLK_PEG_N15P# PEX_REFCLK_N VID_PLLVDD +1.05VS_VGA
RV208
22U_0805_6.3V6M
4.7U_0402_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
CLK_REQ AK12
PEX_CLKREQ_N
1
10K_0402_5%
CV50
CV51
CV52
CV53
CLK
DGPU_HOLD_RST# 1 2 @
180 ohm 1 1 1 1
RV39
RV69 10K_0402_5% 1 @ 2 PEX_TSTCLK_OUT AJ26 H3 XTALIN

B RV47 200_0402_1% PEX_TSTCLK_OUT# AK26 PEX_TSTCLK_OUT XTAL_IN H2 XTAL_OUT B
(ESR=0.2) Bead
2
PEX_TSTCLK_OUT_N XTAL_OUT
DV8 DGPU_PEX_RST# 1 @ 2 DGPU_PEX_RST#_R AJ12 J4 XTALOUT 2 2 2 2
2
SYS_PEX_RST_MON# 2 RV40 1 2 0_0402_1% PEX_TERMP AP29 PEX_RST_N XTAL_OUTBUFF H1 XTALSSIN 1 2

PEX_TERMP XTAL_SSIN
1
RV50 2.49K_0402_1% 10K_0402_5% RV49
1 RV51
DGPU_PEX_RST# <21>
10K_0402_5%
GPU_PEX_RST_HOLD# 3 Under GPU
N116P-GX_BGA908
(below 150mils)
2
@
BAT54A-7-F_SOT23-3
Internal Thermal Sensor
GC6 2.0 function +PLLVDD 1 2
+1.05VS_VGA
22U_0805_6.3V6M
0.1U_0402_10V7K
1 2
RV52 10M_0402_5% 1 1 LV8
CV72
CV73
BLM18PG181SN1D_2P
YV1
SYS_PEX_RST_MON# 27MHZ_10PF_7V27000050
2 2 30 ohm@100MHz (ESR=0.05)
XTALIN 1 3XTAL_OUT
1 3
5
GND GND
VGA_SMB_CK2 4 3 CV70 CV71
EC_SMB_CK2 <8,40,41,46> 2 4
10P_0402_50V8J 10P_0402_50V8J
+3.3V_GFX_AON 2N7002DW-T/R7_SOT363-6
<56,57> NVVDD_PWR_GD
QV1B CV72 under GPU
CV73 near GPU
2
2
2
RV56
10K_0402_5% RV57 VGA_SMB_DA2 1 6
A EC_SMB_DA2 <8,40,41,46> A
10K_0402_5%
1 2
G
2N7002DW-T/R7_SOT363-6
QV12 QV1A
1
1 3 CLK_REQ
<10,34> CLKREQ_PCIE#0
D
2N7002H 1N_SOT23-3
N16P_PCIE/DAC/GPIO
5 4 3 2 1
5 4 3 2 1
UV1D
Part 4 of 7
AM6
AN6 IFPA_TXC P8
AP3 IFPA_TXC_N 3V3AUX_NC AC6
AN3 IFPA_TXD0 NC AJ28
D
AN5 IFPA_TXD0_N NC AJ4 D
AM5 IFPA_TXD1 NC AJ5
AL6 IFPA_TXD1_N NC AL11
AK6 IFPA_TXD2 NC C15
AJ6 IFPA_TXD2_N NC D19
AH6 IFPA_TXD3 NC D20
NC
IFPA_TXD3_N NC D23
NC D26
AJ9 NC H31
AH9 IFPB_TXC NC T8
AP6 IFPB_TXC_N NC V32
AP5 IFPB_TXD4 NC
AM7 IFPB_TXD4_N
IFPB_TXD5
trace width: 16mils
AL7
AN8 IFPB_TXD5_N
IFPB_TXD6
differential voltage sensing.
AM8
AK8 IFPB_TXD6_N
IFPB_TXD7
differential signal routing.
AL8
IFPB_TXD7_N L4 VCCSENSE_VGA
VDD_SENSE VCCSENSE_VGA <57>
AK1
<21> DDI1_LANE_P0 IFPC_L0
AJ1
<21> DDI1_LANE_N0 IFPC_L0_N
AJ3 L5 VSSSENSE_VGA
<21> DDI1_LANE_P1 IFPC_L1 GND_SENSE VSSSENSE_VGA <57>
AJ2
AH3
AH4
AG5
AG4
C TEST C
AM1 AK11 TESTMODE
AM2 IFPD_L0 TESTMODE
IFPD_L0_N
1
AM3 AM10 GPU_JTAG_TCK PAD~D T98 @
AM4 IFPD_L1 JTAG_TCK AM11 GPU_JTAG_TDI PAD~D T99 @
AL3 IFPD_L1_N JTAG_TDI AP12 GPU_JTAG_TDO PAD~D T100 @ RV62
AL4 IFPD_L2 JTAG_TDO AP11 GPU_JTAG_TMS PAD~D T101 @ 10K_0402_5%
AK4 IFPD_L2_N JTAG_TMS AN11 GPU_JTAG_TRST# 1 2
2
AK5 IFPD_L3 JTAG_TRST_N
IFPD_L3_N RV63
LVDS/TMDS
10K_0402_5%
AD2
AD3 IFPE_L0
AD1 IFPE_L0_N
AC1 IFPE_L1 SERIAL
AC2 IFPE_L1_N H6 ROM_CS
IFPE_L2 ROM_CS_N ROM_CS <29>
AC3 H4 ROM_SCLK
IFPE_L2_N ROM_SCLK ROM_SCLK <29>
AC4 H5 ROM_SI
IFPE_L3 ROM_SI ROM_SI <29>
AC5 H7 ROM_SO
IFPE_L3_N ROM_SO ROM_SO <29>
+3.3V_GFX_AON
AE3
AE4 IFPF_L0
IFPF_L0_N
2
AF4
AF5 IFPF_L1 RV34
AD4 IFPF_L1_N GENERAL 10K_0402_5%
AD5 IFPF_L2 L2 2 1
AG1 IFPF_L2_N BUFRST_N RV64 10K_0402_5%
1
AF1 IFPF_L3 M1 OVERT#
IFPF_L3_N OVERT OVERT# <22>
B B
J1 1 2
MULTI_STRAP_REF0_GND RV66 40.2K_0402_1%
HDMI_SCL AG3
<21> HDMI_SCL IFPC_AUX_I2CW _SCL
HDMI_SDA AG2
<21> HDMI_SDA IFPC_AUX_I2CW _SDA_N J2 STRAP0
STRAP0 STRAP0 <29>
J7 STRAP1
STRAP1 STRAP1 <29>
AK3 J6 STRAP2
IFPD_AUX_I2CX_SCL STRAP2 STRAP2 <29>
AK2 J5 STRAP3
IFPD_AUX_I2CX_SDA_N STRAP3 STRAP3 <29>
J3 STRAP4
STRAP4 STRAP4 <29>
AB3
AB4 IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N K3
THERMDP K4
AF3 THERMDN
AF2 IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N
N116P-GX_BGA908
@
A A

N16P_HDMI
5 4 3 2 1
5 4 3 2 1
UV1E
+1.35VS_VGA Part 5 of 7 3500mA Under GPU Near GPU +1.05VS_VGA

For GDDR5 setting. Near GPU
AA27 AG19
FBVDDQ_0 PEX_IOVDD_0
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CV83
CV84
CV85
CV86
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
AA30 AG21
FBVDDQ_1 PEX_IOVDD_1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CV74
CV75
CV76
CV110
CV77
CV78
CV79
CV80
CV87
CV88
CV89
CV90
CV91
CV92
CV93
CV94
CV95
CV111
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
D 1 1 1 1 1 1 2 2 1 1 1 1 AB27 AG22 1 1 1 1 1 1 2 2 2 2 D
AB33 FBVDDQ_2 PEX_IOVDD_2 AG24
AC27 FBVDDQ_3 PEX_IOVDD_3 AH21
AD27 FBVDDQ_4 PEX_IOVDD_4 AH25
2 2 2 2 2 2 1 1 2 2 2 2 AE27 FBVDDQ_5 PEX_IOVDD_5 2 2 2 2 2 2 1 1 1 1
AF27 FBVDDQ_6
AG27 FBVDDQ_7 AG13
B13 FBVDDQ_8 PEX_IOVDDQ_0 AG15
B19 FBVDDQ_9 PEX_IOVDDQ_1 AG16 +1.05VS_VGA
E13 FBVDDQ_11 PEX_IOVDDQ_2 AG18
Under GPU(below 150mils) FBVDDQ_12 PEX_IOVDDQ_3
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
+1.35VS_VGA E19 AG25
FBVDDQ_14 PEX_IOVDDQ_4
CV96
CV97
CV98
CV99
H10 AH15 1 1 1 1
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
H11 AH18
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CV100
CV101
CV102
CV103
CV112
CV113
CV104
CV105
CV106
CV107
CV108
CV109
1 1 1 1 1 1 1 1 1 1 1 1 H12 AH26
H13 FBVDDQ_17 PEX_IOVDDQ_7 AH27
H14 FBVDDQ_18 PEX_IOVDDQ_8 AJ27 2 2 2 2
H18 FBVDDQ_19 PEX_IOVDDQ_9 AK27
2 2 2 2 2 2 2 2 2 2 2 2 H19 FBVDDQ_22 PEX_IOVDDQ_10 AL27
H20 FBVDDQ_23 PEX_IOVDDQ_11 AM28
Near GPU
POWER
H21 FBVDDQ_24 PEX_IOVDDQ_12 AN28 +3.3V_GFX_AON
H22 FBVDDQ_25 PEX_IOVDDQ_13 +3.3V_GFX_AON
H23 FBVDDQ_26
+1.35VS_VGA H24 FBVDDQ_27 Place near balls Place near GPU
Under GPU(below 150mils) H8 FBVDDQ_28
FBVDDQ_29 PEX_PLL_HVDD
AH12 +3.3V_GFX_AON 210mA
0.1U_0402_10V7K
0.1U_0402_10V7K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
H9
FBVDDQ_30
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
CV114
CV115
CV116
CV202
CV214
CV213
L27 1 1 1 1 1 1
FBVDDQ_31
1U_0402_6.3V6K
1U_0402_6.3V6K
CV211
CV210
CV209
CV206
CV207
CV208
CV205
CV215
CV203
CV204
1 1 1 1 1 1 1 1 1 1 M27
N27 FBVDDQ_32 AG12 +3.3V_GFX_AON
P27 FBVDDQ_33 PEX_SVDD_3V3
R27 FBVDDQ_34 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 T27 FBVDDQ_35
T30 FBVDDQ_36
FBVDDQ_37 PEX_PLLVDD
AG26 150mA
T33
Y27 FBVDDQ_38 +3.3V_GFX_AON
FBVDDQ_43
C +3VS_VGA C
J8
3V3_AON K8 85mA
3V3_AON L8 Place near balls Place near GPU
B16
FBVDDQ_AON
3V3_MAIN
3V3_MAIN
M8 +3VS_VGA 85mA
0.1U_0402_10V7K
0.1U_0402_10V7K
4.7U_0603_6.3V6K
E16
+1.05VS_VGA FBVDDQ_AON
1U_0402_6.3V6K
CV117
CV118
CV119
CV120
H15 1 1 1 1
LV16 H16 FBVDDQ_AON RV551
2 1 IFP_IOVDD V27 FBVDDQ_AON AH8 @1 2 0_0402_5% IFP_PLLVDD
FBVDDQ_AON IFPAB_PLLVDD
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
W27 AJ8 @1 2 1K_0402_1%

FBVDDQ_AON IFPAB_RSET 2 2 2 2
1U_0402_6.3V6K
CV435
CV436
CV437
CV438
4.7U_0603_6.3V6K
BLM18PG181SN1D_0603 1 1 1 1 1 1 1 1 W30 RV548

FBVDDQ_AON
CV428
CV216
CV429
CV434
W33 AG8 RV552

FBVDDQ_AON IFPA_IOVDD AG9 1 2 @ IFP_IOVDD
IFPB_IOVDD
2 2 2 2 2 2 2 2 0_0402_5%
AF7 IFP_PLLVDD
IFPC_PLLVDD AF8 RV549 1 2 1K_0402_1%
IFPC_RSET +1.05VS_VGA
F1 AF6 IFP_IOVDD
FB_VDDQ_SENSE IFPC_IOVDD 150mA
1U_0603_10V6K
0.1U_0402_10V7K
4.7U_0805_25V6-K
+3.3V_GFX_AON +1.35VS_VGA
CV121
CV122
CV123
F2 AG7 IFP_PLLVDD 1 1 1
FB_GND_SENSE IFPD_PLLVDD AN2
LV17 NC
2 1 IFP_PLLVDD 1 2 J27 AG6 IFP_IOVDD
RV77 40.2_0402_1% FB_CAL_PD_VDDQ IFPD_IOVDD 2 2 2
BLM18PG181SN1D_0603
1 2 H27 AB8
FB_CAL_PU_GND IFPEF_PLVDD
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
CV431
CV432
CV433
4.7U_0603_6.3V6K
1 1 RV78 40.2_0402_1% AD6 RV550 1 @ 2 1K_0402_1%

IFPEF_RSET
CV430
CV217
1 1 1
1 2 H25 AC7 RV554
RV79 60.4_0402_1% FB_CAL_TERM_GND IFPE_IOVDD AC8 1 2 @ IFP_IOVDD
2 2
2 2 2
IFPF_IOVDD 0_0402_5% Place near balls
Place near balls
B B
@
CALIBRATION PIN GDDR5

FB_CAL_x_PD_VDDQ 40.2 ohm +3.3V_GFX_AON
FB_CAL_x_PU_GND 40.2 ohm
FB_CAL_xTERM_GND 60.4 ohm +3VS +3.3V_GFX_AON
+5VALW QV86
LP2301ALT1G_SOT23-3
D
3 1
RV184
+3VS
0.1U_0402_25V6
100K_0402_5%
G
2
CV363
2
1
DGPU_PWR_EN#
2
RV528
10K_0402_5%
1
D
<11> DGPU_PWR_EN 2 QV87

G DMN65D8LW-7_SOT323-3
S
3
1
RV68
100K_0402_5%
@
2
A A

N16P_Power
5 4 3 2 1
5 4 3 2 1
UV1F
Part 6 of 7
A2 D2
AA17 GND_0 GND_100 D31
AA18 GND_1 GND_101 D33
58+30%A AA20 GND_2
GND_3
GND_102
GND_103
E10
AA22 E22
AB12 GND_4 GND_104 E25
UV1G +VGA_CORE AB14 GND_5 GND_105 E5
+VGA_CORE AB16 GND_6 GND_106 E7
AB19 GND_7 GND_107 F28
Part 7 of 7 V17 AB2 GND_8 GND_108 F7
AA12 VDD_56 V18 AB21 GND_9 GND_109 G10
D
AA14
AA16
AA19
VDD_0
VDD_1
VDD_2
VDD_57
VDD_58
VDD_59
V20
V22
W12
+3VS_VGA A33
AB23
AB28
GND_10
GND_11
GND_12
GND_110
GND_111
GND_112
G13
G16
G19 D
AA21 VDD_3 VDD_60 W14 +3VS_VGA AB30 GND_13 GND_113 G2
AA23 VDD_4 VDD_61 W16 UV11 AB32 GND_14 GND_114 G22
AB13 VDD_5 VDD_62 W19 AB5 GND_15 GND_115 G25
AB15 VDD_6
VDD_7
VDD_63
VDD_64
W21 +3VS 1
VIN VOUT
7 60mil AB7 GND_16
GND_17
GND_116
GND_117
G28
AB17 W23 2 8 AC13 G3
AB18 VDD_8 VDD_65 Y13 VIN VOUT AC15 GND_18 GND_118 G30
AB20 VDD_9 VDD_66 Y15 3V3_MAIN_EN 3 6 AC17 GND_19 GND_119 G32
AB22 VDD_10 VDD_67 Y17 <22,56,57> 3V3_MAIN_EN ON CT AC18 GND_20 GND_120 G33
AC12 VDD_11 VDD_68 Y18 AA13 GND_21 GND_121 G5
AC14 VDD_12 VDD_69 Y20 4 AC20 GND_22 GND_122 G7
VDD_13 VDD_70 +5VS VBIAS 1 GND_23 GND_123
AC16 Y22 5 CV4 AC22 K2
AC19 VDD_14 VDD_71 GND 9 4.7U_0402_6.3V6M AE2 GND_24 GND_124 K28
AC21 VDD_15 GND @ AE28 GND_25 GND_125 K30
AC23 VDD_16 U1 2 AE30 GND_26 GND_126 K32
M12 VDD_17 XVDD_1 U2 AOZ1336_DFN8_2X2 AE32 GND_27 GND_127 K33
M14 VDD_18 XVDD_2 U3 AE33 GND_28 GND_128 K5
M16 VDD_19 XVDD_3 U4 AE5 GND_29 GND_129 K7
POWER
M19 VDD_20 XVDD_4 U5 AE7 GND_30 GND_130 M13
M21 VDD_21 XVDD_5 U6 AH10 GND_31 GND_131 M15
M23 VDD_22 XVDD_6 U7 AA15 GND_32 GND_132 M17
N13 VDD_23 XVDD_7 U8 AH13 GND_33 GND_133 M18
N15 VDD_24 XVDD_8 AH16 GND_34 GND_134 M20
N17 VDD_25 AH19 GND_35 GND_135 M22
N18 VDD_26 V1 AH2 GND_36 GND_136 N12
N20 VDD_27 XVDD_9 V2 AH22 GND_37 GND_137 N14
N22 VDD_28 XVDD_10 V3 AH24 GND_38 GND_138 N16
P12 VDD_29 XVDD_11 V4 AH28 GND_39 GND_139 N19
GND
P23 VDD_34 XVDD_16 AH5 GND_44 GND_144 N30
R13 VDD_35 AH7 GND_45 GND_145 N32
R15 VDD_36 W2 AJ7 GND_46 GND_146 N33
R17 VDD_37 XVDD_17 W3 AK10 GND_47 GND_147 N5
R18 VDD_38 XVDD_18 W4 AK7 GND_48 GND_148 N7
R20 VDD_39 XVDD_19 W5 AL12 GND_49 GND_149 P13
C C
R22 VDD_40 XVDD_20 W7 AL14 GND_50 GND_150 P15
T12 VDD_41 XVDD_21 W8 AL15 GND_51 GND_151 P17
T14 VDD_42 XVDD_22 AL17 GND_52 GND_152 P18
T16 VDD_43 AL18 GND_53 GND_153 P20
T19 VDD_44 Y1 AL2 GND_54 GND_154 P22
T21 VDD_45 NC Y2 AL20 GND_55 GND_155 R12
T23 VDD_46 NC Y3 AL21 GND_56 GND_156 R14
U13 VDD_47 NC Y4 AL23 GND_57 GND_157 R16
U15 VDD_48 XVDD_23 Y5 AL24 GND_58 GND_158 R19
U20 VDD_51 XVDD_26 Y8 AL30 GND_61 GND_161 T13
U22 VDD_52 XVDD_27 AL32 GND_62 GND_162 T15
V13 VDD_53 AL33 GND_63 GND_163 T17
V15 VDD_54 AA1 AL5 GND_64 GND_164 T18
VDD_55 NC AA2 AM13 GND_65 GND_165 T2
NC AA3 AM16 GND_66 GND_166 T20
NC AA5 AM22 GND_68 GND_168 AG11
NC AA7 AN1 GND_70 GND_170 T32
NC AA8 AN10 GND_71 GND_171 T5
NC AN13 GND_72 GND_172 T7
AN16 GND_73 GND_173 U12
AN19 GND_74 GND_174 U14
N116P-GX_BGA908 AN22 GND_75 GND_175 U16
@ AN25 GND_76 GND_176 U19
AN30 GND_77 GND_177 U21
+1.35VS_VGA AN34
AN4
AN7
GND_78
GND_79
GND_80
GND_178
GND_179
GND_180
U23
V12
V14
AP2 GND_81 GND_181 V16
+1.35V_VDDQ +1.35VS_VGA AP33 GND_82 GND_182 V19
+5VALW B+_BIAS QV83 B1 GND_83 GND_183 V21
AON6508_SON8-5 B10 GND_84 GND_184 V23
1 B22 GND_85 GND_185 W13
+VGA_CORE 2 B25 GND_86 GND_186 W15
1
B GND_87 GND_187 B
470K_0402_5%
@ RV529
470K_0402_5%
5 3 B28 W17
GND_88 GND_188
RV183
B31 W18
GND_89 GND_189
1
10U_0603_6.3V6M
20K_0402_5%
@ RV181
+3VALW B34 W20
1
GND_90 GND_190
CV365
1 1 B4 W22
4
GND_91 GND_191
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
1 1 1 1 1 1 1 1 1 1 1 1 1 B7 W28
2
1
GND_92 GND_192
4.7U_0603_6.3V6K
CV419
4.7U_0603_6.3V6K
CV405
4.7U_0603_6.3V6K
CV406
4.7U_0603_6.3V6K
CV407
4.7U_0603_6.3V6K
CV408
4.7U_0603_6.3V6K
CV409
22U_0805_6.3VAM
CV410
22U_0805_6.3VAM
CV411
22U_0805_6.3VAM
CV412
22U_0805_6.3VAM
CV413
22U_0805_6.3VAM
CV414
22U_0805_6.3VAM
CV415
22U_0805_6.3VAM
CV416
CV417
CV418
100K_0402_5%
+ + C10 Y12
2
GND_93 GND_193
RV182
DGPU_PWR_ON C13 Y14
2
C19 GND_94 GND_194 Y16
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 GND_95 GND_195
DMN66D0LDW-7_SOT363-6
C22 Y19
GND_96 GND_196
3
C25 Y21
2
1
GND_97 GND_197
2.2M_0402_5%
0.047U_0402_25V
1 C28 Y23
GND_98 GND_198
QV84B
RV180
CV366
C7 AH11
DGPU_PWR_ON# 5 GND_99 GND_199 C16
GND_OPT W32
2 GND_OPT
DMN66D0LDW-7_SOT363-6
DV7
2
6
NVVDD_PWR_GD 3
<56,57> NVVDD_PWR_GD
QV84A
N116P-GX_BGA908
1 2 @
2
<11,22> GPU_GC6_FB_EN
200K_0402_5%
1
1
RV209
BAT54CW-7-F SOT-323
2
A A

N16P_VGA CORE/GND
5 4 3 2 1
5 4 3 2 1
FBA_D[0..63]
<27> FBA_D[0..63] FBC_D[0..63]
<28> FBC_D[0..63]
UV1B PU for X32 mode PU for X32 mode

UV1C
Part 2 of 7
FBA_D0 L28 U30 FBA_CS#_L Part 3 of 7
FBA_D1 M29 FBA_D0 FBA_CMD0 T31 FBA_MA3_BA3_L FBA_CS#_L <27> FBC_D0 G9 D13 FBC_CS#_L
30ohms (ESR=0.01) Bead FBA_D2 L29 FBA_D1
FBA_D2
FBA_CMD1
FBA_CMD2
U29 FBA_MA2_BA0_L FBA_MA3_BA3_L
FBA_MA2_BA0_L
<27>
<27>
FBC_D1 E9 FBB_D0
FBB_D1
FBB_CMD0
FBB_CMD1
E14 FBC_MA3_BA3_L FBC_CS#_L <28>
FBC_MA3_BA3_L <28>
FBA_D3 M28 R34 FBA_MA4_BA2_L FBC_D2 G8 F14 FBC_MA2_BA0_L
D
P/N;SM010007W00 FBA_D4 N31 FBA_D3
FBA_D4
FBA_CMD3
FBA_CMD4
R33 FBA_MA5_BA1_L FBA_MA4_BA2_L
FBA_MA5_BA1_L
<27>
<27>+1.35VS_VGA
FBC_D3 F9 FBB_D2
FBB_D3
FBB_CMD2
FBB_CMD3
A12 FBC_MA4_BA2_L FBC_MA2_BA0_L
FBC_MA4_BA2_L
<28>
<28>
FBA_D5 P29 U32 FBA_WE#_L FBC_D4 F11 B12 FBC_MA5_BA1_L D
FBA_D6 R29 FBA_D5 FBA_CMD5 U33 FBA_MA7_MA8_L FBA_WE#_L <27> FBC_D5 G11 FBB_D4 FBB_CMD4 C14 FBC_WE#_L FBC_MA5_BA1_L <28>+1.35VS_VGA
FBA_D7 P28 FBA_D6 FBA_CMD6 U28 FBA_MA6_MA11_L FBA_MA7_MA8_L <27> FBC_D6 F12 FBB_D5 FBB_CMD5 B14 FBC_MA7_MA8_L FBC_WE#_L <28>
FBA_D7 FBA_CMD7 FBA_MA6_MA11_L <27> FBB_D6 FBB_CMD6 FBC_MA7_MA8_L <28>
1
+1.05VS_VGA +FB_PLLAVDD FBA_AVDD_1.05_3.3V FBA_D8 J28 V28 FBA_ABI#_L FBC_D7 G12 G15 FBC_MA6_MA11_L
FBA_D8 FBA_CMD8 FBA_ABI#_L <27> FBB_D7 FBB_CMD7 FBC_MA6_MA11_L <28>
1
FBA_D9 H29 V29 FBA_MA12_RFU_L RV95 FBC_D8 G6 F15 FBC_ABI#_L
FBA_D10 J29 FBA_D9 FBA_CMD9 V30 FBA_MA0_MA10_L FBA_MA12_RFU_L <27> FBC_D9 F5 FBB_D8 FBB_CMD8 E15 FBC_MA12_RFU_L FBC_ABI#_L <28>
10K_0402_5% RV96
300mA 1 2 +FB_PLLAVDD 1 @ 2 FBA_D11 H28 FBA_D10
FBA_D11
FBA_CMD10
FBA_CMD11
U34 FBA_MA1_MA9_L FBA_MA0_MA10_L
FBA_MA1_MA9_L
<27>
<27>
FBC_D10 E6 FBB_D9
FBB_D10
FBB_CMD9
FBB_CMD10
D15 FBC_MA0_MA10_L FBC_MA12_RFU_L
FBC_MA0_MA10_L
<28>
<28> 10K_0402_5%
22U_0805_6.3V6M~D
RV97 0_0402_1% FBA_D12 G29 U31 FBA_RAS#_L FBC_D11 F6 A14 FBC_MA1_MA9_L
2
FBA_D13 E31 FBA_D12 FBA_CMD12 V34 FBA_RST#_L FBA_RAS#_L <27> FBC_D12 F4 FBB_D11 FBB_CMD11 D14 FBC_RAS#_L FBC_MA1_MA9_L <28>
LV13 1
2
CV151 FBA_D14 E32 FBA_D13 FBA_CMD13 V33 FBA_CKE_L FBA_RST#_L <27> FBC_D13 G4 FBB_D12 FBB_CMD12 A15 FBC_RST#_L FBC_RAS#_L <28>
PBY160808T-300Y-N_2P
FBA_D15 F30 FBA_D14 FBA_CMD14 Y32 FBA_CAS#_L FBA_CKE_L <27> FBC_D14 E2 FBB_D13 FBB_CMD13 B15 FBC_CKE_L FBC_RST#_L <28>
FBA_D16 C34 FBA_D15 FBA_CMD15 AA31 FBA_CS#_H FBA_CAS#_L <27> FBC_D15 F3 FBB_D14 FBB_CMD14 C17 FBC_CAS#_L FBC_CKE_L <28>
2 FBA_D17 D32 FBA_D16 FBA_CMD16 AA29 FBA_MA3_BA3_H FBA_CS#_H <27> FBC_D16 C2 FBB_D15 FBB_CMD15 D18 FBC_CS#_H FBC_CAS#_L <28>
FBA_D18 B33 FBA_D17 FBA_CMD17 AA28 FBA_MA2_BA0_H FBA_MA3_BA3_H <27> FBC_D17 D4 FBB_D16 FBB_CMD16 E18 FBC_MA3_BA3_H FBC_CS#_H <28>
FBA_D19 C33 FBA_D18 FBA_CMD18 AC34 FBA_MA4_BA2_H FBA_MA2_BA0_H <27> FBC_D18 D3 FBB_D17 FBB_CMD17 F18 FBC_MA2_BA0_H FBC_MA3_BA3_H <28>
FBA_D20 F33 FBA_D19 FBA_CMD19 AC33 FBA_MA5_BA1_H FBA_MA4_BA2_H <27> FBC_D19 C1 FBB_D18 FBB_CMD18 A20 FBC_MA4_BA2_H FBC_MA2_BA0_H <28>
FBA_D21 F32 FBA_D20 FBA_CMD20 AA32 FBA_WE#_H FBA_MA5_BA1_H <27>+1.35VS_VGA FBC_D20 B3 FBB_D19 FBB_CMD19 B20 FBC_MA5_BA1_H FBC_MA4_BA2_H <28>
FBA_D22 H33 FBA_D21 FBA_CMD21 AA33 FBA_MA7_MA8_H FBA_WE#_H <27> FBC_D21 C4 FBB_D20 FBB_CMD20 C18 FBC_WE#_H FBC_MA5_BA1_H <28>+1.35VS_VGA
FBA_D23 H32 FBA_D22 FBA_CMD22 Y28 FBA_MA6_MA11_H FBA_MA7_MA8_H <27> FBC_D22 B5 FBB_D21 FBB_CMD21 B18 FBC_MA7_MA8_H FBC_WE#_H <28>
FBA_D23 FBA_CMD23 FBA_MA6_MA11_H <27> FBB_D22 FBB_CMD22 FBC_MA7_MA8_H <28>
1
FBA_D24 P34 Y29 FBA_ABI#_H FBC_D23 C5 G18 FBC_MA6_MA11_H
FBA_D24 FBA_CMD24 FBA_ABI#_H <27> FBB_D23 FBB_CMD23 FBC_MA6_MA11_H <28>
1
FBA_D25 P32 W31 FBA_MA12_RFU_H RV98 FBC_D24 A11 G17 FBC_ABI#_H
FBA_D26 P31 FBA_D25 FBA_CMD25 Y30 FBA_MA0_MA10_H FBA_MA12_RFU_H <27> FBC_D25 C11 FBB_D24 FBB_CMD24 F17 FBC_MA12_RFU_H FBC_ABI#_H <28>
10K_0402_5% RV99
FBA_D27 P33 FBA_D26 FBA_CMD26 AA34 FBA_MA1_MA9_H FBA_MA0_MA10_H <27> FBC_D26 D11 FBB_D25 FBB_CMD25 D16 FBC_MA0_MA10_H FBC_MA12_RFU_H <28>
10K_0402_5%
MEMORY INTERFACE B
FBA_D28 L31 FBA_D27 FBA_CMD27 Y31 FBA_RAS#_H FBA_MA1_MA9_H <27> FBC_D27 B11 FBB_D26 FBB_CMD26 A18 FBC_MA1_MA9_H FBC_MA0_MA10_H <28>
2
FBA_D29 L34 FBA_D28 FBA_CMD28 Y34 FBA_RST#_H FBA_RAS#_H <27> FBC_D28 D8 FBB_D27 FBB_CMD27 D17 FBC_RAS#_H FBC_MA1_MA9_H <28>
2
FBA_D30 L32 FBA_D29 FBA_CMD29 Y33 FBA_CKE_H FBA_RST#_H <27> FBC_D29 A8 FBB_D28 FBB_CMD28 A17 FBC_RST#_H FBC_RAS#_H <28>
FBA_D31 L33 FBA_D30 FBA_CMD30 V31 FBA_CAS#_H FBA_CKE_H <27> FBC_D30 C8 FBB_D29 FBB_CMD29 B17 FBC_CKE_H FBC_RST#_H <28>
FBA_D32 AG28 FBA_D31 FBA_CMD31 R28 FBA_CAS#_H <27> FBC_D31 B8 FBB_D30 FBB_CMD30 E17 FBC_CAS#_H FBC_CKE_H <28>
FBA_D33 AF29 FBA_D32 FBA_CMD32 AC28 FBC_D32 F24 FBB_D31 FBB_CMD31 G14 FBC_CAS#_H <28>
MEMORY INTERFACE
FBA_D34 AG29 FBA_D33 FBA_CMD33 R32 FBC_D33 G23 FBB_D32 FBB_CMD32 G20
FBA_D35 AF28 FBA_D34 FBA_CMD34 AC32 FBC_D34 E24 FBB_D33 FBB_CMD33 C12
FBA_D36 AD30 FBA_D35 FBA_CMD35 FBC_D35 G24 FBB_D34 FBB_CMD34 C20
C FBA_D37 AD29 FBA_D36 FBC_D36 D21 FBB_D35 FBB_CMD35 C
FBA_D38 AC29 FBA_D37 FBC_D37 E21 FBB_D36
FBA_D39 AD28 FBA_D38 FBC_D38 G21 FBB_D37
FBA_D40 AJ29 FBA_D39 FBC_D39 F21 FBB_D38
FBA_D41 AK29 FBA_D40 FBC_D40 G27 FBB_D39
FBA_D42 AJ30 FBA_D41 FBC_D41 D27 FBB_D40
FBA_D43 AK28 FBA_D42 FBC_D42 G26 FBB_D41
FBA_D44 AM29 FBA_D43 FBC_D43 E27 FBB_D42
FBA_D45 AM31 FBA_D44 R30 FBA_CLK0 FBC_D44 E29 FBB_D43
FBA_D46 AN29 FBA_D45 FBA_CLK0 R31 FBA_CLK0# FBA_CLK0 <27> FBC_D45 F29 FBB_D44 D12 FBC_CLK0
FBA_D47 AM30 FBA_D46 FBA_CLK0_N AB31 FBA_CLK1 FBA_CLK0# <27> FBC_D46 E30 FBB_D45 FBB_CLK0 E12 FBC_CLK0# FBC_CLK0 <28>
FBA_D48 AN31 FBA_D47 FBA_CLK1 AC31 FBA_CLK1# FBA_CLK1 <27> FBC_D47 D30 FBB_D46 FBB_CLK0_N E20 FBC_CLK1 FBC_CLK0# <28>
FBA_D49 AN32 FBA_D48 FBA_CLK1_N FBA_CLK1# <27> FBC_D48 A32 FBB_D47 FBB_CLK1 F20 FBC_CLK1# FBC_CLK1 <28>
A
FBA_D50 AP30 FBA_D49 FBC_D49 C31 FBB_D48 FBB_CLK1_N FBC_CLK1# <28>
FBA_D51 AP32 FBA_D50 FBC_D50 C32 FBB_D49
FBA_D52 AM33 FBA_D51 K31 FBA_WCK0 FBC_D51 B32 FBB_D50
FBA_D53 AL31 FBA_D52 FBA_WCK01 L30 FBA_WCK0_N FBA_WCK0 <27> FBC_D52 D29 FBB_D51 F8 FBC_WCK0
FBA_D54 AK33 FBA_D53 FBA_WCK01_N H34 FBA_WCK1 FBA_WCK0_N <27> FBC_D53 A29 FBB_D52 FBB_WCK01 E8 FBC_WCK0_N FBC_WCK0 <28>
FBA_D55 AK32 FBA_D54 FBA_WCK23 J34 FBA_WCK1_N FBA_WCK1 <27> FBC_D54 C29 FBB_D53 FBB_WCK01_N A5 FBC_WCK1 FBC_WCK0_N <28>
FBA_D56 AD34 FBA_D55 FBA_WCK23_N AG30 FBA_WCK2 FBA_WCK1_N <27> FBC_D55 B29 FBB_D54 FBB_WCK23 A6 FBC_WCK1_N FBC_WCK1 <28>
FBA_D57 AD32 FBA_D56 FBA_WCK45 AG31 FBA_WCK2_N FBA_WCK2 <27> FBC_D56 B21 FBB_D55 FBB_WCK23_N D24 FBC_WCK2 FBC_WCK1_N <28>
FBA_D58 AC30 FBA_D57 FBA_WCK45_N AJ34 FBA_WCK3 FBA_WCK2_N <27> FBC_D57 C23 FBB_D56 FBB_WCK45 D25 FBC_WCK2_N FBC_WCK2 <28>
FBA_D59 AD33 FBA_D58 FBA_WCK67 AK34 FBA_WCK3_N FBA_WCK3 <27> FBC_D58 A21 FBB_D57 FBB_WCK45_N B27 FBC_WCK3 FBC_WCK2_N <28>
FBA_D60 AF31 FBA_D59 FBA_WCK67_N FBA_WCK3_N <27> FBC_D59 C21 FBB_D58 FBB_WCK67 C27 FBC_WCK3_N FBC_WCK3 <28>
FBA_D61 AG34 FBA_D60 FBC_D60 B24 FBB_D59 FBB_WCK67_N FBC_WCK3_N <28>
FBA_D62 AG32 FBA_D61 FBC_D61 C24 FBB_D60
FBA_D63 AG33 FBA_D62 J30 FBC_D62 B26 FBB_D61
FBA_D63 NC J31 FBC_D63 C26 FBB_D62 D6
FBA_DBI0# P30 NC J32 FBB_D63 NC D7
<27> FBA_DBI0# FBA_DBI1# F31 FBA_DQM0 NC J33 FBC_DBI0# E11 NC C6
<27> FBA_DBI1# FBA_DBI2# F34 FBA_DQM1 NC AH31 <28> FBC_DBI0# FBC_DBI1# E3 FBB_DQM0 NC B6
<27> FBA_DBI2# FBA_DBI3# M32 FBA_DQM2 NC AJ31 <28> FBC_DBI1# FBC_DBI2# A3 FBB_DQM1 NC F26
B <27> FBA_DBI3# FBA_DBI4# AD31 FBA_DQM3 NC AJ32 <28> FBC_DBI2# FBC_DBI3# C9 FBB_DQM2 NC E26 FBA_AVDD_1.05_3.3V +3.3V_GFX_AON B
<27> FBA_DBI4# FBA_DBI5# AL29 FBA_DQM4 NC AJ33 <28> FBC_DBI3# FBC_DBI4# F23 FBB_DQM3 NC A26
<27> FBA_DBI5# FBA_DBI6# AM32 FBA_DQM5 NC <28> FBC_DBI4# FBC_DBI5# F27 FBB_DQM4 NC A27
<27> FBA_DBI6# FBA_DBI7# AF34 FBA_DQM6 <28> FBC_DBI5# FBC_DBI6# C30 FBB_DQM5 NC
<27> FBA_DBI7# FBA_DQM7 <28> FBC_DBI6# FBB_DQM6
1
RV104 10K_0402_5% FBC_DBI7# A24
FBA_EDC0 M31 E1 2 1 <28> FBC_DBI7# FBB_DQM7 RV210 RV211
FBA_EDC1 G31 FBA_DQS_WP0 FB_CLAMP FBC_EDC0 D10 0_0402_5% 0_0402_5%
<27> FBA_EDC[7..0] FBA_EDC2 E33 FBA_DQS_WP1
FBA_DQS_WP2
+FB_PLLAVDD
50mA FBC_EDC1 D5 FBB_DQS_WP0
FBB_DQS_WP1
@
FBA_EDC3 M33 CV152 0.1U_0402_10V7K FBC_EDC2 C3
2
FBA_EDC4 AE31 FBA_DQS_WP3 K27 1 2 <28> FBC_EDC[7..0] FBC_EDC3 B9 FBB_DQS_WP2
FBA_EDC5 AK30 FBA_DQS_WP4 FB_DLL_AVDD FBC_EDC4 E23 FBB_DQS_WP3 H17 PLL_AVDD
FBA_DQS_WP5 FBB_DQS_WP4 FBB_PLL_AVDD
0.1U_0402_10V7K
FBA_EDC6 AN33 FBC_EDC5 E28
FBA_DQS_WP6 Place close to ball FBB_DQS_WP5 120mA
CV153
FBA_EDC7 AF33 FBC_EDC6 B30 1
FBA_DQS_WP7 U27 PLL_AVDD FBC_EDC7 A23 FBB_DQS_WP6
FBA_PLL_AVDD FBB_DQS_WP7
22U_0805_6.3V6M
0.1U_0402_10V7K
M30
FBA_DQS_RN0 120mA
CV154
CV155
1U_0402_6.3V6K
H30 1 1 1 D9
FBA_DQS_RN1 FBB_DQS_RN0 2
CV156
E34 E4
M34 FBA_DQS_RN2 H26 B2 FBB_DQS_RN1
AF30 FBA_DQS_RN3 FB_VREF A9 FBB_DQS_RN2
AK31 FBA_DQS_RN4 2 2 2 D22 FBB_DQS_RN3
AM34 FBA_DQS_RN5 D28 FBB_DQS_RN4
AF32 FBA_DQS_RN6
FBA_DQS_RN7
A30 FBB_DQS_RN5
FBB_DQS_RN6
Place close to ball
B23
FBB_DQS_RN7
Place close to ball Place close to BGA
N116P-GX_BGA908
@ N116P-GX_BGA908
@
FBA_RST#_L FBC_RST#_L
FBA_RST#_H FBC_RST#_H
1
1
A A
RV107 RV108 RV110 RV111
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
2
2
N16P_MEM Interface
5 4 3 2 1
5 4 3 2 1
Memory Partition A - Lower 32 bits MF=0 MF=1

UV6 UV7
FBA_D[0..63] MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

<26> FBA_D[0..63]
FBA_EDC[7..0] A4 FBA_D0 A4 FBA_D56
<26> FBA_EDC[7..0] DQ24 DQ0 DQ24 DQ0
FBA_EDC0 C2 A2 FBA_D1 FBA_EDC7 C2 A2 FBA_D57
FBA_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D2 FBA_EDC6 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D58
FBA_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D3 FBA_EDC5 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D59
UV6 S4G@ UV7 S4G@ FBA_EDC3 R2 EDC2 EDC1 DQ27 DQ3 E4 FBA_D4 FBA_EDC4 R2 EDC2 EDC1 DQ27 DQ3 E4 FBA_D60
EDC3 EDC0 DQ28 DQ4 BYTE0 EDC3 EDC0 DQ28 DQ4 BYTE7
E2 FBA_D5 E2 FBA_D61
DQ29 DQ5 F4 FBA_D6 DQ29 DQ5 F4 FBA_D62
FBA_DBI0# D2 DQ30 DQ6 F2 FBA_D7 FBA_DBI7# D2 DQ30 DQ6 F2 FBA_D63
<26> FBA_DBI0# DBI0# DBI3# DQ31 DQ7 <26> FBA_DBI7# DBI0# DBI3# DQ31 DQ7
FBA_DBI1# D13 A11 FBA_D8 FBA_DBI6# D13 A11 FBA_D48
FBA_DBI2# P13 A13 FBA_D9 FBA_DBI5# P13 A13 FBA_D49
D K4G41325FC-HC03 K4G41325FC-HC03 FBA_DBI3# P2 B11 FBA_D10 FBA_DBI4# P2 B11 FBA_D50 D
B13 FBA_D11 BYTE1 B13 FBA_D51
SA00007D800 SA00007D800 FBA_CLK0 J12 DQ19 DQ11 E11 FBA_D12 FBA_CLK1 J12 DQ19 DQ11 E11 FBA_D52
<26> FBA_CLK0 CK DQ20 DQ12 <26> FBA_CLK1 CK DQ20 DQ12 BYTE6
FBA_CLK0# J11 E13 FBA_D13 FBA_CLK1# J11 E13 FBA_D53
<26> FBA_CLK0# CK# DQ21 DQ13 <26> FBA_CLK1# CK# DQ21 DQ13
FBA_CKE_L J3 F11 FBA_D14 FBA_CKE_H J3 F11 FBA_D54
<26> FBA_CKE_L CKE# DQ22 DQ14 <26> FBA_CKE_H CKE# DQ22 DQ14
UV8 S4G@ UV9 S4G@ F13 FBA_D15 F13 FBA_D55
DQ23 DQ15 U11 FBA_D16 DQ23 DQ15 U11 FBA_D40
FBA_MA2_BA0_L H11 DQ8 DQ16 U13 FBA_D17 FBA_MA4_BA2_H H11 DQ8 DQ16 U13 FBA_D41
<26> FBA_MA2_BA0_L BA0/A2 BA2/A4 DQ9 DQ17 <26> FBA_MA4_BA2_H BA0/A2 BA2/A4 DQ9 DQ17
FBA_MA5_BA1_L K10 T11 FBA_D18 FBA_MA3_BA3_H K10 T11 FBA_D42
FBA_MA4_BA2_L K11 T13 FBA_D19 BYTE2 FBA_MA2_BA0_H K11 T13 FBA_D43
FBA_MA3_BA3_L H10 N11 FBA_D20 FBA_MA5_BA1_H H10 N11 FBA_D44 BYTE5
K4G41325FC-HC03 K4G41325FC-HC03 N13 FBA_D21 N13 FBA_D45
DQ13 DQ21 M11 FBA_D22 DQ13 DQ21 M11 FBA_D46
SA00007D800 SA00007D800 FBA_MA7_MA8_L K4 DQ14 DQ22 M13 FBA_D23 FBA_MA0_MA10_H K4 DQ14 DQ22 M13 FBA_D47
<26> FBA_MA7_MA8_L A8/A7 A10/A0 DQ15 DQ23 <26> FBA_MA0_MA10_H A8/A7 A10/A0 DQ15 DQ23
FBA_MA1_MA9_L H5 U4 FBA_D24 FBA_MA6_MA11_H H5 U4 FBA_D32
FBA_MA0_MA10_L H4 U2 FBA_D25 FBA_MA7_MA8_H H4 U2 FBA_D33
FBA_MA6_MA11_L K5 T4 FBA_D26 FBA_MA1_MA9_H K5 T4 FBA_D34
FBA_MA12_RFU_L J5 T2 FBA_D27 BYTE3 FBA_MA12_RFU_H J5 T2 FBA_D35 BYTE4
<26> FBA_MA12_RFU_L A12/RFU/NC DQ3 DQ27 <26> FBA_MA12_RFU_H A12/RFU/NC DQ3 DQ27
N4 FBA_D28 N4 FBA_D36
A5 DQ4 DQ28 N2 FBA_D29 A5 DQ4 DQ28 N2 FBA_D37
U5 VPP/NC DQ5 DQ29 M4 FBA_D30 +1.35VS_VGA U5 VPP/NC DQ5 DQ29 M4 FBA_D38
2 RV116 1 VPP/NC DQ6 DQ30 M2 FBA_D31 2 RV117 1 VPP/NC DQ6 DQ30 M2 FBA_D39
1K_0402_1% DQ7 DQ31 1K_0402_1% DQ7 DQ31
J1 +1.35VS_VGA J1 +1.35VS_VGA
2 RV118 1 J10 MF 2 RV119 1 J10 MF
2 RV120 1 1K_0402_1% J13 SEN B1 2 RV121 1 1K_0402_1% J13 SEN B1
121_0402_1% ZQ VDDQ D1 121_0402_1% ZQ VDDQ D1
VDDQ F1 VDDQ F1
FBA_ABI#_L J4 VDDQ M1 FBA_ABI#_H J4 VDDQ M1
<26> FBA_ABI#_L ABI# VDDQ <26> FBA_ABI#_H ABI# VDDQ
FBA_RAS#_L G3 P1 FBA_CAS#_H G3 P1
<26> FBA_RAS#_L RAS# CAS# VDDQ <26> FBA_CAS#_H RAS# CAS# VDDQ
FBA_CS#_L G12 T1 FBA_WE#_H G12 T1
<26> FBA_CS#_L CS# WE# VDDQ <26> FBA_WE#_H CS# WE# VDDQ
FBA_CLK0 FBA_CAS#_L L3 G2 FBA_RAS#_H L3 G2
<26> FBA_CAS#_L CAS# RAS# VDDQ <26> FBA_RAS#_H CAS# RAS# VDDQ
FBA_WE#_L L12 L2 FBA_CS#_H L12 L2
<26> FBA_WE#_L WE# CS# VDDQ <26> FBA_CS#_H WE# CS# VDDQ
B3 B3
2
VDDQ D3 VDDQ D3
VDDQ F3 VDDQ F3
80.6_0402_1% FBA_WCK0_N D5 VDDQ H3 FBA_WCK3_N D5 VDDQ H3
RV123 <26> FBA_WCK0_N WCK01# WCK23# VDDQ <26> FBA_WCK3_N WCK01# WCK23# VDDQ
C FBA_WCK0 D4 K3 FBA_WCK3 D4 K3 C
<26> FBA_WCK0 WCK01 WCK23 VDDQ <26> FBA_WCK3 WCK01 WCK23 VDDQ
M3 M3
1
FBA_CLK0# FBA_WCK1_N P5 VDDQ P3 FBA_WCK2_N P5 VDDQ P3

<26> FBA_WCK1_N WCK23# WCK01# VDDQ <26> FBA_WCK2_N WCK23# WCK01# VDDQ
Near to VRAM FBA_WCK1 P4 T3 FBA_WCK2 P4 T3
<26> FBA_WCK1 WCK23 WCK01 VDDQ <26> FBA_WCK2 WCK23 WCK01 VDDQ
E5 E5
VDDQ N5 VDDQ N5
+FBA_VREFD_L A10 VDDQ E10 +FBA_VREFD_L A10 VDDQ E10
U10 VREFD VDDQ N10 U10 VREFD VDDQ N10
+FBA_VREFC0 J14 VREFD VDDQ B12 +FBA_VREFC0 J14 VREFD VDDQ B12
VREFC VDDQ D12 VREFC VDDQ D12
VDDQ F12 VDDQ F12
VDDQ H12 VDDQ H12
FBA_RST#_L J2 VDDQ K12 FBA_RST#_H J2 VDDQ K12
<26> FBA_RST#_L RESET# VDDQ <26> FBA_RST#_H RESET# VDDQ
M12 M12
VDDQ P12 VDDQ P12
VDDQ T12 VDDQ T12
+1.35VS_VGA VDDQ G13 VDDQ G13
H1 VDDQ L13 H1 VDDQ L13
K1 VSS VDDQ B14 K1 VSS VDDQ B14
1
B5 VSS VDDQ D14 B5 VSS VDDQ D14

RV125 G5 VSS VDDQ F14 G5 VSS VDDQ F14
549_0402_1% L5 VSS VDDQ M14 FBA_CLK1 L5 VSS VDDQ M14
T5 VSS VDDQ P14 T5 VSS VDDQ P14
RV126 VSS VDDQ VSS VDDQ
B10 T14 B10 T14
2
2
1 2 +FBA_VREFC0 D10 VSS VDDQ D10 VSS VDDQ
931_0402_1% G10 VSS G10 VSS
L10 VSS A1 80.6_0402_1% L10 VSS A1
W=16mils P10 VSS VSSQ C1 RV175 P10 VSS VSSQ C1
820P_0402_25V7
1
T10 VSS VSSQ E1 T10 VSS VSSQ E1

CV158
1
RV127 H14 VSS VSSQ N1 FBA_CLK1# H14 VSS VSSQ N1
1.33K_0402_1% K14 VSS VSSQ R1 K14 VSS VSSQ R1
+1.35VS_VGA VSS VSSQ U1 +1.35VS_VGA VSS VSSQ U1
2 VSSQ H2 Near to VRAM VSSQ H2
2
G1 VSSQ K2 G1 VSSQ K2
L1 VDD VSSQ A3 L1 VDD VSSQ A3
G4 VDD VSSQ C3 G4 VDD VSSQ C3
L4 VDD VSSQ E3 L4 VDD VSSQ E3
C5 VDD VSSQ N3 C5 VDD VSSQ N3
B VDD VSSQ VDD VSSQ B
+1.35VS_VGA R5 R3 R5 R3
C10 VDD VSSQ U3 C10 VDD VSSQ U3
R10 VDD VSSQ C4 R10 VDD VSSQ C4
1
D11 VDD VSSQ R4 D11 VDD VSSQ R4

RV128 G11 VDD VSSQ F5 G11 VDD VSSQ F5
549_0402_1% L11 VDD VSSQ M5 L11 VDD VSSQ M5
P11 VDD VSSQ F10 P11 VDD VSSQ F10
RV129 VDD VSSQ VDD VSSQ
G14 M10 G14 M10
2
1 2 +FBA_VREFD_L L14 VDD VSSQ C11 L14 VDD VSSQ C11

931_0402_1% VDD VSSQ R11 VDD VSSQ R11
VSSQ A12 VSSQ A12
VSSQ C12 VSSQ C12
820P_0402_25V7
1
D VSSQ E12 VSSQ E12

CV159
1 VSSQ VSSQ
2 RV130 N12 N12
<22> MEM_VREF VSSQ VSSQ
G 1.33K_0402_1% R12 R12
QV20 170-BALL VSSQ U12 170-BALL VSSQ U12
S
3
2N7002W-T/R7_SOT323-3 2 VSSQ H13 VSSQ H13

2
SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13

VSSQ A14 VSSQ A14
VSSQ C14 VSSQ C14
VSSQ E14 VSSQ E14
VSSQ N14 VSSQ N14
VSSQ R14 VSSQ R14
VSSQ U14 VSSQ U14
VSSQ VSSQ
H4G@ H5GC4H24MFR-T2C H4G@ H5GC4H24MFR-T2C
+1.35VS_VGA
+1.35VS_VGA
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
CV381
CV168
CV169
CV170
CV171
CV172
CV173
CV174
CV175
CV384
CV383
CV382
CV387
CV386
CV385
CV388
2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
CV373
CV160
CV161
CV162
CV163
CV164
CV165
CV166
CV167
CV375
CV374
CV376
CV378
CV377
CV379
CV380
2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A
1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2

N16P_GDDR5_A
1.0
5 4 3 2 1
5 4 3 2 1
Memory Partition A - Lower 32 bits UV8 MF=0 UV9 MF=1

MF=0 MF=1 MF=1 MF=0
FBC_D[0..63] MF=0 MF=1 MF=1 MF=0
<26> FBC_D[0..63]
A4 FBC_D56
FBC_EDC[7..0] A4 FBC_D0 FBC_EDC7 C2 DQ24 DQ0 A2 FBC_D57
<26> FBC_EDC[7..0] DQ24 DQ0 EDC0 EDC3 DQ25 DQ1
FBC_EDC0 C2 A2 FBC_D1 FBC_EDC6 C13 B4 FBC_D58
FBC_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBC_D2 FBC_EDC5 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_D59
FBC_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBC_D3 FBC_EDC4 R2 EDC2 EDC1 DQ27 DQ3 E4 FBC_D60
EDC2 EDC1 DQ27 DQ3 BYTE0 EDC3 EDC0 DQ28 DQ4 BYTE7
FBC_EDC3 R2 E4 FBC_D4 E2 FBC_D61
EDC3 EDC0 DQ28 DQ4 E2 FBC_D5 DQ29 DQ5 F4 FBC_D62
DQ29 DQ5 F4 FBC_D6 FBC_DBI7# D2 DQ30 DQ6 F2 FBC_D63
DQ30 DQ6 <26> FBC_DBI7# DBI0# DBI3# DQ31 DQ7
FBC_DBI0# D2 F2 FBC_D7 FBC_DBI6# D13 A11 FBC_D48
<26> FBC_DBI0# DBI0# DBI3# DQ31 DQ7 <26> FBC_DBI6# DBI1# DBI2# DQ16 DQ8
FBC_DBI1# D13 A11 FBC_D8 FBC_DBI5# P13 A13 FBC_D49
D FBC_DBI2# P13 A13 FBC_D9 FBC_DBI4# P2 B11 FBC_D50 D
FBC_DBI3# P2 B11 FBC_D10 B13 FBC_D51
<26> FBC_DBI3# DBI3# DBI0# DQ18 DQ10 DQ19 DQ11
FBC_CLK0 B13 FBC_D11 BYTE1 FBC_CLK1 J12 E11 FBC_D52 BYTE6
DQ19 DQ11 <26> FBC_CLK1 CK DQ20 DQ12
FBC_CLK0 J12 E11 FBC_D12 FBC_CLK1# J11 E13 FBC_D53
<26> FBC_CLK0 CK DQ20 DQ12 <26> FBC_CLK1# CK# DQ21 DQ13
FBC_CLK0# J11 E13 FBC_D13 FBC_CKE_H J3 F11 FBC_D54
<26> FBC_CLK0# <26> FBC_CKE_H
2
FBC_CKE_L J3 CK# DQ21 DQ13 F11 FBC_D14 CKE# DQ22 DQ14 F13 FBC_D55
<26> FBC_CKE_L CKE# DQ22 DQ14 DQ23 DQ15
F13 FBC_D15 U11 FBC_D40
80.6_0402_1% DQ23 DQ15 U11 FBC_D16 FBC_MA4_BA2_H H11 DQ8 DQ16 U13 FBC_D41
RV178 DQ8 DQ16 <26> FBC_MA4_BA2_H BA0/A2 BA2/A4 DQ9 DQ17
FBC_MA2_BA0_L H11 U13 FBC_D17 FBC_MA3_BA3_H K10 T11 FBC_D42
<26> FBC_MA2_BA0_L BA0/A2 BA2/A4 DQ9 DQ17 <26> FBC_MA3_BA3_H BA1/A5 BA3/A3 DQ10 DQ18
Near to VRAM FBC_MA5_BA1_L K10 T11 FBC_D18 FBC_MA2_BA0_H K11 T13 FBC_D43
<26> FBC_MA5_BA1_L <26> FBC_MA2_BA0_H
1
FBC_CLK0# FBC_MA4_BA2_L K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBC_D19 FBC_MA5_BA1_H H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 FBC_D44
<26> FBC_MA4_BA2_L BA2/A4 BA0/A2 DQ11 DQ19 <26> FBC_MA5_BA1_H BA3/A3 BA1/A5 DQ12 DQ20 BYTE5
FBC_MA3_BA3_L H10 N11 FBC_D20 BYTE2 N13 FBC_D45
<26> FBC_MA3_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 DQ13 DQ21
N13 FBC_D21 M11 FBC_D46
DQ13 DQ21 M11 FBC_D22 FBC_MA0_MA10_H K4 DQ14 DQ22 M13 FBC_D47
DQ14 DQ22 <26> FBC_MA0_MA10_H A8/A7 A10/A0 DQ15 DQ23
FBC_MA7_MA8_L K4 M13 FBC_D23 FBC_MA6_MA11_H H5 U4 FBC_D32
<26> FBC_MA7_MA8_L A8/A7 A10/A0 DQ15 DQ23 <26> FBC_MA6_MA11_H A9/A1 A11/A6 DQ0 DQ24
FBC_MA1_MA9_L H5 U4 FBC_D24 FBC_MA7_MA8_H H4 U2 FBC_D33
FBC_MA0_MA10_L H4 U2 FBC_D25 FBC_MA1_MA9_H K5 T4 FBC_D34
FBC_MA6_MA11_L K5 T4 FBC_D26 FBC_MA12_RFU_H J5 T2 FBC_D35 BYTE4
<26> FBC_MA6_MA11_L A11/A6 A9/A1 DQ2 DQ26 <26> FBC_MA12_RFU_H A12/RFU/NC DQ3 DQ27
FBC_MA12_RFU_L J5 T2 FBC_D27 BYTE3 N4 FBC_D36
<26> FBC_MA12_RFU_L A12/RFU/NC DQ3 DQ27 DQ4 DQ28
N4 FBC_D28 A5 N2 FBC_D37
A5 DQ4 DQ28 N2 FBC_D29 +1.35VS_VGA U5 VPP/NC DQ5 DQ29 M4 FBC_D38
U5 VPP/NC DQ5 DQ29 M4 FBC_D30 2 RV131 1 VPP/NC DQ6 DQ30 M2 FBC_D39
2 RV132 1 VPP/NC DQ6 DQ30 M2 FBC_D31 1K_0402_1% DQ7 DQ31
1K_0402_1% DQ7 DQ31 J1 +1.35VS_VGA
J1 +1.35VS_VGA 2 RV133 1 J10 MF
2 RV134 1 J10 MF 2 RV135 1 1K_0402_1% J13 SEN B1
2 RV136 1 1K_0402_1% J13 SEN B1 121_0402_1% ZQ VDDQ D1
121_0402_1% ZQ VDDQ D1 VDDQ F1
VDDQ F1 FBC_ABI#_H J4 VDDQ M1
VDDQ <26> FBC_ABI#_H ABI# VDDQ
FBC_ABI#_L J4 M1 FBC_CAS#_H G3 P1
<26> FBC_ABI#_L ABI# VDDQ <26> FBC_CAS#_H RAS# CAS# VDDQ
FBC_RAS#_L G3 P1 FBC_WE#_H G12 T1
<26> FBC_RAS#_L RAS# CAS# VDDQ <26> FBC_WE#_H CS# WE# VDDQ
FBC_CS#_L G12 T1 FBC_RAS#_H L3 G2
<26> FBC_CS#_L CS# WE# VDDQ <26> FBC_RAS#_H CAS# RAS# VDDQ
FBC_CAS#_L L3 G2 FBC_CLK1 FBC_CS#_H L12 L2
<26> FBC_CAS#_L CAS# RAS# VDDQ <26> FBC_CS#_H WE# CS# VDDQ
FBC_WE#_L L12 L2 B3
<26> FBC_WE#_L WE# CS# VDDQ VDDQ
B3 D3
2
VDDQ D3 VDDQ F3
VDDQ F3 FBC_WCK3_N D5 VDDQ H3
VDDQ 80.6_0402_1% <26> FBC_WCK3_N WCK01# WCK23# VDDQ
C FBC_WCK0_N D5 H3 FBC_WCK3 D4 K3 C
<26> FBC_WCK0_N WCK01# WCK23# VDDQ RV138 <26> FBC_WCK3 WCK01 WCK23 VDDQ
FBC_WCK0 D4 K3 M3
<26> FBC_WCK0 WCK01 WCK23 VDDQ VDDQ
M3 FBC_WCK2_N P5 P3
<26> FBC_WCK2_N
1
FBC_WCK1_N P5 VDDQ P3 FBC_CLK1# FBC_WCK2 P4 WCK23# WCK01# VDDQ T3
<26> FBC_WCK1_N WCK23# WCK01# VDDQ <26> FBC_WCK2 WCK23 WCK01 VDDQ
FBC_WCK1 P4 T3 E5
<26> FBC_WCK1 WCK23 WCK01 VDDQ VDDQ
E5 N5
VDDQ N5 +FBC_VREFD_H A10 VDDQ E10
+FBC_VREFD_H A10 VDDQ E10 U10 VREFD VDDQ N10
U10 VREFD VDDQ N10 +FBC_VREFC1 J14 VREFD VDDQ B12
+FBC_VREFC1 J14 VREFD VDDQ B12 VREFC VDDQ D12
VREFC VDDQ D12 VDDQ F12
VDDQ F12 VDDQ H12
VDDQ H12 FBC_RST#_H J2 VDDQ K12
VDDQ <26> FBC_RST#_H RESET# VDDQ
FBC_RST#_L J2 K12 M12
<26> FBC_RST#_L RESET# VDDQ VDDQ
M12 P12
VDDQ P12 VDDQ T12
VDDQ T12 VDDQ G13
VDDQ G13 H1 VDDQ L13
H1 VDDQ L13 K1 VSS VDDQ B14
+1.35VS_VGA K1 VSS VDDQ B14 B5 VSS VDDQ D14
B5 VSS VDDQ D14 G5 VSS VDDQ F14
G5 VSS VDDQ F14 L5 VSS VDDQ M14
1
L5 VSS VDDQ M14 T5 VSS VDDQ P14

RV140 T5 VSS VDDQ P14 B10 VSS VDDQ T14
549_0402_1% B10 VSS VDDQ T14 D10 VSS VDDQ
D10 VSS VDDQ G10 VSS
RV141 VSS VSS
G10 L10 A1
2
1 2 +FBC_VREFC1 L10 VSS A1 P10 VSS VSSQ C1

931_0402_1% P10 VSS VSSQ C1 T10 VSS VSSQ E1
820P_0402_25V7
W=16mils
1
T10 VSS VSSQ E1 H14 VSS VSSQ N1

CV177
1 VSS VSSQ VSS VSSQ

RV142 H14 N1 K14 R1
1.33K_0402_1% K14 VSS VSSQ R1 +1.35VS_VGA VSS VSSQ U1
+1.35VS_VGA VSS VSSQ U1 VSSQ H2
2 VSSQ H2 G1 VSSQ K2
2
G1 VSSQ K2 L1 VDD VSSQ A3

L1 VDD VSSQ A3 G4 VDD VSSQ C3
G4 VDD VSSQ C3 L4 VDD VSSQ E3
L4 VDD VSSQ E3 C5 VDD VSSQ N3
B VDD VSSQ VDD VSSQ B
C5 N3 R5 R3
R5 VDD VSSQ R3 C10 VDD VSSQ U3
C10 VDD VSSQ U3 R10 VDD VSSQ C4
R10 VDD VSSQ C4 D11 VDD VSSQ R4
+1.35VS_VGA D11 VDD VSSQ R4 G11 VDD VSSQ F5
G11 VDD VSSQ F5 L11 VDD VSSQ M5
L11 VDD VSSQ M5 P11 VDD VSSQ F10
1
P11 VDD VSSQ F10 G14 VDD VSSQ M10

RV143 G14 VDD VSSQ M10 L14 VDD VSSQ C11
549_0402_1% L14 VDD VSSQ C11 VDD VSSQ R11
VDD VSSQ R11 VSSQ A12
RV144 VSSQ VSSQ
A12 C12
2
1 2 +FBC_VREFD_H VSSQ C12 VSSQ E12

931_0402_1% VSSQ E12 VSSQ N12
820P_0402_25V7
1
VSSQ N12 VSSQ R12

CV178
1 VSSQ VSSQ
RV145 R12 170-BALL U12
1
D 1.33K_0402_1% 170-BALL VSSQ U12 VSSQ H13

2 VSSQ H13 SGRAM GDDR5 VSSQ K13
<22> MEM_VREF 2 VSSQ VSSQ
G SGRAM GDDR5 K13 A14
2
QV21 VSSQ A14 VSSQ C14

S
3
2N7002W-T/R7_SOT323-3 VSSQ C14 VSSQ E14

VSSQ E14 VSSQ N14
VSSQ N14 VSSQ R14
VSSQ R14 VSSQ U14
VSSQ U14 VSSQ
VSSQ H4G@ H5GC4H24MFR-T2C
H4G@ H5GC4H24MFR-T2C
+1.35VS_VGA
+1.35VS_VGA
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
CV389
CV179
CV180
CV181
CV182
CV183
CV184
CV185
CV186
CV392
CV390
CV391
CV395
CV393
CV394
CV396
2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
CV397
CV187
CV188
CV189
CV190
CV191
CV192
CV193
CV194
CV399
CV400
CV398
CV402
CV403
CV401
CV404
2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A
1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2

N16P_GDDR5_B
1.0
5 4 3 2 1
5 4 3 2 1
X7656331L01 : SAMR1@
X7656331L81 : HYNR1@
HYNR1@ SAMR1@
X7656331L05 : SAMR3@
HYNIX 2GB R1 SAMSUNG 2GB R1 X7656331L09 : HYNR3@
X7656331L81 X7656331L01
ZZZ ZZZ
D D
+3.3V_GFX_AON
HYNR3@ SAMR3@
HYNIX 2GB R3 SAMSUNG 2GB R3
2
X7656331L09 X7656331L05
RV146 RV147 RV148 RV149 RV150
ZZZ 49.9K_0402_1% 34.8K_0402_1% 10K_0402_1% 15K_0402_1% 20K_0402_1%
@ @ @ @
1
MICR3@
STRAP0
<23> STRAP0
STRAP1
<23> STRAP1
Micron 2GB R3 STRAP2
<23> STRAP2
STRAP3
<23> STRAP3
X7656331L82 STRAP4
<23> STRAP4
2
+3.3V_GFX_AON RV152 RV153 RV154 RV155 RV156
49.9K_0402_1% 34.8K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 20K_0402_1%
@ @ @ @ @
1
C C
2
2
RV157 RV158 RV159
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
@ @ @
SA00007D800 S IC D5 128M32 K4G41325FC-HC03 FBGA 170P

1
1
ROM_SI
<23>
<23>
<23>
ROM_SI
ROM_SO
ROM_SCLK
ROM_SO
ROM_SCLK
SA00007UZ1L S IC D5 128M32 EDW4032BABG-60-F-R A31!
SA00008HQ0L S IC D5 128M32/3G H5GC4H24AJR-ROC FBGA
SA00008HQ1L S IC D5 128M32/3G H5GC4H24AJR-ROC A31!
2
2
RV160 RV161 RV162
34.8K_0402_1% 4.99K_0402_1% 15K_0402_1%
@
GPU FB Memory GDDR5 ROM_SO ROM_SCLK ROM_SI STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
1
Samsung K4G41325FC-HC03
2500MHz PD PD PD PU NA NA NA NA
4.99K 4.99K 20K 49.9K
256Mx16
N16P-GX
B Hynix H5GC4H24AJR-R0C B
+3VS_VGA 2500MHz PD PD PD PU NA NA NA NA
4.99K 4.99K 34.8K 49.9K
256Mx16
1
RV167
10K_0402_5%
2
ROM_CS
<23> ROM_CS
W25X20CL 2M-Bit/256K-byte
A A

N16P_MISC
5 4 3 2 1
5 4 3 2 1
UL1
<12> PCIE_CRX_DTX_P6
2 1 PCIE_CRX_C_DTX_P6 30
TX_P VDD33
1 W=40mils +LAN_IO
CL1 0.1U_0402_16V7K~D 16
2 1 PCIE_CRX_C_DTX_N6 29 AVDD33
<12> PCIE_CRX_DTX_N6 TX_N
CL2 0.1U_0402_16V7K~D
PCIE_CTX_C_DRX_P6 35 13 +AVDDL
+LAN_IO <12> PCIE_CTX_C_DRX_P6 RX_P AVDDL 19
<12> PCIE_CTX_C_DRX_N6
PCIE_CTX_C_DRX_N6 36
RX_N
AVDDL
AVDDL
31 +DVDDL W=20mils
34
1U_0402_6.3V6K~D
0.1U_0402_16V7K~D
CLK_PCIE_P2 33 AVDDL 6
<10> CLK_PCIE_P2 REFCLK_P AVDDL_REG
1
1 1
RL1 CLK_PCIE_N2 32
<10> CLK_PCIE_N2 REFCLK_N 22 +AVDDH CL3 CL4
D 4.7K_0402_5%~D D
CLKREQ_PCIE#2 4 AVDDH 9
<10> CLKREQ_PCIE#2 CLKREQ# AVDDH_REG 2 2
2
PLT_RST# 2
<10,32,41,44> PLT_RST# PERST# 37 +DVDDL
PCIE_WAKE# 3 DVDDL_REG
<41> PCIE_WAKE# WAKE#
11 LAN_MDIP0
25 TRXP0 12 LAN_MDIN0
26 SMCLK TRXN0 14 LAN_MDIP1 close to UL1 pin37
The pull-up resisters might not be 28
27
SMDATA
NC
TRXP1
TRXN1
TRXP2
15
17
18
LAN_MDIN1
LAN_MDIP2
LAN_MDIN2
necessory due to existence 41 TESTMODE
GND
TRXN2
TRXP3
20
21
LAN_MDIP3
LAN_MDIN3
TRXN3 W=20mils
on PCH side. XTLI
XTLO
8
7 XTLI
+AVDDH
1U_0402_6.3V6K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
XTLO 40
25MHZ_10PF_7V25000014
1 2 5 LX
+LAN_IO ISOLAT# 1 1 1
RL2 30K_0402_5% 24
4
PPS CL5 CL6 CL7
LAN_ACTIVITY# 38 10 +RBIAS 1 2
GND
GND
LAN_LINK#_R 39 LED_0 RBIAS 2 2 2
LAN_LED2#_R 23 LED_1 RL3
LED_2
2
2.37K_0402_1%~D
OSC
OSC
RL4
YL1 5.1K_0402_1%~D E2400-RIV1-RL QFN 40P E-LAN CTRL
3
15P_0402_50V8J
15P_0402_50V8J
1
2 2
close to UL1 pin9 close to UL1 pin22
CL8 CL9
1 1
+3VALW
C C
W=40mils
1 1
CL40 CL41
4.7U_0805_10V4Z 0.1U_0402_16V7K
2 2
+LAN_IO 1A
UL2 +AVDDL W=20mils
1 W=40mils
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
4.7U_0603_6.3V6K~D
5 OUT
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1000P_0402_50V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
IN 2 1 1 1 1 1 1 1 1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
4 GND
CL22
EN_WOL#
<41> EN_WOL# EN 3 1 2 CL18 CL19 CL20 CL21 CL23 CL24 CL25
OCB +3VS 1 1 1 1 1 1 1
1 2 2 2 2 2 2 2 2
CL26 SY6288D20AAC_SOT23-5 RL5 CL11 CL12 CL13 CL14 CL15 CL16 CL17
0.1U_0402_16V7K 10K_0402_5%
2 2 2 2 2 2 2
2
close to UL1 pin1 close to UL1 pin16 close to UL1 pin6 close to UL1 pin34 close to UL1 pin31 close to UL1 pin13 close to UL1 pin19
@EMI@
TIMAG: S X'FORM_ IH-160 LAN,SP050006F00 CL27
0.1U_0402_16V7K~D JLAN
BOTHHAND: S X'FORM_ GST5009-D LF LAN,SP050006B00

B B
1 2 LAN_ACTIVITY# 10
Yellow LED-
+LAN_IO
2 1 9
RL8 330_0402_5% Yellow LED+
RJ45_MDI3- 8
PR4-
RJ45_MDI3+ 7
TL1 PR4+
RL9 RJ45_MDI1- 6
+VDDCT_L 1 24 RJ45_CT3 1 2 PR2-
LAN_MDIN3 2 TCT1 MCT1 23 RJ45_MDI3- 75_0402_1%~D RJ45_MDI2- 5
LAN_MDIP3 3 TD1+ MX1+ 22 RJ45_MDI3+ PR3-
TD1- MX1- RL10 RJ45_MDI2+ 4
4 21 RJ45_CT2 1 2 PR3+ 17
LAN_MDIN2 5 TCT2 MCT2 20 RJ45_MDI2- 75_0402_1%~D RJ45_MDI1+ 3 GND
LAN_MDIP2 6 TD2+ MX2+ 19 RJ45_MDI2+ PR2+ 16
TD2- MX2- RL11 RJ45_MDI0- 2 GND
7 18 RJ45_CT1 1 2 PR1- 15
LAN_MDIN1 8 TCT3 MCT3 17 RJ45_MDI1- 75_0402_1%~D RJ45_MDI0+ 1 GND
LAN_MDIP1 9 TD3+ MX3+ 16 RJ45_MDI1+ PR1+ 14
TD3- MX3- RL12 2 1 LAN_LINK# 11 GND
10 15 RJ45_CT0 1 2 EMI@ CL28 0.1U_0402_16V7K~D Green LED-
LAN_MDIN0 11 TCT4 MCT4 14 RJ45_MDI0- 75_0402_1%~D 1 2 LAN_LED2# 13
LAN_MDIP0 12 TD4+ MX4+ 13 RJ45_MDI0+ EMI@ CL29 0.1U_0402_16V7K~D Orange LED-
TD4- MX4- 1 2 12
+LAN_IO Green-Orange LED+
QL3 LL1
2 ME2N7002E1-G 1N SOT-23-3 ESD 1KV BLM15AG121SN1D_L0402_2P
350UH_GST5009-CLF EMI@ SANTA_130456-511
D
CL30 3 1 2 1 CONN@
10P_1808_3KV7K~D RL13 130_0402_1%~D 2
2
1 LAN_LED2#_R 2 1 @EMI@
RL14 130_0402_5%~D CL31
G
2
LAN_LINK#_R RL15 0.1U_0402_16V7K~D
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1000P_0402_50V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
1K_0402_1%~D 1
A A
CL32
CL33
CL34
CL35
CL36
CL37
CL38
CL39
2 1 2 1 2 1 2 1
1
+LAN_IO
1 2 1 2 1 2 1 2

LAN E2400
5 4 3 2 1
5 4 3 2 1
+3.3V_1.8V_DVDD_IO +1.8VS +5V_PVDD +5VS

CA53,CA55 change Value Line1-VREFO-L
RA29 1 2 0_0603_5% LA13 @
from 10U_0603_6.3V6M~D to 1 2 1 @ 2
RA30 1 2 0_0603_5% BLM15AG121SN1D_L0402_2P RA33 0_0603_1%
4.7U_0603_6.3V6K
1
+3VS
CA57,CA58 close +5V_PVDD +5V_PVDD
DA18 RA31 1 2 0_0603_5% +5VA +5VS
RA37 1 @ 2 0_0603_1%
to UA1 pin1 BAT54AW_SOT323-3~D
RA32 1 2 0_0603_5%
+3.3V_1.8V_DVDD CA71,CA51 place close to pin26 1 @ 2
0.1U_0402_16V7K
1 1 1 1 RA34 0_0603_1%
3
+5VA
CA54
10U_0603_6.3V6M
CA53
0.1U_0402_16V7K
CA56
10U_0603_6.3V6M
CA55
Moat
1 1
0.1U_0402_16V7K
CA58
4.7U_0603_6.3V6K
CA57
GNDA GND Moat
1
2 2 2 2
D 1 1 D
+3.3V_1.8V_DVDD
0.1U_0402_16V7K
CA51
10U_0603_6.3V6M
CA71
RA165 RA166 +1.8VS
2 2 4.7K_0402_5% +CODEC_AVDD2 +1.8VS
4.7K_0402_5%
2 2 Near to UA1 Place on the moat between GND & GNDA.
LA16 @ LA15
2
+CODEC_AVDD2 CA67 RA80 1 2 1 2
+3.3V_1.8V_DVDD_IO +3.3V_1.8V_DVDD
10U_0603_6.3V6M
4.7U_0805_25V6K 1K_0402_1% BLM15AG121SN1D_L0402_2P BLM15AG121SN1D_L0402_2P
LINE1-L 1 2 1 2 Line-IN-L +3VS
CA59,CA60 close 1
CA61
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16V7K
UA1 LINE1-R 1 2 1 2 Line-IN-R RA38 1 @ 2 0_0603_1%
to UA1 pin9 1 1 1
CA59
CA60
CA79
1 26 CA68
DVDD AVDD1 40 2 4.7U_0805_25V6K RA82
9 AVDD2 1K_0402_1%
2 2 DVDD-IO 2
36 +3VS +3VS
CPVDD 41
HDA_BIT_CLK_R 6 PVDD1 46 DA8
<9> HDA_BIT_CLK_R BCLK PVDD2
EC Beep
1
2
5
Moat RA168 1 ESD@ 2 100K_0402_5%
<41> BEEP#
<9> HDA_SDOUT_R SDATA-OUT +3.3V_1.8V_DVDD
13 JACK_SENSE# 1 2 @ 1 PC_BEEP RA36 RA175
10 HP/LINE1 JD(JD1) 14 RA171 1 2 100K_0402_5% HPOUT2-JD CA66 0.1U_0402_16V7K 10K_0402_5% 10K_0402_5%
<9> HDA_SYNC_R SYNC MIC2/LINE2 JD(JD2) 15 RA170 1 ESD@ 2 100K_0402_5% +3.3V_1.8V_DVDD MCU Beep 3
2
SPDIFO/FRONT JD(JD3)/GPIO3 <9> SPKR
1
1 2 8 CA69 1 2 0.1U_0402_16V7K 2 EAPD#
<9> HDA_SDIN0 SDATA-IN
RA130 22_0402_5% @ BAT54C-7-F_SOT23-3 @
HDA_RST#_R 11 RA19 HP_MUTE# 1
<9> HDA_RST#_R RESETB 32 HPOUT-L 10K_0402_5%
HPOUT-L(PORT-I-L) 33 HPOUT-R 3 DEPOP#_EC
2
LINE1-R 21 HPOUT-R(PORT-I-R) DEPOP#_EC <41>
HDA_BIT_CLK_R HDA_RST#_R LINE1-L 22 LINE1-R(PORT-C-R)
Line1-VREFO-R 30 LINE1-L(PORT-C-L) DA15
Line1-VREFO-L 31 LINE1-VREFO-R 42 INT-SPK-L+ BAT54AW_SOT323-3~D
LINE1-VREFO-L SPK-OUT-L+
1
1 HP2_D_R 23 43 INT-SPK-L-
RA35 CA70 HP2_D_L 24 LINE2-R(PORT-E-R) SPK-OUT-L- 45 INT-SPK-R+
33_0402_1% 0.1U_0402_16V7K LINE2-L(PORT-E-L) SPK-OUT-R+ 44 INT-SPK-R-
@EMI@ @ESD@ SPK-OUT-R-
2 16
2
MONO-OUT
1
CA21
CA70 close to UA1 pin11 2
C GPIO0/DMIC-DATA MIC_DATA <20> C
22P_0402_50V8J +MIC2-VREFO 29 3 MIC_CLK_L 1 2 MIC_CLK ESD@
+MIC2-VREFO MIC2-VREFO GPIO1/DMIC-CLK MIC_CLK <20>
@EMI@ RING2 17 48 JACK_PLUG# RA4 1 2 200K_0402_5% JACK_SENSE#
2 SLEEVE 18 MIC2-L(PORT-F-L)/RING
MIC2-R(PORT-F-R)/SLEEVE
SPDIF-OUT/GPIO2 LA1 EMI@
1
@EMI@ Close to UA1 Pin42,43,44,45
2 1 MIC1-L 19 CA24 BLM15BB221SN1D_2P CA22
CA74 MIC_CAP
CBP
37 1U_0402_6.3V6K
2
22P_0402_50V8J Reserve for cancel Delay circutis JSPK
10U_0603_6.3V6M 35 2 1 INT-SPK-R- EMI@ LA3 1 2 BLM15PX121SN1D_2P SPK_R-_CONN 1
20 CBN INT-SPK-R+ EMI@ LA4 1 2 BLM15PX121SN1D_2P SPK_R+_CONN 2 1
+3VL_RTC NC 2
INT-SPK-L- EMI@ LA5 1 2 BLM15PX121SN1D_2P SPK_L-_CONN 3
PDB 47 INT-SPK-L+ EMI@ LA6 1 2 BLM15PX121SN1D_2P SPK_L+_CONN 4 3
PDB 28 CA23 2 1 2.2U_0603_6.3V6K RA79 1K_0402_1% 4
RA167 1 ESD@ 2 100K_0402_5% VREF 12 CA65 2 1 0.1U_0402_16V7K 2 1 PC_BEEP 5
PCBEEP Trace width for SPK-L+/SPK-L-/SPK-R+/SPK-R- GND1
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
CA62 1 2 10U_0603_6.3V6M 27 34 CA25 2 1 1U_0402_6.3V6K 6
CA63 1 2 10U_0603_6.3V6M 39 LDO1-CAP CPVEE GND2
LDO2-CAP Speaker 4 ohm : 40mil 1 1 1 1
3
EMI@ CA29
EMI@ CA30
EMI@ CA31
EMI@ CA32
CA64 1 2 10U_0603_6.3V6M 7
Moat E-T_3806K-F04N-03R
LDO3-CAP
AZ5125-02S.R7G_SOT23-3
DA13
@ESD@
AZ5125-02S.R7G_SOT23-3
DA14
@ESD@
Speaker 8 ohm : 20mil CONN@
1
EAPD# 4 25 2 2 2 2
DVSS AVSS1 38 RA174 DA17
49 AVSS2 10K_0402_5% BAT54AW_SOT323-3~D
GND
2
ALC3234-CG_MQFN48_6X6 3
1
Line1-VREFO-R 1
1
RA172 RA173
+3.3V_1.8V_DVDD 4.7K_0402_5% 4.7K_0402_5%
2
1
HP2_D_R 1 2 HP2_D_R_C 1 2 HP2_D_R_R 1 @ 2 HP2_D_R1_JK
RA183 RA1 0_0603_1% 1
+
100K_0402_5% CA3 RA23
B 100U_B2_6.3VM_LESR55M 8.2_0402_5%~D CA75 B
100P_0402_50V8J~D
2
2
EC_MUTE# 1 2 PDB HP2_D_L 1 2 HP2_D_L_C 1 2 HP2_D_L_R 1 @ 2 HP2_D_L1_JK
<41> EC_MUTE#
DA19 RA2 0_0603_1% 1
2
RB751V-40_SOD323-2 CA4 RA24
AZ5125-02S.R7G_SOT23-3
DA16
ESD@
100U_B2_6.3VM_LESR55M 8.2_0402_5%~D CA76
100P_0402_50V8J~D
2
RA25
0_0402_1%
UA2
MAX9892ERT+T_UCSP6~D
Moat Re-tasking port
Headphone/Speaker Out
1
1 @ 2 A1
INL
+MIC2-VREFO HP_MUTE#
1 @ 2 A3
B1 INR +3VS /Line-In/Microphone
Universal Audio Jack(UAJ) RA26
0_0402_1%
/MUTE
B2
Headphone/Speaker Out VDD
1
2 1 B3 JHP2
RA20 RA53 SET
GND
2.2K_0402_5% 2.2K_0402_5%
/iPhone or Nokia headset/Line-In/Microphone CA77
0.01U_0402_16V7K HP2_D_L1_JK
3 G
1 L
2
A2
ESD@
SLEEVE LA7 2 1 BLM15PX330SN1D 0402 W=40mils SLEEVE_R JHP1 HPOUT2-JD 5
ESD@
RING2 RA55 LA10 2 1 BLM15PX330SN1D 0402 W=40mils RING2_R SLEEVE_R 3 G
15_0402_1% EMI@ AUD_HP_OUT_L_CN 1 L 6
HPOUT-L 1 2 Line-IN-L LA8 2 1 FBMA-L11-160808-800LMT_2P AUD_HP_OUT_L_CN
EMI@ Setting the Turn-Off Time: HP2_D_R1_JK 2 R G 7
HPOUT-R 1 2 Line-IN-R LA9 2 1 FBMA-L11-160808-800LMT_2P AUD_HP_OUT_R_CN JACK_PLUG# 5 4 M
Ton (ms) = 0.02 x Cset (pF)
RA56 SINGA_2SJ3095-063111F
15_0402_1% UA3 6 CONN@
A RA21 MAX9892ERT+T_UCSP6~D A
100_0402_1% AUD_HP_OUT_R_CN 2 R G 7
1 2 A1 RING2_R 4 M
INL
3
1 2 A3 SINGA_2SJ3095-063111F
INR
AZ5125-02S.R7G_SOT23-3
DA10
ESD@
AZ5123-02S SOT23
DA12
ESD@
HP_MUTE# RA22 B1 +3VS CONN@

100_0402_1% /MUTE
Setting the Turn-Off Time: 1 1 1 1
100P_0402_50V8J
CA39 EMI@
100P_0402_50V8J
CA33 EMI@
680P_0402_50V8J
CA38 ESD@
680P_0402_50V8J
CA40 ESD@
Change SLEEVE to Pin3, RING2 to Pin4 for Realtek's recommend at dat.04/07

B2
Ton (ms) = 0.02 x Cset (pF) 2 1 B3
SET
VDD
2 2 2 2
Moat Compal Electronics, Inc.
GND
CA78 Security Classification Compal Secret Data

0.1U_0402_16V4Z~D 2015/01/06 2016/01/06 Title
1
Audio Codec ALC3234

A2
5 4 3 2 1
5 4 3 2 1
D D
+3VS_WLAN_NGFF +5VALW
1
100K_0402_5%
RN9
100K_0402_5%~D
RN3
100K_0402_5%~D
RN6
2
2
2
G
NGFF(M.2)2230 slot(E Key) BT_LED 3 1
WLAN_LED# <38>
D
QN1
2
2N7002K_SOT23-3
G
+3VS_WLAN_NGFF
WLAN_LED 3 1
JNGFF
D
1 2
3 GND 3.3VAUX 4 QN3
<12> USB20_P8 5 USB_D+ 3.3VAUX 6 WLAN_LED 2N7002K_SOT23-3
<12> USB20_N8 7 USB_D- LED1# 8
9 GND PCM_CLK 10
11 SIDO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_IN 14
C SDO_DAT0 PCM_OUT C
15 16 BT_LED
17 SDO_DAT1 LED2# 18
19 SDO_DAT2 GND 20
21
23
SDO_DAT3
SDIO_WAKE#
SDIO_RESET#
UART_WAKE#
UART_RX
22
For EC to detect
debug card insert.
24 1 2
25 UART_TX 26
CN7 1 2 0.1U_0402_10V7K PCIE_CTX_C_DRX_P5 27 GND UART_CTS 28 RN7
<12> PCIE_CTX_DRX_P5 1 2 0.1U_0402_10V7K PCIE_CTX_C_DRX_N5 29 PETP0 UART_RTS 30 1 2
CN8 @ 100K_0402_5%
<12> PCIE_CTX_DRX_N5 31 PETN0 RESERVED 32 EC_TX <41> +3VS_WLAN_NGFF +3VS
RN11 1 @ 2 0_0402_1%
33 GND RESERVED 34 EC_RX <41>
RN12 0_0402_1%
<12>
<12>
PCIE_CRX_DTX_P5
PCIE_CRX_DTX_N5
35 PERP0
PERN0
RESERVED
COEX3
36
Prevent backdriver from +3VS_WLAN_NGFF to +3VS
1
37 38
39 GND COEX2 40 RN5
<10> CLK_PCIE_P1 REFCLKP0 COEX1
41 42 SUSCLK_R RN1 1 @ 2 0_0402_1% 10K_0402_5 QN2
<10> CLK_PCIE_N1 REFCLKN0 SUSCLK SUSCLK <10,36>
2
43 44 PLT_RST#_R RN2 1 @ 2 0_0402_1% DMN65D8LW-7_SOT323-3
G
45 GND PERST0# 46 PLT_RST# <10,30,36,41,44>
CLKREQ_PCIE#1 BT_OFF# @
2
<10> CLKREQ_PCIE#1 47 CLKEQ0# W_DISABLE2# 48 BT_OFF# <11> 1 3
WLAN_WAKE# WL_OFF#_R
<41> WLAN_WAKE# 49 PEWAKE0# W_DISABLE1# 50 WL_OFF# <11>
S
51 GND I2C_DATA 52
RSRVD/PETP1 I2C_CLK
1
53 54 1
55 RSRVD/PETN1 ALERT 56 CN9 RN14
57 GND RESERVED 58 +3VS_WLAN_NGFF 0.1U_0402_10V7K 10K_0402_5
59 RSRVD/PERP1 RESERVED 60
61 RSRVD/PERN1 RESERVED 62 2
2
GND RESERVED
1
63 64
65 RESERVED 3.3VAUX 66 RN10
67 RESERVED 3.3VAUX 10K_0402_5
GND
2
69 68
MTG77 MTG76 BT_OFF#
+5VALW CONN@ LOTES_APCI0019-P009A +3VALW +3VS_WLAN_NGFF

B B
JWDB1
1 2 2
UART_2_CTXD_DRXD 2 1
<11> UART_2_CTXD_DRXD 2
UART_2_CRXD_DTXD 3 5 CN2 CN1
<11> UART_2_CRXD_DTXD 4 3 G1 6 1U_0402_6.3V6K UN1 100U_1206_6.3V6M
4 G2 1 5 1 1
ACES_88266-04001 IN OUT
CONN@ closed to pin 2, 4 closed to pin 72,74 GND
2 +3VALW
+3VS_WLAN_NGFF +3VS_WLAN_NGFF 4 3 2 1
<41> AOAC_WLAN EN OC
SY6288C20AAC_SOT23-5 RN8
1
10K_0402_5%
22U_0603_6.3V6M~D
0.1U_0402_10V7K~D
22U_0603_6.3V6M~D
0.1U_0402_10V7K~D
1 1 1 1
RN13
CN6
CN5
CN4
CN3
100K_0402_5%
2
2 2 2 2
A A

NGFF WLAN/BT
1.0
5 4 3 2 1
5 4 3 2 1
+3VLP +3VLP +3VLP +3VLP
SDMK0340L-7-F_SOD323-2
1
1
220K_0402_5%
RU4
100K_0402_5% RU5 DU8 1
CU26
USB charge for DC S5
0.1U_0402_16V7K
2
2
5
CU27 1
P
2 1 2 NC 4
A Y USBCHG_DET_D <53>
Left side (power share)
G
D D
2.2U_0603_6.3V6K
1
UU5
3
TC7SZ14FU_SSOP5~D RU6
1M_0402_5%
+5V_USB_PWR1
+5V_USB_PWR1
2
JUSB1
LU1 EMI@ DU9 1
USB3_CTX_DRX_P1 2 1 USB3_CTX_C_DRX_P1 1 2 USB3_CTX_C_L_DRX_P1 USBCHG_DET# 2 1 USB20_N2_CONN 2 VBUS
<12> USB3_CTX_DRX_P1 USBCHG_DET_EC# <41> D-
10U_0603_6.3V6M~D
CU4 0.1U_0402_10V7K USB20_P2_CONN 3 14 1
SDMK0340L-7-F_SOD323-2 USB3_CRX_L_DTX_N2 5 D+ GND 13 CU6
1 1 SSRX- GND 1
1
47U_0805_6.3V6M~D
CU2
CU3
USB3_CTX_DRX_N1 2 1 USB3_CTX_C_DRX_N1 4 3 USB3_CTX_C_L_DRX_N1 CU28 CU29 USB3_CRX_L_DTX_P2 6 12 +
<12> USB3_CTX_DRX_N1 8 SSRX+ GND 11
CU5 0.1U_0402_10V7K 0.1U_0402_16V7K 0.1U_0402_16V7K USB3_CTX_C_L_DRX_N2 150U_B15G_6.3VM_R70M
HCM1012GD670A05P USB3_CTX_C_L_DRX_P2 9 SSTX- GND 4 @
2
2 2 USBCHG_DET# 10 SSTX+ GND 7 2 2
D1-DP GND
2
TAITW_USB011-107BRL-TW
CONN@
DU1
L30ESDL5V0C3-2_SOT23-3
LU2 EMI@ ESD@
USB3_CRX_DTX_P1 1 2 USB3_CRX_L_DTX_P1
<12> USB3_CRX_DTX_P1
+5VALW
1
USB3_CRX_DTX_N1 4 3 USB3_CRX_L_DTX_N1
<12> USB3_CRX_DTX_N1
HCM1012GD670A05P
1
CU7
Power share +5V_USB_PWR1 USB3_CRX_L_DTX_N2 1
DU2
9 USB3_CRX_L_DTX_N2
0.1U_0402_16V7K USB3_CRX_L_DTX_P2 2 8 USB3_CRX_L_DTX_P2

2 UU1
1
IN OUT
12 W=80mils USB3_CTX_C_L_DRX_N2 4 7 USB3_CTX_C_L_DRX_N2
13 9 USB3_CTX_C_L_DRX_P2 5 6 USB3_CTX_C_L_DRX_P2
<12> USB_OC1# FAULT# NC
LU3 EMI@
USB20_P1 1 2 USB20_P1_CONN USB20_N2 2 11 SW_USB20_N2
<12> USB20_P1 <12> USB20_N2 3 DM_OUT DM_IN 10
USB20_P2 SW_USB20_P2
<12> USB20_P2 DP_OUT DP_IN 3
C USB20_N1 4 3 USB20_N1_CONN RU1 1 2 10K_0402_5 4 15 RU2 2 1 19.1K_0402_1% C
<12> USB20_N1 +3VLP ILIM_SEL ILIM1
5 16 RU3 2 1 19.1K_0402_1% TVWDF1004AD0_DFN9
MCM1012B900F06BP_4P <41> PWRSHARE_EN_EC# EN ILIM0
ESD@
6
<41> CTL1 7 CTL1 14
<41> 1 CTL2 2 8 CTL2 GND 17
+3VLP CTL3 GPAD
RU7 10K_0402_5
TPS2546RTER_QFN16_3X3 +5V_USB_PWR2
Right side
47U_0805_6.3V6M~D
10U_0603_6.3V6M~D
1
1
CU10
CU11
HCM1012GD670A05P +5V_USB_PWR2
2
USB3_CTX_DRX_P2 2 1 USB3_CTX_C_DRX_P2 4 3 USB3_CTX_C_L_DRX_P2 2
<12> USB3_CTX_DRX_P2
CU12 0.1U_0402_10V7K JUSB2
1
USB3_CTX_DRX_N2 2 1 USB3_CTX_C_DRX_N2 1 2 USB3_CTX_C_L_DRX_N2 USB20_N1_CONN 2 VBUS
<12> USB3_CTX_DRX_N2 3 D-
CU13 0.1U_0402_10V7K USB20_P1_CONN
LU4 EMI@ 4 D+
+5VALW USB3_CRX_L_DTX_N1 5 GND
USB3_CRX_L_DTX_P1 6 StdA-SSRX- 10
7 StdA-SSRX+ GND1 11
USB3_CTX_C_L_DRX_N1 8 GND-DRAIN GND2 12
HCM1012GD670A05P USB3_CTX_C_L_DRX_P1 9 StdA-SSTX- GND3 13
1 1 StdA-SSTX+ GND4
USB3_CRX_DTX_P2 4 3 USB3_CRX_L_DTX_P2 CU14 CU15
<12> USB3_CRX_DTX_P2
SANTA_377175-1
4.7U_0805_10V4Z 0.1U_0402_16V7K CONN@
2
USB3_CRX_DTX_N2 1 2 USB3_CRX_L_DTX_N2 2 2 +5V_USB_PWR2
<12> USB3_CRX_DTX_N2 DU5
LU5 EMI@ UU3 USB3_CRX_L_DTX_N1 1 9 USB3_CRX_L_DTX_N1
OUT
1 W=80mils DU4
5 L30ESDL5V0C3-2_SOT23-3 USB3_CRX_L_DTX_P1 2 8 USB3_CRX_L_DTX_P1
IN 2 ESD@
USB_PWR_EN# 4 GND USB3_CTX_C_L_DRX_N1 4 7 USB3_CTX_C_L_DRX_N1
<41> USB_PWR_EN# EN 3
MCM1012B900F06BP_4P
4 3 OCB USB_OC0# <12> 5 6
SW_USB20_P2 USB20_P2_CONN 1 USB3_CTX_C_L_DRX_P1 USB3_CTX_C_L_DRX_P1
1
CU16 SY6288D20AAC_SOT23-5 1
B B
CU17
0.1U_0402_16V7K
SW_USB20_N2 1 2 USB20_N2_CONN 0.1U_0402_16V7K

2 3
LU6 EMI@ 2
TVWDF1004AD0_DFN9
ESD@
A A

USB 3.0/2.0 x2
1.0
5 4 3 2 1
5 4 3 2 1
+3V_PCIE_MUX +3V_PCIE_MUX
+3VS 1 @ 2
1U_0402_6.3V4Z~D
0.1U_0402_16V7K
0.1U_0402_16V7K
RM64 0_0603_1%
+3VALW 1 @ 2 1 1 1
CM1
CM2
CM3
RM65 0_0603_5% UM1
CM46 1 2 0.22U_0402_10V6K PEG_CRX_GTX_N0_C 1 42

<12> PCIE_CRX_GTX_N1 AI+ GND_9 2 2 2
CM47 1 2 0.22U_0402_10V6K PEG_CRX_GTX_P0_C 2 41
<12> PCIE_CRX_GTX_P1 AI- VDD_8
3 40
<35> PEG_CRX_GTX_N0_DGPU AOb+ GND_8
4 39
<35> PEG_CRX_GTX_P0_DGPU AOb- VDD_7
CM48 1 2 0.22U_0402_10V6K PEG_CRX_GTX_N3_C 5 38
<12> PCIE_CRX_GTX_N4 BI+ GND_7
CM49 1 2 0.22U_0402_10V6K PEG_CRX_GTX_P3_C 6 37
<12> PCIE_CRX_GTX_P4 BI- AOa+ PEG_CRX_GTX_N0_GPU <22>
7 36
D <35> PEG_CRX_GTX_N3_DGPU BOb+ AOa- PEG_CRX_GTX_P0_GPU <22> D
8 35
From CPU RX <12>
<35> PEG_CRX_GTX_P3_DGPU
PCIE_CRX_GTX_N3
CM50
CM51
1
1
2 0.22U_0402_10V6K
2 0.22U_0402_10V6K
PEG_CRX_GTX_N2_C
PEG_CRX_GTX_P2_C
9
10
11
BOb-
VDD_1
CI+
GND_6
VDD_6
BOa+
34
33
32
PEG_CRX_GTX_N3_GPU <22>
<12> PCIE_CRX_GTX_P3 CI- BOa- PEG_CRX_GTX_P3_GPU <22>
12 31
<35> PEG_CRX_GTX_N2_DGPU COb+ VDD_5
13 30
<12>
<12>
<35> PEG_CRX_GTX_P2_DGPU
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P2
CM52
CM53
1
1
2 0.22U_0402_10V6K
2 0.22U_0402_10V6K
PEG_CRX_GTX_N1_C
PEG_CRX_GTX_P1_C
14
15
16
COb-
DI+
DI-
SEL
GND_5
COa+
29
28
27
PEG_CRX_GTX_N2_GPU <22>
To N16P-GX TX
<35> PEG_CRX_GTX_N1_DGPU DOb+ COa- PEG_CRX_GTX_P2_GPU <22>
17 26
<35> PEG_CRX_GTX_P1_DGPU DOb- VDD_4
18 25
19 GND_1 GND_4 24
VDD_2 DOa+ PEG_CRX_GTX_N1_GPU <22>
20 23
GND_2 DOa- PEG_CRX_GTX_P1_GPU <22>
21 22
VDD_3 GND_3
43
HEATGND
Pin Number HD3SS3415 PI3PCIE3415
HD3SS3415RUAR WQFN 42P
21 NC VDD
25 NC GND
31 NC VDD
35 NC GND SEL Pin Function
39 NC VDD +3V_PCIE_MUX +3V_PCIE_MUX Low xI ---> xOa
PCIE_SEL <11>
High xI ---> xOb
2
1U_0402_6.3V4Z~D
0.1U_0402_16V7K
0.1U_0402_16V7K
1 1 1 RM34
CM4
CM5
CM6
UM2 10K_0402_5%
+3VALW
1 42
<12> PCIE_CTX_C_GRX_P1
1
AI+ GND_9 2 2 2
0.1U_0402_10V7K
2 41
<12> PCIE_CTX_C_GRX_N1 AI- VDD_8
CTX_DRX_P0 CM36 1 2 0.22U_0402_10V6K 3 40
C CTX_DRX_N0 CM37 1 2 0.22U_0402_10V6K 4 AOb+ GND_8 39 C
AOb- VDD_7 1
CM64
5 38
<12> PCIE_CTX_C_GRX_P2 BI+ GND_7
6 37 PEG_CTX_GRX_P0_GPU_C CM44 1 2 0.22U_0402_10V6K
<12> PCIE_CTX_C_GRX_N2 BI- AOa+ PEG_CTX_GRX_P0_GPU <22>
CTX_DRX_P1 CM34 1 2 0.22U_0402_10V6K 7 36 PEG_CTX_GRX_N0_GPU_C CM45 1 2 0.22U_0402_10V6K
BOb+ AOa- PEG_CTX_GRX_N0_GPU <22> 2@
CTX_DRX_N1 CM35 1 2 0.22U_0402_10V6K 8 35
From CPU TX 9 BOb-
VDD_1
GND_6
VDD_6
34
5
10 33 PEG_CTX_GRX_P1_GPU_C CM42 1 2 0.22U_0402_10V6K
<12> PCIE_CTX_C_GRX_P3 CI+ BOa+ PEG_CTX_GRX_P1_GPU <22>
11 32 PEG_CTX_GRX_N1_GPU_C CM43 1 2 0.22U_0402_10V6K 1
P
<12> PCIE_CTX_C_GRX_N3 CI- BOa- PEG_CTX_GRX_N1_GPU <22> <41> CDR_TXRX_GOOD B
CTX_DRX_P2 CM32 1 2 0.22U_0402_10V6K 12 31 4
COb+ VDD_5 O CDR_ON_ELC <37>
CTX_DRX_N2 CM33 1 2 0.22U_0402_10V6K 13 30 2
To N16P-GX RX
G
14 COb- SEL 29 A
<12> PCIE_CTX_C_GRX_P4 DI+ GND_5
15 28 PEG_CTX_GRX_P2_GPU_C CM40 1 2 0.22U_0402_10V6K UM7
<12> PCIE_CTX_C_GRX_N4 PEG_CTX_GRX_P2_GPU <22>
3
CTX_DRX_P3 CM30 1 2 0.22U_0402_10V6K 16 DI- COa+ 27 PEG_CTX_GRX_N2_GPU_C CM41 1 2 0.22U_0402_10V6K TC7SH08FU_SSOP5~D
DOb+ COa- PEG_CTX_GRX_N2_GPU <22> +3VALW
CTX_DRX_N3 CM31 1 2 0.22U_0402_10V6K 17 26
18 DOb- VDD_4 25
19 GND_1 GND_4 24 PEG_CTX_GRX_P3_GPU_C CM38 1 2 0.22U_0402_10V6K
VDD_2 DOa+ PEG_CTX_GRX_P3_GPU <22>
1
20 23 PEG_CTX_GRX_N3_GPU_C CM39 1 2 0.22U_0402_10V6K
GND_2 DOa- PEG_CTX_GRX_N3_GPU <22>
21 22
VDD_3 GND_3 RM35
43 100K_0402_5%
HEATGND JCDRA
2
1
Caldera_ON CDR_ON <41>
HD3SS3415RUAR WQFN 42P 2
Caldera_PWRGD PWGD_USBOC <41>
3 CTX_DRX_P0
T0+
1
4 CTX_DRX_N0
T0- 5 RM36
GND 6 CTX_DRX_P1 470K_0402_5%
T1+ 7 CTX_DRX_N1
T1- 8
2
GND 9 CTX_DRX_P2 +3VALW
T2+ 10 CTX_DRX_N2
T2- 11
GND 12 CTX_DRX_P3
T3+ +3VALW
0.1U_0402_10V7K
13 CTX_DRX_N3
PCIE_CLK_BUFFER +3VS
T3-
GND
R0+
14
15
CRX_DGFX_CRXP0 <35> 1 2 1
CM11
16
+3VS R0- CRX_DGFX_CRXN0 <35>
17 RM4 RM2
B GND B
0.1U_0402_10V7K
0.1U_0402_10V7K
2 1 18 10K_0402_5% 10K_0402_5%
R1+ CRX_DGFX_CRXP1 <35> 2@
CM15
CM16
1 1 19
R1- CRX_DGFX_CRXN1 <35>
5
RM18 CM17 20
2
GND
1
2.2_0402_1% 22U_0603_6.3V6M 21 1
P
CALDERA_PRSNT# CDR_PRNT# <35,37,41> B CALDERA_RST# <41>
22 CDR_RST# 4
2
PLTRST# O
1
RM19 2 2 23 2
GND A SOC_PLTRST# <10,22>
G
RM21 4.7K_0402_5% 24
R2+ CRX_DGFX_CRXP2 <35>
1K_0402_1% 25
CRX_DGFX_CRXN2 <35>
2
3
@ UM4 R2- 26 CDR_BTN# UM3
BUTTON# CDR_BTN# <41>
1 20 27 TC7SH08FU_SSOP5~D
CDR_LED_WHITE <41>
2
PLL_BW_SEL VDDA LED_WHITE
1
RM22 1 @ 2 0_0402_1% CLK+ 2 19 28
<10> CLK_PCIE_P0 SRCIN GNDA LED_RED CDR_LED_RED <41>
RM23 1 @ 2 0_0402_1% CLK- 3 18 RM24 2 1 475_0402_1% 29
<10> CLK_PCIE_N0 SRCIN# IRef GND
CLKREQ_PCIE#0 4 17 CLKREQ#_DGPU 30 RM17
<10,22> CLKREQ_PCIE#0 OE_0# OE_1# CLKREQ#_DGPU <41> R3+ CRX_DGFX_CRXP3 <35>
2 1 CLKREQ#_DGPU +3VS 5 16 +3VS CM62 31 100K_0402_5%
VDD VDD R3- CRX_DGFX_CRXN3 <35>
DM1 RB751V-40_SOD323-2 6 15 0.01U_0402_25V7K 32
2
RM37 1 @ 2 0_0402_1% CLK_N15P_C RM39 2 1 33_0402_1% CLK_PEG_N15P_R 7 GND GND 14 2 1 DGFX_CLK+_R 1 2 DGFX_CLK+ GND 33 DGFX_CLK+
<22> CLK_PEG_N15P CLK0 CLK1 REFCLK+
RM38 1 @ 2 0_0402_1% CLK_N15P#_C RM40 2 1 33_0402_1% CLK_PEG_N15P#_R 8 13 2 RM26 1 33_0402_1% DGFX_CLK-_R 1 2 DGFX_CLK- 34 DGFX_CLK-
<22> CLK_PEG_N15P# CLK0# CLK1# REFCLK-
9 12 RM27 33_0402_1% 35
VDD VDD GND
0.1U_0402_10V7K
0.1U_0402_10V7K
10 11 0.01U_0402_25V7K 36 CM9 1 2 0.1U_0402_10V6K

SDATA SCLK SSTX+ USB3_CRX_DTX_N3 <12>
1
1
1
1
CM18
CM19
49.9_0402_1%
RM41
49.9_0402_1%
RM42
49.9_0402_1%
RM28
49.9_0402_1%
RM29
1 1 CM63 37 CM10 1 2 0.1U_0402_10V6K LM1 EMI@
SSTX- USB3_CRX_DTX_P3 <12>
1U_0402_6.3V
CM20
38 3 4
GND USB20_P3 <12>
1
PI6CEQ20200LIEX_TSSOP20 39 USB20_P3_PCH
USBD+ 40 USB20_N3_PCH
2 2 USBD- 41 2 1
USB20_N3 <12>
2
2
2
2
GND 42
SSRX+ USB3_CTX_DRX_N3 <12>
43 MCM1012B900F06BP_4P
SSRX- USB3_CTX_DRX_P3 <12>
44
GND 45 CDR_I2C_CLK RM67 1 @ 2 0_0402_1%
I2C_CLK I2C_CLK <37,38,39>
46 CDR_I2C_DAT RM66 1 @ 2 0_0402_1%
I2C_DATA I2C_DAT <37,38,39>
47
GND 48
+3VS GND 49
GND 50
GND
TE_2260531-1
CONN@
2
A A
RM30 RM31
2.2K_0402_5% 2.2K_0402_5%
1
<8> SOC_SML0DATA
<8> SOC_SML0CLK
PCIE MUX/CLK_BUFFER
Size
1.0
5 4 3 2 1
5 4 3 2 1
D D
2.5VOUT
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1 1 1 1 1
CM7
CM8
CM12
CM13
CM14
2 2 2 2 2
Tie 1KΩ to VDD = Register Access SMBus Slave mode

FLOAT = Read External EEPROM (Master SMBUS Mode)
Tie 1KΩ to GND = Pin Mode
14
41
36
51
9
UM5
VDD
VDD
VDD
VDD
VDD
+3VS
CM54 1 2 0.22U_0402_10V6K PEG_CRX_GTX_P0_DGPU_C 1 45
<34> PEG_CRX_GTX_P0_DGPU OUTB_0+ INB_0+ CRX_DGFX_CRXP0 <34>
CM55 1 2 0.22U_0402_10V6K PEG_CRX_GTX_N0_DGPU_C 2 44
<34> PEG_CRX_GTX_N0_DGPU OUTB_0- INB_0- CRX_DGFX_CRXN0 <34>
2
CM61 1 2 0.22U_0402_10V6K PEG_CRX_GTX_N3_DGPU_C 8 37 RM52
1K_0402_1%
10 35
1
11 INA_0+ OUTA_0+ 34
12 INA_0- OUTA_0- 33 ENSMB
13 INA_1+ OUTA_1+ 32
INA_1- OUTA_1-
1
15 31
16 INA_2+ OUTA_2+ 30 @
17 INA_2- OUTA_2- 29 RM53
18 INA_3+ OUTA_3+ 28 1K_0402_1%
INA_3- OUTA_3-
2
C 54 DEMB1 C
EQA1 19 DEMB1/AD0 53 DEMB0
EQA0 20 EQA1 DEMB0/AD1 52 RM61 2 1 20K_0402_5%
EQA0 PRSNT CDR_PRNT# <34,37,41>
21 50 EC_SMB_CK1 <40,41,51,52>
22 RATE DEMA1/SCL 49
+3VS RXDET DEMA0/SDA EC_SMB_DA1 <40,41,51,52>
48 ENSMB
ENSMB 47 EQB1
+3VS EQB1/AD2
23 46 EQB0
W=20mils 24 LPBK
VIN
EQB0/AD3
10U_0805_10V4Z
1U_0603_10V4Z
10U_0805_10V4Z
1U_0603_10V4Z
25
1 2 VGA_EN VGA_EN 26 VDD_SEL
27 SD_TH/READ_EN 55
1 1 1 1 ALL_DONE DAP_GND
CM21
CM22
CM23
CM24
RM7
1
2
1K_0402_1%
@
RM8 2 2 2 2 RM6 DS80PCI402SQNOPB_WQFN54_10X5P5
1K_0402_1% 10K_0402_5%
2
EQ Settings DEMA Settings Level control Settings DEM*EGPU

EQA1 EQA0 dB at dB at DEMA1 DEMA0 Level Pin Setting Description Suggested Use
EQ*MB
Level EQB1 EQB0 2.5G 4G Suggested Use Level DEMB1 DEMB0 DEM dB Suggested Use 1kΩ to GND
+3VS
1 0 <5 inch 4–mil trace
1 0 0 3.7 4.9 < 5 inch trace 1 0 0 0 <5 inch 4–mil trace
20kΩ to GND RM44
2 R <5 inch 4–mil trace 1K_0402_1%
2 0 R 5.8 7.9 5 inch 5–mil trace 2 0 R 0 <5 inch 4–mil trace
Float 10 inch 4–mil trace 1 2 EQA1 1 2 EQB1 1 2 DEMB1
7.7 9.9 -3.5
3 F
B 3 0 F 5 inch 4–mil trace 3 0 F 10 inch 4–mil trace RM10 RM20 B
4 1 1kΩ to VDD <5 inch 4–mil trace
8.9 11 10 inch 5–mil trace 0 <5 inch 4–mil trace 1K_0402_1% 1K_0402_1%
4 R 1 4 0 1
5 R 0 11.2 14.3 10 inch 4–mil trace 5 R 0 -3.5 10 inch 4–mil trace
6 R R 11.4 14.6 15 inch 4–mil trace 6 R R -6 15 inch 4–mil trace
7 R F 13.5 17 20 inch 4–mil trace 7 R F 0 <5 inch 4–mil trace
8 R 1 15 18.5 25 to 30 inch 4–mil trace 8 R 1 -3.5 10 inch 4–mil trace
12.8 18 30 inch 4–mil trace -6 15 inch 4–mil trace 1 2 EQA0 1 2 EQB0
9 F 0 9 F 0
17.4 22 35 inch 4–mil trace 0 <5 inch 4–mil trace RM12 RM43 1 2 DEMB0
10 F R 10 F R 1K_0402_1% 1K_0402_1%
19.7 24.4 10m, 30awg cable -3.5 10 inch 4–mil trace RM47
11 F F 11 F F 1K_0402_1%
12 F 1 21.1 25.8 12 F 1 -6 15 inch 4–mil trace
13 1 0 21.7 27.4 13 1 0 0 <5 inch 4–mil trace
14 1 R 23.5 29.0 10m – 12m cable 14 1 R -3.5 10 inch 4–mil trace
15 1 F 25.8 31.4 15 1 F -6 15 inch 4–mil trace
16 1 1 27.3 32.7 16 1 1 -9 20 inch 4–mil trace
A A

PCIE re-driver
Size
1.0
5 4 3 2 1
A B C D E F G H
1 1
+5V_HDD
+3VS
10U_0603_25V6M
0.1U_0402_25V6K~D
1000P_0402_50V7K~D
RS2
10K_0402_5% 1 1 1
DET_SATA# port0 +5VS +5V_HDD
CS1
CS6
CS5
1
1 @ 2
<12> SATA_GP0 2 2 2
RS13 0_0201_1% @ JP1
1 @ 2 1 @ 2 1 2
<12> SATA_GP1 1 2
RS14 0_0201_1% RS3 0_0402_1%
DET_PCIE port7/8 JUMP_43X118
1
D
Reserve for Legacy SATA
QN7 2 IFDET_SATAEX1
DMN65D8LW-7_SOT323-3 G
@ S
1
RS4
20K_0402_5% JHDD
@ RS12 1 2 0_0201_5% SATA_CRX_R_DTX_P0 1
<12> SATA_CRX_DTX_P0 1
RS11 1 2 0_0201_5% SATA_CRX_R_DTX_N0 2
2
<12> SATA_CRX_DTX_N0 3 2
RS10 1 2 0_0201_5% SATA_CTX_R_DRX_P0 4 3
<12> SATA_CTX_DRX_P0 4
RS9 1 2 0_0201_5% SATA_CTX_R_DRX_N0 5
<12> SATA_CTX_DRX_N0 6 5
SATA_CRX_DTX_N1 7 6
<12> SATA_CRX_DTX_N1 8 7
SATA_CRX_DTX_P1
+3VS <12> SATA_CRX_DTX_P1 9 8
PCIE_CTX_DRX_P11 10 9
<12> PCIE_CTX_DRX_P11 10
PCIE_CTX_DRX_N11 11
<12> PCIE_CTX_DRX_N11 11
2
FFS_INT2_CONN 12
RS5 SATA_CTX_DRX_P1 13 12
2 <12> SATA_CTX_DRX_P1 13 2
10K_0402_5% SATA_CTX_DRX_N1 14
<12> SATA_CTX_DRX_N1 15 14
PCIE_CTX_DRX_N12 16 15
<12> PCIE_CTX_DRX_N12
1
PCIE_CTX_DRX_P12 17 16
<12> PCIE_CTX_DRX_P12 17
18
1 @ 2 PCIE_CRX_DTX_P11 19 18
<12> SATA_GP2 <12> PCIE_CRX_DTX_P11 20 19
RS6 0_0402_1% PCIE_CRX_DTX_N11
<12> PCIE_CRX_DTX_N11 21 20
DET_PCIE port11/12 HDD/SSD1 <12> DEVSLP1 21
1
D PCIE_CRX_DTX_P12 22
2 <12> PCIE_CRX_DTX_P12 23 22
QN6 IFDET_SATAEX2 PCIE_CRX_DTX_N12
<12> PCIE_CRX_DTX_N12 24 23
DMN65D8LW-7_SOT323-3 G
<10> CLKREQ_PCIE#3 25 24
@ S <10> CLK_PCIE_P3
3
26 25
<10> CLK_PCIE_N3 26
1
27
<10> CLKREQ_PCIE#5 28 27
RS7 <10> CLK_PCIE_P5
20K_0402_5% 29 28
<10> CLK_PCIE_N5 29
@ SSD2 <12> DEVSLP2 30
RS15 1 @ 2 0_0402_1% PCIELED# 31 30
2
<12,38> SOC_SATALED# 32 31
IFDET_SATAEX1
IFDET_SATAEX2 33 32
RS8 1 @ 2 0_0402_1% SUSCLK_HDD 34 33
<10,32> SUSCLK 35 34
<10,32,41,44> PLT_RST# 36 35 41
+5V_HDD 36 G1
37 42
38 37 G2 43
39 38 G3 44
40 39 G4 45
40 G5
+3VS STARC_111H40-100100-G7-R
Free Fall Sensor for HDD CONN@
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
1 1
DET_SATA#/PCI-E Module Type
CS7
CS2
3 3
2 2
US1 0 SATA
LNG3DM 10
1 RES 13
14 VDD_IO
VDD
RES
RES
15
16
1 PCI-E
FFS_INT1 11 RES
<8> FFS_INT1 9 INT 1 5
FFS_INT2
<8> FFS_INT2 INT 2 GND 12
7 GND
6 SDO/SA0
<8,18,19> SOC_SMBDATA 4 SDA / SDI / SDO
<8,18,19> SOC_SMBCLK SCL/SPC 2
8 NC 3
CS NC
KXCNL-1010_LGA16_3X3
+5VS
1
+3VS
@
RS1
100K_0402_5%
2
G
FFS_INT2 3 1 1 2 FFS_INT2_CONN
S
QS1 DS1
DMN65D8LW-7_SOT323-3 SDM10U45-7_SOD523-2~D
4 4

SATA HDD/M2 cards
1.0
A B C D E F G H
5 4 3 2 1
+3.3V_F383
D D
1U_0805_10V7
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
22P_0402_50V8J~D
1 1 1 2
CE1
CE2
CE3
CE4
@
+3.3V_F383
2 2 2 1 I2C_DAT 4.7K_0402_5%~D 2 1 RE2
place RE5 as close as UE1
I2C_CLK 4.7K_0402_5%~D 2 1 RE3
UE1
6 2 SPI_MOCLK 1 @ 2 SPI_MOCLK_R
VDD P0.0 1 SPI_MOSO RE5 0_0603_1%
USB20_P7 4 P0.1 32 SPI_MOSI
<12> USB20_P7 USB20_N7 5 D+ P0.2 31 SPI_MOCS#
1 2 <12> USB20_N7 D- P0.3 30
@ I2C_DAT
+5VALW P0.4 I2C_DAT <34,38,39>
RE4 0_0603_1% 7 29 I2C_CLK
+5VS
1 @ 2 W=40mils +3.3V_F383
8 REGIN
VBUS
P0.5
P0.6
28 I2C_CLK
CDR_PRNT#
<34,38,39>
<34,35,41>
RE6 0_0603_5% 27
1 2 9 P0.7 CDR_ON_ELC <34>
+3.3V_F383 RST#/C2CK
RE8 10 26 SLP_S3
P3.0/C2D P1.0
1U_0805_10V7
0.1U_0402_16V4Z~D
1 1 1K_0402_1%~D 25 BATT_CHG_LED 10K_0402_5% 2 1 RE9 +3VALW_EC
P1.1
CE6
CE7
PCIE_GEN3#_GEN2 18 24 ACIN#
AMD#_NV_R 17 P2.0 P1.2 23 LID_SW_IN#_D 2 1 LID_SW_IN#
16 P2.1 P1.3 22 BATT_LOW_LED LID_SW_IN# <38,41>
@ DE1
2 2 15 P2.2 P1.4 21 SLP_S5 SDMK0340L-7-F_SOD323-2~D
14 P2.3 P1.5 20 SLP_S4 CE8 @ 1 2 0.1U_0402_16V4Z~D
13 P2.4 P1.6 19 CE9 @ 1 2 0.1U_0402_16V4Z~D
12 P2.5 P1.7
+3.3V_F383 11 P2.6 3
P2.7 GND
JELC C8051F383-GQ_LQFP32_7X7
@
+3.3V_F383 1
1
CE13
CE14
CE15
CE16
CE17
CE18
2
2
0.1U_0402_16V4Z
3
3 4
1 4
CE10
5 1 1 1 1 1 1 UE2
5 6 SPI_MOSI 15_0402_5% 2 1 RE10 5 2 RE11 1 2 15_0402_5% SPI_MOSO
@ 6 +3.3V_F383 DI SO
2 7 SPI_MOCLK_R 15_0402_5% 2 1 RE12 6
C
GND1 8 2 2 2 2 2 2 CLK C
GND2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 2 SPI_MOCS# 1
AMPHE_G846A06201EU RE13 10K_0402_5 CS
CONN@ 1 2 7
Close to JP1 RE14 10K_0402_5 HOLD
1 2 3
RE15 10K_0402_5 WP
8 4
<41> PCIE_GEN3#_GEN2 +3.3V_F383 VCC VSS
0.1U_0402_16V4Z~D
22P_0402_50V8J~D
1 2 1 W25Q80DVSSIG_SO8
+3.3V_F383
CE19
RE21 1K_0402_1%~D 1
CE20
2
2
+3.3V_F383 +3.3V_F383
1
RE16 RE45
100K_0402_5% 100K_0402_5%
2
SLP_S3 SLP_S4 +3VALW +3.3V_F383

1 1 @
D D J1
2 1
2 2 2 1
<6,10,13,41> PM_SLP_S3# G <6,10,13,41,54> PM_SLP_S4# G
QE4 QE14 JUMP_43X118
ME2N7002E1-G 1N SOT-23-3 ESD 1KV ME2N7002E1-G 1N SOT-23-3 ESD 1KV
B B
S S
3 3
UE9
5 1
IN OUT
1 2
GND
+3.3V_F383 +3.3V_F383 CE21 4 3 1 2
EN OC +3VS
4.7U_0805_10V4Z
2 SY6288C20AAC_SOT23-5 RE19
1
10K_0402_5%
RE18 RE17
100K_0402_5% 100K_0402_5%
2
ACIN# SLP_S5
<41> 3V_F383_ON
1 1
D D
2 2
<10,22,41,51,52> ACIN G <6,10,41> PM_SLP_S5# G
QE7 QE6
S S +3.3V_F383 behavior
3 3
S0 S3 S4 S5
AC IN ON ON ON ON
BATT only ON ON OFF OFF
+3.3V_F383 +3.3V_F383
AC mode battery full in S5:turn off ELC controller
1
RE24 RE22
100K_0402_5% 100K_0402_5%
2
BATT_CHG_LED BATT_LOW_LED
1 1
A D D A
2 2
<41> BATT_CHG_LED# G <41> BATT_LOW_LED# G
QE9 QE8
S S
3 3

ELC (1)C8051F383
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
5 4 3 2 1
5 4 3 2 1
Power LED +5VS +5VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+5VALW
1 1 W=20mils
CE28
CE30
+3.3V_F383
+3.3V_F383 +3.3V_F383 +5VALW
100K_0402_5%
JSLIT
1
D 2 2 D
1
1
RE30
RE26 1 2
CE24 LID_SW 3 2
4.7K_0402_1%~D 3
UE3 0.1U_0402_16V4Z~D LOGO_LED_R_DRV# 4
4
1
3
S
4.7K_0402_1%~D
RE27
4.7K_0402_1%~D
RE28 QE10 LOGO_LED_G_DRV# 5
2
24 27 2 Power_LED
G
2 LOGO_LED_B_DRV# 6 5
RESET Vcc 7 6
3 ALIEN_LED_R_DRV# ALIEN_LED_R_DRV# 8 7
OUT0 1 8
I2C_CLK 25 4 ALIEN_LED_G_DRV# D LP2301ALT1G 1P SOT-23-3 ALIEN_LED_G_DRV# 9
2
<34,37,39> I2C_CLK 26 SCL OUT1 5

D
10 9
I2C_DAT ALIEN_LED_B_DRV# ALIEN_LED_B_DRV#
1
<34,37,39> I2C_DAT SDA OUT2 6 2 11 10
LOGO_LED_R_DRV#
31 OUT3 8 <41> PWR_LED# 12 11
AD0_UE3 LOGO_LED_G_DRV# G
AD1_UE3 32 A0 OUT4 9 LOGO_LED_B_DRV# QE11 +LED_PWR 13 12
AD2_UE3 1 A1 OUT5 10 LED_R_7313# S ME2N7002E1-G 1N SOT-23-3 ESD 1KV 14 GND
AD3_UE3 2 A2 OUT6 11 LED_G_7313# 3 GND
A3 OUT7 14 LED_B_7313# ACES_50208-01201-P01_12P
OUT8
1
1
4.7K_0402_1%~D
RE29
4.7K_0402_1%~D
RE38
12 15 PWR_R_7313# CONN@
13 N.C. OUT9 16 PWR_G_7313#
28 N.C. OUT10 17 PWR_B_7313#
29 N.C. OUT11 19 HDD_R_7313#
30 N.C. OUT12 20 HDD_G_7313#
Logic up LED board
2
N.C. OUT13 21 HDD_B_7313#

OUT14
1
22
RE37 OUT15
10K_0402_5 7 23
18 GND GND 33
GND GND
2
TLC59116FIRHBR_VQFN32_5X5
+5VALW
+5VS
1
RE34 1
100K_0402_5% CE23
0.1U_0402_16V4Z
2
LID_SW 2 JPWR
C HDD_B 1 1 C
D 2 1
+3VALW 2
3
+LED_PWR 3
3
DMN66D0LDW-7_SOT363-6~D LID_SW_IN# 2 QE12 LED_R_7313# 4
<37,41> LID_SW_IN# G LED_B_7313# 5 4
ME2N7002E1-G 1N SOT-23-3 ESD 1KV
5
QE2B
LED_G_7313# 6
5 S CAPS_LED 7 6
3 <41> CAPS_LED 8 7
WLAN_LED#
<32> WLAN_LED# 9 8
HDD_R
4
+5VS HDD_G 10 9
HDD_B_7313# HDD_B 11 10
11
100K_0402_5%
ON/OFF_BTN# 12
<41> ON/OFF_BTN# 12
1
HDD_R 13
13
RE36
@ T97 PWR_G_7313# 14
+3VS PWR_R_7313# 15 14
PTP pin define PWR_B_7313# 16 15

16
6
LID_SW_IN# 17
2
18 17
DMN66D0LDW-7_SOT363-6~D
VDD 18
1
QE2A
19
RE1 SATA_LED_ACT 2 20 19
20
@
10K_0402_5
I2C_DATA +3VS_TOUCH
CE25 1 2 1U_0402_6.3V6K~D 21
22 21
1
22
6
RE70 1 @ 2 0_0402_5% I2C_1_SDA_R 23

I2C_CLK
2
<11> I2C_1_SDA 23
HDD_R_7313# RE71 1 @ 2 0_0402_5% I2C_1_SCL_R 24
<11> I2C_1_SCL 24
QE3A
+3VS_TOUCH RE72 1 2 100K_0402_5% 25

2 HDD_G TP_INT# 26 25
<12,36> SOC_SATALED#
GND <41>
<41> TP_INT#
PTP_DISABLE#
PTP_DISABLE#
TP_DATA
27
28
26
27
1
<41> TP_DATA 28
ATTN <41> TP_CLK
TP_CLK 29
29
3
PTP_KBBL# 30
<41> PTP_KBBL# 30
+3VS_TOUCH RE73 1 2 10K_0402_5%
PTP_DISABLE#(CLOSE LID)
QE3B
31
5 32 GND
GND
PS2_DATA
4
ACES_50506-03041-P01
HDD_G_7313#
PS2_CLK CONN@
B
1
PTP_KBBL#(KB BL) B
LID_SW 2
D
QE13
NC Logic low LED board
G ME2N7002E1-G 1N SOT-23-3 ESD 1KV
S
3
+3VS_TOUCH
+3VS_TOUCH
10U_0603_6.3V6M~D
39_0402_5%~D
RT89
1
+3VALW 1 1 @ 2 +3VS
+3VALW
CT115
RT81 0_0603_1%
1
+3VLP +V_TP +3VS_TOUCH
470K_0402_5%~D
RT88
1
UT5
2 RT84 RT85
2
1 @ 2 1 7 10K_0402_5% 10K_0402_5%
+3VS VIN VOUT
2
2
RT82 0_0603_5% 2 8
2
VIN VOUT
0.1U_0402_10V6K
RK1
G
1
2
100K_0402_5% RT90 TP_EN 3 6 I2C_1_SDA 1 6 I2C_1_SDA_R

<41> TP_EN ON CT
CT110
D
2200P_0402_25V7K
8.2_0402_5%~D 1
QT2B
CT111
@ QT1B
1
5
2 1 5 4 2 DMN66D0LDW-7_SOT363-6
ON/OFF_BTN# VBIAS 5 @
G
GND 9 2 I2C_1_SCL 4 3 I2C_1_SCL_R
4
GND
D
1
6
QT1A
CK1 CT113 AOZ1336_DFN8_2X2 DMN66D0LDW-7_SOT363-6
QT2A
0.1U_0402_16V7K 0.047U_0402_25V7K
2
2 TP_EN 2
AOZ1336(SA00006U600)
1
100P_0402_50V8J~D
CT114
Remove SW2 for layout routing dat.05/06 1

A
ON/OFF switch power button 2
TPS22967(SA000070S00) A
Bottom Side pop only before MP

ELC (2)PTP/PWR SW
5 4 3 2 1
5 4 3 2 1
+5VS
1 @ 2 +5V_3V_ELC
RE7 0_0603_5%
Default use +3VS 1 @ 2
+3VS
RE20 0_0603_1%
I2C address
A3 A2 A1 A0
+5V_3V_ELC +5V_3V_ELC
UE1 (sheet 10 in Caldera board) 0 0 0 1
D +3VS +3VS D
UE4 (sheet 39) 0 0 1 0
1
RE47 KB_LED_R1 RE59 KB_LED_R3
UE3 (sheet 38) 0 0 1 1
6
39K_0402_5% 39K_0402_5%
RE46 RE58
3rd LED drive (reserve) 0 1 0 0 100K_0402_5% 100K_0402_5%
3 2
3 2
KB_LED_R1_DRV 2 KB_LED_R3_DRV 2
QE15A QE21A
2
QE15B DMN66D0LDW-7_SOT363-6~D QE21B DMN66D0LDW-7_SOT363-6~D
1
DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D
KB_LED_R1_DRV# 5 KB_LED_R3_DRV# 5
4
+3.3V_F383
+3.3V_F383
+3.3V_F383 1
+5V_3V_ELC +5V_3V_ELC
RE41 1
4.7K_0402_1%~D CE29 +3VS +3VS
1
UE4 0.1U_0402_16V4Z~D
1
RE49 KB_LED_G1 RE61 KB_LED_G3

2
6
RE40 24 27 2 39K_0402_5% 39K_0402_5%
RESET Vcc
1
4.7K_0402_1%~D
3 KB_LED_R1_DRV# RE48 RE60
3 2
3 2
I2C_CLK 25 OUT0 4 KB_LED_G1_DRV# 100K_0402_5% KB_LED_G1_DRV 2 100K_0402_5% KB_LED_G3_DRV 2
2
<34,37,38> I2C_CLK 26 SCL OUT1 5

I2C_DAT KB_LED_B1_DRV# QE16A QE22A
<34,37,38> I2C_DAT SDA OUT2 6 KB_LED_R2_DRV# QE16B DMN66D0LDW-7_SOT363-6~D QE22B DMN66D0LDW-7_SOT363-6~D
1
AD0_UE4 31 OUT3 8 KB_LED_G2_DRV#
A0 OUT4 DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D
AD1_UE4 32 9 KB_LED_B2_DRV# KB_LED_G1_DRV# 5 KB_LED_G3_DRV# 5
AD2_UE4 1 A1 OUT5 10 KB_LED_R3_DRV#
AD3_UE4 2 A2 OUT6 11 KB_LED_G3_DRV#
4
A3 OUT7 14 KB_LED_B3_DRV#
OUT8
1
1
4.7K_0402_1%~D
RE42
4.7K_0402_1%~D
RE43
4.7K_0402_1%~D
RE39
12 15 KB_LED_R4_DRV#
13 N.C. OUT9 16 KB_LED_G4_DRV#
28 N.C. OUT10 17 KB_LED_B4_DRV# +5V_3V_ELC +5V_3V_ELC
29 N.C. OUT11 19
30 N.C. OUT12 20
2
N.C. OUT13
1
21 +3VS +3VS
OUT14
1
22 RE51 KB_LED_B1 RE63 KB_LED_B3

OUT15
6
C RE44 39K_0402_5% 39K_0402_5% C
1
10K_0402_5 7 23 QE17A
18 GND GND 33 RE50 RE62
3 2
3 2
GND GND 100K_0402_5% KB_LED_B1_DRV 2 100K_0402_5% KB_LED_B3_DRV 2
2
QE23A
TLC59116FIRHBR_VQFN32_5X5 QE17B QE23B DMN66D0LDW-7_SOT363-6~D
1
DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D
KB_LED_B1_DRV# 5 KB_LED_B3_DRV# 5
4
+5V_3V_ELC
+5V_3V_ELC
+3VS
1
+3VS
1
RE65 KB_LED_R4
6
RE53 KB_LED_R2 39K_0402_5%
6
JKBBL 39K_0402_5% RE64
1 RE52 100K_0402_5%
3 2
2 1 100K_0402_5% KB_LED_R4_DRV 2
3 2
KB_LED_R1 3 2 KB_LED_R2_DRV 2 QE24A
2
KB_LED_G1 4 3 QE18A QE24B DMN66D0LDW-7_SOT363-6~D
1
KB_LED_B1 5 4 QE18B DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D
1
KB_LED_R2 6 5 KB_LED_R4_DRV# 5
6 DMN66D0LDW-7_SOT363-6~D
KB_LED_G2 7 KB_LED_R2_DRV# 5
KB_LED_B2 8 7
4
KB_LED_R3 9 8
4
KB_LED_G3 10 9
KB_LED_B3 11 10
B
KB_LED_R4 12 11 +5V_3V_ELC B
+5VS KB_LED_G4 13 12 +5V_3V_ELC
KB_LED_B4 14 13 +3VS
14
1
15 +3VS
15
1
16 RE67 KB_LED_G4
16
6
17 RE55 KB_LED_G2 39K_0402_5%
17
1
18 39K_0402_5%
18
1
19 21 RE66
3 2
20 19 GND 22 RE54 100K_0402_5% KB_LED_G4_DRV 2
3 2
20 GND 100K_0402_5% KB_LED_G2_DRV 2 QE25A
ACES_50552-02001-001 QE19A QE25B DMN66D0LDW-7_SOT363-6~D
1
CONN@ QE19B DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D
2
1
DMN66D0LDW-7_SOT363-6~D KB_LED_G4_DRV# 5
KB_LED_G2_DRV# 5
4
4
+5V_3V_ELC
+5V_3V_ELC
1
+3VS
1
+3VS RE69 KB_LED_B4
6
RE57 KB_LED_B2 39K_0402_5%
6
1
39K_0402_5% QE26A
1
RE68 DMN66D0LDW-7_SOT363-6~D
3 2
RE56 100K_0402_5% KB_LED_B4_DRV 2
3 2
100K_0402_5% KB_LED_B2_DRV 2
QE20A QE26B
1
QE20B DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D
2
DMN66D0LDW-7_SOT363-6~D KB_LED_B4_DRV# 5
KB_LED_B2_DRV# 5
4
4
A A

ELC (3)KBBL
5 4 3 2 1
5 4 3 2 1
Main:
NCT7718W(SA000067P00)
Address:1001_100xb(0x98) UF1 CPU FAN control circuit
Second: @ +3VS
ADM1032ARMZ-REEL(SA010320110) +3VS +5VS
0.1U_0402_10V7K
Address:100_1100(0x4C) ADM1032ARMZ-REEL 1
CF2
22U_0805_6.3VAM
D SA010320110 1 D
CF1
2
10K_0402_5%
10K_0402_5%
10K_0402_5%
2
2
SENSOR_DIODE_P1
2
RF1
RF2
RF3
1 1 UF1
1
@ C 1 8 EC_SMB_CK2
VDD SCL EC_SMB_CK2 <8,22,41,46>
CF3 2 CF4
100P_0402_50V8J B 470P_0402_50V7K 2 7 EC_SMB_DA2 EC_SMB_DA2 <8,22,41,46>
1
2 E QF1 2 D+ SDA
3
SENSOR_DIODE_N1 MMBT3904WT1G_SC70-3 3 6 JFAN1
D- ALERT# 1
1 2 4 5 2 1
+3VS
Diode circuit s used for skin temp sensor RF4
4.7K_0402_5%
T_CRIT# GND
NCT7718W_MSOP8
<41>
<41>
CPU_FAN_PWM
CPU_FAN_FB
2
DF1
1
SDMK0340L-7-F_SOD323-2
3
4
2
3
4
(placed near CPU). 5

6 GND1
GND2
Place CF3 close to QF1 as possible. E-T_3806K-F04N-03R
CONN@
Main:
W83L771AWG-2(SA00003PU00) GPU FAN control circuit
+3VS +5VS
Address:1001_101xb(0x9A) UF2
Second:
22U_0805_6.3VAM
1
+3VS
CF5
@
ADM1032ARMZ-2R(SA010320120)
10K_0402_5%
10K_0402_5%
10K_0402_5%
2
2
2
0.1U_0402_10V7K
RF5
RF6
RF7
Address:100_1101(0x4D) ADM1032ARMZ-2R 1
CF6
C C
SA010320120
1
2
SENSOR_DIODE_P2 JFAN2
1 1 UF2 1
1
1
@ C 1 8 EC_SMB_CK2 2
2 VDD SCLK <41> GPU_FAN_PWM 2 1 3 2
CF7 CF8
2 7 <41> GPU_FAN_FB 4 3
100P_0402_50V8J B 470P_0402_50V7K EC_SMB_DA2 DF2
2 E QF2 2 D+ SDATA SDMK0340L-7-F_SOD323-2 4
3
SENSOR_DIODE_N2 MMBT3904WT1G_SC70-3 3 6 5
D- ALERT# 6 GND1
1 2 4 5 GND2
+3VS
Diode circuit s used for skin temp sensor RF8
6.8K_0402_5%~D
THERM# GND
W83L771AWG-2_TSSOP8
E-T_3806K-F04N-03R
CONN@
(placed between DIMM1 and DIMM2).

Place CF7 close to QF2 as possible.
JTH
EC_SMB_CK1 1
<35,41,51,52> EC_SMB_CK1 2 1
EC_SMB_DA1
<35,41,51,52> EC_SMB_DA1 3 2
4 G1
G2
ACES_50271-00201-001 INT_KBD Connector
CONN@
B JKB B
30 31
KSO7 29 30 GND 32
KSO0 28 29 GND
KSI1 27 28
KSI7 26 27
KSO9 25 26
KSI6 24 25
KSI5 23 24
KSI[0..7] KSO3 22 23
<41> KSI[0..7] 21 22
KSI4
KSO[0..17] KSI2 20 21
<41> KSO[0..17] 19 20
KSO1
KSI3 18 19
KSI0 17 18
KSO13 16 17
KSO5 15 16
KSO2 14 15
KSO4 13 14
KSO8 12 13
KSO6 11 12
KSO11 10 11
KSO10 9 10
KSO12 8 9
KSO14 7 8
KSO15 6 7
KSO16 5 6
KSO17 4 5
3 4
2 3
1 2
1
ACES_50552-03001-001
CONN@
A A

FAN/KB/Thermal sensor
1.0
5 4 3 2 1
5 4 3 2 1
+3VALW
SD028000080 0_0402_5% +5VALW
Board ID SD034120280 12K_0402_1%
2
SD034150280 15K_0402_1%
1
RK3 +5VALW
Ra 100K_0402_1% SD028200280 20K_0402_1% RK5
549_0402_1%
SD034270280 27K_0402_1%
1
1
AD_BID0 RK30
SD034330280 33K_0402_1%
2
100K_0402_5%~D
EMI@ SD034430280 43K_0402_1%
3
S
LK1 +EC_VCCA
1
SD034560280 56K_0402_1%
2
+3VALW_EC FBMA-L11-160808-800LMT_0603 RK7 CK7
G
2
Rb
1 @ 2 +3VALW_EC 1 2 +EC_VCCA
43K_0402_1%
@
0.1U_0402_10V7K SD034750280 75K_0402_1% QK1
1
+3VALW
RK4 0_0603_1% 1 1 2 2
2 SD034100380 100K_0402_1% D LP2301ALT1G 1P SOT-23-3
1
D
CK3 CK2 @EMI@ @EMI@ 1 SD034130380 130K_0402_1%
1
D 0.1U_0402_10V7K 0.1U_0402_10V7K CK4 CK5 CK6 CDRA_LED WHITE_T 2 D
+3VLP
1 @ 2
2 2 1
1000P_0402_50V7K
1
1000P_0402_50V7K +3VLP 0.1U_0402_10V7K SD034160380 160K_0402_1% G
RK6 0_0603_5% RK7 QK2
2 SD034200380 200K_0402_1% S ME2N7002E1-G 1N SOT-23-3 ESD 1KV
CDR_LED_WHITE <34>
ECAGND
Pilot Build SD000001B80 240K_0402_1% 3
ID@
+3VS_WLAN_NGFF SD00000G280 270K_0402_1%
+5VALW
PLT_RST# SD034330380 330K_0402_1%
111
125
27K_0402_1%
22
33
96
67
1
SD028430380 430K_0402_1%
9
CK8 @ESD@ UK1
1
RK2 SD034270280 +5VALW
VCC0
VCC_LPC
VCC
VCC
VCC
VCC
AVCC
0.047U_0402_16V4Z 10K_0402_5% RK19
2 100_0402_1%
1
221 ohm for white LED
1
1 21 CDRA_LED WHITE_T RK12
2
<32> WLAN_WAKE# GATEA20/GPIO00 EC_VCCST_PG/GPIO0F
Place CK8 <8> EC_KBRST#
EC_KBRST#
SERIRQ
2
3 KBRST#/GPIO01 BEEP#/GPIO10
23
26
BEEP#
CPU_FAN_PWM
BEEP# <31> 316 ohm for red LED 100K_0402_5%~D
<8> SERIRQ SERIRQ EC_FAN_PWM/GPIO12 CPU_FAN_PWM <40> on dock cable side
3
S
ESPI_CS# 4 PWM Output 27 GPU_FAN_PWM
close to RC13.1
2
<8> ESPI_CS# 5 LPC_FRAME# AC_OFF/GPIO13 GPU_FAN_PWM <40> G
2
ESPI_IO3_R
<8> ESPI_IO3_R 7 LPC_AD3 2 1 100P_0402_50V8J ECAGND
@EMI@ @EMI@ ESPI_IO2_R CK11
<8> ESPI_IO2_R 8 LPC_AD2 63 ECAGND <51>
CK9 RK9 ESPI_IO1_R BATT_TEMP 1 QK3
<8> ESPI_IO1_R 10 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 64 BATT_TEMP <51,52>
0.1U_0402_10V7K 0_0402_5% ESPI_IO0_R LPC & MISC PCIE_WAKE# D LP2301ALT1G 1P SOT-23-3
2 1 1 2 <8> ESPI_IO0_R LPC_AD0 VCIN1_BATT_DROP/AD1/GPIO39 65 PCIE_WAKE# <30> D
ADP_I
1
12 ADP_I/AD2/GPIO3A 66 ADP_I <51,52> 2
ESPI_CLK_R AD Input AD_BID0 CDRA_LED RED_T
<8> ESPI_CLK_R 13 CLK_PCI_EC AD_BID/AD3/GPIO3B 75
PLT_RST# USBCHG_DET_EC# USBCHG_DET_EC# <33>
G
2 @ 1 47K_0402_5% <10,30,32,36,44> PLT_RST# 37 PCIRST#/GPIO05 AD4/GPIO42 76
+3VALW_EC RK8 EC_RST# EDP_BKLTEN EDP_BKLTEN <6> QK4
20 EC_RST# AD5/GPIO43 CDR_LED_RED <34>
EC_SCI# S ME2N7002E1-G 1N SOT-23-3 ESD 1KV
2 1 <6> EC_SCI# 38 EC_SCI#/GPIO0E 3
CK10 0.1U_0402_10V7K SLP_SUS#
<10,14> SLP_SUS# CLKRUN#/GPIO1D
@
RK8,CK10 follow Tulip BTM for 9022 setting dat.03/27 68 EN_INVPWR
DA0/GPIO3C 70 EN_INVPWR <20>
DA Output TBT_PCIE_WAKE#
+3VALW_EC 55 EN_DFAN1/DA1/GPIO3D 71 TBT_PCIE_WAKE# <44>
KSI0 SUSWARN#
56 KSI0/GPIO30 DA2/GPIO3E 72 SUSWARN# <10>
KSI1 LCD_TEST
KSI[0..7] 57 KSI1/GPIO31 DA3/GPIO3F LCD_TEST <20>
KSI2
1 2 <40> KSI[0..7] 58 KSI2/GPIO32 83
EC_ESB_CLK KSI3 EC_MUTE# VR_ON_EC +3VS_TOUCH
KSO[0..17] 59 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A 84 EC_MUTE# <31>
RK20 4.7K_0402_5% KSI4 PM_SLP_S5# 1
1 2 <40> KSO[0..17] 60 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B 85 PM_SLP_S5# <6,10,37>
EC_ESB_DAT KSI5 CDR_TXRX_GOOD @ESD@ VR_ON_EC
61 KSI5/GPIO35 PSCLK2/GPIO4C 86 CDR_TXRX_GOOD <34> 2 1
C RK22 4.7K_0402_5% KSI6 PS2 Interface SYS_PWROK CK12 TP_CLK C
62 KSI6/GPIO36 PSDAT2/GPIO4D 87 SYS_PWROK <10>
KSI7 TP_CLK TP_CLK <38> 0.1U_0402_10V7K VCCST_PG_EC 4.7K_0402_5% RK10
+3VALW_EC KSO0 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_DATA 2 TP_DATA 2 1
40 KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <38>
KSO1 4.7K_0402_5% RK11
+3VS RPK1 KSO2 41 KSO1/GPIO21
KSO2/GPIO22 Place CE12
2
5 4 EC_SMB_CK1 KSO3 42 97 SUSACK#
6 3 43 KSO3/GPIO23 ENKBL/GPXIOA00 98 SUSACK# <10>
EC_SMB_DA1 KSO4 EN_WOL# CK14
between DK1 and RK14
2
7 2 44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 EN_WOL# <30>
EC_SMB_CK2 KSO5 ME_EN 100P_0402_50V8J
8 1 EC_SMB_DA2 KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH
ME_EN <9>
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 VCIN0_PH <51>
ACIN 2 1
2.2K_0804_8P4R_5% KSO8 47 KSO7/GPIO27 VCCST_PG_EC
KSO8/GPIO28 SPI Device Interface
KSO9 48 119 PWRSHARE_EN_EC# 1
KSO9/GPIO29 MISO/GPIO5B PWRSHARE_EN_EC# <33>
1
KSO10 49 120 TP_INT# @ESD@ @ESD@
50 KSO10/GPIO2A MOSI/GPIO5C 126 TP_INT# <38>
KSO11 SPI Flash ROM CDRA_LED RED_T CK13 DK1
1
KSO12 51 KSO11/GPIO2B SPICLK/GPIO58 128 3V_F383_ON 220P_0402_50V8J L03ESDL5V0CG3-2_SOT-523-3
2 1 52 KSO12/GPIO2C SPICS#/GPIO5A 3V_F383_ON <37> 2
PM_SLP_S0# KSO13
KSO14 53 KSO13/GPIO2D @ESD@
CK21 @ESD@ KSO15 54 KSO14/GPIO2E 73 VR_PWRGD PCH_PWROK 1 2
0.1U_0402_10V7K KSO16 81 KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 74 CDR_BTN#
VR_PWRGD <58>
Place CK13 CK19 0.1U_0402_10V7K
KSO17 82 KSO16/GPIO48
KSO17/GPIO49
SYS_PWROK/AD7/GPIO41
GPIO50
89 PD_IRQ#
CDR_BTN#
PD_IRQ#
<34>
<46> between DK1 and UK1 Place DK1 close to UK1 @ESD@
2 1 PM_SLP_S5# 90 BATT_CHG_LED# SYS_PWROK 1 2
BATT_CHG_LED#/GPIO52 91 BATT_CHG_LED# <37>
CAPS_LED CK20 0.1U_0402_10V7K
77 CAPS_LED#/GPIO53 92 CAPS_LED <38>
CK17 @ESD@ EC_SMB_CK1 GPIO PWR_LED#
<35,40,51,52> EC_SMB_CK1 78 EC_SMB_CLK1/GPIO44 PWR_LED#/GPIO54 93 PWR_LED# <38>
0.1U_0402_10V7K EC_SMB_DA1 BATT_LOW_LED# BATT_LOW_LED# <37>
<35,40,51,52> EC_SMB_DA1 79 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55 95
EC_SMB_CK2 SYSON
2 1 <8,22,40,46> EC_SMB_CK2 80 EC_SMB_CLK2/GPIO46 SYSON/GPIO56 121 1 2 SYSON <13,54>
PM_SLP_S3# EC_SMB_DA2 IMVP_VR_ON @ VR_ON_EC
<8,22,40,46> EC_SMB_DA2 EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 127 VR_ON_EC <10>
RK14 0_0402_1%
DPWROK_EC/GPIO59 DPWROK_EC <10> 1
Place CK17,CK19,CK20 close to UK1
2
CK15 @ESD@ SM Bus CK16
0.1U_0402_10V7K RK15 0.1U_0402_10V7K
PM_SLP_S3# 6 100 EC_RSMRST# 10K_0402_5% +3VS +3VS
2 1 <6,10,13,37> PM_SLP_S3# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 EC_RSMRST# <6,10> 2
PM_SLP_S4# PM_SLP_S4# PCIE_GEN3#_GEN2 @
<6,10,13,37,54> PM_SLP_S4# GPIO07 GPXIOA04 PCIE_GEN3#_GEN2 <37>
2
EC_SMI#_R 15 102 VCIN1_PH
1
16 GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05 103 VCIN1_PH <51> 1 2
CK18 @ESD@ PS_ID VCOUT1_PH @ RK32
<51> PS_ID GPIO0A VCOUT1_PROCHOT#/GPXIOA06
2
0.1U_0402_10V7K EC_ESB_CLK 17 104 VCOUT0_PH# RK16 10K_0402_5% 10K_0402_5%
18 GPIO0B VCOUT0_MAIN_PWR_ON/GPXIOA07 105 VCOUT0_PH# <53>
EC_ESB_DAT BKOFF#
G
Please close to EC CLKREQ#_DGPU 19 GPIO0C
GPIO GPO
BKOFF#/GPXIOA08 106 PBTN_OUT#
BKOFF# <20>
1
25 AC_PRESENT/GPIO0D GPXIOA09 107 1 PBTN_OUT#
2 <6,10> 1 3
WAKE_PCH# TP_INT#
<10> WAKE_PCH# 28 PWM2/GPIO11 PCH_PWR_EN/GPXIOA10 108 PCH_PWR_EN <14,56> +3VS PCH_TP_INT# <6>
CPU_FAN_FB RK17 43_0402_1%
S
B <40> CPU_FAN_FB FAN_SPEED1/GPIO14 PWR_VCCST_PG/GPXIOA11 CDR_ON <34> B
1 @ 2 EC_SMI#_R GPU_FAN_FB 29 QK5
<11> EC_SMI# <40> GPU_FAN_FB 30 FANFB1/GPIO15 +3VALW
RK40 0_0402_5% <32> EC_TX EC_TX 2N7002K_SOT23-3
1 2 EC_RX 31 EC_TX/GPIO16 110 ACIN GPU_ALERT# RK28 2 1 10K_0402_5% 1 @ 2
<44> TBT_RESET_N_EC <32> EC_RX EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01 ACIN <10,22,37,51,52>
2
RK41 0_0402_5% PCH_PWROK 32 112 EC_ON RC157 100K_0402_5%
<10> PCH_PWROK 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 EC_ON <53>
PM_SLP_S0# ON/OFF_BTN# GPU_OVERT# RK29 2 1 10K_0402_5% RK37
<6,10> PM_SLP_S0#
1 2 PM_CLKRUN#_R 36 SUSP_LED#/GPIO19 ON/OFF#/GPXIOD03 115 ON/OFF_BTN# <38>
GPI LID_SW_IN# 10K_0402_5%
2 1 <8> PM_CLKRUN# NUM_LED#/GPIO1A LID_SW#/GPXIOD04 116 LID_SW_IN# <37,38>
@ PCH_PWROK RK38 @ 0_0402_5% SUSP# @
1 2 SUSP#/GPXIOD05 117 SUSP# <13,42,44>
RK18 10K_0402_5% USB_PWR_EN#
1
<42> DSW_EN GPXIOD06 118 1 USB_PWR_EN#
2 <33> 1 2
RK39 0_0402_5% PECI_EC PWGD_USBOC @ PWGD_USBOC_EC
122 PECI/GPXIOD07 H_PECI <6> <34> PWGD_USBOC
+1.0V_PGOOD RK21 43_0402_1% RK36 0_0402_1%
<55> +1.0V_PGOOD PBTN_OUT#/GPIO5D
1
VCCST_PG_EC 123 124 +V18R 1 @ 2 D
<10> VCCST_PG_EC PM_SLP_S4#/GPIO5E V18R/VCC_IO2 +3VALW_EC
RK31 0_0402_1% 2 QK6
AGND
G 2N7002KW_SOT323-3
Not support 1.8V
GND
GND
GND
GND
GND
+3VALW_EC UK2 @
EC_ESB_CLK 1 13 S
3
KB9022QD_LQFP128_14X14 ESB_CLK TEST_EN#
11
24
35
94
113
69
1
+3VALW_EC DEPOP#_EC 2 14
<31> DEPOP#_EC GPIO00 GPIO08/CAS_DAT TP_EN <38>
RM1 LK2
47K_0402_5%
100K_0402_5%~D ECAGND 2 1 RST# 3 15 PWGD_USBOC_EC

RST# GPIO09
1
FBMA-L11-160808-800LMT_0603
EC_ESB_DAT 4 16
W=20mils
RK27
2
ESB_DAT GPIO0A CALDERA_RST# <34>

CLKREQ#_DGPU 5 17
CLKREQ#_DGPU <34> <34,35,37> CDR_PRNT# GPIO01 GPIO0B PTP_KBBL# <38>
2
M_THERMAL# 6 18 GPU_ALERT#
1 2 <18,19> M_THERMAL# GPIO02 GPIO0C/PWM0 GPU_ALERT# <22>
@ RST#
<58> VR_HOT#
RK25 0_0402_1%
ME_FWP PCH has internal 20K pulldown <33> CTL1
7
GPIO03 GPIO0D/PWM1
19 TS_EN
TS_EN <20>
.1U_0402_16V7K~D
+3VS 8 20 AOAC_WLAN
(suspend power rail) 2 <33> CTL2 GPIO04 GPIO0E/PWM2 AOAC_WLAN <32>
CK26
9 21 GPU_OVERT#
<22> GPU_PWR_LEVEL GPIO05 GPIO0F/PWM3 GPU_OVERT# <22>
1
1 @ 2 H_PROCHOT# <6,51,52> ME_EN

RK35 RK34 0_0402_5% 1 DBC_EN 10 22 PD_PWR_EN
<20> DBC_EN GPIO06 GPIO10/ESB_RUN# PD_PWR_EN <11,46>
1
10K_0402_5% @
RK24 11 23
<38> PTP_DISABLE# GPIO07/CAS_CLK GPIO11/BaseAddOpt
1
RK23 D 1K_0402_5%
W=60mils
2
VCOUT1_PH 1 2 2 QV8 +3VS 12 24
GND
A GND VCC +3VALW_EC A
G 2N7002KW_SOT323-3
2
0.1U_0402_16V4Z
2
60.4K_0402_1% 1 1
CK25
RK33 S RK26 KC3810_QFN24_4X4
3
25
100K_0402_5% CK27 10K_0402_5%
@ 0.033U_0402_16V
2 2
Reserve for abnormal shutdown

1
M_THERMAL#
1 2 EC_RSMRST#
<51,53> POK
DK3 RB751V-40_SOD323-2 Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 PCH_PWROK
DK2 RB751V-40_SOD323-2
EC ENE-KB9022/KC3810
1.0
5 4 3 2 1
A B C D E
1
+5VS and +3VS switch +3VALW TO +3VALW_DSW
1
RO9 1 @ 2 0_0805_5%
+5VALW +5VS
@ +5VALW +3VALW +3VALW_DSW

UO3 J510 UO4
1 14 5VS 2 1
2 VIN1 VOUT1 13 2 1 1 7
VIN1 VOUT1 VIN VOUT
CO11
10U_0805_10V4Z
CO12
10U_0603_6.3V6M
RO7 CO10 JUMP_43X79 2 8
<13,41,44> SUSP#
SUSP# W=10mils 1 2 82K_0402_5% 5VS_GATE 3
ON1 CT1
12 1 2 220P_0402_50V8J 1 1
VIN VOUT
@ 3 6
2200P_0402_25V7K
4 11 <41> DSW_EN ON CT
0.1U_0402_10V6K
RO8 VBIAS GND CO13 @ 1 1
2 2
CO23
CO22
1 2 470K_0402_5% 3VS_GATE 5 10 1 2 220P_0402_50V8J 4
ON2 CT2 @ VBIAS 5
6 9 3VS GND 9 @ @
1 VIN2 VOUT2 GND
1
CO14 CO15 +3VALW 7 8 2 2
VIN2 VOUT2
0.01U_0603_25V7K
0.01U_0603_25V7K
15 +3VS TPS22967DSGR_SON8_2X2
2
2
GPAD @
AOZ1331 DFN 14P DUAL LOAD SW J511 For Test,
2 1 APE8937(SA000070L00) CT pin use 2200pf for
2 1 AOZ1336(SA00006U600)
TPS22967(SA000070S00) soft start tuning
CO16
10U_0603_6.3V6M
CO17
10U_0603_6.3V6M
JUMP_43X79
+3VALW +5VALW
1 1
@
2 2
CO18
10U_0603_6.3V6M
CO19
10U_0603_6.3V6M
CO20
10U_0603_6.3V6M
CO21
10U_0603_6.3V6M
2 2
1 1 1 1
2 2 2 2
3 3
+5VALW
+0.675VS_VTT
1
1
RO5 RO3
22_0603_5% 100K_0402_5%
2
SUSP
1 2
1
D D
2 SUSP SUSP# 2 QO2
G G 2N7002K_SOT23-3
S QO1 S
1
2N7002K_SOT23-3
3
RO6
100K_0402_5%
2
For Intel S3 power reduction
4 4

DC/DC Interface
1.0
A B C D E
5 4 3 2 1
Screw Hole
H8 H10 H12 H13 H14 H15 H16 H17 H18 H19 H21
H_3P0 H_3P0 H_3P0 H_3P0 H_2P9 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
@ @ @ @ @ @ @ @ @ @ @
1
D D
Echo MLK delete H24,H25
H9 H28
H_2P7X3P0 H_3P0
@ @
1
Add H28,H29 for USB3.1 type C
H11 H29
H_2P7 H_3P3
@ @
1
1
H20
H_3P2
@
1
C C
H26
H_3P5
@
1
H22
H_3P0
@
1
H23
H_2P7X3P2
@
1
H27
H_5P0N
@
1
H1 H2 H3 H4
H_3P8 H_4P4X3P8 H_4P4X3P8 H_4P2
@ @ @ @
CPU bracket
1
B B
H5 H6 H7
H_4P4X3P8 H_4P4X3P8 H_3P8
@ @ @
GPU bracket
1
FD1 FD2 FD3 FD4

@ FIDUCAL @ FIDUCIAL @ FIDUCAL @ FIDUCIAL
FIDUCIAL MARK
1
A A

Screw Hole
1.0
5 4 3 2 1
5 4 3 2 1
UT1
S IC DSL6340 SLKYB B0 FC-CSP I/O CONTROL

SA000090N0L UT1A
ARES2R1@ 0.22U_0201_6.3V6M 2 1 TBT@ CT3 PCIE_CTX_C_DRX_P10 Y23 V23 PCIE_CRX_C_DTX_P100.22U_0201_6.3V6M 2 1 TBT@ CT14
<12> PCIE_CTX_DRX_P10 PCIE_RX0_P PCIE_TX0_P PCIE_CRX_DTX_P10 <12>
0.22U_0201_6.3V6M 2 1 TBT@ CT15 PCIE_CTX_C_DRX_N10 Y22 V22 PCIE_CRX_C_DTX_N100.22U_0201_6.3V6M 2 1 TBT@ CT16
<12> PCIE_CTX_DRX_N10 PCIE_RX0_N PCIE_TX0_N PCIE_CRX_DTX_N10 <12>
UT1 PCIE X2 Bus
(Link to CPU Port 9~10) 0.22U_0201_6.3V6M 2 1 TBT@ CT1 PCIE_CTX_C_DRX_P9 T23 P23 PCIE_CRX_C_DTX_P9 0.22U_0201_6.3V6M 2 1 TBT@ CT12
<12> PCIE_CTX_DRX_P9 PCIE_RX1_P PCIE_TX1_P PCIE_CRX_DTX_P9 <12>
PCIe GEN3
0.22U_0201_6.3V6M 2 1 TBT@ CT13 PCIE_CTX_C_DRX_N9 T22 P22 PCIE_CRX_C_DTX_N9 0.22U_0201_6.3V6M 2 1 TBT@ CT2
<12> PCIE_CTX_DRX_N9 PCIE_RX1_N PCIE_TX1_N PCIE_CRX_DTX_N9 <12>
M23 K23
M22 PCIE_RX2_P PCIE_TX2_P K22
PCIE_RX2_N PCIE_TX2_N
D S IC A31 DSL6340 QSCX B0 THUNDERBOLT D
SA000090N2L H23 F23
ARQSR1@ H22 PCIE_RX3_P PCIE_TX3_P F22
PCIE_RX3_N PCIE_TX3_N
UT1 PCIE CLK V19 L4 TBT_RST#_R RT1 2 MP@ 1 0_0201_5%
<10> CLK_PCIE_P4 PCIE_REFCLK_100_IN_P PERST_N PLT_RST# <10,30,32,36,41>
(From PCH CLKOUT4) T19
<10> CLK_PCIE_N4 2 1 AC5 PCIE_REFCLK_100_IN_N N16 PCIE_RBIAS 1 TBT@ 2 3.01K_0201_1%
CLKREQ_PCIE#4 @ CLKREQ_PCIE#4_R RT3
<10> CLKREQ_PCIE#4 PCIE_CLKREQ_N PCIE_RBIAS
RT2 0_0201_5%
<6> SOC_DP1_P0 CT6 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP1_P0_C AB7 R2
CT7 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP1_N0_C AC7 DPSNK0_ML0_P DPSRC_ML0_P R1
S IC DSL6340 SLL42 B1 FCCSP 337P THUNDERBOLT A31 !
<6> SOC_DP1_N0 DPSNK0_ML0_N DPSRC_ML0_N Closed to UT1 +3.3V_TBT_SX
SA000090N5L <6> SOC_DP1_P1 CT8 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP1_P1_C AB9 N2
ARQSR3@ CT9 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP1_N1_C AC9 DPSNK0_ML1_P DPSRC_ML1_P N1 TBT_I2C_SDA RT26 2 TBT@ 1 3.3K_0201_5%
SOURCE PORT 0
<6> SOC_DP1_N1 DPSNK0_ML1_N DPSRC_ML1_N TBT_I2C_SCL RT27 2 TBT@ 1 3.3K_0201_5%
SINK PORT 0
<6> SOC_DP1_P2 CT10 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP1_P2_C AB11 L2 TBT_PCIE_WAKE_N RT28 2 TBT@ 1 10K_0201_5%
CT23 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP1_N2_C AC11 DPSNK0_ML2_P DPSRC_ML2_P L1 TBT_CIO_PLUG_EVENT# RT29 2 TBT@ 1 10K_0201_5%
<6> SOC_DP1_N2 DPSNK0_ML2_N DPSRC_ML2_N SUSP#_R RT30 2 @ 1 10K_0201_5%
CPU DDI1 <6> SOC_DP1_P3 CT11 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP1_P3_C AB13 J2 BATLOW# RT31 2 TBT@ 1 10K_0201_5%
CT24 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP1_N3_C AC13 DPSNK0_ML3_P DPSRC_ML3_P J1 TBTA_I2C_INT RT32 2 TBT@ 1 10K_0201_5%
+3VS_TBT <6> SOC_DP1_N3 DPSNK0_ML3_N DPSRC_ML3_N
Reserve for common DP design TBTB_I2C_INT RT33 2 TBT@ 1 10K_0201_5%
CT25 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP1_AUXP_C Y11 W19 TBT_RESET_N RT80 2 TBT@ 1 10K_0201_5%
<6> SOC_DP1_AUXP DPSNK0_AUX_P DPSRC_AUX_P
CT26 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP1_AUXN_C W11 Y19 NC_B4 RT86 2 @ 1 10K_0201_5%
<6> SOC_DP1_AUXN DPSNK0_AUX_N DPSRC_AUX_N
CPU_DP1_AUXN_C RT76 1 @ 2 100K_0201_5% TBT_FORCE_PWR_R RT94 2 @ 1 10K_0201_5%
CPU_DP2_AUXN_C RT77 1 @ 2 100K_0201_5% AA2 G1 TBT_SRC_HPD RT4 1 TBT@ 2 1M_0201_1%
<6> SOC_DP1_HPD DPSNK0_HPD DPSRC_HPD
CPU_DP1_AUXP_C RT78 1 @ 2 100K_0201_5%
CPU_DP2_AUXP_C RT79 1 @ 2 100K_0201_5% SOC_DP1_CTRL_CLK Y5 N6 DPSRC_RBIAS RT5 1 TBT@ 2 14K_0402_1%
<6> SOC_DP1_CTRL_CLK DPSNK0_DDC_CLK DPSRC_RBIAS
CLKREQ_PCIE#4 RT24 1 TBT@ 2 10K_0201_5% SOC_DP1_CTRL_DATA R4
<6> SOC_DP1_CTRL_DATA DPSNK0_DDC_DATA U1 TBT_I2C_SDA <46>
CT27 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP2_P0_C AB15 GPIO_0 U2
<6> SOC_DP2_P0 DPSNK1_ML0_P GPIO_1 TBT_I2C_SCL <46>
CT28 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP2_N0_C AC15 V1 TBT_EE_WP_N
LC GPIO
<6> SOC_DP2_N0 DPSNK1_ML0_N GPIO_2 V2 TBT_TMU_CLK_OUT @ T1
CT29 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP2_P1_C AB17 GPIO_3 W1 TBT_PCIE_WAKE_N RT10 1 MP@ 2 0_0201_5% KB9022
+3.3V_LC +3.3V_LC <6> SOC_DP2_P1 DPSNK1_ML1_P GPIO_4 TBT_PCIE_WAKE# <41>
<6> SOC_DP2_N1 CT30 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP2_N1_C AC17 W2 TBT_CIO_PLUG_EVENT# TBT_CIO_PLUG_EVENT# <11>
To CPU pin AD4
DPSNK1_ML1_N GPIO_5 Y1 TBT_HDMI_DDC_DATA
GPIO_6 @ T2
CT31 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP2_P2_C AB19 Y2 TBT_HDMI_DDC_CLK
SINK PORT 1
<6> SOC_DP2_P2 DPSNK1_ML2_P GPIO_7 @ T3
<6> SOC_DP2_N2 CT32 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP2_N2_C AC19 AA1 TBT_SRC_CFG1 RT11 1 TBT@ 2 1M_0201_1%
C DPSNK1_ML2_N GPIO_8 J4 TBTA_I2C_INT C
CPU DDI2 POC_GPIO_0 TBTA_I2C_INT <46>
CT33 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP2_P3_C AB21 E2 TBTB_I2C_INT
POC GPIO
<6> SOC_DP2_P3 DPSNK1_ML3_P POC_GPIO_1
1
1
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
RT6 RT7 RT8 RT9 <6> SOC_DP2_N3 CT34 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP2_N3_C AC21 D4 RTD3_USB_PWR_EN_R RT12 1 @ 2 0_0201_5% RTD3_USB_PWR_EN <11>
From CPU pin AP7
DPSNK1_ML3_N POC_GPIO_2 H4 TBT_FORCE_PWR_R RT13 1 MP@ 2 0_0201_5% From CPU pin J2
POC_GPIO_3 TBT_FORCE_PWR <12>
TBT@ TBT@ TBT@ TBT@ CT35 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP2_AUXP_C Y12 F2 BATLOW# RT14 1 @ 2 0_0201_5% PM_BATLOW# <10>
From CPU pin BD16
<6> SOC_DP2_AUXP DPSNK1_AUX_P POC_GPIO_4
CT36 TBT@ 1 2 0.1U_0201_6.3V6K CPU_DP2_AUXN_C W12 D2 SUSP#_R RT15 1 MP@ 2 0_0201_5% SUSP# <13,41,42>
From EC pin 116
<6> SOC_DP2_AUXN DPSNK1_AUX_N POC_GPIO_5
JTAG1 F1 RTD3_CIO_PWR_EN_R RT16 1 @ 2 0_0201_5% RTD3_CIO_PWR_EN <11>
From CPU pin AN8
2
1 Y6 POC_GPIO_6
1 <6> SOC_DP2_HPD DPSNK1_HPD
TBT_TDI 2 E1 TBT_TEST_EN RT17 1 TBT@ 2 100_0201_5%
TBT_TMS 3 2 SOC_DP2_CTRL_CLK Y8 TEST_EN
Misc
3 <6> SOC_DP2_CTRL_CLK DPSNK1_DDC_CLK
TBT_TCK 4 SOC_DP2_CTRL_DATA N4 AB5 TBT_TEST_PWG RT18 1 TBT@ 2 100_0201_5%
4 <6> SOC_DP2_CTRL_DATA DPSNK1_DDC_DATA TEST_PWR_GOOD YT1
TBT_TDO 5
6 5 2 TBT@ 1 DPSNK_RBIAS Y18 F4 TBT_RESET_N 25MHZ_12PF_7V25000012
6 DPSNK_RBIAS RESET_N TBT_RESET_N <46>
RT19 14K_0402_1% RT23 1 2 0_0201_5%
TBT_RESET_N_EC <41>
7 TBT_TDI Y4 D22 TBT_XTAL_25_IN 1 3
8 GND TBT_TMS V4 TDI XTAL_25_IN D23 TBT_XTAL_25_OUT 1 3
GND TMS XTAL_25_OUT 1 GND GND 1
TBT_TCK T4
ACES_50228-0067N-001 TBT_TDO W4 TCK AB3 TBT_EE_DI CT37 TBT@ CT38
TDO MISC EE_DI 2 4
CONN@ AC4 TBT_EE_DO 12P_0402_50V8J 12P_0402_50V8J
2 TBT@ 1 TBT_RBIAS H6 EE_DO AC3 TBT_EE_CS_N TBT@ 2 2 TBT@
RT25 4.75K_0402_0.5% TBT_RSENSE J6 RBIAS EE_CS_N AB4 TBT_EE_CLK
+3VS_TBT RSENSE EE_CLK
A15 B7
<47> USB3_A_TRX_DTX_P1 PA_RX1_P PB_RX1_P
B15 A7
<47> USB3_A_TRX_DTX_N1 PA_RX1_N PB_RX1_N
TBTA_LSTX RT21 2 @ 1 10K_0201_5%
CLKREQ_PCIE#4_R RT20 2 TBT@ 1 10K_0201_5% <47> USB3_A_TTX_C_DRX_P1 CT39 TBT@ 2 1 0.22U_0201_6.3V6M USB3_A_TTX_DRX_P1 A17 A9 TBT_TMU_CLK_OUT RT34 1 TBT@ 2 100K_0201_5%
CT40 TBT@ 2 1 0.22U_0201_6.3V6M USB3_A_TTX_DRX_N1B17 PA_TX1_P PB_TX1_P B9 TBT_FORCE_PWR_R RT35 1 TBT@ 2 100K_0201_5%
<47> USB3_A_TTX_C_DRX_N1 PA_TX1_N PB_TX1_N
RPT1 RTD3_CIO_PWR_EN_R RT36 1 TBT@ 2 100K_0201_5%
SOC_DP2_CTRL_CLK 1 8 CT41 TBT@ 2 1 0.22U_0201_6.3V6M USB3_A_TTX_DRX_P0 A19 A11 RTD3_USB_PWR_EN_R RT37 1 TBT@ 2 100K_0201_5%
<47> USB3_A_TTX_C_DRX_P0 PA_TX0_P PB_TX0_P
SOC_DP2_CTRL_DATA 2 7 <47> USB3_A_TTX_C_DRX_N0 CT42 TBT@ 2 1 0.22U_0201_6.3V6M USB3_A_TTX_DRX_N0B19 B11
SOC_DP1_CTRL_CLK 3 6 PA_TX0_N PB_TX0_N NC_B4 RT45 1 TBT@ 2 100K_0201_5%
TBT PORTS
SOC_DP1_CTRL_DATA 4 5 <47> USB3_A_TRX_DTX_P0
B21 A13 NC_B5 RT46 1 TBT@ 2 100K_0201_5%
A21 PA_RX0_P PB_RX0_P B13 NC_G2 RT47 1 TBT@ 2 100K_0201_5%
Port A
PORT B
<47> USB3_A_TRX_DTX_N0 PA_RX0_N PB_RX0_N
TBT@ 2.2K_0804_8P4R_5%
<46> TBT_A_AUX_P_C CT43 TBT@ 2 1 0.1U_0201_6.3V6K TBT_A_AUX_P Y15 Y16
B CT44 TBT@ 2 1 0.1U_0201_6.3V6K TBT_A_AUX_N W15 PA_DPSRC_AUX_P PB_DPSRC_AUX_P W16 B
<46> TBT_A_AUX_N_C PA_DPSRC_AUX_N PB_DPSRC_AUX_N
SOC_DP1_HPD RT38 1 TBT@ 2 100K_0201_5% Close to UT2
SOC_DP2_HPD RT39 1 TBT@ 2 100K_0201_5% TBT_A_USB20_P E20 E19
<46> TBT_A_USB20_P PA_USB2_D_P PB_USB2_D_P
TBTA_LSTX RT40 1 TBT@ 2 1M_0201_1% TBT_A_USB20_N D20 D19 TBT_EE_DI RT98 1 @ 2 0_0201_5%
<46> TBT_A_USB20_N PA_USB2_D_N PB_USB2_D_N PD_EE_DI <46>
TBTA_HPD RT41 1 TBT@ 2 100K_0201_5% TBT_EE_DO RT99 1 @ 2 0_0201_5% PD_EE_DO <46>
TBTA_LSRX RT42 1 TBT@ 2 1M_0201_1% <46> TBTA_LSTX TBTA_LSTX A5 B4 NC_B4 TBT_EE_CS_N RT100 1 @ 2 0_0201_5% PD_EE_CS_N <46>
PA_LS_G1 PB_LS_G1
POC
POC
<46> TBTA_LSRX TBTA_LSRX A4 B5 NC_B5 TBT_EE_CLK RT101 1 @ 2 0_0201_5% PD_EE_CLK <46>
TBTA_HPD M4 PA_LS_G2 PB_LS_G2 G2 NC_G2
<46> TBTA_HPD PA_LS_G3 PB_LS_G3
2 TBT@ 1 PA_USB2_RBIAS H19 F19 PB_USB2_RBIAS 1 TBT@ 2
RT43 499_0201_1% PA_USB2_RBIAS PB_USB2_RBIAS RT44 499_0201_1%
AC23 D6
AB23 THERMDA MONDC_SVR
THERMDA A23
V18 ATEST_P B23
PCIE_ATEST ATEST_N +3.3V_FLASH +3.3V_LC
AC1 DEBUG E18
TEST_EDM USB2_ATEST
2
L15 W13
N15 FUSE_VQPS_64 MONDC_DPSNK_0 RT105 RT106
FUSE_VQPS_128 W18 0_0402_5%
MONDC_DPSNK_1 0_0402_5%
C23 @
C22 MONDC_CIO_0 AB2
1
MONDC_CIO_1 MONDC_DPSRC
@ ALPINE-RIDGE_BGA337
UT2
TBT_EE_DI 5 2 TBT_EE_DO 1 2
DI SO 3.3K_0402_5% TBT@ RT49
TBT_EE_CLK 6 1
CLK
1 2 TBT_EE_CS_N 1 CT45
RT50 TBT@ 3.3K_0402_5% CS
0.1U_0402_10V7K
1 2 TBT_HOLD_N 7 2
HOLD TBT@
RT51 TBT@ 3.3K_0402_5%
A 1 2 TBT_EE_WP_N 3 A
RT48 TBT@ 3.3K_0402_5% WP
8 4
VCC VSS
W25Q80DVSSIG_SO8
TBT@

Thunderbolt (1/2)
1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_TBT_SX +3VS_TBT +3VALW +3.3V_TBT_SX +3VALW +3VS +3VS_TBT +3.3V_LC +3.3V_TBT_SX +3VS_TBT
1 @ 2 1 2 1 @ 2
0.1U_0201_6.3V6K
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
RT104 0_0402_5% RT97 0_0402_5% RT52 0_0805_5%
1 1 1 1 1 1 1 1
Reserve RT104 follow E-team's design dat.04/07 1 2 CT46 CT47 CT48 CT49 CT50 CT51 CT52 CT53
RT95 0_0805_5%
D
TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ D
2 2 2 2 2 2 2 2
R13
+0.9V_DP
R6
H9
F8
UT1B
L8 A2
VCC3P3_SX
VCC3P3A
VCC3P3_LC
VCC3P3_S0
VCC0P9_DP VCC3P3_SVR
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
L11 A3
L12 VCC0P9_DP VCC3P3_SVR B3
1 1 1 1 1 1 1 VCC0P9_DP VCC3P3_SVR
CT54 CT57 CT58 CT59 CT60 CT61 CT62 M8
T11 VCC0P9_DP
TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ T12 VCC0P9_DP L9 +0.9V_SVR
2 2 2 2 2 2 2 VCC0P9_DP VCC0P9_SVR
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
L6 M9
M6 VCC0P9_ANA_DPSRC VCC0P9_SVR E12
VCC0P9_ANA_DPSRC VCC0P9_SVR_ANA 1 1 1 1 1 1 1
V11 E13 CT63 CT64 CT65 CT66 CT67 CT68 CT69
V12 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F11
+0.9V_PCIE V13 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F12 TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ TBT@
VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F13 2 2 2 2 2 2 2
M13 VCC0P9_SVR_ANA F15
VCC0P9_PCIE VCC0P9_SVR_ANA
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
M15 J9
M16 VCC0P9_PCIE VCC0P9_SVR_SENSE
1 1 1 1 VCC0P9_PCIE
CT55 CT70 CT71 CT72 L19 LT1 TBT@
N19 VCC0P9_ANA_PCIE_1 C1 TBT_SVR_IND 1 2
VCC0P9_ANA_PCIE_1 SVR_IND
47U_0603_6.3V6M
47U_0603_6.3V6M
47U_0603_6.3V6M
TBT@ TBT@ TBT@ TBT@ L18 C2 0.6UH_MND-04ABIR60M-XGL_20%
2 2 2 2 M18 VCC0P9_ANA_PCIE_2 SVR_IND D1
VCC0P9_ANA_PCIE_2 SVR_IND 1 1 1
+0.9V_USB N18 CT73 CT74 CT75
VCC
VCC0P9_ANA_PCIE_2
R15 A1 TBT@ TBT@ TBT@
1U_0201_6.3V6M VCC0P9_USB SVR_VSS 2 2 2
1U_0201_6.3V6M
R16 B1
+0.9V_CIO VCC0P9_USB SVR_VSS B2
1 1 SVR_VSS
CT77 CT56 R8
R9 VCC0P9_CIO
TBT@ TBT@ R11 VCC0P9_CIO
2 2 VCC0P9_CIO
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
R12 F18 +0.9V_LVR_OUT
VCC0P9_CIO VCC0P9_LVR
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 H18
CT78 CT79 CT80 +3.3V_ANA_PCIE L16 VCC0P9_LVR J11
VCC3P3_ANA_PCIE VCC0P9_LVR 1 1 1 1
+3.3V_ANA_USB2 J16 H11 CT81 CT82 CT83 CT84
C
TBT@ TBT@ TBT@ VCC3P3_ANA_USB2 VCC0P9_LVR_SENSE C
2 2 2
1U_0201_6.3V6M
1U_0201_6.3V6M
A6 V5 TBT@ TBT@ TBT@ TBT@
A8 VSS_ANA VSS_ANA V6 2 2 2 2
1 1 VSS_ANA VSS_ANA
CT85 CT86 A10 V8
A12 VSS_ANA VSS_ANA V9
TBT@ TBT@ A14 VSS_ANA VSS_ANA V15
2 2 A16 VSS_ANA VSS_ANA V16
A18 VSS_ANA VSS_ANA V20
A20 VSS_ANA VSS_ANA W5
A22 VSS_ANA VSS_ANA W6
B6 VSS_ANA VSS_ANA W8
B16 VSS_ANA VSS_ANA Y9
B22 VSS_ANA VSS_ANA AA22
D8 VSS_ANA VSS_ANA AA23
D9 VSS_ANA VSS_ANA AB6
GND
E8 VSS_ANA VSS_ANA AB20
E9 VSS_ANA VSS_ANA AB22
E11 VSS_ANA VSS_ANA AC6
F9 VSS_ANA VSS_ANA AC16
B F16 VSS_ANA VSS_ANA AC18 B
F20 VSS_ANA VSS_ANA AC20
G22 VSS_ANA VSS_ANA AC22
G23 VSS_ANA VSS_ANA D5
H1 VSS_ANA VSS E4
H2 VSS_ANA VSS E5
H12 VSS_ANA VSS E6
H13 VSS_ANA VSS F5
H15 VSS_ANA VSS F6
H16 VSS_ANA VSS H5
H20 VSS_ANA VSS H8
J5 VSS_ANA VSS J8
J18 VSS_ANA VSS J12
J19 VSS_ANA VSS J13
J20 VSS_ANA VSS J15
J22 VSS_ANA VSS L13
J23 VSS_ANA VSS M11
K1 VSS_ANA VSS M12
K2 VSS_ANA VSS N8
L5 VSS_ANA VSS N9
L20 VSS_ANA VSS N11
L22 VSS_ANA VSS N12
L23 VSS_ANA VSS N13
M1 VSS_ANA VSS T6
M2 VSS_ANA VSS T8
M5 VSS_ANA VSS T9
M19 VSS_ANA VSS T13
M20 VSS_ANA VSS T15
N5 VSS_ANA VSS T16
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
N20 VSS_ANA VSS T18

N22 VSS_ANA VSS AB1
N23 VSS_ANA VSS AC2
VSS_ANA VSS
@ ALPINE-RIDGE_BGA337
P1
P2
R5
R18
R19
R20
R22
R23
T1
T2
T5
T20
U22
U23
A A

Thunderbolt (2/2)
1.0
5 4 3 2 1
5 4 3 2 1
+3VALW +3VALW_PD
1 MP@ 2
RT53 0_0402_5%
1
RT103
+3VALW 0_0402_5%
UT3 @ +3VS_TBT
@
2
2 1 1 7 +3VS_PD_R 1 @ 2 Remove RT56 for layout routing dat.05/06
CT87 1U_0402_6.3V6K 2 VIN VOUT 8 RT54 0_0402_5%
VIN VOUT +5VALW +5VALW_PD
3 6
<11,41> PD_PWR_EN ON CT
1 1
CT107 CT88
1
4 4.7U_0402_6.3V6M 0.1U_0402_10V6K
RT55
+5VALW
1
VBIAS 5 @ PD@
60mil 3A 60mil 3A
D GND 2 2 D
100K_0402_5% CT89 9
@ 1U_0402_6.3V6K GND
@
2
2 AOZ1336_DFN8_2X2
@
+5VALW_PD +TBTA_VBUS
60mil 3A 60mil 3A Change DT1 and add DT15 follow E-team's design for DELL dat.04/07
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1 1 1 1
CT90 CT91 CT92 CT93
3
CT106
1U_0603_25V6K DT1 DT15
2 2 2 2 SDM10U45-7_SOD523-2~D AZ4024-02S_SOT23-3~D
2
ESD@ ESD@
1
TBTA_LDO_BMC
+1.8VD_TBTA_LDO Close to UT4
+1.8VA_TBTA_LDO
1 1
1
CT98 CT99 CT100
2
2.2U_0603_16V6K 4.7U_0603_10V6K 4.7U_0603_10V6K
2
PD@ 2 2 RT22
PD@ +3VALW_PD PD@ +3.3V_FLASH
0_0201_5%
@
1
1
+3VS CT101
1U_0402_6.3V6K 0.6A
Follow TD team 2
Master0:0 ohm
H10
C11
D11
PD@
A11
B11
B10
A10
C C
H1
B1
K1
A2
E1
A6
A7
A8
B7
B9
A9
Slave1:93.1K ohm UT4
1
1
RT83 1 2 0_0402_5% F1
LDO_1V8A
PP_CABLE
PP_HV
PP_HV
PP_HV
PP_HV
SENSEP
LDO_1V8D
LDO_BMC
SENSEN
VIN_3V3
VDDIO
PP_5V0
PP_5V0
PP_5V0
PP_5V0
HV_GATE1
HV_GATE2
RT107 RT57 RT58 I2C_ADDR
10K_0402_5% 10K_0402_5% 10K_0402_5% D1 +3.3V_TBT_SX_R +3.3V_TBT_SX
<44> TBT_I2C_SDA I2C_SDA1
@ @ <44> TBT_I2C_SCL
D2
C1 I2C_SCL1 RT61
<44> TBTA_I2C_INT
2
2
PD_IRQ# I2C_IRQ1_N 1 2
<8,22,40,41> EC_SMB_DA2 RT59 1 MP@ 2 0_0402_5% TBTA_I2C_SDA1_R A5 0_0402_5%

RT60 1 MP@ 2 0_0402_5% TBTA_I2C_SCL1_R B5 I2C_SDA2 H11 @ +3.3V_FLASH
<8,22,40,41> EC_SMB_CK2 I2C_SCL2 VBUS
<41> PD_IRQ# PD_IRQ# B6 J10
I2C_IRQ2_N VBUS J11
B2 VBUS K11
T64 TP@ GPIO0 VBUS
T65 TP@
C2 1
TI's Request D10 GPIO1
T66 TP@ GPIO2 1
+3.3V_FLASH +3.3V_FLASH G11 CT102
T67 TP@ GPIO3
C10 RT96 1U_0402_6.3V6K CT103
<44> TBTA_HPD GPIO4 2
E10 H2 1 @ 2 10U_0603_10V6M
T68 TP@ GPIO5 VOUT_3V3 PD@ 2
T69 TP@
G10 PD@
TI's Request D7 GPIO6 0_0402_1%
T70 TP@ GPIO7
UT6 T71 TP@
H6
PD_EE_DI 5 2 PD_EE_DO 1 2 GPIO8 G1
DI SO 3.3K_0402_5% PD@ RT93 PD_EE_CLK A3 LDO_3V3
<44> PD_EE_CLK SPI_CLK
PD_EE_CLK 6 1 <44> PD_EE_DI PD_EE_DI B4
CLK PD_EE_DO A4 SPI_MOSI
<44> PD_EE_DO SPI_MISO
1 2 PD_EE_CS_N 1 CT105 <44> PD_EE_CS_N PD_EE_CS_N B3 K6 TBT_A_USB20_PT TBT_A_USB20_PT <47>
RT92 PD@ 3.3K_0402_5% CS SPI_SS_N C_USB_TP L6 TBT_A_USB20_NT
0.1U_0402_10V7K C_USB_TN TBT_A_USB20_NT <47>
1 2 PD_HOLD_N 7 2 TBT_A_USB20_P L5
HOLD PD@ <44> TBT_A_USB20_P USB_RP_P
RT87 PD@ 3.3K_0402_5% <44> TBT_A_USB20_N TBT_A_USB20_N K5
1 2 PD_EE_WP_N 3 USB_RP_N
RT91 PD@ 3.3K_0402_5% WP RT62 2 PD@ 1 100K_0402_5%PD_UART E2 K7 TBT_A_USB20_PB
UART_TX C_USB_BP TBT_A_USB20_PB <47>
8 4 F2 L7 TBT_A_USB20_NB
VCC VSS UART_RX C_USB_BN TBT_A_USB20_NB <47>
W25Q80DVSSIG_SO8 T62 TP@
F4
B PD@ TI's Request G4 SWD_DATA B
T63 TP@ SWD_CLK L9 TBTA_CC1 TBTA_CC1 <47>
C_CC1 L10 TBTA_CC2 +3.3V_FLASH
C_CC2 TBTA_CC2 <47>
RT63 2 PD@ 1 100K_0402_5%TBTA_MRESET E11
MRESET
1
K9 RPD_G1 RT64 1 PD@ 2 10K_0402_5%
TBTA_LSTX L4 RPD_G1 K10 RPD_G2 RT65 1 PD@ 2 10K_0402_5% RT66 RT67
<44> TBTA_LSTX TBT_LSTX/R2P RPD_G2
TBTA_LSRX K4 TI's Requirement 10K_0402_5% 10K_0402_5%
<44> TBTA_LSRX TBT_LSRX/P2R
PD@ PD@
2
+3.3V_TBT_SX RT68 2 PD@ 1 100K_0402_5%TBTA_DIG_AUD_P L3 E4 DEBUG_CTL1
RT69 2 PD@ 1 100K_0402_5%TBTA_DIG_AUD_N K3 DIG_AUD_P/DEBUG3 DEBUG_CTL1 D5 DEBUG_CTL2
DIG_AUD_N/DEBUG4 DEBUG_CTL2
1
RT70 RT71 2 PD@ 1 100K_0402_5%TBTA_DEBUG1 L2

RT72 2 PD@ 1 100K_0402_5%TBTA_DEBUG2 K2 DEBUG1
100K_0402_5% DEBUG2
@
K8 TBTA_SBU1
TBTA_SBU1 <47>
2
TBT_A_AUX_P_C J1 C_SBU1 Differential Signal

<44> TBT_A_AUX_P_C AUX_P
<44> TBT_A_AUX_N_C TBT_A_AUX_N_C J2 L8 TBTA_SBU2 TBTA_SBU2 <47>
AUX_N C_SBU2
1
RT73 1 @ 2 BUSPOWER# F10

+3.3V_FLASH BUSPOWER_N
100K_0402_5% RT74 0_0402_1% F11 RESET_N 1 @ 2 TBT_RESET_N TBT_RESET_N <44>
RESET_N RT102 0_0402_5%
@
TBTA_ROSC G2
2
R_OSC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
RT75 PD@ TPS65982_BGA96

A1
D6
E5
E6
E7
F5
G5
H4
H5
B8
D8
E8
F6
F7
F8
G6
G7
G8
H7
H8
L1
L11
15K_0402_1%
PD@
2
A 1 A
CT104
0.22U_0402_10V4Z
2
PD@

PD
E TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
5 4 3 2 1
5 4 3 2 1
USB3_A_TTX_C_DRX_P0 DT2 1 2
ESD@
ESD8011MUT5G X3DFN2 ESD
USB3_A_TTX_C_DRX_N0 DT3 1 2
ESD@
D ESD8011MUT5G X3DFN2 ESD D
USB3_A_TRX_DTX_P0 DT4 1 2
ESD@
USB3_A_TRX_DTX_N0 DT5 1 2
+TBTA_VBUS +TBTA_VBUS ESD@
USB3_A_TTX_C_DRX_P1 DT6 1 2
JUSBCx ESD@
A1 B12 ESD8011MUT5G X3DFN2 ESD
GND GND
<44> USB3_A_TTX_C_DRX_P0
A2 B11 USB3_A_TRX_DTX_P0 <44> USB3_A_TTX_C_DRX_N1 DT7 1 2
A3 SSTXP1 SSRXP1 B10 ESD@
<44> USB3_A_TTX_C_DRX_N0 SSTXN1 SSRXN1 USB3_A_TRX_DTX_N0 <44>
TBT@ CT94 1 2 0.47U_0402_25V6K A4 B9 TBT@ CT96 1 2 0.47U_0402_25V6K
VBUS VBUS USB3_A_TRX_DTX_P1 DT8 1 2
TBTA_CC1 A5 B8 TBTA_SBU2 ESD@
<46> TBTA_CC1 CC1 RFU2 TBTA_SBU2 <46>
TBT_A_USB20_L_PT A6 B7 TBT_A_USB20_L_NB
TBT_A_USB20_L_NT A7 DP1 DN2 B6 TBT_A_USB20_L_PB USB3_A_TRX_DTX_N1 DT9 1 2
DN1 DP2 ESD@
Bottom
TBTA_SBU1 A8 B5 TBTA_CC2 ESD8011MUT5G X3DFN2 ESD
<46> TBTA_SBU1 RFU1 CC2 TBTA_CC2 <46>
TOP
TBT@ CT95 1 2 0.47U_0402_25V6K A9 B4 TBT@ CT97 1 2 0.47U_0402_25V6K TBTA_CC1 DT111 2
VBUS VBUS ESD@
A10 B3 ESD8011MUT5G X3DFN2 ESD
<44> USB3_A_TRX_DTX_N1 SSRXN2 SSTXN2 USB3_A_TTX_C_DRX_N1 <44>
A11 B2
<44> USB3_A_TRX_DTX_P1 SSRXP2 SSTXP2 USB3_A_TTX_C_DRX_P1 <44>
TBTA_CC2 DT121 2
A12 B1 ESD@
GND GND ESD8011MUT5G X3DFN2 ESD
1 4 TBTA_SBU1 DT131 2
GND GND 6 ESD@
2 GND 3 ESD8011MUT5G X3DFN2 ESD
5 GND GND
GND TBTA_SBU2 DT141 2
CONN'@ JAE_DX07S024JJ2 ESD@
C
5/6 New Connector C
MCM1012B900F06BP_4P MCM1012B900F06BP_4P
TBT_A_USB20_PT 4 3 TBT_A_USB20_L_PT TBT_A_USB20_NB 4 3 TBT_A_USB20_L_NB DT10
<46> TBT_A_USB20_PT <46> TBT_A_USB20_NB
TBT_A_USB20_L_PT 1 9 TBT_A_USB20_L_PT
<46> TBT_A_USB20_NT TBT_A_USB20_NT 1 2 TBT_A_USB20_L_NT <46> TBT_A_USB20_PB TBT_A_USB20_PB 1 2 TBT_A_USB20_L_PB TBT_A_USB20_L_NT 2 8 TBT_A_USB20_L_NT
LT2 EMI@ LT3 EMI@ TBT_A_USB20_L_NB 4 7 TBT_A_USB20_L_NB
TBT_A_USB20_L_PB 5 6 TBT_A_USB20_L_PB
ESD@ TVWDF1004AD0_DFN9
B B
A A

Thunderbolt+USB3.1 TypeC
1.0
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) Page 1

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
1 HW
2 HW
D D
3 HW
4 HW
5 HW
6 HW
7 HW
8 HW
9 HW
10 HW
11 HW
12 HW
13 HW
14 HW
C 15 HW C
16 HW
17 HW
18 HW
19 HW
20 HW
21 HW
22 HW
23 HW
24 HW
25 HW
26 HW
27 HW
B B
28 HW
29 HW
30 HW
31 HW
32 HW
33 HW
34 HW
35 HW
36 HW
37 HW
38 HW
39 HW
A A
40 HW
41 HW
42 HW

HW-PIR Page.1
1.0
5 4 3 2 1
5 4 3 2 1

Request
43 HW
44 HW
D D
45 HW
46 HW
47 HW
48 HW
49 HW
50 HW
51 HW
52 HW
53 HW
54 HW
55 HW
56 HW
C 57 HW C
58 HW
59 HW
60 HW
61 HW
62 HW
63 HW
64 HW
65 HW
66 HW
67 HW
68 HW
69 HW
B B
70 HW
71 HW
72 HW
73 HW
74 HW
75 HW
76 HW
77 HW
78 HW
79 HW
80 HW
81 HW
A A
82 HW
83 HW
84 HW

HW-PIR Page.2
1.0
5 4 3 2 1
5 4 3 2 1

Request
85
86
D D
87
88
89
90
91
92
93
94
95
96
97
98
C C
B B
A A

HW-PIR Page.3
1.0
5 4 3 2 1
A B C D
VIN +3VALW
ADPIN
1000P_0402_50V7K
1000P_0402_50V7K
PJPDC
2.2K_0402_5%
100P_0402_50V8J
100P_0402_50V8J
1
1
1
1
2
EMI@ PC1
EMI@ PC2
EMI@ PC3
EMI@ PC4
2
2 3
2
3
PR3
4
4 5 PR4
5 6 33_0402_5%
1
6 7 1 3 PSID-3 1 2 PS_ID <41>
S
1
7 8 PQ7
1
GND 9 FDV301N_G 1N SOT23-3

GND
G
2
ACES_50300-00701-001
100K_0402_1%
2
PR8
PR6
PSID PSID-2 2 1
+5VALW
1
10K_0402_1%
1
C
PSID-1 2 PQ2
15K_0402_1%
B MMST3904-7-F_SOT323~D
2
E
3
PR9
@
1
PD1
SM24_SOT23
1
BATT+ BATT+
BATT+
BATT+
PQ3
1000P_0402_50V7K
10P_0402_50V8J
100P_0402_50V8J
10P_0402_50V8J
0.022U_0402_25V7K
0.01U_0402_25V7K
1
SI3457CDV-T1-GE3_TSOP6
EMI@ PC6
EMI@ PC7
EMI@ PC8
EMI@ PC9
@ PC16
@ PC17
6
2
1
5
2
PD2 PD3 2 2
4 1
D
TVNST52302AB0_SOT523-3
EMI@
TVNST52302AB0_SOT523-3
EMI@ B+ B+_BIAS
100K_0402_1%
0.1U_0402_25V6
0.22U_0603_25V7K
1
G
2
1
PR12
PC10
PC11
3
@
2
ACES_51202-00901-001
2
11 BATT_TEMP <41,51,52> +5VALW PR13
11 10 100K_0402_1%
10 9 1 2 VSB_N_001
9
1VSB_N_003
8
8 7 CLK_SMB 1 2 PR16 PR14
7 6 DAT_SMB 1 PR22 2 100_0402_5% PR15 10K_0402_1% 100K_0402_1%
6 5 BATT_PRS 1 PR21 2 100_0402_5% 1 2 1 2
5 4 SYS_PRES PR19 100_0402_5% +3VALW
1
4 3 0_0402_5% @ PR17 D
3 2 <41,53> POK 1 2 VSB_N_0022 PQ4
2 1 G 2N7002KW _SOT323-3
1 PR18 0_0402_5% @
.1U_0402_16V7K
S
3
1
EC_SMB_CK1 <35,40,41,52>
PC12
PBATT 1 2
0_0402_5% @ @
2
PR20
1 2 EC_SMB_DA1 <35,40,41,52>
Battery connector:
1.GND 0_0402_5% @
2.GND
3.BAT_ALERT @
3
4.SYS_PRES JRTC
3
5.BATT_PRS 1
6.DAT_SMB 1 2 +RTCBATT
2 3
7.CLK_SMB G1 4
8.BATT++ G2 ADP_I <41,52> CPU thermal protection at 93 +/- 3 degree C
9.BATT++ Adapter Proctection
10.GND ACES_50271-00201-001
VCIN1_PH setting
11.GND Trigger point : 0.730V CPU OTP
Recovery point : 0.635V VCIN0_PH setting
Trigger point : 1V +3VALW +3VLP
2
Recovery point : 2.21V
PR23
Adapter protection:
2
VIN if battery removed, adaptor only,
110K_0402_1%
PR24 PR25 @
Erp lot6 Circuit then trigger the H_PROCHOT#, 16.2K_0402_1% 12.1K_0402_1%
1
3.3K_1206_5%~D
keep @ in BOM since battery can not
1
1
be removed by end user

<41> VCIN0_PH
PR32
<6,41,52> H_PROCHOT# <41> VCIN1_PH
1
PR30
ACIN <10,22,37,41,52>
2
2
1M_0402_1%
6
PR26 PC13 @
2N7002KW_SOT323-3
PC14 PH1
2
PQ9A
1U_0603_25V6K 100K_0402_1% .1U_0402_16V7K 100K_0402_1%_TSM0B104F4251RZ

1
1
1
2 D
1
<41> ECAGND
PQ8
PR29 1 2 2
<41,51,52> BATT_TEMP
3
4
G 4
1
PQ9B
10K_0402_1%
200K_0402_1% S
3
2
PR31
2
PR28
5
1M_0402_1%
1
1
PC15
4
0.1U_0402_25V6
2
PWR-DCIN/BATT CONN/OTP
A B C D
A B C D
CC = 3.5A
1
D
2 PQ700
CV = 17.7V
G 2N7002KW_SOT323-3 CP = 117W/19.5V = 6A
S Hyprid trigger point = CP x 1.07 =6.42A
3
PR700 PR701
1M_0402_5% 3M_0402_5%
1 2 1 2
Iada=0~6.67A(130W)
VIN PQ701
P1 ADP_I = 40*Iadapter*Rsense
1 1
MDU1516URH_POWERDFN56-8-5 PQ702
MDV1526URH 1N PDFN33-8
P2 PR702
B+ PQ703
1 1 0.01_1206_1% 1
2200P_0402_50V7K
2 2 2
5 3 3 5 1 4 5 3
0.1U_0402_25V6
2 3
PC701
1 CSSN_1
1 CSSP_1
1 4
4
1
PC700
4.7_0603_5%
CHG_B+ PC722
2
EMI@ PL701 0.022U_0402_25V7K
PR725
PD700
2
1UH_PCMB041B-1R0MS_4.2A_20% 1 2
0_0402_5%
0_0402_5%
2 1 2
BATT+
10U_0805_25V6K
10U_0805_25V6K
PR703
PR704
2
2200P_0402_50V7K
1
PC705
PC706
0.1U_0402_25V6
PC702
10K_0402_1%
1
1
@EMI@ PC703
3 0.047U_0402_25V7K
@EMI@ PC704
10_0402_1%
VIN
2
PC707 PC708 PC709 1 2
PR729
PR728
2
2
0.1U_0402_25V6 0.1U_0402_25V6 0.01U_0402_25V7K
2
4.12K_0603_1%
4.12K_0603_1%
1
1 2 1 2 1 2 S SCH DIO BAT54CW-7-F SOT-323 DII
2.2U_0603_16V6K
2.2_0603_1%
10_1206_1%
PR706
PR705
BATDRV_CHG 2
BATSRC_CHG 2
1
1
PR707
PR708
2
+3VALW
PC710
S TR MDV1528URH 1N PDFN33-8
2
REGN_CHG 1
5
1 2
BTST_CHG
100K_0402_1%
1
DH_CHG
DL_CHG
LX_CHG
2
PC711 PR710
PR709
1U_0603_25V6K 31.6K_0402_1%
PQ704
DH_CHG 4
1 2
PU700 PQ705
28
27
26
25
24
23
22
1
D 2N7002W-T/R7_SOT323-3
2TB_STAT#_CHG
VCC
REGN
GND
BTST
PHASE
HIDRV
LODRV
G PR712
3
2
1
29 S PL700 0.01_1206_1%
CSSP_2
CSSN_2
2 2
3
PWPD 3.3UH_PCMB053T-3R3MS_5A_20%
PR711 LX_CHG 1 2CHG1 4 BATT+
1 21 1 2
ACN ILIM 2 3
S TR MDV1528URH 1N PDFN33-8
1
6.49K_0402_1%
5
2 20 PR713
CSON_1
CSOP_1
ACP SRP 4.7_1206_5%
@EMI@
10U_0805_25V5K~D
10U_0805_25V5K~D
CMSRC_CHG 3 19
2
CMSRC SRN
1
SNUB_CHG
PQ706
PC712
PC713
DL_CHG 4
1
ACDRV_CHG 4 18 BATDRV_CHG PC715
2
ACDRV BQ24780SRUYR_WQFN28_4X4 BATDRV 680P_0402_50V7K
@EMI@
2
<10,22,37,41,51> ACIN 5 17 BATSRC_CHG
3
2
1
ACOK BATSRC
PR714
REGN_CHG 1 2
VIN ACDET_CHG 6 16 TB_STAT#_CHG
120K_0402_5%
100K_0402_5% ACDET TB_STAT#

324K_0402_1%
1
PC716 PC717 PC721

1
7 15 0.1U_0402_25V6 0.1U_0402_25V6 0.1U_0402_25V6

PR715
IADP BATPRES#
1
<41,51> ADP_I 1 2 1 2 1 2
PR716
PROCHOT#
PR718
CMPOUT
10K_0402_5%
CMPIN
100P_0402_50V8J
IDCHG
2
PMON
SDA
2
SCL
2
PR722
PC718
AC Det
2
10_0402_5%
Max:18.16V 1 2
1
10
11
12
13
14
Typ :17.98V
Min :17.8V +3VALW PR723
1
10_0402_5%
1
1 2 1 2
PR719
PC719
49.9K_0402_1%
2200P_0402_50V7K
0_0402_5%
PC720
0_0402_5%
2
1
100P_0402_50V8J
PR721
2
<41,51> BATT_TEMP
PR720
3
@ @ 3
@
2
2
2
<58> 0_0402_5% PR727
1
<6,41,51>
EC_SMB_DA1
EC_SMB_CK1
H_PROCHOT#
<35,40,41,51>
<35,40,41,51>
I_SYS
4 4

PWR-Charger
A B C D
A B C D E
+3VLP
2
0_0603_5%~D
PR115
PC101
1
4.7U_0603_6.3V6K
1 2
1 1
Output capacitor ESR need follow
below equation to make sure feed back
loop stability
ESR=20mV*L*fsw/2V
PR101 PR102
6.49K_0402_1% 15K_0402_1%
1 2 1 2
VFB=2V VFB=2V
PR103 PR104
10K_0402_1% 10K_0402_1%
1 2 1 2
54.9K_0402_1%
68.1K_0402_1%
1
1
PR105
PR106
B+
B+
10U_0805_25V6K
10U_0805_25V6K
B+
FB_3V
FB_5V
1
CS2
CS1
PC114
PC102
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
POK need pull high, it
2
1
5
@EMI@ PC100
@EMI@ PC103
PC104
PC113
will pull high on VS
5
MDV1525URH_PDFN33-8-5
transfer circuit
2
PU100 21
CS2
VFB2
VREG3
VFB1
CS1
TP
PQ100
2 2
PQ102
4
3V_EN 6 20 5V_EN 4
EN2 EN1 PR107 @
200_0402_1%
7 19 1 2
1
2
3
<41,51> POK PGOOD VCLK
3
2
1
PL101
LX_3V 8 18 LX_5V
4.7UH_5.5A_20%_7X7X3_M PC105 PR108 SW2 TPS51225CRUKR_QFN20_3X3 SW1 PR109 PC106 PL102
1 2 LX_3V 0.1U_0402_25V6 0_0603_5% 0_0603_5% 0.1U_0402_25V6 S COIL 1.5UH +-20% 9A 7X7X3
+3VALWP 1 2 1 2 BST_3V 9 17 BST_5V 1 2 1 2 LX_5V 1 2
VBST2 VBST1 +5VALWP
1
5
4.7_1206_5%
680P_0603_50V8J 4.7_1206_5%
UG_3V 10 16 UG_5V
DRVH2 DRVH1
1
@EMI@ PR110
@EMI@ PR111
VREG5
DRVL2
DRVL1
VO1
220U_B2_6.3VM_R25M
220U_B2_6.3VM_R25M
VIN
PQ101
1 1
2
PQ103
4
11
12
13
14
15
2
PC107
PC108
+ 4 +
680P_0603_50V8J
LG_3V LG_5V
1
1
2 2
@EMI@ PC109
@EMI@ PC110
1
2
3
3
2
1
+5VALWP
2
2
B+
3.3VALWP VL
TDC=5.6A
Peak Current 8A
1
3
OCP current 9.6A PC111
3
FSW=355kHz 4.7U_0603_6.3V6K 5VALWP
2
TYP MAX OVP=Vout*(112.5%~117.5%) TDC=9.5A
H/S Rds(on) : 11.5mohm 14mohm Peak Current 13.5A
L/S Rds(on) : 7mohm 8.4mohm OCP=Vtrip/Rdson+Iripple/2 OCP current 16.2A
Vtrip=Ics(min)*Rcs/8+1mV FSW=300kHz
EN Vcs=Ics*vcs should be in the range of 0.2~2V TYP MAX
Rising=1.6~0.3V H/S Rds(on) : 11.5mohm 14mohm
Vout=VFB*(1+Rtop/Rbot) L/S Rds(on) : 5.7mohm 6.8mohm
PR100 0_0402_5% VFB=2V
3V_EN 1 2
PR112 0_0402_5%
5V_EN 1 2 @ PJ100 @ PJ102
+5VALWP 1 2 +5VALW +3VALWP 1 2 +3VALW
1 2 1 2
PD100 PR113 JUMP_43X118 JUMP_43X118
<41> EC_ON 2 2.2K_0402_5%
1 1 2
<33> USBCHG_DET_D 3
BAS40CW_SOT323-3
PR114 0_0402_5%
<41> VCOUT0_PH# 1 2
4 4
200K_0402_1%
4.7U_0603_6.3V6K
1
PR116
PC112

2
PWR-3.3VALWP/5VALWP
2
Size
A B C D E
5 4 3 2 1
D D
1.35VP
TDC=16.7A
Ipeak=24A
OCP=28.8A
Switching Frequency: 285kHz
Pin19 need pull separate from +1.35VP.

If you have +1.35V and +0.675V sequence question, 0.675Volt +/- 5%
you can change from +1.35VP to +1.35VS. TDC 0.7A
PJ203 @
B+ 1 2 1.35V_B+ PR200 Peak Current 1A
1 2 2.2_0603_5%
JUMP_43X39 BST_1.35V 1 2 BOOT_1.35V
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
+1.35VP
10P_0402_50V8J
1
1
PC202
PC203
PC215
PC216
@ PC217
@EMI@ PC200
@EMI@ PC201
DH_1.35V +0.675VSP
2
MDU1516URH_POWERDFN56-8-5
SW _1.35V
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
PC204
PC205
PC206
5
0.1U_0603_25V7K
16
17
18
19
20
2
PQ200
C PU200 C
2
VLDOIN
PHASE
UGATE
BOOT
VTT
21
PAD
4 DL_1.35V 15 1
LGATE VTTGND
14 2
PL201 PR201 PGND VTTSNS
1
2
3
1UH_PCMB104T-1R0MH_18A_20% 10K_0402_1%
1 2 1 2 CS_1.35V 13 3
+1.35VP PC207 CS RT8207MZQW _W QFN20_3X3 GND
1
1U_0402_10V6K
5
1 2 12 4 VTTREF_1.35V
VDDP VTTREF
PQ201
@EMI@ PR202 PR203
ESR=9m ohm
MDU1511RH_POWERDFN56-8-5
1 4.7_1206_5% 5.1_0603_5%
330U_D2_2V_Y
1 2 VDD_1.35V 11 5
1 2
+5VALW VDD VDDQ

+1.35VP
1
+
PGOOD
PC209
OVP: 110%~120%
4 PC210
2.2_0603_5%
VFB=0.75V, Vout=1.35V
TON
1
2
@EMI@ PC211 0.033U_0402_16V7K
FB
S5
S3
2
TYP MAX 2 680P_0402_50V7K PC212
PR204
2
H/S Rds(on) : 11.7mohm 14mohm 1U_0402_10V6K
10
6
L/S Rds(on) : 2.7mohm 3.3mohm
1
2
3
FB_1.35V
TON_1.35V
EN_0.675VSP
EN_1.35V
PR205
8.06K_0402_1%
PR206 1 2 +1.35VP
887K_0402_1%
B 1.35V_B+ 1 2 B
1
@ PR208
0_0402_5%
1 2 PR207
<13,41> SYSON
10K_0402_1%
2
Mode Level +0.675VSP VTTREF_1.35V PR210
1 2
S5 L off off <6,10,13,37,41> PM_SLP_S4#
S3 L off on 0_0402_5% @
1
S0 H on on @ PC213 @ PJ200
0.1U_0402_10V7K +1.35VP 1 2 +1.35V_VDDQ +1.35VS_VGA
1 2
Note: S3 - sleep ; S5 - power off
2
JUMP_43X118
@ PJ201
PR209 1 2 1
330U_D2_2V_Y
1 2 1 2
<7> 0.675V_DDR_VTT_ON JUMP_43X118 +
PC208
0_0402_5% @
1
@ PC214 2
0.1U_0402_10V7K
2
PJ202 @
1 2
+0.675VSP 1 2 +0.675VS_VTT
A
JUMP_43X39 A

PWR-1.35VP/0.675VSP
5 4 3 2 1
5 4 3 2 1
PJ301 @
+1.0VSP_B+ 1 2
1 2 B+
JUMP_43X39
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
1.0V
1
@EMI@ PC301
@EMI@ PC302
PC303
PC304
+3V_PRIM TDC 7A
Peak Current 10A
2
OCP current 12A
5
FSW=290kHz
PR301
D 10K_0402_5% D
PQ300
2
4
<41> +1.0V_PGOOD
PR302 PC305
PU300 2.2_0603_5% 0.1U_0603_25V7K
PR303 1 10 BST_+1.0VSP 1 2 1 2
3
2
1
64.9K_0402_1% PGOOD VBST
PR300 1 2 TRIP_+1.0VSP 2 9 UG_+1.0VSP PL300
<56> +1.8V_PG TRIP DRVH
0_0402_5% 1UH_6.6A_20%_5X5X3_M
1 2 EN_+1.0VSP 3 8 SW _+1.0VSP 1 2
EN SW
FB_+1.0VSP 4 7 +1.0VALWP
VFB V5IN
+5VALW
1
0.1U_0402_16V7K
RF_+1.0VSP 5 6 LG_+1.0VSP
220U_B2_2.5VM_R15M
220U_B2_2.5VM_R15M
TST DRVL
PR305 @EMI@
@ PC300
1 1
1
11 4.7_1206_5%
TP
1
+ +
PQ301
PC306
PC307
2
2
PR306 TPS51212DSCR_SON10_3X3 PC308 4
470K_0402_1% 1U_0603_6.3V6M
1
PC309 @EMI@ 2 2
2
680P_0402_50V7K
3
2
1
2
Switching Frequency: 290kHz
C PR307 C
4.32K_0402_1%
OVP: 120%-130%
1 2 VFB=0.7V
TYP MAX
H/S Rds(on) : 11.5mohm 14mohm
1
L/S Rds(on) : 7mohm 8.4mohm

PR308
10K_0402_1%
2
PJ302 @
+1.0VALWP 1 2 +1.0V_PRIM
1 2
JUMP_43X39
PJ303 @
1 2
1 2
JUMP_43X39
B B
A A

PWR-1.0VALWP
5 4 3 2 1
5 4 3 2 1
D D
PC800
22U_0603_6.3V6M
1 2
PL800
PJ800 @
+3VALW 1 2 4 3 LX_1.05V 1 2
1 2 IN LX
+1.05VSP
1
JUMP_43X39 2 5 2
1.05VSP
68P_0402_50V8J
PR812 +3VS PG GND 1UH_2.8A_30%_4X4X2_F
1
62K_0402_5% @ PR800 6 1 TDC 2A
PC803
22U_0603_6.3V6M
22U_0603_6.3V6M
FB EN
1
1 2 100K_0402_5%
PC804
PC805
<22,25,57> 3V3_MAIN_EN Peak Current 2.9A
2
@ PR801 @EMI@ PR803 PR804 OCP current 3.5A
2
33K_0402_5% 4.7_0603_5% 7.5K_0402_1%
<22,25,57> NVVDD_PWR_GD
1 2 +1.05VSP_ON FSW=1MHz
2
Rup
2
PU800
0.047U_0402_25V7K
1
SY8032ABC_SOT23-6
PC801
1
PR802 FB_1.05V
1M_0402_5%
1
2
@EMI@ PC802
C 680P_0402_50V7K PR805 C
2
10K_0402_1%
Rdown
2
Note: PJ801 @
When design Vin=5V, please stuff snubber
+1.05VSP 1 2 +1.05VS_VGA
to prevent Vin damage 1 2
Vout=0.6V* (1+Rup/Rdown) JUMP_43X79
PJ802
+3VALW 2 1 +1.8V_VIN
2 1
JUMP_43X39
@
10P_0402_50V8J
1
PC806
@ PC810
B 4.7U_0603_6.3V6K B
2
PJ803
1 2
+1.8VALWP 1 2 +1.8V_PRIM
11
@ JUMP_43X39
6 5
GND
<14,41> PCH_PWR_EN
PR809 7 VIN
VIN
VOUT
VOUT
4 +1.8VALWP
0_0402_5% 8 3
VIN VOUT +1.8V_PRIM
1
1 2 9 2
12.7K_0402_1%
0.01U_0402_25V7K
EN FB
1
10
VCNTL POK
1 TDC 0.27A
PR808
PC809
10U_0603_6.3V6M
1
Rup
10K_0402_5%
0.1U_0402_16V7K
PU801
1
PR806
PC808
APL5930QBI-TRG_TDFN10_3X3 @
PC807
2
2
@ PR810
2
10K_0402_5%
1
1 2
10K_0402_1%
PR807
+3V_PRIM Rdown
2
<55> +1.8V_PG
A Vout=0.8V* (1+Rup/Rdown) A

PWR-1.05VS_VGA/1.8V_PRIM
5 4 3 2 1
PJ600 @
B+
1 2 GPU_B+
1 2
JUMP_43X79
@EMI@ PL600
1 2
FBMA-L11-453215800LMA90T_2P
+3VS
1
PR600
0_0402_5%~D
10U_0805_25V6K
2200P_0402_50V7K~D
@
PR610
1
1 2 NVVDD PWM_VID <22>
PC600
@EMI@ PC634
1
0_0402_5% @
2
PR602
U2_UGATE1
0_0402_5%~D
@
2
PR601
2.2 +-5% 0603
U2_BOOT1 1 2
PQ605
1
S TR AON6992 2N DFN5X6D +VGA_CORE
PL601
D1
G1
.1U_0603_25V7K
0.24UH_PCME063T-R24MS1R195_28A_20%
PC612
2
U2_PHASE1 2 1
1U_0402_6.3V6K
PR607 7U2_PHASE1
D2/S1
1
1 2 NVVDD PSI <22>

1
PC613
20K_0402_1%
47P_0402_50V8J~D
0_0402_5% @
PR606
PC614
G2
S2
S2
S2
2
1
U2_LGATE1
+3VS
VGA_CORE
6
@
2
2
PR649 TDC 51.1A
Peak Current 87A
1
56,57> 3V3_MAIN_EN PR611 PR613 PR614 @
10.5K_0402_1%
2K_0402_1%
1 2
20K_0402_1%
1 2
OCP=104A
GPU_REFIN 10K_0402_1%~D
TYP MAX
1
PR615
1
@ 0_0402_5% H/S Rds(on):6.7mohm ,8.5mohm

3K_0402_1%
18K_0402_1%
0_0402_5%~D
2700P_0402_50V7K
2700P_0402_50V7K
2
1
1 2 3V3_MAIN_EN <22,25,56,57>
PR623
L/S Rds(on):1.8mohm ,2.3mohm

1
1
PR620
PR616
PC616
PC617
PC618
0.047U_0402_25V7K
@
1 2
@
2
2N7002KW_SOT323-3
2
D
10U_0805_25V6K
2 @
U2_BOOT1
GPU_B+
1
@
PQ610
GPU_REFADJ
G
0_0402_5%
.01U_0402_16V7K
1
PR618
PC601
S
10K_0402_1%~D
GPU_FBRTN 3
1
U2_UGATE1
U2_UGATE2
GPU_VID
GPU_PSI
PC626
PR631
GPU_EN
2
2
@ GPU_FBRTN
2
PR650 PR617 PQ606

6
1
340K_0402_1% PU600 2.2 +-5% 0603 S TR AON6992 2N DFN5X6D
GPU_B+ 2 1 U2_BOOT2 1 2
D1
G1
PSI
UGATE1
BOOT1
VID
EN
REFADJ
PL602
.1U_0603_25V7K
1
PR622 0.24UH_PCME063T-R24MS1R195_28A_20%
23> VSSSENSE_VGA 0_0402_5% GPU_REFIN 7 24 U2_PHASE1 7U2_PHASE2 2 1
PC619
1 2 REFIN PHASE1 D2/S1
2
PR624 GPU_VREF 8 23 U2_LGATE1 U2_PHASE2
100_0402_1% VREF LGATE1
G2
S2
S2
S2
1 2 GPU_TON 9 22 U2_PWM3 PR625 +5VS
TON GND/PWM3 2.2 +-5% 0603
6
PR627 GPU_FBRTN 10 21 1 2
23> VCCSENSE_VGA 0_0402_5% RGND PVCC
1 2 11 20
TALERT/ISEN2
GPU_FB U2_LGATE2
VSNS LAGTE2
U2_LGATE2
TSNS/ISEN3
VCC/ISNE1
12 19 U2_PHASE2
1U_0603_6.3V6M
SS PHASE2
UGATE2
PGOOD
1 2
BOOT2
+VGA_CORE
1
PC622
GND
PR629
100_0402_1%
2
RT8813AGQW_WQFN24_4X4
25
13
GPU_TALERT/ISEN2 14
15
16
17
18
GPU_TSNS/ISEN3
GPU_DSBL/ISEN1
GPU_PGOOD1
U2_UGATE2
+5VS
U2_BOOT2
10U_0805_25V6K
GPU_B+
1
PC602
2
1
PR643
1
2.2 +-5% 0603 PR633 PQ607
2.2 +-5% 0603 S TR AON6992 2N DFN5X6D
D1
G1
<22,25,56> NVVDD_PWR_GD 1 2 PL603
2
+3VS 0.24UH_PCME063T-R24MS1R195_28A_20%
2
PR638 7 PHASE3 2 1
10K_0402_1%~D
PC629 D2/S1
PC625
.1U_0603_25V7K
1
.1U_0603_25V7K PU601
PR639
10K_0402_1%
G2
S2
S2
S2
2
2
1
6
PR619
2
1 2 8 3UG3
VCC UGATE
.01U_0402_16V7K
1
PC627 0_0402_5% @ GPU_EN 1 4

PHASE3 PR642 EN BOOT
@ U2_PWM3 1 2 5 2 PHASE3
2
PWM PHASE
0_0402_5% @ 6 7LG3
GND LGATE
TP
RT9610BZQW WDFN8 MOSFET DRIVER ET88

9
2
PR646
10K_0402_1%
PR648
1
10K_0402_1%
U2_PHASE2

U2_PHASE1
PWR-VGA_CORE
5 4 3 2 1
+1.0V_VCCST
PR501
0.1U_0402_25V6
1_0402_5%
1
45.3_0402_1%
100_0402_1%
75_0402_1%
PC501
1 2
+5VALW VCC_SA
PR503
PR500
PR502
Local sense put on HW site PR504 TDC 4A
2
0_0402_5%
@ 1 2 CPU_B+ Peak Current 5A
0.1U_0402_25V6
OCP current 6A
1U_0402_10V6K
D <15> SOC_SVID_CLK 1 2 1 2 D
Choke DCR 13 m ohm
1
PR505 0_0402_5% @ 49.9_0402_1% PR506
PC502
PC503
<15> SOC_SVID_ALERT#_R 1 2 1 2
PR507 0_0402_5% @ 0_0402_5% PR508
2
<15> SOC_SVID_DAT 1 2 1 2
PR509 0_0402_5% @ 10_0402_1% PR510
<41> VR_HOT# PR511 CPU_B+
0_0402_5%
1 2 1 2 EMI@ PL501
1 2 1 2
B+
PC511 @EMC@
PC512 @EMC@
@ PC500 47P_0402_50V8J~D
PR512 FBMA-L11-453215800LMA90T_2P
2200P_0402_50V7K
10U_0805_25V6K
33U_D2_25VM_R60M
33U_D2_25VM_R60M
33U_D2_25VM_R60M
0.1U_0402_25V6K~D
PH500 PR514 34K_0402_1% 1 1 1
10U_0805_25V6K
10U_0805_25V6K
470K_0402_5%_ TSM0B474J4702RE 10.5K_0402_1% 1 2
PC504
PC505
PC506
1 2 1 2 PR517 1.91K_0402_1% PR515 + + +
1
PC508
PC509
PC510
86.6K_0402_1% 1 2 PR513
1 2 1 2 +3VS 48.7K_0402_1%
PR516 PC513 <41> VR_PWRGD 1 2 2 2 2
2
27.4K_0402_1% 330P_0402_50V8J 0_0402_5% PR518
1 2 1 2
PC514 PR520 <10> VR_ON @
2200P_0402_50V7K 3.6K_0402_1% PR519 0_0402_5% @
1 2 1 2 PR528 0_0402_5% PU501
40
39
38
37
36
35
34
33
32
31
PC515 PU500 FCCM_VSA 1 2 1
68P_0402_50V8J 0.22U_0402_16V7K 2 ZCD_EN# 13
VR_ENABLE
VR_READY
SCLK
SDA
VCC
VIN
VR_HOT#
ALERT#
PROG1
PROG2
1 2 PC518 3 VCIN CGND 12 PWM_VSA
0_0402_5% PR521 1 2 4 CGND PWM 11
1 2 PC516 PR522 <52> I_SYS 1 2 1 30 PWM_VSA 5 BOOT VDRV 10 PT1 1UH +-20% 6.6A
+VCC_GT PR586 100_0402_1% 1000P_0402_50V7K 316_0402_1% 2 PSYS PWM_C 29 FCCM_VSA 1 2 6 PHASE PGND 9 TP@ PL500
1 2 1 2 3 IMON_B FCCM_C 28 7 VIN GL 8 SA_SW 1 2
<15> VCCGT_SENSE NTC_B ISUMN_C PGND VSWH
+VCC_SA
PR526 @EMC@
@ PC517 PR523 4 27 PR524
COMP_B ISUMP_C
0.082U_0402_16V7K
1 2 1.96K_0402_1% 5 26 2.2_0603_5% SIC531CDT1GE3_POWERPAK22_4X3

FB_B RTN_C
4.7_1206_5%
PC519
1 2 6 25 FB_VSA
1
1
330P_0402_50V7K 7 RTN_B FB_C 24 COMP_VSA
ISUMP_B COMP_C
1
PC521 PR525 8 23 IMON_VSA 1_0402_5% 1_0402_5%
C ISUMN_B IMON_C PR527 C
PC520 680P_0402_50V7K 2K_0402_1% 9 22 PR579 PR580
2
1 2 @ 1 2 1 2 10 ISEN1_B PWM_A 21 PWM_IA <59> 2 1 2 1 3.65K_0603_1%

ISEN2_B FCCM_A
ISUMN_A
ISUMP_A
PWM1_B
PWM2_B
COMP_A
2
FCCM_B
FCCM_IA <59>
IMON_A
0.01U_0402_50V7K 41
NTC_A
RTN_A
ISUMP_VSA 2
AGND
1
FB_A
+5VS
SA_SNUB
ISUMN_VSA
<15> VSSGT_SENSE PR585 PC522 PC523 PC534
100_0402_1% 1000P_0402_50V7K 1U_0402_10V6K 1U_0402_10V6K
2
1 2
11
12
13
14
15
16
17
18
19
20
680P_0603_50V7K
ISL95857HRTZ-T_TQFN40_5X5
<59> ISUMP_GT
1
<59> FCCM_GT
@EMC@ PC525
COMP_IA
4.42K_0402_1%
IMON_IA
NTC_IA
1
<59> PWM1_GT
FB_IA
2
2
PR529
PC524
330P_0402_50V7K
10K +-5% 0402 B25/50 4250K
@ PR572
20M_0402_5% 1 2
0.01U_0402_25V7K
PR530
2
11K_0402_1%
0.1U_0402_25V6
84.5K_0402_1%
1
1
10P_0402_50V8J
7.32K_0402_1%
PR532
PC526
PC527
1 2
PR531
PH501 PR533
1
2200P_0402_50V7K
1200P_0402_50V7K
PR534 PC529 470K_0402_5%_ TSM0B474J4702RE 10.5K_0402_1%
2
2
1
PH502
PC528
@ 1K_0402_1% 2200P_0402_50V7K 1 2 1 2
2
1 2 1 2 ISUMP_VSA
2
249_0402_1%
PR536 27.4K_0402_1% 1 2
1
PR538 1 2
2.61K_0402_1%
1
2
PC530
PR537
274_0402_1% PR535 1.4K_0402_1%
2
<59> ISUMN_GT PC533
PC531
1 2 PR541 PR571 @
PR539
2200P_0402_50V7K 3.6K_0402_1% 1 2 1 2 20M_0402_5%
10K +-5% 0402 B25/50 4250K

1 2 1 2
2
.1U_0402_16V7K
0.033U_0402_16V7K
PC532 PR540
1
1
2
6800P_0402_25V7K
1K_0402_1%
11K_0402_1%
PC535 2200P_0402_50V7K 1K_0402_1%
68P_0402_50V8J
PC541
PR542
1
1
PR543
PC537
1 2
PC536
2
1
B PC540 PR545 PR544 PC539 B
1
2200P_0402_50V7K 316_0402_1% 1 2 1 2
+5VALW
330P_0402_50V7K
1 2 1 2
PH503
316_0402_1% 2200P_0402_50V7K
PR546
2
1 2 PR547
1
133K_0402_1%
1 2
1
1.37K_0402_1% @ PC543 ISUMN_VSA
680P_0402_50V7K 2K_0402_1%
PC542
PR548
0.01U_0402_25V7K 1.69K_0402_1% PC544
1
2K_0402_1%
1 2 @ .1U_0402_16V7K
2
.1U_0402_16V7K
1 2 PR584
2
1
PR550
100_0402_1%
PR549
PC545 1 2
2
1 2
PC546
680P_0402_50V7K
0.1U_0402_25V6 VSA_SEN- <13>
2
PC548
PC547
PR581 1 2
2
100_0402_1%
1
1 2 @ PC549
+VCC_CORE 0.01U_0402_50V7K
0.082U_0402_16V7K
1 2
PR551
<15> VCCSENSE 11K_0402_1%
2
PC550
1 2
@ PC552
1
@ PC551 PR552 PH504 @ 330P_0402_50V7K
1 2 4.42K_0402_1% 10K +-5% 0402 B25/50 4250K 1 2
0.082U_0402_16V7K
1 2 1 2
PC553
330P_0402_50V7K
1
VSA_SEN+ <13>
PR570
20M_0402_5% ISUMN_IA <59>
2
PC554 @ 1 2 1 2
A
1 2 +VCC_SA A
100_0402_1%
0.01U_0402_50V7K ISUMP_IA <59> PR583
<15> VSSSENSE
PR582
100_0402_1%
1 2 Security Classification Compal Secret Data Compal Electronics, Inc.
PWR-CPU_VCC_SA
Local sense put on HW site AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
5 4 3 2 1
5 4 3 2 1
D D
VCC_core
TDC 21A VCC_GT
Peak Current 28A TDC 18A
CPU_B+ OCP current 34A CPU_B+ Peak Current 31A
Choke DCR 0.66 +-7%m ohm OCP current 37A
Choke DCR 0.66 +-7%m ohm
PC558 @EMC@
PC559 @EMC@
PC575 @EMC@
PC576 @EMC@
2200P_0402_50V7K
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
1
1
PC555
PC556
PC557
PC572
PC573
PC574
2
2
+5VS +5VS
<58>
<58>
<58>
<58>
PWM1_GT
PWM_IA
FCCM_GT
FCCM_IA
2
2
1_0402_5%
1_0402_5%
PR573
PR574
2
10K_0402_5%
10K_0402_5%
1_0402_5%
1
2
1_0402_5%
PR576
PR578
1
1
PR575
PR577
1U_0402_10V6K
1U_0402_10V6K
@
@
1
2
0_0402_5%
0_0402_5%
1
PC567
PR556
PC580
PR569
2
PU502 PU503
2
2
C C
1 28 1 28
1
1
2 PWM CGND 27 PC569 2 PWM CGND 27 PC570
3 ZCD_EN# GL 26 1U_0402_10V6K 3 ZCD_EN# GL 26 1U_0402_10V6K
PC560 4 VCIN DSBL# 25 PC578 4 VCIN DSBL# 25
1 2 5 CGND THWn 24 1 2 PL503 1 2 5 CGND THWn 24 1 2 PL504
6 BOOT VDRV 23 0.15UH_PCME064T-R15MS_36A_20% 6 BOOT VDRV 23 0.15UH_PCME064T-R15MS_36A_20%
0.22U_0402_16V7K NC PGND 0.22U_0402_16V7K NC PGND
1 2 7 22 PT2 1 2 7 22 PT3
PR553 8 PHASE GL 21 TP@ CORE_SW 1 4 PR564 8 PHASE GL 21 TP@ GT_SW 1 4
VIN SW
+VCC_CORE VIN SW
+VCC_GT
1000P_0402_50V7K
PR554 @EMC@
PR565 @EMC@
4.7_0603_5% 9 20 4.7_0603_5% 9 20
10 VIN SW 19 2 3 10 VIN SW 19 2 3
PGND SW PGND SW
4.7_1206_5%
4.7_1206_5%
11 18 11 18
2GT1P
1
1
SW SW SW SW
1000P_0402_50V7K
PC561
12 17 12 17
1
1
SW SW SW SW
PC579
13 16 PR555 13 16
14 SW SW 15 14 SW SW 15
2
SW SW 3.65K_0603_1% SW SW PR567
2
SIC632CDT1GE3_POWERPAK31_5X5 SIC632CDT1GE3_POWERPAK31_5X5 3.65K_0603_1%
2
2
2
CORE_SNUB
1
GT_SNUB1
680P_0603_50V7K
680P_0603_50V7K
1
@EMC@ PC568
@EMC@ PC581
<58>
<58>
<58>
<58>
ISUMP_GT
ISUMN_GT
ISUMP_IA
ISUMN_IA
2
2
B B
A A

PWR-CPU_VCC_CORE/GT
USTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
5 4 3 2 1
5 4 3 2 1
+VGA_CORE
D D
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1U_0402_10V6K
1
1
PC927
PC928
PC929
PC930
PC931
PC932
PC933
PC934
2
2
22U_0805_6.3VAM
22U_0805_6.3VAM
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0603_6.3V
4.7U_0603_6.3V
4.7U_0603_6.3V
1 1
1
1
PC951
PC952
PC953
PC944
PC945
PC946
PC947
PC948
PC949
PC950
2
2
2 2
C C
4.7U_0603_6.3V
4.7U_0603_6.3V
4.7U_0603_6.3V
4.7U_0603_6.3V
4.7U_0603_6.3V
4.7U_0603_6.3V
4.7U_0603_6.3V
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1 1 1 1 1
470U_D2_2VM_R4.5M~D
470U_D2_2VM_R4.5M~D
470U_D2_2VM_R4.5M~D
470U_D2_2VM_R4.5M~D
470U_D2_2VM_R4.5M~D
1 1 1 1 1
1
1
PC954
PC955
PC956
PC957
PC958
PC959
PC960
+ + + + +
PC961
PC962
PC963
PC964
PC965
PC966
PC967
PC968
PC969
PC970
2
2 2 2 2 2 2 2 2 2 2
B B
A A

PWR-GPU DECOUPLING
5 4 3 2 1
4
3
2
1
+VCC_SA
+VCC_CORE
A
A
2
1
+
2 1 220U 2.5V Y D2 ESR9M H1.9 SX 2 1 2 1
2
1
2
1
2
1
PC1121
PC1142 PC1129 PC1088 PC1056 PC1031 PC1000
2
1
+
1U_0201_6.3V6M 10U_0402_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 22U_0603_6.3V6M
2 1 220U 2.5V Y D2 ESR9M H1.9 SX 2 1 2 1
2
1
2
1
2
1
PC1122
PC1143 PC1130 PC1089 PC1057 PC1032 PC1001
2 1 2 1 2 1
2
1
2
1
2
1
PC1144 PC1131 PC1090 PC1058 PC1033 PC1002

2 1 2 1 2 1
2
1
2
1
2
1
PC1145 PC1132 PC1091 PC1059 PC1034 PC1003

2 1 2 1 2 1
2
1
2
1
2
1
PC1146 PC1133 PC1092 PC1060 PC1035 PC1004

2 1 2 1 2 1
2
1
2
1
2
1
PC1147 PC1134 PC1093 PC1061 PC1036 PC1005

2 1 2 1 2 1
2
1
2
1
2
1
PC1148 PC1135 PC1094 PC1062 PC1037 PC1006

2 1 2 1
2
1
2
1
2
1
2
1
PC1149 PC1136 PC1095 PC1063 PC1038 PC1007

2 1 2 1
B
B
2
1
2
1
2
1
2
1
PC1150 PC1137 PC1096 PC1064 PC1039 PC1008

2 1 2 1
2
1
2
1
2
1
PC1138 PC1097 PC1065 PC1040 PC1009

10U_0402_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 47U_0805_6.3V6M 10U_0402_6.3V6M
2 1 2 1
2
1
2
1
2
1
PC1139 PC1098 PC1066 PC1041 PC1010

2 1 2 1
2
1
2
1
2
1
PC1140 PC1099 PC1067 PC1042 PC1011

2 1 2 1
2
1
2
1
2
1
PC1141 PC1100 PC1068 PC1043 PC1012

2 1 2 1
2
1
PC1101 PC1069 PC1013

1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M
2 1 2 1
2
1
PC1102 PC1070 PC1014

1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M
2 1 2 1
2
1
PC1103 PC1071 PC1015

1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M
2 1 2 1
2
1
Issued Date
PC1104 PC1072 PC1016
C
C
1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M

2 1
2
1
PC1105 PC1017
1U_0201_6.3V6M 10U_0402_6.3V6M
2
1
PC1018
10U_0402_6.3V6M
2015/01/06
+VCC_GT
2 1
PC1123 2 1 2 1
2
1
2
1
2
1
2
1
1U_0201_6.3V6M
2 1 PC1106 PC1073 PC1163 PC1151 PC1044 PC1019
PC1124 2 1 2 1
2
1
2
1
2
1
2
1
1U_0201_6.3V6M
Compal Secret Data

2 1 PC1107 PC1074 PC1165 PC1152 PC1045 PC1020
Deciphered Date
PC1125 2 1 2 1
2
1
2
1
2
1
2
1
1U_0201_6.3V6M
2 1 PC1108 PC1075 PC1164 PC1153 PC1046 PC1021
D
D
PC1126 2 1 2 1
2
1
2
1
2
1
2
1
1U_0201_6.3V6M
PC1109 PC1076 PC1167 PC1154 PC1047 PC1022
2
1
+

220U 2.5V Y D2 ESR9M H1.9 SX 2 1 2 1
2
1
2
1
2
1
2
1
PC1127
2016/01/06
PC1110 PC1077 PC1166 PC1155 PC1048 PC1023

2
1
+

220U 2.5V Y D2 ESR9M H1.9 SX 2 1 2 1
2
1
2
1
2
1
2
1
PC1128
PC1111 PC1078 PC1169 PC1156 PC1049 PC1024
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2 1 2 1
2
1
2
1
2
1
2
1
PC1112 PC1079 PC1168 PC1157 PC1050 PC1025


2 1 2 1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2
1
2
1
2
1
2
1
Size
Title
Date:
@
PC1113 PC1080 PC1171 PC1158 PC1051 PC1026

2 1 2 1
2
1
2
1
2
1
2
1
PC1114 PC1081 PC1170 PC1159 PC1052 PC1027

2 1 2 1
2
1
2
1
2
1
2
1
Document Number
@
PC1115 PC1082 PC1172 PC1160 PC1053 PC1028

2 1 2 1
LA-C901P
2
1
2
1
2
1
2
1
PC1116 PC1083 PC1173 PC1161 PC1054 PC1029

Tuesday, August 04, 2015

2 1 2 1
2
1
2
1
2
1
2
1
PC1117 PC1084 PC1174 PC1162 PC1055 PC1030

E
E

2 1 2 1
2
1
2
1
Sheet
PC1118 PC1085 PC1178 PC1175

1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1
2
1
2
1
61
PWR-CPU DECOUPLING
PC1119 PC1086 PC1179 PC1176

1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M
of
2 1 2 1
2
1
2
1
PC1120 PC1087 PC1180 PC1177

63
1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M

Rev
1.0
4
3
2
1
5 4 3 2 1
Power block
CPU OTP
Page 51
D Turn Off D
Input B+
DC IN +3VALWP: TDC:5.6A
Switch +5VALWP: TDC:9.5A Always
Page 52
TPS51225CRUKR Page 53
CHARGER +1.35VP/+0.675VSP:TDC:16.7A/0.7A
CC:3.5A PM_SLP_S4#
RT8207MZQW
CV:17.7V Page 54
BQ24780S
Page 52
C C
+1.0VALWP: TDC:7A +1.8V_PG
Battery TPS51212DSCR
Page 55
+1.05VSP: TDC:2A 3V3_MAIN_EN

SY8032ABC
Page 56
+1.8VALWP: TDC:0.27A PCH_PWR_EN

APL5930QBI
Page 56
+VGA_CORE
3V3_MAIN_EN TDC:51.1A
B RT8813AGQW B
Page 57
+VCC_CORE
TDC: 21A
+VCC_GT
VR_ON
TDC:18
+VCC_SA
TDC:4A
ISL95857HRTZ
Page 58,59
A A

PWR_POWER BLOCK DIAGRAM
Size
5 4 3 2 1
5 4 3 2 1

Request
D
1 56 1.05VS_VGA 2015/3/6 Compal_PWR For EE request to fine tune power sequence. Change PR812 from 33k to 62k. X01 D
Change PR615 from 33k to 0.

2 57 VGA_CORE 2015/3/6 Compal_PWR For EE request to fine tune power sequence. Non-pop PC618. X01
Change PR550 from 2kOhm to @. X01

3 58,59 CPU 2015/4/1 Compal_PWR For CPU transient and DC/DC EA fine tune. Change PC547 from 680pF to @.
Change PC543 from 0.01uF to @.
Change PC527 from 0.01uF to @.
Change PR552 from 2.61kOhm to 4.42kOhm.
Change PR529 from 2.61kOhm to 4.42kOhm.
Change PC516 from 2200pF to 1000pF.
Change PR570 from @ to 20MOhm.
Change PR553,PR564 from 2.2 to 4.7ohm
4 54 1.35VP 2015/4/7 Compal_PWR For EE request to fine tune power sequence. Add PR210 to connect with PM_SLP_S4# , non-pop PR208. X01
C C
5 54 1.35VP 2015/4/8 Compal_PWR For fine tune OCP. Change PR201 from 8.06kohm to 10kom. X01
6 55 1.0VALWP 2015/4/8 Compal_PWR Improve output ripple voltage. Add PC307. X01
7 51 DCIN/BATT CONN/OTP 2015/5/20 Compal_PWR For change CPU OTP point. Change PR24 from 12.1k to 16.2k. X04
8 51 DCIN/BATT CONN/OTP 2015/7/8 Compal_PWR For cost down removed baed remove PL1,PL2,PL3 1.0
9 57 VGA_CORE 2015/7/8 Compal_PWR For cost down change baed to jumper Add PJ600
B B
10 53 3.3VALWP 2015/7/8 Compal_PWR For cost down removed baed remove PL101
1.0
11 56 1.8V_PRIM 2015/7/8 Compal_PWR HW didn't need this. remove PR811 remove PR811
1.0
A A

PWR-PIR
Size
5 4 3 2 1

Dell Alienware 13 R2 LA-C901P Rev1.0 (A00) PDF

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Dell Alienware 13 R2 LA-C901P Rev1.0 (A00) PDF

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A B C D E

MODEL NAME : AAP01

DA40023X000 LS-C902P SSD/B (w/o redriver)

PCB 1FU LA-C901P REV0 M/B MLK 3

PCB 1FU LA-C901P REV1 MB MLK TRIP 3 A31!

HDMI@ ROYALTY HDMI W/LOGO

RO0000002HM HDMI W/Logo:RO0000002HM

Layout Dell logo

Security Classification Compal Secret Data Compal Electronics, Inc.

panel KXCNL-1010 NCT7718W (Reserve)

P.47 P.44,45 P.18,19

SSD 1 SATA3.0 port0,1

Security Classification Compal Secret Data Compal Electronics, Inc.

Power Button Out

Board ID Table for AD channel

2 15K DVT-1.1(R0.3) PCI EXPRESS

Lane 7~8 M.2 SATA+PCIeX2

Security Classification Compal Secret Data Compal Electronics, Inc.

SKYLAKE R9 SOC_SML0CLK 11 CLK BUFFER 4 FFS SMBUS Address [0x1D]

8 UF1 SMBUS Address [0x98]

8 UF2 SMBUS Address [0x9A]

Security Classification Compal Secret Data Compal Electronics, Inc.

UC1 UC1 UC1A SKL-U

+3V_PRIM Change from +3VALW to +3V_PRIM to fix leakage on S5

Place to CPU side

Buffer with Open Drain Output

+1.35V_VDDQ +3VALW +3VS

Security Classification Compal Secret Data Compal Electronics, Inc.

RC21/44 place to within 1100 mil of SPIO_MOSI/SPI0_IO2 pin for CMC

SOC_SPI_CS#0 RC53 1 @ 2 1K_0402_1%

Single SPI ROM_CS0#

#545659 SKL_PCH_EDS_R0.7 P.84 UC1G SKL-U

To Enable ME Override Reserve RC229 follow TD team dat.04/23

+3VS TD Team Solution ABO Solution

RC105 1 2 10K_0402_5% CLKREQ_PCIE#5 +1.0V_CLK5_F24NS Closed to CPU

+3V_PRIM From 543016_SKL_PDG_UY_v1.0

H_CPUPWRGD As Short As Possible GPP_B12/SLP_S0#

60.4_0402_1% 1 2015/01/06 2016/01/06 Title

RC203 2 1 10K_0402_5% SOC_GPIOB21

8 1 I2C_1_SDA VGA_ID GPP_D9 RANK_ID GPP_D10 Project_ID1 Project_ID0

<44> RTD3_CIO_PW R_EN RTD3_CIO_PW R_EN AN8 P2 VGA_ID

RC118 1 @ 2 2.2K_0402_5% GSPI0_MOSI

RC201 1 @ 2 2.2K_0402_5% GSPI1_MOSI

GSPI0_MOSI (Internal Pull Down):

0 = Disable No Reboot mode. --> AAX05 Use

1 = Enable No Reboot Mode. (PCH will disable the TCO

Security Classification Compal Secret Data Compal Electronics, Inc.

For Power consumption Measurement +1.35V_VDDQ +1.35V_VDDQ_CPU +1.0VS_VCCIO

2 +5VALW +1.35V_VDDQ_CPU +1.35V_VDDQ_CPU +1.35V_VCCSFR_OC

RC188 1 @ 2 0_0402_1% CC89 1 2 0.1U_0402_25V6

UC12 3 Imax : 3 A BSC Side

BSC Side PSC Side PSC Side BSC Side

CC93 Follow 543016_SKL UY PDG_rev1_3

RC161 1 @ 2 0_0402_1% RC176 1 @ 2 0_0603_1% AN13 PRIMCORE_VID1 T131 TP@

+1.0V_DTS SY6288C20AAC_SOT23-5 +3VALW

RC1741 @ 2 0_0402_5% EN_3V_PRIM

I (Max) : 2.766 A(+1.0V_MPHYPLL)

Trace Length < 25 mils @ SKL-U_BGA1356

RC179 For 2+3e Solution

1 : Disabled; No Physical Display Port

0 : Enabled; An external Display Port device is

<6> CFG0 CFG0 E68 BB68 T156 TP@

DDR_A_CLK#0 103 104 DDR_A_CLK#1