Salado 14 HSW DSC MB La-9934p r1.0

A B C D E
COMPAL CONFIDENTIAL
MODEL NAME : VAL91
1
PCB NO : LA-9934P(eDP) 1
GPIO P/N: 2012.8.1 Rev 2.7

BOM P/N :
X76 of SPI:
SALADO 14 HSW DSC
X7650731L03 HASWELL + LYNX POINT
SA000039A30 (64M W25Q64FVSSIQ)
SA00003K820 (32M W25Q32FVSSIQ) 2013-07-04
X7650731L04
SA00006N000 (32M MX25L3273EM2I-10G) REV : 1.0 (A00)
2
SA00006N100
X76 of VRAM: (64M MX25L6473EM2I-10G) @ : Nopop Component 2
X7650731L53 - SAMSUNG CONN@ : Connector Component

SA00006EU1L (128M32 K4G41325FC-HC04)
SD034453180 (4.53K +-1% 0402)
SPI@ : For X76 SPI
X7650731L54 - HYNIX VRAM@ : For X76 VRAM
SA00006O41L (128M32/2.5G H5GC4H24MFR-T2C)
SD000000680 (8.45K +-1% 0402) 14DSC
EMC@: EMI/RF/ESD ask to add V
CXDP@ : CPU XDP
PXDP@ : PCH XDP
3 3
4 4
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
Compal Electronics, Inc.
Title
MB PCB
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Part Number Description
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Cover Page
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
1.0
DAA0006L000 PCB 0YH LA-9932P REV0 M/B DSC 6 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD LA-9934P
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Date: Wednesday, May 07, 2014 Sheet 1 of 71
A B C D E
A B C D E
Block Diagram AMD

VRAM GDD5 X4 SUN XT S3 PEG Gen3 x8Lane
P54-55
P49-53
Intel DDR3L-DIMM X2
1
eDP CONN iEDP 2Lane Memory BUS (DDR3L) 1
P28
HasWell 1333/1600 MHz BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
P13-14
rPGA CPU
HDMI level shifter DPB
HDMI CONN PS8401A
947 Pins
P26
P26
USB2.0[12] Camera Through LVDS Cable
DPC P28
DPD P6-12
DOCKING Dock VGA
P44 FDI DMI
USB3.0[1]
LANEX2 LANEX4
USB2.0[0] JUSB1
DAI SLG55584AVTR USB P40
USB2.0[0]
USB2.0 [3,6] Power Share P40
SATA2
DOCK LAN
Intel USB3.0[2]
USB2.0[1] JUSB2
(PERN1/USBRN3) Lynx Point USB P41
iVGA
VGA Video Switch BGA USB3.0[5]
USB2.0[2]
CRT CONN TS3V713ELRTGR JUSB3 P42
695 Pins
2 2
P25
on IO board
P15-23 USB3.0[6] USB3.0 Repeater USB3.0[6] IO/B
Card Reader PS8713 USB2.0[9]

SD4.0/MMC PCIE2 JUSB4
OZ777FJ2LN
P36 P36
(PERN2/USBRN4)
HD Audio I/F
PCIE
SPI
Intel Clarkville
PCIE7 PCIE6 PCIE3 S-ATA 0/1/2/3/4/5 6GB/s
I217LM
P33
EXPRESS 1/2 Mini Card 1/2 Mini Card Full Mini Card
SATA1
SATA0
SATA3
Card Pink Pather WLAN/BT,WiGig WWAN/mSATA W25Q64FV DOCK LAN LAN SWITCH
P39 P37 P37 P38 SATA_TXN4/PETN1 P18 To Docking side PI3L720 P33
USB2.0[10] USB2.0[8] USB2.0[4] USB2.0[5] 64M 4K sector
W25Q32FV RJ45
3 3
P18 P34
Smart Card TDA8034HN USH
32M 4K sector
BCM5882
RFID HDD HDA Codec INT.Speaker

P31
Fingerprint FP_USB USB2.0[7] ALC3226 P30
CONN USH Module P30
CPU XDP Port LPC BUS PCIE4 E-Module FFS

P7 33MHz P32
LNG3DMP31
SMSC SIO Combo Jack
BC BUS P30
PCH XDP Port
P15
MEC5048
P45
DAI
To Docking side
WiFi ON/OFF SMSC KBC

on SNIFFER board
MEC5075 Discrete TPM
P46 Dig. MIC
DC/DC Interface AT97SC3204
P48
P35
4 Through LVDS Cable 4
LED P24
TP CONN KB CONN
P47 P47
PWM FAN DELL CONFIDENTIAL/PROPRIETARY
P46
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Block Diagram
1.0
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD LA-9934P
A B C D E
5 4 3 2 1
USB 2.0 USB 3.0

PORT# PORT# DESTINATION
POWER STATES
0 1 Rear Side (JUSB1)
Signal SLP SLP SLP SLP ALWAYS M SUS RUN CLOCKS
State S3# S4# S5# A# PLANE PLANE PLANE PLANE
1 2 Right Side TOP (JUSB2)
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON 2 5 Right Side bottom (JUSB3)
D D
S3 (Suspend to RAM) / M3 LOW HIGH HIGH HIGH ON ON ON OFF OFF 3 3 (PERN1/USBRN3) DOCKING (JDOCK1)
S4 (Suspend to DISK) / M3 LOW LOW HIGH HIGH ON ON OFF OFF OFF 4 WLAN (JMINI2)
S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF 5 WWAN (JMINI1)
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON OFF ON OFF OFF PCH 6 DOCKING (JDOCK1)
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF 7 USH (JUSH1)
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF 8 Pink Pather (JMINI3)
9 6 Left Side (JUSB4)

PM TABLE
10 Express card (JEXP1)
+PWR_SRC +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M
C C
+PWR_SRC_S +1.35V_MEM +3.3V_RUN +1.05V_M +1.05V_M 11 None
+5V_ALW +1.5V_RUN (M-OFF)
power
plane +3.3V_ALW +0.675V_DDR_VTT 12 CAMERA (JCAM1)
+3.3V_ALW_PCH +VCC_CORE
+3.3V_RTC_LDO +1.05V_RUN 13 LCD Touch
+GPU_CORE
+1.35V_MEM_GFX
State
+1.8V_RUN_GFX PCI EXPRESS DESTINATION
+VGA_PCIE SATA DESTINATION
+3.3V_RUN_GFX Lane 1 (SATA_TXN4/PETN1) WWAN (JMINI1) SATA by default
+VDDCI SATA 0 HDD (JSATA1)
Lane 2 (SATA_RXN5/PERN2) None
SATA 1 ODD (JSATA2)
S0 ON ON ON ON ON Lane 2 (PERN2/USBRN4) 10/100/1G LOM
SATA 2 Dock (JDOCK1)
S3 ON ON OFF ON OFF Lane 3 WLAN (JMINI2) SATA 3 NA
B S5 S4/AC ON OFF OFF ON OFF Lane 4 E3 Module Bay (JSATA2) B
SATA 4 (SATA_TXN4/PETN1) WWAN (JMINI1)

S5 S4/AC don't exist OFF OFF OFF OFF OFF Lane 5 None SATA by default
Lane 6 Pink Pather (JMINI3)
Lane 7 Express card (JEXP1)
Lane 8 MMI
DISPLAY Ports
Connetion
On CPU
DDIB MB HDMI (JHDMI1)
A
DDIC Dock DP port 1 A
DDID Dock DP port 2

PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Index and Configuration
1.0
5 4 3 2 1
5 4 3 2 1
EN_INVPWR FDC654P
D +BL_PWR_SRC D
Q21
BATTERY
MODC_EN
DGPU_PWR_EN# ISL62883CHRTZ-T
+GPU_CORE
(PU600)
+PWR_SRC
RUN_ON
ADAPTER
TPS22966
(U37)
+5V_RUN
CHARGER
BQ24717 +5V_MOD
C
(PU700) ALWON C
TPS51225
+5V_ALW
(PU100) +5V_HDD Pop option
+5V_RUN
SYN470DBC
0.75V_DDR_VTT_ON
RUN_ON
+1.5V_RUN
PU400
IMVP_VR_ON
SUS_ON
A_ON
+3.3V_ALW
MCARD_WWAN_PWREN
DGPU_PWR_EN#_Q
MCARD_MISC_PWREN
DGPU_PWR_EN#
DGPU_PWR_EN#
AUX_EN_WOWL
EN_LCDPWR
ISL95812 RT8207MZQW TPS51212DSCR
SIO_SLP_LAN#
RUN_ON
B (PU500) (PU200) (PU300) SUS_ON B
PCH_ALW_ON
A_ON
SY8036L G971 APL3512 TPS22966 TPS22966 TPS22966 TPS22966 TPS22965

+VCC_CORE +1.35V_MEM +0.675V_DDR_VTT +1.05V_M
(PU602) (PU603) (U148) (U57) (U36) (U146) (U145) (UV60)
RUN_ON
DGPU_PWR_EN#
+3.3V_ALW +3.3V_PCIE +3.3V_PCIE
+VGA_PCIE +1.8V_RUN_GFX +LCDVDD +3.3V_WLAN +3.3V_LAN +3.3V_SUS +3.3V_M +3.3V_RUN +3.3V_RUN_GFX
_PCH _FLASH _WWAN
SI4164
SI4164 (Q63)
(QV1)
A A
+1.05V_RUN DELL CONFIDENTIAL/PROPRIETARY

+1.35V_MEM_GFX PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Power Rail
1.0
5 4 3 2 1
5 4 3 2 1
2.2K
SMBUS Address [0x9a]
2.2K
+3.3V_ALW_PCH
R10 MEM_SMBCLK 202
MEM_SMBDATA
2N7002
U11 200 DIMMA SMBUS Address [A0]
2N7002
2.2K
D 202 D
PCH
+3.3V_LAN 200 DIMMB
2.2K SMBUS Address [A4]
U8 LAN_SMBCLK 28
LAN_SMBDATA 31 LOM SMBUS Address [C8]
R7
N11 K6 53
51 XDP1 SMBUS Address [TBD]
2.2K
SML1_SMBDATA
SML1_SMBCLK
+3.3V_ALW_PCH
2.2K 53
51 XDP2
A5 B6 2.2K SMBUS Address [TBD]
SMBUS Address
3A 3A APR_EC: 0x48
2.2K +3.3V_ALW SPR_EC: 0x70 10K
MSLICE_EC: 0x72
B4 DOCK_SMB_CLK 127
1A USB: 0x59
129 AUDIO: 0x34 10K
+3.3V_RUN
1A A3 DOCK_SMB_DAT DOCKING
SLICE_BATTERY: 0x17
SLICE_CHARGER: 0x13 4
G Sensor
@ 2.2K 6 SMBUS Address [0x3B]
C C
+LCD_VDD
@ 2.2K
B5 LCD_SMBCLK
1B
1B A4 LCD_SMDATA
13
2.2K 14 eDP to LVDS CONVERTER SMBUS Address TBD
KBC 2.2K
+3.3V_ALW
100 ohm 7
1C A56 PBAT_SMBCLK
100 ohm 6 BATTERY SMBUS Address [0x16]
1C B59 PBAT_SMBDAT CONN
2.2K
+3.3V_SUS
2.2K
USH_SMBCLK M9
1E A50
L9 USH SMBUS Address [0xa4]
1E B53 USH_SMBDAT
2.2K
B B
+3.3V_SUS
2.2K
MEC 5075 7
2B A49 CARD_SMBCLK
8 Express card SMBUS Address [TBD]
2B B52 CARD_SMBDAT
2.2K
+3.3V_ALW
2.2K
B50 CHARGER_SMBCLK
1G 9
A47 CHARGER_SMBDAT Charger SMBUS Address [0x12]
1G 8
2.2K
+3.3V_ALW
2.2K
B7 BAY_SMBDAT 29
2D
30 E3 Module Bay SMBUS Address [0xd2]
A7 BAY_SMBCLK
2D
100 2
2.2K
100 3 MBATT
A +3.3V_RUN A
2.2K
B49 GPU_SMBCLK 8
2A
B48 GPU_SMBDAT 9 GPU SMBUS Address [0xXX]
2A
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SMBus block diagram
1.0
5 4 3 2 1
5 4 3 2 1
+VCOMP_OUT
PEG_COMP 2 1
D 24.9_0402_1% RC1 D
CAD Note:
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils.
JCPU1A Haswell rPGA EDS
E23 PEG_COMP
PEG_RCOMP M29 PEG_CRX_GTX_N0 PEG_CRX_GTX_N[0..7] <49>
D21 PEG_RXN_0 K28 PEG_CRX_GTX_N1
<16> DMI_CRX_PTX_N0 C21 DMI_RXN_0 PEG_RXN_1 M31 PEG_CRX_GTX_N2 PEG_CTX_GRX_P[0..7]
<16> DMI_CRX_PTX_N1 B21 DMI_RXN_1 PEG_RXN_2 L30 PEG_CRX_GTX_N3 PEG_CTX_GRX_P[0..7] <49>
<16> DMI_CRX_PTX_N2 A21 DMI_RXN_2 PEG_RXN_3 M33 PEG_CRX_GTX_N4 PEG_CTX_GRX_N[0..7]
<16> DMI_CRX_PTX_N3 DMI_RXN_3 PEG_RXN_4 L32 PEG_CTX_GRX_N[0..7] <49>
PEG_CRX_GTX_N5
D20 PEG_RXN_5 M35 PEG_CRX_GTX_N6
<16> DMI_CRX_PTX_P0 C20 DMI_RXP_0 PEG_RXN_6 L34 PEG_CRX_GTX_N7
<16> DMI_CRX_PTX_P1 B20 DMI_RXP_1 PEG_RXN_7 E29
<16> DMI_CRX_PTX_P2 A20 DMI_RXP_2 PEG_RXN_8 D28
<16> DMI_CRX_PTX_P3
DMI
DMI_RXP_3 PEG_RXN_9 E31
D18 PEG_RXN_10 D30
<16> DMI_CTX_PRX_N0 DMI_TXN_0 PEG_RXN_11
<16> DMI_CTX_PRX_N1 C17 E35
B17 DMI_TXN_1 PEG_RXN_12 D34
<16> DMI_CTX_PRX_N2 DMI_TXN_2 PEG_RXN_13
<16> DMI_CTX_PRX_N3 A17 E33
DMI_TXN_3 PEG_RXN_14 E32
D17 PEG_RXN_15 L29 PEG_CRX_GTX_P0 PEG_CRX_GTX_P[0..7] <49> PEG_CTX_GRX_C_P0 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P0
<16> DMI_CTX_PRX_P0 CC1
C18 DMI_TXP_0 PEG_RXP_0 L28 PEG_CRX_GTX_P1 PEG_CTX_GRX_C_N0 CC2 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N0
<16> DMI_CTX_PRX_P1 DMI_TXP_1 PEG_RXP_1
<16> DMI_CTX_PRX_P2 B18 L31 PEG_CRX_GTX_P2
C A18 DMI_TXP_2 PEG_RXP_2 K30 PEG_CRX_GTX_P3 PEG_CTX_GRX_C_P1 CC3 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P1 C
<16> DMI_CTX_PRX_P3 DMI_TXP_3 PEG_RXP_3 L33 PEG_CRX_GTX_P4 PEG_CTX_GRX_C_N1 CC4 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N1
PEG_RXP_4 K32 PEG_CRX_GTX_P5
PEG_RXP_5 L35 PEG_CRX_GTX_P6 PEG_CTX_GRX_C_P2 CC5 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P2
PEG_RXP_6 K34 PEG_CRX_GTX_P7 PEG_CTX_GRX_C_N2 CC6 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N2
PEG_RXP_7 F29
PEG_RXP_8
PEG
H29 E28 PEG_CTX_GRX_C_P3 CC7 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P3
<16> FDI_CSYNC
FDI
J29 FDI_CSYNC PEG_RXP_9 F31 PEG_CTX_GRX_C_N3 CC8 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N3
<16> FDI_INT DISP_INT PEG_RXP_10 E30
PEG_RXP_11 F35 PEG_CTX_GRX_C_P4 CC9 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P4
PEG_RXP_12 E34 PEG_CTX_GRX_C_N4 CC10 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N4
PEG_RXP_13 F33
PEG_RXP_14 D32 PEG_CTX_GRX_C_P5 CC11 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P5
PEG_RXP_15 H35 PEG_CTX_GRX_C_N0 PEG_CTX_GRX_C_N5 CC12 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N5
PEG_TXN_0 H34 PEG_CTX_GRX_C_N1
PEG_TXN_1 J33 PEG_CTX_GRX_C_N2 PEG_CTX_GRX_C_P6 CC13 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P6
PEG_TXN_2 H32 PEG_CTX_GRX_C_N3 PEG_CTX_GRX_C_N6 CC14 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N6
PEG_TXN_3 J31 PEG_CTX_GRX_C_N4
PEG_TXN_4 G30 PEG_CTX_GRX_C_N5 PEG_CTX_GRX_C_P7 CC15 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P7
PEG_TXN_5 C33 PEG_CTX_GRX_C_N6 PEG_CTX_GRX_C_N7 CC16 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N7
PEG_TXN_6 B32 PEG_CTX_GRX_C_N7
PEG_TXN_7 B31
PEG_TXN_8 A30
PEG_TXN_9 B29
PEG_TXN_10 A28
PEG_TXN_11 B27
PEG_TXN_12 A26
PEG_TXN_13 B25
PEG_TXN_14 A24
PEG_TXN_15 J35 PEG_CTX_GRX_C_P0
PEG_TXP_0 G34 PEG_CTX_GRX_C_P1
PEG_TXP_1 H33 PEG_CTX_GRX_C_P2
B PEG_TXP_2 G32 PEG_CTX_GRX_C_P3 B
PEG_TXP_5 B33 PEG_CTX_GRX_C_P6
PEG_TXP_6 A32 PEG_CTX_GRX_C_P7
PEG_TXP_7 C31
PEG_TXP_8 B30
PEG_TXP_9 C29
PEG_TXP_10 B28
PEG_TXP_11 C27
PEG_TXP_12 B26
PEG_TXP_13 C25
PEG_TXP_14 B24
PEG_TXP_15
1 OF 9
LOTES_AZIF0012-P002B_HASWELL
CONN@
A A
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT CPU (1/7)
1.0
5 4 3 2 1
5 4 3 2 1
SM_DRAMPWROK with DDR Power Gating Topology

+VCCIO_OUT
+PCH_VCCDSW3_3
+1.35V_MEM
+PCH_VCCDSW3_3
0.1U_0402_25V6
0.1U_0402_25V6
1 2 PM_DRAM_PWRGD_A
CXDP@ CC17
CXDP@ CC18
RC12 100K_0402_5% 1 1
1
+VCCIO_OUT
1.8K_0402_1%
CC19 @
1 2
RC6
1 2 RUNPWROK_R
@ RC5 100K_0402_5% 0.1U_0402_25V6 2 2
1 2 1.35V_SUS_PWRGD
2
5
@ RC9 6.8K_0402_5% JXDP1
2 1 RUNPWROK_R 1 XDP_PREQ# 1
P
D <46> RUNPWROK B OBSFN_A0 D
@ RC7 0_0402_5% 4 RUNPWROK_AND 2 1 PM_DRAM_PWRGD_CPU XDP_PRDY# 2
2 1 PM_DRAM_PWRGD_A 2 O @ RC10 0_0402_5% 3 OBSFN_A1
<16> PM_DRAM_PWRGD
G
@ RC13 0_0402_5% A UC1 4 GND
Place near JXDP1 OBSDATA_A[0]
3.3K_0402_1%
74AHC1G09GW_TSSOP5 5
39_0402_5%
3
OBSDATA_A[1]
1
@ RC15
6
GND
RC16
7
CFG3 8 OBSDATA_A[2]
<10> CFG3 OBSDATA_A[3]
RC20 need to close to JCPU1 9
H_CPUPWRGD CXDP@ RC20 1 2 1K_0402_1% H_CPUPWRGD_XDP 10 GND
2
HOOK0
L2N7002WT1G_SC-70-3
CXDP@ RC21 1 2 0_0402_5% CFD_PWRBTN#_XDP 11
1 1
<15,16> SIO_PWRBTN#_R HOOK1
@ QC1
CXDP@ RC22 1 2 0_0402_5% CPU_PWR_DEBUG_R 12
D <11> CPU_PWR_DEBUG HOOK2
@ RC24 1 2 0_0402_5% SYS_PWROK_XDP 13
@ QC5 <16,45> SYS_PWROK HOOK3
2 14
<46,48> RUN_ON_ENABLE# HOOK4
L2N7002WT1G_SC-70-3 G 15
16 HOOK5
S
3
RUNPWROK_AND 1 3 PM_DRAM_PWRGD_CPU CPU_PLTRST#_R 1 2 XDP_RST#_R 17 VCCOBS_AB
S
CXDP@ RC23 1K_0402_1% XDP_DBRESET# 18 HOOK6
19 HOOK7
XDP_TDO 20 GND
G
2
XDP_TRST# 21 TDO
2 1 RUNPWROK_R XDP_TDI 22 TRSTn
<13,14,18> DDR_HVREF_RST_PCH TDI
@ RC104 0_0402_5% XDP_TMS 23
2 1 24 TMS 27
<46,58> 1.35V_SUS_PWRGD TCK1 GND
@ RC103 0_0402_5% 1 25 28
XDP_TCLK 26 GND GND
CC138 TCK0
0.01U_0402_16V7K Refer CRB 1.5 MOLEX_52435-2671
2 CONN@
C C
JCPU1B Haswell rPGA EDS

Refer CRB 1.5
+1.05V_RUN CPU_DETECT# AP32 MISC AP3 SM_RCOMP0 +3.3V_ALW_PCH
DDR3L
+VCCST <45> CPU_DETECT# SKTOCC SM_RCOMP_0 AR3 SM_RCOMP1
Refer CRB 1.5 H_CATERR# AN32 SM_RCOMP_1 AP2 SM_RCOMP2 1 2 SYS_PWROK_XDP
CATERR SM_RCOMP_2
THERMAL
1 2 H_THERMTRIP# PECI_EC AR27 AN3 DDR3_DRAMRST#_CPU DDR3_DRAMRST#_CPU <13> @ RC11 1K_0402_1%
<46> PECI_EC AK31 PECI SM_DRAMRST
@ RC27 100_0402_1%
RC30 1 2 56_0402_5% H_PROCHOT#_R AM30 FC_AK31 AR29 XDP_PRDY#
<46,50,61,64,65> H_PROCHOT# PROCHOT PRDY
H_THERMTRIP# @ RC31 1 2 0_0402_5% H_THERMTRIP#_R AM35 AT29 XDP_PREQ#
<46> H_THERMTRIP# THERMTRIP PREQ AM34 XDP_TCLK
TCK AN33 XDP_TMS CFG3
+VCCIO_OUT place RC31 near CPU TMS AM33 XDP_TRST#
H_PM_SYNC AT28 TRST AM31 XDP_TDI_R CXDP@ RC32 1 2 0_0402_5% XDP_TDI
JTAG
<16> H_PM_SYNC PM_SYNC TDI
1
PWR
@ RC33 1 2 0_0402_5% VCCPWRGOOD_0_R AL34 AL33 XDP_TDO_R CXDP@ RC34 1 2 0_0402_5% XDP_TDO
<20> H_CPUPWRGD PWRGOOD TDO
1 2 H_CATERR# PM_DRAM_PWRGD_CPU AC10 AP33 XDP_DBRESET#_R @ RC35 2 1 0_0402_5% XDP_DBRESET# XDP_DBRESET# <15,16> RC100 @
@ RC28 49.9_0402_1% CPU_PLTRST#_R AT26 SM_DRAMPWROK DBR 1K_0402_1%
1 2 H_PROCHOT# PLTRSTIN AR30 XDP_OBS0 Refer CRB 1.0
BPM_N_0 PAD~D
RC29 62_0402_5% AN31 XDP_OBS1 @ T173
2
BPM_N_1 PAD~D
@ RC38 2 1 0_0402_5% CPU_DPLL# G28 AN29 XDP_OBS2 @ T174
<17> CLK_CPU_DPLL# DPLL_REF_CLKN BPM_N_2 PAD~D
CLOCK
@ RC40 2 1 0_0402_5% CPU_DPLL H28 AP31 XDP_OBS3 @ T88 XDP_DBRESET#
<17> CLK_CPU_DPLL DPLL_REF_CLKP BPM_N_3 PAD~D
@ RC42 2 1 0_0402_5% CPU_SSC_DPLL# F27 AP30 XDP_OBS4 @ T89
<17> CLK_CPU_SSC_DPLL# SSC_DPLL_REF_CLKN BPM_N_4 PAD~D
@ RC44 2 1 0_0402_5% CPU_SSC_DPLL E27 AN28 XDP_OBS5 @ T90 1
<17> CLK_CPU_SSC_DPLL SSC_DPLL_REF_CLKP BPM_N_5 PAD~D
@ RC46 2 1 0_0402_5% CPU_DMI# D26 AP29 XDP_OBS6 @ T116 EMC@
<17> CLK_CPU_DMI# BCLKN BPM_N_6 PAD~D
@ RC48 2 1 0_0402_5% CPU_DMI E26 AP28 XDP_OBS7 @ T117 C1553
Refer CRB 1.0 <17> CLK_CPU_DMI BCLKP BPM_N_7 PAD~D 0.047U_0402_25V7K
@ T118
+1.05V_RUN +VCCST 2 OF 9 2
2 1 CONN@ different with 15
22U_0805_6.3V6M
22U_0805_6.3V6M
B @ RC99 0_0603_5% B
close CPU
1 1 ESD Request
@ CC47
@ CC48
2 2 PU/PD for JTAG signals

+3.3V_RUN
XDP_DBRESET# RC52 2 1 1K_0402_1%

EMC@
+1.05V_RUN
XDP_TMS @ RC53 2 1 51_0402_1%
VCCPWRGOOD_0_R XDP_TDI @ RC54 2 1 51_0402_1%
10K_0402_5%
XDP_PREQ# @ RC55 2 1 51_0402_1%
Buffered reset to CPU
1
+3.3V_RUN
RC56
XDP_TDO CXDP@ RC57 2 1 51_0402_1%
+1.05V_RUN DDR3 COMPENSATION SIGNALS
0.1U_0402_25V6
2
1
1K_0402_1%
@ SM_RCOMP0 RC58 1 2 100_0402_1% XDP_TCLK RC59 2 1 51_0402_1%

CC21
RC60
SM_RCOMP1 RC61 1 2 75_0402_1% XDP_TRST# RC62 2 1 51_0402_1%

2
UC2 @ @ SM_RCOMP2 RC63 1 2 100_0402_1%
CAD Note:
2
1 5
2 NC VCC Avoid stub in the PWRGD path
A <15,16> PCH_PLTRST#
3 A 4 PCH_PLTRST#_BUF 1 2 CPU_PLTRST#_R
CAD Note: A
GND Y @ RC64 43_0402_5%
while placing resistors RC33 & RC56 Trace width=12~15 mil, Spcing=20 mils
SN74LVC1G07DCKR_SC70-5~D
2 1 Max trace length= 500 mil
<20> CPU_PLTRST#
20K_0402_5%
@ RC66 0_0402_5%
@
1
RC67
PROPRIETARY NOTE:
Title
2
CAD Note: TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT CPU (2/7)
PLACE PULL-UP RESISTOR WITHIN 2 INCH OF THE CPU BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
1.0
5 4 3 2 1
5 4 3 2 1
D D
JCPU1C Haswell rPGA EDS
<13> DDR_A_D[0..63] DDR_A_D0 AR15 AC7 @ T2 PAD~D JCPU1D Haswell rPGA EDS
AT14 SA_DQ_0 RSVD U4 <14> DDR_B_D[0..63]
DDR_A_D1 M_CLK_DDR#0
DDR_A_D2 AM14 SA_DQ_1 SA_CKN0 V4 M_CLK_DDR0 M_CLK_DDR#0 <13> DDR_B_D0 AR18 AG8 @ T3 PAD~D
DDR_A_D3 AN14 SA_DQ_2 SA_CKP0 AD9 DDR_CKE0_DIMMA M_CLK_DDR0 <13> DDR_B_D1 AT18 SB_DQ_0 RSVD Y4 M_CLK_DDR#2
DDR_A_D4 AT15 SA_DQ_3 SA_CKE_0 U3 M_CLK_DDR#1 DDR_CKE0_DIMMA <13> DDR_B_D2 AM17 SB_DQ_1 SB_CKN0 AA4 M_CLK_DDR2 M_CLK_DDR#2 <14>
AR14 SA_DQ_4 SA_CKN1 V3 M_CLK_DDR#1 <13> AM18 SB_DQ_2 SB_CKP0 AF10 DDR_CKE2_DIMMB M_CLK_DDR2 <14>
DDR_A_D5 M_CLK_DDR1 DDR_B_D3
DDR_A_D6 AN15 SA_DQ_5 SA_CKP1 AC9 DDR_CKE1_DIMMA M_CLK_DDR1 <13> DDR_B_D4 AR17 SB_DQ_3 SB_CKE_0 Y3 M_CLK_DDR#3 DDR_CKE2_DIMMB <14>
DDR_A_D7 AM15 SA_DQ_6 SA_CKE_1 U2 DDR_CKE1_DIMMA <13> DDR_B_D5 AT17 SB_DQ_4 SB_CKN1 AA3 M_CLK_DDR3 M_CLK_DDR#3 <14>
DDR_A_D8 AM9 SA_DQ_7 SA_CKN2 V2 DDR_B_D6 AN17 SB_DQ_5 SB_CKP1 AG10 DDR_CKE3_DIMMB M_CLK_DDR3 <14>
DDR_A_D9 AN9 SA_DQ_8 SA_CKP2 AD8 DDR_B_D7 AN18 SB_DQ_6 SB_CKE_1 Y2 DDR_CKE3_DIMMB <14>
DDR_A_D10 AM8 SA_DQ_9 SA_CKE_2 U1 DDR_B_D8 AT12 SB_DQ_7 SB_CKN2 AA2
DDR_A_D11 AN8 SA_DQ_10 SA_CKN3 V1 DDR_B_D9 AR12 SB_DQ_8 SB_CKP2 AG9
DDR_A_D12 AR9 SA_DQ_11 SA_CKP3 AC8 DDR_B_D10 AN12 SB_DQ_9 SB_CKE_2 Y1
DDR_A_D13 AT9 SA_DQ_12 SA_CKE_3 DDR_B_D11 AM11 SB_DQ_10 SB_CKN3 AA1
DDR_A_D14 AR8 SA_DQ_13 M7 DDR_CS0_DIMMA# DDR_B_D12 AT11 SB_DQ_11 SB_CKP3 AF9
DDR_A_D15 AT8 SA_DQ_14 SA_CS_N_0 L9 DDR_CS1_DIMMA# DDR_CS0_DIMMA# <13> DDR_B_D13 AR11 SB_DQ_12 SB_CKE_3
DDR_A_D16 AJ9 SA_DQ_15 SA_CS_N_1 M9 DDR_CS1_DIMMA# <13> DDR_B_D14 AM12 SB_DQ_13 P4 DDR_CS2_DIMMB#
DDR_A_D17 AK9 SA_DQ_16 SA_CS_N_2 M10 DDR_B_D15 AN11 SB_DQ_14 SB_CS_N_0 R2 DDR_CS3_DIMMB# DDR_CS2_DIMMB# <14>
DDR_A_D18 AJ6 SA_DQ_17 SA_CS_N_3 M8 M_ODT0 DDR_B_D16 AR5 SB_DQ_15 SB_CS_N_1 P3 DDR_CS3_DIMMB# <14>
DDR_A_D19 AK6 SA_DQ_18 SA_ODT_0 L7 M_ODT1 M_ODT0 <13> DDR_B_D17 AR6 SB_DQ_16 SB_CS_N_2 P1
DDR_A_D20 AJ10 SA_DQ_19 SA_ODT_1 L8 M_ODT1 <13> DDR_B_D18 AM5 SB_DQ_17 SB_CS_N_3
DDR_A_D21 AK10 SA_DQ_20 SA_ODT_2 L10 DDR_B_D19 AM6 SB_DQ_18 R4 M_ODT2
DDR_A_D22 AJ7 SA_DQ_21 SA_ODT_3 V5 DDR_A_BS0 DDR_B_D20 AT5 SB_DQ_19 SB_ODT_0 R3 M_ODT3 M_ODT2 <14>
DDR_A_D23 AK7 SA_DQ_22 SA_BS_0 U5 DDR_A_BS1 DDR_A_BS0 <13> DDR_B_D21 AT6 SB_DQ_20 SB_ODT_1 R1 M_ODT3 <14>
DDR_A_D24 AF4 SA_DQ_23 SA_BS_1 AD1 DDR_A_BS2 DDR_A_BS1 <13> DDR_B_D22 AN5 SB_DQ_21 SB_ODT_2 P2
DDR_A_D25 AF5 SA_DQ_24 SA_BS_2 DDR_A_BS2 <13> DDR_B_D23 AN6 SB_DQ_22 SB_ODT_3 R7 DDR_B_BS0
AF1 SA_DQ_25 V10 AJ4 SB_DQ_23 SB_BS_0 P8 DDR_B_BS0 <14>
DDR_A_D26 DDR_B_D24 DDR_B_BS1
DDR_A_D27 AF2 SA_DQ_26 VSS U6 DDR_A_RAS# DDR_B_D25 AK4 SB_DQ_24 SB_BS_1 AA9 DDR_B_BS2 DDR_B_BS1 <14>
C DDR_A_D28 AG4 SA_DQ_27 SA_RAS U7 DDR_A_WE# DDR_A_RAS# <13> DDR_B_D26 AJ1 SB_DQ_25 SB_BS_2 DDR_B_BS2 <14> C
DDR_A_D29 AG5 SA_DQ_28 SA_WE U8 DDR_A_CAS# DDR_A_WE# <13> DDR_B_D27 AJ2 SB_DQ_26 R10
AG1 SA_DQ_29 SA_CAS DDR_A_CAS# <13> AM1 SB_DQ_27 VSS R6
DDR_A_D30 DDR_B_D28 DDR_B_RAS#
DDR_A_D31 AG2 SA_DQ_30 V8 DDR_A_MA0 DDR_A_MA[0..15] <13> DDR_B_D29 AN1 SB_DQ_28 SB_RAS P6 DDR_B_WE# DDR_B_RAS# <14>
DDR_A_D32 J1 SA_DQ_31 SA_MA_0 AC6 DDR_A_MA1 DDR_B_D30 AK2 SB_DQ_29 SB_WE P7 DDR_B_CAS# DDR_B_WE# <14>
DDR_A_D33 J2 SA_DQ_32 SA_MA_1 V9 DDR_A_MA2 DDR_B_D31 AK1 SB_DQ_30 SB_CAS DDR_B_CAS# <14>
DDR_A_D34 J5 SA_DQ_33 SA_MA_2 U9 DDR_A_MA3 DDR_B_D32 L2 SB_DQ_31 R8 DDR_B_MA0 DDR_B_MA[0..15] <14>
DDR_A_D35 H5 SA_DQ_34 SA_MA_3 AC5 DDR_A_MA4 DDR_B_D33 M2 SB_DQ_32 SB_MA_0 Y5 DDR_B_MA1
DDR_A_D36 H2 SA_DQ_35 SA_MA_4 AC4 DDR_A_MA5 DDR_B_D34 L4 SB_DQ_33 SB_MA_1 Y10 DDR_B_MA2
DDR_A_D37 H1 SA_DQ_36 SA_MA_5 AD6 DDR_A_MA6 DDR_B_D35 M4 SB_DQ_34 SB_MA_2 AA5 DDR_B_MA3
DDR_A_D38 J4 SA_DQ_37 SA_MA_6 AC3 DDR_A_MA7 DDR_B_D36 L1 SB_DQ_35 SB_MA_3 Y7 DDR_B_MA4
DDR_A_D39 H4 SA_DQ_38 SA_MA_7 AD5 DDR_A_MA8 DDR_B_D37 M1 SB_DQ_36 SB_MA_4 AA6 DDR_B_MA5
DDR_A_D40 F2 SA_DQ_39 SA_MA_8 AC2 DDR_A_MA9 DDR_B_D38 L5 SB_DQ_37 SB_MA_5 Y6 DDR_B_MA6
DDR_A_D41 F1 SA_DQ_40 SA_MA_9 V6 DDR_A_MA10 DDR_B_D39 M5 SB_DQ_38 SB_MA_6 AA7 DDR_B_MA7
DDR_A_D42 D2 SA_DQ_41 SA_MA_10 AC1 DDR_A_MA11 DDR_B_D40 G7 SB_DQ_39 SB_MA_7 Y8 DDR_B_MA8
DDR_A_D43 D3 SA_DQ_42 SA_MA_11 AD4 DDR_A_MA12 DDR_B_D41 J8 SB_DQ_40 SB_MA_8 AA10 DDR_B_MA9
DDR_A_D44 D1 SA_DQ_43 SA_MA_12 V7 DDR_A_MA13 DDR_B_D42 G8 SB_DQ_41 SB_MA_9 R9 DDR_B_MA10
DDR_A_D45 F3 SA_DQ_44 SA_MA_13 AD3 DDR_A_MA14 DDR_B_D43 G9 SB_DQ_42 SB_MA_10 Y9 DDR_B_MA11
DDR_A_D46 C3 SA_DQ_45 SA_MA_14 AD2 DDR_A_MA15 DDR_B_D44 J7 SB_DQ_43 SB_MA_11 AF7 DDR_B_MA12
DDR_A_D47 B3 SA_DQ_46 SA_MA_15 DDR_B_D45 J9 SB_DQ_44 SB_MA_12 P9 DDR_B_MA13
DDR_A_D48 B5 SA_DQ_47 DDR_B_D46 G10 SB_DQ_45 SB_MA_13 AA8 DDR_B_MA14
E6 SA_DQ_48 AP15 DDR_A_DQS#[0..7] <13> J10 SB_DQ_46 SB_MA_14 AG7
DDR_A_D49 DDR_A_DQS#0 DDR_B_D47 DDR_B_MA15
DDR_A_D50 A5 SA_DQ_49 SA_DQS_N_0 AP8 DDR_A_DQS#1 DDR_B_D48 A8 SB_DQ_47 SB_MA_15
DDR_A_D51 D6 SA_DQ_50 SA_DQS_N_1 AJ8 DDR_A_DQS#2 DDR_B_D49 B8 SB_DQ_48
DDR_A_D52 D5 SA_DQ_51 SA_DQS_N_2 AF3 DDR_A_DQS#3 DDR_B_D50 A9 SB_DQ_49 AP18 DDR_B_DQS#0 DDR_B_DQS#[0..7] <14>
DDR_A_D53 E5 SA_DQ_52 SA_DQS_N_3 J3 DDR_A_DQS#4 DDR_B_D51 B9 SB_DQ_50 SB_DQS_N_0 AP11 DDR_B_DQS#1
DDR_A_D54 B6 SA_DQ_53 SA_DQS_N_4 E2 DDR_A_DQS#5 DDR_B_D52 D8 SB_DQ_51 SB_DQS_N_1 AP5 DDR_B_DQS#2
DDR_A_D55 A6 SA_DQ_54 SA_DQS_N_5 C5 DDR_A_DQS#6 DDR_B_D53 E8 SB_DQ_52 SB_DQS_N_2 AJ3 DDR_B_DQS#3
DDR_A_D56 E12 SA_DQ_55 SA_DQS_N_6 C11 DDR_A_DQS#7 DDR_B_D54 D9 SB_DQ_53 SB_DQS_N_3 L3 DDR_B_DQS#4
DDR_A_D57 D12 SA_DQ_56 SA_DQS_N_7 AP14 DDR_A_DQS0 DDR_A_DQS[0..7] <13> DDR_B_D55 E9 SB_DQ_54 SB_DQS_N_4 H9 DDR_B_DQS#5
DDR_A_D58 B11 SA_DQ_57 SA_DQS_P_0 AP9 DDR_A_DQS1 DDR_B_D56 E15 SB_DQ_55 SB_DQS_N_5 C8 DDR_B_DQS#6
DDR_A_D59 A11 SA_DQ_58 SA_DQS_P_1 AK8 DDR_A_DQS2 DDR_B_D57 D15 SB_DQ_56 SB_DQS_N_6 C14 DDR_B_DQS#7
B E11 SA_DQ_59 SA_DQS_P_2 AG3 A15 SB_DQ_57 SB_DQS_N_7 AP17 DDR_B_DQS[0..7] <14> B
DDR_A_D60 DDR_A_DQS3 DDR_B_D58 DDR_B_DQS0
DDR_A_D61 D11 SA_DQ_60 SA_DQS_P_3 H3 DDR_A_DQS4 DDR_B_D59 B15 SB_DQ_58 SB_DQS_P_0 AP12 DDR_B_DQS1
DDR_A_D62 B12 SA_DQ_61 SA_DQS_P_4 E3 DDR_A_DQS5 DDR_B_D60 E14 SB_DQ_59 SB_DQS_P_1 AP6 DDR_B_DQS2
DDR_A_D63 A12 SA_DQ_62 SA_DQS_P_5 C6 DDR_A_DQS6 DDR_B_D61 D14 SB_DQ_60 SB_DQS_P_2 AK3 DDR_B_DQS3
AM3 SA_DQ_63 SA_DQS_P_6 C12 DDR_A_DQS7 DDR_B_D62 A14 SB_DQ_61 SB_DQS_P_3 M3 DDR_B_DQS4
+SM_VREF SM_VREF SA_DQS_P_7 SB_DQ_62 SB_DQS_P_4
F16 DDR_B_D63 B14 H8 DDR_B_DQS5
+SA_DIMM_VREFDQ SA_DIMM_VREFDQ SB_DQ_63 SB_DQS_P_5
F13 C9 DDR_B_DQS6
+SB_DIMM_VREFDQ SB_DIMM_VREFDQ SB_DQS_P_6 C15 DDR_B_DQS7
SB_DQS_P_7
3 OF 9 4 OF 9
LOTES_AZIF0012-P002B_HASWELL LOTES_AZIF0012-P002B_HASWELL
CONN@ CONN@
A A
Title
CPU (3/7)
Size Document Number Rev
1.0
LA-9934P
Date: Wednesday, May 07, 2014 Sheet 8 of 71
5 4 3 2 1
5 4 3 2 1
D D
COMPENSATION PU FOR eDP

+VCOMP_OUT
EDP_COMP 2 1
24.9_0402_1% RC73
CAD Note:Trace width=20 mils ,Spacing=25mil,

Max length=100 mils.
JCPU1H Haswell rPGA EDS
T28 M27
<26> TMDSB_CPU_N2 U28 DDIB_TXN0 EDP_AUXN N27 EDP_CPU_AUX# <28>
<26> TMDSB_CPU_P2 T30 DDIB_TXP0 EDP_AUXP P27 EDP_HPD# EDP_CPU_AUX <28>
C <26> TMDSB_CPU_N1 U30 DDIB_TXN1 EDP_HPD E24 EDP_COMP C
<26> TMDSB_CPU_P1 U29 DDIB_TXP1 EDP_RCOMP R27
<26> TMDSB_CPU_N0 V29 DDIB_TXN2 EDP_DISP_UTIL PAD~D T4 @
<26> TMDSB_CPU_P0 U31 DDIB_TXP2
<26> TMDSB_CPU_CLK# V31 DDIB_TXN3 eDP
<26> TMDSB_CPU_CLK DDIB_TXP3 P35
T34 EDP_TXN_0 R35 EDP_CPU_LANE_N0 <28>
<44> DPC_CPU_LANE_N0 U34 DDIC_TXN0 EDP_TXP_0 N34 EDP_CPU_LANE_P0 <28>
<44> DPC_CPU_LANE_P0 U35 DDIC_TXP0 EDP_TXN_1 P34 EDP_CPU_LANE_N1 <28>
<44> DPC_CPU_LANE_N1 V35 DDIC_TXN1 EDP_TXP_1 P33 EDP_CPU_LANE_P1 <28>
<44> DPC_CPU_LANE_P1 U32 DDIC_TXP1 DDI FDI_TXN_0 R33 FDI_CTX_PRX_N0 <16>
<44> DPC_CPU_LANE_N2 T32 DDIC_TXN2 FDI_TXP_0 N32 FDI_CTX_PRX_P0 <16>
<44> DPC_CPU_LANE_P2 U33 DDIC_TXP2 FDI_TXN_1 P32 FDI_CTX_PRX_N1 <16>
<44> DPC_CPU_LANE_N3 V33 DDIC_TXN3 FDI_TXP_1 FDI_CTX_PRX_P1 <16>
<44> DPC_CPU_LANE_P3 DDIC_TXP3
P29
<44> DPD_CPU_LANE_N0 R29 DDID_TXN0
<44> DPD_CPU_LANE_P0 N28 DDID_TXP0
<44> DPD_CPU_LANE_N1 P28 DDID_TXN1
<44> DPD_CPU_LANE_P1 P31 DDID_TXP1 Question:
<44> DPD_CPU_LANE_N2 DDID_TXN2
<44> DPD_CPU_LANE_P2
R31
N30 DDID_TXP2 JCPU1H.P27 pinout is EDP_HPD. is it high active when Plug in eDP device?
<44> DPD_CPU_LANE_N3 P30 DDID_TXN3
<44> DPD_CPU_LANE_P3 DDID_TXP3
8 OF 9
+VCCIO_OUT
10K_0402_5%
2
CONN@
RC74
HPD INVERSION FOR EDP
B B
1
EDP_HPD#
1
D
2 QC3
<28> CPU_EDP_HPD
G L2N7002WT1G_SC-70-3
S
3
100K_0402_5%
1
RC75
2
QC3 change PN to SB50138003L S TR BSS138-7-F 1N SOT23-3
A A
PROPRIETARY NOTE:
Title
1.0
5 4 3 2 1
5 4 3 2 1
CFG STRAPS for CPU

CFG2
1K_0402_1%
1
@ RC76
D D
2
PEG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
CFG2 definition matches socket pin map definition
0:Lane Reversed
JCPU1I Haswell rPGA EDS
CFG4
@ T11 PAD~D AT1
AT2 RSVD_TP C23
1K_0402_1%
@ T5 PAD~D PAD~D T12 @
RSVD_TP RSVD_TP
1
@ T6 PAD~D AD10 B23 PAD~D T7 @
RSVD RSVD_TP
RC77
D24 PAD~D T13 @
@ T8 PAD~D A34 RSVD_TP D23 PAD~D T14 @
@ T9 PAD~D A35 RSVD_TP RSVD_TP
RSVD_TP
2
@ T10 PAD~D W29
@ T15 PAD~D W28 RSVD_TP AT31 CFG_RCOMP
H_CPU_RSVD G26 RSVD_TP CFG_RCOMP AR21 CFG16 PAD~D T167 @
W33 TESTLO_G26 CFG_16 AR23 CFG18 PAD~D T168 @
@ T16 PAD~D AL30 VSS CFG_18 AP21 CFG17 PAD~D T169 @
@ T17 PAD~D AL29 RSVD CFG_17 AP23 CFG19 PAD~D T170 @
C
+VCC_CORE
F25 RSVD CFG_19 Display Port Presence Strap C
VCC
@ T18 PAD~D C35 AR33 PAD~D T19 @
@ T20 PAD~D B35 RSVD_TP RSVD G6 FC_G6 1 : Disabled; No Physical Display Port
RSVD_TP FC_G6 AM27 PAD~D T22 @
@ T23 PAD~D AL25 RSVD AM26 PAD~D T24 @ CFG4 attached to Embedded Display Port
RSVD_TP RSVD F5 PAD~D T25 @
@ T26 PAD~D W30 RSVD AM2 PAD~D T27 @ 0 : Enabled; An external Display Port device is
@ T28 PAD~D W31 RSVD_TP RSVD K6 PAD~D T29 @
H_CPU_TESTLO W34 RSVD_TP RSVD connected to the Embedded Display Port
TESTLO_W34 E18 PAD~D T30 @
@ T157PAD~D CFG0 AT20 RSVD
@ T158PAD~D CFG1 AR20 CFG_0 U10 PAD~D T31 @ CFG6
CFG2 AP20 CFG_1 RSVD P10 PAD~D T32 @
CFG3 AP22 CFG_2 RSVD CFG5
<7> CFG3 CFG4 AT22 CFG_3 B1
1K_0402_1%
CFG_4 NC
1
1K_0402_1%
CFG5 AN22 A2 PAD~D T33 @
CFG_5 RSVD
@ RC78
@
CFG6 AT25 AR1 PAD~D T34 @
CFG_6 RSVD_TP
RC79
CFG7 AN23
@ T159PAD~D CFG8 AR24 CFG_7 E21 PAD~D T35 @
@ T160PAD~D CFG9 AT23 CFG_8 RSVD_TP E20 PAD~D T36 @
2
@ T161PAD~D CFG10 AN20 CFG_9 RSVD_TP
@ T162PAD~D CFG11 AP24 CFG_10 AP27
@ T163PAD~D CFG12 AP26 CFG_11 VSS AR26
@ T164PAD~D CFG13 AN25 CFG_12 VSS
@ T165PAD~D CFG14 AN26 CFG_13 AL31
@ T166PAD~D CFG15 AP25 CFG_14 VSS AL32
CFG_15 VSS
PCIE Port Bifurcation Straps
9 OF 9 Refer 1.2 CRB
2 1 H_CPU_TESTLO 11: (Default) x16 - Device 1 functions 1 and 2 disabled
RC80 49.9_0402_1% LOTES_AZIF0012-P002B_HASWELL
B 2 1 CFG_RCOMP CONN@ 10: x8, x8 - Device 1 function 1 enabled ; function 2 B
RC81 49.9_0402_1%
2 1 H_CPU_RSVD CFG[6:5] disabled
RC82 49.9_0402_1% 01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG7
1
1K_0402_1%
@ RC83
2
Note: Reserve this circuit
for future compatibility
RESET_OUT# <15,16,46>
PEG DEFER TRAINING

1
@ RC69
6.04K_0402_1% 1: (Default) PEG Train immediately
CFG7 following xxRESETB de assertion
2
FC_G6 0: PEG Wait for BIOS for training

A A
1
@ RC68
2.67K_0402_1%
2
PROPRIETARY NOTE:
Title
1.0
5 4 3 2 1
5 4 3 2 1
+VCC_CORE
JCPU1E Haswell rPGA EDS
AA26
VCC AA28
@ T39 PAD~D K27 VCC AA34
@ T40 PAD~D L27 RSVD VCC AA30
@ T41 PAD~D T27 RSVD VCC AA32
@ T42 PAD~D V27 RSVD VCC AB26
D
RSVD VCC AB29 D
+1.35V_MEM VCC AB25
VCC AB27
VCC AB28
AB11 VCC AB30
AB2 VDDQ VCC AB31
AB5 VDDQ VCC AB33
AB8 VDDQ VCC AB34
AE11 VDDQ VCC AB32
AE2 VDDQ VCC AC26
AE5 VDDQ VCC AB35
AE8 VDDQ VCC AC28
AH11 VDDQ VCC AD25
K11 VDDQ VCC AC30
N11 VDDQ VCC AD28
N8 VDDQ VCC AC32
T11 VDDQ VCC AD31
T2 VDDQ VCC AC34
T5 VDDQ VCC AD34
T8 VDDQ VCC AD26
W11 VDDQ VCC AD27
W2 VDDQ VCC AD29
W5 VDDQ VCC AD30
W8 VDDQ VCC AD32
VDDQ VCC AD33
@ T43 PAD~D N26 VCC AD35
K26 RSVD VCC AE26
+VCC_CORE VCC VCC
AL27 AE32
@ T44 PAD~D AK27 RSVD VCC AE28
+1.05V_RUN @ T45 PAD~D RSVD VCC AE30
VCC AG28
VCC AG34
+VCCIO_OUT max. current VCC
150_0402_1%
AE34
VCC
1
is 300mA, 20mil VCC
AF25
RC85
AF26
C +1.05V_RUN +VCCIO_OUT VCCSENSE_R AL35 VCC AF27 C
@ T46 PAD~D E17 VCC_SENSE VCC AF28
AN35 RSVD VCC AF29
+VCCIO_OUT
2
2 1 A23 VCCIO_OUT VCC AF30
+VCCIO2PCH_R FC_A23 VCC
@ RC86 0_0603_5% +VCOMP_OUT F22 AF31
CPU_PWR_DEBUG W32 VCOMP_OUT VCC AF32
@ T48 PAD~D AL16 RSVD VCC AF33
RSVD VCC
10K_0402_5%
RESISTOR STUFFING OPTIONS ARE @ T49 PAD~D J27 AF34
RSVD VCC
1
@ T50 PAD~D AL13 AF35
PROVIDED FOR TESTING PURPOSES RSVD VCC
@
@ T51 PAD~D AG26
VCC
RC89
AH26
H_CPU_SVIDALRT# AM28 VCC AH29
VIDSCLK AM29 VIDALERT VCC AG30
<61> VIDSCLK
2
VIDSOUT AL28 VIDSCLK VCC AG32
VIDSOUT VCC AH32
+VCCIO_OUT AP35 VCC AH35
SVID ALERT <7> CPU_PWR_DEBUG
H27
AP34
VSS
PWR_DEBUG
VSS
VCC
VCC
VCC
AH25
AH27
75_0402_1%
AT35 AH28
RSVD_TP VCC
1
@ T52 PAD~D AR35 AH30

RSVD_TP VCC
RC87
@ T53 PAD~D AR32 AH31

CAD Note: Place the PU resistors close to CPU @ T54 PAD~D AL26 RSVD_TP VCC AH33
RC87 close to CPU 300 - 1500mils +1.05V_RUN +VCCIO2PCH +VCCIO2PCH_R @ T55 PAD~D AT34 RSVD_TP VCC AH34
AL22 VSS VCC AJ25
2
AT33 VSS VCC AJ26

2 1 H_CPU_SVIDALRT# 2 1 2 1 AM21 VSS VCC AJ27
<61> VIDALERT_N
@ T72 VSS VCC
4.7U_0603_6.3V6K
RC88 43_0402_5% @ RC105 0_0603_5% @ RC106 0_0603_5% AM25 AJ28
PAD~D AM22 VSS VCC AJ29
1 VSS VCC
CC137
AM20 AJ30
AM24 VSS VCC AJ31
+VCCIO_OUT AL19 VSS VCC AJ32
SVID DATA 2
@
AM23 VSS
VSS
VCC
VCC
AJ33
130_0402_1%
AT32 AJ34
VSS VCC
1
AJ35
CAD Note: Place the PU resistors close to CPU VCC
RC90
B Place T72 close to G25 B

RC90 close to CPU 300 - 1500mils VCC H25
T55 for iFDIM test VCC J25
VCC K25
2
+VCC_CORE VCC L25

VIDSOUT VCC M25
<61> VIDSOUT VCC
+1.35V_MEM Y25 N25
VDDQ DECOUPLING Y26 VCC VCC P25
Y27 VCC VCC R25
Y28 VCC VCC T25
Y29 VCC VCC
VCC
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
330U_D2_2VM_R6M~D
330U_D2_2VM_R6M
1 1 Y30 U25
VCC VCC
@ CC34
1 1 1 1 1 1 1 1 1 1 Y31 U26
+VCC_CORE VCC VCC
@ CC24
@ CC25
@ CC26
@ CC27
@ CC28
@ CC29
@ CC30
@ CC31
CC35
+ + Y32 V25
VCC VCC
CC32
CC33
Y33 V26
VCC_SENSE 2 2 2 2 2 2 2 2 2 2 2 2
Y34 VCC
VCC
VCC
100_0402_1%
Y35 W26
VCC VCC
1
W27
VCC
RC91
5 OF 9
CONN@
CAD Note: RC92 SHOULD BE PLACED CLOSE TO CPU
2
VCCSENSE 2 1 VCCSENSE_R
<61> VCCSENSE
@ RC92 0_0402_5%
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
CAD Note: RC93 SHOULD BE PLACED CLOSE TO CPU 1 1 1 1 1 1 1 1 1 1 1
@ CC41
@ CC37
@ CC42
@ CC43
@ CC38
@ CC44
@ CC39
@ CC45
@ CC46
CC40
CC36
VSSSENSE 2 1 VSSSENSE_R
<61> VSSSENSE VSSSENSE_R <12> 2 2 2 2 2 2 2 2 2 2 2
@ RC93 0_0402_5%
1
100_0402_1%
A A
RC94
2
PROPRIETARY NOTE:
Title
1.0
5 4 3 2 1
5 4 3 2 1
JCPU1F JCPU1G
Haswell rPGA EDS Haswell rPGA EDS
A10 AK34 B34 K10

A13 VSS VSS AK5 B4 VSS VSS K2
D A16 VSS VSS AL1 B7 VSS VSS K29 D
A19 VSS VSS AL10 C1 VSS VSS K3
A7 VSS VSS AL21 C28 VSS VSS L11
AA11 VSS VSS AL23 C30 VSS VSS L26
AA25 VSS VSS E22 C32 VSS VSS L6
AA27 VSS VSS AL3 C34 VSS VSS M11
AB1 VSS VSS AL6 D10 VSS VSS M30
AB10 VSS VSS AL7 D13 VSS VSS M32
AA33 VSS VSS AL8 D16 VSS VSS M34
AA35 VSS VSS AL9 D19 VSS VSS M6
AB3 VSS VSS AM10 D22 VSS VSS N1
AC25 VSS VSS AM13 D25 VSS VSS N10
AB6 VSS VSS E25 D31 VSS VSS N3
AD11 VSS VSS AN10 D7 VSS VSS N4
AC29 VSS VSS AN13 E1 VSS VSS N5
C AC35 VSS VSS AN2 E16 VSS VSS N9 C
AD7 VSS VSS AN21 E4 VSS VSS P11
AE1 VSS VSS AN24 E7 VSS VSS P26
AE10 VSS VSS AN27 F10 VSS VSS P5
AE25 VSS VSS AN30 F11 VSS VSS R11
AE35 VSS VSS AP1 F17 VSS VSS R32
AE7 VSS VSS AP16 F21 VSS VSS T1
AE9 VSS VSS AP19 F23 VSS VSS T10
AF11 VSS VSS AP4 F24 VSS VSS T29
AF6 VSS VSS AP7 F26 VSS VSS T3
AF8 VSS VSS W25 F28 VSS VSS T31
AG11 VSS VSS AR10 F30 VSS VSS T33
AE31 VSS VSS AR16 F34 VSS VSS T4
AE33 VSS VSS AR2 F6 VSS VSS T7
AH1 VSS VSS AR25 F8 VSS VSS U11
AH10 VSS VSS AR28 F9 VSS VSS U27
AH2 VSS VSS AR31 G1 VSS VSS V11
AG27 VSS VSS AR34 G11 VSS VSS V28
AG29 VSS VSS AR4 G2 VSS VSS V30
AH3 VSS VSS AR7 G27 VSS VSS V32
AG33 VSS VSS AT10 G29 VSS VSS V34
AG35 VSS VSS AT13 G3 VSS VSS W1
AH4 VSS VSS AT16 G31 VSS VSS W10
B AH6 VSS VSS AT21 G35 VSS VSS W35 B
AH9 VSS VSS AT3 H10 VSS VSS W7
AJ11 VSS VSS AT30 H26 VSS VSS W9
AJ5 VSS VSS AT4 H6 VSS VSS Y11
AK11 VSS VSS AT7 H7 VSS VSS H11
AK25 VSS VSS B10 J11 VSS VSS AL24
AK26 VSS VSS B13 J26 VSS VSS F19
AK28 VSS VSS B16 J28 VSS VSS T26
AK29 VSS VSS B19 J30 VSS VSS AK35
AK30 VSS VSS B2 J32 VSS VSS_SENSE AK33 VSSSENSE_R <11>
AK32 VSS VSS B22 J34 VSS RSVD PAD~D T56 @
E19 VSS VSS J6 VSS
VSS K1 VSS
VSS
6 OF 9 7 OF 9
LOTES_AZIF0012-P002B_HASWELL LOTES_AZIF0012-P002B_HASWELL
CONN@ CONN@
A A
PROPRIETARY NOTE:
Title
1.0
5 4 3 2 1
5 4 3 2 1
+SA_DIMM_VREFDQ +SA_DIMM_VREFDQ_Q +1.35V_MEM

Populate RD1, De-Populate RD3 for Intel DDR3
1
1K_0402_1%
VREFDQ multiple methods M1
@ RD26 1 20_0402_5%
RD19
+SA_DIMM1_VREFDQ VREFDQ multiple methods M3
JDIMM1 H=5.2mm
2
@ QD6A
DMN66D0LDW-7_SOT363-6
1 6 RD17 1 2 2_0402_1%
+DIMM1_VREF_DQ
+1.35V_MEM +1.35V_MEM
1K_0402_1%
1 +SA_DIMM1_VREFDQ @ RD1 1 2 0_0402_5%
1K_0402_1%
D JDIMM1 D
1
RD27
CD47 +V_DDR_REF @ RD3 1 2 0_0402_5% 1 2
VREF_DQ VSS1
RD18
0.022U_0402_16V7K 3 4 DDR_A_D4
2 VSS2 DQ4
2.2U_0402_6.3V6M
0.1U_0402_25V6
DDR_A_D0 5 6 DDR_A_D5
@ DDR_A_D1 7 DQ0 DQ5 8
1 1
2
9 DQ1 VSS3 10 DDR_A_DQS#0
2
VSS4 DQS#0
CD1
CD2
11 12 DDR_A_DQS0
RC109 13 DM0 DQS0 14
2 @ 2 DDR_A_D2 15 VSS5 VSS6 16 DDR_A_D6
24.9_0402_1% DQ2 DQ6
DDR_HVREF_RST_PCH 19 DQ3 DQ7 20
2
<14,18,7> DDR_HVREF_RST_PCH 21 VSS7 VSS8 22
DDR_A_D8 DDR_A_D12
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
25 DQ9 DQ13 26
+V_DDR_REF, +SA_DIMM1_VREFDQ, +SA_DIMM_VREFDQ, +DIMM1_VREF_DQ DDR_A_DQS#1 27 VSS9 VSS10 28
traces should be at least 20 mils wide and 20 mils spacing to other signals /planes. DDR_A_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#_R
31 DQS1 RESET# 32
DDR_A_D10 33 VSS11 VSS12 34 DDR_A_D14
+SM_VREF +SM_VREF_Q 37 DQ11 DQ15 38
+1.35V_MEM DDR_A_D16 39 VSS13 VSS14 40 DDR_A_D20
DQ17 DQ21
1
1K_0402_1%
@ RD29 1 20_0402_5% 43 44
DDR_A_DQS#2 45 VSS15 VSS16 46
DDR_A_DQS2 47 DQS#2 DM2 48
RD22
@ QD7 49 DQS2 VSS17 50 DDR_A_D22
+SM_VREF_DIMM DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23
2
L2N7002WT1G_SC-70-3 DDR_A_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_A_D28
VSS20 DQ28
S
3 1 RD20 1 2 2_0402_1% DDR_A_D24 57 58 DDR_A_D29

DDR_A_D25 59 DQ24 DQ29 60
VSS22 DQS#3
1K_0402_1%
1K_0402_1%
63 64 DDR_A_DQS3
G
2
DM3 DQS3
1
1
1 65 66
VSS23 VSS24
RD28
RD21
CD48 DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
71 DQ27 DQ31 72
0.022U_0402_16V7K VSS25 VSS26
@ 2
C C
2
2
1
73 74 DDR_CKE1_DIMMA
<8> DDR_CKE0_DIMMA 75 CKE0 CKE1 76 DDR_CKE1_DIMMA <8>
RC110
DDR_HVREF_RST_PCH 77 VDD1 VDD2 78 DDR_A_MA15
24.9_0402_1% NC1 A15
DDR_A_BS2 79 80 DDR_A_MA14
<8> DDR_A_BS2 81 BA2 A14 82
2
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11

DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
Layout Note: 87 A9 A7 88
Place near JDIMM1 DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
+1.35V_MEM M_CLK_DDR0 101 VDD9 VDD10 102 M_CLK_DDR1
<8> M_CLK_DDR0 103 CK0 CK1 104 M_CLK_DDR1 <8>
M_CLK_DDR#0 M_CLK_DDR#1
<8> M_CLK_DDR#0 105 CK0# CK1# 106 M_CLK_DDR#1 <8>
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <8>
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
DDR_A_BS0 109 110 DDR_A_RAS#

<8> DDR_A_BS0 111 BA0 RAS# 112 DDR_A_RAS# <8>
1 1 1 1 VDD13 VDD14
DDR_A_WE# 113 114 DDR_CS0_DIMMA#
<8> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <8>
CD3
CD4
CD5
CD6
DDR_A_CAS# 115 116 M_ODT0

<8> DDR_A_CAS# 117 CAS# ODT0 118 M_ODT0 <8>
2 2 2 2 Layout Note: DDR_A_MA13 119 VDD15 VDD16 120 M_ODT1 +DIMM1_VREF_CA
Place near JDIMM1.203,204 121 A13 ODT1 122 M_ODT1 <8>
<8> DDR_CS1_DIMMA# 123 S1# NC2 124
125 VDD17 VDD18 126 2 1
NCTEST VREF_CA +V_DDR_REF
127 128 @ RD5 0_0402_5%
DDR_A_D33 131 DQ32 DQ36 132 DDR_A_D37 2 1
DQ33 DQ37 +SM_VREF_DIMM
133 134 @ RD13 0_0402_5%
+1.35V_MEM DDR_A_DQS4 137 DQS#4 DM4 138
DQS4 VSS31
2.2U_0402_6.3V6M
0.1U_0402_25V6
+0.675V_DDR_VTT 139 140 DDR_A_D38
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39
B DQ34 DQ39 B
@ CD15
DDR_A_D35 143 144 1 1
DQ35 VSS33
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD16
145 146 DDR_A_D44
VSS34 DQ44
330U_2.5V_M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
DDR_A_D40 147 148 DDR_A_D45

DDR_A_D41 149 DQ40 DQ45 150
1 1 1 1 1 DQ41 VSS35 2 2
@ CD13
1 1 1 1 1 1 1 151 152 DDR_A_DQS#5

VSS36 DQS#5
CD7
CD8
CD9
CD10
CD11
CD12
CD14
CD17
CD18
CD19
CD20
+ 153 154 DDR_A_DQS5

155 DM5 DQS5 156
2 2 2 2 DDR_A_D42 157 VSS37 VSS38 158 DDR_A_D46
2 2 2 2 2 2 2 2 DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
161 DQ43 DQ47 162
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
167 DQ49 DQ53 168
DDR_A_DQS6 171 DQS#6 DM6 172
173 DQS6 VSS43 174 DDR_A_D54
DDR_A_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_A_D60
<8> DDR_A_DQS#[0..7] 183 DQ56 DQ61 184
DDR_A_D57
<8> DDR_A_D[0..63] 187 VSS48 DQS#7 188
All VREF traces should DDR_A_DQS7
189 DM7 DQS7 190
<8> DDR_A_DQS[0..7] have 10 mil trace width 191 VSS49 VSS50 192
DDR_A_D58 DDR_A_D62
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
<8> DDR_A_MA[0..15] +3.3V_RUN 195 DQ59 DQ63 196
DIMM1_SA0 197 VSS51 VSS52 198
199 SA0 EVENT# 200
+1.35V_MEM 201 VDDSPD SDA 202 DDR_XDP_WAN_SMBDAT <14,15,18,31>
DIMM1_SA1
SA1 SCL DDR_XDP_WAN_SMBCLK <14,15,18,31>
0.1U_0402_25V6
2.2U_0402_6.3V6M
1 +0.675V_DDR_VTT
203 204 +0.675V_DDR_VTT
VTT1 VTT2
1
1
CD22
205 206
G1 G2
CD21
@ RD4 2 1 0_0402_5% @ RD2

2 TYCO_2-2013290-1
1K_0402_5%
2 CONN@
A @ QD9 +V_DDR_REF, +SM_VREF_DIMM, +DIMM1_VREF_CA,+SM_VREF, +DIMM1_VREF_CA A
2
L2N7002WT1G_SC-70-3
traces should be at least 20 mils wide and 20 mils spacing to other signals /planes.
S
3 1 1 2
<7> DDR3_DRAMRST#_CPU DDR3_DRAMRST#_R <14>
@ RD25 0_0402_5%
G
2
1
@ RD24
4.99K_0402_1%
DDR_HVREF_RST_PCH
1 2 DIMM1_SA0
1
@ RD6 0_0402_5%
@ CD45 1 2 DIMM1_SA1 PROPRIETARY NOTE: Compal Electronics, Inc.
2
0.047U_0402_16V4Z @ RD7 0_0402_5% Title

2 THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDRIII-SODIMM SLOT1
1.0
5 4 3 2 1
5 4 3 2 1

JDIMM2 H=9.2mm
+DIMM2_VREF_DQ
@ RD8 1 2 0_0402_5% +1.35V_MEM +1.35V_MEM
+SB_DIMM_VREFDQ +SB_DIMM_VREFDQ_Q +SB_DIMM2_VREFDQ
JDIMM2
+V_DDR_REF @ RD9 1 2 0_0402_5% 1 2
3 VREF_DQ VSS1 4 DDR_B_D4
+1.35V_MEM VSS2 DQ4
2.2U_0402_6.3V6M
0.1U_0402_25V6
D DDR_B_D0 5 6 DDR_B_D5 D
DDR_B_D1 7 DQ0 DQ5 8
DQ1 VSS3
1
1K_0402_1%
@ RD31 2 1 0_0402_5% 1 1 9 10 DDR_B_DQS#0
VSS4 DQS#0
CD24
CD23
11 12 DDR_B_DQS0
13 DM0 DQS0 14
RD15
DDR_B_D2 15 VSS5 VSS6 16 DDR_B_D6
@ QD6B +SB_DIMM2_VREFDQ 2 @ 2 DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D7
2
19 DQ3 DQ7 20
DMN66D0LDW-7_SOT363-6 DDR_B_D8 21 VSS7 VSS8 22 DDR_B_D12
4 3 RD14 1 2 2_0402_1% DDR_B_D9 23 DQ8 DQ12 24 DDR_B_D13
DQ9 DQ13
0.022U_0402_16V7K
25 26
VSS9 VSS10
1K_0402_1%
DDR_B_DQS#1 27 28
DQS#1 DM1
1
1K_0402_1%
DDR_B_DQS1 29 30 DDR3_DRAMRST#_R
5
DQS1 RESET# DDR3_DRAMRST#_R <13>
1
RD30
1 31 32
VSS11 VSS12
RD16
DDR_B_D10 33 34 DDR_B_D14
DQ10 DQ14
CD46
DDR_B_D11 35 36 DDR_B_D15
@ 37 DQ11 DQ15 38
2
2 DDR_B_D16 39 VSS13 VSS14 40 DDR_B_D20
2
DDR_B_D17 41 DQ16 DQ20 42 DDR_B_D21
43 DQ17 DQ21 44
DDR_B_DQS#2 45 VSS15 VSS16 46
DQS#2 DM2
1
24.9_0402_1%
DDR_B_DQS2 47 48
DQS2 VSS17
RC108
49 50 DDR_B_D22
<13,18,7> DDR_HVREF_RST_PCH 51 VSS18 DQ22 52
DDR_B_D18 DDR_B_D23
DDR_B_D19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D28
2
DDR_B_D24 57 VSS20 DQ28 58 DDR_B_D29

+V_DDR_REF, +SB_DIMM2_VREFDQ, +SB_DIMM_VREFDQ, +DIMM2_VREF_DQ DDR_B_D25 59 DQ24 DQ29 60
traces should be at least 20 mils wide and 20 mils spacing to other signals /planes. 61 DQ25 VSS21 62 DDR_B_DQS#3
63 VSS22 DQS#3 64 DDR_B_DQS3
65 DM3 DQS3 66
DDR_B_D27 69 DQ26 DQ30 70 DDR_B_D31
71 DQ27 DQ31 72
VSS25 VSS26
C DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB C
<8> DDR_B_DQS#[0..7] <8> DDR_CKE2_DIMMB 75 CKE0 CKE1 76 DDR_CKE3_DIMMB <8>
77 VDD1 VDD2 78 DDR_B_MA15
<8> DDR_B_D[0..63] 79 NC1 A15 80
DDR_B_BS2 DDR_B_MA14
<8> DDR_B_BS2 81 BA2 A14 82
<8> DDR_B_DQS[0..7] 83 VDD3 VDD4 84
DDR_B_MA12 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
<8> DDR_B_MA[0..15] 87 A9 A7 88
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
Layout Note: M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3
Place near JDIMM2 <8> M_CLK_DDR2 103 CK0 CK1 104 M_CLK_DDR3 <8>
M_CLK_DDR#2 M_CLK_DDR#3
<8> M_CLK_DDR#2 105 CK0# CK1# 106 M_CLK_DDR#3 <8>
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <8>
DDR_B_BS0 109 110 DDR_B_RAS#
<8> DDR_B_BS0 111 BA0 RAS# 112 DDR_B_RAS# <8>
DDR_B_WE# 113 VDD13 VDD14 114 DDR_CS2_DIMMB#
<8> DDR_B_WE# 115 WE# S0# 116 DDR_CS2_DIMMB# <8>
DDR_B_CAS# M_ODT2
<8> DDR_B_CAS# 117 CAS# ODT0 118 M_ODT2 <8>
+1.35V_MEM DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3 +DIMM2_VREF_CA
121 A13 ODT1 122 M_ODT3 <8>
DDR_CS3_DIMMB#
<8> DDR_CS3_DIMMB# 123 S1# NC2 124
125 VDD17 VDD18 126 2 1
NCTEST VREF_CA +V_DDR_REF
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
127 128 @ RD10 0_0402_5%

1 1 1 1 DQ32 DQ36
DDR_B_D33 131 132 DDR_B_D37 2 1
DQ33 DQ37 +SM_VREF_DIMM
CD25
CD26
CD27
CD28
133 134 @ RD23 0_0402_5%

DDR_B_DQS#4 135 VSS29 VSS30 136
2 2 2 2 DQS#4 DM4
2.2U_0402_6.3V6M
0.1U_0402_25V6
DDR_B_DQS4 137 138
139 DQS4 VSS31 140 DDR_B_D38
VSS32 DQ38
@ CD37
DDR_B_D34 141 142 DDR_B_D39 1 1
DQ34 DQ39
CD38
DDR_B_D35 143 144
145 DQ35 VSS33 146 DDR_B_D44
B DQ40 DQ45 B
DDR_B_D41 149 150 2 2
151 DQ41 VSS35 152 DDR_B_DQS#5
+1.35V_MEM 153 VSS36 DQS#5 154 DDR_B_DQS5
155 DM5 DQS5 156
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47
161 DQ43 DQ47 162
VSS39 VSS40
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_B_D48 163 164 DDR_B_D52

DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53
1 DQ49 DQ53
@ CD35
330U_2.5V_M
1 1 1 1 1 1 1 167 168
VSS41 VSS42
CD29
CD30
CD31
CD32
CD33
CD34
CD36
+ DDR_B_DQS#6 169 170

DDR_B_DQS6 171 DQS#6 DM6 172
+V_DDR_REF, +SM_VREF_DIMM, +DIMM1_VREF_CA,+SM_VREF, +DIMM1_VREF_CA
173 DQS6 VSS43 174 DDR_B_D54 traces should be at least 20 mils wide and 20 mils spacing to other signals /planes.
2 2 2 2 2 2 2 2 DDR_B_D50 175 VSS44 DQ54 176 DDR_B_D55
DDR_B_D51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_B_D60
DDR_B_D57 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDR_B_DQS#7
187 VSS48 DQS#7 188 DDR_B_DQS7
189 DM7 DQS7 190
DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63
+3.3V_RUN 195 DQ59 DQ63 196
DIMM2_SA0 197 VSS51 VSS52 198
Layout Note: 199 SA0 EVENT# 200
Place near JDIMM2.203,204 201 VDDSPD SDA 202 DDR_XDP_WAN_SMBDAT <13,15,18,31>
DIMM2_SA1
SA1 SCL DDR_XDP_WAN_SMBCLK <13,15,18,31>
0.1U_0402_25V6
2.2U_0402_6.3V6M
203 204
+0.675V_DDR_VTT VTT1 VTT2 +0.675V_DDR_VTT
1 1
CD43
CD44
205 206
G1 G2
TYCO_2-2013311-1
2 2 CONN@
+0.675V_DDR_VTT
A A
2 1 DIMM2_SA0
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
@ RD11 0_0402_5%
1 1 1 1
CD39
CD40
CD41
CD42
2 2 2 2 +3.3V_RUN DELL CONFIDENTIAL/PROPRIETARY

2 1 DIMM2_SA1
@ RD12 0_0402_5% PROPRIETARY NOTE: Compal Electronics, Inc.
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDRIII-SODIMM SLOT2
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Date: Friday, May 09, 2014 Sheet 14 of 71
5 4 3 2 1
5 4 3 2 1
+RTC_CELL
PCH XDP
PXDP@ RH3 1 2 0_0402_5% XDP_FN0 +3.3V_ALW_PCH JXDP2
<19,40,41,42> USB_OC0#
330K_0402_1%
PXDP@ RH4 1 2 0_0402_5% XDP_FN1 1 2
<17,19,42> USB_OC1# GND0 GND1
1
PXDP@ RH6 1 2 0_0402_5% XDP_FN2 +3.3V_ALW_PCH 3 4 XDP_FN16
<17,19> USB_OC2# OBSFN_A0 OBSFN_C0
RH5
PXDP@ RH7 1 2 0_0402_5% XDP_FN3 5 6 XDP_FN17
<19> USB_OC3# OBSFN_A1 OBSFN_C1
0.1U_0402_25V6
PXDP@ RH8 1 2 0_0402_5% XDP_FN4 7 8
<19,43> USB_OC4# PXDP@ RH9 1 2 0_0402_5% XDP_FN5 XDP_FN0 9 GND2 GND3 10 XDP_FN8
<19> USB_OC5# 1 OBSDATA_A0 OBSDATA_C0
PXDP@
PXDP@ RH17 1 2 0_0402_5% XDP_FN6 XDP_FN1 11 12 XDP_FN9
2
<19> USB_OC6# OBSDATA_A1 OBSDATA_C1
CH2
PXDP@ RH10 1 2 0_0402_5% XDP_FN7 13 14
<19,46> SIO_EXT_SMI# HDD_DET# PXDP@ RH11 1 2 0_0402_5% XDP_FN8 XDP_FN2 15 GND4 GND5 16 XDP_FN10
PCH_INTVRMEN <15,17,31> HDD_DET# BBS_BIT0_R PXDP@ RH13 1 2 0_0402_5% XDP_FN9 2 XDP_FN3 17 OBSDATA_A2 OBSDATA_C2 18 XDP_FN11
D D
PCH_GPIO36 PXDP@ RH12 1 2 0_0402_5% XDP_FN10 19 OBSDATA_A3 OBSDATA_C3 20
<20> PCH_GPIO36 PCH_GPIO37 PXDP@ RH14 1 2 0_0402_5% XDP_FN11 21 GND6 GND7 22
<20> PCH_GPIO37 MCARD_PCIE_SATA# PXDP@ RH16 1 2 0_0402_5% XDP_FN12 23 OBSFN_B0 OBSFN_D0 24
INTVRMEN - INTEGRATED SUS 1.05V VRM <20,45> MCARD_PCIE_SATA# PCH_GPIO49 PXDP@ RH19 1 2 0_0402_5% XDP_FN13 25 OBSFN_B1 OBSFN_D1 26
<20> PCH_GPIO49 GND8 GND9
ENABLE <17,33> LANCLK_REQ#
LANCLK_REQ# PXDP@ RH20 1 2 0_0402_5% XDP_FN14 XDP_FN4 27
OBSDATA_B0 OBSDATA_D0
28 XDP_FN12
High - Enable Internal VRs MMICLK_REQ# PXDP@ RH22 1 2 0_0402_5% XDP_FN15 XDP_FN5 29 30 XDP_FN13
<17,36> MMICLK_REQ# SIO_EXT_WAKE# PXDP@ RH24 1 2 0_0402_5% XDP_FN16 31 OBSDATA_B1 OBSDATA_D1 32 +3.3V_ALW_PCH_JTAG
Low - Enable External VRs <17,20,45> SIO_EXT_WAKE# PCH_GPIO35 PXDP@ RH25 1 2 0_0402_5% XDP_FN17 XDP_FN6 33 GND10 GND11 34 XDP_FN14
<20> PCH_GPIO35 PCH_RSMRST#_Q PXDP@ RH26 1 2 1K_0402_1% RSMRST#_XDP XDP_FN7 35 OBSDATA_B2 OBSDATA_D2 36 XDP_FN15
<16,47> PCH_RSMRST#_Q OBSDATA_B3 OBSDATA_D3
RESET_OUT# PXDP@ RH27 1 2 1K_0402_1% RESET_OUT#_R 37 38
<10,16,46> RESET_OUT# GND12 GND13
1
RSMRST#_XDP 39 40 +1.05V_RUN
1 2 PCH_PWRBTN#_XDP 41 PWRGOOD/HOOK0 ITPCLK/HOOK4 42 RH52
<16,7> SIO_PWRBTN#_R HOOK1 ITPCLK#/HOOK5
PXDP@ RH28 0_0402_5% 43 44 +3.3V_ALW_PCH 210_0402_1%
45 VCC_OBS_AB VCC_OBS_CD 46 RESET_OUT#_R
47 HOOK2 RESET#/HOOK6 48 XDP_DBRESET#
2
PXDP@ RH30 0_0402_5% 49 HOOK3 DBR#/HOOK7 50 XDP_DBRESET# <16,7>
1 2 DDR_XDP_WAN_SMBDAT_R2 51 GND14 GND15 52 PCH_JTAG_TDO
<13,14,18,31> DDR_XDP_WAN_SMBDAT SDA TD0
1 2 DDR_XDP_WAN_SMBCLK_R2 53 54 PCH_JTAG_RST_R 1 2 PCH_JTAG_RST
<13,14,18,31> DDR_XDP_WAN_SMBCLK SCL TRST#
PXDP@ RH31 0_0402_5% 55 56 PCH_JTAG_TDI @ RH32 0_0402_5%
PCH_JTAG_TCK 57 TCK1 TDI 58 PCH_JTAG_TMS
TCK0 TMS
1
+3.3V_RUN +3.3V_ALW_PCH 59 60 PXDP@
GND16 GND17 RH56
SAMTE_BSH-030-01-L-D-A CONN@ 100_0402_1%
1 2 SPKR 1 2 PCH_AZ_SDOUT
@ RH34 10K_0402_5% @ RH35 1K_0402_1%
2
+3.3V_RUN
NO REBOOT STRAP FLASH DESCRIPTOR SECURITY OVERRIDE
DISABLED WHEN LOW (DEFAULT) LOW = DESABLED (DEFAULT) BBS_BIT0_R 2 1
ENABLED WHEN HIGH HIGH = ENABLED CH4 4.7K_0402_5% RH37
1 2 PCH_RTCX1_R 1 2 PCH_RTCX1
@ RH38 0_0402_5%
C C
18P_0402_50V8J
1
YH1 RH39 UH1A DH82LPMS-QCG1-B0_FCBGA695~D
+3.3V_RUN 32.768KHZ_12.5PF_Q13FC1350000 10M_0402_5%
BC8 PSATA_PRX_DTX_N0_C
2
1 2 B5 SATA_RXN_0 BE8 PSATA_PRX_DTX_N0_C <31>
PCH_GPIO33 PSATA_PRX_DTX_P0_C
2
RTCX1 SATA_RXP_0 PSATA_PRX_DTX_P0_C <31>
@ RH40 10K_0402_5% CH5 HDD
1 2 PCH_RTCX2 B4 AW8 PSATA_PTX_DRX_N0_C
Follow Check list 1.0 RTCX2 SATA_TXN_0 AY8 PSATA_PTX_DRX_P0_C PSATA_PTX_DRX_N0_C <31>
RTC
RH42 1 2 20K_0402_1% 18P_0402_50V8J SRTCRST# B9 SATA_TXP_0 PSATA_PTX_DRX_P0_C <31>
+RTC_CELL SRTCRST# BC10 SATA_ODD_PRX_DTX_N1_C
SATA_RXN_1 SATA_ODD_PRX_DTX_N1_C <32>
RH43 1 2 1M_0402_5% INTRUDER# A8 BE10 SATA_ODD_PRX_DTX_P1_C
INTRUDER# SATA_RXP_1 SATA_ODD_PRX_DTX_P1_C <32>
ODD/ E Module Bay
PCH_INTVRMEN G10 AV10 SATA_ODD_PTX_DRX_N1_C
INTVRMEN SATA_TXN_1 AW10 SATA_ODD_PTX_DRX_P1_C SATA_ODD_PTX_DRX_N1_C <32>
RH44 1 2 20K_0402_1% PCH_RTCRST# D9 SATA_TXP_1 SATA_ODD_PTX_DRX_P1_C <32>
RTCRST# BB9 SATA_PRX_DKTX_N2_C
SATA_RXN_2 SATA_PRX_DKTX_N2_C <44>
BD9 SATA_PRX_DKTX_P2_C
<35> PCH_RTCRST# SATA_RXP_2 SATA_PRX_DKTX_P2_C <44>
CMOS_CLR1 CMOS setting PCH_AZ_BITCLK B25 DOCK
HDA_BCLK AY13 SATA_PTX_DKRX_N2_C
1 2 1 2 PCH_AZ_SYNC A22 SATA_TXN_2 AW13 SATA_PTX_DKRX_P2_C SATA_PTX_DKRX_N2_C <44>
Shunt Clear CMOS 1 2 1 2 HDA_SYNC SATA_TXP_2 SATA_PTX_DKRX_P2_C <44>
Open Keep CMOS SPKR AL10 BC12

<30> SPKR SPKR SATA_RXN_3 BE12
@ @ PCH_AZ_RST# C24 SATA_RXP_3
ME1 SHORT PADS~D CMOS1 SHORT PADS~D HDA_RST# AR13
ME_CLR1 TPM setting SATA_TXN_3
AZALIA
1 2 1 2 PCH_AZ_CODEC_SDIN0 L22 AT13
SATA
1U_0402_6.3V6K <30> PCH_AZ_CODEC_SDIN0 HDA_SDI0 SATA_TXP_3
Shunt Clear ME RTC Registers CH6 1U_0402_6.3V6K CH7
CMOS place near DIMM K22
HDA_SDI1 BD13 PCIE_SATA_PRX_WANTX_N4
Open Keep ME RTC Registers G22 SATA_RXN4/PERN1 BB13 PCIE_SATA_PRX_WANTX_P4
PCIE_SATA_PRX_WANTX_N4 <38>
HDA_SDI2 SATA_RXP4/PERP1 PCIE_SATA_PRX_WANTX_P4 <38>
WWAN (JMINI1)
F22 AV15 PCIE_SATA_PTX_WANRX_N4
HDA_SDI3 SATA_TXN4/PETN1 AW15 PCIE_SATA_PTX_WANRX_P4 PCIE_SATA_PTX_WANRX_N4 <38>
SATA_TXP4/PETP1 PCIE_SATA_PTX_WANRX_P4 <38> SATA by default
B
<45> ME_FWP
1 2 PCH_AZ_SDOUT A24 B
RH45 1K_0402_1% HDA_SDO BC14
PCH_GPIO33 B17 SATA_RXN5/PERN2 BE14
DOCKEN#/GPIO33 SATA_RXP5/PERP2
+3.3V_ALW_PCH USB30_SMI# C22 AP15
<32,45> USB30_SMI# HDA_DOCK_RST#/GPIO13 SATA_TXN5/PETN2 AR15
SATA_TXP5/PETP2
1
0_0603_5%
RH46
PXDP@
AY5 SATA_COMP
SATA_RCOMP
AP3 SATA_ACT#
SATALED# SATA_ACT# <24>
2
RH47 2 1 51_0402_1% PCH_JTAG_TCK AB3 AT1 HDD_DET#

JTAG_TCK SATA0GP/GPIO21 HDD_DET# <15,17,31>
+3.3V_ALW_PCH_JTAG RH48 1 2 210_0402_1% PCH_JTAG_TMS AD1 AU2 BBS_BIT0_R 1 3
S
JTAG_TMS SATA1GP/GPIO19 PCH_SATA_MOD_EN# <46>
RH50 1 2 210_0402_1% PCH_JTAG_TDI AE2 BD4 SATA_IREF 2 1
JTAG
JTAG_TDI SATA_IREF +1.5V_RUN
@ RH51 0_0402_5% QH2
G
2
PCH_JTAG_TDO AD3 BA2 BSS138W-7-F_SOT323-3~D
JTAG_TDO TP9
PXDP@ RH54
PXDP@ RH55
PAD~D T57 @
<16,7> PCH_PLTRST#
1 2 PCH_TP25 F8 BB2
TP25 TP8
100_0402_1%
100_0402_1%
@ RH53 0_0402_5% PAD~D T58 @

1
C26
@ T59 PAD~D TP22
PCH_JTAG_RST AB6
TP20
SATA Impedance Compensation
2
1 OF 11
HDA for Codec RPH10

DH82LPMS-QCG1-B0_FCBGA695~D
SATA_COMP 1 2
+1.5V_RUN
7.5K_0402_1% RH57
1 8 PCH_AZ_BITCLK
UH1 change PN to SA00005NE2L IC A31 DH82LPMS QCG1 B0 FCBGA 695P PCH
<30> PCH_AZ_CODEC_BITCLK
2 7 PCH_AZ_SDOUT CAD note:
<30> PCH_AZ_CODEC_SDOUT
3 6 PCH_AZ_RST#
A <30> PCH_AZ_CODEC_RST#
4 5 PCH_AZ_SYNC
Place the resistor within 500 mils of the PCH. Avoid A
<30> PCH_AZ_CODEC_SYNC routing next to clock pins.
33_8P4R_5%
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PCH (1/9)
1.0
5 4 3 2 1
5 4 3 2 1
SYS_RESET# +3.3V_RUN
1 2 RPH4
@ RH66 0_0402_5% PCI_PIRQA# 1 8
+3.3V_RUN +RTC_CELL PCI_PIRQB# 2 7
1
+PCH_VCCDSW3_3 @ CH10 EMC@ PCI_PIRQC# 3 6
330K_0402_1%
1 2 C1554 PCI_PIRQD# 4 5
2
0.047U_0402_25V7K
5
2
RH67
1 2 PCH_PCIE_WAKE# 0.1U_0402_25V6 8.2K_8P4R_5%
RH92 10K_0402_5% 1
ESD Request
P
<15,7> XDP_DBRESET# B
1 2 SIO_SLP_LAN# 4 SYS_RESET# close PCH
@ RH80 10K_0402_5% 2 1 ME_RESET# 2 O SYS_RESET# <35>
1
G
@ RH70 8.2K_0402_5% A @ UC3 RPH6
74AHC1G09GW_TSSOP5 <20> PCH_GPIO07 4 5
3
+3.3V_ALW_PCH +3.3V_ALW2 PCH_GPIO55 XFR_ID# 3 6
@ CH11 DSWODVREN CAM_MIC_CBL_DET# 2 7
D 1 2 LCD_CBL_DET# 1 8 D
1
330K_0402_1%
1K_0402_1%
1 2 PCH_PCIE_WAKE#
@ RH81
@ RH76
@ RH78 10K_0402_5% 0.1U_0402_25V6 10K_8P4R_5%
2
1 2 SUS_STAT#/LPCPD# PCH_DPWROK 1 2 PCH_RSMRST#_R
@ RH73 10K_0402_5% @ RH79 0_0402_5%
VCC
1 2 ME_SUS_PWR_ACK SIO_SLP_A# 1 PCH_CRT_DDC_CLK 2 1
2
RH75 10K_0402_5% IN B 4 PM_APWROK_R 2.2K_0402_5% RH88
PM_APWROK 2 OUT Y PCH_CRT_DDC_DAT 2 1
GND
1
+3.3V_RUN <46> PM_APWROK IN A
RESET_OUT# 1 2 SYS_PWROK UH2 2.2K_0402_5% RH89
@ RH85 0_0402_5%
1 2 CLKRUN# NL17SZ08DFT2G_SC70-5
3
RH90 8.2K_0402_5%
1 2 ME_RESET# DGPU_PWR_EN# 2 1
@ RH93 8.2K_0402_5% ME_SUS_PWR_ACK_R 1 2 SUSACK#_R DSWODVREN - ON DIE DSW VR ENABLE A16 SWAP OVERRIDE STRAP 8.2K_0402_5% RH328
@ RH91 0_0402_5%
1 2
@ RH87 0_0402_5%
HIGH = ENABLED (DEFAULT)
1 2 PCH_DPWROK LOW = DISABLED STP_A16OVR LOW = A16 SWAP OVERRIDE PCH_DDPB_CTRLCLK 2 1
RH120 100K_0402_5% HIGH = DEFAULT 2.2K_0402_5% RH255
PCH_DDPB_CTRLDATA 2 1
2.2K_0402_5% RH256
UH1B LPT_PCH_M_EDS
AW22
<6> DMI_CTX_PRX_N0 AR20 DMI_RXN_0
<6> DMI_CTX_PRX_N1 DMI_RXN_1 AJ35
FDI_RXN_0 FDI_CTX_PRX_N0 <9>
AP17
<6> DMI_CTX_PRX_N2 DMI_RXN_2
AV20 AL35
<6> DMI_CTX_PRX_N3 DMI_RXN_3 FDI_RXN_1 FDI_CTX_PRX_N1 <9>
AY22 AJ36 UH1E LPT_PCH_M_EDS
<6> DMI_CTX_PRX_P0 DMI_RXP_0 FDI_RXP_0 FDI_CTX_PRX_P0 <9>
AP20
<6> DMI_CTX_PRX_P1 DMI_RXP_1 AL36 PCH_CRT_BLU T45 R40 PCH_DDPB_CTRLCLK PCH_DDPB_CTRLCLK <26>
FDI_RXP_1 FDI_CTX_PRX_P1 <9> <25> PCH_CRT_BLU VGA_BLUE DDPB_CTRLCLK
AR17
<6> DMI_CTX_PRX_P2 DMI_RXP_2
AW20 AV43 PAD~D T62 @ PCH_CRT_GRN U44 R39 PCH_DDPB_CTRLDATA
C <6> DMI_CTX_PRX_P3 DMI_RXP_3 TP16 <25> PCH_CRT_GRN VGA_GREEN DDPB_CTRLDATA PCH_DDPB_CTRLDATA <26> C
BD21 AY45 PAD~D T63 @ PCH_CRT_RED V45 R35 PCH_DDPC_CTRLCLK <29>

<6> DMI_CRX_PTX_N0 DMI_TXN_0 TP5 <25> PCH_CRT_RED VGA_RED DDPC_CTRLCLK
BE20
<6> DMI_CRX_PTX_N1 DMI_TXN_1 DMI FDI AV45 PAD~D T60 @ PCH_CRT_DDC_CLK M43 R36
TP15 <25> PCH_CRT_DDC_CLK VGA_DDC_CLK DDPC_CTRLDATA PCH_DDPC_CTRLDATA <29>
BD17
<6> DMI_CRX_PTX_N2 BE18 DMI_TXN_2 AW44 M45 N40
PAD~D T61 @ PCH_CRT_DDC_DAT
CRT
<6> DMI_CRX_PTX_N3 DMI_TXN_3 TP10 <25> PCH_CRT_DDC_DAT VGA_DDC_DATA DDPD_CTRLCLK PCH_DDPD_CTRLCLK <29>
BB21 AL39 FDI_CSYNC 1 2 HSYNC N42 N38
<6> DMI_CRX_PTX_P0 DMI_TXP_0 FDI_CSYNC FDI_CSYNC <6> <25> PCH_CRT_HSYNC VGA_HSYNC DDPD_CTRLDATA PCH_DDPD_CTRLDATA <29>
BC20 RH94 20_0402_1%
<6> DMI_CRX_PTX_P1 DMI_TXP_1 AL40 FDI_INT 1 2 VSYNC N44
FDI_INT FDI_INT <6> <25> PCH_CRT_VSYNC VGA_VSYNC
BB17 RH95 20_0402_1% H45
<6> DMI_CRX_PTX_P2 BC18 DMI_TXP_2 AT45 DDPB_AUXN
FDI_IREF 2 1 1 2 CRT_IREF U40
DISPLAY
<6> DMI_CRX_PTX_P3 DMI_TXP_3 FDI_IREF +1.5V_RUN DAC_IREF
@ RH96 0_0402_5% RH97 649_0402_1% K43
2 1 DMI_IREF BE16 AU42 PAD~D T64 @ U39 DDPC_AUXN DPC_PCH_DOCK_AUX# <29>
+1.5V_RUN DMI_IREF TP17 VGA_IRTN
@ RH98 0_0402_5% J42
AW17 AU44 PAD~D T66 @ DDPD_AUXN DPD_PCH_DOCK_AUX# <29>
@ T65 PAD~D TP12 TP13 BIA_PWM_PCH N36 H43
<28> BIA_PWM_PCH EDP_BKLTCTL DDPB_AUXP
AV17 AR44 FDI_RCOMP 2 1
LVDS
TP7 FDI_RCOMP +1.5V_RUN
@ T67 PAD~D 7.5K_0402_1% RH99 PANEL_BKEN_PCH K36 K45
<28> PANEL_BKEN_PCH EDP_BKLTEN DDPC_AUXP DPC_PCH_DOCK_AUX <29>
+1.5V_RUN
1 2 DMI_RCOMP AY17
RH100 7.5K_0402_1% DMI_RCOMP ENVDD_PCH G36 J44
<28,45> ENVDD_PCH EDP_VDDEN DDPD_AUXP DPD_PCH_DOCK_AUX <29>
K40
1 2 SUSACK#_R R6 C8 DSWODVREN PCI_PIRQA# H20 DDPB_HPD HDMIB_PCH_HPD <26>
<45> SUSACK# SUSACK# DSWVRMEN PIRQA#
@ RH101 0_0402_5% K38
SYS_RESET# AM1 L13 PCH_DPWROK PCI_PIRQB# L20 DDPC_HPD DPC_PCH_DOCK_HPD <44>
SYS_RESET# DPWROK PCH_DPWROK <45> PIRQB# H39
1 2 SYS_PWROK_R AD7 K3 PCH_PCIE_WAKE# PCI_PIRQC# K17 DDPD_HPD DPD_PCH_DOCK_HPD <44>
<45,7> SYS_PWROK SYS_PWROK WAKE# PCH_PCIE_WAKE# <46> PIRQC#
@ RH102 0_0402_5%
1 2 PCH_PWROK F10 AN7 CLKRUN# PCI_PIRQD# M20
<10,15,46> RESET_OUT# PWROK CLKRUN# CLKRUN# <35,45,46> PIRQD#
@ RH103 0_0402_5% System Power G17 LCD_CBL_DET#
Management PIRQE#/GPIO2 LCD_CBL_DET# <28>
PM_APWROK_R AB7 U7 SUS_STAT#/LPCPD# A12
APWROK SUS_STAT#/GPIO61 SUS_STAT#/LPCPD# <35> <49> DGPU_HOLD_RST# GPIO50 F17 XFR_ID#
PCI PIRQF#/GPIO3 XFR_ID# <43>
1 2 PM_DRAM_PWRGD_R H3 Y6 SUSCLK PAD~D T68 @ B13
<7> PM_DRAM_PWRGD DRAMPWROK SUSCLK/GPIO62 <37> CPPE# GPIO52
B @ RH104 0_0402_5% L15 CAM_MIC_CBL_DET# B
PIRQG#/GPIO4 CAM_MIC_CBL_DET# <28>
1 2 PCH_RSMRST#_R J2 Y7 DGPU_PWR_EN# C12
<15,47> PCH_RSMRST#_Q RSMRST# SLP_S5#/GPIO63 SIO_SLP_S5# <35,46> <53> DGPU_PWR_EN# GPIO54
@ RH105 0_0402_5% M15 FFS_PCH_INT 2 1
PIRQH#/GPIO5 HDD_FALL_INT <31>
1 2 ME_SUS_PWR_ACK_R J4 C6 SIO_SLP_S4# BBS_BIT1 C10 0_0402_5% @ RH106
<46> ME_SUS_PWR_ACK SUSWARN#/SUSPWRNACK/GPIO30 SLP_S4# SIO_SLP_S4# <35,45,58> GPIO51
@ RH107 0_0402_5% AD10 @ T71 PAD~D
<15,7> SIO_PWRBTN#_R PME#
1 2 SIO_PWRBTN#_R K1 H1 SIO_SLP_S3# A10
<46> SIO_PWRBTN# PWRBTN# SLP_S3# SIO_SLP_S3# <35,39,40,45,60,62> <37> USB_MCARD1_DET# GPIO53
@ RH108 0_0402_5% Y11 PCH_PLTRST# @ RH109 2 1 0_0402_5%
PLTRST# PLTRST_USH# <35>
E6 F3 SIO_SLP_A# PCH_GPIO55 AL6 @ RH110 2 1 0_0402_5%
<46> AC_PRESENT ACPRESENT/GPIO31 SLP_A# SIO_SLP_A# <35,45,59> GPIO55 PLTRST_MMI# <36>
@ RH111 2 1 0_0402_5%
5 OF 11 PLTRST_LAN# <33>
+PCH_VCCDSW3_3 1 2 PCH_BATLOW# K7 F1 @ RH113 2 1 0_0402_5%
BATLOW#/GPIO72 SLP_SUS# SIO_SLP_SUS# <45> PLTRST_EMB# <32>
RH112 8.2K_0402_5% @ RH114 2 1 0_0402_5%
PCH_RI# N4 AY3 H_PM_SYNC DH82LPMS-QCG1-B0_FCBGA695~D PLTRST_GPU# <49>
<19> PCH_RI# RI# PMSYNCH H_PM_SYNC <7> +3.3V_RUN
@ T75 PAD~D AB10 G5 SIO_SLP_LAN# @ CH12
TP21 SLP_LAN# SIO_SLP_LAN# <39,45> 1 2
D2
<45> SIO_SLP_WLAN# SLP_WLAN#/GPIO29 0.1U_0402_25V6
4 OF 11 RPH17
UH3
5
1 8 PCH_CRT_RED NL17SZ08DFT2G_SC70-5
2 7 PCH_CRT_GRN
VCC
3 6 PCH_CRT_BLU PCH_PLTRST# 1
<15,7> PCH_PLTRST# IN B
4 5 4
OUT Y PCH_PLTRST#_EC <35,37,38,39,45,46>
2
GND
150_0804_8P4R_1% IN A
Boot BIOS Strap
1 2 ENVDD_PCH
3
SATA_SLPD RH118 100K_0402_5%
BBS_BIT1
BBS_BIT1 (BBS_BIT0) Boot BIOS Location
1K_0402_1%
0 0 LPC
1
@ RH119
A 0 1 Reserved (NAND) A
2
1 0 PCI
* 1 1 SPI DELL CONFIDENTIAL/PROPRIETARY

GPIO51 has internal pull up.
PROPRIETARY NOTE:
Title
1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW_PCH
RPH20 RPH8
4 5 MMICLK_REQ# USB_OC2# 4 5 +3.3V_ALW_PCH
+3.3V_RUN <15,19> USB_OC2#
3 6 HDD_DET# PEG_B_CLKRQ# 3 6
2 7 CLK_BUF_CKSSCD# HDD_DET# <15,31> MINI2CLK_REQ# 2 7
1 8 CLK_BUF_CKSSCD PCIECLKRQ6# 1 8 RPH18
GFX_CLK_REQ# 4 5
10K_8P4R_5% 10K_8P4R_5% LANCLK_REQ# 3 6
+3.3V_RUN
IRQ_SERIRQ 2 7
+3.3V_ALW_PCH <18,35,45,46> IRQ_SERIRQ 1 8
RPH9
RPH21 EMBCLK_REQ# 4 5 10K_8P4R_5%
D 4 5 MINI1CLK_REQ# EXPCLK_REQ# 3 6 D
+3.3V_ALW_PCH
3 6 PCH_SMB_ALERT# SIO_EXT_WAKE# 2 7
2 7 TEMP_ALERT# PCH_SMB_ALERT# <18> <15,20,45> SIO_EXT_WAKE# 1 8
1 8 PM_LANPHY_ENABLE TEMP_ALERT# <18,45> <15,19,42> USB_OC1#
+PCH_VCCDSW3_3 PM_LANPHY_ENABLE <20,33>
10K_8P4R_5%
10K_8P4R_5%
GFX_CLK_REQ#
L2N7002WT1G_SC-70-3
UH1C
1
LPT_PCH_M_EDS D
QH3
2
<45> 3.3V_RUN_GFX_ON
G
Y43 AB35 CLK_PCIE_VGA# S
3
<38> CLK_PCIE_MINI1# CLKOUT_PCIE_N_0 CLKOUT_PEG_A CLK_PCIE_VGA# <49>
WWAN (Mini Card 1)---> Y45 AB36 CLK_PCIE_VGA
<38> CLK_PCIE_MINI1 CLKOUT_PCIE_P_0 CLKOUT_PEG_A_P CLK_PCIE_VGA <49>
MINI1CLK_REQ# AB1 AF6 GFX_CLK_REQ#
<38> MINI1CLK_REQ# PCIECLKRQ0#/GPIO73 PEGA_CLKRQ#/GPIO47 GFX_CLK_REQ# <50>
AA44 Y39
<33> CLK_PCIE_LAN# AA42 CLKOUT_PCIE_N_1 CLKOUT_PEG_B
<33> CLK_PCIE_LAN CLKOUT_PCIE_P_1 Y38
10/100/1G LAN ---> CLKOUT_PEG_B_P
LANCLK_REQ# AF1
<15,33> LANCLK_REQ# PCIECLKRQ1#/GPIO18 U4 PEG_B_CLKRQ#
AB43 PEGB_CLKRQ#/GPIO56
<36> CLK_PCIE_MMI# CLKOUT_PCIE_N_2 AF39 CLK_CPU_DMI#
AB45 CLKOUT_DMI CLK_CPU_DMI# <7>
MMI---> <36> CLK_PCIE_MMI CLKOUT_PCIE_P_2 AF40 CLK_CPU_DMI RPH5
MMICLK_REQ# AF3 CLKOUT_DMI_P CLK_CPU_DMI <7> CLK_BUF_BCLK# 4 5
<15,36> MMICLK_REQ# PCIECLKRQ2#/GPIO20/SMI# AJ40 CLK_CPU_SSC_DPLL# CLK_BUF_BCLK 3 6
AD43 CLKOUT_DP AJ39 CLK_CPU_SSC_DPLL CLK_CPU_SSC_DPLL# <7> CLK_BUF_DMI# 2 7
<37> CLK_PCIE_MINI3# AD45 CLKOUT_PCIE_N_3 CLKOUT_DP_P CLK_CPU_SSC_DPLL <7> CLK_BUF_DMI 1 8
C
PP (Mini Card 3)---> <37> CLK_PCIE_MINI3 CLKOUT_PCIE_P_3 C
MINI3CLK_REQ# T3 AF35 CLK_CPU_DPLL#
<19,37> MINI3CLK_REQ# PCIECLKRQ3#/GPIO25 CLKOUT_DPNS AF36 CLK_CPU_DPLL CLK_CPU_DPLL# <7> 10K_8P4R_5%
AF43 CLKOUT_DPNS_P CLK_CPU_DPLL <7>
<39> CLK_PCIE_EXP# AF45 CLKOUT_PCIE_N_4 AY24 CLK_BUF_DMI# CLK_PCH_14M RH1461 2 10K_0402_5%
<39> CLK_PCIE_EXP EXPCLK_REQ# V3 CLKOUT_PCIE_P_4 CLKIN_DMI AW24 CLK_BUF_DMI
Express card---> <39> EXPCLK_REQ# PCIECLKRQ4#/GPIO26 CLOCK SIGNAL CLKIN_DMI_P
AE44 AR24 CLK_BUF_BCLK#
<37> CLK_PCIE_MINI2# AE42 CLKOUT_PCIE_N5 CLKIN_GND AT24 CLK_BUF_BCLK
<37> CLK_PCIE_MINI2 MINI2CLK_REQ# AA2 CLKOUT_PCIE_P_5 CLKIN_GND_P
<37> MINI2CLK_REQ# PCIECLKRQ5#/GPIO44 H33 CLK_BUF_DOT96#
WLAN (Mini Card 2)---> CLKIN_DOT96N
AB40 G33 CLK_BUF_DOT96
AB39 CLKOUT_PCIE_N_6 CLKIN_DOT96P
PCIECLKRQ6# AE4 CLKOUT_PCIE_P_6 BE6 CLK_BUF_CKSSCD#
PCIECLKRQ6#/GPIO45 CLKIN_SATA BC6 CLK_BUF_CKSSCD
AJ44 CLKIN_SATA_P CLOCK TERMINATION for FCIM and need close to PCH
<32> CLK_PCIE_EMB# CLKOUT_PCIE_N_7 F45 CLK_PCH_14M
AJ42 REFCLK14IN D17 CLK_PCI_LOOPBACK
eModule Bay---> <32> CLK_PCIE_EMB CLKOUT_PCIE_P_7 CLKIN_33MHZLOOPBACK
EMBCLK_REQ# Y3 AM43 XTAL25_IN 2 1
<32> EMBCLK_REQ# PCIECLKRQ7#/GPIO46 XTAL25_IN AL44 XTAL25_OUT 1 2 0_0402_5%
@ RH152
AH43 XTAL25_OUT EMC@ RH153 1M_0402_5%
XTAL25_IN_R
CLKOUT_ITPXDP C40 PCI_TPM_TCM RH155 2 1 22_0402_5%
AH45 CLKOUTFLEX0/GPIO64 CLK_PCI_TPM <35>
CLKOUT_ITPXDP_P F38 SIO_14M RH157 2 1 22_0402_5%
2 1 22_0402_5% PCI_5048 D44 CLKOUTFLEX1/GPIO65 CLK_SIO_14M <45>
EMC@ RH158
<45> CLK_PCI_5048 CLKOUT_33MHZ0 F36 CLK_80H 2 1 22_0402_5%
RH159 YH2
2 1 22_0402_5% PCI_MEC E44 CLKOUTFLEX2/GPIO66 PCLK_80H <37>
EMC@ RH160 25MHZ 10PF +-20PPM 7V25000014
<46> CLK_PCI_MEC CLKOUT_33MHZ1 F39 3 1
EMC@ RH162 2 1 22_0402_5% PCI_DOCK B42 CLKOUTFLEX3/GPIO67 OUT IN
<44> CLK_PCI_DOCK CLKOUT_33MHZ2 AM45 ICLK_IREF 1 2 4 2
ICLK_IREF +1.5V_RUN GND GND
12P_0402_50V8J
12P_0402_50V8J
F41 @ RH163 0_0402_5% 2 2
CLKOUT_33MHZ3
CH13
CH14
AD39
B CLK_PCI_LOOPBACK EMC@ RH164 2 1 22_0402_5% PCI_LOOPBACKOUT A40 TP19 AD38 PAD~D T76 @ B
CLKOUT_33MHZ4 TP18 PAD~D T77 @
AN44 PCH_CLK_BIASREF 1 2 1 1
DIFFCLK_BIASREF +1.5V_RUN
7.5K_0402_1% RH165
2 OF 11
PCIECLK REQ Pull UP Power Rail: DH82LPMS-QCG1-B0_FCBGA695~D

SUS Rail : 0 3 4 5 6 7 RPH19
Core Rail: 1 2 CLK_BUF_DOT96#
CLK_BUF_DOT96
4
3
5
6
PCH_GPIO06 2 7
<20> PCH_GPIO06
CONTACTLESS_DET# 1 8
<20,35> CONTACTLESS_DET# +3.3V_RUN
CLK_PCI_DOCK
10K_8P4R_5%
1
@ RH330
33_0402_5%
100P_0402_50V8J
2
1
@
CH76
A A
PROPRIETARY NOTE:
Title
1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
2
MEM_SMBCLK 6 1
DDR_XDP_WAN_SMBCLK <13,14,15,31>
QH4A
5
D +3.3V_ALW_PCH D
MEM_SMBDATA 3 4
DDR_XDP_WAN_SMBDAT <13,14,15,31>
QH4B
DMN66D0LDW-7_SOT363-6 DDR_HVREF_RST_PCH 2 1
1K_0402_1% RH170
RPH12
SML1_SMBDATA 1 8
SML1_SMBCLK 2 7
UH1D LPT_PCH_M_EDS
MEM_SMBCLK 3 6
MEM_SMBDATA 4 5
2.2K_8P4R_5%
N7 PCH_SMB_ALERT#
A20 SMBALERT#/GPIO11 PCH_SMB_ALERT# <17>
<35,37,45,46> LPC_LAD0 LAD_0 R10 MEM_SMBCLK
SMBus
C20 SMBCLK
<35,37,45,46> LPC_LAD1 LAD_1 U11 MEM_SMBDATA
A18 SMBDATA
LPC
<35,37,45,46> LPC_LAD2 LAD_2 N8 DDR_HVREF_RST_PCH
C18 SML0ALERT#/GPIO60 DDR_HVREF_RST_PCH <13,14,7>
<35,37,45,46> LPC_LAD3 LAD_3 U8 LAN_SMBCLK
B21 SML0CLK LAN_SMBCLK <33>
<35,37,45,46> LPC_LFRAME# LFRAME# R7 LAN_SMBDATA
D21 SML0DATA LAN_SMBDATA <33> +3.3V_LAN
@ T87 PAD~D LPC_LDRQ0#
LDRQ0# H6 TEMP_ALERT#
G20 SML1ALERT#/PCHHOT#/GPIO74 TEMP_ALERT# <17,45> LAN_SMBCLK 2 1
<45> LPC_LDRQ1# LDRQ1#/GPIO23 K6 SML1_SMBCLK 2.2K_0402_5% RH174
IRQ_SERIRQ AL11 SML1CLK/GPIO58 SML1_SMBCLK <46> LAN_SMBDATA 2 1
<17,35,45,46> IRQ_SERIRQ SERIRQ N11 SML1_SMBDATA 2.2K_0402_5% RH175
SML1DATA/GPIO75 SML1_SMBDATA <46>
C C
AF11 PCH_CL_CLK1
AJ11 CL_CLK PCH_CL_CLK1 <37>
PCH_SPI_CLK
SPI_CLK AF10 PCH_CL_DATA1
PCH_SPI_CS0# AJ7 C-Link CL_DATA PCH_CL_DATA1 <37>
SPI_CS0# AF7 PCH_CL_RST1#
PCH_SPI_CS1# AL7 CL_RST# PCH_CL_RST1# <37>
SPI_CS1#
AJ10
SPI_CS2#
SPI
BA45 PAD~D T78 @
PCH_SPI_DO AH1 TP1
SPI_MOSI BC45 PAD~D T79 @
PCH_SPI_DIN AH3 Thermal TP2
SPI_MISO BE43 PAD~D T80 @
PCH_SPI_DO2 AJ4 TP4
SPI_IO2 BE44 PAD~D T81 @
PCH_SPI_DO3 AJ2 TP3
SPI_IO3 AY43 PCH_TD_IREF 1 2
TD_IREF RH176 8.2K_0402_1%
3 OF 11
+3.3V_SPI
1 2 SPI_PCH_DO2_64 +3.3V_SPI
R3664 1K_0402_5%
1 2 SPI_PCH_DO3_64 C746
R3668 1K_0402_5% 200 MIL SO8 1 2
1 2 SPI_PCH_DO2_32
B R3665 1K_0402_5% 64Mb Flash ROM 0.1U_0402_25V6 B
1 2 SPI_PCH_DO3_32 U52
R3666 1K_0402_5% SPI_PCH_CS0# R7 1 2 47_0402_5% SPI_PCH_CS0#_R 1 8 JSPI1
SPI_DIN64 2 /CS VCC 7 SPI_PCH_DO3_64 R3669 1 2 33_0402_5% SPI_PCH_DO3 2 1 SPI_PCH_CS1# 1
SPI_PCH_DO2_64 3 DO(IO1) /HOLD(IO3) 6 SPI_CLK64 0_0402_5% RH177 @ PCH_SPI_CS1# 2 1
4 /WP(IO2) CLK 5 SPI_DO64 2 1 SPI_PCH_DO 3 2
SPI_WP#_SEL 2 1 GND DI(IO0) 0_0402_5% RH178 @ PCH_SPI_DO 4 3
<45> SPI_WP#_SEL 2 1 SPI_PCH_DIN 5 4
@ RH180 0_0402_5% W25Q64FVSSIQ_SO8
0_0402_5% RH179 @ PCH_SPI_DIN 6 5
SPI@ 6
RPH7 2 1 SPI_PCH_CLK 7
SPI_CLK64 1 8 SPI_PCH_CLK 0_0402_5% RH181 @ PCH_SPI_CLK 8 7
SPI_DO64 2 7 SPI_PCH_DO 2 1 SPI_PCH_CS0# 9 8
SPI_CLK32 3 6 SPI_PCH_CLK 0_0402_5% RH182 @ PCH_SPI_CS0# 10 9
RPH11 SPI_PCH_DO3_324 5 SPI_PCH_DO3 2 1 SPI_PCH_DO2 11 10
SPI_PCH_DIN 1 8 SPI_DIN64 0_0402_5% RH183 @ PCH_SPI_DO2 12 11
SPI_PCH_DO2 2 7 SPI_PCH_DO2_64 33_8P4R_5% 2 1 SPI_PCH_DO3 13 12
SPI_PCH_DIN 3 6 SPI_DIN32 0_0402_5% RH184 @ PCH_SPI_DO3 14 13
SPI_PCH_DO2 4 5 SPI_PCH_DO2_32 15 14
+3.3V_SPI 15
16
+3.3V_M 16
33_8P4R_5% +3.3V_SPI 17
2 1 18 17
C1216 0_0402_5% RH185 @ 19 18
200 MIL SO8 1 2 20 19
20
32Mb Flash ROM 0.1U_0402_25V6 21
U53 22 GND1
SPI_PCH_CS1# R936 1 2 47_0402_5% SPI_PCH_CS1#_R 1 8 GND2
SPI_DIN32 2 /CS VCC 7 SPI_PCH_DO3_32 TYCO_2-2041070-0
SPI_PCH_DO2_32 3 DO/IO1 /HOLD/IO3 6 SPI_CLK32 CONN@
4 /WP/IO2 CLK 5 SPI_DO32 1 2 SPI_PCH_DO
SPI_WP#_SEL 2 1 GND DI/IO0 R901 33_0402_5%
@ RH186 0_0402_5% W25Q32FVSSIQ_SO8
A A
SPI@
PROPRIETARY NOTE:
Title
1.0
5 4 3 2 1
5 4 3 2 1
D D
UH1I LPT_PCH_M_EDS
AW31 B37
<44> USB3RN3 PERN1/USB3RN3 USB2N0 USBP0- <40>
<44> USB3RP3
AY31
PERP1/USB3RP3 USB2P0
D37
USBP0+ <40>
----->Rear Side
MLK DOCK -----> USB2N1
A38
USBP1- <41>
<44> USB3TN3
BE32
PETN1/USB3TN3 USB2P1
C38
USBP1+ <41>
----->Right Side Top
BC32 A36
<44> USB3TP3 PETP1/USB3TP3 USB2N2 USBP2- <42>
USB2P2
C36
USBP2+ <42>
----->Right Side bottom
AT31 A34
<33> PCIE_PRX_GLANTX_N2 PERN2/USB3RN4 USB2N3 USBP3- <44>
<33> PCIE_PRX_GLANTX_P2
AR31
PERP2/USB3RP4 USB2P3
C34
USBP3+ <44>
----->DOCK
10/100/1G LAN ---> B33
USB2N4 USBP4- <37>
<33> PCIE_PTX_GLANRX_N2
BD33
PETN2/USB3TN4 USB2P4
D33
USBP4+ <37>
----->WLAN/WIMAX
BB33 F31
<33> PCIE_PTX_GLANRX_P2 PETP2/USB3TP4 USB2N5 G31 USBP5- <38> ----->WWAN/UWB
USB2P5 K31 USBP5+ <38>
AW33 USB2N6 L31 USBP6- <44> ----->DOCK
<37> PCIE_PRX_WLANTX_N3 PERN_3 USB2P6 USBP6+ <44>
AY33 G29
WLAN (JMINI2)--->
<37> PCIE_PRX_WLANTX_P3 PERP_3 USB2N7 H29 USBP7- <35> ----->USH
BE34 USB2P7 A32 USBP7+ <35>
<37> PCIE_PTX_WLANRX_N3 BC34 PETN_3 USB2N8 C32 USBP8- <37> ----->WPAN
<37> PCIE_PTX_WLANRX_P3 PETP_3 USB2P8 A30 USBP8+ <37>
AT33 USB2N9 C30 USBP9- <43> ----->Left Side USBRBIAS
C <32> PCIE_PRX_EMBTX_N4 AR33 PERN_4 USB2P9 B29 USBP9+ <43> C
<32> PCIE_PRX_EMBTX_P4 PERP_4 USB2N10 USBP10- <39>
----->Express Card
22.6_0402_1%
E3 Module Bay---> D29
USB2P10 USBP10+ <39>
1
BE36 A28
<32> PCIE_PTX_EMBRX_N4 PETN_4 USB2N11
RH187
BC36 C28
<32> PCIE_PTX_EMBRX_P4 PETP_4 USB2P11 G26
USB2N12 USBP12- <28>
----->Camera
PCIe
AW36 F26
USB
AV36 PERN_5 USB2P12 F24 USBP12+ <28>
2
PERP_5 USB2N13 USBP13-
USB2P13
G24
USBP13+
----->Touch
BD37
BB37 PETN_5
PETP_5 AR26
AY38 USB3RN1 AP26 USB3RN1 <40>
<37> PCIE_PRX_WPANTX_N6 PERN_6 USB3RP1 USB3RP1 <40> CAD NOTE:
AW38 BE24
Pink Pather (JMINI3)--->
<37> PCIE_PRX_WPANTX_P6 PERP_6 USB3TN1 BD23 USB3TN1 <40> ----->Rear Side Route single-end 50-ohms and max 500-mils length.
BC38 USB3TP1 AW26 USB3TP1 <40> Avoid routing next to clock pins or under stitching capacitors.
<37> PCIE_PTX_WPANRX_N6 BE38 PETN_6 USB3RN2 AV26 USB3RN2 <41>
<37> PCIE_PTX_WPANRX_P6 PETP_6 USB3RP2 USB3RP2 <41> Recommended minimum spacing to other signal traces is 15 mils.
BD25
AT40 USB3TN2 BC24 USB3TN2 <41> ----->Right Side Top
<39> PCIE_PRX_EXPTX_N7 AT39 PERN_7 USB3TP2 AW29 USB3TP2 <41>
<39> PCIE_PRX_EXPTX_P7 PERP_7 USB3RN5 AV29 USB3RN5 <42>
EXPRESS Card---> USB3RP5 USB3RP5 <42>
<39> PCIE_PTX_EXPRX_N7
BE40
PETN_7 USB3TN5
BE26
USB3TN5 <42>
----->Right Side bottom
BC40 BC26
<39> PCIE_PTX_EXPRX_P7 PETP_7 USB3TP5 AR29 USB3TP5 <42>
AN38 USB3RN6 AP29 USB3RN6 <43>
<36> PCIE_PRX_MMITX_N8 AN39 PERN_8 USB3RP6 BD27 USB3RP6 <43> ----->Left Side
<36> PCIE_PRX_MMITX_P8 PERP_8 USB3TN6 BE28 USB3TN6 <43>
BD42 USB3TP6 USB3TP6 <43>
MMI ---> <36> PCIE_PTX_MMIRX_N8 PETN_8
BD41 K24 USBRBIAS
<36> PCIE_PTX_MMIRX_P8 PETP_8 USBRBIAS# K26
USBRBIAS
1 2 PCH_PCIE_IREF BE30 M33 PAD~D T82 @
+1.5V_RUN PCIE_IREF TP24
@ RH188 0_0402_5% L33 PAD~D T83 @
B TP23 B
@ T84 PAD~D BC30 P3 USB_OC0#
TP11 OC0#/GPIO59 V1 USB_OC1# USB_OC0# <15,40,41,42>
OC1#/GPIO40 U2 USB_OC2# USB_OC1# <15,17,42>
BB29 OC2#/GPIO41 P1 USB_OC2# <15,17>
@ T85 PAD~D USB_OC3#
TP6 OC3#/GPIO42 M3 USB_OC4# USB_OC3# <15>
OC4#/GPIO43 T1 USB_OC4# <15,43>
USB_OC5#
1 2 PCH_PCIE_RCOMP BD29 OC5#/GPIO9 N2 USB_OC6# USB_OC5# <15>
+1.5V_RUN PCIE_RCOMP OC6#/GPIO10 USB_OC6# <15>
RH192 7.5K_0402_1% M1 SIO_EXT_SMI#
OC7#/GPIO14 SIO_EXT_SMI# <15,46>
9 OF 11
+3.3V_ALW_PCH
RPH3
USB_OC5# 4 5
USB_OC3# 3 6
USB_OC0# 2 7
MINI3CLK_REQ# 1 8
<17,37> MINI3CLK_REQ#
10K_8P4R_5%
RPH1
USB_OC4# 4 5
SIO_EXT_SMI# 3 6
USB_OC6# 2 7
1 8
<16> PCH_RI#
10K_8P4R_5%
A A
PROPRIETARY NOTE:
Title
1.0
5 4 3 2 1
5 4 3 2 1
+PCH_VCCDSW3_3 Support Deep S3 mode
2 1 EC_WAKE# 1 2
LANWAKE# <33,46>
RH216 10K_0402_5% @ RH196 0_0402_5%
+3.3V_RUN UH1F LPT_PCH_M_EDS
2 1 AT8
<46> SIO_EXT_SCI# BMBUSY#/GPIO0
@ RH195 0_0402_5% +3.3V_RUN
USH_DET# F13
<35> USH_DET# TACH1/GPIO1
2 1 USH_DET# RPH14
RH202 100K_0402_5% PCH_GPIO06 A14 TPM_ID1 1 8
<17> PCH_GPIO06 TACH2/GPIO6
D 1 2 PCH_GPIO22 PCH_GPIO34 2 7 D
RH331 10K_0402_5% G15 CPU/Misc 3 6
SIO_A20GATE
<16> PCH_GPIO07 TACH3/GPIO7 SIO_RCIN# 4 5
SIO_EXT_WAKE# Y1
<15,17,45> SIO_EXT_WAKE# GPIO8
RPH16 10K_8P4R_5%
8 1 PCH_GPIO35 PM_LANPHY_ENABLE K13
<17,33> PM_LANPHY_ENABLE LAN_PHY_PWR_CTRL/GPIO12
7 2 TPM_ID0 AN10 SIO_A20GATE
TP14 SIO_A20GATE <46>
6 3 SIO_EXT_SCI# PCH_GPIO15 AB11
5 4 GPIO15 AY1 PAD~D T86 @
MCARD_PCIE_SATA# AN2 PECI
<15,45> MCARD_PCIE_SATA# SATA4GP/GPIO16
10K_8P4R_5% AT6 SIO_RCIN#
GPIO RCIN# SIO_RCIN# <46>
DGPU_PWROK C14
<45,62> DGPU_PWROK TACH0/GPIO17 AV3 H_CPUPWRGD +1.05V_RUN
PROCPWRGD H_CPUPWRGD <7>
PCH_GPIO22 BB4
<35> PCH_GPIO22 SCLOCK/GPIO22
RPH13 AV1 PCH_THRMTRIP#_R 2 1
8 1 PCH_GPIO71 PCH_GPIO24 Y10 THRMTRIP# RH206 56_0402_5%
GPIO24
0.1U_0402_25V6
7 2 PCH_GPIO70 AU4 CPU_PLTRST#
PLTRST_PROC# CPU_PLTRST# <7>
6 3 EC_WAKE# R11 1
<46> EC_WAKE# GPIO27
5 4 PCH_GPIO69 N10
VSS
CH17
SLP_ME_CSW_DEV# AD11
<45> SLP_ME_CSW_DEV# GPIO28
10K_8P4R_5%
PCH_GPIO34 AN6 2
GPIO34
PCH_GPIO35 AP1
<15> PCH_GPIO35 GPIO35/NMI#
PCH_GPIO36 AT3
<15> PCH_GPIO36 SATA2GP/GPIO36
1 2 PCH_GPIO22 PCH_GPIO37 AK1
<15> PCH_GPIO37 SATA3GP/GPIO37
RH332 @ 100K_0402_5%
TPM_ID0 AT7
SLOAD/GPIO38
TPM_ID1 AM3 A2
SDATAOUT0/GPIO39 VSS A41
AN4 VSS A43
<31> FFS_INT2 SDATAOUT1/GPIO48 VSS A44
C
PCH_GPIO49 AK3 VSS B1 C
<15> PCH_GPIO49 SATA5GP/GPIO49 VSS B2
+3.3V_ALW_PCH KB_DET# U12 VSS B44
<47> KB_DET# GPIO57 VSS CRB1.2 already change to GND directly at UH1.A44, B45, BD1 pins
B45
CONTACTLESS_DET# C16 VSS BA1
<17,35> CONTACTLESS_DET# TACH4/GPIO68 VSS BC1
RPH15 PCH_GPIO69 D13 VSS BD1
8 1 PCH_GPIO15 TACH5/GPIO69 VSS BD2
7 2 PCH_GPIO24 PCH_GPIO70 G13 VSS BD44
6 3 KB_DET# TACH6/GPIO70 VSS BD45
5 4 DGPU_PWROK PCH_GPIO71 H15 VSS BE2
TACH7/GPIO71 VSS BE3
10K_8P4R_5% VSS D1
BE41 VSS E1
BE5 VSS NCTF VSS E45
C45 VSS VSS A4
A5 VSS VSS
VSS
6 OF 11
+3.3V_ALW_PCH
+3.3V_RUN
2
4.7K_0402_5%
1 2 MCARD_PCIE_SATA#
RH222
RH224 10K_0402_5%
2 1 PCH_GPIO49
RH225 10K_0402_5%
1
SLP_ME_CSW_DEV# 2 1 MCARD_PCIE_SATA#
@ RH226 10K_0402_5%
B 2 1 PCH_GPIO49 B
1
1K_0402_1%
@ RH227 10K_0402_5%
@ RH223
2
+3.3V_RUN
Config GPIO16,49 2 1 PCH_GPIO36
@ RH228 1K_0402_1%
PLL ON DIE VR ENABLE 1 2 PCH_GPIO37
USB X4,PCIEX8,SATAX6 11 RH229 1K_0402_1%
ENABLED - HIGH(DEFAULT) 2 1 PCH_GPIO36
DISABLED - LOW * USB X6,PCIEX8,SATAX4 01 RH230 10K_0402_5%
2 1 PCH_GPIO37
@ RH231 10K_0402_5%
SATA2GP/GPIO36 , SATA3GP/GPIO37 SAMPLED AT RISING EDGE OF PWROK.

WEAK INTERNAL PULL-DOWN.(WEAK INTERNAL PULL-DOWN IS DISABLED AFTER
PLRST_N DE-ASSERTS).
NOTE: THIS SIGNAL SHOLD NOT BE PULLED HIGH WHEN STRAP IS SAMPLED.
A A
PROPRIETARY NOTE: Compal Electronics, Inc.
Title
1.0
5 4 3 2 1
5 4 3 2 1
LH1
+VCCADAC 2 1
+1.5V_RUN
BLM18PG181SN1D_2P
0.01U_0402_16V7K
0.1U_0402_25V6
10U_0603_6.3V6M
D D
1 1 1
CH18
CH19
CH20
2 2 2
UH1G LPT_PCH_M_EDS
PCH Power Rail Table
+1.05V_RUN P45
VCCADAC1_5
AA24 P43 +1.5V_RUN Voltage Rail Voltage S0 Iccmax Current (A)
AA26 VCC CRT DAC VSS
VCC
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 AD20 M31
VCC VCCADACBG3_3 +3.3V_RUN +1.05V_RUN
AD22 VCC 1.05V 1.138 A
VCC
CH21
CH22
CH23
CH24
AD24
VCC
1U_0402_6.3V6K
AD26 BB44
2 2 2 2 AD28 VCC VCCVRM
VCC FDI 1 VCCIO 1.05V 3.629 A
AE18 AN34
VCC VCCIO +3.3V_RUN
CH25
AE20
AE22 VCC AN35
VCC VCCIO 2
VCCADAC1_5 1.5V 0.070 A
AE24
AE26 VCC R30
VCC HVCMOS VCC3_3_R30
0.1U_0402_25V6
AG18 R32 VCCADAC3_3 3.3V 0.0133 A
AG20 VCC VCC3_3_R32
VCC 1
AG22 Y12 +3.3V_ALW_PCH
VCC DCPSUS1
CH27
AG24 VCCCLK 1.05V 0.306 A
Y26 VCC AJ30
VCC VCCSUS3_3 2
Core
AJ32
VCCSUS3_3
VCCCLK3_3 3.3V 0.055 A
+1.05V_M AJ26
C +PCH_VCCDSW U14 USB3 DCPSUS3 AJ28 C
AA18 DCPSUSBYP DCPSUS3 AK20
VCCASW VCCIO +1.05V_RUN VCCVRM 1.5V 0.183 A
U18 AK26
VCCASW VCCVRM
22U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
U20 AK28
VCCASW VCCVRM +1.5V_RUN
1 1 1 U22 VCC3_3 3.3V 0.133 A
U24 VCCASW BE22
CH28
CH29
CH30
V18 PCIe/DMI
V20 VCCASW AK18
2 2 2 VCCASW VCCIO +1.05V_RUN VCCASW 1.05V 0.67 A
V22
V24 VCCASW AN11
Y18 VCCSUSHDA 3.3V 0.01 A
Y20 VCCASW SATA AK22
Y22 VCCASW VCCIO +1.05V_RUN
VCCASW AM18
VCCIO VCCSPI 3.3V 0.022 A
AM20
VCCIO AM22
VCCMPHY VCCIO AP22
VCCIO VCCSUS3_3 3.3V 0.261 A
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
AR22 1 1 1 1 1
VCCIO AT22
VCCIO
CH34
CH35
CH36
CH37
CH38
VCCDSW3_3 3.3V 0.015 A
7 OF 11
2 2 2 2 2
DH82LPMS-QCG1-B0_FCBGA695~D V_PROC_IO 1.05V 0.004 A
1 2 +PCH_VCCDSW
RH232 5.11_0402_1%
+PCH_VCCDSW_R
B B
1U_0402_6.3V6K
1
CH40
A A
PROPRIETARY NOTE:
Title
1.0
5 4 3 2 1
5 4 3 2 1
Support DEEP SX: populated RH238, de-populated RH237
+3.3V_ALW_PCH
+PCH_VCCDSW3_3
0.1U_0402_25V6
2 1
UH1H LPT_PCH_M_EDS
0_0603_5% RH237 @
+3.3V_ALW_PCH
0.1U_0402_25V6
1 2 1 +3.3V_ALW
+3.3V_ALW_PCH
CH43
0_0603_5% RH238 @
1
CH44
R24 R20
R26 VCCSUS3_3 VCCSUS3_3 R22 2
D D
VCCSUS3_3 VCCSUS3_3
0.1U_0402_25V6
R28
+1.05V_RUN U26 VCCSUS3_3 GPIO/LPC 2
1 VCCSUS3_3 A16 +PCH_VCCDSW3_3
CH45 M24 VCCDSW3_3 +3.3V_RUN PCH Power Rail Table
VSS AA14 +PCH_VCCSST 1 2
2 +3.3V_RUN DCPSST
0.1U_0402_25V6
U35 CH46 0.1U_0402_25V6
VCCUSBPLL AE14
1 Voltage Rail Voltage S0 Iccmax Current (A)
USB
L24 VCC3_3 AF12
VCC3_3 VCC3_3
CH47
0.1U_0402_25V6
AG14
VCC3_3 +3.3V_ALW_PCH
0.1U_0402_25V6
U30 1 VCC 1.05V 1.138 A
2 +1.05V_RUN V28 VCCIO
1 VCCIO
CH48
CH49
V30 U36 +1.05V_RUN
Y30 VCCIO VCCIO
VCCIO 2
VCCIO 1.05V 3.629 A
2
0.1U_0402_25V6
+1.5V_RUN Y35 Azalia
DCPSUS2
1U_0402_6.3V6K
1 A26 1 VCCADAC1_5 1.5V 0.070 A
AF34 VCCSUSHDA
VCCVRM
CH50
CH51
+RTC_CELL
10U_0603_6.3V6M
1 +PCH_VCC AP45 K8 +3.3V_VCCPRTCSUS VCCADAC3_3 3.3V 0.0133 A
2 VCC VCCSUS3_3 2
CH52
+PCH_VCCCLK Y32 A6
VCCCLK VCCRTC
2 RTC
VCCCLK 1.05V 0.306 A
0.1U_0402_25V6
0.1U_0402_25V6
1U_0402_6.3V6K
+PCH_VCCCLK3_3 M29 P14 +PCH_DCPRTC CH54
VCCCLK3_3 DCPRTC P16 1 2
DCPRTC 1 1 1
L29 VCCCLK3_3 3.3V 0.055 A
VCCCLK3_3
CH55
CH56
CH57
0.1U_0402_25V6
L26 AJ12 +VCCIO2PCH
M26 VCCCLK3_3 V_PROC_IO AJ14 +3.3V_M 2 2 2
VCCCLK3_3
CPU
V_PROC_IO VCCVRM 1.5V 0.183 A
U32
VCCCLK3_3
1U_0402_6.3V6K
ICC
V32 AD12 VCC3_3 3.3V 0.133 A
VCCCLK3_3 SPI VCCSPI
+PCH_VCCCLK AD34 1
VCCCLK P18 +PCH_VCCCFUSE
C VCC VCCASW 1.05V 0.67 A C
CH59
AA30 P20
AA32 VCCCLK VCC
VCCCLK L17 2
VCCASW +1.05V_M VCCSUSHDA 3.3V 0.01 A
AD35
VCCCLK R18
AG30 VCCASW +VCCIO2PCH
VCCCLK VCCSPI 3.3V 0.022 A
AG32
VCCCLK AW40
VCCVRM +1.5V_RUN
AD36 VCCSUS3_3 3.3V 0.261 A
+1.05V_RUN VCCCLK +3.3V_RUN
0.1U_0402_25V6
0.1U_0402_25V6
1U_0402_6.3V6K
AK30
AE30 VCC3_3
Thermal 1 1 1
AE32 VCCCLK AK32
VCCCLK VCC3_3 VCCDSW3_3 3.3V 0.015 A
0.1U_0402_25V6
CH60
CH61
CH62
1 2 +PCH_VCC
@ RH246 0_0603_5% 1 2 2 2
10U_0603_6.3V6M
1U_0402_6.3V6K
8 OF 11
V_PROC_IO 1.05V 0.004 A
@ CH63
CH65
1 1 DH82LPMS-QCG1-B0_FCBGA695~D
CH64
2 2
Place near pin AP45
+PCH_VCCCFUSE 2 1 +3.3V_RUN
+1.05V_RUN +PCH_VCCCLK @ RH242 0_0805_5%
1U_0402_6.3V6K
1 2 1
@ RH244 0_0805_5%
1U_0402_6.3V6K
1U_0402_6.3V6K
CH66
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2
@ CH68
1 1 1 1 1
CH67
CH69
CH70
CH71
B B
2 2 2 2 2
Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36
Place near pin AG30,AG32,AE30,AE32
+3.3V_VCCPRTCSUS 2 1
+3.3V_RUN +3.3V_ALW_PCH
+PCH_VCCCLK3_3 @ RH240 0_0603_5%
2 1 +3.3V_ALW
1U_0402_6.3V6K
1 @ RH241 0_0603_5%
1 2
CH53
@ RH245 0_0805_5%
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1
CH72
CH73
CH74
CH75
2 2 2 2
Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32
A A
Title
1.0
5 4 3 2 1
5 4 3 2 1
D D
UH1J LPT_PCH_M_EDS
AL34 K39 UH1K LPT_PCH_M_EDS

AL38 VSS VSS L2
AL8 VSS VSS L44 AA16 B19
AM14 VSS VSS M17 AA20 VSS VSS B23
AM24 VSS VSS M22 AA22 VSS VSS B27
AM26 VSS VSS N12 AA28 VSS VSS B31
AM28 VSS VSS N35 AA4 VSS VSS B35
AM30 VSS VSS N39 AB12 VSS VSS B39
AM32 VSS VSS N6 AB34 VSS VSS B7
AM16 VSS VSS P22 AB38 VSS VSS BA40
AN36 VSS VSS P24 AB8 VSS VSS BD11
AN40 VSS VSS P26 AC2 VSS VSS BD15
AN42 VSS VSS P28 AC44 VSS VSS BD19
AN8 VSS VSS P30 AD14 VSS VSS AY36
AP13 VSS VSS P32 AD16 VSS VSS AT43
C AP24 VSS VSS R12 AD18 VSS VSS BD31 C
AP31 VSS VSS R14 AD30 VSS VSS BD35
AP43 VSS VSS R16 AD32 VSS VSS BD39
AR2 VSS VSS R2 AD40 VSS VSS BD7
AK16 VSS VSS R34 AD6 VSS VSS D25
AT10 VSS VSS R38 AD8 VSS VSS AV7
AT15 VSS VSS R44 AE16 VSS VSS F15
AT17 VSS VSS R8 AE28 VSS VSS F20
AT20 VSS VSS T43 AF38 VSS VSS F29
AT26 VSS VSS U10 AF8 VSS VSS F33
AT29 VSS VSS U16 AG16 VSS VSS BC16
AT36 VSS VSS U28 AG2 VSS VSS D4
AT38 VSS VSS U34 AG26 VSS VSS G2
D42 VSS VSS U38 AG28 VSS VSS G38
AV13 VSS VSS U42 AG44 VSS VSS G44
AV22 VSS VSS U6 AJ16 VSS VSS G8
AV24 VSS VSS V14 AJ18 VSS VSS H10
BB25 VSS VSS V43 AJ24 VSS VSS H22
AV40 VSS VSS W2 AJ34 VSS VSS H24
AV6 VSS VSS W44 AJ38 VSS VSS H26
AW2 VSS VSS Y14 AJ6 VSS VSS H31
F43 VSS VSS Y16 AJ8 VSS VSS H36
AY10 VSS VSS Y24 AK14 VSS VSS H40
AY15 VSS VSS Y28 AK24 VSS VSS H7
AY20 VSS VSS Y34 AK43 VSS VSS K10
AY26 VSS VSS Y36 AK45 VSS VSS K15
AY29 VSS VSS Y40 AL12 VSS VSS K20
AY7 VSS VSS Y8 AL2 VSS VSS K29
B11 VSS VSS BC22 VSS VSS K33
B15 VSS BB42 VSS VSS BC28
B VSS VSS VSS B
10 OF 11 11 OF 11
DH82LPMS-QCG1-B0_FCBGA695~D DH82LPMS-QCG1-B0_FCBGA695~D
A A
PROPRIETARY NOTE:
Title
1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW Q83B Battery LED

HDD LED solution for White LED DMN66D0LDW-7_SOT363-6
10K_0402_5%
+5V_ALW 4 3 BAT2_LED#_Q 1 2 BATT_WHITE# <47>
<45> BAT2_LED#
1
R949 1.8K_0402_5%
R932
BATT_YELLOW# <47>
5
MASK_BASE_LEDS#
3
Q74B
2
DMN66D0LDW-7_SOT363-6 Q74A
D59 DMN66D0LDW-7_SOT363-6
4 3 1 2 1 6 2
<15> SATA_ACT#
RB751V40_SC76-2 Q75 1 2 BATT_WHITE_LED# <28>
PDTA114EU_SC70-3 R958 680_0402_5%
2
<45> MASK_SATA_LED# BATT_YELLOW_LED# <28>
1
D D
D62 1 2
1 2 MASK_BASE_LEDS# R934 1.8K_0402_5% SATA_LED <47>
<45> LED_SATA_DIAG_OUT#
RB751V40_SC76-2 Q83A
1 6 BAT1_LED#_Q 1 2
<45> BAT1_LED#
R951 330_0402_5%
PANEL_HDD_LED <28>
2
MASK_BASE_LEDS#
3
Q84B
4 3 2
1 2
Q81 R953 330_0402_5%
PDTA114EU_SC70-3
1
1 2 Q84A LED1 +5V_ALW
SYS_LED_MASK# R938 680_0402_5% Breath LED DMN66D0LDW-7_SOT363-6
1 6 BREATH_LED#_Q 1 2 BREATH_WHITE_LED_SNIFF 1 2
<44,45> BREATH_LED#
R957 220_0402_5%
LTW-193ZDS5_WHITE
Place LED1 close to SW1
2
MASK_BASE_LEDS#
+3.3V_ALW
WLAN LED solution for White LED

100K_0402_5%
+5V_ALW
1
1 2 BREATH_WHITE_LED# <28>
R937
R955 680_0402_5%
3
Q100
L2N7002WT1G_SC-70-3
2
C C
S
D
3 1 2
<37,38,45> WIRELESS_LED#
PWR SW
POWER_SW#_MB 2 SW1 1
G
2
Q79 <35,46> POWER_SW#_MB

MASK_BASE_LEDS# PDTA114EU_SC70-3
1
4 3
SKRBAAE010_4P
1 2
R3671 1.8K_0402_5% WLAN_LED <47> POWER & INSTANT ON SWITCH
+3.3V_ALW
@ C778
1 2
POWER_SW#_MB
0.1U_0402_25V6
5
1
EMC@
VCC
SYS_LED_MASK# 1 C1558
<32,33,45> SYS_LED_MASK# IN B 0.047U_0402_25V7K
4 MASK_BASE_LEDS#
LID_CL# 2 OUT Y 2
GND
<45,47> LID_CL# IN A
U58
NL17SZ08DFT2G_SC70-5
3
Close C478
ESD Request
B B
LED Circuit Control Table

SYS_LED_MASK# LID_CL#
Mask All LEDs (Sniffer Function) 0 X

Mask Base MB LEDs (Lid Closed) 1 0
Do not Mask LEDs (Lid Opened) 1 1
@ H1 @ H2 @ H3 @ H4 @ H5 @ H6 @ H7 @ H8 @ H9 @ H10 @ H11 @ H12

H_3P8 H_3P8 H_3P3 H_3P0 H_3P3 H_3P3 H_3P0 H_3P0 H_3P3 H_3P0 H_3P0 H_3P0
1
@ H13 @ H14 @ H15 @ H16 @ H17 @ H18 @ H19 @ H20 @ H21 @ H22 @ H23
H_3P0 H_3P2 H_3P3 H_3P3 H_2P0N H_2P3 H_2P3 H_3P0 H_3P1X2P1N H_3P3 H_3P3
1
A
Fiducial Mark A
@ FD1 @ FD2 @ FD3 @ FD4

1 1 1 1
FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PWR SW/LED/PAD/ME
1.0
5 4 3 2 1
2 1
B
SW for MB/DOCK B
+5V_RUN +3.3V_RUN
U6
PCH_CRT_RED 1 16
<16> PCH_CRT_RED PCH_CRT_GRN 2 R 5V VDD
<16> PCH_CRT_GRN 5 G 4
PCH_CRT_BLU
<16> PCH_CRT_BLU PCH_CRT_HSYNC 6 B VDD 23
<16> PCH_CRT_HSYNC PCH_CRT_VSYNC 7 H_SOURCE VDD 32
<16> PCH_CRT_VSYNC PCH_CRT_DDC_DAT 9 V_HOURCE VDD
<16> PCH_CRT_DDC_DAT PCH_CRT_DDC_CLK 10 SDA_SOURCE 27 RED_CRT
<16> PCH_CRT_DDC_CLK SCL_SOURCE R1 25 RED_CRT <43>
GREEN_CRT
G1 22 BLUE_CRT GREEN_CRT <43>
CRT_SWITCH 30 B1 20 HSYNC_BUF BLUE_CRT <43>
<45> CRT_SWITCH SEL H1_OUT 18 VSYNC_BUF HSYNC_BUF <43>
V1_OUT 12 DAT_DDC2_CRT VSYNC_BUF <43>
29 SDA1 14 CLK_DDC2_CRT DAT_DDC2_CRT <43>
+3.3V_RUN TEST SCL1 CLK_DDC2_CRT <43>
1 2 8 26 RED_DOCK
+3.3V_RUN Reserved R2 RED_DOCK <44>
R61 4.7K_0402_5% 24 GREEN_DOCK
3 G2 21 BLUE_DOCK GREEN_DOCK <44>
11 GND B2 19 HSYNC_DOCK BLUE_DOCK <44>
28 GND H2_OUT 17 VSYNC_DOCK HSYNC_DOCK <44>
31 GND V2_OUT 13 DAT_DDC2_DOCK VSYNC_DOCK <44>
33 GND SDA2 15 CLK_DDC2_DOCK DAT_DDC2_DOCK <44>
GPAD SCL2 CLK_DDC2_DOCK <44>
TS3V713ELRTGR_TQFN32_6X3
+3.3V_RUN +5V_RUN
0.01U_0402_16V7K
0.01U_0402_16V7K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
SEL1/SEL2 Chanel Source
1 1 1 1 1 1
0 A=B1 MB @ @
C25
C26
C27
C28
C29
C30
1 A=B2 APR/SPR 2 2 2 2 2 2
A A
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT CRT SW
1.0
2 1
2 1
+1.5V_RUN
1
PAD-OPEN1x1m
@ PJP2
2
+3.3V_RUN
+1.5V_RUN_HDMI
0.01UF_0402_25V7K
0.1U_0402_25V6
0.01UF_0402_25V7K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1 1 1 1 1
C354
C355
C340
C344
C342
1 1
C31
C32
2 2 2 2 2 1 2
2 2 @ R62 0_0402_5%
EMC@ L1
TMDSE_RP_CLK# 1 2 TMDSE_CON_CLK#
1 2
11
37
12
40
20
31
19
U19 TMDSE_RP_CLK 4 3 TMDSE_CON_CLK
4 3
VDD33
VDD33
VDDRX
VDDRX
VDDTX
VDDTX
VDDTA
C349 2 1 0.1U_0402_25V6 TMDSE_CPU_P2_C 6 CMMI21T-900Y-N_0805_4P
<9> TMDSB_CPU_P2 IN_D0p
1.8P_0402_50V8
1.8P_0402_50V8
C348 2 1 0.1U_0402_25V6 TMDSE_CPU_N2_C 7 1 @ 1 @
<9> TMDSB_CPU_N2 2 1 4 IN_D0n 1 2
C347 0.1U_0402_25V6 TMDSE_CPU_P1_C
<9> TMDSB_CPU_P1 IN_D1p
CE7
CE5
C346 2 1 0.1U_0402_25V6 TMDSE_CPU_N1_C 5 @ R63 0_0402_5%
<9> TMDSB_CPU_N1 2 1 1 IN_D1n
C351 0.1U_0402_25V6 TMDSE_CPU_P0_C
<9> TMDSB_CPU_P0 2 1 2 IN_D2p 2 2
C350 0.1U_0402_25V6 TMDSE_CPU_N0_C
<9> TMDSB_CPU_N0 2 1 9 IN_D2n
C352 0.1U_0402_25V6 TMDSE_CPU_CLK_C
<9> TMDSB_CPU_CLK 2 1 IN_CKp
B C353 0.1U_0402_25V6 TMDSE_CPU_CLK#_C 10 1 2 B
<9> TMDSB_CPU_CLK# IN_CKn 25 TMDSE_RP_P2 @ R64 0_0402_5%
36 OUT_D0p 24 TMDSE_RP_N2
PD# OUT_D0n 27 TMDSE_RP_P1 EMC@ L2
8 OUT_D1p 26 TMDSE_RP_N1 TMDSE_RP_P0 4 3 TMDSE_CON_P0
I2C_CTL_EN OUT_D1n 30 TMDSE_RP_P0 4 3
OUT_D2p 29 TMDSE_RP_N0
@ R65 1 2 4.7K_0402_5% 13 OUT_D2n 22 TMDSE_RP_CLK TMDSE_RP_N0 1 2 TMDSE_CON_N0
+3.3V_RUN DCIN_EN/SCL_CTL OUT_CKp 1 2
HDMI_BUF 14 21 TMDSE_RP_CLK#
DDCBUF/SDA_CTL OUT_CKn +VDISPLAY_VCC CMMI21T-900Y-N_0805_4P
1.8P_0402_50V8
1.8P_0402_50V8
HDMI_ISET 34 1 @ 1 @
ISET 1 2
CE17
CE16
@ R68 0_0402_5%
PCH_DDPB_CTRLCLK 38 32 HDMI_SCL_SINK 1.5K_0402_5% 2 1 R69
<16> PCH_DDPB_CTRLCLK 39 SCL_SRC SCL_SNK 33 2 1 R70 2 2
PCH_DDPB_CTRLDATA HDMI_SDA_SINK 1.5K_0402_5%
<16> PCH_DDPB_CTRLDATA SDA_SRC SDA_SNK 1 2
@ R71 0_0402_5%
R72 1 2 4.7K_0402_5% 23
+3.3V_RUN CFG 28 HDMI_HPD_SINK EMC@ L3
HPD_SNK TMDSE_RP_P1 4 3 TMDSE_CON_P1
HDMI_EQ 17 4 3
HDMI_PRE 16 EQ//I2C_ADDR0
PRE/I2C_ADDR1 TMDSE_RP_N1 1 2 TMDSE_CON_N1
+3.3V_RUN 1 2
HDMIB_PCH_HPD 3 CMMI21T-900Y-N_0805_4P
<16> HDMIB_PCH_HPD HPD_SRC
1.8P_0402_50V8
1.8P_0402_50V8
HDMI_CEC 2 1 1 @ 1 @
10K_0402_5% R73 1 2
GND PAD
CE13
CE18
18 @ R74 0_0402_5%
REXT HDMIB_PCH_HPD 1 2
GND
GND
2 2
4.99K_0402_1%
100K_0402_5% R75
1
1 2
R76
PS8401ATQFN40GTR2-A4_TQFN40_5X5 @ R77 0_0402_5%
15
35
41
EMC@ L4
TMDSE_RP_P2 4 3 TMDSE_CON_P2
4 3
2
TMDSE_RP_N2 1 2 TMDSE_CON_N2
1 2
CMMI21T-900Y-N_0805_4P
1.8P_0402_50V8
1.8P_0402_50V8
1 @ 1 @
+3.3V_RUN +3.3V_RUN 1 2
CE15
CE14
@ R78 0_0402_5%
2 2
1
1
4.7K_0402_5%
4.7K_0402_5%
@ R79
@ R80
2
HDMI_BUF HDMI_EQ +5V_RUN
+VDISPLAY_VCC
1
1
4.7K_0402_5%
4.7K_0402_5%
@ R81
@ R82
0.1U_0402_25V6
10U_0603_6.3V6M
IN
2
EMC@ U89 1 1
@ C46
C47
AP2330W-7_SC59-3
2 2
GND
OUT
Receiver equalization setting; Internal pull down at ~150kΩ, 3.3V I/O.
Enable active DDC buffer; Internal pull up at 150KΩ±20%, 3.3V I/O
3
L: programmable EQ for channel loss up to 12.4dB JHDMI1
L: default, passive DDC pass-through H: programmable EQ for channel loss up to 4.3dB HDMI_HPD_SINK 19
18 HP_DET
H: active DDC buffer with default threshold M: programmable EQ for channel loss up to 8.6dB 17 +5V
M: active DDC buffer without internal pull up resistor HDMI_SDA_SINK 16 DDC/CEC_GND
HDMI_SCL_SINK 15 SDA
+3.3V_RUN 14 SCL
A +3.3V_RUN HDMI_CEC 13 Reserved A
TMDSE_CON_CLK# 12 CEC 20
11 CK- GND 21
CK_shield GND
1
4.7K_0402_5%
TMDSE_CON_CLK 10 22
CK+ GND
1
4.7K_0402_5%
TMDSE_CON_N0 9 23
D0- GND
@ R85
R86
8
TMDSE_CON_P0 7 D0_shield
TMDSE_CON_N1 6 D0+
2
5 D1-
2
HDMI_PRE TMDSE_CON_N2 3 D1+
HDMI_ISET 2 D2-
D2+
1
4.7K_0402_5%
1
4.7K_0402_5%
@ R88
CONCR_099ATAC19NBLCNF
@ R87
CONN@
2
2
TMDS output swing adjustment; Internal pull down at ~150kΩ, 3.3V I/O. Output pre-emphasis setting; Internal pull down at ~150kΩ, 3.3V I/O. DELL CONFIDENTIAL/PROPRIETARY
L: default L: no pre-emphasis
H: increase +13% H: 1.6dB pre-emphasis
PROPRIETARY NOTE:
M: reduce -13% M: 2.5dB pre-emphasis THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT HDMI CONN
1.0
2 1
5 4 3 2 1
D D
C C
B B
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-9934P
5 4 3 2 1
5 4 3 2 1
LCD Power
JEDP1 CONN@ +LCDVDD
+5V_ALW for panel side LED power
1 +3.3V_ALW
1 +5V_ALW
2 Change netname : LCD_ENVDD_CVT to ENVDD_PCH 5/6 @ C455
2 3 BATT_WHITE_LED# <24>
10U_0603_6.3V6M U148
3 4 BATT_YELLOW_LED# <24> 1 2 1
4 5 BREATH_WHITE_LED# <24> VOUT 5
5 6 PANEL_HDD_LED <24> VIN
6 7 D7 2
7 8 DMIC0 <30> GND 4
8 9 2 SS
D 9 DMIC_CLK <30> <16,45> ENVDD_PCH D
10 1 3
10 EN
100P_0402_50V8J
100P_0402_50V8J
11
11 +CAMERA_VDD
12 USBP12_D- 1 1 3 APL3512ABI-TRG_SOT23-5
12 <45> LCD_VCC_TEST_EN
@ C1206
@ C1207
100K_0402_5%
13 USBP12_D+
13
1
14
14 15 CAM_MIC_CBL_DET# <16>
BAT54CW_SOT323-3
15 2 2
R3737
16 PIN15: LOOP_BACK
16 17
17 +BL_PWR_SRC
18 1 2
2
18 19 @ C246 0.1U_0603_50V7K
19 20
20 21 EMC@ LV1 1 2 BIA_PWM
21 22 DISP_ON BLM15BB221SN1D_2P~D
22 23
23 24
24 25
25 26
26 27 CPU_EDP_HPD <9>
27 28
28 29
29 30 LCD_TST <45>
30 31
31 +LCDVDD
32
32 33 EDP_CPU_AUX#_C C105 1 2 0.1U_0402_25V6
33 34 1 2 EDP_CPU_AUX# <9>
EDP_CPU_AUX_C C104 0.1U_0402_25V6
46 34 35 1 2 EDP_CPU_AUX <9>
EDP_CPU_LANE_P0_C C100 0.1U_0402_25V6
45 G6 35 36 1 2 EDP_CPU_LANE_P0 <9>
EDP_CPU_LANE_N0_C C101 0.1U_0402_25V6
44 G5 36 37 1 2 EDP_CPU_LANE_N0 <9>
EDP_CPU_LANE_P1_C C103 0.1U_0402_25V6
43 G4 37 38 1 2 EDP_CPU_LANE_P1 <9>
EDP_CPU_LANE_N1_C C118 0.1U_0402_25V6
42 G3 38 39 EDP_CPU_LANE_N1 <9>
41 G2 39 40
G1 40 LCD_CBL_DET# <16>
ACES_59003-04006-001
C FDC654P: P CHANNAL C
LCD Backlight +PWR_SRC

Q21
FDC654P-G_SSOT-6 +BL_PWR_SRC
D9 6
0.1U_0603_50V7K
4 5
S
1
2 2
BIA_PWM_PCH <16>
1000P_0402_50V7K
C296
BIA_PWM 1 1
100K_0402_5%
G
1
1
2
10K_0402_5%
3
3
BIA_PWM_EC <46>
C297
+LCDVDD +BL_PWR_SRC +CAMERA_VDD R1137
R422
BAT54CW_SOT323-3 2
0.1U_0402_25V6
0.1U_0603_50V7K
0.1U_0603_50V7K
2
1 1
2
@ C298
@ C247
@ C248
1
PWR_SRC_ON
2 2 Q22
2 L2N7002WT1G_SC-70-3
1 2 1 3
S
Close to JLVDS1.24~27 Close to JLVDS1.11,12 Close to JLVDS1.33 R423 47K_0402_5%
D10
G
2
2
1 PANEL_BKEN_PCH <16>
DISP_ON
<46> EN_INVPWR
100K_0402_5%
3 Panel backlight power control by EC

PANEL_BKEN_EC <45>
1
R1138
BAT54CW_SOT323-3
2
B B
Remove Touch Screen
For Webcam
1 2
@ R427 0_0402_5%
DLW21HN900SQ2L_0805_4P
USBP12+ 4 3 USBP12_D+
<19> USBP12+ 4 3
USBP12- 1 2 USBP12_D-
<19> USBP12- 1 2
EMC@ L10
1 2
@ R428 0_0402_5%
Webcam PWR CTRL

+CAMERA_VDD Q23 +3.3V_RUN
A A
DMG2301U-7_SOT23-3
1 3
D
S
0.1U_0402_25V6
10U_0603_6.3V6M
0.1U_0402_25V6
G
2
@ C300
1 1 1
C299
C301
<45> CCD_OFF
2 2 2
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT LVDS/CAM/TS
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Date: Friday, May 09, 2014 Sheet 28 of 71
5 4 3 2 1
5 4 3 2 1
AUX/DDC GPU for DPC to E-DOCK

+3.3V_RUN
C356
1 2
D 0.1U_0402_25V6 D
U20
1 14
2 1 DPC_PCH_DOCK_AUX_C 2 BE0 VCC 13
<16> DPC_PCH_DOCK_AUX A0 BE3
C357 0.1U_0402_25V6
3 12 PCH_DDPC_CTRLCLK
<44> DPC_DOCK_AUX B0 A3 PCH_DDPC_CTRLCLK <16>
4 11
2 1 DPC_PCH_DOCK_AUX#_C 5 BE1 B3 10
<16> DPC_PCH_DOCK_AUX# A1 BE2
C360 0.1U_0402_25V6
6 9 PCH_DDPC_CTRLDATA
<44> DPC_DOCK_AUX# B1 A2 PCH_DDPC_CTRLDATA <16>
7 8
GND B2
PI3C3125LEX_TSSOP14
+3.3V_RUN
10K_0402_5%
1
R415
Vinafix
2
DPC_CA_DET#
6
C C
Q331A
DPC_CA_DET 2 DMN66D0LDW-7_SOT363-6
+3.3V_RUN <44> DPC_CA_DET
1
RP1
+5V_RUN
1 8 PCH_DDPC_CTRLCLK C365 @
2 7 PCH_DDPC_CTRLDATA 1 2
3 6 PCH_DDPD_CTRLCLK
4 5 PCH_DDPD_CTRLDATA 0.1U_0402_25V6
1
2.2K_8P4R_5%
NC
2 4
A Y
G
U21 @
TC7SET04FU_SSOP5~D
3
+3.3V_RUN
R491
1
1
2
2
DPD_CA_DET
1M_0402_5%
DPC_CA_DET
AUX/DDC GPU for DPD to E-DOCK 1
C366
2
R492 1M_0402_5% 0.1U_0402_25V6
U23
1 14
2 1 DPD_PCH_DOCK_AUX_C 2 BE0 VCC 13
<16> DPD_PCH_DOCK_AUX A0 BE3
C367 0.1U_0402_25V6
B 3 12 PCH_DDPD_CTRLCLK B
<44> DPD_DOCK_AUX B0 A3 PCH_DDPD_CTRLCLK <16>
4 11
2 1 DPD_PCH_DOCK_AUX#_C 5 BE1 B3 10
<16> DPD_PCH_DOCK_AUX# A1 BE2
C368 0.1U_0402_25V6
6 9 PCH_DDPD_CTRLDATA
<44> DPD_DOCK_AUX# B1 A2 PCH_DDPD_CTRLDATA <16>
7 8
GND B2
PI3C3125LEX_TSSOP14
+3.3V_RUN
10K_0402_5%
1
R416
2
DPD_CA_DET#
3
Q331B
DPD_CA_DET 5 DMN66D0LDW-7_SOT363-6
<44> DPD_CA_DET
+5V_RUN
4
C369 @
1 2
A A
0.1U_0402_25V6
5
1
P
NC
2 4
A Y U24 @ DELL CONFIDENTIAL/PROPRIETARY
G
TC7SET04FU_SSOP5~D
3
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DP SW
1.0
5 4 3 2 1
2 1
INT_SPK_L+, INT_SPKL_L+ :40 mils trace, keep 10mils spacing

Internal Speakers Header INT_SPK_L-, INT_SPKL_L- :40 mils trace, keep 10mils spacing
INT_SPK_R+, INT_SPKR_R+ :40 mils trace, keep 10mils spacing
INT_SPK_R-, INT_SPKR_R- :40 mils trace, keep 10mils spacing place close to pin27
L77
INT_SPK_L-, INT_SPKL_L- with INT_SPK_R+, INT_SPKR_R+
JSPK1 CONN@ keep 20mils spacing +VDDA_AVDD 1 2 +5V_RUN
+5V_RUN
10U_0603_6.3V6M
INT_SPK_L+ EMC@ L702 1 2 BLM18PG330SN1D_2P INT_SPKL_L+ 1 BLM15PX600SN1D_2P
1
0.1U_0402_25V6
INT_SPK_L- EMC@ L703 1 2 BLM18PG330SN1D_2P INT_SPKL_L- 2
2
1
INT_SPK_R+ EMC@ L704 1 2 BLM18PG330SN1D_2P INT_SPKR_R+ 3 5 +3.3V_RUN +3.3V_RUN_DVDD 1 C968, C956 place close to pin38
1
3 G1
C955
INT_SPK_R- EMC@ L705 1 2 BLM18PG330SN1D_2P INT_SPKR_R- 4 6 +DVDD_CORE 1 2 +3.3V_RUN R1095 @
4 G2
C957
10U_0603_6.3V6M
@ PJP60 @ R1658 0_0603_5% 0_0805_5%
10U_0603_6.3V6M
0.1U_0402_25V6
ACES_50273-0040N-001 1 2
2
1 2 2
1
2
1
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
1U_0603_10V7K
0.1U_0402_25V6
C956
JUMP_43X79 1 C959, C958 place close to pin39
C954
C968
C952
C994
0.1U_0402_25V6
10U_0805_10V6K
0.1U_0402_25V6
10U_0805_10V6K
2
2
@ C973
@ C974
@ C975
@ C976
1 1 1 1 1 1
1
2
C958
C960
U74
C959
C961
1 27
DREG_OUT AVDD1 38 +VDDA_AVDD2
2
2 2 2 2 AVDD2/HVDD(3.3) 2 2
3 45 +VDDA_PVDD C961, C960 place close to pin45
DVDD-IO PVDD2 39 +VREFOUT
PVDD1
9 13 AUD_SENSE_A
DVDD Sense A 14 AUD_SENSE_B SLEEVE R1145 1 2 2.2K_0402_5%
Sense B
28 RING2 SLEEVE and RING2 Routing 40 mils. RING2 R1146 1 2 2.2K_0402_5%
PCH_AZ_CODEC_BITCLK 6 LINE1-L/RING2 29 SLEEVE
<15> PCH_AZ_CODEC_BITCLK BIT-CLK LINE1-R/SLEEVE 23 +VREFOUT +VREFOUT
PCH_AZ_CODEC_SDOUT 5 LINE1-VREFO
<15> PCH_AZ_CODEC_SDOUT SDATA-OUT 31 C969 1 2 10U_0603_6.3V6M
10 HPOUT-L/MIC-CAP 33 AUD_HP_OUT_L
<15> PCH_AZ_CODEC_SYNC SYNC AVSS2/HPOUT-L
Place R1096 close to codec 32 AUD_HP_OUT_R
B 1 2 PCH_AZ_SDIN0_R 8 HP-OUT-R B
<15> PCH_AZ_CODEC_SDIN0 R1096 22_0402_5% SDATA-IN 40 INT_SPK_L+
PCH_AZ_CODEC_RST# 11 SPK-L+ 41 INT_SPK_L-
<15> PCH_AZ_CODEC_RST# RESET# SPK-L-
44 INT_SPK_R+ 2 1 1 2
SPK-R+ 43 SPKR <15>
INT_SPK_R- C1105 0.1U_0402_25V6 R1119 100K_0402_5%
DAI_12MHZ# 1 2 I2S_MCLK 15 SPK-R- 2 1 1 2
<44> DAI_12MHZ# I2S_MCLK BEEP <46>
R1654 22_0402_5% 12 AUD_PC_BEEP C1106 0.1U_0402_25V6 R1120 100K_0402_5%
DAI_BCLK# 1 2 I2S_BCLK 16 PCBEEP
<44> DAI_BCLK# R1668 22_0402_5% I2S_SCLK 2 DMIC_CLK_L 1 2 1 2
DAI_DO# 1 2 I2S_DO 17 GPIO0/DMIC-CLK 4 EMC@ L13 BLM15BB221SN1D_0402 DMIC_CLK <28> @ R1141 10K_0402_5%
<44> DAI_DO# I2S_DOUT GPIO1/DMIC-DATA DMIC0 <28>
R1097 33_0402_5% 46 Place L13 close to codec 1 2
DAI_LRCK# 18 DMIC1/GPIO2 48 @ R1142 10K_0402_5%
SLEEVE <44> DAI_LRCK# I2S_LRCK GPIO3
DAI_DI 24 37 1 EN_I2S_NB_CODEC#
<44> DAI_DI I2S_DIN MONO-OUT/CBP EN_I2S_NB_CODEC# <45>
C962
+RTC_CELL 2.2U_0603_16V6K
19 35 2
MIC1-L CBN SPKR
BCLK: Audio serial data bus bit clock input/output
LRCK: Audio serial data bus word clock 20
MIC1-R
100K_0402_5%
input/output 1
36 EMC@
CBP/AVSS2
1
AUD_NB_MUTE# 47 C1559
<45> AUD_NB_MUTE# EAPD/PD
R1703
21 +ALC3226_LDO_CAP 0.047U_0402_25V7K
LDO-CAP 2
1U_0603_10V6K
+3.3V_RUN 1 2 22
JDREF
3
Q330B R1099 10K_0402_5% 1 7 34 +ALC3226_CPVEE

DVSS CPVEE 25 +ALC3226_VREF
2
VREF
C967 @
10U_0603_6.3V6M
42
PVSS
1
0.1U_0402_25V6
2.2U_0603_16V6K
2.2U_0603_16V6K
20K_0402_1%
5 2 1 PCH_AZ_CODEC_RST# 30 close R1119
1
ESD Request
2
2 49 MIC1-VREFO 26
C1107
C1214
GND AVSS1
C965
R1642
C963
R39 @
4
Q330A 0_0402_5% ALC3226-CG_QFN48_7X7
1
2
2
2 2 1 AUD_NB_MUTE#
R40 @
1
0_0402_5% place at Codec bottom side

@ PJP62
1 2
Close to U74 pin6
PAD-OPEN1x1m
PCH_AZ_CODEC_BITCLK
1
@ R1076 place at AGND and DGND plane

33_0402_5%
1 2
1 2
Place closely to Pin 13. R5 @

@ C977 0_0402_5%
100P_0402_50V8J 1 2
2
AUD_SENSE_A
R6 @
0_0402_5% +3.3V_RUN
1
39.2K_0402_1%
1 2
Combo Jack
R1086
10K_0402_5%
R15 @
1
0_0402_5%
2
R1100
Normal
L2N7002WT1G_SC-70-3
D Open
2
2 AUD_HP_NB_SENSE
10U_0603_6.3V6M
G JHP1
0.1U_0402_25V6
S Q324 SLEEVE @ R3731 1 2 0_0402_5% EXT_MIC 4

3
@ C1247
1 1 RING2 @ R3732 1 2 0_0402_5% RING2_L 3

AUD_HP_OUT_R 2 1 AUD_HP_OUT_R1 EMC@ L706 1 2 BLM15BD601SN1D_2P AUD_HP_OUT_R2 2
C972
base E-team detect issue , AUD_HP_OUT_L R1679 2 19.1_0402_1% AUD_HP_OUT_L1 EMC@ L707 1 2 BLM15BD601SN1D_2P AUD_HP_OUT_L2 1
R1677 9.1_0402_1%
A 2 2 reserve RC to delay time 5 A
G 7
6 G
8
SINGA_2SJ3082-000111F
EXT_MIC CONN@
Add for solve pop noise and detect issue
0_0402_5%
EMC@
C1556
100P_0402_50V8J
2
L03ESDL5V0CC3-2_SOT23-3
L03ESDL5V0CC3-2_SOT23-3
AUD_HP_NB_SENSE
AUD_HP_NB_SENSE <45>
EMC@ D82
EMC@ D81
Notes:
1
Place closely to Pin 14 AUD_SENSE_B Keep PVDD supply and speaker traces routed on the DGND plane. RING2_L
Keep away from AGND and other analog signals
@ R1676
1
1
EMC@
2
1
+3.3V_RUN C1557 R1088

+3.3V_RUN
Resistor SENSE_A SENSE_B
R1079 R1080 100P_0402_50V8J 100K_0402_5%
2
1
39.2K_0402_1% 20K_0402_1%
1
39.2K PORT A PORT E For EMC request
2
1
R1081
2
100K_0402_5%
R1082 20K PORT B PORT F PORT A External MIC
100K_0402_5%
2
10K NA DMIC0 PORT B HeadPhone Out

2 5 PROPRIETARY NOTE:
<45> DOCK_HP_DET DOCK_MIC_DET <45> Title
5.11K SPDIFOUT0 SPDIFOUT1 (DMIC1) PORT C Dock Audio THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Q106A Q106B
Codec
1
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
2.49K Pull-up to AVDD PORT D Internal SPK BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
1.0
2 1
5 4 3 2 1
D D
HDD PWR
+5V_HDD +5V_RUN
@ PJP3
1 2
1 2
JUMP_43X79
SHORT DEFAULT
@ PJP53
+3.3V_RUN
1 2 +3.3V_RUN_FFS
Free Fall Sensor
10U_0603_6.3V6M
0.1U_0402_25V6
PAD-OPEN1x1m
1 1
U88
C387
C388
LNG3DM 10
2 2 1
14 VDD_IO
VDD
RES
RES
RES
13
15
16
HDD CONN
JSATA1
11 RES 1
<16> HDD_FALL_INT FFS_INT2 9 INT 1 5 C383 2 1 0.01U_0402_16V7K SATA_PTX_DRX_P0 2 GND
INT 2 GND 12 <15> PSATA_PTX_DRX_P0_C RX+
C384 2 1 0.01U_0402_16V7K SATA_PTX_DRX_N0 3
7 GND <15> PSATA_PTX_DRX_N0_C 4 RX-
6 SDO/SA0 C385 2 1 0.01U_0402_16V7K SATA_PRX_DTX_N0 5 GND
<13,14,15,18> DDR_XDP_WAN_SMBDAT 4 SDA / SDI / SDO <15> PSATA_PRX_DTX_N0_C TX-
C386 2 1 0.01U_0402_16V7K SATA_PRX_DTX_P0 6
<13,14,15,18> DDR_XDP_WAN_SMBCLK SCL/SPC 2 <15> PSATA_PRX_DTX_P0_C 7 TX+
8 NC 3 @ PJP64 GND
CS NC 1 2 +3.3V_RUN_HDD 8
C +3.3V_RUN 3.3V C
LNG3DMTR_LGA16_3X3 9
PAD-OPEN1x1m 1 2 +3.3V_RUN_HDD_R 10 3.3V
@ R1635 0_0402_5% 11 3.3V
12 GND
<15,17> HDD_DET# 13 GND
14 GND
+5V_HDD 5V
15
16 5V
+5V_HDD 17 5V
FFS_INT2_Q 18 GND 23
Reserved GND1
100K_0402_5%
19 24
GND GND2
1
20
12V
@ R506
21
+3.3V_RUN +5V_HDD +3.3V_RUN_HDD 22 12V
+3.3V_RUN 12V
100K_0402_5%
CONN@
2
1
1000P_0402_50V7K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
SANTA_196003-1
R508
1 2 DDR_XDP_WAN_SMBDAT
R501 10K_0402_5% FFS_INT2_Q 1 1 1 1
C395
C396
C402
C399
1 2 DDR_XDP_WAN_SMBCLK
3
R502 10K_0402_5% Main SATA +5V Default
2
1 2 HDD_FALL_INT
2 2 2 2
Q29B
R503 100K_0402_5%
5
6
4
Q29A
FFS_INT2 2
<20> FFS_INT2
Place near HDD CONN
1
B B
A A
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT HDD
1.0
5 4 3 2 1
5 4 3 2 1
+5V_MOD/+5V_RUN source
D D
+5V_MOD +5V_RUN
@ PJP4
1 2
1 2
JUMP_43X79
+5V_ALW
U37
1 14 1 2
2 1 2 VIN1 VOUT1 13 @ C765 10U_0603_6.3V6M
100K_0402_5% R512 VIN1 VOUT1
+3.3V_ALW2 3 12 1 2
<45> MODC_EN ON1 CT1 C438 470P_0402_50V7K
4 11
VBIAS GND
1
R517 5 10 1 2
<39,45,48,60> RUN_ON ON2 CT2
100K_0402_5% C436 470P_0402_50V7K
6 9
7 VIN2 VOUT2 8
+5V_RUN
2
VIN2 VOUT2
1
10U_0603_6.3V6M
MODC_EN# 15
GPAD
@ C764
6
TPS22966DPUR_SON14_2X3
2
Q76A
MODC_EN 2
1
C C
ODD CONN
JSATA2
1
C407 2 1 0.01U_0402_16V7K SATA_ODD_PTX_DRX_P1 2 GND
<15> SATA_ODD_PTX_DRX_P1_C A+
C406 2 1 0.01U_0402_16V7K SATA_ODD_PTX_DRX_N1 3
<15> SATA_ODD_PTX_DRX_N1_C 4 A-
C405 2 1 0.01U_0402_16V7K SATA_ODD_PRX_DTX_N1 5 GND
<15> SATA_ODD_PRX_DTX_N1_C C404 2 1 0.01U_0402_16V7K SATA_ODD_PRX_DTX_P1 6 B-
<15> SATA_ODD_PRX_DTX_P1_C 7 B+
GND
8
<46> DEVICE_DET# 9 DP
+5V_MOD +5V
10
Q76B MOD_MD 11 +5V
DMN66D0LDW-7_SOT363-6 12 MD
MOD_MD 4 3 ZODD_WAKE# 13 GND
ZODD_WAKE# <45> GND
14
15 GND
5
MODC_EN# <17> CLK_PCIE_EMB 16 REFCLK+

<17> CLK_PCIE_EMB# 17 REFCLK-
B 18 GND B
<19> PCIE_PRX_EMBTX_P4 19 PETX+
<19> PCIE_PRX_EMBTX_N4 20 PETX-
Q123B
DMN66D0LDW-7_SOT363-6 21 GND
4 3 USB30_SMI# 0.1U_0402_25V6 2 1 C409 PCIE_PTX_EMBRX_P4_C 22 GND
USB30_SMI# <15,45> <19> PCIE_PTX_EMBRX_P4 2 1 C408 PCIE_PTX_EMBRX_N4_C 23 PERX+
0.1U_0402_25V6
<19> PCIE_PTX_EMBRX_N4 24 PERX-
GND
5
USB30_EN 25
+5V_MOD +5V
26
<17> EMBCLK_REQ# 27 CLKREQ#
+3.3V_ALW_PCH <36,37,38,39,46> PCIE_WAKE# 28 WAKE#
<16> PLTRST_EMB# 29 PERST# 32
<46> BAY_SMBDAT 30 SMB_DATA GND1 33
RP18
1 8 <46> BAY_SMBCLK 31 SMB_CLK GND2
ZODD_WAKE#
2 7 <45> MOD_SATA_PCIE#_DET HPD
MOD_MD +3.3V_ALW
3 6 MOD_SATA_PCIE#_DET
+3.3V_ALW
100K_0402_5%
4 5 SYS_LED_MASK# TYCO_2-2129116-3
SYS_LED_MASK# <24,33,45>
1
CONN@
10K_8P4R_5%
R515
+5V_MOD
2
1000P_0402_50V7K
0.1U_0402_25V6
USB30_EN
1 1
C397
C398
6
2 2
Q123A
MOD_SATA_PCIE#_DET 2
A A
1
Place near ODD CONN DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT ODD
1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_LAN
1 2 TP_LAN_JTAG_TMS
@ R545 10K_0402_5%
1 2 TP_LAN_JTAG_TCK
@ R546 10K_0402_5% +0.9V_LAN
U31
1 2 LANCLK_REQ#_R 48 13 LAN_TX0+ REGCTL_PNP10 1 2

<15,17> LANCLK_REQ# @ R1187 0_0402_5% 36 CLK_REQ_N MDI_PLUS0 14 LAN_TX0- 4.7UH_CBC2012T4R7M_20% L29
+3.3V_LAN <16> PLTRST_LAN# PE_RST_N MDI_MINUS0
10U_0603_6.3V6M
0.1U_0402_25V6
CLK_PCIE_LAN 44 17 LAN_TX1+ 1 1
<17> CLK_PCIE_LAN PE_CLKP MDI_PLUS1
C462
C463
1 2 LANWAKE# CLK_PCIE_LAN# 45 18 LAN_TX1-
<17> CLK_PCIE_LAN#
PCIE
PE_CLKN MDI_MINUS1
MDI
@ R558 4.7K_0402_5% 2 1 PCIE_PRX_GLANTX_P2_C
<19> PCIE_PRX_GLANTX_P2
D C458 0.1U_0402_25V6 38 20 LAN_TX2+ D
+PCH_VCCDSW3_3 Support Deep S3 mode 2 1 PCIE_PRX_GLANTX_N2_C 39 PETp MDI_PLUS2 21 LAN_TX2- 2 2
<19> PCIE_PRX_GLANTX_N2 PETn MDI_MINUS2 Place R548, C462, C463 and L29 close to U31
C459 0.1U_0402_25V6
2 1 LANWAKE# +3.3V_LAN 1 2 PCIE_PTX_GLANRX_P2_C 41 23 LAN_TX3+
<19> PCIE_PTX_GLANRX_P2 PERp MDI_PLUS3
@ R566 10K_0402_5% C460 0.1U_0402_25V6 42 24 LAN_TX3-
PERn MDI_MINUS3
10K_0402_5%
1 2 PCIE_PTX_GLANRX_N2_C Pin 6 is SVR_EN in Clarkville
<19> PCIE_PTX_GLANRX_N2
1
@ R549
C461 0.1U_0402_25V6
1 2 LAN_SMBCLK_R 28 6 VCT_LAN_R1 @ R152 2 1 0_0402_5%
<18> LAN_SMBCLK
SMBUS
@ R551 0_0402_5% 31 SMB_CLK SVR_EN_N +0.9V_LAN +3.3V_LAN_OUT
1 2 LAN_SMBDATA_R SMB_DATA 1 +RSVD_VCC3P3_1 R553 2 1 4.7K_0402_5%
<18> LAN_SMBDATA RSVD_VCC3P3_1 +3.3V_LAN
@ R552 0_0402_5%
2
LANWAKE# 2 5
<20,46> LANWAKE# LANWAKE_N VDD3P3_IN
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
22U_0805_6.3V6M
22U_0805_6.3V6M
1 2 LAN_DISABLE#_R 3
<17,20> PM_LANPHY_ENABLE LAN_DISABLE_N
@ R555 0_0402_5% SMBus Device Address 0xC8 4 +3.3V_LAN_OUT @ R154 2 1 0_0603_5% +3.3V_LAN 1 1 1 1 1 1
VDD3P3_4
C1177
C1178
<45> LAN_DISABLE#_R
10K_0402_5%
1U_0603_10V6K
C466
C467
C468
C469
15 1
VDD3P3_15
1
@ R557
LOM_ACTLED_YEL# 26 19
LED0 VDD3P3_19 2 2 2 2 2 2
C464
LOM_SPD100LED_ORG# 27 29
LED1 VDD3P3_29
LED
LOM_SPD10LED_GRN# 25 +0.9V_LAN
LED2 2
47
2
VDD0P9_47 46
@ T142 PAD~D TP_LAN_JTAG_TDI 32 VDD0P9_46 37
JTAG_TDI VDD0P9_37 Note:
@ T143 PAD~D TP_LAN_JTAG_TDO 34 Place C1178 close to pin5
JTAG_TDO +1.0V_LAN will work at 0.95V to 1.15V
JTAG
TP_LAN_JTAG_TMS 33 43 Pin 2 is WAKE_EN in Clarkville
TP_LAN_JTAG_TCK 35 JTAG_TMS VDD0P9_43
JTAG_TCK 11
VDD0P9_11
@ R1144 1 2 0_0402_5% XTALO 9 40 0.9Vdc POWER OPTIONS
XTALI 10 XTAL_OUT VDD0P9_40 22
XTAL_IN VDD0P9_22
Internal SRV
Y3 16 Shared with PCH
25MHZ_18PF_X3G025000DI1H-H VDD0P9_16 8
VDD0P9_8 1.05V SVR *
1 3 LAN_TEST_EN 30
IN OUT TEST_EN
27P_0402_50V8J
27P_0402_50V8J
2 4 RES_BIAS 12 7 REGCTL_PNP10 STUFF: R548 STUFF: L29

C GND GND RBIAS CTRL0P9 C
2 2 NO STUFF: L29 NO STUFF: R548
C470
49
VSS_EPAD
1
C471
1K_0402_5%
3.01K_0402_1%
WGI217LM-QQ4R-A3_QFN48_6X6~D
1 1
R561
R562
Need update symbol by pin 5
LAN ANALOG SWITCH

+3.3V_LAN
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1 1 1
C472
C473
C474
2 2 2
Layout Notice : Place bead as
close PI3L500 as possible
39
30
21
14
8
4
1
U32
VDD
VDD
VDD
VDD
VDD
VDD
VDD
38 SW_LAN_TX3-
B0+ SW_LAN_TX3- <34> +3.3V_LAN
B 37 SW_LAN_TX3+ B
B0- SW_LAN_TX3+ <34>
LAN_TX3- @ R3763 1 20_0603_5% LAN_TX3-R 2
A0+ 34 SW_LAN_TX2- @ C478
LAN_TX3+ @ R3764 1 20_0603_5% LAN_TX3+R 3 B1+ 33 SW_LAN_TX2+ SW_LAN_TX2- <34> 1 2
A0- B1- SW_LAN_TX2+ <34>
29 SW_LAN_TX1- 0.1U_0402_25V6
B2+ SW_LAN_TX1- <34>
5
LAN_TX2- @ R3765 1 20_0603_5% LAN_TX2-R 6 28 SW_LAN_TX1+
A1+ B2- SW_LAN_TX1+ <34>
U15
VCC
LAN_TX2+ @ R3766 1 20_0603_5% LAN_TX2+R 7 25 SW_LAN_TX0- LOM_SPD100LED_ORG# 1 NL17SZ08DFT2G_SC70-5
A1- B3+ SW_LAN_TX0- <34> IN B
24 SW_LAN_TX0+ 4
B3- SW_LAN_TX0+ <34> OUT Y WLAN_LAN_DISB# <45>
LOM_SPD10LED_GRN# 2
GND
LAN_TX1- @ R3767 1 20_0603_5% LAN_TX1-R 9 17 LAN_ACTLED_YEL# IN A
A2+ LEDB0 18 LED_100_ORG#
LAN_TX1+ @ R3768 1 20_0603_5% LAN_TX1+R 10 LEDB1 41 LED_10_GRN#
3
A2- LEDB2
36 DOCK_LOM_TRD3-
C0+ DOCK_LOM_TRD3- <44>
LAN_TX0- @ R3769 1 20_0603_5% LAN_TX0-R 11 35 DOCK_LOM_TRD3+
A3+ C0- DOCK_LOM_TRD3+ <44>
Q326
LAN_TX0+ @ R3770 1 20_0603_5% LAN_TX0+R 12 32 DOCK_LOM_TRD2- Q325A L2N7002WT1G_SC-70-3
A3- C1+ 31 DOCK_LOM_TRD2+ DOCK_LOM_TRD2- <44> DMN66D0LDW-7_SOT363-6
C1- DOCK_LOM_TRD2+ <44>
D
LAN_ACTLED_YEL# 1 6 LED_10_GRN# 3 1
LAN_ACTLED_YEL#_Q <34> LED_10_GRN#_Q <34>
DOCKED 13 27 DOCK_LOM_TRD1-
<45> DOCKED SEL C2+ DOCK_LOM_TRD1- <44>
26 DOCK_LOM_TRD1+
C2- DOCK_LOM_TRD1+ <44>
G
2
2
LOM_ACTLED_YEL# 15 23 DOCK_LOM_TRD0-
LEDA0 C3+ DOCK_LOM_TRD0- <44>
LOM_SPD100LED_ORG# 16 22 DOCK_LOM_TRD0+ SYS_LED_MASK#
LEDA1 C3- DOCK_LOM_TRD0+ <44> SYS_LED_MASK# <24,32,45>
LOM_SPD10LED_GRN# 42 SYS_LED_MASK#
LEDA2 19 DOCK_LOM_ACTLED_YEL#
LEDC0 DOCK_LOM_ACTLED_YEL# <44>
5 20 DOCK_LOM_SPD100LED_ORG#
PD LEDC1 DOCK_LOM_SPD100LED_ORG# <44>
40 DOCK_LOM_SPD10LED_GRN#
LEDC2 DOCK_LOM_SPD10LED_GRN# <44>
43 Q325B
1: TO DOCK PAD_GND DMN66D0LDW-7_SOT363-6
DOCKED LED_100_ORG# 4 3
LED_100_ORG#_Q <34>
0: TO RJ45
A A
PI3L720ZHEX_TQFN42_9X3P5
5
SYS_LED_MASK#
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT LAN
1.0
5 4 3 2 1
5 4 3 2 1
D D
SW_LAN_TX0+_R 1 2 SW_LAN_TX0-_R
@ C500 100P_0402_50V8J
SW_LAN_TX1+_R 1 2 SW_LAN_TX1-_R
@ C501 100P_0402_50V8J
T156
1 1:1 24 NB_LAN_TX0+ +3.3V_LAN

@ R575 1 2 0_0402_5% SW_LAN_TX0+_R TD1+ TX1+
<33> SW_LAN_TX0+
@ R576 1 2 0_0402_5% SW_LAN_TX0-_R
<33> SW_LAN_TX0- 2
TD1- 23 NB_LAN_TX0-
TX1- JLOM1
C479 0.47U_0603_10V7K
2 1 +TRM_CT1 3 22 Z2805 9
TDCT1 TXCT1 Yellow LED+
C480 0.47U_0603_10V7K 1 2 10
C 2 1 +TRM_CT2 4 21 Z2807 <33> LAN_ACTLED_YEL#_Q Yellow LED- C
R1166 150_0402_5%
5 TDCT2 TXCT2 20 NB_LAN_TX1+ NB_LAN_TX3- 8
TD2+ 1:1 TX2+ PR4-
@ R577 1 20_0402_5% SW_LAN_TX1+_R NB_LAN_TX3+ 7
<33> SW_LAN_TX1+ PR4+
@ R578 1 20_0402_5% SW_LAN_TX1-_R NB_LAN_TX1- 6
<33> SW_LAN_TX1- 6 19 NB_LAN_TX1- PR2-
TD2- TX2- NB_LAN_TX2- 5
PR3-
NB_LAN_TX2+ 4
PR3+
NB_LAN_TX1+ 3
SW_LAN_TX2+ 7 1:1 18 NB_LAN_TX2+ PR2+
<33> SW_LAN_TX2+ TD3+ TX3+ 2
NB_LAN_TX0-
PR1- 15
NB_LAN_TX0+ 1 GND
SW_LAN_TX2- 8 PR1+ 14
<33> SW_LAN_TX2- TD3- 17 NB_LAN_TX2- 1 2 11 GND
TX3- <33> LED_10_GRN#_Q Green LED-
R1653 150_0402_5%
1 2 13
+TRM_CT3 9 16 Z2806 <33> LED_100_ORG#_Q Orange LED-
R1167 150_0402_5%
TDCT3 TXCT3 12
Green-Orange LED+
+TRM_CT4 10 15 Z2808
TDCT4 TXCT4
75_0402_1%
75_0402_1%
75_0402_1%
75_0402_1%
SW_LAN_TX3+ 11 1:1 14 NB_LAN_TX3+ J-L_TNBNRBC80002008
<33> SW_LAN_TX3+ TD4+ TX4+
0.47U_0603_10V7K
0.47U_0603_10V7K
+3.3V_LAN
CONN@
1 1
C483
C484
SW_LAN_TX3- 12 13 NB_LAN_TX3-
2 2 <33> SW_LAN_TX3- TD4- TX4-
1U_0603_10V6K
0.1U_0402_25V6
470P_0402_50V7K
1 1 1
1
B B
C481
C482
C1167
350uH_IH-115-F~D
2 2 2
T156 change PN to SP050006Y00 S X'FORM_ NS692417 LAN
GND
R571 2
R572 2
R573 2
R574 2
CHASSIS
1 2 EMC@ C485 GND_CHASSIS
150P_1808_3KV8J
Close to JLOM1
A A
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT RJ45 Conn
1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN_TPM
+3.3V_RUN +3.3V_RUN_TPM
PJP61 +3.3V_RUN_TPM
0.1U_0402_25V6
4700P_0402_25V7K
D 1 2 D
1 1
ATMEL TPM for E4
C44
C45
PAD-OPEN1x1m
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0402_25V6
CONN@
2 2
1 1 1 1
U39
C550
C551
C552
C553
10
5 VCC_0 19 2 2 2 2
SB3V VCC_1 24
1 2 VCC_2
<16> SUS_STAT#/LPCPD#
@ R1667 0_0402_5%
1 2
<20> PCH_GPIO22
@ R3771 0_0402_5%
1 2 SP_TPM_LPC_EN_R 28 12
<45> SP_TPM_LPC_EN LPCPD# V_BAT 13
@ R1169 0_0402_5%
26 NBO_13 14
<18,37,45,46> LPC_LAD0 23 LAD0 NBO_14
<18,37,45,46> LPC_LAD1 20 LAD1
<18,37,45,46> LPC_LAD2 17 LAD2
<18,37,45,46> LPC_LAD3 LAD3 6
GPIO6
21 9 1 2
<17> CLK_PCI_TPM 22 LCLK TESTBI 8 R657 4.7K_0402_5%
<18,37,45,46> LPC_LFRAME# 16 LFRAME# TESTI
<16,37,38,39,45,46> PCH_PLTRST#_EC 27 LRESET#
<17,18,45,46> IRQ_SERIRQ 15 SERIRQ
<16,45,46> CLKRUN# CLKRUN# 7
NC_7
1 4
C 2 ATEST_1 GND_4 11 C
3 ATEST_2 GND_11 18
ATEST_3 GND_18 25
GND_25
AT97SC3204-DX4A12-AB_TSSOP28
JUSH1 pin reverse between IVY and

HSW to support E4 13 USH board
JUSH1
22
21 GND2
GND1
20
19 20
<19> USBP7- 18 19
USH CONN <46>

<19>
USH_SMBCLK
USBP7+ 17
16
15
18
17
16
<46> USH_SMBDAT 14 15
<45> BCM5882_ALERT# 13 14
+3.3V_SUS +3.3V_SUS 13
12
11 12
USH_SMBCLK 2 1 10 11
2.2K_0402_5% R589 9 10
USH_SMBDAT 2 1 8 9
B +3.3V_RUN 8 B
2.2K_0402_5% R585 7
+5V_RUN 7
6
USH_PWR_STATE# 1 2 <16> PLTRST_USH# 5 6
JAPS1 1M_0402_5% R1640 <45> USH_PWR_STATE# 4 5
1 <17,20> CONTACTLESS_DET# 3 4
+3.3V_ALW_PCH 1 3
2 2
<16,39,40,45,60,62> SIO_SLP_S3# 3 2 1 2
+PCH_VCCDSW3_3 3 <20> USH_DET# 1
4
<16,46> SIO_SLP_S5# 5 4 HB_A522020-SCHR22
<16,45,58> SIO_SLP_S4# 6 5
<16,45,59> SIO_SLP_A# 6 CONN@
7
+3.3V_ALW 7
8
9 8
<15> PCH_RTCRST# 10 9
11 10
<24,46> POWER_SW#_MB 12 11 +3.3V_SUS +3.3V_RUN +5V_RUN
13 12
<16> SYS_RESET# 14 13
14
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
15
16 15
16
1 1 1
C53
C51
C52
17
18 GND
GND @ @ @
TYCO_1-2041070-6~D 2 2 2
CONN@
Close to JUSH1
A A
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT USH board conn / TPM
1.0
5 4 3 2 1
A B C D E
C575 must close to U38.27 within 50mils

C576 must close to U38.9 within 50mils
C577 must close to U38.9 with 100mils
+3.3V_RUN L45 must close to U38.9 within 200mils Close to U38.11
+3.3V_RUN +3.3V_RUN_OZVCC trace width 30mils
+3.3V_RUN
L45 2 1 +3.3V_RUN_OZVCC
BLM15BD601SN1D_2P
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
close to U38.23
close to U38.42
4.7U_0603_6.3V6K
0.1U_0402_25V6
1
1
C581
C574
C578
C577
C576
C575
2
2
C1502
C1503
2
1 1
1
+1.2V_OZ_AUX_LDO
+3.3V_OZ_IO_LDO
0.1U_0402_25V6
4.7U_0603_6.3V6K
1U_0603_10V7K
+1.2V_LDO +3.3V_RUN
2
2
C800
C566
C564
U38
Close to U38.13
4.7U_0603_6.3V6K
1
1
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
0.1U_0402_25V6
9 12
PE_33VCCAIN
OZ777FJ2LN AUX_LDO_CAP
close to U38.10
close to U38.41
close to U38.10
2
27
2 UHSII_33VCCAIN/NC
2
C1507
C1506
C1505
25
SD_IO_LDO_CAP
C1504
C1501
1
42
1
1
SD_33VCCD
trace width 30mils 23 Close to U38.25 Close to U38.12
SD_SKT_33VIN
trace width 30mils 13 22
AUX _33VIN SD_SKT_33VOUT +3.3V_RUN_CARD
11 24
+1.2V_LDO +3.3V_RUN MAIN_LDO_VIN SD_SKT_18VOUT +1.8V_RUN_CARD
L47 10
L47 close to U38.31 within 200mils C559 1 2 1U_0603_10V7K
2 1 +1.2V_LDO, +1.2V_LDO_OZ trace width 30mils MAIN_LDO_12VOUT C560 1 2 4.7U_0603_6.3V6K
BLM15BD601SN1D_2P
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
41
CORE_12VCCD
close to U38.31
close to U38.26
close to U38.31
close to U38.34
close to U38.1
20 SD_WPI
SD_WPI
2
+1.2V_LDO_OZ 36 21 SD_CD#
UHSII_12VCCAIN/NC SD_CD#
C561
C1510
C1509
C1508
31
2 28 UHSII_12VCCAIN/NC 43 SD_CLK_R EMC@ R676 1 2 10_0402_1% SD_CLK 2
1
UHSII_12VCCAIN/NC SD_CLK 45 SD_CMD

1 SD_CMD
PE_12VCCAIN 39
MMC_D7 40
R677 must be close to U38 less than 100mils MMC_D6 44
1 2 OZ_PE_REXT 4 MMC_D5 46
R677 191_0402_1% PE_REXT MMC_D4 47 SD_D3
C567 1 2 0.1U_0402_25V6 PCIE_PTX_MMIRX_P8_C 6 SD_D3 48 SD_D2
<19> PCIE_PTX_MMIRX_P8 PE_RXP SD_D2
C568 1 2 0.1U_0402_25V6 PCIE_PTX_MMIRX_N8_C 5 37
<19> PCIE_PTX_MMIRX_N8 PE_RXM SD_D1 38
C569 1 2 0.1U_0402_25V6 PCIE_PRX_MMITX_P8_C 7 SD_D0 @ LE5
<19> PCIE_PRX_MMITX_P8 C571 1 2 0.1U_0402_25V6 PCIE_PRX_MMITX_N8_C 8 PE_TXP 29 SD_D1_RCLKR_N 1 2 SD_D1_RCLK_N
<19> PCIE_PRX_MMITX_N8 PE_TXM SD_RCLK_M/NC 30 SD_D0_RCLKR_P 1 2
2 SD_RCLK_P/NC 32 SD_UHS2_D1P_R
<17> CLK_PCIE_MMI# 3 PE_REFCLKM SD_D1P/NC 33 SD_UHS2_D1N_R 4 3 SD_D0_RCLK_P_MMC_D0
<17> CLK_PCIE_MMI PE_REFCLKP SD_D1M/NC 34 SD_UHS2_D0N_R 4 3
15 SD_D0M/NC 35 SD_UHS2_D0P_R DLW21SN900HQ2L_0805_4P
<16> PLTRST_MMI# PE_RST#_GATE# SD_D0P/NC @ RE27 1 2 0_0402_5%
OZ_LDO_EN 14 26 R1702 1 2 4.7K_0402_1%
MAIN_LDO_EN SD_REXT/NC
16 R1702 must be close to U38 less than 100mils @ RE28 1 2 0_0402_5%
<32,37,38,39,46> PCIE_WAKE# DEV_WAKE#
17 19
<15,17> MMICLK_REQ# CLKREQ# LED# please routing daisy chain
MULTIO_0 18 49 1. from U38.38 (SD_D0) -> U38.32 (SD_RCLK_P) -> LE5.4
IO0_LDOSEL GND 2. From U38.37 (SD_D1) -> U38.33 (SD_RCLK_N) -> LE5.1
OZ777FJ2LN_QFN48_6X6
+3.3V_RUN_CARD
LE2 @ JSD1
3 SD_UHS2_D1P_R 1 2 SD_UHS2_D1P 4 3
1 2 14 VDD/VDD1
SD_CMD 2 VDD2
4.7U_0603_6.3V6K
SD_UHS2_D1N_R 4 3 SD_UHS2_D1N SD_CLK 5 CMD
4 3 CLK
@ C572
1
DLW21SN900HQ2L_0805_4P SD_CD# 17
@ RE3 1 2 0_0402_5% SD_WPI 18 CARD DETECT
WRITE PROTEC
0.1U_0402_25V6
2
1
1M_0402_5%
SD_D0_RCLK_P_MMC_D0 7
DAT0/RCLK+
2
R3884
@ RE4 1 2 0_0402_5% SD_D1_RCLK_N 8
DAT1/RCLK-
C802
SD_D2 9
+3.3V_RUN SD_D3 1 DAT2
1
SD_UHS2_D0P 11 CD/DAT3
2
LE4 @ SD_UHS2_D0N 12 D0+
SD_UHS2_D0N_R 1 2 SD_UHS2_D0N +1.8V_RUN_CARD SD_UHS2_D1P 16 D0- 19
1 2 OZ_LDO_EN 1 2 SD_UHS2_D1N 15 D1+ GND 20
R894 10K_0402_5% D1- GND 21
SD_UHS2_D0P_R 4 3 SD_UHS2_D0P 3 GND 22
0.1U_0402_25V6
4 3 O2 request 6 VSS1 GND 23
VSS2 GND
@ C580
1 2 MULTIO_0 DLW21SN900HQ2L_0805_4P 10 24
VSS3 GND
1
R1700 100K_0402_5% @ RE25 1 2 0_0402_5% 13 25
VSS4 GND
ALPS_SCDACA0101
2
@ RE26 1 2 0_0402_5% CONN@
4 4
only for MMC/SD

PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Card Reader
1.0
A B C D E
5 4 3 2 1
1 2
@ R693 0_0402_5%
<45> WLAN_RADIO_DIS#
D31
1 2 WLAN_RADIO_DIS#_R
RB751V40_SC76-2
Mini WLAN/WIMAX/60GHz H=9 +3.3V_WLAN
1 2
@ R694 0_0402_5% 2 1 WIGIG60GHZ_DIS#_R
@ R725 100K_0402_5%
1 2 WIGIG60GHZ_DIS#_R
<45> WIGIG60GHZ_DIS#
D35 RB751V40_SC76-2
1 2 2 1 WLAN_RADIO_DIS#_R
@ R695 0_0402_5% @ R3885 100K_0402_5%
1 2 BT_RADIO_DIS#_R
<45> BT_RADIO_DIS# 2 1 BT_RADIO_DIS#_R
D36 RB751V40_SC76-2
+3.3V_WLAN +3.3V_WLAN @ R3886 100K_0402_5%
D JMINI2 D
<32,36,38,39,46> PCIE_WAKE# PCIE_WAKE# 1 2
3 1 2 4
5/24 confirmed with Sean can remove 3 4
COEX2_WLAN_ACTIVE and pin4 COEX1_BT_ACTIVE
5 6
7 5 6 8 C595
<17> MINI2CLK_REQ# 9 7 8 10 1 2 +3.3V_RUN
11 9 10 12
<17> CLK_PCIE_MINI2# 13 11 12 14 MSDATA 4700P_0402_25V7K RP20
<17> CLK_PCIE_MINI2 15 13 14 16 1 8 USB_MCARD1_DET#
17 15 16 18 HOST_DEBUG_TX <46> 2 7 CPPE#
<45,46> EC5048_TX 19 17 18 20 WLAN_RADIO_DIS#_R 3 6
<46> MSCLK 21 19 20 22 2 1 PCH_PLTRST#_EC 4 5 AUX_EN_WOWL
21 22 PCH_PLTRST#_EC <16,35,38,39,45,46> AUX_EN_WOWL <39,45>
PCIE_PRX_WLANTX_N3 23 24 @ R703 0_0402_5%
<19> PCIE_PRX_WLANTX_N3 PCIE_PRX_WLANTX_P3 25 23 24 26 100K_0804_8P4R_5%
<19> PCIE_PRX_WLANTX_P3 27 25 26 28
C596 0.1U_0402_25V6 29 27 28 30
1 2 PCIE_PTX_WLANRX_N3_C 31 29 30 32 WIGIG60GHZ_DIS#_R
<19> PCIE_PTX_WLANRX_N3 1 2 PCIE_PTX_WLANRX_P3_C 33 31 32 34
<19> PCIE_PTX_WLANRX_P3 35 33 34 36
C598 0.1U_0402_25V6 USBP4-
37 35 36 38 USBP4- <19>
CPPE# USBP4+
<16> CPPE# 39 37 38 40 USBP4+ <19>
USB_MCARD1_DET#
41 39 40 42 USB_MCARD1_DET# <16>
WIGIG_LED#
43 41 42 44 WLAN_LED#
45 43 44 46 BT_LED#
<18> PCH_CL_CLK1 47 45 46 48 1 2
<18> PCH_CL_DATA1 47 48 MSDATA <46>
@ R707 2 1 0_0402_5% 49 50 @ R706 0_0402_5%
<18> PCH_CL_RST1# 51 49 50 52
BT_RADIO_DIS#_R WIMAX_LED# STUDY FOR DEBUG
51 52
53 54
GND1 GND2
BELLW_80003-8041
CONN@
+3.3V_WLAN
C C
8
7
6
5
RP13
100K_0804_8P4R_5%
5
+3.3V_WLAN
1
2
3
4
WIGIG_LED# 4 3 WIRELESS_LED#
WIRELESS_LED# <24,38,45>
Q124B
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
0.1U_0402_25V6
2
1 1 1 2 2 1
@ C603
WLAN_LED# 1 6
C604
C605
C606
C607
C608
Q124A
2 2 2 1 1 2 DMN66D0LDW-7_SOT363-6
2
G
BT_LED# 3 1
D
Q89
L2N7002WT1G_SC-70-3
1/2 Minicard Pink Pather Card H=9

+3.3V_PCIE_FLASH
+3.3V_PCIE_FLASH
B JMINI3 B
PCIE_WAKE# 1 2
3 1 2 4
5 3 4 6
7 5 6 8
<17,19> MINI3CLK_REQ# 9 7 8 10 LPC_LFRAME# <18,35,45,46>
11 9 10 12 LPC_LAD3 <18,35,45,46>
CLK_PCIE_MINI3#
<17> CLK_PCIE_MINI3# 13 11 12 14 LPC_LAD2 <18,35,45,46>
CLK_PCIE_MINI3
<17> CLK_PCIE_MINI3 15 13 14 16 LPC_LAD1 <18,35,45,46>
17 15 16 18 LPC_LAD0 <18,35,45,46>
PCH_PLTRST#_EC
PCLK_80H 19 17 18 20
<17> PCLK_80H 21 19 20 22 PCH_PLTRST#_EC
PCIE_PRX_WPANTX_N6 23 21 22 24
<19> PCIE_PRX_WPANTX_N6 PCIE_PRX_WPANTX_P6 25 23 24 26
<19> PCIE_PRX_WPANTX_P6 27 25 26 28
C617 0.1U_0402_25V6 29 27 28 30
1 2 PCIE_PTX_WPANRX_N6_C 31 29 30 32
<19> PCIE_PTX_WPANRX_N6 1 2 PCIE_PTX_WPANRX_P6_C 33 31 32 34
<19> PCIE_PTX_WPANRX_P6 35 33 34 36
C618 0.1U_0402_25V6 USBP8-
37 35 36 38 USBP8- <19>
USBP8+
39 37 38 40 USBP8+ <19>
41 39 40 42
43 41 42 44
45 43 44 46
47 45 46 48
49 47 48 50
51 49 50 52
51 52
+3.3V_PCIE_FLASH 53 54
GND1 GND2
BELLW_80003-1121
CONN@
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
0.1U_0402_25V6
1 1 1 2 2 1
@ C621
C622
C623
C624
C625
C626
A A
2 2 2 1 1 2
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT WLAN/Pink Pather Mini Card
1.0
5 4 3 2 1
5 4 3 2 1
Mini WWAN/GPS/LTE/UWB H=9 (1) Wake Enabled and Active

+3.3V_PCIE_WWAN +3.3V_PCIE_WWAN (2) Wake NOT Enabled nor Active
JMINI1
<32,36,37,39,46> PCIE_WAKE# PCIE_WAKE# 1 2 D0-D2&D3 hot Power D3 cold Power
3 1 2 4
3 4 PWR Rail Voltage
5 6
7 5 6 8 Tolerance
<17> MINI1CLK_REQ# 7 8 +SIM_PWR Peak(mA) Typ(mA) Peak(mA) Typ(mA)
9 10 UIM_DATA
CLK_PCIE_MINI1# 11 9 10 12 UIM_CLK
<17> CLK_PCIE_MINI1# CLK_PCIE_MINI1 13 11 12 14 UIM_RESET
<17> CLK_PCIE_MINI1 13 14 +3.3V_PCIE_WWAN +-9% 2750 800 800 (1) 150 (1)
15 16 +UIM_VPP
17 15 16 18 5 (2)
19 17 18 20
D 19 20 WWAN_RADIO_DIS# <45> D
21 22 2 1
23 21 22 24 PCH_PLTRST#_EC <16,35,37,39,45,46>
@ R704 0_0402_5%
<15> PCIE_SATA_PRX_WANTX_P4 25 23 24 26
<15> PCIE_SATA_PRX_WANTX_N4 27 25 26 28
29 27 28 30
2 1 PCIE_SATA_PTX_WANRX_N4_C 31 29 30 32
<15> PCIE_SATA_PTX_WANRX_N4 33 31 32 34
C417 0.1U_0402_10V7K
2 1 PCIE_SATA_PTX_WANRX_P4_C 35 33 34 36 USBP5-
<15> PCIE_SATA_PTX_WANRX_P4 37 35 36 38 USBP5- <19>
C416 0.1U_0402_10V7K USBP5+
39 37 38 40 USBP5+ <19>
41 39 40 42 LED_WWAN_OUT#
check if need to change to 10nF due
to WWAN slot has no PCIE device
43
45
47
41
43
45
42
44
46
44
46
48
+SIM_PWR SIM Card Push-Push
49 47 48 50 JSIM1
51 49 50 52 1
<45> HW_GPS_DISABLE2# 51 52 UIM_RESET 2 VCC 11
RST GND_2
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
53 54 UIM_CLK 3 12
GND1 GND2 +3.3V_PCIE_WWAN 4 CLK GND_3 13
+3.3V_PCIE_WWAN 5 D+ GND_4 14
1 1 1 GND_1 GND_5
@ C639
@ C636
BELLW_80003-8041 +UIM_VPP 6 15
VPP GND_6
C616
CONN@ UIM_DATA 7 16
I/O GND_7
150U_D2_6.3VY_R15M
100K_0402_5%
8 17
2 2 2 D- GND_8
0.047U_0402_16V4Z
0.047U_0402_16V4Z
33P_0402_50V8J
22U_0805_6.3V6M
33P_0402_50V8J
9 18
DET GND_9
2
1 10
COM
R719
33P_0402_50V8J
33P_0402_50V8J
33P_0402_50V8J
33P_0402_50V8J
1 1 1 1 1
C615
+
1 1 1 1
C610
C611
C612
C613
C614
@ C631
@ C630
@ C628
@ C629
T-SOL_159-1000302602
2
G
CONN@
1
2 2 2 2 2 2
LED_WWAN_OUT# 3 1 2 2 2 2
WIRELESS_LED# <24,37,45>
D
Q77
L2N7002WT1G_SC-70-3
C C
B B
A A
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT WWAN Mini Card
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-9934P
5 4 3 2 1
5 4 3 2 1
+3.3V_PCIE_WWAN/+3.3V_PCIE_FLASH
D
+1.5V_RUN +3.3V_RUN +3.3V_SUS

Express Card PWR S/W +3.3V_CARDAUX +3.3V_CARD +1.5V_CARD
D
+3.3V_PCIE_WWAN
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
10U_0603_6.3V6M
0.1U_0402_25V6
10U_0603_6.3V6M
0.1U_0402_25V6
10U_0603_6.3V6M
@ C446
U145 10U_0603_6.3V6M
2 1 +3.3V_ALW
1 14 1 2 1 1 1 1 1 1 1 1 1
R726 100K_0402_5% 2 VIN1 VOUT1 13
VIN1 VOUT1
C635
C634
C633
C642
C643
C640
C641
C637
C638
3 12 1 2
<45> MCARD_WWAN_PWREN ON1 CT1 2 2 2 2 2 2 2 2 2
C445 470P_0402_50V7K
+5V_ALW
4 11
VBIAS GND U41
5 10 1 2 17 15
<45> MCARD_MISC_PWREN ON2 CT2 2 AUXIN AUXOUT 3
C450 470P_0402_50V7K
6 9 12 3.3VIN 3.3VOUT 11
2 1 7 VIN2 VOUT2 8 1.5VIN 1.5VOUT
VIN2 VOUT2 +3.3V_PCIE_FLASH
R733 100K_0402_5% 1 @ R734 1 2 0_0402_5% 20 8 CARD_RESET#
15 <16,35,40,45,60,62> SIO_SLP_S3# SHDN# PERST#
@ R717 1 2 0_0402_5% EXPRCRD_STBY_R# 1 10 EXPRCRD_CPPE#
GPAD <32,45,48,60> RUN_ON 6 STBY# CPPE# 9
@ C449 <16,35,37,38,45,46> PCH_PLTRST#_EC CPUSB#
TPS22966DPUR_SON14_2X3 19 SYSRST# CPUSB#
10U_0603_6.3V6M OC#
2
0.1U_0402_25V6
EMC@ CE10
0.1U_0402_25V6
EMC@ CE11
EMC@ CE12
0.1U_0402_25V6
+3.3V_RUN
4 1 1 1
5 NC 18
+3.3V_CARD NC RCLKEN
+1.5V_CARD
13
14 NC 7
+1.5V_RUN NC GND 2 2 2
16 21
NC PAD
TPS2231MRGPR-2_QFN20_4X4
C C
Note: Add connection on pin4, pin5, pin 13

and pin14 to support GMT 2nd source part
Express Card Conn.
+3.3V_WLAN/+3.3V_LAN source
+3.3V_WLAN
U57
+3.3V_ALW
1 14 1 2
2 VIN1 VOUT1 13 @ C423 10U_0603_6.3V6M
VIN1 VOUT1
3 12 1 2
<37,45> AUX_EN_WOWL ON1 CT1 C444 470P_0402_50V7K
4 11
+5V_ALW VBIAS GND
5 10 1 2
<16,45> SIO_SLP_LAN# ON2 CT2 C448 470P_0402_50V7K
6 9 +3.3V_SUS
7 VIN2 VOUT2 8
VIN2 VOUT2 +3.3V_LAN
1
15
GPAD
2.2K_0402_5%
2.2K_0402_5%
B @ C447 B
1
TPS22966DPUR_SON14_2X3 10U_0603_6.3V6M
2
R732
R731
JEXP1
2
1 2 CPUSB#
3 1 2 4
<19> USBP10- 5 3 4 6
<19> USBP10+ 7 5 6 8 CARD_SMBCLK <46>
9 7 8 10 CARD_SMBDAT <46>
<17> CLK_PCIE_EXP# 9 10 +1.5V_CARD
11 12
<17> CLK_PCIE_EXP 11 12
0.1U_0402_25V6
13 14 1
15 13 14 16 PCIE_WAKE# <32,36,37,38,46>
<19> PCIE_PRX_EXPTX_N7 15 16 +3.3V_CARDAUX
C645
17 18 CARD_RESET#
<19> PCIE_PRX_EXPTX_P7 17 18
0.1U_0402_25V6
19 20
21 19 20 22 2
<19> PCIE_PTX_EXPRX_N7 21 22 +3.3V_CARD 1 @
23 24
<19> PCIE_PTX_EXPRX_P7 23 24
C646
25 26
27 25 26 28 EXPRCRD_CPPE#
<17> EXPCLK_REQ# 27 28 2
0.1U_0402_25V6
29 30 @
29 30
1
31 32
GND GND
C649
2
@
E-T_1001K-F30C-03L
CONN@
A A
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PCIE-SATA SW / PCIE PWR
1.0
5 4 3 2 1
5 4 3 2 1
Rear Side (JUSB1)
D D
1 2
@ R1605 0_0402_5%
EMC@ L95
4 3 USB3RN1_D-
<19> USB3RN1 4 3
1 2 USB3RP1_D+
<19> USB3RP1 1 2
CMMI21T-900Y-N_0805_4P
1 2
@ R1604 0_0402_5%
1 2
@ R1606 0_0402_5%
C C
EMC@ L96
1 2 USB3TN1_C 4 3 USB3TN1_D-
<19> USB3TN1 4 3
C1533 0.1U_0402_25V6
1 2 USB3TP1_C 1 2 USB3TP1_D+
<19> USB3TP1 1 2
C1534 0.1U_0402_25V6
CMMI21T-900Y-N_0805_4P
1 2
@ R1603 0_0402_5%
1 2
@ R736 0_0402_5%
EMC@ D78
USB3TP1_D+ 1 9 USB3TP1_D+
EMC@ L51
USB3TN1_D- 2 8 USB3TN1_D- USBP0_D- 1 2 USBP0_R_D- +5V_USB_CHG_PWR
1 2 JUSB1
USB3RP1_D+ 4 7 USB3RP1_D+ 1
USBP0_D+ 4 3 USBP0_R_D+ USBP0_R_D- 2 VBUS
4 3 D-
0.1U_0402_25V6
USB3RN1_D- 5 6 USB3RN1_D- 1 USBP0_R_D+ 3
D+
47U_0805_6.3V6M
220U_6.3V_M
DLW21HN900SQ2L_0805_4P 1 1 4
GND
@ C1552
C651
B + USB3RN1_D- 5 B
StdA-SSRX-
2
C654
L30ESDL5V0C3-2_SOT23-3
EMC@ D72
USB3RP1_D+ 6 10
3 1 2 7 StdA-SSRX+ GND 11
@ R740 0_0402_5% 2 2 2 USB3TN1_D- 8 GND-DRAIN GND 12
TVWDF1004AD0_DFN9 USB3TP1_D+ 9 StdA-SSTX- GND 13
StdA-SSTX+ GND
SANTA_373130-1
+5V_ALW CONN@
1
100K_0402_5%
2
R816
1
PWRSHARE_EN#
<45> USB_PWR_SHR_VBUS_EN
<16,35,39,45,60,62> SIO_SLP_S3#
@ R153 1 2 0_0402_5%
U2
+5V_ALW 2.5A +5V_USB_CHG_PWR
1
D U48
@ R1626 1 2 0_0402_5% SB# 8 1 2 Q48 1 8
<45> USB_PWR_SHR_EN# 7 CB CEN 2 2 GND VOUT 7
USBP0_D- G L2N7002WT1G_SC-70-3
<19> USBP0- TDM DM VIN VOUT
10U_0603_6.3V6M
0.1U_0402_25V6
6 3 USBP0_D+ +5V_ALW S 3 6
3
<19> USBP0+ 5 TDP DP 4 SEL PWRSHARE_EN# 4 VIN VOUT 5

VDD SELCDP EN FLG USB_OC0# <15,19,41,42>
+5V_ALW 9 1 1
Thermal Pad
2
10K_0402_5%
@ C676
G547I2P81U_MSOP8
C675
SLG55594AVTR_TDFN8_2X2
R1614
2 2
0.1U_0402_25V6
A
1 A
1
C715
2
L2N7002WT1G_SC-70-3
1
D
@
Q59
USB_PWR_SHR_EN# 2
G
S
3
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT USB3.0_JUSB1 Rear
5 4 3 2 1
5 4 3 2 1
Right Side Top (JUSB2)
D D
C C
EMC@ L107 EMC@ D88

4 3 USBP1_D- USB3RN2_D- 1 9 USB3RN2_D-
<19> USBP1- 4 3
USB3RP2_D+ 2 8 USB3RP2_D+
1 2 USBP1_D+
<19> USBP1+ 1 2 USB3TN2_D- 4 7 USB3TN2_D-
1 2 USB3TP2_D+ 5 6 USB3TP2_D+
@ R3689 0_0402_5%
1 2
@ R3690 0_0402_5% 3
TVWDF1004AD0_DFN9
EMC@ L108
1 2 USB3RP2_D+
<19> USB3RP2 1 2
4 3 USB3RN2_D-
<19> USB3RN2 4 3 EMC@ D89
CMMI21T-900Y-N_0805_4P USBP1_D- 2
1 2 1
@ R3691 0_0402_5% USBP1_D+ 3
B B
1 2
@ R3696 0_0402_5% L30ESDL5V0C3-2_SOT23-3
D88, D89 must be as close as
EMC@ L109 possible to JUSB2
1 2 USB3TP2_C 1 2 USB3TP2_D+
<19> USB3TP2 1 2
C1519 0.1U_0402_25V6
1 2 USB3TN2_C 4 3 USB3TN2_D-
<19> USB3TN2 4 3
C1518 0.1U_0402_25V6
CMMI21T-900Y-N_0805_4P
1 2
@ R3697 0_0402_5%
1 2
@ R3698 0_0402_5%
+5V_USB_PWR2
JUSB2
USB3TP2_D+ 9
1 SSTX+
USB3TN2_D- 8 VBUS
1 SSTX-
150U_B2_6.3VM_R35M
0.1U_0402_25V6
1 USBP1_D- 2
+5V_USB_PWR2 + 7 D-
GND
C1523
C1524
+5V_ALW U91 USBP1_D+ 3 10
1 8 USB3RP2_D+ 6 D+ GND 11
2 GND VOUT 7 2 2 4 SSRX+ GND 12
3 VIN VOUT 6 USB3RN2_D- 5 GND GND 13
VIN VOUT SSRX- GND
10U_0603_6.3V6M
0.1U_0402_25V6
4 5 USB_OC0#
<42,45> ESATA_USB_PWR_EN# EN FLG USB_OC0# <15,19,40,42>
1 1 LOTES_ABA-USB-116-P04
@ C1525
G547I2P81U_MSOP8 CONN@
C1526
A 2 2 A
place C1523 between JUSB2 and JUSB3
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT USB3.0_JUSB2 Right Side top
5 4 3 2 1
5 4 3 2 1
Right Side bottom (JUSB3)
D D
C C
EMC@ L111
USB3RP5 1 2 USB3RP5_D+
<19> USB3RP5 1 2
EMC@ D91
USB3RN5 4 3 USB3RN5_D- USB3RN5_D- 1 9 USB3RN5_D-
<19> USB3RN5 4 3
CMMI21T-900Y-N_0805_4P USB3RP5_D+ 2 8 USB3RP5_D+
1 2
@ R3721 0_0402_5% USB3TN5_D- 4 7 USB3TN5_D-
1 2 USB3TP5_D+ 5 6 USB3TP5_D+
@ R3722 0_0402_5%
EMC@ L112 3
C418 1 2 0.1U_0402_25V6 USB3TP5_C 1 2 USB3TP5_D+
<19> USB3TP5 1 2 TVWDF1004AD0_DFN9
C419 1 2 0.1U_0402_25V6 USB3TN5_C 4 3 USB3TN5_D-

<19> USB3TN5 4 3
CMMI21T-900Y-N_0805_4P EMC@ D90
1 2 USBP2_D+ 2
@ R3727 0_0402_5% 1 +5V_USB_PWR3
USBP2_D- 3 JUSB3
1 2 USB3TP5_D+ 9
@ R3728 0_0402_5% 1 SSTX+
L30ESDL5V0C3-2_SOT23-3 USB3TN5_D- 8 VBUS
1 SSTX-
150U_B2_6.3V-M~D
0.1U_0402_25V6
1 USBP2_D- 2
D-
@ C1538
+ 7
GND
C1539
D90, D91 must be as close as USBP2_D+ 3 10
USB3RP5_D+ 6 D+ GND 11
possible to JUSB3 2 2 4 SSRX+ GND 12
EMC@ L110 USB3RN5_D- 5 GND GND 13
USBP2+ 1 2 USBP2_D+ SSRX- GND
<19> USBP2+ 1 2
B LOTES_ABA-USB-116-P04 B
USBP2- 4 3 USBP2_D- CONN@

<19> USBP2- 4 3
1 2 +5V_USB_PWR3 +5V_USB_PWR2
@
@ R3710 0_0402_5% +5V_ALW U93 PJP702
1 8 1 2
1 2 2 GND VOUT 7 1 2
@ R3711 0_0402_5% 3 VIN VOUT 6 JUMP_43X79
VIN VOUT 5
10U_0603_6.3V6M
0.1U_0402_25V6
<41,45> ESATA_USB_PWR_EN# 4 USB_OC1#

EN FLG USB_OC1# <15,17,19>
1 1
@ C1540
@ C1541
G547I2P81U_MSOP8 1 2
@ R3773 0_0402_5% USB_OC0# <15,19,40,41>
2 2
A A
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT USB3.0_JUSB3 Right Side bot
1.0
5 4 3 2 1
5 4 3 2 1
D D
C C
I/O board CONN.
JIO1
2 1
<16> XFR_ID# 4 2 1 3
<25> VSYNC_BUF 6 4 3 5 RED_CRT <25>
<25> HSYNC_BUF 8 6 5 7 GREEN_CRT <25>
B 10 8 7 9 BLUE_CRT <25> B
<25> DAT_DDC2_CRT 12 10 9 11
<25> CLK_DDC2_CRT 14 12 11 13
+5V_ALW 16 14 13 15 +5V_ALW
+5V_RUN 16 15
18 17
18 17 +3.3V_RUN
20 19
20 19
0.1U_0402_25V6
22 21
24 22 21 23
24 23 1
@ C50
1 26 25
28 26 25 27 @ C998
<15,19> USB_OC4# 30 28 27 29
30 29 USB3RN6 <19> 0.1U_0402_25V6
32 31 2
2 <19> USBP9+ 34 32 31 33 USB3RP6 <19>
<19> USBP9- 36 34 33 35
38 36 35 37 USB3TN6 <19>
<45> USB_SIDE_EN# 40 38 37 39 USB3TP6 <19>
40 39
DETECT_GND
42 41
G2 G1
E&T_1000K-Y40E-02L
CONN@
+5V_RUN
0.1U_0402_25V6
1
@ C1001
A A
Close to JIO1.16/18
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT USB3.0_JUSB4 Left Side
1.0
5 4 3 2 1
5 4 3 2 1
JDOCK1 CONN@
DOCK_DET_1 1 2 DOCK_AC_OFF
3 1 2 4 DOCK_AC_OFF <65>
<33>
DOCK_LOM_SPD10LED_GRN# DPD_CA_DET 5 3 4 6 DPC_CA_DET DOCK_LOM_SPD100LED_ORG# <33>
<29> DPD_CA_DET 7 5 6 8 DPC_CA_DET <29>
C690 2 1 0.1U_0402_25V6 DPD_CPU_LANE_P0_C EMC@ 2 RE7 133_0402_5% DPD_DOCK_LANE_P0 9 7 8 10 DPC_DOCK_LANE_P0 EMC@ 1 RE17 2 33_0402_5% DPC_CPU_LANE_P0_C C691 2 1 0.1U_0402_25V6
D <9> DPD_CPU_LANE_P0 9 10 DPC_CPU_LANE_P0 <9> D
C679 2 1 0.1U_0402_25V6 DPD_CPU_LANE_N0_C EMC@ 2 RE8 133_0402_5% DPD_DOCK_LANE_N0 11 12 DPC_DOCK_LANE_N0 EMC@ 1 RE18 2 33_0402_5% DPC_CPU_LANE_N0_C C680 2 1 0.1U_0402_25V6
<9> DPD_CPU_LANE_N0 13 11 12 14 DPC_CPU_LANE_N0 <9>
<9> DPD_CPU_LANE_P1 15 16 DPC_CPU_LANE_P1 <9>
DPD_DOCK_AUX 33 31 32 34 DPC_DOCK_AUX
<29> DPD_DOCK_AUX DPD_DOCK_AUX# 35 33 34 36 DPC_DOCK_AUX# DPC_DOCK_AUX <29>
<29> DPD_DOCK_AUX# 37 35 36 38 DPC_DOCK_AUX# <29>
DPD_PCH_DOCK_HPD 39 37 38 40 DPC_PCH_DOCK_HPD
<16> DPD_PCH_DOCK_HPD 41 39 40 42 DPC_PCH_DOCK_HPD <16>
+NBDOCK_DC_IN_SS 41 42 ACAV_DOCK_SRC# <65>
0.033U_0402_16V7K
0.033U_0402_16V7K
1 43 44 1
BLUE_DOCK 45 43 44 46
<25> BLUE_DOCK 47 45 46 48 DAT_DDC2_DOCK <25>
47 48 CLK_DDC2_DOCK <25>
@ C695
@ C696
49 50 Close to DOCK
2 51 49 50 52 2
RED_DOCK 53 51 52 54 SATA_PRX_DKTX_P2 2 1 Its for Enhance ESD on dock issue.
<25> RED_DOCK 55 53 54 56 SATA_PRX_DKTX_P2_C <15>
Close to DOCK SATA_PRX_DKTX_N2 C697 2 1 0.01U_0402_16V7K
57 55 56 58 SATA_PRX_DKTX_N2_C <15>
C698 0.01U_0402_16V7K
Its for Enhance ESD on dock issue. GREEN_DOCK 59 57 58 60 SATA_PTX_DKRX_P2 1 2
<25> GREEN_DOCK 61 59 60 62 SATA_PTX_DKRX_P2_C <15>
SATA_PTX_DKRX_N2 C699 1 2 0.01U_0402_16V7K
63 61 62 64 C700 0.01U_0402_16V7K SATA_PTX_DKRX_N2_C <15> L99 @
65 63 64 66 USBP6_R_D+ 3 4
<25> HSYNC_DOCK 67 65 66 68 USBP6_R_D- 3 4 USBP6+ <19>
<25> VSYNC_DOCK 69 67 68 70
DPD_PCH_DOCK_HPD 71 69 70 72 2 1
<46> CLK_MSE 73 71 72 74 USBP3+ <19> 2 1 USBP6- <19>
C <46> DAT_MSE 75 73 74 76 USBP3- <19> C
DLW21SN900HQ2L_0805_4P
77 75 76 78 @ R1672 1 2 0_0402_5%
<30> DAI_BCLK# 77 78 CLK_KBD <46>
1
79 80
<30> DAI_LRCK# 81 79 80 82 DAT_KBD <46>
R757 83 81 82 84 @ R1673 1 2 0_0402_5%
<30> DAI_DI 85 83 84 86 USB3RN3 <19>
100K_0402_5%
<30> DAI_DO# 87 85 86 88 USB3RP3 <19>
2
89 87 88 90
<30> DAI_12MHZ# 91 89 90 92 USB3TN3 <19>
93 91 92 94 USB3TP3 <19>
95 93 94 96
97 95 96 98 DPC_PCH_DOCK_HPD
<45> D_LAD0 99 97 98 100 BREATH_LED# <24,45>
<45> D_LAD1 101 99 100 102 DOCK_LOM_ACTLED_YEL# <33>
101 102
100K_0402_5%
103 104
<45> D_LAD2 103 104 DOCK_LOM_TRD0+ <33>
1
105 106
<45> D_LAD3 105 106 DOCK_LOM_TRD0- <33>
R758
107 108
109 107 108 110
<45> D_LFRAME# 111 109 110 112 DOCK_LOM_TRD1+ <33> +LOM_VCT
<45> D_CLKRUN# 113 111 112 114 DOCK_LOM_TRD1- <33>
2
113 114
1U_0402_6.3V6K
115 116 1
<45> D_SERIRQ 115 116
@ C701
117 118
<45> D_DLDRQ1# 117 118 +LOM_VCT
119 120
CLK_PCI_DOCK 121 119 120 122
<17> CLK_PCI_DOCK 123 121 122 124 DOCK_LOM_TRD2+ <33> 2
125 123 124 126 DOCK_LOM_TRD2- <33>
127 125 126 128 +3.3V_ALW
<46> DOCK_SMB_CLK 129 127 128 130 DOCK_LOM_TRD3+ <33>
<46> DOCK_SMB_DAT 131 129 130 132 DOCK_LOM_TRD3- <33>
133 131 132 134 DOCK_DET# 1 2
<45,56,65> DOCK_SMB_ALERT# 135 133 134 136 DOCK_DCIN_IS+ <64>
10K_0402_5% R755
<56> DOCK_PSID 137 135 136 138 DOCK_DCIN_IS- <64>
B 139 137 138 140 D32 B
<46> DOCK_PWR_BTN# 141 139 140 142 DOCK_POR_RST# <46>
RB751V40_SC76-2
143 141 142 144 DOCK_DET_R# 1 2
<45,56,65> SLICE_BAT_PRES# 143 144 DOCK_DET# <45,65>
145 149
GND1 PWR2 +DOCK_PWR_BAR
146 150
+DOCK_PWR_BAR PWR1 PWR2
0.1U_0603_50V7K
147 151
PWR1 PWR2
0.1U_0603_50V7K
148 152
PWR1 GND2
3
2
4.7U_0805_25V6K~D
L30ESD24VC3-2_SOT23-3
C703
1 1 153 159
Shield_G Shield_G
@
C702
@ D33
154 160
Shield_G Shield_G
CE6
155 161
156 Shield_G Shield_G 162 2 @
2 2 @ 157 Shield_G Shield_G 163
158 Shield_G Shield_G 164
Shield_G Shield_G
1
JAE_WD2F144WB1R300~D
Vinafix
CLK_PCI_DOCK
1
@ R3761
33_0402_5%
A A
100P_0402_50V8J
2
1
@
C1551
2
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DOCKING CONN
1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW +3.3V_ALW
@ PJP63
1 2 DYN_TURB_PWR_ALRT# +3.3V_ALW_5048 1 2
@ R796 10K_0402_5%
10U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
PAD-OPEN1x1m
RP4
1 8 PROCHOT_GATE 1 1 1 1 1 1
2 7 ESATA_USB_PWR_EN#
C705
C706
C707
C708
C709
C710
3 6 CPU_DETECT#
4 5 USB_PWR_SHR_EN#
D
2 2 2 2 2 2 D
100K_0804_8P4R_5%
A17
B30
A43
A54
RP3
B5
1 8 USB_PWR_SHR_VBUS_EN U46 SMSC feedback disconnect LPC_LDRQ0# at A23 pin
2 7 WWAN_RADIO_DIS#
VCC1
VCC1
VCC1
VCC1
VCC1
3 6 SLICE_BAT_PRES# A23 PAD~D T147 @
4 5 WIRELESS_ON#/OFF B52 GPIOI0 B63
<25> CRT_SWITCH GPIOA0 GPIOI1 SIO_SLP_A# <16,35,59>
A49 A60 0.75V_DDR_VTT_ON
100K_0804_8P4R_5% B53 GPIOA1 GPIOI2/TACH0 A61 0.75V_DDR_VTT_ON <58>
<39> MCARD_MISC_PWREN GPIOA2 GPIOI3 SIO_SLP_S4# <16,35,58>
<64> PROCHOT_GATE PROCHOT_GATE A50 B65
GPIOA3 GPIOI4 SIO_SLP_S3# <16,35,39,40,60,62>
RP2 LID_CL_SIO# B54 A62
GPIOA4 GPIOI5 IMVP_PWRGD <61>
1 8 HW_GPS_DISABLE2# DOCK_SMB_ALERT# A51 B66
<44,56,65> DOCK_SMB_ALERT# GPIOA5 GPIOI6 IMVP_VR_ON <61>
2 7 USB_SIDE_EN# TOUCH_SCREEN_PD# B55 A63
3 6 TOUCH_SCREEN_PD# TOUCH_SCREEN_PD# A52 GPIOA6 GPIOI7 DOCK_AC_OFF_EC <65>
4 5 DOCK_SMB_ALERT# <50> GPU_PWR_LEVEL GPIOA7 B67
USB_SIDE_EN# A33 GPIOJ0 A64 AUX_EN_WOWL <37,39>
<43> USB_SIDE_EN# GPIOB0 GPIOJ1/TACH1 WLAN_LAN_DISB# <33>
10K_8P4R_5% B36 A5 SIO_SLP_LAN#
<30> EN_I2S_NB_CODEC# GPIOB1 GPIOJ2/TACH2 SIO_SLP_LAN# <16,39>
A34 B6
<35> USH_PWR_STATE# GPOC2 GPIOJ3 SIO_SLP_SUS# <16>
<65> EN_DOCK_PWR_BAR B37 A6
A35 GPOC3 GPIOJ4 B7 GPIO_PSID_SELECT <56>
<28> PANEL_BKEN_EC GPOC4 GPIOJ5 MODC_EN <32>
+3.3V_RUN B38 A7
<16,28> ENVDD_PCH GPOC5 GPIOJ6 DOCK_HP_DET <30>
LCD_TST A36 B8
<28> LCD_TST GPOC6/TACH4 GPIOJ7 DOCK_MIC_DET <30>
1 2 SP_TPM_LPC_EN A37
@ R772 10K_0402_5% <56> PSID_DISABLE# B40 GPIOC7 A8 ME_FWP
<56,65> PBAT_PRES# GPIOD0 GPIOK0 ME_FWP <15>
A38 B9
<33> DOCKED GPIOC1 GPIOK1/TACH3 MASK_SATA_LED# <24>
1 2 DP_HDMI_HPD B41 B10 USB_PWR_SHR_EN#
<44,65> DOCK_DET# GPIOC0 GPIOK2 USB_PWR_SHR_EN# <40>
@ R1154 100K_0402_5% A39 A10
<30> AUD_NB_MUTE# GPIOB7 GPIOK3 LED_SATA_DIAG_OUT# <24>
B42 B11 TEMP_ALERT#_R 1 2 +3.3V_RUN
<39> MCARD_WWAN_PWREN GPIOB6 GPIOK4 TEMP_ALERT# <17,18>
A40 A11 RUN_ON @ R738 0_0402_5%
<28> LCD_VCC_TEST_EN GPIOB5 GPIOK5 RUN_ON <32,39,48,60>
B43 B12 RP5
<28> CCD_OFF GPIOB4 GPIOK6 AC_DIS <56,65>
A41 A12 D_CLKRUN# 4 5
<30> AUD_HP_NB_SENSE GPIOB3 GPIOK7 SPI_WP#_SEL <18>
ESATA_USB_PWR_EN# B44 D_SERIRQ 3 6
<41,42> ESATA_USB_PWR_EN# GPIOB2 B60 SUS_ON D_DLDRQ1# 2 7
GPIOL0/PWM7 SUS_ON <48,58>
A57 SLICE_BAT_ON 1 8
C
B32 GPIOL1/PWM8 B64 C
GPIOD1 GPIOL2/PWM0 BAT1_LED# <24>trace width 10 mils
<65> SLICE_BAT_ON A31 B68 100K_0804_8P4R_5%
B33 GPIOD2 GPIOL3/PWM1 A9
<44,56,65> SLICE_BAT_PRES# GPIOD3 GPIOL4/PWM3 BAT2_LED# <24>trace width 10 mils
MODULE_BATT_PRES# B15 B1
<64> MODULE_BATT_PRES# A15 GPIOD4 GPIOL5/PWM2 A18 USH_PWR_ON
GPIOD5 GPIOL6 USH_PWR_ON <48>
B16 A44 PAD~D T146 @
A16 GPIOD6 GPIOL7/PWM5 RP6
GPIOD7 B34 HW_GPS_DISABLE2# RUN_ON 1 8
GPIOM1 HW_GPS_DISABLE2# <38>
B39 CPU_VTT_ON 2 7
GPIOM3/PWM4 BREATH_LED# <24,44>
A1 B51 0.75V_DDR_VTT_ON 3 6
<37> WIGIG60GHZ_DIS# GPIOE0/RXD GPIOM4/PWM6 DIS_BAT_PROCHOT# <65>
B2 SUS_ON 4 5
<37,45,46> EC5048_TX GPIOE1/TXD
A2
B3 GPIOE2/RTS# A27 100K_0804_8P4R_5%
<15,20> MCARD_PCIE_SATA# GPIOE3/DSR# LAD0 LPC_LAD0 <18,35,37,46>
CPU_DETECT# A3 A26
<7> CPU_DETECT# GPIOE4/CTS# LAD1 LPC_LAD1 <18,35,37,46>
B45 B26
GPIOE5/DTR# LAD2 LPC_LAD2 <18,35,37,46>
A42 B25
<32> MOD_SATA_PCIE#_DET GPIOE6/RI# LAD3 LPC_LAD3 <18,35,37,46>
DP_HDMI_HPD B4 A21 LPC_LFRAME# RP19
GPIOE7/DCD# LFRAME# LPC_LFRAME# <18,35,37,46>
B22 PCH_PLTRST#_EC LID_CL_SIO# 1 8 +3.3V_ALW
LRESET# PCH_PLTRST#_EC <16,35,37,38,39,46>
A28 <15,32> USB30_SMI# USB30_SMI# 2 7 +3.3V_ALW_PCH
PCICLK CLK_PCI_5048 <17>
A59 B20 CLKRUN# CHARGE_EN 3 6
<32> ZODD_WAKE# GPIOF0 CLKRUN# CLKRUN# <16,35,46>
B62 LCD_TST 4 5
<35> BCM5882_ALERT# GPIOF1
A58 A22
<16> SUSACK# GPIOF2 LDRQ1# LPC_LDRQ1# <18>
B61 B21 100K_0804_8P4R_5%
GPIOF3/TACH8 SER_IRQ IRQ_SERIRQ <17,18,35,46>
A56 A32
<20,62> DGPU_PWROK GPIOF4/TACH7 14.318MHZ/GPIOM0 CLK_SIO_14M <17>
VGA_ID B59 B35 EC_32KHZ_ECE5048 <46>
A55 GPIOF5 CLK32/GPIOM2
<17> 3.3V_RUN_GFX_ON GPIOF6
B58
<20> SLP_ME_CSW_DEV# GPIOF7 B29
DLAD0 B28 D_LAD0 <44>
B47 DLAD1 A25 D_LAD1 <44>
<33> LAN_DISABLE#_R GPIOG0/TACH5 DLAD2 D_LAD2 <44>
CHARGE_EN A45 A24
SYS_LED_MASK# B48 GPIOG1 DLAD3 B23 D_LAD3 <44>
<24,32,33> SYS_LED_MASK# GPIOG2 DLFRAME# D_LFRAME# <44>
DYN_TURB_PWR_ALRT# A46 A19 D_CLKRUN#
GPIOG3 DCLKRUN# D_CLKRUN# <44>
<15,17,20> SIO_EXT_WAKE# B49 B24 D_DLDRQ1#
GPIOG4 DLDRQ1# D_DLDRQ1# <44>
B A47 A20 D_SERIRQ B
<24,37,38> WIRELESS_LED# GPIOG5 DSER_IRQ D_SERIRQ <44>
USB_PWR_SHR_VBUS_EN B50
<40> USB_PWR_SHR_VBUS_EN A48 GPIOG6
<37> WLAN_RADIO_DIS# GPIOG7/TACH6 A29
BC_INT# BC_INT#_ECE5048 <46>
B31
+3.3V_ALW BC_DAT BC_DAT_ECE5048 <46>
WIRELESS_ON#/OFF B13 A30
<47> WIRELESS_ON#/OFF GPIOH0 BC_CLK BC_CLK_ECE5048 <46>
A13
<37> BT_RADIO_DIS# GPIOH1
WWAN_RADIO_DIS# A53
<38> WWAN_RADIO_DIS# SYSOPT1/GPIOH2
1 2 VGA_ID B57 A4
<16,7> SYS_PWROK SYSOPT0/GPIOH3 PWRGD AND_PWRGD <46>
@ R800 100K_0402_5% @ T122 PAD~D B14
A14 GPIOH4 B56 SP_TPM_LPC_EN
<16> SIO_SLP_WLAN# GPIOH5 OUT65 SP_TPM_LPC_EN <35>
2 1 VGA_ID CPU_VTT_ON B17
R803 100K_0402_5% 1 2 B18 GPIOH6
<16> PCH_DPWROK GPIOH7
@ R802 0_0402_5% B19 1 2
TEST_PIN R804 1K_0402_5%
B46 +CAP_LDO
CAP_LDO
4.7U_0603_6.3V6K
1
B27
VSS
C714
C1
EP
VGA_ID0 DB Version 0.4 2
Discrete 0 ECE5048-LZY_DQFN132_11X11~D
LID_CL_SIO# 2 1
UMA 1 R807 10_0402_1%
LID_CL# <24,47>
0.047U_0402_16V4Z
1
+CAP_LDO trace width 20 mils
1 2 USB_PWR_SHR_EN#
<37,45,46> EC5048_TX
C716
@ R806 0_0402_5%
2
ME_FWP PCH has internal 20K PD.
ME_FWP
1
A A
1K_0402_5%
@ R793
2
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT ECE5048
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-9934P
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
@ C721 @ C733
@ C720 1 2 1 2
1 2
1U_0402_6.3V6K 1U_0402_6.3V6K
0.1U_0402_25V6
5
+RTC_CELL POWER_SW_IN# 1 2 DOCK_PWR_SW# 1 2
POWER_SW#_MB <24,35> DOCK_PWR_BTN# <44>
R811 10K_0402_5% R825 10K_0402_5%
VCC
1U_0402_6.3V6K
1U_0402_6.3V6K
ECE5048_PWRGD 1 1 2 +RTC_CELL_VBAT 1 1
IN B 4 @ R830 0_0402_5%
OUT Y AND_PWRGD <45> remove unstuff components??
0.1U_0402_25V6
C722
C734
RUNPWROK 2
GND
IN A
@ U50 2 2
1
NL17SZ08DFT2G_SC70-5
C724
+1.05V_RUN
10K_0402_5%
1 2
1
@ R1179
@ R1180 0_0402_5%
D D
U51
1 2 +3.3V_ALW 1 2 +3.3V_VTR
@ R3772 0_0402_5% @ R834 0_0402_5% B64 A10 SYSTEM_ID
VBAT GPIO021/RC_ID1 H_PROCHOT# <50,61,64,65,7>
0.1U_0402_25V6
1U_0402_6.3V4Z
B10 BOARD_ID
2
GPIO020/RC_ID2
L2N7002WT1G_SC-70-3
1 1 B8 R888 1 2 1K_0402_5%
GPIO014/GPTP-IN7/RC_ID3 VOL_UP# <47>
1
@ R8391 2 0_0402_5% A22 B27 D
+3.3V_ALW H_VTR GPIO025/UART_CLK LANWAKE# <20,33>
C739
C775
Q47
B44 HOST_DEBUG_TX PROCHOT#_EC 2
GPIO120/UART_TX HOST_DEBUG_TX <37>
0.1U_0402_25V6
1U_0402_6.3V4Z
+3.3V_ALW B46 HOST_DEBUG_RX G
2 2 +3.3V_VTR_ADC A58 GPIO124/GPTP-OUT5/UART_RX B26 RUNPWROK
@
1 1 S
3
VTR_ADC VCC_PWRGD RUNPWROK <7>
100K_0402_5%
A25 EN_INVPWR
GPIO060/KBRST/BCM_B_INT# EN_INVPWR <28>
C736
2
C757
1 2 BC_DAT_ECE1117 B36
GPIO101/ECGP_SCLK/GANG_DATA5 PCH_SATA_MOD_EN# <15>
@ R812
R817 100K_0402_5% B3 B37
2 2 A11 VTR GPIO103/ECGP_MISO/GANG_DATA7 B38 PCIE_WAKE# SLICE_PERF_EN <65>
A26 VTR GPIO105/ECGP_MOSI A34 PCIE_WAKE# <32,36,37,38,39>
RP7 ECE5048_PWRGD
1 8 PCIE_WAKE# +3.3V_ALW B35 VTR GPIO102/BCM_C_INT#/GANG_DATA6 A35 DYN_TUR_CURRNT_SET#
1
2 7 HOST_DEBUG_RX @ PJP65 A41 VTR GPIO104 A36 DYN_TUR_CURRNT_SET# <64>
3 6 CHARGER_SMBDAT 1 2 +3.3V_ALW_VTR A52 VTR GPIO106 A40 MSDATA
4 5 VTR GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP B43 MSDATA <37>
CHARGER_SMBCLK MSCLK
GPIO117/MSCLK/V2P_COUT_HI MSCLK <37>
10U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
PAD-OPEN1x1m A45
GPIO127/A20M SIO_A20GATE <20>
10K_8P4R_5% 1 1 1 1 1 1 1 B65 FWP#
A5 NFWP
<18> SML1_SMBDATA GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA/GANG_BUSY
C781
C759
C774
C776
C777
C780
C782
B6
<18> SML1_SMBCLK GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_ERROR
A37 B57 R887 1 2 1K_0402_5%
2 2 2 2 2 2 2 <47> CLK_TP_SIO B40 GPIO110/PS2_CLK2/GPTP-IN6 GPIO156/LED0 B1 VOL_DOWN# <47>
@ R1070 1 2 0_0402_5% DEVICE_DET#
<47> DAT_TP_SIO A38 GPIO111/PS2_DAT2/GPTP-OUT6 GPIO157/LED1 A55 DEVICE_DET# <32>
CLK_KBD PS_ID
<44> CLK_KBD B41 GPIO112/PS2_CLK1A GPIO153/LED2 A1 PS_ID <56>
DAT_KBD
<44> DAT_KBD A39 GPIO113/PS2_DAT1A GPIO027/GPTP-OUT1 B28 ALW_PWRGD_3V_5V <57>
CLK_MSE
<44> CLK_MSE B42 GPIO114/PS2_CLK0A GPIO026/GPTP-IN1 B2 1 2 1.05V_A_PWRGD <59>
+5V_RUN DAT_MSE +RTC_CELL
<44> DAT_MSE PBAT_SMBDAT B59 GPIO115/PS2_DAT0A GPIO001/ECSPI_CS1 A8 VOL_MUTE# <47>
R884 1K_0402_5%
<56> PBAT_SMBDAT GPIO154/I2C1C_DATA/PS2_CLK1B GPIO015/GPTP-OUT7/GANG_DATA3 ME_SUS_PWR_ACK <16>
PBAT_SMBCLK A56 B9 1.35V_SUS_PWRGD RP15
<56> PBAT_SMBCLK GPIO155/I2C1C_CLK/PS2_DAT1B GPIO016/GPTP-IN8/GANG_DATA4 1.35V_SUS_PWRGD <58,7>
RP8 A9 VCI_IN3# 1 8
1 8 GPIO017/GPTP-OUT8 PM_APWROK <16>
CLK_KBD JTAG_TDI A51 B39 RESET_OUT# DOCK_PWR_SW# 2 7
2 7 GPIO145/I2C1K_DATA/JTAG_TDI GPIO107/NRESET_OUT RESET_OUT# <10,15,16>
DAT_KBD JTAG_TDO B55 A44 POWER_SW_IN# 3 6
3 6 CLK_MSE JTAG_CLK B56 GPIO146/I2C1K_CLK/JTAG_TDO GPIO125/GPTP-IN5 B47 PCH_RSMRST# PCH_PCIE_WAKE# <16> LAT_ON_SW# 4 5
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK GPIO126 PCH_RSMRST# <47>
4 5 DAT_MSE JTAG_TMS A53 A54 AC_PRESENT
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS GPIO151/GPTP-IN4 AC_PRESENT <16>
JTAG_RST# A57 B58 100K_0804_8P4R_5%
JTAG_RST# GPIO152/GPTP-OUT4 SIO_PWRBTN# <16>
4.7K_8P4R_5%
+3.3V_ALW DOCK_POR_RST# FAN1_TACH_FB B22 A3 DOCK_SMB_DAT
DOCK_POR_RST# A21 GPIO050/FAN_TACH1/GTACH GPIO003/I2C1A_DATA/GANG_MODE B4 DOCK_SMB_CLK DOCK_SMB_DAT <44>
<44> DOCK_POR_RST# B23 GPIO051/FAN_TACH2 GPIO004/I2C1A_CLK/GANG_START A4 DOCK_SMB_CLK <44>
RP14 LCD_SMBDAT
1 8 <20> EC_WAKE# B24 GPIO052/FAN_TACH3 GPIO005/I2C1B_DATA/BCM_B_DAT/GANG_STROBE B5
PBAT_SMBDAT A_ON LCD_SMBCLK +3.3V_ALW
<48,59> A_ON GPIO053/PWM0 GPIO006/I2C1B_CLK/BCM_B_CLK/GANG_FULL
0.1U_0402_25V6
2 7 PBAT_SMBCLK PCH_ALW_ON A23 B7 BAY_SMBDAT
<48> PCH_ALW_ON GPIO054/PWM1 GPIO012/I2C1H_DATA/I2C2D_DATA/GANG_DATA1 BAY_SMBDAT <32>
3 6 GPU_SMBDAT 1 B25 A7 BAY_SMBCLK LCD_SMBCLK 2 1
C737 <28> BIA_PWM_EC GPIO055/PWM2 GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA2 BAY_SMBCLK <32>
4 5 GPU_SMBCLK FAN1_PWM A24 B48 GPU_SMBDAT 2.2K_0402_5% R418 @
GPIO056/PWM3/GPWM GPIO130/I2C2A_DATA/BCM_C_DAT B49 GPU_SMBCLK LCD_SMBDAT 2 1
2.2K_0804_8P4R_5% GPIO131/I2C2A_CLK/BCM_C_CLK A47 CHARGER_SMBDAT 2.2K_0402_5% R420 @
2 GPIO132/I2C1G_DATA B50 CHARGER_SMBDAT <64>
+3.3V_RUN CHARGER_SMBCLK RP10
A43 GPIO140/I2C1G_CLK B52 CHARGER_SMBCLK <64>
<45> BC_CLK_ECE5048 BC_DAT_ECE5048 B45 GPIO123/BCM_A_CLK GPIO141/I2C1F_DATA/I2C2B_DATA A49 CARD_SMBDAT <39> DOCK_SMB_DAT 1 8
+3.3V_RUN <45> BC_DAT_ECE5048 A42 GPIO122/BCM_A_DAT GPIO142/I2C1F_CLK/I2C2B_CLK B53 CARD_SMBCLK <39> 2 7
C DOCK_SMB_CLK C
<45> BC_INT#_ECE5048 B20 GPIO121/BCM_A_INT# GPIO143/I2C1E_DATA A50 USH_SMBDAT <35> 3 6
BAY_SMBDAT
<64,65> ACAV_IN_NB GPIO032/BCM_E_CLK GPIO144/I2C1E_CLK USH_SMBCLK <35>
RP17 A18 BAY_SMBCLK 4 5
1 8 RUNPWROK
Place close pin A21 <16,35> SIO_SLP_S5#
B19 GPIO031/GPTP-OUT2/BCM_E_DAT A59 SYSPWR_PRES 1 2
<30> BEEP GPIO030/GPTP-IN2/BCM_E_INT# SYSPWR_PRES +3.3V_ALW2
2 7 AC_PRESENT A20 R874 1K_0402_5% 2.2K_8P4R_5%
+PCH_VCCDSW3_3 <47> BC_CLK_ECE1117 GPIO047/LSBCM_D_CLK
3 6 MSDATA <47> BC_DAT_ECE1117 BC_DAT_ECE1117 B21 A64
GPIO046/LSBCM_D_DAT VCI_OVRD_IN ACAV_IN <64,65>
4 5 PCH_RSMRST# A19 A60 DYN_TUR_CURRNT_SET# 2 1
<47> BC_INT#_ECE1117 GPIO045/LSBCM_D_INT# VCI_OUT B67 ALWON <57>
POWER_SW_IN# 100K_0402_5% R1171
10K_8P4R_5% A6 VCI_IN0# A63 DOCK_PWR_SW# THERMATRIP3# 1 2
<15,19> SIO_EXT_SMI# A27 GPIO011/nSMI/GANG_DATA0 VCI_IN1# B63 LAT_ON_SW# R866 close to U51 at least 250mils 8.2K_0402_5% R52
<20> SIO_RCIN# A28 GPIO061/LPCPD# VCI_IN2# B68 VCI_IN3#
<17,18,35,45> IRQ_SERIRQ B30 SER_IRQ VCI_IN3#
<16,35,37,38,39,45> PCH_PLTRST#_EC A29 LRESET# B51 1 2
+PECI_VREF +1.05V_RUN +3.3V_ALW
<17> CLK_PCI_MEC B31 PCI_CLK VREF_PECI A48 1 2
RP9 PECI_EC_R @ R866 0_0402_5%
<18,35,37,45> LPC_LFRAME# LFRAME# PECI_DAT PECI_EC <7>
0.1U_0402_25V6
1 8 A30 R952 43_0402_5% 1 RP16
2 7 <18,35,37,45> LPC_LAD0 B32 LAD0 1 8
EN_INVPWR BC_DAT_ECE5048
<18,35,37,45> LPC_LAD1 LAD1
C740
3 6 PCH_ALW_ON A31 B13 REM_DIODE1_N C285 1 2 2200P_0402_50V7K JTAG_RST# 2 7
4 5 <18,35,37,45> LPC_LAD2 B33 LAD2 DN1-THERM A13 3 6
DOCK_POR_RST# REM_DIODE1_P DEVICE_DET#
<18,35,37,45> LPC_LAD3 A32 LAD3 DP1-VREF_T B14 2
REM_DIODE2_N C283 1 2 2200P_0402_50V7K SYSPWR_PRES 4 5
<16,35,45> CLKRUN# A33 CLKRUN# DN2 A14 REM_DIODE2_P
100K_0804_8P4R_5%
<20> SIO_EXT_SCI# GPIO100/NEC_SCI DP2 A15 VGA_THERMDN C287 1 2 2200P_0402_50V7K 100K_0804_8P4R_5%
1 2 RESET_OUT# MEC_XTAL1 A61 DN3 B16 VGA_THERMDP
@ R843 8.2K_0402_5% MEC_XTAL2 2 1 MEC_XTAL2_R A62 XTAL1 DP3 A16 REM_DIODE4_N C286 1 2 2200P_0402_50V7K
@ R1068 0_0402_5% B62 XTAL2 DN4 B17 REM_DIODE4_P
<45> EC_32KHZ_ECE5048 GPIO160/32KHZ_OUT DP4 B15
1 2 A_ON VIN A17 VSET_5075
C283, C285, C286, C287 Place near U51 VGA_THERMDN
VSET A12 VGA_THERMDN <50>
R424 47K_0402_5% VCP VCP <64> VGA_THERMDP
VCP B34 VGA_THERMDP <50>
THERMATRIP2#
GPIO MAP 1.8 THERMTRIP2# A2 THERMATRIP3#
GPIO002/THERMTRIP3# B29 THERMATRIP3# <50>
THSEL_STRAP
VSS_ADC
GPIO024/THSEL_STRAP
VSS_RO
VR_CAP
A46 PROCHOT#_EC
32 KHz Clock
H_VSS
PROCHOT_IN#/PROCHOT_IO#
AGND
B61 V_SYS_R 1 2
V_SYS <64>
VSS
V_ISYS R392 4.7K_0402_5%
EP
MEC5075-LZY_DQFN132_11X11~D
B66
B11
B60
+VR_CAP B12
B54
B18
C1
JTAG_RST# MEC_XTAL1 1 2 MEC_XTAL2
C290 Place near U51.A48
15mil PECI_EC_R 1 2 Channel Location
27P_0402_50V8J
27P_0402_50V8J
Y6 @ C290 47P_0402_50V8J
1
1 32.768KHZ_12.5PF_Q13FC1350000 1 DP1/DN1 CPU

1U_0402_6.3V6K
4.7U_0603_6.3V6K
1
1
JTAG1 CONN@
@SHORT PADS~D
100_0402_1%
C743
C741
1 1
@
2 2 DP2/DN2 GPU V.R

C735
R836
C779
THSEL_STRAP 1 2
2 2 R1069 1K_0402_5%
DP3/DN3 VGA
2
2
ESR <2ohms
DP4/DN4 CPU V.R
2
B B
1: Channel 1 will provide Thermistor Readings
0: Channel 1 will provide Diode Readings
+3.3V_ALW R875 C744 REV +3.3V_ALW +3.3V_ALW +3.3V_ALW
+3.3V_ALW 240K 4700p ***
1K_0402_5%
10K_0402_5%
130K 4700p ***
1
49.9_0402_1%
2K_0402_5%
R875
1
8
7
6
5
R871
R872
33K 4700p ***
R864
VSET_5075 RP11
0.1U_0402_25V6
10K_8P4R_5%
4.3K 4700p ***
1.24K_0402_1%
2
1
8
7
6
5
1
100K_0402_5%
RUNPWROK
1
2K 4700p X00
2
1
2
3
4
R407
@ R850
4700P_0402_25V7K
JDEG2 BOARD_ID SYSTEM_ID FWP#
C284
L2N7002WT1G_SC-70-3
1
1
* 1K 4700p A00
1
2 JTAG_TDI 4700P_0402_25V7K D
2 1
2
2
10K_0402_5%
Q45
3 JTAG_TMS 1 2
<48,7> RUN_ON_ENABLE#
2
1
2
3
4
C742
4 JTAG_CLK RP12 G
4
C744
@ R879
5 JTAG_TDO 10K_8P4R_5% S
3
11 5 6 MSCLK 2
12 G1 6 7 MSDATA 2
1
G2 7 8 HOST_DEB_TX 1 2 HOST_DEBUG_TX FAN1_TACH_FB
8 9 @ R853 0_0402_5%
9 EC5048_TX <37,45>
10
Rest=1.24k , Tp=92 degree 10 1
EMC@
HB_A531015-SCHR21 BOARD_ID rise time is measured from 5%~68%. CHIPSET_ID for BID function C1555
CONN@ 0.047U_0402_25V7K
2
close JFAN1
EMI Request
+3.3V_ALW
Place under CPU DP4/DN4 for Skin on Q3, place Q3 close to Vcore VR choke. JFAN1
Place C8 close to the Q1 as possible REM_DIODE4_N +5V_RUN
1
1
100P_0402_50V8J
8.2K_0402_5%
REM_DIODE1_P +3.3V_RUN R30 1 2 10K_0402_5% FAN1_TACH_FB 2

2
1
100P_0402_50V8J
R51
1 R38 1 2 10K_0402_5% FAN1_PWM 3

3
1
3
@ C8
@ C16
RB751V40_SC76-2
22U_0805_6.3V6M
4
E
2 C
4
1
2 2 5
B
1 G5
D1
C7
B 6
E 2 C G6
3
1 Q1 ACES_50273-0040N-001
PMST3904_SOT323-3 2 CONN@
2
REM_DIODE1_N REM_DIODE4_P THERMATRIP2#
A Q3 A
+VCCIO_OUT
PMST3904_SOT323-3
PMST3904_SOT323-3
0.1U_0402_25V6
1
C
DP2/DN2 for GPU V.R on Q2, place Q2 close to GPU V.R and C9 close to Q2 1 2 2 1
Q4
C18
R55 2.2K_0402_5% B
REM_DIODE2_P E When 5075 solution use PWM FAN
3
2
100P_0402_50V8J
1
1
@ C9
C
2
B
2 <7> H_THERMTRIP#
E
3
Q2
PMST3904_SOT323-3
REM_DIODE2_N
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT MEC5075
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Date: Monday, May 12, 2014 Sheet 46 of 71
5 4 3 2 1
5 4 3 2 1
Touch Pad +3.3V_TP
+3.3V_RUN
@ R1161
1 2
0_0603_5%
Media Board
+3.3V_ALW 1 2
+3.3V_TP @ R1162 0_0603_5% +5V_ALW
JTP1
4.7K_0402_5%
4.7K_0402_5%
1
1
1
D TP_CLK 2 D
2
R903
R902
TP_DATA 3 1
4 3
5 4 @ C1002
+3.3V_TP
PS2_DAT_TS 6 5 9
Close to JMDIA1
0.1U_0402_25V6
2
PS2_CLK_TS 7 6 G1 10 2
1 2 TP_DATA 8 7 G2 JMDIA1
<46> DAT_TP_SIO 8
@ R3735 0_0603_5% 1
1 2 TP_CLK 2 1
<46> CLK_TP_SIO 2
@ R3736 0_0603_5% HB_A520820-SCHR22 3
<46> VOL_MUTE# 3
CONN@ 4
<46> VOL_DOWN# 4
5
<46> VOL_UP# 5
6
+3.3V_TP 7 6
8 G1
G2
0.1U_0402_25V6
HB_A520620-SCHR22
1 CONN@
C755
2 @
Place close to JTP1
1 2
C
+5V_ALW RSMRST# +3.3V_ALW_PCH +3.3V_ALW
@ R1623 0_0402_5%
+3.3V_ALW_PCH
C
+3.3V_ALW
Keyboard Pitch: 1.0
10K_0402_5%
10K_0402_5%
8.2K_0402_5%
1
2
33_0402_5%
@ R1622
@ R1624
@ C288
R1629
R1630
1 2 JKB1
1
0.1U_0402_25V6 <20> KB_DET# PS2_CLK_TS 2 1
2
5
PS2_DAT_TS 3
2
1
U8 +3.3V_ALW +5V_RUN 4 3
VCC
+3.3V_ALW 4
<46> PCH_RSMRST# 1 +5V_RUN 5
IN B 5
0.1U_0402_25V6
0.1U_0402_25V6
1 4 PCH_RSMRST#_Q <15,16> 6
VCC 3 RSMRST# 2 OUT Y <46> BC_INT#_ECE1117 7 6
GND
RESET# IN A 1 1 <46> BC_DAT_ECE1117 7
0.01U_0402_16V7K
C756
C758
2 8
GND 8
10K_0402_5%
1 U9 9
<46> BC_CLK_ECE1117 9
2
10
3
2 2 10
C289
R1636
RT9818A-44GU3_SC70-3 NL17SZ08DFT2G_SC70-5 @ @
11
2 GND 12
GND
1
HB_A091020-SAHR22
CONN@
Place close to JKB1
B B
SNIFFER /Hall SENSOR BOARD
JSF1
1
2 1
+3.3V_ALW <24,45> LID_CL# 3 2
+3.3V_ALW 3
4
<45> WIRELESS_ON#/OFF 4
0.1U_0402_25V6
5 7
5 G1
@ C1184
1 6 8
6 G2
HB_A090620-SAHR21
2 CONN@
WIRELESS_ON/OFF#:
LOW: ON (Default)
Close to JSF1 HIGH: OFF
+5V_ALW (PITCH 0.5) Right side LED JLED1

1
1
0.1U_0402_25V6
BATT_YELLOW# 2
<24> BATT_YELLOW# 2
1 BATT_WHITE# 3
<24> BATT_WHITE# 3
C1004
SATA_LED 4
<24> SATA_LED 4
WLAN_LED 5
<24> WLAN_LED 5
6
@ 2 7 6
8 G1
A G2 A
HB_A520620-SCHR22
Close to JLED2 CONN@
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Int KB/TP/BT/RSMRST
1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW_PCH/+3.3V_RUN Source
SI4164DY
VDS RDS(on) ID(A)
D +3.3V_ALW_PCH 30 0.0032ohm at VGS=10V 30A D
@ C452 30 0.0039ohm at VGS=4.5V 26.3A
U146 10U_0603_6.3V6M
1 14 1 2
+3.3V_ALW VIN1 VOUT1
2 13
VIN1 VOUT1
3 12 1 2
<46> PCH_ALW_ON ON1 CT1 C451 470P_0402_50V7K
+5V_ALW
4
VBIAS GND
11
+1.05V_RUN Source
5 10 1 2
<32,39,45,48,60> RUN_ON ON2 CT2 C454 2200P_0402_50V7K
6 9
7 VIN2 VOUT2 8 +3.3V_ALW2 +PWR_SRC
VIN2 VOUT2 +3.3V_RUN
1 +1.05V_M Q63
15 AO4354_SOIC-8 +1.05V_RUN
GPAD @ C453 8 1
1
TPS22966DPUR_SON14_2X3 10U_0603_6.3V6M 7 2
1
2
10U_0603_6.3V6M
R930 6 3
1
R909 330K_0402_5% 5 1
C772
100K_0402_5% R931
20K_0402_5%
4
1.05V_RUN_ENABLE
2
2
2
3
1M_0402_5%
100P_0402_50V8J
1
Q52B
R1611
1
RUN_ON_ENABLE# 5
<46,48,7> RUN_ON_ENABLE#
C773
6
2
2
Q52A
C C
2
<32,39,45,48,60> RUN_ON
1
+3.3V_M/+3.3V_SUS source
+3.3V_M
Discharge Circuit U36
@ C439
10U_0603_6.3V6M
1 14 1 2
+3.3V_ALW VIN1 VOUT1
2 13
+1.35V_MEM VIN1 VOUT1
3 12 1 2
B <46,59> A_ON ON1 CT1 B
+1.05V_RUN +0.675V_DDR_VTT C437 470P_0402_50V7K
4 11
+5V_ALW VBIAS GND
1
1
@ R926 1 2 5 10 1 2
<45,58> SUS_ON ON2 CT2
@ R925 220_0402_5% @ R927 @ R1607 0_0402_5% C435 470P_0402_50V7K
39_0402_5% 22_0603_5% 6 9
7 VIN2 VOUT2 8
+3.3V_SUS
2
VIN2 VOUT2
+1.35V_MEM_CHG
2
15
+1.05V_RUN_CHG
GPAD 1
1 2
<45> USH_PWR_ON
+DDR_CHG
@ R1620 0_0402_5% TPS22966DPUR_SON14_2X3 @ C443

10U_0603_6.3V6M
2
<46,48,7> RUN_ON_ENABLE#
L2N7002WT1G_SC-70-3
L2N7002WT1G_SC-70-3
1
D D
L2N7002WT1G_SC-70-3
@ Q72
Q70 @
RUN_ON_ENABLE# 2 2
1
D
@ Q71
G G
S 2 S
3
G
S
3
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, POWER CONTROL
LA-9934P
5 4 3 2 1
5 4 3 2 1
UV1A
UV1F
PEG_CTX_GRX_P[0..7]
<6> PEG_CTX_GRX_P[0..7]
PEG_CTX_GRX_N[0..7]
<6> PEG_CTX_GRX_N[0..7]
PEG_CTX_GRX_P0 AF30 AH30 PEG_CRX_GTX_C_P0 AB11
PEG_CRX_GTX_P[0..7] PEG_CTX_GRX_N0 AE31 PCIE_RX0P PCIE_TX0P AG31 PEG_CRX_GTX_C_N0 NC_VARY_BL AB12
<6> PEG_CRX_GTX_P[0..7] PCIE_RX0N PCIE_TX0N NC_DIGON
PEG_CRX_GTX_N[0..7]
<6> PEG_CRX_GTX_N[0..7]
PEG_CTX_GRX_P1 AE29 AG29 PEG_CRX_GTX_C_P1
PEG_CTX_GRX_N1 AD28 PCIE_RX1P PCIE_TX1P AF28 PEG_CRX_GTX_C_N1
PCIE_RX1N PCIE_TX1N AL15
D NC_UPHYAB_TMDPA_TX0N AK14 D
PEG_CTX_GRX_P2 AD30 AF27 PEG_CRX_GTX_C_P2 NC_UPHYAB_TMDPA_TX0P
PEG_CRX_GTX_P0 CV1 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P0 PEG_CTX_GRX_N2 AC31 PCIE_RX2P PCIE_TX2P AF26 PEG_CRX_GTX_C_N2 AH16
PEG_CRX_GTX_N0 CV2 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N0 PCIE_RX2N PCIE_TX2N NC_UPHYAB_TMDPA_TX1N AJ15
NC_UPHYAB_TMDPA_TX1P
PEG_CRX_GTX_P1 CV4 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P1 PEG_CTX_GRX_P3 AC29 AD27 PEG_CRX_GTX_C_P3 AL17
PEG_CRX_GTX_N1 CV3 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N1 PEG_CTX_GRX_N3 AB28 PCIE_RX3P PCIE_TX3P AD26 PEG_CRX_GTX_C_N3 NC_UPHYAB_TMDPA_TX2N AK16
PCIE_RX3N PCIE_TX3N NC_UPHYAB_TMDPA_TX2P
PEG_CRX_GTX_P2 CV5 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P2 AH18
PEG_CRX_GTX_N2 CV6 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N2 PEG_CTX_GRX_P4 AB30 AC25 PEG_CRX_GTX_C_P4 NC_UPHYAB_TMDPA_TX3N AJ17
PEG_CTX_GRX_N4 AA31 PCIE_RX4P PCIE_TX4P AB25 PEG_CRX_GTX_C_N4 NC_UPHYAB_TMDPA_TX3P
PEG_CRX_GTX_P3 CV7 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P3 PCIE_RX4N PCIE_TX4N AL19
PEG_CRX_GTX_N3 CV8 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N3 NC_TXOUT_L3P AK18
PEG_CTX_GRX_P5 AA29 Y23 PEG_CRX_GTX_C_P5 NC_TXOUT_L3N
PEG_CRX_GTX_P4 CV9 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P4 PEG_CTX_GRX_N5 Y28 PCIE_RX5P PCIE_TX5P Y24 PEG_CRX_GTX_C_N5
PEG_CRX_GTX_N4 CV10 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N4 PCIE_RX5N PCIE_TX5N TMDP
PEG_CRX_GTX_P5 CV11 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P5 PEG_CTX_GRX_P6 Y30 AB27 PEG_CRX_GTX_C_P6 AH20

PEG_CRX_GTX_N5 CV12 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N5 PEG_CTX_GRX_N6 W31 PCIE_RX6P PCIE_TX6P AB26 PEG_CRX_GTX_C_N6 NC_UPHYAB_TMDPB_TX0N AJ19
PCIE_RX6N PCIE_TX6N NC_UPHYAB_TMDPB_TX0P
PEG_CRX_GTX_P6 CV14 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P6 AL21
PEG_CRX_GTX_N6 CV15 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N6 PEG_CTX_GRX_P7 W29 Y27 PEG_CRX_GTX_C_P7 NC_UPHYAB_TMDPB_TX1N AK20
PEG_CTX_GRX_N7 V28 PCIE_RX7P PCIE_TX7P Y26 PEG_CRX_GTX_C_N7 NC_UPHYAB_TMDPB_TX1P
PEG_CRX_GTX_P7 CV16 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P7 PCIE_RX7N PCIE_TX7N AH22
PEG_CRX_GTX_N7 CV17 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N7 NC_UPHYAB_TMDPB_TX2N AJ21
V30 W24 NC_UPHYAB_TMDPB_TX2P
U31 NC#V30 NC#W24 W23 AL23
NC#U31 NC#W23 NC_UPHYAB_TMDPB_TX3N AK22
NC_UPHYAB_TMDPB_TX3P
U29 V27 AK24
T28 NC#U29 NC#V27 U26 NC_TXOUT_U3P AJ23
NC#T28 NC#U26 NC_TXOUT_U3N
PCI EXPRESS INTERFACE

C C
T30 U24
R31 NC#T30 NC#U24 U23
NC#R31 NC#U23 216-0841009-A0-SUN_FCBGA631~D
R29 T26
P28 NC#R29 NC#T26 T27
NC#P28 NC#T27
P30 T24
N31 NC#P30 NC#T24 T23
NC#N31 NC#T23
N29 P27
M28 NC#N29 NC#P27 P26
NC#M28 NC#P26
M30 P24
L31 NC#M30 NC#P24 P23
NC#L31 NC#P23
L29 M27
K30 NC#L29 NC#M27 N26
NC#K30 NC#N26
CLOCK
AK30
<17> CLK_PCIE_VGA AK32 PCIE_REFCLKP
<17> CLK_PCIE_VGA# PCIE_REFCLKN
CALIBRATION
B Y22 1 2 B
PCIE_CALR_TX +VGA_PCIE
RV296 1.69K_0402_1%
1 2 N10 AA22 1 2 +VGA_PCIE
RV25 1K_0402_5% TEST_PG PCIE_CALR_RX RV298 1K_0402_1%
DGPU_PEX_RST 1 2 DGPU_PEX_RST_R AL27

@ RV18 0_0402_5% PERSTB
216-0841009-A0-SUN_FCBGA631~D
don't connect to PCH
+3.3V_ALW
+3.3V_RUN
0.1U_0402_25V6
1
1
+3.3V_RUN_GFX
@ CV87
RV33
1
100K_0402_5%
2 RV29
2.2K_0402_5%
2
1
P
<16> DGPU_HOLD_RST#
2
A B 4 DGPU_PEX_RST A
O DGPU_PEX_RST <50>
<16> PLTRST_GPU# 2
A
G
74AHC1G09GW_TSSOP5
3
UV14
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SUN-PCIE
1.0
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN_GFX
UV1B
@ RPV1
GPU_JTAG_TDO 4 5
GPU_JTAG_TDI 3 6 AF2
GPU_JTAG_TMS 2 7 NC#AF2 AF4
GPU_JTAG_TRSTB 1 8 NC#AF4
N9 AG3
10K_8P4R_5% L9 DBG_DATA16 NC#AG3 AG5
AE9 DBG_DATA15 NC#AG5
DPA
GPU_JTAG_TCK RV88 2 1 10K_0402_5% Y11 DBG_DATA14 AH3
AE8 DBG_DATA13 NC#AH3 AH1
Need to discuss with ME place these parts in door.(bottom) AD9 DBG_DATA12 NC#AH1
AC10 DBG_DATA11 AK3
AD7 DBG_DATA10 NC#AK3 AK1
D D
AC8 DBG_DATA9 NC#AK1
DVO
AC7 DBG_DATA8 AK5
AB9 DBG_DATA7 NC#AK5 AM3
AB8 DBG_DATA6 NC#AM3
AB7 DBG_DATA5 AK6
AB4 DBG_DATA4 NC#AK6 AM5
AB2 DBG_DATA3 NC#AM5
DPB
Y8 DBG_DATA2 AJ7
Y7 DBG_DATA1 NC#AJ7 AH6
DBG_DATA0 NC#AH6
AK8
+3.3V_RUN_GFX NC#AK8 AL7
NC#AL7
1 2 GPU_HOT# W6
RV103 4.7K_0402_5% V6 NC#W6
NC#V6 V4
AC6 NC#V4 U5
AC5 NC#AC5 NC#U5
NC#AC6 W3
AA5 NC#W3 V2
AA6 NC#AA5 NC#V2
DPC
NC#AA6 Y4 GPU_PWR_LEVEL 1 2 GPU_HOT#
NC#Y4 <45> GPU_PWR_LEVEL GPU_HOT# <62>
W5 @ RV76 0_0402_5%
NC#W5
U1 AA3
W1 NC#U1 NC#AA3 Y2
U3 NC#W1 NC#Y2
NC#U3 +VCCIO_OUT
PMST3904_SOT323-3
Y6 J8
NC#Y6 NC#J8
0.1U_0402_25V6
AA1
NC#AA1
1
C
1 2 2 1
QV8
CV358
@ RV78 2.2K_0402_5% B
E
3
I2C @
2
@
R1
R3 SCL
SDA
<46,61,64,65,7> H_PROCHOT#
AM26
NC_R AK26
GPU_PSI# U6 GENERAL PURPOSE I/O NC_AVSSN
<62> GPU_PSI# GPIO_0
U10 AL25
T10 NC_GPIO_1 NC_G AJ25
C
U8 NC_GPIO_2
SMBDATA
NC_AVSSN Hynix VRAM: RV241 =8.45k C
U7 AH24
GPU_HOT# T9
T8
SMBCLK
GPIO_5_AC_BATT
NC_B
NC_AVSSN
AG25
* Samsung VRAM: RV241 =4.53Kohm
T7 GPIO_6 DAC1 AH26
P10 NC_GPIO_7 NC_HSYNC AJ27
T105 GPIO_8_ROMSO NC_VSYNC
T106 P4
P2 GPIO_9_ROMSI +1.8V_RUN_GFX +1.8V_RUN_GFX +1.8V_RUN_GFX +1.8V_RUN_GFX
<62> GPU_VID_0 GPIO_10_ROMSCK
N6 AD22
N5 NC_GPIO_11 NC_RSET
8.45K_0402_1%
8.45K_0402_1%
NC_GPIO_12
1
N3 AG24
8.45K_0402_1%
4.53K_0402_1%
NC_GPIO_13 NC_AVDD
1
RV244
RV237
Y9 AE22
NC_GPIO_14 NC_AVSSQ
RV239
RV241
N1
VRAM@
<62> GPU_VID_2 GPIO_15_PWRCNTL_0
M4 AE23
<62> GPU_VID_1 GPIO_16 NC_VDD1DI
GPU_THERMAL_INT R6 AD23
2
W10 GPIO_17_THERMAL_INT NC_VSS1DI @
2
THERMTRIP_VGA M2 NC_GPIO_18
GPIO_19_CTF FutureASIC/SEYMOUR/PARK
P8 AM12 PS_0 PS_1 PS_2 PS_3
<62> GPU_VID_3 GPIO_20_PWRCNTL_1 CEC_1
P7
<62> GPU_VID_4 GPIO_21
N8
0.082U_0402_16V7K
0.68U_0402_10V
0.68U_0402_10V
0.68U_0402_10V
2K_0402_1%
T108
2K_0402_1%
2K_0402_1%
GPIO_22_ROMCSB
1
AK10 AK12
4.75K_0402_1%
GPIO_29 NC_SVI2#AK12 1 1 1 1
CV341
AM10 AL11
RV243
CV342
RV238
CV357
CV340
RV242
RV240
GFX_CLK_REQ# 1 2 GFX_CLK_REQ#_R N7 GPIO_30 NC_SVI2#AL11 AJ11
<17> GFX_CLK_REQ# CLKREQB NC_SVI2#AJ11
@ RV52 0_0402_5%
GPU_JTAG_TRSTB L6 @ 2 @ 2 2 @ 2
2
GPU_JTAG_TDI L5 JTAG_TRSTB
confirm with AMD GPU_JTAG_TCK L3 JTAG_TDI
JTAG_TCK
GPU_JTAG_TMS L1 AL13 T151
+3.3V_RUN_GFX GPU_JTAG_TDO K4 JTAG_TMS NC_GENLK_CLK AJ13
JTAG_TDO NC_GENLK_VSYNC T152
TESTEN K7
AF24 TESTEN
NC#AF24 AG13
NC_SWAPLOCKA
2
AH12
NC_SWAPLOCKB
@
RV41 AB13
5.11K_0402_1% W8 NC_GENERICA
W9 NC_GENERICB
W7 NC_GENERICC AC19 PS_0
1
TESTEN AD10 NC_GENERICD PS_0

AJ9 NC_GENERICE_HPD4 AD19 PS_1
NC#AJ9 PS_1
1
AL9
RV49 DBG_CNTL0 AE17 PS_2
1K_0402_5% AC14 PS_2
1 2 PX_EN AB16 NC_HPD1 AE20 PS_3
@ RV48 0_0402_5% PX_EN PS_3
2
B B
AE19
AC16 TS_A
NC_DBG_VREFG
DDC/AUX
AE6 +3.3V_RUN_GFX
PLL/CLOCK NC_DDC1CLK AE5
NC_DDC1DATA
AD2
NC_AUX1P AD4
NC_AUX1N
AC11
NC_DDC2CLK
1
AC13
NC_DDC2DATA
@
RV57
XTALIN AM28 AD13 20K_0402_5%
XTALOUT_R AK28 XTALIN NC_AUX2P AD11
XTALOUT NC_AUX2N
3
E
2
B
AC22 AD20 QV4 2
AB22 XO_IN NC#AD20 AC20 MMBT3906WT1G_SC70-3
XO_IN2 NC#AC20 C
1
AE16
NC#AE16 AD16 RV59 THERMATRIP3# <46>
NC#AD16
20K_0402_5%
PMST3904_SOT323-3
0.1U_0402_25V6
SEYMOUR/FutureASIC AC1
NC_DDCVGACLK
1
VGA_THERMDP T4 AC3 RV58 C 1
<46> VGA_THERMDP
2
VGA_THERMDN T2 DPLUS THERMAL NC_DDCVGADATA 1 2 2
<46> VGA_THERMDN DMINUS
QV7
CV57
B
1
DGPU_PEX_RST 1 2 2.2K_0402_5% E
<49> DGPU_PEX_RST
3
2
0.1U_0402_25V6
TS_FDO R5 D71 RB751V40_SC76-2 RV56
1K_0402_5%
GPIO28_FDO
2
+1.8V_RUN_GFX 1 2 +TSVDD AD17 20K_0402_5% 1
TSVDD
RV60
LV16 BLM15BD121SN1D_0402 AC17
TSVSS
PMST3904_SOT323-3
CV53 @
CV98
CV92
CV93
1U_0402_6.3V6K
10U_0603_6.3V6M
0.1U_0402_25V6
1
On-die thermal sensor power. C
1 1 1 20mil 2
QV3
GPU_THERMAL_INT 1 2 1 2 2
TSVDD : 1.8V @ 13mA
1
216-0841009-A0-SUN_FCBGA631~D RV53 47K_0402_5% RV55 47K_0402_5% B
0.01U_0402_16V7K
E
3
2 2 2
100K_0402_5%
THERMTRIP_VGA 1 2
2
RV47 47K_0402_5% 1
CV52
RV61
2 1
TS_FDO XTALOUT 1 2 XTALOUT_R RV104 10K_0402_5% 2
1
@ RV125 0_0402_5%
2
A A
RV111
10K_0402_5%
RV100
XTALIN
1
1M_0402_5%
1 2
RV77 @ 0_0402_5%
3 1
4 2
G2
1
CV94 G1 CV95
6.8P_0402_50V8C YV1 6.8P_0402_50V8C
2
PROPRIETARY NOTE:
Title
27MHZ_10PF_7V27000023 THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SUN-GPIO,HDMI,DP,DAC
1.0
5 4 3 2 1
5 4 3 2 1
+1.8V_RUN_GFX
VDDR1 @ 1500mA, GDDR5 1125MHz (PCIE_PVDD : 1.8V @ 100mA)
+1.35V_MEM_GFX
10U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
CV26
CV13
CV18
CV19
CV20
CV21
CV22
CV23
CV25
CV24
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1
CV68
CV67
CV66
2 2 2 2 2 2 2 2 2 2 2 2 2
D D
UV1D
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
20mil
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
AM30
40mil MEM I/O PCIE_PVDD
PCIE
CV163
CV164
CV165
CV166
CV167
CV56
CV58
1 1 CV59 1 1 1 1 1 1 H13 AB23

H16 VDDR1 NC#AB23 AC23
H19 VDDR1 NC#AC23 AD24 +VGA_PCIE
J10 VDDR1 NC#AD24 AE24
2 2 2 2 2 2 2 2 VDDR1 NC#AE24 PCIE_VDDC : 0.95V @
J23 AE25
J24 VDDR1 NC#AE25 AE26
2.5A max. current is 4.0A
J9 VDDR1 NC#AE26 AF25
VDDR1 NC#AF25
10U_0603_6.3V6M
10U_0603_6.3V6M
K10 AG26
VDDR1 NC#AG26
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
K23
K24 VDDR1 160mil
VDDR1 1 1 1 1 1 1 1 1 1
CV70
CV76
CV75
CV74
CV73
CV71
CV69
CV77
CV72
K9 L23
+1.8V_RUN_GFX +VDDC_CT L11 VDDR1 PCIE_VDDC L24
LV19 L12 VDDR1 PCIE_VDDC L25
1 2 L13 VDDR1 PCIE_VDDC L26 2 2 2 2 2 2 2 2 2
(1.8V@13mA VDD_CT) VDDR1 PCIE_VDDC
0.1U_0402_25V6
BLM15BD121SN1D_0402 L20 M22
VDDR1 PCIE_VDDC
10U_0603_6.3V6M
CV60
CV55
CV54
1U_0402_6.3V6K
L21 N22
L22 VDDR1 PCIE_VDDC N23
1 1 1 VDDR1 PCIE_VDDC N24
PCIE_VDDC R22
PCIE_VDDC T22
2 2 2 LEVEL PCIE_VDDC U22
TRANSLATION PCIE_VDDC V22
20mil AA20 PCIE_VDDC +GPU_CORE
AA21 VDD_CT
AB20 VDD_CT AA15
C AB21 VDD_CT CORE VDDC N15 C
VDD_CT VDDC N17
+3.3V_RUN_GFX VDDC R13
LV30 I/O VDDC R16
(3.3V@25mA VDDR3) 20mil VDDC
1 2 +3.3V_RUN_GFX_VDDR3 AA17 R18
VDDR3 VDDC
0.1U_0402_25V6
BLM15BD121SN1D_0402 AA18 Y21

VDDR3 VDDC
CV61
CV49
CV62
1U_0402_6.3V6K
1U_0402_6.3V6K
AB17 T12
AB18 VDDR3 VDDC T15
1 1 1 VDDR3 VDDC T17
V12 VDDC T20
Y12 NC_VDDR4 VDDC U13
2 2 2 U12 NC_VDDR4 VDDC U16
NC_VDDR4 VDDC U18
VDDC V21
VDDC V15
VDDC V17
VDDC V20
VDDC
POWER
Y13
VDDC Y16
VDDC Y18
VDDC AA12
VDDC M11
VDDC N12
VDDC U11
VDDC
PLL
+VGA_PCIE
60mil
R21
+1.8V_RUN_GFX BIF_VDDC U21
BIF_VDDC (BIF_VDDC : 0.95V @ 1.4A)
B B
1.8V @ 90mA 20mil
2 1 +1.8V_MPLL_PVDD L8
MPLL_PVDD +GPU_CORE
0.1U_0402_25V6
LV17 BLM15BD221SN1D_0402
10U_0603_6.3V6M
CV216
CV219
CV215
1U_0402_6.3V6K
ISOLATED
only change CPN 1 1 1 CORE I/O
M13
240mil VDDC : @ 5A)
20mil H7 VDDCI M15
SPLL_PVDD VDDCI
10U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
M16
2 2 2 VDDCI
CV78
CV79
CV80
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
M17
VDDCI M18
VDDCI 1 1 1 1 1 1 1
CV81
CV82
CV83
CV84
M20
20mil H8 VDDCI M21
+1.8V_RUN_GFX SPLL_VDDC VDDCI N20
J7 VDDCI 2 2 2 2 2 2 2
1.8V @ 75mA SPLL_PVSS
2 1 +1.8V_SPLL_PVDD
0.1U_0402_25V6
10U_0603_6.3V6M
CV221
CV222
CV220
1U_0402_6.3V6K
1 1 1 216-0841009-A0-SUN_FCBGA631~D
2 2 2 check if can murge VDDC&VDDCI
+VGA_PCIE
0.95V @ 100mA
2 1 +VGA_PCIE_SPLL_VDDC
0.1U_0402_25V6
10U_0603_6.3V6M
CV224
CV225
CV223
1U_0402_6.3V6K
A
1 1 1 A
2 2 2
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SUN-Power
1.0
5 4 3 2 1
5 4 3 2 1
UV1E
AA27 A3
AB24 GND GND A30
AB32 GND GND AA13
AC24 GND GND AA16
AC26 GND GND AB10
AC27 GND GND AB15
+1.8V_RUN_GFX AD25 GND GND AB6
AD32 GND GND AC9
AE27 GND GND AD6
1.8V @20mA GND GND
D AF32 AD8 D
GND GND
0.1U_0402_25V6
AG27 AE7
GND GND
10U_0603_6.3V6M
CV201
CV203
CV198
1U_0402_6.3V6K
AH32 AG12
K28 GND GND AH10
1 1 1 GND GND
K32 AH28
L27 GND GND B10
M32 GND GND B12
2 2 2 UV1G N25 GND GND B14
N27 GND GND B16
P25 GND GND B18
20mil DP POWER NC/DP POWER
P32 GND GND B20
AG15 AE11 R27 GND GND B22
AG16 NC_DP_VDDR NC#AE11 AF11 T25 GND GND B24
AF16 NC_DP_VDDR NC#AF11 AE13 T32 GND GND B26
AG17 NC_DP_VDDR NC#AE13 AF13 U25 GND GND B6
AG18 NC_DP_VDDR NC#AF13 AG8 U27 GND GND B8
AG19 NC_DP_VDDR NC#AG8 AG10 V32 GND GND C1
AF14 NC_DP_VDDR NC#AG10 W25 GND GND C32
DP_VDDR W26 GND GND E28
W27 GND GND F10
Y25 GND GND F12
Y32 GND GND F14
AG20 AF6 GND GND F16
+VGA_PCIE AG21 NC_DP_VDDC NC#AF6 AF7 GND F18
AF22 NC_DP_VDDC NC#AF7 AF8 GND F2
20mil AG22 NC_DP_VDDC NC#AF8 AF9 GND F20
AD14 NC_DP_VDDC NC#AF9 M6 GND F22
0.95V @16 mA DP_VDDC GND#56 GND
0.1U_0402_25V6
N13 F24
GND#57 GND
10U_0603_6.3V6M
CV202
CV204
CV199
1U_0402_6.3V6K
N16 F26
N18 GND#58 GND F6
1 1 1 GND#59 GND
AG14 AE1 N21 GND F8
AH14 NC_DP_VSSR NC#AE1 AE3 P6 GND#60 GND G10
C AM14 NC_DP_VSSR NC#AE3 AG1 P9 GND#61 GND G27 C
2 2 2 AM16 NC_DP_VSSR NC#AG1 AG6 R12 GND#62 GND G31
AM18 NC_DP_VSSR NC#AG6 AH5 R15 GND#63 GND G8
AF23 NC_DP_VSSR NC#AH5 AF10 R17 GND#64 GND H14
AG23 NC_DP_VSSR NC#AF10 AG9 R20 GND#65 GND H17
AM20 NC_DP_VSSR NC#AG9 AH8 T13 GND#66 GND H2
AM22 NC_DP_VSSR NC#AH8 AM6 T16 GND#67 GND H20
AM24 NC_DP_VSSR NC#AM6 AM8 T18 GND#68 GND H6
AF19 NC_DP_VSSR NC#AM8 AG7 T21 GND#69 GND J27
AF20 NC_DP_VSSR NC#AG7 AG11 T6 GND#70 GND J31
AE14 NC_DP_VSSR NC#AG11 U15 GND#71 GND K11
DP_VSSR U17 GND#72 GND K2
U20 GND#73 GND K22
U9 GND#74 GND K6
AF17 AE10 V13 GND#75 GND
NC_UPHYAB_DP_CALR NC#AE10 V16 GND#76
V18 GND#77
Y10 GND#78
216-0841009-A0-SUN_FCBGA631~D Y15 GND#79 if need ?
Y17 GND#80
Y20 GND#81
R11 GND#82 A32
GND#83 VSS_MECH T131
T11 AM1
AA11 AM32
M12
N11 GND#86
V11 GND#87
GND#88
216-0841009-A0-SUN_FCBGA631~D
B B
AMD recommended setting

MLPS Bit
strap R_PU R_PD C
PS0: 11001 RV243=8.45K RV201=2K CV335=NC
PS1: 11000 RV237=NC RV238=4.75K CV329=NC
A
PS2: 00000 RV239=NC RV240=4.75K CV331=0.68u A
PS3: 11000 RV241=NC RV242=4.75K CV333=NC
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SUN-DP Power,GND
1.0
5 4 3 2 1
5 4 3 2 1
+1.35V_MEM_GFX
CLKA0 1 2
RV187 121_0402_1%
CLKA0# 1 2
RV188 121_0402_1%
CLKA1 1 2
RV189 121_0402_1%
DQA0_0[0..31] CLKA1# 1 2
DQA0_[0..31] <54>
RV190 121_0402_1%
DQA1_[0..31]
DQA1_[0..31] <55>
MAA0_[0..8]
MAA0_[0..8] <54>
D
MAA1_[0..8] D
MAA1_[0..8] <55>
EDCA0_[0..3] UV1C
EDCA0_[0..3] <54>
EDCA1_[0..3] GDDR5/DDR3 GDDR5/DDR3
EDCA1_[0..3] <55> K27 K17
DQA0_0 MAA0_0
DDBIA0_[0..3] DQA0_1 J29 DQA0_0 MAA0_0 J20 MAA0_1
DDBIA0_[0..3] <54> H30 DQA0_1 MAA0_1 H23
DQA0_2 MAA0_2
DDBIA1_[0..3] DQA0_3 H32 DQA0_2 MAA0_2 G23 MAA0_3
DDBIA1_[0..3] <55> G29 DQA0_3 MAA0_3 G24
DQA0_4 MAA0_4
DQA0_5 F28 DQA0_4 MAA0_4 H24 MAA0_5
DQA0_6 F32 DQA0_5 MAA0_5 J19 MAA0_6
DQA0_7 F30 DQA0_6 MAA0_6 K19 MAA0_7
DQA0_8 C30 DQA0_7 MAA0_7 G20 MAA0_8
DQA0_9 F27 DQA0_8 MAA0_8 L17
DQA0_10 A28 DQA0_9
DQA0_10
MAA0_9 +3.3V_RUN_GFX Source
DQA0_11 C28 J14 MAA1_0
DQA0_12 E27 DQA0_11 MAA1_0 K14 MAA1_1
DQA0_13 G26 DQA0_12 MAA1_1 J11 MAA1_2
Place close to UV1 DQA0_14 D26 DQA0_13 MAA1_2 J13 MAA1_3
DQA0_15 F25 DQA0_14 MAA1_3 H11 MAA1_4
DQA0_16 A25 DQA0_15 MAA1_4 G11 MAA1_5
+1.35V_MEM_GFX DQA0_17 C25 DQA0_16 MAA1_5 J16 MAA1_6 +3.3V_ALW +3.3V_RUN_GFX
DQA0_18 E25 DQA0_17 MAA1_6 L15 MAA1_7 QV12
DQA0_19 D24 DQA0_18 MAA1_7 G14 MAA1_8 DMG2301U-7_SOT23-3
DQA0_19 MAA1_8
1
DQA0_20 E23 L16

DQA0_20 MAA1_9
D
RV145 DQA0_21 F23 3 1
40.2_0402_1% DQA0_22 D22 DQA0_21 E32 WCKA0_0
DQA0_23 F21 DQA0_22 WCKA0_0 E30 WCKA0B_0 WCKA0_0 <54>
MEMORY INTERFACE
DQA0_24 E21 DQA0_23 WCKA0B_0 A21 WCKA0_1 WCKA0B_0 <54>
G
1
2
2
DQA0_25 D20 DQA0_24 WCKA0_1 C21 WCKA0B_1 WCKA0_1 <54>
+VDD_MEM15_REFDA DQA0_26 F19 DQA0_25 WCKA0B_1 E13 WCKA1_0 WCKA0B_1 <54> DGPU_PWR_EN#_Q CV423
DQA0_27 A19 DQA0_26 WCKA1_0 D12 WCKA1B_0 WCKA1_0 <55>
DQA0_27 WCKA1B_0 WCKA1B_0 <55> 10U_0603_6.3V6M
DQA0_28 D18 E3 WCKA1_1 2
1 DQA0_28 WCKA1_1 WCKA1_1 <55> 1
1
470P_0402_50V7K
@ CV411
CV275 DQA0_29 F17 F4 WCKA1B_1
RV146 1U_0603_10V6K DQA0_30 A17 DQA0_29 WCKA1B_1 WCKA1B_1 <55>
100_0402_1% DQA0_31 C17 DQA0_30 H28 EDCA0_0
2 DQA1_0 E17 DQA0_31 EDCA0_0 C27 EDCA0_1 2
C DQA1_0 EDCA0_1 C
DQA1_1 D16 A23 EDCA0_2
2
DQA1_2 F15 DQA1_1 EDCA0_2 E19 EDCA0_3

DQA1_3 A15 DQA1_2 EDCA0_3 E15 EDCA1_0
DQA1_4 D14 DQA1_3 EDCA1_0 D10 EDCA1_1
DQA1_5 F13 DQA1_4 EDCA1_1 D6 EDCA1_2
DQA1_6 A13 DQA1_5 EDCA1_2 G5 EDCA1_3
DQA1_7 C13 DQA1_6 EDCA1_3
+1.35V_MEM_GFX DQA1_8 E11 DQA1_7 H27 DDBIA0_0
DQA1_9 A11 DQA1_8 DDBIA0_0 A27 DDBIA0_1
DQA1_10 C11 DQA1_9 DDBIA0_1 C23 DDBIA0_2
DQA1_10 DDBIA0_2
1
DQA1_11 F11 C19 DDBIA0_3

RV148 DQA1_12 A9 DQA1_11 DDBIA0_3 C15 DDBIA1_0
40.2_0402_1% DQA1_13 C9 DQA1_12 DDBIA1_0 E9 DDBIA1_1
DQA1_14 F9 DQA1_13 DDBIA1_1 C5 DDBIA1_2
DQA1_15 D8 DQA1_14 DDBIA1_2 H4 DDBIA1_3
2
DQA1_16 E7 DQA1_15 DDBIA1_3

+VDD_MEM15_REFSA DQA1_17 A7 DQA1_16 L18 ADBIA0
DQA1_18 C7 DQA1_17 ADBIA0 K16 ADBIA1 ADBIA0 <54>
DQA1_19 F7 DQA1_18 ADBIA1 ADBIA1 <55>
1 DQA1_19
1
CV274 DQA1_20 A5 H26 CLKA0

RV147 1U_0603_10V6K DQA1_21 E5 DQA1_20 CLKA0 H25 CLKA0# CLKA0 <54>
100_0402_1% DQA1_22 C3 DQA1_21 CLKA0B CLKA0# <54>
2 DQA1_23 E1 DQA1_22 G9 CLKA1
DQA1_24 G7 DQA1_23 CLKA1 H9 CLKA1# CLKA1 <55>
2
DQA1_25 G6 DQA1_24 CLKA1B CLKA1# <55>

DQA1_25 SI4164DY
DQA1_26 G1 G22 RASA0#
DQA1_27 G3 DQA1_26 RASA0B G17 RASA1# RASA0# <54> VDS RDS(on) ID(A)
DQA1_28 J6 DQA1_27 RASA1B RASA1# <55> 30 0.0032ohm at VGS=10V 30A
DQA1_29 J1 DQA1_28 G19 CASA0#
DQA1_29 CASA0B CASA0# <54> 30 0.0039ohm at VGS=4.5V 26.3A
DQA1_30 J3 G16 CASA1#
DQA1_31 J5 DQA1_30 CASA1B CASA1# <55>
DQA1_31 H22 CSA0#_0
+VDD_MEM15_REFDA K26 CSA0B_0 J22 CSA0#_0 <54>
+VDD_MEM15_REFSA J26 MVREFDA CSA0B_1
MVREFSA G13 CSA1#_0
J25 CSA1B_0 K13 CSA1#_0 <55>
Place RV178~RV180, CV343,CV344 1 2 K25 NC#J25 CSA1B_1
B
close to UV1 within 1000mil RV36 120_0402_1% MEM_CALRP0
CKEA0
K20 CKEA0
CKEA0 <54>
+1.35V_MEM_GFX Source B
J17 CKEA1 +1.35V_MEM_GFX

RV179 CKEA1 CKEA1 <55> +PWR_SRC +1.35V_MEM QV1
G25 WEA0# AO4354_SOIC-8
RV178 1 WEA0B WEA0# <54>
470K_0402_5%
2 1 2 DRAM_RST#_R L10 H10 WEA1# +3.3V_ALW2 8 1
<54,55> DRAM_RST# DRAM_RST WEA1B WEA1# <55>
1
7 2
10_0402_1%
2
5.11K_0402_1%
10U_0603_6.3V6M
49.9_0402_1% K8 6 3
CLKTESTA
1
RV180
RV67
39_0402_5%
L7 5 1
CLKTESTB
1
C783
RV182
2
CV343 @ CV344
4
120P_0402_50V9 68P_0402_50V9 216-0841009-A0-SUN_FCBGA631~D RV81 GFX_MEM_VTT_EN
2
100K_0402_5% 2
2
QV5
L2N7002WT1G_SC-70-3
100P_0402_50V8J
L2N7002WT1G_SC-70-3
+1.35V_MEM_GFX_CHG
1
1
D
2.2M_0402_5%
QV2
S
D
DGPU_PWR_EN# 3 1DGPU_PWR_EN#_Q 2 1
<16> DGPU_PWR_EN#
RV80
G
CV129
S
3
2
G
2
2
RV82 @ 2
+3.3V_RUN
100K_0402_5%
CLKTESTA
L2N7002WT1G_SC-70-3
CLKTESTB
<63> DGPU_PWR_EN#_Q
1
D
1
D
QV11
2DGPU_PWR_EN#_Q
1
@ @ QV6 2DGPU_PWR_EN# G
CV85 CV86 L2N7002WT1G_SC-70-3 G S
3
0.1U_0402_25V6 0.1U_0402_25V6 @ S
2
3
1
route 50ohms single-ended/100ohms diff

@ @
RV46 RV45 and keep short
51.1_0402_1% 51.1_0402_1%
A A
2
Debug only, for clock observation,

if not needed, DNI 5mil 5mil
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SUN-MEM Interface A
1.0
5 4 3 2 1
5 4 3 2 1
Memory Partition A - Lower 16 bits 64X32 GDDR5 VRAM@

UV5
MIRROR
VRAM@ MF=0 MF=1 MF=1 MF=0
UV4
NORMAL
A4 DQA0_23
MF=0 MF=1 MF=1 MF=0 EDCA0_2 C2 DQ24 DQ0 A2 DQA0_21
<53> EDCA0_2 C13 EDC0 EDC3 DQ25 DQ1 B4 DQA0_22
A4 DQA0_12 EDCA0_0 R13 EDC1 EDC2 DQ26 DQ2 B2 DQA0_20
EDCA0_1 C2 DQ24 DQ0 A2 DQA0_15 <53> EDCA0_0 R2 EDC2 EDC1 DQ27 DQ3 E4 DQA0_19
<53> EDCA0_1 C13 EDC0 EDC3 DQ25 DQ1 B4 DQA0_13 EDC3 EDC0 DQ28 DQ4 E2 DQA0_18
EDCA0_3 R13 EDC1 EDC2 DQ26 DQ2 B2 DQA0_14 DQ29 DQ5 F4 DQA0_16
<53> EDCA0_3 R2 EDC2 EDC1 DQ27 DQ3 E4 DQA0_11 DDBIA0_2 D2 DQ30 DQ6 F2 DQA0_17
EDC3 EDC0 DQ28 DQ4 E2 DQA0_10 D13 DBI0# DBI3# DQ31 DQ7 A11
DQ29 DQ5 +1.35V_MEM_GFX DBI1# DBI2# DQ16 DQ8
F4 DQA0_8 DDBIA0_0 P13 A13
DDBIA0_1 D2 DQ30 DQ6 F2 DQA0_9 P2 DBI2# DBI1# DQ17 DQ9 B11
D13 DBI0# DBI3# DQ31 DQ7 A11 DBI3# DBI0# DQ18 DQ10 B13
D +1.35V_MEM_GFX DBI1# DBI2# DQ16 DQ8 DQ19 DQ11 D
DDBIA0_3 P13 A13 CLKA0 J12 E11
P2 DBI2# DBI1# DQ17 DQ9 B11 <53,54> CLKA0 J11 CK DQ20 DQ12 E13
CLKA0#
DBI3# DBI0# DQ18 DQ10 B13 <53,54> CLKA0# J3 CK# DQ21 DQ13 F11
CKEA0
J12 DQ19 DQ11 E11 <53,54> CKEA0 CKE# DQ22 DQ14 F13
CLKA0
<53,54> CLKA0 J11 CK DQ20 DQ12 E13 J5 DQ23 DQ15 U11
CLKA0# MAA0_8 DQA0_4
<53,54> CLKA0# J3 CK# DQ21 DQ13 F11 A12/A13 DQ8 DQ16 U13
CKEA0 DQA0_3
<53,54> CKEA0 CKE# DQ22 DQ14 F13 K4 DQ9 DQ17 T11
MAA0_0 DQA0_5
MAA0_8 J5 DQ23 DQ15 U11 DQA0_31 MAA0_1 K5 A8/A7 A10/A0 DQ10 DQ18 T13 DQA0_2
A12/A13 DQ8 DQ16 U13 DQA0_29 MAA0_3 K10 A11/A6 A9/A1 DQ11 DQ19 N11 DQA0_6
MAA0_7 K4 DQ9 DQ17 T11 DQA0_28 MAA0_2 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 DQA0_1
MAA0_6 K5 A8/A7 A10/A0 DQ10 DQ18 T13 DQA0_30 BA2/A4 BA0/A2 DQ13 DQ21 M11 DQA0_7
MAA0_5 K10 A11/A6 A9/A1 DQ11 DQ19 N11 DQA0_26 MAA0_5 H10 DQ14 DQ22 M13 DQA0_0
MAA0_4 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 DQA0_27 DQA0_[0..31] MAA0_4 H11 BA3/A3 BA1/A5 DQ15 DQ23 U4
BA2/A4 BA0/A2 DQ13 DQ21 M11 DQA0_[0..31] <53> H5 BA0/A2 BA2/A4 DQ0 DQ24 U2
DQA0_25 MAA0_6
MAA0_3 H10 DQ14 DQ22 M13 DQA0_24 EDCA0_[0..3] MAA0_7 H4 A9/A1 A11/A6 DQ1 DQ25 T4
H11 BA3/A3 BA1/A5 DQ15 DQ23 U4 EDCA0_[0..3] <53> A10/A0 A8/A7 DQ2 DQ26 T2
MAA0_2
MAA0_1 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2 DDBIA0_[0..3] DQ3 DQ27 N4
H4 A9/A1 A11/A6 DQ1 DQ25 T4 DDBIA0_[0..3] <53> A5 DQ4 DQ28 N2
MAA0_0
A10/A0 A8/A7 DQ2 DQ26 T2 MAA0_[0..8] U5 NC DQ5 DQ29 M4
DQ3 DQ27 N4 MAA0_[0..8] <53> NC DQ6 DQ30 M2
A5 DQ4 DQ28 N2 DQ7 DQ31
NC DQ5 DQ29 +1.35V_MEM_GFX +1.35V_MEM_GFX
U5 M4 J1
NC DQ6 DQ30 M2 J10 MF
DQ7 DQ31 1 2 J13 SEN B1
J1 +1.35V_MEM_GFX RV107 ZQ VDDQ D1
J10 MF 121_0402_1% VDDQ F1
RV108 1 2 121_0402_1% J13 SEN B1 ADBIA0 J4 VDDQ M1
ZQ VDDQ D1 <53,54> ADBIA0 G3 ABI# VDDQ P1
CASA0#
VDDQ F1 <53,54> CASA0# G12 RAS# CAS# VDDQ T1
WEA0#
J4 VDDQ M1 <53,54> WEA0# L3 CS# WE# VDDQ G2
ADBIA0 RASA0#
<53,54> ADBIA0 G3 ABI# VDDQ P1 <53,54> RASA0# L12 CAS# RAS# VDDQ L2
RASA0# +1.35V_MEM_GFX CSA0#_0
<53,54> RASA0# G12 RAS# CAS# VDDQ T1 <53,54> CSA0#_0 WE# CS# VDDQ B3
CSA0#_0
<53,54> CSA0#_0 L3 CS# WE# VDDQ G2 VDDQ D3
CASA0#
<53,54> CASA0# CAS# RAS# VDDQ VDDQ
1U_0402_6.3V6K
2.37K_0402_1%
+1.35V_MEM_GFX WEA0# L12 L2 F3
<53,54> WEA0# WE# CS# VDDQ VDDQ
1
B3 1 WCKA0B_1 D5 H3
VDDQ <53,54> WCKA0B_1 WCK01# WCK23# VDDQ
CV325
RV140
D3 WCKA0_1 D4 K3
VDDQ <53,54> WCKA0_1 WCK01 WCK23 VDDQ
1U_0402_6.3V6K
2.37K_0402_1%
C
F3 M3 C
VDDQ VDDQ
1
1 WCKA0B_0 D5 H3 WCKA0B_0 P5 P3
<53,54> WCKA0B_0 WCK01# WCK23# VDDQ 2 <53,54> WCKA0B_0 WCK23# WCK01# VDDQ
CV322
RV109
WCKA0_0 D4 K3 WCKA0_0 P4 T3
2
<53,54> WCKA0_0 WCK01 WCK23 VDDQ M3 <53,54> WCKA0_0 WCK23 WCK01 VDDQ E5
VDDQ VDDQ
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
WCKA0B_1 P5 P3 N5
2 <53,54> WCKA0B_1 P4 WCK23# WCK01# VDDQ T3 A10 VDDQ E10
WCKA0_1 +VREFD2_1 1 1 1 1 1 1
2
<53,54> WCKA0_1 WCK23 WCK01 VDDQ VREFD VDDQ
CV139
CV140
CV179
CV182
E5 +VREFD2_2 U10 N10
VDDQ VREFD VDDQ
1U_0402_6.3V6K
5.49K_0402_1%
CV137
CV138
N5 +VREFC2 J14 B12
VDDQ VREFC VDDQ
1
+VREFD1_1 A10 E10 1 D12
VREFD VDDQ VDDQ 2 2 2 2 2 2
CV327
RV181
+VREFD1_2 U10 N10 F12
VREFD VDDQ VDDQ
1U_0402_6.3V6K
5.49K_0402_1%
+VREFC1 J14 B12 H12

VREFC VDDQ VDDQ
1
1 D12 DRAM_RST# J2 K12

VDDQ 2 <53,55> DRAM_RST# RESET# VDDQ
CV207
RV128
F12 M12
2
VDDQ H12 VDDQ P12
DRAM_RST# J2 VDDQ K12 VDDQ T12
2 RESET# VDDQ M12 VDDQ G13
2
VDDQ P12 VDDQ L13

VDDQ T12 VDDQ B14
VDDQ G13 VDDQ D14
VDDQ L13 VDDQ F14
+1.35V_MEM_GFX VDDQ B14 VDDQ M14
VDDQ 10U_0603_6.3V6M VDDQ
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
D14 G1 P14
VDDQ F14 L1 VDD VDDQ T14
VDDQ 1 1 1 1 1 1 1 VDD VDDQ
CV42
CV178
CV188
CV141
CV142
CV143
CV151
M14 G4
G1 VDDQ P14 L4 VDD
L1 VDD VDDQ T14 C5 VDD A1
G4 VDD VDDQ 2 2 2 2 2 2 2 R5 VDD VSSQ C1
L4 VDD C10 VDD VSSQ E1
C5 VDD A1 R10 VDD VSSQ N1
R5 VDD VSSQ C1 D11 VDD VSSQ R1
VDD VSSQ VDD VSSQ
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
C10 E1 G11 U1
R10 VDD VSSQ N1 L11 VDD VSSQ H2
1 1 1 1 1 VDD VSSQ VDD VSSQ
CV41
CV176
CV177
CV152
CV153
D11 R1 +1.35V_MEM_GFX P11 K2

G11 VDD VSSQ U1 G14 VDD VSSQ A3
L11 VDD VSSQ H2 L14 VDD VSSQ C3
2 2 2 2 2 P11 VDD VSSQ K2 VDD VSSQ E3
VDD VSSQ VSSQ
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
G14 A3 N3
L14 VDD VSSQ C3 VSSQ R3
B VDD VSSQ 1 1 1 1 VSSQ B
CV154
CV155
E3 H1 U3
VSSQ VSS VSSQ
CV130
CV131
N3 K1 C4
VSSQ R3 B5 VSS VSSQ R4
H1 VSSQ U3 2 2 2 2 G5 VSS VSSQ F5
K1 VSS VSSQ C4 L5 VSS VSSQ M5
B5 VSS VSSQ R4 T5 VSS VSSQ F10
G5 VSS VSSQ F5 B10 VSS VSSQ M10
L5 VSS VSSQ M5 D10 VSS VSSQ C11
T5 VSS VSSQ F10 G10 VSS VSSQ R11
B10 VSS VSSQ M10 L10 VSS VSSQ A12
D10 VSS VSSQ C11 P10 VSS VSSQ C12
G10 VSS VSSQ R11 T10 VSS VSSQ E12
L10 VSS VSSQ A12 H14 VSS VSSQ N12
P10 VSS VSSQ C12 K14 VSS VSSQ R12
T10 VSS VSSQ E12 VSS170-BALL VSSQ U12
H14 VSS VSSQ N12 VSSQ H13
K14 VSS VSSQ R12 SGRAM GDDR5 VSSQ K13
VSS170-BALL VSSQ U12 VSSQ A14
VSSQ H13 VSSQ C14
SGRAM GDDR5 VSSQ K13 VSSQ E14
VSSQ A14 VSSQ N14
VSSQ C14 VSSQ R14
VSSQ E14 VSSQ U14
VSSQ N14 VSSQ
VSSQ R14 K4G41325FC-HC04_FBGA170~D
VSSQ U14 +1.35V_MEM_GFX +1.35V_MEM_GFX
VSSQ
K4G41325FC-HC04_FBGA170~D
1U_0402_6.3V6K
2.37K_0402_1%
1U_0402_6.3V6K
2.37K_0402_1%
+1.35V_MEM_GFX +1.35V_MEM_GFX
1
1 1
CV328
RV183
CV330
RV185
1U_0402_6.3V6K
2.37K_0402_1%
1U_0402_6.3V6K
2.37K_0402_1%
1
1 1
2 2
CV208
RV139
CV323
RV129
PROPRIETARY NOTE:
2

2 2 +VREFC2 +VREFD2_2 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
A A
2
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

1U_0402_6.3V6K
5.49K_0402_1%
1U_0402_6.3V6K
5.49K_0402_1%
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1
+VREFC1 +VREFD1_2 1 1
CV329
RV184
CV331
RV186
1U_0402_6.3V6K
5.49K_0402_1%
1U_0402_6.3V6K
5.49K_0402_1%
1
1 1
2 2
CV326
RV110
CV324
RV131
2
2 2
2
Title
SUN-VRAM_A Lower
1.0
LA-9934P
5 4 3 2 1
5 4 3 2 1
Memory Partition A - Upper 16 bits VRAM@

UV6
NORMAL
VRAM@
UV3
MIRROR MF=0 MF=1 MF=1 MF=0
MF=0 MF=1 MF=1 MF=0 A4 DQA1_6

EDCA1_0 C2 DQ24 DQ0 A2 DQA1_4
A4 DQA1_19 <53> EDCA1_0 C13 EDC0 EDC3 DQ25 DQ1 B4 DQA1_7
EDCA1_2 C2 DQ24 DQ0 A2 DQA1_22 EDCA1_3 R13 EDC1 EDC2 DQ26 DQ2 B2 DQA1_5
<53> EDCA1_2 C13 EDC0 EDC3 DQ25 DQ1 B4 DQA1_18 <53> EDCA1_3 R2 EDC2 EDC1 DQ27 DQ3 E4 DQA1_3
EDCA1_1 R13 EDC1 EDC2 DQ26 DQ2 B2 DQA1_20 EDC3 EDC0 DQ28 DQ4 E2 DQA1_2
<53> EDCA1_1 R2 EDC2 EDC1 DQ27 DQ3 E4 DQA1_17 DQ29 DQ5 F4 DQA1_0
EDC3 EDC0 DQ28 DQ4 E2 DQA1_23 DDBIA1_0 D2 DQ30 DQ6 F2 DQA1_1
DQ29 DQ5 F4 DQA1_16 D13 DBI0# DBI3# DQ31 DQ7 A11
DQ30 DQ6 +1.35V_MEM_GFX DBI1# DBI2# DQ16 DQ8
DDBIA1_2 D2 F2 DQA1_21 DDBIA1_3 P13 A13
D13 DBI0# DBI3# DQ31 DQ7 A11 P2 DBI2# DBI1# DQ17 DQ9 B11
+1.35V_MEM_GFX DBI1# DBI2# DQ16 DQ8 DBI3# DBI0# DQ18 DQ10
D DDBIA1_1 P13 A13 B13 D
P2 DBI2# DBI1# DQ17 DQ9 B11 CLKA1 J12 DQ19 DQ11 E11
DBI3# DBI0# DQ18 DQ10 B13 CLKA1# J11 CK DQ20 DQ12 E13
CLKA1 J12 DQ19 DQ11 E11 CKEA1 J3 CK# DQ21 DQ13 F11
<53> CLKA1 J11 CK DQ20 DQ12 E13 CKE# DQ22 DQ14 F13
CLKA1#
<53> CLKA1# J3 CK# DQ21 DQ13 F11 J5 DQ23 DQ15 U11
CKEA1 MAA1_8 DQA1_30
<53> CKEA1 CKE# DQ22 DQ14 F13 A12/A13 DQ8 DQ16 U13 DQA1_31
MAA1_8 J5 DQ23 DQ15 U11 DQA1_13 MAA1_7 K4 DQ9 DQ17 T11 DQA1_29
A12/A13 DQ8 DQ16 U13 DQA1_15 MAA1_6 K5 A8/A7 A10/A0 DQ10 DQ18 T13 DQA1_28
MAA1_0 K4 DQ9 DQ17 T11 DQA1_14 MAA1_5 K10 A11/A6 A9/A1 DQ11 DQ19 N11 DQA1_26
MAA1_1 K5 A8/A7 A10/A0 DQ10 DQ18 T13 DQA1_12 MAA1_4 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 DQA1_27
MAA1_3 K10 A11/A6 A9/A1 DQ11 DQ19 N11 DQA1_9 BA2/A4 BA0/A2 DQ13 DQ21 M11 DQA1_24
MAA1_2 K11 BA1/A5 BA3/A3 DQ12 DQ20 N13 DQA1_8 MAA1_3 H10 DQ14 DQ22 M13 DQA1_25
BA2/A4 BA0/A2 DQ13 DQ21 M11 DQA1_11 MAA1_2 H11 BA3/A3 BA1/A5 DQ15 DQ23 U4
MAA1_5 H10 DQ14 DQ22 M13 DQA1_10 MAA1_1 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2
MAA1_4 H11 BA3/A3 BA1/A5 DQ15 DQ23 U4 MAA1_0 H4 A9/A1 A11/A6 DQ1 DQ25 T4
MAA1_6 H5 BA0/A2 BA2/A4 DQ0 DQ24 U2 A10/A0 A8/A7 DQ2 DQ26 T2
MAA1_7 H4 A9/A1 A11/A6 DQ1 DQ25 T4 DQ3 DQ27 N4
A10/A0 A8/A7 DQ2 DQ26 T2 A5 DQ4 DQ28 N2
DQ3 DQ27 N4 U5 NC DQ5 DQ29 M4
A5 DQ4 DQ28 N2 NC DQ6 DQ30 M2
U5 NC DQ5 DQ29 M4 DQ7 DQ31
NC DQ6 DQ30 M2 J1 +1.35V_MEM_GFX
+1.35V_MEM_GFX DQ7 DQ31 MF
J10
J1 +1.35V_MEM_GFX 1 2 J13 SEN B1
J10 MF RV117 ZQ VDDQ D1
RV118 1 2 121_0402_1% J13 SEN B1 121_0402_1% VDDQ F1
ZQ VDDQ D1 ADBIA1 J4 VDDQ M1
VDDQ F1 RASA1# G3 ABI# VDDQ P1
ADBIA1 J4 VDDQ M1 CSA1#_0 G12 RAS# CAS# VDDQ T1
<53> ADBIA1 G3 ABI# VDDQ P1 L3 CS# WE# VDDQ G2
CASA1# CASA1#
<53> CASA1# G12 RAS# CAS# VDDQ T1 L12 CAS# RAS# VDDQ L2
WEA1# +1.35V_MEM_GFX WEA1#
<53> WEA1# L3 CS# WE# VDDQ G2 WE# CS# VDDQ B3
RASA1#
<53> RASA1# L12 CAS# RAS# VDDQ L2 VDDQ D3
+1.35V_MEM_GFX CSA1#_0
<53> CSA1#_0 WE# CS# VDDQ VDDQ
1U_0402_6.3V6K
2.37K_0402_1%
B3 F3
VDDQ VDDQ
1
D3 1 WCKA1B_0 D5 H3
VDDQ <53,55> WCKA1B_0 WCK01# WCK23# VDDQ
1U_0402_6.3V6K
2.37K_0402_1%
CV352
RV195
F3 WCKA1_0 D4 K3
VDDQ <53,55> WCKA1_0 WCK01 WCK23 VDDQ
1
C 1 WCKA1B_1 D5 H3 M3 C
<53,55> WCKA1B_1 WCK01# WCK23# VDDQ VDDQ
CV209
RV119
WCKA1_1 D4 K3 WCKA1B_1 P5 P3
<53,55> WCKA1_1 WCK01 WCK23 VDDQ M3 2 <53,55> WCKA1B_1 P4 WCK23# WCK01# VDDQ T3
WCKA1_1
2
P5 VDDQ P3 <53,55> WCKA1_1 WCK23 WCK01 VDDQ E5
WCKA1B_0
2 <53,55> WCKA1B_0 WCK23# WCK01# VDDQ VDDQ
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
WCKA1_0 P4 T3 N5
2
<53,55> WCKA1_0 WCK23 WCK01 VDDQ E5 A10 VDDQ E10

+VREFD4_1 1 1 1 1 1 1
VDDQ VREFD VDDQ
CV147
CV150
CV181
CV185
N5 +VREFD4_2 U10 N10
VDDQ VREFD VDDQ
1U_0402_6.3V6K
5.49K_0402_1%
CV149
CV148
+VREFD3_1 A10 E10 +VREFC4 J14 B12
VREFD VDDQ VREFC VDDQ
1
+VREFD3_2 U10 N10 1 D12
VREFD VDDQ VDDQ 2 2 2 2 2 2
1U_0402_6.3V6K
5.49K_0402_1%
CV351
RV196
+VREFC3 J14 B12 F12
VREFC VDDQ VDDQ
1
1 D12 H12
VDDQ VDDQ
CV210
RV120
F12 DRAM_RST# J2 K12

VDDQ H12 2 <53,54> DRAM_RST# RESET# VDDQ M12
2
DRAM_RST# J2 VDDQ K12 VDDQ P12
2 RESET# VDDQ M12 VDDQ T12
2
VDDQ P12 VDDQ G13

VDDQ T12 VDDQ L13
VDDQ G13 VDDQ B14
VDDQ L13 VDDQ D14
+1.35V_MEM_GFX VDDQ B14 VDDQ F14
VDDQ D14 VDDQ M14
VDDQ VDDQ
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
F14 G1 P14
VDDQ M14 L1 VDD VDDQ T14
VDDQ 1 1 1 1 1 1 1 VDD VDDQ
CV44
CV145
CV146
CV144
CV156
G1 P14 G4
VDD VDDQ VDD
CV180
CV189
L1 T14 L4
G4 VDD VDDQ C5 VDD A1
L4 VDD 2 2 2 2 2 2 2 R5 VDD VSSQ C1
C5 VDD A1 C10 VDD VSSQ E1
R5 VDD VSSQ C1 R10 VDD VSSQ N1
VDD VSSQ VDD VSSQ
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
C10 E1 D11 R1
R10 VDD VSSQ N1 G11 VDD VSSQ U1
1 1 1 1 1 VDD VSSQ VDD VSSQ
CV43
CV157
CV158
D11 R1 L11 H2
VDD VSSQ VDD VSSQ
CV191
CV192
G11 U1 +1.35V_MEM_GFX P11 K2

L11 VDD VSSQ H2 G14 VDD VSSQ A3
2 2 2 2 2 P11 VDD VSSQ K2 L14 VDD VSSQ C3
G14 VDD VSSQ A3 VDD VSSQ E3
L14 VDD VSSQ C3 VSSQ N3
VDD VSSQ VSSQ
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
B
E3 R3 B
VSSQ N3 H1 VSSQ U3
VSSQ 1 1 1 1 VSS VSSQ
CV159
CV162
R3 K1 C4
VSSQ VSS VSSQ
CV134
CV133
H1 U3 B5 R4
K1 VSS VSSQ C4 G5 VSS VSSQ F5
B5 VSS VSSQ R4 2 2 2 2 L5 VSS VSSQ M5
G5 VSS VSSQ F5 T5 VSS VSSQ F10
L5 VSS VSSQ M5 B10 VSS VSSQ M10
T5 VSS VSSQ F10 D10 VSS VSSQ C11
B10 VSS VSSQ M10 G10 VSS VSSQ R11 DQA1_[0..31]
D10 VSS VSSQ C11 L10 VSS VSSQ A12 DQA1_[0..31] <53>
G10 VSS VSSQ R11 P10 VSS VSSQ C12 EDCA1_[0..3]
L10 VSS VSSQ A12 T10 VSS VSSQ E12 EDCA1_[0..3] <53>
P10 VSS VSSQ C12 H14 VSS VSSQ N12 DDBIA1_[0..3]
T10 VSS VSSQ E12 K14 VSS VSSQ R12 DDBIA1_[0..3] <53>
H14 VSS VSSQ N12 VSS170-BALL VSSQ U12 MAA1_[0..8]
K14 VSS VSSQ R12 VSSQ H13 MAA1_[0..8] <53>
VSS170-BALL VSSQ U12 SGRAM GDDR5 VSSQ K13
VSSQ H13 VSSQ A14
SGRAM GDDR5 VSSQ K13 VSSQ C14
VSSQ A14 VSSQ E14
VSSQ C14 VSSQ N14
VSSQ E14 VSSQ R14
VSSQ N14 VSSQ U14
VSSQ R14 VSSQ
VSSQ U14 K4G41325FC-HC04_FBGA170~D
+1.35V_MEM_GFX +1.35V_MEM_GFX VSSQ
K4G41325FC-HC04_FBGA170~D +1.35V_MEM_GFX +1.35V_MEM_GFX
1U_0402_6.3V6K
2.37K_0402_1%
1U_0402_6.3V6K
2.37K_0402_1%
1
1U_0402_6.3V6K
2.37K_0402_1%
1U_0402_6.3V6K
2.37K_0402_1%
1 1
1
1
CV333
RV191
CV350
RV193
1 1
CV356
RV203
CV354
RV197
2 2
PROPRIETARY NOTE:
2
2 2
2
A +VREFD3_2 +VREFC3 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT A
+VREFD4_2 +VREFC4 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
1U_0402_6.3V6K
5.49K_0402_1%
1U_0402_6.3V6K
5.49K_0402_1%
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1
1U_0402_6.3V6K
5.49K_0402_1%
1U_0402_6.3V6K
5.49K_0402_1%
1 1
1

CV332
RV192
CV349
RV194
1 1
CV355
RV205
CV353
RV198
2 2 DELL CONFIDENTIAL/PROPRIETARY
2
2 2
2

Title
SUN-VRAM_A Upper
1.0
LA-9934P
5 4 3 2 1
5 4 3 2 1
+COINCELL
COIN RTC Battery
1
PR1
1K_0402_5%~D
+3.3V_RTC_LDO
2
JRTC1
Z4012
+COINCELL 1
2 1
3 2
D
4 G1 D
2
G2
+RTC_CELL ACES_50273-0020N-001
PD3
1
BAS40-05W_SC70 1
PC3
ESD Diodes 1U_0603_10V4Z~D
1
PD2 PD4 2
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
EMC@ EMC@
3
EMC@ PL2
FBMJ4516HS720NT_2P~D +3.3V_ALW
1 2
Primary Battery Connector

EMC@ PL3
1
FBMJ4516HS720NT_2P~D
100K_0402_5%~D
PBATT1 1 2
+PBATT_C +PBATT
11
PR6
GND 10
GND 9 PRP2
2
9 8 100_0804_8P4R_5%
2200P_0402_50V7K
8 7 Z4304 8 1
7 6 Z4305 7 2
PBAT_SMBDAT <46>
1
6 5 6 3
PC5
Z4306
5 PBAT_SMBCLK <46> PBAT_PRES# <45,65>
4 5 4
4 3
2
3 2
EMC@
2 1 PQ7
C C
1 DMG2301U-7 1P_SOT23-3
OCTEK_BTJ-09WKFB 1 2 1 3
3
DOCK_SMB_ALERT# <44,45,65>
PD7
SDMK0340L-7-F_SOD323-2~D Vth: -0.4 ~ -1
2
2
GND @ PR26
1 2
<44,45,65> SLICE_BAT_PRES#
1500P_0402_7K~D
1
PC17
0_0402_5%
2
+3.3V_ALW
@ PR10 PU1
2.2K_0402_5%~D
2
1 2 1 6
<44> DOCK_PSID NO IN GPIO_PSID_SELECT <45>
0_0402_5%~D
PR11
2 5 +5V_ALW
EMC@ PL4 PR12 GND V+
1
BLM15AG102SN1D_2P 33_0402_5%~D
NB_PSID 2 1 1 3 1 2 NB_PSID_TS5A63157 3 4
D
S
NC COM PS_ID <46>
PQ1 74LVC1G3157GW SC-88 6P
100K_0402_1%~D
2
FDV301N_G_NL_SOT23-3~D
G
2
+5V_ALW
PR13
10K_0402_1%~D
1
1
B B
C
2 PQ2
PR14
B MMST3904-7-F_SOT323~D
E
15K_0402_1%
3
2
2
PR15
PR16
1 2
PSID_DISABLE# <45>
1
@ 10K_0402_5%~D
DC_IN+ Source
+DC_IN +DC_IN_SS
EMC@ PL5 PQ4
FBMA-L11-453215-800LMA90T_1812~D FDS6679AZ_G_SO8~D
1 2 +DC_IN 1 8
2 S D 7
3
3 S D 6
IMD2AT-108_SC74-6~D
4 S D 5
G D
2
1
0.022U_0805_50V7K~D
2
PQ6B
1M_0402_5%~D
PC8
10U_0805_25V6K
100K_0402_5%~D
1
PR18
1
1
100P_0603_50V8
PR20
PC13
2
1
PR23
PC12
@EMC@ PC14
4.7K_0805_5%~D
1000P_0603_50V7K
2
IMD2AT-108_SC74-6~D
1
JESS_UCNR2451M005-0 1 2
2
5 SOFT_START_GC <65>
2
5 4 -DCIN_JACK 10K_0402_5%~D
@ PR22
2
4 3
EMC@
1M_0402_5%~D
3 2 +DCIN_JACK 5
PQ6A
AC_DIS <45,65>
2
2 1
PR25
A A
1
PJPDC1
2
6
PJP1
1 2
PAD-OPEN 1x3m
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D PWR_+DCIN
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1.0
LA-9934P
5 4 3 2 1
A B C D E
+3.3V_ALW2
+3.3V_RTC_LDO
PR100
6.49K_0402_1%~D
1 2 PR101
15K_0402_1%
1 2 1 1
1U_0603_10V5K~D
PR102 PR104
10K_0402_1% @ PR103 10K_0402_1%
1
PC114
1 2 0_0402_5% 2 1
110K_0402_1%~D
2
115K_0402_1%~D
+3V5V_PWR_SRC
PR106
PR105
+3V5V_PWR_SRC +3.3V_ALW
1
<46> ALW_PWRGD_3V_5V
1
110K_0402_1%~D
EMC@ PL103
2
1UH_MMD-05CZ-1R0M-M7L_7A_20%
PR119
2 1 PU100
10U_0805_25V6K
0.1U_0402_25V6
1
1
PC109
+PWR_SRC
CS2
VFB2
VREG3
VFB1
CS1
2200P_0402_50V7K
10U_0805_25V6K
@EMC@ PC103
0.1U_0402_25V6
21
SIS412DN-T1-GE3_POWERPAK8-5~D
1
PAD
1
1
PC110
3V_5V_EN 6
2
EN2
5
@EMC@ PC105
@EMC@ PC106
@ PR118 14
VO1
5
0_0402_5% @ PR111
2
1 2 7 200_0402_1%
PGOOD
PQ101
19 2 1
VCLK
PQ102
4 UG_3V 10 TPS51225CRUKR_QFN20_3X3
PC112 PR108 DRVH2 16 UG_5V 4
0.1U_0603_25V7K~D 2.2_0603_5% DRVH1 PR107 PC111
1 2 1 2 BST_3V 9 2.2_0603_5% 0.1U_0603_25V7K
VBST2 17 BST_5V 1 2 1 2
1
2
3
2 VBST1 2
3
2
1
SW2 8
SW2 18 SW1
VREG5
DRVL2
DRVL1
PL101 SW1 PL102
+3VALWP +5VALWP
EN1
VIN
2.2UH_VMPI0703AR-2R2M-Z01 8A_20% 3.3UH_ETQP3W3R3WFN 7A_20%
1 2 1 2
11
12
13
3V_5V_EN 20
15
680P_0603_50V7K
680P_0603_50V7K
SIS472DN-T1_POWERPAK1212-8-5
5
1
220U_6.3V_M_R18M
@EMC@ PC119
LG_3V LG_5V
1
@EMC@ PC116
220U_6.3V_M_R18M
2
PC101
+
1
SNUB_3V 2
PQ103
PQ104
1 SNUB_5V
PC102
4 4 +
2
1U_0603_10V5K~D
0.1U_0603_25V7K
4.7_1206_5%
1
2
3
3
2
1
1
1
4.7_1206_5%
PC117
PC118
@EMC@ PR112
@EMC@ PR109
2
2
+3V5V_PWR_SRC +5V_ALW2
3 3
3V_5V_EN
@ PR110
0_0402_5%
1 2
<46> ALWON
+5VALWP
+3VALWP Ripple voltage -
Ripple voltage - Static load 3% / Dynamic load 5%
Static load 3% / Dynamic load 5% Frequency 300kHz
1U_0603_10V6K
Frequency 350kHz TDC 6.08A

1
PJP101
PC120
PJP100
2 1 1 2 Peak Current 8.68A
TDC 6.48A +3VALWP +3.3V_ALW +5VALWP +5V_ALW
2
Peak Current 9.25A @ PAD-OPEN 1x2m~D

PAD-OPEN 4x4m OCP current 10.4A
OCP current 11.1A PJP102 PJP103 TYP MAX
1 2 1 2
TYP MAX H/S Rds(on) 24mohm , 30mohm
H/S Rds(on) 24mohm , 30mohm PAD-OPEN 4x4m PAD-OPEN 4x4m L/S Rds(on) 10.3mohm , 12.4mohm
L/S Rds(on) 10.3mohm , 12.4mohm Choke DCR Max:28mohm
Choke DCR Max:17mohm
4 4
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_+3VALWP/5VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9934P
A B C D E
5 4 3 2 1
0.675Volt +/- 5%
PJP201 TDC 0.525A
VLDOIN_1.35V 2 1 +1.35V_MEN_P Peak Current 0.75A
OCP Current 2.6A
+PWR_SRC PJP200
PR200
PAD-OPEN1x1m
fixed by IC
2 1 1.35V_B+ 1 2 BOOT_1.35V
2 1
2.2_0603_5%
JUMP_43X118
DH_1.35V
2200P_0402_50V7K
D D
+0.675V_P
10U_0805_25V6K
10U_0805_25V6K
2
SIR472DP-T1-GE3_POWERPAK8-5~D
10U_0805_6.3V6M
10U_0805_6.3V6M
1
1
PC206 SW _1.35V
PJP202
5
PC202
PC203
PC205
0.22U_0603_10V7K
1
2 1
1
DL_1.35V
PC207
PC208
16
17
18
19
20
@ PU200 +0.675V_DDR_VTT
PQ201
@EMC@
PAD-OPEN1x1m
VLDOIN
PHASE
UGATE
BOOT
VTT
2
4 21
PAD
15 1
LGATE VTTGND
1
2
3
PR201 14 2
+1.35V_MEN_P PL201 6.98K_0402_1% PGND VTTSNS +V_DDR_REF
1UH_PCMC104T-1R0MN 20A_20%~D 1 2 CS_1.35V
1 2 13 3
PC213 CS RT8207MZQW _W QFN20_3X3 GND
5
1U_0603_10V6K
680P_0603_50V7K
330U_SX_2VY_R9M
SIRA10DP-T1-GE3_POWERPAK-SO8-5~D
PR203 2 1VDDP_1.35V 12 4 +V_DDR_REF
220U_6.3V_M_R18M
VDDP VTTREF
1
1 1 5.1_0603_5%
+ + PC212 1 2 VDD_1.35V 11 5 PC209

PC216
PC201
SNUB_1.35V 2 VDD VDDQ +1.35V_MEN_P
PGOOD
4
PQ203
0.033U_0402_16V7~D
TON
2 2 +5V_ALW
@EMC@
PC210
FB
S5
S3
@ 1U_0603_10V6K
2
3
2
1
10
6
2
C C
+3.3V_ALW PR211
1
@ PC211
4.7_1206_5%
0_0402_5%
@ 220P_0402_50V8J~D
1 2
PR202
1
1
PR209
2
100K_0402_1%~D PR204
+5V_ALW
@EMC@
8.06K_0402_1%~D
1.35V_FB 1 2
2
<46,7> 1.35V_SUS_PW RGD
PR205
1M_0402_1%
2
@ PR206 1.35V_B+ 1 2
1
200K_0402_5% PR207
1 2 S5_1.35V 10K_0402_1% PC214
<16,35,45> SIO_SLP_S4#
@ .1U_0402_16V7K
2
1
@ PC215 @ PR208
1
@ PR210 0_0402_5%
0_0402_5% 1U_0402_6.3V6K 1 2 S3_1.35V
<45> 0.75V_DDR_VTT_ON
1 2 2
<45,48> SUS_ON
+1.35V_MEN
Ripple voltage -
B
Static load 3% / Dynamic load 5% +1.35V_MEN_P
B
Frequency 250kHz Mode S3 S5 +1.5V_MEN +V_DDR_REF +0.675V_P
TDC 8.71A S5 L L off off off
VFB=0.75V, 1.35= 0.75*(1+PR204/PR207)
Peak Current 12.45A S3 L H on on off(Hi-Z) FB sense trace
S0 H H on on on
OCP current 14.9A
TYP MAX
H/S Rds(on) :12.2mohm , 15mohm
L/S Rds(on) :4.1mohm , 5mohm
PJP203
Choke DCR 2.35mohm 2 1
2 1
JUMP_1x3m
PJP204
+1.35V_MEN_P 2
2 1
1 +1.35V_MEM
JUMP_1x3m
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_+1.35V/0.675VSP
Date: W ednesday, May 07, 2014 Sheet 58 of 71
5 4 3 2 1
5 4 3 2 1
PJP300
+1.05VSP_B+ 2 1
+PWR_SRC
PAD-OPEN 1x2m~D
+3.3V_ALW
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
1
1
PC303
PC302
PC304
PC305
2
D D
2
5
PR300
@EMC@
100K_0402_5% @
@EMC@
PQ301
1
<46> 1.05V_A_PW RGD 4
PC306
PU300 .1U_0603_25V7K
PR301
1 10 BST_+1.05VSP 1 2 2 1
3
2
1
PGOOD VBST
PR302 2.2_0603_5%
1 2 TRIP_+1.05VSP 2 9 UG_+1.05VSP PL301
TRIP DRVH 1UH_ETQP3W 1R0W FN 11.8A_20%
93.1K_0402_1%
@ PR303 EN_+1.05VSP 3 8 SW _+1.05VSP @ PR309 1 2
150K_0402_5% EN SW 0_0402_5% +1.05V_MP
1 2 FB_+1.05VSP 4 7 +1.05VSP_5V 1 2
<16,35,45> SIO_SLP_A# VFB V5IN
+5V_ALW
10U_0805_6.3V6M
220U_6.3V_M_R18M
@ PR308 RF_+1.05VSP 5 6 LG_+1.05VSP @EMC@ 1
TST DRVL
1
0_0402_5% 1 2 PC309
1
1 2 11 +
PC301
PC310
<46,48> A_ON TP 1000P_0603_50V7K
PC308
1SNUB_1.05V 2
1
TPS51212DSCR_SON10_3X3 1U_0603_10V6K
2
2
PQ303
@ PC307
0.22U_0402_16V7K PR305 4
2
470K_0402_1%
2
3
2
1
C @EMC@ C
PR304
4.7_1206_5%
2
PR306
4.99K_0402_1%
2 1
Vout=0.7*(1+PR306/PR307)
2
PR307
10K_0402_1%
1
PJP301
+1.05V_MP 2
2 1
1 +1.05V_M
B JUMP_43X118 B
+1.05V_M
Ripple voltage -
Static load 3% / Dynamic load 5%
Frequency 290kHz
TDC 4.66A
Peak Current 6.52A
OCP current 7.8A
TYP MAX
H/S Rds(on) 24mohm , 30mohm
L/S Rds(on) 10.3mohm ,12.4mohm
Choke DCR 11mohm
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_+1.05V_MP
5 4 3 2 1
A B C D
+1.5V_RUN
Ripple voltage -
1
Frequency 1MHz 1
TDC 0.63A
Peak Current 0.9A
OCP current 4A fixed by IC
Choke DCR 27mohm
PU400 PL401
4
PJP400 1UH +-30% NRS4018T1R0NDGJ 3.2A
+3.3V_ALW 2 1 1.5VSP_VIN 10 2 1.5VSP_LX 1 2
PG
PVIN LX +1.5V_RUNP
22P_0402_50V8J
PAD-OPEN 1x2m~D 9 3
PVIN LX
1
680P_0402_50V7K
@EMC@
1
@EMC@ PC407
PC402
2 2
PC400 PC401 8
22U_0603_6.3V6M 0.1U_0402_25V6 SVIN PR402
SNUB_1.5VSP 2
6 1.5VSP_FB 30.1K_0402_1%
2
FB
47P_0402_50V8J
22U_0603_6.3V6M
22U_0603_6.3V6M
5
2
EN
1
PC403
PC404
@EMC@ PC405
NC
NC
TP
@ PR403
11
2
1 2 EN_1.5VSP
<16,35,39,40,45,62> SIO_SLP_S3#
1
.1U_0402_16V7K
0_0402_5%
1
PC406
SYN470DBC_DFN10_3X3 PR405
4.7_0805_5%
@ PR406 20K_0402_1%
@EMC@ PR401
0_0402_5%
2
1 2 @
<32,39,45,48> RUN_ON
2
<Vo=1.5V> VFB=0.6V
3
Vo=VFB*(1+PR402/PR405)=0.6*(1+30.1K/20K)=1.5V 3
PJP401
2 1
+1.5V_RUNP +1.5V_RUN
PAD-OPEN 1x2m~D
Vinafix DELL CONFIDENTIAL/PROPRIETARY

4 4

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_+1.5V_RUNP
A B C D
5 4 3 2 1
+VCCIO_OUT PR500 130_0402_1%~D

2 1
@ PR503 75_0402_5%
2 1
D PC548 D
1U_0402_6.3V6K PR504 54.9_0402_1%
1 2 2 1
VCC_core (Base on PDDG rev 1.1)
PR507=21k,Vboot=1.7V PL2 TDC 26A
Peak Current 55A
<11> VIDSOUT PR507
21K_0402_1%~D DC Load line -1.5mV/A
1 2
<11> VIDALERT_N Icc_Dyn_VID1 35A
<11> VIDSCLK PR509 OCP current 64A
3.24K_0402_1%~D
1 2 Choke DCR 0.97m ohm
@ PR511 PR512
0_0402_5% 16.9K_0402_1%~D +5V_ALW
<45> IMVP_VR_ON 1 2 1 2 FSW:400Khz
BOOT2
2
UGATE2
PR519 1.91K_0402_1% PHASE2 @ PR520
2 1 0_0402_5%
TYP MAX +PWR_SRC
+3.3V_RUN H/S Rds(on) :12.2mohm , 15mohm
<45> IMVP_PWRGD PC509 PJP500
1
1U_0603_10V6K L/S Rds(on) :2.75mohm , 3.5mohm PAD-OPEN 4x4m
32
31
30
29
28
27
26
25
1 2 1 2
VCORE_VDDP
PC500
SDA
ALERT#
SLOPE/PROG1
PROG3
PROG2
BOOT2
UGATE2
PHASE2
1 2
@EMC@
1000P_0402_50V7K PL504
1 24 LGATE2 FBMA-L11-453215-800LMA90T_1812
PR521 VR_ON 2 SCLK LGATE2 23 CPU_B+ 1 2
VR_ON VDDP
470P_0402_50V7K~D
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6K~D
97.6K_0402_1% 3 22
PGOOD PWM3
5
2 1 IMON 4 21 LGATE1
C
@ PR524 5 IMON LGATE1 20 PHASE1 PQ505 C
VR_HOT# PHASE1
1
@EMC@
EMC@
PC512
PC513
PC514
PC515
PC516
1 2 VR_HOT# 6 19 UGATE1
0_0402_5% COMP 7 NTC UGATE1 18 BOOT1
FB 8 COMP BOOT1 17
<46,50,64,65,7> H_PROCHOT#
2
FB VIN @ PR526 4
FB2/VSEN
UGATE2
0_0402_5%
ISUMN
ISUMP
NTC
ISEN3
ISEN2
ISEN1
Pull high put on HW site 33 1 2 CPU_B+
VDD
RTN
PAD
0.22U_0603_25V7K
PH500 PL502
3
2
1
470K_0402_5%_TSM0B474J4702RE 9 PU500 0.22UH_PCME064T-R22MS0R985 28A_20%~D
10
11
12
13
14
15
16
1
47P_0402_50V8J~D
2 1VCORE_NTC1 2 PR529 ISL95812HRZ-T_QFN32_4x4 PHASE2 2 1

+VCC_CORE
680P_0603_50V7K
PC510
1 2
1
PC511
PR528 PR525 PR536
@EMC@ PC524
27.4K_0402_1% 3.83K_0402_1% 6.04K_0402_1%~D PR534 PQ508 3.65K_0603_1%
SIRA06DP-T1-GE3_POWERPAK8-5
2 1 BOOT2 2 1 1 2 1 2
2
FB2/VSEN 2.2_0603_5% PR538
1SNUB_V2 2
PR530 PC522 100K_0603_1%
+5V_ALW
1
1_0402_1%~D 0.22U_0603_16V7K 1 2
1 2 LGATE2 4 PR544
ISUMP
ISEN2 10_0402_1%
4700P_0402_25V7K~D
@ PR546
4.7_1206_5%
PC520 10K_0402_5%
2
@EMC@
PR541
PR533 390PF_0402_50V7K~D PC518 +VCC_CORE 2 1
3
2
1
COMP FB 2 1 2 1 0.1U_0402_10V7K
2
1
ISUMN
PC521
Connect to PH1 output

2
909_0402_1%
10_0402_1%~D
2
PR539
499_0402_1%~D
PR537
2
PR535
2 1
PC525
2 1
1.65K_0402_1%
56P_0402_50V8J
1
2
4700P_0402_25V7K~D
1
2
1.5K_0402_1%
PC526
PR543
PR545
2K_0402_1% CPU_B+
1
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6K~D
B 1 1 1 B
100U_25V_M
100U_25V_M
100U_25V_M
2 1
PC530
PC531
PC532
PQ509 + + +
1
1
@EMC@
PC533
PC534
PC535
PC536
PC527
2 2 2
330P_0402_50V7K~D
1
2
UGATE1 4
1
4.99M_0402_1%
PC528
0.1U_0402_10V6K~D
PR558
1 2 PL503
3
2
1
0.22UH_PCME064T-R22MS0R985 28A_20%~D
PHASE1 2 1
2
+VCC_CORE
680P_0603_50V7K
PC529
.1U_0603_16V7K~D
5
@EMC@ PC543
ISEN2 @ PR548 1 2 PR550 PQ512
0_0402_5% BOOT1 2 1 1 2
1 2 2.2_0603_5% PR552 PR553
1SNUB_V1 2
ISEN1 @ PC538 PC542 3.65K_0603_1% 100K_0603_1%
0.033U_0603_16V6K~D 0.22U_0603_16V7K 1 2 1 2
1
PC539 1 2 LGATE1 4
0.022U_0402_16V6K ISEN1 PR556
<11> VCCSENSE
ISUMP
2 1 @ PR555 10_0402_1%
4.7_1206_5%
PR549 10K_0402_5%
PR554
PC540 11K_0402_1% +VCC_CORE 2 1
3
2
1
ISUMN 2
@EMC@
0.022U_0402_16V6K @ PC541 1 2
2 1 ISUMN 1 2 Connect to PH2 output
0.082U_0402_16V7K
PR551
2
PC545
330P_0402_50V7K PH501
1
10K_0402_5%_ERTJ0ER103J 2.61K_0402_1%
1 2 1 2
2
PC546 @
1 2
.1U_0402_16V7K
ISUMP
1
A A
0.01U_0402_50V7K
PC547
ISUMN
2
<11> VSSSENSE
Local sense put on HW site
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_VCORE_ISL95812 for QC
5 4 3 2 1
5 4 3 2 1
Initial voltage is 0.85V +VGA_B+

+3.3V_RUN_GFX PJP600
2 1
2 1 +PWR_SRC
PR602 10K_0402_1%~D JUMP_43X118
1 2
2200P_0402_50V7K
0.1U_0603_25V7K
10U_0805_25V6K
10U_0805_25V6K
PR604 10K_0402_1%~D @EMC@ PL602
1
1 2 FBMA-L11-453215-800LMA90T_1812
PC601
PC603
PC604
1 2
PC602
@ PR600 PR605 10K_0402_1%~D
2
0_0402_5% 1 2
1 2
@EMC@
<63> DGPU_PWR_EN
PR608 10K_0402_1%~D
@EMC@
@ PR607 1 2
10K_0402_1%
D D
1 2 PR610 10K_0402_1%~D
<16,35,39,40,45,60> SIO_SLP_S3#
1 2
@ PC600 PR614 PC605
22P_0402_50V8J PR612 10K_0402_1%~D 4.7_0603_5%~D 0.22U_0603_10V7K PQ600
1 2 1 2 BOOT2_VGA 1 2 1
BOOT2_2_VGA 2 CSD87351Q5D_SON8~D
1
+GPU_CORE
2
PR615 10K_0402_1%~D
PR616 1 2 UGATE2_VGA PL600
10K_0402_1% @ PR620 0_0402_5% 7 0.22UH_PCME064T-R22MS0R985 28A_20%~D
1 2 DPRSLPVR_R 1 2 PH2_VGA 3 6 PHASE2_VGA 2 1
GPU_VID_4 <50> 5
@ PR618 0_0402_5% LGATE2_VGA 4
680P_0603_50V7K
1 2
10K_0402_5%
3.65K_0402_1%
GPU_VID_3 <50>
1
1
+3.3V_RUN @ PR621 0_0402_5% PR624
PC607
PR619
1 1
470U_X_2VY_R9M
470U_X_2VY_R9M
1 2 1_0402_5%
PR623
GPU_VID_2 <50>
8
+ +
PC606
PC677
1SNUB_GPU_P2 2
@ PR625 0_0402_5%
2
1
1 2
@EMC@
GPU_VID_1 <50> 2 2
PR627
1.91K_0402_1% @ PR628 0_0402_5%
@ PR629 1 2 VSUM+_VGA @ PR626 VSUM-_VGA
GPU_VID_0 <50>
0_0402_5% 0_0402_5%
2
1 2 1 2+GPU_CORE
4.7_1206_5%
<20,45> DGPU_PWROK
PR622
@ PR631 0_0402_5%~D
<50> GPU_PSI# 1 2 Layout Note:
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
2 1 Connect to Phase1 Choke
@EMC@
+3.3V_RUN
2
VID6
VID0
PR691 10K_0402_1% PR632 ISEN2_VGA
47K_0402_1%~D
2 1
GNDA_GPU_CORE
@ PR633 PC608
0_0402_5% 1U_0603_10V6K
40
39
38
37
36
35
34
33
32
31
C 2 1 PU600 1 2
VID4 VID3 VID2 VID1 VID0 Vo C
<50> GPU_HOT#
0 1 1 0 1 1.175
CLK_EN#
VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON
BOOT2
30 0 1 1 1 0 1.15 GPU_CORE
GNDA_GPU_CORE 29
1 UGATE2 28 0 1 1 1 1 1.125 Frequency 400kHz
2 PGOOD PHASE2 27
PR634 PH600 3 PSI# VSSP2 26
1 0 0 0 0 1.1 TDC 33A
RBIAS LGATE2
1.4K_0402_1%~D 470K_0402_5%_TSM0B474J4702RE 4
VR_TT# VCCP
25 1 2
+5V_ALW 1 0 0 0 1 1.075 Peak Current 49.5A
2 1 1 2 NTC_VGA 5 24
6 NTC
VW
PWM3
LGATE1
23 @ PR635 1 0 0 1 0 1.05 OCP current 59.4A
7 22 0_0402_5%
8 COMP VSSP1 21 1 0 0 1 1 1.025 TYP MAX
FB PHASE1
9
ISEN3 1 0 1 0 0 1
UGATE1
VW_VGA 10 H/S Rds(on) :12.2mohm , 15mohm

BOOT1
ISUM+
ISEN2
1
1 0 1 0 1 0.975
ISEN1
ISUM-
VSEN
IMON
COMP_VGA PC610
VDD
1000P_0402_50V7K
L/S Rds(on) :2.75mohm , 3.5mohm

RTN
VIN
FB_VGA 41 1U_0603_10V6K
5.9K_0402_1%
AGND 1 0 1 1 0 0.95
1
PC611
Choke DCR 0.97mohm

2
ISL62883CHRTZ-T_TQFN40_5X5
PR638
1 0 1 1 1 0.925
11
12
13
14
15
16
17
18
19
20
PR639
2
1
499_0402_1%~D
2 1
PC612
2
GNDA_GPU_CORE 1 1 0 0 0 0.9
2
1 1 0 0 1 0.875 Bulk cap 470u 4.5mohm *4

470P_0402_50V7K~D
PC613 PR640 1 1 0 1 0 0.85 MLCC 2.2u *16 / 10u *7
ISUM-_VGA
47P_0402_50V8J~D 3.57K_0402_1%~D 1 1 0 1 1 0.825

1 2 1 2
+5V_RUN
1 1 1 0 0 0.8
@ PR643
ISEN2_VGA 0_0402_5% 1 1 1 0 1 0.775
1 2 1 2 1 2 +VGA_B+
ISEN1_VGA +VGA_B+
PC614 PR642
0.22U_0402_10V4Z
0.22U_0402_10V4Z
1
150P_0402_50V8J 324K_0402_1%~D 1 2
+5V_ALW
1
PR645
PC615
PC616
0.22U_0603_25V7K
PR644 1_0402_5%
1U_0603_10V6K
1
249K_0402_1%~D
PC617
PC618
2
BOOT1_VGA
0.1U_0603_25V7K
2
B B
10U_0805_25V6K
10U_0805_25V6K
2
1
PC619
PC621
PC622
GNDA_GPU_CORE GNDA_GPU_CORE
2
VSUM-_VGA VSUM+_VGA UGATE1_VGA
@EMC@
+GPU_CORE 1 2 VSEN_VGA PQ601
PR649 PC623 CSD87351Q5D_SON8~D
1
@ PR650 4.7_0603_5%~D 0.22U_0603_10V7K
1
0_0402_5% 1 2 BOOT1_1_VGA 1 2 2
2.61K_0402_1%
+GPU_CORE
PR648
PL601
7 0.22UH_PCME064T-R22MS0R985 28A_20%~D
PHASE1_VGA 3 6 PHASE1_VGA 2 1
2
5
0.15U_0603_16V7K
1
0.033U_0402_16V7K~D
LGATE1_VGA 4
PC624
680P_0603_50V7K
1
1
330P_0402_50V7K
PC626
PC627
PC631
10K_0402_5%
3.65K_0402_1%
2
1
PR651
1 1
470U_X_2VY_R9M
470U_X_2VY_R9M
PR654
2
SNUB_GPU_P1 2
1_0402_5% + +
PR652
PC628
PC629
GNDA_GPU_CORE
@EMC@
2
1
1
11K_0402_1%
2
1
PC630 PH601 2 2
PR655
1000P_0402_50V7K 10K_0402_1%_TSM0A103F34D1RZ
2
VSUM+_VGA VSUM-_VGA
2
Layout Note:
4.7_1206_5%
1
PR653
@ PR657 PR659 Place near Phase1 Choke @ PR656
0_0402_5% 1.18K_0402_1% 0_0402_5%
1 2 RTN_VGA 1 2 VSUM-_VGA 1 2+GPU_CORE
@EMC@
2
OCP setting ISEN1_VGA
Layout Note:
A Ri = PR659 Connect to Phase2 Choke A
1
PC632
.1U_0402_16V7K
2
PJP602
1 2
PAD-OPEN1x1m DELL CONFIDENTIAL/PROPRIETARY

GNDA_GPU_CORE GNDA_GPU_CORE
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_+GPU_CORE
5 4 3 2 1
5 4 3 2 1
VFB=0.6V Vo=VFB*(1+PR683/PR684)=0.6*(1+5.9K/10K)=0.95V
PL603
PJP609 +VGA_PCIEP
4
D PU602 1UH_FDSD0420-H-1R0M-P3T_4.9A_20% D
+3.3V_ALW 2 1 PCIE_B+ 10 2 LX_PCIE 1 2
PG
2 1 PVIN LX
9 3
JUMP_43X79 PVIN LX
680P_0402_50V7K
1
@EMC@ PC667
PC660 8
@EMC@ PC680 22U_0603_6.3V6M SVIN +VGA_PCIE (0.95V)
2
0.1U_0603_25V7K~D 6 FB_PCIE Ripple voltage -
2
FB
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
5
EN
SNUB_PCIE
1
PC661
PC662
PC663
PC664
SS
TP
LX
@ PR681 SY8036LDBC_DFN10_3x3
0_0402_5% Frequency 1MHz
11
PC666 1
2
1 2 EN_PCIE
<62,63> DGPU_PWR_EN TDC 4.2A
0.1U_0402_10V7K
1
0.1U_0402_10V7K
PR683
Peak Current 6A
1
PC665
1
5.9K_0402_1% OCP current 7.5A fixed by IC
4.7_0805_5%~D
@EMC@ PR680
2 1
@ Choke DCR 29mohm
2
PC668
1
+3.3V_RUN 2 1
C C
PR684
+VGA_PCIEP
PJP610
10K_0402_1% 22P_0402_50V8J
1
2 1
+VGA_PCIEP +VGA_PCIE
2
2 1
PR692
100K_0402_1% JUMP_43X79
2
@ PR697
0_0402_5%
1 2
DGPU_PWR_EN <62,63>
1
D
2
<53> DGPU_PWR_EN#_Q
G PJP611
PQ610 S +1.8V_RUN_VIN 2 1 +3.3V_ALW
3
DMN65D8LW-7 1N SOT323-3
1 PAD-OPEN 1x2m~D
1
PC669 PC670
1U_0603_10V4Z~D 22U_0603_6.3V6M
1.8Volt
2
2
Ripple voltage -
B Static load 3% / Dynamic load 5% B
TDC 0.43A
6
PU603
5 Peak Current 0.61A
VPP
7 VIN
POK 9
OCP 4.2A fixed by IC
TPAD
@ PR688 3
0_0402_5% VO +1.8V_RUNP
1 2 EN_+1.8V_RUN 8 4
<62,63> DGPU_PWR_EN VEN VO
22U_0603_6.3V6M
47P_0402_50V8J~D
GND
@EMC@ PC674
0.1U_0402_10V7K
2 +1.8V_RUN_FB PR687
ADJ
PC675
PC672
15K_0402_1%
1
APL5930KAI-TRG SOP 8P PJP612

1
2
2 1
1
@ +1.8V_RUNP +1.8V_RUN_GFX
2
PAD-OPEN 1x2m~D
1
PR689
12K_0402_1%
A <Vo=1.8V> Vref=0.8V DELL CONFIDENTIAL/PROPRIETARY A

2
(Tolerance must be +-1.5% to meet WCEPTA)

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_+VGA_PCIE/+1.8V_RUN_GFX
5 4 3 2 1
5 4 3 2 1
@ PD700 EMC@
2 1 PL701
1UH_MMD-05CZ-1R0M-M7L_7A_20%
ES2AA-13-F_SMA2~D 2 1
PQ700 PR701 +PWR_SRC_AC CHAGER_SRC TYP MAX
SI4835DDY-T1-GE3_SO8~D +SDC_IN 0.01_1206_1%~D H/S Rds(on) 12.2mohm , 15mohm
8 1 @ PJP700
22U_0805_25V6K
22U_0805_25V6K
+DC_IN_SS
7 2 4 1 1 2 L/S Rds(on) 2.7mohm , 3.5mohm
6 3
Choke DCR 6.2mohm
0.1U_0603_25V7K~D
1
5 3 2 PAD-OPEN 4x4m
PC724
PC728
@
Choke Itye:14.2A / Isat:15A
1
@ PR700
2
0_0402_5% @
PC700
1 2 @ PR702 @
DC_BLOCK_GC <65>
1
0_0402_5% D
@ PR710 1 2 2 PQ701
<65> CSS_GC
0_0402_5% G NTR4502PT1G_SOT23-3~D
1
D <46> VCP D
1 2 D S
3
2 PQ703A
G SI3993CDV-T1-GE3_TSOP6~D
PD701
+PWR_SRC
PQ702 S
S
2 NTR4502PT1G_SOT23-3~D 5 6
D
+DOCK_PWR_BAR DOCK_DCIN_IS+ <44>
PU703
1 6 1 Near PL700
CSSN_1
REF Out
G
CSSP_1
1
CSSN_1 3 PQ703B
+DC_IN_SS @ PR703 SI3993CDV-T1-GE3_TSOP6~D
PR744 10K_0402_5%~D
10U_0805_25V6K
10U_0805_25V6K
22U_0805_25V6K
22U_0805_25V6K
22U_0805_25V6K
BAT54CW_SOT323~D
S
44.2_0402_1%~D 2 1 2 4
D
DOCK_DCIN_IS- <44>
2 5 2 1
1
GND IN- @
PC731
PC732
PC737
PC738
PC739
100K_0402_1%
100K_0402_1%
1
1
3 4 @ PR704 PR705
G
+SDC_IN
3
V+ IN+ 0_0402_5% 0_0402_5%
PR706
2
2 1 CSSP_1 PC703 PC704 @ @ @
PR707
1
INA199A1DCKR_SC70-6~D 1U_0603_25V6K 0.1U_0402_25V6K PC705 @ PR709
1
0.1U_0603_25V7K~D
1
59_0402_1% PR742 1 2 1 2 1 2 0_0402_5%
PC720
2
PR736 10_1206_5%~D 1 2
DK_CSS_GC <65>
2
0.1U_0402_25V6K
GNDA_CHG
2
+SDC_IN GNDA_CHG PC706
1
PC707 PU700 1 2
Discrete current monitor circuit
316K_0402_1%~D
sense adapter 10U_0805_25V6K
ACN
ACP
2
2
2 1 +DCIN 20 16 BQ24715_REGN 1U_0603_10V6K~D
PR713
VCC REGN PD702
BAT54HT1G_SOD323-2~D
5
PR714
49.9K_0402_1%~D 3 17 PR715
22U_0805_25V6K
22U_0805_25V6K
22U_0805_25V6K
22U_0805_25V6K
2200P_0402_50V7K~D
1
1
2 1 CMSRC BTST
SIR472DP-T1-GE3_POWERPAK8-5
SIR472DP-T1-GE3_POWERPAK8-5
2.2_0603_5%
BOOT 1 2
BOOT_D
1
PC708
PQ704
PQ705
PC710
PC712
PC713
PC714
PC734
1 2 4 18 CHG_UGATE 4 4
ACDRV HIDRV
PC709
2
1
0.047U_0603_25V7K~D
0.1U_0402_25V6K
BQ24715_REGN
GNDA_CHG CHARGER_SMBCLK
@EMC@
C C
CHARGER_SMBDAT 6 19
3
2
1
3
2
1
ACDET PHASE CHG_PHASE
pull up 10K in HW side (R827 R828)
<46> CHARGER_SMBDAT 8 15 CHG_LGATE

SDA LODRV +PWR_SRC
1
PR741
100K_0402_1% 9 14 PL700 PR716
<46> CHARGER_SMBCLK SCL GND +VCHGR
0.01_1206_1%~D
@ PR717 2.2UH_ PCMB104E-2R2MS 14A_20%~D
2
0_0402_5% 2 1 4 1
1 2 5 13
<46,64,65> ACAV_IN ACOK SRP 3 2
10U_0805_25V6K
10U_0805_25V6K
0.1U_0603_25V7K~D
1
7 12 PC715
<46> V_SYS IOUT SRN
PR743 @EMC@
2SNUB_Charger 2
1
121K_0402_1% sense battery @ PR720 1000P_0603_50V7K~D
0_0402_5%~D
PQ706
PQ711
@EMC@
PC717
PC718
PC719
2
1 2 10 11 4 4
+3.3V_ALW
2
2
PC716 CELL /BATDRV
TP
100P_0402_50V8J~D @
680P_0603_50V7K
1
BQ24717RGRR_QFN20_3P5X3P5
21
1
PR746 10K_0402_1%~D PR721
@ PC735
3
2
1
3
2
1
BQ24715_REGN 1 2 @EMC@ @ PC721 PC722 PC723
GNDA_CHG 4.7_1206_5%~D 0.1U_0402_25V6K 0.1U_0402_25V6K 0.1U_0402_25V6K
2
GNDA_CHG 1 2 1 2 1 2
<65> CHARGER_CELL_PIN
1
@ PR747 PJP701 GNDA_CHG GNDA_CHG
0_0402_5%~D 1 2 @ PR718 0_0402_5%
1 2 1 2 SRP
+3.3V_ALW2
PAD-OPEN1x1m @ PR719
GNDA_CHG 0_0402_5%
1 2 SRN
B B
@ PR745
0_0402_5% +5V_ALW
H_PROCHOT# <46,50,61,65,7>
+5V_ALW 1 2 OP_5V PR722
0.01U_0402_25V7K~D
DYN_TUR_CURRENT_SET# 4.02K_0402_1%~D
1 2 BATDRV# <65>
1
PC725
221K_0402_1%~D
2
2
PR723
@ PR724 Judge AC form NB side not DOCK side

90W High (5.36A)
2
+3.3V_ALW2 @ 0_0402_5%
PR725
1.8M_0402_1%
1
1 2
130W Low (7.41A)
1
PR726
150K_0402_1%~D PR728
DMN66D0LDW-7 2N_SOT363-6~D
+3.3V_ALW2
8
20K_0402_1%~D PU701A
VCP 1 2 3
P
2
+ 1 BQ24715_REGN
6
2 O PQ707B
-
G
DMN66D0LDW-7 2N_SOT363-6~D +DC_IN PR734

LM393DR_SO8~D 1M_0402_1%~D
PQ707A
48.7K_0402_1%
10K_0402_1%~D
1200P_0402_50V7K
220P_0402_50V8J~D
1
1.0143V (90W) 2 5 1 2
249K_0402_1%
162K_0402_1%
232K_0402_1%~D
1
1
PC727
PR733
1.4178V (130W)
100P_0402_50V8J~D
1
+3.3V_ALW
PR730
PC736
PR732
PR735
1
4
1
OP_5V
PR731
PC726
2
2
2
2
8
1.73V PU701B @ PR737
PR748 5 0_0402_5%
P
100P_0402_50V8J~D
1
D +3.3V_ALW 100K_0402_5%~D + 7 1 2
2 6 O ACAV_IN_NB <46,65>
10K_0402_1%~D
<46> DYN_TUR_CURRNT_SET#
22.6K_0402_1%~D
42.2K_0402_1%~D
-
G
G PC733
2
100P_0402_50V8J~D
1
1
S @ PR727 0.1U_0402_10V7K~D 1.47V LM393DR_SO8~D
3
4
1
1
PQ709 0_0402_5%~D 2 1
PC729
PR738
PR739
PC730
PR740
DMN65D8LW-7_SOT323-3~D 2 1
<45> MODULE_BATT_PRES#
2
5
A PU704 A
2
1
1 D
P
4 B 2
O ACAV_IN <46,64,65>
2 G
PROCHOT_GATE <45>
G
A
S
3
PQ710
Adapter Protection Circuit for Turbo Mode DELL CONFIDENTIAL/PROPRIETARY
3
74AHC1G08GW_SSOP5~D DMN65D8LW-7_SOT323-3~D

Title
PWR_Charger for DSC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9934P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, May 07, 2014 Sheet 64 of 71
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
PC801 PR801
0.1U_0402_10V7K~D 100K_0402_5%~D
1 2 2 1
Purpose: Trigger PROCHOT# when +3.3V_ALW
active battery is removed from
5
PQ802
system.
1
SLICE_BAT_PRES# 1 D DMN65D8LW-7_SOT323-3~D
P
B 4 2
Allows EC to re-establish SLICE_BAT_ON 2 O G
G
A +3.3V_ALW
PD807 PQ801 system performance for battery S H_PROCHOT# <46,50,61,64,7>
3
PD806 SDMK0340L-7-F_SOD323-2~D NTR4502PT1G_SOT23-3~D
3
PDS5100H-13_POWERDI5-3~D next in line. PU801
1
3 +PBATT_IN_SS 2 1 3 1 74AHC1G08GW_SOT353~D
+NBDOCK_DC_IN_SS
1
1
240K_0402_5%~D
2 PR807
3
2
100K_0402_5%~D
2
PQ809
PR802
PD800 SI4835DDY-T1-GE3_SO8~D +3.3V_ALW
2
PDS5100H-13_POWERDI5-3~D 1 8 5 DMN66D0LDW-7 2N_SOT363-6~D
D 3 +BATT_SUM 2 7 PQ805B D
1
1 3 6 PR817
4
+VCHGR 2 5 PQ811 330K_0402_5%~D PR810
1
FDS6679AZ_G_SO8~D 100K_0402_5%~D
100K_0402_5%~D
2
PQ800 1 8 1 2 +3.3V_ALW2
47K_0402_5%~D
+PBATT
4
SI4835DDY-T1-GE3_SO8~D 2 S D 7
PR813
PR804
2
1 8 3 S D 6
4 S D 5
6
2 7 +3.3V_ALW
PQ806B
6 2
G D
3 6 PR808 PC805
PQ806A
1
5 100K_0402_5%~D 0.1U_0402_10V7K~D
1 2 2 DMN66D0LDW-7 2N_SOT363-6~D
PR821 PQ805A
4
2
820_0603_5% DMN66D0LDW-7 2N_SOT363-6~D 2 SLICE_BAT_ON 5 2
10K_0402_5%~D
1
1
5
<64> BATDRV# 1 2 3301_DSCHRG_FET_GC PQ807A PU804
PBAT_PRES# 1
PR815
P
1
1
B
3
SDMK0340L-7-F_SOD323-2~D
4
2 O
G
A
1
2 2
+3.3V_ALW2 PC811 DMN66D0LDW-7 2N_SOT363-6~D 5
3
0.01U_0603_25V7K~D PQ807B SLICE_BAT_PRES# <44,45,56,65>
PD818
2
@ PR812
PD811
4
0_0402_5% 74AHC1G08GW_SOT353~D 1 2
CHARGER_CELL_PIN <64>
2
+PWR_SRC_AC 1 2
<45> DIS_BAT_PROCHOT#
PR816 @ PR811
6 1
PC807 0_0402_5% SDMK0340L-7-F_SOD323-2~D

100K_0402_5%~D
1 2 1 2
0.47U_0805_25V7K~D
STSTART_DCBLOCK_GC
2
PQ812A
PDS5100H-13_POWERDI5-3~D
1
1
2
3
4
@ PR890 PQ810
PQ812B
G
S
S
S
0_0402_5% FDS6679AZ_G_SO8~D
5 1 2
PD808
SLICE_BAT_ON <45,65>
D
D
D
D
4
PBAT_PRES# <45,56> +3.3V_ALW2
8
7
6
5
2
3
PR814
330K_0402_5%~D PC808
2 1 0.1U_0402_10V7K~D
Purpose: Turn on the PQ817
2 1 for primary or module bay
PU805
+3.3V_ALW2 74AHC1G08GW_SOT353~D battery to provide power to
5
PC810
dock side without AC exist.
100K_0402_5%~D
+DOCK_PWR_BAR
2
C C
0.1U_0402_10V7K~D 1
P
B
1
@ PC809 2 1 4 SLICE_BAT_PRES# <44,45,56,65>
PR818
PU806 O 2 1 2
1500P_0402_7K~D +3.3V_ALW2
G
74AHC1G08GW_SOT353~D A PR819
5
PD810 100K_0402_5%~D
1
BAT54CW_SOT323~D 1 D
P
3 4 B 2
O DOCK_DET# <44,45,65>
2 ACAV_IN# G
G
PQ815 PQ826 1 A PQ817
S
10K_0402_5%~D
3
1
FDS6679AZ_G_SO8~D FDS6679AZ_G_SO8~D DMN65D8LW-7_SOT323-3~D
3
2
PR822
8 1 1 8
7 D S 2 2 S D 7
6 D S 3 3 S D 6
2
5 D S 4 4 S D 5
AO3418_SOT323-3
D G G D
Purpose: Turn on the PQ815
1
D
PQ816
2 +3.3V_ALW2 +3.3V_ALW2 for Slice battery discharge
@ PR894 G +3.3V_ALW2
0_0402_5%~D S PC812 without AC exist
2
+3.3V_ALW2 1 2 Vth: 0.5~1.5 0.1U_0402_10V7K~D
PQ828 2 1 PR823 PR824 @
@ PR895 DMG2301U-7 1P_SOT23-3 PU807 100K_0402_5%~D 100K_0402_5%~D
0_0402_5% 74AHC1G08GW_SOT353~D
5
3
+3.3V_ALW 1 2 3 1
1
1
P
B SLICE_BAT_ON <45,65>
1
PD813 4
O
1
3
BAT54CW_SOT323~D 2
2
2
G
PR830 PD819 A
PQ819B
100K_0402_5%~D SDMK0340L-7-F_SOD323-2~D
1
1 2 D 5 ACAV_IN#
PQ813A
DMN65D8LW-7_SOT323-3~D
PD820 PR826 2
2
12
3
SDMK0340L-7-F_SOD323-2~D DMN66D0LDW-7 2N_SOT363-6~D 240K_0402_5% 1 G @
DOCK_SMB_ALERT# <44,45,56>
4
1 2 1 6 2 1 2
PQ818
<44,45,56,65> SLICE_BAT_PRES# S
3
2
3
3
PQ813B
1
6
PR828 D PR827 PQ814
2
<45,56> AC_DIS 1 2 2 DMN66D0LDW-7 2N_SOT363-6~D 1 2 NTR4502PT1G_SOT23-3~D @ PR882 @ PR881
10K_0402_5%~D G 4 3 47K_0402_5% 0_0402_5% 0_0402_5%~D
S 2 1 +3.3V_ALW2 1 2 2 1 2
<44,45,56,65> SLICE_BAT_PRES# SLICE_PERF_EN <46,65>
3
PQ829
DMN65D8LW-7_SOT323-3~D 5 PR829 @ PQ819A
1
100K_0402_5%~D +NBDOCK_DC_IN_SS DMN66D0LDW-7 2N_SOT363-6~D
1
B @ PR831 B
SLICE_BAT_PRES# <44,45,56,65>
1
0_0805_5% @ PR832 @ PR884
2
G
1 2 0_0402_5% 0_0402_5%~D @ PR886 PQ827
+DC_IN_SS 1 2 DMN65D8LW-7_SOT323-3~D
+DOCK_PWR_BAR 0_0402_5%
3 1
2
1
S
D
0.1U_0603_50V4Z~D
3301_DSCHRG_FET_GC PD821
@ PC820
PD815 SDMK0340L-7-F_SOD323-2~D
DK_PWRBAR
1 2 CD3301_DCIN BAT54CW_SOT323~D <44,45,65> DOCK_DET# PQ821A

+DC_IN
DC_IN_SS
PR835 47_0805_5%~D @ PR838 2 <46,65> SLICE_PERF_EN DMN66D0LDW-7 2N_SOT363-6~D
NTR4502PT1G_SOT23-3~D
NTR4502PT1G_SOT23-3~D
2
2
0_0402_5% 1 6 2 1
1
PC813 1 2 +PBATT 1
DOCK_AC_OFF <44> PQ831 +3.3V_ALW2
PR839
0.1U_0603_50V4Z~D @ PR843 3 PQ821B 240K_0402_5% DMN65D8LW-7_SOT323-3~D
2
2
1
1
0_0402_5% DMN66D0LDW-7 2N_SOT363-6~D 1 1
PQ822
PQ830
P50ALW 1 2 PR844 4 3 2 2 2 1 1 3 +3.3V_ALW2
36
35
34
33
32
31
30
29
28
S
+5V_ALW
1
PU800 @ PR850 10K_0402_5%~D 2 1 +3.3V_ALW2 2 2
<56>1 SOFT_START_GC
2 0_0402_5% PR834 PC814 PR864
3 3
NC
CHARGERVR_DCIN
DK_PWRBAR
GND
NC
BLK_MOSFET_GC
DSCHRG_MOSFET_GC
DC_IN_SS
PBatt+
+3.3V_ALW2
3
@ PR847 CD_PBATT_OFF 1 2 PR849 100K_0402_5%~D 0.1U_0402_10V7K~D 100K_0402_5%~D
G
SLICE_BAT_ON <45,65>
2
2
PR846 100K_0402_5%~D 0_0402_5% 100K_0402_5%~D 2 1
<44> ACAV_DOCK_SRC# 1 2 ACAVDK_SRC 1 2 2 1
2
1
PR840
1
5
@ PR854 1 27 @ PR885 47K_0402_5% PR833 ACAV_IN#
0_0805_5% 2 DC_IN P50ALW 26 0_0402_5%~D @ PR887 100K_0402_5%~D 1
P
SS_GC PBATT_OFF B SLICE_BAT_PRES# <44,45,56,65>
+SDC_IN 1 2 ERC1 3 25 DK_AC_OFF 0_0402_5% 4
ERC1 DK_AC_OFF_EN O
1
4 24 +DC_IN_SS +PBATT 2 DOCK_DET# <44,45,65> D
ACAV_IN_NB <46,64>
2
G
5 ACAVDK_SRC ACAV_IN_NB 23 0_0402_5% A 2
<46,64,65> ACAV_IN
2
CD3301_SDC_IN 6 GND GND 22 DK_AC_OFF_EN 1 2 PU808 G

DOCK_AC_OFF_EC <45>
3
7 SDC_IN DK_AC_OFF_EN 21 PR858 74AHC1G08GW_SOT353~D S
0.1U_0603_50V4Z~D
3
<64> DC_BLOCK_GC 8 DC_BLK_GC SL_BAT_PRES# 20 @ PR857 1M_0402_5%~D <46,65> SLICE_PERF_EN PQ825
@ PC818
ACAV_IN BLKNG_MOSFET_GC
1
P33ALW2 9 19 1 2 DMN65D8LW-7_SOT323-3~D
EN_DK_PWRBAR
P33ALW2 NBDK_DCINSS <44,45,65> DOCK_DET#

<46,64,65> ACAV_IN
SS_DCBLK_GC
2
DK_CSS_GC
SLICE_BAT_PRES# <44,45,56,65>
PWR_SRC
@ PR862 @ PQ823
CSS_GC
P33ALW
0_0402_5% 37 NTR4502PT1G_SOT23-3~D
TP
ERC3
ERC2
1 2 @ PR863
GND
+3.3V_ALW2
3
1 2 3 1
+NBDOCK_DC_IN_SS
0_0402_5%~D @ PR866
CD3301BRHHR_QFN36_6X6~D 0_0402_5%
10
11
12
13
14
15
16
17
18
@ PR868 1 2 @ PQ824A
2
EN_DOCK_PWR_BAR <45>
2
0_0402_5% @ PR869DMN66D0LDW-7 2N_SOT363-6~D

0.1U_0603_25V7K~D
<64> CSS_GC P33ALW 1 2 1 2 1 2 6 1

ERC2
<64> DK_CSS_GC +3.3V_ALW

@ PR870
1
ERC3 240K_0402_5%~D 47K_0402_5%~D

PC815
A
@ PQ824B A
Vinafix.com
2
EN_DK_PWRBAR DMN66D0LDW-7 2N_SOT363-6~D

0.047U_0603_25V7K~D
2
+3.3V_ALW2 1 2 3 4
0.1U_0402_25V4Z~D
1 2
@ PR875
PC816
STSTART_DCBLOCK_GC 1M_0402_5%~D 100K_0402_5%~D

PC817
@ PR877 PR874
0_0805_5% <46,65> SLICE_PERF_EN 1 2
2
@ 3301_PWRSRC 1 2
+PWR_SRC_AC
@ PR883
0_0402_5%~D
0.1U_0603_50V4Z~D
@ PC819

2
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PWR_Selector
LA-9934P
5 4 3 2 1
5 4 3 2 1
Based on PDDG rev 1.1 Table 5-1.
+VCC_CORE +VCC_CORE
Bottom inside socket
1 1 1 1
D 1 1 1 1 1 D
+ PC905 + PC906 + @ PC907 + @ PC908
PC900 PC901 PC902 PC903 PC904
10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M
2 2 2 2 2 2 2 2 2
1 1 1 1 1 1
1
PC909 PC910 PC911 PC912 PC913 PC914
10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM + @ PC916
2 2 2 2 2 2
330U_D2_2.5VY_R9M
2
+VCC_CORE Top near socket edge
1 1 1 1 1
PC917 PC918 PC919 PC920 PC921
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2 2
Top inside socket

+GPU_CORE
C 1 1 1 1 1 C
PC922 PC923 PC924 PC925 PC926

2 2 2 2 2
2.2U_0402_6.3V
2.2U_0402_6.3V
2.2U_0402_6.3V
2.2U_0402_6.3V
2.2U_0402_6.3V
2.2U_0402_6.3V
2.2U_0402_6.3V
2.2U_0402_6.3V
1
1
PC927
PC928
PC929
PC930
PC931
PC932
PC933
PC934
2
2
1 1 1 1 1
PC935 PC936 PC937 PC938 PC939
2 2 2 2 2
2.2U_0402_6.3V
2.2U_0402_6.3V
2.2U_0402_6.3V
2.2U_0402_6.3V
2.2U_0402_6.3V
2.2U_0402_6.3V
2.2U_0402_6.3V
2.2U_0402_6.3V
1
1
PC951
PC944
PC945
PC946
PC947
PC948
PC949
PC950
1 1 1 1
PC940 PC941 PC942 PC943
2
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2
Bottom near socket edge

B B
10U_0805_4VAM
10U_0805_4VAM
10U_0805_4VAM
10U_0805_4VAM
10U_0805_4VAM
10U_0805_4VAM
10U_0805_4VAM
1 1 1 1 1 1 1
PC963
PC964
PC965
PC966
PC970
PC971
PC972
2 2 2 2 2 2 2
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_PROCESSOR DECOUPLING
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )

Request
Item Page# Title Date Issue Description Solution Description Rev.
Owner
D D
1 64 Charger 1/8 TI Change cell pin pull high reference voltage from Depop PR720 and pop PR746
X01
+3.3V_ALW to BQ24715_REGN
2 64 Charger 1/8 Compal Reduce adapter current ripple PC714,PC728,PC712,PC713,PC714,PC734 pop 22uF cap X01
3 61 VCC_CORE 1/8 Compal Reduce adapter current ripple Add input jump PJP500 and unpop PL504, PC516 pop 470pF X01
4 64 Charger 1/8 Compal Fine tune H_PROCHOT# response time. Add 0402 cap PC736(1.2nF) on PU701 pin1 X01
64 Charger 1/8 Compal Control H_PROCHOT# when AC removed. Add PR727(0 ohm) and MODULE_BATT_PRES# connect to PU701 pin1
5 X01
61 VCC_CORE 1/8 Compal Reduce noise on +VCCIO_OUT. Add 1uF cap (PC548) on +VCCIO_OUT
6 X01
HW
61 Charger 1/8 Compal For Input current sense stabilize. PC703 change from 0402 0.1uF to 0603 1uF
7 X01
C C
65 Selector 1/8 Compal For undock shutdown issue. Add PQ827 and gate connect to SLICE_BAT_PRES#.
8 X01
64 Charger 1/8 Compal To prevent charger into sleep mode when PC707 change from 1uF to 10uF.
9 X01
dual AC transient.
64 Charger 1/8 Compal Improve ACAV_IN_NB ref voltage accuracy. PR733 connect to +3.3V_ALW2. PR740 change from 12K to 10K
10 X01
PR733 change from 130k to 48.8k
61 VCC_CORE 1/8 Intersil Fine tune IMON,OCP, Iout offset. Add PR558 4.99M on ISUMP to GND. PR535 change from 432 to 499.
11 X01
PR521 change from 95.3k to 97.6k. PC500 change from 0.01u to 1000p
12 62 GPU_CORE 1/8 Compal Change enable signal to DGPU_PWR_EN. PC600 unpop, PR600 change from 10k to 0 ohm.
X01
HW
13 64 Charger 1/9 Compal Fine tune ACOK response time. PC708 change from 0.01uF to 0.1uF X01
56 DCIN 1/9 Compal GPIO net - AC_DIS# is high active. AC_DIS# cahnge to AC_DIS. X01
B 14 B
65 selector Corrent net name.
15 64 Charger 1/9 Compal Improve current sense accuracy. PR744=44.2ohm PR736=59ohm X01
16 65 Selector 1/9 Compal AC_DIS circuit modify to improve Add PD820,PQ828,PQ829,PR895. X01
output voltage level.
17 59 1.05V_VM 1/11 Compal Improve output ripple voltage. Add 10uF(PC310) on output. X01
18 62 GPU_CORE 1/11 Compal DGPU_PWR_EN# has glitch when entry S3/S4/S5. DGPU_PWR_EN# change to DGPU_PWR_EN#_Q. X01
HW
19 56 DCIN 1/14 Compal To prevent PD2 damage issue, PD2 pin5 connect to +3.3V_ALW, Add PR27 0 ohm X01
ESD team suggest pin5 connect to VCC. PD2 change from NXP(SC300001100) to AMC(SC300001G00)
20 61 GPU_CORE 1/15 AMD Add GPU_VID_4. Add GPU_VID_4 and 0ohm PR620. X01
A A
21 64 Charger 1/17 Compal Adapter protect from rating+0.75A to 2A. PR730 change from 150k to 249k X01
PR731 change from 66.5K to 162K
unpop PR727 DELL CONFIDENTIAL/PROPRIETARY
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PWR P.I.R (1/2)
5 4 3 2 1
5 4 3 2 1

Request
Owner
D D
1 56 DCIN 4/2 Compal PD2 ESD diode damange issue. ESD diode change from dual package to single
X02
ESD package(PD2,PD4)
PR26,PR27,PR103,PR110,PR118, PR208,PR210,PR211,PR308,PR309,PR406, PR511,
2 All All 4/8 Compal 0 ohm resistor change to short pad.
PR520,PR524,PR526,PR548,PR600, PR618,PR620,PR621,PR625,PR628,PR629,
X02
PR635,PR643,PR650,PR657,PR681,PR688, PR700,PR702,PR704,PR705,PR709,PR710,
PR717,PR718,PR719,PR724,PR737,PR745, PR811,PR812,PR832,PR838,PR843,PR847,
PR850,PR857,PR862,PR866,PR868,
PR882, PR886,PR887,PR890,PR895,1,PR854,PR877
3 56 DCIN 4/11 Compal Saving space. PL4 change from 0603 to 0402. X02
C C
B B
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PWR P.I.R (2/2)
5 4 3 2 1
5 4 3 2 1

Request
Owner
D D
1 37,45,46 HW 12/10/2012 Compal Change R-Pak package. Change RP3,RP4,RP5,RP6,RP9,RP13 P/N to SD309100380
X01
(Change Package from 1206 to 0804)
Change RP8 P/N to SD309470180
2 46 HW 12/10/2012 Compal Change R-Pak package. X01
(Change Package from 1206 to 0804)
3 35 HW 12/10/2012 Compal Change New TPM Chip Change U39 P/N to SA00004WQ40 (AT97SC3204-DX4A12-ABF) X01
4 28 HW 12/18/2012 Compal Impact SMT DFX stilt and solder risk. Change JLVDS1 P/N from SP01001BS00 to SP01001BT00 X01
Reserve PCH GPIO 22 for moving SP_TPM_LPC_EN from OUT65

5 20,35 HW 12/21/2012 DELL Update GPIO map to rev 3.0C X01
and add PD 100k(RH332)
6 30 HW 12/21/2012 Compal Remove non-pop item Remove R3730 X01
7 46 HW 12/21/2012 DELL Update GPIO map to rev 3.0C Add a 0ohm resistor R3772 to short RUNPWROK and AND_PWRGD X01
C C
8 28 HW 12/21/2012 DELL ATG droop Remove ATG config 1@,2@ X01
9 40 HW 12/26/2012 Compal Support Samsung Galaxy Tab charger in S3. Change USB charger P/N from SLGC55584AVTR to SLG55594AVTR X01
Inter-pair skew test issue, Change HDMI LV Shift P/N from PS8401ATQFN40GTR2-A3
10 26 HW 12/27/2012 Compal X01
PS8401 design change from A3 to A4. to PS8401ATQFN40GTR2-A4.
11 38 ME 01/02/2013 Compal JSIM1 BOSS hole update from 3.55mm to 1.7mm. Change JSIM1 P/N from 159-1000302600 to 159-1000302602 X01
12 47 ME 01/03/2013 Compal JSF1 pitch change from 0.5mm to 1.0mm Change JSF1 P/N from A520620-SCHR22 to A090620-SAHR21 X01
1.Change R1119 ,R1120 to 100K

13 30 HW 01/03/2013 COMPAL Follow Realtek recommend circuit 2.Change R1677 R1679 to 9.1 ohm X01
3.Change C958,C960 from 0603 to 0805
B B
14 28 HW 01/04/2013 COMPAL Import U148 of 2nd source U148 pin4 connect to +3.3V_ALW and remove C33 X01
R820,R818,R829,R822 change to RP14

R1125,R810,R1156,R819 change to RP15
15,17,18, R814,R920,R870,R876 change to RP16
15 HW 01/04/2013 COMPAL Import R-Pak RH168,RH329,RH125 change to RPH18
20,46 X01
RH138,RH136,RH257,RH201 change to RPH19
A 16 46 HW 01/07/2013 COMPAL Change Board ID from X00 to X01 Change R875 from 240K to 130K X01 A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT EE P.I.R (1/2)
5 4 3 2 1
5 4 3 2 1

Request
Owner
D D
17 30 HW 01/08/2013 Compal Follow EMI request Change 0 ohm to 33 ohm bead for internal SPK (L702~L705) X01
Change C470,471 from 33pF to 27pF

17,33, Change CH13,CH14 from 18pF to 12pF
18 HW 01/08/2013 Compal Follow Crystal EA result. X01
46,50 Change C743,C741 from 22pF to 27pF
Change CV94,CV95 from 10pF to 6.8pF
Change RC35 from 0hom to 0ohm short
Pop RC52 1K
19 7,16 HW 01/11/2013 Compal Follow ESD result. Add C1553 0.047u X01
Add C1554 0.047u
20 46 HW 01/11/2013 Compal Follow EMI result. Add C1555 0.047u X01
21 28 HW 01/14/2013 Compal To avoid +3.3V Camera inrush De-populate C300 10U_0805 CAP X01
C C
The RTD2136R ripple is better than
22 27 HW 01/15/2013 Compal Change C109 from 22uF to 10uF. X01
S version. The cap can be use small.
As Sun PowerPlay Clock PA request, Sun-XT

23 50 HW 01/16/2013 Compal Add GPU_VID_4 to control ~ 1.150V X01
VDDC range from 0.925 to 1.150V, so extra
VDDC_VID4 is needed
24 7 HW 03/11/2013 Compal Follow Intel DG Rev.1.5 Change RC12 from 10k to 100k. X01
Change 0 ohm resistor to short pad

25 6~45 HW 04/01/2013 Compal For Vender recommend circuit Change Q63,QV1 P/N from SB00000RV00 to SB00000ZN00
X02
Change L77 P/N from SM010022010 to SM01000MO00
26 27 HW 04/01/2013 Compal Follow Realtek recommend circuit L60,L61,L62 change to R3881,R3882,R3883(Short 0ohm) X02
B B
27 39 HW 04/01/2013 Dell Dell don't want EXP@ config on MB. Remove EXP@ config X02
Follow HDMI EA result.

28 26 HW 04/01/2013 Compal Pop R86 X02
Change repeter setting.
R955 from 1.8k to 680 ohm

R938 from 1.8k to 680 ohm
Follow Icon Brightness result.
29 24 HW 04/01/2013 Compal R958 from 620 to 680 ohm X02
Change LED resistance.
R934 from 1K to 1.8k ohm
R3671 from 1.4k to 1.8k ohm
R949 from 680 to 1.8k ohm
OZ777FJ2 enters into test mode unexpectedly

A 30 36 HW 04/01/2013 Compal Add R3884 1M ohm to GND on SD_CD# X02 A
with SD card inserted incompletely.
Title
5 4 3 2 1
5 4 3 2 1

Request
Owner
D D
31 15~23,33 HW 04/01/2013 Compal Intel ChipSet update. Change PCH C1 version to C2 version. P/N from SA00006P30L to SA00006P33L X02
Change 330uF OSCON P/N from SF000002Z00 to SF000003100 (CD14,CD36)

32 13,14,40 HW 04/01/2013 Compal Update OSCON P/N for DFX issue X02
Change 220uF OSCON P/N from SF000002Y00 to SF000003000 (C651)
33 7 HW 04/01/2013 Compal No support CPU XDP JTAG PU/PD issue Pop RC59, RC62,RH52 for Intel recommend X02
34 50 HW 04/01/2013 Compal GPU_HOT# voltage issue Change RV103 from 100k to 4.7k for AMD recommend X02
35 46 HW 04/01/2013 COMPAL Change Board ID from X01 to X02 Change R875 from 130K to 33K X02
Change R725 PU Net from WIGIG60GHZ_DIS# to WIGIG60GHZ_DIS#_R

36 37 HW 04/08/2013 COMPAL Schematic synchronous X02
Add R3885 to WLAN_RADIO_DIS#_R
C C
Add R3886 to BT_RADIO_DIS#_R
Add L706,L707(BLM15BD601SN1D)
37 30,24 HW 04/11/2013 COMPAL Sleeve / Ring2 have EMI noise. X02
Add C1556 ,C1557 (100pF)
H20 connect from GND to NC for ESD request. (EMI AGND and DGND noise)
Add C1559 47nF cap on SPKR
The system running DVD will hand
38 7,16,32 HW 04/19/2013 COMPAL Add C1558 47nF cap on POWER_SW#_MB X02
when doing ESD test.
Pop C1553
Change TMP version from DX4A12 to X4A12.
39 35 HW 04/23/2013 COMPAL TPM Chip Update. X02
P/N from SA00004WQ40 to SA00004WQ50
Change PCH from R1 to R3. P/N from SA00006P33L to SA00006P35L
15~23,33, Change PHY from R1 to R3. P/N from SA00005OO3L to SA00005OO5L
37 HW 06/04/2013 COMPAL Change chip P/N to R3 A00
49~55 Change GPU from R1 to R3. P/N from SA00006ES0L to SA00006ES1L
Change VRAM from R1 to R3. P/N from SA00006EU0L to SA00006EU1L
B 38 46 HW 06/04/2013 COMPAL Change Board ID from X02 to A00 Change R875 from 33K to 1K A00 B
Change RH177,RH178,RH179,RH181,RH182,RH183,
39 18 HW 06/04/2013 COMPAL Change 0 0hm to short 0 ohm A00
RH184,RH185 to short 0 ohm
A A
Title
5 4 3 2 1
5 4 3 2 1

Request
Owner
D D
1 27 HW 56/2014 COMPAL Remove eDP to LVDS switch Remove eDP to LVDS switch U27 and C106,C107,C108,C109,C110,C111,C112, A01(1.1)
C113,C114,C115,C116,C117,PJP67,R100,R101,R102,R103,R104,R105,R106,R107,
R108,R109,R110,R111,R112,R113,R114,R3881,R3882,R3883,U26.
eDP signal to eDP connector directly.
2 28 HW 5/6/2014 COMPAL Change eDP connector for eDP cable 1.Replace JLVDS1 by JeDP1. Modify LVDS signal to eDP signal. A01(1.1)
2.Remove C40,C41,C43,C49
3.Modify RE3762 to LV1
3 28 HW 5/6/2014 COMPAL Camra connector combine to eDP connector 1.Replace JCAM1 A01(1.1)
2.Camera signal move to JeDP1 PIN7~PIN14.
3.Confirm with ESD, Remove D8 for saving layout space.
Add C248 for +CAMERA_VDD
4 28 HW 5/6/2014 COMPAL Change DISP_ON control Remove U54,R1139,C725 A01(1.1)

C C
5 28 HW 5/6/2014 COMPAL Change BIA_PWM net 1.Modify BIA_PWM_LVDS to BIA_PWM A01(1.1)

Remove U56,R429,C727
2.Modify BIA_PWM_CVT to BIA_PWM_PCH
B B
A A
Title
Date: Friday, May 16, 2014 Sheet 78 of 78
5 4 3 2 1

Salado 14 HSW DSC MB La-9934p r1.0

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9 6 Left Side (JUSB4)

SATA 4 (SATA_TXN4/PETN1) WWAN (JMINI1)

Lane 6 Pink Pather (JMINI3)

Lane 7 Express card (JEXP1)

DDID Dock DP port 2

SY8036L G971 APL3512 TPS22966 TPS22966 TPS22966 TPS22966 TPS22965

+1.05V_RUN DELL CONFIDENTIAL/PROPRIETARY

JCPU1A Haswell rPGA EDS

SM_DRAMPWROK with DDR Power Gating Topology

JCPU1B Haswell rPGA EDS

2 2 PU/PD for JTAG signals

XDP_DBRESET# RC52 2 1 1K_0402_1%

XDP_TMS @ RC53 2 1 51_0402_1%

VCCPWRGOOD_0_R XDP_TDI @ RC54 2 1 51_0402_1%

@ SM_RCOMP0 RC58 1 2 100_0402_1% XDP_TCLK RC59 2 1 51_0402_1%

SM_RCOMP1 RC61 1 2 75_0402_1% XDP_TRST# RC62 2 1 51_0402_1%

JCPU1C Haswell rPGA EDS

COMPENSATION PU FOR eDP

CAD Note:Trace width=20 mils ,Spacing=25mil,

CFG STRAPS for CPU

PEG DEFER TRAINING

FC_G6 0: PEG Wait for BIOS for training

@ T52 PAD~D AR35 AH30

@ T53 PAD~D AR32 AH31

AT33 VSS VCC AJ26

B Place T72 close to G25 B

+VCC_CORE VCC L25

A10 AK34 B34 K10

+SA_DIMM_VREFDQ +SA_DIMM_VREFDQ_Q +1.35V_MEM

9 DQ1 VSS3 10 DDR_A_DQS#0

3 1 RD20 1 2 2_0402_1% DDR_A_D24 57 58 DDR_A_D29

DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11

DDR_A_BS0 109 110 DDR_A_RAS#

DDR_A_CAS# 115 116 M_ODT0

DDR_A_D40 147 148 DDR_A_D45

1 1 1 1 1 1 1 151 152 DDR_A_DQS#5

+ 153 154 DDR_A_DQS5

@ RD4 2 1 0_0402_5% @ RD2

0.047U_0402_16V4Z @ RD7 0_0402_5% Title

Populate RD4, De-Populate RD9 for Intel DDR3

DQS1 RESET# DDR3_DRAMRST#_R <13>

2 DDR_B_D16 39 VSS13 VSS14 40 DDR_B_D20

DDR_B_D24 57 VSS20 DQ28 58 DDR_B_D29

127 128 @ RD10 0_0402_5%

133 134 @ RD23 0_0402_5%

DDR_B_D48 163 164 DDR_B_D52

+ DDR_B_DQS#6 169 170

2 2 2 2 +3.3V_RUN DELL CONFIDENTIAL/PROPRIETARY

Open Keep CMOS SPKR AL10 BC12

RH47 2 1 51_0402_1% PCH_JTAG_TCK AB3 AT1 HDD_DET#

@ RH53 0_0402_5% PAD~D T58 @

HDA for Codec RPH10

BD21 AY45 PAD~D T63 @ PCH_CRT_RED V45 R35 PCH_DDPC_CTRLCLK <29>

* 1 1 SPI DELL CONFIDENTIAL/PROPRIETARY