Compal La-7901p r1.0 Schematics

A B C D E
COMPAL CONFIDENTIAL
MODEL NAME : QXW00
1 PCB NO : LA-7901P (DA60000PM00) 1
BOM P/N : 4619F631L01 / L02

GPIO MAP: E4_VC_GPIO_map_rev_1.1
Korbel 14 UMA--Non vPRO

Ivy/Sandy Bridge + Panther POINT(HM77w/DASH)
2 2
2012-03-03
REV : 1.0 (A00)
@ : Nopop Component
CONN@ : Connector Component
MB Type BOM P/N
TPM 43* 1@ 3@ 5@
3 3
TCM 2@ 4@ 5@
TPM DIS 2@ 3@
HM77 w/o Vpro
QM77 w/ Vpro
PCH XDP PXDP@
HDMI LOGO 46@
4 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
MB PCB Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Part Number Description
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Cover Sheet
DA60000PM00 PCB 0LH LA-7901P REV0 M/B UMA BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7901P
Date: Saturday, March 03, 2012 Sheet 1 of 61
A B C D E
A B C D E
Intel
Memory BUS
Ivy/Sandy Bridge 1.5V DDRIII 1333 /1600 MHz
DDRIII-DIMM X4
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
P12-13
Processorr
rPGA 989 Socket
1 1
P6-11
USB port 11
BT 4.0
P41
FDI x8 DMI Gen 2x 4 USB port 12

Camera
P24
Through LVDS Cable
LVDS CONN LVDS Fingerprint

P23 USB port 13 CONN
P41
HDMI CONN DPB
SATA port 4
P25 E-SATA
On IO board USB3.0 port 3 USB 3.0 Port
INTEL USB USB port 2 USB 2.0 Port
CRT CONN VGA P36
P37
For MB/DOCK Panther POINT-M
Video Switch VGA USB3.0 port 2 USB 3.0 Port
Docking VGA PI3V713-AZLEX BGA 989 Balls
2 USB port 1 USB 2.0 Port 2
P23 HM77 P36
Docking DPC USB port 0.9
USB2.0
Docking DPD SATA 3.0 Port0 P37
HDD CONN on IO board
P14~21
P27
Port1
PCIE BUS ODD CONN
P28
LPC Bus
SPI Bus
Port7 Port6 Port3 Port5 Port2 Port1
HD Audio I/F
BROADCOM Card Reader Smart card 1/2 Mini Card 1/2 Mini Card Full Mini Card
BCM5761 OZ600FJ0 Express card PP WLAN/WiFi WWAN
INT.Speaker
P30~31 P33 P35 P34 P34 P34 MDC
HDA Codec P29
USB port 10 USB port 6 USB port 4 USB port 5 P37
W25Q32BVSSIG 92HD90B2
LAN SWITCH P14 P29
3 SDXC/MMC 32M 4K sector RJ11 3
PI3L720 Combo Jack
China TCM1.2
P31 P33 DAI
SSX44B on IO board P37
P32
on Audio board
Docking LAN W25Q32BVSSIG
Discrete TPM P14
RJ45 32M 4K sector Dig. MIC
P37 AT97SC3204
on IO board P32
Option Through LVDS Cable
SMSC SIO
ECE5048 BC BUS
P39 Docking DPC
CPU XDP Port Docking DPD
P7
SMSC KBC DAI
PWM FAN EMC4021 ECE5055
PCH XDP Port
USB2.0 [3,8]
P14 P22 P22 P40 DOCKING
SATA port 5
WiFi ON/OFF
4
P37 DOCK LAN 4
DC/DC Interface TP CONN KB CONN USB3.0 [4]

P42
P41 P41
P38
LED
P43
FFS LNG3DM Compal Electronics, Inc.
P27 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT UMA Block Diagram
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
Date: Friday, March 02, 2012 Sheet 2 of 61
A B C D E
5 4 3 2 1
POWER STATES
USB 3.0 PORT# Connetion USB PORT# DESTINATION
Signal SLP SLP SLP SLP ALWAYS M SUS RUN CLOCKS
State S3# S4# S5# A# PLANE PLANE PLANE PLANE
1 NA 0 JUSB (Right side-IO/B)
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON
2 JUSB1 (Left side) 1 JUSB (Left side)
D D
S3 (Suspend to RAM) / M3 LOW HIGH HIGH HIGH ON ON ON OFF OFF
3 JUSB2 (Left side) 2 JESA1 (Leftt side ESATA)
S4 (Suspend to DISK) / M3 LOW LOW HIGH HIGH ON ON OFF OFF OFF
4 DOCKING 3 MLK DOCK
S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF
4 WLAN
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON OFF ON OFF OFF
5 WWAN
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF
PCH
*1 6 JMINI3(Flash)-for w/ Vpro
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF
*1 7 DOCKING
8 NA
PM TABLE
9 JUSB (Right side-Audio/B)
+15V_ALW +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M
C C
+5V_ALW +1.5V_MEM +3.3V_RUN +1.05V_M +1.05V_M
10 Express card/Smart Card
+3.3V_ALW_PCH +1.8V_RUN (M-OFF)
power
+3.3V_RTC_LDO +1.5V_RUN
plane 11 Bluetooth
+0.75V_DDR_VTT
+VCC_CORE
12 Camera
+1.05V_RUN_VTT
+1.05V_RUN
State 13 BIO
*1: HM76 don't support port 6,7
S0 ON ON ON ON ON
SATA DESTINATION
S3 ON ON OFF ON OFF
SATA 0 HDD
S5 S4/AC ON OFF OFF ON OFF
SATA 1 ODD/ E3 Module Bay
B
S5 S4/AC don't exist OFF OFF OFF OFF OFF PCI EXPRESS DESTINATION B
SATA 2 NA
need to update Power Status and Lane 1 MINI CARD-1 WWAN
PM Table SATA 3 NA
Lane 2 MINI CARD-2 WLAN
SATA 4 ESATA
Lane 3 Express card
SATA 5 Dock
Lane 4 None
Lane 5 1/2vMINI CARD-3 PCIE

UMA DP/HDMI Port Connetion
Port B MB HDMI Conn Lane 6 MMI
Lane 7 10/100/1G LOM

Port C Dock DP port 2
Lane 8 None
A Port D Dock DP port 1 A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Index and Config.
5 4 3 2 1
5 4 3 2 1
SIO_SLP_S3#
MODC_EN
EN_INVPWR FDC654P
+BL_PWR_SRC
D
(Q21) D
SI3456BDV SI3456BDV
ADAPTER
(Q27) (Q30)
1.05V_0.8V_PWROK
ISL95836
+VCC_GFXCORE
(PU700)
+5V_HDD +5V_MOD
+PWR_SRC
BATTERY Pop option
+5V_RUN
ALWON
RT8205
+5V_ALW
CHARGER (PU100)
C C
+3.3V_ALW
MCARD_WWAN_PWREN
MCARD_MISC_PWREN
1.05V_VTTPWRGD
AUX_EN_WOWL
SIO_SLP_S3#
PCH_ALW_ON
RUN_ON
SIO_SLP_A#
SIO_SLP_LAN#
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_S3#
AUX_ON
SUS_ON
RT8207
TPS51212 TPS51212
ISL95836 (PU200)
SYN470 TPS51461 SI3456 SI3456
(PU700) (PU500) (PU400) SI3456 SI3456 S13456 SI3456 TPS22966 SI3456
(PU300) (PU7) (Q42) (Q40)
SIO_SLP_S4#
DDR_ON
(Q38) (Q49) (Q54) (Q34) (U78) (Q58)

1.05V_0.8V_PWROK
0.75V_DDR_VTT_ON
CPU_VTT_ON
SIO_SLP_A#
SIO_SLP_S3#
SIO_SLP_S3#
CPU1.5V_S3_GATE
B
+1.5V_MEM B
+3.3V_PCIE_FLASH
+1.8V_RUN +VCC_SA +3.3V_WLAN +3.3V_ALW_PCH +3.3V_SUS +3.3V_LAN +3.3V_M
+VCC_CORE +1.05V_RUN_VTT +1.05V_M SIO_SLP_S3#
R206 +3.3V_PCIE_WWAN
Pop option
SIO_SLP_S3# AO4728 NTGS4141N
(QC3) (Q59)
+3.3V_M +3.3V_RUN +5V_RUN +3.3V_SUS
PJP8
SI4164 Pop option
(Q63)
+1.5V_CPU_VDDQ +1.5V_RUN +0.75V_DDR_VTT
+1.05V_RUN +1.0V_LAN
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Power Rail
5 4 3 2 1
5 4 3 2 1
2.2K
SMBUS Address [0x9a]
2.2K
+3.3V_ALW_PCH
H14 MEM_SMBCLK 202
DMN66D0L
C9 MEM_SMBDATA 200 DIMM1 SMBUS Address [A0]
DMN66D0L
DMN66D0L
202
PCH
DMN66D0L LAN_APE_SMB_DATA0 L09 DIMM2
D
C8 DMN66D0L 200 SMBUS Address [A4] D
LAN_APE_SMB_CLK0 L10 BCM LOM SMBUS Address [**]

G12
DMN66D0L
M16 E14 53
2.2K XDP1 SMBUS Address [TBD]
2.2K +3.3V_LAN 51
SML1_SMBDATA
2.2K
SML1_SMBCLK
+3.3V_ALW_PCH
2.2K 53
51 XDP2
A5 B6 SMBUS Address [TBD]
2.2K
3A 3A
2.2K
+3.3V_ALW 10K
A50 SIO_LAN_SMBCLK
1E +3.3V_RUN
B53 SIO_LAN_SMBDAT 10K
1E
2.2K
4
6 G Sensor
SMBUS Address [3B]
2.2K +3.3V_ALW SMBUS Address
C C
APR_EC: 0x48
B4 DOCK_SMB_CLK 127
1A SPR_EC: 0x70
DOCK_SMB_DAT
129 DOCKING MSLICE_EC: 0x72 30
1A A3 USB: 0x59
32 WWAN
AUDIO: 0x34 SMBUS Address [TBD]
SLICE_BATTERY: 0x17
2.2K SLICE_CHARGER: 0x13
+3.3V_ALW
2.2K
KBC B5 LCD_SMBCLK
1B
A4 LCD_SMDATA
1B
2.2K
+3.3V_ALW
2.2K
100 ohm 7
1C A56 PBAT_SMBCLK
6 BATTERY SMBUS Address [0x16]
1C B59 PBAT_SMBDAT 100 ohm
CONN
B B
2.2K
MEC 5055 2.2K

+3.3V_SUS
7
2B A49 CARD_SMBCLK
8 Express card SMBUS Address [TBD]
2B B52 CARD_SMBDAT
2.2K
+3.3V_ALW
2.2K
B50 10
1G CHARGER_SMBCLK
A47 9 Charger
1G CHARGER_SMBDAT SMBUS Address [0x12]
2.2K
+3.3V_ALW
2.2K
2D B7 BAY_SMBDAT
A A
2D A7 BAY_SMBCLK
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SMBUS TOPOLOGY
5 4 3 2 1
5 4 3 2 1
JCPU1I
D D
JCPU1A T35 F22
PEG_COMP VSS161 VSS234
J22 T34 F19
PEG_ICOMPI VSS162 VSS235
J21 T33 E30
DMI_CRX_PTX_N0 PEG_ICOMPO VSS163 VSS236
<16> DMI_CRX_PTX_N0 B27 H22 T32 E27
DMI_CRX_PTX_N1 DMI_RX#[0] PEG_RCOMPO VSS164 VSS237
<16> DMI_CRX_PTX_N1 B25 (1)PEG_RCOMPO (H22) use 4mil connect to PEG_ICOMPI, then T31 E24
DMI_CRX_PTX_N2 DMI_RX#[1] VSS165 VSS238
<16> DMI_CRX_PTX_N2 A25 T30 E21
DMI_CRX_PTX_N3 DMI_RX#[2] use 4mil connect to RC2. VSS166 VSS239
<16> DMI_CRX_PTX_N3 B24 K33 T29 E18
DMI_RX#[3] PEG_RX#[0] VSS167 VSS240
M35 (2)PEG_ICOMPO use 12mil connect to RC2 T28 E15
DMI_CRX_PTX_P0 PEG_RX#[1] VSS168 VSS241
<16> DMI_CRX_PTX_P0 B28 L34 T27 E13
DMI_CRX_PTX_P1 DMI_RX[0] PEG_RX#[2] VSS169 VSS242
<16> DMI_CRX_PTX_P1 B26 J35 T26 E10
DMI_CRX_PTX_P2 DMI_RX[1] PEG_RX#[3] VSS170 VSS243
<16> DMI_CRX_PTX_P2 A24 DMI_RX[2] PEG_RX#[4] J32 P9 VSS171 VSS244 E9
DMI_CRX_PTX_P3 B23
DMI
<16> DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5] H34 P8 VSS172 VSS245 E8
PEG_RX#[6] H31 P6 VSS173 VSS246 E7
<16> DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 G21 G33 P5 E6
DMI_CTX_PRX_N1 DMI_TX#[0] PEG_RX#[7] VSS174 VSS247
<16> DMI_CTX_PRX_N1 E22 DMI_TX#[1] PEG_RX#[8] G30 P3 VSS175 VSS248 E5
<16> DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 F21 F35 P2 E4
DMI_CTX_PRX_N3 DMI_TX#[2] PEG_RX#[9] VSS176 VSS249
<16> DMI_CTX_PRX_N3 D21 DMI_TX#[3] PEG_RX#[10] E34 N35 VSS177 VSS250 E3
PEG_RX#[11] E32 N34 VSS178 VSS251 E2
<16> DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 G22 D33 N33 E1
DMI_CTX_PRX_P1 DMI_TX[0] PEG_RX#[12] VSS179 VSS252
<16> DMI_CTX_PRX_P1 D22 DMI_TX[1] PEG_RX#[13] D31 N32 VSS180 VSS253 D35
<16> DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 F20 B33 N31 D32
DMI_CTX_PRX_P3 DMI_TX[2] PEG_RX#[14] VSS181 VSS254
<16> DMI_CTX_PRX_P3 C21 C32 N30 D29
PCI EXPRESS* - GRAPHICS

DMI_TX[3] PEG_RX#[15] VSS182 VSS255
N29 VSS183 VSS256 D26
PEG_RX[0] J33 N28 VSS184 VSS257 D20
PEG_RX[1] L35 N27 VSS185 VSS258 D17
PEG_RX[2] K34 N26 VSS186 VSS259 C34
<16> FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 A21 H35 M34 C31
FDI_CTX_PRX_N1 FDI0_TX#[0] PEG_RX[3] VSS187 VSS260
<16> FDI_CTX_PRX_N1 H19 FDI0_TX#[1] PEG_RX[4] H32 L33 VSS188 VSS261 C28
<16> FDI_CTX_PRX_N2 FDI_CTX_PRX_N2 E19 G34 L30 C27
<16> FDI_CTX_PRX_N3 F18 FDI0_TX#[3] PEG_RX[6] G31 L27 VSS190 VSS263 C25
<16> FDI_CTX_PRX_N4 FDI_CTX_PRX_N4 B21 F33 L9 C23
FDI1_TX#[0] PEG_RX[7] VSS191 VSS264
Intel(R) FDI
C FDI_CTX_PRX_N5 C
<16> FDI_CTX_PRX_N5 C20 FDI1_TX#[1] PEG_RX[8] F30 L8 VSS192 VSS265 C10
<16> FDI_CTX_PRX_N6 FDI_CTX_PRX_N6 D18 E35 L6 C1
<16> FDI_CTX_PRX_N7 E17 FDI1_TX#[3] PEG_RX[10] E33 L5 VSS194 VSS267 B22
F32 L4 B19
<16> FDI_CTX_PRX_P0 FDI_CTX_PRX_P0 A22 FDI0_TX[0]

PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
D34
E31
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
<16> FDI_CTX_PRX_P1 FDI_CTX_PRX_P1 G19 C33 L1 B13
FDI_CTX_PRX_P2 FDI0_TX[1] PEG_RX[14] VSS198 VSS271
<16> FDI_CTX_PRX_P2 E20 B32 K35 B11
FDI_CTX_PRX_P3 FDI0_TX[2] PEG_RX[15] VSS199 VSS272
<16> FDI_CTX_PRX_P3 G18 K32 B9
FDI_CTX_PRX_P4 FDI0_TX[3] VSS200 VSS273
<16> FDI_CTX_PRX_P4 B20 M29 K29 B8
FDI_CTX_PRX_P5 FDI1_TX[0] PEG_TX#[0] VSS201 VSS274
<16> FDI_CTX_PRX_P5 C19 M32 K26 B7
<16> FDI_CTX_PRX_P6 D19 M31 J34 B5
<16> FDI_CTX_PRX_P7 F17 L32 J31 B3
FDI1_TX[3] PEG_TX#[3] VSS204 VSS277
L29 H33 B2
FDI_FSYNC0 PEG_TX#[4] VSS205 VSS278
<16> FDI_FSYNC0 J18 K31 H30 A35
FDI_FSYNC1 FDI0_FSYNC PEG_TX#[5] VSS206 VSS279
<16> FDI_FSYNC1 J17 K28 H27 A32
FDI1_FSYNC PEG_TX#[6] VSS207 VSS280
J30 H24 A29
FDI_INT PEG_TX#[7] VSS208 VSS281
<16> FDI_INT H20 J28 H21 A26
FDI_INT PEG_TX#[8] VSS209 VSS282
H29 H18 A23
FDI_LSYNC0 PEG_TX#[9] VSS210 VSS283
<16> FDI_LSYNC0 J19 G27 H15 A20
FDI_LSYNC1 FDI0_LSYNC PEG_TX#[10] VSS211 VSS284
<16> FDI_LSYNC1 H17 E29 H13 A3
FDI1_LSYNC PEG_TX#[11] VSS212 VSS285
F27 H10
PEG_TX#[12] VSS213
(1) EDP_COMPIO use 4mil trace to RC1 PEG_TX#[13]
D28 H9
VSS214
F26 H8
(2) EDP_ICOMPO use 12mil to RC1 PEG_TX#[14] VSS215
E25 H7
EDP_COMP PEG_TX#[15] VSS216
A18 H6
eDP_COMPIO VSS217
A17 M28 H5
eDP_ICOMPO PEG_TX[0] VSS218
B16 M33 H4
eDP_HPD# PEG_TX[1] VSS219
M30 H3
PEG_TX[2] VSS220
L31 H2
PEG_TX[3] VSS221
C15 L28 H1
eDP_AUX PEG_TX[4] VSS222
D15 K30 G35
B eDP_AUX# PEG_TX[5] VSS223 B
K27 G32
PEG_TX[6] VSS224
J29 G29
eDP
PEG_TX[7] VSS225
C17 J27 G26
eDP_TX[0] PEG_TX[8] VSS226
F16 H28 G23
C16 G28 G20
G15 E28 G17
F28 G11
PEG_TX[12] VSS230
C18 D27 F34
eDP_TX#[0] PEG_TX[13] VSS231
E16 E26 F31
D16 D25 F29
F15
eDP_TX#[3]
TYCO_2134146-3_IVYBRIDGE~D
Link CIS
+1.05V_RUN_VTT +1.05V_RUN_VTT TYCO_2134146-3_IVYBRIDGE~D

Link CIS
1 2 EDP_COMP 1 2 PEG_COMP
RC1 24.9_0402_1%~D RC2 24.9_0402_1%~D
DP Compensation PEG Compensation
eDP_COMPIO and ICOMPO signals should be shorted near PEG_ICOMPI and RCOMPO signals should be shorted and routed
balls and routed with typical impedance <25 mohms with - max length = 500 mils - typical impedance = 43 mohms
A PEG_ICOMPO signals should be routed with - max length = 500 mils A
- typical impedance = 14.5 mohms
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Ivy/Sandt Bridge (1/6)
5 4 3 2 1
5 4 3 2 1
Follow DG Rev0.71 SM_DRAMPWROK topology +1.05V_RUN_VTT
+1.5V_CPU_VDDQ
+1.05V_RUN_VTT +1.05V_RUN_VTT
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
+3.3V_ALW_PCH
1
+3.3V_ALW_PCH
200_0402_1%~D
CC156 1 1
1 2 JXDP1
RC12
CC65
CC66
1 GND0 GND1 2
0.1U_0402_25V6K~D 1 2 SYS_PWROK_XDP XDP_PREQ# 3 4 CFG16 CFG16 <9>
@ RC124 1K_0402_1%~D 2 2 XDP_PRDY# OBSFN_A0 OBSFN_C0 CFG17
5 6 CFG17 <9>
2
OBSFN_A1 OBSFN_C1
5
7 GND2 GND3 8
1 XDP_OBS0 9 10 CFG0 CFG0 <9>
P
D <39,40> RUNPWROK B OBSDATA_A0 OBSDATA_C0 D
4 RUNPWROK_AND 1 2 PM_DRAM_PWRGD_CPU XDP_OBS1 11 12 CFG1 CFG1 <9>
O RC28 130_0402_1%~D OBSDATA_A1 OBSDATA_C1
<16> PM_DRAM_PWRGD 2 A Place near JXDP1 13 GND4 GND5 14
G
UC2 XDP_OBS2 15 16 CFG2 CFG2 <9>
OBSDATA_A2 OBSDATA_C2
39_0402_5%~D
74AHC1G09GW_TSSOP5~D XDP_OBS3 17 18 CFG3 CFG3 <9>
3
@ RC64
+3.3V_ALW_PCH 1 2 19 20
RC18 200_0402_1%~D CFG10 GND6 GND7 CFG8
<9> CFG10 21 OBSFN_B0 OBSFN_D0 22 CFG8 <9>
<9> CFG11 CFG11 23 24 CFG9 CFG9 <9>
OBSFN_B1 OBSFN_D1
25 GND8 GND9 26
XDP_OBS4 27 28 CFG4 CFG4 <9>
1
XDP_OBS5 OBSDATA_B0 OBSDATA_D0 CFG5
29 OBSDATA_B1 OBSDATA_D1 30 CFG5 <9>
SSM3K7002FU_SC70-3~D
The resistor for HOOK2 should beplaced XDP_OBS6
31 GND10 GND11 32
CFG6
33 OBSDATA_B2 OBSDATA_D2 34 CFG6 <9>
1
D such that the stub is very small on CFG0 net
@ QC1
XDP_OBS7 35 36 CFG7 CFG7 <9>
OBSDATA_B3 OBSDATA_D3
<11,42> RUN_ON_CPU1.5VS3# 2 37 38
G H_CPUPWRGD H_CPUPWRGD_XDP GND12 GND13 CLK_XDP
1 2 39
PWRGOOD/HOOK0 ITPCLK/HOOK4
40
S RC5 1 2 1K_0402_1%~D CFD_PWRBTN#_XDP 41 42 CLK_XDP#
<14,16> SIO_PWRBTN#_R
3
RC6 0_0402_5%~D HOOK1 ITPCLK#/HOOK5
43 44
CFG0 XDP_HOOK2 VCC_OBS_AB VCC_OBS_CD XDP_RST#_R
1 2 45
HOOK2 RESET#/HOOK6
46
RC7 1 2 1K_0402_1%~D SYS_PWROK_XDP 47 48 XDP_DBRESET#
<16,39> SYS_PWROK HOOK3 DBR#/HOOK7
@ RC9 0_0402_5%~D 49 50
DDR_XDP_SMBDAT_R1 GND14 GND15 XDP_TDO
<12,13,14,15,27,34> DDR_XDP_WAN_SMBDAT 1 2 51 52
RC125 1 DDR_XDP_SMBCLK_R1 SDA TD0 XDP_TRST#
<12,13,14,15,27,34> DDR_XDP_WAN_SMBCLK 2 0_0402_5%~D 53 54
RC127 0_0402_5%~D SCL TRST# XDP_TDI
55 56
XDP_TCLK TCK1 TDI XDP_TMS
57 58
TCK0 TMS
59 60
GND16 GND17
SAMTE_BSH-030-01-L-D-A CONN@
+1.05V_RUN_VTT
1 2 H_THERMTRIP#
@ RC126 56_0402_5%~D
1 2 H_CATERR#
@ RC128 49.9_0402_1%~D JCPU1B
1 2 H_PROCHOT#
RC44 62_0402_5%~D
C C
A28 CPU_DMI @ RC13 1 2 0_0402_5%~D
BCLK CLK_CPU_DMI <15>
C26 A27 CPU_DMI# @ RC15 1 2 0_0402_5%~D XDP_RST#_R 2 1
<18> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <15> PLTRST_XDP# <17>
MISC
CLOCKS
RC8 1K_0402_1%~D
<39> CPU_DETECT# AN34

SKTOCC# CPU_DPLL RC16 1
DPLL_REF_CLK
A16 2 1K_0402_1%~D
A15 CPU_DPLL# RC17 1 2 1K_0402_1%~D +1.05V_RUN_VTT
DPLL_REF_CLK# CLK_XDP 1 2 CLK_CPU_ITP <15>
RH107 0_0402_5%~D
H_CATERR# AL33 1 2 CLK_XDP# 1 2
CATERR# CLK_CPU_ITP# <15>
@ RC48 0_0402_5%~D RH106 0_0402_5%~D
D
DDR3_DRAMRST#_CPU
THERMAL
<40> PECI_EC AN33 PECI SM_DRAMRST# R8 3 1 DDR3_DRAMRST# <12>
4.99K_0402_1%~D
QC2 <9> CLK_XDP_ITP 1 2
BSS138W-7-F_SOT323-3~D @ RH109 0_0402_5%~D
DDR3
MISC
VR1 TOPOLOGY
G
2
1
<40,51,52> H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 <9> CLK_XDP_ITP# 1 2
PROCHOT# SM_RCOMP[0]
RC50
RC57 56_0402_5%~D A5 SM_RCOMP1 DDR_HVREF_RST @ RH108 0_0402_5%~D
SM_RCOMP[1]
0.047U_0402_16V4Z~D
Close to JCBU1 A4 SM_RCOMP2
SM_RCOMP[2]
<22> H_THERMTRIP# 1 2 H_THERMTRIP#_R AN32 1
2
THERMTRIP#
CC177
RC129 0_0402_5%~D
place RC129 near CPU
2
AP29 XDP_PRDY#
PRDY# XDP_PREQ#
PREQ# AP27
AR26 XDP_TCLK 1 2
TCK <15> DDR_HVREF_RST_PCH
AR27 XDP_TMS @ RC46 0_0402_5%~D PU/PD for JTAG signals
TMS XDP_TRST# +3.3V_RUN
PWR MANAGEMENT
AM34 AP30 1 2
JTAG & BPM
<16> H_PM_SYNC PM_SYNC TRST# <40> DDR_HVREF_RST_GATE DDR_HVREF_RST <12>

@ RC47 0_0402_5%~D
AR28 XDP_TDI_R
TDI XDP_TDO_R XDP_DBRESET# RC19 2
AP26 1 1K_0402_1%~D
TDO
<18> H_CPUPWRGD 1 2 VCCPWRGOOD_0_R AP33 UNCOREPWRGOOD
B RC25 1K_0402_5%~D B
+1.05V_RUN_VTT
AL35 XDP_DBRESET#_R RC26 2 1 0_0402_5%~D XDP_DBRESET# <14,16>
PM_DRAM_PWRGD_CPU DBR# XDP_TMS RC27 2
V8 1 51_0402_1%~D
SM_DRAMPWROK
AT28 XDP_OBS0_R RC30 1 2 0_0402_5%~D XDP_OBS0 XDP_TDI RC29 2 1 51_0402_1%~D
BPM#[0] XDP_OBS1_R RC31 0_0402_5%~D XDP_OBS1 XDP_TDI_R XDP_TDI
BPM#[1] AR29 1 2 1 2
AR30 XDP_OBS2_R RC33 1 2 0_0402_5%~D XDP_OBS2 RC23 0_0402_5%~D XDP_PREQ# @ RC32 2 1 51_0402_1%~D
PCH_PLTRST#_R BPM#[2] XDP_OBS3_R RC34 0_0402_5%~D XDP_OBS3
AR33 RESET# BPM#[3] AT30 1 2
AP32 XDP_OBS4_R RC36 1 2 0_0402_5%~D XDP_OBS4 XDP_TDO_R 1 2 XDP_TDO XDP_TDO RC35 2 1 51_0402_1%~D
BPM#[4] XDP_OBS5_R RC37 0_0402_5%~D XDP_OBS5 RC24 0_0402_5%~D
BPM#[5] AR31 1 2
AT31 XDP_OBS6_R RC38 1 2 0_0402_5%~D XDP_OBS6
BPM#[6] XDP_OBS7_R RC39 0_0402_5%~D XDP_OBS7
BPM#[7] AR32 1 2
XDP_TCLK RC40 2 1 51_0402_1%~D
For ESD concern, please put near CPU XDP_TRST# RC41 2 1 51_0402_1%~D
Link CIS
Buffered reset to CPU Place closed JCPU1 VCCPWRGOOD_0_R

SM_RCOMP0 1 2
+3.3V_RUN
10K_0402_5%~D
PECI_EC H_THERMTRIP# H_CPUPWRGD XDP_DBRESET# RC42 140_0402_1%~D
1
+1.05V_RUN_VTT SM_RCOMP1 1 2
0.1U_0402_25V6K~D
0.047U_0402_16V4Z~D
RC130
RC43 25.5_0402_1%~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
SM_RCOMP2 1 2
75_0402_1%~D
@ CE13
1 1 1 1 1 RC45 200_0402_1%~D
1
2
CC140
RC4
CC143
CC144
CC141
2 2 2 2 2
UC1 SM_RCOMP2 --> 15mil
2
1 5
A 2
NC VCC Avoid stub in the PWRGD path SM_RCOMP1/0 --> 20mil A
<14,17> PCH_PLTRST# A PCH_PLTRST#_BUF PCH_PLTRST#_R
3 GND Y 4 1
RC10
2
43_0402_5%~D while placing resistors RC25 & RC130 Max length 500mils
100P_0402_50V8J~D
SN74LVC1G07DCKR_SC70-5~D
Open drain buffer
1 ESD request
CC142
2
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Ivy/Sandy Bridge (2/6)
5 4 3 2 1
5 4 3 2 1
JCPU1C JCPU1D
D D
AB6 M_CLK_DDR0 AE2 M_CLK_DDR2

<12> DDR_A_D[0..63] SA_CK[0] M_CLK_DDR0 <12> <13> DDR_B_D[0..63] SB_CK[0] M_CLK_DDR2 <13>
AA6 M_CLK_DDR#0 AD2 M_CLK_DDR#2
DDR_A_D0 SA_CLK#[0] DDR_CKE0_DIMMA M_CLK_DDR#0 <12> DDR_B_D0 SB_CLK#[0] DDR_CKE2_DIMMB M_CLK_DDR#2 <13>
C5 V9 DDR_CKE0_DIMMA <12> C9 R9 DDR_CKE2_DIMMB <13>
DDR_A_D1 SA_DQ[0] SA_CKE[0] DDR_B_D1 SB_DQ[0] SB_CKE[0]
D5 A7
DDR_A_D2 SA_DQ[1] DDR_B_D2 SB_DQ[1]
D3 D10
D2 C8
DDR_A_D4 SA_DQ[3] M_CLK_DDR1 DDR_B_D4 SB_DQ[3] M_CLK_DDR3
D6 AA5 M_CLK_DDR1 <12> A9 AE1 M_CLK_DDR3 <13>
DDR_A_D5 SA_DQ[4] SA_CK[1] M_CLK_DDR#1 DDR_B_D5 SB_DQ[4] SB_CK[1] M_CLK_DDR#3
C6 SA_DQ[5] SA_CLK#[1] AB5 M_CLK_DDR#1 <12> A8 SB_DQ[5] SB_CLK#[1] AD1 M_CLK_DDR#3 <13>
DDR_A_D6 C2 V10 DDR_CKE1_DIMMA DDR_B_D6 D9 R10 DDR_CKE3_DIMMB
SA_DQ[6] SA_CKE[1] DDR_CKE1_DIMMA <12> SB_DQ[6] SB_CKE[1] DDR_CKE3_DIMMB <13>
DDR_A_D7 C3 DDR_B_D7 D8
F10 SA_DQ[8] G4 SB_DQ[8]
DDR_A_D9 F8 DDR_B_D9 F4
G10 SA_DQ[10] SA_CK[2] AB4 F1 SB_DQ[10] SB_CK[2] AB2
DDR_A_D11 G9 AA4 DDR_B_D11 G1 AA2
DDR_A_D12 SA_DQ[11] SA_CLK#[2] DDR_B_D12 SB_DQ[11] SB_CLK#[2]
F9 SA_DQ[12] SA_CKE[2] W9 G5 SB_DQ[12] SB_CKE[2] T9
DDR_A_D13 F7 DDR_B_D13 F5
G8 SA_DQ[14] F2 SB_DQ[14]
DDR_A_D15 G7 DDR_B_D15 G2
K4 SA_DQ[16] SA_CK[3] AB3 J7 SB_DQ[16] SB_CK[3] AA1
DDR_A_D17 K5 AA3 DDR_B_D17 J8 AB1
DDR_A_D18 SA_DQ[17] SA_CLK#[3] DDR_B_D18 SB_DQ[17] SB_CLK#[3]
K1 SA_DQ[18] SA_CKE[3] W10 K10 SB_DQ[18] SB_CKE[3] T10
DDR_A_D19 J1 DDR_B_D19 K9
J5 SA_DQ[20] J9 SB_DQ[20]
DDR_A_D21 J4 DDR_B_D21 J10
DDR_A_D22 SA_DQ[21] DDR_CS0_DIMMA# DDR_B_D22 SB_DQ[21] DDR_CS2_DIMMB#
J2 SA_DQ[22] SA_CS#[0] AK3 DDR_CS0_DIMMA# <12> K8 SB_DQ[22] SB_CS#[0] AD3 DDR_CS2_DIMMB# <13>
DDR_A_D23 K2 AL3 DDR_CS1_DIMMA# DDR_B_D23 K7 AE3 DDR_CS3_DIMMB#
DDR_A_D24 SA_DQ[23] SA_CS#[1] DDR_CS1_DIMMA# <12> DDR_B_D24 SB_DQ[23] SB_CS#[1] DDR_CS3_DIMMB# <13>
M8 SA_DQ[24] SA_CS#[2] AG1 M5 SB_DQ[24] SB_CS#[2] AD6
DDR_A_D25 N10 AH1 DDR_B_D25 N4 AE6
C DDR_A_D26 SA_DQ[25] SA_CS#[3] DDR_B_D26 SB_DQ[25] SB_CS#[3] C
N8 SA_DQ[26] N2 SB_DQ[26]
DDR_A_D27 N7 DDR_B_D27 N1
M10 SA_DQ[28] M4 SB_DQ[28]
DDR_A_D29 M9 AH3 M_ODT0 DDR_B_D29 N5 AE4 M_ODT2
DDR_A_D30 SA_DQ[29] SA_ODT[0] M_ODT1 M_ODT0 <12> DDR_B_D30 SB_DQ[29] SB_ODT[0] M_ODT3 M_ODT2 <13>
N9 SA_DQ[30] SA_ODT[1] AG3 M_ODT1 <12> M2 SB_DQ[30] SB_ODT[1] AD4 M_ODT3 <13>
DDR_A_D31 M7 AG2 DDR_B_D31 M1 AD5
DDR SYSTEM MEMORY B

SA_DQ[31] SA_ODT[2] SB_DQ[31] SB_ODT[2]
DDR SYSTEM MEMORY A
DDR_A_D32 AG6 AH2 DDR_B_D32 AM5 AE5

DDR_A_D33 SA_DQ[32] SA_ODT[3] DDR_B_D33 SB_DQ[32] SB_ODT[3]
AG5 AM6
AK6 AR3
AK5 AP3
AH5 DDR_A_DQS#[0..7] <12> AN3 DDR_B_DQS#[0..7] <13>
DDR_A_D37 SA_DQ[36] DDR_A_DQS#0 DDR_B_D37 SB_DQ[36] DDR_B_DQS#0
AH6 C4 AN2 D7
DDR_A_D38 SA_DQ[37] SA_DQS#[0] DDR_A_DQS#1 DDR_B_D38 SB_DQ[37] SB_DQS#[0] DDR_B_DQS#1
AJ5 G6 AN1 F3
AJ6 J3 AP2 K6
AJ8 M6 AP5 N3
AK8 AL6 AN9 AN5
AJ9 AM8 AT5 AP9
AK9 AR12 AT6 AK12
AH8 AM15 AP6 AP15
DDR_A_D45 SA_DQ[44] SA_DQS#[7] DDR_B_D45 SB_DQ[44] SB_DQS#[7]
AH9 AN8
AL9 AR6
AL8 AR5
AP11 DDR_A_DQS[0..7] <12> AR9 DDR_B_DQS[0..7] <13>
DDR_A_D49 SA_DQ[48] DDR_A_DQS0 DDR_B_D49 SB_DQ[48] DDR_B_DQS0
AN11 D4 AJ11 C7
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AL12 F6 AT8 G3
AM12 K3 AT9 J6
AM11 N6 AH11 M3
AL11 AL5 AR8 AN6
AP12 AM9 AJ12 AP8
AN12 AR11 AH12 AK11
AJ14 AM14 AT11 AP14
DDR_A_D57 SA_DQ[56] SA_DQS[7] DDR_B_D57 SB_DQ[56] SB_DQS[7]
AH14 AN14
B DDR_A_D58 SA_DQ[57] DDR_B_D58 SB_DQ[57] B
AL15 AR14
AK15 DDR_A_MA[0..15] <12> AT14 DDR_B_MA[0..15] <13>
AL14 AT12
DDR_A_D61 SA_DQ[60] DDR_A_MA0 DDR_B_D61 SB_DQ[60] DDR_B_MA0
AK14 AD10 AN15 AA8
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AJ15 W1 AR15 T7
DDR_A_D63 SA_DQ[62] SA_MA[1] DDR_A_MA2 DDR_B_D63 SB_DQ[62] SB_MA[1] DDR_B_MA2
AH15 W2 AT15 R7
SA_DQ[63] SA_MA[2] DDR_A_MA3 SB_DQ[63] SB_MA[2] DDR_B_MA3
W7 T6
SA_MA[3] DDR_A_MA4 SB_MA[3] DDR_B_MA4
V3 T2
V2 T4
W3 T3
DDR_A_BS0 SA_MA[6] DDR_A_MA7 DDR_B_BS0 SB_MA[6] DDR_B_MA7
<12> DDR_A_BS0 AE10 W6 <13> DDR_B_BS0 AA9 R2
DDR_A_BS1 SA_BS[0] SA_MA[7] DDR_A_MA8 DDR_B_BS1 SB_BS[0] SB_MA[7] DDR_B_MA8
<12> DDR_A_BS1 AF10 V1 <13> DDR_B_BS1 AA7 T5
DDR_A_BS2 SA_BS[1] SA_MA[8] DDR_A_MA9 DDR_B_BS2 SB_BS[1] SB_MA[8] DDR_B_MA9
<12> DDR_A_BS2 V6 W5 <13> DDR_B_BS2 R6 R3
SA_BS[2] SA_MA[9] DDR_A_MA10 SB_BS[2] SB_MA[9] DDR_B_MA10
AD8 AB7
V4 R1
W4 T1
DDR_A_CAS# SA_MA[12] DDR_A_MA13 DDR_B_CAS# SB_MA[12] DDR_B_MA13
<12> DDR_A_CAS# AE8 AF8 <13> DDR_B_CAS# AA10 AB10
DDR_A_RAS# SA_CAS# SA_MA[13] DDR_A_MA14 DDR_B_RAS# SB_CAS# SB_MA[13] DDR_B_MA14
<12> DDR_A_RAS# AD9 V5 <13> DDR_B_RAS# AB8 R5
DDR_A_WE# SA_RAS# SA_MA[14] DDR_A_MA15 DDR_B_WE# SB_RAS# SB_MA[14] DDR_B_MA15
<12> DDR_A_WE# AF9 V7 <13> DDR_B_WE# AB9 R4
SA_WE# SA_MA[15] SB_WE# SB_MA[15]
TYCO_2134146-3_IVYBRIDGE~D TYCO_2134146-3_IVYBRIDGE~D
Link CIS Link CIS
A A
Title
5 4 3 2 1
5 4 3 2 1
CFG Straps for Processor

CFG2
1 1K_0402_1%~D
@ RC51
2
D D
PEG Static Lane Reversal - CFG2 is for the 16x

1:(Default) Normal Operation; Lane #
CFG2 definition matches socket pin map definition
JCPU1E
0:Lane Reversed
AH27 @ T39 PAD~D CFG4

CFG0 VCC_DIE_SENSE
<7> CFG0 AK28 CFG[0] VSS_DIE_SENSE AH26
1K_0402_1%~D
CFG1 AK29
<7> CFG1 CFG[1]
1
CFG2 AL26
<7> CFG2 CFG[2]
@ RC52
CFG3 AL27
<7> CFG3 CFG4 CFG[3]
AK26 L7 @ T1 PAD~D
<7> CFG4 CFG[4] RSVD28
CFG5 AL29 AG7 @ T2 PAD~D
<7> CFG5 CFG6 CFG[5] RSVD29
AL30 AE7 @ T3 PAD~D
<7> CFG6
2
CFG7 CFG[6] RSVD30 @ T4 PAD~D
<7> CFG7 AM31 CFG[7] RSVD31 AK2
CFG8 AM32
<7> CFG8 CFG9 CFG[8]
AM30 W8 @ T5 PAD~D
<7> CFG9 CFG10 CFG[9] RSVD32
CFG
<7> CFG10 AM28 CFG[10]
CFG11 AM26
<7> CFG11 CFG12 CFG[11]
AN28 AT26 @ T6 PAD~D
+VCC_GFXCORE CFG13 AN31
CFG[12] RSVD33
AM33 @ T7 PAD~D Display Port Presence Strap
CFG14 CFG[13] RSVD34 @ T8 PAD~D
AN26 CFG[14] RSVD35 AJ27
1 2 VAXG_VAL_SENSE CFG15 AM27
@RC122
@ RC122 49.9_0402_1%~D CFG16 AK31
CFG[15] 1 : Disabled; No Physical Display Port
C <7> CFG16 CFG17 CFG[16] C
<7> CFG17 AN29 CFG[17] CFG4 attached to Embedded Display Port
1
100_0402_1%~D
0 : Enabled; An external Display Port device is

@ RC69
T8 @ T11 PAD~D
RSVD37 @ T13 PAD~D
VAXG_VAL_SENSE AJ31
RSVD38 J16
H16 @ T15 PAD~D connected to the Embedded Display Port
2
VSSAXG_VAL_SENSE VAXG_VAL_SENSE RSVD39 @ T16 PAD~D

AH31 VSSAXG_VAL_SENSE RSVD40 G16
VCC_VAL_SNESE AJ33
VSSAXG_VAL_SENSE VSS_VAL_SNESE VCC_VAL_SENSE CFG6
1 2 AH33
VSS_VAL_SENSE
@RC123
@ RC123 49.9_0402_1%~D
CFG5
PAD~D T22 @ AJ26 AR35 @ T17 PAD~D
RSVD5 RSVD_NCTF1
1
1K_0402_1%~D
1K_0402_1%~D
AT34 @ T18 PAD~D
RSVD_NCTF2
1
@ RC54
AT33 @ T19 PAD~D
RESERVED
RSVD_NCTF3
@RC53
@
AP35 @ T20 PAD~D
RSVD_NCTF4
RC53
AR34 @ T21 PAD~D
+VCC_CORE RSVD_NCTF5
2
1 2 VCC_VAL_SNESE PAD~D T28 @ F25
@RC120
@ RC120 49.9_0402_1%~D PAD~D T29 @ RSVD8
F24
RSVD9
100_0402_1%~D
PAD~D T30 @ F23

RSVD10
1
PAD~D T31 @ D24 B34 @ T23 PAD~D

RSVD11 RSVD_NCTF6
@ RC71
PAD~D T33 @ G25 A33 @ T24 PAD~D

PAD~D T35 @ RSVD12 RSVD_NCTF7 @ T25 PAD~D
G24 A34
E23 B35
D23 C35
PCIE Port Bifurcation Straps
2
PAD~D T38 @ RSVD15 RSVD_NCTF10

C30
VSS_VAL_SNESE PAD~D T40 @ RSVD16
1 2 A31
@RC121
@ RC121 49.9_0402_1%~D PAD~D T41 @ B30
RSVD17 11: (Default) x16 - Device 1 functions 1 and 2 disabled
PAD~D T42 @ RSVD18
B29
PAD~D T43 @ D30
RSVD19
AJ32 @ T32 PAD~D 10: x8, x8 - Device 1 function 1 enabled ; function 2
PAD~D T44 @ RSVD20 RSVD51 @ T34 PAD~D
B PAD~D T45 @
B31
A30
RSVD21 RSVD52
AK32
CFG[6:5] disabled B
PAD~D T46 @ C29
RSVD22 01: Reserved - (Device 1 function 1 disabled ; function
RSVD23
AN35
2 enabled)
BCLK_ITP CLK_XDP_ITP <7>
PAD~D T47 @ J20 AM35
PAD~D T48 @ B18
RSVD24 BCLK_ITP# CLK_XDP_ITP# <7> 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
RSVD25
PAD~D T52 @ J15 AT2 @ T49 PAD~D CFG7

RSVD27 RSVD_NCTF11 @ T50 PAD~D
AT1
RSVD_NCTF12
1K_0402_1%~D
AR1 @ T51 PAD~D
RSVD_NCTF13
1
@ RC56
B1 @ T53 PAD~D
KEY
2
Link CIS PEG DEFER TRAINING
1: (Default) PEG Train immediately
CFG7 following xxRESETB de assertion
0: PEG Wait for BIOS for training
A A
Title
5 4 3 2 1
5 4 3 2 1
JCPU1F POWER
+VCC_CORE
+1.05V_RUN_VTT
53A AG35
8.5A
VCC1
AG34 AH13
VCC2 VCCIO1
AG33 AH10
D VCC3 VCCIO2 D
AG32 AG10
VCC4 VCCIO3
AG31 AC10
VCC5 VCCIO4
AG30 Y10
VCC6 VCCIO5
AG29 U10
VCC7 VCCIO6
AG28 P10
VCC8 VCCIO7
AG27 L10
VCC9 VCCIO8
AG26 J14
VCC10 VCCIO9
AF35 J13
VCC11 VCCIO10
AF34 J12
VCC12 VCCIO11
AF33 J11
VCC13 VCCIO12
AF32 H14
VCC14 VCCIO13
AF31 VCC15 VCCIO14 H12
AF30 VCC16 VCCIO15 H11
AF29 VCC17 VCCIO16 G14
AF26 F14
PEG AND DDR

VCC20 VCCIO19
AD35 VCC21 VCCIO20 F13
AD32 VCC24 VCCIO23 E14
AD30 VCC26
AD28 VCC28 VCCIO26 D14
AC35 VCC31 VCCIO29 D11
AC34 VCC32 VCCIO30 C14
C C
AC30 VCC36 VCCIO34 B14
AC29 VCC37 VCCIO35 B12
AC28 VCC38 VCCIO36 A14
AC27 VCC39 VCCIO37 A13
AC26 A12 +1.05V_RUN_VTT
VCC40 VCCIO38
AA35 VCC41 VCCIO39 A11
AA34 VCC42
75_0402_1%~D
AA33 J23
VCC43 VCCIO40
1
AA32
VCC44
RC60
AA31
VCC45
AA30
VCC46 Note: Place the PU resistors close to CPU
AA29
VCC47 RC61 close to CPU 300 - 1500mils
AA28
2
VCC48
AA27
VCC49 H_CPU_SVIDALRT#
AA26 1 2 VIDALERT_N <51>
VCC50 RC61 43_0402_5%~D
Y35
VCC51
Y34
CORE SUPPLY
VCC52
Y33
VCC53
Y32
VCC54 +1.05V_RUN_VTT
Y31
VCC55
Y30
VCC56
130_0402_1%~D
Y29
VCC57
1
Y28
VCC58 CAD Note: Place the PU Iccmax current changed for PDDG Rev0.7
RC63
Y27
VCC59 resistors close to CPU
Y26
V35
VCC60 CPU Power Rail Table
VCC61 H_CPU_SVIDALRT# RC63 close to CPU 300 - 1500mils
V34 AJ29 S0 Iccmax
2
VCC62 VIDALERT# VIDSCLK
SVID
V33
VCC63 VIDSCLK
AJ30
VIDSOUT VIDSCLK <51> Voltage Rail Voltage Current (A)
V32 AJ28 VIDSOUT <51>
VCC64 VIDSOUT
V31
VCC65
V30
VCC66 VCC 0.65-1.3 53
B
V29
VCC67 H_CPU_SVIDALRT# must be routed between the B
V28
VCC68 VIDSOUT and VIDSCLK lines to reduce cross talk.
V27
VCC69 VCCIO 1.05 8.5
V26
U35
VCC70 18 mils spacing to others.
VCC71
U34
VCC72 VAXG 0.0-1.1 26
U33
VCC73
U32
VCC74
U31 VCCPLL 1.8 3
VCC75
U30
VCC76
U29
VCC77
U28
VCC78 +VCC_CORE VDDQ 1.5 5
U27
VCC79
U26
VCC80
R35
VCC81 VCCSA 0.65-0.9 6
100_0402_1%~D
R34
VCC82
1
R33
VCC83
RC66
R32
VCC84 +1.5V_MEM 1.5 12-16
R31
VCC85
R30
VCC86 5A to Mem controller(+1.5V_CPU_VDDQ)
R29 Place RC67, RC68 near CPU 1 @ RC75 2
2
VCC87 100_0402_1%~D 5-6A to 2 DIMMs/channel
R28
VCC88 VCCSENSE_R @ RC67 1
R27 AJ35 2 0_0402_5%~D
SENSE LINES
R26
VCC89 VCC_SENSE
AJ34 VSSSENSE_R @ RC68 1 2 0_0402_5%~D
VCCSENSE <51> 2-5A to +1.5V_RUN & +0.75V_DDR_VTT
VCC90 VSS_SENSE VSSSENSE <51>
P35
VCC91
P34 2 1 +1.05V_RUN_VTT
VCC92
100_0402_1%~D
P33 RC98 10_0402_1%~D
VCC93
1
P32 B10 VTT_SENSE VTT_SENSE <49>
VCC94 VCCIO_SENSE
RC70
P31 A10 VSSIO_SENSE_R VSSIO_SENSE_R <49>
VCC95 VSS_SENSE_VCCIO
P30
VCC96
P29
VCC97
10_0402_1%~D
P28
2
VCC98
1
P27 VCC99
RC133
A A
P26 VCC100
2
TYCO_2134146-3_IVYBRIDGE~D Title
Link CIS TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Ivy/Sandy Bridge (5/6)
5 4 3 2 1
5 4 3 2 1
+1.5V_CPU_VDDQ Source
+PWR_SRC_S +1.5V_MEM QC3 +1.5V_CPU_VDDQ
AO4304L_SO8 +V_DDR_SMREF +V_DDR_REF
+1.5V_MEM
330K_0402_5%~D
8 1
1
+3.3V_ALW2 7 2 1 2 +1.5V_CPU_VDDQ
RC72
10U_0603_6.3V6M~D
6 3 @ RC135 0_0402_5%~D
1
20K_0402_5%~D
1K_0402_1%~D
1K_0402_1%~D
5 1
1
100K_0402_5%~D
CC135
@ RC80
1 2
RC84
@
@ RC134 0_0402_5%~D
4
RC74
RC73
RUN_ON_CPU1.5VS3 2 @ QC5 +V_SM_VREF_CNT
2
D NTR4503NT1G_SOT23-3~D D
2
3
DMN66D0LDW-7_SOT363-6~D
1M_0402_5%~D
0.022U_0402_25V7K~D
1 3
1
1
QC4B
RC143
RUN_ON_CPU1.5VS3# 5
CC136
1K_0402_1%~D
1K_0402_1%~D
1
1
4
2 2
@ RC81
RC78
2
6
QC4A
<16,27,35,39,42,47,48,49> SIO_SLP_S3# 1 2
@ RC82 0_0402_5%~D RUN_ON_CPU1.5VS3
2
<40> CPU1.5V_S3_GATE 1 2 2
@ RC79 0_0402_5%~D
1
RUN_ON_CPU1.5VS3# <7,42>
JCPU1H
AT35 VSS1 VSS81 AJ22

+VCC_GFXCORE
AT22 VSS6 VSS86 AJ7
100_0402_1%~D
AT19 VSS7 VSS87 AJ4
1
AT16 AJ3
POWER VSS8 VSS88
RC99
AT13 VSS9 VSS89 AJ2
+VCC_GFXCORE JCPU1G AT7 VSS11 VSS91 AH35
1 @ RC76 2 AT4 AH34
2
100_0402_1%~D VSS12 VSS92
33A AT3 VSS13 VSS93 AH32
AT24 VAXG1 VAXG_SENSE AK35 VCC_AXG_SENSE <51> AR25 VSS14 VSS94 AH30
SENSE
LINES
AT23 VAXG2 VSSAXG_SENSE AK34 VSS_AXG_SENSE <51> AR22 VSS15 VSS95 AH29
C
AT21 VAXG3 AR19 VSS16 VSS96 AH28 C
100_0402_1%~D
AT20 VAXG4 AR16 VSS17 VSS98 AH25
1
RC100
AR24 VAXG7 AR7 VSS20 VSS101 AH16
AR23 VAXG8 AR4 VSS21 VSS102 AH7
AR21 AR2 AH4
2
VAXG9 VSS22 VSS103
AR20 VAXG10 +V_SM_VREF should AP34 VSS23 VSS104 AG9
AR18 VAXG11 SM_VREF AL1 +V_SM_VREF_CNT AP31 VSS24 VSS105 AG8
AR17 VAXG12
have 10 mil trace width AP28 VSS25 VSS106 AG4
AP24 VAXG13 AP25 VSS26 VSS107 AF6
VREF
AP20 B4 +DIMM0_1_VREF_CPU +DIMM0_1_VREF_CPU AP16 AF2
VAXG16 SA_DIMM_VREFDQ +DIMM0_1_CA_CPU VSS29 VSS110
AP18 VAXG17 SB_DIMM_VREFDQ D1 +DIMM0_1_CA_CPU AP13 VSS30 VSS111 AE35
AP17 VAXG18 AP10 VSS31 VSS112 AE34
AN24 CC178 2 1 0.1U_0402_10V7K~D AP7 AE33
VAXG19 VSS32 VSS113
AN23 VAXG20 AP4 VSS33 VSS114 AE32
AN21 VAXG21 AP1 VSS34 VSS115 AE31
AN20 +1.5V_CPU_VDDQ CC179 2 1 0.1U_0402_10V7K~D AN30 AE30
VAXG22 VSS35 VSS116
AN18 VAXG23 6A AN27 VSS36 VSS117 AE29
AN17 AN25 AE28
5A VSS
DDR3 -1.5V RAILS
VAXG24 CC149 VSS37 VSS118

AM24 VAXG25 VDDQ1 AF7 2 1 0.1U_0402_10V7K~D +1.5V_MEM AN22 VSS38 VSS119 AE27
GRAPHICS
AM23 VAXG26 VDDQ2 AF4 AN19 VSS39 VSS120 AE26

AM21 VAXG27 VDDQ3 AF1 1 AN16 VSS40 VSS121 AE9
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
330U_D2_2VM_R6M~D
AM20 AC7 1 1 1 1 1 1 CC150 2 1 0.1U_0402_10V7K~D AN13 AD7
VAXG28 VDDQ4 + VSS41 VSS122
AM18 VAXG29 VDDQ5 AC4 AN10 VSS42 VSS123 AC9
CC161
CC162
CC163
CC164
CC165
CC166
CC167
AM17 VAXG30 VDDQ6 AC1 AN7 VSS43 VSS124 AC8
AL24 VAXG31 VDDQ7 Y7 AN4 VSS44 VSS125 AC6
2 2 2 2 2 2 2
AL23 VAXG32 VDDQ8 Y4 AM29 VSS45 VSS126 AC5
AL21 VAXG33 VDDQ9 Y1 AM25 VSS46 VSS127 AC3
AL20 VAXG34 VDDQ10 U7 AM22 VSS47 VSS128 AC2
AL18 VAXG35 VDDQ11 U4 AM19 VSS48 VSS129 AB35
AL17 VAXG36 VDDQ12 U1 AM16 VSS49 VSS130 AB34
AK24 VAXG37 VDDQ13 P7 AM13 VSS50 VSS131 AB33
B AK23 VAXG38 VDDQ14 P4 AM10 VSS51 VSS132 AB32 B
AK21 VAXG39 VDDQ15 P1 AM7 VSS52 VSS133 AB31
AK20 VAXG40 AM4 VSS53 VSS134 AB30
AK18 +1.5V_CPU_VDDQ AM3 AB29
VAXG41 VSS54 VSS135
AK17 VAXG42 AM2 VSS55 VSS136 AB28
AJ24 +VCC_SA AM1 AB27
VAXG43 VSS56 VSS137
AJ23 VAXG44 1 AL34 VSS57 VSS138 AB26
1 2 +DIMM0_1_VREF_CPU AJ21 VAXG45 6A CC151 AL31 VSS58 VSS139 Y9
@ RC96 1K_0402_1%~D AJ20 @ AL28 Y8
VAXG46 VSS59 VSS140
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
330U_D2_2VM_R6M~D
1 2 +DIMM0_1_CA_CPU AJ18 VAXG47 0.1U_0402_10V7K~D AL25 VSS60 VSS141 Y6
2
@ CC168
@ RC97 1K_0402_1%~D AJ17 M27 1 1 1 1 1 AL22 Y5

VAXG48 VCCSA1 VSS61 VSS142
CC169
CC170
CC171
AH24 VAXG49 VCCSA2 M26 AL19 VSS62 VSS143 Y3
SA RAIL
CC172
AH23 L26 + AL16 Y2
VAXG50 VCCSA3 VSS63 VSS144
AH21 VAXG51 VCCSA4 J26 AL13 VSS64 VSS145 W35
2 2 2 2
2 +1.5V_MEM
AH17 VAXG54 VCCSA7 H26 AL4 VSS67 VSS148 W32
VCCSA8 H25 AL2 VSS68 VSS149 W31
AK33 VSS69 VSS150 W30
1 1 AK27 VSS71 VSS152 W28
CC153 CC152 AK25 W27
@ @ VSS72 VSS153
+1.8V_RUN 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D
1.8V RAIL
VCCSA_SENSE H23 VCCSA_SENSE <50> AK19 VSS74 VSS155 U9

2 2
1.2A AK16 VSS75 VSS156 U8
AK13 VSS76 VSS157 U6
B6 VCCPLL1 AK10 VSS77 VSS158 U5
A6 VCCPLL2 VCCSA_VID[0] C22 VCCSA_VID_0 <50> AK7 VSS78 VSS159 U3
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
330U_D2_2.5VM_R6M~D
MISC
1 1 1 1 A2 VCCPLL3 VCCSA_VID[1] C24 VCCSA_VID_1 <50> AK4 VSS79 VSS160 U2

AJ25 VSS80
CC173
CC174
CC175
CC176
+
ESD Request
2 2 2
VCCIO_SEL A19 1 2 VCCP_PWRCTRL <49>
2 @ RC140 0_0402_5%~D
A
TYCO_2134146-3_IVYBRIDGE~D Depop RC140 for ES2 CPU A
Link CIS
Link CIS
Title
5 4 3 2 1
5 4 3 2 1
All VREF traces should

have 10 mil trace width
JDIMM1 Rev Type H=8mm
<8> DDR_A_DQS#[0..7]
2-3A to 1 DIMMs/channel
<8> DDR_A_D[0..63]
+DIMM1_VREF_DQ
<8> DDR_A_DQS[0..7] +1.5V_MEM +1.5V_MEM
+V_DDR_REFA_M3 1 2
@ RD7 0_0402_5%~D JDIMM1
<8> DDR_A_MA[0..15]
+V_DDR_REF 1 2 1 2
@ RD1 0_0402_5%~D VREF_DQ VSS1 DDR_A_D4
3 VSS2 DQ4 4
D DDR_A_D0 5 6 DDR_A_D5 D
DDR_A_D1 DQ0 DQ5 +1.5V_MEM
7 DQ1 VSS3 8
2.2U_0603_6.3V6K~D
0.1U_0402_25V6K~D
9 10 DDR_A_DQS#0
VSS4 DQS#0 DDR_A_DQS0
11 12
Populate RD1, De-Populate RD7 for Intel DDR3 1 1 DM0 DQS0
1K_0402_1%~D
13 VSS5 VSS6 14
1
CD1
CD2
DDR_A_D2 15 16 DDR_A_D6
VREFDQ multiple methods M1 DQ2 DQ6
RD27
2 2 DQ3 DQ7
Populate RD7, De-Populate RD1 for Intel DDR3 DDR_A_D8
19
21
VSS7 VSS8 20
22 DDR_A_D12
DDR_A_D9 DQ8 DQ12 DDR_A_D13
VREFDQ multiple methods M3 23 24
2
DQ9 DQ13
25 VSS9 VSS10 26
DDR_A_DQS#1 27 28
DDR_A_DQS1 DQS#1 DM1 DDR3_DRAMRST#_R
29 DQS1 RESET# 30 <13> DDR3_DRAMRST#_R 1 2 DDR3_DRAMRST# <7>
31 32 RD28 1K_0402_1%~D
DDR_A_D10 VSS11 VSS12 DDR_A_D14
33 34
35 36
DQ11 DQ15
37 38
39 40
41 42
Layout Note: 43
DQ17
VSS15
DQ21
VSS16
44
DDR_A_DQS#2 45 46
Place near JDIMM1 DDR_A_DQS2 47
49
DQS#2
DQS2
DM2
VSS17
48
50 DDR_A_D22 @ RD29 1 2 0_0402_5%~D
DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 52
DDR_A_D19 DQ18 DQ23
53 54
DQ19 VSS19 DDR_A_D28 QD1
55 56
VSS20 DQ28
D
DDR_A_D24 57 58 DDR_A_D29 +DIMM0_1_VREF_CPU 3 1 BSS138_NL_SOT23-3 +V_DDR_REFA_M3
+1.5V_MEM DDR_A_D25 DQ24 DQ29
59 60
DQ25 VSS21 DDR_A_DQS#3
61 62
63 64
G
2
DM3 DQS3
65 66
VSS23 VSS24
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
DQ26 DQ30 <7> DDR_HVREF_RST
1 1 1 1 DDR_A_D27 69 70 DDR_A_D31
DQ27 DQ31
71 72
VSS25 VSS26
CD3
CD4
CD5
CD6
2 2 2 2 @ RD30 1 2 0_0402_5%~D
C <8> DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA <8> C
CKE0 CKE1
75 76
VDD1 VDD2 DDR_A_MA15 QD2
77 78
NC1 A15
D
79 80 DDR_A_MA14 +DIMM0_1_CA_CPU 3 1 BSS138_NL_SOT23-3 +V_DDR_REFB_M3
<8> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 VDD3 VDD4 DDR_A_MA11
83 84
+1.5V_MEM DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 86
G
2
A9 A7
87 88
DDR_A_MA8 VDD5 VDD6 DDR_A_MA6 DDR_HVREF_RST
89 A8 A6 90
DDR_A_MA5 91 92 DDR_A_MA4
A5 A4
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
93 VDD7 VDD8 94
DDR_A_MA3 95 96 DDR_A_MA2
A3 A2 M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
330U_SX_2VY~D
1 DDR_A_MA1 97 98 DDR_A_MA0
A1 A0
1 1 1 1 1 1 1 99 VDD9 VDD10 100
CD7
CD8
CD9
CD10
CD11
CD51
CD13
CD14
+ 101 102
<8> M_CLK_DDR0 CK0 CK1 M_CLK_DDR1 <8>
<8> M_CLK_DDR#0 103 CK0# CK1# 104 M_CLK_DDR#1 <8>
105 VDD11 VDD12 106
2 2 2 2 2 2 2 2 DDR_A_MA10 107 108
A10/AP BA1 DDR_A_BS1 <8>
<8> DDR_A_BS0 109 BA0 RAS# 110 DDR_A_RAS# <8>
111 VDD13 VDD14 112
<8> DDR_A_WE# 113 WE# S0# 114 DDR_CS0_DIMMA# <8>
<8> DDR_A_CAS# 115 CAS# ODT0 116 M_ODT0 <8>
117 VDD15 VDD16 118
DDR_A_MA13 119 120
A13 ODT1 M_ODT1 <8> +DIMM1_VREF_CA
<8> DDR_CS1_DIMMA# 121 S1# NC2 122
123 VDD17 VDD18 124
125 NCTEST VREF_CA 126 2 1 +V_DDR_REF
127 128 @ RD11 0_0402_5%~D
VSS27 VSS28
2.2U_0603_6.3V6K~D
0.1U_0402_25V6K~D
DDR_A_D32 129 130 DDR_A_D36
131 132
Layout Note: 133
DQ33
VSS29
DQ37
VSS30 134 1 1
CD15
CD16
DDR_A_DQS#4 135 136
Place near JDIMM1.203,204 DDR_A_DQS4 137
139
DQS#4
DQS4
DM4
VSS31 138
140 DDR_A_D38
DDR_A_D34 VSS32 DQ38 DDR_A_D39 2 2
141 DQ34 DQ39 142
DDR_A_D35 143 144
DQ35 VSS33 DDR_A_D44
145 VSS34 DQ44 146
B DDR_A_D40 147 148 DDR_A_D45 B
DDR_A_D41 DQ40 DQ45
149 DQ41 VSS35 150
151 152 DDR_A_DQS#5
153 DM5 DQS5 154
+0.75V_DDR_VTT 155 156
157 DQ42 DQ46 158
DDR_A_D43 159 160 DDR_A_D47
DQ43 DQ47
161 VSS39 VSS40 162
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
DDR_A_D48 163 164 DDR_A_D52

1 1 1 1 165 DQ49 DQ53 166
167 VSS41 VSS42 168
CD17
CD18
CD19
CD20
DDR_A_DQS#6 169 170

DDR_A_DQS6 DQS#6 DM6
171 DQS6 VSS43 172
2 2 2 2 173 174 DDR_A_D54
DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 DQ50 DQ55 176
DDR_A_D51 177 178
DQ51 VSS45 DDR_A_D60
179 VSS46 DQ60 180
DDR_A_D56 181 182 DDR_A_D61
DDR_A_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_A_DQS#7
187 DM7 DQS7 188
189 VSS49 VSS50 190
DDR_A_D58 191 192 DDR_A_D62
+3.3V_RUN DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 DQ59 DQ63 194
195 VSS51 VSS52 196
DIMM1_SA0 197 198
SA0 EVENT#
199 VDDSPD SDA 200 DDR_XDP_WAN_SMBDAT <7,13,14,15,27,34>
DIMM1_SA1 201 202
SA1 SCL DDR_XDP_WAN_SMBCLK <7,13,14,15,27,34>
0.1U_0402_25V6K~D
2.2U_0603_6.3V6K~D
+0.75V_DDR_VTT 203 VTT1 VTT2 204 +0.75V_DDR_VTT

1 1
1 2 DIMM1_SA0 205 206
G1 G2
CD21
CD22
RD2 10K_0402_5%~D
LCN_DAN06-K4806-0103
1 2 DIMM1_SA1 2 2 CONN@
RD3 10K_0402_5%~D
Link CIS
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDRIII-SODIMM SLOT1
5 4 3 2 1
5 4 3 2 1
<8> DDR_B_DQS#[0..7]
All VREF traces should
have 10 mil trace width
JDIMM2 Rev Type H=4
<8> DDR_B_D[0..63] 2-3A to 1 DIMMs/channel
<8> DDR_B_DQS[0..7] +V_DDR_REF 1 2
@ RD4 0_0402_5%~D +DIMM2_VREF_DQ +1.5V_MEM
JDIMM2 +1.5V_MEM
<8> DDR_B_MA[0..15]
+V_DDR_REFB_M3 1 2 1 VREF_DQ VSS 2
@ RD8 0_0402_5%~D 3 4 DDR_B_D4
VSS DQ4
2.2U_0603_6.3V6K~D
0.1U_0402_25V6K~D
D DDR_B_D0 5 6 DDR_B_D5 D
DDR_B_D1 DQ0 DQ5
7 DQ1 VSS 8
1 1 9 10 DDR_B_DQS#0
VSS DQS0#
CD23
CD24
11 12 DDR_B_DQS0
DM0 DQS0
13 VSS VSS 14
DDR_B_D2 15 16 DDR_B_D6
2 2 DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18
19 20
Populate RD4, De-Populate RD8 for Intel DDR3 DDR_B_D8 21
VSS VSS
22 DDR_B_D12
DDR_B_D9 DQ8 DQ12 DDR_B_D13
VREFDQ multiple methods M1 23
25
DQ9 DQ13 24
26
DDR_B_DQS#1 VSS VSS
Populate RD8, De-Populate RD4 for Intel DDR3 DDR_B_DQS1
27
29
DQS1# DM1 28
30
DQS1 RESET# DDR3_DRAMRST#_R <12>
VREFDQ multiple methods M3 DDR_B_D10
31
33
VSS VSS 32
34 DDR_B_D14
35 DQ11 DQ15 36
37 VSS VSS 38
41 DQ17 DQ21 42
43 VSS VSS 44
DDR_B_DQS#2 45 46
Layout Note: DDR_B_DQS2 47
DQS2#
DQS2
DM2
VSS 48
49 50 DDR_B_D22
VSS DQ22
Place near JDIMM2 DDR_B_D18
DDR_B_D19
51
53
DQ18 DQ23 52
54
DDR_B_D23
DQ19 VSS DDR_B_D28
55 VSS DQ28 56
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS 60
61 62 DDR_B_DQS#3
VSS DQS3# DDR_B_DQS3
63 DM3 DQS3 64
65 VSS VSS 66
+1.5V_MEM DDR_B_D26 67 68 DDR_B_D30
69 DQ27 DQ31 70
71 VSS VSS 72
C C
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1 1 1 1 <8> DDR_CKE2_DIMMB 73 CKE0 CKE1 74 DDR_CKE3_DIMMB <8>
75 VDD VDD 76
CD25
CD26
CD27
CD28
77 78 DDR_B_MA15
DDR_B_BS2 NC A15 DDR_B_MA14
<8> DDR_B_BS2 79 BA2 A14 80
2 2 2 2
81 VDD VDD 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD VDD 88
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD VDD 94
+1.5V_MEM DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD VDD 100
M_CLK_DDR2 101 102 M_CLK_DDR3
<8> M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 <8>
M_CLK_DDR#2 103 104 M_CLK_DDR#3
<8> M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3 <8>
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
105 VDD VDD 106

DDR_B_MA10 107 108 DDR_B_BS1 DDR_B_BS1 <8>
A10/AP BA1
330U_SX_2VY~D
1 DDR_B_BS0 109 110 DDR_B_RAS#

<8> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <8>
1 1 1 1 1 1 1 111 VDD VDD 112
CD29
CD30
CD31
CD32
CD33
CD34
CD35
CD36
+ DDR_B_WE# 113 114

<8> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <8>
DDR_B_CAS# 115 116 M_ODT2
<8> DDR_B_CAS# CAS# ODT0 M_ODT2 <8>
117 VDD VDD 118
2 2 2 2 2 2 2 2 DDR_B_MA13 M_ODT3 +DIMM2_VREF_CA
119 A13 ODT1 120 M_ODT3 <8>
<8> DDR_CS3_DIMMB# 121 S1# NC 122
123 VDD VDD 124
125 TEST VREF_CA 126 2 1 +V_DDR_REF
127 128 @ RD15 0_0402_5%~D
VSS VSS
2.2U_0603_6.3V6K~D
0.1U_0402_25V6K~D
DDR_B_D32 129 130 DDR_B_D36
131 DQ33 DQ37 132
133 VSS VSS 134 1 1
CD38
DDR_B_DQS#4 135 136
DQS4# DM4
CD37
DDR_B_DQS4 137 138
DQS4 VSS DDR_B_D38
B 139 VSS DQ38 140 B
DDR_B_D34 DDR_B_D39 2 2
141 DQ34 DQ39 142
DDR_B_D35 143 144
Layout Note: 145
DQ35
VSS
VSS
DQ44 146 DDR_B_D44
DDR_B_D40 147 148 DDR_B_D45
Place near JDIMM2.203,204 DDR_B_D41 149
151
DQ40
DQ41
DQ45
VSS 150
152 DDR_B_DQS#5
VSS DQS5# DDR_B_DQS5
153 DM5 DQS5 154
155 VSS VSS 156
DDR_B_D42 157 158 DDR_B_D46
159 DQ43 DQ47 160
161 VSS VSS 162
DDR_B_D48 163 164 DDR_B_D52
+0.75V_DDR_VTT DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 DQ49 DQ53 166
167 VSS VSS 168
DDR_B_DQS#6 169 170
DDR_B_DQS6 DQS6# DM6
171 DQS6 VSS 172
173 174 DDR_B_D54
VSS DQ54
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
DDR_B_D50 175 176 DDR_B_D55

DDR_B_D51 DQ50 DQ55
1 1 1 1 177 DQ51 VSS 178
179 180 DDR_B_D60
VSS DQ60
CD39
CD40
CD41
CD42
DDR_B_D56 181 182 DDR_B_D61

DDR_B_D57 DQ56 DQ61
183 DQ57 VSS 184
2 2 2 2 DDR_B_DQS#7
185 VSS DQS7# 186
187 188 DDR_B_DQS7
DM7 DQS7
189 VSS VSS 190
DDR_B_D58 191 192 DDR_B_D62
193 DQ59 DQ63 194
+3.3V_RUN 195 196
DIMM2_SA0 VSS VSS
197 SA0 EVENT# 198
199 VDDSPD SDA 200 DDR_XDP_WAN_SMBDAT <7,12,14,15,27,34>
0.1U_0402_25V6K~D
2.2U_0603_6.3V6K~D
DIMM2_SA1 201 202

SA1 SCL DDR_XDP_WAN_SMBCLK <7,12,14,15,27,34>
+0.75V_DDR_VTT 203 VTT VTT 204 +0.75V_DDR_VTT
1 1
CD43
CD44
A
205 GND1 GND2 206 A
207 BOSS1 BOSS2 208
+3.3V_RUN
2 2
2 1 DIMM2_SA1 LCN_DAN06-K4406-0103
RD5 10K_0402_5%~D CONN@
2 1 DIMM2_SA0 Link CIS DELL CONFIDENTIAL/PROPRIETARY

RD6 10K_0402_5%~D
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDRIII-SODIMM SLOT2
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW_PCH JXDP2
1 2
GND0 GND1 XDP_FN16
3 4
+RTC_CELL +3.3V_ALW_PCH OBSFN_A0 OBSFN_C0 XDP_FN17
5 6
+3.3V_ALW_PCH OBSFN_A1 OBSFN_C1
7 8
XDP_FN0 GND2 GND3 XDP_FN8
9 10
1
330K_0402_1%~D
1K_0402_1%~D
0.1U_0402_25V6K~D
USB_OC0#_R PXDP@ RH1 1 2 33_0402_5%~D XDP_FN0 XDP_FN1 11 12 XDP_FN9
<17> USB_OC0#_R OBSDATA_A1 OBSDATA_C1
1
RH66
PXDP@ CH1
USB_OC1#_R PXDP@ RH3 1 2 33_0402_5%~D XDP_FN1 1 13 14
RH38 <17> USB_OC1#_R USB_OC2# PXDP@ RH4 33_0402_5%~D XDP_FN2 XDP_FN2 GND4 GND5 XDP_FN10
<17> USB_OC2# 1 2 15 16
USB_OC3# PXDP@ RH5 33_0402_5%~D XDP_FN3 XDP_FN3 OBSDATA_A2 OBSDATA_C2 XDP_FN11
1 2 17 18
<17> USB_OC3# USB_OC4#_R PXDP@ RH6 33_0402_5%~D XDP_FN4 OBSDATA_A3 OBSDATA_C3
1 2 19 20
2
<17> USB_OC4#_R USB_OC5# PXDP@ RH7 33_0402_5%~D XDP_FN5 2 GND6 GND7
1 2 21 22
2
<17> USB_OC5# USB_OC6# PXDP@ RH8 33_0402_5%~D XDP_FN6 OBSFN_B0 OBSFN_D0

<17> USB_OC6# 1 2 23 24
PCH_INTVRMEN PCH_AZ_SYNC SIO_EXT_SMI# PXDP@ RH9 33_0402_5%~D XDP_FN7 OBSFN_B1 OBSFN_D1
<17,40> SIO_EXT_SMI# 1 2 25 26
SLP_ME_CSW_DEV# PXDP@ RH10 33_0402_5%~D XDP_FN8 XDP_FN4 GND8 GND9 XDP_FN12
<18,39> SLP_ME_CSW_DEV#
1 2 27 28
OBSDATA_B0 OBSDATA_D0
1
330K_0402_1%~D
100K_0402_5%~D
USB_MCARD1_DET# PXDP@ RH12 1 2 33_0402_5%~D XDP_FN9 XDP_FN5 29 30 XDP_FN13
<18,34> USB_MCARD1_DET# OBSDATA_B1 OBSDATA_D1
1
@ RH282
HDD_DET#_R PXDP@ RH13 1 2 33_0402_5%~D XDP_FN10 31 32
GND10 GND11
@ RH39
BBS_BIT0_R PXDP@ RH14 1 2 33_0402_5%~D XDP_FN11 XDP_FN6 33 34 XDP_FN14

D PCH_GPIO36 PXDP@ RH15 33_0402_5%~D XDP_FN12 XDP_FN7 OBSDATA_B2 OBSDATA_D2 XDP_FN15 D
<18> PCH_GPIO36 1 2 35 36
PCH_GPIO37 PXDP@ RH16 33_0402_5%~D XDP_FN13 RH283 PXDP@ 1K_0402_1%~D OBSDATA_B3 OBSDATA_D3
1 2 37 38
2
<18> PCH_GPIO37 PCH_GPIO16 PXDP@ RH17 33_0402_5%~D XDP_FN14 GND12 GND13 +3.3V_ALW_PCH
1 2 <40,51> 1.05V_0.8V_PWROK 1 2 1.05V_0.8V_PWROK_R 39 40
2
<18> PCH_GPIO16 TEMP_ALERT# PXDP@ RH18 33_0402_5%~D XDP_FN15 PWRGOOD/HOOK0 ITPCLK/HOOK4

<18,39> TEMP_ALERT# 1 2 <7,16> SIO_PWRBTN#_R 1 2 PCH_PWRBTN#_XDP 41 42
PCH_GPIO15 PXDP@ RH19 33_0402_5%~D XDP_FN16 RH21 PXDP@ 0_0402_5%~D HOOK1 ITPCLK#/HOOK5
<18> PCH_GPIO15 1 2 43 44
SIO_EXT_SCI#_R PXDP@ RH20 33_0402_5%~D XDP_FN17 VCC_OBS_AB VCC_OBS_CD RSMRST#_XDP
<18> SIO_EXT_SCI#_R 1 2 45 46
PCH_RSMRST#_Q PXDP@ RH24 1K_0402_1%~D RSMRST#_XDP HOOK2 RESET#/HOOK6 XDP_DBRESET#
<16,41> PCH_RSMRST#_Q 1 2 47 48
RH284 PXDP@ 0_0402_5%~D HOOK3 DBR#/HOOK7 XDP_DBRESET# <7,16>
49 50
DDR_XDP_WAN_SMBDAT_R2 GND14 GND15 PCH_JTAG_TDO
INTVRMEN- Integrated SUS <7,12,13,15,27,34> DDR_XDP_WAN_SMBDAT 1 2
DDR_XDP_WAN_SMBCLK_R2
51
SDA TD0
52
1.1V VRM Enable PCH_AZ_SYNC is sampled <7,12,13,15,27,34> DDR_XDP_WAN_SMBCLK

RH285
1 2
0_0402_5%~D
53
SCL TRST#
54
PCH_JTAG_TDI
55 56
at the rising edge of RSMRST# pin. PXDP@ PCH_JTAG_TCK TCK1 TDI PCH_JTAG_TMS
High - Enable Internal VRs 57 58
TCK0 TMS
So signal should be PU to the ALWAYS rail. 59 60
Low - Enable External VRs GND16 GND17
CH2 SAMTE_BSH-030-01-L-D-A CONN@
2 1 PCH_RTCX1
10M_0402_5%~D
15P_0402_50V8J~D
1
RH2
YH1
32.768KHZ_12.5PF_Q13FC1350000~D UH4A
2
A20 C38 LPC_LAD0
LPC_LAD0 <32,34,39,40>
2
CH3 RTCX1 FWH0 / LAD0 LPC_LAD1
A38 LPC_LAD1 <32,34,39,40>
+RTC_CELL PCH_RTCX2_R PCH_RTCX2 FWH1 / LAD1 LPC_LAD2 +3.3V_RUN
2 1 1 2 C20 B37
LPC
RTCX2 FWH2 / LAD2 LPC_LAD2 <32,34,39,40>
@ RH286 0_0402_5%~D C37 LPC_LAD3
FWH3 / LAD3 LPC_LAD3 <32,34,39,40>
RH22 1 2 20K_0402_5%~D 15P_0402_50V8J~D PCH_RTCRST# D20
RTCRST# LPC_LFRAME# PCH_GPIO33 RH355 2
D36 LPC_LFRAME# <32,34,39,40> 1 100K_0402_5%~D
RH23 1 FWH4 / LFRAME#
2 20K_0402_5%~D SRTCRST# G22
SRTCRST# IRQ_SERIRQ RH28 2
E36 1 8.2K_0402_5%~D
RH11 1 LDRQ0#
2 1M_0402_5%~D INTRUDER# K22 K36 LPC_LDRQ1#
RTC
INTRUDER# LDRQ1# / GPIO23 LPC_LDRQ1# <39>
BBS_BIT0_R RH52 2 1 4.7K_0402_5%~D
@ CH100 PCH_INTVRMEN C17 V5 IRQ_SERIRQ
INTVRMEN SERIRQ IRQ_SERIRQ <32,39,40>
2 1 HDD_DET# RH30 2 1 10K_0402_5%~D
1 2 1 2 27P_0402_50V8J~D AM3 SPKR @ RH35 2 1 10K_0402_5%~D

1 2 1 2 SATA0RXN PSATA_PRX_DTX_N0_C <27>
1 2 PCH_AZ_BITCLK N34 AM1
<37> PCH_AZ_MDC_BITCLK HDA_BCLK SATA0RXP PSATA_PRX_DTX_P0_C <27>
RH32 33_0402_5%~D AP7 HDD
SATA 6G
SATA0TXN PSATA_PTX_DRX_N0_C <27>
<37> PCH_AZ_MDC_SYNC 1 2 PCH_AZ_SYNC_Q PCH_AZ_SYNC L34 AP5 PSATA_PTX_DRX_P0_C <27> No Reboot Strap
@ @ RH33 33_0402_5%~D HDA_SYNC SATA0TXP
ME1 SHORT PADS~D CMOS1 SHORT PADS~D T10 AM10 Low = Default
<29> SPKR SPKR SATA1RXN SATA_ODD_PRX_DTX_N1_C <28>
1 2 1 2 AM8 SATA_ODD_PRX_DTX_P1_C <28> SPKR
C 1U_0402_6.3V6K~D SATA1RXP C
CH5 1U_0402_6.3V6K~D CH4
<37> PCH_AZ_MDC_RST# 1 2 PCH_AZ_RST# K34
HDA_RST# SATA1TXN
AP11 SATA_ODD_PTX_DRX_N1_C <28> ODD/ E Module Bay High = No Reboot
CMOS place near DIMM RH34 33_0402_5%~D AP10
SATA1TXP SATA_ODD_PTX_DRX_P1_C <28>
PCH_AZ_CODEC_SDIN0 E34 AD7
<29> PCH_AZ_CODEC_SDIN0 HDA_SDIN0 SATA2RXN
AD5
PCH_AZ_MDC_SDIN1 SATA2RXP
<37> PCH_AZ_MDC_SDIN1 G34 AH5
HDA_SDIN1 SATA2TXN +3.3V_ALW_PCH
CMOS_CLR1 CMOS setting SATA2TXP
AH4
C34
@ RH287 HDA_SDIN2
Shunt Clear CMOS +3.3V_ALW_PCH 1 2 1K_0402_1%~D AB8
IHDA
SATA3RXN
A34 AB10
RH36 HDA_SDIN3 SATA3RXP
Open Keep CMOS <37> PCH_AZ_MDC_SDOUT 1 2 33_0402_5%~D AF3 PCH_GPIO13 R712 2 1 100K_0402_5%~D
SATA3TXN
AF1
RH50 SATA3TXP
<39> ME_FWP 1 2 1K_0402_1%~D PCH_AZ_SDOUT A36
HDA_SDO
ME_CLR1 TPM setting Y7
SATA
+3.3V_ALW_PCH SATA4RXN ESATA_PRX_DTX_N4_C <36>
Y5 ESATA_PRX_DTX_P4_C <36>
SATA4RXP
Shunt Clear ME RTC Registers PCH_GPIO33 C36
HDA_DOCK_EN# / GPIO33 SATA4TXN
AD3 ESATA_PTX_DRX_N4_C <36> E-SATA
AD1 ESATA_PTX_DRX_P4_C <36>
SATA4TXP
1
0_0603_5%~D
Open Keep ME RTC Registers PCH_GPIO13 N32

@ HDA_DOCK_RST# / GPIO13
Y3 SATA_PRX_DKTX_N5_C <38>
SATA5RXN
RH288
Y1 SATA_PRX_DKTX_P5_C <38>
SATA5RXP
SATA5TXN
AB3 SATA_PTX_DKRX_N5_C <38> DOCK
RH59 2 1 51_0402_1%~D PCH_JTAG_TCK J3 AB1
2
JTAG_TCK SATA5TXP SATA_PTX_DKRX_P5_C <38>

+3.3V_ALW_PCH_JTAG RH44 2 1 200_0402_1%~D PCH_JTAG_TMS H7 Y11 +1.05V_RUN
JTAG_TMS SATAICOMPO
JTAG
RH45 2 1 200_0402_1%~D PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
JTAG_TDI SATAICOMPI RH40 37.4_0402_1%~D
RH29 1 2 33_0402_5%~D PCH_AZ_SDOUT RH43 2 1 200_0402_1%~D PCH_JTAG_TDO H1
<29> PCH_AZ_CODEC_SDOUT JTAG_TDO +1.05V_RUN
AB12
RH26 1 PCH_AZ_SYNC_Q SATA3RCOMPO
<29> PCH_AZ_CODEC_SYNC 2 33_0402_5%~D
100_0402_1%~D
100_0402_1%~D
100_0402_1%~D
AB13 SATA3_COMP 1 2
SATA3COMPI
1
RH27 1 2 33_0402_5%~D PCH_AZ_RST# @ @ @ RH42 49.9_0402_1%~D

<29> PCH_AZ_CODEC_RST#
RH48
RH49
RH47
RH25 1 2 33_0402_5%~D PCH_AZ_BITCLK PCH_SPI_CLK T3 AH1 RBIAS_SATA3 1 2

<29> PCH_AZ_CODEC_BITCLK SPI_CLK SATA3RBIAS RH46 750_0402_1%~D
27P_0402_50V8J~D
1 PCH_SPI_CS0# Y14
2
SPI_CS0#
@ CH101
PCH_SPI_CS1# T1
SPI_CS1# SATA_ACT#
P3
SPI
2 SATALED# SATA_ACT# <43>
PCH_SPI_DO V4 V14 HDD_DET#_R @ RH290 1 2 0_0402_5%~D
SPI_MOSI SATA0GP / GPIO21 HDD_DET# <27>
B PCH_SPI_DIN U3 P1 BBS_BIT0_R 1 3 B
S
SPI_MISO SATA1GP / GPIO19 PCH_SATA_MOD_EN# <40>
QH1
+5V_RUN PCH_SPI_CLK BD82HM77 QPRG C1_BGA989~D BSS138W-7-F_SOT323-3~D
G
2
<7,17> PCH_PLTRST#
10P_0402_50V8J~D
2
G
1
@ CE15
1 2 PCH_AZ_SYNC_Q 3 1 PCH_AZ_SYNC
RH31 1M_0402_5%~D BBS_BIT0 - BIOS BOOT STRAP BIT 0
S
2
QH7
JSPI1
INTEL HDA_SYNC isolation circuit 0_0402_5%~D 2 1 RH345 SPI_PCH_CS1# 1
Close to UH4.T3 PCH_SPI_CS1# 2
1
0_0402_5%~D SPI_PCH_DO 2
2 1 RH346 3
PCH_SPI_DO 3
4
0_0402_5%~D 4
2 1 RH347 SPI_PCH_DIN 5
+3.3V_SPI PCH_SPI_DIN 5
6
+3.3V_SPI C745 0_0402_5%~D 6
2 1 RH348 SPI_PCH_CLK 7
C746 PCH_SPI_CLK 7
1 2 8
0_0402_5%~D 8
1 2 2 1 RH349 SPI_PCH_CS0# 9
0.1U_0402_25V6K~D PCH_SPI_CS0# 9
10
10
3.3K_0402_5%~D
0.1U_0402_25V6K~D +3.3V_SPI 11
11
1
3.3K_0402_5%~D
+3.3V_M_RUN 12
1
12
R890
13
200 MIL SO8 13
R891
U53 2 1 14
SPI_PCH_CS1# R936 1 14
2 47_0402_5%~D SPI_PCH_CS1#_R 1 8 RH360 0_0603_5%~D 15
64Mb Flash ROM SPI_PCH_DIN R895 1 2 33_0402_5%~D SPI_DIN32 2
CS# VCC
7 SPI_HOLD# +3.3V_RUN 16
15
2
U52 SPI_WP#_SEL_R DO HOLD# SPI_CLK32 R897 1 16

3 6 2 33_0402_5%~D SPI_PCH_CLK
2
SPI_PCH_CS0# WP# CLK +3.3V_M_RUN

1 2 SPI_PCH_CS0#_R 1 8 4 5 SPI_DO32 R900 1 2 33_0402_5%~D SPI_PCH_DO 2 1
R935 47_0402_5%~D /CS VCC GND DI @ RH359 0_0603_5%~D 17
SPI_PCH_DIN +3.3V_M G1
1 2 SPI_DIN64 2 7 SPI_HOLD# W25Q32BVSSIG_SO8~D 18
R894 33_0402_5%~D DO /HOLD G2
1 2 SPI_WP#_SEL_R 3 6 SPI_CLK64 1 2 SPI_PCH_CLK 2 1
<39> SPI_WP#_SEL
@ R898 0_0402_5%~D /WP CLK R899 33_0402_5%~D 200 MIL SO8 SPI_CLK32 RH350 0_0603_5%~D
4 5 SPI_DO64 1 2 SPI_PCH_DO
GND DIO 32Mb Flash ROM
33_0402_5%~D 27P_0402_50V8J~D
R901 33_0402_5%~D HRS_FH12-16S-0P5SH(55)~D

1
CONN@
@ RE2
W25Q64CVSSIG_SO8
A SPI_CLK64 A
33_0402_5%~D 27P_0402_50V8J~D
HM76(w/o vpro): depop RH350 and pop RH359

1
2
@ RE1
QM77(w/ vpro) : pop RH350 and depop RH359

1
@ CE2
2
2
1
@ CE1
2 Close to U53 Compal Electronics, Inc.

Title
PCH (1/8)
Size Document Number Rev
Close to U52 1.0
LA-7901P
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW_PCH +3.3V_RUN
2
6 1 MEM_SMBCLK MEM_SMBCLK 6 1
<30,40> SIO_LAN_SMBCLK DDR_XDP_WAN_SMBCLK <7,12,13,14,27,34>
QH8A QH5A
5
DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D
3 4 MEM_SMBDATA MEM_SMBDATA 3 4
<30,40> SIO_LAN_SMBDATA DDR_XDP_WAN_SMBDAT <7,12,13,14,27,34>
D QH8B QH5B D
UH4B
+3.3V_ALW_PCH
PCIE_PRX_WANTX_N1 BG34
<34> PCIE_PRX_WANTX_N1 PERN1
PCIE_PRX_WANTX_P1 BJ34 E12 PCH_SMB_ALERT#
<34> PCIE_PRX_WANTX_P1 PERP1 SMBALERT# / GPIO11
WWAN (Mini Card 1)---> PCIE_PTX_WANRX_N1 AV32 SML1_SMBCLK RH298 1 2 2.2K_0402_5%~D
<34> PCIE_PTX_WANRX_N1 PCIE_PTX_WANRX_P1 PETN1 MEM_SMBCLK
<34> PCIE_PTX_WANRX_P1 AU32 H14
PETP1 SMBCLK SML1_SMBDATA RH299 1 2 2.2K_0402_5%~D
PCIE_PRX_WLANTX_N2 BE34 C9 MEM_SMBDATA
<34> PCIE_PRX_WLANTX_N2 PERN2 SMBDATA
PCIE_PRX_WLANTX_P2 BF34 DDR_HVREF_RST_PCH RH300 2 1 1K_0402_1%~D
<34> PCIE_PRX_WLANTX_P2 PERP2
WLAN (Mini Card 2)---> PCIE_PTX_WLANRX_N2 BB32
<34> PCIE_PTX_WLANRX_N2 PETN2 RH301
<34> PCIE_PTX_WLANRX_P2
PCIE_PTX_WLANRX_P2 AY32 PCH_GPIO74 2 1 10K_0402_5%~D
PETP2 DDR_HVREF_RST_PCH
A12
SMBUS
PCIE_PRX_EXPTX_N3 SML0ALERT# / GPIO60 DDR_HVREF_RST_PCH <7> MEM_SMBCLK RH302
<35> PCIE_PRX_EXPTX_N3 BG36 2 1 2.2K_0402_5%~D
PCIE_PRX_EXPTX_P3 PERN3 SML0CLK
<35> PCIE_PRX_EXPTX_P3 BJ36 PERP3 SML0CLK C8
EXPRESS Card---> PCIE_PTX_EXPRX_N3 AV34 MEM_SMBDATA RH303 2 1 2.2K_0402_5%~D
<35> PCIE_PTX_EXPRX_N3 PCIE_PTX_EXPRX_P3 PETN3 SML0DATA
<35> PCIE_PTX_EXPRX_P3 AU34 PETP3 SML0DATA G12
PCH_SMB_ALERT# RH304 2 1 10K_0402_5%~D
BF36 PERN4
BE36 PEG_A_CLKRQ# RH80 2 1 10K_0402_5%~D
PERP4 PCH_GPIO74
AY34 PETN4 SML1ALERT# / PCHHOT# / GPIO74 C13
BB34 SML0CLK RH305 2 1 2.2K_0402_5%~D
PETP4 SML1_SMBCLK
SML1CLK / GPIO58 E14 SML1_SMBCLK <30,40>
PCIE_PRX_WPANTX_N5 BG37 SML0DATA RH306 2 1 2.2K_0402_5%~D
PCI-E*
<34> PCIE_PRX_WPANTX_N5 PERN5
1/2 MINI CARD-3 PCIE <34> PCIE_PRX_WPANTX_P5
PCIE_PRX_WPANTX_P5 BH37 PERP5 SML1DATA / GPIO75 M16 SML1_SMBDATA
SML1_SMBDATA <30,40>
PCIE_PTX_WPANRX_N5 AY36
(Mini Card 3)---> <34> PCIE_PTX_WPANRX_N5 PCIE_PTX_WPANRX_P5 BB36
PETN5
<34> PCIE_PTX_WPANRX_P5 PETP5
PCIE_PRX_MMITX_N6 BJ38 CLK_PCI_LOOPBACK PCH_CL_CLK1
<33> PCIE_PRX_MMITX_N6 PERN6
PCIE_PRX_MMITX_P6 BG38
C <33> PCIE_PRX_MMITX_P6 PERP6 C
10P_0402_50V8J~D
10P_0402_50V8J~D
MMI ---> PCIE_PTX_MMIRX_N6 AU36 M7 PCH_CL_CLK1
Controller
<33> PCIE_PTX_MMIRX_N6 PETN6 CL_CLK1 PCH_CL_CLK1 <34>
PCIE_PTX_MMIRX_P6 AV36 1 1
<33> PCIE_PTX_MMIRX_P6 PETP6
@CE17
@
@ CE16
CE17
PCIE_PRX_GLANTX_N7 BG40 T11 PCH_CL_DATA1
Link
<30> PCIE_PRX_GLANTX_N7 PERN7 CL_DATA1 PCH_CL_DATA1 <34>
PCIE_PRX_GLANTX_P7 BJ40
<30> PCIE_PRX_GLANTX_P7 PERP7 2 2
10/100/1G LAN ---> PCIE_PTX_GLANRX_N7 AY40
<30> PCIE_PTX_GLANRX_N7 PCIE_PTX_GLANRX_P7 PETN7 PCH_CL_RST1#
<30> PCIE_PTX_GLANRX_P7 BB40 PETP7 CL_RST1# P10 PCH_CL_RST1# <34>
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8 RF review in 0629
M10 PEG_A_CLKRQ#
@ RH307
@RH307 PEG_A_CLKRQ# / GPIO47
<34> CLK_PCIE_MINI1# 2 1 0_0402_5%~D PCIE_MINI1# Y40
@RH308
@ RH308 CLKOUT_PCIE0N
<34> CLK_PCIE_MINI1 2 1 0_0402_5%~D PCIE_MINI1 Y39
RH81 CLKOUT_PCIE0P
WWAN (Mini Card 1)---> +3.3V_ALW_PCH 2 1 10K_0402_5%~D AB37
MINI1CLK_REQ# CLKOUT_PEG_A_N
<34> MINI1CLK_REQ# J2 AB38
PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P
CLOCKS
CLK_BUF_DMI# RH74 1 2 10K_0402_5%~D
CLK_BUF_DMI RH75 1 2 10K_0402_5%~D
@ RH82 2 1 0_0402_5%~D PCIE_LAN# AB49 AV22 CLK_CPU_DMI#
<30> CLK_PCIE_LAN# @ RH83 CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# <7>
<30> CLK_PCIE_LAN 2 1 0_0402_5%~D PCIE_LAN AB47 AU22 CLK_CPU_DMI
CLK_CPU_DMI <7>
CLKOUT_PCIE1P CLKOUT_DMI_P CLK_BUF_BCLK RH91
10/100/1G LAN ---> 1 2 10K_0402_5%~D
LANCLK_REQ# M1
<30> LANCLK_REQ# PCIECLKRQ1# / GPIO18
AM12
CLKOUT_DP_N
AM13
@ RH85 CLKOUT_DP_P
<33> CLK_PCIE_MMI# 2 1 0_0402_5%~D PCIE_MMI# AA48 CLK_BUF_DOT96# RH76 1 2 10K_0402_5%~D
@ RH86 CLKOUT_PCIE2N
MMI---> <33> CLK_PCIE_MMI 2 1 0_0402_5%~D PCIE_MMI AA47 CLK_BUF_DOT96 RH77 1 2 10K_0402_5%~D
RH87 CLKOUT_PCIE2P
+3.3V_RUN 1 2 10K_0402_5%~D BF18 CLK_BUF_DMI#
MMICLK_REQ# CLKIN_DMI_N CLK_BUF_DMI
<33> MMICLK_REQ# V10 BE18
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P CLK_BUF_CKSSCD# RH78 1 2 10K_0402_5%~D
CLK_BUF_CKSSCD RH79 1 2 10K_0402_5%~D
@ RH88 2 1 0_0402_5%~D PCIE_MINI3# Y37 BJ30 CLK_BUF_BCLK
<34> CLK_PCIE_MINI3# CLKOUT_PCIE3N CLKIN_GND1_N
PP (Mini Card 3)---> @ RH90 2 1 0_0402_5%~D PCIE_MINI3 Y36 BG30 CLK_BUF_BCLK
<34> CLK_PCIE_MINI3 CLKOUT_PCIE3P CLKIN_GND1_P
B +3.3V_ALW_PCH RH152 2 1 10K_0402_5%~D CLK_PCH_14M RH183 1 2 10K_0402_5%~D B
MINI3CLK_REQ# A8
<34> MINI3CLK_REQ# PCIECLKRQ3# / GPIO25
G24 CLK_BUF_DOT96#
CLKIN_DOT_96N CLK_BUF_DOT96
E24
@ RH92 CLKIN_DOT_96P
<35> CLK_PCIE_EXP# 2 1 0_0402_5%~D PCIE_EXP# Y43
CLKOUT_PCIE4N
Express card---> @ RH93 2 1 0_0402_5%~D PCIE_EXP Y45
<35> CLK_PCIE_EXP
+3.3V_ALW_PCH RH94 2 1 10K_0402_5%~D
CLKOUT_PCIE4P
AK7 CLK_BUF_CKSSCD# CLOCK TERMINATION for FCIM and need close to PCH
EXPCLK_REQ# CLKIN_SATA_N CLK_BUF_CKSSCD
<35> EXPCLK_REQ# L12 AK5
PCIECLKRQ4# / GPIO26 CLKIN_SATA_P
@ RH95 2 1 0_0402_5%~D PCIE_MINI2# V45 K45 CLK_PCH_14M

<34> CLK_PCIE_MINI2# CLKOUT_PCIE5N REFCLK14IN
@ RH96 2 1 0_0402_5%~D PCIE_MINI2 V46
<34> CLK_PCIE_MINI2 CLKOUT_PCIE5P
WLAN (Mini Card 2)---> +3.3V_ALW_PCH RH97 2 1 10K_0402_5%~D
MINI2CLK_REQ# L14 H45 CLK_PCI_LOOPBACK
<34> MINI2CLK_REQ# PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LOOPBACK <17>
AB42 V47 XTAL25_IN 2 1

CLKOUT_PEG_B_N XTAL25_IN
1M_0402_5%~D
AB40 V49 XTAL25_OUT @ RH309 0_0402_5%~D
CLKOUT_PEG_B_P XTAL25_OUT
1
RH99
+3.3V_ALW_PCH RH98 1 2 10K_0402_5%~D PEG_B_CLKRQ# E6
PEG_B_CLKRQ# / GPIO56
Y47 XCLK_RCOMP RH100 1 2 90.9_0402_1%~D +1.05V_RUN YH2
XCLK_RCOMP 25MHZ_10PF_Q22FA2380049900~D
V40
2
CLKOUT_PCIE6N
V42 3 1
CLKOUT_PCIE6P OUT IN
+3.3V_ALW_PCH RH110 2 1 10K_0402_5%~D PCIECLKRQ6# T13 4 2
PCIECLKRQ6# / GPIO45 GND GND
10P_0402_50V8J~D
10P_0402_50V8J~D
V38 K43 CLK_48M RH322 2 1 22_0402_5%~D 2 2
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 CLK_SMART_48M <35>
V37
FLEX CLOCKS
CH18
CH19
CLKOUT_PCIE7P SIO_14M RH313
CLKOUTFLEX1 / GPIO65
F47 2 1 22_0402_5%~D CLK_SIO_14M <39>
+3.3V_ALW_PCH RH104 2 1 10K_0402_5%~D PCIECLKRQ7# K12
PCIECLKRQ7# / GPIO46 PCI_TPM_TCM 5@ RH311 1 1
H47 2 1 10_0402_1%~D CLK_PCI_TPM_TCM <32>
@ RH280
@RH280 CLKOUTFLEX2 / GPIO66
<7> CLK_CPU_ITP# 2 1 0_0402_5%~D CLK_BCLK_ITP# AK14
CLKOUT_ITPXDP_N
RH314 2 1 10_0402_1%~D PCLK_80H <34>
@RH281
@ RH281 2 1 0_0402_5%~D CLK_BCLK_ITP AK13 K49 JETWAY_14M @ RH315 2 1 22_0402_5%~D
<7> CLK_CPU_ITP CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 JETWAY_CLK14M <32>
A A
BD82HM77 QPRG C1_BGA989~D

PCIE REQ power rail:
suspend: 0 3 4 5 6 7
core: 1 2 DELL CONFIDENTIAL/PROPRIETARY
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PCH (2/8)
5 4 3 2 1
5 4 3 2 1
RH357 1 2 0_0402_5%~D +RTC_CELL
+3.3V_RUN
2 330K_0402_1%~D
+3.3V_ALW_PCH @ CH99
RH127
1 2
1 2 SUS_STAT#/LPCPD#
5
@ RH318 10K_0402_5%~D 0.1U_0402_25V6K~D
1 2 ME_SUS_PWR_ACK 1
P
<7,14> XDP_DBRESET#
1
RH144 10K_0402_5%~D B SYS_RESET# +3.3V_RUN
O 4
1 2 PCH_PCIE_WAKE# 2 1 ME_RESET# 2 A
G
RH142 10K_0402_5%~D @ RH141 8.2K_0402_5%~D @ UC3 DSWODVREN
1 2 SIO_SLP_LAN# 74AHC1G09GW_TSSOP5~D PCH_CRT_DDC_CLK 2 1
3
D @ RH319 10K_0402_5%~D RH317 2.2K_0402_5%~D D
330K_0402_1%~D
1 2 PCH_RI# DSWODVREN - On Die DSW VR Enable PCH_CRT_DDC_DAT 2 1
RH140 10K_0402_5%~D RH316 2.2K_0402_5%~D
1
@ RH129
Enabled (DEFAULT) PCH_SDVO_CTRLCLK 2 1
PCH_DPWROK 1 2 PCH_RSMRST#_R RH351 2.2K_0402_5%~D
+3.3V_RUN @ RH113 0_0402_5%~D PCH_SDVO_CTRLDATA
ME_SUS_PWR_ACK_R SUSACK#_R
HIGH: RH127 STUFFED, RH352
2 1
2.2K_0402_5%~D
1 2
1 2 CLKRUN# @ RH323 0_0402_5%~D RH129 UNSTUFFED
2
RH137 8.2K_0402_5%~D SYS_PWROK_R 2 1 RESET_OUT#
1 2 ME_RESET# @ RH321 0_0402_5%~D Disabled
@ RH138 8.2K_0402_5%~D RESET_OUT# 1 2 PM_APWROK_R
@ RH119 0_0402_5%~D LOW: RH129 STUFFED,
RH127 UNSTUFFED
UH4C
DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 UH4D

<6> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <6>
DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1 PANEL_BKEN_PCH J47 AP43
<6> DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <6> <24> PANEL_BKEN_PCH L_BKLTEN SDVO_TVCLKINN
DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 ENVDD_PCH M45 AP45
<6> DMI_CTX_PRX_N2 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 <6> <24,39> ENVDD_PCH L_VDD_EN SDVO_TVCLKINP
DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3
<6> DMI_CTX_PRX_N3 DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 <6>
BC12 FDI_CTX_PRX_N4 BIA_PWM_PCH P45 AM42
FDI_RXN4 FDI_CTX_PRX_N4 <6> <24> BIA_PWM_PCH L_BKLTCTL SDVO_STALLN
DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5 AM40
<6> DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <6> SDVO_STALLP
DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6 LDDC_CLK_PCH T40
<6> DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 <6> <24> LDDC_CLK_PCH L_DDC_CLK
DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7 LDDC_DATA_PCH K47 AP39
<6> DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 <6> <24> LDDC_DATA_PCH L_DDC_DATA SDVO_INTN
DMI_CTX_PRX_P3 BJ20 AP40
<6> DMI_CTX_PRX_P3 DMI3RXP SDVO_INTP
BG14 FDI_CTX_PRX_P0 T45
FDI_RXP0 FDI_CTX_PRX_P0 <6> L_CTRL_CLK
DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1 P39
<6> DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 <6> L_CTRL_DATA
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2
<6> DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 <6>
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 1 2 LVD_IBG AF37 P38 PCH_SDVO_CTRLCLK <25>
C <6> DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P3 <6> LVD_IBG SDVO_CTRLCLK C
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 RH344 2.37K_0402_1%~D AF36 M39
<6> DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 <6> LVD_VBG SDVO_CTRLDATA PCH_SDVO_CTRLDATA <25>
BG12 FDI_CTX_PRX_P5 Minimum speacing of 20mils for LVD_IBG
DMI
FDI
FDI_RXP5 FDI_CTX_PRX_P5 <6>
DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6 AE48
<6> DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 <6> LVD_VREFH
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 AE47 AT49
<6> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <6> LVD_VREFL DDPB_AUXN
DMI_CRX_PTX_P2 AY18 AT47
<6> DMI_CRX_PTX_P2 DMI2TXP DDPB_AUXP
DMI_CRX_PTX_P3 AU18 AT40
<6> DMI_CRX_PTX_P3 DMI3TXP DDPB_HPD HDMIB_PCH_HPD <25>
AW16 FDI_INT LCD_ACLK-_PCH AK39
FDI_INT FDI_INT <6> <24> LCD_ACLK-_PCH LVDSA_CLK#
LCD_ACLK+_PCH AK40 AV42
LVDS
+1.05V_RUN <24> LCD_ACLK+_PCH LVDSA_CLK DDPB_0N TMDSB_PCH_N2 <25>
BJ24 AV12 FDI_FSYNC0 AV40
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <6> DDPB_0P TMDSB_PCH_P2 <25>
LCD_A0-_PCH AN48 AV45
<24> LCD_A0-_PCH LVDSA_DATA#0 DDPB_1N TMDSB_PCH_N1 <25>
1 2 DMI_COMP_R BG25 BC10 FDI_FSYNC1 LCD_A1-_PCH AM47 AV46
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <6> <24> LCD_A1-_PCH LVDSA_DATA#1 DDPB_1P TMDSB_PCH_P1 <25>
RH111 49.9_0402_1%~D LCD_A2-_PCH AK47 AU48
<24> LCD_A2-_PCH LVDSA_DATA#2 DDPB_2N
Digital Display Interface

RBIAS_CPY FDI_LSYNC0 TMDSB_PCH_N0 <25>
1 2 BH21
DMI2RBIAS FDI_LSYNC0
AV14 FDI_LSYNC0 <6> AJ48
LVDSA_DATA#3 DDPB_2P
AU47
TMDSB_PCH_P0 <25>
RH112 750_0402_1%~D AV47
FDI_LSYNC1 LCD_A0+_PCH DDPB_3N TMDSB_PCH_CLK# <25>
BB10 FDI_LSYNC1 <6> <24> LCD_A0+_PCH AN47 AV49
FDI_LSYNC1 LCD_A1+_PCH LVDSA_DATA0 DDPB_3P TMDSB_PCH_CLK <25>
<24> LCD_A1+_PCH AM49 LVDSA_DATA1
LCD_A2+_PCH AK49
<24> LCD_A2+_PCH LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46 PCH_DDPC_CTRLCLK <26>
A18 DSWODVREN P42
DSWVRMEN DDPC_CTRLDATA PCH_DDPC_CTRLDATA <26>
LCD_BCLK-_PCH AF40
<24> LCD_BCLK-_PCH LVDSB_CLK#
SUSACK#_R PCH_DPWROK LCD_BCLK+_PCH
System Power Management
<39> SUSACK# 1 2 C12 E22 PCH_DPWROK <39> <24> LCD_BCLK+_PCH AF39 AP47
@ RH114 0_0402_5%~D SUSACK# DPWROK LVDSB_CLK DDPC_AUXN DPC_PCH_DOCK_AUX# <26>
DDPC_AUXP AP49 DPC_PCH_DOCK_AUX <26>
LCD_B0-_PCH AH45 AT38
<24> LCD_B0-_PCH LVDSB_DATA#0 DDPC_HPD DPC_PCH_DOCK_HPD <38>
SYS_RESET# K3 B9 PCH_PCIE_WAKE# LCD_B1-_PCH AH47
SYS_RESET# WAKE# PCH_PCIE_WAKE# <40> <24> LCD_B1-_PCH LVDSB_DATA#1
LCD_B2-_PCH AF49 AY47
<24> LCD_B2-_PCH LVDSB_DATA#2 DDPC_0N DPC_PCH_LANE_N0 <38>
AF45 LVDSB_DATA#3 DDPC_0P AY49 DPC_PCH_LANE_P0 <38>
1 2 SYS_PWROK_R P12 N3 CLKRUN# AY43
<7,39> SYS_PWROK SYS_PWROK CLKRUN# / GPIO32 CLKRUN# <32,39,40> DDPC_1N DPC_PCH_LANE_N1 <38>
@ RH116 0_0402_5%~D LCD_B0+_PCH AH43 AY45
<24> LCD_B0+_PCH LVDSB_DATA0 DDPC_1P DPC_PCH_LANE_P1 <38>
LCD_B1+_PCH AH49 BA47
<24> LCD_B1+_PCH LVDSB_DATA1 DDPC_2N DPC_PCH_LANE_N2 <38>
1 2 PCH_PWROK L22 G8 SUS_STAT#/LPCPD# T56 PAD~D @ LCD_B2+_PCH AF47 BA48
<40> RESET_OUT# PWROK SUS_STAT# / GPIO61 <24> LCD_B2+_PCH LVDSB_DATA2 DDPC_2P DPC_PCH_LANE_P2 <38>
@ RH117 0_0402_5%~D AF43 BB47
B LVDSB_DATA3 DDPC_3N DPC_PCH_LANE_N3 <38> B
DDPC_3P BB49 DPC_PCH_LANE_P3 <38>
PM_APWROK_R L10 N14 SUSCLK T57 PAD~D @
APWROK SUSCLK / GPIO62
T58 PAD~D @ PCH_CRT_BLU N48 M43 PCH_DDPD_CTRLCLK <26>
<23> PCH_CRT_BLU CRT_BLUE DDPD_CTRLCLK
1 2 PM_DRAM_PWRGD_R B13 D10 SIO_SLP_S5# PCH_CRT_GRN P49 M36
<7> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 SIO_SLP_S5# <40,42> <23> PCH_CRT_GRN CRT_GREEN DDPD_CTRLDATA PCH_DDPD_CTRLDATA <26>
@ RH320 0_0402_5%~D PCH_CRT_RED T49
<23> PCH_CRT_RED CRT_RED
T59 PAD~D @
1 2 PCH_RSMRST#_R C21 H4 SIO_SLP_S4# AT45
<14,41> PCH_RSMRST#_Q RSMRST# SLP_S4# SIO_SLP_S4# <39,42,46> DDPD_AUXN DPD_PCH_DOCK_AUX# <26>
@ RH120 0_0402_5%~D PCH_CRT_DDC_CLK T39 AT43
CRT
<23> PCH_CRT_DDC_CLK CRT_DDC_CLK DDPD_AUXP DPD_PCH_DOCK_AUX <26>
PCH_CRT_DDC_DAT M40 BH41
<23> PCH_CRT_DDC_DAT CRT_DDC_DATA DDPD_HPD DPD_PCH_DOCK_HPD <38>
1 2 ME_SUS_PWR_ACK_R K16 F4 SIO_SLP_S3#
<40> ME_SUS_PWR_ACK SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# SIO_SLP_S3# <11,27,35,39,42,47,48,49>
@ RH121 0_0402_5%~D BB43
DDPD_0N DPD_PCH_LANE_N0 <38>
<7,14> SIO_PWRBTN#_R <23> PCH_CRT_HSYNC
RH123 1 2 20_0402_1%~D HSYNC M47 CRT_HSYNC DDPD_0P BB45 DPD_PCH_LANE_P0 <38>
1 2 SIO_PWRBTN#_R E20 G10 SIO_SLP_A# RH124 1 2 20_0402_1%~D VSYNC M49 BF44
<40> SIO_PWRBTN# PWRBTN# SLP_A# SIO_SLP_A# <39,42,48> <23> PCH_CRT_VSYNC CRT_VSYNC DDPD_1N DPD_PCH_LANE_N1 <38>
@ RH122 0_0402_5%~D BE44
T62 PAD~D @ DDPD_1P DPD_PCH_LANE_P1 <38>
DDPD_2N BF42 DPD_PCH_LANE_N2 <38>
AC_PRESENT H20 G16 SIO_SLP_SUS# CRT_IREF T43 BE42
<40> AC_PRESENT ACPRESENT / GPIO31 SLP_SUS# SIO_SLP_SUS# <39> DAC_IREF DDPD_2P DPD_PCH_LANE_P2 <38>
T42 CRT_IRTN DDPD_3N BJ42 DPD_PCH_LANE_N3 <38>
1K_0402_0.5%~D
T63 PAD~D @ BG42
DDPD_3P DPD_PCH_LANE_P3 <38>
1
+3.3V_ALW_PCH 1 2 PCH_BATLOW# E10 AP14 H_PM_SYNC
H_PM_SYNC <7>
BATLOW# / GPIO72 PMSYNCH
RH126
RH139 8.2K_0402_5%~D BD82HM77 QPRG C1_BGA989~D
PCH_CRT_BLU 2 1
PCH_RI# A10 K14 SIO_SLP_LAN# RH131 150_0402_1%~D
RI# SLP_LAN# / GPIO29 SIO_SLP_LAN# <30,39> PCH_CRT_GRN 2 1
2
RH132 150_0402_1%~D
BD82HM77 QPRG C1_BGA989~D PCH_CRT_RED 2 1
RH133 150_0402_1%~D
ENVDD_PCH 2 1
+3.3V_ALW2 RH134 100K_0402_5%~D
CH108
1 2
A 0.1U_0402_25V6K~D A
5
SIO_SLP_A# 1
P
B PM_APWROK_R
O 4
2
<40> PM_APWROK A DELL CONFIDENTIAL/PROPRIETARY
G
UH5
3
TC7SH08FU_SSOP5~D
Title
@ RH118
1 2
0_0402_5%~D
5 4 3 2 1
5 4 3 2 1
UH4E
RSVD1 AY7
RSVD2 AV7
PAD~D T72 @ BG26 AU3
PAD~D T64 @ TP1 RSVD3
BJ26 TP2 RSVD4 BG4
PAD~D T73 @ BH25
PAD~D T65 @ TP3
BJ16 TP4 RSVD5 AT10
PAD~D T74 @ BG16 BC8
AH38
PAD~D T67 @ TP6
AH37 AU2
D +3.3V_RUN PAD~D T75 @ TP7 RSVD7 D
AK43 AT4
AK45 AT3
C18 AT1
PCI_PIRQA# PAD~D T68 @ TP10 RSVD10
1 2 N30 AY3
RH324 8.2K_0402_5%~D PAD~D T69 @ TP11 RSVD11
H3 AT5
PCI_PIRQB# PAD~D T78 @ TP12 RSVD12
1 2 AH12
TP13 RSVD13
AV3
RH325 8.2K_0402_5%~D PAD~D T79 @ AM4 AV1
PCI_PIRQC# PAD~D T80 @ TP14 RSVD14
1 2 AM5
TP15 RSVD15
BB1
RH326 8.2K_0402_5%~D PAD~D T70 @ Y13 BA3
PCI_PIRQD# PAD~D T81 @ TP16 RSVD16
1 2 K24 BB5
RH329 8.2K_0402_5%~D PAD~D T71 @ TP17 RSVD17
L24 BB3
PCI_REQ1# PAD~D T82 @ TP18 RSVD18
1 2 AB46 TP19 RSVD19 BB7
RH327 10K_0402_5%~D PAD~D T83 @ AB45 BE8
LCD_CBL_DET# TP20 RSVD20
1 2 BD4
RSVD
RH330 10K_0402_5%~D RSVD21
RSVD22 BF6
1 2 CAM_MIC_CBL_DET#
RH331 10K_0402_5%~D PAD~D T84 @ B21 AV5
BT_DET# PAD~D T85 @ TP21 RSVD23
1 2 M20 AV10
RH328 10K_0402_5%~D PAD~D T86 @ TP22 RSVD24
AY16 TP23
1 2 PCH_GPIO3 PAD~D T87 @ BG46 AT8
RH332 10K_0402_5%~D TP24 RSVD25
1 2 PCIE_MCARD2_DET# AY5
RH361 10K_0402_5%~D RSVD26
RSVD27 BA2
BE28 USB3Rn1
<36> USB3RN2 BC30 USB3Rn2 RSVD28 AT12
<36> USB3RN3 BE32 USB3Rn3 RSVD29 BF3
<38> USB3RN4 BJ32 USB3Rn4
BC28 USB3Rp1
<36> USB3RP2 BE30 USB3Rp2
BF32
USB30
<36> USB3RP3 USB3Rp3 USBP0-
<38> USB3RP4 BG32 USB3Rp4 USBP0N C24 USBP0- <37>
C
AV26 USB3Tn1 USBP0P A24 USBP0+
USBP0+ <37>
----->Back Right--IO C
BB26 C25 USBP1-
<36> USB3TN2 USB3Tn2 USBP1N USBP1- <36>
<36> USB3TN3 AU28 USB3Tn3 USBP1P B25 USBP1+
USBP1+ <36>
----->Left Side
AY30 C26 USBP2-
<38> USB3TN4 USB3Tn4 USBP2N USBP2- <36>
PCI_GNT3# AU26 USB3TP1 USBP2P A26 USBP2+
USBP2+ <36>
----->Left side E-SATA
AY26 K28 USBP3-
<36> USB3TP2 USB3Tp2 USBP3N USBP3- <38>
<36> USB3TP3 AV28 USB3Tp3 USBP3P H28 USBP3+
USBP3+ <38>
----->MLK DOCK
1K_0402_1%~D
AW30 E28 USBP4-

<38> USB3TP4 USB3Tp4 USBP4N USBP4- <34>
----->WLAN/WIMAX
1
@ RH333
D28 USBP4+
USBP4P USBP5- USBP4+ <34>
C28 USBP5- <34>
USBP5N USBP5+ ----->WWAN/UWB
A28 USBP5+ <34>
USBP5P USBP6-
C29 USBP6- <34>
USBP6N
B29 USBP6+
USBP6+ <34>
----->Flash
2
PCI_PIRQA# USBP6P USBP7-

K40 N28 USBP7- <38>
PIRQA# USBP7N
PCI_PIRQB# K38
PIRQB# USBP7P
M28 USBP7+
USBP7+ <38>
----->DOCK
PCI_PIRQC# H38 L30 USBP8-
PCI
PCI_PIRQD# G38
PIRQC#
PIRQD#
USBP8N
USBP8P
K30 USBP8+ ----->Non used +3.3V_ALW_PCH
G30 USBP9-
USBP9N USBP9- <37>
A16 swap override Strap/Top-Block PCI_REQ1# C46
REQ1# / GPIO50 USBP9P
E30 USBP9+
USBP9+ <37>
----->Right side--IO RPH1
C44 C30 USBP10- USB_OC0#_R 4 5
USB
<34> PCIE_MCARD2_DET# REQ2# / GPIO52 USBP10N USBP10- <35>
Swap Override jumper <41> BT_DET# E40
REQ3# / GPIO54 USBP10P
A30 USBP10+
USBP10+ <35>
----->Express Card USB_OC1#_R 3 6
L32 USBP11- USB_OC3# 2 7
USBP11N USBP11- <41>
BBS_BIT1 D47
GNT1# / GPIO51 USBP11P
K32 USBP11+
USBP11+ <41> ----->Blue Tooth USB_OC4#_R 1 8
USBP12-
Low = A16 swap PCI_GNT3#
E42
GNT2# / GPIO53 USBP12N
G32
USBP12+
USBP12- <24>
----->Camera 10K_1206_8P4R_5%~D
PCI_GNT#3 F46
GNT3# / GPIO55 USBP12P
E32
USBP13- USBP12+ <24>
RPH2
High = Default C32 USBP13- <32>
USBP13N
USBP13P
A32 USBP13+
USBP13+ <32>
----->BIO USB_OC2# 4 5
LCD_CBL_DET# G42 USB_OC5# 3 6
<24> LCD_CBL_DET# PIRQE# / GPIO2
PCH_GPIO3 G40 USB_OC6# 2 7
CAM_MIC_CBL_DET# PIRQF# / GPIO3 USBRBIAS 1 SIO_EXT_SMI#
<24> CAM_MIC_CBL_DET# C42 C33 2 1 8
FFS_PCH_INT PIRQG# / GPIO4 USBRBIAS# RH151 22.6_0402_1%~D
<27> HDD_FALL_INT 1 2 D44
@ RH334 0_0402_5%~D PIRQH# / GPIO5 10K_1206_8P4R_5%~D
Route single-end 50-ohms and max 500-mils length.
B33
B @ RH336 USBRBIAS Minimum spacing to other signals: 15 mils B
<33> PLTRST_MMI# 1 2 0_0402_5%~D PAD~DT104 @ K10
PME#
RH337 1 2 0_0402_5%~D
<7> PLTRST_XDP# PCH_PLTRST# USB_OC0#_R
@ RH338 1 2 0_0402_5%~D C6 A14 @ RH339
@RH339 1 2 0_0402_5%~D
<30> PLTRST_LAN# PLTRST# OC0# / GPIO59 USB_OC1#_R USB_OC0# <36,37>
K20 @RH341
@ RH341 1 2 0_0402_5%~D
OC1# / GPIO40 USB_OC1# <36>
B17 USB_OC2#
PCI_5048 OC2# / GPIO41 USB_OC3# USB_OC2# <14>
RH160 2 1 22_0402_5%~D H49 C16
<39> CLK_PCI_5048 PCI_MEC CLKOUT_PCI0 OC3# / GPIO42 USB_OC4#_R USB_OC3# <14>
RH102 2 1 22_0402_5%~D H43 L16 @RH356
@ RH356 1 2 0_0402_5%~D
<40> CLK_PCI_MEC PCI_DOCK CLKOUT_PCI1 OC4# / GPIO43 USB_OC5# USB_OC4# <37>
RH103 2 1 22_0402_5%~D J48 A16
<38> CLK_PCI_DOCK CLKOUT_PCI2 OC5# / GPIO9 USB_OC6# USB_OC5# <14>
K42 D14 USB_OC6# <14>
RH105 PCI_LOOPBACKOUT CLKOUT_PCI3 OC6# / GPIO10
<15> CLK_PCI_LOOPBACK 2 1 22_0402_5%~D H40
CLKOUT_PCI4 OC7# / GPIO14
C14 SIO_EXT_SMI# <14,40>
USB_OC0#_R <14>
USB_OC1#_R <14>
USB_OC4#_R <14>
+3.3V_RUN
CH102
1 2 Boot BIOS Strap
Reserve for ESD in 6/22 0.1U_0402_25V6K~D
PCH_PLTRST#
SATA_SLPD BBS_BIT1
BBS_BIT1 (BBS_BIT0) Boot BIOS Location
5
0.1U_0402_25V6K~D
1K_0402_1%~D
UH3
1
@ CE10
@ RH342
1 1 0 0 LPC
P
<7,14> PCH_PLTRST# B
4 PCH_PLTRST#_EC <32,34,35,39,40>
O
2
A
G
2 TC7SH08FU_SSOP5~D
0 1 Reserved (NAND)
3
2
A A
1 0 PCI
* 1 1 SPI
Title
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
+3.3V_ALW_PCH
SIO_A20GATE 2 1
RH158 10K_0402_5%~D
4.7K_0402_5%~D
SIO_RCIN# 2 1
2 RH203 10K_0402_5%~D
RH53
SIO_EXT_SCI# 1 2
RH263 10K_0402_5%~D
PCH_GPIO1 1 2
RH164 100K_0402_5%~D
1
D UH4F PCH_GPIO36 1 2 D
<14> SIO_EXT_SCI#_R
SLP_ME_CSW_DEV# @RH171
@ RH171 10K_0402_5%~D
1 2 T7 C40 CONTACTLESS_DET# PCH_GPIO37 1 2
<40> SIO_EXT_SCI# BMBUSY# / GPIO0 TACH4 / GPIO68
1 1K_0402_1%~D
@RH259
@ RH259 0_0402_5%~D @RH173
@ RH173 1K_0402_1%~D
@ RH353
PCH_GPIO1 A42 B41 PCH_GPIO69 PCH_GPIO16 2 1

TACH1 / GPIO1 TACH5 / GPIO69 RH272 10K_0402_5%~D
IO_LOOP# H36 C41 PCIE_MCARD3_DET# TEMP_ALERT# 1 2
TACH2 / GPIO6 TACH6 / GPIO70 PCIE_MCARD3_DET# <34>
RH266 10K_0402_5%~D
2
PCH_GPIO7 E38 A40 USB_MCARD2_DET# MEDIA_DET# 1 2

TACH3 / GPIO7 TACH7 / GPIO71 USB_MCARD2_DET# <34>
RH181 10K_0402_5%~D
SIO_EXT_WAKE# C10 PCH_GPIO7 1 2
<39> SIO_EXT_WAKE# GPIO8 RH178 10K_0402_5%~D
PM_LANPHY_ENABLE C4 PCH_GPIO17 2 1
Note: PCH has internal pull up 20k ohm on vPro only--- LAN_PHY_PWR_CTRL / GPIO12 RH269 8.2K_0402_5%~D
E3_PAID_TS_DET# (GPIO27) <14> PCH_GPIO15
PCH_GPIO15 G2 GPIO15 A20GATE P4 SIO_A20GATE
SIO_A20GATE <40>
IO_LOOP# 2 1
RH163 10K_0402_5%~D
AU16 PCH_GPIO34 1 2
PCH_GPIO16 PECI RH182 10K_0402_5%~D
SLP_ME_CSW_DEV# PLL ON DIE VR ENABLE <14> PCH_GPIO16 U2 SATA4GP / GPIO16
P5 SIO_RCIN# CONTACTLESS_DET# 2 1
RCIN# SIO_RCIN# <40>
RH256 10K_0402_5%~D
ENABLED HIGH (DEFAULT) PCH_GPIO17 H_CPUPWRGD +1.05V_RUN_VTT
D40 AY11
GPIO
TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD <7>
CPU/MISC
MEDIA_DET# T5 AY10 PCH_THRMTRIP#_R 2 1 PCH_GPIO36 1 2
DISABLED LOW <43> MEDIA_DET# SCLOCK / GPIO22 THRMTRIP#
0.1U_0402_25V6K~D
RH262 56_0402_5%~D RH174 10K_0402_5%~D
PCIE_MCARD1_DET# E8 T14 INIT3_3V# PAD~D T106@ 1 PCH_GPIO37 1 2
<34> PCIE_MCARD1_DET# GPIO24 INIT3_3V#
CH97
RH172 10K_0402_5%~D
PCH_GPIO27 E16 AY1 DF_TVS PCH_GPIO17 1 2
GPIO27 DF_TVS @RH273
@ RH273 1K_0402_1%~D
+3.3V_ALW_PCH SLP_ME_CSW_DEV# P8 2 PCH_GPIO16 1 2
<14,39> SLP_ME_CSW_DEV# GPIO28
AH8 @RH265
@ RH265 10K_0402_5%~D
SIO_EXT_WAKE# PCH_GPIO34 TS_VSS1 PCH_GPIO69
2 1 K1 1 2
RH177 10K_0402_5%~D STP_PCI# / GPIO34 RH260 1.5K_0402_1%~D
TS_VSS2 AK11
1 2 PCH_GPIO15 USB_MCARD1_DET# K4
<14,34> USB_MCARD1_DET# GPIO35
RH354 1K_0402_1%~D AH10
TS_VSS3
2 1 PM_LANPHY_ENABLE <14> PCH_GPIO36
PCH_GPIO36 V8
C
RH179 10K_0402_5%~D SATA2GP / GPIO36 C
TS_VSS4 AK10
2 1 PCH_GPIO27 PCH_GPIO37 M5
<14> PCH_GPIO37 SATA3GP / GPIO37
RH180 10K_0402_5%~D
2 1 KB_DET# TPM_ID0 N2 P37 NC_1 PAD~D T108 @
RH170 10K_0402_5%~D SLOAD / GPIO38 NC_1
TPM_ID1 M3 SDATAOUT0 / GPIO39
FFS_INT2 V13 BG2 VSS_NCTF_15
<27> FFS_INT2 SDATAOUT1 / GPIO48 VSS_NCTF_15
TEMP_ALERT# V3 BG48 VSS_NCTF_16
<14,39> TEMP_ALERT# SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
KB_DET# D6 BH3 VSS_NCTF_17
<41> KB_DET# GPIO57 VSS_NCTF_17
BH47 VSS_NCTF_18
VSS_NCTF_18
VSS_NCTF_1 A4 BJ4 VSS_NCTF_19
VSS_NCTF_1 VSS_NCTF_19
NCTF
VSS_NCTF_5 VSS_NCTF_23 Layout note:
Layout note: A6
BJ6
Trace wide 10mil & length 30mil
Trace wide 10mil & length 30mil B3
C2 All NCTF pins should have thick
All NCTF pins should have thick VSS_NCTF_8 B47
C48 VSS_NCTF_26
traces at 45°from the pad.
traces at 45°from the pad. VSS_NCTF_9 BD1
D1 VSS_NCTF_27
VSS_NCTF_10 BD49 D49 VSS_NCTF_28

B B
VSS_NCTF_11 BE1 E1 VSS_NCTF_29
VSS_NCTF_12 BE49 E49 VSS_NCTF_30
VSS_NCTF_13 BF1 F1 VSS_NCTF_31
VSS_NCTF_14 BF49 F49 VSS_NCTF_32 DMI & FDI Termination Voltage

Set to Vss when LOW
DF_TVS
Set to Vcc when HIGH
+VCCDFTERM
1 2.2K_0402_5%~D
+3.3V_RUN +3.3V_RUN
RH149
RH149 need to close to CPU
10K_0402_5%~D
20K_0402_5%~D
2
2
1
1@ RH267
3@ RH268
DF_TVS 2 1 DF_TVS_R 2 1 H_SNB_IVB# <7>

1K_0402_1%~D RH358 0_0402_5%~D @ RH150
TPM_ID0 TPM_ID1
1
TPM_ID0 TPM_ID1
China TPM 0 0
PLACE RH150 CLOSE TO THE BRANCHING POINT
No TPM, No China TPM 0 1 ( TO CPU and NVRAM CONNECTOR)
10K_0402_5%~D
2@ RH270
2.2K_0402_5%~D
4@ RH271
TBD
2
A TPM 1 1 A
1
Title
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
LH1
+VCCADAC 2 1
0.01U_0402_16V7K~D
0.1U_0402_10V7K~D
22U_0603_6.3V6M~D
1UH_GLFR1608T1R0M-LR_20%~D
D UH4G POWER 1 1 1 PCH Power Rail Table D
+1.05V_RUN
CH34
CH35
CH36
S0 Iccmax
AA23
VCCCORE[1] VCCADAC
U48 Voltage Rail Voltage Current (A)
AC23 2 2 2
VCCCORE[2]
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
AD21
VCCCORE[3]
CRT
1 1 1 1 AD23
VCCCORE[4] VSSADAC
U47 V_PROC_IO 1.05 0.001
AF21
VCCCORE[5]
CH30
CH32
CH33
CH31
VCC CORE
AF23
VCCCORE[6]
AG21
VCCCORE[7]
V5REF 5 0.001
2 2 2 2 AG23
VCCCORE[8]
AG24 VCCCORE[9] VCCALVDS AK36 +3.3V_RUN
AG26 VCCCORE[10]
V5REF_Sus 5 0.001
AG27 VCCCORE[11] VSSALVDS AK37
AG29 +1.8V_RUN
VCCCORE[12]
AJ23 VCCCORE[13]
LH8 Vcc3_3 3.3 0.288
AJ26 AM37 +1.8V_RUN_LVDS 2 1
LVDS
VCCCORE[14] VCCTX_LVDS[1]
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
22U_0805_6.3V6M~D
AJ27 100NH_HK1608R10J-T_5%_0603~D
VCCCORE[15]
AJ29 VCCCORE[16] VCCTX_LVDS[2] AM38 VccADAC3 3.3 0.063
AJ31 VCCCORE[17] 1 1 1 0.1uH inductor, 200mA
CH103
CH104
CH105
VCCTX_LVDS[3] AP36 CPN : SHI0110BJ0L VccADPLLA 1.05 0.08
VCCTX_LVDS[4] AP37
+1.05V_RUN 2 2 2
+1.05V_RUN AN19 VCCIO[28]
VccADPLLB 1.05 0.08
@RH247
@ RH247 +3.3V_RUN
1 2 +VCCAPLLEXP BJ22 VCCAPLLEXP
1UH_LB2012T1R0M_20%~D VccCore 1.05 1.7
10U_0603_6.3V6M~D
1 VCC3_3[6] V33
@
0.1U_0402_10V7K~D
AN16
HVCMOS
VCCIO[15]
CH40
1 VccDMI 1.05 0.047
CH43
AN17 VCCIO[16]
C 2 V34 C
VCC3_3[7]
VccIO 1.05 3.711
2
AN21 VCCIO[17]
AN26 VCCIO[18]
VccASW 1.05 0.903
+1.05V_RUN
AN27 VCCIO[19] VCCVRM[3] AT16 +1.05V_+1.5V_1.8V_RUN
VccSPI 3.3 0.01
AP21
VCCIO[20]
+1.05V_RUN_VCCCLKDMI +1.05V_RUN
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1 1 1 1 1 AP23
VCCIO[21] VCCDMI[1]
AT20 +1.05V_RUN_VTT VccDSW3_3 3.3 0.001
CH44
CH45
CH46
CH47
CH48
AP24 CH49 1 2 1U_0402_6.3V6K~D 2 1
DMI
VCCIO[22]
1U_0402_6.3V6K~D
10U_0603_6.3V6M~D
RH205 0_0603_5%~D VCCDFTERM 1.8 0.002
VCCIO
2 2 2 2 2 AP26 AB36 +1.05V_RUN_VCCCLKDMI
VCCIO[23] VCCCLKDMI 1 1
@ CH106
CH50
AT24
VCCIO[24]
VccRTC 3.3 6uA
2 2
AN33
VCCIO[25]
VccSus3_3 3.3 0.126
+3.3V_RUN AN34 AG16
VCCIO[26] VCCDFTERM[1] +VCCDFTERM VccSusHDA 3.3 0.01
BH29 AG17 2 1 +3.3V_RUN
VCC3_3[3] VCCDFTERM[2] @ RH276 0_0805_5%~D VccVRM 1.8 / 1.5 0.167
DFT / SPI
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
AJ16 1 @ PJP66
VCCDFTERM[3]
CH51
1 2 +1.8V_RUN VccClkDMI 1.05 0.07
CH52
+1.05V_+1.5V_1.8V_RUN AP16
2 VCCVRM[2] PAD-OPEN1x1m
AJ17
VCCDFTERM[4] 2 VccSSC 1.05 0.095
B +VCCAPLL_FDI B
BG6
VccAFDIPLL
VccDIFFCLKN 1.05 0.055
+1.05V_RUN AP17
VCCIO[27] +VCCSPI
V1 2 1 +3.3V_M
VCCSPI
FDI
@RH202
@ RH202 0_0603_5%~D VccALVDS 3.3 0.001
1U_0402_6.3V6K~D
+1.05V_RUN_VTT AU20 2 1 +3.3V_RUN
VCCDMI[2] @RH204
@ RH204 0_0603_5%~D
1
CH54
+1.05V_RUN VccTX_LVDS 1.8 0.04
2
1 2 +VCCAPLL_FDI
@RH195
@ RH195 0.022_0805_1%
HM76(w/o vpro): depop RH202 and pop RH204

QM77(w/ vpro) : pop RH202 and depop RH204
+1.5V_RUN +1.05V_+1.5V_1.8V_RUN
2 1
@RH197
@ RH197 0_0603_5%~D
A A
Title
5 4 3 2 1
5 4 3 2 1
+PWR_SRC_S
+5V_ALW +5V_ALW_PCH
100K_0402_5%~D
QH4
1
+1.05V_RUN
RH279
1 3
0.1U_0402_10V7K~D
1 2 +VCCACLK
+3.3V_ALW_PCH +1.05V_RUN
20K_0402_5%~D
@RH200
@ RH200 0.022_0805_1%
D
POWER D
1
UH4J 1
G
2
+3.3V_ALW2
CH98
RH278
1 2
0.1U_0402_10V7K~D
RH201 0_0402_5%~D AD49 N26 5V_ALW_PCH_ENABLE
VCCACLK VCCIO[29]
1U_0402_6.3V6K~D
3300P_0402_50V7K~D
1 2
1
@ RH253 0_0402_5%~D D 2
1 P26 1 1
2
VCCIO[30]
CH55
CH56
+VCCDSW3_3 T16 2
VCCDSW3_3 <42> ALW_ON_3.3V#
0.1U_0402_10V7K~D
QH6
CH107
P28 G
VCCIO[31]
S
3
2 +PCH_VCCDSW 2 2
V12 T27
DCPSUSBYP VCCIO[32]
@CH57
@
1
+3.3V_ALW_PCH
CH57
T29
+3.3V_RUN_VCC_CLKF33 VCCIO[33]
T38 VCC3_3[5]
+1.05V_RUN
2 +3.3V_ALW_PCH
0.1U_0402_10V7K~D
@LH3
@ LH3 T23
+VCCAPLL_CPY_PCH VCCSUS3_3[7]
1 2 BH23 VCCAPLLDMI2
10U_0603_6.3V6M~D
10UH_LBR2012T100M_20%~D T24 1
VCCSUS3_3[8]
CH59
0.1U_0402_10V7K~D
+1.05V_RUN AL29 VCCIO[14]
1 VCCSUS3_3[9] V23 1
USB
2
CH58
CH60
+VCCSUS1 AL24 V24
+3.3V_RUN DCPSUS[3] VCCSUS3_3[10]
1U_0402_6.3V6K~D
2 2 +3.3V_ALW_PCH
1 VCCSUS3_3[6] P24
+5V_ALW_PCH
@CH61
@
1 2 +3.3V_RUN_VCC_CLKF33
CH61
RH215 0.022_0805_1% AA19 VCCASW[1]
10U_0603_6.3V6M~D
10_0402_1%~D
VCCIO[34] T26 +1.05V_RUN
1
2
1U_0402_6.3V6K~D
1 1 AA21 VCCASW[2] +3.3V_ALW_PCH

@CH73
@
RH208
DH2
Note: If EMI concern, pop with
CH73
CH74
AA24 M26 +PCH_V5REF_SUS RB751S40T1_SOD523-2~D

SHI00008S0L, 10UH +-20% +1.05V_M VCCASW[3] V5REF_SUS
2 2
AA26
2
VCCASW[4]
Clock and Miscellaneous
0.1U_0402_10V7K~D
AN23 +VCCA_USBSUS
DCPSUS[4] +PCH_V5REF_SUS
AA27 VCCASW[5] 1
VCCSUS3_3[1] AN24
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
CH66
0.1U_0402_10V7K~D
C
AA29 VCCASW[6] 1 C
1 CH67 1 1 1 1 2
CH68
CH69
CH64
CH65
CH63
AA31 VCCASW[7]
AC26 P34 +PCH_V5REF_RUN 2
2 2 2 2 2 VCCASW[8] V5REF
AC27 VCCASW[9]
N20 +3.3V_ALW_PCH
VCCSUS3_3[2]
AC29
PCI/GPIO/LPC
+1.05V_RUN VCCASW[10]
1U_0603_10V7K~D
N22
LH6 VCCSUS3_3[3] +3.3V_RUN
AC31 1
+1.05V_RUN_VCCA_A_DPL VCCASW[11] +3.3V_RUN +5V_RUN
1 2 P20
VCCSUS3_3[4]
CH70
0.1U_0402_10V7K~D
10UH_LBR2012T100M_20%~D AD29
LH7 VCCASW[12]
P22
VCCSUS3_3[5] 2
10_0402_1%~D
1 2 +1.05V_RUN_VCCA_B_DPL AD31 1
VCCASW[13]
1
CH72
10UH_LBR2012T100M_20%~D
220U_B2_2.5VM_R35M~D
220U_B2_2.5VM_R35M~D
RH213
W21 AA16
VCCASW[14] VCC3_3[1] +3.3V_RUN
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1 1 DH3
W23 W16 2
1 1 VCCASW[15] VCC3_3[8] RB751S40T1_SOD523-2~D
CH94
CH92
CH95
CH93
+ +
2
W24 T34
VCCASW[16] VCC3_3[4]
0.1U_0402_10V7K~D
2 2 2 2 W26 +PCH_V5REF_RUN
VCCASW[17]
+3.3V_RUN 1
CH75
1U_0603_10V7K~D
W29
VCCASW[18]
1
0.1U_0402_10V7K~D
CH71
W31 AJ2
VCCASW[19] VCC3_3[2] 2
1
W33
VCCASW[20] 2
CH76
AF13
CH78 VCCIO[5]
+VCCRTCEXT 2
2 1 N16
DCPRTC
AH13 +1.05V_RUN
0.1U_0402_10V7K~D VCCIO[12]
+1.05V_+1.5V_1.8V_RUN Y49 AH14 +VCCA_USBSUS
VCCVRM[4] VCCIO[13]
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
B B
1 1
+1.05V_RUN
CH77
@ CH62
AF14
+1.05V_RUN_VCCA_A_DPL VCCIO[6]
BD47
VCCADPLLA +VCCSATAPLL
AK1
SATA
VCCAPLLSATA 2 2
1U_0402_6.3V6K~D
1 +1.05V_RUN_VCCA_B_DPL BF47
VCCADPLLB
+1.05V_RUN
CH79
AF11 +1.05V_+1.5V_1.8V_RUN
VCCVRM[1]
AF17
2 VCCIO[7]
AF33
CH81 VCCDIFFCLKN[1]
AF34 AC16
VCCDIFFCLKN[2] VCCIO[2] +1.05V_RUN
1U_0402_6.3V6K~D
1 2 AG34
VCCDIFFCLKN[3]
AC17 1
VCCIO[3]
CH82
1U_0402_6.3V6K~D @LH5
@ LH5
AG33 AD17 +VCCSATAPLL 1 2
VCCSSC VCCIO[4]
1U_0402_6.3V6K~D
10U_0603_6.3V6M~D
10UH_LBR2012T100M_20%~D
+1.05V_M +VCCSST 2
1 1
+1.05V_M
0.1U_0402_10V7K~D
@ CH80
V16
DCPSST
CH96
1U_0402_6.3V6K~D
1 2 +1.05V_M_VCCSUS 1 +1.05V_M_VCCSUS
CH84
@RH248
@ RH248 0.022_0805_1%
2 T17 T21 2
1 DCPSUS[1] VCCASW[22]
@CH83
@
V19
2 DCPSUS[2]
CH83
MISC
+1.05V_RUN_VTT V21
2 VCCASW[23]
BJ8
CPU
V_PROC_IO +3.3V_ALW_PCH
T19
VCCASW[21]
4.7U_0603_6.3V6K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
+RTC_CELL
1 1 1
CH85
CH86
CH87
A22 P32
VCCRTC VCCSUSHDA
0.1U_0402_10V7K~D
RTC
HDA
2 2 2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1U_0402_6.3V6K~D
1
1 1 1 BD82HM77 QPRG C1_BGA989~D
CH88
CH89
CH90
CH91
A A
2
2 2 2
Title
5 4 3 2 1
5 4 3 2 1
UH4I
AY4 VSS[159] VSS[259] H46

AY42 VSS[160] VSS[260] K18
AY46 VSS[161] VSS[261] K26
AY8 VSS[162] VSS[262] K39
B11 VSS[163] VSS[263] K46
B15 VSS[164] VSS[264] K7
UH4H B19 L18
VSS[165] VSS[265]
H5 B23 L2
VSS[0] VSS[166] VSS[266]
B27 L20
D VSS[167] VSS[267] D
AA17 AK38 B31 L26
VSS[1] VSS[80] VSS[168] VSS[268]
AA2 AK4 B35 L28
VSS[2] VSS[81] VSS[169] VSS[269]
AA3 AK42 B39 L36
VSS[3] VSS[82] VSS[170] VSS[270]
AA33 AK46 B7 L48
VSS[4] VSS[83] VSS[171] VSS[271]
AA34 AK8 F45 M12
VSS[5] VSS[84] VSS[172] VSS[272]
AB11 AL16 BB12 P16
VSS[6] VSS[85] VSS[173] VSS[273]
AB14 AL17 BB16 M18
VSS[7] VSS[86] VSS[174] VSS[274]
AB39 AL19 BB20 M22
VSS[8] VSS[87] VSS[175] VSS[275]
AB4 AL2 BB22 M24
VSS[9] VSS[88] VSS[176] VSS[276]
AB43 AL21 BB24 M30
VSS[10] VSS[89] VSS[177] VSS[277]
AB5 AL23 BB28 M32
VSS[11] VSS[90] VSS[178] VSS[278]
AB7 VSS[12] VSS[91] AL26 BB30 VSS[179] VSS[279] M34
AC19 VSS[13] VSS[92] AL27 BB38 VSS[180] VSS[280] M38
AC24 VSS[16] VSS[95] AL34 BC14 VSS[183] VSS[283] M46
AC33 VSS[17] VSS[96] AL48 BC18 VSS[184] VSS[284] M8
AC34 VSS[18] VSS[97] AM11 BC2 VSS[185] VSS[285] N18
AC48 VSS[19] VSS[98] AM14 BC22 VSS[186] VSS[286] P30
AD10 VSS[20] VSS[99] AM36 BC26 VSS[187] VSS[287] N47
AD11 VSS[21] VSS[100] AM39 BC32 VSS[188] VSS[288] P11
AD13 VSS[23] VSS[102] AM45 BC36 VSS[190] VSS[290] T33
AD26 VSS[26] VSS[105] AN2 BC48 VSS[193] VSS[293] P47
AD27 VSS[27] VSS[106] AN29 BD46 VSS[194] VSS[294] P7
AD33 VSS[28] VSS[107] AN3 BD5 VSS[195] VSS[295] R2
AD34 VSS[29] VSS[108] AN31 BE22 VSS[196] VSS[296] R48
AD36 VSS[30] VSS[109] AP12 BE26 VSS[197] VSS[297] T12
AD37 VSS[31] VSS[110] AP19 BE40 VSS[198] VSS[298] T31
AD38 VSS[32] VSS[111] AP28 BF10 VSS[199] VSS[299] T37
C C
AD4 VSS[34] VSS[113] AP32 BF16 VSS[201] VSS[301] W34
AD45 VSS[38] VSS[117] AP46 BF26 VSS[205] VSS[305] V11
AD46 VSS[39] VSS[118] AP8 BF28 VSS[206] VSS[306] V17
AD8 AR2 BD3 V26
VSS[40] VSS[119] VSS[207] VSS[307]
AE2 AR48 BF30 V27
VSS[41] VSS[120] VSS[208] VSS[308]
AE3 AT11 BF38 V29
VSS[42] VSS[121] VSS[209] VSS[309]
AF10 AT13 BF40 V31
VSS[43] VSS[122] VSS[210] VSS[310]
AF12 AT18 BF8 V36
VSS[44] VSS[123] VSS[211] VSS[311]
AD14 AT22 BG17 V39
VSS[45] VSS[124] VSS[212] VSS[312]
AD16 AT26 BG21 V43
VSS[46] VSS[125] VSS[213] VSS[313]
AF16 AT28 BG33 V7
VSS[47] VSS[126] VSS[214] VSS[314]
AF19 AT30 BG44 W17
VSS[48] VSS[127] VSS[215] VSS[315]
AF24 AT32 BG8 W19
VSS[49] VSS[128] VSS[216] VSS[316]
AF26 AT34 BH11 W2
VSS[50] VSS[129] VSS[217] VSS[317]
AF27 AT39 BH15 W27
VSS[51] VSS[130] VSS[218] VSS[318]
AF29 AT42 BH17 W48
VSS[52] VSS[131] VSS[219] VSS[319]
AF31 AT46 BH19 Y12
VSS[53] VSS[132] VSS[220] VSS[320]
AF38 AT7 H10 Y38
VSS[54] VSS[133] VSS[221] VSS[321]
AF4 AU24 BH27 Y4
VSS[55] VSS[134] VSS[222] VSS[322]
AF42 AU30 BH31 Y42
VSS[56] VSS[135] VSS[223] VSS[323]
AF46 AV16 BH33 Y46
VSS[57] VSS[136] VSS[224] VSS[324]
AF5 AV20 BH35 Y8
VSS[58] VSS[137] VSS[225] VSS[325]
AF7 AV24 BH39 BG29
VSS[59] VSS[138] VSS[226] VSS[328]
AF8 AV30 BH43 N24
VSS[60] VSS[139] VSS[227] VSS[329]
AG19 AV38 BH7 AJ3
VSS[61] VSS[140] VSS[228] VSS[330]
AG2 AV4 D3 AD47
VSS[62] VSS[141] VSS[229] VSS[331]
AG31 AV43 D12 B43
VSS[63] VSS[142] VSS[230] VSS[333]
AG48 AV8 D16 BE10
B VSS[64] VSS[143] VSS[231] VSS[334] B
AH11 AW14 D18 BG41
VSS[65] VSS[144] VSS[232] VSS[335]
AH3 AW18 D22 G14
VSS[66] VSS[145] VSS[233] VSS[337]
AH36 AW2 D24 H16
VSS[67] VSS[146] VSS[234] VSS[338]
AH39 AW22 D26 T36
VSS[68] VSS[147] VSS[235] VSS[340]
AH40 AW26 D30 BG22
VSS[69] VSS[148] VSS[236] VSS[342]
AH42 AW28 D32 BG24
VSS[70] VSS[149] VSS[237] VSS[343]
AH46 AW32 D34 C22
VSS[71] VSS[150] VSS[238] VSS[344]
AH7 AW34 D38 AP13
VSS[72] VSS[151] VSS[239] VSS[345]
AJ19 AW36 D42 M14
VSS[73] VSS[152] VSS[240] VSS[346]
AJ21 AW40 D8 AP3
VSS[74] VSS[153] VSS[241] VSS[347]
AJ24 AW48 E18 AP1
VSS[75] VSS[154] VSS[242] VSS[348]
AJ33 AV11 E26 BE16
VSS[76] VSS[155] VSS[243] VSS[349]
AJ34 AY12 G18 BC16
VSS[77] VSS[156] VSS[244] VSS[350]
AK12 AY22 G20 BG28
VSS[78] VSS[157] VSS[245] VSS[351]
AK3 AY28 G26 BJ28
VSS[79] VSS[158] VSS[246] VSS[352]
G28
BD82HM77 QPRG C1_BGA989~D VSS[247]
G36
VSS[248]
G48
VSS[249]
H12
VSS[250]
H18
VSS[251]
H22
VSS[252]
H24
VSS[253]
H26
VSS[254]
H30
VSS[255]
H32
VSS[256]
H34
VSS[257]
F3
VSS[258]

A A
Title
5 4 3 2 1
5 4 3 2 1
+FAN1_VOUT JFAN1
FAN1_DET# 1 1
2 2
RB751S40T1_SOD523-2~D
FAN1_TACH_FB 3 3
4 4
22U_0805_6.3V6M~D
1
1 5
GND
C219
6
GND
D2
D D
ACES_50279-0040N-001 HM76(w/o vpro): depop R385 and pop R386
2 CONN@
QM77(w/ vpro) : pop R385 and depop R386
2
Link CIS
+3.3V_ALW
BC_INT#_EMC4022 2 1
@R386
@ R386 10K_0402_5%~D
FAN1_DET# 2 1
+5V_RUN @R408
@ R408 10K_0402_5%~D
+3.3V_M
(1) DP3/DN3 for SODIMM on Q14, place Q14 close to SODIMM and C272 close to Q14
(2) DP5/DN5 for Skin on Q13, place Q13 close to Vcore VR choke. +3.3V_RUN
10U_0805_10V6K~D
0.1U_0402_25V6K~D
REM_DIODE2_P_4022 1 1 BC_INT#_EMC4022 2 1
100P_0402_50V8J~D
100P_0402_50V8J~D
C276
C275
R385 10K_0402_5%~D
10U_0603_6.3V6M~D
0.1U_0402_25V6K~D
1 1 Q13 FAN1_TACH_FB 2 1
1
3
@ C272
@ C277
E
C MMBT3904WT1G_SC70-3~D U9 R426 10K_0402_5%~D
B 2 2 FAN1_DET#
2 2 1 1 2 1
C305
C738
B R402 10K_0402_5%~D
2 E 2 C
2 VDD_PWRGD 2 1
3
VDD_H R389 10K_0402_5%~D

3 VDD_H
Q14 2 2 THERMATRIP2#
6 VDD_L THERMTRIP2# 17
MMBT3904WT1G_SC70-3~D REM_DIODE2_N_4022 VDD_PWRGD 13 +RTC_CELL
VDD_PWRGD
N/C 18
THERM_STP# 1 2
Place under CPU C270 1 2 2200P_0402_50V7K~D REM_DIODE1_N_4022 23 DN1/THERM
@R390
@ R390 47K_0402_1%~D
REM_DIODE1_P_4022 24 19 THERM_STP#
DP1/VREF_T SYS_SHDN# THERM_STP# <45>
Place C266 close to the Q12 as possible
REM_DIODE1_P_4022 C279 2 1 2200P_0402_50V7K~D REM_DIODE2_N_4022 26 20 POWER_SW# +3.3V_RUN
DN2/DP4 POWER_SW#
100P_0402_50V8J~D
C REM_DIODE2_P_4022 C
27 DP2/DN4
1
@ C266
2 C
2 30 21 ACAV_IN <40,52,53> FAN1_TACH_FB 1 2
B N/C ACAVAIL_CLR @R430
@ R430 10K_0402_5%~D
29 N/C ATF_INT#/BC_IRQ# 9 BC_INT#_EMC4022 <40>
E
3
1 Q12
MMBT3904WT1G_SC70-3~D REM_DIODE1_N_4022 <52> MAX8731_IINP 4.7K_0402_5%~D 2 1 R387 VCP2 31
10K_0402_5%~D 2 VCP_4021 VCP
1 R429 25
VIN
5 +FAN1_VOUT
VSET_4021 FAN_OUT
28 4
VSET FAN_OUT
8 BC_CLK_EMC4022 <40>
+3.3V_M FAN1_TACH_FB SMCLK/BC_CLK
10 7 BC_DAT_EMC4022 <40>
@ R407 2 TACH/GPIO1 SMDATA/BC_DATA
+3.3V_M 1 10K_0402_5%~D
R404 2 1 10K_0402_5%~D 11
TEST3
1 8.2K_0402_5%~D
1 2 FAN1_DET#_R 15
<39> FAN1_DET# GPIO3/PWM/THERMTRIP_SIO
R395
@ R806 0_0402_5%~D
2
<40> PCH_PWRGD# 1 2 3V_PWROK# 12

R391 1K_0402_1%~D 3V_PWROK# +3.3V_M
THERMATRIP2#
+1.05V_RUN_VTT 1 +VCC_4022 2 R388 1
VDD
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1U_0402_6.3V6K~D
1 32 +ADDR_XEN 1 2 +VCC_4022 22_0402_5%~D
ADDR_MODE/XEN
1
C278
C 4.7K_0402_5%~D R393
1 R399 2 2 +RTC_CELL 14
TEST1 1 1
C1179
2.2K_0402_5%~D B 22
2 TEST2
C273
E 16 33
3
RTC_PWR3V VSS
10K_0402_5%~D
B Q16 B
1
2 2
1U_0402_6.3V6K~D
PMST3904_SOT323-3~D
R403
1 EMC4021-1-EZK-TR_QFN32_5X5~D
<7> H_THERMTRIP#
C274
2
2
+RTC_CELL
VSET_4021 C281
0.1U_0402_25V6K~D
1 2
1 1.24K_0402_1%~D
1 0.1U_0402_25V6K~D
5
R406
C282
P
B DOCK_PWR_SW# <40>
POWER_SW# 4
2 O
2 POWER_SW_IN# <40>
2
G
U10
3
TC7SH08FU_SSOP5~D
Rest=1.24k, Tp=92degree
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT FAN & Thermal Sensor
5 4 3 2 1
2 1
B
SW for MB/DOCK B
+5V_RUN
U18
PCH_CRT_RED 1 16 +3.3V_RUN
<16> PCH_CRT_RED PCH_CRT_GRN R 5V VDD
<16> PCH_CRT_GRN 2 G
PCH_CRT_BLU 5 4
<16> PCH_CRT_BLU PCH_CRT_HSYNC B VDD
<16> PCH_CRT_HSYNC 6 H_SOURCE VDD 23
PCH_CRT_VSYNC 7 32
<16> PCH_CRT_VSYNC PCH_CRT_DDC_DAT V_HOURCE VDD
<16> PCH_CRT_DDC_DAT 9 SDA_SOURCE
PCH_CRT_DDC_CLK 10 27 RED_CRT
<16> PCH_CRT_DDC_CLK SCL_SOURCE R1 GREEN_CRT RED_CRT <37>
G1 25 GREEN_CRT <37>
22 BLUE_CRT
CRT_SWITCH B1 HSYNC_BUF BLUE_CRT <37>
<39> CRT_SWITCH 30 SEL H1_OUT 20
VSYNC_BUF HSYNC_BUF <37>
V1_OUT 18
DAT_DDC2_CRT VSYNC_BUF <37>
SDA1 12
CLK_DDC2_CRT DAT_DDC2_CRT <37>
+3.3V_RUN 29 TEST SCL1 14 CLK_DDC2_CRT <37>
1 2 8 26 RED_DOCK
+3.3V_RUN Reserved R2 RED_DOCK <38>
R556 4.7K_0402_5%~D 24 GREEN_DOCK
G2 BLUE_DOCK GREEN_DOCK <38>
3 21
GND B2 HSYNC_DOCK BLUE_DOCK <38>
11 19
GND H2_OUT VSYNC_DOCK HSYNC_DOCK <38>
28 17
GND V2_OUT DAT_DDC2_DOCK VSYNC_DOCK <38>
31 13
GND SDA2 CLK_DDC2_DOCK DAT_DDC2_DOCK <38>
33 15
GPAD SCL2 CLK_DDC2_DOCK <38>
PI3V713-AZLEX_TQFN32_6X3~D
change TI(SA00004RS0L) as main source from Pericom +3.3V_RUN +5V_RUN
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1 1 1 1 1 1
@C332
@
@C333
@
SEL1/SEL2 Chanel Source
C332
C333
C334
C335
C336
C339
0 A=B1 MB 2 2 2 2 2 2
1 A=B2 APR/SPR
Close to U18
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT CRT/Video switch
2 1
5 4 3 2 1
+3.3V_RUN
1 2 LDDC_CLK_PCH
R159 2.2K_0402_5%~D
JLVDS1 1 2 LDDC_DATA_PCH
1 R160 2.2K_0402_5%~D +LCDVDD
1 +CAMERA_VDD
2 DMIC0
2 Place near to JLVDS1 +PWR_SRC_S
130_0402_1%~D
3 Q18
LCD Power
3
1
4 DMIC_CLK0 SI3456DDV-T1-GE3_TSOP6~D
4 +LCDVDD +3.3V_ALW
R413
5
D
5
1 470K_0402_5%~D
6 USBP12_D- 6
S
6 USBP12_D+ +3.3V_ALW
7 4 5
7
R412
0.1U_0402_25V6K~D
D D
8 CAM_MIC_CBL_DET# <17> 2
2
8
+LCVDVDD_CHG
9 +BL_PWR_SRC 1
9
1 10K_0402_5%~D
10
G
1
2
10
C292
11
3
11 DISP_ON
12
12
R414
13
13 1 2 BIA_PWM_LVDS
2
0.022U_0402_25V7K~D
14 LE92 BLM18BB221SN1D_2P~D
LCD_CBL_DET# <17>
2
14
4.7M_0402_5%~D
15
15
1
16 LCD_BCLK+_PCH <16> 1
16
R1632
C293
17 LCD_BCLK-_PCH <16>
17
5P_0402_50V8C~D
5P_0402_50V8C~D
Q19A
Q19B
18
18
19 19 LCD_B2+_PCH <16> 1 1 2 5
2
@ C40
@ C41
20 LCD_B2-_PCH <16>
2
20
21 LCD_B1+_PCH <16>
4
21
22 22 LCD_B1-_PCH <16>
1
2 2
23 23 LCD_B0+_PCH <16>
24 24 LCD_B0-_PCH <16>
25 25
26 26 LCD_ACLK+_PCH <16> <39> LCD_VCC_TEST_EN 2
27 1 EN_LCDPWR 2
27 LCD_ACLK-_PCH <16>
28 28
29 29 LCD_A2+_PCH <16> <16,39> ENVDD_PCH 3
5P_0402_50V8C~D
5P_0402_50V8C~D
30 1 1 Q20
30 LCD_A2-_PCH <16>
@ C42
@ C43
31 PDTC124EU_SC70-3~D
LCD_A1+_PCH <16>
3
31 D6
32 32 LCD_A1-_PCH <16>
33 BAT54CW_SOT323-3~D
33 LCD_A0+_PCH <16> 2 2
34 34 LCD_A0-_PCH <16>
35 35 LDDC_DATA_PCH <16>
41 G1 36 36 LDDC_CLK_PCH <16>
42 G2 37 37 LCD_TST <39>
43 G3 38 38 +3.3V_RUN
44 G4 39 39
C C
45 G5 40 40 +LCDVDD
STARC_111H40-100000-G4-R
CONN@
Link CIS +PWR_SRC Q21
40mil FDC654P-G_SSOT-6~D +BL_PWR_SRC 40mil
D
6
S
4 5
0.1U_0603_50V7K~D
2
+LCDVDD +3.3V_RUN +BL_PWR_SRC 1 1
1000P_0402_50V7K~D
100K_0402_5%~D
C296
1
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0603_50V7K~D
3
1 2
R422
1 1 1
C298
C243
C246
C297
2
2
2 2 2
PWR_SRC_ON
FDC654P: P CHANNAL
Close to JLVDS1.39,40 Close to JLVD1.38 Close to JLVD1.38 Q22
1 2 1 3
S
R423 47K_0402_5%~D
BIA_PWM_LVDS 1 2 DISP_ON 1 2
G
BIA_PWM_PCH <16> PANEL_BKEN_PCH <16>
2
10K_0402_5%~D
100K_0402_5%~D
D66 D67
<40> EN_INVPWR
1
RB751VM-40TE-17_SOD323-2~D RB751VM-40TE-17_SOD323-2~D
R1137
R1138
B B
1 2 BIA_PWM_EC <40> 1 2 PANEL_BKEN_EC <39>
D68 D69 Panel backlight power control by EC
2
RB751VM-40TE-17_SOD323-2~D RB751VM-40TE-17_SOD323-2~D
@ R427
1 2
0_0402_5%~D Webcam PWR CTRL
L10 +CAMERA_VDD Q23 +3.3V_RUN
USBP12+ 1 2 USBP12_D+ DMIC_CLK0 PMV65XP_SOT23-3~D
<17> USBP12+ 1 2 <29> DMIC_CLK0
0.1U_0402_25V6K~D
DMIC0 1 3
S
<29> DMIC0
0.1U_0402_25V6K~D
10U_0805_10V6K~D
USBP12- 4 3 USBP12_D-
<17> USBP12- 4 3
2
1
3
OCF2012181YZF_4P
PESD5V0U2BT_SOT23-3~D
C301
1 1
G
2
C299
C300
1 2
@ R428 0_0402_5%~D 2
2 2 <39> CCD_OFF
D8
D9
1
1
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT LVDS & CAM Conn
5 4 3 2 1
2 1
L99
1 2
9NH_0402HS-9N0EJTS_5%~D
L19 @
C353 2 1 0.1U_0402_10V7K~D TMDSB_PCH_CLK#_C 4 3 TMDSB_CON_CLK#
<16> TMDSB_PCH_CLK# 4 3
+5V_RUN
C352 2 1 0.1U_0402_10V7K~D TMDSB_PCH_CLK_C 1 2 TMDSB_CON_CLK

<16> TMDSB_PCH_CLK 1 2
RB751VM-40TE-17_SOD323-2~D
3.9P_0402_50V8C
3.9P_0402_50V8C
DLW21SN900HQ2L_0805_4P~D
2
L100 1 1
1 0_0402_5%~D
C1209
C1210
1 2
@ D65
R1163
+3.3V_RUN
2 2
2
L101
B B
1 2
2
L20 @
1 6 PCH_SDVO_CTRLCLK_R 1 2 +5V_HDMI_DDC C351 2 1 0.1U_0402_10V7K~D TMDSB_PCH_P0_C 1 2 TMDSB_CON_P0
<16> PCH_SDVO_CTRLCLK <16> TMDSB_PCH_P0 1 2
R1153 2.2K_0402_5%~D
Q120A
5
DMN66D0LDW-7_SOT363-6~D C350 2 1 0.1U_0402_10V7K~D TMDSB_PCH_N0_C 4 3 TMDSB_CON_N0

<16> TMDSB_PCH_N0 4 3 +3.3V_RUN
3.9P_0402_50V8C
3.9P_0402_50V8C
4 3 PCH_SDVO_CTRLDATA_R 1 2 DLW21SN900HQ2L_0805_4P~D 1 1
<16> PCH_SDVO_CTRLDATA
C1211
C1212
R1152 2.2K_0402_5%~D L102 HDMI_CEC 2 1
Q120B 1 2 R1165 10K_0402_5%~D
DMN66D0LDW-7_SOT363-6~D 9NH_0402HS-9N0EJTS_5%~D
2 2
L103
1 2
Note:
L22 @ AOI found open soldering is
C347 2 1 0.1U_0402_10V7K~D TMDSB_PCH_P1_C 1 2 TMDSB_CON_P1 due to the difference between
<16> TMDSB_PCH_P1 1 2
Main and 2nd on PAD dimension.
C346 2 F2 change to 2nd source
<16> TMDSB_PCH_N1 1 0.1U_0402_10V7K~D TMDSB_PCH_N1_C 4 3 TMDSB_CON_N1 +5V_RUN
4 3 "SP040003H0L (F_MF-MSMF050-2)"
3.9P_0402_50V8C
3.9P_0402_50V8C
BAT1000-7-F_SOT23-3~D
DLW21SN900HQ2L_0805_4P~D 1 1 PCB Footprint
C1213
C1214
L104
2
3
1 2
NC
2 2
D4
+3.3V_RUN
L105 +VDISPLAY_VCC
2+5V_RUN_HDMI 1
1 2
1M_0402_5%~D
2
R1168
0.1U_0402_10V7K~D
10U_0805_10V6K~D
L21 @
C349 2 1 0.1U_0402_10V7K~D TMDSB_PCH_P2_C 1 2 TMDSB_CON_P2
<16> TMDSB_PCH_P2 1 2
1 1
2
G
0.5A_15V_SMD1812P050TF
C338
1
C337
C348 2 1 0.1U_0402_10V7K~D TMDSB_PCH_N2_C 4 3 TMDSB_CON_N2
<16> TMDSB_PCH_N2 4 3
2 0_1206_5%~D
3 1 HDMIB_PCH_HPD_R 1 2
<16> HDMIB_PCH_HPD 2 2
3.9P_0402_50V8C
3.9P_0402_50V8C
R1128 20K_0402_5%~D DLW21SN900HQ2L_0805_4P~D
S
F2
@
L106 1 1
C1215
C1216
R5
Q121 1 2
SSM3K7002FU_SC70-3~D 9NH_0402HS-9N0EJTS_5%~D
1
2 2 CONN@
JHDMI1
HDMIB_PCH_HPD_R 19
HP_DET
18
+5V
17
TMDSB_PCH_P2_C R452 604_0402_1% HDMI_OB PCH_SDVO_CTRLDATA_R DDC/CEC_GND
1 2 16
TMDSB_PCH_N2_C R450 604_0402_1% PCH_SDVO_CTRLCLK_R SDA
1 2 15
TMDSB_PCH_P1_C R448 604_0402_1% SCL
1 2 14
TMDSB_PCH_N1_C R449 604_0402_1% HDMI_CEC Reserved
1 2 13
TMDSB_PCH_P0_C R454 604_0402_1% TMDSB_CON_CLK# CEC
1 2 12 20
TMDSB_PCH_N0_C R453 604_0402_1% CK- GND
1 2 11 21
TMDSB_PCH_CLK_C R456 604_0402_1% TMDSB_CON_CLK CK_shield GND
1 2 10 22
CK+ GND
TMDSB_PCH_CLK#_C R455 1 2 604_0402_1% TMDSB_CON_N0 9 23
D0- GND
8
TMDSB_CON_P0 D0_shield
7
1
D TMDSB_CON_N1 D0+
6
D1-
Q26
+3.3V_RUN R458 1 2 10K_0402_5%~D 2 5
G TMDSB_CON_P1 D1_shield
4
A TMDSB_CON_N2 D1+ A
S 3
3
D2-
2
TMDSB_CON_P2 D2_shield
1
D2+
HONGL_13-13201904CP
Link CIS
HDMI 46@
Part Number Description
RO0000002HM HDMI W/Logo:RO0000002HM
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT HDMI port
2 1
5 4 3 2 1
D D
AUX/DDC SW for DPD to E-DOCK AUX/DDC SW for DPC to E-DOCK

+3.3V_RUN
C366 +3.3V_RUN
1 2 C356
1 2
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
U23
1 14 U20
DPD_AUX_C BE0 VCC
<16> DPD_PCH_DOCK_AUX 2 1 2 A0 BE3 13 1 BE0 VCC 14
C367 0.1U_0402_10V7K~D 2 1 DPC_AUX_C 2 13
<16> DPC_PCH_DOCK_AUX A0 BE3
3 12 C357 0.1U_0402_10V7K~D
<38> DPD_DOCK_AUX B0 A3 PCH_DDPD_CTRLCLK <16>
<38> DPC_DOCK_AUX 3 B0 A3 12 PCH_DDPC_CTRLCLK <16>
4 BE1 B3 11
C DPD_AUX#_C C
<16> DPD_PCH_DOCK_AUX# 2 1 5 A1 BE2 10 4 BE1 B3 11
C368 0.1U_0402_10V7K~D 2 1 DPC_AUX#_C 5 10
<16> DPC_PCH_DOCK_AUX# A1 BE2
6 9 C360 0.1U_0402_10V7K~D
<38> DPD_DOCK_AUX# B1 A2 PCH_DDPD_CTRLDATA <16>
<38> DPC_DOCK_AUX# 6 B1 A2 9 PCH_DDPC_CTRLDATA <16>
7 GND B2 8
7 GND B2 8
PI3C3125LEX_TSSOP14~D
PI3C3125LEX_TSSOP14~D
+5V_RUN
C369
1 2 +5V_RUN
C365
0.1U_0402_25V6K~D 1 2
5
0.1U_0402_25V6K~D
P
NC
1
2 4 DPD_CA_DET#
<38> DPD_CA_DET A Y
NC
G
U24 2 4 DPC_CA_DET#
<38> DPC_CA_DET A Y
TC7SET04FU_SSOP5~D
3
G
U21
TC7SET04FU_SSOP5~D
3
Note:When implement 2nd source, please check Vil and Vih spec is meet main source spec
Note:When implement 2nd source, please check Vil and Vih spec is meet main source spec
B B
+3.3V_RUN
1 2 PCH_DDPC_CTRLCLK
R487 2.2K_0402_5%~D Intel WW18 Strapping option
1 2 PCH_DDPC_CTRLDATA
R488 2.2K_0402_5%~D
1 2 PCH_DDPD_CTRLCLK
R489 2.2K_0402_5%~D Intel WW18 Strapping option
1 2 PCH_DDPD_CTRLDATA
R490 2.2K_0402_5%~D
1 2 DPD_CA_DET
R491 1M_0402_5%~D
1 2 DPC_CA_DET
R492 1M_0402_5%~D
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DP SW
5 4 3 2 1
5 4 3 2 1
D D
HDD power +PWR_SRC_S

+5V_ALW
1100K_0402_5%~D
@
+3.3V_RUN
R499
+3.3V_ALW2
1 2 DDR_XDP_WAN_SMBDAT
1
2
5
6
R501 10K_0402_5%~D
100K_0402_5%~D
1 2 DDR_XDP_WAN_SMBCLK D @ Q27
2
1
@ R500
R502 10K_0402_5%~D G SI3456DDV-T1-GE3_TSOP6~D
1 2 HDD_FALL_INT HDD_EN_5V 3
R503 100K_0402_5%~D S
4
3
+3.3V_RUN
1M_0402_5%~D
0.1U_0603_50V7K~D
2
1
@
@
@ PJP53 1 +5V_HDD +5V_RUN
Q28B
R517
C393
1 2 +3.3V_RUN_FFS @ PJP3
10U_0603_6.3V6M~D
0.1U_0402_25V6K~D
5 1 2
1 2
10U_0805_10V6K~D
PAD-OPEN1x1m
2
100K_0402_5%~D
1 1 1 JUMP_43X79
2
6
1
@
C387
C388
C394
R504
Q28A
2 2 U88 2
<35,39,42,47,48> RUN_ON 1 2 2
LNG3DM @ R1621 0_0402_5%~D
2
100K_0402_5%~D
C C
10 <11,16,35,39,42,47,48,49> SIO_SLP_S3# 1 2
1
RES
1
1 13 @ R1624 0_0402_5%~D
VDD_IO RES
@
14 VDD RES 15
R505
RES 16
HDD_FALL_INT 11
<17> HDD_FALL_INT FFS_INT2 INT 1
9 5
2
INT 2 GND
GND 12
7
SDO/SA0
<7,12,13,14,15,34> DDR_XDP_WAN_SMBDAT 6
SDA / SDI / SDO
<7,12,13,14,15,34> DDR_XDP_WAN_SMBCLK 4
SCL/SPC
2
NC
8 3
CS NC
LNG3DMTR_LGA16_3X3~D
JSATA1
1
+5V_HDD C383 2 SATA_PTX_DRX_P0 GND
<14> PSATA_PTX_DRX_P0_C 1 0.01U_0402_16V7K~D 2
C384 2 SATA_PTX_DRX_N0 A+
<14> PSATA_PTX_DRX_N0_C 1 0.01U_0402_16V7K~D 3
A-
4
GND
100K_0402_5%~D
C385 2 1 0.01U_0402_16V7K~D SATA_PRX_DTX_N0 5

<14> PSATA_PRX_DTX_N0_C B-
1
@ R506
C386 2 1 0.01U_0402_16V7K~D SATA_PRX_DTX_P0 6

<14> PSATA_PRX_DTX_P0_C B+
7
+3.3V_RUN GND
@ PJP64
100K_0402_5%~D
1 2 +3.3V_RUN_HDD 8
+3.3V_RUN
2
V33
1
9
V33
R508
B FFS_INT2_Q PAD-OPEN1x1m B
10
V33
Note : Short PJP64 for SSD HDD issue 11
GND
HDD_DET# 12
<14> HDD_DET# GND
3
13
2
GND
+5V_HDD 14
V5
Q29B
15
V5
5 16
V5
17
GND
6
+5V_HDD +3.3V_RUN_HDD FFS_INT2_Q 18

4
Reserved
19 23
GND GND
20 24
V12 GND
Q29A
1000P_0402_50V7K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
FFS_INT2 2 21
<18> FFS_INT2 V12
0.1U_0402_25V6K~D
22
V12
1 1 1 1
1
C395
C396
C402
C399
SANTA_198202-1
CONN@
2 2 2 2
Link CIS
Close to JSATA1
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT HDD CONNECTOR
5 4 3 2 1
5 4 3 2 1
D D
+3.3V_RUN
C C
2 1 DEVICE_DET#
ODD power R1125 100K_0402_5%~D
CONN@
JSATA2
+PWR_SRC_S +5V_ALW 1
GND
<14> SATA_ODD_PTX_DRX_P1_C
C407 2 1 0.01U_0402_16V7K~D SATA_ODD_PTX_DRX_P1 2
RX+
470K_0402_5%~D
<14> SATA_ODD_PTX_DRX_N1_C
C406 2 1 0.01U_0402_16V7K~D SATA_ODD_PTX_DRX_N1 3
RX-
1
+3.3V_ALW2 4
GND
R507
C405 2 1 0.01U_0402_16V7K~D SATA_ODD_PRX_DTX_N1 5

<14> SATA_ODD_PRX_DTX_N1_C TX-
100K_0402_5%~D
C404 2 1 0.01U_0402_16V7K~D SATA_ODD_PRX_DTX_P1 6

TX+
<14> SATA_ODD_PRX_DTX_P1_C
1
1
2
5
6
7
GND
R509
D Q30
2
G SI3456DDV-T1-GE3_TSOP6~D DEVICE_DET# 8
<40> DEVICE_DET# DP
2 MOD_EN 3 +5V_MOD 9
S +5V
10
2
+5V
3
0.022U_0402_25V7K~D
+5V_MOD +5V_RUN PAD~D T88 @ TEST POINT 11

4
MD
4.7M_0402_5%~D
@ PJP4 12 14
GND GND1
1
Q31B
1 1 2 13 15
1 2 GND GND2
R518
C400
MODC_EN# 5
10U_0805_10V6K~D
100K_0402_5%~D
JUMP_43X79 SANTA_205902-1~D
6
1
1 Link CIS
4
2
R511
2
Q31A
C401
+5V_MOD
<39> MODC_EN 2
2
2
100K_0402_5%~D
1000P_0402_50V7K~D
0.1U_0402_25V6K~D
1
1
1 1
R512
C397
C398
B B
2 2
2
Close to JSATA2
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT ODD CONNECTOR
5 4 3 2 1
2 1
+5V_RUN
Place C994, C952~C957 close to Codec
Internal Speakers Header +3.3V_RUN +3.3V_RUN_DVDD +3.3V_RUN_DVDD
place close to pin27
+VDDA_AVDD 1
L77
2
BLM21PG600SN1D_0805~D
0.1U_0402_25V6K~D
1U_0603_10V7K~D
10U_0805_10V6K~D
15 mils trace JSPK1 1 1 1
INT_SPK_L+ L91 1 2 BLM18PG121SN1D_0603 INT_SPKL_L+ 1 PJP60
@PJP60
@ +DVDD_CORE +5V_RUN
1
C957
C956
C955
INT_SPK_L- L92 1 2 BLM18PG121SN1D_0603 INT_SPKR_L- 2 1 2
2
0.1U_0402_25V6K~D
10U_0805_10V6K~D
INT_SPK_R+ L93 1 2 BLM18PG121SN1D_0603 INT_SPKR_R+ 3 1 1
3 2 2 2
1U_0603_10V7K~D
0.1U_0402_25V6K~D
INT_SPK_R- L94 1 2 BLM18PG121SN1D_0603 INT_SPKR_R- 4 1 1 +VDDA_PVDD 2 1
4 PAD-OPEN1x1m 0_0805_5%~D R1095
C952
C994
C953
C954
10U_0805_10V6K~D
0.1U_0402_25V6K~D
10U_0805_10V6K~D
0.1U_0402_25V6K~D
5
GND 2 2 U72
6 1 1 1 1
GND 2 2
2200P_0402_50V7K~D
2200P_0402_50V7K~D
2200P_0402_50V7K~D
2200P_0402_50V7K~D
1
DVDD_CORE AVDD1
27 C957 place close to pin38
C958
C959
C960
C961
1 1 1 1 ACES_50279-0040N-001 38
CONN@ AVDD2
2 2 2 2
C973
C974
C975
C976
3 45
Link CIS DVDD_IO PVDD
39
2 2 2 2 PVDD
2
9 13 AUD_SENSE_A +VREFOUT
DVDD SENSE_A AUD_SENSE_B
14
SENSE_B
1U_0603_10V7K~D
1
3.3_0402_5%~D
3.3_0402_5%~D
3.3_0402_5%~D
3.3_0402_5%~D
28 MIC_IN_L C1163 1 2 2.2U_0603_6.3V6K~D
PORTA_L MIC_IN_R <37>
2
DE2
DE1
C1180
PCH_AZ_CODEC_BITCLK 6 29 MIC_IN_R
<14> PCH_AZ_CODEC_BITCLK BITCLK PORTA_R
R169
R170
R171
R172
23 +VREFOUT
VrefOut_A +VREFOUT 2
PCH_AZ_CODEC_SDOUT 5 1 2
<14> PCH_AZ_CODEC_SDOUT SDATA_OUT
31 R1143 2.2K_0402_5%~D
PORTB_L AUD_HP_OUT_L <37>
10 32
1
1
<14> PCH_AZ_CODEC_SYNC SYNC PORTB_R AUD_HP_OUT_R <37>
B R1096 1 2 33_0402_5%~D PCH_AZ_SDIN0_R 8 40 INT_SPK_L+ B
<14> PCH_AZ_CODEC_SDIN0 SDATA_IN PORTD_+L INT_SPK_L-
Place R1096 close to codec PORTD_-L
41
Place closed U72 PCH_AZ_CODEC_RST# 11
<14> PCH_AZ_CODEC_RST# RESET# INT_SPK_R+
44
PORTD_+R INT_SPK_R-
43
PORTD_-R
I2S_MCLK @
@R167
R167 1 2 0_0402_5%~D I2S_MCLK_R 15 25 AUD_PC_BEEP C1105 2 1 0.1U_0402_25V6K~D R1119 1 2 100K_0402_5%~D
I2S_MCLK MONO_OUT SPKR <14>
I2S_BCLK @
@R168
R168 1 2 0_0402_5%~D I2S_BCLK_R 16 12 C1106 2 1 0.1U_0402_25V6K~D R1120 1 2 100K_0402_5%~D
I2S_SCLK PC_BEEP BEEP <40>
Place LE3/LE4 close to codec
I2S_DO R1097 1 2 33_0402_5%~D I2S_DO_R 17 LE3 1 2 BLM18BB221SN1D_2P~D
I2S_DOUT DMIC_CLK_L LE4 DMIC_CLK0 <24>
Place R1097 close to codec 2 1 2 BLM18BB221SN1D_2P~D @R1141
@ R1141 1 2 10K_0402_5%~D
I2S_LRCLK DMIC_CLK/GPIO 1 DMIC_CLK1 <43>
18 4 DMIC0 <24>
I2S_LRCLK DMIC_0/GPIO 2 @R1142
@ R1142 1
46 DMIC1 <43> 2 10K_0402_5%~D
I2S_DI# DMIC1/GPIO0/SPDIFOUT1
24 48 1 2 EN_I2S_NB_CODEC# <39>
I2S_DIN SPDIFOUT0//GPIO3/Aux_Out R1641 0_0402_5%~D
36
CAP+
1
19
+3.3V_RUN No Connect C962
Close to U72 pin5 Close to U72 pin6 4.7U_0603_6.3V6K~D
20
No Connect 2
+3.3V_RUN 1 2
CAP-
35 Place C962 close to codec
4.7K_0402_5%~D
PCH_AZ_CODEC_SDOUT PCH_AZ_CODEC_BITCLK R1099 10K_0402_5%~D

1
@R1084
@
47 21 CODEC_VREF
<39> AUD_NB_MUTE# EAPD VREFFILT
10_0402_1%~D
R1084
22 CODEC_CAP2
CAP2
1
47_0402_5%~D
@R1076
@
34 CODEC_VN
V-
1
@R1077
@
R1076
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
1U_0603_10V7K~D
10U_0805_10V6K~D
7 37 CODEC_VREG
DVSS Vreg
R1077
1 1 1 1
2
42 26
PVSS AVSS1
C963
C964
C965
C966
30
2
PCH_AZ_CODEC_RST# AVSS
49 33
2
GND AVSS 2 2 2 2
0.1U_0402_10V7K~D
10P_0402_50V8J~D
10P_0402_50V8J~D
1 1 92HD90B2X5NLGXYAX8_QFN48_7X7~D
1
@C978
@
@C977
@
@C984
@
C978
C977
C984
2 2
2 Notes: place at AGND and DGND plane
Keep PVDD supply and speaker traces routed on the DGND plane. 1 2
C981 0.1U_0402_25V6K~D
Keep away from AGND and other analog signals 1 2
place at Codec bottom side C982 0.1U_0402_25V6K~D
1 2
@PJP62
@ PJP62 C983 0.1U_0402_25V6K~D
1 2 1 2
Place closely to Pin 13. C985 0.1U_0402_25V6K~D
PAD-OPEN1x1m 1 2
+VDDA_AVDD @PJP63
@ PJP63 C986 0.1U_0402_25V6K~D
1 2 1 2
C987 0.1U_0402_25V6K~D
AUD_SENSE_A 2 R1083 1
2.49K_0402_1%~D PAD-OPEN1x1m
20K_0402_1%~D
0.1U_0402_10V7K~D
1
1
R1086
C980
+3.3V_RUN
2 +3.3V_RUN
2
100K_0402_5%~D
+3.3V_RUN
1
R1087
0.1U_0402_10V7K~D
6
2
DA204U_SOT323-3~D
DA204U_SOT323-3~D
DA204U_SOT323-3~D
DA204U_SOT323-3~D
2
2
C1103
@D54
@
@D55
@
@D56
@
@D57
@
D54
D55
D56
D57
DMIC0 Camera/B
2 5 AUD_HP_NB_SENSE <37,39> 1
0.1U_0402_25V6K~D
Q107A Q107B 1 DMIC1 Power/B

1
1
DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D U73 @
@C967
@
R162, R163, R164, R165,R166 CO-lay with U73 16

VCC
C967
2 DAI_BCLK# R162 1 2 22_0402_5%~D I2S_BCLK 2 3 DAI_BCLK#

1A 1Y# DAI_BCLK# <38>
A
Add for solve pop noise and detect issue Resistor SENSE_A SENSE_B A
DAI_LRCK# R163 1 2 0_0402_5%~D I2S_LRCLK 4 5 DAI_LRCK#
2A 2Y# DAI_LRCK# <38>
39.2K PORT A PORT E DAI_DO# R164 1 2 0_0402_5%~D I2S_DO 6 7 DAI_DO#
3A 3Y# DAI_DO# <38>
DAI_12MHZ# R165 1 2 22_0402_5%~D I2S_MCLK 10 9 DAI_12MHZ#
4A 4Y# DAI_12MHZ# <38>
20K PORT B PORT F
12 11
Place closely to Pin 14 5A 5Y# +3.3V_RUN
+VDDA_AVDD 10K NA DMIC0 14 13 I2S_DI# 1 2 DAI_DI
6A 6Y# R166 0_0402_5%~D
EN_I2S_NB_CODEC# 1
OE1#
2
AUD_SENSE_B 2 R1078 1 5.11K SPDIFOUT0 SPDIFOUT1 (DMIC1) 2 1 15 8
2.49K_0402_1%~D @R1540
@ R1540 1K_0402_1%~D OE2# GND @D58
@ D58
DA204U_SOT323-3~D
39.2K_0402_1%~D
20K_0402_1%~D
1000P_0402_50V7K~D
1 2.49K Pull-up to AVDD CD74HC366M96_SO16~D

1
+3.3V_RUN
R1079
R1080
C979
+3.3V_RUN
1
1 100K_0402_5%~D
2
100K_0402_5%~D
PORT A External MIC

1
DAI_DI <38>
R1081
R1082
PORT B HeadPhone Out

2
PORT C Dock Audio

<39> DOCK_HP_DET 2 5 DOCK_MIC_DET <39>
PORT D Internal SPK
Q106A Q106B
1
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Azalia (HD) Codec
2 1
5 4 3 2 1
UL1A +3.3V_LAN
BCM5761 LAN_SMB_CLK 2 1
CL4 2 1 0.1U_0402_10V7K~D PCIE_PRX_GLANTX_P7_C A10 K2 LAN_TX0+ 2.2K_0402_5%~D RL28
<15> PCIE_PRX_GLANTX_P7 PCIE_TXDP TRD0+
K1 LAN_TX0- LAN_SMB_DATA 2 1
CL1 PCIE_PRX_GLANTX_N7_C TRD0-
<15> PCIE_PRX_GLANTX_N7 2 1 0.1U_0402_10V7K~D B10 2.2K_0402_5%~D RL29
PCIE_TXDN LAN_TX1+ LAN_APE_SMB_CLK0
TRD1+ J2 2 1
CL2 1 2 0.1U_0402_10V7K~D PCIE_PTX_GLANRX_P7_C A6 J1 LAN_TX1- 2.2K_0402_5%~D RL30
<15> PCIE_PTX_GLANRX_P7 PCIE_RXDP TRD1- LAN_APE_SMB_DATA0 2 1
Media
CL3 1 2 0.1U_0402_10V7K~D PCIE_PTX_GLANRX_N7_C B6 H2 LAN_TX2+ 2.2K_0402_5%~D RL31
<15> PCIE_PTX_GLANRX_N7 PCIE_RXDN TRD2+
PCI-E
H1 LAN_TX2- LAN_APE_SMB_CLK1 2 1
TRD2- 2.2K_0402_5%~D RL32
<15> CLK_PCIE_LAN A8 REFCLK+
G2 LAN_TX3+ LAN_APE_SMB_DATA1 2 1
TRD3+ LAN_TX3- 2.2K_0402_5%~D RL33
<15> CLK_PCIE_LAN# B8 REFCLK- TRD3- G1
D ENERGYDET 2 1 D
+3.3V_RUN RL1 1 2 10K_0402_5%~D 10K_0402_5%~D RL2
@ RL3 1 2 0_0402_5%~D LANCLK_REQ#_R J9 J8 ENERGYDET 0_0402_5%~D 2 1 RL4 @ LOM_SMB_ALERT# 2 1
<15> LANCLK_REQ# CLKREQ# ENERGYDET LOM_ENERGY_DET <39>
4.7K_0402_5%~D RL12
+3.3V_LAN NV_STRAP1 2 1
PLTRST_LAN# J10 G7 LOM_VAUXPRSNT 1K_0402_1%~D 2 1 RL5 +3.3V_LAN 4.7K_0402_5%~D @ RL20
<17> PLTRST_LAN# PERST# VAUXPRSNT NV_STRAP0 2 1
PCIE_WAKE# K7 B1 LOM_VMAINPRSNT 1K_0402_1%~D 2 1 RL6 +3.3V_RUN 4.7K_0402_5%~D @ RL19
<34,35,40> PCIE_WAKE# WAKE# VMAINPRSNT
4.7K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
1
F10 LOM_LOW_PWR_R 0_0402_5%~D 2 1 RL7 @

LOW_PWR LOM_LOW_PWR <39>
@ RL18
@ RL17
@ RL16
@ RL15
LAN_SMB_CLK H5
LAN_SMB_DATA SMB_CLK GPIO1 1K_0402_1%~D 2
J6 E5 1 RL8 @ +3.3V_LAN
SMB_DATA GPIO1/SERIAL_DI
2
SMBUS
LAN_APE_SMB_CLK0 L10 J7 GPIO2 1K_0402_1%~D 2 1 RL9 @
LAN_APE_SMB_DATA0 APE_SMB_CLK0 GPIO2/SERIAL_DO
L9
LAN_SCLK APE_SMB_DATA0 GPIO0 @ TL1 PAD~D
D2
Misc
LAN_CS# LAN_APE_SMB_CLK1 GPIO0
L8
LAN_SI LAN_APE_SMB_DATA1 APE_SMB_CLK1
L7
LAN_SO APE_SMB_DATA1 APE_GPIO0 @ TL2 PAD~D
L3
APE_GPIO0
L4 LOM_SMB_ALERT# <39>
APE_GPIO1 APE_GPIO2 @ TL3 PAD~D +3.3V_LAN
L5
APE_GPIO2
4.7K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
USB
F11 L6 APE_GPIO3 @ TL4 PAD~D
HUSB_DP APE_GPIO3
1
10K_0402_5%~D
E11 L2 APE_GPIO5 @ TL5 PAD~D
HUSB_DN APE_GPIO5
1
@ RL27
@ RL26
@ RL25
@ RL24
L1 APE_GPIO6 @ TL6 PAD~D

APE_GPIO6
R549
C1 APE_GPIO4 @ RL13 1 2 0_0402_5%~D
NV_STRAP1 APE_GPIO4
C10 LOM_ENEGRY_DET is high active (TM )
2
NV_STRAP0 NV_STRAP1
D10
2
NV_STRAP0 WLAN_LAN_DISB# (vpro) is low active.
NVRAM
B2 LAN_PWR_DOWN RL14 1 2 4.7K_0402_5%~D
LAN_SO PWR_DOWN LOM_LOW_PWR_R
G5
SO 1.TM config, --> depop U15
LAN_SI J3
SI WLAN_LAN_DISB# signal level is floating.
10K_0402_5%~D
LAN_CS# K3
CS#
1
@ R557
LAN_SCLK J4 G10 LAN_TMS @ TL7 PAD~D 2.vPro config,
SCLK TMS LAN_TDO @ TL8 PAD~D
K6 LOM_ENERGY_DET pull high always.
TDO LAN_TDI @ TL9 PAD~D
F9
TEST
TDI LAN_TCK @ TL10 PAD~D
H7
LOM_SPD10LED_GRN# TCK LAN_TRST# @ TL11 PAD~D
C K5 K9 C
2
RL22 XTALO LOM_SPD100LED_ORG# LINKLED# TRST#
1 2 200_0402_1%~D J5
SPD100LED#
LED
PAD~D TL12 @ K4 E2 GPHY_TVCOI @ RL21 1 2 4.7K_0402_5%~D
SPD1000LED# GPHY_TVCOI
YL1 XTALI LOM_ACTLED_YEL# H6
25MHZ_10PF_X3G025000FA1H~D TRAFFICLED#
1 IN
OUT 3
Clock
2 4 XTALO A4
Bias
GND GND XTALO
12P_0402_50V8J~D
12P_0402_50V8J~D
F1 RDAC RL23 1 2 1.2K_0402_1%~D

XTALI RDAC
1 1 B4 XTALI
CL5
CL6
2 2 +3.3V_LAN
BCM5761B0KFBGH_FBGA121~D
+3.3V_LAN
@ C478
1 2
2
+3.3V_LAN 2 1
+3.3V_LAN +3.3V_LAN SIO_LAN_SMBCLK <15,40>
0.1U_0402_10V7K~D 0_0402_5%~D RL50
5
0.1U_0402_25V6K~D
LAN_APE_SMB_CLK0 1 6 2 1 SML1_SMBCLK <15,40>

LOM_SPD100LED_ORG# 1 QL2A 0_0402_5%~D RL49 @
P
UL3 @ B DMN66D0LDW-7_SOT363-6~D
1 O 4 WLAN_LAN_DISB# <39>
UL2 8 1 LAN_CS# LOM_SPD10LED_GRN# 2
VCC S# A
G
CL7
8 1 LAN_CS# 7 2 LAN_SI @ U15 2 1

VCC S# RESET# Q
5
7 2 LAN_SI LAN_SCLK 6 3 TC7SH08FU_SSOP5~D 0_0402_5%~D RL10 @ 2 1 SIO_LAN_SMBDATA <15,40>
3
LAN_SCLK RESET# Q 2 LAN_SO C W# 0_0402_5%~D RL51
6 C W# 3 5 D VSS 4
LAN_SO 5 4 LAN_APE_SMB_DATA0 4 3 2 1
D VSS SML1_SMBDATA <15,40>
M25PE80-VMW6TP_SO8W8 QL2B 0_0402_5%~D RL48 @
M25PE80-VMN6TP_SO8N8 CL7 place close to UL2 DMN66D0LDW-7_SOT363-6~D
co-lay with UL2
2 1
B 0_0402_5%~D RL11 @ B
+3.3V_LAN
LAN ANALOG SWITCH

0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1 1 1
C472
C473
C474
2 2 2
+PWR_SRC_S Q34
+3.3V_ALW SI3456DDV-T1-GE3_TSOP6~D +3.3V_LAN +3.3V_M
39
30
21
14
8
4
1
U32
D
100K_0402_5%~D
Layout Notice : Place as 6
VDD
VDD
VDD
VDD
VDD
VDD
VDD
S
1
38 +3.3V_ALW2 5 4 1 2
close PI3L500 as possible B0+ SW_LAN_TX0+ <37>
R564
37 2 @ R563 0_1206_5%~D
B0- SW_LAN_TX0- <37>
10U_0603_6.3V6M~D
LAN_TX0+ L30 1 2 0_0603_5%~D LAN_TX0+R 2 1
A0+
0.1U_0402_10V7K~D
34 1 1
G
B1+ SW_LAN_TX1+ <37>
100K_0402_5%~D
LAN_TX0- L31 1 2 0_0603_5%~D LAN_TX0-R 3 33 SW_LAN_TX1- <37>
3
A0- B1-
C475
C476
R565
B2+ 29 SW_LAN_TX2+ <37>
LAN_TX1+ L33 1 2 0_0603_5%~D LAN_TX1+R 6 28 ENAB_3VLAN 2 2
A1+ B2- SW_LAN_TX2- <37>
3
1M_0402_5%~D
2200P_0402_50V7K~D
LAN_TX1- L32 1 2 0_0603_5%~D LAN_TX1-R 7 25 SW_LAN_TX3+ <37>
2
A1- B3+
1
B3- 24 SW_LAN_TX3- <37>
Q35B
R1638
1
LAN_TX2+ L34 1 2 0_0603_5%~D LAN_TX2+R 9 17 5
A2+ LEDB0 LAN_ACTLED_YEL# <37>
C477
LEDB1 18 LED_100_ORG# <37>
LAN_TX2- L35 1 2 0_0603_5%~D LAN_TX2-R 10 41 LED_10_GRN# <37>
2
A2- LEDB2
6
2
36 @ RL46 1 2 0_0402_5%~D
C0+ DOCK_LOM_TRD0+ <38> <40> AUX_ON
Q35A
LAN_TX3+ L36 1 2 0_0603_5%~D LAN_TX3+R 11 35
A3+ C0- DOCK_LOM_TRD0- <38>
@ RL47 1 2 0_0402_5%~D 2
<16,39> SIO_SLP_LAN#
LAN_TX3- L37 1 2 0_0603_5%~D LAN_TX3-R 12 32
A3- C1+ DOCK_LOM_TRD1+ <38>
A 31 DOCK_LOM_TRD1- <38> A
1
C1-
<39> DOCKED
13 SEL C2+ 27 DOCK_LOM_TRD2+ <38>
C2- 26 DOCK_LOM_TRD2- <38>
LOM_ACTLED_YEL#
TO DOCK
15 LEDA0 C3+ 23 DOCK_LOM_TRD3+ <38>
LOM_SPD100LED_ORG# 16 22
LEDA1 C3- DOCK_LOM_TRD3- <38>
LOM_SPD10LED_GRN# 42 LEDA2
LEDC0 19 DOCK_LOM_ACTLED_YEL# <38>
5 PD LEDC1 20 DOCK_LOM_SPD100LED_ORG# <38>
1: TO DOCK LEDC2 40 DOCK_LOM_SPD10LED_GRN# <38> Compal Electronics, Inc.
FROM NIC DOCKED 43 PAD_GND Title
0: TO RJ45 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT LAN (1/2) BCM5761
PI3L720ZHEX_TQFN42_9X3P5~D
change TI(SA00003LD0L) as main source from Pericom NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
5 4 3 2 1
5 4 3 2 1
UL1B
+1.2V_LAN +1.2V_LAN_PCIE_SDSVDDL +1.2V_LAN
LL1 BCM5761
1 2 H8 VDDC_H08 VSS_H09 H9
BLM18AG601SN1D_0603~D H4
VSS_H04
4.7U_0603_6.3V6K~D
0.1U_0402_25V6K~D
G9 VDDC_G09 VSS_G11 G11
1 1 VSS_G06 G6
CL10
CL11
G8 VDDC_G08 VSS_G04 G4
F8
VSS_F08
E10 F7
2 2 VDDC_E10 VSS_F07
F6
VSS_F06
Power
Digital
D D
C9 E8
VDDC_C09 VSS_E08
E7
GND
VSS_E07
E6
LAN_VDDP VSS_E06
2 1 F4 E4
+3.3V_LAN CL12 1U_0603_10V7K~D VDDP VSS_E04
D4
VSS_D04
D3
VSS_D03
K8 C6
+3.3V_LAN +3.3V_LAN_XTALVDDH VDDIO_K08 VSS_C06
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
B11
LL2 VSS_B11
1 1 H10 B7
VDDIO_H10 VSS_B07
1 2 A11
VSS_A11
0.1U_0402_25V6K~D
CL8
CL9
BLM18AG601SN1D_0603~D C2 A9
VDDIO_C02 VSS_A09
1 VSS_A07 A7
2 2 A3 A2
VDDIO_A03 VSS_A02
+3.3V_LAN
CL13
2 +1.2V_LAN_PCIE_SDSVDDL B9 PCIE_SDSVDDL
D7 LAN_TP_D07 RL34 2 1 10K_0402_5%~D
TP_D07 LAN_TP_D06 RL35 10K_0402_5%~D
TP_D06 D6 2 1
+3.3V_LAN_XTALVDDH A5 D5 LAN_TP_D05 RL36 2 1 10K_0402_5%~D
XTALVDDH TP_D05 LAN_TP_C05 RL37 10K_0402_5%~D
TP_C05 C5 2 1
+3.3V_LAN +3.3V_LAN_BIASVDDH F5 LAN_TP_F05 RL38 2 1 10K_0402_5%~D
LL3 TP_F05 LAN_TP_C03 RL39 10K_0402_5%~D
TP_C03 C3 2 1
Power
Bias
1 2 B5 LAN_TP_B05 RL40 2 1 10K_0402_5%~D
TP_B05
0.1U_0402_25V6K~D
BLM18AG601SN1D_0603~D +3.3V_LAN_BIASVDDH F2 BIASVDDH
1
NC_C04 C4
CL14
L11 LAN_NC_L11 @ TL13
@TL13 PAD~D
NC_L11 LAN_NC_K11 @TL14
@ TL14 PAD~D
NC_K11 K11
2 LAN_NC_J11 @TL15
@ TL15 PAD~D
J11
Others
+1.2V_LAN_AVDDL NC_J11 LAN_NC_H11 @TL16
@ TL16 PAD~D
E3 AVDDL_E03 NC_H11 H11
Power
Analog
F3 AVDDL_F03
C LAN_NC_K10 @RL41
@ RL41 1 C
NC_K10 K10 2 4.7K_0402_5%~D
DC_D11 D11
+1.2V_LAN +1.2V_LAN_AVDDL +3.3V_LAN_AVDDH G3 B3
LL4 AVDDH_G03 NC_B03
1 2 H3 AVDDH_H03
4.7U_0603_6.3V6K~D
0.1U_0402_25V6K~D
BLM18AG601SN1D_0603~D D9 LAN_DC_D09 @RL42

@ RL42 2 1 4.7K_0402_5%~D
DC_D09 +3.3V_LAN
1 1
E9
DC_E09
CL15
CL16
C8
DC_C08
2 2 +1.2V_LAN_PCIE_PLLVDDL C7 D8 LAN_TP_D08 RL43 1 2 4.7K_0402_5%~D
PCIE_PLLVDDL TP_D08
Power
PLL
+1.2V_LAN_GPHY_PLLVDDL
Regulator
E1
GPHY_PLLVDDL LAN_REGCTL12
D1
Voltage
+3.3V_LAN +3.3V_LAN_AVDDH REGCTL12
LL5
1 2 +1.2V_LAN_PLLVDDL C11 A1 LAN_REGOUT25 1 2 LAN_VDDP
USB_PLLVDDL REGOUT25
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
BLM18AG601SN1D_0603~D RL44 0_0402_5%~D

1 1
CL17
CL18
BCM5761B0KFBGH_FBGA121~D
2 2
+3.3V_LAN
+1.2V_LAN +1.2V_LAN_PCIE_PLLVDDL
LL6
+1.2V_LAN
4.7U_0603_6.3V6K~D
1 2
4.7U_0603_6.3V6K~D
0.1U_0402_25V6K~D
BLM18AG601SN1D_0603~D
11.5_1206_5%
1 1 1
CL19
CL21
B B
CL20
RL45
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2 2 2 1 1 1 1
CL22
CL23
CL24
CL25
2 2 2 2
3
LAN_REGCTL12 1
+1.2V_LAN_GPHY_PLLVDDL
0.047U_0402_16V4Z~D
LL7 1
2
4
@ CL29
1 2
4.7U_0603_6.3V6K~D
0.1U_0402_25V6K~D
1 1 QL1
2
10U_0805_10V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
PBSS5540Z_SOT223-3~D
CL26
CL27
1 1 1 1 1
CL31
CL32
CL33
CL34
CL35
2 2
2 2 2 2 2
+1.2V_LAN_PLLVDDL
LL8
1 2
4.7U_0603_6.3V6K~D
0.1U_0402_25V6K~D
A
1 1 A
CL30
CL28
2 2
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT LAN (2/2) BCM5761
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN +3.3V_RUN_TPM
@PJP61
@ PJP61
1 2 +3.3V_SB3V
PAD-OPEN1x1m
+3.3V_RUN_TPM
0.1U_0402_25V6K~D
4700P_0402_25V7K~D
+3.3V_SB3V
1@ C44
1@ C45
1 1
+3.3V_RUN_TPM
1 2
1@ R873 0_0402_5%~D
D 2 2 D
ATMEL TPM for E4
2200P_0402_50V7K~D
2200P_0402_50V7K~D
2200P_0402_50V7K~D
0.1U_0402_25V6K~D
1@ U39 1 1 1 1
+3.3V_RUN_TPM 5@ 5@ 5@ 5@
C550
C551
C552
C553
10
VCC_0
5 19
SB3V VCC_1 2 2 2 2
1 2 VCC_2
24
@ R1663 10K_0402_5%~D
1 2
R1662 0_0402_5%~D
5@
1 2 SP_TPM_LPC_EN_R 28 12 NC_12
<39> SP_TPM_LPC_EN LPCPD# V_BAT
@ D87 RB751S40T1_SOD523-2~D 13
NBO_13 JETWAY_CLK14M <15>
LPC_LAD0 26 14 NC_P 1 2
<14,34,39,40> LPC_LAD0 LPC_LAD1 LAD0 NBO_14
23 4@ C554 1U_0402_6.3V6K~D
<14,34,39,40> LPC_LAD1 LPC_LAD2 LAD1
<14,34,39,40> LPC_LAD2 20 LAD2
LPC_LAD3 17
<14,34,39,40> LPC_LAD3 LAD3 NC_6
GPIO6 6
CLK_PCI_TPM_TCM 21 9 TCM_BA0
<15> CLK_PCI_TPM_TCM LPC_LFRAME# LCLK TESTBI
<14,34,39,40> LPC_LFRAME# 22 LFRAME# TESTI 8
PCH_PLTRST#_EC 16
<17,34,35,39,40> PCH_PLTRST#_EC IRQ_SERIRQ LRESET#
27 +3.3V_RUN_TPM
<14,39,40> IRQ_SERIRQ CLKRUN# SERIRQ
<16,39,40> CLKRUN# 15 CLKRUN#
7 PP 1 2
NC_7 @ R656 4.7K_0402_5%~D
CLK_PCI_TPM_TCM 1 4
ATEST_1 GND_4
2 ATEST_2 GND_11 11
TCM_BA1 3 18
ATEST_3 GND_18
1
33_0402_5%~D
GND_25 25
@ RE5
C C
AT97SC3204-X2A18-AB_TSSOP28
2
Co-lay U37 and U39 1 2

27P_0402_50V8J~D
1 @ R741 0_0402_5%~D
@ CE3
LPC layout: Place TCM first and then end LPC with TPM. L52
2 4 3 USBP13_R_D-
<17> USBP13- 4 3
1 2 USBP13_R_D+
<17> USBP13+ 1 2
OCF2012181YZF_4P
2
China TCM: NationZ & Jetway co-lay
1 2
@ R742 0_0402_5%~D
D73
+3.3V_RUN_TPM
LOW:Power Down Mode 4@ U37
High:Working Mode 10
1
VDD_0
19
VDD_1
24
VDD_2
SP_TPM_LPC_EN_R 28
B LPC_LAD0 LPCPD# B
26 11
LPC_LAD1 LAD0 GND_11
23 18
20 25
17 4
LAD3 GND_4 +3.3V_SB3V
+3.3V_RUN
JBIO1
CLK_PCI_TPM_TCM 21 5 1
LPC_LFRAME# LCLK NC_5 NC_12 1
22 12 2
LFRAME# NC_12 2
0.1U_0402_25V6K~D
PCH_PLTRST#_EC 16 13 JETWAY_CLK14M USBP13_R_D- 3
IRQ_SERIRQ LRESET# NC_13 USBP13_R_D+ 3
27 1 4
SERIRQ 4
C51
+3.3V_RUN_TPM CLKRUN# 15 1 5 7
PP CLKRUN# NC_1 5 G1
7 2 6 8
TCM_BA1 PP NC_2 NC_6 6 G2
3 6
TCM_BA0 BA_1 NC_6 JETWAY_CLK14M 2 PS_HPF10052-06M000R
9 8
BA_0 NC_8 NC_P CONN@
14
NC_P
10K_0402_5%~D
10K_0402_5%~D
Link CIS
1
1
@R657
@
33_0402_5%~D
1
R657
@ R658
@ RE6
SSX44-B-D-T1_TSSOP28~D
2
2
TCM_BA0
27P_0402_50V8J~D
TCM_BA1
1
10K_0402_5%~D
10K_0402_5%~D
@ CE4
1
5@ 5@
R659
R660
2
2
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT TPM/TCM/BIO Conn
5 4 3 2 1
A B C D E
1 1
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
1 1
+1.5V_RUN +VDDH_SD +3.3V_RUN
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
C559
C560
L47 L45
1 2 1 2 1 1
4.7U_0603_6.3V6K~D 2 2
0.1U_0402_25V6K~D
BLM18BD601SN1D_0603~D BLM18PG471SN1D_2P~D
4.7U_0603_6.3V6K~D
0.01U_0402_16V7K~D
0.1U_0402_25V6K~D
C563
C564
1 1
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
1 1 1 2 2
C561
C562
1 1
C577
C576
C575
2 2
C565
C566
U38
2 2 2
+3.3VDDH +OZ_DVDD 2 2
16 3.3VDDH DVDD 10
+VDDH_SD 9 8 +OZ_AVDD
+PE_VDDH VDDH AVDD
32 PE_VDDH
+3.3V_RUN SD/MMC_CLK
+PE_VDDH 17 +SKT_VCC
L44 SKT_VCC
MMI_VCC_OUT 15 +3.3V_RUN_CARD
2 33_0402_5%~D
1 2 <15> CLK_PCIE_MMI 2 PE_REFCLKP
0.1U_0402_25V6K~D
0.01U_0402_16V7K~D
4.7U_0603_6.3V6K~D
@RE678
@
BLM18BD601SN1D_0603~D 1 28 SD/MMCDAT1_R R663 1 2 33_0402_5%~D SD/MMCDAT1
<15> CLK_PCIE_MMI# PE_REFCLKM SD_D1
RE678
1 1 1 26 SD/MMCDAT2_R R664 1 2 33_0402_5%~D SD/MMCDAT2
SD_D2 SD/MMCDAT0_R
MMI_D0 29 R665 1 2 33_0402_5%~D SD/MMCDAT0
C573
C574
C578
C569 1 2 0.1U_0402_10V7K~D PCIE_PRX_MMITX_P6_C 6 27
1
<15> PCIE_PRX_MMITX_P6 C571 0.1U_0402_10V7K~D PCIE_PRX_MMITX_N6_C PE_TXP MS_D1
<15> PCIE_PRX_MMITX_N6 1 2 7 PE_TXM MS_D2 25
2 2 2 C567 1 2 0.1U_0402_10V7K~D PCIE_PTX_MMIRX_P6_C 5 24 SD/MMCDAT3_R R668 1 2 33_0402_5%~D SD/MMCDAT3
<15> PCIE_PTX_MMIRX_P6 PE_RXP MMI_D3
10P_0402_50V8J~D
2 C568 0.1U_0402_10V7K~D PCIE_PTX_MMIRX_N6_C SD/MMCDAT4_R R669 33_0402_5%~D SD/MMCDAT4 2
<15> PCIE_PTX_MMIRX_N6 1 2 4 PE_RXM MMI_D4 23 1 2
@ CE757
R677 1 2 191_0402_1%~D 3 22 SD/MMCDAT5_R R670 1 2 33_0402_5%~D SD/MMCDAT5 1
PE_REXT MMI_D5 SD/MMCDAT6_R R672 33_0402_5%~D SD/MMCDAT6
Place R677 close to U38 MMI_D6 21 1 2
33 20 SD/MMCDAT7_R R673 1 2 33_0402_5%~D SD/MMCDAT7
GPAD MMI_D7
PLTRST_MMI# 13 11 2
place close to pin U38.32 <17> PLTRST_MMI# PE_RST# MS_CD#
19 SD/MMCCMD_R R674 1 2 33_0402_5%~D SD/MMCCMD
SD_CMD/MS_BS SD/MMCCLK_R
18 R676 1 2 10_0402_1%~D SD/MMC_CLK
MMI_CLK SD/MMCCD#
14 12
MMICLK_REQ# MULTI-IO1 SD_CD# SDWP
31 30
<15> MMICLK_REQ# MULTI-IO2 SD_WPI Place closed R676 pin 2
OZ600FJ0LN_QFN32_5X5~D
Note: The trace need to route as

daisy-chain and the trace of SD signals
need to route as short as possible
JSD1
+3.3V_RUN_CARD SD/MMCDAT3 14
SD/MMCCMD DAT3/SD1
12
CMD/SD2
10
VSS1/SD3
9
SD/MMC_CLK VCC/SD4
8
CLK/SD5
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
6
GND/VSSS2/SD6
1
10K_0402_5%~D
1 1 SD/MMCDAT0 4
SD/MMCDAT1 DAT0/SD7
3
Vendor review in 6/22 and reserve for SD3.0 UHS-I 200MHz transfer DAT1/SD8
C570
C572
R826
SD/MMCDAT2 15
3 DAT2/SD9 3
SD/MMCDAT0 SD/MMCDAT1 SD/MMCDAT2 SD/MMCDAT3 SD/MMCCMD 2 2 SD/MMCDAT4 13
2
SD/MMCDAT5 DAT4/MMC10
11
DAT5/MMC11
10P_0402_50V8J~D
10P_0402_50V8J~D
10P_0402_50V8J~D
10P_0402_50V8J~D
10P_0402_50V8J~D
SD/MMCDAT6 7
DAT6/MMC12
@ C775
@ C776
@ C777
@ C779
@ C780
1 1 1 1 1 SD/MMCDAT7 5
DAT7/MMC13
19
CD_WP_SW/GND
20
2 2 2 2 2 CD_WP_SW/GND
SD/MMCCD# 17
SDWP CD_SW/SD
18
SD/MMCCD# WP_SW/SD
2
SDWP CD_SW_TAISOL/SD
1
WP/SW_TAISOL/SD
16
GND_SW
T-SOL_156-4000000601_NR
CONN@
4 4
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Card Reader OZ600FJ0
A B C D E
5 4 3 2 1
Mini WLAN/WIMAX H=6.7

1 2
@ R693 0_0402_5%~D +3.3V_ALW_PCH
1 2 WLAN_RADIO_DIS#_R PCIE_MCARD1_DET# 1 2
<39> WLAN_RADIO_DIS#
R692 100K_0402_5%~D
D31
RB751S40T1_SOD523-2~D +3.3V_RUN
USB_MCARD1_DET# 1 2 PCIE_MCARD1_DET#
@R698
@ R698 0_0402_5%~D PCIE_MCARD1_DET# 1 2
@R699
@ R699 100K_0402_5%~D
USB_MCARD1_DET# 1 2
D D
+3.3V_WLAN +3.3V_WLAN R701 100K_0402_5%~D
CONN@
JMINI2 +1.5V_RUN
1 2
<30,35,40> PCIE_WAKE# @ R700 1 1 2
2 0_0402_5%~D 3
3 4
4
<41> COEX2_WLAN_ACTIVE @ R702 1 2 0_0402_5%~D 5 6
<41> COEX1_BT_ACTIVE 5 6
7 8
<15> MINI2CLK_REQ# 7 8
9 10
9 10
<15> CLK_PCIE_MINI2# 11 12
11 12 MSDATA
<15> CLK_PCIE_MINI2 13 14
13 14 HOST_DEBUG_TX
15 16 HOST_DEBUG_TX <40>
Mini WWAN/GPS/LTE/UWB H=4 <40> HOST_DEBUG_RX
<40> MSCLK
17
19
21
15
17
19
21
16
18
20
22
18
20
22
WLAN_RADIO_DIS#_R
2 1 PCH_PLTRST#_EC
PCIE_PRX_WLANTX_N2 23 24 @R703
@ R703 0_0402_5%~D
<15> PCIE_PRX_WLANTX_N2 PCIE_PRX_WLANTX_P2 23 24
<15> PCIE_PRX_WLANTX_P2
25 25 26 26
27 27 28 28
+3.3V_PCIE_WWAN C596 0.1U_0402_10V7K~D 29 30
29 30
<15> PCIE_PTX_WLANRX_N2 1 2 PCIE_PTX_WLANRX_N2_C 31 32
31 32
<15> PCIE_PTX_WLANRX_P2 1 2 PCIE_PTX_WLANRX_P2_C 33 33 34 34
USB_MCARD2_DET# 1 2 PCIE_MCARD2_DET# C598 0.1U_0402_10V7K~D 35 36 USBP4-
35 36 USBP4- <17>
2.2K_0402_5%~D
2.2K_0402_5%~D
@ R697 0_0402_5%~D PCIE_MCARD1_DET# 37 38 USBP4+
<18> PCIE_MCARD1_DET# 37 38 USBP4+ <17>
1
@ R1160
@ R1159
39 40 USB_MCARD1_DET#
39 40 WIMAX_LED# USB_MCARD1_DET# <14,18>
41 41 42 42
43 44 WLAN_LED#
43 44
<15> PCH_CL_CLK1 45 45 46 46
+3.3V_RUN 47 48 1 2
2
<15> PCH_CL_DATA1 47 48 MSDATA <40>
@ R707 1 2 0_0402_5%~D 49 50 @ R706 0_0402_5%~D
USB_MCARD2_DET# WWAN_SMBCLK <15> PCH_CL_RST1# 49 50
1 2 1 2 DDR_XDP_WAN_SMBCLK <7,12,13,14,15,27> 51 51 52 52 WIMAX_LED# STUDY FOR DEBUG
R694 100K_0402_5%~D 0_0402_5%~D R1157 @
WWAN_SMBDAT 1 2 53 54
DDR_XDP_WAN_SMBDAT <7,12,13,14,15,27> GND1 GND2
0_0402_5%~D R1158 @
BELLW_80003-4041
+3.3V_PCIE_WWAN CONN@ +3.3V_PCIE_WWAN Link CIS

JMINI1
PCIE_WAKE# 1 2 +3.3V_WLAN +3.3V_WLAN
1 2 +1.5V_RUN +3.3V_WLAN
C 3 3 4 4 C
5 5 6 6 +1.5V_RUN_WWAN
MINI1CLK_REQ# 7 8
<15> MINI1CLK_REQ# 7 8 +SIM_PWR
100K_0402_5%~D
100K_0402_5%~D
9 10 UIM_DATA COEX2_WLAN_ACTIVE HOST_DEBUG_TX
9 10 UIM_DATA <37>
2
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
0.1U_0402_25V6K~D
CLK_PCIE_MINI1# 11 12 UIM_CLK
<15> CLK_PCIE_MINI1# 11 12 UIM_CLK <37>
4700P_0402_25V7K~D
CLK_PCIE_MINI1 13 14 UIM_RESET 1 1 1 1 1 2 2 1
<15> CLK_PCIE_MINI1 13 14 UIM_RESET <37>
33P_0402_50V8J~D
@ C603
R718
R705
15 16 UIM_VPP
15 16 UIM_VPP <37>
C601
C602
C604
C605
C606
C607
C608
17 17 18 18 1
5
@ C600
C595
19 20 1
1
19 20 WWAN_RADIO_DIS# <39> 2 2 2 2 2 1 1 2
21 21 22 22 1 2 PCH_PLTRST#_EC <17,32,35,39,40>
PCIE_PRX_WANTX_N1 23 24 @R704
@ R704 0_0402_5%~D WIMAX_LED# 4 3 WIRELESS_LED#
<15> PCIE_PRX_WANTX_N1 PCIE_PRX_WANTX_P1 23 24 2
<15> PCIE_PRX_WANTX_P1
25 25 26 26
27 28 2 Q124B
27 28
2
29 30 WWAN_SMBCLK DMN66D0LDW-7_SOT363-6~D
29 30
<15> PCIE_PTX_WANRX_N1
C597 1 2 0.1U_0402_10V7K~D PCIE_PTX_WANRX_N1_C 31 32 WWAN_SMBDAT
31 32
<15> PCIE_PTX_WANRX_P1
C599 1 2 0.1U_0402_10V7K~D PCIE_PTX_WANRX_P1_C 33 34 WLAN_LED# 1 6
33 34 USBP5-
35 35 36 36 USBP5- <17>
1 2 PCIE_MCARD2_DET#_R 37 38 USBP5+ Q124A
<17> PCIE_MCARD2_DET# 37 38 USBP5+ <17>
@ R725 0_0402_5%~D 39 40 USB_MCARD2_DET# DMN66D0LDW-7_SOT363-6~D
39 40 LED_WWAN_OUT# USB_MCARD2_DET# <18>
41 41 42 42
43 43 44 44
45 45 46 46
47 47 48 48
49 50
<39> HW_GPS_DISABLE2# 51
53
49
51
GND1 GND2
50
52 52
54
1/2 Minicard Pink Pather/60GHz Card H=6.7
LCN_DAN08-52406-0500 +3.3V_RUN
Link CIS
1 2 PCIE_MCARD3_DET# +3.3V_PCIE_FLASH +3.3V_PCIE_FLASH
R711 100K_0402_5%~D USB_MCARD3_DET# 1 2 PCIE_MCARD3_DET#
+3.3V_PCIE_WWAN CONN@ @ R708 0_0402_5%~D
+1.5V_RUN +1.5V_RUN_WWAN +3.3V_PCIE_WWAN JMINI3 +1.5V_RUN
PCIE_WAKE# 1 2
COEX2_WLAN_ACTIVE 1 1 2
2 1 2 3 4
3 4
330U_D2E_6.3VM_R25~D
R727 0_0805_5%~D @ R709 0_0402_5%~D 5 6

5 6
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
33P_0402_50V8J~D
22U_0805_6.3V6M~D
33P_0402_50V8J~D
100K_0402_5%~D
7 8 LPC_LFRAME#
<15> MINI3CLK_REQ# 7 8 LPC_LFRAME# <14,32,39,40>
2
B B
33P_0402_50V8J~D
0.047U_0402_16V4Z~D
330U_6.3V_M
1 1 1 1 1 1 1 9 10 LPC_LAD3
9 10 LPC_LAD3 <14,32,39,40>
@ C1176
R719
1 1 CLK_PCIE_MINI3# 11 12 LPC_LAD2
<15> CLK_PCIE_MINI3# 11 12 LPC_LAD2 <14,32,39,40>
C593
C594
C610
C611
C612
C613
C614
C615
+ + CLK_PCIE_MINI3 13 14 LPC_LAD1
<15> CLK_PCIE_MINI3 13 14 LPC_LAD1 <14,32,39,40>
15 16 LPC_LAD0
15 16 LPC_LAD0 <14,32,39,40>
2
2 2 2 2 2
G
PCH_PLTRST#_EC 17 18
1
2 2 2 2 17 18
<15> PCLK_80H 19 19 20 20
LED_WWAN_OUT# 3 1 21 22 1 2 PCH_PLTRST#_EC
WIRELESS_LED# <39,43> 21 22
PCIE_PRX_WPANTX_N5
S
23 24 @ R710 0_0402_5%~D
<15> PCIE_PRX_WPANTX_N5 PCIE_PRX_WPANTX_P5 23 24
25 25 26 26
Q77 <15> PCIE_PRX_WPANTX_P5
27 27 28 28
SSM3K7002FU_SC70-3~D 29 30
29 30
<15> PCIE_PTX_WPANRX_N5
C617 1 2 0.1U_0402_10V7K~D PCIE_PTX_WPANRX_N5_C 31 31 32 32
<15> PCIE_PTX_WPANRX_P5
C618 1 2 0.1U_0402_10V7K~D PCIE_PTX_WPANRX_P5_C 33 33 34 34
35 36 USBP6-
35 36 USBP6+ USBP6- <17>
Primary Power Aux Power <18> PCIE_MCARD3_DET#
37 37 38 38 USBP6+ <17>
PWR Voltage 39 40 NC_USB_MCARD3_DET#
39 40
41 42
Rail Tolerance Peak Normal Normal 43
41 42
44
43 44
45 45 46 46
47 47 48 48
+3.3V +-9% 1000 750 49 49 50 50
51 51 52 52
250 (Wake enable)
+3.3Vaux +-9% 330 250 5 (Not wake enable) 53 GND1 GND2 54
+1.5V +-5% 500 375 NA BELLW_80003-4041
Link CIS
+1.5V_RUN +3.3V_PCIE_FLASH
WPAN Noise
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
0.1U_0402_25V6K~D
USB_MCARD3_DET#
4700P_0402_25V7K~D
1 1 1 1 1 2 2 1
@C621
@
1
@ C627
C619
C620
C621
C622
C623
C624
C625
C626
A A
2 2 2 2 2 1 1 2
2
Title
Mini Card
1.0
LA-7901P
5 4 3 2 1
5 4 3 2 1
D D
+3.3V_SUS
1 2 CARD_SMBDAT
Express/Smart Card Conn.
R731 2.2K_0402_5%~D
1 2 CARD_SMBCLK
R732 2.2K_0402_5%~D +3.3V_RUN +1.5V_RUN
JEXP1
2 1
Power Control for Mini card2

2 1
4 4 3 3
6 6 5 5
8 8 7 7
<17> USBP10+ 10 10 9 9
+PWR_SRC_S Q38 12 11
<17> USBP10- 12 11 +5V_RUN
+3.3V_ALW SI3456DDV-T1-GE3_TSOP6~D 14 13
14 13
100K_0402_5%~D
+3.3V_WLAN 16 15
<15> CLK_PCIE_EXP# 16 15
D
6 18 17
S
<15> CLK_PCIE_EXP 18 17
R714
5 4 20 20 19 19 +3.3V_SUS
+3.3V_ALW 2 <15> PCIE_PRX_EXPTX_N3 22 21
22 21
20K_0402_5%~D
1 <15> PCIE_PRX_EXPTX_P3 24 24 23 23
1
100K_0402_5%~D
C647 0.1U_0402_10V7K~D 26 25 0_0402_5%~D 2 1 R734 @
G
SIO_SLP_S3# <11,16,27,39,42,47,48,49>
2
26 25
1
R715
<15> PCIE_PTX_EXPRX_N3 1 2 PCIE_PTX_EXPRX_N3_C 28 27
3
28 27 EXPRESS_DET# <39>
R713
<15> PCIE_PTX_EXPRX_P3 1 2 PCIE_PTX_EXPRX_P3_C 30 30 29 29 EXPRCRD_STBY_R# 0_0402_5%~D 2 1 R717 @ RUN_ON <27,39,42,47,48>

C648 0.1U_0402_10V7K~D 32 31
32 31 EXPCLK_REQ# <15>
<40> CARD_SMBCLK 34 33
2
34 33 SMART_DET# <39>
3
<40> CARD_SMBDAT 36 35 PCH_PLTRST#_EC <17,32,34,39,40>
2
36 35
1M_0402_5%~D
4700P_0402_25V7K~D
38 38 37 37
1
1 <30,34,40> PCIE_WAKE# 40 40 39 39 CLK_SMART_48M <15>
Q39B
R1620
5
C632
42 G2 G1 41
6
2
Q39A
C E&T_1001K-F40C-03L C
2 CONN@
<39> AUX_EN_WOWL
Link CIS
100K_0402_5%~D
1
1
R716
+1.5V_RUN +3.3V_RUN +3.3V_SUS +5V_RUN +1.5V_RUN

EXPCLK_REQ# EXPRESS_DET# PCH_PLTRST#_EC
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2
1 1 1 1 1 1 1 1
C635
C634
C633
C645
C636
CE20
CE22
CE14
2 2 2 2 2 2 2 2
Close to JEXP1 ESD Request
Power Control for Mini card3

B
Power Control for Mini card1 +PWR_SRC_S B
+3.3V_ALW Q42 +3.3V_PCIE_FLASH
+PWR_SRC_S SI3456DDV-T1-GE3_TSOP6~D
470K_0402_5%~D
+3.3V_ALW Q40 +PCIE_WWAN +3.3V_PCIE_WWAN
D
470K_0402_5%~D
SI3456DDV-T1-GE3_TSOP6~D +3.3V_ALW 6
S
R729
5 4
D
1
+3.3V_ALW 6 @ PJP9 2
S
R722
100K_0402_5%~D
20K_0402_5%~D
5 4 1 2 1
1
2
G
2
100K_0402_5%~D
1K_0402_1%~D
R728
R730
1 PAD-OPEN 1x3m
3
1
1
G
2
R721
3
R723
2
2
4.7M_0402_5%~D
220P_0402_50V8J~D
3
1
220P_0402_50V8J~D
Q43B
1
2
2
4.7M_0402_5%~D
R1628
1 5
1
C650
+3.3V_WWAN_CHG
6
Q41B
R1625
C644
MCARD_WWAN_PWREN# 5
4
2
2
6
2
Q43A
4
<39> MCARD_MISC_PWREN 2
2
Q41A
1
100K_0402_5%~D
<39> MCARD_WWAN_PWREN 2
1
100K_0402_5%~D
R733
1
1
D
R726
Q73
2 MCARD_WWAN_PWREN#
2
G
S
3
2
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT MINI CARD PWR/EXP_SC
5 4 3 2 1
5 4 3 2 1
1 2
@ R736 0_0402_5%~D
1 2
@ R1606 0_0402_5%~D L51
4 3 USBP1_R_D-
<17> USBP1- 4 3
L96
C412 2 1 .1U_0402_16V7K~D USB3T_N2 1 2 USB3TN2_D-
<17> USB3TN2 1 2 USBP1_R_D+
<17> USBP1+ 1 1 2 2
2
C413 2 1 .1U_0402_16V7K~D USB3T_P2 4 3 USB3TP2_D+ DLW21SN900SQ2L_0805_4P~D
<17> USB3TP2 4 3
DLW21SN900HQ2L_0805_4P~D 1 2 +5V_USB_PWR CONN@
@ R740 0_0402_5%~D JUSB1
D72
D D
1 2 1
VBUS
150U_D2_6.3VY_R15M~D
@ R1603 0_0402_5%~D USBP1_R_D- 2
D-
0.1U_0402_25V6K~D
1 USBP1_R_D+ 3
D+
1 4
GND
C651
+ USB3RN2_D- 5
1
StdA-SSRX-
C654
USB3RP2_D+ 6 10
StdA-SSRX+ GND
7 11
2 2 USB3TN2_D- GND-DRAIN GND
8 12
USB3TP2_D+ StdA-SSTX- GND
9 13
StdA-SSTX+ GND
@ R1605
1 2
0_0402_5%~D
Place D72 close to JUSB1 LOTES_AUSB0015-P001A
D78
L95 USB3TP2_D+ 1 10 USB3TP2_D+ Link CIS
1 2 USB3RN2_D-
<17> USB3RN2 1 2 USB3TN2_D- USB3TN2_D-
2 9
4 3 USB3RP2_D+ USB3RP2_D+ 4 7 USB3RP2_D+

<17> USB3RP2 4 3
DLW21SN900HQ2L_0805_4P~D USB3RN2_D- 5 6 USB3RN2_D-
1 2 3
@ R1604 0_0402_5%~D
8
IP4292CZ10-TB_XSON10U10~D
Place D78 close to JUSB1
+5V_USB_PWR
C C
+5V_ALW U48 +SATA_SIDE_PWR
1 GND FAULT1# 10 USB_OC0# <17,37>
2 IN OUT1 9
10U_0805_10V6K~D
0.1U_0402_25V6K~D
3 IN OUT2 8
4 EN1# ILIM 7
1 1 <39> ESATA_USB_PWR_EN# 5 EN2# FAULT#2 6 USB_OC1# <17>
C676
C675
24.9K_0402_1%~D
11
T-PAD
1
R748
TPS2560DRCR-PG1.1_SON10_3X3~D
2 2
2
+SATA_SIDE_PWR
150U_D2_6.3VY_R15M~D
0.1U_0402_25V6K~D
1 2 1 2 1
@ R1609 0_0402_5%~D @ R1150 0_0402_5%~D 1
C667
C668
+
L97 L90
C414 2 1 .1U_0402_16V7K~D USB3T_N3 1 2 USB3TN3_D- 1 2 USBP2_D-
<17> USB3TN3 1 2 <17> USBP2- 1 2 2 2
C415 2 1 .1U_0402_16V7K~D USB3T_P3 4 3 USB3TP3_D+ 4 3 USBP2_D+

<17> USB3TP3 4 3 <17> USBP2+ 4 3 CONN@
DLW21SN900HQ2L_0805_4P~D DLW21SN900SQ2L_0805_4P~D JESA1
1
VBUS
2
1 2 1 2 USBP2_D- 2
B @ R1612 0_0402_5%~D @ R1151 0_0402_5%~D USBP2_D+ D- USB2.0 B
3
D+
4
GND
D74
5
GND
<14> ESATA_PTX_DRX_P4_C C671 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_P4 6
A+
<14> ESATA_PTX_DRX_N4_C C672 1 2 0.01U_0402_16V7K~D SATA_PTX_DRX_N4 7
A- ESATA
8
1
GND
C673 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_N4 9
<14> ESATA_PRX_DTX_N4_C B-
C674 1 2 0.01U_0402_16V7K~D SATA_PRX_DTX_P4 10
B+
<14> ESATA_PRX_DTX_P4_C
11
GND
Place D74 close to JESATA1 USB3RN3_D- 12

USB3RP3_D+ SSRX-
13
D79 SSRX+
1 2 14
@ R1607 0_0402_5%~D USB3TP3_D+ USB3TP3_D+ USB3TN3_D- GND
1 10 15
USB3TP3_D+ SSTX- USB3.0
16
L98 USB3TN3_D- USB3TN3_D- SSTX+
2 9
1 2 USB3RN3_D-
<17> USB3RN3 1 2 USB3RP3_D+ 4 7 USB3RP3_D+ 17
GND
18
USB3RP3_D+ USB3RN3_D- USB3RN3_D- GND
<17> USB3RP3 4 3 5 6 19
4 3 GND
20
DLW21SN900HQ2L_0805_4P~D GND
3
TAIWI_EU147-165CRL-TW
1 2 8
@ R1608 0_0402_5%~D Link CIS
IP4292CZ10-TB_XSON10U10~D
Place D79 close to JESATA1
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT USB2.0/3.0 ESATA
5 4 3 2 1
5 4 3 2 1
D D
IO BOARD
+5V_ALW
AUDIO BOARD 1
3
JIO1
1
3
2
4
2
4
+SIM_PWR
UIM_CLK <34>
5 5 6 6 UIM_RESET <34>
7 7 8 8 UIM_VPP <34>
JAUD1 9 10
<17,36> USB_OC0# 9 10 UIM_DATA <34>
1 1 <39> USB_SIDE_EN# 11 11 12 12
2 2 AUD_HP_OUT_R <29> 13 13 14 14 +3.3V_ALW_PCH
3 3 <17> USBP0- 15 15 16 16
4 4 AUD_HP_OUT_L <29> <17> USBP0+ 17 17 18 18 PCH_AZ_MDC_SDIN1 <14>
5 5 19 19 20 20 PCH_AZ_MDC_SYNC <14>
6 SW_LAN_TX0- 21 22 PCH_AZ_MDC_SDOUT <14>
6 MIC_IN_R <29> <30> SW_LAN_TX0- 21 22
7 SW_LAN_TX0+ 23 24 PCH_AZ_MDC_RST1#
7 <30> SW_LAN_TX0+ 23 24
8 8 25 25 26 26 PCH_AZ_MDC_BITCLK <14>
AUD_HP_NB_SENSE <29,39> SW_LAN_TX1-
9 9 <30> SW_LAN_TX1- 27 27 28 28
USB_OC4# <17> SW_LAN_TX1+ RED_CRT
10 10 USB_SIDE_EN# <39> <30> SW_LAN_TX1+ 29 29 30 30 RED_CRT <23>
11 +5V_ALW 31 32 GREEN_CRT GREEN_CRT <23>
11 SW_LAN_TX2- 31 32 BLUE_CRT
12 12 <30> SW_LAN_TX2- 33 33 34 34 BLUE_CRT <23>
13 SW_LAN_TX2+ 35 36
13 <30> SW_LAN_TX2+ 35 36 HSYNC_BUF
14 14 37 37 38 38 HSYNC_BUF <23>
15 SW_LAN_TX3- 39 40 VSYNC_BUF VSYNC_BUF <23>
15 <30> SW_LAN_TX3- 39 40
16 SW_LAN_TX3+ 41 42 DAT_DDC2_CRT
16 <30> SW_LAN_TX3+ 41 42 CLK_DDC2_CRT DAT_DDC2_CRT <23>
17 17 43 43 44 44 CLK_DDC2_CRT <23>
18 USBP9_R_D+ 45 46
C 18 USBP9_R_D- <30> LAN_ACTLED_YEL# 45 46 C
19 19 <30> LED_100_ORG# 47 47 48 48 +5V_RUN
20 20 <30> LED_10_GRN# 49 49 50 50 +3.3V_LAN
GND 21
GND 22
51 G1 G2 52
CONN@
ACES_51522-0200N-P01 E&T_1000K-F50E-04R
CONN@
Link CIS
Link CIS
2 1
0_0402_5%~D R1657 @
L107 +3.3V_LAN +5V_RUN +3.3V_ALW_PCH +5V_ALW

USBP9_R_D- 3 4
+5V_ALW 3 4 USBP9- <17>
0.1U_0402_10V7K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_16V4Z~D
1 1 1
0.1U_0402_16V4Z~D
C482
C1001
C998
USBP9_R_D+ 2 1 1
2 1 USBP9+ <17>
C1185
1
C1186
OCF2012181YZF_4P
2 2 2
2
2 1
2 0_0402_5%~D R1656 @
Place close to JIO1.20,22 Place close to JIO1.14,16 Place close to JIO1.14,16 Place close to JIO1.6,8,10,12
Close to JAUD1.
Q44
B SSM3K7002FU_SC70-3~D B
1 3 PCH_AZ_MDC_RST1#
S
<14> PCH_AZ_MDC_RST#
+5V_ALW
100K_0402_5%~D
G
2
1
10K_0402_5%~D
1
R751
R752
2
2
<39> MDC_RST_DIS#
Sniffer Switch SF1

1
1
<39> WIRELESS_ON#/OFF 2
2
3
3
SC12P-C-V-TR_3P
Defult on,
A A
WIRELESS_ON/OFF#:
LOW: ON
HIGH: OFF DELL CONFIDENTIAL/PROPRIETARY
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT IO/AUDIO/MEDIA/SNF
5 4 3 2 1
5 4 3 2 1
JDOCK1
DOCK_DET_1 1 2 DOCK_AC_OFF
1 2 DOCK_AC_OFF <39,53>
3 3 4 4
<30> DOCK_LOM_SPD10LED_GRN# DPD_CA_DET DPC_CA_DET DOCK_LOM_SPD100LED_ORG# <30>
5 5 6 6
<26> DPD_CA_DET DPC_CA_DET <26>
7 7 8 8
C690 2 1 0.1U_0402_10V7K~D DPD_DOCK_LANE_P0 9 10 DPC_DOCK_LANE_P0 C691 2 1 0.1U_0402_10V7K~D
<16> DPD_PCH_LANE_P0 DPD_DOCK_LANE_N0 9 10 DPC_DOCK_LANE_N0 DPC_PCH_LANE_P0 <16>
C679 2 1 0.1U_0402_10V7K~D 11 12 C680 2 1 0.1U_0402_10V7K~D
<16> DPD_PCH_LANE_N0 11 12 DPC_PCH_LANE_N0 <16>
13 14
C681 DPD_DOCK_LANE_P1 13 14 DPC_DOCK_LANE_P1
<16> DPD_PCH_LANE_P1 2 1 0.1U_0402_10V7K~D 15 16 C682 2 1 0.1U_0402_10V7K~D
C683 DPD_DOCK_LANE_N1 15 16 DPC_DOCK_LANE_N1 DPC_PCH_LANE_P1 <16>
<16> DPD_PCH_LANE_N1 2 1 0.1U_0402_10V7K~D 17
17 18
18 C684 2 1 0.1U_0402_10V7K~D
D DPC_PCH_LANE_N1 <16> D
19 20
<16> DPD_PCH_LANE_P2 2 1 0.1U_0402_10V7K~D 21
21 22
22 C693 2 1 0.1U_0402_10V7K~D
C685 DPD_DOCK_LANE_N2 DPC_DOCK_LANE_N2 DPC_PCH_LANE_P2 <16>
23 24
24 C686 2 1 0.1U_0402_10V7K~D
DPC_PCH_LANE_N2 <16>
25 26
<16> DPD_PCH_LANE_P3 2 1 0.1U_0402_10V7K~D 27 28 C688 2 1 0.1U_0402_10V7K~D
C689 DPD_DOCK_LANE_N3 27 28 DPC_DOCK_LANE_N3 DPC_PCH_LANE_P3 <16>
29 30
30 C694 2 1 0.1U_0402_10V7K~D DPC_PCH_LANE_N3 <16>
31 32
DPD_DOCK_AUX 31 32 DPC_DOCK_AUX
<26> DPD_DOCK_AUX 33 34 DPC_DOCK_AUX <26>
DPD_DOCK_AUX# 33 34 DPC_DOCK_AUX#
<26> DPD_DOCK_AUX# 35 36 DPC_DOCK_AUX# <26>
35 36
37 38
DPD_PCH_DOCK_HPD 37 38 DPC_PCH_DOCK_HPD
<16> DPD_PCH_DOCK_HPD 39 40 DPC_PCH_DOCK_HPD <16>
39 40
0.033U_0402_16V7K~D
+NBDOCK_DC_IN_SS 41 41 42 42 ACAV_DOCK_SRC# <53>
0.033U_0402_16V7K~D
1 43 43 44 44
BLUE_DOCK 45 46 1
<23> BLUE_DOCK 45 46 DAT_DDC2_DOCK <23>
C695
47 47 48 48 CLK_DDC2_DOCK <23>
C696
49 49 50 50
2 51 52
RED_DOCK 51 52 SATA_PRX_DKTX_P5 C697 2 2
<23> RED_DOCK 53 54 1 0.01U_0402_16V7K~D SATA_PRX_DKTX_P5_C <14>
53 54 SATA_PRX_DKTX_N5 C698 2
Close to DOCK 55 55 56 56 1 0.01U_0402_16V7K~D SATA_PRX_DKTX_N5_C <14> Close to DOCK
57 57 58 58
Its for Enhance ESD on dock issue. <23> GREEN_DOCK
GREEN_DOCK 59 59 60 60 SATA_PTX_DKRX_P5 C699 1 2 0.01U_0402_16V7K~D SATA_PTX_DKRX_P5_C <14>
Its for Enhance ESD on dock issue.
61 62 SATA_PTX_DKRX_N5 C700 1 2 0.01U_0402_16V7K~D
61 62 SATA_PTX_DKRX_N5_C <14>
63 63 64 64
65 66 USBP7_D+ 2 1
<23> HSYNC_DOCK 65 66 USBP7_D- 2 1 USBP7+ <17>
<23> VSYNC_DOCK 67 67 68 68
69 69 70 70
DPD_PCH_DOCK_HPD 71 72 3 4
<40> CLK_MSE 71 72 USBP3+ <17> 3 4 USBP7- <17>
<40> DAT_MSE 73 73 74 74 USBP3- <17>
75 76 @ L108 OCF2012181YZF_4P
75 76
100K_0402_5%~D
<29> DAI_BCLK# 77 77 78 78 CLK_KBD <40>

1
79 80 R1672 2 1 0_0402_5%~D
<29> DAI_LRCK# 79 80 DAT_KBD <40>
R757
81 81 82 82
C R1673 C
<29> DAI_DI 83 83 84 84 USB3RN4 <17> 2 1 0_0402_5%~D
<29> DAI_DO# 85 85 86 86 USB3RP4 <17>
87 88
2
87 88
<29> DAI_12MHZ# 89 89 90 90 USB3TN4 <17>
91 92 DPC_PCH_DOCK_HPD
91 92 USB3TP4 <17>
93 93 94 94
100K_0402_5%~D
95 95 96 96
1
<39> D_LAD0 97 98
97 98 BREATH_LED# <39,43>
R758
<39> D_LAD1 99 100
99 100 DOCK_LOM_ACTLED_YEL# <30>
101 102
101 102
<39> D_LAD2 103 104
103 104 DOCK_LOM_TRD0+ <30>
<39> D_LAD3 105 106
2
105 106 DOCK_LOM_TRD0- <30>
107 108
107 108 +3.3V_ALW
<39> D_LFRAME# 109 110
109 110 DOCK_LOM_TRD1+ <30> +LOM_VCT
<39> D_CLKRUN# 111 112
111 112 DOCK_LOM_TRD1- <30>
113 114
113 114
1U_0402_6.3V6K~D
115 116 DOCK_DET# 1 2
<39> D_SERIRQ 115 116
117 118 +LOM_VCT 1 10K_0402_5%~D R755
<39> D_DLDRQ1# 117 118
@ C701
119 120
119 120
<17> CLK_PCI_DOCK 121 122 DOCK_LOM_TRD2+ <30>
121 122
123 124 DOCK_LOM_TRD2- <30>
123 124 2
125 126
125 126
<40> DOCK_SMB_CLK 127 128 DOCK_LOM_TRD3+ <30>
127 128
<40> DOCK_SMB_DAT 129 130 DOCK_LOM_TRD3- <30>
129 130
131 132
131 132
<39,44> DOCK_SMB_ALERT# 133 134 DOCK_DCIN_IS+ <52>
133 134
<44> DOCK_PSID 135 136 DOCK_DCIN_IS- <52>
135 136
137 138
137 138
<40> DOCK_PWR_BTN# 139 140 DOCK_POR_RST# <40>
139 140 D32
141 142
141 142 DOCK_DET_R#
<39,44,53> SLICE_BAT_PRES# 143 144 1 2 DOCK_DET# <39>
143 144
B RB751S40T1_SOD523-2~D B
145 149 +DOCK_PWR_BAR
GND1 PWR2
+DOCK_PWR_BAR 146 150
PWR1 PWR2
0.1U_0603_50V7K~D
147 151
PWR1 PWR2
0.1U_0603_50V7K~D
PESD24VS2UT_SOT23-3~D
148 152
PWR1 GND2
3
2
4.7U_0805_25V6K~D
C703
1 @ 1 153 159
Shield_G Shield_G
C702
154 160
Shield_G Shield_G
CE6
D33
155 161
Shield_G Shield_G 2
156 162
2 2 Shield_G Shield_G
157 163
1
Shield_G Shield_G
158 164
Shield_G Shield_G
JAE_WD2F144WB6-DT
CONN@
Link CIS
DAI_12MHZ# DAI_BCLK# CLK_PCI_DOCK
1 10_0402_1%~D
10_0402_1%~D
33_0402_5%~D
1
1
@ RE11
@ RE12
R756
2
2
4.7P_0402_50V8C~D
4.7P_0402_50V8C~D
12P_0402_50V8J~D
1 1 1
@ CE8
@ CE9
C704
A 2 2 2 A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DOCKING CONN
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
+3.3V_ALW
10U_0603_6.3V6M~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_10V7K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1 2 DYN_TURB_PWR_ALRT# 1 1 1 1 1 1 +3.3V_RUN
C705
C706
C707
C708
C709
C710
R796 10K_0402_5%~D
1 2 HW_GPS_DISABLE2#
R798 100K_0402_5%~D D_CLKRUN# 2 1
PROCHOT_GATE 2 2 2 2 2 2 R777 100K_0402_5%~D
1 2
R761 100K_0402_5%~D D_SERIRQ 2 1
1 2 CPU_DETECT# R780 100K_0402_5%~D
A17
B30
A43
A54
R763 100K_0402_5%~D D_DLDRQ1#
B5
2 1
1 2 SLICE_BAT_PRES# U46 R782 100K_0402_5%~D
R760 100K_0402_5%~D EXPRESS_DET# 2 1
VCC1
VCC1
VCC1
VCC1
VCC1
D 1 2 WWAN_RADIO_DIS# A23 R460 100K_0402_5%~D D
R774 100K_0402_5%~D CRT_SWITCH GPIOI0 SIO_SLP_A# SMART_DET#
<23> CRT_SWITCH B52 B63 SIO_SLP_A# <16,42,48> 2 1
USB_PWR_SHR_EN# MDC_RST_DIS# GPIOA0 GPIOI1 0.75V_DDR_VTT_ON R461 100K_0402_5%~D
1 2 <37> MDC_RST_DIS# A49 A60 0.75V_DDR_VTT_ON <46>
R776 100K_0402_5%~D MCARD_MISC_PWREN GPIOA1 GPIOI2/TACH0 SIO_SLP_S4# PCMCIA_DET#
<35> MCARD_MISC_PWREN B53 A61 SIO_SLP_S4# <16,42,46> 2 1
USB_SIDE_EN# PROCHOT_GATE GPIOA2 GPIOI3 SIO_SLP_S3# R463 100K_0402_5%~D
1 2 <52> PROCHOT_GATE A50 B65 SIO_SLP_S3# <11,16,27,35,42,47,48,49>
R768 10K_0402_5%~D LID_CL_SIO# GPIOA3 GPIOI4 IMVP_PWRGD MCARD_PCIE_SATA#
B54 A62 IMVP_PWRGD <51> 2 1
ESATA_USB_PWR_EN# DOCK_SMB_ALERT# GPIOA4 GPIOI5 R457 100K_0402_5%~D
1 2 <38,44> DOCK_SMB_ALERT# A51 B66 1 2 IMVP_VR_ON <51>
R769 100K_0402_5%~D GPIOA5 GPIOI6 @R765
@ R765 0_0402_5%~D SP_TPM_LPC_EN
B55 A63 DOCK_AC_OFF_EC <53> 2 1
USB_PWR_SHR_VBUS_EN GPIOA6 GPIOI7 @R772
@ R772 10K_0402_5%~D
1 2 A52
R778 100K_0402_5%~D GPIOA7 WIRELESS_ON#/OFF
B67 AUX_EN_WOWL <35> 2 1
DOCK_SMB_ALERT# USB_SIDE_EN# GPIOJ0 @R766
@ R766 100K_0402_5%~D
1 2 <37> USB_SIDE_EN# A33
GPIOB0 GPIOJ1/TACH1
A64 ---vPro
WLAN_LAN_DISB# <30> only
R762 10K_0402_5%~D EN_I2S_NB_CODEC# B36 A5 SIO_SLP_LAN#
<29> EN_I2S_NB_CODEC# GPIOB1 GPIOJ2/TACH2 SIO_SLP_LAN# <16,30>
1 2 SIO_FAN1_DET# A34 B6 SIO_SLP_SUS#
GPOC2 GPIOJ3 SIO_SLP_SUS# <16>
R1183 10K_0402_5%~D <53> EN_DOCK_PWR_BAR EN_DOCK_PWR_BAR B37 A6
ZODD_WAKE# PANEL_BKEN_EC GPOC3 GPIOJ4 MODC_EN GPIO_PSID_SELECT <44>
1 2 <24> PANEL_BKEN_EC A35 B7 MODC_EN <28>
R516 10K_0402_5%~D ENVDD_PCH GPOC4 GPIOJ5 DOCK_HP_DET
<16,24> ENVDD_PCH B38 GPOC5 GPIOJ6 A7 DOCK_HP_DET <29>
1 2 WIRELESS_ON#/OFF LCD_TST A36 B8 DOCK_MIC_DET
<24> LCD_TST GPOC6/TACH4 GPIOJ7 DOCK_MIC_DET <29>
R771 100K_0402_5%~D PSID_DISABLE# A37
<44> PSID_DISABLE# PBAT_PRES# GPIOC7 ME_FWP
<44> PBAT_PRES# B40 GPIOD0 GPIOK0 A8 ME_FWP <14>
DOCKED A38 B9 MASK_SATA_LED#
<30> DOCKED GPIOC1 GPIOK1/TACH3 MASK_SATA_LED# <43>
DOCK_DET# B41 B10
<38> DOCK_DET# GPIOC0 GPIOK2 1.8V_RUN_PWRGD <47>
AUD_NB_MUTE# A39 A10 LED_SATA_DIAG_OUT#
<29> AUD_NB_MUTE# GPIOB7 GPIOK3 LED_SATA_DIAG_OUT# <43>
MCARD_WWAN_PWREN B42 B11 TEMP_ALERT#_R 1 2
<35> MCARD_WWAN_PWREN GPIOB6 GPIOK4 TEMP_ALERT# <14,18>
LCD_VCC_TEST_EN A40 A11 RUN_ON @R738
@ R738 0_0402_5%~D
<24> LCD_VCC_TEST_EN GPIOB5 GPIOK5 RUN_ON <27,35,42,47,48>
CCD_OFF B43 B12
<24> CCD_OFF GPIOB4 GPIOK6
AUD_HP_NB_SENSE A41 A12
<29,37> AUD_HP_NB_SENSE GPIOB3 GPIOK7 SPI_WP#_SEL <14>
ESATA_USB_PWR_EN# B44
<36> ESATA_USB_PWR_EN# GPIOB2
B60 SUS_ON
GPIOL0/PWM7 SUS_ON <42>
GPIOL1/PWM8 A57
B32 B64 BAT1_LED# trace width 20 mils
GPIOD1 GPIOL2/PWM0 BAT1_LED# <43>
<53> SLICE_BAT_ON SLICE_BAT_ON A31 B68
SLICE_BAT_PRES# GPIOD2 GPIOL3/PWM1 BAT2_LED#
<38,44,53> SLICE_BAT_PRES# B33 GPIOD3 GPIOL4/PWM3 A9 BAT2_LED# <43> trace width 20 mils
EXPRESS_DET# B15 B1
<35> EXPRESS_DET# SMART_DET# GPIOD4 GPIOL5/PWM2 USH_PWR_ON
<35> SMART_DET# A15 GPIOD5 GPIOL6 A18 PAD~D T117 @
PCMCIA_DET# B16 A44
C GPIOD6 GPIOL7/PWM5 C
A16 GPIOD7
B34 HW_GPS_DISABLE2#
GPIOM1 HW_GPS_DISABLE2# <34>
B39 BREATH_LED#
GPIOM3/PWM4 BREATH_LED# <38,43>
A1 GPIOE0/RXD GPIOM4/PWM6 B51
USB_PWR_SHR_EN# B2
GFX_MEM_VTT_ON GPIOE1/TXD
A2 GPIOE2/RTS#
MCARD_PCIE_SATA# B3 A27 LPC_LAD0
GPIOE3/DSR# LAD0 LPC_LAD0 <14,32,34,40>
CPU_DETECT# A3 A26 LPC_LAD1
<7> CPU_DETECT# GPIOE4/CTS# LAD1 LPC_LAD1 <14,32,34,40>
DGPU_PWR_EN B45 B26 LPC_LAD2
GPIOE5/DTR# LAD2 LPC_LAD2 <14,32,34,40>
@ R801 1 2 0_0402_5%~D SIO_FAN1_DET# A42 B25 LPC_LAD3
<22> FAN1_DET# GPIOE6/RI# LAD3 LPC_LAD3 <14,32,34,40>
@ T116 PAD~D DP_HDMI_HPD B4 A21 LPC_LFRAME#
GPIOE7/DCD# LFRAME# LPC_LFRAME# <14,32,34,40>
B22 PCH_PLTRST#_EC
LRESET# PCH_PLTRST#_EC <17,32,34,35,40>
A28 CLK_PCI_5048 RUN_ON 2 1
PCICLK CLK_PCI_5048 <17>
ZODD_WAKE# A59 B20 CLKRUN# R786 100K_0402_5%~D
GPIOF0 CLKRUN# CLKRUN# <16,32,40>
LOM_SMB_ALERT# B62 CPU_VTT_ON 2 1
<30> LOM_SMB_ALERT# GPIOF1
SUSACK# A58 A22 LPC_LDRQ1# R789 100K_0402_5%~D
<16> SUSACK# GPIOF2 LDRQ1# LPC_LDRQ1# <14>
LOM_ENERGY_DET B61 B21 IRQ_SERIRQ 0.75V_DDR_VTT_ON 2 1
<30> LOM_ENERGY_DET GPIOF3/TACH8 SER_IRQ IRQ_SERIRQ <14,32,40>
@ T110 PAD~D DGPU_PWROK A56 A32 CLK_SIO_14M R790 100K_0402_5%~D
GPIOF4/TACH7 14.318MHZ/GPIOM0 CLK_SIO_14M <15>
VGA_ID B59 B35 EC_32KHZ_ECE5048 <40> SLICE_BAT_ON 2 1
3.3V_RUN_GFX_ON GPIOF5 CLK32/GPIOM2 R791 100K_0402_5%~D
@ T109 PAD~D A55
SLP_ME_CSW_DEV# GPIOF6 SUS_ON
<14,18> SLP_ME_CSW_DEV# B58 2 1
GPIOF7 D_LAD0 R878 100K_0402_5%~D
B29 D_LAD0 <38>
DLAD0 D_LAD1 LCD_TST
B28 D_LAD1 <38> 2 1
LOM_LOW_PWR DLAD1 D_LAD2 R767 100K_0402_5%~D
<30> LOM_LOW_PWR B47 A25 D_LAD2 <38>
CHARGE_EN GPIOG0/TACH5 DLAD2 D_LAD3 SYS_LED_MASK#
A45 A24 D_LAD3 <38> 2 1
SYS_LED_MASK# GPIOG1 DLAD3 D_LFRAME# R775 10K_0402_5%~D
<43> SYS_LED_MASK# B48 B23 D_LFRAME# <38>
DYN_TURB_PWR_ALRT# GPIOG2 DLFRAME# D_CLKRUN# DGPU_PWR_EN
A46 A19 D_CLKRUN# <38> 2 1
GPIOG3 DCLKRUN# D_DLDRQ1# R1582 100K_0402_5%~D
<18> SIO_EXT_WAKE# 1 2 B49 B24 D_DLDRQ1# <38>
@ R797 0_0402_5%~D GPIOG4 DLDRQ1# D_SERIRQ GFX_MEM_VTT_ON
<34,43> WIRELESS_LED# A47 A20 D_SERIRQ <38> 2 1
GPIOG5 DSER_IRQ R1583 100K_0402_5%~D
B4 non used USB_PWR_SHR_VBUS_EN B50
GPIOG6
WLAN_RADIO_DIS# A48 CHARGE_EN 2 1
<34> WLAN_RADIO_DIS# GPIOG7/TACH6
A29 BC_INT#_ECE5048 R3 100K_0402_5%~D
BC_INT# BC_INT#_ECE5048 <40>
B31 BC_DAT_ECE5048
BC_DAT BC_DAT_ECE5048 <40>
WIRELESS_ON#/OFF B13 A30 BC_CLK_ECE5048
<37> WIRELESS_ON#/OFF GPIOH0 BC_CLK BC_CLK_ECE5048 <40>
B BT_RADIO_DIS# A13 B
<41> BT_RADIO_DIS# GPIOH1
WWAN_RADIO_DIS# A53
<34> WWAN_RADIO_DIS# SYSOPT1/GPIOH2
SYS_PWROK B57 A4 RUNPWROK
<7,16> SYS_PWROK SYSOPT0/GPIOH3 PWRGD RUNPWROK <7,40>
@ T114 PAD~D DGPU_SELECT# B14
GPIOH4 SP_TPM_LPC_EN
A14 B56 SP_TPM_LPC_EN <32>
CPU_VTT_ON GPIOH5 OUT65
<49> CPU_VTT_ON B17
GPIOH6
<16> PCH_DPWROK 1 2 B18
@ R802 0_0402_5%~D GPIOH7 +3.3V_ALW
B19 1 2
TEST_PIN R804 1K_0402_1%~D @C711
@ C711
B46 +CAP_LDO 0.1U_0402_25V6K~D
CAP_LDO
4.7U_0603_6.3V6K~D
1 1 2
B27
VSS
5
+3.3V_ALW C1
EP
C714
ACAV_IN_NB 1 D34 @
P
2 <40,52,53> ACAV_IN_NB B
DB Version 0.4 4 2 1
O DOCK_AC_OFF <38,53>
100K_0402_5%~D
ECE5048-LZY_DQFN132_11X11~D DOCK_AC_OFF_EC 2
A
1
33K_0402_5%~D
RB751S40T1_SOD523-2~D
1
R800
@ U47
@U47
@R770
@
TC7SH08FU_SSOP5~D
R770
+CAP_LDO trace width 20 mils
2
+3.3V_ALW
2
100K_0402_5%~D
VGA_ID
1
CLK_PCI_5048 CLK_SIO_14M
R805
ME_FWP PCH has internal 20K PD.

100K_0402_5%~D
10_0402_1%~D
Reserve for ESD in 6/22

1
(suspend power rail)

10_0402_1%~D
Place closed U46

@R803
@
@R795
@
@R794
@
2
R803
R795
R794
ME_FWP PCH_PLTRST#_EC
0.1U_0402_25V6K~D
LID_CL_SIO# 2 1 LID_CL# <43>
2
R807 10_0402_1%~D
1K_0402_1%~D
4.7P_0402_50V8C~D
0.047U_0402_16V4Z~D
1
1
@R793
@
4.7P_0402_50V8C~D
@CE11
@
A A
R793
CE11
1 1 1
@C713
@
@C712
@
2
C713
C712
C716
VGA_ID0
2
2 2 2
Discrete 0
UMA 1 DELL CONFIDENTIAL/PROPRIETARY
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT ECE5048
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW +RTC_CELL
100K_0402_5%~D
C720
1 2
1
+3.3V_ALW
R810
0.1U_0402_25V6K~D +RTC_CELL @ C721
5
1 2
1 1 2 +RTC_CELL_VBAT
P
<49,50> 1.05V_VTTPWRGD B
4 @ R815 0_0402_5%~D 1U_0402_6.3V6K~D
1.05V_0.8V_PWROK <14,51>
2
O
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
10U_0603_6.3V6M~D
<50> VCCSAPWROK 2 1 1 1 1 1 1 1 1 1
G
A U50 1 <22> POWER_SW_IN# 1 2 POWER_SW#_MB <43>
C725
C727
C729
C731
C726
C728
C739
C732
C730
TC7SH08FU_SSOP5~D R811 10K_0402_5%~D
C723
1U_0402_6.3V6K~D
2 2 2 2 2 2 2 2 2
1
2
C722
+3.3V_ALW 2
B64
A11
A22
B35
A41
A58
A52
A26
B3
D 1 2 PCIE_WAKE# U51 D
R759 10K_0402_5%~D
VBAT
VTR[1]
VTR[2]
VTR[3]
VTR[4]
VTR[5]
VTR[6]
VTR[7]
VTR[8]
2 1 BC_DAT_EMC4022
R821 100K_0402_5%~D +RTC_CELL
1 2 BC_DAT_ECE5048
100K_0402_5%~D
R814 100K_0402_5%~D PS/2 INTERFACE MISC INTERFACE
1
1 2 BC_DAT_ECE1117 SML1_SMBDATA A5 A10 SYSTEM_ID
<15,30> SML1_SMBDATA GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA GPIO021/RC_ID1
R819
R817 100K_0402_5%~D SML1_SMBCLK B6 B10 BOARD_ID @ C733
<15,30> SML1_SMBCLK GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK GPIO020/RC_ID2
1 2 PBAT_SMBDAT CLK_TP_SIO A37 B14 DDR_ON 1 2
<41> CLK_TP_SIO GPIO110/PS2_CLK2/GPTP-IN6 GPIO025/UART_CLK DDR_ON <46>
R818 2.2K_0402_5%~D DAT_TP_SIO B40 B44 HOST_DEBUG_TX
<41> DAT_TP_SIO GPIO111/PS2_DAT2/GPTP-OUT6 GPIO120/UART_TX HOST_DEBUG_TX <34>
1 2 PBAT_SMBCLK CLK_KBD A38 B46 HOST_DEBUG_RX 1U_0402_6.3V6K~D
<38> CLK_KBD HOST_DEBUG_RX <34>
2
R820 2.2K_0402_5%~D DAT_KBD GPIO112/PS2_CLK1A GPIO124/GPTP-OUT5/UART_RX RUNPWROK
<38> DAT_KBD B41 B26
LPC_LDRQ#_MEC CLK_MSE GPIO113/PS2_DAT1A VCC_PRWGD EN_INVPWR RUNPWROK <7,39>
1 2 <38> CLK_MSE A39 A25 <22> DOCK_PWR_SW# 1 2 DOCK_PWR_BTN# <38>
@ R823 100K_0402_5%~D DAT_MSE GPIO114/PS2_CLK0A GPIO060/KBRST EN_INVPWR <24> R825 10K_0402_5%~D
<38> DAT_MSE B42 B36 PCH_SATA_MOD_EN# <14>
CHARGER_SMBDAT PBAT_SMBDAT GPIO115/PS2_DAT0A GPIO101/ECGP_SCLK
1 2 <44> PBAT_SMBDAT B59 B37
GPIO154/I2C1C_DATA/PS2_CLK1B GPIO103/ECGP_MISO
1U_0402_6.3V6K~D
R827 2.2K_0402_5%~D PBAT_SMBCLK A56 B38 1
<44> PBAT_SMBCLK GPIO155/I2C1C_CLK/PS2_DAT1B GPIO105/ECGP_MOSI
1 2 CHARGER_SMBCLK A34 DDR_HVREF_RST_GATE
GPIO102/HSPI_SCLK DDR_HVREF_RST_GATE <7>
C734
R828 2.2K_0402_5%~D A35 DYN_TUR_CURRNT_SET#
SIO_LAN_SMBDATA GPIO104/HSPI_MISO CPU1.5V_S3_GATE DYN_TUR_CURRNT_SET# <52>
1 2 A36 CPU1.5V_S3_GATE <11>
R830 2.2K_0402_5%~D GPIO106/HSPI_MOSI MSDATA 2
JTAG INTERFACE GPIO116/MSDATA
A40 MSDATA <34>
1 2 SIO_LAN_SMBCLK JTAG_TDI A51 B43 MSCLK
GPIO145/I2C1K_DATA/JTAG_TDI GPIO117/MSCLK MSCLK <34>
R831 2.2K_0402_5%~D JTAG_TDO B55 A45 SIO_A20GATE
GPIO146/I2C1K_CLK/JTAG_TDO GPIO127/A20M SIO_A20GATE <18>
1 2 GPU_SMBDAT JTAG_CLK B56 A55 PS_ID
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK GPIO153/LED3 PS_ID <44>
R829 2.2K_0402_5%~D JTAG_TMS A53 A57
GPU_SMBCLK JTAG_RST# GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS GPIO156/LED1
1 2 B57 B61
R822 2.2K_0402_5%~D JTAG_RST# GPIO157/LED2 FWP#
B65
LCD_SMBCLK nFWP PROCHOT#_EC +3.3V_ALW_PCH
1 2 A46
R418 2.2K_0402_5%~D PROCHOT#/PWM4
1 2 LCD_SMBDAT FAN PWM & TACH
R420 2.2K_0402_5%~D B22 GENERAL PURPOSE I/O AC_PRESENT 2 1
<38> DOCK_POR_RST# GPIO050/FAN_TACH1
1 2 DOCK_SMB_DAT A21 B2 R884 1 2 1K_0402_1%~D R835 10K_0402_5%~D
GPIO051/FAN_TACH2 GPIO001/ECSPI_CS1 VOL_MUTE <43>
R838 2.2K_0402_5%~D AUX_ON B23 A2
<30> AUX_ON GPIO052/FAN_TACH3 GPIO002/ECSPI_CS2
1 2 DOCK_SMB_CLK B24 B8 R886 1 2 1K_0402_1%~D +5V_RUN
GPIO053/PWM0 GPIO014/GPTP-IN7/HSPI_CS1 VOL_UP <43>
R841 2.2K_0402_5%~D PCH_ALW_ON A23 B18 R887 1 2 1K_0402_1%~D
<42,44> PCH_ALW_ON GPIO054/PWM1 GPIO040/GPTP-OUT3/HSPI_CS2 VOL_DOWN <43>
1 2 BAY_SMBDAT <24> BIA_PWM_EC BIA_PWM_EC B25 A8 CLK_KBD 2 1
GPIO055/PWM2 GPIO015/GPTP-OUT7 ME_SUS_PWR_ACK <16>
R854 2.2K_0402_5%~D A24 B9 1.5V_SUS_PWRGD R845 4.7K_0402_5%~D
GPIO056/PWM3 GPIO016/GPTP-IN8 1.5V_SUS_PWRGD <46>
1 2 BAY_SMBCLK A9 DAT_KBD 2 1
GPIO017/GPTP-OUT8 PM_APWROK <16>
R856 2.2K_0402_5%~D A14 1.05V_A_PWRGD_SIO 1 2 R846 4.7K_0402_5%~D
GPIO026/GPTP-IN1 1.05V_A_PWRGD <48>
1 2 DYN_TUR_CURRNT_SET# BC-LINK B15 @ R857 0_0402_5%~D CLK_MSE 2 1
GPIO027/GPTP-OUT1 ALW_PWRGD_3V_5V <45>
R1171 100K_0402_5%~D BC_CLK_ECE5048 A43 A17 DEVICE_DET# R851 4.7K_0402_5%~D
<39> BC_CLK_ECE5048 GPIO123/BCM_A_CLK GPIO041 DEVICE_DET# <28>
1 2 1.05V_A_PWRGD_SIO BC_DAT_ECE5048 B45 B39 RESET_OUT# DAT_MSE 2 1
<39> BC_DAT_ECE5048 GPIO122/BCM_A_DAT GPIO107/nRESET_OUT RESET_OUT# <16>
@ R888 100K_0402_5%~D BC_INT#_ECE5048 A42 A44 R852 4.7K_0402_5%~D
C <39> BC_INT#_ECE5048 GPIO121/BCM_A_INT# GPIO125/GPTP-IN5 C
BC_CLK_EMC4022 A12 B47 PCH_RSMRST#
<22> BC_CLK_EMC4022 GPIO022/BCM_B_CLK GPIO126 PCH_RSMRST# <41> +3.3V_RUN
<22> BC_DAT_EMC4022 BC_DAT_EMC4022 B13 A54 AC_PRESENT
GPIO023/BCM_B_DAT GPIO151/GPTP-IN4 AC_PRESENT <16>
1 2 MSDATA BC_INT#_EMC4022 A13 B58 SIO_PWRBTN#
<22> BC_INT#_EMC4022 GPIO024/BCM_B_INT# GPIO152/GPTP-OUT4 SIO_PWRBTN# <16>
R869 10K_0402_5%~D B20 VOL_MUTE 2 1
DDR_ON PCH_PCIE_WAKE# GPIO044/BCM_C_CLK @ R1169 100K_0402_5%~D
1 2 A18
R876 100K_0402_5%~D <16> PCH_PCIE_WAKE# PCIE_WAKE# GPIO043/BCM_C_DAT VOL_DOWN
<30,34,35> PCIE_WAKE# B19
GPIO042/BCM_C_INT#
SMBUS INTERFACE 2 1
1 2 PCH_ALW_ON BC_CLK_ECE1117 A20 A3 DOCK_SMB_DAT @ R1197 100K_0402_5%~D
<41> BC_CLK_ECE1117 GPIO047/LSBCM_D_CLK GPIO003/I2C1A_DATA DOCK_SMB_DAT <38>
R880 100K_0402_5%~D <41> BC_DAT_ECE1117 BC_DAT_ECE1117 B21 B4 DOCK_SMB_CLK VOL_UP 2 1
GPIO046/LSBCM_D_DAT GPIO004/I2C1A_CLK DOCK_SMB_CLK <38>
1 2 DOCK_POR_RST# BC_INT#_ECE1117 A19 A4 LCD_SMBDAT @ R1118 100K_0402_5%~D
<41> BC_INT#_ECE1117 GPIO045/LSBCM_D_INT# GPIO005/I2C1B_DATA
R881 100K_0402_5%~D BEEP A16 B5 LCD_SMBCLK +RTC_CELL
<29> BEEP GPIO032/GPTP-IN3/BCM_E_CLK GPIO006/I2C1B_CLK
1 2 EN_INVPWR SIO_SLP_S5# B16 B7 BAY_SMBDAT
<16,42> SIO_SLP_S5# GPIO31/GPTP-OUT2/BCM_E_DAT GPIO012/I2C1H_DATA/I2C2D_DATA
R882 100K_0402_5%~D ACAV_IN_NB A15 A7 BAY_SMBCLK
<39,52,53> ACAV_IN_NB GPIO30/GPTP-IN2/BCM_E_INT# GPIO013/I2C1H_CLK/I2C2D_CLK
1 2 1.05V_0.8V_PWROK B48 GPU_SMBDAT VCI_IN1# 2 1
R883 10K_0402_5%~D GPIO130/I2C2A_DATA GPU_SMBCLK R1156 100K_0402_5%~D
B49
RESET_OUT# GPIO131/I2C2A_CLK CHARGER_SMBDAT LAT_ON_SW#
1 2 HOST INTERFACE GPIO132/I2C1G_DATA
A47 CHARGER_SMBDAT <52> 2 1
@ R843 8.2K_0402_5%~D SIO_EXT_SMI# A6 B50 CHARGER_SMBCLK R870 100K_0402_5%~D
<14,17> SIO_EXT_SMI# GPIO011/nSMI GPIO140/I2C1G_CLK CHARGER_SMBCLK <52>
1 2 CPU1.5V_S3_GATE SIO_RCIN# A27 B52 CARD_SMBDAT
<18> SIO_RCIN# GPIO061/LPCPD# GPIO141/I2C1F_DATA/I2C2B_DATA CARD_SMBDAT <35>
R889 100K_0402_5%~D LPC_LDRQ#_MEC B29 A49 CARD_SMBCLK
LDRQ# GPIO142/I2C1F_CLK/I2C2B_CLK CARD_SMBCLK <35>
1 2 PCH_RSMRST# IRQ_SERIRQ A28 B53 SIO_LAN_SMBDATA
<14,32,39> IRQ_SERIRQ SER_IRQ GPIO143/I2C1E_DATA SIO_LAN_SMBDATA <15,30>
R892 10K_0402_5%~D PCH_PLTRST#_EC B30 A50 SIO_LAN_SMBCLK
<17,32,34,35,39> PCH_PLTRST#_EC LRESET# GPIO144/I2C1E_CLK SIO_LAN_SMBCLK <15,30>
1 2 AUX_ON CLK_PCI_MEC A29
<17> CLK_PCI_MEC PCI_CLK
R874 2.7K_0402_5%~D LPC_LFRAME# B31
<14,32,34,39> LPC_LFRAME# LFRAME#
LPC_LAD0 A30 DELL PWR SW INF
<14,32,34,39> LPC_LAD0 LAD0
LPC_LAD1 B32 A59
<14,32,34,39> LPC_LAD1 LAD1 BGPO0
LPC_LAD2 A31 B63 LAT_ON_SW#
<14,32,34,39> LPC_LAD2 LAD2 VCI_IN2#
LPC_LAD3 B33 A60 ALWON
<14,32,34,39> LPC_LAD3 LAD3 VCI_OUT ALWON <45>
CLKRUN# A32 A63 VCI_IN1#
<16,32,39> CLKRUN# CLKRUN# VCI_IN1#
SIO_EXT_SCI# A33 B67 POWER_SW_IN#
<18> SIO_EXT_SCI# GPIO100/nEC_SCI VCI_IN0#
B1 ACAV_IN
VCI_OVRD_IN ACAV_IN <22,52,53> +1.05V_RUN_VTT
A1 DOCK_PWR_SW#
VCI_IN3#
MASTER CLOCK
MEC_XTAL1 A61 PECI B51 +PECI_VREF 1 2
MEC_XTAL2 2 MEC_XTAL2_R XTAL1 PECI_VREF PECI_EC_R @ R862 0_0402_5%~D
1 A62 A48 1 2 PECI_EC <7>
XTAL2 PECI
0.1U_0402_25V6K~D
@ R1068 1 2 0_0402_5%~D B62 DB Version 0.12 R863 43_0402_5%~D R862 close to
<39> EC_32KHZ_ECE5048 GPIO160/32KHZ_OUT
@ R867 0_0402_5%~D I2S B17 1
I2S_DAT
B27 R1659 1 2 100K_0402_5%~D U51& least 250mils
VSS_RO
VR_CAP
I2S_CLK
C737
B34 B28 R1658 1 2 100K_0402_5%~D
VSS[1]
VSS[4]
AGND
NC1 I2S_WS
A64
NC2 2
EP
B68
+3.3V_ALW NC3
JTAG_RST# citcuit MEC5055-LZY_DQFN132_11X11~D
B66
B11
B60
+VR_CAP B12
B54
C1
close to U51.B57
10K_0402_5%~D
1
B B
15mil
R824
32 KHz Clock 15mil +3.3V_RUN

+3.3V_M
+3.3V_ALW
2
1
4.7U_0603_6.3V6K~D
100K_0402_5%~D
10K_0402_5%~D
MEC_XTAL1
10K_0402_5%~D
JTAG_RST# 1
R799
MEC_XTAL2
0.1U_0402_25V6K~D
C740
R893
C740 close to U51.B12
1
1
100_0402_1%~D
R872
1
2
2
@
1 2
1
2
JTAG1 CONN@
@SHORT PADS~D
C735
R836
Y6 @ R1180 0_0402_5%~D
2
32.768KHZ_12.5PF_Q13FC1350000~D RUNPWROK
2
39P_0402_50V8J~D
1 2 <22> PCH_PWRGD#
2
H_PROCHOT# <7,51,52>
39P_0402_50V8J~D
FWP#
1 1
1
D D D
C743
C741
2 10K_0402_5%~D
+1.05V_RUN_VTT
2
Q50
@ Q47
RESET_OUT# 2 2 PROCHOT#_EC 2
<42> RUN_ON_ENABLE#
@ R879
Q45
G G G
2
2 2 S S S
1
10K_0402_5%~D
@ R1179
1
+3.3V_ALW
2
PROCHOT#_EC
+3.3V_ALW
130K_0402_5%~D
240K_0402_5%~D
100K_0402_5%~D
1
2
R875 C744 REV
33K_0402_5%~D
@ R877
@ R812
Place closely pin A29
1
R871
+3.3V_ALW 240K 4700p X00

R875
CLK_PCI_MEC
DOCK_POR_RST# PCH_PLTRST#_EC
130K 4700p X01
2
1
1
10_0402_1%~D 4.7P_0402_50V8C~D
@ R885
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
SYSTEM_ID
* 62K 4700p X02
2
10K_0402_5%~D
49.9_0402_1%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
1 1
1
+3.3V_ALW
4700P_0402_25V7K~D
@ CE12
33K 4700p A00
R864
R858
R859
R860
C736
2
R861
4700P_0402_25V7K~D
BOARD_ID
8.2K 4700p 1
2 2
@
1
1
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
100K_0402_5%~D
@ R850
C742
A A
4.3K 4700p 1
2
R847
R848
R849
C744
JDEG2 1
1 2
1 2K 4700p
@ C747
2 JTAG_TDI
2 JTAG_TMS 2
3
1K 4700p
2
3 JTAG_CLK 2
4 Reserve for ESD in 6/22 Place closed U51
4 JTAG_TDO
5
5 MSCLK
11 6
G1 6 MSDATA
12 7
G2 7
8
8 HOST_DEB_TX
HOST_DEB_RX
@ R853 1
@ R855 1
2 0_0402_5%~D HOST_DEBUG_TX
HOST_DEBUG_RX BOARD_ID rise time is measured from 5%~68%. SYSTEM_ID for BID function DELL CONFIDENTIAL/PROPRIETARY
9 2 0_0402_5%~D
9 Pop R877 240K for vPro and depop R871
10
10 Compal Electronics, Inc.
TYCO_1-2041070-0~D
* Pop R871 130K for non-vPro and depoip R877 Title
CONN@ PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT MEC5055
5 4 3 2 1
5 4 3 2 1
Touch Pad BlueTooth +3.3V_RUN
+3.3V_TP
0.1U_0402_16V4Z~D
1
+3.3V_RUN
4.7K_0402_5%~D
4.7K_0402_5%~D
C748
1
1
R903
R902
JTP1 1 2 BT_COEX_STATUS2
D
8 R1133 1K_0402_1%~D 2 D
TP_CLK 8
7
7 G2
10 1 2 BT_PRI_STATUS
TP_DATA 6 9 R1134 1K_0402_1%~D JBT1
2
6 G1
5 1
L54 2 TP_DATA 5 1
<40> DAT_TP_SIO 1 BLM18AG601SN1D_0603~D +3.3V_TP 4 2
PS2_DAT_TS 4 <17> BT_DET# 2
3 <34> COEX1_BT_ACTIVE 3
L55 2 TP_CLK PS2_CLK_TS 3 BT_COEX_STATUS2 3
<40> CLK_TP_SIO 1 BLM18AG601SN1D_0603~D 2 4
2 BT_PRI_STATUS 4
1 5
10P_0402_50V8J~D 1 5
10P_0402_50V8J~D
10P_0402_50V8J~D
6
<43> BT_ACTIVE 6
10P_0402_50V8J~D
1 1 1 1 ACES_51522-00801-001 7
<39> BT_RADIO_DIS# 7
2
C752
C750
C749
CONN@ 8
<34> COEX2_WLAN_ACTIVE 8
C751
9
Link CIS 10
9
2 2 2 2 10
D37
<17> USBP11- 11 11
<17> USBP11+ 12 12
+3.3V_TP 13 G1
14 G2
0.1U_0402_16V4Z~D
ACES_50224-0120N-001
1
1 CONN@
100P_0402_50V8J~D
Link CIS
C755
33P_0402_50V8J~D
1 10K_0402_5%~D
@ C754
2 1 1
C753
R904
+3.3V_ALW +3.3V_RUN +3.3V_TP
1 2 2 2
2
R1161 0_0603_5%~D
1 2
Place close to JTP1
@R1162
@ R1162 0_0603_5%~D
C C
RSMRST circuit
1 2
@R1623
@ R1623 0_0402_5%~D
+3.3V_ALW_PCH
+5V_ALW_PCH +3.3V_ALW
100K_0402_5%~D
C288
1
2
33_0402_5%~D
1 2
R1629
R1622
0.1U_0402_25V6K~D
5
U4
2
1
1
P
<40> PCH_RSMRST# B
+5V_ALW_PCH_U4 1 4 1 2
VCC O PCH_RSMRST#_Q <14,16>
0.01U_0402_16V7K~D
3 RSMRST# 2 R1655 0_0402_5%~D

RESET# A
G
2 U7
GND TC7SH08FU_SSOP5~D
1
3
C289
RT9818A-44GU3_SC70-3~D
2
B B
Keyboard
JKB1
1
1 PS2_CLK_TS KB_DET# <18>
2
2 PS2_DAT_TS
3
3
4 +3.3V_ALW
4
5 +5V_RUN
5
6
6 BC_INT#_ECE1117 <40>
7 BC_DAT_ECE1117 <40>
7
8
8
9 BC_CLK_ECE1117 <40>
9
10
10
11
GND
12
GND
ACES_51524-0100N-001 +3.3V_ALW +5V_RUN
CONN@
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
Link CIS 1 1
C756
C758
A A
2 2
Place close to JKB1 Title
Int KB/TP/BT/RSMRST
1.0
LA-7901P
5 4 3 2 1
5 4 3 2 1
+1.5V_RUN Source
+3.3V_ALW_PCH Source +PWR_SRC_S
+3.3V_ALW
Q49
SI3456DDV-T1-GE3_TSOP6~D +3.3V_ALW_PCH DC/DC Interface +PWR_SRC_S
100K_0402_5%~D
+3.3V_ALW2 +1.5V_MEM Q59 +1.5V_RUN
D
6 AO4304L_SO8
470K_0402_5%~D
5 4 8 1
1
100K_0402_5%~D
R905
10U_0603_6.3V6M~D
2 7 2
20K_0402_5%~D
10U_0603_6.3V6M~D
20K_0402_5%~D
1 6 3
1
R907
R920
1 5 1
G
2
C760
R908
C769
R921
+3.3V_ALW2
3
ALW_ENABLE
4
100K_0402_5%~D
2
1
2 2
D D
2
3300P_0402_50V7K~D
R909
1.5V_RUN_ENABLE
Q51B
1M_0402_5%~D
1
470P_0402_50V7K~D
ALW_ON_3.3V# 5
<20> ALW_ON_3.3V#
1
R1619
C762
2.2M_0402_5%
1
R1610
C771
4
6
2
Q52B
1 2 RUN_ON_ENABLE# 5
<40,44> PCH_ALW_ON <40> RUN_ON_ENABLE#
2
2
Q51A
@ R737 0_0402_5%~D
2
<16,40> SIO_SLP_S5# 1 2 2
4
6
@ R745 0_0402_5%~D
Q52A
<11,16,27,35,39,47,48,49> SIO_SLP_S3# 1 2
1
@ R735 0_0402_5%~D
<27,35,39,47,48> RUN_ON 1 2 2
@ R744 0_0402_5%~D
1
+1.05V_RUN Source
+PWR_SRC_S +PWR_SRC_S
+3.3V_SUS Source Q54
470K_0402_5%~D
330K_0402_5%~D
+3.3V_ALW SI3456DDV-T1-GE3_TSOP6~D +3.3V_SUS +1.05V_M Q63 +1.05V_RUN
1
SI4164DY-T1-GE3_SO8~D
D
+1.05V_RUN_VTT
R911
6 +1.05V_RUN 8 1
R930
+3.3V_ALW2 5 4 7 2
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
2 @ PJP7 6 3
1
20K_0402_5%~D
20K_0402_5%~D
1 1 2 5 1
2
1
100K_0402_5%~D
C772
1
G
1
R914
R931
PAD-OPEN 1x3m
4
R915
C765
SUS_ENABLE +1.05V_M
@ PJP8 1.05V_RUN_ENABLE 2
2
3
2
1 2
2
4.7M_0402_5%~D
220P_0402_50V8J~D
100P_0402_50V8J~D
2
1
D
Q53B
1M_0402_5%~D
1 PAD-OPEN 1x3m
1
R1618
C767
SUS_ON_3.3V# 5 2 1
Q64
R1611
C773
For SSI G
6
4 S
3
C <39> SUS_ON 1 2 2 w/ vpro: PJP7 open and PJP8 open C
2
2
Q53A
@ R739 0_0402_5%~D
w/o vpro: PJP7 open and PJP8 short.depop Q63
2
<16,39,46> SIO_SLP_S4# 1 2 2
@ R746 0_0402_5%~D For PT
w/o vpro: PJP7 and PJP8 open.pop Q63
1
+PWR_SRC_S
+5V_RUN Source
470K_0402_5%~D
+5V_ALW Q55 +5V_RUN
1
AO4478L_SO8
R906
8 1
+PWR_SRC_S 7 2
+3.3V_M Source
10U_0805_10V4Z~D
+3.3V_ALW Q58 6 3
1
470K_0402_5%~D
20K_0402_5%~D
SI3456DDV-T1-GE3_TSOP6~D +3.3V_M +3.3V_SUS 5 1
2
1
+3.3V_ALW2
D
R917
C761
R910
6
S
4
5 4 2 1 5V_RUN_ENABLE
2
100K_0402_5%~D
2 @ R206 0_0603_5%~D
2
1
1
2
R918
10U_0603_6.3V6M~D
220P_0402_25V8J
For w/o vpro,+3.3V_M
G
1
D
20K_0402_5%~D
1
3
change to +3.3V_SUS
C768
@ R919
Q62
A_ENABLE 2 1
G
2
3
C763
S
3
2
2
Q57B
4.7M_0402_5%~D
220P_0402_50V8J~D
2
1
A_ON_3.3V# 5 1
R1617
6
C770
4
2
Q57A
+3.3V_RUN Source
2
<16,39,48> SIO_SLP_A# 2
1
+PWR_SRC_S +3.3V_ALW Q61 +3.3V_RUN

B B
AO4478L_SO8
470K_0402_5%~D
8 1
1
7 2
R912
10U_0805_6.3V6M~D
20K_0402_5%~D
6 3
1
5 1
C764
R913
2
4
Discharge Circuit
2
2
3.3V_RUN_ENABLE
220P_0402_25V8J
1M_0402_5%~D
1
1
D
@
+1.5V_CPU_VDDQ 1
Q56
R1627
+3.3V_SUS +3.3V_ALW_PCH +5V_RUN +1.5V_RUN +3.3V_RUN +1.05V_RUN +0.75V_DDR_VTT 2
C766
+3.3V_M G
1
1K_0402_1%~D
1K_0402_1%~D
1K_0402_1%~D
39_0603_5%~D
39_0402_5%~D
220_0402_5%~D
S
3
1
1
2
22_0603_5%~D
2
1
@
1K_0402_1%~D +3.3V_SUS_CHG
@ R928
@ R923
@ R924
@ R925
R926
39_0603_5%~D
1
@ R922
R929
R927
R916
2
+1.5V_CPU_VDDQ_CHG
2
2
+3.3V_ALWPCH_CHG
+5V_RUN_CHG
+1.5V_RUN_CHG
+3.3V_RUN_CHG
+1.05V_RUN_CHG
2
2
+DDR_CHG
+3.3V_M_CHG
1
D D D D
1
1
D D @ D D D
@ Q65
@ Q67
@ Q68
@ Q70
RUN_ON_ENABLE# 2 2 2 2
@ Q66
Q69
Q71
SUS_ON_3.3V# ALW_ON_3.3V# G G G G Q72 A_ON_3.3V#

2 2 <7,11> RUN_ON_CPU1.5VS3# 2 2 2
Q60
G G S S S S G G G
3
S S S S S
3
3
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT POWER CONTROL
5 4 3 2 1
5 4 3 2 1
HDD LED solution for White LED +3.3V_ALW

Battery LED
Q83B +5V_ALW
1 10K_0402_5%~D
+5V_ALW DMN66D0LDW-7_SOT363-6~D White
4 3 BAT2_MB_LED#_Q 1 2 BATT_WHITE_MB
<39> BAT2_LED#
R932
R949 1.2K_0402_5%~D
3
1
5
3
SYS_LED_MASK#
Q74B Q74A 2
DMN66D0LDW-7_SOT363-6~D D59 DMN66D0LDW-7_SOT363-6~D Q125B
4 3 1 2 1 6 2 DMN66D0LDW-7_SOT363-6~D
<14> SATA_ACT# Yellow
4 3 BAT1_MB_LED#_Q 1 2 BATT_YELLOW_MB
D <39> BAT1_LED# D
RB751S40T1_SOD523-2~D Q75 R951 470_0402_5%~D LED2
PDTA114EU_SC70-3~D LTW-326DSKS-5A_WHI-YEL
2
Note: LED current must be at least 2mA
5
LED3 SYS_LED_MASK#
<39> MASK_SATA_LED#
1
SYS_LED_MASK#
1 2 SATA_LED_MB 2 1
R934 1.2K_0402_5%~D
3
LTW-110DC5-C_WHITE Q125A
Note: LED current must be at least 2mA DMN66D0LDW-7_SOT363-6~D
1 6 BAT1_LED#_Q 1 2 BATT_YELLOW_LED
HDD_LED R953 130_0402_5%~D
2
3
MASK_BASE_LEDS#
Q80A
D62 DMN66D0LDW-7_SOT363-6~D Q83A
1 2 1 6 2 DMN66D0LDW-7_SOT363-6~D
<39> LED_SATA_DIAG_OUT#
1 6 BAT2_LED#_Q 1 2 BATT_WHITE_LED
RB751S40T1_SOD523-2~D Q81 R958 560_0402_5%~D
PDTA114EU_SC70-3~D
2
MASK_BASE_LEDS#
1
MASK_BASE_LEDS# 1 2
R938 1.1K_0402_1%~D
Breath LED
WLAN LED solution for White LED
+3.3V_ALW Q84A +5V_ALW
+5V_ALW DMN66D0LDW-7_SOT363-6~D
100K_0402_5%~D
C 1 6 BREATH_LED#_Q 1 2 BREATH_WHITE_LED_MB 1 2 C
<38,39> BREATH_LED#
1
R957 1.2K_0402_5%~D
R937
3
3
LED1
Q78A SYS_LED_MASK# LTW-110DC5-C_WHITE
2
DMN66D0LDW-7_SOT363-6~D Note: LED current must be at least 2mA

<34,39> WIRELESS_LED# 1 6 2
Q84B
4 3 BREATH_PWR_LED#_R 1 2 BREATH_PWR_LED#
2
Q79 R959 1.2K_0402_5%~D

MASK_BASE_LEDS# PDTA114EU_SC70-3~D
1
5
3
MASK_BASE_LEDS#
Q78B
<41> BT_ACTIVE 5
4
100K_0402_5%~D
1 2 WLAN_LED
1
R939 1.2K_0402_5%~D
MEDIA BOARD
R950
JMED1
2
+5V_ALW 1
1
2
<40> POWER_SW#_MB 2
+3.3V_RUN 3
BREATH_PWR_LED# 3
4
4
5
@ SW2 5
<29> DMIC_CLK1 6
NTC033-XJ1J-X260CM_4P 6
7
POWER_SW#_MB 7
3 1 8
<29> DMIC1 8
9
<18> MEDIA_DET# 9
PESD24VS2UT_SOT23-3~D
10
<40> VOL_MUTE 10
2
11 13
LED Circuit Control Table <40> VOL_DOWN
12
11 GND
14
B <40> VOL_UP 12 GND B
D23
4 2
ACES_51522-01201-001
SYS_LED_MASK# LID_CL# +3.3V_RUN +5V_ALW CONN@
Link CIS
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
Mask All LEDs (Sniffer Function) 0 X 1 1
C1005
C1004
Mask Base MB LEDs (Lid Closed) 1 0
Do not Mask LEDs (Lid Opened) 1 1 2 2
Close to JMED1
+3.3V_ALW LED BOARD
JLED1
C778 +5V_ALW 1
1
1 2 2
2
+3.3V_ALW 3
0.1U_0402_25V6K~D HDD_LED 3
4
4
5
BATT_WHITE_LED 5
BATT_YELLOW_LED 5
1 6
P
<39> SYS_LED_MASK# B 6
4 MASK_BASE_LEDS# WLAN_LED 7
O 7
<39> LID_CL# 2 <39> LID_CL# 8
A 8
G
U58 9 11
TC7SH08FU_SSOP5~D 9 GND
10 12
3
10 GND
+3.3V_ALW +5V_ALW
ACES_51522-01001-001
Fiducial Mark
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
CONN@
@ FD1 1 1 Link CIS
C1002
C1003
1
@ H1 @ H2 @ H3 @ H4 @ H5 @ H6 @ H7 @ H8 @ H9 @ H10 @ H11 @ H12 @ H13 @ H14
FIDUCIAL MARK~D H_2P8 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P3 H_3P3 H_1P6X3P0N H_3P8 H_3P8 H_3P8 H_3P8 H_6P7N
A
@ FD2
EMI CLIP 2 2 A
1 CLIP1 @
1
EMI_CLIP
FIDUCIAL MARK~D
@ FD3 @ H15 @ H16 @ H17 @ H18 @ H19 GND

1 Close to JLED1
1 H_2P2N H_2P3 H_2P3 H_3P3 H_2P3
FIDUCIAL MARK~D
1
@ FD4
Title
1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL PWR/LED Conn/PAD/ME
FIDUCIAL MARK~D TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
5 4 3 2 1
5 4 3 2 1
+COINCELL
COIN RTC Battery
1
PR1
1K_0402_5%
+3.3V_RTC_LDO
2
D +COINCELL D
Z4012
JRTC1
1
1
2
ESD Diodes +RTC_CELL
2
2
3
G1
4
G2
1
PD4 ACES_50273-0020N-001
1
PD5 PD6 CONN@
PESD24VS2UT_SOT23-3~D PESD24VS2UT_SOT23-3~D PL2 +3.3V_ALW RB715FGT106_UMD3
1
FBMJ4516HS720NT_2P~D
1 2 PC3
Primary Battery Connector 1U_0603_10V6K
2
PL3
1
FBMJ4516HS720NT_2P~D Move to power schematic
100K_0402_5%
PBATT1 PBATT+_C 1 2 PBATT+
PR6
11
0.1U_0402_25V6
G2
1
10
G1
PC4
9 PR7
2
9 100_0402_5% PR9
8
2
8 Z4304 100_0402_5% PR8
7 1 2 PBAT_SMBCLK <40>
7 Z4305 100_0402_5%
6 1 2 PBAT_SMBDAT <40>
6 Z4306
5 1 2 PBAT_PRES# <39>
5
1
4
PC5 4 PQ1
3
2200P_0402_25V7K 3
2
2
2 FDN338P_G_NL_SOT23-3~D
1
1 PD8
SUYIN_200045MR009G188ZL 1 2 1 3
3
DOCK_SMB_ALERT# <38,39>
CONN@
SCH DIO DB2J31400L SOD323-2
2
2
C C
GND 1 PR10
2
<38,39,53> SLICE_BAT_PRES#
0_0402_5%
@
1
PC6
1500P_0402_7K~D
2
+3.3V_ALW
PR11 @ PU1
2.2K_0402_1%
2
1 2 <38> DOCK_PSID 1 6 GPIO_PSID_SELECT <39>
0_0402_5% NO IN
PR12
2 5 +5V_ALW
PL4 PR13 GND V+
1
BLM18BD102SN1D_0603~D 33_0402_5%~D
NB_PSID NB_PSID_TS5A63157
S
2 1 1 3 1 2 3 4 PS_ID <40>
NC COM
PQ2 TS5A63157DCKR_SC70-6~D
100K_0402_1%
2
FDV301N_G_NL_SOT23-3~D
G
2
PR14 +5V_ALW
10K_0402_1%
1
1
C
PQ3
PR15
2
B MMST3904-7-F_SOT323~D
E
15K_0402_1%~D
3
2
2
PR16
PR17
B
1 2 B
PSID_DISABLE# <39>
1
10K_0402_5%
@
DC_IN+ Source
+PWR_SRC +PWR_SRC_S
3 1
+DC_IN +DC_IN_SS
PQ5
100K_0402_1%
0.1U_0402_25V6
0.22U_0603_25V7K
1
FDS6679AZ_G_SO8~D
1
PC9
PC8
PR19
1 8
PL5 S D
2 7
FBMJ4516HS720NT_2P~D S D
3 6
2
+DC_IN S D
1 2 4 5
2
G D PQ4
1
PR20 TP0610K-T1-E3_SOT23-3
1M_0402_5%~D
10U_0805_25V6K
0.022U_0603_50V7K
2
22K_0402_1%
100K_0402_5%
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1
VSB_N_001
PC10
PR21
1 2
1
PC15
1VSB_N_003
1
PC11
PC13
PC14
PR22
0.1U_0402_25V6
2
1
PJPDC1 PR23
@ 4.7K_0805_5%~D
2
1
PS_HPW15003-05M101R 1 2
@0.1U_0402_25V6
SOFT_START_GC <53>
2
1
PC12
5
2
5 D
4 -DCIN_JACK 10K_0402_5%
PR24
4
1
PR25
2 VSB_N_002 PQ6
PC16
3 1 2
1M_0402_5%~D
<40,42> PCH_ALW_ON
2
3
2 +DCIN_JACK 0_0402_5% G SSM3K7002FU_SC70-3
2
2
PR26
1 @ S
.1U_0402_16V7K
3
1
PC17
CONN@
2
PL6
2
FBMJ4516HS720NT_2P~D
1 2
8/18 change from 7 pin to 5 pin
A A
0.1U_0402_25V6
1
PC18
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +DCIN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-7902P
5 4 3 2 1
A B C D E
2VREF_6182
1
PC101
1U_0603_16V6K
2
@ PC120 @ PC121
2 1 2 1
1 1
22P_0402_50V8J~D 22P_0402_50V8J~D
PJP100 PR101 PR102
1 2 13.7K_0402_1% 30.9K_0402_1%
1 2 1 2
@
PAD-OPEN 1x3m
+PWR_SRC +DC1_PWR_SRC PR103 PR104

20K_0402_1% 20K_0402_1% +DC1_PWR_SRC
FB_3V FB_5V 1
PL100 +3.3V_RTC_LDO 1 2 2
1UH_PCMB053T-1R0MS_7A_20%
2 1
+3.3V_ALW2
PR105 PR106
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
PR100 130K_0402_1% 93.1K_0402_1%~D

1
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
PC103
PC119
0.1U_0402_25V6
1 2 1 2 ENTRIP2 ENTRIP1
1 2
1
PC100
PC102
PC106
PC118
0_0402_5%
PC104
PC105
PQ100 @
2
1
FDMC8884_POWER33-8-5 PU100
5
@ @
ENTRIP2
FB2
TONSEL
FB1
ENTRIP1
REF
1
PC107 PQ101
4 10U_0603_6.3V6M 25 FDMC8884_POWER33-8-5
P PAD
2
7 VO2 VO1 24 4
1
2
3
PC108 8 23 PC109
0.22U_0402_16V7K~D VREG3 PGOOD 0.22U_0402_16V7K~D
PR107 PR108
1 2 BST1_3V 1 2 BST_3V 9 22 BST_5V 1 2 BST1_5V 1 2
3
2
1
BOOT2 BOOT1
2.2_0603_5% 2.2_0603_5%
PL101 UG_3V 10 21 UG_5V PL103
2 4.7UH_FDSD0630-H-4R7M-P3_5.5A_20% UGATE2 UGATE1 4.7UH_FDSD0630-H-4R7M-P3_5.5A_20% 2
+3.3V_ALWP 1 2 LX_3V 11 PHASE2 PHASE1 20 LX_5V 1 2
+5V_ALWP
1
1
4.7_1206_5%
4.7_1206_5%
LG_3V 12 19 LG_5V
LGATE2 LGATE1
150U_B2_6.3VM_R35M
PR109
PR110
PQ102
SKIPSEL
150U_B2_6.3VM_R35M
FDMC8878_POWER33-8-5
VREG5
1
1
GND
VIN
PC110
NC
EN
2
PC111
4 4 +
SNUB_3V
SNUB_5V
13
14
15
16
17
18
2 PQ103
RT8205LZQW(2) WQFN 24P PWM FDMC7692S_POWER33-8-5 2
680P_0402_50V7K
1
2
3
3
2
1
680P_0402_50V7K
+5V_ALW2
PC112
1
PC113
3.3VALWP
1
TDC 5.185A
2
2
Peak Current 7.407A
1
300K_0402_1%
1U_0603_10V6K
1
+3.3V_ALW
PC115
PC114
OCP current 9.629A
PR111
4.7U_0805_10V6K
2
2
PD100
PR113 +DC1_PWR_SRC PR112
2
@ 499K_0402_1% 100K_0402_1%
1
1 2 2 1 @
+PWR_SRC
1
PC116
2VREF_6182
2
@ RLZ5.1B_LL34 0.1U_0402_25V6
ALW_PWRGD_3V_5V <40>
ENTRIP2
ENTRIP1
5VALWP
2N7002DW-T/R7_SOT363-6~D
2N7002DW-T/R7_SOT363-6~D
3 3
TDC 4.415A
Peak Current 6.308A
3
OCP current 8.2A

PQ104B
PQ104A
5 2
PJP101
4
1 2
PAD-OPEN 1x3m
PR114
100K_0402_1% PJP102
1 2
+5V_ALW2 +5V_ALWP 1 2 +5V_ALW (5A,180mils ,Via NO.= 9)
1
PAD-OPEN 1x3m
PR115 PQ105 PJP103
2K_0402_1% PDTC115EU_SOT323-3
+3.3V_ALWP 1 2 +3.3V_ALW (4A,120mils ,Via NO.= 6)
<40> ALWON 1 2 2
PAD-OPEN 1x3m
PR116
3
<22> THERM_STP# 1 2
0_0402_5%
@
1U_0603_10V6K
4 4
1
PC117
2
@
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +5V_ALW/3.3V_ALW
A B C D E
5 4 3 2 1
1.5Volt +/- 5%
TDC 9.74A
D D
Peak Current 13.915A 0.75Volt +/- 5%
OCP current 16.698A TDC 0.525A
Peak Current 0.75A
+PWR_SRC PJP200 OCP Current 0.9A
2 1 1.5V_B+
PJP204
PR200
@ PAD-OPEN 1x2m~D 1 2 BOOT_1.5V VLDOIN_1.5V 2 1 +1.5V_MEN_P
2.2_0603_5%
@ PAD-OPEN1x1m
DH_1.5V +0.75V_P
0.1U_0402_25V6
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
0.22U_0402_16V7K~D
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
SW _1.5V
PC278
PC281
PC274
PC276
PC279
1
2200P_0402_25V7K
2
1
DL_1.5V
PC280
PC263
16
17
18
19
20
PU200
VLDOIN
PHASE
UGATE
BOOT
VTT
2
PAD 21
4 15 1
+1.5V_MEN_P PQ200 LGATE VTTGND
FDMC8884_POW ER33-8-5
PR201 14 2
C PL200 22.6K_0402_1% PGND VTTSNS +V_DDR_REF C
1
2
3
1UH_FDSD0630-H-1R0M_11A_20% 1 2 CS_1.5V
1 2 13 CS GND 3
RT8207MZQW _W QFN20_3X3
+5V_ALW
5
PR202 1 2 PC272 12 4 +V_DDR_REF
VDDP VTTREF
1
1 5.1_0603_5%~D 1U_0603_10V6K
PC275
+ PC65 680P_0402_50V7K 1 2 VDD_1.5V 11 5 VDDQ_1.5V +1.5V_MEN_P
+5V_ALW
2
330U_2.5V_M VDD VDDQ
PGOOD
4
1
1SNUB_1.5V
TON
2 PC253 PC277
FB
S5
S3
1U_0603_10V6K 0.033U_0402_16V7~D
2
PQ210
1
2
3
10
6
FDMC7692S_POW ER33-8-5
PR203
+3.3V_ALW @
4.7_1206_5% PR237
1
0_0402_5%
PR204 1.5V_FB 1 2
2
100K_0402_1%
@ PC215
22P_0402_50V8J~D
2
2 1
Mode Level +0.75V_P +V_DDR_REF <40> 1.5V_SUS_PW RGD 1.5V_SUS_PW RGD
PR205
S5 L off off
2
@ 1M_0402_1%~D
1
S3 L off on PR206 1.5V_B+ 1 2 PR238
0_0402_5% 0_0402_5% PC282
B S0 H on on S5_1.5V @ .1U_0402_16V7K B
<40> DDR_ON 1 2
2
1
1
Note: S3 - sleep ; S5 - power off PR232

1 2 PC255
<16,39,42> SIO_SLP_S4#
0_0402_5% @ .1U_0402_16V7K
2
@ PR236
<39> 0.75V_DDR_VTT_ON 1 2
0_0402_5%
@
+1.5V_MEN_P
PJP203
PJP201
+1.5V_MEN_P 2 2 1 1 +1.5V_MEM +0.75V_P 2 1 +0.75V_DDR_VTT
@ JUMP_1x3m
@ PAD-OPEN1x1m
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.5V_MEN/+0.75V_DDR_VTT
5 4 3 2 1
A B C D
1 1
PR300
2 1
1.8Volt +/-5%
+3.3V_RUN
TDC 0.85A
10K_0402_5%
Peak Current 1.215A
1.8V_RUN_PWRGD <39> OCP current 1.458A
PU300 PL301
4
PJP301 1UH +-30% NRS4018T1R0NDGJ 3.2A
+3.3V_ALW 2 1 1.8VSP_VIN 10 2 1.8VSP_LX 1 2
PG
PVIN LX +1.8V_RUNP
22P_0402_50V8J
@ PAD-OPEN 1x2m~D 9 3
PVIN LX
1
1
1
4.7_0603_5%
2 2
PC301
PC300 PC307 8 SVIN
PR301
22U_0805_6.3VAM 0.1U_0402_25V6 PR302
6 1.8VSP_FB 20K_0402_1%
2
FB
47P_0402_50V8J
22U_0805_6.3VAM
22U_0805_6.3VAM
5
2
EN
PC306
NC
NC
TP
PC302
PC303
0_0402_5% @
11
2
SNUB_1.8VSP
<27,35,39,42,48> RUN_ON 1 2EN_1.8VSP
1
1
.1U_0402_16V7K
PR303 @
PC304
SYN470DBC_DFN10_3X3 PR305
1
@ PR304 10K_0402_1%
PR306 47K_0402_5%
2
<11,16,27,35,39,42,48,49> SIO_SLP_S3# 1 2
680P_0402_50V7K
0_0402_5% @
PC305
@
2
@
<Vo=1.8V> VFB=0.6V
3
Vo=VFB*(1+PR64/PR67)=0.6*(1+20K/10K)=1.8V 3
PJP300
2 1
+1.8V_RUNP +1.8V_RUN
@ PAD-OPEN 1x2m~D
4
DELL CONFIDENTIAL/PROPRIETARY 4

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.8V_RUN
A B C D
5 4 3 2 1
PJP400
D +V1.05SP_B+ D
2 1
+PWR_SRC
@ PAD-OPEN 1x2m~D
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
2200P_0402_25V7K
0.1U_0402_25V6
1
1
PC401
PC402
PC403
PC400
5
+3.3V_ALW
2
100K_0402_1%
1
PR400
4
2
PR401 PC404 PQ400
3
2
1
<40> 1.05V_A_PWRGD PU400 2.2_0603_5% 0.1U_0402_25V6 FDMC8884_POWER33-8-5
PR402 1 10 BST_+V1.05SP 1 2 1 2
82K_0402_1% PGOOD VBST
S0 mode be high level 1 2 TRIP_+V1.05SP 2 9 UG_+V1.05SP PL400
TRIP DRVH 1UH_FDSD0630-H-1R0M_11A_20%
C
EN_+V1.05SP 3 EN SW 8 SW_+V1.05SP 1 2 +1.05V_MP C
5
PR403 FB_+V1.05SP 4 7
VFB V5IN +5V_ALW
<16,39,42> SIO_SLP_A# 1 2
0_0402_5% RF_+V1.05SP 5 6 LG_+V1.05SP 1
RF DRVL
1
@ 1 2
1 2 11 + PC406
<11,16,27,35,39,42,47,49> SIO_SLP_S3# TP
1
@ 4 PR404 220U_B2_2.5VM_R15M
PR408 0_0402_5% TPS51212DSCR_SON10_3X3 PC405 4.7_1206_5%
1 2 PR405 1U_0402_6.3V6K 2
<27,35,39,42,47> RUN_ON
2
PQ405
@ 470K_0402_1%
1
PR409 0_0402_5%
2
3
2
1
1
PC407
@ .1U_0402_16V7K PC408
：：
2
680P_0402_50V7K
2
With vPro pop PR403
Without vPro pop PR408
5@ for TM pop
6@ for vPOR pop PR406
4.99K_0402_1%
B B
2 1
+1.05Volt +/- 5%
2
TDC 4.7A
PR407 Peak Current 6.5A
10K_0402_1%
OCP current 7.8A
1
+1.05V_MP 2 1 +1.05V_M
PJP401
@ PAD-OPEN 1x2m~D
A
DELL CONFIDENTIAL/PROPRIETARY A

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.05V_M
5 4 3 2 1
5 4 3 2 1
PJP500
+V1.05S_VCCPP_B+ 2 1
+PWR_SRC
@ PAD-OPEN 1x2m~D
+3.3V_RUN
2200P_0402_25V7K
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
0.1U_0402_25V6
1
1
PC501
PC502
PC503
PC500
2
D D
2
5
PR500
100K_0402_5%
1
PR502 PC504
2.2_0603_5% 0.1U_0402_25V6 4
<40,50> 1.05V_VTTPWRGD
1 2 1 2
PQ500
PU500 FDMC8884_POWER33-8-5
PR501 1 10 BST_+V1.05S_VCCPP
3
2
1
84.5K_0402_1% PGOOD VBST
1 2 TRIP_+V1.05S_VCCPP 2 TRIP DRVH 9 UG_+V1.05S_VCCPP PL500
1UH_FDSD0630-H-1R0M_11A_20%
EN_+V1.05S_VCCPP 3 8 SW_+V1.05S_VCCPP 1 2
@ PR503 EN SW +1.05VTTP
1 2 FB_+V1.05S_VCCPP 4 7
<39> CPU_VTT_ON
0_0402_5% VFB V5IN +5V_ALW 1
1 2 RF_+V1.05S_VCCPP 5 6 LG_+V1.05S_VCCPP
42,47,48> SIO_SLP_S3# RF DRVL
1
@ PR307 + PC511
11 PC505 220U_B2_2.5VM_R15M
0_0402_5% TP 1U_0603_6.3V6M PR504
2
1
TPS51212DSCR_SON10_3X3 4.7_1206_5% 2
1
PC506
2
C C
@ .1U_0402_16V7K PR505 4 PC510
2
470K_0402_1% .1U_0402_16V7K
2
1
2
PC508
PQ501 680P_0402_50V7K @
3
2
1
2
FDMC7692S_POWER33-8-5 Local sense put on HW site
PR507
4.99K_0402_1%
2 1 VTT_SENSE_FB 1 PR508 2 VTT_SENSE <10>
0_0402_5%
@
VSSIO_SENSE_R_FB 1 PR513 2 VSSIO_SENSE_R <10>

0_0402_5%
@
1
PR509 +3.3V_RUN +1.05Volt +/- 5%

@
71.5K_0402_1% TDC 6A
B VCCP_PWRCTRL = "High" , Vo = 1.05V (SNB) Peak Current 8.5A
B
2
VCCP_PWRCTRL = "Low" , Vo = 1V (IVB)

OCP current 10.2A
2
PR510 PR511
10K_0402_1% @ 10K_0402_5%
SSM3K7002FU_SC70-3
1
1
1
D
PQ502
2 From GPIO
VCCP_PWRCTRL <11>
G
S
3
1
@ PJP501
PR514 2 1
@ 10_0402_1% PC509
2
@ .01U_0402_16V7K @ PAD-OPEN 1x2m~D

2
PJP502
+1.05VTTP 2 1 +1.05V_RUN_VTT
A @ PAD-OPEN 1x2m~D DELL CONFIDENTIAL/PROPRIETARY A

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.05V_RUN_VTT
5 4 3 2 1
5 4 3 2 1
VID [0] VID[1] VCCSA Vout

D
0 0 0.9V D
The 1k PD on the VCCSA VIDs are empty. 0 1 0.8V

These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability. 1 0 0.725V
1 1 0.675V
PR78
1K_0402_5%
2 1
output voltage adjustable network
+3.3V_RUN
1 PR90
2 VCCSA_VID_1 <11>
0_0402_5%
100K_0402_5%
@
1
PR79
1 PR91
2
VCCSA
VCCSA_VID_0 <11>
0_0402_5% TDC 4.2A
2
@
<40> VCCSAPWROK
2 PR80
1 PR81 Peak Current 6A
0_0402_5% 1K_0402_5%
+VCCSA_PWRGD
@ 2 1 OCP current 7.2A
+5V_ALW
1U_0603_10V6K
2
PC74
PR82
10_0402_1% PR83
1
2 1 +VCCSA_EN 1 2 1.05V_VTTPWRGD <40,49>
PC75 0_0402_5%
C 2.2U_0603_10V7K @ C
1 2
18
17
16
15
14
13
PU7
PR84 PC76
VID1
VID0
PGOOD
EN
V5FILT
V5DRV
2.2_0603_1% 0.1U_0402_25V6
12 +VCCSA_BT 1 2+VCCSA_BT_1 1 2
BST PL15
19
PGND 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
SW
11 +VCCSA_PHASE 1 2 +VCCSA_P
20
PGND
22U_0805_6.3V6M
.1U_0402_16V7K
10
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
2200P_0402_25V7K
SW
1
21
PGND
2
PC77
PC79
PC81
PC82
PC83
PC84
PC85
TPS51461RGER_QFN24_4X4~D @ 680P_0402_50V7K
PC80
9
0.1U_0402_25V6
10U_0805_25V6K
2200P_0402_25V7K
1 2
SW
22
1
VIN
1
@
PC89 8
10U_0805_25V6K SW PR85
PC86
PC87
PC88
23
+3.3V_ALW
2
VIN @ 4.7_1206_5%
PJP19 7
2
SW
2 1 +VCCSA_PWR_SRC +VCCSA_PWR_SRC 24
VIN
@ PAD-OPEN 1x2m~D 25
COMP
MODE
TP
SLEW
VOUT
VREF
GND
1
6
2 1
PR86
22K_0402_1%
PR87
100_0402_5%
PC90 2 1
B B
2 1
GNDA_VCCSA
0.22U_0402_16V7K~D
2 1 2 1
1 PR88
2
0.01U_0402_25V7K
VCCSA_SENSE <11>
PC91 PR89 0_0402_5%
2
3300P_0402_50V7K 5.1K_0402_1% @
PC92
PJP20
+VCCSA_P 1 2
+VCC_SA
PAD-OPEN 4x4m
PJP21
2 1
PAD-OPEN1x1m
GNDA_VCCSA
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +VCC_SA
5 4 3 2 1
5 4 3 2 1
PR701 PC701
2K_0402_1% 330P_0402_50V7K
VCC_GFXCORE
Local sense put on HW site 2 1 2 1 TDC 21.5A
PR702 PR703 PC702 Peak Current 33A
2 1 2 1 2 1
OCP current 57.18A
+VCC_PWR_SRC
150K_0402_1%~D
@ PC703 2.74K_0402_1% 130K_0402_1% 150P_0402_50V8F~D
Load line -3.9mV/A
PR705
2 1
<11> VCC_AXG_SENSE PR704 PC704 PC705
330P_0402_50V7K 2 1 2 1 1 2
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
<11> VSS_AXG_SENSE PC706 499_0402_1% 390P_0402_50V7K 68P_0402_50V8J
5
1 2
PQ708
1
PC746
PC747
PC749
PC752
0.01U_0402_50V7K
D D
2
4
VSUMG+
2.61K_0402_1%
MDU1516URH 1N POWERDFN56-8
3
2
1
1
0.022U_0402_25V7K 1 2 IMVP_PWRGD
0.082U_0402_16V7K
.1U_0402_16V7K
PR707
@
11K_0402_1%
PR708 0_0402_5% PL704

1
0.36UH_FDUE104J-H-R36M=P3_33A_20%~D
+VCC_GFXCORE
1
1
PR709
PC707
PC708
PC709
10KB_0402_5%_ERTJ0ER103J
4 1
1 2
680P_0402_50V7K
@ PR710
5
649_0402_1%~D PQ711 PQ710 GP1_SW GP1_Vo
SIR818DP-T1-GE3_POWERPAK8-5
3 2
2
PC751
1 2
2
2
PH700
LGATE1G
10K_0603_1%
3.65K_0603_1%
PC710 PC750
10K_0402_1%
PR711 3300P_0402_50V7K PHASE1G 0.22U_0402_16V7K~D
2
1 1
1_0402_5%
PR761
PR758
PR759
PR762
383_0402_1% 4 4
PGOODG
4.7_1206_5%
VSUMG- 1 2 UGATE1G
1
PR763
.1U_0402_16V7K
PR760
@ BOOT1G 2.2_0603_5% @
1
1
@ ISEN2G
3
2
1
3
2
1
PC711
@ PC712
2
2 1
2
2
VSUMG+ VSUMG-
40
39
38
37
36
35
34
33
32
31
VSUMG- 0.22U_0402_16V7K~D PU700 BOOT2
@ PC713
ISUMNG
RTNG
FBG
COMPG
PGOODG
PWM2G
LGATE1G
PHASE1G
UGATE1G
BOOT1G
2 1 UGATE2 ISEN1G
PR712
1 2 2 1 0.22U_0402_16V7K~D PHASE2
PH701
3.83K_0402_1% 470K_0402_5%_ TSM0B474J4702RE 1 PR713 2 ISEN1G
1
2
ISUMPG BOOT2 30
29 LGATE2 PR714 +5V_ALW VCC_core
+5V_RUN 0_0402_5% ISEN2G 3
ISEN1G UGATE2
28 1 2 TDC 36A
PR7151 @ NTCG ISEN2G PHASE2 0_0402_5%
2 4 27
C
27.4K_0402_1% SCLK 5
NTCG
SCLK
LGATE2
VCCP 26 VCCP @ 1 2 Peak Current 53A C
<10> VIDSCLK 2 ALERT# 1 PR716 6 25 PR717

0_0402_5% 7
ALERT# VDD
24 PWM3 1_0603_5% OCP current 64A
@ PR718 SDA PWM3 PR720
<10> VIDALERT_N 1 2 8 VR_HOT# LGATE1 23 Load line -1.9mV/A
0_0402_5% VR_EN 9 22 LGATE1 2 1
VR_ON PHASE1
<10> VIDSOUT 1 @ PR7192 SDA NTC 10 NTC UGATE1 21 Icc_Dyn_VID1 43A
ISEN3/FB2
0_0402_5% PHASE1 1_0603_5%
PGOOD
1 @ PR7212 VR_HOT#
BOOT1
ISUMN
ISUMP
1
COMP
ISEN2
ISEN1
0_0402_5% UGATE1
+PWR_SRC
RTN
@ PR722 @ 41 PC714 PC715 PL700
FB
<39> IMVP_VR_ON TP 1U_0603_10V6K 1U_0603_10V6K FBMA-L11-453215-121LMA90T_2
<7,40,52> H_PROCHOT# 1 2
2
0_0402_5% +VCC_PWR_SRC 1 2
11
12
13
14
15
16
17
18
19
20
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
<14,40> 1.05V_0.8V_PWROK 1 PR723
2 ISL95836HRTZ-T_TQFN40_5X5~D
+1.05V_RUN_VTT
5
PR724 @ 0_0402_5%
1 2 @ BOOT1 PQ700
PGOOD
1
PC716
PC717
PC700
PC753
0_0402_5% PR725 COMP
43P_0402_50V8J~D
ISEN3
ISEN2
ISEN1
1 2 2 1
PC719
PH702 PR726
2
1
3.83K_0402_1% 470K_0402_5%_ TSM0B474J4702RE 1 2 IMVP_PWRGD <39> UGATE2 4

0_0402_5%
PR727 @ PR728 1.91K_0402_1%
2
27.4K_0402_1% 2 1
2 1 +3.3V_RUN MDU1516URH 1N POWERDFN56-8 PL701
3
2
1
0.36UH_FDUE104J-H-R36M=P3_33A_20%~D
PHASE2 4 1
+VCC_CORE
680P_0402_50V7K
PC720 22P_0402_50V8J 3 2
PC725
PR730 54.9_0402_1% COMP PR729 PQ703 PQ702
2 1
BOOT2 2 1 1 2
2 1 SCLK PR732 @ 2.2_0603_5% P2_SW P2_Vo
2
1 2 PC721
+5V_RUN 0_0402_5% PC722 0.22U_0402_16V7K~D PR733 PR734
1
4.7_1206_5%
@ PR735 75_0402_5% PR736 390P_0402_50V7K PC723 LGATE2 4 4 ISEN21 2 2 1ISEN1
PR731
2 1 ALERT# 2 1 2 1 2 1 10K_0603_1% @ 10K_0402_1%
B B
@ PC724 499_0402_1% 47P_0402_50V8J
PR737 130_0402_1% 2 1 PR738
3
2
1
3
2
1
2
2 1 SDA 0.22U_0402_6.3V6K VSUM+ 1 2
PC726 PR742 3.65K_0603_1%
VSUM- 2 1 PR740 PR741 PC727 21K_0402_1% PR743
0.22U_0402_6.3V6K 2 1 2 1 2 1 1 2 VSUM- 2 1
PC728 1_0402_5%
2 1 2K_0402_1% 130K_0402_1% 150P_0402_50V8F~D
0.22U_0402_6.3V6K +VCC_PWR_SRC
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
100U_25V_M~D
100U_25V_M~D
0.1U_0402_25V6
PR744 PC729 1 1
5
1 2 1 2
+
PC730
+
PC731
PQ704
1
PC733
PC734
PC736
PC754
2K_0402_1% 680P_0402_50V7K
VSUM+
2 2
.1U_0402_16V7K
0.22U_0402_16V7K~D
2
11K_0402_1%
2.61K_0402_1%
0.047U_0402_25V7K
@ UGATE1 4
PC737
1
PR746
10KB_0402_5%_ERTJ0ER103J
1 2
PC740
VCCSENSE <10>
1
330P_0402_50V7K MDU1516URH 1N POWERDFN56-8 PL702
3
2
1
PC741 0.36UH_FDUE104J-H-R36M=P3_33A_20%~D
VSSSENSE <10>
12
1 2 PHASE1 4 1
+VCC_CORE
PC738 2
PC739 2
680P_0402_50V7K
PR747
PH703
0.01U_0402_50V7K
3 2
2
PC745
PR749 PQ706 PQ707 P1_Vo
PR750 BOOT1 2 1 1 2 P1_SW
2
VSUM- 2 1 2.2_0603_5%
2
365_0402_1% PC742
0.22U_0402_16V7K~D PR752 PR753
Local sense put on HW site
1
4.7_1206_5%
.1U_0402_16V7K
LGATE1 4 4 ISEN11 2 2 1 ISEN2

1
PR751
PR754 10K_0603_1% @ 10K_0402_1%
PC743
1 2 1 2 PC744
3300P_0402_25V7K
2
649_0402_1%~D PR755
3
2
1
3
2
1
2
A A
VSUM+1 2
3.65K_0603_1%
PR757
VSUM- 2 1
1_0402_5%
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +VCC_CORE
5 4 3 2 1
A B C D
ISL88731C 11@ @ PD1300

2 1 PL1300
BQ24747 22@ ES2AA-13-F
1UH_PCMB053T-1R0MS_7A_20%
2 1
PR1301
+SDC_IN 0.01_1206_1%~D +PWR_SRC CHAGER_SRC
1 PJP800
2 4 1 1 2
+DC_IN_SS
5 3
@0.1U_0402_25V6
PQ1300 3 2 @ PAD-OPEN 4x4m
47P_0402_50V8J
0.1U_0402_25V6
SI7121DN-T1-GE3_POWERPAK8-5
1
PC1300
PC1301
PC1302
4
PR1300
2
1
1 2 PR1302 D
DC_BLOCK_GC <53>
0_0402_5% 1 2 2 PQ1301
1 <53> CSS_GC 1
@ 0_0402_5% G NTR4502PT1G_SOT23-3~D @
1
@ D S
3
2 PQ1303A
G AP2623GY-HF 2P SOT26-6
PQ1302 S
PD1302
S
NTR4502PT1G_SOT23-3~D
D
5 6 DOCK_DCIN_IS+ <38>
E2 AC_OK=17.7 Volt +DOCK_PWR_BAR 2
CSSN_1
CSSP_1
1
G
1
PR1313 PQ1303B
3 PR1303 AP2623GY-HF 2P SOT26-6
TI bq24745 = 316K +DC_IN_SS 10K_0402_5%
10_0402_5%
S
Intersil ISL88731 = 226K
D
2 1 2 4
10_0402_5%
100K_0402_1%
BAT54CW_SOT323~D DOCK_DCIN_IS- <38>
PR1304
11@1
1
11@
PR1305
PR1306
100K_0402_1%
1
1
11@
G
3
+SDC_IN
MAX8731A_LDO MAX8731_REF PC1303 PC1304
PR1307
0.1U_0402_25V6 0.047U_0402_25V7K
11@ 10K_0402_1%
22@ 10K_0402_5%
11@ 226K_0402_1%~D
2
<53> +CHGR_DC_IN 1 2 1 2 11@ 1 2 1 2 PR1312
2
1
1
PC1305 1 2 DK_CSS_GC <53>
PR1309 0.1U_0402_25V6 0_0402_5%
PR1310
PR1311
2
@ 1_0805_5%~D 11@ @
PR1313
GNDA_CHG
28
27
1
PC1306 GNDA_CHG PU1300 ICOUT
2
0.1U_0805_50V7K
CSSN
ICREF
CSSP
2 1 +DCIN 22 26
1
DCIN ICOUT
2
PR1317 PR1318
1
2 49.9K_0402_1%
1 2 2.2_0603_1% PR1319
ACIN
1PS76SB21 SOD323-2
BOOT
25 1 2 BOOT_D 4.7_0603_5% PC1309
BOOT
1 PR1320 2 13 11@ 1U_0603_10V6K
11@ 15.8K_0402_1%
2
<22,40,53> ACAV_IN ACOK
1
0_0402_5% 11@
PC1310
0.1U_0402_25V6
0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_25V7K
1
1
1
@
PD1301
2 1 11
VDDSMB
5
PC1307
PR1316
1
0.01U_0402_25V7K GNDA_CHG PQ1304
PC1313
PC1314
PC1315
10
2
SCL
PC1312
22@ 2
GNDA_CHG 9 21 MAX8731A_LDO 1 2
2
2
+5V_ALW SDA VDDP
2 2
GNDA_CHG 14 PC1311 4
NC CHG_UGATE 1U_0603_10V6K
24
MAX8731_IINP UGATE
8
VICM
1
23 2 1 +VCHGR_B
@ 3300P_0402_50V7K
PC1316 PHASE PR1322 MDU1516URH 1N POWERDFN56-8
6
3
2
1
FBO
1
.1U_0402_16V7K 11@ 0_0603_5%
2
1 2 5
EAI PC1317
1
GNDA_CHG PR1323 @ 220P_0402_50V7K~D CHG_LGATE
PC1319
2 1 1 2 4 20
2.2K_0402_1%
200K_0402_5% PC1318 PR1324 EAO LGATE PR1326 +VCHGR

<40> CHARGER_SMBCLK
56P_0402_50V8~D
1
22@ 2200P_0402_25V7K 7.5K_0402_5% PL1301 0.01_1206_1%~D

PR1325
PC1320
2
<40> CHARGER_SMBDAT 22@ 22@ 5.6UH_FDVE1040-H-5R6M-P3_9.2A_20%~D
2
2 11@
MAX8731_REF 3 19 2 1+VCHGR_L
4 1
VREF PGND
18
PC1321 CSOP
3 2
22@1
<22> MAX8731_IINP
1
22@
120P_0402_50VNPO~D 1 2 7 17
0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
CE CSON
5
1 2 22@ PR1327
10_0402_5%
@ 8.45K_0402_1%
220P_0402_50V7K~D
1
1
10K_0402_5% 15 VFB 1 PR1328 2 PC1322
PR1330
+VCHGR
@.1U_0402_16V7K
2
VFB
1
1
Vref 22@ 680P_0402_50V7K
PC1330
PC1331
PC1332
12
0.01U_0402_25V7K
0.01U_0402_25V7K
0.01U_0402_25V7K
GND
2 11@
100_0402_5% PR1331
PR1329
PC1329
16
TI bq24747 = 3.3V NC
1
1
PC1327 0_0402_5%
PC1323
PC1325
PC1326
29
22@2
2
TP
2
Intersil ISL88731C = 3.2V 1U_0603_10V6K @
PQ1305
PC1324
PC1328
4
2
2
22@ PR1332
11@ 2
11@ 2
2
VDDP
1
ISL88731C_QFN28_5X5~D 4.7_1206_5%
TI bq24747 = 6V 11@ PJP801
1 2 PC1333
3
2
1
1
Intersil ISL88731C = 5.1V @ 0.1U_0402_25V6
22@ 1 2 1 2 1 2
@ PAD-OPEN1x1m
GNDA_CHG GNDA_CHG PC1334 PC1335
GNDA_CHG 0.22U_0402_16V7K @ 0.1U_0402_25V6
Maximum charging current is 7.2A 11@
GNDA_CHG
MAX8731_REF
+5V_ALW
+DC_IN MAX8731_REF
@ 100P_0402_50V8J
@0.01U_0402_25V7K
DYN_TUR_CURRENT_SET# PR1333
10K_0402_1%
3
1M_0402_1%~D 3
47K_0402_1%~D
232K_0402_1%~D
1
1
PC1336
PC1337
221K_0402_1%~D H_PROCHOT# <7,40,51> 1 2

2
PR1334
PR1335
PR1336
PR1338
+5V_ALW
65W High
2
2
+3.3V_ALW2
+5V_ALW PR1340 PR1339
2
1.8M_0402_1% 0_0402_5%
1
8
1 2 PU1304B
90W Low @
1
5 PR1342
P
+
1
PR1341 7 1 2
O ACAV_IN_NB <39,40,53>
2N7002DW-T/R7_SOT363-6~D
2N7002DW-T/R7_SOT363-6~D
150K_0402_1%~D PR1343 6 0_0402_5%
22.6K_0402_1%
100P_0402_50V8J
42.2K_0402_1%~D
41.2K_0402_1%~D
-
8
G
PQ1307B
20K_0402_1% PU1304A @
100P_0402_50V8J
6
1
PQ1307A
MAX8731_IINP 1 2 3 LM393DR_SO8~D
P
2
4
+
1
PC1338
PR1346
PR1347
PC1339
PR1348
1
O
2 5
-
G
2
220P_0402_50V7K~D
2
LM393DR_SO8~D @
4
2
1
PC1340
66.5K_0402_1%
150K_0402_1%~D
+3.3V_ALW
100P_0402_50V8J
1
2
1
PR1349
PR1350
PC1341
1
2
PR1351
+3.3V_ALW 100K_0402_5%
1
D PC1342
<40> DYN_TUR_CURRNT_SET# 2 0.1U_0402_25V6
2
G
S 2 1
3
PQ1310
2N7002KW 1N SOT323-3
5
PU1302
1
D
1
P
B
4 2 ACAV_IN <22,40,53>
O G
2 PROCHOT_GATE <39>
A
G
S 2N7002KW 1N SOT323-3
3
To preset system to throtlle
Adapter Protection Circuit for Turbo Mode PQ1306
3
4
TC7SH08FU_SSOP5~D switching from AC to DC 4
PU1300 22@ PR1313 22@ PR1325 22@ PC1334 22@ PR1330 22@ PR1304 22@ PR1305 22@ PC1304 22@ PR1322 22@
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Charger
BQ24747 316k_0402_1% 4.7k_0402_1% 0.1U_0402_25V6 0_0402_5% 0_0402_5% 0_0402_5% 0.1U_0402_25V6 1 +-5% 0603 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A B C D
5 4 3 2 1
S2AA-13-F SMA
PD17
2 1
PQ43
+DOCK_PWR_BAR 8 1
D S
7 2
D S
6 3
D D S D
5 4
0.47U_0805_25V7K~D
D G
1
FDS6679AZ_SO8~D
PC187
PR207
330K_0402_5%
2
2
PR208
1 2STSTART_DCBLOCK_GC
0_0402_5%
@
PD18
2
1
3
PDS5100H-13_POWERDI5-3~D
1 PR209
2
PQ44 PBATT+ PQ45 330K_0402_5% PQ46
SI7121DN-T1-GE3_POWERPAK8-5 FDS6679AZ_SO8~D 8 1
D S
1 1 8 7 2
S D PBATT_IN_SS D S
2 2 7 6 3 +PWR_SRC
+VCHGR S D D S
5 3 3 6 5 4
2200P_0402_25V7K
S D D G
1
4 5
1K_1206_5%
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
PR210 G D FDS6679AZ_SO8~D
PR211
1
1 2
4
0_0402_5%
@
PC188
PC189
PC196
PC197
PC198
PC199
PC200
2
2
1
PR212 PC190
1U_0603_25V6
1 2 BLK_MOSFET_GC 1U_0603_25V6
C 0_0402_5% C
1
@
PC191
2
2
@ PR214
2
+DOCK_PWR_BAR 1 2 DK_PWR_BAR PR213
0_0402_5% 0_0402_5% PR215
1 2 3301_DC_IN_SS @ 0_0402_5%
+DC_IN_SS 0_0402_5%
DSCHRG_MOSFET_GC
@
1
@ PR216
1
<52> +CHGR_DC_IN
+DC_IN 1 2 CD3301_DCIN
PR217 47_0805_5%~D
1
PC192
0.1U_0603_50V4Z
2
@ PR218
36
35
34
33
32
31
30
29
28
1 2 +5V_ALW
<44> SOFT_START_GC PU11 0_0402_5%
PR219 100K_0402_5% PR220
GPIO Input from NB
NC
CHARGERVR_DCIN
DK_PWRBAR
GND
NC
BLK_MOSFET_GC
DSCHRG_MOSFET_GC
PBatt+
DC_IN_SS
+3.3V_ALW2 1 2 1 2 SLICE_BAT_ON <39>

0_0402_5%
1 PR221 2 ACAVDK_SRC
@
1 PR222 2
Embedded Controller
<38> ACAV_DOCK_SRC# DOCK_AC_OFF <38,39>
0_0402_5% 1 27 0_0402_5%
PR224 @ DC_IN P50ALW CD_PBATT_OFF @
2 26 1 2
ERC1 SS_GC PBATT_OFF DK_AC_OFF
+SDC_IN 1 2 3 25
ERC1 DK_AC_OFF_EN 3301_ACAV_IN_NB 1M_0402_5%~D
4 24 1 PR225 2 ACAV_IN_NB <39,40,52>
@ 0_0402_5% ACAVDK_SRC ACAV_IN_NB 0_0402_5% PR223
5 23
CD3301_SDC_IN GND GND DK_AC_OFF_EN @
6 22 1 PR226 2 DOCK_AC_OFF_EC <39>
B SDC_IN DK_AC_OFF_EN SL_BAT_PRES# 0_0402_5%
B
7 21
<52> DC_BLOCK_GC ACAVIN DC_BLK_GC SL_BAT_PRES# BLKNG_MOSFET_GC @
8 20
P33ALW2 9 ACAV_IN BLKNG_MOSFET_GC
19
P33ALW2 NBDK_DCINSS
EN_DK_PWRBAR
<22,40,52> ACAV_IN 1 PR227 2

SS_DCBLK_GC
0_0402_5% PR229
DK_CSS_GC
@ 1 2 SLICE_BAT_PRES# <38,39,44>
PWR_SRC
0_0402_5%
CSS_GC
P33ALW
37 @
TP
ERC3
ERC2
1 PR228 2 1 PR230 2
GND
+3.3V_ALW2 +NBDOCK_DC_IN_SS
0_0402_5% 0_0402_5%
@ @
CD3301ARHHR QFN 36P CONTROL LOGIC
10
11
12
13
14
15
16
17
18
PR231
0.1U_0402_25V6
<52> CSS_GC P33ALW 1 2

ERC2
<52> DK_CSS_GC +3.3V_ALW

0_0402_5%
1
ERC3 @
PC193
PR233
EN_DK_PWRBAR 1 2 EN_DOCK_PWR_BAR <39>
2
0.047U_0402_25V7K
0_0402_5%
0.1U_0402_25V6
@ 1 2
PC194
STSTART_DCBLOCK_GC 1M_0402_5%~D
PC195
@ PR234
PR235
2
3301_PWRSRC 1 2 +PWR_SRC
@ 0_0402_5%
@
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Selector
5 4 3 2 1
5 4 3 2 1
+VCC_CORE
D 1 1 1 1 1 D
PC1153 PC1163 PC1164 PC1168 PC1169

2
10U_0805_4VAM~D
2
10U_0805_4VAM~D
2
10U_0805_4VAM~D
2
10U_0805_4VAM~D
2
10U_0805_4VAM~D +VCC_GFXCORE
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1
PC1111
PC1112
PC1113
PC1114
PC1115
PC1116
PC1117
PC1118
PC1170 PC1171 PC1108 PC1109 PC1110
10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
2 2 2 2 2 2 2 2 2 2 2 2 2
+1.05V_RUN_VTT
+VCC_CORE +1.05V_RUN_VTT
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1
PC1124
PC1125
PC1126
PC1127
PC1128
PC1129
PC1130
PC1131
PC1132
PC1134
PC1119 PC1120 PC1121 PC1122 PC1123
2 2 2 2 2 2 2 2 2 2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 1 1 1 1 1 1 1
2 2 2 2 2
PC1135
PC1136
PC1137
PC1138
PC1139
PC1140
PC1141
2 2 2 2 2 2 2
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1 1 1 1 1 1 1
C 1 1 1 1 1 @ @ @ C
PC1147
PC1148
PC1149
PC1150
PC1151
PC1152
PC1154
PC1143 PC1144 PC1145 PC1146 PC1101
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 2 2 2 2 2 2 2
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
2 2 2 2 2
330U 2V M D2E LESR6M

1 1
1
PC1157
PC1158
+ +
PC1500
PC1501
PC1502
PC1503
PC1504
2
2
2 2

1 1
1 1 1 1 1
PC1165
PC1166
+ +
PC1102 PC1103 PC1104 PC1105 PC1106
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2 2 2 2
1
PC1107
22U_0805_6.3VAM
2
+VCC_CORE
B B

1 1 1 1
+ + + + PC1175
PC1173
PC1174
PC1187
470U_D2_2VM_R4.5M
2 3 2 3 2 3 2 3
@
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
1
1
+
PC1400
PC1401
PC1402
PC1403
PC1404
PC1176
2
2 3 330U 2V M D2E LESR6M
A A

Title
PROCESSOR DECOUPLING
1.0
LA-7902P
5 4 3 2 1
5 4 3 2 1
V ersion Change L ist ( P. I. R . L ist ) Page 1

R equest
Item Page# Title D ate O w ner Issue D escription Solution D escription R ev.
D
1 44 Power 8/18 Compal ME design change. PJPDC1 change from 7pin to 5pin X01 D
2 45 Power 8/18 Compal Main and 2nd IC common setting. De-pop PD100,PR113,PR111 X01
3 45 Power 8/18 Compal Prevent Jitter issue. Add PC120,PC121,PC215 parallel with X01
46 PR101,PR102,PR207
PU700 VCCP and VDD change form +5V_RUN

4 51 Power 8/18 Compal Prevent output voltage glitch when power up. to +5V_ALW X01
5 53 Power 8/18 Dell Change net name PBATT to SLICE_BAT_ON. Change net name same as E4. X01
6 50 Power 8/18 Compal Reserve 0 ohm resistance for test. Add PR90, PR91 X01
C C
7 45 Power 8/30 Compal For reduce EMI radiation. Pop PL100, PL1300 X01
52
8 54 Power 8/30 Compal Reserve cap for improve transient response. Reserve PC1176 X01
9 53 Power 8/30 Compal For reduce EMI radiation. Add PC196, PC197, PC198, PC199, PC200 X01
Change PQ4, PC1153, PC1163, PC1164, PC1168,

PC1169, PC1170, PC1171, PC1108, PC1109, PC1110, X01
10 54 Power 8/31 Compal Change to green P/N. PC1187, PC1173, PC1174, PC1175, PC1157, PC1158,
PC179, PQ1310, PQ1306 to green P/N
Change 6@ to pop for PC400~PC406, PC408, PL400,

B 11 48 Power 9/1 Dell For support TL+TM PQ400, PQ405, PR400~PR407, X01 B
PU400. 5@ to @ for PR408.
12 49 Power 9/1 Compal For fix 1.05V_RUN_VTT on 1.05V Depop PR509, PR511, PQ502. X01
Change PR507 to 4.99k.
13 51 Power 9/5 Compal Follow EMI requirement. Change PL700 to SM01000DJ00 X01
14 45 Power 9/6 Compal Change to green P/N. Change PC107, PC263, PC280, PC405, X01
46 PC505 to HF P/N.
15 52 Power 9/13 Compal For reduce EMI radiation. Pop PC1400~1404, PC1500~PC1504. X01
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_PIR 1
5 4 3 2 1
5 4 3 2 1
R equest
Item Page# Title D ate O w ner Issue D escription Solution D escription R ev.
16 51 Power 9/14 Compal Adjust CPU transient , Add PC740 to 0.1uF X01
D loadline and OCP Change PR750 to 365 ohm
D
Change PR741 to 130K ohm

Change PC744 to 3300pF,PR754 to 649ohm.
17 51 Power 9/14 Compal Adjust AXG transient , Change PR703 to 130K ohm X01
loadline and OCP Change PC709 to 82nF
Change PR702 to 2.74K ohm
Change PR711 to 383 ohm
18 52 Power 11/17 Compal Shortage issue Change PQ1303 from NTGD416 to AP2623 X02
19 52 Power 11/17 Compal Need ESD protected Change PQ1306, PQ1310 from SB57002040L X02
C
to SB000009Q80 C
20 53 Power 11/17 Compal IC version upgrade Change PU11 from CD3301 to CD3301A X02
21 45 Power 11/17 Compal Shortage issue Change PC110, PC111 from SGA00004E00 X02
to SGA00002N80
22 45 Power 11/17 Compal EMI request Pop PC1138,PC1139,PC1149,PC1150 X02
23 44 Power 11/21 Compal Erp lot6 tier2 Fail issue PWR_SRC_S control signal change from +3.3V_ALW X02
to PCH_ALW_ON
24 44 Power 12/05 Compal Prevent COS. Change PD8 from SCS0340L01L to SCS00005C00 X02
Change PD1301 from SCS00003M0L to SCS00004O0L
Change PC1176,PC1174,PC1173,PC1187,PC1157,PC1158, X02

B B
25 54 Power 12/13 Compal Prevent COS.
PC1165,PC1166 to SGA00002U1L
26 50 Power 12/13 Compal Improve efficiency change PR86 to 22K_0402_5% X02
27 47 Power 12/16 Compal Prevent COS. Change PL301 from SH00000MN00 to SH00000MW00 X02
A A
Title
PWR_PIR 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-7902P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Friday, March 02, 2012 Sheet 56 of 61
5 4 3 2 1
5 4 3 2 1
R equest
Item Page# Title D ate Issue D escription Solution D escription R ev.
O w ner
1 11 HW 08/25/2011 COMPAL INTEL review feedback Add CC178,CC179,CC149,CC150 X01
2 HW 08/25/2011 COMPAL Leave LDRQ0# no connection on both of 5048 and PCH side X01
D 14,39 SMSC request to delete LPC_LDRQ0# D
Removed R743
X01
3 22 HW 08/25/2011 COMPAL Removed reserve circuit for EMC4022 Removed R405,C280,R392,R394
4 Load SW sources output rising time Change back to E3 +3.3V/5V_RUN discrete solution
42 HW COMPAL X01
08/25/2011 mismatch and COS. cost concern Removed U78 and add Q55,Q61 circuit
5 29 HW 08/25/2011 COMPAL Codec is change to 92HD93 Pop R162~R166 and de-pop U73,R1540 X01
Pop option for 92HD93/ALC290=>R1646/C1164; R1644/R1643;

C965/R1642; Q107/R171
6 29 HW 08/25/2011 COMPAL Reserve co-lay with ALC290 Reserve for ALC290 only: C1204, C1205, R1647, C1165, R1648 X01
Reserve for 92HD93 only: R1645, C963
Add R174 depop and R175 pop
C C
7 20 HW 08/25/2011 COMPAL Vgs less than cut-in voltage in battery mode Add control circuit QH6,R279,CH107 for +5V_ALW_PCH X01
8 27,28 HW 08/25/2011 COMPAL Vgs of 5V MOS maybe large than max rating Add R517, R518 X01
9 11 HW 08/25/2011 COMPAL Follow INTEL PDDG 0.8 De-pop RC140 X01
10 40 HW 08/25/2011 COMPAL Change board ID to X01 Change R875 to 130Kohms X01
11 34 HW 08/25/2011 COMPAL PCH GPIO52 need 8.2~10K pull up +3.3VS Change R695 from 100K to 10Kohms X01
12 23 HW 08/25/2011 COMPAL CRT SW 2nd source TI, TS3V713 pin29 is VDD Connect U18 pin29 to +3.3V_RUN X01
13 HW 08/25/2011 COMPAL +1.05V_M turn off before APWROK de-assert Add UH5,CH108 6@ circuit reserve for VPRO X01
16
B 14 HW COMPAL Reset IC threshold voltage issue Change U4 to RT9801A (threshold adjustable) X01 B
41 08/25/2011
Add R1649~R1654;Reserve R1655 and pop R1623
15 26 HW 08/25/2011 COMPAL DPX_CA_DET voltage too low through dongle Change U21 and U24 to SA000055G0L X01
16 17,18 HW 08/25/2011 COMPAL Request from INTEL review feedback Pop RH332 for PCH_GPIO3 and RH180 for GPIO27 X01
17 HW 08/25/2011 COMPAL Material changed Power team request Q59 change to SB00000L80L X01
42
18 HW 08/25/2011 COMPAL White light LED brightness is abnormal Change R934, R938, R939, R949, R958, R957 and R959 X01
43
to 1.2 Kohms
19 40 HW 08/25/2011 COMPAL Reserve C1208 for ESD backup plan Reserve C1208 for ESD backup plan X01
20 11 HW 08/25/2011 COMPAL S3 can't resume issue Control 1.5V_VDDQ by EC. Pop RC79 and de-pop RC82 X01
21 17 HW 08/25/2011 COMPAL INTEL review feedback Change RH331,RH272 to 10K ohm X01
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT HW_PIR 1
5 4 3 2 1
5 4 3 2 1
R equest
O w ner
22 34 HW 08/25/2011 COMPAL WWAN card request JMINI1 pin 1 connect to PCIE_WAKE# X01
D 23 14 HW 08/25/2011 COMPAL ROM size changed Change U52 to 8M and R936,R895,R897,R900 to 6@ X01 D
24 11 HW 08/25/2011 COMPAL Material package changed Change CC161~CC166 from 0402 to 0603 X01
25 42 HW 08/25/2011 COMPAL BOM changed Change Q60 to 6@ X01
26 39 HW 08/25/2011 COMPAL GPIO signal name changed same as E/P Change PBATT_OFF to SLICE_BAT_ON X01
27 34 HW 08/25/2011 COMPAL Material package changed Changed C615 to SF000002000 X01
28 30 HW 08/26/2011 COMPAL LAN EA result Changed RL23 to 1.2K Ohm. X01
29 40 HW 08/26/2011 COMPAL Backdrive issue Depop R1169,R1197,R118 due to it has internal pull high. X01
30 37 HW 08/29/2011 COMPAL To avoid power short to GND NC Pin 15 for JAUD1 X01
C 31 37 HW 08/30/2011 COMPAL Follow connector list Swap JAUD1 pin. X01 C
32 12 HW 08/30/2011 COMPAL Change part to HF part Change QD1, QD2 part number to SB501380050 (for HF) X01
33 15 HW 09/01/2011 COMPAL For clock EA Change RH311 and RH314 to 10 ohm X01
34 43 HW 09/01/2011 COMPAL ME drawing update Add H19 X01
Change U53,R936,R895,R897,R900,RH350,UH5,CH108,RH116
14,16
RH202,R385,R426,R402,Q63,R931,Q58,Q60
19,22 X01
35 HW 09/01/2011 COMPAL BOM option change for TL R916,RL46,R871 to pop
30,40
Change RH359,RH321,RH119,RH204,R430,R386,R408
42
,R206,RL47,R877,to depop
Chamge resistor to Inductor

Change R451, R459, R462, R466, R468, R469, R470, R471 to
36 25 HW 09/02/2011 COMPAL Due to EMI HDMI test Fail, add EMI solution
B 9nH L99, L100, L101, L102, L103, L104, L105, L106. X01 B
Add C1209, C1210, C1211, C1212, C1213, C1214, C1215

and C1216 between Inductor and HDMI connector
37 37 HW 09/05/2011 COMPAL ME connector list change Change JAU1 to 50271-0020N-001 X01
38 37 HW 09/06/2011 COMPAL EMI issue Add L107 & R1656,R1657 X01
X01
39 15,30 HW 09/06/2011 COMPAL Follow LL to reserve SM bus for BRCM LAN Add QH8,RL50,RL51
40 36 HW 09/08/2011 COMPAL Follow Intel design guide Change C412~C415 to 0.1uF for USB3.0 signal X01
41 7 HW 09/08/2011 COMPAL Follow ESD recommand. Reserve CC1141~CC144 for ESD

X01
Change CH2,CH3 to 18pF
42 14,15,40 HW 09/08/2011 COMPAL Crystal EA result Change C741,C743 to 39pF
A A
Change CH18,CH19 to 10pF X01
Change CL5,CL6=33pF,RL22=510 ohm
Title
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5 4 3 2 1
R equest
O w ner
43 29 HW 09/13/2011 COMPAL Follow IDT recommand Swap R169~R172,C973~C976 connection X01
Change Q55,Q61 part for open soldering

44 42 HW 09/13/2011 COMPAL Change Q55,Q61 from DMN3030LSS-13 to AO4478L X01
D issue. D
45 40 HW 10/13/2011 COMPAL Change board ID to X02 Change R875 to 62Kohm X02
46 42 HW 10/13/2011 COMPAL Rated Vgs of Q61 is 25V De-pop R1627 X02
47 39 HW 10/13/2011 COMPAL SMSC change 5048 pin A23 to GPIOI0 Re-link ECE 5048 symbol X02
48 40 HW 10/13/2011 COMPAL SMSC review feedback Reserve R1658 and R1659 100Kohms to GND for I2S disabled X02
Update U4 symbol and add R1629 for backup of inrush

prevention.
49 41 HW 10/13/2011 COMPAL Change reset IC to RT9818A-44GU3 Change RSMRST# pull up with 100Koms. Pop R1655 and de-pop X02
R1623.Delete R1649~R1654
C C
When suspend/resume cycles, wireless SW

50 39 HW 10/13/2011 COMPAL Change pull up rail to +3.3V_ALW for WIRELESS_ON#/OFF X02
GPIO IRQs keeps giving
Pop snubber on speaker trace with C: 2200pF and R: 3.3ohms.

51 29 HW 10/13/2011 COMPAL 15" UMA speaker no sound issue X02
Change bead rated current from 200mA to 2A.
52 29 HW 10/13/2011 COMPAL EMI request Pop C981,C982,C983,C985,C986,C987 X02
53 27 HW 10/13/2011 COMPAL Depop HDD control power circuit for cost down. Depop R1624,Q28,R500,R499,R617,C393 X02
54 30 HW 10/18/2011 COMPAL Crystal EA result Change YL1 to 3G025000FA1H, CL5,CL6 to 12pF.RL22 to 200 ohm. X02
55 All HW 10/18/2011 COMPAL For cost saving. Change 0 ohm to R-short. X02
B B
56 42 HW 10/26/2011 COMPAL 1V leakage on 3.3V_RUN during system boot Pop Q69 and R929 X02
Inrush current with Smart Card

57 42 HW 10/26/2011 COMPAL change C763 and C766 to 2200p X02
detect fail issue
58 43 HW 10/27/2011 COMPAL LED Conn PIN definition change JLED1 PIN define change X02
59 37 HW 10/27/2011 COMPAL Remove 2pin connector for Audio performance Remove JAG1 2 pin connector. X02
Change MOSFET to wihtout Schottky Diode for

60 42 HW 11/01/2011 COMPAL change QC3, Q59 as AO4304L from AO4728L X02
+1.5V_RUN leakage issue
61 14 HW 11/15/2011 COMPAL RTC issue change CH2, CH3 to 15pF X02
62 14 HW 11/15/2011 COMPAL S5 power consumption over spec. depop RH288 X02

A A
Title
5 4 3 2 1
5 4 3 2 1
R equest
O w ner
De-pop R725, remove R695 and add +3.3V_RUN
63 34 HW 11/29/2011 COMPAL S3 had leakage in +3/5V_RUN X02
pull high at PCH side(RH361)
U39(TPM) is changed to SA00004WQ10

D 64 32 HW 11/29/2011 COMPAL TPM is changed to AT97SC3204-X2A18-AB X02 D
(AT97SC3204-X2A18-AB) for WIN8 support
Add D87, R1662 and R1663 (pull high to +3.3V_RUN_TPM)

65 32 HW 11/29/2011 COMPAL +3.3V_RUN Giltch when AC plugin X02
for HW solution backup
66 14~21 HW 11/29/2011 COMPAL Change PCH to C1 version Change UH4 to SA00005AG1L(HM77 for non vpro) X02
RC72 from 100K to 330K; RC143 form 330K to 1M; CC136 form 0.1u to 0.022u
Change RC value at Gate of MOS R412 from 100K to 470K; R1632 form 1M to 4.7M; C293 form 0.1u to 0.022u
67 HW 11/29/2011 COMPAL X02
Load SW to modify power rail R507 from 100K to 470K; R517 form 1M to 4.7M; C400 form 0.1u to 0.022u
soft start timing R722 from 100K to 470K; R1625 form 1M to 4.7M; C644 form 4700p to 220p
R729 from 100K to 470K; R1628 form 1M to 4.7M; C650 form 4700p to 220p
R917 from 100K to 470K; R1617 form 1M to 4.7M; C770 form 4700p to 220p
R920 from 100K to 470K; R1610 form 470K to 2.2M; C771 form 4700p to 470p
R930 from 100K to 330K; R1611 form 470K to 1M; C773 form 2200p to 100p
R906 from 100K to 470K; C763 form 2200p to 220p
C R912 from 100K to 470K; C766 form 470p to 220p C
68 36 HW 12/01/2011 COMPAL Change P/N for HF Change C412~C415 P/N to SE076104K8L X02
69 35 HW 12/01/2011 COMPAL Reserve 0.1uF CAP to GND for ESD request reserve CE14, CE20, CE22, CC151, CC152, CC153 to GND X02
70 19 HW 12/05/2011 COMPAL Change LH1 from bead to Inductor for CRT Change LH1 to 1uH Inductor(SHI00007W0L) X02
Swap USB Port7 and Port8 and reserve a choke(L108)

at E-Docking side:
71 17,38 HW 12/07/2011 COMPAL EMI solution for E-Docking USB port X02
Port7 from NA to E-docking
Port8 from E-Docking to NA
Change USB9,12,13 CMC to 180ohm

72 24,32,37 HW 12/07/2011 COMPAL Change L10,L52,L107 to SM070002X00(OCF2012181YZF) X02
for EMI request
B B
Follow CONN List_1130A
73 37 HW 12/08/2011 COMPAL Change JAUD1 to ACES_51522-0200N-P01 X02
Change JAUD1 to ACES_51522-0200N-P01
Thermal requests to change OTP

74 22 HW 12/09/2011 COMPAL Change R406 from 953ohm to 1.24Kohm X02
from 88 to 92
75 41 HW 12/09/2011 COMPAL To prevent inrush current at reset IC input Change R1629 from 0ohms to 33ohms resistor X02
76 19 HW 12/09/2011 COMPAL For CRT issue Change CH36 from 10uF to 22uF X02
Change R448,R449,R450,R452,R453,R454,R455,R456
77 25 HW 12/13/2011 COMPAL Change HDMI R,C value for EMI request X02
from 680ohm to 604ohm; C1209~C1216 from 4.7pF to 3.9pF
78 42 HW 12/15/2011 COMPAL +3.3V_SUS sequence timing R911 from 100K to 470K; R1618 from 1M to 4.7M;
X02
C767 from 4700p to 220p
R934 from 1.2K to 820, R957 from 1.2K to 1K, R951 from 330 to 270,
79 43 HW 12/15/2011 COMPAL Change current limit resistors of LED X02
A R949 from 1.2K to 910, A
Title
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5 4 3 2 1
R equest
O w ner
80 34 HW 01/04/2012 COMPAL Change RC25 value for ESD Change RC25 from 0ohm to 1kohm(ST MEMO) A00
SMSC creates a new catalog part number and

D 81 40 HW 01/17/2012 COMPAL Change U51 P/N to SA00003TZ2L A00 D
IC marking for the MEC5055
Change R938 to 1.1k ohm, R958 to 560 ohm, R953 to 130 ohm,
82 43 HW 02/20/2012 COMPAL Change current limit resistors of LED R951 to 470 ohm, A00
change R939, R959, R957, R934, R949 to 1.2k ohm
Dalmore14 UMA hang on white screen issue

83 38 HW 02/24/2012 COMPAL when attached AC+media battery after hot Change R755 from 100k ohm to 10k ohm A00
dock.
84 40 HW 02/24/2012 COMPAL Change board ID to A00 Change R875 to 33K ohm A00
Change SD CLK damping resistor for EMI

85 33 HW 02/24/2012 COMPAL Change R676 from 33 ohm to 10 ohm A00
request
C C
Change C550,C551,C552,C553,R659,R660,R1662,RH311
86 32 HW 02/24/2012 COMPAL Change BOM option for TPM/TCM funtion A00
BOM option to 5@
For DFX conern of F2 2nd source, SP040003H0L,

87 25 HW 03/03/2012 COMPAL SMT request to change F2 footprint A00
change F2 footprint to F_MF-MSMF050-2
88 14~21,30 HW 03/03/2012 COMPAL Change PCH P/N for X-build UH4 is changed to SA00005AG3L A00
89 14 HW 03/03/2012 COMPAL De-pop resistor on PCH JTAG for power saving De-pop RH288, RH47, RH48 and RH49 A00
B B
A A
Title
5 4 3 2 1
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Compal La-7901p r1.0 Schematics

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A B C D E

BOM P/N : 4619F631L01 / L02

Korbel 14 UMA--Non vPRO

HM77 w/o Vpro

PCH XDP PXDP@

HDMI LOGO 46@

FDI x8 DMI Gen 2x 4 USB port 12

LVDS CONN LVDS Fingerprint

DC/DC Interface TP CONN KB CONN USB3.0 [4]

Lane 5 1/2vMINI CARD-3 PCIE

Port B MB HDMI Conn Lane 6 MMI

Lane 7 10/100/1G LOM

(Q38) (Q49) (Q54) (Q34) (U78) (Q58)

+VCC_CORE +1.05V_RUN_VTT +1.05V_M SIO_SLP_S3#

SI4164 Pop option

+1.5V_CPU_VDDQ +1.5V_RUN +0.75V_DDR_VTT

LAN_APE_SMB_CLK0 L10 BCM LOM SMBUS Address [**]

MEC 5055 2.2K

PCI EXPRESS* - GRAPHICS

<16> FDI_CTX_PRX_P0 FDI_CTX_PRX_P0 A22 FDI0_TX[0]

+1.05V_RUN_VTT +1.05V_RUN_VTT TYCO_2134146-3_IVYBRIDGE~D

DP Compensation PEG Compensation

- typical impedance = 14.5 mohms

Follow DG Rev0.71 SM_DRAMPWROK topology +1.05V_RUN_VTT

<39> CPU_DETECT# AN34

<16> H_PM_SYNC PM_SYNC TRST# <40> DDR_HVREF_RST_GATE DDR_HVREF_RST <12>

Buffered reset to CPU Place closed JCPU1 VCCPWRGOOD_0_R

AB6 M_CLK_DDR0 AE2 M_CLK_DDR2

DDR SYSTEM MEMORY B

DDR_A_D32 AG6 AH2 DDR_B_D32 AM5 AE5

CFG Straps for Processor

PEG Static Lane Reversal - CFG2 is for the 16x

AH27 @ T39 PAD~D CFG4

0 : Enabled; An external Display Port device is

VSSAXG_VAL_SENSE VAXG_VAL_SENSE RSVD39 @ T16 PAD~D

PAD~D T30 @ F23

PAD~D T31 @ D24 B34 @ T23 PAD~D

PAD~D T33 @ G25 A33 @ T24 PAD~D

PAD~D T38 @ RSVD15 RSVD_NCTF10

PAD~D T52 @ J15 AT2 @ T49 PAD~D CFG7

PEG AND DDR

AT35 VSS1 VSS81 AJ22

VAXG24 CC149 VSS37 VSS118

AM23 VAXG26 VDDQ2 AF4 AN19 VSS39 VSS120 AE26

@ RC97 1K_0402_1%~D AJ17 M27 1 1 1 1 1 AL22 Y5

VCCSA_SENSE H23 VCCSA_SENSE <50> AK19 VSS74 VSS155 U9

1 1 1 1 A2 VCCPLL3 VCCSA_VID[1] C24 VCCSA_VID_1 <50> AK4 VSS79 VSS160 U2

All VREF traces should

DDR_A_D48 163 164 DDR_A_D52

DDR_A_DQS#6 169 170

+0.75V_DDR_VTT 203 VTT1 VTT2 204 +0.75V_DDR_VTT

105 VDD VDD 106

1 DDR_B_BS0 109 110 DDR_B_RAS#

+ DDR_B_WE# 113 114

DDR_B_D50 175 176 DDR_B_D55

DDR_B_D56 181 182 DDR_B_D61

DIMM2_SA1 201 202

2 1 DIMM2_SA0 Link CIS DELL CONFIDENTIAL/PROPRIETARY

<17> USB_OC5# USB_OC6# PXDP@ RH8 33_0402_5%~D XDP_FN6 OBSFN_B0 OBSFN_D0

BBS_BIT0_R PXDP@ RH14 1 2 33_0402_5%~D XDP_FN11 XDP_FN6 33 34 XDP_FN14

<18> PCH_GPIO16 TEMP_ALERT# PXDP@ RH18 33_0402_5%~D XDP_FN15 PWRGOOD/HOOK0 ITPCLK/HOOK4

1.1V VRM Enable PCH_AZ_SYNC is sampled <7,12,13,15,27,34> DDR_XDP_WAN_SMBCLK

1 2 1 2 27P_0402_50V8J~D AM3 SPKR @ RH35 2 1 10K_0402_5%~D