Dell Latitude E7240 - Compal LA-9431P

A B C D E
COMPAL CONFIDENTIAL
MODEL NAME : VAZ50
m
1 1
PCB NO : LA-9431P (DAA00005Z10)
co
BOM P/N : 4319LL31LXX
a.
GPIO MAP: 3.0C
si
ne
2
Goliad 12" 2
do
Haswell ULT
In
2013-05-17
REV : 1.0 (A00)
i-
@ : Nopop Component
1@ : M/B 8M SPI ROM Component
SPI on MB TAA
is
3 2@ : TAA/B 8M SPI ROM 3
EMC@ : EMI & ESD & RF Component Vpro 1@/4@/EMC@/ 2@/5@/EMC@

XDP@ : XDP Component
kn
3@/EMC_3@ 3@/EMC_3@
CONN@ : Connector Component
3@ : Delete componet for cost down BOM non-Vpro 1@/EMC@/ 2@/5@/EMC@
Te
3@/EMC_3@ 3@/EMC_3@
EMC_3@ : Delete EMC component for cost down BOM
4@ : M/B 4M SPI ROM Component non-Vpro
w.
5@ : TAA/B 4M SPI ROM (cost down) 1@/EMC@ 2@/5@/EMC@/

7@ : M/B for 8M SPI(Reverse)
ww
4 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
MB PCB PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Part Number Description BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Cover Sheet
DAA00005Z10 PCB 0VM LA-9431P REV1 M/B 4 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.3
LA-9431P
Date: Friday, May 17, 2013 Sheet 1 of 59
A B C D E
A B C D E
Goliad12 Block Diagram
Memory BUS (DDR3L)

1333/1600MHz DDRIII-DIMM X2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
eDP CONN eDP
m
1 REV. type 1
PAGE 22
co
PAGE 18 19
DP
Mini-DP
PAGE 27 USB2.0[3] Camera
PAGE 22
Trough eDP Cable
a.
DP INTEL
For MB/Dock Pericom DDI2
DOCKED_LIO_EN
DP Video Switch PI3VDP12412 HASWELL SLGC55594A
DP
IDT VMM2320 PAGE 27
ULT
VGA PAGE 21 NX3DV221 SW_USB2.0[0] USB POWER SHARE
USB2.0[0] PAGE 33
USB20 Switch
si
PAGE 33
BGA CPU USB DOCKED DOCK _USB2.0[0] USB3.0/2.0+PS

USB3.0[2]
DOCKING HDMI Reduce Level DDI1 PAGE 33
HDMI CONN
ne
ShifterPAGE 23 SW_USB2.0[5]
PORT PAGE 23
PAGE 34
USB2.0[5] PI3USB3102 SW_USB3.0[3] USB3.0/2.0
PAGE 33
2
USB3.0[3]
USB3&2 Switch 2
PAGE 32 DOCK _USB2.0[5]

DAI
DOCK_USB3.0[3]
DOCK_USB3.0[3]
do
PAGE 6~17
SATA1 USB2.0[1]
DOCK_USB2.0[0] Card reader USB3.0/2.0
SD4.0 PCIE5_L0 USB3.0[1] PAGE 35
DOCK_USB2.0[5] O2 Micro OZ777FJ2LN
PAGE 30 PAGE 30 IO/B
In
PCI Express BUS HD Audio I/F PAGE 20
Near Field
SPI
SATA0
PCIE3 PCIE4 PCIE6_L0 USB2.0[7] Communications con
i-
Intel Clarkville WLAN+BT/ Full Mini Card Discrete TPM Full Mini Card INT.Speaker
I218LM 60GHz WWAN+mSATA AT97SC3204 W25Q64FVSSIQ HDA Codec
PAGE 28 PAGE 31 PAGE 31
PAGE 29 mSATA PAGE 25 PAGE 26
ALC3226
is 64M 4K sector
3
USB2.0[2] USB2.0[6] PAGE 26 Vol bottom SW 3
LAN SWITCH SATA2 W25Q32FVSSIQ Combo Jack PAGE 40

Touch Screen
LPC
PI3L720
PAGE 28
Conn
kn
32M 4K sector PAGE 7 CPU XDP Port

DAI PAGE 9
PAGE 22 To Docking side
Transformer Smart Card TDA8034HN USH Trough eDP Cable Automatic Power
PAGE 35 BCM5882 SMSC SIO
Dig. Switch (APS) PAGE 9
Te
RFID ECE5048
MIC
Fingerprint FP_USB USB2.0[4]
PAGE 36
PAGE 22 WiFi ON/OFF
RJ45 CONN PAGE 35
PAGE 35 Trough eDP Cable IO/B
PAGE 29 USH board
w.
SMSC KBC DC/DC Interface

BC BUS PAGE 39
FAN CONN MEC5075
PAGE 37 PAGE 37
Power On/Off
ww
4 4
KB and TP CONN SW & LED PAGE 40

PAGE 38
Title
Block Diagram
Size Document Number Rev
0.3
LA-9431P
A B C D E
5 4 3 2 1
POWER STATES
Signal SLP SLP SLP SLP ALWAYS M SUS RUN CLOCKS PCIE USB3.0 SATA DESTINATION
State S3# S4# S5# A# PLANE PLANE PLANE PLANE
USB3.0 1 JUSB3-->Right
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON
USB3.0 2 JUSB1-->Rear left
m
D D
S3 (Suspend to RAM) / M3 LOW HIGH HIGH HIGH ON ON ON OFF OFF
PCIE 1 USB3.0 3 JUSB2-->Rear Right//DOCK
co
S4 (Suspend to DISK) / M3 LOW LOW HIGH HIGH ON ON OFF OFF OFF
PCIE 2
S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF
PCIE 3 LOM
a.
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON OFF ON OFF OFF
PCIE 4 WLAN (WiGi)
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF
PCIE 5 MMI (CARD READER)
si
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF
PCIE 6 SATA 3 WWAN(PP/mSATA)
SATA 2 NA
PM TABLE
ne
+5V_ALW +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M SATA 1 mSATA
C C
+3.3V_ALW +1.35V_MEM +3.3V_RUN +1.05V_M +1.05V_M
+3.3V_ALW_PCH +0.675V_DDR_VTT (M-OFF) SATA 0 DOCK
power
+3.3V_RTC_LDO +1.05V_RUN
do
plane
+VCC_CORE
USB PORT# DESTINATION
0 JUSB1 // E-Dock 1
In
State
1 JUSB3
S0 ON ON ON ON ON
2 WLAN + BT
i-
S3 ON ON OFF ON OFF HSW
3 CAMERA
ULT
S5 S4/AC ON OFF OFF ON OFF
4 USH->SMART CARD
S5 S4/AC don't exist OFF OFF OFF OFF OFF
is
B B
5 JUSB2 // E-Dock 2
need to update Power Status and
PM Table 6 WWAN
kn
7 TOUCH
0 BIO
Te
USH
1 NA
w.
ww
A A
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Index and Config.
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-9431P
5 4 3 2 1
5 4 3 2 1
A_ON
+1.05V_RUN +3.3V_RUN
PWRSHARE_EN# ESATA_USB_PWR_EN#
USB_SIDE_EN#
TPS51212
(PU300) G547I2P81U G547I2P81U G547I2P81U
DOCKED
(U35) (U32) (U52)
m
D D
co
ADAPTER +1.05V_M
TPS22966 +5V_USB_
+USB_PWR +USB_SIDE_PWR
(U31) CHG_PWR
MPHYP_PWR_EN
a.
SI3456DDV
(Q125)
+1.05V_RUN_VMM +3.3V_RUN_VMM
BATTERY +PWR_SRC
si
EN_INVPWR FDC654P +1.05V_MODPHY
+BL_PWR_SRC
(Q2)
ne
ALWON
C TPS51285BRUKR C
+5V_ALW
CHARGER (PU100)
do
PCH_ALW_ON
+3.3V_ALW
MCARD_WWAN_PWREN
In
RUN_ON
AUX_EN_WOWL
SIO_SLP_LAN#
ENVDD_PCH
3.3V_HDD_EN
RUN_ON
RUN_ON
RUN_ON
RUN_ON
TPS22966
SUS_ON
i-
(U43)
A_ON
TPS51622 RT8207
(PU500) (PU11)
TPS22966 TPS22966 TPS22966 TPS22966 APL3512A TPS22966 TPS22966
(U45)
is (U22) (U22) (U3) (U9) (U46) (U18)
H_VR_EN
B B
SUS_ON
+3.3V_ALW_PCH
0.675V_DDR_VTT_ON
kn
+VCC_CORE +1.35V_MEM +5V_RUN +3.3V_RUN

_AUDIO _AUDIO
+3.3V_M +3.3V_LAN +3.3V_WLAN
Te
+3.3V_RUN +5V_RUN +1.05V_RUN
3.3V_CAM_EN
3.3V_TS_EN
w.
+3.3V_mSATA_WWAN
+0.675V_DDR_VTT +3.3V_SUS +3.3V_HDD +LCDVDD
LP2301ALT1G
+3.3V_TSP
(Q1)
ww
A A
LP2301ALT1G
+3.3V_CAM
(Q3) DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Rail
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
LA-9431P
5 4 3 2 1
5 4 3 2 1
2.2K
SMBUS Address [0x9a]
2.2K
+3.3V_ALW_PCH
AP2 MEM_SMBCLK 202
MEM_SMBDATA
2N7002
AH1 200 DIMMA
2N7002
1K
202
PCH
m
D
1K
+3.3V_ALW_PCH 200 DIMMB D
SML0CLK 0ohm LAN_SMBCLK 28
co
AN1
SML0DATA 0ohm LAN_SMBDATA 31 LOM
AK1
AH3 AU3 53
51
XDP
2.2K
SML1_SMBDATA
+3.3V_ALW_PCH
a.
SML1_SMBCLK 2.2K
0ohm depop NFC_SMBCLK
A5 B6 2.2K 0ohm depop NFC_SMBDATA NFC
3A 3A
2.2K +3.3V_ALW
si
B4 DOCK_SMB_CLK 127
1A
129 DOCKING
1A A3 DOCK_SMB_DAT
30
ne
2.2K 32 WWAN
C
+3.3V_ALW C
2.2K
B5 LCD_SMBCLK
do
1B
A4 LCD_SMBDAT
1B
2.2K
KBC
In
+3.3V_ALW
2.2K
100 ohm 7
1C A56 PBAT_SMBCLK
6 BATTERY
1C B59 PBAT_SMBDAT 100 ohm
CONN
2.2K
i-
+3.3V_SUS
2.2K
A50 M9
1E USH_SMBCLK
B53 L9 USH
1E USH_SMBDAT
is
B B
2.2K
+3.3V_ALW
2.2K
MEC 5075
kn
2B A49 CARD_SMBCLK
2B B52 CARD_SMBDAT
10K
+3.3V_ALW
10K
Te
B50 9
1G CHARGER_SMBCLK
A47 8 Charger
1G CHARGER_SMBDAT
w.
2.2K
+3.3V_ALW
2.2K
2D B7 BAY_SMBDAT
ww
A
2D A7 BAY_SMBCLK A
2.2K
+3.3V_ALW
2.2K
2A B7 GPU_SMBDAT Compal Electronics, Inc.
Title
2A A7 GPU_SMBCLK SMBUS TOPOLOGY

0.3
LA-9431P
5 4 3 2 1
5 4 3 2 1
+RTC_CELL
330K_0402_1%
1
RC1
2 PCH_INTVRMEN
330K_0402_1%
1
m
@ RC2
D D
+3.3V_ALW_PCH
2
1 2 PCH_AZ_SDOUT
co
@ RC3 1K_0402_5%
INTVRMEN - INTEGRATED SUS 1.05V VRM FLASH DESCRIPTOR SECURITY OVERRIDE

ENABLE LOW = ENABLE (DEFAULT)
High - Enable Internal VRs HIGH = DISABLE
Low - Enable External VRs
a.
si
CC1 1 2 PCH_RTCX1_R 1 2 PCH_RTCX1
@ RC4 0_0402_5%
10M_0402_5%
15P_0402_50V8J
1
YC1
ne
RC5
HASWELL_MCP_E
UC1E
2
C 32.768KHZ_12.5PF_Q13FC135000040 C
2
AW5
CC2 1 215P_0402_50V8J PCH_RTCX2 AY5 RTCX1
1 2 INTRUDER# AU6 RTCX2 J5
INTRUDER RTC SATA_RN0/PERN6_L3 SATA_PRX_DKTX_N0_C <34>
RC7 1M_0402_5% PCH_INTVRMEN AV7 H5
INTVRMEN SATA_RP0/PERP6_L3 SATA_PRX_DKTX_P0_C <34>
+RTC_CELL
1 2 SRTCRST# AV6 B15 DOCK
RC8 1 220K_0402_5% PCH_RTCRST# AU7 SRTCRST SATA_TN0/PETN6_L3 A15 SATA_PTX_DKRX_N0_C <34>
do
RC6 20K_0402_5% RTCRST SATA_TP0/PETP6_L3 SATA_PTX_DKRX_P0_C <34>
CMOS_CLR1 CMOS setting J8
<9> PCH_RTCRST# SATA_RN1/PERN6_L2 SATA_PRX_DTX_N1_C <25>
Shunt Clear CMOS H8
SATA_RP1/PERP6_L2 SATA_PRX_DTX_P1_C <25>
1 2 1 2 A17 SATA HDD (for Goliad 12 to MSATA)
1 2 1 2 SATA_TN1/PETN6_L2 B17 SATA_PTX_DRX_N1_C <25>
Open Keep CMOS SATA_TP1/PETP6_L2 SATA_PTX_DRX_P1_C <25>
PCH_AZ_BITCLK AW8 J6
@ @ PCH_AZ_SYNC AV11 HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6
ME_CLR1 TPM setting ME1 SHORT PADS~D CMOS1 SHORT PADS~D PCH_AZ_RST# AU8 HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 B14
1 2 1 2 PCH_AZ_CODEC_SDIN0 AY10 HDA_RST/I2S_MCLK SATA_TN2/PETN6_L1 C15
Shunt Clear ME RTC Registers
In
1U_0402_6.3V6K <26> PCH_AZ_CODEC_SDIN0 HDA_SDI0/I2S0_RXD AUDIO SATA SATA_TP2/PETP6_L1
CC3 1U_0402_6.3V6K CC4 AU12
1 2 PCH_AZ_SDOUT AU11 HDA_SDI1/I2S1_RXD F5
Open Keep ME RTC Registers CMOS place near DIMM <36> ME_FWP
RC9 1K_0402_5% AW10 HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0 E5
SATA_PRX_mSATATX_N3 <31>
HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 SATA_PRX_mSATATX_P3 <31>
AV10 C17 mSATA HDD(for WWAN card)
AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17 SATA_PTX_mSATARX_N3 <31>
I2S1_SCLK SATA_TP3/PETP6_L0 SATA_PTX_mSATARX_P3 <31>
PCH Rx side need use strap pin to update PCIE +/-
V1 MPCIE_RST#
SATA0GP/GPIO34 U1 HDD_DET# MPCIE_RST# <31,7>
SATA1GP/GPIO35 HDD_DET# <25>
V6 PCH_GPIO36
i-
+1.05V_M SATA2GP/GPIO36 AC1 mCARD_PCIE_SATA# PCH_GPIO36 <10> +3.3V_RUN
SATA3GP/GPIO37 mCARD_PCIE_SATA# <36>
<9> PCH_JTAG_TRST# PCH_JTAG_TRST# AU62
PCH_TRST
1
0_0603_5%
@ <9> PCH_JTAG_TCK PCH_JTAG_TCK AE62 A12 SATA_IREF 2 1 +PCH_ASATA3PLL HDD_DET# 1 2

PCH_TCK SATA_IREF
RC16
<9> PCH_JTAG_TDI PCH_JTAG_TDI AD61 L11 @ RC14 0_0402_5% 100K_0402_5% RC11

PCH_JTAG_TDO AE61 PCH_TDI RSVD K10 PAD~D T1 @ mCARD_PCIE_SATA# 1 2
<9> PCH_JTAG_TDO PCH_TDO JTAG RSVD PAD~D T2 @
<9> PCH_JTAG_TMS PCH_JTAG_TMS AD62 C12 SATA_COMP 10K_0402_5% RC12
AL11 PCH_TMS SATA_RCOMP U3 SATA_ACT#
@ T3 PAD~D
2
AC4 RSVD SATALED SATA_ACT# <40>

@ T4 PAD~D RSVD
<9> PCH_JTAG_JTAGX PCH_JTAG_JTAGX AE63
+1.05V_M_JTAG2 1 PCH_JTAG_TDI AV2 JTAGX
@ T5 PAD~D
B
RC17
2
51_0402_1%
1
is RSVD B
PCH_JTAG_TDO
RC18 51_0402_1% SATA Impedance Compensation
5 OF 19 Rev1p2
2 1 PCH_JTAG_TMS +PCH_ASATA3PLL
RC20 51_0402_1%
SATA_COMP 1 2
2 1 PCH_JTAG_JTAGX RC19 3.01K_0402_1%
@ RC10 1K_0402_1%
kn
CAD note:
2 1
Place the resistor within 500 mils of the PCH. Avoid
PCH_JTAG_TCK
@ RC22 51_0402_1% routing next to clock pins.
reference FFRD sch 0.5
reference 479493 figure 7-1
Te
HDA for Codec

1 2 PCH_AZ_SDOUT
<26> PCH_AZ_CODEC_SDOUT
RC23 33_0402_5%
1 2 PCH_AZ_SYNC
<26> PCH_AZ_CODEC_SYNC
RC24 33_0402_5%
w.
1 2 PCH_AZ_RST#
<26> PCH_AZ_CODEC_RST#
RC25 33_0402_5%
1 2 PCH_AZ_BITCLK
<26> PCH_AZ_CODEC_BITCLK
RC26 33_0402_5%
27P_0402_50V8J
EMC@
@ CC5
1
A A
2
ww
EMI depop location

PROPRIETARY NOTE:
Title
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT MCP(1/12)
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
0.3
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD LA-9431P
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Date: Friday, May 17, 2013 Sheet 6 of 59
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
UC1G HASWELL_MCP_E
LPC_LAD0 AU14 AN2 PCH_SMB_ALERT#

<25,29,36,37> LPC_LAD0 LAD0 SMBALERT/GPIO11 PCH_SMB_ALERT# <11>
LPC_LAD1 AW12 AP2 MEM_SMBCLK
<25,29,36,37> LPC_LAD1 LAD1 SMBCLK
2
LPC_LAD2 AY12 LPC AH1 MEM_SMBDATA
<25,29,36,37> LPC_LAD2 LAD2 SMBDATA
LPC_LAD3 AW11 AL2
G
<25,29,36,37> LPC_LAD3 LAD3 SML0ALERT/GPIO60
LPC_LFRAME# AV12 SMBUS AN1 SML0CLK MEM_SMBCLK 6 1
<25,29,36,37> LPC_LFRAME# LFRAME SML0CLK DDR_XDP_WAN_SMBCLK <18,19,31,9>
S
AK1 SML0DATA
SML0DATA AU4 PCH_GPIO73 QC1B
SML1ALERT/PCHHOT/GPIO73
5
AU3 SML1_SMBCLK DMN66D0LDW-7_SOT363-6
SML1CLK/GPIO75 AH3 SML1_SMBDATA SML1_SMBCLK <37>
G
SML1DATA/GPIO74 SML1_SMBDATA <37>
PCH_SPI_CLK AA3 MEM_SMBDATA 3 4
DDR_XDP_WAN_SMBDAT <18,19,31,9>
m
SPI_CLK
S
PCH_SPI_CS0# Y7 AF2 PCH_CL_CLK1
SPI_CS0 CL_CLK PCH_CL_CLK1 <31>
D PCH_SPI_CS1# Y4 AD2 PCH_CL_DATA1 QC1A D
SPI_CS1 CL_DATA PCH_CL_DATA1 <31> +3.3V_ALW_PCH
+3.3V_M AC2 SPI C-LINK AF4 PCH_CL_RST1# DMN66D0LDW-7_SOT363-6
PCH_SPI_DO AA2 SPI_CS2 CL_RST PCH_CL_RST1# <31>
1 2 PCH_SPI_DO2 PCH_SPI_DIN AA4 SPI_MOSI
co
R1 1K_0402_5% PCH_SPI_DO2 Y6 SPI_MISO
1 2 PCH_SPI_DO3 PCH_SPI_DO3 AF1 SPI_IO2 SML0CLK 2 1 MEM_SMBCLK 2 1
R2 1K_0402_5% SPI_IO3 @ RC29 0_0402_5% LAN_SMBCLK <28> 2.2K_0402_5% RC28
reference PDG0.7 SML0DATA 2 1 MEM_SMBDATA 2 1
LAN_SMBDATA <28>
@ RC31 0_0402_5% 2.2K_0402_5% RC30
2 1
7 OF 19 Rev1p2 @ RC33 0_0402_5% NFC_SMBCLK <20>
2 1 PCH_GPIO73 2 1
NFC_SMBDATA <20>
a.
@ RC35 0_0402_5% 10K_0402_5% RC34
SML1_SMBCLK 1 2
2.2K_0402_5% RC36
SML1_SMBDATA 1 2
+3.3V_M +3.3V_RUN 2.2K_0402_5% RC37
SML0CLK 2 1
64Mb Flash ROM 1@ C5 1K_0402_5% RC38
1 2 1 2 DDR_XDP_WAN_SMBDAT SML0DATA 2 1
200 MIL SO8 R122 10K_0402_5% 1K_0402_5% RC39
reference PDG0.7 1 2 DDR_XDP_WAN_SMBCLK Intel PDG 0.9
si
0.1U_0402_25V6
U1 1@ R123 10K_0402_5%
PCH_SPI_CS0# 1@ R3 1 2 0_0402_5% SPI_PCH_CS0#_R 1 8
PCH_SPI_DIN 1@ R4 1 2 33_0402_5% SPI_DIN64 2 /CS VCC 7 SPI_PCH_DO3_64 1@ R5 1 2 33_0402_5% PCH_SPI_DO3
PCH_SPI_DO2 1@ R6 1 2 33_0402_5% SPI_PCH_DO2_64 3 DO(IO1) /HOLD(IO3) 6 SPI_CLK64 1@ R7 1 2 33_0402_5% PCH_SPI_CLK
4 /WP(IO2) CLK 5 SPI_DO64 1@ R9 1 2 33_0402_5% PCH_SPI_DO
SPI_WP#_SEL 2 1 GND DI(IO0)
<36> SPI_WP#_SEL
@ R8 0_0402_5% W25Q64FVSSIQ_SO8
CONN@ +3.3V_M
ne
JTAA1
PCH_SPI_DO
PCH_SPI_DO
2@
5@
R11
R12
1
1
2 33_0402_5%
2 33_0402_5%
TAA_DO64
TAA_DO32
1
3 1
3
2
4
2
4
TAA Config
5 6
PCH_SPI_CLK 2@ R13 1 2 33_0402_5% TAA_CLK64 7 5 6 8 TAA_DO3_64 2@ R43 1 2 33_0402_5% PCH_SPI_DO3
C
+3.3V_M PCH_SPI_CLK 5@ R18 1 2 33_0402_5% TAA_CLK32 9 7 8 10 TAA_DO3_32 5@ R48 1 2 33_0402_5% PCH_SPI_DO3 C
PCH_SPI_CS0# 2@ R10 1 2 0_0402_5% TAA_CS0#_R 11 9 10 12 TAA_DO2_64 2@ R58 1 2 33_0402_5% PCH_SPI_DO2

200 MIL SO8 4@ C6 PCH_SPI_CS1# 5@ R17 1 2 0_0402_5% TAA_CS1#_R 13 11
13
12
14
14 TAA_DO2_32 5@ R59 1 2 33_0402_5% PCH_SPI_DO2
1 2 15 16
32Mb Flash ROM 15 16
do
PCH_SPI_DIN 2@ R22 1 2 33_0402_5% TAA_DIN64 17 18
reference PDG0.7 0.1U_0402_25V6 PCH_SPI_DIN 5@ R41 1 2 33_0402_5% TAA_DIN32 19 17 18 20
U2 4@ 19 20
PCH_SPI_CS1# 4@ R14 1 2 0_0402_5% SPI_PCH_CS1#_R 1 8 21 22
PCH_SPI_DIN 4@ R15 1 2 33_0402_5% SPI_DIN32 2 /CS VCC 7 SPI_PCH_DO3_32 4@ R16 1 2 33_0402_5% PCH_SPI_DO3 23 G G 24
XB use 50185-02041-001
PCH_SPI_DO2 4@ R19 1 2 33_0402_5% SPI_PCH_DO2_32 3 DO/IO1 /HOLD/IO3 6 SPI_CLK32 4@ R20 1 2 33_0402_5% PCH_SPI_CLK G G
4 /WP/IO2 CLK 5 SPI_DO32 4@ R21 1 2 33_0402_5% PCH_SPI_DO ACES_50185-02041-001
SPI_WP#_SEL 2 1 GND DI/IO0
@R23
@ R23 0_0402_5% W25Q32FVSSIQ_SO8
In
CC7
1 2 XTAL24_IN_R 2 1
@ RC40 0_0402_5%
1M_0402_5%
SPI_CLK32 SPI_CLK64 18P_0402_50V8J
3
4
HASWELL_MCP_E
33_0402_5%
33_0402_5%
RC44
UC1F
2
2
@ R45
@ R57
i-
YC2
24MHZ_12PF_X3G024000DC1H
1
2
C43 A25 XTAL24_IN CC6
1
C42 CLKOUT_PCIE_N0 XTAL24_IN B25 XTAL24_OUT 2 1

1 2 PCIECLK_REQ0# U2 CLKOUT_PCIE_P0 XTAL24_OUT
+3.3V_RUN PCIECLKRQ0/GPIO18
0.1U_0402_25V6
0.1U_0402_25V6
2 2 RC57 10K_0402_5% K21 PAD~D T6 @ 18P_0402_50V8J

RSVD
@ C85
@ C76
B41 M21 PAD~D T7 @

CLKOUT_PCIE_N1 RSVD
1 1 <29> PCH_TPM_LPC_EN
RC56
is1 2 10K_0402_5%
A41
Y5 CLKOUT_PCIE_P1
PCIECLKRQ1/GPIO19
DIFFCLK_BIASREF
C26
C35
CLK_BIASREF
MCP_TESTLOW1
+3.3V_RUN TESTLOW_C35
B CLK_PCIE_LAN# C41 CLOCK C34 MCP_TESTLOW2 B
<28> CLK_PCIE_LAN# CLK_PCIE_LAN B42 CLKOUT_PCIE_N2 TESTLOW_C34 AK8 MCP_TESTLOW3
10/100/1G LAN ---> <28> CLK_PCIE_LAN CLKOUT_PCIE_P2 TESTLOW_AK8
LANCLK_REQ# AD1 SIGNALS AL8 MCP_TESTLOW4
<10,28> LANCLK_REQ# PCIECLKRQ2/GPIO20 TESTLOW_AL8
CLK_PCIE_MINI2# B38 AN15 PCI_CLK_LPC_0 0_0402_5% 1 2 RC65 @ PCI_CLK_LPC
<31> CLK_PCIE_MINI2# CLKOUT_PCIE_N3 CLKOUT_LPC_0
WLAN (Mini Card 2)---> CLK_PCIE_MINI2 C37 AP15 PCI_CLK_LPC_1 22_0402_5% 1 2 RC64 EMC_3@
<31> CLK_PCIE_MINI2 CLKOUT_PCIE_P3 CLKOUT_LPC_1 CLK_PCI_DOCK <34>
kn
MINI2CLK_REQ# N1 22_0402_5% 1 2 RC66 EMC@
<31> MINI2CLK_REQ# PCIECLKRQ3/GPIO21 CLK_PCI_LPDEBUG <25>
B35
ADD EMI solution(EMC) <30> CLK_PCIE_MMI#
CLK_PCIE_MMI# A39
CLKOUT_PCIE_N4
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
A35
CLK_PCIE_MMI B39
<30> CLK_PCIE_MMI U5 CLKOUT_PCIE_P4
MMI---> <30> MMICLK_REQ#
MMICLK_REQ#
PCIECLKRQ4/GPIO22
+3.3V_RUN RC55 1 2 10K_0402_5%
+3.3V_RUN CLK_PCIE_MINI1# B37
<31> CLK_PCIE_MINI1# CLK_PCIE_MINI1 A37 CLKOUT_PCIE_N5
WWAN (Mini Card 1)---> <31> CLK_PCIE_MINI1 CLKOUT_PCIE_P5
RP4 MINI1CLK_REQ# T2
<31> MINI1CLK_REQ# PCIECLKRQ5/GPIO23
Te
1 8 DGPU_PWROK
DGPU_PWROK <10>
2 7 MINI2CLK_REQ# 6 OF 19 Rev1p2
3 6 MINI1CLK_REQ#
4 5 MPCIE_RST#
MPCIE_RST# <31,6>
10K_8P4R_5%
+PCH_VCCACLKPLL
w.
CLK_BIASREF 1 2
3.01K_0402_1% RC45
PCI_CLK_LPC_0 2 1 MCP_TESTLOW1 1 2
12P_0402_50V8J @CC15
@ CC15 10K_0402_5% RC46
PCI_CLK_LPC EMC@ RC58 1 2 22_0402_5% MCP_TESTLOW2 1 2
CLK_PCI_TPM_TCM <29> 10K_0402_5% RC47
PCI_CLK_LPC_1 2 1 EMC@ RC61 1 2 22_0402_5% MCP_TESTLOW3 1 2
12P_0402_50V8J @CC14
@ CC14 CLK_PCI_5048 <36> 10K_0402_5% RC50
ww
EMC@ RC63 1 2 22_0402_5% MCP_TESTLOW4 1 2

CLK_PCI_MEC <37> 10K_0402_5% RC52
A A
PROPRIETARY NOTE: Compal Electronics, Inc.
Title
For RF request(EMC) TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT MCP(2/12)
Every pin need one gnd by itself BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-9431P
5 4 3 2 1
5 4 3 2 1
m
D HASWELL_MCP_E HASWELL_MCP_E D
UC1C UC1D
<19> DDR_B_D[0..63]
<18> DDR_A_D[0..63]
DDR_A_D0 AH63 AU37 M_CLK_DDR#0
co
SA_DQ0 SA_CLK#0 M_CLK_DDR#0 <18>
DDR_A_D1 AH62 AV37 M_CLK_DDR0 DDR_B_D0 AY31 AM38 M_CLK_DDR#2
SA_DQ1 SA_CLK0 M_CLK_DDR0 <18> SB_DQ0 SB_CK#0 M_CLK_DDR#2 <19>
DDR_A_D2 AK63 AW36 M_CLK_DDR#1 DDR_B_D1 AW31 AN38 M_CLK_DDR2
SA_DQ2 SA_CLK#1 M_CLK_DDR#1 <18> SB_DQ1 SB_CK0 M_CLK_DDR2 <19>
DDR_A_D3 AK62 AY36 M_CLK_DDR1 DDR_B_D2 AY29 AK38 M_CLK_DDR#3
SA_DQ3 SA_CLK1 M_CLK_DDR1 <18> SB_DQ2 SB_CK#1 M_CLK_DDR#3 <19>
DDR_A_D4 AH61 DDR_B_D3 AW29 AL38 M_CLK_DDR3
SA_DQ4 SB_DQ3 SB_CK1 M_CLK_DDR3 <19>
DDR_A_D5 AH60 AU43 DDR_CKE0_DIMMA DDR_B_D4 AV31
SA_DQ5 SA_CKE0 DDR_CKE0_DIMMA <18> SB_DQ4
DDR_A_D6 AK61 AW43 DDR_CKE1_DIMMA DDR_B_D5 AU31 AY49 DDR_CKE2_DIMMB
SA_DQ6 SA_CKE1 DDR_CKE1_DIMMA <18> SB_DQ5 SB_CKE0 DDR_CKE2_DIMMB <19>
DDR_A_D7 AK60 AY42 DDR_B_D6 AV29 AU50 DDR_CKE3_DIMMB
SA_DQ7 SA_CKE2 SB_DQ6 SB_CKE1 DDR_CKE3_DIMMB <19>
DDR_A_D8 AM63 AY43 DDR_B_D7 AU29 AW49
AM62 SA_DQ8 SA_CKE3 AY27 SB_DQ7 SB_CKE2 AV50
a.
DDR_A_D9 DDR_B_D8
DDR_A_D10 AP63 SA_DQ9 AP33 DDR_CS0_DIMMA# DDR_B_D9 AW27 SB_DQ8 SB_CKE3
SA_DQ10 SA_CS#0 DDR_CS0_DIMMA# <18> SB_DQ9
DDR_A_D11 AP62 AR32 DDR_CS1_DIMMA# DDR_B_D10 AY25 AM32 DDR_CS2_DIMMB#
SA_DQ11 SA_CS#1 DDR_CS1_DIMMA# <18> SB_DQ10 SB_CS#0 DDR_CS2_DIMMB# <19>
DDR_A_D12 AM61 DDR_B_D11 AW25 AK32 DDR_CS3_DIMMB#
SA_DQ12 SB_DQ11 SB_CS#1 DDR_CS3_DIMMB# <19>
DDR_A_D13 AM60 AP32 DDR_B_D12 AV27
DDR_A_D14 AP61 SA_DQ13 SA_ODT0 DDR_B_D13 AU27 SB_DQ12 AL32
DDR_A_D15 AP60 SA_DQ14 AY34 DDR_A_RAS# DDR_B_D14 AV25 SB_DQ13 SB_ODT0
SA_DQ15 SA_RAS DDR_A_RAS# <18> SB_DQ14
DDR_A_D16 AP58 AW34 DDR_A_WE# DDR_B_D15 AU25 AM35 DDR_B_RAS#
SA_DQ16 SA_WE DDR_A_WE# <18> SB_DQ15 SB_RAS DDR_B_RAS# <19>
DDR_A_D17 AR58 AU34 DDR_A_CAS# DDR_B_D16 AM29 AK35 DDR_B_WE#
SA_DQ17 SA_CAS DDR_A_CAS# <18> SB_DQ16 SB_WE DDR_B_WE# <19>
si
DDR_A_D18 AM57 DDR_B_D17 AK29 AM33 DDR_B_CAS#
SA_DQ18 SB_DQ17 SB_CAS DDR_B_CAS# <19>
DDR_A_D19 AK57 AU35 DDR_A_BS0 DDR_B_D18 AL28
SA_DQ19 SA_BA0 DDR_A_BS0 <18> SB_DQ18
DDR_A_D20 AL58 AV35 DDR_A_BS1 DDR_B_D19 AK28 AL35 DDR_B_BS0
SA_DQ20 SA_BA1 DDR_A_BS1 <18> SB_DQ19 SB_BA0 DDR_B_BS0 <19>
DDR_A_D21 AK58 AY41 DDR_A_BS2 DDR_B_D20 AR29 AM36 DDR_B_BS1
SA_DQ21 SA_BA2 DDR_A_BS2 <18> SB_DQ20 SB_BA1 DDR_B_BS1 <19>
DDR_A_D22 AR57 DDR_B_D21 AN29 AU49 DDR_B_BS2
SA_DQ22 DDR_A_MA[0..15] <18> SB_DQ21 SB_BA2 DDR_B_BS2 <19>
DDR_A_D23 AN57 AU36 DDR_A_MA0 DDR_B_D22 AR28
SA_DQ23 SA_MA0 SB_DQ22 DDR_B_MA[0..15] <19>
DDR_A_D24 AP55 AY37 DDR_A_MA1 DDR_B_D23 AP28 AP40 DDR_B_MA0
DDR_A_D25 AR55 SA_DQ24 SA_MA1 AR38 DDR_A_MA2 DDR_B_D24 AN26 SB_DQ23 SB_MA0 AR40 DDR_B_MA1
DDR_A_D26 AM54 SA_DQ25 SA_MA2 AP36 DDR_A_MA3 DDR_B_D25 AR26 SB_DQ24 SB_MA1 AP42 DDR_B_MA2
ne
DDR_A_D27 AK54 SA_DQ26 SA_MA3 AU39 DDR_A_MA4 DDR_B_D26 AR25 SB_DQ25 SB_MA2 AR42 DDR_B_MA3
DDR_A_D28 AL55 SA_DQ27 SA_MA4 AR36 DDR_A_MA5 DDR_B_D27 AP25 SB_DQ26 SB_MA3 AR45 DDR_B_MA4
C DDR_A_D29 AK55 SA_DQ28 SA_MA5 AV40 DDR_A_MA6 DDR_B_D28 AK26 SB_DQ27 SB_MA4 AP45 DDR_B_MA5 C
DDR_A_D30 AR54 SA_DQ29 SA_MA6 AW39 DDR_A_MA7 DDR_B_D29 AM26 SB_DQ28 SB_MA5 AW46 DDR_B_MA6
DDR_A_D31 AN54 SA_DQ30 SA_MA7 AY39 DDR_A_MA8 DDR_B_D30 AK25 SB_DQ29 SB_MA6 AY46 DDR_B_MA7
DDR_A_D32 AY58 SA_DQ31 SA_MA8 AU40 DDR_A_MA9 DDR_B_D31 AL25 SB_DQ30 SB_MA7 AY47 DDR_B_MA8
DDR_A_D33 AW58 SA_DQ32 SA_MA9 AP35 DDR_A_MA10 DDR_B_D32 AY23 SB_DQ31 SB_MA8 AU46 DDR_B_MA9
DDR_A_D34 AY56 SA_DQ33 SA_MA10 AW41 DDR_A_MA11 DDR_B_D33 AW23 SB_DQ32 SB_MA9 AK36 DDR_B_MA10
DDR_A_D35 AW56 SA_DQ34 DDR CHANNEL A SA_MA11 AU41 DDR_A_MA12 DDR_B_D34 AY21 SB_DQ33 DDR CHANNEL B SB_MA10 AV47 DDR_B_MA11
do
DDR_A_D36 AV58 SA_DQ35 SA_MA12 AR35 DDR_A_MA13 DDR_B_D35 AW21 SB_DQ34 SB_MA11 AU47 DDR_B_MA12
DDR_A_D37 AU58 SA_DQ36 SA_MA13 AV42 DDR_A_MA14 DDR_B_D36 AV23 SB_DQ35 SB_MA12 AK33 DDR_B_MA13
DDR_A_D38 AV56 SA_DQ37 SA_MA14 AU42 DDR_A_MA15 DDR_B_D37 AU23 SB_DQ36 SB_MA13 AR46 DDR_B_MA14
DDR_A_D39 AU56 SA_DQ38 SA_MA15 DDR_B_D38 AV21 SB_DQ37 SB_MA14 AP46 DDR_B_MA15
SA_DQ39 DDR_A_DQS#[0..7] <18> SB_DQ38 SB_MA15
DDR_A_D40 AY54 AJ61 DDR_A_DQS#0 DDR_B_D39 AU21
SA_DQ40 SA_DQSN0 SB_DQ39 DDR_B_DQS#[0..7] <19>
DDR_A_D41 AW54 AN62 DDR_A_DQS#1 DDR_B_D40 AY19 AW30 DDR_B_DQS#0
DDR_A_D42 AY52 SA_DQ41 SA_DQSN1 AM58 DDR_A_DQS#2 DDR_B_D41 AW19 SB_DQ40 SB_DQSN0 AV26 DDR_B_DQS#1
DDR_A_D43 AW52 SA_DQ42 SA_DQSN2 AM55 DDR_A_DQS#3 DDR_B_D42 AY17 SB_DQ41 SB_DQSN1 AN28 DDR_B_DQS#2
SA_DQ43 SA_DQSN3 SB_DQ42 SB_DQSN2
In
DDR_A_D44 AV54 AV57 DDR_A_DQS#4 DDR_B_D43 AW17 AN25 DDR_B_DQS#3
DDR_A_D45 AU54 SA_DQ44 SA_DQSN4 AV53 DDR_A_DQS#5 DDR_B_D44 AV19 SB_DQ43 SB_DQSN3 AW22 DDR_B_DQS#4
DDR_A_D46 AV52 SA_DQ45 SA_DQSN5 AL43 DDR_A_DQS#6 DDR_B_D45 AU19 SB_DQ44 SB_DQSN4 AV18 DDR_B_DQS#5
DDR_A_D47 AU52 SA_DQ46 SA_DQSN6 AL48 DDR_A_DQS#7 DDR_B_D46 AV17 SB_DQ45 SB_DQSN5 AN21 DDR_B_DQS#6
DDR_A_D48 AK40 SA_DQ47 SA_DQSN7 DDR_B_D47 AU17 SB_DQ46 SB_DQSN6 AN18 DDR_B_DQS#7
SA_DQ48 DDR_A_DQS[0..7] <18> SB_DQ47 SB_DQSN7
DDR_A_D49 AK42 AJ62 DDR_A_DQS0 DDR_B_D48 AR21
SA_DQ49 SA_DQSP0 SB_DQ48 DDR_B_DQS[0..7] <19>
DDR_A_D50 AM43 AN61 DDR_A_DQS1 DDR_B_D49 AR22 AV30 DDR_B_DQS0
DDR_A_D51 AM45 SA_DQ50 SA_DQSP1 AN58 DDR_A_DQS2 DDR_B_D50 AL21 SB_DQ49 SB_DQSP0 AW26 DDR_B_DQS1
DDR_A_D52 AK45 SA_DQ51 SA_DQSP2 AN55 DDR_A_DQS3 DDR_B_D51 AM22 SB_DQ50 SB_DQSP1 AM28 DDR_B_DQS2
i-
DDR_A_D53 AK43 SA_DQ52 SA_DQSP3 AW57 DDR_A_DQS4 DDR_B_D52 AN22 SB_DQ51 SB_DQSP2 AM25 DDR_B_DQS3
DDR_A_D54 AM40 SA_DQ53 SA_DQSP4 AW53 DDR_A_DQS5 DDR_B_D53 AP21 SB_DQ52 SB_DQSP3 AV22 DDR_B_DQS4
DDR_A_D55 AM42 SA_DQ54 SA_DQSP5 AL42 DDR_A_DQS6 DDR_B_D54 AK21 SB_DQ53 SB_DQSP4 AW18 DDR_B_DQS5
DDR_A_D56 AM46 SA_DQ55 SA_DQSP6 AL49 DDR_A_DQS7 DDR_B_D55 AK22 SB_DQ54 SB_DQSP5 AM21 DDR_B_DQS6
DDR_A_D57 AK46 SA_DQ56 SA_DQSP7 DDR_B_D56 AN20 SB_DQ55 SB_DQSP6 AM18 DDR_B_DQS7
DDR_A_D58 AM49 SA_DQ57 AP49 DDR_B_D57 AR20 SB_DQ56 SB_DQSP7
SA_DQ58 SM_VREF_CA +SM_VREF_CA SB_DQ57
DDR_A_D59 AK49 AR51 +SM_VREF_DQ0 DDR_B_D58 AK18
DDR_A_D60 AM48 SA_DQ59 SM_VREF_DQ0 AP51 DDR_B_D59 AL18 SB_DQ58
B SA_DQ60 SM_VREF_DQ1 +SM_VREF_DQ1 SB_DQ59 B
DDR_A_D61 AK48 DDR_B_D60 AK20
DDR_A_D62
DDR_A_D63
AM51
AK51
SA_DQ61
SA_DQ62
is DDR_B_D61
DDR_B_D62
AM20
AR18
SB_DQ60
SB_DQ61
SA_DQ63 DDR_B_D63 AP18 SB_DQ62
SB_DQ63
kn
3 OF 19 Rev1p2 4 OF 19 Rev1p2
Te
w.
A A
ww
PROPRIETARY NOTE:
Title
0.3
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW_PCH +RTC_CELL
1 2 +3.3V_RUN
330K_0402_1%
@ RC72 0_0402_5% @ CC9
2
+3.3V_RUN 1 2
RC73
@ CC8
1 2 0.1U_0402_25V6
1 2 SUS_STAT#/LPCPD#
5
@ RC74 10K_0402_5% 0.1U_0402_25V6 +3.3V_ALW2
1
5
XDP_DBRESET# 1 @ CC82
P
B 4 SYS_RESET# PCH_PLTRST# 1 1 2
P
2 1 ME_RESET# 2 O B 4 PCH_PLTRST#_EC
A O PCH_PLTRST#_EC <25,29,31,36,37>
G
@ RC76 8.2K_0402_5% @ UC2 2 0.1U_0402_25V6 DSWODVREN
A
G
+PCH_VCCDSW3_3 74AHC1G09GW_TSSOP5~D UC3
330K_0402_1%
TC7SH08FU_SSOP5~D
@ RC78
2
SIO_SLP_A# 1
P
B 4 PM_APWROK_R
PCH_DPWROK 1 2 PCH_RSMRST#_R PM_APWROK 2 O
m
<37> PM_APWROK A
G
@ RC79 0_0402_5% UC7
D 1 2 PCH_PCIE_WAKE# TC7SH08FU_SSOP5~D D
1
RC71 10K_0402_5% ME_SUS_PWR_ACK_R 1 2 SUSACK#_R
@ RC82 0_0402_5%
co
RESET_OUT# 1 2 SYS_PWROK_R 1 2
@ RC84 0_0402_5% @ RC144 0_0402_5%
+3.3V_RUN DSWODVREN - ON DIE DSW VR ENABLE

HIGH = ENABLED (DEFAULT)
1 2 ME_RESET# UC1H HASWELL_MCP_E
@ RC81 8.2K_0402_5%
LOW = DISABLED
SYSTEM POWER MANAGEMENT
a.
@ RC86 1 2 0_0402_5% SUSACK#_R AK2 AW7 DSWODVREN
<12,36> SUSACK# SUSACK DSWVRMEN
SYS_RESET# AC3 AV5 PCH_DPWROK
SYS_RESET DPWROK PCH_DPWROK <36>
@ RC87 1 2 0_0402_5% SYS_PWROK_R AG2 AJ5 PCH_PCIE_WAKE#
<36,9> SYS_PWROK SYS_PWROK WAKE PCH_PCIE_WAKE# <37>
@ RC88 1 2 0_0402_5% PCH_PWROK AY7
<15,37> RESET_OUT# PCH_PWROK
@ RC300 1 2 0_0402_5% PM_APWROK_R AB5 JAPS1 CONN@
<20> PLTRST_NFC# APWROK
@ RC89 1 2 0_0402_5% PCH_PLTRST# AG7 V5 CLKRUN# +3.3V_ALW_PCH 1
<29> PLTRST_USH# PLTRST CLKRUN/GPIO32 CLKRUN# <10,29,36,37> 1
@ RC90 1 2 0_0402_5% AG4 SUS_STAT#/LPCPD# SIO_SLP_S3# 2
<30> PLTRST_MMI# SUS_STAT/GPIO61 2
@ RC91 1 2 0_0402_5% AE6 SUSCLK +PCH_VCCDSW3_3
3
+3.3V_ALW_PCH <28> PLTRST_LAN# SUSCLK/GPIO62 T10 PAD~D@ 3
@ RC92 1 2 0_0402_5% AP5 SIO_SLP_S5# SIO_SLP_S5# 4
<21> PLTRST_VMM2320# SLP_S5/GPIO63 SIO_SLP_S5# <37> 4
@ RC93 1 2 0_0402_5% PCH_RSMRST#_R AW6 SIO_SLP_S4# 5
<38> PCH_RSMRST#_Q RSMRST T11 PAD~D@ 5
RP10 @ RC94 1 2 0_0402_5% ME_SUS_PWR_ACK_R AV4 SIO_SLP_A# 6
<37> ME_SUS_PWR_ACK SUSWARN/SUSPWRDNACK/GPIO30 T12 PAD~D @ 6
AL7 AJ6 7
si
SIO_PWRBTN# SIO_SLP_S4# +PCH_VCCDSW3_3
<37,9> SIO_PWRBTN# PWRBTN SLP_S4 SIO_SLP_S4# <36,39,43> 7
1 8 ME_SUS_PWR_ACK AC_PRESENT AJ8 AT4 SIO_SLP_S3# 8
<12,37> AC_PRESENT ACPRESENT/GPIO31 SLP_S3 SIO_SLP_S3# <36,39,43> 8
2 7 USB_OC3# PCH_BATLOW# AN4 AL5 SIO_SLP_A# PCH_RTCRST# 9
USB_OC3# <11> <12> PCH_BATLOW# BATLOW/GPIO72 SLP_A SIO_SLP_A# <36,39,44> <6> PCH_RTCRST# 9
3 6 SIO_EXT_WAKE# SIO_SLP_S0# AF3 AP4 SIO_SLP_SUS# 10
SIO_EXT_WAKE# <12,36> <37> SIO_SLP_S0# SLP_S0 SLP_SUS SIO_SLP_SUS# <36> 10
4 5 KB_DET# AM5 AJ7 SIO_SLP_LAN# POWER_SW#_MB 11
KB_DET# <12,38> <36> SIO_SLP_WLAN# SLP_WLAN/GPIO29 SLP_LAN SIO_SLP_LAN# <28,36> <37,40> POWER_SW#_MB 11
12
10K_8P4R_5% SYS_RESET# 13 12
14 13
SIO_SLP_S0# 15 14
8 OF 19 Rev1p2 16 15
1 2 PCH_RSMRST#_R 17 16
18 17
ne
RC136 10K_0402_5%
19 18
20 GND
+3.3V_RUN GND
ACES_50506-01841-P01
C XDP@ CC41 C
2 1
UC6 XDP@
0.1U_0402_25V6
14
VCC
PCH_JTAG_TDO 1 2 TDO_XDP 2 3 CPU_XDP_TDO
do
<6> PCH_JTAG_TDO 1A 1B
XDP@ RC95 0_0402_5%
+1.05V_RUN
RUNPWROK 1
1OE
0.1U_0402_25V6
0.1U_0402_25V6
1 2 TDI_XDP 1 2 TDI_XDP_R 5 6 CPU_XDP_TDI
<6> PCH_JTAG_TDI 2A 2B
RC96 0_0402_5% RC103 0_0402_5% 1 1
XDP@ XDP@ @ @
+1.05V_RUN +1.05V_RUN
CC10
CC11
RUNPWROK 4
2OE
1 2 TMS_XDP 9 8 CPU_XDP_TMS 2 2
<6> PCH_JTAG_TMS 3A 3B
RC101 0_0402_5% JXDP1
In
XDP@ 1 2
RUNPWROK 10 CPU_XDP_PREQ# 3 GND0 GND1 4 CFG17
3OE OBSFN_A0 OBSFN_C0 CFG17 <13>
CPU_XDP_PRDY# 5 6 CFG16 CFG16 <13>
TRST#_XDP 12 11 CPU_XDP_TRST# 7 OBSFN_A1 OBSFN_C1 8
4A 4B CFG0 9 GND2 GND3 10 CFG8
Place near JXDP1 <13> CFG0
CFG1 11 OBSDATA_A0 OBSDATA_C0 12 CFG9
CFG8 <13>
<13> CFG1 OBSDATA_A1 OBSDATA_C1 CFG9 <13>
RUNPWROK 13 7 13 14
<36,37> RUNPWROK 4OE GND GND4 GND5
H_PROCHOT# <13> CFG2 CFG2 15 16 CFG10 CFG10 <13>
15 CFG3 17 OBSDATA_A2 OBSDATA_C2 18 CFG11
GND PAD <13> CFG3 OBSDATA_A3 OBSDATA_C3 CFG11 <13>
1 19 20
@ XDP_OBS0_R 21 GND6 GND7 22 CFG19
i-
OBSFN_B0 OBSFN_D0 CFG19 <13>
CC149 XDP_OBS1_R 23 24 CFG18 CFG18 <13>
74CBTLV3126BQ_DHVQFN14_2P5X3 OBSFN_B1 OBSFN_D1
22P_0402_50V8J 25 26
2 reference Shark Bay ULT Validation Customer Debug Port CFG4 27 GND8 GND9 28 CFG12
<13> CFG4 OBSDATA_B0 OBSDATA_D0 CFG12 <13>
Implementation Requirement Rev 1.0 <13> CFG5 CFG5 29 30 CFG13 CFG13 <13>
31 OBSDATA_B1 OBSDATA_D1 32
RC5 need to close to JCPU1 GND10 GND11
2 1 CPU_XDP_TRST# <13> CFG6 CFG6 33 34 CFG14 CFG14 <13>
<6> PCH_JTAG_TRST# OBSDATA_B2 OBSDATA_D2
0_0402_5% RC135 @ RC105 1 2 1K_0402_5% <13> CFG7 CFG7 35 36 CFG15 CFG15 <13>
<15> H_VCCST_PWRGD OBSDATA_B3 OBSDATA_D3
ESD request, place near CPU side XDP@ 37 38
2 1 CPU_XDP_TCLK H_CPUPWRGD @ RC106 1 2 1K_0402_5% H_VCCST_PWRGD_XDP 39 GND12 GND13 40
<6> PCH_JTAG_JTAGX PWRGOOD/HOOK0 ITPCLK/HOOK4
0_0402_5% RC97 @ @ RC107 1 2 0_0402_5% CFD_PWRBTN#_XDP 41 42
<37,9> SIO_PWRBTN# HOOK1 ITPCLK#/HOOK5
43 44
B
0_0402_5%
2 1 TDO_XDP
RC123 @
is <15> CPU_PWR_DEBUG#
<36,9> SYS_PWROK
@ RC108
@ RC110
1
1
2 0_0402_5%
2 0_0402_5%
CPU_PWR_DEBUG#_R
SYS_PWROK_XDP
45
47
49
VCC_OBS_AB
HOOK2
HOOK3
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
46
48
50
XDP_RST#_R
XDP_DBRESET# RC109
XDP@
2 1 PCH_PLTRST#_EC
1K_0402_5%
B
PCH_JTAG_TDO 2 1 TDI_XDP_R @ RC111 1 2 0_0402_5% DDR_XDP_SMBDAT_R1 51 GND14 GND15 52 TDO_XDP
<18,19,31,7> DDR_XDP_WAN_SMBDAT SDA TD0
0_0402_5% RC104 @ @ RC112 1 2 0_0402_5% DDR_XDP_SMBCLK_R1 53 54 TRST#_XDP
<18,19,31,7> DDR_XDP_WAN_SMBCLK SCL TRST#
@ RC142 1 2 0_0402_5% PCH_JTAG_TCK_R 55 56 TDI_XDP
<6> PCH_JTAG_TCK TCK1 TDI
PCH_JTAG_TCK 2 1 CPU_XDP_TCLK CPU_XDP_TCLK 57 58 TMS_XDP
0_0402_5% RC124 @ 59 TCK0 TMS 60 CFG3_R 1 2 CFG3
+1.05V_VCCST GND16 GND17 RC99 1K_0402_5%
SAMTE_BSH-030-01-L-D-A CONN@ XDP@ +1.05V_RUN
1 2 H_CATERR#
kn
@ RC113 49.9_0402_1%
1 2 H_PROCHOT# TDO_XDP @ RC280 2 1 51_0402_1%
RC114 62_0402_5% +3.3V_ALW_PCH
2
XDP@
RC102
1K_0402_5% Place near JXDP1.48
XDP_DBRESET#
1
H_CPUPWRGD
Te
SYS_PWROK_XDP 1
10K_0402_5%
XDP@ CC68
PU/PD for JTAG signals
1
100P_0402_50V8J
1 0.1U_0402_25V6
HASWELL_MCP_E
RC115
reference CRB 1 UC1B @ CC48

@ 0.1U_0402_25V6 2 +3.3V_RUN
CC90
CPU_DETECT# D61 2
Place near JXDP1.47
2
2 <36> CPU_DETECT# H_CATERR# K61 PROC_DETECT XDP_DBRESET# RC116 2 1 1K_0402_5%

MISC
ESD request PECI_EC N62 CATERR J62 CPU_XDP_PRDY#
<37> PECI_EC PECI PRDY K62 CPU_XDP_PREQ#
JTAG
PREQ E60 CPU_XDP_TCLK +1.05V_RUN
w.
PROC_TCK E61 CPU_XDP_TMS

CAD Note: 1 2H_PROCHOT#_R K63 PROC_TMS E59 CPU_XDP_TRST# CPU_XDP_TMS @ RC118 2 1 51_0402_1%
<37,46,47,48> H_PROCHOT# PROCHOT PROC_TRST
Avoid stub in the PWRGD path RC117 56_0402_5% THERMAL F63 CPU_XDP_TDI
PROC_TDI F62 CPU_XDP_TDO CPU_XDP_TDI @ RC119 2 1 51_0402_1%
while placing resistors RC115 PROC_TDO
H_CPUPWRGD C61 CPU_XDP_PREQ# @ RC120 2 1 51_0402_1%
PROCPWRGD PWR
J60 XDP_OBS0_R CPU_XDP_TDO RC122 2 1 51_0402_1%
DDR3 COMPENSATION SIGNALS BPM#0
BPM#1
H60 XDP_OBS1_R
H61 XDP_OBS2_R PAD~D T122 @
BPM#2 H62 XDP_OBS3_R PAD~D T126 @
ww
A 200_0402_1% 2 1RC125 SM_RCOMP0 SM_RCOMP0 AU60 BPM#3 K59 XDP_OBS4_R PAD~D T129 @ CPU_XDP_TCLK RC127 2 1 51_0402_1% A
SM_RCOMP1 AV60 SM_RCOMP0 DDR3 BPM#4 H63 XDP_OBS5_R PAD~D T130 @
121_0402_1% 2 1RC129 SM_RCOMP1 SM_RCOMP2 AU61 SM_RCOMP1 BPM#5 K60 XDP_OBS6_R PAD~D T131 @ CPU_XDP_TRST# @ RC131 2 1 51_0402_1%
AV15 SM_RCOMP2 BPM#6 J61 XDP_OBS7_R PAD~D T132 @
<18> DDR3_DRAMRST#_CPU SM_DRAMRST BPM#7
100_0402_1% 2 1RC133 SM_RCOMP2 <18> DDR_PG_CTRL AV61
SM_PG_CNTL1
CAD Note: 2 OF 19 Rev1p2
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
Title
0.3
5 4 3 2 1
5 4 3 2 1
HASWELL_MCP_E
UC1A
DDI1_LANE_N0 C54 C45 EDP_CPU_LANE_N0 COMPENSATION PU FOR eDP

<23> DDI1_LANE_N0 DDI1_LANE_P0 C55 DDI1_TXN0 EDP_TXN0 B46 EDP_CPU_LANE_P0 EDP_CPU_LANE_N0 <22> follow intel feedback
<23> DDI1_LANE_P0 DDI1_LANE_N1 B58 DDI1_TXP0 EDP_TXP0 A47 EDP_CPU_LANE_N1 EDP_CPU_LANE_P0 <22>
<23> DDI1_LANE_N1 DDI1_LANE_P1 C58 DDI1_TXN1 EDP_TXN1 B47 EDP_CPU_LANE_P1 EDP_CPU_LANE_N1 <22> +VCCIOA_OUT
<23> DDI1_LANE_P1 DDI1_LANE_N2 B55 DDI1_TXP1 EDP_TXP1 EDP_CPU_LANE_P1 <22>
<23> DDI1_LANE_N2 DDI1_LANE_P2 A55 DDI1_TXN2 C47
<23> DDI1_LANE_P2 DDI1_LANE_N3 A57 DDI1_TXP2 EDP_TXN2 C46 EDP_COMP 2 1
<23> DDI1_LANE_N3 DDI1_LANE_P3 B57 DDI1_TXN3 EDP_TXP2 A49 24.9_0402_1% RC134
m
<23> DDI1_LANE_P3 DDI1_TXP3 DDI EDP EDP_TXN3 B49
D DDI2_LANE_N0 C51 EDP_TXP3 D
<27> DDI2_LANE_N0
DDI2_LANE_P0 C50 DDI2_TXN0 A45 EDP_CPU_AUX#
CAD Note:Trace width=20 mils ,Spacing=25mil,
<27> DDI2_LANE_P0 DDI2_TXP0 EDP_AUXN EDP_CPU_AUX# <22>
<27> DDI2_LANE_N1
DDI2_LANE_N1 C53
DDI2_TXN1 EDP_AUXP
B45 EDP_CPU_AUX
EDP_CPU_AUX <22>
Max length=100 mils.
co
DDI2_LANE_P1 B54
+3.3V_RUN <27> DDI2_LANE_P1 DDI2_LANE_N2 C49 DDI2_TXP1 D20 EDP_COMP
<27> DDI2_LANE_N2 DDI2_LANE_P2 B50 DDI2_TXN2 EDP_RCOMP A43
1 2 CONTACTLESS_DET# <27> DDI2_LANE_P2 DDI2_LANE_N3 A53 DDI2_TXP2 EDP_DISP_UTIL
RC137 10K_0402_5% <27> DDI2_LANE_N3 DDI2_LANE_P3 B53 DDI2_TXN3
<27> DDI2_LANE_P3 DDI2_TXP3
1 2 TOUCHPAD_INTR#
RC140 10K_0402_5%
a.
1 OF 19 Rev1p2
+3.3V_RUN
1 2 TOUCH_RST_N_GYRO_INT1
RC202 10K_0402_5%
CPU_DPB_CTRLCLK 2 1
Intel WW18 Strapping option 2.2K_0402_5% RC139
HASWELL_MCP_E
UC1I CPU_DPB_CTRLDAT 2 1
si
2.2K_0402_5% RC141
CPU_DPC_CTRLCLK 2 1
Intel WW18 Strapping option 2.2K_0402_5% RC143
CPU_DPC_CTRLDAT 2 1
EDP_BIA_PWM B8 B9 CPU_DPB_CTRLCLK 2.2K_0402_5% RC145
<22> EDP_BIA_PWM A9 EDP_BKLCTL DDPB_CTRLCLK C9 CPU_DPB_CTRLCLK <23> 2 1
PANEL_BKLEN CPU_DPB_CTRLDAT CPU_DPB_AUX#
1 2 ENVDD_PCH <22> PANEL_BKLEN ENVDD_PCH C6 EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA D9 CPU_DPC_CTRLCLK CPU_DPB_CTRLDAT <23>
100K_0402_5% RC147
@ RC152 100K_0402_5% <22,36> ENVDD_PCH EDP_VDDEN DDPC_CTRLCLK D11 CPU_DPC_CTRLDAT CPU_DPC_CTRLCLK <27> CPU_DPC_AUX# 2 1
DDPC_CTRLDATA CPU_DPC_CTRLDAT <27>
ne
2 1 CODEC_IRQ 100K_0402_5% RC149
@ RC154 1K_0402_5%
U6
<29> CONTACTLESS_DET# DGPU_PWROK P4 PIRQA/GPIO77 C5 CPU_DPB_AUX#
C <7> DGPU_PWROK PIRQB/GPIO78 DISPLAY DDPB_AUXN C
PIRQ#_TPM N4 B6 CPU_DPC_AUX#
<12> PIRQ#_TPM HDD_FALL_INT N2 PIRQC/GPIO79 DDPC_AUXN B5 CPU_DPB_AUX CPU_DPC_AUX# <27> DPC_HPD 2 1
AD4 PIRQD/GPIO80 DDPB_AUXP A6 CPU_DPC_AUX 100K_0402_5% RC151
@T13
@ T13 PAD~D PME DDPC_AUXP CPU_DPC_AUX <27>
GPIO CPU_DPB_AUX 2 1
TOUCHPAD_INTR# U7 100K_0402_5% RC153
do
TOUCH_RST_N_GYRO_INT1 L1 GPIO55 CPU_DPC_AUX 2 1
L3 GPIO52 C8 DPB_HPD 100K_0402_5% RC155
R5 GPIO54 DDPB_HPD A8 DPC_HPD DPB_HPD <23>
+3.3V_RUN CODEC_IRQ L4 GPIO51 DDPC_HPD D6 DPC_HPD <27>
GPIO53 EDP_HPD EDP_CPU_HPD <22>
RP6
100K_0402_5%
0.1U_0402_25V6
1
1 8 CLKRUN# 1 @
CLKRUN# <29,36,37,9>
In
RC158
CC450
2 7 LANCLK_REQ# 9 OF 19 Rev1p2
LANCLK_REQ# <28,7>
3 6 HDD_FALL_INT
4 5 PCH_GPIO36
PCH_GPIO36 <6> 2
2
10K_8P4R_5%
reference PDG 0.9
i-
ESD solution for black screen issue
is
B B
kn
Te
w.
ww
A A
PROPRIETARY NOTE:
Title
0.3
5 4 3 2 1
5 4 3 2 1
m
D D
co
HASWELL_MCP_E
UC1K
a.
PCIE_PRX_MMITX_N5 F10 AN8 USBP0-
<30> PCIE_PRX_MMITX_N5 PERN5_L0 USB2N0 USBP0- <33>
<30> PCIE_PRX_MMITX_P5
PCIE_PRX_MMITX_P5 E10
PERP5_L0 USB2P0
AM8 USBP0+
USBP0+ <33>
----->Ext Port 1 and DOCK2 (USB SW)
MMI -->
PCIE_PTX_MMIRX_N5 C23 AR7 USBP1-
<30> PCIE_PTX_MMIRX_N5 PETN5_L0 USB2N1 USBP1- <35>
<30> PCIE_PTX_MMIRX_P5
PCIE_PTX_MMIRX_P5 C22
PETP5_L0 USB2P1
AT7 USBP1+
USBP1+ <35> ----->Ext Port 2 IO/B
F8 AR8 USBP2-
si
PERN5_L1 USB2N2 USBP2- <31>
E8
PERP5_L1 USB2P2
AP8 USBP2+
USBP2+ <31>
----->WLAN/BT
B23 AR10 USBP3-
A23 PETN5_L1 USB2N3 AT10 USBP3+ USBP3- <22>
PETP5_L1 USB2P3 USBP3+ <22> ----->Camera
H10 AM15 USBP4-
G10 PERN5_L2 USB2N4 AL15 USBP4+ USBP4- <29> ----->USH
PERP5_L2 USB2P4 USBP4+ <29>
ne
B21 AM13 USBP5-
C21 PETN5_L2 USB2N5 AN13 USBP5+
USBP5- <32> ----->Ext Port 3 and DOCK1(USB SW)
PETP5_L2 USB2P5 USBP5+ <32>
E6 AP11 USBP6-
C F6 PERN5_L3 USB2N6 AN11 USBP6+ USBP6- <31> C
PERP5_L3 USB2P6 USBP6+ <31> ----->WWAN
B22 AR13 USBP7-
PETN5_L3 USB2N7 USBP7- <22>
A21
PETP5_L3 USB2P7
AP13 USBP7+
USBP7+ <22>
----->Touch
do
PCIE_PRX_GLANTX_N3 G11
<28> PCIE_PRX_GLANTX_N3 F11 PERN3 G20
PCIE_PRX_GLANTX_P3
<28> PCIE_PRX_GLANTX_P3 PERP3 USB3RN1 H20 USB3RN1 <35>
10/100/1G LAN ---> USBRBIAS
PCIE_PTX_GLANRX_N3 C29 USB3RP1 USB3RP1 <35>
<28> PCIE_PTX_GLANRX_N3 PETN3 ----->Ext USB3 Port 1
22.6_0402_1%
PCIE_PTX_GLANRX_P3 B30 PCIe USB C33
<28> PCIE_PTX_GLANRX_P3 PETP3 USB3TN1 USB3TN1 <35>
1
B34
USB3TP1 USB3TP1 <35>
RC159
PCIE_PRX_WLANTX_N4 F13
<31> PCIE_PRX_WLANTX_N4 G13 PERN4 E18
PCIE_PRX_WLANTX_P4
<31> PCIE_PRX_WLANTX_P4 PERP4 USB3RN2 USB3RN2 <33>
In
WLAN (Mini Card 2)---> F18
PCIE_PTX_WLANRX_N4 B29 USB3RP2 USB3RP2 <33>
----->Ext USB3 Port 3 IO/B
2
<31> PCIE_PTX_WLANRX_N4 PCIE_PTX_WLANRX_P4 A29 PETN4 B33
<31> PCIE_PTX_WLANRX_P4 PETP4 USB3TN2 A33 USB3TN2 <33>
G17 USB3TP2 USB3TP2 <33>
<32> USB3RN3 F17 PERN1/USB3RN3
<32> USB3RP3 PERP1/USB3RP3
Ext USB Port 2 <---- CAD NOTE:
C30
<32> USB3TN3 C31 PETN1/USB3TN3 AJ10 USBRBIAS Route single-end 50-ohms and max 500-mils length.
i-
<32> USB3TP3 PETP1/USB3TP3 USBRBIAS AJ11 Avoid routing next to clock pins or under stitching capacitors.
F15 USBRBIAS AN10 PAD~D T14 @
PERN2/USB3RN4 RSVD Recommended minimum spacing to other signal traces is 15 mils.
G15 AM10 PAD~D T15 @
PERP2/USB3RP4 RSVD
B31
A31 PETN2/USB3TN4
PETP2/USB3TP4 AL3 USB_OC0#
OC0/GPIO40 AT1 USB_OC1# USB_OC0# <33>
USB_OC1# <35>
reference CRB 3.01K 1% @ T16 PAD~D E15
RSVD
is OC1/GPIO41
OC2/GPIO42
OC3/GPIO43
AH2
AV3
USB_OC2#
USB_OC3# USB_OC2# <33>
B @ T17 PAD~D E13 USB_OC3# <9> +3.3V_ALW_PCH B
RC161 1 2 3.01K_0402_1% PCH_PCIE_RCOMP A27 RSVD
+PCH_AUSB3PLL PCIE_RCOMP
@RC163
@ RC163 1 2 0_0402_5% PCH_PCIE_IREF B27
PCIE_IREF
USB_OC1# 1 2
10K_0402_5% RC166
kn
11 OF 19 Rev1p2
+3.3V_ALW_PCH
RP5
USB_OC2# 8 1
Te
USB_OC0# 7 2
PCH_SMB_ALERT# 6 3
<7> PCH_SMB_ALERT# MEDIACARD_PWREN 5 4
<12,30> MEDIACARD_PWREN
10K_8P4R_5%
w.
ww
A A
PROPRIETARY NOTE:
Title
0.3
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
RP2
H_THERMTRIP# PIRQ#_TPM 8 1
<10> PIRQ#_TPM PCH_GPIO83 7 2
100P_0402_50V8J
SIO_RCIN# 6 3
1 2 EC_WAKE# 1 5 4
<28,37> LAN_WAKE# @
@RC301
@ RC301 0_0402_5%
CC91
10K_8P4R_5%
2 RP8
+3.3V_RUN 3.3V_TS_EN 8 1
m
PCH_GPIO84 7 2
D 2 1 MPHYP_PWR_EN UC1J HASWELL_MCP_E ESD request PCH_GPIO85 6 3 D
RC170 100K_0402_5% 3.3V_TP_EN 5 4
2 1 SIO_EXT_SCI#
co
RC199 100K_0402_5% 10K_8P4R_5%
PCH_AUDIO_EN P1 D60 H_THERMTRIP#_R @ RC172 2 1 0_0402_5% +3.3V_ALW_PCH

SIO_EXT_WAKE# AU2 BMBUSY/GPIO76 THERMTRIP V4 SIO_RCIN# H_THERMTRIP# <37>
+PCH_VCCDSW3_3
<36,9> SIO_EXT_WAKE# PM_LANPHY_ENABLEAM7 GPIO8 RCIN/GPIO82 T4 IRQ_SERIRQ SIO_RCIN# <37>
<28> PM_LANPHY_ENABLE PCH_GPIO15 AD6 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ AW15 PCH_OPI_COMP IRQ_SERIRQ <29,36,37>
RP9
Y1 GPIO15 MISC PCH_OPI_RCOMP AF20 @ T18 PAD~D PCH_GPIO9 8 1 +PCH_VCCDSW3_3
2 1 PM_LANPHY_ENABLE <28> LAN_RST# PCH_GPIO17 T3 GPIO16 RSVD AB21 SLATE_MODE_R 7 2
@ T19 PAD~D
RC197 10K_0402_5% @ T139 PAD~D AD5 GPIO17 RSVD PCH_BATLOW# 6 3
a.
EC_WAKE# AN5 GPIO24 <9> PCH_BATLOW# AC_PRESENT 5 4
<37> EC_WAKE# AD7 GPIO27 <37,9> AC_PRESENT
2 1 EC_WAKE# <20> PCH_NFC_RST NFC_IRQ AN3 GPIO28 10K_8P4R_5%
<20> NFC_IRQ GPIO26 R6
RC206 10K_0402_5% PCH_GPIO83
MEDIACARD_RST# AG6 GSPI0_CS/GPIO83 L6 PCH_GPIO84 PCH_GPIO83 1 2
+3.3V_ALW_PCH suppoer DSW mode <30> MEDIACARD_RST# MEDIACARD_PWRENAP1 GPIO56 GSPI0_CLK/GPIO84 N6 PCH_GPIO85 100_0402_5% 7@RC292
<11,30> MEDIACARD_PWREN AL4 GPIO57 GSPI0_MISO/GPIO85 L8
SLATE_MODE_R BBS_BIT reference PDG0.9
NFC_DET# AT5 GPIO58 GSPI0_MOSI/GPIO86 R7 PCH_GPIO87 +1.05V_VCCST
si
<20> NFC_DET# AK4 GPIO59 GSPI1_CS/GPIO87 L5
PCH_GPIO44 3.3V_TP_EN
AB6 GPIO44 GPIO GSPI1_CLK/GPIO88 N7 H_THERMTRIP# 2 1
<30> MEDIACARD_IRQ# PCH_GPIO48 U4 GPIO47 GSPI1_MISO/GPIO89 K2 3.3V_TS_EN <22>
1K_0402_5% R24
@ T140 PAD~D PCH_GPIO49 Y3 GPIO48 GSPI_MOSI/GPIO90 J1 CPPE# 3.3V_HDD_EN <31>
2 1 PCH_GPIO44 @ T141 PAD~D TOUCH_PANEL_INTR# P3 GPIO49 UART0_RXD/GPIO91 K3 CPUSB# CPPE# <31>
<22> TOUCH_PANEL_INTR# Y2 GPIO50 UART0_TXD/GPIO92 J2 CPUSB# <31>
RC200 10K_0402_5% MPHYP_PWR_EN
2 1 MEDIACARD_IRQ# <39> MPHYP_PWR_EN KB_DET# AT3 HSIOPC/GPIO71 LPIO UART0_RTS/GPIO93 G1
<38,9> KB_DET# PCH_GPIO14 AH4 GPIO13 UART0_CTS/GPIO94 K4
RC205 10K_0402_5%
@ T138 PAD~D GPIO14 UART1_RXD/GPIO0
ne
3.3V_CAM_EN# AM4 G2
<22> 3.3V_CAM_EN# AG5 GPIO25 UART1_TXD/GPIO1 J3 1 2
SIO_EXT_SMI# LCD_CBL_DET# PCH_OPI_COMP
<37> SIO_EXT_SMI# PCH_GPIO46 AG3 GPIO45 UART1_RST/GPIO2 J4 LCD_CBL_DET# <22>
49.9_0402_1% RC168
GPIO46 UART1_CTS/GPIO3 F2 I2C0_SDA
C PCH_GPIO9 AM3 I2C0_SDA/GPIO4 F3 I2C0_SCL C
PCH_GPIO10 AM2 GPIO9 I2C0_SCL/GPIO5 G4 I2C1_SDA_TCH_PAD
@ T137 PAD~D P2 GPIO10 I2C1_SDA/GPIO6 F1 I2C1_SCL_TCH_PAD
<31> mSATA_DEVSLP C4 DEVSLP0/GPIO33 I2C1_SCL/GPIO7 E3 USH_DET#
L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4 CAM_MIC_CBL_DET# USH_DET# <29>
do
2 1 3.3V_CAM_EN# <25> HDD_DEVSLP SIO_EXT_SCI# N5 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 D3 PCH_GPIO66 CAM_MIC_CBL_DET# <22>
+3.3V_RUN
<37> SIO_EXT_SCI# V2 DEVSLP2/GPIO39 SDIO_D0/GPIO66 E4
RC211 100K_0402_5% SPKR TPM_ID0
2 1 <26> SPKR SPKR/GPIO81 SDIO_D1/GPIO67 C3
NFC_IRQ TPM_ID1
RC210 100K_0402_5% SDIO_D2/GPIO68 E2 SLP_ME_CSW_DEV#
2 1 MPHYP_PWR_EN SDIO_D3/GPIO69 SLP_ME_CSW_DEV# <36> IRQ_SERIRQ 2 1
@
RC169
R C169 10K_0402_5% 10 OF 19 Rev1p2 10K_0402_5% RC178
2 1 PCH_AUDIO_EN +3.3V_ALW_PCH USH_DET# 2 1
RC215 10K_0402_5% 10K_0402_5% RC282
In
RP7 LCD_CBL_DET# 2 1
I2C1_SDA_TCH_PAD @ RC174 2 1 0_0402_5% 10K_0402_5% RC189
1 8 MEDIACARD_RST# I2C1_SDA_VMM <21> CPPE# 2 1
2 7 PCH_GPIO46 I2C1_SCL_TCH_PAD @ RC176 2 1 0_0402_5% 100K_0402_5% RC185
3 6 I2C1_SCL_VMM <21> 2 1
SUSACK# CAM_MIC_CBL_DET#
4 5 SUSACK# <36,9>
SIO_EXT_SMI# 10K_0402_5% RC193
I2C1_SDA_TCH_PAD <38> CPUSB# 2 1
10K_8P4R_5% 100K_0402_5% RC191
I2C1_SCL_TCH_PAD <38> 2 1
I2C1_SDA_TCH_PAD
i-
2.2K_0402_5% RC201
I2C1_SCL_TCH_PAD 2 1
+3.3V_RUN 2.2K_0402_5% RC203
+3.3V_RUN +3.3V_RUN TPM_ID0 2 1
10K_0402_5% RC284
TPM_ID1 2 1
1
1
@
1K_0402_5%
10K_0402_5%
20K_0402_5% RC285
@RC283
@
RC218
RC181 SLP_ME_CSW_DEV# 2 1
is
RC283
10K_0402_5% 10K_0402_5% RC289

+3.3V_ALW_PCH +3.3V_RUN 3.3V_HDD_EN 2 1
B 10K_0402_5% RC295 B
2
2
I2C0_SDA 2 1
1
1
1K_0402_5%
1K_0402_5%
PCH_GPIO66 BBS_BIT TOUCH_PANEL_INTR# 2.2K_0402_5% RC204

@ RC222
I2C0_SCL 2 1
1
1K_0402_5%
RC190
2.2K_0402_5% RC208
1
1
@ RC288
1K_0402_5%
PCH_GPIO87 1 2
@ RC287
kn
RC180 @ 10K_0402_5% RC216
2
10K_0402_5%
PCH_GPIO15 SPKR
2
2
GPIO66 GPIO86 GPIO15 GPIO81
TOP-BLOCK SWAP OVERRIDE BOOT BIOS STRAP BIT BBS TLS CONFIDENTIALITY NO REBOOT STRAP
Te
Low depop RC288 (DEFAULT) :Enable HIGH LPC HIGH HIGH

High pop RC288:Diable LOW(DEFAULT) SPI LOW(DEFAULT) LOW(DEFAULT)
503118_503118_LPT_LP_PCH_EDS_Rev1_0
non use GPIO:
w.

ww
A
GPIO87 GPIO93 GPIO94 A
PROPRIETARY NOTE:
Title
0.3
5 4 3 2 1
5 4 3 2 1
CFG STRAPS for CPU
m
D D
CFG0
co
1K_0402_1%
1
@ RC232
2
a.
UC1S HASWELL_MCP_E
EAR-STALL/NOT STALL RESET SEQUENCE AFTER PCU PLL IS LOCKE
1:(Default) Normal Operation; No stall
CFG0
0:Lane Reversed
si
CFG0 AC60 AV63 PAD~D T20 @
<9> CFG0 CFG1 AC62 CFG0 RSVD_TP AU63 PAD~D T21 @
<9> CFG1 AC63 CFG1 RSVD_TP
<9> CFG2 CFG3 AA63 CFG2
<9> CFG3 AA60 CFG3 C63
CFG4 PAD~D T22 @
<9> CFG4 Y62 CFG4 RSVD_TP C62 CFG1
PAD~D T23 @
<9> CFG5 Y61 CFG5 RSVD_TP B43 PAD~D T24 @
<9> CFG6 CFG6 RSVD
1K_0402_1%
ne
Y60
<9> CFG7 CFG7
1
CFG8 V62 A51 PAD~D T25 @
<9> CFG8 CFG8 RSVD_TP
@ RC233
CFG9 V61 B51 PAD~D T26 @
<9> CFG9 CFG10 V60 CFG9 RSVD_TP
C <9> CFG10 U60 CFG10 L60 C
PAD~D T27 @
<9> CFG11 T63 CFG11 RESERVED RSVD_TP
<9> CFG12
2
T62 CFG12 N60 PAD~D T28 @
<9> CFG13 T61 CFG13 RSVD
<9> CFG14 T60 CFG14 W23 PAD~D T29 @
do
<9> CFG15 CFG15 RSVD Y22 PAD~D T30 @
AA62 RSVD AY15 PROC_OPI_RCOMP
<9> CFG16 U63 CFG16 PROC_OPI_RCOMP
<9> CFG18 AA61 CFG18 AV62 PAD~D T31 @ PCH/PCH LESS MODE SELECTION
<9> CFG17 U62 CFG17 RSVD D58 PAD~D T32 @
<9> CFG19 CFG19 RSVD
CFG_RCOMP V63 P22 1:(Default) Normal Operation
CFG_RCOMP VSS N21 CFG1
VSS 0:Lane Reversed
In
@ T33 PAD~D A5
RSVD P20 PAD~D T34 @
@ T35 PAD~D E1 RSVD R20 PAD~D T36 @
@ T37 PAD~D D1 RSVD RSVD
@ T38 PAD~D J20 RSVD
@ T39 PAD~D H18 RSVD
TDI_IREF B12 RSVD
TD_IREF
19 OF 19 Rev1p2
i-
2 1 CFG_RCOMP
RC235 49.9_0402_1%
1 2 TDI_IREF PROC_OPI_RCOMP 1 2
RC236 8.2K_0402_1%
is 49.9_0402_1% RC237
B B
kn
CFG4
1K_0402_1%
CFG9 CFG8
1
CFG10
1
1
1K_0402_1%
1K_0402_1%
RC238
Te
1
1K_0402_1%
@ RC240
@ RC241
@ RC239
2
2
2
2
w.
Display Port Presence Strap

NO SVID PROTOCOL CAPABLE VR CONNECTED ALLOW THE USE OF NOA ON LOCKED UNITS
SAFE MODE BOOT 1 : Disabled; No Physical Display Port
1: VRS support SVID protocol are present 1: Enable(Default): Noa will be disable in
1: POWER FEATURES ACTIVATED DURING CFG4 attached to Embedded Display Port
0:No VR support SVID is present locked units and enable in un-locked units
RESET CFG9 CFG8 0 : Enabled; An external Display Port device is
CFG10 The chip will not generate(OR Respond to) 0: Enable Noa will be available pegardless of
ww
A A
0: POWER FEATURES (ESPECIALLY CLOCK connected to the Embedded Display Port
SVID activity the locking of the unit
GATINE ARE NOT ACTIVATED
PROPRIETARY NOTE:
Title
0.3
5 4 3 2 1
5 4 3 2 1
m
D D
2 1 1
0_0402_5% @ RC254
co
HASWELL_MCP_E
UC1Q
DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3

DC_TEST_AY3_AW3 AY3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4 DC_TEST_A4
DC_TEST_AY60 AY60 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4
a.
DC_TEST_AY61_AW61 AY61 DAISY_CHAIN_NCTF_AY60 A60 DC_TEST_A60
DC_TEST_AY62_AW62 AY62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A61 DC_TEST_A61_B61
TP_DC_TEST_B2 B2 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A62 DC_TEST_A62 2
2 1
DC_TEST_A3_B3 B3 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 AV1 DC_TEST_AV1 0_0402_5% @ RC266
DC_TEST_A61_B61 B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 AW1 DC_TEST_AW1 2 1
B62 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW2 DC_TEST_AY2_AW2 0_0402_5% @ RC268
DC_TEST_B62_B63 B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW3
C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW61
4
si
DC_TEST_C1_C2 C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY62_AW62
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW63 DC_TEST_AW63
DAISY_CHAIN_NCTF_AW63
17 OF 19 Rev1p2
3
2 1
0_0402_5% @ RC269
ne
C C
Package Daisy Chain:

1.B2-PKG-C1-PCB-C2-PKG-B3-PCB-A3-PKG-A4
do
2.A62-PKG-A61-PCB-B61-PKG-B62-PCB-B63-PKG-A60
3.AY60-PKG-AW61-PCB-AY61-PKG-AW62-PCB-AY62-PKG-AW63
4.AW1-PKG-AW3-PCB-AY3-PKG-AW2-PCB-AY2-PKG-AV1
In
HASWELL_MCP_E
UC1R
N23 @
RSVD_N23 PAD~D T48
RSVD R23 RSVD_R23 @
PAD~D T49
RSVD T23 RSVD_T23 @
AT2 PAD~D T51
@T50 PAD~D RSVD_AT2 RSVD @
RSVD U10 RSVD_U10 PAD~D T53
i-
@T52 PAD~D RSVD_AU44 AU44 RSVD
@T54 PAD~D RSVD_AV44 AV44 RSVD
@T55 PAD~D RSVD_D15 D15 RSVD @
RSVD AL1 RSVD_AL1 PAD~D T56
RSVD AM11 RSVD_AM11 @
PAD~D T57
RSVD AP7 @
RSVD_AP7 PAD~D T59
@T58 PAD~D RSVD_F22 F22 RSVD @
RSVD AU10 RSVD_AU10 PAD~D T61
@T60 PAD~D RSVD_H22 H22 RSVD @
RSVD AU15 RSVD_AU15 PAD~D T63
@T62 PAD~D RSVD_J21 J21 RSVD @
RSVD AW14 RSVD_AW14 PAD~D T64
@
is RSVD
RSVD
AY14 RSVD_AY14 PAD~D T65
B B
18 OF 19 Rev1p2
kn
Te
w.
ww
A A
PROPRIETARY NOTE:
Title
0.3
5 4 3 2 1
5 4 3 2 1
+1.05V_RUN
+1.35V_MEM +3.3V_ALW
150_0402_1%
1 2
1
EMC@ C452 22U_0603_6.3V6M
+1.05V_RUN +VCCIO_OUT VDDQ DECOUPLING
RC253
+1.35V_MEM
+3.3V_RUN +5V_ALW Reference ULT DDRDG_080912 change to10uX6 2.2uX4
2 1 1 2
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
@ RC242 0_0603_5% EMC@ C453 22U_0603_6.3V6M
1 1 1 1 1 1 1 1 1 1
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
CPU_PWR_DEBUG# @ @
+VCC_CORE +1.35V_MEM
CC81
CC52
CC12
CC13
CC16
CC17
CC18
CC19
CC20
CC21
RESISTOR STUFFING OPTIONS ARE
10K_0402_5%
PROVIDED FOR TESTING PURPOSES
m
1
1 2 2 2 2 2 2 2 2 2 2 2
@
D @ C454 22U_0603_6.3V6M D
RC258
+VCC_CORE +1.05V_RUN
co
2
1 2
@ C458 22U_0603_6.3V6M
+VCC_CORE +3.3V_RUN
+1.05V_VCCST +3.3V_RUN 1 2
@ C459 22U_0603_6.3V6M
a.
+VCC_CORE +1.35V_MEM
1
@
+VCC_CORE
@
HASWELL_MCP_E
RC255 RC259 1 2 UC1L
10K_0402_5% 10K_0402_5% @ C460 22U_0603_6.3V6M
@ T66 PAD~D L59 C36
+1.35V_MEM @ T67 PAD~D J58 RSVD VCC C40
2
+1.35V_MEM +1.05V_RUN RSVD VCC C44
H_VR_EN 2 1 H_VR_READY AH26 VCC C48
si
10K_0402_5% RC256 1 2 AJ31 VDDQ VCC C52
@ C461 22U_0603_6.3V6M AJ33 VDDQ VCC C56
+3.3V_ALW +1.05V_VCCST AJ37 VDDQ VCC E23
AN33 VDDQ VCC E25
AP43 VDDQ VCC E27
AR48 VDDQ VCC E29
H_VCCST_PWRGD AY35 VDDQ VCC E31
VDDQ VCC
100P_0402_50V8J
AY40 E33
VDDQ VCC
ne
UC4 1 AY44 E35
1 5 1 2 1K_0402_5% @ AY50 VDDQ VCC E37
NC VCC RC243 VDDQ VCC
CC22
@ CC24 0.1U_0402_25V6 E39
@ RC263 2 1 0_0402_5% 2 F59 VCC E41
<37,9> RESET_OUT# +VCC_CORE
1
C A 4 H_VCCST_PWRGD 2 N58 VCC VCC E43 C
Y @ T68 PAD~D RSVD VCC
3 @ T69 AC58 E45
GND PAD~D RSVD VCC E47
74AUP1G07GW_TSSOP5 VCCSENSE E63 VCC E49
AB23 VCC_SENSE VCC E51
do
@ T70 PAD~D RSVD VCC
A59 E53
+VCCIO_OUT VCCIO_OUT VCC
E20 E55
+VCCIOA_OUT VCCIOA_OUT VCC
@ T71 PAD~D AD23 E57
AA23 RSVD VCC F24
+1.05V_VCCST ESD Request @ T72 PAD~D
AE59 RSVD VCC F28
@ T73 PAD~D
SVID ALERT H_CPU_SVIDALRT# L62
RSVD
VIDALERT
VCC
VCC
VCC
F32
F36
75_0402_1%
VIDSCLK N63 F40

<46> VIDSCLK VIDSCLK VCC
1
In
VIDSOUT L63 F44
VIDSOUT VCC
RC244
H_VCCST_PWRGD @RC245
@ RC245 1 2 0_0402_5% VCCST_PWRGD B59 HSW ULT POWER F48
CAD Note: Place the PU resistors close to CPU <9> H_VCCST_PWRGD H_VR_EN @RC246
@ RC246 1 2 0_0402_5% VR_EN F60 VCCST_PWRGD VCC F52
<46> H_VR_EN VR_EN VCC
RC224 close to CPU 300 - 1500mils <46> H_VR_READY
H_VR_READY @RC247
@ RC247 1 2 0_0402_5% VR_READY C59
VR_READY VCC
F56
G23
2
D63 VCC G25

2 1 H_CPU_SVIDALRT# CPU_PWR_DEBUG# H59 VSS VCC G27
<46> VIDALERT_N <9> CPU_PWR_DEBUG# P62 PWR_DEBUG VCC G29
43_0402_5% RC248
P60 VSS VCC G31
i-
@ T74 PAD~D RSVD_TP VCC
@ T75 P61 G33
PAD~D N59 RSVD_TP VCC G35
+1.05V_VCCST @ T76 PAD~D RSVD_TP VCC
@ T77 N61 G37
SVID DATA @ T78
PAD~D
PAD~D
T59 RSVD_TP
RSVD
VCC
VCC
G39
110_0402_1%
@ T79 AD60 G41

PAD~D RSVD VCC
1
AD59 G43
CAD Note: Place the PU resistors close to CPU @ T80 PAD~D RSVD VCC
RC249
@ T81 AA59 G45

PAD~D RSVD VCC
RC249close to CPU 300 - 1500mils @ T82 PAD~D
AE60 G47
is @ T83
@ T84
PAD~D
PAD~D
AC59
AG58
RSVD
RSVD
VCC
VCC
G49
G51
2
B U59 RSVD VCC G53 B

@ T85 PAD~D RSVD VCC
VIDSOUT @ T86 V59 G55
<46> VIDSOUT PAD~D RSVD VCC G57
AC22 VCC H23
+1.05V_VCCST VCCST VCC
AE22 J23
AE23 VCCST VCC K23
VCCST VCC K57
kn
AB57 VCC L22

+VCC_CORE +VCC_CORE VCC VCC
AD57 M23
reference ULT CRB AG57 VCC VCC M57
VCC_SENSE C24 VCC
VCC
VCC
VCC
P57
100_0402_1%
C28 U57
VCC VCC
1
C32 W57
VCC VCC
RC250
12 OF 19 Rev1p2
Te
2
+1.05V_RUN +1.05V_VCCST
PJP11
VCCSENSE 1 2
<46> VCCSENSE
22U_0603_6.3V6M
1U_0402_6.3V6K
PAD-OPEN1x1m
@
CAD Note: RC250 SHOULD BE PLACED CLOSE TO CPU 1 1

w.
CC50
CC26
2 2
ww
A A
PROPRIETARY NOTE:
Title
0.3
5 4 3 2 1
5 4 3 2 1
+1.05V_MODPHY +1.05V_MODPHY_PCH
1 2
@ RC262 0_0805_5% +1.05V_M +1.05V_RUN
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CC29 place near K9; 1 1 1
@
CC74
CC27
CC29
CC27 place near L10
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
1 @ 1 @ 1 @
2 2 2
CC74 place near M9
CC73
CC71
CC72
+ + +
VCCHSIO
2 2 2
S0 Iccmax = 1.838A
m
D D
+1.05V_MODPHY
+PCH_AUSB3PLL
co
LC1
1 2
22U_0603_6.3V6M
22U_0603_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30% 1 1
CC76
CC42 place near B18 CC42

2 2 UC1M HASWELL_MCP_E
VCCUSB3PLL
K9
S0 Iccmax = 41mA +1.05V_MODPHY_PCH
a.
+1.05V_RUN L10 VCCHSIO
M9 VCCHSIO +RTC_CELL
N8 VCCHSIO mPHY AH11
VCC1_05 VCCSUS3_3 +PCH_RTC_VCCSUS3_3 CC35,CC38, CC39 place near AG10
1U_0402_6.3V6K
P9 RTC AG10
+1.05V_MODPHY +PCH_ASATA3PLL VCC1_05 VCCRTC
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
1 +PCH_AUSB3PLL B18 AE7 +DCPRRTC 1 2
LC2 VCCUSB3PLL DCPRTC
@
+PCH_ASATA3PLL B11 CC36 1 1 1
VCCSATA3PLL +3.3V_M
CC31
1 2 0.1U_0402_10V7K @
22U_0603_6.3V6M
22U_0603_6.3V6M
CC38
CC39
CC35
2.2UH_LQM2MPN2R2NG0L_30%
1 1
2 Y20 SPI Y8 CC40 place near Y8
RSVD VCCSPI
si
2 2 2
0.1U_0402_10V7K
AA21 OPI
CC49 place near B11 VCCAPLL
CC77
CC49
+V1.05S_APLLOPI W21 1
VCCAPLL
@
AG14
VCCSATA3PLL 2 2 VCCASW +1.05V_M
CC40
AG13
VCCASW CC34 and CC33 place near +1.05V_RUN
S0 Iccmax = 42mA +3.3V_ALW_PCH J13 USB3 2
+PCH_DCPSUS DCPSUS3 J11 J11; CC37 place near AE8
VCC1_05
0.1U_0402_10V7K
H11
VCC1_05
10U_0603_6.3V6M
AH14 AXALIA/HDA H15 +PCH_VCCDSW 2 1
+1.05V_RUN +V1.05S_APLLOPI VCCHDA VCC1_05
ne
+1.05V_M
1U_0402_6.3V6K
1U_0402_6.3V6K
C AE8 5.11_0402_1% RC275 C
+PCH_VCCDSW_R
LC5 1 CC44 place near AH14 VCC1_05 1 1 1
CC44
AF22
VCC1_05
22U_0805_6.3V6M
CC37
CC33
CC34
1 2 AH13 VRM/USB2/AZALIA AG19 +PCH_VCCDSW
+3.3V_ALW_PCH DCPSUS2 DCPSUSBYP
100U_1206_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
2.2UH_LQM2MPN2R2NG0L_30% CORE AG20
1 1
2 DCPSUSBYP AE9 CC46 CC47 place near AE9 1 1
2 2 2
VCCASW
@
AF9
CC56 place near AA21 CC28 place near AC9 VCCASW
CC55
CC56
CC46
CC47
AC9 AG8
VCCSUS3_3 VCCASW
1U_0402_6.3V6K
AA9 AD10
VCCAPLL 2 2 +3.3V_RUN VCCSUS3_3 DCPSUS1 +PCH_DCPSUS1 2 2
22U_0603_6.3V6M
+PCH_VCCDSW3_3 AH10 AD8

VCCDSW3_3 DCPSUS1
do
V8 GPIO/LCC
S0 Iccmax = 57mA 1 CC43 place near V8 VCC3_3 1
CC28
CC65
W9
VCC3_3 +3.3V_RUN
22U_0603_6.3V6M
J15 +1.5V_THERMAL
THERMAL SENSOR VCCTS1_5 K14
2 1 VCC3_3 CC59 place near K14 2
0.1U_0402_10V7K
K16
VCC3_3 CC65 place near AG19
CC43
1
+1.05V_M +PCH_DCPSUS +3.3V_RUN
2 +1.05V_RUN
@
CC59
RC276 J18
1 2
+PCH_VCC1P05
K19 VCCCLK SDIO/PLSS U8 CC45 place near U8
VCCCLK VCCSDIO 2
1U_0402_6.3V6K
A20 T9
In
+PCH_VCCACLKPLL VCCACLKPLL VCCSDIO +PCH_RTC_VCCSUS3_3 +3.3V_ALW_PCH
0_0603_5% J17 1
VCCCLK
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
R21
CC63 close to Pin J17 VCCCLK
CC45
T21 LPT LP POWER 2 1
CC66 place near AH13 1 1 1 1 1 VCCCLK
@ CC66
@ CC61
@ CC62
K18 SUS OSCILLATOR AB8 0_0402_5% @ RC261

CC64 close to Pin R21 RSVD DCPSUS4 +PCH_DCPSUS4 2
CC63
CC64
M20
CC61 CC62 place near J13 V21 RSVD +1.05V_RUN +3.3V_ALW
2 2 2 2 2 AE20 RSVD AC20
DcpSus2 +3.3V_ALW_PCH VCCSUS3_3 RSVD CC60 place near AG16
1U_0402_6.3V6K
AE21 AG16 2 1
VCCSUS3_3 USB2 VCC1_05 AG17 0_0402_5% @ RC264
S0 Iccmax = 25mA
i-
VCC1_05
CC60
1 1
1U_0402_6.3V6K
DcpSus3 CC30 place near AH11
CC30
13 OF 19 Rev1p2
B S0 Iccmax = 10mA 2 2 VCCSUS3_3 B
S0 Iccmax = 63mA
+3.3V_ALW_PCH +PCH_VCCDSW3_3
@ RC265
1 2
0_0402_5%
is
+PCH_DCPSUS1 +1.05V_M
+3.3V_ALW
1U_0402_6.3V6K
2 1
1U_0402_6.3V6K
1 2 0_0402_5% @ RC272
@ RC267 0_0402_5% 1 1
@ CC54
@
CC54 place near AD10

CC32
CC32 place near AH10

kn
2 2 DCPSUS1
VCCDSW3_3
S0 Iccmax = 109mA
S0 Iccmax = 114mA
+1.05V_RUN +PCH_VCC1P05
+PCH_DCPSUS4 @ +1.05V_M
LC3 LC4
Te
1U_0402_6.3V6K
1 2 2 1
100U_1206_6.3V6M
1U_0402_6.3V6K
2.2UH_LQM2MPN2R2NG0L_30% 1 1 2.2UH_LQM2MPN2R2NG0L_30%
100U_1206_6.3V6M
CC51 place near J18 1 1
CC79
CC51
@
CC53 place near AB8
CC53
CC75
VCCCLK 2 2
2 2 DCPSUS4
S0 Iccmax = 200mA
S0 Iccmax = 1mA
w.
A A
+PCH_VCCACLKPLL
+1.05V_RUN
LC6
1U_0402_6.3V6K
1 2
100U_1206_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30% 1 1
PROPRIETARY NOTE:
CC58 place near A20
CC78
CC58
ww
Title
VCCACLKPLL 2 2 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT MCP(11/12)
S0 Iccmax = 31mA 0.3
5 4 3 2 1
5 4 3 2 1
m
D D
co
HASWELL_MCP_E HASWELL_MCP_E
UC1N UC1O UC1P HASWELL_MCP_E
H17
A11 AJ35 AP22 AV59 D33 VSS H57
A14 VSS VSS AJ39 AP23 VSS VSS AV8 D34 VSS VSS J10
A18 VSS VSS AJ41 AP26 VSS VSS AW16 D35 VSS VSS J22
a.
A32 VSS VSS AJ47 AP31 VSS VSS AW35 D39 VSS VSS K1
A36 VSS VSS AJ50 AP38 VSS VSS AW37 D41 VSS VSS K12
A40 VSS VSS AJ52 AP39 VSS VSS AW4 D42 VSS VSS L13
si
AA1 VSS VSS AJ63 AR11 VSS VSS AW50 D49 VSS VSS L58
AA58 VSS VSS AK23 AR15 VSS VSS AW51 D5 VSS VSS L61
AB10 VSS VSS AK3 AR17 VSS VSS AW59 D50 VSS VSS L7
AB20 VSS VSS AK52 AR23 VSS VSS AW60 D51 VSS VSS M22
AB22 VSS VSS AL10 AR31 VSS VSS AY11 D53 VSS VSS N10
AB7 VSS VSS AL13 AR33 VSS VSS AY16 D54 VSS VSS N3
AC61 VSS VSS AL17 AR39 VSS VSS AY18 D55 VSS VSS P59
AD21 VSS VSS AL20 AR43 VSS VSS AY22 D57 VSS VSS P63
VSS VSS VSS VSS VSS VSS
ne
AD3 AL22 AR49 AY24 D59 R10
AD63 VSS VSS AL23 AR5 VSS VSS AY26 D62 VSS VSS R22
AE10 VSS VSS AL26 AR52 VSS VSS AY30 D8 VSS VSS R8
AE5 VSS VSS AL29 AT13 VSS VSS AY33 E11 VSS VSS T1
C AE58 VSS VSS AL31 AT35 VSS VSS AY4 E17 VSS VSS T58 C
AF11 VSS VSS AL33 AT37 VSS VSS AY51 F20 VSS VSS U20
do
AF17 VSS VSS AL45 AT46 VSS VSS AY6 F38 VSS VSS V10
AF18 VSS VSS AL46 AT49 VSS VSS B20 F42 VSS VSS V3
AG1 VSS VSS AL51 AT61 VSS VSS B24 F46 VSS VSS V7
AG11 VSS VSS AL52 AT62 VSS VSS B26 F50 VSS VSS W20
AG21 VSS VSS AL54 AT63 VSS VSS B28 F54 VSS VSS W22
AG23 VSS VSS AL57 AU1 VSS VSS B32 F58 VSS VSS Y10
AG60 VSS VSS AL60 AU16 VSS VSS B36 F61 VSS VSS Y59
AG61 VSS VSS AL61 AU18 VSS VSS B4 G18 VSS VSS Y63
VSS VSS VSS VSS VSS VSS
In
AG62 AM1 AU20 B40 G22
AG63 VSS VSS AM17 AU22 VSS VSS B44 G3 VSS
AH17 VSS VSS AM23 AU24 VSS VSS B48 G5 VSS V58
AH19 VSS VSS AM31 AU26 VSS VSS B52 G6 VSS VSS AH46
AH20 VSS VSS AM52 AU28 VSS VSS B56 G8 VSS VSS V23
AH22 VSS VSS AN17 AU30 VSS VSS B60 H13 VSS VSS E62
AH24 VSS VSS AN23 AU33 VSS VSS C11 VSS VSS_SENSE AH16 VSSSENSE <46>
AH28 VSS VSS AN31 AU51 VSS VSS C14 16 OF 19 Rev1p2 VSS
VSS VSS VSS VSS
1
100_0402_1%
AH30 AN32 AU53 C18
i-
AH32 VSS VSS AN35 AU55 VSS VSS C20
VSS VSS VSS VSS
RC260
AH34 AN36 AU57 C25
AH36 VSS VSS AN39 AU59 VSS VSS C27
AH38 VSS VSS AN40 AV14 VSS VSS C38
2
AH44 VSS VSS AN45 AV24 VSS VSS D12
AH51
AH53
VSS
VSS
VSS
VSS
VSS
VSS
AN48
AN49
is
AV33
AV34
VSS
VSS
VSS
VSS
VSS
VSS
D18
D2
CAD Note: RC260 SHOULD BE PLACED CLOSE TO CPU
B AH55 AN51 AV36 D21 B
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ25 VSS VSS AP10 AV49 VSS VSS D29
kn

VSS VSS VSS 15 OF 19 Rev1p2 VSS
14 OF 19 Rev1p2
Te
w.
ww
A A
PROPRIETARY NOTE:
Title
0.3
5 4 3 2 1
5 4 3 2 1
1 2 H=4mm
+SM_VREF_DQ0_DIMM1
@ RD1 0_0402_5% +DIMM1_VREF_DQ Reverse Type
+1.35V_MEM +1.35V_MEM 2-3A to 1 DIMMs/channel
JDIMM1 CONN@
1 2
3 VREF_DQ VSS1 4 DDR_A_D9
VSS2 DQ4
2.2U_0402_6.3V6M
0.1U_0402_25V6
DDR_A_D13 5 6 DDR_A_D12
DDR_A_D8 7 DQ0 DQ5 8 +1.35V_MEM
Populate RD1, De-Populate RD7 for Intel DDR3 DQ1 VSS3
1 1 9 10 DDR_A_DQS#1
VREFDQ multiple methods M1 VSS4 DQS#0
CD2
11 12 DDR_A_DQS1
Populate RD7, De-Populate RD1 for Intel DDR3 DM0 DQS0
CD1
13 14
VSS5 VSS6
1
VREFDQ multiple methods M3 DDR_A_D14 15 16 DDR_A_D15
m
2 2 DDR_A_D10 17 DQ2 DQ6 18 DDR_A_D11 RD3
D 19 DQ3 DQ7 20 470_0402_5% D
DDR_A_D29 21 VSS7 VSS8 22 DDR_A_D25
DDR_A_D28 23 DQ8 DQ12 24 DDR_A_D24
2
DQ9 DQ13
co
All VREF traces should 25 26
DDR_A_DQS#3 27 VSS9 VSS10 28 1 2
have 10 mil trace width DQS#1 DM1 <19> DDR3_DRAMRST# DDR3_DRAMRST#_CPU <9>
0.1U_0402_25V6
DDR_A_DQS3 29 30 DDR3_DRAMRST# @RC279
@ RC279 0_0402_5%
31 DQS1 RESET# 32
DDR_A_D30 33 VSS11 VSS12 34 DDR_A_D27 @
<8> DDR_A_DQS#[0..7] DQ10 DQ14 1
CD3
DDR_A_D31 35 36 DDR_A_D26
37 DQ11 DQ15 38
<8> DDR_A_D[0..63] DDR_A_D44 39 VSS13 VSS14 40 DDR_A_D45
DDR_A_D41 41 DQ16 DQ20 42 DDR_A_D40 2
a.
<8> DDR_A_DQS[0..7] 43 DQ17 DQ21 44
DDR_A_DQS#5 45 VSS15 VSS16 46 +1.35V_MEM
<8> DDR_A_MA[0..15] DDR_A_DQS5 47 DQS#2 DM2 48
DQS2 VSS17
1
1.8K_0402_1%
49 50 DDR_A_D42
DDR_A_D43 51 VSS18 DQ22 52 DDR_A_D46
DQ18 DQ23 CAD NOTE
Layout Note: Note: DDR_A_D47 53 54
RC217
55 DQ19 VSS19 56 DDR_A_D52 PLACE THE CAP NEAR TO
Place near JDIMM1 Check voltage tolerance of DDR_A_D51 57 VSS20 DQ28 58 DDR_A_D53 DIMM RESET PIN +SM_VREF_DQ0_DIMM1 +SM_VREF_DQ0
si
2
DQ24 DQ29
VREF_DQ at the DIMM socket DDR_A_D50 59
DQ25 VSS21
60
61 62 DDR_A_DQS#6
63 VSS22 DQS#3 64 DDR_A_DQS6 RC173 1 2
65 DM3 DQS3 66
VSS23 VSS24 1
DDR_A_D49 67 68 DDR_A_D54 2_0402_1%
+1.35V_MEM DQ26 DQ30
1.8K_0402_1%
DDR_A_D48 69 70 DDR_A_D55 CC70
DQ27 DQ31
1
71 72 0.022U_0402_16V7K
VSS25 VSS26 2
RC221
ne
1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA RC195

<8> DDR_CKE0_DIMMA DDR_CKE1_DIMMA <8>
2
75 CKE0 CKE1 76
VDD1 VDD2 24.9_0402_1%
CD4
CD5
CD6
CD7
CD8
CD9
CD10
CD11
C 77 78 DDR_A_MA15 C
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
<8> DDR_A_BS2
2
2 2 2 2 2 2 2 2 81 BA2 A14 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
do
87 A9 A7 88
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
+1.35V_MEM 99 A1 A0 100
M_CLK_DDR0 101 VDD9 VDD10 102 M_CLK_DDR1
<8> M_CLK_DDR0 CK0 CK1 M_CLK_DDR1 <8>
In
M_CLK_DDR#0 103 104 M_CLK_DDR#1
<8> M_CLK_DDR#0 105 CK0# CK1# 106 M_CLK_DDR#1 <8>
VDD11 VDD12
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_A_MA10 107 108 DDR_A_BS1

A10/AP BA1 DDR_A_BS1 <8>
DDR_A_BS0 109 110 DDR_A_RAS#
<8> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <8> DDR3L SODIMM ODT GENERATION
330U_D3_2.5VY_R6M
1 111 112
DDR_A_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMA# +5V_ALW +1.35V_MEM
1 1@ 1 1 1@ 1 1 1 <8> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <8>
CD14
CD15
CD16
CD17
CD18
CD19
CD20
CD21
CD22
+ DDR_A_CAS# 115 116 M_ODT0 QD1

<8> DDR_A_CAS# 117 CAS# ODT0 118 BSS138-G_SOT23-3
VDD15 VDD16
220K_0402_5%~D
DDR_A_MA13 119 120 M_ODT1
i-
A13 ODT1
1
2 2 2 2 2 2 2 2 2 DDR_CS1_DIMMA# 121 122 +SM_VREF_CA_DIMM 1 3
S
<8> DDR_CS1_DIMMA# S1# NC2
R28
123 124
125 VDD17 VDD18 126 +SM_VREF_CA_DIMM1 1 2 1 2 M_ODT0
NCTEST VREF_CA
2.2U_0402_6.3V6M
0.1U_0402_25V6
127 128 @ RD12 0_0402_5% R29 66.5_0402_1%
G
2
DDR_A_D0 129 VSS27 VSS28 130 DDR_A_D5 1 2 M_ODT1
2
DDR_A_D1 131 DQ32 DQ36 132 DDR_A_D4 0.675V_DDR_VTT_ON R30 66.5_0402_1%
DQ33 DQ37 1 1
CD12
CD13
133 134 1 2
DDR_A_DQS#0 135 VSS29 VSS30 136 M_ODT2 <19>
R31 66.5_0402_1%
is DQS#4 DM4
2
DDR_A_DQS0 137 138 1 2
139 DQS4 VSS31 140 DDR_A_D3 2 2 M_ODT3 <19>
@R32 R33 66.5_0402_1%
B DDR_A_D2 141 VSS32 DQ38 142 DDR_A_D7 B
Layout Note: DQ34 DQ39 2M_0402_5%
DDR_A_D6 143 144
Place near JDIMM1.203,204 145 DQ35 VSS33 146 DDR_A_D18
1
DDR_A_D21 147 VSS34 DQ44 148 DDR_A_D19
DDR_A_D20 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#2
153 VSS36 DQS#5 154 DDR_A_DQS2
kn
155 DM5 DQS5 156

DDR_A_D17 157 VSS37 VSS38 158 DDR_A_D22 +1.35V_MEM
DDR_A_D16 159 DQ42 DQ46 160 DDR_A_D23
+0.675V_DDR_VTT 161 DQ43 DQ47 162 @CD23
@ CD23
DDR_A_D36 163 VSS39 VSS40 164 DDR_A_D37 U5 0.1U_0402_25V6
DDR_A_D33 165 DQ48 DQ52 166 DDR_A_D32 1 5 1 2
167 DQ49 DQ53 168 NC VCC
DDR_A_DQS#4 169 VSS41 VSS42 170 2
Te
DQS#6 DM6 <9> DDR_PG_CTRL A

0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_A_DQS4 171 172 4 0.675V_DDR_VTT_ON

173 DQS6 VSS43 174 3 Y 0.675V_DDR_VTT_ON <43>
1 1 1 1 1 1 DDR_A_D35
VSS44 DQ54 GND
CD26
CD27
CD28
CD29
CD30
CD31
DDR_A_D34 175 176 DDR_A_D39

DDR_A_D38 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_A_D63 74AUP1G07GW_TSSOP5
2 2 2 2 2 2 DDR_A_D62 181 VSS46 DQ60 182 DDR_A_D59
DDR_A_D58 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDR_A_DQS#7
VSS48 DQS#7
w.
187 188 DDR_A_DQS7

189 DM7 DQS7 190
DDR_A_D60 191 VSS49 VSS50 192 DDR_A_D56
DDR_A_D61 193 DQ58 DQ62 194 DDR_A_D57
195 DQ59 DQ63 196
@RD5
@ RD5 1 2 0_0402_5% 197 VSS51 VSS52 198
199 SA0 EVENT# 200
+3.3V_RUN VDDSPD SDA DDR_XDP_WAN_SMBDAT <19,31,7,9>
1 2 201 202
203 SA1 SCL 204 DDR_XDP_WAN_SMBCLK <19,31,7,9>
@RD6
@ RD6 0_0402_5%
ww
1 1 VTT1 VTT2 +0.675V_DDR_VTT

2.2U_0402_6.3V6M
0.1U_0402_25V6
A A
+0.675V_DDR_VTT
CD24
@ 205 206
G1 G2
CD25
2 2 FOX_AS0A621-U4R6-7H
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDRIII-SODIMM SLOT1
5 4 3 2 1
5 4 3 2 1
H=4mm 2-3A to 1 DIMMs/channel

+DIMM2_VREF_DQ +1.35V_MEM +1.35V_MEM
JDIMM2 CONN@
1 2 1 2
+SM_VREF_DQ1_DIMM2
@RD7
@ RD7 0_0402_5% 3 VREF_DQ
VSS2
VSS1
DQ4
4 DDR_B_D12 Reverse Type
2.2U_0402_6.3V6M
0.1U_0402_25V6
DDR_B_D8 5 6 DDR_B_D9
DDR_B_D14 7 DQ0 DQ5 8
9 DQ1 VSS3 10 DDR_B_DQS#1
1 1 VSS4 DQS#0
CD33
11 12 DDR_B_DQS1
DM0 DQS0
CD32
Populate RD4, De-Populate RD8 for Intel DDR3 13 14
DDR_B_D10 15 VSS5 VSS6 16 DDR_B_D13 +1.35V_MEM
VREFDQ multiple methods M1 2 2 DDR_B_D11 17 DQ2 DQ6 18 DDR_B_D15
DQ3 DQ7
1
Populate RD8, De-Populate RD4 for Intel DDR3
1.8K_0402_1%
19 20
m
DDR_B_D28 21 VSS7 VSS8 22 DDR_B_D25
D
VREFDQ multiple methods M3 DQ8 DQ12 D
RC67
25 DQ9 DQ13 26
DDR_B_DQS#3 27 VSS9 VSS10 28 +SM_VREF_CA_DIMM +SM_VREF_CA
2
DQS#1 DM1
co
0.1U_0402_25V6
DDR_B_DQS3 29 30 DDR3_DRAMRST#
31 DQS1 RESET# 32 DDR3_DRAMRST# <18>
<8> DDR_B_DQS#[0..7] Note: VSS11 VSS12
DDR_B_D26 33 34 DDR_B_D30 1 @ RC68 1 2
Check voltage tolerance of DQ10 DQ14
CD34
All VREF traces should DDR_B_D27 35 36 DDR_B_D31 1
<8> DDR_B_D[0..63] DQ11 DQ15
have 10 mil trace width VREF_DQ at the DIMM socket 37
VSS13 VSS14
38 2_0402_1%
1.8K_0402_1%
DDR_B_D40 39 40 DDR_B_D45 CC67
<8> DDR_B_DQS[0..7] DQ16 DQ20
1
DDR_B_D41 41 42 DDR_B_D44 2
DQ17 DQ21 0.022U_0402_16V7K
2
RC69
43 44
<8> DDR_B_MA[0..15] DDR_B_DQS#5 45 VSS15 VSS16 46
a.
DQS#2 DM2
1
DDR_B_DQS5 47 48
49 DQS2 VSS17 50 DDR_B_D47 RC83
2
DDR_B_D46 51 VSS18 DQ22 52 DDR_B_D43
Layout Note: DQ18 DQ23 CAD NOTE 24.9_0402_1%
DDR_B_D42 53 54
Place near JDIMM2 55 DQ19 VSS19 56 DDR_B_D61 PLACE THE CAP NEAR TO
2
DDR_B_D56 57 VSS20 DQ28 58 DDR_B_D60 DIMM RESET PIN
DDR_B_D57 59 DQ24 DQ29 60
si
63 VSS22 DQS#3 64 DDR_B_DQS7
65 DM3 DQS3 66
DDR_B_D58 69 DQ26 DQ30 70 DDR_B_D62
+1.35V_MEM 71 DQ27 DQ31 72
VSS25 VSS26 +1.35V_MEM
1
1.8K_0402_1%
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
ne
DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
<8> DDR_CKE2_DIMMB 75 CKE0 CKE1 76 DDR_CKE3_DIMMB <8>
RC130
1 1 1 1 1 1 1 1 VDD1 VDD2
77 78 DDR_B_MA15
NC1 A15 +SM_VREF_DQ1_DIMM2 +SM_VREF_DQ1
CD35
CD36
CD37
CD38
CD39
CD40
CD41
CD42
DDR_B_BS2 79 80 DDR_B_MA14
<8> DDR_B_BS2
2
C 81 BA2 A14 82 C
2 2 2 2 2 2 2 2 DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7 RC126 1 2
87 A9 A7 88
VDD5 VDD6 1
DDR_B_MA8 89 90 DDR_B_MA6 2_0402_1%
do
A8 A6
1.8K_0402_1%
DDR_B_MA5 91 92 DDR_B_MA4 CC69
A5 A4
1
93 94 0.022U_0402_16V7K
VDD7 VDD8 2
RC132
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
A1 A0
1
+1.35V_MEM 99 100
M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3 RC128
<8> M_CLK_DDR2 M_CLK_DDR3 <8>
2
M_CLK_DDR#2 103 CK0 CK1 104 M_CLK_DDR#3
<8> M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3 <8> 24.9_0402_1%
105 106
VDD11 VDD12
In
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_B_MA10 107 108 DDR_B_BS1

DDR_B_BS1 <8>
2
DDR_B_BS0 109 A10/AP BA1 110 DDR_B_RAS#
<8> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <8>
330U_D3_2.5VY_R6M
1 111 112
@ @ DDR_B_WE# 113 VDD13 VDD14 114 DDR_CS2_DIMMB#
1 1 1 1 1 1 1 1 <8> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <8>
CD45
CD46
CD47
CD48
CD49
CD50
CD51
CD52
CD53
+ DDR_B_CAS# 115 116 M_ODT2

<8> DDR_B_CAS# 117 CAS# ODT0 118 M_ODT2 <18>
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3
2 2 2 2 2 2 2 2 2 DDR_CS3_DIMMB# 121 A13 ODT1 122 M_ODT3 <18> +SM_VREF_CA_DIMM
<8> DDR_CS3_DIMMB# 123 S1# NC2 124
i-
125 VDD17 VDD18 126 +SM_VREF_CA_DIMM2 1 2
127 NCTEST VREF_CA 128 @ RD13 0_0402_5%
VSS27 VSS28
2.2U_0402_6.3V6M
0.1U_0402_25V6
DDR_B_D1 131 DQ32 DQ36 132 DDR_B_D0
133 DQ33 DQ37 134
VSS29 VSS30 1 1
CD44
DDR_B_DQS#0 135 136
DQS#4 DM4
CD43
DDR_B_DQS0 137 138
139 DQS4 VSS31 140 DDR_B_D2
is DDR_B_D3
DDR_B_D7
141
143
VSS32
DQ34
DQ35
DQ38
DQ39
VSS33
142
144
DDR_B_D6 2 2
B 145 146 DDR_B_D16 B

Layout Note: VSS34 DQ44
DDR_B_D21 147 148 DDR_B_D17
Place near JDIMM2.203,204 DDR_B_D20 149 DQ40 DQ45 150
155 DM5 DQS5 156
kn
DDR_B_D23 159 DQ42 DQ46 160 DDR_B_D18

161 DQ43 DQ47 162
+0.675V_DDR_VTT DDR_B_D33 165 DQ48 DQ52 166 DDR_B_D32
167 DQ49 DQ53 168
DDR_B_DQS#4 169 VSS41 VSS42 170
DDR_B_DQS4 171 DQS#6 DM6 172
173 DQS6 VSS43 174 DDR_B_D34
Te
VSS44 DQ54
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_B_D35 175 176 DDR_B_D38

DDR_B_D39 177 DQ50 DQ55 178
1 1 1 1 1 1 DQ51 VSS45
CD54
CD55
CD56
CD57
CD58
CD59
179 180 DDR_B_D51

DDR_B_D52 181 VSS46 DQ60 182 DDR_B_D55
DDR_B_D49 183 DQ56 DQ61 184
2 2 2 2 2 2 185 DQ57 VSS47 186 DDR_B_DQS#6
189 DM7 DQS7 190
VSS49 VSS50
w.
DDR_B_D48 191 192 DDR_B_D54

DDR_B_D53 193 DQ58 DQ62 194 DDR_B_D50
195 DQ59 DQ63 196
@ RD11 2 1 0_0402_5% 197 VSS51 VSS52 198
199 SA0 EVENT# 200
+3.3V_RUN VDDSPD SDA DDR_XDP_WAN_SMBDAT <18,31,7,9>
2 1 201 202
+3.3V_RUN SA1 SCL DDR_XDP_WAN_SMBCLK <18,31,7,9>
@ RD10 0_0402_5% 203 204
+0.675V_DDR_VTT VTT1 VTT2 +0.675V_DDR_VTT
2.2U_0402_6.3V6M
0.1U_0402_25V6
205 206
ww
A G1 G2 A
1 1
CD60
@ FOX_AS0A621-U4R6-7H
CD61
2 2
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRIII-SODIMM SLOT2
LA-9431P
5 4 3 2 1
5 4 3 2 1
m
D D
co
a.
si
+3.3V_ALW_PCH
ne
0.1U_0402_25V6 @ C388
1 2
5
C U29 C
1
P
<9> PLTRST_NFC# B 4 NFC_RST

2 O
<12> PCH_NFC_RST A
G
+3.3V_ALW_PCH
do
3
TC7SH08FU_SSOP5~D
CONN@
JNFC1 +3.3V_ALW_PCH
1
1
0.1U_0402_16V4Z
2
+3.3V_ALW_PCH 3 2
@T87 PAD~D TP_NFC_SWP_PWR_RSVD 4 3 @
4 1
C1
@T88 PAD~D TP_NFC_RSVD4 5
NFC_RST 6 5
6
In
7
NFC_SMBCLK 8 7 2
<7> NFC_SMBCLK 9 8
NFC_SMBDATA
1 2 <7> NFC_SMBDATA 10 9
NFC_DET# TP_NFC_RSVD3
R38 100K_0402_5% 11 10
<12> NFC_IRQ 12 11
@T89 PAD~D TP_NFC_RSVD1 13 12
NFC_DET# 14 13 C1 close to JNFC1
<12> NFC_DET# 15 14
15 16
i-
1 2 TP_NFC_RSVD3 GND 17
@ R37 0_0402_5% GND
E-T_6718K-Y15N-01L
ST change to 6718K-Y15N-01L
is
B B
kn
Te
w.
ww
A A
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT NFC/Sensor Hub Conn
0.3
5 4 3 2 1
2 1
+1.05V_RUN_VMM +3.3V_RUN_VMM
+3.3V_RUN_VMM
EEPROM
1
+3.3V_RUN_VMM
L1 L2 C34
U6B R64
1 2 +1.05V_VMM_VDD E6 3.3V Analog H5 +3.3V_RUN_VDDA 1 2 10K_0402_5% 1 2
VDD VDDRX_33
10U_0603_6.3V6M
.01U_0402_16V7K
.01U_0402_16V7K
0.1U_0402_25V6
1U_0603_10V6K
E7 C10 1 1 1 1
VDD VDDTX0_33
C132
1U_0603_10V6K
0.1U_0402_25V6
0.1U_0402_25V6
.01U_0402_16V7K
.01U_0402_16V7K
C13
C14
C15
C16
BLM18AG102SN1D_2P 1 1 1 1 1 1 E8 H12 BLM18AG102SN1D_2P U7 0.1U_0402_25V6
2
VDD VDDTX1_33
C8
C9
C11
C10
C12
E9 K6 VMM_SPI_CS# 1 8
H6 VDD VGA_AVDD33 K7 VMM_SPI_DIN 2 CS# VCC 7 VMM_SPI_HOLD R65 2 1
H7 VDD VGA_AVDD33 2 2 2 2 VMM_SPI_WP# 3 DO(IO1) HOLD#(IO3) 6 VMM_SPI_CLK 2.2K_0402_5%
1V Digital
2 2 2 2 2 2 H8 VDD 4 WP#(IO2) CLK 5 VMM_SPI_DO
H9 VDD C5 GND DI(IO0)
VDD VSS D5 W25X10CLSNIG _SO8
E3 VSS D6
G3 VDDRX VSS D7
VDDRX VSS D8
m
C8 VSS D9 U6A
C9 VDDTX0 VSS D10 0.1U_0402_10V7K 1 2 C155 DP12412_P0_C G1 B7
VDDTX0 VSS <27> DP12412_P0 RxP0 Tx0P0 DPC_LANE_P0 <34>
1U_0603_10V6K
0.1U_0402_25V6
.01U_0402_16V7K
1 1 1 F12 D11 0.1U_0402_10V7K 1 2 C156 DP12412_N0_C G2 A7
VDDTX1 VSS <27> DP12412_N0 RxN0 Tx0N0 DPC_LANE_N0 <34>
G12 E4 0.1U_0402_10V7K 1 2 C157 DP12412_P1_C F1 B8
VDDTX1 VSS <27> DP12412_P1 RxP1 Tx0P1 DPC_LANE_P1 <34>
C25
C17
C18
E11 1 2 F2
co
0.1U_0402_10V7K C158 DP12412_N1_C A8
VSS <27> DP12412_N1 RxN1 Tx0N1 DPC_LANE_N1 <34>
J3 F4 0.1U_0402_10V7K 1 2 C159 DP12412_P2_C E1 B9
2 2 2 VDDXT1V VSS <27> DP12412_P2 RxP2 Tx0P2 DPC_LANE_P2 <34>
F5 0.1U_0402_10V7K 1 2 C160 DP12412_N2_C E2 A9
E5 VSS F6 <27> DP12412_N2 1 2 D1 RxN2 Tx0N2 B10 DPC_LANE_N2 <34>
0.1U_0402_10V7K C161 DP12412_P3_C
+1.05V_RUN_VMM VDDLP VSS <27> DP12412_P3 RxP3 Tx0P3 DPC_LANE_P3 <34>
F7 0.1U_0402_10V7K 1 2 C162 DP12412_N3_C D2 A10
H3 VSS <27> DP12412_N3 1 2 H1 RxN3 Tx0N3 A14 DPC_LANE_N3 <34>
0.1U_0402_10V7K C19 DP12412_AUX_C
L4 VDDRXA0 <27> DP12412_AUX RxAUXP CAD0 DPC_CA_DET <24,34>
F3 F8 0.1U_0402_10V7K 1 2 C20 DP12412_AUX#_C H2 B11
VDDRXA1 VSS <27> DP12412_AUX# RXAUXN Tx0AUXP SW_DPC_AUX <24>
1 2 +1.05V_VMM_VDDTX D3 F9 SRCDET C2 A11
VDDRXA2 VSS F10 J1 RxSRCDET Tx0AUXN B12 VMM_DPC_CTRLCLK SW_DPC_AUX# <24>
DP12412_HPD
VSS <27> DP12412_HPD RxHPD Tx0DDCSCL VMM_DPC_CTRLCLK <24>
1U_0603_10V6K
0.1U_0402_25V6
.01U_0402_16V7K
.01U_0402_16V7K
BLM18AG102SN1D_2P 1 1 1 1 E10 F11 A12 VMM_DPC_CTRLDAT
VDDTX0A0 VSS Tx0DDCSDA VMM_DPC_CTRLDAT <24>
a.
C21
C22
C23
C24
C7 G4 A6
1 V Analog
C6 VDDTX0A1 VSS G5 Tx0HPD DPC_DOCK_HPD <34>
VDDTX0A2 VSS A13 E13
2 2 2 2 H11 G6 <9> PLTRST_VMM2320# RSTN_IN Tx1P0 E14 DPB_LANE_P0 <34>
E12 VDDTX1A0 VSS G7 VMM_MESCL B5 Tx1N0 F13 DPB_LANE_N0 <34>
D12 VDDTX1A1 VSS G8 VMM_MESDA B6 MESCL Tx1P1 F14 DPB_LANE_P1 <34>
B VDDTX1A2 VSS MESDA Tx1N1 DPB_LANE_N1 <34> B
G9 VMM_SPI_WP# B1 G13
J10 VSS G10 ROMWP Tx1P2 G14 DPB_LANE_P2 <34>
K8 VGA_AVDD VSS G11 Tx1N2 H13 DPB_LANE_N2 <34>
K9 VGA_AVDD VSS H4 VMM_SPI_CS# A4 Tx1P3 H14 DPB_LANE_P3 <34>
si
K10 VGA_AVDD VSS D4 VMM_SPI_CLK B3 SPICS Tx1N3 M14 DPB_LANE_N3 <34>
+3.3V_RUN_VMM VGA_AVDD VSS VMM_SPI_DIN B4 SPICLK CAD1 J13 DPB_CA_DET <24,34>
SPIDI Tx1AUXP SW_DPB_AUX <24>
J2 VMM_SPI_DO A3 J14
L5 VDDSA J5 SPIDO Tx1AUXN K13 SW_DPB_AUX# <24>
VMM_DPB_CTRLCLK
1 2 +3.3V_RUN_VDDIO C3 VSS J11 Tx1DDCSCL L14 VMM_DPB_CTRLDAT VMM_DPB_CTRLCLK <24>
VDDIO VSS Tx1DDCSDA VMM_DPB_CTRLDAT <24>
1U_0603_10V6K
0.1U_0402_25V6
.01U_0402_16V7K
.01U_0402_16V7K
C4 J12 D14 K14
3.3V IO
BLM18AG102SN1D_2P C11 VDDIO VSS K5 D13 GPIO0 Tx1HPD DPB_DOCK_HPD <34>
1 1 1 1 VDDIO VSS GPIO1
C26
C27
C28
C29
C12 H10 C14 L9 VMM2310_TX2P0

K3 VDDIO VGA_AVSS J6 C13 GPIO2 VGA_VSYNC M9 VMM2310_TX2N0
K4 VDDIO VGA_AVSS J7 B14 GPIO3 VGA_HSYNC M6 VMM2310_TX2N3
ne
2 2 2 2 K11 VDDIO VGA_AVSS J8 B13 GPIO4 VGA_RP L6
K12 VDDIO VGA_AVSS J9 VMM_GPIO6 C1 GPIO5 VGA_RN M7 VMM2310_TX2N2
J4 VDDIO VGA_AVSS VMM_GPIO7 M12 GPIO6/INT VGA_GP L7
VDDXT3V VMM_GPIO8 M13 GPIO7/MSCL VGA_GN M8 VMM2310_TX2N1
IDTVMM2320BKG8_BGA168 2 1 VMM_GPIO9 L3 GPIO8/MSDA VGA_BP L8
+3.3V_RUN_VDDA R63 1M_0402_5% LP_CTL B2 GPIO9 VGA_BN L4 VMM2310_SCL
+1.05V_RUN_VMM A5 LP_CTL VGA_SCL M4 VMM2310_SDA
LP_EN VGA_SDA
1
M3 VMM2310_HDP
do
PJP12 CLK_27M_IN_R 1 2 K2 VGA_DET M5 VMM2310_AUXN
RX_STS VGA_IREF
1
PAD-OPEN1x1m @ R107 0_0402_5% L2 L5 VMM2310_AUXP
M1 TX0_STS VGA_NC PAD~D T40 @
+1.05V_RUN R66 M2 TX1_STS A1
TX2_STS SSDA I2C1_SDA_VMM <12>
Y1 1M_0402_5% A2
I2C1_SCL_VMM <12>
2
U31 1 3 SSCL
2
1 14 1 2 IN OUT M11
VIN1 VOUT1 TRSTN I2C debug port to VMM2320
22P_0402_50V8J
22P_0402_50V8J
2 13 +1.05V_RUN_VMM_U31 C432 0.1U_0402_10V7K 1 2 4 1 CLK_27M_IN K1 M10
VIN1 VOUT1 GND GND XIN TCK L12
TMS
C42
C43
DOCKED 3 12 C433 1 2 L13
In
<27,28,32,36> DOCKED ON1 CT1 L1 TMS2 L11 +3.3V_RUN_VMM
470P_0402_50V7K 27MHZ_12PF_X1E000021042600 CLK_27M_OUT
4 11 2 2 XOUT TDI L10
+5V_ALW VBIAS GND TDO
DOCKED 5 10 C394 1 2 VMM_MESCL 1 2
ON2 CT2 470P_0402_50V7K IDTVMM2320BKG8_BGA168 R40 2.2K_0402_5%
6 9 +3.3V_RUN_VMM VMM_MESDA 1 2
+3.3V_RUN VIN2 VOUT2
7 8 +3.3V_RUN_VMM_U31 2 1 +3.3V_RUN_VMM R42 2.2K_0402_5%
VIN2 VOUT2 SW_DPB_AUX# 1 2
15 2 PJP13 PAD-OPEN1x1m VMM_DPC_CTRLCLK 1 2 R44 1M_0402_5%
GPAD
i-
R49 2.2K_0402_5% VMM_GPIO6 1 2
TPS22966DPUR_SON14_2X3~D C392 VMM_DPC_CTRLDAT 1 2 R52 2.2K_0402_5%
0.1U_0402_10V7K
XB: non Vpro use A2 part R46 2.2K_0402_5% VMM_GPIO7 1 2
1
Vpro use A3 part SW_DPC_AUX# 1 2
VMM_GPIO8
R53
1
2.2K_0402_5%
2
R91 1M_0402_5%
R54 2.2K_0402_5%
SW_DPC_AUX 1 2
R92 1M_0402_5% SRCDET 1 2
SW_DPB_AUX 1 2 R69 1M_0402_5%
LP_CTL 1
is2
R47 1M_0402_5% VMM_DPB_CTRLCLK 1
R70
VMM_DPB_CTRLDAT 1
2
2.2K_0402_5%
2
@ R207 100K_0402_5% RED_DOCK 1 2 R72 2.2K_0402_5%
R311 150_0402_1%
GREEN_DOCK 1 2
R312 150_0402_1%
BLUE_DOCK 1 2
R351 150_0402_1%
kn
VMM2310_TX2N3 1 2 RED_DOCK
@ R73 0_0402_5% RED_DOCK <34> +3.3V_RUN_VMM
Te
VMM2310_TX2N2 1 2 GREEN_DOCK VMM2310_HDP 2 1

@ R75 0_0402_5% GREEN_DOCK <34> R74 10K_0402_5%
A A
VMM2310_TX2N1 1 2 BLUE_DOCK
@ R76 0_0402_5% BLUE_DOCK <34>
VMM2310_SCL 1 2 CLK_DDC2_DOCK
w.
@ R77 0_0402_5% CLK_DDC2_DOCK <34> VMM2310_AUXN 1 2

R85 3.74K_0402_1%
VMM2310_SDA 1 2 DAT_DDC2_DOCK
DAT_DDC2_DOCK <34>
@ R81 0_0402_5%
VMM2310_TX2N0 1 2 HSYNC_DOCK
@ R84 0_0402_5% HSYNC_DOCK <34>
VMM2310_TX2P0 1 2 VSYNC_DOCK
VSYNC_DOCK <34>
ww
@ R88 0_0402_5%
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT IDT VMM2320 DP and VGA SW
2 1
5 4 3 2 1
+3.3V_TSP
ACES_50398-04071-001
45 40
44 G5 40 39
43 G4 39 38 USBP7- <11>
42 G3 38 37 USBP7+ <11>
41 G2 37 36
G1 36 35 DMIC0 <26>
2
35 34
L30ESDL5V0C3-2_SOT23-3
@
34 33 DMIC_CLK <26>
D8
+3.3V_CAM
m
33 32
100P_0402_50V8J
100P_0402_50V8J
USBP3_D-
D 32 31 USBP3_D+ D
31 30 1 @ 1 @
30 29 CAM_MIC_CBL_DET# <12>
CE1
CE2
IO_LOOP 1 2
29 28
co
R108 1K_0402_5%
28 27 2 2
+BL_PWR_SRC
1
27 26
26 25
25 24
1 2 ESD depop location(EMC)
C52 0.1U_0603_50V7K
24 23
23 22 LE1 1
EMC@LE1
EMC@ 2 BIA_PWM
22 21 DISP_ON BLM15BB221SN1D_2P~D
21 20
a.
20 19
19 18
18 17
17 16
16 15 EDP_CPU_HPD <10>
15 14
14 13
13 12 LCD_TST <36>
si
12 11
11 10 +LCDVDD
10 9 EDP_CPU_AUX#_C C54 2 1 0.1U_0402_10V7K
9 8 EDP_CPU_AUX# <10>
EDP_CPU_AUX_C C55 2 1 0.1U_0402_10V7K
8 7 EDP_CPU_AUX <10>
EDP_CPU_LANE_P0_C C59 2 1 0.1U_0402_10V7K
7 6 EDP_CPU_LANE_P0 <10>
EDP_CPU_LANE_N0_C C56 2 1 0.1U_0402_10V7K
6 5 EDP_CPU_LANE_N0 <10>
EDP_CPU_LANE_P1_C C60 2 1 0.1U_0402_10V7K
5 4 EDP_CPU_LANE_P1 <10>
EDP_CPU_LANE_N1_C C57 2 1 0.1U_0402_10V7K
4 3 EDP_CPU_LANE_N1 <10>
ne
3 2
2 1 LCD_CBL_DET# <12>
1 +3.3V_RUN
C JEDP1 CONN@ Pin 29 for cable detact GND C
Pin 17 ~20 for BL_GND
Pin 3, 10 for eDP High speed GND CONN@
Pin 14,15 for LCD_GND
JLED1
do
1
+5V_ALW 1
2
+LCDVDD +3.3V_CAM +5V_ALW <40> BATT_WHITE_LED# 3 2
+3.3V_TSP +3.3V_RUN
<40>
<40>
BATT_YELLOW_LED#
PANEL_HDD_LED#
4 3
4
For LCDVDD +LCDVDD +3.3V_ALW
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
5 @
<40> BREATH_WHITE_LED# 5 C431
0.1U_0402_16V4Z
1 1 @ 6 U9
<12> TOUCH_PANEL_INTR# 7 6 2 1 1
1 @ 1 @ 1 @
GND VOUT
C63
C68
C62
C64 8 5
@
GND VIN
In
C3
C
10U_0603_6.3V6M
3
2 2 2
Close to 2
Close to 2
Close to 2
Close to Close to ACES_50450-0067N-P01 D2
GND
0.01U_0402_16V7K
2 4
JEDP1.11,12 JEDP1.33 JLED1.1 JEDP1.40 JEDP1.2 <36> LCD_VCC_TEST_EN SS
@ C430
check 1
1 EN_LCDPWR 3
EN
3 APL3512ABI-TRG_SOT23-5
<10,36> ENVDD_PCH
2
2
D10
R104
i-
3 EDP_BIA_PWM D21
BAT54CW_SOT323-3 100K_0402_5%
EDP_BIA_PWM <10> 3
BIA_PWM 1 PANEL_BKLEN <10>
1
DISP_ON 1
2 BIA_PWM_EC
BIA_PWM_EC <37>
1
2
PANEL_BKEN_EC <36>
R95 R96
10K_0402_5% BAT54CW_SOT323-3 100K_0402_5%
is
BAT54CW_SOT323-3
2
B B
Touch Screen Connector

+3.3V_CAM
+3.3V_TSP
kn
1
Q2 +3.3V_RUN
For Webcam
1
PJP9 +PWR_SRC
+3.3V_RUN 40mil
10K_0402_5%
PAD-OPEN1x1m 6 PJP10
40mil
D
1
4 5 PAD-OPEN1x1m +3.3V_RUN
S
+BL_PWR_SRC
R94
Q3 2 FDC654P-G_SSOT-6 Q1
LP2301ALT1G_SOT23-3 1 LP2301ALT1G_SOT23-3
2
1000P_0402_50V7K
0.1U_0402_25V6
Te
2
0.1U_0402_25V6
+3.3V_CAM_Q 1 3 +3.3V_TSP_Q 1 3
D
S
1
3
2
1
1 1
C61
1 R97 C65
C67
C66
100K_0402_5% 0.1U_0603_50V7K
G
G
2
2
2
2 2
2
1 2 2
<36> CCD_OFF PWR_SRC_ON
@ R102 0_0402_5%
6
w.
Q4 2 G
D
Q17B
<12> 3.3V_TS_EN
3
1 2 L2N7002WT1G_SC-70-3 S DMN66D0LDW-7_SOT363-6
<12> 3.3V_CAM_EN# 5
D
@ R106 0_0402_5% G
Q17A
1
1 2 1 3 DMN66D0LDW-7_SOT363-6
D
R99 47K_0402_5%
4
check Resistor
G
2
change back to CCD_OFF at Goliad project

ww
A EMC@ L8 A
1 2 USBP3_D+ EN_INVPWR
<11> USBP3+ 1 2 <37> EN_INVPWR
FDC654P: P CHANNAL
<11> USBP3-
4
4 3
3 USBP3_D- DELL CONFIDENTIAL/PROPRIETARY
Panel backlight power control by EC
DLW21HN900SQ2L_4P
1 2
@ R100 0_0402_5% Compal Electronics, Inc.
Title
1 2 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
@ R101 0_0402_5%
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
eDP & CAM &TS Conn
0.3
5 4 3 2 1
5 4 3 2 1
EMC@ L9
EMC@L9
1 2
9NH_0402HS-9N0EJTS_5%
L10 @
2 1 TMDS_CLK_C 1 2 TMDSB_CON_CLK
<10> DDI1_LANE_P3 1 2
C103 0.1U_0402_10V7K
2 1 TMDS_CLK#_C 4 3 TMDSB_CON_CLK#
<10> DDI1_LANE_N3 4 3
C191 0.1U_0402_10V7K
1.8P_0402_50V8
1.8P_0402_50V8
DLW21SN900HQ2L-0805_4P 1 1
@ C273
@ C274
m
EMC@ L11
EMC@L11
D 1 2
9NH_0402HS-9N0EJTS_5% 2 2
+5V_RUN D
co 0.1U_0402_16V4Z
EMC@L12
EMC@ L12 EMI depop location(EMC) @ 1
C333
1 2
9NH_0402HS-9N0EJTS_5% +VHDMI_VCC
1
U48
2
IN
L13 @
2 1 TMDS_P0_C 1 2 TMDSB_CON_P0
a.
<10> DDI1_LANE_P2 1 2
C199 0.1U_0402_10V7K
0.1U_0402_10V7K
10U_0603_6.3V6M
1 1
2 1 TMDS_N0_C 4 3 TMDSB_CON_N0 @
<10> DDI1_LANE_N2 4 3
C87
C88
C209 0.1U_0402_10V7K
GND
OUT
1.8P_0402_50V8
1.8P_0402_50V8
DLW21SN900HQ2L-0805_4P 1 1 2 2
@ C275
@ C276
EMC@L14
EMC@ L14 AP2330W-7_SC59-3
3
1 2
si
9NH_0402HS-9N0EJTS_5% 2 2
EMC@L15
EMC@ L15
1 2 EMI depop location(EMC) JHDMI1 CONN@
9NH_0402HS-9N0EJTS_5% HDMI_HPD_SINK 19
18 HP_DET
17 +5V
DDC/CEC_GND
ne
L16 @ CPU_DPB_CTRLDAT_R 16
2 1 TMDS_P1_C 1 2 TMDSB_CON_P1 CPU_DPB_CTRLCLK_R 15 SDA
<10> DDI1_LANE_P1 1 2 14 SCL
C269 0.1U_0402_10V7K
HDMI_CEC 13 Reserved
CEC
C <10> DDI1_LANE_N1
2
C270
1 TMDS_N1_C
0.1U_0402_10V7K
4
4 3
3 TMDSB_CON_N1 TMDSB_CON_CLK# 12
11 CK- GND
CK_shield GND
20
21 C
1.8P_0402_50V8
1.8P_0402_50V8
DLW21SN900HQ2L-0805_4P 1 1 TMDSB_CON_CLK 10 22
CK+ GND
@C277
@
@C278
@
TMDSB_CON_N0 9 23
D0- GND
C277
C278
EMC@L17
EMC@ L17 8
do
1 2 TMDSB_CON_P0 7 D0_shield
9NH_0402HS-9N0EJTS_5% 2 2 TMDSB_CON_N1 6 D0+
5 D1-
TMDSB_CON_P1 4 D1_shield
EMC@L18
EMC@ L18 TMDSB_CON_N2 3 D1+
1 2 EMI depop location(EMC) 2 D2-
D2_shield
9NH_0402HS-9N0EJTS_5% TMDSB_CON_P2 1
D2+
In
LCN_AUF05-1922S10-0019
L19 @
2 1 TMDS_P2_C 1 2 TMDSB_CON_P2
<10> DDI1_LANE_P0 1 2
C271 0.1U_0402_10V7K
2 1 TMDS_N2_C 4 3 TMDSB_CON_N2
<10> DDI1_LANE_N0 4 3
C272 0.1U_0402_10V7K
1.8P_0402_50V8
1.8P_0402_50V8
DLW21SN900HQ2L-0805_4P 1 1
@ C279
@ C382
i-
EMC@ L20
EMC@L20
1 2
9NH_0402HS-9N0EJTS_5% 2 2
EMI depop location(EMC)

is +3.3V_RUN
B +5V_RUN
B
HDMI_CEC 2 1
@ R473 10K_0402_5%
+3.3V_RUN
RB751VM-40TE-17_SOD323-2
kn 2
@
0_0402_5%
R472
@
D65
Q120B TMDS_P2_C R465 1 2 470_0402_1% HDMI_OB

1
2
2
DMN66D0LDW-7_SOT363-6 TMDS_N2_C R468 1 2 470_0402_1%

TMDS_P1_C R467 1 2 470_0402_1%
G
1 6 CPU_DPB_CTRLCLK_R 1 2 +5V_HDMI_DDC TMDS_N1_C R469 1 2 470_0402_1%

Te
<10> CPU_DPB_CTRLCLK 1 2
S
R471 2.2K_0402_5% TMDS_P0_C R462 470_0402_1%

TMDS_N0_C R463 1 2 470_0402_1%
5
TMDS_CLK_C R464 1 2 470_0402_1%

TMDS_CLK#_C R466 1 2 470_0402_1%
G
4 3 CPU_DPB_CTRLDAT_R 1 2
<10> CPU_DPB_CTRLDAT
S
R470 2.2K_0402_5%
1
Q120A D
DMN66D0LDW-7_SOT363-6 R460 1 2 10K_0402_5% 2 Q29
+3.3V_RUN
w.
G L2N7002WT1G_SC-70-3
S
3
+3.3V_RUN
1M_0402_5%
ww
2
R475
A A
2
G
1
3 1 HDMI_HPD_SINK 1 2
<10> DPB_HPD R474 20K_0402_5%
S

Q121 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
L2N7002WT1G_SC-70-3 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, HDMI Conn
LA-9431P
5 4 3 2 1
+3.3V_RUN_VMM
AUX/DDC SW for DPB to E-DOCK 1 2
C93
0.1U_0402_25V6
U11
m
1 14
D 2 1 SW_DPB_AUX_C 2 BE0 VCC 13 D
<21> SW_DPB_AUX A0 BE3
C94 0.1U_0402_10V7K
DPB_DOCK_AUX 3 12
<34> DPB_DOCK_AUX B0 A3 VMM_DPB_CTRLCLK <21>
co
4 11
2 1 SW_DPB_AUX#_C 5 BE1 B3 10
<21> SW_DPB_AUX# A1 BE2
C95 0.1U_0402_10V7K
DPB_DOCK_AUX# 6 9
<34> DPB_DOCK_AUX# B1 A2 VMM_DPB_CTRLDAT <21>
7 8
GND B2
PI3C3125LEX_TSSOP14~D
a.
+3.3V_RUN_VMM
100K_0402_5%
1
si
R60
2
DPB_CA_DET#
ne
1
D
DPB_CA_DET 2 Q10
<21,34> DPB_CA_DET
G BSS138W-7-F_SOT323-3
C C
S
do
+3.3V_RUN_VMM
AUX/DDC SW for DPC to E-DOCK
In
1 2
C97
0.1U_0402_25V6
U13
1 14
2 1 SW_DPC_AUX_C 2 BE0 VCC 13
i-
<21> SW_DPC_AUX A0 BE3
C98 0.1U_0402_10V7K
DPC_DOCK_AUX 3 12
<34> DPC_DOCK_AUX B0 A3 VMM_DPC_CTRLCLK <21>
4 11
2 1 SW_DPC_AUX#_C 5 BE1 B3 10
<21> SW_DPC_AUX# A1 BE2
C99 0.1U_0402_10V7K
DPC_DOCK_AUX# 6 9
<34> DPC_DOCK_AUX# B1 A2 VMM_DPC_CTRLDAT <21>
7
GND B2
8
is
B PI3C3125LEX_TSSOP14~D B
+3.3V_RUN_VMM
kn
100K_0402_5%
1
R56
2
Te
DPC_CA_DET#
1
D
DPC_CA_DET 2 Q6
<21,34> DPC_CA_DET
G BSS138W-7-F_SOT323-3
S
3
w.
ww
A A
1 2 DPB_CA_DET
R120
1
1M_0402_5%
2 DPC_CA_DET Compal Electronics, Inc.
R121 1M_0402_5% PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DP SW_DP125
LA-9431P
5 4 3 2 1
5 4 3 2 1
+3.3V_HDD
Mini mSATA H=4
1 2 HDD_DEVSLP
@ R155 10K_0402_5% +3.3V_HDD +3.3V_HDD
JMINI3 CONN@
1 2
3 1 2 4
m
5 3 4 6
D 7 5 6 8 LPC_LFRAME# D
7 8 LPC_LFRAME# <29,36,37,7>
9 10 LPC_LAD3 LPC_LAD3 <29,36,37,7>
11 9 10 12 LPC_LAD2
11 12 LPC_LAD2 <29,36,37,7>
co
13 14 LPC_LAD1
13 14 LPC_LAD1 <29,36,37,7>
15 16 LPC_LAD0
17 15 16 18 LPC_LAD0 <29,36,37,7>
PCH_PLTRST#_EC
<29,31,36,37,9> PCH_PLTRST#_EC 19 17 18 20
<7> CLK_PCI_LPDEBUG 21 19 20 22
2 1 SATA_PRX_DTX_P1 23 21 22 24
<6> SATA_PRX_DTX_P1_C C108 2 1 .01U_0402_16V7K SATA_PRX_DTX_N1 25 23 24 26
<6> SATA_PRX_DTX_N1_C C109 .01U_0402_16V7K 27 25 26 28
29 27 28 30
a.
C106 2 1 .01U_0402_16V7K SATA_PTX_DRX_N1 31 29 30 32
<6> SATA_PTX_DRX_N1_C 31 32
C105 2 1 .01U_0402_16V7K SATA_PTX_DRX_P1 33 34
<6> SATA_PTX_DRX_P1_C 35 33 34 36
37 35 36 38
+3.3V_HDD 39 37 38 40
41 39 40 42
43 41 42 44 HDD_DEVSLP
43 44 HDD_DEVSLP <12>
0.1U_0402_25V6
0.1U_0402_25V6
45 46
si
47 45 46 48
@ 49 47 48 50
1 1 49 50
C113
C114
HDD_DET# 51 52
<6> HDD_DET# 51 52
53 54
2 2 GND1 GND2
LCN_DAN08-52406-0500
ne
C C
Place near JMINI3
do
In
RING2 ,RING2_L
AUD_HP_OUT_L ,AUD_HP_OUT_L1 +3.3V_RUN
i-
AUD_HP_OUT_R ,AUD_HP_OUT_R1
1
SLEEVE ,EXT_MIC
Trace width to 15mils. R480
10K_0402_5%
Combo Jack
JHP1 CONN@
2
7
<26> RING2
RING2 @ R491 2
is
1 0_0402_5% RING2_L
3
B AUD_HP_OUT_L EMC@L51 2 1 BLM18AG221SN1D_2P AUD_HP_OUT_L1 1 B

<26> AUD_HP_OUT_L
5
Normal
Open
AUD_HP_NB_SENSE 6
kn
AUD_HP_OUT_R EMC@L52 2 1 BLM18AG221SN1D_2P AUD_HP_OUT_R1 2

<26> AUD_HP_OUT_R 2 1 4
SLEEVE SLEEVE_L
<26> SLEEVE
@ R492 0_0402_5%
SINGA_2SJ3080-003111F
Te
EMC@ EMC@ EMC@
2
D30 D31 D32
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
220P_0402_50V7K
1 1 1 1 AUD_HP_NB_SENSE
AUD_HP_NB_SENSE <26,36>
L03ESDL5V0CC3-2_SOT23-3
@ @ @ @
1
C440
C441
C442
C443
2 2 2 2 R481
100K_0402_5%
w.
2
1
1
ww
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Min Card/mSATA/Combo Jack
5 4 3 2 1
2 1
+5V_RUN_AUDIO +3.3V_RUN_AUDIO
place close to pin27 +5V_RUN_AUDIO
Internal Speakers Header L21
1
+VDDA_AVDD1 1 2
1
0.1U_0402_25V6
10U_0603_6.3V6M
+3.3V_RUN_AUDIO +3.3V_RUN_AUDIO PBY160808T-600Y-N_2P @ R140
place close to pin38 0_0603_5%
40 mils trace keep 10 mil spacing DVDD_IO should match CONN@
1 1
@ R130
2
with HDA Bus level
C115
C117
JSPK1 +VDDA_AVDD2 0_0805_5%
0.1U_0402_25V6
10U_0603_6.3V6M
INT_SPK_L+ EMC@ L22 1 2 BLM18PG330SN1_2P INT_SPKR_L+ 1 +DVDD_CORE place close to pin39 place close to pin45
2
1 2 2
1U_0603_10V6K
0.1U_0402_25V6
1U_0603_10V6K
0.1U_0402_25V6
10U_0603_6.3V6M
INT_SPK_L- EMC@ L23 1 2 BLM18PG330SN1_2P INT_SPKR_L- 2 1 1 1 1 1 1 1
INT_SPK_R+ EMC@ L24 1 2 BLM18PG330SN1_2P INT_SPKR_R+ 3 2 @
3
C118
C119
C405
C121
C150
C116
0.1U_0402_25V6
10U_0603_6.3V6M
0.1U_0402_25V6
10U_0603_6.3V6M
INT_SPK_R- EMC@ L25 1 2 BLM18PG330SN1_2P INT_SPKR_R- 4
4
C120
1 1 1 1
5 2 2 2 2 2 U17 2 2
GND
C129
C128
C123
C122
m
6 1 27
@ @ @ @ GND DREG_OUT AVDD1 38
AVDD2/HVDD(3.3) 2 2 2 2
C124
C125
C126
C127 ACES_50209-0040N-001
3 45 +VDDA_PVDD
DVDD-IO PVDD2 39
co
1 1 1 1 PVDD1 +VREFOUT
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
9 13 AUD_SENSE_A
DVDD Sense A 14 AUD_SENSE_B
2 2 2 2 Sense B RING2 1 2
28 RING2 R187 2.2K_0402_5%
PCH_AZ_CODEC_BITCLK 6 LINE1-L/RING2 29 SLEEVE RING2 <25> SLEEVE 1 2
<6> PCH_AZ_CODEC_BITCLK BIT-CLK LINE1-R/SLEEVE SLEEVE <25>
23 +VREFOUT R197 2.2K_0402_5%
PCH_AZ_CODEC_SDOUT 5 LINE1-VREFO 1 2 SLEEVE/RING2/AUD_HP_OUT_R/AUD_HP_OUT_L
<6> PCH_AZ_CODEC_SDOUT SDATA-OUT 31
a.
C385 10U_0603_6.3V6M please keep 15mils trace
10 HPOUT-L/MIC-CAP 33 AUD_OUT_L 1 2 AUD_HP_OUT_L
<6> PCH_AZ_CODEC_SYNC SYNC AVSS2/HPOUT-L AUD_HP_OUT_L <25>
Place R136 close to codec 32 AUD_OUT_R R162 1 2 18_0402_5% AUD_HP_OUT_R +VREFOUT
1 2 PCH_AZ_SDIN0_R 8 HP-OUT-R R166 18_0402_5% AUD_HP_OUT_R <25>
<6> PCH_AZ_CODEC_SDIN0 SDATA-IN
1U_0603_10V4Z
B R136 33_0402_5% 40 INT_SPK_L+ 1 2 B
SPK-L+ 1
@
PCH_AZ_CODEC_RST# 11 41 INT_SPK_L- @ R194 10K_0402_5%
<6> PCH_AZ_CODEC_RST# RESET# SPK-L-
C131
1 2
Close to U17 44 INT_SPK_R+ @ R153 10K_0402_5%
SPK-R+ 43 INT_SPK_R- 2 1 1 2 2
SPK-R- SPKR <12>
si
1 2 I2S_MCLK 15 C145 0.1U_0402_25V6 R147 1K_0402_5%
EMI depop location(EMC) <34> DAI_12MHZ# R137 22_0402_5% I2S_MCLK
PCBEEP
12 AUD_PC_BEEP 2 1 1 2
BEEP <37>
1 2 I2S_BCLK 16 C146 0.1U_0402_25V6 R151 1K_0402_5%
<34> DAI_BCLK# R139 22_0402_5% I2S_SCLK 2 1 2
DMIC_CLK_L DMIC_CLK
1 2 I2S_DOPlace R142 close to codec 17 GPIO0/DMIC-CLK 4 EMC@ R170 33_0402_5% DMIC_CLK <22>
<34> DAI_DO# I2S_DOUT GPIO1/DMIC-DATA DMIC0 <22>
R142 33_0402_5% 46
1 2 I2S_LRCLK 18 DMIC1/GPIO2 48
<34> DAI_LRCK# @ R143 0_0402_5% I2S_LRCK GPIO3 1 2
1 2 I2S_DI# 24 37 1 @ R186 0_0402_5%
ne
<34> DAI_DI @ R144 0_0402_5% I2S_DIN MONO-OUT/CBP C134 DMIC_CLK
Close to U17 pin5 Close to U17 pin6 EN_I2S_NB_CODEC# <36>
22P_0402_50V8J
2.2U_0603_6.3V6K
1
PCH_AZ_CODEC_SDOUT PCH_AZ_CODEC_BITCLK 19 35 2 @
MIC1-L CBN Place C134 close to Codec
C130
BCLK: Audio serial data bus bit clock input/output
LRCK: Audio serial data bus word clock input/output 20
MIC1-R
1
2
@ R148 @ R149 36
47_0402_5% 33_0402_5% AUD_NB_MUTE# 47 CBP/AVSS2
do
<36> AUD_NB_MUTE# EAPD/PD Place close to Codec
1U_0603_10V6K
21 +ALC290_LDO_CAP
+3.3V_RUN_AUDIO LDO-CAP 22 place close to pin2
1
2
7 JDREF 34 +ALC3226_CPVEE
1 1 DVSS CPVEE EMI depop location(EMC)
C410
25 +ALC3226_VREF
VREF
1
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
20K_0402_1%
10U_0603_6.3V6M
@C135
@C135 @ C136 1 2 42
2 PVSS
0.1U_0402_25V6
0.1U_0402_10V7K 10P_0402_50V8J R150 10K_0402_5% 30 2 1 1 1
2 2 49 MIC1-VREFO 26
GND AVSS1
C167
C169
C138
R39
C140
In
ALC3226-CG_QFN48_7X7
2
1 2 2 2
place at AGND and DGND plane

Notes:
Place closely to Pin 13. 1 2 Keep PVDD supply and speaker traces routed on the DGND plane.
AUD_SENSE_A C141 Keep away from AGND and other analog signals
0.1U_0402_25V6
i-
1 2 place at Codec bottom side
1
@ PJP4
R152 C142 1 2
39.2K_0402_1% 0.1U_0402_25V6
1 2
PAD-OPEN1x1m
2
C144
DMN66D0LDW-7_SOT363-6
0.1U_0402_25V6
is
6
3
Q20B
Q20A
D D
2 G G 5
AUD_HP_NB_SENSE <25,36>
EMI Request(EMC)
S S
0.1U_0402_25V6
10U_0603_6.3V6M
1
1 1 +5V_RUN_AUDIO
@
C137
C408
1
SLEEVE
2 2
kn
PJP24
PAD-OPEN1x1m
+RTC_CELL
Add for solve pop noise and detect issue
U18
2
+5V_ALW 1 14 1 2
VIN1 VOUT1
1
100K_0402_5%
2 13 +5V_RUN_AUDIO_U18 @ C188 0.1U_0402_10V7K

VIN1 VOUT1
R202
A A
1 2 3 12 C147 1 2
<36,37,39> RUN_ON
Te
@ R154 0_0402_5% ON1 CT1 470P_0402_50V7K

Place closely to Pin 14
4 11
2
VBIAS GND
3
Q123A
5 5 10 C148 1 2
D
G
AUD_SENSE_B S
ON2 CT2 1000P_0402_50V7K
+3.3V_ALW 6 9
4
7 VIN2 VOUT2 8 +3.3V_RUN_AUDIO_U18 2 1

VIN2 VOUT2 +3.3V_RUN_AUDIO

6
1
1
+3.3V_RUN_AUDIO
Q123B
2 1 2 PCH_AZ_CODEC_RST# 15
D
PJP25 PAD-OPEN1x1m
w.
R156 R157 +3.3V_RUN_AUDIO S @ R213 0_0402_5% GPAD @ C139

39.2K_0402_1% 20K_0402_1% TPS22966DPUR_SON14_2X3~D 0.1U_0402_10V7K
1
1
1 2 AUD_NB_MUTE# 2
1
R158 @ R220 0_0402_5%

2
100K_0402_5% R159
100K_0402_5%
Realtek feedback
2
Prevent the Noise from Combo Jack

2
ww
while system entry into S3 / S4 /S

6
<36> DOCK_HP_DET
2 G
D
S
D
S
G 5
DOCK_MIC_DET <36>
Q21B Q21A
1
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Azalia (HD) Codec-ALC3226
LA-9431P
2 1
5 4 3 2 1
m
D D
co
a.
XB use SA00006ZP00 (S IC AP2337SA-7 SOT-23 3P LOAD SWITCH)
+3.3V_RUN
+3.3V_RUN
0.1U_0402_16V4Z
si
@
1
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
C383
+3.3V_RUN
1
1 1 1 1 U50
@ 2
IN
C151
C152
C153
C154
U19
12 42 mDP_LANE_N0 C163 1 2 0.1U_0402_10V7K mDP_LANE_N0_C
2 2 2 2 VDD D0-A
ne
21 41 mDP_LANE_P0 C164 1 2 0.1U_0402_10V7K mDP_LANE_P0_C
1 2 mDP_AUX#_C 34 VDD D0+A 40 mDP_LANE_N1 C165 1 2 0.1U_0402_10V7K mDP_LANE_N1_C
R163 100K_0402_5% VDD D1-A 39 mDP_LANE_P1 C166 1 2 0.1U_0402_10V7K mDP_LANE_P1_C
D1+A 38 mDP_LANE_N2 C168 1 2 0.1U_0402_10V7K mDP_LANE_N2_C
GND
OUT
C DOCKED 2 D2-A 37 mDP_LANE_P2 C170 1 2 0.1U_0402_10V7K mDP_LANE_P2_C C
<21,28,32,36> DOCKED 3 GPU_SEL D2+A 36 mDP_LANE_N3 1 2 mDP_LANE_N3_C
C172 0.1U_0402_10V7K
1 2 mDP_HPD <10> DDI2_LANE_N0 4 D0- D3-A 35 mDP_LANE_P3 1 2 mDP_LANE_P3_C
C173 0.1U_0402_10V7K AP2337SA-7 SOT-23 +VDISPLAY_VCC
<10> DDI2_LANE_P0
3
R164 100K_0402_5% 6 D0+ D3+A 24 mDP_AUX#
<10> DDI2_LANE_N1 D1- AUX-A
.01U_0402_16V7K
1 2 mDP_AUX_C 7 23 mDP_AUX
do
<10> DDI2_LANE_P1 8 D1+ AUX+A 16 mDP_HPD
R165 100K_0402_5%
2 1 <10> DDI2_LANE_N2 9 D2- HPD_A
mDP_CA_DET 1
<10> DDI2_LANE_P2 10 D2+ 33
R167 1M_0402_5%
<10> DDI2_LANE_N3 D3- D0-B DP12412_N0 <21>
C171
1 2 DPB_MB_P14 11 32
<10> DDI2_LANE_P3 D3+ D0+B 31 DP12412_P0 <21>
R168 5.1M_0402_5%
D1-B 30 DP12412_N1 <21> 2
13 D1+B 29 DP12412_P1 <21>
<10> CPU_DPC_AUX# 14 AUX- D2-B 28 DP12412_N2 <21>
<10> CPU_DPC_AUX AUX+ D2+B DP12412_P2 <21>
In
DOCKED 5 27
18 AUX_HPD_SEL D3-B 26 DP12412_N3 <21>
<10> DPC_HPD HPD D3+B 19 DP12412_P3 <21> JmDP1 CONN@
1 AUX-B 20 DP12412_AUX# <21> 20
GND AUX+B DP12412_AUX <21> DP_PWR
0.1U_0402_25V6
17 15 19
@ 22 GND HPD_B DP12412_HPD <21> mDP_AUX#_C 18 GND 24
1 GND AUX_CH_N GND4
C451
43 25 2 1 mDP_LANE_N2_C 17 23
HGND OE +3.3V_RUN LANE2_N GND3
R161 4.7K_0402_5% mDP_AUX_C 16 22
PI3VDP12412ZHEX_TQFN42_9X3P5~D mDP_LANE_P2_C 15 AUX_CH_P GND2 21
i-
2 14 LANE2_P GND1
13 GND
mDP_LANE_N3_C 12 GND
mDP_LANE_N1_C 11 LANE3_N
mDP_LANE_P3_C 10 LANE1_N
DOCKED function mDP_LANE_P1_C 9 LANE3_P
ESD solution for black screen issue 8 LANE1_P
GND
1 Dock 7
is 0 mini DP
DPB_MB_P14
mDP_LANE_N0_C
6
5
GND
CONFIG2
LANE0_N
B mDP_CA_DET 4 B
+3.3V_RUN mDP_LANE_P0_C 3 CONFIG1
AUX/DDC SW for DPC to Mini DP 1 2

mDP_HPD 2
1
LANE0_P
HOT-PLUG
GND
C411 ACON_MAR2C-20K1800
0.1U_0402_25V6
kn
C174 U49
0.1U_0402_10V7K 1 14
mDP_AUX 2 1 SW_mDP_AUX_C 2 BE0 VCC 13
A0 BE3
mDP_AUX_C 3 12
B0 A3 CPU_DPC_CTRLCLK <10>
4 11
Te
mDP_AUX# 2 1 SW_mDP_AUX#_C 5 BE1 B3 10

C175 0.1U_0402_10V7K A1 BE2
mDP_AUX#_C 6 9
B1 A2 CPU_DPC_CTRLDAT <10>
7 8
GND B2
PI3C3125LEX_TSSOP14~D
w.
+3.3V_RUN
100K_0402_5%
1
R67
ww
A A
2
mDP_CA_DET#
1
D
mDP_CA_DET 2
G
Q31
BSS138W-7-F_SOT323-3 Compal Electronics, Inc.
S Title
3
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT mDP/DP12412
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
+0.9V_LAN
2 1
10K_0402_5%
@ C406 XB use SA000066W3L(S IC WGI218LM SLK3A B1 QFN 48P PHY )
2
0.1U_0402_10V7K REGCTL_PNP10 1 2
4.7UH_CBC2012T4R7M_20% L26
R331
0.1U_0402_10V7K
10U_0603_6.3V6M
1 1
C177
C180
U20 @ U21
1
1
P
<12> LAN_RST# B 4 PLT_LAN_RST# 1 2 LANCLK_REQ#_R 48 13 LAN_TX0+
2 O <10,7> LANCLK_REQ# @ R169 0_0402_5% PLT_LAN_RST# 36 CLK_REQ_N MDI_PLUS0 14 LAN_TX0- 2 2
<9> PLTRST_LAN# A PE_RST_N MDI_MINUS0
100K_0402_5%
1
@ CLK_PCIE_LAN 44 17 LAN_TX1+
<7> CLK_PCIE_LAN
3
PE_CLKP MDI_PLUS1
R25
TC7SH08FU_SSOP5~D CLK_PCIE_LAN# 45 18 LAN_TX1-
<7> CLK_PCIE_LAN# PE_CLKN MDI_MINUS1
m
PCIE
2 1 PCIE_PRX_GLANTX_P3_C
MDI
<11> PCIE_PRX_GLANTX_P3
D C179 0.1U_0402_10V7K 38 20 LAN_TX2+ D
2 1 PCIE_PRX_GLANTX_N3_C 39 PETp MDI_PLUS2 21 LAN_TX2-
<11> PCIE_PRX_GLANTX_N3 Place C117, C180 and L26 close to U21
2
1 2 C176 0.1U_0402_10V7K PETn MDI_MINUS2
@ R145 0_0402_5% 1 2 PCIE_PTX_GLANRX_P3_C 41 23 LAN_TX3+
co
<11> PCIE_PTX_GLANRX_P3 PERp MDI_PLUS3
C178 0.1U_0402_10V7K 42 24 LAN_TX3-
+3.3V_LAN 1 2 PCIE_PTX_GLANRX_N3_C PERn MDI_MINUS3 +0.9V_LAN
<11> PCIE_PTX_GLANRX_N3
10K_0402_5%
C181 0.1U_0402_10V7K
1
@ R173
1 2 LAN_SMBCLK_R 28 6 VCT_LAN_R1 @ R175 2 1 0_0402_5%
<7> LAN_SMBCLK
31 SMB_CLK SVR_EN_N Pin 6 is SVR_EN in Clarkville
SMBUS
@ R174 0_0402_5%
SMB_DATA
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
22U_0805_6.3V6M
1 2 LAN_SMBDATA_R 1 +RSVD_VCC3P3_1 R178 2 1 4.7K_0402_5% +3.3V_LAN
<7> LAN_SMBDATA RSVD_VCC3P3_1
@ R177 0_0402_5% 1 1 1 1 1
C187
1 2 LAN_WAKE#_R 2 5 reference INTEL r217 circuit version1.7
<12,37> LAN_WAKE#
2
LANWAKE_N VDD3P3_IN
C183
C184
C185
C186
1 2 @ R179 0_0402_5%
LAN_DISABLE#_R 3
a.
<12> PM_LANPHY_ENABLE LAN_DISABLE_N
@ R180 0_0402_5% SMBus Device Address 0xC8 4 +3.3V_LAN_OUT 2 1 +3.3V_LAN
VDD3P3_4 @ R181 0_0603_5% 2 2 2 2 2
<36> LAN_DISABLE#_R
10K_0402_5%
1U_0603_10V6K
15 1
VDD3P3_15
1
@ R182
Pin 2 is WAKE_EN in Clarkville LOM_ACTLED_YEL# 26 19
LED0 VDD3P3_19
C182
LOM_SPD100LED_ORG# 27 29
+3.3V_LAN LOM_SPD10LED_GRN# 25 LED1 VDD3P3_29 +0.9V_LAN
LED
LED2 2
Note:
1 2 TP_LAN_JTAG_TMS 47
+1.0V_LAN will work at 0.95V to 1.15V
2
@ R171 10K_0402_5% VDD0P9_47 46

VDD0P9_46
si
1 2 TP_LAN_JTAG_TCK @ T92 PAD~D TP_LAN_JTAG_TDI 32 37
@ R172 10K_0402_5% @ T93 PAD~D TP_LAN_JTAG_TDO 34 JTAG_TDI VDD0P9_37
2 1 LAN_WAKE#_R TP_LAN_JTAG_TMS 33 JTAG_TDO 43
JTAG
@ R176 4.7K_0402_5% TP_LAN_JTAG_TCK 35 JTAG_TMS VDD0P9_43
JTAG_TCK 11
VDD0P9_11
XTALO_R 1 2 XTALO 9 40 +3.3V_LAN
@ R183 0_0402_5% XTALI 10 XTAL_OUT VDD0P9_40 22
XTAL_IN VDD0P9_22
1
16
VDD0P9_16
1
ne
8
R206 LAN_TEST_EN 30 VDD0P9_8 PJP20
1M_0402_5% TEST_EN +3.3V_ALW PAD-OPEN1x1m
Y3 RES_BIAS 12 7 REGCTL_PNP10
2
C
3 1 RBIAS CTRL0P9 C
OUT IN
33P_0402_50V8J
49 U22
2
VSS_EPAD
1
33P_0402_50V8J
1K_0402_5%
3.01K_0402_1%
4 2 1 14 1 2
GND GND 2 VIN1 VOUT1 13 +3.3V_LAN_U22 C426 0.1U_0402_10V7K
2 2 WGI218LM-SLK3A-B1_QFN48_6X6~D VIN1 VOUT1
C189
R184
R185
25MHZ_18PF_7V25000034
C190
do
2 1 3 12 1 2
<36,9> SIO_SLP_LAN# ON1 CT1
@ R196 0_0402_5% C407 470P_0402_50V7K
2
2
1 1 4 11
+5V_ALW VBIAS GND
MCARD_WWAN_PWREN 5 10 1 2
<36> MCARD_WWAN_PWREN ON2 CT2 C427 470P_0402_50V7K
6 9
7 VIN2 VOUT2 8 +3.3V_mSATA_WWAN_U22 2 1 +3.3V_mSATA_WWAN
VIN2 VOUT2
15 1 PJP21 PAD-OPEN1x1m
In
GPAD
1 2 MCARD_WWAN_PWREN TPS22966DPUR_SON14_2X3~D @ C425
R50 100K_0402_5% 0.1U_0402_10V7K
LAN ANALOG SWITCH 2
+3.3V_LAN
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
i-
1 1 1
C192
C193
C194
2 2 2
Layout Notice : Place bead as
close PI3L500 as possible
39
30
21
14
8
4
1
U23
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B
B0+
B0-
38
37
is
SW_LAN_TX0+
SW_LAN_TX0-
SW_LAN_TX0+
SW_LAN_TX0-
<35>
<35>
+3.3V_LAN
B
LAN_TX0+ 1 2 LAN_TX0+R 2 @ C198
EMC@ L27 12NH_0603CS-120EJTS_5% A0+ 34 SW_LAN_TX1+ 1 2
B1+ SW_LAN_TX1+ <35>
LAN_TX0- 1 2 LAN_TX0-R 3 33 SW_LAN_TX1-
A0- B1- SW_LAN_TX1- <35>
EMC@ L28 12NH_0603CS-120EJTS_5% 0.1U_0402_10V7K
5
29 SW_LAN_TX2+
LAN_TX1+ 1 2 LAN_TX1+R 6 B2+ 28 SW_LAN_TX2- SW_LAN_TX2+ <35> LOM_SPD100LED_ORG# 1
P
EMC@ L29 12NH_0603CS-120EJTS_5% A1+ B2- SW_LAN_TX2- <35> B 4
kn
LAN_TX1- 1 2 LAN_TX1-R 7 25 SW_LAN_TX3+ LOM_SPD10LED_GRN# 2 O WLAN_LAN_DISB# <36>

A1- B3+ SW_LAN_TX3+ <35> A
G
EMC@ L30 12NH_0603CS-120EJTS_5% 24 SW_LAN_TX3- U24
B3- SW_LAN_TX3- <35>
NL17SZ08DFT2G_SSOP5~D
3
LAN_TX2+ 1 2 LAN_TX2+R 9 17 SW_ACTLED_YEL#
EMC@ L31 12NH_0603CS-120EJTS_5% A2+ LEDB0 18 SW_100_ORG#
LAN_TX2- 1 2 LAN_TX2-R 10 LEDB1 41 SW_10_GRN#
EMC@ L32 12NH_0603CS-120EJTS_5% A2- LEDB2
36 DOCK_LOM_TRD0+
C0+ DOCK_LOM_TRD0+ <34>
LAN_TX3+ 1 2 LAN_TX3+R 11 35 DOCK_LOM_TRD0-
A3+ C0- DOCK_LOM_TRD0- <34>
Te
EMC@ L33 12NH_0603CS-120EJTS_5%

LAN_TX3- 1 2 LAN_TX3-R 12 32 DOCK_LOM_TRD1+
A3- C1+ DOCK_LOM_TRD1+ <34>
EMC@ L34 12NH_0603CS-120EJTS_5% 31 DOCK_LOM_TRD1- Q32B Q33B
C1- DOCK_LOM_TRD1- <34>
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
DOCKED 13 27 DOCK_LOM_TRD2+ SW_ACTLED_YEL# 1 6 LAN_ACTLED_YEL# SW_10_GRN# 1 6 LED_10_GRN#
LAN_ACTLED_YEL# <35> LED_10_GRN# <35>
D
<21,27,32,36> DOCKED SEL C2+ 26 DOCK_LOM_TRD2- DOCK_LOM_TRD2+ <34>
C2- DOCK_LOM_TRD2- <34>
G
LOM_ACTLED_YEL# 15 23 DOCK_LOM_TRD3+
DOCK_LOM_TRD3+ <34>
2
LOM_SPD100LED_ORG# 16 LEDA0 C3+ 22 DOCK_LOM_TRD3-
LEDA1 C3- DOCK_LOM_TRD3- <34>
w.
LOM_SPD10LED_GRN# 42 MASK_BASE_LEDS# MASK_BASE_LEDS#

LEDA2 MASK_BASE_LEDS# <40>
19 DOCK_LOM_ACTLED_YEL#
LEDC0 DOCK_LOM_ACTLED_YEL# <34>
5 20 DOCK_LOM_SPD100LED_ORG# Q33A
PD LEDC1 DOCK_LOM_SPD100LED_ORG# <34>
40 DOCK_LOM_SPD10LED_GRN# DMN66D0LDW-7_SOT363-6
LEDC2 DOCK_LOM_SPD10LED_GRN# <34>
43 Q32A 4 3
1: TO DOCK
D
PAD_GND DMN66D0LDW-7_SOT363-6
DOCKED SW_100_ORG# 4 3 LED_100_ORG#
G
LED_100_ORG# <35>
D
0: TO RJ45
5
G
A A
ww
PI3L720ZHEX_TQFN42_9X3P5~D
5
MASK_BASE_LEDS#
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT LAN Lewisville / LAN SW
0.3
5 4 3 2 1
5 4 3 2 1
m
D D
co
+3.3V_RUN +3.3V_RUN_TPM
@ PJP5
1 2
+3.3V_RUN_TPM
PAD-OPEN1x1m
+3.3V_RUN_TPM +3.3V_SUS
a.
0.1U_0402_25V6
4700P_0402_25V7K
ATMEL TPM for E4
1 1 USH board conn
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0402_25V6
@ 1 2 USH_SMBCLK
C200
C201
R190 2.2K_0402_5%
U25 1 1 1 1 1 2 USH_SMBDAT
2 2 @ R191 2.2K_0402_5%
C203
C202
C384
C204
10 1 2 USH_PWR_STATE# CONN@
si
5 VCC_0 19 R195 1M_0402_5% JUSH1
SB3V VCC_1 24 2 2 2 2 1
PCH_TPM_LPC_EN 1 2 VCC_2 2 1 +5V_RUN +3.3V_RUN +3.3V_SUS
<7> PCH_TPM_LPC_EN <11> USBP4- 2
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
@ R198 10_0402_5% 3
<11> USBP4+ 4 3
USH_SMBCLK 5 4 @ @ @
<37> USH_SMBCLK 5 1 1 1
C208
C207
C206
1 2 SP_TPM_LPC_EN_R 28 12 USH_SMBDAT 6
<36> SP_TPM_LPC_EN LPCPD# V_BAT 13 <37> USH_SMBDAT 7 6
@ R193 0_0402_5%
NBO_13 <36> BCM5882_ALERT# 7
ne
LPC_LAD0 26 14 8
<25,36,37,7> LPC_LAD0 23 LAD0 NBO_14 9 8 2 2 2
LPC_LAD1
<25,36,37,7> LPC_LAD1 LAD1 +3.3V_SUS 9
LPC_LAD2 20 10
<25,36,37,7> LPC_LAD2 LPC_LAD3 17 LAD2 11 10
C <25,36,37,7> LPC_LAD3 LAD3 6 12 11 C
GPIO6 13 12
+3.3V_RUN 13
21 9 14
<7> CLK_PCI_TPM_TCM LCLK TESTBI +5V_RUN 14
LPC_LFRAME# 22 8 15
<25,36,37,7> LPC_LFRAME# 16 LFRAME# TESTI <9> PLTRST_USH# USH_PWR_STATE# 16 15
do
<25,31,36,37,9> PCH_PLTRST#_EC IRQ_SERIRQ 27 LRESET# <36> USH_PWR_STATE# 17 16
<12,36,37> IRQ_SERIRQ 15 SERIRQ <10> CONTACTLESS_DET# 18 17
CLKRUN#
<10,36,37,9> CLKRUN# CLKRUN# 7 19 18 21
NC_7 20 19 GND 22
1 4 <12> USH_DET# 20 GND
2 ATEST_1 GND_4 11 E-T_6718K-Y20N-00L
3 ATEST_2 GND_11 18
ATEST_3 GND_18 25
GND_25
In
AT97SC3204-X4A12-ABF _TSSOP28
XB use SA00004WQ50(S IC AT97SC3204-X4A12-ABF TSSOP 28P TPM) ST change to 6718K-Y20N-00L
i-
is
B B
kn
Te
w.
ww
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USH board conn / TPM
LA-9431P
5 4 3 2 1
A B C D E
+3.3V_RUN +3.3V_RUN
+3.3V_RUN_CARD +1.8V_RUN_CARD
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
C215 close to U27.9
C213 C214 close to U27.35
L35
@ @
1
0.1U_0402_25V6
4.7U_0603_6.3V6K
0.1U_0402_25V6
C229
C228
1 2 +3.3V_RUN_AIN @
C227
BLM15AG601SN1D_2P
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
2
C210
C211
C212
1
2
C213
C214
C215
2
m
1 C210 close to U27.42 C227 near U27.22 C228 C229 near U27.24 1
C211 C212 close to U27.23
homestay ES1(no SD4.0)
co
+1.2V_LDO +3.3V_RUN
use 3.3V
U27
SSI ES2(symbol should be update 26~36 pin swap) please routing daisy chain
1. from U27.38 (SD_D0) -> U27.32 (SD_RCLK_P) -> L46.4
2. From U27.37 (SD_D1) -> U27.33 (SD_RCLK_N) -> L46.1
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
9 12 +AUX_LDO @ R231 1 2 0_0402_5%

PE_33VCCAIN
OZ777FJ2LN AUX_LDO_CAP
4.7U_0603_6.3V6K
0.1U_0402_25V6
4.7U_0603_6.3V6K
0.1U_0402_25V6
a.
2
27 L46 @
2 UHSII_33VCCAIN/NC
2
C223
C217
C218
25 +SD_IO_LDO SD/MMCDAT0 4 3 SD/MMCDAT0_D

SD_IO_LDO_CAP 4 3
1U_0402_6.3V6K
C224
C219
C225
C226
4.7U_0603_6.3V6K
0.1U_0402_25V6
4.7U_0603_6.3V6K
1
42 2
1
1
SD_33VCCD
C222
2
2
@ SD/MMCDAT1 1 2
1 2
C220
C216
C221
23 SD/MMCDAT1_D
SD_SKT_33VIN DLW21SN900SQ2L-0805_4P
1
13 22 1
+3.3V_RUN_CARD
si
AUX _33VIN SD_SKT_33VOUT 1 2
11 24 @ R297 0_0402_5%
+1.2V_LDO MAIN_LDO_VIN SD_SKT_18VOUT +1.8V_RUN_CARD
L36 10
1 2 +1.2V_LDO_AIN MAIN_LDO_12VOUT
BLM15AG601SN1D_2P @ R306 1 2 0_0402_5%
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6 41
CORE_12VCCD 20 SDWP L47 @
SD_WPI
2
ne
@ 36 21 SD/MMCCD# SD_UHS2_D0P 4 3 SD_UHS2_D0P_D
UHSII_12VCCAIN/NC SD_CD# 4 3
C230
C231
C232
C233
C234
31 EMC@
28 UHSII_12VCCAIN/NC 43 SD/MMCCLK_R R230 1 2 10_0402_5% SD/MMCCLK
1
UHSII_12VCCAIN/NC SD_CLK 45 SD/MMCCMD SD_UHS2_D0N 1 2 SD_UHS2_D0N_D

SD_CMD 1 2
5P_0402_50V8C
2 1 2
PE_12VCCAIN 39 DLW21SN900SQ2L-0805_4P
MMC_D7 1
@
40
MMC_D6
C255
44 1 2
1 2 PE_REXT 4 MMC_D5 46 @ R315 0_0402_5%
do
R205 191_0402_1% PE_REXT MMC_D4 47 SD/MMCDAT3 @ R410 1 2 0_0402_5% SD/MMCDAT3_R 2
C235 1 2 0.1U_0402_10V7K PCIE_PTX_MMIRX_P5_C 6 SD_D3 48 SD/MMCDAT2 @ R341 1 2 0_0402_5% SD/MMCDAT2_R
<11> PCIE_PTX_MMIRX_P5 PE_RXP SD_D2
C236 1 2 0.1U_0402_10V7K PCIE_PTX_MMIRX_N5_C 5 37 SD/MMCDAT1 @ R333 1 2 0_0402_5%
<11> PCIE_PTX_MMIRX_N5 PE_RXM SD_D1 38 SD/MMCDAT0
C237 1 2 0.1U_0402_10V7K PCIE_PRX_MMITX_P5_C 7 SD_D0 L48 @
<11>
<11>
PCIE_PRX_MMITX_P5
PCIE_PRX_MMITX_N5
C238 1 2 0.1U_0402_10V7K PCIE_PRX_MMITX_N5_C 8 PE_TXP
PE_TXM SD_RCLK_M/NC
29 EMI depop location(EMC) SD_UHS2_D1P 1
1 2
2 SD_UHS2_D1P_D
30
2 SD_RCLK_P/NC 32 SD_UHS2_D1P
<7> CLK_PCIE_MMI# PE_REFCLKM SD_D1P/NC
In
3 33 SD_UHS2_D1N SD_UHS2_D1N 4 3 SD_UHS2_D1N_D
<7> CLK_PCIE_MMI PE_REFCLKP SD_D1M/NC 34 SD_UHS2_D0N 4 3
PE_RST# 15 SD_D0M/NC 35 SD_UHS2_D0P DLW21SN900SQ2L-0805_4P
PE_RST#_GATE# SD_D0P/NC
14 26 R211 1 2 4.7K_0402_1% 1 2
<11,12> MEDIACARD_PWREN MAIN_LDO_EN SD_REXT/NC @ R337 0_0402_5%
16
<12> MEDIACARD_IRQ# DEV_WAKE#
17 19
i-
<7> MMICLK_REQ# CLKREQ# LED#
IO_LDOSEL 18 49
IO0_LDOSEL GND
OZ777FJ2LN_QFN48_6X6
MMC+ need confirm
Near to JSD1
is +3.3V_RUN_CARD
+1.8V_RUN_CARD
4
JSD1 CONN@
VDD/VDD1
3 @ R443 1 2 0_0402_5% +3.3V_RUN_CARD 14 3
SD/MMCCMD 2 VDD2
SD/MMCCLK 5 CMD
+3.3V_RUN CLK
SD/MMCCD# 18
+3.3V_RUN 0.1U_0402_25V6 @ C341
@C341 SDWP 19 CARD DETECT
WRITE PROTEC
0.1U_0402_25V6
4.7U_0603_6.3V6K
1 2
kn
1 1 SD/MMCCD# SD/MMCDAT0_D 7
DAT0/RCLK+
1
@U26
@ U26 @ SD/MMCDAT1_D 8
DAT1/RCLK-
C239
C240
0.1U_0402_25V6
1M_0402_5%
R212 1 SD/MMCDAT2_R 9
P
<9> PLTRST_MMI# B DAT2
1
100K_0402_5% 4 PE_RST# 1 SD/MMCDAT3_R 1
O 2 2 CD/DAT3
R493
2 SD_UHS2_D0P_D 11
<12> MEDIACARD_RST# A D0+
G
100K_0402_5%
C256
SD_UHS2_D0N_D 12
2
IO_LDOSEL SD_UHS2_D1P_D 16 DO-

3
D1+
1
TC7SH08FU_SSOP5~D @ 2 SD_UHS2_D1N_D 15 20
Te
2
D1- GND1
1
R27
21
@ R214 3 GND2 22
100K_0402_5% +1.8V_RUN_CARD 6 VSS1 GND3 23
10 VSS2 GND4 24
2
13 VSS3 GND5 25
2
17 VSS4 GND6 26
O2 request VSS5 GND7
ALPS_SCDADA0101_NR
w.
0.1U_0402_25V6
4.7U_0603_6.3V6K
1 1
C246
2 2 C247
ww
4 4
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Card Reader OZ777FJ2
A B C D E
5 4 3 2 1
+3.3V_WLAN
Mini WWAN/GPS/LTE/mSATA H=3.6 Mini WLAN/WIiGi/BT H=3.6
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.1U_0402_25V6
0.1U_0402_25V6
4.7U_0603_6.3V6K
0.1U_0402_25V6
@ C257
1 1 1 2 2 1
+3.3V_mSATA_WWAN +3.3V_mSATA_WWAN +3.3V_WLAN +3.3V_WLAN
C258
C259
C260
C261
C262
JMINI2 CONN@
<37> PCIE_WAKE# PCIE_WAKE# 1 2 JMINI1 CONN@
3 1 2 4 PCIE_WAKE# 1 2 2 2 2 1 1 2
5 3 4 6 3 1 2 4
MINI1CLK_REQ# 7 5 6 8 5 3 4 6
<7> MINI1CLK_REQ# 7 8 +SIM_PWR 5 6
9 10 UIM_DATA 7 8
m
CLK_PCIE_MINI1# 11 9 10 12 UIM_CLK <7> MINI2CLK_REQ# 9 7 8 10 1 2
D <7> CLK_PCIE_MINI1# CLK_PCIE_MINI1 13 11 12 14 UIM_RESET 11 9 10 12 D
<7> CLK_PCIE_MINI1 15 13 14 16 UIM_VPP <7> CLK_PCIE_MINI2# 13 11 12 14 MSDATA C241 4700P_0402_25V7K
17 15 16 18 <7> CLK_PCIE_MINI2 15 13 14 16
17 18 15 16 HOST_DEBUG_TX <37>
co
19 20 17 18
21 19 20 22 MINI_CARD_RST# WWAN_RADIO_DIS# <36> <36,37> EC5048_TX 19 17 18 20 WLAN_RADIO_DIS#_R
23 21 22 24 <37> MSCLK 21 19 20 22 MINI_CARD_RST#
<6> SATA_PRX_mSATATX_P3 25 23 24 26 23 21 22 24
<6> SATA_PRX_mSATATX_N3 27 25 26 28 <11> PCIE_PRX_WLANTX_N4 25 23 24 26
3@ C244 0.1U_0402_10V7K 29 27 28 30 WWAN_SMBCLK <11> PCIE_PRX_WLANTX_P4 27 25 26 28
1 2 SATA_PTX_mSATARX_N3_C 31 29 30 32 WWAN_SMBDAT C242 0.1U_0402_10V7K 29 27 28 30
<6> SATA_PTX_mSATARX_N3 1 2 SATA_PTX_mSATARX_P3_C 33 31 32 34 1 2PCIE_PTX_WLANRX_N4_C 31 29 30 32 WIGIG60GHZ_DIS#_R
<6> SATA_PTX_mSATARX_P3 35 33 34 36 <11> PCIE_PTX_WLANRX_N4 1 2PCIE_PTX_WLANRX_P4_C 33 31 32 34
C245 0.1U_0402_10V7K
a.
37 35 36 38 USBP6- <11> <11> PCIE_PTX_WLANRX_P4 35 33 34 36
3@ C243 0.1U_0402_10V7K
39 37 38 40 USBP6+ <11> 37 35 36 38 USBP2- <11>
41 39 40 42 LED_WWAN_OUT# <12> CPPE# 39 37 38 40 USBP2+ <11>
43 41 42 44 41 39 40 42 CPUSB# <12>
mSATA_DEVSLP WIMAX_LED#
45 43 44 46 mSATA_DEVSLP <12> 43 41 42 44 WLAN_LED#
47 45 46 48 45 43 44 46 BT_LED#
49 47 48 50 <7> PCH_CL_CLK1 47 45 46 48 1 2
51 49 50 52 <7> PCH_CL_DATA1 47 48 MSDATA <37>
@ R223 1 2 0_0402_5% 49 50 @ R222 0_0402_5%
si
<36> HW_GPS_DISABLE2# 51 52 <7> PCH_CL_RST1# 51 49 50 52
53 54 BT_RADIO_DIS#_R 51 52 WIMAX_LED# STUDY FOR DEBUG
+3.3V_mSATA_WWAN GND1 GND2 53 54
GND1 GND2
LCN_DAN08-52216-0100
1 2 mSATA_DEVSLP LCN_DAN08-52216-0100
@R160
@ R160 10K_0402_5% 1 2
+3.3V_mSATA_WWAN +3.3V_mSATA_WWAN @ R215 0_0402_5%
ne
D12
1 2 WLAN_RADIO_DIS#_R
<36> WLAN_RADIO_DIS#
0.047U_0402_16V4Z
0.047U_0402_16V4Z
33P_0402_50V8J
22U_0805_6.3V6M
33P_0402_50V8J
150U_B2_6.3VM_R35M
150U_B2_6.3VM_R35M
2.2K_0402_5%
2.2K_0402_5%
1 1 RB751S40T1G_SOD523-2
1
1
@ R216
@ R217
3@ C248
3@ C249
3@ C250
3@ C251
3@ C252
3@ C253
C C
1 1 1 1 1
+ + @
C254
1 2 Primary Power Aux Power
2 2 2 2 2 2 2
@ R224 0_0402_5% PWR Voltage
D13
do
Rail Tolerance
2
1 2 WIGIG60GHZ_DIS#_R Peak Normal Normal

2 1 <36> WIGIG60GHZ_DIS#
WWAN_SMBCLK
<18,19,7,9> DDR_XDP_WAN_SMBCLK
@ R218 0_0402_5% RB751S40T1G_SOD523-2
2 1 WWAN_SMBDAT +3.3V +-9% 1000 750
<18,19,7,9> DDR_XDP_WAN_SMBDAT
@ R219 0_0402_5%
250 (Wake enable)
1 2 +3.3Vaux +-9% 330 250 5 (Not wake enable)
@ R225 0_0402_5%
In
D14
1 2 BT_RADIO_DIS#_R
<36> BT_RADIO_DIS#
RB751S40T1G_SOD523-2
+3.3V_HDD LED control circuit
i-
1
+3.3V_WLAN
PJP22
3.3V_ALW for LID power PAD-OPEN1x1m
+3.3V_ALW
100K_0402_5%
100K_0402_5%
100K_0402_5%
U3
2
is
2
1 14 1 2
VIN1 VOUT1
R229
R227
R228
2 13 +3.3V_HDD_U3 @ C428 0.1U_0402_10V7K
B CONN@ VIN1 VOUT1 B
14 1 2 3 12 1 2
GND2 <12> 3.3V_HDD_EN ON1 CT1
5
13 @R129
@ R129 0_0402_5% C429 470P_0402_50V7K Q22A
1
GND1 4 11
G
+5V_ALW VBIAS GND WIMAX_LED# 4 3
12 5 10 1 2 WIRELESS_LED# <36,40>
D
AUX_EN_WOWL
+3.3V_ALW 12 <36> AUX_EN_WOWL ON2 CT2
11
kn
C409 470P_0402_50V7K DMN66D0LDW-7_SOT363-6
<36,40> LID_CL# 11
2
10 6 9
9 10 7 VIN2 VOUT2 8 +3.3V_WLAN_U3 2 1 Q22B
G
+SIM_PWR 9 VIN2 VOUT2 +3.3V_WLAN
UIM_DATA 8 WLAN_LED# 1 6
7 8 15
D
UIM_VPP PJP23 PAD-OPEN1x1m
UIM_RESET 6 7 GPAD DMN66D0LDW-7_SOT363-6
6 1 @ C422
2
5 TPS22966DPUR_SON14_2X3~D Q30B
UIM_CLK 4 5 0.1U_0402_10V7K
G
3 4 BT_LED# 1 6
Te
2 3 1 2 2
D
AUX_EN_WOWL
1 2 R51 100K_0402_5% DMN66D0LDW-7_SOT363-6
<40,41> +COINCELL 1
JSH1
+3.3V_mSATA_WWAN
E-T_6718K-Y12N-01L
100K_0402_5%
w.
2
R226
1 2
+3.3V_ALW @R131
@ R131 0_0402_5%
0.1U_0402_16V4Z
5
ST change to 6718K-Y12N-01L & swap pin Q30A
1
+3.3V_RUN
G
1
@ LED_WWAN_OUT# 4 3
C50
D
0.1U_0402_25V6 @ C338
ww
A 2 1 DMN66D0LDW-7_SOT363-6 A
2
@
5
U30
1
P
<25,29,36,37,9> PCH_PLTRST#_EC B 4 MINI_CARD_RST#

O
100K_0402_5%
2
<6,7> MPCIE_RST# A
G

1
TC7SH08FU_SSOP5~D @
3
R26
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Mini Card/SIM Card
2

LA-9431P
5 4 3 2 1
5 4 3 2 1
m
D D
co
a.
si
ne
C C
do
In
i-
SA000064200
+3.3V_SUS
is U33
4.7U_0603_6.3V6K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6 3
B 9 VDD 31 B
12 VDD TX+A 30 SW_USB3TP3 <33>
1 1 1 1 1 1 1 VDD TX-A SW_USB3TN3 <33>
@ @ @ 16 27
VDD RX+A SW_USB3RP3 <33>
C420
C419
C418
C415
C417
C414
C416
20 26
29 VDD RX-A 19 SW_USB3RN3 <33>
2 2 2 2 2 2 2 VDD D+A 18 SW_USBP5+ <33>
D-A 17 SW_USBP5- <33>
kn
USB_IDA
25
check port mapping 1 TX+B 24 DOCK_USB3TP3 <34>
<11> USB3TP3 2 TX+ TX-B 23 DOCK_USB3TN3 <34>
DOCKED function <11> USB3TN3 4 TX- RX+B 22 DOCK_USB3RP3 <34>
<11> USB3RP3 5 RX+ RX-B 15 DOCK_USB3RN3 <34>
1 Dock <11> USB3RN3 6 RX- D+B 14 DOCK_USBP5+ <34>
Te
<11> USBP5+ 7 D+ D-B 13 DOCK_USBP5- <34>

0 M/B <11> USBP5- 8 D- USB_IDB
USB_ID
11
OE#
10 21
<21,27,28,36> DOCKED 32 SS_SEL GND 28
HS_SEL GND
w.
33
HGND
PI3USB3102ZLEX_TQFN32_6X3
ww
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Mini Card PWR
LA-9431P
5 4 3 2 1
5 4 3 2 1
L37 EMC@
4 3 USB3RN3_D- +USB_PWR
<32> SW_USB3RN3
JUSB2 CONN@
1 2 USB3RP3_D+ D15 EMC@ 1
<32> SW_USB3RP3 USB3RN3_D- 1 9 USB3RN3_D- USBP5_D- 2 VBUS
DLW21SN670HQ2L_4P USBP5_D+ 3 D-
1 2 USB3RP3_D+ 2 8 USB3RP3_D+ 4 D+
GND
150U_B2_6.3VM_R35M
0.1U_0402_25V6
@ R235 0_0402_5% USB3RN3_D- 5
USB3TN3_D- 4 7 USB3TN3_D- USB3RP3_D+ 6 SSRX- 10
1 SSRX+ GND
1 2 1 7 11
@ R236 0_0402_5% USB3TP3_D+ 5 6 USB3TP3_D+ + USB3TN3_D- 8 GND GND 12
m
SSTX- GND
3
C280
C281
USB3TP3_D+ 9 13
SSTX+ GND
EMC@D16
EMC@
D L38 EMC@ D
2 1 SW_USB3TN3_C 4 3 USB3TN3_D- 2 2 SANTA_373070-1
<32> SW_USB3TN3
C282 0.1U_0402_10V7K 3
co
D16
<32> SW_USB3TP3 2 1 SW_USB3TP3_C 1 2 USB3TP3_D+ TVWDF1004AD0_DFN9
C283 0.1U_0402_10V7K
DLW21SN670HQ2L_4P
1 2
1
@ R237 0_0402_5%
1 2
@ R239 0_0402_5%
a.
+5V_ALW +USB_PWR
L39 EMC@
SW_USBP5+ 1 2 USBP5_D+ U32
<32> SW_USBP5+ 1 2 1 8
2 GND VOUT 7
VIN VOUT
0.1U_0402_25V6
SW_USBP5- 4 3 USBP5_D- 3 6
<32> SW_USBP5- 4 3 4 VIN VOUT 5
<36> ESATA_USB_PWR_EN# EN FLG USB_OC2# <11>
10U_0603_6.3V6M
DLW21HN900SQ2L_4P 1 1
si
1 2 G547I2P81U_MSOP8
C284
C285
@ R238 0_0402_5%
1 2 2 2
@ R240 0_0402_5%
ne
C +5V_ALW C
2
R243
do
100K_0402_5%
+5V_USB_CHG_PWR
1
1 2 PWRSHARE_EN#
<36> USB_PWR_SHR_VBUS_EN
@R241
@ R241 0_0402_5% JUSB1 CONN@
1
U39 D 1
1 2 SB# 8 1 PWRSHARE_EN 2 Q7 USBP0_D- 2 VBUS
<36> USB_PWR_SHR_EN# CB CEN D-
In
@ R242 0_0402_5% SW_USBP0- 7 2 PS_USBP0_D- G L2N7002WT1G_SC-70-3 USBP0_D+ 3
TDM DM D+
150U_B2_6.3VM_R35M
0.1U_0402_25V6
SW_USBP0+ 6 3 PS_USBP0_D+ S 4
3
+3.3V_ALW 5 TDP DP 4 SEL 1 2 USB3RN2_D- 5 GND
VddSMART-CDP +5V_ALW 1 SSRX-
+5V_ALW 9 R244 10K_0402_5% 1 USB3RP2_D+ 6 10
U36 Thermal-Pad SSRX+ GND
0.1U_0402_25V6
+ 7 11
GND GND
C290
C291
10 1 SW_USBP0+ SLG55594AVTR_TDFN8_2X2 USB3TN2_D- 8 12
VCC 1D+ SSTX- GND
2
0.1U_0402_25V6
1 9 2 SW_USBP0- 1 USB3TP2_D+ 9 13
<36> DOCKED_LIO_EN S 1D- 2 2 SSTX+ GND
EMC@ D18
8 3
<11> USBP0+ D+ 2D+ DOCK_USBP0+ <34>
C322
C287
7 4 SANTA_373070-1
i-
<11> USBP0- 6 D- 2D- 5 DOCK_USBP0- <34>
2 OE# GND 2
NX3DV221GM_XQFN10U10_2X1P55
check port mapping
1
DOCKED_LIO_EN function
is
B 1 Dock B
0 M/B
D17 EMC@
USB3RN2_D- 1 9 USB3RN2_D- +5V_ALW +5V_USB_CHG_PWR
USB3RP2_D+ 2 8 USB3RP2_D+
kn
L40 EMC@ U35
4 3 USB3RN2_D- 1 8
<11> USB3RN2 4 3 GND VOUT
0.1U_0402_25V6
USB3TN2_D- 4 7 USB3TN2_D- 2 7
3 VIN VOUT 6
1 2 USB3RP2_D+ USB3TP2_D+ 5 6 USB3TP2_D+ PWRSHARE_EN# 4 VIN VOUT 5
<11> USB3RP2 1 2 1 EN FLG USB_OC0# <11>
10U_0603_6.3V6M
1
C289
DLW21SN900HQ2L-0805_4P G547I2P81U_MSOP8
C288
1 2
@ R246 0_0402_5% 3 2
Te
2
1 2 TVWDF1004AD0_DFN9
@ R247 0_0402_5%
L41 EMC@ EMC@ L42

2 1 USB3TN2_C 4 3 USB3TN2_D- PS_USBP0_D+ 4 3 USBP0_D+
<11> USB3TN2 4 3
w.
C292 0.1U_0402_10V7K
2 1 USB3TP2_C 1 2 USB3TP2_D+ PS_USBP0_D- 1 2 USBP0_D-

<11> USB3TP2 1 2
C293 0.1U_0402_10V7K
DLW21SN900HQ2L-0805_4P CMM0805-120Y-N_4P
1 2 1 2
@ R248 0_0402_5% @R249
@ R249 0_0402_5%
1 2 1 2
ww
A @ R250 0_0402_5% @R251

@ R251 0_0402_5% A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USB x2
LA-9431P
5 4 3 2 1
5 4 3 2 1
JDOCK1 CONN@
DOCK_DET_1 1 2 DOCK_AC_OFF
3 1 2 4 DOCK_AC_OFF <48>
<28> DOCK_LOM_SPD10LED_GRN# DPC_CA_DET 5 3 4 6 DPB_CA_DET DOCK_LOM_SPD100LED_ORG# <28>
m
<21,24> DPC_CA_DET 7 5 6 8 DPB_CA_DET <21,24>
D C302 2 1 0.1U_0402_10V7KDPC_LANE_P0_C R259 1 2 33_0402_5% DPC_DOCK_LANE_P0 9 7 8 10 DPB_DOCK_LANE_P0 R260 1 2 33_0402_5% DPB_LANE_P0_C C294 2 1 0.1U_0402_10V7K D
<21> DPC_LANE_P0 9 10 DPB_LANE_P0 <21>
C295 2 1 0.1U_0402_10V7KDPC_LANE_N0_C R252 1 2 33_0402_5% DPC_DOCK_LANE_N0 11 12 DPB_DOCK_LANE_N0 R261 1 2 33_0402_5% DPB_LANE_N0_C C296 2 1 0.1U_0402_10V7K
<21> DPC_LANE_N0 13 11 12 14 DPB_LANE_N0 <21>
13 14
co
C297 2 1 0.1U_0402_10V7KDPC_LANE_P1_C R253 1 2 33_0402_5% DPC_DOCK_LANE_P1 15 16 DPB_DOCK_LANE_P1 R254 1 2 33_0402_5% DPB_LANE_P1_C C298 2 1 0.1U_0402_10V7K
C304 2 1 0.1U_0402_10V7KDPC_LANE_P2_C R257 1 2 33_0402_5% DPC_DOCK_LANE_P2 21 19 20 22 DPB_DOCK_LANE_P2 R262 1 2 33_0402_5% DPB_LANE_P2_C C305 2 1 0.1U_0402_10V7K
C300 2 1 0.1U_0402_10V7KDPC_LANE_P3_C R265 1 2 33_0402_5% DPC_DOCK_LANE_P3 27 25 26 28 DPB_DOCK_LANE_P3 R258 1 2 33_0402_5% DPB_LANE_P3_C C308 2 1 0.1U_0402_10V7K
a.
DPC_DOCK_AUX 33 31 32 34 DPB_DOCK_AUX
<24> DPC_DOCK_AUX 35 33 34 36 DPB_DOCK_AUX <24>
DPC_DOCK_AUX# DPB_DOCK_AUX#
<24> DPC_DOCK_AUX# 37 35 36 38 DPB_DOCK_AUX# <24>
DPC_DOCK_HPD 39 37 38 40 DPB_DOCK_HPD
<21> DPC_DOCK_HPD 41 39 40 42 DPB_DOCK_HPD <21>
+NBDOCK_DC_IN_SS 41 42 ACAV_DOCK_SRC# <48>
0.033U_0402_16V7K
0.033U_0402_16V7K
43 44
ESD depop location(EMC) 1
@
<21> BLUE_DOCK
BLUE_DOCK 45 43
45
44
46
46
DAT_DDC2_DOCK <21>
1
@ ESD depop location(EMC)
C310
C311
47 48
si
49 47 48 50 CLK_DDC2_DOCK <21>
2 49 50 2
Close to DOCK
51 52
RED_DOCK 53 51 52 54 SATA_PRX_DKTX_P0 C312 2 1 .01U_0402_16V7K Its for Enhance ESD on dock issue.
<21> RED_DOCK 55 53 54 56 SATA_PRX_DKTX_P0_C <6>
Close to DOCK SATA_PRX_DKTX_N0 C313 2 1 .01U_0402_16V7K
57 55 56 58 SATA_PRX_DKTX_N0_C <6>
Its for Enhance ESD on dock issue. GREEN_DOCK 59 57 58 60 SATA_PTX_DKRX_P0 C314 1 2 .01U_0402_16V7K
<21> GREEN_DOCK 61 59 60 62 SATA_PTX_DKRX_P0_C <6>
SATA_PTX_DKRX_N0 C315 1 2 .01U_0402_16V7K
63 61 62 64 SATA_PTX_DKRX_N0_C <6>
63 64
ne
65 66 DOCK_USBP0_D+ 2 1
<21> HSYNC_DOCK 67 65 66 68 2 1 DOCK_USBP0+ <33>
DOCK_USBP0_D-
DPC_DOCK_HPD <21> VSYNC_DOCK 69 67 68 70
71 69 70 72 3 4
C <37> CLK_MSE 73 71 72 74 DOCK_USBP5+ <32> 3 4 DOCK_USBP0- <33> C
<37> DAT_MSE 75 73 74 76 DOCK_USBP5- <32>
DLW21SN900SQ2L-0805_4P
75 76
1
77 78 @ L43 DPB_DOCK_HPD
<26> DAI_BCLK# 79 77 78 80 CLK_KBD <37> 2 1
<26> DAI_LRCK# 81 79 80 82 DAT_KBD <37>
R268 @ R269 0_0402_5%
do
100K_0402_5% 83 81 82 84 2 1
<26> DAI_DI 83 84 DOCK_USB3RN3 <32>
1
85 86 @ R270 0_0402_5%
<26> DAI_DO# DOCK_USB3RP3 <32>
2
87 85 86 88
89 87 88 90
<26> DAI_12MHZ# 89 90 DOCK_USB3TN3 <32> EMI solution for E-Docking USB(EMC) R271
91 92 100K_0402_5%
93 91 92 94 DOCK_USB3TP3 <32>
2
95 93 94 96
97 95 96 98
<36> D_LAD0 97 98 BREATH_LED# <36,40>
In
99 100
<36> D_LAD1 101 99 100 102 DOCK_LOM_ACTLED_YEL# <28>
103 101 102 104
<36> D_LAD2 105 103 104 106 DOCK_LOM_TRD0+ <28>
<36> D_LAD3 107 105 106 108 DOCK_LOM_TRD0- <28> +3.3V_ALW
109 107 108 110
<36> D_LFRAME# 111 109 110 112 DOCK_LOM_TRD1+ <28> +LOM_VCT
<36> D_CLKRUN# 113 111 112 114 DOCK_LOM_TRD1- <28> DOCK_DET# 1 2
115 113 114 116 R272 10K_0402_5%
i-
<36> D_SERIRQ 115 116 1
117 118 @
<36> D_DLDRQ1# 117 118 +LOM_VCT
119 120 C316
121 119 120 122 1U_0402_6.3V6K
<7> CLK_PCI_DOCK 123 121 122 124 DOCK_LOM_TRD2+ <28> 2
125 123 124 126 DOCK_LOM_TRD2- <28>
127 125 126 128
<37> DOCK_SMB_CLK 129 127 128 130 DOCK_LOM_TRD3+ <28>
<37> DOCK_SMB_DAT 131 129 130 132 DOCK_LOM_TRD3- <28>
<36,41,48> DOCK_SMB_ALERT#
<41> DOCK_PSID
is 133
135
131
133
135
132
134
136
134
136 DOCK_DCIN_IS+
DOCK_DCIN_IS-
<47>
<47>
B 137 138 B
139 137 138 140
<37> DOCK_PWR_BTN# 141 139 140 142 DOCK_POR_RST# <37>
D19
SLICE_BAT_PRES# 143 141 142 144 DOCK_DET_R# 1 2
<36,41,48> SLICE_BAT_PRES# 143 144 DOCK_DET# <36,48>
145 148 RB751S40T1G_SOD523-2
146 GND1 GND2 149
kn
+DOCK_PWR_BAR PWR1 PWR2 +DOCK_PWR_BAR

147 150
PWR1 PWR2
0.1U_0603_50V7K
PESD24VS2UT_SOT23-3
0.1U_0603_50V7K
3
2
4.7U_0805_25V6-K
151 157 1
Shield_G Shield_G
C318
1 @ 1 @ 152 158
Shield_G Shield_G
C317
153 159
Shield_G Shield_G
CE7
D20
154 160
155 Shield_G Shield_G 161 2
2 2 156 Shield_G Shield_G 162
Te
1
Shield_G Shield_G
DAI_12MHZ# DAI_BCLK# CLK_PCI_DOCK
WD2F144WB8
1
JAE_WD2F144WB8-DT
@ RE4 @ RE5 @ R273
10_0402_1% 10_0402_1% 33_0402_5%
ESD depop location(EMC)
2
w.
1 1 1
@CE8
@CE8 @CE9
@CE9 @ C319
4.7P_0402_50V8C 4.7P_0402_50V8C 12P_0402_50V8J
2 2 2
ww
A EMI depop location(EMC) A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT E series Dock Connector
5 4 3 2 1
5 4 3 2 1
T94
<28> SW_LAN_TX1-
SW_LAN_TX1- 1
TD1+
1:1
TX1+
24 NB_LAN_TX1-
RJ45 LOM circuit
SW_LAN_TX1+ 2
<28> SW_LAN_TX1+ TD1- 23 NB_LAN_TX1+ +3.3V_LAN
TX1-
m
D 3 22 Z2805 D
TDCT1 TXCT1
470P_0402_50V7K
co
0.1U_0402_10V7K
4 21 Z2807 1 1
SW_LAN_TX0- 5 TDCT2 TXCT2 20 NB_LAN_TX0-
<28> SW_LAN_TX0- TD2+ 1:1 TX2+
C320
C321
0.47U_0603_10V7K
0.47U_0603_10V7K
1 1
2 2 +3.3V_LAN:20mils
SW_LAN_TX0+ 6 19 NB_LAN_TX0+
C324
C323
<28> SW_LAN_TX0+ TD2- TX2-

2 2 JLOM1 CONN@
a.
R274
1 2 LAN_ACTLED_YEL_R# 10
<28> LAN_ACTLED_YEL# Yellow LED-
150_0402_5%
SW_LAN_TX3- 7 1:1 18 NB_LAN_TX3- 9
<28> SW_LAN_TX3- TD3+ TX3+ Yellow LED+
NB_LAN_TX3- 8
PR4-
SW_LAN_TX3+ 8 NB_LAN_TX3+ 7
si
<28> SW_LAN_TX3+ TD3- 17 PR4+
NB_LAN_TX3+
TX3- NB_LAN_TX1- 6
PR2-
9 16 Z2806 NB_LAN_TX2- 5
TDCT3 TXCT3 PR3-
NB_LAN_TX2+ 4
10 15 Z2808 PR3+
SW_LAN_TX2- 11 TDCT4 1:1 TXCT4 14 NB_LAN_TX2- NB_LAN_TX1+ 3
<28> SW_LAN_TX2- TD4+ TX4+ PR2+
75_0402_1%
75_0402_1%
75_0402_1%
75_0402_1%
ne
0.47U_0603_10V7K
0.47U_0603_10V7K
1 1 NB_LAN_TX0- 2
PR1- 15
GND
C325
C326
NB_LAN_TX0+ 1
C SW_LAN_TX2+ 12 13 NB_LAN_TX2+ PR1+ 14 C
2 2 <28> SW_LAN_TX2+ TD4- TX4- 1 2 LED_10_GRN_R# 11 GND
<28> LED_10_GRN# Green LED-
R275 150_0402_5%
1 2 LED_100_ORG_R# 13
<28> LED_100_ORG# Orange LED-
1
TAIMA_IH-115-F R276 150_0402_5%
do
12
Green-Orange LED+
rev1
SANTA_130456-341
R277 2
R278 2
R279 2
R280 2
Symbol update OK
In
GND 1 2
150P_1808_2.5KV8J
+GND_CHASSIS
EMC@C327
EMC@ C327
CHASSIS use 40mil trace if necessary
i-
L55 EMC@
4 3 USB3RN1_D- D34 EMC@ +USB_SIDE_PWR
<11> USB3RN1 4 3 USB3RN1_D- 1 9 USB3RN1_D-
1 2 USB3RP1_D+ USB3RP1_D+ 2 8 USB3RP1_D+ JUSB3 CONN@

<11> USB3RP1 1 2 1
DLW21SN900HQ2L-0805_4P USB3TN1_D- 4 7 USB3TN1_D- USBP1_R_D- 2 VBUS
D-
150U_B2_6.3VM_R35M
0.1U_0402_25V6
USBP1_R_D+ 3
1
@ R484
2
0_0402_5%
is USB3TP1_D+ 5 6 USB3TP1_D+ 1
1 USB3RN1_D-
4
5
D+
GND
StdA-SSRX-
B 1 2 + USB3RP1_D+ 6 10 B
StdA-SSRX+ GND
3
C444
C445
@ R485 0_0402_5% 7 11
GND-DRAIN GND
EMC@D33
EMC@
3 USB3TN1_D- 8 12
2 2 USB3TP1_D+ 9 StdA-SSTX- GND 13
TVWDF1004AD0_DFN9 StdA-SSTX+ GND
D33
TAITW_PUBAUE-09FLBS1FF4H0
kn
L56 EMC@
1
<11> USB3TN1 2 1 USB3TN1_RP_C 4 3 USB3TN1_D- ST change to PUBAUE-09FLBS1FF4H0
C448 0.1U_0402_10V7K 4 3
<11> USB3TP1 2 1 USB3TP1_RP_C 1 2 USB3TP1_D+

C449 0.1U_0402_10V7K 1 2
Te
DLW21SN900HQ2L-0805_4P
L54 EMC@
1 2 1 2 USBP1_R_D+
<11> USBP1+ 1 2
@R486
@ R486 0_0402_5%
1 2
@R487
@ R487 0_0402_5% 4 3 USBP1_R_D- +USB_SIDE_PWR
<11> USBP1- 4 3
+5V_ALW U52
w.
DLW21HN900SQ2L_4P 1 8
1 2 2 GND VOUT 7
CONN@ @ R482 0_0402_5% 3 VIN VOUT 6
JSF1 1 2 4 VIN VOUT 5
<36> USB_SIDE_EN# EN FLG USB_OC1# <11>
10U_0603_10V6M
0.1U_0402_25V6
1 @ R483 0_0402_5%
2 1 G547I2P81U_MSOP8
2 1 1
3
<36> WIRELESS_ON#/OFF 3
C446
C447
4
4
ww
A 2 2 A
5
GND1 6
GND2
ACES_50277-0040N-001
RJ45 and USBx1
To Sniffer Board BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Size Document Number
LA-9431P
Rev
0.3

5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
1 2 ALS_INT#
R281 10K_0402_5%
1 2 HW_GPS_DISABLE2#
R282 100K_0402_5% +3.3V_ALW +3.3V_ALW_U37
PJP6
1 2 CPU_DETECT# 1 2
R284 100K_0402_5% 1 1 1 1 1 1
1 2 SLICE_BAT_PRES#
R285 100K_0402_5% C328 PAD-OPEN1x1m C329 C330 C334 C331 C332
10U_0603_6.3V6M 0.1U_0402_25V6 0.1U_0402_25V6 0.1U_0402_10V7K 0.1U_0402_25V6 0.1U_0402_25V6
m
2 2 2 2 2 2
D 1 2 USB_PWR_SHR_EN# D
R287 100K_0402_5%
A17
B30
A43
A54
1 2 USB_SIDE_EN#
B5
co
R288 10K_0402_5% U37
1 2 WIGIG60GHZ_DIS#
VCC1
VCC1
VCC1
VCC1
VCC1
R289 100K_0402_5% A23
1 2 USB_PWR_SHR_VBUS_EN B52 GPIOI0 B63 SIO_SLP_A#
<33> DOCKED_LIO_EN A49 GPIOA0 GPIOI1 A60 SIO_SLP_A# <39,44,9> +3.3V_ALW
R291 100K_0402_5%
1 2 DOCK_SMB_ALERT# MCARD_MISC_PWREN B53 GPIOA1 GPIOI2/TACH0 A61
@ T97 PAD~D GPIOA2 GPIOI3 SIO_SLP_S4# <39,43,9>
R292 100K_0402_5% PROCHOT_GATE A50 B65 RP11
<47> PROCHOT_GATE GPIOA3 GPIOI4 SIO_SLP_S3# <39,43,9>
1 2 WIRELESS_ON#/OFF LID_CL_SIO# B54 A62
DOCK_SMB_ALERT# A51 GPIOA4 GPIOI5 B66 IMVP_PWRGD <46> PROCHOT_GATE 8 1
R293 100K_0402_5%
a.
1 2 ESATA_USB_PWR_EN# <34,41,48> DOCK_SMB_ALERT# TOUCH_SCREEN_PD# B55 GPIOA5 GPIOI6 A63 IMVP_VR_ON <46> XFR_ID_BIT# 7 2
@ T98 PAD~D GPIOA6 GPIOI7 DOCK_AC_OFF_EC <48>
R295 100K_0402_5% A52 WWAN_RADIO_DIS# 6 3
1 2 BT_RADIO_DIS# GPIOA7 B67 AUX_EN_WOWL SUS_ON 5 4
R298 100K_0402_5% USB_SIDE_EN# A33 GPIOJ0 A64 AUX_EN_WOWL <31>
<35> USB_SIDE_EN# EN_I2S_NB_CODEC# B36 GPIOB0 GPIOJ1/TACH1 A5 SIO_SLP_LAN# WLAN_LAN_DISB# <28>
100K_0804_8P4R_5%
<26> EN_I2S_NB_CODEC# USH_PWR_STATE# A34 GPIOB1 GPIOJ2/TACH2 B6 SIO_SLP_SUS# SIO_SLP_LAN# <28,9>
<29> USH_PWR_STATE# B37 GPOC2 GPIOJ3 A6 SIO_SLP_SUS# <9>
<48> EN_DOCK_PWR_BAR EN_DOCK_PWR_BAR
PANEL_BKEN_EC A35 GPOC3 GPIOJ4 B7 MODC_EN GPIO_PSID_SELECT <41>
PAD~D T101 @
si
<22> PANEL_BKEN_EC B38 GPOC4 GPIOJ5 A7
ENVDD_PCH DOCK_HP_DET
<10,22> ENVDD_PCH LCD_TST A36 GPOC5 GPIOJ6 B8 DOCK_MIC_DET DOCK_HP_DET <26>
<22> LCD_TST PSID_DISABLE# A37 GPOC6/TACH4 GPIOJ7 DOCK_MIC_DET <26>
<41> PSID_DISABLE# PBAT_PRES# B40 GPIOC7 A8 ME_FWP
<41,48> PBAT_PRES# GPIOD0 GPIOK0 ME_FWP <6>
DOCKED A38 B9 MASK_SATA_LED#
<21,27,28,32> DOCKED B41 GPIOC1 GPIOK1/TACH3 B10 MASK_SATA_LED# <40>
+3.3V_RUN DOCK_DET# USB_PWR_SHR_EN#
<34,48> DOCK_DET# AUD_NB_MUTE# A39 GPIOC0 GPIOK2 A10 LED_SATA_DIAG_OUT# USB_PWR_SHR_EN# <33> +3.3V_RUN
<26> AUD_NB_MUTE# MCARD_WWAN_PWREN B42 GPIOB7 GPIOK3 B11 LED_SATA_DIAG_OUT# <40>
<28> MCARD_WWAN_PWREN GPIOB6 GPIOK4
ne
LCD_VCC_TEST_EN A40 A11 RUN_ON
<22> LCD_VCC_TEST_EN B43 GPIOB5 GPIOK5 B12 RUN_ON <26,37,39>
CCD_OFF
<22> CCD_OFF AUD_HP_NB_SENSE A41 GPIOB4 GPIOK6 A12 AC_DIS <41,48>
<25,26> AUD_HP_NB_SENSE ESATA_USB_PWR_EN# B44 GPIOB3 GPIOK7 SPI_WP#_SEL <7> D_CLKRUN# 2 1
C 1 2 SP_TPM_LPC_EN <33> ESATA_USB_PWR_EN# GPIOB2 B60 SUS_ON C
R299 100K_0402_5%
GPIOL0/PWM7 A57 SUS_ON <39,43> D_SERIRQ 2 1
@ R304 10K_0402_5%
MODULE_ON B32 GPIOL1/PWM8 B64 BAT1_LED# R300 100K_0402_5%
@ T106 PAD~D
A31 GPIOD1 GPIOL2/PWM0 B68 BAT1_LED# <40>trace width 20 mils 2 1
<48> SLICE_BAT_ON SLICE_BAT_ON D_DLDRQ1#
SLICE_BAT_PRES# B33 GPIOD2 GPIOL3/PWM1 A9 BAT2_LED# R301 100K_0402_5%
do
<34,41,48> SLICE_BAT_PRES# MODULE_BATT_PRES# B15 GPIOD3 GPIOL4/PWM3 B1 BAT2_LED# <40>trace width 20 mils LPC_LDRQ1# 2 1
@ T107 PAD~D GPIOD4 GPIOL5/PWM2
A15 A18 R296 10K_0402_5%
B16 GPIOD5 GPIOL6 A44 USH_PWR_ON <39>
CHARGE_PBATT FP_POA_EN
@ T110 PAD~D GPIOD6 GPIOL7/PWM5 PAD~D T100 @
A16
GPIOD7 B34 HW_GPS_DISABLE2#
GPIOM1 B39 BREATH_LED# HW_GPS_DISABLE2# <31> RUN_ON 2 1
A1 GPIOM3/PWM4 B51 BREATH_LED# <34,40>
WIGIG60GHZ_DIS# R303 100K_0402_5%
<31> WIGIG60GHZ_DIS# B2 GPIOE0/RXD GPIOM4/PWM6 DIS_BAT_PROCHOT# <48> 2 1
CPU_VTT_ON
<31,37> EC5048_TX GPIOE1/TXD
In
A2 R305 100K_0402_5%
mCARD_PCIE_SATA# B3 GPIOE2/RTS# A27 LPC_LAD0
<6> mCARD_PCIE_SATA# CPU_DETECT# A3 GPIOE3/DSR# LAD0 A26 LPC_LAD1 LPC_LAD0 <25,29,37,7>
<9> CPU_DETECT# B45 GPIOE4/CTS# LAD1 B26 LPC_LAD1 <25,29,37,7> 2 1
XFR_ID_BIT# LPC_LAD2 SLICE_BAT_ON
A42 GPIOE5/DTR# LAD2 B25 LPC_LAD2 <25,29,37,7>
LPC_LAD3 R307 100K_0402_5%
B4 GPIOE6/RI# LAD3 A21 LPC_LAD3 <25,29,37,7>
DP_HDMI_HPD LPC_LFRAME#
@ T115 PAD~D GPIOE7/DCD# LFRAME# LPC_LFRAME# <25,29,37,7>
1 2 LCD_TST B22 PCH_PLTRST#_EC
LRESET# A28 CLK_PCI_5048 PCH_PLTRST#_EC <25,29,31,37,9>
R309 100K_0402_5%
1 2 A59 PCICLK B20 CLK_PCI_5048 <7>
SYS_LED_MASK# CLKRUN#
i-
BCM5882_ALERT# B62 GPIOF0 CLKRUN# CLKRUN# <10,29,37,9>
R310 10K_0402_5%
1 2 <29> BCM5882_ALERT# A58 GPIOF1 A22
CHARGE_EN LPC_LDRQ1#
<12,9> SUSACK# EDID_SELECT# B61 GPIOF2 LDRQ1# B21 IRQ_SERIRQ
R313 100K_0402_5% @ T118 PAD~D
A56 GPIOF3/TACH8 SER_IRQ A32 IRQ_SERIRQ <12,29,37>
VGA_ID B59 GPIOF4/TACH7 14.318MHZ/GPIOM0 B35
GPIOF5 CLK32/GPIOM2 EC_32KHZ_ECE5048 <37>
A55
SLP_ME_CSW_DEV# B58 GPIOF6
<12> SLP_ME_CSW_DEV# GPIOF7 B29 D_LAD0
<28> LAN_DISABLE#_R
LAN_DISABLE#_R B47
GPIOG0/TACH5
is DLAD0
DLAD1
DLAD2
B28
A25
D_LAD1
D_LAD2
D_LAD0
D_LAD1
<34>
<34>
B CHARGE_EN A45 A24 D_LAD3 D_LAD2 <34> B
SYS_LED_MASK# B48 GPIOG1 DLAD3 B23 D_LFRAME# D_LAD3 <34>
<40> SYS_LED_MASK# GPIOG2 DLFRAME# D_LFRAME# <34>
ALS_INT# A46 A19 D_CLKRUN#
B49 GPIOG3 DCLKRUN# B24 D_DLDRQ1# D_CLKRUN# <34>
<12,9> SIO_EXT_WAKE# GPIOG4 DLDRQ1# D_DLDRQ1# <34>
WIRELESS_LED# A47 A20 D_SERIRQ
<31,40> WIRELESS_LED# USB_PWR_SHR_VBUS_EN B50 GPIOG5 DSER_IRQ D_SERIRQ <34>
<33> USB_PWR_SHR_VBUS_EN WLAN_RADIO_DIS# A48 GPIOG6
kn
<31> WLAN_RADIO_DIS# GPIOG7/TACH6 A29 BC_INT#_ECE5048

BC_INT# B31 BC_DAT_ECE5048 BC_INT#_ECE5048 <37>
B13 BC_DAT A30 BC_DAT_ECE5048 <37>
WIRELESS_ON#/OFF BC_CLK_ECE5048
<35> WIRELESS_ON#/OFF BT_RADIO_DIS# A13 GPIOH0 BC_CLK BC_CLK_ECE5048 <37>
<31> BT_RADIO_DIS# A53 GPIOH1
WWAN_RADIO_DIS#
<31> WWAN_RADIO_DIS# SYS_PWROK B57 SYSOPT1/GPIOH2 A4 RUNPWROK
<9> SYS_PWROK DGPU_SELECT# B14 SYSOPT0/GPIOH3 PWRGD RUNPWROK <37,9>
@ T121 PAD~D GPIOH4
A14 B56 SP_TPM_LPC_EN
Te
<9> SIO_SLP_WLAN# CPU_VTT_ON B17 GPIOH5 OUT65 SP_TPM_LPC_EN <29>

+3.3V_ALW
1 2 B18 GPIOH6
<9> PCH_DPWROK GPIOH7 B19 1 2
@ R319 0_0402_5%
TEST_PIN R321 1K_0402_5% +CAP_LDO trace width 20 mils
1
B46 +CAP_LDO
CAP_LDO CLK_PCI_5048 R322
1
B27 100K_0402_5%
VSS C1 C336
EP
1
w.
4.7U_0603_6.3V6K
2
DB Version 0.4 2 @ R324
+3.3V_ALW ECE5048-LZY_DQFN132_11X11~D 33_0402_5% LID_CL_SIO# 2 1
LID_CL# <31,40>
R325 10_0402_1%
100K_0402_5%
2
2
R317
1 C337
ME_FWP PCH has internal 20K PD. @ C339 0.047U_0402_16V4Z
33P_0402_50V8J 2
ww
A (suspend power rail) A

1
ME_FWP 2
VGA_ID
1
100K_0402_5%
@ R326
@R326
2
1K_0402_5%
@ R320
VGA_ID0
2
Discrete 0 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
1
UMA 1 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SIO & GPIO ECE5048
LA-9431P
5 4 3 2 1
5 4 3 2 1
+RTC_CELL
+RTC_CELL +RTC_CELL
1 2 +RTC_CELL_VBAT
100K_0402_5%
100K_0402_5%
@ R332 0_0402_5%
1
0.1U_0402_25V6
R327
R328
@ C340 @ C342
1 1 2 1 2
C345
1U_0402_6.3V6K 1U_0402_6.3V6K
2
2 POWER_SW_IN# 1 2 DOCK_PWR_SW# 1 2
POWER_SW#_MB <40,9> DOCK_PWR_BTN# <34>
R329 10K_0402_5% R330 10K_0402_5%
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1
1 2 +3.3V_VTR
+3.3V_ALW_U38
C343
C344
@ R336 0_0402_5%
0.1U_0402_25V6
1U_0402_6.3V4Z
2 2
1 1
C346
+1.05V_RUN
C352
2 2
10K_0402_5%
1 2
1
@ R335
@ R334 0_0402_5%
m
U38
D D
1 2 +3.3V_VTR_ADC B64 A10 SYSTEM_ID
+3.3V_ALW_U38 VBAT GPIO021/RC_ID1 H_PROCHOT# <46,47,48,9>
@ R490 0_0402_5% B10 BOARD_ID
2
GPIO020/RC_ID2
0.1U_0402_25V6
1U_0402_6.3V4Z
B8 VOL_UP_R R338 1 2 10K_0402_5%
GPIO014/GPTP-IN7/RC_ID3 VOL_UP <40>
1
A22 B27 LAN_WAKE# D
1 1 H_VTR GPIO025/UART_CLK LAN_WAKE# <12,28>
co
B44 HOST_DEBUG_TX PROCHOT#_EC 2 Q9 @
GPIO120/UART_TX HOST_DEBUG_TX <31>
C353
C347
+3.3V_ALW B46 HOST_DEBUG_RX G L2N7002WT1G_SC-70-3
A58 GPIO124/GPTP-OUT5/UART_RX B26 RUNPWROK S
3
2 2 VTR_ADC VCC_PWRGD RUNPWROK <36,9>
100K_0402_5%
A25 EN_INVPWR
GPIO060/KBRST/BCM_B_INT# EN_INVPWR <22>
2
1 2 PCIE_WAKE# B36 PCH_SATA_MOD_EN#
GPIO101/ECGP_SCLK/GANG_DATA5 PAD~D T123 @
@ R342
R340 10K_0402_5% B3 B37
1 2 BC_DAT_ECE5048 A11 VTR GPIO103/ECGP_MISO/GANG_DATA7 B38 PCIE_WAKE# SLICE_PERF_EN <48>
+3.3V_ALW +3.3V_ALW_U38 A26 VTR GPIO105/ECGP_MOSI A34 PCIE_WAKE# <31>
R343 100K_0402_5% DDR_HVREF_RST_GATE
1 2 BC_DAT_ECE1117 B35 VTR GPIO102/BCM_C_INT#/GANG_DATA6 A35
PJP7
1
R344 100K_0402_5% A41 VTR GPIO104 A36 DYN_TUR_CURRNT_SET# <47>
1 2 1 2 A52 VTR GPIO106 A40 SIO_SLP_S0# <9>
PBAT_SMBDAT MSDATA +RTC_CELL
VTR GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP B43 MSDATA <31>
R345 2.2K_0402_5% MSCLK
GPIO117/MSCLK/V2P_COUT_HI MSCLK <31>
10U_0603_6.3V6M
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1 2 PBAT_SMBCLK PAD-OPEN1x1m A45 POA_WAKE# 2 1
R339 2.2K_0402_5% GPIO127/A20M B65 FWP# 100K_0402_5% R346
1 1 1 1 1 1 1
a.
1 2 CHARGER_SMBDAT @ SML1_SMBDATA A5 NFWP VCI_IN2# 2 1
<7> SML1_SMBDATA GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA/GANG_BUSY
C349
C354
C350
C355
C356
C351
C348
R348 10K_0402_5% SML1_SMBCLK B6 100K_0402_5% R347
1 2 <7> SML1_SMBCLK A37 GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_ERROR B57
CHARGER_SMBCLK CLK_TP_SIO VOL_DOWN_R R349 1 2 10K_0402_5%
2 2 2 2 2 2 2 <38> CLK_TP_SIO B40 GPIO110/PS2_CLK2/GPTP-IN6 GPIO156/LED0 B1 VOL_DOWN <40>
R350 10K_0402_5% DAT_TP_SIO DEVICE_DET# +3.3V_ALW
<38> DAT_TP_SIO A38 GPIO111/PS2_DAT2/GPTP-OUT6 GPIO157/LED1 A55
+5V_RUN change to 10K by vendor feedback CLK_KBD PS_ID
<34> CLK_KBD B41 GPIO112/PS2_CLK1A GPIO153/LED2 A1 PS_ID <41>
DAT_KBD ALW_PWRGD_3V_5V
1 2 <34> DAT_KBD A39 GPIO113/PS2_DAT1A GPIO027/GPTP-OUT1 B28 ALW_PWRGD_3V_5V <42> 2 1
CLK_KBD CLK_MSE 1.05V_A_PWRGD DOCK_SMB_DAT
<34> CLK_MSE B42 GPIO114/PS2_CLK0A GPIO026/GPTP-IN1 B2 1.05V_A_PWRGD <44>
R354 4.7K_0402_5% DAT_MSE VOL_MUTE_R R352 1 2 10K_0402_5% 2.2K_0402_5% R359
1 2 <34> DAT_MSE B59 GPIO115/PS2_DAT0A GPIO001/ECSPI_CS1 A8 VOL_MUTE <40> 2 1
DAT_KBD PBAT_SMBDAT DOCK_SMB_CLK
<41> PBAT_SMBDAT A56 GPIO154/I2C1C_DATA/PS2_CLK1B GPIO015/GPTP-OUT7/GANG_DATA3 B9 ME_SUS_PWR_ACK <9>
R355 4.7K_0402_5% PBAT_SMBCLK 1.35V_SUS_PWRGD 2.2K_0402_5% R361
1 2 <41> PBAT_SMBCLK GPIO155/I2C1C_CLK/PS2_DAT1B GPIO016/GPTP-IN8/GANG_DATA4 A9 1.35V_SUS_PWRGD <43> 2 1
CLK_MSE PM_APWROK DYN_TUR_CURRNT_SET#
A51 GPIO017/GPTP-OUT8 B39 PM_APWROK <9>
R356 4.7K_0402_5% JTAG_TDI RESET_OUT# 100K_0402_5% R363
1 2 B55 GPIO145/I2C1K_DATA/JTAG_TDI GPIO107/NRESET_OUT A44 RESET_OUT# <15,9> 2 1
DAT_MSE JTAG_TDO PCH_PCIE_WAKE# LCD_SMBDAT
R357 4.7K_0402_5% JTAG_CLK B56 GPIO146/I2C1K_CLK/JTAG_TDO GPIO125/GPTP-IN5 B47 PCH_RSMRST# PCH_PCIE_WAKE# <9> 2.2K_0402_5% R451
si
A53 GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK GPIO126 A54 PCH_RSMRST# <38> 2 1
JTAG_TMS AC_PRESENT LCD_SMBCLK
+3.3V_RUN A57 GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS GPIO151/GPTP-IN4 B58 AC_PRESENT <12,9>
JTAG_RST# SIO_PWRBTN# 2.2K_0402_5% R387
JTAG_RST# GPIO152/GPTP-OUT4 SIO_PWRBTN# <9> 2 1
BAY_SMBDAT
1 2 VOL_MUTE FAN1_TACH B22 A3 DOCK_SMB_DAT 2.2K_0402_5% R453
A21 GPIO050/FAN_TACH1/GTACH GPIO003/I2C1A_DATA/GANG_MODE B4 DOCK_SMB_DAT <34> 2 1
@ R358 100K_0402_5% DOCK_SMB_CLK BAY_SMBCLK
1 2 <34> DOCK_POR_RST# B23 GPIO051/FAN_TACH2 GPIO004/I2C1A_CLK/GANG_START A4 DOCK_SMB_CLK <34>
VOL_DOWN LCD_SMBDAT 2.2K_0402_5% R452
<12> EC_WAKE# B24 GPIO052/FAN_TACH3 GPIO005/I2C1B_DATA/BCM_B_DAT/GANG_STROBE B5 2 1
@ R360 100K_0402_5% A_ON LCD_SMBCLK DDR_HVREF_RST_GATE
1 2 <39,44> A_ON A23 GPIO053/PWM0 GPIO006/I2C1B_CLK/BCM_B_CLK/GANG_FULL B7
VOL_UP PCH_ALW_ON BAY_SMBDAT 100K_0402_5% R353
<39> PCH_ALW_ON B25 GPIO054/PWM1 GPIO012/I2C1H_DATA/I2C2D_DATA/GANG_DATA1 A7 2 1
@ R362 100K_0402_5% <22> BIA_PWM_EC BIA_PWM_EC BAY_SMBCLK THERMATRIP3#
1 2 FAN1_PWM FAN1_PWM A24 GPIO055/PWM2 GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA2 B48 GPU_SMBDAT 100K_0402_5% R364
R408 10K_0402_5% GPIO056/PWM3/GPWM GPIO130/I2C2A_DATA/BCM_C_DAT B49 GPU_SMBCLK DEVICE_DET# 2 1
1 2 FAN1_TACH GPIO131/I2C2A_CLK/BCM_C_CLK A47 CHARGER_SMBDAT 100K_0402_5% R365
GPIO132/I2C1G_DATA B50 CHARGER_SMBDAT <47> 2 1
R376 10K_0402_5% CHARGER_SMBCLK HOST_DEBUG_RX
GPIO140/I2C1G_CLK CHARGER_SMBCLK <47>
ne
BC_CLK_ECE5048 A43 B52 CARD_SMBDAT 10K_0402_5% R401
<36> BC_CLK_ECE5048 BC_DAT_ECE5048 B45 GPIO123/BCM_A_CLK GPIO141/I2C1F_DATA/I2C2B_DATA A49 CARD_SMBCLK
<36> BC_DAT_ECE5048 A42 GPIO122/BCM_A_DAT GPIO142/I2C1F_CLK/I2C2B_CLK B53
BC_INT#_ECE5048 USH_SMBDAT RP3
<36> BC_INT#_ECE5048 B20 GPIO121/BCM_A_INT# GPIO143/I2C1E_DATA A50 USH_SMBDAT <29> 8 1
ACAV_IN_NB USH_SMBCLK CARD_SMBDAT
<47,48> ACAV_IN_NB A18 GPIO032/BCM_E_CLK GPIO144/I2C1E_CLK USH_SMBCLK <29> 7 2
SIO_SLP_S5# GPU_SMBDAT
<9> SIO_SLP_S5# BEEP B19 GPIO031/GPTP-OUT2/BCM_E_DAT A59 1 2 GPU_SMBCLK 6 3
<26> BEEP GPIO030/GPTP-IN2/BCM_E_INT# SYSPWR_PRES +3.3V_ALW2
100K_0402_5%
C BC_CLK_ECE1117 A20 R367 1K_0402_5% CARD_SMBCLK 5 4 C
<38> BC_CLK_ECE1117 GPIO047/LSBCM_D_CLK
1
1 2 MSDATA BC_DAT_ECE1117 B21 A64 ACAV_IN
<38> BC_DAT_ECE1117 GPIO046/LSBCM_D_DAT VCI_OVRD_IN ACAV_IN <47,48>
R366 10K_0402_5% BC_INT#_ECE1117 A19 A60 ALWON 2.2K_0804_8P4R_5%
1 2 <38> BC_INT#_ECE1117 GPIO045/LSBCM_D_INT# VCI_OUT B67 ALWON <42>
PCH_ALW_ON POWER_SW_IN#
VCI_IN0#
R370
R368 100K_0402_5% SIO_EXT_SMI# A6 A63 DOCK_PWR_SW#
1 2 <12> SIO_EXT_SMI# A27 GPIO011/nSMI/GANG_DATA0 VCI_IN1# B63
DOCK_POR_RST# SIO_RCIN# VCI_IN2#
2
R369 100K_0402_5% <12> SIO_RCIN# IRQ_SERIRQ A28 GPIO061/LPCPD# VCI_IN2# B68 POA_WAKE#
1 2 EN_INVPWR <12,29,36> IRQ_SERIRQ PCH_PLTRST#_EC B30 SER_IRQ VCI_IN3#
R866 close to U51 at least 250mils
do
<25,29,31,36,9> PCH_PLTRST#_EC A29 LRESET# B51 1 2
R371 100K_0402_5% CLK_PCI_MEC +PECI_VREF +1.05V_RUN
1 2 <7> CLK_PCI_MEC B31 PCI_CLK VREF_PECI A48 1 2
A_ON LPC_LFRAME# PECI_EC_R @ R374 0_0402_5%
<25,29,36,7> LPC_LFRAME# LFRAME# PECI_DAT PECI_EC <9>
0.1U_0402_25V6
R372 100K_0402_5% LPC_LAD0 A30 R375 43_0402_5% 1
1 2 <25,29,36,7> LPC_LAD0 B32 LAD0
RESET_OUT# LPC_LAD1
<25,29,36,7> LPC_LAD1 LAD1
C360
@ R373 8.2K_0402_5% LPC_LAD2 A31 B13 REM_DIODE1_N C358 1 2 2200P_0402_50V7K
1 2 <25,29,36,7> LPC_LAD2 B33 LAD2 DN1-THERM A13
PCH_RSMRST# LPC_LAD3 REM_DIODE1_P
<25,29,36,7> LPC_LAD3 A32 LAD3 DP1-VREF_T B14 2
R377 10K_0402_5% CLKRUN# REM_DIODE2_N C359 1 2 2200P_0402_50V7K
<10,29,36,9> CLKRUN# A33 CLKRUN# DN2 A14
SIO_EXT_SCI# REM_DIODE2_P
<12> SIO_EXT_SCI# GPIO100/NEC_SCI DP2 A15
MEC_XTAL1 A61 DN3 B16
MEC_XTAL2 2 1 MEC_XTAL2_R A62 XTAL1 DP3 A16 REM_DIODE4_N C361 1 2 2200P_0402_50V7K
@ R378 1 2 0_0402_5% B62 XTAL2 DN4 B17 REM_DIODE4_P
<36> EC_32KHZ_ECE5048 GPIO160/32KHZ_OUT DP4 B15
@ R379 0_0402_5% C283, C285, C286, C287 Place near U51
VIN
In
A17 VSET_5075
1 2 VOL_UP_R VSET A12
VCP VCP <47>
EMC@ C455 0.1U_0402_25V6 B34 THERMATRIP2#
THERMTRIP2# A2 THERMATRIP3#
1 2 VOL_DOWN_R GPIO002/THERMTRIP3# B29 THSEL_STRAP
VSS_ADC
GPIO024/THSEL_STRAP
VSS_RO
VR_CAP
EMC@ C456 0.1U_0402_25V6 A46 PROCHOT#_EC
H_VSS
PROCHOT_IN#/PROCHOT_IO#
AGND
B61 1 2
V_SYS <47>
VSS
1 2 VOL_MUTE_R V_ISYS R381 4.7K_0402_5%
EP
EMC@ C457 0.1U_0402_25V6
MEC5075-LZY_DQFN132_11X11~D
B66
B11
B60
+VR_CAP B12
B54
B18
C1
ESD Request 15mil XB use SA00005IH1L(S IC MEC5075-LZY-SAL00 DQFN 132P EC)
i- 4.7U_0603_6.3V6K
32 KHz Clock 1
C366
2
MEC_XTAL1 1 2 MEC_XTAL2
ESR <2ohms
22P_0402_50V8J
22P_0402_50V8J
Y4
+3.3V_ALW 1 32.768KHZ_12.5PF_Q13FC1350000~D 1
5075 Setting for Thermal Design

C364
C365
2 2
is
100K_0402_5%
1
R380
B B
CONN@ Align E5,P5 Fan module pin define
JFAN1
then swap pin define
2
6
Thermal diode mapping 5 GND2
JTAG_RST# GND1
CLK_PCI_MEC
DOCK_POR_RST# +3.3V_RUN 5075 Channel Location 4
4
1
1
10_0402_1%
3 FAN1_PWM
3
1U_0402_6.3V6K
@ R382
10K_0402_5%
2 FAN1_TACH
DP1/DN1 CPU
1
2
kn
1
1
JTAG1 CONN@
@SHORT PADS~D
100_0402_1%
1 1
1 +5V_RUN
0.1U_0402_25V6
R35
@
+3.3V_ALW
C362
R384
22U_0805_6.3V6M
RB751V40_SC76-2
ACES_50277-0040N-001
1 DP2/DN2 DIMM
2
1
4.7P_0402_50V8C
C357
1 @
2
C7
D1
2
2
100K_0402_5%
1 2 DP4/DN4 V.R
1
2
RUNPWROK
2
@ C363
R36
2
2
+3.3V_ALW
2
Place under CPU
2
Place C266 close to the Q11 as possible
8.2K_0402_5%
Place close pin A21
1
R402
RUN_ON# 5 REM_DIODE1_P
D
Place close pin A29

G
Q5A
100P_0402_50V8J
Te
@ C370
EMI depop location(EMC) 2
4
1
C
6
2 Q11
2
Q5B
2
D
G B
<26,36,39> RUN_ON 1 E
S MMBT3904WT1G_SC70-3~D
3
THERMATRIP2#
1
+3.3V_ALW REM_DIODE1_N
+1.05V_RUN
0.1U_0402_25V6
1
C
DP2/DN2 for SODIMM on Q13, place Q13 close 1 2 2 Q12 1
to SODIMM and C372 close to Q13
C371
R403 2.2K_0402_5% B MMST3904-7-F_SOT323-3
E
RP1
3
w.
REM_DIODE2_P
1 8 JTAG_TDI driven low when +3.3V_RUN is OFF; 2
100P_0402_50V8J
2 7 JTAG_CLK
driven high when +3.3V_RUN is ON 1
1
@ C372
3 6 MSCLK C
4 5 HOST_DEBUG_TX 2 Q13
<12> H_THERMTRIP#
B
2 E MMBT3904WT1G_SC70-3~D
3
10K_8P4R_5%
REM_DIODE2_N VSET_5075
0.1U_0402_25V6
1.58K_0402_1%
1
+3.3V_ALW
DP4/DN4 for Skin on Q14, place Q14 close to Vcore VR choke.
H=0.98 1
R394
THSEL_STRAP 1 2
R392 C368 REV
ww
C367
+3.3V_ALW +3.3V_ALW +3.3V_ALW REM_DIODE4_P R383 1K_0402_5%
A A
100P_0402_50V8J
240K 4700p X00 2

10K_0402_5%
49.9_0402_1%
10K_0402_5%
CONN@
2
1
+3.3V_ALW
1K_0402_5%
1K_0402_5%
10K_0402_5%
JDEG1
130K 4700p X01
1
1
R388
R385
R391
@C373
@
2 C
C373
R386
R393
12 2 Q14
GND2 62K 4700p *** 1: Channel 1 will provide Thermistor Readings
R392
11 B
GND1
1
1
10K_0402_5%
100K_0402_5%
E MMBT3904WT1G_SC70-3~D
33K 4700p X02 0: Channel 1 will provide Diode Readings
2
1
@ R398
2
R397
10 REM_DIODE4_N
10 8.2K 4700p *** Rest=1.58K , Tp=96 degree
4700P_0402_25V7K
9 JTAG_TDI BOARD_ID SYSTEM_ID FWP#

9 8 JTAG_TMS
4.3K 4700p ***
2
8
4700P_0402_25V7K
7 JTAG_CLK 1
7
2
10K_0402_5%
6 JTAG_TDO
6 2K 4700p *** 1
C369
5 MSCLK 5048_TX should be change Host_debug_tx

5
C368
@ R399
4 MSDATA
4
3
3 HOST_DEB_TX 1 2 HOST_DEBUG_TX * 1K 4700p A00 2
2 DELL CONFIDENTIAL/PROPRIETARY
2 @ R400 0_0402_5%
EC5048_TX <31,36>
1
2 1
1 Pin8 5075_TXD for EC Debug PROPRIETARY NOTE:
ACES_50521-01041-P01 pin9 5048_TXD for SBIOS debug Title
BOARD_ID rise time is measured from 5%~68%. THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
pin define different with original part
CHIPSET_ID for BID function TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT KBC & SIO MEC5075
0.3
5 4 3 2 1
5 4 3 2 1
+3.3V_TP
Touch Pad CONN@
4.7K_0402_5%
4.7K_0402_5%
JKBTP1
18
GND2 Place close to JKBTP1
1
R404
R405
17
m
KB_DET# 16 GND1
D 1 2 <12,9> KB_DET# 15 16 +3.3V_TP +3.3V_ALW +5V_RUN D
<12> I2C1_SDA_TCH_PAD 14 15
@ R450 0_0402_5%
1 2 13 14
<12> I2C1_SCL_TCH_PAD
2
13
co
@ R449 0_0402_5% 12
+5V_RUN 12
1 2 TP_DATA 11 1 1 1
<37> DAT_TP_SIO +3.3V_ALW 11
@ R441 0_0402_5% 10
1 2 TP_CLK <37> BC_INT#_ECE1117 9 10 @ C374 @ C375 @ C376
<37> CLK_TP_SIO <37> BC_DAT_ECE1117 8 9
@ R444 0_0402_5% 0.1U_0402_25V6 0.1U_0402_25V6 0.1U_0402_25V6
8 2 2 2
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
1 @ 1 7
<37> BC_CLK_ECE1117 7
C377
@ 1 1 6
6
C378
@ @ 5
+3.3V_TP 5
C379
C380
TP_DATA 4
a.
2 2 TP_CLK 3 4
2 2 2 3
1 2
1
E-T_6718K-Y16N-01L
EMI depop location(EMC) EMI depop location(EMC)
si
ST change to 6718K-Y16N-01L
+3.3V_RUN +3.3V_TP
ne
PJP8
1 2
C C
PAD-OPEN1x1m
do
@ eDP Cable (30P Normal)
Part Number Description
DC02001PB00 H-CONN SET 0VM MB-EDP-LED-CAM
@ eDP Cable (40P Touch Screen)
In
DC02001PA00 H-CONN SET 0VM MB-EDP-LED-CAM-TS
@ Sniffer cable
i-
DC02001P900 H-CONN SET 0VM MB-SNIFFER
@ TP_FFC
NBX0001CV00 FFC 16P F P0.5 PAD=0.3 104.4MM MB-KBTP

is
B @ FP FFC B

NBX0001CX00 FFC 6P G P0.5 PAD=0.3 86.4MM USH/B-FP
kn
@ USH FFC
NBX0001CT00 FFC 20P G P0.5 PAD=0.3 33.5MM MB-USH/B
RSMRST circuit @ R414
@R414
0_0402_5%
1 2 @ NFC board _FFC
@ RTC BATT
Part Number Description GC20323MX00 BATT CR2032 3V

+5V_ALW +3.3V_ALW 220MAH MAXELL
Te
+3.3V_ALW
NBX0001CU00 FFC 15P F P0.5 PAD=0.3 56.01MM MB-NFC
@ C386
1
1 2 @ Speak
1
10K_0402_5%
R440
@ Media Board FFC Part Number Description

R411 0.1U_0402_25V6 Part Number
33_0402_5% EC SIDE Description
U41 PK230003Q0L SPK PACK ZJX 2.0W 4 OHM FG
5
U42 NBX0001CS00 FFC 8P G P0.5 PAD=0.3 51.8MM MB-MEDIA/B

2
1
P
<37> PCH_RSMRST#
2
B
w.
+5V_ALW_U41 1 4 1 2 @ Battery bridge cable

VCC O PCH_RSMRST#_Q <9>
.01U_0402_16V7K
3 RSMRST# 2 @ R413 0_0402_5% @ SIM Board FFC + Hall Sensor FFC

RESET# A Part Number Description
G
1 2
GND Part Number Description
TC7SH08FU_SSOP5~D DC020014Z10 H-CONN SET 0FD M/B-BATTERY 9PIN
3
C387
NBX0001CR00 FFC 12P G P0.5 PAD=0.3 73.3MM MB-SIM+HALL/B

RT9818A-44GU3_SC70-3~D
2 @ UMA DC_IN wire cable
change to E4 solution
ww
A A
DC30100BN0 CONN SET 0FD DCJACK-MB WDMD-DCE30004-DF
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, KB/TP/RSMRST
LA-9431P
5 4 3 2 1
5 4 3 2 1
DC/DC Interface
+3.3V_ALW_PCH/+1.05V_RUN source
+3.3V_ALW_PCH
1
PJP14
m
PAD-OPEN1x1m
D D
U43
2
co
1 14 +3.3V_ALW_PCH_U43 1 2
+3.3V_ALW VIN1 VOUT1
2 13 C389 0.1U_0402_10V7K
VIN1 VOUT1
1 2 3 12 1 2
<37> PCH_ALW_ON ON1 CT1
@ R416 0_0402_5% C390 470P_0402_50V7K
SIO_SLP_S3# 1 2 4 11
+1.05V_MODPHY <36,43,9>
<26,36,37>
SIO_SLP_S3#
RUN_ON
RUN_ON
@ R417
1
0_0402_5%
2
+5V_ALW
5
VBIAS
ON2
GND
CT2
10 1 2
@ R418 0_0402_5% C391 470P_0402_50V7K
a.
6 9
+1.05V_M Q125 +1.05V_MODPHY +1.05V_M VIN2 VOUT2
7 8 +1.05V_RUN_U43 2 1
+5V_ALW VIN2 VOUT2 +1.05V_RUN
SI3456DDV-T1-GE3_TSOP6
GPAD
D
6
S
5 4 TPS22966DPUR_SON14_2X3~D C393
1
10K_0402_5%
10U_0603_6.3V6M
2 0.1U_0402_10V7K
1 2
si
1
+3.3V_ALW2
20K_0402_5%
R445
1
C413
3
@R447
2
1
2
100K_0402_5%
2200P_0402_50V7K
1.05V_MODPHY_EN
2
+3.3V_SUS/+3.3V_M source
R442
C412
ne
2
3 +3.3V_SUS
2
Q124A
D
MPHYP_PWR_EN# 5 G
1
C C
4
PJP16
6
Q124B
D PAD-OPEN1x1m
2 G 1 2
1 2 <36> USH_PWR_ON
@ R439 0_0402_5%
do
S
<12> MPHYP_PWR_EN
@ R420 0_0402_5% U45
1
2
1 2 1 14 +3.3V_SUS_U45 1 2
<36,43,9> SIO_SLP_S4# 2 VIN1 VOUT1 13
@ R421 0_0402_5% C396 0.1U_0402_10V7K
VIN1 VOUT1
1 2 3 12 C397 1 2
<36,43> SUS_ON ON1 CT1
@ R422 0_0402_5% 470P_0402_50V7K
4 11
+5V_ALW VBIAS GND
In
1 2 5 10 C398 1 2
<36,44,9> SIO_SLP_A# ON2 CT2
@ R423 0_0402_5% 470P_0402_50V7K
6 9
1 2 7 VIN2 VOUT2 8 +3.3V_M_U45 2 1
<37,44> A_ON +3.3V_ALW VIN2 VOUT2 +3.3V_M
@ R424 0_0402_5%
GPAD
TPS22966DPUR_SON14_2X3~D C399
i-
0.1U_0402_10V7K
2
is +3.3V_RUN/+5V_RUN source
+5V_RUN
B B
1
PJP18
PAD-OPEN1x1m
kn
U46
2
SIO_SLP_S3# 1 2 1 14 +5V_RUN_U46 1 2
+5V_ALW VIN1 VOUT1
@ R425 0_0402_5% 2 13 C400 0.1U_0402_10V7K
VIN1 VOUT1
RUN_ON 1 2 3 12 C401 1 2
@ R426 0_0402_5% ON1 CT1 470P_0402_50V7K
4 11
VBIAS GND
5 10 C402 1 2
Te
ON2 CT2 1000P_0402_50V7K

6 9
+3.3V_ALW VIN2 VOUT2
7 8 +3.3V_RUN_U46 2 1
VIN2 VOUT2 +3.3V_RUN
GPAD
TPS22966DPUR_SON14_2X3~D C403
0.1U_0402_10V7K
2
w.
ww
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, POWER CONTROL
LA-9431P
5 4 3 2 1
5 4 3 2 1
+5V_ALW +5V_ALW
Battery LED
+3.3V_ALW HDD LED solution for White LED
+5V_ALW
1
Q23A
R428 LED7
10K_0402_5% DMN66D0LDW-7_SOT363-6
4 3 BAT2_LED#_Q 1 2 BATT_WHITE# 1 2
<36> BAT2_LED#
D
3
Q24A Q24B R427 150_0402_5% W
2
DMN66D0LDW-7_SOT363-6 Q15
G
D23 DMN66D0LDW-7_SOT363-6 PDTA114EU_SC70-3 BATT_YELLOW# 3 4
5
4 3 1 2 1 6 2 MASK_BASE_LEDS# Y
<6> SATA_ACT#
m
RB751S40T1G_SOD523-2 LTW-295DSKS-5A_YEL-WHITE
G
D D
5
2
1 2
R429 BATT_WHITE_LED# <22>
<36> MASK_SATA_LED#
330_0402_5%
co
D24 LED6
1 2 1 2 SATA_LED 2 1 Q23B
<36> LED_SATA_DIAG_OUT#
MASK_BASE_LEDS# R430 150_0402_5% R431
RB751S40T1G_SOD523-2 LTW-193ZDS5_WHITE DMN66D0LDW-7_SOT363-6 150_0402_5% BATT_YELLOW_LED# <22>
1 6 BAT1_LED#_Q 1 2
<36> BAT1_LED#
D
PANEL_HDD_LED# <22>
G
2
3
Q25A MASK_BASE_LEDS# R433
a.
DMN66D0LDW-7_SOT363-6 Q26 150_0402_5%
PDTA114EU_SC70-3 1 2
4 3 2
D
G
Q28A
Breath LED
5
4 3
D
1 2 +5V_ALW
si
SYS_LED_MASK# R438 220_0402_5%
5
Q28B
DMN66D0LDW-7_SOT363-6 LED1
1 6 BREATH_LED#_Q 1 2 BREATH_WHITE_LED_SNIFF 1 2
<34,36> BREATH_LED#
D
R434 150_0402_5%
LTW-193ZDS5_WHITE
G
Place LED1 close to SW1 LED(white) current need to reach 2mA,
2
+3.3V_ALW
WLAN LED solution for White LED MASK_BASE_LEDS#
need to check current limit resistor
ne
1 2 BREATH_WHITE_LED# <22>
R436 330_0402_5%
+5V_ALW
1
C R432 C
100K_0402_5%
3
Q25B
DMN66D0LDW-7_SOT363-6 Q16
2
PDTA114EU_SC70-3
1 6 2
do
<31,36> WIRELESS_LED#
S
D
G
2
MASK_BASE_LEDS#
1
LED5
1 2 WLAN_LED 2 1
R435 150_0402_5%
LTW-193ZDS5_WHITE
In
+3.3V_ALW
i-
@ C404 0.1U_0402_25V6
1 2
5
U47
SYS_LED_MASK# 1
P
<36> SYS_LED_MASK# B 4 MASK_BASE_LEDS#

2 O MASK_BASE_LEDS# <28>
<31,36> LID_CL# A
G
TC7SH08FU_SSOP5~D
is
3
B B
kn
SW1
2 1 @ JRTC1
<37,9> POWER_SW#_MB 1 3
<31,41> +COINCELL 2 1 G 4
2 G
TYCO_2-1775293-2~D
4 3
SKRBAAE010_4P
Te
POWER & INSTANT ON SWITCH

CONN@
JMEDIA
8
GND2 7
6 GND1
5 6
w.
<37> VOL_UP 4 5
<37> VOL_DOWN 3 4
<37> VOL_MUTE 2 3
1 2
LED Circuit Control Table 1
Fiducial Mark
@ FD1 E-T_6718K-Y06N-01L
1 SYS_LED_MASK# LID_CL#
ww
FIDUCIAL MARK~D
A
@ FD2
Mask All LEDs (Sniffer Function) 0 X ST update symbol to 6718K-Y06N-01L A
1
Mask Base MB LEDs (Lid Closed) 1 0
FIDUCIAL MARK~D
Do not Mask LEDs (Lid Opened) 1 1
@ FD3
1
FIDUCIAL MARK~D
@ FD4
@ H1
H_2P8
@ H2
H_2P8
@ H3
H_2P8
@ H4
H_2P8
@ H5
H_2P3
@ H8 @ H9
H_3P4 H_3P4
@ H10
H_3P4
@ H11
H_3P4
@ H12 @ H13 @ H14 @ H15 @ H16 @ H17 @ H18
H_2P8 H_2P8 H_2P1 H_2P8 H_2P8 H_2P8 H_2P8
@ ST1
CLIP_C5P1
@ ST2
H_2P8
1 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
FIDUCIAL MARK~D BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PAD & ME & LED
1
LA-9431P
5 4 3 2 1
5 4 3 2 1
+COINCELL
COIN RTC Battery
1
PR1
1K_0402_5%~D
+3.3V_RTC_LDO
2
+COINCELL
Z4012
+COINCELL <31,40>
m
D D
2
+RTC_CELL
co
1
1
PD1 PD2
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3 PD3
PL1
1
FBMJ4516HS720NT_2P~D +3.3V_ALW BAS40CW SOT-323 1
1 2 PC1
3
Primary Battery Connector 1U_0603_10V4Z~D
PL2
1
FBMJ4516HS720NT_2P~D 2
a.
PBATT+_C 1 2 +PBATT
PR2
1
LLTOP_ALLTOP C144LS-109A9-L 9P BATT P2 @ PC2
1 0.1U_0603_25V7K~D 100K_0402_5%~D
2
1 2 PRP2
2
2 3 Z4304 8 1
PBAT_SMBCLK <37>
2200P_0402_50V7K~D
3 4 Z4305 7 2
4 5 PBAT_SMBDAT <37>
Z4306 6 3
5 6 PBAT_PRES# <36,48>
1
5 4
PC3
6 7
si
7 8 100_0804_8P4R_5% PQ1
2
8 9 ME2301D-G 1P SOT-23-3
9 10 PD4
GND 11 1 2 1 3
3
GND DOCK_SMB_ALERT# <34,36,48>
@ PBATT1 SDMK0340L-7-F_SOD323-2~D
2
2
@ PR6
ne
GND 1 2
<34,36,48> SLICE_BAT_PRES#
0_0402_5%
1
PC4
C C
1500P_0402_7K~D
2
do
+5V_ALW
In
+3.3V_ALW
2
@ PD5
DA204U_SOT323~D GND
@ PR7 PU111
2
change from 0603 to 0402 size PN: SM010028600 1 2
<34> DOCK_PSID
1
NO IN
6
GPIO_PSID_SELECT <36>
i-
0_0402_5%~D
PR8
1
2 5
PL3 PR9
2.2K_0402_5%~D GND V+ +5V_ALW
1
BLM15AG102SN1D_2P 33_0402_5%~D
NB_PSID 2 1 1 3 1 2 NB_PSID_TS5A63157 3 4
D
S
NC COM PS_ID <37>
PQ2 TS5A63157DCKR_SC70-6~D
2
FDV301N_G_NL_SOT23-3~D +5V_ALW
G
2
PR10
100K_0402_1%~D
is
1
1
B B
C
2 PQ3 PR11
B MMST3904-7-F_SOT323~D 10K_0402_1%~D
E
3
2
2
PR12
@ PR13
15K_0402_1%~D
kn
1 2
PSID_DISABLE# <36>
1
10K_0402_5%~D
DC_IN+ Source
Te
+DC_IN +DC_IN_SS
PQ4
FDMC6679AZ_MLP8-5
DCX124EK-7-F PNP/NPN_SC74-6~D
1
PL4 2
FBMJ4516HS720NT_2P~D 3 5
1 2 +DC_IN
3
1
w. 1M_0402_5%~D
4
2
0.022U_0805_50V7K~D
PQ6B
PR14
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
100K_0402_5%~D
1
10U_0805_25V6K
PC5
0.1U_0603_25V7K~D
2
VZ0603M260APT_0603
1
1
PC10
PC8
ACES_50299-00501-003
PR15
PC7
PC6
1000P_0603_50V7K~D
2
1
7 PR17
0.1U_0603_25V7K~D
GND 6
PD6
1
4.7K_0805_5%~D
1 2 @ <48> @ @
SOFT_START_GC
2
GND
1
PC9
PC11
2
5 -DCIN_JACK @ 10K_0402_5%~D
PR16
5
1
4 2
2
4 3 +DCIN_JACK 5
ww
@ AC_DIS <36,48>
2
3 2
A PR18 A
@
2 1 PQ6A
1 1M_0402_5%~D
2
DCX124EK-7-F PNP/NPN_SC74-6~D
6
@ PJPDC1 PJP1
1 2
PAD-OPEN 1x3m
1
PC12 @ Compal Electronics, Inc.

2
0.1U_0603_25V7K~D Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D +DCIN
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 0.3
LA-9591P
5 4 3 2 1
A B C D E
+3.3V_RTC_LDO
m
1 1
+3.3V_ALW2
co
PR100 PR101
6.49K_0402_1%~D 15K_0402_1%
1 2 2 1
PR102 PR104
a.
2
0_0402_5%
4.7U_0603_10V6K
10K_0402_5%~D 10K_0402_5%~D
PR103
1 2 2 1
1
PC100
@ PJP100
@
2
1 2 <37> ALW_PWRGD_3V_5V
2
PR105
+DC1_PWR_SRC
2
PR106
si
PAD-OPEN 1x3m 20K_0402_1%~D
16.9K_0402_1%
+DC1_PWR_SRC +3.3V_ALW
1
1
PL100
1UH_PCMB053T-1R0MS_7A_20%
2200P_0402_50V7K
2 1 PU100
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
1
1
PR107
PC106
PC102
PC103
ne
CS2
VFB2
VREG3
VFB1
CS1
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
PC101
0.1U_0402_25V6
100K_0402_1%~D 21
PAD
1
1
PC104
6
PC107
EN
2
EN2
5
PC108
PC105
14 @
@
1
VO1
5
2 @ PR108 PR114 2
@
2
1 2 PGOOD_3V_5V 7 200_0402_1%
@ PGOOD 19 2 1
@ @ 0_0402_5% VCLK
4 UG_3V 10 TPS51285BRUKR QFN 20P
+PWR_SRC
do
PC109 PR110 DRVH2 16 UG_5V 4
PQ100 0.1U_0603_25V7K 2.2_0603_5% DRVH1 PR109 PC110
FDMC8884_POWER33-8-5 1 2 1 2 BST_3V 9 2.2_0603_5% 0.1U_0603_25V7K
VBST2 17 BST_5V 1 2 1 2 PQ101
1
2
3
VBST1
3
2
1
SW2 8 FDMC8884_POWER33-8-5
SW2 18 SW1
VREG5
DRVL2
DRVL1
PL101 SW1 PL102
+3.3V_ALWP +5V_ALWP
EN1
In
VIN
2.2UH_ETQP3W2R2WFN_8.5A_20% 3.3UH_ETQP3W3R3WFN_7A_20%
2 1 1 2
11
12
13
20
15
5
5
330U_D_6.3VM_R25M
330U_D_6.3VM_R25M
0.1U_0603_25V7K
1 @ PC111 1
EN
0.1U_0603_25V7K
680P_0603_50V7K LG_3V LG_5V
1
PC112
PC113
PC115
+ PC114 @ +
2
i-
680P_0603_50V7K
PC116
4 4
2
2 2
@ PQ102
2
1
0.1U_0603_25V7K
4.7U_0603_10V6K
FDMC7692S_POWER33-8-5 PQ103 @
1
1
2
3
3
2
1
1
1
FDMC7692S_POWER33-8-5
PC117
PC118
PR112 @
@ PR111
4.7_1206_5% 4.7_1206_5%
2
is
2
3 3
+DC1_PWR_SRC +5V_ALW2
kn
EN
3VALWP
TDC 6.7 A
Peak Current 8.1 A @ PR113
PJP101
2 1
OCP Current 9.72 A <37> ALWON
+5V_ALWP 1 2
+5V_ALW 5VALWP
Te
0_0402_5%
Rds(on): 13.6m ohm (max) TDC 4.88 A
PAD-OPEN 1x3m
PJP102
Peak Current 6.89 A
1 2
+3.3V_ALW OCP Current 8.268 A
+3.3V_ALWP
Rds(on):13.6m ohm (max)
PAD-OPEN 1x3m
w.
1U_0603_10V6K
1
PC119
@
ww
4 4

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +5V_ALW/3.3V_ALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9591P
A B C D E
5 4 3 2 1
1.35Volt +/- 5%
TDC: 7.2 A 0.75Volt +/- 5%
Peak Current: 10 A TDC 0.525A
OCP current: 12 A Peak Current 0.75A
Rds(on): 13.6m ohm(max) OCP Current 0.9A
+PWR_SRC
m
PJP200
D 2 1 1.35V_B+ D
PJP201
PR200
PAD-OPEN 1x2m~D 1 2 BOOT_1.35V +VLDOIN_1.35V 2 1 +1.35V_MEN_P
co
2.2_0603_5%~D
PAD-OPEN1x1m
DH_1.35V +0.675V_P
0.1U_0402_25V6
2200P_0402_50V7K~D
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
0.22U_0603_16V7K~D
22U_0805_6.3V6M
1
2
SW _1.35V
PC202
PC200
PC201
PC203
PC204
a.
2
1
5
1
DL_1.35V
PC205
16
17
18
19
20
@ @ PU11
VLDOIN
PHASE
UGATE
BOOT
VTT
2
21
PAD
4 15 1
+1.35V_MEN_P PQ200 LGATE VTTGND
si
FDMC8884_POW ER33-8-5
PR201 14 2
PL200 23.7K_0402_1% PGND VTTSNS +V_DDR_REF
1
2
3
1UH_PCMB063T-1R0MS_12A_20% 1 2 CS_1.35V
1 2 13 3
PC209 CS RT8207MZQW _W QFN20_3X3 GND
5
1U_0603_10V6K~D
ne
12 4 +V_DDR_REF
@ PC208 VDDP VTTREF
1
330U_D2_2VM_R15M
1
680P_0603_50V7K PR202
+1.35V_MEN_P
PC207
C + 1 2 VDD_1.35V 11 5 C
SNUB_1.35V 2
VDD VDDQ
PGOOD
4 5.1_0603_5%~D
+5V_ALW
TON
2 PQ201
PC212
FB sense trace
FB
S5
S3
PC211
do
FDMC7692S_POW ER33-8-5 0.033U_0402_16V7~D
1U_0603_10V6K~D when FB pull down to GND
1
2
3
10
6
+5V_ALW
+3.3V_ALW
1
PR205
1
@ PR203 8.06K_0402_1%~D
PR204 1.35V_FB 2 1
In
4.7_1206_5%
100K_0402_1%~D
2
PC213
2
100P_0402_50V8J~D
<37> 1.35V_SUS_PW RGD 1.35V_SUS_PW RGD 2 1
PR206
@ PR207 1.35V_B+ 1 2
i-
0_0402_5%~D
1M_0402_1%~D
1 2 S5_1.35V
<36,39,9> SIO_SLP_S4#
1
@ PR208 PR209 @ PC214
1 2 10K_0402_1%
<36,39> SUS_ON 0.1U_0402_16V7K~D
0_0402_5% @ PR210
2
is <18> 0.675V_DDR_VTT_ON
1 2
1
1
B @ PC215 0_0402_5% B
0.1U_0402_16V7K~D @ PR211
2
1 2
<36,39,9> SIO_SLP_S3#
0_0402_5%~D
Mode S3 S5 +1.5V_MEN +V_DDR_REF +0.75V_P
kn
S5 L L off off off

S3 L H on on off(Hi-Z)
+1.35V_MEN_P
S0 H H on on on
FB sense trace
Te
PJP203
2 1
2 1
JUMP_1x3m
w.
PJP204
PJP202
+1.35V_MEN_P 2 1
+1.35V_MEM
2 1
+0.675V_P 2 1 +0.675V_DDR_VTT
JUMP_1x3m
PAD-OPEN1x1m
ww
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.35V_MEN/+0.675V_DDR_VTT
5 4 3 2 1
5 4 3 2 1
PJP300
+V1.05SP_B+ 2 1
+PWR_SRC
PAD-OPEN 1x2m~D
2200P_0402_50V7K
4.7U_0805_25V6K~D
0.1U_0402_25V6
10U_0805_25V
1
1
m
D D
+3.3V_ALW
PC300
PC301
PC302
PC303
2
2
co
1
@ @
4 @
PR300
PR301 PC304
100K_0402_1%~D 2.2_0603_5% 0.1U_0603_25V7K
1 2 1 2 PQ300
2
FDMC8884_POWER33-8-5
a.
3
2
1
<37> 1.05V_A_PWRGD PU300
1 10 BST_+V1.05SP
PGOOD VBST
1 PR302 2 2 9
TRIP_+V1.05SP UG_+V1.05SP PL300
TRIP DRVH 2.2UH_ETQP3W2R2WFN_8.5A_20%
95.3K_0402_1%
EN_+V1.05SP 3
EN SW
8 SW_+V1.05SP 1 2 +1.05V_MP
si 5
@ PR303 FB_+V1.05SP 4 7
<36,39,9> SIO_SLP_A# 1 2 VFB V5IN +5V_ALW
0_0402_5%~D RF_+V1.05SP 5 6 LG_+V1.05SP 1
RF DRVL
1
S0 mode be high level
1
11 @ PC306 +
TP PC305 PC307
4
2
C 680P_0603_50V7K C
@ PR304 TPS51212DSCR_SON10_3X3 1U_0402_6.3V6K~D 220U_B2_2.5VM_R15M
ne
2
1 2 PQ301 2
<37,39> A_ON
1
0_0402_5% FDMC7692S_POWER33-8-5
1
@ PR306
3
2
1
PR305
4.7_1206_5%
1
@ PC308 470K_0402_1%
2
do
2
0.1U_0402_16V7K
2
In
PR307
2 1
4.99K_0402_1%
+1.05Volt +/- 5%
i-
2
TDC 3.67 A
B PR308 B
Peak Current 5.25 A
10K_0402_1%
PJP301 OCP current 6.3 A
1
+1.05V_MP 2 1 +1.05V_M Rds(on): 13.6m ohm (max)

is
PAD-OPEN 1x2m~D
kn
Te
A
DELL CONFIDENTIAL/PROPRIETARY A
w.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.05V_M
ww
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN +3.3V_ALW
m
D D
+5V_ALW
1
PJP400 @ PJP402
co
PAD-OPEN1x1m PAD-OPEN1x1m
1
PC400
2
1U_0402_6.3V6K
a.
6
1
5
VCNTL
7 VIN PC401
POK 4.7U_0805_6.3V6K
+3.3V_RUN 4
PJP401
2
VOUT
3 1.5VSP 2 1
PR400
VOUT
+1.5V_THERMAL
1
1 2 8 2 PAD-OPEN1x1m
EN FB
si
GND
100K_0402_5%~D
9 PR402 PC403
VIN
1
1.54K_0402_1% 0.01U_0402_25V7K
1
@ PR401 @ PC402 PU400 PC404
2
2
47K_0402_5% 0.1U_0402_16V7K APL5930KAI-TRG_SO8 22U_0805_6.3V6M
2
1
2
C PR403 C
ne
1.74K_0402_1%
2
do
In
i-
B B
is
kn
Te
A A
w.
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date <Issued_Date> Deciphered Date <Deciphered_Date> Title
+1.05VS_VTTP/+1.0VSP
ww
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Chief River VC 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2 1
5 4 3 2 1
20120911 TI-Alex Note: Although there is no pulse-overlap in 1-phase mode, during USR, the pulse comes in immediately.
So, the problem with PR504 = DNP is that if there is a high ripple, and USR is faultily detected, you will get a double-pulse.
So, we want to make sure USR is not active if it is not necessary. So, I moved it all the way to highest level so PR504 works to 8.87k.
VREF
100K_0402_1%_NCP15WF104F03RC
1
IMON
8.87K_0402_1%
PH500
365K_0402_1%
4700P_0603_50V7K
1M_0402_1%
2
2
75_0402_1%
PC500
PR502
PR501
PR503
1 PR504
@ PR500
1
75_0402_1%
@
m
10K_0402_5%~D
0.1U_0402_16V7K~D
2
D OCP-I B-RAMP F-IMAX O-USR D
1
PR505
SLEWA
150K_0402_1%
75K_0402_1%
150K_0402_1%
150K_0402_1%
2
2
PC501
PR508
co
1 PR506
PR507
+PWR_SRC
PR509
2
2
@ PJP500
1
PR510
1 2 +VCC_PWR_SRC
39K_0402_5%~D
22U_0805_25V6K
10U_0805_25V6K
22U_0805_25V6K
10U_0805_25V6K
PAD-OPEN 4x4m
100U_D3L_20VM_R55M
33U_D_25VM_R60M
1 1 1
PC735
PC736
PC731
PC732
PC734
PC738
+ +
PL501
PR511
+VCC_PWR_SRC 1 2 1 2
a.
2
2
@ PR536 FBMA-L11-453215-121LMA90T @ 2 2
10K_0402_5%~D
2 0_0402_5%1
H_VR_EN <15>
CSP1 2 1
16
15
14
13
12
11
10
9
PU500 IMVP_VR_ON <36>
@ PR537 0_0402_5%
CSN1
VBAT
THERM
SLEWA
B-RAMP
F-IMAX
IMON
OCP-I
O-USR
SKIP#
si
PWM1
+3.3V_RUN 17 8
18 CSP1 VR_ON 7 @ PR539
@ PR513
+3.3V_RUN 19 CSN1 SKIP# 6 1 2 2 0_0402_5%
1
20 CSN2 PWM1 5 75_0402_1% H_VR_READY <15>
21 CSP2 PWM2 4
PU3 N/C @ PR540
22 3 2 1
23 N/C PGOOD 2 IMVP_PWRGD <36>
GFB VDD 0_0402_5%
24 1 @ PR516
VFB VDIO
GFB
VFB
1 2
ne
+3.3V_RUN
VIDSOUT
1.91K_0402_1%~D
VR_HOT#
ALERT#
PU501
COMP
DROP
VREF
VCLK
GND
GND
9 +VCC_CORE
V5A
C PC504 C
PR519 PWM1 8 PGND2
2 1 PWM PL500
1_0603_5%
+3.3V_RUN 1 2 7
BOOT VSW
4 0.22UH_FDUE0640J-H-R22M=P3_25A_20%
3
25
26
27
28
29
30
31
32
33
TPS51622RSM PC503 0.1U_0402_25V6 @PR520

@PR520 4 1
2 1 6 PGND1 2 0_0402_5%
4.7_1206_5%~D
do
2
5 BOOT_R VDD 1SKIP#1 1 2
SKIP#
1
1000P_0402_50V7K~D PR517 VIN SKIP# 3 2
0_0603_5%~D
1U_0603_10V6K
@ PC506 PC505 1 2
1 2 PR522
PR521
1 2 1 2
1
CSD97374CQ4M_SON8_3P5X4P5
100P_0402_50V8~D
2.32K_0402_1% TI recommend 1nF
1VR_HOT#
1 PR523 2
VREF
820P_0603_50V7K~D
10K_0402_5%~D
PC508
In
2
2
1 2 1 2 PC507
0_0402_5%
VIDALERT_N
PR534
0.33U_0603_10V7K~D
2
1
PR535 PC509
VIDSCLK
PC512
4.87K_0402_1% 1500P_0402_50V7K 1U_0603_10V7K~D
@
2 1 +5V_RUN
1
2
+5V_ALW
1U_0603_10V7K~D
PR526
2
PC510
10_0603_1%
i-
1
PR512
47P_0402_50V8J~D
2
2.1K_0402_1%~D
2 1 CSP1
10K_0402_1%_TSM0A103F34D1RZ
1
PC514
1
<37,47,48,9> H_PROCHOT#
PH501
0.068U_0402_16V7K
+1.05V_VCCST
0.068U_0402_16V7K
is
2
B B
3.01K_0402_1%
43.2K_0402_1%
1
1
PC502
1
1
1
PC513
PR515
54.9_0402_1%
110_0402_1%
75_0402_1%
PR514
PR529
PC511
PR527
PR528
0.1U_0402_25V6
2
kn
2
2
@ @ PR531
2
0_0402_5%
2 1 VFB CSN1
<15> VIDSCLK <15> VCCSENSE
<15> VIDALERT_N
from processor @ PR532
<15> VIDSOUT 0_0402_5%
2 1 GFB
<17> VSSSENSE
Te
CPU
TDC 10 A
Peak Current 32 A
OCP Current 38.4 A
DCR: 0.82m +-5% ohm
w.
PH500 B value: 4250k 1%

PH501 B value: 3435k 1%
ww
A A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +VCC_CORE
5 4 3 2 1
5 4 3 2 1
PL700
1UH_PCMB042T-1R0MS_4.5A_20%
2 1
PQ700 V30415-T1-GE3 1P POWERPAK1212-8
+PWR_SRC_AC CHAGER_SRC
1
+SDC_IN PR700
0.01_1206_1%~D @ PJP700
2
5 3 4 1 1 2
+DC_IN_SS sense adapter
3 2 PAD-OPEN 4x4m
0.1U_0603_25V7K~D
@ @ PR710
1
0_0402_5%
@ PR701 <37> VCP 1 2
PC700
1 2
DC_BLOCK_GC <48>
1
0_0402_5% @ PR702 D
1 2 2 PQ701
m
<48> CSS_GC
0_0402_5% G NTR4502PT1G_SOT23-3~D
1
D D
D S PU703
3
2 PQ703A 1 6
G SI3993CDV-T1-GE3_TSOP6~D REF Out
co
PQ702 S CSSN_1
S
NTR4502PT1G_SOT23-3~D 5 6
D
PD701 DOCK_DCIN_IS+ <34>
PR748
2 44.2_0402_1%~D
+DOCK_PWR_BAR
CSSN_1
CSSP_1
2 5 2 1
G
1
1 PQ703B GND IN-
3
PR703 SI3993CDV-T1-GE3_TSOP6~D +SDC_IN 3
V+ IN+
4
10K_0402_5%~D
+DC_IN_SS PR749
10_0402_5%~D
10_0402_5%~D
S
2 1 2 4 2 1 CSSP_1
D
100K_0402_1%~D
DOCK_DCIN_IS- <34>
BAT54CW_SOT323~D INA199A1DCKR_SC70-6~D
PC733 59_0402_1%
1
a.
PR704
PR705
PR706
100K_0402_1%~D
1
1
@ PR708
G
0.1U_0603_25V7K~D
3
1 2
<48> +CHGR_DC_IN
2
PC703 PC704
PR707
1_0805_1%~D 1U_0603_25V6K 0.1U_0603_25V7K~D PC705 Discrete current monitor circuit
2
1 2 1 2 1 2 @ PR709
10_1206_5%~D
2
1
1 2
DK_CSS_GC <48>
PR745
0.1U_0603_25V7K~D 0_0402_5%
+SDC_IN GNDA_CHG
si
GNDA_CHG PC709
1
PC706 PU700 1 2
10U_0805_25V6K
ACN
ACP
2
2
PR713 2 1 +DCIN 20 16 BQ24715_REGN 1U_0603_10V6K~D
VCC REGN PD702
261K_0402_1%
+SDC_IN BAT54HT1G_SOD323-2~D
5
PR714 @ PR725
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
2200P_0402_50V7K~D
49.9K_0402_1%~D 1 2 3 17 PR715
1
2 1 CMSRC BTST 2.2_0603_5%
0_0402_5%
1
1
1
1 2
PC742
PC707
PC711
PC712
PC741
ne
2 1 4 18 CHG_UGATE 4
2
2
2
ACDRV HIDRV
0.047U_0603_25V7M
1
PC708 0.1U_0402_25V6
PC713
C GNDA_CHG C
6 19
3
2
1
ACDET PHASE
PQ704
BQ24715_REGN SIRA14DP-T1GE3_POWERPAK-SO8-5 +PWR_SRC
100K_0402_1%~D
8 15 CHG_LGATE
do
<37> CHARGER_SMBDAT SDA LODRV
1
PR747
9 14 PR716
+VCHGR
<37> CHARGER_SMBCLK SCL GND PL701
0.01_1206_1%~D
3.3UH_FDVE1040-H-3R3M=P3_11.3A_20%~D
2
@ PR717 2 1 4 1
1 2 5 13
<37,47,48> ACAV_IN ACOK SRP 3 2
820P_0603_50V7K~D
10U_0805_25V6K
0_0402_5%
In
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
121K_0402_1%~D
0.1U_0603_25V7K~D
1
PC714
2
7 12
PC737
PC716
0_0402_5%
<37> V_SYS IOUT SRN
1
0_0402_5%
PR719
PR746
PR718
2
PR722
PC715
PC717
PC718
100P_0402_50V8J~D
2
+3.3V_ALW @ PR726 4.02K_0402_1%
2
2
2
1 2 10 11 1 2 4 @ @
PC719
1
CELL /BATDRV
2
TP
10K_0402_1%~D @
1
4.7_1206_5%~D
BQ24715RGRR_QFN
21
i-
PR711 @ PC720 PC721
BQ24715_REGN 1 2
3
2
1
GNDA_CHG GNDA_CHG PQ706 0.1U_0603_25V7K~D 0.1U_0603_25V7K~D PC722
1
PR724
10K_0402_1%~D 1 2 1 2 1 2
GNDA_CHG SIRA06DP-T1-GE3_POWERPAKSO-8
@PR750
@ PR750 0.1U_0603_25V7K~D
1 2
<48> CHARGER_CELL_PIN
0_0402_5% PJP701 GNDA_CHG
1 2 GNDA_CHG
@ PR751
1 2
+3.3V_ALW2 10K_0402_1%~D
is GNDA_CHG
PAD-OPEN1x1m
B BATDRV# <48> B
+5V_ALW H_PROCHOT# <37,46,48,9>
100P_0402_50V8J~D
0.01U_0402_25V7K~D
DYN_TUR_CURRENT_SET#
1
PR727
PC724
PC725
kn 2
221K_0402_1%~D
45W High
2
+3.3V_ALW2 +5V_ALW @ @
PR729
@ PR728
0_0402_5%
1.8M_0402_1%
1
1 2
65W Low
1
1
PR730
150K_0402_1% PR732 BQ24715_REGN
+3.3V_ALW2
8
20K_0402_1%~D PU2A
DMN66D0LDW-7 2N SOT363-6
VCP 1 2 3
Te
P
2
+
1
O
6
3
PQ710A
PQ710B
2
-
G
LM393DR_SO8~D
220P_0402_50V8J~D
2 5 +DC_IN
210K_0402_1%
69.8K_0402_1%
PC727
+3.3V_ALW
100P_0402_50V8J~D
1
@ PC740 PR736
10K_0402_1%~D
1
4
1
1M_0402_1%~D
+3.3V_ALW
PR734
PR735
PC726
232K_0402_1%~D
48.7K_0402_1%
2
1
220P_0402_50V8J
1
1 2
2
PR737
PR739
w.
PR738
2
PC728
+5V_ALW
6 2
0.1U_0402_25V4Z~D
PQ712A 2 1
PR740
2
2
DMN66D0LDW-7 2N SOT363-6 100K_0402_5%~D
8
PU2B
5
2 PU3 5 @ PR741
P
<37> DYN_TUR_CURRNT_SET#
2
1 + 7 1 2 ACAV_IN_NB <37,48>
P
4 B 6 O
22.6K_0402_1%~D
42.2K_0402_1%~D
0_0402_5%
1
O 100P_0402_50V8J~D -
G
2
1
PROCHOT_GATE <36>
100P_0402_50V8J~D
A
1
G
10K_0402_1%~D
ww
LM393DR_SO8~D
4
3
1
PC729
PR742
PR743
PC730
A A
3
TC7SH08FU_SSOP5~D
PR744
2
2
5
ACAV_IN <37,47,48>
2
2
PQ712B
Adapter Protection Circuit for Turbo Mode
4
Title
+GPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-9591P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Friday, May 17, 2013 Sheet 47 of 58
5 4 3 2 1
5 4 3 2 1
PD807 PQ801
PD806 NTR4502PT1G 1P SOT23-3 +3.3V_ALW
PDS5100H-13_POWERDI5-3~D
SDMK0340L-7-F_SOD323-2~D Purpose: Trigger PROCHOT# when PC801 PR801
+PBATT_IN_SS active battery is removed from
1
3 2 1 3 1 0.1U_0402_10V7K 100K_0402_5%~D
1 +NBDOCK_DC_IN_SS 1 2 2 1
2 system. +3.3V_ALW
6
2
Allows EC to re-establish
5
PQ809 PQ802A
SI4835DDY-T1-GE3_SO8~D PR802 system performance for battery SLICE_BAT_PRES# 1
P
1 8 B 4 2 DMN66D0LDW-7 2N_SOT363-6~D
100K_0402_5%~D
+BATT_SUM 2 7 next in line. SLICE_BAT_ON 2 O
+3.3V_ALW
1
A
G
3 6 H_PROCHOT# <37,46,47,9>
1
5
PU801
3
1
100K_0402_5%~D
+3.3V_ALW2
2
PR804 +PWR_SRC_AC TC7SH08FU_SSOP5~D
1
PR813
100K_0402_5%~D PR807
3
+3.3V_ALW 100K_0402_5%~D
6 2
PR808
1
PD800 100K_0402_5%~D PQ805B
2
m
PDS5100H-13_POWERDI5-3~D PC803 5 DMN66D0LDW-7 2N_SOT363-6~D
1
D 3 1 2 D
+3.3V_ALW2 DMN66D0LDW-7 2N_SOT363-6~D
2
+VCHGR 1 2 PR810
10K_0402_5%~D
4
1
PQ807A
SDMK0340L-7-F_SOD323-2~D
2 0.1U_0603_25V7K~D 100K_0402_5%~D
PR815
PC806
3
PQ800 1 2
co
2
SI4835DDY-T1-GE3_SO8~D PQ811
1 8 PR816 +PBATT 1 8 +3.3V_ALW
PQ806B
PR817 2200P_0402_50V7K~D
2 2
2 DMN66D0LDW-7 2N_SOT363-6~D
6
2 7 2 7 1 5 PC805
PQ806A
100K_0402_5%~D
DMN66D0LDW-7 2N_SOT363-6~D
SLICE_BAT_PRES# <34,36,41,48> PC807 @ PR811
6
3 6 3 6 PQ807B 0.1U_0402_10V7K
330K_0402_5%~D 1 2 2 1 PQ805A
PD811
5 5 0_0402_5% 1 2
4
0.47U_0805_25V7K~D 2 DMN66D0LDW-7 2N_SOT363-6~D
FDS6679AZ-G_SO8~D SLICE_BAT_ON 5 2
4
1
1
PBAT_PRES# 1
P
4
1
B
STSTART_DCBLOCK_GC
1
2
3
<47> BATDRV# 4
6
2 O
A
G
a.
PQ812A
1
4 PU804
3
2 @ PD818
DMN66D0LDW-7 2N_SOT363-6~D PD808
PDS5100H-13_POWERDI5-3~D PQ810 SDMK0340L-7-F_SOD323-2~D
3
TC7SH08FU_SSOP5~D
1
FDS6679AZ-G_SO8~D
PR821 1 @ PR812 2 1 2
PQ812B
<36> DIS_BAT_PROCHOT# CHARGER_CELL_PIN <47>

820_0603_5%~D
5 1 2 3301_DSCHRG_FET_GC 0_0402_5%
<36,41> PBAT_PRES# SLICE_BAT_ON <36,48>
8
7
6
5
2
3
PR814
330K_0402_5%~D
4
2 1
1
PC811
si
0.01U_0603_25V7K~D
+DOCK_PWR_BAR
5
PQ826
FDMC6679AZ_MLP8-5
4 +3.3V_ALW2
PC808
Purpose: Turn on the PQ817
ne
0.1U_0402_10V7K
2 1 for primary or module bay
1
2
3
PU805
+3.3V_ALW2 TC7SH08FU_SSOP5~D battery to provide power to
5
100K_0402_5%~D
C PC810 1 dock side without AC exist. C
2
SLICE_BAT_PRES# <34,36,41,48>
P
@ B
2 1 4
1
PC809 PU806 O 2 1 PR819 2
PR818
A +3.3V_ALW2
G
1500P_0402_7K~D TC7SH08FU_SSOP5~D 0.1U_0402_10V7K 100K_0402_5%~D
5
2
1
1 D
P
B
1
2
3
1 2 4 2 DOCK_DET# <34,36,48>
O 1 @ PR820 2 ACAV_IN#
do
PD810 2 G
A
G
10K_0402_5%~D
S PQ817
3
1
4 SDMK0340L-7-F_SOD323-2~D 0_0402_5% DMN65D8LW-7_SOT323-3~D
PQ815
3
PR822
FDS6679AZ-G_SO8~D
2
8
7
6
5
AO3418_SOT23-3
1
D
2 +3.3V_ALW2 +3.3V_ALW2 Purpose: Turn on the PQ817
PQ816
G +3.3V_ALW2 for Slice battery discharge
In
S PC812
@ PR894
2
1 2 0.1U_0402_10V7K without AC exist
+3.3V_ALW2 0_0402_5%~D
PQ829 2 1 PR823 PR824 @
1
SI2301CDS-T1-GE3 1P_SOT23-3 PU807
TC7SH08FU_SSOP5~D 100K_0402_5%~D 100K_0402_5%~D
PD813
3
1 2 3 1
5
PD814
+3.3V_ALW
1
@ PR895 SDMK0340L-7-F_SOD323-2~D SDMK0340L-7-F_SOD323-2~D 1
P
B SLICE_BAT_ON <36,48>
0_0402_5% 1 2 4
1
2
O 1 @ PR825 2
3
2
2
2
PR830 A
PQ819B
100K_0402_5%~D 0_0402_5%
1
D
DMN65D8LW-7_SOT323-3~D
5 ACAV_IN#
i-
PD820 PQ813A 2
2
SDMK0340L-7-F_SOD323-2~D DMN66D0LDW-7 2N_SOT363-6~D
NTR4502PT1G 1P SOT23-3
PR826 PD819 G @
1 2
4
<34,36,41,48> SLICE_BAT_PRES# 1 6 2 1 SDMK0340L-7-F_SOD323-2~D S
PQ818
3
100K_0402_5%~D 1 2
DOCK_SMB_ALERT# <34,36,41>
D PQ832
1
PR828 PQ813B
6
<36,41> AC_DIS 1 2 2 DMN65D8LW-7_SOT323-3~D
1
DMN66D0LDW-7 2N_SOT363-6~D 1
PQ814
10K_0402_5%~D G 4 3 2
S PR829
2 1 2 2
3
SLICE_PERF_EN <37,48>
100K_0402_5%~D
+3.3V_ALW2 3
3
@ PQ819A
5
1
B @ PR831
0_0402_5%
2
@ PR832
0_0402_5%
1
+DOCK_PWR_BAR
is 2
PR848
0_0402_5%~D
0_0402_5%
PR853
2
1
PR827
2
100K_0402_5%~D 1
@ PR834
2 SLICE_BAT_PRES# <34,36,41,48>
B
+DC_IN_SS 1 2 +NBDOCK_DC_IN_SS 0_0402_5%
1
@
3
S
@ 1 2
2 PR841 1 3301_DSCHRG_FET_GC @
DSCHRG_MOSFET_GC
G
1 2 @ PR861 2 PQ828 PD816
1
<47> +CHGR_DC_IN 0_0402_5%
@ PR833 0_0402_5% DMN65D8LW-7_SOT323-3~D SDMK0340L-7-F_SOD323-2~D
<37,48> SLICE_PERF_EN
<34,36,48> DOCK_DET# D PD821
CHGVR_DCIN
PR835 0_0402_5%
DK_PWRBAR
1
PD815
2
1 2 CD3301_DCIN PQ821A SDMK0340L-7-F_SOD323-2~D
+DC_IN
DC_IN_SS
2 DMN66D0LDW-7 2N_SOT363-6~D PR839

47_0805_5%~D
kn
1 6 2 1
NTR4502PT1G_SOT23-3~D
@PR838
@
2
PR838
1
PC813 2 1 1 100K_0402_5%~D
DOCK_AC_OFF <34>
0.1U_0603_50V4Z~D 0_0402_5%
+PBATT PQ821B PQ831
@ PR843 3
2
2
1
1
DMN66D0LDW-7 2N_SOT363-6~D 1 DMN65D8LW-7_SOT323-3~D
0_0402_5%
1
1
PQ830
P50ALW 1 2 BAT54CW_SOT323~D 4 3 2
36
35
34
33
32
31
30
29
28
@ PR844 PR849 PQ822

PR846 PU800 +5V_ALW 2 1 2 2 1 1 3
+3.3V_ALW2
S
2
+3.3V_ALW2 <41>1 SOFT_START_GC
2 @PR850
@ 10K_0402_5%~D +3.3V_ALW2 3
NTR4502PT1G 1P SOT23-3
2
NC
CHARGERVR_DCIN
DK_PWRBAR
GND
NC
BLK_MOSFET_GC
DSCHRG_MOSFET_GC
PR850
DC_IN_SS
PBatt+
100K_0402_5%~D
3
1
CD_PBATT_OFF 2 3 PR837 PC814
3
100K_0402_5%~D SLICE_BAT_ON <36,48>
2
@ PR847 100K_0402_5%~D 0.1U_0402_10V7K
G
0_0402_5%
2
1 2ACAVDK_SRC 1 PR840 2 2 1
<34> ACAV_DOCK_SRC#
2 1 +3.3V_ALW2
0_0402_5% 100K_0402_5%~D
2
Te
1 27
5
2 DC_IN P50ALW 26 PR836
@ PR854 @ PR851 @ PR852
1
1 2 ERC1 3 SS_GC PBATT_OFF 25 DK_AC_OFF @ PR855 100K_0402_5%~D 1
+SDC_IN
P
ERC1 DK_AC_OFF_EN 0_0402_5% 0_0402_5%~D 0_0402_5% B SLICE_BAT_PRES# <34,36,41,48> PR864
4 24 3301_ACAV_IN_NB 1 2 4
0_0402_5%
5 ACAVDK_SRC ACAV_IN_NB 23
ACAV_IN_NB <37,47> +DC_IN_SS O 2 DOCK_DET# <34,36,48> 100K_0402_5%~D
+PBATT
1
G
GND GND
1
CD3301_SDC_IN 6 22 DK_AC_OFF_EN 1 2
SDC_IN DK_AC_OFF_EN DOCK_AC_OFF_EC <36> PU808
7 21 SL_BAT_PRES# @ PR857
2
3
<47> DC_BLOCK_GC ACAVIN 8 DC_BLK_GC SL_BAT_PRES# 20 0_0402_5% TC7SH08FU_SSOP5~D
PR858 <37,48> SLICE_PERF_EN
<34,36,48> DOCK_DET#
P33ALW2 9 ACAV_IN BLKNG_MOSFET_GC 19 1 2 ACAV_IN#
@ PR859
EN_DK_PWRBAR
1 2 P33ALW2 NBDK_DCINSS
<37,47,48> ACAV_IN @ PR860 1M_0402_5%~D
SS_DCBLK_GC
0_0402_5%
1
0_0402_5% D
DK_CSS_GC
1 2 @ PR872
w.
PWR_SRC
@ PQ823 <37,47,48> ACAV_IN 1 2 2

CSS_GC
P33ALW
@ PR862 37 ME2301D-G 1P SOT-23-3 G

TP 0_0402_5%
ERC3
ERC2
1 2 @ PR863 S
+3.3V_ALW2
3
GND
PQ825
3
1 2 3 1
0_0402_5%
0_0402_5% @ PR866
+NBDOCK_DC_IN_SS DMN65D8LW-7_SOT323-3~D
CD3301BRHHR_QFN36_6X6~D 0_0402_5%
10
11
12
13
14
15
16
17
18
2 1 @ PQ824A
2
EN_DOCK_PWR_BAR <36>
2
@ PR869 @ PR870 DMN66D0LDW-7 2N_SOT363-6~D

@ PR868
0.1U_0603_25V7K~D
<47> CSS_GC 1 2 1 2 1 2 1 6
P33ALW
ERC2
<47> DK_CSS_GC
0_0402_5% +3.3V_ALW
1
ERC3 240K_0402_5%~D 47K_0402_5%~D

PC815
A @ PQ824B A
ww
EN_DK_PWRBAR DMN66D0LDW-7 2N_SOT363-6~D

0.047U_0603_25V7M
2
PR874 @ PR856 1 2 4 3
0.1U_0402_25V4Z~D
+3.3V_ALW2
1
1 2 D
0_0402_5%~D DOCK_DET# <34,36,48>
2 2 1 @ PR875
PC816
1M_0402_5%~D
1
STSTART_DCBLOCK_GC 100K_0402_5%~D
PC817
G
5
S PQ827 @
3
@ PR877 <37,48> SLICE_PERF_EN

2
@ 3301_PWRSRC 1 2 DMN65D8LW-7_SOT323-3~D
0_0402_5% +PWR_SRC_AC
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Selector
LA-9591P
5 4 3 2 1
5 4 3 2 1
Based on PDDG rev 0.7 Table 5-1.
+VCC_CORE
m
D D
1 1 1 1 1
co
PC900 PC901 @ PC902 @ PC903 PC904
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2
a.
1 1 1 1 1
PC905 PC906 PC907 @ PC908 PC909
2 2 2 2 2
si
1 1 1 1 1
PC910 @ PC911 @ PC912 PC913 PC914
2 2 2 2 2
ne
C C
1 1 1 1 1
do
PC915 PC916 PC917 PC918 @ PC919 @
2 2 2 2 2
In
1 1 1 1 1
PC920 PC921 PC922 PC923 @ PC924 @
2 2 2 2 2
i-
1 1 1 1 1
PC925 PC926 PC927 PC928 PC929
2 2 2 2 2
is
B B
kn
Te
w.
ww
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PROCESSOR DECOUPLING
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V ersion Change L ist ( P. I. R . L ist ) Page 1

R equest
Item Page# Title D ate O w ner Issue D escription Solution D escription R ev.
1 P45 1.5VSP 8/17 Compal Base power budget request, add 1.5V powre rail Add PU400
m
D D
co
2 P42 +5V/+3.3V 8/17 Compal reserver PR114 for TPS51282 application ADD @PR114
3 P47 Charger 8/17 Compal EC can't detect charger IC cause can't charger modify SMBus net for correct connect
a.
4 P46 Vcore 8/17 Compal schematic control error cause can't set OCP add Vref net for correct connect
5 P48 Selector 8/17 Compal in order to meet latest multi-battery request change control signal for meet E5 request
si
6 P43 1.35V/0.675V 8/17 Compal chagne OCP setting change PR201 from 20k to 24.9k.
7 P42 +5V/+3.3V 10/22 Compal Reserve 0ohm for 3v5v enable debug Change PR113 X01
from SD03420018L (S RES 1/16W 2K +-1% 0402)
ne
to SD028000080 (S RES 1/16W 0 +-5% 0402)
C C
8 10/22 Change PL300

P44 +1.05V_MP Compal +1.05V_MP EA for ripple portion can't meet
from SH00000PJ00 (S COIL 1UH +-20% PCMB063T-1R0MS 12A) X01
spec. 31.5mv, after change from 1u to 2.2u test is pass
to SH00000MR00 (S COIL 2.2UH +-20% ETQP3W2R2WFN 8.5A)
do
Change PU100
9 P42 +5V/+3.3V 10/22 Compal Original 3v5v IC -TPS51225 can't support 2cell battery from SA00005LS00 (S IC TPS51225CRUKR QFN 20P PWM) X01
follow TI suggestion, When TPS51285A/B is used, to SA000064T00 (S IC TPS51285BRUKR QFN 20P PWM)
please update the below four components. 1)2)Change PC118(VREG5 Cap) and PC100(VREG3 Cap)
1)VREG5 cap to 4.7uF from SE080105K80(S CER CAP 1U 10V K X5R 0603)
In
2)VREG3 cap to 4.7uF to SE00000MA00(S CER CAP 4.7U 10V K X5R 0603)
3)CS1 resistor to 1/5 of the Tps51275’s value
4)CS2 resistor to 1/5 of the Tps51275’s value 3) Change PR106(for CS1)
5)VCLK connection (when not be used): add 200-ohm to GND from SD03484528L (S RES 1/16W 84.5K +-1% 0402)
to SD034169280 (S RES 1/16W 16.9K +-1% 0402)
i-
4) Change PR105(for CS2)
from SD03410038L (S RES 1/16W 100K +-1% 0402)
to SD034200280 (S RES 1/16W 20K +-1% 0402)
5) Add PR114 SD034200080(S RES 1/16W 200 +-1% 0402)

is
B B
P47 Charger 10/22 Compal To avoid HW and Power SMT materials can't entirely X01
10 replace
Change PU3,PU801,PU804,PU805,PU806,PU807
from SA74108040L(S IC 74AHC1G08GW SOT353 AND)
P48 Selector to SA00708012L(S IC TC7SH08FU SSOP 5P AND)
kn
11 P47 Charger 10/22 Compal follow E5- Salado 14"15" schematic 1) @PQ819, @PQ824 X01
2) EMI request for add PL700
SH00000IW00(S COIL 1UH +-20% PCMB042T-1R0MS 4.5A)
Compal follow TI suggestion modify setting value to meet Intel 1) Change PR501
Te
12 P46 Vcore 11/02 X01

VR12.6(ULV) validation EA from SD034422380 (S RES 1/16W 422K +-1% 0402)
1) Imon to SD034365380 (S RES 1/16W 365K +-1% 0402)
2) Loadline
3) transient 2) Change PR521
from SD000009M80 (S RES 1/16W 2.61K +-1% 0402)
w.
to SD00000WS8L(S RES 1/16W 2.32K +-1% 0402)
3) @PC506 100p_0402 and change PR535

from SD02810028L(S RES 1/16W 10K +-5% 0402)
ww
A to SD034487100 (S RES 1/16W 4.87K +-1% 0402 (LF)) A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_PIR 1
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1) Change PR711
P47 Charger 11/05 Compal 1) TI suggestion BQ24715 cell pin pull high 3.3V change
13 from SD02800008L (S RES 1/16W 0 +-5% 0402) X01
m
D to V_regn(6v) for sequence issue D
to SD034100280 (S RES 1/16W 10K +-1% 0402)
,add PR750 SD028000080(S RES 1/16W 0 +-5% 0402)
co
2) Reserve 0 ohm for debug
2) Add @PR751
Compal 1) @PR863, @PR870, @PR869, @PR824, @PR875, @PQ823

14 P42 +5V/+3.3V 11/05 follow E5- Salado 14"15" schematic X01
a.
2) Add @PR848, @PR851
and add PR834, PR852, PR853, all is
SD028000080(S RES 1/16W 0 +-5% 0402)
si
3) Add PR874 SD028100480(S RES 1/16W 1M +-5% 0402)
4) Add PD819 SCS0340L01L(S SCH DIO SDMK0340L-7-F SOD-323)
15 P47 Charger 11/05 Compal Improve charger efficiency Change PR715 X01
ne
from SD028200A80 (S RES 1/16W 20 +-5% 0402)
to SD013220B80 (S RES 1/10W 2.2 +-5% 0603)
C C
16 P47 Charger 11/05 Compal Delete @PR731, @PR733, @PU702 X01

follow E5- Salado 14"15" schematic
do
Compal Support QAD WCEPTA analysis, to modify 1.05 OCP Rtrip Change PR302 X01
17 P44 +1.05VTTP 11/05 -QAD team from SD00000H880 (S RES 1/16W 54.9K +-1% 0402)
resistance to 95K, Cpk value will pass specification.
-Huang.Hanks to SD034953280 (S RES 1/16W 95.3K +-1% 0402 )
(PCP)
In
Compal EMC team suggestion @PC105, @PC203, @PC301 X01
18 P48 +5V/+3.3V 11/05
i-
- EMC team
1.35V/0.675V Wen. Andy
+1.05V_MP is Add
B
19 P48 Selector 11/15 Compal follow E5- Salado 14"15" schematic
PQ827 SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3), X01 B
for undock shutdown issue @PR856 SD028000080 (S RES 1/16W 0 +-5% 0402),
PQ816 SB534020000 (S TR AO3402 1N SOT-23),
PQ828 SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3),
kn
PR861 SD028000080 (S RES 1/16W 0 +-5% 0402)
PR802, PR827, PR840 change

from SD028240380 (S RES 1/16W 240K +-5% 0402)
to SD028470280 (S RES 1/16W 47K +-5% 0402),
Te
PR804, PR826, PR839 change

from SD028470280 (S RES 1/16W 47K +-5% 0402),
to SD028240380 (S RES 1/16W 240K +-5% 0402)
w.
P47 Charger 12/12 Compal Change PR713 X01

20 from SD034294380 (S RES 1/16W 294K +-1% 0402)
to SD034261380 (S RES 1/16W 261K +-1% 0402)
P48 Selector
@PR844
ww
A A
21 P41 +DCIN 2013 Compal- ESD team's PD1 vendor(NXP) proposal PD1 pin 5 PD1 pin5 connect to +3.3V_ALW X01_2
connected to the VCC (5V or 3.3V). DELL CONFIDENTIAL/PROPRIETARY
/01/11 ESD team
Title
5 4 3 2 1
5 4 3 2 1

R equest
1). Add PU808
22 P48 Selector 2013/ Compal To avoid +DOCK_PWR_BAR leakage voltage when system P/N: SA007080120 (S IC TC7SH08FU SSOP 5P AND)
X01_2
m
only with main battery
D
01/23 D
2). Add PQ830
co
P/N: SB000007900 (S TR NTR4502PT1G 1P SOT23-3)
3). Add PQ831

P/N: SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3)
a.
4). Add PD821
P/N: SCS0340L010 (S SCH DIO SDMK0340L-7-F SOD-323)
5). Add PR836, PR837

P/N: SD028100380 (S RES 1/16W 100K +-5% 0402)
si
6). Add PC814
P/N: SE102104K00 (S CER CAP 0.1U 10V +-10% X7R 0402)
ne
23 P41 +DCIN 2013 Compal PPM-Jovins_Chang and Sourcer-Willie_Zeng highlight Change PQ6 X02
SB000009N8L will shortage after 2013/05 From : SB000009N8L (S TR IMD2AT-108 PNP/NPN SC74-62)
C /02/07 To : SB000009P80 (TR DCX124EK-7-F PNP/NPN SC74R-6)
C
P48 Selector 2013/ Compal GPIO net - AC_DIS# is high active. Corrent net name. 1). Change PQ6A.5 and PR828.1 net name from AC_DIS#
do
24 to AC_DIS
X02
02/18 AC_DIS circuit modify to improve output voltage level. 2). Add PQ829
P/N: SB00000H500 (S TR SI2301CDS-T1-GE3 1P SOT23-3)
, PQ832
In
P/N: SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3)
, PD820
P/N: SCS0340L010 (S SCH DIO SDMK0340L-7-F SOD-323)
, @PR894
, PR895
i-
P/N: SD028000080 (S RES 1/16W 0 +-5% 0402)
3). modify PR828,PR830

4). Delete PQ820
is 5). Delete PL5, add PJP1
B B
25 P41 2013/ Compal-ME DFX highlight Battery connetor(locattion:PBATT1) Battery connetor(locattion:PBATT1) footprint follow
+DCIN ME team Iris requesti to change
X02
hard to insert.
02/18 from SUYIN_200277GR009M262ZR_9P-T
kn
to ALLTO_C144LS-109A9-L_9P-T
26 P48 Selector 2013/ Compal layout spec limit Delete PD817, modify PD815 footprint same as PD701,
X02
from SDMK0340L-7-F_SOD323-2
02/18 to RB717F_SOT323-3
Te
Vcore 2013/ Compal- Add snubber component by ESD team request Add
27 P46 X02
PC508, PC714
P48 Selector 02/18 ESD team P/N:SE025821K80 (S CER CAP 820P 50V K X7R 0603)
Hsu. Matt PR522, PR724
w.
P/N:SD001470B80 (S RES 1/4W 4.7 +-5% 1206 )

ww
A A
Title
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1). Change PC703 from 0.1U to 1U
28 P48 Selector 2013/ Compal follow E5- Salado 14"15" schematic P/N: SE000006900 (S CER CAP 1UF 25V K X5R 0603) X02
m
D
02/21 D
2). Change PC706 from 1U to 0.1U

1) For Input current sense stablilze
co
P/N: SE00000QK00 (S CER CAP 10U 25V K X5R 0805 H1.25)
2) To provent charger into sleep mode dual 3). Change PC708 from 0.01U to 10U
AC transient. P/N: SE00000G880 (S CER CAP 0.1U 25V K X5R 0402)
a.
4). Change PR734 from 100K ohm to 210K ohm
3) Fine tune ACOK response time. P/N: SD034210380 (S RES 1/16W 210K +-1% 0402)
Change PR735 from 46.4K ohm to 69.8K ohm
P/N: SD034698280 (S RES 1/16W 69.8K +-1% 0402)
4) Adapter protect rating setting
si
5) Fine tune H_PROCHOT# response time. 5). Add @PC740
6). Change PR738.pin1 from BQ24715_REGN connect to +3.3V_ALW2.

6) Improve ACAV_IN_NB ref voltage accuracy.
ne
Change PR738 from 118K ohm to 48.7K ohm
P/N: SD034487280 (S RES 1/16W 48.7K +1% 0402)
C
7) Improve current sense accuracy. Change PR744 from 12K ohm to 10K ohm
C
P/N: SD034100280 (S RES 1/16W 10K +-1%
do
7). Change PR748 from 6.8 ohm to 210K ohm
P/N: SD034442A80 (S RES 1/16W 44.2 +-1% 0402)
Change PR749 from 10 ohm to 69.8K ohm
P/N: SD00000W200 (S RES 1/16W 59 +-1% 0402)
In
29 P46 Vcore 2013/ Compal- Add 22U_0805 by ESD team request Change PC732, PC736 from 10U to 22U X02
02/26 ESD team from
P/N: SE00000QK00 (S CER CAP 10U 25V K X5R 0805 H1.25)
Hsu. Matt
i-
to
P/N: SE00000XH80 (S CER CAP 22U 25V M X5R 0805 H1.25)
is
B B
30 P48 Selector 2013/ Compal Modify resistor value to meet voltage 1). Change PR802,PR827,PR840 from 47K ohm to 100K X02
02/27 tolerence P/N: SD028100380 (S RES 1/16W 100K +-5% 0402)
kn
2). Change PR804,PR826,PR839 from 240K to 100K

P/N: SD028100380 (S RES 1/16W 100K +-5% 0402)
31 P47 Charger 2013/ Compal follow E5- Salado 14"15" schematic to 1). Add PC741, PC742 X02_1
Te
03/18 add charger input MLCC to 88u P/N: SE00000XH80 (S CER CAP 22U 25V M X5R 0805 H1.25)
2). Due to space limit, so delete @PC701, @PC702,
@PC710
32 P42 +5V/+3.3V 2013/ Compal support DFX team change choke layout pad 1). Change PL101, PL102, PL200, PL300 PCB FootPrint X02_1
w.
to avoid soldering issue change

P43 1.35V/0.675V 03/20 from CYNTE_PCMC063T-2R2MN_2P
P44 +1.05V_MP to CYNTE_PCMB064T-3R3MS_2P
Vcore 2013/ Compal Support acoustic team to reduce noise 3). Change PC738 X02_1
33 P46
ww
A A
from 33U(SGA00005M00) to 100U
03/21 P/N: SGA00008R00 (S POLY C 100U 20V M D ESR55M
(D3L_H=2.8mm) DELL CONFIDENTIAL/PROPRIETARY
Title
5 4 3 2 1
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V ersion Change L ist ( P. I. R . L ist )

R equest
Item Page# Title D ate Issue D escription Solution D escription R ev.
O w ner
m
D D
1 22,40,38 ESD 11/05/2012 COMPAL ESD team request Remove D3,D27,D22,DE1,DE2 0.2(X01)
26,34 Reserve D20
co
2 27 Safty 11/05/2012 COMPAL Safty team request Pop F2 and reserve R160 0.2(X01)
3 37 HW 11/05/2012 COMPAL Based on align E5,P5 Fan module pin define Swap JFAN1 pin define 0.2(X01)
a.
4 22,40,38 HW 11/06/2012 COMPAL To avoid PT phase occurs ESD issue and Reserve D3,D27,D22,DE1,DE2 0.2(X01)
26 change back ESD request
5 40 36 HW 11/08/2012 DELL DELL drop Media LED function Remove backlight LED function and change connector to 6pin 0.2(X01)
6 26 HW 11/09/2012 COMPAL Remove EMI solution at Speaker side Remove R132, R133, R134 and R135 0.2(X01)
si
7 12,22,37 HW 11/09/2012 DELL DELL drop ALS function Remove ALS interface from EC and CPU side than move touch screen 0.2(X01)
signal to eDP side
8 22 HW 11/09/2012 COMPAL change Webcam power enable from PCH pop R106 and de-pop R102 0.2(X01)
ne
9 10 HW 11/09/2012 COMPAL Schmatic error and remove eDP backlight Remove RC150 0.2(X01)
C C
control pull up resistor
10 39 HW 11/12/2012 COMPAL +1.05V_MODPHY can't meet INTEL timing spec change +1.05V_MODPHY to MOS solution 0.2(X01)
do
11 18 19 HW 11/12/2012 COMPAL Remove DIMM VERF power rail from power side Remove RD2, RD4, RD8 and RD9 0.2(X01)
12 27 HW 11/12/2012 COMPAL change miniDP OCP solution remove D10 R160 F2 and add U50 de-pop C383 0.2(X01)
13 26 HW 11/12/2012 COMPAL refer salado 14" to change PCBEEP circuit remove C132,C146,R146,R138,C133 and C143 than add C145,C146,R147,R151 0.2(X01)
In
and de-pop R194 R153
14 26 HW 11/12/2012 COMPAL If doesn't has external power, Sleeve will Add AUD_NB_MUTE# to control Sleeve pin. 0.2(X01)
be floating mode and no reference GND.
i-
15 37 HW 11/12/2012 COMPAL Change board ID to X01 change R392 form 240K to 130Kohm 0.2(X01)
change +1.05V_RUN_VMM power enable signal from LP_EN to DOCKED and add 0.2(X01)
+3.3V_RUN_VMM for DP2320 series 3.3V power rail
remove L3 and move U6.E5 to +1.05V_VMM_VDD power rail
16 21 HW 11/12/2012 COMPAL
is
Vendor update schematic for power saving change U6.J4 to +3.3V_RUN_VDDA
B B
R85 change to 3.74K_1%

remove LP_EN, R232 and U6A.A5 to NC
remove R55 and pop-option R207 when use VMM2310
kn
17 21 HW 11/12/2012 COMPAL change VMM2320 config remove DP to VGA PTN3392 circuit and add 0ohm pop option for 2320 config 0.2(X01)
18 22 HW 11/13/2012 COMPAL Add Mic power and remove DBC function Add 3.3V_RUN for Mic power and remove DBC function at JeDP.2 0.2(X01)
19 19 HW 11/13/2012 COMPAL refer PDG1.0 to change SODIMM control change RC68, RC126 and RC173 from 2.2 to 2ohm 1% 0.2(X01)
Te
circuit resistor change RC67,RC69,RC130,RC132,RC217 and RC221 from 1.82K to 1.8Kohm 1%

20 37,36,12 HW 11/13/2012 COMPAL GPIO map update to 2.7 version Move EC_WAKE# from ECE5048[L]5 to MEC5075 GPIO52. 0.2(X01)
Change name: 1.5V_SUS_PWRGD to 1.35V_SUS_PWRGD for DDR3L.
w.
Add NFC_DET# ECE5048 GPIOL[5] to NFC moudle & add R38 PU

21 20,27,29 ME 11/13/2012 COMPAL ME change connector change JmDP1,JNFC1,JMEDIA,JKBTP1,JUSH1 0.2(X01)
,38,40
22 24 HW 11/14/2012 COMPAL Vendor update schematic for power saving align AUX/DDC SW voltage with DP Hub to +3.3V_RUN_VMM 0.2(X01)
ww
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT EE P.I.R (1/6)
5 4 3 2 1
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O w ner
m
D 23 2,3,6,34 HW 11/15/2012 COMPAL update SATA topology fro Mainstream CPU exchange SATA1&SATA2 topology 0.2(X01) D
co
24 12 HW 11/15/2012 COMPAL Add LAN_WAKE# T-topology Pop RC301 to link LAN_WAKE# and EC_WAKE# 0.2(X01)
25 15 HW 11/15/2012 COMPAL remove RC252 for cost saving change RC252 to PJP11(1mm jumper-short) 0.2(X01)
26 16 HW 11/15/2012 INTEL MOW_WW46 request change for VCCUSB3PLL and change CC42 and CC49 from 1u_0402 to 22u_0603 0.2(X01)
a.
VCCSATA3PLL change CC76 and CC77 from 100u_1206 to 22u_0603
27 20,28,30,31 HW 11/15/2012 COMPAL change AND gate to same source Change U20, U26, U29 and U30 from SA74108040L to SA00708012L 0.2(X01)
28 34 ME 11/15/2012 COMPAL ME change Docking connector change JDOCK1 that Pin145 from PWR1 to GND1 & Pin148 from PWR2 to GND2 0.2(X01)
si
29 38,12 HW 11/15/2012 COMPAL remove +3.3V_TP power load switch solution remove U40, R458,C424 and C423 0.2(X01)
30 22 HW 11/15/2012 COMPAL change LCDVDD power control circuit change U9 from TPS22966 to APL3512 solution 0.2(X01)
31 31,32 HW 11/15/2012 COMPAL remove TPS22965 solution remove U51(TPS22965) and U34(TPS22965) than add U3(TPS22966) 0.2(X01)
ne
32 10,27 HW 11/15/2012 COMPAL ESD solution for black screen issue Add CC450 on EDP_CPU_HPD to GND and C451 on DPC_HPD to GND 0.2(X01)
C C
33 40 ME 11/16/2012 COMPAL ME change drawing Add H18 and H10,H11 change size from 2.3 to 3.4 , 0.2(X01)
H5 change size from 2.8 to 2.3
do
34 22 HW 11/16/2012 COMPAL change diode to daul-diode fro cost saving remove D4,D5,D6,D7 and add D10,D21 0.2(X01)
35 40 ME 11/16/2012 COMPAL ME request change SW1 to SKRBAAE010 0.2(X01)
36 30 ME 11/16/2012 COMPAL ME change connector change SD1 0.2(X01)
In
37 21,26,28, HW 11/16/2012 COMPAL For EA rework request Add PJP12~25 for +1.05V_RUN_VMM,+3.3V_RUN_VMM,+3.3V_ALW_PCH,+1.05V_RUN, 0.2(X01)
31,39 +3.3V_SUS,+3.3V_M,+5V_RUN,+3.3V_RUN,+3.3V_LAN,+3.3V_mSATA_WWAN,+3.3V_HDD
,+3.3V_WLAN,+5V_RUN_AUDIO,+3.3V_RUN_AUDIO
i-
38 37 HW 11/19/2012 COMPAL change thermal diode for cost saving change Q11,Q13 and Q14 form SB000008P0L to SB33904510L 0.2(X01)
change L44 and L45 from SM01000558L to SM01000C500 0.2(X01)
change L35 and L36 from SM01000AM0L to SM01000C500
39 38,26,30,22 HW 11/19/2012 COMPAL change Bead for cost reduce change LE1 from SM01000DH0L to SM01000BV00
is change L21 from SM01001788L to SM010005N00
B B
40 9 HW 11/19/2012 COMPAL change APS pin 11 net_name for DELL APS debug Change JAPS1.11 net name from SIO_PWRBTN# to POWER_SW#_MB 0.2(X01)
change net name from HOST_ALERT1_R_N to PCH_GPIO15, and pop RC190
41 12,28 HW 11/19/2012 COMPAL support TLS confidentility 0.2(X01)
kn
remove R188
42 37 HW 11/19/2012 COMPAL change thermal OTP to 98 degree change R394 from 1.24K to 1.82K_1% 0.2(X01)
43 31 HW 11/20/2012 COMPAL Intel notice remove HDD_DEVSLP function on remove HDD_DEVSLP from JMINI2.44 0.2(X01)
WWAN JMINI port de pop HDD_DEVSLP pull up resistor R155
Te
44 28 HW 11/20/2012 COMPAL LOM LED issue reverse Q32,Q33 of C & D gate 0.2(X01)
45 22 HW 11/20/2012 COMPAL ME change connector change JLED1 0.2(X01)
w.
46 35 HW 11/21/2012 COMPAL Align EMI part change L54 pat to DLW21SN900SQ2L that same with L42, L39 0.2(X01)
47 15 HW 11/22/2012 COMPAL Per Intel CRB updated change VCCST_PWRGD pull high value from 10K ohm to 1K ohm 0.2(X01)
48 26 HW 11/22/2012 COMPAL Universal Jack no longer supported on X5 Remove D9,D11,R209,R210,C195,C196,R198,R199 0.2(X01)

ww
A A
49 6,12,25,31 HW 11/26/2012 DELL For support DEVSLP on WWAN JMINI2 & mSATA SATA HDD change from port0 to port1, and connect HDD_DEVSLP 0.2(X01)
JMINI3 Dock change from port1 to port2, and connect mSATA_DEVSLP
Title
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R equest
O w ner
m
D 50 21,26 HW 11/26/2012 COMPAL change Bead for cost reduce L6 and L7 from SM01000GG0L to BLM15PX471SN1D(SM01000M700) 0.2(X01) D
L22, L23, L24 and L25 from SM010028800 to BLM15PX121SN1D(SM01000L300)
co
51 31 HW 11/26/2012 COMPAL change WWAN power control signal Change U3.5 from 3.3_1.5V_WLAN_E to SIO_SLP_WLAN# 0.2(X01)
52 12,36 HW 11/27/2012 COMPAL NFC_DET# change to PCH side GPIO59 UC1.AT5 change from PCH_GPIO59 to NFC_DET#
0.2(X01)
U37.B1 change to NC
a.
53 22,26,38,40 HW 11/27/2012 COMPAL Remove ESD reserve location Per ESD experiment, D3,D27,D22,DE1,DE2 can be remove 0.2(X01)
54 33 HW 11/27/2012 COMPAL Per USB2.0 EA result Change U42 from SM01002080L(DLW21SN900SQ2L) to SM070001600(OCE2012120YZF)0.2(X01)
si
55 6,12,25,31 HW 11/27/2012 DELL Per Dell requset, only JMINI3(mSATA ) SATA HDD use port0 ,Dock use port1 0.2(X01)
support DEVSLP
56 31 HW 11/28/2012 COMPAL change +3.3V_WLAN PWR control change +3.3V_WLAN PWR control from SIO_SLP_WLAN# to AUX_EN_WOWL 0.2(X01)
ne
57 28 HW 11/28/2012 COMPAL change +3.3V_mSATA_WWAN control change +3.3V_mSATA_WWAN control from WWAN_mSATA_EN to MCARD_WWAN_PWREN 0.2(X01)
C C
58 34 HW 11/28/2012 COMPAL For EMI request, change to 33 ohm for R252/R253/R254/R255/R256/R257/R258/R259/R260/

0.2(X01)
docking DVI noise R261/R262/R263/R264/R265/R266/R267 change to 33ohm from 0 ohm
do
59 21 HW 11/28/2012 COMPAL For use IDT2320, need change EEPROM PN U7 change from SA00003FL10(W25X10BVSNIG) to SA00006HH00(W25X10CLSNIG) 0.2(X01)
60 22 HW 11/28/2012 COMPAL change Bead for cost reduce LE1 change from SM01000DH0L(BLM18BB221SN1D)to SM01000BV00(BLM15BB221SN1D)0.2(X01)
In
61 6,25,31 HW 11/29/2012 DELL To support mainstream and Premium CPU, SATA HDD change from port0 to port1, and connect HDD_DEVSLP
0.2(X01)
change to SATA port assignment. Dock change from port1 to port0, and connect mSATA_DEVSLP
62 12,31,34 HW 11/29/2012 DELL To support the SATA DevSLP function for Change DEVSLP0/GPIO33 to mSATA_DEVSLP 0.2(X01)
i-
new SATA port assignment. and DEVSLP1 to HDD_DEVSLP
63 33 HW 01/10/2013 COMPAL For USB3.0 EA result L37 & L38 change to SM070000S80(S COM FI_ CHENG HANN WCM2012F2SF-670T04) 0.3(X02)
64 40 HW 01/10/2013 COMPAL For ME team force test result SW1 change to SN111005800(S TACK SW BCL31 SKRBAAE010 SPST) 0.3(X02)
is
B B
65 9 HW 01/17/2013 COMPAL For U42 2nd source (MC74VHC1G08DFT2G)can't PCH_RSMRST#_R add RC136 10K pull dowm 0.3(X02)
boot issue
kn
66 28 HW 01/17/2013 COMPAL For meet INTEL LAN SPEC Y3 change to SJ10000JC00(S CRYSTAL 25MHZ 18PF +-30PPM 7V25000034) 0.3(X02)
67 22 HW 01/17/2013 COMPAL For trial run U9 2nd source U9 pin 4 & pin5 connect to +3.3V_ALW 0.3(X02)
1.change R435 from 1.8k to 150(SD028150080)

Te
2.R430/R438/R436 from 2.2k to 150(SD028150080)

68 40 HW 01/17/2013 COMPAL For LED light test result 3.R434 change from 220 to 150(SD028150080)
4.R427 change from 1K to 150 ohm(SD028150080) 0.3(X02)
5.R429 change from 620 to 330 ohm(SD028330080)
w.
6.R431/R433 change from 330 to150 ohm(SD028150080)
1. modify JEDP1 pin assignment

69 22 HW 01/17/2013 COMPAL For prevent EDP pin shift then cause 0.3(X02)
2. pin 29 (IO_LOOP) add 1k pull down
broken issue
ww
A A

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D 1.L22/L23/L24/L25 change to SM010019400 from SM01000L300 D
2.L51/L52 change to SM01000FV00 from SM01000AM0L 0.3(X02)

70 25,26 HW 12/05/2012 COMPAL For Audio Presison result
co
3.Delete L50/L53 & add R491/R492 0 ohm-short
71 37 HW 12/07/2012 COMPAL Change Board ID for ST R392 change to 33K ohm from 130k ohm 0.3(X02)
a.
1. JNFC1 change to 6718K-Y15N-01L
2. JKBTP1 change to 6718K-Y16N-01L
72 HW 02/19/2012 COMPAL Change connector tyoe 3. JUSH1 change to 6718K-Y20N-00L
4. JUSB3 change to PUBAUE-09FLBS1FF4H0 0.3(X02)
si
5.JMEDIA change to 6718K-Y06N-01L
6. SH1 change to 6718K-Y12N-01L
1. Q11/Q13/Q14 change to SB000008P00(S TR MMBT3904WT1G NPN SC70-3)
ne
73 37 HW 02/21/2012 COMPAL For OTP issue, & change OTP to 96 degree
from SB33904510L(S TR PMST3904 NPN SOT323-3) 0.3(X02)
from 98 degree
C 2. R394 chagne to SD00000SJ80(S RES 1/16W 1.58K +-1% 0402) from C
SD034182180(S RES 1/16W 1.82K +-1% 0402)

74 7 HW 02/21/2012 COMPAL change JTAA1 connector type JTAA1 change to PANAS_AXK820145WG from ACES_50185-02041-001 0.3(X02)
do
75 38 HW 02/21/2012 COMPAL Per EMI Test result Remove L44 & L45 0.3(X02)
76 38 HW 02/21/2012 COMPAL Per ESD Test result Pop C141 & C142 & C143 0.3(X02)
In
77 9 HW 02/21/2012 COMPAL add XDP@ for XDP component change XDP circuit to XDP@ 0.3(X02)
78 9 HW 02/21/2012 COMPAL update XDP circuit for INTEL ITE can't boot remove RC121 and pop RC102 0.3(X02)
i-
79 9,11,35 HW 02/21/2012 COMPAL Fixed 2 USB Port use the same OC# signal 1.change JUSB3 OC# from USB_OC0# to USB_OC1#
0.3(X02)
issue 2.change USB_OC1#/3# to USB_OC1#, USB_OC3# and add RC166 for OC1# pull
up resistor
80 9,11,35 HW 02/21/2012 COMPAL
is
Add jumper for clock buffer co-layout add PJP26, PJP27 and PJP28 beween UC5 0.3(X02)
B B
1.L42 change to SM070003N00(CHILISIN CMM0805-20Y-N)from SM070001600(

SUPERWORLD OCE2012120YZF)
kn
81 33 HW 02/21/2013 COMPAL Per EMI test result 2.L37/L38 change to SM070001R00(MURATA DLW21SN670HQ2L) 0.3(X02)
from SM070001E0L(MURATA DLW21SN900HQ2L)
3.L8/L39/L54 change to SM070001N00(MURATA DLW21HN900SQ2L)from
SM01002080L(MURATA DLW21SN900SQ2L)
Te
1. Pop CC71 & CC72 & CC73

82 33 HW 02/22/2013 COMPAL Per ESD test result
2. Add C452 & C453 & C454(@) 22uF 0603 size 0.3(X02)
3. R338 & R349 & R352 change to 10k ohm from 1k ohm
w.
4. Add C455 & C456 & C457 0.1UF

83 9,12 HW 02/25/2013 COMPAL For LID & AOAC S3 wake up issue Change Net name to SIO_EXT_SMI# from USB_OC3# and change to
0.3(X02)
PCH_GPIO45 from SIO_EXT_SMI#
ww
A A

Title
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5 4 3 2 1

R equest
O w ner
m
D 1. add CC86~CC90 between clock signal D
84 7 HW 02/25/2013 COMPAL add RF noise solution at clock buffer 2. add RC62 for UC5 power rail 0.3(X02)
co
3. change RC100 from 0ohm short to 10ohm
4. change UC5 from IDT_5V60034DCG8 to CYPRESS_CY2304SXI-1T
85 23 HW 02/25/2013 COMPAL refer INTEL MOW to upfate HDMI cost reduce change R462~R469 resistor from 680(SD034680080) to 470ohm(SD034470080) 0.3(X02)
level shifter main link
a.
86 33 HW 02/25/2013 COMPAL change USB charge solution for SAMSUNG phone change U39 from SA00004VH00 to SA00006L600 0.3(X02)
87 26 HW 02/27/2013 COMPAL for Fixed BIOS fliah HOTSOS issue change R154 from PCH_AUDIO_EN to RUN_ON 0.3(X02)
si
88 9 HW 02/28/2013 COMPAL For ESD request Add CC149(@) on H_PROCHOT# near CPU side 0.3(X02)
89 9 HW 02/28/2013 COMPAL Follow INTEL CRB XDP schematic CC68 change to 0.1uF from 0.01uF 0.3(X02)
ne
C 90 7 HW 02/28/2013 COMPAL For RF 24MHz issue 1. remove UC5 CC25,CC57,CC80,CC86~CC90,CC22,RC62,RC100,CC23 C
0.3(X02)
2. Change RC65 to 0 ohm-short
91 9 HW 02/28/2013 COMPAL For Touch panel issue 1.TOUCH_PANEL_INTR# add RC181(@) PU & RC180 PD 0.3(X02)
do
92 7,29 HW 03/01/2013 COMPAL refer GPIO3.0 to add PCH_TPM_LPC_EN 1. add RC56 for pull up enable signal and add R198 for pop option 0.3(X02)
2. change R193 form 0hm to 10ohm
In
93 7 HW 03/12/2013 COMPAL Base on INTEL EDS SPEC Update Rev 1.5.1 1. LANCLK_REQ# change to UC1.AD1 from UC1.Y5
2. MINI1CLK_REQ# change to UC1.T2 from UC1.U2
3. MINI2CLK_REQ# change to UC1.N1 from UC1.T2 0.4(X02)
4. MMICLK_REQ# change to UC1.U5 from UC1.AD1
5. PCH_TPM_LPC_EN change to UC1.Y5 from UC1.U5
i-
94 7 HW 03/14/2013 COMPAL For PCIE CLK & PCIE CLK REQ signal mapping 1. CLK_PCIE_LAN change CLKOUT_PCIE port2
2. CLK_PCIE_MINI2 change CLKOUT_PCIE port3
0.4(X02)
3. CLK_PCIE_MMI change CLKOUT_PCIE port4
is 4. CLK_PCIE_MINI1 change CLKOUT_PCIE port5
B B
95 30 HW 03/14/2013 COMPAL For O2 enters into test mode unexpectedly 1. SD/MMCCD# add C256(0.1uF) & R493(1M) pull-down to GND 0.4(X02)
with SD card inserted incompletely issue. 2. C222 change to 1uF(SE000000K80) from 0.1u(SE00000G880)
kn
96 21 HW 03/15/2013 COMPAL For Synaptics vender request 1. Delete VMM2310 co-lay related schematic 0.4(X02)
97 21 HW 03/15/2013 COMPAL For ESD request 1. Add C458(@) &C459(@) &C460(@) &C461(@) 22uF 0603 size 0.4(X02)
Te
98 7 HW 03/18/2013 COMPAL For INTEL request PCIECLK_REQ0# add RC57(10k) pull-high to+3.3V_RUN 0.4(X02)
99 21 HW 03/20/2013 COMPAL For Synaptics vender request 1. Delete R78/R80/R82

0.4(X02)
w.
2. add C132
100 21 HW 03/20/2013 COMPAL For ME request ST2 change to H_2P8 from CLIP_C5P1 0.4(X02)
101 9, 12, 15 HW 03/22/2013 COMPAL For ESD request 1. H_CPUPWRGD add CC90 100pF(@) to GND
0.4(X02)
ww
A A
2. H_THERMTRIP# add CC91 100pF(@) to GND
3. H_VCCST_PWRGD add CC22 100pF(@) to GND

Title
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5 4 3 2 1

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D D
102 9 HW 03/27/2013 COMPAL For Touch panel issue pop RC181 and depop RC180(@) 0.4(X02)
co
For XDP SPEC
103 9 HW 03/27/2013 COMPAL pop RC97 & RC135 0.4(X02)
104 32 HW 04/24/2013 COMPAL For USB S3 wake up issue U33 power rail change from +3.3V_RUN to +3.3V_SUS 1.0(A00)
a.
105 9 HW 04/24/2013 COMPAL For XDP signal should be contact to PCH change RC97 and RC135 to 0ohm short 1.0(A00)
106 37 HW 04/25/2013 COMPAL Change Board ID for A00 R392 change from33K ohm to 1K ohm 1.0(A00)
si
107 40 HW 04/25/2013 COMPAL For LED EA R436 change from150 ohm to 330 ohm;R438 change from 150 ohm to 220 ohm 1.0(A00)
108 28 HW 04/25/2013 COMPAL for support Vpro reset pin depop U20 and add R145 1.0(A00)
ne
109 12 HW 04/25/2013 COMPAL reserve for support non vpro pop option pin reserve RC292 100 ohm pull down 1.0(A00)
C C
110 6 HW 05/13/2013 COMPAL For Crystal EA result & RTC time fail issue 1. CC1 & CC2 change from 18pF to 15pF 1.0(A00)
do
111 16 HW 05/17/2013 COMPAL For ESD request Depop CC71/CC72/CC73 1.0(A00)
In
i-
is
B B
kn
Te
w.
ww
A A

Title
5 4 3 2 1

Dell Latitude E7240 - Compal LA-9431P

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Dell Latitude E7240 - Compal LA-9431P

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A B C D E

PCB NO : LA-9431P (DAA00005Z10)

EMC@ : EMI & ESD & RF Component Vpro 1@/4@/EMC@/ 2@/5@/EMC@

5@ : TAA/B 4M SPI ROM (cost down) 1@/EMC@ 2@/5@/EMC@/

Goliad12 Block Diagram

Memory BUS (DDR3L)

BGA CPU USB DOCKED DOCK _USB2.0[0] USB3.0/2.0+PS

PAGE 32 DOCK _USB2.0[5]

LAN SWITCH SATA2 W25Q32FVSSIQ Combo Jack PAGE 40

32M 4K sector PAGE 7 CPU XDP Port

SMSC KBC DC/DC Interface

KB and TP CONN SW & LED PAGE 40

USB PORT# DESTINATION

+VCC_CORE +1.35V_MEM +5V_RUN +3.3V_RUN

+3.3V_RUN +5V_RUN +1.05V_RUN

SML0CLK 0ohm LAN_SMBCLK 28

2A A7 GPU_SMBCLK SMBUS TOPOLOGY

INTVRMEN - INTEGRATED SUS 1.05V VRM FLASH DESCRIPTOR SECURITY OVERRIDE

@ <9> PCH_JTAG_TCK PCH_JTAG_TCK AE62 A12 SATA_IREF 2 1 +PCH_ASATA3PLL HDD_DET# 1 2

<9> PCH_JTAG_TDI PCH_JTAG_TDI AD61 L11 @ RC14 0_0402_5% 100K_0402_5% RC11

AC4 RSVD SATALED SATA_ACT# <40>

HDA for Codec

EMI depop location

LPC_LAD0 AU14 AN2 PCH_SMB_ALERT#

PCH_SPI_CS0# 2@ R10 1 2 0_0402_5% TAA_CS0#_R 11 9 10 12 TAA_DO2_64 2@ R58 1 2 33_0402_5% PCH_SPI_DO2

C42 CLKOUT_PCIE_N0 XTAL24_IN B25 XTAL24_OUT 2 1

2 2 RC57 10K_0402_5% K21 PAD~D T6 @ 18P_0402_50V8J

B41 M21 PAD~D T7 @

EMC@ RC63 1 2 22_0402_5% MCP_TESTLOW4 1 2

+3.3V_RUN DSWODVREN - ON DIE DSW VR ENABLE

reference CRB 1 UC1B @ CC48

2 <36> CPU_DETECT# H_CATERR# K61 PROC_DETECT XDP_DBRESET# RC116 2 1 1K_0402_5%

PROC_TCK E61 CPU_XDP_TMS

DDI1_LANE_N0 C54 C45 EDP_CPU_LANE_N0 COMPENSATION PU FOR eDP

reference PDG 0.9

PCH_AUDIO_EN P1 D60 H_THERMTRIP#_R @ RC172 2 1 0_0402_5% +3.3V_ALW_PCH

10K_0402_5% 10K_0402_5% RC289

PCH_GPIO66 BBS_BIT TOUCH_PANEL_INTR# 2.2K_0402_5% RC204

Low depop RC288 (DEFAULT) :Enable HIGH LPC HIGH HIGH

GPIO17 GPIO21 GPIO22 GPIO24

CFG STRAPS for CPU

Display Port Presence Strap

DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3

Package Daisy Chain:

VIDSCLK N63 F40

D63 VCC G25

@ T79 AD60 G41

@ T81 AA59 G45

B U59 RSVD VCC G53 B

AB57 VCC L22

CAD Note: RC250 SHOULD BE PLACED CLOSE TO CPU 1 1

CC42 place near B18 CC42

+PCH_VCCDSW3_3 AH10 AD8

K18 SUS OSCILLATOR AB8 0_0402_5% @ RC261

CC54 place near AD10

CC32 place near AH10

AJ29 VSS VSS AP20 AV55 VSS VSS D31

1 1 1 1 1 1 1 1 DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA RC195

DDR_A_MA10 107 108 DDR_A_BS1

+ DDR_A_CAS# 115 116 M_ODT0 QD1

155 DM5 DQS5 156

DQS#6 DM6 <9> DDR_PG_CTRL A

DDR_A_DQS4 171 172 4 0.675V_DDR_VTT_ON

DDR_A_D34 175 176 DDR_A_D39