KSJ EtherCAT FPGA Master 【Introduction】

【EtherCAT】Problematic cases FPGA based EtherCAT master

■Cyclic communication at accurate time intervals is required.
→ Inconstant timing due to OS influence (even if real-time OS)
■ High-speed periodic communication of 100 μsec or less.
→ Often tough case for actual data size / slave number
■ EtherCAT logic should be independent from user logic.
can resolve these problems
■Cyclic EtherCAT flame transmittion jitter is
50 nsec or less, due to non-OS existing
■40 μsec cyclic communication (PDO) has achieved
with 40bytes × 5slaves !
■Master stack works only on FPGA, it does not affect CPU.

→ It easily tends to be an interfering design (*Since our master stack is based on HDL,
it does not relate with FPGA vendor)

■ Xilinx FPGA based EtherCAT Master 【Function image】

■ KSJ FPGA EtherCAT master function

Our master stack is limited to basic and important functions of EtherCAT.
Corresponds to :「ETG.1500 classB standard」, 「DC」, 「Cable Redundancy」
※Some of class A functions are implemented (FoE)

■Cyclic communication speed / transmission timing jitter

32bit data ×1 slave system 8 μsec (Jitter ≒ 30nsec)
40Byte data × 5 slaves system 40 μsec (Jitter ≒ 30nsec)

■ CPU, FPGA utilizing for users

・CPU area can be freely designed by users, including OS.
・User FPGA logic can be implemented into our master stack free area
(User can combine our logic and user logic)
・KSJ can provide EtherCAT API whch can work on FreeRTOS, Xenomai, BareMetal, etc.
 KSJ EtherCAT DC control feature
Timing of DC function Problem ・DC trigger timing does not link
with cyclic communication timing
■ Standard EtherCAT network ・But DC trigger should happen
within cyclic communication interval.
・Then, those timing should be managed
by Master control.

■Faster cyclic PDO (< 100μsec) makes more severe

■DC trigger timing is same for all slaves,
but the timing for receiving frame is different!

■ Timing chart of DC trigger and frame receive

Strength
We can offer FPGA based Master stack.
It leads stable cyclic timing controlling even if 100μsec PDO.

■ DC timing synchronization on “bilayer” EtherCAT system

Generally, DC timing sync can be available only on Grand EtherCAT line or Local EtherCAT line.

KSJ “Grand Slave & Local master” enables to synchronize both of DC timing !
(Our result: 6 Grand slaves × 8 Local slaves can synchronize DC with 100 μsec PDO)
 KSJ EtherCAT slave achievement
■ Features of each slave type

We can provide various forms of slaves according to required performance!

Minimize the initial/board cost
→ Using ESC (EtherCAT slave control) IC, like Beckhoff ET1100.
Correspond to some volume of user microprocessor application
→ Using micro-processor built-in ESC (Infineon XMC, TI Sitara, etc.)
High-speed EtherCAT slave or User FPGA logic exist
→ Implement ESC IP core into FPGA,
Dual Port RAM for date exchange with user logic.)

＊KSJ slave supported function

→ CiA402, FoE, FSoE, etc.

■ ESC ASIC based Slave diagram ■ Micro processor based Slave diagram

■ FPGA based Slave diagram

Strong points
・ User only need to take care of
the interface on DPRAM.
( EtherCAT slave function and
DPRAM is inside of FPGA area.)
・ Reduced numbers of parts
・ Low risk of part’s EOL

Now, KSJ designed HDL EtherCAT slave stack without microblaze processor.
It become more suitable for function safety standard (SIL4).
 KSJ EtherCAT Evaluation board
～KSJ master stack or slave stack is implemented～
■ LZ202 Hardware spec
・Xilinx Zynq SoC XC7Z010 implemented
(Dual ARM Cortex A9 CPU 667 MHz
+ FPGA Logic 28K logic cell)
・ 1GB DDR3 SDRAM 1066Mbps
・ QSPI NOR Flash 32MB
・ RJ45 100Mbps 2 EtherCAT ports
・ RJ45 1Gbps Ethernet port (for TCP/IP)
・ microSD slot (SDHC, SDHS)
・ USB micro Connector for UART
Micro USB ・ Expansion Connector: 80port’s GPIO
(UART) (57pin connected to Zynq,
2 x 100Mb 16 pin can be used as differential pair pins)
1Gb EtherCAT MicroSD ・ Power supply DC 24V
Ethernet ・ Size: 130x80mm
・ Temperature environment: 0-50 ℃
・ RoHS Corresponded

■Providable EtherCAT Master stack on LZ202

Measured
Measured Master
Version Working area OS Supported function PDO cyclic speed
transmitting jitter
(32bit × 3slaves)
KSJ FPGA
ARM CPU
Master ・ETG.1500 Class B standard
1 & FreeRTOS 20 μsec 30 nsec
(ARM ・DC function
Xilinx FPGA
initialization)
KSJ FPGA
Master ・ETG.1500 Class B standard
2 Xilinx FPGA - 20 μsec 30 nsec
(microblaze ・DC function
version)
KSJ FPGA
Slave (FPGA area) PDO, DC
3 Xilinx FPGA - - -
(using Beckhoff (ARM CPU) SDO
IP core

■KSJ offering data for our stack evaluation

・EtherCAT API/driver（FreeRTOS*）※Other OS is negociable.
・FPGA design data（as Xilinx Vivado project）
・MicroBlaze software
・Sample application（FreeRTOS）
・Windows sample application（for Master evaluation using TCP/IP）

■Implementable KSJ EtherCAT slave stack on LZ202

・Beckhoff IP core and KSJ slave stack is implemented on LZ202
・For evaluation, sample digital I/O board connection LZ202 expansion connector can provided.