A B C D E

1 1

Boston

LA-2721 Schematics Document

2 2

Intel Dothan / Alviso GM(PM) / DDR-1 / ICH6-M

(nVIDIA NV44MV / ATi M24C)

Rev:1.0
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:55 Sheet 1 of 53
A B C D E
 A B C D E

Compal confidential
File Name : LA-2721 Fan Conn Thermal Sensor Clock Generator
page 38 Intel Dothan CPU ADM1032ARM ICS954226
page 4,5
CRT/TV-OUT
page 4 page 14
page 15
1
H_A#(3..31) FSB H_D#(0..63)
1

400 / 533 Mhz

NV44MV/M24C
VGA Board Intel Alviso DDR-1 333 Mhz
DDR-SO-DIMM X2
page 16
GM( GML,PM) BANK 0, 1, 2, 3page 11,12,13

LCD CONN PCBGA 1257 page 6,7,8,9,10

page 16 Signal Channel DDR-1
Docking AMP & Audio Jack
DMI Audiopage 31 page 32
MARVELL LAN
RJ45 CONN 88E8036 PCI-E BUS USB 2.0 USB conn x 4
2
page 28 88E8053 page 39 2
page 27

IDSEL:PCI_AD18
Intel ICH6-M USB 2.0 BT Conn
page 36
GNT#1 PCI BUS mBGA-609
REQ#1 Audio CKT
IDSEL: PCI_AD20 AC-LINK
IRQG# ALC250-D
GNT#2
IRQH# page 17,18,19,20 page 30
REQ#2
Mini PCI IRQA#
TI Controller
MDC
socket IRQB# PCI7411/6411/4510/1510 page 35
page 29 IRQC# page 23,24 LPC BUS
IRQD# SATA
SATA to PATA
PATA HDD conn
88SA8040
3
1 394 Slot 0 5in1 CardReader page 21 page 21 3
Conn. Slot page 25
page 24 page 26 PATA
CDROM
Connector
page 22
Power On/Off CKT.
page 39
Docking CONN.
SMsC LPC47N217 ENE KB910 *RJ-11 / 45(LED*2)
LPC47N207 *COMPOSITE Video Out
page 35
DC/DC Interface CKT. RTC CKT. *LINE IN / OUT
page 33,34
page 42 page 41 *PS/2
*Print port
Int. KBD *1394
page 36 *USB
Power Circuit DC/DC Power OK CKT. FIR *DC JACK
Touch Pad
4 page 44~50 page 41
page 38 CONN. page 36 BIOS 4

page 37 page 39

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:56 Sheet 2 of 53
A B C D E
 A B C D E

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
S0 (Full ON) HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1 (Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
1 B+ AC or battery power rail for power circuit. N/A N/A N/A 1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+CPU_CORE Core voltage for CPU ON OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+DDRVTT 1.25V switched power rail for DDR terminator ON OFF OFF
+1.5VALW 1.5V always on power rail ON ON ON*
+1.5VS 1.5V switched power rail ON OFF OFF Board ID / SKU ID Table for AD channel
+1.8VS 1.8V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+DDRVCC 2.5V power rail for DDR ON ON OFF Ra/Rc/Re 100K +/- 1%
+2.5VS 2.5V switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+3VALW 3.3V always on power rail ON ON ON* 0 0 0 V 0 V 0.100 V
+3V 3.3V power rail ON ON OFF 1 8.2K +/- 1% 0.216 V 0.250 V 0.289 V
+3VS 3.3V switched power rail ON OFF OFF 2 18K +/- 1% 0.436 V 0.503 V 0.538 V
+5VALW 5V always on power rail ON ON ON* 3 33K +/- 1% 0.712 V 0.819 V 0.875 V
+5VS 5V switched power rail ON OFF OFF 4 56K +/- 1% 1.036 V 1.185 V 1.264 V
+5VCD 5V switched power rail for CDROM ON OFF OFF 5 100K +/- 1% 1.453 V 1.650 V 1.759 V
2 2
+12VALW 12V always on power rail ON ON ON* 6 200K +/- 1% 1.935 V 2.200 V 2.341 V
+RTCVCC RTC power ON ON ON 7 NC 2.500 V 3.300 V 3.300 V
+5VAMP 5V switched power rail for amplifier ON OFF OFF
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BOARD ID Table
Board ID PCB Revision
External PCI Devices 0 0.1
Device IDSEL# REQ#/GNT# Interrupts 1 0.2
C ardBus AD20 2 PIRQA/PIRQB/PIRQC/PIRQD 2 0.3
1394 AD20 2 PIRQA/PIRQB/PIRQC/PIRQD 3 1.0
Card reader AD20 2 PIRQA/PIRQB/PIRQC/PIRQD 4
Mini-PCI AD18 1 PIRQG/PIRQH 5
6
7
3 3

SKU ID Table
EC SM Bus1 address EC SM Bus2 address SKU_ID1 1 3 7
Button Button Button
Device Address Device Address
SKU_ID 0 1 2 3 4 5 6
0 10 1 8 0
Smart Battery 0001 011X b ADM1032 1001 110X b
1 10C 3 C 2
EEPROM(24C16/02) 1010 000X b 2'nd Battery 1001 011X b
(24C04) 2 10G 5 9 4
1011 000Xb Docking 1010 000X b
3 10GC 7 D 6
4
5
6
ICH6M SM Bus address 7
Device Address
4 4
Clock Generator 1101 001Xb
( ICS 952623)

DDR DIMM0 1001 000Xb

DDR DIMM1 1001 001Xb Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
Notes
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:55 Sheet 3 of 53
A B C D E
 5 4 3 2 1

JP23A

H_A#[3..31] H_A#3 P4 A19 H_D#0 H_D#[0..63]

<6> H_A#[3..31] H_A#4
H_A#5
U4
A3#
A4#
Dothan D0#
D1# A25 H_D#1
H_D#2
H_D#[0..63] <6>
+3VS
V3 A5# D2# A22
H_A#6 R3 B21 H_D#3
H_A#7 A6# D3# H_D#4
V2 A7# D4# A24
H_A#8 W1 B26 H_D#5
H_A#9 A8# D5# H_D#6
T4 A9# D6# A21
H_A#10 W2 B20 H_D#7 1
A10# D7#

1
H_A#11 Y4 C20 H_D#8
H_A#12 A11# D8# H_D#9 C552 R490
Y1 A12# D9# B24
D H_A#13 U1 D24 H_D#10 0.1U_0402_16V4Z @ 10K_0402_5% D
H_A#14 A13# D10# H_D#11 2
AA3 A14# D11# E24 1
H_A#15 Y3 C26 H_D#12 C553

2
H_A#16 A15# D12# H_D#13 U37
AA2 A16# D13# B23
H_A#17 AF4 E23 H_D#14 2200P_0402_50V7K THERMDA 2 1
H_A#18 A17# D14# H_D#15 2 D+ VDD1
AC4 A18# D15# C25
H_A#19 AC7 H23 H_D#16 THERMDC 3 6
H_A#20 A19# D16# H_D#17 D- ALERT#
AC3 A20# D17# G25
H_A#21 AD3 L23 H_D#18 <30,35,40> EC_SMB_CK2 8 4
H_A#22 A21# D18# H_D#19 SCLK THERM#
AE4 A22# D19# M26
H_A#23 AD2 H24 H_D#20 <30,35,40> EC_SMB_DA2 7 5
H_A#24 A23# D20# H_D#21 SDATA GND
AB4 A24# D21# F25
H_A#25 AC6 ADDR GROUP DATA GROUP G24 H_D#22
H_A#26 A25# D22# H_D#23
AD5 A26# D23# J23 ADM1032ARM_RM8
H_A#27 AE2 M23 H_D#24
H_A#28 A27# D24# H_D#25
AD6 A28# D25# J25
H_A#29 AF3 L26 H_D#26 +1.05VS
H_A#30 A29# D26# H_D#27
AE1 A30# D27# N24
H_A#31 AF1 M25 H_D#28
H_REQ#[0..4] A31# D28# H_D#29
<6> H_REQ#[0..4] D29# H26
H_REQ#0 R2 N25 H_D#30
H_REQ#1 REQ0# D30# H_D#31 ITP_TDI R73 150_0402_5%
P3 REQ1# D31# K25 2 1
H_REQ#2 T2 Y26 H_D#32
H_REQ#3 REQ2# D32# H_D#33 ITP_TDO R74
P1 REQ3# D33# AA24 2 1 @ 54.9_0402_1%
H_REQ#4 T1 T25 H_D#34
REQ4# D34# H_D#35 H_CPURST# R72
D35# U23 2 1 @ 54.9_0402_1%
U3 V23 H_D#36
<6> H_ADSTB#0 ADSTB0# D36# H_D#37 ITP_TMS R71 39.2_0603_1%
<6> H_ADSTB#1 AE5 ADSTB1# D37# R24 2 1
R26 H_D#38
C
D38# H_D#39 PRO_CHOT# R77 56_0402_5% C
D39# R23 2 1
A16 AA23 H_D#40
ITP_CLK0 D40# H_D#41 H_PWRGOOD R67 200_0402_5%
A15 ITP_CLK1 D41# U26 2 1
V24 H_D#42
D42# H_D#43 H_IERR# R69 56_0402_5%
<14> CLK_CPU_BCLK B15 BCLK0 D43# U25 2 1
B14 HOST CLK V26 H_D#44
<14> CLK_CPU_BCLK# BCLK1 D44#
Y23 H_D#45
D45# H_D#46
D46# AA26
Y25 H_D#47 +3VS
D47# H_D#48
<6> H_ADS# N2 ADS# D48# AB25
L1 AC23 H_D#49
<6> H_BNR# BNR# D49# H_D#50 ITP_DBRRESET# R70 150_0402_5%
<6> H_BPRI# J3 BPRI# D50# AB24 2 1
N4 AC20 H_D#51
<6> H_BR0# BR0# D51# H_D#52
<6> H_DEFER# L4 DEFER# D52# AC22
H2 AC25 H_D#53
<6> H_DRDY# DRDY# D53# H_D#54
<6> H_HIT# K3 HIT# D54# AD23
K4 CONTROL GROUP AE22 H_D#55 ITP_TRST# R75 2 1 680_0402_5%
<6> H_HITM# H_IERR# HITM# D55# H_D#56
A4 IERR# D56# AF23
J2 AD24 H_D#57 ITP_TCK R76 2 1 27.4_0402_1%
<6> H_LOCK# H_CPURST# LOCK# D57# H_D#58
<6> H_CPURST# B11 RESET# D58# AF20
AE21 H_D#59 TEST1 R68 2 1 @ 1K_0402_5%
D59# H_D#60
D60# AD21
H_RS#[0..2] H_RS#0 H1 AF25 H_D#61 TEST2 R65 2 1 @ 1K_0402_5%
<6> H_RS#[0..2] RS0# D61#
H_RS#1 K1 AF22 H_D#62
H_RS#2 RS1# D62# H_D#63
L2 RS2# D63# AF26
<6> H_TRDY# M3 TRDY#

DINV0# D25 H_DINV#0 <6>

DINV1# J26 H_DINV#1 <6>
B B
C8 BPM0# DINV2# T24 H_DINV#2 <6>
B8 BPM1# DINV3# AD20 H_DINV#3 <6>
A9 BPM2#
C9 H_FERR# 2 1
BPM3# Reserve for debug C677 220P_0402_50V8J
DSTBN0# C23 H_DSTBN#0 <6>
ITP_DBRRESET# A7 K24 C677 close to South Bridge (U13)
DBR# DSTBN1# H_DSTBN#1 <6>
<6> H_DBSY# M2 DBSY# DSTBN2# W25 H_DSTBN#2 <6>
<18> H_DPSLP# B7 DPSLP# DSTBN3# AE24 H_DSTBN#3 <6>
<18> H_DPRSTP# G1 DPRSTP# DSTBP0# C22 H_DSTBP#0 <6>
<6> H_DPWR# C19 DPWR# DSTBP1# L24 H_DSTBP#1 <6>
A10 MISC W24 H_SMI# 2 1
PRDY# DSTBP2# H_DSTBP#2 <6> C678 @ 180P_0402_50V8J
B10 PREQ# DSTBP3# AE25 H_DSTBP#3 <6>
PRO_CHOT# B17 H_INIT# 2 1
PROCHOT# C679 @ 180P_0402_50V8J
H_PWRGOOD E4 PWRGOOD NMI 2 1
<18> H_PWRGOOD
H_CPUSLP# A6 SLP# C675 680P_0402_50V8J
<6,18> H_CPUSLP#
ITP_TCK A13 TCK H_A20M# 2 1
ITP_TDI C12 TDI C2 H_A20M# C681 @ 180P_0402_50V8J
A20M# H_A20M# <18>
ITP_TDO A12 TDO D3 H_FERR# H_INTR 2 1
FERR# H_FERR# <18>
TEST1 C5 TYCO_1612365-1_Dothan A3 H_IGNNE# C682 @ 180P_0402_50V8J
TEST1 IGNNE# H_IGNNE# <18>
TEST2 F23 TEST2 B5 H_INIT# H_IGNNE# 2 1
INIT# H_INIT# <18>
ITP_TMS C11 TMS D1 H_INTR C683 @ 180P_0402_50V8J
LINT0 H_INTR <18>
ITP_TRST# B13 TRST# D4 NMI R614 2 1 0_0402_5% H_STPCLK# 2 1
LINT1 H_NMI <18>
LEGACY CPU C684 @ 180P_0402_50V8J
THERMAL H_PWRGOOD 2 1
THERMDA B18 C6 H_STPCLK# C685 @ 180P_0402_50V8J
THERMDC A18
THERMDA DIODE STPCLK#
B4 H_SMI#
H_STPCLK# <18> Reserve for debug H_CPUSLP# 2 1
THERMDC SMI# H_SMI# <18> C675, C678, C679, C681 ~ C686
C17 C686 @ 180P_0402_50V8J
<6,18> H_THERMTRIP# THERMTRIP# close to CPU (JP13)
A A

THERMDA & THERMDC Trace / Space = 10 / 10 mil

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
Dothan Processor in mFCPGA479
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:59 Sheet 4 of 53
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE +CPU_CORE
JP23B JP23C
330U_D_2VM
R390 1 2 @ 54.9_0402_1% VCCSENSE AE7 A2 1 1 1 F20 T26
R391 1 @ 54.9_0402_1% VSSSENSE VCCSENSE VSS VCC VSS
2 AF6 VSSSENSE VSS A5 F22 VCC VSS U2
A8 + C38 + C64 + C43 G5 U6
VSS VCC VSS
VSS A11 G21 VCC VSS U22
F26 A14 330U_D_2VM H6 U24
VCCA0 VSS 2 2 2 VCC VSS
B1 VCCA1 VSS A17 H22 VCC VSS V1
+VCCA N1 A20 330U_D_2VM J5 V4
VCCA2 VSS VCC VSS
AC26 VCCA3 VSS A23 J21 VCC VSS V5
VSS A26 K22 VCC VSS V21
D
+1.05VS P23 VCCQ0 VSS B3 U5 VCC VSS V25 D
W4 B6 +CPU_CORE V6 W3
VCCQ1 VSS VCC VSS
VSS B9 V22 VCC VSS W6
B12 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M W5 W22
D10 VCCP
Dothan VSS
VSS B16 1 1
C465
1
C463
1 1
C497
1 1 W21
VCC
VCC
VSS
VSS W23
D12 B19 Y6 W26
D14
VCCP
VCCP
VSS
VSS B22
C464 C466 C498 C496
Y22
VCC
VCC
Dothan VSS
VSS Y2
D16 VCCP VSS B25 AA5 VCC VSS Y5
2 2 2 2 2 2 2
1.5V FOR DOTHAN-B E11 VCCP VSS C1
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
AA7 VCC VSS Y21
E13 C4 AA9 Y24

POWER, GROUNG, RESERVED SIGNALS AND NC

VCCP VSS VCC VSS
+1.5VS 1 2 E15 VCCP VSS C7 AA11 VCC VSS AA1
R454 0_1206_5% F10 C10 AA13 AA4
VCCP VSS +CPU_CORE VCC VSS
F12 VCCP VSS C13 AA15 VCC VSS AA6
F14 VCCP VSS C15 AA17 VCC VSS AA8
1 1 F16 C18 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AA19 AA10
VCCP VSS VCC VSS
K6 VCCP VSS C21 1 1 1 1 1 1 1 AA21 VCC VSS AA12
L5 C24 C474 C475 C70 AB6 AA14
C501 C500 VCCP VSS VCC VSS
L21 VCCP VSS D2 AB8 VCC VSS AA16
2 2 C495 C478 C479 C71
M6 VCCP VSS D5 AB10 VCC VSS AA18
0.01U_0402_16V7K 2 2 2 2 2 2 2
M22 VCCP VSS D7 AB12 VCC VSS AA20
10U_0805_6.3V6M N5 D9 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AB14 AA22
VCCP VSS VCC VSS
N21 VCCP VSS D11 AB16 VCC POWER, GROUND VSS AA25
P6 VCCP VSS D13 AB18 VCC VSS AB3
P22 D15 +CPU_CORE AB20 AB5
VCCP VSS VCC VSS
R5 VCCP VSS D17 AB22 VCC VSS AB7
R21 D19 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AC9 AB9
VCCP VSS VCC VSS
T6 VCCP VSS D21 1 1 1 1 1 1 1 AC11 VCC VSS AB11
T22 D23 C435 C485 C494 AC13 AB13
VCCP VSS VCC VSS
U21 VCCP VSS D26 AC15 VCC VSS AB15
C E3 C436 C484 C462 C60 AC17 AB17 C
VSS 2 2 2 2 2 2 2 VCC VSS
VSS E6 AC19 VCC VSS AB19
D6 E8 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AD8 AB21
+CPU_CORE VCC VSS VCC VSS
D8 VCC VSS E10 AD10 VCC VSS AB23
D18 VCC VSS E12 AD12 VCC VSS AB26
D20 E14 +CPU_CORE AD14 AC2
VCC VSS VCC VSS
D22 VCC VSS E16 AD16 VCC VSS AC5
E5 E18 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AD18 AC8
VCC VSS VCC VSS
E7 VCC VSS E20 1 1 1 1 1 1 1 AE9 VCC VSS AC10
E9 E22 C434 C57 C56 AE11 AC12
VCC VSS VCC VSS
E17 VCC VSS E25 AE13 VCC VSS AC14
E19 F1 C84 C81 C80 C55 AE15 AC16
VCC VSS 2 2 2 2 2 2 2 VCC VSS
E21 VCC VSS F4 AE17 VCC VSS AC18
F6 F5 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AE19 AC21
VCC VSS VCC VSS
F8 VCC VSS F7 AF8 VCC VSS AC24
F18 VCC VSS F9 AF10 VCC VSS AD1
F11 +CPU_CORE AF12 AD4
VSS VCC VSS
VSS F13 AF14 VCC VSS AD7
E1 F15 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AF16 AD9
<50> PSI# PSI# VSS VCC VSS
VSS F17 1 1 1 1 1 1 1 AF18 VCC VSS AD11
+1.05VS E2 F19 C78 C54 C79 AD13
<50> CPU_VID0 VID0 VSS VSS
<50> CPU_VID1 F2 VID1 VSS F21 VSS AD15
F3 F24 C83 C59 C82 C58 AD17
<50> CPU_VID2 VID2 VSS VSS
1

2 2 2 2 2 2 2
<50> CPU_VID3 G3 VID3 VSS G2 VSS AD19
R388 G4 G6 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M AD22
<50> CPU_VID4 VID4 VSS VSS
1K_0402_1% H4 G22 M4 AD25
<50> CPU_VID5 VID5 VSS VSS VSS
VSS G23 M5 VSS VSS AE3
G26 M21 AE6
2

GTL_REF0 VSS VSS VSS

1 2 AD26 GTLREF VSS H3 M24 VSS VSS AE8
B R389 2K_0402_1% B
VSS H5 Vcc-core C,uF ESR, mohm ESL,nH N3 VSS VSS AE10
VSS H21 Decoupling N6 VSS VSS AE12
<14> CPU_BSEL0 C16 BSEL0 VSS H25 N22 VSS VSS AE14
<14> CPU_BSEL1 C14 BSEL1 VSS J1 SPCAP,Polymer 3X330uF 7m ohm/2 3.5nH/2 N23 VSS VSS AE16
VSS J4 N26 VSS VSS AE18
COMP0 P25 J6 MLCC 0805 X5R 35X10uF 5m ohm/35 0.6nH/35 P2 AE20
COMP1 COMP0 VSS VSS VSS
P26 COMP1 VSS J22 P5 VSS VSS AE23
COMP2 AB2 J24 P21 AE26
COMP3 COMP2 VSS VSS VSS
AB1 COMP3 VSS K2 P24 VSS VSS AF2
VSS K5 R1 VSS VSS AF5
VSS K21 R4 VSS VSS AF9
VSS K23 R6 VSS VSS AF11
B2 RSVD VSS K26 R22 VSS VSS AF13
C3 RSVD VSS L3 R25 VSS VSS AF15
E26 L6 +1.05VS T3 AF17
RSVD VSS VSS VSS
AF7 RSVD VSS L22 T5 VSS VSS AF19
AC1 L25 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z T21 AF21
RSVD VSS VSS VSS
VSS M1 1 T23 VSS VSS AF24
1 1 1 1 1 1 1 1 1 1
+
TYCO_1612365-1_Dothan C431 C72 C73 C67 C62 C65 C75 C77 C66 C61 C53 TYCO_1612365-1_Dothan
2 2 2 2 2 2 2 2 2 2 2

150U_D2_6.3VM 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

R444 1 2 27.4_0402_1% COMP0

A A
R441 1 2 54.9_0402_1% COMP1

R392 1 2 27.4_0402_1% COMP2

R393 1 2 54.9_0402_1% COMP3

Security Classification Compal Secret Data Compal Electronics, Inc.
TRACE CLOSELY CPU < 0.5' Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title

COMP0, COMP2 layout : Width 18mils and Space 25mils Dothan Processor in mFCPGA479
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
COMP1, COMP3 layout : Space 25mils AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:54 Sheet 5 of 53
5 4 3 2 1
 5 4 3 2 1

H_RS#[0..2] +1.5VS
H_RS#[0..2] <4>
H_A#[3..31]
<4> H_A#[3..31] CLK_DREF_SSC R32 1 2 VGA@ 0_0402_5%
H_REQ#[0..4] H_D#[0..63]
<4> H_REQ#[0..4] H_D#[0..63] <4> CLK_DREF_SSC# R33 1 2 VGA@ 0_0402_5%
U4A
U4B
H_A#3 G9 E4 H_D#0
H_A#4 C9
HA3#
HA4#
Alviso HD0#
HD1# E1 H_D#1
<19> DMI_ITX_MRX_N0
DMI_ITX_MRX_N0 AA31 DMIRXN0 CFG0 G16 CFG0
H_A#5 E9 F4 H_D#2 DMI_ITX_MRX_N1 AB35 H13 MCH_CLKSEL1
HA5# HD2# <19> DMI_ITX_MRX_N1 DMIRXN1 CFG1 MCH_CLKSEL1 <14> +1.05VS
H_A#6 B7 H7 H_D#3 DMI_ITX_MRX_N2 AC31 G14 MCH_CLKSEL0
HA6# HD3# <19> DMI_ITX_MRX_N2 DMIRXN2 CFG2 MCH_CLKSEL0 <14>
D H_A#7 A10 E2 H_D#4 DMI_ITX_MRX_N3 AD35 F16 D
HA7# HD4# <19> DMI_ITX_MRX_N3 DMIRXN3 CFG3
H_A#8 F9 F1 H_D#5 F15
H_A#9 HA8# HD5# H_D#6 DMI_ITX_MRX_P0 CFG4 CFG5 CFG0 R378 1
D8 HA9# HD6# E3 <19> DMI_ITX_MRX_P0 Y31 DMIRXP0 CFG5 G15 2 10K_0402_5%
H_A#10 B10 D3 H_D#7 DMI_ITX_MRX_P1 AA35 E16 CFG6
HA10# HD7# <19> DMI_ITX_MRX_P1 DMIRXP1 CFG6
H_A#11 E10 K7 H_D#8 DMI_ITX_MRX_P2 AB31 D17 CFG7
HA11# HD8# <19> DMI_ITX_MRX_P2 DMIRXP2 CFG7 +2.5VS
H_A#12 G10 F2 H_D#9 DMI_ITX_MRX_P3 AC35 J16
HA12# HD9# <19> DMI_ITX_MRX_P3 DMIRXP3 CFG8
H_A#13 D9 J7 H_D#10 D15 CFG9
H_A#14 HA13# HD10# H_D#11 DMI_MTX_IRX_N0 CFG9
E11 HA14# HD11# J8 <19> DMI_MTX_IRX_N0 AA33 DMITXN0 CFG10 E15
H_A#15 F10 H6 H_D#12 DMI_MTX_IRX_N1 AB37 D14
<19> DMI_MTX_IRX_N1

DMI
H_A#16 HA15# HD12# H_D#13 DMI_MTX_IRX_N2 DMITXN1 CFG11 CFG12 CFG5 R371 1
G11 HA16# HD13# F3 <19> DMI_MTX_IRX_N2 AC33 DMITXN2 CFG12 E14 2 @ 1K_0402_5%
H_A#17 G13 K8 H_D#14 DMI_MTX_IRX_N3 AD37 H12 CFG13
HA17# HD14# <19> DMI_MTX_IRX_N3 DMITXN3 CFG13
H_A#18 C10 H5 H_D#15 C14
H_A#19 HA18# HD15# H_D#16 DMI_MTX_IRX_P0 CFG14

CFG/RSVD
C11 HA19# HD16# H1 <19> DMI_MTX_IRX_P0 Y33 DMITXP0 CFG15 H15
H_A#20 D11 H2 H_D#17 DMI_MTX_IRX_P1 AA37 J15 CFG16 CFG6 R373 1 2 @ 1K_0402_5%
HA20# HD17# <19> DMI_MTX_IRX_P1 DMITXP1 CFG16
H_A#21 C12 K5 H_D#18 DMI_MTX_IRX_P2 AB33 H14
HA21# HD18# <19> DMI_MTX_IRX_P2 DMITXP2 CFG17
H_A#22 B13 K6 H_D#19 DMI_MTX_IRX_P3 AC37 G22 CFG18 CFG7 R361 1 2 @ 1K_0402_5%
HA22# HD19# <19> DMI_MTX_IRX_P3 DMITXP3 CFG18
H_A#23 A12 J4 H_D#20 G23 CFG19
H_A#24 HA23# HD20# H_D#21 CFG19 CFG9 R376 1
F12 HA24# HD21# G3 CFG20 D23 2 @ 1K_0402_5%
H_A#25 G12 H3 H_D#22 AM33 G25
HA25# HD22# <11> DDRA_CLK1 SM_CK0 RSVD21
H_A#26 E12 J1 H_D#23 AL1 G24 CFG12 R382 1 2 @ 1K_0402_5%
HA26# HD23# <11> DDRA_CLK2 SM_CK1 RSVD22
H_A#27 C13 L5 H_D#24 AE11 J17
H_A#28 HA27# HD24# H_D#25 SM_CK2 RSVD23 CFG13 R381 1
B11 HA28# HD25# K4 <12> DDRB_CLK1 AJ34 SM_CK3 RSVD24 A31 2 @ 1K_0402_5%
H_A#29 D13 J5 H_D#26 AF6 A30
HA29# HD26# <12> DDRB_CLK2 SM_CK4 RSVD25
H_A#30 A13 P7 H_D#27 AC10 D26 CFG16 R377 1 2 @ 1K_0402_5%
H_A#31 HA30# HD27# H_D#28 SM_CK5 RSVD26
F13 HA31# HD28# L7 RSVD27 D25
J3 H_D#29 AN33 CFG[17:3]: internal pull-up
HD29# <11> DDRA_CLK1# SM_CK0#

DDR MUXING
A11 P5 H_D#30 AK1
HOST

HPCREQ# HD30# <11> DDRA_CLK2# SM_CK1#

H_REQ#0 A7 L3 H_D#31 AE10
H_REQ#1 HREQ#0 HD31# H_D#32 SM_CK2# CFG18 R46
D7 HREQ#1 HD32# U7 <12> DDRB_CLK1# AJ33 SM_CK3# 1 2 @ 1K_0402_5%
C H_REQ#2 B8 V6 H_D#33 AF5 C
HREQ#2 HD33# <12> DDRB_CLK2# SM_CK4#
H_REQ#3 C7 R6 H_D#34 AD10 CFG19 R45 1 2 @ 1K_0402_5%
H_REQ#4 HREQ#3 HD34# H_D#35 SM_CK5#
A8 HREQ#4 HD35# R5
B9 P3 H_D#36 DDRA_CKE0 AP21 CFG[19:18]: internal pull-down
<4> H_ADSTB#0 HADSTB#0 HD36# <11> DDRA_CKE0 SM_CKE0
E13 T8 H_D#37 DDRA_CKE1 AM21
<4> H_ADSTB#1 HADSTB#1 HD37# <11> DDRA_CKE1 SM_CKE1
R7 H_D#38 DDRB_CKE0 AH21
HD38# <12> DDRB_CKE0 SM_CKE2
AB1 R8 H_D#39 DDRB_CKE1 AK21
<14> CLK_MCH_BCLK# HCLKN HD39# <12> DDRB_CKE1 SM_CKE3
AB2 U8 H_D#40 J23
<14> CLK_MCH_BCLK HCLKP HD40# BM_BUSY# PM_BMBUSY# <19>
R4 H_D#41 DDRA_SCS#0 AN16 J21 EXT_TS#0
HD41# <11> DDRA_SCS#0 SM_CS0# EXT_TS0#
G4 T4 H_D#42 DDRA_SCS#1 AM14 H22 EXT_TS#1
<4> H_DSTBN#0 HDSTBN#0 HD42# <11> DDRA_SCS#1 SM_CS1# EXT_TS1#
K1 T5 H_D#43 DDRB_SCS#0 AH15 F5 H_THERMTRIP#
<4> H_DSTBN#1 HDSTBN#1 HD43# <12> DDRB_SCS#0 SM_CS2# THRMTRIP# H_THERMTRIP# <4,18>
R3 R1 H_D#44 DDRB_SCS#1 AG16 AD30
<4> H_DSTBN#2 HDSTBN#2 HD44# <12> DDRB_SCS#1 SM_CS3# PWROK VGATE <14,19,50>
V3 T3 H_D#45 AE29

CLK PM
<4> H_DSTBN#3 HDSTBN#3 HD45# RSTIN# PLT_RST# <16,17,19,21,22,24,27,34,35>
G5 V8 H_D#46 R352 1@ 2 40.2_0402_1% M_OCDCOMP0 AF22
<4> H_DSTBP#0 HDSTBP#0 HD46# H_D#47 R368 1 SM_OCDCOMP0
<4> H_DSTBP#1 K2 HDSTBP#1 HD47# U6 2 40.2_0402_1% M_OCDCOMP1 AF16 SM_OCDCOMP1
R2 W6 H_D#48 @ AP14 A24 CLK_DREF_96M#
<4> H_DSTBP#2 HDSTBP#2 HD48# SM_ODT0 DREF_CLKN CLK_DREF_96M# <14>
W4 U3 H_D#49 AL15 A23 CLK_DREF_96M
<4> H_DSTBP#3 HDSTBP#3 HD49# SM_ODT1 DREF_CLKP CLK_DREF_96M <14>
H8 V5 H_D#50 AM11 D37 CLK_DREF_SSC
<4> H_DINV#0 HDINV#0 HD50# SM_ODT2 DREF_SSCLKP CLK_DREF_SSC <14>
K3 W8 H_D#51 Reserve for DDR2 AN10 C37 CLK_DREF_SSC#
<4> H_DINV#1 HDINV#1 HD51# SM_ODT3 DREF_SSCLKN CLK_DREF_SSC# <14>
T7 W7 H_D#52
<4> H_DINV#2 HDINV#2 HD52# H_D#53 R384 1
<4> H_DINV#3 U5 HDINV#3 HD53# U2 +DDRVCC 2 80.6_0402_1% M_RCOMPN AK10 SMRCOMPN
U1 H_D#54 R386 1 2 80.6_0402_1% M_RCOMPP AK11 AP37 +2.5VS
HD54# H_D#55 SMVREF SMRCOMPP NC1
HD55# Y5 AF37 SMVREF0 NC2 AN37
H10 Y2 H_D#56 AD1 AP36 EXT_TS#0 R354 1 2 10K_0402_5%
<4> H_CPURST# HCPURST# HD56# SMVREF1 NC3
V4 H_D#57 M_XSLEW AE27 AP2
HD57# H_D#58 SMXSLEWIN NC4 EXT_TS#1 R351 1
<4> H_ADS# F8 HADS# HD58# Y7 AE28 SMXSLEWOUT NC5 AP1 2 10K_0402_5%
B5 W1 H_D#59 M_YSELW AF9 AN1
<4> H_TRDY# HTRDY# HD59# SMYSLEWIN NC6
G6 W3 H_D#60 AF10 B1
<4> H_DPWR# HDPWR# HD60# SMYSLEWOUT NC7
F7 Y3 H_D#61 A2
B <4> H_DRDY# HDRDY# HD61# H_D#62 NC8 B
<4> H_DEFER# E6 HDEFER# HD62# Y6 NC9 B37 Refer to sheet 14 for FSB
H_D#63

NC
F6 HEDRDY# HD63# W2
+1.05VS NC10 A36 CFG[2:0] frequency select
<4> H_HITM# D6 HHITM# NC11 A37
D4 J11 H_VREF Low = DMI x 2
<4> H_HIT# HHIT# HVREF H_XRCOMP R54 2 24.9_0402_1%
B3 C1 1 (10mil:20mil) CFG5 High = DMI x 4
<4> H_LOCK#
<4> H_BR0# E7
HLOCK#
HBREQ0#
HXRCOMP
HXSCOMP C2 H_XSCOMP
H_YRCOMP
R53 1
R56 2
2 54.9_0402_1%
24.9_0402_1%
ALVISO_BGA1257
R3PM@
*
<4> H_BNR# A5 HBNR# HYRCOMP T1 1 Low = DDR-II
D5 L1 H_YSCOMP R55 1 2 54.9_0402_1% CFG6 High = DDR-I
<4> H_BPRI#
<4> H_DBSY# C6
HBPRI#
HDBSY#
HYSCOMP
HXSWING D1 H_XSWING
H_YSWING +DDRVCC
*
<4,18> H_CPUSLP# G8 HCPUSLP# HYSWING P1 Low = DT/Transportable CPU
H_RS#0 A4 CFG7 High = Mobile CPU
H_RS#1 C5
HRS0#
HRS1#
*

1
H_RS#2 B4 H_XRCOMP & H_YRCOMP Trace / Space = 10 / 20 mil CFG9 Low = Reverse Lane
HRS2# R398 High = Normal Operation
R3PM@ALVISO_BGA1257 +1.05VS 1K_0402_1%
*
00 = Reserved
CFG[13:12] 01 = XOR Mode Enabled
2
0.1U_0402_16V4Z SMVREF 10 = All Z Mode Enabled
1

11 = Normal Operation (Default)

R399
221_0603_1% R396
1
C445
1 1 *
CFG16
C450 Low = Disabled
+1.05VS +1.05VS 1K_0402_1% 0.1U_0402_16V4Z (FSB Dynamic High = Enabled
*
2

2 2 ODT)
2

H_YSWING (12mil:10mil)
1

CFG18
1

R387 R395 Low = 1.05V (Default)

100_0603_1% 221_0603_1%
1
C443
R397
(VCC Select) High = 1.5V *
A A
(5mil:15mil) (12mil:10mil) 0.1U_0402_16V4Z 100_0603_1% CFG19
2

2
Low = 1.05V (Default)
*
2

H_VREF H_XSWING (VTT Select) High = 1.2V

1

1 1
C414 R385 C437 R394
Security Classification Compal Secret Data Compal Electronics, Inc.
0.1U_0402_16V4Z 200_0603_1% 0.1U_0402_16V4Z 100_0603_1% 2005/05/06 2006/05/06 Title
2 2 Issued Date Deciphered Date
Alviso HOST(1/5)
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:58 Sheet 6 of 53
5 4 3 2 1
 5 4 3 2 1

DDRA_SDQ[0..63]
<11> DDRA_SDQ[0..63]
DDRA_SDM[0..7]
<11> DDRA_SDM[0..7]
DDRA_SDQS[0..7]
<11> DDRA_SDQS[0..7]
DDRA_SMA[0..13] DDRB_SMA[0..13]
<11> DDRA_SMA[0..13] <12> DDRB_SMA[0..13]
D D

U4C U4D
AK15 AG35 DDRA_SDQ0 AJ15 AE31
<11> DDRA_SBS0 SA_BS0# SADQ0 <12> DDRB_SBS0 SB_BS0# SBDQ0
AK16 AH35 DDRA_SDQ1 AG17 AE32
<11> DDRA_SBS1 SA_BS1# SADQ1 <12> DDRB_SBS1 SB_BS1# SBDQ1
AL21 AL35 DDRA_SDQ2 AG21 AG32
SA_BS2# SADQ2 DDRA_SDQ3 SB_BS2# SBDQ2
SADQ3 AL37 SBDQ3 AG36
DDRA_SDM0 AJ37 AH36 DDRA_SDQ4 AF32 AE34
DDRA_SDM1 SA_DM0 SADQ4 DDRA_SDQ5 SB_DM0 SBDQ4
AP35 SA_DM1 SADQ5 AJ35 AK34 SB_DM1 SBDQ5 AE33
DDRA_SDM2 AL29 AK37 DDRA_SDQ6 AK27 AF31
DDRA_SDM3 SA_DM2 SADQ6 DDRA_SDQ7 SB_DM2 SBDQ6
AP24 SA_DM3 SADQ7 AL34 AK24 SB_DM3 SBDQ7 AF30
DDRA_SDM4 AP9 AM36 DDRA_SDQ8 AJ10 AH33
DDRA_SDM5 SA_DM4 SADQ8 DDRA_SDQ9 SB_DM4 SBDQ8
AP4 SA_DM5 SADQ9 AN35 AK5 SB_DM5 SBDQ9 AH32
DDRA_SDM6 AJ2 AP32 DDRA_SDQ10 AE7 AK31
DDRA_SDM7 SA_DM6 SADQ10 DDRA_SDQ11 SB_DM6 SBDQ10
AD3 SA_DM7 SADQ11 AM31 AB7 SB_DM7 SBDQ11 AG30
AM34 DDRA_SDQ12 AG34
DDRA_SDQS0 SADQ12 DDRA_SDQ13 SBDQ12
AK36 SA_DQS0 SADQ13 AM35 AF34 SB_DQS0 SBDQ13 AG33
DDRA_SDQS1 AP33 AL32 DDRA_SDQ14 AK32 AH31
DDRA_SDQS2 SA_DQS1 SADQ14 DDRA_SDQ15 SB_DQS1 SBDQ14
AN29 SA_DQS2 SADQ15 AM32 AJ28 SB_DQS2 SBDQ15 AJ31
DDRA_SDQS3 AP23 AN31 DDRA_SDQ16 AK23 AK30
DDRA_SDQS4 SA_DQS3 SADQ16 DDRA_SDQ17 SB_DQS3 SBDQ16
AM8 SA_DQS4 SADQ17 AP31 AM10 SB_DQS4 SBDQ17 AJ30
DDRA_SDQS5 AM4 AN28 DDRA_SDQ18 AH6 AH29
DDRA_SDQS6 SA_DQS5 SADQ18 DDRA_SDQ19 SB_DQS5 SBDQ18
AJ1 SA_DQS6 SADQ19 AP28 AF8 SB_DQS6 SBDQ19 AH28
DDRA_SDQS7 AE5 AL30 DDRA_SDQ20 AB4 AK29
SA_DQS7 SADQ20 DDRA_SDQ21 SB_DQS7 SBDQ20
SADQ21 AM30 SBDQ21 AH30
AK35 AM28 DDRA_SDQ22 AF35 AH27
C
SA_DQS0# SADQ22 DDRA_SDQ23 SB_DQS0# SBDQ22 C
AP34 AL28 AK33 AG28

DDR SYSTEM MEMORY B

SA_DQS1# SADQ23 DDRA_SDQ24 SB_DQS1# SBDQ23
AN30 AP27 AK28 AF24
DDR MEMORY SYSTEM A

SA_DQS2# SADQ24 DDRA_SDQ25 SB_DQS2# SBDQ24

AN23 SA_DQS3# SADQ25 AM27 AJ23 SB_DQS3# SBDQ25 AG23
AN8 AM23 DDRA_SDQ26 AL10 AJ22
SA_DQS4# SADQ26 DDRA_SDQ27 SB_DQS4# SBDQ26
AM5 SA_DQS5# SADQ27 AM22 AH7 SB_DQS5# SBDQ27 AK22
AH1 AL23 DDRA_SDQ28 AF7 AH24
SA_DQS6# SADQ28 DDRA_SDQ29 SB_DQS6# SBDQ28
AE4 SA_DQS7# SADQ29 AM24 AB5 SB_DQS7# SBDQ29 AH23
AN22 DDRA_SDQ30 AG22
DDRA_SMA0 SADQ30 DDRA_SDQ31 DDRB_SMA0 SBDQ30
AL17 SA_MA0 SADQ31 AP22 AH17 SB_MA0 SBDQ31 AJ21
DDRA_SMA1 AP17 AM9 DDRA_SDQ32 DDRB_SMA1 AK17 AG10
DDRA_SMA2 SA_MA1 SADQ32 DDRA_SDQ33 DDRB_SMA2 SB_MA1 SBDQ32
AP18 SA_MA2 SADQ33 AL9 AH18 SB_MA2 SBDQ33 AG9
DDRA_SMA3 AM17 AL6 DDRA_SDQ34 DDRB_SMA3 AJ18 AG8
DDRA_SMA4 SA_MA3 SADQ34 DDRA_SDQ35 DDRB_SMA4 SB_MA3 SBDQ34
AN18 SA_MA4 SADQ35 AP7 AK18 SB_MA4 SBDQ35 AH8
DDRA_SMA5 AM18 AP11 DDRA_SDQ36 DDRB_SMA5 AJ19 AH11
DDRA_SMA6 SA_MA5 SADQ36 DDRA_SDQ37 DDRB_SMA6 SB_MA5 SBDQ36
AL19 SA_MA6 SADQ37 AP10 AK19 SB_MA6 SBDQ37 AH10
DDRA_SMA7 AP20 AL7 DDRA_SDQ38 DDRB_SMA7 AH19 AJ9
DDRA_SMA8 SA_MA7 SADQ38 DDRA_SDQ39 DDRB_SMA8 SB_MA7 SBDQ38
AM19 SA_MA8 SADQ39 AM7 AJ20 SB_MA8 SBDQ39 AK9
DDRA_SMA9 AL20 AN5 DDRA_SDQ40 DDRB_SMA9 AH20 AJ7
DDRA_SMA10 SA_MA9 SADQ40 DDRA_SDQ41 DDRB_SMA10 SB_MA9 SBDQ40
AM16 SA_MA10 SADQ41 AN6 AJ16 SB_MA10 SBDQ41 AK6
DDRA_SMA11 AN20 AN3 DDRA_SDQ42 DDRB_SMA11 AG18 AJ4
DDRA_SMA12 SA_MA11 SADQ42 DDRA_SDQ43 DDRB_SMA12 SB_MA11 SBDQ42
AM20 SA_MA12 SADQ43 AP3 AG20 SB_MA12 SBDQ43 AH5
DDRA_SMA13 AM15 AP6 DDRA_SDQ44 DDRB_SMA13 AG15 AK8
SA_MA13 SADQ44 DDRA_SDQ45 SB_MA13 SBDQ44
SADQ45 AM6 SBDQ45 AJ8
AN15 AL4 DDRA_SDQ46 AH14 AJ5
<11> DDRA_SCAS# SA_CAS# SADQ46 <12> DDRB_SCAS# SB_CAS# SBDQ46
AP16 AM3 DDRA_SDQ47 AK14 AK4
<11> DDRA_SRAS# SA_RAS# SADQ47 <12> DDRB_SRAS# SB_RAS# SBDQ47
AF29 AK2 DDRA_SDQ48 AF15 AG5
SA_RCVENIN# SADQ48 DDRA_SDQ49 SB_RCVENIN# SBDQ48
AF28 SA_RCVENOUT# SADQ49 AK3 AF14 SB_RCVENOUT# SBDQ49 AG4
AP15 AG2 DDRA_SDQ50 AH16 AD8
<11> DDRA_SWE# SA_WE# SADQ50 <12> DDRB_SWE# SB_WE# SBDQ50
AG1 DDRA_SDQ51 AD9
B SADQ51 DDRA_SDQ52 SBDQ51 B
SADQ52 AL3 SBDQ52 AH4
AM2 DDRA_SDQ53 AG6
SADQ53 DDRA_SDQ54 SBDQ53
SADQ54 AH3 SBDQ54 AE8
AG3 DDRA_SDQ55 AD7
SADQ55 DDRA_SDQ56 SBDQ55
SADQ56 AF3 SBDQ56 AC5
AE3 DDRA_SDQ57 AB8
SADQ57 DDRA_SDQ58 SBDQ57
SADQ58 AD6 SBDQ58 AB6
AC4 DDRA_SDQ59 AA8
SADQ59 DDRA_SDQ60 SBDQ59
SADQ60 AF2 SBDQ60 AC8
AF1 DDRA_SDQ61 AC7
SADQ61 DDRA_SDQ62 SBDQ61
SADQ62 AD4 SBDQ62 AA4
AD5 DDRA_SDQ63 AA5
SADQ63 SBDQ63

R3PM@ ALVISO_BGA1257 R3PM@

ALVISO_BGA1257

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
Alviso DDR(2/5)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:55 Sheet 7 of 53
5 4 3 2 1
 5 4 3 2 1

+3VS +2.5VS

PCIE_MTX_C_GRX_N[0..15]
<16> PCIE_MTX_C_GRX_N[0..15]

1
PCIE_MTX_C_GRX_P[0..15]
<16> PCIE_MTX_C_GRX_P[0..15]
R36
2.2K_0402_5% PCEI_GTX_C_MRX_N[0..15]
<16> PCEI_GTX_C_MRX_N[0..15]

2
NOVGA@

G
2
PCEI_GTX_C_MRX_P[0..15]
<16> PCEI_GTX_C_MRX_P[0..15]
1 3 LBKLT_EN
<16,35> GMCH_ENBKL

S
D D
Q9 BSS138_SOT23
NOVGA@ U4G
+2.5VS R40 1 2 @ 3K_0402_1% H24 D36 PEG_COMP 1 2 +1.5VS
R349 1 SDVOCTRL_DATA EXP_COMPI
2 @ 3K_0402_1% H25 SDVOCTRL_CLK EXP_ICOMPO D34 R31 24.9_0402_1%
AB29

MISC
<14> CLK_MCH_3GPLL# GCLKN
AC29 E30 PCEI_GTX_C_MRX_N0
<14> CLK_MCH_3GPLL GCLKP EXP_RXN0/SDVO_TVCLKIN#
F34 PCEI_GTX_C_MRX_N1
EXP_RXN1/SDVO_INT# PCEI_GTX_C_MRX_N2
EXP_RXN2/SDVO_FLDSTALL# G30
GMCH_TV_COMPS A15 H34 PCEI_GTX_C_MRX_N3
GMCH_TV_LUMA TVDAC_A EXP_RXN3 PCEI_GTX_C_MRX_N4
<15> GMCH_TV_LUMA C16 TVDAC_B EXP_RXN4 J30
GMCH_TV_CRMA A17 K34 PCEI_GTX_C_MRX_N5
<15> GMCH_TV_CRMA TVDAC_C EXP_RXN5
2 1 TV_REFSET J18 L30 PCEI_GTX_C_MRX_N6
R364 4.99K_0402_1% TV_REFSET EXP_RXN6 PCEI_GTX_C_MRX_N7
2 1 B15 TV_IRTNA EXP_RXN7 M34
R366 0_0402_5% B16 N30 PCEI_GTX_C_MRX_N8
TV_IRTNB EXP_RXN8 PCEI_GTX_C_MRX_N9
B17 P34

TV
TV_IRTNC EXP_RXN9 PCEI_GTX_C_MRX_N10
EXP_RXN10 R30
T34 PCEI_GTX_C_MRX_N11
EXP_RXN11 PCEI_GTX_C_MRX_N12
EXP_RXN12 U30
V34 PCEI_GTX_C_MRX_N13
EXP_RXN13 PCEI_GTX_C_MRX_N14
EXP_RXN14 W30
GMCH_CRT_CLK E24 Y34 PCEI_GTX_C_MRX_N15
<15> GMCH_CRT_CLK DDCCLK EXP_RXN15
GMCH_CRT_DATA E23
<15> GMCH_CRT_DATA DDCDATA
E21 D30 PCEI_GTX_C_MRX_P0
<15> GMCH_CRT_B BLUE EXP_RXP0/SDVO_TVCLKIN
2 1 D21 E34 PCEI_GTX_C_MRX_P1
R355 150_0402_1% BLUE# EXP_RXP1/SDVO_INT PCEI_GTX_C_MRX_P2
<15> GMCH_CRT_G C20 GREEN EXP_RXP2/SDVO_FLDSTALL F30
2 1 B20 G34 PCEI_GTX_C_MRX_P3
R360 150_0402_1% GREEN# EXP_RXP3 PCEI_GTX_C_MRX_P4
<15> GMCH_CRT_R A19 RED EXP_RXP4 H30
2 1 B19 J34 PCEI_GTX_C_MRX_P5
C R367 150_0402_1% RED# EXP_RXP5 PCEI_GTX_C_MRX_P6 C
H21 K30

VGA
<15> GMCH_CRT_VSYNC VSYNC EXP_RXP6
G21 L34 PCEI_GTX_C_MRX_P7
<15> GMCH_CRT_HSYNC HSYNC EXP_RXP7

PCI - EXPRESS GRAPHICS

1 2 REFSET J20 REFSET EXP_RXP8 M30 PCEI_GTX_C_MRX_P8
R359 255_0402_1% N34 PCEI_GTX_C_MRX_P9
EXP_RXP9 PCEI_GTX_C_MRX_P10
EXP_RXP10 P30
R34 PCEI_GTX_C_MRX_P11
EXP_RXP11 PCEI_GTX_C_MRX_P12
EXP_RXP12 T30
U34 PCEI_GTX_C_MRX_P13
EXP_RXP13 PCEI_GTX_C_MRX_P14
EXP_RXP14 V30
W34 PCEI_GTX_C_MRX_P15
EXP_RXP15
E25 LBKLT_CTL
LBKLT_EN F25 E32 PCIE_MTX_GRX_N0 C326 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N0
LCTLA_CLK LBKLT_EN EXP_TXN0/SDVOB_RED# PCIE_MTX_GRX_N1 C16
C23 LCTLA_CLK EXP_TXN1/SDVOB_GREEN# F36 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N1
+2.5VS LCTLB_DATA C22 G32 PCIE_MTX_GRX_N2 C331 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N2
LDDC_CLK LCTLB_DATA EXP_TXN2/SDVOB_BLUE# PCIE_MTX_GRX_N3 C18
F23 LDDC_CLK EXP_TXN3/SDVOB_CLKN H36 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N3
R41 1 2 2.2K_0402_5% GMCH_CRT_CLK LDDC_DATA F22 J32 PCIE_MTX_GRX_N4 C341 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N4
GMCH_ENVDD LDDC_DATA EXP_TXN4/SDVOC_RED# PCIE_MTX_GRX_N5 C20
<16> GMCH_ENVDD F26 LVDD_EN EXP_TXN5/SDVOC_GREEN# K36 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N5
R43 1 2 2.2K_0402_5% GMCH_CRT_DATA LIBG C33 L32 PCIE_MTX_GRX_N6 C357 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N6
LIBG EXP_TXN6/SDVOC_BLUE# PCIE_MTX_GRX_N7 C23
C31 LVBG EXP_TXN7/SDVOC_CLKN M36 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N7
R357 1 2 2.2K_0402_5% LCTLB_DATA F28 N32 PCIE_MTX_GRX_N8 C365 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N8
LVREFH EXP_TXN8 PCIE_MTX_GRX_N9 C26
F27 LVREFL EXP_TXN9 P36 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N9
R44 1 2 2.2K_0402_5% LCTLA_CLK R32 PCIE_MTX_GRX_N10 C374 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N10
GMCH_TXCLK- EXP_TXN10 PCIE_MTX_GRX_N11 C28
<16> GMCH_TXCLK- B30 LACLKN EXP_TXN11 T36 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N11
GMCH_TXCLK+ B29 U32 PCIE_MTX_GRX_N12 C388 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N12
<16> GMCH_TXCLK+ LACLKP EXP_TXN12

LVDS
C25 V36 PCIE_MTX_GRX_N13 C31 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N13
R39 100K_0402_5% LBKLT_EN LBCLKN EXP_TXN13 PCIE_MTX_GRX_N14 C402 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N14
1 2 C24 LBCLKP EXP_TXN14 W32 1 2
Y36 PCIE_MTX_GRX_N15 C36 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_N15
R347 1 1.5K_0402_1% LIBG GMCH_TXOUT0- EXP_TXN15
2 <16> GMCH_TXOUT0- B34 LADATAN0
GMCH_TXOUT1- B33
B <16> GMCH_TXOUT1- LADATAN1 B
R379 1 2 75_0402_1% GMCH_TV_COMPS GMCH_TXOUT2- B32 D32 PCIE_MTX_GRX_P0 C317 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P0
<16> GMCH_TXOUT2- LADATAN2 EXP_TXP0/SDVOB_RED
E36 PCIE_MTX_GRX_P1 C14 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P1
R370 1 150_0402_1% GMCH_TV_LUMA EXP_TXP1/SDVOB_GREEN PCIE_MTX_GRX_P2 C329
2 EXP_TXP2/SDVOB_BLUE F32 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P2
GMCH_TXOUT0+ A34 G36 PCIE_MTX_GRX_P3 C17 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P3
<16> GMCH_TXOUT0+ LADATAP0 EXP_TXP3/SDVOB_CLKP
R372 1 2 150_0402_1% GMCH_TV_CRMA GMCH_TXOUT1+ A33 H32 PCIE_MTX_GRX_P4 C335 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P4
<16> GMCH_TXOUT1+ LADATAP1 EXP_TXP4/SDVOC_RED
GMCH_TXOUT2+ B31 J36 PCIE_MTX_GRX_P5 C19 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P5
<16> GMCH_TXOUT2+ LADATAP2 EXP_TXP5/SDVOC_GREEN
K32 PCIE_MTX_GRX_P6 C347 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P6
EXP_TXP6/SDVOC_BLUE PCIE_MTX_GRX_P7 C22 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P7
EXP_TXP7/SDVOC_CLKP L36 1 2
M32 PCIE_MTX_GRX_P8 C362 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P8
EXP_TXP8 PCIE_MTX_GRX_P9 C24
C29 LBDATAN0 EXP_TXP9 N36 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P9
D28 P32 PCIE_MTX_GRX_P10 C371 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P10
LBDATAN1 EXP_TXP10 PCIE_MTX_GRX_P11 C27 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P11
C27 LBDATAN2 EXP_TXP11 R36 1 2
T32 PCIE_MTX_GRX_P12 C383 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P12
+2.5VS EXP_TXP12 PCIE_MTX_GRX_P13 C29
EXP_TXP13 U36 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P13
+3VS V32 PCIE_MTX_GRX_P14 C400 1 2 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P14
EXP_TXP14 PCIE_MTX_GRX_P15 C34 VGA@ 0.1U_0402_16V4Z PCIE_MTX_C_GRX_P15
C28 LBDATAP0 EXP_TXP15 W36 1 2
D27 LBDATAP1
2

C26 LBDATAP2
R332 R327
2.2K_0402_5% 4.7K_0402_5%
2
G

NOVGA@ NOVGA@
R3PM@ ALVISO_BGA1257
1

LDDC_CLK 3 1 GMCH_LCD_CLK
GMCH_LCD_CLK <16>
S

Q46
NOVGA@ BSS138_SOT23

A +2.5VS A
+3VS
2

R28 R25
2.2K_0402_5% 4.7K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
2
G

NOVGA@ NOVGA@ 2005/05/06 2006/05/06 Title

Issued Date Deciphered Date
Alviso PCI-E(3/5)
1

LDDC_DATA 3 1 GMCH_LCD_DATA
GMCH_LCD_DATA <16> THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
S

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Q6 1.0
NOVGA@ BSS138_SOT23
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:55 Sheet 8 of 53
5 4 3 2 1
 5 4 3 2 1

+1.05VS
4000mA
U4F C310
U4E 0.1U_0402_16V4Z C311 2.2U_0603_6.3V6K
0.1U_0402_16V4Z 0.1U_0402_16V4Z
+1.05VS K13 AM37 V1.8_DDR_CAP1 2 1 0.1U_0402_16V4Z
VTT0 VCCSM0 V1.8_DDR_CAP2
+1.05VS T29 VCC0 VCCA_TVDACA0 F17 +3VS_DAC J13 VTT1 VCCSM1 AH37 2 1 1 1 1 1 1 1
R29 E17 K12 AP29 V1.8_DDR_CAP5 2 1 C348 C339 C426
VCC1 VCCA_TVDACA1 VTT2 VCCSM2 C334
N29 VCC2 VCCA_TVDACB0 D18 W11 VTT3 VCCSM3 AD28 +DDRVCC
M29 C18 120mA V11 AD27 0.1U_0402_16V4Z C369 C406 C418
VCC3 VCCA_TVDACB1 VTT4 VCCSM4 2 2 2 2 2 2
K29 VCC4 VCCA_TVDACC0 F18 U11 VTT5 VCCSM5 AC27
J29 E18 T11 AP26 22U_1206_16V4Z_V1
VCC5 VCCA_TVDACC1 VTT6 VCCSM6 2.2U_0603_6.3V6K 0.1U_0402_16V4Z
D V28 R11 AN26 D
U28
T28
VCC6
VCC7
VCC8 POWER VCCA_TVBG
VSSA_TVBG
H18
G18
P11
N11
VTT7
VTT8
VTT9
POWER VCCSM7
VCCSM8
VCCSM9
AM26
AL26 +DDRVCC
2200mA
R28 VCC9 M11 VTT10 VCCSM10 AK26
P28 D19 L11 AJ26 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VCC10 VCCD_TVDAC VTT11 VCCSM11
N28 VCC11 VCCDQ_TVDAC H17 24mA K11 VTT12 VCCSM12 AH26 1
M28 VCC12 W10 VTT13 VCCSM13 AG26 1 1 1 1 1 1 1 1
L28 B26 V10 AF26 + C355 C353 C354 C401
VCC13 VCCD_LVDS0 +1.5VS VTT14 VCCSM14
K28 VCC14 VCCD_LVDS1 B25 U10 VTT15 VCCSM15 AE26
J28 A25 60mA T10 AP25 C483 C413 C409 C407 C351
VCC15 VCCD_LVDS2 VTT16 VCCSM16 330U_D2E_2.5VM 2 2 2 2 2 2 2 2 2
H28 VCC16 R10 VTT17 VCCSM17 AN25
G28 VCC17 VCCA_LVDS A35 +2.5VS P10 VTT18 VCCSM18 AM25
V27 10mA N10 AL25 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VCC18 VTT19 VCCSM19
U27 VCC19 VCCHV0 B22 M10 VTT20 VCCSM20 AK25
T27 VCC20 VCCHV1 B21 2mA K10 VTT21 VCCSM21 AJ25
R27 VCC21 VCCHV2 A21 J10 VTT22 VCCSM22 AH25
P27 VCC22 Y9 VTT23 VCCSM23 AG25
+2.5VS
N27 VCC23 VCCTX_LVDS0 B28 W9 VTT24 VCCSM24 AF25 VCCHV(Ball A21,B21,B22)
M27 VCC24 VCCTX_LVDS1 A28 60mA U9 VTT25 VCCSM25 AE25
L27 VCC25 VCCTX_LVDS2 A27 R9 VTT26 VCCSM26 AE24
K27 VCC26 P9 VTT27 VCCSM27 AE23
J27 VCC27 VCCA_SM0 AF20 +1.5VS_DDRDLL N9 VTT28 VCCSM28 AE22 1 1 1 1 1 1
H27 AP19 M9 AE21 C315 C324 C373 C368 C340 C344
VCC28 VCCA_SM1 VTT29 VCCSM29
K26 VCC29 VCCA_SM2 AF19 L9 VTT30 VCCSM30 AE20
H26 VCC30 VCCA_SM3 AF18 J9 VTT31 VCCSM31 AE19
2 0.1U_0402_16V4Z 2 0.01U_0402_16V7K 2 4.7U_0805_10V4Z 2 0.1U_0402_16V4Z 2 4.7U_0805_10V4Z 2 0.1U_0402_16V4Z
K25 VCC31 N8 VTT32 VCCSM32 AE18
J25 VCC32 VCC3G0 AE37 +1.5VS_PEG M8 VTT33 VCCSM33 AE17
K24 VCC33 VCC3G1 W37 N7 VTT34 VCCSM34 AE16
K23 VCC34 VCC3G2 U37 M7 VTT35 VCCSM35 AE15
C K22 VCC35 VCC3G3 R37 N6 VTT36 VCCSM36 AE14 VCCA_LVDS (Ball A35) VCCTX_LVDS(Ball A27,A28,B28) C
K21 VCC36 VCC3G4 N37 M6 VTT37 VCCSM37 AP13 VCCA_CRTDAC(Ball F19,E19)
W20 VCC37 VCC3G5 L37 A6 VTT38 VCCSM38 AN13
U20 J37 N5 AM13 +2.5VS_DAC R375
VCC38 VCC3G6 C44 1 VTT39 VCCSM39 0_0603_5%
T20 VCC39 M5 VTT40 VCCSM40 AL13
K20 0.47U_0603_16V4Z N4 AK13 1 2 +2.5VS
VCC40 VTT41 VCCSM41
V19 VCC41 M4 VTT42 VCCSM42 AJ13
U19 VCC42 VCCA_3GPLL0 Y29 +1.5VS_3GPLL N3 VTT43 VCCSM43 AH13 1 1 1 1
2 C394 C381 C376 C380
K19 VCC43 VCCA_3GPLL1 Y28 M3 VTT44 VCCSM44 AG13
W18 VCC44 VCCA_3GPLL2 Y27 N2 VTT45 VCCSM45 AF13
V18 VCC45 M2 VTT46 VCCSM46 AE13
2 4.7U_0805_10V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.022U_0402_16V7K
T18 VCC46 B2 VTT47 VCCSM47 AP12
K18 VCC47 VCCA_3GBG F37 +2.5VS_3GBG V1 VTT48 VCCSM48 AN12
K17 VCC48 VSSA_3GBG G37 N1 VTT49 VCCSM49 AM12
1 M1 VTT50 VCCSM50 AL12
+1.5VS AC1 VCCD_HMPLL1 VCC_SYNC H20 +2.5VS_DAC G1 VTT51 VCCSM51 AK12 VCC_SYNC(Ball H20)
AC2 VCCD_HMPLL2 VCCSM52 AJ12
+1.5VS_DPLLA +1.5VS_DPLLA B23 F19 70mA C46 AH12
+1.5VS_DPLLB VCCA_DPLLA VCCA_CRTDAC0 0.47U_0603_16V4Z 2 VCCSM53
+1.5VS_DPLLB
+1.5VS_HPLL
C35 VCCA_DPLLB VCCA_CRTDAC1 E19 VCCSM54 AG12
+1.5VS VCCD_TVDAC (Ball D19)
+1.5VS_HPLL AA1 VCCA_HPLL VSSA_CRTDAC G19 1 VCCSM55 AF12
+1.5VS_MPLL +1.5VS_MPLL AA2 AE12 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VCCA_MPLL VCCSM56
VCCSM57 AD11
C49 AC11
R3PM@ ALVISO_BGA1257 0.22U_0402_10V4Z 2 VCCSM58
VCCSM59 AB11 1 1 1 1 1 1
1 AB10 C42 C21 C350 C359 C375 C395 C397
VCCSM60 0.1U_0402_16V4Z C439
VCCSM61 AB9
VCCSM62 AP8 V1.8_DDR_CAP6 2 1 0.1U_0402_16V4Z
C51 AM1 V1.8_DDR_CAP4 2 1 4.7U_0805_10V4Z 2 2 2 2 2 2
0.22U_0402_10V4Z 2 VCCSM63
VCCSM64 AE1 V1.8_DDR_CAP3 2 1
B C438 0.1U_0402_16V4Z 0.022U_0402_16V7K 0.022U_0402_16V7K B
0.1U_0402_16V4Z
R3PM@ ALVISO_BGA1257 VCCD_LVDS(Ball A25,B25,B26) VCCDQ_TVDAC (Ball H17)
+1.05VS

+1.5VS_DPLLA +1.5VS_DPLLB +1.5VS_DDRDLL +1.5VS_PEG

950mA
R348 R37 R42 1000mA
60mA 0_0603_5% 60mA 0_0603_5% 0_0603_5% R30
1 2 +1.5VS 1 2 +1.5VS 1 2 +1.5VS 4.7U_0805_10V4Z 1 2470U_D2_2.5VM +1.5VS 1 1 1 1
0_1206_5% 1 C412 C405 C390 C372
1 1 1 1 1 1 1 1 1

2
C358 C364 C15 C323 C25 C378 C12 C307 C13 + C11
D28 2 2.2U_0603_6.3V6K 2 2.2U_0603_6.3V6K 2 2.2U_0603_6.3V6K 2 2.2U_0603_6.3V6K

2 22U_1206_16V4Z_V1 2 0.1U_0402_16V4Z 2 22U_1206_16V4Z_V1 2 0.1U_0402_16V4Z 2 22U_1206_16V4Z_V1 2 0.1U_0402_16V4Z 2 2 2 4.7U_0805_10V4Z 2 @ RB751V_SOD323

1
22U_1206_16V4Z_V1 VCCA_TVDAC VCCA_TVBG (Ball H18)
+3VS +3VS_DAC
120mA
Reserve for debug L1
CHB1608U301_0603
1 2 1 2
0.15mA R575 @ 1K_0402_5%
+1.5VS_3GPLL R337 R336 +2.5VS_3GBG
1 1 1 1 1
0.5_0603_1% 0_0603_5% C391 C392 C386 C384
+1.5VS_HPLL R57 +1.5VS_MPLL R400 1 2+3GPLL 1 2 1 2 + C32
+1.5VS +2.5VS
60mA 0_0603_5% 60mA 0_0603_5% 1 R338 0_0603_5% 150U_D2_6.3VM
2 2 2 2
A 1 2 +1.5VS 1 2 +1.5VS 1 1 A
C306 C309 2
1 1 1 1 C343 0.1U_0402_16V4Z 0.1U_0402_16V4Z
C52 C50 C451 C440 2
2 10U_1206_16V4Z 2 0.1U_0402_16V4Z 0.022U_0402_16V7K 0.1U_0402_16V4Z 0.022U_0402_16V7K
2 22U_1206_16V4Z_V1 2 0.1U_0402_16V4Z 2 22U_1206_16V4Z_V1 2 0.1U_0402_16V4Z
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
Alviso POWER(4/5)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:54 Sheet 9 of 53
5 4 3 2 1
 5 4 3 2 1

U4H
U4I U4J
+1.05VS L12 VTT_NCTF17 VCCSM_NCTF31 AB12 +DDRVCC
M12 VTT_NCTF16 VCCSM_NCTF30 AC12 Y1 VSS271 AL24 VSS267
N12 VTT_NCTF15 VCCSM_NCTF29 AD12 D2 VSS270 VSSALVDS B36 AN24 VSS266 VSS67 AC32
P12 VTT_NCTF14 VCCSM_NCTF28 AB13 G2 VSS269 A26 VSS265 VSS66 AD32
R12 VTT_NCTF13 VCCSM_NCTF27 AC13 J2 VSS268 VSS195 AA11 E26 VSS264 VSS65 AJ32
T12 VTT_NCTF12 VCCSM_NCTF26 AD13 L2 VSS260 VSS194 AF11 G26 VSS263 VSS64 AN32
U12 VTT_NCTF11 VCCSM_NCTF25 AC14 P2 VSS259 VSS193 AG11 J26 VSS262 VSS63 D33
D V12 VTT_NCTF10 VCCSM_NCTF24 AD14 T2 VSS258 VSS192 AJ11 B27 VSS261 VSS62 E33 D
W12 VTT_NCTF9 VCCSM_NCTF23 AC15 V2 VSS257 VSS191 AL11 E27 VSS129 VSS61 F33
L13 VTT_NCTF8 VCCSM_NCTF22 AD15 AD2 VSS256 VSS190 AN11 G27 VSS128 VSS60 G33
M13 VTT_NCTF7 VCCSM_NCTF21 AC16 AE2 VSS255 VSS189 B12 W27 VSS127 VSS59 H33
N13
P13
R13
T13
U13
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VCCSM_NCTF20
VCCSM_NCTF19
VCCSM_NCTF18
VCCSM_NCTF17
AD16
AC17
AD17
AC18
AD18
AH2
AL2
AN2
A3
C3
VSS254
VSS253
VSS252
VSS251
VSS
VSS188
VSS187
VSS186
VSS185
D12
J12
A14
B14
F14
AA27
AB27
AF27
AG27
AJ27
VSS126
VSS125
VSS124
VSS123
VSS VSS58
VSS57
VSS56
VSS55
J33
K33
L33
M33
N33
VTT_NCTF2 VCCSM_NCTF16 VSS250 VSS184 VSS122 VSS54
V13 VTT_NCTF1 VCCSM_NCTF15 AC19 AA3 VSS249 VSS183 J14 AL27 VSS121 VSS53 P33
W13 VTT_NCTF0 VCCSM_NCTF14 AD19 AB3 VSS248 VSS182 K14 AN27 VSS120 VSS52 R33
VCCSM_NCTF13 AC20 AC3 VSS247 VSS181 AG14 E28 VSS119 VSS51 T33
VCCSM_NCTF12 AD20 AJ3 VSS246 VSS180 AJ14 W28 VSS118 VSS50 U33
Y12 VSS_NCTF68 VCCSM_NCTF11 AC21 C4 VSS245 VSS179 AL14 AA28 VSS117 VSS49 V33
AA12 VSS_NCTF67 VCCSM_NCTF10 AD21 H4 VSS244 VSS178 AN14 AB28 VSS116 VSS48 W33
Y13 VSS_NCTF66 VCCSM_NCTF9 AC22 L4 VSS243 VSS177 C15 AC28 VSS115 VSS47 AD33
AA13 VSS_NCTF65 VCCSM_NCTF8 AD22 P4 VSS242 VSS176 K15 A29 VSS114 VSS46 AF33
L14 VSS_NCTF64 VCCSM_NCTF7 AC23 U4 VSS241 VSS175 A16 D29 VSS113 VSS45 AL33
M14 VSS_NCTF63 VCCSM_NCTF6 AD23 Y4 VSS240 VSS174 D16 E29 VSS112 VSS44 C34
N14 VSS_NCTF62 VCCSM_NCTF5 AC24 AF4 VSS239 VSS173 H16 F29 VSS111 VSS43 AA34
P14 VSS_NCTF61 VCCSM_NCTF4 AD24 AN4 VSS238 VSS172 K16 G29 VSS110 VSS42 AB34
R14 VSS_NCTF60 VCCSM_NCTF3 AC25 E5 VSS237 VSS171 AL16 H29 VSS109 VSS41 AC34
T14 VSS_NCTF59 VCCSM_NCTF2 AD25 W5 VSS236 VSS170 C17 L29 VSS108 VSS40 AD34
U14 VSS_NCTF58 VCCSM_NCTF1 AC26 AL5 VSS235 VSS169 G17 P29 VSS107 VSS39 AH34
V14 VSS_NCTF57 VCCSM_NCTF0 AD26 AP5 VSS234 VSS168 AF17 U29 VSS106 VSS38 AN34
W14 VSS_NCTF56 B6 VSS233 VSS167 AJ17 V29 VSS105 VSS37 B35
Y14 VSS_NCTF55 VCC_NCTF78 L17 +1.05VS J6 VSS232 VSS166 AN17 W29 VSS104 VSS36 D35
AA14 VSS_NCTF54 VCC_NCTF77 M17 L6 VSS231 VSS165 A18 AA29 VSS103 VSS35 E35
AB14 VSS_NCTF53 VCC_NCTF76 N17 P6 VSS230 VSS164 B18 AD29 VSS102 VSS34 F35
C L15 P17 T6 U18 AG29 G35 C
VSS_NCTF52 VCC_NCTF75 VSS229 VSS163 VSS101 VSS33
M15 T17 AA6 AL18 AJ29 H35
NCTF

VSS_NCTF51 VCC_NCTF74 VSS228 VSS162 VSS100 VSS32

N15 VSS_NCTF50 VCC_NCTF73 U17 AC6 VSS227 VSS161 C19 AM29 VSS99 VSS31 J35
P15 VSS_NCTF49 VCC_NCTF72 V17 AE6 VSS226 VSS160 H19 C30 VSS98 VSS30 K35
R15 VSS_NCTF48 VCC_NCTF71 W17 AJ6 VSS225 VSS159 J19 Y30 VSS97 VSS29 L35
T15 VSS_NCTF47 VCC_NCTF70 L18 G7 VSS224 VSS158 T19 AA30 VSS96 VSS28 M35
U15 VSS_NCTF46 VCC_NCTF69 M18 V7 VSS223 VSS157 W19 AB30 VSS95 VSS27 N35
V15 VSS_NCTF45 VCC_NCTF68 N18 AA7 VSS222 VSS156 AG19 AC30 VSS94 VSS26 P35
W15 VSS_NCTF44 VCC_NCTF67 P18 AG7 VSS221 VSS155 AN19 AE30 VSS93 VSS25 R35
Y15 VSS_NCTF43 VCC_NCTF66 R18 AK7 VSS220 VSS154 A20 AP30 VSS92 VSS24 T35
AA15 VSS_NCTF42 VCC_NCTF65 Y18 AN7 VSS219 VSS153 D20 D31 VSS91 VSS23 U35
AB15 VSS_NCTF41 VCC_NCTF64 L19 C8 VSS218 VSS152 E20 E31 VSS90 VSS22 V35
L16 VSS_NCTF40 VCC_NCTF63 M19 E8 VSS217 VSS151 F20 F31 VSS89 VSS21 W35
M16 VSS_NCTF39 VCC_NCTF62 N19 L8 VSS216 VSS150 G20 G31 VSS88 VSS20 Y35
N16 VSS_NCTF38 VCC_NCTF61 P19 P8 VSS215 VSS149 V20 H31 VSS87 VSS19 AE35
P16 VSS_NCTF37 VCC_NCTF60 R19 Y8 VSS214 VSS148 AK20 J31 VSS86 VSS18 C36
R16 VSS_NCTF36 VCC_NCTF59 Y19 AL8 VSS213 VSS147 C21 K31 VSS85 VSS17 AA36
T16 VSS_NCTF35 VCC_NCTF58 L20 A9 VSS212 VSS146 F21 L31 VSS84 VSS16 AB36
U16 VSS_NCTF34 VCC_NCTF57 M20 H9 VSS211 VSS145 AF21 M31 VSS83 VSS15 AC36
V16 VSS_NCTF33 VCC_NCTF56 N20 K9 VSS210 VSS144 AN21 N31 VSS82 VSS14 AD36
W16 VSS_NCTF32 VCC_NCTF55 P20 T9 VSS209 VSS143 A22 P31 VSS81 VSS13 AE36
Y16 VSS_NCTF31 VCC_NCTF54 R20 V9 VSS208 VSS142 D22 R31 VSS80 VSS12 AF36
AA16 VSS_NCTF30 VCC_NCTF53 Y20 AA9 VSS207 VSS141 E22 T31 VSS79 VSS11 AJ36
AB16 VSS_NCTF29 VCC_NCTF52 L21 AC9 VSS206 VSS140 J22 U31 VSS78 VSS10 AL36
R17 VSS_NCTF28 VCC_NCTF51 M21 AE9 VSS205 VSS139 AH22 V31 VSS77 VSS9 AN36
Y17 VSS_NCTF27 VCC_NCTF50 N21 AH9 VSS204 VSS138 AL22 W31 VSS76 VSS8 E37
AA17 VSS_NCTF26 VCC_NCTF49 P21 AN9 VSS203 VSS137 H23 AD31 VSS75 VSS7 H37
AB17 VSS_NCTF25 VCC_NCTF48 T21 D10 VSS202 VSS136 AF23 AG31 VSS74 VSS6 K37
AA18 VSS_NCTF24 VCC_NCTF47 U21 L10 VSS201 VSS135 B24 AL31 VSS73 VSS5 M37
B B
AB18 VSS_NCTF23 VCC_NCTF46 V21 Y10 VSS200 VSS134 D24 A32 VSS72 VSS4 P37
AA19 VSS_NCTF22 VCC_NCTF45 W21 AA10 VSS199 VSS133 F24 C32 VSS71 VSS3 T37
AB19 VSS_NCTF21 VCC_NCTF44 L22 F11 VSS198 VSS132 J24 Y32 VSS70 VSS2 V37
AA20 VSS_NCTF20 VCC_NCTF43 M22 H11 VSS197 VSS131 AG24 AA32 VSS69 VSS1 Y37
AB20 VSS_NCTF19 VCC_NCTF42 N22 Y11 VSS196 VSS130 AJ24 AB32 VSS68 VSS0 AG37
R21 VSS_NCTF18 VCC_NCTF41 P22
Y21 VSS_NCTF17 VCC_NCTF40 R22
AA21 VSS_NCTF16 VCC_NCTF39 T22
AB21 U22 R3PM@ ALVISO_BGA1257 ALVISO_BGA1257
VSS_NCTF15 VCC_NCTF38 R3PM@
Y22 VSS_NCTF14 VCC_NCTF37 V22
AA22 VSS_NCTF13 VCC_NCTF36 W22
AB22 VSS_NCTF12 VCC_NCTF35 L23
Y23 VSS_NCTF11 VCC_NCTF34 M23
AA23 VSS_NCTF10 VCC_NCTF33 N23
AB23 VSS_NCTF9 VCC_NCTF32 P23
Y24 VSS_NCTF8 VCC_NCTF31 R23
AA24 VSS_NCTF7 VCC_NCTF30 T23
AB24 VSS_NCTF6 VCC_NCTF29 U23
Y25 VSS_NCTF5 VCC_NCTF28 V23
AA25 VSS_NCTF4 VCC_NCTF27 W23
AB25 VSS_NCTF3 VCC_NCTF26 L24
Y26 VSS_NCTF2 VCC_NCTF25 M24
AA26 VSS_NCTF1 VCC_NCTF24 N24
AB26 VSS_NCTF0 VCC_NCTF23 P24
VCC_NCTF22 R24
+1.05VS V25 VCC_NCTF10 VCC_NCTF21 T24
W25 VCC_NCTF9 VCC_NCTF20 U24
L26 VCC_NCTF8 VCC_NCTF19 V24
A M26 VCC_NCTF7 VCC_NCTF18 W24 A
N26 VCC_NCTF6 VCC_NCTF17 L25
P26 VCC_NCTF5 VCC_NCTF16 M25
R26 VCC_NCTF4 VCC_NCTF15 N25
T26 VCC_NCTF3 VCC_NCTF14 P25
U26 VCC_NCTF2 VCC_NCTF13 R25
V26 T25
W26
VCC_NCTF1
VCC_NCTF0
VCC_NCTF12
VCC_NCTF11 U25
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title

R3PM@ ALVISO_BGA1257 Alviso POWER(5/5)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:54 Sheet 10 of 53
5 4 3 2 1
 5 4 3 2 1

+DDRVCC +DDRVCC +DIMM_VREF +DDRVCC

JP7
1 VREF VREF 2

1
3 4 R321 RP1 RP3 +DDRVTT
DDRA_DQ1 VSS VSS DDRA_DQ0 DDRA_SDQ0 DDRA_DQ0 DDRA_SDQ6 DDRA_DQ6
5 DQ0 DQ4 6 1 8 1 8
DDRA_DQ5 7 8 DDRA_DQ4 DDRA_SDQ1 2 7 DDRA_DQ1 DDRA_SDQ7 2 7 DDRA_DQ7
DQ1 DQ5 1K_0402_1% DDRA_SDQ4 DDRA_DQ4 DDRA_SDQ2 DDRA_DQ2
9 VDD VDD 10 3 6 3 6
DDRA_DQS0 11 12 DDRA_DM0 DDRA_SDQ5 4 5 DDRA_DQ5 DDRA_SDQ3 4 5 DDRA_DQ3

2
DDRA_DQ7 DQS0 DM0 DDRA_DQ6
13 DQ2 DQ6 14
15 16 10_0804_8P4R_5% 10_0804_8P4R_5%
VSS VSS

1
D DDRA_DQ3 17 18 DDRA_DQ2 1 R322 RP2 RP57 D
DDRA_DQ13 DQ3 DQ7 DDRA_DQ8 DDRA_SDM0
19 DQ8 DQ12 20 1 4 DDRA_DM0 RP4 DDRA_SMA4 4 5
21 22 DDRA_SDQS0 2 3 DDRA_DQS0 DDRA_SDQ8 1 8 DDRA_DQ8 DDRA_SMA6 3 6
DDRA_DQ9 VDD VDD DDRA_DQ12 1K_0402_1% DDRA_SDQ13 DDRA_DQ13 DDRA_SMA8
23 DQ9 DQ13 24 2 7 2 7
DDRA_DQS1 DDRA_DM1 2 10_0404_4P2R_5% DDRA_SDQ12 DDRA_DQ12 DDRA_SMA11
25 26 3 6 1 8

2
DQS1 DM1 DDRA_SDQ9 DDRA_DQ9
27 VSS VSS 28 4 5
DDRA_DQ15 29 30 DDRA_DQ14 56_0804_8P4R_5%
DDRA_DQ11 DQ10 DQ14 DDRA_DQ10 C298 RP6 10_0804_8P4R_5%
31 DQ11 DQ15 32
33 34 0.1U_0402_16V4Z DDRA_SDQ14 1 8 DDRA_DQ14
VDD VDD DDRA_SDQ15 DDRA_DQ15
<6> DDRA_CLK1 35 CK0 VDD 36 2 7
37 38 DDRA_SDQ10 3 6 DDRA_DQ10 RP5 RP60
<6> DDRA_CLK1# CK0# VSS
39 40 DDRA_SDQ11 4 5 DDRA_DQ11 DDRA_SDM1 1 4 DDRA_DM1 DDRA_SRAS# 4 5
VSS VSS DDRA_SDQS1 DDRA_DQS1 DDRA_SBS1
2 3 3 6
10_0804_8P4R_5% DDRA_SMA0 2 7
DDRA_DQ16 41 42 DDRA_DQ17 10_0404_4P2R_5% DDRA_SMA2 1 8
DDRA_DQ20 DQ16 DQ20 DDRA_DQ21
43 DQ17 DQ21 44
45 46 RP7 RP9 56_0804_8P4R_5%
DDRA_DQS2 VDD VDD DDRA_DM2 DDRA_SDQ16 DDRA_DQ16 DDRA_SDQ18 DDRA_DQ18
47 DQS2 DM2 48 1 8 1 8
DDRA_DQ18 49 50 DDRA_DQ19 DDRA_SDQ17 2 7 DDRA_DQ17 DDRA_SDQ19 2 7 DDRA_DQ19
DQ18 DQ22 DDRA_SDQ20 DDRA_DQ20 DDRA_SDQ22 DDRA_DQ22
51 VSS VSS 52 3 6 3 6
DDRA_DQ22 53 54 DDRA_DQ23 DDRA_SDQ21 4 5 DDRA_DQ21 DDRA_SDQ23 4 5 DDRA_DQ23 56_0404_4P2R_5%
DDRA_DQ25 DQ19 DQ23 DDRA_DQ24 DDRA_SCAS#
55 DQ24 DQ28 56 1 4
57 58 10_0804_8P4R_5% 10_0804_8P4R_5% DDRA_SCS#1 2 3
DDRA_DQ29 VDD VDD DDRA_DQ28
59 DQ25 DQ29 60
DDRA_DQS3 61 62 DDRA_DM3 RP10 RP62
DQS3 DM3 DDRA_SDQ24 DDRA_DQ24
63 64 RP8 1 8
DDRA_DQ27 VSS VSS DDRA_DQ26 DDRA_SDQS2 DDRA_DQS2 DDRA_SDQ25 DDRA_DQ25 56_0804_8P4R_5%
65 DQ26 DQ30 66 1 4 2 7
DDRA_DQ30 67 68 DDRA_DQ31 DDRA_SDM2 2 3 DDRA_DM2 DDRA_SDQ28 3 6 DDRA_DQ28 DDRA_SMA5 1 8
DQ27 DQ31 DDRA_SDQ29 DDRA_DQ29 DDRA_SMA7
69 VDD VDD 70 4 5 2 7
C 71 72 10_0404_4P2R_5% DDRA_SMA9 3 6 C
CB0 CB4 10_0804_8P4R_5% DDRA_SMA12
73 CB1 CB5 74 4 5
75 76 RP12
VSS VSS DDRA_SDQ26 DDRA_DQ26 RP13
77 78 1 8 RP11
DQS8 DM8 DDRA_SDQ27 DDRA_DQ27 DDRA_SDM3 DDRA_DM3
79 CB2 CB6 80 2 7 1 4
81 82 DDRA_SDQ31 3 6 DDRA_DQ31 DDRA_SDQS3 2 3 DDRA_DQS3
VDD VDD DDRA_SDQ30 DDRA_DQ30
83 CB3 CB7 84 4 5
85 86 10_0404_4P2R_5% 56_0804_8P4R_5%
DU DU/RESET# 10_0804_8P4R_5% DDRA_SBS0
87 VSS VSS 88 1 8
89 90 DDRA_SMA10 2 7
CK2 VSS RP16 RP18 DDRA_SMA1
91 CK2# VDD 92 3 6
93 94 DDRA_SDQ37 1 8 DDRA_DQ37 DDRA_SDQ38 1 8 DDRA_DQ38 DDRA_SMA3 4 5
DDRA_CKE1 VDD VDD DDRA_CKE0 DDRA_SDQ36 DDRA_DQ36 DDRA_SDQ39 DDRA_DQ39
<6> DDRA_CKE1 95 CKE1 CKE0 96 DDRA_CKE0 <6> 2 7 2 7
97 98 DDRA_SDQ33 3 6 DDRA_DQ33 DDRA_SDQ35 3 6 DDRA_DQ35 RP14
DDRA_SMA12 DU/A13 DU/BA2 DDRA_SMA11 DDRA_SDQ32 DDRA_DQ32 DDRA_SDQ34 DDRA_DQ34
99 A12 A11 100 4 5 4 5
DDRA_SMA9 101 102 DDRA_SMA8
A9 A8 10_0804_8P4R_5% 10_0804_8P4R_5%
103 VSS VSS 104
DDRA_SMA7 105 106 DDRA_SMA6 RP15
DDRA_SMA5 A7 A6 DDRA_SMA4 RP19 DDRA_SWE#
107 108 RP17 2 3
DDRA_SMA3 A5 A4 DDRA_SMA2 DDRA_SDQS4 DDRA_DQS4 DDRA_SDQ41 DDRA_DQ41 DDRA_SCS#0
109 A3 A2 110 1 4 1 8 1 4
DDRA_SMA1 111 112 DDRA_SMA0 DDRA_SDM4 2 3 DDRA_DM4 DDRA_SDQ45 2 7 DDRA_DQ45
A1 A0 DDRA_SDQ44 DDRA_DQ44 56_0404_4P2R_5%
113 VDD VDD 114 3 6
DDRA_SMA10 115 116 DDRA_SBS1 10_0404_4P2R_5% DDRA_SDQ40 4 5 DDRA_DQ40
A10/AP BA1 DDRA_SBS1 <7>
DDRA_SBS0 117 118 DDRA_SRAS# DDRA_SMA13 1 2
<7> DDRA_SBS0 BA0 RAS# DDRA_SRAS# <7>
DDRA_SWE# 119 120 DDRA_SCAS# RP21 10_0804_8P4R_5% R48 56_0402_5%
<7> DDRA_SWE# WE# CAS# DDRA_SCAS# <7>
DDRA_SCS#0 121 122 DDRA_SCS#1 DDRA_SDQ46 1 8 DDRA_DQ46 DDRA_CKE1 1 2
<6> DDRA_SCS#0 S0# S1# DDRA_SCS#1 <6> 10_0404_4P2R_5%
DDRA_SMA13 123 124 DDRA_SDQ42 2 7 DDRA_DQ42 R47 56_0402_5%
DU DU DDRA_SDQ47 DDRA_DQ47 DDRA_SDQS5
125 VSS VSS 126 3 6 2 3 DDRA_DQS5 DDRA_CKE0 1 2
DDRA_DQ36 127 128 DDRA_DQ37 DDRA_SDQ43 4 5 DDRA_DQ43 DDRA_SDM5 1 4 DDRA_DM5 R369 56_0402_5%
B DDRA_DQ33 DQ32 DQ36 DDRA_DQ32 B
129 DQ33 DQ37 130
10_0804_8P4R_5% RP20
131 VDD VDD 132
DDRA_DQS4 133 134 DDRA_DM4
DDRA_DQ38 DQS4 DM4 DDRA_DQ39 RP22
135 DQ34 DQ38 136
137 138 DDRA_SDQ52 1 8 DDRA_DQ52 RP23 DDRA_DQ[0..63]
DDRA_DQ35 VSS VSS DDRA_DQ34 DDRA_SDQ49 DDRA_DQ49 DDRA_SDQS6 DDRA_DQS6 DDRA_DQ[0..63] <12>
139 DQ35 DQ39 140 2 7 1 4
DDRA_DQ41 141 142 DDRA_DQ45 DDRA_SDQ53 3 6 DDRA_DQ53 DDRA_SDM6 2 3 DDRA_DM6 DDRA_DM[0..7]
DQ40 DQ44 DDRA_DM[0..7] <12>
143 144 DDRA_SDQ48 4 5 DDRA_DQ48
DDRA_DQ44 VDD VDD DDRA_DQ40 10_0404_4P2R_5% DDRA_DQS[0..7]
145 DQ41 DQ45 146 DDRA_DQS[0..7] <12>
DDRA_DQS5 147 148 DDRA_DM5 10_0804_8P4R_5%
DQS5 DM5
149 VSS VSS 150
DDRA_DQ46 151 152 DDRA_DQ42 RP24 RP25
DDRA_DQ47 DQ42 DQ46 DDRA_DQ43 DDRA_SDQ54 DDRA_DQ54 DDRA_SDQ60 DDRA_DQ60
153 DQ43 DQ47 154 1 8 1 8
155 156 DDRA_SDQ55 2 7 DDRA_DQ55 DDRA_SDQ61 2 7 DDRA_DQ61
VDD VDD DDRA_SDQ50 DDRA_DQ50 DDRA_SDQ56 DDRA_DQ56
157 VDD CK1# 158 DDRA_CLK2# <6> 3 6 3 6
159 160 DDRA_SDQ51 4 5 DDRA_DQ51 DDRA_SDQ58 4 5 DDRA_DQ58
VSS CK1 DDRA_CLK2 <6> DDRA_SDQ[0..63]
161 VSS VSS 162 <7> DDRA_SDQ[0..63]
DDRA_DQ52 163 164 DDRA_DQ49 10_0804_8P4R_5% 10_0804_8P4R_5%
DDRA_DQ53 DQ48 DQ52 DDRA_DQ48 DDRA_SDM[0..7]
165 DQ49 DQ53 166 <7> DDRA_SDM[0..7]
167 168 RP26 RP27
DDRA_DQS6 VDD VDD DDRA_DM6 DDRA_SDQS7 DDRA_DQS7 DDRA_SDQ57 DDRA_DQ57 DDRA_SDQS[0..7]
169 DQS6 DM6 170 1 4 1 8 <7> DDRA_SDQS[0..7]
DDRA_DQ54 171 172 DDRA_DQ55 DDRA_SDM7 2 3 DDRA_DM7 DDRA_SDQ63 2 7 DDRA_DQ63
DQ50 DQ54 DDRA_SDQ59 DDRA_DQ59 DDRA_SMA[0..13]
173 VSS VSS 174 3 6 <7> DDRA_SMA[0..13]
DDRA_DQ50 175 176 DDRA_DQ51 10_0404_4P2R_5% DDRA_SDQ62 4 5 DDRA_DQ62
DDRA_DQ60 DQ51 DQ55 DDRA_DQ61
177 DQ56 DQ60 178
179 180 10_0804_8P4R_5%
DDRA_DQ56 VDD VDD DDRA_DQ58
181 DQ57 DQ61 182
DDRA_DQS7 183 184 DDRA_DM7
DQS7 DM7
A 185 VSS VSS 186 A
DDRA_DQ57 187 188 DDRA_DQ63
DDRA_DQ62 DQ58 DQ62 DDRA_DQ59
189 DQ59 DQ63 190
191 VDD VDD 192
D_CK_SDATA 193 194
<12,14> D_CK_SDATA SDA SA0
D_CK_SCLK 195 196
<12,14> D_CK_SCLK SCL SA1
197 198
+3VS
199
VDD_SPD
VDD_ID
SA2
DU 200
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title

AMP_1565917-1
DDR-SODIMM SLOT0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
DIMM0 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Boston LA-2721 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 2005/5/6 下午 11:47:58 Sheet 11 of 53
5 4 3 2 1
 A B C D E
JP20
+DIMM_VREF 1 VREF VREF 2 +DIMM_VREF
+DDRVTT 3 4
+DDRVCC DDRA_DQ1 VSS VSS DDRA_DQ0 +DDRVCC
5 DQ0 DQ4 6 1
DDRA_DQ5 7 8 DDRA_DQ4 C297
RP40 RP41 DDRA_DQ[0..63] DQ1 DQ5
<11> DDRA_DQ[0..63] 9 VDD VDD 10
DDRA_DQS0 11 12 DDRA_DM0 0.1U_0402_16V4Z
DDRA_DQ1 DDRA_DQS0 DDRA_DM[0..7] DDRA_DQ7 DQS0 DM0 DDRA_DQ6 2
4 5 5 4 <11> DDRA_DM[0..7] 13 DQ2 DQ6 14
DDRA_DQ0 3 6 6 3 DDRA_DM0 15 16
DDRA_DQ5 DDRA_DQ7 DDRA_DQS[0..7] DDRA_DQ3 VSS VSS DDRA_DQ2
2 7 7 2 <11> DDRA_DQS[0..7] 17 DQ3 DQ7 18
DDRA_DQ4 1 8 8 1 DDRA_DQ6 DDRA_DQ13 19 20 DDRA_DQ8
DDRB_SMA[0..13] DQ8 DQ12
<7> DDRB_SMA[0..13] 21 VDD VDD 22
56_0804_8P4R_5% 56_0804_8P4R_5% DDRA_DQ9 23 24 DDRA_DQ12
DDRA_DQS1 DQ9 DQ13 DDRA_DM1
25 DQS1 DM1 26
1 27 VSS VSS 28 1
RP42 RP44 DDRA_DQ15 29 30 DDRA_DQ14
DDRA_DQ11 DQ10 DQ14 DDRA_DQ10
31 DQ11 DQ15 32
DDRA_DQ3 4 5 5 4 DDRA_DQ9 33 34
DDRA_DQ2 DDRA_DQ12 VDD VDD
3 6 6 3 <6> DDRB_CLK1 35 CK0 VDD 36
DDRA_DQ13 2 7 7 2 DDRA_DQS1 37 38
<6> DDRB_CLK1# CK0# VSS
DDRA_DQ8 1 8 8 1 DDRA_DM1 39 40
VSS VSS
56_0804_8P4R_5% 56_0804_8P4R_5%
RP45 DDRA_DQ16 41 42 DDRA_DQ17
DDRA_DQ15 DDRA_DQ20 DQ16 DQ20 DDRA_DQ21
5 4 43 DQ17 DQ21 44
6 3 DDRA_DQ14 45 46
DDRA_DQ11 DDRA_DQS2 VDD VDD DDRA_DM2
7 2 47 DQS2 DM2 48
8 1 DDRA_DQ10 DDRA_DQ18 49 50 DDRA_DQ19
DQ18 DQ22
51 VSS VSS 52
56_0804_8P4R_5% DDRA_DQ22 53 54 DDRA_DQ23
DDRA_DQ25 DQ19 DQ23 DDRA_DQ24
55 DQ24 DQ28 56
RP47 RP49 57 58
DDRA_DQ16 DDRA_DQS2 DDRA_DQ29 VDD VDD DDRA_DQ28
4 5 5 4 59 DQ25 DQ29 60
DDRA_DQ17 3 6 6 3 DDRA_DM2 DDRA_DQS3 61 62 DDRA_DM3
DDRA_DQ20 DDRA_DQ18 DQS3 DM3
2 7 7 2 63 VSS VSS 64
DDRA_DQ21 1 8 8 1 DDRA_DQ19 DDRA_DQ27 65 66 DDRA_DQ26
DDRA_DQ30 DQ26 DQ30 DDRA_DQ31
67 DQ27 DQ31 68
56_0804_8P4R_5% 56_0804_8P4R_5% 69 70
VDD VDD
71 CB0 CB4 72
73 CB1 CB5 74
RP50 RP52 75 76
VSS VSS
77 DQS8 DM8 78
DDRA_DQ22 4 5 5 4 DDRA_DQ29 79 80
2 DDRA_DQ23 DDRA_DQ28 CB2 CB6 2
3 6 6 3 81 VDD VDD 82
DDRA_DQ25 2 7 7 2 DDRA_DQS3 83 84
DDRA_DQ24 DDRA_DM3 CB3 CB7
1 8 8 1 85 DU DU/RESET# 86
87 VSS VSS 88
56_0804_8P4R_5% 56_0804_8P4R_5% 89 90
CK2 VSS
91 CK2# VDD 92
RP53 93 94
DDRA_DQ27 DDRB_CKE1 VDD VDD DDRB_CKE0
5 4 <6> DDRB_CKE1 95 CKE1 CKE0 96 DDRB_CKE0 <6>
6 3 DDRA_DQ26 97 98
DDRA_DQ30 DDRB_SMA12 DU/A13 DU/BA2 DDRB_SMA11
7 2 99 A12 A11 100
8 1 DDRA_DQ31 DDRB_SMA9 101 102 DDRB_SMA8
A9 A8
103 VSS VSS 104
56_0804_8P4R_5% DDRB_SMA7 105 106 DDRB_SMA6
RP56 RP58 DDRB_SMA5 A7 A6 DDRB_SMA4
107 A5 A4 108
DDRB_SMA11 4 5 5 4 DDRB_SMA12 DDRB_SMA3 109 110 DDRB_SMA2
DDRB_SMA8 DDRB_SMA9 DDRB_SMA1 A3 A2 DDRB_SMA0
3 6 6 3 111 A1 A0 112
DDRB_SMA6 2 7 7 2 DDRB_SMA7 113 114
DDRB_SMA4 DDRB_SMA5 DDRB_SMA10 VDD VDD DDRB_SBS1
1 8 8 1 115 A10/AP BA1 116 DDRB_SBS1 <7>
+DDRVTT DDRB_SBS0 117 118 DDRB_SRAS#
<7> DDRB_SBS0 BA0 RAS# DDRB_SRAS# <7>
56_0804_8P4R_5% 56_0804_8P4R_5% DDRB_SWE# 119 120 DDRB_SCAS#
<7> DDRB_SWE# WE# CAS# DDRB_SCAS# <7>
DDRB_SCS#0 121 122 DDRB_SCS#1
<6> DDRB_SCS#0 S0# S1# DDRB_SCS#1 <6>
DDRB_SMA13 123 124
RP59 RP61 DU DU
125 VSS VSS 126
2 1 DDRB_SMA10 DDRA_DQ36 127 128 DDRA_DQ37
DDRB_SMA2 DDRB_SMA3 56_0402_5% R383 DDRA_DQ33 DQ32 DQ36 DDRA_DQ32
4 5 5 4 129 DQ33 DQ37 130
DDRB_SMA0 3 6 6 3 DDRB_SMA1 2 1 DDRB_CKE1 131 132
DDRB_SBS1 DDRB_SBS0 56_0402_5% R365 DDRA_DQS4 VDD VDD DDRA_DM4
2 7 7 2 133 DQS4 DM4 134
DDRB_SRAS# 1 8 8 1 DDRB_SWE# 2 1 DDRB_CKE0 DDRA_DQ38 135 136 DDRA_DQ39
56_0402_5% R362 DQ34 DQ38
137 VSS VSS 138
3 56_0804_8P4R_5% 56_0804_8P4R_5% DDRA_DQ35 DDRA_DQ34 3
139 DQ35 DQ39 140
DDRA_DQ41 141 142 DDRA_DQ45
RP63 RP71 DQ40 DQ44
143 VDD VDD 144
DDRB_SCAS# 4 5 DDRA_DQ44 145 146 DDRA_DQ40
DDRB_SCS#1 DDRA_DQ50 DDRA_DQS5 DQ41 DQ45 DDRA_DM5
3 6 5 4 147 DQS5 DM5 148
DDRB_SCS#0 2 7 6 3 DDRA_DQ51 149 150
DDRB_SMA13 DDRA_DQ60 DDRA_DQ46 VSS VSS DDRA_DQ42
1 8 7 2 151 DQ42 DQ46 152
8 1 DDRA_DQ61 DDRA_DQ47 153 154 DDRA_DQ43
56_0804_8P4R_5% DQ43 DQ47
155 VDD VDD 156
56_0804_8P4R_5% 157 158
VDD CK1# DDRB_CLK2# <6>
159 VSS CK1 160 DDRB_CLK2 <6>
RP64 RP65 161 162
DDRA_DQ36 DDRA_DQS4 RP72 DDRA_DQ52 VSS VSS DDRA_DQ49
4 5 5 4 163 DQ48 DQ52 164
DDRA_DQ37 3 6 6 3 DDRA_DM4 5 4 DDRA_DQ56 DDRA_DQ53 165 166 DDRA_DQ48
DDRA_DQ33 DDRA_DQ38 DDRA_DQ58 DQ49 DQ53
2 7 7 2 6 3 167 VDD VDD 168
DDRA_DQ32 1 8 8 1 DDRA_DQ39 7 2 DDRA_DQS7 DDRA_DQS6 169 170 DDRA_DM6
DDRA_DM7 DDRA_DQ54 DQS6 DM6 DDRA_DQ55
8 1 171 DQ50 DQ54 172
56_0804_8P4R_5% 56_0804_8P4R_5% 173 174
RP67 56_0804_8P4R_5% DDRA_DQ50 VSS VSS DDRA_DQ51
175 DQ51 DQ55 176
DDRA_DQ60 177 178 DDRA_DQ61
DDRA_DQ44 DQ56 DQ60
5 4 179 VDD VDD 180
6 3 DDRA_DQ40 DDRA_DQ56 181 182 DDRA_DQ58
DDRA_DQS5 RP73 DDRA_DQS7 DQ57 DQ61 DDRA_DM7
7 2 183 DQS7 DM7 184
RP66 8 1 DDRA_DM5 5 4 DDRA_DQ57 185 186
DDRA_DQ35 DDRA_DQ63 DDRA_DQ57 VSS VSS DDRA_DQ63
4 5 6 3 187 DQ58 DQ62 188
DDRA_DQ34 3 6 56_0804_8P4R_5% 7 2 DDRA_DQ62 DDRA_DQ62 189 190 DDRA_DQ59
DDRA_DQ41 DDRA_DQ59 DQ59 DQ63
2 7 8 1 191 VDD VDD 192
DDRA_DQ45 1 8 RP68 D_CK_SDATA 193 194
<11,14> D_CK_SDATA SDA SA0 +3VS
5 4 DDRA_DQ46 56_0804_8P4R_5% D_CK_SCLK 195 196
4 <11,14> D_CK_SCLK SCL SA1 4
56_0804_8P4R_5% 6 3 DDRA_DQ42 197 198
DDRA_DQ47 +3VS VDD_SPD SA2
7 2 199 VDD_ID DU 200
8 1 DDRA_DQ43

RP70 56_0804_8P4R_5% AMP_1565918-1

RP69
DDRA_DQS6 4 5 5 4 DDRA_DQ52 Security Classification Compal Secret Data Compal Electronics, Inc.
DDRA_DM6 3 6 6 3 DDRA_DQ49 2005/05/06 2006/05/06 Title
DDRA_DQ54 DDRA_DQ53
Issued Date Deciphered Date
DDRA_DQ55
2
1
7
8
7
8
2
1 DDRA_DQ48 DDR-SODIMM SLOT1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
56_0804_8P4R_5% 56_0804_8P4R_5% 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:58 Sheet 12 of 53
A B C D E
 A B C D E

Layout note :
Distribute as close as possible
to DDR-SODIMM.

+DDRVCC

1 1
1 1 1 1 1 1 1 1 1
C316 C313 C304 C411 C460 C449 C448 C396 C300
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2

+DDRVCC +DDRVCC

1 1
C377
0.1U_0402_16V4Z
2 2
1 1 1 1
C457 C337 C349 + +
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C35 C8
2 2 150U_D2_6.3VM 150U_D2_6.3VM
2 2

Layout note :
2 Place one cap close to every 2 pull up resistors termination to 2

+1.25V

+DDRVTT

1 1
C338
0.1U_0402_16V4Z
2 2
+DDRVTT
1 1 1 1 1 1
C305 C366 C422 C452 C389 C303 C387 1 1 1 1 1 1 1 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 C39 C33 C37 C428 C30 C398 C446 C410
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2

+DDRVTT

1 1 1 1 1 1 1 1
C308 C314 C325 C379 C345 C408 C453 C416
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2

3 3

+DDRVTT

1 1 1 1 1 1 1 1
C455 C454 C430 C459 C456 C403 C419 C433
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2

+DDRVTT

+DDRVTT
1 1 1 1

1 1 1 1 1 1 1 1 C361 C333 C356 C327

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
C442 C458 C40 C301 C425 C420 C370 C382 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
DDR SODIMM Decoupling
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:56 Sheet 13 of 53
A B C D E
 A B C D E F G H

R443 0_0805_5% 40mil

+CLK_VDD1
Clock Generator
+CLK_VDD48 +CLK_VDDREF +3VS 1 2
FSC FSB FSA CPU SRC PCI 1
C461
1
C470
1 1 1 1 1 1

CLKSEL0 CLKSEL1 CLKSEL2 C505 C468 C472 C471 C503 C504

MHz MHz MHz 0.047U_0402_16V7K 2.2U_0603_6.3V6K 0.047U_0402_16V7K 0.047U_0402_16V7K 0.047U_0402_16V7K 0.047U_0402_16V7K
2 2.2U_0603_6.3V6K 2 0.047U_0402_16V7K 2 2 2 2 2 2
1 0 1 100 100 33.3
*
0 0 1 133 100 33.3
1
* 1

0 1 1 166 100 33.3 +CLK_VCCA 1 2 +CLK_VDD1

+CLK_VDD1 R483
U35
40mil 2.2_0402_5% +CLK_VDD2
0 1 0 200 100 33.3 1 1
R442 0_0805_5%
+CLK_VDD2 40mil
21 VDDPCIEX_0 +3VS 1 2
28 37 C515 C506
VDDPCIEX_1 VDDA 2 2.2U_0603_6.3V6K 2 0.047U_0402_16V7K
+3VS Table : ICS 954226AGT 34 VDDPCIEX_2 1 1 1
GNDA 38
1 VDDPCI_0
7 C477 C473 C476
CLKSEL2 VDDPCI_1 STP_PCI# 2 2.2U_0603_6.3V6K 2 0.047U_0402_16V7K 2 0.047U_0402_16V7K
1 2 PCI/SRC_STOP# 55 PM_STP_PCI# <19>
R401 10K_0402_5% +CLK_VDD1
54 STP_CPU#
CPU_STOP# PM_STP_CPU# <19,50>
1 2 CLK_PCI0
R420 10K_0402_5% 42
C511 Y4 VDDCPU
1 2 +CLK_VDDREF 48 VDDREF
1 2 CLK_PCI2 30P_0402_50V8J 14.318MHZ_16PF_DSX840GA R465 1_0402_5% 15mil
R466 10K_0402_5% 1 2 41 CLK_CPU1 R473 1 2 33_0402_5% CLK_MCH_BCLK
CPUCLKT1 CLK_MCH_BCLK <6>
1 1 2 +CLK_VDD48 11 VDD48
R412 2.2_0402_5% 15mil 40 CLK_CPU1# R472 1 2 33_0402_5% CLK_MCH_BCLK#
CPUCLKC1 CLK_MCH_BCLK# <6>
1 2 CLK_PCI1 CLK_MCH_BCLK 1 2
R419 10K_0402_5% C510 XTALIN 50 R485 49.9_0402_1%
30P_0402_50V8J X1 CLK_MCH_BCLK# 1 2
2

1 2 XTALOUT 49 44 CLK_CPU0 R475 1 2 33_0402_5% CLK_CPU_BCLK R484 49.9_0402_1%

X2 CPUCLKT0 CLK_CPU_BCLK <4>
CLK_ICH_48M R402 1 2 12_0402_5% CLK_CPU_BCLK 1 2
<19> CLK_ICH_48M
43 CLK_CPU0# R474 1 2 33_0402_5% CLK_CPU_BCLK# R487 49.9_0402_1%
CPUCLKC0 CLK_CPU_BCLK# <4>
2 CLK_SD_48M R403 1 2 12_0402_5% CLKSEL2 12 CLK_CPU_BCLK# 1 2 2
<24> CLK_SD_48M FS_A/USB_48MHz
CLK_14M_CODEC 2 1 5IN1@ CLKSEL0 53 R486 49.9_0402_1%
<30> CLK_14M_CODEC REF1/FSLC/TEST_SEL
R463 12_0402_5% CLK_CPU_ITP 1 2
R482 @ 49.9_0402_1%
CLKSEL1 16 36 CLK_CPU2 R471 1 2@ 33_0402_5% CLK_CPU_ITP CLK_CPU_ITP# 1 2
FSLB/TEST_MODE CPUCLKT2_ITP/PCIEXT6 R481 @ 49.9_0402_1%
35 CLK_CPU2# R470 1 2@ 33_0402_5% CLK_CPU_ITP# CLK_PCIE_LAN 1 2
CPUCLKC2_ITP/PCIEXC6 R480 49.9_0402_1%
5 CLK_PCIE_LAN# 1 2
PCICLK5 R479 49.9_0402_1%
CLK_PCI_MINI 1 2 CLK_PCI4 4 33 CLK_PCIE_SATA 1 2
<29> CLK_PCI_MINI PCICLK4 PEREQ1#/PCIEXT5
R430 33_0402_5% R405 49.9_0402_1%
CLK_PCI_SIO 1 2 CLK_PCI3 3 32 CLK_PCIE_SATA# 1 2
<33,34> CLK_PCI_SIO PCICLK3 PEREQ2#/PCIEXC5
R431 33_0402_5% R404 49.9_0402_1%
CLK_PCI_PCM 1 2 CLK_PCI2 56 CLK_MCH_3GPLL 1 2
<24> CLK_PCI_PCM PCICLK2/REQ_SEL
R467 33_0402_5% 31 CLK_SRC5 R469 1 2 33_0402_5% CLK_PCIE_LAN R424 49.9_0402_1%
PCIEXT4 CLK_PCIE_LAN <27>
CLK_PCI_LPC 1 2 CLK_PCI1 9 CLK_MCH_3GPLL# 1 2
<35> CLK_PCI_LPC SELPCIEX_LCDCLK#/PCICLK_F1
R410 33_0402_5% 30 CLK_SRC5# R468 1 2 33_0402_5% CLK_PCIE_LAN# R423 49.9_0402_1%
PCIEXC4 CLK_PCIE_LAN# <27>
CLK_PCIE_VGA 1 2
R407 49.9_0402_1%
CLK_PCI_ICH 1 2 CLK_PCI0 8 26 CLK_SRC4 R414 1 2 33_0402_5% CLK_PCIE_SATA CLK_PCIE_VGA# 1 2
<17> CLK_PCI_ICH ITP_EN/PCICLK_F0 SATACLKT CLK_PCIE_SATA <18>
R411 33_0402_5% R406 49.9_0402_1%
D_CK_SCLK 46 27 CLK_SRC4# R413 1 2 33_0402_5% CLK_PCIE_SATA# CLK_PCIE_ICH 1 2
<11,12> D_CK_SCLK SCLK SATACLKC CLK_PCIE_SATA# <18>
R426 49.9_0402_1%
CLK_PCIE_ICH# 1 2
D_CK_SDATA 47 24 CLK_SRC3 R434 1 2 33_0402_5% CLK_MCH_3GPLL R425 49.9_0402_1%
<11,12> D_CK_SDATA SDATA PCIEXT3 CLK_MCH_3GPLL <8>
CLK_DREF_SSC 1 2
25 CLK_SRC3# R433 1 2 33_0402_5% CLK_MCH_3GPLL# R409 49.9_0402_1%
PCIEXC3 CLK_MCH_3GPLL# <8>
1 2 CLKIREF 39 IREF
CLK_DREF_SSC# 1 2
3 R464 475_0402_1% 15mil R408 49.9_0402_1% 3

22 CLK_SRC2 R416 1 2 33_0402_5% CLK_PCIE_VGA CLK_DREF_96M 1 2

+3VS PCIEXT2 CLK_PCIE_VGA <16>
R428 49.9_0402_1%
R457 23 CLK_SRC2# R415 1 2 33_0402_5% CLK_PCIE_VGA# CLK_DREF_96M# 1 2
+3VS PCIEXC2 CLK_PCIE_VGA# <16>
4.7K_0402_5% R427 49.9_0402_1%
2

R449
G

1 2 +3VS
4.7K_0402_5% 19 CLK_SRC1 R436 1 2 33_0402_5% CLK_PCIE_ICH
PCIEXT1 CLK_PCIE_ICH <19>
2

D_CK_SCLK
G

<19> CK_SCLK 1 3 1 2 +3VS

20 CLK_SRC1# R435 1 2 33_0402_5% CLK_PCIE_ICH#
D

PCIEXC1 CLK_PCIE_ICH# <19>

Q51 1 3 D_CK_SDATA 13
2N7002_SOT23 <19> CK_SDATA GND_0
D

Q50 29 17 CLK_SRC0 R418 1 2 33_0402_5% CLK_DREF_SSC

GND_1 LCDCLK_SS/PCIEX0T CLK_DREF_SSC <6>
2N7002_SOT23
2 18 CLK_SRC0# R417 1 2 33_0402_5% CLK_DREF_SSC#
+1.05VS GND_2 LCDCLK_SS/PCIEX0C CLK_DREF_SSC# <6>
45 GND_3
14 CLK_DOT R438 1 2 33_0402_5% CLK_DREF_96M
DOTT_96MHz CLK_DREF_96M <6>
2

R432 51 15 CLK_DOT# R437 1 2 33_0402_5% CLK_DREF_96M#

GND_4 DOTC_96MHz CLK_DREF_96M# <6>
@ 1K_0402_5%
6 GND_5
R422 R429
4.7K_0402_5% 0_0402_5% +3VS 1 2 VGATE <6,19,50>
1

CLKSEL1 1 2 1 2 R421 10K_0402_5%

MCH_CLKSEL1 <6>

2
G
1 2 2 1 CPU_BSEL1 <5>
R439 R440 10 VTT_POWERGD# 1 3
@ 0_0402_5% 0_0402_5% VTT_PWRGD#/PD

S
52 CLK_REF 1 2 CLK_14M_SIO Q47
REF0 CLK_14M_SIO <33,34>
R461 12_0402_5% 2N7002_SOT23
4 +1.05VS 4

ICS954226AGT_TSSOP56 1 2 CLK_ICH_14M
CLK_ICH_14M <19>
R462 12_0402_5%
2

R450
@ 1K_0402_5%

R455 R451 Security Classification Compal Secret Data Compal Electronics, Inc.
4.7K_0402_5% 0_0402_5% 2005/05/06 2006/05/06 Title
Issued Date Deciphered Date
1

CLKSEL0 1 2 1 2 MCH_CLKSEL0 <6> Clock Generator

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1 2 2 1 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
CPU_BSEL0 <5>
R448 R456 1.0
@ 0_0402_5% 0_0402_5%
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:58 Sheet 14 of 53
A B C D E F G H
 A B C D E

CRT Connector D_CRT_R

D_CRT_G
D_CRT_B
R4 1
R320 1
R5
2 470_0402_1%
2 470_0402_1%
1 2 470_0402_1%
+5VS CRT Board
1 2 0.1U_0402_16V4Z 8P_0402_50V8K
+5VS
C10 8P_0402_50V8K
U3 8P_0402_50V8K R611 JP2
W D@
VCC 16 1 2W=40mils 1
DOCKIN# 1 2 2 2 +3VS 0_1206_5%
<35,40> DOCKIN# SEL 2
15 2 D_CRT_R DSUB_12_DATA
OE# 1B1 D_CRT_R <40> 3
1 5 D_CRT_G DSUB_15_CLK 1
2B1 D_CRT_G <40> C671 C672 C673 4
11 D_CRT_B H SYNC
3B1 D_CRT_B <40> 1 1 1 5
4 14 VSYNC
<16> VGA_CRT_R 1A 4B1 6
<8> GMCH_CRT_R 1 2 7 2A 7
R15 NOVGA@ 0_0402_5% 9 CRT_R L20 1 2 CRT_R_L
3A FCM2012C-800_0805 8
12 4A 1B2 3 9
6 CRT_G L21 1 2 CRT_G_L
<16> VGA_CRT_G 2B2 10
1 2 10 FCM2012C-800_0805
<8> GMCH_CRT_G 3B2 11
R24 NOVGA@ 0_0402_5% 13 CRT_B L22 1 2 CRT_B_L
4B2 FCM2012C-800_0805 12
<16> VGA_CRT_B 8 GND
1 2 1 1 1 ACES_85201-1205
<8> GMCH_CRT_B
R16 NOVGA@ 0_0402_5% W D@ FSAV330MTC_TSSOP16 C670 C669 C668

1
R7 R18 R8 8P_0402_50V8K
2 2 2
Close to VGA conn. 8P_0402_50V8K
150_0402_1% 150_0402_1% 8P_0402_50V8K

2
150_0402_1%
For EMI request
+5VS
VGA_CRT_R 1 2 CRT_R D_CRT_HSYNC 1 2 H SYNC
R10 WOD@ 0_0402_5% 1 2 2 1 L18 FCM1608C-121T_0603
VGA_CRT_G 1 2 CRT_G C299 0.1U_0402_16V4Z R319 10K_0402_5%
R21 WOD@ 0_0402_5% D_CRT_VSYNC 1 2 VSYNC

5
1
VGA_CRT_B 1 2 CRT_B L19 FCM1608C-121T_0603
R12 WOD@ 0_0402_5%

P
OE#
2 4 D_CRT_HSYNC 1 1
<16> VGA_CRT_HSYNC A Y D_CRT_HSYNC <40>
2 C667 C666 2
Pop with No-Docking

G
1 2 U33
<8> GMCH_CRT_HSYNC
R26 NOVGA@ 39_0402_5% SN74AHCT1G125GW_SOT353-5 10P_0402_50V8J 10P_0402_50V8J

3
2 2
+5VS

1 2
C296 0.1U_0402_16V4Z

5
1
P
OE#
2 4 D_CRT_VSYNC
<16> VGA_CRT_VSYNC A Y D_CRT_VSYNC <40>

G
1 2 U32
<8> GMCH_CRT_VSYNC
R22 NOVGA@ 39_0402_5% SN74AHCT1G125GW_SOT353-5

3
Close to VGA conn. +2.5VS
+5VS
+3VS 0_0402_5% VGA@ 2 1 R27

2
G
+2.5VS 0_0402_5% NOVGA@
2 1 R23 VGA_DDC_DATA 3 1 D_DDC_DATA
D_DDC_DATA <40>

D
1

Q7
BSS138_SOT23 NOVGA@
0_0402_5%NOVGA@ R14 R19
1 2 R11 4.7K_0402_5% 2 1
<8> GMCH_CRT_DATA
0_0402_5% VGA@ R29
2

2
2
G

3 4.7K_0402_5% +2.5VS 3
VGA_DDC_DATA 3 1 DSUB_12_DATA
<16> VGA_DDC_DATA
S

2
G
Q5
2
G

BSS138_SOT23
VGA_DDC_CLK 3 1 D_DDC_CLK
D_DDC_CLK <40>
VGA_DDC_CLK DSUB_15_CLK

D
<16> VGA_DDC_CLK 3 1
Q8
S

Q3 BSS138_SOT23 NOVGA@
BSS138_SOT23
<8> GMCH_CRT_CLK 1 2 2 1
R9 0_0402_5% VGA@ R34
0_0402_5% NOVGA@

Close to VGA conn.

1 2 C85
@ 22P_0402_50V8J
<16> VGA_TV_LUMA
1 2 L2 1 2
<8> GMCH_TV_LUMA
R17 NOVGA@ 0_0402_5% FBM-11-160808-121T_0603

L3 1 2
<16> VGA_TV_CRMA
FBM-11-160808-121T_0603 TV-OUT
JP24
Conn.
<8> GMCH_TV_CRMA 1 2
1

R20 NOVGA@ 0_0402_5% 1 2 C88 CRMA_1 4 1. Y ground

4
1

R63 @ 22P_0402_50V8J LUMA_1 3 6 2. C ground

R66 3 6
2 2 5 5 3. Y (luminance+sync)
Close to VGA conn. C87 C76 1 4. C (crominance)
4 1 4
150_0402_1% 100P_0402_25V8K 100P_0402_25V8K C89 C86
2

150_0402_1% ALLTO_C10877-104A1-L_4P
2

100P_0402_25V8K 100P_0402_25V8K

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
CRT & TVout Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:56 Sheet 15 of 53
A B C D E
 5 4 3 2 1

PCIE_MTX_C_GRX_N[0..15]
<8> PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
<8> PCIE_MTX_C_GRX_P[0..15]
LCD POWER CIRCUITGMCH_ENVDD <8> PCEI_GTX_C_MRX_N[0..15]
PCEI_GTX_C_MRX_N[0..15]
<8> GMCH_ENVDD PCEI_GTX_C_MRX_P[0..15]
<8> PCEI_GTX_C_MRX_P[0..15]

+3VALW
U2

5
1
SN74AHCT1G125GW_SOT353-5
NOVGA@

P
OE#
+LCDVDD
2 4
D
1
A Y
VGA BOARD Conn. D

G
1

2
C5

3
0.01U_0402_16V7K JP19
R1 NOVGA@ 2 +3VS
B+ 1 2 B+
300_0402_5%
NOVGA@ R2 3 4
1 2

1
100_0402_5% Q1 5 6
7 8

3
D NOVGA@
S
NOVGA@ DAC_BRIG VGA_DDC_CLK
G 9 10 VGA_DDC_CLK <15>
Q2 2 2 AO3413_SOT23 DISPOFF# VGA_DDC_DATA
11 12 VGA_DDC_DATA <15>
2N7002_SOT23 G INVT_PWM
NOVGA@ 13 14 VGA_TV_LUMA
S 1
D
VGA_TV_LUMA <15>
3

1
15 16
2

+LCDVDD VGA_CRT_R
<15> VGA_CRT_R 17 18 VGA_TV_CRMA
19 20 VGA_TV_CRMA <15>
R3 C3 VGA_CRT_G
2 <15> VGA_CRT_G 21 22 VGA_CRT_VSYNC
23 24 VGA_CRT_VSYNC <15>
100K_0402_5% 0.047U_0402_16V7K 1 1 VGA_CRT_B VGA_CRT_HSYNC
<15> VGA_CRT_B VGA_CRT_HSYNC <15>
1

NOVGA@ NOVGA@ C2 C1 25 26 SUSP#

27 28 SUSP# <26,30,32,35,37,38,42,49>
+3VALW GMCH_ENBKL
29 30 GMCH_ENBKL <8,35>
4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 NOVGA@ 2 NOVGA@ 31 32
+2.5VS 33 34 +1.5VS
35 36 DVI_DET <40>
<40> DVI_TXC+ 37 38 DVI_SCLK <40>
<40> DVI_TXC- 39 40 DVI_SDATA <40>
41 42
<40> DVI_TXD0+ 43 44 +3VS
<40> DVI_TXD0- 45 46
C
47 48 C
<40> DVI_TXD1+ 49 50 +5VS
<40> DVI_TXD1- 51 52 +5VALW
53 54
<40> DVI_TXD2+ 55 56
<40> DVI_TXD2- 57 58
R38 59 60
<19> PLTRST_VGA# 1 2 VGA@ 0_0402_5% 61 62 CLK_PCIE_VGA <14>
R35 1 2 @ 0_0402_5%
<6,17,19,21,22,24,27,34,35> PLT_RST# 63 64 CLK_PCIE_VGA# <14>
PCEI_GTX_C_MRX_P0 65 66 PCIE_MTX_C_GRX_P0
PCEI_GTX_C_MRX_N0 67 68 PCIE_MTX_C_GRX_N0
69 70
PCEI_GTX_C_MRX_P1 71 72 PCIE_MTX_C_GRX_P1
PCEI_GTX_C_MRX_N1 73 74 PCIE_MTX_C_GRX_N1
+3VS 75 76
PCEI_GTX_C_MRX_P2 77 78 PCIE_MTX_C_GRX_P2
PCEI_GTX_C_MRX_N2 79 80 PCIE_MTX_C_GRX_N2
81 82
1

R6 PCEI_GTX_C_MRX_P3 83 84 PCIE_MTX_C_GRX_P3
PCEI_GTX_C_MRX_N3 85 86 PCIE_MTX_C_GRX_N3
4.7K_0402_5% 87 88
D1 PCEI_GTX_C_MRX_P4 89 90 PCIE_MTX_C_GRX_P4
2

BKOFF# 91 92
<35> BKOFF# 1 2 RB751V_SOD323 DISPOFF# PCEI_GTX_C_MRX_N4
93 94
PCIE_MTX_C_GRX_N4

PCEI_GTX_C_MRX_P5 95 96 PCIE_MTX_C_GRX_P5
PCEI_GTX_C_MRX_N5 97 98 PCIE_MTX_C_GRX_N5
99 100
PCEI_GTX_C_MRX_P6 101 102 PCIE_MTX_C_GRX_P6
PCEI_GTX_C_MRX_N6 103 104 PCIE_MTX_C_GRX_N6
B 105 106 B
PCEI_GTX_C_MRX_P7 107 108 PCIE_MTX_C_GRX_P7
PCEI_GTX_C_MRX_N7 109 110 PCIE_MTX_C_GRX_N7
111 112
PCEI_GTX_C_MRX_P8 113 114 PCIE_MTX_C_GRX_P8
LCD/PANEL BD. Conn. PCEI_GTX_C_MRX_N8 115
117
116
118
PCIE_MTX_C_GRX_N8

PCEI_GTX_C_MRX_P9 119 120 PCIE_MTX_C_GRX_P9

JP4 PCEI_GTX_C_MRX_N9 121 122 PCIE_MTX_C_GRX_N9
123 124
2 1 PCEI_GTX_C_MRX_P10 125 126 PCIE_MTX_C_GRX_P10
4 3 GMCH_TXOUT0- <8> 127 128
PCEI_GTX_C_MRX_N10 PCIE_MTX_C_GRX_N10
+3VS 6 5 GMCH_TXOUT0+ <8> 129 130
8 7 PCEI_GTX_C_MRX_P11 131 132 PCIE_MTX_C_GRX_P11
+LCDVDD 10 9 GMCH_TXOUT1- <8> 133 134
PCEI_GTX_C_MRX_N11 PCIE_MTX_C_GRX_N11
12 11 GMCH_TXOUT1+ <8> 135 136
GMCH_LCD_CLK 14 13 PCEI_GTX_C_MRX_P12 137 138 PCIE_MTX_C_GRX_P12
1 <8> GMCH_LCD_CLK 16 15 GMCH_TXOUT2+ <8> 139 140
C4 GMCH_LCD_DATA PCEI_GTX_C_MRX_N12 PCIE_MTX_C_GRX_N12
<8> GMCH_LCD_DATA 18 17 GMCH_TXOUT2- <8> 141 142
DAC_BRIG
<35> DAC_BRIG 20 19 143 144
@ 0.1U_0402_16V4Z INVT_PWM PCEI_GTX_C_MRX_P13 PCIE_MTX_C_GRX_P13
2 <35> INVT_PWM 22 21 GMCH_TXCLK- <8> 145 146
DISPOFF# PCEI_GTX_C_MRX_N13 PCIE_MTX_C_GRX_N13
24 23 GMCH_TXCLK+ <8> 147 148
26 25 PCEI_GTX_C_MRX_P14 149 150 PCIE_MTX_C_GRX_P14
B+ 28 27 151 152
PCEI_GTX_C_MRX_N14 PCIE_MTX_C_GRX_N14
30 29 153 154
ACES_88242-3000 PCEI_GTX_C_MRX_P15 155 156 PCIE_MTX_C_GRX_P15
NOVGA@ PCEI_GTX_C_MRX_N15 157 158 PCIE_MTX_C_GRX_N15
159 160
VGA@ ACES_88081-1600
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
VGA / LCD CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:55 Sheet 16 of 53
5 4 3 2 1
 5 4 3 2 1

RP37
1 8 PCI_SERR#
+3VS
2 7 PCI_TRDY#
3 6 PCI_FRAME#
D 4 5 PCI_STOP# U13B D
<24,29> PCI_AD[0..31] PCI_AD0 PCI_REQ#0
8.2K_0804_8P4R_5% PCI_AD1
E2 AD[0] REQ[0]# L5
PAD~D T5
Internal Pull-up.
PCI_AD2
E5
C2
AD[1] PCI GNT[0]# C1
B5 PCI_REQ#1 Sample high destination is LPC.
AD[2] REQ[1]# PCI_REQ#1 <29>
PCI_AD3 F5 B6 PCI_GNT#1
AD[3] GNT[1]# PCI_GNT#1 <29>
PCI_AD4 F3 M5 PCI_REQ#2 PCI_GNT#5
AD[4] REQ[2]# PCI_REQ#2 <24>
RP36 PCI_AD5 E9 F1 PCI_GNT#2
AD[5] GNT[2]# PCI_GNT#2 <24>
1 8 PCI_PLOCK# PCI_AD6 F2 B8 PCI_REQ#3
+3VS AD[6] REQ[3]#

1
2 7 P CI_IRDY# PCI_AD7 D6 C8 PAD~D T3
PCI_PERR# PCI_AD8 AD[7] GNT[3]# PCI_REQ#4 R529
3 6 E6 AD[8] REQ[4]#/GPI[40] F7
4 5 PCI_DEVSEL# PCI_AD9 D3 E7 PAD~D T4 @ 0_0402_5%
PCI_AD10 AD[9] GNT[4]#/GPO[48] PCI_REQ#5
A2 AD[10] REQ[5]#/GPI[1] E8
8.2K_0804_8P4R_5% PCI_AD11 D2 F6 PCI_GNT#5

2
PCI_AD12 AD[11] GNT[5]#/GPO[17] PCI_REQ#6
D5 AD[12] REQ[6]#/GPI[0] B7 2 1 BT_DET# <33,34,36>
PCI_AD13 H3 D8 R230 NOSIO@ 0_0402_5% PAD~D T2
PCI_AD14 AD[13] GNT[6]#/GPO[16]
B4 AD[14]
RP39 PCI_AD15 J5 J6 PCI_C/BE#0
PCI_PIRQD# PCI_AD16 AD[15] C/BE[0]# PCI_C/BE#1 PCI_C/BE#0 <24,29>
+3VS 1 8 K2 AD[16] C/BE[1]# H6 PCI_C/BE#1 <24,29>
2 7 PCI_PIRQB# PCI_AD17 K5 G4 PCI_C/BE#2
PCI_PIRQC# PCI_AD18 AD[17] C/BE[2]# PCI_C/BE#3 PCI_C/BE#2 <24,29>
3 6 D4 AD[18] C/BE[3]# G2 PCI_C/BE#3 <24,29>
4 5 PCI_PIRQA# PCI_AD19 L6
PCI_AD20 AD[19] P CI_IRDY#
G3 AD[20] IRDY# A3 PCI_IRDY# <24,29>
8.2K_0804_8P4R_5% PCI_AD21 H4 E1 PCI_PAR
PCI_AD22 AD[21] PAR PCI_RST# PCI_PAR <24,29>
H2 AD[22] PCIRST# R2 PCI_RST# <24,29,34,35>
PCI_AD23 H5 C3 PCI_DEVSEL#
RP35 PCI_AD24 AD[23] DEVSEL# PCI_PERR# PCI_DEVSEL# <24,29>
B3 AD[24] PERR# E3 PCI_PERR# <24,29>
1 8 PCI_PIRQE# PCI_AD25 M6 C5 PCI_PLOCK#
+3VS AD[25] PLOCK#
2 7 PCI_PIRQF# PCI_AD26 B2 G5 PCI_SERR#
PCI_PIRQG# PCI_AD27 AD[26] SERR# PCI_STOP# PCI_SERR# <24,29>
3 6 K6 AD[27] STOP# J1 PCI_STOP# <24,29>
C 4 5 PCI_REQ#6 PCI_AD28 K3 J2 PCI_TRDY# C676 2 1@ 180P_0402_50V8J C
PCI_AD29 AD[28] TRDY# PCI_TRDY# <24,29>
A5 AD[29]
8.2K_0804_8P4R_5% PCI_AD30 L1
PCI_AD31 AD[30]
K4 AD[31]
R5 PLT_RST#
PLTRST# PLT_RST# <6,16,19,21,22,24,27,34,35>
RP34 G6 CLK_PCI_ICH CLK_PCI_ICH
PCICLK CLK_PCI_ICH <14>
1 8 PCI_REQ#5 PCI_FRAME# J3 P6
+3VS <24,29> PCI_FRAME# FRAME# PME#
2 7 PCI_REQ#3

2
3 6 PCI_REQ#1 Interrupt I/F
4 5 PCI_REQ#4 PCI_PIRQA# N2 D9 PCI_PIRQE#
<24> PCI_PIRQA# PCI_PIRQB# PIRQ[A]# PIRQ[E]#/GPI[2] PCI_PIRQF# R528
<24> PCI_PIRQB# L2 PIRQ[B]# PIRQ[F]#/GPI[3] C7
8.2K_0804_8P4R_5% PCI_PIRQC# M1 C6 PCI_PIRQG# @ 10_0402_5%
<24> PCI_PIRQC# PIRQ[C]# PIRQ[G]#GPI[4] PCI_PIRQG# <29>
PCI_PIRQD# L3 M3 PCI_PIRQH#
<24> PCI_PIRQD# PCI_PIRQH# <29>

1
PIRQ[D]# PIRQ[H]#/GPI[5]

RP38 AC5
RESERVED 1
C615
SATA[1]RXN/RSVD[1] @ 10P_0402_50V8J
+3VS 1 8 AD5 SATA[1]RXP/RSVD[2]
2 7 PCI_REQ#0 AF4
PCI_REQ#2 SATA[1]TXN/RSVD[3] 2
3 6 AG4 SATA[1]TXP/RSVD[4]
4 5 PCI_PIRQH# AC9 SATA[3]RXN/RSVD[5]
AD9 SATA[3]RXP/RSVD[6]
8.2K_0804_8P4R_5% AF8 SATA[3]TXN/RSVD[7]
AG8 SATA[3]TXP/RSVD[8]
U3 TP[3]/RSVD[9]
R3SB@ ICH6_BGA609

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
ICH6(1/4)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:55 Sheet 17 of 53
5 4 3 2 1
 5 4 3 2 1

+1.05VS

+RTCVCC H_FERR# 1 2
C201 18P_0402_50V8J
ICH_RTCX1 R96 56_0402_5%
1

10M_0402_5%
Y2

1
R228 3 4
NC OUT

R219
1M_0402_1% 32.768KHZ_12.5P_1TJS125BJ2A251 2 1
NC IN U13A
D D
2

2
INTRUDER# Y1 P2 LPC_LAD0
RTCX1 LAD[0]/FWH[0] LPC_AD0 <33,34,35>

RTC
C202 18P_0402_50V8J
ICH_RTCX2 Y2 N3 LPC_LAD1
RTCX2 LAD[1]/FWH[1] LPC_LAD2 LPC_AD1 <33,34,35>
LAD[2]/FWH[2] N5 LPC_AD2 <33,34,35>
2 1 ICH_RTCRST# AA2 N4 LPC_LAD3

LPC
+RTCVCC RTCRST# LAD[3]/FWH[3] LPC_AD3 <33,34,35>
R227
+3VS 20K_0402_5% INTRUDER# AA3 N6
INTVRMEN INTRUDER# LDRQ[0]# LPC_DRQ#1
AA5 INTVRMEN LDRQ[1]#/GPI[41] P4 LPC_DRQ#1 <33,34>
1

2 1 P3 LPC_FRAME#
LFRAME#/FWH[4] LPC_FRAME# <33,34,35>
R135 close to RAM door J2 JOPEN D12 EE_CS R139 1
B12 EE_SHCLK 2 10K_0402_5% +3VS
10K_0402_5% D11 AF22 EC_GA20
EE_DOUT A20GATE EC_GA20 <35>
C204 F13 AF23 H_A20M#
H_A20M# <4>
2

1U_0402_6.3V4Z EE_DIN A20M#

LAN
R94 2 @ 0_0402_5% H_CPUSLP#

CPU
1 2 F12 LAN_CLK CPUSLP# AE27 1 H_CPUSLP# <4,6>
PHDD_LED#
B11 AE24 H_DPRSTP#
LAN_RSTSYNC DPRSLP#/TP[4] H_DPRSTP# <4>
DPSLP#/TP[2] AD27 H_DPSLP# <4>
E12 LANRXD[0]
E11 AF24 FERR# 1 2 H_FERR#
LANRXD[1] FERR# H_FERR# <4>
C13 R95 56_0402_5%
LANRXD[2] H_PWRGOOD
CPUPWRGD/GPO[49] AG25 H_PWRGOOD <4>
C12 LANTXD[0]
C11 AG26 H_IGNNE#
LANTXD[1] IGNNE# H_IGNNE# <4>
C607 R527 E13 AE22
22P_0402_50V8J 10_0402_5% LANTXD[2] INIT3_3V# H_INIT#
INIT# AF27 H_INIT# <4>
1 2 2 1 AG24 H_INTR R134
INTR H_INTR <4>
C 10K_0402_5% C
ICH_AC_BITCLK C10 1 2 +3VS
<30,36> ICH_AC_BITCLK ACZ_BIT_CLK

AC-97/AZALIA
ICH_AC_SYNC R171 1 2 33_0402_5% A C_SYNC B9 AD23 EC_KBRST#
<30,36> ICH_AC_SYNC ACZ_SYNC RCIN# EC_KBRST# <35>
ICH_AC_RST# A10 AF25 H_NMI
<30,36> ICH_AC_RST# ACZ_RST# NMI H_NMI <4>
AG27 H_SMI#
SMI# H_SMI# <4>
ICH_AC_SDIN0 F11
<30> ICH_AC_SDIN0 ACZ_SDIN[0]
ICH_AC_SDIN1 F10 AE26 H_STPCLK#
<36> ICH_AC_SDIN1 ACZ_SDIN[1] STPCLK# H_STPCLK# <4>
B10 ACZ_SDIN[2]
AE23 THRMTRIP#
ICH_AC_SDOUT THRMTRIP#
<30,36> ICH_AC_SDOUT C9 ACZ_SDO
IDE_DA[0..2] <22>
AC16 IDE_DA0
PHDD_LED# DA[0] IDE_DA1
<35> PHDD_LED# AC19 SATALED# DA[1] AB17
AC17 IDE_DA2
DA[2]
SATA_DTX_C_IRX_N0 AE3 AD16 IDE_DCS1#
<21> SATA_DTX_C_IRX_N0 SATA[0]RXN DCS1# IDE_DCS1# <22>
SATA_DTX_C_IRX_P0 AD3 AE17 IDE_DCS3#
<21> SATA_DTX_C_IRX_P0 SATA[0]RXP DCS3# IDE_DCS3# <22>
SATA_ITX_DRX_N0 AG2
SATA_ITX_DRX_P0 SATA[0]TXN
AF2 SATA[0]TXP IDE_DD[0..15] <22>
AD14 IDE_DD0
DD[0]

SATA
R193 2 1 1K_0402_5% AD7 AF15 IDE_DD1
SATA[2]RXN DD[1]

PIDE
R197 2 1 1K_0402_5% AC7 AF14 IDE_DD2
SATA[2]RXP DD[2] IDE_DD3
AF6 SATA[2]TXN DD[3] AD12
AG6 AE14 IDE_DD4
SATA[2]TXP DD[4] IDE_DD5
DD[5] AC11
CLK_PCIE_SATA# AC2 AD11 IDE_DD6
<14> CLK_PCIE_SATA# SATA_CLKN DD[6]
CLK_PCIE_SATA AC1 AB11 IDE_DD7
<14> CLK_PCIE_SATA SATA_CLKP DD[7]
AE13 IDE_DD8
B DD[8] IDE_DD9 B
AG11 SATARBIAS# DD[9] AF13
R178 1 2 24.9_0402_1% SATARBIAS AF11 AB12 IDE_DD10
SATARBIAS DD[10] IDE_DD11
DD[11] AB13
AC13 IDE_DD12
DD[12] IDE_DD13
DD[13] AE15
AG15 IDE_DD14
IDE _DIORDY DD[14] IDE_DD15
<22> IDE_DIORDY AF16 IORDY DD[15] AD13
IDE_IRQ AB16
<22> IDE_IRQ IDEIRQ
R174 1 2 4.7K_0402_5% IDE _DIORDY IDE_DDACK# AB15
+3VS <22> IDE_DDACK# DDACK#
IDE_DIOW# AC14 AB14 IDE_DDREQ
<22> IDE_DIOW# DIOW# DDREQ IDE_DDREQ <22>
IDE_DIOR# AE16
<22> IDE_DIOR# DIOR#
R523 1 2 8.2K_0402_5% IDE_IRQ

R3SB@ ICH6_BGA609

MAINPWON <44,45,47>
R118

1
@ 330_0402_5% C
+1.05VS 1 2 2 Q15
B @ 2SC2411K_SC59
Place near ICH6 side. E

3
SATA_ITX_DRX_N0 2 1 SATA_ITX_C_DRX_N0 +1.05VS 1 2 2 1 THRMTRIP#
SATA_ITX_C_DRX_N0 <21>
C179 0.01U_0402_16V7K R121 75_0402_1% R124
56_0402_5%
A A
SATA_ITX_DRX_P0 2 1 SATA_ITX_C_DRX_P0
SATA_ITX_C_DRX_P0 <21>
C181 0.01U_0402_16V7K H_THERMTRIP#
H_THERMTRIP# <4,6>

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
ICH6(2/4)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:55 Sheet 18 of 53
5 4 3 2 1
 5 4 3 2 1

+3VALW

1 2 ICH_SMLINK0
R225 10K_0402_5% U13C
1 2 ICH_SMLINK1 EC_SWI# T2 H25 PCIE_PTX_C_IRX_N1
<35> EC_SWI# RI# PERn[1] PCIE_PTX_C_IRX_N1 <27>
R244 10K_0402_5% H24 PCIE_PTX_C_IRX_P1
PERp[1] PCIE_PTX_C_IRX_P1 <27>
1 2 CK_SCLK GPI26 AF17 G27 PCIE_ITX_PRX_N1 1 2 PCIE_ITX_C_PRX_N1
SATA[0]GP/GPI[26] PETn[1] PCIE_ITX_C_PRX_N1 <27>
R525 2.2K_0402_5% GPI27 AE18 G26 PCIE_ITX_PRX_P1 C112 1 2 0.1U_0402_16V4Z PCIE_ITX_C_PRX_P1
SATA[1]GP/GPI[29] PETp[1] PCIE_ITX_C_PRX_P1 <27>
1 2 CK_SDATA GPI28 AF18 C113 0.1U_0402_16V4Z
R524 2.2K_0402_5% GPI29 SATA[2]GP/GPI[30]
AG18 SATA[3]GP/GPI[31] PERn[2] K25
1 2 LINKALERT# K24
R237 10K_0402_5% CK_SCLK PERp[2]
D <14> CK_SCLK Y4 SMBCLK PETn[2] J27 D

PCI-EXPRESS
1 2 EC_LID_OUT# CK_SDATA W5 J26
R222 @ 10K_0402_5% <14> CK_SDATA LINKALERT# SMBDATA PETp[2]
Y5 LINKALERT#
1 2 EC_SWI# ICH_SMLINK0 W4 M25
SMLINK[0] PERn[3]

GPIO
R223 10K_0402_5% ICH_SMLINK1 U6 M24
PM_BATLOW# MCH_SYNC# SMLINK[1] PERp[3]
1 2 AG21 MCH_SYNC# PETn[3] L27
R226 8.2K_0402_5% SB_SPKR F8 L26
<30> SB_SPKR SPKR PETp[3]
1 2 ICH_PCIE_WAKE#
R236 1K_0402_5% W3 P24
<37> SUS_STAT# SUS_STAT#/LPCPD# PERn[4]
1 2 SYSRST# P23
R224 10K_0402_5% SYSRST# PERp[4] +3VALW
U2 SYS_RESET# PETn[4] N27
PETp[4] N26
+3VS PM_BMBUSY# AD19
<6> PM_BMBUSY# BM_BUSY#/GPI[6]
T25 DMI_MTX_IRX_N0 RP29
DMI[0]RXN DMI_MTX_IRX_N0 <6>
1 2 ICH_GPI7 ICH_GPI7 AE19 T24 DMI_MTX_IRX_P0 USB_OC#5 4 5
GPI[7] DMI[0]RXP DMI_MTX_IRX_P0 <6>
R155 10K_0402_5% EC_SMI# R1 R27 DMI_ITX_MRX_N0 USB_OC#4 3 6
<35> EC_SMI# GPI[8] DMI[0]TXN DMI_ITX_MRX_N0 <6>
1 2 PM_CLKRUN# R26 DMI_ITX_MRX_P0 USB_OC#6 2 7
DMI[0]TXP DMI_ITX_MRX_P0 <6>

DIRECT MEDIA INTERFACE

R154 8.2K_0402_5% AC IN W6 USB_OC#7 1 8
<35,39,44> ACIN SMBALERT#/GPI[11]
1 2 ICH_VGATE V25 DMI_MTX_IRX_N1
DMI[1]RXN DMI_MTX_IRX_N1 <6>
R150 10K_0402_5% EC_LID_OUT# M2 V24 DMI_MTX_IRX_P1 10K_0804_8P4R_5%
<35> EC_LID_OUT# GPI[12] DMI[1]RXP DMI_MTX_IRX_P1 <6>
1 2 MCH_SYNC# EC_SCI# R6 U27 DMI_ITX_MRX_N1
<35> EC_SCI# GPI[13] DMI[1]TXN DMI_ITX_MRX_N1 <6>
R145 10K_0402_5% U26 DMI_ITX_MRX_P1
DMI[1]TXP DMI_ITX_MRX_P1 <6>
1 2 SERIRQ PM_STP_PCI# AC21
<14> PM_STP_PCI# STP_PCI#/GPO[18]
R146 10K_0402_5% Y25 DMI_MTX_IRX_N2 RP28
DMI[2]RXN DMI_MTX_IRX_N2 <6>
1 2 AB21 Y24 DMI_MTX_IRX_P2 USB_OC#3 4 5
<37> SB_INT_FLASH_SEL# GPO[19] DMI[2]RXP DMI_MTX_IRX_P2 <6>
C680 @ 33P_0402_50V8J W27 DMI_ITX_MRX_N2 USB_OC#0 3 6
DMI[2]TXN DMI_ITX_MRX_N2 <6>
PM_STP_CPU# AD22 W26 DMI_ITX_MRX_P2 USB_OC#1 2 7
<14,50> PM_STP_CPU# STP_CPU#/GPO[20] DMI[2]TXP DMI_ITX_MRX_P2 <6>
Reserve for noise USB_OC#2 1 8
AB24 DMI_MTX_IRX_N3
DMI[3]RXN DMI_MTX_IRX_N3 <6>
C 1 2 SYS_PWROK AD20 AB23 DMI_MTX_IRX_P3 10K_0804_8P4R_5% C
GPO[21] DMI[3]RXP DMI_MTX_IRX_P3 <6>
R220 10K_0402_5% PLTRST_VGA# AD21 AA27 DMI_ITX_MRX_N3
<16> PLTRST_VGA# GPO[23] DMI[3]TXN DMI_ITX_MRX_N3 <6>
1 2 EC_RSMRST# AA26 DMI_ITX_MRX_P3
DMI[3]TXP DMI_ITX_MRX_P3 <6>
R234 10K_0402_5% IDE_HRESET# V3
<21> IDE_HRESET# GPIO[24]
AD25 CLK_PCIE_ICH#
DMI_CLKN CLK_PCIE_ICH# <14>
RP30 IDE_MRESET# P5 AC25 CLK_PCIE_ICH
<35> IDE_MRESET# GPIO[25] DMI_CLKP CLK_PCIE_ICH <14>
4 5 GPI29 R3
GPI28 EC_FLASH# GPIO[27]
3 6 <37> EC_FLASH# T3 GPIO[28]
2 7 GPI27 PM_CLKRUN# AF19 F24
GPI26 <29,33,34> PM_CLKRUN# CLKRUN#/GPIO[32] DMI_ZCOMP
1 8 AF20 GPIO[33]
AC18 F23 DMI_IRCOMP R510 1 2 24.9_0402_1% +1.5VS
100_1206_8P4R_5% GPIO[34] DMI_IRCOMP
ICH_PCIE_WAKE# U5 C23 USB_OC#4
<27> ICH_PCIE_WAKE# WAKE# OC[4]#/GPI[9]
D23 USB_OC#5
PM_DPRSLPVR SERIRQ OC[5]#/GPI[10] USB_OC#6
1 2 <24,33,34,35> SERIRQ AB20 SERIRQ OC[6]#/GPI[14] C25
R140 100K_0402_5% C24 USB_OC#7
EC_THERM# OC[7]#/GPI[15]
<35> EC_THERM# AC20 THRM#
C27 USB_OC#0
OC[0]#
2 1 ICH_VGATE AF21 B27 USB_OC#1
<6,14,50> VGATE
R151 0_0402_5%
CLK_ICH_14M
VRMPWRGD OC[1]#
OC[2]# B26 USB_OC#2
USB_OC#3
USB PORT# DESTINATION
E10 CLK14 OC[3]# C26
CLK_ICH_48M USB20_N0

CLOCK
A27 CLK48 USBP[0]N C21 USB20_N0 <40>
D21 USB20_P0
T6
PAD~D
V6 SUSCLK
USBP[0]P
USBP[1]N A20
B20
USB20_N1
USB20_P1
USB20_P0 <40>
USB20_N1 <39> 0 Docking
PM_SLP_S3# USBP[1]P USB20_N2 USB20_P1 <39>
T4 D19
<35> PM_SLP_S3#
<35> PM_SLP_S4#
PM_SLP_S4# T5
SLP_S3#
SLP_S4#
USBP[2]N
USBP[2]P C19 USB20_P2 USB20_N2 <39>
USB20_P2 <39> 1 JP3

USB
PM_SLP_S5# T6 A18 USB20_N3
B <35> PM_SLP_S5# SLP_S5# USBP[3]N USB20_N3 <39> B
B18 USB20_P3
<41> SYS_PWROK
SYS_PWROK AA1 PWROK
USBP[3]P
USBP[4]N E17 USB20_N4 USB20_P3 <39>
USB20_N4 <39> 2 JP17

POWER MGT
D17 USB20_P4
PM_DPRSLPVR USBP[4]P USB20_N5 USB20_P4 <39>
AE20 B16
<50> PM_DPRSLPVR
PM_BATLOW# V2
DPRSLPVR/TP[1] USBP[5]N
USBP[5]P A16
C15
USB20_P5 USB20_N5 <36>
USB20_P5 <36> 3 JP3
<35> PM_BATLOW# BATLOW#/TP[0] USBP[6]N
D15
<35> PBTN_OUT#
PBTN_OUT# U1 PWRBTN#
USBP[6]P
USBP[7]N A14
B14
4 JP17
PLT_RST# USBP[7]P
V5
<6,16,17,21,22,24,27,34,35> PLT_RST#
EC_RSMRST# Y3
LAN_RST#
USBRBIAS# A22
B22
USBRBIAS 1
R512
2
22_0402_1%
5 BlueTooth
<35> EC_RSMRST# RSMRST# USBRBIAS
R3SB@ ICH6_BGA609 6 Reserve
7 Reserve

CLK_ICH_48M CLK_ICH_14M
<14> CLK_ICH_48M <14> CLK_ICH_14M
1
1

R526
A A
R507 @ 10_0402_5%
@ 10_0402_5%
2
2

1
1
C608
C581
2
@ 10P_0402_50V8J Security Classification Compal Secret Data Compal Electronics, Inc.
@ 10P_0402_50V8J 2005/05/06 2006/05/06 Title
2 Issued Date Deciphered Date
ICH6(3/4)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:57 Sheet 19 of 53
5 4 3 2 1
 5 4 3 2 1

+1.5VS
Near PIN F27(C155), +1.5VS C606
P27(C154), AB27(C157) U13E +RTCVCC 0.1U_0402_16V4Z U13D
1 2 E27 VSS[172] VSS[86] F4
+1.5VS AA22 VCC1_5[1] VCC1_5[98] F9 Y6 VSS[171] VSS[85] F22

220U_D2_4VM_R12

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 AA23 U17 0.1U_0402_16V4Z C580 Y27 F19
VCC1_5[2] VCC1_5[97] 0.1U_0402_16V4Z VSS[170] VSS[84]
2 2 2 AA24 VCC1_5[3] VCC1_5[96] U16 Y26 VSS[169] VSS[83] F17

C160
+ AA25 U14 1 2 Y23 E25
VCC1_5[4] VCC1_5[95] 2 2 VSS[168] VSS[82]

C588

C613

C576
AB25 U12 C196 W7 E19
VCC1_5[5] VCC1_5[94] C610 VSS[167] VSS[81]
AB26 VCC1_5[6] VCC1_5[93] U11 W25 VSS[166] VSS[80] E18
2 1 1 1 0.1U_0402_16V4Z
AB27 VCC1_5[7] VCC1_5[92] T17 W24 VSS[165] VSS[79] E15
D F25 T11 C6231 1
1 2 W23 E14 D
VCC1_5[8] VCC1_5[91] VSS[164] VSS[78]
F26 VCC1_5[9] VCC1_5[90] P17 W1 VSS[163] VSS[77] D7
F27 P11 0.1U_0402_16V4Z C585 V4 D22
VCC1_5[10] VCC1_5[89] 0.1U_0402_16V4Z VSS[162] VSS[76]
G22 M17 V27 D20

CORE
VCC1_5[11] VCC1_5[88] VSS[161] VSS[75]
G23 VCC1_5[12] VCC1_5[87] M11 1 2 V26 VSS[160] VSS[74] D18
G24 VCC1_5[13] VCC1_5[86] L17 V23 VSS[159] VSS[73] D14
G25 L16 C601 U25 D13
+5VS +3VS VCC1_5[14] VCC1_5[85] 0.1U_0402_16V4Z VSS[158] VSS[72]
H21 VCC1_5[15] VCC1_5[84] L14 U24 VSS[157] VSS[71] D10
H22 VCC1_5[16] VCC1_5[83] L12 1 2 U23 VSS[156] VSS[70] D1
J21 VCC1_5[17] VCC1_5[82] L11 U15 VSS[155] VSS[69] C4
2

2
J22 AA21 C611 U13 C22
R192 D13 VCC1_5[18] VCC1_5[81] 0.1U_0402_16V4Z VSS[154] VSS[68]
K21 VCC1_5[19] VCC1_5[80] AA20 T7 VSS[153] VSS[67] C20
K22 VCC1_5[20] VCC1_5[79] AA19 1 2 T27 VSS[152] VSS[66] C18

PCIE
10_0402_5% RB751V_SOD323 L21 T26 C14
VCC1_5[21] C622 VSS[151] VSS[65]
L22 T23 B25
1

VCC1_5[22] 0.1U_0402_16V4Z +3VS 0.1U_0402_16V4Z VSS[150] VSS[64]

M21 VCC1_5[23] VCC3_3[21] AA10 T16 VSS[149] VSS[63] B24
ICH_V5REF_RUN M22 AG19 1 2 T15 B23
VCC1_5[24] VCC3_3[20] VSS[148] VSS[62]
2 2 2 N21 VCC1_5[25] VCC3_3[19] AG16 T14 VSS[147] VSS[61] B21
N22 AG13 2 2 C602 T13 B19
C177 C599 VCC1_5[26] VCC3_3[18] 0.1U_0402_16V4Z VSS[146] VSS[60]
N23 VCC1_5[27] VCC3_3[17] AD17 T12 VSS[145] VSS[59] B15
1U_0603_10V4Z C614 0.1U_0402_16V4Z N24 AC15 C605 Near PIN 1 2 T1 B13
1 1 1 VCC1_5[28] VCC3_3[16] VSS[144] VSS[58]
N25 AA17 R4 AG7

IDE
0.1U_0402_16V4Z P21
VCC1_5[29] VCC3_3[15]
AA15 C6191 1 AG13, AG16 C592 R25
VSS[143] VSS[57]
AG3
VCC1_5[30] VCC3_3[14] 0.1U_0402_16V4Z VSS[142] VSS[56]
P25 VCC1_5[31] VCC3_3[13] AA14 R24 VSS[141] VSS[55] AG22
P26 VCC1_5[32] VCC3_3[12] AA12 1 2 R23 VSS[140] VSS[54] AG20
P27 0.1U_0402_16V4Z R17 AG17
VCC1_5[33] C591 VSS[139] VSS[53]
R21 VCC1_5[34] R16 VSS[138] VSS[52] AG14
R22 P1 +3VS 0.1U_0402_16V4Z R15 AG12
VCC1_5[35] VCC3_3[11] VSS[137] VSS[51]

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
T21 VCC1_5[36] VCC3_3[10] M7 2 2 2 1 2 R14 VSS[136] VSS[50] AG1
C T22 L7 R13 AF7 C
VCC1_5[37] VCC3_3[9] VSS[135] VSS[49]

C624

C620

C625
U21 L4 C584 R12 AF3
VCC1_5[38] VCC3_3[8] 0.01U_0402_16V7K VSS[134] VSS[48]
U22 VCC1_5[39] VCC3_3[7] J7 R11 VSS[133] VSS[47] AF26
1 1 1
V21 VCC1_5[40] VCC3_3[6] H7 1 2 P22 VSS[132] VSS[46] AF12

GROUND
PCI
V22 VCC1_5[41] VCC3_3[5] H1 P16 VSS[131] VSS[45] AF10
W21 VCC1_5[42] VCC3_3[4] E4 Near PIN A25 P15 VSS[130] VSS[44] AF1
W22 VCC1_5[43] VCC3_3[3] B1 Near PIN C583
P14 VSS[129] VSS[43] AE7
Y21 A6 P13 AE6
Y22
VCC1_5[44] VCC3_3[2] A2-A6, D1-H1 0.01U_0402_16V7K P12
VSS[128] VSS[42]
AE25
VCC1_5[45] VSS[127] VSS[41]
VCCSUS1_5[3] U7 +1.5VALW 1 2 N7 VSS[126] VSS[40] AE21
+1.5VS AA6 VCC1_5[46] VCCSUS1_5[2] R7 N17 VSS[125] VSS[39] AE2
AB4 VCC1_5[47] Near PIN AA19 N16 VSS[124] VSS[38] AE12

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
AB5 VCC1_5[48] 2 2 2 N15 VSS[123] VSS[37] AE11

USB
2 AB6 VCC1_5[49] VCCSUS1_5[1] G19 N14 VSS[122] VSS[36] AE10

C595
C617

C616
AC4 VCC1_5[50] N13 VSS[121] VSS[35] AD6
Near PIN AG5 C621 AD4 G20 N12 AD24
0.1U_0402_16V4Z VCC1_5[51] VCC1_5[78] 1 1 1 VSS[120] VSS[34]
AE4 VCC1_5[52] VCC1_5[77] F20 N11 VSS[119] VSS[33] AD2
1
AE5 VCC1_5[53] VCC1_5[76] E24 N1 VSS[118] VSS[32] AD18

SATA
AF5 VCC1_5[54] VCC1_5[75] E23 M4 VSS[117] VSS[31] AD15

USB CORE
AG5 VCC1_5[55] VCC1_5[74] E22 M27 VSS[116] VSS[30] AD10
VCC1_5[73] E21 +3VALW M26 VSS[115] VSS[29] AD1
+1.5VS AA7 VCC1_5[56] VCC1_5[72] E20 M23 VSS[114] VSS[28] AC6
AA8 D27 C603 M16 AC3
VCC1_5[57] VCC1_5[71] 0.1U_0402_16V4Z VSS[113] VSS[27]
AA9 VCC1_5[58] VCC1_5[70] D26 M15 VSS[112] VSS[26] AC26
2 AB8 VCC1_5[59] VCC1_5[69] D25 1 2 M14 VSS[111] VSS[25] AC24
AC8 VCC1_5[60] VCC1_5[68] D24 +1.5VS M13 VSS[110] VSS[24] AC23
+5VALW +3VALW C612 C600
Near PIN AG9 0.1U_0402_16V4Z
AD8 VCC1_5[61] +2.5VS 0.1U_0402_16V4Z
M12 VSS[109] VSS[23] AC22
AE8 VCC1_5[62] VCC1_5[67] G8 L25 VSS[108] VSS[22] AC12
1
AE9 VCC1_5[63] 1 2 L24 VSS[107] VSS[21] AC10
2

B B
AF9 VCC1_5[64] VCC2_5[4] AB18 L23 VSS[106] VSS[20] AB9
R147 D9 AG9 PCI/IDE RBP P7 C618 L15 AB7
VCC1_5[65] VCC2_5[2] 0.1U_0402_16V4Z VSS[105] VSS[19]
L13 VSS[104] VSS[18] AB2

0.1U_0402_16V4Z
10_0402_5% RB751V_SOD323 ICH6_VCCPLL AC27 AA18 ICH_V5REF_RUN 2 1 2 K7 AB19
VCCDMIPLL V5REF[2] VSS[103] VSS[17]
+3VS E26 A8 K27 AB10
1

VCC3_3[1] V5REF[1] VSS[102] VSS[16]

C596
ICH_V5REF_SUS C586 K26 AB1
ICH_V5REF_SUS 0.1U_0402_16V4Z VSS[101] VSS[15]
2 2 +1.5VS AE1 VCCSATAPLL V5REF_SUS F21 K23 VSS[100] VSS[14] AA4
C142 1
2 +3VS AG10 VCC3_3[22] 1 2 K1 VSS[99] VSS[13] AA16
C593 Near PIN A25 +1.5VS J4 AA13
1U_0603_10V4Z 0.1U_0402_16V4Z VCCUSBPLL VSS[98] VSS[12]
1 1 C578 E26, E27
A13 VCCLAN3_3/VCCSUS3_3[1] VCCSUS3_3[20] A24 +3VALW Near PIN A24 J25 VSS[97] VSS[11] AA11
+3VS F14 VCCLAN3_3/VCCSUS3_3[2] J24 VSS[96] VSS[10] A9
0.1U_0402_16V4Z 1 G13 AB3 +RTCVCC J23 A7
VCCLAN3_3/VCCSUS3_3[3] VCCRTC VSS[95] VSS[9]
G14 VCCLAN3_3/VCCSUS3_3[4] Near PIN AB18 H27 VSS[94] VSS[8] A4
VCCLAN1_5/VCCSUS1_5[2] G11 H26 VSS[93] VSS[7] A26
+3VALW A11 VCCSUS3_3[1] VCCLAN1_5/VCCSUS1_5[1] G10 +1.5VS H23 VSS[92] VSS[6] A23
U4 VCCSUS3_3[2] G9 VSS[91] VSS[5] A21
V1 VCCSUS3_3[3] V_CPU_IO[3] AG23 G7 VSS[90] VSS[4] A19
+3VS
V7 VCCSUS3_3[4] V_CPU_IO[2] AD26 +1.05VS G21 VSS[89] VSS[3] A15
W2 AB22 C609 G12 A12
VCCSUS3_3[5] V_CPU_IO[1] 0.1U_0402_16V4Z VSS[88] VSS[2]
Y7 VCCSUS3_3[6] G1 VSS[87] VSS[1] A1

0.1U_0402_16V4Z
VCCSUS3_3[19] G16 2 1 2
+3VALW A17 VCCSUS3_3[7] VCCSUS3_3[18] G15 C590 Near PIN AG23 R3SB@ ICH6_BGA609
B17 VCCSUS3_3[8] VCCSUS3_3[17] F16
0.1U_0402_16V4Z

0.1U_0402_16V4Z

2 2 C17 VCCSUS3_3[9] VCCSUS3_3[16] F15

R92 R93 1 C153
F18 VCCSUS3_3[10] VCCSUS3_3[15] E16
C597

C598

0_0603_5% 0.5_0603_1% G17 D16 0.1U_0402_16V4Z

ICH6_VCCDMIPLL 1 ICH6_VCCPLL VCCSUS3_3[11] VCCSUS3_3[14]
+1.5VS 1 2 2 G18 VCCSUS3_3[12] VCCSUS3_3[13] C16 1 2
1 1
A A
2 1 R3SB@ ICH6_BGA609 Near PIN AG10

C107
Near PIN A17
0.1U_0402_16V4Z 1 C111 2
0.01U_0402_16V7K
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title

Near PIN
ICH6(4/4)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
AC27 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:58 Sheet 20 of 53
5 4 3 2 1
 5 4 3 2 1

+5VS

0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS

+3VS
1 1 1 1 C98
C260 C247 1 2 ATAIOSEL 1 2 0.1U_0402_16V4Z
R502 10K_0402_5%
C266 C243 1 2 PIDE_HIORDY

5
2 2 2 2 R503 4.7K_0402_5% U10
1000P_0402_50V7K 1U_0603_10V4Z 1 2 PIDE_HIOCS16# 1

P
<19> IDE_HRESET# B
R506 10K_0402_5% R86 4 SATA_RST#
T0 PLT_RST# Y
D 1 2 <6,16,17,19,22,24,27,34,35> PLT_RST# 1 2 2 A D

G
Pleace near HD CONN R129 @ 10K_0402_5%
1 2 T2 0_0402_5% TC7SH08FU_SSOP5

3
R131 @ 10K_0402_5%
1 2 T3
+1.8VS R132 10K_0402_5%
1 2 T6
0.1U_0402_16V4Z R133 10K_0402_5%

1 1 1
C106

C94 C136
2 2 2
4.7U_0805_10V4Z 0.1U_0402_16V4Z

Pleace near U178

U8

PIDE_HDD0 62 32 SATA_DTX_IRX_P0 C5752 1 0.01U_0402_16V7KSATA_DTX_C_IRX_P0

HDD0 TXP SATA_DTX_C_IRX_P0 <18>
PIDE_HDD1 64 31 SATA_DTX_IRX_N0 C5722 1 0.01U_0402_16V7KSATA_DTX_C_IRX_N0
HDD1 TXM SATA_DTX_C_IRX_N0 <18>
PIDE_HDD2 SATA_ITX_C_DRX_P0
C PIDE_HDD3
2
5
HDD2 SATA RXP 27
28 SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_P0 <18>
C
HDD3 RXM SATA_ITX_C_DRX_N0 <18>
PIDE_HDD4 7
PIDE_HDD5 HDD4 SATA_RST#
11 HDD5 RST# 17
PIDE_HDD6 13 33 T0
PIDE_HDD7 HDD6 T0 T1 T1 2
15 34 1
Config & Debug

PIDE_HDD8 HDD7 T1 T2 10K_0402_5% R130

14 HDD8 T2 35
PIDE_HDD9 12 36 T3
PIDE_HDD10 HDD9 T3
10 HDD10 T4 37
PIDE_HDD11 6 38 T5 1 2
Parallel ATA

PIDE_HDD12 HDD11 T5 T6 R125 10K_0402_5%

3 HDD12 T6 39
PIDE_HDD13 1 40
PIDE_HDD14 HDD13 T7
63 HDD14 CNFG2 20
PIDE_HDD15 61 19 CNFG1 1 2
HDD15 CNFG1 R500 10K_0402_5%
CNFG0 18
21 ATAIOSEL
PIDE_HDA0 ATAIOSEL
50 HDA0
PIDE_HDA1 51 22 IDE_XTLIN
PIDE_HDA2 HDA1 XTLIN/OSC
49 HDA2 XTLOUT 23
PIDE_HCS0# 48
PIDE_HCS1# HCS0# +3VS +1.8VS +3VS
47
R505PIDE_HIOCS16# 52
HCS1#
ISET 26
44
2
R104
1
12.1K_0603_1%
P-ATA HDD Conn.
PIDE_HINTRQ HIOCS16# VDDIO_0 JP29
2 1 53 HINTRQ VDDIO_1 4
PIDE_HDMACK# 54 9 PIDE_HRESET# 1 2
10K_0402_5% PIDE_HIORDY HDMACK# VDD_0 PIDE_HDD7 1 2 PIDE_HDD8
55 HIORDY VDD_1 41 3 3 4 4
PIDE_HDIOR# 58 56 PIDE_HDD6 5 6 PIDE_HDD9
R89 5.6K_0402_5% PIDE_HDIOW# HDIOR# VDD_2 PIDE_HDD5 5 6 PIDE_HDD10
59 HDIOW# VAA1 24 7 7 8 8
2 1 PIDE_HDREQ 60 29 0.1U_0402_16V4Z L5 PIDE_HDD4 9 10 PIDE_HDD11
PIDE_HRESET# 1 HDMARQ VAA2 9 10
2 PIDE_R_HRESET# 16 HRESET# Power 0_0603_5% PIDE_HDD3 11 11 12 12 PIDE_HDD12
B R78 33_0402_5% PIDE_HDD2 PIDE_HDD13 B
46 HPDIAG# VSS1 25 Change to 0 ohm 13 13 14 14
30 1 1 1 1 PIDE_HDD1 15 16 PIDE_HDD14
VSS2 C109 C133 PIDE_HDD0 15 16 PIDE_HDD15
GND_0 8 17 17 18 18
2.2U_0603_6.3V6K
45
43
UAO UART GND_1 42
57 PIDE_HDREQ
19
21
19 20 20
22
UAI GND_2 21 22
1

2 2 2 2 PIDE_HDIOW# 23 23 24 24
C124 C110 PIDE_HDIOR# 25 26
88SA8040_TQFP64 PIDE_HIORDY 25 26 SEC_CSEL R240 1
27 27 28 28 2 470_0402_5%
R126 0.01U_0402_16V7K 1000P_0402_50V7K PIDE_HDMACK# 29 30
29 30
1

10K_0402_5% PIDE_HINTRQ 31 32 R251 1 2 10K_0402_5%

2

R127 PIDE_HDA1 31 32 R255 1

33 33 34 34 2 10K_0402_5%
0_0603_5% PIDE_HDA0 35 36 PIDE_HDA2
R266 PIDE_HCS0# 35 36 PIDE_HCS1#
37 37 38 38
1 2 @ 10K_0402_5% 39 40
2

39 40
Close to pin29, pin30 +5VS 41 41 42 42 +5VS
43 43 44 44
OCTEK_HDS-22TA1_44P_RV
+3VS
1

+3VS
R105
0_0402_5% 4.7U_0805_10V4Z 0.1U_0402_16V4Z
X1 1 1 1
2

4 3 IDE_XTLIN
VDD OUT C95 C137 C96
0.1U_0402_16V4Z
A 2 2 2 A

1 1 CONT VSS 2
C114 OSC 25MHZ SG645PCG
0.1U_0402_16V4Z
2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
PATA / SATA HDD Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:58 Sheet 21 of 53
5 4 3 2 1
 5 4 3 2 1

+5VS
Placea caps. near CDROM
CONN. 1U_0603_10V4Z

1 1 1 1 IDE_DD[0..15]
C507 C512 C502 C493 <18> IDE_DD[0..15]
IDE_DA[0..2]
<18> IDE_DA[0..2]
2 2 2 2
D 0.1U_0402_16V4Z 10U_1206_16V4Z D
1000P_0402_50V7K

C559 CDROM CONN

C 2 1 CD_AGND C
CD_AGND <30>
10U_0805_10V4Z

JP25 1 2 DCS3#
<30> INT_CD_L <18> IDE_DCS3#
INT_CD_L 1 2 INT_CD_R R583 0_0402_5%
INT_CD_R <30>
R600 2 1@ 0_0402_5% 3 4 1 2 1 2 DCS1#
<35> ODD_RESET# <18> IDE_DCS1#
1 2 5 6 IDE_DD8 R494 @ 0_0603_5% R584 0_0402_5%
<6,16,17,19,21,24,27,34,35> PLT_RST#
R599 IDE_DD7 7 8 IDE_DD9
22_0402_5% IDE_DD6 9 10 IDE_DD10
IDE_DD5 11 12 IDE_DD11
IDE_DD4 13 14 IDE_DD12
IDE_DD3 15 16 IDE_DD13
IDE_DD2 17 18 IDE_DD14
IDE_DD1 19 20 IDE_DD15
IDE_DD0 21 22 IDE_DDREQ <18>
23 24 IDE_DIOR# <18>
<18> IDE_DIOW# 25 26
<18> IDE_DIORDY 27 28 IDE_DDACK# <18>
<18> IDE_IRQ 29 30
31 32 PDIAG# 1 R476 2 100K_0402_5% +5VS
<18> IDE_DA1
<18> IDE_DA0 33 34 IDE_DA2 <18>
DCS1# 35 36 DCS3#
1 2 37 38 W=80mils
+5VS +5VS
R477 100K_0402_5% 39 40
+5VS 41 42
<35> SHDD_LED# 43 44
45 46
SD_CSEL 47 48
49 50 1 2 +5VS
2

B R447 @ 100K_0402_5% B
53 54
R452
470_0402_5% OCTEK_CDR-50JD1
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
ODD Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:54 Sheet 22 of 53
5 4 3 2 1
 5 4 3 2 1

+S1_VCC +3VS

M10
M12
H10
H11
H12

D19
A11

K12

K19
J12
M7

M9
S1_A[0..25]

H8
H9

N7
A5

K8
J8
<26> S1_A[0..25]
D U12A D
S1_D[0..15]

VCCA
VCCA

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

RSVD
RSVD
<26> S1_D[0..15] S1_D10 D1 A_CAD31/A_D10
S1_D9 C1
S1_D1 A_CAD30/A_D9
D3 A_CAD29/A_D1 DATA N1 DATA <26>
S1_D8 C2 L6
A_CAD28/A_D8 CLOCK CLOCK <26>
S1_D0 B1 N2
A_CAD27/A_D0 LATCH LATCH <26>
S1_A0 B4
S1_A1 A_CAD26/A_A0
A4 A_CAD25/A_A1
S1_A2 E6
S1_A3 A_CAD24/A_A2 +3VS
B5 A_CAD23/A_A3
S1_A4 C6 B15
S1_A5 A_CAD22/A_A4 RSVD 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0603_10V4Z
B6 A_CAD21/A_A5 RSVD A16
S1_A6 G9 B16 1 1 1 2 2
S1_A25 A_CAD20/A_A6 RSVD
C7 A_CAD19/A_A25 RSVD A17
S1_A7 B7 C16 C132 C170 C173 C176 C163
S1_A24 A_CAD18/A_A7 RSVD
A7 A_CAD17/A_A24 RSVD D17
S1_A17 2 2 2 1 1
A10 A_CAD16/A_A17 RSVD C19
S1_IOWR# E11 D18 0.1U_0402_16V4Z 0.1U_0402_16V4Z
<26> S1_IOWR# A_CAD15/A_IOWR# RSVD
S1_A9 G11 E17
S1_IORD# A_CAD14/A_A9 RSVD
<26> S1_IORD# C11 A_CAD13/A_IORD# RSVD E19
S1_A11 B11 G15 +3VS
S1_OE# A_CAD12/A_A11 RSVD
<26> S1_OE# C12 A_CAD11/A_OE# RSVD F18
S1_CE2# B12 H14 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2.2U_0603_6.3V6K
<26> S1_CE2# A_CAD10/A_CE2# RSVD
S1_A10 A12 H15 1 1 1 1 1
S1_D15 A_CAD9/A_A10 RSVD C162
E12 A_CAD8/A_D15 RSVD G17
S1_D7 C13 K17 C156 C158 C131 C129
S1_D13 A_CAD7/A_D7 RSVD
F12 A_CAD6/A_D13 RSVD L13
S1_D6 2 2 2 2 2
A13 A_CAD5/A_D6 RSVD K18
C S1_D12 C14 L15 0.1U_0402_16V4Z 0.1U_0402_16V4Z C
S1_D5 A_CAD4/A_D12 RSVD
E13 A_CAD3/A_D5 RSVD L17
S1_D11 A14 L18
S1_D4 A_CAD2/A_D11 RSVD
B14 A_CAD1/A_D4 RSVD L19
S1_D3 E14 M17
A_CAD0/A_D3 RSVD +S1_VCC
M14
S1_REG# C5
PCI 7411 RSVD
RSVD M15
N19
<26> S1_REG# A_CC/BE3#/A_REG# RSVD
S1_A12 F9 N18 1 1
S1_A8 A_CC/BE2#/A_A12 RSVD
B10 A_CC/BE1#/A_A8 RSVD N15
S1_CE1# G12 M13 C171 C167
<26> S1_CE1# A_CC/BE0#/A_CE1# RSVD 0.1U_0402_16V4Z 0.1U_0402_16V4Z
RSVD P18
S1_A13 2 2
G10 A_CPAR/A_A13 RSVD P17
S1_A23 C8 P19
S1_A22 A_CFRAME#/A_A23 RSVD
A8 A_CTRDY#/A_A22 RSVD F15
S1_A15 B8 G18
S1_A20 A_CIRDY#/A_A15 RSVD
A9 A_CSTOP#/A_A20 RSVD K14
S1_A21 C9 M18
S1_A19 A_CDEVSEL#/A_A21 RSVD
E10 A_CBLOCK#/A_A19 RSVD K13
S1_A14 F10 G19
S1_WAIT# A_CPERR#/A_A14 RSVD
<26> S1_WAIT# B3 A_CSERR#/A_WAIT# RSVD H17
S1_INPACK# E7 J13
<26> S1_INPACK# A_CREQ#/A_INPACK# RSVD
S1_WE# B9 J17
<26> S1_WE# A_CGNT#/A_WE# RSVD
S1_BVD1 B2 H19
<26> S1_BVD1 A_CSTSCHG/A_BVD1(STSCHG/RI) RSVD
S1_WP C3 J19
<26> S1_WP A_CCLKRUN#/A_WP(IOIS16) RSVD
S1_A16 2 1 A16_CLK E9 J18
R117 33_0402_5% A_CCLK/A_A16 RSVD
C4 A_CINT#/A_READY(IREQ) RSVD B18
S1_RDY# E18
<26> S1_RDY# RSVD
S1_RST A6 J15
B <26> S1_RST A_CRST#/A_RESET RSVD B
RSVD F14
S1_BVD2 A2 A18 4510_2 2 1
<26> S1_BVD2 A_CAUDIO/A_BVD2(SPKR#) RSVD
H18 R187 4510@ 1K_0402_5%
S1_CD1# RSVD
<26> S1_CD1# C15 A_CCD1#/A_CD1# RSVD B19
S1_CD2# E5 F17
<26> S1_CD2# A_CCD2#/A_CD2# RSVD
S1_VS1 A3 C17
<26> S1_VS1 A_CVS1/A_VS1# RSVD
S1_VS2 E8 N13 Reserve for TI PCI4510
<26> S1_VS2 A_CVS2/A_VS2# RSVD
RSVD B17
S1_D14 B13 C18
S1_D2 A_CRSVD/A_D14 RSVD
D2 A_CRSVD/A_D2 RSVD F19
+3VS S1_A18 C10 N17
A_CRSVD/A_A18 RSVD
RSVD A15
R182 2 1 10K_0402_5% E2 K15
R179 2 A_USB_EN# RSVD
1 10K_0402_5% E1 B_USB_EN#
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

7411@ PCI7411GHK_PBGA288
G7
G8
G13
H13
J9
J10
J11
K9
K10
K11
L8
L9
L10
L11
L12
M8

S1_CD1# S1_CD2#

1 1
C166 C172
10P_0402_50V8J 10P_0402_50V8J
2 2
A A

Closed to Pin C15 Closed to Pin E5

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
PCI7421(1/2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:55 Sheet 23 of 53
5 4 3 2 1
 5 4 3 2 1

4510@ 0.1U_0402_16V4Z
C143
1 2 FILTER1
+AVDD_7421 +3VS
+3VS +3VS
0.1U_0402_16V4Z AVDD_7421 0.1U_0402_16V4Z L13 Close U12 pin V19
C146
0_0603_5% 7411@ 0.1U_0402_16V4Z
1 1 1 1 1 Change to 0 ohm 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
C582 1 1 1 1 1 1 2
C135 C127 C126 C134 C130 C169 C139
C149 1 2 1U_0603_25V4Z
2 2 2 2 2 C125 C128 C168 C175
D D
10U_1206_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 2 1
+AVDD_7421 +3VS 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0603_10V4Z

W10
M19
R13
R14
V17

V19
T18

W3
H1
U12B

VCCP
VCCP
VR_PORT
VR_PORT
AVDD
AVDD
AVDD

VDPLL_33
VDPLL_15
U2 PCI_AD31
AD31 PCI_AD30
AD30 V1
MC_PWR_CTRL_0 F1 V2 PCI_AD29
<25> MC_PWR_CTRL_0 MC_PWR_CTRL_0 AD29
1 2 F2 U3 PCI_AD28
R176 @ 0_0402_5% MC_PWR_CTRL_1 AD28 PCI_AD27
AD27 W2
SDCD# E3 V3 PCI_AD26
<25> SDCD# SD_CD# AD26
MSCD# F5 U4 PCI_AD25
<25> MSCD# MS_CD# AD25
SMCD# F6 V4 PCI_AD24
<25> SMCD# SM_CD# AD24
V5 PCI_AD23
R157 2 5IN1@ AD23
<25> MSCLK_SDCLK 1 33_0402_5% AD22 U5 PCI_AD22
R164 2 5IN1@
1 33_0402_5% G5 R6 PCI_AD21
<25> SMELWP# MS_CLK/SD_CLK/SM_EL_WP# AD21
MSBS_SDCMD_SMWE2 F3 P6 PCI_AD20
<25> MSBS_SDCMD_SMWE2 MSDATA3_SDDAT3_SMD3 MS_BS/SD_CMD/SM_WE# AD20 PCI_AD19
<25> MSDATA3_SDDAT3_SMD3 H5 MS_DATA3/SD_DAT3/SM_D3 AD19 W6
MSDATA2_SDDAT2_SMD2 G3 V6 PCI_AD18
<25> MSDATA2_SDDAT2_SMD2 MSDATA1_SDDAT1_SMD1 MS_DATA2/SD_DAT2/SM_D2 AD18 PCI_AD17 PCI_AD[0..31]
<25> MSDATA1_SDDATA1_SMD1 G2 MS_DATA1/SD_DAT1/SM_D1 AD17 U6 PCI_AD[0..31] <17,29>
MSDATA0_SDDAT0_SMD0 G1 R7 PCI_AD16
<25> MSDATA0_SDDAT0_SMD0 MS_SDIO(DATA0)/SD_DAT0/SM_D0 AD16 PCI_AD15
AD15 V9
U9 PCI_AD14
R152 5IN1@ AD14
<25> SMRE# 1 2 33_0402_5% J5 SD_CLK/SM_RE#/SC_GPIO1 AD13 R9 PCI_AD13
C SMALE J3 N9 PCI_AD12 C
<25> SMALE SMD4 SD_CMD/SM_ALE/SC_GPIO2 AD12 PCI_AD11
<25> SMD4 H3 SD_DAT0/SM_D4/SC_GPIO6 AD11 V10
SMD5 J6 U10 PCI_AD10
<25> SMD5 SMD6 SD_DAT1/SM_D5/SC_GPIO5 AD10 PCI_AD9
<25> SMD6 J1 SD_DAT2/SM_D6/SC_GPIO4 AD9 R10
SMD7 J2 N10 PCI_AD8
C63 <25> SMD7 SD_DAT3/SM_D7/SC_GPIO3 AD8
1 2 1U_0603_25V4Z TPBIAS0
<25> SDWP_SMCE#
SDWP_SMCE# H7 SD_WP/SM_CE# AD7 V11 PCI_AD7 CLK_SD_48M 2 R148 1
1394@ U11 PCI_AD6 4510@ 1K_0402_5%
AD6 PCI_AD5
AD5 R11
2

SMCLE J7 W12 PCI_AD4

<25> SMCLE SMRB# SM_CLE/SC_GPIO0 AD4 PCI_AD3
<25> SMRB# K1 SM_R/B AD3 V12
R59 R58 K2 U12 PCI_AD2 Reserve for TI PCI4510
56.2_0402_1% 56.2_0402_1% SM_PHYS_WP#/SC_FCB AD2 PCI_AD1
AD1 N11
JP22 1394@ 1394@ W13 PCI_AD0
1

TPA0+ +3VS AD0

4 4 L2 RSVD
6 3 TPA0- K5
G 3 TPB0+ RSVD
5 G 2 2 K3 RSVD C/BE3# W4 PCI_C/BE#3 <17,29>
1 TPB0- R143 1 2 10K_0402_5% K7 W7
1 RSVD C/BE2# PCI_C/BE#2 <17,29>
L1 W9
RSVD
PCI7411 C/BE1# PCI_C/BE#1 <17,29>
2

TYCO_1470383-2 L3 W11
1394@ RSVD C/BE0# PCI_C/BE#0 <17,29>
<26> VCCD1# L5 RSVD
R62 R60 P9
56.2_0402_1% 56.2_0402_1% PAR PCI_PAR <17,29>
P12 TEST0 FRAME# V7 PCI_FRAME# <17,29>
1394@ 1394@ W17 R8
1

FILTER1 NC TRDY# PCI_TRDY# <17,29>

T19 RSVD IRDY# U7 PCI_IRDY# <17,29>
STOP# W8 PCI_STOP# <17,29>
2

1 DEVSEL# N8 PCI_DEVSEL# <17,29>

+3VS CLK_SD_48M M1 W5 PCM_ID 2 1 PCI_AD20
<14> CLK_SD_48M CLK_48 IDSEL
R61 C68 V8 R112 100_0402_5%
5.11K_0402_1% 220P_0402_50V7K PERR# PCI_PERR# <17,29>
SERR# U8 PCI_SERR# <17,29>
B 1394@ 2 1394@ R109 1 B
2 4.7K_0402_5% R17 U1 PCI_REQ#2 <17>
1

PHY_TEST_MA REQ#
GNT# T2 PCI_GNT#2 <17>

PCICLK P5 CLK_PCI_PCM <14>

R138 1 2 6.34K_0402_1% U18 R3 R123 2 1 0_0402_5%
R0 PCIRST# PCI_RST# <17,29,34,35>
U19 T1 2 1 R120 2 1 @ 0_0402_5%
R1 GRST# PLT_RST# <6,16,17,19,21,22,27,34,35>
TPBIAS0 U15 T3 R128 0_0402_5%
TPA0+ TPBIAS0 RI_OUT#/PME#
V15 TPA0P
TPA0- W15 R2 R136 2 1 4.7K_0402_5% +3VS
TPB0+ TPA0N SUSPEND#
V14 TPB0P
TPB0- W14 L7 PCM_SPK#
TPB0N SPKROUT PCM_SPK# <30>
C116 1 2 1U_0603_25V4Z TPBIAS1 TPBIAS1 U17
W D@ TPA1+ TPBIAS1 PCI_PIRQA#
V18 TPA1P MFUNC0 N3 PCI_PIRQA# <17>
TPA1- W18 M5 PCI_PIRQB#
TPA1N MFUNC1 PCI_PIRQB# <17>
2

TPB1+ V16 P1 PCI_PIRQC# +3VS

TPB1P MFUNC2 PCI_PIRQC# <17>
TPB1- W16 P2 SERIRQ
TPB1N MFUNC3 SERIRQ <19,33,34,35>
R115 R114 AVDD_7421 R101 1 2 1K_0402_5% M11 P3 PCI_PIRQD#
56.2_0402_1% CPS MFUNC4 PCI_PIRQD# <17>
56.2_0402_1% R116 2 1 4.7K_0402_5% P15 N5 5IN1_LED#
CNA MFUNC5 5IN1_LED <25,39>
W D@ W D@ R19 R1 R144 1 2 10K_0402_5%
1

TPA1+ XO MFUNC6
<40> TPA1+ R18 XI
TPA1- C589 18P_0402_50V8J R12 M3 R153 1 2 220_0402_5% R137 1 2 @ 10K_0402_5%
<40> TPA1- PC0(TEST1) SCL
TPB1+ U13 M2 R149 1 2 220_0402_5%
<40> TPB1+ PC1(TEST2) SDA
2

VSSPLL
TPB1- VSSPLL
<40> TPB1- V13 PC2(TEST3)
AGND
AGND
AGND

X3 H2
VR_EN#
2

24.576MHz_16P_3XG-24576-43E1

2
1
1

R111 R110 7411@ PCI7411GHK_PBGA288 R165 C148 PCM_SPK# R103 1 2 10K_0402_5%

N12
U14
U16

P14
T17

56.2_0402_1% 56.2_0402_1% C587 18P_0402_50V8J 220_0402_5% 0.1U_0402_16V4Z

W D@ W D@
1

A 2 A

1
2

1
LED R MAY CHANGE TO 150OHM
R98 C118
5.11K_0402_1% 220P_0402_50V7K
W D@ 2 W D@ Security Classification Compal Secret Data Compal Electronics, Inc.
1

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title

PCI7421(2/2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:54 Sheet 24 of 53
5 4 3 2 1
 5 4 3 2 1

D D

5 in 1 CardReader Conn.
JP27
+VCC_5IN1 41 XD-VCC SD-VCC 15 +VCC_5IN1
MS-VCC 9
MSDATA0_SDDAT0_SMD0 33
<24> MSDATA0_SDDAT0_SMD0 XD-D0
MSDATA1_SDDATA1_SMD1 34 4 IN 1 CONN 16 MSCLK_SDCLK
<24> MSDATA1_SDDATA1_SMD1 XD-D1 SD_CLK MSCLK_SDCLK <24>
MSDATA2_SDDAT2_SMD2 35 19 MSDATA0_SDDAT0_SMD0
<24> MSDATA2_SDDAT2_SMD2 XD-D2 SD-DAT0
MSDATA3_SDDAT3_SMD3 36 20 MSDATA1_SDDATA1_SMD1
+3VS <24> MSDATA3_SDDAT3_SMD3 XD-D3 SD-DAT1
SMD4 37 11 MSDATA2_SDDAT2_SMD2
<24> SMD4 XD-D4 SD-DAT2
SMD5 38 12 MSDATA3_SDDAT3_SMD3
<24> SMD5 XD-D5 SD-DAT3
SMD6 39 13 MSBS_SDCMD_SMWE2
<24> SMD6 XD-D6 SD-CMD
R245 2 1 10K_0402_5% SDCD# SMD7 40 21 SDCD#
<24> SMD7 XD-D7 SD-CD-SW SDCD# <24>
SD-CD-COM 22
R243 2 1 10K_0402_5% MSCD# MSBS_SDCMD_SMWE2 30 43 SDWP_SMCE#
<24> MSBS_SDCMD_SMWE2 XD-WE SD-WP-SW SDWP_SMCE# <24>
SMELWP# 31 44
<24> SMELWP# XD-WP SD-WP-COM
R163 2 1 10K_0402_5% SMCD# SMALE 29
<24> SMALE XD-ALE
SMCD# 23 8 MSCLK_SDCLK
<24> SMCD# XD-CD MS-SCLK
C SMRB# 2 1 25 4 MSDATA0_SDDAT0_SMD0 C
<24> SMRB# XD-R/B MS-DATA0
R168 5IN1@ 0_0402_5% 26 3 MSDATA1_SDDATA1_SMD1
+VCC_5IN1 <24> SMRE# XD-RE MS-DATA1
SDWP_SMCE# 27 5 MSDATA2_SDDAT2_SMD2
<24> SDWP_SMCE# XD-CE MS-DATA2
SMCLE 28 7 MSDATA3_SDDAT3_SMD3
<24> SMCLE XD-CLE MS-DATA3
6 MSCD#
MS-INS MSCD# <24>
R162 2 1 2.2K_0402_5% SMRB# 32 2 MSBS_SDCMD_SMWE2
5IN1@ XD-GND MS-BS
24 XD-GND SD-GND 14
SD-GND 17
R161 2 1 2.2K_0402_5% SDWP_SMCE# 42 1
5IN1@ N.C. MS-GND
18 N.C. MS-GND 10
5IN1@ TAITW_R007-530-L3

+VCC_5IN1

1U_0603_10V4Z 4.7K_0402_5%
5IN1@ @
SD/XD/MS PWR SWITCH

2
B +3VS B
2 2
+3VS C200 C209 R204
C194
2

0.1U_0402_16V4Z
R201 +3VS +VCC_5IN1 5IN1@ 1 1

1
2
10K_0402_5%
U21 R199
1 8 10K_0402_5% 4.7U_0805_10V4Z
1

GND OUT 5IN1@ 5IN1@

R200 2 IN OUT 7
3 6

1
IN OUT +3VS
<24> MC_PWR_CTRL_0 2 1 4 EN# FLG 5
0_0402_5%
5IN1@ G528_SO8
1

2
D 5IN1@ 0.1U_0402_16V4Z
2 Q17 C180 R580 2 5IN1@ 2
<24,39> 5IN1_LED
G @ 2N7002_SOT23 100_0402_5%
2

S 5IN1@ C208 C192 C198

3

R203 @ 0.1U_0402_16V4Z 4.7U_0805_10V4Z 1U_0603_10V4Z

1
5IN1@ 1 1
5IN1@
10K_0402_5%

1
D
1

Q60 2 MC_PWR_CTRL_0
G
S 2N7002_SOT23
3

5IN1@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
5 IN 1 Stocket
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:58 Sheet 25 of 53
5 4 3 2 1
 5 4 3 2 1

Power Switch for PCMCIA

DATA
For 7411
<23> DATA
<23> CLOCK CLOCK
LATCH +S1_VCC +S1_VPP +S1_VCC +S1_VPP
<23> LATCH
+3VS
D <16,30,32,35,37,38,42,49> SUSP# D
U38
C152 C157
3 20 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DATA 12V
4 CLOCK 12V 7
2 1 5 C161 <23> S1_A[0..25] S1_A[0..25] C165
+3VS LATCH
R495 7464@ 10K_0402_5% 12 7464@ 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
RESET# C573 S1_D[0..15]
15 OC# NC3 14 <23> S1_D[0..15]
7464@ 0.01U_0402_16V7K+S1_VPP 21 13 7464@ 4.7U_0805_10V4Z
SHDN# 3.3V C571
2 1
C564 20mil
2 1 8 AVPP NC4 24 +5VS
C563 19 2
7464@ 1U_0402_6.3V4Z +S1_VCC NC0 5V C560 0.1U_0402_16V4Z
5V 1
7464@
2 1
C570
9 AVCC GND 11 C561 4.7U_0805_10V4Z
7464@
CardBus Socket
40mil 10 AVCC
7464@ 10U_1206_16V4Z 17 23
NC1 NC5 JP12
18 NC2 NC6 22
NC7 16 GND 1
NC8 6 GND 35
2 S1_D3
DATA3 S1_CD1#
CD1# 36 S1_CD1# <23>
7464@ TPS2220ADBR_SSOP24 3 S1_D4
DATA4 S1_D11
DATA11 37
4 S1_D5
DATA5 S1_D12
DATA12 38
5 S1_D6
C
DATA6 S1_D13 C
DATA13 39
6 S1_D7
DATA7 S1_D14
DATA14 40
7 S1_CE1#
CE1# S1_CE1# <23>
41 S1_D15
DATA15 S1_A10
8
For 4510 ADD10
CE2# 42
9
S1_CE2#
S1_OE#
S1_CE2# <23>
OE# S1_OE# <23>
43 S1_VS1
VS1# S1_VS1 <23>
10 S1_A11
+S1_VCC ADD11 S1_IORD#
IORD# 44 S1_IORD# <23>
U11 11 S1_A9
ADD9 S1_IOWR#
VCC 13 1 2 IOWR# 45 S1_IOWR# <23>
12 C569 12 S1_A8
VCC 4515@ 10U_0805_10V4Z ADD8 S1_A17
9 12V VCC 11 ADD17 46
13 S1_A13
+S1_VPP ADD13 S1_A18
ADD18 47
14 S1_A14
4515@ 0.01U_0402_16V7K ADD14 S1_A19
ADD19 48
+5VS 10 1 2 15 S1_WE#
VPP WE# S1_WE# <23>
C103 49 S1_A20
4515@ 0.1U_0402_16V4Z ADD20 S1_RDY#
5 5V 1 2 READY 16 S1_RDY# <23>
6 C100 50 S1_A21
5V ADD21
4515@ 1U_0402_6.3V4Z VCC 17 +S1_VCC
C102 C101 1 CLOCK 51
VCCD0 F_VCCD1# VCC
VCCD1 2 2 1 VCCD1# <24> VPP 18 +S1_VPP
15 LATCH R102 52
+3VS VPPD0 DATA 4515@ 0_0402_5% VPP S1_A16
VPPD1 14 ADD16 19
4515@ 4.7U_0805_10V4Z 53 S1_A22
B ADD22 S1_A15 B
3 3.3V ADD15 20
4 8 54 S1_A23
3.3V OC ADD23
SHDN

21 S1_A12
GND

C104 C105 ADD12 S1_A24

ADD24 55
22 S1_A7
4515@ TPS2211AIDBR_SSOP16 ADD7 S1_A25
56
7

16

ADD25 S1_A6
ADD6 23
4515@ 4.7U_0805_10V4Z 57 S1_VS2
VS2# S1_VS2 <23>
24 S1_A5
4515@ 0.1U_0402_16V4Z ADD5 S1_RST
RESET 58 S1_RST <23>
1

25 S1_A4
R91 ADD4 S1_WAIT#
WAIT# 59 S1_WAIT# <23>
4.7K_0402_5% 26 S1_A3
ADD3 S1_INPACK#
4515@ INPACK# 60 S1_INPACK# <23>
27 S1_A2
2

ADD2 S1_REG#
REG# 61 S1_REG# <23>
28 S1_A1
+3VS ADD1 S1_BVD2
BVD2 62 S1_BVD2 <23>
29 S1_A0
ADD0 S1_BVD1
BVD1 63 S1_BVD1 <23>
30 S1_D0
DATA0 S1_D8
DATA8 64
31 S1_D1
DATA1 S1_D9
69 GND DATA9 65
70 32 S1_D2
GND DATA2 S1_D10
DATA10 66
33 S1_WP
WP S1_WP <23>
67 S1_CD2#
CD2# S1_CD2# <23>
A GND 34 A
GND 68
SANTA_130606-1_LT

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
CardBUS Socket
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:54 Sheet 26 of 53
5 4 3 2 1
 5 4 3 2 1

U36
+3VALW
PCIE_PTX_C_IRX_P1 C555 1 2 0.1U_0402_16V4Z PCIE_PTX_IRX_P1 49 LED 59 LAN_ACTIVITY#
<19> PCIE_PTX_C_IRX_P1 TX_P LED_ACTn LAN_ACTIVITY# <28,40>
PCIE_PTX_C_IRX_N1 C554 1 2 0.1U_0402_16V4Z PCIE_PTX_IRX_N1 50 PCI-E 60
<19> PCIE_PTX_C_IRX_N1 TX_N LED_LINK10/100n
PCIE_ITX_C_PRX_P1 54 62
<19> PCIE_ITX_C_PRX_P1 RX_P LED_LINK1000n
PCIE_ITX_C_PRX_N1 53 63 LAN_LINK#
<19> PCIE_ITX_C_PRX_N1 RX_N LED_LINKn LAN_LINK# <28,40>

1
<19> ICH_PCIE_WAKE# 6 WAKEn
55 46 R492
<14> CLK_PCIE_LAN REFCLKP TESTMODE +LAN_AVDD25
56 TEST 29 4.7K_0402_5%
<14> CLK_PCIE_LAN# REFCLKN TSTPT

3
D PLT_RST# 5 D
<6,16,17,19,21,22,24,34,35> PLT_RST# PERSTn
64 +LAN_AVDD25

2
LAN_MDI0+ VDD25 LAN_CTRL12
<28> LAN_MIDI0+ 17 MDIP0 1
LAN_MDI0- 18 POWER 19 +LAN_AVDDL 1 2 Q52
<28> LAN_MIDI0- LAN_MDI1+ MDIN0 AVDDL L12 0_0603_5% BCP69_SOT223
<28> LAN_MIDI1+ 20 MDIP1 AVDDL 22
LAN_MDI1- 21 Media & 28

2
4
<28> LAN_MIDI1- LAN_MDI2+ MDIN1 AVDDL
<28> LAN_MIDI2+ 26 MDIP2 AVDDL 32 +LAN_AVDDL
LAN_MDI2- 27 GROUND 51
<28> LAN_MIDI2- LAN_MDI3+ MDIN2 AVDDL C488 0.1U_0402_16V4Z
<28> LAN_MIDI3+ 30 MDIP3 AVDDL 52 40mil
LAN_MDI3- 31 57 1 2 +LAN_VDD12
<28> LAN_MIDI3- MDIN3 AVDDL
1
VPD_CLK 38 23
VPD_DATA VPD_CLK AVDD C557
+3VALW
41 VPD_DATA EEPROM
1 +3VALW 4.7U_0805_10V4Z
VDDO_TTL 2
34 SPI_DO VDDO_TTL 8
35 SPI_DI FLASH VDDO_TTL 40
R458 2 1 4.7K_0402_5% VPD_CLK 37 MEMORY 45
R459 SPI_CLK VDDO_TTL
2 1 4.7K_0402_5% VPD_DATA 36 SPI_CS VDDO_TTL 61
LAN_X1 15 2 +LAN_VDD12
LAN_X2 XTALI VDD
14 XTALO CLOCK VDD 7
VDD 13
+3VALW R460 2 1 10K_0402_5% 10 33
R453 2 LOM_DISABLEn VDD
1 10K_0402_5% 12 VAUX_AVLBL VDD 39
11 44 +3VALW
R478 2 SWITCH_VCC VDD
1 10K_0402_5% 47 VMAIN_AVLBL VDD 48
9 SWITCH_VAUX VDD 58
24 HSDACP
8053@ 25 65
HSDACN EPAD

1
C R445 2 1 4.87K_0402_1% 16 Analog C
LAN_CTRL25 RSET R493
4 CTRL25 SMCLK/NC 42
LAN_CTRL12 3 43 4.7K_0402_5%
CTRL12 SMDATA/NC

3
2
R445 -- 2K for 88E8036 88E8053_QFN64 LAN_CTRL25 1
4.87K for 88E8053 8053@ Q53
BCP69_SOT223

2
4
+3VALW
40mil
+LAN_AVDD25
1 1
+3VALW
C558 C556
4.7U_0805_10V4Z 0.1U_0402_16V4Z
C566 2 2
1 2 0.1U_0402_16V4Z 1 1 1 1 1
C516 C531 C508 C509 C551

U41 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

2 2 2 2 2
8 VCC A0 1
7 WP A1 2
VPD_CLK 6 3
VPD_DATA SCL A2
5 SDA GND 4
AT24C16AN-10SI-2.7_SO8

B B
1

+LAN_AVDDL
R501

100K_0402_5%
2

1 1 1 1 1 1
C487 C490 C489 C548 C547 C549
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2

+LAN_VDD12

Y3
LAN_X1 LAN_X2 1 1 1 1 1 1
C550 C532 C492 C514 C517 C513
25MHZ_20P_1BX25000CK1A 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 2 2 2 2 2 2
C482 C491
A A
27P_0402_50V8J 27P_0402_50V8J
2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
LAN Marvell 88E8053
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:56 Sheet 27 of 53
5 4 3 2 1
 5 4 3 2 1

Q41
unpop when use 88E8036(10/100) +3V 3 1 1 2 T=10mil LAN_ACT
R312

47K
300_0402_5%

10K
DTA114YKA_SC59

2
LAN_ACTIVITY#
<27,40> LAN_ACTIVITY#
1 1
C321 C322

D Q45 D
2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z
8053@
+3V 3 1 1 2 T=10mil LAN_LINK
R318

47K
+LAN_AVDD25 300_0402_5%
TST1284B(SP050001X00) for 88E8036(10/100)

10K
1

1
R344
49.9_0402_1% GST5009(SP050005600) for 88E8053(GbE) DTA114YKA_SC59

2
R343 8053@ R345 R346
49.9_0402_1% 49.9_0402_1% 49.9_0402_1% LAN_LINK#
<27,40> LAN_LINK#
8053@
2

2
RJ45_MDI1-_C
<27> LAN_MIDI1-
T1
1 2
R618 @ 0_0402_5%
12 13 RJ45_MDI1+_C L23
<27> LAN_MIDI1+ TD4- MX4- RJ45_MDI1-_C RJ45_MDI1-
11 TD4+ MX4+ 14 1 1 2 2
10 15 MCT2
TCT4 MCT4
9 16 RJ45_MDI3-_C RJ45_MDI1+_C 4 3 RJ45_MDI1+
<27> LAN_MIDI3- TD3- MX3- 4 3
8 TD3+ MX3+ 17
7 18 WCM2012F2S-900T04_0805
TCT3 MCT3
6 TD2- MX2- 19 1 2
5 20 RJ45_MDI3+_C R619 @ 0_0402_5%
<27> LAN_MIDI3+ TD2+ MX2+
4 TCT2 MCT2 21
1 2
C 3 22 R620 @ 0_0402_5% C
TD1- MX1- RJ45_MDI2-_C L24
<27> LAN_MIDI2- 2 TD1+ MX1+ 23
1 24 MCT1 RJ45_MDI3-_C 1 1 2 RJ45_MDI3-
TCT1 MCT1 2

0.5u_GST5009 RJ45_MDI3+_C 4 3 RJ45_MDI3+

8053@ RJ45_MDI2+_C 4 3
<27> LAN_MIDI2+ WCM2012F2S-900T04_0805

1 2
RJ45_MDI0-_C R621 @ 0_0402_5%
<27> LAN_MIDI0-
1 2
R622 @ 0_0402_5%
L25
RJ45_MDI0+_C RJ45_MDI2-_C 1 1 2 RJ45_MDI2-
<27> LAN_MIDI0+ 2
1

RJ45_MDI2+_C 4 3 RJ45_MDI2+
R342 R341 R340 R339 4 3
49.9_0402_1% 49.9_0402_1% WCM2012F2S-900T04_0805

1
49.9_0402_1% 49.9_0402_1%
8053@ 8053@ 1 2
2

R328 R329 R623 @ 0_0402_5%

75_0402_1% 75_0402_1% 1 2
1 1 R624 @ 0_0402_5%

2
C320 C319 L26
RJ45_MDI0-_C 1 1 2 RJ45_MDI0-
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2
B 2 8053@ 2 B
RJ45_MDI0+_C 4 3 RJ45_MDI0+
4 3
WCM2012F2S-900T04_0805

1 2
R625 @ 0_0402_5% EMI Solution Reserve.

RJ45_MDI3- R326 1 2 0_0402_5% 8036@ JP5

RJ45_MDI3+ R325 1 2 0_0402_5% 8036@ LAN_LINK 1
LAN_ACT 1
2 2 1 2
RJ45_MDI2- R323 1 2 0_0402_5% 8036@ 3 R615 0_0603_5%
RJ45_MDI2+ R324 1 0_0402_5% 8036@ 3
2 4 4
RJ45_GND 5 5
1

RJ45_MDI3- 6 1 2
<40> RJ45_MDI3- RJ45_MDI3+ 6 R616 0_0603_5%
7
reseved for 88E8036(10/100) R330 R331 <40> RJ45_MDI3+ RJ45_GND 8
7
8
75_0402_1% 75_0402_1% RJ45_MDI2- 9
<40> RJ45_MDI2- RJ45_MDI2+ 9
10 1 2
2

<40> RJ45_MDI2+ RJ45_GND 10 R617 0_0603_5%

11 11
RJ45_MDI1- 12
RJ45_GND <40> RJ45_MDI1- RJ45_MDI1+ 12
RJ45_GND <40> <40> RJ45_MDI1+ 13 13
RJ45_GND 14
RJ45_MDI0- 14
<40> RJ45_MDI0- 15 15
RJ45_MDI0+ 16
<40> RJ45_MDI0+ 16

A A
ACES_87213-1600 DGND RJ45_GND

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
LAN Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:55 Sheet 28 of 53
5 4 3 2 1
 A B C D E

1
+3V 1

C277 1 2 0.1U_0402_16V4Z
KILL@ PCI_AD[0..31]
PCI_AD[0..31] <17,24>

5
U29
1 MINI_PCI SOCKET

P
<35> WL_OFF# B
Y 4
<35,36,38> KILL_SW# 2 A

G
TIP
TC7SH08FU_SSOP5 JP30

3
KILL@ 1 2 RING
LAN RESERVED 1 2
KEY KEY
3 3 4 4
5 5 6 6
7 7 8 8
D21 9 10 LAN RESERVED
RB751V_SOD323 9 10
11 11 12 12
KILL@
1 2 13 14
+3VS_MINIPCI 13 14
15 15 16 16
L9 PCI_PIRQH# 17 18 W=30mils
<17> PCI_PIRQH#
W=40mils 17 18 +5VS_MINIPCI
1 2 19 20 PCI_PIRQG#
+3V 19 20 PCI_PIRQG# <17>
0_0603_5% 21 22
21 22 W=40mils +3VS_MINIPCI
23 23 24 24 +3V
CLK_PCI_MINI 25 26 PCI_RST# L10
<14> CLK_PCI_MINI 25 26 PCI_RST# <17,24,34,35> W=40mils
27 27 28 28 1 2 +3V
29 30 0_0603_5%
<17> PCI_REQ#1 29 30 PCI_GNT#1 <17>
31 31 32 32
PCI_AD31 33 34
33 34 PME# <33,34,35>
2 PCI_AD29 35 36 2 1 2
35 36 CH_CLK <36>
37 38 PCI_AD30 R589 BT@0_0402_5%
PCI_AD27 37 38
39 39 40 40
PCI_AD25 41 42 PCI_AD28
R588 2 41 42
<36> CH_DATA 1BT@0_0402_5% 43 43 44 44 PCI_AD26
45 46 PCI_AD24
<17,24> PCI_C/BE#3 PCI_AD23 45 46 MINI_IDSEL1
47 47 48 48 2 PCI_AD18 IDSEL : PCI_AD18
49 50 R287 100_0402_5%
PCI_AD21 49 50 PCI_AD22
51 51 52 52
PCI_AD19 53 54 PCI_AD20
53 54
55 55 56 56 PCI_PAR <17,24>
PCI_AD17 57 58 PCI_AD18
57 58 PCI_AD16
<17,24> PCI_C/BE#2 59 59 60 60
<17,24> PCI_IRDY# 61 61 62 62
63 63 64 64 PCI_FRAME# <17,24>
CLK_PCI_MINI 65 66
<19,33,34> PM_CLKRUN# 65 66 PCI_TRDY# <17,24>
<17,24> PCI_SERR# 67 67 68 68 PCI_STOP# <17,24>
1

69 69 70 70
R302 71 72
@ 33_0402_5% <17,24> PCI_PERR# 71 72 PCI_DEVSEL# <17,24>
<17,24> PCI_C/BE#1 73 73 74 74
PCI_AD14 75 76 PCI_AD15
75 76 PCI_AD13
77 78
2

PCI_AD12 77 78 PCI_AD11
79 79 80 80
1 PCI_AD10 81 82
81 82 PCI_AD9
83 83 84 84
C291 PCI_AD8 85 86
@ 10P_0402_50V8J PCI_AD7 85 86 PCI_C/BE#0 <17,24>
87 87 88 88
2 PCI_AD6
89 89 90 90
PCI_AD5 91 92 PCI_AD4
3 91 92 PCI_AD2 3
93 93 94 94
PCI_AD3 95 96 PCI_AD0
W=30mils 95 96
+5VS_MINIPCI 97 97 98 98
PCI_AD1 99 100
99 100
101 101 102 102 +5VS_MINIPCI
103 103 104 104
105 105 106 106 1 2 2 1
107 107 108 108
109 110 C274 C286 C287 C280
109 110 @ 1000P_0402_50V7K @ 0.1U_0402_16V4Z @ 0.1U_0402_16V4Z @ 10U_1206_16V4Z
111 111 112 112
2 1 1 2
113 113 114 114
115 115 116 116
117 117 118 118
119 119 120 120
121 121 122 122
1 2 W=30mils 123 124 W=20mils
+5VS 123 124 +3V
L11 0_0603_5% 2
TYCO_1470422-3
0603 C273
0.1U_0402_16V4Z
+5VS_MINIPCI 1
+3VS_MINIPCI

2 2 2 2 2 1
C289 C290 C288 C270 C269 C271
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_1206_16V4Z
1 1 1 1 1 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
Mini PCI Slot
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:56 Sheet 29 of 53
A B C D E
 A B C D E F G H

+3V 28.7K for Module Design (VDDA = 4.702)

C272 +VDDA
1 2 0.1U_0402_16V4Z (output = 250 mA)
60mil

1
U23
U31A R288 40mil

14
+5VALW 4 VIN VOUT 5 +VDDA
SN74LVC14APWLE_TSSOP14 10K_0402_5% 1 1

2
C279 C210 C213 2 6 R533 1 4.85V

P
R295 C276 DELAY SENSE or ADJ 30K_0402_1%
<35> BEEP# 1 O 2 2 1 1 2

2
I 1U_0402_6.3V4Z 22U_1206_16V4Z_V1 0.1U_0402_16V4Z C212
560_0402_5% 7 ERROR CNOISE 1

G
1U_0402_6.3V4Z 2 2 10U_1206_16V4Z
2 1
2
8 3 1

1
SD GND

1
C629
1 R291 +VDDA=V power SI9182DH-AD_MSOP8 1

1
10K_0402_5% R612 2 1 0_0402_5%
<35,39,41,42,48> SYSON 2
R613 2 1 @ 0_0402_5% R532
<16,26,32,35,37,38,42,49> SUSP#

2
+3V C275 0.1U_0402_16V4Z 10K_0402_1%
1 2 MONO_IN +VDDA=VS power

2
U31B
14

SN74LVC14APWLE_TSSOP14 1U_0402_6.3V4Z

1
C285 C 1 2 R248 2 1 @ 6.8K_0402_5%
P

R300 Q32
<24> PCM_SPK# 3 I O 4 2 1 1 2 2 R289
560_0402_5% B 2SC2411K_SC59 2.4K_0402_5% R249 2 1 @ 6.8K_0402_5%
G

1U_0402_6.3V4Z E

3
R247 2 1 1 2 C215 LINEL
<31> LINE_IN_L
7

W D@ 1U_0402_6.3V4Z
C284 W D@ 6.8K_0402_5%
R299 R250 2
2 1 1 2 <31> LINE_IN_R 1 1 2 C218 LINER
560_0402_5% W D@ 1U_0402_6.3V4Z

1
1U_0402_6.3V4Z W D@ 6.8K_0402_5% 1 1
+3V D16
R296 RB751V_SOD323 C216 C217
U31C 10K_0402_5% WOD@1U_0402_6.3V4Z WOD@1U_0402_6.3V4Z
14

SN74LVC14APWLE_TSSOP14 2 2

2
P

<19> SB_SPKR 5 I O 6
G

AC97 Codec
7

2 2
R267 1 2 0_0603_5% +3VS
+AVDD_AC97
0.1U_0402_16V4Z +AC97_DVDD R268 1 2@ 0_0603_5% +3V
L8 Change to 0 ohm
1 2 0.1U_0402_16V4Z 1 1 1
+VDDA
FBM-L10-160808-301-T_0603 1 1 1 C651
C657 C232 C237 C248 Reserve for Hardware EQ
C230 10U_1206_16V4Z
10U_0805_10V4Z 2 2 2

25

38

9
2 2 2 +5VAMP
0.1U_0402_16V4Z 0.1U_0402_16V4Z Close to U42 JP31

AVDD1

AVDD2

DVDD1

DVDD2
LINE_OUT_L R592 8
1 2@ 0_0402_5% EQ_IN_LEFT
7
LINE_OUT_R R593 1 2@ 0_0402_5% EQ_IN_RIGHT
C233 1U_0603_10V4Z LINE_OUT_L R594 6
1 2 14 AUX_L LINE_OUT_L 35 1 2 0_0402_5% 5
R595 1 2 0_0402_5%
C633 1U_0603_10V4Z LINE_OUT_R R596 4
1 2 15 AUX_R LINE_OUT_R 36 <32> AMP_LEFT 1 2@ 0_0402_5% EQ_OUT_LEFT
3
R597 1 2@ 0_0402_5% EQ_OUT_RIGHT
<32> AMP_RIGHT 2
<35> SPKSEL 16 JD2 MONO_OUT/VREFOUT3 37 1
<32,35> NBA_PLUG
C224 1 2 17 39 @ ACES_20301-0800
JD1 HP_OUT_L HP_OUT_L <31>
1U_0603_10V4Z
R242 2 1 6.8K_0402_5% LINEL 23 41
LINE_IN_L HP_OUT_R HP_OUT_R <31>
R254 2 1 6.8K_0402_5% LINER 24 LINE_IN_R AUDIO_AC_BITCLK R542 1
BIT_CLK 6 2 33_0402_5% ICH_AC_BITCLK <18,36>
R534 2 1 20K_0402_5% C630 1 2 0.1U_0402_16V4Z 18
3 <22> INT_CD_L CD_L 3
8 R541 1 2 22_0402_5%
SDATA_IN ICH_AC_SDIN0 <18>
R539 2 1 20K_0402_5% C631 1 2 0.1U_0402_16V4Z 20
<22> INT_CD_R CD_R
2 R545 1 2 0_0402_5%
CD_GNA C632 1 1U_0603_10V4Z XTL_IN CLK_14M_CODEC <14>
2 19 CD_GND
1 2 C_MIC 21
<32> MIC MIC1
C234 1U_0603_10V4Z 1 2 SMB_CLK
<4,35,40> EC_SMB_CK2
1 2 22 3 R561 0_0402_5%
R537 20K_0402_5% CD_GNA C235 1U_0603_10V4Z MIC2 XTL_OUT SMB_DATA
<22> CD_AGND 2 1 <4,35,40> EC_SMB_DA2 1 2
1 2 13 29 C645 1 2 1000P_0402_50V7K R563 0_0402_5%
C225 0.1U_0402_16V4Z PHONE AFILT1
1

MONO_IN 12 30 C646 1 2 1000P_0402_50V7K

R536 R246 PC_BEEP AFILT2
6.8K_0402_5% 28
VREFOUT +AUD_VREF
0_0402_5% R538 2 1 AUDIO_AC_RST# 11
<18,36> ICH_AC_RST# RESET#
22_0402_5% 27 1U_0402_6.3V4Z
2

R257 2 VREF
<18,36> ICH_AC_SYNC 1 AUDIO_AC_SYNC 10 SYNC
22_0402_5% 32 C242 1 2 0.01U_0402_16V7K
R543 2 DCVOL
<18,36> ICH_AC_SDOUT 1 AUDIO_AC_SDOUT 5 SDATA_OUT
C236 1 2 1U_0603_10V4Z
22_0402_5% 1 1
SMB_DATA 45 31 C649 1 2 1U_0603_10V4Z C642
SDA NC R547 1
1 2 46 XTLSEL VREFOUT2 33 2 @ 0_0402_5% C639
R221 0_0603_5% 34 R555 1 2 @ 0_0603_5% +AVDD_AC97 0.1U_0402_16V4Z
VAUX R556 1 2 2
<32,35> EAPD 47 SPDIFI/EAPD DISABLE# 43 2 @ 0_0402_5% EC_IDERST <35>
2

44 SMB_CLK
R553 SCK
1 2 48 SPDIFO 1 2 +3VS
R309 0_0603_5% 0_0402_5% 40 R557 10K_0402_5%
NC
4 DVSS1 AVSS1 26
7 42
1

4 DVSS2 AVSS2 4
1 2
R286 0_0603_5% U46 ALC250-VD_LQFP48

DGND AGND
1 2
R601 @ 0_0603_5%
With 14.318Mhz : R553 POP Security Classification Compal Secret Data Compal Electronics, Inc.
With 24.576Mhz : R553 DEPOP Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title

DGND AGND
AC97 CODEC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:55 Sheet 30 of 53
A B C D E F G H
 5 4 3 2 1

1 2 R275 1 2 R269 1 2 W D@ 10K_0402_5% R262 1 2 W D@ 4.7K_0402_5%

<40> LINEIL#
C254 W D@ 1U_0402_6.3V4Z W D@ 1K_0402_5% 1

C249 W D@ 1000P_0402_50V7K +VDDA

W D@ 1U_0402_6.3V4Z
2 C223 1 2
1

4
C256 W D@ 1000P_0402_50V7K 2

V+
-
O 1 LINE_IN_L <30>
R276 1 2 R270 1
1 2 2 2 W D@ 10K_0402_5% 3 +VDDA

V-
<40> LINEIL +
C255 W D@ 1K_0402_5% U43A
D W D@ 1U_0402_6.3V4Z W D@ LMV824MTX_TSSOP14 D

11
+DOCK_AUD_VREF R263 1 W2D@ 4.7K_0402_5% +VDDA

4
+DOCK_AUD_VREF
9

V+
R552 - +DOCK_AUD_VREF
O 8
1 2 10

V-
R278 1 +
<40> LINEIR# 1 2 2 W D@ 1K_0402_5%R272 1 2 W D@ 10K_0402_5% R265 1 2 W D@ 4.7K_0402_5% W D@ 100K_0402_5% U43C

2
C259 1 1 C655 LMV824MTX_TSSOP14 1

11
W D@ 1U_0402_6.3V4Z W D@ C654
C250 W D@ 1000P_0402_50V7K +VDDA R551 W D@ 1U_0402_6.3V4Z
W D@ 100K_0402_5%
2 2 0.1U_0402_16V4Z 2

1
1 W D@

4
C257 W D@ 1000P_0402_50V7K 6

V+
W D@ 1K_0402_5% -
O 7 LINE_IN_R <30>
R277 1 2 R271
1 2 2 1 2 W D@ 10K_0402_5% 5

V-
<40> LINEIR +
C258 U43B
W D@ 1U_0402_6.3V4Z W D@ LMV824MTX_TSSOP14

11
+DOCK_AUD_VREF R264 1 2
W D@ 4.7K_0402_5%

R279 1 2 W D@ 22K_0402_5%

1 2
C245 W D@ 68P_0402_50V8K +VDDA
C C
+VDDA C220 1 2
R273

4
W D@ 1U_0402_6.3V4Z 4 1U_0402_6.3V4Z
W D@ 22K_0402_5% 2

V+
- W D@
1 2 1 2 9 1 1 2
V+

<30> HP_OUT_L - O LINEOL <40>

C238 8 3 C219 1U_0402_6.3V4Z

V-
O + U45A
+DOCK_AUD_VREF 10 W D@
V-

2
2 U45C W D@ LMV824MTX_TSSOP14

11
11

C252 W D@ LMV824MTX_TSSOP14 R258

0.1U_0402_16V4Z 4.7K_0402_5%
1 W D@ W D@

1
R259 2 1 4.7K_0402_5%

W D@
+VDDA

4
6

V+
-
O 7 1 2 LINEOL# <40>
+DOCK_AUD_VREF 5 C239 1U_0402_6.3V4Z

V-
+ U45B W D@
2
W D@ LMV824MTX_TSSOP14

11
C226
0.1U_0402_16V4Z
W D@ 1

B B
W D@
22K_0402_5%

R280 1 2
W D@ 68P_0402_50V8K
1 2
C246 +VDDA

+VDDA 1 2
C222 1U_0402_6.3V4Z
4

R274 W D@
4

W D@ 1U_0402_6.3V4Z W D@ 22K_0402_5% 2
V+

-
1 2 1 2 9 1 1 2
V+

<30> HP_OUT_R - O LINEOR <40>

C240 8 3 C221 1U_0402_6.3V4Z
V-

O + U44A W D@
+DOCK_AUD_VREF 10
V-

+
2

2 U44C W D@ LMV824MTX_TSSOP14
11
11

C253 W D@ LMV824MTX_TSSOP14 R260

0.1U_0402_16V4Z W D@ 4.7K_0402_5%
1 W D@ W D@ 4.7K_0402_5%
1

R261 2 1

+VDDA
4

6
V+

-
A O 7 1 2 LINEOR# <40> A
+DOCK_AUD_VREF 5 C241 1U_0402_6.3V4Z
V-

+ U44B W D@
2
11

C227 W D@ LMV824MTX_TSSOP14
0.1U_0402_16V4Z
W D@ 1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
Docking Audio
PROPRIETARY NOTE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:57 Sheet 31 of 53
5 4 3 2 1
 A B C D E

+5VAMP

Reserve for debug

Speaker Conn.

1
R540
+5VAMP +5VS 100K_0402_5%
JP6
J4 +5VAMP SPKL+ R350 1 2 0_0603_5%

2
SHUTDOWN# SPKL- R353 0_0603_5% 4
2 2 1 1 W=40mil Q27 SPKR+ R356
1 2
0_0603_5% 3
1 2 2

1
@ JUMP_43X118 D 2N7002_SOT23 SPKR- R363 0_0603_5%
2 1 1 2 1
1 1 1 2 EC_MUTE <35> 1
C626 C627 G ACES_85204-0400
10U_1206_16V4Z 0.1U_0402_16V4Z C644 C643 S

3
1 2 0.1U_0402_16V4Z 4.7U_0805_10V4Z
2 2

1
D Q30
2 EAPD
EAPD <30,35>
G
S @ 2N7002_SOT23

3
U42
7 22 R546 1 2 100K_0402_5% +5VAMP
PVDD SHUTDOWN# NBA_PLUG
18 PVDD SE/BTL# 15
19 VDD PC-BEEP 14 1 2
11 BYPASS C650 0.1U_0402_16V4Z
R253 1 BYPASS
2 100K_0402_5% PATH_SEL_1 2 HP/LINE# LOUT- 9 SPKL-
VOL_AMP 3 16 SPKR- +AUD_VREF
SPKL+ VOLUME ROUT-
4 LOUT+ LIN 10
SPKR+ 21 8
<30> AMP_LEFT
C636
1 2
1U_0402_6.3V4Z
LEFT_2
RIGHT_2
5
23
ROUT+
LLINEIN
RIN
1
MIC JACK
RLINEIN GND

1
1 2 6 12 JP16
<30> AMP_RIGHT LHPIN GND
C635 1U_0402_6.3V4Z 20 13 2 2 2 5
RHPIN GND R570 R571
GND 24
17 C647 4.7K_0402_5% 4.7K_0402_5% 4
CLK C251 C244 1U_0402_6.3V4Z

2
TPA0232PWP_TSSOP24 1U_0402_6.3V4Z1 1 1 MIC1 3
1 1U_0402_6.3V4Z 1 6
2 2 1 2 MIC 1 2 2
<30> MIC
2 C648 1 L17 FBM-11-160808-700T_0603 1 2
C228 0.047U_0402_16V7K WM-64PCY_2P 1
C640 2 45MIC@ C660 FOX_JA6033L-5S3-TR
0.1U_0402_16V4Z 1 1 C638 2 0.1U_0402_16V4Z C663
0.1U_0402_16V4Z 2 220P_0402_50V7K 220P_0402_50V7K
+5VAMP MIC@ 2
2

R535
@ 100K_0402_5%
HeadPhone JACK
JP15
1

PATH_SEL_1 5
1

D NBA_PLUG
<30,35> NBA_PLUG 4
2 SUSP#
SUSP# <16,26,30,35,37,38,42,49>
Q28 SPKR+ C267 1 2 150U_4A_10VM L16 1

+
G 1 2 2 3
@ 2N7002_SOT23 S R573 0_0402_5% FBM-11-160808-700T_0603 6
3

SPKL+ C268 1 2 150U_4A_10VM L15 1

+
1 2 2 2
R572 0_0402_5% FBM-11-160808-700T_0603 1
FOX_JA6033L-5S3-TR
C661 C662
330P_0402_50V7K 330P_0402_50V7K

3 3
VR R569 3.9K

R568 3.3K
+5VAMP R569 1 2 3.9K_0402_5%
R567 6.19K
2
C664
3

VR1 SPK
0.01W_10KC_EVUTWRB49C14 @ 0.1U_0402_16V4Z Bias
1
(Gain) 0.67 V
5 2 VOL_AMP
10 dB

HP
4

1.54 V
+5VAMP -6 dB
1

R564 R568 R567

100K_0402_5% 3.3K_0603_1% 6.19K_0603_1%
2

4 4
1

D
2 Q58
G 2N7002_SOT23
S
Security Classification Compal Secret Data Compal Electronics, Inc.
3
1

D
NBA_PLUG 2 2005/05/06 2006/05/06 Title
G
Issued Date Deciphered Date
Q57 S AMP & Audio Jack
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2N7002_SOT23 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:54 Sheet 32 of 53
A B C D E
 A B C D E

SUPER I/O SMsC LPC47N207

+3VS +3V
1 LPC_AD[0..3] 1
<18,34,35> LPC_AD[0..3]

1
1 1
C594
C579 C565 SI207@ 0.1U_0402_16V4Z
SI207@ 0.1U_0402_16V4Z SI207@ 4.7U_0805_10V4Z 2
2 2

17
31
42
60

48
5
U40

3.3V
3.3V
3.3V
3.3V
3.3V

VTR
LPC_AD0 64
LPC_AD1 LAD0
2 LAD1 GPIO10 27
LPC_AD2 4 28
LPC_AD3 LAD2 GPIO11 SIO_SMI#
7 LAD3 GPIO12/IO_SMI# 30 SIO_SMI# <34>
32 SIO_IRQ
GPIO13/IRQIN1 SIO_IRQ <34>
GPIO14/IRQIN2 33
10 LPC_CLK_33 GPIO15 34
12 LDRQ1# GPIO16 35
LPC_DRQ#1 24 36
<18,34> LPC_DRQ#1 LDRQ0# GPIO17
LPC_FRAME#

GPIO
<18,34,35> LPC_FRAME# 14 LFRAME# GPIO30 38
PM_CLKRUN#

LPC I/F
<19,29,34> PM_CLKRUN# 16 CLKRUN# GPIO31 39
SERIRQ 19 40
<19,24,34,35> SERIRQ CLK_PCI_SIO SERIRQ GPIO32 BT_DET#
<14,34> CLK_PCI_SIO 21 PCI_CLK GPIO33 41 BT_DET# <17,34,36>
2 22 43 FIR_DET# 2
<34> SIO_RST# PCIRST# GPIO34 FIR_DET# <34,38>
CLK_14M_SIO 23 44
<14,34> CLK_14M_SIO SIO_14M GPIO35
SIO_PD# 25 46
<34> SIO_PD# LPCPD# GPIO36
PME# 47 61
<29,34,35> PME# IO_PME# GPIO37

RXD1 1 2
R516 SI207@ 1K_0402_5%
63 52 RXD1
DLAD0 RXD1 RXD1 <34,38>
TXD1 Base I/O Address

SERIAL I/F
1 DLAD1 TXD1 53 TXD1 <34,38>
3 54 DSR#1 * 0 = 02Eh
DLAD2 DRSR1# DSR#1 <34,38>
6 55 RTS#1 1 = 04Eh
DLAD3 RTS1#/SYSOPT0 RTS#1 <34,38>
CTS#1

DLPC I/F
CTS1# 56 CTS#1 <34,38>
57 DTR#1
DTR1#/SYSOPT1 DTR#1 <34,38>
9 58 RI#1
DLPC_CLK_33 RI1# RI#1 <34,38>
11 59 DCD#1
DLDRQ1# DCD1# DCD#1 <34,38>
13 DTR#1 1 2
DLFRAME# IRTXOUT R513 SI207@ 10K_0402_5%
15 DCLKRUN# IRTX2 49 IRTXOUT <34,38>
18 50 IRRX
DSER_IRQ IRRX2 IRRX <34,38>
IRMODE

IR
26 DSIO_14M IRMODE/IRRX3 51 IRMODE <34,38>

GND0
GND1
GND2
GND3
GND4
GND5
+3VS
SI207@ LPC47N207-JN_STQFP64

8
20
29
37
45
62

2
3 3
R521
@ 10K_0402_5%
+3VS
Base I/O Address

1
RP74
DCD#1 1 8 0 *= 02Eh
RI#1 2 7 RTS#1 1 = 04Eh
CTS#1 3 6

2
DSR#1 4 5
R520
4.7K_8P4R_1206_5% SI207@ 1K_0402_5%

1
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
LPC-Super I/O 207
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:57 Sheet 33 of 53
A B C D E
 A B C D E

SUPER I/O SMsC LPC47N217 LPC_AD[0..3]

+3VS

<18,33,35> LPC_AD[0..3]

1 1
+3VS
C567 C577
R496 1 2 10K_0402_5% SIO_PD# U39 4.7U_0805_10V4Z 0.1U_0402_16V4Z
LPC_AD0 RXD1 2 2
10 LAD0 RXD1 62 RXD1 <33,38>
R518 1 2 10K_0402_5% SIO_SMI# LPC_AD1 TXD1

SERIAL I/F
12 LAD1 TXD1 63 TXD1 <33,38>
LPC_AD2 13 64 DSR#1 217@ 217@
LAD2 DSR1# DSR#1 <33,38>
1 R509 2 1 100K_0402_5% FIR_DET# LPC_AD3 14 1 RTS#1 1
LAD3 RTS1# RTS#1 <33,38>
2 CTS#1
CTS1# CTS#1 <33,38>
R511 2 1 100K_0402_5% BT_DET# LPC_FRAME# 15 3 DTR#1
<18,33,35> LPC_FRAME# LFRAME# DTR1# DTR#1 <33,38>
LPC_DRQ#1 16 4 RI#1
<18,33> LPC_DRQ#1 LDRQ# RI1# RI#1 <33,38>

LPC I/F
5 DCD#1
DCD1# DCD#1 <33,38>
R498 1 2 0_0402_5% SIO_RST# 17
<17,24,29,35> PCI_RST# PCI_RESET#
R497 1 2 @ 0_0402_5% <33> SIO_PD# SIO_PD# 18 37 IRRX
<6,16,17,19,21,22,24,27,35> PLT_RST# LPCPD# IRRX <33,38>
<33> SIO_RST# FIR IRRX2
IRTX2 38 IRTXOUT
IRTXOUT <33,38>
PM_CLKRUN# 19 39 IRMODE
<19,29,33> PM_CLKRUN# CLKRUN# IRMODE/IRRX3 IRMODE <33,38>
CLK_PCI_SIO 20 +3VS
<14,33> CLK_PCI_SIO PCI_CLK
SERIRQ 21 41 INIT#
<19,24,33,35> SERIRQ PME# SER_IRQ INIT# SLCTIN#
<29,33,35> PME# 6 IO_PME# SLCTIN# 42
44 LPD0
PD0

2
CLK_14M_SIO 9 46 LPD1
<14,33> CLK_14M_SIO CLK14 PD1
CLOCK 47 LPD2 R514
PD2 LPD3 @ 10K_0402_5%
23 GPIO40 PD3 48

PARALLEL I/F
24 49 LPD4
SIO_IRQ R519 2 GPIO41 PD4
1@ 10K_0402_5% 25 50 LPD5 Base I/O Address

1
GPIO42 PD5 LPD6
27 GPIO43 PD6 51
IRRX R515 1 2 10K_0402_5% FIR_DET# LPD7 0 *= 02Eh

GPIO
<33,38> FIR_DET# 28 GPIO44 PD7 53
BT_DET# 29 55 LPTSLCT SIO_GPIO11 1 = 04Eh
<17,33,36> BT_DET# GPIO45 SLCT LPTSLCT <40>
30 56 LPTPE
GPIO46 PE LPTPE <40>

2
LPTBUSY
Agilent IRRX unpop 10K 31
32
GPIO47 BUSY 57
58 LPTACK#
LPTBUSY <40>
R517
GPIO10 ACK# LPTACK# <40>
Vishay IRRX pop 10K SIO_GPIO11
SIO_SMI#
33
34
GPIO11/SYSOPT ERROR# 59
60
LPTERR#
LPTAFD#
LPTERR# <40>
1K_0402_5%
217@
<33> SIO_SMI# GPIO12/IO_SMI# ALF#
SIO_IRQ 35 61 LPTSTB#
<33> SIO_IRQ

1
GPIO13/IRQIN1 STROBE#
36 GPIO14/IRQIN2
40 GPIO23
2 2
8 VSS VTR 7 +3V
CLK_14M_SIO CLK_PCI_SIO 22 11 1
VSS VCC
43 VSS POWER VCC 26
2

52 45 C568
R499 VSS VCC 217@ 0.1U_0402_16V4Z
VCC 54 +3VS
NOSIO@ 10K_0402_5% R504 2
@ 10_0402_5% 217@ LPC47N217_STQFP64
1

1 1
C562
NOSIO@ 15P_0402_50V8J C574
@ 15P_0402_50V8J
2 2

Docking Parallel Port Close to Docking Serial Port

+5V_PRN
C404 1
for Debug
2 @ 220P_0402_50V7K LPTSLCTIN#

D23 C399 1 2 @ 220P_0402_50V7K LPTINIT# RP48

3 LPTSLCT 3
+5VS 2 1 +5V_PRN 1 8
C393 1 2 @ 220P_0402_50V7K LPTERR# 2 7 LPTPE
217@ RB420D_SOT23 3 6 LPTBUSY
1

C385 1 2 @ 220P_0402_50V7K AFD#/3M# 4 5 LPTACK# +5VS

R315217@
2.2K_0402_5% C346 1 2 @ 220P_0402_50V7K LPTACK# 217@ 2.7K_1206_8P4R_5%
RP55 JP13
C342 1 2 @ 220P_0402_50V7K LPTBUSY 1 8 AFD#/3M# 1
2

C295 1
2 7 LPTERR# 2 2
1 2 C336 1 2 @ 220P_0402_50V7K LPTPE 3 6 LPTINIT# RXD1 3 3
4 5 LPTSLCTIN# TXD1 4 4
217@ 220P_0402_50V7K C332 1 2 @ 220P_0402_50V7K LPTSLCT DSR#1 5
217@ 2.7K_1206_8P4R_5% RTS#1 5
6 6
217@ C352 1 2 @ 220P_0402_50V7K F D0 RP54 CTS#1 7
LPTSTB# R316 1 33_0402_5% R_LPTSTB# F D0 DTR#1 7
2 R_LPTSTB# <40> 1 8 8 8
217@ C360 1 2 @ 220P_0402_50V7K F D1 2 7 F D1 RI#1 9
LPTAFD# R358 1 33_0402_5% AFD#/3M# F D2 DCD#1 9
2 AFD#/3M# <40> 3 6 10 10
217@ C363 1 2 @ 220P_0402_50V7K F D2 4 5 F D3
INIT# R374 1 2 33_0402_5% LPTINIT# @ E&T_96212-1011S
LPTINIT# <40>
217@ C367 1 2 @ 220P_0402_50V7K F D3 217@ 2.7K_1206_8P4R_5%
SLCTIN# R380 1 2 33_0402_5% LPTSLCTIN# RP46
LPTSLCTIN# <40>
C318 1 2 @ 220P_0402_50V7K F D4 1 8 F D7
C330 2 7 F D6
C312 1 2 @ 220P_0402_50V7K F D5 3 6 F D5
RP51 4 5 F D4
LPD0 1 8 F D0 C328 1 2 @ 220P_0402_50V7K F D6
FD0 <40>
LPD1 2 7 F D1 217@ 2.7K_1206_8P4R_5%
FD1 <40>
LPD2 3 6 F D2 1 2 @ 220P_0402_50V7K F D7
FD2 <40>
LPD3 4 5 F D3
4 FD3 <40> 4

217@ 68_1206_8P4R_5%

RP43
LPD7 4 5 F D7
LPD6 3 6 F D6
FD7
FD6
<40>
<40>
Security Classification Compal Secret Data Compal Electronics, Inc.
LPD5 2 7 F D5 2005/05/06 2006/05/06 Title
LPD4 F D4
FD5 <40> Issued Date Deciphered Date
1 8 FD4 <40> LPC-Super I/O 217
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
217@ 68_1206_8P4R_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:57 Sheet 34 of 53
A B C D E
 5 4 3 2 1

+3VALW For EC Tools

+3VALW
JP14

2
1 1 +5VALW
KBA[0..19] R216 2 E51_RXD
KBA[0..19] <37> L7 0_0402_5% 2 E51_TXD
Change to 0 ohm 3 3
ADB[0..7] 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2 4
ADB[0..7] <37> 4
1 1 C184 1 1 2 2 0_0603_5%

1
C147 1 @ ACES_85205-0400
C182 C164 C122 C191
1000P_0402_50V7K 1000P_0402_50V7K C144 1 1
L4 2 2 2 2 1 1 C183 C189

ECAGND
ECAGND 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z
1 2
FBM-L11-160808-800LMT_0603 0.1U_0402_16V4Z 1U_0603_10V4Z
2 2
D D
KSI[0..7]
KSI[0..7] <36,39>

123
136
157
166

161

159
KSO[0..15]

16
34
45

95

96
KSO[0..15] <36>
U14
LPC_AD0 15

VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCCA

AGND

VCCBAT

BATGND
C154 <18,33,34> LPC_AD0 LPC_AD1 LAD0 KSO0
<18,33,34> LPC_AD1 14 LAD1 GPOK0/KSO0 49
@ 22P_0402_50V8J LPC_AD2 13 50 KSO1
R181 2 <18,33,34> LPC_AD2 LPC_AD3 LAD2 GPOK1/KSO1 KSO2
2 1 1 @ 33_0402_5% <18,33,34> LPC_AD3 10 LAD3 GPOK2/KSO2 51 Analog Board ID definition,
KSO3
<18,33,34> LPC_FRAME#
LRST#
9 LFRAME# LPC Interface GPOK3/KSO3 52
KSO4 Please see page 3.
165 LRST#/GPIO2C GPOK4/KSO4 53

ENE-KB910-B4
18 56 KSO5
<14> CLK_PCI_LPC LCLK GPOK5/KSO5
7 57 KSO6 +3VALW
+3VALW <19,24,33,34> SERIRQ DOCKIN# SERIRQ GPOK6/KSO6 KSO7
<15,40> DOCKIN# 25 CLKRUN#/GPIO0C * GPOK7/KSO7 58
24 59 KSO8
LPCPD#/GPIO0B * GPOK8/KSO8
2

60 KSO9
GPOK9/KSO9

2
R208 FR D# 150 61 KSO10
10K_0402_5% <37> FRD# RD# GPOK10/KSO10
FW R# KSO11 R119

Internal Keyboard
<37> FW R# 151 WR# GPOK11/KSO11 64
FSEL# 173 65 KSO12 Ra 100K_0402_5%
<37> FSEL# MEMCS# GPOK12/KSO12
SELIO# 152 66 KSO13
1

ADB0 IOCS# GPOK13/KSO13 KSO14

138 67

1
ADB1 D0 GPOK14/KSO14 KSO15 AD_BID0
139 D1 GPOK15/KSO15 68
PME# ADB2 140 153
<29,33,34> PME# D2 GPOK16/KSO16

2
ADB3 141 154 KSO17 1
D3 GPOK17/KSO17 KSO17 <39>
ADB4 144 R122 C138
ADB5 D4 KSI0 33K_0402_1%
145 D5 GPIK0/KSI0 71 EC_PLAYBTN# <36,39> Rb

X-BUS Interface
R166 1 2 0_0402_5% ENBKL ADB6 146 72 KSI1 0.1U_0402_16V4Z
<8,16> GMCH_ENBKL D6 GPIK1/KSI1 EC_STOPBTN# <36,39> 2
ADB7 147 73 KSI2
EC_REVBTN# <36,39>

1
KBA0 D7 GPIK2/KSI2 KSI3
124 A0 GPIK3/KSI3 74 EC_FRDBTN# <36,39>
R213 1 2 0_0402_5% LRST# KBA1 125 77 KSI4
<17,24,29,34> PCI_RST# A1/XIOP_TP GPIK4/KSI4
KBA2 126 78 KSI5
R217 1 KBA3 A2 GPIK5/KSI5 KSI6
2 @ 0_0402_5% 127 79
C <6,16,17,19,21,22,24,27,34> PLT_RST#
KBA4 A3 GPIK6/KSI6 KSI7 C
128 A4/DMRP_TP GPIK7/KSI7 80
KBA5 131
KBA6 A5/EMWB_TP INVT_PWM +3VALW
132 A6 GPOW0/PWM0 32 INVT_PWM <16>
KBA7 133 33 BEEP#
A7 GPOW1/PWM1 BEEP# <30>
KBA8 143 36 PWR_SUSP_LED
A8 FAN2PWM/GPOW2/PWM2 PWR_SUSP_LED <39>

2
+3VALW +3VALW KBA9 142 37 ACOFF
A9 GPOW3/PWM3 ACOFF <46>
SKU ID definition, SKU ID1 definition KBA10 135 Pulse Width GPOW4/PWM4 38 R170
KBA11 A10 EC_ON 10K_0402_5%
134 39 EC_ON <41>
Please see page 3. KBA12 130
A11 GPOW5/PWM5
40 EC_LID_OUT#
A12 GPOW6/PWM6 EC_LID_OUT# <19>
2

KBA13 129 43 EC_MUTE

EC_MUTE <32>

1
R99 R113 KBA14 A13 FAN1PWM/GPOW7/PWM7 D10
121 A14
Rc 100K_0402_1% Re 100K_0402_1% KBA15 120 2 ON /OFF
A15 GPWU0 ON/OFF <41>
KBA16 113 26 2 1
A16 GPWU1 ACIN <19,39,44>
KBA17 112 29 KILL_SW#
KILL_SW# <29,36,38>
1

SKU_ID SKU_ID1 KBA18 A17 GPWU2 PM_SLP_S3#

104 A18 GPWU3 30 PM_SLP_S3# <19> RB751V_SOD323
KBA19 103 Wake Up Pin 44 PM_SLP_S5#
A19 GPWU4 PM_SLP_S5# <19>
2

C123 1 2 0.1U_0402_16V4Z IE_BTN# 108 76 IDE_MRESET#

<39> IE_BTN# A20/GPIO23 GPWU5 IDE_MRESET# <19>
R106 +3VALW 2 1 105 172 PME#
R108 2 E51CS#/GPIO20/ISPEN TIN1/GPWU6 PM_SLP_S4#
Rd 1 0_0402_5% Rf @ 0_0402_5% R160 100K_0402_5%
TIN2/FANFB2/GPWU7 176 PM_SLP_S4# <19>
10@ KB_CLK 110 2 1 ECAGND
<40> KB_CLK PSCLK1
R605 2 1 8.2K_0402_1% KB_DATA 111 81 BATT_TEMP C121 0.01U_0402_16V7K
BATT_TEMP <45>
1

10C@ <40> KB_DATA PS_CLK PSDAT1 GPIAD0/AD0 SKU_ID

<40> PS_CLK 114 PSCLK2 GPIAD1/AD1 82
R606 2 18K_0402_1% PS_DATA BATT_AOVP
1
10G@ <40> PS_DATA TP_CLK
115 PSDAT2PS2 Interface GPIAD2/AD2 83
DPCONF_S5P_R
BATT_AOVP <46>
R604 1 5.6K_0402_5%
<36> TP_CLK 116 PSCLK3 GPIAD3/AD3 84 2 DPCONF_S5P <40>
R607 2 1 33K_0402_1% TP_DATA 117 Analog To Digital 87 ALI/MH#
<36> TP_DATA PSDAT3 GPIAD4/AD4 ALI/MH# <45>
10GC@ 88 SKU_ID1
GPIAD5/AD5 SKU_ID1 <39>
R608 2 1 56K_0402_1% EC_SMB_CK1 163 89 AD_BID0
SID4@ <37,45> EC_SMB_CK1 EC_SMB_DA1 SCL1 GPIAD6/AD6
<37,45> EC_SMB_DA1 164 SDA1 GPIAD7/AD7 90 1 2 ADP_I <46>
R609 2 1 100K_0402_1% EC_SMB_CK2 169 SMBus R142 100K_0402_5%
SID5@ <4,30,40> EC_SMB_CK2 EC_SMB_DA2 SCL2 DAC_BRIG
<4,30,40> EC_SMB_DA2 170 SDA2 GPODA0/DA0 99 DAC_BRIG <16> 1 2
R610 2 1 200K_0402_1% 100 BT_PWR C140 0.22U_0402_10V4Z
GPODA1/DA1 BT_PWR <36>
B SID6@ DKN_B+_ON 8 101 IREF B
<46> DKN_B+_ON GPIO04 GPODA2/DA2 IREF <46>
EC_SCI# 20 102 EN_DFAN1#
<19> EC_SCI# GPIO07 GPODA3/DA3 EN_DFAN1 <38>
BT_RST# 21 Digital To Analog 1
<36> BT_RST# GPIO08 GPODA4/DA4
BT_WAKE_UP 22 42 R141 1 2 @ 0_0402_5% PM_BATLOW#
<36> BT_WAKE_UP GPIO09 GPODA5/DA5 PM_BATLOW# <19>
ENBKL 27 47 EC_IDERST
GPIO0D GPODA6/DA6 EC_IDERST <30>
+3VALW BKOFF# 28 174 AUD_SUDMUT_P3# CRY1 1 R211 2 CRY2
<16> BKOFF# GPIO0E GPODA7/DA7 AUD_SUDMUT_P3# <40>
RP32 FSTCHG 48 @ 20M_0603_5%
<46> FSTCHG GPIO10

2
1 8 MODE# EC_SMI# 62 85 PWR_LED#
<19> EC_SMI# GPIO13 * GPIO18/XIO8CS# PWR_LED# <39>
2 7 FR D# ODD_RESET# 63 86 WL_BT_LED# R212
<22> ODD_RESET# GPIO14 * GPIO19/XIO9CS# WL_BT_LED# <39>
3 6 SELIO# 69 91 HDD_LED#
<29> WL_OFF# GPIO15 * GPIO1A/XIOACS# HDD_LED# <39>
4 5 FSEL# 70 GPIO 92 BATT_LOW_LED# 0_0402_5%
<19> EC_SWI# GPIO16 * GPIO1B/XIOBCS# BATT_LOW_LED# <39>
75 Expanded I/O * GPIO1C/XIOCCS# 93 BATT_CHGI_LED#
<41> S4_LATCH BATT_CHGI_LED# <39>

1
10K_0804_8P4R_5% GPIO17
<41> S4_SATA 109 GPIO24 94
+5VALW +5VS LID_SW# 118 * GPIO1D/XIODCS# 97 SPKSEL
<39> LID_SW# GPIO25 * GPIO1E/XIOECS# SPKSEL <30>
RP33 RP31 MODE# 119 98 NBA_PLUG 1 1
<39> MODE# GPIO26 * GPIO1F/XIOFCS# NBA_PLUG <30,32>
1 8 EC_SMB_CK1 1 8 KB_CLK SYSON 148 C199 C205
<30,39,41,42,48> SYSON GPIO27

4
2 7 EC_SMB_DA1 2 7 KB_DATA SUSP# 149 171 FAN_SPEED1
<16,26,30,32,37,38,42,49> SUSP# GPIO28 GPIO2E/TOUT1/FANFB1 FAN_SPEED1 <38>

10P_0402_50V8J

10P_0402_50V8J
3 6 EC_SMB_CK2 3 6 PS_CLK VR_ON 155 12 1394_PHYRST_S3P X2

OUT
IN
<50> VR_ON GPIO29 DPLL_TP/GPIO06/FANFB3 1394_PHYRST_S3P <40> 2 2
4 5 EC_SMB_DA2 4 5 PS_DATA EJCTSW# 156 FANTEST_TP/GPIO05/FAN3PWM 11 1394_DILSON_S3P
<40> EJCTSW# GPIO2A 1394_DILSON_S3P <40>
BT_DETACH 162
<36> BT_DETACH GPIO2B
4.7K_0804_8P4R_5% 4.7K_0804_8P4R_5% PBTN_OUT# 168 175 EC_THERM#
<19> PBTN_OUT# GPIO2D TOUT2/GPIO2F EC_THERM# <19>
Timer Pin

NC

NC
PADS_LED# 55 3
<36> PADS_LED# FnLock#/GPIO12 * E51IT0/GPIO00 EC_RSMRST# <19>
C150 0.1U_0402_16V4Z CAPS_LED# 54 4 SHDD_LED#
<36> CAPS_LED# SHDD_LED# <22>

3
+5VS NUM_LED# CapLock#/GPIO011 * E51IT1/GPIO01 E51_RXD
2 1 <36> NUM_LED# 23 NumLock#/GPIO0A * E51RXD/GPIO21/ISPCLK 106 1 2 EAPD <30,32>
41 107 E51_TXD R169 0_0402_5%
<18> PHDD_LED# ScrollLock#/GPIO0F * E51TXD/GPIO22/ISPDAT
2 1 TP_CLK +3VALW 2 1 19 ECRST# MISC
4.7K_0402_5% R180 R173 47K_0402_5% 5 158 CRY2
<18> EC_GA20 GA20/GPIO02 XCLKI
2 1 TP_DATA <18> EC_KBRST# 6 KBRST#/GPIO03 XCLKO 160 CRY1 32.768KHZ_12.5P_1TJS125BJ2A251
4.7K_0402_5% R183 31
GND
GND
GND
GND
GND
GND

ECSCI#
A A
KB910Q B4_LQFP176
17
35
46
122
137
167

1 2 ENBKL
+3VALW R158 @ 120K_0402_5%

2 1 KBA1 1 2 DPCONF_S5P_R
1K_0402_5% R186 R107 10K_0402_5%
2 1 KBA4
1K_0402_5% R188 1 2 1394_PHYRST_S3P Security Classification Compal Secret Data Compal Electronics, Inc.
2 1 KBA5 R184 1K_0402_5% 2005/05/06 2006/05/06 Title
1K_0402_5% R189
Issued Date Deciphered Date
2 1 EJCTSW# 1 2 1394_DILSON_S3P ENE-KB910
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
100K_0402_5% R206 R185 1K_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:54 Sheet 35 of 53
5 4 3 2 1
 +3V +3VS_MDC +5VS_MDC BlueTooth Interface
MDC CONN. 1 1 1
C141 C604 C145 +5VS +3VS
1U_0805_25V4Z 1U_0805_25V4Z 1U_0805_25V4Z
2 MDC@ 2 MDC@ 2 MDC@

2
JP26 R446 C480
100K_0402_5% 0.1U_0402_16V4Z
1 2 BT@ BT@
MONO_OUT/PC_BEEP AUDIO_PWRDN/DETECH

3
S
3 4

1
GND MONO_PHONE G
5 AUXA_RIGHT RESERVED/BT_ON# 6 2
7 8 Change to 0 ohm Q48
AUXA_LEFT GND +5VS_MDC 1 BT@AO3413_SOT23
9 10 2 +5VS
D

1
CD_GND +5Vmain

1
11 12 L6 0_0603_5% Q49 C481
R522 CD_RIGHT RESERVED/USB+ MDC@ BT@DTC124EK_SC59
13 CD_LEFT RESERVED/USB- 14
0_0402_5% 15 16 1 2 0.1U_0402_16V4Z
GND RESERVED/PRIMARY_DN +3VS +BT_VCC
+3V 1 MDC@ 2 17 +3.3Vaux/BT_VCC RESERVED/+5VD/WAKEUP 18 R156 10K_0402_5% BT@
Change to 0 ohm 19 20 MDC@ 2
GND RESERVED/GND <35> BT_PWR
+3VS 1 2 +3VS_MDC 21 +3.3Vmain AC97_SYNC 22 R603 1 2 ICH_AC_SYNC <18,30>
C469
L14 MDC@0_0603_5% 23 24 1 2 0_0402_5% MDC@0_0402_5%
AC97_SDATA_OUT AC97_SDATA_IN1 R159 MDC@1 10U_1206_16V4Z
25 AC97_RESET# AC97_SDATA_IN0 26 2 ICH_AC_SDIN1 <18>
R175 2 1MDC_AC_SDOUT 27 28 R167 MDC@22_0402_5%
<18,30> ICH_AC_SDOUT

3
MDC@22_0402_5% GND GND R172 1
29 AC97_MSTRCLK AC97_BITCLK 30 2 ICH_AC_BITCLK <18,30>
R177 2 1MDC_AC_RST# MDC@22_0402_5%
<18,30> ICH_AC_RST#
MDC@22_0402_5% R602 C674
ACES_88018-3010 1 2 2 1
MDC@ @ 10_0402_5%
@ 10P_0402_50V8J Module ID
Indication for polarity of reset
Reset input High Active --> Low ,
Reset input Low Active --> Open

TP CONN. +5VS

D24 @ DAN217_SC59
JP10 2
TP_CLK 1 +3VS
12 1
3 C69
TP_DATA 11 C90 C486 +5VS @ 0.1U_0402_16V4Z
<35> TP_DATA TP_CLK 10 @ 180P_0402_50V8J
<35> TP_CLK 9 0.1U_0402_16V4Z
2
8 2
1 TP_DATA 1
7

5
3 U6
6 C91 1

P
5 <29,35,38> KILL_SW# B
@ 180P_0402_50V8J D4 @ DAN217_SC59 4 BT_RESET#
SW_L 4 2 Y
3 <35> BT_RST# 2 A

G
SW_R
R79 2 2 @ TC7SH08FU_SSOP5
1

3
@ 0_0402_5% 1
ACES_87151-1207
TP Button Touchpad mount direction:
SW1 SW2 Standard: N/A, Reverse: Stuff 1 2
R64 0_0402_5%
SW_L 1 3 SW_R 1 3 BT@

2 4 2 4
SMT1-05_4P SMT1-05_4P INT_KBD CONN.
6
5

6
5

JP11 JP9
1 NUM_LED# <35> 1
2 PADS_LED# <35> 2
BT_DET#
KSI[0..7] 3 CAPS_LED# <35> <17,33,34> BT_DET# 3
KSI[0..7] <35,39> 4 1 2 +3VS 4
KSO15 300_0402_5% R489
KSO[0..15] 5 KSO14 5
KSO[0..15] <35> 6 6
KSO10
7 KSO11 BT_RESET# 7
8 KSO8 BT_WAKE_UP 8
9 <35> BT_WAKE_UP 9
KSO9
KSO7 C525 100P_0402_25V8K KSO15 C544 100P_0402_25V8K 10 KSO13 10
11 KSI7 11
KSO6 C537 100P_0402_25V8K KSO14 C529 100P_0402_25V8K 12 KSO3 12
13 <35> BT_DETACH 13
KSO7
14 <29> CH_CLK 14
KSO5 C522 100P_0402_25V8K KSO13 C541 100P_0402_25V8K KSO12 R590 2 1
15 KSI4 USB20_P5 @ 100K_0402_5% 15
KSO4 C518 100P_0402_25V8K KSO12 C539 100P_0402_25V8K 16 KSI6 <19> USB20_P5 USB20_N5 16
17 KSI5 <19> USB20_N5 17
18 <29> CH_DATA 18
KSO3 C540 100P_0402_25V8K KSI0 C521 100P_0402_25V8K KSO6 R591 2 1
19 KSO5 @ 100K_0402_5% 19
20 +BT_VCC 20
KSI4 C524 100P_0402_25V8K KSO11 C528 100P_0402_25V8K KSI3
21 KSI0 (MAX=200mA) ACES_87151-2005
KSO2 C533 100P_0402_25V8K KSO10 C543 100P_0402_25V8K 22 KSO0 C467 BT@
23 KSO1 (Top Contact)
KSO1 C520 100P_0402_25V8K KSI1 C534 100P_0402_25V8K 24 KSI1 0.1U_0402_16V4Z
25 KSI2 BT@
26 Bluetooth Connector
KSO0 C535 100P_0402_25V8K KSI2 C519 100P_0402_25V8K KSO2
27 KSO4
KSI5 C523 100P_0402_25V8K KSO9 C527 100P_0402_25V8K 28
29 1 2 +3VS
300_0402_5% R491
KSI6 C538 100P_0402_25V8K KSI3 C536 100P_0402_25V8K 30
31
KSI7 C526 100P_0402_25V8K PADS_LED# C530 100P_0402_25V8K 32
33
34 1 2 +3VS
KSO8 C542 100P_0402_25V8K NUM_LED# C546 100P_0402_25V8K 300_0402_5% R488
ACES_88170-3400
CAPS_LED# C545 100P_0402_25V8K
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
MDC / BT / KBD / TP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:58 Sheet 36 of 53
 +3VALW +3VALW
C203
SB_INT_FLASH_SEL# <19>

1
1 2 R241
100K_0402_5%

13
SUSP# <16,26,30,32,35,38,42,49>
0.1U_0402_16V4Z U26D

2
G

OE#
5
U22 INT_FLASH_SEL 11 12 SUS_STAT# <19>

2
O I
2 1 3

P
I0 EC_FLASH# <19>
FWE# 4

S
O SN74LVC125APWLE_TSSOP14
I1 1

G
Q24
TC7SH32FU_SSOP5 2N7002_SOT23

3
FWR# <35>

+3VALW

C211 1 2 0.1U_0402_16V4Z

2
R229
10K_0402_5% INT_FLASH_EN# R239 1 2

100K_0402_5%

10
+5VALW +5VALW U26C

OE#
INT_FSEL# R2321 2 22_0402_5% 8 9
O I FSEL# <35>

1
R235
C214 1 2 0.1U_0402_16V4Z
100K_0402_5% SN74LVC125APWLE_TSSOP14
2

1 2
U25
8 1 R233 @ 0_0402_5%
VCC A0
7 WP A1 2
<35,45> EC_SMB_CK1 6 SCL A2 3
<35,45> EC_SMB_DA1 5 SDA GND 4
AT24C16AN-10SI-2.7_SO8
1

R231

100K_0402_5%
2

KBA[0..19]
<35> KBA[0..19]
ADB[0..7]
<35> ADB[0..7]

1MB ROM Socket

1MB Flash ROM JP28
+3VALW KBA16 KBA17
KBA15 1 2
U24
KBA14 3 4
KBA0 KBA13 5 6 KBA19
21 A0 VCC0 31 7 8
KBA1 20 30 1 KBA12 KBA10
KBA2 A1 VCC1 C229 KBA11 9 10 ADB7
19 A2 11 12
KBA3 18 KBA9 ADB6
KBA4 A3 ADB0 0.1U_0402_16V4Z KBA8 13 14 ADB5
17 A4 D0 25 15 16
KBA5 ADB1 2 FWE# ADB4
16 A5 D1 26 17 18
KBA6 15 27 ADB2 RESET# +3VALW
KBA7 A6 D2 ADB3 INT_FLASH_EN# 19 20
14 A7 D3 28 21 22
KBA8 8 32 ADB4 INT_FLASH_SEL
KBA9 A8 D4 ADB5 KBA18 23 24 ADB3
7 A9 D5 33 25 26
KBA10 36 34 ADB6 KBA7 ADB2
KBA11 A10 D6 ADB7 KBA6 27 28 ADB1
6 A11 D7 35 29 30
KBA12 5 KBA5 ADB0
KBA13 A12 KBA4 31 32 FR D#
4 A13 33 34
KBA14 3 10 RESET# 1 2 +3VALW KBA3
KBA15 A14 RP# R256 100K_0402_5% KBA2 35 36 FSEL#
2 A15 NC 11 37 38
KBA16 1 12 KBA1 KBA0
KBA17 A16 READY/BUSY# 39 40
40 A17 NC0 29
KBA18 13 38 @ SUYIN_80065AR-040G2T
KBA19 A18 NC1
37 A19
INT_FSEL# 22
FR D# CE#
<35> FRD# 24 OE# GND0 23
FWE# 9 39
WE# GND1

SST39VF080-70_TSOP40 Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
BIOS & EXT. I/O PORT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:56 Sheet 37 of 53
 Close to Docking +3V
Kill SWITCH
2
+3V
C119
W D@ 0.1U_0402_16V4Z
1

26
3

2
D26 U7
KILL@ DAN217_SC59 +3V 2 28

VCC
C1+
V+ 27 2 1
C115 C120 W D@ 0.1U_0402_16V4Z

2
W D@ 0.1U_0402_16V4Z 24
1 C1-
2 1 3 2 1

1
R550 C2+ V- C92 W D@ 0.1U_0402_16V4Z
100K_0402_5% C93
W D@ 0.1U_0402_16V4Z 2

1
1 C2- DTR#
<33,34> DTR#1 14 TIN1 TOUT1 9 DTR# <40>
KILL_SW# 13 10 RTS#
KILL_SW# <29,35,36> <33,34> RTS#1 TIN2 TOUT2 RTS# <40>
12 11 TXD
<33,34> TXD1 TIN3 TOUT3 TXD <40>
3

19 4 CTS#
<33,34> CTS#1 ROUT1 RIN1 CTS# <40>
18 5 R I#
3

<33,34> RI#1 ROUT2 RIN2 RI# <40>

17 6 RXD
<33,34> RXD1 ROUT3 RIN3 RXD <40>
16 7 DC D#
<33,34> DCD#1 ROUT4 RIN4 DCD# <40>
1BS003-1211L_3P KILL@ SW3 15 8 DSR#
<33,34> DSR#1 ROUT5 RIN5 DSR# <40>
20 ROUTB2
INVLD# 21
<16,26,30,32,35,37,42,49> SUSP# 23 FORCEON
GND 25
22 FORCEOFF#
W D@ MAX3243CAI_SSOP28

FAN Conn
+12VALW +5VS

1 2
C41
0.1U_0402_16V4Z
8

1
P

1
EN_DFAN1 3 C Q10 D2 C47
<35> EN_DFAN1 +IN
1 EN_FAN1 1 2 2 FMMT619_SOT23 1SS355_SOD323 10U_1206_16V4Z

2
OUT B
2 1 2 -IN R51 2 E
3

2
G

R49 U5A 100_0402_5%

10K_0402_5% LM358A_SO8 C48 FAN1 L: R POP; FIR Enable
FIR Module
4

@ 0.1U_0402_16V4Z JP21 H: R De-POPFIR Disable

1

1
D3 3
1N4148_SOT23 2
1 2 1
R50 8.2K_0402_5%
ACES_85205-0300
2

FIR_DET# R508 1 2 1K_0402_5%

<33,34> FIR_DET#
FIR@

+3VS R52 1 2 10K_0402_5%

<35> FAN_SPEED1 +IR_ANODE

2 2 +3VS

C45 C423 (60mil) R548 @ 4.7_1206_5%

@ 1000P_0402_50V7K @ 1000P_0402_50V7K +3VS 1 2
1 1
1
1 2 (60mil)
C652 R549 4.7_1206_5%

2
1 22U_1206_16V4Z_V1 FIR@
2
C653 R559 IR1
@ 10U_0805_10V4Z 0_1206_5% 1
2 FIR@ IRED_A IRTXOUT
2 3 IRTXOUT <33,34>

1
IRRX IRED_C TXD IRMODE
<33,34> IRRX 4 RXD SD/MODE 5 IRMODE <33,34>
+IR_3VS 6 7
(30mil) VCC MODE
8 GND
1 1 (30mil, 3via)
FIR@ TFDU6102-TR3_8P
C658 C659
FIR@ 10U_1206_16V4Z FIR@ 0.1U_0402_16V4Z
2 2
SD/MODE: SHUTDOWN MODE, HIGH ACTIVE
MODE: HIGH/LOW SPEED SELECT

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
FAN1 / FIR / Kill
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:56 Sheet 38 of 53
 5 4 3 2 1

Switch Board Conn.

JP8
USB Board Conn. PWR_LED_1#
PWR_SUSPLED# 1
2 KSO17 C441 1
<35> SKU_ID1 3 2 220P_0402_50V7K
ON/OFFBTN# C432 1 2 220P_0402_50V7K
<35> KSO17 4
ON/OFFBTN# PWR_LED_1# C447 1 2 220P_0402_50V7K
<41> ON/OFFBTN# 5
+5VALW +5VALW IEBTN# PWR_SUSPLED# C444 1 2 220P_0402_50V7K
ACES_87213-1000 ACES_87213-1000 MODEBTN# 6 IEBTN# C429 1
7 2 220P_0402_50V7K
1 1 EC_PLAYBTN# MODEBTN# C427 1 2 220P_0402_50V7K
1 1 <35,36> EC_PLAYBTN# 8
2 2 EC_STOPBTN# EC_REVBTN# C415 1 2 220P_0402_50V7K
2 2 <35,36> EC_STOPBTN# 9
D 3 3 SYSON# EC_FRDBTN# EC_FRDBTN# C417 1 2 220P_0402_50V7K D
3 SYSON# <42> 3 <35,36> EC_FRDBTN# 10
4 4 EC_REVBTN# EC_PLAYBTN# C424 1 2 220P_0402_50V7K
4 4 <35,36> EC_REVBTN# 11
5 5 EC_STOPBTN# C421 1 2 220P_0402_50V7K
5 USB20_N1 <19> 5 USB20_N2 <19> 12
6 6 USB20_P1 <19> 6 6 USB20_P2 <19>
7 7 ACES_85201-1205
7 7
8 8 USB20_N3 <19> 8 8 USB20_N4 <19>
9 9 USB20_P3 <19> 9 9 USB20_P4 <19>
10 10 10 10
JP3 JP17
D17
POWER/ON LED
PWR_SUSPLED1# 3 4
2 MODE# <35>
MODEBTN# 1
3 51ON# PWR_LED_0# 2 1
51ON# <41,44>
D8
DAN202U_SC70 HT-297UD/NB_BLUE/AMB_0603
B@
+3VALW

+5VALW

SYSON D18 AC IN LED

3

Q61 +3VALW 1 2 2 1
2

47K 2N7002_SOT23 R304 300_0402_5%

G

HT-191NB_BLUE_0603

1
PWR_SUSP_LED B@ D
2 1 3 PWR_SUSP_LED <35>
C 10K R100 Q40 C
2
D

<19,35,44> ACIN
100K_0402_5% G 2N7002_SOT23
R5861 2 S

3
Q16 @ 0_0402_5%
BATTERY CHG

1
DTA114YKA_SC59
1

2 B@
Change from 300 to 120 IE_BTN# <35>
IEBTN# 1 +5VALW HT-297UD/NB_BLUE/AMB_0603
R87 1 2 120_0402_5% PWR_SUSPLED# 3 51ON#

D7 1 2 3 4 BATT_LOW_LED#
BATT_LOW_LED# <35>
R576 1 2 120_0402_5% PWR_SUSPLED1# DAN202U_SC70 R293 300_0402_5%

1 2 2 1 BATT_CHGI_LED#
BATT_CHGI_LED# <35>
R292 300_0402_5%

D19
RTCVREF

R598 1
0_0402_5%
2 1 2
R298 47K_0402_5% 100K_0402_5% 1
+5VS HDDD20 LED
2 R205 +3VALW
1 2 2 1 HDD_LED# <35>
U30 R301 300_0402_5%
A3212EEH_MLP6 HT-191NB_BLUE_0603
2 LID_SW# B@
LID_SW# <35>
5 1 L ID 1
VDD OUTPUT
3 S4_LID_SW# <41>
1
1 4 2 C282 D12
B C292 NC NC DAN202U_SC70 B
GND

0.1U_0402_16V4Z 10P_0402_25V8K
2
2
3

Lid SW
+3VALW
WL&BT LED
D27
1 2 2 1 WL_BT_LED# <35>
R558 KILL@ 300_0402_5%
KILL@ HT-191UD_AMBER_0603

+5VALW

+5VS
5IN1 LED
SYSON <30,35,41,42,48>
3

Q39 D25
2

DTA114YKA_SC59 47K Q62

G

1 2 2 1
2N7002_SOT23 R554 300_0402_5%
2 1 3 PWR_LED# 5IN1@ HT-191NB_BLUE_0603
PWR_LED# <35>

1
10K B@ D
D

2 Q35
<24,25> 5IN1_LED
R5871 2 G 2N7002_SOT23
@ 0_0402_5% S 5IN1@

3
A A
1

Change from 120 to 300

R297 1 2 300_0402_5% PWR_LED_0#
Security Classification Compal Secret Data Compal Electronics, Inc.
R303 1 2 300_0402_5% PWR_LED_1# 2005/05/06 2006/05/06 Title
Issued Date Deciphered Date
Switchs & LED
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:56 Sheet 39 of 53
5 4 3 2 1
 A B C D E

+3VALW +3VALW +3VALW

W D@ 0.1U_0402_16V4Z

1
C302 2 1 R335
W D@ 10K_0402_5% 100K_0402_5%

5
U34
R334 2 1 DCOCT1# 2

2
I0 DOCKIN#
4
Docking Conn. R333 1 2 DCOCT2# 1 I1
O DOCKIN# <15,35>

G
JP18A W D@ 10K_0402_5% W D@ TC7SH32FU_SSOP5 JP18B

3
1 245 GND GND 247 249 GND GND 251 1
246 GND GND 248 250 GND GND 252

+DC_IN_S1 241 VCC VCC 242 +DC_IN_S1 243 VCC VCC 244

DKN_B+ 1 S1 S61 61 DKN_B+ DKN_B+ 121 S121 S181 181 DKN_B+

2 S2 S62 62 122 S122 S182 182
DCOCT1# 3 63 EJCTSW# D_EC_SMB_CK2 123 183 D_EC_SMB_DA2
S3 S63 EJCTSW# <35> S123 S183
+5VS 4 S4 S64 64 +5VS +5VS 124 S124 S184 184 +5VS
PS_CLK 5 65 PS_DATA +5VALW 125 185
<35> PS_CLK S5 S65 PS_DATA <35> S125 S185
KB_CLK 6 66 KB_DATA TPA1+ 126 186 TPA1-
<35> KB_CLK S6 S66 KB_DATA <35> <24> TPA1+ S126 S186 TPA1- <24>
7 S7 S67 67 127 S127 S187 187
1394_PHYRST_S3P 8 68 TPB1+ 128 188 TPB1-
<35> 1394_PHYRST_S3P S8 S68 <24> TPB1+ S128 S188 TPB1- <24>
DPCONF_S5P 9 69 1394_DILSON_S3P 129 189 USB20_P0
<35> DPCONF_S5P S9 S69 1394_DILSON_S3P <35> S129 S189 USB20_P0 <19>
10 70 130 190 USB20_N0
S10 S70 S130 S190 USB20_N0 <19>
11 S11 S71 71 131 S131 S191 191
D_DDC_CLK 12 72 D_DDC_DATA 132 192
<15> D_DDC_CLK S12 S72 D_DDC_DATA <15> S132 S192
D_CRT_R 13 73 133 193
<15> D_CRT_R S13 S73 S133 S193
D_CRT_G 14 74 Pin 73, 74 and 75 for VGA GND AUD_SUDMUT_P3# 134 194 LINEOR
<15> D_CRT_G S14 S74 <35> AUD_SUDMUT_P3# S134 S194 LINEOR <31>
D_CRT_B 15 75 135 195 LINEOR#
<15> D_CRT_B S15 S75 S135 S195 LINEOR# <31>
D_CRT_VSYNC 16 76 D_CRT_HSYNC LINEOL 136 196 LINEOL#
<15> D_CRT_VSYNC S16 S76 D_CRT_HSYNC <15> <31> LINEOL S136 S196 LINEOL# <31>
DVI_SCLK 17 77 DVI_SDATA LINEIL 137 197 LINEIL#
<16> DVI_SCLK S17 S77 DVI_SDATA <16> <31> LINEIL S137 S197 LINEIL# <31>
18 78 LINEIR# 138 198 LINEIR
S18 S78 <31> LINEIR# S138 S198 LINEIR <31>
19 S19 S79 79 139 S139 S199 199
20 80 DOCK_ON/OFFBTN# 140 200 RXD
S20 S80 <41> DOCK_ON/OFFBTN# S140 S200 RXD <38>
21 81 DC D# 141 201 RTS#
S21 S81 <38> DCD# S141 S201 RTS# <38>
DVI_TXD2+ 22 82 DSR# 142 202 CTS#
<16> DVI_TXD2+ S22 S82 <38> DSR# S142 S202 CTS# <38>
DVI_TXD2- 23 83 TXD 143 203 DTR#
<16> DVI_TXD2- S23 S83 <38> TXD S143 S203 DTR# <38>
2 DVI_TXD1+ 24 84 R I# 144 204 LPTSLCT 2
<16> DVI_TXD1+ S24 S84 <38> RI# S144 S204 LPTSLCT <34>
DVI_TXD1- 25 85 LPTPE 145 205 LPTBUSY
<16> DVI_TXD1- S25 S85 <34> LPTPE S145 S205 LPTBUSY <34>
DVI_TXD0+ 26 86 F D7 146 206 LPTACK#
<16> DVI_TXD0+ S26 S86 <34> FD7 S146 S206 LPTACK# <34>
DVI_TXD0- 27 87 F D6 147 207 F D5
<16> DVI_TXD0- S27 S87 <34> FD6 S147 S207 FD5 <34>
28 S28 S88 88 148 S148 S208 208
29 S29 S89 89 149 S149 S209 209
DVI_TXC+ 30 90 F D4 150 210 F D3
<16> DVI_TXC+ S30 S90 <34> FD4 S150 S210 FD3 <34>
DVI_TXC- 31 91 F D1 151 211 LPTSLCTIN#
<16> DVI_TXC- S31 S91 <34> FD1 S151 S211 LPTSLCTIN# <34>
DVI_DET 32 92 F D2 152 212 LPTINIT#
<16> DVI_DET S32 S92 <34> FD2 S152 S212 LPTINIT# <34>
33 93 F D0 153 213 LPTERR#
S33 S93 <34> FD0 S153 S213 LPTERR# <34>
34 94 R_LPTSTB# 154 214 AFD#/3M#
S34 S94 <34> R_LPTSTB# S154 S214 AFD#/3M# <34>
35 S35 S95 95 155 S155 S215 215
36 S36 S96 96 156 S156 S216 216
37 S37 S97 97 157 S157 S217 217
38 S38 S98 98 158 S158 S218 218
39 S39 S99 99 159 S159 S219 219
40 S40 S100 100 160 S160 S220 220
41 S41 S101 101 161 S161 S221 221
42 S42 S102 102 162 S162 S222 222
43 S43 S103 103 163 S163 S223 223
44 S44 S104 104 164 S164 S224 224
45 S45 S105 105 165 S165 S225 225
46 S46 S106 106 166 S166 S226 226
47 S47 S107 107 167 S167 S227 227
48 S48 S108 108 168 S168 S228 228
49 S49 S109 109 169 S169 S229 229
50 S50 S110 110 170 S170 S230 230
51 S51 S111 111 171 S171 S231 231
52 S52 S112 112 172 S172 S232 232
3 3
173 S173 S233 233
234 LAN_ACTIVITY#
S234 LAN_ACTIVITY# <27,28>
RJ45_MDI3+ 55 115 RJ45_MDI2- +3VALW 175 235 LAN_LINK#
<28> RJ45_MDI3+ S55 S115 RJ45_MDI2- <28> S175 S235 LAN_LINK# <27,28>
RJ45_MDI3- 56 236 DCOCT2#
<28> RJ45_MDI3- S56 RJ45_MDI2+ S236
S117 117 RJ45_MDI2+ <28> RJ45_GND 178 LAN
MDC1_RING <28> RJ45_GND RJ45_MDI0+ L178 RJ45_MDI1+
59 M59 <28> RJ45_MDI0+ 179 L179 L239 239 RJ45_MDI1+ <28>
MDC2_TIP 60 MODEM RJ45_MDI0- 180 240 RJ45_MDI1-
M60 +5VALW +3VALW <28> RJ45_MDI0- L180 L240 RJ45_MDI1- <28>
2

253 GND GND 254

R314
W D@ 100K_0402_5%
2

W D@ TYCO_1674036 W D@ TYCO_1674036
G
1

1 3 Q44 1394_DILSON_S3P
W D@ 2N7002_SOT23
D

W D@ 4.7K_0402_5%
1 2 +5VALW
2
G

R313

3 1 D_EC_SMB_CK2
<4,30,35> EC_SMB_CK2 4.7K_0402_5%
S

Q42
W D@ 2N7002_SOT23 1 2 +5VALW
2
G

R311 W D@
MDC to Docking Conn. 3 1 D_EC_SMB_DA2
4 <4,30,35> EC_SMB_DA2 4
S

JP1 Q43
W D@ 2N7002_SOT23
1
MDC1_RING 2
MDC2_TIP 3
4 Security Classification Compal Secret Data Compal Electronics, Inc.
W D@ ACES_87213-0410 2005/05/06 2006/05/06 Title
Issued Date Deciphered Date
Docking
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:55 Sheet 40 of 53
A B C D E
 A B C D E

Reserved power button

SW4
+3VALW
1 3

2 4
Power Button RTC Battery

2
@ SMT1-05_4P R81
- +

6
5
BATT1 +RTCBATT
100K_0402_5%
2 1 +RTCBATT

1
1 D5 1
2 ON/OFF <35>
ON/OFFBTN# 1
<39> ON/OFFBTN#
3 51ON# RTCBATT
51ON# <39,44>

1
45@
RTCVREF DAN202U_SC70 D15

BAS40-04_SOT23
+RTCVCC

2
2

2
R84 R83
+CHGRTC
100K_0402_5% 100K_0402_5% 1
W D@ W D@
1

2 1
C261
G
0.1U_0402_16V4Z
2
<40> DOCK_ON/OFFBTN# 3 1
Q11
S

2N7002_SOT23
W D@

1 2

R85 @ 0_0402_5%

2 +3VALW 2

1
2 D6
2

C99
1

R80 1000P_0402_50V7K
4.7K_0402_5% 1 RLZ20A_LL34 RTCVREF RTCVREF RTCVREF RTCVREF

2
1

EC_ON 1 2 2
<35> EC_ON

1
R82 D11 C193 0.1U_0402_16V4Z
33K_0402_5% R198 R190 R191 1 2 ON/OFFBTN#

Q13 100K_0402_5% 100K_0402_5% 680K_0402_5% 1N4148_SOT23 2

3

3
DTC124EK_SC59

2
1

5
D C665 D29

1
Q12 D
2

P
G Q26 1
1 2 2 A Y 4 1 2 2
2N7002_SOT23 S C178 1U_0805_16V7K R214 G 2N7002_SOT23
3

G
10K_0402_5% S 0.1U_0402_16V4Z

1
U17

3
1
D NC7SZ14M5X_SOT23-5
2 Q20
<39> S4_LID_SW#
G 2N7002_SOT23 PSOT24C_SOT23
S

1
D

<30,35,39,42,48> SYSON 2
G
Q23 S

3
2N7002_SOT23
3 3

RTCVREF 1 2 1 2
R202 C190 1U_0805_16V7K
10K_0402_5%
RTCVREF
U19 C197 0.1U_0402_16V4Z
1 CD1# VCC 14 1 2
Power ON Circuit 2 D1 CD2# 13
<35> S4_LATCH 3 CP1 D2 12
RTCVREF 1 2 4 SD1# CP2 11
2

+3VS R238 5 10
1 Q1 SD2#
R218 10K_0402_5% C207 6 09
+3V +3V Q1# Q2
10K_0402_5% 7 GND Q2# 08
@ 1U_0805_16V7K
1

2 74LCX74MTC_TSSOP14
1

R284 U31D U31E

14

14

+3VALW 1 2
180K_0402_5% SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 R252 D14

1
10K_0402_5% D
P

P
2

9 D_SET_S4 Q25
I O 8 11 I O 10 SYS_PWROK <19> <35> S4_SATA 2 1 2
G 2N7002_SOT23
G

2 +3V POWER +3V POWER S

3
RB751V_SOD323
7

C264 R285
1U_0805_25V4Z
1 100K_0402_5%

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
Power OK/Reset/RTC battery
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:53 Sheet 41 of 53
A B C D E
 A B C D E

+3V +2.5VS
+3VALW TO +3V +5VALW TO +5VS
+3V

2
+5VALW +5VS R281 R13
U15 @ 470_0402_5% @470_0402_5%
1 1 8 D S 1
C263 C262 7 2

1
D S
6 D S 3 1 1
10U_1206_16V4Z 1U_0805_25V4Z 5 4 C155 C151
D G

1
+3VALW 2 2 D D
1 U27 1 SI4800DY_SO8 4.7U_0805_10V4Z 1U_0805_25V4Z 2 SYSON# 2 SUSP 1
2 2 G G
8 D S 1
7 2 R283 C174 S Q31 S Q4

3
D S 100K_0402_5% 4.7U_0805_10V4Z @ 2N7002_SOT23 @ 2N7002_SOT23
6 D S 3
SYSON_ALW 2
5 D G 4 1 2 +12VALW

1
SI4800DY_SO8 2

1
C265 R282 D 5VS_GATE
1
C231 2 SYSON#
0.1U_0402_16V4Z @ 1M_0402_5% G
10U_1206_16V4Z 1 S Q29
2

3
2 2N7002_SOT23

+3VS +5VS
+1.5VALW TO +1.5VS

2
R307 R308
+1.5VALW +1.5VS @470_0402_5% @ 470_0402_5%
U20
8 D 1

1
S
7 D S 2
6 D S 3 1 1

1
C187 C188 D D
5 D 4
+3VALW TO +3VS G
2 SUSP 2 SUSP
1 SI4800DY_SO8 4.7U_0805_10V4Z 1U_0805_25V4Z G G
+3VS 2 2 S Q34 S Q38

3
C206 @ 2N7002_SOT23 @ 2N7002_SOT23
4.7U_0805_10V4Z
2 2 2
1 1
+3VALW C278 C283

U28 10U_1206_16V4Z 1U_0805_25V4Z 5VS_GATE

2 2
8 D S 1
7 2 R294
D S 100K_0402_5%
6 D S 3
5 4 5VS_GATE 1 2 +12VALW
D G +1.5VS
SI4800DY_SO8 +DDRVCC to +2.5VS (DDR1)
1

2
1 2
1

C281 C293 R290 D +DDRVCC +2.5VS R90

2 SUSP @470_0402_5%
10U_1206_16V4Z 0.1U_0402_16V4Z @ 1M_0402_5% G U1
2 1 Q33
S 8 1
2

1
2N7002_SOT23 D S
7 D S 2
6 D S 3

1
D
5 D G 4 1 1
C6 C9 2 SUSP
SI4800DY_SO8 G
1 4.7U_0805_10V4Z 1U_0805_25V4Z S Q14

3
2 2 @ 2N7002_SOT23
C7
4.7U_0805_10V4Z
2
+3VALW +3VALW
+3V
5VS_GATE
3 3

2
1

C159
R209
0.1U_0402_16V4Z
14

14

0_0402_5% U16A 1 U16B

+5VALW +5VALW
P

P
2

1 I O 2 3 I O 4 V_ON <48>
2
G

2
C185 +3VALW POWER +3VALW POWER
SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 R194 R195
7

@ 0.1U_0402_16V4Z 10K_0402_5% 10K_0402_5%

1

1
SUSP SYSON#
<49> SUSP <39> SYSON#

1
+3VS
100K 100K
2 SYSON 2
+3VALW +3VALW <16,26,30,32,35,37,38,49> SUSP# <30,35,39,41,48> SYSON

DTC115EKA_SOT23 DTC115EKA_SOT23
1

100K 100K
R210 Q18 Q19

3
14

14

0_0402_5% U16C U16D

P

P
2

4 5 I O 6 9 I O 8 VS_ON <49> 4
2
G

C186 +3VALW POWER +3VALW POWER

SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
7

@ 0.1U_0402_16V4Z
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
POWER CONTROL CKT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:56 Sheet 42 of 53
A B C D E
 5 4 3 2 1

+3VALW +3V

CF8 CF2 CF3 CF5 CF7

14
SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 U16F +VDDA U31F

14
SN74LVC14APWLE_TSSOP14

P
13 12

P
I O

4
13 12

1
I O

G
13

V+
-

G
D CF6 CF1 CF9 CF10 CF4 SN74LVC14APWLE_TSSOP14 14 D

7
SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 O
12

V-

7
+ U43D
W D@ LMV824MTX_TSSOP14

11
1

1
FD6 FD3 FD5 FD4 FD1 FD2
FIDUCAL FIDUCAL FIDUCAL FIDUCAL FIDUCAL FIDUCAL

+3VALW
1

1
+VDDA

14
U16E

4
P
11 10 13 +12VALW

V+
I O -
O 14

G
12

V-
SN74LVC14APWLE_TSSOP14 + U44D U5B

7
H11 H22 H15 H2 H16 H21 W D@ LMV824MTX_TSSOP14 5 +IN

11
SCREW S315D118 SCREW S315D118 SCREW S315D118 SCREW S315D118 SCREW S315D118 SCREW S315D118 7
OUT
6 -IN

LM358A_SO8
1

1
C +VDDA C

4
H1 H12 H18 H23 H5 13

V+
SCREW S315D118 SCREW S315D118 SCREW S315D118 SCREW S315D118 SCREW S394D157 -
O 14
12

V-
+ U45D
W D@ LMV824MTX_TSSOP14

11
1

H9 H13 H10 H14 H7 H20

SCREW C295D177 SCREW C295D117 SCREW C295D117 SCREW C295D117 SCREW C315D118 SCREW C315D118

+3VALW
1

14
4

1
U26B U26A
B B

P
OE#

OE#
H17 H19 H3 H6 5 6 2 3
SCREW C236D157 SCREW C236D157 SCREW C315D157 SCREW C315D157 I O I O

G
SN74LVC125APWLE_TSSOP14 SN74LVC125APWLE_TSSOP14

7
1

NPTH
M1 M2 M3 H4 H8
SCREW C197D197 SCREW C236D236 SCREW O276X197D276X197 SCREW C79D79N SCREW C79D79N
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
Screws
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:58 Sheet 43 of 53
5 4 3 2 1
 A B C D

+DC_IN_S1 VIN
PF1
12A_65VDC_451012 VS
JST_S4B-EH DC_IN_S2 1 2 +DC_IN_S1 1 2 VIN PR1
PL1 1M_0402_1%
4 FBM-L18-453215-900LMA90T_1812 1 2
4

1
3 3

1
PR2 VS PR3
2 PC1 PC2 PC3 PC4 61.9K_0402_1% 5.6K_0402_5% PR4
1
2 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K 100P_0402_50V8J 1K_0402_1% 1

2
1 1 2 ACIN <19,35,39>

2
1 PR5

8
PJP1 15.4K_0402_1% PU1A
1 2 3 LM393M_SO8

P
+ PACIN
O 1 PACIN <46,47>
2 -

G
1

1
4
PC5 PR6 PC6 PD1 PR7
1000P_0402_50V7K 20K_0402_1% 0.1U_0402_16V7K RLZ4.3B_LL34 10K_0402_1%

2
2

2
VIN
2 1
Vin Detector
RTCVREF
PD2

2
1N4148_SOD80 PR8
BATT_A 2 1 PD3 10K_0402_1% 3.3V High 14.57 14.01 13.46
1N4148_SOD80
Low 14.06 13.51 12.98

1
1
PR9
1538VCC 33_1206_5% VS
PR10 PQ1
200_0603_5% TP0610K_SOT23

2
PR11
2 CHGRTCP 1 2 3 1 1K_1206_5% 2

1 2
PD4
1

1N4148_SOD80 PR13
1

1
PR12 1K_1206_5%
100K_0402_1% PC7 PC8 2 1 1 2
0.22U_1206_25V7K 0.1U_0603_25V7K VIN B+
2

2
PR15
2

1K_1206_5%
<39,41> 51ON# 1 2 1 2
PR14
22K_0402_1%

1
RTCVREF
PR16
PU2 499K_0402_1%
S-812C33AUA-C2N-T2_SOT89
PR17 PR18
3.3V

2
510_0603_5% 510_0603_5% PR19 PR20
1 2 1 2 3 2 10K_0402_1% 2.2M_0402_5%
+CHGRTC OUT IN
1 2 1 2
VL
1
1

GND PC9

1
PC10 1U_0805_25V4Z
2

1
10U_0805_10V4Z 1 PD5 PR21
2

8
RB715F_SOT323 PU1B 499K_0402_1% PC11
2 5 1000P_0402_50V7K

P
<18,45,47> MAINPWON

2
+
1 7

2
O
3
<46> ACON 3 - 6 1 2 VL 3

G
PR22

1
34K_0402_1%

4
1

1
PR23

1
PC12 LM393M_SO8 237K_0402_1%
PJ1 PJ2 1000P_0402_50V7K PR24

2
2 1 2 1 PC13 66.5K_0402_1%
+3VALWP +3VALW +1.8VSP +1.8VS

2
2 1 2 1 1000P_0402_50V7K

2
JUMP_43X118 JUMP_43X79 PR25

1
D 47K_0402_1%
(5A,200mils ,Via NO.= 10) (150mA,40mils ,Via NO.= 2)
PQ2 2 1 2 PACIN
PJ3 SN7002N_SOT23 G
+5VALWP 2 1 +5VALW PJ4 S

3
2 1

1
+1.5VALWP 2 2 1 1 +1.5VALW
JUMP_43X118
(5A,200mils ,Via NO.= 10) JUMP_43X118 Precharge detector
PJ5 (4A,160mils ,Via NO.= 8)
2
+12VALWP 2 2 1 1 +12VALW
14.3V/13.18V for adapter +5VALWP
PQ3
PJ6 DTC115EUA_SC70
JUMP_43X39
+1.25VSP 2 1 +DDRVTT

3
2 1
(120mA,40mils ,Via NO.= 2)
JUMP_43X118
PJ7 (2A,80mils ,Via NO.= 4)
+2.5VP 2 2 1 1 +DDRVCC
JUMP_43X118
PJ8
4 2 2 1 1
4

JUMP_43X118
(8A,320mils ,Via NO.= 16)
PJ9
2 1
+1.05VSP 2 1 +1.05VS Security Classification Compal Secret Data Compal Electronics, Inc.
JUMP_43X118 2005/05/06 2006/05/06 Title
Issued Date Deciphered Date
(4A,160mils ,Via NO.= 8) DCIN & DETECTOR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
INC. Date: 2005/5/6 下午 11:47:57 Sheet 44 of 53
A B C D
 A B C D

PH1 under CPU botten side :

CPU thermal protection at 84 degree C
Recovery at 45 degree C
1 1

PF2 VMB_A PL2 VL VS VL

PJP2 12A_65VDC_451012 FBM-L18-453215-900LMA90T_1812
1 BATT_A_S1 1 2 1 2
BATT+ BATT_A

2
PR27
1K_0402_1% PR28

1
2 ALI/NIMH# 1 2 47K_0402_1% PR26
ID AB/I PH1 PC14 47K_0402_1%
B/I 3 1 2 +3VALWP MAINPWON <18,44,47>

1
4 TS_A 0.1U_0603_25V7K

1
TS EC_SMDA PC15 PC16 PR29
SMD 5

1
6 EC_SMCA 1000P_0402_50V7K 0.01U_0402_25V7Z 10KB_0603_1%_TH11-3H103FT 1 2

2
SMC PR30 47K_0402_1% PQ4
GND 7

8
1K_0402_1% PR31 DTC115EUA_SC70
TYCO_1775828-1_7P_RV 1 2 3 PU3A

P
+
2

16.9K_0402_1% 1 2 1 2

2
O
2 TM_REF1 2 -

G
PR32 PR33 PD6
100_0402_5% 100_0402_5% LM393M_SO8 1SS355_SOD323
ALI/MH# <35>

4
1

3
1
PR35
1

1
6.49K_0402_1% PR34
2 1 PC17 3.32K_0402_1%
+3VALWP
0.22U_0805_16V7K_V2

2
1

1
2 1 VL
PR37 PC18 PR36
1K_0402_1% 1000P_0402_50V7K 100K_0402_1%

2
2 2
2

1
BATT_TEMP <35>
PR38
100K_0402_1%
EC_SMB_DA1 <35,37>

2
EC_SMB_CK1 <35,37>

PH2 near main Battery CONN :

BAT. thermal protection at 79 degree C
Recovery at 45 degree C

VL VL

3 3

2
PH2 PR39
47K_0402_1%
10KB_0603_1%_TH11-3H103FT PR40
47K_0402_1%

1
1 2

PR41

8
14.7K_0402_1% PU3B
1 2 5

P
+
O 7 2 1
TM_REF1 6 -

G
PD7

1
PR42 LM393M_SO8 1SS355_SOD323

4
PC19 3.48K_0402_1%
0.22U_0805_16V7K_V2

4
2 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
BATTERY CONN / OTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
INC. Date: 2005/5/6 下午 11:47:56 Sheet 45 of 53
A B C D
 A B C D

Iadp=0~4.7A
P2 P3 B+
PQ5
PQ6 PQ7 PR43 AO4407_SO8
AO4407_SO8 AO4407_SO8 0.015_2512_1% PJ10 1 8
VIN 8 1 1 8 2 1 2 2 1 1 B++ 2 7
7 2 2 7 3 6

1
6 3 3 6 JUMP_43X118 5
5 5 PC20 PC21 PC22
4.7U_1206_25V6K 4.7U_1206_25V6K 4.7U_1206_25V6K

4
4

4
1 1
1

1
PR44 PR45
47K_0402_1% PQ8 200K_0402_1%
3
DTA144EUA_SC70 PR46
47K_0402_1%
2

2
47K

1
1 2 VIN
2 PU4
47K

2
<35> ADP_I 1 -INC2 24

2
+INC2

3
2
1
PC23 PR48
0.1U_0603_25V7K 100K_0402_1% PQ9 PR47
2 1 2 23 AO4407_SO8 1K_0402_1%
OUTC2 GND
1

PC24 DH_CHG 4 ACOFF#

1

1
0.022U_0402_16V7K
3 22 CS 1 2
+INE2 CS

1
2

1
4 -INE2 VCC(o) 21 1 2

1
PQ10 PC26 PR49 PR50 PR51

5
6
7
8
DTC115EUA_SC70 0.1U_0402_16V7K 10K_0402_1% 25.5K_0402_1% 10K_0402_1% PC25 2 ACOFF <35>
1

D 0.1U_0603_25V7K
1 2 1 2 5 20
3

2
PR52 FB2 OUT PC28 PQ11
2

2
G 100K_0402_1% PC27 0.1U_0603_25V7K DTC115EUA_SC70
S PQ12 4700P_0402_25V7K 6 19 1 2 LX_CHG
3

3
SN7002N_SOT23 PR53 VREF VH PC31
2

1
1K_0402_1% 0.1U_0603_25V7K
PC29 1 2 1 2 7 18 1 2
ACOFF#1 0.1U_0402_16V7K FB1 VCC
2
CC=0.5~3.3A

2
2 PC30 2

PD11 1000P_0402_50V7K 8 17 1 2
1SS355_SOD323 -INE1 RT PR54 CV=12.6V(6 CELLS LI-ION)
68K_0402_5%
1

D PL3
<35> IREF 1 2 9 +INE1 -INE3 16
PACIN 1 2 2 PR55 PR58 PR59 15U_SPC-1204P-150_4A_20%
<44,47> PACIN
G PQ13 143K_0402_1% 10K_0402_1% 47K_0402_1% 1 2 1 2 BATT_A
PR56 S SN7002N_SOT23 2 1 10 15 1 2 1 2
3

OUTC1 FB3
1
3K_0402_1% PR57
1

1
PC32 0.02_2512_1%
PR60 PC33 11 14 ACON 1500P_0402_50V7K PD12
<44> ACON OUTD CTL

1
100K_0402_1% 0.1U_0402_16V7K EC31QS04
2

PC34 PC36
2

12 13 4.7U_1206_25V6K 4.7U_1206_25V6K

2
-INC1 +INC1
IREF=1.31*Icharge PC35
MB3887_SSOP24 4.7U_1206_25V6K
IREF=0.6V~3.21V
SE_CHG+
+3VALWP
CS
4.2V
1

2 1 2 1
1

PR63 PQ14 PR61 PR62

47K_0402_1% DTC115EUA_SC70 150K_0603_0.1% 300K_0603_0.1%
2

3 2 3

PQ16
1

DKN_B+ AO4407_SO8 B+

8 1
3

7 2
<35> FSTCHG 2 6 3
PQ15 5
DTC115EUA_SC70

4
PR64
3

VMB_A 27K_0402_1%
B+ 1 2

2
1

1 2 PR65
PR66 10K_0402_1%
OVP voltage : LI 340K_0402_1% PC37
3S2P : 13.5V--> BATT_OVP= 1.5V 1U_1206_25V7K

1
2

PU5B
(BAT_OVP=0.1111 *VMB)

1
LM358A_SO8 5
+
1

+5VALWP 7 0
- 6
PR67
499K_0402_1% 2
<35> DKN_B+_ON
8

PU5A
2

LM358A_SO8 3 PQ17
P

+ DTC115EUA_SC70
1 0
4 <35> BATT_AOVP 2 4

3
-
G

PC38
4
1

0.01U_0402_25V7Z
PR68 PR69
2

2.2K_0402_5% 105K_0402_1%
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title

CHARGER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
INC. Date: 2005/5/6 下午 11:47:58 Sheet 46 of 53
A B C D
 5 4 3 2 1

PC39
4.7U_1210_25V6K
N4 1 2

1
D D

2
PC40 PD13
B+++ PC41 470P_0805_100V7K EC11FS2_SOD106

1
PJ11 1 2 BST_3.3V BST_5V

2
2 1 SNB 2 1 FLYBACK
B+ 2 1 0.1U_0603_25V7K

2
JUMP_43X118 PR70

8
7
6
5
22_1206_5%
1

PC43

D
D
D
D

2
PC42 4.7U_1206_25V6K PQ18
4.7U_1206_25V6K SI4800BDY_SO8 VS PD14
2

DAP202U_SOT323 1 2

3
G
S
S
S
PT1
PC44 B+++ 10uH_SDT-1205P-100-118_5A_20%

1
2
3
4

2
0.1U_0603_25V7K

1
VL
LX_3.3V PD15

5
6
7
8
1SS355_SOD323 +12VALWP
8
7
6
5
PQ19

D
D
D
D
1

1
D SI4800BDY_SO8
D
D
D

1
PQ20 PC45 PC46

1
SI4810BDY-T1_SO8 PC47 4.7U_1206_25V6K 4.7U_1206_25V6K

2
1

G
S
S
S
PC48 4.7U_0805_6.3V6K PR71

2
G

1
S
S
S

0.1U_0603_25V7K 1.54K_0402_1%

4
3
2
1
PC49
1
2
3
4

2
1

4.7U_1206_25V6K

DH_3.3V

2
1

DL_3.3V
PL4 PC50

5
6
7
8

1
C 10UH_SPC-1205P-100_4.5A_20% 47P_0402_50V8J C
2

2 1 PC51

D
D
D
D
PR72 47P_0402_50V8J
2

2
1.27K_0402_1% PQ21

22

21
2

PU6 SI4810BDY-T1_SO8

1
S
S
S
PR73 PC52 25 4

V+

VL
1.27K_0402_1% 0.47U_0603_16V7K BST3 12OUT
5
2

4
3
2
1
VDD PR74
27 DH3 BST5 18
2

16 DH_5V 2M_0402_1%
1

PR75 DH5 LX_5V

2 1 26 17

2
1M_0402_1% PR76 LX3 LX5 DL_5V
24 DL3 DL5 19
+3VALWP 0_0402_5% ISE_3.3V+ 20
PR77 PGND ISE_5V+
14
1

620_0402_5% CSH5
1 CSH3 CSL5 13
2 1 ISE_3.3V- 2 12
CSL3 FB5

1
VSE_3V 3 15
FB3 SEQ

1
1 <44,46> PACIN 1 2 10 SKIP# REF 9 2.5VREF
1

PR78 23 6 PC53 PR79

SHDN# SYNC
1

1
PC54 + PD16 10K_0402_1% 11 0.47U_0603_16V7K 698_0402_1%

2
220U_6.3VM_R15 SKUL30-02AT_SMA PR80 RST# PC56
7

2
3.32K_0402_1% PC55 TIME/ON5 4.7U_0805_6.3V6K
2

2
2 100P_0402_50V8J 28

GND
+5VALWP
2

RUN/ON3
POK <48>
PR81
1

1
47K_0402_1%

1
VS 1 2 PC57 MAX1902EAI_SSOP28 PR82 1
1

1
1000P_0402_50V7K 10.2K_0402_1% PC58
2

PC59 PR83 100P_0402_50V8J PC60 + PD17

2
@ 100P_0402_50V8J 10K_0402_1% 220U_6.3VM_R15 SKUL30-02AT_SMA
2

2
1

B VSE_5V B
PC61 2
1

2
1

1
@ 0.047U_0603_25V7M
2

PR84 PC62
10K_0402_1% @ 100P_0402_50V8J

2
2 1 VL

2
PR85
220K_0402_5%

MAINPWON <18,44,45>
1

PC63
0.47U_0603_16V7K
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
5V/3.3V/12V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:55 Sheet 47 of 53
5 4 3 2 1
 A B C D

PJ12
ISL6227B+ 2 1 B+
2 1

1
JUMP_43X118

1
1 PC64 PC65 PR86 1

1
4.7U_1206_25V6K 4.7U_1206_25V6K 0_1206_5%

2
PC66 PC67

2
+5VALWP 4.7U_1206_25V6K 4.7U_1206_25V6K

2
1

2
PC68

1
4.7U_0805_6.3V6K PC69 PR87 PC70
0.1U_0603_25V7K 2.2_0603_5% 2.2U_0805_10V6K

2
1
PD18

3
8
7
6
5
DAP202U_SOT323
BST_1.5V

D
D
D
D
2.5V PQ22
SI4800BDY_SO8

BST_2.5V
PC71 PC72

14

28
G
S
S
S
+2.5VP 0.01U_0402_25V7Z PU7 0.01U_0402_25V7Z

5
6
7
8
PL5 2 1 12 SOFT1 17 2 1

VIN

VCC
1
2
3
4
2.2UH_SPC-1205P-2R2B_13A_30% SOFT2

D
D
D
D
1 2 PC74 PQ23
0.1U_0402_16V7K SI4800BDY_SO8
1 2 1 1 2BST_2.5V-1
6 BOOT1 BOOT2 23 BST_1.5V-1
1 2 2 1

G
S
S
S
PR88 PR89
+1.5V
8
7
6
5
+ PC75 PC73 0_0603_5% 0_0603_5%

4
3
2
1
220U_6.3VM_R15 0.1U_0402_16V7K

D
D
D
D
2 2

DH_2.5V 5 24 DH_1.5V PL6 +1.5VALWP

2 PQ24 UGATE1 UGATE2 2.2UH_SPC-1205P-2R2B_13A_30%
SI4810BDY-T1_SO8 LX_2.5V 4 25 LX_1.5V 1 2
PHASE1 PHASE2

G
S
S
S PR91 PR92
1
2
3
4
1

5
6
7
8
1.87K_0402_1% 1.54K_0402_1% 1
1

PR90 1 2ISE_2.5V 7 22 ISE_1.5V 1 2

D
D
D
D
18.2K_0402_1% PC76 ISEN1 ISEN2 PQ25 + PC77
0.01U_0402_25V7Z PR93 DL_2.5V 2 27 DL_1.5V SI4810BDY-T1_SO8 220U_6.3VM_R15
2

LGATE1 LGATE2

1
0_0402_5% PC78
2

1
2

S
S
S
0.01U_0402_25V7Z
2

PR94

4
3
2
1

2
3 26 0_0402_5% PR95
PGND1 PGND2 6.81K_0402_1%

2
9 VOUT1 VOUT2 20
VSE_2.5V 10 19 VSE_1.5V
VSEN1 VSEN2
8 EN1 EN2 21 1 2 POK <47>
1 2 15 16 PR96
<30,35,39,41,42> SYSON PG1 PG2/REF
1

PR97 0_0402_5%

GND

DDR
1

1
PR98 @ 0_0402_5% 11 18
OCSET1 OCSET2

1
10K_0402_1% PR99 1 2 PR100 PR101
<42> V_ON

1
@ 0_0402_5% PR106 ISL6227CA-T_SSOP28 PC79 @ 0_0402_5% 10K_0402_1%

13
1
0_0402_5% @ 0.1U_0402_16V7K
2

2
1

PR103 PR102
2

2
PC80 100K_0402_1% 100K_0402_1%
@ 0.1U_0402_16V7K
2

2
2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
2.5V/1.5V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:56 Sheet 48 of 53
A B C D
 5 4 3 2 1

PR104
10_0603_5% PJ13
1 2 2 2 1 1 +5VALW

2
JUMP_43X118

1
PD19
PC81 1N4148_SOD80 PC82 PC83
1U_0603_6.3V6M 22U_1206_6.3V6M 22U_1206_6.3V6M

2
2
D D

1
1
PR105 PC84

5
6
7
8
6.49K_0402_1% 470P_0603_50V7K

5
PU8

D
D
D
D
2
PQ26

VCC
1
SI4800BDY_SO8

1
1 BST_1.05V
BOOT

G
S
S
S
7 PC85
OCSET 0.1U_0402_16V7K

4
3
2
1
2 DH_1.05V PL7
PR140 UGATE 3UH_SPC-07040-3R0_5A_30%

1
100K_0402_1% D
6 FB 2 1 +1.05VSP
VL 2 1 2 PQ27
G SN7002N_SOT23 8 LX_1.05V
PHASE

5
6
7
8
S 1

3
PR139

D
D
D
D
0_0402_5% PQ28 + PC86
VS_ON 1 2 3 4 SI4800BDY_SO8 220U_6.3VM_R15
GND LGATE

G
2

S
S
S
PR138
1

@ 0_0402_5% D APW7057KC-TR_SOP8

4
3
2
1
SUSP# 1 2 2 PQ38 DL_1.05V
G SN7002N_SOT23
2

S PR107
3

PC87 2.26K_0402_1%
@ 0.1U_0402_16V7K VSE_1.05V 1 2
1

2
C C
1 2
PR108
7.15K_0402_1% PC88
0.1U_0402_16V7K

+DDRVCC

1
PJ14

1
JUMP_43X118

2
PC89

2
1U_0603_6.3V6M
2 1 PU9
1 VIN VCNTL 6 +3VALWP
B PU10 PC90 B
2 GND NC 5

1
0.1U_0402_16V7K PC91
+1.8VSP 1 5 1 2 10U_1206_6.3V7K PR109 3 7 PC92
VOUT BP 1K_0402_1% VREF NC 1U_0603_6.3V6M

2
2 PR141 4 8
GND @ 0_0402_5% VOUT NC

2
+3V 3 VIN SHDN# 4 1 2SUSP# SUSP# <16,26,30,32,35,37,38,42> TP 9
1

PR142 APL5331KAC-TR_SO8
PC93 APL5301-18BC-TR_SOT23-5 0_0402_5%
1U_0603_6.3V6M 1 2VS_ON PR110 +1.25VSP
VS_ON <42>
2

1
0_0402_5% D

1
SUSP 1 2 2 PR111 PC94
<42> SUSP
G 1K_0402_1% 0.1U_0402_16V7K

1
S PQ29

2
1
SN7002N_SOT23 PC95

2
PC96 10U_1206_6.3V7K

2
@ 0.1U_0402_16V7K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
1.05V/1.8V/1.25V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:54 Sheet 49 of 53
5 4 3 2 1
 CPU_B+
+5VS
PL8
FBM-L18-453215-900LMA90T_1812
1 2 B+

4.7U_1206_25V6K

4.7U_1206_25V6K
1

1
PD20 1 1
PR112 EP10QY03

PC97

PC98
10_0603_5% 2 1 BST_CPU1 + PC99 + PC100

2
100U_25V_M 100U_25V_M

2
2 2

2
PC101
2.2U_0603_6.3V6K

2
PC102

5
6
7
8
1U_0603_16V6K PU11 PC103
0.01U_0402_25V7Z

1
PC104 PQ30

2
VCC 10 30 0.22U_0603_16V7K AO4408_SO8
VCC VDD

2
24 36 DH_CPU1 4
<5> CPU_VID0 D0 V+
23 26 BST_CPU1-1 2 PR113 1 PR145
<5> CPU_VID1 D1 BSTM +CPU_CORE
0_0603_5% 0_0603_5%
22 28 DH_CPU1_1 2 1 PL9 PR114
<5> CPU_VID2

3
2
1
D2 DHM 0.56UH_ETQP4LR56WFC_21A_20% 0.001_2512_5%
21 27 LX_CPU1 1 2 1 2
<5> CPU_VID3 D3 LXM

5
6
7
8
20 29 DL_CPU1
<5> CPU_VID4 D4 DLM

1
19 31 PQ31 PR143 CPU VCC SENSE
<5> CPU_VID5 D5 PGND AO4410_SO8 4.7_1206_5%
<6,14,19> VGATE

1
PR115 0_0402_5% 25 37 CM_CPU+
VROK CMP PR116 PR119
1 2 4

1 2
4 38 CM_CPU- 909_0402_1% 499_0402_1%
S0 CMN

1000P_0402_50V7K
VCC PR117 @10_0402_5%2

2
3K_0402_1%
PR122 VCC 5 17 ISE_CPU1+ PC117

2
S1 OAIN+

PR121

PC105
0_0402_5% REF PR120 @10_0402_5%2 680P_0603_50V8J PC106 PR118

3
2
1

2
1 2 6 16 ISE_CPU1- 1 2 499_0402_1%
<35> VR_ON

1
PR123 30.1K_0402_1% SHDN# OAIN-
2 1 1 15 VSE_CPU 0.47U_0603_16V7K

1
TIME FB PR124 909_0402_1%
PR125 1 2 12 14 1 2 1 2
200K_0402_1% PC107 CCV CCI PC108 470P_0402_50V8J @
1 2 270P_0402_50V7K 2 35 BST_CPU2-1
TON BSTS
PR127 1 2 REF 8 33 DH_CPU2_1
66.5K_0402_1% REF DHS
1 2
1 2 PC109 0.22U_0603_16V7K 9 34 LX_CPU2 PR126
ILIM LXS 3K_0402_1%
+5VS
VSE_CPU 1 2 7 32 DL_CPU2 1 2 1 2
OFS DLS
100P_0402_50V8J
10.7K_0402_1%

PR128 3 40 ISE_CPU2+ PC110 PR129

SUS CSP
2

100K_0402_1% 1 2 0.022U_0402_16V7K 0_0402_5%

2
PR130

PC111

0_0603_5%
18 39 ISE_CPU2-
SKIP CSN

PR146
2
1

2
D CPU_B+

0_0603_5%
11 13 PD22
GND GNDS
1

PR131
2 EP10QY03
<14,19> PM_STP_CPU#
1

G 2 PQ33

1
PQ32 S G RHU002N06_SOT323
3

4.7U_1206_25V6K

4.7U_1206_25V6K
RHU002N06_SOT323 S MAX1532AETL_TQFN40
3

1
PC112

5
6
7
8

1
27P_0402_50V8J BST_CPU2
1

PQ34

PC113

PC114
AO4408_SO8

2
0.22U_0603_16V7K
<19> PM_DPRSLPVR 1 2

PC115
PR132 DH_CPU2 4
0_0402_5% +5VS 1 2

2
PR133
2

20K_0402_1% PL10

3
2
1
2

PR134 0.56UH_ETQP4LR56WFC_21A_20%
10K_0402_1% 1 2
PR135

5
6
7
8

1
100K_0402_1%
1 1

1
PR144
1

D PQ35 4.7_1206_5% PR136

2 PQ36 AO4410_SO8 909_0402_1%
G RHU002N06_SOT323

2
S 4
3

2
1

1
2 PQ37
<5> PSI# B HMBT2222A_SOT23 PC118 1 2
E 680P_0603_50V8J
3

3
2
1

2
PC116
0.47U_0603_16V7K

1 2

PR137
909_0402_1%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:54 Sheet 50 of 53
 5 4 3 2 1

ECU00 PIR List

********** From Rev:0.1 to Rev:0.2 PIR List **********

1. Change R30 from 0603 package to 1206 package (Page9)

2. Add filter at CRT signal for EMI request (Page15)
D D
3. Delete F1, D22 and change +CRT_VCC to +5VS (Page15)
4. Delete Software DJ circuit and change +5VCD to +5VS (Page21,22,32)
5. Chnage LAN_LINK and LAN_ACT signal to JP5 pin1,2 (Page28)
6. Add R588, R589, R590, R591 for co-existance function (Page29,36)
7. Add JP31 and R592~R597 for hardware EQ reserve (Page30)
8. Add SKU ID table (Page3,35)
9. Change JP3 and JP17 to 10pin (Page39)
10. Change U30 power from +3VALW to +CHGRTC (Page39)

********** From Rev:0.2 to Rev:0.3 PIR List **********

11. Reverse Q41, Q45 pin1, pin3 (Page28)

12. Non-stuff R586, R587 (Page39)
C 13. Change D27 to Amber LED (Page39) C

14. Change U30 power to RTCVREF (Page39)

15. Non-stuff R268, R556 and Stuff R268, R557 (Page30)
16. Remove SATA 88SA8040 crystal reserve (Page21)
17. Change L1 to SM010012500 (Page9)
18. Add R602, C674 for EMI request (Page36)
19. Change ODD reset to PLT_RST# (Page22)
20. Connect Codec pin16, 17 to EC for EQ (Page30, 35)
21. Add D29 (Page41)
22. Add R604 and change R107 to 470ohm (Page35)
23. Change R568 to 3.3kohm (Page32)
24. Add R611 (Page15)

********** From Rev:0.2 to Rev:0.3 PIR List **********

25. Replace JP2 (Page15)
B B
26. Replace R358 for interfer (Page15)
27. Add three while area for ME.
28. .JP29 change from OCTEK_HDS-22TA1_44P_RV to OCTEK_HDS-22TA1_44P_RV-S.
29. JP30, update Mini PCI new Foot print form QTC to AMP to update outline.
30. U30. update new Foot print from A3212EEH_MLP6_5P to A3212EEH_MLP6_5P-S.
31. Change PCB PN to Rev1.0.
32. C146 的 BOM Structure 7411@ 後有空格 , delete.
33. R603 的 BOM Structure MDC@ 後有空格 , delete.
34. R199 的 BOM Structure 7411@ 改為 5IN1@
35. Change Q6 and Q46 from 2N7002 to SB501380009
36. Add C675 680P for H_NMI.
37. Reserve C676 180P for PCI_SERR#
38. Add C677 220P for H_FERR#
39. Reserve C678 ~ C686 180P for H_SMI#, H_INIT#, SERRIRQ, H_A20M#, H_INTR, H_IGNNE#, H_STPCLK#, H_PWRGOOD and H_CPUSLP#.

A
40. Add R615 ~ R617 0Ohm for EMI solution link DGND and RJ45_GND. A

41. Change R542 from 22 Ohm to 33 Ohm.

42. R527 and C607 change from @ to mount for audio EMI.
43. Add L23 ~ L26 (SM070000H00) and Reserve R618 ~ R625 for EMI Security Classification Compal Secret Data Compal Electronics, Inc.
44. Change U2 to SA411250200 Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title

45. Change C510 and C511 from 33P to 30P (SE071300J00) PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/7 上午 11:21:11 Sheet 51 of 53
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List ) for Power Circuit

Request
Item Page# Title Date Owner Description Rev.
D D

1 50 ADD PR145, PR146

2 46 Change PL3 to 15UH

3 47 Change PC39 to 4.7U_1210

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/05/06 Deciphered Date 2006/05/06 Title
Power changed-List History-1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:47:58 Sheet 52 of 53
5 4 3 2 1
 5 4 3 2 1

45@ ZZZ U4 U12 U36

JST_S4B-EH
DA800001L10 SA0091500N0 SA000013200 SA880360000 D18
4 4 --PCB ZKL LA-2721 --S IC A51 915GM-C1 --S IC PCI1510RGVF PBGA --S IC88E88036 10/100 2 1

3 3 REV1 M/B BGA 1257P GMCH R3 253P PC CARD CTRL LAN CTRL HT-191UYG-DT_GRN_0603
DA800001L10 G@
2 R3GM@ SA0091500N0 1510@ SA000013200 8036@ SA880360000
2 D20
1 U12 T1 2 1
1 U4
PJP1 HT-191UYG-DT_GRN_0603
D SA045100110 SP050001X00 D
SA0000187A0 G@
--S IC PCI4510RGVF PBGA --TST1284B 10/100
--S IC A51 910GML-C1 224P PCI-CARD BUS LAN Transformer D25
BGA 1257P GMCH R3 2 1
4510@ SA045100110 8036@ SP050001X00
R3GML@SA0000187A0 HT-191UYG-DT_GRN_0603
U12 G@

U4 SA064110000 R445 2 1 2K_0402_1%

8036@
SA0091500M0 --S IC PCI6411ZHK PBGA-
--S IC A51 915GM-C1 288 PCI-CARD BUS
BGA 1257P GMCH R1 6411@ SA064110000

R1GM@ SA0091500M0
D17

U4 2 A 1

SA000018790
4 3
--S IC A51 910GML-C1 YG

BGA 1257P GMCH R1

HT-297DQ/GQ_AMB/YG_0603
R1GML@SA000018790 G@

C U4 D19 C

SA0091501J0 2 A 1
--S IC 915PM-C1
BGA 1257P GMCH R1 4 YG 3

R1PM@ SA0091501J0
HT-297DQ/GQ_AMB/YG_0603
G@
U13

SA8280108B0
--S IC A51 FW82801FBM
SL7W6 B2 BGA 609P!
R1SB@ SA8280108B0

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/04/25 Deciphered Date 2006/04/25 Title
For BOM create
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Boston LA-2721
Date: 2005/5/6 下午 11:50:26 Sheet 53 of 53
5 4 3 2 1