00cdb Compal LA-3954P PDF

5 4 3 2 1
COMPAL CONFIDENTIAL
MODEL NAME : E-Docking (For APR)
D D
PCB NO : LA-3954P
COMPAL P/N : TBD
E-Docking Schematics Document

C
E-APR C
2008-04-18
REV : 0.4 (DELL: X03)
B B
A A
MB PCB
DELL CONFIDENTIAL/PROPRIETARY
Part Number Description
BOM NO: TBD Compal Electronics, Inc.
DA40000930L PCB LA-3954P PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
REV0.3 MB
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Cover Sheet
PCB P/N: TBD NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Size Document Number Rev
X03
LA-3954P
Date: Friday, April 18, 2008 Sheet 1 of 29
5 4 3 2 1
5 4 3 2 1
Compal confidential Block Diagram

Model : E-Docking
E Docking Connector
PS8121E Display Port
Display Port/ Repeater
D DVI -VS w/buffer Page 13
D
Display Port #1 Adapters
w/ port sel DVI
TI SN75DP122 Page 13
Page 13
HDMI
Display Port/ PS8121E Display Port

DVI -VS
Repeater w/buffer Page 14
Display Port #2
w/ port sel DVI
TI SN75DP122 Page 14
Page 14
VGA VGA
Page 12
C C
USB 2.0 HUBPage 8

USB 2.0
SMSC USB2513
USB (2) (6) User Ports
Page 9,10,11
USB 2.0 HUBPage 8
SMSC USB2513
Monitor Stand
SMBUS#1 interface Page 5
SATA P -ESATA
Page 10
LIO LPT/RS232
LPC SMSC 47N237 Page 7
Page 6
SMBUS Mic Detect
SMBUS SMBUS#1
B
MIC In B
Page 16
Dock Audio
Dock Audio Intf. Interface
Page 15
HCP Detect Audio Conns
Page 16
LOM RJ45
Page 11
PS2 (x2) PS2 (x2)

Page 9
Power Power
A A
Page TBD
Page 5
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Block Diagram
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. X03
LA-3954P
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
10K 10K 48 (0100 1000)

D D
2N7002 SMSC 47N237

2N7002
+3.3V_SUS
USB_HUB1_RST#
2.2K 2.2K
DOCK_SMB_ALERT#
C DOCK_SMB_DAT 2N7002 C
USB2513
DOCK_SMB_CLK 2N7002
Port 4/5/6
58/59 (0101-100x)
+3.3V_SUS
USB_HUB2_RST#
2.2K 2.2K
USB2513
Port 1/2/3
58/59 (0101-100x)
+3.3V_RUN
B B
2.2K 2.2K
2N7002
Audio
2N7002 SSM2603
34/35 (0011-010X)
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SMBus Block Diagram
LA-3954P
5 4 3 2 1
5 4 3 2 1
D D
ADAPTER +PWR_SRC
Docking
+PWR_SRC
NB_DET#
+3V_ALW2
MAX8778ETJ +5V_ALW
C C
+15V_ALW
NB_DET#
NB_DET#
+5V_ALW +3.3V_ALW
B B
DK_SUSON
DK_RUNON
DK_RUNON
+5V_RUN +3.3V_SUS +3.3V_RUN
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Rail Block Diagram
LA-3954P
5 4 3 2 1
5 4 3 2 1
+5V_ALW
Monitor Stand
1
R253
10K_0402_5%~D
JP1 JMS1
2
DOCK_DET_1 1 2 DOCK_AC_OFF MS_ENABLE# 1
1 2 DOCK_AC_OFF <18> DOCK_PWR_BTN# 1
<11> DOCK_LOM_SPD10LED_GRN# 3 3 4 4 DOCK_LOM_SPD100LED_ORG# <11> DOCK_PWR_BTN# 2 2
D HOT_UNDOCK# D
<13> DP_A_CA_DET1 5 5 6 6 DP_B_CA_DET1 <14> 3 3
7 8 BREATH_PWR_MS_LED# 4
7 8 D10 DOCKED_MS_LED# 4
<13> DP_A_L0+ 9 9 10 10 DP_B_L0+ <14> 5 5
11 12 +5V_ALW 2 1 +5V_ALW_MS 6
<13> DP_A_L0- 11 12 DP_B_L0- <14> 6
13 13 14 14 7 7
15 16 RB500V-40 TE-17_SOD323-2~D
<13> DP_A_L1+ 15 16 DP_B_L1+ <14>
<13> DP_A_L1- 17 17 18 18 DP_B_L1- <14> 8 Shield
19 19 20 20 9 Shield
<13> DP_A_L2+ 21 21 22 22 DP_B_L2+ <14>
23 24 MOLEX_53398-0719
<13> DP_A_L2- 23 24 DP_B_L2- <14>
25 25 26 26
<13> DP_A_L3+ 27 27 28 28 DP_B_L3+ <14>
<13> DP_A_L3- 29 29 30 30 DP_B_L3- <14>
31 31 32 32
<13> DP_A_AUX+ 33 33 34 34 DP_B_AUX+ <14>
<13> DP_A_AUX- 35 35 36 36 DP_B_AUX- <14>
37 37 38 38
<13> DP_A_HP 39 39 40 40 DP_B_HP <14> Q7
3
<18> +NBDOCK_DC_IN_SS 41 41 42 42 ACAV_DOCK_SRC# <18>
43 44 2N7002W-7-F_SOT323-3~D MS_ENABLE# 2 U39
G
43 44 INB BREATH_PWR_MS_LED#
<12> VGA_B 45 45 46 46 VGA_DDC_DAT <7,12> O 4
D
47 48 BREATH_PWR_LED# 3 1 BREATH_PWR_LED_1# 1
47 48 VGA_DDC_CLK <7,12> INA
P
49 50 SN74AHC1G32DCKR_SC70-5~D
49 50
51 52
5
51 52 C204
G
<12> VGA_R 53 54
2
53 54 SATA_SBRX_DTX_P <10>
55 55 56 56 +5V_ALW 2 1
SATA_SBRX_DTX_N <10>
57 57 58 58
59 60 +3.3V_ALW 0.1U_0402_16V4Z~D
<12> VGA_G 59 60 SATA_SBTX_DRX_P <10>
61 61 62 62 SATA_SBTX_DRX_N <10>
63 63 64 64
<12> VGA_HS 65 65 66 66 USB_A_+ <8>
<12> VGA_VS 67 67 68 68 USB_A_- <8>
C C
69 69 70 70
<9> CLK_MSE 71 71 72 72 USB_B_+ <8>
<9> DAT_MSE 73 73 74 74 USB_B_- <8> Q6
3
75 75 76 76
77 78 2N7002W-7-F_SOT323-3~D MS_ENABLE# 2 U40
G
<15> DAI_BCLK 77 78 CLK_KBD <9> INB
79 80 4 DOCKED_MS_LED#
<15> DAI_LRCK 79 80 DAT_KBD <9> O
D
81 82 DOCKED_LED# 3 1 DOCKED_LED_1# 1
<6> D_LAD[0..3] 81 82 <6> DOCKED_LED# INA
P
83 84 RESV_011 SN74AHC1G32DCKR_SC70-5~D
<15> DAI_DI 83 84
<15> DAI_DO 85 86
5
85 86 RESV_010
C203
G
87 88
2
87 88
<15> DAI_12MHZ 89 89 90 90 RESV_021 +5V_ALW 2 1
91 91 92 92 RESV_020
93 94 +3.3V_ALW 0.1U_0402_16V4Z~D
93 94
95 95 96 96
97 98 BREATH_PWR_LED#
<6> D_LAD0 97 98
<6> D_LAD1 99 99 100 100 DOCK_LOM_ACTLED_YEL# <11>
101 101 102 102
<6> D_LAD2 103 103 104 104 DOCK_LOM_TRD0+ <11>
<6> D_LAD3 105 105 106 106 DOCK_LOM_TRD0- <11>
107 108 +DOCK_PWR_BAR R297
107 108 0_0402_5%~D
<6> D_LFRAME# 109 109 110 110 DOCK_LOM_TRD1+ <11>
<6> D_CLKRUN# 111 111 112 112 DOCK_LOM_TRD1- <11> 1 2
100K_0402_5%~D
113 113 114 114
1
115 116 TRCT0_1_DOCK
<6> D_SERIRQ 115 116 TRCT0_1_DOCK <11>
117 118 TRCT2_3_DOCK
<6> D_DLDRQ1# 117 118 TRCT2_3_DOCK <11>
DOCK_DET_2 DOCK_DET_1
S
119 119 120 120 1 3 DOCK_DET_1 <18>
@ R238
121 122 Q25
<6> CLK_PCI_DOCK 121 122 DOCK_LOM_TRD2+ <11>
123 124 @ 2N7002W-7-F_SOT323-3~D
DOCK_LOM_TRD2- <11>
2
123 124
125 126
G
2
125 126
<6,8,16> DOCK_SMB_CLK 127 127 128 128 DOCK_LOM_TRD3+ <11>
129 130 HOT_UNDOCK#
<6,8,16> DOCK_SMB_DAT 129 130 DOCK_LOM_TRD3- <11> <6> HOT_UNDOCK#
131 131 132 132
100K_0402_5%~D
B B
<6> DOCK_SMB_ALERT# 133 133 134 134 DOCK_DCIN_IS+ <18>
0.1U_0603_50V4Z~D
<18> DOCK_PS_ID 135 135 136 136 DOCK_DCIN_IS- <18> 1
137 137 138 138
@ C202
DOCK_PWR_BTN# 139 140 DOCK_POR_RST# <19>
Add net at 12/27.
139 140
@ R239
141 142 NB_DET#
SLICE_BAT_PRES# 141 142 NB_DET# <18> 2
143 144 DOCK_DET_2
2
SLICE_CONN_LOOP# 143 144
145 PWR1 PWR3 149 +DOCK_PWR_BAR

+DOCK_PWR_BAR 146 PWR2 PWR3 150
147 PWR2 PWR3 151
148 PWR2 PWR4 152
153 Shield_G1 Shield_G5 157

154 158 JP2
Shield_G2 Shield_G6 DOCKED_LED_1#
155 Shield_G3 Shield_G7 159 1 1
156 160 BREATH_PWR_LED_1# 2
Shield_G4 Shield_G8 DOCK_PWR_BTN# 2
161 Shield_G9 Shield_G11 163 DOCK_PWR_BTN# 3 3
162 Shield_G10 Shield_G12 164 +5V_ALW 4 4
HOT_UNDOCK# 5 5
6 6
JAE_WD2M144WB1 7 Shield
8 Shield
MOLEX_48227-0611
+DOCK_PWR_BAR
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
0.1U_0603_50V4Z~D
0.1U_0603_50V4Z~D
0.1U_0603_50V4Z~D
0.1U_0603_50V4Z~D
0.1U_0603_50V4Z~D
0.1U_0603_50V4Z~D
1 1 1 1 1 1 1 1 1 1 1 1
A A
C158
C159
C205
C206
C218
C219
C207
C208
C160
C161
C220
C221
2 2 2 2 2 2 2 2 2 2 2 2
Close to connector Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Docking Connector
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD X03
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-3954P
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
+3.3V_RUN
R149 +VTR3 R150 +VTR +VR_CAP +VTR1 +VTR2 +VTR3
0_0402_5%~D @ 0_0402_5%~D
R2 1 2 100K_0402_1%~D D_LAD0 1 2 2 1
R3 1 2 100K_0402_1%~D D_LAD1
0.1U_0402_16V4Z~D
@ 4.7U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
R4 1 2 100K_0402_1%~D D_LAD2 R151 +VTR2 R152 1 1 1 1 1
R5 1 2 100K_0402_1%~D D_LAD3 0_0402_5%~D @ 0_0402_5%~D
C153
C154
C155
C156
C157
1 2 2 1
R6 1 2 100K_0402_1%~D D_LFRAME#
2 2 2 2 2
0.1U_0402_16V4Z~D
R7 @1 2 100K_0402_1%~D D_CLKRUN# 1 R153 +VTR1 R154
R8 @1 2 100K_0402_1%~D D_SERIRQ 0_0402_5%~D @ 0_0402_5%~D
C188
1 2 2 1
R9 @1 2 100K_0402_1%~D D_DLDRQ1#
D 2 R155 +VR_CAP D
0_0402_5%~D
1 2
R228 1 2 @ 100K_0402_1%~D TXD1
R229 1 2 @ 100K_0402_1%~D RTS1# +VTR +3.3V_ALW
13
48
53
65
93
U1
R230 1 2 @ 100K_0402_1%~D DTR1# C21 C23 C25
VCC
VCC
VCC
VCC
VCC
<5> D_LAD[0..3] 10U_0805_10V4Z~D
0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
R240 2 1 10K_0402_5%~D HP_SHTDN# D_LAD0 20 1 2 1
LAD0 VTR
POWER
D_LAD1 21 18 1 1 1 1 1 R156
D_LAD2 LAD1 VTR 0_0402_5%~D
22 LAD2 VTR 32
D_LAD3 23 63
LAD3 VTR
+3.3V_ALW DOCK_SIO_ALERT# RXD1 2 2 2 2 2
17 nIO_PME# RXD 84 RXD1 <7>
D_LFRAME# TXD1 C22 C24
LPC & GPIO

<5> D_LFRAME# 24 nLFRAME# TXD 85 TXD1 <7>
SERIAL PORT
D_DLDRQ1# 25 86 DSR1# 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
<5> D_DLDRQ1# nLDRQ# nDSR# DSR1# <7>
R10 1 2 100K_0402_1%~D DOCK_SIO_ALERT# SIO_RESET# 26 nPCIRST# nRTS# 87 RTS1#
RTS1# <7>
LPCPD# 27 88 CTS1#
nLPCPD# nCTS# CTS1# <7>
R185 2 1 10K_0402_5%~D DOCKED_LED# D_CLKRUN# 28 89 DTR1#
<5> D_CLKRUN# nCLKRUN# nDTR# DTR1# <7>
CLK_PCI_DOCK 29 90 RI1#
<5> CLK_PCI_DOCK PCICLK nRI# RI1# <7>
D_SERIRQ 30 91 DCD1#
<5> D_SERIRQ SER_IRQ nDCD# DCD1# <7>
R15 2 1 10K_0402_5%~D 44
R17 10K_0402_5%~D 45 LGP44
2 1 LGP45
R227 2 1 47K_0402_5%~D LPCPD# R18 2 1 10K_0402_5%~D 46
+3.3V_ALW R19 10K_0402_5%~D 47 LGP46 R20 INIT#
+3.3V_RUN 2 1 SYSOPT/LGP47 nINIT# 66 1 2 33_0402_5%~D INIT# <7>
67 R21 1 2 33_0402_5%~D SLCT_IN#
nSLCTIN# SLCT_IN# <7>
R241 1 2 100K_0402_1%~D DK_RUNON SLCT 77 SLCT
SLCT <7>
10K_0402_5%~D
10K_0402_5%~D
SIO_XTAL1 61 78 PE
XTAL1 PE PE <7>
2
R242 1 2 100K_0402_1%~D DK_SUSON SIO_XTAL2 62 79 BUSY
XTAL2 BUSY BUSY <7>
ACK#
CLK
nACK# 80 ACK# <7>
R27
R28
R183 2 1 10K_0402_5%~D SIO_RESET# +3.3V_ALW 64 81 ERROR# +3.3V_ALW
24MHZ_OUT nERROR# ERROR# <7>
PARALLEL PORT
C R30 AFD# C
nALF# 82 1 2 33_0402_5%~D AFD# <7>
C165 2 1 0.1U_0402_16V4Z~D 83 R31 1 2 33_0402_5%~D STRB#
1 STRB# <7>
1
nSTROBE#
10K_0402_5%~D
47K_0402_1%~D
47K_0402_1%~D
47K_0402_1%~D
47K_0402_1%~D
47K_0402_1%~D
47K_0402_1%~D
PD[0..7] <7>
1
SMB_DAT 3 68 R32 1 2 33_0402_5%~D PD0

SDAT PD0
2
@ SMB_CLK 9 69 R33 1 2 33_0402_5%~D PD1
SCLK PD1
R42
R43
R44
R45
@ R46
@R236
2 70 R34 1 2 33_0402_5%~D PD2
SDAT_1 PD2
R231
8 71 R35 1 2 33_0402_5%~D PD3

SCLK_1 PD3 R36 33_0402_5%~D PD4 @
4 72 1 2
SMBUS
2
SDAT_2 PD4 R37 33_0402_5%~D PD5

10 73 1 2
1
R38 SCLK_2 PD5
0100 1000 2 1 10K_0402_5%~D 5 SMB_A0 PD6 74 R39 1 2 33_0402_5%~D PD6 DOCK_ID0
DOCK_SMB_ALERT# 6 75 R40 1 2 33_0402_5%~D PD7 DOCK_ID1
+3.3V_ALW <5> DOCK_SMB_ALERT# nSMBINT PD7 DOCK_ID2
DTYPE0
1
MIC_DET 15 11 VTT_PWRGD DTYPE1

<16> MIC_DET GPIO10 GPIO30 VTT_PWRGD <19>
R177 ACAV_IN_DOCK 49 33 DOCK_ID0 DTYPE2
<18> ACAV_IN_DOCK GPIO11 GPIO31
10K_0402_5%~D +3.3V_ALW R184 2 1 10K_0402_5%~D 50 34 DOCK_ID1
HOT_UNDOCK# GPIO12 GPIO32 DOCK_ID2
51 GPIO13 GPIO33 35
52 36 DTYPE0
2
GPIO14 GPIO34
2
47K_0402_1%~D
47K_0402_1%~D
47K_0402_1%~D
47K_0402_1%~D
47K_0402_1%~D
47K_0402_1%~D
+3.3V_ALW R179 2 1 10K_0402_5%~D 54 37 DTYPE1
GPIO15 GPIO35
R51
@ R52
R53
@ R54
R55
R237
HOT_UNDOCK# R180 2 1 10K_0402_5%~D 55 38 DTYPE2
<5> HOT_UNDOCK# GPIO16 GPIO36
HP_DET 16 12 R181 2 1 10K_0402_5%~D +3.3V_ALW
<16> HP_DET GPIO17 GPIO37
+3.3V_ALW R182 2 1 10K_0402_5%~D 57 GPIO PORT 92 DPB_LP @
GPIO20 GPIO50 DPB_LP <14>
58 94 DPB_PRI
DPB_PRI <14>
1
<18> PS_ID_DISABLE# LPCPD# GPIO21 GPIO51 DPA_LP
59 GPIO22 GPIO52 95 DPA_LP <13>
HP_SHTDN# 14 96 DPA_PRI
<15> HP_SHTDN# GPIO23 GPIO53 DPA_PRI <13>
+3.3V_ALW R178 2 1 10K_0402_5%~D 40 97 USB_HUB2_RST#
GPIO24 GPIO54 USB_HUB2_RST# <8>
AUX_ON 41 98 USB_HUB1_RST#
GPIO25 GPIO55 USB_HUB1_RST# <8>
DOCKED_LED# 42 99 DK_RUNON
<5> DOCKED_LED# GPIO26 GPIO56 DK_RUNON <7,17>
SIO_RESET# 43 100 DK_SUSON
GPIO27 GPIO57 DK_SUSON <17>
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B B
<17> AUX_ON
AUX_ON Dock ID
7
19
31
39
56
60
76
1
LPC47N237-MT_TQFP100~D
R190
GP33 GP32 GP31
2.7K_0402_5%~D ID2 ID1 ID0
X00 0 0 0
2
X01 0 0 1
note: R60 and C29 are placed near U1 chip
X02 0 1 0
SIO_XTAL1
X03 0 1 1 *
R269@ R41 CLK_PCI_DOCK
1M_0402_5%~D 0_0402_5%~D
A00 1 0 0
SIO_XTAL2
1 2 1 2 A01 1 0 1
2 R60
33_0402_5%~D
DOCK_SMB_DAT SMB_DAT Y1 Dock Type ID
D
<5,8,16> DOCK_SMB_DAT 1 3
Q1 2 1
1
2N7002W-7-F_SOT323-3~D 24MHZ_12PF_1BX24000CE1B~D 1 GP36 GP35 GP34

G
2
C29
10P_0402_50V8J~D ID2 ID1 ID0
C27 C28 2
15P_0402_50V8J~D 12P_0402_50V8J~D
E-APR 0 0 1 *
E-LIO 1 0 0
DOCK_SMB_CLK SMB_CLK
D
<5,8,16> DOCK_SMB_CLK 1 3
A A
Q3
R65 2N7002W-7-F_SOT323-3~D
G
2
0_0402_5%~D
1 2
+3.3V_ALW
Title
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
SMSC 47N237
X03
5 4 3 2 1
5 4 3 2 1
+5V_RUN
1
C31
0.1U_0402_16V4Z~D DCD1
C32 DSR1
2 0.47U_0402_10V4Z~D RXD1#
1 2 RTS1
D TXD1# D
26
U2 CTS1
1 2 3243C1+ 28 DTR1
VCC
C33 0.1U_0402_16V4Z~D C1+ 3243V+ C34 RI1
V+ 27
0.47U_0402_10V4Z~D
3243C1- 24 3 3243V- 1 2
3243C2+ C1- V-
1 2 1 C2+
C35 0.47U_0402_10V4Z~D
270P_0402_50V7K~D
270P_0402_50V7K~D
270P_0402_50V7K~D
270P_0402_50V7K~D
270P_0402_50V7K~D
270P_0402_50V7K~D
270P_0402_50V7K~D
270P_0402_50V7K~D
3243C2- 2
TXD1 C2- TXD1#
<6> TXD1 14 T1IN T1OUT 9 1 1 1 1 1 1 1 1
RTS1# 13 10 RTS1
<6> RTS1# T2IN T2OUT
C36
C37
C38
C39
C40
C41
C42
C43
DTR1# 12 11 DTR1
<6> DTR1# T3IN T3OUT
DCD1# 19 4 DCD1
<6> DCD1# R1OUT R1IN 2 2 2 2 2 2 2 2
RI1# 18 5 RI1
<6> RI1# R2OUT R2IN
RXD1 17 6 RXD1#
<6> RXD1 CTS1# R3OUT R3IN CTS1
<6> CTS1# 16 R4OUT R4IN 7
DSR1# 15 8 DSR1
<6> DSR1# R5OUT R5IN
20 R2OUTB
INVALID# 21
+3.3V_RUN 23 JP5
FORCEON
GND 25
<6,17> DK_RUNON 22 FORCEOFF#
MAX3243ECUI+T_TSSOP28~D 41
42
43
44
45 Serial
46
47
48
C C
49
50
<6> SLCT 16 51
17
<6> PE 18
19 52
PD3 C259 1 2 270P_0402_50V7K~D 20
<6> BUSY
PD[0..7] <6> 21
PD2 C260 1 2 270P_0402_50V7K~D 22 53
<6> ACK#
23
PD1 C261 1 2 270P_0402_50V7K~D 24
<6> PD7
RP1 +LPT5V 25
PD0 C262 1 2 270P_0402_50V7K~D 26
<6> PD6 Print
PD0 1 8 27
PD1 2 7 28
<6> PD5
PD2 3 6 PD7 C263 1 2 270P_0402_50V7K~D 29
PD3 4 5 30
<6> PD4
PD6 C264 1 2 270P_0402_50V7K~D 31
4.7K_1206_8P4R_5%~D 32
<6> PD3
PD5 C265 1 2 270P_0402_50V7K~D 33
<6> SLCT_IN#
<6> PD2 34
PD4 C266 1 2 270P_0402_50V7K~D 35
<6> INIT#
RP2 +LPT5V 36
<6> PD1
<6> ERROR# 37
PD4 1 8 ACK# C267 1 2 270P_0402_50V7K~D 38
<6> PD0
PD5 2 7 39
<6> AFD#
PD6 3 6 BUSY C268 1 2 270P_0402_50V7K~D STRB# 40
PD7 4 5
PE C269 1 2 270P_0402_50V7K~D
B 4.7K_1206_8P4R_5%~D +LPT5V B
SLCT C270 1 2 270P_0402_50V7K~D D1
+5V_RUN 2 1 1
<5,12> VGA_DDC_CLK VGA_DDC_CLK 11
SLCT_IN#C271 1 2 270P_0402_50V7K~D RB751V_SOD323-2~D 6
1
RP3 +LPT5V 2
INIT# C272 1 2 270P_0402_50V7K~D R67 <12> JVGA_VS JVGA_VS 12
AFD# 1 8 1K_0402_5%~D <12> +CRT_VCC +CRT_VCC 7
ERROR# 2 7 ERROR# C273 1 2 270P_0402_50V7K~D <12> BLUE BLUE 3 VGA
INIT# 3 6 <12> JVGA_HS JVGA_HS 13
2
SLCT_IN# 4 5 AFD# C274 1 2 270P_0402_50V7K~D STRB# 8
<6> STRB#
1 <12> GREEN GREEN 4
4.7K_1206_8P4R_5%~D <5,12> VGA_DDC_DAT VGA_DDC_DAT 14
C30 9
270P_0402_50V7K~D RED 5
2 <12> RED
15
10
RP4 +LPT5V
SLCT 1 8 TYCO_2-1734198-1
PE 2 7
BUSY 3 6
ACK# 4 5
4.7K_1206_8P4R_5%~D
A A

Title
LPT and RS232
X03
5 4 3 2 1
5 4 3 2 1
+3.3V_SUS +3.3VDDA_USB1
L1
+3.3V_SUS +3.3VDDA_USB1 +3.3V_SUS +3.3V_SUS BLM18PG181SN1_0603~D
P_XTAL1 1 2
1U_0603_10V6K~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 1
1U_0603_10V6K~D
1U_0603_10V6K~D
1U_0603_10V6K~D
0.1U_0402_16V4Z~D
R68 R69 1 1 1 1 1 1 1 1 1
C189
C44
C190
1M_0402_5%~D 0_0402_5%~D
C180
C45
C191
C184
C47
C48
C49
1 2 1 2 P_XTAL2 C46
2 2 10U_0805_10V4Z~D
Y2 2 2 2 2 2 2 2 2 2
24MHZ_12PF_1BX24000CE1B~D
D D
23
10
29
VDD33PLL 36
15
2 1
SMBUS or EEPROM INTERFACE BEHAVIOR
5
U3
15P_0402_50V8J~D
VDDA33
VDDA33
VDDA33
VDD33CR
VDD33
18P_0402_50V8J~D
1
R70
CFG_SEL1 CFG_SEL0
C50
C51
1K_0402_5%~D
1 2 27
Pin25 Pin24
2 +3.3V_SUS VBUS_DET S_USBP1- Internal Default Configuration
USBDN1_DM 1
2 S_USBP1+
S_USBP1- <9> 0 0
USBDN1_DP S_USBP1+ <9>
S_USB1_EN SMBus slave address 58 (0101100x)
<5> USB_A_+ 31
30
USBUP_DP PRTPWR1 12
13 S_USB_OC1# * 0 1
<5> USB_A_- USBUP_DM OCS1_N
1 0 Bus Power Operation / LED Mode = USB
S_USBP2- 2-Wire I2C EEPROMS are support
+3.3V_SUS +3.3V_SUS P_XTAL1 33
USBDN2_DM 3
4 S_USBP2+
S_USBP2- <9> 1 1
XTAL1/CLKIN USBDN2_DP S_USBP2+ <9>
16 S_USB2_EN
PRTPWR2 S_USB_OC2#
OCS2_N 17
2
@ R72 R73 @
2.2K_0402_5%~D 2.2K_0402_5%~D P_XTAL2 32 XTAL2 S_USBP3-
USBDN3_DM 6 S_USBP3- <9>
R162 7 S_USBP3+
0_0402_5%~D 1 18 S_USB3_EN S_USB3_EN <9>
1
FX_SMB_CLK FX1_SMB_CLK PRTPWR3 S_USB_OC3# R263
1 2 24 SCL/SMBCLK/CFG_SEL0 OCS3_N 19 S_USB_OC3# <9>
FX_SMB_DAT 1 2 FX1_SMB_DAT 22 0_0402_5%~D
+3.3V_SUS R163 PCFG_SEL1 SDA/SMBDATA/NON_REM1 S_USB_OC1#
25 HS_IND/CFG_SEL1 1 2 S_USB_OC12# <9>
0_0402_5%~D 8
NC S_USB_OC2#
+3.3V_SUS 1 2 28 SUSP_IND/LOCAL_PWR/NON_REM0 NC 9 1 2
1
R74 20
R221 10K_0402_5%~D NC R265
NC 21
4.7K_0402_5%~D 35 @ 0_0402_5%~D
RBIAS
USB_HUB1_RST# 26 34 +VDD18PLL_1
<6> USB_HUB1_RST#
2
C USB_HUB1_RST# RESET_N VDD18PLL +VDD18_1 R264 C

100K_0402_5%~D
VDD18 14
12K_0402_1%~D
1 11 37 0_0402_5%~D
1 TEST Thermal Slug(VSS)
1U_0603_10V6K~D
1U_0603_10V6K~D
0.1U_0402_10V6K~D
0.1U_0402_16V4Z~D
C75 1 1 1 1 S_USB1_EN 1 2 S_USB12_EN <9>
1
0.1U_0402_16V4Z~D
C52
C53
C54
C55
R215@ USB2513-AEZG_QFN36_6X6~D S_USB2_EN 1 2
2
R75
R76
47K_0402_5%~D
2 2 2 2 R266
2
@ 0_0402_5%~D
2
DOCK_SMB_DAT FX_SMB_DAT
D
<5,6,16> DOCK_SMB_DAT 1 3
Q2
2N7002W-7-F_SOT323-3~D +3.3V_SUS +3.3VDDA_USB2
L2
G
2
+3.3V_SUS +3.3VDDA_USB2 +3.3V_SUS +3.3V_SUS BLM18PG181SN1_0603~D

1 2
1U_0603_10V6K~D
1U_0603_10V6K~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 1 1 R298
VDDA33 1U_0603_10V6K~D
1U_0603_10V6K~D
1 1 1 1 1 1 1 1 0_0402_5%~D
C192
C56
C193
C185
S_USB_OC4# 1 2 S_USB_OC45# <11>
C57
C181
C194
C59
C60
C61
DOCK_SMB_CLK FX_SMB_CLK C58
D
<5,6,16> DOCK_SMB_CLK 1 3
Q4 2 2 2 10U_0805_10V4Z~D S_USB_OC5# 1 2
2N7002W-7-F_SOT323-3~D 2 2 2 2 2 2 2 2
R66 R299
G
2
0_0402_5%~D @ 0_0402_5%~D
23
VDDA33 10
29
VDD33PLL 36
15
VDDA33 5
+3.3V_SUS 1 2 U5
VDD33CR
VDD33
B R80 R301 B
1K_0402_5%~D 0_0402_5%~D
+3.3V_SUS 1 2 27 S_USB4_EN 1 2
VBUS_DET S_USB45_EN <11>
1 S_USBP4-
+3.3V_SUS USBDN1_DM S_USBP4- <11>
2 S_USBP4+ S_USB5_EN 1 2
31 12 S_USB4_EN
<5> USB_B_+ USBUP_DP PRTPWR1
30 13 S_USB_OC4# R300
<5> USB_B_- USBUP_DM OCS1_N
1
@ 0_0402_5%~D
R222
4.7K_0402_5%~D 3 S_USBP5-
+3.3V_SUS +3.3V_SUS USBDN2_DM S_USBP5- <11>
S_XTAL1 33 4 S_USBP5+
XTAL1/CLKIN USBDN2_DP S_USBP5+ <11>
16 S_USB5_EN
2
USB_HUB2_RST# PRTPWR2 S_USB_OC5#

OCS2_N 17
2
1 R81 R82
C81 2.2K_0402_5%~D 2.2K_0402_5%~D S_XTAL2 32
0.1U_0402_16V4Z~D XTAL2 S_USBP6-
USBDN3_DM 6 S_USBP6- <10>
R166 7 S_USBP6+
2 USBDN3_DP S_USBP6+ <10>
0_0402_5%~D 18 S_USB6_EN
S_USB6_EN <10>
1
FX_SMB_CLK FX2_SMB_CLK PRTPWR3 S_USB_OC6#

1 2 24 SCL/SMBCLK/CFG_SEL0 OCS3_N 19 S_USB_OC6# <10>
FX_SMB_DAT 1 2 FX2_SMB_DAT 22
R167 SCFG_SEL1 25
SDA/SMBDATA/NON_REM1
HS_IND/CFG_SEL1
SMBUS or EEPROM INTERFACE BEHAVIOR
0_0402_5%~D 8
NC
+3.3V_SUS 1
R83
2 28 SUSP_IND/LOCAL_PWR/NON_REM0 NC 9
20
CFG_SEL1 CFG_SEL0
S_XTAL1 10K_0402_5%~D NC
35
NC 21 Pin25 Pin24
RBIAS
0 0 Internal Default Configuration
R77 R78 USB_HUB2_RST# 26 34 +VDD18PLL_2
<6> USB_HUB2_RST# RESET_N VDD18PLL
1M_0402_5%~D 0_0402_5%~D +VDD18_2 SMBus slave address 58 (0101100x)
VDD18 14
* 0 1
100K_0402_5%~D
12K_0402_1%~D
1 2 1 2 S_XTAL2 11 TEST Thermal Slug(VSS) 37

1
1U_0603_10V6K~D
1U_0603_10V6K~D
0.1U_0402_10V6K~D
0.1U_0402_16V4Z~D
1 1 1 1 1 0 Bus Power Operation / LED Mode = USB

1
Y3
C64
C65
C66
C67
A 24MHZ_12PF_1BX24000CE1B~D R216@ USB2513-AEZG_QFN36_6X6~D 2-Wire I2C EEPROMS are support A

1 1
R84
R85
2 1 47K_0402_5%~D
2 2 2 2
2
2
18P_0402_50V8J~D
15P_0402_50V8J~D
1
C62
C63
2 Compal Electronics, Inc.

Title
SMSC USB2513
X03
5 4 3 2 1
5 4 3 2 1
@ FUSE1 @L3
@ L3 DLW21SN900SQ2_0805~D
L0603 1 1 USBP2_D+
<8> S_USBP2+ 2 2
1 2
+USB_A_PWR
+USB_A_PWR 4 3 USBP2_D-
<8> S_USBP2- 4 3
+5V_ALW PJP8 U7 U10 @
PAD-OPEN 4x4m 1 8 S_USB_OC12# S_USB_OC12# <8> R86 0_0402_5%~D USBP1_D+ 1 4 USBP2_D+
GND OC1# D1+ D2+
2 1 2 IN OUT1 7 2 1
<8> S_USB12_EN 3 EN1 OUT2 6 2 GND VCC 5 +USB_A_PWR
150U_D_6.3VM_R18M~D
0.1U_0402_16V4Z~D
Short mode 4 5 R87 0_0402_5%~D
EN2 OC2#
10U_1206_16V4Z~D
0.1U_0402_16V4Z~D
2 1 USBP2_D- 3 6 USBP1_D- 1 1
D2- D1-
C69
D TPS2066ADR_SO8~D D
C68
IP4220CZ6_SO6~D +
1 1
C71
C72
@ L4
@L4 DLW21SN900SQ2_0805~D
USBP1_D- 2 JUSB1
<8> S_USBP1- 1 1 2 2
@ 2 USB
1 VBUS
2 2 USBP2_D- 2 D-
4 3 USBP1_D+ USBP2_D+ 3 PORT1
<8> S_USBP1+ 4 3 D+
4 GND
R89 0_0402_5%~D
2 1 +USB_A_PWR 5 VBUS
USBP1_D- 6
R88 0_0402_5%~D USBP1_D+ D- PORT2
7 D+
2 1 8 GND
+USB_B_PWR 9 VBUS
2008.03.12 modify USBP3_D- 10
USBP3_D+ D- PORT3
11 D+
@FUSE3
@ FUSE3 +USB_B_PWR 12
L0603 GND
1 2 13 SHLD1
+USB_B_PWR 14
@ L5
@L5 DLW21SN900SQ2_0805~D D25 @ SHLD2
15 SHLD3
+5V_ALW PJP10 U37 1 1 USBP3_D- +USB_B_PWR
PAD-OPEN 4x4m S_USB_OC3#
<8> S_USBP3- 2 2 1 GND VCC 4 16 SHLD4
1 GND OC1# 8 S_USB_OC3# <8> Need close JUSB1.
2 1 2 7 FOX_UB11123-M4-4F
IN OUT1
150U_D_6.3VM_R18M~D
0.1U_0402_16V4Z~D
3 6 4 3 USBP3_D+ USBP3_D+ 2 3 USBP3_D-
Short mode EN1 OUT2 <8> S_USBP3+ 4 3 IO1 IO2
<8> S_USB3_EN 4 EN2 OC2# 5 1
10U_1206_16V4Z~D
0.1U_0402_16V4Z~D
R90 0_0402_5%~D PRTR5V0U2X_SOT143-4~D 1
C73
+
C74
TPS2066ADR_SO8~D 2 1
1 1
C77
C76
R91 0_0402_5%~D
2 2
2 1
C @ C
2 2
L9 F1
BLM21PG600SN1D_0805~D 3A_6VDC_2920SMD300
1 2 +5V_RUN_PS2_A 1 2 +5V_RUN_PS2
+5V_RUN
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
+5V_RUN
1 1
C92
C213
B 2 2
PS2 Connector B
1
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
@ @ @ @
R105
R106
R107
R108
2
2
L10 JPS1
BLM18AG601SN1D_0603~D 3
<5> DAT_KBD 1 2 5
1
L11 KEYBOARD
BLM18AG601SN1D_0603~D DAT_KBD_1 2 PURPLE
1 2 CLK_KBD_1 6
<5> CLK_KBD
4
L12
BLM18AG601SN1D_0603~D 9
1 2 DAT_MSE_1 11
<5> DAT_MSE
7 13
L13 MOUSE 14
BLM18AG601SN1D_0603~D 8 GREEN 15
1 2 CLK_MSE_1 12 16
<5> CLK_MSE
10
TYCO_1734336-6
270P_0402_50V7K~D
270P_0402_50V7K~D
270P_0402_50V7K~D
270P_0402_50V7K~D
1 1 1 1
C93
C94
C95
C96
2 2 2 2
A A
Title
USB Port x3 and PS2x2
X03
5 4 3 2 1
5 4 3 2 1
+USB_D_PWR
D34 @
1 GND VCC 4
JESATA
+USB_D_PWR 1 VBUS
USBP6_D+ 2 3 USBP6_D- USBP6_D- 2
IO1 IO2 USBP6_D+ D- USB
3 D+
PRTR5V0U2X_SOT143-4~D 4 GND
D D
5 GND
SATA_SBTX_C_DRX_P 6
@ FUSE9 SATA_SBTX_C_DRX_N T+ ESATA
7 T-
L0603 8
+USB_D_PWR SATA_SBRX_C_DTX_N_1 SATA_SBRX_C_DTX_N GND
1 2 2 1 9 R-
C83 0.01U_0402_16V7K~D 10
SATA_SBRX_C_DTX_P_1 SATA_SBRX_C_DTX_P ESATA_DET R+
2 1 11 GND
+5V_ALW PJP7 U33 @ L33 DLW21SN900SQ2_0805~D C84 0.01U_0402_16V7K~D
PAD-OPEN 4x4m 1 8 S_USB_OC6# 1 1 USBP6_D+
GND OC1# S_USB_OC6# <8> <8> S_USBP6+ 2 2 12 SHLD1
2 1 2 IN OUT1 7 13 SHLD2
3 EN1 OUT2 6 14 SHLD3
Short mode S_USB6_EN_1 4 5 4 3 USBP6_D- 15
EN2 OC2# <8> S_USBP6- 4 3 +USB_D_PWR SHLD4
10U_1206_16V4Z~D
0.1U_0402_16V4Z~D
TPS2066ADR_SO8~D R302 0_0402_5%~D Need close JESATA. TYCO_1909573-3

1 1 2 1
C197
C198
150U_D_6.3VM_R18M~D
0.1U_0402_16V4Z~D
R303 0_0402_5%~D
@ 2 1 1
2 2
1
C255
+
C256
2 2
C C
+1.8V_RUN +1.8V_RUN
U42
2 VDD EN 20 1 2
6 R262 10K_0402_5%~D
VDD
11 VDD
+5V_ALW 15 SATA_SBTX_C_DRX_P_1 2 1 SATA_SBTX_C_DRX_P
VDD C244 0.01U_0402_16V7K~D
19 VDD
C211 R308
2 1 SATA_SBTX_DRX_P 3 18 470_0402_5%~D
<5> SATA_SBTX_DRX_P AI+ AO+
5
0.1U_0402_16V4Z~D SATA_SBTX_DRX_N 4 17 SATA_SBTX_C_DRX_N_1 2 1 SATA_SBTX_C_DRX_N

SN74AHC1G32DCKR_SC70-5~D <5> SATA_SBTX_DRX_N AI- AO-
S_USB6_EN 1 C245 0.01U_0402_16V7K~D
P
<8> S_USB6_EN INA S_USB6_EN_1 SATA_SBRX_DTX_P SATA_SBRX_C_DTX_P_1

O 4 <5> SATA_SBRX_DTX_P 7 BO+ BI+ 14
2 INB
G
U41 SATA_SBRX_DTX_N 8 13 SATA_SBRX_C_DTX_N_1

+5V_ALW <5> SATA_SBRX_DTX_N BO- BI-
3
GND 5
1
+5V_ALW R267 1 2 1K_0402_5%~D 1 9

R188 EQA GND
GND 12
10K_0402_5%~D R268 1 2 1K_0402_5%~D 10 16
EQB GND
1
R187 PI2EQX3211BHE_SSOP20~D
2
10K_0402_5%~D
1
D
2
ESATA_DET 2 Q5
G 2N7002W-7-F_SOT323-3~D
B S B
3
R293 R287
@ 0_0402_5%~D @ 0_0402_5%~D
SATA_SBRX_DTX_P 1 2 SATA_SBRX_P 1 2SATA_SBRX_C_DTX_P_1
R294 R288
+3.3V_RUN NCP1117ST18T3G_SOT223-3~D +1.8V_RUN +1.8V_RUN @ 0_0402_5%~D @ 0_0402_5%~D
SATA_SBRX_DTX_N 1 2 SATA_SBRX_N 1 2SATA_SBRX_C_DTX_N_1
ADJ/GND
Need close U42 pin 6, 19.

3 2 R295 R289
IN OUT
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
@ 0_0402_5%~D @ 0_0402_5%~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
SATA_SBTX_DRX_P 1 2 SATA_SBTX_P 1 2SATA_SBTX_C_DRX_P_1

1 1 U43 1 1
1
C238
C239
C240
C241
1 1 R296 R290
C253
C254
@ 0_0402_5%~D @ 0_0402_5%~D
@ @ SATA_SBTX_DRX_N 1 2 SATA_SBTX_N 1 2SATA_SBTX_C_DRX_N_1
2 2 2 2
2 2
A A
Bill0703: Please place under U42. (co-layout..)

Benson0912: If populate R287~290 and R293~R296,
the U42,R262, R267, R268 ,U43, C239, C241 DELL CONFIDENTIAL/PROPRIETARY
is no-stuff and C244,C245 will change to 0ohm.
Title
E-SATA+USB Port x1
X03
5 4 3 2 1
5 4 3 2 1
+3.3V_LAN
JP3
R102
TRCT0_1_2_3 6 13 LED_10_GRN_R# DOCK_LAN_ACTLED_YEL# 1 2 LED_1000_YEL_R#
VCC LED2_GREEN- <5> DOCK_LOM_ACTLED_YEL#
DOCK_LOM_TRD0+ 2 14 150_0402_5%~D
<5> DOCK_LOM_TRD0+ MD1+ LED2_+ R103
DOCK_LOM_TRD0- 3 15 LED_100_ORG_R# DOCK_LED_10# 1 2 LED_10_GRN_R#
<5> DOCK_LOM_TRD0- MD1- LED2_ORANGE- <5> DOCK_LOM_SPD10LED_GRN#
DOCK_LOM_TRD1+ 4 150_0402_5%~D
D <5> DOCK_LOM_TRD1+ MD2+ R104 D
DOCK_LOM_TRD1- 5 DOCK_LED_100# 1 2 LED_100_ORG_R#
<5> DOCK_LOM_TRD1- MD2- <5> DOCK_LOM_SPD100LED_ORG#
LED1_YELLOW+ 12
DOCK_LOM_TRD2+ 7 150_0402_5%~D
<5> DOCK_LOM_TRD2+ MD3+ LED_1000_YEL_R#
LED1_YELLOW- 11
DOCK_LOM_TRD2- 8
<5> DOCK_LOM_TRD2- MD3- +USB_C_PWR
DOCK_LOM_TRD3+ 9
<5> DOCK_LOM_TRD3+ MD4+
VBUS0 16 Need close JP3.
DOCK_LOM_TRD3- 10 17 USBP4_D-
<5> DOCK_LOM_TRD3- MD4- D0-
18 USBP4_D+
D0+ +USB_C_PWR
1 CH_GND GND 19
0.1U_0402_16V4Z~D
24 SHLD1 VBUS1 20
150U_D_6.3VM_R18M~D
25 21 USBP5_D-
SHLD2 D1- USBP5_D+
26 SHLD3 D1+ 22 1
27 SHLD4 GND 23 1
C78
+
C79
TYCO_1840015-1
2 2
Modify symbol at 12/19
C C
@L34
@ L34 DLW21SN900SQ2_0805~D
1 1 USBP4_D+
@FUSE10
@ FUSE10
<8> S_USBP4+ 2 2
L0603
1 2 +USB_C_PWR 4 3 USBP4_D- +USB_C_PWR
<8> S_USBP4- 4 3
R304 0_0402_5%~D U44 @
+5V_ALW PJP11 U45 2 1 USBP4_D+ 1 4 USBP5_D+
PAD-OPEN 4x4m S_USB_OC45# D1+ D2+
1 GND OC1# 8 S_USB_OC45# <8>
2 1 2 7 R305 0_0402_5%~D 2 5
IN OUT1 GND VCC
<8> S_USB45_EN 3 EN1 OUT2 6 2 1
Short mode 4 5 USBP5_D- 3 6 USBP4_D-
EN2 OC2# D2- D1-
10U_1206_16V4Z~D
0.1U_0402_16V4Z~D
TPS2066ADR_SO8~D @ L35 DLW21SN900SQ2_0805~D

@L35 IP4220CZ6_SO6~D
1 1 USBP5_D+
1 1 <8> S_USBP5+ 2 2
C257
C258
@ 4 3 USBP5_D-
2 2 <8> S_USBP5- 4 3
R306 0_0402_5%~D
2 1
R307 0_0402_5%~D
2 1
B B
L31
0_0603_5%~D
1 2 TRCT0_1_2_3
<5> TRCT2_3_DOCK
<5> TRCT0_1_DOCK
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
1 1
C209
C210
@ @
2 2
A
Close to JP3 connector A
Title
RJ45+USB Portx2
X03
5 4 3 2 1
5 4 3 2 1
+5V_RUN
RB500V-40 TE-17_SOD323-2~D
0_1206_5%~D
2
2
D3 D4 D5
R243 @
@ DA204U_SOT323-3~D @ DA204U_SOT323-3~D @ DA204U_SOT323-3~D
D2
1 +CRTVCC 1
1
1
1
D D
+5V_RUN
1.1A_6V_1812L110PR~D
2
0_1206_5%~D
2
@
R109
F4
L14
BK1608HS220T_0603~D
VGA_R 1 2
<5> VGA_R
1
L15
BK1608HS220T_0603~D +CRT_VCC
VGA_G 1 2
<5> VGA_G
L16
BK1608HS220T_0603~D
0.01U_0402_16V7K~D
VGA_B 1 2
<5> VGA_B
2.2P_0402_50V8C~D
2.2P_0402_50V8C~D
2.2P_0402_50V8C~D
2.2P_0402_50V8C~D
2.2P_0402_50V8C~D
2.2P_0402_50V8C~D
1 1 1 1 1 1 1
1
1
150_0402_1%~D
150_0402_1%~D
150_0402_1%~D
C100
C101
C102
C103
C97
C98
C99
R270
R271
R272
2 2 2 2 2 2 2
2
+5V_SYNC
RED RED <7>

VGA_DDC_DAT VGA_DDC_DAT <5,7>
GREEN GREEN <7>
2.2K_0402_5%~D
2.2K_0402_5%~D
1
1
1K_0402_5%~D
1K_0402_5%~D
JVGA_HS JVGA_HS <7>
R110 @
R111 @
C BLUE C
BLUE <7>
R291
R292
+CRT_VCC +CRT_VCC <7>
JVGA_VS JVGA_VS <7>
2
VGA_DDC_CLK VGA_DDC_CLK <5,7>
<5,7> VGA_DDC_DAT
<5,7> VGA_DDC_CLK
L17
68NH_LQW18AN68NJ00D_5%_0603
HSYNC_BUF 1 2 HSYNC_BUF_1 1 2
R273 10_0402_5%~D L18
68NH_LQW18AN68NJ00D_5%_0603
VSYNC_BUF 1 2 VSYNC_BUF_1 1 2
22P_0402_50V8J~D
22P_0402_50V8J~D
10P_0402_50V8J~D
10P_0402_50V8J~D
R274 10_0402_5%~D 1 1 1 1
C104
C105
C106
C107
@ @
2 2 2 2
B B
+5V_RUN
2
D6
RB500V-40 TE-17_SOD323-2~D
1K_0402_5%~D
+5V_SYNC
1
+5V_SYNC 1 2
R113
5
U13
P
OE#
VGA_HS 1 2 HSYNC_L 2 4 HSYNC_BUF

<5> VGA_HS A Y
R114 39_0402_5%~D
G
74AHCT1G125GW_SOT353-5~D
3
DA204U
5
U14
K1 A2
P
OE#
VGA_VS 1 2 VSYNC_L 2 4 VSYNC_BUF

<5> VGA_VS A Y
R116 39_0402_5%~D
G
74AHCT1G125GW_SOT353-5~D
3
A1 K2
A A
Title
CRT
X03
5 4 3 2 1
5 4 3 2 1
JP4 +3.3V_RUN_DPA
U15 1 2
1 2
SDM10U45-7_SOD523-2~D
+3.3V_RUN_DPA R247 1 2 0_0402_5%~D 14 56 DPA_DOCK_RP1_LANE0 DPA_DVI_LANE0# 3 4 DPB_DVI_CLK
R248 VCC DP_SINK0(p) 3 4 DPB_DVI_CLK <14>
1 2 0_0402_5%~D 17 VCC DP_SINK0(n) 55 DPA_DOCK_RP1_LANE0# DPA_DVI_LANE0 5 5 6 6 DPB_DVI_CLK#
DPB_DVI_CLK# <14>
0_1206_5%~D
R249 1 2 0_0402_5%~D 23 7 8
VCC 7 8
2
53 DPA_DOCK_RP1_LANE1 DPA_DVI_LANE1# 9 10 DPB_DVI_LANE2
DP_SINK1(p) 9 10 DPB_DVI_LANE2 <14>
+5V_RUN_DPA 2 52 DPA_DOCK_RP1_LANE1# DPA_DVI_LANE1 11 12 DPB_DVI_LANE2# @
VDD DP_SINK1(n) 11 12 DPB_DVI_LANE2# <14>
R244
D7
8 VDD 13 13 14 14
34 50 DPA_DOCK_RP1_LANE2 DPA_DVI_LANE2# 15 16 DPB_DVI_LANE1
DPB_DVI_LANE1 <14>
+3.3V_RUN_AR 1
VDD DP_SINK2(p) DPA_DOCK_RP1_LANE2# DPA_DVI_LANE2 15 16 DPB_DVI_LANE1#
48 49 17 18 DPB_DVI_LANE1# <14>
1
VDD DP_SINK2(n) 17 18
54 VDD 19 19 20 20
47 DPA_DOCK_RP1_LANE3 DPA_DVI_CLK 21 22 DPB_DVI_LANE0
DP_SINK3(p) 21 22 DPB_DVI_LANE0 <14>
+3.3V_RUN_DPA 38 46 DPA_DOCK_RP1_LANE3# DPA_DVI_CLK# 23 24 DPB_DVI_LANE0#
VDD*1 DP_SINK3(n) 23 24 DPB_DVI_LANE0# <14>
25 25 26 26
45 DPA_DOCK_AUX DPA_DVI_DETECT 27 28 DPB_DVI_DETECT DPB_DVI_DETECT <14> +DPA_VCC
D AUX_SINK(p) DPA_DOCK_AUX# 27 28 D
AUX_SINK(n) 43 29 29 30 30
3A_6VDC_2920SMD300
DPA_DVI_SCLK 31 32 DPB_DVI_SCLK DPB_DVI_SCLK <14>
31 32
0.01U_0402_16V7K~D
DP_A_L0+ 3 40 DP_HPD1_SINK DPA_DVI_SDAT 33 34 DPB_DVI_SDAT DPB_DVI_SDAT <14>
<5> DP_A_L0+ ML_IN0 (p) DP_HPD_SINK 33 34
0_1206_5%~D
10U_0805_10V4Z~D
DP_A_L0- 4 41 DPA_DOCK_CA_DET 35 36
<5> DP_A_L0- ML_IN0 (n) CAD_SINK 35 36
2
32 DPA_DVI_DETECT +5V_RUN_DPA 37 38 +5V_RUN_DPB 1 1
TMDS_HPD_SINK 37 38
100K_0402_5%~D
@
DP_A_L1+ 6 39 40
<5> DP_A_L1+ ML_IN1(p) 39 40
F2
R117
C108
C128
DP_A_L1- 7 19 DPA_DVI_LANE0
<5> DP_A_L1- ML_IN1(n) TMDS_SINK0(p)
100K_0402_5%~D
18 DPA_DVI_LANE0#
TMDS_SINK0(n)
1
2 2
R275
DP_A_L2+ 9
<5> DP_A_L2+
1
DP_A_L2- ML_IN2(p) DPA_DVI_LANE1 TYCO_1775729-1 @
<5> DP_A_L2- 10 ML_IN2(n) TMDS_SINK1(p) 22
R276
21 DPA_DVI_LANE1#
2
DP_A_L3+ TMDS_SINK1(n)
<5> DP_A_L3+ 12 ML_IN3(p)
DP_A_L3- 13 25 DPA_DVI_LANE2
<5> DP_A_L3-
2
ML_IN3(n) TMDS_SINK2(p) DPA_DVI_LANE2#
TMDS_SINK2(n) 24
JDP1
DP_A_AUX+ 36 16 DPA_DVI_CLK 20
<5> DP_A_AUX+ AUX(p)_I2C_SCL TMDS_SINK_CLK(p) L29 DP_PWR
DP_A_AUX- 35 15 DPA_DVI_CLK# 19
<5> DP_A_AUX- AUX(n)_I2C_SDA TMDS_SINK_CLK(n) 0_0402_5%~D RTN
DPA_DOCK_HPD 1 2 DPA_DOCK_HPD_1 18
DPA_DVI_SCLK +3.3V_RUN_DPA DPA_DOCK_AUX# HP_DET
I2C_SCL 29 17 AUX_CH-
DP_A_HP 37 28 DPA_DVI_SDAT 16
DP_A_CA_DET1 HPD I2C_SDA DPA_DOCK_AUX GND
39 CAD 15 AUX_CH+
14 GND
R328 4.7K_0402_5%~D PS_I2C_CTL_EN# DPA_DOCK_CA_DET 13 CA_DET
5.1M_0402_5%~D
DPA_PRI 33 DPA_DOCK_LANE3#_C 12
<6> DPA_PRI Priority LAN3-
1M_0402_5%~D
DPA_LP 30 5 R211 4.7K_0402_5%~D PS_MODE 11 21
<6> DPA_LP LP GND LAN3_shield GND
R119
11 DPA_DOCK_LANE3_C 10 22
GND LAN3+ GND
R232
26 20 DPA_DOCK_LANE2#_C 9 23
VSadj GND LAN2- GND
1 DPVadj GND 27 8 LAN2_shield GND 24
100K_0402_5%~D
4.7K_0402_1%~D
3.48K_0402_1%~D
31 DPA_DOCK_LANE2_C 7
1
GND LAN2+
1
42 DPA_DOCK_LANE1#_C 6
GND LAN1-
R202
44 R317 500_0402_1% PS_REXT 5

GND LAN1_shield
R199
R201
57 51 DPA_DOCK_LANE1_C 4
C Thermal GND C275 2.2U_0603_10V6K~D PS_CEXT DPA_DOCK_LANE0#_C LAN1+ C
3 LAN0-
SN75DP122_QFN56~D 2
2
DPA_DOCK_LANE0_C LAN0_shield
1 LAN0+
MOLEX_47272-0026
Display port Connector

0.033U_0402_16V7K~D
DP_A_HP
<5> DP_A_HP +3.3V_RUN_DPA
100K_0402_5%~D
U46
D28 @
1
@ 1 DPA_DOCK_RP1_LANE0 C251 1 2 0.1U_0402_10V7K~D DPA_DOCK_RP_LANE0 38

DPA_DOCK_RP1_LANE0# IN1p
@ C280 1 2 0.1U_0402_10V7K~D DPA_DOCK_RP_LANE0# 39 IN1n VCC 46 DPA_DOCK_LANE0_C 1 10 DPA_DOCK_LANE0_C
R277
C182
VCC 40
DPA_DOCK_RP1_LANE1 C279 1 2 0.1U_0402_10V7K~D DPA_DOCK_RP_LANE1 41 33 DPA_DOCK_LANE0#_C 2 9 DPA_DOCK_LANE0#_C
2 DPA_DOCK_RP1_LANE1# IN2p VCC
C252 1 2 0.1U_0402_10V7K~D DPA_DOCK_RP_LANE1# 42 21
2
IN2n VCC DPA_DOCK_LANE1_C DPA_DOCK_LANE1_C

VCC 15 4 7
DPA_DOCK_RP1_LANE2 C277 1 2 0.1U_0402_10V7K~D DPA_DOCK_RP_LANE2 44 11
DPA_DOCK_RP1_LANE2# C281 1 IN3p VCC
2 0.1U_0402_10V7K~D DPA_DOCK_RP_LANE2# 45 IN3n
DPA_DOCK_LANE1#_C 5 6 DPA_DOCK_LANE1#_C
23 DPA_DOCK_LANE0 C222 1 2 0.1U_0402_10V7K~D DPA_DOCK_LANE0_C
DPA_DOCK_RP1_LANE3 C278 1 DPA_DOCK_RP_LANE3 47 OUT1p DPA_DOCK_LANE0# DPA_DOCK_LANE0#_C
2 0.1U_0402_10V7K~D IN4p OUT1n 22 C223 1 2 0.1U_0402_10V7K~D 3
DPA_DOCK_RP1_LANE3# C243 1 2 0.1U_0402_10V7K~D DPA_DOCK_RP_LANE3# 48 IN4n DPA_DOCK_LANE1 C224 1 DPA_DOCK_LANE1_C 8
OUT2p 20 2 0.1U_0402_10V7K~D
DPA_DOCK_AUX C290 1 2 0.1U_0402_10V7K~D DPA_DOCK_RP_AUX 8 19 DPA_DOCK_LANE1# C225 1 2 0.1U_0402_10V7K~D DPA_DOCK_LANE1#_C
DP_A_CA_DET1 DPA_DOCK_AUX# C291 1 SCL/AUX+ OUT2n
<5> DP_A_CA_DET1 2 0.1U_0402_10V7K~D DPA_DOCK_RP_AUX# 9 SDA/AUX-
RCLAMP0524P.TCT~D
100K_0402_5%~D
17 DPA_DOCK_LANE2 C226 1 2 0.1U_0402_10V7K~D DPA_DOCK_LANE2_C

OUT3p
1
@ +3.3V_RUN_DPA 29 16 DPA_DOCK_LANE2# C227 1 2 0.1U_0402_10V7K~D DPA_DOCK_LANE2#_C

SCLZ OUT3n D29 @
28 SDAZ
R278
R322 1 2100K_0402_5%~D 14 DPA_DOCK_LANE3 C228 1 2 0.1U_0402_10V7K~D DPA_DOCK_LANE3_C DPA_DOCK_LANE2_C 1 10 DPA_DOCK_LANE2_C

B PS_MODE OUT4p DPA_DOCK_LANE3# C229 1 B
36 MODE OUT4n 13 2 0.1U_0402_10V7K~D DPA_DOCK_LANE3#_C
R323 1 2100K_0402_5%~D PS_I2C_CTL_EN# 26 DPA_DOCK_LANE2#_C 2 9 DPA_DOCK_LANE2#_C
2
DPA_DOCK_HPD I2C_CTL_EN#
30 HPD_SINK
25 7 DP_HPD1_SINK DPA_DOCK_LANE3_C 4 7 DPA_DOCK_LANE3_C
PS_PC0 OE# HPD
3 PC0
PS_PC1 4 5 DPA_DOCK_LANE3#_C 5 6 DPA_DOCK_LANE3#_C
PS_REXT PC1 GND
6 REXT GND 12
35 CFG0 GND 18 3
34 CFG1 GND 24
2 31 8
PS_CEXT CFG2 GND
10 CEXT GND 37
DPA_DOCK_CA_DET 27 43 RCLAMP0524P.TCT~D
DDCBUF1_EN# CA_DET GND
32 DDCBUF_EN#
1 NC VSS 49 D30 @
DPA_DOCK_AUX 1 10 DPA_DOCK_AUX
PS8121EQFN48G_QFN48_7X7~D
+3.3V_RUN_DPA DPA_DOCK_AUX# 2 9 DPA_DOCK_AUX#
DPA_DOCK_CA_DET 4 7 DPA_DOCK_CA_DET
1 2 DPA_LP
R200 100K_0402_5%~D DPA_DOCK_HPD 5 6 DPA_DOCK_HPD
1 2 DDCBUF1_EN# +3.3V_RUN_DPA +3.3V_RUN_DPA
R319 100K_0402_5%~D 3
+3.3V_RUN_DPA
4.7K_0402_5%~D
8
4.7K_0402_5%~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
R309 1 2 DPA_DOCK_AUX# 1 1
100K_0402_5%~D @ @ RCLAMP0524P.TCT~D
R318
R320
C200
C196
@ R310 1 2 DPA_DOCK_AUX
100K_0402_5%~D 2 2
140mA+3.3V_RUN_DPA 35mA Place close to JDP1 connector
A +3.3V_RUN R203 +5V_RUN R204 +5V_RUN_DPA @ R311 1 2 DPA_DOCK_AUX# PS_PC0 A
0_0603_5%~D 0_0603_5%~D 100K_0402_5%~D PS_PC1
1 2 1 2
R312 1 2 DPA_DOCK_AUX
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
100K_0402_5%~D
1 1 1 1 1 1
Close JDP1
C168
C169
C170
C171
C172
C173
2 2 2 2 2 2 Compal Electronics, Inc.

Close U15 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Port A DP/DVI
Close U15 LA-3954P
5 4 3 2 1
5 4 3 2 1
U16 +3.3V_RUN_DPB
+3.3V_RUN_DPB R250 1 2 0_0402_5%~D 14 56 DPB_DOCK_RP1_LANE0
VCC DP_SINK0(p)
SDM10U45-7_SOD523-2~D
R251 1 2 0_0402_5%~D 17 55 DPB_DOCK_RP1_LANE0#
R252 VCC DP_SINK0(n) +3.3V_RUN_DPB
1 2 0_0402_5%~D 23 VCC
0_1206_5%~D
53 DPB_DOCK_RP1_LANE1
DP_SINK1(p)
2
+5V_RUN_DPB 2 52 DPB_DOCK_RP1_LANE1# R313 1 2 DPB_DOCK_AUX#
VDD DP_SINK1(n) 100K_0402_5%~D @
8 VDD
D9
R245
34 50 DPB_DOCK_RP1_LANE2
VDD DP_SINK2(p) DPB_DOCK_RP1_LANE2# @R314
@ R314 1
48 49 2 DPB_DOCK_AUX
1
VDD DP_SINK2(n) 100K_0402_5%~D
54
1
VDD DPB_DOCK_RP1_LANE3
+3.3V_RUN_BR
47
+3.3V_RUN_DPB 38 VDD*1
DP_SINK3(p)
DP_SINK3(n) 46 DPB_DOCK_RP1_LANE3#
DPB_DOCK_AUX
@R315
@ R315 1 2 DPB_DOCK_AUX#
100K_0402_5%~D Display port Connector
AUX_SINK(p) 45
D DPB_DOCK_AUX# D
AUX_SINK(n) 43 R316 1 2 DPB_DOCK_AUX
100K_0402_5%~D +DPB_VCC
3A_6VDC_2920SMD300
DP_B_L0+ 3 40 DP_HPD2_SINK
<5> DP_B_L0+ ML_IN0 (p) DP_HPD_SINK
DP_B_L0- 4 41 DPB_DOCK_CA_DET
<5> DP_B_L0- ML_IN0 (n) CAD_SINK Close JDP2
10U_0805_10V4Z~D
0.01U_0402_16V7K~D
32 DPB_DVI_DETECT
TMDS_HPD_SINK
0_1206_5%~D
DP_B_L1+ 6
<5> DP_B_L1+ ML_IN1(p)
@
DP_B_L1- 7 19 DPB_DVI_LANE0 1 1
<5> DP_B_L1- ML_IN1(n) TMDS_SINK0(p) DPB_DVI_LANE0 <13>
F3
R124
C117
C133
18 DPB_DVI_LANE0#
TMDS_SINK0(n) DPB_DVI_LANE0# <13>
DP_B_L2+ 9
100K_0402_5%~D
DP_B_L2- 10 22 DPB_DVI_LANE1
<5> DP_B_L2- DPB_DVI_LANE1 <13>
1
ML_IN2(n) TMDS_SINK1(p)
1
DPB_DVI_LANE1# 2 2
TMDS_SINK1(n) 21 DPB_DVI_LANE1# <13>
DP_B_L3+ 12 @
R279
DP_B_L3- 13 25 DPB_DVI_LANE2
<5> DP_B_L3- ML_IN3(n) TMDS_SINK2(p) DPB_DVI_LANE2 <13>
24 DPB_DVI_LANE2#
TMDS_SINK2(n) DPB_DVI_LANE2# <13>
2
DP_B_AUX+ 36 16 DPB_DVI_CLK
<5> DP_B_AUX+ AUX(p)_I2C_SCL TMDS_SINK_CLK(p) DPB_DVI_CLK <13>
DP_B_AUX- 35 15 DPB_DVI_CLK# JDP2
<5> DP_B_AUX- AUX(n)_I2C_SDA TMDS_SINK_CLK(n) DPB_DVI_CLK# <13>
L30 20 DP_PWR
29 DPB_DVI_SCLK 19
I2C_SCL DPB_DVI_SCLK <13>
+3.3V_RUN_DPB 0_0402_5%~D RTN
DP_B_HP 37 28 DPB_DVI_SDAT DPB_DOCK_HPD 1 2 DPB_DOCK_HPD_1 18
HPD I2C_SDA DPB_DVI_SDAT <13> HP_DET
DP_B_CA_DET1 39 DPB_DOCK_AUX# 17
CAD AUX_CH-
16 GND
DPB_DOCK_AUX 15
DPB_PRI R329 4.7K_0402_5%~D PS1_I2C_CTL_EN# AUX_CH+
<6> DPB_PRI 33 Priority 14 GND
DPB_LP 30 5 DPB_DOCK_CA_DET 13
<6> DPB_LP LP GND CA_DET
5.1M_0402_5%~D
11 R226 4.7K_0402_5%~D PS1_MODE DPB_DOCK_LANE3#_C 12
GND LAN3-
1M_0402_5%~D
26 VSadj GND 20 11 LAN3_shield GND 21
1 27 DPB_DOCK_LANE3_C 10 22
DPVadj GND LAN3+ GND
100K_0402_5%~D
R233
R126
4.7K_0402_1%~D
3.48K_0402_1%~D
31 DPB_DOCK_LANE2#_C 9 23
GND LAN2- GND
1
GND 42 8 LAN2_shield GND 24

R208
44 DPB_DOCK_LANE2_C 7
1
GND LAN2+
R205
R207
57 51 R331 500_0402_1% PS1_REXT DPB_DOCK_LANE1#_C 6

C Thermal GND LAN1- C
5 LAN1_shield
SN75DP122_QFN56~D C276 2.2U_0603_10V6K~D PS1_CEXT DPB_DOCK_LANE1_C 4
2
DPB_DOCK_LANE0#_C LAN1+
3 LAN0-
2 LAN0_shield
DPB_DOCK_LANE0_C 1 LAN0+
MOLEX_47272-0026
U47 +3.3V_RUN_DPB
DPB_DOCK_RP1_LANE0 C286 1 2 0.1U_0402_10V7K~D DPB_DOCK_RP_LANE0 38
DPB_DOCK_RP1_LANE0# C282 1 IN1p
2 0.1U_0402_10V7K~D DPB_DOCK_RP_LANE0# 39 IN1n VCC 46
VCC 40
DPB_DOCK_RP1_LANE1 C287 1 2 0.1U_0402_10V7K~D DPB_DOCK_RP_LANE1 41 33
+3.3V_RUN_DPB DPB_DOCK_RP1_LANE1# C284 1 IN2p VCC
2 0.1U_0402_10V7K~D DPB_DOCK_RP_LANE1# 42 IN2n VCC 21 D31 @
VCC 15
DPB_DOCK_RP1_LANE2 C283 1 2 0.1U_0402_10V7K~D DPB_DOCK_RP_LANE2 44 11 DPB_DOCK_LANE0_C 1 10 DPB_DOCK_LANE0_C
DPB_LP DPB_DOCK_RP1_LANE2# C288 1 IN3p VCC
1 2 2 0.1U_0402_10V7K~D DPB_DOCK_RP_LANE2# 45 IN3n
R206 100K_0402_5%~D 23 DPB_DOCK_LANE0 C230 1 2 0.1U_0402_10V7K~D DPB_DOCK_LANE0_C DPB_DOCK_LANE0#_C 2 9 DPB_DOCK_LANE0#_C
DDCBUF2_EN# DPB_DOCK_RP1_LANE3 C289 1 OUT1p
1 2 2 0.1U_0402_10V7K~D DPB_DOCK_RP_LANE3 47
IN4p OUT1n 22 DPB_DOCK_LANE0# C231 1 2 0.1U_0402_10V7K~D DPB_DOCK_LANE0#_C
R321 100K_0402_5%~D DPB_DOCK_RP1_LANE3# C285 1 2 0.1U_0402_10V7K~D DPB_DOCK_RP_LANE3# 48 DPB_DOCK_LANE1_C 4 7 DPB_DOCK_LANE1_C
IN4n DPB_DOCK_LANE1 C232 1
OUT2p 20 2 0.1U_0402_10V7K~D DPB_DOCK_LANE1_C
DPB_DOCK_AUX C292 1 2 0.1U_0402_10V7K~D DPB_DOCK_RP_AUX 8 19 DPB_DOCK_LANE1# C233 1 2 0.1U_0402_10V7K~D DPB_DOCK_LANE1#_C DPB_DOCK_LANE1#_C 5 6 DPB_DOCK_LANE1#_C
DPB_DOCK_AUX# SCL/AUX+ OUT2n
C293 1 2 0.1U_0402_10V7K~D DPB_DOCK_RP_AUX# 9 SDA/AUX-
DPB_DVI_DETECT 17 DPB_DOCK_LANE2 C234 1 2 0.1U_0402_10V7K~D DPB_DOCK_LANE2_C 3
DPB_DVI_DETECT <13> +3.3V_RUN_DPB OUT3p
29 16 DPB_DOCK_LANE2# C235 1 2 0.1U_0402_10V7K~D DPB_DOCK_LANE2#_C
SCLZ OUT3n
100K_0402_5%~D
28 8
SDAZ
1
R324 1 2100K_0402_5%~D 14 DPB_DOCK_LANE3 C236 1 2 0.1U_0402_10V7K~D DPB_DOCK_LANE3_C

PS1_MODE OUT4p DPB_DOCK_LANE3# C237 1 DPB_DOCK_LANE3#_C
36 MODE OUT4n 13 2 0.1U_0402_10V7K~D RCLAMP0524P.TCT~D
R281
R325 1 2100K_0402_5%~D PS1_I2C_CTL_EN# 26

DPB_DOCK_HPD I2C_CTL_EN#
30 HPD_SINK D32 @
25 7 DP_HPD2_SINK
2
B PS1_PC0 OE# HPD DPB_DOCK_LANE2_C B

3 PC0 1 10 DPB_DOCK_LANE2_C
PS1_PC1 4 5
PS1_REXT PC1 GND DPB_DOCK_LANE2#_C 2 DPB_DOCK_LANE2#_C
6 REXT GND 12 9
35 CFG0 GND 18
34 24 DPB_DOCK_LANE3_C 4 7 DPB_DOCK_LANE3_C
CFG1 GND
2 CFG2 GND 31
0.033U_0402_16V7K~D
DP_B_HP PS1_CEXT 10 37 DPB_DOCK_LANE3#_C 5 6 DPB_DOCK_LANE3#_C

<5> DP_B_HP CEXT GND
100K_0402_5%~D
DPB_DOCK_CA_DET 27 43
CA_DET GND
1
@ 1 DDCBUF2_EN# 32 3
@ +3.3V_RUN_DPB DDCBUF_EN#
1 NC VSS 49
+3.3V_RUN_DPB
R280
C183
8
4.7K_0402_5%~D
4.7K_0402_5%~D
2 PS8121EQFN48G_QFN48_7X7~D RCLAMP0524P.TCT~D
2
@ @
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 1 D33 @
R330
R334
DPB_DOCK_AUX 1 10 DPB_DOCK_AUX
C214
C201
2 2 PS1_PC0 DPB_DOCK_AUX# DPB_DOCK_AUX#

2 9
PS1_PC1 DP_B_CA_DET1
<5> DP_B_CA_DET1
100K_0402_5%~D
DPB_DOCK_CA_DET 4 7 DPB_DOCK_CA_DET
1
@
DPB_DOCK_HPD 5 6 DPB_DOCK_HPD
R282
3
2
RCLAMP0524P.TCT~D
A 140mA Place close to JDP2 connector A

+3.3V_RUN R209 +3.3V_RUN_DPB
+5V_RUN
35mA +5V_RUN_DPB
0_0603_5%~D R210
1 2 0_0603_5%~D
1 2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 1 1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 1 1
C174
C175
C176
2 2 2
C177
C178
C179
2 2 2 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Port B DP/DVI
Close U16 Close U16 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Size Document Number Rev
X03
LA-3954P
5 4 3 2 1
5 4 3 2 1
D D
+3.3V_RUN
+3.3V_RUN +3.3V_AVDD +3.3V_DCVDD +3.3V_RUN

3
2
D11 D12 D13 D15 L21 L25
@
@
DA204U_SOT323-3~D
DA204U_SOT323-3~D
DA204U_SOT323-3~D
DA204U_SOT323-3~D
+3.3V_RUN BLM21PG331SN1D_2P~D BLM18EG601SN1D_2P~D
1 2 1 2
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
4.7U_0805_10V4Z~D
14
U38A 2 2
1
1
We will create this part. 1 2 2
P
R71
C127
C132
DAI_BCLK 1 2 I2S_BCLK_1 1 2 I2S_BCLK 2008.3.10 Modify.
<5> DAI_BCLK I O
C126
C129
C130
33_0402_5%~D
G
1 1
SN74LVC14APWR_TSSOP14 2 1 1
7
U17
SSM2603
+3.3V_RUN 3 4
DCVDD DGND
18 AVDD AGND 19
14
12 HPVDD PGND 15
U38B 5 DBVDD
P
DAI_LRCK 3 4 I2S_LRCLK 24 16
<5> DAI_LRCK I O LLINEIN LOUT
ROUT 17
G
23 RLINEIN
SN74LVC14APWR_TSSOP14 +3.3V_RUN
7
C C212
<16> FX3_SMB_CLK
FX3_SMB_CLK 28 SCLK LHPOUT 13 AUD_DOCK_HP_OUT_L AUD_DOCK_HP_OUT_L <16> C
2 1 FX3_SMB_DAT 27 14 AUD_DOCK_HP_OUT_R AUD_DOCK_HP_OUT_R <16>
<16> FX3_SMB_DAT SDIN RHPOUT
330P_0402_50V7K~D
330P_0402_50V7K~D
C199
14
R235
+3.3V_RUN U38F 0.1U_0402_16V4Z~D 1 2 1 2 I2S_12MHZ 1 6 1 1 D36
MCLK/XTI CLKOUT @ @ PMEG2020EJ_SC90-2~D
2
P
22_0402_5%~D XTO
C187
C186
10P_0402_50V8J~D I2S_BCLK
14
13 I O 12 BCLK 7 2 1 +3.3V_AVDD
10P_0402_50V8J~D 22_0402_5%~D
U38C DOCK_MICIN 22
<16> DOCK_MICIN MICIN
2
R246 MICBIAS I2S_DO 2 2 D35
21 8
P
<16> MICBIAS MICBIAS DACDAT
R234
DAI_DO 5 6 I2S_DO SN74LVC14APWR_TSSOP14 0_0402_5%~D 10 I2S_DI PMEG2020EJ_SC90-2~D
<5> DAI_DO
7
I O ADCDAT
<6> HP_SHTDN# 1 2 25 MUTEN 2 1 +3.3V_AVDD
G
9 I2S_LRCLK
SN74LVC14APWR_TSSOP14 DACLRC I2S_LRCLK
26 11
7
1
CSB ADCLRC
1
2
R133 @ 20 29
VMID Thermal Pad
C195
4.7U_0805_10V4Z~D
+3.3V_RUN 10K_0402_5%~D
1 SSM2603CPZ-REEL7_LFCSP28_5X5~D Modify by ADI 2008.03.15
1
1
14
C131
U38D R174
10K_0402_5%~D
P
R79 2
DAI_12MHZ 9 8 I2S_12MHZ_11 2 I2S_12MHZ
<5> DAI_12MHZ I O
33_0402_5%~D
2
G
+3.3V_RUN
SN74LVC14APWR_TSSOP14 +3.3V_RUN
7
D8 @
1 GND VCC 4
3
DA204U_SOT323-3~D
+3.3V_RUN
@
2 IO1 IO2 3
D14
14
U38E PRTR5V0U2X_SOT143-4~D
P
I2S_DI 11 10
B I O DAI_DI <5> B
G
SN74LVC14APWR_TSSOP14
7
DAI_12MHZ
DAI_DO
DAI_LRCK
DAI_BCLK 100K_0402_5%~D
100K_0402_5%~D
100K_0402_5%~D
100K_0402_5%~D
1
1
R217
R218
R219
R220
2
A A
Title
Audio DAC
X03
5 4 3 2 1
5 4 3 2 1
D D
JAUD1
R255 68_0402_5%~D C135 100U_D_6.3VM_R15M~D 7
AUD_DOCK_HP_OUT_L HP_SPK_L2 HP_SPK_L1 5
+
<15> AUD_DOCK_HP_OUT_L 1 2 1 2 1 24
R256 68_0402_5%~D C140 100U_D_6.3VM_R15M~D
AUD_DOCK_HP_OUT_R HP_SPK_R2 HP_SPK_R1
+
<15> AUD_DOCK_HP_OUT_R 1 2 1 2 4 21
22K_0402_5%~D
22K_0402_5%~D
2 2P
1
R224
HP_DET 3
<6> HP_DET 2Q
R223
2008.3.15 Modify. A
2
14
2
MIC_2 5 11
8 1P
MIC_DET 6
<6> MIC_DET 1Q
B
Close to U17 Part 10 SHLD1
11 SHLD2
12 SHLD3
13 SHLD4
TYCO_6-1775390-6
<15> MICBIAS
1
C R140 C
200_0402_5%~D
+3.3V_RUN
C88
2
2 1
1
2008.3.15 Modify.
10U_0805_10V4Z~D R135
1
100K_0402_5%~D
R136
2K_0402_5%~D
2
HP_DET
2
C143 +3.3V_RUN
R139
200_0402_5%~D 2.2U_0603_6.3V6K~D
DOCK_MICIN 1 2 MIC_1 1 2 MIC_2
<15> DOCK_MICIN
1
1000P_0402_50V7K~D
R138
100K_0402_5%~D
2
C145
MIC_DET
1
B B
+3.3V_RUN
2.2K_0402_5%~D
2.2K_0402_5%~D
1
1
R147
R148
2
DOCK_SMB_DAT FX3_SMB_DAT
D
<5,6,8> DOCK_SMB_DAT 1 3 FX3_SMB_DAT <15>

Q23
2N7002W-7-F_SOT323-3~D
G
2
Q24
DOCK_SMB_CLK 3 2N7002W-7-F_SOT323-3~D FX3_SMB_CLK
D
<5,6,8> DOCK_SMB_CLK 1 FX3_SMB_CLK <15>
R214
G
2
0_0402_5%~D
+3.3V_RUN 1 2
A A
Title
Audio (HeadPhone Jack and MIC)
X03
5 4 3 2 1
5 4 3 2 1
+5V_ALW +5V_RUN
Q11 +5V_RUN Source
SI4800BDY-T1-E3_SO8~D +5V_RUN +3.3V_RUN
8 1
Design current: 200mA
D S
7 D S 2 Max current: 200mA
1
10U_0805_10V4Z~D
+3.3V_ALW2 +15V_ALW 6 3
D S
1
20K_0402_5%~D
5 1 R168 R169
D
G
1K_0402_5%~D 1K_0402_5%~D
C162
R170
@ @
4
R171
2
2
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
100K_0402_5%~D
2
1
D D
1
R172 D D
2
100K_0402_5%~D RUN_ENABLE RUN_ON_5V# 2 2
@ Q12
@ Q13
G G
1
D
2N7002W-7-F_SOT323-3~D
S S
3
RUN_ON_5V# 2
4700P_0402_25V7K~D
G
S 1
3
1
D
Q14
C163
+3.3V_ALW Q16 +3.3V_RUN
<6,7> DK_RUNON 2
G SI4800BDY-T1-E3_SO8~D
Q15 S 2
8 1
3
2N7002W-7-F_SOT323-3~D D S
7 D S 2
10U_0805_10V4Z~D
6 D S 3
1
20K_0402_5%~D
5 D
G
1
R173
4
C164
+3.3V_SUS
+3.3V_RUN Source
2
2
1
R194
Max current: 300mA 1K_0402_5%~D
@
2N7002W-7-F_SOT323-3~D
RUN_ENABLE
1
D
SUS_ON_5V# 2
@ Q18
G
S
3
+3.3V_ALW +3.3V_SUS
C Q22 C
SI4800BDY-T1-E3_SO8~D
8 D S 1
10U_0805_10V4Z~D
+3.3V_ALW2 +15V_ALW 7 2
D S
1
20K_0402_5%~D
6 3
5
D
D
S
1
+3.3V_SUS Source
1
R198
C167
R196
4
100K_0402_5%~D
Max current: 300mA
2
1
2
R197
2
100K_0402_5%~D SUS_ENABLE
1
D
2N7002W-7-F_SOT323-3~D
2
SUS_ON_5V# 2
4700P_0402_25V7K~D
G
S 1
3
1
D
Q20
C166
<6> DK_SUSON 2
G
Q21 2
S
SCREW HOLE
3
2N7002W-7-F_SOT323-3~D
CLIP3 CLIP2 CLIP1 H1 H2 H3 H5 H6 H7

CLIP_4P9X2P4 CLIP_4X2P4 EMI-79x138 @ 3P0 @ 3P0 @ 3P0 @ 3P0 @ 3P0 @ 3P0
Q26
+3.3V_ALW SI3456BDV-T1-E3_TSOP6~D +3.3V_LAN
1
D
6
S
5 4
4.7U_0805_10V4Z~D
0.1U_0402_16V4Z~D CLIP5 CLIP4

2
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
B CLIP_6P2X2P9 CLIP_6P2X2P9 B
2 2 1
1 2
G
C247
H11 H8 H9 H10 H14 H16

C246
C249
C250
@ H_1P3X3P3N @ 3P0 @ 3P0 @ 3P0 @ 3P8 @ 5P1N
1
1 1
2 1
+DOCK_PWR_BAR +DOCK_PWR_BAR
1
CLIP6
CLIP_4P9X2P4
1
ENAB_3VLAN
R283
1
100K_0402_5%~D
1
R284
100K_0402_5%~D
2
ENAB_3VLAN
2
D
2N7002W-7-F_SOT323-3~D
1
2 R285
1
200K_0402_5%~D
Q27
G C248 470K_0402_5%~D
FIDUCIAL MARK
1
D 4700P_0402_25V7K~D +DOCK_PWR_BAR
S
3
2
R286
<6> AUX_ON 2
2
G FD1 FD2 FD3 FD4

Q28 S 1 1 1 1
3
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2N7002W-7-F_SOT323-3~D
1 1 1 1 1 1 FIDUCAL FIDUCAL FIDUCAL FIDUCAL
C70
C80
C82
C85
C86
C87
FD5 FD6
2 2 2 2 2 2
1 1
FIDUCAL FIDUCAL
A A
Title
EE Power
X03
5 4 3 2 1
5 4 3 2 1
This Capacitor should be

used only as last resort
for EMI suppression. Dock DC_IN
Capacitance should be as PD10
DOCK_PSID
small as possible. B540C~D
2 1
+DOCK_DC_IN_SS
PL5 PQ1 P_FDS6681Z_SO8~D PQ2 P_FDS6681Z_SO8~D
FBMJ4516HS720NT 1806~D +DOCK_SDC_IN
PJPDC1 +DOCK_DC_IN PR1 +DOCK_PWR_BAR
0.1U_0603_25V7K~D
1 2
PL1 0.01_2512_1%~D
10U_1206_25V6M~D
DETECT 5 1 1
FBMJ4516HS720NT 1806~D
0.01U_0603_25V7K~D
0.1U_0603_50V4Z~D
0.1U_0603_50V4Z~D
9 GND_4 2 2
4.7K_0805_5%~D
DC+_1 1 1 2 3 5 5 3 1 4
1
@ PC2
PC3
PC4
PC1
PC5
240K_0402_5%~D
D
8 GND_3 D
PR2
PR3
2 PL2 2 3
DC+_2 FBMJ4516HS720NT 1806~D
2
7 GND_2 DC-_1 3 1 2
1M_0402_5%~D
PL6
4.99K_0402_1%~D
0.022U_0805_50V7K~D
2
1
2
2
6 4 FBMJ4516HS720NT 1806~D
GND_1 DC-_2
PC6
PR4
PR5
1 2
IMD2AT-108_SC74-6~D
1
VZ0603M260APT_0603
VZ0603M260APT_0603
PQ4
FOX_JPD113D-DB570-7F NTR4502PT1G_SOT23-3~D
1
PQ3B
2
PD1
PD2
3
1 1 1 3 DOCK_DCIN_IS- <5>
PR46
1
@ @ 100K_0402_5%~D
2
2
4
10K_0402_1%~D
@ PD12 PQ5
2
+DOCK_DC_IN RB751V_SOD323~D 2 2 NTR4502PT1G_SOT23-3~D
IMD2AT-108_SC74-6~D
1
PR8
2
1M_0402_5%~D
22K_0402_1%~D
3
2 1 1 2 2 1 1 3 DOCK_DCIN_IS+ <5>
1
PR68
1
PR6
PR7
@ PR59 0_0402_5%~D PR56
PQ3A
1
200K_0402_5%~D PR64 @ 5 100K_0402_5%~D
2
2
6
1K_0402_5%~D
1
@ PR62 @ PQ19A
2
@ PR60 200K_0402_5%~D 2N7002DW-T/R7_SOT363-6~D
2
200K_0402_5%~D 2 1 2
2
2
0_0402_5%~D
10U_1206_25V6M~D
10U_1206_25V6M~D
1
100K_0402_5%~D
ACAV_DOCK_SRC# <5>
2
1
3
PR55
PR57
IMD2AT-108_SC74-6~D
1
PC44
PC45
PR63
100K_0402_5%~D
2
1
2 1 5 @ @ PR54 +DOCK_DC_IN
2
1
<5> NB_DET# PQ19B @ @ @ D
0.047U_0603_16V4Z~D
PQ6A
2
@ PR61 RHU002N06_SOT323
0.1U_0603_50V4Z~D
5 2 1 2 2 1
4
1
@ PR65 0_0402_5%~D <5> DOCK_AC_OFF G PQ7
1
D
PC43
40.2K_0402_1%~D 2N7002DW-T/R7_SOT363-6~D PR9
12.1K_0402_1%~D
S
3
0_0402_5%~D RHU002N06_SOT323
1
+DOCK_DC_IN_SS
PC7
100K_0402_1%~D 2
2
PQ18
PR10
240K_0402_5%~D
C G C
2
@ S
2
3
PR11
1
2
1
D
16.5K_0402_1%~D 100K_0402_1%~D
PR69
3
1
IMD2AT-108_SC74-6~D
2 0_0402_5%~D
1
PR12
1. Populated PR68 PQ8
G @
1 2 S
2
2. Reserve delay circuir, no stuff.
PQ6B
2 RHU002N06_SOT323
30K_0402_1%~D
PD3 @ PR67
1
D
LM431SBCMF_SOT23-3
RB751V_SOD323~D 1 2
RHU002N06_SOT323 DOCK_DET_1 <5>
PU1
PR13
RHU002N06_SOT323
3 2 1 2
G PQ9 0_0402_5%~D
1
D PR14 S
4
3
PQ10
PR15
2 43K_0402_5%
1
G
1
D PR66
S
3
2 0_0402_5%~D
10K_0402_1%~D
G
0.047U_0402_16V5K~D
1
56K_0402_5%~N
PQ11 S
2
1
2
PC8
PR16
PR17
NTS4001NT1G_SC70-3
2
2
1
Dock PS_ID Detector PD11
+DOCK_DC_IN_SS 2 1 +NBDOCK_DC_IN_SS <5> +DOCK_DC_IN 5V_3V_REF
B B
PR142 +3.3V_ALW
+5V_ALW 1M_0402_1%~D
+3.3V_ALW RB751V-40_SOD323~D
32.4K_0402_1%~D
1 2
232K_0402_1%~D
PR58
1
100K_0402_5%~D
DA204U_SOT323~D
PR143
PR144
+5V_ALW
2
4
PD4
PR18 PU11A
2.2K_0402_5%~D
8
@ 0_0402_5%~D 2 LM393DR_SO8~D PR145
2
IN-
PR19
1 2 1 5 0_0402_5%~D
P
O IN+
100P_0402_50V8J
3 7 1 2 ACAV_IN_DOCK <6>
1
IN+ O
21.5K_0402_1%~D
6
1
IN-
G
100P_0402_50V8J
PU11B
1
PC41
100K_0402_1%~D
LM393DR_SO8~D
4
2
PR146
PR20
1
PC42
PR147
PQ12 33_0402_5%~D
2
DOCK_PSID 3 FDV301N_NL_SOT23-3~D DOCK_PS_ID
D
1 1 2 DOCK_PS_ID <5>
2
+5V_ALW
1
+5V_ALW +5V_ALW
G
2
100K_0402_1%~D
2V* 100K/ (100K+32.4K)=1.51V

2
PR21
10K_0402_1%~D
DA204U_SOT323~D
17.8V*21.5K/(232K+21.5K)= 1.51V
1
2
SM24_SOT23
PR22
PD6
1
PD5
PR23
@ @ 100_0402_5%~D
1
1 2
PS_ID_DISABLE# <6>
1
2 C PQ13
A B PMBT3904_SOT23~D A
E
15K_0402_1%~D
3
2
PR24
Title
Power DC-DC
X03
5 4 3 2 1
5 4 3 2 1
+3.3V_ALWP/ +5V_ALWP/ +5V_ALW2 / +15V_ALWP
Place these CAPs No Install for ISL6236 Place these CAPs

DC1_PWR_SRC
PJP1 close to FETs Install 10 ohm for MAX8778 close to FETs
1 2 +3P3V_+5V_PWR_SRC
+DOCK_PWR_BAR
PAD-OPEN 4x4m
+5V_ALW2 +5V_VCC1
D D
2200P_0402_50V7K~D
0.1U_0805_50V7K~D
2200P_0402_50V7K~D
2
0_0805_5%~D
0_0805_5%~D
PR27
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
0.1U_0805_50V7K~D
1
1 1 1 1 10_0603_5%~D
1
@ PC10
PC11
PC12
PR25
PR26
PC15
PC16
@ PC9
4.7U_0805_10V6K~D
2 1
PC13
PC14
2
2
1
2 2 2 2
PC17
+3.3V_ALW2
0_0402_5%~D
0_0402_5%~D
2
1
PR28
PR29
PR30
1U_0603_10V6K~D
+3.3V_ALW2 @ 0_0402_5%~D
2
1
PC18
1 2 @
0.1U_0603_25V7K~D
@ PR31
3.3K_1206_5%~D 0.1U_0603_25V7K~D
2
2
0_0402_5%~D
0_0402_5%~D
1
PC19
3.3K_1206_5%~D 0.1U_0603_25V7K~D
1 2
EN_3V_5V
1
PC21
PR32
@ PC38
PC20
1
1U_0402_6.3V6K~D 0.1U_0402_10V7K~D
1
1
@ PC37
2
Use 0.1uF for ISL6236. 1 2 GNDA_3V5V
2
Use 1uF for MAX8778. @
5 Volt +/-5% 2
Design current: 4.7A 3.3 Volt +/-5%
1
8 GNDA_3V5V
7
6
5
@ PR51
Max current:6.7A GNDA_3V5V +3.3V_ALWP_REFIN2
Design current: 0.4A
1
8
7
6
5
4
3
2
1
PQ14 PU2 5V_3V_REF
D
D
D
OCP_min= 7.14A D
FDS8880_NL_SO8~D
@ PR50
@ PC22 Max current: 0.57A
LDO
ONLDO
REF
LDOREFIN
IN
RTC
VCC
TON
0.1U_0402_10V7K~D
2
4
POK1
2 1 PR33
OCP_min= 2.2A
GNDA_3V5V
2
G 51K_0402_1%~D PQ15
9 BYP REFIN2 32
6
+5V_ALWP 10 31 1
<BOM 2
Structure>
OUT1 ILIM2
S
S
S
11 30
D1
D1
FB1 OUT2
C GNDA_3V5V 1 PR34 2 12 29 1 PR35 2 +3.3V_ALWP C
1
2
3
110K_0402_1%~D ILIM1 SKIP# 0_0402_5%~D POK2

13 PGOOD1 PGOOD2 28 4 G1
PL4 EN_3V_5V 14 27 EN_3V_5V 3 PL3
3.3UH_SIL1045R-3R3PF_8.2A_30% +5V_ALW_UGATE ON1 ON2 +3.3V_ALW_UGATE S1 8.2UH_FDV0630-8R2M=P3 3.7A_20%
15 DH1 DH2 26
1 2 +5V_ALW_PHASE 16 25 +3.3V_ALW_PHASE 7 2 1
LX1 LX2 D2
MAX8778ETJ+_TQFN32_5X5~D
8
7
6
5
4.7_1206_5%
4.7_1206_5%~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
8
SECFB
D2
1
AGND
PGND
0_0603_1%
0_0603_1%~D
PQ16 GNDA_3V5V
BST1
BST2
2
S2
VDD
PAD
G2
1
1
DL1
DL2
FDS6676AS_NL_SO8~D
680p_0603_50VNPO~D PR52
PR53
330U_D3L_6.3VM_R25~D
330U_D3L_6.3VM_R25~D
330U_D3L_6.3VM_R25~D
1
1
@ PR36
PC23
PR37
2200P_0402_50V7K~D
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
1
1
PC27
1 1 FDS6982AS_NL_SO8~D 1
33
17
18
19
20
21
22
23
24
680p_0603_50VNPO~D
4
2
1
1
+ + +
PC24
@ PC25
PC26
PC28
PC29
GNDA_3V5V
2
2
PC36
PC35
1 2
1
PC40
PR38 PR39
2
2
2 2 2
PC39
0_0603_1%~D
1_0603_5%~D 1_0603_5%~D
1
2
3
1
0_0603_1%~D
1 2 +5V_ALW_BOOT +3.3V_ALW_BOOT1 2
2
1
@ PR41
2
PR40
+5V_ALW_LGATE +3.3V_ALW_LGATE
2
2
0.1U_0603_25V7K~D
PC30
GNDA_3V5V
+5V_ALW2
+5V_ALWP 2 0.1U_0603_25V7K~D GNDA_3V5V
1 1 2
@ PC31
GNDA_3V5V 3 PJP2
0.1U_0603_25V7K~D
2 1
PD7
2
BAT54SW-7-F_SOT323~D PAD-OPEN 2x2m~D
1
PC33
PC32
GNDA_3V5V The p-p inductor ripple current/2=0.46A

2 0.1U_0603_25V7K~D GNDA_3V5V
VILIM1/10= 5uA*51K=25.5mV
2
1 1 2
3 consider 20% tolerance,25.5mV*80%=20.4mV 25.5mV*120%=30.6mV
PD13 OCP(min)=25.5mV/(16mOHM (Rds(on, typ)*1.3)+0.46A=1.68A
2 1 PD8 PD9 1 +3.3V_ALWP
<5> DOCK_POR_RST# +3.3V_ALWP OCP(max)=30.6mV/(16mOHM*1.3)+0.46A=1.93A
10K_0402_1%~D
BAT54SW-7-F_SOT323~D
2
B B
The p-p inductor ripple current/2=1.4A
0.1U_0603_25V7K~D
1
PR45
PC46
100K_0402_5%~D
100K_0402_5%~D
RB751V_SOD323~D
VILIM1/10= 5uA*110K=55mV
2
consider 20% tolerance,55mV*80%=44mV 55mV*120%=66mV
2
PR43
@ PR44
OCP(min)=44mV/(5.9mOHM (Rds(on, typ)*1.3)+1.4A=7.14A
1
BAT54CW_SOT323-3~D
OCP(max)=66mV/(5.9mOHM*1.3)+1.4A=10A
1
POK2
2
0_0402_5%~D
PR47
PR48
1
200K_0402_1%~D
2 1 POK1
VTT_PWRGD <6>
+15V_ALWP
0.1U_0603_25V7K~D
2
1
PJP3 PR49
PC34
+15V_ALWP 2 1 39K_0402_1%~D
+15V_ALW
(100mA,20mils ,Via NO.=1)
2
PAD-OPEN1x1m
PJP4
+5V_ALWP 1 2 (5A,200mils ,Via NO.=10)
+5V_ALW
GNDA_3V5V
PAD-OPEN 4x4m
PJP5
+3.3V_ALWP 1 2 +3.3V_ALW (7.5A,300mils ,Via NO.=15)
A A
PAD-OPEN 4x4m
Title
Power 3V/5V
X03
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
14 5,9, ME 9/6 DELL Customer Request: 1.Change JP2 symbol from TYCO_48226-1211 to TYCO_48226-0611.
D
10,11 1.Change Y TO B(6pin) Connector for POWER BOARD. 2.Change JESATA symbol from TYCO_1759557-2 to TYCO_1909573-3. D
3.Change JUSB1 symbol from TYCO_5787617-4 to Foxconn_UB11123-M4-4F. 4layer X00
2.Change E-SATA+USB Connector.
3.Change TREBLE USB Connector. 4.Change JP3 symbol from TYCO_1840021-1 to SUYIN_020181MHBK4M508ZA.
4.Change RJ45+2USB Connector. 5.Change page from P09-USB Port x6 + E-SATA to P09-USB Port x3 and PS2x2.
6.Change page from P10-RJ45 and PS2x2 to P10-E-SATA+USB Port x1.
7.Add page P11-RJ45+USB Portx2.
Item 2
NO-POP the U20, U21, U22, U23, U24, U25, U26, U27,C147,C148,C149,
15 15 GG list 9/5 DELL No-pop the Link Detect Circuit in Audio Section: C150,C151,C152,R143,R144,R145,R146 parts 4layer X00
U20, U21, U22, U23, U24, U25, U26, U27
16 9,10,11 GG list 9/6 Item 3 1.JESATA use TPS2066 x1 and 150uF x1.
DELL USB Cost Reduction: 2.JUSB1 use TPS2066 x2 and 150uF x2. 4layer X00
No-pop ESD diodes 3.JP3 use TPS2066 x1 and 150uF x1.
Only use 4 TPS2066 switches 4.No-pop ESD Diodes.
Only use 4 150uF caps
C C
17 8 GG list 9/6 DELL Item 4 Pop 1Mohm resistors R68 and R77.
Pop 1Mohm resistors on USB crystal circuits 4layer X00
(R68 and R77)
18 8 GG list 9/6 DELL Item 5 NO_Pop the 47k resistors R215 and R216.
No-pop the 47K resistors (R215 and R216) on 4layer X00
USB hub reset lines since this signal is pulled
low by the LPC before 3V_SUS comes up.
Item 8
19 10 GG list 9/6 DELL Remove it.
Please remove DC blocking caps C242 and C243 at 4layer X00
U42.These caps are already present on Roush near
the docking connector. Please verify.
20 9,10,11 EE 9/6 COMPAL Remove FUSE (LF453) Parts. Remove it. 4layer X00
B 21 15 EE 9/11 COMPAL 1.Headphones and Microphone detect wrong. 1.Change HP_DET and MIC_DET to pulled up. 4layer X00 B
2.Audio input signal short ground. 2.Change JAUD1.9 from Ground to NC pin.
22 6 GG list 9/12 DELL Item10 Modify OK.Net:SIO_RESET# Add pull down R183 resistor.
Disconnect PCI_RST# from pin 26 on LPC. 4layer X00
We will use GPIO27 from the LPC to control
the reset of LPC bus. Name the net SIO_RESET#.
schematic (PS2)These pull up resistors are already present on NO_Pop the 10K resistors R105,R106,R107,R108. 4layer X00
23 9 review 9/12 Compal
Roush.
schematic OR and NOTGate Power add CAPS to GND 1.Add caps C203,C204,C211,C212 to GND. 4layer X00
24 5,10,15 review 9/17 Compal 2.Change caps packaged size to 0402.
schematic DOCK_LED_10#,DOCK_LED_100# R103,R104 change to 150 ohm.
25 11 review 9/12 Compal 4layer X00
Change current limit resistors
schematic JP3 connector by pass caps alyeady present NO_pop the 0.01U caps C209,C210.
26 11 review 9/12 Compal 4layer X00
SUYIN_020181MHBK4M508ZA
schematic Update DOCK_ID to X02 R43 change to No_pop;R52 change to pop.
A 27 6 review 9/12 Compal 4layer X00 A
Title
EE PIR-1
X03
5 4 3 2 1
5 4 3 2 1

Request
Item 11 No-pop the R243,R109 resistors;POP the D2 diode F4 fuse.
28 12 GG list 9/17 DELL 4layer X00
D Please populate the fuse and the diode and no-pop the D
0 ohm resistors at the VGA connector.

Item 12 No-pop the R244,R117 resistors;POP the D7 diode F2 fuse. 4layer X00
29 13 GG list 9/17 DELL Please populate the fuse and the diode and no-pop the
0 ohm resistors at the DP connector.
30 14 GG list 9/17 DELL Item 13 No-pop the R245,R124 resistors;POP the D9 diode F3 fuse.
4layer X00
Please populate the fuse and the diode and no-pop the
0 ohm resistors at the DP connector.
31 Item 15 No-pop the R282 resistor. 4layer X00
14 GG list 9/17 DELL
Please no-pop R282 since it is popped on
Roush/Maybach.
32 22 EE 9/17 COMPAL Add new EE PIR-3 page. Add Page22 EE PIR-3. 4layer X00
33 15 GG list 9/19 DELL Layout issue Item34 Add D8 ESD diode between AGND and GND at
Audio connector. 4layer X00
C Add no-pop ESD diode between AGND and GND at the C
audio connector for ESD purposes.
34 15 GG list 9/19 DELL Layout issue item 37 Add the C165,C183 0.1uF caps.
AUD_DOCK_HP_OUT - Traces change reference planes 4layer X00
between AGND and GND. They need to maintain the
same reference plane throughout their runs. The traces
also do not reference planes for 100 mils. If not, add and
populate 0.1uF capacitors where the traces cross the
moats. See attached picture hp_crossing the moat.jpg for
moat crossings and bypass locations, circled in red
33 13 GG list 9/20 DELL Item 17 No-pop the R278 resistor (CA_DET pull down).
4layer X00
Need to no pop R278 (CA_DET pull down). The system
side has(/is adding) a pull down for this net too.
For now no pop, but in the future - may remove.
B B
34 13,14 GG list 9/20 DELL Item 18 No-pop the R277,R280 resistors (HPD pull downs). 4layer X00
Need to no pop R277, R280 (HPD pull downs). The
system side has pull downs for these nets.
For now no pop, after testing remove.
35 8 GG list 9/20 DELL Item 19 No-pop the R72,R73 resistors. 4layer X00
We need to no-pop one pair of the pull-up resistors for the keep one pair of the pull-up resistor for the USB SMBus.
USB SMBus. There are two pairs of pull-ups on this bus.
36 6,8 EE 11/5 Benson Test Crystal EA fail.modify the circuit. Recommend circuit:
1.Change Y1 part from 24MHZ_20PF_1BX24000BK1A~D to 24MHZ_12PF_1BX24000CE1B~D.
2.Change C27 part from 18P_0402_50V8J~D to 15P_0402_50V8J~D.
3.Change C28 part from 18P_0402_50V8J~D to 12P_0402_50V8J~D. 4layer X01
4.Change C51,C63 part from 12P_0402_50V8J~D to 15P_0402_50V8J~D.
5.Change C50,C62 part from 12P_0402_50V8J~D to 18P_0402_50V8J~D.
37 13 EE 11/06 Benson DVI port A and port b on DVI board location wrong. Modify JP4 board to board connector port A,B location. 4layer X01
A A
Title
EE PIR-2
X03
5 4 3 2 1
5 4 3 2 1

Request
38 10 EE 11/07 Benson Test SATA EA fail.modify the circuit. Net: SATA_SBTX_C_DRX_P_1 and SATA_SBTX_C_DRX_N_1 point add series
connection R308 470ohm. 4layer X01
D D
39 5 DELL 11/07 Benson Modify E-DOCK PIN OUT Add JP1 pin41 pin net: +DOCK_DC_IN_SS.source by P18-PWR_Dock DC_IN/PS_ID. 4layer X01
40 15 COMPAL 11/08 Benson Audio SM2602 DVSS,AVSS,HPVSS noise. Change L28,L29,L30 part to 0 ohmresistors . 4layer X01
41 6 COMPAL 11/08 Benson Change DOCK ID to X03. No-pop the R51 resistor;Pop the R42 resistor. 4layer X01
42 6 GG list 11/09 Benson U39, U40 use a different schematic symbol for an OR gate Change U39,U40 symbol to SN74AHC1G32DCKR_SC70-5~D best on Roush. 4layer X01
then the U59 from Roush schematics. Compal needs to
standardize on one symbol for an OR gate.
What is being done to prevent the symbol issues seen
on Roush? This needs to be resolved before PT gerber.
43 6 SCH164847 11/12 Benson No-pop Duplicate Pull-up Resistors on APR Please no-pop the following resistors since they are pulled up on 4layer X01
the system side when docked:R7,R8,R9,R231.
44 6 SCH164844 11/12 Benson Fix DVI Pinout Issue on APR and DVI Daughter Card. There is a pin define error on the connector pinouts of both APR and DVI 4layer X01
daughtercard that is preventing DVI display.The pinout on JP4 (APR) and
C
JP1 (DVI board) need to change for proper DVI display on both channels. C
DVI Port A should be above Display Port A
DVI Port B should be above Display Port B.
45 5 SCH164880 11/13 Benson Passing 3V_ALW to Power Board we add Q6 at DOCKED_LED# net and Q7 at BREATH_PWR_LED# net. 4layer X01
46 6 COMPAL 11/13 Benson Change connector part. Change JP2 symbol from MOLEX_48226-0611 to MOLEX_48227-0611. 4layer X01
47 6 SCH164886 11/13 Benson Add Comparator Circuit for AC_AVIN_DOCK. Please add a comparator circuit, as outlined in separate email.The output of this comparator circuit 4layer X01
will be named ACAV_IN_DOCK and needs to be routed to a Dock EC GPIO.Use GPIO11 on the APR.
and Remove the R186 part.
48 5 COMPAL 11/13 Benson Follow the POWER PIR2 item 2. Change net "ACAV_IN_DOCK#" to "ACAV_DOCK_SRC#" 4layer X01
49 17 COMPAL 11/13 Benson Add EMI CLIP. ADD CLIP2~CLIP6 Part.
4layer X01
1.Please reserve R71,R79 0 ohm at Dock connector side and AC termination at the End for
50 15 COMPAL 11/14 Benson Audio EMI test fail.
I2S_BCLK and I2S_12MHz. 4layer X01
2. I2S_BCLK parallel R234 22 ohm and C195 10P to GND.
B B
2. I2S_12MHZ parallel R235 22 ohm and C199 10P to GND.
51 16 COMPAL 11/15 Bill MIC bias resistor needs to change from 4.99 ohm to Change R139 from 4.99ohm to 40.2Kohm. 4layer X01
40Kohm at R139.
52 13,14 COMPAL 11/15 Bill Change F2, F3 to 3A_6VDC_2920SMD300 Change F2, F3 to 3A_6VDC_2920SMD300 4layer X01
53 6,8,16 COMPAL 11/19 Benson Have found that high Resistance values at the gate of the Change the R65,R66,R214 from 10K to 0ohm 4layer X01
SMBus isolation FETs may affect the Vgs turn-on volatge,
causing the SMBus to disconnect unexpectedly because
the isolation FETs are not turning on.
54 13, 14 COMPAL 12/13 Jake Lee Customer Request:

4layer X02
1.Change resistor for SN75DP122_QFN56~D. 1. Change part R202 from 5.11Kto 3.48K.
2.Change resistor for SN75DP122_QFN56~D. 2. Change part R208 from 5.11Kto 3.48K.
A A
Title
EE PIR-3
X03
5 4 3 2 1
5 4 3 2 1

Request
55 13, 14, COMPAL 12/13 Jake Lee Customer Request:
D
15 1.Change FUSE part 1. Change part F2 from 3A_6VDC to 1.1A_6V. 4layer X02 D
2.Change SSM2603CPZ 2. Change part F3 from 3A_6VDC to 1.1A_6V.

3. Change part U17 from SSM2603 to SSM2603.
56 5 COMPAL 12/19 Jake Lee Customer Request: 4layer X02

1. Change resistor for TYCO_1840015-1. 1. Change part JP3 from SUYIN_020181MHBK4M508ZA to TYCO_1840015-1.
57 16 COMPAL 12/27 Jake Lee Headphone channels of right and left are exchanging. Exchange nets of between the AUD_COCK_HP_OUT_R and the AUD_DOCK_HP_OUT_L. 4layer X02
58 5 COMPAL 12/27 Jake Lee The DOCK_POR_RST# signal will now be used to control Add new net of DOCK_POR_RST# to JP1.140. 4layer X02
the power to the dock.
59 6 COMPAL 01/07 Benson Change DOCK ID to X02. No-pop the R42 resistor;Pop the R51 resistor. 4layer X02
60 13,14 DELL 01/15 Benson Base on Roush Discrete Graphics changes for DP. 1. Add 10KOhm POP the PU (R309) and NO-POP the PD (R311) on DPA_DOCK_AUX#. 4layer X02
C 2. Add 10KOhm NO-POP the PU (R310) and POP the PD (R312) on DPA_DOCK_AUX. C
3. Add 10KOhm POP the PU (R313) and NO-POP the PD (R315) on DPB_DOCK_AUX#.
4. Add 10KOhm NO-POP the PU (R314) and POP the PD (R316) on DPB_DOCK_AUX.
61 5 DELL 01/14 Benson The Docking pinout will change to move the DOCK_DET# Swap pin141 and pin143 on connector.
Swap pin142 and pin144 on connector. 4layer X02
and SLICE_BAT_PRES# pins to minimize the false
detection of an attached dock or slice battery when the
system is inserted at an angle
62 11 DELL 01/15 Benson Customer Request Change L31 to 0 ohm resistor for LOM CT signaling 4layer X02
63 9,10,11 DELL 01/15 Benson Change COMPAL part. Change U7,U33,U37,U45 from TPS2066DR_SO8~D to TPS2066ADR_SO8~D0 part. 4layer X02
64 7 COMPAL 01/16 Benson Parallel capactior change to 0402 capacitor... Change CP1,CP2,CP3,CP4 from Parallel capactior to (C259-C274) 0402
capactior. 4layer X02
65 12 COMPAL 01/29 Benson Change the ports for CRT EA report. Add 2.2pF capacitor to C97~C102 and change L14~L16 to 22 ohm bead 4layer X02
(BK1608HS220T_0603~D).
B 66 12 COMPAL 01/24 Benson Customer Request: 4layer X02 B

1. Change part F4 from 3A_6VDC to 1.1A_6V.
1.Change FUSE part
67 15 DELL 2/12 Benson For customer request. 1.Change part L21,L25from BK1608LM182-T_0603~D to BLM18EG601SN1D_2P~D.
Power supply filtering for U17 the SSM2603. 2.Pin3 and pin5 of U19 are combined together,and remove part C133,C187 4layer X02
and add L25 to keep the power supply clean.
3.Pin12 and pin18 of U19 are combined together,and remove part C124,C125.
Change C126,C129,C131 from 1uF to 10U_0805_10V4Z~D.
68 13,14 DELL 2/14 Benson For customer request.
Based on a review of the DP spec.we are 4layer X02
considering making changes to the DP 1.Change part F2 and F3 from 1.1A_6V_1812L110PR~D to 3A_6VDC_2920SMD300.
connector power delivery, like adding a 2. Add part C128 10U_0805_10V4Z~D at +DPA_VCC net
PTC fuse and bulk capacitance on the 3. Add part C133 10U_0805_10V4Z~D at +DPB_VCC net
system and dock side.
4layer X02
69 13,14 DELL 2/14 Benson DP BOM Changes to Support PT SMT R202 and R208 should change to 3.83K for passing DP eye.
A A
Title
EE PIR-4
X03
5 4 3 2 1
5 4 3 2 1

Request
70 13,14,16 DELL 02/19 Benson Customer Request:
D 1.Change Display connector part 1. Change part JDP1,JDP2 from MOLEX_47272-0001~D to MOLEX_47272-0026. 4layer X02 D
2.Change Audio connector part 2. Change part JAUD1 from TYCO_1775390-6 to TYCO_6-1775390-6.
71 13, 14 DELL 02/19 Benson DP BOM Changes to Support PT SMT
R202 and R208 should change to 3.83K for passing DP eye. 4layer X02
For customer request. 1. Add D35 part.anode to the output Pin13(LHOUT) and the cathode to
72 15,16 DELL 02/19 Benson pin 12 HPVDD.
Audio Output protection.
2. Add D36 part.anode to the output Pin14(RHOUT) and the cathode to 4layer X02
pin 12 HPVDD.
3. Add one capacitor of around 300pF in parallel with R223 and do the
same for R224, and place these 2 capacitors be close to the U17.
73 12 DELL For customer request.

02/19 Benson F4 change to No_pop;R109 change to pop. 4layer X02
Change CRT FUSE to No_pop.
74 15,16 ADI 02/19 Benson Recommended by ADI 1.Delete the R23~R26 Part 0_0603_5%~D. 4layer X02
2.Delete the C165,C183 Part 0.1U_0402_16V7K~D.
3.Delete the L28~L30 Part 0_0603_5%~D.
C 4.Add the C134 Part 0.1U_0402_16V7K~D at +3.3V_RUN. C
5.Add the C132 Part 0.1U_0402_16V7K~D at +3.3V_AVDD.

6.Add the R92 Part 0_0402_5%~D at AGND and DGND.
7.Change the C275 net from HP_SPK_L1 to AUD_DOCK_HP_OUT_L.
8.Change the C276 net from HP_SPK_R1 to AUD_DOCK_HP_OUT_R.
9.Change the C145 net from MIC3 to MIC2.
10.Delete the D26,D27 Part PRTR5V0U2X_SOT143-4~D.
11.Delete the L24 Part BLM18AG121SN1D_0603~D.
12.Delete the R225~R226 Part 0_0402_5%~D.
75 6,13,14 COMPAL 03/04 Benson Enhance ESD test result. 1.Add C165 0.1uF on SIO_RESET#(near chip side). 4layer X02
2.Add C183 and C183 0.1uF on DP_A_HP and DP_B_HP(near chip side)
76 15,16 ADI 03/10 Benson Recommended by ADI 1.Delete the C134 Part 0.1U_0402_16V7K~D.
2.Change the C126,C131 Part from 10U_0805_10V4Z~D to 4.7U_0805_10V4Z~D. 4layer X02
B
3.Change C129 Part from 10U_0805_10V4Z~D to 0.1U_0402_16V7K~D. B
4.Delete the C275,C276,L23,L22,C137,C138,R141 part.

5.Change the R139 from 40.2K_0402_1%~D to 200_0402_1%~D.
6.Change the C145,1 net from Mic_2 to DOCK_MICIN.by the way change to
1000PF.
77 13 COMPAL 03/10 Benson Change the ports for DPa EA report. 1.Change R202 Part from 3.83K_0402_1%~D to 4.02K_0402_1%~D.
4layer X02
78 16 COMPAL 03/12 Benson We review audio schematic found Symbol pin 1.Modify JAUD1 symbol.
4layer X02
define mirror.
79 13,14 DELL 03/12 Benson Change the ports for DPa an DPb EA report. 1.Change R202 Part from 4.02K_0402_1%~D to 3.48K_0402_1%~D.
1.Change R208 Part from 3.83K_0402_1%~D to 3.48K_0402_1%~D. 4layer X02
80 15 COMPAL 03/12 Benson Recommended by ADI 1.Delete R92 Resister AGND Connect DGND
2.Change L25 part from 0_0805 to BLM18EG601SN1D_2P~D 4layer X02
81 17 COMPAL 03/12 Benson Modify H14 SCREW HOLE 1.Change H14 from 3P25 to 3P8.
4layer X02
A A
82 9 COMPAL 03/12 Benson L4 swap for layout routing issue. 1.L4 swap PIN define. 4layer X02
Title
EE PIR-5
X03
5 4 3 2 1
5 4 3 2 1

Request
83 17 DELL 03/13 Benson EMI Request
D APR and add several 0.1µF capacitance from Vcc to GND 1. +DOCK_PWR_BAR net New add: 6*0.1µF C80,C82,C85,C86,C87,C70 at BOT 4layer X02 D
and PCI_CLK AC terminal. and TOP side.

2. PCI_CLK: change BOM: R60 change to 33 ohm, C29 change to 10P
84 17 DELL 03/13 Benson Audio jack pin define correct 1.Swap pin1 and pin4 on JAUD1
2.Swap pin2 and pin3 on JAUD1 4layer X02
3.Swap pin6 and pin8 on JAUD1
4.Swap pin5 and pin9 on JAUD1
1.Change C246 part form 4.7U_0603_6.3V4Z~D to 4.7U_0805_10V4Z~D. 4layer X02

85 17 DELL 03/14 Benson Change COMPAL part
86 12 DELL 03/14 Benson Change the ports for CRT EA report. Modify 2.2pF capacitor to C97~C102. 4layer X02
87 15,16 ADI 03/15 Benson 1.Improve Dynamic Range on HP and Mic. 1.Change L21 to BLM21PG331SN1D. 4layer X02
2.Need to adjust Mic Bias to accommodate Bias current of 2.Change C136 to 2K_0402_5%~D.
C
<750uA 3.Connect a cap C88 (10uf) from R136 pin 1 to Analog Ground and connect C
3.System noise is effecting the Microphone performance. a resistor R140 (200ohm) from R136 pin 1 to MICBIAS.
4.Need to meet GS Mark Spec 4.Change C135 & C140 to 100uf and the output resistor R225,R226 values
5.Improve THD on HP will be 68 Ohms.
5.Connect 2 capacitors C186,C187 of 300pF from pin 13 and pin 14 respectively to
the analog ground on U17. Please make these Nopop for now.
87 15,16 ADI 03/15 Benson R225,R226 part correct 1.Change the R225,R226 to 68_0402_5%~D.
4layer X02
88 13,14 DELL 04/08 Benson Add DP to DP repeater. Add U46,U47 8121E parts. 4layer X03
Remove the U19,U20,U21,U22,U23,U24,U25,U26 part. 4layer X03

89 13 DELL 04/08 Benson Remove the about audio no-pop part.
B B
90 13,14 TI 04/11 Cindy 1.Change pin8 and 9 of PS8121E from AUX_A_CH+/- to DPA_DOCK_AUX/#. 4layer X03
for TI comments.
2.Change HPD flow to DP connector to PS8121 to DP122 to Dock connector (1)Pin18 JDP1
connector feed pin30 PS8121 (HPD_SINK) (2)Pin 7 of PS8121 (HPD) feed pin40 DP122
(DP_HPD_SINK) (3)Pin37 DP122 (HPD) feed pin39 docking station connector
3.Add R139 and R321 to pull high DDCBUF_EN# of PS8121E.
4.remove CA_DET application circuit.
91 13,14 DELL 04/16 Benson for Dell comments. 1. C182,C183 should be "no-pop" and the value should change to 0.033uF
(0402 pkg).
2. Place pads for a 600 ohm FB (0402 pkg) between JDP1 pin 18 and the 4layer X03
DPA_DOCK_HPD net. Please use a 0 ohm resistor in this location.
3. Place pads for a 600 ohm FB (0402 pkg) between JDP2 pin 18 and the
DPB_DOCK_HPD net. Please use a 0 ohm resistor in this location.
4. Populate the R244,R245 and "no-pop" the D7,D9.
5. Change the R276,R279 to "no-pop".
A 4layer X03 A
92 06 COMPAL 04/16 Benson Change Dock ID form X02 to X03. 1.Change the R44 to "pop" ,R53 to "no-pop".
4layer X03
93 13 DELL 04/18 Benson for Dell comments. 1.Change the PS_PC0 "R318" and PS_PC1 "R320" to "no-pop".
Title
EE PIR-5
X03
5 4 3 2 1
5 4 3 2 1

Request
94 13,14 Parade 04/18 Benson for Parade comments.
D 1.Add the C290,C291 AC_coupled capacitor on AUX channel U46 and 4layer X03 D
Please add the ac-coupled capacitor on AUX channel add the R322,R323 pull up 100K to 3.3V .
to PS8121ED 2.Add the C292,C293 AC_coupled capacitor on AUX channel U47 and
add the R324,R325 pull up 100K to 3.3V .
C C
B B
A A
Title
EE PIR-6
X03
5 4 3 2 1
5 4 3 2 1

Request
1 17 8/2 Change PR10 and PR12 from 240K to 100K X01
D GG list DELL Follow GG_issue_list Change PR11 from 100K to 240K D
Change PR13 and PR16 from 240K to 150K

Change PR14 from 100K to 43K
Change PR15 from 240K to 7.87K
Change PR17 from 100K to 56K
Change PC8 from 0.1U to 1U
Add PR140 and PR141.

Connect PR140_2 to NB_Det#, X01
Because the Vgs rating for RUH002N06 is 20V
Derating and the NB_Det# is 19V.so we need adding Connect PR140_1 to PR141_2and PQ17_2.
2 18 issue resister to divide the voltage. Connect PR141_1 to GND
8/7 Compal
+3.3V_ALWP Because the power budget is 0.57A_MAX
Choke Size for *3.3V_ALWP, we change the size for PL3 Change PL3 from 10mm*10mm*4mm to 7mm*7mm*3mm X01
3 18 8/7 Compal
change location PR52 and PC39 each other change location PR52 and PC39 each other X01
4 18 EMI 8/9 Compal change location PR53 and PC40 each other change location PR53 and PC40 each other
The APL431LBAC-TRL for PU1 is not approve Change PU1 from APL431LBAC-TRL(AMPEC) to TL431BQDBZR(TI).
5 17 PSL issue 8/15 Compal vender base on DELL PSL list Change PR15 from 7.87K to 16.5K X01
C C
Add PD10 between PQ2.1 and PQ22.8 Add PD10 between PQ2.1 and PQ22.8
6 17 DC_IN 8/15 Compal X01
Dock supports the 230W adapter. The FDS6679 Change PQ1 and PQ2 from FDS6679 AZ to FDS6681Z
7 17 DC_IN 8/20 Compal is not enough to meet current rating. We plan to X01
change MOS for PQ1 and PQ2.
X02
8 18 Component 9/6 Compal The FDS6676AS is common part Change PQ16 from FDS6676S to FDS6676AS.
9 17 Time seqence setting when NB insert to Docking
DC_IN 9/10 Compal Add PR54 and PR55, no-pop PR54 X02
10 Component Compal The Vender (TI) will material shortage issue for
17 shortage issue9/12 TL431BQDBZR on PU1 Change PU1 form TL431BQDBZR (TI)to LM431SBCMF(FIRCHILD) X02
We plan to implement TL431BQDBZR on PT 2nd source
ACAV_IN 10/26 DELL Support E-Dock hot plug/unplug of AC Adapter

11 17 circuit 1. Change component X02
B B
PC6 from 0.47U to 0.1U
PR4 from 240K to 1M
PR6 from 47K to 220K
PR7 from 47K to 22K
PR8 from 100K to 10K
PR5 from 100K to 4.99K
PR10 from 100K to 24.9K
PR13 and PR16 from 150K to 30K
PC8 from 1U to .047U
2, Change net name for PR12.1 from +DOCK_SDC_IN to +DOCK_DC_IN_SS
3. Stuff PR54 and un-stuff PR55
12 17 PSID circuit 10/31 Compal Dock PSID signal fail Change net name from +5VALW to +5V_ALW for PD3_Pin3, PR22_Pin2 X02
and PD5_Pin3
A A
Title
Power PIR
X03
5 4 3 2 1
5 4 3 2 1

Request
1 17 ACAV_IN 11/12 DELL When no AC adapter is in E-Dock and 1.Delete cline between PR8_pin2 and Pq4_pin2 X02
D
circuit EN_DOCK_PWR_BAR is low to hold of Roush PQ23, 2.Add PR46(100K) between PQ4_pin3 nad PQ4_pin2. D
there is back drive issue where the 3.Add PR56(100K) between PQ5_pin3 nad PQ5_pin2.
+DOCK_PWR_BAR is held up. The issue is that NB 4.Add PR57(100K) between PQ18_pin1 nad PQ5_pin2.
DOCK_DCIN_IS+ and - on the NB side is biased up 5.Add PQ18(RHU002N06), connect PQ18_Pin1 to PR57_pin2; connect
to +PWR_SRC potential, this holds the source PQ18_pin2 to PD3_pin2; connect PQ18_pin3 to GND
terminals of both PQ4, and PQ5 higher than
their gates, which are biased up to
+DOCK_PWR_BAR rail. The FET's perhaps
operate in a linear mode where they are not
fully turned off allowing current flow back into
the _DOCK_PWR_BAR rail.
17 ACAV_IN Change net "ACAV_IN_DOCK#" to "ACAV_DOCK_SRC#"

2 circuit 11/12 DELL Change net "ACAV_IN_DOCK#" to "ACAV_DOCK_SRC#" X02
17 Comparator
3 Circuit 11/12 DELL Add Comparator Circuit 1.Add PU11 (LM393) X02
C C
2.Add PC41 and PC42(100P)
3.Add PR143 (232K)
4.Add PR146 (21.5K)
5.Add PR144 (32.4K)
6.Add PR147 (100K)
7.Add PR142 (1M) 8.Add PR145 (0)
9.Add new net for "ACAV_IN_DOCK" 10 Add PR58(100K)
4 17 ACAV_IN 11/15 DELL EE work item Add PD11 (RB751) X02

circuit
ACAV_IN 11/15 DELL Change PC6 from 0.1U to 0.022U

5 17 circuit EE work item Change PR6 from 220K to 1M ohm X02
6 18 POR issue 12/20 DELL Reserve the Dock side delay circuit, but 1. Add PR68 (0)
B
show it as no stuff with resistor option to Add @PR59 (200K) X03 B
short out. Add @PR60 (200K)

Add @PR61 (0)
Add @PR62 (200K)
Add @PR63 (100K)
Add @PR64 (1K)
Add @PR65 (40.2K)
Add @PC43 (0.047U)
Add @PC44 (10U)
Add @PC45 (10U)
Add @PD12 (RB751V)
Add @PQ19A (2N7002DW)
Add @PQ19B (2N7002DW)
A A
Title
Power PIR
X03
5 4 3 2 1
5 4 3 2 1

Request
7 19 POR issue 12/20 DELL POR issue 1.Delete PR42, PR140, PQ17 X03
D
2.Add PD13 (RB751V) D
3.Add PC46 (0.1U)

4.Change PR45 from 4.99K to 10K
5.Add net DOCK_POR_RST# and connect to PD13_pin2
8 18 E-Dock 12/24 DELL marginal on guarantee turn off PQ11. 1.Change PR16 from 30K to 10K
Worse With the Vgth of 1 to 2.5 volts, the node 2.Change PR10 from 24.9K to 12.1K X03
case PQ11 at the gate only drops to 1 volt. I think this 3.Change PQ11 from RHU002N06(ROHM) to NTS4001NT1G(ON)
is a result of changing from a 1.5V Vref
TL431 to a 2.5V TL31 early in development.
We also need to be able to turn on the transistor
while powered via battery power so the 2.5V
threshold is important as well. When calculation
the circuit values required I find adjusting PR13
, and PR16 considering battery voltage of 9 volts
is right at 2.5V, while the values result in a low
C C
voltage of ~1V, just not too much margin.
Really we need a tighter Vgth MOSFET.
To add a PR69 0 ohm option on the next Dock

9 18 crowbar 12/24 DELL Gerber out to tie PQ8 source to pin 1. Add PR69 0 ohm, no stuff. X03
The other 0 ohm will still got to dock ground.
This to allow instant release of NB AC softstart
upon hot undock if we later determine we have an
issue.
01/30 Compal The vender (DELTA) molding type is non psl. Change PL3 form 10UH +-20% MPL73-100 3A (DELTA)to 8.2UH +-20% X03
10 19 +3.3V FDV0630-8R2M=P3 3.7A (TOKO).
B B
PQ1 and PQ2 are P-channel material

11 18 Dock DC_IN 03/19 Compal ,but we use N-channel symbol. Change PQ1 and PQ2 symbol from N-Channel to P-Channel. X03
A A
Title
Power PIR
X03
5 4 3 2 1

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5 4 3 2 1

E-Docking Schematics Document

Compal confidential Block Diagram

Display Port/ PS8121E Display Port

USB 2.0 HUBPage 8

PS2 (x2) PS2 (x2)

10K 10K 48 (0100 1000)

2N7002 SMSC 47N237

145 PWR1 PWR3 149 +DOCK_PWR_BAR

153 Shield_G1 Shield_G5 157

R229 1 2 @ 100K_0402_1%~D RTS1# +VTR +3.3V_ALW

LPC & GPIO

SMB_DAT 3 68 R32 1 2 33_0402_5%~D PD0

8 71 R35 1 2 33_0402_5%~D PD3

SDAT_2 PD4 R37 33_0402_5%~D PD5

MIC_DET 15 11 VTT_PWRGD DTYPE1

2N7002W-7-F_SOT323-3~D 24MHZ_12PF_1BX24000CE1B~D 1 GP36 GP35 GP34

Compal Electronics, Inc.

C USB_HUB1_RST# RESET_N VDD18PLL +VDD18_1 R264 C

+3.3V_SUS +3.3VDDA_USB2 +3.3V_SUS +3.3V_SUS BLM18PG181SN1_0603~D

USB_HUB2_RST# PRTPWR2 S_USB_OC5#

FX_SMB_CLK FX2_SMB_CLK PRTPWR3 S_USB_OC6#

1 2 1 2 S_XTAL2 11 TEST Thermal Slug(VSS) 37

1 1 1 1 1 0 Bus Power Operation / LED Mode = USB

A 24MHZ_12PF_1BX24000CE1B~D R216@ USB2513-AEZG_QFN36_6X6~D 2-Wire I2C EEPROMS are support A

2 Compal Electronics, Inc.

R90 0_0402_5%~D PRTR5V0U2X_SOT143-4~D 1

TPS2066ADR_SO8~D R302 0_0402_5%~D Need close JESATA. TYCO_1909573-3

0.1U_0402_16V4Z~D SATA_SBTX_DRX_N 4 17 SATA_SBTX_C_DRX_N_1 2 1 SATA_SBTX_C_DRX_N

<8> S_USB6_EN INA S_USB6_EN_1 SATA_SBRX_DTX_P SATA_SBRX_C_DTX_P_1

U41 SATA_SBRX_DTX_N 8 13 SATA_SBRX_C_DTX_N_1

+5V_ALW R267 1 2 1K_0402_5%~D 1 9

Need close U42 pin 6, 19.

SATA_SBTX_DRX_P 1 2 SATA_SBTX_P 1 2SATA_SBTX_C_DRX_P_1

Bill0703: Please place under U42. (co-layout..)

TPS2066ADR_SO8~D @ L35 DLW21SN900SQ2_0805~D

RED RED <7>

VGA_HS 1 2 HSYNC_L 2 4 HSYNC_BUF

VGA_VS 1 2 VSYNC_L 2 4 VSYNC_BUF

44 R317 500_0402_1% PS_REXT 5

Display port Connector

@ 1 DPA_DOCK_RP1_LANE0 C251 1 2 0.1U_0402_10V7K~D DPA_DOCK_RP_LANE0 38

IN2n VCC DPA_DOCK_LANE1_C DPA_DOCK_LANE1_C

17 DPA_DOCK_LANE2 C226 1 2 0.1U_0402_10V7K~D DPA_DOCK_LANE2_C

@ +3.3V_RUN_DPA 29 16 DPA_DOCK_LANE2# C227 1 2 0.1U_0402_10V7K~D DPA_DOCK_LANE2#_C

R322 1 2100K_0402_5%~D 14 DPA_DOCK_LANE3 C228 1 2 0.1U_0402_10V7K~D DPA_DOCK_LANE3_C DPA_DOCK_LANE2_C 1 10 DPA_DOCK_LANE2_C

2 2 2 2 2 2 Compal Electronics, Inc.

GND 42 8 LAN2_shield GND 24

57 51 R331 500_0402_1% PS1_REXT DPB_DOCK_LANE1#_C 6

R324 1 2100K_0402_5%~D 14 DPB_DOCK_LANE3 C236 1 2 0.1U_0402_10V7K~D DPB_DOCK_LANE3_C

R325 1 2100K_0402_5%~D PS1_I2C_CTL_EN# 26

B PS1_PC0 OE# HPD DPB_DOCK_LANE2_C B

DP_B_HP PS1_CEXT 10 37 DPB_DOCK_LANE3#_C 5 6 DPB_DOCK_LANE3#_C

2 2 PS1_PC0 DPB_DOCK_AUX# DPB_DOCK_AUX#

A 140mA Place close to JDP2 connector A

+3.3V_RUN +3.3V_AVDD +3.3V_DCVDD +3.3V_RUN

<16> MICBIAS MICBIAS DACDAT

<5,6,8> DOCK_SMB_DAT 1 3 FX3_SMB_DAT <15>

<5,6,8> DOCK_SMB_CLK 1 FX3_SMB_CLK <15>

CLIP3 CLIP2 CLIP1 H1 H2 H3 H5 H6 H7

0.1U_0402_16V4Z~D CLIP5 CLIP4

H11 H8 H9 H10 H14 H16