DNS m116cc (Lengda m116 Intel Calpella Reva)

5 4 3 2 1
catalog
01 Cover sheet
02 Block_Diagram
03
D SMBUS_&_IRQ_Routing D
04 Power_On_Sequence
05 Power_Block
06 Clock Generator
07 CPU1
08 CPU2
09
10
11
THERMAL
NB1
NB2
INTEL CALPELLA Platform
12 NB3
13 NB4
14 NB5
15 NB6
C C
16 LCD
17 CRT
18 DDR2_SODIMM0
19 TBD
20 DDR2_Temination
21 ICH9M1
22 ICH9M2
23 ICH9M3
24 ICH9M4 Version : A
25 LAN
26 Audio_ALC269 Drawing by : CQ.CHEN
27 SATA Connector
B 28 MiniCard1-WirLAN {Item}\t{Lengda Code}\t{Quantity}\t{Reference}\t{Description}\t{Value}\t{Tolerance}\t{PCB Footprint}\t{Voltage}\t{Wattage}\t{POP}\t{100M}\t{1000M}\t{NSHDMI}\t{NSBT261}\t{NS3G} B
29 MiniCard2-3G {Item}\t{Lengda Code}\t{Quantity}\t{Reference}\t{100M}\t{NS3G}
30 Fan&Card Reader
31 KBC-IT8502E
32 Power_Charger
33 Power_System
34 Power_DDR2
35 Power_+V1.05S_+V1.5S
36 Power_VCore
37 Power_Good
38 Power_S3_S4
39 USB_PORT&LED
40 Main_Board CONNECTOR
A
41
42
HDD Board
DC IN
Notes: A
Lengda Technology Ltd.

Part Value Prefix : "@" means nopop 5th floor,Block K,
Xiamen Exprot Processing Zone,
Haicang District,Xiamen,China,361026
Net Value suffix : "#" means Low Active
Title <Title>
Size Sheet Rev
Cover Sheet
C Name A
ENGINEER: Ivan Date: Thursday, February 17, 2011 Sheet 1 of 63
5 4 3 2 1
5 4 3 2 1
BLOCK DIAGRAM System Power

TPS51125
D
DDR3-1066/1333 SO DIMM1 D
14.318MHz
XDP CPU Power
DDR3-1066/1333 SO DIMM2
CPU TPS51621
Intel Calpella
CLK_CPU_BCLK CPU
Clock Gen
DREFCLK SRC-0/DOT96 dGPU Power
DMI FDI
DREFSSCLK SRC-1/SE1 TPS51621
CLK_PCIE
R.G.B
CRT CLK_FWHPCI
CLK_KBCPCI Chipset Power
LVDS TPS51117
C C
LCD
ME Flash
SATA
Hard Disk Control Link
DDR3 Power
PCH PCI-E PCI-E 3 TPS51116
LAN 25MHz
SATA CLK_PCIE
ODD
PCI-E 1 PCIE/USB-WIFI
32.768KHz LPC BUS USB1 Charger
BQ24705
PCI-E 2 PCIE/USB-3G
CLK_KBCPCI USB11
B
KBC USB2.0
B
32.768KHz S3/S4 Control

and Discharge
CLK_Azalia Azalia
TOUCH USB0 Camera
FAN Flash KB PAD USB2 Card Reader
USB4 PORT3
Audio USB8 PORT2
Codec
USB10 BlueTooth
USB12 PORT2
A A

5th floor,Block K,
Title <Title>
Size Sheet Rev
Block Diagram
C Name A
ENGINEER: Ivan Date: Monday, March 08, 2010 Sheet 2 of 63
5 4 3 2 1
5 4 3 2 1
RESET TOPOLOGY
CPU
D D
PLT_RST# BUF_PLT_RST#
Buffer HDD
MiniCard1
MiniCard2
PCH GPU
KBC
ACZ_RST# LPC Port
Audio
DVD ROM
LAN
C C
B B
A A

5th floor,Block K,
Title <Title>
Size Sheet Rev
RESET TOPOLOGY
C Name A
5 4 3 2 1
ACIN 03
POWER ON SEQUENCE Circuit
+V_DC_IN
5AC 1BAT
1AC +V_ADP_IN POWSW#
D
1 Startup D
Circuit
+V_ADP_OUT
+VBAT
Batt Charger
Circuit
5AC
+V_DC SMCONOFF#
7 +V3.3A +V5A
PM_S4_STATE#
+V3.3 S4 +V3.3A PM_SLP_S3#
+V5 shutdown +V5A

System VR EC_VAUX_ON
Power Monitors KBC1122
+V3.3A,+V5A
control RSMRST#_PWRGD
DELAY_IN
C Delay 99ms Delay 10ms C
ALL_SYS_VRPWRGD
DELAY_OUT
IMVP_VR_ON
PM_PWRBTN#
PMRSMRST#
+V3.3A +V5A
PM_S4_STATE#
SYSTEM_PWRGD
S3 shutdown
Power control 5a 5b
PM_SLP_S3#
+V3.3S +V5S
MPWROK
CLPWROK
PM_S4_STATE# ICH9 CLK_PWRGD
H_PWRGD
+V1.8 PM_SLP_S4#
AND
PM_SLP_S4# PM_SLP_S3#
+V1.8 +V0.9S
VRMPWRGD
PWROK
LDO DDR2 17
1.5S VR
B B
+VCC_Core
17 +VCCP
15 14
PLT_RST#
DDR_VR_PWRGD
1.05S VR MPWROK ALL_SYS_VRPWRGD
CHIPSET_VRPWRGD
AND
+VCC_GMCH_Core
H_CPURST#
+VCCP CPU
+V1.05S AND Penryn
19
+VCC_CORE IMVP_VR_ON
Cantiga
ENABLE
DELAY_IN DELAY_OUT MPWROK
PWROK CLPWROK
A
IMVP +V3.3S A
VR GVR_VR_EN
CLK_EN# System +VBAT +VCC_GFXCORE
CLK_PWRGD Clock GFX VR Lengda Technology Ltd.

ENABLE 5th floor,Block K,
Title <Title>
Size Sheet Rev
Power_On_Sequence
C Name A
5 4 3 2 1
5 4 3 2 1
BC BC
BB BB
BA BA
AZ AZ
AY AY
AX AX
AW AW
AV
POWER Delivery Architectural Block Diagram AV
AU AU
AT AT
AS AS
AR AR
AQ AQ
AP
ADAPTOR AP
AO +V_DC DDR2 POWER Module +V1.8 +V0.9S AO
AN AN
AM AM
+V1.8S
AL AL
Charger
AK
CPU VCORE POWER Module AK
+VCC_CORE
AJ AJ
AI AI
AH AH
+V1.05S
AG AG
BATTERY
1.05V POWER Module
AF AF
AE AE
AD AD
AC AC
1.5V POWER Module

AB +V1.5S AB
AA AA
Z Z
Y +V3.3A Y
+V3.3S
X X
W +V5A W
V
+V5S V
U SYSTEM POWER Module U
T T
S S
R R
Q Q
P P
O O
N N
M M
L L
K K
J J
I I
H H
G G
F F
E
Lengda Technology Ltd. E
5th floor,Block K,
D Xiamen Exprot Processing Zone, D
C C
Title <Title>
B B
Size Sheet Rev
Power_Block
C Name A
A ENGINEER: Ivan Date: Thursday, March 04, 2010 Sheet 5 of 58
A
5 4 3 2 1
5 4 3 2 1
Request Signal
SRC0 DREFCLK
+V3.3S
SRC1 DREFSSCLK
LAYOUT NOTE: PLACE ONE PER PIN
FB1 120R FB0805N VDD_CLK3.3 SRC2 CLK_SATA CLK_SATA_OE#
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 SRC3 CLK_PCIE_SOCKET1
1uF
CC0603N
4.7UF
CC0603N
0.1u
CC0402N
0.1u
CC0402N
0.1u
CC0402N
0.1u
CC0402N
0.1u
CC0402N
0.1u
CC0402N
0.1u
CC0402N
0.1u
CC0402N
0.1u
CC0402N
0.1u
CC0402N
0.1u
CC0402N SRC4 CLK_PCIE_ICH
POP = NA
SRC6 CLK_PCIE_LAN
D SRC8 CLK_PCIE_NEWCARD CPPE# D
SRC9 CLK_PCIE_3GPLL CLK_MCH_OE#

VDD_48
SRC10 CLK_PCIE_SOCKET2 CLK_PCIE_SOCKET2_OE#
C14 C15
0.1u 4.7UF
CC0402N CC0603N
POP = NA
VDD_PLL3
C18 C17 C16 20PF CC0402N XIN

0.1u 4.7UF
2
CC0402N CC0603N
POP = NA X1 X10
X8A01431AFK1H OSC-2-14.318MHZ
POP = NA
1
C19 20PF CC0402N XOUT
SMB_CLK_S2 13,16,29,30
ccq,evt->dvt,0625
SMB_DATA_S2 13,16,29,30
C20 C21
22pF 22pF
CC0402N CC0402N
U1 POP = NA POP = NA
1 **CR#_A/PCI-0 SCLK 64
VDD_CLK3.3 2 63
VDD_PCI SDATA FS_C R1 33 RC0402N
3 **CR#_B/PCI-1 **FSC/TEST_SEL/REF 62 CLK_BUF_REF14 16
TME/PCI-2 4 61 VDD_CLK3.3
**TME/PCI-2 VDD_REF XIN
5 PCI-3 Xin 60
SRC5_EN/PCI4 6 59 XOUT
ITP_EN/PCI-5 **SRC5_EN/PCI-4 Xout
7 **ITP_EN/PCIF-5 GND_REF 58
C
For EMI VDD_48
8
9
GND_PCI **FSB/TEST_MODE 57
56
FS_B
R11 1k RC0402N C
VDD_48 **CK_PWRGD/PD# CLK_PWRGD 41
POP = NA CC0402N 10pF C23 CLK_CD48 R9 22 RC0402N FS_A 10 55 VDD_CLK3.3 C22 0.1u CC0402N
28 CLK_CD48 **FSA/USB48 VDD_CPU CPU0 R915 0 RC0402N
11 GND_48 CPU-0 54 CLK_BUF_BCLK_P 16
VDD_CLK3.3 12 53 CPU0# R916 0 RC0402N CLK_BUF_BCLK_N 16
R43 0 RC0402N SRC-0/DOT96 VDD_IO1 CPU-0#
16 CLK_BUF_DOT96_P
16 CLK_BUF_DOT96_N R44 0 RC0402N SRC-0/DOT96#
13
14
SRC-0/DOT96 RTM875T-606 GND_CPU 52
51
SRC-0#/DOT96# CPU-1
15 GND_IO1 CPU-1# 50
VDD_PLL3 16 49 VDD_CLK3.3
R917 0 RC0402N SRC-1/SE1 VDD_PLL3 VDD_CPU_IO R14 0 RC0402N POP = NA
16 CLK_BUF_CKSSCD_P 17 SRC-1/SE1 RESET# 48
16 CLK_BUF_CKSSCD_N R918 0 RC0402N SRC-1#/SE2 18 SRC-1#/SE2 TSSOP64 SRC-8/CPU_ITP 47 PCIE_CLK5
PCIE_CLK5#
R15
R16
0 RC0402N
0 RC0402N
POP = NA
POP = NA
BCLK_ITP_P 7
19 GND_PLL3 SRC-8#/CPU_ITP# 46 BCLK_ITP_N 7
VDD_CLK3.3 20 45 VDD_CLK3.3
R913 0 RC0402N VDD_PLL3_IO VDD_SRC_IO3
16 CLK_BUF_EXP_P 21 SRC-2/SATA **CR#_F/SRC-7 44
16 CLK_BUF_EXP_N R914 0 RC0402N 22 43
SRC-2#/SATA# **CR#_E/SRC-7#
23 GND_SRC1 GND_SRC3 42
24 41 +V3.3S
**CR#_C/SRC-3 SRC-6
25 **CR#_D/SRC-3# SRC-6# 40
VDD_CLK3.3 26 39 VDD_CLK3.3
VDD_SRC_IO1 VDD_SRC1 PCI_STOP# R22 0 RC0402N POP = NA PCI_STOP# R919 10k RC0402N
27 SRC-4 **PCI_STOP#/SRC-5 38 STP_PCI# 19
28 37 CPU_STOP# CPU_STOP# R8 10k RC0402N
SRC-4# **CPU_STOP#/SRC-5# VDD_CLK3.3
29 GND_SRC2 VDD_SRC_IO2 36
30 35 R20 0 RC0402N POP = NA
SRC-9 SRC-10# R21 0 RC0402N POP = NA
31 SRC-9# SRC-10 34
32 33 R23 0 RC0402N POP = NA
**CR#_G/SRC-11# **CR#_H/SRC-11
TSSOP50P810-64N
+V1.1S_VTT +V1.1S_VTT +V1.1S_VTT +V3.3S
STRAP MODE STUFF UNSTUFF
R24 R25 R26 R27 NO OVERCLOCKING R26 PULL UP R27 PULLDOWN

B 1k 1k TME B
56 10k
RC0402N RC0402N RC0402N RC0402N NORMAL R26 PULLDOWN R27 PULL UP
POP = NA POP = NA POP = NA
SRC5 ENABLED R19 PULL UP R23 PULLDOWN
FS_A FS_B FS_C SRC5_EN/PCI4 SRC5_EN
R23PULLDOWN R19 PULL UP
SRC5 DISABLED
R28 R29 R30
1k 1k 1k R31 ITP ENABLED R24 PULL DOWN R25 PULL UP
RC0402N RC0402N RC0402N 10k SRC-5 pair enable strap. ITP_EN
POP = NA RC0402N SRC8 ENABLED R25 PULL UP R24 PULL DOWN
1 Pins37,38 as SRC-5 differential pair.
0 Pin37 as CPU_STOP# , pin 38 as PCI_STOP#.
+V3.3S
R32
10k
RC0402N
POP = NA
ITP_EN/PCI-5
R33 LVTTL CPU-ITP/SRC-8 select

10k
RC0402N 1 Pin 46,47 as CPU_ITP differential pair.
POP = NA
0 Pin 46,47 as SRC-8 differential pair.
+V3.3S
A A
R34
10k
RC0402N
POP = NA 1 NO OVERCLOCKING
TME/PCI-2
0 NORMAL Lengda Technology Ltd.
R35 5th floor,Block K,
10k Xiamen Exprot Processing Zone,
RC0402N Haicang District,Xiamen,China,361026
Title <Title>
Size Sheet Rev
Clock Generator
C Name A
ENGINEER: Ivan Date: Friday, October 15, 2010 Sheet 6 of 62
5 4 3 2 1
5 4 3 2 1
D D
U2A
B12 PEG_IRCOMP_R R36 49.9 ±1% RC0402N
PEG_ICOMPI
PEG_ICOMPO A13
17 DMI_TXN0 F7 DMI_RX#[0] PEG_RCOMPO D12
17 DMI_TXN1 J8 B11 EXP_RBIAS R38 750 ±1% RC0402N
DMI_RX#[1] PEG_RBIAS
17 DMI_TXN2 K8 DMI_RX#[2]
17 DMI_TXN3 J4 DMI_RX#[3] PEG_RX#[0] G40
PEG_RX#[1] G38
17 DMI_TXP0 F9 DMI_RX[0] PEG_RX#[2] H34
J6 P34 ccq,dvt->pvt,1008
17 DMI_TXP1 DMI_RX[1] PEG_RX#[3]
DMI
17 DMI_TXP2 K9 G28 U2B
DMI_RX[2] PEG_RX#[4] RC0402N 20±1% R37 H_COMP3
17 DMI_TXP3 J2 DMI_RX[3] PEG_RX#[5] H25 AD71 COMP3
H24 AK7 R39 0 RC0402N
PEG_RX#[6] BCLK BCLK_CPU_P 19
H_COMP2
Misc
17 DMI_RXN0 H17 D29 RC0402N 20±1% R40 AC70 AK8 R41 0 RC0402N
DMI_TX#[0] PEG_RX#[7] COMP2 BCLK# BCLK_CPU_N 19
17 DMI_RXN1 K15 DMI_TX#[1] PEG_RX#[8] B26
17 DMI_RXN2 J13 D26 RC0402N 49.9 ±1% R42 H_COMP1 AD69 K71
DMI_TX#[2] PEG_RX#[9] COMP1 BCLK_ITP BCLK_ITP_P 6
Clocks
17 DMI_RXN3 F10 DMI_TX#[3] PEG_RX#[10] B23
RC0402N 49.9 ±1% R45 H_COMP0 BCLK_ITP# J70 BCLK_ITP_N 6 For XDP
PEG_RX#[11] D22 AE66 COMP0
17 DMI_RXP0 G17 A20 L21 R46 0 RC0402N
DMI_TX[0] PEG_RX#[12] PEG_CLK CLK_EXP_P 16
17 DMI_RXP1 M15 D19 J21 R47 0 RC0402N
DMI_TX[1] PEG_RX#[13] PEG_CLK# CLK_EXP_N 16
17 DMI_RXP2 G13 A17 POP = NA RC0402N 0 R48 SKTOCC#_R M71
DMI_TX[2] PEG_RX#[14] PROC_DETECT R49 0 RC0402N
17 DMI_RXP3 J11 DMI_TX[3] PEG_RX#[15] B14 DPLL_REF_SSCLK Y2 CLK_DP_P 16
W4 R50 0 RC0402N
DPLL_REF_SSCLK# CLK_DP_N 16
F40 +V1.1S_VTT RC0402N 49.9 ±1% R51 H_CATERR# N61
PEG_RX[0] CATERR#
PEG_RX[1] J38
17 FDI_TXN[7:0] PEG_RX[2] G34
FDI_TXN0 ccq,evt->dvt,0625 BJ12 SM_DRAMRST#
Thermal
L2 FDI_TX#[0] PEG_RX[3] M34 SM_DRAMRST#
FDI_TXN1 N7 J28 R483 0 RC0402N N19
FDI_TX#[1] PEG_RX[4] 19 H_PECI PECI
FDI_TXN2 M4 G25 BV33 SM_RCOMP_0 R53 100 ±1% RC0402N
FDI_TXN3 FDI_TX#[2] PEG_RX[5] SM_RCOMP[0] SM_RCOMP_1 R55 24.9 ±1% RC0402N
P1 FDI_TX#[3] PEG_RX[6] K24 SM_RCOMP[1] BP39
FDI_TXN4 N10 B28 BV40 SM_RCOMP_2 R54 130 ±1% RC0402N
FDI_TXN5 FDI_TX#[4] PEG_RX[7] SM_RCOMP[2]
Intel(R) FDI
DDR3
Misc
R7 FDI_TX#[5] PEG_RX[8] A27 41 H_PROCHOT# N67 PROCHOT#
FDI_TXN6 U7 B25 AV66 PM_EXTTS#0 R83 0 RC0402N POP = NA
FDI_TX#[6] PEG_RX[9] PM_EXT_TS#[0] PM_EXTTS#0_EC 12,34
FDI_TXN7 W8 A24 +V1.1S_VTT R57 68 RC0402N AV64 PM_EXTTS#1
FDI_TX#[7] PEG_RX[10] PM_EXT_TS#[1] R58 10k RC0402N
PEG_RX[11] B21 +V1.1S_VTT
C 17 FDI_TXP[7:0] PEG_RX[12] B19 19 H_THRMTRIP# N17 THERMTRIP#
C
FDI_TXP0 K1 B18 R84 0 RC0402N POP = NA
FDI_TX[0] PEG_RX[13] TS#_DIMM 12,13
FDI_TXP1 N5 B16
FDI_TXP2 FDI_TX[1] PEG_RX[14] R60 10k RC0402N
N2 FDI_TX[2] PEG_RX[15] D15 PRDY# U71 +V1.1S_VTT
FDI_TXP3 R2 U69
FDI_TXP4 FDI_TX[3] R68 68 RC0402N POP = NA PREQ#
N9 N40
PCI EXPRESS -- GRAPHICS
FDI_TX[4] PEG_TX#[0] +V1.1S_VTT

FDI_TXP5 R8 L38 N70 T67
FDI_TX[5] PEG_TX#[1] RESET_OBS# TCK TP8
FDI_TXP6 U6 M32 R61 0 RC0402N POP = NA N65
FDI_TX[6] PEG_TX#[2] TMS TP9
FDI_TXP7
Power Management
W10 D40 M17 P69 R74 51 RC0402N
FDI_TX[7] PEG_TX#[3] PM_SYNC TRST#
PEG_TX#[4] A38
17 FDI_FSYNC0 AC7 FDI_FSYNC[0] PEG_TX#[5] G32 17 H_PM_SYNC TDI T69
17 FDI_FSYNC1 AC9 B33 T71 R920 51 RC0402N +V1.1S_VTT
FDI_FSYNC[1] PEG_TX#[6] TDO
PEG_TX#[7] B35 TDI_M P71
JTAG & MBP

17 FDI_INT AB5 L30 R372 0 RC0402N AM7 T70 R911 0 RC0402N
FDI_INT PEG_TX#[8] VCCPWRGOOD_1 TDO_M
PEG_TX#[9] A31
17 FDI_LSYNC0 AA1 B32 W71 R912 1k RC0402N +V3.3S
FDI_LSYNC[0] PEG_TX#[10] R63 0 RC0402N DBR#
17 FDI_LSYNC1 AB2 FDI_LSYNC[1] PEG_TX#[11] L28 19 H_CPUPWRGD Y67 VCCPWRGOOD_0
PEG_TX#[12] N26
PEG_TX#[13] M24 BPM#[0] J69 DBR#:
G21 R909 0 RC0402N DRAM_PWRGD AM5 J67 This signal is ANDed with Master Reset
PEG_TX#[14] 17 PM_DRAM_PWRGD SM_DRAMPWROK BPM#[1]
PEG_TX#[15] J20 BPM#[2] J62 to generate SYS_RESET.
BPM#[3] K65
PEG_TX[0] L40 30 H_VTTPWRGD H15 VTTPWRGOOD BPM#[4] K62
PEG_TX[1] N38 BPM#[5] J64
PEG_TX[2] N32 BPM#[6] K69
PEG_TX[3] B39 TP13 Y70 TAPPWRGOOD BPM#[7] M69
PEG_TX[4] B37
PEG_TX[5] H32 G3 RSTIN#
A34 R66 1.5K ±1% RC0402N
PEG_TX[6] 18,25,29,30,34 BUF_PLT_RST#
PEG_TX[7] D36
PEG_TX[8] J30
PEG_TX[9] B30
D33 ARD_BGA_r1p0
PEG_TX[10] R67
PEG_TX[11] N28
M25 750 ±1%
PEG_TX[12] RC0402N
PEG_TX[13] N24
PEG_TX[14] F21
B PEG_TX[15] L20 B
ARD_BGA_r1p0
+V1.5M
This Resistance Place Close to SO-DIMM
R147
1K
RC0402N
R135 0 RC0402N POP = NA

Dual Lay with Q105 PIN 2&3
Q105
+V3.3A 13 DDR3_DRAMRST# 3 2 SM_DRAMRST#

D S
G
BSS138
C696 0.1u CC0402N Close to SODIMM C228 0.1u CC0402N SOT95P280-3N
1
R1031 R539 0 RC0402N
19 DRAMRST_CNTRL_PCH
8.2K U56 R563
RC0402N SN74LVC1G08DCKR 100k
34 DRAMRST_CNTRL
5
sot65p190-5n +V1.5M_CPU C412 RC0402N

1 470pF
4 DRAMPWRGD_CPU CC0402N
30,38 V1.1S1.5S_PWRGD 2
R910 R69
3
1.5K ±1% 1.1K ±1%

RC0402N RC0402N
POP = NA
A DRAM_PWRGD A
R70
750 ±1%
RC0402N Lengda Technology Ltd.
5th floor,Block K,
Title <Title>
Size Sheet Rev
CPU1
C Name A
5 4 3 2 1
5 4 3 2 1
U2C U2D
D D
SA_CK[0] BM34 M_CLK_DDR0 13 SB_CK[0] BU33

13 M_A_DQ[63..0] SA_CK#[0] BP35 M_CLK_DDR#0 13 SB_CK#[0] BV34
SA_CKE[0] BF20 M_CKE0 13 BA2 SB_DQ[0] SB_CKE[0] BT26
M_A_DQ0 AT8 AW2
M_A_DQ1 SA_DQ[0] SB_DQ[1]
AT6 SA_DQ[1] BD1 SB_DQ[2]
M_A_DQ2 BB5 BE4 BV38
M_A_DQ3 SA_DQ[2] SB_DQ[3] SB_CK[1]
BB9 SA_DQ[3] SA_CK[1] BK36 M_CLK_DDR1 13 AY1 SB_DQ[4] SB_CK#[1] BU39
M_A_DQ4 AV7 BH36 M_CLK_DDR#1 13 BC2 BT24
M_A_DQ5 SA_DQ[4] SA_CK#[1] SB_DQ[5] SB_CKE[1]
AV6 SA_DQ[5] SA_CKE[1] BK24 M_CKE1 13 BF2 SB_DQ[6]
M_A_DQ6 BE6 BH2
BE8 SA_DQ[7] BG4 SB_DQ[8]
M_A_DQ8 BF11 BG1
BE11 SA_DQ[9] SA_CS#[0] BH40 M_CS#0 13 BR6 SB_DQ[10] SB_CS#[0] BP46
M_A_DQ10 BK5 BJ47 M_CS#1 13 BR8 BT43
M_A_DQ11 SA_DQ[10] SA_CS#[1] SB_DQ[11] SB_CS#[1]
BH13 SA_DQ[11] BJ4 SB_DQ[12]
M_A_DQ12 BF9 BK2
BF6 SA_DQ[13] BU9 SB_DQ[14]
M_A_DQ14 BK7 BF43 M_ODT0 13 BV10 BV45
M_A_DQ15 SA_DQ[14] SA_ODT[0] SB_DQ[15] SB_ODT[0]
BN8 SA_DQ[15] SA_ODT[1] BL47 M_ODT1 13 BR10 SB_DQ[16] SB_ODT[1] BU49
M_A_DQ16 BN11 BT12
BN9 SA_DQ[17] BT15 SB_DQ[18]
M_A_DQ18 BG17 BV15
BK15 SA_DQ[19] BV12 SB_DQ[20]
M_A_DQ20 BK9 BP12 BB4
M_A_DQ21 SA_DQ[20] SB_DQ[21] SB_DM[0]
BG15 SA_DQ[21] M_A_DM[7..0] 13 BV17 SB_DQ[22] SB_DM[1] BL4
M_A_DQ22 BH17 BB10 M_A_DM0 BU16 BT13
M_A_DQ23 SA_DQ[22] SA_DM[0] M_A_DM1 SB_DQ[23] SB_DM[2]
BK17 SA_DQ[23] SA_DM[1] BJ10 BP15 SB_DQ[24] SB_DM[3] BP22
M_A_DQ24 BN20 BM15 M_A_DM2 BU19 BV47
BN17 SA_DQ[25] SA_DM[3] BN24 BV22 SB_DQ[26] SB_DM[5] BV57
M_A_DQ26 BK25 BG44 M_A_DM4 BT22 BU65
BH25 SA_DQ[27] SA_DM[5] BG53 BP19 SB_DQ[28] SB_DM[7] BF67
M_A_DQ28 BJ20 BN62 M_A_DM6 BV19
M_A_DQ29 SA_DQ[28] SA_DM[6] M_A_DM7 SB_DQ[29]
BH21 SA_DQ[29] SA_DM[7] BH59 BV20 SB_DQ[30]
M_A_DQ30 BG24 BT20
DDR SYSTEM MEMORY A
BG25 SA_DQ[31] BT48 SB_DQ[32]

M_A_DQ32 BJ40 BV48
C BM43 SA_DQ[33] M_A_DQS#[7..0] 13 BV50 SB_DQ[34] SB_DQS#[0] BE2 C
M_A_DQ34 BF47 AY5 M_A_DQS#0 BP49 BM3
M_A_DQ35 SA_DQ[34] SA_DQS#[0] M_A_DQS#1 SB_DQ[35] SB_DQS#[1]
BF48 SA_DQ[35] SA_DQS#[1] BJ7 BT47 SB_DQ[36] SB_DQS#[2] BU12
M_A_DQ36 BN40 BN13 M_A_DQS#2 BV52 BT19
BH43 SA_DQ[37] SA_DQS#[3] BL21 BV54 SB_DQ[38] SB_DQS#[4] BT52
M_A_DQ38 BN44 BH44 M_A_DQS#4 BT54 BV55
BN47 SA_DQ[39] SA_DQS#[5] BK51 BP53 SB_DQ[40] SB_DQS#[6] BU63
M_A_DQ40 BN48 BP58 M_A_DQS#6 BU53 BG69
BN51 SA_DQ[41] SA_DQS#[7] BE62 BT59 SB_DQ[42]
DDR SYSTEM MEMORY - B

M_A_DQ42 BH53 BT57
BJ55 SA_DQ[43] BP56 SB_DQ[44]
M_A_DQ44 BH48 BT55
BJ48 SA_DQ[45] M_A_DQS[7..0] 13 BU60 SB_DQ[46]
M_A_DQ46 BM53 AY7 M_A_DQS0 BV59
M_A_DQ47 SA_DQ[46] SA_DQS[0] M_A_DQS1 SB_DQ[47]
BN55 SA_DQ[47] SA_DQS[1] BJ5 BV61 SB_DQ[48] SB_DQS[0] BD4
M_A_DQ48 BF55 BL13 M_A_DQS2 BP60 BN4
M_A_DQ49 SA_DQ[48] SA_DQS[2] M_A_DQS3 SB_DQ[49] SB_DQS[1]
BN57 SA_DQ[49] SA_DQS[3] BN21 BR66 SB_DQ[50] SB_DQS[2] BV13
M_A_DQ50 BN65 BK44 M_A_DQS4 BR64 BT17
BJ61 SA_DQ[51] SA_DQS[5] BH51 BR62 SB_DQ[52] SB_DQS[4] BT50
M_A_DQ52 BF57 BM60 M_A_DQS6 BT61 BU56
BJ57 SA_DQ[53] SA_DQS[7] BE64 BN68 SB_DQ[54] SB_DQS[6] BV62
M_A_DQ54 BK64 BL69 BJ69
M_A_DQ55 SA_DQ[54] SB_DQ[55] SB_DQS[7]
BK61 SA_DQ[55] BJ71 SB_DQ[56]
M_A_DQ56 BJ63 BF70
BF64 SA_DQ[57] M_A_A[15..0] 13 BG71 SB_DQ[58]
M_A_DQ58 BB64 BT36 M_A_A0 BC67
M_A_DQ59 SA_DQ[58] SA_MA[0] M_A_A1 SB_DQ[59]
BB66 SA_DQ[59] SA_MA[1] BP33 BK70 SB_DQ[60]
M_A_DQ60 BJ66 BV36 M_A_A2 BK67
M_A_DQ61 SA_DQ[60] SA_MA[2] M_A_A3 SB_DQ[61]
BF65 SA_DQ[61] SA_MA[3] BG34 BD71 SB_DQ[62]
M_A_DQ62 AY64 BG32 M_A_A4 BD69 BT34
M_A_DQ63 SA_DQ[62] SA_MA[4] M_A_A5 SB_DQ[63] SB_MA[0]
BC70 SA_DQ[63] SA_MA[5] BN32 SB_MA[1] BP30
BK32 M_A_A6 BV29
SA_MA[6] M_A_A7 SB_MA[2]
SA_MA[7] BJ30 SB_MA[3] BU30
BN30 M_A_A8 BV31
SA_MA[8] M_A_A9 SB_MA[4]
13 M_A_BS0 BT38 SA_BS[0] SA_MA[9] BF28 BV43 SB_BS[0] SB_MA[5] BT33
13 M_A_BS1 BH38 BH34 M_A_A10 BV41 BT31
SA_BS[1] SA_MA[10] M_A_A11 SB_BS[1] SB_MA[6]
13 M_A_BS2 BF21 SA_BS[2] SA_MA[11] BH30 BV24 SB_BS[2] SB_MA[7] BP26
BJ28 M_A_A12 BV27
B SA_MA[12] M_A_A13 SB_MA[8] B
SA_MA[13] BF40 SB_MA[9] BT27
BN28 M_A_A14 BU46 BU42
SA_MA[14] M_A_A15 SB_CAS# SB_MA[10]
13 M_A_CAS# BK43 SA_CAS# SA_MA[15] BN25 BT40 SB_RAS# SB_MA[11] BU26
13 M_A_RAS# BL38 SA_RAS# BT41 SB_WE# SB_MA[12] BT29
13 M_A_WE# BF38 SA_WE# SB_MA[13] BT45
SB_MA[14] BV26
SB_MA[15] BU23
ARD_BGA_r1p0
ARD_BGA_r1p0
A A

5th floor,Block K,
Title <Title>
Size Sheet Rev
CPU2
C Name A
5 4 3 2 1
10 9 8 7 6 5 4 3 2 1
U2J U2I
VSS90 AY24
AH53 A40 BU62 AY23
J J
VSS202 VSS404 VSS1 VSS91
AH51 VSS203 VSS405 A36 BU58 VSS2 VSS92 AY21
AH37 VSS211 VSS413 A8 BU21 VSS10 VSS100 AW67
AH35 VSS212 VSS393 B62 BU18 VSS11 VSS101 AW62
U2E AH30 B51 BU7 AW51
AH28 VSS216 VSS397 B48 BP42 VSS15 VSS105 AW48
RSVD32 W66 AH26 VSS217 VSS398 B44 BN64 VSS16 VSS106 AW44
I RSVD33 W64 AH24

AH23
VSS218
VSS219
VSS399
VSS400
A59
A55
BN6
BM70
VSS17
VSS18
VSS107
VSS108
AW41
AW37 I
AH21 VSS220 VSS401 A52 BM51 VSS19 VSS109 AV9
RSVD34 AC69 AH19 VSS221 VSS402 A48 BM44 VSS20 VSS110 AV1
RSVD35 AC71 AH17 VSS222 VSS403 A45 BM32 VSS21 VSS111 AU70
AH15 VSS223 VSS288 AA17 BM24 VSS22 VSS112 AU62
RSVD36 AA71 AH4 VSS224 VSS289 AA15 BM17 VSS23 VSS113 AU57
RSVD37 AA69 AG64 VSS225 VSS290 AA14 BL57 VSS24 VSS114 AU53
AG9 VSS226 VSS291 AA4 BL55 VSS25 VSS115 AU50
R71 3.01K ±1% RC0603N POP = NA CFG0 AL4 CFG[0] RSVD38 R66 AG6 VSS227 VSS292 W69 BL48 VSS26 VSS116 AU46
AM2 CFG[1] RSVD39 R64 AF69 VSS228 VSS293 W62 BL40 VSS27 VSS117 AU42
AK1 CFG[2] AF62 VSS229 VSS294 W57 BL28 VSS28 VSS118 AU39
R72 3.01K ±1% RC0603N POP = NA CFG3 AK2 AF1 W53 BL20 AU35
R73 3.01K ±1% RC0603N POP = NA CFG4 CFG[3] VSS230 VSS295 VSS29 VSS119
AK4 CFG[4] AE70 VSS231 VSS296 W50 BK63 VSS30 VSS120 AU33
AJ2 R1095 POP = NA
CFG[5] RSVD_NCTF[3] BT5 AE64 VSS232 VSS297 W46 BK60 VSS31 VSS121 AU32
H H
AT2 BR5 0 RC0402N AD62 W42 BK53 AU30
CFG[6] RSVD_NCTF[4] VSS233 VSS298 VSS32 VSS122
AG7 CFG[7] AD57 VSS234 VSS299 W6 BK34 VSS33 VSS123 AU28
AF4 R1096 POP = NA
CFG[8] RSVD_NCTF[2] BV6 0 RC0402N
AD53 VSS235 VSS300 W1 BK10 VSS34 VSS124 AU26
AG2 CFG[9] RSVD_NCTF[1] BV8 AD50 VSS236 VSS301 V70 BJ64 VSS35 VSS125 AU24
AH1 AD46 U64 BJ21 AU23
AC2
AC4
CFG[10]
CFG[11]
CFG[12]
RSVD45
RSVD46
AV69
AK71
AD42
AD4
VSS237
VSS238
VSS239
VSS VSS302
VSS303
VSS304
U62
U57
BJ9
BJ1
VSS36
VSS37
VSS38 VSS
VSS126
VSS127
VSS128
AU21
AU19
AE2 CFG[13] RSVD47 AN69 AC67 VSS240 VSS305 U53 BH70 VSS39 VSS129 AU17
AD1 CFG[14] RSVD48 AP66 AC64 VSS241 VSS306 U50 BH57 VSS40 VSS130 AU15
AF8 CFG[15] RSVD49 AH66 AC10 VSS242 VSS307 U46 BH55 VSS41 VSS131 AU14
AF6 CFG[16] RSVD50 AK66 AC5 VSS243 VSS308 U42 BH47 VSS42 VSS132 AU4
AB7 CFG[17] RSVD51 AR71 AC1 VSS244 VSS309 U39 BH24 VSS43 VSS133 AT64
RSVD52 AM66 AB70 VSS245 VSS310 U9 BH20 VSS44 VSS134 AT10
RSVD53 AK69 AB62 VSS246 VSS311 U4 BH15 VSS45 VSS135 AR62
RSVD54 AU71 AB57 VSS247 VSS312 T1 BG51 VSS46 VSS136 AR57
G RSVD55 AT70
G
AB53 VSS248 VSS313 R70 BG36 VSS47 VSS137 AR53
RSVD56 AR69 AB50 VSS249 VSS314 R62 BF62 VSS48 VSS138 AR50
RSVD57 AU69 AB46 VSS250 VSS315 R57 BF30 VSS49 VSS139 AR46
RESERVED
RSVD58 AT67 AB42 VSS251 VSS316 R53 BF13 VSS50 VSS161 AN51
AB39 VSS252 VSS317 R50 BF8 VSS51 VSS162 AN48
AU1 RSVD_TP[0] RSVD_TP[2] AP2 AB37 VSS253 VSS318 R46 BE70 VSS52 VSS163 AN44
RSVD_TP[1] AN7 AB35 VSS254 VSS319 R42 BE65 VSS53 VSS164 AN41
AB33 VSS255 VSS320 R5 BE9 VSS54 VSS165 AN37
T4 RSVD15 RSVD62 AV4 AB32 VSS256 VSS321 P4 BE1 VSS55 VSS166 AN5
T2 RSVD16 RSVD63 AU2 AB30 VSS257 VSS322 N63 BD57 VSS56 VSS167 AN4
AB28 VSS258 VSS323 N57 BD53 VSS57 VSS168 AM64
U1 RSVD17 RSVD64 BE69 AB26 VSS259 VSS324 N53 BD50 VSS58 VSS169 AM8
V2 RSVD18 RSVD65 BE71 AB24 VSS260 VSS325 N50 BD46 VSS59 VSS170 AL62
AB23 VSS261 VSS326 N46 BD42 VSS60 VSS171 AL55
AV71 RSVD19 AB21 VSS262 VSS327 N30 BD39 VSS61 VSS172 AL51
AW70 AB19 N21 BD14 AL48
F AY69
RSVD20
RSVD21
DC_TEST_BV71 BV71
DC_TEST_BV69 BV69
AB17
AB15
VSS263
VSS264
VSS265
VSS328
VSS329
VSS330
N15
M53
BB71
BB62
VSS62
VSS63
VSS64
VSS173
VSS174
VSS175
AL44
AL41
F
BB69 RSVD22 DC_TEST_BV68 BV68 AB14 VSS266 VSS331 M42 BB57 VSS65 VSS176 AL37
DC_TEST_BV5 BV5 AB9 VSS267 VSS332 M36 BB53 VSS66 VSS177 AL35
D8 RSVD23 DC_TEST_BV3 BV3 AA66 VSS268 VSS333 M1 BB50 VSS67 VSS178 AL33
B7 RSVD24 DC_TEST_BV1 BV1 AA64 VSS269 VSS334 L70 BB46 VSS68 VSS179 AL1
DC_TEST_BT71 BT71 AA62 VSS270 VSS335 L57 BB42 VSS69 VSS180 AK70
A10 RSVD26 DC_TEST_BT69 BT69 AA57 VSS271 VSS336 L48 BB39 VSS70 VSS181 AK64
B9 RSVD27 DC_TEST_BT3 BT3 AA53 VSS272 VSS337 L47 BB7 VSS71 VSS182 AK55
DC_TEST_BT1 BT1 AA50 VSS273 VSS338 L13 BB1 VSS72 VSS183 AK51
C5 RSVD_NCTF[7] DC_TEST_BR71 BR71 AA46 VSS274 VSS339 K64 BA70 VSS73 VSS184 AK48
A6 RSVD_NCTF[8] DC_TEST_BR1 BR1 AA42 VSS275 VSS340 K53 AY71 VSS74 VSS185 AK44
DC_TEST_E71 E71 AA39 VSS276 VSS341 K43 AY66 VSS75 VSS186 AK41
E3 RSVD_NCTF[6] DC_TEST_E1 E1 AA37 VSS277 VSS342 K36 AY62 VSS76 VSS187 AK37
F1 C71 AA35 K34 AY59 AK32
E RSVD_NCTF[5] DC_TEST_C71
DC_TEST_C69
DC_TEST_C3
C69
C3
AA33
AA32
VSS278
VSS279
VSS280
VSS343
VSS344
VSS345
K32
K25
AY55
AY51
VSS77
VSS78
VSS79
VSS188
VSS189
VSS190
AK30
AK28
E
DC_TEST_A71 A71 AA30 VSS281 VSS346 K17 AY48 VSS80 VSS191 AK26
DC_TEST_A69 A69 AA28 VSS282 VSS347 K11 AR42 VSS140 VSS192 AK24
AA23 VSS285 VSS350 J65 AR33 VSS143 VSS195 AK19
AA21 VSS286 VSS351 J57 AR32 VSS144 VSS196 AK17
ARD_BGA_r1p0 AA19 J48 AR30 AK15
F20 VSS374 VSS353 J47 AR28 VSS146 VSS198 AJ70
F4 VSS375 VSS354 J40 AR26 VSS147 VSS199 AH62
E37 VSS376 VSS355 J9 AR24 VSS148 VSS200 AH57
E33 VSS377 VSS356 H53 AR23 VSS149 VSS201 AH55
E30 VSS378 VSS357 H43 AR21 VSS150 VSS202 BV66
E16 VSS379 VSS358 H36 AR19 VSS151 VSS203 BV64
D E12
D41
VSS380
VSS381
VSS359
VSS360
H1
G70
AR17
AR15
VSS152
VSS153
VSS204
VSS205
BT68
BR69 D
D38 VSS382 VSS361 G57 AR14 VSS154 VSS206 BR68
D34 VSS383 VSS362 G53 AR4 VSS155 VSS207 BR3
D31 VSS384 VSS363 G48 AR1 VSS156 VSS208 BN71
D27 VSS385 VSS364 G47 AP70 VSS157 VSS209 BN1
Layout Note: D24 VSS386 VSS365 G43 AP64 VSS158 VSS210 BL71
D20 G30 AN62 BL1
VSS_NCTF3,4,5 should be routed as trace D17
VSS387 VSS366
G24 AN55
VSS159 VSS211
R14
and not as a GND plane. D13 VSS389 VSS368 G20 AY44 VSS81 VSS213 H71
D10 VSS390 VSS369 G15 AY41 VSS82 VSS214 F71
D6 VSS391 VSS370 F61 AY37 VSS83 VSS215 E69
B65 VSS392 VSS371 F48 AY35 VSS84 VSS216 E68
RC0402N 0 R78 ISENSEN_NCB40 F47 AY33 A66
VSS373 F28 AY32 VSS86 VSS218 A64
C ARD_BGA_r1p0
AY30
AY28
AY26
VSS87
VSS88
VSS219
VSS220
E5
C68 C
VSS89
ARD_BGA_r1p0
VSS (AP34) can be left NC is

CRB implementation; EDS/DG
B recommendation to GND
B

5th floor,Block K,
A Title <Title>
A
Size Sheet Rev
CPU1
C Name A
10 9 8 7 6 5 4 3 2 1
U2H +VCC_CORE
+VCC0 AF57
J J
VCC_1 +V1.1S_VCCTT +V1.1S_VTT
VCC_2 AF55
VCC_3 AF53
AF51 U2F
+VCC_CORE VCC_4
BD55 VCAP0_1 VCC_5 AF50
BD51 VCAP0_2 VCC_6 AF48 VTT0_11 AW14
BD48 VCAP0_3 VCC_7 AF46 10 PSI# VTT0_12 AW12
BB55 VCAP0_4 VCC_8 AF44 VTT0_13 AU60
BB51 AF42 AU59 C60 C61 C62 C63 C64 C65
VCAP0_5 VCC_9 TP17 VTT0_14
C430 C431 C434 C435 BB48 AF41 F68 AU12 10uF 10uF 10uF 10uF 10uF 10uF
10uF 10uF 10uF 10uF VCAP0_6 VCC_10 PSI# VTT0_15 CC0603N CC0603N CC0603N CC0603N CC0805N CC0805N
AY57 VCAP0_7 VCC_11 AD55 41 H_VID[0..6] VTT0_16 AR60
CC0805N CC0805N CC0805N CC0805N AY53 AD51 H_VID0 A61 AR59
VCAP0_8 VCC_12 H_VID1 VID[0] VTT0_17
CPU VIDS
AY50 AD48 +V1.1S_VTT D61 AR12
POP = NA VCAP0_9 VCC_13 H_VID2 VID[1] VTT0_18
AW57 VCAP0_10 VCC_14 AD44 D62 VID[2] VTT0_19 AN60
ccq,evt->dvt,0625 AW53 AD41 ccq,dvt->pvt,1008 H_VID3 A62 AN59 ccq,evt->dvt,0625
VCAP0_11 VCC_15 R594 H_VID4 VID[3] VTT0_20 C562
AW50 VCAP0_12 VCC_16 AB55 B63 VID[4] VTT0_21 AN35
I I
1k
Place under cavity AU55 VCAP0_13 VCC_17 AB51
RC0402N
H_VID5
H_VID6
D64 VID[5] VTT0_22 AN33 10uF
AU51 AB48 D66 AN17 CC0805N
+VCC_CORE VCAP0_14 VCC_18 POP = NA VID[6] VTT0_23
AU48 VCAP0_15 VCC_19 AB44 VTT0_24 AN15
AR55 VCAP0_16 VCC_20 AB41 TP15 AN1 VTT_SELECT[1] VTT0_25 AN14
AR51 VCAP0_17 VCC_21 AA55 VTT0_26 AN12
AR48 AA51 41 PM_DPRSLPVR RC0402N 0 R81 F66 AM10
24X 1uF 0402 VCAP0_18 VCC_22 PROC_DPRSLPVR VTT0_27
AN57 VCAP0_19 VCC_23 AA48 VTT0_28 AL60
3X 22uF 0805 AN53 AA44 AL59
VCAP0_20 VCC_24 VTT0_29
C424
10uF
C425
10uF
C426
22uF
17X 10uF 0805
3X 470uF 4mOhms
AN50
AL57
VCAP0_21 POWER VCC_25 AA41
W55 +VCC_CORE VTT0_30 AL17
AL15
1.1V RAIL POWER

CC0805N CC0805N CC0805N VCAP0_22 VCC_26 VTT0_31
AL53 VCAP0_23 VCC_27 W51 VTT0_32 AL14
POP = NA AL50 W48 41 IMVP_IMON A41 AL12
6.3V VCAP0_24 VCC_28 R82 ISENSE VTT0_33
AK57 VCAP0_25 VCC_29 W44 VTT0_34 AK35
ccq,evt->dvt,0625 AK53 W41 ±1% 100 AK33
SENSE LINES
AK50 U55 RC0402N AF39
H VCC_32
VCC_33
U51
U48
U44 F64
VTT0_37
VTT0_38
AF37
AF35
AF33
H
VCC_34 41 VCCSENSE VCC_SENSE VTT0_39
CPU CORE SUPPLY VCC_35 U41 41 VSSSENSE F63 VSS_SENSE VTT0_40 AF32
VCC_36 R55 VTT0_41 AF30
VCC_37 R51 VTT0_42 AD39
+VCC_CORE R48 R85 39 VTT_SENSE N13 BF60
VCC_38 ±1% 100 VTT_SENSE VTT0_1
VCC_39 R44 VTT0_2 BF59
R41 RC0402N R12 BD60
VCC_40 TP5 VSS_SENSE_VTT VTT0_3
+VCC1 P60 BD59
VCC_41 VTT0_4
VCC_42 N55 VTT0_5 BB60
C438 C439 C440 C441 C442 C443 C444 N51 BB59
10uF 10uF 10uF 10uF 10uF 10uF 10uF VCC_43 VTT0_6
VCC_44 N48 VTT0_7 AY60
CC0805N CC0805N CC0805N CC0805N CC0805N CC0805N CC0805N BD44 VCAP1_1 VCC_45 N44 Place near the processor VTT0_8 AW60
BD41 VCAP1_2 VCC_46 N42 VTT0_9 AW35
POP = NA POP = NA
G G
BD37 VCAP1_3 VCC_47 M60 VTT0_10 AW33
BB44 VCAP1_4 VCC_48 M51 VTT0_43 AD37
BB41 VCAP1_5 VCC_49 M44 VTT0_44 AD35
Place under cavity ccq,evt->dvt,0625 BB37 L55 AD33
AY46 VCAP1_7 VCC_51 K60 VTT0_46 AD32
AY42 VCAP1_8 VCC_52 K51 VTT0_47 AD30
AY39 K44 +V1.8S +V1.8S_VCCSFR W35
POWER
AW46 VCAP1_10 VCC_54 J55 VTT0_49 W33
AW42 VCAP1_11 VCC_55 H60 W39 VCCPLL1 VTT0_50 W32
1.8V
AW39 VCAP1_12 VCC_56 H51 W37 VCCPLL2 VTT0_51 W30
AU44 H44 C68 C69 U37 W28
VCAP1_13 VCC_57 10uF 10uF VCCPLL3 VTT0_52
AU41 VCAP1_14 VCC_58 G60 R39 VCCPLL4 VTT0_53 W26
AU37 VCAP1_15 VCC_59 G55 CC0805N CC0805N R37 VCCPLL5 VTT0_54 W24 The decoupling capacitors, filter
ccq,evt->dvt,0625 AR44 G51 W23
VCAP1_16 VCC_60 VTT0_55 recommendations and sense resistors on the
+VCC_CORE AR41 G44 U35
AR37
VCAP1_17 VCC_61
F55
VTT0_56
U33
CPU/PCH Rails are specific to the CRB
F AN46
AN42
VCAP1_18
VCAP1_19
VCAP1_20
VCC_62
VCC_63
VCC_64
E60
E57
VTT0_57
VTT0_58
VTT0_59
U32
U30
Implementation. Customers need to follow the
recommendations in the Calpella Platform F
AN39 VCAP1_21 VCC_65 E53 VTT0_60 U28 Design Guide
C445 C446 C447 C448 C449 C450 C451 AL46 E50 U26
10uF 10uF 10uF 10uF 10uF 10uF 10uF VCAP1_22 VCC_66 VTT0_61
AL42 VCAP1_23 VCC_67 E46 VTT0_62 U24
CC0805N CC0805N CC0805N CC0805N CC0805N CC0805N CC0805N AL39 E42 U23
AK46 VCAP1_25 VCC_69 D59 VTT0_64 R35
POP = NA POP = NA POP = NA AK42 D57 R33
VCAP1_26 VCC_70 +V1.5M POP = NA +VCCDDR_CLK VTT0_65
AK39 VCAP1_27 VCC_71 D55 VTT0_66 R32
VCC_72 D54 VTT0_67 R30
Place between inductor and socket on top layer VCC_73 D52 FB7
+V1.5M_CPU
120R BB14 VDDQ_CK[1] VTT0_68 R28
TP7
D50 FB0805N BB12 R26
VCC_74 VDDQ_CK[2] VTT0_69 +V1.1S_VTT
VCC_75 D48 VTT0_70 R24
D47 FB11 120R C350 R23
VCC_76 ccq,dvt->pvt,1008 FB0805N 1uF VTT0_71 R102 0 RC0603N
D45 AY10
E +VCC_CORE VCC_77
VCC_78
VCC_79
D43
B60
CC0402N VTT0_72
VTT0_73 AN9 R103 0 RC0603N
E
VCC_80 B56
VCC_81 B53
B49 ARD_BGA_r1p0
C325 C306 C308 C307 C309 C310 C324 C323 C329 VCC_82 TP18
VCC_83 B46
1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF B42
VCC_84
CC0402N CC0402N CC0402N CC0402N CC0402N CC0402N CC0402N CC0402N CC0402N
VCC_85 A57 VTT_SELECT
VCC_86 A54 Arrandale drives this pin High while Clarksfield drives this pin Low.
VCC_87 A50 For a common motherboard design that supports both Arrandale and Clarksfield (rPGA),
VCC_88 A47
A43 VTT_SELECT pin is used to drive FET circuitry to change VR resistor feedback combination to tune output voltage for VTT rail.
VCC_89
C327 C326 C328
1uF 1uF 1uF
D CC0402N CC0402N CC0402N ARD_BGA_r1p0

D
+V1.1S_VCCTT
C345 C331 C334 C333 C335 C342 C344 C343 C349 +VCC0
1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF C353 C352 C354 C356 C357 C355 C359
CC0402N CC0402N CC0402N CC0402N CC0402N CC0402N CC0402N CC0402N CC0402N 1uF 1uF 1uF 1uF 1uF 1uF 1uF
CC0402N CC0402N CC0402N CC0402N CC0402N CC0402N CC0402N
C239 C281 C285 C284 C287 C286 C289 C288 C293

1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF
C347 C346 C348 C360 C358 C361 C394 C413 C362 C414
C 1uF
CC0402N
1uF
CC0402N
1uF
CC0402N
1uF
CC0402N
1uF
CC0402N
1uF
CC0402N
1uF
CC0402N
1uF
CC0402N
1uF
CC0402N
1uF
CC0402N C
C291 C290 C292
1uF 1uF 1uF
CC0402N CC0402N CC0402N C452 C432 C453 C554 C555 C553 C559
1uF 1uF 1uF 1uF 1uF 1uF 1uF
+VCC1
B C301
1uF
C294
1uF
C296
1uF
C295
1uF
C297
1uF
C298
1uF
C300
1uF
C299
1uF
C305
1uF
B
C303 C302 C304

1uF 1uF 1uF Lengda Technology Ltd.
CC0402N CC0402N CC0402N
5th floor,Block K,
A Title <Title>
A
Size Sheet Rev
CPU4_Power1
C Name A
ENGINEER: Ivan Date: Thursday, October 21, 2010 Sheet 10 of 44
10 9 8 7 6 5 4 3 2 1
For S3 Power safe
+V1.5_VCCDDQ +V1.5_DIMM0
J +V1.5M +V1.5M_CPU
J
J9
JC_2
POP = NA
Q104
8 1
7 2
6 3
5
Note: AO4468
4
Layout Place See Document 425302 PG19
42 SLPS3#_CONTROL_1.5S R132 0 RC0402N
I C411
I
470pF
CC0402N
POP = NA
+VCC_GFXCORE +VGFX_CORE
U2G
AN32 VAXG1
AN30 VAXG2 VAXG_SENSE AF12 VCC_AXG_SENSE 40
H Refer to 3622164 AN28 VAXG3 VSSAXG_SENSE AF10 VSS_AXG_SENSE 40
H
SENSE
LINES
1
ccq,evt->dvt,0625 C73 C74 C75 AN26 VAXG4
+ CP1 22uF 10uF 10uF AN24
GFXVR_EN R560 4.7K±1% RC0402N 330uF CC0805N CC0603N CC0603N VAXG5
AN23 VAXG6
GFXVR_DPRSLPVR R908 10k RC0402N POP = NA CCP7343N AN21 VAXG7 GFX_VID[0..6] 40
2
AN19 AF71 GFX_VID0

VAXG8 GFX_VID[0] GFX_VID1
AL32 VAXG9 GFX_VID[1] AG67
AL30 AG70 GFX_VID2
GRAPHICS VIDs
AL28 VAXG11 GFX_VID[3] AH71
AL26 AN71 GFX_VID4
AL24 VAXG13 GFX_VID[5] AM67
GFX_VID6
GRAPHICS
AL23 VAXG14 GFX_VID[6] AM70
C560 C561 C566 C567 C569 C568 C573 AL21
1uF 1uF 1uF 1uF 1uF 1uF 1uF VAXG15
AL19 VAXG16
CC0402N CC0402N CC0402N CC0402N CC0402N CC0402N CC0402N AK14 AH69 GFXVR_EN 40
VAXG17 GFX_VR_EN
G G
AK12 VAXG18 GFX_DPRSLPVR AL71 GFXVR_DPRSLPVR 40
AJ10 AL69 GFXVR_IMON 40 +V1.5M_CPU
VAXG19 GFX_IMON
AH14 VAXG20
AH12 +V1.5_VCCDDQ
C582 C581 C587 C588 C590 C589 C591 VAXG21
AF28 VAXG22 VDDQ1 BU40
1uF 1uF 1uF 1uF 1uF 1uF 1uF AF26 BU35
VAXG23 VDDQ2
1
CC0402N CC0402N CC0402N CC0402N CC0402N CC0402N CC0402N AF24 BU28 CP3
VAXG24 VDDQ3 C76 C77 C78 C79 C80 C81 C82
AF23 BN38 + 220uF
VAXG25 VDDQ4 1uF 1uF 1uF 1uF 1uF 10uF 10uF CCP7343N
AF21 VAXG26 VDDQ5 BM25
AF19 BL30 CC0402N CC0402N CC0402N CC0402N CC0402N CC0805N CC0805N
VAXG27 VDDQ6
2
- 1.5V RAILS
AF17 VAXG28 VDDQ7 BJ38
AF15 VAXG29 VDDQ8 BH32
AF14 VAXG30 VDDQ9 BH28
AD28 BG43 ccq,evt->dvt,0625
VAXG31 VDDQ10
AD26 VAXG32 VDDQ11 BF16
AD24 BF15
F AD23
AD21
VAXG33
VAXG34
VAXG35
VDDQ12
VDDQ13
VDDQ14
BD35
BD33
F
AD19 VAXG36 VDDQ15 BD32
The decoupling capacitors, filter +V1.1S_VTT +V1.1S_VCC_PEG_DMI AD17 VAXG37 VDDQ16 BD30
recommendations and sense resistors on the VDDQ17 BD28
CPU/PCH Rails are specific to the CRB VDDQ18 BD26
W21 VTT1_1 VDDQ19 BD24
Implementation. Customers need to follow the W19 BD23
DDR3
VTT1_2 VDDQ20
recommendations in the Calpella Platform
PEG & DMI

U21 VTT1_3 VDDQ21 BD21
Design Guide C85 C86 U19 BD19
10uF 10uF VTT1_4 VDDQ22
U17 VTT1_5 VDDQ23 BD17
POWER
CC0805N CC0805N U15 BD15
VTT1_6 VDDQ24
U14 VTT1_7 VDDQ25 BB35
U12 VTT1_8 VDDQ26 BB33
R21 BB32
E C592 C593
ccq,evt->dvt,0625 R19
R17
VTT1_9
VTT1_10
VTT1_11
VDDQ27
VDDQ28
VDDQ29
BB30
BB28
E
1uF 1uF R15 BB26
CC0402N CC0402N VTT1_21 VDDQ30
VDDQ31 BB24
VDDQ32 BB23
+VCCTTG BB21
VDDQ33
VDDQ34 BB19
VDDQ35 BB17
AK62 BB15 +V1.1S_VCCTTA_DDR +V1.1S_VTT
VCAP2_1 VDDQ36
AK60 VCAP2_2
C88 C24 C95 C94 C93 AK59
1uF 1uF 1uF 1uF 1uF VCAP2_3 FB10 120R
AH60 VCAP2_4 VTT0_DDR AW32
CC0402N CC0402N CC0402N CC0402N CC0402N AH59 AW30 FB0805N
VCAP2_5 VTT0_DDR[1] C66 C67 C72
AF60 VCAP2_6 VTT0_DDR[2] AW28
AF59 AW26 1uF 1uF 1uF
VCAP2_7 VTT0_DDR[3]
D AD60
AD59
VCAP2_8
VCAP2_9
VTT0_DDR[4]
VTT0_DDR[5]
AW24
AW23
CC0402N CC0402N CC0402N
D
AB60 VCAP2_10 VTT0_DDR[6] AW21
AB59 VCAP2_11 VTT0_DDR[7] AW19
AA60 AW17 +V1.1S_VCC_SA +V1.1S_VTT
VCAP2_12 VTT0_DDR[8]
AA59 VCAP2_13 VTT0_DDR[9] AW15
W60 VCAP2_14
W59 VCAP2_15 VTT1_12 AD15
U60 VCAP2_16 VTT1_13 AD14
U59 AD12 C71 C70 C87 C90
VCAP2_17 VTT1_14 10uF 10uF 10uF 10uF
R60 VCAP2_18 VTT1_15 AB12
R59 AA12 CC0805N CC0805N CC0805N CC0805N
VCAP2_19 VTT1_16
VTT1_17 W17
W15 ccq,evt->dvt,0625
VTT1_18
VTT1_19 W14
C VTT1_20 W12
C
ARD_BGA_r1p0 C91 C25
1uF 1uF
CC0402N CC0402N
Please note that the VTT Rail

B Values are B
Arrandale VTT=1.05V;
Clarksfield VTT=1.1V

5th floor,Block K,
A Title <Title>
A
Size Sheet Rev
CPU1
C Name A
10 9 8 7 6 5 4 3 2 1
J Thermal Sensor J
+V3.3A
I C98
0.1u Place near the Hotest Air I
CC0402N
POP = NA U3 EMC1402
3
1 8 I2C1B_CLK
VDD SMCLK I2C_CLK2 34
Q118 1 R86 0 RC0402N 2 7 I2C1B_DATA
MMBT3904 DP SMDATA I2C_DATA2 34
POP = NA C99 3 6 EMC_ALERT# R122 0 RC0402N POP = NA
POP = NA 470pF DN ALERT TS#_DIMM 7,13
2 4 THERM GND 5
R88 0 RC0402N CC0402N
POP = NA POP = NA TSOP65P490-8N R87 4.7K RC0402N +V3.3A
POP = NA POP = NA
R89 0 RC0402N POP = NA

7,34 PM_EXTTS#0_EC
H +V3.3A R124 4.7K RC0402N

POP = NA
EMC_THERM# H
ccq,evt->dvt,0625
G G
CPU FAN Control

F +V3.3S
F
+V5S
R93
10k
RC0402N
R94 FB2
10k 180.0 ohm
34 KBC_FAN_SPEED RC0402N FB0603N
3
Q3
C103 1 D4 N P 1SS355TE17 sod2514n
0.1u
E CC0402N
OTRDTC144EUA R95 E
2
100
RC0402N
C100
C104 0.1u
1000pF CC0402N
CC0402N
CN11
FAN_VCC 1
FAN_BACK 1
2 2 E1 E1
R92 0 RC0603N FAN_DRV 3 E2
34 FAN_PWMIN 3 E2
D 4 4 D
U58
34 FAN_ON
FAN_VCC
1 EN GND4 8 Dual Lay
C96 2.2uF CC0603N 2 7
C97 2.2uF CC0603N FAN_DRV VIN GND3
3 VOUT GND2 6
VSET 4 5 CN24
VSET GND1
POP = NA FAN_BACK 1 E1
POP = NA APL5607 1 E1
FAN_DRV 2 E2
POP = NA 2 E2
3 3
C 34 FAN_PWMIN
R278 1k RC0603N
POP = NA
POP = NA
C
C89
1uF
CC0603N
POP = NA
B B

5th floor,Block K,
A Title <Title>
A
Size Sheet Rev
THERMAL
C Name A
ENGINEER: Ivan Date: Wednesday, October 20, 2010 Sheet 12 of 44
5 4 3 2 1
DDR3 SODIMM0
Layout Note:
Place the 0-Ω resistors close to SO-DIMM connector.
The overall routing length for both DIMM_VREF traces should be <= 5000 mils (127 mm).
D Avoid changing reference plane during the entire routing length. If reference plane has to be changed D
during the transition to 0-Ω resistors, then GND stitching vias are needed next to resistor pads.
Place GND stitching vias within 100 mils (2.54 mm) of DIMM_VREF traces close to SO-DIMM connector.
CN2A
8 M_A_A[15..0] M_A_DQ[63..0] 8
M_A_A0 98 5 M_A_DQ0
M_A_A1 A0 DQ0 M_A_DQ1
97 A1 DQ1 7
M_A_A2 96 15 M_A_DQ2 +V1.5_DIMM0
95 A3 DQ3 17 CN2B
M_A_A4 92 4 M_A_DQ4
91 A5 DQ5 6 75 VDD1 VSS16 44
M_A_A6 90 16 M_A_DQ6 76 48
M_A_A7 A6 DQ6 M_A_DQ7 VDD2 VSS17
86 A7 DQ7 18 81 VDD3 VSS18 49
M_A_A8 89 21 M_A_DQ8 82 54
85 A9 DQ9 23 87 VDD5 VSS20 55
M_A_A10 107 33 M_A_DQ10 88 60
M_A_A11 A10/AP DQ10 M_A_DQ11 VDD6 VSS21
84 A11 DQ11 35 93 VDD7 VSS22 61
M_A_A12 83 22 M_A_DQ12 94 65
M_A_A13 A12/BC# DQ12 M_A_DQ13 VDD8 VSS23
119 A13 DQ13 24 99 VDD9 VSS24 66
M_A_A14 80 34 M_A_DQ14 100 71
78 A15 DQ15 36 105 VDD11 VSS26 72
39 M_A_DQ16 106 127
DQ16 M_A_DQ17 +V3.3S VDD12 VSS27
8 M_A_BS0 109 BA0 DQ17 41 111 VDD13 VSS28 128
Note: 8 M_A_BS1 108 BA1 DQ18 51 M_A_DQ18 112 VDD14 VSS29 133
If SA0_DIM0 = 0, SA1_DIM0 = 0 79 53 M_A_DQ19 117 134
8 M_A_BS2 BA2 DQ19 VDD15 VSS30
M_CS#0 114 40 M_A_DQ20 118 138
SO-DIMMA SPD Address is 0xA0 8 M_CS#0
M_CS#1 121
S0# DQ20
42 M_A_DQ21 123
VDD16 VSS31
139
SO-DIMMA TS Address is 0x30 8 M_CS#1 S1# DQ21 VDD17 VSS32
M_CLK_DDR0 101 50 M_A_DQ22 C105 C106 124 144
8 M_CLK_DDR0 CK0 DQ22 VDD18 VSS33
If SA0_DIM0 = 1, SA1_DIM0 = 0 8 M_CLK_DDR#0
M_CLK_DDR#0 103 CK0# DQ23 52 M_A_DQ23 0.1u 2.2uF
VSS34 145
SO-DIMMA SPD Address is 0xA2 M_CLK_DDR1 102 57 M_A_DQ24 CC0402N CC0603N 199 150
8 M_CLK_DDR1 CK1 DQ24 +V1.5_DIMM0 VDDSPD VSS35
M_CLK_DDR#1 104 59 M_A_DQ25 151
SO-DIMMA TS Address is 0x32 8 M_CLK_DDR#1
M_CKE0 73
CK1# DQ25
67 M_A_DQ26 77
VSS36
155
8 M_CKE0 CKE0 DQ26 NC1 VSS37
M_CKE1 74 69 M_A_DQ27 122 156
8 M_CKE1 CKE1 DQ27 NC2 VSS38
C M_A_CAS# 115 56 M_A_DQ28 125 161 C
8 M_A_CAS# CAS# DQ28 NCTEST VSS39
M_A_RAS# 110 58 M_A_DQ29 R97 162
8 M_A_RAS# RAS# DQ29 VSS40
+V3.3S R96 10k RC0402N POP = NA M_A_WE# 113 68 M_A_DQ30 1K±1% 7,12 TS#_DIMM 198 167
8 M_A_WE# WE# DQ30 EVENT# VSS41
R98 10k RC0402N SA0_DIM0 197 70 M_A_DQ31 RC0402N 30 168
SA0 DQ31 7 DDR3_DRAMRST# RESET# VSS42
R99 10k RC0402N SA1_DIM0 201 129 M_A_DQ32 172
SMB_CLK_S2 SA1 DQ32 M_A_DQ33 R101 0 RC0402N POP = NA VREF_DQ0 VSS43
6,16,29,30 SMB_CLK_S2 202 SCL DQ33 131 1 VREF_DQ VSS44 173
SMB_DATA_S2 200 141 M_A_DQ34 126 178
6,16,29,30 SMB_DATA_S2 SDA DQ34 VREF_CA VSS45
143 M_A_DQ35 C107 C108 179
M_ODT0 DQ35 M_A_DQ36 R100 0.1u 2.2uF VSS46
8 M_ODT0 116 ODT0 DQ36 130 2 VSS1 VSS47 184
M_ODT1 120 132 M_A_DQ37 1K±1% CC0402N CC0603N 3 185
8 M_ODT1 ODT1 DQ37 VSS2 VSS48
140 M_A_DQ38 RC0402N 8 189
8 M_A_DM[7..0] DQ38 VSS3 VSS49
M_A_DM0 11 142 M_A_DQ39 9 190
M_A_DM1 DM0 DQ39 M_A_DQ40 VSS4 VSS50
28 DM1 DQ40 147 13 VSS5 VSS51 195
M_A_DM2 46 149 M_A_DQ41 R1071 14 196
M_A_DM3 DM2 DQ41 M_A_DQ42 VSS6 VSS52
63 DM3 DQ42 157 0 19 VSS7
M_A_DM4 136 159 M_A_DQ43 RC0402N 20 +V0.75M
M_A_DM5 DM4 DQ43 M_A_DQ44 POP = NA VSS8
153 DM5 DQ44 146 25 VSS9
M_A_DM6 170 148 M_A_DQ45 26 203
M_A_DM7 DM6 DQ45 M_A_DQ46 VSS10 VTT1
187 DM7 DQ46 158 31 VSS11 VTT2 204
160 M_A_DQ47 32
8 M_A_DQS[7..0] DQ47 VSS12
M_A_DQS0 12 163 M_A_DQ48 37
M_A_DQS1 DQS0 DQ48 M_A_DQ49 VSS13
29 DQS1 DQ49 165 38 M_VREF 38 VSS14 E1 E1
M_A_DQS2 47 175 M_A_DQ50 43 E2
M_A_DQS3 DQS2 DQ50 M_A_DQ51 VSS15 E2
64 DQS3 DQ51 177
M_A_DQS4 137 164 M_A_DQ52 C109 C110
M_A_DQS5 DQS4 DQ52 M_A_DQ53 0.1u 2.2uF
154 DQS5 DQ53 166
M_A_DQS6 171 174 M_A_DQ54 CC0402N CC0603N 0706A1BA40E
M_A_DQS7 DQS6 DQ54 M_A_DQ55
8 M_A_DQS#[7..0] 188 DQS7 DQ55 176
M_A_DQS#0 10 181 M_A_DQ56
M_A_DQS#1 DQS#0 DQ56 M_A_DQ57
27 DQS#1 DQ57 183
M_A_DQS#2 45 191 M_A_DQ58
62 DQS#3 DQ59 193
M_A_DQS#4 135 180 M_A_DQ60
152 DQS#5 DQ61 182
M_A_DQS#6 169 192 M_A_DQ62
186 DQS#7 DQ63 194
+V1.5M +V1.5_DIMM0 +V1.5_DIMM0
B B
0706A1BA40E
1
CP4 C115 C116 C117 C118 C119 C120 C111 C112 C113 C114
+ 220uF 10uF 10uF 10uF 10uF 10uF 10uF 0.1u 0.1u 0.1u 0.1u
CCP7343N CC0603N CC0603N CC0603N CC0603N CC0603N CC0603N CC0402N CC0402N CC0402N CC0402N
2
Note: Place close to SODIMM Note:
Layout Place See Document 425302 PG19
+V0.75M
+V0.75M
C121 C122 C123 C124 C125

1uF 1uF 1uF 1uF 10uF
CC0402N CC0402N CC0402N CC0402N CC0805N
Note:
Place between the two DIMMs
A A

5th floor,Block K,
Title <Title>
Size Sheet Rev
DDR3_SODIMM0
C Name A
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

5th floor,Block K,
Title <Title>
Size Sheet Rev
DDR3_SODIMM1
C Name A
5 4 3 2 1
5 4 3 2 1
C146 12pF CC0402N

OSC120P150X670-4L
D +V3.3A +V3.3A_RTC 32.768KHz D
RTCRST# requeres 18-25ms
4
X2
D5
P N
delay. R107
10M
3 2
Use the RC circuit delay the RC0402N
1
BAT54WS-7-F C147
SOD1713N 1uF signal .
CC0603N
C148 12pF CC0402N
ccq,evt->dvt,0625
D6
CN4
E1 E1 1 R108 1k RC0402N P N R109 20K ±1% RC0402N
1
BAT54WS-7-F
E2 2 SOD1713N C149
E2 2 R110 20K ±1% RC0402N 1uF U4A
CC0603N
LPC_AD[3..0] 34
RTC_X1 B13 D33 LPC_AD0
C150 RTC_X2 RTCX1 FWH0 / LAD0 LPC_AD1
D13 RTCX2 FWH1 / LAD1 B33
1uF C32 LPC_AD2
CC0603N FWH2 / LAD2 LPC_AD3
FWH3 / LAD3 A32
RTC_RST# C14 +V3.3S
RTCRST#
FWH4 / LFRAME# C34 LPC_FRAME# 34
INTVRMEN- Integrated SUS SRTC_RST# D17 SRTCRST#
1.1V VRM Enable A34 PCH_DRQ#0 R128 10k RC0402N POP = NA
LDRQ0#
RTC
LPC
R112 1M RC0402N SM_INTRUDER# A16 F34 PCH_DRQ#1 R180 10k RC0402N POP = NA
High - Enable Internal VRs INTRUDER# LDRQ1# / GPIO23
R111 330K RC0402N PCH_INTVRMEN A14 AB9 INT_SERIRQ
INTVRMEN SERIRQ INT_SERIRQ 34
R123 10k RC0402N
R113 33 RC0402N BCLK A30

26 HDA_BITCLK HDA_BCLK
NO REBOOT STRAP R115 33 RC0402N SYNC D29
SATA0RXN AK7
AK6
+V3.3S 26 HDA_SYNC HDA_SYNC SATA0RXP
SATA0TXN AK11
PCH_SPKR P1 AK9
SPKR SATA0TXP
C R121 10k RC0402N PCH_SPKR R118 33 RC0402N C30 C
POP = NA 26 HDA_RST# HDA_RST#
SATA1RXN AH6 SATA_RXN0 31
SATA1RXP AH5 SATA_RXP0 31
Disabled when LOW DEFAULT 26 HDA_SDATAIN0 G30 HDA_SDIN0 SATA1TXN AH9 C153 0.01uF CC0402N
SATA_TXN0 31
Enabled when HIGH AH8 C154 0.01uF CC0402N
SATA1TXP SATA_TXP0 31
F30 HDA_SDIN1
SATA2RXN AF11
E32 HDA_SDIN2 SATA2RXP AF9
IHDA
SATA2TXN AF7
F32 HDA_SDIN3 SATA2TXP AF6
SATA3RXN AH3
26 HDA_SDATAOUT
R126 33 RC0402N HDA_SDOUT B29 HDA_SDO SATA3RXP AH1 PCH-HM55 are disabled SATA Ports 2&3
Q77 AF3
R1116 8.2K RC0402N POP = NA SATA3TXN
+V3.3S SATA3TXP AF1
2 3 R235 1k RC0402N H32
S D HDA_DOCK_EN# / GPIO33
SATA
SATA4RXN AD9
G
J30 HDA_DOCK_RST# / GPIO13 SATA4RXP AD8

2N7002LT1 AD6
SATA4TXN
1
SATA4TXP AD5
34 ME_FLASH R870 1k RC0402N R131 51 RC0402N M3 AD3

JTAG_TCK SATA5RXN
SATA5RXP AD1
R134 100 ±1% RC0402N POP = NA JTAG_TMS K3 AB3
JTAG_TMS SATA5TXN
SATA5TXP AB1
R137 100 ±1% RC0402N POP = NA JTAG_TDI K1 JTAG_TDI
JTAG
R139 100 ±1% RC0402N POP = NA JTAG_TDO J2 AF16 +V1.1S_VCC_SATA
JTAG_TDO SATAICOMPO
R141 100 ±1% RC0402N POP = NA JTAG_RST# J4 AF15 R142 37.4 ±1% RC0603N
TRST# SATAICOMPI
+V3.3A
SPI_CLK BA2
34 SPI_SCK SPI_CLK
R133 200 ±1% RC0402N JTAG_TMS
SPI_CS0# AV3 R143 10k RC0402N +V3.3S
34 SPI_SCE# SPI_CS0#
R136 200 ±1% RC0402N JTAG_TDI
B
AY3 SPI_CS1# SATALED# T3 SATA_LED# 32 B
R138 200 ±1% RC0402N JTAG_TDO +V3.3S R231 8.2K RC0402N POP = NA
R140 20K RC0402N JTAG_RST# SPI_SI AY1 Y9 R144 10k RC0402N +V3.3S
34 SPI_MOSI SPI_MOSI SATA0GP / GPIO21
SPI
SPI_SO AV1 V1 R145 10k RC0402N
34 SPI_MISO SPI_MISO SATA1GP / GPIO19
IBX-M_BGA1071_R1P5
SPI_MOSI:
+V3.3S
To enable Intel TPM (Intel Trusted Platform Module),
a pull-up on the PCH SPI_MOSI pin to V3.3M rail is required.
+V3.3S
R491
R490 3.3K
3.3K U21 MX25L3205D RC0402N
RC0402N SPI_CS0# 1 8
SPI_SO CS# VCC
2 SO/SIO1 HOLD# 7
3 6 SPI_CLK
WP#/ACC SCLK SPI_SI
4 GND SI/SIO0 5
SOIC127P800-8N
ME Flash
NOTE:
SPI_CLK & SPI_MOSI must be length matched to within 500 mils (12.7 mm).
SPI_CLK & SPI_CS0# must be length matched to within 500 mils (12.7 mm).
A A

5th floor,Block K,
Title <Title>
Size Sheet Rev
PCH1
C Name A
ENGINEER: Ivan Date: Wednesday, November 24, 2010 Sheet 15 of 44
5 4 3 2 1
5 4 3 2 1
+V3.3A +V3.3S
D +V3.3A D
U4B
R149 R150 R151 R152 Value of pull-up resistors
2.2K 2.2K Q4 10k 10k determined by line load.
1
BG30 B9 R148 10k RC0402N RC0402N RC0402N 2N7002LT1 RC0402N RC0402N
29 PCIE_RXN1_WLAN PERN1 SMBALERT# / GPIO11
BJ30 SOT95P240-3N
G
29 PCIE_RXP1_WLAN PERP1
C156 0.1u CC0402N BF29 H14 SMB_CLK 3 2
29 PCIE_TXN1_WLAN PETN1 SMBCLK D S SMB_CLK_S2 6,13,29,30
C157 0.1u CC0402N BH29
29 PCIE_TXP1_WLAN PETP1
1
C8 SMB_DATA Q5
SMBDATA 2N7002LT1
AW30
G
30 PCIE_RXN2_3G PERN2
30 PCIE_RXP2_3G BA30 PERP2 3 D S 2 SOT95P240-3N SMB_DATA_S2 6,13,29,30
C158 0.1u CC0402N BC30 J14 R153 10k RC0402N +V3.3A
30 PCIE_TXN2_3G C159 0.1u CC0402N PETN2 SML0ALERT# / GPIO60
30 PCIE_TXP2_3G BD30 PETP2
C6 R154 2.2K RC0402N
SML0CLK
25 PCIE_RXN3_LAN AU30
SMBus
PERN3 R155 2.2K RC0402N
25 PCIE_RXP3_LAN AT30 PERP3 SML0DATA G8
C160 0.1u CC0402N AU32
25 PCIE_TXN3_LAN C363 0.1u CC0402N PETN3
25 PCIE_TXP3_LAN AV32 PETP3
M14 R156 10k RC0402N
SML1ALERT# / GPIO74 R158 2.2K RC0402N
BA32 PERN4
BB32 PERP4 SML1CLK / GPIO58 E10 I2C_CLK1 34
BD32 PETN4
BE32 PETP4 SML1DATA / GPIO75 G12 I2C_DATA1 34
R157 2.2K RC0402N +V3.3A
PCI-E*
BF33 PERN5
BH33 PERP5 CL_CLK1 T13
Controller
BG32 PETN5
BJ32 PETP5 CL_DATA1 T11
Link
BA34 PERN6 CL_RST1# T9
AW34 PERP6
BC34 PETN6
BD34 PETP6
H1 R386 10k RC0402N
PEG_A_CLKRQ# / GPIO47
AT34 PERN7
AU34 PERP7
AU36 AD43 R159 0 RC0402N POP = NA
PETN7 CLKOUT_PEG_A_N R160 0 RC0402N POP = NA
AV36 PETP7 CLKOUT_PEG_A_P AD45
C PCH-HM55 are disabled PCIE Ports 7&8 C
BG34 PERN8 CLKOUT_DMI_N AN4 CLK_EXP_N 7
PEG
BJ34 PERP8 CLKOUT_DMI_P AN2 CLK_EXP_P 7
BG36 PETN8
BJ36 PETP8
CLKOUT_DP_N / CLKOUT_BCLK1_N AT1 CLK_DP_N 7
CLKOUT_DP_P / CLKOUT_BCLK1_P AT3 CLK_DP_P 7
AK48 CLKOUT_PCIE0N
AK47 CLKOUT_PCIE0P
From CLK BUFFER

CLKIN_DMI_N AW24 CLK_BUF_EXP_N 6
+V3.3A R161 10k RC0402N P9 BA24
PCIECLKRQ0# / GPIO73 CLKIN_DMI_P CLK_BUF_EXP_P 6
R163 0 RC0402N AM43 AP3

29 CLK_PCIE_WLAN_N CLKOUT_PCIE1N CLKIN_BCLK_N CLK_BUF_BCLK_N 6
R164 0 RC0402N AM45 AP1
29 CLK_PCIE_WLAN_P CLKOUT_PCIE1P CLKIN_BCLK_P CLK_BUF_BCLK_P 6
29 CLK_WLAN_OE# U4 PCIECLKRQ1# / GPIO18

+V3.3S R384 10k RC0402N F18
CLKIN_DOT_96N CLK_BUF_DOT96_N 6
CLKIN_DOT_96P E18 CLK_BUF_DOT96_P 6
R165 0 RC0402N AM47
30 CLK_PCIE_3G_N R166 0 RC0402N CLKOUT_PCIE2N
30 CLK_PCIE_3G_P AM48 CLKOUT_PCIE2P
CLKIN_SATA_N / CKSSCD_N AH13 CLK_BUF_CKSSCD_N 6
30 CLK_3G_OE# N4 PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P AH12 CLK_BUF_CKSSCD_P 6
+V3.3S R176 10k RC0402N
R167 0 RC0402N AH42 P41

25 CLK_PCIE_LAN_N CLKOUT_PCIE3N REFCLK14IN CLK_BUF_REF14 6
R168 0 RC0402N AH41
25 CLK_PCIE_LAN_P CLKOUT_PCIE3P
R169 0 RC0402N A8 J42
25 CLK_LAN_OE# PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK CLK_PCI_FB 18
R239 10k RC0402N ccq,evt->dvt,0625
AM51 AH51 XTAL25M_IN C161 20PF CC0402N
CLKOUT_PCIE4N XTAL25_IN XTAL25M_OUT
AM53 CLKOUT_PCIE4P XTAL25_OUT AH53
2
R240 10k RC0402N M9 AF38 R170 90.9 ±1% RC0402N +V1.1S X4
PCIECLKRQ4# / GPIO26 XCLK_RCOMP R171 X3 25MHZ
1M 25MHZ X8A025AFK1H
+V3.3A AJ50 T45 R172 22 RC0402N POP = NA RC0402N POP = NA
CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64
1
B B
AJ52 CLKOUT_PCIE5P C162 20PF CC0402N
R267 10k RC0402N H6 P43 R173 22 RC0402N POP = NA
Clock Flex
PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65
AK53 T42 R174 22 RC0402N POP = NA

CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66
AK51 CLKOUT_PEG_B_P
R268 10k RC0402N P13 N50 R175 22 RC0402N POP = NA
PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67
IBX-M_BGA1071_R1P5
A A

5th floor,Block K,
Title <Title>
Size Sheet Rev
PCH2
C Name A
5 4 3 2 1
5 4 3 2 1
D D
R284 100k RC0402N

R273 100k RC0402N
U4D
U4C FDI_TXN[7:0] 7 22 GM_BKLTEN T48 BJ46

FDI_TXN0 L_BKLTEN SDVO_TVCLKINN
FDI_RXN0 BA18 22 GM_VDDEN T47 L_VDD_EN SDVO_TVCLKINP BG46
7 DMI_RXN0 BC24 BH17 FDI_TXN1
DMI0RXN FDI_RXN1 FDI_TXN2
7 DMI_RXN1 BJ22 DMI1RXN FDI_RXN2 BD16 22 GM_BKLT_CTRL Y48 L_BKLTCTL SDVO_STALLN BJ48
7 DMI_RXN2 AW20 BJ16 FDI_TXN3 +V3.3S R64 2.2K RC0402N BG48
DMI2RXN FDI_RXN3 FDI_TXN4 SDVO_STALLP
7 DMI_RXN3 BJ20 DMI3RXN FDI_RXN4 BA16 22 DDC_CLK AB48 L_DDC_CLK
BE14 FDI_TXN5 22 DDC_DATA Y45 BF45
FDI_RXN5 FDI_TXN6 R75 2.2K RC0402N L_DDC_DATA SDVO_INTN
7 DMI_RXP0 BD24 DMI0RXP FDI_RXN6 BA14 SDVO_INTP BH45
7 DMI_RXP1 BG22 BC12 FDI_TXN7 R187 10k RC0402N AB46
DMI1RXP FDI_RXN7 R189 10k RC0402N L_CTRL_CLK
7 DMI_RXP2 BA20 DMI2RXP FDI_TXP[7:0] 7 +V3.3S V48 L_CTRL_DATA
7 DMI_RXP3 BG20 BB18 FDI_TXP0
DMI3RXP FDI_RXP0 FDI_TXP1 R177 2.37K ±1% RC0402N LVDS_IBG
FDI_RXP1 BF17 AP39 LVD_IBG SDVO_CTRLCLK T51
7 DMI_TXN0 BE22 BC16 FDI_TXP2 AP41 T53
DMI0TXN FDI_RXP2 FDI_TXP3 LVD_VBG SDVO_CTRLDATA
7 DMI_TXN1 BF21 DMI1TXN FDI_RXP3 BG16
7 DMI_TXN2 BD20 AW16 FDI_TXP4 AT43
DMI2TXN FDI_RXP4 FDI_TXP5 LVD_VREFH
7 DMI_TXN3 BE18 DMI3TXN FDI_RXP5 BD14 AT42 LVD_VREFL DDPB_AUXN BG44
BB14 FDI_TXP6 BJ44
FDI_RXP6 FDI_TXP7 DDPB_AUXP
7 DMI_TXP0 BD22 DMI0TXP FDI_RXP7 BD12 DDPB_HPD AU38
+V3.3S
LVDS
7 DMI_TXP1 BH21 DMI1TXP 22 LA_CLKN AV53 LVDSA_CLK#
7 DMI_TXP2 BC20 DMI2TXP 22 LA_CLKP AV51 LVDSA_CLK DDPB_0N BD42
7 DMI_TXP3 BD18 DMI3TXP FDI_INT BJ14 FDI_INT 7 DDPB_0P BC42
22 LA_DATAN0 BB47 BJ42
DMI
FDI
LVDSA_DATA#0 DDPB_1N
BF13 BA52 BG42
Digital Display Interface

FDI_FSYNC0 FDI_FSYNC0 7 22 LA_DATAN1 LVDSA_DATA#1 DDPB_1P
+V1.1S BH25 22 LA_DATAN2 AY48 BB40
DMI_ZCOMP LVDSA_DATA#2 DDPB_2N
FDI_FSYNC1 BH13 FDI_FSYNC1 7 AV47 LVDSA_DATA#3 DDPB_2P BA40
R178 49.9 ±1% RC0402N BF25 DMI_IRCOMP DDPB_3N AW38 R62 R59 POP=NA Can disable Port C
BJ12 FDI_LSYNC0 7 22 LA_DATAP0 BB48 BA38 2.2K 2.2K
FDI_LSYNC0 LVDSA_DATA0 DDPB_3P RC0402N RC0402N
22 LA_DATAP1 BA50 LVDSA_DATA1
FDI_LSYNC1 BG14 FDI_LSYNC1 7 22 LA_DATAP2 AY49 LVDSA_DATA2
AV48 LVDSA_DATA3 DDPC_CTRLCLK Y49 HDMI_CTRLCLK 24
C
DDPC_CTRLDATA AB49 HDMI_CTRLDATA 24 C
+V3.3S
+V3.3A AP48 LVDSB_CLK#
AP47 LVDSB_CLK DDPC_AUXN BE44
R227 10k RC0402N R179 10k RC0402N BD44
DDPC_AUXP DDPC_HPD
AY53 LVDSB_DATA#0 DDPC_HPD AV40
34 PM_SYSRST# T6 SYS_RESET# WAKE# J12 PCIE_WAKE# 25,29,30 AT49 LVDSB_DATA#1
AU52 BE40 C499 0.1u CC0402N TMDS_DATAN2 24
LVDSB_DATA#2 DDPC_0N C496 0.1u CC0402N
AT53 LVDSB_DATA#3 DDPC_0P BD40 TMDS_DATAP2 24
30 SYS_PWROK M6 Y1 BF41 C497 0.1u CC0402N TMDS_DATAN1 24
SYS_PWROK CLKRUN# / GPIO32 PM_CLKRUN# 34 +V3.3S DDPC_1N
AY51 BH41 C498 0.1u CC0402N TMDS_DATAP1 24
R181 150 ±1% RC0402N LVDSB_DATA0 DDPC_1P C503 0.1u
HDMI CC0402N
AT48 LVDSB_DATA1 DDPC_2N BD38 TMDS_DATAN0 24
System Power Management
30 PM_PCH_PWROK B17 R182 8.2K RC0402N R183 150 ±1% RC0402N AU50 BC38 C500 HDMI
0.1u CC0402N TMDS_DATAP0 24
R558 10k RC0402N PWROK R184 150 ±1% RC0402N LVDSB_DATA2 DDPC_2P C501 HDMI
0.1u CC0402N
AT51 LVDSB_DATA3 DDPC_3N BB36 TMDS_CLKN 24
BA36 C502 HDMI
0.1u CC0402N TMDS_CLKP 24
R186 0 RC0402N MEPWROK DDPC_3P HDMI
K5 MEPWROK SUS_STAT# / GPIO61 P8 PM_SUS_STAT# 34
30 PM_MEPWROK R185 0 RC0402N POP = NA HDMI
23 GM_CRT_B AA52 U50 HDMI
R780 10k RC0402N CRT_BLUE DDPD_CTRLCLK HDMI
A10 LAN_RST# SUSCLK / GPIO62 F3 TP10 23 GM_CRT_G AB53 CRT_GREEN DDPD_CTRLDATA U52
23 GM_CRT_R AD53 CRT_RED
7 PM_DRAM_PWRGD D9 E4 SLP_S5# BC46

DRAMPWROK SLP_S5# / GPIO63 TP11 DDPD_AUXN
23 CRT_DDC_CLK V51 CRT_DDC_CLK DDPD_AUXP BD46
23 CRT_DDC_DATA V53 CRT_DDC_DATA DDPD_HPD AT38
34 PM_RSMRST# C16 H7 SLP_S4# R190 0 RC0402N PM_SLP_S4# 34,38,42
R199 10k RC0402N RSMRST# SLP_S4#
DDPD_0N BJ40
23 CRT_HSYNC Y53 CRT_HSYNC DDPD_0P BG40
34 SUS_PWR_ACK M1 SUS_PWR_DN_ACK / GPIO30 SLP_S3# P12 SLP_S3# R191 0 RC0402N PM_SLP_S3# 34,38,39,42 23 CRT_VSYNC Y51 CRT_VSYNC DDPD_1N BJ38
+V3.3A R463 10k RC0402N BG38
DDPD_1P
CRT
DDPD_2N BF37
34 PM_PWRBTN# P5 K8 SLP_M# R263 0 RC0402N POP = NA R194 1k ±1% RC0402N AD48 BH37
PWRBTN# SLP_M# DAC_IREF DDPD_2P
AB51 CRT_IRTN DDPD_3N BE36
DDPD_3P BD36
P7 N2 +V5S
34 AC_PRESENT ACPRESENT / GPIO31 TP23 TP12
IBX-M_BGA1071_R1P5
+V3.3A R198 8.2K RC0402N
34 PM_BATLOW# A6 BATLOW# / GPIO72 PMSYNCH BJ10 H_PM_SYNC 7
R195
B B
R197 8.2K RC0402N 10k
+V3.3A R196 10k RC0402N PM_RI# F14 F6 R193 10k RC0402N POP = NA +V3.3A RC0402N
RI# SLP_LAN# / GPIO29
1
IBX-M_BGA1071_R1P5
Q75 HDMI BSS138
G
DDPC_HPD 2 S D 3 HDMI_HPD 24
SLP_M#:
Can be left as NC when Intel AMT is not supported on the platform. R652 R205 0 RC0402N POP = NA
100k
MEPWROK: HDMI
Should be asserted when all Intel ME power rails are up and stable.
RC0402N Dual
HDMILay
It can be connected to PCH_PWROK pin on PCH when Intel AMT is not enabled.
HDMI
A A

5th floor,Block K,
Title <Title>
Size Sheet Rev
PCH3
C Name A
ENGINEER: Ivan Date: Friday, December 10, 2010 Sheet 17 of 44
5 4 3 2 1
5 4 3 2 1
U4E
H40 AD0 NV_CE#0 AY9
N34 AD1 NV_CE#1 BD1
C44 AD2 NV_CE#2 AP15
D
A38 AD3 NV_CE#3 BD8 D
C36 AD4
J34 AD5 NV_DQS0 AV9
A40 AD6 NV_DQS1 BG8
D45 AD7
E36 AD8 NV_DQ0 / NV_IO0 AP7
H48 AD9 NV_DQ1 / NV_IO1 AP6
E40 AD10 NV_DQ2 / NV_IO2 AT6
C40 AD11 NV_DQ3 / NV_IO3 AT9
M48 AD12 NV_DQ4 / NV_IO4 BB1
M45 AD13 NV_DQ5 / NV_IO5 AV6
F53 AD14 NV_DQ6 / NV_IO6 BB3
M40 AD15 NV_DQ7 / NV_IO7 BA4
M43 BE4
NVRAM
AD16 NV_DQ8 / NV_IO8
J36 AD17 NV_DQ9 / NV_IO9 BB6
K48 AD18 NV_DQ10 / NV_IO10 BD6
F40 AD19 NV_DQ11 / NV_IO11 BB7
C42 AD20 NV_DQ12 / NV_IO12 BC8
K46 AD21 NV_DQ13 / NV_IO13 BJ8
M51 BJ6 +V_NVRAM_VCCPNAND
AD22 NV_DQ14 / NV_IO14
J52 AD23 NV_DQ15 / NV_IO15 BG6
K51 AD24
L34 BD3 R233 1k RC0402N POP = NA
AD25 NV_ALE
F42 AD26 NV_CLE AY6
J40 AD27
G46 AD28
F44 AU2 R385 32.4 RC0402N POP = NA
AD29 NV_RCOMP
M47 AD30
PCI
H36 AD31 NV_RB# AV7
J50 C/BE0# NV_WR#0_RE# AY8

G42 C/BE1# NV_WR#1_RE# AY5
+V3.3S H47 C/BE2#
G34 C/BE3# NV_WE#_CK0 AV11
NV_WE#_CK1 BF5
R200 8.2K RC0402N INT_PIRQA# G38
R201 8.2K RC0402N INT_PIRQB# H51
PIRQA# Allocation USB Devices
PIRQB#
C
R202
R203
8.2K
8.2K
RC0402N
RC0402N
INT_PIRQC#
INT_PIRQD#
B37
A44
PIRQC# USBP0N H18
J18
USB_PN0 22 USB0 Camera C
PIRQD# USBP0P USB_PP0 22
R204 8.2K RC0402N PCI_REQ#0 F51
USBP1N A18
C18
USB_PN1 29 USB1 WLAN
REQ0# USBP1P USB_PP1 29
R206
R229
8.2K RC0402N
8.2K RC0402N
PCI_REQ#1
DGPU_SELECT#
A46
B45
REQ1# / GPIO50 USBP2N N20
P20
USB_PN2 28 USB2 Cardreader
REQ2# / GPIO52 USBP2P USB_PP2 28
R207 8.2K RC0402N
ccq,evt->dvt,0625
PCI_REQ#3 M53 REQ3# / GPIO54 USBP3N J20
L20
USB4 Port 3
USBP3P
R208
R209
1k RC0402N
1k RC0402N
PCI_GNT0#
PCI_GNT1#
F48
K45
GNT0# USBP4N F20
G20
USB_PN4 31 USB5 NA
GNT1# / GPIO51 USBP4P USB_PP4 31
R210 1k RC0402N POP = NA PCI_GNT3#
F36
H53
GNT2# / GPIO53 USBP5N A20
C20
USB6 Disabled
GNT3# / GPIO55 USBP5P
R211 8.2K RC0402N INT_PIRQE# B41
USBP6N M22
N22
USB7 Disabled
PIRQE# / GPIO2 USBP6P
R212
R213
8.2K
8.2K
RC0402N
RC0402N
INT_PIRQF#
INT_PIRQG#
K53
A36
PIRQF# / GPIO3 USBP7N B21
D21
USB8 Port 2
PIRQG# / GPIO4 USBP7P
R214 8.2K RC0402N INT_PIRQH# A48 PIRQH# / GPIO5 USBP8N H22
J22
USB_PN8 31 USB10 Bluetooth
USBP8P USB_PP8 31
USB11 3G
USB
K6 PCIRST# USBP9N E22
USBP9P F22
R215
R216
8.2K
8.2K
RC0402N
RC0402N
PCI_SERR#
PCI_PERR#
E44
E50
SERR# USBP10N A22
C22
USB_PN10 31 USB12 Port 1
PERR# USBP10P USB_PP10 31
USBP11N G24 USB_PN11 30
USBP11P H24 USB_PP11 30 PCH-HM55 are disabled USB Ports 6&7
R217 8.2K RC0402N PCI_IRDY# A42 L24
IRDY# USBP12N USB_PN12 31
H44 PAR USBP12P M24 USB_PP12 31
+V3.3S R218 8.2K RC0402N PCI_DEVSEL# F46 A24
PCI_FRAME# DEVSEL# USBP13N
R219 8.2K RC0402N C46 FRAME# USBP13P C24 Place within 500mils of PCH ball,
R220 8.2K RC0402N PCI_LOCK# D49
And avoid routing next to
C163 0.1u CC0402N PLOCK# USB_BIA R221 22.6 ±1% RC0402N clock/high speed signals
USBRBIAS# B25
R222 8.2K RC0402N PCI_STOP#_PCH D41
U5 R223 8.2K RC0402N PCI_TRDY# STOP# +V3.3A
C48 TRDY# USBRBIAS D25
5
1 M7 PME#
4 N16 R224 10k RC0402N
7,25,29,30,34 BUF_PLT_RST# PLT_RST# OC0# / GPIO59 R225 10k RC0402N
2 D5 PLTRST# OC1# / GPIO40 J16
OC2# / GPIO41 F16 USB_OC2# USB_OC2# 31
USB_OC2# R226 10k RC0402N
R237 SN74LVC1G08DCKR R6 22 RC0402N N52 L16 R228 10k RC0402N
34 CLK_FWHPCI CLKOUT_PCI0 OC3# / GPIO42
3
B B
100k sot65p190-5n
16 CLK_PCI_FB
R52 22 RC0402N P53 CLKOUT_PCI1 OC4# / GPIO43 E14 USB_OC4# USB_OC4# 31
RC0402N R5 22 RC0402N P46 G16 R232 10k RC0402N
34 CLK_PCI_KBC CLKOUT_PCI2 OC5# / GPIO9
P51 CLKOUT_PCI3 OC6# / GPIO10 F12 USB_OC6# USB_OC6# 31
P48 T15 R236 10k RC0402N
CLKOUT_PCI4 OC7# / GPIO14
SMC_WAKE_SCI# 34
IBX-M_BGA1071_R1P5
OC#[3:0] can only be used for EHCI Controller 1

OC#[4:7] can only be used for EHCI Controller 2
A A

5th floor,Block K,
Title <Title>
Size Sheet Rev
PCH4
C Name A
5 4 3 2 1
5 4 3 2 1
+V3.3S U4H
U4F AB16 VSS[0]
R238 1k RC0402N Y3 AH45 AA19 AK30
R653 10k RC0402N BMBUSY# / GPIO0 CLKOUT_PCIE6N VSS[1] VSS[80]
CLKOUT_PCIE6P AH46 AA20 VSS[2] VSS[81] AK31
34 SMC_EXTSMI# C38 TACH1 / GPIO1 AA22 VSS[3] VSS[82] AK32
AM19 VSS[4] VSS[83] AK34
+V3.3S R241 10k RC0402N D37 AA24 AK35
R720 10k RC0402N TACH2 / GPIO6 VSS[5] VSS[84]
CLKOUT_PCIE7N AF48 AA26 VSS[6] VSS[85] AK38
MISC
34 SMC_RUNTIME_SCI# J32 TACH3 / GPIO7 CLKOUT_PCIE7P AF47 AA28 VSS[7] VSS[86] AK43
AA30 VSS[8] VSS[87] AK46
+V3.3A R244 10k RC0402N F10 AA31 AK49
D GPIO8 VSS[9] VSS[88] D
AA32 VSS[10] VSS[89] AK5
+V3.3S R721 10k RC0402N K9 U2 AB11 AK8
LAN_PHY_PWR_CTRL / GPIO12 A20GATE H_A20GATE 34 VSS[11] VSS[90]
AB15 VSS[12] VSS[91] AL2
R245 1k RC0402N T7 R786 10k RC0402N +V3.3S AB23 AL52
GPIO15 VSS[13] VSS[92]
AB30 VSS[14] VSS[93] AM11
R243 +V3.3S R246 10k RC0402N AA2 AM3 BCLK_CPU_N 7 AB31 BB44
10k SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N VSS[15] VSS[94]
AB32 VSS[16] VSS[95] AD24
RC0402N R242 10k RC0402N F38 AM1 BCLK_CPU_P 7 AB39 AM20
TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P +V1.1S_VTT VSS[17] VSS[96]
BIOS_REC_R Y7 BG10 AB47 AM24
SCLOCK / GPIO22 PECI H_PECI 7 VSS[19] VSS[98]
GPIO
H10 T1 H_RCIN# 34 R248 AB8 AM28
TP16 GPIO24 RCIN# VSS[21] VSS[100]
3
R784 R247 10k RC0402N +V3.3S 56 AC2 BA42

Q46 10k R650 10k RC0402N POP = NA RC0402N VSS[22] VSS[101]
AB12 BE10 H_CPUPWRGD 7 AC52 AM30
S D
2N7002LT1 RC0402N GPIO27 PROCPWRGD VSS[23] VSS[102]
CPU
AD11 VSS[24] VSS[103] AM31
1 SOT95P237-3N POP = NA +V3.3A R249 10k RC0402N V13 BD10 R250 54.9 RC0402N AD12 AM32
34 BIOS_REC G GPIO28 THRMTRIP# H_THRMTRIP# 7 VSS[25] VSS[104]
POP = NA AD16 AM34
VSS[26] VSS[105]
2
6 STP_PCI# M11 STP_PCI# / GPIO34 AD23 VSS[27] VSS[106] AM35

+V3.3S R796
R418
10k
10k
RC0402N
RC0402N
Note: AD30 VSS[28] VSS[107] AM38
V6 AD31 AM39
GPIO35 R248 and R250 Place close to PCH! AD32
VSS[29] VSS[108]
AM42
R251 10k RC0402N VSS[30] VSS[109]
+V3.3S AB7 SATA2GP / GPIO36 TP1 BA22 AD34 VSS[31] VSS[110] AU20
AU22 VSS[32] VSS[111] AM46
R252 10k RC0402N AB13 AW22 AD42 AV22
SATA3GP / GPIO37 TP2 VSS[33] VSS[112]
AD46 VSS[34] VSS[113] AM49
R253 10k RC0402N V3 BB22 AD49 AM7
SLOAD / GPIO38 TP3 VSS[35] VSS[114]
AD7 VSS[36] VSS[115] AA50
R254 10k RC0402N P3 AY45 AE2 BB10
R255 100k RC0402N POP = NA SDATAOUT0 / GPIO39 TP4 VSS[37] VSS[116]
AE4 VSS[38] VSS[117] AN32
+V3.3A R269 10k RC0402N H3 AY46 AF12 AN50
R270 10k RC0402N PCIECLKRQ6# / GPIO45 TP5 VSS[39] VSS[118]
Y13 VSS[40] VSS[119] AN52
7 DRAMRST_CNTRL_PCH F1 PCIECLKRQ7# / GPIO46 TP6 AV43 AH49 VSS[41] VSS[120] AP12
AU4 VSS[42] VSS[121] AP42
+V3.3S R256 10k RC0402N AB6 AV45 AF35 AP46
R257 10k RC0402N SDATAOUT1 / GPIO48 TP7 VSS[43] VSS[122]
AP13 VSS[44] VSS[123] AP49
34 TEMP_ALERT# AA4 SATA5GP / GPIO49 / TEMP_ALERT# TP8 AF13 AN34 VSS[45] VSS[124] AP5
AF45 VSS[46] VSS[125] AP8
C R258 10k RC0402N F8 M18 AF46 AR2 C
GPIO57 TP9 VSS[47] VSS[126]
AF49 VSS[48] VSS[127] AR52
TP10 N18 AF5 VSS[49] VSS[128] AT11
AF8 VSS[50] VSS[129] BA12
A4 VSS_NCTF_1 TP11 AJ24 AG2 VSS[51] VSS[130] AH48
A49 VSS_NCTF_2 AG52 VSS[52] VSS[131] AT32
NCTF
RSVD
A5 VSS_NCTF_3 TP12 AK41 AH11 VSS[53] VSS[132] AT36
A50 VSS_NCTF_4 AH15 VSS[54] VSS[133] AT41
A52 VSS_NCTF_5 TP13 AK42 AH16 VSS[55] VSS[134] AT47
A53 VSS_NCTF_6 AH24 VSS[56] VSS[135] AT7
B2 VSS_NCTF_7 TP14 M32 AH32 VSS[57] VSS[136] AV12
B4 VSS_NCTF_8 AV18 VSS[58] VSS[137] AV16
B52 VSS_NCTF_9 TP15 N32 AH43 VSS[59] VSS[138] AV20
B53 VSS_NCTF_10 AH47 VSS[60] VSS[139] AV24
BE1 VSS_NCTF_11 TP16 M30 AH7 VSS[61] VSS[140] AV30
BE53 VSS_NCTF_12 AJ19 VSS[62] VSS[141] AV34
BF1 VSS_NCTF_13 TP17 N30 AJ2 VSS[63] VSS[142] AV38
BF53 VSS_NCTF_14 AJ20 VSS[64] VSS[143] AV42
BH1 VSS_NCTF_15 TP18 H12 AJ22 VSS[65] VSS[144] AV46
BH2 VSS_NCTF_16 AJ23 VSS[66] VSS[145] AV49
BH52 VSS_NCTF_17 TP19 AA23 AJ26 VSS[67] VSS[146] AV5
BH53 VSS_NCTF_18 AJ28 VSS[68] VSS[147] AV8
BJ1 VSS_NCTF_19 NC_1 AB45 AJ32 VSS[69] VSS[148] AW14
BJ2 VSS_NCTF_20 AJ34 VSS[70] VSS[149] AW18
BJ4 VSS_NCTF_21 NC_2 AB38 AT5 VSS[71] VSS[150] AW2
BJ49 VSS_NCTF_22 AJ4 VSS[72] VSS[151] BF9
BJ5 VSS_NCTF_23 NC_3 AB42 AK12 VSS[73] VSS[152] AW32
BJ50 VSS_NCTF_24 AM41 VSS[74] VSS[153] AW36
BJ52 VSS_NCTF_25 NC_4 AB41 AN19 VSS[75] VSS[154] AW40
BJ53 VSS_NCTF_26 AK26 VSS[76] VSS[155] AW52
D1 VSS_NCTF_27 NC_5 T39 AK22 VSS[77] VSS[156] AY11
D2 VSS_NCTF_28 AK23 VSS[78] VSS[157] AY43
D53 VSS_NCTF_29 AK28 VSS[79] VSS[158] AY47
E1 VSS_NCTF_30 INIT3_3V# P6 TP6
E53 IBX-M_BGA1071_R1P5
VSS_NCTF_31
TP24 C10
IBX-M_BGA1071_R1P5
B B
AD15
AD51
AD47
AK45
AK39
AV14
AT12
AT13
W52
AM6
AM5
M12
M16
M20
M34
M38
M42
M46
M49
H49
N38
N24
R52
U30
U31
U32
U34
AT8
K11
K43
K47
P11
P22
P30
P32
P34
P42
P45
P47
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
P24
Y47
T12
T41
T46
T49
T43
L14
L18
L22
L32
L36
L40
L52
J24
W2
M5
M8
H5
R2
K7
V5
V7
V8
Y5
Y6
Y8
T5
T8
L2
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]
U4I
IBX-M_BGA1071_R1P5
A A
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

AY7
B11
B15
B19
B23
B31
B35
B39
B43
B47
B7
BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49
BB5
BC10
BC14
BC18
BC2
BC22
BC32
BC36
BC40
BC44
BC52
BH9
BD48
BD49
BD5
BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50
BE6
BE8
BF3
BF49
BF51
BG18
BG24
BG4
BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47
BH7
C12
C50
D51
E12
E16
E20
E24
E30
E34
E38
E42
E46
E48
E6
E8
F49
F5
G10
G14
G18
G2
G22
G32
G36
G40
G44
G52
AF39
H16
H20
H30
H34
H38
H42
5th floor,Block K,
Title <Title>
Size Sheet Rev
PCH5
C Name A
5 4 3 2 1
5 4 3 2 1
D D
+V1.1S +V1.1S_PCH_VCC ccq,dvt->pvt,1124 +V3.3S
U4G POWER 100nH

AB24 AE50 VCCADAC_1_2 FB3 1 2 LC0603N
VCCCORE[1] VCCADAC[1]
AB26 VCCCORE[2]
AB28 AE52 C167 C166 C168
C155 C165 VCCCORE[3] VCCADAC[2] 0.1u 0.01uF 10uF
AD26 VCCCORE[4]
Please note that all Ibex Peak-M rails with 10uF 1uF CC0402N CC0402N CC0603N
CRT
AD28 VCCCORE[5] VSSA_DAC[1] AF53
netnames +V1.1S and +V1.1M rails are actually CC0603N CC0402N AF26 VCCCORE[6]
VCC CORE
+V1.05S and +V1.05M rails (Refer Page 55) AF28 VCCCORE[7] VSSA_DAC[2] AF51
AF30 VCCCORE[8]
AF31 VCCCORE[9]
AH26 +V3.3S
VCCCORE[10]
AH28 VCCCORE[11]
AH30 VCCCORE[12]
AH31 VCCCORE[13] VCCALVDS AH38
AJ30 VCCCORE[14]
AJ31 AH39 +V1.8S
VCCCORE[15] VSSA_LVDS
100nH
+V1.1S AP43 VCC_TX_LVDS L20 1 2 LC0603N
VCCTX_LVDS[1]
VCCTX_LVDS[2] AP45
AT46 C169 C170 C171
LVDS
+V1.1S VCCTX_LVDS[3] 0.01uF 0.01uF 10uF ccq,evt->dvt,0625
AK24 VCCIO[24] VCCTX_LVDS[4] AT45
CC0402N CC0402N CC0805N
R259 0 RC0603N POP = NA BJ24 VCCAPLLEXP

VCC3_3[2] AB34
+V3.3S
C AN20 VCCIO[25] VCC3_3[3] AB35 C
AN22
HVCMOS
+V1.1S VCCIO[26]
AN23 VCCIO[27] VCC3_3[4] AD35
AN24 VCCIO[28]
AN26 C172
VCCIO[29] 0.1u
AN28 VCCIO[30]
BJ26 CC0402N
VCCIO[31]
BJ28 VCCIO[32]
C164 C174 C175 C176 C177 AT26
10uF 1uF 1uF 1uF 1uF VCCIO[33]
AT28 VCCIO[34]
CC0603N CC0402N CC0402N CC0402N CC0402N AU26 +V1.8S
VCCIO[35]
AU28 VCCIO[36]
AV26 VCCIO[37]
AV28 AT24 +V1.1S_VTT
VCCIO[38] VCCVRM[2]
AW26 VCCIO[39]
AW28 VCCIO[40]
DMI
BA26 VCCIO[41] VCCDMI[1] AT16
BA28 VCCIO[42]
BB26 AU16 C178
VCCIO[43] VCCDMI[2] 1uF
BB28 VCCIO[44]
BC26 CC0402N
VCCIO[45]
PCI E*
BC28 VCCIO[46]
BD26 VCCIO[47]
BD28 VCCIO[48]
BE26 VCCIO[49] VCCPNAND[1] AM16
BE28 VCCIO[50] VCCPNAND[2] AK16
+V3.3S BG26 AK20 +V_NVRAM_VCCPNAND +V1.8S
VCCIO[51] VCCPNAND[3]
BG28 VCCIO[52] VCCPNAND[4] AK19
BH27 VCCIO[53] VCCPNAND[5] AK15
VCCPNAND[6] AK13
AN30 VCCIO[54] VCCPNAND[7] AM12
C408
NAND / SPI
AN31 VCCIO[55] VCCPNAND[8] AM13
0.1u AM15 C179
CC0402N VCCPNAND[9] 0.1u
+V1.8S AN35 CC0402N
VCC3_3[1]
+V1.1S
B
AT22 VCCVRM[1] B
R260 0 RC0603N POP = NA BJ18 AM8 +V3.3S
VCCFDIPLL VCCME3_3[1]
VCCME3_3[2] AM9
FDI
AM23 VCCIO[1] VCCME3_3[3] AP11

VCCME3_3[4] AP9
C180
IBX-M_BGA1071_R1P5 0.1u
CC0402N
A A

5th floor,Block K,
Title <Title>
Size Sheet Rev
PCH6
C Name A
ENGINEER: Ivan Date: Wednesday, December 01, 2010 Sheet 20 of 44
5 4 3 2 1
5 4 3 2 1
+V1.1S +V1.1S_VCCA_CLK
R465 0 RC0603N POP = NA
C173 C182
10uF 1uF
CC0603N CC0402N +V1.1S
POP = NA POP = NA U4J POWER
AP51 VCCACLK[1] VCCIO[5] V24
VCCIO[6] V26
AP53 Y24 C183
VCCACLK[2] VCCIO[7] 1uF
VCCIO[8] Y26
CC0402N
R782 0 RC0402N AF23 V28
D VCCLAN[1] VCCSUS3_3[1] D
VCCSUS3_3[2] U28
AF24 U26 +V3.3A
VCCLAN[2] VCCSUS3_3[3]
VCCSUS3_3[4] U24
VCCSUS3_3[5] P28
C184 0.1u CC0402N Y20 P26
DCPSUSBYP VCCSUS3_3[6]
VCCSUS3_3[7] N28
+V1.1S N26
VCCSUS3_3[8] C191 C185
AD38 VCCME[1] VCCSUS3_3[9] M28
M26 0.1u 0.1u
VCCSUS3_3[10] CC0402N CC0402N
AD39 L28
USB
VCCME[2] VCCSUS3_3[11]
VCCSUS3_3[12] L26
AD41 VCCME[3] VCCSUS3_3[13] J28
C186 C189 J26
22uF 1uF VCCSUS3_3[14]
AF43 VCCME[4] VCCSUS3_3[15] H28
CC0805N CC0402N H26
VCCSUS3_3[16]
AF41 VCCME[5] VCCSUS3_3[17] G28
VCCSUS3_3[18] G26
AF42 VCCME[6] VCCSUS3_3[19] F28
+V1.1S F26
VCCSUS3_3[20] +V3.3A
V39 VCCME[7] VCCSUS3_3[21] E28
E26
Clock and Miscellaneous

VCCSUS3_3[22]
V41 VCCME[8] VCCSUS3_3[23] C28
VCCSUS3_3[24] C26
1
V42 VCCME[9] VCCSUS3_3[25] B27
C187 C190 A28 D7
22uF 1uF VCCSUS3_3[26] +V3.3S
Y39 VCCME[10] VCCSUS3_3[27] A26 BAT54
CC0805N CC0402N +V1.1S
SOT95P280-3N
Y41 VCCME[11] VCCSUS3_3[28] U23
+V1.1S R90 0 RC0805N POP = NA +V5A
2
3
1
Y42 VCCME[12] VCCIO[56] V23
0 dual lay D8
L18 1 2 F24 +V5A_PCH_VCC5REFSUS R264 10 RC0603N BAT54
V5REF_SUS
SOT95P280-3N +V5S
C192 0.1u CC0402N V9 C193 0.1u CC0402N
DCPRTC
1
2
3
+ CP6 C213
330uF 1uF K49 V5S_PCH_VCC5REF R265 10 RC0603N
CCP7343N VCC_VRM_PCH V5REF
C CC0402N +V1.8S AU24 VCCVRM[3]
C
PCI/GPIO/LPC
2
ccq,evt->dvt,0625 POP = NA
J38 C194
VCCADPLLA VCC3_3[8] +V3.3S 1uF
BB51 VCCADPLLA[1]
+V1.1S R91 0 RC0805N POP = NA Close to the PCH BB53 L38 CC0402N
VCCADPLLA[2] VCC3_3[9]
0 dual lay M36
L19 VCCADPLLB VCC3_3[10]
1 2 BD51 VCCADPLLB[1]
BD53 N36 C195 +V3.3S
+V1.1S VCCADPLLB[2] VCC3_3[11] 0.1u
1
AH23 P36 CC0402N

VCCIO[21] VCC3_3[12]
+ CP7 C214 AJ35
330uF C196 C197 VCCIO[22]
1uF AH35 VCCIO[23] VCC3_3[13] U35
CCP7343N CC0402N 1uF 1uF C198
2
POP = NA CC0402N CC0402N AF34 0.1u

+V1.1S VCCIO[2] CC0402N
VCC3_3[14] AD13
AH34 +V1.1S
VCCIO[3]
Close to the PCH
AF32 VCCIO[4]
AK3 VCCSATAPLL R266 0 RC0603N POP = NA
C200 C199 0.1u CC0402N VCCSATAPLL[1]
V12 DCPSST VCCSATAPLL[2] AK1
1uF
CC0402N +V1.1S_VCC_SATA +V1.1S C202 C181
1uF 10uF
C201 0.1u CC0402N Y22 CC0402N CC0603N
DCPSUS POP = NA POP = NA
VCCIO[9] AH22
+V3.3A
P18 VCCSUS3_3[29] VCCVRM[4] AT20 +V1.8S
U19 +V1.1S_VCC_SATA
VCCSUS3_3[30]
SATA
PCI/GPIO/LPC
VCCIO[10] AH19
C204 U20 VCCSUS3_3[31]
0.1u VCCIO[11] AD20
CC0402N U22 VCCSUS3_3[32]
AF22 C205
VCCIO[12]
1uF
B VCCIO[13] AD19 CC0402N B
V15 VCC3_3[5] VCCIO[14] AF20
+V3.3S AF19
VCCIO[15]
V16 VCC3_3[6] VCCIO[16] AH20
Y16 VCC3_3[7] VCCIO[17] AB19

VCCIO[18] AB20
C206 AB22 +V1.1S
VCCIO[19]
0.1u VCCIO[20] AD22
+V1.1S_VTT CC0402N AT18 V_CPU_IO[1]
AA34
CPU
VCCME[13]
VCCME[14] Y34
AU18 V_CPU_IO[2] VCCME[15] Y35
AA35 C409 C531
C207 C208 C209 VCCME[16] 10uF ccq,evt->dvt,0625
1uF
4.7uF 0.1u 0.1u CC0402N CC0805N
CC0603N CC0402N CC0402N
RTC
A12 VCCRTC VCCSUSHDA L30

HDA
+V3.3A_RTC
IBX-M_BGA1071_R1P5
+V3.3A +V1.5A
R493 R494
C210 C211 0 0
0.1u 0.1u RC0603N RC0603N
CC0402N CC0402N POP = NA
C212
1uF
CC0402N
Close to the PCH

A A

5th floor,Block K,
Title <Title>
Size Sheet Rev
PCH7
C Name A
5 4 3 2 1
5 4 3 2 1
AUO 40PIN CON"

1 NC
14寸LCD cable
2
3
4
VDD
VDD
DVDD
LVDS Connector +V3.3S
LCD_VCC
5 NC LCD_VCC
6 SCL U6
CN1 5 VIN
7 SDA VOUT 1
1 1 Tss=0.2*Css*Vin R271 0 RC0402N POP = NA 4 SS
D 8 Rin0- 2 2 C220
D
3 0.1u C215 C216 C217 3 2 C218 C219
3 EN/ENBGND
LCD CON" 9 Rin0+ 4
5
4
5 LA_CLKN 17
CC0402N 10uF
CC1206N
1uF
CC0603N
0.01uF
CC0402N APL3512A/B
0.1u
CC0402N
10uF
CC1206N
+V3.3A
10 GND E1 E1 6 6 LA_CLKP 17 POP = NA SOT95P280-5N
7 7
VCC 1 11 Rin1- E2 E2 8 8 LA_DATAN2 17
2
9 9 LA_DATAP2 17
VCC 2 12 Rin1+ 10 10 D19 Set Tss=6.6ms
11 11 LA_DATAN1 17
VCC 3 13 GND 12 12 LA_DATAP1 17 3
SOT95P280-3N
13 17 GM_VDDEN R272 0 RC0402N
13
GND 4 14 Rin2- 14 14 LA_DATAN0 17
LCD_VLED
USE APL3512A High Enable
15 15 LA_DATAP0 17
ClkIN- 5 15 Rin2+ 16 16 DBC_EN
1
17 17
ClkIN+ 6 16 GND 18 18
LED_EN
19 19
GND 7 17 ClkIN- 20 20 R274 0 RC0402N BL_ADJ 34
Rin2- 8 18 ClkIN+ R276 0 RC0402N POP = NA GM_BKLT_CTRL 17

R275
Rin2+ 9 19 GND 0
POP = NA R439
GND 10 20 NC RC0402N 10k
RC0402N
Rin1- 11 21 NC
Rin1+ 12 22 GND
+V_DC For AUO B140XW01-V8
GND 13 23 NC +V5S_CAM
R481 0 RC0805N R478 0 RC0805N POP = NA
+V5S
Rin0- 14 24 NC J5
Dual Lay Dual Lay
1 F5 LCD_VLED
1
Rin0+ 15 25 GND E1 E1 2 2 USB_PN0 18
R480 0 RC0805N
POP = NA
1 2 SL050
F4632N
R380 0 RC0805N POP = NA
3 3 USB_PP0 18
(DBC_EN)GND 16 26 NC 4 4 1 AO4419 8
5 ccq,evt->dvt,0625 2 7
5
C Vled 17 27 NC E2 E2 6 6 DDC_CLK 17 3 6 C221
10uF
C222
0.1u
C
7 7 DDC_DATA 17 5
Vled 18 28 GND 8 8 C223 R279 CC1210N CC0402N
4
10uF 100k Q6
LED_EN 19 29 NC C1.0T-1-8AWB
SMD-CN-100P-8L
CC1210N RC0402N SOIC127P600-8N
ADJ 20 30 NC POP = NA
31 VLED_GND
32 VLED_GND +V5S_CAM LED_EN
R281
E1
LED_EN
33 VLED_GND
+V3.3S
2.2K
RC0402N
1
34 NC J4
2 USB_PN0 18
3 USB_PP0 18
35 PWM 4 C225 0.1u CC0402N R282
10k C226
5
36 LED_EN U7 RC0402N 1uF
3
5pin Q7 CC0402N
E2
37 NC(V1)/DBC_EN(V3) SMD-CN-100P-5L 30,34 BLCTL 1 OTRDTC144EUA

4 R283 1K RC0402N 1
38 VLED 17 GM_BKLTEN 2
3
39 VLED Q8
S D
3
2
PIN1 to PIN1 Dual Lay 2N7002LT1
40 VLED R285
10k
1 G
POP = NA
2
RC0402N
Set When Vin=9v Ton about 2.1757ms

When Vin=19.95v Ton about 8.45ms
B B
A A

5th floor,Block K,
Title <Title>
Size Sheet Rev
LCD CONN
C Name A
5 4 3 2 1
10 9 8 7 6 5 4 3 2 1
J J
I I
+V3.3S OPTIONAL ESD/HOTPLUG
PROTECTION DIODES
+V5S
2
D10 D11 D12
CRT CONN 3 3
SOT95P280-3N
3
SOT95P280-3N SOT95P280-3N
C231
0.1u
CC0402N
2
F1
f1206n
1
POP = NA
1
H J1
1 CRT_R_R
FB4 47 FB0603N GM_CRT_R 17 H
R GM_CRT_G 17
2 CRT_G_G FB5 47 FB0603N GM_CRT_B 17
G CRT_B_B
B 3
11 FB6 47 FB0603N
MS0 DAC1_DDC1DATA_B
DATA 12
4 R289 R290 R291
MS2 DAC1_DDC1CLK_B C232 C233 C234 150 ±1% 150 ±1% 150 ±1%
CLK 15
9 RC0402N RC0402N RC0402N
VCC DAC1_HSYNC_B 10pF 10pF 10pF
HS 13
14 DAC1_VSYNC_B CC0402N CC0402N CC0402N
VS
VSS1 5
VSS2 6
VSS3 7
C235 C236
G G
VSS4 8
VSS5 10
E1 33pF 33pF
E1 CC0402N CC0402N
E2 E2
POP = NA POP = NA
CRT_DB15
TH-CN-115X150P_VGA
For EMI BUFFER AND LEVEL SHIFT LOGIC

ASSUMING +5V CRT
+V5S
+V3.3S
F DAC1_RED 6
R292
2.2K
F
2
1 RC0402N R293
1
11 D13 2.2K
7 RC0402N
G
DAC1_GRN 2 3DAC1_DDC1DATA_B 3 2 CRT_DDC_DATA 17
DAC1_DDC1DATA 12 SOT95P280-3N D S
8 +V3.3S
DAC1_BLU 3
DAC1_HSYNC 13 Q9
1
DDC1VCC 9
4
2
DAC1_VSYNC 14 R294 R295
1
10 D14 2.2K 2.2K
DAC1_DDC1CLK 5 RC0402N RC0402N
G
E 15
+V5S
3DAC1_DDC1CLK_B
SOT95P280-3N
3
D S
2 CRT_DDC_CLK 17 E
CON_15PF_DSUB_RA
Q10
1
18
2
17 U9
1
5
16 D15
1 6
2 DAC1_RED 1 3 R296 39 RC0402N 4 2 CRT_HSYNC 17
15 11 SOT95P280-3N
3 7 C237
4 DAC1_GRN 2 0.1u
3
12 DAC1_DDC1DATA 12 CC0402N
D D
1
5 8
6 DAC1_BLU 3
8 DAC1_HSYNC 13
2
14 DDC1VCC 9 U10
1
5
9 4 D16
10 DAC1_VSYNC 14
7 10 3 R297 39 RC0402N 4 2 CRT_VSYNC 17
11 5 SOT95P280-3N
13 DAC1_DDC1CLK 15 C238
0.1u
3
CC0402N
1
CON 18PIN MINIVGA CON_15PF_DSUB_RA
OPTIONAL ESD/HOTPLUG
PROTECTION DIODES
C C
B B

5th floor,Block K,
A Title <Title>
A
Size Sheet Rev
FAN&Card reader
C Name A
10 9 8 7 6 5 4 3 2 1
NOTE:
Place one capacitor for two power pins.
+V3.3S
3.3V
J J
3.3V
3.3V
3.3V
C494 C495 C528 C529
0.1u 0.01uF 0.1u 0.1u
CC0402N CC0402N CC0402N CC0402N
4.7K POP = NA
4.7K POP = NA
GND_HDMI
4.7K
4.7K
+V5S
I SDA_SINK R76 2.2K RC0402N 5V I
R707
HPDINV R708
DDC_EN R709
R116
SCL_SINK R77 2.2K RC0402N
ccq,evt->dvt,0625
GND_HDMI
GND_HDMI
GND_HDMI
DC Coupled TMDS Signals
HPD_SINK
SDA_SINK
SCL_SINK
HPDINV R722 4.7K RC0402N
17 TMDS_DATAP2 IN_D2+ OVS R117 4.7K RC0402N POP = NA
OE_N
OVS
3.3V
3.3V
17 TMDS_DATAN2 IN_D2-
17 TMDS_DATAP1 IN_D1+
IN_D1- GND_HDMI
36
35
34
33
32
31
30
29
28
27
26
25
17 TMDS_DATAN1
U11
17 TMDS_DATAP0 IN_D0+
CFG/OVS
DDCBUF_EN/HPDINV
HPD_SINK
SDA_SINK
SCL_SINK
GND36
VCC33
GND31
GND27
VCC26
DDC_EN
OE#/OE_N
17 TMDS_DATAN0 IN_D0-
17 TMDS_CLKP IN_CLK+ GND_HDMI 37 24 GND_HDMI

GND37 GND24
H H
17 TMDS_CLKN IN_CLK- IN_CLK- 38 23 GM_OUT_CLK-
IN_CLK+ IN_D1- OUT_D1- GM_OUT_CLK+
39 IN_D1+ OUT_D1+ 22
17 HDMI_CTRLCLK SCL 3.3V 40 21 3.3V
SDA IN_D0- VCC40 VCC21 GM_OUT_D0-
17 HDMI_CTRLDATA Changed SDA and SCL Pull up on CPU side 41 SN75DP139 20
HPD_OUT IN_D0+ IN_D2- OUT_D2- GM_OUT_D0+
17 HDMI_HPD 42 IN_D2+ OUT_D2+ 19
GND_HDMI 43 18 GND_HDMI
GND43 GND18
HPD/HPD_SOURCE
IN_D1- GM_OUT_D1-
SDA/SDA_SOURCE
44 17
SCL/SCL_SOURCE
IN_D1+ IN_D3- OUT_D3- GM_OUT_D1+
45 IN_D3+ OUT_D3+ 16
3.3V 46 15 3.3V
VCC46 VCC15
REXT/VSADJ
IN_D2- GM_OUT_D2-
PC1/12C_EN
47 14
RT_EN#/NC
IN_D2+ IN_D4- OUT_D4- GM_OUT_D2+
48 13
PC0/SRC
IN_D4+ OUT_D4+
From Chipset or Gfx E1 GND_HDMI
GND12
VCC11
E1
GND1
GND5
VCC2
NOTE:
PS8101 4 pairs of TMDS input pins(IN_Dx+/IN_Dx-) are identical
G G
GND_HDMI 1
2
3
4
GND_HDMI 5
6
HPD_OUT 7
8
9
10
11
GND_HDMI 12
So TMDS CLK+/- and Datax+/- can be connected freely to any pair of TMDS input pins
Also positive and negtive can be swapped for each pair TMDS input pins
VSADJ
3.3V
3.3V
SDA
PC0
PC1
SCL
It's the same for PS8101 4 pairs of TMDS output pins
GND_HDMI R114 4.7K RC0402N

3.3V R710 4.7K RC0402N
3.3V R711 4.7K RC0402N R719
4.02k For PS8101 Value=499ohm
Recommended Equalization: [PC1,PC0]=01, 4dB
For SN75DP139 Value=4.02kohm
+V3.3S
F GND_HDMI
F
15
14
13
U44
DO-VCC1
D1- NC
D2- VCC
TPD8S009
GND11
GND2
GND5
GND8
DO+
D1+
D2+
D3+
D3-
For HDMI ESD
Place as close to the HDMI CONN as possible
1
2
3
4
5
6
7
8
9
10
11
12
E CN15 E
GND_HDMI
GM_OUT_D2+ OUT_D2+ 1
GND_HDMI 1
2 2
GM_OUT_D2- OUT_D2- 3
4 4
GND_HDMI 5
GM_OUT_D1- OUT_D1- 5
6 6
GND_HDMI 7
8 8
GM_OUT_D0- OUT_D0- 9 E1
GM_OUT_CLK+ OUT_CLK+ 9 E1
10 10 E2 E2
GND_HDMI 11 E3
GM_OUT_CLK- OUT_CLK- 11 E3
12 12 E4 E4
D SCL_SINK
+V3.3S R714 27K RC0402N POP = NA CEC_CONN
SCL_CONN
13
14
13
14
D
15 15
SDA_SINK SDA_CONN 16
GND_HDMI 16
17 17
+V5S F4 2 1 f1206n 18
HPD_SINK HPD_CONN 18
19 19
R146 C492 HDMI Source Receptacle Connector

20K 0.1u
RC0402N CC0402N
C GND_HDMI
C
1920x 1200 @ 60 Hz using HDMI
B B

5th floor,Block K,
A Title <Title>
A
Size Sheet Rev
HDMI Port
C Name A
5 4 3 2 1
+V3.3A R309 0 RC0805N POP = NA
U22
5 VIN
1 VDD33
R451 0 RC0402N POP = NA 4 VOUT
SS
C229 C330 C332 3 2 C240 C241 C242 C243 C244 C245
10uF 1uF 0.01uF EN/ENBGND 10uF 10uF 0.1u 0.1u 0.1u 0.1u
CC1206N CC0603N CC0402N APL3512A/B CC1206N CC1206N CC0402N CC0402N CC0402N CC0402N
POP = NA SOT95P280-5N POP = NA POP = NA
Remove R423 and R426 for RTL8102EL application.
D R423 and R426 are used in the RTL8111DL application. D
Tss=0.2*Css*Vin C242 C243 C244 are for 8102EL VDD33 pins-- 1, 29, 37.
Set Tss=6.6ms C242 C243 C244 C245 are for 8111DL VDD33 pins-- 1, 29, 37, 40. Remove R315 if switching regulator is enabled. Remove R312 if
external power 1.2V is used.
30,34 LAN_VDDEN R417 0 RC0402N
XTAL2 C246 20PF CC0402N

R1117
10k C344 C346 are only for 8111DL
2
RC0402N X6
X5 25MHZ
C252 C253 C254 HC-49U/S X8A025AFK1H
0.1u POP = NA ccq,evt->dvt,0625
1
10uF 10uF CC0402N
VDD33
XTAL1 C255 20PF CC0402N
POP = NAPOP = NA
R312 0
RC0603N
Use 0 ohm for 8102EL application POP = NA
R433 value should be 2.49K R314
R310 0 RC0805N * C387 and C389 are for U38 EVDD12 pin 19. R312 is only required by RTL8102EL
L2 4.7uH
(1%) for all application. 2.49K
R315 0
CTRL12A 1 2 POP = NA R311 0 RC0603N POP = NA EVDD12

LC5757N RC0603N POP = NA
C250 C251 R316 1K RC0402N
C247 C248 C249 1uF 1uF
L23 4.7uH 10uF 10uF 0.1u CC0402N CC0402N
CTRL15/VDD33
1 2 POP = NA CC1206N CC1206N CC0402N
DVDD12
CTRL12/VDD
CTRL12/VDD
CTRL12A
VDD33
VDD33
LC4040L U12
XTAL2
XTAL1
RSET
GND
POP = NA POP = NA EECS 1 8 VDD33
CS VCC
Note 1: The Trace length Dual Lay EESK 2 SK DC 7 C261
between L1 and 8111DL's Pin Remove R468&R469 in 8102EL application EEDI

EEDO
3 DI ORG 6 0.1u
4 5 CC0402N
DO GND
1 must be within 0.5 cm. C29 C29 C32 are only for RTL8111DL. POP = NA
48
47
46
45
44
43
42
41
40
39
38
37
and C54 to L8 must be within U13 RC0603N R317 3.57K +V3.3A
C R313 C
0.5cm. Refer to Layout guide
VCTRL12A/SROUT12
GND4
RSET
REFCLK_N03EL/11DL NC/ENSWREG
VCTR12DVDDSR
CKTAL2
CKTAL1
REFCLK_PRTL8102EL/ NC/VDDSR
NC/AVDD332
NC/LV_PLL
LED0
VDD33
0
for more detail. RC0603N * C372 C379 C388 C392 C393 are for 8111DL DVDD12 pins-- 10, 13, 30, 36, 39. VDD33 DVDD12
POP = NA 1 36
MDI0+ AVDD331 DVDD123 EESK
2 MDIP0 LED1/EESK 35
* C372 C379 C388 C392 are for 8102EL DVDD12 pins-- 10, 13, 30, 36. MDI0-
DVDD12
3 MDIN0 LED2/EEDI 34 EEDI
EEDO
4 NC/FB12 LED3/EEDO 33
MDI1+ 5 32 EECS
DVDD12 MDI1- MDIP1 EECS GND +V3.3S
6 MDIN1 GND3 31
GND 7 30 DVDD12
C256 C257 C258 C259 C260 MDI2+ GND1 DVDD122 VDD33
8 NC/MDIP2 VDD331 29
0.1u 0.1u 0.1u 0.1u 0.1u MDI2- 9 28 ISOLATEB R318 1k RC0402N
NC/MDIN2 ISOLATEB
VDDTX/EVDD12
CC0402N CC0402N CC0402N CC0402N CC0402N DVDD12 10 27 PERSTB R321 0 RC0402N BUF_PLT_RST# 7,18,29,30,34
MDI3+ DVDD12/AVDD12 PERSTB LANWAKEB
11 NC/MDIP3 LANWAKEB 26 PCIE_WAKE# 17,29,30
POP = NA MDI3- 12 25
DVDD121
NC/MDIN3 CLKREQB CLK_LAN_OE# 16
NC/GPO
R322
NC/NC
HSON
EGND
HSOP
GND2
15K±1%
HSIN
HSIP
RC0603N
48_RTL8102EL/11DL
13
14
15
16
17
18
19
20
21
22
23
24
Pin 23 is GPO pin for
EVDD12
REFCLK+
DVDD12
REFCLK-
8111DL. It is used for
HSON
HSOP
GND
HSIP
GND
HSIN
For RTL8111DL, use this block For RTL8102EL, use this block. DSM function.
VDD33 R319 0 RC0603N CTRL12/VDD DVDD12 R320 0 RC0603N CTRL12/VDD
C263 0.1u CC0402N
POP = NA PCIE_RXN3_LAN 16
HSIP C264 0.1u CC0402N
16 PCIE_TXP3_LAN PCIE_RXP3_LAN 16
HSIN
16 PCIE_TXN3_LAN CLK_PCIE_LAN_N 16
CLK_PCIE_LAN_P 16
B B
R323 0 RC0402N
3
B3
330mA 4
GND
POP = NA
2 1
B2 FIL1 UNB
R324 0 RC0402N
R325 0 RC0402N U14 HS00-04078
3 330mA 4 U15 HS00-04078
CN5 B3 GND MDI0+ LAN_TX0P
7 TD+ TX+ 10
POP = NA MDI2+ 7 10 LAN_TX2P
MDI0- LAN_TX0N TD+ TX+
2 1 8 TD- TX- 9
E1 1
B2 FIL2 UNB
LAN_TX0P MDI2- 8 9 LAN_TX2N
E1 P1 R326 0 RC0402N LAN_TX0N MDI1+ LAN_TX1P TD- TX-
E2 E2 P2 2 1 RD+ RX+ 16
3 LAN_CT MDI3+ 1 16 LAN_TX3P
P3 LAN_TX1P MDI1- LAN_TX1N RD+ RX+
P4 4 2 RD- RX- 15
5 LAN_TX1N MDI3- 2 15 LAN_TX3N
P5 LAN_CMT V_DAC LAN_CT RD- RX-
P6 6 3 CT1 CT3 14
7 R327 0 RC0402N LAN_TX2P V_DAC 3 14 LAN_CT1
P7 CT1 CT3
P8 8 2B2 FIL3 UNB 1 LAN_TX2N V_DAC 6 CT2 CMT 11 LAN_CMT
POP = NA LAN_CT1 V_DAC 6 11 LAN_CMT1
CT2 CMT
4 NC1 NC3 12
B3
3 GND
4 LAN_TX3P C266 4 12
330mA C270 NC1 NC3
5 NC2 NC4 13
R328 0 RC0402N LAN_TX3N 0.1u 5 13
0.1u C271 C272 NC2 NC4
R329 0 RC0402N smd-transf-127p-16n
R330 R331 R332 0.1u 0.1u smd-transf-127p-16n
2B2 FIL4 UNB 1 75 75 75 LAN_CMT1 POP = NA
POP = NA LAN_TX2P R334 0 R335 0
POP = NA R333 LAN_TX2N R337 0
B3
3 GND
4 75 C265 LAN_TX3P R338 0 R339 0 LAN_N1
330mA LAN_N1 POP = NA LAN_TX3N R340 0
R336 0 RC0402N 0.1u R487 0 RC0603N
C269 R486 0 RC0603N

A C267 C268 ccq,dvt->pvt,1008 A
1000pF 1000pF 0.01uF R485 0 RC0603N
CC1206N CC0402N
POP = NA R484 0 RC0603N
FB8 47 FB0603N
POP = NA
5th floor,Block K,
only smt one of C339 and C342 ,dual layout C273 0.01uF Xiamen Exprot Processing Zone,
C274 1000pF
Title <Title>
Size Sheet Rev
PCIE-LAN
C Name A
5 4 3 2 1
8 7 6 5 4 3 2 1
<<Attention>>
Surges of PVDD >7V duration 0.1ms when
class D amplifier is working may damage
MICR-VREFO
the amplifier, 10uF tantalum capacitors HP_OUT_L
+V5S +V5_PVDD
are required at PVDD1 and PVDD2 to MIC2-VREFO FB17 120R
HP_OUT_R
FB0805N
suppress the surge. MICL-VREFO
AC_VREF
C465 10uF CC1206N
AGND Place next to pin 27
AGND C474 0.1u CC0402N
D D
+V5_AVDD +V5S +V5_AVDD
C472 +V5_AVDD FB18 120R
C471 2.2UF FB0805N
2.2UF
C462 C461 CC0603N CC0603N
0.1u 10uF Place next to pin 38
CC0402N CC1206N C422 C468 Place next to pin 25
AGND U16 0.1u 10uF
36
35
34
33
32
31
30
29
28
27
26
25
ALC269 CC0402N CC1206N
CBP
CPVEE
HPOUT-L
CPVREF
MIC2-VREFO
VREF
MIC1-VREFO-L
AVSS1
AVDD1
CBN
HPOUT-R
MIC1-VREFO-R
AGND
+V5_PVDD 37 24 AGND
AVSS2 LINE1-R
38 AVDD2 LINE1-L 23
39 22 C421 4.7uF R360 1K RC0603N AUD_MIC_IN_R R342 4.7K MICR-VREFO
PVDD1 MIC1-R RC0603N AUD_MIC_IN_L R349 4.7K MICL-VREFO
Place next to pin 39,and C419 C417 C420 SPK_L+ 40 SPK-OUT-L+ MIC1-L 21 C433 4.7uF R363 1K
Tantalum capacitor is 0.1u 4.7uF 4.7uF SPK_L- 41 20
CC0402N CC0805N CC0805N SPK-OUT-L- MONO-OUT R361 20K RC0402N R356 Placement near Audio Codec MIC2-VREFO R341 4.7K
required for C303 42 PVSS1 JDREF 19 AGND CN21
43 PVSS2 Sense B 18 B1
+V5_PVDD SPK_R- 44 17 C478 2.2uF CC0603N AUD_MIC2_IN_R 2 E2
SPK_R+ SPK-OUT-R- MIC2-R C479 2.2uF CC0603N AUD_MIC2_IN_L 2 E2
45 SPK-OUT-R+ MIC2-L 16 1 D
46 PVDD2 LINE2-R 15 AGND 2 S
47 14 1 E1
SDATA-OUT
C467 C466 C454 EAPD/SPDIFO2 LINE2-L 090814 1 E1
48 13
SDATA-IN
GP0/DMD
GP1/DMC
Place next to pin 46,and SPDIFO Sense-A
DVDD-IO
PCBEEP
RESET#
0.1u 4.7uF 4.7uF R343 39.2K RC0603N EARPHONE_SEL
Tantalum capacitor is 20K
DVDD
ccq,evt->dvt,0625
SYNC
CC0402N CC0805N CC0805N R347 MUTE_MIC POP = NA
DVSS
BCLK
PD#
required for C237 AGND
ANALOG
E1
Placement near Audio Codec FB32 120R
+V3.3S FB0805N POP = NA
E1
1
2
3
4
5
6
7
8
9
10
11
12
+V3.3S
0929 增加 R345 0 RC0603N 091217:增加AGND
DIGITAL 090814 R346 0 RC0603N

+V3.3S +V1.5S R532 0 RC0603N
C469 C470 (Include Thermal pad) R354 0 RC0603N
10uF 0.1u TP14 R531 0 RC0603N
R479 R476 C473 CC0805N CC0402N
C 10K 10K R348 0.1u Dennis Modify R445 R458 AGND R488 0 RC0603N ccq,dvt->pvt,1008 C
RC0402N RC0402N 10K CC0402N 0 0 Digital_ground
U17 RC0603N RC0603N R528 0 RC0603N
5
POP = NA
HDA_RST# 15
1 Tied at one point only under the R529 0 RC0603N
34 EC_MUTE# HDA_SYNC 15
4 PD#
ALC269 or near the ALC269
15 HDA_RST# 2
R359
3
R477 22 RC0402N C392 C393

HDA_SDATAIN0 15
3
1K Q16 R351 22 RC0402N 10uF 0.1u

D
HDA_BITCLK 15
3
RC0402N BSS138 HDA_SDATAOUT 15 CC0805N CC0402N AGND
S D
1
G
S
1 Q17 C423
G SOT95P280-3N
2
R350 OTR2N7002LT1 22pF

2
10K CC0402N
POP = NA
RC0402N
<<Attention>>
For power_on/off de-pop circuit and system booting warning
signal: Please System BIOS Engineer Note :
1. If you want the system make warning signal after power on
, please let EC_MUTE# High first.
2.When you want to exit your Bios Programming Code, please let
the EC_MUTE# Low.(The programming is different from before . )
PD#=0V : Power down Class D SPK amplifer

PD#=3.3V : Power up Class D SPK amplifer
091015 更改
SPK_L+ R352 120R
FB0805N
C389
B B
1uF BAR 1.25T-2-4PWB-T
POP = NA
ccq,evt->dvt,0625 C390 L_OUT+ 4
L_OUT- P4 J2
1uF 3 P3 E2 E2
C475 POP = NA R_OUT+ 2 E1 010030FR006G100ZL
SPK_L- R353 120R AGND R_OUT- P2 E1 ccq,evt->dvt,0625 180.0 ohm
1uF 1 P1 6
FB0805N POP = NA AGND FB19 FB0603N 1
SPK_R+ R355 120R CN6 HP_OUT_L R364 75 RC0402N FB21 180.0 ohm 2
HP_OUT_L
FB0805N FB0603N
C476 HP_OUT_R R356 75 RC0402N FB26 180.0 ohm 3
HP_OUT_R
1uF AGND FB0603N EARPHONE_SEL 4
POP = NA 5
C391 C463 C464
1uF 100pF 100pF
C477 POP = NA CC0402N CC0402N
SPK_R- R357 120R AGND 1uF
FB0805N POP = NA
AGND
AGND
<<Attention>>
If mount the LC filter((L9~L12;C295/C299;C300/C293/C294/C296),Please let them
together and close to codec. If the PCB trace and Speaker wire length is
less than 20cm, don't need the LC filter(L9~L12;C295/C299) to eliminate the
EMI,If L9,L0,L11,L12 are replaced by 0 ohm/1.6A resistetor(please don't use J3
010030FR006G100ZL
general bead, because it may influence the THD+N quality) ,and C295,C299 MUTE_MIC 5
should be NC.And,please make the trace length/ Speaker wire length of ccq,evt->dvt,0625 4
SPKL+/L-/R+/R- be the same as possible as you can. AUD_MIC_IN_R FB22 180.0 ohm 3
FB0603N
C300/C293/C294/C296 are reserved for EMI fine-tune ; For EMI issue, please AUD_MIC_IN_L FB23 180.0 ohm 2
also refer our ALC269 Layout guide document FB0603N 1
6
C459 C460
A 100pF 100pF FB24 A
CC0402N CC0402N 180.0 ohm
FB0603N
AGND AGND conect to claw

AGND 5th floor,Block K,
Title <Title>
Size Sheet Rev
Audio Codec
C Name A
8 7 6 5 4 3 2 1
10 9 8 7 6 5 4 3 2 1
J J
I I
H H
G G
F F
E E
D D
C C
B B

5th floor,Block K,
A Title <Title>
A
Size Sheet Rev
Audio Jack
C Name A
ENGINEER: Ivan Date: Thursday, April 01, 2010 Sheet 27 of 44
10 9 8 7 6 5 4 3 2 1
J J
Cardreader
SD/MS/MMC Combo
I I
RC0402N
REG_3V3
REG_1V8
D3V3
0
C262 C852
2.2uF R80 4.7UF
R777
CC0603N 0 CC0603N
REG18_VDD18
+V3.3S
SM/SD/MS_D7
SM/SD/MS_D6
SM/SD/MS_D5
RC0603N
H H
C595 REG_3V3
DGND
D3V3
0.1u
CC0402N
C851 R192
2.2uF 30k ±1%
36
35
34
33
32
31
30
29
28
27
26
25
U49 CC0603N RC0603N
REG18Vout
REG33Vout
REG33Vin
SM/SD/MS_D7
GPIO6
SM/SD/MS_D6
GPIO5
SM/SD/MS_D5
GPIO1
GPIO4
VSS26
TC
ccq,dvt->pvt,1008
37 GPIO7 REG5Vin 24
XTALI R779 0 RC0402N CLK12M_OUT 38 23 C853
SM_CE/SD_WP Clk12M-out LED/GPIO0 SM/SD/MS_D4 4.7UF
39 SM_CE/SD_WP SM/SD/MS_D4 22
SD_CLK/MS_CLK FB28 220 FB0603N SM_WP 40 21 RST CC0603N
DGND SM_WP/SD_CLK/MS_CLK RST
G G
41 VSS41 GPIO3 20
SM_WP_SW/SD_CMD/MS_BS
SM_WR
ccq,evt->dvt,0625 C600 0.1u
42 SM_WR
IT1337E-48 ClkSel 19 CLKSEL R387 0 RC0402N
43 SD/MS/xD 18 SM/SD/MS_D3
C601 0.1u POP = NA CC0402N EE_SDA SM/SD/MS_D3
44 EE_CLK SM_CD 17
CC0402N D3V3 45 16 SM_ALE
R768 0 RC0402N AVDD33 SM_ALE PWR_SW
18 USB_PP2 46 DP PWR_SW2 15 PWR_SW
R767 0 RC0402N 47 14 D3V3
SM_RNB/SD_CD
18 USB_PN2 DM VDD33
SM_RD/MS_INS
DGND 48 13 DGND
SM/SD/MS_D0
SM/SD/MS_D1
SM/SD/MS_D2
AVSS VSS13 C596 C598
0.1u 1uF
SM_CLE
CC0402N CC0402N
Clk-48M
XTALO
VDD18
xD_CD
XTALI
IT1337E/FN
1
2
3
4
5
6
7
8
9
10
11
12
F F
SM_CLE
XD_CD
C599 20PF CC0402N POP = NA XTALO
C534
SD_CMD/MS_BS
SM_RNB/SD_CD
R770 0.1u
SM_RD/MS_INS
REG18_VDD18
SM/SD/MS_D0
SM/SD/MS_D1
SM/SD/MS_D2
X8 270K CC0402N
48MCLK_IN
OSC-2 RC0603N
POP = NA
POP = NA
C597 20PF 1
CC0402N POP = NA XTALI
CN12
R1090 0 RC0402N POP = NA SM_RNB/SD_CD CD SD

E SM/SD/MS_D3
SD_CMD/MS_BS
S1
S2
CD
CD/DAT3
CMD
6 CLK_CD48
R388 0 RC0402N
E
DGND S3
PWR_SW VSS1_SD
S4 VDD
SD_CLK/MS_CLK S5
DGND CLK
S6 VSS2_SD
SM/SD/MS_D0 S7
SM/SD/MS_D1 DAT0
S8 DAT1 E4 E4
SM/SD/MS_D2 S9 E3
DAT2 E3
SM_CE/SD_WP WP1 E2
R1089 0 RC0402N POP = NA WP2 WP1 E2
WP2 WP2 E1 E1
DGND M1 PWR_SW REG_3V3

SD_CMD/MS_BS VSS1_MS
M2 BS
D R781
0
SM/SD/MS_D1
SM/SD/MS_D0
SM/SD/MS_D2
M3
M4
DATA1
DIO/D0 R286 2.2K RC0402N SM_CE/SD_WP R280
D
RC0402N M5 DATA2
SM_RD/MS_INS M6 INS
MS 1k
ccq,dvt->pvt,1008 SM/SD/MS_D3 M7 R287 10k RC0402N SM_WR RC0402N
SD_CLK/MS_CLK DATA3
M8 SCLK
PWR_SW M9 R288 1M RC0402N SM_RD/MS_INS
DGND VCC XD_CD
M10 VSS2_MS R358 47K RC0402N SM_RNB/SD_CD
3 IN 1 Connector
C C
B B

5th floor,Block K,
A Title <Title>
A
Size Sheet Rev
Card reader
C Name A
5 4 3 2 1
D D
+V3.3S
C316 C317 C318

10uF 0.1u 0.1u
Minicard
CC1206N CC0402N CC0402N
POP = NA
+V1.5S
C319 C320 C321

10uF 0.1u 0.1u
ccq,dvt->pvt,1008 CN9 CC1206N CC0402N CC0402N
C 1 2 POP = NA C
17,25,30 PCIE_WAKE# WAKE# +3.3V_1 +V3.3S
3 RSVD1 GND7 4
R530 0 RC0402N 5 6
34 BT_ON POP = NA RSVD2 +1.5V_1
16 CLK_WLAN_OE# 7 CLKREQ# UIM_PWR1 8
9 GND1 UIM_DATA 10
11 12 R371
16 CLK_PCIE_WLAN_N REFCLK- UIM_CLK 10k +V3.3S
16 CLK_PCIE_WLAN_P 13 REFCLK+ UIM_RESET 14
15 16 RC0402N
GND2 UIM_Vpp POP = NA
KEY
17 RSVD3 GND8 18
19 20 R373 0 RC0402N
RSVD4 W_DISABLE# WIRELESS_ON 34
21 22 R374 0 RC0402N
GND3 PERST# BUF_PLT_RST# 7,18,25,30,34
16 PCIE_RXN1_WLAN 23 PER_N0 +3.3V_AUX 24
25 26 C322
16 PCIE_RXP1_WLAN PER_P0 GND9 0.1u
27 GND4 +1.5V_2 28
29 30 R375 0 RC0402N SMB_CLK_S2 6,13,16,30 CC0402N
GND5 SMB_CLK R376 0 RC0402N
16 PCIE_TXN1_WLAN 31 PET_N0 SMB_DATA 32 SMB_DATA_S2 6,13,16,30
16 PCIE_TXP1_WLAN 33 PET_P0 GND10 34
35 GND6 USB_D- 36 USB_PN1 18
+V3.3S 37 38
RSVD5 USB_D+ USB_PP1 18
39 RSVD6 GND11 40
41 RSVD7 LED_WWAN# 42
43 RSVD8 LED_WLAN# 44
45 C_CLK LED_WPAN# 46
47 C_DAT +1.5V_3 48
49 C_RST GND12 50
51 RSVD12 +3.3V_2 52
E1
E2
E3
071CAAAZ40B
E1
E2
E3
B B
MH10
ccq,evt->dvt,0625
Dual lay for half card.
Ivan Modify
A A

5th floor,Block K,
Title <Title>
Size Sheet Rev
Minicard1
C Name A
5 4 3 2 1
10 9 8 7 6 5 4 3 2 1
Dual Lay with U23 PIN1 to PIN4
R2 0 RC0402N
J J
39 V1.1S_PWRGD
+V3.3S
C802 0.1u CC0402N

ccq,evt->dvt,0625 POP = NA
U23
SN74LVC1G08DCKR
5
sot65p190-5n
R162 0 RC0402N 1 POP = NA
POP = NA 4
+V3.3A V1.5S_PWRGD 2
+V3.3A
3
C726 +V3.3S
I R19
499K±1%
RC0402N
POP = NA U8
0.1u
CC0402N
POP = NA C572 0.1u CC0402N
I
V1.1S_OUT 1 8
TLV3492_REF OUTA +V 1.5S_OUT R17 0 RC0402N U32
2 -INA OUTB 7
3 6 TLV3492_REF POP = NA SN74LVC1G08DCKR
+INA -INB
5
4 5 sot65p190-5n
R18 -V +INB +V3.3A
7,38 V1.1S1.5S_PWRGD 1
160K±1% TLV3492 4 PM_MEPWROK 17
RC0402N SOT65P280-8N 2
38 DDR3VR_PWRGD
POP = NA POP = NA
R452
3
0 +V3.3S
+V1.1S +V1.5M_CPU RC0402N R1077 R1084
POP = NA 100k 10k
RC0402N RC0402N C578 0.1u CC0402N POP = NA
SET:Vref=800mv POP = NA POP = NA R555
R129 1K +V3.3S
R127 ccq,evt->dvt,0625 100k,±1% U29
H H
RC0402N
3
20K ±1% RC0603N SN74LVC1G08DCKR R904 0 RC0402N POP = NA
PM_PCH_PWROK 17
5
RC0402N POP = NA Q96 sot65p190-5n C645 0.1u CC0402N POP = NA
S D
S D
POP = NA Q93 2N7002LT1 39 PM_1.5S1.1SMPWRGD 1
1 BSS138 1 POP = NA 4 ALL_SYS_VRPWRGD 34
G POP = NA G U30
39 V1.1S_VTT_PWRGD 2
2
SN74LVC1G08DCKR
5
R125 R130 C188 R456 R556 sot65p190-5n
3
120k±1% C764 150k ±1%
±1% 0.01uF 1M 10k 1
RC0603N 0.022uF RC0402N CC0402N RC0402N RC0402N 4 R756 0 RC0402N
PM_PCH_PWROK 17
POP = NA CC0402N POP = NA POP = NA 2
34 DELAY_VR_PWRGOOD
±1% POP = NA POP = NA R757 0 RC0402N
SYS_PWROK 17
3
R557
R596 2.2K 10k
H_VTTPWRGD 7
Dual Lay for V1.5S_PWRGD RC0402N
R824
1K±1%
3
RC0402N
Q108
S D
G 38,42 PS_S3CNTRL PS_S3CNTRL 1 G
BSS138
SOT95P280-3N
G
2
CDMA
F 7,38
38
17,25,29
25,34
V1.1S1.5S_PWRGD
DDR3VR_PWRGD
PCIE_WAKE#
LAN_VDDEN
F
34,41 VR_PWRGOOD
22,34 BLCTL
34,41 IMVP_VR_ON
+V3.3S C351 C427 C428 C429 C436 C437 C594
0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u
C488 C489
10uF 0.1u
CC1206N CC0402N
+V1.5S
E C487
10uF
C485
0.1u
E
CC1206N CC0402N
CN10 +VCC_SIM
17,25,29 PCIE_WAKE# 1 WAKE# +3.3V_1 2

3 4 +V3.3S
RSVD1 GND7
5 RSVD2 +1.5V_1 6
16 CLK_3G_OE# 7 CLKREQ# UIM_PWR1 8
9 10 RC0402N 0 R574 SIM_IO
GND1 UIM_DATA RC0402N 0 R610 SIM_CLK R492
16 CLK_PCIE_3G_N 11 REFCLK- UIM_CLK 12
13 14 RC0402N 0 R611 SIM_RST 10k +V3.3S
16 CLK_PCIE_3G_P REFCLK+ UIM_RESET RC0402N
15 GND2 UIM_Vpp 16
090814 POP = NA
KEY 4.7K R261 R382
17 RSVD3 GND8 18 RC0402N
R379 0 RC0402N
0
RC0603N
SIM CARD +VCC_SIM
D D
19 RSVD4 W_DISABLE# 20 3G_LED 32,34
21 22 R383 0 RC0402N
GND3 PERST# BUF_PLT_RST# 7,18,25,29,34
23 24 C530
16 PCIE_RXN2_3G PER_N0 +3.3V_AUX 0.1u C486 C484
16 PCIE_RXP2_3G 25 PER_P0 GND9 26
27 28 CC0402N 10uF 0.1u
GND4 +1.5V_2 POP = NA R693 0 RC0402N CC1206N CC0402N C493
29 GND5 SMB_CLK 30 SMB_CLK_S2 6,13,16,29
31 32 R694 0 RC0402N 090814 0.1u C491
16 PCIE_TXN2_3G PET_N0 SMB_DATA SMB_DATA_S2 6,13,16,29
33 34 CC0402N 2.2uF
16 PCIE_TXP2_3G PET_P0 GND10 R712
35 36 CC0603N
+V3.3S GND6 USB_D- USB_PN11 18 100k
37 RSVD5 USB_D+ 38 USB_PP11 18
39 40 RC0402N
RSVD6 GND11
41 RSVD7 LED_WWAN# 42 POP = NA
43 44 R381 SIM1
RSVD8 LED_WLAN# 10k
45 C_CLK LED_WPAN# 46 C1 VCC
47 48 RC0402N SIM_RST C2
C_DAT +1.5V_3 SIM_CLK MCLR/RST
49 C_RST GND12 50 C3 RB6/Oscl/CLK
51 RSVD12 +3.3V_2 52 C5 VSS/GND
C6 VPP
SIM_IO C7 RB7/I/O
D1
E1
E2
E3
ccq,evt->dvt,0625 CLK_3G_OE#_R D1
D2
C C
ccq,dvt->pvt,1124 D2
E1
E2
E3
071CAAAZ40B C490 E1 254070FB008XX05ZL

22pF E1
E2 E2
CC0402N
C283
100pF SMD-SIM-CN-127P-8N
CC0402N
POP = NA
CLK_3G_OE# RC0402N 0 R591
MH20 +VCC_SIM
B C1
C5
SIM2
C1
B
SIM_RST C5
C2 C2
C6 C6
SIM_CLK C3 C3
Dual lay for half card. SIM_IO C7 C7
254070FB006S103ZL
E1 E1
E2 E2
Ivan Modify E3 E3
SMD-SIM-127P-6N
POP = NA
Dual Lay 5th floor,Block K,
A A
Title <Title>
Size Sheet Rev
3G Card & Power Good
D Name A
ENGINEER: Ivan Friday, December 10, 2010 30 of 44
Date: Sheet
10 9 8 7 6 5 4 3 2 1
10 9 8 7 6 5 4 3 2 1
J J
TO HDD BOARD
+V5S +V3.3S
+V5S_CAM CN7 CN25
18 USB_PN12 1 1 1 1
U18 18 USB_PP12 2 2 E1 2 E1
R365 E1 2 E1
5 VIN 18 USB_OC6# 3 3 E2 E2 3 3 E2 E2
1 0 POP = NA 4 4 4
VOUT 4
I Tss=0.2*Css*Vin
C311
R366
C312
0 RC0402N POP = NA
C313
4 SS
C314 C315
RC0603N 15
15
SATA_TXP0
SATA_TXN0
5 5
6 6
5
6
5
6
I
3 EN/ENBGND 2 7 7 7 7
10uF 1uF 0.01uF 0.1u 10uF 8 8 8
15 SATA_RXN0 8
CC1206N CC0603N CC0402N APL3512A/B CC0402N CC1206N C480 C481
15 SATA_RXP0 9 9 9 9
POP = NA SOT95P280-5N 0.1u 10uF 10 10 10 10
CC0402N CC1206N 11 11 11
POP = NA POP = NA 11
12 12 12 12
13 13 13 13
14 14 14 14
15 15 15 15
16 16 16 16
R367 0 RC0402N
34 Camera_ON
USE APL3512A High Enable +V5S POP = NA

H R368
10k
H
RC0402N
POP = NA
Camera CONN--Dual lay with LCD CONN
C482 C483
GND 10uF 0.1u
CC1206N CC0402N
G G
Bluetooth CONN TO USB BOARD

F CN8
F
1 +V5S
1
18 USB_PP10 2 2 CN16
18 USB_PN10 3 3 E1 E1
+V3.3S 4 E2 1
R369 0 RC0402N 4 E2 1
34 BT_ON 5 5 2 2
R370 0 RC0603N 6 3
6 3
4 4
18 USB_PP8 5 5
ccq,dvt->pvt,1124 6 E1
18 USB_PN8 6 E1
18 USB_OC4# 7 7 E2 E2
8
E 18
18
USB_PP4
USB_PN4
9
10
8
9
10
E
18 USB_OC2# 11 11
12 12
GND
Ivan Modify GND
D D
C C
B B

5th floor,Block K,
A Title <Title>
A
Size Sheet Rev
SATA&Camera&BT
C Name A
5 4 3 2 1
D D
POP = NA
+V3.3S R635 LED11
2 3 100 2 1
Q71 ledc0603n
OTRDTC144EUA POP = NA +V3.3A
POP = NA
34 CHG_LED
1
R616 LED2 R621 LED1
2 3 100 2 1 2 3 100 2 1
34 CAPLOCK_LED
Q56
OTRDTC144EUA
ledc0603n
LED 34 CHG_LED
Q55
OTRDTC144EUA
ledc0603n
1
1
R618 LED3
100 2 1
15 SATA_LED# 090814 BOISTAR兼容设计
C C
ledc0603n
R619 LED5
34 PWR_LED_RED
1
2 3 100 2 1
Q58 Q57 OTRDTC144EUA POP = NA
ledc0603n R612 LED4
OTRDTC144EUA 2 3 100 2 1
34 NUMLOCK_LED
1
POP = NA POP = NA ledc0603n

R620 LED7
2 3 100 2 1 Q59 R613 LED6
Q70 2 3 100 2 1
ledc0603n
OTRDTC144EUA POP = NA ledc0603n
R617 0 RC0402N POP = NA OTRDTC144EUA POP = NA
34 WIFI_LED
1
34 PWR_LED_GRN
1
R614 0 RC0402N
30,34 3G_LED
1
Q62 OTRDTC144EUA
R615 LED8
2 3 100 2 1
ledc0603n
34 PWR_LED_RED
1
+V3.3A
Q81 OTRDTC144EUA
R651 LED10
2 3 100 2 1
B B
ledc0603n
Q82 R687 LED9

2 3 100 2 1
ledc0603n
ME 34 PWR_LED_GRN
OTRDTC144EUA
1
090814
MH1
MH2
MH3
MH4
MH12
MH5
MH8
MH7
MH13
090820 MH11
MH21
MARK1 MARK2
A A
MARK3 MARK4
MARK5 MARK6
5th floor,Block K,
MARK7 MARK8
Title <Title>
Size Sheet Rev
USB Port3 & LED & ME
C Name A
5 4 3 2 1
5 4 3 2 1
+V5S
X[0..15]
Keyboard Connector
34 X[0..15]
D D
C574 C575 X15 28
X2 28
27 27
10uF 0.1u X0 26 +V3.3A
X3 26
25 25
X11 24
X8 24
CN18 23 23
GND X9 Y0 R629 10k
22 22
X7 Y1 R624 10k
1 1 21 21
X12 Y2 R623 10k
2 2 20 20
X1 Y3 R627 10k
3 3 16 16
X6 Y4 R625 10k
4 4 18 18
X5 Y5 R628 10k
5 5 17 17
X13 Y6 R622 10k
E1 E1 6 6 19 19
X14 Y7 R626 10k
E2 E2 7 7 15 15
8 TBCLK Y[0..7] X10 14
8 TBDATA TBCLK 34 34 Y[0..7] Y5 14
9 9 TBDATA 34 13 13 E2 E2
10 Y4 12 E1
10 Y7 12 E1
11 11 11 11
12 X4 10
12 Y6 10
9 9
Y0 8
Y2 8 GND
7 7
C576 C579 Y3 6
Y1 6
5 5
47pF 47pF 4
CC0402N CC0402N 4
3 3
2 2
1 1
GND
Connect to Touch PAD GND CN19
090814
TO KEY_BOARD
C C
CN20
1 1
E1 E1 2 2
E2 E2 3 3
4 4
GND
Connect to L R button
TO TP_BOARD
+V3.3A +V3.3S
R695 R696 M40 Modify

0 0
RC0402N RC0402N
B
SW_BOARD FUNCTION POP = NA B
OCH168WAD R630
C580
SW1 SW2 U36
3 NC3 VDD 4 VDD 1 10k
4 3 status 4 3 0.1u
4 3 3G_ON 34 4 3 POWSW# 35
5
2 3 RC0402N SN74LVC1G04DCKR CC0402N
GND GND R632 sot65p190-5n
6 6 5 5 6 6 5 5
1 5 2 2 4 -LID R631 0 RC0402N LID 34
NC1 OUT OUT
1
2 2 1 1 2 2 1 1 U26 1k
BU52021HFV U34
3
TMG-533-S-T/R(180GF) TMG-533-S-T/R(180GF) sop50p160-5n RC0402N
SW_TMG-53N SW_TMG-53N POP = NA
Ivan Modify
SW3
4 4 3 3 WIFI_BUTTON 34
6 6 5 5
2 2 1 1
A A
TMG-533-S-T/R(180GF)
SW_TMG-53N

5th floor,Block K,
Title <Title>
Size Sheet Rev
Main_Board CONNECTOR
C Name A
5 4 3 2 1
5 4 3 2 1
+V3.3A_KBC
+V3.3A +V3.3A_KBC
+V3.3A_RTC
Layout Note:
R389 0 RC0402N VBAT
Recommended net "+V3.3A" and R378 0 RC0805N POP = NA
R390 0 RC0402N POP = NA "+V3.3A_RTC" minimum trace
width 12mils.
R391 +V3.3A_KBC
0 L80LLAT R392 0 RC0402N
RC0402N L80HLAT R393 0 RC0402N
POP = NA R394 0 RC0402N 1.8432Mhz_IN I2C_CLK3 R395 10k RC0402N
35 SMC_SHUTDOWN# R396 0 RC0402N POP = NA
15 SPI_MISO
R397 0 RC0402N POP = NA I2C_DATA3 R398 10k RC0402N
+V3.3S 15 SPI_MOSI
R399 0 RC0402N
+V3.3A_KBC 29 WIRELESS_ON R400 0 RC0402N I2C_CLK2 R403 10k RC0402N
30,32 3G_LED R401 0 RC0402N
32 NUMLOCK_LED
I2C_DATA2 R407 10k RC0402N
D D
R402 0 RC0402N
CHG_LED 32
P
FB9 180.0FB0603N
ohm +V3.3AVCC R404 0 RC0402N
CAPLOCK_LED 32
R405 D20 R406 0 RC0402N
ADP_IN# 35
0 R408 0 RC0402N
+V3.3AVCC
sod2514n PWR_LED_GRN 32
C230 RC0603N +V3.3A_KBC R409 0 RC0402N
10uF C336 POP = NA +V3.3A_KBC R410 0 RC0402N I2C_DATA3 PWR_LED_RED 32
VBAT
N
CC0603N 0.1u R411 0 RC0402N I2C_CLK3 For GPU Thermal
CC0402N U19 R412 0 RC0402N
PM_CLKRUN# 17
IT8502E/F/G(JX) +V3.3A_KBC
+V5S
114
121
127
107
R413 10k RC0402N
11
26
50
92
74
84
83
82
56
57
33
19
20
99
98
97
96
95
94
93
3
R415 10k RC0402N
15 LPC_AD[3..0]
LPC_AD0 10 110 TBCLK R414 10k RC0402N
VBAT
VSTBY6
VSTBY5
VSTBY4
VSTBY3
VSTBY2
VSTBY1
EGCLK/WUI27/GPE3
EGCS#/WUI26/GPE2
EGAD/WUI25/GPE1
KSO16/SMOSI/GPC3
KSO17/SMISO/GPC5
GINT/CTS0#/GPD5
L80HLAT/BAO/WUI24/GPE0
SBUSY/GPG1/ID7
GPH6/ID6
GPH5/ID5
GPH4/ID4
WUI19/GPH3/ID3
CTX1/WUI18/GPH2/SMDAT3/ID2
VCC
AVCC
L80LLAT/WUI7/GPE7
CRX1/WUI17/SMCLK3/GPH1/ID1
CLKRUN#/WUI16/GPH0/ID0
LAD0 SMCLK0/GPB3 SMB_CLK_BT 36
LPC_AD1 9 LAD1 SMDAT0/GPB4 111 SMB_DATA_BT 36 For Battery
LPC_AD2 8 115 I2C_CLK1 TBDATA R433 10k RC0402N
SM BUS
LAD2 SMCLK1/GPC1 I2C_CLK1 16
LPC_AD3 7 LAD3 SMDAT1/GPC2 116 I2C_DATA1
I2C_DATA1 16 For PCH
R416 100 RC0402N 22 117 I2C_CLK2 LID
7,18,25,29,30 BUF_PLT_RST# LPCRST#/WUI4/GPD2 SMCLK2/WUI22/PECI/GPF6 I2C_CLK2 12
18 CLK_PCI_KBC 13 LPCCLK SMDAT2/PECIRQT#/WUI23/GPF7 118 I2C_DATA2
I2C_DATA2 12 For Thermal Sensor
6 R419
15 LPC_FRAME# LFRAME#
85 TBCLK 10k
PS2CLK0/TMB0/GPF0 TBCLK 33
R420 0 RC0402N LPCPD# 17 86 TBDATA RC0402N
17 PM_SUS_STAT# ccq,evt->dvt,0625POP = NA LPCPD#/WUI6/GPE6 PS2DAT0/TMB1/GPF1 TBDATA 33
P N 87 R421 0 RC0402N POP = NA
+V3.3A_KBC PS2CLK1/DTR0#/GPF2 ALL_SYS_VRPWRGD 30
sod2514n D39 R434 0 RC0402N POP GA20
= NA 126 88 R422 0 RC0402N
PS/2
19 H_A20GATE GA20/GPB5 PS2DAT1/RTS0#/GPF3 IMVP_VR_ON 30,41
R423 0 RC0402N SERIQ 5 89 R424 0 RC0402N VR_PWRGOOD 30,41
15 INT_SERIRQ SERIRQ PS2CLK2/WUI20/GPF4
R425 0 RC0402N 15 90 R426 0 RC0402N
19 SMC_EXTSMI# ECSMI#/GPD4 PS2DAT2/WUI21/GPF5 DELAY_VR_PWRGOOD 30
P N 23 ECSCI#/GPD3 LPC GPIO
R427 D21 sod2514n POP = NA WRST# 14
R428 0 RC0402N WRST#
100k 19 SMC_RUNTIME_SCI# 4 KBRST#/GPB6
RC0402N P N 16 PWUREQ#/GPC7/BBO
D22 sod2514n POP = NA
R429 0 RC0402N 24 R430 0 RC0603N
PWM0/GPA0 FAN_PWMIN 12
R431 0 RC0402N 25 R432 0 RC0402N
19 H_RCIN# PWM1/GPA1 BL_ADJ 22
C337 P N 28 R435 0 RC0402N
PWM2/GPA2 WIFI_BUTTON 33
1uF D23 sod2514n POP = NA 119 29 R436 0 RC0402N POP = NA R443
CC0402N GPC0 PWM3/GPA3 R437 0 RC0402N 10k
123 TMA0/GPB2 PWM4/GPA4 30 BT_ON 31
R440 0 RC0402N POP = NA 31 R438 0 RC0402N RC0402N
18 SMC_WAKE_SCI# PWM5/GPA5 PM_RSMRST# 17
32 R441 0 RC0402N POP = NA POP = NA
PWM6/SSCK/GPA6 SPI_SCK 15
C R442 100 RC0402N POP = NA PWM 34 R444 0 RC0402N C
17 PM_SYSRST# PWM7/GPA7 PM_PWRBTN# 17
R554 0 RC0402N POP = NA 47 R446 0 RC0402N
7 DRAMRST_CNTRL TACH0/GPD6 KBC_FAN_SPEED 12
48 R447 0 RC0402N
TACH1/TMA1/GPD7 BLCTL 22,30
IT8502E/F/G(JX) TMRI0/WUI2/GPC4
TMRI1/WUI3/GPC6
120
124
R448
R469
0
0
RC0402N
RC0402N WIFI_LED
LAN_VDDEN
32
25,30
R450
10k
RC0402N
125 R453 0 RC0402N

PWRSW/GPE4 R454 0 RC0402N POP = NA SMC_ONOFF# 35
RI1#/WUI0/GPD0 18
WAKE UP 21 R455 0 RC0402N
RI2#/WUI1/GPD1 FAN_ON 12
WUI5/GPE5 35
112 R457 0 RC0402N
RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7 ME_FLASH 15
Please do not place any pull-up
resistor on GPG0, GPG2, and GPG6 109 8051TX R459 0 RC0402N
(Reserved hardware strapping). TXD/SOUT0/GPB1 AC_PRESENT 17
UART 108 8051RX R460 0 RC0402N POP = NA
RXD/SIN0/GPB0 PM_BATLOW# 17
66 R461 0 RC0402N
ADC0/GPI0 Vbattery_ec 36
R961 0 RC0402N POP = NA 106 67 R462 0 RC0402N
19 BIOS_REC GPG0 ADC1/GPI1 TEMP_ALERT# 19
FSCK 105 68 R188 0 RC0402N
FSCK ADC2/GPI2 SUS_PWR_ACK 17
104 69 R464 0 RC0402N
DSR0#/GPG6 ADC3/GPI3 PM_SLP_S4# 17,38,42
FMISO 103 FLASH 70 R466 0 RC0402N
FMISO ADC4/WUI28/GPI4 PM_SLP_S3# 17,38,39,42
FMOSI 102 71 R473 100 RC0402N
FMOSI ADC5/WUI29/GPI5 LID 33
FSCE# 101 72 R449 100 RC0402N
FSCE# ADC6/WUI30/GPI6 BAT-DEK# 36
R759 0 RC0402N POP = NA 100 A/D D/A 73 R785 10k RC0402N
15 SPI_SCE# SSCE0#/GPG2 ADC7/WUI31/GPI7
X0 36
X1 KSO0/PD0
37 KSO1/PD1
X2 38
X3
X4
39
40
KSO2/PD2
KSO3/PD3 DAC0/GPJ0 76
77
R471
R472
0
0
RC0402N
RC0402N
P_CHG 36 LPC debug Port
KSO4/PD4 KBMX DAC1/GPJ1 CHG# 36
B
X5
X6
41
42
KSO5/PD5
KSO6/PD6
DAC2/GPJ2
DAC3/GPJ3
78
79
R467
R758
0
0
RC0402N
RC0402N
POP = NA
PM_EXTTS#0_EC 7,12
Camera_ON 31
(KBC Debug Port) B
X7 43 80 R1120 0 RC0402N +V3.3S
KSO7/PD7 DAC4/DCD0#/GPJ4 3G_ON 36
X8 44 81 R760 0 RC0402N POP = NA
X9 KSO8/ACK# DAC5/RIG0#/GPJ5 EC_MUTE# 26
45
E1
X10 KSO9/BUSY C338 0.1u
46 KSO10/PE
X11 51 2 CC0402N 1
E1
KSO11/ERR# CK32KE 1
KSI3/SLIN#
KSI1/AFD#
X12
KSI0/STB#
KSI2/INIT#
52 KSO12/SLCT CLOCK CK32K 128 2 2

X13 53 3
VCORE
X14 KSO13 3
AVSS
54 4
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
7,18,25,29,30 BUF_PLT_RST#
KSI4
KSI5
KSI6
KSI7
X15 KSO14 4
55 KSO15 15 LPC_AD3 5 5
X[0..15] C339 10pF CC0402N 6
33 X[0..15] 15 LPC_AD2 6
15 LPC_AD1 7 7
58
59
60
61
62
63
64
65
27
49
91
113
122
75
12
15 LPC_AD0 8 8
X7 9 CN3
15 LPC_FRAME# 9
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
1
10 F2T20U-XXT3-E
18 CLK_FWHPCI 10
C340 3 2 R474 11 SMD-CN-50P-20N-H
Y[0..7] 0.1u 10M 11
33 Y[0..7] 15 INT_SERIRQ 12 12
CC0402N POP = NA L80HLAT 13 13
4
14 14
+V3.3A_KBC 15 15 ccq,dvt->pvt,1008
16 16
17 17
C341 10pF CC0402N 18 18
19 19
L80LLAT R475 0 RC0402N 20
E2
20
R468 Layout Note: POP = NA
R470 4.7K
32.768kHz clock lines:
E2
4.7K U20 MX25L3205D RC0402N
RC0402N FSCE# 1 8 a. If possible, please avoid using any
FMISO CS# VCC POP = NA
2 SO/SIO1 HOLD# 7 through-hole.
3 6 FSCK
4
WP#/ACC SCLK
5 FMOSI b. Please make the trace length short, and
GND SI/SIO0
the trace width wide enough.
SOIC127P800-8N c. The spacing to the closest neighbor
should be wide enough.
A A

5th floor,Block K,
Title <Title>
Size Sheet Rev
KBC_IT8502E
C Name A
5 4 3 2 1
10 9 8 7 6 5 4 3 2 1
J Power Button Detect & Latch J

Power Sequence
+V_DC_IN +V_DC 05
Q63 AO4419
1 8
2 7
3 6
C544 C551 C552 5 C550 C556
0.1uF 10uF 10uF SOIC127P600-8N 10uF 0.1uF
4
I CC0603N CC1210N CC1210N
POP = NA
C543
0.1uF
CC0603N
R899
390K
RC0603N
CC1210N CC0603N
I
R902
PWRONLATCHG 100
RC1206N
R901
100k
RC0402N
Power Sequence
3
H H
Q64
S D
2N7002LT1
PS_LATCH# 1 SOT95P240-3N
7AC 4BAT G
2
R903
1M
RC0402N
D32
G 36 DC_GATE N P sod2514n G
D33
POWSW# N P sod2514n R898 0 RC0402N
33 POWSW#
3
D34 Q65
S D
N P sod2514n SMC_ONOFF# 34
2N7002LT1
1 SOT95P240-3N
34 SMC_SHUTDOWN# G
2
D35
ACOK# N P sod2514n R900
36 ACOK# ADP_IN# 34
100k
RC0402N
F F
E Adaptor In E
FB25 120R +V_ADP_IN
FB0805N 1AC
MAX 3.5A
AC_IN AC_IN FB27 120R
CN14 FB0805N
4
1 AC_IN
AC_IN
N
2 AC_DETECT C540
AC_DETECT
AC_DETECT AC_DETECT D29 0.1uF C537 C538 C539 R489
3 CC0603N 0.1uF 0.1uF 4.7uF 2k
D sod5227n CC0603N CC0603N CC1210N RC1206N

D
P
5
DCIN
thr-dcin-5n
C C
B B

5th floor,Block K,
A Title <Title>
A
Size Sheet Rev
DCIN & Small Boards CONN
C Name A
10 9 8 7 6 5 4 3 2 1
J J
+V_DC_IN +V_DC_IN
C511 C510
4.7uF 0.1uF
CC1210N CC0603N
C504
0.033uF +VBAT
CC0603N
+V_ADP_IN R660
I 100k
RC0402N R665
100k
I
Layout NOTE: R679 RC0402N
3
2
1
100k
RC0402N
The AGND_CHG connect to POP = NA 4 Q44
AO4419
Vbattery_ec 34
GND through E1 pin; C515

0.1uF
SOIC127P600-8N R666
10k
by via only!
5
6
7
8
CC0603N R671 RC0402N
POP = NA 51K
RC0402N
+V_ADP_IN PVCC
3
H H
N
AC current limit: 3.9A Q50
S D
Q43 Q45 2N7002LT1 D25
R678 0.011_1%RC2512N ACOK# R680 1K
8 1 1 8 1 G
7 2 2 7 sod5227n
2
6 3 3 6
P
C522 R482 5 AO4419 5
0.1uF 2.2Ω SOIC127P600-8N AO4419 C585 C586
4
CC0603N POP = NA SOIC127P600-8N 10uF 10uF

CC1210N CC1210N
RC0805N RC0402N 150k ±1% R656 R667 150k ±1%
RC0402N C523 0.1uF CC0603N
C126 PHASE
2.2uF CC0402N 0.01uF C518 C516 0.01uF CC0402N C505
CC0805N C520 0.1uF
POP = NA +VBAT +VBAT CC0603N
1
2
ccq,evt->dvt,0625 0.1uF
G R670
100k
R684
100k PVCC
CC0603N D 5
6 L9
Charge current:1.5A
F2
CN13
G
RC0402N RC0402N HDRV 8 7 1 2 R686 0.011_1%RC2512N 1 2 1 1
N
22uH f6125n 2
DC_GATE REGN Q42 C512 C513 2
35 DC_GATE 34 SMB_CLK_BT 3 3
D24 R663 LDRV 3 APM4906 C519 10uF 0.1uF 4 E1
S 34 SMB_DATA_BT 4 E1
R658 sod2514n 0 SOIC127P600-8N 10uF CC1210N CC0603N 5 E2
THRM_BAT 5 E2
R659 C517 2.2 RC0603N CC1210N
REGN
P
4
100k 0.01uF RC0603N REGN 6
34 BAT-DEK# 6
RC0402N POP = NA 7 7
3
C508 VREF_CHG
Q67 CC0402N 1uF
E1
24
23
22
21
20
19
U45
S D
2N7002LT1 C521 CC0603N C14401-107A1-B

1 0.1uF R681 C509 AGND_CHG thr-bat-200p-7n
HIDRV
LODRV
BTST
E1
PH
REGN
PGND
G CC0603N 10k C524 0.1uF CC0603N
F F
2
RC0402N 0.1uF
3
CC0603N
Q66 1 18 DPMDET# Battery Connector
S D
2N7002LT1 R661 0 RC0402N PVCC DPMDET# CELLS

34 CHG# 2 CHGEN# CELLS 17
ACOK# R662 1k 1 R673 3 16
G 51K ACN BQ24705 SRP
4 ACP SRN 15
2
PVCC RC0402N ACDET 5 14

C506 ACDET BAT SRSET R654 100k±1% RC0603N VREF_CHG C583
6 ACSET SRSET 13
ACGOOD#
0.1uF 0.1uF
ISYNSET
IADAPT
CC0603N CC0603N
AGND
VREF
VADJ
VREF_CHG R664 R674 Close to IC
R685 AGND_CHG 20K±1% 1.2K
750K±1% RC0603N RC0603N AGND_CHG
7
8
9
10
11
12
RC0603N Please near to the IC
E E
3
R676 Q73
15K±1% AGND_CHG C584 100pF CC0402N 2N7002LT1
S D
RC0603N
ACOK# 1 R683 1K RC0402N P_CHG 34
ACDET ACSET VREF_CHG VADJ G
2
AGND_CHG Ichg=((VCH/VREF)*(0.1/Rsr)=2.02A
Set Vacdet must be: 2.424V<Vacdet<3.007V R675
C514 Set charge current about 2.02A
1uF R697
See the spec Page 4 and Page 7 11.3k±1% Place near to the IC CC0603N 75K±1% AGND_CHG Set prechg current about 111.349MA
RC0603N RC0402N
Isyn set 303MA
R657 AGND_CHG
120k±1% AGND_CHG
RC0603N AGND_CHG
D Iac=(VAC/VREF)*(0.1/Rac)=3.9A VREF_CHG
D
AGND_CHG R677
0
RC0402N
VREF_CHG REGN VREF_CHG POP = NA
CELLS
For 19V-4.74A Adapter Set the 2 Cells
R669
R668 R655 10k
100k 0 RC0402N R682
RC0402N RC0402N 0
POP = NA RC0402N
C VADJ ACOK# ACOK# 35 POP = NA

C
R672 C507
68K 0.1uF
RC0402N CC0603N
POP = NA
Set the default 4.2V per cell
B B

5th floor,Block K,
A Title <Title>
A
Size Sheet Rev
Power_Charger&Battery Conn
C Name A
5 4 3 2 1
+V_DC
R495
D D
0 +V_DC
RC0402N
POP = NA
VREF
C364 C365 C366
10uF 10uF 0.1uF C368 TONSEL R496 0 RC0402N VREG3
CC1210N CC1210N CC0603N 0.22uF POP = NA R497 0 RC0402N VREG5 C367 C369 C370
CC0603N POP = NA R498 0 RC0402N VREF 0.1uF 10uF 10uF
CC0603N CC1210N CC1210N
R499 R500
±1% 20K±1% 20K±1%
±1%
RC0603N RC0603N
R501 30k ±1% VFB1 VFB2 R502 13k_1% RC0603N

RC0603N
R503 270K RC0603N R504 270K RC0603N
Vtrip=Rtrip*Itrip/9-24
1
2
3
4
5
6
+V3.3A_KBC
VREF
ENTRIP1
VFB1
TONSEL
VFB2
ENTRIP2
100k R377 0 RC0805N
+V5A VREG5 R505 E1 +V3.3A
+5VA/11A E1
1
2
RC0402N C371 10uF CC0603N +3.3VA/11A
2
1
24 7 D 5
OCP=13.45A 5 D POP = NA RC0402N 0 R506 23
V01 VO2
8 VREG3 6 L3
L4 6 0.1u C373 22
PGOOD VREG3
9 C372 0.1u CC0402N 8 7 1 2
OCP=12.28A
DRVH1A R507 2.2 CC0402N VBST1 TPS51125RGE VBST2 R508 2.2 DRVH2A 2.2uH
1 2 7 8 21 DRVH1 DRVH2 10
2.2uH RC0603N 20 11 RC0603N Q13
Q12 LL1 LL2 R509 0 DRVL2A APM4910K
19 DRVL1 DRVL2 12 3
SKIPSEL
1
APM4910K 3 DRVL1A R510 0 RC0603N RC0603N S SOIC127P600-8N CP12 CP13 CP35
VREG5
1
CP38 CP10 CP11 SOIC127P600-8N S C376 C377
VCLK
+ + +
GND
4
EN0
VIN
C C374 C375 + + + 2.2uF 0.1u C
4
0.1u 150uF 150uF 220UF CC0603N CC0402N
2
CC0402N 2.2uF 220UF 150uF 150uF U24 CCP7343N CCP7343N CAE630W570HN
2
18
17
16
15
14
13
CC0603N CAE630W570HN CCP7343N CCP7343N POP = NA POP = NA
POP = NA POP = NA
R511 620K RC0603N POP = NA
VCLK ccq,evt->dvt,0625 Dual Lay
ccq,evt->dvt,0625 Dual Lay VREG5
C378 R513 R512 0 RC0402N VREG5

10uF +V_DC 0 R514 0 RC0402N VREF
CC0805N RC0402N POP = NA
POP = NA
C379
0.1uF
CC0603N
C563 C558
0.1u 0.1u
CC0402N CC0402N
+V15A
3
VREG5 1 2 1 2
C564 D17 C565 D18 C570

0.1u SOT95P280-3N 0.1u SOT95P280-3N 1uF
CC0402N CC0402N CC0805N
+V1.5A +V3.3A
B B
IccMAX=10MA
U46 APL5315
4 VOUT VIN 3
GND
C526 5 1 R739 0 RC0603N C527
1uF SET/BP SHDN 1uF
CC0603N R754 CC0603N
2
27K ±1%
RC0402N
R742
30k ±1%
RC0603N
For HDMI
A A

5th floor,Block K,
Title <Title>
Size Sheet Rev
Power_System
C Name A
5 4 3 2 1
5 4 3 2 1
+V_DC
C395 C396 C397

0.1uF 10uF 10uF
D D
CC0603N CC1210N CC1210N
POP = NA POP = NA
5
6
7
8
+V1.5M
4 Q18
AO4468 +V1.5M
C399 SOIC127P600-8N +1.5V/12A
+V0.75M 0.1u C398 L6
3
2
1
Iout MAX=2A CC0402N 0.1uF 1 2
OCP=14.82A
CC0603N 0.68uH
+V0.75M R534 0 RC0603N
5
6
7
8
1
R535 D27 CP17
0 R536 0 RC0603N 4 Q19 10MQ040N + 220uF C400 C401
RC0603N AO4430 sod5225n CCP7343N 10uF 0.1u
SOIC127P600-8N POP = NA CC1206N CC0402N
2
POP = NA
MODE DISCHARGE MODE
P
3
2
1
C402 C403
E1
24
23
22
21
20
19
U27
V5IN No discharge 10uF
CC0805N
10uF
CC0805N
VTT
VBST
E1
LL
DRVL
VLDOIN
DRVH
VDDQ Tracking discharge
S4/GND Non-tracking discharge 1 18
VTTGND PGND +V5A
2 VTTSNS CS_GND 17
3 GND CS 16 R537 27K RC0402N
TPS51116RGE
4 MODE V5IN 15
+V1.5M 5 14 R515 10 RC0603N
R538 VTTREF V5FILT
6 COMP PGOOD 13
VDDQSNS
0
VDDQSET
R540 0 RC0402N RC0402N C404 C405
POP = NA 1uF 1uF
NC1
NC2
R542 CC0603N CC0603N
S3
S5
100k
13 M_VREF R541 0 RC0402N RC0402N
7
8
9
10
11
12
+V1.5M
C C406
0.033uF
+V5A
S3 & S5 Control C
CC0603N +V1.5M DDR3_PWRGD R543 0 RC0402N

DDR3VR_PWRGD 30 STATE S3 S5 VDDQ VTTREF VTT
R544 C407
S0 HI HI ON ON ON
75K 470pF R545
Vtrip(mV)=Rtrip(kohm) *10uA
RC0603N CC0603N 0
S3 LO HI ON ON OFF(HI-Z)
POP = NA RC0402N Iocp=Vtrip/Rds(on)+Iripple/2
POP = NA
S4/S5 LO LO OFF(Discharge) OFF(Discharge) OFF(Discharge)
R548 0 RC0402N PM_SLP_S4# 17,34,42
R546
75K
RC0603N
R1032 100k RC0402N DDR_STBY VDDQSET VDDQ (V) VTTREF & VTT NOTE
7,30 V1.1S1.5S_PWRGD
17,34,39,42 PM_SLP_S3# R547 0 RC0402N POP = NA GND 2.5 VDDQSNS/2 DDR

R1068 0 RC0402N V5IN 1.8 VDDQSNS/2 DDR2
FB Resistors Adjustable VDDQSNS/2 1.5V< VDDQ<3V
3
Q106
FB Resistors=(100*VDDQ-75)kohm
S D
BSS138
30,42 PS_S3CNTRL 1 G SOT95P280-3N
2
B B
+V5A
ccq,evt->dvt,0625 C410 C525

10uF 0.1uF
CC0805N CC0603N Dual Lay
+V1.8S
+V1.8S/2A
2
1
U28 Imax=1.5A
L7 2.2uH
VIN
NC
17,34,39,42 PM_SLP_S3# R552 0 RC0402N 6 7 1 2

EN LX1 LC6666N
1
8 CP37
PGND
5 COMP
C83 + 220uF Vout=0.8*(1+R1/R2)
4 22uF CCP7343N
FB
AGND
CC0805N POP = NA
2
LX0
R551 ccq,evt->dvt,0625
15K±1%
±1% APW7145KA
3
E1
RC0603N
C848
820pF
CC0402N
R550 12k ±1% RC0603N R549 15K±1%
±1% RC0603N
C849 56pF CC0603N POP = NA
A A
Place close to the IC

5th floor,Block K,
Title <Title>
Size Sheet Rev
Power_DDR3 & 1.8S
C Name A
ENGINEER: Ivan Date: Thursday, October 21, 2010 Sheet 38 of 44
5 4 3 2 1
5 4 3 2 1
+V_DC +V_DC_CPU
+V_DC_CPU
D D
R800 0 RC0402N
30 PM_1.5S1.1SMPWRGD
R516 0 RC0402N POP = NA C380 C381 C382
17,34,38,42 PM_SLP_S3# D30
0.1u 10uF 10uF
CC0402N
N P POP = NA CC1210N CC1210N
Set Fsw=300KHZ
R518 BAT54WS-7-F
2.2 SOD1713N
5
6
7
8
+V5S R519 RC0603N Processor IO voltage is 1.05 V for Arrandale
200K±1%
RC0603N R522 0 RC0603N 4 Q14 and 1.1 V for Clarksfield.
AON6428L +V1.1S_VTT
14
1
U25 SOIC127P605X520-8N
R520 R521 +V1.05S/20A
EN_PSV
VBST
3
2
1
100k 300 ±1%
RC0402N RC0603N 2 13 1.05_UGATE L5 0.47uH,2.1m ohm
3
TON DRVH
12 1.05_LL 1 2
OCP=22.97A
VOUT LL R523 14K ±1% RC0603N
4 V5FILT TRIP 11
10 VTT_SENSE R559 0 RC0402N POP = NA 5 TPS51117RGY 10 +V5S
R524 0 RC0402N VFB V5DRV
30 V1.1S_VTT_PWRGD 6 PGOOD DRVL 9
5
6
7
8
C384 1uF CC0402N
PGND
GND
1
C388 1.05_LGATE R525 0 RC0603N 4 Q15
E1
1uF AON6718L D26 + CP14 + CP15 C385 C386 C387
CC0402N SOIC127P605X520-8N10MQ040N 330uF 330uF 10uF 10uF 0.1uF
E1
Rtrip=Vtrip/10 sod5225n CCP7343N CCP7343N CC1206N CC1206N CC0603N
3
2
1
2
Iocp=Vtrip/Rdson+Iripple/2
P
IF USE APW7141 The value must be 2.2ohm POP = NA
R526
12k ±1%
RC0603N
ccq,dvt->pvt,1008
Vout=0.75*(1+R1/R2)
C C
R527
30k ±1%
RC0603N
+V_DC
R1072 0 RC0402N C546 C730 C832

17,34,38,42 PM_SLP_S3# D31
0.1u 10uF 10uF
CC0402N
N P POP = NA CC1210N CC1210N
R1085 BAT54WS-7-F Rtrip=Vtrip/10

2.2 SOD1713N Iocp=Vtrip/Rdson+Iripple/2
+V5S R517 RC0603N
B B
200K±1%
RC0603N
+V1.1S
14
1
1
2
R1083 R1075
U31
D
For PCH And dGPU
5
EN_PSV
VBST
100k 300 ±1% 6 L21

RC0402N RC0603N 2 13 R1076 0 RC0603N 8 7 1 2 +V1.05S/11A
TON DRVH
3 12 1.5uH
VOUT LL R1073 20K±1% RC0603N Q22
4 V5FILT TRIP 11 OCP=13.6A
1
5 TPS51117RGY 10 +V5S 3 APM4910K CP16

R1074 0 RC0402N VFB V5DRV S SOIC127P600-8N
6 9 + 220uF C834 C836 C535
30 V1.1S_PWRGD PGOOD DRVL C536 1uF CC0402N CCP7343N 10uF 10uF 0.1uF
4
PGND
CC1206N CC1206N CC0603N

GND
C835
E1
1uF R1078 0 RC0603N

CC0402N
7
E1
IF USE APW7141 The value must be 2.2ohm
R1080
12k ±1%
RC0603N
Vout=0.75*(1+R1/R2)
R1081
30k ±1%
RC0603N
A A

5th floor,Block K,
Title <Title>
Size Sheet Rev
Power_1.1S_VTT
C Name A
5 4 3 2 1
5 4 3 2 1
D D
+VCC_GFXCORE
CSN_GFX
R1006 CSP_GFX
100 ±1% +V_DC_CPU
RC0402N
CC0402N ccq,dvt->pvt,1008
VSNS_GFX C545 6.8nF

GFX_VID[0..6] 11
GNDSNS_GFX R1011 0 RC0402N GFX_VID6
R1009 0 RC0402N GFX_VID5 dual lay
R1010 0 RC0402N GFX_VID4 C724 C725 C723 6.8nF CC0603N
R1005 R1015 0 RC0402N GFX_VID3 10uF 10uF POP = NA
100 ±1% R1014 0 RC0402N GFX_VID2 CC1210N CC1210N ccq,evt->dvt,0625
RC0402N 11 GFXVR_DPRSLPVR R1013 0 RC0402N GFX_VID1 R1022 150k ±1% RC0402N
R1012 0 RC0402N GFX_VID0
11 GFXVR_IMON +VCC_GFXCORE/12A
R1021 56.2K±1% RC0402N R1020 10K_NTC RC0402N
Close to the IC GNDSNS_GFX R1088 24k±1% RC0402N OCP=15A
5
6
7
8
C203 0.01uF CC0402N ccq,evt->dvt,0625
4 Q60 R1023 +VCC_GFXCORE
Lay out Note: R1018 0 RC0603N DRVH_GFX AON6428L 68K ±1%
R1016 56 RC0402N POP = NA SOIC127P605X520-8N RC0402N
E1
10
11
12
13
14
15
16
Place on hotest air. +V1.1S_VTT D36
9
0.45uH LC100W100N
L11
3
2
1
ccq,dvt->pvt,1124 N P 1 2
+V5S
E1
DPRSLPVR
VID6
VID5
VID4
VID3
VID2
VID1
VID0
POP = NA
BAT54WS-7-F dual lay L8 0.47uH,2.1m ohm
N
5
6
7
8
1
GND_51611 R1008 2K±1% RC0402N R1007 20K 8 17 SOD1713N 1 2
IMON DRVH R1017 0 RC0603N C721 1uF CC0603N D28
7 18 + CP31 + CP33 C722 C719
VR_TT# VBST LL_GFX Q61 10MQ040N 330uF 330uF 1uF 0.1uF
6 THERM LL 19 4
VSNS_GFX 5 20 R1019 0 RC0603N DRVL_GFX AON6718L sod5225n CCP7343N CCP7343N CC0805N CC0603N
11 VCC_AXG_SENSE VSNS DRVL
2
GNDSNS_GFX 4 TPS51611 21 +V5S SOIC127P605X520-8N POP = NA
11 VSS_AXG_SENSE GNDSNS V5IN
P
C CSN_GFX R1030 470 RC0402N CSN_GFX_R 3 22 R1024 10k RC0402N POP = NA C
CSN MODE
3
2
1
CSP_GFX R1033 470 RC0402N CSP_GFX_R 2 23 R1025 10k RC0402N POP = NA
CSP PGOOD C455
1 GND1 CLKEN# 24
TRIPSEL
2.2uF
OSRSEL
TONSEL
DROOP
VR_ON
V5FILT
ISLEW
C457 C456 CC0603N
VREF
33pF 33pF
CC0402N CC0402N Close to the IC
U52
32
31
30
29
28
27
26
25
GFXCore_PGOOD R3 10k RC0402N +V3.3S
ccq,evt->dvt,0625
GND_51611 C847 0.22uF R952 1.9K ±1% RC0603N POP = NA
CC0603N
VREF_GFX
R65 0 RC0402N
GFXVR_EN 11
C458 33pF CC0402N
ccq,evt->dvt,0625 R1042 0 RC0402N +V5S
R1045 3.83k±1% RC0402N POP = NA
Rdroop=(Rcseff*Acs)/(GM*Rimvp) +V5S R969 4.7 R1043 0 RC0402N +V3.3S
RC0603N POP = NA
GND_51611 C729 1uF CC0603N R1041 0 RC0402N
R1047 260K±1% RC0603N POP = NA
VREF_GFX R1035 91K±1% RC0402N R1044 0 RC0402N POP = NA VREF_GFX
R1029 0 RC0402N R1040 0 RC0402N

POP = NA
+V3.3S R1028 0 RC0402N R1038 0 RC0402N +V5S
POP = NA POP = NA
R1027 0 RC0402N R1039 0 RC0402N +V3.3S
POP = NA
R1037 0 RC0402N
POP = NA
OSRSEL VOLTAGE Result

B B
GND Minimum voltage(Maximum reduction)

VREF(1.7V) Medium voltage TONSEL VOLTAGE FREQUENCY(KHZ)
3.3V Maximum voltage
5.0V OSR Off GND 250KHZ
VREF(1.7V) 300KHZ v
3.3V 350KHZ
5.0V 500KHZ
A A

5th floor,Block K,
Title <Title>
Size Sheet Rev
Power_GFXCore
C Name A
5 4 3 2 1
5 4 3 2 1
D +VCC_CORE D
R634
100 CSN1_IN
RC0402N
CSP1_IN
CCQ20100406 +V_DC_CPU
VSNS CC0402N
GNDSNS
H_VID[0..6] 10
H_VID6_R R937 0 RC0402N H_VID6
H_VID5_R R935 0 RC0402N H_VID5 C547 10nF
R633 H_VID4_R R936 0 RC0402N H_VID4
100 H_VID3_R R940 0 RC0402N H_VID3
RC0402N H_VID2_R R939 0 RC0402N H_VID2 C733 C734 C728 10nF CC0603N
ccq,evt->dvt,0625 H_VID1_R R938 0 RC0402N H_VID1 10uF 10uF POP = NA
H_VID0_R R576 0 RC0402N H_VID0 CC1210N CC1210N
R941 0 RC0402N R1079 150k ±1% RC0402N
PM_DPRSLPVR_R
10 PM_DPRSLPVR
Close to the IC 10 IMVP_IMON +VCC_CORE/27A
R1099 75K±1% RC0402N R1070 10K_NTC RC0402N
GNDSNS R1093 24k±1% RC0402N OCP=32A
ccq,evt->dvt,0625
5
6
7
8
C282 0.01uF CC0402N
R1082 +VCC_CORE
Lay out Note: R1100 68 RC0402N
R1087 0 RC0603N DRVH 4 Q83 68K ±1%
AON6428L RC0402N
E1
10
11
12
13
14
15
16
Place on hotest air. +V1.1S_VTT D37
9
SOIC127P605X520-8N L12 0.45uH LC100W100N
7 H_PROCHOT# R56 0 RC0402N N P +V5S 1 2
E1
DPRSLPVR
VID6
VID5
VID4
VID3
VID2
VID1
VID0
3
2
1
ccq,dvt->pvt,1124 BAT54WS-7-F
N
5
6
7
8
5
6
7
8
1
GND_51611_CPU R1067 2K±1% RC0402N R1066 20K 8 17 SOD1713N
IMON DRVH R1086 0 RC0603N C732 1uF CC0603N D38
7 18 + CP34 + CP36 + CP32 + CP41 C727 C720
VR_TT# VBST LL Q84 Q85 10MQ040N 330uF 330uF 330uF 330uF 1uF 0.1uF
6 THERM LL 19 4 4
VSNS 5 20 R1094 0 RC0603N DRVL AON6718L AON6718L sod5225n CCP7343N CCP7343N CCP7343N CCP7343N CC0805N CC0603N
10 VCCSENSE VSNS DRVL
2
GNDSNS 4 TPS51611 21 +V5S SOIC127P605X520-8N SOIC127P605X520-8N
10 VSSSENSE GNDSNS V5IN
P
CSN1_IN R1048 470 RC0402N CSN 3 22 R1069 10k RC0402N POP = NA POP = NA ccq,evt->dvt,0625
CSN MODE
3
2
1
3
2
1
C C
CSP1_IN R1065 470 RC0402N CSP 2 23 R1098 10k RC0402N
CSP PGOOD C548
1 GND1 CLKEN# 24
TRIPSEL
2.2uF +V3.3S
OSRSEL
TONSEL
CPU MODE ccq,dvt->pvt,1008
DROOP
VR_ON
V5FILT
ISLEW
C542 C541 CC0603N
VREF
33pF 33pF
CC0402N CC0402N Close to the IC
U53 RC0402N 0 R965 R962
VR_PWRGOOD 30,34
32
31
30
29
28
27
26
25
10k
CPUCore_PGOOD R13 10k RC0402N +V3.3S RC0402N
ccq,evt->dvt,0625
CLK_PWRGD 6
GND_51611_CPU C850 0.22uF R967 1.9K ±1% RC0603N
3
CC0603N
VREF_CPU +V1.1S_VTT
S D
R79 0 RC0402N 2N7002LT1
IMVP_VR_ON 30,34
C549 33pF CC0402N CLKEN# 1 Q80
ccq,evt->dvt,0625 R1054 0 RC0402N G
+V5S
2
R1057 3.83k±1% RC0402N POP = NA C697
Rdroop=(Rcseff*Acs)/(GM*Rimvp)
+V5S R968 4.7 R1055 0 RC0402N +V3.3S 0.01uF
RC0603N POP = NA CC0402N R577 R579 R581 R583 R585 R587 R589 R592
C731 1uF CC0603N R1053 0 RC0402N R344 1k 1k 1k 1k 1k 1k 1k 1k 1k
GND_51611_CPU
RC0402N RC0402N RC0402N RC0402N RC0402N RC0402N RC0402N RC0402N RC0402N
R1058 260K±1% RC0603N POP = NA POP = NA POP = NA POP = NA POP = NA
H_VID0_R
VREF_CPU R1097 91K±1% RC0402N R1056 0 RC0402N POP = NA VREF_CPU H_VID1_R
H_VID2_R
R1046 0 RC0402N R1052 0 RC0402N H_VID3_R
POP = NA H_VID4_R ccq,dvt->pvt,1008
+V3.3S R1036 0 RC0402N R1050 0 RC0402N +V5S H_VID5_R
POP = NA POP = NA H_VID6_R
R1034 0 RC0402N R1051 0 RC0402N +V3.3S PM_DPRSLPVR_R
POP = NA PSI#
R1049 0 RC0402N
POP = NA
R362 R578 R580 R582 R584 R586 R588 R590 R593

1k 1k 1k 1k 1k 1k 1k 1k 1k
OSRSEL VOLTAGE Result RC0402N RC0402N RC0402N RC0402N RC0402N RC0402N RC0402N RC0402N RC0402N
POP = NA POP = NA POP = NA POP = NA POP = NA POP = NA
B GND
VREF(1.7V)
Minimum voltage(Maximum reduction)
Medium voltage TONSEL VOLTAGE FREQUENCY(KHZ)
B
3.3V Maximum voltage
5.0V OSR Off GND 250KHZ
VREF(1.7V) 300KHZ v
3.3V 350KHZ PSI#
10 PSI#
5.0V 500KHZ
A A

5th floor,Block K,
Title <Title>
Size Sheet Rev
Power_Vcore
C Name A
5 4 3 2 1
S3 /S4 Power control

+V3.3A +V3.3S +V1.5M +V1.5S
+V15A Q68 Q98

8 1 8 1
7 2 7 2
6 3 6 3
R561 100k RC0402N SLPS3#_CONTROL C418 5 C416 C557 C762 5 C735
10uF AO4468 0.01uF 10uF 10uF AO4468 10uF
4
CC1206N CC0402N CC1206N CC1206N CC1206N
D D
R906
3
100k
RC0402N
S D
30,38 PS_S3CNTRL 1 Q74
G 2N7002LT1 SLPS3#_CONTROL R564 1k RC0402N SLPS3#_CONTROL R869 1K RC0402N SLPS3#_CONTROL_1.5S 11
2
3
C383 C533
0.01uF 0.01uF
S D
R907 CC0402N CC0402N
R562 1K RC0402N 1 Q72 1M
17,34,38,39 PM_SLP_S3# G 2N7002LT1 RC0402N
2
+V5A +V5S
Q69
8 1
7 2
6 3 C532 C571
C577 5 0.01uF 10uF
10uF AO4468 CC0402N CC1206N
4
CC1206N
C C
SLPS3#_CONTROL R905 1k RC0402N
C415
0.01uF
CC0402N
Power Discharge Circuit

+V5A
+V5S +V3.3S +V1.5S +V0.75M +V1.1S +V1.1S_VTT +V1.8S +VCC_GFXCORE +VCC_CORE +V1.5M_CPU
B B
SLP_S3# DISCHARGE CIRCUIT
DESIGNED FOR ~100ms
DISCHARGE ON ALL S3 R565
100k R566 R567 R568 R569 R570 R4 R7 R10 R12 R571
RAILS. RC0402N 97.6 ±1% 97.6 ±1% 220 22 470 470 470 47 47 220
RC0603N RC0603N RC0603N RC0402N RC0402N RC0402N RC0402N RC0603N RC0603N RC0603N
S3_DISCHARGE
CCQ20100406
3
3
Q25 R572 Q26 Q27 Q28 Q29 Q30 Q34 Q35 Q36 Q31 Q76
S D
S D
S D
S D
S D
S D
S D
S D
S D
S D
S D
2N7002LT1 1M 2N7002LT1 2N7002LT1 2N7002LT1 2N7002LT1 2N7002LT1 2N7002LT1 2N7002LT1 2N7002LT1 2N7002LT1 2N7002LT1
1 RC0402N 1 1 1 1 1 1 1 1 1 1
17,34,38,39 PM_SLP_S3# G G G G G G G G G G G
2
2
+V5A
SLP_S4# DISCHARGE CIRCUIT +V1.5M
DESIGNED FOR ~100ms

DISCHARGE ON ALL S3 R573 R120
RAILS. 100k 68
RC0402N RC0402N
S4_DISCHARGE
3
A A
Q32 Q33
S D
S D
2N7002LT1 R575 2N7002LT1

1 1M 1
17,34,38 PM_SLP_S4# G G
RC0402N
2

5th floor,Block K,
Title <Title>
Size Sheet Rev
Power_S3_S4
C Name A
5 4 3 2 1
10 9 8 7 6 5 4 3 2 1
J J
I I
H H
G G
F F
E E
D D
C C
B B

5th floor,Block K,
A Title <Title>
A
Size Sheet Rev
DCIN & USB Board
C Name A
10 9 8 7 6 5 4 3 2 1
J J
I I
H H
G G
F F
E E
D D
C C
B B

5th floor,Block K,
A Title <Title>
A
Size Sheet Rev
Platform Change List
C Name A
10 9 8 7 6 5 4 3 2 1
J J
H_+V3.3
I I
To Main Board H_C2 H_C3
H_STXP0
H_STXN0
22
21
20
19
22
21
20
10uF 0.1u H_SRXN0 H_C1 0.01uF CC0402N 19
18 18
CC1206N CC0402N H_SRXP0 H_C4 0.01uF CC0402N 17 17
H_CN2 16 16
15 15
H_USB_PN1 1 14
H_USB_PP1 1 H_GND 14
2 2 E1 E1 13 13 E2 E2
H_USB_OC1# 3 E2 12 E1
3 E2 12 E1
4 4 11 11
H_STXP0 5 H_+V5 10
H_STXN0 5 H_R1 1_1% RC0603N 10
6 6 9 9
H H
7 HMH1 8
H_SRXN0 7 H_GND 8
8 8 7 7
H_+V3.3 H_SRXP0 9 6
H_GND 9 6
10 10 HMH2 5 5
H_+V3.3 11 H_C5 H_C6 H_C7 H_C8 4
11 4
12 12 3 3
13 10uF 10uF 0.1u 0.1u 2
H_+V5 13 CC1206N CC1206N CC0402N CC0402N 2
14 14 1 1
15 POP = NA POP = NA
15 H_GND
16 16 H_CN1
Ivan Modify
G H_GND
H_GND
G
H_CN4
H_USB_PN1 A1 B1 H_USB_PN1
H_USB_PP1 A1 B1 H_USB_PP1
A2 A2 B2 B2
H_USB_OC1# A3 B3 H_USB_OC1#
A3 B3
A4 A4 B4 B4
H_STXP0 A5 B5 H_STXP0
H_STXN0 A5 B5 H_STXN0
A6 A6 B6 B6
A7 B7
F H_+V3.3
H_SRXN0
H_SRXP0
A8
A9
A7
A8
A9
B7
B8
B9
B8
B9
H_SRXN0
H_SRXP0 H_+V3.3
F
H_GND A10 B10 H_GND
H_+V3.3 A10 B10 H_+V3.3
A11 A11 B11 B11
A12 A12 B12 B12
A13 A13 B13 B13
H_+V5 A14 B14 H_+V5
A14 B14
A15 A15 B15 B15
A16 A16 B16 B16
F4K16U-A1T3-J
091215
Dual Lay
POP = NA FPC CONN
E E
USB Port1 CLOSE +V5_USB0
USB_SINGLE_VERT
1
H_+V5 H_R4 0 RC0603N H_C11
H_F1 H_CN3 + H_CP1
1 2 +V5_USB0 100uF 1000pF
330mA CCP7343N
E1
E2
D D
2
f1206n H_C9 FIL_175P200X120-4L USB_D0P
0.1u H_R2 H_USB_PN1 1 UNB B22 1
E1
E2
CC0402N 562 1
2 2
RC0603N H_FIL1 POP = NA 3
GND 3
H_USB_PP1 4 B33 USB_D0N 4 H_GND
E3
H_GND H_USB_OC1# 4
E3
1
1
H_D1 H_D2
H_R3 H_C10 H_R5 0 RC0603N USB0005DP USB0005DP
1k 0.1u CC0402N CC0402N
RC0603N CC0402N POP = NA POP = NA
2
H_GND
C H_GND
H_GND C
CLOSE USB_SINGLE_VERT
B B

5th floor,Block K,
A Title <Title>
A
Size Sheet Rev
HDD Board
C Name A
ENGINEER: Wain Date: Wednesday, October 20, 2010 Sheet 45 of 42
10 9 8 7 6 5 4 3 2 1
J J
USB Port Board

I I
+V5_USB1
USB Port2
1
+V5_USB
+ U_CP1 U_C5
U_F1 100uF
1 2 f1206n +V5_USB1 CCP7343N 1000pF
2
H H
U_C1 U_R1 U_R5 0 RC0603N
0.1u 562 330mA U_CN2
CC0402N RC0603N FIL_175P200X120-4L GND_USB
U_USB_PN0 1 UNB B22 1 E1
U_USB_OC0# 1 E1
2 2 E2 E2
U_FIL1 POP = NA 3 E4
U_USB_PP0 GND B33 3 E4
4 4 4 E3 E3
GND_USB U_R2 U_C3
1k 0.1u
RC0603N CC0402N
U_R6 0 RC0603N
1
U_D3 U_D4
USB0005DP USB0005DP
CC0402N CC0402N 090814
GND_USB POP = NA POP = NA
2
GND_USB
G G
GND_USB
USB Port3 +V5_USB2
1
U_C6
+ U_CP2
+V5_USB U_R7 0 RC0603N 100uF 1000pF
CCP7343N
F F
2
U_F2 330mA U_CN3
1 2 f1206n +V5_USB2 FIL_175P200X120-4L
U_USB_PN5 1 UNB B22 1 E1
U_C2 1 E1
2 2 E2 E2
0.1u U_R3 U_FIL2 POP = NA 3 E4
CC0402N 562 U_USB_PP5 GND B33 3 E4 GND_USB
4 4 4 E3 E3
RC0603N
GND_USB U_USB_OC5# U_R8 0 RC0603N
1
U_D1 U_D2
U_R4 U_C4 USB0005DP USB0005DP
1k 0.1u CC0402N CC0402N 090814
RC0603N CC0402N POP = NA POP = NA
2
E E
GND_USB
GND_USB
GND_USB
D D
To Main Board
C +V5_USB
C
12 12
11 11
10 UMH1
10
9 9
U_USB_PP0 8
U_USB_PN0 8 UMH2
7 7 E2 E2
U_USB_OC0# 6 E1
6 E1
5 5
U_USB_PP5 4
U_USB_PN5 4
3 3
U_USB_OC5# 2 2 GND_USB
1 1
B U_CN1 B
GND_USB

5th floor,Block K,
A Title <Title>
A
Size Sheet Rev
USB Board
C Name A
10 9 8 7 6 5 4 3 2 1
J J
I I
H H
G G
F F
E E
D D
C C
B B

5th floor,Block K,
A Title <Title>
A
Size Sheet Rev
3G Board
C Name A
ENGINEER: Ivan Date: Monday, October 11, 2010 Sheet 47 of 44

DNS m116cc (Lengda m116 Intel Calpella Reva)

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DNS m116cc (Lengda m116 Intel Calpella Reva)

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5 4 3 2 1

29 MiniCard2-3G {Item}\t{Lengda Code}\t{Quantity}\t{Reference}\t{100M}\t{NS3G}

Lengda Technology Ltd.

BLOCK DIAGRAM System Power

32.768KHz S3/S4 Control

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+V5 shutdown +V5A

CLK_PWRGD Clock GFX VR Lengda Technology Ltd.

AO +V_DC DDR2 POWER Module +V1.8 +V0.9S AO

1.5V POWER Module

U SYSTEM POWER Module U

SRC9 CLK_PCIE_3GPLL CLK_MCH_OE#

C18 C17 C16 20PF CC0402N XIN

+V1.1S_VTT +V1.1S_VTT +V1.1S_VTT +V3.3S

STRAP MODE STUFF UNSTUFF

R24 R25 R26 R27 NO OVERCLOCKING R26 PULL UP R27 PULLDOWN

R33 LVTTL CPU-ITP/SRC-8 select

FDI_TX[4] PEG_TX#[0] +V1.1S_VTT

JTAG & MBP

R135 0 RC0402N POP = NA

+V3.3A 13 DDR3_DRAMRST# 3 2 SM_DRAMRST#

sot65p190-5n +V1.5M_CPU C412 RC0402N

1.5K ±1% 1.1K ±1%

SA_CK[0] BM34 M_CLK_DDR0 13 SB_CK[0] BU33

BG25 SA_DQ[31] BT48 SB_DQ[32]

DDR SYSTEM MEMORY - B

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I RSVD33 W64 AH24

VSS (AP34) can be left NC is

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1.1V RAIL POWER

D CC0402N CC0402N CC0402N ARD_BGA_r1p0

C239 C281 C285 C284 C287 C286 C289 C288 C293

C303 C302 C304

AN19 AF71 GFX_VID0

PEG & DMI

Please note that the VTT Rail

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R89 0 RC0402N POP = NA

H +V3.3A R124 4.7K RC0402N

CPU FAN Control

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C121 C122 C123 C124 C125

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C146 12pF CC0402N

Use the RC circuit delay the RC0402N

R113 33 RC0402N BCLK A30

J30 HDA_DOCK_RST# / GPIO13 SATA4RXP AD8

34 ME_FLASH R870 1k RC0402N R131 51 RC0402N M3 AD3

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From CLK BUFFER

R163 0 RC0402N AM43 AP3

29 CLK_WLAN_OE# U4 PCIECLKRQ1# / GPIO18

R167 0 RC0402N AH42 P41

PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65

AK53 T42 R174 22 RC0402N POP = NA

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R284 100k RC0402N

U4C FDI_TXN[7:0] 7 22 GM_BKLTEN T48 BJ46

Digital Display Interface

7 PM_DRAM_PWRGD D9 E4 SLP_S5# BC46

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