Dell Latitude 5290 Compal LA-F391P DDM60 Rev1.0 (A00) Схема

A B C D E
COMPAL CONFIDENTIAL
1 MODEL NAME :DDM60 1
PCB NO : LA-F391P
BOM P/N : 431A8K31LXX
BR MLK12 KBL-U UMA

Kabylake U42
2
2017-09-25 2
REV :1.0 (A00)

@ : Nopop Component
EMC@ : EMI, ESD and RF Component
@EMC@ : EMI, ESD and RF Nopop Component
CXDP@ : XDP Component
CONN@ : Connector Component
U42@ : KBL-R U42 Component
3 3
U22@ : KBL-R U22 Component

DS3@ : Support DS3 Component
MB PCB
Part Number Description
NDS3@ : No Support DS3 Component
DAA000EB000 PCB 258 LA-F391P REV0 MB 1
650@ : Pop NPCT650VB2YX Component
Layout Dell logo
750@ : Pop NPCT750JAAYX Component
4 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
COPYRIGHT 2015
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
ALL RIGHT RESERVED TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Cover Sheet
REV:X00 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Re v
PWB: 9RJMF NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.2
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-F391P
Date : Monday, September 25, 2017 Sheet 1 of 70
A B C D E
A B C D E
BreckenridgeMLK 12 UMA Block Diagram Reverse Type
Memory BUS (DDR4) DDR4-SO-DIMM X2

BANK 0, 1, 2, 3
DDR4 2133MHz for KBL-U
2-Lane eDP1.3 DDR4 2400MHz for KBL-H P20~21
1 EDP CONN Up to 2x8GB Modules 1
P29
USB2.0[8]
LCD Touch
P29
HDMI 1.4 HDMI DDI[1]
CONN USB2.0[5]
P23 INTEL Camera
P29 Trough eDP Cable
USB2.0[9] SLGC55544BVTR USB2.0[9]_PS
USB POWER SHARE
P43
Kaby Lake Refresh U MCP USB USB3.0 Conn
SW2_DP1 DP DeMUX DDI[2] USB3.0[6]
PS(Ext Port 1)
To Type C PS8338B P43
P22
USB2.0[2]
SW2_DP3 USB3.0 Conn
VGA DP TO VGA USB3.0[3] (Ext Port 2) P44
CONN RTD2166 P24 To VGA
P24
2 2
PAGE 6~19
PCIE[1] PCIE[4] SATA[1]/PCIE[8] PCIE[3]
SATA[0]
Card reader Intel Jacksonville M.2,3042 Key B M.2,3030 Key A
RTS5242 P31 WGI219LM P30 WWAN/LTE/HCA SATA[2]/PCIE[12][11]
WLAN+BT
SPI
P33 P33
INT.Speaker
USB2.0[4] USB2.0[7] W25Q128JVSIQ P34
SD4.0 Transformer P8
ESPI
P31 P30
USB3.0[2] 128M 4K sector HD Audio I/F HDA Codec Universal Jack
W25Q128JVSIQ ALC3254 P34 P34
RJ45 P30 P8
128M 4K sector Dig. MIC
reserve P29
TPM1.2/2.0 Nuvoton
NPCT750JAAYX P38 Trough eDP Cable
SATA REPEATER
PI3EQX6741STZDEX SATA HDD
3 Conn P41 3
KB/TP CONN P41
SMSC KBC P45 LID SWITCH
LED board P46
MEC5105
P35-36 SATA/PCIE REPEATER
FAN CONN PS8558 x2 M.2 2280 USH CONN
P36 SSD Conn P40 P38
P39
Non-AR Type C CPU&PCH XDP Port

P14
DP1.2 4 lanes AUTOMATIC POWER

TX/RX
SW2_DP1 SWITCH(APS) P11
HS Redriver Switch
TUSB546@ USB3.0[1] Smart Card TDA8034HN
PS8743@ P25
USH TPM1.2 USB2.0[10] Free Fall sensor
P41
BCM58102
USB 3.0 + AM GPIO RFID/NFC SPI
Type C CONN. USB2.0 DC/DC Interface
SMBUS P47
CC PD Solut i on USB2.0[1] Fingerprint SPI

TPS65982DC CONN POWER ON/OFF
4
Vbus
SW & LED P46
4
P28 P26-27 USH board P39
5V VR DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Charger BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Block diagram
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Re v
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.2
LA-F391P
Date: Monday, September 25, 2017 Sheet 2 of 70
A B C D E
5 4 3 2 1
POWER STATES For Breckenridge12/14/15 UMA

M RUN CLOCKS
USB3.0 SSIC PCIE SATA DESTINATION USB PORT# DESTINATION
Signal SLP SLP SLP SLP ALWAYS SUS
S3# S4# S5# A# PLANE PLANE PLANE PLANE
State USB3.0-1 Type-C Port 1 Type-C Port
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON

USB3.0-2 SSIC M.2 3042(LTE) 2 JUSB2-->Lef t
USB3.0-3 JUSB2-->Lef t 3 JUSB3-->Rear Lef t
S3 (Suspend to RAM) / M3 LOW HIGH HIGH HIGH ON ON ON OFF OFF
USB3.0-4 JUSB3-->Rear Lef t 4 M2 3042(WWAN)
D D
S4 (Suspend to DISK) / M3 LOW LOW HIGH HIGH ON ON OFF OFF OFF USB3.0-5 PCIE-1 Card Reader 5 Camera
S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF

USB3.0-6 PCIE-2 JUSB1-->Right 6 NA
PCIE-3 M.2 3030(WLAN) 7 M.2 3030(BT)

S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON OFF ON OFF OFF
PCIE-4 LOM 8 Touch Screen
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF PCIE-5 NA 9 JUSB1-->Right
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF
PCIE-6 NA 10 USH
PCIE-7 SATA-0 SATA HDD
PM TABLE PCIE-8 SATA-1 M.2 3042(SATA Cache or HCA)
+5V_ALW PCIE-9 NA
+3.3V_ALW PCIE-10 NA
+3.3V_ALW_DSW +3.3V_CV2 +5V_RUN
+3.3V_ALW_PCH +1.2V_MEM +3.3V_RUN PCIE-11 SATA-1*
power
M.2 2280 SSD
C plane +RTC_CELL +2.5V_MEM +0.6V_DDR_VTT PCIE-12 SATA-2 (PCIex2 or SATA) C
+1.8V_PRIM +1.0V_VCCST +1.8V_RUN

12" not support JUSB3
+1.0V_PRIM +VCC_CORE
+1.0V_PRIM_CORE +VCC_GT
+5V_ALW2 +VCC_SA
State
+3.3V_ALW2 +1.0VS_VCCIO
+3.3V_RTC_LDO
+1.0V_MPHYGT
S0 ON ON ON
S3 ON ON OFF
S5 S4/AC ON OFF OFF
S5 S4/AC doesn't exist OFF OFF OFF
B B
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Port assignment
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number R ev
0.2
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F391P
5 4 3 2 1
5 4 3 2 1
PCH_PRIM_EN
(SIO_SLP_SUS#) CPU PWR
SIO_SLP_S4# SIO_SLP_S4#
TPS22961 PCH PWR
+1.2V_MEM (UZ26) +VCC_SFR_OC
GT3 PWR
SY8210A
(PU200) Peripheral Device PWR
0.6V_DDR_VTT_ON RUN_ O N
TPS22961 SIO_SLP_S0# TYPE-C Power
Barrel Type-C +0.6V_DDR_VTT (UZ19) +1.0V_VCCSTG
ADAPTER ADAPTER GPU PWR
SIO_SLP_S4#
TPS22961
D (UZ21) +1.0V_VCCST D
PCH_PRIM_EN
(SIO_SLP_SUS#)
SYX198D
(PU301) +1.0V_PRIM
RUN_ O N
CHARGER TPS62134C
ISL9538 +PWR_SRC +5V_ALW (PU401) +1.0VS_VCCIO
ALW O N
(PU901) SY8288C PCH_PRIM_EN
(PU102) TPS62134D
(SIO_SLP_SUS#)
(PU402) +1.0V_PRIM_CORE
+5V_ALW 2
3.3V_TS_EN
RUN_ O N @PCH_3.3V_TS_EN
EM5209 LP2301
(UZ4) +5V_RUN (QV8) +3.3V_TSP
BATTERY AUD_PW R_EN

EM5209
(@UZ5) +5V_RUN_AUDIO
USB_POW ERSHARE_VBUS_EN
SY8288B +3.3V_RTC_LDO SLGC55544C
(PU100) (UI3) +5V_USB_CHG_PW R
C ALW O N C
USB_PW R_EN1#
+3.3V_ALW 2 SY6288
(UI1) +USB_EX2_PW R
+3.3V_ALW
PCH_PRIM_EN RUN_ O N
RT8097A (SIO_SLP_SUS#) AOZ1336
(PU501) +1.8V_PRIM (UZ8) +1.8V_RUN
CSD97396Q
ISL95857 CSD97396Q (PU610) AO6405 SIO_SLP_LAN#
(PU602) (PU612) CSD97396Q (QV1) +3.3V_LAN

(PU613) EM5209
(UZ2)
IMVP_VR_ON
3.3V_W WAN_EN
IMVP_VR_ON
IMVP_VR_ON
U42@
EN_INVPWR
+3.3V_WWAN
@PCH_ALW _ON
PCH_PRIM_EN
(SIO_SLP_SUS#)
+3.3V_ALW _PCH
B EM5209 B
(UZ3)
RUN_ O N 3.3V_CAM_EN#
+VCC_SA +VCC_GT +VCC_CORE +BL_PWR_SRC LP2301A
+3.3V_RUN (QZ1) +3.3V_CAM
@SIO_SLP_W LAN#
AUX_EN_W OW L
EM5209 AUD_PW R_EN
(UZ4) +3.3V_WLAN EM5209
(@UZ5) +3.3V_RUN_AUDIO
LCD_VCC_TEST_EN
ENVDD_PC H
G524B1T11U
(UV24) +LCDVDD
TYPE-C
+TBTA_VBUS(5V~20V)
CV2_ON
TPS22967
(UZ18) +3.3V_CV2
USH/ B
SIO_SLP_S4#
AP7361C
(PU503) +2.5V_MEM
for DDR4
A
+5V_ALW A
AP2204 AP2112K
(UT8) (UT7) +3.3V_TBT_SX
+5V_TBT_VBUS
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power rails
0.2
Date: Tuesday, September 19, 2017 Sheet 4 of 70
5 4 3 2 1
5 4 3 2 1
1K 2.2K
1K
+3.3V_ALW_PCH 2.2K
+3.3V_RUN
R7 MEM_SMBCLK 202
DDR_XDP_WAN_SMBCLK
MEM_SMBD ATA
DMN66D0LDW -7
R8 200 DIMM1
DDR_XDP_WAN_SMBDAT
DMN66D0LDW -7
499
SKL-U 202
D +3.3V_ALW_PCH 200 DIMM2 D

499
R9 SML0_SMBCLK 28
SML0_SMBDATA 31 LOM
W2
V3 W3 53
51 XDP
1K
SML1_SMBDATA
SML1_SMBCLK
+3.3V_ALW_PCH
1K
1
E11 D8 2.2K LNG2DMTR
4
2.2K
+3.3V_TP
03 03
DAT_TP_SIO_I2C_CLK 9
02 C12
02 E10 CLK_TP_SIO_I2C_DAT 8 TP
2.2K 2.2K
+3.3V_ALW +3.3V_CV2
2.2K 2.2K
01 B3 USH_EXPANDER_SMBCLK M9
C C
E5
USH
01 USH_EXPANDER_SMBDAT L9
2.2K USH/B
KBC 2.2K +3.3V_ALW
00 D7 UPD2_SMBCLK
00 E7 UPD2_SMBDAT
2.2K @2.2K
2.2K +3.3V_ALW +3.3V_TBTA_FLASH

MEC 5105 @2.2K
04 C3 UPD1_SMBCLK 0ohm short pad UPD1_SMBCLK_Q B5 PD &

04 B4 UPD1_SMBDAT 0ohm short pad UPD1_SMBDAT_Q A5 FW reflash
F7
05
05 B6
B 06 A12 B
06 N10
07 M4
07 M7
08 C5
08 C8
09 F6
09 E9 2.2K
Charger
+3.3V_ALW
2.2K
100 ohm 4
10 N2 PBAT_CHARGER_SMBCLK
BATTERY
A 10 M3 PBAT_CHARGER_SMBD AT 100 ohm 5
CONN A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Port assignment
0.2
5 4 3 2 1
5 4 3 2 1
For 2LANE EDP,BR/SB12

+3.3V_RUN
UC1A CPU@ KBL-R U4+2
Rev_0.1
CPU_DP1_CTRL_CLK
2 1 E55 C47
RC175 2.2K_0402_5% <23> CPU_DP1_N0 F55 DDI1_TXN[0] EDP_TXN[0] C46 EDP_TXN0 <29>
CPU_DP1_CTRL_DATA <23> CPU_DP1_P0 DDI1_TXP[0] EDP_TXP[0] EDP_TXP0 <29>
2 1 E58 D46
RC178 2.2K_0402_5% <23> CPU_DP1_N1 F58 DDI1_TXN[1] EDP_TXN[1] C45 EDP_TXN1 <29>
2 1
CPU_DP2_CTRL_CLK HDMI <23> CPU_DP1_P1 F53 DDI1_TXP[1] EDP_TXP[1] A45 EDP_TXP1 <29>
D RC176 2.2K_0402_5% <23> CPU_DP1_N2 G53 DDI1_TXN[2] EDP_TXN[2] B45 D
CPU_DP2_CTRL_DATA <23> CPU_DP1_P2 DDI1_TXP[2] EDP_TXP[2]
2 1 F56 A47
RC177 2.2K_0402_5% <23> CPU_DP1_N3 G56 DDI1_TXN[3] EDP_TXN[3] B47
<23> CPU_DP1_P3 DDI1_TXP[3] EDP_TXP[3]
C50 E45
<22> CPU_DP2_N0 DDI2_TXN[0] DDI EDP_AUXN F45 EDP_AUXN <29>
D50 EDP
<22> CPU_DP2_P0 DDI2_TXP[0] EDP_AUXP EDP_AUXP <29>
C52
<22> CPU_DP2_N1 D52 DDI2_TXN[1] B52
PS8338(NON AR) <22> CPU_DP2_P1 A50 DDI2_TXP[1] EDP_DISP_UTIL
<22> CPU_DP2_N2 DDI2_TXN[2] CPU_DP1_AUXN
B50 G50
<22> CPU_DP2_P2 D51 DDI2_TXP[2] DDI1_AUXN F50 CPU_DP1_AUXP PAD~D @ T281
<22> CPU_DP2_N3 C51 DDI2_TXN[3] DDI1_AUXP E48 PAD~D @ T282
<22> CPU_DP2_P3 DDI2_TXP[3] DDI2_AUXN F48 CPU_DP2_AUXN <22>
DDI2_AUXP G46 CPU_DP3_AUXN CPU_DP2_AUXP <22>
DISPLAY SIDEBANDS RSVD F46 CPU_DP3_AUXP PAD~D @ T1
CPU_DP1_CTRL_CLK RSVD PAD~D @ T2
L13
<23> CPU_DP1_CTRL_CLK CPU_DP1_CTRL_DATA GPP_E18/DDPB_CTRLCLK
L12 L9
<23> CPU_DP1_CTRL_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7 CPU_DP1_HPD <23>
CPU_DP2_CTRL_CLK GPP_E14/DDPC_HPD1 L6 CPU_DP2_HPD <22> EDP_HPD
N7 1 2
<22> CPU_DP2_CTRL_CLK CPU_DP2_CTRL_DATA GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9
N8 RC1 100K_0402_5%
<22> CPU_DP2_CTRL_DATA GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10
N11 GPP_E17/EDP_HPD EDP_HPD <29>
GPP_E23 GPP_E22
N12 R12
T120 @ PAD~D GPP_E23 EDP_BKLTEN R11 PANEL_BKLEN <29>
EDP_COMP EDP_BKLTCTL U13 EDP_BIA_PWM <29>
RC2 2 1 24.9_0402_1% E52
+1.0VS_VCCIO EDP_RCOMP EDP_VDDEN ENVDD_PCH <29>
KBL-RU42_BGA1356 1 OF 20
COMPENSATION PU FOR eDP
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils. KBL-RU42_BGA1356.olb
C C
UC1I CPU@ KBL-R U4+2

Rev_0.1
CSI-2
A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
B B38 CSI2_DN3 CSI2_CLKN3 A26 B
CSI2_DP3 CSI2_CLKP3
CSI2_COMP
C31 E13 RC3 1 2 100_0402_1%
CSI2_DN4 CSI2_COMP B7 TBT_FORCE_PWR
D31
CSI2_DP4 GPP_D4/FLASHTRIG PAD~D @ T19
C33
D33 CSI2_DN5
A31 CSI2_DP5 EMMC
B31 CSI2_DN6 AP2
A33 CSI2_DP6 GPP_F13/EMMC_DATA0AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1AP3
CSI2_DP7 GPP_F15/EMMC_DATA2AN3
A29 GPP_F16/EMMC_DATA3AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
EMMC_RCOMP
AT1 1 2
EMMC_RCOMP RC4 200_0402_1%
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU (1/14)
LA-F391P
5 4 3 2 1
5 4 3 2 1
For DDR4
<21> DDR_B_DQS#[0..7]
<20> DDR_A_DQS#[0..7]
DDR4, Ballout for side by side(Non-Interleave) <20> DDR_A_D[0..63]
<21> DDR_B_D[0..63]
<21> DDR_B_DQS[0..7]
D <20> DDR_A_DQS[0..7] D
<21> DDR_B_MA[0..16]
UC1C CPU@ KBL-R U4+2
<20> DDR_A_MA[0..16] Rev_0.1
UC1B CPU@ KBL-R U4+2
DDR_A_D16 Interleave / Non-Interleaved DDR_B_CLK#0
Rev_0.1 AF65 AN45
DDR_A_D0 DDR_A_CLK#0 DDR_A_D17 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46 DDR_B_CLK#1 DDR_B_CLK#0 <21>
AL71 AU53 AF64
DDR_A_D1 DDR0_DQ[0] DDR0_CKN[0] AT53 DDR_A_CLK0 DDR_A_CLK#0 <20> DDR_A_D18 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] AP45 DDR_B_CLK0 DDR_B_CLK#1 <21>
AL68 AK65
DDR_A_D2 DDR0_DQ[1] DDR0_CKP[0] AU55 DDR_A_CLK#1 DDR_A_CLK0 <20> DDR_A_D19 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46 DDR_B_CLK1 DDR_B_CLK0 <21>
AN68 AK64
DDR_A_D3 DDR0_DQ[2] DDR0_CKN[1] AT55 DDR_A_CLK1 DDR_A_CLK#1 <20> DDR_A_D20 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 <21>
AN69 AF66
DDR_A_D4 DDR0_DQ[3] DDR0_CKP[1] DDR_A_CLK1 <20> DDR_A_D21 DDR1_DQ[4]/DDR0_DQ[20] DDR_B_CKE0
AL70 AF67 AN56
DDR_A_D5 DDR0_DQ[4] DDR_A_CKE0 DDR_A_D22 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] AP55 DDR_B_CKE1 DDR_B_CKE0 <21>
AL69 BA56 AK67
DDR_A_D6 DDR0_DQ[5] DDR0_CKE[0] BB56 DDR_A_CKE1 DDR_A_CKE0 <20> DDR_A_D23 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55 DDR_B_CKE2 DDR_B_CKE1 <21>
AN70 AK66
DDR_A_D7
AN71 DDR0_DQ[6] DDR0_CKE[1] AW56 DDR_A_CKE2 DDR_A_CKE1 <20> DDR_A_D24
AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53 DDR_B_CKE3 PAD~D @ T5
DDR_A_D8
AR70 DDR0_DQ[7] DDR0_CKE[2] AY56 DDR_A_CKE3 PAD~D @ T3 DDR_A_D25
AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3] PAD~D @ T6
DDR_A_D9
AR68 DDR0_DQ[8] DDR0_CKE[3] PAD~D @ T4 DDR_A_D26
AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42
DDR_B_CS#0
DDR_A_D10 DDR0_DQ[9] DDR_A_CS#0 DDR_A_D27 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] AY42 DDR_B_CS#1 DDR_B_CS#0 <21>
AU71 AU45 AH68
DDR_A_D11 DDR0_DQ[10] DDR0_CS#[0] AU43 DDR_A_CS#1 DDR_A_CS#0 <20> DDR_A_D28 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42 DDR_B_ODT0 DDR_B_CS#1 <21>
AU68 AF71
DDR_A_D12 DDR0_DQ[11] DDR0_CS#[1] AT45 DDR_A_ODT0 DDR_A_CS#1 <20> DDR_A_D29 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW42 DDR_B_ODT1 DDR_B_ODT0 <21>
AR71 AF69
DDR_A_D13 DDR0_DQ[12] DDR0_ODT[0] AT43 DDR_A_ODT1 DDR_A_ODT0 <20> DDR_A_D30 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDR_B_ODT1 <21>
AR69 AH70
DDR_A_D14 DDR0_DQ[13] DDR0_ODT[1] DDR_A_ODT1 <20> DDR_A_D31 DDR1_DQ[14]/DDR0_DQ[30]
AU70 AH69
DDR_A_D15 DDR0_DQ[14] DDR_A_D48 DDR1_DQ[15]/DDR0_DQ[31] DDR3L / LPDDR3 / DDR4 DDR_B_MA5
AU69 AT66 AY48
DDR0_DQ[15] DDR3L / LPDDR3 / DDR4 DDR_A_MA5 DDR_A_D49 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR_B_MA9
BA51 AU66 AP50
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR_A_MA9 DDR_A_D50 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR_B_MA6
BB54 AP65 BA48
DDR_A_D32 Interleave / Non-Interleaved DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR_A_MA6 DDR_A_D51 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR_B_MA8
BB65 BA52 AN65 BB48
DDR_A_D33 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR_A_MA8 DDR_A_D52 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR_B_MA7
AW65 AY52 AN66 AP48
DDR_A_D34 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR_A_MA7 DDR_A_D53 DDR1_DQ[20]/DDR0_DQ[52] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR_B_BG0
AW63 AW52 AP66 AP52
DDR_A_D35 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR_A_BG0 DDR_A_D54 DDR1_DQ[21]/DDR0_DQ[53] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR_B_MA12 DDR_B_BG0 <21>
AY63 AY55 AT65 AN50
DDR_A_D36 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_A_MA12 DDR_A_BG0 <20> DDR_A_D55 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR_B_MA11
BA65 AW54 AU65 AN48
DDR_A_D37 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR_A_MA11 DDR_A_D56 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR_B_ACT#
AY65 BA54 AT61 AN53
DDR_A_D38 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR_A_ACT# DDR_A_D57 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR_B_BG1 DDR_B_ACT# <21>
BA63 BA55 AU61 AN52
DDR_A_D39 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR_A_BG1 DDR_A_ACT# <20> DDR_A_D58 DDR1_DQ[25]/DDR0_DQ[57] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR_B_MA13 DDR_B_BG1 <21>
BB63 AY54 AP60 BA43
DDR_A_D40 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_MA13 DDR_A_BG1 <20> DDR_A_D59 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDR_B_MA15
BA61 AU46 AN60 AY43
C DDR_A_D41 DDR0_DQ[24]/DDR0_DQ[40] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR_A_MA15 DDR_A_D60 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR_B_MA14 C
AW61 AU48 AN61 AY44
DDR_A_D42 DDR0_DQ[25]/DDR0_DQ[41] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR_A_MA14 DDR_A_D61 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR_B_MA16
BB59 AT46 AP61 AW44
DDR_A_D43 DDR0_DQ[26]/DDR0_DQ[42] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR_A_MA16 DDR_A_D62 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR_B_BA0
AW59 AU50 AT60 BB44
DDR_A_D44 DDR0_DQ[27]/DDR0_DQ[43] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR_A_BA0 DDR_A_D63 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]AY47 DDR_B_MA2 DDR_B_BA0 <21>
BB61 AU52 AU60
DDR_A_D45 DDR0_DQ[28]/DDR0_DQ[44] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]AY51 DDR_A_MA2 DDR_A_BA0 <20> DDR_B_D16 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDR_B_BA1
AY61 AU40 BA44
DDR_A_D46 DDR0_DQ[29]/DDR0_DQ[45] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR_A_BA1 DDR_B_D17 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]AW46 DDR_B_MA10 DDR_B_BA1 <21>
BA59 AT48 AT40
DDR_A_D47 DDR0_DQ[30]/DDR0_DQ[46] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]AT50 DDR_A_MA10 DDR_A_BA1 <20> DDR_B_D18 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR_B_MA1
AY59 AT37 AY46
DDR_B_D0 DDR0_DQ[31]/DDR0_DQ[47] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR_A_MA1 DDR_B_D19 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR_B_MA0
AY39 BB50 AU37 BA46
DDR_B_D1 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR_A_MA0 DDR_B_D20 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
AW39 AY50 AR40
DDR_B_D2 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR_B_D21 DDR1_DQ[36]/DDR1_DQ[20] DDR_B_MA3
AY37 AP40 BB46
DDR_B_D3 DDR0_DQ[34]/DDR1_DQ[2] DDR_A_MA3 DDR_B_D22 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[3] BA47 DDR_B_MA4
AW37 BA50 AP37
DDR_B_D4 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] BB52 DDR_A_MA4 DDR_B_D23 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[4]
BB39 AR37
DDR_B_D5 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] AM70 DDR_A_DQS#0 DDR_B_D24 DDR1_DQ[39]/DDR1_DQ[23]
BA39 AT33
DDR_B_D6 DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQSN[0] AM69 DDR_A_DQS0 DDR_B_D25 DDR1_DQ[40]/DDR1_DQ[24] Interleave / Non-Interleaved DDR_A_DQS#2
BA37 AU33 AH66
DDR_B_D7 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSP[0] AT69 DDR_A_DQS#1 DDR_B_D26 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[0]/DDR0_DQSN[2]AH65 DDR_A_DQS2
BB37 AU30
DDR_B_D8 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSN[1] AT70 DDR_A_DQS1 DDR_B_D27 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[0]/DDR0_DQSP[2]AG69 DDR_A_DQS#3
AY35 AT30
DDR_B_D9 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSP[1] DDR_B_D28 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[1]/DDR0_DQSN[3]AG70 DDR_A_DQS3
AW35 AR33
DDR_B_D10 DDR0_DQ[41]/DDR1_DQ[9] DDR_B_D29 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[1]/DDR0_DQSP[3]AR66 DDR_A_DQS#6
AY33 AP33
DDR_B_D11 DDR0_DQ[42]/DDR1_DQ[10] Interleave / Non-Interleaved DDR_A_DQS#4 DDR_B_D30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[2]/DDR0_DQSN[6]AR65 DDR_A_DQS6
AW33 BA64 AR30
DDR_B_D12 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSN[2]/DDR0_DQSN[4]AY64 DDR_A_DQS4 DDR_B_D31 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[2]/DDR0_DQSP[6]AR61 DDR_A_DQS#7
BB35 AP30
DDR_B_D13 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSP[2]/DDR0_DQSP[4]AY60 DDR_A_DQS#5 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[3]/DDR0_DQSN[7]AR60 DDR_A_DQS7
BA35
DDR_B_D14 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSN[3]/DDR0_DQSN[5]BA60 DDR_A_DQS5 DDR_B_D48 DDR1_DQSP[3]/DDR0_DQSP[7]AT38 DDR_B_DQS#2
BA33 AU27
DDR_B_D15 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSP[3]/DDR0_DQSP[5]BA38 DDR_B_DQS#0 DDR_B_D49 DDR1_DQ[48] DDR1_DQSN[4]/DDR1_DQSN[2]AR38 DDR_B_DQS2
BB33 AT27
DDR_B_D32 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSN[4]/DDR1_DQSN[0]AY38 DDR_B_DQS0 DDR_B_D50 DDR1_DQ[49] DDR1_DQSP[4]/DDR1_DQSP[2]AT32 DDR_B_DQS#3
AY31 AT25
DDR_B_D33 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSP[4]/DDR1_DQSP[0]AY34 DDR_B_DQS#1 DDR_B_D51 DDR1_DQ[50] DDR1_DQSN[5]/DDR1_DQSN[3]AR32 DDR_B_DQS3
AW31 AU25
DDR_B_D34 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSN[5]/DDR1_DQSN[1]BA34 DDR_B_DQS1 DDR_B_D52 DDR1_DQ[51] DDR1_DQSP[5]/DDR1_DQSP[3]
AY29 AP27
DDR_B_D35 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSP[5]/DDR1_DQSP[1]BA30 DDR_B_DQS#4 DDR_B_D53 DDR1_DQ[52] DDR_B_DQS#6
AW29 AN27 AR25
DDR_B_D36 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSN[6]/DDR1_DQSN[4]AY30 DDR_B_DQS4 DDR_B_D54 DDR1_DQ[53] DDR1_DQSN[6] AR27 DDR_B_DQS6
BB31 AN25
DDR_B_D37 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSP[6]/DDR1_DQSP[4]AY26 DDR_B_DQS#5 DDR_B_D55 DDR1_DQ[54] DDR1_DQSP[6] AR22 DDR_B_DQS#7
BA31 AP25
DDR_B_D38 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSN[7]/DDR1_DQSN[5]BA26 DDR_B_DQS5 DDR_B_D56 DDR1_DQ[55] DDR1_DQSN[7] AR21 DDR_B_DQS7
BA29 AT22
DDR_B_D39
BB29 DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_B_D57
AU22 DDR1_DQ[56] DDR1_DQSP[7] AN43 DDR_B_ALERT# DDR1_PAR,DDR1_ALERT# for DDR4
DDR_B_D40
AY27 DDR0_DQ[55]/DDR1_DQ[39] AW50
DDR_A_ALERT# DDR0_PAR,DDR0_ALERT# for DDR4 DDR_B_D58
AU21 DDR1_DQ[57] DDR1_ALERT# AP43 DDR_B_PARITY DDR_B_ALERT# <21>
B DDR_B_D41 DDR0_DQ[56]/DDR1_DQ[40] DDR0_ALERT# DDR_A_PARITY DDR_A_ALERT# <20> DDR_B_D59 DDR1_DQ[58] DDR1_PAR AT13 DDR_DRAMRST# DDR_B_PARITY <21> B
AW27 AT52 AT21
DDR_B_D42 DDR0_DQ[57]/DDR1_DQ[41] DDR0_PAR DDR_A_PARITY <20> DDR_B_D60 DDR1_DQ[59] DRAM_RESET# AR18 SM_RCOMP0 DDR_DRAMRST# <20>
AY25 AN22 DDR CH - B
DDR_B_D43 DDR0_DQ[58]/DDR1_DQ[42] DDR_B_D61 DDR1_DQ[60] DDR_RCOMP[0] AT18 SM_RCOMP1
AW25 DDR CH - A AY67 +DDR_VREF_CA AP22
DDR_B_D44 DDR0_DQ[59]/DDR1_DQ[43] DDR_VREF_CA AY68 +DDR_VREF_A_DQ DDR_B_D62 DDR1_DQ[61] DDR_RCOMP[1] AU18 SM_RCOMP2
BB27 AP21
DDR_B_D45 DDR0_DQ[60]/DDR1_DQ[44] DDR0_VREF_DQ BA67 PAD~D @ T132 DDR_B_D63 DDR1_DQ[62] DDR_RCOMP[2]
BA27 +DDR_VREF_B_DQ AN21 3 OF 20
DDR_B_D46 DDR0_DQ[61]/DDR1_DQ[45] DDR1_VREF_DQ DDR1_DQ[63]
BA25
DDR_B_D47 DDR0_DQ[62]/DDR1_DQ[46]
BB25 2 OF 20 AW67 KBL-RU42_BGA1356
DDR0_DQ[63]/DDR1_DQ[47] DDR_VTT_CNTL DDR_VTT_CTRL <20>
KBL-RU42_BGA1356
DDR4 COMPENSATION SIGNALS

SM_RCOMP0
RC5 1 2 121_0402_1%
SM_RCOMP1
RC6 1 2 80.6_0402_1%
SM_RCOMP2
RC7 1 2 100_0402_1%
CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil
A A
LA-F391P
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
PCH EDS R0.7 p.235~236
UC1E CPU@ KBL-R U4+2
For BR/SB
2
Rev_0.1
SPI - FLASH
PCH_SPI_CLK SMBUS, SMLINK MEM_SMBCLK MEM_SMBCLK
AV2 R7 6 1
PCH_SPI_D1 SPI0_CLK GPP_C0/SMBCLK R8 MEM_SMBDATA DDR_XDP_WAN_SMBCLK <14,20,21,41>
AW3
PCH_SPI_D0 SPI0_MISO GPP_C1/SMBDATA R10 PCH_SMB_ALERT#
CXDP@ RC10 1 2 1K_0402_1% AV3 QC2A
<14> PCH_SPI_DO_XDP PCH_SPI_D2 SPI0_MOSI GPP_C2/SMBALERT#
5
CXDP@ RC11 1 2 1K_0402_1% AW2 DMN65D8LDW-7_SOT363-6
<14> PCH_SPI_DO2_XDP PCH_SPI_D3 SPI0_IO2 SML0_SMBCLK
AU4 R9
PCH_SPI_CS#0 SPI0_IO3 GPP_C3/SML0CLK W2 SML0_SMBDATA SML0_SMBCLK <30> MEM_SMBDATA
AU3 3 4
PCH_SPI_CS#1 SPI0_CS0# GPP_C4/SML0DATA W1 GPP_C5 SML0_SMBDATA <30> DDR_XDP_WAN_SMBDAT <14,20,21,41>
D AU2 D
PCH_SPI_CS#2 SPI0_CS1# GPP_C5/SML0ALERT#
AU1 QC2B
<37> PCH_SPI_CS#2 SPI0_CS2# SML1_SMBCLK
W3 DMN65D8LDW-7_SOT363-6 +3.3V_RUN
GPP_C6/SML1CLK V3 SML1_SMBDATA SML1_SMBCLK <35>
SPI - TOUCH GPP_C7/SML1DATA AM7 GPP_B23 SML1_SMBDATA <35>
GPP_B23/SML1ALERT#/PCHHOT# DDR_XDP_WAN_SMBDAT
M2 1 2
M3 GPP_D1/SPI1_CLK RC318 2.2K_0402_5%
GPP_D2/SPI1_MISO DDR_XDP_WAN_SMBCLK
J4 1 2
V1 GPP_D3/SPI1_MOSI RC319 2.2K_0402_5%
GPP_D21/SPI1_IO2 ESPI_IO0_R
V2 AY13 RC366 1 2 15_0402_5%
GPP_D22/SPI1_IO3 GPP_A1/LAD0/ESPI_IO0 BA13 ESPI_IO1_R ESPI_IO0 <35,36>
M1 LPC RC367 1 2 15_0402_5%
GPP_D0/SPI1_CS# GPP_A2/LAD1/ESPI_IO1 BB13 ESPI_IO2_R ESPI_IO1 <35,36>
RC368 1 2 15_0402_5% ESPI_IO2 <35,36>
GPP_A3/LAD2/ESPI_IO2 AY12 ESPI_IO3_R +3.3V_ALW_PCH
RC369 1 2 15_0402_5%
C LINK GPP_A4/LAD3/ESPI_IO3 BA12 ESPI_IO3 <35,36>
G3 GPP_A5/LFRAME#/ESPI_CS#BA11 ESPI_CS# <35,36>
<33> PCH_CL_CLK1 CL_CLK GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RESET# <35,36> MEM_SMBCLK
G2 1 2
<33> PCH_CL_DATA1 CL_DATA
G1 RC12 1K_0402_5%
<33> PCH_CL_RST1# CL_RST# ESPI_CLK MEM_SMBDATA
AW9 EMI@ RC16 1 2 15_0402_5% 1 2
GPP_A9/CLKOUT_LPC0/ESPI_CLKAY9 PCI_CLK_LPC1 ESPI_CLK_5105 <35,36>
@ RC22 1 2 22_0402_5%
SML1_SMBCLK RC14 1K_0402_5%
AW13 GPP_A10/CLKOUT_LPC1AW11 CLKRUN# 1 2
GPP_A0/RCIN# GPP_A8/CLKRUN# RC15 1K_0402_5%
SML1_SMBDATA
AY11 1 2
<35> ESPI_ALERT# GPP_A6/SERIRQ RC17 1K_0402_5%
SML0_SMBCLK
RC21 2 1 8.2K_0402_1% 1 2
+3.3V_1.8V_ESPI
KBL-RU42_BGA1356 5 OF 20 RC347 499_0402_1%
SML0_SMBDATA
1 2
RC348 499_0402_1%
+3.3V_LAN
C C
SOFTWARE TAA RF Request SML0_SMBCLK

1 2
@ RC19 499_0402_1%
PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R ESPI_CLK_5105 SML0_SMBDATA
1 2 1 2
@RF@ CC316 33P_0402_50V8J @ RC20 499_0402_1%
33_0402_5%
33_0402_5%
1
1
@EMI@
@EMI@
RPC1
RC28
RC29
PCH_SPI_D1_R1 PCH_SPI_D1_0_R SML0_SMBCLK

1 8 1 2
<37> PCH_SPI_D1_R1 PCH_SPI_D0_R1 PCH_SPI_D0_0_R
+3.3V_SPI 2 7 @RF@ CC318 33P_0402_50V8J CLKRUN# 1 2
PCH_SPI_CLK_R1 PCH_SPI_CLK_0_R
2
<37> PCH_SPI_D0_R1 3 6 LPC@ RC27 8.2K_0402_5%

<37> PCH_SPI_CLK_R1 PCH_SPI_D3_R1 PCH_SPI_D3_0_R SML1_SMBCLK
33P_0402_50V8J
33P_0402_50V8J
4 5 1 2
PCH_SPI_D2_R1
2 1 @RF@ CC319 33P_0402_50V8J
@EMI@
@EMI@
1
@ RC30 1K_0402_5% 33_0804_8P4R_5%

PCH_SPI_D3_R1 MEM_SMBCLK
CC7
CC8
2 1 1 2
@ RC31 1K_0402_5% @RF@ CC320 33P_0402_50V8J +3.3V_ALW_PCH
2
PCH_SPI_D3_R1
2 1
@ RC316 1K_0402_5%
PCH_SMB_ALERT#
1 2
PCH_SPI_D3_R1 PCH_SPI_D3_1_R
@ RC407 1 2 33_0402_5% Place close CPU side RC23 2.2K_0402_5%
PCH_SPI_CLK_R1 PCH_SPI_CLK_1_R
03/02:follow Intel MOW_2015WW06 @ RC408 1 2 33_0402_5%
PCH_SPI_D0_R1 PCH_SPI_D0_1_R
@ RC409 1 2 33_0402_5%
PCH_SPI_D1_R1
@ RC410 1 2 33_0402_5%
PCH_SPI_D1_1_R TLS CONFIDENTIALITY
HIGH ENABLE
LOW(DEFAULT) DISABLE
WEAK INTERNAL 20K PD
B B
+3.3V_ALW_PCH
GPP_C5
CONN@ 1 2
+3.3V_SPI ESPI@ RC25 4.7K_0402_5%
ACES_50506-02041-P01
PCH_SPI_CS#1_R1
CC9 2 1 1
PCH_SPI_CS#1 1
1 2 @RC32 0_0402_5% 2
2 1
PCH_SPI_D0_R1
3 2 EC interface
128Mb Flash ROM 0.1U_0201_10V6K 0_0402_5% RC33 @
PCH_SPI_D0
PCH_SPI_D1_R1
4 3
HIGH ESPI
UC5 2 1 5 4
PCH_SPI_CS#0_R1
@ RC37 1 2 0_0402_5%
PCH_SPI_CS#0_R2
1 8 0_0402_5% RC34 @
PCH_SPI_D1
6 5 LOW(DEFAULT) LPC
PCH_SPI_D1_0_R /CS VCC PCH_SPI_D3_0_R PCH_SPI_CLK_R1 6
2 7 2 1 7 WEAK INTERNAL 20k PD
PCH_SPI_D2_R1 PCH_SPI_D2_0_R IO1 IO3 PCH_SPI_CLK_0_R PCH_SPI_CLK 7
RC39 1 2 33_0402_5% 3 6
PCH_SPI_D0_0_R 0_0402_5% RC35 @ PCH_SPI_CS#0_R1 8
4 IO2 CLK 5 2 1 9 8
GND IO0 PCH_SPI_CS#0 9
0_0402_5% RC36 @ 10
PCH_SPI_D2_R1 10
W25Q128JVSIQ_SO8 2 1 11
PCH_SPI_D2 11 +3.3V_ALW_PCH
0_0402_5% RC38 @ 12
PCH_SPI_D3_R1 12
+3.3V_SPI 2 1 13
PCH_SPI_D3 13
0_0402_5% RC40 @ 14
@ CC10 15 14
+3.3V_SPI 15 GPP_B23
1 2 16 1 2
128Mb Flash ROM +3.3V_ALW_PCH
17 16 RC317 150K_0402_5%
0.1U_0201_10V6K 2 1 18 17
@ UC6 0_0402_5% RC41 @ 19 18
PCH_SPI_CS#1_R1 PCH_SPI_CS#1_R2 19
@ RC42 1 2 0_0402_5% 1 8 20
EXI BOOT STALL BYPASS
PCH_SPI_D1_1_R /CS VCC PCH_SPI_D3_1_R 20
2 7 21
PCH_SPI_D2_R1 PCH_SPI_D2_1_R IO1 IO3 PCH_SPI_CLK_1_R GND1
@ RC43 1 2 33_0402_5% 3 6 22
HIGH ENABLED
IO2 CLK PCH_SPI_D0_1_R GND2
4 5
GND IO0 JSPI1 LOW(DEFAULT) DIABLED
A W25Q128JVSIQ_SO8 WEAK INTERNAL PD A
LA-F391P
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
2 1
HDD_FALL_INT
For BR/SB UMA
RC370 10K_0402_5%
PCH_3.3V_TS_EN
2 1
@ RC282 100K_0402_5%
UC1F CPU@ KBL-R U4+2

SIO_EXT_SCI#
2 1 Rev_0.1
LPSS ISH
RC237 10K_0402_5%
LPSS_UART2_RXD
2 1
MEM_INTERLEAVED
@ RC402 49.9K_0402_1% <31> MEDIACARD_IRQ# AN8 P2
LPSS_UART2_TXD ONE_DIMM# GPP_B15/GSPI0_CS# GPP_D9 P3
2 1 AP7
TPM_PIRQ#_R GPP_B16/GSPI0_CLK GPP_D10 P4 AR_DET#
D @ RC403 49.9K_0402_1% 2 1 AP8 D
NRB_BIT GPP_B17/GSPI0_MISO GPP_D11 P1
RC560 0_0402_5% AR7
GPP_B18/GSPI0_MOSI GPP_D12
HDD_FALL_INT
AM5 M4
<41> HDD_FALL_INT SIO_EXT_SCI# GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA N3
2 1 AN7
<37> TPM_PIRQ# GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL +1.8V_RUN
@RC561 0_0402_5% AP5
<29> PCH_3.3V_TS_EN BBS_BIT6 GPP_B21/GSPI1_MISO
AN5 N1
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2 ISH_I2C2_SDA
1 2
GPP_C8 GPP_D8/ISH_I2C1_SCL
2 1 AB1 RC363 1K_0402_5%
GPP_C8/UART0_RXD ISH_I2C2_SDA ISH_I2C2_SCL
Reser ve @ RC405 100K_0402_5% AB2 AD11 1 2
<36> SBIOS_TX TYPEC_CON_SEL1
TYPEC_CON_SEL2
W4 GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDAAD12 ISH_I2C2_SCL ISH_I2C2_SDA <33> WWAN RC362 1K_0402_5%
AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL ISH_I2C2_SCL <33>
GPP_C11/UART0_CTS#
LPSS_UART2_RXD
AD1 U1
9/24: Reserve for embedded locat i on ,r ef er I nt el P DG 0. 9
LPSS_UART2_TXD GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA ISH_UART0_RXD <33>
AD2 U2
GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL ISH_UART0_TXD <33>
AD3 U3
AD4 GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS#U4 ISH_UART0_RTS# <33> WLAN
GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT# ISH_UART0_CTS# <33> +3.3V_RUN
+3.3V_ALW_PCH AC1
GPP_C12/UART1_RXD/ISH_UART1_RXD RTD3_CIO_PWR_EN SIO_EXT_WAKE# <35>
U7 AC2
U6 GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD AC3 PAD~D @ T18
GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# HDD_EN LCD_CBL_DET# <29> LCD_CBL_DET#
AB4 1 2
SIO_EXT_WAKE# GPP_C15/UART1_CTS#/ISH_UART1_CTS# HDD_EN <41>
2 1 U8 RC287 100K_0402_5%
<45> I2C1_SDA_TP U9 GPP_C18/I2C1_SDA AY8
RC283 10K_0402_5% CLKDET#
2 1
LPSS_UART2_RXD <45> I2C1_SCK_TP GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 BA8 PAD~D @ T258
@ RC330 49.9K_0402_1% AH9 GPP_A19/ISH_GP1 BB7
LPSS_UART2_TXD
2 1 AH10 GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BA7
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 AY7 TPM_TYPE
@ RC331 49.9K_0402_1%
GPP_A22/ISH_GP4 AW7 LID_CL#_PCH
AH11
AH12 GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 AP13 PAD~D @ T268
GPP_F7/I2C3_SCL Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6
AF11
C AF12 GPP_F8/I2C4_SDA GPP_A GROUP is +1.8V C
GPP_F9/I2C4_SCL
TPM_TYPE
1 2
@ RC349 100_0402_1%
+3.3V_RUN
+3.3V_RUN
NRB_BIT
2 1 TPM_TYPE no function,Reserve GPIO for future use,
10K_0402_5%
@ RC186 4.7K_0402_5%
2
@ RC267
RC349
NO REBOOT STRAP POP China TPM

HIGH No REBOOT
1
LOW(DEFAULT) REBOOT ENABLE ONE_DIMM#

DEPOP TPM
Internal 20k PD
1
10K_0402_5%
RC268
2
B +3.3V_ALW_PCH B
DIMM Detect
BBS_BIT6
2 1
@ RC184 8.2K_0402_5%
HIGH 1 DIMM
LOW 2 DIMM +3.3V_ALW_PCH
+3.3V_ALW_PCH
BOOT BIOS Dest i nat i on(Bi t 6
)
HIGH LPC
LOW(DEFAULT) SPI
2
2
Internal 20k PD RC400
+3.3V_ALW_PCH +3.3V_ALW_PCH @ RC371 10K_0402_5%
10K_0402_5%
1
2
@ RC555 @ RC553
AR_DET#
10K_0402_5% 10K_0402_5% MEM_INTERLEAVED
1
TYPEC_CON_SEL1 TYPEC_CON_SEL2
1
1
10K_0402_5%
1
10K_0402_5% @RC401
@ RC556 @ RC554 RC372
2
10K_0402_5% 10K_0402_5% AR_DET#
2
DIMM TYPE
2
HI GH NON AR
A HI GH Interleave A
LOW AR
LOW Non-Interleave
Vendor JAE FOXCON TBD TBD DELL CONFIDENTIAL/PROPRIETARY

TYPEC_CON_SEL1 LOW LOW HI GH HI GH
TYPEC_CON_SEL2 LOW HI GH LOW HI GH TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
LA-F391P
5 4 3 2 1
5 4 3 2 1
For NON AR, Breckenridge 12/14/15 UMA

UC1H CPU@ KBL-R U4+2
Rev_0.1
SSIC / USB3
PCIE / USB3 / SATA
H8
USB3_1_RXN G8 USB3_PRX_DTX_N1 <25>
H13 USB3_1_RXP C13 USB3_PRX_DTX_P1 <25>
D <31> PCIE_PRX_DTX_N1
<31> PCIE_PRX_DTX_P1
G13 PCIE1_RXN/USB3_5_RXN USB3_1_TXN D13 USB3_PTX_DRX_N1 <25> ----->Type-C Port D
B17 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3_PTX_DRX_P1 <25>
Card Reader RTS5242-----> <31> PCIE_PTX_DRX_N1 A17 PCIE1_TXN/USB3_5_TXN J6
<31> PCIE_PTX_DRX_P1 PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_RXNH6 USB3_PRX_DTX_N2 <33>
G11 USB3_2_RXP/SSIC_RXP B13 USB3_PRX_DTX_P2 <33>
<43> USB3_PRX_DTX_N6
<43> USB3_PRX_DTX_P6
F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_TXNA13 USB3_PTX_DRX_N2 <33> -----> M.2 3042(LTE)
D16 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_TXP USB3_PTX_DRX_P2 <33>
Ext USB3 Port 1 Charge-----> <43> USB3_PTX_DRX_N6 C16 PCIE2_TXN/USB3_6_TXN J10
USB3_PRX_DTX_N3 <44>
<43> USB3_PTX_DRX_P6 PCIE2_TXP/USB3_6_TXP USB3_3_RXN H10
H16 USB3_3_RXP B15 USB3_PRX_DTX_P3 <44>
<33> PCIE_PRX_DTX_N3
<33> PCIE_PRX_DTX_P3
G16 PCIE3_RXN USB3_3_TXN A15 USB3_PTX_DRX_N3 <44> -----> Ext USB3 Port 2
D17 PCIE3_RXP USB3_3_TXP USB3_PTX_DRX_P3 <44>
M.2 3030(WLAN) ---> <33> PCIE_PTX_DRX_N3 C17 PCIE3_TXN E10
<33> PCIE_PTX_DRX_P3 PCIE3_TXP USB3_4_RXN F10
G15 USB3_4_RXP C15
<30> PCIE_PRX_DTX_N4 PCIE4_RXN USB3_4_TXN D15
F15
<30> PCIE_PRX_DTX_P4 PCIE4_RXP USB3_4_TXP
B19
10/100/1G LAN ---> <30> PCIE_PTX_DRX_N4
A19 PCIE4_TXN AB9
USB20_N1 <26>
<30> PCIE_PTX_DRX_P4 PCIE4_TXP USB2N_1 AB10
F16 USB2P_1 USB20_P1 <26> -----> Typce-C(Non AR)
E16 PCIE5_RXN AD6
C19 PCIE5_RXP USB2N_2 AD7 USB20_N2 <44>
D19 PCIE5_TXN USB2P_2 USB20_P2 <44> -----> Ext USB Port 2(LEFT)
PCIE5_TXP AH3
G18 USB2N_3 AJ3
F18 PCIE6_RXN USB2P_3
D20 PCIE6_RXP AD9
PCIE6_TXN USB2N_4 AD10 USB20_N4 <33>
C20
PCIE6_TXP USB2P_4 USB20_P4 <33> -----> M2 3042(WWAN)
F20 AJ1
<41> SATA_PRX_DTX_N0 E20 PCIE7_RXN/SATA0_RXN USB2N_5 AJ2 USB20_N5 <29>
Spindle HDD---> <41> SATA_PRX_DTX_P0 B21 PCIE7_RXP/SATA0_RXP
USB2
USB2P_5 USB20_P5 <29> -----> Camera
C <41> SATA_PTX_DRX_N0 A21 PCIE7_TXN/SATA0_TXN AF6 C
<41> SATA_PTX_DRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 AF7
G21 USB2P_6
<33> PCIE_PRX_DTX_N8 PCIE8_RXN/SATA1A_RXN
F21 AH1
M.2 3042(SATA Cache <33> PCIE_PRX_DTX_P8
D21 PCIE8_RXP/SATA1A_RXP USB2N_7 AH2 USB20_N7 <33>
or/HCA)---> <33> PCIE_PTX_DRX_N8 C21 PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 <33> -----> M.2 3030(BT)
<33> PCIE_PTX_DRX_P8 PCIE8_TXP/SATA1A_TXP AF8
E22 USB2N_8 AF9 USB20_N8 <29>
E23 PCIE9_RXN USB2P_8 USB20_P8 <29> -----> LCD Touch
B23 PCIE9_RXP AG1
A23 PCIE9_TXN USB2N_9 AG2 USB20_N9 <43>
PCIE9_TXP USB2P_9 USB20_P9 <43> -----> Ext USB Port 1 Charge(RIGHT)
F25 AH7
PCIE10_RXN USB2N_10 AH8 USB20_N10 <38>
E25
D23 PCIE10_RXP USB2P_10 USB20_P10 <38> -----> USH
C23 PCIE10_TXN AB6 USBCOMP RC44 1 2 113_0402_1%
PCIE10_TXP USB2_COMP AG3 USB2_ID
PCIE_RCOMPN USB2_ID AG4 USB2_VBUSSENSE USB2_ID <26>
F5 RC338 1 2 1K_0402_5%
PCIE_RCOMPP PCIE_RCOMPN USB2_VBUSSENSE
RC45 1 2 100_0402_1% E5
PCIE_RCOMPP A9
D56 GPP_E9/USB2_OC0# C9 USB_OC0# <43>
<14> CPU_XDP_PRDY# PROC_PRDY# GPP_E10/USB2_OC1# D9 USB_OC2# USB_OC1# <44>
D61
<14> CPU_XDP_PREQ# PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC3#
BB11 Reser ve
GPP_A7/PIRQA# GPP_E12/USB2_OC3#
E28 J1
<39> PCIE_PRX_DTX_N11 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2 HDD_DEVSLP <41>
E27
<39> PCIE_PRX_DTX_P11 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3 M3042_DEVSLP <33>
D24
<39> PCIE_PTX_DRX_N11 C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 M2280_DEVSLP <40>
<39> PCIE_PTX_DRX_P11 E30 PCIE11_TXP/SATA1B_TXP H2
M2 2280 SSD ---> <39> PCIE_PRX_DTX_N12 F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0H3 M3042_PCIE#_SATA
M2280_PCIE_SATA#
HDD_DET# <39,41>
<39> PCIE_PRX_DTX_P12 A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1G4 M3042_PCIE#_SATA <35>
<39> PCIE_PTX_DRX_N12 B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 M2280_PCIE_SATA# <39,40>
B <39> PCIE_PTX_DRX_P12 PCIE12_TXP/SATA2_TXP H1 B
SATALED#
GPP_E8/SATALED# SATALED# <33,40,46>
USB2_ID
KBL-RU42_BGA1356 8 OF 20 RC337 1 2 10K_0402_5%
+3.3V_ALW_PCH
10K_8P4R_5%
USB_OC2#
1 8
USB_OC0#
2 7
USB_OC1#
3 6
USB_OC3#
4 5
RPC3
+3.3V_RUN
M2280_PCIE_SATA# RPC4
4 5
HDD_DET#
3 6
SATALED# 2 7
M3042_PCIE#_SATA
1 8
10K_8P4R_5%
A A
LA-F391P
5 4 3 2 1
5 4 3 2 1
For BR UMA
For KBL-R U22 U22@ CC21
1 2
15P_0402_50V8J
2
1M_0402_1%
3
4
U22@
RC46
U22@ YC1
24MHZ_12PF_X3G024000DC1H
1
2
XTAL24_IN_U22
D U22@ CC22 D
XTAL24_OUT_U22 XTAL24_OUT_U22_R
UC1J CPU@ KBL-R U4+2 1 2 1 2
Rev_0.1 Close to CPU
@ RC295 0_0402_5%
CLOCK SIGNALS XTAL24_IN_U42_CPU XTAL24_IN_U42 For Skylake,YC1 24 MHz (50 Ohm ESR) 15P_0402_50V8J
KBL-U / KBL-R U4+2
E3 XTAL24_OUT_U42_CPU U42@ RC417 1 2 33_0402_5% XTAL24_OUT_U42
For Cannonlake,YC1 38.4 MHz (30 Ohm ESR)
D42 RSVD_E3/XTAL24_IN C7 U42@ RC418 1 2 33_0402_5% 546765_546765_2014WW48_Skylake_MOW_Rev_1_0
<33> CLK_PCIE_N0 CLKOUT_PCIE_N0 RSVD_C7/XTAL24_OUT XTAL24_IN_U22_CPU XTAL24_IN_U22
CLKREQ_PCIE#0_R C42 E37 XTAL24_OUT_U22_CPU U22@ RC419 1 2 33_0402_5% XTAL24_OUT_U22
<33> CLK_PCIE_P0 2 1 RC373 @RF@ AR10 CLKOUT_PCIE_P0 XTAL24_IN/NC_2 E35 1 2
WWAN---> <33> CLKREQ_PCIE#0 0_0402_5% U22@ RC420 33_0402_5%
RC189 2 1 10K_0402_5% GPP_B5/SRCCLKREQ0# XTAL24_OUT/NC_1
+3.3V_RUN
WLAN--->
<33> CLK_PCIE_N1
<33> CLK_PCIE_P1
<33> CLKREQ_PCIE#1
0_0402_5% 2 1 RC374 @RF@
CLKREQ_PCIE#1_R
B42
A42
AT7
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
GPP_B6/SRCCLKREQ1#
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
F43
E43
CLK_ITPXDP_N
CLK_ITPXDP_P @ RC297
@ RC298
1
1
2 0_0402_5%
2 0_0402_5%
CLK_ITPXDP_N_R
CLK_ITPXDP_P_R
<14>
<14>
For KBL-R U42 CC334
U42@
1 2
RC47 2 1 10K_0402_5%
+3.3V_RUN
D41 BA17 SUSCLK 12P_0402_50V8J
SUSCLK <33,40>
2
CLKOUT_PCIE_N2 GPD8/SUSCLK
1M_0402_1%
CLKREQ_PCIE#2_R C41 U42@
CLKOUT_PCIE_P2
3
4
RC421
AT8
RC50 2 1 10K_0402_5% GPP_B7/SRCCLKREQ2# U42@YC3
+3.3V_RUN
D40 XCLK_BIASREF 24MHZ_12PF_X3G024000DC1H
<40> CLK_PCIE_N3 CLKOUT_PCIE_N3
CLKREQ_PCIE#3_R C40 E42 1 2
<40> CLK_PCIE_P3 +1.0V_CLK5
1
2
0_0402_5% 2 1 RC376 @RF@ AT10 CLKOUT_PCIE_P3 XCLK_BIASREF RC52 2.7K_0402_1%
M.2 SDD---> <40> CLKREQ_PCIE#3 2 1 10K_0402_5% GPP_B8/SRCCLKREQ3# AM18
PCH_RTCX1
1 2
XTAL24_IN_U42
+3.3V_RUN RC59 PCH_RTCX2 For Skylake, pop RC52,depop RC324 XTAL24_OUT_U42 XTAL24_OUT_U42_R CC335
U42@
B40 RTCX1 AM20 @ RC324 59_0402_1% For Cannonlake, pop RC324,depop RC52 1 2 1 2
<30> CLK_PCIE_N4 A40 CLKOUT_PCIE_N4 RTCX2
CLKREQ_PCIE#4_R 546765_546765_2014WW48_Skylake_MOW_Rev_1_0 U42@ RC422 33_0402_5%
<30> CLK_PCIE_P4 CLKOUT_PCIE_P4
LAN---> 0_0402_5% 2 1 RC377 @RF@ AU8 AN18 SRTCRST# RC56 1 2 20K_0402_5% +RTC_CELL_PCH For Skylake,YC3 24 MHz (50 Ohm ESR) 12P_0402_50V8J
<30> CLKREQ_PCIE#4 2 1 10K_0402_5% GPP_B9/SRCCLKREQ4# SRTCRST# AM16
+3.3V_RUN RC51
E40 RTCRST# CC24 1 2 1U_0402_6.3V6K
<31> CLK_PCIE_N5 E38 CLKOUT_PCIE_N5
<31> CLK_PCIE_P5 CLKREQ_PCIE#5_R CLKOUT_PCIE_P5 PCH_RTCRST# <35>
0_0402_5% 2 1 RC378 @RF@ AU7 CC23
Card Reader ---> <31> CLKREQ_PCIE#5
RC190 2 1 10K_0402_5% GPP_B10/SRCCLKREQ5# PCH_RTCRST#
RC57 1 2 20K_0402_5%
PCH_RTCX1
1 2
+3.3V_RUN PCH_RTCX2
CC25 1 2 1U_0402_6.3V6K 15P_0402_50V8J
1
RC54 YC2
1 2 10M_0402_5% 32.768KHZ_12.5PF_9H03200042
1 2 ESR MAX=50k ohm
2
1
+3.3V_LAN CC26
SHORT PADS~D PCH_RTCX2_R
PCH_PLTRST# 1 2 1 2
C C
1 2 @ CMOS1 @ RC296 0_0402_5%
PCH_PLTRST# PLTRST_TPM# <37>
LAN_WAKE# @ RC62 1 2 0_0402_5% @ RC60 0_0402_5% CMOS1 must take care short & touch risk on layout placement 12P_0402_50V8J
PLTRST_LAN# <30>
2 1 PCH_PLTRST#_AND
@ RL70 10K_0402_5% 1 2
@ RC244 1 2 0_0402_5% @ RC325 0_0402_5% SIO_SLP_SUS#
+3.3V_ALW_DSW PCH_PLTRST#_EC <36> 1 2
<18> VCCDSW_EN_GPIO @DS3@RC441 PCH_PRIM_EN <17,47,53,54,55>
0_0402_5%
+3.3V_ALW_PCH
2 1 @ RC445 NDS3@ DC1 NDS3@ RC442
VCCDSW_EN_Q
RC323 10K_0402_5% 1 2 2 1 1 2
<35> VCCDSW_EN
PCH_PCIE_WAKE#
5
2 1 0_0402_5% RB751S40T1G_SOD523-2 0_0402_5%

RC67 1K_0402_5% 1 PCH_PLTRST#_AND
P
B 4
PCH_PLTRST#_AND <31,33,38,40> NDS3@ DC2
2 O 1 2
<45,51> ALW_PWRGD_3V_5V
G
+1.0V_VCCST UC7 A
VCCST_PWRGD TC7SH08FU_SSOP5~D @ RC65 RB751S40T1G_SOD523-2
3
2 1 100K_0402_5%
RC71 1K_0402_5%
2
+3.3V_ALW_PCH RC439RC440RE536RC215RC441RC442
ME_SUS_PWR_ACK
2 1 +3.3V_ALW_DSW
@ RC74 10K_0402_5% Support DS3 V X V X V X 8/21 can change to 10K for merge to RP
10/6 depop, prevent singal step. PCH_BATLOW#
1 2
PCH_PWROK
2 1 No Support DS3 X V X V X V RC72 8.2K_0402_5%
AC_PRESENT
@ RC411 10K_0402_5% 1 2
RC243 10K_0402_5%
UC1K CPU@ KBL-R U4+2
'V' mean POP, 'X' mean DE-POP
Rev_0.1 +RTC_CELL_PCH
SYSTEM POWER MANAGEMENT
SIO_SLP_S0#
AT11
GPP_B12/SLP_S0# AP15 SIO_SLP_S0# <17,37,54>
INTRUDER# 1 2
PCH_PLTRST# GPD4/SLP_S3# SIO_SLP_S3# <35,36>
SYS_RESET# AN10 BA16 RC69 1M_0402_5%
B5 GPP_B13/PLTRST# GPD5/SLP_S4# AY16 SIO_SLP_S4# <17,35,52,55>
PCH_RSMRST#_AND SYS_RESET# GPD10/SLP_S5# SIO_SLP_S5# <35>
AY17 +3.3V_ALW_PCH
<14,45> PCH_RSMRST#_AND RSMRST# MPHYP_PWR_EN
H_CPUPWRGD_R H_CPUPWRGD AN15 1 2
B @ RC77 1 2 1K_0402_5% VCCST_PWRGD_CPU A68 SLP_SUS# AW15 SIO_SLP_SUS# <35> @ RC387 10K_0402_5% B
T9 @ PAD~D PROCPWRGD SLP_LAN# SIO_SLP_LAN# <35,47>
RC78 1 2 60.4_0402_1% B65 BB17 VRALERT# 1 2
<14,35,36> VCCST_PWRGD VCCST_PWRGD GPD9/SLP_WLAN# AN16 SIO_SLP_WLAN# <35,47> @ RC73 10K_0402_5%
B6 GPD6/SLP_A# SIO_SLP_A# <35>
<14,35> SYS_PWROK SYS_PWROK
BA20 BA15 1 2
<56> PCH_PWROK BB20 PCH_PWROK GPD3/PWRBTN# AY15 SIO_PWRBTN# <14,35>
PCH_BATLOW# @ RC344 10K_0402_5%
<35> PCH_DPWROK DSW_PWROK GPD1/ACPRESENT AC_PRESENT <35>
ME_SUS_PWR_ACK_R AU13
@ RC444 1 2 0_0402_5% AR13 GPD0/BATLOW# +3.3V_ALW
<35> ME_SUS_PWR_ACK SUSACK#_R GPP_A13/SUSWARN#/SUSPWRDNACK
@ RC443 1 2 0_0402_5% AP11 SIO_SLP_LAN#
<35> SUSACK# GPP_A15/SUSACK# AU11 PME# 1 2
BB15 GPP_A11/PME# AP16 PAD~D @ T115
INTRUDER# @ RC68 10K_0402_5%
+3.3V_1.8V_PGPPA <35,36> PCH_PCIE_WAKE# AM15 WAKE# INTRUDER#
<30,35> LAN_WAKE# GPD2/LAN_WAKE# MPHYP_PWR_EN
AW17 AM10
SUSACK#_R <30> PM_LANPHY_ENABLE GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE#
2 1 AT15 AM11 VRALERT# SUSCLK 1 2
<29> 3.3V_CAM_EN# GPD7/RSVD GPP_B2/VRALERT#
@ RC551 1K_0402_5% @ RC48 1K_0402_5%
2 1 KBL-RU42_BGA1356 11 OF 20 connect to VCCMPHYGTAON_1P0 enable pin

RC311 10K_0402_5%
JAPS1
1
+3.3V_ALW_PCH SIO_SLP_S3# 1
2
1 2 +3.3V_RUN 3 2
RC215 @ RC290 0_0402_5%
+3.3V_ALW SIO_SLP_S5#
4 3
SIO_SLP_S4# 4
POP NO Support Deep sleep 10K_0402_5% SYS_RESET# SIO_SLP_A# 5
2
6 5
RC291 @
DE-POP Support Deep sleep +3.3V_RUN 7 6

XDP_DBRESET# +3.3V_ALW 7
0.1U_0402_25V6
@ESD@
H_CPUPWRGD VCCST_PWRGD PCH_DPWROK PCH_RSMRST#_AND PCH_RTCRST# 8
1 2 <14> XDP_DBRESET# 9 8
9
5
1
RC215 0_0402_5% 10
1
+3.3V_RUN 10
100P_0402_50V8J
ESD@ CC300
100P_0402_50V8J
ESD@ CC301
NDS3@ 1 11
SYS_RESET#_R SYS_RESET#
P
B <36,46> POWER_SW#_MB 11
1
1
0.01UF_0402_25V7K
100K_0402_1%
1 ME_RESET# 4 1 2 SYS_RESET# 12
2
1
O 12
CC302
@ RC75 2 1 2 RC224 1K_0402_5% 13
A 13
G
CC266
RC220
10K_0402_5% @ RC225 8.2K_0402_5% @ UC12 SIO_SLP_S0# 14

2 1 74AHC1G09GW_TSSOP5 15 14
2
2 @ RC227 8.2K_0402_5% 16 15
2
17 16
ESD Request:place near CPU side 18 17
19 18
A GND A
if pop UC12, RC291 also need pop(74AHC1G09GW is OD output) 20
ESD Request:place near CPU side GND
CONN@
ACES_50506-01841-P01
0.2
5 4 3 2 1
5 4 3 2 1
+1.0V_VCCSTG
PCH_JTAG_TDI
1 2
RC81 51_0402_5%
PCH_JTAG_TDO
1 2
RC82 100_0402_5%
PCH_JTAG_TMS
1 2
UC1D CPU@ KBL-R U4+2 RC130 51_0402_5%
Rev_0.1
H_CATERR# CPU_XDP_TCLK XDP_JTAGX
D63 1 2
A54 CATERR# @ RC328 0_0402_5%
<35> PECI_EC PROCHOT#_R PECI
D 1 2 C65 D
<35,56,59> PROCHOT# H_THERMTRIP# PROCHOT# JTAG
RC84 499_0402_1% C63
<20,21,36> H_THERMTRIP# A65 THERMTRIP#
SKTOCC# CPU_XDP_TCLK
B61
CPU MISC PROC_TCK CPU_XDP_TDI CPU_XDP_TCLK <14>
C55 D60
<14> XDP_OBS0_R BPM#[0] PROC_TDI CPU_XDP_TDO CPU_XDP_TDI <14>
D55 A61
<14> XDP_OBS1_R XDP_OBS2_R BPM#[1] PROC_TDO CPU_XDP_TMS CPU_XDP_TDO <14>
T10 @ PAD~D B54 C60
XDP_OBS3_R BPM#[2] PROC_TMS CPU_XDP_TRST# CPU_XDP_TMS <14>
T11 @ PAD~D C56 B59
BPM#[3] PROC_TRST# CPU_XDP_TRST# <14>
1 2
+1.0V_VCCST SIO_EXT_SMI# PCH_JTAG_TCK
A6 B56 @ RC86 51_0402_5%
GPP_E3/CPU_GP0 PCH_JTAG_TCK D59 PCH_JTAG_TDI PCH_JTAG_TCK <14>
A7
H_CATERR# <29> TOUCH_SCREEN_PD# TOUCHPAD_INTR# GPP_E7/CPU_GP1 PCH_JTAG_TDI A56 PCH_JTAG_TDO PCH_JTAG_TDI <14>
2 1 BA5
<35,45> TOUCHPAD_INTR# GPP_B3/CPU_GP2 PCH_JTAG_TDO C59 PCH_JTAG_TMS PCH_JTAG_TDO <14>
@ RC79 49.9_0402_1% AY5
H_THERMTRIP# <29> TOUCH_SCREEN_DET# GPP_B4/CPU_GP3 PCH_JTAG_TMS C61 CPU_XDP_TRST# PCH_JTAG_TMS <14>
2 1
CPU_POPIRCOMP PCH_TRST# A59 XDP_JTAGX
RC80 1K_0402_5% AT16 1 2
PCH_POPIRCOMP +1.0V_VCCSTG
AU16 PROC_POPIRCOMP JTAGX @ RC87 1K_0402_5%
EDRAM_OPIO_RCOMP
+1.0V_VCCSTG H66 PCH_OPIRCOMP
EOPIO_RCOMP
H65 OPCE_RCOMP
2 1 PROCHOT# OPC_RCOMP
1
RC83 1K_0402_5%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
RC88
RC89
RC90
RC91
Service Mode Switch:
+3.3V_RUN Add a switch to ME_FWP signal to unlock the ME region and
2
TOUCHPAD_INTR#
allow the ent i r e r egi on of t he SPI f l ash to be updat ed us i ng FPT.
2 1
RC414 10K_0402_5% +3.3V_ALW_PCH
CAM_MIC_CBL_DET#
2 1
ME_FWP ME_FWP_PCH
RC413 10K_0402_5% 1 2
CONTACTLESS_DET#
2 1 @ RC221 0_0402_5%
2
RC278 10K_0402_5% PT,ST pop RC222 and SW1; MP pop RC221
TOUCH_SCREEN_PD#
2 1 TOUCH_SCREEN_PD# don't move to RPC, @ RC222
C @ RC272 10K_0402_5% 1K_0402_5% C
AUD_PWR_EN
2 1
RC279 10K_0402_5%
IR_CAM_DET#
1
2 1 @ SW1
RC345 100K_0402_5% <35> ME_FWP 1
HOST_SD_WP#
2 1 2 A
ME_FWP_PCH
RC292 10K_0402_5% 3 B
FFS_INT2
2 1 4 C
RC404 10K_0402_5% 5 G1
G2
SS3-CMFTQR9_3P
+3.3V_ALW_PCH ME_FWP PCH has internal 20K PD.
2 1
SIO_EXT_SMI# (suspend power rail)
RC346 10K_0402_5% FLASH DESCRIPTOR SECURITY OVERRIDE
UC1G CPU@ KBL-R U4+2
KB_DET#
2 1 Rev_0.1
RC288 10K_0402_5%
LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short
AUDIO
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short
HDA_SYNC
RC92 1 2 33_0402_5% BA22
<34> HDA_SYNC_R HDA_BIT_CLK HDA_SYNC/I2S0_SFRM
EMI@ RC93 1 2 33_0402_5% AY22
<34> HDA_BIT_CLK_R HDA_SDOUT HDA_BLK/I2S0_SCLK
RC94 1 2 33_0402_5% BB22 SDIO / SDXC
<34> HDA_SDOUT_R ME_FWP_PCH 1 2 BA21 HDA_SDO/I2S0_TXD
RC223 1K_0402_5%
<34> HDA_SDIN0 HDA_SDI0/I2S0_RXD
AY21 AB11
HDA_RST# HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13 CAM_MIC_CBL_DET# <29>
RC95 1 2 33_0402_5% AW22
<34> HDA_RST#_R FFS_INT2 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12
<41> FFS_INT2 J5
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
I2S1_SFRM GPP_G3/SD_DATA2 W11 CONTACTLESS_DET#
AW20
HDA_BIT_CLK_R I2S1_TXD GPP_G4/SD_DATA3 W10 CONTACTLESS_DET# <38>
GPP_G5/SD_CD# W8 AUD_PWR_EN HOST_SD_WP# <31>
AK7
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7 AUD_PWR_EN <34>
1 GPP_F0/I2S2_SCLK GPP_G7/SD_WP SPK_DET# <34>
AK9
B RF@ CC27 AK10 GPP_F2/I2S2_TXD BA9 B
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7BB9
47P_0402_50V8J GPP_A16/SD_1P8_SEL
2
IR_CAM_DET# SD_RCOMP
H5 AB7 RC96 1 2 200_0402_1%
<29> IR_CAM_DET# GPP_D19/DMIC_CLK0 SD_RCOMP
D7
Close to RC93 GPP_D20/DMIC_DATA0
KB_DET#
D8 AF13
<45> KB_DET# C8 GPP_D17/DMIC_CLK1 GPP_F23
GPP_D18/DMIC_DATA1
AW5
<34> SPKR GPP_B14/SPKR
PCH_JTAG_TDO PCH_JTAG_TDI XDP_JTAGX H_THERMTRIP#
PROCHOT#
0.1U_0402_25V6
@ESD@
0.1U_0402_25V6
@ESD@
0.1U_0402_25V6
@ESD@
@ESD@
0.1U_0402_25V6
@ESD@
0.1U_0402_25V6
1
1
RF Request. Place near CPU side (Intel MOW)
2
CC303
CC304
CC305
CC312
CC310
HDA_RST# HDA_SDIN0 HDA_SDOUT
+3.3V_ALW_PCH +3.3V_ALW_PCH
HDA_SDOUT
2 1 SPKR 2 1
@ RC183 8.2K_0402_5% @ RC187 4.7K_0402_5% 1 1 1 ESD request,Place near CPU side.
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
@RF@ CC331
@RF@ CC332
@RF@ CC333
2 2 2
A
TOP SWAP STRAP Flash Descriptor Security override A
HIGH ENABLE HIGH DISABLE

LOW(DEFAULT) DISABLE LOW(DEFAULT) ENABLE
Internal 20k PD
LA-F391P
5 4 3 2 1
5 4 3 2 1
<14> CFG[0..19]
D D
CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin

UC1S CPU@ KBL-R U4+2
Rev_0.1 UC1T CPU@ KBL-R U4+2
RESERVED SIGNALS-1 Rev_0.1
2 1 CFG0 SPARE
@ RC113 10K_0402_1% CFG0 E68 BB68 1/5 2014WW52 MOW reserve to support
2 1 B67 CFG[0] RSVD_TP_BB68 BB69 PAD~D @ T12 Cannonlake-U PCH compatibility AW69 F6
CFG1
D65 CFG[1] RSVD_TP_BB69 PAD~D @ T13 AW68 RSVD_AW69 RSVD_F6
@ RC112 10K_0402_1% CFG2 close UC1.U11/U12 and <400mil
2 1 CFG3 D67 CFG[2] AK13 AU56 RSVD_AW68 C11
E70 CFG[3] RSVD_TP_AK13 AK12 PAD~D @ T14 +1.8V_PRIM +VCC_1P8 AW48 RSVD_AU56 RSVD_C11 B11
@ RC110 10K_0402_1% CFG4
CFG[4] RSVD_TP_AK12 PAD~D @ T15 RSVD_AW48 RSVD_B11
CFG5 C68 A11
CFG6 D68 CFG[5] BB2 1 2 U12 RSVD_A11 D12
Stall reset sequence CFG7 C67 CFG[6] RSVD_BB2 BA3 @ RC313 0_0402_5% U11 RSVD_U12 RSVD_D12 C12
CFG8 F71 CFG[7] RSVD_BA3 H11 RSVD_U11 RSVD_C12 F52
HIGH(DEFAULT) No stall(Normal Operat i on) 1
1U_0402_6.3V6K
CFG9 G69 CFG[8] RSVD_H11 RSVD_F52
LOW sta l l CFG10 F70 CFG[9] AU5
CC222
G68 CFG[10] TP5 AT5 PAD~D @ T128
CFG11
H70 CFG[11] TP6 PAD~D @ T129 2
CFG12 KBL-RU42_BGA1356 20 OF 20
CFG13 G71 CFG[12] @
CFG14 H69 CFG[13] D5
CFG15 G70 CFG[14] RSVD_D5 D4
CFG[15] RSVD_D4 B2
CFG16 E63 RSVD_B2 C2
CFG17 F63 CFG[16] RSVD_C2
CFG[17] B3
CFG18 E66 RSVD_B3 A3
CFG19 F66 CFG[18] RSVD_A3
C 2 1 CFG4 CFG[19] AW1 C
CFG_RCOMP RSVD_AW1
RC109 1K_0402_5% 2 1 E60
RC114 49.9_0402_1% CFG_RCOMP E1
ITP_PMODE RSVD_E1 E2
+1.0V_PRIM_XDP 2 1 E8
RC115 1.5K_0402_5% ITP_PMODE RSVD_E2
AY2 BA4
AY1 RSVD_AY2 RSVD_BA4 BB4
<14> ITP_PMODE RSVD_AY1 RSVD_BB4
eDP enable D1 A4
D3 RSVD_D1 RSVD_A4 C4
HIGH(DEFAULT) Disabled RSVD_D3 RSVD_C4
LOW Enabled K46 BB5
K45 RSVD_K46 TP4 PAD~D @ T130
RSVD_K45 A69
AL25 RSVD_A69 B69
AL27 RSVD_AL25 RSVD_B69
RSVD_AL27 AY3
C71 RSVD_AY3
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70
F60 RSVD_C70
RSVD_F60 C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54
T16 @ PAD~D BA70 AY4
RSVD_TP_BA70 TP1 BB3 PAD~D @ T126
T17 @ PAD~D BA68
RSVD_TP_BA68 TP2 PAD~D @ T127
J71 AY71
J68 RSVD_J71 VSS_AY71 AR56
RSVD_J68 ZVM#
1 2 F65 AW71
ZVM# for SKYLAKE-U 2+3e
U42@RC436 G65 VSS_F65 RSVD_TP AW70 PAD~D @ T113
0_0402_5%
B VSS_G65 RSVD_TP PAD~D @ T114 B
F61 AP56
E61 RSVD_F61 MSM# C64 1 2
MSM# for SKYLAKE-U 2+3e
RSVD_E61 PROC_SELECT# +1.0V_VCCST
@ RC120 100K_0402_5%
For Skylake , RC120 depop

KBL-RU42_BGA1356 19 OF 20 For Cannonlake, RC120 pop
546765_546765_2014W W 48_Skylake_MOW _Rev_1_0
PROC_SELECT#:This pin is for compatibility

with future platforms. It should be unconnected
for KBL
A A
LA-F391P
5 4 3 2 1
5 4 3 2 1
+1.0V_PRIM +1.0V_PRIM_XDP
1 2 +1.0V_PRIM_XDP CXDP@
@ RC216 0_0603_1% CPU XDP XDP_PRSNT_PIN1
1
RC121
2 CFG3
0_0402_5% +1.0V_PRIM_XDP
<13> CFG[0..19]
1 2 +3.3V_RUN
@ RC122 0_0402_5%
+1.0V_PRIM_XDP JXDP1 CC30
1 2 2 1
CPU_XDP_PREQ# GND0 GND1 4 UC8
<10> CPU_XDP_PREQ# 3 CFG17
CPU_XDP_PRDY# OBSFN_A0 OBSFN_C0 6
0.1U_0201_10V6K
0.1U_0201_10V6K
5 CFG16 0.1U_0201_10V6K
<10> CPU_XDP_PRDY# OBSFN_A1 OBSFN_C1 8
@ CC28
@ CC29
1 1 7 14
CFG0 9 GND2 GND3 10 CFG8 VCC
OBSDATA_A0 OBSDATA_C0 12 TDO_XDP
CFG1 11 CFG9 2 3 CPU_XDP_TDO <12>
13 OBSDATA_A1 OBSDATA_C1 14 1A 1B
D 2 2 CFG2 15 GND4 GND5 16 CFG10 D
CFG3 17 OBSDATA_A2 OBSDATA_C2 18 CFG11 1
19 OBSDATA_A3 OBSDATA_C3 20 1OE
XDP_OBS0 GND6 GND7 22 TDI_XDP
CXDP@ RC239 1 2 0_0402_5% 21 CFG19 5 6 CPU_XDP_TDI <12>
<12> XDP_OBS0_R XDP_OBS1 OBSFN_B0 OBSFN_D0 24 2A 2B
CXDP@ RC240 1 2 0_0402_5% 23 CFG18
<12> XDP_OBS1_R OBSFN_B1 OBSFN_D1 26
25
Place near CFG4 27 GND8 GND9 28 CFG12 4
JXDP1 CFG5 29 OBSDATA_B0 OBSDATA_D0 30 CFG13 2OE
OBSDATA_B1 OBSDATA_D1 32 XDP_TMS
RC5 need to close to JCPU1 31 9 8 CPU_XDP_TMS <12>
CFG6 33 GND10 GND11 34 CFG14 3A 3B
@ RC123 1 2 1K_0402_5% CFG7 35 OBSDATA_B2 OBSDATA_D2 36 CFG15
<11,35,36> VCCST_PWRGD 37 OBSDATA_B3 OBSDATA_D3 38 10
H_VCCST_PWRGD_XDP GND12 GND13 40 3OE
<11,45> PCH_RSMRST#_AND CXDP@ RC124 1 2 39
PWRGOOD/HOOK0 ITPCLK/HOOK4 42 CLK_ITPXDP_P_R <11> TRST#_XDP
1K_0402_5% 41 12 11 CPU_XDP_TRST# <12>
FIVR_EN <11,35> SIO_PWRBTN# HOOK1 ITPCLK#/HOOK5 44 CLK_ITPXDP_N_R <11> 4A 4B
@ RC217 1 2 0_0402_5% 43
FIVR_EN_R VCC_OBS_AB VCC_OBS_CD 46 ITP_PMODE
CFG0 @ RC126 1 2 1K_0402_5% 45
RESET_OUT#_R HOOK2 RESET#/HOOK6 48 XDP_DBRESET# ITP_PMODE <13>
CXDP@ RC128 1 2 0_0402_5% 47 XDP_DBRESET# <11> 13 7
<8> PCH_SPI_DO_XDP HOOK3 DBR#/HOOK7 50 <35> RUNPWROK 4OE GND
@ RC129 1 2 0_0402_5% 49
<11,35> SYS_PWROK GND14 GND15 52 TDO_XDP
51 15
<8,20,21,41> DDR_XDP_WAN_SMBDAT SDA TD0 54 TRST#_XDP GND PAD
53
<8,20,21,41> DDR_XDP_WAN_SMBCLK SCL TRST# 56 TDI_XDP
55
<12> PCH_JTAG_TCK CPU_XDP_TCLK TCK1 TDI 58 XDP_TMS
<12> CPU_XDP_TCLK 57
TCK0 TMS 60 74CBTLV3126BQ_DHVQFN14_2P5X3
59
GND16 GND17 PCH_SPI_DO2_XDP <8>
SAMTE_BSH-030-01-L-D-A CONN@
+1.0V_VCCSTG
+1.0VS_VCCIO +3.3V_ALW_PCH
CPU_XDP_TMS
1 2
FIVR_EN_R
2 1 RC131 51_0402_5%
1.5K_0402_5%
CXDP@ RC133
CPU_XDP_TDI
2
C RC132 150_0402_5% +3.3V_ALW_DSW 1 2 C
+1.0V_VCCST RC134 51_0402_5%
CPU_XDP_TDO
1.5K_0402_5%
1 2
FIVR_EN
@ RC241
2 1 RC135 100_0402_5%
@ RC218 150_0402_5%
1
FIVR_EN CPU_XDP_TRST#
2 1 1 2
PCH_SPI_DO_XDP
@ RC219 10K_0402_5% Place near JXDP1.48 @ RC136
CPU_XDP_TCLK 51_0402_5%
1
1 2
RESET_OUT#_R XDP_DBRESET# SIO_PWRBTN#
RC139 51_0402_5%
0.1U_0402_25V6
0.1U_0402_25V6
CXDP@ CC32
0.1U_0402_25V6
1
@ CC33
@
CC269
1
+3.3V_RUN Place near JXDP1.41 XDP_TMS
2
1 2
PCH_JTAG_TMS <12>
2
TDI_XDPRC228 0_0402_5%
@
XDP_DBRESET#
2
2 1 1 2
PCH_JTAG_TDI <12>
RC137 3K_0402_5% @ RC229 0_0402_5%
+1.0V_PRIM_XDP TDO_XDP
1 2
@ RC230
PCH_JTAG_TDO <12>
0_0402_5%
2 1
CPU_XDP_PREQ# Place near JXDP1.47
@ RC138 51_0402_5%
TDO_XDP H_VCCST_PWRGD_XDP CPU_XDP_TRST#

B B
0.1U_0402_25V6
@ESD@
0.1U_0402_25V6
@ESD@
0.1U_0402_25V6
@ESD@
1
1
2
2
CC306
CC307
CC308
ESD request,Place near JXDP1 side. ESD request,Place near UC8 side.
A A
LA-F391P
5 4 3 2 1
5 4 3 2 1
+VCC_CORE: 0.3~1.35V +VCC_CORE +VCC_CORE

PSC(Primary side cap) : Place as close to the package as possible
UC1L CPU@ KBL-R U4+2 BSC(Backside cap) : Place on secondary side, underneath the package
Rev_0.1
CPU POWER 1 OF 4
A30 G32
A34 VCC_A30 VCC_G32 G33
Component placement order:
A39 VCC_A34 VCC_G33 G35 Package edge > 0402 caps > 0805 caps > Bulk caps >Power source
A44 VCC_A39 VCC_G35 G37
AK33 VCC_A44 VCC_G37 G38
AK35 VCC_AK33 VCC_G38 G40
AK37 VCC_AK35 VCC_G40 G42
AK38 VCC_AK37 VCC_G42 J30
D AK40 VCC_AK38 VCC_J30 J33 D
AL33 VCC_AK40 VCC_J33 J37
AL37 VCC_AL33 VCC_J37 J40
AL40 VCC_AL37 VCC_J40 K33 +VCC_CORE
AM32 VCC_AL40 VCC_K33 K35
AM33 VCC_AM32 VCC_K35 K37
100_0402_1%
VCC_AM33 VCC_K37
2
AM35 K38
RC140
G30 VCC_AM38 VCC_K42 K43
VCC_G30 VCC_K43
+VCC_CORE_G0
1
K32 E32 VCCSENSE
T122 @ PAD~D RSVD VCC_SENSE E33 VCCSENSE <56>
VSSSENSE
+VCC_CORE_G1 VSS_SENSE VSSSENSE <56>
AK32
T123 @ PAD~D RSVD H_CPU_SVIDALRT#
1
B63
100_0402_1%
AB62 VIDALERT# A63 VIDSCLK
VCCOPC_AB62 VIDSCK D64 VIDSCLK <56>
P62 VIDSOUT
RC141
V62 VCCOPC_P62 VIDSOUT
VCCOPC_V62 G20
2
H63 VCCSTG_G20
VCC_OPC_1P8_H63
G61
VCC_OPC_1P8_G61
AC63
AE63 VCCOPC_SENSE
VSSOPC_SENSE +1.0V_VCCSTG_R
1 2 +1.0V_VCCSTG
AE62 @ RC143 0_0603_5%
AG62 VCCEOPIO
VCCEOPIO
AL63
AJ62 VCCEOPIO_SENSE
VSSEOPIO_SENSE
C C
RF Request
VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e
(w/ on package cache) VIDSCLK 1 2
@RF@ CC321 33P_0402_50V8J
Place close CPU side
B B
+1.0V_VCCST
SVID ALERT
56_0402_1%
2
RC152
CAD Note: Place the PU resistors close to CPU

RC204 close to CPU 300 - 1500mils
1
H_CPU_SVIDALRT#
2 1
<56> VIDALERT_N
220_0402_5% RC153
+1.0V_VCCST
SVID DATA
2
100_0402_1%
CAD Note: Place the PU resistors close to CPU

RC157
RC208close to CPU 300 - 1500mils

1
A VIDSOUT A
<56> VIDSOUT
LA-F391P
5 4 3 2 1
5 4 3 2 1
+VCCGT: 0.3~1.35V
KBL-R 4+2 and KBL-U 2+2&2+3e opt i on ( pl ace on po wer page)

+VCC_GT_+VCC_CORE +VCC_GT
UC1M CPU@ KBL-R U4+2

Rev_0.1
CPU POWER 2 OF 4
D A48 KBL-U / KBL-R U4+2 N70 D
A53 VCCGT/VCCCORE_5 VCCGT N71
J43 VCCGT/VCCCORE_6 VCCGT R63
J45 VCCGT/VCCCORE_44 VCCGT R64
J46 VCCGT/VCCCORE_45
VCCGT/VCCCORE_48
VCCGT R65
VCCGT R66
VCCGT R67
VCCGT R68
Follow KBL-R_U42_Processor_Line_BGA1356_Ballout_Rev1p0
J52
K48 VCCGT/VCCCORE_49 VCCGT R69
K50 VCCGT/VCCCORE_57 VCCGT R70
+VCC_GT_K52
1 2 K52 VCCGT/VCCCORE_58 VCCGT R71
+VCC_GT VCCGT/RSVD_6 VCCGT T62
@ RC437 0_0402_5%
A58 VCCGT U65
+VCC_GT
A62 VCCGT VCCGT U68
A66 VCCGT VCCGT U71
AA63 VCCGT VCCGT W63
AC64 VCCGT VCCGT W70
AC65 VCCGT VCCGT W71 KBL-R 4+2 and KBL-U 2+2&2+3e opt i on ( pl ace on po wer page)
AC66 VCCGT VCCGT Y62 +VCC_GT_+VCC_CORE
AC67 VCCGT VCCGT
AC68 VCCGT KBL-U / KBL-R U4+2 AK42
AC69 VCCGT VCCGTX_AK42/VCCCORE_12 AK43
AC70 VCCGT VCCGTX_AK43/VCCCORE_13AK45
AC71 VCCGT VCCGTX_AK45/VCCCORE_14AK46
J53 VCCGT VCCGTX_AK46/VCCCORE_15AK48
J55 VCCGT VCCGTX_AK48/VCCCORE_16AK50
C J56 VCCGT VCCGTX_AK50/VCCCORE_17AL43 C
J58 VCCGT VCCGTX_AL43/VCCCORE_21AL46
J60 VCCGT VCCGTX_AL46/VCCCORE_22AL50
K53 VCCGT VCCGTX_AL50/VCCCORE_23AM48
K55 VCCGT VCCGTX_AM48/VCCCORE_29AM50
K56 VCCGT VCCGTX_AM50/VCCCORE_30 AM52
VCCGT VCCGTX_AM52/VCCCORE_31 +VCC_GT_AK52
K58 AK52 1 2 +VCC_GT
K60 VCCGT VCCGTX_AK52/RSVD_5 @ RC438 0_0402_5%
L62 VCCGT AK53
+VCC_GTX
L63 VCCGT VCCGTX_AK53 AK55
L68 VCCGT VCCGTX_AK70 AL53
+VCC_GT L69 VCCGT VCCGTX_AL53 AL56 VCCGTX for KBL-U 2+3e only
L70 VCCGT VCCGTX_AL56 AL60
L71 VCCGT VCCGTX_AL60 AM53
M62 VCCGT VCCGTX_AM53 AM56
100_0402_1%
N63 VCCGT VCCGTX_AM56 AM58

2
RC161
N64 VCCGT VCCGTX_AM58 AU58

N66 VCCGT VCCGTX_AU58 AU63
N67 VCCGT VCCGTX_AU63 BB57 Avoid adding via to adjust DDR trace
N69 VCCGT VCCGTX_BB57 BB66 So, f l oat i ng pi n of AK70, BB57, BB66 , AU58 , AU6
3
1
VCCGT VCCGTX_BB66
VCC_GT_SENSE
J70 AK62
<56> VCC_GT_SENSE VSS_GT_SENSE
J69 VCCGT_SENSE VCCGTX_SENSE AL61
<56> VSS_GT_SENSE VSSGT_SENSE VSSGTX_SENSE
1
100_0402_1%
RC163
B B
2
A A
LA-F391P
5 4 3 2 1
5 4 3 2 1
+1.2V_MEM +VCC_SFR_OC
+VCCPLL_OC source 1 2
@ RZ119 0_0402_5%
+1.2V_MEM_CPUCLK +1.2V_MEM
UZ26
@ RC231 1 2 0_0402_5% VDDQ: 8.45A 1
+1.2V_MEM 2 1 2 VIN1
CZ102 1U_0402_6.3V6K VIN2
7 6 1 2
D
PSC VIN thermal VOUT CZ103 0.1U_0201_10V6K D
3
+5V_ALW VBIAS
VCCSTG_EN
1 2 4 5
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
@ RZ120 0_0402_5% ON GND
1 1 1 1
CC176
CC177
CC178
CC179
+3.3V_ALW TPS22961DNYR_WSON8
+1.0VS_VCCIO @ CZ104
2 2 2 2 UC1N CPU@ KBL-R U4+2 1 2
Rev_0.1
5
CPU POWER 3 OF 4 0.1U_0402_10V7K
AU23 AK28 1
P
AU28 VDDQ_AU23 VCCIO AK30 <11,47,53,54,55> PCH_PRIM_EN B 4
PSC AU35 VDDQ_AU28 VCCIO AL30 2 O
VDDQ_AU35 VCCIO <11,17,35,52,55> SIO_SLP_S4# A
G
AU42 AL42
BB23 VDDQ_AU42 VCCIO AM28 @ UZ34
3
VDDQ_BB23 VCCIO
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M BB32 AM30

1 1 1 TC7SH08FU_SSOP5~D
VDDQ_BB32 VCCIO +VCC_SA
CC294
CC295
CC296 BB41 AM42

+1.2V_MEM_CPUCLK BB47 VDDQ_BB41 VCCIO
BB51 VDDQ_BB47 AK23
2 2 2 VDDQ_BB51 VCCSA AK25
PSC VCCSA G23
AM40 VCCSA G25
VDDQC VCCSA G27
A18 VCCSA G28 +1.0VS_VCCIO
10U_0402_6.3V6M
VCCST VCCSA J22

1 VCCSA
A22 J23
CC297
VCCSTG_A22 VCCSA J27
100_0402_1%
VCCSA
2
AL23 K23
2 VCCPLL_OC VCCSA K25
RC165
+1.0V_VCCST K20 VCCSA K27
K21 VCCPLL_K20 VCCSA K28 +1.0VS_VCCIO
C
PSC VCCPLL_K21 VCCSA K30 C
1
VCCSA
VCCIO_SENSE
AM23
VCCIO_SENSE AM22 VSSIO_SENSE VCCIO_SENSE <54> PSC
+1.0V_VCCSTG VSSIO_SENSE VSSIO_SENSE <54>
1
1U_0402_6.3V6K
H21
BSC VSSSA_SENSE H20
CC195
1
VCCSA_SENSE
100_0402_1%
100_0402_1%
1 1 1 1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2
RC166
RC167
CC252
CC253
CC250
CC251
+VCC_SFR_OC 1 2
1
1U_0402_6.3V6K
+VCC_SA 2 2 2 2
RC168 100_0402_1%
CC199
2
+1.0V_VCCST
2@ PSC
1 1
2.2P_0402_50V8C
1U_0402_6.3V6K
1U_0402_6.3V6K
1 VSA_SEN- <56>
CC288
RF@ CC322
VSA_SEN+ <56>
S0 S0Ix S3
CC202
2 2
2
SIO_SLP_S0# HI GH LOW LOW
SIO_SLP_S3# HI GH HI GH LOW
RF Request
AND HI GH LOW LOW
B B
+1.0V_VCCST source +1.0V_VCCSTG source

+1.0V_VCCSTG +1.0V_VCCST
1 2
@ RZ151 0_0603_5%
pop option with UZ19
1
+1.0V_PRIM
PJP2
UZ19 PAD-OPEN1x1m
+1.0V_PRIM PJP1 2 1 1
UZ21 2 1 CZ105 1U_0402_6.3V6K 2 VIN1
+1.0V_VCCST VIN2
2 1 1
+1.0V_VCCSTG_C
2
CZ100 1U_0402_6.3V6K 2 VIN1 +5V_ALW 7 6 1 2
VIN2 PAD-OPEN1x1m VIN thermal VOUT CZ106 0.1U_0201_10V6K
+5V_ALW +1.0V_VCCST_C
7 6 1 2 3
VIN thermal VOUT CZ101 0.1U_0201_10V6K VBIAS
3 +3.3V_ALW 4 5
VBIAS ON GND
4 5
<11,17,35,52,55> SIO_SLP_S4# ON GND TPS22961DNYR_WSON8
4.4mohm/6A
5
TPS22961DNYR_WSON8
1 TR=12.5us@Vin=1.05V
P
<11,37,54> SIO_SLP_S0# B VCCSTG_EN
4
4.4mohm/6A 2 O
TR=12.5us@Vin=1.05V <35,36,47,54> RUN_ON
UZ35 A G
TC7SH08FU_SSOP5~D
3
A A
@ RZ320 1 2 0_0402_5%
LA-F391P
5 4 3 2 1
5 4 3 2 1
close UC1.AL1 and <120mil

+1.0V_PRIM +1.0V_MPHYGT
+1.0V_MPHYAON +1.0V_PRIM
+1.0VO_DSW +1.0V_PRIM_CORE
close UC1.K17 and <120mil close UC1.AB19 and <400mil
PCH PWR close UC1.Y16 and <400mil
+1.0V_SRAM
+3.3V_PGPPB
1 1 1 1 close UC1.AG15 and <120mil 1 2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
+3.3V_PGPPC +3.3V_PGPPE @ RC309 0_0603_5%
@ CC205
@ CC206
close UC1.T16 and <400mil
CC203
CC204
1
1U_0402_6.3V6K
+1.0V_MPHYAON UC1O CPU@ KBL-R U4+2 +1.0V_APLLEBB
@ CC265
2 2 2 2 Rev_0.1 1 1
1U_0402_6.3V6K
1U_0402_6.3V6K
1 2 CPU POWER 4 OF 4 1 2
@ CC207
@ CC208
D @ RC299 0_0603_5% AB19 Must be +1.8V 2 @ RC310 0_0603_5% D
AB20 VCCPRIM_1P0 AK15
VCCPRIM_1P0 VCCPGPPA +3.3V_1.8V_PGPPA 2 2
+1.0V_CLK6 P18 AG15
VCCPRIM_1P0 VCCPGPPB Y16 +3.3V_1.8V_PGPPG
close UC1.AF18 and <400mil VCCPGPPC
1 2 AF18 Y15
VCCPRIM_CORE VCCPGPPD +3.3V_PGPPD
@ RC300 0_0402_5% AF19 T16 close UC1.AD15 and <400mil
V20 VCCPRIM_CORE VCCPGPPE AF16 1
1U_0402_6.3V6K
VCCPRIM_CORE VCCPGPPF +1.8V_PGPPF +3.3V_ALW_PCH
+1.0V_DTS V21 AD15
CC326
VCCPRIM_CORE VCCPGPPG +3.3V_1.8V_PGPPG
1 2 AL1 V19
@ RC301 0_0402_5% DCPDSW_1P0 VCCPRIM_3P3_V19 2
K17 T1 +1.8V_PRIM
1
1U_0402_6.3V6K
VCCMPHYAON_1P0 VCCPRIM_1P0_T1 +1.0V_DTS
+1.0V_CLK1 L1
@ CC209
VCCMPHYAON_1P0 AA1
VCCATS_1P8 close UC1.AA1 and <400mil
1 2 +1.0V_MPHYGT N15 close UC1.V19 and <120mil
@ RC302 0_0402_5% N16 VCCMPHYGT_1P0_N15 AK17 +RTC_CELL_PCH 2
1
1U_0402_6.3V6K
VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3 +3.3V_ALW_PCH
close UC1.N15 and CC210 <400mil, CC211 <120mil N17
+1.0V_CLK3 P15 VCCMPHYGT_1P0_N17 AK19
CC212
P16 VCCMPHYGT_1P0_P15 VCCRTC_AK19 BB14
VCCMPHYGT_1P0_P16 VCCRTC_BB14 close UC1.AK19 and <120mil 2
1 2 1 1 1 1
47U_0805_6.3V6M
1U_0402_6.3V6K
0.1U_0201_10V6K
1U_0402_6.3V6K
@ RC303 0_0402_5% K15 BB10 +DCPRTC
@ CC210
+1.0V_AMPHYPLL VCCAMPHYPLL_1P0 DCPRTC
L15 close UC1.BB10 and <120mil
CC211
CC270
CC213
VCCAMPHYPLL_1P0 A14 1
0.1U_0201_10V6K
2 2 VCCCLK1 +1.0V_CLK1 2 2
V15
+1.0V_APLL VCCAPLL_1P0 K19
CC214
+1.8V_PRIM VCCCLK2 +1.0V_CLK2
+1.8V_PGPPF +1.0V_PRIM AB17
Y18 VCCPRIM_1P0_AB17 L21 2
VCCPRIM_1P0_Y18 VCCCLK3 +1.0V_CLK3
1 2
@ RC304 0_0402_5% +3.3V_ALW_DSW AD17 N20 +1.0V_CLK4
AD18 VCCDSW_3P3_AD17 VCCCLK4
+3.3V_1.8V_PGPPG AJ17 VCCDSW_3P3_AD18 L19 +1.0V_CLK6
VCCDSW_3P3_AJ17 VCCCLK5 +1.0V_CLK5
C @ RC234 1 2 0_0402_5% AJ19 A10 C
+3.3V_VCCHDA VCCHDA VCCCLK6
close UC1.A10 and <120mil
+1.0V_SRAM AJ16 AN11 CORE_VID0 <54> 1
1U_0402_6.3V6K
+3.3V_ALW_PCH +3.3V_SPI VCCSPI GPP_B0/CORE_VID0 AN13
@ CC216
GPP_B1/CORE_VID1 CORE_VID1 <54>
close UC1.AF20 and <400mil AF20
1 2 AF21 VCCSRAM_1P0
@ RC235 0_0402_5% +3.3V_ALW_PCH T19 VCCSRAM_1P0 2
1
Take care!!! Note1 on Page 19
1U_0402_6.3V6K
T20 VCCSRAM_1P0
RF Request
@ CC217
+3.3V_1.8V_PGPPA +1.0V_PRIM VCCSRAM_1P0

AJ21
LPC@ RC211 1 2 0_0402_5% 2 +1.0V_APLLEBB VCCPRIM_3P3_AJ21 +1.0V_APLL +3.3V_VCCHDA +1.0V_APLLEBB
AK20
+3.3V_1.8V_ESPI VCCPRIM_1P0_AK20
+1.8V_PRIM N18
PJP4 VCCAPLLEBB_1P0
1 2 1 2 close UC1.N18 and <120mil
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
1 1 1 1
1U_0402_6.3V6K
@ESPI@ RC212 0_0402_5% KBL-RU42_BGA1356 15 OF 20

PAD-OPEN1x1m
CC218
RF@ CC323
RF@ CC324
RF@ CC325
+3.3V_ALW_PCH +3.3V_PGPPB
2 2 2 2
1 2 Must be +1.8V for eSPI I/F
@ RC305 0_0402_5% +3.3V_ALW_DSW +3.3V_ALW_PCH
+3.3V_PGPPC
1 2
1 2 NDS3@ RC440 0_0402_5% +3.3V_ALW
@ RC306 0_0402_5% +1.0V_MPHYGT +1.0V_AMPHYPLL
close UC1.K15, UC1.L15 and <100mil 1 2
+3.3V_PGPPD @ RC214 0_0402_5%
@ RC169 1 2 0_0603_5% QC7
1 2 close UC1.K15 and <120mil LP2301ALT1G_SOT23-3
@ RC307 0_0402_5% 1 1 1
1U_0402_6.3V6K
47U_0805_6.3V6M
0.1U_0201_10V6K
B +3.3V_ALW_DSW_R B
1 2 1 3
S
@ CC219
+3.3V_PGPPE @DS3@RC439 0_0402_5%

@ CC281
@ CC264
+1.0V_PRIM +1.0V_CLK5 +3.3V_ALW_PCH
499K_0402_1%
1
2 2 2
22U_0603_6.3V6M
@ CC279
22U_0603_6.3V6M
@ CC280
1 2 1 1
G
2
RC432
@ RC308 0_0402_5%
1 2
8/28 schematic review @ RC171 0_0402_5%
2 2
0.1U_0402_25V6K
close UC1.L19 and <100mil 1 1 1
1U_0402_6.3V6K
47U_0805_6.3V6M
0.1U_0201_10V6K
2
1
@
@ CC221
CC223
100K_0402_5%
CC340
LC1,LC2 need link SM01000S100(S SUPPRE_ FBMA-1H-100505-601T 0402)
CC224
2
2
+1.0V_APLL 2 2 2
49.9K_0402_1%
RC431
1
+3.3V_ALW_PCH +1.0V_PRIM
RC433
+3.3V_VCCHDA
1
LC1 1 2 BLM15GA750SN1D_2P LC2 1 2 BLM15GA750SN1D_2P
RC439RC440RE536RC215RC441RC442 close UC1.AK17 and <120mil
0.1U_0201_10V6K
0.1U_0201_10V6K
2
1 1 1 1
1U_0402_6.3V6K
47U_0805_6.3V6M
@ CC215
CC313
@ CC225
CC314
L2N7002WT1G_SC-70-3
Support DS3 V X V X V X
2 2 2 2 +1.0V_PRIM +1.0V_MPHYGT
1
D
No Support DS3 X V X V X V PJP3
QC6
2 VCCDSW_EN_GPIO <11> 1 2
G
close UC1.AJ19 and <400mil close UC1.V15 and <100mil 'V' mean POP, 'X' mean DE-POP S PAD-OPEN1x3m
3
+1.0V_MPHYGT source
561280_561280_KBL_UY_PDG_Rev0p9 :
A
MPHY has defeature A
+1.0V_PRIM +1.0V_CLK4 +1.0V_PRIM +1.0V_CLK2
1 2 1 2
@ RC173 0_0402_5% @ RC170 0_0402_5% DELL CONFIDENTIAL/PROPRIETARY
close UC1.N20 and <100mil 1 1
47U_0805_6.3V6M
47U_0805_6.3V6M

@ CC226
@ CC220
close UC1.K19 and <100mil PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
2 2
LA-F391P
5 4 3 2 1
5 4 3 2 1
Note1: VCCPRIM_CORE Implementat i on w

it h PC H C ORE_ VI D Rec o mmenda t i on
CPU@ CPU@
UC1P KBL-R U4+2 UC1Q KBL-R U4+2 CPU@ R1: PR408,PR411 ; R2: PR417,PR418 ; R3,PR419,PR420 ; R4: PR423 ; R5: PR424
Rev_0.1 Rev_0.1 UC1R KBL-R U4+2
GND 1 OF 3 GND 2 OF 3 Rev_0.1
GND 3 OF 3
A5 AL65 AT63 BA49 F8 L18
A67 VSS VSS AL66 AT68 VSS VSS BA53 G10 VSS VSS L2
A70 VSS VSS AM13 AT71 VSS VSS BA57 G22 VSS VSS L20
AA2 VSS VSS AM21 AU10 VSS VSS BA6 G43 VSS VSS L4
AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8
D AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10 D
AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13
AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19
AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21
AD13 VSS VSS AM68 AV71 VSS VSS BB43 G63 VSS VSS P17
AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10
AF1 VSS VSS AN42 AW36 VSS VSS D18 J8 VSS VSS U63
AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
C AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17 C
AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
AH64 VSS VSS AR15 AY66 VSS VSS E11
AH67 VSS VSS AR16 B10 VSS VSS E15
AJ15 VSS VSS AR20 B14 VSS VSS E18
AJ18 VSS VSS AR23 B18 VSS VSS E21 KBL-RU42_BGA1356 18 OF 20
AK11 VSS VSS AR42 B34 VSS VSS E53
AK27 VSS VSS AR5 B58 VSS VSS F1
AK8 VSS VSS AR55 BA1 VSS VSS F23
AL2 VSS VSS AR58 BA10 VSS VSS F27
AL35 VSS VSS AT2 BA2 VSS VSS F33
AL52 VSS VSS AT4 F68 VSS VSS F40
AL58 VSS VSS AT56 VSS VSS BA41
B AL64 VSS VSS AT58 VSS B
VSS VSS
KBL-RU42_BGA1356 16 OF 20 KBL-RU42_BGA1356 17 OF 20
A A
LA-F391P
5 4 3 2 1
5 4 3 2 1
For DDR4
<7> DDR_A_DQS#[0..7] +1.2V_MEM +1.2V_MEM
JDIMM1
<7> DDR_A_D[0..63]
DDR_A_D1 1 2 DDR_A_D4
<7> DDR_A_DQS[0..7] 3 VSS1 VSS2 4
5 DQ5 DQ4 6
<7> DDR_A_MA[0..16] DDR_A_D0 DDR_A_D5
7 VSS3 VSS4 8
9 DQ1 DQ0 10
DDR_A_DQS#0 VSS5 VSS6
DDR_A_DQS0 11 12
13 DQS0_c DM0_n/DBI0_n 14
DQS0_t VSS7 DDR_A_D3
15 16
Layout Note: DDR_A_D6
17 VSS8 DQ6 18 DDR_A_D7
DQ7 VSS9
D
Place near JDIMM1 DDR_A_D2 19
VSS10 DQ2
20 +1.2V_MEM
D
21 22 DDR_A_D9
23 DQ3 VSS11 24
DDR_A_D13 VSS12 DQ12
25 26 DDR_A_D8
1
DQ13 VSS13
470_0402_1%
DDR_A_D12 27 28
29 VSS14 DQ8 30
DQ9 VSS15 DDR_A_DQS#1
RD11
31 32 DDR_A_DQS1
+1.2V_MEM 33 VSS16 DQS1_c 34
35 DM1_n/DBI_n DQS1_t 36
DDR_A_D15 DDR_A_D10
2
37 VSS17 VSS18 38
39 DQ15 DQ14 40
DDR_A_D14 VSS19 VSS20 DDR_A_D11 DDR_DRAMRST#
41 42 1 2
DQ10 DQ11 <21> DDR_DRAMRST#_R DDR_DRAMRST# <7>
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
330U_D3_2.5VY_R6M
DDR_A_D35 43 44 DDR_A_D32 @ RD12 0_0402_5%
45 VSS21 VSS22 46
47 DQ21 DQ20 48
DDR_A_D37 DDR_A_D36
1
@ 49 VSS23 VSS24 50
1
1
DQ17 DQ16
CD1
CD2
CD3
CD4
CD5
CD6
CD7
CD8
CD17
+ DDR_A_DQS#4 51 52
53 VSS25 VSS26 54
DDR_A_DQS4 DQS2_c DM2_n/DBI2_n
55 56 DDR_A_D39
2
2
57 DQS2_t VSS27 58
59 60 DDR_A_D33
61 DQ23 VSS29 62 +1.2V_MEM
63 64 DDR_A_D40
65 DQ19 VSS31 66
DDR_A_D44
1
1K_0402_1%
67 VSS32 DQ28 68
DQ29 VSS33 DDR_A_D41
DDR_A_D45 69 70
VSS34 DQ24
RD15
71 72
+1.2V_MEM +2.5V_MEM DQ25 VSS35
+DDR_VREF_A_CA +DDR_VREF_CA
DDR_A_DQS#5
2
73 74 DDR_A_DQS5
75 VSS36 DQS3_c 76
DM3_n/DBI3_n DQS3_t
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_10V6M
10U_0603_10V6M
DDR_A_D42 77 78 DDR_A_D47 1 2
79 VSS37 VSS38 80 RD17 2_0402_1%
1 1 1 1
1
DQ30 DQ31
0.022U_0402_16V7K
DDR_A_D46 81 82 DDR_A_D43
VSS39 VSS40
CD9
CD10
CD11
CD12
CD13
CD14
CD15
CD16
CD18
CD19
CD20
CD21
1K_0402_1%
83 84
1
85 DQ26 DQ27 86
2
1
2 2 2 2 VSS41 VSS42
RD16
CD31
87 88
89 CB5/NC CB4/NC 90
91 VSS43 VSS44 92
2
93 CB1/NC CB0/NC 94
2
95 VSS45 VSS46 96
1
DQS8_c DM8_n/DBI_n/NC
24.9_0402_1%
97 98
DQS8_t VSS47
RD18
99 100
C VSS48 CB6/NC C
101 102
103 CB2/NC VSS49 104
105 VSS50 CB7/NC 106 DDR_DRAMRST#_R
2
107 CB3/NC VSS51 108
DDR_A_CKE0 VSS52 RESET_n DDR_A_CKE1
109 110 1
<7> DDR_A_CKE0 111 CKE0 CKE1 112 DDR_A_CKE1 <7>
DDR_A_BG1 VDD1 VDD2 DDR_A_ACT#
DDR_A_BG0 113 114 DDR_A_ALERT# CD29 @
<7> DDR_A_BG1 115 BG1 ACT_n 116 DDR_A_ACT# <7>
<7> DDR_A_BG0 BG0 ALERT_n DDR_A_ALERT# <7> 0.1U_0402_25V6
117 118 2
DDR_A_MA12 VDD3 VDD4 DDR_A_MA11
DDR_A_MA9 119 120 DDR_A_MA7
121 A12 A11 122
Layout Note: DDR_A_MA8 123 A9 A7 124 DDR_A_MA5
VDD5 VDD6
Place near DDR_A_MA6 125
A8 A5
126 DDR_A_MA4 JDIMM1_EVENT#
127 128 1 2
JDIMM1.258 DDR_A_MA3 129 A6 A4 130 DDR_A_MA2 @ RD14 1K_0402_5%
H_THERMTRIP# <12,21,36>
131 VDD7 VDD8 132
DDR_A_MA1 JDIMM1_EVENT#
133 A3 A2 134
135 A1 EVENT_n/NF 136
DDR_A_CLK0 VDD9 VDD10 DDR_A_CLK1
DDR_A_CLK#0 137 138 DDR_A_CLK#1
<7> DDR_A_CLK0 139 CK0_t CK1_t/NF 140 DDR_A_CLK1 <7>
<7> DDR_A_CLK#0 141 CK0_c CK1_c/NF 142 DDR_A_CLK#1 <7>
DDR_A_PARITY VDD11 VDD12 DDR_A_MA0
DDR_A_BA1 143 144 DDR_A_MA10
+DDR_VREF_A_CA <7> DDR_A_PARITY 145 PARITY A0 146
<7> DDR_A_BA1 147 BA1 A10/AP 148
+0.6V_DDR_VTT DDR_A_CS#0 DDR_A_BA0
149 VDD13 VDD14 150
<7> DDR_A_CS#0 DDR_A_MA14 CS0_n BA0 DDR_A_MA16 DDR_A_BA0 <7>
151 152
<7> DDR_A_MA14 WE_n/A14 RAS_n/A16
DDR_A_ODT0 153 154 DDR_A_MA15
VDD15 VDD16
0.1U_0402_10V6K
DDR_A_CS#1 155 156 DDR_A_MA13

<7> DDR_A_ODT0 ODT0 CAS_n/A15
10U_0603_10V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
2.2U_0402_6.3V6M
1 1 157 158
<7> DDR_A_CS#1 CS1_n A13
@ CD26
159 160 +DDR_VREF_A_CA

1 1 DDR_A_ODT1
1
VDD17 VDD18
CD22
CD23
CD24
CD25
161 162 T50 @ PAD~D

+DDR_VREF_A_CA
<7> DDR_A_ODT1 ODT1 C0/CS2_n/NC
163 164 DIMM1_SA2
2 2 PAD~D @ T51 165 VDD19 VREFCA 166
2
2 2 167 C1, CS3_n,NC SA2 168

DDR_A_D30 VSS53 VSS54 DDR_A_D31
169 170
171 DQ37 DQ36 172
173 174
175 DQ33 DQ32 176
DDR_A_DQS#3 VSS57 VSS58
DDR_A_DQS3 177 178
179 DQS4_c DM4_n/DBI4_n 180
DQS4_t VSS59 DDR_A_D28
DDR_A_D27 181 182
B 183 VSS60 DQ39 184 B
DDR_A_D29 185 186
187 VSS62 DQ35 188
DDR_A_D21 189 190
191 VSS64 DQ45 192 DDR_A_D16
193 DQ44 VSS65 194
195 196 DDR_A_DQS#2
197 DQ40 VSS67 198 DDR_A_DQS2
DIMM Select +3.3V_RUN +3.3V_RUN +3.3V_RUN
+3.3V_RUN
DDR_A_D19
199
201
203
VSS68
DM5_n/DBI5_n
VSS69
DQS5_c
DQS5_t
VSS70
200
202
204
DDR_A_D18
+1.2V_MEM
1
205 DQ46 DQ47 206

@ RD4 @ RD6 @ RD8 207 208 UD1
1
0_0402_5% 0_0402_5% 0_0402_5% @ 209 DQ42 DQ43 210 1 5 1 2

DDR_A_D48 VSS73 VSS74 DDR_A_D53 NC VCC
RD10 211 212 @ CD32 0.1U_0201_10V6K
213 DQ52 DQ53 214 2
0_0603_5% DDR_A_D49 DDR_A_D52 <7> DDR_VTT_CTRL
2
215 VSS75 VSS76 216 A 4

DIMM1_SA0 DQ49 DQ48 Y 0.6V_DDR_VTT_ON <52>
DIMM1_SA1 +3.3V_RUN_DIMM1 DDR_A_DQS#6 217 218 3
2
219 VSS77 VSS78 220 GND 1 2

DIMM1_SA2 DDR_A_DQS6 DQS6_c DM6_n/DBI6_n +3.3V_RUN
0.1U_0201_10V6K
SA0 SA1 SA2 221 222 DDR_A_D54 74AUP1G07GW_TSSOP5 RD19 100K_0402_5%

DQS6_t VSS79
2.2U_0402_6.3V6M
1 1 DDR_A_D50 223 224

1
VSS80 DQ54
CD28
@ @ @ 225 226
DIMM1 0 0 0 DQ55 VSS81 DDR_A_D55
CD27
RD5 RD7 RD9 DDR_A_D51 227 228

DIMM2 1 0 0 0_0402_5% 0_0402_5% 0_0402_5%
2 2
DDR_A_D56
229
231
233
VSS82
DQ51
VSS84
DQ50
VSS83
DQ60
230
232
234
DDR_A_D61 6/8 Change to SA00007WE00 DII
DIMM3 0 1 0 DDR_A_D60
2
235 DQ61 VSS85 236

DIMM4 1 1 0 237 238 DDR_A_DQS#7
239 DQ56 VSS87 240
VSS88 DQS7_c DDR_A_DQS7
241 242
243 DM7_n/DBI7_n DQS7_t 244
245 246
247 DQ62 DQ63 248
249 250
251 DQ58 DQ59 252
253 VSS93 VSS94 254
<8,14,21,41> DDR_XDP_WAN_SMBCLK +3.3V_RUN_DIMM1 SCL SDA DIMM1_SA0 DDR_XDP_WAN_SMBDAT <8,14,21,41>
255 256
257 VDDSPD SA0 258
+2.5V_MEM DIMM1_SA1 +0.6V_DDR_VTT
259 VPP1 VTT 260
261 VPP2 SA1 262
GND1 GND2
A A
LCN_DAN05-Q0406-0103
CONN@
LINK DAN05-Q0406-0103 DONE
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Titl e
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDR4
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
LA-F391P
D a te : Tuesday, September 19, 2017 She e t 20 of 70
5 4 3 2 1
5 4 3 2 1
For DDR4
<7> DDR_B_DQS#[0..7]
+1.2V_MEM +1.2V_MEM
<7> DDR_B_D[0..63]
JDIMM2
<7> DDR_B_DQS[0..7] 1 2
DDR_B_D1 VSS1 VSS2 DDR_B_D5
3 4
<7> DDR_B_MA[0..16] DQ5 DQ4
DDR_B_D4 5 6 DDR_B_D0
7 VSS3 VSS4 8
9 DQ1 DQ0 10
DDR_B_DQS#0
11 VSS5 VSS6 12
DDR_B_DQS0 DQS0_c DM0_n/DBI0_n
13 14 DDR_B_D2
15 DQS0_t VSS7 16
DDR_B_D7
17 VSS8 DQ6 18
DQ7 VSS9 DDR_B_D3
19 20
Layout Note: DDR_B_D6
21 VSS10 DQ2 22 DDR_B_D9
DQ3 VSS11
D
Place near JDIMM2 DDR_B_D13 23
VSS12 DQ12
24
D
25 26 DDR_B_D8
27 DQ13 VSS13 28
DDR_B_D12 VSS14 DQ8
29 30 DDR_B_DQS#1
31 DQ9 VSS15 32 DDR_B_DQS1
33 VSS16 DQS1_c 34
35 DM1_n/DBI_n DQS1_t 36
37 38
+1.2V_MEM 39 DQ15 DQ14 40
41 42
43 DQ10 DQ11 44
45 46
DQ21 DQ20
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
330U_D3_2.5VY_R6M
DDR_B_D36 47 48 DDR_B_D32
49 VSS23 VSS24 50
51 DQ17 DQ16 52
DDR_B_DQS#4
1
@ 53 VSS25 VSS26 54
DDR_B_DQS4
1
1
DQS2_c DM2_n/DBI2_n
CD33
CD34
CD35
CD36
CD37
CD38
CD39
CD40
CD49
+ 55 56 DDR_B_D34
57 DQS2_t VSS27 58
DDR_B_D39 VSS28 DQ22
59 60 DDR_B_D35
2
2
61 DQ23 VSS29 62
63 64 DDR_B_D40
65 DQ19 VSS31 66
67 68 DDR_B_D41
69 DQ29 VSS33 70
71 72
DQ25 VSS35
+1.2V_MEM +2.5V_MEM
DDR_B_DQS#5
73 74 DDR_B_DQS5
75 VSS36 DQS3_c 76
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_10V6M
10U_0603_10V6M
79 80
81 DQ30 DQ31 82
1 1 1 1 DDR_B_D45 DDR_B_D47
1
83 VSS39 VSS40 84
DQ26 DQ27
CD41
CD42
CD43
CD44
CD45
CD46
CD47
CD48
CD50
CD51
CD52
CD53
85 86 JDIMM2_EVENT#
87 VSS41 VSS42 88 1 2
H_THERMTRIP# <12,20,36>
2
2 2 2 2 89 CB5/NC CB4/NC 90 @ RD27 1K_0402_5%

91 VSS43 VSS44 92
93 CB1/NC CB0/NC 94
95 VSS45 VSS46 96
97 DQS8_c DM8_n/DBI_n/NC 98
99 DQS8_t VSS47 100
101 VSS48 CB6/NC 102
103 CB2/NC VSS49 104
C VSS50 CB7/NC C
105 106 DDR_DRAMRST#_R
107 CB3/NC VSS51 108
DDR_B_CKE0 DDR_B_CKE1 DDR_DRAMRST#_R <20>
109 VSS52 RESET_n 110
<7> DDR_B_CKE0 111 CKE0 CKE1 112 DDR_B_CKE1 <7>
DDR_B_BG1 VDD1 VDD2 DDR_B_ACT#
DDR_B_BG0 113 114 DDR_B_ALERT# 1
<7> DDR_B_BG1 115 BG1 ACT_n 116 DDR_B_ACT# <7>
<7> DDR_B_BG0 117 BG0 ALERT_n 118 DDR_B_ALERT# <7>
DDR_B_MA12 DDR_B_MA11 @ CD61
119 VDD3 VDD4 120
DDR_B_MA9 A12 A11 DDR_B_MA7 0.1U_0402_25V6
121 122 2
123 A9 A7 124
DDR_B_MA8 VDD5 VDD6 DDR_B_MA5
DDR_B_MA6 125 126 DDR_B_MA4
127 A8 A5 128
129 A6 A4 130
DDR_B_MA3 VDD7 VDD8 DDR_B_MA2
DDR_B_MA1 131 132 JDIMM2_EVENT#
133 A3 A2 134
135 A1 EVENT_n/NF 136
DDR_B_CLK0 DDR_B_CLK1
137 VDD9 VDD10 138
<7> DDR_B_CLK0 DDR_B_CLK#0 CK0_t CK1_t/NF DDR_B_CLK#1 DDR_B_CLK1 <7>
139 140
<7> DDR_B_CLK#0 141 CK0_c CK1_c/NF 142 DDR_B_CLK#1 <7>
Layout Note: DDR_B_PARITY
DDR_B_BA1 143 VDD11 VDD12 144
DDR_B_MA0
DDR_B_MA10
<7> DDR_B_PARITY PARITY A0
Place near <7> DDR_B_BA1
145
BA1 A10/AP
146
147 148
JDIMM2.258 DDR_B_CS#0
DDR_B_MA14 149 VDD13 VDD14 150
DDR_B_BA0
DDR_B_MA16
<7> DDR_B_CS#0 CS0_n BA0 DDR_B_BA0 <7>
151 152
<7> DDR_B_MA14 153 WE_n/A14 RAS_n/A16 154
DDR_B_ODT0 VDD15 VDD16 DDR_B_MA15
DDR_B_CS#1 155 156 DDR_B_MA13
<7> DDR_B_ODT0 ODT0 CAS_n/A15
157 158
<7> DDR_B_CS#1 159 CS1_n A13 160 +DDR_VREF_B_CA
DDR_B_ODT1 VDD17 VDD18
161 162 T54 @ PAD~D
+DDR_VREF_B_CA
<7> DDR_B_ODT1 163 ODT1 C0/CS2_n/NC 164
+0.6V_DDR_VTT DIMM2_SA2
PAD~D @ T55 165 VDD19 VREFCA 166 +1.2V_MEM
+DDR_VREF_B_CA 167 C1, CS3_n,NC SA2 168
DDR_B_D21 DDR_B_D16
1
VSS53 VSS54
1K_0402_1%
169 170
171 DQ37 DQ36 172
10U_0603_10V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
173 174
RD28
175 DQ33 DQ32 176
1 1 DDR_B_DQS#2
1
VSS57 VSS58
CD54
CD55
CD56
0.1U_0402_10V6K
2.2U_0402_6.3V6M
DDR_B_DQS2 177 178 +DDR_VREF_B_CA +DDR_VREF_B_DQ
2
DQS4_c DM4_n/DBI4_n
@ CD58
1 1 179 180 DDR_B_D18

DQS4_t VSS59
CD57
DDR_B_D23 181 182

2
2 2 183 VSS60 DQ39 184 1 2

DQ38 VSS61 DDR_B_D19
DDR_B_D22 185 186 RD30 2_0402_1%
2 2 VSS62 DQ35
0.022U_0402_16V7K
B 187 188 DDR_B_D28 B
DQ34 VSS63
1K_0402_1%
DDR_B_D24 189 190
1
191 VSS64 DQ45 192 DDR_B_D29
1
DQ44 VSS65
RD29
CD62
DDR_B_D25 193 194
195 VSS66 DQ41 196 DDR_B_DQS#3
197 DQ40 VSS67 198 DDR_B_DQS3
2
199 VSS68 DQS5_c 200
2
DDR_B_D26 DDR_B_D31
VSS69 VSS70
24.9_0402_1%
203 204
1
205 DQ46 DQ47 206
RD31
+3.3V_RUN 207 208
209 DQ42 DQ43 210
DDR_B_D52 DDR_B_D53
DIMM Select +3.3V_RUN +3.3V_RUN +3.3V_RUN 211 VSS73 VSS74 212
1
@ 213 DQ52 DQ53 214

DDR_B_D49 DDR_B_D48
2
RD26 215 VSS75 VSS76 216
1
@ 217 DQ49 DQ48 218

0_0603_5% DDR_B_DQS#6
@ RD20 RD22 @ RD24 219 VSS77 VSS78 220
DDR_B_DQS6 DQS6_c DM6_n/DBI6_n
0_0402_5% 0_0402_5% 0_0402_5% +3.3V_RUN_DIMM2 221 222 DDR_B_D50
2
223 DQS6_t VSS79 224

225 226 DDR_B_D51
2
227 DQ55 VSS81 228

DIMM2_SA0 DDR_B_D54 VSS82 DQ50
2.2U_0402_6.3V6M
0.1U_0201_10V6K
DIMM2_SA1 1 229 230 DDR_B_D61

1
231 DQ51 VSS83 232

DIMM2_SA2 DDR_B_D56 VSS84 DQ60
CD59
CD60
233 234
SA0 SA1 SA2 235 DQ61 VSS85 236
DDR_B_D60
DDR_B_D57
2
1
@ @ 2 237 VSS86 DQ57 238

DIMM1 0 0 0 239 DQ56 VSS87 240
DDR_B_DQS#7
RD21 @ RD23 RD25 DDR_B_DQS7
0_0402_5% 241 VSS88 DQS7_c 242
DIMM2 1 0 0 0_0402_5% 0_0402_5%
DIMM3 0 1 0 245 246
*
2
247 DQ62 DQ63 248

249 250
DIMM4 1 1 0 251 DQ58 DQ59 252
253 VSS93 VSS94 254
<8,14,20,41> DDR_XDP_WAN_SMBCLK +3.3V_RUN_DIMM2 SCL SDA DIMM2_SA0 DDR_XDP_WAN_SMBDAT <8,14,20,41>
255 256
257 VDDSPD SA0 258
+2.5V_MEM VPP1 VTT DIMM2_SA1 +0.6V_DDR_VTT
259 260
261 VPP2 SA1 262
GND1 GND2
A LCN_DAN05-Q0406-0103 A
CONN@
LINK DAN05-Q0406-0103 DONE
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDR4
LA-F391P
5 4 3 2 1
A B C D E
+3.3V_RUN
For Breckenridge 12/14/15
SW2_DP1_AUXN
2 1
RV70 100K_0402_5%
SW2_DP3_AUXN
2 1
RV72 100K_0402_5%
1
+3.3V_RUN
Priority: Type-C -> VGA 1
CV62 CV61 close to pin30 &57
2 1 SW2_DP1_CADET CV66,CV69,CV70 close to pin5,21,51
RV73 1M_0402_5%
SW2_DP3_CADET
0.01UF_0402_25V7K
0.01UF_0402_25V7K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
2 1
RV75 1M_0402_5% 1 1 1
SW2_DP1_AUXP
CV83
CV84
CV85
2 1 UV7
CV81
CV82
RV76 100K_0402_5%
SW2_DP3_AUXP
2 1 5
2
RV78 100K_0402_5% 2 2 2 21 VDD33 50
30 VDD33 OUT1_D0p 49 SW2_DP1_P0 <25>
51 VDD33 OUT1_D0n SW2_DP1_N0 <25>
57 VDD33 47
VDD33 OUT1_D1p 46 SW2_DP1_P1 <25>
OUT1_D1n SW2_DP1_N1 <25>
CV86 1 2 0.1U_0201_10V6K CPU_DP2_P0_C 6 45 -----> TYPE C
<6> CPU_DP2_P0 1 2 0.1U_0201_10V6K CPU_DP2_N0_C 7 IN_D0p OUT1_D2p 44 SW2_DP1_P2 <25>
CV87
+3.3V_RUN <6> CPU_DP2_N0 IN_D0n OUT1_D2n SW2_DP1_N2 <25>
1 2 0.1U_0201_10V6K CPU_DP2_P1_C 9 42
CV88
<6> CPU_DP2_P1 1 2 0.1U_0201_10V6K CPU_DP2_N1_C 10 IN_D1p OUT1_D3p 41 SW2_DP1_P3 <25>
CV89
<6> CPU_DP2_N1 IN_D1n OUT1_D3n SW2_DP1_N3 <25>
1 2 0.1U_0201_10V6K CPU_DP2_P2_C
CV90 12
<6> CPU_DP2_P2 CPU_DP2_N2_C 13 IN_D2p
CV91 1 2 0.1U_0201_10V6K 40
<6> CPU_DP2_N2 IN_D2n OUT2_D0p SW2_DP3_P0 <24>
2
2
39
RV79 @
RV83 @
RV91 @
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
@ @ @
CPU_DP2_P3_C 15 OUT2_D0n SW2_DP3_N0 <24>
CV92 1 2 0.1U_0201_10V6K
RV89
<6> CPU_DP2_P3 CPU_DP2_N3_C 16 IN_D3p

RV81
RV85
RV87
RV93
RV95
CV93 1 2 0.1U_0201_10V6K 37
<6> CPU_DP2_N3 IN_D3n OUT2_D1p 36 SW2_DP3_P1 <24>
OUT2_D1n SW2_DP3_N1 <24>
-----> VGA
1
1 35
2 4 OUT2_D2p 34 2
SW2_PS8338_P0 @ T204 PAD~D IN_CA_DET OUT2_D2n
3
<6> CPU_DP2_HPD 2 IN_HPD 32
SW2_PS8338_P1 @ T223 PAD~D
SW2_PS8338_P1 I2C_CTL_EN OUT2_D3p
1 31
SW2_PS8338_P0 60 Pl1/SCL_CTL OUT2_D3n
SW2_PS8338_SW Pl0/SDA_CTL
for support TMDS signal need contact SCL/SDA to P22,23 26
SW2_PS8338_PEQ OUT1_AUXp_SCL SW2_DP1_AUXP <25,26>
22 27
<6> CPU_DP2_CTRL_CLK 23 IN_DDC_SCL OUT1_AUXn_SDA SW2_DP1_AUXN <25,26>
SW2_PS8338_CFG0 <6> CPU_DP2_CTRL_DATA 1 2 0.1U_0201_10V6K CPU_DP2_AUXP_C 24 IN_DDC_SDA 28
CV94
<6> CPU_DP2_AUXP 1 2 0.1U_0201_10V6K CPU_DP2_AUXN_C 25 IN_AUXp OUT2_AUXp_SCL 29 SW2_DP3_AUXP <24>
CV95
SW2_PS8338_PC10 <6> CPU_DP2_AUXN IN_AUXn OUT2_AUXn_SDA SW2_DP3_AUXN <24>
SW2_PS8338_CFG0 SW2_DP1_CADET
59 43
SW2_PS8338_PC11 58 CFG0 OUT1_CA_DET 48
SW2_PS8338_PC10 56 CFG1 OUT1_HPD SW2_DP1_HPD <25,26>
SW2_PS8338_PC20 SW2_PS8338_PC11 55 PC10 33 SW2_DP3_CADET
SW2_PS8338_PC20 PC11 OUT2_CA_DET
54 38
SW2_PS8338_PC21 SW2_PS8338_PC21 PC20 OUT2_HPD SW2_DP3_HPD <24>
53
PC21 18 SW2_PS8338_SW
11 SW 8 SW2_PS8338_PEQ
19 GND PEQ 14 PAD~D @ T224
52 GND PD 17
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
GND CEXT
1
61 20
PAD(GND) REXT
2.2U_0402_6.3V6M
@ RV80
@ RV82
@ RV84
@ RV86
RV88
RV90
@ RV92
RV94
RV96
1
PS8338BQFN60GTR-A0_QFN60_5X9
4.99K_0402_1%
1
RV97
CV96
@ @ @
2
2
2
3 3
Port switching control or priority configuration. Internal pull down ~150KΩ ,

3.3V I/O
For Control Switching Mode (CFG0 = L):
SW = L: Port1 is selected (default)
SW = H: Port2 is selected
For Automatic Switching Mode (CFG0 = H):
SW = L: Port1 has higher priority when both ports are plugged
SW = H: Port2 has higher priority when both ports are plugged (default)
vender sugguest MUX use LLEQ PEQ=M and PI0=H !!
Programmable input equalization levels, Internal pull down at ~150Kohm,3.3V I/O

PEQ =
L: default,LEQ, compensate channel loss up to 11.5dB @HBR2
H: HEQ, compensate channel loss up to 14.5dB @HBR2
M:LLEQ, compensate channel loss up to 8.5dB @HBR2
PI0:Automatic EQ disable, Internal pull down ~150K ohm, 3.3V I/O

4 4
PI0 = L: Automatic EQ enable(default)
H: Automatic EQ disable
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DP SW2 PS8348B
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Re v
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.2
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-F391P
Date : Tuesday, September 19, 2017 Sheet 22 of 70
A B C D E
5 4 3 +5V_RUN 2 1
For 1.65G HDMI from CPU
0.1U_0201_10V6K
1
1
CV39
+VHDMI_VCC
2
IN
AP2330W-7_SC59-3
UV2
0.1U_0201_10V6K
10U_0603_10V6M
1
CV41
EMI@ RV24 1 2 5.6_0402_5%
GND
OUT
HDMI_L_TX_P2
@
HCM1012GH900BP_4P
CV40
D HDMI_TX_P2
D
2
2
1 2 2 3 EMI@ 2
<6> CPU_DP1_P0
3
CV31 0.1U_0402_25V6 2 3 RV26
<6> CPU_DP1_N0
CV32
1 2
0.1U_0402_25V6
HDMI_TX_N2
1
1 4
4
200_0402_5%
HDMI connector
HDMI_L_TX_N2
1
@EMI@ LV3
1 2
EMI@ RV25 5.6_0402_5% HDMI_HPD JHDMI1 CONN@
19
EMI@ 1 2 5.6_0402_5% 18 HP_DET
RV27 HDMI_L_TX_P1
17 +5V
HCM1012GH900BP_4P +3.3V_RUN HDMI_CTRL_DATA DDC/CEC_GND
16
HDMI_TX_P1 HDMI_CTRL_CLK SDA
2
1 2 2 3 EMI@ 15
<6> CPU_DP1_P1 2 3 14 SCL 23
CV33 0.1U_0402_25V6 RV29 HDMI_CEC
2 1 13 Utility GND4 22
HDMI_TX_N1 200_0402_5% HDMI_L_CLKN CEC GND3
1 2 1 4 10K_0402_5% @ RV19 12 21
<6> CPU_DP1_N1 1 4 CK- GND2
CV34 0.1U_0402_25V6 11 20
HDMI_L_TX_N1 HDMI_L_CLKP
1
@EMI@ LV6 10 CK_shield GND1
HDMI_L_TX_N0 CK+
1 2 9
EMI@ 5.6_0402_5% 8 D0-
RV28 HDMI_L_TX_P0
7 D0_shield
HDMI_L_TX_N1 D0+
EMI@ RV30 1 2 5.6_0402_5% 6
HDMI_L_TX_P0 D1-
5
HCM1012GH900BP_4P HDMI_L_TX_P1 D1_shield
4
HDMI_TX_P0 HDMI_L_TX_N2 D1+
2
1 2 2 3 EMI@ 3
<6> CPU_DP1_P2 2 3 D2-
CV35 0.1U_0402_25V6 RV32 2
HDMI_L_TX_P2 D2_shield
200_0402_5% 1
HDMI_TX_N0 D2+
1 2 1 4
<6> CPU_DP1_N2 1 4
CV36 0.1U_0402_25V6 HDMI_L_TX_N0 LOTES_AHDM0046-P002A
1
@EMI@ LV9
1 2
EMI@ RV31 5.6_0402_5%
EMI@ LINK AHDM0046-P002A DONE
RV33 1 2 5.6_0402_5%
HDMI_L_CLKP
HDMI_TX_P2 HDMI_OB
C HDMI_CLKP
HCM1012GH900BP_4P
HDMI_TX_N2
RV10 1 2 470_0402_1%
C
2
2 1 2 3 EMI@ RV11 1 2 470_0402_1%
<6> CPU_DP1_P3 2 3 HDMI_TX_P1
0.1U_0402_25V6 RV35 RV12 1 2 470_0402_1%
HDMI_TX_N1
CV37 200_0402_5% RV13 1 2 470_0402_1%
HDMI_CLKN HDMI_TX_P0
2 1 1 4 RV14 1 2 470_0402_1%
<6> CPU_DP1_N3 1 4 HDMI_TX_N0
CV38 0.1U_0402_25V6 RV15 1 2 470_0402_1%
HDMI_L_CLKN HDMI_CLKP
1
@EMI@ LV12 RV16 1 2 470_0402_1%
HDMI_CLKN
RV17 1 2 470_0402_1%
1 2
EMI@ RV34 5.6_0402_5%
1
D
+3.3V_RUN RV18 1 2 10K_0402_5% 2 QV4

G L2N7002WT1G_SC-70-3
S
3
+3.3V_RUN
1M_0402_5%
2
RV20
2
G
1
HDMI_HPD
3 1 1 2
<6> CPU_DP1_HPD RV21 20K_0402_5%
S
QV5
L2N7002WT1G_SC-70-3
B B
+3.3V_RUN
QV3A +VHDMI_VCC
2
DMN65D8LDW-7_SOT363-6
HDMI_CTRL_CLK
1 6 1 2
<6> CPU_DP1_CTRL_CLK
RV22 2.2K_0402_5%
5
HDMI_CTRL_DATA
4 3 1 2
<6> CPU_DP1_CTRL_DATA
RV23 2.2K_0402_5%
QV3B
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, HDMI CONN
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
0.2
5 4 3 2 1
5 4 3 2 1
For Breckenridge 12/14/15

For Realtek Solution
+3.3V_RUN +3.3V_RUN Place near UV6.4 Place near UV6.25 Place near UV6.26
+3.3V_RUN
+VCCK_12
60ohm/1A UV6 60ohm/1A
+3.3V_RUN +3.3V_VGA +VDD_DAC_33
0.1U_0402_25V6
0.1U_0402_25V6
2.2U_0402_16V6K
1 2 1 20 2 1 1 1 1
+VCCK_12 AVC33 VDD_DAC_33
0.1U_0402_25V6
CV103
CV104
CV105
0.1U_0402_25V6
LV14 BLM15PX600SN1D_2P 4 BLM15PX600SN1D_2P LV30 1
AVCC_12 +VCCK_12
D 14 25 1
D
VCC_33 VCCK_12
CV100
CV106
SW2_DP3_AUXP_C 2 2 2
2 1 ISPSCL 0.1U_0402_10V7K 1 2 CV111 2 26
<22> SW2_DP3_AUXP SW2_DP3_AUXN_C AUX_P PVCC_33 +3.3V_RUN 2
@ RV106 4.7K_0402_5% 0.1U_0402_10V7K 1 2 CV112 3 +CRT_VCC
2 1 ISPSDA <22> SW2_DP3_AUXN AUX_N 2
SW2_DP3_P0_C
@ RV107 4.7K_0402_5% 0.1U_0402_10V7K 1 2 CV107 5 17
<22> SW2_DP3_P0 SW2_DP3_N0_C LANE0_P HVSYNC_PWR 18 VSYNC_CRT
0.1U_0402_10V7K 1 2 CV108 6
<22> SW2_DP3_N0 SW2_DP3_P1_C LANE0_N VSYNC 19 HSYNC_CRT
0.1U_0402_25V6
4.7U_0402_6.3V6M
0.1U_0402_10V7K 1 2 CV109 7
<22> SW2_DP3_P1 SW2_DP3_N1_C LANE1_P HSYNC
0.1U_0402_10V7K 1 2 CV110 8 1 1
SW2_DP3_HPD <22> SW2_DP3_N1 LANE1_N
CV101
CV102
2 1
BLUE_CRT
RV102 100K_0402_5%
+3.3V_RUN
RV123
RV124
1
1
2 4.7K_0402_5%
2 4.7K_0402_5%
10
9 POL1/SPI_CEB
POL2
RTD2166 BLUE_P
21
22
GREEN_CRT 2 2
RV620 1 2 4.7K_0402_5% 11 GREEN_P
+3.3V_RUN GPI1/SPI_CLK RED_CRT
RV622 1 2 4.7K_0402_5% 12 23
+3.3V_RUN GPI2/SPI_SI RED_P
13
GPI3/SPI_SO
CLK_DDC2_CRT
15
DAT_DDC2_CRT VGA_SCL
16
VGA_SDA 27
ISPSCL 30 LDO_RSTB 28
ISPSDA 29 SMB_SCL EXT_CLK_IN 31
SMB_SDA EXT1.2V_CTRL
SW2_DP3_HPD
32 24
<22> SW2_DP3_HPD HPD GND 33
EPAD_GND
RTD2166-CG_QFN32_4X4
C C
Operation Mode Table

POL1(P10)
0 1
0 X X
POL2
(P9) 1 ROM EEPROM +5V_RUN
3
PJDLC05C_SOT23-3
PJDLC05C_SOT23-3
@ESD@ DV5
@ESD@ DV6
1
UV4
IN
AP2330W-7_SC59-3
GND
OUT
RED_CRT
1 2
EMI@ LV16 BLM15BB470SN1D_2P
GREEN_CRT
3
B 1 2 +CRT_VCC B
BLUE_CRT
1 2
40mils
12P_0402_50V8J
12P_0402_50V8J
12P_0402_50V8J
1
3.3P_0402_50V8C
3.3P_0402_50V8C
3.3P_0402_50V8C
1
1
75_0402_1%
75_0402_1%
75_0402_1%
1 1 1
1 1 1 CV134
1U_0402_6.3V6K
RV116
RV117
RV118
CV129
CV130
CV131
2 JCRT1
2 2 2 @ @ @ 6
CV126
CV127
CV128
2
2
2 2 2 @ T87 PAD~D JCRT-11 11
RED 1
7
12
+CRT_VCC GREEN 2
8
HSYNC_CONN
13
BLUE 3
9
VSYNC_CONN
2
14
2.2K_0402_5%
2.2K_0402_5%
M_ID2#
1K_0402_5%
1K_0402_5%
4 G 16
RV119
RV120
RV121
RV122
10 G 17
15
5
DAT_DDC2_CRT
1
1
@ @
0.1U_0402_16V4Z
CLK_DDC2_CRT 1 CCM_C070546HR015M29CZR
CV135
CONN@
HSYNC_CRT
2 1
2
L
i
n
k
C
0
7
0
5
4
6
H
R
0
1
5
M
2
9
C
Z
R
d
o
n
e
EMI@ RV650 75_0402_1%
VSYNC_CRT
1 2
EMI@ RV651 75_0402_1%
A 2P_0402_50V8C~D A
2P_0402_50V8C~D
1 1
CV132
CV133
2 2 DELL CONFIDENTIAL/PROPRIETARY
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DP to VGA & VGA Conn
LA-F391P
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN_UT9 +3.3V_CPS 8743@ UT9

For NON-AR port1
1 2
LT11 BLM15PX600SN1D_2P
10U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
TUSB546: Pop RT246,Depop CT122 PS8743BQFN40GTR-B1_QFN40_4X6 TUSB546: Pop RT300,Depop RT145,RT301
1 1 1 1 PS8740: Depop RT246,Pop CT122 SA00009E910 PS8743:Depop RT301,Pop RT145,RT300(change to 0.1uf)(VDD_DCI)
CT118
CT119
CT120
CT121
PS8743: Depop RT246,Pop CT122(CEXT)
+3.3V_RUN_UT9
CT117
8743@ 2 1 8743@ RT145
2.2U_0402_6.3V6M CT122 TUSB546: Pop RT69,RT90,Depop RT417,RT418
2
2 2 2 2 PS8743: Depop RT69,RT90,Pop RT417,RT418
UT9 546@ (EQ1=CE_USB,EQ0=FLIP)
+3.3V_CPS_R1 MUX1_USB_EQ1
2
1K_0402_5%
@ RT145
D 546@ 1 2 1 35 D
VCC EQ1 MUX1_USB_EQ0 MUX1_USB_EQ1 <26>
RT246 0_0402_5% 6 38
+3.3V_RUN_UT9 20 VCC EQ0 MUX1_USB_EQ0 <26>
+3.3V_RUN 0_0402_5%
VCC MUX1_I2C_EN
28 17 SD028000080
VCC I2C_EN
MUX1_DPEQ1
1
2 (VDD_DCI)
1 2 SW2_DP1_P0_C DPEQ1 14 MUX1_DPEQ0 MUX1_I2C_EN
1 2 9
<22> SW2_DP1_P0 SW2_DP1_N0_C DP0p DPEQ0/A1
@ RT397 0_0603_5% CT103 1 2 0.1U_0402_25V6 10
<22> SW2_DP1_N0 DP0n MUX1_SSEQ1
546@RT300
8743@ CT213
20K_0402_5%
CT104 0.1U_0402_25V6 3
SW2_DP1_P1_C MUX1_SSEQ0
1K_0402_5%
1
1
SSEQ1 11
@ RT301
0.1U_0402_25V6
1 2 12
<22> SW2_DP1_P1 SW2_DP1_N1_C DP1p SSEQ0/A0
1
+3.3V_VDD_PIC CT105 1 2 0.1U_0402_25V6 13
<22> SW2_DP1_N1 DP1n
CT106 0.1U_0402_25V6
SW2_DP1_P2_C MUX1_FLIP_SEL
1 2 15 21
1 2 <22> SW2_DP1_P2 SW2_DP1_N2_C MUX1_FLIP_SEL <26>
2
CT107 1 2 0.1U_0402_25V6 16 DP2p FLIP/SCL
<22> SW2_DP1_N2 MUX1_USB_SEL
2
0_0603_5% @ RT398 CT108 0.1U_0402_25V6 DP2n 22
SW2_DP1_P3_C CTL0/SDA MUX1_USB_SEL <26>
1 2 18
<22> SW2_DP1_P3 SW2_DP1_N3_C DP3p MUX1_DP_SEL
CT109 1 2 0.1U_0402_25V6 19 23
<22> SW2_DP1_N3 DP3n CTL1 MUX1_DP_SEL <26>
CT110 0.1U_0402_25V6
31 34 I2C Programming or Pin Strap Programming Select,Internally

<28> TBTA_RX1N 30 RX1n TX1n 33 TBTA_TX1N <28> 30k pull-up and 60k pull-down
<28> TBTA_RX1P RX1p TX1p TBTA_TX1P <28> I2C_EN =
+3.3V_RUN_UT9 39 37 0: Tie 1k to GND,Pin Strap(I2C disable)
<28> TBTA_RX2N 40 RX2n TX2p 36 TBTA_TX2P <28> R:Tie 20k to GND,TI Test Mode(I2C enabled)
<28> TBTA_RX2P RX2p TX2n TBTA_TX2N <28> F: Float,TI Test Mode(I2C enabled)
1:Tie 1k to VCC,I2C enabled
USB3_PTX_C_DRX_P1 USB3_PRX_C_DTX_P1
2
1 2 8 5 2 1
<10> USB3_PTX_DRX_P1 USB3_PTX_C_DRX_N1 SSTXp SSRXp 4 USB3_PRX_C_DTX_N1 USB3_PRX_DTX_P1 <10>
546@ CT113 1 2 0.1U_0402_25V6 7 CT111 2 1 0.1U_0402_25V6
<10> USB3_PTX_DRX_N1 SSTXn SSRXn USB3_PRX_DTX_N1 <10>
RT308 CT114 0.1U_0402_25V6 CT112 0.1U_0402_25V6
4.7K_0402_5% AUX1_SNOOP_EN# TUSB546A_SBU1_R
TUSB546:(AUX1_SNOOP_EN#) 29 27 1 2
AUX1_SNOOP_EN# TUSB546A_SBU2_R TBTA_SBU1 <26,28>
1
Pop RT308, Depop RT416 1 2 32 SNK_CAD/DCI_DAT SBU1 26 8743@ RT132 1 2 0_0402_5% 8743@ RT414
<22,26> SW2_DP1_HPD HPDIN/DCI_CLK SBU2 TBTA_SBU2 <26,28> TUSB546A_SBU1_R
C PS8743:(I2C_EN) @ RT380 0_0402_5% 8743@ RT133 0_0402_5% 1 2 2M_0402_5% C
Pin Control mode Depop RT308,Pop RT416 SW2_DP1_AUXP_C
for pin control , connect to PD GPIO 24 2 1
AUXp 25 SW2_DP1_AUXN_C SW2_DP1_AUXP <22,26>
1
8743@ I2C mode Pop RT308,Depop RT416 Check I2C or Pin control 41 8743@ CT115 2 1 0.1U_0402_25V6 8743@ RT415
PAD AUXn SW2_DP1_AUXN <22,26> TUSB546A_SBU2_R
RT416 8743@ CT116 0.1U_0402_25V6 1 2 2M_0402_5%
4.7K_0402_5% TUSB546A_QFN40_4X6
2
+3.3V_RUN_UT9
+3.3V_RUN_UT9 +3.3V_RUN_UT9
SW2_DP1_AUXN_C
1 2
1
4.7K_0402_5%
4.7K_0402_5%
@ RT412
@ RT411
100K_0402_5% RT131
+3.3V_RUN_UT9
+3.3V_RUN_UT9 +3.3V_RUN_UT9 SW2_DP1_AUXP_C
@ RT137 1 2
(CEQ) (DPEQ) 100K_0402_5% RT130
MUX1_USB_SEL MUX1_FLIP_SEL
2
2
1K_0402_5%
@ RT143
2
1
1K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
1K_0402_5%
@ RT137
@ RT247
@ RT413
@ RT410
4.7K_0402_5%
SD028470180
1
MUX1_USB_EQ0
1
2
(SSDE/DCI_DATA) (REXT)
MUX1_SSEQ0 MUX1_DPEQ1
546@ RT144
546@ RT138
546@ RT248
20K_0402_5%
8743@ RT248 PS8743B Pin Control Mode PS8743B Pin Control Mode
1
1K_0402_5%
@ RT304
20K_0402_5%
20K_0402_5%
USB Type-C connector facing RX channel receiver DP Receiver equalization setting;

1
1
1K_0402_5%
1K_0402_5%
@ RT302
@ RT303
PS8743B Pin Control Mode equalization setting;Internally tied to VDD33/2, 3.3V I/O. Internal tied to VDD33/2, 3.3V I/O.
USB HOST facing TX channel CEQ = DPEQ =
De-emphasis setting. Internally pull down at 150k. L: Compensation for channel loss up to 7dB L: Compensation for channel loss up to 7dB
Tolerant to VDD_DCI only. H: Compensation for channel loss up to 18.5dB H: Compensation for channel loss up to 14.5dB
2
2
B SSDE = 4.99K_0402_1% M: Compensation for channel loss up to 11.5dB(default) M: Compensation for channel loss up to 10.5dB(default) B
2
L: -3.5dB Output De-emphasis(default)

H: -6dB Output De-emphasis
SD034499180
Ser the USB receiver equalizer gain for upstream facing Select the DisplayPort receiver equalizer gain ,Internally Ser the USB receiver equalizer gain for downstream facing
SSTXP/N,Internally 30k pull-up and 60k pull-down 30k pull-up and 60k pull-down RX1 and RX2 when USB utilized,Internally 30k pull-up and
SSEQ = DPEQ = 60k pull-down
0: Tie 1k to GND 0: Tie 1k to GND USB_EQ =
R:Tie 20k to GND R:Tie 20k to GND 0: Tie 1k to GND
F: Float F: Float R:Tie 20k to GND
1:Tie 1k to VCC 1:Tie 1k to VCC F: Float
1:Tie 1k to VCC
@ RT135 +3.3V_RUN_UT9 @ RT139 +3.3V_RUN_UT9 +3.3V_RUN_UT9

546@ RT139
@
2
2
1K_0402_5%
1K_0402_5%
1K_0402_5%
RT141
@ RT135
4.7K_0402_5% 4.7K_0402_5%
SD028470180 SD028470180
1
(ADDR/DCICFG) (CDE/DCI_CLK)
MUX1_SSEQ1 MUX1_DPEQ0 MUX1_USB_EQ1
546@ RT136
546@ RT142
20K_0402_5%
20K_0402_5%
20K_0402_5%
@ RT136
1
1
1K_0402_5%
@ RT305
1K_0402_5%
@ RT306
1K_0402_5%
@ RT307
A @ A
RT140
2
4.7K_0402_5%
SD028470180
PROPRIETARY NOTE: Compal Electronics, Inc.

PS8743B Pin Control Mode PS8743: PS8743B Pin Control Mode THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
DCI mode configuration pin; Internally tied to I2C Control mode USB Type-C connector facing TX channel TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
VDD33/2, 3.3V I/O. ADDR: I2C control bus address LSB. De-emphasis setting. Internally pull down at 150k. BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
DP/USB3 Repeater SW TUSB546
DCICFG = Internally pull down at 150k, 3.3VI/O. Tolerant to VDD_DCI only. Size Document Number Re v
L: DCI mode disabled [ADDR] = CDE =
H: DCI mode enabled
M: Automatic DCI mode entering enabled (default)
L: 0x20/0x21
H: 0x22/0x23
L: -3.5dB Output De-emphasis(default)
H: -6dB Output De-emphasis
LA-F391P
5 4 3 2 1
5 4 3 2 1
+3.3V_VDD_PIC
+3.3V_TBTA_FLASH +3.3V_TBTA_FLASH
For NON-AR port1
2
1
1
3.3K_0402_5%
3.3K_0402_5%
3.3K_0402_5%
3.3K_0402_5%
.1U_0402_16V7K
RT50
CT70
RT51
RT52
RT53
UPD1_SMBCLK_Q
1
1 6
<35> UPD1_SMBCLK
@ QT1A
2 DMN66D0LDW-7_SOT363-6
2
2
@ RT58 1 2 0_0402_5%
UT6 TBTA_ROM_CS#_PD_R
5
TBTA_ROM_HOLD#_PD 8 1 TBTA_ROM_DO_PD_R
7 VCC CS# 2
TBTA_ROM_CLK_PD_R HOLD#(IO3) DO(IO1) 3 TBTA_ROM_WP#_PD UPD1_SMBDAT_Q
TBTA_ROM_DI_PD_R 6 4 3
5 CLK WP#(IO2) 4 <35> UPD1_SMBDAT
DI(IO0) GND @ QT1B
GD25Q80CSIGR_SO8 DMN66D0LDW-7_SOT363-6
@ RT59 1 2 0_0402_5%
D D
TBTA_ROM_CLK_PD_R TBTA_ROM_CLK_PD
TBTA_ROM_DI_PD_R @ RT54 1 2 0_0402_5% TBTA_ROM_DI_PD
TBTA_ROM_DO_PD_R @ RT55 1 2 0_0402_5% TBTA_ROM_DO_PD UPD1_SMBINT#_R
TBTA_ROM_CS#_PD_R @ RT56 1 2 0_0402_5% TBTA_ROM_CS#_PD @ RT60 1 2 0_0402_5%
@ RT57 1 2 <35> UPD1_SMBINT#
0_0402_5%
+3.3V_TBTA_FLASH
JDB1
1 TBTA_ROM_CLK_PD_R
1 2
2 TBTA_ROM_DI_PD_R
3 TBTA_ROM_DO_PD_R
3 4
4 TBTA_ROM_CS#_PD_R
7 5
8 GND 5 6 +3.3V_TBTA_FLASH +3.3V_TBTA_FLASH +3.3V_TBTA_FLASH +5V_ALW
GND 6
PJP8 TI is 1x47uf+1x0.1uf
1
JXT_FP241AH-006GAAM 8743@ 1 2
CONN@ @ RT405 @ RT406 RT407
1M_0402_5% 1M_0402_5% 10K_0402_5% PAD-OPEN 1x3m +TBTA_Vbus_1
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
1 1 1 1
CT75
CT76
CT77
CT78
2
2
MUX1_FLIP_SEL_R TBTA_DEBUG3 TBTA_DEBUG4
2 2 2 2
+TBTA_LDO_BMC
+VCC1V8D_TBTA_LDO
+VCC1V8A_TBTA_LDO RT64 @ 1 2 0_0402_5%
RT65 @ 1 2 0_0402_5%
+3.3V_VDD_PIC +3.3V_VDD_PIC_PDA
HV_GATE1_A
HV_GATE2_A
PJP7
2.2U_0402_16V6K
2.2U_0402_16V6K
2.2U_0402_16V6K
1 1 1
TI is 3x1uf 1 2
+5V_ALW_PDA
CT71
CT72
CT73
PAD-OPEN1x1m 1
2 2 2 1 2
1U_0402_16V6K
CT74
C C
DIV = R2/(R1+R2) @ RT63 0_0402_5%
Factory Device Descrip ti o n
H10
C11
D11
A11
B11
B10
A10
Configu ra ti o n 2
H1
B1
K1
A2
E1
A6
A7
A8
B7
B9
A9
DIV_min DIV_max
UT5
+3.3V_TBTA_FLASH F1
LDO_1V8A
PP_CABLE
SENSEP
LDO_1V8D
LDO_BMC
GND
GND
GND
GND
SENSEN
VIN_3V3
VDDIO
PP_5V0
PP_5V0
PP_5V0
PP_5V0
HV_GATE1
HV_GATE2
UFP only +3.3V_TBTA_FLASH I2C_ADDR
5V @0.9A Sink capability with "Ask for Max/" for RT378 2 1 10K_0402_5% D1
0.0 0 0.0 8 0 anything from 0.9 -3.0A RT379 2 1 10K_0402_5% D2 I2C_SDA1 +TBTA_Vbus_1
TBT Alternate Modes not supported +3.3V_TBTA_FLASH I2C_SCL1
DisplayPort Alternate Modes not supported C1
2
I2C_IRQ1_N TI has 1x1uf

TI VID supported
+3.3V_ALW UPD1_SMBDAT_Q
10K_0402_1% @ RT66 2 1 3.3K_0402_5% UPD1_SMBCLK_Q A5 +3.3V_PDA_VOUT +3.3V_TBTA_FLASH
UFP only RT76 @ RT67 2 1 3.3K_0402_5% UPD1_SMBINT#_R B5 I2C_SDA2 H11
1
5V @0.9A Sink capability with "Ask for Max/" for @ RT68 2 1 10K_0402_5% B6 I2C_SCL2 VBUS J10
PD1_GPIO8
1
anything from 0.9 -3.0A 2 1 0_0402_5% I2C_IRQ2_N VBUS J11
1U_0603_25V6K
0.1 0 0.1 8 1 MUX1_FLIP_SEL 8743@ RT417
CT82
TBT Alternate Modes not supported <25> MUX1_USB_EQ0 MUX1_FLIP_SEL_R VBUS 1 1
2 1 0_0402_5% B2 K11
1U_0402_16V6K
546@ RT69
10U_0603_6.3V6M
CT83
DisplayPort Alternate Modes -Sink, C and D pin configuration <25> MUX1_FLIP_SEL EN_PD_HV_1 EN_PD_HV_1_R
2
1
0_0402_5% 2 1 RT70 @ C2 GPIO0 VBUS
CT84
TI VID supported <60> EN_PD_HV_1 PD1_GPIO2
RT377 RT71 2 1 1M_0402_5% AC1_DISC#_R D10 GPIO1
0_0402_5% 2 1 RT72 @ G11 GPIO2 2 2
43K_0402_1% <59,60> AC1_DISC# SW2_DP1_HPD_R
UFP only 0_0402_5% 2 1 RT73 @ C10 GPIO3
<22,25> SW2_DP1_HPD OTG_ID GPIO4
0.2 0 0.2 8 2 5V @3.0A Source capability @ RT74 2 1 0_0402_5% E10 H2
PD1_GPIO6
2
TBT Alternate Modes not supported <10> USB2_ID 2 1 0_0402_5% G10 GPIO5 VOUT_3V3
@ RT75 PD1_GPIO7
DisplayPort Alternate Modes not supported 2 1 0_0402_5% D7 GPIO6
TI VID supported @ RT339 PD1_GPIO8
H6 GPIO7
GPIO8 G1
TBTA_ROM_CLK_PD LDO_3V3
UFP only TBTA_ROM_DI_PD A3
0.3 0 0.3 8 3 5V @3.0A Source capability B4 SPI_CLK
TBT Alternate Modes not supported TBTA_ROM_DO_PD SPI_MOSI
TBTA_ROM_CS#_PD A4
DisplayPort Alternate Modes -Sink, C and D pin configuration SPI_MISO
TI VID supported B3 K6
SPI_SS_N C_USB_TP L6 TBTA_TOP_P <28>
C_USB_TN TBTA_TOP_N <28>
UART_MOSI L5
2 1 <10> USB20_P1 USB_RP_P
DRP UART_MOSI K5
5V @0.9-3.0A Sink capability <10> USB20_N1 USB_RP_N
RT81 100K_0402_5%
UART_MISO
0.4 0 0.4 8 5V @3.0A Source capability 2 1 2 1 E2 K7
TBT Alternate Modes not supported UART_MISO UART_TX C_USB_BP TBTA_BOT_P <28>
4 @ RT82 1M_0402_5% 0_0402_5% RT83 @ F2 L7
DisplayPort Alternate Modes not supported UART_RX C_USB_BN TBTA_BOT_N <28>
TI VID supported
Accepts data and power role swaps, but does not @ RT84 2 1 0_0402_5% F4
@ T219 PAD~D SWD_DATA
initi a te . @ RT85 2 1 0_0402_5% G4 TI has 2x220pf
@ T220 PAD~D SWD_CLK TBTA_CC1 <28>
L9
C_CC1 L10
DRP C_CC2 WHEN CONNECT BUSPOWERZ TO GND,
TBTA_MRESET TBTA_CC2 <28>
5V @0.9-3.0A Sink capability 2 1 1M_0402_5% E11
820P_0402_50V7K
820P_0402_50V7K
B RT86 CONNECT ALSO RPD_Gn to C_CCn 1 1 B
5V @3.0A Source capability MRESET
TBT Alternate Modes not supported
0.5 0 0.5 8 5 K9 1 2
CT85
CT86
DisplayPort Alternate Modes - Source, C, D, and E TBTA_LSTX_R RPD_G1
pin configurations. @ RT87 1 2 0_0402_5% TBTA_LSRX_R L4 K10 @ RT104 1 2 0_0402_5%
TI VID supported @ RT88 1 2 0_0402_5% K4 TBT_LSTX/R2P RPD_G2 @ RT105 0_0402_5% +3.3V_TBTA_FLASH 2 2
Accepts power role swaps but will not initiate. TBT_LSRX/P2R
Accepts data role swap to UFP and can initiate.
TBTA_DEBUG3 TBTA_DBG_CTL1
MUX1_FLIP_SEL/MUX1_USB_SEL control by: MUX1_USB_SEL 1 2 TBTA_DEBUG4 L3 E4 TBTA_DBG_CTL2 RT106 1 2 10K_0402_5%
GPIO: Pop RT69,RT90;Depop RT375,RT376 <25> MUX1_DP_SEL @ RT89 2 1 0_0402_5% K3 DIG_AUD_P/DEBUG3 DEBUG_CTL1 D5
DRP RT107 1 2 10K_0402_5%
5V @0.9-3.0A Sink capability I2C:Depop RT69,RT90;pop RT375,RT376 <25> MUX1_USB_SEL DIG_AUD_N/DEBUG4 DEBUG_CTL2
546@ RT90 2 1 0_0402_5%
5V @3.0A Source capability <25> MUX1_USB_EQ1
TBT Alternate Modes not supported MUX1_FLIP_SEL UPD1_SMBCLK_Q8743@ RT418 0_0402_5% TBTA_DEBUG1
0.6 0 0.6 8 6 MUX1_USB_SEL @ RT375 1 2 0_0402_5% UPD1_SMBDAT_Q
1 2 TBTA_DEBUG2 L2
DisplayPort Alternate Modes - Source, C, D, and E DEBUG1
pin configurations. @ RT376 1 2 0_0402_5% @ RT92 1 2 0_0402_5% K2
TI VID supported @ RT93 0_0402_5% DEBUG2
TBTA_SBU1_R
Accepts power role swaps but will not initiate. K8 2 1
Accepts data role swap to DFP and can initiate. TBTA_AUXP_C C_SBU1 TBTA_SBU1 <25,28>
546@ CT80 1 2 0.1U_0201_10V6K TBTA_AUXN_C J1 546@ RT108
TBTA_SBU2_R 0_0402_5%
<22,25> SW2_DP1_AUXP 1 2 0.1U_0201_10V6K J2 AUX_P L8 2 1
Route in pass through manner so AUX can be snooped by 546 <22,25> SW2_DP1_AUXN
546@ CT81
TBTA_SBU2 <25,28>
0.7 0 1.0 0 7 Infinite boot retry from Flash to Host I/F cycles. AUX_N C_SBU2 546@ RT109 0_0402_5%
F10 PDA_RESET#_R
BUSPOWER_N F11 0_0402_5% 2 1 @ RT110
+3.3V_TBTA_FLASH RESET_N
TBTA_ROSC
HRESET
G2
+3.3V_TBTA_FLASH R_OSC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
SS
2
15K_0402_1%
@
0_0402_5%
TPS65982DC_BGA96
RT100
TBTA_AUXN_C
A1
D6
E5
E6
E7
F5
G5
H4
H5
B8
D8
E8
F6
F7
F8
G6
G7
G8
H7
H8
L1
L11
2 1
RT98
RT95 546@ 100K_0402_5%

2
TBTA_AUXP_C
1
2 1 +VCC1V8D_TBTA_LDO
RT96 546@ 100K_0402_5% 1 2
@ RT97 0_0402_5%
1
100K_0402_5%
1
0_0402_5%
1
@ CT87
RT101
RT103
RT99
0_0402_5% 0.22U_0402_16V7K
2 @
2
2
A A
Link TPS65982D (from SA00009W200 to SA00009W210) 08/04

running change from SA00009W210 to SA0000AK400 12/31
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
[Type C]PD Controller TI
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number Rev
LA-F391P 0.2

5 4 3 2 1
5 4 3 2 1
+5V_ALW
DT1 +5V_PD_VDD
2 1 +3.3V_VDD_PIC
+5V_TBT_VBUS UT7
1N4148WS-L_SOD323-2 1 5
DT2 VCC VOUT
D 2 1 2 D
100K_0402_5%
GND
1
@
0.1U_0201_10V6K
1U_0402_10V6K
1N4148WS-L_SOD323-2 3 4
RT393
1 1 EN ADJ/NC
2.2U_0402_10V6M
0.1U_0402_25V6K
1
1
CT88
CT89
@
CT91
CT92
1 2 AP2112K-3.3TRG1_SOT23-5
2
2 2 RT111 100K_0402_5%
2
1
CT90
1U_0402_10V6K
2
+TBTA_Vbus_1
UT8
place near UT7
1
VCC
1U_0603_50V6K
DT3 1
+5V_TBTA_VBUS_D
1 2 3
VOUT
CT94
2
1N4148WS-L_SOD323-2 GND
AP2204R-5.0TRG1_SOT89-3 2
1U_0402_10V6K
1
CT93
C C
B B
A A
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD [Type C]PD Power
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number Re v
LA-F391P 0.2

5 4 3 2 1
5 4 3 2 1
For NON AR Config
D D
RF Request
+TBTA_VBUS +TBTA_VBUS +TBTA_VBUS +TBTA_VBUS
JUSBC1
A1 B12
GND_A1 GND_B12
TBTA_TX1P_C
CT95 1 2 0.22U_0201_6.3V6K TBTA_TX1N_C A2 B11
<25> TBTA_TX1P TX1+ RX1+ TBTA_RX1P <25>
CT96 1 2 0.22U_0201_6.3V6K A3 B10
<25> TBTA_TX1N TBTA_RX1N <25>
2
TX1- RX1-
12P_0402_50V8J
RF@ CT189
82P_0402_50V8J
RF@ CT190
1 1
2 1 A4 B9 1 2 ESD@ DT4
0.01U_0201_25V6K CT99 TBTA_CC1 VBUS_A4 VBUS_B9
TBTA_SBU2 CT100 0.01U_0201_25V6K L30ESD24VC3-2_SOT23-3
A5 B8
<26> TBTA_CC1 CC1 SBU2 TBTA_SBU2 <25,26> 2 2
TBTA_TOP_P_R TBTA_BOT_N_R
1 2 A6 B7 1 2
<26> TBTA_TOP_P TBTA_TOP_N_R D+_A6 D-_B7 TBTA_BOT_P_R TBTA_BOT_N <26>
@EMI@RT120 1 2 0_0402_5% A7 B6 @EMI@ RT122 1 2 0_0402_5%
Bottom
C <26> TBTA_TOP_N D-_A7 D+_B6 TBTA_BOT_P <26> C
@EMI@RT121 0_0402_5% @EMI@ RT123 0_0402_5%
TOP
TBTA_SBU1 TBTA_CC2
A8 B5
<25,26> TBTA_SBU1 TBTA_CC2 <26>
1
SBU1 CC2
2 1 A9 B4 1 2
0.01U_0201_25V6K CT101 VBUS_A9 VBUS_B4
TBTA_TX2N_CCT102 0.01U_0201_25V6K
A10 B3 0.22U_0201_6.3V6K 2 1 CT98
<25> TBTA_RX2N RX2- TX2- TBTA_TX2P_C TBTA_TX2N <25>
A11 B2 0.22U_0201_6.3V6K 2 1 CT97
<25> TBTA_RX2P RX2+ TX2+ TBTA_TX2P <25>
A12 B1
GND_A12 GND_B1
1 4
2 GND1 GND4 5
3 GND2 GND5 6
GND3 GND6
JAE_DX07BD24JJ2
D
X
0
7
B
D
2
4
J
J
2
L
I
N
K
D
O
N
E
CONN@
Premium 12/14/15 UMA:Check SBU1/SBU2 connect to PD or PS8740B
DT5, DT6, DT9, DT10, DT13, DT14, DT17,DT18,

change CPN from SC40000AT00 to SC40000DF00 06/07/2017
ESD@ DT5 ESD@ DT13
B B
TBTA_TX1P_C TBTA_RX1P
1 2 1 2
AZ5B75-01B_CSP0603P2Y AZ5B75-01B_CSP0603P2Y
ESD@ DT6 ESD@ DT14

TBTA_TX1N_C TBTA_RX1N
1 2 1 2
ESD@ DT9 ESD@ DT17

TBTA_RX2N TBTA_TX2P_C
1 2 1 2
ESD@ DT10 ESD@ DT18

TBTA_RX2P TBTA_TX2N_C
1 2 1 2
DT39 ESD@ DT40 ESD@

TBTA_CC2 TBTA_CC2 TBTA_SBU2 TBTA_SBU2
1 1 10 9 1 1 10 9
TBTA_CC1 TBTA_CC1 TBTA_SBU1 TBTA_SBU1
2 2 9 8 2 2 9 8
TBTA_TOP_P_R TBTA_TOP_P_R TBTA_BOT_N_R TBTA_BOT_N_R
4 4 7 7 4 4 7 7
TBTA_TOP_N_R TBTA_TOP_N_R TBTA_BOT_P_R TBTA_BOT_P_R
5 5 6 6 5 5 6 6
A A
3 3 3 3
8 8
L05ESDL5V0NA-4_SLP2510P8-10-9 L05ESDL5V0NA-4_SLP2510P8-10-9
PROPRIETARY NOTE:
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USB 3.0 CONN TYPE C
LA-F391P
5 4 3 2 1
5 4 3 2 1
LINK 50398-04041-001 DONE

JEDP1
1
+3.3V_TSP
TOUCH_PANEL_INTR#:
Close lid >> TP_EN = 0 >> Disable touch events
Open lid >> TP_EN = 1 >> Enable touch events 1
LV27 EMI@
2
For 2LANE EDP &3.3V_TSP
1 USB20_N8_R USB20_N8 <10>
2
2
3
4
3
4
5
USB20_P8_R
4 3
USB20_P8 <10>
For Breckenridge&Steamboat 12
5 6 TOUCH_SCREEN_PD# <12>
EXC24CQ900U_4P
6
AZC199-02SPR7G_SOT23-3
7
DMIC0 <34>
3
7
@ESD@
8
8 9
3
9 10 DMIC_CLK0 <34>
10 +3.3V_RUN
11 RF Request
11 USB20_N5_R +3.3V_CAM
27P_0402_50V8J
@RF@ CA5
27P_0402_50V8J
@RF@ CA6
1
12 USB20_P5_R
12 +3.3V_TSP
DV4
13
1
13
1
14
14 15 CAM_MIC_CBL_DET# <12>
15 16 Pin15: LOOP_BACK
D D
2
16 17
17 +BL_PWR_SRC
18
18 19 +3.3V_RUN
19
ESD depop locat i on
20 BIA_PWM
20
12P_0402_50V8J
RF@ CV18
82P_0402_50V8J
RF@ CV19
21 EMI@ LV1 1 2
10K_0402_5%
21 DISP_ON 1 1
2
22 BLM15PX221SN1D_2P
RV8
22 RF Request
23
23 24
24 25 2 2
25 26 +LCDVDD
EDP_HPD <6> TOUCH_SCREEN_DET#
1
26 27
27 EDP_HPD
28 1 2
28 29 @ RV7 100K_0402_5%
29 30 LCD_TST <35>
30 31 Reserve for EA
If touch panel, GPIO Low-> Touch Mic. EQ ;
31 TOUCH_SCREEN_DET#
+LCDVDD others the GPIO is High -> Non-Touch Mic.
32 EDP_AUXN_C
32 33 EDP_AUXP_C CV1 2 1TOUCH_SCREEN_DET#
0.1U_0402_25V6
<12>
EQ
33 EDP_AUXN <6>
34 EDP_TXP0_C CV2 2 1 0.1U_0402_25V6
34 35 2 1 0.1U_0402_25V6 EDP_AUXP <6>
EDP_TXN0_C CV3
41 35 36 2 1 0.1U_0402_25V6 EDP_TXP0 <6>
EDP_TXP1_C CV4
G1 36 EDP_TXN0 <6>
42 37 EDP_TXN1_C CV5 2 1 0.1U_0402_25V6
43 G2 37 38 2 1 0.1U_0402_25V6 EDP_TXP1 <6>
CV6 EDP_TXN1 <6>
44 G3 38 39
45 G4 39 40
G5 40 LCD_CBL_DET# <9>
ACES_50398-04041-001
CONN@
JIR1
1
1 2 IR_CAM_DET# <12>
+BL_PWR_SRC +LCDVDD +3.3V_TSP 2 RF Request
+3.3V_CAM +3.3V_RUN 3
3 4 +PWR_SRC
0.1U_0201_10V6K 4
0.1U_0603_50V7K
0.1U_0201_10V6K
0.1U_0201_10V6K
5
0.1U_0201_10V6K
5 6
1 1 1 1 +PWR_SRC
@RF@ 6
1
@RF@ @RF@
100P_0402_50V8J
RF@ CZ3
@ @RF@ 7 1
GND
CZ2
CV11
CV12
CZ1
CA7
8
GND
2
2
2 2 2
C 2 C
ACES_50208-0060N-P01
CONN@
Close to JEDP1.17~19 Close to JEDP1.30~31 Close to JEDP1.11 Close to JEDP1.1 Close to JEDP1.10 Link ACES_50208-0060N-P01 done
DV1 DV2
EDP_BIA_PWM
3 3
EDP_BIA_PWM <6> PANEL_BKLEN <6>
BIA_PWM DISP_ON
1 1
BIA_PWM_EC
2 2
BIA_PWM_EC <35> PANEL_BKEN_EC <35>
For Breckenridge 12
1
4.7K_0402_5%
4.7K_0402_5%
For Touchscreen
1
BAT54CW_SOT323-3 BAT54CW_SOT323-3
RV1
RV2
+3.3V_RUN +3.3V_TSP +3.3V_RUN

2
QV8
2
10K_0402_5%
LP2301ALT1G_SOT23-3
2
+3.3V_RUN 1 3
RV6
S
100K_0402_5%
G
1
2
1
RV326
RF Request
1 2
RV400 0_0402_5%
+LCDVDD +3.3V_CAM +BL_PWR_SRC
L2N7002WT1G_SC-70-3
1
D
0.1U_0402_25V6K
1
QV7
@ RV323 1 2 0_0402_5% 2 @
<35> 3.3V_TS_EN
CV635
G
@ RV324 1 2 0_0402_5% S
<9> PCH_3.3V_TS_EN
2
12P_0402_50V8J
RF@ CV20
82P_0402_50V8J
RF@ CV21
12P_0402_50V8J
RF@ CV22
82P_0402_50V8J
RF@ CV23
12P_0402_50V8J
RF@ CV24
82P_0402_50V8J
RF@ CV25
B 1 1 1 1 1 1 B
2 2 2 2 2 2
LCDVDD POWER +LCDVDD +EDP_VDD

+3.3V_ALW
@
CV16 PJP12 UV24
2 1 1 2 1
WebCAM
+3.3V_CAM +3.3V_RUN Backlight POWER +BL_PWR_SRC_P +BL_PWR_SRC 10U_0603_10V6M
VOUT
VIN
5
QZ1 PAD-OPEN1x1m 2
GND
0.01UF_0402_25V7K
LP2301ALT1G_SOT23-3 +PWR_SRC QV1 @ RZ93 4
PJP13 EN
@
1 2
CV17
1 3 6 1 2 3
D
0.01_1206_1%
4 5 /OC
S
2 Co-lay: G524B1T11U_SOT23-5
2
1 PAD-OPEN1x2m
Short PJP12;Depop RZ93
G
1000P_0402_50V7K
2
0.1U_0603_50V7K
@ RZ90 DV3
G
270K_0402_5%
2
AO6405_TSOP6 1 2
CV13
3
2
0.01_1206_1% 2
RV4
<35> LCD_VCC_TEST_EN EN_LCDPWR

CV15
1 2 1
<11> 3.3V_CAM_EN#
RZ380 0_0402_5%
1
2
0.1U_0402_25V6K
Co-lay: 3
<6> ENVDD_PCH
1
1
2
100K_0402_5%
@ Short PJP13;Depop RZ90
CZ200
RV3
BL_PWR_SRC_ON
BAT54CW_SOT323-3
2
QV2
1
A A
L2N7002WT1G_SC-70-3
0.01U_0402_50V7K
1
1 2 1 3
D
S
CV14
RV5 47K_0402_5%
LZ1 EMI@ USB20_P5_R
1 2 2
G
<10> USB20_P5
2
<10> USB20_N5
4 3
USB20_N5_R
<35> EN_INVPWR
EXC24CQ900U_4P
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, eDP CONN & Touch screen
LA-F391P
Date: Friday, September 22, 2017 Sheet 29 of 70
5 4 3 2 1
5 4 3 2 1
Layout Not i c e : Pl ac e bead as

+3.3V_LAN UL1 close UL4 as possible
TP_LAN_JTAG_TMS CLKREQ_PCIE#4 LAN_MDIP0 LAN_MDIP0_L
2 1 48 13 LAN_MDIN0 RL71 1 2 2.2_0603_5% LAN_MDIN0_L
<11> CLKREQ_PCIE#4 36 CLK_REQ_N MDI_PLUS0 14 1 2 2.2_0603_5%
@ RL1 10K_0402_5%
TP_LAN_JTAG_TCK RL72
2 1 <11> PLTRST_LAN# PE_RST_N MDI_MINUS0
LAN_MDIP1 LAN_MDIP1_L
@ RL2 10K_0402_5%
CLKREQ_PCIE#4 44 17 LAN_MDIN1 RL73 1 2 2.2_0603_5% LAN_MDIN1_L
2 1 <11> CLK_PCIE_P4 45 PE_CLKP MDI_PLUS1 18 1 2 2.2_0603_5%
PCIE_PRX_C_DTX_P4 RL74
PCIE
<11> CLK_PCIE_N4 PE_CLKN MDI_MINUS1
1 2
MDI
@ RL4 4.7K_0402_5% LAN_MDIP2 LAN_MDIP2_L
<10> PCIE_PRX_DTX_P4 38 20 1 2 2.2_0603_5%
CL1 0.1U_0402_25V6
PCIE_PRX_C_DTX_N4 LAN_MDIN2 RL75 LAN_MDIN2_L
1 2 39 PETp MDI_PLUS2 21 RL76 1 2 2.2_0603_5%
<10> PCIE_PRX_DTX_N4 PETn MDI_MINUS2
CL2 0.1U_0402_25V6
PCIE_PTX_C_DRX_P4 LAN_MDIP3 LAN_MDIP3_L
+3.3V_LAN 1 2 41 23 RL77 1 2 2.2_0603_5%
<10> PCIE_PTX_DRX_P4 PERp MDI_PLUS3 24 LAN_MDIN3 LAN_MDIN3_L
CL5 0.1U_0402_25V6
PCIE_PTX_C_DRX_N4 42 RL78 1 2 2.2_0603_5%
1 2 PERn MDI_MINUS3
<10> PCIE_PTX_DRX_N4
CL6 0.1U_0402_25V6 VCT_LAN_R1
2
28 6 1 2
10K_0402_5%
SMBUS
<8> SML0_SMBCLK 31 SMB_CLK SVR_EN_N
D <8> SML0_SMBDATA SMB_DATA
0_0402_5%
+RSVD_VCC3P3_1 @ RL3 RF Request D
1 4.7K_0402_5% 1 2 RL6
RL5 @
RSVD_VCC3P3_1 +3.3V_LAN +3.3V_LAN_OUT
LAN_DISABLE#_R 2 5
1
1 2 <11,35> LAN_WAKE# 3 LANWAKE_N VDD3P3_IN
<11> PM_LANPHY_ENABLE +3.3V_LAN_OUT
@ RL7 0_0402_5% LAN_DISABLE_N 4 1 2
SMBus Device Address 0xC8 VDD3P3_4 +3.3V_LAN
0_0603_5% @ RL8
10K_0402_5%
0.1U_0201_10V6K
22U_0805_6.3V6M
LOM_ACTLED_YEL# 15 1
1
VDD3P3_15 19
@ RL9
LOM_SPD100LED_ORG# 26 Place CL28 close to UL1.5
LED0 VDD3P3_19 29
CL7
CL28
@RF@
@RF@
LOM_SPD10LED_GRN# 27
LED1 VDD3P3_29
LED
12P_0402_50V8J
82P_0402_50V8J
25 +0.9V_LAN
1 1
2
LED2 BLM15PX181SN1D_2P 2
2 47 1 2 +3.3V_LAN
VDD0P9_47 46
CL12
CL11
CL29
CL30
TP_LAN_JTAG_TDI LL2 EMI@
VDD0P9_46 37 2 2
22U_0603_6.3V6M
0.1U_0201_10V6K
@ T88 PAD~D TP_LAN_JTAG_TDO 32
@ T89 PAD~D 34 JTAG_TDI VDD0P9_37
TP_LAN_JTAG_TMS 1
1
JTAG_TDO
JTAG
+0.9V_LAN TP_LAN_JTAG_TCK 33 43
35 JTAG_TMS VDD0P9_43
JTAG_TCK 11
2
VDD0P9_11 2
470P_0402_50V7K
XTALO_R
0.1U_0201_10V6K
1 2 XTALO 9 40 1
1
XTAL_OUT VDD0P9_40 22
0.1U_0201_10V6K
0.1U_0201_10V6K
@EMI@ CL10
0.1U_0201_10V6K
@ RL34 0_0402_5% XTALI 10
1
XTAL_IN VDD0P9_22 16
CL18
CL19
1 1 1 VDD0P9_16 8
CL9
CL8
LAN_TEST_EN
RJ45 LOM circuit
2
RL11 30 VDD0P9_8 +0.9V_LAN 2
1M_0402_5% TEST_EN
RES_BIAS +REGCTL_PNP10
2 2 2 YL1 12 7 1 2
+3.3V_LAN:20mils
2
3 1 RBIAS CTRL0P9 4.7UH_BRC2012T4R7MD_20% LL1
OUT IN
0.1U_0201_10V6K
10U_0603_10V6M
49 Idc_min =5 0 0 m A
1
27P_0402_50V8J
VSS_EPAD
1K_0402_5%
3.01K_0402_1%
4 2 DCR=10 0 m o h m @ JLOM1
1
1
27P_0402_50V8J
GND GND
CL3
CL4
WGI219LM-QREF- A0_QFN48_6X6~D LAN_ACTLED_YEL# LAN_ACTLED_YEL_R#
1
CL14
RL12
RL13
Note : 25MHZ_18PF_7V25000034 1 2 10
CL13
Yellow LED-
+1.0V_LAN will work at 0.95V to 1.15V RL14 150_0402_5%
2
change to SA000081G0L, S IC A32 WGI219LM QREF A0 QFN 48P PHY 2 9
2
2
Yellow LED+
RJ45_MDIN3
8
PR4-
RJ45_MDIP3
Place CL3, CL4 and LL1 close to UL1 7
PR4+
RJ45_MDIN1
6
PR2-
RJ45_MDIN2
5
PR3-
C RJ45_MDIP2 C
4
PR3+
RJ45_MDIP1
3
PR2+
RJ45_MDIN0
2
PR1- 15
RJ45_MDIP0 GND
1
PR1+ 14
LED_10_GRN# LED_10_GRN_R# GND
1 2 11
RL19 150_0402_5% Green LED-
LED_100_ORG# LED_100_ORG_R#
1 2 13
RL20 150_0402_5% Orange LED-
12
Green-Orange LED+
SANTA_130456-821
CONN@
Link 130456-821 DONE
When LAN & WLAN are exist at the same time, WLAN will disable
+3.3V_LAN TL1
2 1 1 24 Z2805
@ CL15 CL16 0.1U_0201_10V6K TCT1 MCT1
LAN_MDIN3_L RJ45_MDIN3
1 2 2 23
TD1+ MX1+
LAN_MDIP3_L RJ45_MDIP3
0.1U_0201_10V6K 3 22
5
TD1- MX1-
LOM_SPD100LED_ORG#
1 2 1 4 21 Z2807
P
B 4 CL17 0.1U_0201_10V6K TCT2 MCT2

LOM_SPD10LED_GRN# O LOM_CABLE_DETECT# <35> LAN_MDIN1_L RJ45_MDIN1
2 5 20
G
A UL2 TD2 MX2+

B TC7SH08FU_SSOP5~D 6 19 B
3
TD2- MX2-
2 1 7 18 Z2806
CL20 0.1U_0201_10V6K TCT3 MCT3
8 17
TD3+ MX3+
QL1A 9 16
TD3- MX3-
LOM_ACTLED_YEL# DMN65D8LDW-7_SOT363-6 LAN_ACTLED_YEL#
1 6 2 1 10 15 Z2808
CL21 0.1U_0201_10V6K TCT4 MCT4
11 14
+3.3V_LAN TD4+ MX4+
2
LED_MASK# 12 13
TD4- MX4-
LED_MASK# <35,46>
1
RL29 350UH_IH-160
1M_0402_5%
QL1B 1 75_0402_1%
1 75_0402_1%
1 75_0402_1%
1 75_0402_1%
LOM_SPD100LED_ORG# LED_100_ORG#
2
4 3
+3.3V_LAN
5
LED_MASK#
1
RL30
1M_0402_5%
QL2A
RL15 2
RL16 2
RL17 2
RL18 2
LOM_SPD10LED_GRN# DMN65D8LDW-7_SOT363-6
LED_10_GRN#
2
1 6
+GND_CHASSIS
GND 1 2
EMI@ CL22 10P_1808_3KV8J
CHASSIS
2
LED_MASK# use 40mil trace if necessary
For WLAN can't recognize during enable

Unobtrusive mode(BITS152312)
QL2B
4 3
A A
5
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, LAN Clarkvillie & RJ45
LA-F391P
5 4 3 2 1
A B C D E
For PCIE Interface
1 1
+3.3V_RUN +3.3V_MMI_IN
PJP14
1 2
RF Request
+3.3V_MMI_AUX +3.3V_MMI_IN
+3.3V_MMI_AUX +3.3V_MMI_IN PAD-OPEN1x2m
+3.3V_MMI_IN +3.3V_MMI_AUX
4.7U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0402_6.3V6M
1 2
support D3 Hot(if D3 cold PIN11,PIN27 need Add MOS on/of f 3 V3 AUX)
1 1 1 1
CR4
0_0603_5% R274 @
CR3
CR1
CR2
@RF@
@RF@
@RF@
@RF@
2 2 2 2
12P_0402_50V8J
82P_0402_50V8J
12P_0402_50V8J
82P_0402_50V8J
1 1 1 1
CR27
CR28
CR25
CR26 +3.3V_MMI_AUX
2 2 2 2
MEDIACARD_IRQ#
2 1 7/18 Vender suggest.
RR19 10K_0402_5%
27
11
UR1
3V3aux
3V3_IN
1 12 +DV33_18
<11,33,38,40> PCH_PLTRST#_AND PERST# CARD_3V3 18 +3.3V_RUN_CARD
2 1 2
<11> CLKREQ_PCIE#5 CLK_REQ# DV33_18 CR22 1U_0402_6.3V6K
5 SD/MMCDAT1/RCLK-_R
<11> CLK_PCIE_P5 REFCLKP
6 15 SD/MMCDAT1/RCLK- 1 2 SD/MMCDAT0/RCLK+_R
<11> CLK_PCIE_N5 REFCLKN SP1 16 1 2
PCIE_PTX_C_DRX_P1 SD/MMCDAT0/RCLK+ @ RR9 0_0402_5% SD/MMCCLK_R
CR11 1 2 0.1U_0402_25V6 3 RTS5242 SP2 17 SD/MMCCLK @ RR10 1 2 0_0402_5%
<10> PCIE_PTX_DRX_P1 PCIE_PTX_C_DRX_N1 SD/MMCCMD_R
HSIP SP3
@EMI@ CR21
CR12 1 2 0.1U_0402_25V6 PCIE_PRX_C_DTX_P1 4 19 SD/MMCCMD @EMI@ RR5 1 2 0_0402_5% SD/MMCDAT3_R
<10> PCIE_PTX_DRX_N1 HSIN SP4
5P_0402_50V8C
CR13 1 2 0.1U_0402_25V6 PCIE_PRX_C_DTX_N1 7 20 SD/MMCDAT3 @ RR6 1 2 0_0402_5% SD/MMCDAT2_R
<10> PCIE_PRX_DTX_P1 CR14 1 2 0.1U_0402_25V6 8 HSOP SP5 21 SD/MMCDAT2 @ RR7 1 2 0_0402_5%
1
<10> PCIE_PRX_DTX_N1 HSON SP6 29 SDWP @ RR8 0_0402_5%
SP7
32
2 2
2
<9> MEDIACARD_IRQ# 31 WAKE#
SD/MMCCD# 30 MS_INS#
+1.2V_LDO SD_CD#
7/18
SD_UHS2_D1P Vender suggest
CR13 close to UR2.10 22 SD_UHS2_D1N EMI depop locat i on
SD_LN1_P 23
CR9 CR10 close to UR2.14 SD_LN1_M
10 SD_UHS2_D0P
14 AV12 26
DV12S SD_LN0_P 25 SD_UHS2_D0N
SD_LN0_M
4.7U_0603_6.3V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
13
+1.8V_RUN_CARD SD_VDD2
1 1 24 +SDREG2 CR15 1 2
E-PAD
1
9 SDREG2 28
CR5
+RREF SD_GPIO 1U_0402_6.3V6K
CR6
CR7
RREF GPIO 2 1
+3.3V_MMI_AUX
10K_0402_5% RR3
2
2 2 RTS5242-GR_QFN32_4X4
33
1
6.2K_0402_1%
RR4
2
3 3
JSD1 CONN@
SD/MMCDAT2_R
SD/MMCDAT3_R 1
QR1 2 DAT2
SD/MMCCMD_R
L2N7002WT1G_SC-70-3 3 CD/DAT3
HOST_ SD _ WP# SD WP_ Q SD W P STATU S 4 CMD
+3.3V_RUN_CARD SD/MMCCLK_R VDD1
SDWP 1 3 5
S
6 CLK
SD/MMCDAT0/RCLK+_R VSS
Hig h Hig h Write Protect(SD LOCK) SD/MMCDAT1/RCLK-_R 7
8 DAT0/RCLK+
G
2
Hig h SD/MMCCD# 9 DAT1/RCLK-
Low Low Write Enable 13 CD
<12> HOST_SD_WP# +1.8V_RUN_CARD VDD2
14
15 SWIO
SD_UHS2_D0P VSS
Hig h Hig h Write Protect(SD& FW LOCK) SD_UHS2_D0N 16
Low 17 D0+
18 D0- 10
SD_UHS2_D1N VSS GND
Low Hig h Write Protect(FW LOCK) SD_UHS2_D1P 19 11
+3.3V_RUN_CARD +1.8V_RUN_CARD 20 D1- GND 12
21 D1+ GND 22
VSS GND 23
GND
0.1U_0201_10V6K
0.1U_0201_10V6K
T-SOL_158-1000902614
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
2 2
2
CR17
CR19
CR20
CR18
1
1
1 1
CR38,CR39 near JSD1.4 CR40,CR41 near JSD1.14
4 4
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Card Reader RTS5242
LA-F391P
A B C D E
5 4 3 2 1
D D
C
NO SUPPORT C
B B
A A
PCIE REPEATER for M.2 3042
LA-F391P 0.2

5 4 3 2 1
5 4 3 2 1
+3.3V_WWAN for no AR,Brekenridge 12/14/15 UMA/Steamboat

NGFF slot B Key B
WWAN_PWR_EN
2 1 +3.3V_WWAN
RZ43 47K_0402_5%
100P_0402_50V8J
JNGFF2 CONN@
RF@ CZ198
1 2
<35> NGFF_CONFIG_3 3 CONFIG_3 3.3V_2 4
WWAN_PWR_EN
1
5 GND_3 3.3V_4 6
USB20_P4_L GND_5 FUL_CARD_PWR_OFF# 8 WWAN_RADIO_DIS#_R
7
USB20_N4_L
9 USB_D_P W_DISABLE1# 10 SLOT2_SATA_LED#
1 2
SATALED# <10,40,46> NGFF slot A Key A
2
11 USB_D_N LED1# @ RN101 0_0402_5%
GND_11
D +3.3V_WLAN D
20
21 I2S_CLK 22 JNGFF1 CONN@
<35> NGFF_CONFIG_0 CONFIG_0 I2S_RX
23 24 GPS_DISABLE#_R USB20_P7_L 1 2
<35> WWAN_WAKE# 2 1 25 WOWWAN# I2S_TX 26 3 GND_1 3.3V_2 4
DPR W_DISABLE2# USB20_N7_L USB_D_P 3.3V_4
@RF@ USB3_PRX_L_DTX_N2
RZ326 0_0402_5% 27 28 UIM_RESET 5 6
29 GND_27 I2S_WA 30 7 USB_D_N LED1#
USB3_PRX_L_DTX_P2 USB3.0_TX_N UIM_RESET UIM_CLK GND_7
31 32 UIM_DATA
33 USB3.0_TX_P UIM_CLK 34
USB3_PTX_L_DRX_N2 GND_33 UIM_DATA
35 36
support SATA/PCIE USB3_PTX_L_DRX_P2
37 USB3.0_RX_N UIM_PWR 38 ISH_I2C2_SCL_R
+SIM_PWR
16
39 USB3.0_RX_P N/C_38 40 2 1 M3042_DEVSLP <10> 17 LED2# 18
GND_39 GNSS_SCL ISH_I2C2_SDA_R ISH_I2C2_SCL <9> DP_MLDIR_GND GND_18 20
41 42 @ RZ76 2 1
0_0402_5% 19
<10> PCIE_PRX_DTX_P8 43 PET_N0 GNSS_SDA 44 ISH_I2C2_SDA <9>
21 DP_ML3N DP_AUXN 22
@ RZ77 0_0402_5%
<10> PCIE_PRX_DTX_N8 45 PET_P0 GNSS_IRQ 46 23 DP_ML3P DP_AUXP 24
PCIE_PTX_C_DRX_N8 GND_45 SYSCLK GND_23 GND_24 26
CZ10 1 2 0.1U_0402_25V6 PCIE_PTX_C_DRX_P8 47 48 PCH_PLTRST#_AND 9/24: Reserve for embedded locat i on ,r ef er I nt el PDG 0. 9 25
<10> PCIE_PTX_DRX_N8 1 2 0.1U_0402_25V6 49 PER_N0 TX_BLANKING 50 27 DP_ML2N DP_ML1N 28
CZ11
<10> PCIE_PTX_DRX_P8 PER_P0 PERST# DP_ML2P DP_ML1P 30
51 52 PCIE_WAKE# 29
GND_51 CLKREQ# CLKREQ_PCIE#0 <11> GND_29 GND_30 32
53 54 31
<11> CLK_PCIE_N0 55 REFCLKN PEWAKE# 56 33 DP_HPD DP_ML0N 34
<11> CLK_PCIE_P0 REFCLKP REF_RFFE2_SCLK PCIE_PTX_C_DRX_P3 GND_33 DP_ML0P 36
57 58 @ RZ132 2
WWAN_COEX3 1 0_0402_5% WLAN_COEX3 CZ12 1 2 0.1U_0402_25V6 PCIE_PTX_C_DRX_N3 35
59 GND_57 REF_RFFE2_SDATA 60 HOST_DEBUG_TX <35,36> <10> PCIE_PTX_DRX_P3 PER_P0 GND_36 38
ANTCTL0 COEX3 WWAN_COEX2 @RF@ RZ128 1 2 0_0201_5% WLAN_COEX2
<10> PCIE_PTX_DRX_N3
CZ13 1 2 0.1U_0402_25V6 37
PER_N0 CLink_RST 40 PCH_CL_RST1# <8>
61 62 WWAN_COEX1 @RF@ RZ129 1 2 0_0201_5% WLAN_COEX1 39
63 ANTCTL1 COEX2 64 GND_39 CLink_DATA 42 PCH_CL_DATA1 <8>
@RF@ RZ130 1 2 0_0201_5% 41
65 ANTCTL2 COEX1 66
SIM_DET WLAN <10> PCIE_PRX_DTX_P3 43 PET_P0 CLink_CLK 44 WLAN_COEX3
WLAN_COEX2
PCH_CL_CLK1 <8>
PAD~D @ T225 67 N/C_65 SIM_DETECT 68 <10> PCIE_PRX_DTX_N3 45 PET_N0 COEX3 46
RESET# N/C_68 GND_45 COEX2 48 WLAN_COEX1
69 70 47 WIGIG_32KHZ
<35> NGFF_CONFIG_1 CONFIG_1 3.3V_70 <11> CLK_PCIE_P1 REFCLK_P0 COEX1 50
71 72 49 PCH_PLTRST#_AND @ RZ56 1 2 0_0402_5%
GND_71 3.3V_72 <11> CLK_PCIE_N1 REFCLK_N0 SUSCLK(32KHz) 52 SUSCLK <11,40>
73 74 51 BT_RADIO_DIS#_R
75 GND_73 3.3V_74 53 GND_51 PERST0# 54 PCH_PLTRST#_AND <11,31,38,40>
<35> NGFF_CONFIG_2 CONFIG_2 <11> CLKREQ_PCIE#1 PCIE_WAKE# CLKREQ0# W_DISABLE2# 56 WLAN_WIGIG60GHZ_DIS#_R
55 ISH_UART0_RXD_R
<36,40> PCIE_WAKE# 57 PEWAKE0# W_DISABLE1# 58 2 1
GND_57 I2C_DATA 60 ISH_UART0_TXD_R ISH_UART0_RXD <9>
77 76 59 ISH_UART0_CTS#_R @ RZ78 2 1 0_0402_5%
GND1 GND2 PER_P1 I2C_CLK 62 ISH_UART0_TXD <9>
61 ISH_UART0_RTS#_R @ RZ79 2 1 0_0402_5%
63 PER_N1 ALERT# 64 ISH_UART0_CTS# <9>
CONCR_213BAAA42FA
GND_63 RESERVED 66 PCH_PLTRST#_AND @ RZ80 2 1 0_0402_5%
ISH_UART0_RTS# <9>
65 @ RZ81 0_0402_5%
67 PET_P1 PERST1# 68
PET_N1 CLKREQ1# 70 PCIE_WAKE#
69
71 GND_69 PEWAKE1# 72
73 REFCLK_P1 3.3V_72 74
75 REFCLK_N1 3.3V_74 9/24: Reserve for embedded locat i on ,r ef er I nt el PDG 0. 9
GND_75
C RF Request C
+3.3V_WWAN
77 76
GND1 GND2
+3.3V_WWAN CONCR_213AAAA42FA
47P_0402_50V8J
100P_0402_50V8J
2000P_0402_50V7K
RF@
.047U_0402_16V7K
.047U_0402_16V7K
33P_0402_50V8J
33P_0402_50V8J
RF@ CZ24
100U_B2_6.3VM_R35M
RF@ CZ26
1
RF@ CZ25
1
1
22U_0603_6.3V6M
+ WWAN_RADIO_DIS#_R
1
CZ23
1 2
<35> WWAN_RADIO_DIS#
CZ17
CZ18
CZ19
CZ20
CZ21
2 DZ5
2
RB751S40T1G_SOD523-2
GPS_DISABLE#_R
1 2
<35> GPS_DISABLE#
DZ6
1 2 RB751S40T1G_SOD523-2
@RF@ RI27 0_0402_5%
HCM1012GH900BP_4P
USB3_PRX_L_DTX_P2 +3.3V_WLAN
4 3
RF Request
USB3_PRX_L_DTX_N2
1 2
0.01UF_0402_25V7K
0.1U_0201_10V6K
10U_0603_10V6M
0.01UF_0402_25V7K
0.1U_0201_10V6K
4.7U_0603_6.3V6K
LI16 RF@ 1 2 WLAN_WIGIG60GHZ_DIS#_R
@RF@ RI47 0_0402_5% 1 2
1 2 <35> WLAN_WIGIG60GHZ_DIS#
1 1 1
1
@RF@ RI28 0_0402_5% DZ1
CZ28
CZ30
CZ27
CZ29
CZ31
CZ32
RB751S40T1G_SOD523-2
2
1 2 2 2 2
@RF@ RI29 0_0402_5% MCM1012B900F06BP_4P
HCM1012GH900BP_4P USB20_P4_L
USB3_PTX_C_DRX_P2 USB3_PTX_L_DRX_P2 4 3
2 1 4 3 <10> USB20_P4
<10> USB3_PTX_DRX_P2
CI30 0.1U_0402_25V6 USB20_N4_L BT_RADIO_DIS#_R
B USB3_PTX_C_DRX_N2 USB3_PTX_L_DRX_N2 1 2 1 2 B
2 1 1 2 <10> USB20_N4 <35> BT_RADIO_DIS#
Place near JNGFF1.72/JNGFF1.74 Place near JNGFF1.2/JNGFF1.4
<10> USB3_PTX_DRX_N2 LI8 RF@
CI29 0.1U_0402_25V6 DZ2
LI17 RF@ RB751S40T1G_SOD523-2
1 2
@RF@ RI30 0_0402_5% RF Request
1 2
@RF@ RI48 0_0402_5% +3.3V_WLAN
SIM Card Push-Push
+SIM_PWR
15P_0402_50V8J
15P_0402_50V8J
15P_0402_50V8J
15P_0402_50V8J
STATE # CONFIG_0 CONFIG_1 CONFIG_2 CONFIG_3 Module Type M3042_PCIE#_SATA
RF@ CZ33
RF@ CZ34
RF@ CZ35
RF@ CZ36
JSIM1 CONN@
4.7U_0402_6.3V6M
UIM_RESET 1 5
1
2 VCC GND 6
UIM_CLK UIM_DATA 0 GND GND GND GND SSD-SATA High RF Request
1
3 RST VPP 7
CLK I/O
CZ37
4 8 1 2
2
RFU1 RFU2 @RF@ RI49 0_0402_5%
SIM_DET 1 GND HIGH GND GND SSD-PCIE(2 lane) Low
2
9
DTSW
10
11 GND 14
8 HIGH GND GND GND W WAN Low
12 GND GND 15
13 GND GND 16
GND GND 14 HIGH GND HIGH HIGH HCA-PCIE(1 lane) Low MCM1012B900F06BP_4P
USB20_P7_L
4 3
T
-
S
O
L
_
5
-
9
9
1
5
0
3
0
0
4
0
0
0
-
6
L
I
N
K
D
O
N
E
<10> USB20_P7
T-SOL_5-991503004000-6 15 HIGH HIGH HIGH HIGH NA Low
USB20_N7_L
1 2
<10> USB20_N7
LI9 RF@
Power Rating TBD
+SIM_PWR Primary Power Aux Power
1 2 PWR Voltage
@RF@ RI50 0_0402_5%
UIM_CLK Rail Tolerance
@RF@
Peak Normal Normal

1
15K_0402_5%
47P_0402_50V8J
@RF@ CZ38
+3.3V
RZ335
1
A A
2
+SIM_PWR
UIM_DATA UIM_RESET
2
33P_0402_50V8J
33P_0402_50V8J
@RF@ CZ39
@RF@ CZ40
1
51_0402_5%
@RF@
0.1U_0402_25V6
RF@ CZ41
1
1
2
2
RZ334
2

RF Request TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
NGFF Card
LA-F391P
5 4 3 2 1
2 1
+3.3V_RUN_AUDIO +5V_RUN_AUDIO
2W x 1ch, 4ohm +1.8V_RUN place close to pin41 place close to pin46 LA13
+5V_RUN_PVDD_L
+1.8V_RUN_AUDIO +3.3V_RUN_AUDIO_DVDD 1 2
Internal Speakers Header 1 2 place close to pin20 2 1 HCB2012KF-121T50_2P
0.1U_0201_10V6K
10U_0603_10V6M
0.1U_0201_10V6K
10U_0603_10V6M
0.1U_0201_10V6K
10U_0603_10V6M
@ RA3 0_0603_5% LA14 BLM15PX600SN1D_2P 1 1 1 1 1 1
10U_0603_10V6M
0.1U_0201_10V6K
CA45
CA47
CA60
40 mils trace keep 20 mil spacing +3.3V_RUN_AUDIO_IO 600 Ohm/2A
0.1U_0201_10V6K
10U_0603_10V6M
CA46
CA48
CA59
INT_SPK_L+ INT_SPKR_L+ JSPK1 1 2 1
CA58
CA57
INT_SPK_L- EMI@ LA6 1 2 BLM15PX330SN1D_2P INT_SPKR_L- 1 7 1 LA12 BLM15PX600SN1D_2P
1
1 G1 2 2 2 2 2 2
CA10
CA61
0.1U_0201_10V6K
10U_0603_10V6M
INT_SPK_R+ EMI@ LA7 1 2 BLM15PX330SN1D_2P INT_SPKR_R+ 2
EMI@ LA8 1 2 3 2
INT_SPK_R- INT_SPKR_R- 1
1
3 2
CA55
CA56
EMI@ LA9 1 2 BLM15PX330SN1D_2P SPK_DET# 4
2
5 4 2
<12> SPK_DET# 5
PESD5V0U2BT_SOT23-3
PESD5V0U2BT_SOT23-3
6 8
2
2
3
6 G2 +5V_RUN_AUDIO 2
@ESD@
@ESD@
ACES_50271-0060N-001 LA5 +VDDA_AVDD1
CONN@ 2 1 place close to pin40
@EMI@ CA22
@EMI@ CA23
@EMI@ CA19
@EMI@ CA24
Link ACES_50271-0060N-001 DONE BLM15PX600SN1D_2P
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
10U_0603_10V6M
0.1U_0201_10V6K
1
1
DA6
DA7
CA8
CA9
+3.3V_RUN
2
2
2
1
5/9 update
RA58
10K_0402_5% SPKR_R
Close to UA1 pin42~45 SPK_DET# UA1 2 1 1 2
SPKR <12>
2
AUD_PC_BEEP CA27 0.1U_0402_25V6
BEEP_R RA12 1K_0402_5%
34 2 1 1 2
6 PCBEEP BEEP <35>
CA28 1K_0402_5% 0.1U_0402_25V6 RA13
I2C DATA 30 RING2
7 MIC2-L/RING2 SLEEVE/RING2 please keep 40 mils trace width
Close to UA1 pin14 SPK_ D ET# I2C CLK 31 SLEEVE
PK23000 U O0 0 M1 15 MIC2-R/SLEEVE AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
HDA_BIT_CLK_R <12> HDA_SYNC_R SYNC LINE1_L HP_OUT_L
(FG-CPL0 8 8 0 0 0 ) Low 36 1 2
DMIC_CLK0 LINE1-L
PK23000 U O0 0 M2 14 LINE1_R CA43 10U_0603_10V6M
HP_OUT_R
<12> HDA_BIT_CLK_R
2
(PB2610KFG04 T-0 3 3 -9 MG1 ) Hig h BCLK 35 1 2

HDA_SDOUT_R LINE1-R
10P_0402_50V8J
@EMI@CA54
33_0402_5% 17 CA44
INT_SPK_L+ 10U_0603_10V6M
<12> HDA_SDOUT_R
1
RA17 SDATA-OUT 42
B 13 SPK-OUT-L+ B
@EMI@ INT_SPK_L-
DC DET/EPAD
10P_0402_50V8J
@EMI@ CA33
Place RA9 close toHDA_SDIN0_R

codec 43
1 1
1 2 16 SPK-OUT-L-
<12> HDA_SDIN0 SDATA-IN INT_SPK_R-
RA9 33_0402_5% 44
11 SPK-OUT-R-
I2S-MCLK INT_SPK_R+
45
2
10 SPK-OUT-R+
place close to UA1 pin5 HP_OUT_L AUD_HP_OUT_L
I2S-BCLK 27 2 1
HPOUT-L 5/10 update
HP_OUT_R 16.2_0402_1% RA7
AUD_HP_OUT_R
9 26 2 1
I2S-OUT HPOUT-R 16.2_0402_1% RA8
12 SPKR_R
I2S-LRCK
330P_0402_50V8J
330P_0402_50V8J
100P_0402_50V8J
8 1 1
I2S-IN
10K_0402_5%
1
1
CA74
CA73
@ CA72
@ RA51
1
RA62 1 2 100K_0402_5% I2S-EN/SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC-CLK-IN
4 2 2
<29> DMIC0
2
GPIO0/DMIC-DATA12
DMIC_CLK0 DMIC_CLK0_CODEC
1 2 5
2
<29> DMIC_CLK0 EMI@ RA14 22_0402_5% GPIO1/DMIC-CLK
1 2 PD# 2
CA31 1U_0603_10V6K PDB
+3.3V_RUN_AUDIO_DVDD RA18 1
AUD_SENSE_A 2 10K_0402_5% 48 +3.3V_RUN_AUDIO_DVDD
JD1
AUD_SENSE_B
1 2 47 BEEP_R
+3.3V_RUN_AUDIO JD2
0.1U_0402_25V6
RA61 100K_0402_1% Place CA70 close to codec
100P_0402_50V8J
1 2
CA70
10K_0402_5%
CA35 2.2U_0402_6.3V6M
1
@ CA62
@ RA45
1 2 38
RA44 100K_0402_5% VREF
2
1 2 39 1 2
+RTC_CELL
2
CA51 10U_0603_10V6M LDO1-CAP @ RA57 0_0402_5%
1 2 32 33 1 2
+5V_ALW
2
+3.3V_RUN_AUDIO CA25 10U_0603_10V6M MIC2-CAP 5VSTB/AUX MODE @ RA53 0_0402_5%
+VDDA_AVDD1
40
SLEEVE 2 1 +MIC2-VREFO-R 29 AVDD1
Place closely to Pin 48. RA6 2.2K_0402_5% MIC2-VREFO-R 20
+1.8V_RUN_AUDIO
100K_0402_1%
1
RING2 2 1 +MIC2-VREFO-L 28 CPVDD/AVDD2

MIC2-VREFO-L +3.3V_RUN_AUDIO_DVDD
RA5 2.2K_0402_5% 3 RF Request RF Request RF Request
RA59
DVDD
+3.3V_RUN_AUDIO_IO
18 +5V_RUN_AUDIO +1.8V_RUN_AUDIO +1.8V_RUN +3.3V_RUN_AUDIO
DVDD-IO
AUD_SENSE_A +5V_RUN_PVDD_L
2
1 2 25 41
CPVEE PVDD1
0.1U_0402_25V6
CA49 1U_0603_10V6K
200K_0402_1%
1
@ CA41
24 46
CBN PVDD2
Place CA29 close to Codec
RA60
RF@ CA69
2 1 23 49
2
CBP G
33P_0402_50V8J
CA29 1U_0603_10V6K
12P_0402_50V8J
RF@ CA63
68P_0402_50V8J
RF@ CA64
12P_0402_50V8J
RF@ CA65
68P_0402_50V8J
RF@ CA66
12P_0402_50V8J
RF@ CA67
68P_0402_50V8J
RF@ CA68
1 2 21 37 1 1 1 1 1 1 1
2
CA52 10U_0603_10V6M LDO2-CAP AVSS1

AUD_HP_NB_SENSE Add for solve
1 2 19 22
pop noise and LDO3-CAP AVSS2
CA53 10U_0603_10V6M
detect issue 2 2 2 2 2 2 2
ALC3254-VA3-CG_MQFN48_6X6
place at AGND and DGND plane

CLASS-D POWER DOWN CONTROL CIRCUIT
1 2
@ RA35 0_0402_5%
1 2 PJP19
680P_0402_50V7K
@ESD@ CA13
@ RA48 0_0402_5% 1 2 1
1 2
@ RA36 0_0402_5% PAD-OPEN1x1m
@ DA8 1 2
<35> NB_MUTE# 2
RB751S40T1G_SOD523-2 PD# 1 2
@ RA37 0_0402_5%
1 2 JHP1
<12> HDA_RST#_R 7
@ RA50 0_0402_5% RING2_R
RING2 ESD@ LA10 1 2 BLM15PX330SN1D_2P 4 GND
AUD_HP_OUT_L AUD_HP_OUT_L1 #4 G/M HP-Out-Right Nokia-MIC
HDA_Link is 3.3V,no need level shift circuit EMI@ LA15 1 2 BLM15PX330SN1D_2P 1 Normal
#1 L/R
Open HP-Out-Lef t iPhone-MIC
5
A #5 A
AUD_HP_NB_SENSE
6
AUD_HP_OUT_R AUD_HP_OUT_R1 #6 AGND
EMI@ LA16 1 2 BLM15PX330SN1D_2P 2
SLEEVE_R #2 R/L
SLEEVE ESD@ LA11 1 2 BLM15PX330SN1D_2P 3
PJP17 #3 M/G
Power sequence +5V_RUN_AUDIO(501us) > +3.3V_RUN_AUDIO(1204 us) > +1.8V_RUN 1 2 Global Headset
680P_0402_50V7K
SINGA_2SJ3095-085111F
+5V_RUN +5V_RUN_AUDIO
@ESD@CA1
@EMI@ CA2
@EMI@ CA3
@ESD@ CA4
ESD@ ESD@ ESD@ CONN@
Universal Jack
3
+5V_RUN_AUDIO PAD-OPEN1x2m DA1 DA2 DA3
2.5A Link 2SJ3095-085111F DONE
AZ5123-02S.R7G_SOT23-3
AZ5123-02S.R7G_SOT23-3
330P_0402_50V8J
330P_0402_50V8J
680P_0402_50V7K
680P_0402_50V7K
@ESD@ CA12
2 1 1 1 1
PESD5V0U2BT_SOT23-3
Reserve for support D3 cold
1
PJP18
@ PJP15 1 2
+3.3V_RUN +3.3V_RUN_AUDIO 1 2 2 2 2
PAD-OPEN1x1m
+5V_RUN PAD-OPEN1x1m
500mA
@ UZ5 +5V_RUN_AUDIO_UZ5
2
1
1 14 1 2
2 VIN1 VOUT1 13 @ CZ125 0.1U_0201_10V6K
VIN1 VOUT1
3 12 1 2
<12> AUD_PWR_EN ON1 CT1 220P_0402_50V7K
@ CZ126
4 11
+5V_ALW VBIAS GND
5 10 1 2
ON2 CT2 @ CZ127 1000P_0402_50V7K
+3.3V_RUN
6
VIN2 VOUT2
9 +3.3V_RUN_AUDIO_UZ5 @ PJP16 DELL CONFIDENTIAL/PROPRIETARY
7 8 1 2
VIN2 VOUT2 +3.3V_RUN_AUDIO
15
GPAD PAD-OPEN1x1m
EM5209VF_SON14_2X3 1 2
@ CZ128 0.1U_0201_10V6K
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Codec ALC3253
LA-F391P
2 1
5 4 3 2 1
+RTC_CELL_VBAT GPIO2 2 3 GPIO2 2 4 GPIO2 2 7 GPIO0 1 6 GPIO0 5 6 GPIO0 5 5

For BR UMA +3.3V_ALW
1 2 eSPI NA NA * PR IM_ PWR GD NA NA PCH_ R SMR ST# UPD1_SMBDAT

+RTC_CELL 1 2
@ RE32 0_0402_5% LPC SH D _ IO0 SH D _ IO1 SH D _ IO2 SH D _ IO3 SHD _ C L K SH D _ C S#
RE302 2.2K_0402_5%
0.1U_0201_10V6K
* For Version B IC UPD1_SMBCLK
1 1 2
CE11
UPD1_SMBINT# RE303 2.2K_0402_5%
+3.3V_ALW_UE1 GPIO2 0 4 GPIO0 11 GPIO1 0 0 GPIO0 2 1 GPIO0 6 7 1 2
eSPI NA NA NA SIO_ R C IN # NA
2 RE91 100K_0402_5%
0.1U_0201_10V6K
1U_0402_6.3V6K
0.1U_0201_10V6K
PJP22 LPC RSMR ST# SIO_EXT_ SMI# SIO_EXT_ SC I# LPC PD # CL KR U N # UPD2_SMBINT#
1 2
1 2 1 1
+3.3V_ALW PBAT_CHARGER_SMBDATRE92 100K_0402_5%
1
CE13
CE14
CE23
1 2
10U_0603_6.3V6M
PAD-OPEN1x1m
PBAT_CHARGER_SMBCLKRE37 2.2K_0402_5%
1
1 2
2
2 2
CE16
GPU_SMDAT RE43 2.2K_0402_5%
1 2
2
UE1 TYPEC_ID
F2 GPU_SMCLK RE524 2.2K_0402_5%
GPIO033/RC_ID0 SYSTEM_ID TYPEC_ID <36> 1 2
A2 J10 BOARD_ID SIO_SLP_SUS#_R
SYSTEM_ID <36> RE525 1
+3.3V_ALW_UE1 VBAT GPIO034/RC_ID1/SPI0_CLK J13 UPD2_SMBDAT 2 2.2K_0402_5%
D GPIO036/RC_ID2/SPI0_MISO BOARD_ID <36> D
B7 E7 UPD2_SMBCLK NDS3@ RE561 100K_0402_5%
2 1 VTR_ANALOG GPIO003/SMB00_DATA/SPI0_CS# D7 RPE12
+3.3V_ALW_UE1 GPIO004/SMB00_CLK/SPI0_MOSI
0.1U_0201_10V6K
0.1U_0201_10V6K
22U_0603_6.3V6M
0.1U_0201_10V6K
100_0402_1% RE314 K2 1 8
VREF_ADC G3 2 7
1 1 1 1 +3.3V_EC_PLL
GPIO057/VCC_PWRGD GPS_DISABLE# RUNPWROK <14> UPD2_SMBCLK
CE19
CE20
@ CE17
F1 H5 UPD2_SMBDAT 3 6
VTR_PLL GPIO060/KBRST/48MHZ_OUT GPS_DISABLE# <33>
CE18
G11 4 5
H1 GPIO104/UART0_TX G12 HOST_DEBUG_TX <33,36>
2 2 2 2 VTR_REG GPIO105/UART0_RX ME_FWP <12>
B13 UPD1_SMBINT# 2.2K_0804_8P4R_5%
G8 GPIO127/A20M/UART0_CTS# F10 ME_SUS_PWR_ACK <11>
+VSS_PLL VTR1 GPIO225/UART0_RTS# UPD1_SMBINT# <26>
M9 PCIE_WAKE#_R NGFF_CONFIG_1 RPE9
+3.3V_ALW_UE1 VTR2
close to pin G8/M9 N5 N13 NGFF_CONFIG_2 1 8
+3.3V_ALW_UE1 +1.8V_3.3V_ALW_VTR3 VTR3 GPIO025/TIN0/nEM_INT/UART_CLK N12 PCIE_WAKE#_R <36>
PCH_DPWROK_EC NGFF_CONFIG_0 2 7
GPIO026/TIN1 M11 SIO_SLP_S4# <11,17,52,55>
0.1U_0201_10V6K
1 @DS3@RE536 1 2 0_0402_5% RUN_ON_EC F8 NGFF_CONFIG_3 3 6

<11> PCH_DPWROK E8 GPIO020 GPIO027/TIN2 H9 SIO_SLP_A# <11>
4 5
RF Request <36> RUN_ON_EC GPIO045 GPIO030/TIN3 SIO_SLP_LAN# <11,47>
CE15
BT_RADIO_DIS# M12 VGA_IDENTIFY

+3.3V_ALW <9> SIO_EXT_WAKE# C2 GPIO120 L9 100K_0804_8P4R_5%
2 <33> BT_RADIO_DIS# F9 GPIO166 GPIO017/GPTP-IN5 M10
SIO_SLP_SUS#_R NGFF_CONFIG_1 <33> USB_PWR_EN2# RPE11
1 <50,59>
2 PBAT_PRES# GPIO175 GPIO151/ICT4 N9
PCH_ALW_ON N4 USB_POWERSHARE_EN# 1 8
<11> SIO_SLP_SUS# GPIO230 GPIO152/GPTP-OUT3 NGFF_CONFIG_0 <33>
DS3@ RE349 43K_0402_1% M8 USB_PWR_EN1# 2 7
<47> PCH_ALW_ON K8 GPIO231 C11 3 6
<11> AC_PRESENT GPIO233 GPIO156/LED0 D10 BREATH_LED# <46> USB_POWERSHARE_VBUS_EN
Close to pin H1 4 5
E11 GPIO157/LED1 D11 BAT1_LED# <46>
<8> SML1_SMBDATA GPIO007/SMB03_DATA/PS2_CLK0B GPIO153/LED2 E1 BAT2_LED# <46>
WWAN_WAKE# D8 100K_0804_8P4R_5%
<8> SML1_SMBCLK GPIO010/SMB03_CLK/PS2_DAT0B GPIO226/LED3 LCD_VCC_TEST_EN <29> AC_DIS
12P_0402_50V8J
RF@ CE59
68P_0402_50V8J
RF@ CE60
1 1 M13
<33> WWAN_WAKE# GPIO110/PS2_CLK2 1 2
WLAN_WIGIG60GHZ_DIS# K12 E5
<11> SUSACK# GPIO111/PS2_DAT2 GPIO005/SMB01_DATA/GPTP-OUT4 B3 USH_EXPANDER_SMBDAT <38> GPS_DISABLE# @ RE83 100K_0402_5%
L13 VCCDSW_EN VCCDSW_EN
<33> WLAN_WIGIG60GHZ_DIS# GPIO112/PS2_CLK1A GPIO006/SMB01_CLK/GPTP-OUT7 M7 USH_EXPANDER_SMBCLK <38> 1 2
VCCST_PWRGD_EC K11 DGPU_PWROK
2 2 <11,14> SIO_PWRBTN# GPIO113/PS2_DAT1A GPIO012/SMB07_DATA/TOUT3 M4 VCCDSW_EN <11> WLAN_WIGIG60GHZ_DIS#RE12 100K_0402_5%
0.1U_0402_25V6
1 2 K10 PBAT_CHARGER_SMBDAT
<11,14,36> VCCST_PWRGD N11 GPIO114/PS2_CLK0A/nEC_SCI GPIO013/SMB07_CLK/TOUT2 M3 PAD~D @ T147 1 2
@ RE308 0_0402_5% PBAT_CHARGER_SMBCLK
<36> LID_CL_SIO# GPIO115/PS2_DAT0A GPIO130/SMB10_DATA/TOUT1 N2 PBAT_CHARGER_SMBDAT <50,59> RE8 100K_0402_5%
@ CE66
1 2 E10 WWAN_WAKE#
<45> CLK_TP_SIO_I2C_DAT 1 2
1
<47> SLP_WLAN#_GATE @ RE552 0_0402_5% C12 GPIO154/SMB02_DATA/PS2_CLK1B GPIO131/SMB10_CLK/TOUT0 N10 PBAT_CHARGER_SMBCLK <50,59>
<45> DAT_TP_SIO_I2C_CLK GPIO155/SMB02_CLK/PS2_DAT1B GPIO132/SMB06_DATA A12 LED_MASK# NGFF_CONFIG_2 <33> RE38 10K_0402_5%
LED_MASK#
JTAG_TDI GPIO140/SMB06_CLK/ICT5 B6 GPU_SMDAT LED_MASK# <30,46> 1 2
JTAG_TDO E9 GPU_SMCLK RE21 10K_0402_5%
2
<36> JTAG_TDI F6 GPIO145/SMB09_DATA/JTAG_TDI GPIO141/SMB05_DATA/SPI1_CLK/UART0_DCD#F7
<36> JTAG_TDO JTAG_CLK GPIO146/SMB09_CLK/JTAG_TDO GPIO142/SMB05_CLK/SPI1_MOSI/UART0_DSR#B4 UPD1_SMBDAT THERMTRIP1# 1 2
JTAG_TMS C8 UPD1_SMBCLK
<36> JTAG_CLK GPIO147/SMB08_DATA/JTAG_CLK GPIO143/SMB04_DATA/SPI1_MISO/UART0_DTR#C3 UPD1_SMBDAT <26> PCIE_WAKE#_R RE301 10K_0402_5%
JTAG_RST# C5
<36> JTAG_TMS GPIO150/SMB08_CLK/JTAG_TMS GPIO144/SMB04_CLK/SPI1_CS#/UART0_RI# UPD1_SMBCLK <26> 1 2
G13 I_BATT_R
JTAG_RST# J4 1 2 300_0402_5% GPU_PWR_LEVEL RE35 10K_0402_5%
PJP20 I_SYS_R RE64
GPIO200/ADC00 J5 I_BATT <59> 1 2
1 2 E3 RE312 1 2 300_0402_5%
+1.8V_PRIM +1.8V_3.3V_ALW_VTR3 <36> TACH_FAN1 GPIO051 D1 GPIO050/FAN_TACH0/GTACH0 GPIO201/ADC01 J6 GPIO202
I_SYS <56,59>
BC_DAT_ECE1117 RE5 10K_0402_5%
1 T141 @ PAD~D LCD_TST GPIO051/FAN_TACH1/GTACH1 GPIO202/ADC02 G2 PAD~D @ T262 1 2
PAD-OPEN1x1m M2 @ RE318
USH_PWR_STATE# 1 2 0_0402_5%
<29> LCD_TST L10 GPIO052/FAN_TACH2/LRESET# GPIO203/ADC03 H2 TOUCHPAD_INTR# <12,45> WWAN_RADIO_DIS# RE365 100K_0402_5%
C CE22 <36> PWM_FAN1 USB_POWERSHARE_VBUS_EN 1 2 C
0.1U_0201_10V6K GPIO054 L11 GPIO053/PWM0/GPWM0 GPIO204/ADC04 J2 USH_PWR_STATE# <38>
T142 @ PAD~D PCH_RSMRST# GPIO054/PWM1/GPWM1 GPIO205/ADC05 J3 USB_POWERSHARE_EN# USB_POWERSHARE_VBUS_EN <43> RE10 100K_0402_5%
2 M5 BT_RADIO_DIS#
<45> PCH_RSMRST# USB_PWR_EN1# USB_POWERSHARE_EN# <43> 1 2
CE21 J8 GPIO055/PWM2/SHD_CS#/(RSMRST#) GPIO206/ADC06 K3
@
1 <50> PS_ID GPIO056/PWM3/SHD_CLK GPIO207/ADC07 D3 USB_PWR_EN1# <44> RE11 100K_0402_5%
PJP21 0.1U_0201_10V6K TBT_RESET_N_EC_R N1
<29> BIA_PWM_EC GPIO001/PWM4 GPIO210/ADC08 D2 AUX_EN_WOWL <47>
1 2 L8
+3.3V_ALW GPIO002/PWM5 GPIO211/ADC09 E2 LOM_CABLE_DETECT# <30>
Close to pin N5 N6 USB_PWR_EN2#
2 <50,59,60> HW_ACAVIN_NB J9 GPIO014/PWM6/GPTP-IN6 GPIO212/ADC10 G5 BC_INT#_ECE1117 <45> +RTC_CELL
PAD-OPEN1x1m UPD2_SMBINT#
<29> PANEL_BKEN_EC BEEP H11 GPIO015/PWM7 GPIO213/ADC11 F5
<34> BEEP GPIO035/PWM8/CTOUT1 GPIO214/ADC12 K4 DCIN1_EN VCI_IN1#
AC_DIS D9 1 2
<11,47> SIO_SLP_WLAN# H12 GPIO133/PWM9 GPIO215/ADC13 L1 DCIN1_EN <60>
<59> AC_DIS VCI_IN2# RE507 100K_0402_5%
G10 GPIO134/PWM10/UART1_RTS# GPIO216/ADC14 L3 PCH_PCIE_WAKE# <11,36>
1 2
<38> BCM5882_ALERT# H10 GPIO135/UART1_CTS# GPIO217/ADC15 LAN_WAKE# <11,30>
MSCLK CV2_ON_R POA_WAKE# RE508 100K_0402_5%
<36> MSCLK G9 GPIO170/TFDP_CLK/UART1_TX H8
+3.3V_ALW MSDATA 3.3V_TS_EN RE539 1 2 100_0402_5% 1 2
<36> MSDATA GPIO171/TFDP_DATA/UART1_RX GPIO222/SER_IRQ J7 CV2_ON <38>
MASK_SATA_LED# RE324 100K_0402_5%
A4 GPIO223/SHD_IO0 L6 3.3V_TS_EN <29>
LOM_CABLE_DETECT# <34> NB_MUTE# EN_INVPWR GPIO022/GPTP-IN0 GPIO224/GPTP-IN4/SHD_IO1 L7 1.8V_PRIM_PWRGD MASK_SATA_LED# <46>
2 1 RESET_IN# B2 VBUS1_ECOK
<29> EN_INVPWR C1 GPIO023/GPTP-IN1 GPIO227/SHD_IO2 M6
@ RE505 100K_0402_5% USH_DET# IMVP_VR_ON_EC I_BATT_R
2 1 N7 GPIO024/nRESETI GPIO016/GPTP-IN7/SHD_IO3/ICT3 VBUS1_ECOK <60> 1 2 2200P_0402_50V7K
CE3
@ RE526 10K_0402_5% BCM5882_ALERT# <36> IMVP_VR_ON_EC K9 GPIO031/GPTP-OUT1 D6
<11,36> SIO_SLP_S3# GPIO032/GPTP-OUT0 BGPO0 C7 EC_FPM_EN <38> I_SYS_R
2 1 N8 CE4 1 2 2200P_0402_50V7K
<11> SIO_SLP_S5# GPI0040/GPTP-OUT2 GPIO164/VCI_OVRD_IN A5 ACAV_IN <59>
RE532 4.7K_0402_5% VBUS3_ECOK RE59 close
+PECI_VREF to UE2 at least 250mils
VCI_OUT D5 ALWON <51>
F13 VCI_IN1# 2 1
T264 @ PAD~D GPIO121/PVT_IO0 GPIO163/VCI_IN0# B5 POWER_SW_IN# <36> +1.0V_VCCST
E13 VCI_IN2# 0_0402_5% RE59 @
<50,60> AC_DISC# GPIO124/GPTP-OUT6/PVT_CS# GPIO162/VCI_IN1# D4
0.1U_0201_10V6K
GPU_PWR_LEVEL C13 POA_WAKE# PCH_RSMRST#
<38> USH_DET# E12 GPIO125/GPTP-OUT5/PVT_CLK GPIO161/VCI_IN2# E4 1 2
POA_WAKE# <38>
1
GPIO126/PVT_IO3 GPIO000/VCI_IN3#
CE25
RTCRST_ON SYS_PWROK RE342 10K_0402_5%
RPE10 CV2_ON_R WWAN_RADIO_DIS# F11 1 2
8 1 F12 GPIO122/BCM0_DAT/PVT_IO1 C6 RE56 10K_0402_5%
IMVP_VR_ON_EC <33> WWAN_RADIO_DIS# I_SYS_R
2
7 2 D12 GPIO123/BCM0_CLK/PVT_IO2 GPIO165/32KHZ_IN/CTOUT0 3.3V_WWAN_EN <47> 1 2
PCH_ALW_ON <45> BC_DAT_ECE1117 GPIO046/BCM1_DAT 32KHZ_OUT
@
6 3 RUN_ON_EC D13 F3 @ CE54 1 2 10P_0402_50V8J LCD_TST RE313 10K_0402_5%
<45> BC_CLK_ECE1117 GPIO047/BCM1_CLK GPIO221/GPTP-IN3/32KHZ_OUT
5 4 1 2
F4 +PECI_VREF EN_INVPWR RE20 100K_0402_5%
<33> NGFF_CONFIG_3 GPIO041/SYS_SHDN#
100K_0804_8P4R_5% @ RE57 2 1 1K_0402_5% B1 J11 PECI_EC_R 1 2
+3.3V_ALW2 SYSPWR_PRES GPIO044/VREF_VTT K13
TBT_RESET_N_EC_R GPIO011
VBUS2_ECOK K7 M3042_PCIE#_SATA RE60 1 2 43_0402_5% RE55 100K_0402_5%
T143 @ PAD~D PECI_EC <12>
1
1 2 N3 GPIO011/nSMI GPIO042/PECI_DAT/SB-TSI_DAT J12

<50,60> VBUS2_ECOK GPIO021/LPCPD# GPIO043/SB-TSI_CLK A8 REM_DIODE1_N M3042_PCIE#_SATA REM_DIODE1_N
<10>
100K_0402_5%
@ RE95 100K_0402_5% K6 REM_DIODE1_P CE24 1 2 2200P_0402_50V7K REM_DIODE1_P

<8,36> ESPI_RESET# GPIO061/LPCPD#/ESPI_RESET# DN1_DP1A A7 REM_DIODE1_N <36>
RE58
H7 REM_DIODE2_N REM_DIODE2_N
<8> ESPI_ALERT# K1 GPIO063/SER_IRQ/ESPI_ALERT# DP1_DN1A A10 1 2 2200P_0402_50V7K REM_DIODE1_P <36> +3.3V_RUN
REM_DIODE2_P CE26 REM_DIODE2_P
<36> PCH_PLTRST#_5105 GPIO064/LRESET# DN2_DP2A A9 REM_DIODE2_N <36>
G7
2
<8,36> ESPI_CLK_5105 H6 GPIO065/PCI_CLK/ESPI_CLK DP2_DN2A B9 REM_DIODE2_P <36>

<8,36> ESPI_CS# K5 GPIO066/LFRAME#/ESPI_CS# DN3_DP3A B8
<8,36> ESPI_IO0 GPIO070/LAD0/ESPI_IO0 DP3_DN3A A11 REM_DIODE4_N REM_DIODE4_N 3.3V_TS_EN
B L4 REM_DIODE4_P CE27 1 2 2200P_0402_50V7K REM_DIODE4_P 1 2 B
<8,36> ESPI_IO1 G6 GPIO071/LAD1/ESPI_IO1 DN4_DP4A B10 REM_DIODE4_N <36>
+VR_CAP @ RE547 100K_0402_5%
<8,36> ESPI_IO2 L5 GPIO072/LAD2/ESPI_IO2 DP4_DN4A C10 REM_DIODE4_P <36>
<8,36> ESPI_IO3 ENABLE_DS# GPIO073/LAD3/ESPI_IO3 VIN C9 VSET_5105
L2
GPIO067/CLKRUN# VSET B11 VSET_5105 <36> +3.3V_ALW
SYS_PWROK GPIO100
RESET_OUT M1
T144 @ PAD~D GPIO100/nEC_SCI VCP H3 I_ADP <59>
VSS_ANALOG
@ RE548 1 2 0_0402_5% DCIN2_EN G4 THERMTRIP2#
<11,14> SYS_PWROK GPIO106/PWROK GPIO103/THERMTRIP2# B12 THERMTRIP2# <36>
L12 THERMTRIP1#
PROCHOT#_R1 VGA_IDENTIFY
<50> DCIN2_EN GPIO107/nSMI THERMTRIP1# H13
VSS_ADC
1 2 1 2
VSS_PLL
MEC_XTAL1
VR_CAP
A1 GPIO160/PWM11/PROCHOT# PROCHOT# <12,56,59>
+3.3V_ALW MEC_XTAL2_R RE288 100_0402_5% VGA_IDENTIFY RE84 100K_0402_5%
XTAL1
VSS1
VSS2
VSS3
A3 1 2
100K_0402_5%
XTAL2 @ RE85 100K_0402_5%

2
RE63
+1.8V_3.3V_ALW_VTR3 MEC5105_WFBGA169_11X11
A6
A13
E6
H4
J1
C4
G1
1U_0402_6.3V6K
+VR_CAP
1
1
@
+VSS_PLL
RE549 VGA_IDENTIFY
JTAG_RST#
100K_0402_5%
Discrete 0
1
+RTC_CELL_PCH +RTC_CELL
UMA 1
2
Deep Sleep support

1
ENABLE_DS# QE15
CE31
2
1U_0402_6.3V6K
LP2301ALT1G_SOT23-3
1
1
JTAG1 @
@SHORT PADS~D
100_0402_1%
non Deep Sleep 1

1
@ RE65
1 3
S
1
CE30
Deep Sleep 0
1U_0402_6.3V6K
10K_0402_5%
RE550 +RTC_CELL_PCH +RTC_CELL
2
1
100K_0402_5%
G
2
2
1
RE546
+3.3V_RUN
CE63
2
1 2
2
@RE551 0_0402_5%
2
2
+3.3V_ALW
10K_0402_5%
DE2
2
2 1
RE67
For MEC5105 Rev.A:Pop RE361,Depop RE360,RE362 @ RE94

For MEC5105 Rev.B/C:Depop RE361,Pop RE360,RE362 RB751S40T1G_SOD523-2 1 2
For WDT issue fix options&assessment:Pop RE361, Depop RE362 75_0402_5% PCH_RTCRST# <11>
100K_0402_5%
2
1
RUNPWROK D RE543 D
RESET_IN# RTCRST_ON_R RTCRST_ON RTCRST_ON
@ RE361 1 2 49.9K_0402_1% QE17 2 1 2 1 2 2 @ QE12

1.8V_PRIM_PWRGD <55>
RE68
MEC_XTAL2_R For EMI request L2N7002WT1G_SC-70-3 G RE565 0_0402_5% G L2N7002WT1G_SC-70-3
1
0.1U_0402_25V6
ESPI_CLK_5105 RE362 1 2 100K_0402_5% S 1M_0402_5% S
+3.3V_ALW
3
3
22P_0402_50V8J
100K_0402_5%
@ RE93
1
2
QE2B
@ CE64
1
1
RE541
A 100K_0201_5% A
RUN_ON#
33_0402_5%
1
CE65
5
@EMI@
2
@ RE290 <47> RUN_ON#
32 KHz Clock
RE350
2
0_0402_5%
4
1
6
2
QE2A
YE1
33P_0402_50V8J
MEC_XTAL1 MEC_XTAL2
1 2 2
@EMI@
8/28 schematic review

<17,36,47,54> RUN_ON
1
10P_0402_50V8J
10P_0402_50V8J
CE57
32.768KHZ_9PF_X1A000141000200
2
1

CE28
CE29
2
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, EC MEC5105
LA-F391P
5 4 3 2 1
5 4 3 2 1
+1.8V_3.3V_ALW_VTR3
+3.3V_ALW For BR UMA
2
UE6
RE340
1 5 10K_0402_5%
NC VCC
2
1
<11> PCH_PLTRST#_EC A 4
3 Y PCH_PLTRST#_5105 <35>
GND
74AUP1G07GW_TSSOP5
+RTC_CELL
PCIE_WAKE# <33,40>
6/8 Change to SA00007WE00 DII
1
100K_0402_5%
RE31
@ CE10
1 2 2 1 1 2
<35> PCIE_WAKE#_R PCH_PCIE_WAKE# <11,35>
0_0402_5% RE275 @ 0_0402_5% @ RE274
1U_0402_6.3V6K
2
<35> POWER_SW_IN# 1 2 Stuff RE275 and no stuff RE274 keep E5 design
POWER_SW#_MB <11,46>
ESPI LPC RE33 1K_0402_5% Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)
PAGE
2.2U_0402_6.3V6M
D D
1
+3.3V_RUN
CE12
JESPI 2 1
2
1 0_0402_5% @ RE304
RC8_15ohm
1
2
3
4
2
3
4
5
ESPI_IO0
ESPI_IO1
ESPI_IO2
<8,35>
<8,35>
<8,35>
8 RC25_10K +3.3V_ALW
@ CE53
5
RC13/RC27_8.2K
6 +3.3V_ALW 1 2
6 ESPI_IO3 <8,35>
100K_0402_5%
7 PCH_PLTRST#_EC UE4 +3.3V_ALW
ESPI_CS# <8,35>
1
7
RE25
8 LPC@ RE375 1 2 0_0402_5% ESPI_RESET# 0.1U_0402_25V6K
5
11 8 9 @ RE560 1 20_0402_5% IMVP_VR_ON_EC 1 5
GND 9 ESPI_RESET# <8,35> NC VCC
12 10 1 IMVP_VR_ON
P
GND 10 ESPI_CLK_5105 <8,35> <35> IMVP_VR_ON_EC B
SIO_SLP_S3# 4 2
JXT_FP241AH-010GAAM LID_CL_SIO# RE26 2 O A 4
<11,35,36> SIO_SLP_S3#
G
2 1 UE3 A 3 Y VCCST_PWRGD <11,14,35>
CONN@ <35> LID_CL_SIO# LID_CL# <46> GND
18 RC212_0ohm RC211_0ohm
.047U_0402_16V7K
TC7SH08FU_SSOP5~D
3
10_0402_5% 74AUP1G07GW_TSSOP5
CE8
J
X
T
_
F
P
2
4
1
A
H
-
0
1
0
G
A
A
M
L
I
N
K
D
O
N
E
0603 0603
2
IMVP_VR_ON <56>
1 2
0_0402_5% @ RE280
6/8 Change to SA00007WE00 DII
RF Request
RUN_ON_EC
+3.3V_ALW 2 1
<35> RUN_ON_EC RUN_ON <17,35,47,54>
LPC 80Port Debug LPC ESPI
RE337,RE338 1
0_0402_5% @ RE292
68P_0402_50V8J
1 +3.3V_RUN +3.3V_RUN +3.3V_ALW
RE339,RE340, @ CE52
RF@ CE61
1 2
31
2
2 +3.3V_RUN +3.3V_RUN 0.1U_0402_25V6K
RE341
5
1
3 LPC_LAD0 ESPI_IO0
P
B 4
2 O
G
0_ohm UE5 A
4 LPC_LAD1 ESPI_IO1 TC7SH08FU_SSOP5~D
3
5 LPC_LAD2 ESPI_IO2
6 LPC_LAD3 ESPI_IO3 +3.3V_ALW
RE2 / RE3
+3.3V_ALW
+3.3V_ALW
7 LPC_FRAME# ESPI_CS#
1
32
2
0_ohm
C RE300 C
RE343 RE79 130K_0402_5%
8 PCH_PLTRST# NA
240K_0402_5% 4.3K_0402_5%
SYSTEM_ID
2
9 GND GND BOARD_ID
1
<35> SYSTEM_ID
<35> TYPEC_ID <35> BOARD_ID
1
1
1
10 LPC_CLOCK ESPI_CLK CE47
CE62 CE40 4700P_0402_25V7K
2
4700P_0402_25V7K 4700P_0402_25V7K
2
RE343 CE62 REV RE79 CE40 REV RE300 CE47 PANEL SIZE
* 240K 4700p Single Port ACE w/o AR 240K 4700p X00 240K 4700p 11"
130K 4700p Single Port ACE w/AR 130K 4700p X01 * 130K 4700p 12"
62K 4700p Dual Port ACE w/o AR 62K 4700p X02 62K 4700p 13"
33K 4700p Dual Port ACE w/AR 33K 4700p X03 33K 4700p 14"
8.2K 4700p Dual Port ACE (w/AR +w/o AR) 8.2K 4700p reserved 8.2K 4700p 15"
4.3K 4700p * 4.3K 4700p A00 4.3K 4700p 17"
2K 4700p 2K 4700p 2K 4700p 15P
1K 4700p 1K 4700p 1K 4700p
PD_ACE_DET# rise t i me i s meas ur ed fr o m 5 %~68 %. BOARD_ID rise t i me i s meas ur ed fr o m 5 %~68 %. SYSTEM_ID rise t i me i s meas ur ed fr o m 5 %~68 %.
VSET_5105
VSET_5105 <35>
0.1U_0402_25V6
1
1.58K_0402_1%
1
CE38
RE77
2
2
+3.3V_ALW
Rest=1.58K , Tp=96 degree???
8
7
6
5
10K_8P4R_5%
10_0402_1%
RE71
B B
RPE7
1
Link 50271-0040N-001 DONE
10K_0402_5%
10K_0402_5%
10K_0402_5%
100K_0402_5%
@ RE75
2
1
2
3
4
JFAN1
RE72
RE73
RE74
JDEG1 +EC_DEBUG_VCC 1
1 PWM_FAN1
JTAG_TDI 1 2 TACH_FAN1
1 2 JTAG_TMS 2 PWM_FAN1 <35>
JTAG_TDI <35> 3
2
2 3 3 TACH_FAN1 <35>
JTAG_CLK JTAG_TMS <35> +3.3V_RUN 4
3 4 JTAG_TDO 4 +5V_RUN
4 5 JTAG_CLK <35>
RE86
10U_0603_6.3V6M
5 JTAG_TDO <35> 5
6 MSCLK 10K_0402_5%
1
PWM_FAN1
GND1 6
6 7 1 2
1
MSDATA
HOST_DEBUG_TX 1 2 GND2 @ DE1
7 8 DEBUG_TX
CE32
8 RE48 10K_0402_5%
TACH_FAN1 ACES_50271-0040N-001 BZV55-B5V6_SOD80C2
11 9 1 2
GND 9 CONN@
2
12 10
GND 10 RE51 10K_0402_5%
2
1 2
<9> SBIOS_TX
JXT_FP241AH-010GAAM @ RE306
CONN@ 0_0402_5%
HOST_DEBUG_TX <33,35>
MSDATA <35>
MSCLK <35>
J
X
T
_
F
P
2
4
1
A
H
-
0
1
0
G
A
A
M
L
I
N
K
1
D
O
N
2
E
@ RE30 0_0402_5% Thermal diode mapping
5085 Channel Locat i on
Place under CPU
DP1/DN1 Place CE35 close to the QE3 as possible
CPU (QE3)
REM_DIODE1_P <35>
100P_0402_50V8J
DP2/DN2 WiGig (QE5)
1
C
@ CE35
2
DN2a/DP2a DDR (QE7) B
1
E QE3
3
MMST3904-7-F_SOT323-3
DP3/DN3 NA REM_DIODE1_N <35>
DP2/DN2 for WiGig on QE5, place QE5 close

DP4/DN4 CPU VR (QE6) to WiGig and CE37 close to QE5
DP4/DN4 for Skin on

QE6, place QE6 close to DN2a/DP2a for DDR on QE7, place QE7 close
RE69
Vcore VR choke. to DDR and CE46 close to QE7
0.1U_0402_25V6
1 2
+1.0VS_VCCIO +3.3V_ALW THERMTRIP2# <35>
REM_DIODE4_P <35> REM_DIODE2_P <35>
MMST3904-7-F_SOT323-3
SIO_SLP_S3# <11,35,36> 8.2K_0402_5%
1
MMST3904-7-F_SOT323-3
CE36
100P_0402_50V8J
@ QE11
2
1
100P_0402_50V8J
100P_0402_50V8J
@ CE37
E
G
QE7
1
1
@ CE46
C C 2
B 2
2
QE4
@ CE39
A 1 3 1 2 2 2 B A
2
C
RE70 2.2K_0402_5% B B E QE5
D
3
+1.0V_VCCST E E QE6 MMST3904-7-F_SOT323-3
3
L2N7002WT1G_SC-70-3 MMST3904-7-F_SOT323-3
REM_DIODE2_N <35>
1 2
<12,20,21> H_THERMTRIP# REM_DIODE4_N <35>
@ RE90 0_0402_5%
Tit l e
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT MEC5105 Support
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Si ze Document Number Re v
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.2
5 4 3 2 1
5 4 3 2 1
For NUVOTON TPM
@ RZ367 1 2 0_0402_5%
+3.3V_M_TPM
+UZ12_TPM place CZ50, CZ75 as close as UZ12.8
@ RZ89 1 2 0_0402_5%
+3.3V_RUN
10U_0402_6.3V6M
0.1U_0201_10V6K
D D
1 1
CZ75
CZ50
+3.3V_ALW 2 2
@ RZ369 1 2 0_0402_5%
+3.3V_ALW_PCH +3.3V_ALW
@ RZ368 1 2 0_0402_5%
+3.3V_M_TPM
2
PJP391
TPM_PIRQ#
1 2 PAD-OPEN1x1m
RZ69 10K_0402_5%
1
+3.3V_ALW_UZ12
0.1U_0201_10V6K
10U_0603_10V6M
1 1 place CZ51,CZ52 as close as UZ12.1
+3.3V_RUN
CZ51
CZ52
1
2 2
@ RZ362
10K_0402_5%
UZ12
1
TPM_GPIO0
2
1 2 29 VSB 1 2
<11,17,54> SIO_SLP_S0# GPIO0/SDA/XOR_OUT +UZ12_TPM +3.3V_M_TPM
@750@ RZ112 0_0402_5% 30 8 650@ RZ366 0_0402_5%
TPM_LPM# GPIO1/SCL VDD 14 +UZ12_VHIO
1 2 3 1 2
C GPIO2/GPX VHIO 22 +3.3V_RUN C
650@ RZ363 0_0402_5% 6 @750@ RZ365 0_0402_5%
GPIO3/BADD VHIO
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0603_10V6M
PCH_SPI_D1_2_R
RZ58 1 2 33_0402_5% 24 2 1 1 1
<8> PCH_SPI_D1_R1 PCH_SPI_D0_2_R LAD0/MISO NC 7
RZ59 1 2 33_0402_5% 21
<8> PCH_SPI_D0_R1 LAD1/MOSI NC 10
CZ54
CZ53
CZ55
18
<9> TPM_PIRQ# 15 LAD2/SPI_IRQ# NC 11
LAD3 NC 25 2 2 2
PCH_SPI_CLK_2_R NC 26
EMI@ RZ60 1 2 33_0402_5%
PCH_SPI_CS#2_R
19
<8> PCH_SPI_CLK_R1 @ RZ61 1 2 0_0402_5% 20 LCKL/SCLK NC 31
<8> PCH_SPI_CS#2 17 LFRAME#/SCS# NC
<11> PLTRST_TPM# 27 LRESET#/SPI_RST#/SRESET# 9
TPM_GPIO4 SERIRQ GND 16
13
T283 @ PAD~D CLKRUN#/GPIO4/SINT# GND 23
28 CZ53,CZ55 as close as UZ12.14
LPCPD# GND 32
1
10K_0402_5%
@ CZ54 as close as UZ12.22

GND 33
RZ62
4
5 PP PGND 12
TEST Reserved
NPCT750JAAYX_QFN32_5X5
2
9/13: change to MP sample : SA0000AQ220
Pop Depop Comment

VDD - V_RUN Power
NPCT65x RZ89, RZ366, RZ62, RZ363 RZ365, RZ367, RZ112 VHIO - V_SPI Power
Option1 (recommended)
B
NPCT75x RZ89, RZ365, RZ112 RZ367, RZ366, RZ62, RZ363 VDD and VHIO - V_RUN power B
Option2 (for Z1 sample [early sample])

NPCT75x RZ367, RZ366 RZ89, RZ365, RZ62 VDD and VHIO - V_SPI power
PCH_SPI_CLK_2_R
RF Request RF Request
+3.3V_ALW +3.3V_M_TPM
33_0402_5%
2
@EMI@
RZ63
1
0.1U_0402_25V6
1
@EMI@
12P_0402_50V8J
RF@ CZ57
68P_0402_50V8J
RF@ CZ58
12P_0402_50V8J
RF@ CZ59
68P_0402_50V8J
RF@ CZ60
1 1 1 1
CZ56
2
2 2 2 2
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USH & TPM
LA-F391P
5 4 3 2 1
5 4 3 2 1
For ATMEL TPM
D D
+3.3V_ALW
USH_EXPANDER_SMBCLK
1 2
RZ8 2.2K_0402_5%
USH_EXPANDER_SMBDAT
1 2
RZ9 2.2K_0402_5%
USH_PWR_STATE#
1 2
RZ10 100K_0402_5%
USH CONN
CONN@
CVILU_CF5026FD0RK-05-NH
28
C 27 GND2 C
GND1
+PWR_SRC_R
@ RZ85 1 2 0_0402_5% 26
+PWR_SRC 26
25
24 25
<35> CV2_ON 24
RZ364 1 2 100_0402_5% 23
<35> POA_WAKE# 22 23
<35> EC_FPM_EN 21 22
20 21
19 20
<10> USB20_N10 18 19
<10> USB20_P10 17 18
16 17
<35> USH_EXPANDER_SMBCLK 16
15
<35> USH_EXPANDER_SMBDAT 15
14
<35> BCM5882_ALERT# 13 14
12 13
11 12
+3.3V_ALW 11
10
9 10
+5V_ALW 9
8
+3.3V_RUN 8
7
+5V_RUN USH_RST#_R 7
@ RZ114 1 2 0_0402_5% 6
<11,31,33,40> PCH_PLTRST#_AND DZ8 5 6
<35> USH_PWR_STATE# CONTACTLESS_DET#_R 5
2 1 4
<12> CONTACTLESS_DET# 4
3
RB751S40T1G_SOD523-2 2 3
USH_DET#_R 2
@ RZ87 1 2 0_0402_5% 1
<35> USH_DET# 1
@ DZ7 JUSH1
2 1
B RB751S40T1G_SOD523-2 Link CVILU_CF5026FD0RK-05-NH B
PCH_PLTRST#_AND Close to JUSH1

+5V_ALW +5V_RUN +3.3V_RUN +3.3V_ALW
.047U_0402_16V7K
ESD@ CZ61
1
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1 1 1
@
2
CZ64
CZ66
CZ67
CZ68
For ESD solution 2 2 2 2
+5V_ALW +5V_RUN +3.3V_RUN +3.3V_ALW

RF Request
RF Request
68P_0402_50V8J
RF@ CZ69
68P_0402_50V8J
RF@ CZ71
68P_0402_50V8J
RF@ CZ72
68P_0402_50V8J
RF@ CZ73
USH_EXPANDER_SMBCLK
1 2 1 1 1 1
@RF@ CZ62 68P_0402_50V8J
USH_EXPANDER_SMBDAT
1 2
A @RF@ CZ63 68P_0402_50V8J 2 2 2 2 A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USH & TPM
LA-F391P
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN +3.3V_RUN
+3.3V_RUN
For Parade 2 Lane solution
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
@ RN51
1
1
@ RN25
@ RN26
@ RN27
@ RN28
RN49
RN50
RN42
RN43
RN44
PCIE/SATA Redriver for 2280
+3.3V_RUN
2
Brekenridge12 Need
2
1
4.7K_0402_5%
RD1_A_DE0
RD1_B_EQ0 RD1_A_EQ0 Brekenridge14U UMA Need
RN228
RD1_A_DE1
RD1_B_EQ1 RD1_A_EQ1
D
RD1_B_DE0 HDD_UN4_UN5_EN Brekenridge14U DSC Need D
2
RD1_B_EQ2 RD1_A_EQ2
RD1_B_DE1
Brekenridge15U UMA Need
1
D
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
HDD_DET#
1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
@ RN52
@ RN53
@ RN54
@ RN179
@ RN176
@ RN174
2 QN7 Brekenridge15U DSC Need
<10,41> HDD_DET#
1
1
@ RN39
@ RN41
G L2N7002WT1G_SC-70-3
RN38
RN40
3
Steamboat12 No need
2
2
2
Steamboat14 Need
Kirkwood12&13 Check
+3.3V_RUN
Programmable output de-emphasis level
0.1U_0201_10V6K
set t i ng for channel A.
0.01UF_0402_25V7K
1 1
A_DE0: internally pulled up at ~150K;
CN20
PWD Funtion
CN21
A_DE1 internally pulled down at ~150K
2 2
[A_DE1,A_DE0] == 0 Normal mode(default)
LL: -2dB
HL:
LH:
-7.5dB
-3.5dB (default) PCIE/SATA Repeater 1 power down mode
HH: -6dB UN4
12
24 VDD_3.3
VDD_3.3
PCIE_PTX_C_RD_DRX_P11
0.22U_0402_10V6K 1 2 CN22 1 18
Programmable output de-emphasis level <10> PCIE_PTX_DRX_P11
0.22U_0402_10V6K 1 2 CN23
PCIE_PTX_C_RD_DRX_N11
2 A_INP A_OUTP 17 PCIE_PTX_RD_DRX_P11 <40>
C set t i ng for channel B
. <10> PCIE_PTX_DRX_N11 A_INN A_OUTN PCIE_PTX_RD_DRX_N11 <40> C
B_DE0: internally pulled up at ~150K; PCIE_PRX_C_RD_DTX_P11

B_DE1 internally pulled down at ~150K 0.22U_0402_10V6K 1 2 CN26 PCIE_PRX_C_RD_DTX_N11 5 14
<10> PCIE_PRX_DTX_P11 1 2 CN27 4 B_OUTP B_INP 15 PCIE_PRX_RD_DTX_P11 <40>
0.22U_0402_10V6K
<10> PCIE_PRX_DTX_N11 B_OUTN B_INN PCIE_PRX_RD_DTX_N11 <40>
[B_DE1,B_DE0] == RD1_A_EQ0 RD1_A_DE0
23 6
RD1_A_EQ1 A_EQ0 A_DE0 RD1_A_DE1
LL: -2dB RD1_A_EQ2 22 8
A_EQ1 A_DE1
HL: -7.5dB 19
A_EQ2
LH: -3.5dB (default) +3.3V_RUN if signal is PCIE GEN3/SATA GEN3 maybe change C value RD1_B_EQ0 RD1_B_DE0
+3.3V_RUN or no need for DG0.9 SATA EXPRESS HDD RD1_B_EQ1 11 13 RD1_B_DE1
HH: -6dB 21 B_EQ0 B_DE0 9
RD1_B_EQ2 B_EQ1 B_DE1
10K_0402_5%
16
B_EQ2
1
100K_0402_5%
HDD_UN4_UN5_EN_R HDD_UN4_UN5_EN
1
RN65
3 RD1_REXT @ RN229 1 2 0_0402_5%
PWD
RN171
7 10 M2280_PCIE_SATA# RN30 1 2 4.99K_0402_1%

25 GND REXT 20
Equalizer control and program for channel A. EPAD MODE M2280_PCIE_SATA# <10,40>
A_EQ0, A_EQ1 and A_EQ2: internally pulled down at ~150K
2
IFDET_SATA_PCIE# RD2_A_EQ2_R RD2_A_EQ2
2
1 2 PS8558BTQFN24GTR2-A_TQFN24_4X4
[A_EQ2,A_EQ1,A_EQ0] ==
@ RN223 0_0402_5%
6
3
LLL: For channel loss up to 17dB (default) M2280_PCIE_SATA# DEVICE interface

LHL: For channel loss up to 14dB
HLL: For channel loss up to 19dB M2280_PCIE_SATA# IFDET_SATA_PCIE#
2 1 2 5 0 SATA
HHL: For channel loss up to 21dB
QN4A
QN4B
@ RN192 0_0402_5%
LLH: For channel loss up to 18dB M2280_PCIE_SATA#
1
4
1 2 1 PCIE
LHH: For channel loss up to 10dB @ RN182 0_0402_5%
HLH: For channel loss up to 16dB
100K_0402_5%
HHH: For channel loss up to 20dB
1
@
Equalizer control and program for channel B. RN183

B_EQ0, B_EQ1 and B_EQ2: internally pulled down at ~150K
2
+3.3V_RUN
[B_EQ2,B_EQ1,B_EQ0] ==
LLL: For channel loss up to 17dB (default) +3.3V_RUN +3.3V_RUN
B B
LHL: For channel loss up to 14dB
0.1U_0201_10V6K
HLL: For channel loss up to 19dB
0.01UF_0402_25V7K
1 1
HHL: For channel loss up to 21dB
10K_0402_5%
10K_0402_5%
CN30
CN31
1
LLH: For channel loss up to 18dB

RN64
RN63
LHH: For channel loss up to 10dB 2 2

HLH: For channel loss up to 16dB
HHH: For channel loss up to 20dB RD2_A_EQ0_R RD2_A_EQ0 PCIE/SATA Repeater
2
RD2_A_EQ1_R RD2_A_EQ1 1 2
1 2 @ RN225 0_0402_5%
6
@ RN224 0_0402_5%
UN5
3
IFDET_SATA_PCIE# 12
1 2 2 24 VDD_3.3
IFDET_SATA_PCIE# VDD_3.3
1 2 5
QN5A
@ RN186 0_0402_5% PCIE_PTX_C_RD_DRX_P12

QN5B
M2280_PCIE_SATA# @ RN189 0_0402_5% 0.22U_0402_10V6K 1 2 CN32 PCIE_PTX_C_RD_DRX_N12 1 18

<10> PCIE_PTX_DRX_P12
1
1 2 0.22U_0402_10V6K 1 2 CN33 2 A_INP A_OUTP 17 PCIE_PTX_RD_DRX_P12 <40>

M2280_PCIE_SATA# <10> PCIE_PTX_DRX_N12
4
@ RN184 0_0402_5% 1 2 A_INN A_OUTN PCIE_PTX_RD_DRX_N12 <40>

100K_0402_5%
@ RN187 0_0402_5% PCIE_PRX_C_RD_DTX_P12

1
100K_0402_5%
@ 0.22U_0402_10V6K 1 2 CN36 5 14
<10> PCIE_PRX_DTX_P12 PCIE_PRX_C_RD_DTX_N12 B_OUTP B_INP PCIE_PRX_RD_DTX_P12 <40>
1
+3.3V_RUN
RN185
@ 0.22U_0402_10V6K 1 2 CN37 4 15
+3.3V_RUN <10> PCIE_PRX_DTX_N12 B_OUTN B_INN PCIE_PRX_RD_DTX_N12 <40>
RN188
RD2_A_EQ0 RD2_A_DE0
23 6
RD2_A_EQ1 A_EQ0 A_DE0 RD2_A_DE1
RD2_A_EQ2 22 8
2
19 A_EQ1 A_DE1
if signal is PCIE GEN3/SATA GEN3 maybe change C value
2
A_EQ2
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
or no need for DG0.9 SATA EXPRESS HDD RD2_B_EQ0 RD2_B_DE0

1
1
@ RN55
@ RN56
@ RN57
@ RN58
10K_0402_5%
10K_0402_5%
10K_0402_5%
RD2_B_EQ1 11 13 RD2_B_DE1
B_EQ0 B_DE0
1
1
@ RN71
21 9
RD2_B_EQ2 B_EQ1 B_DE1
RN69
RN70
16
B_EQ2
HDD_UN4_UN5_EN_R HDD_UN4_UN5_EN
3 RD2_REXT @ RN230 1 2 0_0402_5%
2
7 PWD 10 RN31 1 2 4.99K_0402_1%

M2280_PCIE_SATA#
2
25 GND REXT 20
RD2_A_DE0 EPAD MODE
RD2_A_DE1 PS8558BTQFN24GTR2-A_TQFN24_4X4
RD2_B_EQ0
RD2_B_DE0
A RD2_B_EQ1 A
RD2_B_DE1
RD2_B_EQ2
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
1
1
@ RN60
@ RN62
10K_0402_5%
10K_0402_5%
10K_0402_5%
1
1
RN59
RN61
@ RN72
@ RN73
@ RN74
2

2
SATA/PCIE REPEATER for M.2 2280
LA-F391P 0.2

5 4 3 2 1
5 4 3 2 1
For Brekenridge 12/14/15 UMA/Steamboat
RF Request
+3.3V_HDD_M2 +3.3V_HDD_M2
D D
0.1U_0201_10V6K
0.1U_0201_10V6K
68P_0402_50V8J
@RF@ CN60
22U_0603_6.3V6M
22U_0603_6.3V6M
1 @ 1
1
CN61
CN62
1
CN63
CN64
2
2
2 2
2
2280 SSD
NGFF slot C Key M

Place near HDD CONN
2.8A
+3.3V_HDD_M2
JNGFF3
1 2
3 1 2 4
5 3 4 6
7 5 6 8
NVME_LED#
9 7 8 10 1 2
SATALED# <10,33,46>
+3.3V_HDD_M2 11 9 10 12 @ RN100 0_0402_5%
13 11 12 14
15 13 14 16
M2280_DEVSLP
1 2 17 15 16 18
@ RN37 10K_0402_5% if signal is PCIE GEN3/SATA GEN3 maybe change C value 19 17 18 20
or no need for DG0.9 SATA EXPRESS HDD 21 19 20 22
C 23 21 22 24 C
25 23 24 26
27 25 26 28
PCIE_PRX_C_DTX_N11
2 1 29 27 28 30
<39> PCIE_PRX_RD_DTX_N11 PCIE_PRX_C_DTX_P11
0_0402_5% 2 1 RN82 @ 31 29 30 32
<39> PCIE_PRX_RD_DTX_P11 0_0402_5% RN81 @ 33 31 32 34
PCIE_PTX_C_DRX_N11
CN69 2 1 0.22U_0402_10V6K 35 33 34 36
<39> PCIE_PTX_RD_DRX_N11 PCIE_PTX_C_DRX_P11
CN70 2 1 0.22U_0402_10V6K 37 35 36 38
<39> PCIE_PTX_RD_DRX_P11 39 37 38 40 M2280_DEVSLP <10>
PCIE_PRX_C_DTX_P12
2 1 41 39 40 42
<39> PCIE_PRX_RD_DTX_P12 PCIE_PRX_C_DTX_N12
0_0402_5% 2 1 RN77 @ 43 41 42 44
<39> PCIE_PRX_RD_DTX_N12 0_0402_5% RN78 @ 45 43 44 46
PCIE_PTX_C_DRX_N12
CN71 2 1 0.22U_0402_10V6K 47 45 46 48
<39> PCIE_PTX_RD_DRX_N12 PCIE_PTX_C_DRX_P12
CN72 2 1 0.22U_0402_10V6K 49 47 48 50
<39> PCIE_PTX_RD_DRX_P12 PCH_PLTRST#_AND <11,31,33,38>
51 49 50 52
PCIE_WAKE# CLKREQ_PCIE#3 <11>
53 51 52 54
<11> CLK_PCIE_N3 PCIE_WAKE# <33,36>
55 53 54 56
<11> CLK_PCIE_P3 57 55 56 58
57 58
SUSCLK_R
67 68 1 2
67 68 SUSCLK <11,33>
69 70 @ RN99 0_0402_5%
<10,39> M2280_PCIE_SATA# 71 69 70 72
73 71 72 74
75 73 74
75
Co-lay:
Short PJP31;Depop RZ99 77 76
B GND1 GND2 B
@ RZ99 1 2 0.01_1206_1% LCN_DAN05-67356-0103

CONN@
PJP31
1 2
+3.3V_RUN +3.3V_HDD_M2 Link DAN05-67356-0103 DONE
PAD-OPEN1x3m
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, M2 2280 Socket
LA-F391P
5 4 3 2 1
5 4 3 2 1
p
i
n
3
p
i
n
6
p
i
n
1
3
p
i
n
1
6
p
i
n
1
8
+3.3V_HDD For Breckenridge 12/14/15 UMA
N
C
P
e
r
i
c
o
m
N
C
* TDet_B# TDet_A# TDeT_EN +3.3V_HDD
G
N
D
G G
N N
D D
D
E
W
2
D
E
W
1
G
N
D
+3.3V_RUN
T
I
R
E
X
T
0.01UF_0402_25V7K
0.1U_0201_10V6K
D
E
W
@
1 1
P
a
r
a
d
e
1
B_EQ2 A_EQ2
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
SATA Repeater
@ RN10
@ RN12
@ RN14
@ RN16
@ RN18
@ RN20
@
CN16
CN17
RN226
RN6
RN8
2 2 +5V_HDD
UN7 HDD_UN7_EN
2
DEW2 6 10
NC VDD
1
100K_0402_5%
DEW1 16 20
D NC VDD HDD_A_PRE D
@ RN1
HDD_B_EQ2 +3.3V_RUN
3 13
HDD_A_EQ TDet_B# TDet_A# HDD_B_EQ HDD_B_PRE
1
17 19 D
HDD_A_PRE A_EQ B_EQ HDD_B_PRE HDD_DET#
9 8 2 QN6
HDD_UN7_EN HDD_UN7_EN_R HDD_A_EQ2 HDD_A_EQ
2
A_EM B_EM
1
100K_0402_5%
1 2 7 18 G L2N7002WT1G_SC-70-3
EN TDeT_EN FFS_INT2_Q
@RN227 0_0402_5% S
SATA_PTX_C_RD_DRX_P0 SATA_PTX_RD_DRX_P0 HDD_B_EQ
RN2
CN12 1 2 0.01UF_0402_25V7K 1 15
<10> SATA_PTX_DRX_P0 SATA_PTX_C_RD_DRX_N0 AI+ AO+ SATA_PTX_RD_DRX_N0
3
CN13 1 2 0.01UF_0402_25V7K 2 14
<10> SATA_PTX_DRX_N0 AI- AO-
SATA_PRX_C_RD_DTX_N0 SATA_PRX_RD_DTX_N0 DEW2
QN1B
<10> SATA_PRX_DTX_N0 CN14 1 2 0.01UF_0402_25V7K
SATA_PRX_C_RD_DTX_P0
4 12
SATA_PRX_RD_DTX_P0
CN15 1 2 0.01UF_0402_25V7K 5 BO- BI- 11 DEW1 5
<10> SATA_PRX_DTX_P0 BO+ BI+
HDD_B_EQ2
21
4
GND
6
HDD_A_EQ2
QN1A
PI3EQX6741STZDEX_TQFN20_4X4
FFS_INT2
2
1
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
7.87K_0402_1%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
@ RN17
@
HDD_A_EQ HDD_B_EQ HDD_A_EQ2 HDD_B_EQ2 DEW 1 DEW 2 HDD_A_PRE HDD_B_PRE
1
RN7
RN9
RN11
RN13
RN15
RN19
RN21
PIN17 PIN19 PIN18 PIN13 PIN16 PIN6 PIN9 PIN8
2
Pericom PI3EQX6741ST PD PD PD PD NC NC PD PD
* (RN11) (RN13) (RN21) (RN19) (RN7) (RN9)
TI SN75LVCP601 PD NC PD PD NC NC PH PH
(RN11) (RN21) (RN19) (IPU) (IPU) (RN6) (RN8)
+3.3V_RUN
Parade PS8527C PD PD PD PD NC PD NC NC
(RN13) (RN21) (RN19) (1/2 VDD) (RN15) (1/2 VDD) (1/2 VDD)
(RN11)
10U_0603_10V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
1
1
C C
Free Fall Sensor
CN1
CN2
CN3
A_EQ B_EQ A_EM B_EM
2
LGA1
0 3dB 3dB 0 0dB 0dB LNG2DM
10 5 INT1/IN2:Push-Pull,active high
Main Pericom NC 6dB 6dB NC
* 1 9dB 9dB 1 1.5dB 1.5dB 3
9 VDD_IO
VDD
RES
INT 1
12
11
FFS_INT2 HDD_FALL_INT <9>
4 SDO/SA0 INT 2 FFS_INT2 <12>
<8,14,20,21> DDR_XDP_WAN_SMBDAT SDA/SDI/SDO
1 6
<8,14,20,21> DDR_XDP_WAN_SMBCLK SCL/SPC GND
0 7dB 7dB 0 0dB 0dB 2 GND
7
8
CS GND
2nd TI NC 0dB 0dB NC -4dB -4dB
1 14dB 14dB 1 -2dB -2dB LNG2DMTR_LGA12_2X2
EQ2 EQ1 A_EQ B_EQ A_EM B_EM
(M = VDD/2)
0 M 2.4dB 2.4dB
0 0 7.4dB 7.4dB
3rd Parade 14.4dB 14.4dB
0 1 0 0dB 0dB
M M 12.2dB 12.2dB M -3.5dB -3.5dB +3.3V_HDD
B
M 0 9.4dB 9.4dB 1 -1.5dB -1.5dB B
HDD_DEVSLP
M 1 13.3dB 13.3dB @ RN3
1 2
10K_0402_5%
*s
r
et
dt
c
o
l
o
r
i
s
c
u
r
r
e
n
t
1 M 6.2dB 6.2dB
e
i
n
g
1 0 11.2dB 11.2dB
JSATA1
1 1 5dB 5dB 1
SATA_PTX_RD_DRX_P0 SATA_PTX_C_DRX_P0 1
CN4 2 1 0.01UF_0402_25V7K 2
SATA_PTX_RD_DRX_N0 SATA_PTX_C_DRX_N0 2
CN5 2 1 0.01UF_0402_25V7K 3
4 3
SATA_PRX_RD_DTX_N0 SATA_PRX_C_DTX_N0 4
CN6 2 1 0.01UF_0402_25V7K 5
SATA_PRX_RD_DTX_P0 SATA_PRX_C_DTX_P0 5
CN7 2 1 0.01UF_0402_25V7K 6
7 6
PJP34 8 7
+3.3V_HDD 8
+3.3V_RUN 1 2 9
10 9
+5V_RUN +5V_HDD PAD-OPEN1x2m 11 10
<10> HDD_DEVSLP 11
PJP33 12
2 1 13 12
<10,39> HDD_DET# 14 13
15 14
Co-lay: +5V_HDD +3.3V_HDD
PAD-OPEN1x1m 16 15
Short PJP32;Depop RZ102 +5V_HDD 16
17
+3.3V_RUN 18 17
FFS_INT2_Q 18
1000P_0402_50V7K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
@ RZ102 19
1 2 20 19
+5V_HDD source 20
1
CN8
CN9
@ CN10
CN11
0.01_1206_1% 21
G1
1
22
@ RN4 @ PJP32 23 G2
1.5A
2
1 2 24 G3
10K_0402_5% UZ23 +5V_HDD G4
+5V_ALW @
PAD-OPEN1x1m ACES_59003-02006-002
2
1 7
HDD_EN VIN VOUT +5V_HDD_UZ23 CONN@
A 2 8 1 2 A
VIN VOUT @ CZ129 0.1U_0201_10V6K
3 6 1 2
<9> HDD_EN ON CT @ CZ130 470P_0402_50V7K Link SP010023HA0 DONE
1
RN5 4
Place near HDD CONN
VBIAS 5
10K_0402_5% GND
GND
9 DELL CONFIDENTIAL/PROPRIETARY
2

AOZ1336_DFN8_2X2 Title
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SATA Repeater&HDD CONN
0.2
5 4 3 2 1
5 4 3 2 1
D D
C C
NO SUPPORT
B B
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USB3.0 Repeater
LA-F391P
5 4 3 2 1
5 4 3 2 1
For w/o Repeater
+5V_USB_CHG_PWR
JUSB1
1
DI4 ESD@ USB20_N9_R VBUS
2
USB3_PRX_DTX_N6 USB3_PRX_DTX_N6 USB20_P9_R D-
150U_B2_6.3VM_R35M
1 1 10 9 3
<10> USB3_PRX_DTX_N6 D+
100U_1206_6.3V6M
0.1U_0201_10V6K
4
USB3_PRX_DTX_P6 USB3_PRX_DTX_P6 USB3_PRX_DTX_N6 GND
D 2 2 9 8 1 @ 1 1 5 D
<10> USB3_PRX_DTX_P6 USB3_PRX_DTX_P6 SSRX-
CI17
6 10
USB3_PTX_C_DRX_N6 USB3_PTX_C_DRX_N6 SSRX+ GND 11
CI32
CI14
2 1 4 4 7 7 + 7
<10> USB3_PTX_DRX_N6 USB3_PTX_C_DRX_N6 GND GND 12
2
CI13 0.1U_0402_25V6 8
USB3_PTX_C_DRX_P6 USB3_PTX_C_DRX_P6 2 2 USB3_PTX_C_DRX_P6 SSTX- GND 13
ESD@ DI5
2 1 5 5 6 6 9
2
<10> USB3_PTX_DRX_P6 2 SSTX+ GND
CI16 0.1U_0402_25V6
3 3 ACON_TCRA2-9U1U93
1
CONN@
8
1
L05ESDL5V0NA-4_SLP2510P8-10-9
Link TCRA2-9U1U93 DONE
RF Request
+5V_USB_CHG_PWR
LI7 EMI@
SW_USB20_N9 USB20_N9_R
1 2
SW_USB20_P9 USB20_P9_R
4 3
12P_0402_50V8J
RF@ CI43
68P_0402_50V8J
RF@ CI44
1 1
EXC24CQ900U_4P
C C
+5V_ALW
+5V_USB_CHG_PWR 2 2
UI3
1 12
VIN VOUT
2
<10> USB20_N9 3 DM_OUT
<10> USB20_P9 DP_OUT SW_USB20_P9
10
DP_IN 11 SW_USB20_N9
13
<10> USB_OC0# FAULT# DM_IN
ILIM_SEL
4
ILIM_SEL
5 15
<35> USB_POWERSHARE_VBUS_EN EN ILIM_L 16 RI14 2 1
ILIM_HI 22.1K_0402_1%
6
<35> USB_POWERSHARE_EN# 7 CTL1 9
8 CTL2 NC 14
CTL3 GND 17
Thermal Pad
+5V_ALW SLGC55544CVTR_TQFN16_3X3
RI13 2 1
ILIM_SEL Link Seligro SA000097E10 Done
10K_0402_5% MAIN:SLGC55544CVTR
B +5V_ALW B
47U_0603_6.3V6M
47U_0603_6.3V6M
10U_0402_6.3V6M
0.1U_0201_10V6K
1 1 1 1
@ CI34
@ CI33
@ CI31
CI19
2 2 2 2
Place near UI3.1
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, JUSB1+PS
LA-F391P
5 4 3 2 1
5 4 3 2 1
For Breckenridge/Steamboat 12&Kirkwood

DI1 ESD@
USB3_PRX_DTX_N3 USB3_PRX_DTX_N3
1 1 10 9
USB3_PRX_DTX_P3 USB3_PRX_DTX_P3
2 2 9 8
USB3_PTX_C_DRX_N3 USB3_PTX_C_DRX_N3
2 1 4 4 7 7 RF Request
<10> USB3_PTX_DRX_N3
CI5 0.1U_0402_25V6 USB3_PTX_C_DRX_P3 USB3_PTX_C_DRX_P3
2 1 5 5 6 6 +USB_EX2_PWR +USB_EX2_PWR
<10> USB3_PTX_DRX_P3
CI4 0.1U_0402_25V6 JUSB2
3 3 1
USB20_N2_R VBUS
2
USB20_P2_R D-
8 3
4 D+
USB3_PRX_DTX_N3 GND
0.1U_0201_10V6K
L05ESDL5V0NA-4_SLP2510P8-10-9 5
D USB3_PRX_DTX_P3 SSRX- D
100U_1206_6.3V6M
1 6 10
SSRX+ GND
1
12P_0402_50V8J
RF@ CI45
68P_0402_50V8J
RF@ CI46
CI3
1 1 7 11
USB3_PTX_C_DRX_N3 GND GND
CI1
8 12
USB3_PTX_C_DRX_P3 SSTX- GND
2
LI3 EMI@ 9 13
USB20_P2 USB20_P2_R
2
2 SSTX+ GND
ESD@ DI2
1 2
2
<10> USB20_P2 2 2 ACON_TCRA2-9U1U93
USB20_N2 USB20_N2_R CONN@
1
4 3
<10> USB20_N2
1
EXC24CQ900U_4P
Link TCRA2-9U1U93 DONE
DFB request:
main SM070003Z00 (INPAQ_MCM1012B900F06BP_4P)
Footprint use 2nd source SM070004400 (PANAS_EXC24CQ900U_4P) +USB_EX2_PWR
Pitch change from 0.5mm to 0.55mm
+5V_ALW
UI1
1
5 OUT
IN 2
GND
10U_0603_10V6M
0.1U_0201_10V6K
4
<35> USB_PWR_EN1# EN 3
1 OCB USB_OC1# <10>
@ CI6
CI7
SY6288D20AAC_SOT23-5
2
2
C C
B B
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, JUSB2
0.2
5 4 3 2 1
5 4 3 2 1
RF Request
KB_DET#
1 2
+3.3V_TP RF@ CZ84 68P_0402_50V8J
Touch Pad +3.3V_RUN +3.3V_TP BC_INT#_ECE1117

@RF@ CZ85
1 2
68P_0402_50V8J
1
BC_DAT_ECE1117
PJP35 RF@ CZ83 1 2
1 2 68P_0402_50V8J @RF@ CZ86 68P_0402_50V8J
+3.3V_TP 2
BC_CLK_ECE1117
PAD-OPEN1x1m 1 2
@RF@ CZ87 68P_0402_50V8J
DAT_TP_SIO_R
4.7K_0402_5%
4.7K_0402_5%
1 2
1
D @RF@ CZ88 68P_0402_50V8J D
RZ18
RZ19
CLK_TP_SIO_R
1 2
@RF@ CZ89 68P_0402_50V8J
PS2
2
DAT_TP_SIO_R
2 1
<35> DAT_TP_SIO_I2C_CLK
@ RZ22 0_0402_5%
CLK_TP_SIO_R
2 1
<35> CLK_TP_SIO_I2C_DAT
@ RZ23 0_0402_5% CONN@
Keyboard JKBTP1
10P_0402_50V8J
10P_0402_50V8J
KB_DET#
1
<12> KB_DET# 1
1
2
I2C1_SDA_TP_R 2
CZ80
CZ81
2 1 3
0_0402_5% RZ346 @ 4 3
I2C1_SCK_TP_R
2
2 1 5 4
+5V_RUN 5
0_0402_5% RZ347 @ +3.3V_ALW 6
BC_INT#_ECE1117 6 +3.3V_TP +3.3V_ALW +5V_RUN
7
<35> BC_INT#_ECE1117 BC_DAT_ECE1117 7
8
<35> BC_DAT_ECE1117 9 8
I2C From EC BC_CLK_ECE1117 9
10
<35> BC_CLK_ECE1117 10
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
11 1 1 1
11
@
12
+3.3V_TP DAT_TP_SIO_R 12
CZ90
CZ91
CZ92
13
+3.3V_TP +3.3V_TP CLK_TP_SIO_R 13
14
15 14 2 2 2
16 15
<12,35> TOUCHPAD_INTR# 16
10K_0402_5%
10K_0402_5%
17
I2C1_SDA_TP_R
1
@ @ 18 17
I2C1_SCK_TP_R 18
1
2.2K_0402_5%
2.2K_0402_5%
RZ116
RZ117
19
19
RZ20
RZ21
20
C 20 Place close to JKBTP1 C
2
2
2
21
I2C1_SDA_TP_R GND
1 2 22
<9> I2C1_SDA_TP GND
@ RZ26 0_0402_5%
I2C1_SCK_TP_R
1 2
<9> I2C1_SCK_TP CVILU_CF5020FD0RK-05-NH
@ RZ29 0_0402_5%
I2C From CPU Link HRS_TF49-20S-0P5SH done
Plan is for I2C to be driven by the EC for Win7 and Pre-OS (will utilize Intel I2C drivers for Win7)
For Win8.1 and 10 the EC will control TP over I2C Pre-OS and then the PCH will drive I2C when in Windows
Route PS2 from EC to the touch pad also for contingency plan if I2C has issues
B B
RSMRST circuit
+3.3V_ALW
@ CZ82
1 2
0.1U_0201_10V6K
5
1
P
<35> PCH_RSMRST# B 4
O PCH_RSMRST#_AND <11,14>
<11,51> ALW_PWRGD_3V_5V 2
A
G
UZ6
3
TC7SH08FU_SSOP5~D
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Keyboard
LA-F391P
5 4 3 2 1
5 4 3 2 1
Bat t er y LE D
HDD LED MUX
means EC can switch battery white led and HDD LED by hot key “ Fn+ H”
<35> MASK_SATA_LED#
BATT_WHITE#
BATT_WHITE#
5
1 2
D <35,46> BAT2_LED# D
BAT2_LED#_R RZ361 150_0402_5%
4 3
<10,33,40> SATALED#
@ QZ2B BATT_YELLOW#
3
DMN65D8LDW-7_SOT363-6 R1=10K;R 2 =1 0 K 1 2
<35> BAT1_LED#
@ QZ3 RZ28 330_0402_5%
R2
DDTA114EUA-7-F_SOT323-3
2
Need LINK SB000002T00 Symbol
R1
+3.3V_ALW
1
2
BAT2_LED#_R
1 6
<35,46> BAT2_LED# 1 2
@ QZ2A @ RZ25 150_0402_5%
LED P/N change to SC50000FL00 from SC50000BA00
Breath LED
+5V_ALW
QZ7B LED3
DMN65D8LDW-7_SOT363-6 BREATH_LED#_Q BREATH_WHITE_LED_SNIFF# LTW-C193DC-C_WHITE
4 3 1 2 1 2
C <35> BREATH_LED# C
RZ32 330_0402_5%
Place LED3 close to SW3
5
+3.3V_ALW
MASK_BASE_LEDS#
@ CZ93
1 2
0.1U_0201_10V6K
5
1
P
<30,35> LED_MASK# B MASK_BASE_LEDS#

4
2 O
<36,46> LID_CL#
G
A UZ10
TC7SH08FU_SSOP5~D
3
POWER & INSTANT ON SWITCH

LED board CONN
2 SW3 1
<11,36> POWER_SW#_MB +5V_ALW
JLED1
4 3 BATT_YELLOW# 1
2 1
BATT_WHITE# 2
SKRBAAE010_4P 3
4 3
5 4
<36,46> LID_CL# 6 5
B +3.3V_ALW B
6 7
GND1 8
GND2
CVILU_CF5006FD0R0-05-NH
CONN@
LED Circuit Control Table

Fiducial Mark
@ FD1
1 LED_MASK# LID_CL#
FIDUCIAL MARK~D
@ FD2
Mask All LEDs (Unobtrusive mode) 0 X
1
Mask Base MB LEDs (Lid Closed) 1 0
FIDUCIAL MARK~D
Do not Mask LEDs (Lid Opened) 1 1
@ FD3
1
FIDUCIAL MARK~D
CPU NGFF Standof f
@ FD4
1 @ H1 @ H2 @ H3 @ H4 @ H5 @ H6 @ H7 @ H8 @ H9 @ H10 @ H11 @ H14 @ H15 @ H16 @ H17 @ H18 @ H19 @ H20 @ H21 @ H22 @ H23 @ H24
H_3P8 H_3P8 H_3P8 H_3P8 H_1P1N H_1P1N H_3P2 H_3P2 H_2P8 H_2P8 H_2P1X3P6 H_4P2X5P2 H_2P8 H_3P0 H_2P8 H_2P8 H_2P8 H_2P8 H_2P1 H_2P8 H_3P0 H_3P0
FIDUCIAL MARK~D
1
For JAE JSIM1 boss hole

A
EDP Standof f A
@ H34 @ H42 @ H43
H_3P3 H_0P7N H_0P9N
1
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PAD, LED
LA-F391P
5 4 3 2 1
5 4 3 2 1
+3.3V_WWAN/+3.3V_LAN source +1.8V_RUN source

PJP41
1 2
+3.3V_ALW +3.3V_WWAN
UZ2 +3.3V_WWAN_UZ2
PAD-OPEN1x3m 2.5A PJP42 0.013A
1 14 1 2 1 2
VIN1 VOUT1 +1.8V_PRIM +1.8V_RUN
2 13 CZ119 0.1U_0201_10V6K UZ8
VIN1 VOUT1 PAD-OPEN1x1m
3.3V_WWAN_EN
3 12 1 2 1 7
<35> 3.3V_WWAN_EN ON1 CT1 VIN VOUT +1.8V_RUN_UZ8
CZ109 470P_0402_50V7K 2 8 1 2
D +3.3V_WWAN_UZ2 VIN VOUT D
4 11 CZ120 0.1U_0201_10V6K
+5V_ALW VBIAS GND RUN_ON_1.8V
1 2 3 6 1 2
<17,35,36,47,54> RUN_ON ON CT
5 10 1 2 @ RZ345 0_0402_5% CZ121 470P_0402_50V7K
<11,35> SIO_SLP_LAN# ON2 CT2 CZ110 470P_0402_50V7K 1
6 9 4
VIN2 VOUT2 +3.3V_LAN_UZ2 +5V_ALW VBIAS
7 8 1 2 RF@ CZ124 5
VIN2 VOUT2 CZ111 0.1U_0201_10V6K 2200P_0402_50V7K GND 9
3.3V_WWAN_EN GND
1
1 2 15 2
RZ40 100K_0402_5% GPAD PJP37 @ CZ197
EM5209VF_SON14_2X3 1 2 470P_0402_50V7K AOZ1336_DFN8_2X2
+3.3V_LAN
2
PAD-OPEN1x1m
1A RF Request
Reserve R/C for Audio power sequence, +5V->+3.3V->+1.8V
+5V_RUN
+3.3V_ALW_PCH/+3.3V_RUN source
1
@
RZ370
100_0603_5%
PJP38 0.63A
1 2
+3.3V_ALW_PCH
2
PAD-OPEN1x1m
+3.3V_ALW
+5V_RUN_CHG
UZ3 +3.3V_ALW_PCH_UZ3
C 1 14 1 2 C
2 VIN1 VOUT1 13 CZ112 0.1U_0201_10V6K
VIN1 VOUT1
@ RZ65 1 2 0_0402_5% 3 12 1 2
<35> PCH_ALW_ON ON1 CT1
@ RZ64 1 2 0_0402_5% CZ113 470P_0402_50V7K
<11,17,53,54,55> PCH_PRIM_EN
4 11
+5V_ALW VBIAS GND
1
D
RUN_ON
5 10 1 2 2 @
ON2 CT2 <35> RUN_ON#
CZ114 1000P_0402_50V7K G QZ4
6 9 S L2N7002WT1G_SC-70-3
+3.3V_RUN_UZ3
3
7 VIN2 VOUT2 8 1 2
VIN2 VOUT2 CZ115 0.1U_0201_10V6K
15
GPAD
EM5209VF_SON14_2X3 PJP39
1 2
+3.3V_RUN
PAD-OPEN1x3m
Reserve for S3 no power issue (+5V_RUN discharge circuit)
3.435A
+5V_RUN/+3.3V_WLAN source
B B
PJP40 2A
1 2
+5V_RUN
+5V_ALW +3.3V_ALW
UZ4 PAD-OPEN1x2m
+5V_RUN_UZ4
1 14 1 2
VIN1 VOUT1
1
2 13 CZ116 0.1U_0201_10V6K
VIN1 VOUT1 RZ518
3 12 1 2 10K_0402_5%
<17,35,36,47,54> RUN_ON ON1 CT1 CZ117 470P_0402_50V7K
4 11
2
VBIAS GND 1 2
WLAN_PWR_EN <35> SLP_WLAN#_GATE
5 10 1 2 @ RZ71 0_0402_5%
ON2 CT2 CZ118 470P_0402_50V7K
+3.3V_WLAN_UZ4
2
6 9 1 2 DZ9
G
+3.3V_ALW VIN2 VOUT2
7 8 CZ122 0.1U_0201_10V6K QZ15
VIN2 VOUT2 SLP_WLAN#_M
1 3 3
<11,35> SIO_SLP_WLAN#
15 PJP36
S
GPAD WLAN_PWR_EN
1 2 S TR BSS138W 1N SOT-323-3 1
+3.3V_WLAN
EM5209VF_SON14_2X3 2
<35> AUX_EN_WOWL
PAD-OPEN1x2m
@ RZ96
1 2
WLAN_PWR_EN
1 2 2A BAT54CW_SOT323-3
RZ38 100K_0402_5% 0.01_1206_1%
1 2
Co-lay: @ RZ70 0_0402_5%
Short PJP36;Depop RZ96
EC request to reserve OR gate for WLAN power enable
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power control
0.2
5 4 3 2 1
5 4 3 2 1
+1.0V_PRIM
VCCPRIM_1P 0 PC H SIO_PWRB TN# 8
Timing Diagram for S5 to S0 mode VCCPRIM_CORE
DCPDSW _1P 0
VCCMPHYAON_1P 0
VCCAPLL_1P 0
PWRBTN#
RSMRS T#
PCH_RSMRS T#
7
VCCCLK 1~ 6 SIO_SLP_S US #
VCCMPHYGT_1P 0
VCCSRAM_1P 0
SLP_SUS # 5
SIO_SLP_S 5#
+1.0V_MPHYGT VCCAMPHYPLL_1P 0 SLP_S 5#
VCCAPLLEBB
SIO_SLP_S 4#
9
SLP_S 4# 10
SIO_SLP_S 3#
+3.3V_ALW +3.3V_ALW _DSW SLP_S 3#
3 VCCDSW_3P 3
SLP_A#
SIO_SLP_A #
CPU
+3.3V_SPI 5 +3.3V_ALW _PCH
SIO_SLP_LA N# 11
D
+VCC_COR E VCCHDA SLP_LA N#
D
VCCST_PW RGD VCCSPI
12 VCCST_PW RGD VCC VCCPRIM_3P 3
VC C PGPPA~E SLP_WLAN#/GP D9
SIO_SLP_WLA N#
+1.0VS_VCCIO VC C R TC PR IM RESET_OUT#
H_CPUP W RGD
VCCIO
6
+1.8V_PRIM SYS_ PWR OK
16
15 PROCPWRGD +VCC_GT VCCPGPPG
VCCATS PCH_PWROK
PCH_PWROK
VCCGT
+RTC_CELL 14
PCH_P LTRS T# +1.2V_MEM
17 PLTRS T#
VDDQ
VCCRTC
VCCST_PW RGD
VCCST_PW RGD
12
0.6V_DDR_V TT_ON
VDDQC
VCCPLL_OC +1.0V_PRIM 6 +1.0V_PRIM_CORE
VCCPRIM_CORE
12 DDR_V TT_CNTL +1.0V_VCCST 11 SIO_SLP_S 4# PROCPWRGD
H_CPUP W RGD
15
VCCST TPS22961
VC C STG
VC C PL L 17 PCH_P LTRS T#
PLTRS T#
+VCC_SA
VC C SA
4
PCH_DPW ROK
DSW_PWROK
10 +PW R_SRC
SIO_SLP_S 4#
+1.2V_MEM
VDDQ
+3.3V_ALW SY8210A DD R
+0.6V_DDR_VTT VTT
ENVDD_P CH
+LCDVD D G524B1T11U EDP_VDDE N
+5V_ALW 12
0.6V_DDR_V TT_ON
PCH_PRIM_E N
+1.0V_PRIM_CORE +3.3V_ALW
6 TLV62130
(SIO_SLP_S US #)
SIO_SLP_LA N#
+3.3V_ALW 11 +3.3V_LAN EM5209VF SLP_LA N#
6 +1.8V_PRIM
RT8097A
+5V_RU N
C 3.3V_TS_E N C
+3.3V_TSP LP2301ALT1G GPP_B21
+PW R_SRC
6
+3.3V_RUN
+1.0V_PRIM SYX198
3.3V_CAM_EN#
+3.3V_CAM LP2301ALT1G GPD7
Power Button
EC 5105
1BAT 2AC
11 SIO_SLP_WLA N#
11 ADAPTER
+PW R_SRC
+5V_ALW +5V_ALW 2
EC 5105 ALWON SY8288C
RUN_ON +5V_ALW
+5V_RU N +5V_HD D
EM5209VF 1BAT
+PW R_SRC
+3.3V_ALW +3.3V_RTC_LDO
BATTERY SY8288B
+3.3V_ALW 2 2AC
EM5209VF +3.3V_RUN +3.3V_HDD +3.3V_ALW
B
5 B
+5V_ALW 7 PCH_RSMRS T#
PCH_PRIM_E N +3.3V_ALW
(SIO_SLP_S US #)
+3.3V_ALW @SIO_SLP_WLA N# TPS62134C +1.0VS_VCCIO

4 PCH_DPW ROK
EM5209VF
@PCH_ALW _ON +3.3V_ALW _PCH 5
RESET_OUT#
11 +3.3V_W LAN EM5209VF
AUX_EN_WOW L 16
Pop option
+3.3V_SPI
5 SIO_SLP_S US #
10 SIO_SLP_S 4#
9 SIO_SLP_S 5#
SIO_SLP_LA N#
11 SIO_SLP_S 3# +PW R_SRC

SIO_SLP_A # EN_INVPW R
AO6405 +BL_PW R_SRC 18
+PW R_SRC
12
+VCC_SA
IMVP_VR_ON
13 +VCC_COR E ISL95857
+VCC_GT
PCH_PWROK
A
14 A

Power Sequence
0.2
LA-F391P
Dat e : Tuesday, September 19, 2017 She e t 48 of 70
5 4 3 2 1
5 4 3 2 1
D D
1
C C
B B
A A
Title
Stack-up
LA-F391P
5 4 3 2 1
5 4 3 2 1
+COINCELL
COIN RTC Battery
2200P_0402_50V7K
1
PR2
1
EMC@ PC2
1K_0402_5%
+3.3V_RTC_LDO
+Z4012 2
2
@ JRTC1
1 3
+COINCELL 2 1 G 4
2 G
D D
ACES_50271-0020N-001
2
+RTC_CELL
1
ESD@ PD1 ESD@ PD2
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
EMC@ PL1 PD3
1
FBMJ4516HS720NT_2P
+3.3V_ALW BAS40CW SOT-323
1
3
1 2 PC3
Primary Battery Connector 1U_0603_25V6K
EMC@ PL2
1
FBMJ4516HS720NT_2P 2
PBATT+_C
1 2 +PBATT
@PBATT1 PR1
1
1 2 100K_0402_5%
2
2 3 PRP1
3 PBAT_SMBCLK_C
4 8 1
2200P_0402_50V7K
4 PBAT_SMBDAT_C
5 PBAT_PRES#_C 7 2
5 PBAT_CHARGER_SMBDAT <35,59>
6 6 3
6 PBAT_CHARGER_SMBCLK <35,59> PBAT_PRES# <35,59>
1
7 5 4
EMC@ PC1
7 8
8 9 100_0804_8P4R_5%
2
9 10
10 11
GND 12
GND
DEREN_40-42251-01001RHF +3.3V_ALW
@ PR3
2
GND 1 2
0_0402_5%
PR4
2.2K_0402_5%
C EMC@ PL3 PR5 C
1
BLM15AG102SN1D_2P 33_0402_5%
NB_PSID PS_ID
2 1 1 3 1 2
S
PS_ID <35>
PQ2
2
FDV301N-G_SOT23-3 +5V_ALW
G
2
PR6
100K_0402_1%
3
PD4 ESD@
1
AZ5125-02S.R7G_SOT23-3 C
2 PQ3 PR7
B MMST3904-7-F_SOT323~D 10K_0402_1%
E
1
3
2
2
PR8
15K_0402_1%
1
PD5
S SCH DIO 5A 100V 15UA 0.88V TO227-3
2 +3.3V_VDD_DCIN +DC_IN
DC_IN+ Source 1
3
1000P_0603_50V7K
+DC_IN PU2
1
1
S1 S2
PC11
+SDC_IN VCC
+DC_IN_SS 3
2
PQ9 PQ4 VOUT 2
EMZB08P03V 1P EDFN3X3-8 EMZB08P03V 1P EDFN3X3-8 GND
+SDC_IN
EMC@ PL4 1 1 11/11
RT9058-33GX SOT-89 3P LDO
1
FBMJ4516HS720NT_2P 2 2
AO3409 P-CHANNEL SOT-23
1
1 2 3 5 5 3 PC10
0.022U_0603_50V7K
PR10 2.2U_0402_10V6M
PC4
2
PR11
1
DFLS160-7_POWERDI123-2
PQ5
499K_0402_1%
300K_0402_5%
1
4
4
B S B
1
3
1M_0402_5%
0.022U_0603_50V7K
2
2
G
2
10U_0805_25V6K
@ PD6
2
PC6
PR12
100K_0402_5%
1000P_0603_50V7K
2
1
1
+3.3V_VDD_DCIN
PC8
0.1U_0603_25V7K
D
4.7K_0805_5%
1
1
PR15
@ PJPDC1
2
1
PR14
EMC@ PC5
PC7
-DCIN_JACK 100K_0402_5%
2
1
PR13
1 2
+DCIN_JACK
2
2
2
PR16
1
1
3
49.9K_0402_1%
@EMC@
3 4 PR17
@
4 5 100K_0402_5%
5
6
1
ACES_50290-0050N-001
2
2
PQ1A
PR18 @ PR19
1M_0402_5% 2 1 2
L2N7002WT1G_SC70-3
PC9 0_0402_5%
+3.3V_VDD_DCIN
1
2 1 D @ PR20
2
1
2 1 2
PQ7
0.1U_0402_10V7K G 0_0402_5%
S
3
PU1 VBUS2_ECOK <35,60>

L2N7002WT1G_SC70-3
5
@ PR21 MC74VHC1G08DFT2G_SC70-5P
1
3
<35,59,60> HW_ACAVIN_NB 1 2 1 D
P
B 4 1 2 2
PQ6
0_0402_5%
O
PQ1B
1 2 2 G @ PR25
A
G
@ PR23 S PR24 5 1 2 AC_DISC# <35,60>

3
@ PR22 0_0402_5% 100K_0402_5% 0_0402_5%

3
0_0402_5%
4
1
PR30
100K_0402_5%
PQ8
2
L2N7002WT1G_SC70-3
S
<35> DCIN2_EN
1 2 3 1
A @ PR26 A
0_0402_5%
G
2
1
100K_0402_5%
1
PR28
@ PR29
0_0402_5%
PR27
2
100K_0402_5%
2
2

+3.3V_VDD_DCIN Title
+3.3V_ALW THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D +DCIN
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 0.2
LA-F391P
5 4 3 2 1
A B C D E
@ PR119
0_0402_5%
PGOOD_3V
1 2
ALW_PWRGD_3V_5V <11,45>
PGOOD_5V
1 2
1 @ PR120 1
0_0402_5%
PR102
499K_0402_1%
+PWR_SRC ENLDO_3V5V
1 2
+PWR_SRC
PJP100 @ PR100 PC102
3V_VIN BST_3V
1
1 2 1 2 1 2
499K_0402_1%
PR103
PAD-OPEN 1x2m~D 0.1U_0603_25V7K
0_0603_5%
100P_0402_50V8J
100P_0402_50V8J
1
PC100 PU100
1U_0402_25V6K
1U_0402_25V6K
100P_0402_50V8J
1000P_0402_50V7K
1000P_0402_50V7K
2
1
PC151
PC103
10U_0805_25V6K
10U_0805_25V6K
IN
IN
IN
IN
BS
1
1
@EMC@ PC135
@EMC@ PC136
LX_3V
6 20 PL100
@EMC@ PC133
@EMC@ PC134
PC105
PC104
2
LX LX 1.5UH_9A_20%_7X7X3_M
RF@
LX_3V
2
2
7 19 1 2
RF@
RF@
GND LX +3.3V_ALWP
8 SY8288BRAC_QFN20_3X3 18 @ PR104
RF@ PR106
GND GND 0_0402_5%
4.7_1206_5%
9 17 1 2
100P_0402_50V8J
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
PG LDO +3.3V_ALW2
1
@ PR105
PC153
PC106
PC107
PC108
PC109
PC129
PC110
1
10 16 0_0402_5%
NC NC 1 2 +3.3V_RTC_LDO
OUT
EN2
EN1
2
21
NC
FF
2
GND
RF@
2
PR107
3VALWP
11
12
13
14
15
3V_SN
100K_0402_5%
680P_0603_50V7K
2 1 2 3.3V LDO 150mA~300mA TDC 6.8 A 2
RF@ PC112
+3.3V_ALW
1
Peak Current 9.7 A
1
PC111
Vout is 3.234V~3.366V
OCP Current 9A f i x by I C
ENLDO_3V5V
4.7U_0603_6.3V6K
2
PGOOD_3V
2
PJP102
PC113 PR108 +3.3V_ALWP 1 2 +3.3V_ALW
1000P_0402_50V7K 1K_0402_5% 1 2
3V5V_EN 3V_FB
1 2 1 2 JUMP_43X118
+PWR_SRC PJP103
+5V_ALWP 1 2 +5V_ALW
PJP101 @ PR111 PC114 1 2
5V_VIN BST_5V
1 2 1 2 1 2 JUMP_43X118
PAD-OPEN 1x2m~D 0.1U_0603_25V7K

0_0603_5%
100P_0402_50V8J
1U_0402_25V6K
1U_0402_25V6K
100P_0402_50V8J
100P_0402_50V8J
1000P_0402_50V7K
1000P_0402_50V7K
PU102
PC152
PC115
PC116
100P_0402_50V8J
10U_0805_25V6K
10U_0805_25V6K
1
PC131
@EMC@ PC139
@EMC@ PC140
IN
IN
IN
IN
BS
@EMC@ PC137
@EMC@ PC138
PC117
PC118
LX_5V
6 20 PL101
2
LX LX 1.5UH_9A_20%_7X7X3_M
RF@
RF@
RF@
LX_5V
7 19 1 2
RF@
GND +5V_ALWP
3 SYV828CRAC QFN 20P PWMLX 3
8 18
GND GND
1
PC119
PR112
680P_0603_50V7K 4.7_1206_5%
100P_0402_50V8J
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
1
1
9 17 1 2
RF@
PC132
PC120
PC121
PC122
PC123
PC130
PC124
PG VCC
10 16
2
NC NC 4.7U_0603_6.3V6K
5V_SN
OUT
LDO
EN2
EN1
2
21
RF@
FF
GND
1
11
12
13
14
15
PR113
PC125
100K_0402_5%
RF@
+5V_ALW2
2
1 2
+3.3V_ALW
ENLDO_3V5V
3V5V_EN
PGOOD_5V 5V LDO 150mA~300mA

1
PC126
4.7U_0603_6.3V6K
@ PR114
5VALWP
2
1 2
<35> ALWON
TDC 6.5 A
0_0402_5%
3V5V_EN
Peak Current 9.3 A
OCP Current 9A f i x by I C
1M_0402_1%
4.7U_0603_6.3V6K~D
1
PC127 PR117
PR116
PC128
1000P_0402_50V7K 1K_0402_5%
5V_FB
1 2 1 2
2
2
4 4
EN1 and EN2 dont't floating
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +5V_ALW/3.3V_ALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F391P
A B C D E
5 4 3 2 1
D D
+PWR_SRC
PJP202
1 2 +1.2V_DDR_B+
@EMC@
@EMC@
PU200
10U_0603_25V6M
10U_0603_25V6M
0.1U_0402_25V6
2200P_0402_50V7K
PAD-OPEN 1x2m~D RF@ RF@

1
10 19
PC200
PC201
+3.3V_ALW PR202 PC204

IN OT
PC202
PC203
100P_0402_50V8J 4.7_1206_5% 680P_0603_50V7K

13 18 1 2 1 2
PC231
@ PR203
2
BYP PG
1
1U_0402_6.3V6K
14 12
0_0603_5%
1 2 1
PC205
2
+1.2V_DDRP
VCC BS
1
PC206
C 0.1U_0603_16V7K PL201 C
LX_DDR
2
1
2.2U_0402_6.3V6M
4 11 1 2
RF@
VTTGND LX
PC207
S COIL 1UH +-20% PCMB063T-1R0MS 12A
2
330P_0402_50V7K
2 9 16
PGND FB
1
102K_0402_1%
EMC@ PC216
EMC@
+1.2V_DDRP
PC208
PR204
15 8 PC209
+3.3V_ALW SGND VDDQSNS
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2200P_0402_50V7K
22U_0603_6.3V6M
R1
100P_0402_50V8J
7 1 2
2
VLDOIN
1
PC210
PC211
PC212
PC213
PC223
PC214
PC217
ILMT_DDR
2
2
@ 17 6
PR205 ILMT VTT +0.6VSP
2
The current limit is 0_0402_5% 1 5
S5 VTTSNS
set to 8A, 12A or 16A
1
100K_0402_1%
2 3
1
when this pin is pull S3 VTTREF
22U_0603_6.3V6M
PR206
ILMT_DDR R2
1
1U_0402_10V6K
PC218
low, floating or pull
PC219
high SY8210AQVC_QFN19_4X3
EN_1.2V
+1.2V_DDR OCP set 12A
2
2
@
EN_0.6V
PR207
0_0402_5%
1
@
PR208
1 2
B <11,17,35,55> SIO_SLP_S4# B
0.1U_0402_10V7K
1M_0402_5%
0_0402_5%
1
1
PC221
PR209
+1.2V_DDRP +1.2V_MEM +0.6VSP +0.6V_DDR_VTT

2
@
PJP200 PJP201
2
JUMP_43X118 JUMP_43X39
1 2 1 2
@ 1 2 1 2
PR210
<20> 0.6V_DDR_VTT_ON 1 2
0.1U_0402_10V7K
1M_0402_5%
0_0402_5%
1
@ PC222
+1.2V_DDR 0.6Volt +/- 5%

PR212
TDC 6.2A TDC 1.05A

2
Mode S3 S5 VOUT VTT Peak Current 8.9A Peak Current 1.5A

Normal H H on on
2
Stadby L H on off
OCP Current 12A OCP Current 4.2A (fix)
Shutdown L L off off
Note: S3 - sleep ; S5 - power off
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.2V_MEN/+0.6V_DDR_VTT
5 4 3 2 1
5 4 3 2 1
D D
PJP302
+1VALWP 1
1 2
2 +1.0V_PRIM
JUMP_43X118
RF@ PR303 RF@ PC302

4.7_1206_5% 680P_0603_50V7K
SNB_+1VALWP
+PWR_SRC PJP301
+1VALWP_B+
PU301
1 2 1 2
1 2 2 9 PC304
10U_0603_25V6M IN PG 0.1U_0603_25V7K @ PR304
10U_0603_25V6M
100P_0402_50V8J
100P_0402_50V8J
3 1 BST_+1VALWP 1 2BST_+1VALWP_C
1 2
PC301
PC303
PAD-OPEN 1x2m~D PL301

IN BS
1
1
PC305
PC306
0.68UH_7.9A_20%_5X5X3_M
SW_+1VALWP
C 4
IN LX
6 0_0603_5% 1 2 +1VALWP C
2
2
5 19
RF@
RF@
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
IN LX
330P_0402_50V7K
1
1
7 20
GND LX
PC307
PC308
PC309
PC310
PC311
21.5K_0402_1%
FB_+1VALWP
1
8 14
2
GND FB
PR306
@ PR312 18 17
4.7U_0603_6.3V6K
GND VCC
1
0_0402_5%
1K_0402_5%
EN_+1VALWP
1
1 2 11 10
PC313
PR308
<11,17,47,54,55> PCH_PRIM_EN
2
EN NC
1
13 12
2
ILMT NC
2
PR302 15 16
1M_0402_1% +3.3V_ALW BYP NC
4.7U_0603_6.3V6K
21
2
PAD
1
1
PC312
SY8286RAC_QFN20_3X3 PR311
31.6K_0402_1%
2
+3.3V_ALW
2
1
@ PR307
0_0402_5%
+1.0V_PRIM
B
ILMT_+1VALWP
TDC 5.4A B
2
Peak Current 6.5 A

1
OCP Current 9 A Fix by IC

@ PR310 TYP MAX
0_0402_5% Choke DCR 11.0mohm , 12.0mohm
2
The current limit is set to 6A, 9A or 12A when this pin

is pull low, floating or pull high
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1VALWP
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-F391P
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
LPM LOGIC VID1 LOGIC VID0 LOGIC OUTPUT VOLTAGE
1
@ PR425
0_0402_5% @ PR404
1 2
0 X X 0(LPM)
<11,17,37,54> SIO_SLP_S0# 0_0402_5%
PJP401
TPS62134C 1 0 0 0.80
2
JUMP_43X79 1 0 1 0.95
@ PR402 1 2
0_0402_5% +1VS_VCCIOP 1 2 +1.0VS_VCCIO
1 2
1 1 0 1.00
<17,35,36,47> RUN_ON
1 1 1 1.05
EN_1VS_VCCIO
0.1U_0402_25V6
1
1
@ PC402
PR403
D 1M_0402_1% D
2
2
@ PL405
13
14
15
16
17
3A_Z120_40M_0603_2P
1 2 PU401
Vin=3~17V
+1.0VS_VCCIO
LPM
TP
EN
PGND
PGND
PJP403 TDC 2.2 A
+5V_ALW 1 2
VIN_1VS_VCCIO
12
PVIN VOS
1
+1VS_VCCIOP Peak Current 3.1 A
PL402 OCP Current 4.2 A Fix by IC
10U_0603_10V6M
10U_0603_10V6M
PAD-OPEN1x1m 1UH_1277AS-H-1R0N-P2_3.3A_30%
LX_1VS_VCCIO TYP MAX
+3.3V_ALW
1
11 2 1 2
+1VS_VCCIOP
PC403
PC404
PVIN SW
Choke DCR 48.0mohm
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2
2
TPS62134CRGT_QFN16_3X3
1
10 3
PC406
PC407
PC425
PC426
AVIN SW
100P_0402_50V8J
2
PC409
SNUB_1VS_VCCIO
0.1U_0402_25V6
VID0_VCCIO
1
9 4
PC408
VID0 PG @EMC@ PR405
1
AGND
4.7_0603_5%
RF@
VID1
FBS
@ PR413 PR414 @EMC@
SS
2
10K_0402_1% 10K_0402_1%
VID0_VCCIO
2
1
@EMC@ PC401
SS_1VS_VCCIO
VID1_VCCIO +1VS_VCCIOP
VID1_VCCIO
470P_0402_50V7K
1
1
PR421
0_0402_5%
PR415 @ PR416
470P_0402_50V7K
10K_0402_1% 10K_0402_1%
PR422
2
1
1
0_0402_5%
C @ C
2
1 2
@ PR427
PC410
VCCIO_SENSE <17>
2
0_0402_5%
@ PR412
2
1 2
VSSIO_SENSE <17>
0_0402_5%
"R" for SILERGY

+3.3V_ALW
1
@ PR426 @PR410
0_0402_5% 0_0402_5%
<11,17,37,54> SIO_SLP_S0#
1 2
2
PJP402
@ PR406 JUMP_43X79
EN_1.0V_PRIM_COREP
0_0402_5% 1 2
<11,17,47,53,55> PCH_PRIM_EN
1 2 +1.0V_PRIM_COREP 1 2 +1.0V_PRIM_CORE
0.1U_0402_25V6
1
1
@ PC411
PR407
1M_0402_1%
2
2
@ PL406
13
14
15
16
17
3A_Z120_40M_0603_2P
1 2 PU402
B Vin=3~17V B
LPM
TP
EN
PGND
PGND
VIN_1V_PRIM
+5V_ALW 1 2 12
PVIN VOS
1
+1.0V_PRIM_COREP
+3.3V_ALW
10U_0603_10V6M
10U_0603_10V6M
PL404
PJP404 1UH_1277AS-H-1R0N-P2_3.3A_30%
PAD-OPEN1x1m LX_1V_PRIM
1
11 2 1 2
+1.0V_PRIM_COREP
PC412
PC413
PVIN SW
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2
TPS62134DRGT_QFN16_3X3
1
10 3
PC424
PC415
PC427
PC428
AVIN SW
Rup
100P_0402_50V8J
LPM LOGIC VID1 LOGIC VID0 LOGIC OUTPUT VOLTAGE
2
PC418
0.1U_0402_25V6
1
9 4
PC417
VID0 PG @EMC@ PR409

0 X X 0.7(LPM)
SNUB_1V_PRIM
PR417 PR418 TPS62134D 1 0 0 0.85

2
AGND
10K_0402_1% 10K_0402_1% 4.7_0603_5%

RF@
VID0_PRIM_CORE
VID1
FBS
@EMC@
1 0 1 0.90
SS
VID0_PRIM_CORE
2
VID1_PRIM_CORE 1 1 0 0.95
8
@EMC@ PC419 1 1 1 1.00

1
470P_0402_50V7K
VID1_PRIM_CORE
@ PR408
@ PR419 @ PR420 0_0402_5%
SS_1V_PRIM
10K_0402_1% 10K_0402_1%
<18> CORE_VID0
1 2
2
@ PR411 @ PR423
+1.0V_PRIM_CORE
0_0402_5% 0_0402_5% TDC 1.8 A
1 2 1 2
<18> CORE_VID1 Peak Current 2.6 A
OCP Current 4.2 A Fix by IC
470P_0402_50V7K
1M_0402_1%
TYP MAX
1
1
PR428
A A
@ PR424 Choke DCR 48.0mohm
PC420
100K_0402_1%
2
@
2
"R" for SILERGY
Title
+1VS_VCCIOP/+1.0V_PRIM_COREP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.2
LA-F391P
5 4 3 2 1
5 4 3 2 1
PC531
1 2
PC530
1 2
10U_0603_6.3V6M
@ PL502 10U_0603_6.3V6M
PJP502
3A_Z120_40M_0603_2P
1 2 1 2
+1.8VALWP +1.8V_PRIM
PJP501 PAD-OPEN1x1m
VIN_1.8VALW
1 2
+3.3V_ALW
Imax= 2A, Ipeak= 3A
PAD-OPEN1x1m
FB=0.6V
D D
PR517 PU501
PL501
2 1 1UH_1277AS-H-1R0N-P2_3.3A_30%
+3.3V_ALW LX_1.8VALW
4 3 1 2
100K_0402_5% IN LX +1.8VALWP
1
5 2
68P_0402_50V8J
<35> 1.8V_PRIM_PWRGD PG GND @EMC@ PR502
22U_0603_6.3V6M
22U_0603_6.3V6M
SNUB_1.8VALW
1
6 1
PC503
FB EN
1
4.7_0603_5%
PC501
PC504
PR501
2
RT8097ALGE SOT23 6P PWM
2
EN_1.8VALW 20K_0402_1%
1 2
<11,17,47,53,54> PCH_PRIM_EN Rup
2
1
@EMC@ PC506
@ PR504
1
0_0402_5% 680P_0402_50V7K
2
1
PR505 @ PC505
1M_0402_1%
0.1U_0402_16V7K
FB_1.8VALW
2
2
1
PR506
Rdown +1.8V_PRIM
10K_0402_1% TDC 0.7 A
Note: Peak Current 1 A
2
When design Vin=5V, please stuff snubber OCP Current 3.5A f i x by I C
to prevent Vin damage
Vout=0.6V* (1+Rup/Rdown)
C C
B B
+2.5V_MEN
TDC 0.3A by power budget
AP7361 U-DFN3030-8 Pd limit=1.7W
Peak loading=1.1A.
Pd=(3.3-2.5)*1.1=0.88W < 1.7W
OCP is 1.1~1.5A
PU503
PJP505
+2.5V_VIN AP7361C-FGE-7-01_U-DFN3030-8_3X3 PJP506
1 2 9
+3.3V_ALW GND 1 2.5VSP 1 2
OUT +2.5V_MEM
1
8
PAD-OPEN1x1m PC514 IN 2
NC PAD-OPEN1x1m
1
4.7U_0603_6.3V6K 7 PR515
2
NC 3 21.5K_0402_1% PC515
6 ADJ/NC 0.01UF_0402_25V7K
2
NC
1
EN_2.5V 4
GND PC516
1 2 5
<11,17,35,52> SIO_SLP_S4# EN 22U_0603_6.3V6M
2
@ PR513
1
0_0402_5% @
PR514 PC513
PR516
2
1M_0402_1% .1U_0402_16V7K 10.2K_0402_1%

A A
2
Title
+1.8VALWP/+1.2V_RUN/2.5V_MEM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
LA-F391P
5 4 3 2 1
5 4 3 2 1
+1.0V_VCCST VCC_SA U22 VCC_SA U42

TDC 4.0A TDC 4.0A
Peak Current 4.5A Peak Current 5A
OCP current 10A OCP current 10A
0.1U_0402_25V6
1
1
45.3_0402_1%
75_0402_1%
100_0402_1%
PC602
1 2
+5V_ALW Choke DCR 6.2 m ohm Choke DCR 6.2 m ohm
PR605
PR601
PR604
@ PR602
Local sense put on HW site
2
0_0402_5% CPU_B+ PJP603
0.22U_0603_25V7K
@ 1 2
2
1 2
1U_0603_10V6K
D 1 2 @ PR603 VCCSA_B+ CPU_B+ D
<15> VIDSCLK
1
49.9_0402_1% PR618 0_0402_5%
PC603
PC604
PAD-OPEN1x1m
<15> VIDALERT_N 1 2
@ 0_0402_5% PR625
For ISUMN_IA Setting
2
<15> VIDSOUT 1 2
10_0402_1% PR626
VCCSA_B+
VIDALERT_N_B
<12,35,59> PROCHOT# PR678
VIDSOUT_B
VIDSCLK_B
100_0402_1% PC624 @U42 PC624 @U22
1 2 1 2
1 2
PC605 47P_0402_50V8J~D
470K_0402_5%_B25/50 4700K PR608
10U 25V M X5R 0603 ZRB
10U 25V M X5R 0603 ZRB

PR610 88.7K_0402_1%
PH601
10K_0402_1% 1 2
1
PC612
PC608
1 2 1 2 @ PR613 1.91K_0402_1% PR612 0.015U 25V K X7R 0402 0.022U_0402_16V7K
90.9K +-1% 0402 1 2 PR611
1 2 1 2 +3.3V_RUN 1.87K +-1% 0402
2
PR631 PC613 <11> PCH_PWROK
1 2
27.4K_0402_1% 330P_0402_50V7K @ PR614 0_0402_5%
1 2 1 2
<36> IMVP_VR_ON
PC614 PR617 @ PR616 0_0402_5%
2200P_0402_50V7K 4.3K_0402_1%
1 2 1 2
40
39
38
37
36
35
34
33
32
31
SA_UGATE
PU602
@ PC616 PR619 2.2_0603_5%
VCC
VIN
VR_HOT#
ALERT#
PROG1
PROG2
VR_ENABLE
VR_READY
SCLK
SDA
33P_0402_50V8J @ PR620 1 2
1 2 @ PC617 @ PR621 0_0402_5%
PWM_VSA PU614
1200P_0402_50V7K 316_0402_1% 1 2 1 30
<35,59> I_SYS FCCM_VSA
1
1 2 1 2 2 PSYS PWM_C 29 S IC ISL95808HRZ-TS2778 DFN MOSFET DRIVE PQ614
<15> VCCSENSE IMON_B FCCM_C
@ PR622 3 28 PE642DT 2N PDFN3X3S
D1
D1
D1
G1
@ PC618 1.91K_0402_1% 4 NTC_B ISUMN_C 27 PC611 1 8 PL614
1 2 1 2 5 COMP_B ISUMP_C 26 UGATE PHASE
0.082U_0402_16V7K
FB_VSA 0.22U_0603_16V7K SA_SW 0.47UH_MMD05CZR47M_12A_20%

FB_B RTN_C
@ PC620
6 25 1 2 2 7 10 9 4 1
COMP_VSA
RTN_B FB_C BOOT FCCM D1 D2/S1 +VCC_SA
1
330P_0402_50V7K 7 24 IMON_VSA PWM_SA

ISUMP_B COMP_C
PR627 @EMC@
PC621 PR623 8 23 3 6 3 2
C
PC619 680P_0402_50V7K 2K_0402_1% 9 ISUMN_B IMON_C 22 PWM VCC C
G2
S2
S2
S2
SA_LGATE
2
ISEN1_B PWM_A PWM_GT <57>
1
4.7_1206_5%
1 2 1 2 1 2 10 21 4 5
ISEN2_B FCCM_A FCCM_GT <57> GND LGATE
1
@PR606
TP
ISUMP_A
ISUMN_A
PWM1_B
PWM2_B
PR624
8
COMP_A
FCCM_B
41
IMON_A
0.01UF_0402_25V7K 0_0402_5%
NTC_A
RTN_A
AGND 3.65K_0603_1%
FB_A
PWM_VSA
<15> VSSSENSE
1
2
2
PR679 @
2
0_0402_5%
+5V_ALW
SA_SNUB
ISUMP_VSA
11
12
13
14
15
16
17
18
19
20
ISUMN_VSA
ISL95857AHRTZ-T TQFN 40P PWM
680P_0603_50V7K
1U_0402_10V6K
<57> ISUMP_IA
2
IMON_GT
FB_GT
FCCM_VSA
NTC_GT
COMP_GT
<57> FCCM_IA
4.99K_0402_1%
PC685
@EMC@ PC622
<57> PWM1_IA
2
2
1
<57> PWM2_IA
PR628
@ PR658 PC625
20M_0402_5% 330P_0402_50V7K
2
0.033U_0402_16V7K
0.047U_0402_25V7K
1 2
PR629
1
88.7K_0402_1%
1
2.49K_0402_1%
PC624
@ PC626
1 2
33P 50V J NPO 0402

10K_0402_5%_B25/50 4250K
PR630
PH603
1
1
2200P_0402_50V7K
4700P_0402_25V7K
11K_0402_1%
PR632 PC627 470K_0402_5%_B25/50 4700K

2
2
1
2200P_0402_50V7K
PR633
PC628
@ 1K_0402_1% 1 2 1 2
ISUMP_VSA
PH602
1 2 1 2
2
374_0402_1%
PR647 PR635 1 2
2.61K_0402_1%
@ PR638 27.4K_0402_1% 10K_0402_1%
2
1
PC630
PR640
374_0402_1% 1 2 PR636 665 +-1% 0402
2
PC631
1 2 PC629 PR639
PR642
<57> ISUMN_IA
2200P_0402_50V7K 3.09K_0402_1% 1 2 1 2
10KB_0402_5%
@U42 PC635 1 2 1 2
2
0.022U_0402_16V7K PC632 PR641
0.033U 25V K X7R 0402

ISEN1_IA
2
2
1K_0402_1%
11K_0402_1%
1 2 PC636 1000P_0402_50V7K 1K_0402_1%
33P_0402_50V8J
4700P 50V K X7R 0402
PR643
1
1
PR644
PC633
1 2
PC637
@U42 PC638
1
B 0.022U_0402_16V7K PC639 PR645 PR646 PC640 B
ISEN2_IA
1
1 2 1500P_0402_50V7K 316_0402_1% 1 2 1 2
330P_0402_50V7K
@U22 PR634 1 2 1 2
PH604
0_0402_5% 316_0402_1% 2200P_0402_50V7K
1 2
2
1 2
.1U_0402_16V7K
PR649
+5V_ALW
1
1
113K_0402_1%
1 2 PR648 1 2
ISUMN_VSA
1
PC641
1.91K_0402_1% PC642
<57> ISEN1_IA
680P_0402_50V7K 2K_0402_1%
PC643
PR651
@U22 PR615 0.022U_0402_16V7K 1.62K_0402_1% PC644
2
2K_0402_1%
0_0402_5% 1 2 .1U_0402_16V7K
<57> ISEN2_IA
PR652
1 2
.1U_0402_16V7K
2
1
PR650
PC645
2
1 2
680P_0402_50V7K
PC646 @
0.047U_0402_25V7K
2
VSA_SEN- <17>
PC647
PC601
1 2
2
1
PC649
@ 0.01UF_0402_25V7K
0.082U_0402_16V7K
1 2
<16> VCC_GT_SENSE
PR656
11K_0402_1%
2
PC650
1 2
@ PC652
PR657
1
@ PC651 @ 330P_0402_50V7K
PH605
1 2 4.42K_0402_1% 1 2
0.082U_0402_16V7K
1 2 1 2
@ PC653
330P_0402_50V7K
1
@ PR653 10K_0402_5%_B25/50 4250K VSA_SEN+ <17>

2 1 ISUMN_GT <57>
2
PC654 20M_0402_5%
A A
1 2
ISUMP_GT <57>
0.01UF_0402_25V7K
<16> VSS_GT_SENSE
Local sense put on HW site
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_VCORE_ISL95857
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Siz e Document Number Rev
5 4 3 2 1
5 4 3 2 1
VCC_core (U22) VCC_core (U42)

TDC 21A TDC 42A
+PWR_SRC Peak Current 32A Peak Current 64A U42
PJP601
1 2
OCP current 38.4A OCP current 76.8A
Choke DCR 0.9 +-7%m ohm Choke DCR 0.9 +-7%m ohm PC626 @U42 PR613 @U42 PR621 @U42
PAD-OPEN 4x4m
CPU_B+
1U_0402_25V6K
1U_0402_25V6K
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
+VCC_CORE @U42 +VCC_GT_+VCC_CORE
PC696
@EMC@ PL602
1
1 2 PR682 SOLDER_PREFORMS_0603
@EMC@ PC691
@EMC@ PC692
100P_0402_50V8J
@EMC@ PC689
@EMC@ PC690
1 2
RF@
RF@
1 2
0.1U 25V 0402 93.1K +-1% 0402 1K +-1% 0402
100U_D_20VM_R55M
100U_D_20VM_R55M
9A Z80 10M 1812_2P
2
+VCC_GT @U22
2200P_0402_50V7K
0.1U_0402_25V6K~D
RF@
1 1
10U 25V M X5R 0603 ZRB
10U 25V M X5R 0603 ZRB
10U 25V M X5R 0603 ZRB
10U 25V M X5R 0603 ZRB

PR683 SOLDER_PREFORMS_0603
+ + 1 2 PR638 @U42 PR622 @U42 PC616 @U42 PC617 @U42
1 2
1
1
PC682
PC656
PC657
PC658
PC659
PC660
D D
2 2
2
2
RF@
+VCC_CORE @U42 +VCC_GT_+VCC_CORE 475 +-1% 0402 3.09K_0402_1% 68P 50V J 0402 220P 50V 0402
PR684 SOLDER_PREFORMS_0603
PC606
PC607
1 2
1 2
PC695
U22
PL610
0.15UH_MMD-06CZER15MEX5L__35A_20%
PC626 @U22 PR613 @U22 PR621 @U22 PC617 @U22
PU610 IA_SW1
10 11 4 1 For KBL U42 : Pop PR682 and PR684
9 PGND
VIN
SW
SW
12 +VCC_CORE For KBL U22 : Pop PR683
3 2
PR663 @EMC@
PC655 8 13
0.1U 25V K X5R 0402
VIN GL
IA1P
4.7_1206_5%
0.22U_0603_16V7K IA1N 0.047U_0402_25V7K 86.6K +-1% 0402 316 +-1% 0402 1200P 50V 0402
+5V_ALW
1
1
1 2 7 14
PC686
6 PHASE PGND 15 PR667 @U42 PR668 PR666

N/C PVCC 3.65K_0603_1% PR638 @U22 PR622 @U22 PC616 @U22
10_0402_1%
2
1 PR660 2 5 16 1 2 1 2
1U_0402_10V6K
2
BOOT N/C
10K_0402_1%
3.9_0603_1% 4 17 100K_0402_1%
2
AGND N/C
1
@ PR686
PC661
<56> ISEN1_IA
3 @ PR670
IA_SNUB1
2 VCC 18 100K_0402_1%
2
1 FCCM GL 19 IA2N 2 1
PR688 365 +-1% 0402 1.5K +-1% 0402 33P 50V J 0402
2
1_0603_5% PWM AGND
VCC_IA1
1 2 FDMF3035_PQFN31_5X5
CPU_B+
680P_0603_50V7K
1U_0402_10V6K
+5V_ALW
<56,57>
<56,57>
ISUMP_IA
ISUMN_IA
1
1
PC676
@EMC@ PC662
C C
2
10U 25V M X5R 0603 ZRB
10U 25V M X5R 0603 ZRB
10U 25V M X5R 0603 ZRB
10U 25V M X5R 0603 ZRB

1
1
PC675
PC674
PC664
PC665
@ PR659
0_0402_5%
1 2
<56,57> FCCM_IA
2
@ PR687
0_0402_5%
1 2
<56> PWM1_IA
EMC@ PR669 EMC@ PC670

4.7_1206_5% GT_SNUB 680P_0603_50V7K
10U 25V M X5R 0603 ZRB
10U 25V M X5R 0603 ZRB
10U 25V M X5R 0603 ZRB
10U 25V M X5R 0603 ZRB
1 2 1 2
@U42 PC683
@U42 PC684
@U42 PC672
@U42 PC673
PL612
1
0.15UH_MMD-06CZER15MEX5L__35A_20%
PU612 GT_SW
2
10 11 4 1
9 PGND
VIN
SW
SW
12 +VCC_GT
3 2
@U42 PL613 PC663 8 13
0.1U 25V K X5R 0402

0.15UH_MMD-06CZER15MEX5L__35A_20% 0.22U_0603_16V7K VIN GL
+5V_ALW
1
1 2 7 14
PC687
PHASE PGND PR661
@U42 PU613 6 15
IA_SW2 N/C PVCC
10 11 4 1 3.65K_0603_1%
+VCC_CORE
2
PGND SW
1U_0402_10V6K
9 12 1 PR665 2 5 16
VIN SW BOOT N/C
10K_0402_1%
3 2 3.9_0603_1% 4 17
2
1
8 13 AGND N/C
4.7_1206_5%
PR681
PC668
@U42 PC671
VIN GL
<56>
<56>
1
IA2P
ISUMP_GT
ISUMN_GT
B 0.22U_0603_16V7K IA2N 3 B
0.1U 25V K X5R 0402
+5V_ALW VCC
1
1 2 7 14 2 18
@U42 PC688
@EMC@ PR676
2
PHASE PGND FCCM GL
1
6 15 @U42 PR674 @U42 PR673 1 19 @
2
N/C PVCC 3.65K_0603_1% @U42 PR675 PR680 PWM AGND
10_0402_1%
1 2 5 16 1 2 1 2
1U_0402_10V6K
1_0603_5% VCC_GT FDMF3035_PQFN31_5X5

2
BOOT N/C
1
10K_0402_1%
@U42 PR672 4 17 100K_0402_1% 1 2

+5V_ALW
2
AGND N/C
1
@ PR689
PC697
3.9_0603_1% <56> ISEN2_IA

3
IA_SNUB2
VCC
1U_0402_10V6K
2 18 @ PR677
2
1
1 FCCM GL 19 1 2
PC669
IA1N
2
PWM AGND
@U42
100K_0402_1%
@U42 PR691 FDMF3035_PQFN31_5X5
2
1_0603_5%
1 2
VCC_IA2 VCC_GT (U22) VCC_GT (U42)
+5V_ALW TDC 18A TDC 12A
<56,57>
<56,57>
ISUMP_IA
ISUMN_IA
680P_0603_50V7K
1U_0402_10V6K
Peak Current 31A Peak Current 28A

1
1
@U42 PC677
@EMC@ PC678
@ PR662
0_0402_5%
1 2
OCP current 37.2A OCP current 33.6A
<56> FCCM_GT Choke DCR 0.9 +-7%m ohm Choke DCR 0.9 +-7%m ohm
2
@ PR664
0_0402_5%
1 2
<56> PWM_GT
@U42 PR671
0_0402_5%
1 2
<56,57> FCCM_IA
@U42 PR692
0_0402_5%
1 2
<56> PWM2_IA
A A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_VCORE_ISL95857
5 4 3 2 1
4
3
2
1
+VCC_CORE
A
A
2 1 2 1 2 1
2
1
22U_0603 * 6 pcs
330U_D2_2.5VM_R9M
PC1127 PC1099 PC1083 PC1076
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
+VCC_GT_+VCC_CORE
+
2
1
330U_D2_2.5VM_R9M
PC1062 PC1095 PC1030 PC1081 PC1078
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
2 1
2
1
PC1094 PC1031 PC1080 PC1077
330U_D2_2.5VM_R9M
PC1326 PC1321 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1 2 1
+220u_D7*3 pcs
2 1 @U42
PC1096 PC1032 PC1082 PC1079
VCC_GT_+VCC_CORE Place on CPU

PC1325 RF@ PC1191 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1 2 1 2 1
2 1
100P_0402_50V8J PC1090 PC1033 PC1067 PC1001
PC1324 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
VCC_CORE Place on CPU
22U_0603_6.3V6M 2 1 2 1 2 1 2 1
2 1 RF@ PC1192
2 1 PC1093 PC1034 PC1072 PC1002
PC1323 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M 100P_0402_50V8J 2 1 2 1 2 1 2 1
2 1
PC1091 PC1035 PC1069 PC1003
PC1322 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1097 PC1036 PC1074 PC1004
PC1327 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603 * 33 pcs +1U_0201*35 pcs
22U_0603_6.3V6M 2 1 2 1 2 1 2 1
B
B
2 1
PC1092 PC1037 PC1070 PC1005
PC1330 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1098 PC1038 PC1061 PC1006
PC1331 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1050 PC1039 PC1071 PC1007
PC1332 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1051 PC1084 PC1066 PC1008
PC1333 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1052 PC1086 PC1073 PC1009
PC1334 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1 2 1 2 1
PC1053 PC1085 PC1068 PC1010

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
PC1088 PC1075 PC1011

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
PC1087 PC1064 PC1012

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
PC1089 PC1065 PC1013
C
C
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

+VCC_GT
VCC_SA Place on CPU

2 1 2 1 2 1
+
2
1
330U_D2_2.5VM_R9M
PC1128 PC1040 PC1133 PC1014
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
+
2
1
330U_D2_2.5VM_R9M
PC1063 PC1041 PC1137 PC1015
+220u_D7*2 pcs
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

2 1 2 1 2 1 2 1
+VCC_SA
@ PC1181 PC1042 PC1129 PC1016

22U_0603 * 12 pcs + 1U_0201*7 pcs
22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

2 1 2 1 2 1 2 1
2 1 2 1 @ PC1180 PC1043 PC1132 PC1017

22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
D
D
PC1153 PC1057 2 1 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
@
2 1 2 1
VCC_GT Place on CPU (U22)
PC1177 PC1044 PC1136 PC1018
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1147 PC1058 2 1 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 @ PC1179 PC1045 PC1134 PC1019

22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

PC1148 PC1059 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1
22U_0603 * 26 pcs +1U_0201*12 pcs
@ PC1176 PC1046 PC1020

22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
PC1149 PC1060 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 @ PC1178 PC1047 PC1021
22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
PC1150 PC1139 2 1 2 1 2 1
22U_0603_6.3V6M
Size
Title
1U_0201_6.3V6M
Date:
@
2 1 2 1 PC1175 PC1048 PC1022

22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
PC1151 PC1140 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 PC1049 PC1023
Document
1U_0201_6.3V6M 22U_0603_6.3V6M
PC1152 PC1141 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 PC1055 PC1024
Number
2 1 1U_0201_6.3V6M 22U_0603_6.3V6M
PC1142 2 1 2 1
RF@ PC1198 22U_0603_6.3V6M
100P_0402_50V8J 2 1 PC1056 PC1025
Tuesday, September 19, 2017
2 1 1U_0201_6.3V6M 22U_0603_6.3V6M
PC1143 2 1 2 1
RF@ PC1199 22U_0603_6.3V6M
100P_0402_50V8J 2 1 PC1328 PC1026
E
E
LA-F391P
1U_0201_6.3V6M 22U_0603_6.3V6M
PC1144 2 1
22U_0603_6.3V6M
Sheet
2 1 PC1329
1U_0201_6.3V6M
PC1145
58
22U_0603_6.3V6M
2 1
of
PC1146
22U_0603_6.3V6M
PROCESSOR DECOUPLING
65
Re v
0.1
4
3
2
1
A B C D
+PWR_SRC_AC
+SDC_IN
+CHARGER_SRC
PR901
0.01_1206_1% EMC@ PL901
1UH +-20% 6.6A 5X5X3 MOLDING
1 4 2 1
+PWR_SRC
1
2 3
100P_0402_50V8J
0.1U_0402_25V6
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
15U_B2_25VM_R100M
1
@EMC@ PC902
RF@ PC903
1
1
PC911
PC904
PC905
PC906
PC909
PJP901 +
2
1 2
2
1 PAD-OPEN 4x4m @ 2 1
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
10U_0805_25VAK
15U_B2_25VM_R100M
@ 1
PD906
1
PC913
PC914
PC915
PC916
PC921
DIO SMF4L22A SOD123FL-2 +
2
2
10U_0805_25VAK
10U_0805_25VAK
PR909 PR910
2_0603_1% 2_0603_1%
1
PC951
PC952
2
2200P_0402_50V7K
PC925
1U_0402_25V6K
1U_0402_25V6K
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V6
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
4.7U_0402_6.3V6M
CSIP_ISL9538 CSIN_ISL9538
1 2
PC1193
RF@ PC1194
RF@ PC1195
RF@ PC1196
1
1
RF@ PC928
@EMC@ PC929
@EMC@ PC956
@EMC@ PC957
1U 25V K X5R 0402
1U 25V K X5R 0402
@EMC@ PC958
@EMC@ PC959
1
1
PC926
PC927
2
RF@
2
2
2
PC930
+SDC_IN
PD901 PR943 ADP_ISL9538 0.22U_0603_25V7K
2 1
2 1 1 2
+PWR_SRC
DIO 30MA 30V 0.5UA 0.4V SOD323-2 0_0603_5% PR914
1
3.3_0603_1%
PD903
PR944
2 1 442K_0402_1%
+VBUS_DC_SS
1
2 2
2
RB520SM-30T2R_EMD2-2
BOOT1_ISL9538
ACIN_ISL9538
CSIP_ISL9538
CSIN_ISL9538
UG1_ISL9538
LX1_ISL9538
LG1_ISL9538
PD904
1
2 1
+DC_IN_SS
1
PC955 PR945 PR915

DIO 30MA 30V 0.5UA 0.4V SOD323-2 0.1U_0402_25V6 100K_0402_5% 4.7_0603_5%VDD_ISL9538
2
1 2
2
PR916
2
PU901
16
15
14
13
12
11
10
33
1_0805_5%~D
9
ISL9538HRTZ-TS2778 TQFN 32P CHARGER
PC931
ADP
CSIP
ASGATE
CSIN
PAD
BOOT1
UGATE1
PHASE1
LGATE1
1
1U_0603_25V6 DCIN_ISL9538
+VCHGR
9
1 2
VDDP_ISL9538 UG1_ISL9538 LG1_ISL9538 LG2_ISL9538 UG2_ISL9538 PQ906
@ PR960 0_0402_5% 17 8 2 1 1 8 8 1
D1
D1
1 2 DCIN VDDP G1 G2 PL902 G2 G1 PR917 EMZB08P03V 1P EDFN3X3-8
VDD_ISL9538 LG2_ISL9538 LX1_ISL9538 LX2_ISL9538
2 1 18
VDD LGATE2
7 PC932 2
S1/D2 D2/S1
7 2.2UH_PCMB103T-2R2MS_13A_20% 7
D2/S1 S1/D2
2 0.005_1206_1% 1 +PBATT
2
1U_0402_6.3V6K 2
@ PR919
ACIN_ISL9538 LX2_ISL9538
PC933 PR918 19 6 3 6 1 2 6 3 1 4 3 5
1U_0402_6.3V6K 0_0402_5% ACIN PHASE2 D1 D2/S1 D2/S1 D1
100K_0402_1% UG2_ISL9538
1 2 OTGEN/CMIN 20 5 PR921 4 5 5 4 2 3
S2
S2
OTGEN/CMIN UGATE2 D1 D2/S1 LX1_ISL9538 LX2_ISL9538 D2/S1 D1
ACAV_IN1 @ PR920 0_0402_5% BOOT2_ISL9538 4.7_0603_5%
1
4
1 2 21 4 2 1 2 1
<35,50> PBAT_CHARGER_SMBDAT
10
10
SDA BOOT2
1
4.7_1206_5%
SNUB_CHG24.7_1206_5%
10U_0805_25VAK
10U_0805_25VAK
1
1@ PR922 20_0402_5% 22 3
EMC@ PR923
EMC@ PR924
PQ909 <35,50> PBAT_CHARGER_SMBCLK PC934 PQ905 PQ904
SCL VSYS
1
1
D
PC935
PC936
PR925 PROCHOT#_ISL9538 CSOP_ISL9538 0.22U_0603_25V7K FDPC5030SG 2N POWER CLIP 56-8 FDPC5030SG 2N POWER CLIP 56-8
OTGPG/CMOUT
2 154K_0402_1% 1@ PR926 0_0402_5%

2 23 2
<12,35,56> PROCHOT# PROCHOT# CSOP
<35> AC_DIS
4700P_0402_25V7K
AMON/BMON
G CSON_ISL9538
2
1
24 1
BATGONE
SNUB_CHG1
<60> PROCHOT#_ISL9538
3
2
ACOK CSON
PC937
L2N7002WT1G 1N SC-70-3 @ PR928 0_0402_5% ACOK_ISL9538 BGATE
CMOP
PROG
1 2 @ PR929 0_0402_5%
PSYS
VBAT
680P_0603_50V7K
680P_0603_50V7K
1 2
1
PR927 +PWR_SRC @
BGATE_ISL9538
2
1M_0402_1% @ PR930 PC938

25
26
27
28
29
30
31
32
1
EMC@ PC940
EMC@ PC941
100K_0402_1% 10P_0402_50V8J
PR931 1 2 1 2 1 2
105K_0402_1%
<35,50> PBAT_PRES# 100K_0402_1%
2
PR932 1
3
1 2 @ PC939 0.1U_0402_25V6 3
BGATE_ISL9538
PR933
VBAT1_ISL9538
100K_0402_1%
1 2
+3.3V_ALW PR951
2
@ 0_0402_5%
1 2
<60> CMOUT
COMP_ISL9538 @ PC942
1U 25V K X5R 0402
1 2
499_0402_1%
1
PR934
0.1U_0402_25V6
560P_0402_50V7K
0_0402_5%
PR937
1
1
0_0402_5%
0_0402_5%
12.7K_0402_1%
PC947
1_0603_1%
1
1 2
@ PC943
@ PR947
@ PR936
@ PR948
2
2
PC945
2
1U_0402_25V6M PR938
0.01UF_0402_25V7K
2
1
PC944
1_0603_1%
2
1
PR935
1 2
2
I_BATT
I_ADP
@ PC946 LM393_P
0.22U_0402_25V6K @ PR950
I_SYS <35,56> 1 2 0_0402_5%
1 2
I_ADP <35> PD905

PR939 BAT54CW-7-F SOT-323 PC949
I_BATT <35> @ 0_0402_5% 0.1U_0402_10V7K
<26,60> AC1_DISC# 1 2 3 1 2
PU903
For PSYS Setting +PBATT PR941 1 MC74VHC1G08DFT2G SC70 5P
5
@ 0_0402_5% @ PR946
2 1 1 2 2 1 0_0402_5% For IT8010 voltage
P
<35,50,60> HW_ACAVIN_NB B <35> ACAV_IN
4 1 2
ACAV_IN1 leakage issue
100K_0402_1%
Y
1
PR948 @U42 PR948 @U22 PR940 1 2 2 PR953
A
2
G
PR961
4
100_0402_5% 100K_0402_1% 4
Close to EC ADP_I pin @ PC950 @ PR942 1 2
3
0.1U_0402_25V6 0_0402_5%
1
2
11.8K +-1% 0402 12.7K_0402_1%
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_charger_ISL9538
A B C D
5 4 3 2 1
PD1202
S SCH DIO 5A 100V 15UA 0.88V TO227-3
2
1
3
DCIN_AC_Detector
@ PC1201
0.01UF 25V +-10% X7R 0402
1 2 S4 S5
PQ1213 +VBUS_DC_SS PQ1202
+3.3V_VDD_DCIN PD1801 EMZB08P03V 1P EDFN3X3-8 EMZB08P03V 1P EDFN3X3-8
+DC_IN +3.3V_VDD_DCIN
3 +3.3V_VDD_DCIN +AC_IN 1 1
2 2
D 1 3 5 5 3
+SDC_IN D
LM393_P
1
0.47U 25V K X7R 0603
1500P_0402_50V7K

2 PR1251 PR1202
PC1202
+3.3V_VDD_PIC
1
PQ1215
PQ1203
300K_0402_5% 300K_0402_5%
499K_0402_1%
1
BAT54CW-7-F SOT-323
499K_0402_1%
3
3
S S
PR1203
PR1205
PC1203
2
2
2PR1207
1.8M_0402_1% 2 G
2
G
2
1
1 2
2
1
PR1206 D D +3.3V_VDD_PIC
1
1K_0402_1% PR1252
LM393_P
100K_0402_5% PR1209
240K_0402_1%
1
+3.3V_VDD_PIC 100K_0402_5%
102K_0402_1%
1
PR1201
49.9K_0402_1%
1
1
PR1208
PR1212
2
PR1253 PR1213 PR1214
PU1201A
6
100K_0402_5% 49.9K_0402_1% 100K_0402_5%
2
3
LM393DGKR_VSSOP8
6 2
3
PQ1214A
HW_ACAVIN_NB EN_PD_HV_1#
P
3 2
2
+ 1 2
(> 1 7 . 6 V )
PQ1204B
2 O 5 1 2
-
G
<35,50,59,60> HW_ACAVIN_NB
PQ1201A
<35,60> VBUS1_ECOK
1
PR1220
3
2
@ PR1218
PQ1201B
VBUS1_ECOK
4
4
23.2K_0402_1%
1200P_0402_50V7K
100P_0402_50V8J~D
220P_0402_50V8J~D
1
1 2 5 0_0402_5%
84.5K_0402_1%
1
PQ1214B
PR1219
PC1205
PC1206
<26,60> EN_PD_HV_1
1
1
100K_0402_5%
5
PR1217
PC1207
4
0_0402_5%
1
@ PR1216
PR1262
2
0_0402_5% @
2
6
2
PR1222
2
100K_0402_5% PR1223
PQ1204A
2
2 1 2
AC_DISC# <35,50,60>
1
0_0402_5%
PC1204 @
0.1U_0402_10V7K
2 1 +3.3V_VDD_PIC
PR1210 @ PR1254
1M_0402_5% 0_0402_5%
2 1 1 2
PU1200
5
@ PJP1202 @ PR1211 0_0402_5% MC74VHC1G08DFT2G SC70 5P
1 2 1 2 1
P
1 2 <26,60> EN_PD_HV_1 B 4
(From TI GPIO1) 1 2 2 O
C S3 JUMP_43X118 C
G
@ PR1215 A
EMI Part 0_0402_5%
+TBTA_Vbus_1
3
EMC@ PL1201 PQ1206
5A_Z80_20M_0805_2P EMZB08P03V 1P EDFN3X3-8
1 2 1
+TBTA_Vbus_1 2
1 2 5 3
+TBTA_VBUS PL1202 PQ1205
5A_Z80_20M_0805_2P @ PR1221 L2N7002WT1G_SC70-3
100P_0402_50V8J
100P_0402_50V8J
EMC@ 0_0402_5%
100K_0402_5%
4
1
1 2 3 1
D
<35> DCIN1_EN
0.1U_0402_25V6
1000P_0402_50V7K
1500P_0402_50V7K
1
1
@EMC@ PC1215
EMC@ PC1208
@EMC@ PC1209
PR1227
EMC@ PC1216
499K_0402_1%
2
+3.3V_ALW +3.3V_ALW
G
PC1210
PR1228
2
2
1
2
100K_0402_5%
2
2
100K_0402_5%
2
1
@ PR1255 @ PR1235
PR1226
0_0402_5%
150K_0402_1% @ PR1233
PR1224
@ PR1225
100K_0402_5%
2
@ PR1242 100K_0402_5% +3.3V_ALW
1
0_0402_5%
1
1 2
<35,50> VBUS2_ECOK
2
1 2
<35,60> VBUS1_ECOK
1 PR1231 CMOUT <59>
@ PR1257 100K_0402_5%
+3.3V_VDD_PIC 0_0402_5% AC_DISC# <35,50,60>
+3.3V_ALW @ PR1245
1
PR1229 +3.3V_ALW 0_0402_5%
49.9K_0402_1% 1 2
2
S TR DMN65D8LDW-7 2N SOT363-6
+TBTA_Vbus_1 +3.3V_VDD_PIC
3
+3.3V_ALW D D D D
S3 OVP
PQ1211A
2 5 2 5
PQ1210B
@ PD1205 PR1234 G G G G
PQ1211B
DIO 30MA 30V 0.5UA 0.4V SOD323-2 100K_0402_5%
1
2
1 2 +3.3V_VDD_PIC S S S S
100K_0402_1%
4
@ PR1238
PQ1210A
0_0402_5% PR1259
PR1237
1 2 100K_0402_5% +3.3V_ALW
2
6
@ PR1260 D
PQ1208A
2
@ PR1236 0_0402_5% 2
<26,60> EN_PD_HV_1
1500P_0402_50V7K
1
100K_0402_5% 1 2 G +3.3V_ALW
150K_0402_1%
1
1
PR1240
PC1217
LM393_P
3
100K_0402_1% PQ1209A D PR1230
PQ1208B
PR1239
S
1
2
B 2 DMN65D8LDW-7_SOT363-6 1 2 5 100K_0402_5% B
<26,59> AC1_DISC#
2
G
2
PU1201B
3
@ PR1244 PR1232 @ PROCHOT#_ISL9538 <59>

2
1
8
@ LM393DGKR_VSSOP8 @ PR1243 0_0402_5% S 100K_0402_5%
4
5 0_0402_5% @ PR1261
P
1
+ D
L2N7002WT1G_SC70-3
7 1 2 5 PQ1209B 0_0402_5% D
100P_0402_50V8J
1200P_0402_50V7K
6 O 1 2 2 2
PQ1216
PQ1207A
-
G
1
0.01UF_0402_25V7K
DMN65D8LDW-7_SOT363-6 @ PR1241 G S TR DMN65D8LDW-7 2N SOT363-6 G

100K_0402_1%
100K_0402_1%
4
100P_0402_50V8J
1
3
0_0402_5% D
PC1211
PC1213
S
4
3
1
1 2 5
PR1246
PR1247
PC1212
PC1214
<35,50,59,60> HW_ACAVIN_NB S
1
G PQ1207B
2
@ @ S TR DMN65D8LDW-7 2N SOT363-6
2
@ @ S
2
4
@
1 2
OVP set t i ng: 5. 5
V @ PR1258
0_0402_5%
L2N7002WT1G_SC70-3
@ PR1248 PT1
D
1
0_0402_5% LPS_PROTECT# PAD~D

2 1 2
PQ1212
G
1
S @ PR1250 (From EC)

3
PR1249 0_0402_5%
10K_0402_5% 1 2
EN_PD_HV_1 <26,60>
2
A A
Title
Breckenridge_TypeC_PD
Siz e Document Number Re v
0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-F391P
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R.

List ) Request
Item Page# Title Date Owner Issue Solution Rev.
Description Description
D D
53 RF pop PC100,PC103,PC115,PC116,PC131,PC132,PC151,PC152,
54 Add RF team portion 2017 PC153,PC231,PC301,PC303,PC409,PC418,PC695,PC696, X00
1 56 04/06 Compal RF request & modify Components PC903,PC928,PC1191,PC1192,PC1193,PC1194,PC1195,
57 PC1196
2 2017 Compal Change DrMOS from TI to Fairchild DrMOS change from CSD97396 to FDMF3035 X01
58 Change DrMOS 06/08
1. Depop PC133, PC134, PC135, PC136, PC137, PC138,PC139,PC140, PC689,

51 PC690, PC691, PC692, PC956, PC957,PC958, PC959
3 57 2017 EMI request & modify Components X01
Add EMI portion 06/09 Compal 2. Pop PL901.
59
53
54 Add RF team portion 2017 RF pop PC1198,PC1199 X01
4 56 06/13 Compal RF request & modify Components
57
C 1. Remove PC917, PC918, PC919, PC920 , add PC921 B2 POS CAP C

56 2. CPU input MLCC size change from 0805 to 0603 low noise MLCC
57 2017 For acoustic solution X01
5 Acoustic solution 06/13 Compal CPU input MLCC change to 0603 low noise MLCC PC608, PC612, PC656, PC657, PC658, PC664, PC665, PC672, PC673, PC674,
59 PC675, PC682, PC683, PC684
3. Pop PC607
Change Charger X01

59 Dual-MOS 2017 Compal Dual-MOS change from CSD87351 to AOE6936
6 06/13 Change Dual-MOS from TI to AOS
Tpye-C PD Bead EOL ,so change BR_MLK12_14_15 PL1201/PL1202 Bead

2017 to 80 ohm bead, X02
7 60 EMI portion 07/28 Compal EMI request & modify Components Change SM01000P200 to SM01000U400
2017 X02
ALL Change MLCC PN 07/31 Compal Change MLCC P/N L-end to 0-end 0-end P/N for all MLCC cap
8
For ISL9538 PSYS Setting PR948 change value
B Add Charger portion B
2017 1.UMA U42 change from
9 59 08/03 Compal Intersil FAE request PSYS Setting SD034127280(12.7kohm) to SD034118280 (11.8kohm) X02
2.UMA U22 keep SD034127280(12.7kohm)
59 Change Charger 2017 Change current sense for component derating PR937,PR938,PR909,PR910,PR915 change 0402 to 0603
10 Compal by Intersil FAE confirm X02
61 portion 08/11 SD00001QK80
ALL 0 ohm short pad 2017 Compal For 0ohm no short pad:
11 08/11 0hom change to 0 ohm short pad
U42 DSC:Keep PR943,PR421,PR671,PR692 pop SD028000080 X02
12 59 Change Charger 2017 Power request Add PD906 SC40000EL00 before PL901 Isum choke
portion 08/11 Compal (SC40000EL00- S ZEN DIO SMF4L22A SOD123FL-2) X02
13
A A
Title
PWR P.I.R
LA-F391P
5 4 3 2 1
5 4 3 2 1

List ) Request
Item Page# Title Date Owner Issue Solution Rev.
D D
Tune value for ISL95857A R,C match
IMVP8 CPU
13 56 Controller 2017
08/11 Compal Intersil FAE request U42
Portion 1. Change PC624 SE068103K80 to SE075153K80(0.015uF)
2. Change the PR629 from 86.6kOhm to 88.7kOhm. ( IMON of GT ) X02
3. Change the PC642 from 0.033uF to 0.022uF. ( RC Match of GT )
U22
1. Change PC624 SE068103K80 to SE076223K80(0.022uF)
2. Change the PR638 from 383 Ohm to 365 Ohm
59 Change Charger 2017 Buyer request PD901,PD904 change from SCS0340L010 to SCS00009P00, for common part X02
14 portion 08/11 Compal
15
C C
16
17
18
19
B B
20
21
22
23
A A
24
25 Title
PWR P.I.R
LA-F391P
5 4 3 2 1
5 4 3 2 1

List ) Request Owner Issue Solution
Item Page# Title Date Rev.
D D
1 40 M2 2280 2017/03/9 EE For align with spindle HDD. Add UZ37 circuit for 2280 SSD imdenpenden loadswitch 0.1(X00)
Socket --> add CN50~51, UZ37, PJP30_1*2(and no stuff all)
2 All All 2017/03/9 EE X9 request UC1 CPU change from U22 to U42. 0.1(X00)
3 11 CPU (6/14) 2017/03/14 EE KBL-R U42 X'tal Add RC417~RC422,CC334,CC335, YC3 for U42 crystal 0.1(X00)
4 34 USH & TPM 2017/03/17 EE Prevent POA_WAKE# ESD Add RZ364 100 ohm to POA_WAKE# 0.1(X00)
5 All All 2017/03/17 EE Remove IO expander 1-1.Delete expander IO UE2 relating circuit(RE524,@RE525 change to 0 ohm) 0.1(X00)
remove UE2, CE1, CE2, RE13~18, RE6, CE500, CE504, CE505
4/13 add UMA RE524/525(2.2kohm)--> B6/F7
4/17 B6/F7 change netname to GPU_SMDAT/CLK
1-2. GPIO change (RE374 reserve)
PCH_RSMRST#_GPIO204 -> USH_PWR_STATE# (delete RE363)
PORT80_DET# -> DCIN1_EN (delete RE512,RE513,RZ131)
SHD_IO3 -> VBUS1_ECOK (delete RE366~RE373, RE376,RE377,RE98,UE9)
C
SHD_IO1 -> SATA_LED_EN C
ENVDD_PCH -> DCIN2_EN
SIO_RCIN#_EC -> VBUS2_ECOK
1-3 For DSC (keep RE524, RE525)change name GPU_SMDAT/GPU_SMCLK
SIO_EXT_SCI#_EC -> GPU_PWR_LEVEL (delete RE341)
EXPANDER_GPU_SMCLK -> DGPU_PWROK
RTCRST_ON_GPIO141(B6) -> GPU_SMDAT
X(F7) -> GPU_SMCLK
6 36 MEC5105 2017/03/24 EE Remove Reset Threshold circuit 1. Delete UE7 relating circuit. keep RE536 only 0.1(X00)
Support remove UE7, QE13, RE34, RE348, RE536, RE537, RE530
CE5, CE6, CE503
add RE536 on EC side
7 All All 2017/03/24 EE Add RTC reset circuit 1. RTCRST_ON_GPIO122 change to RTCRST_ON... 0.1(X00)
2-1. +RTC_CELL_PCH circuit (Dell request)
Delete RE514,RE515...
Add QE14~QE17...
Add RE540~RE546...
B B
Add CE63...
Change RC56.2 net name to +RTC_CELL_PCH...
Change UC1.AK19, UC1.BB14 net name to +RTC_CELL_PCH...
2-2.based on AR D 1 . 3 加
加加 R T C c i r c u
t 增加 R
i E5 5 1 避避 +R T C_ C E
L H沒
L_P C沒.
3. +3.3V_ALW_DSW enable circuit (Dell request)
Delete RE524...
Add RC431~RC433...
Add UC13,UC14...
Change UE1.M7 net name to VCCDSW_EN_GPIO...
4. GPIO change
USH_SMBCLK -> USH_EXPANDER_SMBCLK
USH_SMBDAT -> USH_EXPANDER_SMBDAT
Delete RTCRST_ON_GPIO141
PRIM_PWRGD_GPIO024 -> RESET_IN#
5. UC13 chante to QC6, UC14 change to QC7
4/17 RTC power Gate circuit rev.2
Delete RE540, RE542, RE544, RE545, QE14, QE16
Change RE543 to 1M ohm and RE546 to 10K ohm
Add DE2, CE65,
Reserve CE66 for VCCDSW_EN
A A
Title
EE P.I.R (1/8)
LA-F391P
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )

Request Issue Solution
Item Page# Title Date Owner Rev.
D D
8 All All 2017/03/14 EE co-lay DS3/non-DS3 1. DS3 / non-DS3 co-lay 0.1(X00)
Add DC2, (DC1 add NDS3 @)
Add RC501, RC503, RC505 for DS3
Add RC502, RC504, RC506 for Non-DS3
Use the original 0ohm, RC215 instead of RC504, RE536 instead of RC503
3/14
1. based on EDS that add RC503 / RC504 on SUSACK # / ME_SUS_PWR_ACK for DS3
2. UZ3 enable pin change netname to PCH_PRIM_EN
3. RE349 + DS3 @
4. UZ34 input in form SIO_SLP_SUS # to PCH_PRIM_EN
3/15
1. For align KW that change as below "Part Reference"
A RC501 -> RC439
B. RC502 -> RC440
C. RC503 -> RC443
D RC504 -> RC444
E. RC505 -> RC441
F RC506 -> RC442
3/27
Parallel 0ohm in DC2, reserved to avoid NDS3 @, EC too late to load code
C
4/17 RTC Power Gate Circuit option C
RC445 change to connect to VCCDSW_EN and pop
9 09 CPU (4/14) 2017/03/27 EE For antenna request 1. Add RC434, RC435 0ohm for JUART1 power option 0.1(X00)
4/17 JUART whether pin swap, Align with SB.
--> Pin swap align SB
--> EVT phase pop JUART, DVT phase remove
4/20
2. Remove RC435
10 38 USH & TPM 2017/03/27 EE Prevent contactless_det# backdrive 1. Add DZ8 to prevent contactless_det# backdrive 0.1(X00)
USH & TPM

1. TPM
11 37 2017/03/15 EE TPM650 include a. Delete RZ113, RZ111, QZ9 0.1(X00)
b. Add RZ365 and connect to +UZ12_TPM
Add RZ366 and connect to +3.3V_M_TPM
CPU (8/14)
UC1.F65 & G65 to GND
B 12 13 2017/03/15 EE Follow CRB add RC436 to GND before UC1.F65 & G65 0.1(X00) B
13 16 CPU (11/14) 2017/03/15 EE Follow MOW08 UC1.K52/AK52 Must be NOT connected 0.1(X00)
14 10 CPU (5/14) 2017/03/28 EE X9 Port MAP check 1. USB3.0 port1 with port6 swap 0.1(X00)
2. USB2.0 port1 with port9 swap
15 9 CPU (4/14) 2017/03/29 EE For Layout power trace add +UART1_R power netname on JUART1 0.1(X00)
16 8 CPU (3/14) 2017/03/29 ME Connector check JSPI1 change from ENTERY_SP01001FW00 to ACES_SP01001CB10 0.1(X00)
Card Reader
17 31,11 RTS5242 2017/03/29 EMI EMI request 1. RR5~RR10 change to 0ohm 0.1(X00)
CPU (6/14) 2. RC417~RC420 change from 0ohm to 33ohm
18 28 USB 3.0 CONN 2017/03/29 ESD ESD request 1. Change DT7, DT8, DT11, DT12 to DT39 0.1(X00)
TYPE C 2. Change DT15, DT16, DT19, DT20 to DT40
A A
Title
EE P.I.R (2/8)
LA-F391P
5 4 3 2 1
5 4 3 2 1

Request Issue Solution
Item Page# Title Date Owner Rev.
D D
19 16 CPU (11/14) 2017/03/29 EE For BRMLK12 layout request Let AK70,BB57,BB66,AU58,AU63 flooting 0.1(X00)
All
1-1.change Source 1:3 demultiplexer(PS8348B) to 1:2 demultiplexer(PS8338B)
20 All 2017/03/31 EE Follow ARD1.3 remove WIGIG 1-2,remove RV71, RC74, RV77, CV80
2-1. (DP)JNGFF1 remove CV145~150, CV152, CV153, CV156, CV157 0.1(X00)
2-2. (PCIE)JNGFF1 remove CZ14, CZ15
UC1 remove RC375
21 37 USH & TPM 2017/03/31 EE TPM NPCT65X and NPCT75X schematic colay UZ12 relating circuit and change UZ12 to SA0000AQ200 0.1(X00)
22 35 EC MEC5105 2017/04/05 EE RTCRST_ON glitch Reserve CE64 0.1(X00)
23 8 CPU (3/14) 2017/04/05 EE Winbond 16MB SPI ROM EOL (change to J-die) Change UC5, UC6 to SA00005VV20 0.1(X00)
24 26 [Type C]PD 2017/04/05 EE Change PD to PD3.0 Change UT5 to SA0000AP500 0.1(X00)

Controller TI
25 36 MEC5105 2017/04/05 EE Board ID define change change RE79 to 240K for X00 0.1(X00)
Support
C C
All
1. rename form AUD_NB_MUTE# to NB_MUTE# for EC team request
26 All 2017/04/05 EE EC GPIO check 2. rename form SYS_LED_MASK# to LED_MASK# for EC team request 0.1(X00)
3. change net name form THERMATRIP1# to THERMTRIP1# for EC team request
4. swap WWAN_RADIO_DIS# from UE1.M2 to UE1.F12
5. swap LCD_TST from UE1.D1 to UE1.M2
All
1. rename form FAN1_TACH to TACH_FAN1 for EC team request
27 All 2017/04/06 EE EC GPIO check 2. DSC_swap DGPU_PWR_EN to GPIO100 for save level shift at BR MLK project
3-1. DSC_swap GPU_PWR_LEVEL to GPIO126 for save level shift at BR MLK projcet
3-2. DSC_ remove RE5 of GPIO126,
3-3. UMA_remove RE341 of SIO_EXT_SCI# 0.1(X00)
4. SYS_PWROK reserved 0ohm add netname to RESET_OUT
5. rename form ME_FW_EC to ME_FWP for EC team request
rename from ME_FWP to ME_FWP_PCH
6. rename from THERMATRIP2# to THERMTRIP2# for EC team request
7. rename from HW_GPS_DISABLE# to GPS_DISABLE# for EC team request
8-1. rename from VGA_ID to VGA_IDENTIFY for EC team request
8-2. swap to GPIO035 form GPIO017 for ECteam suggestion BEEP need
change to PWM function
8-3. Swap BEEP pin to GPIO035 form GPIO017 EC team request.
B 9. rename from H_PROCHOT# to PROCHOT# for EC team request B
10. rename from USB_PWR_SHR_VBUS_EN to USB_POWERSHARE_VBUS_EN for

EC team request
28 47 Power 2017/04/07 EE +5V_RUN discharge circuit for S3 1. Add but not stuff QZ4 and RZ370 0.1(X00)
control no power issue 2. Add zener diode DE1 (no stuff) for + 5V_RUN discharge
3. RZ370 into 0603 packaging, add net name
29 8 CPU (3/14) 2017/04/07 ME JSPI1 footprint pin1 Reversal 180 of Symbol reverses 180 degrees 0.1(X00)
ENTERY to ACES
30 24 DP to VGA & 2017/04/07 EE When the system can not read the VGA EDID, reserve RV620 PU to +3.3V_RUN 0.1(X00)
VGA Conn the maximum resolution will be pressed ** Pop RV620
at 1024x768
31 36 MEC5105 2017/04/07 EE To increase power current rail for RE71 changed to SD034100A80, that change 49.9 to 10ohm 0.1(X00)
Support each debug card current limiting resistor to smaller.
A A
Title
EE P.I.R (4/8)
LA-F391P
5 4 3 2 1
5 4 3 2 1

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D D
32 All All 2017/04/07 EE EC GPIO check 1. rename from USB_PWR_SHR_LFT_EN# to USB_POWERSHARE_EN# for 0.1(X00)
EC team request
All
1. 3.3V_TS_EN rename to PCH_3.3_TS_EN
33 All 2017/04/10 EE EC GPIO check SHD_IO0 change to 3.3V_TS_EN and delete RE366 and PU 100K RE547 0.1(X00)
Add RV323/RV324 for 3.3V_TS_EN/PCH_3.3V_TS_EN option
2. SHD_CLK -> PS_ID and delete RE374
3. CLKRUN#_EC -> ENABLE_DS# and delete RE337 and add RE549, RE550
4. change net name form PANEL_ID to SYSTEM_ID
5 .SIO_EXT_SMI#_EC -> free and delete RE338
6. SIO_RCIN#_EC -> VBUS2_ECOK and delete RE339/RC13
7. rename from SATA_LED_EN to MASK_SATA_LED# for EC team request
8. rename form FAN1_PWM_1 to PWM_FAN1 for EC team request
9.GPIO054(PS_ID) swap to GPIO056 for EC team request
10. PCH_ALW_ON keep GPIO231 and assign DCIN2_EN to GPIO107
11. EXPANDER_GPU_SMCLK -> free and delete RE525
12. this pin should be change to reserved,Current EC no use PCH_ALW_ON
to control +3.3V_ALW_PCH, it control by SIO_SLP_SUS# directly
13. rename from SLOT2_CONFIG_1 to NGFF_CONFIG_1 for EC team request
14. rename from ACAV_IN_NB to HW_ACAVIN_NB for EC team request
C 15. rename from SLOT2_CONFIG_0 to NGFF_CONFIG_0 for EC team request C
17. rename from LID_CL_NB# to LID_CL_SIO# for EC team request
All
1. Follow SB reserve CLKDET# net,for x7~x8 no use
34 All 2017/04/11 EE PCH GPIO check 2. Follow SB reserve CLKRUN# net,for no use LPC mode 0.1(X00)
3. DEL SIO_RCIN# net,for no use LPC mode
4. Follow SB reserve SIO_EXT_SCI#,for no use LPC mode
5. Rename PCH_3.3V_TS_EN from 3.3V_TS_EN
6. Follow SB reserve PCI_CLK_LPC1, for no use LPC mode
7. Follow SB reserve PME#, for no use LPC mode
8. Follow SB reserve SIO_EXT_SMI# net, for no use LPC mode
35 All All 2017/04/11 EE Following port MAP LOM port to be replaced to port 4 0.1(X00)
36 All All 2017/04/13 EMI EMI request change 0ohm short pad to 0ohm of as below. 0.1(X00)
RC328,RT54~57,RZ56,RN99
B B
37 All All 2017/04/17 EE For All of Repeater 4/17 PWD pin setting double check for all of redrive(dual, signal, USB3) 0.1(X00)
4/21
UMA
1. SATA repeater --> add QN6, RN226, RN227
2. PCIE/SATA repeater --> add QN7, RN228,RN229,RN230
DSC
1. PCIE/SATA repeater --> add QN6, RN226, RN227
38 All All 2017/04/17 EE GPIO map change 4/17 PCH_3.3V_TS_EN PU +3.3V_RUN change page to QV7.2 0.1(X00)
-->Add RV326 and depop RC282/RE547 for 3.3V_TS_EN/PCH_3.3V_TS_EN
1. RC443 BOM structure change to @
2. UMA : GPIO126->GPU_PWR_LEVEL
3. Add RTCRST_ON_R net neme for QE17.2
4. Add SIO_SLP_SUS#_R net name and PU RE561
5. RC27.2->NC for CLKRUN#
6. UMA : HDD_DET#->SATAGP0
7. Remove RE360/RE364 .
A A
Title
EE P.I.R (3/8)
LA-F391P
5 4 3 2 1
5 4 3 2 1

Request
D D
39 47 Power control 2017/04/19 EE EC request to reseve OR gate for Reserve DZ9 0.1(X00)
WLAN power EN 4/20 RZ38 PD change to WLAN_PWR_EN_UZ2
40 36 MEC5105 2017/04/19 EE EC request to reseve ESPI_RESET# for JESPI Reserve RE560 0.1(X00)
Support
41 All All 2017/04/19 EE OTG support Pop RT74, Depop RC337 0.1(X00)
4/20 RC337 10K to GND
EC MEC5105
Add test point T141 for UE1.D1->GPIO051
42 35 2017/04/19 EE Dell request to add test point for Add test point T142 for UE1.L11->GPIO054 0.1(X00)
EC free pins Add test point T264 for UE1.F13->VBUS3_ECOK
Add test point T143 for UE1.K7->GPIO011
Add test point T144 for UE1.M1->GPIO100
Add test point T262 for UE1.J6->GPIO202
Add test point T147 for UE1.M4->DGPU_PWROK only UMA
43 38 USH & TPM 2017/04/19 EE JUSH1 add net name 1. Add net name at DZ8.1 . 0.1(X00)
C 44 37 USH & TPM 2017/04/21 EE TPM change to NPCT650x Change UZ12 to SA00008EL80 and related resistors 0.1(X00) C
USH & TPM

1. The pop option for VHIO power:
45 37 2017/04/24 EE BOM option by “ 650@” o r “ 750@ NPCT750: VHIO=+3.3V_RUN 0.1(X00)
NPCT650: VHIO=+3.3V_ALW_PCH
2. The pop option for SLP_S0# connection:
NPCT750: pop RZ112 (SLP_S0#=GPIO0)
NPCT650: pop RZ363 (SLP_S0#=GPIO2)
3. RZ62 can be removed
46 9 CPU (4/14) 2017/04/24 EE JUART1 remove remvoe JUART1, RC434 0.1(X00)
47 11 CPU (6/14) 2017/04/24 EE Schematic align INTRUDER# PU change to +RTC_CELL_PCH 0.1(X00)
48 All All 2017/04/24 EE GPIO map change GPIO013 net name change to DGPU_PWROK 0.1(X00)
UPD1_ALERT#-->UPD1_SMBINT#
UPD1_SMBUS_ALERT#-->UPD1_SMBINT#_R
B 49 34 Codec ALC3253 2017/03/31 EE Follow ARD1.3 change Codec to 3254 Change Codec schematic from ALC3253 to ALC3254 0.1(X00) B
50 34 Codec ALC3253 2017/04/13 EE Swap ESD diode pin for layout DT39 & DT40 swap pin 0.1(X00)
A A
Title
EE P.I.R (5/8)
LA-F391P
5 4 3 2 1
5 4 3 2 1

Request
D D
32 All All 2017/04/07 EE EC GPIO check 1. rename from USB_PWR_SHR_LFT_EN# to USB_POWERSHARE_EN# for 0.1(X00)
EC team request
All
1. 3.3V_TS_EN rename to PCH_3.3_TS_EN
33 All 2017/04/10 EE EC GPIO check SHD_IO0 change to 3.3V_TS_EN and delete RE366 and PU 100K RE547 0.1(X00)
Add RV323/RV324 for 3.3V_TS_EN/PCH_3.3V_TS_EN option
2. SHD_CLK -> PS_ID and delete RE374
3. CLKRUN#_EC -> ENABLE_DS# and delete RE337 and add RE549, RE550
4. change net name form PANEL_ID to SYSTEM_ID
5 .SIO_EXT_SMI#_EC -> free and delete RE338
6. SIO_RCIN#_EC -> VBUS2_ECOK and delete RE339/RC13
7. rename from SATA_LED_EN to MASK_SATA_LED# for EC team request
8. rename form FAN1_PWM_1 to PWM_FAN1 for EC team request
9.GPIO054(PS_ID) swap to GPIO056 for EC team request
10. PCH_ALW_ON keep GPIO231 and assign DCIN2_EN to GPIO107
11. EXPANDER_GPU_SMCLK -> free and delete RE525
12. this pin should be change to reserved,Current EC no use PCH_ALW_ON
to control +3.3V_ALW_PCH, it control by SIO_SLP_SUS# directly
14. rename from ACAV_IN_NB to HW_ACAVIN_NB for EC team request
C 15. rename from SLOT2_CONFIG_0 to NGFF_CONFIG_0 for EC team request C
17. rename from LID_CL_NB# to LID_CL_SIO# for EC team request
All
1. Follow SB reserve CLKDET# net,for x7~x8 no use
34 All 2017/04/11 EE PCH GPIO check 2. Follow SB reserve CLKRUN# net,for no use LPC mode 0.1(X00)
3. DEL SIO_RCIN# net,for no use LPC mode
4. Follow SB reserve SIO_EXT_SCI#,for no use LPC mode
5. Rename PCH_3.3V_TS_EN from 3.3V_TS_EN
6. Follow SB reserve PCI_CLK_LPC1, for no use LPC mode
7. Follow SB reserve PME#, for no use LPC mode
8. Follow SB reserve SIO_EXT_SMI# net, for no use LPC mode
35 All All 2017/04/11 EE Following port MAP LOM port to be replaced to port 4 0.1(X00)
36 All All 2017/04/13 EMI EMI request change 0ohm short pad to 0ohm of as below. 0.1(X00)
RC328,RT54~57,RZ56,RN99
B B
37 All All 2017/04/17 EE For All of Repeater 4/17 PWD pin setting double check for all of redrive(dual, signal, USB3) 0.1(X00)
4/21
UMA
1. SATA repeater --> add QN6, RN226, RN227
2. PCIE/SATA repeater --> add QN7, RN228,RN229,RN230
DSC
1. PCIE/SATA repeater --> add QN6, RN226, RN227
38 All All 2017/04/17 EE GPIO map change 4/17 PCH_3.3V_TS_EN PU +3.3V_RUN change page to QV7.2 0.1(X00)
-->Add RV326 and depop RC282/RE547 for 3.3V_TS_EN/PCH_3.3V_TS_EN
1. RC443 BOM structure change to @
2. UMA : GPIO126->GPU_PWR_LEVEL
3. Add RTCRST_ON_R net neme for QE17.2
4. Add SIO_SLP_SUS#_R net name and PU RE561
5. RC27.2->NC for CLKRUN#
6. UMA : HDD_DET#->SATAGP0
7. Remove RE360/RE364 .
A A
Title
EE P.I.R (6/8)
LA-F391P
5 4 3 2 1
5 4 3 2 1

Request
D D
39 35 MEC5105 ESPI 2017/06/06 EE GPIO map change UPD2_ALERT#-->UPD2_SMBINT# 0.2(X01)
EC
40 47 Power control 2017/06/06 EE Change netname align with SB WLAN_PWR_EN_U2--> WLAN_PWR_EN 0.2(X01)
RC437.2 --> +VCC_GT_K52
41 16 MCP(11/14) 2017/06/06 EE Add netname for layout RC438.1 --> +VCC_GT_AK52 0.2(X01)
PWR-VCCGT
42 47 MEC5105 ESPI 2017/06/06 EE EC request to reseve OR gate for Add QZ15 and RZ518 0.2(X01)
Power control WLAN power EN Change SIO_SLP_WLAN# to SLP_WLAN#_GATE (EC side UE1.K10) & Add RE552
43 26 [Type C]PD 2017/06/06 EE PD ROM main source change UT6 change to SA000095R10 (GD) 0.2(X01)
Controller TI-1
44 11 MCP(6/14) 2017/06/07 EE Schematic align, avoid SUSACK#_R floating Reserve RC551 0.2(X01)
CLK,PM,RTC
45 37 NuvotonTPM1.2 2017/06/07 EE Nuvoton request to change TPM_PIRQ# power rail TPM_PIRQ# power rail change to +3.3V_ALW_PCH 0.2(X01)
TPM change to NPCT750 Change UZ12 to SA0000AQ200 and related resistors
46 24 DP to VGA & 2017/06/07 EE RTD2166 question UV6.12 add RV622 PU to +3.3V_RUN 0.2(X01)
C VGA ConnRTD2166 C
47 28 [Type C]USB 3.0 2017/06/07 ESD ESD request DT10, DT13, DT14, DT17,DT18,DT5,DT6,DT9 change from 0.2(X01)
CONN TYPEC1 SC40000AT00 to SC40000DF00
48 33 NuvotonTPM1.2 2017/06/07 EE For RBOM request. CZ75 from 4.7uF to 10uF 0.2(X01)
49 33 NGFF Card 2017/06/07 EE Correct the symbol Update JNGFF1/JNGFF2 symbols 0.2(X01)
50 20,36 All 2017/06/08 EE Main source change UD1, UE4, UE6 change to SA00007WE00 0.2(X01)
51 46 All 2017/06/08 DFB DFB request PCB hole from 3.2mm to 3.3mm 0.2(X01)
Location:H34,H35
LA13 symbol change to " TAI-T_HCB2012KF-121T50_2P"
52 ALL All 2017/06/12 DELL Dell request to change cap to L-end P/N L-end P/N for all cap 0.2(X01)
MEC5105
53 36 Support 2017/06/14 EE BOARD_ID change Change RE79 to 130Kohm (rev. X01) 0.2(X01)
B B
54 30 LAN 2017/06/14 EMI EMI request add +0.9V_LAN LL2 180 ohm bead 0.2(X01)
55 29 DMIC 2017/06/14 RF RF request CA5,CA6 change to 27pf 0.2(X01)

1-1. pop PJP33
56 41 All 2017/06/15 DELL DELL request 1-2. Non-pop UZ23,CZ129,CZ130,PJP32 0.2(X01)
2-1. del UZ37,CN50,CN51,PJP30
0.2(X01)
57 9 MCP(4/14)GSPI 2017/06/15 EE GPIO map change Add TypeC_CON_SEL1/TypeC_CON_SEL2 for UC1.W4/UC1.AB3
,I2C,UART,ISH Reserve RC553-RC556 for connector selection
58 47 Power Control 2017/06/15 EE EC request to reseve OR gate for WLAN power EN Change QZ15 to SB00000T000 0.2(X01)
A A
Title
EE P.I.R (7/8)
LA-F391P
5 4 3 2 1
5 4 3 2 1

Request
D
All
1-1. pop PJP33 D
59 41 2017/06/15 DELL DELL request 1-2. Non-pop UZ23,CZ129,CZ130,PJP32 0.2(X01)
2-1. del UZ37,CN50,CN51,PJP30
60 9 MCP(4/14)GSPI 2017/06/15 EE GPIO map change Add TypeC_CON_SEL1/TypeC_CON_SEL2 for UC1.W4/UC1.AB3 0.2(X01)
,I2C,UART,ISH Reserve RC553-RC556 for connector selection
61 47 Power Control 2017/06/15 EE EC request to reseve OR gate for WLAN power EN Change QZ15 to SB00000T000 0.2(X01)
62 25 DP/USB Redriver2017/06/15 EE PS8743 colay Add RT410, RT411, RT412,RT413, RT414, RT415, RT416,CT213 0.2(X01)
SW1 TUSB546 Add RT405, RT406, RT407, RT417, RT418
63 30 Codec - 2017/06/16 EMC EMC request CL11,CL12 change to close UL1.46,47 0.2(X01)
ALC3246
64 24 DP to VGA & 2017/06/21 EE RTK suggest LV19/LV20 --> RV650/RV651 改

75 Ω ; 0.2(X01)
VGA ConnRTD2166
CV132/CV133 改
2P
C 65 26 [Type C]PD 2017/06/21 EE TPS65982(UT5) update version DB --> DC (SA0000AX700) 0.2(X01) C

Controller TI-1
66 34 Codec ALC3246 2017/07/26 ESD ESD request DA2, DA6, DA7 change main source from SCA00002900 to SCA00001A00 0.3(X02)
67 ALL All 2017/08/01 EE Change cap to 0-end P/N 0-end P/N for all cap 0.3(X02)
68 26 [Type C]PD 2017/08/02 EE TI TPS65982 request(TBTA_DEBUG4) pop RT407 when pop 8743 & change to 10K 0.3(X02)
Controller TI
69 28 USB 3.0 2017/08/02 EE SE part COS issue. CT99, CT100, CT101, CT102 change to 0.01u_X5R_0201_25V (SE00000YH00) 0.3(X02)
CONN TYPE C
70 25 DP/USB3 Repeater
2017/08/02 EE TI update version(TUSB546A) TUSB546 change form SA00009R710 to SA00009R720 0.3(X02)
SW TUSB546
71 ALL All 2017/08/03 EE To avoid in-rush current caused voltage drop Add soft start solution(only reserved) on QV8,QZ1 0.3(X02)
(add CV635, CZ200, RZ380,RV400)
8/4
Add soft start solution(only reserved) on QE15,QC7
(add CC340,RE565)
B B
72 36 MEC5105 Support
2017/08/08 EE BOARD_ID change Change RE79 to 62Kohm (rev. X02) 0.3(X02)
73 9 CPU (4/14) 2017/08/09 EE TPM Pin connectivity requirement Add RC560,RC561(reserved) BOM options. 0.3(X02)
74 ALL All 2017/08/11 EE Buyer request main source change 0.3(X02)

1 .SC1N4148180 --> SC100005500
2. SC100000S00 --> SCS00003700
75 30 All 2017/08/11 EMI EMI request CL10 depop 0.3(X02)
A A
Title
EE P.I.R (8/8)
LA-F391P
5 4 3 2 1

Dell Latitude 5290 Compal LA-F391P DDM60 Rev1.0 (A00) Схема

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Dell Latitude 5290 Compal LA-F391P DDM60 Rev1.0 (A00) Схема

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A B C D E

BR MLK12 KBL-U UMA

REV :1.0 (A00)

U22@ : KBL-R U22 Component

BreckenridgeMLK 12 UMA Block Diagram Reverse Type

Memory BUS (DDR4) DDR4-SO-DIMM X2

Non-AR Type C CPU&PCH XDP Port

DP1.2 4 lanes AUTOMATIC POWER

CC PD Solut i on USB2.0[1] Fingerprint SPI

P28 P26-27 USH board P39

POWER STATES For Breckenridge12/14/15 UMA

S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON

S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF

PCIE-3 M.2 3030(WLAN) 7 M.2 3030(BT)

PM TABLE PCIE-8 SATA-1 M.2 3042(SATA Cache or HCA)

+1.8V_PRIM +1.0V_VCCST +1.8V_RUN

S5 S4/AC ON OFF OFF

S5 S4/AC doesn't exist OFF OFF OFF

BATTERY AUD_PW R_EN

(PU602) (PU612) CSD97396Q (QV1) +3.3V_LAN

D +3.3V_ALW_PCH 200 DIMM2 D

KBC 2.2K +3.3V_ALW

2.2K +3.3V_ALW +3.3V_TBTA_FLASH

04 C3 UPD1_SMBCLK 0ohm short pad UPD1_SMBCLK_Q B5 PD &

For 2LANE EDP,BR/SB12

UC1I CPU@ KBL-R U4+2

DDR4 COMPENSATION SIGNALS

SOFTWARE TAA RF Request SML0_SMBCLK

PCH_SPI_D1_R1 PCH_SPI_D1_0_R SML0_SMBCLK

<37> PCH_SPI_D0_R1 3 6 LPC@ RC27 8.2K_0402_5%

@ RC30 1K_0402_5% 33_0804_8P4R_5%

UC1F CPU@ KBL-R U4+2

NO REBOOT STRAP POP China TPM

LOW(DEFAULT) REBOOT ENABLE ONE_DIMM#

Vendor JAE FOXCON TBD TBD DELL CONFIDENTIAL/PROPRIETARY

For NON AR, Breckenridge 12/14/15 UMA

2 1 0_0402_5% RB751S40T1G_SOD523-2 0_0402_5%

2 1 KBL-RU42_BGA1356 11 OF 20 connect to VCCMPHYGTAON_1P0 enable pin

DE-POP Support Deep sleep +3.3V_RUN 7 6

10K_0402_5% @ RC225 8.2K_0402_5% @ UC12 SIO_SLP_S0# 14

HIGH ENABLE HIGH DISABLE

CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin

For Skylake , RC120 depop

546765_546765_2014W W 48_Skylake_MOW _Rev_1_0

PROC_SELECT#:This pin is for compatibility

TDO_XDP H_VCCST_PWRGD_XDP CPU_XDP_TRST#

+VCC_CORE: 0.3~1.35V +VCC_CORE +VCC_CORE

Place close CPU side

CAD Note: Place the PU resistors close to CPU

CAD Note: Place the PU resistors close to CPU

RC208close to CPU 300 - 1500mils

KBL-R 4+2 and KBL-U 2+2&2+3e opt i on ( pl ace on po wer page)

UC1M CPU@ KBL-R U4+2

N63 VCCGT VCCGTX_AM56 AM58

N64 VCCGT VCCGTX_AM58 AU58

22U_0603_6.3V6M BB32 AM30

CC296 BB41 AM42

VCCST VCCSA J22

VCCSTG_A22 VCCSA J27

+1.0V_VCCST source +1.0V_VCCSTG source

close UC1.AL1 and <120mil

+3.3V_1.8V_PGPPA +1.0V_PRIM VCCSRAM_1P0

@ESPI@ RC212 0_0402_5% KBL-RU42_BGA1356 15 OF 20