Dell LATITUDE 3490 3590 LA-F116P PDF

A B C D E
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! " #$%
1
3 1
& ' ( ) *
PCB R1 PCB R3 ZZZ PCB R1

ZZZ ZZZ
DA8001FO000
DA8001BS000 DAZ21C00101
PCB@ PCB_R3@
+ , - - .- ,/,0 PCB_R1_X32@
PCB 21C LA-F115P REV0 M/B 3 PCB CAL50 LA-F115P LS-F111P GOLD A31 !
+ + 1 2-/ PCB 21C LA-F116P REV0 M/B 3
33+ 3+ &
+ + UC1
KBL R1 KBL R3 + SA0000BVB0L
4 + 4 + 4 i3KBLU_23e@
2 UC1 UC1 + +& + 5 #,% & .- ,/,0 S IC A31 FH8067703037315 QNMU J1 2.3G
2
UC1
SA0000AWC0L SA0000AWC2L + ++ + +& + 5 #,% & , .- ,/,0
SA0000BVB1L
i7KBLR_1.8G_QS@ i7KBLR_R3@ + + + + +& + 5 5& .- ,/,0 i3KBLU_23e_R3@
S IC A31 FJ8067703281816 QNBF Y0 1.8G S IC FJ8067703281816 SR3LC Y0 1.8G A31! + 6 .- ,/,0 S IC FH8067703037315 SR3N6 J1 2.3G A31!
UC1 UC1 + ,,/70 $ .- ,/,0
SA0000A370L SA0000AWB3L 89 + 89 + :7; #% <# /
i5KBLU_2.5G_R1@ i5KBLR_R3@ + #7 = >;0
S IC FJ8067702739739 SR2ZU H0 2.5G A31! S IC FJ8067703282221 SR3LB Y0 1.6G A31! + /
UC1 UC1
+ $// #== /,? $
SA0000AWB1L SA0000B2Y1L + 02-/
i5KBLR_1.6G_QS@ i3KBLU_R3@
6+ //- ?=//-
S IC A31 FJ8067703282221 QNEG Y0 1.6G S IC FJ8067702739765 SR3JY H0 2.7G A31!
+ ,>/$ $ ,0/$
UC1 UC1
38 + @ & 838
SA0000AQZ0L SA0000ADV3L
i7KBLR_1.8G_ES@ KBLU_Pentium_R3@
3@+ 3@8A+ 3@8 + 3@8 + '& 02-/
3
S IC A31 FJ8067703281813 QN5C Y0 1.8G S IC FJ8067702739932 SR348 H0 2.3G A31!

@+ @8A+ @8 + @8 + '& 02-/ 3
UC1 UC1
SA0000A344L SA0000ADL3L
+ ,=2
i7KBLU_2.7G@ KBLU_Celeron_R3@
+ + + + .- ,/,0
S IC FJ8067702739740 SR2ZV H0 2.7G A31! S IC FJ8067702739933 SR349 H0 1.8G A31!
+ .- ,/,0
+ + 02-/
UC1 UC1
@ +& @
SA0000ACL0L SA0000ACL1L
+ 9
i3SKL_2.0G_SMB0@ i3SKL_SMB0_R3@
S IC FJ8066201931106 SR2UW D1 2G A31! S IC FJ8066201931106 SR2UW D1 2G A31!

UC1
+ ,=2
+& + & .- ,/,0
SA0000B2Y0L
i3KBLU_R1@
@ B+ & @ B
+ A9
UC1
4 4
SA0000A374L
i5KBLU_R3@
UC1
Security Classification Compal Secret Data
SA0000AWS0L Issued Date 2016/12/01 Deciphered Date 2017/12/01 Title
i5KNLR_R1@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
! " MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, March 02, 2018 Sheet 1 of 65
A B C D E
A B C D E
Loki/Loki-L Block Diagram

Vinafix.com DDR4
4GB/8GB
DDR4 2400MHz Channel A
GPU SODIMM A
P20
1 1
VRAM(GDDR5)* 4 AMD
2GB/4GB GDDR5 R17M-M2-50 PCIe x 4
(15"/17") DDR4
P49~50
25W 4GB/8GB
DDR4 2400MHz Channel B
P44~48
SODIMM B
P20
USB2.0 x 1
Port 1 (USB3.0 Type-A)
USB3.0 x 1
eDP connector eDP 1.2 Intel CPU P26
P28 Kabylake - U
Kabylake - R USB2.0 x 1
HDMI connector , 1.4 DDI x 4 15W Port 2 (USB3.0 Type-A)
P33 USB3.0 x 1
P26
USB2.0 x 1 Port 3 (USB2.0 Type-A)

VGA # VGA converter DP x 2 # DP re-driver DP x 2 # DP MUX DDI x 4
Connector RTD2166 PS8330 PS8338
P39
USB3.0 x 1 # USB3.0 re-driver USB3.0 x 1

PS8713
DP x 4
USB2.0 x 1 # WWAN
2 2
PCIe x 1
USB3.0 x 1 or DP x 4 Type-C MUX USB3.0 x 1
TI TUSB546
USB Type-C P39
Connector
PD controller Type-C USB2 MUX Card reader
CC , USB2.0 USB2.0 x 1 USB2.0 x 1 USB2.0 x 1 SD 3.0 SD Card slot
Cypress CCG4 TI TS3DS10224 RTS5170
P40 P38 P40 # RTS5176E
RJ45 CC , USB2.0 Transformer CC , USB2.0 LAN 10/100 PCIe x 1 USB2.0 x 1

Connector # LAN 10/100/1000 BT with WLAN
P35 P35 P35
PCIe x 1
P32
SATA x 1
M.2 SSD (NVMe)
PCIe x 4 USB2.0 x 1 Camera
P37
P28
ODD SATA x 1
PCH-LP USB2.0 x 1 Touch screen

P31
P28
2.5" SATA x 1
HDD/SSD
USB2.0 x 1 Finger print
P31
P27
3 3
# FFS SMBus
SPI # dTPM
P31
NPCT650VB2YX
P26
eMMC 256 GB eMMC

*UMA only SPI ROM
P42
16 MB
2CH SPEAKER P8
(2CH 2W/4ohm)
HDA CODEC HDA RTC

RING2/SLEEVE
Realtek ALC3246-CG
HP_R/L
P23
Universal Jack
P24 Precision
I2C
Touchpad
Click Pad P26
P6~19
eSPI PS/2
# ----> Loki-L only

4
SMSC KBC 1416 4
MEC1416-NU
Battery RTC P25
I2C
Charger Daughter board
Keyboard PWM FAN Thermal sensor

# GPIO extender
8b
P30 P30 P30
Issued Date 2016/12/01 Deciphered Date 2017/12/01 Title
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D E
5 4 3 2 1
POWER STATES
Signal SLP SLP SLP ALWAYS SUS RUN 3( (
S3# S4# S5# PLANE PLANE PLANE CLOCKS
State
3( - $0 ( ( - $0
S0 (Full ON) / M0
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HIGH HIGH HIGH ON ON ON ON 3 3( - $0 5 ( 3 99 5
D D
S3 (Suspend to RAM) / M3 LOW HIGH HIGH ON ON OFF OFF

3( $03 ( ( - $03
2-/ ( 2-/
S4 (Suspend to DISK) / M3 LOW LOW HIGH ON OFF OFF OFF
#./$# ( @
S5 (SOFT OFF) / M3 LOW LOW LOW ON OFF OFF OFF ! #$% $/#%/$ 5 ( ! 3 @
G3 OFF OFF OFF OFF OFF OFF OFF

@
:7; ?7$//, @
DS3 LOW HIGH HIGH ON ON OFF OFF
B ,>/$ -$ ,0/$
99 5 ! 9
A
8 %#-0/$ - </$ ?:--=2
( '8 #0 0 /$ 2 - </$ ? :--= 2
B '
B' $ "#0 0 /$ 2 - </$ $ #= D $ - </$ 7 $7 : 0
' 8 & $/ E =0#>/ D $ '
' 8@ = 7/% >$#-; 7? - </$ $# =
C
C ' C
(!'8 &8' & (!' - </$ $# = D $ & 0/$. ,#0 $
( '8 & 2?0/. ( ' - </$ $# = C 3 3 '
( ' 8' ( ' - </$ $# =
( '8 A ( ' - </$ D $ A A $# =?
(B ' @ (B' - </$ $# = D $ @
( '8 8@ 6 ( ' - </$ $# = D $ @
(3'8 & & & (3' - </$ $# = Board ID & Model ID table
3( '8 & & 3( ' - </$ $# =
( '8 & 2?0/. ( ' - </$ $# = C 0/. :== % <, :== :- ' =0#>/ #$% %/=
( ' 2?0/. ( ' - </$ $# = EVT
( (
' 9 2?0/. ' 9 #=<#2? , - </$ $# = C
' B' 0 ' - </$ $# = D $ ?:?-/,% - </$ 3 ( 3(B 3
( '8 98 9 ' 9 - </$ D $ A 9 $# =? C DVT1
( 3(
' 98 A ' 9 - </$ D $ A ?:?-/,% $# =? C
' 2?0/. ' - </$ $# = 33( 3(
'@ ' - </$ $# = D $ @ DVT2
3 ( 3( B
( '@ ( ' - </$ $# = D $ @
' 9 2?0/. ' 9 - </$ $# = C ! 3( 3( B3
' 2?0/. ' - </$ $# =
B ( 3( 3 B
& 8 & - </$
' 8 2?0/. >/,0 - </$ $# = B(B 3(3 Pilot
0/ C ./#,? 0;#0 0; ? - </$ -=#,/ ? ,=2 < 0; - </$ #E# =#"=/5 0;/$< ?/ 0 ?
B (! 3( B
! (B 3(
(3 (B
3 3( (
B ( ( B
( ( B
3 ( (
! ( ( B3
( (3BB
3 ( (
B 3 3( (BB
A A

! "
5 4 3 2 1
5 4 3 2 1
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D D
PJPM02
PJPM01 SIO_SLP_S4 #
RT8207PGQW
(PUM01) +1.2VP +1.2V_DDR SIO_SLP_S3 #
SIO_SLP_S0 # JP1
TPS22961
(UZ2) +1.0V_VCCSTG +1.0VS_VCCIO
0.6V_DDR_VTT_ON PJPM03
+0.6VSP +0.6V_DDR_VTT
0ohm 0603
(RC174) +1.0V_MPHYGT
PJPH01 POK PJPH02 SIO_SLP_S4 #

RT6228AGQUF TPS22967
(PUH01) +1VALW P +1.0V_PRIM (UZ1) +1.0V_VCCST
JP7
EM5209VF DGPU_PW R_EN
(UZ5) +0.95VSDGPU
FUSE 1.5A_24V 0ohm 0603
(F1) +DCBAT_LCD (R13) +TPAN_VDD
0ohm 0805
PJPW01 DGPU_PW ROK PJPH3 (RA1) +5V_PVDD
RT6226AGQUF
(PUW01) +1.35VGPUP +1.35V_MEM_GFX
JP5 +5V_HDD
USB_EN#
SY6288D20AAC
(UU1) USB30_VCCA
JP6 +5VS_ODD
PJP501 PJP502
EN_5V PJP503 USB_EN#
SY8180CRAC SY6288D20AAC
(PU501) +5VALW P +5VALW (UU3) USB30_VCCB FUSE 1.5A_6V
C
(FI1) +5V_HDMI C
SIO_SLP_S3 #
PJP301 EM5209VF FUSE 0.5A_13.2V
(UZ3) +5VS (F3) +5V_KB_BL
SY8180CRAC BAS40C
(PU301) +3VLP (D1) +RTC_CELL
ADAPTER OVP_T RIP_P 1 CHARGER
AP22815AW5-7 5A_Z120_25M_0805_2P AON7409 AON7409 ISL9538HRTZ-T
EN_3V (UT7) +CCG_VBUS (PLS11 , PLS12) +CCG_VBUS_1 (PQS01) +VBUS_DC_SS (PQS02) (PUB01)
+RTC_VCC
POK
RT9069-33GB
(UT4) +3.3V_VDD_PIC
CHARGER
ISL9538HRTZ-T +PW R_SRC
(PUB01) (+19VB)
LCD_VCC_TEST_EN_R
or
PJP302 SIO_SLP_S3 # EDP_VDD_EN
EM5209VF SY6288C20AAC
+3VALW P +3VALW (UZ3) +3VS (U1) +LCDVDD
PCH_PW R_EN
EM5209VF SY6288C20AAC
(UZ7) +3VALW_PCH (UZ6) +3.3V_W WAN
BATTERY
JP9
DGPU_PW R_EN
0ohm 0603 TPS22967DSGR
(RM1) +3V_EMMC (UZ4) +3VGS
JP8
PJP1801 POK PJP1802 DGPU_PW R_EN
RT8061AZQW EM5209VF
(PU1801) +1.8VALWP +1.8V_PRIM (UZ5) +1.8VGS
B B
0ohm 0603
(RM2) +1.8V_EMMC
PJP2501 SIO_SLP_S4 # PJP2502

RT9059GSP
(PU2501) +2.5VP +2.5V_MEM
DRVON
PWM1_2ph_CPU
NCP302045MNTXG NCP302045MNTXG
(PUI01) (PUI02) +VCC_CORE
DRVON
PWM_1a_CPU
NCP302045MNTXG
(PUG01) +VCC_GT
DRVON
PWM_1b_CPU
NCP81253MNTBG
(PUA01) +VCC_SA
DGPU_PW R_EN
ISL62771HRTZ-T
(PUV01) +VGA_CORE
A A

# $
5 4 3 2 1
5 4 3 2 1
Vinafix.com
;. 3(3 ;.
' (% ) * '
!%& ;. 3(3 ;.
R7 8 253
A8 A8
D
R8 8
!! 254 D
A8 A8 &
SMBus Address: 000
253
A8
R9 8 ;.
254
' (% ) * A8 &
W2 8 ;. SMBus Address: 010
+
;. ( ;. 1
A8
+ 4
;. ' (% ) * ( ;. ' A8 @3
W3 8 U7
'@ 8 8
13
V3 8
!! U8
%@ A8
'@ 8 8 6 '@
14
A8
SMBus Address: 0x41 / 0x41
U6 U7
3 8 8 A8 19
3
3 8 8 A8 20 ) * SMBus Address: 0x4e/0x4f
3(3 ;. + 3(3 ;.
' (% )" 3(3 ;. + 3(3 ;.

'
8
8 8 A 8 8 ;/$.#=
C !! 7 C
9
8 8 A 8 8
SMBus Address: 1001100xb (x is R/W bit)
12 11
SMB02_CLK SMB02_DATA ( ;. 3(3 ;.
( ;.
' 3(3 ;.
'+ )
6
! 3 8 8 A8
!!
3 8 8
7
" # #$ 3 8 8 A8 3 8 8
1
( ;. 8 8
2
'+ ) 8 8
( ;. SMBus Address: $2C
78
PS2_CLK0 8 8
79
PS2_DAT0 8 8
( ;.
( ;.
' (% )"
9 ;. 4
SMB01_CLK 8 A@8 8
SMB01_DATA 8 ;. 5
8 A@8 8
SMBus Address: 0x01
B B
;. 3
;. 4 ;#$>/$
B
SMBus Address: 0001001 (R/W#)
( ;.
3(3 ;.
( ;. ' , ) ) -
3(3 ;.
' (% )"
91 17 3 8 8 8 8 29 21
8 68 3 8
SMB03_CLK
3 33 6
SMB03_DATA 89 16 28 22 !
8
@ 68 3 8
3 8 8 8 8
;. 3 8 - 18 A6
8 8&
6 17 A7
;. 4 33
8 8& 8 B7 3
8 , 3
9 B6
A A

%&'"
5 4 3 2 1
5 4 3 2 1
Main Func = CPU
+3VS
UC1A SKL-U
2 1 CPU_DP1_CTRL_CLK E55 C47

RC1
RC2
2
2.2K_0402_5%
1 CPU_DP1_CTRL_DATA
2.2K_0402_5%
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<33>
<33>
<33>
HDMI_DATA2#
HDMI_DATA2
HDMI_DATA1#
F55
E58
F58
DDI1_TXN[0]
DDI1_TXP[0]
DDI1_TXN[1]
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
C46
D46
C45
EDP_TX0_DN
EDP_TX0_DP
EDP_TX1_DN
<28>
<28>
<28>
2 1 CPU_DP2_CTRL_DATA <33> HDMI_DATA1 F53 DDI1_TXP[1] EDP_TXP[1] A45 EDP_TX1_DP <28>
D RC212 2.2K_0402_5% <33> HDMI_DATA0# G53 DDI1_TXN[2] EDP_TXN[2] B45 D
2 1 WIFI_RF_EN <33> HDMI_DATA0 F56 DDI1_TXP[2] EDP_TXP[2] A47
RC3 LOKI@ 10K_0402_5% <33> HDMI_CLK# G56 DDI1_TXN[3] EDP_TXN[3] B47
<33> HDMI_CLK DDI1_TXP[3] EDP_TXP[3]
C50 E45
<39> CPU_DP2_N0 D50 DDI2_TXN[0] DDI EDP EDP_AUXN F45 EDP_AUX_DN <28>
<39> CPU_DP2_P0 C52 DDI2_TXP[0] EDP_AUXP EDP_AUX_DP <28>
<39> CPU_DP2_N1 D52 DDI2_TXN[1] B52
<39> CPU_DP2_P1 A50 DDI2_TXP[1] EDP_DISP_UTIL
<39> CPU_DP2_N2 B50 DDI2_TXN[2] G50
+3VALW <39> CPU_DP2_P2 D51 DDI2_TXP[2] DDI1_AUXN F50
<39> CPU_DP2_N3 C51 DDI2_TXN[3] DDI1_AUXP E48 CPU_DP2_AUXN
<39> CPU_DP2_P3 DDI2_TXP[3] DDI2_AUXN F48 CPU_DP2_AUXP CPU_DP2_AUXN <39>
2 1 WIFI_RF_EN DDI2_AUXP G46 CPU_DP3_AUXN CPU_DP2_AUXP <39>
TP1
RC225 MAD@ 10K_0402_5% DISPLAY SIDEBANDS DDI3_AUXN F46 CPU_DP3_AUXP TP2
CPU_DP1_CTRL_CLK L13 DDI3_AUXP
<33> CPU_DP1_CTRL_CLK CPU_DP1_CTRL_DATA L12 GPP_E18/DDPB_CTRLCLK L9
<33> CPU_DP1_CTRL_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7 CPU_DP2_HPD CPU_DP1_HPD <33>
N7 GPP_E14/DDPC_HPD1 L6 CPU_DP2_HPD <39>
CPU_DP2_CTRL_DATA N8 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 CPU_DP2_HPD 2 1
N11 GPP_E17/EDP_HPD EDP_HPD <28>
RC5 100K_0402_5%
N12 GPP_E22/DDPD_CTRLCLK R12 BKLT_IN_EC BKLT_IN_EC 2 1
GPP_E23/DDPD_CTRLDATA EDP_BKLTEN R11 BKLT_IN_EC <25> RC6 100K_0402_5%
RC4 1 2 24.9_0402_1% EDP_COMP E52 EDP_BKLTCTL U13 L_BKLT_CTRL <28>
+1.0VS_VCCIO EDP_RCOMP EDP_VDDEN EDP_VDD_EN <28>
1 OF 20
SKL-U_BGA1356
. "/ (+-./ 0.
( / 1 2 34 5 6 34 5 6 %& ! 8 ,9# : -/+"% ;5< #,
7 3# 5 ,
C C
SKL_ULT
UC1I
CSI-2
A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
B B38 CSI2_DN3 CSI2_CLKN3 A26 B
CSI2_DP3 CSI2_CLKP3
C31 E13 CSI2_COMP RC7 1 2 100_0402_1%
D31 CSI2_DN4 CSI2_COMP B7 WIFI_RF_EN
C33 CSI2_DP4 GPP_D4/FLASHTRIG WIFI_RF_EN <32>
D33 CSI2_DN5 %
A31 CSI2_DP5 EMMC
B31 CSI2_DN6 AP2

A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1 EMMC_DATA0 <42>
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3 EMMC_DATA1 <42>
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3 EMMC_DATA2 <42>
A29 GPP_F16/EMMC_DATA3 AN1 EMMC_DATA3 <42>
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2 EMMC_DATA4 <42>
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4 EMMC_DATA5 <42>
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1 EMMC_DATA6 <42>
A27 CSI2_DP9 GPP_F20/EMMC_DATA7 EMMC_DATA7 <42>
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3 EMMC_RCLK <42>
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4 EMMC_CLK <42>
CSI2_DP11 GPP_F12/EMMC_CMD EMMC_CMD <42>
AT1 EMMC_RCOMP 1 2
EMMC_RCOMP RC8 200_0402_1%
SKL-U_BGA1356 9 OF 20
A A

& ( ) *+ % , &&
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
5 4 3 2 1
5 4 3 2 1
Main Func = CPU

- 2 5 ;
SKL-U
UC1B SKL-U UC1C
<20> DDR_A_D[0..15] DDR_A_D0

DDR_A_D1
AL71
AL68 DDR0_DQ[0]
Vinafix.com DDR0_CKN[0]
DDR0_CKP[0]
AU53
AT53
AU55
DDR_A_CLK#0
DDR_A_CLK0
DDR_A_CLK#1
DDR_A_CLK#0 <20>
DDR_A_CLK0 <20>
<21> DDR_B_D[0..15] DDR_B_D0
DDR_B_D1
AF65
AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0]
AN45
AN46
DDR_B_CLK#0
DDR_B_CLK#1 DDR_B_CLK#0 <21>
DDR_A_D2 AN68 DDR0_DQ[1] DDR0_CKN[1] AT55 DDR_A_CLK1 DDR_A_CLK#1 <20> DDR_B_D2 AK65 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] AP45 DDR_B_CLK0 DDR_B_CLK#1 <21>
D DDR_A_D3 AN69 DDR0_DQ[2] DDR0_CKP[1] DDR_A_CLK1 <20> DDR_B_D3 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46 DDR_B_CLK1 DDR_B_CLK0 <21> D
DDR_A_D4 AL70 DDR0_DQ[3] BA56 DDR_A_CKE0 DDR_B_D4 AF66 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 <21>
DDR_A_D5 AL69 DDR0_DQ[4] DDR0_CKE[0] BB56 DDR_A_CKE1 DDR_A_CKE0 <20> DDR_B_D5 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 DDR_B_CKE0
DDR_A_D6 AN70 DDR0_DQ[5] DDR0_CKE[1] AW56 DDR_A_CKE2 DDR_A_CKE1 <20> DDR_B_D6 AK67 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] AP55 DDR_B_CKE1 DDR_B_CKE0 <21>
DDR_A_D7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56 DDR_A_CKE3 DDR_B_D7 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55 DDR_B_CKE2 DDR_B_CKE1 <21>
TP3
DDR_A_D8 AR70 DDR0_DQ[7] DDR0_CKE[3] TP4 DDR_B_D8 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53 DDR_B_CKE3 TP5
DDR_A_D9 AR68 DDR0_DQ[8] AU45 DDR_A_CS#0 DDR_B_D9 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3] TP6
DDR_A_D10 AU71 DDR0_DQ[9] DDR0_CS#[0] AU43 DDR_A_CS#1 DDR_A_CS#0 <20> DDR_B_D10 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42 DDR_B_CS#0
DDR_A_D11 AU68 DDR0_DQ[10] DDR0_CS#[1] AT45 DDR_A_ODT0 DDR_A_CS#1 <20> DDR_B_D11 AH68 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] AY42 DDR_B_CS#1 DDR_B_CS#0 <21>
DDR_A_D12 AR71 DDR0_DQ[11] DDR0_ODT[0] AT43 DDR_A_ODT1 DDR_A_ODT0 <20> DDR_B_D12 AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42 DDR_B_ODT0 DDR_B_CS#1 <21>
DDR_A_D13 AR69 DDR0_DQ[12] DDR0_ODT[1] DDR_A_ODT1 <20> DDR_B_D13 AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW42 DDR_B_ODT1 DDR_B_ODT0 <21>
DDR_A_D14 AU70 DDR0_DQ[13] BA51 DDR_A_MA5 DDR_B_D14 AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDR_B_ODT1 <21>
DDR_A_D15 AU69 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 DDR_A_MA9 DDR_A_MA5 <20> DDR_B_D15 AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48 DDR_B_MA5
<20> DDR_A_D[16..31] DDR_A_D16 BB65 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BA52 DDR_A_MA6 DDR_A_MA9 <20> <21> DDR_B_D[16..31] DDR_B_D16 AT66 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50 DDR_B_MA9 DDR_B_MA5 <21>
DDR_A_D17 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDR_A_MA8 DDR_A_MA6 <20> DDR_B_D17 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDR_B_MA6 DDR_B_MA9 <21>
DDR_A_D18 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52 DDR_A_MA7 DDR_A_MA8 <20> DDR_B_D18 AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48 DDR_B_MA8 DDR_B_MA6 <21>
DDR_A_D19 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDR_A_BG0 DDR_A_MA7 <20> DDR_B_D19 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDR_B_MA7 DDR_B_MA8 <21>
DDR_A_D20 BA65 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AW54 DDR_A_MA12 DDR_A_BG0 <20> DDR_B_D20 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 DDR_B_BG0 DDR_B_MA7 <21>
DDR_A_D21 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDR_A_MA11 DDR_A_MA12 <20> DDR_B_D21 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDR_B_MA12 DDR_B_BG0 <21>
DDR_A_D22 BA63 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA55 DDR_A_ACT# DDR_A_MA11 <20> DDR_B_D22 AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 DDR_B_MA11 DDR_B_MA12 <21>
DDR_A_D23 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 DDR_A_BG1 DDR_A_ACT# <20> DDR_B_D23 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 DDR_B_ACT# DDR_B_MA11 <21>
DDR_A_D24 BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_BG1 <20> DDR_B_D24 AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52 DDR_B_BG1 DDR_B_ACT# <21>
DDR_A_D25 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46 DDR_A_MA13 DDR_B_D25 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR_B_BG1 <21>
DDR_A_D26 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDR_A_CAS# DDR_A_MA13 <20> DDR_B_D26 AP60 DDR1_DQ[25]/DDR0_DQ[57] BA43 DDR_B_MA13
DDR_A_D27 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDR_A_WE# DDR_A_CAS# <20> DDR_B_D27 AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 DDR_B_CAS# DDR_B_MA13 <21>
DDR_A_D28 BB61 DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 DDR_A_RAS# DDR_A_WE# <20> DDR_B_D28 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44 DDR_B_WE# DDR_B_CAS# <21>
DDR_A_D29 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 DDR_A_BS0 DDR_A_RAS# <20> DDR_B_D29 AP61 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW44 DDR_B_RAS# DDR_B_WE# <21>
DDR_A_D30 BA59 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 DDR_A_MA2 DDR_A_BS0 <20> DDR_B_D30 AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44 DDR_B_BS0 DDR_B_RAS# <21>
DDR_A_D31 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 DDR_A_BS1 DDR_A_MA2 <20> DDR_B_D31 AU60 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47 DDR_B_MA2 DDR_B_BS0 <21>
<20> DDR_A_D[32..47] DDR_A_D32 AY39 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 DDR_A_MA10 DDR_A_BS1 <20> <21> DDR_B_D[32..47] DDR_B_D32 AU40 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44 DDR_B_BS1 DDR_B_MA2 <21>
DDR_A_D33 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 DDR_A_MA1 DDR_A_MA10 <20> DDR_B_D33 AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46 DDR_B_MA10 DDR_B_BS1 <21>
DDR_A_D34 AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 DDR_A_MA0 DDR_A_MA1 <20> DDR_B_D34 AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 DDR_B_MA1 DDR_B_MA10 <21>
C DDR_A_D35 AW37 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 DDR_A_MA3 DDR_A_MA0 <20> DDR_B_D35 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 DDR_B_MA0 DDR_B_MA1 <21> C
DDR_A_D36 BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] BB52 DDR_A_MA4 DDR_A_MA3 <20> DDR_B_D36 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46 DDR_B_MA3 DDR_B_MA0 <21>
DDR_A_D37 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDR_A_MA4 <20> DDR_B_D37 AP40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] BA47 DDR_B_MA4 DDR_B_MA3 <21>
DDR_A_D38 BA37 DDR0_DQ[37]/DDR1_DQ[5] AM70 DDR_A_DQS#0 DDR_B_D38 AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4] DDR_B_MA4 <21>
DDR_A_D39 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 DDR_A_DQS0 DDR_A_DQS#0 <20> DDR_B_D39 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66 DDR_B_DQS#0
DDR_A_D40 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 DDR_A_DQS#1 DDR_A_DQS0 <20> DDR_B_D40 AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDR_B_DQS0 DDR_B_DQS#0 <21>
DDR_A_D41 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] AT70 DDR_A_DQS1 DDR_A_DQS#1 <20> DDR_B_D41 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 DDR_B_DQS#1 DDR_B_DQS0 <21>
DDR_A_D42 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 DDR_A_DQS#2 DDR_A_DQS1 <20> DDR_B_D42 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 DDR_B_DQS1 DDR_B_DQS#1 <21>
DDR_A_D43 AW33 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR_A_DQS2 DDR_A_DQS#2 <20> DDR_B_D43 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDR_B_DQS#2 DDR_B_DQS1 <21>
DDR_A_D44 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 DDR_A_DQS#3 DDR_A_DQS2 <20> DDR_B_D44 AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDR_B_DQS2 DDR_B_DQS#2 <21>
DDR_A_D45 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR_A_DQS3 DDR_A_DQS#3 <20> DDR_B_D45 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDR_B_DQS#3 DDR_B_DQS2 <21>
DDR_A_D46 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDR_A_DQS#4 DDR_A_DQS3 <20> DDR_B_D46 AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] AR60 DDR_B_DQS3 DDR_B_DQS#3 <21>
DDR_A_D47 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDR_A_DQS4 DDR_A_DQS#4 <20> DDR_B_D47 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDR_B_DQS#4 DDR_B_DQS3 <21>
<20> DDR_A_D[48..63] DDR_A_D48 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDR_A_DQS#5 DDR_A_DQS4 <20> <21> DDR_B_D[48..63] DDR_B_D48 AU27 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] AR38 DDR_B_DQS4 DDR_B_DQS#4 <21>
DDR_A_D49 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDR_A_DQS5 DDR_A_DQS#5 <20> DDR_B_D49 AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDR_B_DQS#5 DDR_B_DQS4 <21>
DDR_A_D50 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDR_A_DQS#6 DDR_A_DQS5 <20> DDR_B_D50 AT25 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 DDR_B_DQS5 DDR_B_DQS#5 <21>
DDR_A_D51 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDR_A_DQS6 DDR_A_DQS#6 <20> DDR_B_D51 AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25 DDR_B_DQS#6 DDR_B_DQS5 <21>
DDR_A_D52 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDR_A_DQS#7 DDR_A_DQS6 <20> DDR_B_D52 AP27 DDR1_DQ[51] DDR1_DQSN[6] AR27 DDR_B_DQS6 DDR_B_DQS#6 <21>
DDR_A_D53 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDR_A_DQS7 DDR_A_DQS#7 <20> DDR_B_D53 AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 DDR_B_DQS#7 DDR_B_DQS6 <21>
DDR_A_D54 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_A_DQS7 <20> DDR_B_D54 AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21 DDR_B_DQS7 DDR_B_DQS#7 <21>
DDR_A_D55 BB29 DDR0_DQ[54]/DDR1_DQ[38] AW50 DDR_A_ALERT# DDR_B_D55 AP25 DDR1_DQ[54] DDR1_DQSP[7] DDR_B_DQS7 <21>
DDR_A_D56 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# DDR_A_PAR DDR_A_ALERT# <20> ) ( 6 )(%" +> ? DDR_B_D56 DDR1_DQ[55] DDR_B_ALERT#
AY27 AT52 AT22 AN43
DDR_A_D57 AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR DDR_A_PAR <20> DDR_B_D57 AU22 DDR1_DQ[56] DDR1_ALERT# AP43 DDR_B_PAR DDR_B_ALERT# <21>
DDR_A_D58 AY25 DDR0_DQ[57]/DDR1_DQ[41] AY67 DDR_B_D58 AU21 DDR1_DQ[57] DDR1_PAR AT13 H_DRAMRST# DDR_B_PAR <21>
DDR_A_D59 DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA +V_DDR_REFA_R DDR_B_D59 DDR1_DQ[58] DRAM_RESET# SM_RCOMP0 H_DRAMRST# <20>
AW25 AY68 AT21 AR18
DDR_A_D60 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR CH - A
DDR0_VREF_DQ BA67 DDR_B_D60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP1
DDR_A_D61 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ +V_DDR_REFB_R DDR_B_D61 DDR1_DQ[60] DDR CH - B DDR_RCOMP[1] SM_RCOMP2
BA27 AP22 AU18
DDR_A_D62 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_VTT_CNTL DDR_B_D62 AP21 DDR1_DQ[61] DDR_RCOMP[2]
DDR_A_D63 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL DDR_B_D63 AN21 DDR1_DQ[62]
DDR0_DQ[63]/DDR1_DQ[47] DDR1_DQ[63] #) ( 6 #)(%" +> ?
SKL-U_BGA1356 2 OF 20 SKL-U_BGA1356 3 OF 20
B B
Buffer with Open Drain Output For VTT power control

. "/ (+-./ - /(%
+1.2V_DDR +3VS
SM_RCOMP0 RC10 1 2 121_0402_1%
0.1U_0402_16V7K 2 1 CC1
1
SM_RCOMP1 RC11 1 2 80.6_0402_1%

UC2 RC9
1 5 100K_0402_5% SM_RCOMP2 RC12 1 2 100_0402_1%
NC VCC
DDR_VTT_CNTL 2
2
A 4
3 Y 0.6V_DDR_VTT_ON <57> ( / 1
GND 1 + 2 3#4=# 5 6 34 5
@
74AUP1G07GW_TSSOP5 CC90 7 3 5
100P_0402_50V8J
2
A A

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5 4 3 2 1
5 4 3 2 1
Main Func = CPU +3VS

-) . -3 -)-.
-) - .3 -)-.# QC1A
2
*" ,9 ,4 =4 $ SKL-U
DMN66D0LDW-7_SOT363-6
UC1E
MEM_SMBCLK 6 1
SPI - FLASH PCH_SMBCLK <20,21,31,34>
SMBUS, SMLINK
SMB -> DDR4, FFS
5
Vinafix.com
PCH_SPI_CLK RC203 2 EMI@ 1 0_0402_5% AV2 QC1B
<22> PCH_SPI_CLK PCH_SPI_D1 AW3 SPI0_CLK R7 MEM_SMBCLK DMN66D0LDW-7_SOT363-6
<22> PCH_SPI_D1 PCH_SPI_D0 AV3 SPI0_MISO GPP_C0/SMBCLK R8 MEM_SMBDATA MEM_SMBDATA 3 4
<22> PCH_SPI_D0 PCH_SPI_D2 SPI0_MOSI GPP_C1/SMBDATA SMB_ALERT# PCH_SMBDATA <20,21,31,34>
AW2 R10
PCH_SPI_D3 AU4 SPI0_IO2 GPP_C2/SMBALERT#
PCH_SPI_CS#0 AU3 SPI0_IO3 R9 SML0_SMBCLK
D AU2 SPI0_CS0# GPP_C3/SML0CLK W2 SML0_SMBDATA D
AU1 SPI0_CS1# GPP_C4/SML0DATA W1 GPP_C5
<22> PCH_SPI_CS#2 SPI0_CS2# GPP_C5/SML0ALERT#
W3 SML1_SMBCLK
SPI - TOUCH GPP_C6/SML1CLK SML1_SMBDATA SML1_SMBCLK <25,30,34,45>
V3 SML1 -> EC, DGPU, THM
GPP_C7/SML1DATA GPP_B23 SML1_SMBDATA <25,30,34,45>
M2 AM7
<22> TPM_SPI_IRQ# GPP_D1/SPI1_CLK GPP_B23/SML1ALERT#/PCHHOT#
M3
<31> FFS_INT1 GPP_D2/SPI1_MISO
+3VS 1 2 J4
<31> HDD_EN_PCH GPP_D3/SPI1_MOSI
RC35 10K_0402_5% % V1
V2 GPP_D21/SPI1_IO2
M1 GPP_D22/SPI1_IO3 RPC2
LPC
<31> HDD_DET# GPP_D0/SPI1_CS# PCH_ESPI_IO0
AY13 1 8
GPP_A1/LAD0/ESPI_IO0 PCH_ESPI_IO1 ESPI_IO0 <25>
BA13 2 7
HDD_EN_PCH C LINK GPP_A2/LAD1/ESPI_IO1 PCH_ESPI_IO2 ESPI_IO1 <25>
+3VS 1 2 BB13 3 6
GPP_A3/LAD2/ESPI_IO2 PCH_ESPI_IO3 ESPI_IO2 <25>
RC209 10K_0402_5% G3 AY12 4 5
CL_CLK GPP_A4/LAD3/ESPI_IO3 ESPI_IO3 <25>
G2 BA12 15_0804_8P4R_5%
G1 CL_DATA GPP_A5/LFRAME#/ESPI_CS# BA11 ESPI_CS# <25>
CL_RST# GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RESET# <25>
+3VS
AW13 AW9 PCH_ESPI_CLK 1 EMI@ 2
GPP_A0/RCIN# GPP_A9/CLKOUT_LPC0/ESPI_CLK AY9 RC15 22_0402_5% ESPI_CLK <25>
AY11 GPP_A10/CLKOUT_LPC1 AW11 PCH_SMBDATA 2 1
<25> ESPI_ALERT# GPP_A6/SERIRQ GPP_A8/CLKRUN# @ 2.2K_0402_5% RC27
1
1 2 CC88 @RF@ PCH_SMBCLK 2 1
+1.8V_PRIM MEM_SMBCLK
RC14 10K_0402_5% SKL-U_BGA1356 5 OF 20 82P_0402_50V8J 1 2 2.2K_0402_5% RC28
CC94 33P_0402_50V8J
2
@RF@ +3VALW_PCH
SML0_SMBCLK 1 2
CC95 33P_0402_50V8J
@RF@ MEM_SMBCLK 1 2
SML1_SMBCLK 1 2 RC29 1K_0402_5%
CC96 33P_0402_50V8J MEM_SMBDATA 1 2
C RC30 1K_0402_5% C
SML1_SMBCLK 1 2
+3VALW_PCH +3.3V_SPI
<14> XDP_SPI_SI
RC40 1 CMC@ 2 1K_0402_1% PCH_SPI_D0 CLOSE TO UC1 RC31 1K_0402_5%
SML1_SMBDATA 1 2
1 @ 2 RC41 1 CMC@ 2 1K_0402_1% PCH_SPI_D2 RC32 1K_0402_5%
<14> XDP_SPI_IO2 SML0_SMBCLK
RC17 0_0603_5% 1 2
RC40/41 place to within 1100 mil of SPIO_MOSI/SPI0_IO2 pin for XDP RC33 1K_0402_5%
SML0_SMBDATA 1 2
+3.3V_SPI RC34 1K_0402_5%
1 2 PCH_SPI_CS#0
RC18 4.7K_0402_5%
+3.3V_SPI MOW 2015WW06
1 2 PCH_SPI_D2 ,0( ( +3VALW_PCH

RC19 1K_0402_5%
1 @ 2 PCH_SPI_D3
RC20 1K_0402_5% @
SMB_ALERT# 1 2
RC37 2.2K_0402_5%
A @A
B 9) * B
+3.3V_SPI
+3VALW_PCH
CC3
,0( (
1 2
UC3 0.1U_0402_25V6 GPP_C5 1 2

PCH_SPI_CS#0 1 8 RC38 4.7K_0402_5%
PCH_SPI_D2 RC176 1 FTPM@ 2 15_0402_5% PCH_SPI_D2_R 3 CS# VCC 6 PCH_SPI_CLK_R RC178 1 FTPM@ 2 15_0402_5% PCH_SPI_CLK
PCH_SPI_D3 RC177 1 FTPM@ 2 15_0402_5% PCH_SPI_D3_R 7 WP# SCLK 5 PCH_SPI_D0_R RC179 1 FTPM@ 2 15_0402_5% PCH_SPI_D0
4 HOLD# SI/SIO0 2 PCH_SPI_D1_R RC180 1 FTPM@ 2 15_0402_5% PCH_SPI_D1 PCH_SPI_CLK_R
GND SO/SIO1 ,0/$D#7/
W25Q128FVSIQ_SO8
RC178,RC179,RC180 place colse to UC1 A @A
9) *
2
33_0402_5%
#4@ < 0 .
@EMI@
RC21
UC3 place colse to UX1 +3VALW_PCH
1
% D2 '#=:/ 0 D $ 99 3 9
33P_0402_50V8J
3 4#? ,
@EMI@
RC176 TPM@ RC178 TPM@
2
GPP_B23
CC2
33_0402_5% 33_0402_5% 1 CMC@ 2
SD028330A80 SD028330A80 RC39 150K_0402_5%
1
RC177 TPM@ RC179 TPM@
33_0402_5% 33_0402_5%
6
SD028330A80 SD028330A80
A @A
A 9) * A
RC180 TPM@
33_0402_5%
SD028330A80

& (-) *+% %&
5 4 3 2 1
5 4 3 2 1
Main Func = CPU

+3VALW_PCH
+3VS UC1F SKL-U

KB_DET# 1 2
LAF116 LPSS ISH
RC45 10K_0402_5%
1
RTC_DET# 1 2
RC181 VRAMX32@ AN8 RC46 10K_0402_5%
ONE_DIMM# AP7 GPP_B15/GSPI0_CS# P2 SIO_EXT_WAKE# 1 2
10K_0402_5%
Vinafix.com VRAM_ID1
NRB_BIT
AP8
AR7
GPP_B16/GSPI0_CLK
GPP_B17/GSPI0_MISO
GPP_D9
GPP_D10
P3
P4
DGPU_HOLD_RST#
IR_CAM_DETECT# DGPU_HOLD_RST# <44>
IR_CAM_DETECT# <28>
RC47 10K_0402_5%
2
GPP_B18/GSPI0_MOSI GPP_D11 P1 RTC_DET#

ONE_DIMM# AM5 GPP_D12 RTC_DET# <22>
D <28> DBC_PANEL_EN AN7 GPP_B19/GSPI1_CS# M4 3.3V_TS_EN 1 2 D
GPP_B20/GSPI1_CLK GPP_D5/ISH_I2C0_SDA
1
AP5 N3 RC213 10K_0402_5%

<28> 3.3V_TS_EN AN5 GPP_B21/GSPI1_MISO GPP_D6/ISH_I2C0_SCL
RC182 VRAMX16@
<26> SD_READ_MODE GPP_B22/GSPI1_MOSI N1 DGPU_HOLD_RST# 1 DIS@ 2
10K_0402_5% GPP_D7/ISH_I2C1_SDA
SATA_ODD_PRSNT# AB1 N2 RC48 10K_0402_5%
<31> SATA_ODD_PRSNT# BLUETOOTH_EN AB2 GPP_C8/UART0_RXD GPP_D8/ISH_I2C1_SCL
LAF115 <32> BLUETOOTH_EN
2
W4 GPP_C9/UART0_TXD AD11
<28> LCD_CBL_DET# BOARD_ID2 AB3 GPP_C10/UART0_RTS# GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12
GPP_C11/UART0_CTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL +3VS
TP86 AD1
TP87 AD2 GPP_C20/UART2_RXD U1 DGPU_PWR_EN
SIO_EXT_WAKE# AD3 GPP_C21/UART2_TXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2 VRAM_ID2 DGPU_PWR_EN <43,63>
'& F 3C3 6 !C3 /0/70 <25> SIO_EXT_WAKE# GPP_C22/UART2_RTS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
1
KB_DET# AD4 U3
<30> KB_DET# GPP_C23/UART2_CTS# GPP_D15/ISH_UART0_RTS# U4 IO_CBL_DET# <26>
A @A 6 3 C 3-7? '& ) !* GPP_D16/ISH_UART0_CTS#/SML0BALERT# VGA_CBL_DET# <34>
RC49 DIS@
9 6 ! C -7? '& ) * U7 AC1 BOARD_ID1 10K_0402_5%
<30> I2C0_SDA_TCH_PAD U6 GPP_C16/I2C0_SDA GPP_C12/UART1_RXD/ISH_UART1_RXD AC2 FFS_INT2
<30> I2C0_SCL_TCH_PAD FFS_INT2 <31>
2
GPP_C17/I2C0_SCL GPP_C13/UART1_TXD/ISH_UART1_TXD AC3 UART1_RTS# TP88 DGPU_PWR_EN
+3VS U8 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4 UART1_CTS# TP79
GPP_C18/I2C1_SDA GPP_C15/UART1_CTS#/ISH_UART1_CTS#
2
U9
GPP_C19/I2C1_SCL AY8 RC50 DIS@
1 LOKI@ 2 BLUETOOTH_EN AH9 GPP_A18/ISH_GP0 BA8 150K_0402_5%
RC42 10K_0402_5% AH10 GPP_F4/I2C2_SDA GPP_A19/ISH_GP1 BB7
GPP_F5/I2C2_SCL GPP_A20/ISH_GP2 BA7
1
1 2 FFS_INT2 AH11 GPP_A21/ISH_GP3 AY7
RC36 10K_0402_5% AH12 GPP_F6/I2C3_SDA GPP_A22/ISH_GP4 AW7
GPP_F7/I2C3_SCL GPP_A23/ISH_GP5 AP13
AF11 GPP_A12/BM_BUSY#/ISH_GP6
AF12 GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL
+3VALW
C +3VS C
+3VS
IR_CAM_DETECT# 1 2
1 MAD@ 2 BLUETOOTH_EN RC200 10K_0402_5%
RC226 10K_0402_5%
LCD_CBL_DET# 1 2
RC205 10K_0402_5%
1
+3VS
@ @ VGA_CBL_DET# 1 2
RC61 RC59 RC207 10K_0402_5%
10K_0402_5% 10K_0402_5%
IO_CBL_DET# 1 2
2
1
1
RC206 10K_0402_5%
KBLU@ KBLU@ VRAM_ID2
RC55 RC57 VRAM_ID1
10K_0402_5% 10K_0402_5%
1
2
2
BOARD_ID2 2G_G5@ 2G_G5@
+3VALW_PCH BOARD_ID1 RC62 RC60
10K_0402_5% 10K_0402_5%
2
1 @ 2 NRB_BIT SKLU@ SKLU@
RC44 4.7K_0402_5% RC56 RC58
10K_0402_5% 10K_0402_5%
2
& &
A @A &
B
9)
9/#
* &
LAF115 VRAM x16*4pcs B
VRAM ID VBIOS_ID2 VBIOS_ID1

RC62 4G_G5@ RC61 New_2G_G5@
(PCBA VRAM Size Config.) (GPP_D14) (GPP_B17)
10K_0402_5% 10K_0402_5%
CPU ID BOARD_ID2 BOARD_ID1
RC55 KBLR@ 2G GDDR5 0 0 SD028100280 SD028100280
(PCBA VRAM Size Config.) (GPP_C11) (GPP_C12)
10K_0402_5%
SD028100280 4G GDDR5 0 1
KBL-U 1 1 RC59 4G_G5@ RC60 New_2G_G5@
New 2G GDDR5 1 0 10K_0402_5% 10K_0402_5%
KBL-R 1 0 SD028100280 SD028100280
RC58 KBLR@ Reserved 1 1
Reserved 0 1 10K_0402_5%
SD028100280
SKL-U 0 0
LAF116 VRAM x32*2pcs

VRAM ID VBIOS_ID2 VBIOS_ID1
RC62 X32_1@ RC62 X32_2@
(PCBA VRAM Size Config.) (GPP_D14) (GPP_B17) 10K_0402_5% 10K_0402_5%
SD028100280 SD028100280
2G GDDR5_1 0 0
2G GDDR5_2 0 1
RC60 X32_1@ RC59 X32_2@
Reserved 1 0 10K_0402_5% 10K_0402_5%
SD028100280 SD028100280
A Reserved 1 1 A

& (*) *+.% , / $0 %1
5 4 3 2 1
5 4 3 2 1
Main Func = CPU

PEG_HTX_C_GRX_P[0..3]
<44> PEG_HTX_C_GRX_P[0..3]
PEG_HTX_C_GRX_N[0..3] UC1H SKL-U
<44> PEG_HTX_C_GRX_N[0..3]
PEG_GTX_C_HRX_P[0..3]
<44> PEG_GTX_C_HRX_P[0..3]
<44> PEG_GTX_C_HRX_N[0..3]
PEG_GTX_C_HRX_N[0..3] Vinafix.com PCIE/USB3/SATA
SSIC / USB3
USB3_1_RXN
H8
G8 USB3_CRX_DTX_N1 <26>
PEG_GTX_C_HRX_P0 H13 USB3_1_RXP C13 USB3_CRX_DTX_P1 <26>
D PEG_GTX_C_HRX_N0 G13 PCIE1_RXN/USB3_5_RXN USB3_1_TXN D13 USB3_CTX_DRX_N1 <26> &&&A #6 ! , B !C D
PEG_HTX_C_GRX_P0 B17 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3_CTX_DRX_P1 <26>
PEG_HTX_C_GRX_N0 A17 PCIE1_TXN/USB3_5_TXN J6
PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN H6 USB3_CRX_DTX_N2 <34>
PEG_GTX_C_HRX_P1 G11 USB3_2_RXP/SSIC_1_RXP B13 USB3_CRX_DTX_P2 <34>
PEG_GTX_C_HRX_N1 F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13 USB3_CTX_DRX_N2 <34> &&&A (/ B-. !C
PEG_HTX_C_GRX_P1 D16 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP USB3_CTX_DRX_P2 <34>
PEG_HTX_C_GRX_N1 C16 PCIE2_TXN/USB3_6_TXN J10
PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN H10 USB3_CRX_DTX_N3 <26>
PEG_GTX_C_HRX_P2 H16 USB3_3_RXP/SSIC_2_RXP B15 USB3_CRX_DTX_P3 <26>
&&&A PEG_GTX_C_HRX_N2 G16 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN A15 USB3_CTX_DRX_N3 <26> &&&A 46 ! , B !C
PEG_HTX_C_GRX_P2 D17 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP USB3_CTX_DRX_P3 <26>
PEG_HTX_C_GRX_N2 C17 PCIE3_TXN E10
PCIE3_TXP USB3_4_RXN F10 USB3_CRX_DTX_N4 <39>
PEG_GTX_C_HRX_P3 G15 USB3_4_RXP C15 USB3_CRX_DTX_P4 <39>
PEG_GTX_C_HRX_N3 F15 PCIE4_RXN USB3_4_TXN D15 USB3_CTX_DRX_N4 <39> &&&A +D "
PEG_HTX_C_GRX_P3 B19 PCIE4_RXP USB3_4_TXP USB3_CTX_DRX_P4 <39>
PEG_HTX_C_GRX_N3 A19 PCIE4_TXN AB9
PCIE4_TXP USB2N_1 USB_PN1 <26>
AB10
F16 USB2P_1 USB_PP1 <26> &&&&&A #6 !4, B !C
<35> PCIE_CRX_LANTX_N5 E16 PCIE5_RXN AD6
<35> PCIE_CRX_LANTX_P5 PCIE5_RXP USB2N_2 USB_PN2 <26>
C19 AD7
%. &&&A <35> PCIE_CTX_LANRX_N5 D19 PCIE5_TXN USB2P_2 USB_PP2 <26> &&&&&A 6 !4, B-. !C
<35> PCIE_CTX_LANRX_P5 PCIE5_TXP AH3
USB2N_3 USB_PN3 <26>
G18 AJ3
<32> PCIE_CRX_WLANTX_N6 F18 PCIE6_RXN USB2P_3 USB_PP3 <26> &&&&&A 46 !4, B !C
<32> PCIE_CRX_WLANTX_P6 D20 PCIE6_RXP AD9
%(/ &&&A <32> PCIE_CTX_WLANRX_N6 C20 PCIE6_TXN USB2N_4 AD10
USB_PN4 <40>
<32> PCIE_CTX_WLANRX_P6 PCIE6_TXP USB2P_4 USB_PP4 <40> &&&&&A +D "
F20 AJ1
<31> SATA3_CRX_HDDTX_N0 PCIE7_RXN/SATA0_RXN USB2N_5 USB_PN5 <28>
E20 AJ2
(+( * &&&A <31> SATA3_CRX_HDDTX_P0
B21 PCIE7_RXP/SATA0_RXP
USB2
USB2P_5 USB_PP5 <28> &&&&&A
C <31> SATA3_CTX_HDDRX_N0 A21 PCIE7_TXN/SATA0_TXN AF6 C
<31> SATA3_CTX_HDDRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 USB_PN6 <26>
AF7
<31> SATA_CRX_ODDTX_N1 G21 USB2P_6 USB_PP6 <26> &&&&&A 2 2 B-. !C
F21 PCIE8_RXN/SATA1A_RXN AH1
(+( . &&&A <31> SATA_CRX_ODDTX_P1
D21 PCIE8_RXP/SATA1A_RXP USB2N_7 AH2
USB_PN7 <32>
<31> SATA_CTX_ODDRX_N1
<31> SATA_CTX_ODDRX_P1 C21 PCIE8_TXN/SATA1A_TXN USB2P_7 USB_PP7 <32> &&&&&A !+
PCIE8_TXP/SATA1A_TXP AF8
USB2N_8 USB_PN8 <28>
E22 AF9
<37> PCIE_CRX_NVMETX_N9
<37> PCIE_CRX_NVMETX_P9 E23 PCIE9_RXN USB2P_8 USB_PP8 <28> &&&&&A + 8
B23 PCIE9_RXP AG1
<37> PCIE_CTX_NVMERX_N9 PCIE9_TXN USB2N_9 USB_PN9 <27>
A23 AG2
<37> PCIE_CTX_NVMERX_P9 PCIE9_TXP USB2P_9 USB_PP9 <27> &&&&&A 0
-" &&&A <37> PCIE_CRX_NVMETX_N10 F25 AH7
USB_PN10 <34>
E25 PCIE10_RXN USB2N_10 AH8
<37> PCIE_CRX_NVMETX_P10
<37> PCIE_CTX_NVMERX_N10 D23 PCIE10_RXP USB2P_10 USB_PP10 <34> &&&&&A (/ B-. !C
C23 PCIE10_TXN AB6 USBCOMP RC66 1 2 113_0402_1%
<37> PCIE_CTX_NVMERX_P10 PCIE10_TXP USB2_COMP AG3 USB2_ID RC67 1 2 1K_0402_5% . "/ (+-./ 0. ! .
PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE RC68 1 2 1K_0402_5%
RC65 1 2 100_0402_1% PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE ( / 1
PCIE_RCOMPP A9 USB_OC0# 7 3# 5
D56 GPP_E9/USB2_OC0# C9 USB_OC1# USB_OC0# <26> +3VALW_PCH
<14> XDP_PRDY# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9 USB_OC2# USB_OC1# <26>
<14> XDP_PREQ# BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC3# USB_OC2# <40>
Reserve
GPP_A7/PIRQA# GPP_E12/USB2_OC3# RPC1
E28 J1 USB_OC3# 4 5
<37> PCIE_CRX_NVMETX_N11 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 HDD_DEVSLP <31> USB_OC0#
<37> PCIE_CRX_NVMETX_P11 E27 J2 3 6
D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3 USB_OC1# 2 7
<37> PCIE_CTX_NVMERX_N11 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 SSD_DEVSLP <37> USB_OC2#
C24 1 8
-" &&&A <37> PCIE_CTX_NVMERX_P11
<37> PCIE_CRX_NVMETX_N12 E30 PCIE11_TXP/SATA1B_TXP H2
F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3 10K_8P4R_5%
<37> PCIE_CRX_NVMETX_P12 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1
<37> PCIE_CTX_NVMERX_N12 A25 G4
B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 M2_SSD_PEDET <37>
B
<37> PCIE_CTX_NVMERX_P12 PCIE12_TXP/SATA2_TXP SATA_LED# B
H1 +3VS
GPP_E8/SATALED# SATA_LED# <29,37>
SKL-U_BGA1356 8 OF 20 SATA_LED# 1 2
RC69 10K_0402_5%
@ /E 7/ ,0$ =
8 G $0
8 G 99
8 3G $0 ) 2-/ *
8 G
A A

& ( ) *+ /% % 0
5 4 3 2 1
5 4 3 2 1
Main Func = CPU XTAL24_IN_R

CC6
U22@
RC23 1 U22@ 2 33_0402_5% 1 2
U22@ 15P_0201_25V8J
2
1M_0402_1%
3
4
RC80
UC1J SKL_ULT
YC1 U22@
CLOCK SIGNALS 24MHZ_12PF_X3G024000DC1H
1
2
D42 SUSCLK 1 2
Vinafix.com
<44> CLK_PEG_VGA C42 CLKOUT_PCIE_N0 XTAL24_IN CC7
RC110 1K_0402_5% U22@
<44> CLK_PEG_VGA# AR10 CLKOUT_PCIE_P0 XTAL24_OUT 1 U22@ 2 XTAL24_OUT_R 1 2
&&&A <45> CLK_PCIE_PEG_REQ# 1 2 10K_0402_5% GPP_B5/SRCCLKREQ0#
+3VS RC71 RC24 33_0402_5%
B42 15P_0201_25V8J
D <32> CLK_PCIE_WLAN_N1 A42 CLKOUT_PCIE_N1 F43 CLK_ITPXDP_N D
TP8
<32> CLK_PCIE_WLAN_P1 AT7 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N E43 CLK_ITPXDP_P
%(/&&&A TP9
<32> CLK_PCIE_WLAN_REQ# 1 2 10K_0402_5% GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
+3VS RC72
D41 BA17 SUSCLK RC74 2 @ 1 0_0402_5%
<35> CLK_PCIE_LAN_N2 C41 CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK_WLAN <32>
<35> CLK_PCIE_LAN_P2 AT8 CLKOUT_PCIE_P2 E37 XTAL24_IN
%(/&&&A RC75 2 @ 1 0_0402_5%
<35> CLK_PCIE_LAN_REQ# 1 2 10K_0402_5% GPP_B7/SRCCLKREQ2# XTAL24_IN E35 XTAL24_OUT SUSCLK_EC <25>
+3VS RC73
D40 XTAL24_OUT
C40 CLKOUT_PCIE_N3 E42 XCLK_BIASREF 1 2
CLKOUT_PCIE_P3 XCLK_BIASREF +1.0V_CLK5
AT10 RC76 2.71K_0402_1%
GPP_B8/SRCCLKREQ3# AM18 PCH_RTCX1
B40 RTCX1 AM20 PCH_RTCX2
<37> CLK_PCIE_NVME_N4 A40 CLKOUT_PCIE_N4 RTCX2
<37> CLK_PCIE_NVME_P4 AU8 CLKOUT_PCIE_P4 AN18 1 2 20K_0402_5%
&&&A SRTCRST# RC77
<37> CLK_PCIE_NVME_REQ# GPP_B9/SRCCLKREQ4# SRTCRST# +RTC_CELL_PCH
RC188 1 2 10K_0402_5% AM16
+3VS RTCRST#
E40 CC4 1 2 1U_0402_6.3V6K CC8
E38 CLKOUT_PCIE_N5 PCH_RTCX1 1 2
AU7 CLKOUT_PCIE_P5 PCH_RTCX2
GPP_B10/SRCCLKREQ5# PCH_RTCRST# RC78 1 2 20K_0402_5% 6.8P_0402_50V8C
1
CC5 1 2 1U_0402_6.3V6K YC2
RC82 32.768KHZ_9PF_X1A000141000200
A8 & G SKL-U_BGA1356 10 OF 20 10M_0402_5% 20ppm / 9pF
ESR <50kohm (MAX)
2
UC4 1 2
1
RC108 1 @ 2 0_0402_5% 1 2 CC9
<22,25> RTCRST_ON 1 2
SA741080400
1
+3VS
SHORT PADS~D
2
MAD@ RC164 6.8P_0402_50V8C
G
10K_0402_5% JCMOS1 JP@
5
S IC 74AHC1G08GW SOT353 AND GEN8@ 4 .:?0 0# / 7#$/ ?; $0 1 0 :7; $ ? , =#2 :0 -=#7/./,0

PCH_PLTRST# 1 3 1
P
<42> PCH_PLTRST#
2
C IN1 4 C
D
2 O PLTRST# <22,25,32,34,35,37,44> E . #
IN2
G
UC4 @
SN74AHC1G08DCKR_SC70-5 RC109
UC4
QC2 ( ; .
:/ 2
3
100K_0402_5% SA00000OH00 2N7002K_SOT23-3

GEN8@
LOKI@ +3VALW
2
S IC MC74VHC1G08DFT2G SC70 SIO_SLP_LAN#

5P AND
1 @ 2 +RTC_CELL Buffer with Open Drain Output For VTT power control
RC88 10K_0402_5%
+3VALW
2 1 H_CPUPWRGD +3.3V_ALW_DSW INTRUDER# 1 2 CC12
CC15 100P_0402_50V8J RC91 1M_0402_5% DZ4 0.1U_0402_16V7K 2 1
1 2
@ESD@ PCH_BATLOW# 1 +3VALW
2 UC6
+3VS RC89 8.2K_0402_5% RB751S40T1G_SOD523-2 1 5
AC_PRESENT 1 2 NC VCC
Close to CPU side 1 2 SYS_RESET# VRALERT# 1 2 SIO_SLP_S3# 1 RC103 2 2
RC90 10K_0402_5%
RC86 10K_0402_5% LANWAKE# 1 2 RC92 10K_0402_5% 10K_0402_1% A 4 ALL_SYS_PWRGD
Y
1
RC214 10K_0402_5% CC14 3 1
2 MAD@1 PCH_DPWROK +3.3V_ALW_DSW GND
RC87 100K_0402_5% 74AUP1G07GW_TSSOP5 C35
2
2 @ 1 AC_PRESENT SIO_PWRBTN# 2 @ 1 1U_0402_6.3V6K @ 100P_0402_50V8J
RC211 100K_0402_5% RC93 100K_0402_5% 2
UC1K SKL-U
KBL R check list SYSTEM POWER MANAGEMENT
AT11 SIO_SLP_S0# Buffer with Open Drain Output For VTT power control
GPP_B12/SLP_S0# AP15 SIO_SLP_S3# SIO_SLP_S0# <17,22,25>
PCH_PLTRST# AN10 GPD4/SLP_S3# BA16 SIO_SLP_S4# SIO_SLP_S3# <17,36> +3VALW +1.0V_VCCST
<14> PCH_RSMRST#_Q SYS_RESET# B5 GPP_B13/PLTRST# GPD5/SLP_S4# AY16 SIO_SLP_S5# SIO_SLP_S4# <17,57,59>
TPS1
B RC94 1 2 10K_0402_5% PCH_RSMRST#_Q AY17 SYS_RESET# GPD10/SLP_S5# TPS5 0.1U_0402_16V7K 2 1 CC13 B
RSMRST#
2
AN15 SIO_SLP_SUS#
H_CPUPWRGD_R RC95 1 2 1K_0402_5% H_CPUPWRGD A68 SLP_SUS# AW15 SIO_SLP_LAN# SIO_SLP_SUS# <25,58,59>
TP7 @ TP10 UC7 RC104
H_VCCST_PWRGD RC96 1 2 60.4_0402_1% VCCST_PWRGD B65 PROCPWRGD SLP_LAN# BB17 SIO_SLP_WLAN# TP11 1 5
VCCST_PWRGD GPD9/SLP_WLAN# NC VCC 1K_0402_5%
AN16 SIO_SLP_A# TPS6
B6 GPD6/SLP_A# ALL_SYS_PWRGD 2
<25> SYS_PWROK
1
BA20 SYS_PWROK BA15 SIO_PWRBTN# A 4 H_VCCST_PWRGD
PCH_RSMRST#_Q <25> RESET_OUT# PCH_DPWROK BB20 PCH_PWROK GPD3/PWRBTN# AC_PRESENT SIO_PWRBTN# <25> Y 1
1 @ 2 AY15 2 1 3
DSW_PWROK GPD1/ACPRESENT AU13 PCH_BATLOW# HW_ACAV_IN <25,53,54,55> GND
RC97 0_0402_5% RB751S40T1G_SOD523-2 DZ1 C36
TPS10 AR13 GPD0/BATLOW# 74AUP1G07GW_TSSOP5 @
GPP_A13/SUSWARN#/SUSPWRDNACK MAD@ 100P_0402_50V8J
TPS11 AP11 2
GPP_A15/SUSACK# AU11 PME# TP12
RC99 1 @ 2 0_0402_5% PCH_PCIE_WAKE# BB15 GPP_A11/PME# AP16 INTRUDER#
<25,32,35,37> PCIE_WAKE# AM15 WAKE# INTRUDER#
<25> LANWAKE# AW17 GPD2/LAN_WAKE# AM10 EXT_PWR_GATE# TP13
AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 VRALERT# +3VS
GPD7/RSVD GPP_B2/VRALERT#
1
RC105
10K_0402_5%
SIO_SLP_S0# TPS2
2
UC5 SIO_SLP_S3# TPS3 1 @ 2 ALL_SYS_PWRGD
SIO_SLP_S4# <57> 1.2V_VTT_PWRGD ALL_SYS_PWRGD <25>
TPS4 RC106 0_0402_5%
SA00000OH00
1 @ 2
POK & & 7 $7: 0 +3VALW

@ CC11
1 2
LOKI@ RC107 0_0402_5%
IMVP_VR_ON <60>
S IC MC74VHC1G08DFT2G SC70 5P AND

1
1U_0402_6.3V6K
1M_0402_5%
0.1U_0402_10V7K UC5
1
A A
5
CC10
RC102
SA741080400
1
P
<25> PCH_RSMRST#
2
IN1 4 PCH_RSMRST#_Q MAD@

2
POK 2 O
<25,38,53,56,58,59> POK IN2
G
S IC 74AHC1G08GW SOT353 AND

UC5 @
3
SN74AHC1G08DCKR_SC70-5
& (2) *+ 3 & $0
5 4 3 2 1
5 4 3 2 1
Main Func = CPU
+1.0V_VCCST
1 @ 2 H_CATERR#
RC111 49.9_0402_1% UC1D SKL-U
RC112
1 2 H_THERMTRIP#
1K_0402_5% Vinafix.com <25> PECI_EC
H_CATERR# D63
A54 CATERR#
+1.0V_VCCSTG H_PROCHOT# 1 2 H_PROCHOT#_R C65 PECI
<25,53,55,60> H_PROCHOT# PROCHOT# JTA G
D RC117 499_0402_1% H_THERMTRIP# C63 D
1 2 H_PROCHOT# TP14 A65 THERMTRIP# B61 CPU_XDP_TCK0
SKTOCC# PROC_TCK D60 SOC_XDP_TDI CPU_XDP_TCK0 <14>
RC113 1K_0402_5% CPU MISC
XDP_OBS0_R C55 PROC_TDI A61 SOC_XDP_TDO SOC_XDP_TDI <14>
XDP_OBS1_R D55 BPM#[0] PROC_TDO C60 SOC_XDP_TMS SOC_XDP_TDO <14>
TP15
+3VS XDP_OBS2_R B54 BPM#[1] PROC_TMS B59 SOC_XDP_TRST# SOC_XDP_TMS <14>
TP16
XDP_OBS3_R C56 BPM#[2] PROC_TRST# SOC_XDP_TRST# <14>
TP17
1 2 TOUCH_PAD_INTR# DZ3 TP18 BPM#[3] B56
A6 PCH_JTAG_TCK D59 SOC_XDP_TDI PCH_JTAG_TCK1 <14>
RC114 10K_0402_5% RB751S40T1G_SOD523-2
1 @ 2 TOUCH_SCREEN_PD# 1 2 A7 GPP_E3/CPU_GP0 PCH_JTAG_TDI A56 SOC_XDP_TDO
<25,30> TP_WAKE_KBC# TOUCH_PAD_INTR# BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDO C59 SOC_XDP_TMS
RC115 10K_0402_5%
1 2 DGPU_PWROK TOUCH_SCREEN_PD# 1 @ 2 TOUCH_PANEL_PD# AY5 GPP_B3/CPU_GP2 PCH_JTAG_TMS C61 SOC_XDP_TRST#
<28> TOUCH_SCREEN_PD# GPP_B4/CPU_GP3 PCH_TRST# A59 CPU_XDP_TCK0
RC116 10K_0402_5% RC118 0_0402_5%
CPU_POPIRCOMP AT16 JTAGX
PCH_POPIRCOMP AU16 PROC_POPIRCOMP
EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
EOPIO_RCOMP H65 OPCE_RCOMP +1.8V_PRIM
OPC_RCOMP
1
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
RC119
RC120
RC121
RC122
1
@ DIS@
2
RC51 RC53
10K_0402_5% 10K_0402_5%
2
PROJECT_ID1
ME_FWP 1 LOKI@ 2 ME_FWP_PCH
( / 1 PROJECT_ID0
<25> ME_FWP
RC223 0_0402_5% 2 3 5 6 ? 2F 2 -.3#4 5
1
@ UMA@
+3VALW_PCH RC52 RC54
C 10K_0402_5% 10K_0402_5% C
2
6
4
@
RC227
GND6
GND4
1 ME_FWP
1 1K_0402_5%
1
2 ME_FWP_PCH
2
3
3
GND7
GND5
MSS3N-Q-T-R_3P
7
5
SW3
@ +3VS
UC1G SKL-U
WWAN_CBL_DET# 1 2
AUDIO RC208 10K_0402_5%
RC123 1 2 33_0402_5% HDA_SYNC BA22

<23> HDA_CODEC_SYNC 1 EMI@ 2 HDA_BIT_CLK AY22 HDA_SYNC/I2S0_SFRM
RC124 33_0402_5%
<23> HDA_CODEC_BITCLK 1 2 HDA_SDOUT BB22 HDA_BLK/I2S0_SCLK
8 9 RC125 33_0402_5% SDIO/SDXC
<23> HDA_CODEC_SDOUT ME_FWP_PCH 1 2 BA21 HDA_SDO/I2S0_TXD
RC126 1K_0402_5%
<23> HDA_SDIN0 AY21 HDA_SDI0/I2S0_RXD AB11
9H I = 7 5 7#,J0 :-%#0 / HDA_CODEC_RST# RC127 1 @ 2 33_0402_5% HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13 WWAN_CBL_DET# <34>
A @A H I :,= 7 5 7#, :-%#0 / TP74 J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11
B RF@ I2S1_TXD GPP_G4/SD_DATA3 W10 B
HDA_BIT_CLK HDA_SDOUT 1 2 PROJECT_ID1 AK7 GPP_G5/SD_CD# W8
PROJECT_ID0 AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7 KB_LED_BL_DET <30>
1 CC97 2.2P_0402_50V8C
MAD@RF@ RF@ AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
CC91 HDA_SDIN0 1 2 AK10 GPP_F2/I2S2_TXD BA9
47P_0402_50V8J CC98 2.2P_0402_50V8C GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
2 RF@ GPP_A16/SD_1P8_SEL
HDA_RST# 1 2 H5 AB7 SD_RCOMP RC130 1 2 200_0402_1%
CC99 2.2P_0402_50V8C D7 GPP_D19/DMIC_CLK0 SD_RCOMP
GPP_D20/DMIC_DATA0
TPM_ID D8 AF13
CLOSE TO UC1 <63,64> DGPU_PWROK
DGPU_PWROK C8 GPP_D17/DMIC_CLK1 GPP_F23
GPP_D18/DMIC_DATA1
AW5
<23> SPKR GPP_B14/SPKR
+3VALW SKL-U_BGA1356 7 OF 20
1
+3VALW_PCH +3VALW_PCH TPM@

RC63
10K_0402_5%
1 @ 2 SPKR 1 @ 2 HDA_SDOUT
2
RC128 8.2K_0402_5% RC129 4.7K_0402_5% TPM_ID

1
9 & =#?; /?7$ -0 $ /7:$ 02 E/$$ %/ FTPM@

A RC64 A
A @A A @A 10K_0402_5%
9) * 9) *
2

& (4) *+& % 50 . 1 % 6
5 4 3 2 1
5 4 3 2 1
Main Func = CPU
Vinafix.com
D D
1 @ 2 CFG0 UC1S SKL-U

RC131 10K_0402_1% UC1T SKL-U
RESERVED SIGNALS-1
SPARE
<14> CFG0 CFG0 E68 BB68 TP21
1 @ 2 CFG1 CFG1 B67 CFG[0] RSVD_TP_BB68 BB69 TP22 AW69 F6
<14> CFG1 CFG[1] RSVD_TP_BB69 RSVD_AW69 RSVD_F6 KBLR_XTAL_IN
RC132 10K_0402_1% <14> CFG2 D65 AW68 E3
1 @ 2 CFG3 CFG3 D67 CFG[2] AK13 TP23 +1.8V_PRIM AU56 RSVD_AW68 RSVD_E3 C11
0#== $/?/0 ?/K:/,7/ RC133 10K_0402_1%
<14> CFG3
CFG4 E70 CFG[3] RSVD_TP_AK13 AK12 TP24 AW48 RSVD_AU56 RSVD_C11 B11
<14> CFG4 CFG[4] RSVD_TP_AK12 KBLR_XTAL_OUT C7 RSVD_AW48 RSVD_B11
C68 A11
A @A) * ?0#==) $.#= -/$#0 ,* <14> CFG5
D68 CFG[5] BB2 RC137 1 @ 2 0_0402_5% U12 RSVD_C7 RSVD_A11 D12
9 ?0#== <14> CFG6 CFG[6] RSVD_BB2 RSVD_U12 RSVD_D12
<14> CFG7 C67 BA3 U11 C12
F71 CFG[7] RSVD_BA3 H11 RSVD_U11 RSVD_C12 F52
<14> CFG8 CFG[8] RSVD_H11 RSVD_F52
<14> CFG9 G69
F70 CFG[9] AU5 TP25
<14> CFG10 CFG[10] TP5
<14> CFG11 G68 AT5 TP26
H70 CFG[11] TP6 SKL-U_BGA1356 20 OF 20
<14> CFG12 CFG[12]
<14> CFG13 G71
H69 CFG[13] D5
<14> CFG14 CFG[14] RSVD_D5
<14> CFG15 G70 D4
CFG[15] RSVD_D4 B2
E63 RSVD_B2 C2
<14> CFG16 CFG[16] RSVD_C2
<14> CFG17 F63
1 2 CFG4 CFG[17] B3
RC136 10K_0402_1% E66 RSVD_B3 A3
<14> CFG18 CFG[18] RSVD_A3 CC17
<14> CFG19 F66 U42@
C CFG[19] AW1 RC25 1 U42@ 2 33_0402_5% KBLR_XTAL_IN_R 1 2 C
2 1 CFG_RCOMP E60 RSVD_AW1
RC134 49.9_0402_1% CFG_RCOMP E1 U42@
RSVD_E1 12P_0201_25V8J
2
1M_0402_1%
<14> XDP_ITP_PMODE E8 E2
ITP_PMODE RSVD_E2
3
4
RC22
/ /,#"=/ AY2 BA4 YC3 U42@
AY1 RSVD_AY2 RSVD_BA4 BB4 24MHZ_12PF_X3G024000DC1H
A @A ?#"=/% RSVD_AY1 RSVD_BB4
9) * ,#"=/%
1
2
D1 A4
D3 RSVD_D1 RSVD_A4 C4 KBLR_XTAL_IN CC18
U42@
RSVD_D3 RSVD_C4 KBLR_XTAL_OUT 1 U42@ 2 KBLR_XTAL_OUT_R 1 2
K46 BB5 TP27 RC26 33_0402_5%
K45 RSVD_K46 TP4
RSVD_K45 A69 12P_0201_25V8J
AL25 RSVD_A69 B69
AL27 RSVD_AL25 RSVD_B69
RSVD_AL27 AY3 1 @ 2
C71 RSVD_AY3 RC201 0_0402_5%
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70
F60 RSVD_C70
RSVD_F60 C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54
BA70 AY4 TP28
TP19 BA68 RSVD_TP_BA70 TP1 BB3 TP29
TP20 RSVD_TP_BA68 TP2
J71 AY71 1 @ 2
J68 RSVD_J71 VSS_AY71 AR56 RC202 0_0402_5%
RSVD_J68 ZVM#
F65 AW71 TP30
G65 VSS_F65 RSVD_TP_AW71 AW70 TP31
B VSS_G65 RSVD_TP_AW70 B
F61 AP56
E61 RSVD_F61 MSM# C64 1 @ 2
RSVD_E61 PROC_SELECT# +1.0V_VCCST
RC138 100K_0402_5%
0 5 @ .
8? ? # GB # @C ? G
& 8? ? # GB # @C ? G; G
A A

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5 4 3 2 1
5 4 3 2 1
Main Func = CPU
Connector Less Routing Topology PRIMARY CMC CONN

Vinafix.com
+1.0V_PRIM +1.0V_XDP
D +3.3V_SPI D
CMC@
TPC1 RC149 1 2 0_0603_5%
1 CMC@ 2 XDP_SPI_SI <12> SOC_XDP_TDO
TPC2
<12> CPU_XDP_TCK0
DCI Link RC139 1K_0402_5% TPC3
<12> PCH_JTAG_TCK1
RC142 need POP TPC4
<12> SOC_XDP_TMS
RC146 need POP +1.0V_VCCSTG
RC140 2 CMC@ 1 51_0402_5% SOC_XDP_TMS

TPC5 TPC10
SOC_XDP_TDI <12> SOC_XDP_TDI <13> CFG0
RC141 2 CMC@ 1 51_0402_5% TPC6 TPC11
<12> SOC_XDP_TRST# <13> CFG1
Place to CPU side SOC_XDP_TDO <13> XDP_ITP_PMODE
TPC7
<13> CFG2
TPC12
RC142 2 CMC@ 1 51_0402_5% TPC13
<13> CFG3
TPC14
<13> CFG4
TPC15
<13> CFG5
TPC16
<13> CFG6
TPC17
<13> CFG7
TPC18
+1.0V_XDP <13> CFG17
TPC8 TPC19
<8> XDP_SPI_SI <13> CFG16
TPC9 TPC30
<8> XDP_SPI_IO2 XDP_PREQ# <10>
TPC20 TPC31 XDP_PRDY# <10>
1 CMC@ 2 1K_0402_5% XDP_ITP_PMODE 1 CMC@ 2 XDP_PRSENT_CPU <13> CFG8
RC143 CFG3 TPC21
<13> CFG9 XDP_HOOK0
RC175 0_0402_5% TPC22 TPC32
<13> CFG10
TPC23
<13> CFG11
TPC24
XDP_PRSENT_CPU <13> CFG12
RC144 2 @ 1 0_0402_5% TPC25
PCH_RSMRST#_Q 1 CMC@ 2 XDP_HOOK0 <13> CFG13
TPC26
XDP_SPI_IO2 <11> PCH_RSMRST#_Q <13> CFG14 XDP_PRSENT_CPU
RC145 2 @ 1 0_0402_5% RC148 1K_0402_5% TPC27 TPC33
<13> CFG15
C TPC28 C
2 CMC@ 1 51_0402_1% CPU_XDP_TCK0 <13> CFG19
RC146 TPC29
<13> CFG18
Place to CPU side PCH_JTAG_TCK1
RC147 2 @ 1 51_0402_5%
B B
A A

& (9) *+:
5 4 3 2 1
5 4 3 2 1
Main Func = CPU

B 5 ; 2 C1 G <
! B! G 2 C1 2 ; 2 68 2 G
5 5 2 1
G 2 A 4 A @ A !8 G A 8
' ) . "1 , =#, +VCC_CORE +VCC_CORE
' ) . "B 44C1 4(B (HC

UC1L Vinafix.com SKL-U
CPU POWER 1 OF 4
D ' ) . "B 4C1 $ (B (HC A30
VCC_A30 VCC_G32
G32 D
A34 G33
A39 VCC_A34 VCC_G33 G35
A44 VCC_A39 VCC_G35 G37
AK33 VCC_A44 VCC_G37 G38
AK35 VCC_AK33 VCC_G38 G40
AK37 VCC_AK35 VCC_G40 G42
AK38 VCC_AK37 VCC_G42 J30
AK40 VCC_AK38 VCC_J30 J33
AL33 VCC_AK40 VCC_J33 J37
AL37 VCC_AL33 VCC_J37 J40
AL40 VCC_AL37 VCC_J40 K33 +VCC_CORE
AM32 VCC_AL40 VCC_K33 K35
AM33 VCC_AM32 VCC_K35 K37
VCC_AM33 VCC_K37
100_0402_1%
AM35 K38
AM37 VCC_AM35 VCC_K38 K40
VCC_AM37 VCC_K40
RC150
AM38 K42
G30 VCC_AM38 VCC_K42 K43
VCC_G30 VCC_K43
2
+VCC_CORE_G0 K32 E32 VCCSENSE
RSVD_K32 VCC_SENSE E33 VCCSENSE <60>
TP32 VSSSENSE
+VCC_CORE_G1 AK32 VSS_SENSE VSSSENSE <60>
RSVD_AK32
1
B63 H_CPU_SVIDALRT#
100_0402_1%
TP33
AB62 VIDALERT# A63 VIDSCLK
VCCOPC_AB62 VIDSCK VIDSCLK <60>
RC151
P62 D64 VIDSOUT
V62 VCCOPC_P62 VIDSOUT
VCCOPC_V62 G20
2
H63 VCCSTG_G20
VCC_OPC_1P8_H63
G61
VCC_OPC_1P8_G61
AC63
C AE63 VCCOPC_SENSE C
VSSOPC_SENSE
+1.0V_VCCSTG
AE62
AG62 VCCEOPIO
VCCEOPIO
AL63
AJ62 VCCEOPIO_SENSE
VSSEOPIO_SENSE
. 6 . )# @6 ". -. ? D%( "& 4'
B G C
B B
+1.0V_VCCST
- (%" +
1
56_0402_1%
RC152
0/ =#7/ 0;/ $/? ?0 $? 7= ?/ 0

7= ?/ 0 . =?
2
2 1 H_CPU_SVIDALRT#
<60> VIDALERT_N
RC153 220_0402_5%
+1.0V_VCCST
- (+(
100_0402_1%
1
0/ =#7/ 0;/ $/? ?0 $? 7= ?/ 0

RC154
7= ?/ 0 . =?
2
VIDSOUT
<60> VIDSOUT
A A

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5 4 3 2 1
5 4 3 2 1
Main Func = CPU

' +1 , =#, ' ) +B 44C1 #(B (HC
' +H 1 , =#, ' ) +B 4C1 4@(B (HC
+VCC_GT_42 +VCC_GT
UC1M
Vinafix.com
SKL-U
+VCC_GT
D CPU POWER 2 OF 4 D
N70
A48 VCCGT N71
A53 VCCGT VCCGT R63
A58 VCCGT VCCGT R64
A62 VCCGT VCCGT R65
A66 VCCGT VCCGT R66
AA63 VCCGT VCCGT R67
AA70 VCCGT VCCGT T62
AA71 VCCGT VCCGT U65
AC64 VCCGT VCCGT U68
AC65 VCCGT VCCGT U71
AC66 VCCGT VCCGT W63
J43 VCCGT VCCGT W69
J45 VCCGT VCCGT W70
J46 VCCGT VCCGT W71
J48 VCCGT VCCGT Y62
J50 VCCGT VCCGT +VCC_CORE_42
J52 VCCGT
J53 VCCGT AK42
J55 VCCGT VCCGTX_AK42 AK43
C J60 VCCGT VCCGTX_AK46 AK48 +VCC_GT +VCC_GT_AK52 C
+VCC_GT_K52 K48 VCCGT VCCGTX_AK48 AK50
K50 VCCGT VCCGTX_AK50 AK52
K58 VCCGT VCCGTX_AK58 AK60 +VCC_GT +VCC_GT_AK52
L62 VCCGT VCCGTX_AK70 AL43
L63 VCCGT VCCGTX_AL43 AL46
L64 VCCGT VCCGTX_AL46 AL50 RC443 1 U23@ 2 0_0402_5%
L66 VCCGT VCCGTX_AL53 AL56 @5
L68 VCCGT VCCGTX_AL60 AM48
+VCC_GT L69 VCCGT VCCGTX_AM48 AM50 +VCC_GT_42 +VCC_GT_K52
L70 VCCGT VCCGTX_AM50 AM52
L71 VCCGT VCCGTX_AM52 AM53
M62 VCCGT VCCGTX_AM53 AM56
VCCGT VCCGTX_AM56
1
100_0402_1%
N63 AM58 RC157 1 U22@ 2 0_0402_5%

N64 VCCGT VCCGTX_AM58 AU58
VCCGT VCCGTX_AU58 @5
RC155
N66 AU63
N67 VCCGT VCCGTX_AU63 BB57
N69 VCCGT VCCGTX_BB57 BB66
2
VCCGT VCCGTX_BB66
VCC_GT_SENSE J70 AK62
<60> VCC_GT_SENSE VSS_GT_SENSE J69 VCCGT_SENSE VCCGTX_SENSE
<60> VSS_GT_SENSE AL61
VSSGT_SENSE VSSGTX_SENSE
1
100_0402_1%
B B
RC156
. -/ 4 (/ ( 4 *. % !" %"0+ / .//" +" 0. !% 4 " - /

2
A A

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5 4 3 2 1
5 4 3 2 1
Main Func = CPU
+1.0VS_VCCIO
Vinafix.com (#, +1.2V_DDR

1
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D
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10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1
CC49
CC50
1 1 1 1 1 1
@ CC26
@ CC27
CC28
CC29
CC30
CC31
CC45
CC46
CC47
CC48
2 2 2 2 2 2
2 2 2 2 2 2 +1.0VS_VCCIO
UC1N SKL-U
CPU POWER 3 OF 4
AU23 AK28
! AU28 VDDQ_AU23 VCCIO AK30
AU35 VDDQ_AU28 VCCIO AL30
AU42 VDDQ_AU35 VCCIO AL42
VDDQ_AU42 VCCIO
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 BB23 AM28
BB32 VDDQ_BB23 VCCIO AM30
VDDQ_BB32 VCCIO +VCC_SA
@ CC32
@ CC33
@ CC34
@ CC35
CC36
CC37
CC38
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
BB41 AM42 1 1 1 1
BB47 VDDQ_BB41 VCCIO
2 2 2 2 2 2 2 VDDQ_BB47
CC51
CC52
CC53
CC54
BB51 AK23
VDDQ_BB51 VCCSA AK25
VCCSA G23 2 2 2 2
! AM40 VCCSA G25
VDDQC VCCSA G27
VCCSA
10U_0402_6.3V6M
1U_0402_6.3V6K
A18 G28
VCCST VCCSA J22
1 1 VCCSA
CC39
CC40
A22 J23
VCCSTG_A22 VCCSA J27
AL23 VCCSA K23
2 2 VCCPLL_OC VCCSA K25
+1.0V_VCCST K20 VCCSA K27
K21 VCCPLL_K20 VCCSA K28 E #
VCCPLL_K21 VCCSA
C
VCCSA
K30 ( ; C
AM23 VCCIO_SENSE TP38

VCCIO_SENSE AM22 VSSIO_SENSE TP39 +1.0V_VCCSTG +1.0VS_VCCIO
+1.0V_VCCSTG VSSIO_SENSE
1U_0402_6.3V6K
1 JP1 PJP@
H21 1 2
VSSSA_SENSE 1 2
CC41
H20
! VCCSA_SENSE
100_0402_1%
JUMP_43X79 1
2 CZ8
RC160
SKL-U_BGA1356 14 OF 20 0.1U_0402_25V6
+1.2V_VCCSFR_OC
1U_0402_6.3V6K
1 2 @
1 +VCC_SA Imax : 3.4 A 2
CC42
RC159 100_0402_1%
2
+1.0V_VCCST POP option with Volume
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CC43
1 VSA_SEN- <60>
VSA_SEN+ <60>
CC44
2
2
B B
'#, ) + 8 Imax : 0.24 A '#, ) + 8

E 4
( ; +1.0V_PRIM Imax : 3.4 A + 0.04A
@ UZ2
CZ21 2 1 JP2 PJP@ 1 +1.0V_VCCSTG
2 1 2 VIN1
+1.0V_VCCST VIN2
DZ5 1U_0402_6.3V6K UZ1
1 2 +5VALW 7 6 1 2
1 7 +1.0V_VCCST_C PAD-OPEN1x1m VIN thermal VOUT
+1.0V_PRIM VIN VOUT
RB751S40T1G_SOD523-2 2 8 1 2 3 CZ6
VIN VOUT CZ2 0.1U_0402_10V7K VBIAS 0.1U_0402_10V7K
1.0V_VCCST_EN 1
1U_0402_6.3V6K
0.1U_0402_10V7K
@
1 RZ1 2 3 6 1 4 5
<11,57,59> SIO_SLP_S4# ON CT ON GND
CZ4
CZ5
22.1K_0402_1% RZ2
1 0_0402_5%
1
CZ1 4 1 @ 2 2 TPS22961DNYR_WSON8
+5VALW VBIAS 2
5 CZ3
GND +3VALW , 5 5 $(
0.1U_0402_10V7K
0.1U_0402_10V7K
1 9 470P_0402_50V7K
+ 3#4, 8 I 3#,
2
2 GND
CZ22
5
TPS22967DSGR_SON8_2X2
2 1 +1.0V_VCCSTG +1.0V_VCCST
P
<11,36> SIO_SLP_S3# IN1 4 VCCSTG_EN 1 2 VCCSTG_EN_R
2 O RZ3 49.9K_0402_1% 1 @ 2
<11,22,25> SIO_SLP_S0# IN2 1
G
RZ4 0_0603_5%
UC9 @ 1 2 CZ7
UC9 SN74AHC1G08DCKR_SC70-5 3 0.1U_0402_10V7K
DZ2 2 pop option with UZ1
A RB751S40T1G_SOD523-2 A
SA00000OH00
LOKI@
S IC MC74VHC1G08DFT2G SC70 5P AND

UC9
SA741080400
MAD@
& ( ,) *+ <$ 8 6& &
S IC 74AHC1G08GW SOT353 AND AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
5 4 3 2 1
5 4 3 2 1
Main Func = CPU 7= ?/ ( #,% L 3 . =

+1.0V_PRIM +1.0V_PRIM +1.0V_PRIM
+1.0V_PRIM
7= ?/ ( #,% L 3 . = 7= ?/ ( B #,% L .= +1.0V_SRAM
* 7= ?/ ( ! #,% L .=
+3VALW_PCH RC161 1 2 0_0603_5%
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 7= ?/ ( @ #,% L 3 . =
+3VALW_PCH +3VALW_PCH
@ CC57
@ CC58
Vinafix.com +1.0V_APLLEBB
CC55
CC56
1U_0402_6.3V6K
1 @
@ CC64
UC1O SKL-U 7= ?/ ( ! #,% L .=
'#, ) *D + 8 2 2 2 2
1P_0402_50V8
1U_0402_6.3V6K
CPU POWER 4 OF 4 1 1
CC65
@ CC66
RC162 1 2 0_0603_5%
D AB19 2 D
AB20 VCCPRIM_1P0 AK15
VCCPRIM_1P0 VCCPGPPA +1.8V_PRIM 2 2
P18 AG15
+1.0V_PRIM +1.0V_MPHYGT VCCPRIM_1P0 VCCPGPPB Y16
7= ?/ ( #,% L .= VCCPGPPC
AF18 Y15
VCCPRIM_CORE VCCPGPPD +3VALW_PCH
RC174 1 @ 2 0_0603_5% AF19 T16
V20 VCCPRIM_CORE VCCPGPPE AF16
VCCPRIM_CORE VCCPGPPF +1.8V_PRIM +3VALW_PCH
V21 AD15
VCCPRIM_CORE VCCPGPPG +3VALW_PCH
Imax : 2.8 A AL1 V19
DCPDSW_1P0 VCCPRIM_3P3_V19
7= ?/ (' B #,% L 3 . =
+1.8V_PRIM
1U_0402_6.3V6K
K17 T1 1
VCCMPHYAON_1P0 VCCPRIM_1P0_T1 +1.0V_PRIM
@ CC67
L1
VCCMPHYAON_1P0 AA1
VCCATS_1P8 7= ?/ ( #,% L .=
+1.0V_MPHYGT N15
VCCMPHYGT_1P0_N15 +RTC_CELL_PCH +RTC_CELL 2
1U_0402_6.3V6K
N16 AK17 1
VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3 +3VALW_PCH
N17 GEN8@
VCCMPHYGT_1P0_N17
CC68
P15 AK19 1 2
P16 VCCMPHYGT_1P0_P15 VCCRTC_AK19 BB14 RC199 0_0402_5%
VCCMPHYGT_1P0_P16 VCCRTC_BB14 7= ?/ ( B #,% L 3 . = 2
47U_0805_6.3V6M
1U_0402_6.3V6K
0.1U_0201_6.3V6K
1 1
1U_0201_6.3V6M
@ CC59
K15 BB10
0.1U_0201_6.3V6K
+1.0V_AMPHYPLL VCCAMPHYPLL_1P0 DCPRTC
CC60
L15 7= ?/ ( #,% L 3 . = 1 1
VCCAMPHYPLL_1P0
CC70
CC71
A14 1
2 2 VCCCLK1 +1.0V_PRIM
CC69
V15
+1.0V_APLL VCCAPLL_1P0 K19
VCCCLK2 +1.0V_CLK2 2 2
AB17
+1.0V_PRIM VCCPRIM_1P0_AB17 2
Y18 L21
VCCPRIM_1P0_Y18 VCCCLK3
AD17 N20
+3.3V_ALW_DSW VCCDSW_3P3_AD17 VCCCLK4 +1.0V_CLK4
AD18
AJ17 VCCDSW_3P3_AD18 L19 +1.0V_PRIM
VCCDSW_3P3_AJ17 VCCCLK5 +1.0V_CLK5
C AJ19 A10 C
+1.0V_SRAM +3.3V_HDA VCCHDA VCCCLK6
7= ?/ ( #,% L 3 . =
1U_0402_6.3V6K
AJ16 AN11 TP76 1
+3.3V_SPI VCCSPI GPP_B0/CORE_VID0
@ CC72
AN13 TP77
AF20 GPP_B1/CORE_VID1
7= ?/ ( 3 #,% L .= VCCSRAM_1P0
AF21
+3VALW_PCH VCCSRAM_1P0 2
1U_0402_6.3V6K
1 T19
VCCSRAM_1P0
@ CC62
T20
+1.0V_PRIM VCCSRAM_1P0
AJ21
2 +1.0V_APLLEBB VCCPRIM_3P3_AJ21
AK20
VCCPRIM_1P0_AK20
7= ?/ ( #,% L 3 . = N18
VCCAPLLEBB
1U_0402_6.3V6K
1 1
CC63
CC101
0.5P_0402_50V8
2 2 RF@
+3VALW_PCH +3.3V_HDA +1.0V_MPHYGT +1.0V_AMPHYPLL +1.0V_PRIM +1.0V_CLK2 +1.0V_PRIM +1.0V_CLK5 +3VALW_PCH

7= ?/ ( 4 B #,% L .= 7= ?/ ( 5 ( #,% L .= 7= ?/ ( #,% L 3 . =
L2
1 2 RC169 1 @ 2 0_0603_5% RC170 1 @ 2 0_0603_5% RC171 1 @ 2 0_0603_5%
BLM15BD601SN1D_2P 7= ?/ ( #,% L 3 . =
47U_0805_6.3V6M
47U_0603_6.3V6M
47U_0603_6.3V6M
0.1U_0402_10V7K
1U_0402_6.3V6K
0.1U_0402_10V7K
1U_0402_6.3V6K
1 1 1 1 1 1 7= ?/ ( B #,% L .= 1 1 1
CC76 @
CC77 @
B B
@ CC74
CC78
@ CC73
@ CC75
CC79
CC100 CC61
0.5P_0402_50V8 0.5P_0402_50V8 7= ?/ ( B #,% L .=
2 RF@ 2 @RF@ 2 2 2 2 2 2 2
+1.0V_PRIM +1.0V_APLL
+3VALW +3.3V_ALW_DSW 7= ?/ (' #,% L .= +1.0V_PRIM +1.0V_CLK4
L1
1 GEN8@ 2 1 2
RC163 0_0402_5% BLM15BD601SN1D_2P RC173 1 @ 2 0_0603_5%
1 1
47U_0603_6.3V6M
22U_0603_6.3V6M
@ CC80
22U_0603_6.3V6M
@ CC81
1 1 7= ?/ ( 3 #,% L .= 1
CC84 @
CC83 CC82
0.5P_0402_50V8 0.5P_0402_50V8
2 RF@ 2 @RF@
2 2 2
+3VALW +1.8V_PRIM +1.0V_PRIM

1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1
A A
CC85
CC86
CC87
2 2 2

& ( -) *+ 1 <$
5 4 3 2 1
5 4 3 2 1
Main Func = CPU
UC1P SKL-U UC1Q SKL-U

UC1R SKL-U
GND 1 OF 3 GND 2 OF 3
GND 3 OF 3
A5 AL65 AT63 BA49 F8 L18
A67
A70
AA2
VSS
VSS
VSS
VSS
VSS
VSS
AL66
AM13
AM21
Vinafix.com
AT68
AT71
AU10
VSS
VSS
VSS
VSS
VSS
VSS
BA53
BA57
BA6
G10
G22
G43
VSS
VSS
VSS
VSS
VSS
VSS
L2
L20
L4
AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8
D AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10 D
AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13
AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19
AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21
AD13 VSS VSS AM68 AV71 VSS VSS BB43 G63 VSS VSS P17
AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10
AF1 VSS VSS AN42 AW36 VSS VSS D18 J8 VSS VSS U63
AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
C AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17 C
AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
AH64 VSS VSS AR15 AY66 VSS VSS E11
AH67 VSS VSS AR16 B10 VSS VSS E15
AJ15 VSS VSS AR20 B14 VSS VSS E18
AJ18 VSS VSS AR23 B18 VSS VSS E21 SKL-U_BGA1356 18 OF 20
AK11 VSS VSS AR42 B34 VSS VSS E53
AK27 VSS VSS AR5 B58 VSS VSS F1
AK8 VSS VSS AR55 BA1 VSS VSS F23
AL2 VSS VSS AR58 BA10 VSS VSS F27
AL35 VSS VSS AT2 BA2 VSS VSS F33
AL52 VSS VSS AT4 F68 VSS VSS F40
AL58 VSS VSS AT56 VSS VSS BA41
B AL64 VSS VSS AT58 VSS B
VSS VSS
SKL-U_BGA1356 16 OF 20 SKL-U_BGA1356 17 OF 20
A A

& ( *) *+8%%
5 4 3 2 1
5 4 3 2 1
Main Func = DDR

<7> DDR_A_D[0..63]
<7> DDR_A_MA[0..13]
<7> DDR_A_DQS#[0..7]
<7> DDR_A_DQS[0..7] +1.2V_DDR JDIMM1 CONN@
Layout Note: Layout Note: +1.2V_DDR
1 2
Place near JDIMM1.257,259 Place near JDIMM1.258 DDR_A_D1 3 VSS1 VSS2 4 DDR_A_D0
5 DQ5 DQ4 6
DDR_A_D5 7 VSS3 VSS4 8 DDR_A_D4
9 DQ1 DQ0 10
DDR_A_DQS#0 11 VSS5 VSS6 12
Vinafix.com
DDR_A_DQS0 13 DQS0_c DM0_n/DBI0_n 14
+2.5V_MEM +0.6V_DDR_VTT 15 DQS0_t VSS7 16 DDR_A_D6
DDR_A_D7 17 VSS8 DQ6 18
Layout Note: DQ7 VSS9 DDR_A_D2
19 20
Place near JDIMM1.255 DDR_A_D3 21 VSS10 DQ2 22
DQ3 VSS11 DDR_A_D12
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
D 23 24 D
DDR_A_D9 VSS12 DQ12
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
25 26
DQ13 VSS13 DDR_A_D13
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1 1 1 1 27 28
DDR_A_D8 VSS14 DQ8
CD5
CD6
CD7
CD8
1 1 1 1 29 30
DQ9 VSS15 DDR_A_DQS#1
CD3
CD4
31 32
VSS16 DQS1_c DDR_A_DQS1
CD1
CD2
33 34
2 2 2 2 +3VS 35 DM1_n/DBI_n DQS1_t 36
2 2 2 2 DDR_A_D10 37 VSS17 VSS18 38 DDR_A_D15
39 DQ15 DQ14 40
43 DQ10 DQ11 44
DDR_A_D16 VSS21 VSS22 DDR_A_D21
0.1U_0402_16V7K~D
2.2U_0402_6.3V6M
45 46
47 DQ21 DQ20 48
1 2 DDR_A_D17 VSS23 VSS24 DDR_A_D20
CD9
CD10
49 50
51 DQ17 DQ16 52
DDR_A_DQS#2 53 VSS25 VSS26 54
2 1 DDR_A_DQS2 55 DQS2_c DM2_n/DBI2_n 56
57 DQS2_t VSS27 58 DDR_A_D19
DDR_A_D22 59 VSS28 DQ22 60
61 DQ23 VSS29 62 DDR_A_D23
DDR_A_D18 63 VSS30 DQ18 64
Layout Note: DQ19 VSS31 DDR_A_D28
65 66
Place near JDIMM1 DDR_A_D24 67 VSS32 DQ28 68
69 DQ29 VSS33 70 DDR_A_D25
DDR_A_D29 71 VSS34 DQ24 72
73 DQ25 VSS35 74 DDR_A_DQS#3
75 VSS36 DQS3_c 76 DDR_A_DQS3
+1.2V_DDR 77 DM3_n/DBI3_n DQS3_t 78
81 DQ30 DQ31 82
DQ26 DQ27
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
85 86
87 VSS41 VSS42 88
1 1 1 1 1 1 1 1 CB5/NC CB4/NC
CD11
CD12
CD13
CD14
CD15
CD16
CD17
CD18
89 90
91 VSS43 VSS44 92
93 CB1/NC CB0/NC 94
2 2 2 2 2 2 2 2 95 VSS45 VSS46 96
97 DQS8_c DM8_n/DBI_n/NC 98
99 DQS8_t VSS47 100
101 VSS48 CB6/NC 102
C 103 CB2/NC VSS49 104 C
105 VSS50 CB7/NC 106
107 CB3/NC VSS51 108 DDR4_DRAMRST#
DDR_A_CKE0 VSS52 RESET_n DDR_A_CKE1 DDR4_DRAMRST# <21>
109 110
<7> DDR_A_CKE0 CKE0 CKE1 DDR_A_CKE1 <7>
111 112
+1.2V_DDR DDR_A_BG1 113 VDD1 VDD2 114
<7> DDR_A_BG1 DDR_A_BG0 BG1 ACT_n DDR_A_ALERT# DDR_A_ACT# <7>
115 116
<7> DDR_A_BG0 BG0 ALERT_n DDR_A_ALERT# <7>
117 118
DDR_A_MA12 119 VDD3 VDD4 120 DDR_A_MA11
DDR_A_MA9 121 A12 A11 122 DDR_A_MA7
A9 A7
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
123 124
DDR_A_MA8 125 VDD5 VDD6 126 DDR_A_MA5
1 DDR_A_MA6 A8 A5 DDR_A_MA4
1 1 1 1 1 1 1 1 127 128
+ CD27 129 A6 A4 130
DDR_A_MA3 VDD7 VDD8 DDR_A_MA2
CD19
CD20
CD21
CD22
CD23
CD24
CD25
CD26
330U_D2_2V_Y 131 132

DDR_A_MA1 133 A3 A2 134 2 RD23 1
+1.2V_DDR All VREF traces should
2 2 2 2 2 2 2 2 2 135 A1 EVENT_n/NF 136 240_0402_1%
DDR_A_CLK0 VDD9 VDD10 DDR_A_CLK1
have 10 mil trace width
<7> DDR_A_CLK0
137 138 DDR_A_CLK1 <7>
DDR_A_CLK#0 139 CK0_t CK1_t/NF 140 DDR_A_CLK#1
<7> DDR_A_CLK#0 CK0_c CK1_c/NF DDR_A_CLK#1 <7>
141 142
DDR_A_PAR 143 VDD11 VDD12 144 DDR_A_MA0
<7> DDR_A_PAR DDR_A_BS1 PARITY A0 DDR_A_MA10
145 146
<7> DDR_A_BS1 BA1 A10/AP
147 148
DDR_A_CS#0 149 VDD13 VDD14 150 DDR_A_BS0
<7> DDR_A_CS#0 DDR_A_WE# CS0_n BA0 DDR_A_RAS# DDR_A_BS0 <7>
151 152
<7> DDR_A_WE# WE_n/A14 RAS_n/A16 DDR_A_RAS# <7>
153 154
DDR_A_ODT0 155 VDD15 VDD16 156 DDR_A_CAS#
<7> DDR_A_ODT0 DDR_A_CS#1 ODT0 CAS_n/A15 DDR_A_MA13 DDR_A_CAS# <7>
157 158
<7> DDR_A_CS#1 CS1_n A13
159 160
DDR_A_ODT1 161 VDD17 VDD18 162 TP40
<7> DDR_A_ODT1 ODT1 C0/CS2_n/NC +V_DDR_REFA
163 164
165 VDD19 VREFCA 166 DIMM_CHA_SA2
TP41 167 C1, CS3_n,NC SA2 168
DDR_A_D36 VSS53 VSS54 DDR_A_D33
0.1U_0402_16V7K~D
169 170
171 DQ37 DQ36 172
DDR_A_D37 VSS55 VSS56 DDR_A_D32 1
CD28
173 174
175 DQ33 DQ32 176
+1.2V_DDR DDR_A_DQS#4 177 VSS57 VSS58 178
+1.2V_DDR 2
B +3VS +3VS +3VS DDR_A_D39 183 VSS60 DQ39 184 B
185 DQ38 VSS61 186 DDR_A_D35
DDR_A_D34 187 VSS62 DQ35 188
189 DQ34 VSS63 190 DDR_A_D45
VSS64 DQ45
1
DDR_A_D41 191 192

DQ44 VSS65
1
RD7 193 194 DDR_A_D44

RD1 RD2 RD3 470_0402_1% DDR_A_D40 195 VSS66 DQ41 196
@ @ @ 197 DQ40 VSS67 198 DDR_A_DQS#5
0_0402_5% 0_0402_5% 0_0402_5% VSS68 DQS5_c DDR_A_DQS5
199 200
+1.2V_DDR
2
201 DM5_n/DBI5_n DQS5_t 202

2

DIMM_CHA_SA0 DIMM_CHA_SA1 DIMM_CHA_SA2 DDR4_DRAMRST# 2 @ 1 205 DQ46 DQ47 206
H_DRAMRST# <7> DDR_A_D42 VSS71 VSS72 DDR_A_D46
RD8 0_0402_5% 207 208
209 DQ42 DQ43 210
VSS73 VSS74
1
DDR_A_D48 211 212 DDR_A_D53

1 DQ52 DQ53
RD4 RD5 RD6 @ 213 214
@ @ @ CD29 DDR_A_D52 215 VSS75 VSS76 216 DDR_A_D49
0_0402_5% 0_0402_5% 0_0402_5% DQ49 DQ48
0.1U_0402_16V7K~D 217 218
2 DDR_A_DQS#6 219 VSS77 VSS78 220
+1.2V_DDR
2

DDR_A_D55 225 VSS80 DQ54 226
227 DQ55 VSS81 228 DDR_A_D51
DDR_A_D50 229 VSS82 DQ50 230
231 DQ51 VSS83 232 DDR_A_D59
DDR_A_D57 233 VSS84 DQ60 234
235 DQ61 VSS85 236 DDR_A_D58
DDR_A_D56 237 VSS86 DQ57 238
+V_DDR_REFA_R +1.2V_DDR 239 DQ56 VSS87 240 DDR_A_DQS#7
241 VSS88 DQS7_c 242 DDR_A_DQS7
VSS89 VSS90
1
DDR_A_D60 245 246 DDR_A_D62

RD10 247 DQ62 DQ63 248
1K_0402_1%~D DDR_A_D61 249 VSS91 VSS92 250 DDR_A_D63
20mil 251 DQ58 DQ59 252
PCH_SMBCLK 253 VSS93 VSS94 254 PCH_SMBDATA
<8,21,31,34> PCH_SMBCLK PCH_SMBDATA <8,21,31,34>
2
255 SCL SDA 256 DIMM_CHA_SA0

+V_DDR_REFA +3VS VDDSPD SA0
RD9 1 2 2_0402_1% +2.5V_MEM
257 258 +0.6V_DDR_VTT
259 VPP1 VTT 260 DIMM_CHA_SA1
261 VPP2 SA1 262
1 GND1 GND2
1
A A
CD30 RD12
0.022U_0402_25V7K 1K_0402_1%~D
2
1
RD11
24.9_0402_1% LOTES_ADDR0206-P001A02~D
DEREN_40-42271-26001RHF
SP07001CY0L
2

$* && =$8%
5 4 3 2 1
5 4 3 2 1
Main Func = DDR

+1.2V_DDR JDIMM2 CONN@
<7> DDR_B_D[0..63] +1.2V_DDR
<7> DDR_B_MA[0..13]
1 2
<7> DDR_B_DQS#[0..7] DDR_B_D13 VSS1 VSS2 DDR_B_D9
3 4
<7> DDR_B_DQS[0..7] DQ5 DQ4
Layout Note: Layout Note: 5 6
DDR_B_D12 7 VSS3 VSS4 8 DDR_B_D8
Place near JDIMM2.258 Place near JDIMM2.257,259 9 DQ1 DQ0 10
DDR_B_DQS#1 11 VSS5 VSS6 12
DDR_B_DQS1 13 DQS0_c DM0_n/DBI0_n 14
15 DQS0_t VSS7 16 DDR_B_D14
Vinafix.com
DDR_B_D15 17 VSS8 DQ6 18
19 DQ7 VSS9 20 DDR_B_D11
+0.6V_DDR_VTT +2.5V_MEM 23 DQ3 VSS11 24 DDR_B_D4
D 27 DQ13 VSS13 28 DDR_B_D0 D
31 DQ9 VSS15 32 DDR_B_DQS#0
1U_0402_6.3V6K~D VSS16 DQS1_c DDR_B_DQS0
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
Layout Note: 33 34
35 DM1_n/DBI_n DQS1_t 36
1 1 1 1 1 1 1 1 Place near JDIMM2.255 DDR_B_D7 VSS17 VSS18 DDR_B_D3
CD31
CD32
CD35
CD36
37 38
DQ15 DQ14
CD33
CD34
CD37
CD38
39 40
2 2 2 2 2 2 2 2 43 DQ10 DQ11 44
47 DQ21 DQ20 48
+3VS 51 DQ17 DQ16 52
DDR_B_D19 59 VSS28 DQ22 60
DQ23 VSS29 DDR_B_D18
0.1U_0402_16V7K~D
2.2U_0402_6.3V6M
61 62
DDR_B_D22 63 VSS30 DQ18 64
1 2 DQ19 VSS31 DDR_B_D25
CD39
CD40
65 66
DDR_B_D29 67 VSS32 DQ28 68
69 DQ29 VSS33 70 DDR_B_D28
2 1 DDR_B_D24 71 VSS34 DQ24 72
75 VSS36 DQS3_c 76 DDR_B_DQS3
Layout Note: DM3_n/DBI3_n DQS3_t
77 78
Place near JDIMM2 DDR_B_D26 79 VSS37 VSS38 80 DDR_B_D31
81 DQ30 DQ31 82
85 DQ26 DQ27 86
87 VSS41 VSS42 88
89 CB5/NC CB4/NC 90
91 VSS43 VSS44 92
93 CB1/NC CB0/NC 94
95 VSS45 VSS46 96
+1.2V_DDR 97 DQS8_c DM8_n/DBI_n/NC 98
99 DQS8_t VSS47 100
101 VSS48 CB6/NC 102
103 CB2/NC VSS49 104
VSS50 CB7/NC
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
105 106
C 107 CB3/NC VSS51 108 DDR4_DRAMRST# C
1 1 1 1 1 1 1 1 DDR_B_CKE0 VSS52 RESET_n DDR_B_CKE1 DDR4_DRAMRST# <20>
CD41
CD42
CD43
CD44
CD45
CD46
CD47
CD48
109 110
<7> DDR_B_CKE0 CKE0 CKE1 DDR_B_CKE1 <7>
111 112
DDR_B_BG1 113 VDD1 VDD2 114
2 2 2 2 2 2 2 2 <7> DDR_B_BG1 DDR_B_BG0 BG1 ACT_n DDR_B_ALERT# DDR_B_ACT# <7>
115 116
<7> DDR_B_BG0 BG0 ALERT_n DDR_B_ALERT# <7>
117 118
DDR_B_MA12 119 VDD3 VDD4 120 DDR_B_MA11
DDR_B_MA9 121 A12 A11 122 DDR_B_MA7
123 A9 A7 124
DDR_B_MA8 125 VDD5 VDD6 126 DDR_B_MA5
DDR_B_MA6 127 A8 A5 128 DDR_B_MA4
129 A6 A4 130
+1.2V_DDR DDR_B_MA3 131 VDD7 VDD8 132 DDR_B_MA2
DDR_B_MA1 133 A3 A2 134 2 RD24 1
135 A1 EVENT_n/NF 136 240_0402_1%
+1.2V_DDR
DDR_B_CLK0 137 VDD9 VDD10 138 DDR_B_CLK1
<7> DDR_B_CLK0 DDR_B_CLK1 <7> All VREF traces should
DDR_B_CLK#0 139 CK0_t CK1_t/NF 140 DDR_B_CLK#1
<7> DDR_B_CLK#0 CK0_c CK1_c/NF DDR_B_CLK#1 <7> have 10 mil trace width
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
141 142
DDR_B_PAR 143 VDD11 VDD12 144 DDR_B_MA0
<7> DDR_B_PAR DDR_B_BS1 PARITY A0 DDR_B_MA10
1 1 1 1 1 1 1 1 145 146
<7> DDR_B_BS1 BA1 A10/AP
147 148
DDR_B_CS#0 VDD13 VDD14 DDR_B_BS0
CD49
CD50
CD51
CD52
CD53
CD54
CD55
CD56
149 150
<7> DDR_B_CS#0 DDR_B_WE# CS0_n BA0 DDR_B_RAS# DDR_B_BS0 <7>
151 152
2 2 2 2 2 2 2 2 <7> DDR_B_WE# WE_n/A14 RAS_n/A16 DDR_B_RAS# <7>
153 154
DDR_B_ODT0 155 VDD15 VDD16 156 DDR_B_CAS#
<7> DDR_B_ODT0 DDR_B_CS#1 ODT0 CAS_n/A15 DDR_B_MA13 DDR_B_CAS# <7>
157 158
<7> DDR_B_CS#1 CS1_n A13
159 160
DDR_B_ODT1 161 VDD17 VDD18 162 TP43
<7> DDR_B_ODT1 ODT1 C0/CS2_n/NC +V_DDR_REFB
163 164
165 VDD19 VREFCA 166 DIMM_CHB_SA2
TP42 167 C1, CS3_n,NC SA2 168
171 DQ37 DQ36 172
DDR_B_D33 VSS55 VSS56 DDR_B_D37
0.1U_0402_16V7K~D
173 174
175 DQ33 DQ32 176
DDR_B_DQS#4 VSS57 VSS58 1
CD58
177 178
+1.2V_DDR
DDR_B_D34 183 VSS60 DQ39 184 2
185 DQ38 VSS61 186 DDR_B_D38
B DDR_B_D35 187 VSS62 DQ35 188 B
189 DQ34 VSS63 190 DDR_B_D40
DDR_B_D44 191 VSS64 DQ45 192
193 DQ44 VSS65 194 DDR_B_D41
DDR_B_D45 195 VSS66 DQ41 196
+3VS +3VS +3VS +1.2V_DDR 201 DM5_n/DBI5_n DQS5_t 202
205 DQ46 DQ47 206
209 DQ42 DQ43 210
VSS73 VSS74
1
DDR_B_D52 211 212 DDR_B_D49

RD13 RD14 RD15 213 DQ52 DQ53 214
@ @ @ DDR_B_D53 215 VSS75 VSS76 216 DDR_B_D48
0_0402_5% 0_0402_5% 0_0402_5% DQ49 DQ48
217 218
+1.2V_DDR
2

DIMM_CHB_SA0 DIMM_CHB_SA1 DIMM_CHB_SA2 223 DQS6_t VSS79 224 DDR_B_D55
DDR_B_D50 225 VSS80 DQ54 226
227 DQ55 VSS81 228 DDR_B_D54
VSS82 DQ50
1
DDR_B_D51 229 230

RD16 RD17 RD18 231 DQ51 VSS83 232 DDR_B_D56
@ @ @ DDR_B_D61 233 VSS84 DQ60 234
0_0402_5% 0_0402_5% 0_0402_5% DQ61 VSS85 DDR_B_D57
235 236
DDR_B_D60 237 VSS86 DQ57 238
2

247 DQ62 DQ63 248
+V_DDR_REFB_R DDR_B_D58 249 VSS91 VSS92 250 DDR_B_D62
+1.2V_DDR 251 DQ58 DQ59 252
PCH_SMBCLK 253 VSS93 VSS94 254 PCH_SMBDATA
<8,20,31,34> PCH_SMBCLK SCL SDA DIMM_CHB_SA0 PCH_SMBDATA <8,20,31,34>
255 256
+3VS VDDSPD SA0
1
257 258
+2.5V_MEM VPP1 VTT DIMM_CHB_SA1 +0.6V_DDR_VTT
RD20 259 260
1K_0402_1%~D 261 VPP2 SA1 262
GND1 GND2
20mil
2
A A
RD19 1 2 2_0402_1% +V_DDR_REFB
1
1 LOTES_ADDR0205-P001A02~D
RD21 DEREN_40-42261-26001RHF
CD59 1K_0402_1%~D SP07001HW0L
0.022U_0402_25V7K
2
2
1
RD22
24.9_0402_1% Security Classification Compal Secret Data
2
$* && =%0
5 4 3 2 1
5 4 3 2 1
Main Func = TPM UX1 UX1
SA0000AQ220 SA00008EL90
750@ 650@ +3VALW
0 S IC NPCT750JAAYX QFN 32P TPM S IC NPCT650VBBYX QFN 32P TPM
Vinafix.com CX1, CX2: colse to Pin1
0.1U_0402_10V7K
10U_0402_6.3V6M
1 1
H1 H3 H4 H5 H6 H7
CX2 TPM@
CX1 TPM@
D HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA D
2 2
+3.3V_SPI
1
1
1 TPM@ 2 TPM_SPI_IRQ# UX1 +3VS
H_3P0 H_5P0 H_3P0 H_3P0-G H_3P0-G H_3P0 RX4 10K_0402_5% 1
2 750@ 1 29 VSB
H8 H9 H10 H11 H12 H13 H14 RX9 30
0_0402_5% GPIO0/SDA 8
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA 2 650@ 1 3 GPIO1/SCL VDD1 14
<11,17,25> SIO_SLP_S0# GPIO2/GPX VHIO1
0.1U_0402_10V7K
10U_0402_6.3V6M
RX10 0_0402_5% 6 22 2 RX6 1 +3VS 1 1
GPIO3/BADD VHIO2
PCH_SPI_D1_TPM 0_0402_5%
CX3 TPM@
CX4 TPM@
RX1 1 TPM@ 2 33_0402_5% 24 2
1
1
<8> PCH_SPI_D1 RX2 1 TPM@ 2 33_0402_5% PCH_SPI_D0_TPM 21 LAD0/MISO NC1 7 650@750@
<8> PCH_SPI_D0 LAD1/MOSI NC2
1
H_5P6N TPM_SPI_IRQ# 18 10 2 2
<8> TPM_SPI_IRQ# 15 LAD2/SPI_IRQ# NC3 11 RX8 2 RX7 1
H_3P3-G H_3P5 H_3P5 H_3P2 H_3P2-G H_3P0X4P0 LAD3 NC4 +3.3V_SPI
25 0_0402_5%
RX3 1 TPM@ 2 33_0402_5% PCH_SPI_CLK_TPM 19 NC5 26 cTPM@ 0_0402_5%
<8> PCH_SPI_CLK LCLK/SCLK NC6
<8> PCH_SPI_CS#2 20 31 cTPM@
2
17 LFRAME#/SCS# NC7
<11,25,32,34,35,37,44> PLTRST# LRESET#/SPI_RST#/SRESET#
27 9
13 SERIRQ GND1 16
CLKRUN#/GPIO4/SINT# GND2 CX3, CX4: colse to Pin8
0.1U_0402_10V7K
0.1U_0402_10V7K
10U_0402_6.3V6M
HCPU1 HCPU2 HCPU3 HCPU4 28 23 1 1 1
HOLEA HOLEA HOLEA HOLEA RX5 LPCPD# GND3 32
GND4
CX7 TPM@
CX6 TPM@
CX5 TPM@
10K_0402_5% 4 33
650@750@ 5 PP PGND 12
TEST Reserved 2 2 2
C C
1
2
NPCT650VB2YX_QFN32_5X5 CX5, CX6: colse to Pin14
NPCT650:TPM@/650@/650@750@ @ CX7: colse to Pin22
H_4P0X3P7 H_3P7 H_4P0 H_3P7X4P0
NPCT750:TPM@/750@/650@750@
ChinaTPM:TPM@/cTPM@ UX1 place colse to UC3
SW TPM:fTPM@
FD1 FD2 FD3 FD4
1
Main Func = RTC
+RTC_VCC +3VLP +RTC_CELL +RTC_CELL_PCH +RTC_CELL

Q23 GEN9@
D1 LP2301ALT1G_SOT23-3
R1 2
1K_0402_5% anode 1 1 3
S
B cathode B
2 1 RTC_PWR 3
anode
1U_0402_6.3V6K
10K_0402_5%
1
BAS40C_SOT23-3
G
2
1
R73 GEN9@
1
C59 GEN9@
C1
0.47U_0402_6.3V6K
2
@ D7 GEN9@
2
2 2 1
1
RB751S40T1G_SOD523-2
R2
2
1
D
10M_0402_5% R78 GEN9@
RTCRST_ON
G
Q24 2 1 2 RTCRST_ON <11,25>

L2N7002WT1G_SC-70-3 G
2
0.1U_0402_25V6
3 1 RTC_DET# <9> GEN9@ S 1M_0402_5%
22P_0402_50V8J
100K_0402_5%
S
2
1
1
R79 GEN9@
C61 @
Q1
C60 GEN9@
2N7002K_SOT23-3
2
1
+3VALW_PCH +3.3V_ALW_DSW +3VALW
2 GEN9@ 1 1 3 1 GEN9@ 2
S
D
VCCDSW_ON <25>
A R84 0_0402_5% R66 100K_0402_5% A
1
Q15
LP2301ALT1G 1P SOT-23-3 R65
G
2
DSX@ 499K_0402_1%
2
DSX@
G

2
1 DSX@ 2 1 3
R67 49.9K_0402_1% 2016/12/01 2017/12/01 Title
D
Issued Date Deciphered Date

0 &)$0 )% #>
DSX@ Q4 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
L2N7002WT1G_SC-70-3 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
5 4 3 2 1
5 4 3 2 1
Main Func = Audio

moat
moat
+1.8V_PRIM +1.8V_AVDD
+5V_AVDD +5VS QA1
LN2306LT1G_SOT23-3
+5VS +5V_PVDD 2 @ 1 1 3 RA5 1 @ 2 0_0402_5%
S
RA4 0_0603_5%
1 2
Vinafix.com
1
1 @ 2 CA10 CA11 CA12
G
2
RA1 0_0805_5% RA42 1 2 33_0402_5% DMIC_DATA
<28> DMIC_DATA_EDP
CA1 1 CA2 CA3 1 CA4 Place close to Pin 26
10U_0603_10V6M
+3VS
10U_0603_6.3V6M
2
1
1
EMI@ 2 1
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
10U_0603_10V6M
10U_0603_10V6M
L5 1 2 BLM15PX221SN1D_2P DMIC_CLK Close pin40
D <28> DMIC_CLK_EDP D
2
2 2 AUD_AGND
MAD@RF@ MAD@RF@ L5 place colse to UA1
1
CA9 CA40
82P_0402_50V8J 82P_0402_50V8J +1.8V_CPVDD
2
AUD_AGND
RA6 1 @ 2 0_0402_5%
Layout Note: Layout Note:
Close pin41 Close pin46 2 1 CA14
CA13
.1U_0402_16V7K
10U_0603_6.3V6M
1 2
CLOSE TO UA1
+3VS +3V_DVDD +5V_PVDD +3V_DVDD +5V_AVDD +1.8V_CPVDD Close pin36
2
CA17
RA2 1 @ 2 0_0402_5% .1U_0402_16V7K
1
+5V_PVDD
68P_0201_50V8J
10P_0201_50V8J
68P_0201_50V8J
10P_0201_50V8J
68P_0201_50V8J
10P_0201_50V8J
68P_0201_50V8J
10P_0201_50V8J
2 1 1 1 1 1 1 1 1 1 +3V_DVDD +3V_DVDD
CA43
CA44
CA45
CA46
CA5 CA6
CA47 RF@
CA48 RF@
CA49 RF@
CA50 RF@
+5V_AVDD
2 1
10U_0603_6.3V6M
1 2 2 2 2 2 2 2 2 2
RF@
RF@
RF@
RF@
Close pin9 CA15 CA16
+1.8V_AVDD
.1U_0402_16V7K
.1U_0402_16V7K
10U_0603_6.3V6M
1 2
+1.8V_CPVDD
41
46
26
40
36
1
9
UA1
PVDD1
PVDD2
AVDD1
AVDD2
DVDD
CPVDD
DVDD-IO
11
Delete HDA_RST 12 I2C_SDA 31
C +LINE1_VREFO_L C
HDA_CODEC_BITCLK I2C_SCL LINE1-VREFO-L 30
LINE1-VREFO-R +LINE1_VREFO_R
10 29 +MIC2-VREFO
<12> HDA_CODEC_SYNC 6 SYNC MIC2-VREFO 28 AUD_VREF CA23 1 2 2.2U_0402_6.3V6M
<12> HDA_CODEC_BITCLK 5 BIT-CLK VREF 35 CBN 1 2
AUD_AGND moat +3VALW +RTC_CELL
<12> HDA_CODEC_SDOUT SDATA-OUT CBN
2
HDA_CODEC_SDIN0
33_0402_5%
1 2 8 37 CBP CA24 1U_0603_16V7

<12> HDA_SDIN0 SDATA-IN CBP
RA43
@EMI@
RA7 33_0402_5% RA11 1 @ 2 0_0402_5%

RA9 2 @ 1 0_0402_5% 4 20 V3D3_STB RA12 1 2 0_0402_5%
DMIC_DATA EAPD/DC DET 5VSTB
10 mils
RA8 1 @ 2 10K_0402_5% 2 10 mils
+3V_DVDD DMIC_CLK GPIO0/DMIC-DATA12
3 34 CPVEE CA25 2 1 1U_0603_16V7
1
47 GPIO1/DMIC-CLK CPVEE
<25> EC_MUTE# PDB
33P_0402_50V8J
48
RA41 1 2 100K_0402_5% SPDIFO/GPIO2/DMIC-DATA-34/DMIC-CLK-In/MIC-GPI
2
LDO1_CAP
CA38
@EMI@
CA20 1 2 10U_0603_6.3V6M 27
AUD_AGND
CA21 1 2 10U_0603_6.3V6M LDO2_CAP 39 LDO1-CAP 17 RING2 <24> Layout Note:
LDO3_CAP LDO2-CAP MIC2-L/RING2 SLEEVE <24>
CA22 1 2 10U_0603_6.3V6M 7 18 Width>40mil, to improve Headpohone Crosstalk noise
1
LDO3-CAP MIC2-R/SLEEVE 19 MIC_CAP 1 2

MIC-CAP AUD_AGND Change it to sharp will be better.
24 CA26 10U_0603_6.3V6M Add 2 vias (>0.5A) when trace layer change.
AUD_SPK_L+ 42 LINE2-L 23
RA43,CA38: close to UA1.6 Layout Note: <23> AUD_SPK_L+ AUD_SPK_L- 43 SPK-L+ LINE2-R 22
<23> AUD_SPK_L- AUD_SPK_R- SPK-L- LINE1-L LINE1_L <24>
Speaker trace width >40mil @ 2W4ohm speaker power <23> AUD_SPK_R-
44
SPK-R- LINE1-R
21
LINE1_R <24>
AUD_SPK_R+ 45 16 AUD_PC_BEEP
<23> AUD_SPK_R+ SPK-R+ PCBEEP 32
AUD_SENSE_A HP-OUT-L AUD_HP1_JACK_L <24>
13 33
14 HP/LINE1 JD1 HP-OUT-R AUD_HP1_JACK_R <24>
RA3 2 1 100K_0402_5% AUD_SENSE_A AUD_SENSE 1 RA10 2 15 MIC2/LINE2 JD2 25
+3V_DVDD SPDIFO/FRONT JD3/GPIO3 AVSS1 38
200K_0402_1% AVSS2 49
1 THERMAL PAD moat
@ CA7
moat .1U_0402_16V7K Layout Note: ALC3246-CG_MQFN48_6X6
2 Place close to Pin 13 RA17 1 @ 2 0_0402_5%
ALC3246-CG_MQFN48_6X6
AUD_AGND RA18 1 @ 2 0_0402_5%
AUD_AGND
B B
AUD_AGND
AUD_SENSE 10 mils RA39 1 @ 2 0_0603_5% 10 mils AUD_AGND
JACK_PLUG <24>
RA22 1 @ 2 0_0805_5%
1 1 1
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
EC3003 EMI@
EC2301 EMI@
EC2302 EMI@
2 2 2
Layout Note:
Speaker trace width >40mil @ 2W4ohm speaker power
CONN Pin Net name AUD_AGND Layout Note:
JSPK1 Tied at point only under
1 2 AUD_SPK_R+_C 1
<23> AUD_SPK_R+
RA13 EMI@ BLM15PD800SN1D_2P
AUD_SPK_R-_C 1 Pin1 SPK_R+ Codec or near the Codec
RA14 1 EMI@ 2 BLM15PD800SN1D_2P 2
<23> AUD_SPK_R- 1 2 AUD_SPK_L+_C 3 2
<23> AUD_SPK_L+
RA15 EMI@ BLM15PD800SN1D_2P
AUD_SPK_L-_C 3 Pin2 SPK_R-
RA16 1 EMI@ 2 BLM15PD800SN1D_2P 4
<23> AUD_SPK_L- 5 4
Pin3 SPK_L+ Place on the moat between GND & GNDA.
6 G1
G2
Pin4 SPK_L-
ACES_50224-00401-001
3
CONN@
SP02000GC10 DA3
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1 1 1 1 <12> SPKR 3
L03ESDL5V0CC3-2_SOT23-3
EMI@ CA27
EMI@ CA28
EMI@ CA29
EMI@ CA30
1 AUD_PC_BEEP_C 1 2 1 2 AUD_PC_BEEP
DA1
DA2
RA23 1K_0402_5% CA31 0.1U_0402_16V7K

2 2 2 2 2
<25> BEEP
1
BAT54C-7-F_SOT23-3
@ESD@
@ESD@
1
RA24
10K_0402_5%
A A
2
" -,*2
5 4 3 2 1
5 4 3 2 1
Main Func = Audio Jack
Vinafix.com
D D
E G
RA25 1 2 2.2K_0402_5%
+MIC2-VREFO
B < * 2 E G'5 ' 8 C
RA26 1 2 2.2K_0402_5%
<23> RING2 RA35 1 ESD@ 2 BLM15PX330SN1D_2P RING2_R

RA27 1 2 10_0402_1% AUD_HP1_JACK_L1 RA36 1 @ 2 0_0402_5% HPOUT_L
<23> AUD_HP1_JACK_L 1 2 LINE1-L_C RA28 1 2 1K_0402_5%
<23> LINE1_L CA32 10U_0603_10V6M RA29 1 2 4.7K_0402_5%
+LINE1_VREFO_L
RA31 1 2 10_0402_1% AUD_HP1_JACK_R1 RA37 1 @ 2 0_0402_5% HPOUT_R
<23> AUD_HP1_JACK_R 1 2 LINE1-L_R RA32 1 2 1K_0402_5% RA38 1 ESD@ 2 BLM15PX330SN1D_2P SLEEVE_R
<23> LINE1_R CA33 10U_0603_10V6M RA33 1 2 4.7K_0402_5%
+LINE1_VREFO_R
<23> SLEEVE
Layout Note:
Close to UA1
C C
Main Func = Audio Jack

E G
B < * 2 E G'5 ' 8 C
JHP1 CONN@
SLEEVE_R 3
HPOUT_L 1 G/M
L/R
B B
JACK_PLUG 5
<23> JACK_PLUG 5
JACK_PLUG_DET 6
6
HPOUT_R 2
CLOSE TO JHP1 R/L
HPOUT_R RING2_R 4
HPOUT_L 7 M/G
GND
1 YUQIU_PJ753-F07J1BE-B
2
JACK_PLUG
10K_0402_5%
RA34
10K_0402_5%
RA30
1 1 1 1 1 1 DC021512140
JACK_PLUG_DET JACK_PLUG_DET
100P_0402_50V8J
CA34 EMI@
100P_0402_50V8J
CA35 EMI@
680P_0402_50V8J
CA42 ESD@
680P_0402_50V8J
CA41 ESD@
ESD@
AZ5123-02S.R7G_SOT23-3
DA5
680P_0402_50V8J
CA36 @ESD@
680P_0402_50V8J
CA37 @ESD@
@ @
# 5
2
2 2 2 2 2 2
2
2
RA40 AUD_AGND
0_0402_5%
@
1
1
3
2
ESD@
DA4
ESD@
DA7
AUD_AGND
AUD_AGND AUD_AGND AUD_AGND AUD_AGND
A A
1

" 5 3
5 4 3 2 1
5 4 3 2 1
Main Func = EC DT1 UE1 EC@ RE1 MAD@ RE1 LOKI@ SD034100280 10K_0402_1% +3VALW_EC +3VALW_EC
2 1 SD034137280 13.7K_0402_1%
+3.3V_ADP_DCIN
SD034178280 17.8K_0402_1% Model ID Board ID
EC Chip CPN
1
Vinafix.com
RB551V-30_SOD323-2 SD034221280 22.1K_0402_1%
SD034270280 27K_0402_1% RE3 RE1
1 TYPEC@2 +3VALW_EC SD034324280 32.4K_0402_1% Ra 100K_0402_1% Ra 100K_0402_1%
+3.3V_VDD_PIC
RE72 0_0603_5% MEC1416-NU-D0_VTQFP128_14X14 10K_0402_1% 10K_0402_1% SD034374280 37.4K_0402_1% @ @
SD034499280 49.9K_0402_1%
2
+3VALW 1 @ 2 SD034576280 57.6K_0402_1% MODEL_ID BOARD_ID
+3VALW
RE2 0_0603_5%
SA0000A8L00 SD034100280 SD034100280 SD034649280 64.9K_0402_1%
10U_0603_6.3V6M
0.1U_0402_10V7K
1000P_0402_50V7K
@ CE7
1000P_0402_50V7K
@ CE8
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
RPE1 10K_8P4R_5% SD00000B180 73.2K_0402_1%
1 1 2 2 for Loki-L for Loki 1 1
2
0.1U_0402_10V7K
CE1
0.1U_0402_10V7K
CE2
5 4 KSI0 DE2 SD000002780 82.5K_0402_1%
CE5
CE6
CE9
CE10
CE11
CE12
CE13
6 3 KSI1 2 1 RE3 UMA@ RE3 DIS@ SD034931280 93.1K_0402_1% Rb RE4 Rb
7 2 KSI2 SD034107380 107K_0402_1% 100K_0402_1% RE6
2
8 1 KSI3 RB551V-30_SOD323-2 2 2 1 1 SD034120380 120K_0402_1% 2 2 100K_0402_1%
For
Board ID Select SD034137380 137K_0402_1%
1
SD034154380 154K_0402_1%
RPE2 10K_8P4R_5% EVT 10K SD034200380 200K_0402_1%
D D
5 4 KSI7 10K_0402_1% 37.4K_0402_1% DVT1 17.8K SD034232380 232K_0402_1%
6 3 KSI6 DVT2 27K
7 2 KSI5 Pilot 49.9K SD034100380 100K_0402_1% EC_AGND EC_AGND
8 1 KSI4
SD034100280 SD034374280
+3VALW_EC +1.8V_PRIM +1.8VALW_EC
RPE3 100K_8P4R_5% +3VALW_EC +1.8VALW_EC +3VALW_EC +3VALW
1 8 KSO0 1 @ 2 +RTC_CELL_VBAT 1 @ 2
+RTC_CELL PBAT_CHG_SMBDAT 1
1
2 7 KSO1 RE7 0_0603_5% 1 RE66 0_0603_5% 2
3 6 KSO2 RE8 4.7K_0402_5% RE49
4 5 KSO3 CE14 PBAT_CHG_SMBCLK 1 2 100K_0402_5%
PECI_EC
68P_0201_50V8J
10P_0201_50V8J
68P_0201_50V8J
10P_0201_50V8J
1 1 1 1 0.1U_0402_10V7K RE9 4.7K_0402_5%
PECI_EC <12> SML1_SMBDATA CMP_VIN0
2 2 CMP_VOUT0
CE36 RF@
CE38 RF@
1 @ 2 1 @
2
122
103
1
CE37 RF@
CE39 RF@
RPE4 100K_8P4R_5% RE10 2.2K_0402_5% RE52 100K_0402_5%
43
82
19
65
SML1_SMBCLK
5
1 8 KSO4 UE1 CE15 1 @ 2
2 7 KSO5 2 2 2 2 54 1 2 RE11 2.2K_0402_5%
VBAT
VTR
VTR
VTR
VTR
VTR
VTR
3 6 KSO6 VTR_33_18 DE1 @
4 5 KSO7 0.1U_0402_25V6 AZ5125-01H.R7G_SOD523-2 FAN1_TACH 1 2
KSO0 2 @ TP_WAKE_KBC# 1 2 CE28 220P_0402_50V8J
KSO1 14 GPIO027/KSO00/PVT_IO1 8 PBAT_CHG_SMBDAT RE14 100K_0402_5%
GPIO015/KSO01/PVT_CS# GPIO007/SMB01_DATA/SMB01_DATA18 PBAT_CHG_SMBCLK PBAT_CHG_SMBDAT <53,55> TYPEC_SMBDA
RPE5 100K_8P4R_5% KSO2 15 9 1 2
PBAT_CHG_SMBCLK <53,55>
2
1 8 KSO10 KSO3 16 GPIO016/KSO02/PVT_SCLK GPIO010/SMB01_CLK/SMB01_CLK18 11 GPU_THM_SMBDAT RE30 2.2K_0402_5%
GPIO017/KSO03/PVT_IO0 GPIO012/SMB02_DATA/SMB02_DATA18 GPU_THM_SMBCLK SML1_SMBDATA <8,30,34,45> TYPEC_SMBCLK
2 7 KSO11 KSO4 37 12 1 2
GPIO045/BCM_INT1#/KSO04 GPIO013/SMB02_CLK/SMB02_CLK18 TYPEC_SMBDA SML1_SMBCLK <8,30,34,45> HW_ACAVIN_NB
3 6 KSO12 KSO5 38 89 RE31 2.2K_0402_5% 2 1
GPIO046/BCM_DAT1/KSO05 GPIO130/SMB03_DATA/SMB03_DATA18 TYPEC_SMBCLK TYPEC_SMBDA <38,40> VREF_CPU CCG4_I2C_INT#
4 5 KSO13 <30> KSI[0..7] KSO6 39 91 +1.0V_PRIM 1 2 CE34 100P_0402_50V8J
GPIO047/BCM_CLK1/KSO06 GPIO131/SMB03_CLK/SMB03_CLK18 TYPEC_SMBCLK <38,40>
KSO7 50 96 RE89 1 MAD@2 0_0402_5% RE71 2.2K_0402_5% @
0.1U_0402_25V6
GPIO025/KSO07/PVT_IO2 GPIO141/SMB04_DATA/SMB04_DATA18 PWR_SELECT <53> RESET_OUT#
KSO8 46 97 1 2
<30> KSO[0..16] GPIO055/PWM2/KSO08/PVT_IO3 GPIO142/SMB04_CLK/SMB04_CLK18
1
RPE6 100K_8P4R_5% KSO9 68 RE13 1 2 10K_0402_5% +3VALW CE31 1000P_0402_50V7K
GPIO102/KSO09[CR_STRAP] FAN1_TACH +3VS
CE17
1 8 KSO8 KSO10 72 40
GPIO106/KSO10 GPIO050/TACH0 FAN1_TACH <30> HW_ACAV_IN
2 7 KSO15 KSO11 74 41 2 1
LOM_CABLE_DETECT <35>
2
GPIO110/KSO11 GPIO051/TACH1
1
3 6 KSO14 KSO12 75 CE32 100P_0402_50V8J
4 5 KSO16 KSO13 76 GPIO111/KSO12 44 RE46 SYS_PWROK 1 @ 2
GPIO112/PS2_CLK1A/KSO13 GPIO053/PWM0 KB_LED_PWM <30>
KSO14 77 45 RE68 10K_0402_5%
KSO15 86 GPIO113/PS2_DAT1A/KSO14 GPIO054/PWM1 BEEP <23> 10K_0402_1%
RESET_OUT# 1 2
Close to UE1 each pin
2 1 KSO9 KSO16 92 GPIO125/KSO15 47 RE16 10K_0402_5%
FAN1_PWM <30>
2
RE15 100K_0402_5% 93 GPIO132/KSO16 GPIO056/PWM3 34 VCREF0 +RTC_CELL
USB_EN# <30> CAP_LED# GPIO140/KSO17 GPIO030/BCM_INT0#/PWM4 AUX_EN_WOWL <32>
2 1 35 +3VALW
0.1U_0402_25V6
GPIO031/BCM_DAT0/PWM5 LANWAKE# <11> PCH_RSMRST#
1
RE17 100K_0402_5% KSI0 98 36 1 2
BAT1_LED# GPIO143/KSI0/DTR# GPIO032/BCM_CLK0/PWM6 PCIE_WAKE# PS_ID <53>
2 USB_PWR_SHR_EN_L#
1
100K_0402_5%
2 1 KSI1 99 4 RE48 RE20 10K_0402_5% 1
GPIO144/KSI1/DCD# GPIO002/PWM7 PCIE_WAKE# <11,32,35,37>
CE23
RE41
C RE18 100K_0402_5% KSI2 6 10K_0402_1% RU26 100K_0402_1% C
2 1 BAT2_LED# KSI3 7 GPIO005/SMB00_DATA/SMB00_DATA18/KSI2 1 BAT2_LED#
BAT2_LED# <29>
2
RE21 100K_0402_5% KSI4 104 GPIO006/SMB00_CLK/SMB00_CLK18/KSI3 GPIO157/LED0/TST_CLK_OUT 106 BAT1_LED#
BAT1_LED# <29>
2
KSI5 105 GPIO147/KSI4/DSR# GPIO156/LED1 70 BREATH_LED#
BREATH_LED# <29>
2
KSI6 107 GPIO150/KSI5/RI# GPIO104/LED2
KSI7 108 GPIO151/KSI6/RTS# 80 ME_FWP POWER_SW_IN# 1 2
GPIO152/KSI7/CTS# GPIO116/TFDP_DATA/UART_RX HOST_DEBUG_TX ME_FWP <12> POWER_SW#_MB <29>
81 RE43 100_0402_5%
GPIO117/TFDP_CLK/UART_TX HOST_DEBUG_TX <32>
78 1
<30> CLK_TP_SIO GPIO114/PS2_CLK0 PTP_DIS#
2.2U_0402_6.3V6M
79 90
<30> DAT_TP_SIO GPIO115/PS2_DAT0 GPIO035/SB-TSI_CLK H_PECI PECI_EC PTP_DIS# <30>
CE33
52 94 RE23 1 2 43_0402_1% +3VALW_PCH
<11> SIO_PWRBTN# GPIO026/PS2_CLK1B GPIO033/PECI_DAT/SB_TSI_DAT
<22,25> VCCDSW_ON RE91 1 GEN9@ 2 0_0402_5% 88
GPIO127/PS2_DAT1B 95 VREF_CPU 2
VREF_CPU
2
<11,17,22> SIO_SLP_S0# RE90 2 1 0_0402_5% 59
<8> ESPI_IO0 GPIO040/LAD0/ESPI_IO0 ICSP_CLK
LOKI@ 60 101 RE19
<8> ESPI_IO1 GPIO041/LAD1/ESPI_IO1 GPIO145(ICSP_CLOCK) ICSP_DAT
+3VALW 61 102 @ 1K_0402_5%
<8> ESPI_IO2 GPIO042/LAD2/ESPI_IO2 GPIO146(ICSP_DATA) ICSP_CLR
62 87
<8> ESPI_IO3 ESPI_CS# GPIO043/LAD3/ESPI_IO3 ICSP_MCLR
58
<8> ESPI_CS#
1
GPIO044/LFRAME#/ESPI_CS# NB_MUTE# EC_MUTE# SIO_SLP_SUS#
1
100K_0402_5%
56 119 RE28 1 @ 2 0_0402_5% RE88 1 DSX@ 2 0_0402_5%

<29> MASK_SATA_LED# GPIO064/LRESET# BGPO/GPIO004 SYSPWR_PRES EC_MUTE# <23> SIO_SLP_SUS# <11,58,59>
<8> ESPI_CLK 57 120 1 2 +3VLP
GPIO034/PCI_CLK/ESPI_CLK SYSPWR_PRES/GPIO003
RE25
63 121 RE29 LOKI@ 1K_0402_5%

GPIO067/CLKRUN# VCI_OUT/GPIO036 VCI_IN1 ALWON <56> ME_FWP
RE84 1 @ 2 0_0201_5% 55 126 1 2 +RTC_CELL
<8> ESPI_ALERT# GPIO063/SER_IRQ/ESPI_ALERT# VCI_IN1#/GPIO162 POWER_SW_IN# +3.3V_ALW_DSW
10 127 RE70 100K_0402_5%
<45> GPU_PWR_LEVEL
2
GPIO011/nSMI/nEMI_INT VCI_IN0#/GPIO163
1
100K_0402_5%
<25,29> SYS_LED_MASK# RE540 2 1 0_0402_5% 49 128
LID_CL_SIO# <30> TP_EN# GPIO060/KBRST VCI_OVRD_IN/GPIO164 HW_ACAV_IN <11,53,54,55>
2
@ 53
<8> ESPI_RESET# LID_CL_SIO# GPIO061/LPCPD#/ESPI_RESET# +3VALW_EC PCIE_WAKE#
RE32
66 23 1 2 RE539
<28,29> LID_CL_SIO# GPIO100/nEC_SCI GPIO160/DAC_0 PLT_RST_VGA# <44>
0.047U_0402_16V4Z
24 RE12 1K_0402_5% @ 1K_0402_5%

GPIO161/DAC_1 HW_ACAVIN_NB <53,54,55>
32 22
0.1U_0402_25V6
<38> CCG4_I2C_INT#
2
GPIO126/SHD_SCLK DAC_VREF
1
CE19
28
<11> SYS_PWROK
1
PBAT_PRES# GPIO133/SHD_IO0 CMP_VOUT0
1
@ 29 85
<53,55> PBAT_PRES# GPIO134/SHD_IO1 GPIO124/CMP_VOUT0 CMP_VIN0 CMP_VOUT0 <56>
CE20
30 20 1 @ 2
<59> PRIM_PWRGD VCIN0_PH <30>
2
31 GPIO135/SHD_IO2 GPIO020/CMP_VIN0 25 VCREF0 RE37 0_0402_5%

1
2
<11,22> RTCRST_ON PCH_RSMRST# 27 GPIO136/SHD_IO3 GPIO165/CMP_VREF0
<11> PCH_RSMRST# GPIO123/SHD_CS#[BSS_STRAP]
CE16 83 PROCHOT
67 GPIO120/CMP_VOUT1 21 RE81 1 2 0_0402_5% SYS_LED_MASK#
100P_0402_50V8J <6> BKLT_IN_EC GPIO101/SPI_CLK GPIO021/CMP_VIN1 SYS_LED_MASK# <25,29>
2 69 26 MAD@
ESPI_CLK <55> AC_DIS GPIO103/SPI_IO0 GPIO166/CMP_VREF1/UART_CLK LCD_TST <28>
71 2 @ 1
<26> USB_POWERSHARE_VBUS_EN GPIO105/SPI_IO1
RE85 2 1 0_0402_5% 42 118 RE541 100K_0402_5%
<27> FPR_SCAN# TP_WAKE_KBC# GPIO052/SPI_IO2 GPIO024/ADC7 USB_PWR_SHR_EN_L# <26>
<12,30> TP_WAKE_KBC# 33 117
GPIO062/SPI_IO3 GPIO023/ADC6/A20M PANEL_BKEN_EC <28>
3 116
<35> AUX_ON GPIO001/SPI_CS#/32KHZ_OUT GPIO022/ADC5 MODEL_ID SIO_EXT_WAKE# <9>
2
33_0402_5%
109
B GPIO153/ADC4 I_ADP B
RE67
@EMI@
13 110
<26> USB_EN# nRESET_IN/GPIO014 GPIO154/ADC3 BOARD_ID
RE42 1 @ 2 0_0402_5% RUNPWROK 48 111
VSS_VBAT
<11> ALL_SYS_PWRGD RESET_OUT# GPIO057/VCC_PWRGD GPIO155/ADC2 LCD_VCC_TEST_EN

73 113
<11> RESET_OUT# LCD_VCC_TEST_EN <28>
VR_CAP
GPIO107/nRESET_OUT GPIO122/ADC1 114 I_BATT

1
MEC_XTAL2 GPIO121/ADC0
AVSS
<11> SUSCLK_EC RE45 2 @ 1 0_0402_5% 125 115 +3VALW_EC

VSS
VSS
VSS
VSS
VSS
MEC_XTAL1 RE47 MEC_XTAL1_R XTAL2 ADC_VREF

33P_0402_50V8J
2 1 0_0402_5% 123 GEN9@ RC442

XTAL1
1
1 2
0.1U_0402_25V6
<22,25> VCCDSW_ON PCH_PRIM_EN <36,58,59>
2
CE35
@EMI@
@
124
84
51
17
64
100
EC_AGND 112
18
MEC1416-NU-D0_VTQFP128_14X14 0_0402_5%
EC_AGND 2
+3VS
CE21
1
TP44 GEN9@ DC2

1 1 2
<11,38,53,56,58,59> POK
CE22
RE67,CE35: close to UE1.57 0.1U_0402_10V7K RB751S40T1G_SOD523-2
VR_CAP 1 2
2
3 AM = 7 1
RE50
@ 2
0_0603_5% CE24 1U_0603_16V7 EC_AGND
5
UE2 = ?/
VCC YE1 &L . ;.?
4 OUT Y MEC_XTAL1 1 MEC_XTAL2
<12,53,55,60> H_PROCHOT# INA 2 PROCHOT 2
GND = ?/
2
NL17SZ06DFT2G_SC70-5 NC 32.768KHZ_9PF_X1A000141000200 EC_AGND

1 RE53 1 20ppm / 9pF 1
1
100K_0402_5% ESR <50kohm (MAX)

CE26 CE3 CE4
47P_0402_50V8J 12P_0402_50V8J 12P_0402_50V8J RE51 300_0402_5%
1
2 2 2 I_ADP 1 2
I_ADP_R <55>
1
CE25 2200P_0402_25V7K
2
EC_AGND
+3VALW
+3VALW
1
8
7
6
5
EC_AGND
+3VALW_EC RE59 RPE7
A 49.9_0402_1% 10K_0804_8P4R_5% RE54 300_0402_5% A
I_BATT
1
1
10K_0402_5%
100K_0402_5%
10K_0402_5%
10K_0402_5%
1 2
I_BATT_R <55>
@ RE56
@ RE58
JESPI1 CONN@ JDEG1 CONN@

2
1
2
3
4
RE55
RE57
1 1 1
1 2 1 2 JTAG_TDI RE60 1 @ 2 0_0402_5% ICSP_CLK
2 3 ESPI_IO0 2 3 JTAG_TMS RE61 1 @ 2 0_0402_5% ICSP_CLR CE30 2200P_0402_25V7K
2
3 4 ESPI_IO1 3 4 JTAG_CLK
EC_AGND
4 5 ESPI_IO2 4 5 JTAG_TDO RE63 1 @ 2 0_0402_5% ICSP_DAT 2

5 6 ESPI_IO3 5 6 MSCLK
6 7 ESPI_CS# 6 7 MSDATA
7 8 2 @ 1 7 8 HOST_DEBUG_TX
8 9 PLTRST# <11,22,32,34,35,37,44> 8 9
11 RE65 0_0402_5% 11
12 GND 9 10 ESPI_CLK 12 GND 9 10 EC_AGND Security Classification Compal Secret Data
GND 10 GND 10
1
Pin8 5085_TXD for EC Debug 2016/12/01 2017/12/01 Title

pin9 5048_TXD for SBIOS Issued Date Deciphered Date
JXT_FP241AH-010GAAM JXT_FP241AH-010GAAM RE62
SP010021O00 SP010021O00
debug
10K_0402_5% THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
& * 2
2
5 4 3 2 1
5 4 3 2 1
Main Func = USB3.0 Port1
+5VALW
MAD@
CU23 0.1U_0402_16V4Z
1 2 USB30_VCCA USB30_VCCA
USB30_VCCA
W=80mils UU2 JUSB1
1 12 W=80mils USB3_CTX_DRX_P1_C 9
IN OUT 1 STDA_SSTX+
Vinafix.com
USB_PN1 2 USB3_CTX_DRX_N1_C 8 VBUS
<10,26> USB_PN1 USB_PP1 DM_OUT USB_PP1_R STDA_SSTX-
10P_0201_50V8J
68P_0201_50V8J
3 1 1 3
<10,26> USB_PP1 DP_OUT SW_USB_PP1 D+
CU20 RF@
10 4
DP_IN SW_USB_PN1 USB_PN1_R GND_1
CU19 RF@
1 LOKI@ 2 1 @EMI@ 2 13 11 2
<10,26> USB_PP1 <10,26> USB_OC0# FAULT# DM_IN USB3_CRX_DTX_P1_C D-
RU21 0_0402_5% RU1 0_0402_5% 6
D
4 2 2 7 STDA_SSRX+ D
+5VALW ILIM_SEL USB3_CRX_DTX_N1_C GND_2
MAD@ 5
STDA_SSRX-
3
LU1 EMI@ 5 15 1 RU23 2 80.6K_0402_1%
SW_USB_PP1 2 1 USB_PP1_R <25> USB_POWERSHARE_VBUS_EN EN ILIM_LO 16 1 RU24 2 30K_0402_1% 10
3
ILIM_HI ESD@ GND1
MAD@ 11
6 AZC199-02SPR7G_SOT23-3 12 GND2
SW_USB_PN1 USB_PN1_R <25> USB_PWR_SHR_EN_L# CTL1 EU2602 GND3
1
3 4 7 9 13
8 CTL2 NC 14 GND4
+5VALW
1
MCM1012B900F06BP_4P CTL3 GND 17 ACON_TARAN-9R1391
GNDP
1
CONN@
RU25 TPS2544RTER_WQFN16_3X3
1 LOKI@ 2 1 @EMI@ 2 1M_0402_5%
<10,26> USB_PN1 MAD@
RU22 0_0402_5% RU2 0_0402_5% MAD@
2
CU1
USB3_CTX_DRX_P1_R USB3_CTX_DRX_P1_C USB3_CRX_DTX_P1_C Layout Note: Close JUSB1 EU2601
1 2 2 EMI@ 1 <10> USB3_CRX_DTX_P1
2 EMI@ 1 USB30_VCCA
<10> USB3_CTX_DRX_P1 RU3 0_0402_5% RU5 0_0402_5% USB3_CRX_DTX_N1_C 1 9USB3_CRX_DTX_N1_C
!"
.1U_0402_16V7K
@ 5 USB3_CRX_DTX_P1_C 8USB3_CRX_DTX_P1_C
LOKI@
2 !
LU2 @EMI@ LU3 @EMI@

2 1 2 1 USB3_CTX_DRX_N1_C 4 7USB3_CTX_DRX_N1_C
1 1 1 1 1 !
1U_0402_10V6K
1U_0402_10V6K
22U_0805_10V6M
22U_0805_10V6M
100U_1206_6.3V6M
USB3_CTX_DRX_P1_C 6USB3_CTX_DRX_P1_C
CU6
CU7
CU8
CU9
CU10
5 !
3 4 3 4
2 2 2 2 2 3
HCM1012GH900BP_4P HCM1012GH900BP_4P
8
CU2
1 2 USB3_CTX_DRX_N1_R 2 EMI@ 1 USB3_CTX_DRX_N1_C 2 EMI@ 1 USB3_CRX_DTX_N1_C L05ESDL5V0NA-4_SLP2510P8-10-9
<10> USB3_CTX_DRX_N1 <10> USB3_CRX_DTX_N1
RU4 0_0402_5% RU6 0_0402_5% ESD@
.1U_0402_16V7K
C
Maximum Output Main Func = USB2.0 Port3 + Card Reader on IO/B C
Current 2A
+5VALW USB20_VCCB 1 @EMI@ 2
USB2.0/Card Reader connector
E # 2 % G RU13 0_0402_5%
USB30_VCCC USB30_VCCA JIOB1
+5VALW
UU3 1
1 LU8 <9> SD_READ_MODE 2 1
UU1 JP13 PJP@ 5 OUT 2 1 USB_PP6_R USB_PP6_R 3 2
5
IN
OUT
1 1
1 2
2
<25,26> USB_EN#
4
IN
EN
GND
2
<10> USB_PP6
2 2 USB_PN6_R 4
5
3
4
5
2 JUMP_43X79 3 3 4 USB_PN6_R USB_PP2_R 6
1
<25,26> USB_EN#
4
EN
GND
OCB
3
USB_OC0# <10,26>
1
CU16
OCB
SY6288D20AAC_SOT23-5
USB_OC1# <10> <10> USB_PN6
MCM1012B900F06BP_4P
!4, USB_PN2_R 7
8
6
7
8
CU5 1U_0402_10V6K EMI@ 9
1U_0402_10V6K SY6288D20AAC_SOT23-5 <9> IO_CBL_DET# 10 9
LOKI@ 2 USB20_VCCB USB20_VCCB 1 @EMI@ 2 11 10
2 LOKI@ +RTC_VCC 11
RU14 0_0402_5% 12
+3VS 12
USB20_VCCB
13
1 @EMI@ 2 14 13
1 14
CU17 RU15 0_0402_5% 15
@ 5 15
10P_0201_50V8J
68P_0201_50V8J
22U_0805_10V6M 1 1 16
16
CU22 RF@
@
2
CU21 RF@
LU9 17
2 1 USB_PP2_R 18 GND
2 2 <10> USB_PP2 GND
3 4 USB_PN2_R ACES_51524-0160N-001
<10> USB_PN2
SP01001C600
MCM1012B900F06BP_4P CONN@
EMI@
1 @EMI@ 2
RU16 0_0402_5%
Main Func = USB3.0 Port2

% G ;
B B
USB30_VCCC
1 @EMI@ 2 JUSB2
RU7 0_0402_5% EU2603 USB3_CTX_DRX_P3_C 9
USB3_CRX_DTX_N3_C 1 9USB3_CRX_DTX_N3_C 1 STDA_SSTX+
!"
USB3_CTX_DRX_N3_C 8 VBUS
LU4 LOKI@EMI@ USB3_CRX_DTX_P3_C 2 ! 8USB3_CRX_DTX_P3_C USB_PP3_R 3 STDA_SSTX- @ 5
2 1 USB_PP3_R 4 D+
<10> USB_PP3 USB3_CTX_DRX_N3_C GND_1
4 ! 7USB3_CTX_DRX_N3_C USB_PN3_R 2
USB3_CRX_DTX_P3_C 6 D-
3 4 USB_PN3_R USB3_CTX_DRX_P3_C 5 6USB3_CTX_DRX_P3_C 7 STDA_SSRX+
!
<10> USB_PN3 USB3_CRX_DTX_N3_C GND_2
5
MCM1012B900F06BP_4P 3 STDA_SSRX-
10
GND1
3
8 11
1 @EMI@ 2 12 GND2
3
LOKI@ESD@ GND3
RU8 0_0402_5% L05ESDL5V0NA-4_SLP2510P8-10-9 13
LOKI@ESD@ AZC199-02SPR7G_SOT23-3 GND4
EU2604
1
ACON_TARAN-9R1391
CONN@
1
CU3
1 2 USB3_CTX_DRX_P3_R 2 1 USB3_CTX_DRX_P3_C 2 1 USB3_CRX_DTX_P3_C
<10> USB3_CTX_DRX_P3 <10> USB3_CRX_DTX_P3 Layout Note: Close JUSB2
RU9 LOKI@EMI@ 0_0402_5% RU11 LOKI@EMI@ 0_0402_5% USB30_VCCC
.1U_0402_16V7K
LOKI@
LU5 @EMI@ LU6 @EMI@ @ 5
2 1 2 1
@
1 1 1 1 1
1U_0402_10V6K
1U_0402_10V6K
22U_0805_10V6M
22U_0805_10V6M
100U_1206_6.3V6M
CU11
CU12
CU13
CU14
CU15
3 4 3 4
A A
HCM1012GH900BP_4P HCM1012GH900BP_4P 2 2 2 2 2
CU4
LOKI@
LOKI@
LOKI@
LOKI@
1 2 USB3_CTX_DRX_N3_R 2 1 USB3_CTX_DRX_N3_C 2 1 USB3_CRX_DTX_N3_C
<10> USB3_CTX_DRX_N3 <10> USB3_CRX_DTX_N3
RU10 LOKI@EMI@ 0_0402_5% RU12 LOKI@EMI@ 0_0402_5%
.1U_0402_16V7K
LOKI@

/% - ; ? )6
5 4 3 2 1
5 4 3 2 1
Main Func = Finger Printer
+5VS +3VS
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1
R4 R7
0_0603_5% 0_0603_5%
FP_5V@ FP_3V@
D CONN@ D
CONN@ +3VS
2
ACES_51522-00601-001
FP_VCC SP01001AE00
8 1 2
7 G2 C37 0.1U_0402_16V7K ACES_51522-00801-001
FP_VCC 6 G1 8
FP_VCC_R 5 6 FP_VCC 2 FP@ 1 FP_VCC_R 7 8 10 FPR_SCAN# 2 1
4 5 R86 0_0402_5% 6 7 G2 9 R72 100K_0402_5%
<10,27> USB_PN9 4 <10,27> USB_PN9 6 G1
<10,27> USB_PP9 3 <10,27> USB_PP9 5
FP_GND 2 3 FP_GND 4 5
1 2 3 4
1 2 3
R87
<25> FPR_SCAN# 2
2
JFP 1
EU2701 1
2
JFP1
FP@
AZC199-02SPR7G_SOT23-3
For Loki-L ESD@ EU4012
2
1
AZC199-02SPR7G_SOT23-3
For Loki
1
ESD@
0_0402_5%
1
1
FP_VCC
68P_0201_50V8J
10P_0201_50V8J
1 1
C46
C50
2 2
RF@
RF@
C C
B B
A A

5 4 3 2 1
5 4 3 2 1
Main Func = LCD INVERTER POWER Main Func = CAM

+19VB +DCBAT_LCD
+LCDVDD_LCD +LCDVDD
JEDP1 CONN@ F1 @ 5(
1 1 2 1 2
1 2 +DCBAT_LCD
41 R3 0_0805_5%
42 G1 2 3 1.5A_24V_SMD1812P150TF-24
G2 3 4 1 1
C4 C5 EE note: Never change R16 to short pad after MP
4 5 +LCDVDD_LCD
@
EE note: Never change R3 to short pad after MP
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5 6
0.1U_0603_50V7K
1000P_0402_50V7K
6 7
Trace width = 60mil
RF@ 2 2 +3VS +3VS_CAM
7 8 C12 +3VS_CAM
8 9 1 1
1
C2 C3 +3VS
9 10 LCD_TST_C
82P_0402_50V8J
10 11 DBC_PANEL_EN_R
0.1U_0402_16V7K
1U_0402_10V6K
1 2
2
D 11 12 EDP_HPD 2 2 D
68P_0201_50V8J
R16 0_0603_5% 1
12 13 EDP_HPD <6>
C49
13 14 1
1
LCD_CBL_DET#
33P_0402_50V8J
C14 @
R5
14 15 EDP_AUX LCD_CBL_DET# <9>
10K_0402_5% C15
15 16 EDP_AUX# 2
RF@
4.7U_0402_6.3V6M
2
16 17 +DCBAT_LCD 2
2
17 18 EDP_TX0#
18 19 EDP_TX0
19 20 DBC_PANEL_EN_R 1 2
20 21 EDP_TX1# DBC_PANEL_EN <9>
68P_0201_50V8J
R6 0_0402_5% 1
21 22 EDP_TX1
C47
22 23
23 24
24 25 2
RF@
25 26 IR_CAM_DETECT# L6 MAD@RF@
26 27 LCD_BRIGHTNESS_R IR_CAM_DETECT# <9> LCD_BRIGHTNESS_R 1 2 LCD_BRIGHTNESS
27 28 BLON_OUT_C IR_GND BLM15BD221SN1D_2P
28 29 +3VS_CAM
29 30 DMIC_DATA_EDP +3VS_CAM
30 31 DMIC_CLK_EDP DMIC_DATA_EDP <23>
31 32 DMIC_CLK_EDP <23>
1 LOKI@ 2
32 33 USB_CAMERA_EDP# R80 0_0402_5%
33 34 USB_CAMERA_EDP
34 35 IR_GND 2 1 GND
35 36 USB_PN8_TPNL R85 0_0603_5% 1 @EMI@ 2
36 37 USB_PP8_TPNL R17 0_0402_5%
37 38
38 39 TP_EN IR_GND
39 40 L3 EMI@
40 +TPAN_VDD USB_CAMERA_EDP 2 1 USB_PP5 <10>
RP1
ACES_51540-04001-P01
SP010029F00 1 8 BKLT_CTRL
2 7 BLON_OUT_C USB_CAMERA_EDP# 3 4
EDP_HPD USB_PN5 <10>
3 6
4 5 MCM1012B900F06BP_4P
1 @ 2
100K_8P4R_5% R9 0_0402_5% 1 @EMI@ 2
R18 0_0402_5%
C D3 C
RP2 2 eDP_BKLT_CTRL
BLON_OUT_C 1 8
LCD_BRIGHTNESS 2 7 BKLT_CTRL PANEL_BKEN_EC <25> 1
LCD_TST_C 3 6 LCD_TST
4 5 3 LCD_TST
LCD_TST <25>
BAT54C-7-F_SOT23-3
100_8P4R_5% EC (BIST MODE)
Main Func = TS
D5
C6 1 2 0.1U_0402_16V7K EDP_TX0# 1 2
<6> EDP_TX0_DN EDP_TX0 <25,29> LID_CL_SIO#
<6> EDP_TX0_DP C7 1 2 0.1U_0402_16V7K
RB551V-30_SOD323-2
+3VS +LCDVDD
C8 1 2 0.1U_0402_16V7K EDP_TX1# R19
<6> EDP_TX1_DN EDP_TX1 TP_EN
C9 1 2 0.1U_0402_16V7K C17 1 2
<6> EDP_TX1_DP
1U_0402_6.3V6K U1 + 8 33_0402_5%
TOUCH_SCREEN_PD# <12>
2 1 5 1 5 1
IN OUT +3VS
@
C16
C10 1 2 0.1U_0402_16V7K EDP_AUX# 2 10P_0402_50V8J
<6> EDP_AUX_DN EDP_AUX GND 2
C11 1 2 0.1U_0402_16V7K R57
<6> EDP_AUX_DP
4 3 2 1
EN OC 10K_0402_5%
B Brightness SY6288C20AAC_SOT23-5
B
R8 1 @ 2 0_0402_5% eDP_BKLT_CTRL D4
<6> L_BKLT_CTRL 2
<6> EDP_VDD_EN
1 LCDVDD_EN
3
<25> LCD_VCC_TEST_EN
High Active
1
BAT54C-7-F_SOT23-3 R10 USB_PP8_TPNL 1 EMI@ 2

EC (BIST MODE) 100K_0402_5% R20 0_0402_5%
USB_PP8 <10>
L4 @EMI@
2
2 1
3 4
MCM1012B900F06BP_4P
USB_PN8_TPNL 1 EMI@ 2 USB_PN8 <10>

R21 0_0402_5%
USB_PN8_TPNL
USB_PP8_TPNL
+3VS +5VS
2
+TPAN_VDD_F +TPAN_VDD +TPAN_VDD_F +TPAN_VDD +TPAN_VDD
1
DA6 @ESD@
2
R11 R12 AZC199-02SPR7G_SOT23-3
68P_0201_50V8J
0_0603_5% 0_0603_5% 1
1
C48
@ U3
@ 5 5 1 @ 5
2
1
A
IN OUT A
2
RF@
@ 2
1 2 GND
F2 1.1A_24V_SMD1812P110TF-24 4 3 1 2
<9> 3.3V_TS_EN EN OC +TPAN_VDD_F
1 R30 @ 10K_0402_5%
C31 SY6288C20AAC_SOT23-5
1 2 @ 1U_0402_10V6K @
R13 0_0603_5%
2
EE note: Never change R12/R13 to short pad after MP

) )& )0
5 4 3 2 1
5 4 3 2 1
Main Func = Power BTN Main Func = PWR LED Low actived from KBC GPIO
JPWR1
1
POWER_SW#_MB 2 1
TPS9 LID_CLOSE# 2
3
4 3
+3VALW
R22 1 2 100_0402_5%
Vinafix.com LID_CLOSE#
+3VALW
SP010021Y10
CONN@
JXT_FP226H-006S1BM
5
6
4
GND1
<25,28> LID_CL_SIO# MASK_BASE_LEDS# 1 GND2
D <25> POWER_SW#_MB +5VALW WHITE_LED_PWR 2 1 D
3 2 JXT_FP226H-004S1AM
3
1
POWER_SW#_MB 4 SP01002BJ00
1 @ESD@ TPS8 4
2
LID_CLOSE#
1000P_0402_50V7K
5 7
TST71-N-220-T170-S017_2P
TST71-N-220-T170-S017_2P
R53 CONN@
5 G1 8
EC2901
100K_0402_5% +3VALW 6
MAD@ 6 G2
For Loki
3
2 JPWR2
SW1
SW2
ED2901
2
G
@ESD@
R2
@ @ 3 1 PWR_LED_R# 2 Q20
<25> BREATH_LED#
DDTA144VCA-7-F_SOT23-3 For Loki-L
D
2
2
MAD@
R1
1
Q21
LOW actived from KBC GPIO LN2306LT1G_SOT23-3 For EMI Reserved
1
MAD@ @ESD@
LID_CLOSE# EC2902 1 2 .1U_0402_16V7K
WHITE_LED_PWR
Main Func = Battery LED BJT

R1: 47 K +5VALW
C
Low actived from KBC GPIO R2: 10 K C
MASK_BASE_LEDS#
LED1
+1.8V_PRIM 1 2 1 2
3
R23 @ 10K_0402_5% RC224 10K_0402_5% WHITE_LED_BAT 2 1 2 1
2
R69 200_0402_5% W
R2
1 6 CHG_AMBER_LED_R# 2 Q18 AMBER_LED_BAT 2 1 4 3
<25> BAT1_LED#
DDTA144VCA-7-F_SOT23-3 R68 200_0402_5% Y
<25> MASK_SATA_LED#
Q17A
R1
DMN66D0LDW-7_SOT363-6 LTW-295DSKS-5A_YEL-WHITE~D
2
G
1
<10,37> SATA_LED# 1 2 SATA_LED#_R 3 1 BATT_WHITE_LED_R#
3
R81 @ 0_0402_5%
S
5
AMBER_LED_BAT
R2 C62
Q22 4 3 BATT_WHITE_LED_R# 2 Q19 WHITE_LED_BAT 1 2
LN2306LT1G_SOT23-3 <25> BAT2_LED#
DDTA144VCA-7-F_SOT23-3
Q17B
R1
DMN66D0LDW-7_SOT363-6 1U_0402_10V6K
1
WHITE_LED_BAT
B B
Main Func = Unobtrusive Mode

+3VS
+3VALW
1
R83
+3VALW 100K_0402_5%
1
+3VS
R70
2
1 2 100K_0402_5%
1
C57 0.1U_0402_25V6K SATA_LED#_R
@ R82
2
5
100K_0402_5%
3
1
P
<25> SYS_LED_MASK# IN1 MASK_BASE_LEDS#

4 Q25B
2
LID_CL_SIO# 2 O
IN2 DMN66D0LDW-7_SOT363-6
G
5
U4
3
SN74AHC1G08DCKR_SC70-5
4
6
@
Q25A
SATA_LED# 2
R71 0_0402_5% <10,37> SSD_DAS#

1
1 2
A MAD@ A
VIH 2.1V
VIL 0.9V Issued Date 2016/12/01 Deciphered Date 2017/12/01 Title
) # "
07/28 change note: "SYS_LED_MASK#" from GPIO063 change to GPIO021 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
5 4 3 2 1
5 4 3 2 1
Main Func = KB Main Func = TPAD +3VALW +3VS +TP_VDD
<25> KSI[0..7]
! " # $ % & ' ( #) NTP_WAKE@
1
+TP_VDD +3VS R36 1 2
KB Backlight Power Consumption: 285mA max. TP_WAKE@ 0_0603_5%
R35
<25> KSO[0..16] +5VS F3 KBBL@ +5V_KB_BL 0_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
2
1
1
2 1
R31
R32
R33
R34
JKB1 CONN@ 1
1 0.5A_13.2V_MF-NSMF050-2 KBBL@ +TP_VDD Discharge
<9> KB_DET# KSI7 2 1 C34
KSI6 3 2 .1U_0402_16V7K Q12 +TP_VDD
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2
KSI4 4 3 2 NTK3139PT1G_SOT723-3
KSI2 5 4 DAT_TP_SIO
6 5 <25> DAT_TP_SIO 3 1 1 2
D
KSI5
KSI1 7 6
7
KBBL@ JKBBL1 * <25> CLK_TP_SIO
CLK_TP_SIO
1
KSI3 8 R26 1 TP_WAKE@ TP_WAKE@ R37
KSI0 9 8 1 2 KB_LED_DET_C 2 1 I2C0_SDA_TCH_PAD C18 100_0603_5%
G
D <9> I2C0_SDA_TCH_PAD D
2
9 2
1
KSO5 10 <12> KB_LED_BL_DET 51K_0402_5% 3 5 .1U_0402_16V7K
+*,
1
KSO4 11 10 KB_BL_CTRL# 4 3 G1 6 I2C0_SCL_TCH_PAD 2 D Q13
KSO7 12 11 4 G2 <9> I2C0_SCL_TCH_PAD 1 2 2
KBBL@ <25> TP_EN# 2N7002K_SOT23-3
12
@ESD@ C26
@ESD@ C27
KSO6 13 R27 ACES_51575-00401-001 G
13
10P_0402_50V8J
10P_0402_50V8J
KSO8 14 100K_0402_5% CONN@ R38 S
KSO3 15 14 20K_0402_1%
3
1
1
KSO1 16 15
KSO2 17 16
KSO0 18 17
2
KSO12 19 18
19
1
20 D +TP_VDD +TP_VDD
KSO16 Q8
KSO15 21 20 2 KBBL@
KSO13 22 21 <25> KB_LED_PWM G
1
KSO14 23 22 S
3
KSO9 24 23 LN2306LT1G_SOT23-3 R39
KSO11 25 24
25
" 2 10K_0402_5%
KSO10 26
26
2
CAP_LED 27
2
28 27 +TP_VDD
29 28 31 1 3 INT_TP#
30 29GND31 32 <12,25> TP_WAKE_KBC#
S
30GND32
HEFEN_AFB02-S30F1A-HF Q9 LN2306LT1G_SOT23-3
For EMI Reserved +TP_VDD
68P_0201_50V8J
SP021707030 1
C52
@ESD@
KB_BL_CTRL# EC3001 1 2 .1U_0402_16V7K
+3VS 2
RF@
@ESD@
1
+5V_KB_BL EC3002 1 2 .1U_0402_16V7K
R46 +TP_VDD
2.2K_0402_5%
2 1 CONN@
2
0.1U_0402_16V7K C19 SP01001A900
2
Q10B ACES_51524-0080N-001
G
I2C0_SCL_TCH_PAD 1 6 I2C_SCL_TP +TP_VDD 4.7K_0402_5% 2 1 R40
8
D
DMN66D0LDW-7_SOT363-6 NTP_WAKE@
8
1
1 2 I2C_SDA_TP 7 10
R47 R41 100K_0402_5% I2C_SCL_TP 6 7 G2 9
+3VS 2.2K_0402_5% 5 6 G1
5
5
C Q10A D6 INT_TP# 4 C
+5V_KB_BL PTP_DIS# 1 2 TP_LOCK# 3 4
G
<25> PTP_DIS#
2
I2C0_SDA_TCH_PAD 4 3 I2C_SDA_TP DAT_TP_SIO 2 3
+5VS CLK_TP_SIO 2
D
DMN66D0LDW-7_SOT363-6 RB551V-30_SOD323-2 1
1
1
R24 JTP1
68P_0201_50V8J
100K_0402_5% 1
C51
3
LOW actived from KBC GPIO

2
2
G
RF@
R2
3 1 CAP_LED_R# 2 Q7
<25> CAP_LED# DDTA144VCA-7-F_SOT23-3
S
R1
Q6
LN2306LT1G_SOT23-3
1
R25
CAP_LED_Q 1 2 CAP_LED
1K_0402_5%
+3VS +5VS
Main Func = Thermal 1
22U_0805_10V6M
+3VS
10K_0402_5%
C30
2
2
R50
+3VS
1
1
R48 JFAN1
2.2K_0402_5% 1
2 1
<25> FAN1_PWM
2
3 2
<25> FAN1_TACH
2
Q11B 4 3
G
6 1 THM_SML1_DATA 5 4
B <8,25,34,45> SML1_SMBDATA "FAN1_FB" PU 10k on EC side G1 B
S
DMN66D0LDW-7_SOT363-6 6
G2
1
R49 ACES_50224-00401-001
2.2K_0402_5% CONN@
5
+3VS Q11A SP02000GC10
2
3 4 THM_SML1_CLK
<8,25,34,45> SML1_SMBCLK
S
1
C21
0.1U_0402_16V7K
2
NCT7718_DXP Main Func = OTP

Q14 U2
1 8 THM_SML1_CLK
1 1
1
C @ VDD SCL
LMBT3904LT1G_SOT23-3
2 C22 C23 2 7 THM_SML1_DATA

B 470P_0603_50V8J 2200P_0402_50V7K D+ SDA Close to KBC
E 2 2 3 6 ALERT#
Close to Thermal sensor VD_IN1 for system thermal sensor
3
NCT7718_DXN D- ALERT#
T_CRIT# 4 5
T_CRIT# GND +3VLP +3VALW
DIMM CPU
NCT7718W_MSOP8
1
@
Layout Note: R42 R43
Layout Note: C23 close U2 24.9K_0402_1% 7.15K_0402_1%
DXN and DXP routing width and spacing is 10 mil / 10 mil.
2
VCIN0_PH <25>
1
1 1
A
RH1 @ A
100K_0402_1%_B25/50 4250K C32 C33
0.1U_0402_16V7K 100P_0402_50V8J
2 2
2
VD_IN1_C R45 1 2 0_0402_5%
+3VS
R28 1 2 18.7K_0402_1% ALERT#

1 2 2K_0402_1% T_CRIT#
R29 Issued Date 2016/12/01 Deciphered Date 2017/12/01 Title
3 @' )0 " > )0> ) A
5 4 3 2 1
Main Func = HDD&FFS JHDD
24
23 G4
22 G3
21 G2 JHDD1 @
20 G1 1
Layout Note: SATA3_CTX_C_HDDRX_P0 20 SATA3_CTX_C_HDDRX_P0 1
CS1 1 2 0.01U_0402_50V7K 19 2
Place near JHDD1 SOC TX <10> SATA3_CTX_HDDRX_P0
<10> SATA3_CTX_HDDRX_N0 CS2 1 2 0.01U_0402_50V7K SATA3_CTX_C_HDDRX_N0 18
17
19
18
SATA3_CTX_C_HDDRX_N0 3
4
2
3
3 3
EU3101 @ESD@ CS3 1 2 0.01U_0402_50V7K SATA3_CRX_C_HDDTX_N0 16 17 SATA3_CRX_C_HDDTX_N0 5 4
SATA3_CTX_C_HDDRX_P0 1 !" 9 SATA3_CTX_C_HDDRX_P0 SOC RX
Vinafix.com <10> SATA3_CRX_HDDTX_N0
<10> SATA3_CRX_HDDTX_P0
CS4 1 2 0.01U_0402_50V7K SATA3_CRX_C_HDDTX_P0 15
14
16
15
SATA3_CRX_C_HDDTX_P0 6
7
5
6
SATA3_CTX_C_HDDRX_N0 2 8 SATA3_CTX_C_HDDRX_N0 HDD_DEVSLP_R 13 14 HDD_DEVSLP_R 8 7
!
FFS_INT2_Q 12 13 FFS_INT2_Q 9 8 @
SATA3_CRX_C_HDDTX_N0 4 7 SATA3_CRX_C_HDDTX_N0 11 12 10 9
!
HDD_DEVSLP_R +5V_HDD 11 +5V_HDD 10
<10> HDD_DEVSLP RS1 2 1 0_0402_5% 10 11
SATA3_CRX_C_HDDTX_P0 5 6 SATA3_CRX_C_HDDTX_P0 9 10 12 11
!
RS7 8 9 12
3 10K_0402_5% 7 8 13
+3VS 2 1 6 7 14 GND ! !
8 MAD@ 5 6 GND
1 MAD@ 2 4 5 ACES_51625-01201-001
L05ESDL5V0NA-4_SLP2510P8-10-9 <8> HDD_DET# RS6 0_0402_5% 3 4 CONN@ @
+5VS +5V_HDD 2 3
E 1 2
( ; 1 0 %. - '
ACES_50406-02071-001
JP5 PJP@ +5V_HDD CONN@
@ 5 1 2 @ 5 '
1 2
1000P_0402_50V7K
0 %. -&%
0.1U_0402_25V6K
10U_0805_10V6K
JUMP_43X79
+5V_HDD '
68P_0201_50V8J
1 1 1 1
CS32 RF@
+3VS
CS5 CS6 CS7
' B 3
1
2 2 2 2 +3VS RS4 FFS@
100K_0402_5%
@
0.1U_0402_25V6K
10U_0805_10V6K
1
CS29 FFS@
CS30
1 1 /E 7/
2
US1 FFS@ FFS@ RS3 FFS_INT2_Q
LNG2DM 100K_0402_5% 70 E 0 2
3
@
2 2 10 5 +5V_HDD QS1B FFS@
2
9 VDD_IO RES +5VALW
VDD DMN66D0LDW-7_SOT363-6
12 5
3 INT 1 11 FFS_INT2 FFS_INT1 <8>
4 SDO/SA0 INT 2 FFS_INT2 <9> US2
<8,20,21,34> PCH_SMBDATA @ 5
4
SDA/SDI/SDO
6
1 6 1
<8,20,21,34> PCH_SMBCLK SCL/SPC GND 7 @ 5 5 OUT QS1A FFS@
2 GND 8 IN 2
CS GND GND DMN66D0LDW-7_SOT363-6
4 FFS_INT2 2
<8> HDD_EN_PCH EN 3 1 @ 2
OCB +5VS
LNG2DMTR_LGA12_2X2 1 RS5 10K_0402_5%
1
CS8 SY6288D20AAC_SOT23-5
1U_0402_10V6K @
@
2
Main Func = ODD
@
3 3
@
JODD1
+5VS +5VS_ODD 1 2
E $ SATA_CTX_C_ODDRX_P1 3 1 2 4 SATA_CTX_C_ODDRX_P1 CS12 1ODD@2 0.01U_0402_50V7K
( ; SATA_CTX_C_ODDRX_N1 5
7
3
5
4
6
6
8
SATA_CTX_C_ODDRX_N1 CS11 1ODD@2 0.01U_0402_50V7K
SATA_CTX_ODDRX_P1 <10>
SATA_CTX_ODDRX_N1 <10> SOC TX ! !
JP6 PJP@ SATA_CRX_C_ODDTX_N1 9 7 8 10 SATA_CRX_C_ODDTX_N1 CS10 1ODD@2 0.01U_0402_50V7K
$ 5 1 2 $ 5 SATA_CRX_C_ODDTX_P1 11 9 10 12 SATA_CRX_C_ODDTX_P1 CS9 1ODD@2 0.01U_0402_50V7K
SATA_CRX_ODDTX_N1 <10>
SOC RX
1 2 11 12 SATA_CRX_ODDTX_P1 <10> @
1000P_0402_50V7K
0.1U_0402_25V6K
13 14
SATA_ODD_PRSNT# 13 14 SATA_ODD_PRSNT#
10U_0805_10V6K
JUMP_43X79 15 16
17 15 16 18 SATA_ODD_PRSNT# <9>
1 1 1 +5VS_ODD
19 17 18 20
+5VS_ODD &
CS13 CS14 CS15 21 19 20 22 1 ODD@ 2
SATA_ODD_DA# 21 22 SATA_ODD_DA# +3VS
ODD@ ODD@ ODD@ 23 24 TP46 RC194 10K_0402_5%
2 2 2 23 24 ' 3 B
25 26
GNDGND
'
ACES_50673-0120N-P01
SP01002HK00
CONN@
0 0 /,0 , 3
@
@ !
1 ) %)6
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
5 4 3 2 1
Main Func = WLAN A Key CONN

+3VALW +3.3V_WLAN
Vinafix.com
UW1
+3VS +3.3V_WLAN 5 1 +3VALW
IN OUT
2
GND
D 4 3 2 1 D
1.1A <25> AUX_EN_WOWL EN OC
RW3 2 LOKI@ 1 0_0805_5% RF@ RW12 MAD@ 10K_0402_5%
1 1 1 1 1 1 1 SY6288C20AAC_SOT23-5
2
CW3
.1U_0402_16V7K
CW4
.1U_0402_16V7K
CW5
10U_0603_6.3V6M
CW6
10U_0603_6.3V6M
CW7
.1U_0402_16V7K
CW8
.1U_0402_16V7K
CW9
10P_0402_50V8J
@ @ High Active RW11
100K_0402_5%
MAD@
2 2 2 2 2 2 2 MAD@
1
JWLAN1 CONN@
77 76
MTG77 MTG76
C
+3.3V_WLAN C
75
74 GND 73
72 3.3VAUX RESERVED 71
70 3.3VAUX RESERVED 69
68 RESERVED GND 67
66 RESERVED RSRVD/PERN1 65
64 RESERVED RSRVD/PERP1 63
RW13 1 LOKI@ 2 0_0402_5% 62 RESERVED GND 61
60 ALERT RSRVD/PETN1 59
MAD@ 58 I2C_CLK RSRVD/PETP1 57
DW1 1 2 RB751S40T1G_SOD523-2 56 I2C_DATA GND 55 RW15 1 MAD@ 2 0_0402_5%
<6> WIFI_RF_EN W_DISABLE1# PEWAKE0# CLK_PCIE_WLAN_REQ#_R PCIE_WAKE# <11,25,35,37>
<9> BLUETOOTH_EN DW2 1 2 RB751S40T1G_SOD523-2 54 53 RW9 2 @ 1 0_0402_5%
52 W_DISABLE2# CLKEQ0# 51 CLK_PCIE_WLAN_REQ# <11>
MAD@
1 2 <11,22,25,34,35,37,44> PLTRST# 50 PERST0# GND 49
<11> SUSCLK_WLAN SUSCLK REFCLKN0 CLK_PCIE_WLAN_N1 <11>
RW14 LOKI@ 0_0402_5% 48 47 CLK_PCIE_WLAN_P1 <11>
46 COEX1 REFCLKP0 45
44 COEX2 GND 43
42 COEX3 PERN0 41 PCIE_CRX_WLANTX_N6 <10>
40 RESERVED PERP0 39 PCIE_CRX_WLANTX_P6 <10>
TX_P80DATA 38 RESERVED GND 37 PCIE_CTX_C_WLANRX_N6 2 1 CW1 .1U_0402_16V7K
RESERVED PETN0 PCIE_CTX_C_WLANRX_P6 PCIE_CTX_WLANRX_N6 <10>
36 35 2 1 CW2 .1U_0402_16V7K
UART_RTS PETP0 PCIE_CTX_WLANRX_P6 <10>
34 33
UART_P80 32 UART_CTS GND 31
30 UART_TX SDIO_RESET# 29
B B
28 UART_RX SDIO_WAKE# 27
26 UART_WAKE# SDO_DAT3 25
Reserved for NGFF Debug Card 24
22
GND
LED2#
SDO_DAT2
SDO_DAT1
23
21
20 PCM_OUT SDO_DAT0 19
+3VALW +3.3V_WLAN 18 PCM_IN SDIO_CMD 17
16 PCM_SYNC SIDO_CLK
PCM_CLK
1 @ 2
RW5 0_0805_5% +3.3V_WLAN 7
6 GND 5 USB_PN7
TX_P80DATA LED1# USB_D- USB_PP7 USB_PN7 <10>
1 2 4 3
<25> HOST_DEBUG_TX 3.3VAUX USB_D+ USB_PP7 <10>
RW6 @ 0_0402_5% 2 1
3.3VAUX GND
LCN_DAN05-67306-0100
SP070019F00
1 @ 2 UART_P80
RW10 0_0402_5%
A A

A. =< A 6AA
5 4 3 2 1
5 4 3 2 1
Main Func = HDMI HDMI_CLK_R

RI1 EMI@
HDMI_CLK_R_C HDMI_DATA0#_R
RI4 EMI@
HDMI_DATA0#_R_C
1 2 1 2
5.6_0402_1% 5.6_0402_1%
Vinafix.com LI1 @EMI@ LI2 @EMI@
1
CI1 1 2 0.1U_0402_10V7K HDMI_CLK#_R 3 4 2 1
<6> HDMI_CLK# CI2 1 2 0.1U_0402_10V7K HDMI_CLK_R RI3 EMI@
<6> HDMI_CLK RI6 EMI@
150_0402_5%
CI3 1 2 0.1U_0402_10V7K HDMI_DATA0#_R 2 1 3 4 150_0402_5%
<6> HDMI_DATA0# CI4 1 2 0.1U_0402_10V7K HDMI_DATA0_R
D D
2
<6> HDMI_DATA0 HCM1012GH900BP_4P HCM1012GH900BP_4P
CI5 1 2 0.1U_0402_10V7K HDMI_DATA1#_R

<6> HDMI_DATA1# CI6 1 2 0.1U_0402_10V7K HDMI_DATA1_R RI2 EMI@ RI5 EMI@
<6> HDMI_DATA1 HDMI_CLK#_R 1 2 HDMI_CLK#_R_C HDMI_DATA0_R 1 2 HDMI_DATA0_R_C
CI7 1 2 0.1U_0402_10V7K HDMI_DATA2#_R
<6> HDMI_DATA2# CI8 1 2 0.1U_0402_10V7K HDMI_DATA2_R 5.6_0402_1% 5.6_0402_1%
<6> HDMI_DATA2
RI7 EMI@ RI10 EMI@

HDMI_DATA2_R 1 2 HDMI_DATA2_R_C HDMI_DATA1_R 1 2 HDMI_DATA1_R_C
8
7
6
5
8
7
6
5
RPI1 RPI2 5.6_0402_1% 5.6_0402_1%
470_8P4R_5% 470_8P4R_5%
LI3 @EMI@ LI4 @EMI@

1
2
3
4
1
2
3
4
2
3 4 3 4
HDMI_PLL_GND RI9 EMI@ RI12 EMI@
150_0402_5% 150_0402_5%
2 1 2 1
1
+5VS HCM1012GH900BP_4P HCM1012GH900BP_4P
1
D QI1
C 2 2N7002K_SOT23-3 C
G
S RI8 EMI@ RI11 EMI@
HDMI_DATA2#_R 1 2 HDMI_DATA2#_R_C HDMI_DATA1#_R 1 2 HDMI_DATA1#_R_C
3
5.6_0402_1% 5.6_0402_1%
+5VS +5V_HDMI
W=40mils
2 1
FI1 1
1.5A_6V_1206L150PR~D
CI9
.1U_0402_16V7K
2
JHDMI1 CONN@
19
18 HP_DET
17 +5V ZZZ 45@
B DDC/CEC_GND B
DDC_DATA_HDMI 16
DDC_CLK_HDMI 15 SDA
SCL RO0000002HM
14
13 Reserved
HDMI_CLK#_R_C 12 CEC
+3VS 11 CK-
CK_shield ROYALTY HDMI W/LOGO
HDMI_CLK_R_C 10
HDMI_DATA0#_R_C 9 CK+
8 D0-
+5VS HDMI_DATA0_R_C 7 D0_shield
D0+
1
HDMI_DATA1#_R_C
1M_0402_5%
6
5 D1-
D1_shield
1
HDMI_DATA1_R_C
RI15
4 20
HDMI_DATA2#_R_C 3 D1+ GND 21
2 D2- GND 22
2
D2_shield GND
2
HDMI_DATA2_R_C
G
DI1 1 23
BAW56W_SOT323-3 D2+ GND
3 1 HDMI_HPD_B CONCR_099AKAC19NBLCNF
<6> CPU_DP1_HPD
3
D
DC021702131
2
1
+3VS
20K_0402_5%
RI13 RI14 QI3
RI16
2.2K_0402_5% 2.2K_0402_5% 2N7002KW_SOT323-3
2
2
G
1 6 DDC_CLK_HDMI
A <6> CPU_DP1_CTRL_CLK A
S
QI2B
5
G
4 3 DDC_DATA_HDMI
<6> CPU_DP1_CTRL_DATA
S
QI2A
DMN66D0LDW-7_SOT363-6 Security Classification Compal Secret Data
1 & %> ! )
5 4 3 2 1
5 4 3 2 1
Main Func = WWAN/B & VGA/B
Vinafix.com
JVGA
D
1 D
2 1
<39> VGA_DP2_P0 2
<39> VGA_DP2_N0 3
4 3
5 4
<39> VGA_DP2_P1 5
<39> VGA_DP2_N1 6
7 6
<9> VGA_CBL_DET# 8 7
<39> VGA_DP_AUXP 8
9
<39> VGA_DP_AUXN 9
10
11 10
<8,20,21,31> PCH_SMBDATA 11
12
<8,20,21,31> PCH_SMBCLK 12
13
<39> VGA_DP_HPD 13
+3VS 14
15 14
16 15
+5VS 16
17
18 GND17
GND18
ACES_51625-01601-001
CONN@
C C
JWWAN
1
2 1
3 2
4 3
5 4
TX N <10> USB3_CTX_DRX_N2
6 5
TX P <10> USB3_CTX_DRX_P2
7 6
8 7
RX N <10> USB3_CRX_DTX_N2 9 8
RX P <10> USB3_CRX_DTX_P2 10 9
11 10
CLOSE TO JWWAN <10> USB_PP10
<10> USB_PN10
12 11
13 12
14 13
+3VALW <8,25,30,45> SML1_SMBCLK 14
15
+3VS +3VALW <8,25,30,45> SML1_SMBDATA 15
16
<11,22,25,32,35,37,44> PLTRST# 16
+3VS 17
18 17
+3VALW 18
B
19 B
20 19
20
68P_0201_50V8J
68P_0201_50V8J
1 1 1 1 1 21
21
C39 68P_0201_50V8J
RF@
C40
RF@
C41
RF@
C42
C43
22
23 22
24 23
2 2 2 2 2 24
22U_0402_6.3V6M
22U_0402_6.3V6M
RF@
RF@
25
26 25
<12> WWAN_CBL_DET# 27 26
28 27
29 28
30 29
30 31
GND 32
GND
ACES_51540-03041-001
CONN@
A A

6= (<< A)8. +
RTL8111G-CGT (71.08111.U03/LDO Mode): 10/100/1000M < 252 mW. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
RTL8106E-CG (071.08106.0003): 10/100M <70mW. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2 1
5 4 3 2 1
Main Func = LAN

Layout:
LAN Chip (10/100/1000M & 10/100M co-layout)
For RTL8111H-CG CL5: close to Pin8
* Place CL5,CL6,CL18,CL19 close to each VDD10 pin 8, 30, 3, 22 CL6: close to Pin30
UL1 1000@ CL10
For RTL8106E CL18: close to Pin3 RTL8111H-CG RTL8106E-CG 1 2 LANXIN_R 1 EMI@ 2 LANXIN
CL15,RL1: * Place CL5,CL6 close to each VDD10 pin 8, 30 CL19: close to Pin22 RL8 33_0402_5%
Only for 12P_0402_50V8J YL1
RTL8111 LDO mode. 1000@ SA000080P00 SA000065Y00 1 2
REGOUT RL1 1 2 0_0603_5% VDD10 40 mils XTAL0 GND0
RTL8111H-CG QFN 32P E-LAN CTRL 3 4
Vinafix.com
XTAL1 GND1
CL15
CL5
CL6
CL18
CL19
LDO mode LDO mode
SA000080P00 CL11 25MHZ_10PF_7V25000014
1 1 1 1 1 LANXOUT_R
1 2 1 EMI@ 2 LANXOUT
UL1 100@ 10/100/1000M 10/100M RL9 33_0402_5%
12P_0402_50V8J
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
D 2 2 2 2 2 D
1000@
1000@
1000@
RTL8106E-CG_QFN32_4X4 UL1
SA000065Y00 LAN_MDI0P 1 17 PCIE_CRX_C_LANTX_P5 CL1 1 2 .1U_0402_16V7K
LAN_MDI1P MDIP0 HSOP PCIE_CRX_C_LANTX_N5 PCIE_CRX_LANTX_P5 <10>
4 18 CL2 1 2 .1U_0402_16V7K
LAN_MDI0N MDIP1 HSON PCIE_CRX_LANTX_N5 <10>
2
LAN_MDI1N 5 MDIN0
MDIN1 13 PCIE_CTX_C_LANRX_P5 CL3 1 2 .1U_0402_16V7K
Layout: HSIP PCIE_CTX_C_LANRX_N5 PCIE_CTX_LANRX_P5 <10>
For RTL8111H-CG 14 CL4 1 2 .1U_0402_16V7K
HSIN PCIE_CTX_LANRX_N5 <10>
VDD10 8
* Place CL20 and CL7 and CL8 close to each VDD33 pin 11, 32 ,23 30 AVDD10
VDD10
For RTL8106E +LAN_VDD33 32 AVDD10 19 PLTRST# +3VS
* Place CL7 and CL8 close to each VDD33 pin 23, 32 VDDREG 23 AVDD33 PERSTB PLTRST# <11,22,25,32,34,37,44>
DVDD33 20 ISOLATE#
ISOLATEB
1
+LAN_VDD33 VDDREG 15
<11> CLK_PCIE_LAN_P2 REFCLK_P PCIE_WAKE#
16 21 RL3
<11> CLK_PCIE_LAN_N2 REFCLK_N LANWAKEB PCIE_WAKE# <11,25,32,37>
1K_0402_5%
40 mils RL5 1 @ 2 0_0603_5% <11> CLK_PCIE_LAN_REQ# 1 @ 2 CLK_LAN_REQ2#_R 12 26 RL21 1 MAD@ 2 0_0402_5% LOM_CABLE_DETECT <25>
RL13 0_0402_5% LANXIN 28 CLKREQB GPO RL17 1 2 0_0402_5%
+LAN_VDD33
2
29 CKXTAL1
CL7
CL8
CL20
LANXOUT @ ISOLATE#
CKXTAL2 3 VDD10
1 1 1 NC
1
LED0 27 6 LAN_MDI2P
CL8: close to Pin23 T47 TP@ LED0 NC LAN_MDI2N
CL20: close to Pin11 LED1 25 7 RL4
T45 TP@ LED1 NC 9 LAN_MDI3P 15K_0402_5%
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
2 2 CL7: close to Pin32 2 1 2 RSET 31 NC 10 LAN_MDI3N
RSET NC +LAN_VDD33
1000@
RL2 2.49K_0402_1% 11
2
33 NC 22 VDD10 CL22 1 2 1U_0402_10V6K
GND NC 24 REGOUT
NC CL23 1 2 .1U_0402_16V7K
RTL8106E-CG_QFN32_4X4
@
+LAN_VDD33
C
LAN TransFormer (10/100/1000M & 10/100M co-layout) C
1 1
@ @
CL24 CL25
4.7U_0402_6.3V6M 4.7U_0402_6.3V6M
2 2
MCT3
TL2 MCT2
Layout: MCT1
LAN_MDI3N 16 1 MDO3- MCT0
CL24: close to Pin32 LAN_MDI3P RX+ RD+
15 2 MDO3+
CL25: close to Pin11 14 RX- RD- 3 MCT0
1 1000@ 2 75_0603_5%
1 1000@ 2 75_0603_5%
2 75_0603_5%
2 75_0603_5%
13 CT CT 4
12 NC NC 5
+LAN_VDD33 Rising time (10%~90%) need LAN_MDI2N
11
10
NC
CT
NC
CT
6
7
MCT1
MDO2-
>0.5mS and <100mS. LAN_MDI2P 9 TX+
TX-
TD+
TD-
8 MDO2+
350uH_NS0013LF
1000@
+3VALW OPEN +LAN_VDD33 TL1
1
1
LAN_MDI1P 16 1
MCT RL14
RL15
RL19
RL20
MDO1+
JP11 LAN_MDI1N 15 RX+ RD+ 2 MDO1-
2 1 14 RX- RD- 3 MCT2
13 CT CT 4
2MM 12 NC NC 5
W=40mils W=40mils 11 NC NC 6 MCT3
JP@ LAN_MDI0P CT CT
10 7 MDO0+ 1
LAN_MDI0N 9 TX+ TD+ 8 MDO0-
TX- TD- CL13
10P_1206_2KV8J
LOM_TCT
350uH_NS0013LF 2 ESD@
+3VALW +LAN_VDD33
UL2
+3VALW
Layout note: Layout note:
2 1 5 1
CL9 1U_0402_6.3V6K IN OUT 30 mil spacing between MDI differential pairs. 30 mil spacing between MDI differential pairs.
B 2 B
GND
4 3 2 1
<25> AUX_ON EN OC RL7 10K_0402_5%
SY6288C20AAC_SOT23-5
High Active 1
2
CL12
RL6 0.01U_0402_50V7K
100K_0402_5% 2
Follow Reference Schematic 0.01uF~0.4uF
1
JLAN1 CONN@
12
GND 11
GND 10
GND 9
MDO0+ 1 GND
PR1+
MDO0- 2
PR1-
1.0V Source RL1 CL15 CL18 CL19 CL20 CL8 MDO1+ 3
PR2+
MDO2+ 4
PR3+
MDO2- 5
PR3-
MDO1- 6
RTL8111H-CG PR2-
RTL8111G-CGT LDO O O O O O X MDO3+ 7
PR4+
(71.08111.U03) MDO3- 8
PR4-
SANTA_130460-N
DC021702130
RTL8106E-CG X X X X X O
(071.08106.0003) LDO
A A

- A $0 7 )$0 7 ;2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
5 4 3 2 1
5 4 3 2 1
Main Func = DC/DC
Vinafix.com
NON-DSX(LOKI)
' ' ? ; 5 ' (% ) * ? ; 5 DSX(LOKI-L)
D
+5VALW +5VS '#,4 ) +. '#,4 ) 0 ). D
@ UZ3
CZ23 2 1 1 14 1 2
2 VIN1 VOUT1 13 CZ9 0.1U_0402_10V7K
1U_0402_6.3V6K VIN1 VOUT1
3 12 1 2
ON1 CT1 CZ10 470P_0402_50V7K
4 11 +3VALW +3VALW_PCH
VBIAS GND
For NON-DS3
5 10 1 2 1 LOKI@ 2
<11,17> SIO_SLP_S3# ON2 CT2 CZ11 470P_0402_50V7K RZ9 0_0805_5%
+3VALW
6 9
7 VIN2 VOUT2 8 @ 1 GEN9@ 2 +1.2V_DDR +1.2V_VCCSFR_OC
VIN2 VOUT2 +3VS
CZ37 2 1 RZ10 0_0805_5%
1 15 1 UZ7 For Gen9
@ GPAD 1U_0402_6.3V6K BSC Side
1
CZ25 EM5209VF_DFN14_3X2 CZ12 +3VALW
1 7 1 2
VIN VOUT
1U_0402_6.3V6K
1U_0402_6.3V6K 0.1U_0402_10V7K 2 8 CZ32 RZ16 0_0402_5% 1
2 2 VIN VOUT
CZ36
0.1U_0402_10V7K
RZ21 1 GEN9@ 2 0_0402_5% 3 6 2
<25,58,59> PCH_PRIM_EN ON CT
2
2
2
@ +5VALW
4
CZ46 VBIAS 5 CZ33 GEN9@
1 GND
+5VS +3VS 0.1U_0402_16V7K @ 9 1000P_0402_25V8J
1
1 CZ40 GND
0.1U_0402_10V7K
2 TPS22967DSGR_SON8_2X2
68P_0201_50V8J
68P_0201_50V8J
1 1 1 1 GEN9@
C53
33P_0201_25V8J
C54 RF@
C55
33P_0201_25V8J
C56 RF@
C C
2 2 2 2
RF@
RF@
B B
A A

)
5 4 3 2 1
5 4 3 2 1
Main Func = SSD M Key CONN
Vinafix.com
D D
+3VS_SSD +3VS
JP10 PJP@
1 2
1 2
10U_0805_25V6K~D
1U_0402_6.3V6K~D
0.1U_0402_25V6K~D
1000P_0402_50V7K~D
22U_0603_6.3V6M
22U_0603_6.3V6M
47U_0805_6.3V6M
47U_0805_6.3V6M
JUMP_43X79
1 1 1 1 1 1 1 1
CS24
CS25
CS26
CS27
CS36
CS35
CS34
CS33
@ @ @ @
2 2 2 2 2 2 2 2
NGFF Key M
+3VS_SSD
JSSD1
1 2
3 GND1 3.3VAUX1 4
5 GND2 3.3VAUX2 6
<10> PCIE_CRX_NVMETX_N9 7 PETn3 N/C1 8
<10> PCIE_CRX_NVMETX_P9 9 PETp3 N/C2 10 1 @ 2
CS16 1 2 0.22U_0402_16V7K PCIE_CTX_C_NVMERX_N9 11 GND3 DAS/DSS# 12 R77 0_0402_5% SSD_DAS# <10,29>
<10> PCIE_CTX_NVMERX_N9 PCIE_CTX_C_NVMERX_P9 PERn3 3.3VAUX3
CS17 1 2 0.22U_0402_16V7K 13 14
<10> PCIE_CTX_NVMERX_P9 PERp3 3.3VAUX4
15 16
17 GND4 3.3VAUX5 18
<10> PCIE_CRX_NVMETX_N10 19 PETn2 3.3VAUX6 20
<10> PCIE_CRX_NVMETX_P10 21 PETp2 N/C3 22
C C
CS18 1 2 0.22U_0402_16V7K PCIE_CTX_C_NVMERX_N10 23 GND5 N/C4 24
<10> PCIE_CTX_NVMERX_N10 PCIE_CTX_C_NVMERX_P10 PERn2 N/C5
CS19 1 2 0.22U_0402_16V7K 25 26
<10> PCIE_CTX_NVMERX_P10 PERp2 N/C6
27 28
29 GND6 N/C7 30
<10> PCIE_CRX_NVMETX_N11 31 PETn1 N/C8 32
<10> PCIE_CRX_NVMETX_P11 33 PETp1 N/C9 34
<10> PCIE_CTX_NVMERX_N11 PCIE_CTX_C_NVMERX_P11 PERn1 N/C11
CS21 1 2 0.22U_0402_16V7K 37 38
<10> PCIE_CTX_NVMERX_P11 PERp1 DEVSLP SSD_DEVSLP <10>
39 40
41 GND8 N/C12 42
<10> PCIE_CRX_NVMETX_P12 43 PETn0/SATA-B+ N/C13 44
<10> PCIE_CRX_NVMETX_N12 45 PETp0/SATA-B- N/C14 46
<10> PCIE_CTX_NVMERX_N12 PCIE_CTX_C_NVMERX_P12 PERn0/SATA-A- N/C16
CS23 1 2 0.22U_0402_16V7K 49 50
<10> PCIE_CTX_NVMERX_P12 PERp0/SATA-A+ PERST# PLTRST# <11,22,25,32,34,35,44>
51 52
53 GND10 CLKREQ# 54 CLK_PCIE_NVME_REQ# <11>
RS2 <11> CLK_PCIE_NVME_N4 REFCLKN PEW ake# PCIE_WAKE# <11,25,32,35>
55 56
<11> CLK_PCIE_NVME_P4 REFCLKP N/C17
10K_0402_5% 57 58
2 1 GND11 N/C18
+3VS_SSD
Key M
67 68
69 N/C19 SUSCLK(32kHz)(O)(0/3.3V) 70
<10> M2_SSD_PEDET 71 PEDET(OC-PCIe/GND-SATA) 3.3VAUX7 72
73 GND13 3.3VAUX8 74
75 GND15 3.3VAUX9
GND17
B B
77 76
PTH2 PTH1
LCN_DAN05-67306-0103
PEDET Module Type

0 SATA
1 PCIE
A A

A8& %%
5 4 3 2 1
5 4 3 2 1
Main Func = CCG4

+CCG_VBUS
+3.3V_VDD_PIC UT1
4 5
1
31 11 VBUS_P_CTRL_P1 <40,54>
VDDD VBUS_P_CTRL_P1 RT1
32 12 100K_0402_1%
VDDIO VBUS_C_CTRL_P1 VBUS_C_CTRL_P1 <54>
TYPEC@
+5V_CONN_P1 +5V_CONN_P1 +3.3V_VDD_PIC +3.3V_VDD_PIC 20
VBUS_DISCHARGE <40>
2
CT8 2 1 1U_0603_16V7 33 VBUS_DISCHARGE_P1 VBUS_MON_P1
Vinafix.com
VCCD
TYPEC@
1
2 RT8 @ 1 +3.3V_VDD_PIC 1
68P_0201_50V8J
68P_0201_50V8J
1 1 1 1 1 1 1 10K_0402_5%
1U_0603_16V7
1U_0603_16V7
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
CT78
CT77
+5V_CONN_P1 8 18 HPD_P1 <39> RT2 CT1
D V5V_P1 HPD_P1/GPIO 0.1U_0402_25V6 D
CT2
CT3
CT4
CT5
CT6
10K_0402_1%
23 TYPEC@ 2 TYPEC@
4 5
2
2 2 2 2 2 2 2 V5V_P2
TYPEC@RF@
7
CC2_P1 CCG4_CC2_P1 <40>
TYPEC@RF@
CT10 1 2 390P_0402_50V7K
TYPEC@
TYPEC@
3
I2C_SDA_SCB2_AR/VSEL_1_P1
TYPEC@
TYPEC@
TYPEC@
TYPEC@
4
I2C_SCL_SCB2_AR/VSEL_1_P2 9
CC1_P1 CCG4_CC1_P1 <40>
5
<40> MUX_USB2_FILP I2C_INT_AR_P1 CT11 1 2 390P_0402_50V7K
+#,@ +#, # 4 6
I2C_INT_AR_P2 26 VBUS_C_CTRL_P1 1 2
SDA_3/MUX_CTRL_3_P1/VSEL_2_P1 MUX_A_EN <40>TYPEC@
28
SDA_4/MUX_CTRL_2_P1 MUX_I2C_DATA <39>
29 MUX_I2C_CLK <39> TYPEC@ RT113 100K_0402_1%
VBUS_MON_P1 13 SCL_4/MUX_CTRL_1_P1
VBUS_MON_P1/GPIO VBUS_P_CTRL_P1 1 2
+3.3V_VDD_PIC +3.3V_VDD_PIC
TYPEC@ RT112 100K_0402_1%
37
VBUS_MON_P2/GPIO
1
30
RT3 @ HPD_P2/GPIO
10K_0402_5% RT64 TYPEC@
75K_0402_1%
22
2
CCG4_ID1 CCG4_ID2 CCG4_SWD_IO 1 CC1_P2

SWD_IO/AR_RST#
1
CCG4_SWD_CLK 2
RT4 RT65 SWD_CLK/I2C_CFG_EC
10K_0402_5% 45.3K_0402_1%
TYPEC@ TYPEC@ 15 24
2
<25> CCG4_I2C_INT# I2C_INT_EC CC2_P2

16
<25,40> TYPEC_SMBDA I2C_SDA_SCB1_EC
17 UT1
<25,40> TYPEC_SMBCLK I2C_SCL_SCB1_EC
C 34 C
MUX_CTRL_3_P2/GPIO 35
MUX_CTRL_2_P2/GPIO SA00009U520
36 MUX_B_EN <40>
UT6 MUX_CTRL_1_P2/GPIO TYPEC@
+5VALW TP89 VCONN_MON_P1 19
2 VCONN_MON_P1/GPIO
GND
S IC CYPD4125-40LQXIT QFN40 FOR INTEL FW
14
1 <40,54> OVP_TRIP_P1 OVP_TRIP_P1
IN
1
3
OUT +5V_CONN_P1 CCG4_ID1
CT7 25
0.1U_0402_10V7K SCL_3/VCONN_MON_P2
TYPEC@ 2 AP2330W-7_SC59-3 4 5 CCG4_ID2 27
VSEL_2_P2/GPIO +3.3V_VDD_PIC
TYPEC@
38
0.2A OCP for VCONN! 21
VBUS_C_CTRL_P2
39 JCCG4 CONN@
OVP_TRIP_P2 VBUS_P_CTRL_P2 1
40 1 2
VBUS_DISCHARGE_P2 2 3 CCG4_XRES
+3.3V_VDD_PIC 3 4 CCG4_SWD_CLK
4 5 CCG4_SWD_IO
RT5 1 2 4.7K_0402_5% CCG4_XRES 10 5
XRES 41 CVILU_CH31052VA00-NH
EPAD PCB Footprint = DC021611210
TYPEC@ 1
0.1U_0402_10V7K
+ ;
CT9
TYPEC@
S IC CYPD4125-40LQXIT QFN40 FOR INTEL FW
2 @
? 8 ? 5 J )- )#K 2J )- )4K
B B
> ? 5
)- )# )- )4
# ,>=/ $0 ,0/= ?:-- $0 $.#, N 1 N
4 ,>=/ $0 ,0/= ?:-- $0 2= $/, !
,>=/ $0 ,0/= ?:-- $0 2# /
,>=/ $0 ,0/= ?:-- $0 N
UT4
RT9069-33GB_SOT23-5 DT2 ,>=/ $0 ,0/= ?:-- $0 N1 O
1 5 2 1
+CCG_VBUS_1 VCC OUT TYPEC@
+3.3V_VDD_PIC ) 0;/$" #$% ? ?#./*
2
GND
RB551V-30_SOD323-2 $ ,>=/ $0 ,0/= ?:-- $0 0#$ $% & 3
1
10K_0402_5%
1
2.2U_0603_10V6K
1 1 3 4 9 ,>=/ $0 , 0 ?:-- $0/% O1

1U_0603_25V
0.1U_0402_25V6
NC EN
CT14 @
CT17
RT121
TYPEC@
O ) 0;/$" #$% ? ?#./*

CT15
TYPEC@ 2
2
2 2
TYPEC@
TYPEC@
8
TYPEC@
1 2 % '
RT59 200K_0402_1%
%# ( '
%4 ( '3
1
D
RT6 0_0402_5% TYPEC@
RT59 200k CT53:1U delay 70ms
1U_0603_25V6
1
2 1 2 % ( '
POK <11,25,53,56,58,59>
TYPEC@ CT53
G
A S % ( ' A
LN2306LT1G_SOT23-3
2
@ CT54
TYPEC@
% ( '
QT4
1U_0402_16V6K
%$ ( '!
2
%9 ( '

@
5 4 3 2 1
5 4 3 2 1
Main Func = typec MUX & DP MUX
Vinafix.com
UT2 UT2
SA00009R710 SA00009R720
+3VALW +3.3V_CPS @ TYPEC@
4 5 TUSB546-DCIRNQR USB3.1 DP SW TUSB546A-DCIRNQR QFN40 USB3.1 DP SW

1 2 4 5
LT1 BLM15PX600SN1D_2P
TYPEC@ TUSB546: Pop RT54,Depop CT50
1 1 1 1 1 PS8740:Depop RT54,Pop CT50
10U_0402_6.3V6M
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
D @ D
2 1
TYPEC@ CT19
TYPEC@ CT20
TYPEC@ CT21
TYPEC@ CT22
TYPEC@ CT23
2.2U_0402_6.3V6M CT50
2 2 2 2 2
TYPEC@ UT2
1 2 +3.3V_CPS_R1 1 35 MUX_USB_EQ1
6 VCC EQ1 38 MUX_USB_EQ0
RT54 0_0402_5%
20 VCC EQ0
28 VCC 17 MUX_I2C_EN
+3VALW VCC I2C_EN
2 MUX_DPEQ1
+3.3V_CPS TYPEC_DP_P0 TYPEC_DP_P0_C DPEQ1 MUX_DPEQ0
TYPEC@ CT24 2MAD@1 0.1U_0402_10V7K 9 14
1 2 MUX_I2C_CLK TYPEC_DP_N0 TYPEC_DP_N0_C DP0p DPEQ0/A1
CT25 2MAD@1 0.1U_0402_10V7K 10
DP0n 3 MUX_SSEQ1
RT52 2.2K_0402_5%
1 2 MUX_I2C_DATA TYPEC_DP_P1 TYPEC_DP_P1_C SSEQ1 MUX_SSEQ0
CT26 2MAD@1 0.1U_0402_10V7K 12 11
TYPEC_DP_N1 TYPEC_DP_N1_C DP1p SSEQ0/A0
RT53 TYPEC@ 2.2K_0402_5% CT27 2MAD@1 0.1U_0402_10V7K 13
DP1n
68P_0201_50V8J
1 TYPEC_DP_P2 TYPEC_DP_P2_C
CT79
CT28 2MAD@1 0.1U_0402_10V7K 15 21

TYPEC_DP_N2 TYPEC_DP_N2_C DP2p FLIP/SCL MUX_I2C_CLK <38>
CT29 2MAD@1 0.1U_0402_10V7K 16
DP2n 22
2 TYPEC_DP_P3 TYPEC_DP_P3_C CTL0/SDA MUX_I2C_DATA <38>
TYPEC@RF@
CT30 2MAD@1 0.1U_0402_10V7K 18

TYPEC_DP_N3 TYPEC_DP_N3_C DP3p HPD_P1
CT31 2MAD@1 0.1U_0402_10V7K 19 23 1 TYPEC@2
+3VALW DP3n CTL1 RT101 0_0402_5%
31 34
<40> TYPEC_RX1N RX1n TX1n TYPEC_TX1N <40>
30 33
<40> TYPEC_RX1P
1
RX1p TX1p TYPEC_TX1P <40>

1K_0402_5%
TYPEC@
RT11
39 37
<40> TYPEC_RX2N 40 RX2n TX2p 36 TYPEC_TX2P <40>
<40> TYPEC_RX2P RX2p TX2n TYPEC_TX2N <40>
TYPEC@
2
1 0.1U_0402_10V7K USB3_CTX_C_DRX_P4 8
CT34 2TYPEC@ 5 USB3_CRX_C_DTX_P4
CT36 2 1 0.1U_0402_10V7K
MUX_I2C_EN <10> USB3_CTX_DRX_P4
1 0.1U_0402_10V7K USB3_CTX_C_DRX_N4 7
CT35 2TYPEC@ SSTXp SSRXp 4 USB3_CRX_C_DTX_N4
CT37 2 1 0.1U_0402_10V7K USB3_CRX_DTX_P4 <10>
<10> USB3_CTX_DRX_N4 SSTXn SSRXn USB3_CRX_DTX_N4 <10>
TYPEC@
1
1
1K_0402_5%
20K_0402_5%
@ @ TP84 29 27
RESVD1 SBU1 MUX_SBU1 <40>
RT12
RT13
TP85 32 26
RESVD2 SBU2 MUX_SBU2 <40>
24 TYPEC_DP_AUXP_C TYPEC_DP_AUXP
CT32 2MAD@1 0.1U_0402_10V7K
41 AUXp 25 TYPEC_DP_AUXN_C TYPEC_DP_AUXN HPD_P1 CPU_DP2_HPD
CT33 2MAD@1 0.1U_0402_10V7K 1 LOKI@TYPEC@
2
2
PAD AUXn RT114 0_0402_5%

TUSB546-DCIRNQR USB3.1 DP SW
CPU_DP2_P0 DP_P0 TYPEC_DP_P0_C
@ RT104 1 LOKI@TYPEC@
2 0_0201_5% CT81 2LOKI@TYPEC@
1 0.1U_0402_10V7K
<6> CPU_DP2_P0 CPU_DP2_N0 DP_N0 TYPEC_DP_N0_C
RT105 1 LOKI@TYPEC@
2 0_0201_5% CT82 2LOKI@TYPEC@
1 0.1U_0402_10V7K
<6> CPU_DP2_N0
CPU_DP2_P1 DP_P1 TYPEC_DP_P1_C
I2C Programming or Pin Strap Programming Select,Internally RT106 1 LOKI@TYPEC@
2 0_0201_5% CT83 2LOKI@TYPEC@
1 0.1U_0402_10V7K
30k pull-up and 60k pull-down <6> CPU_DP2_P1 CPU_DP2_N1 DP_N1 TYPEC_DP_N1_C
RT107 1 LOKI@TYPEC@
2 0_0201_5% CT84 2LOKI@TYPEC@
1 0.1U_0402_10V7K
I2C_EN = <6> CPU_DP2_N1
0: Tie 1k to GND,Pin Strap(I2C disable) CPU_DP2_P2 DP_P2 TYPEC_DP_P2_C
+3VS RT108 1 LOKI@TYPEC@
2 0_0201_5% CT85 2LOKI@TYPEC@
1 0.1U_0402_10V7K
R:Tie 20k to GND,TI Test Mode(I2C enabled) +3VS <6> CPU_DP2_P2 CPU_DP2_N2 DP_N2 TYPEC_DP_N2_C
RT109 1 LOKI@TYPEC@
2 0_0201_5% CT86 2LOKI@TYPEC@
1 0.1U_0402_10V7K
C F: Float,TI Test Mode(I2C enabled) <6> CPU_DP2_N2 C
1:Tie 1k to VCC,I2C enabled TYPEC_DP_AUXN 2 MAD@ 1 CPU_DP2_P3 DP_P3 TYPEC_DP_P3_C
RT110 1 LOKI@TYPEC@
2 0_0201_5% CT87 2LOKI@TYPEC@
1 0.1U_0402_10V7K
<6> CPU_DP2_P3 CPU_DP2_N3 DP_N3 TYPEC_DP_N3_C
RT117 100K_0402_5% RT111 1 LOKI@TYPEC@
2 0_0201_5% CT88 2LOKI@TYPEC@
1 0.1U_0402_10V7K
TYPEC_DP_AUXN_C 2 TYPEC@1 <6> CPU_DP2_N3
CPU_DP2_AUXP DP_AUXP TYPEC_DP_AUXP_C
RT97 100K_0402_5% RT102 1 LOKI@TYPEC@
2 0_0201_5% CT89 2LOKI@TYPEC@
1 0.1U_0402_10V7K
VGA_DP_AUXN <6> CPU_DP2_AUXP CPU_DP2_AUXN DP_AUXN TYPEC_DP_AUXN_C
2 MAD@ 1 1 1 1 1 1 RT103 1 LOKI@TYPEC@
2 0_0201_5% CT90 2LOKI@TYPEC@
1 0.1U_0402_10V7K
<6> CPU_DP2_AUXN
1U_0402_10V6K
CT71 MAD@
1U_0402_10V6K
CT72 MAD@
1U_0402_10V6K
CT73 MAD@
0.1U_0402_10V7K
CT74 MAD@
0.1U_0402_10V7K
CT75
RT93 100K_0402_5%
TYPEC_DP_AUXP 2 MAD@ 1 2 2 2 2 2
MAD@
RT116 100K_0402_5%
TYPEC_DP_AUXP_C 2 TYPEC@1
RT94 100K_0402_5%
VGA_DP_AUXP 2 MAD@ 1 UT5
RT98 100K_0402_5%
5
21 VDD33 50
30 VDD33 OUT1_D0p 49 VGA_DP2_P0 <34>
+3VALW +3VALW +3VALW 51 VDD33 OUT1_D0n VGA_DP2_N0 <34>
57 VDD33 47
VDD33 OUT1_D1p 46 VGA_DP2_P1 <34>
OUT1_D1n VGA_DP2_N1 <34>
CPU_DP2_P0 CPU_DP2_P0_C
1
1
1K_0402_5%
1K_0402_5%
1K_0402_5%
@ @ @ CT55 2MAD@1 0.1U_0402_10V7K 6 45

CPU_DP2_N0 CPU_DP2_N0_C IN_D0p OUT1_D2p
RT14
RT20
RT26
CT56 2MAD@1 0.1U_0402_10V7K 7 44

IN_D0n OUT1_D2n
CPU_DP2_P1 CPU_DP2_P1_C
CT57 2MAD@1 0.1U_0402_10V7K 9 42
CPU_DP2_N1 CPU_DP2_N1_C IN_D1p OUT1_D3p
CT58 2MAD@1 0.1U_0402_10V7K 10 41
2
IN_D1n OUT1_D3n
MUX_SSEQ0 MUX_DPEQ1 MUX_USB_EQ0 CPU_DP2_P2 CPU_DP2_P2_C
CT59 2MAD@1 0.1U_0402_10V7K 12
CPU_DP2_N2 CPU_DP2_N2_C IN_D2p TYPEC_DP_P0
CT60 2MAD@1 0.1U_0402_10V7K 13 40
IN_D2n OUT2_D0p 39 TYPEC_DP_N0
CPU_DP2_P3 CPU_DP2_P3_C OUT2_D0n
CT61 2MAD@1 0.1U_0402_10V7K 15
CPU_DP2_N3 CPU_DP2_N3_C IN_D3p TYPEC_DP_P1
1
1
1K_0402_5%
20K_0402_5%
1K_0402_5%
20K_0402_5%
1K_0402_5%
20K_0402_5%
@ @ @ CT62 2MAD@1 0.1U_0402_10V7K 16 37

IN_D3n OUT2_D1p TYPEC_DP_N1
RT15
RT16
RT21
RT22
RT27
RT28
36
TYPEC@
TYPEC@
TYPEC@
OUT2_D1n
35 TYPEC_DP_P2
4 OUT2_D2p 34 TYPEC_DP_N2
2
3 IN_CA_DET OUT2_D2n
<6> CPU_DP2_HPD I2C_CTL_EN 2 IN_HPD 32 TYPEC_DP_P3
1 I2C_CTL_EN OUT2_D3p 31 TYPEC_DP_N3
PL1
PL0 60 Pl1/SCL_CTL OUT2_D3n
Pl0/SDA_CTL
Ser the USB receiver equalizer gain for upstream facing Select the DisplayPort receiver equalizer gain ,Internally Ser the USB receiver equalizer gain for downstream facing 26
SSTXP/N,Internally 30k pull-up and 60k pull-down 30k pull-up and 60k pull-down RX1 and RX2 when USB utilized,Internally 30k pull-up and 22 OUT1_AUXp_SCL 27 VGA_DP_AUXP <34>
SSEQ = DPEQ = 60k pull-down 23 IN_DDC_SCL OUT1_AUXn_SDA VGA_DP_AUXN <34>
0: Tie 1k to GND 0: Tie 1k to GND USB_EQ = CPU_DP2_AUXP CPU_DP2_AUXP_C IN_DDC_SDA TYPEC_DP_AUXP
CT67 2MAD@1 0.1U_0402_10V7K 24 28
R:Tie 20k to GND R:Tie 20k to GND 0: Tie 1k to GND CPU_DP2_AUXN CPU_DP2_AUXN_C IN_AUXp OUT2_AUXp_SCL TYPEC_DP_AUXN
CT68 2MAD@1 0.1U_0402_10V7K 25 29
F: Float F: Float R:Tie 20k to GND IN_AUXn OUT2_AUXn_SDA
1:Tie 1k to VCC 1:Tie 1k to VCC F: Float CFG_0 59 43 2 MAD@ 1
1:Tie 1k to VCC CFG_1 CFG0 OUT1_CA_DET
58 48 RT99 1M_0402_1%
B CFG1 OUT1_HPD VGA_DP_HPD <34> B
PC10 56
PC11 55 PC10 33 2 MAD@ 1
54 PC11 OUT2_CA_DET 38 HPD_P1
PC20 RT100 1M_0402_1%
+3VALW +3VALW +3VALW 53 PC20 OUT2_HPD HPD_P1 <38>
PC21
PC21 18 1 MAD@2
SW +3VS
11 8 PEQ RT115 4.7K_0402_5%
19 GND PEQ 14
GND PD
1
1
1K_0402_5%
1K_0402_5%
1K_0402_5%
@ @ @ 52 17
GND CEXT
RT17
RT23
RT29
61 20
PAD(GND) REXT
1
PS8338BQFN60GTR-A1_QFN60_5X9 1
MAD@ RT82 CT76
2
4.99K_0402_1% 2.2U_0402_6.3V6M
MUX_SSEQ1 MUX_DPEQ0 MUX_USB_EQ1
MAD@ MAD@
2
2
1
1
1K_0402_5%
20K_0402_5%
1K_0402_5%
20K_0402_5%
1K_0402_5%
20K_0402_5%
@ @ @
RT18
RT19
RT24
RT25
RT30
RT31
TYPEC@
TYPEC@
TYPEC@
2
PC10 1 @ 2 PEQ 1 @ 2 PL0 1 @ 2

+3VS +3VS +3VS
RT66 4.7K_0402_5% RT83 4.7K_0402_5% RT79 4.7K_0402_5%
1 @ 2 1 2
RT67 4.7K_0402_5% RT84 4.7K_0402_5%
TYPEC@ PL0
Automatic EQ disable; Internal pull down at ~150K Ohm, 3.3V IO
PC20 1 @ 2 PEQ L: Automatic EQ enable (default)
+3VS H: Automatic EQ disable
RT70 4.7K_0402_5% Programmable input equalization levels; Internal pull down at ~150K Ohm, 3.3V I/O.
1 @ 2 L: default, LEQ, compensate channel loss up to 11.5dB @ HBR2
RT71 4.7K_0402_5% H: HEQ, compensate channel loss up to 14.5dB @ HBR2
M: LLEQ, compensate channel loss up to 8.5dB @ HBR2
PC10,PC20 PL1 1 @ 2
+3VS
AUX interception disable for Port y (y = 1, 2). Internal pull down at ~150K Ohm, 3.3V I/O; RT80 4.7K_0402_5%
L: AUX interception enable, driver configuration is set by link training (default) 1 2
H: AUX interception disable, driver output with fixed 800mV and 0dB CFG_0 1 MAD@2 +3VS RT81 4.7K_0402_5%
M: AUX interception disable, driver output with fixed 400mV and 0dB RT74 4.7K_0402_5% TYPEC@
CFG_0 PL1
Chip operational mode configuration; Auto test enable; Internal pull down at ~150K Ohm, 3.3V I/O.
PC11 1 @ 2 Internal pull down at ~150K Ohm, 3.3V I/O. L: Auto test disable & input offset cancellation enable (default)
+3VS L: Control switching mode (default) H: Auto test enable & input offset cancellation enable
RT68 4.7K_0402_5%
H: Automatic switching mode M: Auto test disable & input offset cancellation disable
1 @ 2
RT69 4.7K_0402_5%
A 1 2 CFG_1 1 2 I2C_CTL_EN 1 2 A
PC21 @ +3VS @ @ +3VS
RT72 4.7K_0402_5% RT75 4.7K_0402_5% RT77 4.7K_0402_5%
1 @ 2 1 @ 2 1 2
+3VS
RT73 4.7K_0402_5% RT76 4.7K_0402_5% RT78 4.7K_0402_5%
TYPEC@
PC11,PC21 CFG_1
Output swing adjustment for Port y (y = 1, 2). Chip operational mode configuration; I2C_CTL_EN
Internal pull down at ~150K Ohm, 3.3V I/O; Internal pull down at ~150K Ohm, 3.3V I/O. I2C control enable; Internal pull down at ~150K Ohm, 3.3V I/O.
L: default L: Automatic power down enable (default) L: Pin control is selected (default)
H: +20% H: Automatic power down disable H: I2C control is selected with default address 0x58,0x59
M: -16.7% M: I2C control is selected with altermative I2C address 0xD6,0xD7

" $ &"
5 4 3 2 1
5 4 3 2 1
Main Func = USB2/I2C Mux

Close to JUSBC1 <500mil
1 @EMI@ 2
RT41 0_0402_5%
LT2 TYPEC@EMI@
2 1 USB_PN4_R
<10> USB_PN4
<10> USB_PP4 3 4 USB_PP4_R Vinafix.com

MCM1012B900F06BP_4P
D D
1 @EMI@ 2
RT42 0_0402_5%
+3VALW +CCG_VBUS +CCG_VBUS
CT38 UT3
2 1 13 20 JUSBC1
TYPEC@ 0.1U_0402_10V7K VCC A1_OUTp 19 A1 B12
USB_PP4_R 1 A1_OUTn TYPEC@ GND1 GND3
USB_PN4_R 2 A_INp 18 TOP_MUX_P CT40 1 2 0.1U_0402_10V7K TYPEC_TX1P_C A2 B11
A_INn A0_OUTp TOP_MUX_N <39> TYPEC_TX1P SSTXP1 SSRXP1 TYPEC_RX1P <39>
17 CT41 1 2 0.1U_0402_10V7K TYPEC_TX1N_C A3 B10
MUX_USB2_FILP A0_OUTn <39> TYPEC_TX1N SSTXN1 SSRXN1 TYPEC_RX1N <39>
14 TYPEC@
<38> MUX_USB2_FILP 16 SAI 15 1 RT39 2 2 1 A4 B9 1 2
CT44 CT46
<38> MUX_A_EN EN_A SAO VBUS1 VBUS3
0_0402_5% 0.47U_0402_25V6K TYPEC@ TYPEC@ 0.47U_0402_25V6K
TYPEC@ A5 B8
TYPEC_SMBCLK_R <38> CCG4_CC1_P1 CC1 SUB2 MUX_SBU2 <39>
RT119 1 TYPEC@ 2 0_0402_5% 3 6
<25,38> TYPEC_SMBCLK TYPEC_SMBDA_R B_INp B1_OUTp TOP_MUX_P_R BOT_MUX_N_R
RT118 1 TYPEC@ 2 0_0402_5% 4 7 A6 B7
<25,38> TYPEC_SMBDA B_INn B1_OUTn TOP_MUX_N_R A7 DP1 DN2 B6 BOT_MUX_P_R
MUX_USB2_FILP 12 8 BOT_MUX_P DN1 DP2
10 SBI B0_OUTp 9 BOT_MUX_N A8 B5
Bottom
<38> MUX_B_EN EN_B B0_OUTn <39> MUX_SBU1 SUB1 CC2 CCG4_CC2_P1 <38>
5 11 1 RT40 2 2 1 A9
TOP
CT45 B4 1 2 CT47
21 GND SBO 0_0402_5% 0.47U_0402_25V6K TYPEC@ VBUS2 VBUS4 TYPEC@ 0.47U_0402_25V6K
Thermal pad A10 B3 TYPEC_TX2N_C 0.1U_0402_10V7K 2TYPEC@
1 CT42
TYPEC@ <39> TYPEC_RX2N SSRXN2 SSTXN2 TYPEC_TX2P_C 0.1U_0402_10V7K TYPEC_TX2N <39>
TS3DS10224RUKR_WQFN20_3X3 A11 B2 2 1 CT43
<39> TYPEC_RX2P SSRXP2 SSTXP2 TYPEC_TX2P <39>
TYPEC@ TYPEC@
A12 B1
GND2 GND4
1 4
2 GND5 GND8 5
3 GND6 GND9 6
GND7 GND10 +CCG_VBUS
MUX_USB2_FILP MUX_A_EN MUX_B_EN A0_OUT B0_OUT JAE_DX07S024JJ2R1300~D

CONN@
C
0 0 1 -- USB2 C
0 1 1 I2C USB2
2
EU4011 @ESD@
1 1 0 USB2 -- L30ESD24VC3-2_SOT23-3
1 1 1 USB2 I2C
1
5V@3A TYPEC@
CT91 1 2 22U_0402_6.3V6M
5
UT7
OUT
1
JP14
2
JP@
1
+CCG_VBUS TYPEC@EMI@
+5VALW IN JUMP_43X39 1 2
2 RT55 0_0402_5% EU4001 EU4002
1 3 4 GND CCG4_CC1_P1 1 9 CCG4_CC1_P1 MUX_SBU2 1 9 MUX_SBU2
D
!" !"
<38,54> VBUS_P_CTRL_P1 EN
1
QT5 3 0_0402_5% 2TYPEC@ 1 RT120 LT3 @EMI@ TOP_MUX_N_R 2 ! 8 TOP_MUX_N_R BOT_MUX_N_R 2 ! 8 BOT_MUX_N_R
OCB USB_OC2# <10> TOP_MUX_N TOP_MUX_N_R
LN2306LT1G_SOT23-3 RT62 2 1
G
2
TYPEC@ SY6861A1AAC_SOT23-5 TOP_MUX_P_R 4 7 TOP_MUX_P_R BOT_MUX_P_R 4 7 BOT_MUX_P_R

10K_0402_5% ! !
TYPEC@ TYPEC@ TOP_MUX_P 3 4 TOP_MUX_P_R MUX_SBU1 5 ! 6 MUX_SBU1 CCG4_CC2_P1 5 ! 6 CCG4_CC2_P1

2
+CCG_VBUS
<38,54> OVP_TRIP_P1 3 3
MCM1012B900F06BP_4P
1
B B
10U_0603_25V6M
10U_0603_25V6M
22U_0805_25V6M
RT63 1 1 1 1 2 8 8
100K_0402_5% RT56 0_0402_5%
CT39 TYPEC@
CT92 TYPEC@
TYPEC@ CT93 @ TYPEC@EMI@ L05ESDL5V0NA-4_SLP2510P8-10-9 L05ESDL5V0NA-4_SLP2510P8-10-9

TYPEC@ESD@ TYPEC@ESD@
2
2 2 2
+CCG_VBUS +CCG_VBUS
TYPEC@EMI@
1
68P_0201_50V8J
1 1 2
CT80
RT33 RT57 0_0402_5%

100_1206_5% TYPEC_TX1P_C 1 2 TYPEC@ESD@ TYPEC_RX1P 1 2 TYPEC@ESD@
TYPEC@ DT3 AZ5B75-01B.R7G_CSP0603P2Y2 DT7 AZ5B75-01B.R7G_CSP0603P2Y2
2
TYPEC@RF@
LT4 @EMI@
2
BOT_MUX_P 2 1 BOT_MUX_P_R TYPEC_TX1N_C 1 2 TYPEC@ESD@ TYPEC_RX1N 1 2 TYPEC@ESD@

DT4 AZ5B75-01B.R7G_CSP0603P2Y2 DT8 AZ5B75-01B.R7G_CSP0603P2Y2
BOT_MUX_N 3 4 BOT_MUX_N_R TYPEC_RX2N 1 2 TYPEC@ESD@ TYPEC_TX2N_C 1 2 TYPEC@ESD@
1
DT5 AZ5B75-01B.R7G_CSP0603P2Y2 DT9 AZ5B75-01B.R7G_CSP0603P2Y2

D MCM1012B900F06BP_4P
2 QT3 TYPEC_RX2P 1 2 TYPEC@ESD@ TYPEC_TX2P_C 1 2 TYPEC@ESD@
<38> VBUS_DISCHARGE 1 2
G 2N7002K_SOT23-3 DT6 AZ5B75-01B.R7G_CSP0603P2Y2 DT10 AZ5B75-01B.R7G_CSP0603P2Y2
S TYPEC@ RT58 0_0402_5%
1
TYPEC@EMI@
3
RT32
100K_0402_5%
TYPEC@
2
A A
Type-C 5V Provide Path Control Security Classification Compal Secret Data

0B
5 4 3 2 1
5 4 3 2 1
CPU +VCC_CORE
VCC
+1.0VS_VCCIO
Vinafix.com VCCIO
VCCGT
+VCC_GT
VCCGTX
Timing Diagram for S5 to S0 mode VDDQ

VDDQC
VCCPLL_OC
+1.2V_DDR +1.2V_VCCSFR_OC
(Loki)
D +1.0V_VCCST D
VCCST +1.0V_VCCSTG
VCCPLL
0.6V_DDR_VTT_ON
VCCSTG
8d DDR_VTT_CNTL
+VCC_SA
VCCSA
+1.0VS_VCCOPC
VCCOPC
+1.8V_PRIM
VCC_OPC_1P8
+1.0VS_VCCOPC
VCCEOPIO
D%( "& 4' ;
PCH PCH_RSMRST#_Q
1a +RTC_CELL +RTC_CELL_PCH
ADAPTER (Loki)
VCCRTC RSMRST#
DSW_PWROK
PCH_DPW ROK_R 5b
+1.0V_PRIM
1b +19VB
VCCPRIM_1P0
DCPDSW _1P0
VCCMPHYAON_1P0
VCCAPLL_1P0 PCH_PW ROK
RESET_OUT#
11
VCCCLK1~6
BATTERY
+1.0V_MPHYGT
VCCMPHYGT_1P0
+1.0V_PRIM VCCSRAM_1P0
VCCAMPHYPLL_1P0
VCCAPLLEBB
SYS_PWROK
SYS_PWROK
12
C C
EXT_PWR_GATE#
10a +PWR_SRC
+3VALW +3.3V_ALW_DSW
3 VCCDSW _3P3 IMVP_VR_ON
+19VB +VCC_SA
2 NCP81218 +VCC_CORE
EN_5V
+VCC_GT
VL
6a Power Button SY8180
+5VALW
3 +3.3V_SPI +3VALW_PCH
+19VB
VCCHDA
VCCSPI PWRBTN#
SIO_PW RBTN# 6b
2 VCCPRIM_3P3
VCCPGPPA~E
VCCRTCPRIM
EN_3V +3VLP SIO_SLP_S5#
SLP_S5#
SY8286
+3VALW +1.8V_PRIM 7
VCCPGPPG
VCCATS
+19VB
+1.0V_PRIM
POK +1.0V_PRIM SIO_SLP_S4#
8a
RT6228 +1.0V_PRIM VCCPRIM_CORE SLP_S4# TPS22967 +1.0V_VCCST
+3VALW +3VALW 8b
POK
RT8061 +1.8V_PRIM 13 PCH_PLTRST#
PLTRST#
RT9059GSP +2.5V_MEM
B B
PRIM_PW RGD
4 EC 1416
PRIM_PW RGD
4 +19VB
+1.2V_DDR
SIO_PW RBTN# 2a +3VALW
8d
VDDQ
6b RT8207
SIO_SLP_SUS#
DDR4
EM5209 +3VALW_PCH 0.6V_DDR_VTT_ON
+0.6V_DDR_VTT VTT
PGOOD
8c
RUNPW ROK 1.2V_VTT_PW RGD
ALL_SYS_PW RGD
10b PCH_RSMRST#
5a
11 RESET_OUT# +5VALW
12 SYS_PWROK
SLP_S3#
SIO_SLP_S3# 9a +5VS
EM5209VF
+3VS
+3VALW
+1.0V_PRIM
AND +1.0V_VCCSTG
A
SLP_S0#
TPS22961 +1.0VS_VCCIO 9b A
+3VALW
EM5209 +1.2V_VCCSFR_OC (Loki)

+1.2V_DDR

! # % C"
5 4 3 2 1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
A B C D E F G H
Main Func = eMMC
+1.8V_EMMC
RM3 1 MMC@ 2 20K_0402_5% EMMC_CMD_R Vinafix.com

1 8 EMMC_D5_R +3VALW +3V_EMMC +1.8V_PRIM +1.8V_EMMC
1 EMMC_D0_R 1
2 7
3 6 EMMC_D4_R
4 5 EMMC_D3_R
RPM1 20K_0804_8P4R_1% RM1 1 MMC@ 2 0_0603_5% RM2 1 MMC@ 2 0_0603_5%
MMC@
4.7U_0402_6.3V6M
0.1U_0402_25V6
4.7U_0402_6.3V6M
0.1U_0402_25V6
UM1 1 1
1
1 8 EMMC_D7_R E6 C14
EMMC_D2_R +3V_EMMC VCC NC
CM1 MMC@
CM2 MMC@
CM3 MMC@
CM4 MMC@
2 7 F5 D1
3 6 EMMC_D6_R J10 VCC NC D2
2
4 5 EMMC_D1_R K9 VCC NC D3 2 2
RPM2 20K_0804_8P4R_1% C6 VCC NC D4
+1.8V_EMMC VCCQ NC
MMC@ M4 D12
N4 VCCQ NC D13
Close Ball C2 +EMMC_VDDI P3 VCCQ NC D14
RM12 1 MMC@ 2 20K_0402_5% EMMC_RCLK_R MMC@ P5 VCCQ NC E1
RM13 1 MMC@ 2 20K_0402_5% EMMC_CLK_R CM5 2 1 0.1U_0402_25V6 C2 VCCQ NC E2
VDDi NC E3
CM8 1 @ 2 22P_0402_50V8J RM14 1 MMC@ 2 10_0402_1% EMMC_CLK_R M6 NC E12
<6> EMMC_CLK EMMC_CMD_R CLK NC RM1,CM1,CM2: close to UM1.F5 RM2,CM3,CM4: close to UM1.P3
RM15 1 MMC@ 2 10_0402_1% M5 E13
<6> EMMC_CMD EMMC_D0_R CMD NC
RM16 1 MMC@ 2 10_0402_1% A3 E14
<6> EMMC_DATA0 EMMC_D1_R DAT0 NC
RM17 1 MMC@ 2 10_0402_1% A4 F1
<6> EMMC_DATA1 EMMC_D2_R DAT1 NC +3V_EMMC +1.8V_EMMC
RM18 1 MMC@ 2 10_0402_1% A5 F2
RM19 1 MMC@ 2 10_0402_1% B2 F3
RM20 1 MMC@ 2 10_0402_1% B3 F12
RM21 1 MMC@ 2 10_0402_1% B4 F13
68P_0201_50V8J
68P_0201_50V8J
RM22 1 MMC@ 2 10_0402_1% B5 F14 1 1
CM9
CM10 @RF@
RM23 1 MMC@ 2 10_0402_1% B6 G1
<6> EMMC_DATA7 DAT7 NC G2
A6 NC G12
VSS NC 2 2
@RF@
E7 G13
G5 VSS NC G14
H10 VSS NC H1
J5 VSS NC H2
K8 VSS NC H3
C4 VSS NC H12
2 N2 VSSQ NC H13 2
N5 VSSQ NC H14
P4 VSSQ NC J1
P6 VSSQ NC J2
VSSQ NC J3
RM24 1 MMC@ 2 10_0402_1% EMMC_RCLK_R H5 NC J12
<6> EMMC_RCLK EMMC_RST# RM25 1 MMC@ 2 0_0402_5% EMMC_RST#_R K5 DS NC J13
RST_n NC
E9 J14
E10 VSF NC K1
F10 VSF NC K2
VSF NC K3
G10 NC K12
K10 RFU NC K13
E8 RFU NC K14
E5 RFU NC L1
G3 RFU NC L2
A7 RFU NC L3
K7 RFU NC L12
K6 RFU NC L13
P7 RFU NC L14
P10 RFU NC M1
RFU NC M2
+3V_EMMC C5 NC M3
A1 NC NC M7
+1.8V_PRIM A2 NC NC M8
MMC@ A8 NC NC M9
0.1U_0402_16V7K 2 1 CM7 A9 NC NC M10
NC NC
1
A10 M11
UM2 RM27 MMC@ A11 NC NC M12
1 5 A12 NC NC M13
NC VCC 10K_0402_5% NC NC
A13 M14
2 A14 NC NC N1
<11> PCH_PLTRST#
2
A 4 EMMC_RST# B1 NC NC N3
3 Y B7 NC NC N6
GND 1 NC NC
3 B8 N7 3
74AUP1G07GW_TSSOP5 CM6 @ B9 NC NC N8
B10 NC NC N9
MMC@ 100P_0402_50V8J NC NC
2 B11 N10
B12 NC NC N11
B13 NC NC N12
B14 NC NC N13
C1 NC NC N14
C3 NC NC P1
C7 NC NC P2
C8 NC NC P8
C9 NC NC P9
C10 NC NC P11
C11 NC NC P12
C12 NC NC P13
C13 NC NC P14
NC NC
THGBMBG8D4KBAIR_VFBGA153
@
4 4

$ 8! &&
A B C D E F G H
5 4 3 2 1
Main Func = GPU
Vinafix.com
D
' ' ,L '#,@ ? D
Maximum Output Current 4A
DIS@
@ CZ28 0.1U_0402_10V7K
CZ26 2 1 1 2
UZ4
1U_0402_6.3V6K JP9 PJP@
+3VS 1
2 VIN VOUT
7
8
+3VGS_OUT 1
1 2
2 +3VGS 250mA
VIN VOUT JUMP_43X79 E L
RZ6 1 DIS@ 2 0_0402_5% +3VGS_GPU_ON 3 6 ( ;
<9,63> DGPU_PWR_EN ON CT
2 2
@ +5VALW 4 CZ14 DIS@
CZ13 VBIAS 5 100P_0402_50V8J
1 GND
0.1U_0402_16V7K @ 9
1 CZ27 GND 1
0.1U_0402_10V7K
2 TPS22967DSGR_SON8_2X2
DIS@
C C
DIS@
@ CZ31 0.1U_0402_10V7K
CZ29 2 1 1 2
1U_0402_6.3V6K
1
UZ5
14 +0.95VSDGPU_OUT 1
JP7 PJP@
2
2300mA
+1.0V_PRIM
2 VIN1 VOUT1 13 1 2 +0.95VSDGPU E 9
VIN1 VOUT1
DGPU_PW R_EN RZ7 1 DIS@ 2 10K_0402_5% +0.95VSDGPU_ON 3 12 2
CZ18 DIS@
1 330P_0402_50V7K
JUMP_43X79 ( ;
@ ON1 CT1
+5VALW
CZ15 1DIS@ 2 0.1U_0402_16V7K CZ30 2 1 4 11
0.1U_0402_10V7K VBIAS GND
RZ8 1 DIS@ 2 10K_0402_5% +1.8VGS_GPU_ON 5 10 2 1 CZ19 DIS@
ON2 CT2 330P_0402_50V7K JP8 PJP@
CZ16 1DIS@ 2 0.1U_0402_16V7K 6 9 +1.8VGS_OUT 1 2
+1.8V_PRIM
7 VIN2
VIN2
VOUT2
VOUT2
8 1 2
JUMP_43X79
+1.8VGS
500mA
@
1
15 2
E @
GPAD
CZ17
1U_0402_6.3V6K EM5209VF_DFN14_3X2 CZ20 DIS@
( ;
2 DIS@ 0.1U_0402_10V7K
1
B B
Maximum Output Current 6A
A A
Security Classification Compal Secret Data Compal Electronics, Inc.

GPU Power
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F115P
5 4 3 2 1
1 2 3 4 5
Main Func = GPU

PEG_HTX_C_GRX_P[0..3]
<10> PEG_HTX_C_GRX_P[0..3]
PEG_HTX_C_GRX_N[0..3] / ; 8 82
<10> PEG_HTX_C_GRX_N[0..3]
PEG_GTX_C_HRX_P[0..3] @
<10> PEG_GTX_C_HRX_P[0..3]
UV1F
PEG_GTX_C_HRX_N[0..3] +VGA_CORE
<10> PEG_GTX_C_HRX_N[0..3]
Vinafix.com @
UV1A VARY_BL
DIGON
AB11
AB12
A A
AL15
TXCAP_DPA3P AK14
PEG_HTX_C_GRX_P0 DIS@ 2 1 CV312 0.22U_0402_16V7K PEG_HTX_GRX_P0 AF30 AH30 PEG_GTX_HRX_P0 DIS@ 2 1 CV1 0.22U_0402_16V7K PEG_GTX_C_HRX_P0 TXCAM_DPA3N
PEG_HTX_C_GRX_N0 DIS@ 2 1 CV306 0.22U_0402_16V7K PEG_HTX_GRX_N0 AE31 PCIE_RX0P PCIE_TX0P AG31 PEG_GTX_HRX_N0 DIS@ 2 1 CV2 0.22U_0402_16V7K PEG_GTX_C_HRX_N0 AH16
PCIE_RX0N PCIE_TX0N TX0P_DPA2P AJ15
TX0M_DPA2N
PEG_HTX_C_GRX_P1 DIS@ 2 1 CV308 0.22U_0402_16V7K PEG_HTX_GRX_P1 AE29 AG29 PEG_GTX_HRX_P1 DIS@ 2 1 CV3 0.22U_0402_16V7K PEG_GTX_C_HRX_P1 AL17
PEG_HTX_C_GRX_N1 DIS@ 2 1 CV305 0.22U_0402_16V7K PEG_HTX_GRX_N1 AD28 PCIE_RX1P PCIE_TX1P AF28 PEG_GTX_HRX_N1 DIS@ 2 1 CV4 0.22U_0402_16V7K PEG_GTX_C_HRX_N1 TX1P_DPA1P AK16
PCIE_RX1N PCIE_TX1N TX1M_DPA1N
AH18
PEG_HTX_C_GRX_P2 DIS@ 2 1 CV307 0.22U_0402_16V7K PEG_HTX_GRX_P2 AD30 AF27 PEG_GTX_HRX_P2 DIS@ 2 1 CV5 0.22U_0402_16V7K PEG_GTX_C_HRX_P2 TX2P_DPA0P AJ17
PEG_HTX_C_GRX_N2 DIS@ 2 1 CV309 0.22U_0402_16V7K PEG_HTX_GRX_N2 AC31 PCIE_RX2P PCIE_TX2P AF26 PEG_GTX_HRX_N2 DIS@ 2 1 CV6 0.22U_0402_16V7K PEG_GTX_C_HRX_N2 TX2M_DPA0N
PCIE_RX2N PCIE_TX2N AL19
NC_TXOUT_L3P AK18
PEG_HTX_C_GRX_P3 DIS@ 2 1 CV313 0.22U_0402_16V7K PEG_HTX_GRX_P3 AC29 AD27 PEG_GTX_HRX_P3 DIS@ 2 1 CV7 0.22U_0402_16V7K PEG_GTX_C_HRX_P3 NC_TXOUT_L3N
PEG_HTX_C_GRX_N3 DIS@ 2 1 CV304 0.22U_0402_16V7K PEG_HTX_GRX_N3 AB28 PCIE_RX3P PCIE_TX3P AD26 PEG_GTX_HRX_N3 DIS@ 2 1 CV8 0.22U_0402_16V7K PEG_GTX_C_HRX_N3
PCIE_RX3N PCIE_TX3N TMDP
AB30 AC25 AH20

AA31 PCIE_RX4P PCIE_TX4P AB25 TXCBP_DPB3P AJ19
PCIE_RX4N PCIE_TX4N TXCBM_DPB3N
AL21
AA29 Y23 TX3P_DPB2P AK20
Y28 PCIE_RX5P PCIE_TX5P Y24 TX3M_DPB2N
PCIE_RX5N PCIE_TX5N AH22
TX4P_DPB1P AJ21
Y30 AB27 TX4M_DPB1N
W31 PCIE_RX6P PCIE_TX6P AB26 AL23
PCIE_RX6N PCIE_TX6N TX5P_DPB0P AK22
TX5M_DPB0N
GPU R1/R3 W29

V28 PCIE_RX7P
PCIE_RX7N
PCIE_TX7P
PCIE_TX7N
Y27
Y26 NC_TXOUT_U3P
NC_TXOUT_U3N
AK24
AJ23
B B
UV1
V30 W24
U31 NC#V30 NC#W24 W23
SA0000B1W0L NC#U31 NC#W23
216-0842024-A11-MAR_FCBGA631
M2_50@ ?
U29 V27
T28 NC#U29 NC#V27 U26
S IC 216-0889004 A0 R17M-M2-50 FCBGA 0FD NC#T28 NC#U26
PCI EXPRESS INTERFACE

UV1 T30 U24
R31 NC#T30 NC#U24 U23
NC#R31 NC#U23
SA0000B1W1L
M2_50_R3@ R29 T26
P28 NC#R29 NC#T26 T27
NC#P28 NC#T27
S IC 216-0889004 A0 R17M-M2-50 WESTON XT BGA 631P GPU A31 !
P30 T24
N31 NC#P30 NC#T24 T23
NC#N31 NC#T23
N29 P27
M28 NC#N29 NC#P27 P26
NC#M28 NC#P26
M30 P24
L31 NC#M30 NC#P24 P23
NC#L31 NC#P23
L29 M27
K30 NC#L29 NC#M27 N26
NC#K30 NC#N26
C CLOCK C
CLK_PEG_VGA AK30
<11> CLK_PEG_VGA CLK_PEG_VGA# PCIE_REFCLKP
AK32
<11> CLK_PEG_VGA# PCIE_REFCLKN +0.95VSDGPU
CALIBRATION
Y22 RV1 1 DIS@ 2 1.69K_0402_1%
PCIE_CALR_TX
RV2 1 DIS@ 2 1K_0402_1% N10 AA22 RV3 1 DIS@ 2 1K_0402_1%
TEST_PG PCIE_CALR_RX
PLT_RST_VGA# AL27
PERSTB
2160856030-A0_FCBGA631
+3VGS
UV2
UV2
@ SA00000OH00
5
PLT_RST#
1 LOKI@DIS@
P
<11,22,25,32,34,35,37> PLTRST# IN1 4

O PLT_RST_VGA# <25>
2 S IC MC74VHC1G08DFT2G SC70 5P AND
<9> DGPU_HOLD_RST# IN2
G
DGPU_HOLD_RST#(GPP_D10)
3
RV4 UV2
MC74VHC1G08DFT2G_SC70-5 100K_0402_5%
D D
DIS@ SA741080400
2
MAD@DIS@
S IC 74AHC1G08GW SOT353 AND

Title
Compal Electronics, Inc.
Issued Date 2016/12/01 Deciphered Date 2017/12/01 MESO_(1/5)_PCIE/DP
Date:
LA-F115P
Friday, March 02, 2018 Sheet 44 of 65
1 2 3 4 5
1 2 3 4 5
Main Func = GPU

+3VGS
@
2 % G8 % <
UV1B +1.8VGS
U? 4 #M N8 2 8 P QH 0$#- #./
&8-: ) ;.* &8-% ) ;.* 0% P Q 8 P QH
1
RV5 RV6 AF2
8 P Q & 8 @P Q
NC#AF2
5
45.3K_0402_1% AF4 RV8
45.3K_0402_1% ( 8 P3Q & 8 @P Q
G
QV1B DIS@ DIS@ NC#AF4 8.45K_0402_1%
DIS@ TP50 N9 AG3 DIS@
( 3 8 P Q & 8 @P3Q
2
TP51 L9 DBG_DATA16 NC#AG3 AG5 PS_0
3 4 VGA_SMB_DA3 TP52 AE9 DBG_DATA15 NC#AG5
DPA ( 3 8 P Q
S
Vinafix.com
<8,25,30,34> SML1_SMBDATA DBG_DATA14
1
TP53 Y11 AH3
D
1
0.68U_0402_10V
TP54 AE8 DBG_DATA13 NC#AH3 AH1
DBG_DATA12 NC#AH1 !(B (BB 8 P Q 8 & 8 8 & P Q
2
DMN66D0LDW-7 2N SOT363-6 TP55 AD9 CV29 RV9
G
QV1A TP56 AC10 DBG_DATA11 AK3 @ 2K_0402_1%
DIS@ TP57 AD7 DBG_DATA10 NC#AK3 AK1
( (BB 2 DIS@
2
TP58 AC8 DBG_DATA9 NC#AK1
A
6 1 VGA_SMB_CK3 TP59 AC7 DBG_DATA8 DVO
AK5
(3 (!3 A
S
<8,25,30,34> SML1_SMBCLK DBG_DATA7 NC#AK5
TP60 AB9 AM3
D
TP61 AB8 DBG_DATA6 NC#AM3 (
DMN66D0LDW-7 2N SOT363-6 TP62 AB7 DBG_DATA5 AK6
TP63 AB4 DBG_DATA4 NC#AK6 AM5
(
TP64 AB2 DBG_DATA3 NC#AM5
DPB
TP65 Y8 DBG_DATA2 AJ7
TP66 Y7 DBG_DATA1 NC#AJ7 AH6 +1.8VGS 0$#- #./
DBG_DATA0 NC#AH6 8 P QH
AK8
2 % G8 % <
NC#AK8 8 P QH 8 P Q & 8 8@ 8 8
1
AL7
NC#AL7 DIS@
#- ), * 0% P Q RV11
8 P3Q & 8 8 8 8
W6 8.45K_0402_1% 8 P Q
V6 NC#W6
! ,
2
NC#V6 V4 PS_1
AC6 NC#V4 U5
8 P Q & 8 68 @8 &'8 8 9 @
NC#AC5 NC#U5 3,
1
AC5 1 8 P Q & 8 68 A8
0.68U_0402_10V
NC#AC6 W3 DIS@
AA5 NC#W3 V2
, CV28 RV12
AA6 NC#AA5 NC#V2 @ 2K_0402_1%
DPC
NC#AA6 Y4 2
2
+1.8VGS NC#Y4 W5
NC#W5
RV82 2 DIS@ 1 4.7K_0402_5% BP_0 U1 AA3 PLL_Analog_out
TP67 FB_VDDCI W1 NC#U1 NC#AA3 Y2
1 4.7K_0402_5% BP_1 U3 NC#W1 NC#Y2
1
RV81 2 DIS@
Y6 NC#U3 J8 RV83
TP68 PLL_Analog_in AA1 NC#Y6 NC#J8 16.2K_0402_1% +1.8VGS
NC#AA1 DIS@
83P QH 0$#- #./
83P QH
1
@
83P Q
I2C RV28 83P3Q
8.45K_0402_1%
TP69 R1
83P Q & 8 8& 8
2
TP70 R3 SCL PS_2
SDA
83P Q & 8 8'@ 8
1
AM26 1
0.082U_0402_16V
+VGA_CORE R AK26
TP90 U6
GENERAL PURPOSE I/O AVSSN#AK26 +3VGS CV11 RV13
83P Q
U10 GPIO_0 AL25 @ 4.75K_0402_1%
T10 GPIO_1 G AJ25 2 DIS@
2
VGA_SMB_DA3 GPIO_2 AVSSN#AJ25
1
+3VGS RV260 2 DIS@ 1 4.7K_0402_5% U8
B VGA_SMB_CK3 U7 SMBDATA AH24 RV162 B
T9 SMBCLK B AG25 4.7K_0402_5%
<25> GPU_PWR_LEVEL GPIO_5_AC_BATT AVSSN#AG25
T8 @
T7 GPIO_6 DAC1 AH26
2
P10 GPIO_7_BLON HSYNC AJ27 WAKEB
P4 GPIO_8_ROMSO VSYNC
GPIO_9_ROMSI
1
P2 +1.8VGS
N6 GPIO_10_ROMSCK AD22 RV163
8 P QH 0$#- #./
+VGA_CORE N5 GPIO_11 RSET 4.7K_0402_5%
GPIO_12 8 P QH
1
N3 AG24 DIS@
Y9 GPIO_13 AVDD AE22 @
8 P Q & 8 @P Q ) /. $2 *
'& 2-/
2
+1.8VGS N1 GPIO_14_HPD2 AVSSQ RV15 8 P3Q & 8 @P Q ) /. $2 *
JTAG M4
R6
GPIO_15_PWRCNTL_0
GPIO_16 VDD1DI
AE23
AD23
8.45K_0402_1%
8 P Q & 8 @P3Q ) /. $2 *
//% $/D/$/,7/
6 ! 7;/.#0 7
2
RV152 @ W10 GPIO_17_THERMAL_INT VSS1DI PS_3
2 1 GPIO19_CTF GPIO19_CTF M2 GPIO_18
GPIO_19_CTF FutureASIC/SEYMOUR/PARK 8 P Q 8 & 8 8 & P Q
1
+3VGS P8 AM12 1
0.68U_0402_10V
10K_0402_5% P7 GPIO_20_PWRCNTL_1 CEC_1 @
GPIO_21 8 P Q 8 & 8 8 & P3Q
2
1 @ 2 N8 CV15 RV16
RV154 1 @ 2 5.1K_0402_1% RV151 RV368 10K_0402_5% AK10 GPIO_22_ROMCSB AK12 RV155 1 DIS@ 2 0_0402_5% SVI2_SVD @ 4.75K_0402_1%
GPIO_29 RSVD#AK12 SVI2_SVT SVI2_SVD <63> 2
10K_0402_5% AM10 AL11 RV156 1 DIS@ 2 0_0402_5% SD034475180
SVI2_SVT <63>
2
DIS@ 1 @ 2 PEG_CLKREQ# N7 GPIO_30 RSVD#AL11 AJ11 RV157 1 DIS@ 2 0_0402_5% SVI2_SVC
<11> CLK_PCIE_PEG_REQ# CLKREQB RSVD#AJ11 SVI2_SVC <63>
RV17 1 DIS@ 2 1K_0402_1% TESTEN RV153 0_0402_5%
1
JTAG_TRSTB L6
JTAG_TDI_GPU L5 JTAG_TRSTB
JTAG_TCK L3 JTAG_TDI
JTAG_TMS_GPU L1 JTAG_TCK AL13
JTAG_TDO_GPU K4 JTAG_TMS GENLK_CLK AJ13
TESTEN K7 JTAG_TDO GENLK_VSYNC
+3VGS AF24 TESTEN
+VGA_CORE NC#AF24 AG13
@ SWAPLOCKA AH12
1 8 JTAG_TDO_GPU AB13 SWAPLOCKB
2 7 JTAG_TDI_GPU W8 GENERICA
3 6 JTAG_TMS_GPU W9 GENERICB
4 5 JTAG_TRSTB W7 GENERICC AC19 PS_0
AD10 GENERICD PS_0
RP34 10K_8P4R_5% AJ9 GENERICE AD19 PS_1
TP72 AL9 NC#AJ9 PS_1
NC#AL9 AE17 PS_2
AC14 PS_2
TP73 PX_EN AB16 HPD1 AE20 PS_3
2 @ 1 JTAG_TCK PX_EN PS_3
RV369 10K_0402_5%
C AE19 C
AC16 TS_A
DBG_VREFG
DDC/AUX
AE6
PLL/CLOCK DDC1CLK AE5
DDC1DATA
AD2
RV20 DIS@ AUX1P AD4 +VGA_CORE
1M_0402_5% AUX1N
XTALOUT XTALIN AC11
DDC2CLK AC13
YV1 DIS@ DDC2DATA
27MHZ_10PF_7V27000050 XTALIN AM28 AD13
XTALOUT AK28 XTALIN AUX2P AD11
3 1 XTALOUT AUX2N
3 1 RV29 1 DIS@ 2 10K_0402_5% AC22 AD20 FB_GND RV158 1 DIS@ 2 0_0402_5% VSSSENSE_VGA
1 GND GND 1 XO_IN NC#AD20 FB_VDDC VCCSENSE_VGA VSSSENSE_VGA <63>
CV18 CV17 RV59 1 DIS@ 2 10K_0402_5% AB22 AC20 RV159 1 DIS@ 2 0_0402_5%
XO_IN2 NC#AC20 VCCSENSE_VGA <63>
10P_0402_50V8J 10P_0402_50V8J
DIS@ 4 2 DIS@ AE16
2 2 NC#AE16 AD16
NC#AD16
SEYMOUR/FutureASIC AC1
+1.8VGS T4
DPLUS THERMAL
DDCVGACLK
DDCVGADATA
AC3 +1.8VGS M2-50 use +1.8v
LV2 DIS@ T2
1 2 # 5( DMINUS
BLM15BD121SN1D_0402
DIS@ GPIO28 R5
Change CV17, CV18 for YV1 frequency deviation CV19 2 1 10U_0603_6.3V6M +TSVDD AD17 GPIO28_FDO
Eason 2/19 DIS@ AC17 TSVDD
TSVSS
2
CV20 2 1 1U_0402_6.3V4Z
DIS@ @
CV21 2 1 0.1U_0402_10V6K RV84 RV87
216-0842024-A11-MAR_FCBGA631
10K_0402_5% 10K_0402_5%
RV21 1 @ 2 10K_0402_5% ? DIS@
1
!"#$% &'()*+% #,,('--../0123
SVI2_SVD 2B C
,#"=/ SVI2_SVC
(
(
2
D D
@ RV88 (B
RV89 10K_0402_5%
10K_0402_5% DIS@ (
1
Title
Issued Date 2016/12/01 Deciphered Date 2017/12/01 MESO_(2/5)_MSIC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Date: Friday, March 02, 2018
LA-F115P
Sheet 45 of 65
1 2 3 4 5
1 2 3 4 5
Main Func = GPU
Vinafix.com
A A
@
UV1E U?
9 5( B* -C / ; 8 82
#@@5( B ; C AA27 A3
AB24 GND GND A30
+1.8VGS AB32 GND GND AA13
@ AC24 GND GND AA16
RV27 1 2 0_0603_5% +DP_VDDR UV1G AC26 GND GND AB10
U?
AC27 GND GND AB15
B
AD25 GND GND AB6 B
CV26
CV27
CV35
NC/DP POWER
; 2 1 1 1
DP POWER
AD32 GND GND AC9
GND GND
( 8 ;B 5(C@ @ @
AG15
AG16 DP_VDDR#AG15 NC#AE11
AE11
AF11
AE27
AF32 GND GND
AD6
AD8
AF16 DP_VDDR#AG16 NC#AF11 AE13 AG27 GND GND AE7
10U_0603_6.3V6M
1U_0402_6.3V4Z
0.1U_0402_10V6K
2 2 2 AG17 DP_VDDR#AF16 NC#AE13 AF13 AH32 GND GND AG12
AG18 DP_VDDR#AG17 NC#AF13 AG8 K28 GND GND AH10
AG19 DP_VDDR#AG18 NC#AG8 AG10 K32 GND GND AH28
AF14 DP_VDDR#AG19 NC#AG10 L27 GND GND B10
DP_VDDR#AF14 M32 GND GND B12
N25 GND GND B14
N27 GND GND B16
P25 GND GND B18
AG20 AF6 P32 GND GND B20
AG21 DP_VDDC#AG20 NC#AF6 AF7 R27 GND GND B22
+0.95VSDGPU AF22 DP_VDDC#AG21 NC#AF7 AF8 T25 GND GND B24
4@ 5( AG22 DP_VDDC#AF22 NC#AF8 AF9 T32 GND GND B26
RV30 1 2 0_0603_5% +DP_VDDC AD14 DP_VDDC#AG22 NC#AF9 U25 GND GND B6
DP_VDDC#AD14 U27 GND GND B8
V32 GND GND C1
CV30
CV33
CV34
W25 GND GND C32
1 1 1 GND GND
AG14 AE1 W26 E28
@ @ @ AH14 DP_VSSR NC#AE1 AE3 W27 GND GND F10
AM14 DP_VSSR NC#AE3 AG1 Y25 GND GND F12
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 AM16 DP_VSSR NC#AG1 AG6 Y32 GND GND F14
AM18 DP_VSSR NC#AG6 AH5 GND GND F16
AF23 DP_VSSR NC#AH5 AF10 GND F18
AG23 DP_VSSR NC#AF10 AG9 GND F2
AM20 DP_VSSR NC#AG9 AH8 GND F20
AM22 DP_VSSR NC#AH8 AM6 M6 GND F22
AM24 DP_VSSR NC#AM6 AM8 N13 GND GND F24
AF19 DP_VSSR NC#AM8 AG7 N16 GND GND F26
AF20 DP_VSSR NC#AG7 AG11 N18 GND GND F6
AE14 DP_VSSR NC#AG11 N21 GND GND
GND F8
DP_VSSR P6 GND GND G10
C C
P9 GND GND G27
R12 GND GND G31
AF17 AE10 R15 GND GND G8
DPAB_CALR NC#AE10 R17 GND GND H14
R20 GND GND H17
T13 GND GND H2
T16 GND GND H20
216-0842024-A11-MAR_FCBGA631 GND GND
? T18 H6
T21 GND GND J27
T6 GND GND J31
U15 GND GND K11
U17 GND GND K2
U20 GND GND K22
U9 GND GND K6
V13 GND GND
V16 GND
V18 GND
Y10 GND
Y15 GND
Y17 GND
Y20 GND
R11 GND A32
T11 GND VSS_MECH AM1
AA11 GND VSS_MECH AM32
M12 GND VSS_MECH
N11 GND
V11 GND
GND
216-0842024-A11-MAR_FCBGA631
?
D D

Title
Issued Date 2016/12/01 Deciphered Date 2017/12/01 MESO_(3/5)_Power/GND
Date:
LA-F115P
1 2 3 4 5
1 2 3 4 5
Main Func = GPU
Vinafix.com
A
' () . " # 80 #80 ,#80 A
@
UV1D +1.8VGS
+1.35V_MEM_GFX
U?
# 5(
AM30 +PCIE_PVDD
- # 4( MEM I/O PCIE_PVDD
PCIE
CV38
CV46
CV39
H13 AB23
CV179
VDDR1 NC#AB23 1 1 1 1
H16 AC23
H19 VDDR1 NC#AC23 AD24 DIS@ DIS@ DIS@ DIS@
CV43
CV44
CV45
CV40
CV47
CV48
CV41
CV42
CV49
CV50
CV51
CV52
CV53
J10 VDDR1 NC#AD24 AE24
CV174
CV175
CV176
CV177
CV178
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
0.01U_0402_16V7K
J23 VDDR1 NC#AE24 AE25 2 2 2 2
' ,L # 80 #80 ,#80 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
DIS@ DIS@ DIS@ DIS@ DIS@
J24 VDDR1 NC#AE25 AE26
J9 VDDR1 NC#AE26 AF25
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 K10 VDDR1 NC#AF25 AG26
K23 VDDR1 NC#AG26
-") 4 9 K24 VDDR1
K9 VDDR1 L23
L11 VDDR1 PCIE_VDDC L24
L12 VDDR1 PCIE_VDDC L25
!-0) # 4 L13 VDDR1 PCIE_VDDC L26
L20 VDDR1 PCIE_VDDC M22 +0.95VSDGPU
L21 VDDR1 PCIE_VDDC N22 #(
L22 VDDR1 PCIE_VDDC N23 +PCIE_VDDC 2 1
%%) # # # VDDR1 PCIE_VDDC N24 RV364 0_0603_5%
CV54
CV55
CV56
CV57
CV58
CV59
CV60
CV120
CV121
PCIE_VDDC R22
PCIE_VDDC 1 1 1 1 1 1 1 1 1
T22
+1.8VGS # 5( LEVEL PCIE_VDDC U22 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
' ) LV3 DIS@ TRANSLATION PCIE_VDDC V22
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1 2 +VDD_CT AA20 PCIE_VDDC 2 2 2 2 2 2 2 2 2
BLM15BD121SN1D_0402 AA21 VDD_CT
AB20 VDD_CT AA15
CV61
CV62
CV63
B
AB21 VDD_CT CORE VDDC N15 B
1 1 1 VDD_CT VDDC
'#, ) " ) 0H N17
# 80 4,480 ,#80 , #80 DIS@ DIS@ DIS@ +3VGS VDDC R13
LV4 DIS@ 4 5( I/O VDDC R16
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 1 2 +VDDR3 AA17 VDDC R18
BLM15BD121SN1D_0402 AA18 VDDR3 VDDC Y21
# AB17 VDDR3 VDDC T12
CV64
CV65
CV66
CV123
AB18 VDDR3 VDDC T15 +VGA_CORE
1 1 1 1 VDDR3 VDDC T17
DIS@ DIS@ DIS@ DIS@ V12 VDDC T20
Y12 VDDR4 VDDC U13
CV67
CV68
CV69
CV70
CV71
CV72
CV73
CV74
CV75
CV76
CV77
CV78
CV79
CV80
10U_0402_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 2 U12 VDDR4 VDDC U16
'#,@ # 80 #80 ,#80 VDDR4 VDDC U18
1 1 1 1 1 1 1 1 1 1 1 1 1 1
VDDC V21 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
VDDC V15
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
VDDC V17 2 2 2 2 2 2 2 2 2 2 2 2 2 2
-") # # # VDDC V20
VDDC
POWER
Y13
VDDC Y16
VDDC Y18
%%) # # # VDDC AA12
VDDC M11
VDDC N12
VDDC U11
%%) # # # VDDC
CV101
CV104
CV100
CV106
CV103
CV109
CV102
CV107
CV108
CV105
+1.8VGS
LV6 DIS@ L 5( PLL
1 1 1 1 1 1 1 1 1 1
1 2 +MPLL_PVDD DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
B/ C BLM15BD221SN1D_2P
CV81
CV82
CV124
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 2 2 2 2 2 2 2
1 1 1
R21 @ 5(
DIS@ DIS@ DIS@ BIF_VDDC U21 +BIF_VDDC
) + # # # BIF_VDDC
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 L8
+1.8VGS MPLL_PVDD
C
LV7 DIS@ 9 5( C
'+ # # # 1 2 +SPLL_PVDD
ISOLATED
CORE I/O
BLM15BD121SN1D_0402 M13
CV84
CV85
CV86
H7 VDDCI M15
1 1 1 SPLL_PVDD VDDCI M16
CV111
CV114
CV110
CV117
CV113
CV118
CV112
CV116
CV119
CV115
' ) DIS@ DIS@ DIS@ VDDCI M17 1 1 1 1 1 1 1 1 1 1
+0.95VSDGPU VDDCI M18
# 5(
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2 LV8 DIS@ VDDCI M20 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
1 2 +SPLL_VDDC H8 VDDCI M21
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
BLM15BD121SN1D_0402 SPLL_VDDC VDDCI N20 2 2 2 2 2 2 2 2 2 2
CV91
CV92
CV93
J7 VDDCI
' # 80 #80 ,#80 1 1 1 SPLL_PVSS
DIS@ DIS@ DIS@
10U_0603_6.3V6M
0.1U_0402_10V6K
1U_0402_6.3V4Z
2 2 2
# 216-0842024-A11-MAR_FCBGA631
?
+0.95VSDGPU
+BIF_VDDC 2 1
RV31 0_0603_5%
+VGA_CORE
CV122
CV181
CV180
1 2 2
DIS@ DIS@ DIS@
CV88
CV89
CV90
CV87
CV125
CV126
CV127
1 1 1 1 1 1 1
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 1 1
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
10U_0603_6.3V6M
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 2 2 2 2 2 2
D D

Title
Issued Date 2016/12/01 Deciphered Date 2017/12/01 MESO_(4/5)_Power
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
Date: Friday, March 02, 2018
LA-F115P
Sheet 47 of 65
1 2 3 4 5
1 2 3 4 5
Main Func = GPU
M_DA[63..0]
<49,50> M_DA[63..0]
M0_MA[8..0]
<49> M0_MA[8..0]
Vinafix.com
A A
M1_MA[8..0]
<50> M1_MA[8..0] @
UV1C U?
GDDR5/DDR3 GDDR5/DDR3
M_DA0 K27 K17 M0_MA0
M_DA1 J29 DQA0_0 MAA0_0/MAA_0 J20 M0_MA1
M_DA2 H30 DQA0_1 MAA0_1/MAA_1 H23 M0_MA2
M_DA3 H32 DQA0_2 MAA0_2/MAA_2 G23 M0_MA3
M_DA4 G29 DQA0_3 MAA0_3/MAA_3 G24 M0_MA4
M_DA5 F28 DQA0_4 MAA0_4/MAA_4 H24 M0_MA5
M_DA6 F32 DQA0_5 MAA0_5/MAA_5 J19 M0_MA6
+1.35V_MEM_GFX +1.35V_MEM_GFX M_DA7 F30 DQA0_6 MAA0_6/MAA_6 K19 M0_MA7
M_DA8 C30 DQA0_7 MAA0_7/MAA_7 G20 M0_MA8
M_DA9 F27 DQA0_8 MAA0_8/MAA_13 L17
M_DA10 A28 DQA0_9 MAA0_9/MAA_15
DQA0_10
1
1
M_DA11 C28 J14 M1_MA0
M_DA12 E27 DQA0_11 MAA1_0/MAA_8 K14 M1_MA1
RV33 RV32 M_DA13 G26 DQA0_12 MAA1_1/MAA_9 J11 M1_MA2
40.2_0402_1% 40.2_0402_1% M_DA14 D26 DQA0_13 MAA1_2/MAA_10 J13 M1_MA3
DIS@ DIS@ M_DA15 F25 DQA0_14 MAA1_3/MAA_11 H11 M1_MA4
2
M_DA16 A25 DQA0_15 MAA1_4/MAA_12 G11 M1_MA5

+MVREFDA +MVREFSA M_DA17 C25 DQA0_16 MAA1_5/MAA_BA2 J16 M1_MA6
M_DA18 E25 DQA0_17 MAA1_6/MAA_BA0 L15 M1_MA7
M_DA19 D24 DQA0_18 MAA1_7/MAA_BA1 G14 M1_MA8
DQA0_19 MAA1_8/MAA_14
1
M_DA20 E23 L16
MEMORY INTERFACE
1 1 M_DA21 DQA0_20 MAA1_9/RSVD
F23
RV34 CV94 RV35 CV95 M_DA22 D22 DQA0_21 E32 M_WCKA0_0
100_0402_1% 1U_0402_6.3V4Z 100_0402_1% 1U_0402_6.3V4Z M_DA23 F21 DQA0_22 WCKA0_0/DQMA0_0 E30 M_WCKA0_0# M_WCKA0_0 <49>
DIS@ 2 DIS@ DIS@ 2 DIS@ M_DA24 E21 DQA0_23 WCKA0B_0/DQMA0_1 A21 M_WCKA0_1 M_WCKA0_0# <49>
2
M_DA25 D20 DQA0_24 WCKA0_1/DQMA0_2 C21 M_WCKA0_1# M_WCKA0_1 <49>

M_DA26 F19 DQA0_25 WCKA0B_1/DQMA0_3 E13 M_WCKA1_0 M_WCKA0_1# <49>
B M_DA27 A19 DQA0_26 WCKA1_0/DQMA1_0 D12 M_WCKA1_0# M_WCKA1_0 <50> B
M_DA28 D18 DQA0_27 WCKA1B_0/DQMA1_1 E3 M_WCKA1_1 M_WCKA1_0# <50>
M_DA29 F17 DQA0_28 WCKA1_1/DQMA1_2 F4 M_WCKA1_1# M_WCKA1_1 <50>
M_DA30 A17 DQA0_29 WCKA1B_1/DQMA1_3 M_WCKA1_1# <50>
M_DA31 C17 DQA0_30 H28 M_EDC_0
M_DA32 E17 DQA0_31 EDCA0_0/QSA0_0 C27 M_EDC_1 M_EDC_0 <49>
M_DA33 D16 DQA1_0 EDCA0_1/QSA0_1 A23 M_EDC_2 M_EDC_1 <49>
M_DA34 F15 DQA1_1 EDCA0_2/QSA0_2 E19 M_EDC_3 M_EDC_2 <49>
M_DA35 A15 DQA1_2 EDCA0_3/QSA0_3 E15 M_EDC_4 M_EDC_3 <49>
M_DA36 D14 DQA1_3 EDCA1_0/QSA1_0 D10 M_EDC_5 M_EDC_4 <50>
M_DA37 F13 DQA1_4 EDCA1_1/QSA1_1 D6 M_EDC_6 M_EDC_5 <50>
RV36 DIS@ RV37 DIS@ M_DA38 A13 DQA1_5 EDCA1_2/QSA1_2 G5 M_EDC_7 M_EDC_6 <50>
49.9_0402_1% 10_0402_1% M_DA39 C13 DQA1_6 EDCA1_3/QSA1_3 M_EDC_7 <50>
1 2 2 1 DRAM_RST_G M_DA40 E11 DQA1_7 H27 M_DBI0#
<49,50> DRAM_RST M_DA41 A11 DQA1_8 DDBIA0_0/QSA0_0B A27 M_DBI1# M_DBI0# <49>
M_DA42 C11 DQA1_9 DDBIA0_1/QSA0_1B C23 M_DBI2# M_DBI1# <49>
DQA1_10 DDBIA0_2/QSA0_2B M_DBI2# <49>
1
M_DA43 F11 C19 M_DBI3#

1 1 M_DA44 DQA1_11 DDBIA0_3/QSA0_3B M_DBI4# M_DBI3# <49>
@ A9 C15
CV96 RV38 CV97 M_DA45 C9 DQA1_12 DDBIA1_0/QSA1_0B E9 M_DBI5# M_DBI4# <50>
120P_0402_50V8J 5.1K_0402_1% 68P_0402_50V8J M_DA46 F9 DQA1_13 DDBIA1_1/QSA1_1B C5 M_DBI6# M_DBI5# <50>
DIS@ 2 DIS@ 2 M_DA47 D8 DQA1_14 DDBIA1_2/QSA1_2B H4 M_DBI7# M_DBI6# <50>
2
M_DA48 E7 DQA1_15 DDBIA1_3/QSA1_3B M_DBI7# <50>

M_DA49 A7 DQA1_16 L18 M_ADBI0
M_DA50 C7 DQA1_17 ADBIA0/ODTA0 K16 M_ADBI1 M_ADBI0 <49>
M_DA51 F7 DQA1_18 ADBIA1/ODTA1 M_ADBI1 <50>
M_DA52 A5 DQA1_19 H26 M_CLK0
M_DA53 E5 DQA1_20 CLKA0 H25 M_CLK#0 M_CLK0 <49>
M_DA54 C3 DQA1_21 CLKA0B M_CLK#0 <49>
M_DA55 E1 DQA1_22 G9 M_CLK1
=#7/ 7= ?/ 0 @ )< 0; , 3 ..* M_DA56 G7 DQA1_23 CLKA1 H9 M_CLK#1 M_CLK1 <50>
#,% -=#7/ 7 .- ,./,0 7= ?/ 0 /#7; 0;/$ M_DA57 G6 DQA1_24 CLKA1B M_CLK#1 <50>
M_DA58 G1 DQA1_25 G22 M_RAS#0
M_DA59 G3 DQA1_26 RASA0B G17 M_RAS#1 M_RAS#0 <49>
M_DA60 J6 DQA1_27 RASA1B M_RAS#1 <50>
M_DA61 J1 DQA1_28 G19 M_CAS#0
C C
M_DA62 J3 DQA1_29 CASA0B G16 M_CAS#1 M_CAS#0 <49>
M_DA63 J5 DQA1_30 CASA1B M_CAS#1 <50>
DQA1_31 H22 M_CS0B#0
+MVREFDA K26 CSA0B_0 J22 M_CS0B#0 <49>
+MVREFSA J26 MVREFDA CSA0B_1
MVREFSA G13 M_CS1B#0
J25 CSA1B_0 K13 M_CS1B#0 <50>
RV39 1 DIS@ 2 120_0402_1% K25 NC#J25 CSA1B_1
MEM_CALRP0 K20 M_CKE0
CKEA0 J17 M_CKE1 M_CKE0 <49>
CKEA1 M_CKE1 <50>
G25 M_WE#0
DRAM_RST_G L10 WEA0B H10 M_WE#1 M_WE#0 <49>
DRAM_RST WEA1B M_WE#1 <50>
RV40 @ 1 2 51.1_0402_1% CV98 @1 2 0.1U_0402_16V4Z K8
RV41 @ 1 2 51.1_0402_1% CV99 @1 2 0.1U_0402_16V4Z L7 CLKTESTA
CLKTESTB
& :0/ ;.? ? ,>=/ /,%/% ;. % D D #,% //- ? ; $0

216-0842024-A11-MAR_FCBGA631
%/":> ,=25 D $ 7= 7 "?/$E#0 ,5 D , 0 ,//%5 ( ?
D D

Title
Issued Date 2016/12/01 Deciphered Date 2017/12/01 MESO_(5/5)_MEM
Date:
LA-F115P
1 2 3 4 5
5 4 3 2 1
Main Func = GDDR5
M_DA[0..31]
Vinafix.com UV13 @ MF=0
MF=0 MF=1 MF=1 MF=0
<48> M_DA[0..31]
A4 M_DA2
M_EDC_0 C2 DQ24 DQ0 A2 M_DA0
<48> M_EDC_0 M_EDC_1 EDC0 EDC3 DQ25 DQ1 M_DA3
C13 B4
R13 L B2
R2 E4 L
+1.35V_MEM_GFX <48> M_EDC_2 EDC3 EDC0 BYTE0 DQ28 DQ4 E2 M_DA7
DQ29 DQ5 F4 M_DA5 BYTE0
D M_DBI0# DQ30 DQ6 M_DA4 D
D2 F2
<48> M_DBI0# M_DBI1# DBI0# DBI3# DQ31 DQ7 M_DA15
VRAMX32@ D13 A11
M_CLK0 <48> M_DBI1# M_DBI3# DBI1# DBI2# DQ16 DQ8 M_DA13
1 2 P13 A13
RV79 60.4_0402_1% P2 B11
<48> M_DBI2# DBI3# DBI0# DQ18 DQ10 M_DA9
B13 L
M_CLK0 J12 DQ19 DQ11 E11 M_DA10
VRAMX32@
<48> M_CLK0 M_CLK#0 J11 CK DQ20 DQ12 E13 M_DA12 BYTE1
M_CLK#0 <48> M_CLK#0 M_CKE0 CK# DQ21 DQ13 M_DA8
1 2 J3 F11
<48> M_CKE0 CKE# DQ22 DQ14 M_DA14
RV370 60.4_0402_1% F13
DQ23 DQ15 U11 M_DA30
M0_MA2 H11 DQ8 DQ16 U13 M_DA28
<48> M0_MA2 M0_MA5 BA0/A2 BA2/A4 DQ9 DQ17 M_DA31
K10 T11
K11 H T13
H10 N11 H
<48> M0_MA3 BA3/A3 BA1/A5 BYTE2 DQ12 DQ20 N13 M_DA26
DQ13 DQ21 M11 M_DA24 BYTE3
M0_MA7 K4 DQ14 DQ22 M13 M_DA25 RV131
<48> M0_MA7 M0_MA1 A8/A7 A10/A0 DQ15 DQ23 M_DA19
H5 U4
RV79 H4 U2 SD034100180
K5 T4
SD00000FU80 J5 T2 H VRAMX16@
<48> M0_MA8 A12/RFU/NC DQ3 DQ27 M_DA18
N4
VRAMX16@ A5 DQ4 DQ28 N2 M_DA21 BYTE2
VPP/NC DQ5 DQ29 M_DA16
1K_0402_1%
U5 M4
VPP/NC DQ6 DQ30 M2 M_DA23 RV133
S RES 1/16W 120 +-1% 0402 DQ7 DQ31
RV134 2 DIS@ 1 1K_0402_1% J1 +1.35V_MEM_GFX SD034100180
RV370 RV135 2 DIS@ 1 1K_0402_1% J10 MF
RV123 2 DIS@ 1 121_0402_1% J13 SEN B1 VRAMX16@
ZQ VDDQ D1
SD00000FU80 VDDQ F1 1K_0402_1%
VRAMX16@ M_ADBI0 J4 VDDQ M1
<48> M_ADBI0 M_RAS#0 ABI# VDDQ
G3 P1 RV132
<48> M_RAS#0 M_CS0B#0 RAS# CAS# VDDQ
S RES 1/16W 120 +-1% 0402 G12 T1
<48> M_CS0B#0 M_CAS#0 CS# WE# VDDQ
L3 G2 SD034121090
<48> M_CAS#0 M_WE#0 CAS# RAS# VDDQ
L12 L2
<48> M_WE#0 WE# CS# VDDQ
C B3 VRAMX16@ C
VDDQ D3
VDDQ F3
M_WCKA0_0# VDDQ 121_0402_1%
D5 H3
<48> M_WCKA0_0# M_WCKA0_0 WCK01# WCK23# VDDQ
D4 L K3
<48> M_WCKA0_0 WCK01 WCK23 VDDQ M3
M_WCKA0_1# P5 VDDQ P3
<48> M_WCKA0_1# M_WCKA0_1 WCK23# H WCK01# VDDQ
+1.35V_MEM_GFX P4 T3
<48> M_WCKA0_1 WCK23 WCK01 VDDQ E5
VDDQ N5
+FB0_VREFDL VDDQ
2.37K_0402_1%
A10 E10
VREFD VDDQ
1
U10 N10
+FB0_VREFCL VREFD VDDQ
RV52 DIS@
J14 B12
VREFC VDDQ D12
VDDQ F12
VDDQ H12
2
DRAM_RST J2 VDDQ K12

<48,50> DRAM_RST RESET# VDDQ M12
+FB0_VREFDL VDDQ P12
VDDQ T12
VDDQ
1U_0402_6.3V6K
5.49K_0402_1%
G13
VDDQ
1
1 H1 L13
VSS VDDQ
CV394 DIS@
RV53 DIS@
K1 B14
B5 VSS VDDQ D14
G5 VSS VDDQ F14
2 L5 VSS VDDQ M14
2
T5 VSS VDDQ P14

B10 VSS VDDQ T14
D10 VSS VDDQ
G10 VSS
L10 VSS A1
P10 VSS VSSQ C1
T10 VSS VSSQ E1
+1.35V_MEM_GFX H14 VSS VSSQ N1
K14 VSS VSSQ R1
+1.35V_MEM_GFX VSS VSSQ U1
VSSQ
2.37K_0402_1%
H2
1
G1 VSSQ K2
B VDD VSSQ B
RV54 DIS@
L1 A3
G4 VDD VSSQ C3
L4 VDD VSSQ E3
C5 VDD VSSQ N3
2
R5 VDD VSSQ R3
C10 VDD VSSQ U3
+FB0_VREFCL R10 VDD VSSQ C4 +1.35V_MEM_GFX
D11 VDD VSSQ R4
VDD VSSQ
1U_0402_6.3V6K
5.49K_0402_1%
G11 F5
1
L11 VDD VSSQ M5

1 VDD VSSQ
CV395 DIS@
RV55 DIS@
P11 F10
CV198
CV213
CV230
CV235
CV233
CV210
CV211
CV157
CV155
CV158
G14 VDD VSSQ M10
VDD VSSQ 1 1 1 1 1 1 1 1 1 1
L14 C11
2 VDD VSSQ R11
2
VSSQ A12
VSSQ C12 2 2 2 2 2 2 2 2 2 2
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
VSSQ E12 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
VSSQ N12
VSSQ R12
170-BALL VSSQ U12
VSSQ H13
SGRAM GDDR5 VSSQ K13
VSSQ A14
VSSQ C14
VSSQ E14
VSSQ N14
VSSQ R14
0 07; ,> #-? D $ ? >,#= ? 0 ;#0 ;#E/ # 7;#,>/ D $ /D /$ /,7/ -= #,/ E =0 #>/
VSSQ U14 %% ?0 07; ,> 7#-? <;/, $ /K: $ /%5 ,/ 7#- -/$ 0 ;$ // ? >,#= ?
VSSQ
H5GC4H24AJR-R0C_BGA170
+1.35V_MEM_GFX
CV238
CV248
CV243
CV242
CV247
CV342
CV344
CV343
CV341
A A
1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

MESO_GDDR5_A0
5 4 3 2 1
5 4 3 2 1
Main Func = GDDR5
<48> M_DA[32..63]
M_DA[32..63]
Vinafix.com
UV15 @ MF=0
MF=0 MF=1 MF=1 MF=0
A4 M_DA38
M_EDC_4 C2 DQ24 DQ0 A2 M_DA37
+1.35V_MEM_GFX <48> M_EDC_4 M_EDC_5 EDC0 EDC3 DQ25 DQ1 M_DA36
D
C13 B4 D
R13 B2 L
R2 E4
<48> M_EDC_6 EDC3 EDC0 DQ28 DQ4 E2 M_DA35 BYTE4
VRAMX32@ DQ29 DQ5 F4 M_DA32
1 2 M_CLK1 M_DBI4# D2 DQ30 DQ6 F2 M_DA34
RV85 60.4_0402_1% D13 A11
P13 A13
VRAMX32@ P2 B11
M_CLK#1 <48> M_DBI6# DBI3# DBI0# DQ18 DQ10 M_DA42
1 2 B13 L
RV86 60.4_0402_1% M_CLK1 J12 DQ19 DQ11 E11 M_DA44
<48> M_CLK1 M_CLK#1 J11 CK DQ20 DQ12 E13 M_DA45 BYTE5
<48> M_CLK#1 M_CKE1 CK# DQ21 DQ13 M_DA46
J3 F11
<48> M_CKE1 CKE# DQ22 DQ14 M_DA47
F13
DQ23 DQ15 U11 M_DA62
M1_MA2 H11 DQ8 DQ16 U13 M_DA61
RV85 K10 T11
K11 T13 H
SD00000FU80 H10 N11
<48> M1_MA3 BA3/A3 BA1/A5 DQ12 DQ20 N13 M_DA58 BYTE7
VRAMX16@ DQ13 DQ21 M11 M_DA56
M1_MA7 K4 DQ14 DQ22 M13 M_DA59
S RES 1/16W 120 +-1% 0402 H5 U4
H4 U2
K5 T4 RV117
RV86 J5 T2 H
<48> M1_MA8 A12/RFU/NC DQ3 DQ27 M_DA54
N4 SD034100180
A5 DQ4 DQ28 N2 M_DA50 BYTE6
SD00000FU80 VPP/NC DQ5 DQ29 M_DA53
U5 M4 VRAMX16@
VRAMX16@ VPP/NC DQ6 DQ30 M2 M_DA49
DQ7 DQ31
1K_0402_1%
S RES 1/16W 120 +-1% 0402 RV117 2 DIS@ 1 1K_0402_1% J1 +1.35V_MEM_GFX
RV119 2 DIS@ 1 1K_0402_1% J10 MF RV119
RV121 2 DIS@ 1 121_0402_1% J13 SEN B1
ZQ VDDQ D1
VDDQ SD034100180
F1
M_ADBI1 J4 VDDQ M1 VRAMX16@
<48> M_ADBI1 M_RAS#1 ABI# VDDQ
C G3 P1 C
<48> M_RAS#1 M_CS1B#0 RAS# CAS# VDDQ
G12 T1 1K_0402_1%
<48> M_CS1B#0 M_CAS#1 CS# WE# VDDQ
L3 G2
<48> M_CAS#1 M_WE#1 CAS# RAS# VDDQ
L12 L2 RV121
<48> M_WE#1 WE# CS# VDDQ
+1.35V_MEM_GFX B3
VDDQ D3
VDDQ SD034121090
F3
M_WCKA1_0# D5 VDDQ H3 VRAMX16@
2.37K_0402_1%
D4 K3
<48> M_WCKA1_0 WCK01 WCK23 VDDQ
1
M3 121_0402_1%
M_WCKA1_1# VDDQ
RV48 DIS@
P5 P3
P4 T3
<48> M_WCKA1_1 WCK23 WCK01 VDDQ E5
VDDQ N5
2
+FB1_VREFDL A10 VDDQ E10

+FB1_VREFDL U10 VREFD VDDQ N10
+FB1_VREFCL J14 VREFD VDDQ B12
VREFC VDDQ
1U_0402_6.3V6K
5.49K_0402_1%
D12
VDDQ
1
1 F12
VDDQ
CV390 DIS@
RV49 DIS@
H12
DRAM_RST J2 VDDQ K12
<48,49> DRAM_RST RESET# VDDQ M12
2 VDDQ P12
2
VDDQ T12
VDDQ G13
H1 VDDQ L13
K1 VSS VDDQ B14
B5 VSS VDDQ D14
G5 VSS VDDQ F14
L5 VSS VDDQ M14
+1.35V_MEM_GFX T5 VSS VDDQ P14
B10 VSS VDDQ T14
D10 VSS VDDQ
VSS
2.37K_0402_1%
G10
VSS
1
L10 A1
VSS VSSQ
RV50 DIS@
P10 C1
T10 VSS VSSQ E1
H14 VSS VSSQ N1
B VSS VSSQ B
K14 R1
2
+1.35V_MEM_GFX VSS VSSQ U1

VSSQ H2
+FB1_VREFCL G1 VSSQ K2
L1 VDD VSSQ A3
VDD VSSQ
1U_0402_6.3V6K
5.49K_0402_1%
G4 C3
VDD VSSQ
1
1 L4 E3
VDD VSSQ
CV391 DIS@
RV51 DIS@
C5 N3 +1.35V_MEM_GFX
R5 VDD VSSQ R3
C10 VDD VSSQ U3
2 R10 VDD VSSQ C4
2
D11 VDD VSSQ R4

CV162
CV166
CV216
CV221
CV219
CV165
CV164
CV161
CV153
CV160
G11 VDD VSSQ F5
VDD VSSQ 1 1 1 1 1 1 1 1 1 1
L11 M5
P11 VDD VSSQ F10
G14 VDD VSSQ M10
L14 VDD VSSQ C11 2 2 2 2 2 2 2 2 2 2
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
VDD VSSQ R11
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
VSSQ A12
VSSQ C12
VSSQ E12
VSSQ N12
VSSQ R12
170-BALL VSSQ U12
VSSQ H13
SGRAM GDDR5 VSSQ K13
VSSQ A14
VSSQ C14
0 07; ,> #-? D $ ? >,#= ? 0 ;#0 ;#E/ # 7;#,>/ D $ /D /$ /,7/ -= #,/ E =0 #>/
VSSQ E14 %% ?0 07; ,> 7#-? <;/, $ /K: $ /%5 ,/ 7#- -/$ 0 ;$ // ? >,#= ?
VSSQ N14
+1.35V_MEM_GFX VSSQ R14
VSSQ U14
VSSQ
H5GC4H24AJR-R0C_BGA170
CV225
CV227
CV170
CV169
CV173
CV335
CV334
CV336
CV333
A 1 1 1 1 1 1 1 1 1 A
2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@

MESO_GDDR5_A1
5 4 3 2 1
5
Vinafix.com 4 3 2 1
Power-Up/Down Sequence 1. All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
preferred. The maximum slew rate on all rails is 50 mV/ s. samsung 4G samsung 2G samsung 2G
2. It is recommended that the 3.3-V rail ramp up first. UV12 UV14
UV13 UV13
3. It is recommended that the 0.95-V rail reach at least 90% of its nominal value UV12 UV14 SA00009TT1L SA00009TT1L
no later than 2 ms from the start of VDDC ramping up. SA000092D1L SA00009TA1L
SA000092D1L SA000092D1L S2G_R3@ S2G_R3@
4. The power rails that are shared with other components on the system should be SX32_1_R3@ SX32_2_R3@
S4G_R3@ S4G_R3@ S IC D5 128M32 K4G41325FE-HC28 FBGA A31! S IC D5 128M32 K4G41325FE-HC28 FBGA A31!
gated for the dGPU so that when the dGPU is powered down (for example S IC D5 256M32 K4G80325FB-HC28 FBGA A31! S IC D5 256M32 K4G80325FB-HC25 FBGA A31!
AMD PowerXpress? idle state), all the power rails are removed from the dGPU. S IC D5 256M32 K4G80325FB-HC28 FBGA A31! S IC D5 256M32 K4G80325FB-HC28 FBGA A31!
The gate circuits must meet the slew rate requirement (such as ? 50 mV/ s).
UV13 UV15
5. VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC UV13 UV15 UV15 UV15
D D
should reach 90% before VDD_CT starts to ramp up (or vice versa). SA00009TT1L SA00009TT1L
SA000092D1L SA000092D1L SA000092D1L SA00009TA1L
S2G_R3@ S2G_R3@
6. For power down, reversing the ramp-up sequence is recommended. S4G_R3@ S4G_R3@ SX32_1_R3@ SX32_2_R3@
S IC D5 128M32 K4G41325FE-HC28 FBGA A31! S IC D5 128M32 K4G41325FE-HC28 FBGA A31!
S IC D5 256M32 K4G80325FB-HC28 FBGA A31! S IC D5 256M32 K4G80325FB-HC28 FBGA A31! S IC D5 256M32 K4G80325FB-HC28 FBGA A31! S IC D5 256M32 K4G80325FB-HC25 FBGA A31!
< 20mS < 20mS

Hynix 4G Hynix 2G Hynix 2G
UV12 UV14
VDDR3(3.3V) >10uS
UV12 UV14 UV13 UV13
+3VGS SA00008HQ1L SA00008HQ1L
(DGPU_PWR_EN) SA00009U11L SA00009U11L SA00009U11L SA00009TM1L
H2G_R3@ H2G_R3@
H4G_R3@ H4G_R3@ HX32_1_R3@ HX32_2_R3@
PCIE_VDDC(0.95V) S IC D5 128M32/3G H5GC4H24AJR-R0C A31! S IC D5 128M32/3G H5GC4H24AJR-R0C A31!
+0.95VSDGPU S IC D5 256M32 H5GC8H24MJR-R0C BGA A31! S IC D5 256M32 H5GC8H24MJR-R0C BGA A31! S IC D5 256M32 H5GC8H24MJR-R0C BGA A31! S IC D5 256M32 H5GQ8H24MJR-R4C BGA A31!
(DGPU_PWR_EN with RC delay)
UV13 UV15
1.8V_IO(1.8V) UV13 UV15 UV15 UV15
+1.8VGS SA00008HQ1L SA00008HQ1L
(DGPU_PWR_EN with RC delay) SA00009U11L SA00009U11L SA00009U11L SA00009TM1L
H2G_R3@ H2G_R3@
H4G_R3@ H4G_R3@ HX32_1_R3@ HX32_2_R3@
VDDC/VDDCI(0.8~1.15V) S IC D5 128M32/3G H5GC4H24AJR-R0C A31! S IC D5 128M32/3G H5GC4H24AJR-R0C A31!
+VGA_CORE S IC D5 256M32 H5GC8H24MJR-R0C BGA A31! S IC D5 256M32 H5GC8H24MJR-R0C BGA A31! S IC D5 256M32 H5GC8H24MJR-R0C BGA A31! S IC D5 256M32 H5GQ8H24MJR-R4C BGA A31!
(DGPU_PWR_EN)
VMEMIO(1.35V or 1.5V)
+1.35V_MEM_GFX > 100mS > 100mS (SW)
(DGPU_PWROK with RC delay) Micron 4G Micron 2G Micron 2G
PWRGOOD
DGPU_PWROK UV12 UV14 UV12 UV14
UV13 UV13
C C
SA00009TV1L SA00009TV1L SA00009E31L SA00009E31L
> 100uS
SA00009TV1L SA00009TI1L
PERSTb M4G_R3@ M4G_R3@ M2G_R3@ M2G_R3@
PLT_RST_VGA# MX32_1_R3@ MX32_2_R3@
Asserted Before PERSTb S IC D5 256M32 MT51J256M32HF-70:A A31! S IC D5 256M32 MT51J256M32HF-70:A A31! S IC D5 128M32 EDW4032BABG-70-F-R A31! S IC D5 128M32 EDW4032BABG-70-F-R A31!
S IC D5 256M32 MT51J256M32HF-70:A A31! S IC D5 256M32 MT51J256M32HF-80:A A31!
REFCLK UV13 UV15
CLK_PEG_VGA/CLK_PEG_VGA# UV13 UV15 UV15 UV15
SA00009E31L SA00009E31L
SA00009TV1L SA00009TV1L SA00009TV1L SA00009TI1L
Device in Device Hardware Reset Device CFG Accessible Device Powering down Device Powered down M2G_R3@ M2G_R3@
DEVICE Reset or Working
M4G_R3@ M4G_R3@ MX32_1_R3@ MX32_2_R3@
S IC D5 128M32 EDW4032BABG-70-F-R A31! S IC D5 128M32 EDW4032BABG-70-F-R A31!
S IC D5 256M32 MT51J256M32HF-70:A A31! S IC D5 256M32 MT51J256M32HF-70:A A31! S IC D5 256M32 MT51J256M32HF-70:A A31! S IC D5 256M32 MT51J256M32HF-80:A A31!
No requirements
New Micron 2G
UV12 UV14
SA00007UZ1L SA00007UZ1L
MNew2G_R3@ MNew2G_R3@
LAF115 VRAM x16*4pcs S IC D5 128M32 EDW4032BABG-60-F-R A31! S IC D5 128M32 EDW4032BABG-60-F-R A31!

LAF116 VRAM x32*2pcs
UV13 UV15
SA00007UZ1L SA00007UZ1L
MNew2G_R3@ MNew2G_R3@
@ 8 PCH_PLTRST#
PCH_PLTRST#_EC
@ S IC D5 128M32 EDW4032BABG-60-F-R A31! S IC D5 128M32 EDW4032BABG-60-F-R A31! B
@ PLT_RST_VGA# &
@
@ 8 DGPU_HOLD_RST#
@ 8 DGPU_PWR_EN
@ 8 DGPU_PWRO K
5 ;- < / 2 ? 8 O Samsung 2G Hynix 2G Micron 2G
RV16 2G_S@ RV15 2G_H@ RV16 2G_H@ RV15 2G_M@

B @ 3 3 @ 3 A 3 @ S 3@
' '@
AR A2, F 3 3 @A @ A3 4& & S 3@
DGPU_PWR_EN#
LDO # B 7$ , 3 3 9 3 @ & S 3@ 4.75K_0402_1% 3.4K_0402_1% 10K_0402_1% 4.75K_0402_1%
SD034475180 SD034340180 SD034100280 SD034475180
( '8 & (B ' @ ( '8 & ( '@ Samsung 4G Hynix 4G Micron 4G

LDO 4 LDO 4 5 ;- @ < / 2 ? 8 O
DGPU_PWR_EN# DGPU_PWR_EN# RV16 4G_S@ RV15 4G_H@ RV16 4G_H@ RV15 4G_M@
B3 @ 3 ! 3 @ 3 A 3 @ S @
'@ 8 & ( '8 8@ 6
A PWM PWM B A2, F 3 ! 3A @ A3 4& & @ S @ 4.75K_0402_1% 3.4K_0402_1% 10K_0402_1% 4.75K_0402_1% A
DGPU_PWR_EN# DGPU_PWRO K
SD034475180 SD034340180 SD034100280 SD034475180
B ' 7$ , 3 ! 3 43 ! 3A S @

MESO_Note
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
C C
B B
A A

= >
5 4 3 2 1
A B C D
@ PJP1
Main Func = DCIN/BATT CONN 1
1 2
2
JUMP_43X79
' )-/ PSID@ PQ1
FDV301N-G_SOT23-3
EMI@ PL1 PSID@ PR1
@ PJPDC1 5A Z150 20M 1210_2P 1 3 33_0402_5%
S
D
+19V_ADPIN 1 2 PSID-3 1 2 PS_ID <25>
8
GND 7
GND
1
1000P_0402_50V7K
2200P_0402_25V7K
1000P_0402_50V7K
2200P_0402_25V7K
10P_0402_25V8J
82P_0402_50V8J
G
6 PSID@ PR4 PR5 PSID@
2
6
100K_0402_1%
1
1
TVNST52302AB0_SOT523-3
5 10K_0402_1% 2.2K_0402_5%
5
Vinafix.com
PSID@ PR3
EMI@ PC1
EMI@ PC2
EMI@ PC3
EMI@ PC4
4 2 1
@RF@ PC15
Mad@RF@ PC16
4
' (%
3
3
2
3
ESD@ PD1
2
2
MMST3904-7-F_SOT323-3
1 1 2
2
1
' (%
1
@EMI@ PL2 C
1 1
PQ2
5A Z150 20M 1210_2P PSID-1 2
ACES_50458-00601-001 B
1
@PJP2 E @ PR7
3
1
PR6 PSID@
1 2 3
PSID@
100K_0402_1%
15K_0402_1%
1 2 1 2 1 ' (%
JUMP_43X79 EMI@ PL3 2
BLM15AG102SN1D_2P
1
PSID 1 2 @ PD2
2
@ PD3 BAV99W_SC70-3
BAV99W_SC70-3
3
PD4
S SCH DIO 5A 100V 15UA 0.88V TO227-3
2
1
3
' )-/
' (%
S1 S2
)( ) -/
) ! )-/
PQ3 PQ4
AON7409_DFN8-5 ' )-/) AON7409_DFN8-5
1 1
' )-/ ' , )( ) -/ 2
3 5 5
2
3 ' )-/
' , )( ) -/
1
% L )
0.022U_0603_50V7K
0.022U_0603_50V7K
DFLS160-7_POWERDI123-2
3
S
PU1 PR47
4
1
1
' , )( ) -/ 2
G
' ,
1M_0402_5%
1M_0402_5%
RT9069-33GB_SOT23-5 300K_0402_5%
' ,
1
PR8
PC6
1 5
PC5
VCC OUT
AC_B2B_S2_SW
PR9
PD12
Loki@ PR52
2
AO3409_SOT23-3
2 PR50 0_0402_5%
1000P_0603_50V7K
AC_B2B_S2_G
2
2
GND AC_B2B_S2_B HW_ACAVIN_NB
PQ19
D
100K_0402_5% @ PR60 2 1
1
1
1
3 4 100K_0402_5%
2
NC EN
1
1
D
PC8
2 Loki@ PR13 PR14 @ @ PR51 2
2
3
1
PC9 Mad@ 100K_0402_5% 10K_0402_5% 2 AC_B2B_S2_A 0_0402_5%
PD11 G 2 1 AC_B2B_S2
2.2U_0402_10V6M
2
LRB715FT1G_SOT323-3 PD10 S PQ17
3
LRB715FT1G_SOT323-3 PR48 2N7002KW_SOT323-3
1
2 D
PR61 100K_0402_5%
2
1
100K_0402_5% 1 PR11 2 2 1 PWR_SELECT2
<54,55> AC_OK
1
1 2 3 510K_0402_5% PR12 G
PWR_SE1 PR10 1M_0402_5% PQ18 S Mad@ PR49
3
1
1M_0402_5% 2N7002KW_SOT323-3 0_0402_5%
2
1
1
Mad@
2N7002KDW_SOT363-6
1
PR63 Loki@ PR15 PR16 (Barrel -> H / Type C -> L)
3
1
D
PR62 100K_0402_5% 12K_0402_1% 100K_0402_5% @ PC23
15K_0402_5% AC_B2B_S2 2 0.1U_0402_10V7K
2
2
PQS30B
PR2 G PQ6
AC_B2B_ACOK
2
1
D
Mad@
5 0_0402_5% 2N7002KW_SOT323-3
2N7002KDW_SOT363-6
S
PWR_SE2 <54>
3
1 2AC_B2B_S1_A 2 PQ5
6
1
G 2N7002KW_SOT323-3
4
1
S PR17 PC10
3
' , )( ) -/
PQS30A
1M_0402_5%
56K_0402_5% 0.1U_0402_50V7K
1
Mad@
PR100
2
' (% )" % L ) PC7 asserts H_PROCHOT# when TypeC is
2
0.1U_0402_50V7K
unplugged, keep low for 10ms
1
2
1
till SW PROCHOT# is issued by EC

0.1U_0402_10V7K
PR22 H_PROCHOT#
2N7002KW_SOT323-3
' (%
1
Mad@ PC21
' ) !
10K_0402_1%
100K_0402_5%
1
1
Mad@
2
1
PRS28
PR64
3
AC_B2B_S1 2
PQ16
100K_0402_5% @ 2N7002KW_SOT323-3 PCS19
2N7002KDW_SOT363-6
2
1
D
Mad@ PR21 G PQ20 LPS@ .1U_0402_16V7K
2
PQS10B
PR65 100K_0402_5% S 2
AC_DIS1 <55>
3
2
5
0_0402_5% G AC_B2B_S1 PRS26 USBC_SW_PROCHOT

1 2 5
2
2 1 PWR_SELECT1 1 D
S 1M_0402_1%
P
<25> PWR_SELECT
3
IN1
1
6
4 2 (Barrel -> H / Type C -> L) @ PCS20
2N7002KDW_SOT363-6
4
O
1
(Barrel -> H / Type C -> L) 2 G PC22 .1U_0402_16V7K
<25,55> HW_ACAVIN_NB
2
IN2
G
1
1
D
PQS10A
Mad@ 0.1U_0402_10V7K @ PRS29
PWR_SELECT2
S
3
PR66 Mad@ PU2 PQ15 USBC_SW_PROCHOT 1 2 2 PQS11 2 100K_0402_1%

3 3
3
1M_0402_1% SN74AHC1G08DCKR_SC70-5 2N7002KW_SOT323-3 G 2N7002KW_SOT323-3
2
@ S
2
PRS30 PRS27
2
100K_0402_1% 1M_0402_1%
Loki@ PR46
0_0402_5%
1
1 2
'#9, )!(++'
1
@ PJP3
2
'#9, )!(++'' Other component (37.1)
+17.4V_BATT+
1 2
JUMP_43X79
(2 1 ! ; 1 ' )-/
EMI@ PL4 if battery removed, adaptor only, asserts H_PROCHOT# when adaptor is " $ 8
5A Z150 20M 1210_2P
1 2 +17.4V_BATT++ then trigger the H_PROCHOT#, unplugged, keep low for 10ms
keep @ in BOM since battery can not till SW PROCHOT# is issued by EC @ PR31
1000P_0402_50V7K
3.3K_1206_5%
1
1
be removed by end user H_PROCHOT#
<11,25,54,55> HW_ACAV_IN 0_0402_5%
82P_0402_50V8J
0.1U_0402_25V7K
0.01U_0402_25V7K
' (%
1
1
1 2
EMI@ PC11
@ PR32
' )-/
10K_0402_1%
ESD@ PD5 ESD@ PD6
1
1
Mad@RF@ PC17
EMI@ PC12
Mad@RF@ PC18
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
PR33
@ PR34
! ; ! 2 <12,25,55,60> H_PROCHOT#
2
3
PC13 1M_0402_1%
2N7002KDW_SOT363-6
2
3 2
.1U_0402_16V7K @ PR35
2
2
1
PQ12B
0_0402_5%
2N7002KDW_SOT363-6
-/# /
2
PBAT_PRES# <25,55> PR36 AC_SW_PROCHOT
1 2 5 1 2
@ PQ13B
-/4 / 1M_0402_1%
6
POK <11,25,38,56,58,59> 5
2N7002KDW_SOT363-6
-/ /
4
1
6
@ PBATT1 PC14
2N7002KDW_SOT363-6
2
1
PQ12A
1 .1U_0402_16V7K PR40
-/ D ) "
4
1
1
@ PQ13A
2 2 100K_0402_1%
2
-/ !(++) 3
3 PR39 PR41 PBAT_PRES# 1 2 2 PQ11 2 @ PR38
' (%
2
4 SYS_PRES PR37 200_0402_5% 10K_0402_1% G 1M_0402_1%
2N7002KW_SOT323-3
-/$ (+) !
2
4
1
5 1 2 1 2
100K_0402_1%
100_0402_5% S PR44
3
2
5
1
DAT_SMB
-/9 % ) ! 6
6
7 CLK_SMB
1
1
2
2
1M_0402_1% @ PR45
PR43
1M_0402_1%
4
-/@ ! ' 7 8 4
1
8 9
-/L ! ' PR42
2
9 10 100_0402_5%
2
-/# ! ' 10
GND
11
PBAT_CHG_SMBCLK <25,55>
12
4# #444 GND
ACES_50458-01001-P01_10P-T
( " ) @& # #& #)# &+ PBAT_CHG_SMBDAT <25,55>
DELL CONFIDENTIAL/PROPRIETARY
PWR_DCIN/BATT CONN
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS X00
A B C D
A B C D
Main Func = Type-C PD Selector

DCIN_AC_Detector
@ PCS01
0.01U_0402_25V7K~D ' , )( ) -/
1 2
' )-/ ' , )( ) -/ % L )
2
2 PRS44 Loki@
0_0402_5%
' , )( ) -/ 1 Mad@ PRS43
0_0402_5%
Vinafix.com
1
3 1 2
' , ) ! )-/ PDS01

4 BAT54CW_SOT323-3 PRS01 4
1.8M_0402_1%
1
1 2 Type@ PDS02
240K_0402_1%
1
PRS02 S SCH DIO 5A 100V 15UA 0.88V TO227-3

102K_0402_1%
2
PRS03
1K_0402_1%
1
LM393_P
PRS04
2
2
PUS01A
EMI Part
8
AS393MMTR-G1_MSOP8 PRS39
3 0_0402_5% Type@EMI@ PLS11 ' ) ! )# Type@
' ! ) ) Type@
P
(>17.6V) + 1 1 2 5A_Z120_25M_0805_2P PQS01 PQS02
2 O HW_ACAVIN_NB <25,53,54,55> 1 2 AON7409_DFN8-5 AON7409_DFN8-5
-
G
1 1
1 2 2 2
' ) ! ' )-/
1200P_0402_50V7K
100P_0402_50V8J~D
220P_0402_50V8J~D
4
Type@EMI@ PLS12 3 5 5 3
23.2K_0402_1%
84.5K_0402_1%
1
1
5A_Z120_25M_0805_2P
PCS02
PCS03
100P_0402_50V8J
100P_0402_50V8J
1
1
PRS05
PRS06
PCS04
100K_0402_5%
1
499K_0402_1%
1000P_0402_50V7K
1500P_0402_50V7K
0.1U_0402_25V6
0.47U_0603_25V7K
4.7U_0603_25V6K
2
2
4
1
3
S
Type@ PRS10
Type@EMI@ PCS05
PCS06
Type@EMI@ PCS07
Type@ PRS07
Type@EMI@ PCS08
499K_0402_1%
2
1
G
2 300K_0402_1% <53> PWR_SE2
2
1
Type@ PCS09
Type@ PRS08
PCS21
Type@ PRS09
PCS10
2
2
USBC_B2B_S2_G
' , )( ) -/
AO3409_SOT23-3
Type@EMI@
2
@
Type@ PQS06
D
Type@
2
1
Type@
1
Type@ PRS15 PRS34 @
100K_0402_5% 10K_0402_1% PRS45
0_0402_5%
2
1
2
1
Type@ PRS16
2N7002KW_SOT323-3
49.9K_0402_1%
PRS36 Type@ Type@ PRS18
1
300K_0402_1% D 0_0402_5%
2
2USBC_B2B_S31
3
S
2
Type@ PQS07
2N7002KDW_SOT363-6
2
' , ) ! )-/
G
2 G
S
0.1U_0402_10V7K
3
1
6
PRS35 @
1
D
PRS37 Type@ 0_0402_5%
Type@ PQS05A
@ PCS17
AO3409_SOT23-3
2 1 2
Type@ PQS13
D
100K_0402_5% VBUS_C_CTRL_P1 <38,54>
1
2 USBC_B2B_S2 @ PQS14 G
0.1U_0402_10V7K
2
3 3
2N7002KW_SOT323-3 S
1 2
3
1
Type@ PRS38
Type@ PCS13
1
D
0_0402_5%
0.1U_0402_10V7K
<38,40,54> VBUS_P_CTRL_P1 1 2 2 PUS02 Type@
2
1
G PQS12 Type@ SN74AHC1G08DCKR_SC70-5
Type@ PCS12
' ) !
5
' , ) ! )-/ S 2N7002KW_SOT323-3
3
1 VBUS_C_CTRL_P1 <38,54>
P
2
4 IN1
Type@ PUS04 O 2
IN2 HW_ACAV_IN <11,25,53,55>
G
RT9058-33GX SOT-89 3P
3
1
VCC
1
3 Type@ PRS32 Type@ PDS04
1000P_0603_50V7K
49.9K_0402_1%
VOUT
2 0_0402_5% SDMK0340L-7-F_SOD323-2 ' , ) ! )-/
Type@ PRS11
GND
1
+3.3V_ADP_DCIN
1 2 2 1 ' , ) ! )-/ PRS42 Type@Mad@
1
1
Type@ PRS25 0_0402_5%

Type@ PCS15
PCS16 Type@ PRS33 PDS05 1M_0402_1% 2 1 USBC_B2B_S1
2
2.2U_0402_10V6M 0_0402_5% SDMK0340L-7-F_SOD323-2
2
2
1
1 2 2 1
0.1U_0402_10V7K
<53,55> AC_OK
2
1
D Type@ PRS12 Type@Loki@
Type@Loki@ Type@Loki@
USBC_B2B_S1
1
1 2 2 1 2 10K_0402_5% PDS03 PRS40 Type@Loki@
PCS14
Type@
<25,55> HW_ACAVIN_NB
2N7002KDW_SOT363-6
G PQS08 Type@ LRB715FT1G_SOT323-3 0_0402_5%
1
D
PRS23 PDS06 S 2N7002KW_SOT323-3 2 2 1
HW_ACAVIN_NB <25,53,54,55>
2
USBC_B2B_S1_A
3
100K_0402_5% SDMK0340L-7-F_SOD323-2 2 1
5
PQS04 Type@ 3 2 1
Type@ PQS05B
Type@Loki@ Type@Loki@ G
AC_OK <53,55>
S 2N7002KW_SOT323-3 2 PRS41 Type@Loki@
0.1U_0402_10V7K
P
3
A
1
5 4 0_0402_5%
Y
1
1
Type@ PCS11
B VBUS_P_CTRL_P1 <38,40,54>
G
3
Type@ PRS14
4
Type@ PRS13 100K_0402_5% PUS03 Type@
3
100K_0402_5% TC7SH32FU_SSOP5
2
1 2 USBC_B2B_OVP 5
' , ) ! )-/
PQS03B
4
2N7002KDW_SOT363-6
2N7002KDW_SOT363-6
6
Type@
Type@ PQS03A
<38,40> OVP_TRIP_P1 2
1
2 2
1 1

PWR_Type-C PD Selector
A B C D
A B C D
Main Func = CHARGER
PRB01
0.02_1206_1% EMI@ PLB11
5A Z150 20M 1210_2P
1 4 +PWR_SRC_AC 1 2 +CHARGER_SRC
' )-/
2 3
'#L !
2200P_0402_50V7K
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
33U_D2_25VM_R40M
0.1U_0402_25V6
Vinafix.com
33U_25V_M
82P_0402_50V8J
1 1
@EMI@ PCB01
@EMI@ PCB02
1
1
+ +
PCB03
PCB04
PCB05
PCB06
Mad@RF@ PCB47
@ PCB07
@ PCB08
@ PJPB01
1
1 2 1
2
1 2 2 2
JUMP_43X118
10U_0805_25V6K~D
10U_0805_25V6K~D
10U_0805_25V6K~D
10U_0805_25V6K~D
10U_0805_25V6K~D
10U_0805_25V6K~D
10U_0805_25V6K~D
10U_0805_25V6K~D
1
1
PCB10
PCB11
PCB12
PCB13
PCB14
PCB15
PCB16
PCB17
2
2
1
1
PRB02 PRB03
2.2_0402_1% 2.2_0402_1%
2
CSIP_CHG
CSIN_CHG
PCB18
4.7U_0402_6.3V6M
2200P_0402_50V7K
2200P_0402_50V7K
1000P_0402_50V7K
1 2
82P_0402_50V8J
0.1U_0402_25V6
1
1
EMI@ PCB21
EMI@ PCB22
EMI@ PCB23
EMI@ PCB24
Mad@RF@ PCB46
1
1
PCB19 PCB20
2
' )-/ 1U_0402_25V6K 1U_0402_25V6K
2
0.22U_0603_25V7K
2
PCB25
2 1 1 2 ADP_CHG
'#L !
2 1
PDB01 PRB04
1
SDMK0340L-7-F_SOD323-2 0_0603_5%
3.3_0603_1%
PRB06
PRB05
2 1 442K_0402_1%
2 ' ! ) ) PDB02
2
2
1
SDMK0340L-7-F_SOD323-2
ACIN_CHG
0.1U_0402_25V6
BOOT1_CHG
1
2 1
UG1_CHG
LX1_CHG
LG1_CHG
1
' )-/) PRB07

PCB26
PDB03 100K_0402_5%
1
SDMK0340L-7-F_SOD323-2 PRB09
2
4.7_0402_5%
2
PRB08 1 2 VDD_CHG
UG1_CHG
UG2_CHG
1_0805_5%~D PUB01
PCB27 ISL9538HRTZ-T_TQFN32_4X4
16
15
14
13
12
11
10
33
2
9
1U_0603_25V6
2 1 DCIN_CHG
BOOT1
UGATE1
PHASE1
LGATE1
CSIN
PAD
ADP
CSIP
ASGATE
PCB29
@
PRB10
1U_0402_6.3V6K PQB01 PQB02 ' * PQB03
1
2 1 OTGEN/CMIN_CHG 17 8 VDDP_CHG 1 2 AON6994_DFN5X6D-8-7 AON6994_DFN5X6D-8-7 PRB12 AON7409_DFN8-5
DCIN VDDP PLB01 0.01_1206_1% 1
G1
D1
D1
G1
VDD_CHG LG2_CHG
2 1 0_0402_5% 18
VDD LGATE2
7 1UH_PCMB104T-1R0MH_18A_20%
1 4
2
3 5
'#9, )!(++'
1
PCB28 @ PRB13 ACIN_CHG 19 6 LX2_CHG 7 LX1_CHG 1 2 LX2_CHG 7

1U_0402_6.3V6K 0_0402_5% ACIN PHASE2 D2/S1 D2/S1 2 3
PRB11 2 1 20 5 UG2_CHG
4
499K_0402_1% @ CMIN UGATE2 PCB30
G2
G2
S2
S2
S2
S2
S2
S2
<53> AC_DIS1 PRB141 2 0_0402_5% 21 4 BOOT2_CHG 1 2 1 2
2
SDA BOOT2
1
ACAV_IN1
4700P_0402_25V7K
<25,53> PBAT_CHG_SMBDAT
4.7_1206_5%
4.7_1206_5%
10U_0805_25V6K~D
10U_0805_25V6K~D
3
3
@ PRB161 2 0_0402_5% 22 3
Mad@RF@ PRB17
Mad@RF@ PRB18
0.22U_0603_25V7K PRB15
SCL VSYS
1
<25,53> PBAT_CHG_SMBCLK
PCB31
PCB32
4.7_0603_1%
1
1
1 PRB19 2 0_0402_5% 23 2 CSOP_CHG
@ PCB33
768K_0402_1%
PQB04
PROCHOT# CSOP
1
AMON/BMON
D <12,25,53,60> H_PROCHOT#
PRB20
2N7002KW_SOT323-3
LG1_CHG
LG2_CHG
1SNUB1_CHG 2
1SNUB2_CHG 2
2
2 24 1 CSON_CHG
BATGONE
BGATE_CHG
2
ZTB02 ACOK CSON
CMOUT
G
BGATE
PRB21
COMP
1 ACOK_CHG
PROG
PSYS
2
VBAT
S @
3
@ PRB22 0_0402_5% 1 2
680P_0603_50V7K
680P_0603_50V7K
'#L !
1
@ PRB24 PCB34
25
26
27
105K_0402_1% 28
29
30
31
32
0_0402_5%
Mad@RF@ PCB36
Mad@RF@ PCB37
1M_0402_1%
100K_0402_1%
3 100K_0402_1% 10P_0402_50V8J 3
1 2 1 2 1 2
PRB43
PRB23
PRB25
1
100K_0402_1%
2
2 1 BATGONE_CHG
PRB26
PRB28
@ PCB35
BGATE_CHG
2
<25,53> PBAT_PRES#
VBAT_CHG
PRB27 0.1U_0402_25V6
100K_0402_1%
1
1 2 @
+3VALW
2
PRB29
@
1 2
0_0402_5%
<25> AC_DIS ZTB01 0_0402_5%

2
@ PCB38
COMP_CHG 1U_0402_25V6K
1 2
499_0402_1%
1
PRB31
PRB30
560P_0402_50V7K
10.5K_0402_1%
@ 1 2
1U_0402_25V6K
0.1U_0402_25V6
1
1
@ PCB39
0_0402_5%
2
1
PRB33
PCB40
PCB41
PRB32 1_0402_1%
1
1
2
2
1
0_0402_5%
0_0402_5%
PRB36 1_0402_1%
2
1 2
PRB34
PRB35
PCB42
2
0.01UF_0402_25V7K
2
I_BATT_R 2
@ @
1 2
@ PRB37
% L )
I_ADP_R
0_0402_5%
1 2
@ PCB43
0.22U_0402_25V6K
I_SYS <60> PRB38 PDB04 PCB44
0_0402_5% BAT54CW_SOT323-3 0.1U_0402_10V7K
1 2 3 1 2
' , ) ! )-/ PUB02
1 SN74AHC1G08DCKR_SC70-5
5
'#9, )!(++' 1 2 2 1
<25> I_BATT_R I_ADP_R <25>
P
2 1 <25,53,54> HW_ACAVIN_NB B 4 1 2
4 Y 4
PRB40 ACAV_IN1 1 2 2 HW_ACAV_IN <11,25,53,54>
A
G
Close to EC ADP_I pin PRB39 0_0402_5% PRB42
1
100_0402_5% PRB41 0_0402_5%
3
@ PCB45 1 2 2 1 0_0402_5%
<53,54> AC_OK
0.1U_0402_25V6
2
PRB44
0_0402_5% PDB05
SDMK0340L-7-F_SOD323-2
DELL CONFIDENTIAL/PROPRIETARY
PWR_CHARGER
A B C D
A B C D E
Main Func = 3.3VALWP/5VALWP
Vinafix.com
1 1
@EMI@ PL311
5A_Z120_25M_0805_2P PR302
1 2 499K_0402_1%
ENLDO_3V5V 1 2 '#L !
PC307
PR301
@ PJP301 @ 0.1U_0402_10V7K
1
3V_VIN BST_3V1
150K_0402_1%
1 2 2 1 2
'#L !
PR303
JUMP_43X39
0_0603_5%
2200P_0402_50V7K
1000P_0402_25V8J
1000P_0402_25V8J
4.7U_0805_25V6K
4.7U_0805_25V6K
0.1U_0402_25V6
PU301
1
82P_0402_50V8J
SY8286BRAC_QFN20_3X3
2
BS
IN
IN
IN
IN
1
1
Mad@RF@ PC316
@EMI@ PC301
EMI@ PC302
PC303
PC304
EMI@ PC305
EMI@ PC306
LX_3V 6 20 PL301
LX LX 1.5UH_9A_20%_7X7X3_M
2
2
7 19 LX_3V 1 2
GND LX ' (%
Mad@RF@ PR305
8 18
GND GND
4.7_1206_5%
' %
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
9 17
PG LDO
1
PC310
PC311
PC312
PC313
@ PC314
10 16
NC NC
4.7U_0402_6.3V6M
(%
OUT
2
EN2
EN1
21
NC
FF
GND
1
+ (
PC308
1 3V_SN 2
PR304
G 8 9(
11
12
13
14
15
680P_0603_50V7K
10K_0402_1%
Mad@RF@ PC309
1 2
' (% . 8 @, (
ENLDO_3V5V
2 2
2
<11,25,38,53,58,59> POK
@ PJP302
150K_0402_1%
PC315 PR306 1 2
' (% 1 2 ' (%
1
@ PR307
1000P_0402_25V8J 1K_0402_5%
EN_3V 3V_FB 1 2 1 2 JUMP_43X118
@EMI@ PL511
2
5A Z150 20M 1210_2P
1 2
1
150K_0402_1%
@ PJP502
@ PR308
1 2
@ PJP501 @
PR501
PC507 ' (% 1 2 ' (%
1 2 5V_VIN BST_5V 1 2 1 2 JUMP_43X79
'#L ! 1 2
2
JUMP_43X79 0.1U_0402_10V7K @ PJP503
0_0603_5%
2200P_0402_50V7K
1000P_0402_25V8J
1000P_0402_25V8J
1 2
PU501 1 2
82P_0402_50V8J
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
1
SY8180CRAC_QFN20_3X3 JUMP_43X79
1
1
Mad@RF@ PC518
@EMI@ PC501
EMI@ PC502
PC503
PC504
EMI@ PC505
EMI@ PC506
BS
IN
IN
IN
IN
LX_5V 6 20 PL501
2
LX LX 1.5UH_9A_20%_7X7X3_M
7 19 LX_5V 1 2
GND LX ' (%
4.7_1206_5%
8 18
GND GND
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
3 3
1
Mad@RF@ Mad@RF@
PR505
9 17 1 2
PC510
PC511
PC512
PC513
PC514
@ PC519
PG VCC
10 16 PC508
2
NC NC
15V_SN
@ 4.7U_0402_6.3V6M
OUT
LDO
PR502
2
EN2
EN1
0_0402_5% 21
FF
EN_3V GND
680P_0603_50V7K
1 2
PC509
11
12
13
14
15
@ PR504
@
PR503
10K_0402_1% VL
' (%
2
EN_5V 1 2 1 2
ENLDO_3V5V
4.7U_0402_6.3V6M
0_0402_5%
1
EN_5V
PC515
POK
PR506
2.2K_0402_5%
(%
2
150K_0402_1%
1 2
<25> ALWON
+ 39, $ (
1
@ PR510
PD501
@
PR507
SDMK0340L-7-F_SOD323-2 G 8 # ,@ (
<25> CMP_VOUT0
1 2 1 2 . 8 # (
2
4.7U_0402_6.3V6M
0_0402_5%
1
1
1
150K_0402_1%
PC516
PR508 PC517 PR509
@ PR511
1M_0402_5% 1000P_0402_25V8J 1K_0402_5%
5V_FB 1 2 1 2
2
2
4 4

PWR_3.3VALWP/5VALWP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1(X00)
A B C D E
A B C D
Main Func = +1.2V_DDR/+0.6V_DDR_VTT

PRM02
2.2_0603_5%
BST_1.2V_R 2 1 BST_1.2V
,$ ' & M
1
@EMI@ PLM11 + #,4(
5A_Z120_25M_0805_2P
1 2 Vinafix.com PCM12
0.1U_0402_10V7K
'#,4 G 8 #, (
2
1 1
'#L ! @ PJPM01
+19VB_1.2V UG_1.2V
1 2
' ,$
JUMP_43X39
82P_0402_50V8J
1000P_0402_50V7K
1000P_0402_50V7K
2200P_0402_50V7K
0.1U_0402_25V6
4.7U_0805_25V6K
4.7U_0805_25V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
LX_1.2V
@EMI@ PCM22
EMI@ PCM23
EMI@ PCM01
EMI@ PCM02
PCM03
PCM04
Mad@RF@ PCM24
1
PCM20
PCM21
16
17
18
19
20
2
2
PUM01
2
VLDOIN
PHASE
UGATE
BOOT
VTT
21
PAD
LG_1.2V 15 1
LGATE VTTGND
PRM03 14 2
PGND VTTSNS
1
15.4K_0402_1%
PQM01 2 1
D1
D1
D1
G1
TR PE642DT 2N PDFN3X3S CS_1.2V 13 3
PCM13 CS RT8207PGQW _W QFN20_3X3 GND
10 9 1U_0603_10V6K
D1 D2/S1 2 1 12 4 VTTREF_1.2V
PRM04 VDDP VTTREF
5.1_0603_5%
G2
S2
S2
S2
1 2 VDD_1.2V 11 5
VDD VDDQ +1.2VP
1
PGOOD
5
8
PCM19
TON
2 ' (% 0.033U_0402_16V7K 2
FB
S5
S3
2
1
1
PRM05
10
6
PCM14 2.2_0603_5%
1U_0603_10V6K
2
@ PCM17
EN_0.6VSP
EN_1.2V
FB_1.2V
2
TON_1.2V
220P_0402_25V8J
1 2
' (%
<11> 1.2V_VTT_PWRGD PRM10
60.4K_0402_1%
@ PRM06 PRM07 1 2
10K_0402_1% +19VB_1.2V 1 2 +1.2VP
1 2
' (% 453K_0402_1% '#,4 )
1
PRM11
@ PCM18 + $,4 (
@
PRM08
100K_0402_1%
.1U_0402_16V7K G 8 @,L (
2
PLM01
<11,17,59> SIO_SLP_S4#
1 2 . 8 # ,9 (
2
1UH_11A_20%_7X7X3_M
1
1 2 0_0402_5% @ PCM15
'#,4 0.1U_0402_10V7K
2
@
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PRM09
1 2
<7> 0.6V_DDR_VTT_ON
1
1
PCM05
PCM06
PCM07
PCM08
PCM09
PCM10
1
3 0_0402_5% @ PCM16 3
0.1U_0402_10V7K
2
@ @EMI@ PRM01 @ PJPM02
2
4.7_1206_5% 1 2
'#,4 1 2 '#,4 )
2
JUMP_43X118
1
@EMI@ PCM11
680P_0402_50V7K
2
@ PJPM03
1 2
' ,$ ' ,$ ) ) ++
JUMP_43X39
4 4

Issued Date 2017/12/01 Title
2016/12/01 Deciphered Date
PWR_+1.2V_MEN/+0.6V_DDR_VTT
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom X00
A B C D
A B C D
Main Func = +1VALWP
'#, ) -
+ 9,$ (
G 8 # ,@ (
Vinafix.com . 8 #4 ( 0 7 <; -
+D (H
' (% G ##, 5 5 6 #4, 5 5
1 1
1
PRH06 PCH12
@ PRH05 10_0603_5% 0.1U_0402_10V6K
100K_0402_5% 1 2 BST_+1VALW_R 1 2
BST_+1VALW
2
@EMI@ PLH11
5A_Z120_25M_0805_2P
1 2
@ PJPH01 PUH01
1
1 2 +19VB_+1VALW RT6228AGQUF_UQFN12_3X3 PLH01
'#L ! 1UH_11A_20%_7X7X3_M
PGOOD
BOOT
JUMP_43X39
5 2 LX_+1VALW 1 2
82P_0402_50V8J
1000P_0402_50V7K
1000P_0402_50V7K
2200P_0402_50V7K
10U_0805_25V6K~D
10U_0805_25V6K~D
0.1U_0402_25V6 VIN LX '# (%
1
1
@EMI@ PCH15
@EMI@ PCH16
@EMI@ PCH01
EMI@ PCH02
PCH03
PCH04
Mad@RF@ PCH17
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
10 FB_+1VALW @ PCH14
2
2
FB
1
330P_0402_50V7K
PCH05
PCH06
PCH07
PCH08
6 11 2 1 ' (% @EMI@ PRH07
2
EN BYP PRH11 4.7_1206_5%
2
12 9 2.2_0402_1%
ILMT VCC
1
PGND
AGND
2
1
1
@ PRH12 @ PJPH02
PCH10
PCH11
LX
1U_0402_10V6K
1U_0402_10V6K
1K_0402_1% 1 2
# '# (% 1 2
'#, ) -
SNUB_+1VALW
4
2
N_DSX@ PRH01 JUMP_43X118
? <3 , $
2
0_0402_5% 1 2
1 2 EN_+1VALW
<11,25,38,53,56,59> POK
LX_+1VALW
PRH08
@DSX@ PRH13 21.5K_0402_1%
1
1
1 2 PCH09
<11,25,59> SIO_SLP_SUS# 0_0402_5% ILMT_+1VALW
2
1M_0402_1%
0.1U_0402_10V7K 2
1
PRH09
@ PRH02
4
2
1 2 Mad@ @EMI@ PCH13 31.6K_0402_1%

<25,36,59> PCH_PRIM_EN
' (% 680P_0603_50V7K
2
2
Mad@ PRH90
100K_0402_5%
1
@
PRH03
0_0402_5%
2
1
@ PRH04
0_0402_5%
2
3 3
4 4

PWR_+1VALWP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C X00
A B C D
A B C D
Main Func = +1.8VALWP / +2.5VP
@ PL1811
5A_Z120_25M_0805_2P
Vinafix.com @ PJP1802
JUMP_43X79
1 2 1 2
1
PU1801 '#,@ (% 1 2 '#,@ ) - 1
11
10 TP 1 PL1801
@ PJP1801 PVIN NC 1UH_6.6A_20%_5X5X3_M
1 2 9 2 LX_1.8VALW 1 2
' (% PVIN LX
'#,@ (%
JUMP_43X39 8 3
2200P_0402_50V7K
SVIN LX
0.1U_0402_25V6
22U_0603_6.3V6M
82P_0402_50V8J
7 4 PRIM_PWRGD <25>
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
NC PGOOD
1
PC1807
PC1801
Mad@RF@ PC1808
Mad@RF@ PC1809
Mad@RF@ PC1810
1
6 5
PC1802
PC1803
PC1804
FB EN PR1803 @EMI@ PR1804 22P_0402_50V8J '#,@ ) -
2
100K_0402_5% 4.7_1206_5% + #(
EN_1.8VALW
2
RT8061AZQW_WDFN10_3X3
G 8 #, (
2
1
@DSX@ PR1806
0_0402_5%
FB=0.6Volt . 8 , ( ? 7 <; -
1 2 2 1
<11,25,58> SIO_SLP_SUS# ' (%
PR1807
1 2 20K_0402_1%
<11,25,38,53,56,58> POK
1
N_DSX@ PR1801 @EMI@ PC1806
0.1U_0402_10V7K
1
0_0402_5% 680P_0402_50V7K PR1805
PC1805
2
1
@ PR1802 10K_0402_1%
1M_0402_5%
2
2
1 2
<25,36,58> PCH_PRIM_EN
2
Mad@ PR1890
0_0402_5%
FB_1.8VALW
2 2
1 2
' (% @ PJP2502
PR2504 1 2
'4, '4, ) "
1
2.2_0402_1% PC2504
1U_0402_6.3V6K JUMP_43X39
2
4 5
GND
@ PJP2501 VDD NC
1 2 2.5V_VIN 3 6 '4,
' (% VIN VOUT
JUMP_43X39 2 7 ADJ_2.5V
10U_0805_10V6K
EN ADJ
1
1
'4,
1
1 8
PC2501
10U_0805_10V6K
PGOOD GND
1
PR2502 @ PC2505 + , (
2
21.5K_0402_1% 0.01U_0402_25V7K
PC2502
G 8 , 9(
2
PU2501
2
2
RT9059GSP_SO8
@
PR2501
?3 ,@
1
3
1 2 EN_2.5V 3
<11,17,57> SIO_SLP_S4#
PR2503
0_0402_5% 10K_0402_1%
0.1U_0402_10V6K
1
@ PC2503
2
2
4 4

PWR_+1.8VALWP / +2.5VP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C X00
A B C D
A B C D
Main Func = CPU
Vinafix.com
I_SYS <55>
1 1
PRZ01
PCZ01
1.5K_0402_1%
. ? ( 1 2 1 2 PCZ02
2200P_0402_50V7K
8200P_0402_25V7K 1 2
PCZ04 COMP_1b_CPU 1 2
1000P_0402_50V7K PCZ03
1 2 15P_0402_50V8J PRZ06
10_0402_5% <61> CSN_1b_VCCSA
PRZ04 2 1
18.2K_0402_1%
1000P_0402_50V7K
2
1.78K_0402_1%
2
@ PRZ03 1 2 0_0402_5% VSPP_1b_CPU_R 1 2 VSP_1b_CPU
PCZ05
PRZ05
<17> VSA_SEN+
1
( G
1
PHZ01
0.01U_0402_25V7K
1
PCZ06 PRZ08 100K_0402_1%_B25/50 4250K
1200P_0402_50V7K
1
1000P_0402_50V7K 1K_0402_1%
1
@ PRZ07 1 2 VSNN_1b_CPU_R 1 2 VSN_1b_CPU
PCZ08
PCZ09
<17> VSA_SEN-
12
0_0402_5%
1 2 PRZ10
2
PCZ07 2200P_0402_25V7K
CSP_1b_VCCSA
12K_0402_1% '
1 2 <61> CSP_1b_VCCSA_R
2
PRZ15 2 1
1
PRZ11 20K_0402_1% 54.9K_0402_1%
@ PRZ14 1 2 0_0402_5% VSP_2ph_CPU 1 2 PRZ13 PRZ16
<15> VCCSENSE
7.5K_0603_1% 10K_0402_1%
1
1 2
PCZ10 U22@ PRZ19 PCZ12 470P_0402_50V7K
2
1000P_0402_50V7K 1K_0402_1%
2
@ PRZ18 1 2 0_0402_5% VSN_2ph_CPU_R 1 2 VSN_2ph_CPU
<15> VSSSENSE
1 2 '#, ) +
PCZ11 3300P_0402_25V7K
1
U42@ PRZ21
2 845_0402_1% PRZ20 U42@ PRZ23 U42@ PRZ19 2
1
49.9_0402_1% 22K_0402_1% 1.54K_0402_1%
PRZ22
U22@ @
PRZ21 1 2 IMVP_VR_ON <11>
110_0402_1%
100_0402_1%
45.3_0402_1%
1 2
IOUT_1b_CPU
619_0402_1%
-. +I +
ILIM_1b_CPU
0_0402_5%
470P_0402_50V7K
2
PCZ13
EN_CPU
PWM_1b_CPU <61>
1
470P_0402_50V7K
2
CSCOMP_2ph_CPU_R
2
. "# G
1
U22@ PRZ23 PRZ43 @ PRZ44
PCZ14
DRVON <61>
4.75K_0402_1%
1
24.9K_0402_1% PCZ24 110_0402_1% 7.5K_0603_1%
1
PHZ02 2 1
49
48
47
46
45
44
43
42
41
40
39
38
37
0.1U_0402_25V6 CSP_1a_VGT_R <61>
PRZ24
2
220K_0402_5%_B25/50 4700K U42@ @
1
1
1 2 PRZ28 PRZ45
VSN_2ph
VSP_2ph
VSP_1b
VSN_1b
COMP_1b
ILIM_1b
CSN_1b
CSP_1b
IOUT_1b
EN
TAB
PSYS
VR_RDY
2
16.9K_0402_1% PCZ15 PUZ01 H_PROCHOT# <12,25,53,55> 12K_0402_1%
PRZ40
PRZ41
PRZ42
1 2
15P_0402_50V8J NCP81218DMNTXG_QFN48_6X6 2 1
2
PRZ26 PRZ27 IOUT_2ph_CPU 1 36 PRZ46 PCZ25 CSN_1a_VGT_NTC
5600P_0402_25V7K
0.022U_0402_16V7K
165K_0402_1% 75K_0402_1% DIFFOUT_2ph_CPU 2 IOUT_2ph PWM_1b 35 49.9_0402_1% 470P_0402_50V7K
DIFFOUT_2ph DRVON
1
1 2 1 2 1 2 U22@ PRZ28 PCZ16 FB_2ph_CPU 3 34 SCLK_CPU 1 2 1 2
CSP1_VCORE1 VIDSCLK <15>
2
FB_2ph SCLK
1
1
PRZ25 66.5K_0603_1% 9.76K_0402_1% 2200P_0402_50V7K COMP_2ph_CPU 4 33 ALERT#_CPU
@ PRZ47 1 2 0_0402_5%
PCZ26
PCZ27
ILIM_2ph_CPU COMP_2ph ALERT# SDIO_CPU PRZ48 1 VIDALERT_N <15>
CSP2_VCORE2 1
PRZ29 U42@
2
66.5K_0603_1%
PCZ17 @ PCZ18
1000P_0402_50V7K
1 2
CSCOMP_2ph_CPU
5
6 ILIM_2ph SDIO
32
31 VR_HOTL# PRZ49 1
2 10_0402_1%
2 100_0402_1%
VIDSOUT <15> PRZ50
97.6K_0402_1%
PHZ03 ) + G
100K_0402_1%_B25/50 4250K
820P_0402_50V7K
2
2
CSSUM_2ph_CPU 7 CSCOMP_2ph VR_HOT# 30 IOUT_1a_CPU 1 2 PRZ51
2
1 2 CSREF_2ph_CPU 8 CSSUM_2ph IOUT_1a 29 CSP_1a_VCORE 10_0402_5%
CSN2_VCORE2 CSP2_2ph_CPU CSREF_2ph CSP_1a
PRZ30 U42@ 10_0402_1% 9 28 2 1 CSN_1a_VGT <61>
1 2 CSP1_2ph_CPU 10 CSP2_2ph CSN_1a 27 ILIM_1a_CPU
ROSC_COREGT
0.1U_0402_25V6
CSN1_VCORE1 CSP1_2ph ILIM_1a

1
TSENSE_2ph_CPU_R 1 2 TSENSE_2ph_CPU 11 26 COMP_1a_CPU
ADDR_VBOOT
PRZ31 10_0402_1%
U42@
10K_0402_1%
10K_0402_1%
0.1U_0402_25V6
1000P_0402_50V7K
2.15K_0402_1% 0.015U_0402_25V7K
TSENSE_1ph
TSENSE_2ph COMP_1a
RSOC_SAUS
1
1
ICCMAX_2ph
0_0402_5% 1 2 12 25 1 2
PCZ32
ICCMAX_1a
ICCMAX_1b
PWM1_2ph
PWM2_2ph
VRMP VSN_1a
1
1
PCZ19 @ PRZ34 PRZ35 PCZ28 3300P_0402_50V7-K
VRMP_CPU
@ PRZ32
PCZ20
@ PRZ33
'#L !)
PWM_1a
1
VSN_1a_CPU_R
VSP_1a
0.1U_0402_25V6 1K_0402_1% 1 2 PCZ33
PCZ31
150P_0402_50V8J
2
2
1
PRZ36 2200P_0402_50V7K
PCZ21
PCZ30
VCC
2
1 2
1
1
PHZ04 61.9K_0402_1% PCZ22 PRZ52
PRZ56
52.3K_0402_1%
PRZ53
2
1000P_0402_50V7K 1K_0402_1% @
1
CSP1_VCORE1 1 2 PCZ23 VSN_1a_CPU
1 2 1 2 VSS_GT_SENSE <16>
2
13
14
1ROSC_SAUS_CPU 15
16
17
18
19
20
21
22
23
24
2
PRZ37 2.15K_0402_1% 100K_0402_1%_B25/50 4250K 0.01U_0402_50V7K
PRZ55
2
1
CSP2_VCORE2 1 2 PCZ29
2
PRZ38 U42@ 2.15K_0402_1% 1000P_0402_50V7K 0_0402_5%
ICCMAX_2ph_CPU
ADDR_VBOOT_CPU
2
VCC_CPU
ICCMAX_1a_CPU
ICCMAX_1b_CPU
2
PRZ57 PRZ58
3
1 2 . "# . 2_0402_1% 4.32K_0402_1% @
PRZ59 3
' (% U22@ PRZ39 1 2 2 1VSP_1a_CPU_R 2 1 VCC_GT_SENSE <16> . ? ) +

1K_0402_1% ' (% VSP_1a_CPU2
1ROSC_COREGT_CPU
1 2 1
24K_0402_1%
0_0402_5%
1
PCZ35 PRZ61
PRZ60
PCZ34 1000P_0402_50V7K 3.65K_0402_1% @
PRZ63
1U_0603_10V6K
2
TSENSE_1ph_CPU 1 2 TSENSE_1ph_CPU_R
1
0_0402_5%
1000P_0402_50V7K
PCZ36
24K_0402_1%
61.9K_0402_1%
1
1
0 ? (
2
<61> PWM_1a_CPU PHZ05
PRZ64
PRZ65
100K_0402_1%_B25/50 4250K
51.1K_0402_1%
97.6K_0402_1%
19.1K_0402_1%
35.7K_0402_1%
0 ? . ": +
2
2
+ .
1
U22@ PRZ66
PRZ67
PRZ68
PRZ69
2
2
PRZ66 U42@
100K_0402_1%
-? ) . " 2;
P$L #,# ? ,
PWM2_2ph_CPU <61>
4 PWM1_2ph_CPU <61> 4

PWR_CPU
A B C D
A B C D
Main Func = CPUcore IA/GT/SA

Vinafix.com '#L !)
EMI@ PLI11 %
)
2
B 4C
1 4, 5& 5
5A Z150 20M 1210_2P '#L !
2 1
1000P_0402_50V7K
2200P_0402_50V7K
1000P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
@ PJPI01
+ 4(
33U_D2_25VM_R40M
0.1U_0402_25V6
1 1 2 1
2 1
33U_25V_M
G 8 $ (
1
+ +
PCI01
PCI02
PCI03
PCI04
@EMI@ PCI05
EMI@ PCI06
EMI@ PCI07
EMI@ PCI08
PCI13
PCI14
JUMP_43X79
. 8 9 (
G ,$9 '& M5 5 B9Q9Q C
2
2 2@
) B 44C
1 % 2 1 4, 5& 5 1
'#L !)
+ 4#(
2200P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
G 8 4(
0.1U_0402_25V6
U42@EMI@ PCI21
U42@EMI@ PCI22
U42@EMI@ PCI27
@U42@EMI@ PCI28
. 8 @(
U42@ PCI23
U42@ PCI24
U42@ PCI25
U42@ PCI26
1
1
G ,$9 '& M5 5 B9Q9Q C
PRI02
2
2_0402_1%
1 2 VCC_VCORE1 U42@ PRI22
' (% 2_0402_1%
VCC_VCORE2
1
1 2
PCI10 PRI01 PCI09 ' (%
1
1U_0402_10V6K 3.9_0603_1% 0.22U_0603_25V7K
PUI01
2
1 2 BST_VCORE1_R 1 2 U42@ PCI30 U42@ PRI21 U42@ PCI29

3 8 1U_0402_10V6K 3.9_0603_1% 0.22U_0603_25V7K
2
VCCD_VCORE1 15 VCC VIN 9 U42@ PUI02 1 2 BST_VCORE2_R 1 2
VCCD VIN 3 8
17 5 BST_VCORE1 PLI01 VCCD_VCORE2 15 VCC VIN 9
THWN BOOT PHASE_VCORE1 VCCD VIN
1
16 7 0.15UH 20% MMD-06DZER15MEM1L 36A

<60,61> DRVON DISB# PHASE BST_VCORE2
PCI11 1 17 5 U42@ PLI02
<60> PWM1_2ph_CPU PWM LX_VCORE1 PHASE_VCORE2
16 THWN BOOT
1
1U_0402_10V6K 2 11 1 4 7 0.15UH 20% MMD-06DZER15MEM1L 36A
' ) . " <60,61> DRVON
2
SMOD# SW 12 U42@ PCI31 1 DISB# PHASE

' (% SW 2 3 1U_0402_10V6K
<60> PWM2_2ph_CPU
2 PWM 11 LX_VCORE2 1 4
' ) . "
2
4 SMOD# SW 12
CGND ' (% SW
1
10 2 3
14 PGND @EMI@ PRI03 4
PGND CGND
1
13 6 4.7_1206_5% 10
19 GL NC 18 14 PGND @U42@EMI@ PRI23
GL AGND 13 PGND 6 4.7_1206_5%
2
NCP302045MNTWG_PQFN33_5X5 19 GL NC 18
CSN1_VCORE1 GL AGND
2
1
@EMI@ PCI12 NCP302045MNTWG_PQFN33_5X5 CSN2_VCORE2
2 2
1
680P_0603_50V8J
2
@U42@EMI@ PCI32
CSP1_VCORE1 680P_0603_50V8J
2
CSP2_VCORE2
EMI@ PLG11
5A Z150 20M 1210_2P
2 1
+)!' '#L !
@ PJPG01
2 1
2 1 ) (
InputCapacitor: JUMP_43X79 % 2 1 # , 5& 5
10uF_0805_X5R_25V
+)!' ) + + (
G 8 (
2200P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
44 & #
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
33U_D2_25VM_R40M
0.1U_0402_25V6
1
% 2 1 ,#5& 5 . 8 9(
1
+
G $,4 '& M5 5B Q Q C
PCG01
PCG02
PCG03
PCG04
@EMI@PCG05
EMI@ PCG06
@EMI@ PCG07
@EMI@ PCG08
PCG13
@ PJPA01
2
2
44&# 2 1
+ #@( ()!' '#L !)
JUMP_43X39
G 8 #(
. 8 9(
G ,$9 '& M5 5 B9Q9Q C ()!'
2200P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
3 3
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
1
1
PCA01
PCA02
@EMI@ PCA03
@EMI@ PCA04
@EMI@ PCA05
@EMI@ PCA06
PRG02 PRA01 PCA07
2
2_0402_1% 2.2_0603_5% 0.22U_0603_16V7K
1 2 VCC_VGT1 1 2 BST_VCCSA_R 1 2
' (%
BST_VCCSA
1
PCG10 PRG01 PCG09 UG_VCCSA

1U_0402_10V6K 3.9_0603_1% 0.22U_0603_25V7K AON7934
PUG01
2
1 2 BST_VGT1_R 1 2
3 8 Rds(on)=12.4~15.8m ohm
VCCD_VGT1 15 VCC VIN 9 PUA01 PQA01
VCCD VIN
1
NCP81253MNTBG_DFN8_2X2 TR PE642DT 2N PDFN3X3S
17 5 BST_VGT1 PLG01 PLA01
D1
D1
D1
G1
THWN BOOT PHASE_VGT1
1
16 7 0.15UH 20% MMD-06DZER15MEM1L 36A 1 8 0.47UH 20% MMD-05CZ-R47MEV1L 12.2A

<60,61> DRVON DISB# PHASE BST DRVH
PCG11 1
<60> PWM_1a_CPU
1U_0402_10V6K 2 PWM 11 LX_VGT1 1 4 <60> PWM_1b_CPU
2 7 10 9 LX_VCCSA 1 4 ' ) (
' ) +
2
SMOD# SW 12 PWM SW D1 D2/S1

SW 2 3 3 6 2 3
<60,61> DRVON EN GND
4
G2
S2
S2
S2
CGND
1
1
10 4 5
PAD
14 PGND @EMI@ PRG03 ' (% VCC DRVL
8
13 PGND 6 4.7_1206_5% @EMI@ PRA02
GL NC
1
19 18 4.7_1206_5%
9
GL AGND PCA08
2
2
2.2U_0603_16V6K CSN_1b_VCCSA <60>
2
NCP302045MNTWG_PQFN33_5X5 CSN_1a_VGT <60> SNB_VCCSA
1
1
@EMI@ PCG12
680P_0603_50V8J LX_VCCSA CSP_1b_VCCSA_R <60>
2
@EMI@ PCA09
2
CSP_1a_VGT_R <60> 680P_0603_50V7K
LG_VCCSA
4 4

2016/12/01 2017/12/01 Title
Issued Date Deciphered Date
PWR_CPUcore IA/GT/SA
A B C D
4
Main Func = CPU/ VGA / SA MLCC

'
) . "
2 1 2 1
Vinafix.com
2 1 2 1 2 1 2 1
'
PCI149 PCI139 PCI129 U42@ PCI121 PCI111 PCI101
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1 2 1
) . "
2
1
+
PCI150 PCI140 PCI130 U42@ PCI122 PCI112 PCI102 U22@ PCI171
A
A
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 220U 2V Y D2
2 1 2 1 2 1 2 1 2 1 2 1
1
+
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 220U 2V Y D2
2 1 2 1 2 1 2 1 2 1 2 1
1
+
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 330U_D2_2V_Y
2 1 2 1 2 1 2 1 2 1 2 1
330U_D2_2V_Y
U42@ PCI172
330U_D2_2V_Y
U42@ PCI171
PCI153 PCI143 PCI133 U42@ PCI125 PCI115 PCI105
2 1 2 1 2 1 2 1 2 1 2 1 2 1
U22@ PCI159 PCI154 PCI144 PCI134 U42@ PCI126 PCI116 PCI106

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1 2 1 2 1
4 H 4480) $ 33A 44
4 H 44 80) 433A 44
+
4 H 4480) $ 33A 4
H
H #80) 4 #33A 44
H #80) 4 #33A 4
2 1 2 1 2 1 2 1 2 1 2 1 2 1

80) 433A 4
. " .8 8
2 1 2 1 2 1 2 1 2 1 2 1
U22@ PCI162 PCI157 PCI147 PCI137 PCI119 PCI109

2 1 2 1 2 1 2 1 2 1 2 1
U22@ PCI163 PCI158 PCI148 PCI138 PCI120 PCI110

B
B
1
'
) +
2 1 2 1 2 1 2 1 2 1 2 1
PCG138 PCG134 PCG131 PCG121 PCG111 PCG101

1U_0201_6.3V6M 0.47U_0201_6.3V6K 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1 2 1 2 1

'
2 1 2 1 2 1 2 1 2 1 2 1
() . "
'
2
1
+
VGA@ PCV171
560U_D2_2VM_R4.5M 2 1 2 1 2 1 2 1 2 1
) +
2
1
+
2
1
+
VGA@ PCV172 1U_0201_6.3V6M 0.47U_0201_6.3V6K 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 220U 2V Y D2

560U_D2_2VM_R4.5M
2 1 2 1 2 1 2 1
1
+
PCG142 PCG125 PCG115 PCG105 @ PCG172
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 220U 2V Y D2
2 1 2 1 2 1 2 1
C
C
PCG143 PCG126 PCG116 PCG106
Security Classification
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

Issued Date
2 1 2 1 2 1 2 1

0
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
LH #80) 4 #
# H 44 80) 4
+
H , 980) 4 #
2 1 2 1 2 1 2 1
H 4480) $ )H 33A 4
H 4480) $ )H 33A 44
( . "
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
+ .8 8
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2016/12/01
2 1 2 1 2 1
PCG130 PCG120 PCG110

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
Compal Secret Data
1
+VCC_GT
'
'
Deciphered Date
) . "
) (
2 1 2 1
U23@
U42@
@U42@ PRC04
D
D
0.0002_0805_5%
0.0002_0805_5%
PCA110 PCA101
1
1
SOLDER_0603
1U_0201_6.3V6M 22U_0603_6.3V6M
9 H #80) 4 #
9 H 4480) $
+
PRC7
PRC01
2 1 2 1
PCA111 PCA102
2
2
2017/12/01
1U_0201_6.3V6M 22U_0603_6.3V6M
'
2 1 2 1
2 1
( .8 8
) . ") 4
PCA112 PCA103
U42@ PCC01 1U_0201_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M
2 1 2 1 2 1
U42@ PCC02 PCA113 PCA104

22U_0603_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1
PCA114 PCA105
1U_0201_6.3V6M 22U_0603_6.3V6M
Date:
Size
Title
'
1
'
2 1 2 1
Document Number
PCA115 PCA106
) . "
Friday, March 02, 2018
PWR_CPU / VGA / SA MLCC
1U_0201_6.3V6M 22U_0603_6.3V6M
) +
2 1 2 1
U42@
@U42@ PRC06
U22@
@U22@ PRC05
PCA116 PCA107
0.0002_0805_5%
0.0002_0805_5%
1U_0201_6.3V6M 22U_0603_6.3V6M
1
1
SOLDER_0603
SOLDER_0603
2 1
PRC03
PRC02
@ PCA108
22U_0603_6.3V6M
2
2 1
E
2 1 @ PCA109
'
22U_0603_6.3V6M
Sheet
PCC03
22U_0603_6.3V6M
) +) 4
2 1
62
PCC04
22U_0603_6.3V6M
of
65
Rev
X00
1
5 4 3 2 1
Main Func = VGA CORE

@ PJPV01
2 1
2 1
+19VB_VGA JUMP_43X79
VGA@EMI@ PLV11
5A Z150 20M 1210_2P
2 1 +19VB
2200P_0402_50V7K
2200P_0402_50V7K
4.7U_0805_25V6K
4.7U_0805_25V6K
Vinafix.com
UG2_VGA
0.1U_0402_25V6K
0.1U_0402_25V6K
10U_0805_25V6K~D
10U_0805_25V6K~D
1
1
VGA@ PCV01
VGA@ PCV02
VGA@ PCV03
VGA@ PCV35
@VGA@EMI@ PCV04
@VGA@EMI@ PCV05
@VGA@EMI@ PCV06
VGA@EMI@ PCV07
VGA@ PQV03
G1
D1
D AON6994_DFN5X6D-8-7 D
2
7
D2/S1
G2
S2
S2
S2
VGA@ PLV02
6
0.22UH_24A_20%_7X7X4_MOLDING
LX2_VGA 4 1
LG2_VGA
' () . "
VGA@ PRV03 3 2
VGA@MAD@RF@ 10K_0402_1%
10K_0402_1%
10K_0402_1%
32.4K_0402_1%
1
UG2_VGA PRV06 ISEN2_VGA 2 1
2
@ PRV02
VGA@ PRV04
VGA@ PRV05
4.7_1206_5%
2
VGA@ PRV07
2
PCV08 VGA@ 3.65K_0603_1%
' (% VGA@ PQV04 0.22U_0402_16V7K VGA@MAD@RF@ VSUM+_VGA 2 1
G1
D1
1 2
AON6994_DFN5X6D-8-7 PCV09
1
680P_0603_50V7K VGA@ PRV08
2
7 1_0402_1%
D2/S1 @ PRV01 VSUM-_VGA 2 1
2
0_0603_5%
VGA@
41
40
39
38
37
36
35
34
33
32
31
G2
S2
S2
S2
PUV01
1
TP
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
PHASE_NB
UGATE_NB
BOOT_NB
BST2_VGA
VGA@ PRV10 100K_0402_1%
2 1 1 30 BST2_VGA
VGA@ PRV09 100K_0402_1% NTC_NB BOOT2 () . " B 4& C
UG2_VGA
2 1 2
IMON_NB UGATE2
29 + (
<45> SVI2_SVC
3
SVC PHASE2
28 LX2_VGA G 8 $ (
LG2_VGA
4 27 LG2_VGA ' (% . 8 94(
VR_HOT_L LGATE2 '#L !) (
5 26
VGA@
PRV12
0_0402_5%
<45> SVI2_SVD SVD ISL62771HRTZ-T_TQFN40_5X5 VDDP VGA@ PRV13 0 3 G*O
1 2 VDDIO_VGA 6 25 2 1
+1.8VGS VDDIO VDD 1_0603_5%
1U_0603_10V6K
1
@ PRV14 0_0402_5% 7 24 LG1_VGA UG1_VGA
2200P_0402_50V7K
2200P_0402_50V7K
4.7U_0805_25V6K
4.7U_0805_25V6K
<45> SVI2_SVT SVT LGATE1
1
C 1 2 C
@ PRV15 0_0402_5%
1U_0603_10V6K
0.1U_0402_25V6
0.1U_0402_25V6
+3VGS 1 2ENABLE_VGA8 23 LX1_VGA
VGA@ PCV11
PCV12
10U_0805_25V6K~D
10U_0805_25V6K~D
<9,43> DGPU_PWR_EN
2
ENABLE PHASE1
2
VGA@ PCV10
1
PWRGD_VGA 9 22 UG1_VGA
VGA@ PCV13
VGA@ PCV14
PCV15
PCV36
@VGA@EMI@ PCV16
@VGA@EMI@ PCV17
@VGA@EMI@ PCV18
PCV19
0.1U_0402_25V6K
G1
D1
PWROK UGATE1
2 1 IMON_VGA 10 21 BST1_VGA
VGA@
VGA@ PQV01
'
2
IMON BOOT1 AON6994_DFN5X6D-8-7 7
D2/S1
PGOOD
VGA@
VGA@
VGA@EMI@
VGA@ PRV16
ISUMN
ISUMP
COMP
ISEN2
ISEN1
VSEN
133K_0402_1%
NTC
RTN
2 1
G2
FB
S2
S2
S2
1
VGA@ PCV20 VGA@ PRV18 VGA@ PRV19
11
12
13
14
15
16
17
18
19
20
6
1000P_0402_50V7K 150K_0402_1% 13.3K_0402_1% @ PRV17 VGA@ PLV01
2 1 2 1 100K_0402_1% 0.22UH_24A_20%_7X7X4_MOLDING
@ PRV20
2
PWRGD_VGA
0_0402_5%
LG1_VGA
LX1_VGA 4 1 ' () . "
1 2
2 1 VGA@ PRV22 3 2
<12,64> DGPU_PWROK VGA@MAD@RF@ 10K_0402_1%
1
@ PHV01 VGA@ PCV22 PRV23 ISEN1_VGA 2 1
470K_0402_5%_TSM0B474J4702RE 0.22U_0402_10V6K UG1_VGA 4.7_1206_5%
2
2 1 ISEN2_VGA VGA@ PRV24
PCV21 VGA@ 3.65K_0603_1%
2
VGA@ PCV23 VGA@MAD@RF@ VSUM+_VGA 2 1
0.22U_0402_16V7K
1 2
0.22U_0402_10V6K PCV24
G1
D1
VSUM-_VGA 2 1 ISEN1_VGA VGA@ PQV02 680P_0603_50V7K VGA@ PRV25
2
1_0402_1%
VGA@ VGA@ VGA@ PCV26 AON6994_DFN5X6D-8-7 7 @ PRV21 VSUM-_VGA 2 1
2
PCV25 PRV26 180P_0402_50V8J @ PRV27 D2/S1
0_0603_5%
1000P_0402_50V7K 301_0402_1% 121K_0402_1%
VSUM+_VGA 1 2 1 2 1 2 1 2
G2
S2
S2
S2
1
330P_0402_50V7K
@ PCV27
VGA@ VGA@
2.61K_0402_1%
BST1_VGA
3
6
1
VGA@ PRV29 PRV31 PCV29

10K_0402_5%_ERTJ0ER103J
VGA@ PRV28
0.033U_0402_16V7K
0.15U_0603_16V7K
1.37K_0402_1% 22.1K_0402_1% 390P_0402_50V7K

11K_0402_1%
1
1 2 1 2 1 2
2
1
1
VGA@ PRV30
VGA@ PCV28
VGA@ PCV30
LG1_VGA
VGA@ VGA@
1 2
PRV32 PCV31
2
2
VGA@ PHV02
2K_0402_1% 330P_0402_50V
2
1 2 1 2
B B
VGA@ PRV33
2
665_0402_1%
VSUM-_VGA 1 2
@
PRV34
1
VGA@ @ PRV35
PCV32 100_0402_1% 2 1
0.1U_0603_50V7K 1 2 1 2 VCCSENSE_VGA <45>
2
0_0402_5%
@ PCV33 @ PRV36
820PF_0402_50V7K 2 1
VSSSENSE_VGA <45>
0_0402_5%
0.01U_0402_50V7K
1
VGA@ PCV34
2
A A

PWR_VGA_CORE
5 4 3 2 1
A B C D
Main Func = +1.35VGPUP
Vinafix.com
1 1
' '#,
+ , (
G 8 , (
1
@ PRW05
. 8 L ( 0 7 <; -
100K_0402_5% +D (H
VGA@ PRW06 VGA@ PCW12
G ##, 5 5 6 #4, 5 5
2
10_0603_5% 0.1U_0402_10V6K
BST_+1.35VGPU 1 2 BST_+1.35VGPU_R 1 2
@VGA@EMI@ PLW11
5A_Z120_25M_0805_2P @ PJPW02
1 2 VGA@ PUW01 1 2
1 2
'#, ) " ) 0H
1
RT6226AGQUF_UQFN12_3X3 '#,
VGA@ PLW01 JUMP_43X118
PGOOD
BOOT
@ PJPW01 1UH_6.6A_20%_5X5X3_M
1 2 +19VB_+1.35VGPU 5 2 LX_+1.35VGPU 1 2
'#L ! VIN LX '#,
JUMP_43X39
82P_0402_50V8J
0.1U_0402_25V6
1000P_0402_50V7K
1000P_0402_50V7K
2200P_0402_50V7K
10U_0805_25V6K~D
10U_0805_25V6K~D
1
@VGA@ PCW14
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
10 330P_0402_50V7K
@VGA@EMI@ PCW15
VGA@EMI@ PCW16
VGA@EMI@ PCW01
VGA@EMI@ PCW02
VGA@ PCW03
VGA@ PCW04
Mad@VGA@RF@ PCW17
FB
1
VGA@MAD@RF@
VGA@ PCW05
VGA@ PCW06
VGA@ PCW07
VGA@ PCW08
' (%
2
6 11 2 1 PRW07
2
2
EN BYP VGA@ PRW11 4.7_1206_5%
2
1
12 9 2.2_0402_1%
ILMT VCC
PGND
AGND
@VGA@ PRW13
1U_0402_10V6K
1U_0402_10V6K
2
1
1
1K_0402_1%
NC
VGA@ PCW10
VGA@ PCW11
Vfb=0.6
SNUB_+1.35VGPU
2 2
R1
LIMT_+1.35VGPU
2
FB__+1.35VGPU 1 2
VGA@ PRW09
LX_+1.35VGPU
1
39.2K_0402_1%
VGA@ PRW10
PRW01
1
@ 31.6K_0402_1%
1 2 EN_+1.35VGPU PCW13
R2
<12,63> DGPU_PWROK 680P_0603_50V7K
2
0_0402_5% VGA@MAD@RF@
1
@ PCW09
VGA@ PRW02 0.1U_0402_25V6 ' (%
1M_0402_1%
2
2
@ PRW03
0_0402_5%
2
1
@ PRW04
0_0402_5%
2
3 3
4 4

PWR_+1.35VGPUP
A B C D
5 4 3 2 1
!
Vinafix.com
D D
0.1(X00)
1 P51 PWR 20160321 COMPAL
0.1(X00)
2 P56 PWR 20160321 COMPAL
C 3 C
B B
7
A A

Changed-List PWR History
5 4 3 2 1

Dell LATITUDE 3490 3590 LA-F116P PDF

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A B C D E

PCB R1 PCB R3 ZZZ PCB R1

KBL R1 KBL R3 + SA0000BVB0L

S IC A31 FJ8067703281813 QN5C Y0 1.8G S IC FJ8067702739932 SR348 H0 2.3G A31!

S IC FJ8066201931106 SR2UW D1 2G A31! S IC FJ8066201931106 SR2UW D1 2G A31!

Loki/Loki-L Block Diagram

USB2.0 x 1 Port 3 (USB2.0 Type-A)

USB3.0 x 1 # USB3.0 re-driver USB3.0 x 1

RJ45 CC , USB2.0 Transformer CC , USB2.0 LAN 10/100 PCIe x 1 USB2.0 x 1

PCH-LP USB2.0 x 1 Touch screen

eMMC 256 GB eMMC

HDA CODEC HDA RTC

# ----> Loki-L only

Keyboard PWM FAN Thermal sensor

S3 (Suspend to RAM) / M3 LOW HIGH HIGH ON ON OFF OFF

G3 OFF OFF OFF OFF OFF OFF OFF

Security Classification Compal Secret Data

PJPH01 POK PJPH02 SIO_SLP_S4 #

PJP2501 SIO_SLP_S4 # PJP2502

Security Classification Compal Secret Data

SMBus Address: 0x41 / 0x41

' (% )" 3(3 ;. + 3(3 ;.

SMB02_CLK SMB02_DATA ( ;. 3(3 ;.

Security Classification Compal Secret Data

Main Func = CPU

2 1 CPU_DP1_CTRL_CLK E55 C47

B31 CSI2_DN6 AP2

Security Classification Compal Secret Data

Main Func = CPU

<20> DDR_A_D[0..15] DDR_A_D0

Buffer with Open Drain Output For VTT power control

SM_RCOMP1 RC11 1 2 80.6_0402_1%

Security Classification Compal Secret Data

Main Func = CPU +3VS

+3.3V_SPI MOW 2015WW06

1 2 PCH_SPI_D2 ,0( ( +3VALW_PCH

UC3 0.1U_0402_25V6 GPP_C5 1 2

Security Classification Compal Secret Data

Main Func = CPU

+3VS UC1F SKL-U

GPP_B18/GSPI0_MOSI GPP_D11 P1 RTC_DET#

AP5 N3 RC213 10K_0402_5%

VRAM ID VBIOS_ID2 VBIOS_ID1

LAF116 VRAM x32*2pcs

Security Classification Compal Secret Data

Main Func = CPU

Security Classification Compal Secret Data

Main Func = CPU XTAL24_IN_R

S IC 74AHC1G08GW SOT353 AND GEN8@ 4 .:?0 0# / 7#$/ ?; $0 1 0 :7; $ ? , =#2 :0 -=#7/./,0

100K_0402_5% SA00000OH00 2N7002K_SOT23-3

S IC MC74VHC1G08DFT2G SC70 SIO_SLP_LAN#

POK & & 7 $7: 0 +3VALW

S IC MC74VHC1G08DFT2G SC70 5P AND

IN1 4 PCH_RSMRST#_Q MAD@

S IC 74AHC1G08GW SOT353 AND

Main Func = CPU

RC123 1 2 33_0402_5% HDA_SYNC BA22

+3VALW_PCH +3VALW_PCH TPM@

RC128 8.2K_0402_5% RC129 4.7K_0402_5% TPM_ID

9 & =#?; /?7$ -0 $ /7:$ 02 E/$$ %/ FTPM@

Security Classification Compal Secret Data

Main Func = CPU

1 @ 2 CFG0 UC1S SKL-U