M09 Maybach UMA: uFCPGA Mobile Penryn Intel Cantiga GM + ICH9M

A B C D E
COMPAL CONFIDENTIAL
MODEL NAME : JAL20
1 1
PCB NO : LA-4041P (DA800009Y1L)

BOM NO : 43153231L01(TPM)
43153231L02 (Non TPM)
M09 Maybach UMA

2
uFCPGA Mobile Penryn 2
Intel Cantiga GM + ICH9M
2008-06-16
REV : 1.0(A00)
3
@ : Nopop Component 3
3@ : disable TPM
4@ : enable TPM
Fix Function Field
4 4
MB PCB
Part Number Description
DELL CONFIDENTIAL/PROPRIETARY
DA800009Y1L PCB 03N LA-4041P REV1 M/B
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Cover Sheet
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-4041P
Date: Monday, June 16, 2008 Sheet 1 of 56
A B C D E
A B C D E
Block Diagram
Compal confidential FAN Thermal Clock Generator
Model : JAL20 +FAN1_VOUT GUARDIAN III Pentium-M CPU ITP Port CK505
page 18
EMC4002 Penryn -4MB (Socket P) +1.05V_VCCP page 7 SLG8LP554
+3.3V_M page6
+3.3V_M page 18
+1.5V_RUN uFCPGA CPU
1 1
+VCC_CORE
+1.05V_VCCP 478pin page 7,8,9
H_A#(3..35) H_D#(0..63)
System Bus
CRT CONN RGB FSB 800/1066 MHz
+5V_RUN page 20 Vedio Switch RGB DDRII-DIMM X2
TS3DV520ERHUR Memory BUS
RGB SVID SVID BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8
+3.3V_RUN page 20 (DDR2) +1.8V_MEM 667 / 800MHz
page 16,17
DP CONN DPB +3.3V_RUN INTEL +1.8V_MEM
+3.3V_RUN page 21 DP Switch DPB +0.9V_DDR_VTT
+1.8V_MEM
DPB TS2DP512 Cantiga
+5V_RUN page 21 +1.5V_RUN
DPC +1.05V_M 1329pin BGA
USB[11]
Camera Through LVDS Cable
+VCC_GFXCORE +5V_RUN page 19
LVDS CONN LVDS +1.05V_VCCP page 10,11,12,13,14,15
+INV_PWR_SRC
Repeater SATA4 E-SATA
+5V_ALW
DMI
+3.3V_RUN USB[2,3] L SIDE
2 DOCKING PCI BUS +3VRUN 33MHz +1.5V_RUN
USB Ports X2 USB2 : Left side top 2
+LCDVDD page 19 100MHz
+LOM_VCT IDSEL:AD17 +5V_ALW page 33 USB3 Left side bottom
PORT (GNT1#,REQ1#)
+DOCK_PWR_BAR (PIRQB#,PIRQD#,PIRQC#)
page 35
USB0 : Right side pair top
SD/MMC 48MHz USB[0,1] R SIDE
DAI CardBus +RTC_CELL INTEL USB Ports X2 USB1 : Right side pair bottom
+5V_ALW
USB[8,9] CONN page 31
R5C847 SNIFFER +1.05V_VCCP
page 33
On IO/B
SATA3
+3.3V_RUN_CARD
+3.3V_RUN page 31,32 IEEE1394 +3.3V_RUN
ICH9-M +3V_RUN/ +1.5V_RUN 100MHz
page 31 GLCI/LCI
DOCK LPC BUS Through CABLE to SD Board +1.5V_RUN 676pin BGA PCIE6
Azalia I/F
Through CABLE to IO Board +3.3V_ALW_ICH
+3.3V_RUN/ +1.5V_RUN 100MHz PCI Express BUS
+3.3V_LAN page 22,23,24,25 S-ATA 0/1
Intel Boazman
PCIE4 PCIE3 PCIE2 PCIE1 AMP & INT. 82567LM
SATA1 SATA0 +3.3V_ALW
Express card Mini Card3 Mini Card2 Mini Card 1 Speaker +1.8V_LAN_M
+1V_LAN_M page 29
+3.3V_CARDAUX SPI +5V_RUN page 28
+1.5V_CARD WPAN/BT/Robson WWAN E-Module S-HDD
+3.3V_CARD WLAN +3.3V_RUN
W25X32VSSIG +5V_HDD
page 32 +3.3V_RUN +3.3V_WLAN +1.5V_RUN SIM card LPC BUS +5V_MOD +3.3V_HDD
+1.5V_RUN page 34 +1.5V_RUN page 34 +SIM_PWR page 34 +3.3V_LAN page 24 page 26 page 26 Azalia Codec LAN SWITCH
page 34 +3.3V_RUN
USH TPM1.2 33MHz
92HD71B PI3L500-AZFEX
3 32Mbit +3.3V_RUN 3
USB[7] USB[6] USB[4] USB[5] +3.3V_LAN pg 30
BCM5880 +VDDA page 27
+3.3V_RUN
+2.5V_AVDD_5880
Smart Card 73S8009CN +1.2V_AVDD_5880
+SC_VCC page 36 page 36
+3.3V_RUN page 36 RJ45
page 33
RFID USB[10] HeadPhone &
page 36
USBH
SMSC KBC MIC Jack
+3.3V_RUN page 33
MEC5035 On IO/B
SMBUS +RTC_CELL
+3.3V_ALW page 38 BC BUS
Through Cable SMSC SIO DAI
BC BUS MDC SSM2602 DOCK
DOCK LPC BUS ECE5028 +3V_SUS +3.3V_RUN page 27
Touch Pad Stick +3.3V_ALW
page 37
page 33
Biometric
+5V_RUN
+5V_ALW
+5V_RUN ECE1077
+3.3V_RUN page 33 +3.3V_ALW +3.3V_ALW On IO/B
+3.3V_RUN page 39 Dig. MIC
4
page 19 4
RJ11
Through LVDS Cable
VCORE (IMVP-6) 3V/5V NB_CORE Selector Int.KBD & Stick
page 39 MDC Cable DELL CONFIDENTIAL/PROPRIETARY
page 47 page 44 page 49 page 50
Title
CHARGER 1.5V/1.05V DC IN/BATT IN Block Diagram

1.8V/0.9V Size Document Number Rev
1.0
page 48 page 45 page 43 page 46 LA-4041P
Date: Thursday, June 05, 2008 Sheet 2 of 56
A B C D E
5 4 3 2 1
POWER STATES USB PORT# DESTINATION

Signal SLP SLP SLP S4 SLP ALWAYS M SUS RUN CLOCKS
State S3# S4# S5# STATE# M# PLANE PLANE PLANE PLANE 0 JUSB1 (Ext Right Side Top)
D
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH HIGH ON ON ON ON ON 1 JUSB1 (Ext Right Side Bottom) D
S3 (Suspend to RAM) / M1 LOW HIGH HIGH HIGH HIGH ON ON ON OFF ON 2 JESA1 (Ext Left Side Top)
S4 (Suspend to DISK) / M1 LOW HIGH HIGH LOW HIGH ON ON ON OFF ON 3 JESA1 (Ext Left Side Bottom)
S5 (SOFT OFF) / M1 LOW HIGH LOW LOW HIGH ON ON ON OFF ON 4 WLAN

ICH9-M
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH HIGH LOW ON OFF ON OFF OFF 5 WWAN
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW LOW ON OFF OFF OFF OFF 6 WPAN
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW LOW ON OFF OFF OFF OFF 7 Card Bus/Express card
8 DOCKING
C
PM TABLE 9 DOCKING C
+15V_ALW +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M 10 USH->BIO

+5V_ALW +1.8V_MEM +3.3V_RUN +1.05V_M +1.05V_M
+3.3V_ALW_ICH +2.5V_RUN (M-OFF) 11 Camera
power
plane +3.3V_RTC_LDO +1.5V_RUN
+0.9V_DDR_VTT
+VCC_GFXCORE
+VCC_CORE
+1.05V_VCCP PCI EXPRESS DESTINATION
State
Lane 1 MINI CARD-1 WWAN

S0 ON ON ON ON ON
Lane 2 MINI CARD-2 WLAN
S3 ON ON OFF ON OFF
Lane 3 MINI CARD-3 BT/UWB
B
S5 S4/AC ON OFF OFF ON OFF
Lane 4 EXPRESS CARD B
S5 S4/AC don't exist OFF OFF OFF OFF OFF

Lane 5 None
Lane 6 10/100/1G LAN
PCI TABLE
PCI DEVICE IDSEL REQ#/GNT# PIRQ
R5C847 AD17 REQ#1 / GNT#1 PIRQ[B..D]
A A
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Index and Config.
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-4041P
5 4 3 2 1
5 4 3 2 1
RUN_ON SI3457DV
( Q17 ) +INV_PWR_SRC
ADAPTER
D D
GFX_CORE_ON ADP3209
+VGFX_COREP
(PU11)
+PWR_SRC
BATTERY
CHARGER
MAX8786 TPS51116 SN0608098 SN0608098
(PU7) (PU4) (PU3) (PU2) ALWON
C C
+3.3V_ALW
0.9V_DDR_VTT_ON
1.5V_RUN_ON
IMVP_VR_ON
ENAB_3VLAN
M_ON
M_ON
ICH_ALW_ON
3.3V_RUN_ON
DDR_ON
SUS_ON
ALW_ON
SN0608098 STS11NF30L
+VCC_CORE +1.8V_MEM +0.9V_DDR_VTT +1.05V_M +1.5V_RUN STS11NF30L SI4336DY SI3456BDV SI3456BDV
(PU2) (Q44) (Q61) (Q54) (Q60) (Q66)
1.05V_RUN_ON
+15V_ALW
+5V_ALW
RUN_ON +3.3V_LAN +3.3V_RUN +3.3V_ALW_ICH +3.3V_M
B B
STS11NF30L +5V_RUN SI34336DY
REGCTL_PNP18
(Q55) (Q67)
MODC_EN
HDDC_EN
RUN_ON
EMC4002 +3.3V_SUS
BCP69
LDO Out
(Q45)
(U3)
SI3456BDV SI3456BDV MAX9789A
+1.05V_VCCP
(Q32) (Q29) (U22)
+1.8V_LAN_M +1.8V_RUN
A A
+5V_HDD +5V_MOD +VDDA

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Rail
LA-4041P
5 4 3 2 1
5 4 3 2 1
2.2K 2.2K
+3.3V_ALW_ICH 2.2K +3.3V_M

2.2K
G16 ICH_SMBCLK MEM_SCLK 197
2N7002 MEM_SDATA
A13 ICH_SMBDATA 195 DIMMA SMBUS Address [TBD]
2N7002
10K
ICH9-M 197
D
10K
+3.3V_ALW_ICH 195
SMBUS Address [TBD] D
DIMMB
C17 AMT_SMBCLK
B18 AMT_SMBDAT
2.2K
93 94 2.2K +5V_ALW
2A 2A 6 DOCK_SMB_CLK 6
1A
5 DOCK_SMB_DAT 5 DOCKING SMBUS Address [TBD]
1A
2.2K
2.2K
+3.3V_ALW
8 LCD_SMBCLK 6
1B INVERTER
C 7 C
LCD_SMDATA 5 SMBUS Address [TBD]
1B (JLVDS)
2.2K
2.2K +3.3V_ALW
1C 112 PBAT_SMBCLK 100 ohm 3
PBAT_SMBDAT
BATTERY SMBUS Address [TBD]
1C 111 100 ohm 4
KBC CONN
2.2K
+3.3V_SUS
2.2K
10
1D EXP_SMBCLK 7
9 2N7002
1D EXP_SMBDATA 8 Express card SMBUS Address [TBD]
2.2K 2N7002
100
1E 2.2K
99
+3.3V_ALW +3.3V_WLAN
1E
2.2K 2.2K
B 30 B
WLAN_SMBCLK
1F 98 CARD_SMBCLK
2N7002 WLAN_SMBDATA 32 WLAN SMBUS Address [TBD]
1F 97 CARD_SMBDAT
2N7002
2.2K
MEC 5035 2.2K
+3.3V_RUN
96 2N7002 MINI_SMBCLK 30
1G
95 MINI_SMBDATA 32 BT/UWB SMBUS Address [TBD]
1H 2N7002
32 30
SMBUS Address [TBD]

2.2K WWAN
2.2K
+3.3V_ALW +3.3V_M
2.2K 2.2K
12 CKG_SMBDAT CLK_SDATA
1H 17
2N7002
13 CKG_SMBCLK CLK_SCLK 16 CLK GEN SMBUS Address [TBD]
1H 2N7002
9 DAI_SMBDATA
A
Charger 2N7002 A
106 10 DAI_SMBCLK DAI
1J
105 2N7002
1J
Dedicated JTAG SMBUS Address [TBD]
2.2K SMBUS Address [TBD]
2.2K
+3.3V_RUN Compal Electronics, Inc.
103 Title
1K
102 Dedicated JTAG SMBUS TOPOLOGY
1K Size Document Number Rev
1.0
LA-4041P
5 4 3 2 1
5 4 3 2 1
+3.3V_M +CK_VDD_MAIN
1 2 +CK_VDD_MAIN
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
L1
+3.3V_M BK2125HS601-T 0805~D
1 1 1 1 1 1 1
2.2K_0402_5%~D
2.2K_0402_5%~D
0_0805_5%~D
1
2
C1
C2
C3
C4
C5
C6
C7
+3.3V_RUN
R851
2 2 2 2 2 2 2
R1
R2
1 2
@ R3
@R3
0_0402_5%~D +CK_VDD_MAIN2 MINI1CLK_REQ# 1 2
1
R4 10K_0402_5%~D
6 1 CLK_SDATA 1 2 MINI2CLK_REQ# 1 2
<27,38,48> CKG_SMBDAT
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
@ L2
@L2 R5 10K_0402_5%~D
Q1A BLM21PG600SN1D_0805~D 1 1 1 CLK_3GPLLREQ# 1 2
D 2N7002DW-T/R7_SOT363-6~D @ R6 10K_0402_5%~D D
C8
C9
C10
+3.3V_M SATA_CLKREQ# 1 2
R7 10K_0402_5%~D
5
Q1B +CK_VDD_48 +CK_VDD_REF 2 2 2 MINI3CLK_REQ# 1 2
2N7002DW-T/R7_SOT363-6~D R8 10K_0402_5%~D
4.7U_0603_6.3V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V7K~D
3 4 CLK_SCLK EXPCLK_REQ# 1 2
<27,38,48> CKG_SMBCLK
1 1 1 R356 10K_0402_5%~D
@
C11
C12
C13
1 2
@R9
@R9 1 2 +CK_VDD_A
2 2 2
4.7U_0603_6.3V4Z~D
0.047U_0402_16V4Z~D
0_0402_5%~D R10 2.2_0603_5%~D
1 1
C14
C15
U1
2 2
FSC FSB FSA CPU SRC PCI 1 7
VDD_SRC VDD_A
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz 49 VDD_SRC
54
65
VDD_SRC
VDD_SRC
SLG8LP554VTR VSS_A 8
0 0 0 266 100 33.3

* PCI_STP# 25 H_STP_PCI#
H_STP_PCI# <24>
30 VDD_PCI
0 0 1 133 100 33.3 36 24 H_STP_CPU#
VDD_PCI CPU_STP# H_STP_CPU# <24>
12 VDD_CPU
0 1 0 200 100 33.3 X1 11 MCH_BCLK 1 2 CLK_MCH_BCLK
CPU_1 CLK_MCH_BCLK <10>
14.31818MHz_20P_1BX14318CC1A~D 1 2 +CK_VDD_REF 18 R11 33_0402_5%~D
R12 0_0603_5%~D VDD_REF MCH_BCLK# CLK_MCH_BCLK#
2 1 CPU_1# 10 1 2 CLK_MCH_BCLK# <10>
0 1 1 166 100 33.3 C16 1 2 +CK_VDD_48 40 VDD_48
R13 33_0402_5%~D
1
33P_0402_50V8J~D R14 0_0603_5%~D
C CPU_BCLK CLK_CPU_BCLK C
CPU_0 14 1 2 CLK_CPU_BCLK <7>
1 0 0 333 100 33.3 Place crystal within CLK_XTAL_IN 20 R15 33_0402_5%~D
C17 XTAL_IN CPU_BCLK# CLK_CPU_BCLK#
500 mils of CK505 13 1 2 CLK_CPU_BCLK# <7>
2
33P_0402_50V8J~D CPU_0# R16 33_0402_5%~D
1 0 1 100 100 33.3 2 1 1 2 CLK_XTAL_OUT 19
R17 0_0402_5%~D XTAL_OUT CPU_ITP CLK_CPU_ITP
CPU_ITP/SRC_10 6 1 2 CLK_CPU_ITP <7>
R18 @ 33_0402_5%~D
1 1 0 400 100 33.3 CLK_ICH_48M R19 2 1 39_0402_5%~D FSA 41 5 CPU_ITP# 1 2 CLK_CPU_ITP#
<24> CLK_ICH_48M USB_48MHz/FSLA CPU_ITP#/SRC_10# CLK_CPU_ITP# <7>
<8,10> CPU_MCH_BSEL0 CPU_MCH_BSEL0 R22 1 2 2.2K_0402_5%~D R21 @ 33_0402_5%~D
<8,10> CPU_MCH_BSEL1 CPU_MCH_BSEL1 R1044 1 2 0_0402_5%~D FSB 45 FSL_B/TEST_MODE PCIE_MINI1 CLK_PCIE_MINI1
SRC_9 3 1 2 CLK_PCIE_MINI1 <34>
<8,10> CPU_MCH_BSEL2 CPU_MCH_BSEL2 R24 1 2 10K_0402_5%~D FSC 23 R23 33_0402_5%~D
REF_0/FSL_C/TEST_SEL PCIE_MINI1# CLK_PCIE_MINI1#
SRC_9# 2 1 2 CLK_PCIE_MINI1# <34>
R25 33_0402_5%~D
+3.3V_M CLK_PCI_5028 R26 2 1 39_0402_5%~D PCI_SIO 34 72 MINI1CLK_REQ# MINI1CLK_REQ# <34>
<37> CLK_PCI_5028 PCICLK4/FCT_SEL CLKREQ_9#
CLK_PCI_TPM R29 2 1 39_0402_5%~D PCI_TPM 33 70 PCIE_MINI2 1 2 CLK_PCIE_MINI2
<36> CLK_PCI_TPM PCICLK3 SRC_8 CLK_PCIE_MINI2 <34>
1
R28 33_0402_5%~D
@ R51
@R51 CLK_PCI_PCM R30 2 1 22_0402_5%~D 32 69 PCIE_MINI2# 1 2 CLK_PCIE_MINI2#
<31> CLK_PCI_PCM PCICLK2/TME SRC_8# CLK_PCIE_MINI2# <34>
10K_0402_5%~D CLK_PCI_DOCK R27 1 2 22_0402_5%~D PCI_DOCK R31 33_0402_5%~D
<35> CLK_PCI_DOCK
CLK_PCI_5035 R32 2 1 39_0402_5%~D PCI_EC 27 71 MINI2CLK_REQ# MINI2CLK_REQ# <34>
<38> CLK_PCI_5035 PCICLK1 CLKREQ_8#
2
FSA CLK_ICH_14M R33 1 2 22_0402_5%~D 66 PCIE_ICH 1 2 CLK_PCIE_ICH

<24> CLK_ICH_14M SRC_7 CLK_PCIE_ICH <24>
CLKREF 22 R34 33_0402_5%~D
REF_1
1
CLK_SIO_14M R35 1 2 22_0402_5%~D 67 PCIE_ICH# 1 2 CLK_PCIE_ICH#

<37> CLK_SIO_14M SRC_7# CLK_PCIE_ICH# <24>
@ R55
@R55 R36 33_0402_5%~D
10K_0402_5%~D MCH_DREFCLK R37 1 2 33_0402_5%~D DOT96 43 38
<10> MCH_DREFCLK DOT_96/27M CLKREQ_7#
MCH_DREFCLK# R38 1 2 33_0402_5%~D DOT96# 44 63 PCIE_MINI3 1 2 CLK_PCIE_MINI3
<10> MCH_DREFCLK# CLK_PCIE_MINI3 <34>
2
DOT_96#/27M_SS SRC_6 R39 33_0402_5%~D

64 PCIE_MINI3# 1 2 CLK_PCIE_MINI3#
SRC_6# CLK_PCIE_MINI3# <34>
CLK_PCI_ICH R41 2 1 33_0402_5%~D PCI_ICH 37 R40 33_0402_5%~D
B <22> CLK_PCI_ICH PCICLK_F0/ITP_EN B
62 MINI3CLK_REQ# MINI3CLK_REQ# <34>
CLKREQ_6#
+3.3V_RUN CLK_PWRGD 39 60
<24> CLK_PWRGD CKPWRGD/PD# SRC_5
10K_0402_5%~D
SRC_5# 61
2
9 NC
R43
TME PIN 32 CLKREQ_5# 29
0 overclocking enabled 58 PCIE_EXP 1 2 CLK_PCIE_EXP

SRC_4 CLK_PCIE_EXP <32>
CLK_SCLK 16 R408 33_0402_5%~D
1
SMBCLK PCIE_EXP# CLK_PCIE_EXP#

1 overclocling disabled 59 1 2
PCI_DOCK * SRC_4#
EXPCLK_REQ#
R415 33_0402_5%~D
CLK_PCIE_EXP# <32>
CLKREQ_4# 57 EXPCLK_REQ# <32>

+3.3V_RUN CLK_SDATA 17 SMBDAT MCH_3GPLL CLK_MCH_3GPLL
SRC_3 55 1 2 CLK_MCH_3GPLL <10>
10K_0402_5%~D
R45 33_0402_5%~D
2
4 56 MCH_3GPLL# 1 2 CLK_MCH_3GPLL# CLK_MCH_3GPLL# <10>

VSS_SRC SRC_3#
R46
ITP_EN PIN 37 R47 33_0402_5%~D

15 28 CLK_3GPLLREQ#_R 1 2 CLK_3GPLLREQ# CLK_3GPLLREQ# <10>
VSS_CPU CLKREQ_3# R48 475_0402_1%~D
0 Pin 5/6 as SRC_10
21 52
1
VSS_REF SRC_2
1 Pin 5/6 as CPU_ITP
PCI_ICH * 31 VSS_PCI SRC_2# 53
+3.3V_RUN 35 26
VSS_PCI CLKREQ_2#
10K_0402_5%~D
42 50 PCIE_SATA 1 2 CLK_PCIE_SATA CLK_PCIE_SATA <23>

VSS_48 SRC_1/SATA
2
@ R49 33_0402_5%~D
R50
68 51 PCIE_SATA# 1 2 CLK_PCIE_SATA# CLK_PCIE_SATA# <23>

VSS_SRC SRC_1#/SATA# R52 33_0402_5%~D
46 SATA_CLKREQ#_R 1 2 SATA_CLKREQ# <24>
CLKREQ_1# R53 475_0402_1%~D
FCTSEL1 PIN43 PIN44 PIN47 PIN48 73
1
A PCI_SIO THRM_PAD DOT96_SSC A

LCD_CLK/SRC_0 47 1 2 DREF_SSCLK <10>
10K_0402_5%~D
R523 33_0402_5%~D
1
0=UMA DOT96T DOT96C 96/100M_T 96/100M_C 48 DOT96_SSC# 1 2

* LCD_CLK#/SRC_0# DREF_SSCLK# <10>
R54
R670 33_0402_5%~D
1=DIS 27M_out 27M SSout SRCT0 SRCC0

SLG8LP554VTR_QFN72_10X10~D
2

0=UMA TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
1=Disc. GRFX down BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Clock Generator
LA-4041P
Date: Friday, June 13, 2008 Sheet 6 of 56
5 4 3 2 1
5 4 3 2 1
+1.05V_VCCP
29
<10> H_A#[3..35]
JCPU1A JITP1 @
H_A#3 J4 H1 H_ADS#
GND6
A[3]# ADS# H_ADS# <10>
ADDR GROUP_0
H_A#4 L5 E2 H_BNR# 28
A[4]# BNR# H_BNR# <10> VTT1
H_A#5 L4 G5 H_BPRI# 27
A[5]# BPRI# H_BPRI# <10> VTT0
H_A#6 K5 26 JCPU1D
H_A#7 A[6]# H_DEFER# ITP_DBRESET# VTAP
M3 A[7]# DEFER# H5 H_DEFER# <10> 25 DBR# A4 VSS[001] VSS[082] P6
H_A#8 N2 F21 H_DRDY# 24 A8 P21
A[8]# DRDY# H_DRDY# <10> DBA# VSS[002] VSS[083]
H_A#9 J1 E1 H_DBSY# ITP_BPM#0 R780 1 @ 2 0_0402_5%~D 23 A11 P24
D A[9]# DBSY# H_DBSY# <10> BPM0# VSS[003] VSS[084] D
H_A#10 N3 22 A14 R2
H_A#11 A[10]# H_BR0# ITP_BPM#1 R781 1 @ GND5 VSS[004] VSS[085]
P5 A[11]# BR0# F1 H_BR0# <10> 2 0_0402_5%~D 21 BPM1# A16 VSS[005] VSS[086] R5
H_A#12 P2 +1.05V_VCCP 20 A19 R22
A[12]# GND4 VSS[006] VSS[087]
CONTROL
H_A#13 L2 D20 H_IERR# 2 1 ITP_BPM#2 R782 1 @ 2 0_0402_5%~D 19 A23 R25
H_A#14 A[13]# IERR# H_INIT# R56 56_0402_5%~D BPM2# VSS[007] VSS[088]
P4 A[14]# INIT# B3 H_INIT# <23> 18 GND3 AF2 VSS[008] VSS[089] T1
H_A#15 P1 ITP_BPM#3 R783 1 @ 2 0_0402_5%~D 17 B6 T4
H_A#16 A[15]# H_LOCK# BPM3# VSS[009] VSS[090]
R1 A[16]# LOCK# H4 H_LOCK# <10> 16 GND2 B8 VSS[010] VSS[091] T23
H_ADSTB#0 M1 ITP_BPM#4 R784 1 @ 2 0_0402_5%~D 15 B11 T26
<10> H_ADSTB#0 ADSTB[0]# BPM4# VSS[011] VSS[092]
C1 H_RESET# 14 B13 U3
RESET# H_RESET# <10> GND1 VSS[012] VSS[093]
H_REQ#0 K3 F3 H_RS#0 ITP_BPM#5 R789 1 @ 2 0_0402_5%~D 13 B16 U6
<10> H_REQ#0 REQ[0]# RS[0]# H_RS#0 <10> BPM5# VSS[013] VSS[094]
H_REQ#1 H2 F4 H_RS#1 H_RESET# 1 2 12 B19 U21
<10> H_REQ#1 REQ[1]# RS[1]# H_RS#1 <10> RESET# VSS[014] VSS[095]
H_REQ#2 K2 G3 H_RS#2 R57 @ 124_0402_1%~D ITP_TCK 11 B21 U24
<10> H_REQ#2 REQ[2]# RS[2]# H_RS#2 <10> FBO VSS[015] VSS[096]
H_REQ#3 J3 G2 H_TRDY# 10 B24 V2
<10> H_REQ#3 REQ[3]# TRDY# H_TRDY# <10> GND0 VSS[016] VSS[097]
H_REQ#4 L1 CLK_CPU_ITP 9 C5 V5
<10> H_REQ#4 REQ[4]# <6> CLK_CPU_ITP BCLKP VSS[017] VSS[098]
G6 H_HIT# CLK_CPU_ITP# 8 C8 V22
HIT# H_HIT# <10> <6> CLK_CPU_ITP# BCLKN VSS[018] VSS[099]
H_A#17 Y2 E4 H_HITM# ITP_TDO 1 2 7 C11 V25
A[17]# HITM# H_HITM# <10> TDO VSS[019] VSS[100]
H_A#18 U5 R930 @ 22.6_0402_1%~D 6 C14 W1
H_A#19 A[18]# ITP_BPM#0 ITP_TCK NC2 VSS[020] VSS[101]
R3 A[19]# BPM[0]# AD4 5 TCK C16 VSS[021] VSS[102] W4
ADDR GROUP_1
H_A#20 W6 AD3 ITP_BPM#1 4 C19 W23
H_A#21 A[20]# BPM[1]# ITP_BPM#2 ITP_TRST# NC1 VSS[022] VSS[103]
H_A#22
U4
Y5
A[21]# BPM[2]# AD1
AC4 ITP_BPM#3
Depop R57 & R930 ITP_TMS
3
2
TRST# C2
C22
VSS[023] VSS[104] W26
Y3
A[22]# BPM[3]# TMS VSS[024] VSS[105]
for Enhance ESD on dock issue
GND7
H_A#23 ITP_BPM#4 ITP_TDI
XDP/ITP SIGNALS
U1 A[23]# PRDY# AC2 1 TDI C25 VSS[025] VSS[106] Y6
H_A#24 R4 AC1 ITP_BPM#5 +1.05V_VCCP D1 Y21
H_A#25 A[24]# PREQ# ITP_TCK VSS[026] VSS[107]
T5 A[25]# TCK AC5 D4 VSS[027] VSS[108] Y24
H_A#26 T3 AA6 ITP_TDI MOLEX_52435-2891_28P~D D8 AA2
30
A[26]# TDI VSS[028] VSS[109]
1
H_A#27 W2 AB3 ITP_TDO D11 AA5
H_A#28 A[27]# TDO ITP_TMS R59 VSS[029] VSS[110]
W5 A[28]# TMS AB5 D13 VSS[030] VSS[111] AA8
H_A#29 Y4 AB6 ITP_TRST# 56_0402_5%~D D16 AA11
H_A#30 A[29]# TRST# ITP_DBRESET# VSS[031] VSS[112]
U2 A[30]# DBR# C20 ITP_DBRESET# <24> D19 VSS[032] VSS[113] AA14
H_A#31 V4 D23 AA16
2
H_A#32 A[31]# VSS[033] VSS[114]
W3 A[32]# D26 VSS[034] VSS[115] AA19
H_A#33 AA4 THERMAL EC_CPU_PROCHOT# E3 AA22
C H_A#34 A[33]# VSS[035] VSS[116] C
AB2 A[34]# E6 VSS[036] VSS[117] AA25
H_A#35 AA3 D21 H_THERMDA E8 AB1
H_ADSTB#1 A[35]# PROCHOT# H_THERMDA <18> VSS[037] VSS[118]
<10> H_ADSTB#1 V1 ADSTB[1]# THERMDA A24 2 E11 VSS[038] VSS[119] AB4
B25 @ C18 +1.05V_VCCP E14 AB8
H_A20M# THERMDC 100P_0402_50V8K~D VSS[039] VSS[120]
<23> H_A20M# A6 A20M# E16 VSS[040] VSS[121] AB11
ICH
H_FERR# A5 C7 E19 AB13

<23> H_FERR# FERR# THERMTRIP# 1 VSS[041] VSS[122]
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
H_IGNNE# C4 H_THERMDC E21 AB16
<23> H_IGNNE# IGNNE# H_THERMDC <18> VSS[042] VSS[123]
1 1 E24 VSS[043] VSS[124] AB19
H_STPCLK# D5 H_THERMTRIP# H_THERMDA, H_THERMDC routing together, F5 AB23
<23> H_STPCLK# STPCLK# H_THERMTRIP# <18> VSS[044] VSS[125]
C19
C20
H_INTR C6 H CLK F8 AB26
<23> H_INTR LINT0 Trace width / Spacing = 10 / 10 mil VSS[045] VSS[126]
H_NMI B4 A22 CLK_CPU_BCLK F11 AC3
<23> H_NMI LINT1 BCLK[0] CLK_CPU_BCLK <6> 2 2 VSS[046] VSS[127]
H_SMI# A3 A21 CLK_CPU_BCLK# F13 AC6
<23> H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# <6> VSS[047] VSS[128]
F16 VSS[048] VSS[129] AC8
M4 RSVD[01] F19 VSS[049] VSS[130] AC11
N5 RSVD[02] F2 VSS[050] VSS[131] AC14
T2 RSVD[03] F22 VSS[051] VSS[132] AC16
V3 RSVD[04] F25 VSS[052] VSS[133] AC19
B2 Place near JITP G4 AC21
RESERVED
RSVD[05] +1.05V_VCCP VSS[053] VSS[134]

D2 RSVD[06] G1 VSS[054] VSS[135] AC24
D22 RSVD[07] G23 VSS[055] VSS[136] AD2
D3 RSVD[08] G26 VSS[056] VSS[137] AD5
F6 RSVD[09] H3 VSS[057] VSS[138] AD8
@ H_RESET# +3.3V_ALW_ICH H6 AD11
R923 51_0402_1%~D VSS[058] VSS[139]
H21 VSS[059] VSS[140] AD13
H24 VSS[060] VSS[141] AD16
1 2 H_THERMTRIP# 1 2 ITP_DBRESET# J2 VSS[061] VSS[142] AD19
TYCO_1-1674770-2_Penryn~D R61 56_0402_5%~D R60 150_0402_5%~D J5 AD22
VSS[062] VSS[143]
J22 VSS[063] VSS[144] AD25
J25 VSS[064] VSS[145] AE1
+1.05V_VCCP K1 AE4
R785 VSS[065] VSS[146]
51_0402_5%~D
Place close to JITP within 1ns = 5000 mil K4 VSS[066] VSS[147] AE8
K23 VSS[067] VSS[148] AE11
B B
1 2 ITP_BPM#5 K26 VSS[068] VSS[149] AE14
@ L3 AE16
VSS[069] VSS[150]
L6 VSS[070] VSS[151] AE19
+1.05V_VCCP L21 AE23
R62 VSS[071] VSS[152]
Place close to CPU within 200 mil 56_0402_5%~D
L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2
1 2 ITP_TDO M5 AF6
VSS[074] VSS[155]
M22 VSS[075] VSS[156] AF8
M25 VSS[076] VSS[157] AF11
+1.05V_VCCP N1 AF13
ITP_TMS VSS[077] VSS[158]
1 2 N4 VSS[078] VSS[159] AF16
R64 39_0402_5%~D N23 AF19
ITP_TDI VSS[079] VSS[160]
1 2 N26 VSS[080] VSS[161] AF21
R65 150_0402_5%~D P3 A25
VSS[081] VSS[162]
VSS[163] AF25
1 2 ITP_TCK
1 2 ITP_TRST# R67 27_0402_5% TYCO_1-1674770-2_Penryn~D
R66 649_0402_1%~D
Place close to JITP within 200ps = 1000 mil

Place close to CPU within 200ps = 1000 mil
A A
Title
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Penryn Processor(1/2)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1.0
5 4 3 2 1
5 4 3 2 1
+VCC_CORE +VCC_CORE
JCPU1C
A7 VCC[001] VCC[068] AB20
A9 VCC[002] VCC[069] AB7
A10 VCC[003] VCC[070] AC7
A12 VCC[004] VCC[071] AC9
A13 VCC[005] VCC[072] AC12
A15 VCC[006] VCC[073] AC13
A17 VCC[007] VCC[074] AC15
A18 VCC[008] VCC[075] AC17
A20 VCC[009] VCC[076] AC18
B7 VCC[010] VCC[077] AD7
D D
<10> H_D#[0..63] B9 VCC[011] VCC[078] AD9
B10 VCC[012] VCC[079] AD10
B12 VCC[013] VCC[080] AD12
JCPU1B B14 AD14
H_D#0 H_D#32 VCC[014] VCC[081]
E22 D[0]# D[32]# Y22 B15 VCC[015] VCC[082] AD15
H_D#1 F24 AB24 H_D#33 B17 AD17
H_D#2 D[1]# D[33]# H_D#34 VCC[016] VCC[083]
E26 D[2]# D[34]# V24 B18 VCC[017] VCC[084] AD18
DATA GRP 0
H_D#3 G22 V26 H_D#35 B20 AE9
D[3]# D[35]# VCC[018] VCC[085]
DATA GRP 2
H_D#4 F23 V23 H_D#36 C9 AE10
H_D#5 D[4]# D[36]# H_D#37 VCC[019] VCC[086]
G25 D[5]# D[37]# T22 C10 VCC[020] VCC[087] AE12
H_D#6 E25 U25 H_D#38 C12 AE13
H_D#7 D[6]# D[38]# H_D#39 VCC[021] VCC[088]
E23 D[7]# D[39]# U23 C13 VCC[022] VCC[089] AE15
H_D#8 K24 Y25 H_D#40 C15 AE17
H_D#9 D[8]# D[40]# H_D#41 VCC[023] VCC[090]
G24 D[9]# D[41]# W22 C17 VCC[024] VCC[091] AE18
H_D#10 J24 Y23 H_D#42 C18 AE20
H_D#11 D[10]# D[42]# H_D#43 VCC[025] VCC[092]
J23 D[11]# D[43]# W24 D9 VCC[026] VCC[093] AF9
H_D#12 H22 W25 H_D#44 D10 AF10
H_D#13 D[12]# D[44]# H_D#45 VCC[027] VCC[094]
F26 D[13]# D[45]# AA23 D12 VCC[028] VCC[095] AF12
H_D#14 K22 AA24 H_D#46 D14 AF14
H_D#15 D[14]# D[46]# H_D#47 VCC[029] VCC[096]
H23 D[15]# D[47]# AB25 D15 VCC[030] VCC[097] AF15
<10> H_DSTBN#0 H_DSTBN#0 J26 Y26 H_DSTBN#2 H_DSTBN#2 <10> D17 AF17
H_DSTBP#0 DSTBN[0]# DSTBN[2]# H_DSTBP#2 VCC[031] VCC[098]
<10> H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 <10> D18 VCC[032] VCC[099] AF18
H_DINV#0 H25 U22 H_DINV#2 E7 AF20
<10> H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 <10> VCC[033] VCC[100]
E9 VCC[034]
E10 VCC[035] VCCP[01] G21 +1.05V_VCCP
H_D#16 N22 AE24 H_D#48 E12 V6
H_D#17 D[16]# D[48]# H_D#49 VCC[036] VCCP[02]
K25 D[17]# D[49]# AD24 E13 VCC[037] VCCP[03] J6
220U_D2_4VY_R15M~D
H_D#18 P26 AA21 H_D#50 E15 K6 1
H_D#19 D[18]# D[50]# H_D#51 VCC[038] VCCP[04]
R23 D[19]# D[51]# AB22 E17 VCC[039] VCCP[05] M6
H_D#20 L23 AB21 H_D#52 E18 J21 +
D[20]# D[52]# VCC[040] VCCP[06]
DATA GRP 1
C21
H_D#21 M24 AC26 H_D#53 E20 K21
D[21]# D[53]# VCC[041] VCCP[07]
H_D#22 L22 D[22]# DATA GRP 3
D[54]# AD20 H_D#54 F7 VCC[042] VCCP[08] M21
2
C H_D#23 H_D#55 C
M23 AE22 F9 N21
H_D#24 P25
D[23]#
D[24]#
D[55]#
D[56]# AF23 H_D#56 F10
VCC[043]
VCC[044]
VCCP[09]
VCCP[10] N6 CRB was 270uF
H_D#25 P23 AC25 H_D#57 F12 R21
H_D#26 D[25]# D[57]# H_D#58 VCC[045] VCCP[11]
P22 D[26]# D[58]# AE21 F14 VCC[046] VCCP[12] R6
H_D#27 T24 AD21 H_D#59 F15 T21
H_D#28 D[27]# D[59]# H_D#60 VCC[047] VCCP[13]
R24 D[28]# D[60]# AC22 F17 VCC[048] VCCP[14] T6
H_D#29 L25 AD23 H_D#61 F18 V21
H_D#30 D[29]# D[61]# H_D#62 VCC[049] VCCP[15]
T25 D[30]# D[62]# AF22 F20 VCC[050] VCCP[16] W21
H_D#31 N25 AC23 H_D#63 AA7
H_DSTBN#1 D[31]# D[63]# H_DSTBN#3 VCC[051]
<10> H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 <10> AA9 VCC[052] VCCA[01] B26 +1.5V_RUN
0.01U_0402_16V7K~D
10U_0805_10V4Z~D
<10> H_DSTBP#1 H_DSTBP#1 M26 AF24 H_DSTBP#3 H_DSTBP#3 <10> AA10 C26
H_DINV#1 DSTBP[1]# DSTBP[3]# H_DINV#3 VCC[053] VCCA[02]
<10> H_DINV#1 N24 DINV[1]# DINV[3]# AC20 H_DINV#3 <10> AA12 VCC[054]
AA13 AD6 VID0
VCC[055] VID[0] VID0 <47>
+V_CPU_GTLREF AD26 R26 COMP0 AA15 AF5 VID1 1 1
GTLREF COMP[0] VCC[056] VID[1] VID1 <47>
TEST1 C23 MISC U26 COMP1 AA17 AE5 VID2
TEST1 COMP[1] VCC[057] VID[2] VID2 <47>
C22
C23
TEST2 D25 AA1 COMP2 AA18 AF4 VID3
TEST2 COMP[2] VCC[058] VID[3] VID3 <47>
TEST3 C24 Y1 COMP3 AA20 AE3 VID4
TEST3 COMP[3] VCC[059] VID[4] VID4 <47> 2 2
PAD~D T25 TEST4 AF26 AB9 AF3 VID5
TEST4 VCC[060] VID[5] VID5 <47>
54.9_0402_1%~D
27.4_0402_1%~D
54.9_0402_1%~D
27.4_0402_1%~D
TEST5 AF1 E5 H_DPRSTP# AC10 AE2 VID6
TEST5 DPRSTP# H_DPRSTP# <10,23,47> VCC[061] VID[6] VID6 <47>
1
PAD~D T138 TEST6 A26 B5 H_DPSLP# AB10
TEST6 DPSLP# H_DPSLP# <23> VCC[062]
R68
R69
R70
R71
PAD~D T4 TEST7 C3 D24 H_DPWR# AB12
TEST7 DPWR# H_PWRGOOD H_DPWR# <10> VCC[063] VCCSENSE
<6,10> CPU_MCH_BSEL0 1 2 B22 BSEL[0] PWRGOOD D6 H_PWRGOOD <23> AB14 VCC[064] VCCSENSE AF7 VCCSENSE <47>
R1041 0_0402_5%~D B23 D7 H_CPUSLP# AB15
BSEL[1] SLP# H_CPUSLP# <10> VCC[065]
1 2 C21 AE6 H_PSI# AB17
H_PSI# <47>
2
<6,10> CPU_MCH_BSEL1 R1042 0_0402_5%~D BSEL[2] PSI# VCC[066] VSSSENSE
AB18 VCC[067] VSSSENSE AE7 VSSSENSE <47>
1 2 TYCO_1-1674770-2_Penryn~D
<6,10> CPU_MCH_BSEL2 R1043 0_0402_5%~D TYCO_1-1674770-2_Penryn~D
Resistor placed within 0.5" of

CPU pin.Trace should be at least Length match within 25 mils, Z0=27.4 ohm
B 25 mils away from any other B
toggling signal. COMP0, COMP2
trace should be 27.4 ohm.
TEST1 COMP1, COMP3 should be 55
TEST2 Place R75 and R76 near CPU
ohm.
PAD~D T144 TEST3
PAD~D T3 TEST5
+VCC_CORE
1K_0402_5%~D
1K_0402_5%~D
2
2
@R72
@
@R73
@
For the purpose of testability, route these signals

R72
R73
1 2 VCCSENSE 1 2
through a ground referenced Z0 = 55ohm trace that R75 100_0402_1%~D @R833
@ R833 27.4_0402_1%~D
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.
1
Reserve for testing

1 2 VSSSENSE
R76 100_0402_1%~D only
FSB BCLK BSEL2 BSEL1 BSEL0 +1.05V_VCCP
Route VCCSENSE and VSSSENSE trace at

1
533 133 0 0 1 27.4 ohms, 7 mils spacing and the placement should be within 1 inch (max)
R77
+V_CPU_GTLREF 1K_0402_1%~D
667 166 0 1 1
2
800 200 0 1 0
1
A A
1067 266 0 0 0 R78

2K_0402_1%~D
2
Layout close CPU PIN AD26 Compal Electronics, Inc.
Title
55 ohm, 0.5 inch (max) PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Penryn Processor(2/2)
1.0
5 4 3 2 1
5 4 3 2 1
+VCC_CORE
Place these inside 1 1 1 1 1 1 1 1 1 1

socket cavity on L8
(North side C24 C25 C26 C27 C28 C29 C30 C31 C32 C33
Secondary) 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
D 2 2 2 2 2 2 2 2 2 2 D
+VCC_CORE
Place these inside 1 1 1 1 1 1 1 1 1 1

socket cavity on L8
(Sorth side C34 C35 C36 C37 C38 C39 C40 C41 C42 C43
Secondary) 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
2 2 2 2 2 2 2 2 2 2
+VCC_CORE
Place these inside 1 1 1 1 1 1

socket cavity on L8
(North side C44 C45 C46 C47 C48 C49
Primary) 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
2 2 2 2 2 2
+VCC_CORE
Place these inside 1 1 1 1 1 1 10uF 0805 X6S -> 85 degree C

socket cavity on L8
(Sorth side C50 C51 C52 C53 C54 C55
C Primary) 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D C
2 2 2 2 2 2
High Frequence Decoupling
Near VCORE regulator.
+VCC_CORE
Board Bottom Side
Board Top Side
ESR <= 1.5m ohm

270U_X_2VM_R4.5M~D
270U_X_2VM_R4.5M~D
270U_X_2VM_R4.5M~D
270U_X_2VM_R4.5M~D
270U_X_2VM_R4.5M~D
270U_X_2VM_R4.5M~D
1 1 1 1 1 1
+ +
@
+ + + + Capacitor > 1320uF
C56
C57
C58
C59
C60
C61
@ @
2 2 2 2 2 2
B B
+1.05V_VCCP
1 1 1 1 1 1
Place these inside
C62 C63 C64 C65 C66 C67 socket cavity on L8
0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D (North side
2 2 2 2 2 2 Secondary)
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU Bypass
LA-4041P
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN U2B
1 2 SDVO_CTRLCLK RSVD1 M36 TP_MCH_RSVD1 T153PAD~D

R180 2.2K_0402_5%~D M_CLK_DDR0 TP_MCH_RSVD2
DDR CLK/ CONTROL/COMPENSATION

<16> M_CLK_DDR0 AP24 SA_CK_0 RSVD2 N36 T154PAD~D
1 2 SDVO_CTRLDATA <16> M_CLK_DDR1
M_CLK_DDR1 AT21 SA_CK_1 RSVD3 R33 TP_MCH_RSVD3 T155PAD~D
R181 2.2K_0402_5%~D M_CLK_DDR2 AV24 T33 TP_MCH_RSVD4 T156PAD~D
<17> M_CLK_DDR2 SB_CK_0 RSVD4
1 2 DDPC_CTRLCLK <17> M_CLK_DDR3
M_CLK_DDR3 AU20 SB_CK_1 RSVD5 AH9 TP_MCH_RSVD5 T157PAD~D
R182 2.2K_0402_5%~D AH10 TP_MCH_RSVD6 T158PAD~D
RSVD6
1 2 DDPC_CTRLDATA <16> M_CLK_DDR#0
M_CLK_DDR#0 AR24 SA_CK#_0 RSVD7 AH12 TP_MCH_RSVD7 T159PAD~D
R183 2.2K_0402_5%~D M_CLK_DDR#1 AR21 AH13 TP_MCH_RSVD8 T160PAD~D
<16> M_CLK_DDR#1 SA_CK#_1 RSVD8
Place close to U2. M_CLK_DDR#2 AU24 K12 TP_MCH_RSVD9 T5 PAD~D
<17> M_CLK_DDR#2 SB_CK#_0 RSVD9
M_CLK_DDR#3 AV20 AL34 ME_JTAG_TCK R804 1 @ 2 100_0402_5%~D T123PAD~D
N28,M28,G36,E36 <17> M_CLK_DDR#3 SB_CK#_1 RSVD10
AK34 ME_JTAG_TDI R805 1 @ 2 100_0402_5%~D
RSVD11 T124PAD~D
DDR_CKE0_DIMMA BC28 AN35 ME_JTAG_TDO R806 1 @ 2 100_0402_5%~D T125PAD~D
H_A#[3..35] <7> <16> DDR_CKE0_DIMMA SA_CKE_0 RSVD12
U2A DDR_CKE1_DIMMA AY28 AM35 ME_JTAG_TMS R807 1 @ 2 100_0402_5%~D T126PAD~D
<8> H_D#[0..63] <16> DDR_CKE1_DIMMA SA_CKE_1 RSVD13
A14 H_A#3 DDR_CKE2_DIMMB AY36 T24 TP_MCH_RSVD14 @ R1088 1 2 51K_0402_1%~D +1.05V_VCCP
H_A#_3 <17> DDR_CKE2_DIMMB SB_CKE_0 RSVD14
D H_D#0 F2 C15 H_A#4 DDR_CKE3_DIMMB BB36 D
H_D#_0 H_A#_4 <17> DDR_CKE3_DIMMB SB_CKE_1
RSVD
H_D#1 G8 F16 H_A#5 B31 TP_MCH_RSVD15 T6 PAD~D
H_D#2 H_D#_1 H_A#_5 H_A#6 DDR_CS0_DIMMA# RSVD15 TP_MCH_RSVD16
F8 H_D#_2 H_A#_6 H13 <16> DDR_CS0_DIMMA# BA17 SA_CS#_0 RSVD16 B2 T7 PAD~D
H_D#3 E6 C18 H_A#7 DDR_CS1_DIMMA# AY16 M1 TP_MCH_RSVD17 T8 PAD~D
H_D#_3 H_A#_7 <16> DDR_CS1_DIMMA# SA_CS#_1 RSVD17
H_D#4 G2 M16 H_A#8 DDR_CS2_DIMMB# AV16
H_D#_4 H_A#_8 <17> DDR_CS2_DIMMB# SB_CS#_0
H_D#5 H6 J13 H_A#9 DDR_CS3_DIMMB# AR13
H_D#_5 H_A#_9 <17> DDR_CS3_DIMMB# SB_CS#_1
H_D#6 H2 P16 H_A#10 AY21 TP_MCH_RSVD20 T9 PAD~D
H_D#7 H_D#_6 H_A#_10 H_A#11 M_ODT0 RSVD20
F6 H_D#_7 H_A#_11 R16 <16> M_ODT0 BD17 SA_ODT_0
H_D#8 D4 N17 H_A#12 M_ODT1 AY17
H_D#_8 H_A#_12 +1.8V_MEM <16> M_ODT1 SA_ODT_1
H_D#9 H3 M13 H_A#13 M_ODT2 BF15
H_D#_9 H_A#_13 <17> M_ODT2 SB_ODT_0
H_D#10 M9 E17 H_A#14 M_ODT3 AY13 BG23 TP_MCH_RSVD22 T10 PAD~D
H_D#_10 H_A#_14 <17> M_ODT3 SB_ODT_1 RSVD22
H_D#11 M11 P17 H_A#15 2 1 SMRCOMP BF23 TP_MCH_RSVD23 T11 PAD~D
H_D#12 H_D#_11 H_A#_15 H_A#16 R79 80.6_0402_1%~D SMRCOMP RSVD23 TP_MCH_RSVD24
J1 H_D#_12 H_A#_16 F17 BG22 SM_RCOMP RSVD24 BH18 T12 PAD~D
H_D#13 J2 G20 H_A#17 2 1 SMRCOMP# SMRCOMP# BH21 BF18 TP_MCH_RSVD25 T164PAD~D
H_D#14 H_D#_13 H_A#_17 H_A#18 R80 80.6_0402_1%~D SM_RCOMP# RSVD25
N12 H_D#_14 H_A#_18 B19
H_D#15 J6 J16 H_A#19 SMRCOMP_VOH BF28
+1.05V_VCCP H_D#16 H_D#_15 H_A#_19 H_A#20 SMRCOMP_VOL SM_RCOMP_VOH
P2 H_D#_16 H_A#_20 E20 BH28 SM_RCOMP_VOL
H_D#17 L2 H16 H_A#21
H_D#_17 H_A#_21
1K_0402_1%~D
H_D#18 R2 J20 H_A#22 +V_DDR_MCH_REF +V_DDR_MCH_REF AV42

H_D#_18 H_A#_22 SM_VREF
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
H_D#19 N9 L17 H_A#23 SM_PWROK AR36
H_D#_19 H_A#_23 SM_PWROK
1
H_D#20 L6 A17 H_A#24 R81 1 2 499_0402_1%~D BF17

H_D#_20 H_A#_24 SM_REXT
R90
H_D#21 M5 B17 H_A#25 1 1 PAD~D T13 TP_SM_DRAMRST# BC36

H_D#22 H_D#_21 H_A#_25 H_A#26 SM_DRAMRST#
J3 H_D#_22 H_A#_26 L16
C68
C69
H_D#23 N2 C21 H_A#27 MCH_DREFCLK B38
H_D#_23 H_A#_27 <6> MCH_DREFCLK DPLL_REF_CLK
H_D#24 R1 J17 H_A#28 MCH_DREFCLK# A38
<6> MCH_DREFCLK#
2
H_D#25 H_D#_24 H_A#_28 H_A#29 2 2 DREF_SSCLK DPLL_REF_CLK#

N5 H_D#_25 H_A#_29 H20 <6> DREF_SSCLK E41 DPLL_REF_SSCLK
+H_VREF H_D#26 N6 B18 H_A#30 DREF_SSCLK# F41
H_D#_26 H_A#_30 <6> DREF_SSCLK# DPLL_REF_SSCLK#
H_D#27 P13 K17 H_A#31
H_D#_27 H_A#_31
0.1U_0402_16V7K~D
H_D#28 H_A#32 CLK_MCH_3GPLL
CLK
N8 H_D#_28 H_A#_32 B20 <6> CLK_MCH_3GPLL F43 PEG_CLK
1
2K_0402_1%~D
1 H_D#29 L7 F21 H_A#33 <6> CLK_MCH_3GPLL# CLK_MCH_3GPLL# E43

H_D#_29 H_A#_33 PEG_CLK#
@C73
@
R94
H_D#30 N10 K21 H_A#34

H_D#_30 H_A#_34
C73
H_D#31 M3 L20 H_A#35

H_D#32 H_D#_31 H_A#_35
Y3 H_D#_32
2 H_D#33 H_ADS# DMI_MRX_ITX_N0
AD14 H12 H_ADS# <7> <24> DMI_MRX_ITX_N0 AE41
2
H_D#34 H_D#_33 H_ADS# H_ADSTB#0 DMI_MRX_ITX_N1 DMI_RXN_0

C
Y6 H_D#_34 H_ADSTB#_0 B16 H_ADSTB#0 <7> <24> DMI_MRX_ITX_N1 AE37 DMI_RXN_1 C
H_D#35 Y10 G17 H_ADSTB#1 DMI_MRX_ITX_N2 AE47
H_D#_35 H_ADSTB#_1 H_ADSTB#1 <7> <24> DMI_MRX_ITX_N2 DMI_RXN_2
H_D#36 Y12 A9 H_BNR# H_BNR# <7> DMI_MRX_ITX_N3 AH39
H_D#_36 H_BNR# <24> DMI_MRX_ITX_N3 DMI_RXN_3
H_D#37 Y14 F11 H_BPRI# H_BPRI# <7>
H_D#38 H_D#_37 H_BPRI# H_BR0# DMI_MRX_ITX_P0
Y7 G12 AE40
HOST
H_D#_38 H_BREQ# H_BR0# <7> <24> DMI_MRX_ITX_P0 DMI_RXP_0

H_D#39 W2 E9 H_DEFER# H_DEFER# <7> DMI_MRX_ITX_P1 AE38 T25
H_D#_39 H_DEFER# <24> DMI_MRX_ITX_P1 DMI_RXP_1 CFG_0 CPU_MCH_BSEL0 <6,8>
H_D#40 AA8 B10 H_DBSY# H_DBSY# <7> DMI_MRX_ITX_P2 AE48 R25
+1.05V_VCCP H_D#_40 H_DBSY# <24> DMI_MRX_ITX_P2 DMI_RXP_2 CFG_1 CPU_MCH_BSEL1 <6,8>
H_D#41 Y9 AH7 CLK_MCH_BCLK DMI_MRX_ITX_P3 AH40 P25
H_D#_41 HPLL_CLK CLK_MCH_BCLK <6> <24> DMI_MRX_ITX_P3 DMI_RXP_3 CFG_2 CPU_MCH_BSEL2 <6,8>
H_D#42 AA13 AH6 CLK_MCH_BCLK# CLK_MCH_BCLK# <6> P20 T14 PAD~D
H_D#43 H_D#_42 HPLL_CLK# H_DPWR# DMI_MTX_IRX_N0 CFG_3
AA9 H_D#_43 H_DPWR# J11 H_DPWR# <8> <24> DMI_MTX_IRX_N0 AE35 DMI_TXN_0 CFG_4 P24 T15 PAD~D
H_D#44 AA11 F9 H_DRDY# DMI_MTX_IRX_N1 AE43 C25 CFG5 CFG5 <12>
H_D#_44 H_DRDY# H_DRDY# <7> <24> DMI_MTX_IRX_N1 DMI_TXN_1 CFG_5
1
H_D#45 AD11 H9 H_HIT# H_HIT# <7> DMI_MTX_IRX_N2 AE46 N24 CFG6 CFG6 <12>
H_D#_45 H_HIT# <24> DMI_MTX_IRX_N2 DMI_TXN_2 CFG_6
R91 H_D#46 AD10 E12 H_HITM# H_HITM# <7> DMI_MTX_IRX_N3 AH42 M24 CFG7 CFG7 <12>
H_D#_46 H_HITM# <24> DMI_MTX_IRX_N3 DMI_TXN_3 CFG_7
221_0402_1%~D H_D#47 AD13 H11 H_LOCK# H_LOCK# <7> E21 T16 PAD~D
H_D#_47 H_LOCK# CFG_8
DMI CFG
H_D#48 AE12 C9 H_TRDY# H_TRDY# <7> DMI_MTX_IRX_P0 AD35 C23 CFG9 CFG9 <12>
H_D#_48 H_TRDY# <24> DMI_MTX_IRX_P0 DMI_TXP_0 CFG_9
H_D#49 AE9 DMI_MTX_IRX_P1 AE44 C24 T17 PAD~D Notes refer
<24> DMI_MTX_IRX_P1
2
H_D#50 H_D#_49 DMI_MTX_IRX_P2 DMI_TXP_1 CFG_10

AA2 AF46 N21 T18 PAD~D
H_SWNG H_D#51 AD8
H_D#_50 <24> DMI_MTX_IRX_P2
DMI_MTX_IRX_P3 AH43
DMI_TXP_2 CFG_11
P21
page 12
H_D#_51 <24> DMI_MTX_IRX_P3 DMI_TXP_3 CFG_12 T19 PAD~D
H_D#52 AA3 T21 T20 PAD~D
H_D#_52 CFG_13
0.1U_0402_16V7K~D
H_D#53 AD3 J8 H_DINV#0 R20 T21 PAD~D

H_D#_53 H_DINV#_0 H_DINV#0 <8> CFG_14
1
100_0402_1%~D
1 H_D#54 AD7 L3 H_DINV#1 M20 T22 PAD~D

R95
H_D#55 AE14 Y13 H_DINV#2 L21 CFG16 CFG16 <12>

C74
H_D#56 AF3 Y1 H_DINV#3 H21 T23 PAD~D

H_D#57
GRAPHICS VID
AC1 H_D#_57 CFG_18 P29 T24 PAD~D
2 H_D#58 H_DSTBN#0 CFG19
AE3 L10 H_DSTBN#0 <8> R28 CFG19 <12>
2
H_D#59 H_D#_58 H_DSTBN#_0 H_DSTBN#1 GFX_VID0 CFG_19 CFG20

AC3 H_D#_59 H_DSTBN#_1 M7 H_DSTBN#1 <8> <49> GFX_VID0 B33 GFX_VID_0 CFG_20 T28 CFG20 <12>
H_D#60 AE11 AA5 H_DSTBN#2 H_DSTBN#2 <8> GFX_VID1 B32
H_D#_60 H_DSTBN#_2 <49> GFX_VID1 GFX_VID_1
H_D#61 AE8 AE6 H_DSTBN#3 H_DSTBN#3 <8> GFX_VID2 G33
H_D#_61 H_DSTBN#_3 <49> GFX_VID2 GFX_VID_2
H_D#62 AG2 GFX_VID3 F33
H_D#_62 <49> GFX_VID3 GFX_VID_3
H_D#63 AD6 L9 H_DSTBP#0 H_DSTBP#0 <8> GFX_VID4 E33 R29 PM_SYNC# PM_SYNC# <24>
H_D#_63 H_DSTBP#_0 <49> GFX_VID4 GFX_VID_4 PM_SYNC#
M8 H_DSTBP#1 H_DSTBP#1 <8> B7 H_DPRSTP# H_DPRSTP# <8,23,47>
H_DSTBP#_1 H_DSTBP#2 PM_DPRSTP#
H_DSTBP#_2 AA6 H_DSTBP#2 <8> PM_EXT_TS#_0 N33
H_SWNG C5 AE5 H_DSTBP#3 H_DSTBP#3 <8> P32 PM_EXTTS# PM_EXTTS# <18>
H_SWING H_DSTBP#_3 PM_EXT_TS#_1
PM
1 2 +H_RCOMP E3 GFX_VR_ON C34 AT40 ICH_PWRGD
H_RCOMP +1.05V_M <49> GFX_VR_ON GFX_VR_EN PWROK ICH_PWRGD <24,41>
R82 24.9_0402_1%~D B15 H_REQ#0 AT11 PLTRST1#_R
H_REQ#_0 H_REQ#0 <7> RSTIN#
B K13 H_REQ#1 T20 THERMTRIP_MCH# THERMTRIP_MCH# <18> B
H_REQ#_1 H_REQ#1 <7> THERMTRIP#
1K_0402_1%~D
F13 H_REQ#2 R32 DPRSLPVR DPRSLPVR <24,47> +3.3V_RUN

H_REQ#_2 H_REQ#2 <7> DPRSLPVR
1
+1.8V_MEM B13 H_REQ#3

H_REQ#_3 H_REQ#3 <7>
<7> H_RESET# H_RESET# C12 B14 H_REQ#4 CL_CLK0 AH37
H_CPURST# H_REQ#_4 H_REQ#4 <7> <24> CL_CLK0 CL_CLK
R83
H_CPUSLP# E11 CL_DATA0 AH36

<8> H_CPUSLP# H_CPUSLP# <24> CL_DATA0 CL_DATA
1
B6 H_RS#0 ICH_CL_PWROK AN36 BG48

H_RS#_0 H_RS#0 <7> <24,38> ICH_CL_PWROK CL_PWROK NC_1
R88 F12 H_RS#1 CL_RST0# AJ35 BF48 PM_EXTTS# 2 1
H_RS#1 <7> <24> CL_RST0#
2
H_RS#_1 CL_RST# NC_2
ME
1K_0402_1%~D C8 H_RS#2 +CL_VREF AH34 BD48 R85 10K_0402_5%~D
H_RS#_2 H_RS#2 <7> CL_VREF NC_3
0.1U_0402_16V4Z~D
+H_VREF A11 BC48

H_AVREF +1.5V_RUN NC_4
B11 BH47
2
H_DVREF NC_5
2
499_0402_1%~D
SMRCOMP_VOH 1 BG47 SM_PWROK 2 1

NC_6
0.01U_0402_16V7K~D
2.2U_0603_6.3V6K~D
R87
C70
CANTIGA ES_FCBGA1329~D 1 <21> DDPC_CTRLCLK DDPC_CTRLCLK N28 BE47 R86 0_0402_5%~D

+3.3V_RUN_D C1047 DDPC_CTRLDATA DDPC_CTRLCLK NC_7
1 1 <12,21> DDPC_CTRLDATA M28 DDPC_CTRLDATA NC_8 BH46
<21> SDVO_CTRLCLK SDVO_CTRLCLK G36 BF46
SDVO_CTRLCLK NC_9
1
2
3.01K_0402_1%~D
C71
C72
NC
C1046 0.1U_0402_16V4Z~D SDVO_CTRLDATA E36 BG45 Use for DDR3 signls,
<21> SDVO_CTRLDATA
1
0.1U_0402_16V4Z~D 2 CLK_3GPLLREQ# SDVO_CTRLDATA NC_10

<6> CLK_3GPLLREQ# K36 BH44
2 2 CLKREQ# NC_11 if support DDR2 need
R93
2 1 U67 R58 <24> MCH_ICH_SYNC# MCH_ICH_SYNC# H36 BH43

10K_0402_5%~D ICH_SYNC# NC_12 connect to GND
16 1 BH6
MISC
VCCB VCCA NC_13 +3.3V_RUN
15 2 2 1 BH5
2
ICH_AZ_MCH_BITCLK CLK_OUT CLK_IN GMCH_HDA_BITCLK MCH_TSATN# NC_14

<23> ICH_AZ_MCH_BITCLK 14 CMD_B CMD_A 3 B12 TSATN# NC_15 BG4
ICH_AZ_MCH_RST# 13 4 GMCH_HDA_RST# HDA support 1.5V BH3
<23> ICH_AZ_MCH_RST# B0 A0 NC_16
1
SMRCOMP_VOL ICH_AZ_MCH_SDOUT 12 5 GMCH_HDA_SDOUT BF3
<23> ICH_AZ_MCH_SDOUT B1 A1 NC_17
0.01U_0402_16V7K~D
2.2U_0603_6.3V6K~D
ICH_AZ_MCH_SYNC 11 6 GMCH_HDA_SYNC BH2 R156

<23> ICH_AZ_MCH_SYNC B2 A2 NC_18
1
1 1 ICH_AZ_MCH_SDIN2 10 7 GMCH_HDA_SDIN2 0_0402_5%~D 1 R42 2 GMCH_HDA_BITCLK_R B28 BG2 30K_0402_5%~D

<23> ICH_AZ_MCH_SDIN2 B3 A3 HDA_BCLK NC_19
1K_0402_1%~D
9 8 U67_OD_DELAY 0_0402_5%~D 1 R44 2 GMCH_HDA_RST#R B30 BE2

GND OE HDA_RST# NC_20
R97
C75
C76
33_0402_5%~D 1 R685 2 GMCH_HDA_SDIN2_R B29 BG1
2
FXL2SD106BQX_DQFN16_2P5X3P5~D 0_0402_5%~D R686 GMCH_HDA_SDOUT_R HDA_SDI NC_21 GFX_VR_ON
1 2 C29 HDA_SDO NC_22 BF1
2 2 0_0402_5%~D R687 GMCH_HDA_SYNC_R
HDA
1 2 A28 BD1
2
HDA_SYNC NC_23
1
+3.3V_ALW BC1
+3.3V_RUN Q153 NC_24 R157
NC_25 F1
+3.3V_ALW2 +15V_ALW SI3456BDV-T1-E3_TSOP6~D A47 100K_0402_5%~D
NC_26
1K_0402_5%~D
+3.3V_RUN_D +3.3V_RUN
D
100K_0402_5%~D
100K_0402_5%~D
6 +3.3V_ALW +3.3V_RUN_D CANTIGA ES_FCBGA1329~D

S
2
1
5 4 1 2 Q155
1
1
1K_0402_5%~D
R1119
R1120
10K_0402_5%~D
2
1
A A
R99
1 @ R1118 NTR4003NT1G_SOT23-3
+1.05V_VCCP
R1122
0_0603_5%~D PLTRST1#_R 2 1
G
PLTRST1# <22,32>
R98
R100 100_0402_5%~D
D
1 3
2
MCH_TSATN_EC <37> @ THERMTRIP_MCH# 1 2 +1.05V_VCCP

2
1 2
1
SSM6N7002FU_US6~D
Q153_GATE R102 56_0402_5%~D

2
100K_0402_5%~D
100P_0402_50V8K~D
R101 C U67_OD_DELAY
G
2
3
54.9_0402_1%~D 2 Q154B
1
1
@ R1121
8.2K_0402_5%~D
B SSM6N7002FU_US6~D 1 Q153_GATE
1
Q154A
R1123
C1049
C E
2
MCH_TSATN# 2 1 1 2 2 5 2
B <24,41> ICH_PWRGD PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
R103 R104 Q3 Title
0_0402_5%~D 330_0402_5%~D E MMST3904-7-F_SOT323-3~D 2 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Cantiga(1 of 6)
3
Q4 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

MMST3904-7-F_SOT323-3~D NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
LA-4041P
5 4 3 2 1
5 4 3 2 1
D D
DDR_A_D[0..63] <16> DDR_B_D[0..63] <17>

U2D U2E
DDR_A_BS0 BD21 AJ38 DDR_A_D0 DDR_B_BS0 BC16 AK47 DDR_B_D0
<16> DDR_A_BS0 SA_BS_0 SA_DQ_0 <17> DDR_B_BS0 SB_BS_0 SB_DQ_0
DDR_A_BS1 BG18 AJ41 DDR_A_D1 DDR_B_BS1 BB17 AH46 DDR_B_D1
DDR_A_BS2 AT25 AN38 DDR_A_D2 DDR_B_BS2 BB33 AP47 DDR_B_D2
AM38 DDR_A_D3 AP46 DDR_B_D3
DDR_A_RAS# SA_DQ_3 DDR_A_D4 SB_DQ_3 DDR_B_D4
<16> DDR_A_RAS# BB20 SA_RAS# SA_DQ_4 AJ36 SB_DQ_4 AJ46
DDR_A_CAS# BD20 AJ40 DDR_A_D5 DDR_B_RAS# AU17 AJ48 DDR_B_D5
<16> DDR_A_CAS# SA_CAS# SA_DQ_5 <17> DDR_B_RAS# SB_RAS# SB_DQ_5
DDR_A_WE# AY20 AM44 DDR_A_D6 DDR_B_CAS# BG16 AM48 DDR_B_D6
<16> DDR_A_WE# SA_WE# SA_DQ_6 <17> DDR_B_CAS# SB_CAS# SB_DQ_6
AM42 DDR_A_D7 DDR_B_WE# BF14 AP48 DDR_B_D7
SA_DQ_7 <17> DDR_B_WE# SB_WE# SB_DQ_7
AN43 DDR_A_D8 AU47 DDR_B_D8
SA_DQ_8 DDR_A_D9 SB_DQ_8 DDR_B_D9
<16> DDR_A_DM[0..7] SA_DQ_9 AN44 SB_DQ_9 AU46
AU40 DDR_A_D10 BA48 DDR_B_D10
SA_DQ_10 <17> DDR_B_DM[0..7] SB_DQ_10
DDR_A_DM0 AM37 AT38 DDR_A_D11 AY48 DDR_B_D11
DDR_A_DM1 SA_DM_0 SA_DQ_11 DDR_A_D12 DDR_B_DM0 SB_DQ_11 DDR_B_D12
AT41 SA_DM_1 SA_DQ_12 AN41 AM47 SB_DM_0 SB_DQ_12 AT47
DDR_A_DM2 AY41 AN39 DDR_A_D13 DDR_B_DM1 AY47 AR47 DDR_B_D13
DDR_A_DM3 SA_DM_2 SA_DQ_13 DDR_A_D14 DDR_B_DM2 SB_DM_1 SB_DQ_13 DDR_B_D14
AU39 SA_DM_3 SA_DQ_14 AU44 BD40 SB_DM_2 SB_DQ_14 BA47
DDR_A_DM4 BB12 AU42 DDR_A_D15 DDR_B_DM3 BF35 BC47 DDR_B_D15
DDR_A_DM5 SA_DM_4 SA_DQ_15 DDR_A_D16 DDR_B_DM4 SB_DM_3 SB_DQ_15 DDR_B_D16
AY6 SA_DM_5 SA_DQ_16 AV39 BG11 SB_DM_4 SB_DQ_16 BC46
DDR_A_DM6 AT7 AY44 DDR_A_D17 DDR_B_DM5 BA3 BC44 DDR_B_D17
SA_DM_6 SA_DQ_17 SB_DM_5 SB_DQ_17
A
DDR_A_DM7 AJ5 BA40 DDR_A_D18 DDR_B_DM6 AP1 BG43 DDR_B_D18
B
SA_DM_7 SA_DQ_18 DDR_A_D19 DDR_B_DM7 SB_DM_6 SB_DQ_18 DDR_B_D19
<16> DDR_A_DQS[0..7] SA_DQ_19 BD43 AK2 SB_DM_7 SB_DQ_19 BF43
DDR_A_DQS0 AJ44 AV41 DDR_A_D20 BE45 DDR_B_D20
C SA_DQS_0 SA_DQ_20 <17> DDR_B_DQS[0..7] SB_DQ_20 C
DDR_A_DQS1 AT44 AY43 DDR_A_D21 DDR_B_DQS0 AL47 BC41 DDR_B_D21
DDR_A_DQS2 SA_DQS_1 SA_DQ_21 DDR_A_D22 DDR_B_DQS1 SB_DQS_0 SB_DQ_21 DDR_B_D22
BA43 SA_DQS_2 SA_DQ_22 BB41 AV48 SB_DQS_1 SB_DQ_22 BF40
MEMORY
DDR_A_DQS3 BC37 BC40 DDR_A_D23 DDR_B_DQS2 BG41 DDR_B_D23
MEMORY
SA_DQS_3 SA_DQ_23 SB_DQS_2 SB_DQ_23 BF41
DDR_A_DQS4 AW12 AY37 DDR_A_D24 DDR_B_DQS3 BG37 BG38 DDR_B_D24
BC8 SA_DQS_5 SA_DQ_25 BD38 BH9 SB_DQS_4 SB_DQ_25 BF38
DDR_A_DQS6 AU8 AV37 DDR_A_D26 DDR_B_DQS5 BB2 BH35 DDR_B_D26
<16> DDR_A_DQS#[0..7] AM7 SA_DQS_7 SA_DQ_27 AT36 AU1 SB_DQS_6 SB_DQ_27 BG35
DDR_A_DQS#0 AJ43 AY38 DDR_A_D28 DDR_B_DQS7 AN6 BH40 DDR_B_D28
SA_DQS#_0 SA_DQ_28 <17> DDR_B_DQS#[0..7] SB_DQS_7 SB_DQ_28
DDR_A_DQS#1 AT43 BB38 DDR_A_D29 DDR_B_DQS#0 AL46 BG39 DDR_B_D29
DDR_A_DQS#2 SA_DQS#_1 SA_DQ_29 DDR_A_D30 DDR_B_DQS#1 SB_DQS#_0 SB_DQ_29 DDR_B_D30
BA44 SA_DQS#_2 SA_DQ_30 AV36 AV47 SB_DQS#_1 SB_DQ_30 BG34
DDR_A_DQS#3 BD37 AW36 DDR_A_D31 DDR_B_DQS#2 BH41 BH34 DDR_B_D31
AY12 SA_DQS#_4 SA_DQ_32 BD13 BH37 SB_DQS#_3 SB_DQ_32 BH14
DDR_A_DQS#5 BD8 AU11 DDR_A_D33 DDR_B_DQS#4 BG9 BG12 DDR_B_D33
AU9 SA_DQS#_6 SA_DQ_34 BC11 BC2 SB_DQS#_5 SB_DQ_34 BH11
DDR_A_DQS#7 AM8 BA12 DDR_A_D35 DDR_B_DQS#6 AT2 BG8 DDR_B_D35
SYSTEM
<16> DDR_A_MA[0..14] SA_DQS#_7 SA_DQ_35 SB_DQS#_6 SB_DQ_35

DDR_A_D36 DDR_B_DQS#7 DDR_B_D36
SYSTEM
SA_DQ_36 AU13 <17> DDR_B_MA[0..14] AN5 SB_DQS#_7 SB_DQ_36 BH12
DDR_A_MA0 BA21 AV13 DDR_A_D37 BF11 DDR_B_D37
DDR_A_MA1 SA_MA_0 SA_DQ_37 DDR_A_D38 DDR_B_MA0 SB_DQ_37 DDR_B_D38
BC24 SA_MA_1 SA_DQ_38 BD12 AV17 SB_MA_0 SB_DQ_38 BF8
DDR_A_MA2 BG24 BC12 DDR_A_D39 DDR_B_MA1 BA25 BG7 DDR_B_D39
DDR_A_MA3 SA_MA_2 SA_DQ_39 DDR_A_D40 DDR_B_MA2 SB_MA_1 SB_DQ_39 DDR_B_D40
BH24 SA_MA_3 SA_DQ_40 BB9 BC25 SB_MA_2 SB_DQ_40 BC5
DDR_A_MA4 BG25 BA9 DDR_A_D41 DDR_B_MA3 AU25 BC6 DDR_B_D41
BA24 SA_MA_5 SA_DQ_42 AU10 AW25 SB_MA_4 SB_DQ_42 AY3
DDR_A_MA6 BD24 AV9 DDR_A_D43 DDR_B_MA5 BB28 AY1 DDR_B_D43
BG27 SA_MA_7 SA_DQ_44 BA11 AU28 SB_MA_6 SB_DQ_44 BF6
DDR_A_MA8 BF25 BD9 DDR_A_D45 DDR_B_MA7 AW28 BF5 DDR_B_D45
AW24 SA_MA_9 SA_DQ_46 AY8 AT33 SB_MA_8 SB_DQ_46 BA1
DDR_A_MA10 BC21 BA6 DDR_A_D47 DDR_B_MA9 BD33 BD3 DDR_B_D47
DDR
BG26 SA_MA_11 SA_DQ_48 AV5 BB16 SB_MA_10 SB_DQ_48 AV2

DDR_A_MA12 DDR_A_D49 DDR_B_MA11 DDR_B_D49
DDR
BH26 SA_MA_12 SA_DQ_49 AV7 AW33 SB_MA_11 SB_DQ_49 AU3
DDR_A_MA13 BH17 AT9 DDR_A_D50 DDR_B_MA12 AY33 AR3 DDR_B_D50
AY25 SA_MA_14 SA_DQ_51 AN8 BH15 SB_MA_13 SB_DQ_51 AN2
AU5 DDR_A_D52 DDR_B_MA14 AU33 AY2 DDR_B_D52
B SA_DQ_52 DDR_A_D53 SB_MA_14 SB_DQ_52 DDR_B_D53 B
SA_DQ_53 AU6 SB_DQ_53 AV1
AT5 DDR_A_D54 AP3 DDR_B_D54
SA_DQ_55 AN10 SB_DQ_55 AR1
AM11 DDR_A_D56 AL1 DDR_B_D56
SA_DQ_57 AM5 SB_DQ_57 AL2
AJ9 DDR_A_D58 AJ1 DDR_B_D58
SA_DQ_59 AJ8 SB_DQ_59 AH1
AN12 DDR_A_D60 AM2 DDR_B_D60
SA_DQ_61 AM13 SB_DQ_61 AM3
AJ11 DDR_A_D62 AH3 DDR_B_D62
SA_DQ_63 AJ12 SB_DQ_63 AJ3
CANTIGA ES_FCBGA1329~D CANTIGA ES_FCBGA1329~D
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Cantiga(2 of 6)
LA-4041P
5 4 3 2 1
5 4 3 2 1
+VCC_PEG
Strap Pin Table
2
U2C Low = DMI x 2
R105 CFG5 DMI X2 Select
49.9_0402_1%~D High = DMI x 4 (Default)
1
BIA_PWM L32 iTPM Host Low = iTPM enable
<19> BIA_PWM L_BKLT_CTRL
PANEL_BKEN_MCH G32 T37 PEGCOMP CFG6
<37> PANEL_BKEN_MCH
M32
L_BKLT_EN PEG_COMPI
T36
Interface High = iTPM disable(Defult)
D L_CTRL_CLK PEG_COMPO D
M33 L_CTRL_DATA Management Low = TLS cipher suite with no confidentiality
LDDC_CLK_MCH K33 H44 CFG7
<19> LDDC_CLK_MCH
LDDC_DATA_MCH J33
L_DDC_CLK PEG_RX#_0
J46
Engine Crypto High = TLS cipher suite with
<19> LDDC_DATA_MCH L_DDC_DATA PEG_RX#_1
PEG_RX#_2 L44 DPB_AUX#
DPB_AUX# <21>
Strap confidentiality(Default)
<19> ENVDD PEG_RX#_3 L40
ENVDD M29 N41 PCI Express Low = Reverse Lane
L_IBG L_VDD_EN PEG_RX#_4
1 2 C44 LVDS_IBG PEG_RX#_5 P48 CFG9 Graphic Lane
R688 2.4K_0402_1%~D B43 N44 DPC_DOCK_AUX# High = Normal Operation(Default)
LVDS_VBG PEG_RX#_6 DPC_DOCK_AUX# <21>
The value is recommended per Intel E37 LVDS_VREFH PEG_RX#_7 T43
E38 LVDS_VREFL PEG_RX#_8 U43
LVDS
LCD_ACLK-_MCH C41 Y43 FSB Dynamic Low=Dynamic ODT Disable
<19> LCD_ACLK-_MCH LVDSA_CLK# PEG_RX#_9
LCD_ACLK+_MCH C40 Y48 CFG16
<19> LCD_ACLK+_MCH
LCD_BCLK-_MCH B37
LVDSA_CLK PEG_RX#_10
Y36
ODT High=Dynamic ODT Enable(default)
<19> LCD_BCLK-_MCH LVDSB_CLK# PEG_RX#_11
LCD_BCLK+_MCH A37 AA43
<19> LCD_BCLK+_MCH LVDSB_CLK PEG_RX#_12
PEG_RX#_13 AD37 CFG19 DMI Lane Low=Normal (default)
LCD_A0-_MCH H47 AC47
<19> LCD_A0-_MCH
LCD_A1-_MCH LVDSA_DATA#_0 PEG_RX#_14 Reversal
<19> LCD_A1-_MCH E46 LVDSA_DATA#_1 PEG_RX#_15 AD39 High=Lane Reversed
LCD_A2-_MCH G40
<19> LCD_A2-_MCH LVDSA_DATA#_2
A40 LVDSA_DATA#_3 PEG_RX_0 H43
GRAPHICS
PEG_RX_1 J44 SDVO/PCIE Low=Only SDVO or PCIEx1 is
LCD_A0+_MCH H48 L43 DPB_AUX CFG20
<19> LCD_A0+_MCH
LCD_A1+_MCH D45
LVDSA_DATA_0 PEG_RX_2
L41 DPB_HPD# DPB_AUX <21> Concurrent operational (default)
<19> LCD_A1+_MCH LVDSA_DATA_1 PEG_RX_3 DPB_HPD# <21>
<19> LCD_A2+_MCH
LCD_A2+_MCH F40 LVDSA_DATA_2 PEG_RX_4 N40 Operation High=SDVO and PCIEx1 are operating
B40 P47
LVDSA_DATA_3 PEG_RX_5
N43 DPC_DOCK_AUX simultaneously via PEG port
LCD_B0-_MCH PEG_RX_6 DPC_DOCK_HPD# DPC_DOCK_AUX <21>
<19> LCD_B0-_MCH A41 LVDSB_DATA#_0 PEG_RX_7 T42 DPC_DOCK_HPD# <35> Low=No SDVO Device Present
LCD_B1-_MCH H38 U42 SDVO_CRTL_DATA
<19> LCD_B1-_MCH
LCD_B2-_MCH G37
LVDSB_DATA#_1 PEG_RX_8
Y42
(default)
<19> LCD_B2-_MCH LVDSB_DATA#_2 PEG_RX_9
J37 LVDSB_DATA#_3 PEG_RX_10 W47 High=SDVO Device Present
PEG_RX_11 Y37
LCD_B0+_MCH B42 AA42 Low=DisplayPort disabled (default)
C <19> LCD_B0+_MCH LVDSB_DATA_0 PEG_RX_12 C
LCD_B1+_MCH G38 AD36 DDPC_CTRLDATA
<19> LCD_B1+_MCH LVDSB_DATA_1 PEG_RX_13
LCD_B2+_MCH F37 AC48 High=DisplayPort device present
<19> LCD_B2+_MCH LVDSB_DATA_2 PEG_RX_14
PCI-EXPRESS
K37 LVDSB_DATA_3 PEG_RX_15 AD40
J41 DPB_LANE_N0 C716 2 1 0.1U_0402_10V7K~D

PEG_TX#_0 DPB_LANE_N1 C717 0.1U_0402_10V7K~D DPB_LANE_N0_C <21>
PEG_TX#_1 M46 2 1 DPB_LANE_N1_C <21>
F25 M47 DPB_LANE_N2 C718 2 1 0.1U_0402_10V7K~D @R106
@ R106 1 2 2.21K_0402_1%~D
TVA_DAC PEG_TX#_2 DPB_LANE_N2_C <21> <10> CFG5
H25 M40 DPB_LANE_N3 C719 2 1 0.1U_0402_10V7K~D
TVB_DAC PEG_TX#_3 DPC_LANE_N0 C720 0.1U_0402_10V7K~D DPB_LANE_N3_C <21> @R107
@ R107 1
K25 TVC_DAC PEG_TX#_4 M42 2 1 DPC_LANE_N0_C <35> <10> CFG6 2 2.21K_0402_1%~D
TV
R48 DPC_LANE_N1 C721 2 1 0.1U_0402_10V7K~D

PEG_TX#_5 DPC_LANE_N1_C <35>
75_0402_5%~D
75_0402_5%~D
75_0402_5%~D
H24 N38 DPC_LANE_N2 C722 2 1 0.1U_0402_10V7K~D @R108

@ R108 1 2 2.21K_0402_1%~D
TV_RTN PEG_TX#_6 DPC_LANE_N2_C <35> <10> CFG7
1
R1116
T40 DPC_LANE_N3 C723 2 1 0.1U_0402_10V7K~D

PEG_TX#_7 DPC_LANE_N3_C <35>
R1114
R1115
U37 @R109
@ R109 1 2 2.21K_0402_1%~D
PEG_TX#_8 <10> CFG9
PEG_TX#_9 U40
C31 Y40 @R110
@ R110 1 2 2.21K_0402_1%~D
TV_DCONSEL_0 PEG_TX#_10 <10> CFG16
E32 AA46
2
TV_DCONSEL_1 PEG_TX#_11
PEG_TX#_12 AA37
PEG_TX#_13 AA40 CFG[5:16] have internal pullup
PEG_TX#_14 AD43
PEG_TX#_15 AC46
CRT_BLU E28 J42 DPB_LANE_P0 C724 2 1 0.1U_0402_10V7K~D

<20> CRT_BLU CRT_BLUE PEG_TX_0 DPB_LANE_P0_C <21> +3.3V_RUN
L46 DPB_LANE_P1 C725 2 1 0.1U_0402_10V7K~D
CRT_GRN PEG_TX_1 DPB_LANE_P2 C726 0.1U_0402_10V7K~D DPB_LANE_P1_C <21>
<20> CRT_GRN G28 CRT_GREEN PEG_TX_2 M48 2 1 DPB_LANE_P2_C <21>
M39 DPB_LANE_P3 C727 2 1 0.1U_0402_10V7K~D @R111
@ R111 1 2 4.02K_0402_1%~D
PEG_TX_3 DPB_LANE_P3_C <21> <10> CFG19
CRT_RED J28 M43 DPC_LANE_P0 C728 2 1 0.1U_0402_10V7K~D
<20> CRT_RED CRT_RED PEG_TX_4 DPC_LANE_P0_C <35>
VGA
R47 DPC_LANE_P1 C729 2 1 0.1U_0402_10V7K~D @R112

@ R112 1 2 4.02K_0402_1%~D
PEG_TX_5 DPC_LANE_P1_C <35> <10> CFG20
G29 N37 DPC_LANE_P2 C730 2 1 0.1U_0402_10V7K~D
CRT_IRTN PEG_TX_6 DPC_LANE_P3 C731 0.1U_0402_10V7K~D DPC_LANE_P2_C <35> @R113
@ R113 1
PEG_TX_7 T39 2 1 DPC_LANE_P3_C <35> <10,21> DDPC_CTRLDATA 2 4.02K_0402_1%~D
G_CLK_DDC2 H32 U36
G_DAT_DDC2 CRT_DDC_CLK PEG_TX_8
J32 CRT_DDC_DATA PEG_TX_9 U39
CRT_HSYNC 1 2 CRT_HSYNC_RJ29 Y39 CFG[19:20] have internal pulldown
B <20> CRT_HSYNC CRT_HSYNC PEG_TX_10 B
R48030_0402_1%~D E29 Y46
CRT_IREF CRT_TVO_IREF PEG_TX_11
2 1 L29 CRT_VSYNC PEG_TX_12 AA36
R672 976_0402_1%~D AA39
CRT_VSYNC PEG_TX_13
<20> CRT_VSYNC 1 2CRT_VSYNC_R PEG_TX_14 AD42
R673 30_0402_1%~D AD46
PEG_TX_15
CANTIGA ES_FCBGA1329~D
+3.3V_RUN
CRT_BLU
NO CONNECT FOR DISCRETE
1 2
R679 150_0402_1%~D
1 2 CRT_GRN R676
1
R680 150_0402_1%~D 2.2K_0402_5%~D

1 2 CRT_RED R675
R681 150_0402_1%~D 2.2K_0402_5%~D 1 @ 2
1 2 ENVDD R8550_0402_5%~D
R682 100K_0402_5%~D
2
G_CLK_DDC2 1 6 CLK_DDC2
CLK_DDC2 <20>
2N7002DW-7-F_SOT363-6~D
Q21A
2
+3.3V_RUN
5
Q21B 2N7002DW-7-F_SOT363-6~D
G_DAT_DDC2 4 3 DAT_DDC2
A DAT_DDC2 <20> A
1 @ 2
R856 0_0402_5%~D
LA-4041P
5 4 3 2 1
5 4 3 2 1
+1.05V_VCCP
CRB 270uF U2H
U13 +3.3V_CRT_DAC +3.3V_RUN

VTT_1 +VCC_PEG
T13 VTT_2
220U_D2_4VY_R15M~D
0.47U_0402_10V4Z~D
1 U12 B27 +3.3V_CRT_DAC 2 1
VTT_3 VCCA_CRT_DAC_1
0.01U_0402_25V7K~D
0.1U_0402_16V4Z~D
1 T12 A26 BLM18PG181SN1_0603~D 1 2 +1.05V_M
VTT_4 VCCA_CRT_DAC_2 +3.3V_CRT_DAC
220U_D2_4VY_R15M~D
+ U11 R114
VTT_5 L43
C109
C110
4.7U_0603_6.3V6M~D
22U_0805_6.3V6M~D
T11 1 1 0_1210_5%~D
VTT_6
U10 A25 1
CRT
2 2 VTT_7 VCCA_DAC_BG
0.01U_0402_25V7K~D
0.1U_0402_16V4Z~D
C732
C733
T10 VTT_8 VSSA_DAC_BG B25 1 1 1 2 +1.05V_VCCP
U9 + @ R115
VTT_9 2 2
C111
C112
C113
T9 1 1 0_1210_5%~D
VTT_10 Follow ERB,CRB option
U8 VTT_11 2 2 2
C734
C735
D
T8 F47 to select +1.05V_M or D
VTT_12 VCCA_DPLLA +1.05V_M_DPLLA +1.05V_VCCP
U7
VTT
VTT_13 2 2
T7 VTT_14 VCCA_DPLLB L48 +1.05V_M_DPLLB
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
2.2U_0603_10V7K~D
U6 VTT_15
1 1 1 T6 AD1
PLL
VTT_16 VCCA_HPLL +1.05V_M_HPLL
U5 VTT_17
C114
C115
C116
T5 VTT_18 VCCA_MPLL AE1 +1.05V_M_MPLL

V3 +VCC_TX_LVDS
2 2 2 VTT_19
U3 VTT_20
V2 J48 +VCC_TX_LVDS
VTT_21 VCCA_LVDS
1000P_0402_50V7K~D
U2
A LVDS
VTT_22
T2 VTT_23 VSSA_LVDS J47 1
V1 VTT_24
C736
U1 VTT_25
+VCCA_PEG_BG 2
VCCA_PEG_BG AD48 1 2 +1.5V_RUN
R778 0_0402_5%~D
1 2 +3.3V_RUN
@R779
@ R779 0_0402_5%~D +1.5V_RUN_QDAC +1.5V_RUN
1
A PEG
+1.05V_M L3 +1.05V_M_PEGPLL
AA48 +1.05V_M_PEGPLL C117 BLM21PG221SN1D_0805~D 2 1
VCCA_PEG_PLL
0.01U_0402_25V7K~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D +1.05V_M 1 2 L44
2
0.1U_0402_16V4Z~D
BLM18PG181SN1_0603~D
100U_D2E_6.3VM_R15M~D
AR20 R116 C118 1 1
VCCA_SM_1 +1.05V_M_A_SM 1 10U_0805_4VAM~D
VCCA_SM_2 AP20 2 1
1U_0603_10V4Z~D
4.7U_0603_6.3V6M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
C737
C738
AN20 2 1
POWER VCCA_SM_3
C119
AR17 0_0805_5%~D 1 R117 1_0402_5%~D
VCCA_SM_4 2 2
VCCA_SM_5 AP17 1 1 1 1 2
@ C124
AN17 +
VCCA_SM_6
C121
C122
C123
C120
VCCA_SM_7 AT16
AR16
A SM
+1.05V_M VCCA_SM_8 2 2 2 2 2
VCCA_SM_9 AP16
C C
2 1 +VCC_AXF
+1.05V_M_SM_CK
10U_0805_4VAM~D
1U_0603_10V4Z~D
R118 +1.05V_M
0_1210_5%~D 1 1
@ C125
VCCA_SM_CK_1 AP28 1 2
C126
0.1U_0402_16V4Z~D
22U_0805_6.3V6M~D
2.2U_0603_6.3V6K~D
B22 AN28 R119 0_1210_5%~D
VCC_AXF_1 VCCA_SM_CK_2
B21 AP25
AXF
2 2 VCC_AXF_2 VCCA_SM_CK_3
A21 VCC_AXF_3 VCCA_SM_CK_4 AN25 1 1 1
@C129
@
VCCA_SM_CK_5 AN24
C127
C128
C129
VCCA_SM_CK_NCTF_1 AM28
AM26
A CK
+1.8V_SM_CK VCCA_SM_CK_NCTF_2 2 2 2
VCCA_SM_CK_NCTF_3 AM25
BF21 VCC_SM_CK_1 VCCA_SM_CK_NCTF_4 AL25
BH20 AM24 +1.05V_M_HPLL +1.05V_M +1.05V_M_MPLL +1.05V_M
SM CK
VCC_SM_CK_2 VCCA_SM_CK_NCTF_5 L4
BG20 VCC_SM_CK_3 VCCA_SM_CK_NCTF_6 AL24
BF20 VCC_SM_CK_4 VCCA_SM_CK_NCTF_7 AM23 24mA Max. 2 1 139.2mA Max. 2 1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
AL23 BLM18AG121SN1D_0603~D L5
VCCA_SM_CK_NCTF_8
2
4.7U_0603_6.3V6M~D
LQH32CNR15M33L_1210~D
1 1 1 R120
+3.3V_RUN K47 0_0603_5%~D
+VCC_TX_LVDS VCC_TX_LVDS
C130
C131
C132
VCCA_TV_DAC_1 B24
1 2 +3.3V_RUN_HV C35 A24
1
VCC_HV_1 VCCA_TV_DAC_2 +1.5V_RUN 2 2 2
TV
R1076 0_0603_5%~D B35 1

VCC_HV_2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
A35
HV
VCC_HV_3 C133
1
C136
A32 1 22U_0805_6.3VAM~D
VCC_HDA 2
HDA
+VCC_PEG V48 VCC_PEG_1

C998
U48 VCC_PEG_2
2
V47
PEG
VCC_PEG_3 2
U47 VCC_PEG_4
+VCC_DMI
D TV/CRT
B B
U46 VCC_PEG_5 VCCD_TVDAC M25
+1.05V_M_DPLLA +1.05V_M_DPLLB
0.1U_0402_16V4Z~D
L28 +1.5V_RUN_QDAC +1.05V_M +1.05V_M

VCCD_QDAC L45 L46
AH48 VCC_DMI_1
1 AF48 VCC_DMI_2 VCCD_HPLL AF1 64.8mA Max. 2 1
10UH_LB2012T100MR_20%_0805~D
64.8mA Max. 2 1
10UH_LB2012T100MR_20%_0805~D
AH47
DMI
VCC_DMI_3
C137
0.1U_0402_16V4Z~D
220U_D2_4VY_R15M~D
0.1U_0402_16V4Z~D
220U_D2_4VY_R15M~D
AG47 VCC_DMI_4 VCCD_PEG_PLL AA47 1 1
+1.05V_M 1 1
2 + +
C741
C739
C742
C740
VCCD_LVDS_1 M38
0.1U_0402_16V4Z~D
LVDS
GMCH_VTTLF1 A8 L37
GMCH_VTTLF2 L1 VTTLF1 VCCD_LVDS_2 +1.05V_M_PEGPLL 2 2 2 2
VTTLF2
VTTLF
GMCH_VTTLF3AB2 1
VTTLF3
0.1U_0402_16V4Z~D
0.47U_0402_10V4Z~D
0.47U_0402_10V4Z~D
0.47U_0402_10V4Z~D
C140
1
1 1 1 2
C142
C143
C144
C141
+1.8V_MEM 2
2 2 2 +VCC_DMI
1U_0603_10V4Z~D
+1.8V_MEM +VCC_TX_LVDS
118.8mA Max. 1
2 1 +VCC_PEG
C743
2 1 PJP52
1000P_0402_50V7K~D
22U_0805_6.3V6M~D
L47 PAD-OPEN1x1m
HK1608R10J-T_0603~D 2
2 1 +1.05V_M
1 1 1 @ L6
LBC2518T91NM_1210~D
C744
C745
+
@ C145
+1.8V_MEM +1.8V_SM_CK 2 2 220U_D2_4VY_R15M~D
2
2 1
0.1U_0402_16V4Z~D
A L7 A
1_0603_5%~D
LQM21FN1R0N00 _0805~D
1
Rdc=0.1~0.2,rated 1
R121
current=220mA(MAX)
C146
C147
10U_0805_4VAM~D 2
2
2 1 Compal Electronics, Inc.

LA-4041P
5 4 3 2 1
5 4 3 2 1
U2G
+1.8V_MEM +VCC_GFXCORE
AP33 VCC_SM_1 VCC_AXG_NCTF_1 W28
330U_D2_2.5VY_R15M
AN33 VCC_SM_2 VCC_AXG_NCTF_2 V28
+1.05V_M
0.1U_0402_10V7K~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
330U_D2_2.5VY_R15M
330U_D2_2.5VY_R15M
U2F BH32 W26
VCC_SM_3 VCC_AXG_NCTF_3
1 BG32 VCC_SM_4 VCC_AXG_NCTF_4 V26 1 1 Layout Note:
@
2 1 1 BF32 VCC_SM_5 VCC_AXG_NCTF_5 W25
C148
C746
C747
D + BD32 V25 + + Place close to GMCH D
C149
C150
C151
AG34 VCC_1 BC32 VCC_SM_7 VCC_AXG_NCTF_7 W24
AC34 VCC_2 BB32 VCC_SM_8 VCC_AXG_NCTF_8 V24
1 2 2 2 2 2
AB34 VCC_3 BA32 VCC_SM_9 VCC_AXG_NCTF_9 W23
AA34 VCC_4 AY32 VCC_SM_10 VCC_AXG_NCTF_10 V23
Y34 VCC_5 AW32 VCC_SM_11 VCC_AXG_NCTF_11 AM21
V34 VCC_6 AV32 VCC_SM_12 VCC_AXG_NCTF_12 AL21
CRB 270uF U34 VCC_7 AU32 VCC_SM_13 VCC_AXG_NCTF_13 AK21
AM33 VCC_8 Layout Note: AT32 VCC_SM_14 VCC_AXG_NCTF_14 W21
AK33 VCC_9 Layout Note: Place on the edge AR32 VCC_SM_15 VCC_AXG_NCTF_15 V21
220U_D2_4VY_R15M~D
22U_0805_6.3VAM~D
0.22U_0402_10V4Z~D
POWER
AJ33 VCC_10 Place close to GMCH AP32 VCC_SM_16 VCC_AXG_NCTF_16 U21
1 AG33 VCC_11 AN32 VCC_SM_17 VCC_AXG_NCTF_17 AM20
1 1 AF33 VCC_12 BH31 VCC_SM_18 VCC_AXG_NCTF_18 AK20
C152
C153
+ BG31 W20
C154
AE33 VCC_13 BF31 VCC_SM_20 VCC_AXG_NCTF_20 U20
VCC CORE
AC33 VCC_14 BG30 VCC_SM_21 VCC_AXG_NCTF_21 AM19
2 2 2
AA33 VCC_15 BH29 VCC_SM_22 VCC_AXG_NCTF_22 AL19
Y33 VCC_16 BG29 VCC_SM_23 VCC_AXG_NCTF_23 AK19
0.47U_0402_16V4Z~D
1U_0603_10V4Z~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
10U_0805_10V4Z~D
22U_0805_6.3VAM~D
W33 VCC_17 BF29 VCC_SM_24 VCC_AXG_NCTF_24 AJ19
V33 VCC_18 BD29 VCC_SM_25 VCC_AXG_NCTF_25 AH19
VCC SM
U33 VCC_19 BC29 VCC_SM_26 VCC_AXG_NCTF_26 AG19 1 1 1 1 1 1
AH28 VCC_20 BB29 VCC_SM_27 VCC_AXG_NCTF_27 AF19
C748
C749
C750
C751
C752
C753
AF28 VCC_21 BA29 VCC_SM_28 VCC_AXG_NCTF_28 AE19
Layout Note: AC28 VCC_22 AY29 VCC_SM_29 VCC_AXG_NCTF_29 AB19
2 2 2 2 2 2
Place close to GMCH AA28 VCC_23 AW29 VCC_SM_30 VCC_AXG_NCTF_30 AA19
AJ26 VCC_24 AV29 VCC_SM_31 VCC_AXG_NCTF_31 Y19
AG26 VCC_25 AU29 VCC_SM_32 VCC_AXG_NCTF_32 W19
AE26 VCC_26 AT29 VCC_SM_33 VCC_AXG_NCTF_33 V19
AC26 VCC_27 AR29 VCC_SM_34 VCC_AXG_NCTF_34 U19
0.22U_0402_10V4Z~D
0.1U_0402_10V7K~D
AH25 VCC_28 AP29 VCC_SM_35 VCC_AXG_NCTF_35 AM17

AG25 VCC_29 VCC_AXG_NCTF_36 AK17
1 1 AF25 VCC_30 BA36 VCC_SM_36/NC VCC_AXG_NCTF_37 AH17 Layout Note: Inside GMCH
+1.05V_M
C155
C156
C C
AG24 VCC_31 BB24 VCC_SM_37/NC VCC_AXG_NCTF_38 AG17 cavity for VCC_AXG.
AJ23 VCC_32 BD16 VCC_SM_38/NC VCC_AXG_NCTF_39 AF17
AH23 VCC_33 BB21 VCC_SM_39/NC VCC_AXG_NCTF_40 AE17
2 2
POWER
AF23 VCC_34 AW16 VCC_SM_40/NC VCC_AXG_NCTF_41 AC17
VCC_NCTF_1 AM32 AW13 VCC_SM_41/NC VCC_AXG_NCTF_42 AB17
T32 VCC_35 VCC_NCTF_2 AL32 AT13 VCC_SM_42/NC VCC_AXG_NCTF_43 Y17
VCC_NCTF_3 AK32 VCC_AXG_NCTF_44 W17
AJ32 V17
VCC GFX NCTF

VCC_NCTF_4 VCC_AXG_NCTF_45
VCC_NCTF_5 AH32 VCC_AXG_NCTF_46 AM16
Layout Note: 1 2 VCC_NCTF_6 AG32 +VCC_GFXCORE Y26 VCC_AXG_1 VCC_AXG_NCTF_47 AL16
Inside GMCH cavity.R123
0_0402_5%~D VCC_NCTF_7 AE32 AE25 VCC_AXG_2 VCC_AXG_NCTF_48 AK16
VCC_NCTF_8 AC32 AB25 VCC_AXG_3 VCC_AXG_NCTF_49 AJ16
VCC_NCTF_9 AA32 AA25 VCC_AXG_4 VCC_AXG_NCTF_50 AH16
VCC_NCTF_10 Y32 AE24 VCC_AXG_5 VCC_AXG_NCTF_51 AG16
VCC_NCTF_11 W32 AC24 VCC_AXG_6 VCC_AXG_NCTF_52 AF16
VCC_NCTF_12 U32 AA24 VCC_AXG_7 VCC_AXG_NCTF_53 AE16
VCC_NCTF_13 AM30 Y24 VCC_AXG_8 VCC_AXG_NCTF_54 AC16
VCC_NCTF_14 AL30 AE23 VCC_AXG_9 VCC_AXG_NCTF_55 AB16
VCC_NCTF_15 AK30 AC23 VCC_AXG_10 VCC_AXG_NCTF_56 AA16
VCC_NCTF_16 AH30 AB23 VCC_AXG_11 VCC_AXG_NCTF_57 Y16
VCC_NCTF_17 AG30 AA23 VCC_AXG_12 VCC_AXG_NCTF_58 W16
VCC_NCTF_18 AF30 AJ21 VCC_AXG_13 VCC_AXG_NCTF_59 V16
VCC_NCTF_19 AE30 AG21 VCC_AXG_14 VCC_AXG_NCTF_60 U16
VCC_NCTF_20 AC30 AE21 VCC_AXG_15
VCC_NCTF_21 AB30 AC21 VCC_AXG_16
VCC_NCTF_22 AA30 AA21 VCC_AXG_17
VCC_NCTF_23 Y30 Y21 VCC_AXG_18
VCC_NCTF_24 W30 AH20 VCC_AXG_19
VCC NCTF
VCC_NCTF_25 V30 AF20 VCC_AXG_20

VCC_NCTF_26 U30 AE20 VCC_AXG_21
VCC_NCTF_27 AL29 AC20 VCC_AXG_22
VCC_NCTF_28 AK29 AB20 VCC_AXG_23
B B
VCC_NCTF_29 AJ29 AA20 VCC_AXG_24
VCC_NCTF_30 AH29 T17 VCC_AXG_25
VCC_NCTF_31 AG29 T16 VCC_AXG_26
VCC_NCTF_32 AE29 AM15 VCC_AXG_27
VCC_NCTF_33 AC29 AL15 VCC_AXG_28
VCC_NCTF_34 AA29 AE15 VCC_AXG_29
VCC_NCTF_35 Y29 AJ15 VCC_AXG_30
VCC_NCTF_36 W29 AH15 VCC_AXG_31
VCC_NCTF_37 V29 AG15 VCC_AXG_32
VCC_NCTF_38 AL28 AF15 VCC_AXG_33
VCC_NCTF_39 AK28 AB15 VCC_AXG_34
VCC_NCTF_40 AL26 AA15 VCC_AXG_35
VCC GFX
VCC_NCTF_41 AK26 Y15 VCC_AXG_36
VCC_NCTF_42 AK25 V15 VCC_AXG_37
VCC_NCTF_43 AK24 U15 VCC_AXG_38
VCC_NCTF_44 AK23 AN14 VCC_AXG_39
AM14 VCC_AXG_40
U14 AV44 VCCSM_LF1
VCC_AXG_41 VCC_SM_LF1
VCC SM LF
T14 BA37 VCCSM_LF2
VCC_AXG_42 VCC_SM_LF2 VCCSM_LF3
VCC_SM_LF3 AM40
AV21 VCCSM_LF4
VCC_SM_LF4 VCCSM_LF5
VCC_SM_LF5 AY5
CANTIGA ES_FCBGA1329~D AM10 VCCSM_LF6
VCC_SM_LF6 VCCSM_LF7
VCC_SM_LF7 BB13
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.22U_0402_10V4Z~D
0.22U_0402_10V4Z~D
0.47U_0402_10V4Z~D
1U_0402_6.3V4Z~D
1U_0402_6.3V4Z~D
VCC_AXG_SENSE AJ14 1 1 1 1 1 1 1
<49> VCC_AXG_SENSE VCC_AXG_SENSE
C157
C158
C159
C160
C161
C162
C163
VSS_AXG_SENSE AH14
<49> VSS_AXG_SENSE VSS_AXG_SENSE
2 2 2 2 2 2 2
A A
LA-4041P
5 4 3 2 1
5 4 3 2 1
U2I
U2J
AU48 VSS_1 VSS_100 AM36 BG21 VSS_199 VSS_297 AH8
AR48 VSS_2 VSS_101 AE36 L12 VSS_200 VSS_298 Y8
AL48 VSS_3 VSS_102 P36 AW21 VSS_201 VSS_299 L8
BB47 VSS_4 VSS_103 L36 AU21 VSS_202 VSS_300 E8
AW47 VSS_5 VSS_104 J36 AP21 VSS_203 VSS_301 B8
AN47 VSS_6 VSS_105 F36 AN21 VSS_204 VSS_302 AY7
AJ47 VSS_7 VSS_106 B36 AH21 VSS_205 VSS_303 AU7
AF47 VSS_8 VSS_107 AH35 AF21 VSS_206 VSS_304 AN7
AD47 VSS_9 VSS_108 AA35 AB21 VSS_207 VSS_305 AJ7
D D
AB47 VSS_10 VSS_109 Y35 R21 VSS_208 VSS_306 AE7
Y47 VSS_11 VSS_110 U35 M21 VSS_209 VSS_307 AA7
T47 VSS_12 VSS_111 T35 J21 VSS_210 VSS_308 N7
N47 VSS_13 VSS_112 BF34 G21 VSS_211 VSS_309 J7
L47 VSS_14 VSS_113 AM34 BC20 VSS_212 VSS_310 BG6
G47 VSS_15 VSS_114 AJ34 BA20 VSS_213 VSS_311 BD6
BD46 VSS_16 VSS_115 AF34 AW20 VSS_214 VSS_312 AV6
BA46 VSS_17 VSS_116 AE34 AT20 VSS_215 VSS_313 AT6
AY46 VSS_18 VSS_117 W34 AJ20 VSS_216 VSS_314 AM6
AV46 VSS_19 VSS_118 B34 AG20 VSS_217 VSS_315 M6
AR46 VSS_20 VSS_119 A34 Y20 VSS_218 VSS_316 C6
AM46 VSS_21 VSS_120 BG33 N20 VSS_219 VSS_317 BA5
V46 VSS_22 VSS_121 BC33 K20 VSS_220 VSS_318 AH5
R46 VSS_23 VSS_122 BA33 F20 VSS_221 VSS_319 AD5
P46 VSS_24 VSS_123 AV33 C20 VSS_222 VSS_320 Y5
H46 VSS_25 VSS_124 AR33 A20 VSS_223 VSS_321 L5
F46 VSS_26 VSS_125 AL33 BG19 VSS_224 VSS_322 J5
BF44 VSS_27 VSS_126 AH33 A18 VSS_225 VSS_323 H5
AH44 VSS_28 VSS_127 AB33 BG17 VSS_226 VSS_324 F5
AD44 VSS_29 VSS_128 P33 BC17 VSS_227 VSS_325 BE4
AA44 VSS_30 VSS_129 L33 AW17 VSS_228
Y44 H33 AT17 BC3
U44
T44
VSS_31
VSS_32
VSS_130
VSS_131 N32
K32
R17
M17
VSS_229
VSS_230 VSS VSS_327
VSS_328 AV3
AL3
M44
F44
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
F32
C32
H17
C17
VSS_231
VSS_232
VSS_233
VSS_329
VSS_330
VSS_331
R3
P3
BC43 VSS_36 VSS_135 A31 VSS_332 F3
AV43 VSS_37 VSS_136 AN29 BA16 VSS_235 VSS_333 BA2
AU43 VSS_38 VSS_137 T29 VSS_334 AW2
AM43 VSS_39 VSS_138 N29 AU16 VSS_237 VSS_335 AU2
J43 VSS_40 VSS_139 K29 AN16 VSS_238 VSS_336 AR2
C43 VSS_41 VSS_140 H29 N16 VSS_239 VSS_337 AP2
C C
BG42 VSS_42 VSS_141 F29 K16 VSS_240 VSS_338 AJ2
AY42 VSS_43 VSS_142 A29 G16 VSS_241 VSS_339 AH2
AT42 VSS_44 VSS_143 BG28 E16 VSS_242 VSS_340 AF2
AN42 VSS_45 VSS_144 BD28 BG15 VSS_243 VSS_341 AE2
AJ42 VSS_46 VSS_145 BA28 AC15 VSS_244 VSS_342 AD2
AE42 VSS_47 VSS_146 AV28 W15 VSS_245 VSS_343 AC2
N42 VSS_48 VSS_147 AT28 A15 VSS_246 VSS_344 Y2
L42 VSS_49 VSS_148 AR28 BG14 VSS_247 VSS_345 M2
BD41 VSS_50 VSS_149 AJ28 AA14 VSS_248 VSS_346 K2
AU41 VSS_51 VSS_150 AG28 C14 VSS_249 VSS_347 AM1
AM41 VSS_52 VSS_151 AE28 BG13 VSS_250 VSS_348 AA1
AH41 VSS_53 VSS_152 AB28 BC13 VSS_251 VSS_349 P1
AD41 VSS_54 VSS_153 Y28 BA13 VSS_252 VSS_350 H1
AA41 VSS_55 VSS_154 P28
Y41 VSS_56 VSS_155 K28 VSS_351 U24
U41 VSS_57 VSS_156 H28 AN13 VSS_255 VSS_352 U28
T41 VSS_58 VSS_157 F28 AJ13 VSS_256 VSS_353 U25
M41 VSS_59 VSS_158 C28 AE13 VSS_257 VSS_354 U29
G41 VSS_60 VSS_159 BF26 N13 VSS_258
B41 VSS_61 VSS_160 AH26 L13 VSS_259
BG40 VSS_62 VSS_161 AF26 G13 VSS_260 VSS_NCTF_1 AF32
BB40 VSS_63 VSS_162 AB26 E13 VSS_261 VSS_NCTF_2 AB32
AV40 VSS_64 VSS_163 AA26 BF12 VSS_262 VSS_NCTF_3 V32
AN40 VSS_65 VSS_164 C26 AV12 VSS_263 VSS_NCTF_4 AJ30
H40 VSS_66 VSS_165 B26 AT12 VSS_264 VSS_NCTF_5 AM29
E40 VSS_67 VSS_166 BH25 AM12 VSS_265 VSS_NCTF_6 AF29
AT39 BD25 AA12 AB29
VSS NCTF
VSS_68 VSS_167 VSS_266 VSS_NCTF_7
AM39 VSS_69 VSS_168 BB25 J12 VSS_267 VSS_NCTF_8 U26
AJ39 VSS_70 VSS_169 AV25 A12 VSS_268 VSS_NCTF_9 U23
AE39 VSS_71 VSS_170 AR25 BD11 VSS_269 VSS_NCTF_10 AL20
N39 VSS_72 VSS_171 AJ25 BB11 VSS_270 VSS_NCTF_11 V20
L39 VSS_73 VSS_172 AC25 AY11 VSS_271 VSS_NCTF_12 AC19
B B
B39 VSS_74 VSS_173 Y25 AN11 VSS_272 VSS_NCTF_13 AL17
BH38 VSS_75 VSS_174 N25 AH11 VSS_273 VSS_NCTF_14 AJ17
BC38 VSS_76 VSS_175 L25 VSS_NCTF_15 AA17
BA38 VSS_77 VSS_176 J25 Y11 VSS_275 VSS_NCTF_16 U17
AU38 VSS_78 VSS_177 G25 N11 VSS_276
AH38 VSS_79 VSS_178 E25 G11 VSS_277
AD38 BF24 C11 BH48
VSS SCB
VSS_80 VSS_179 VSS_278 VSS_SCB_1

AA38 VSS_81 VSS_180 AD12 BG10 VSS_279 VSS_SCB_2 BH1
Y38 VSS_82 VSS_181 AY24 AV10 VSS_280 VSS_SCB_3 A48
U38 VSS_83 VSS_182 AT24 AT10 VSS_281 VSS_SCB_4 C1
T38 VSS_84 VSS_183 AJ24 AJ10 VSS_282 VSS_SCB_5 A3
J38 VSS_85 VSS_184 AH24 AE10 VSS_283
F38 VSS_86 VSS_185 AF24 AA10 VSS_284 NC_26 E1
C38 VSS_87 VSS_186 AB24 M10 VSS_285 NC_27 D2
BF37 VSS_88 VSS_187 R24 BF9 VSS_286 NC_28 C3
BB37 VSS_89 VSS_188 L24 BC9 VSS_287 NC_29 B4
AW37 VSS_90 VSS_189 K24 AN9 VSS_288 NC_30 A5
AT37 VSS_91 VSS_190 J24 AM9 VSS_289 NC_31 A6
AN37 VSS_92 VSS_191 G24 AD9 VSS_290 NC_32 A43
AJ37 VSS_93 VSS_192 F24 G9 VSS_291 NC_33 A44
H37 E24 B9 B45
NC
VSS_94 VSS_193 VSS_292 NC_34

C37 VSS_95 VSS_194 BH23 BH8 VSS_293 NC_35 C46
BG36 VSS_96 VSS_195 AG23 BB8 VSS_294 NC_36 D47
BD36 VSS_97 VSS_196 Y23 AV8 VSS_295 NC_37 B47
AK15 VSS_98 VSS_197 B23 AT8 VSS_296 NC_38 A46
AU36 VSS_99 VSS_198 A23 NC_39 F48
VSS_199 AJ6 NC_40 E48
NC_41 C48
NC_42 B48
A A
LA-4041P
5 4 3 2 1
5 4 3 2 1
+1.8V_MEM +1.8V_MEM +V_DDR_MCH_REF

<11> DDR_A_DQS#[0..7]
+V_DDR_MCH_REF
<11> DDR_A_D[0..63]
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
JDIMMA
<11> DDR_A_DM[0..7] 1 VREF VSS 2
3 4 DDR_A_D4 1 1
DDR_A_D0 VSS DQ4 DDR_A_D5
<11> DDR_A_DQS[0..7] Layout Note: 5 DQ0 DQ5 6
C164
C165
DDR_A_D1 7 8
Place near JDIMMA 9
DQ1 VSS
10 DDR_A_DM0
<11> DDR_A_MA[0..14] VSS DM0 2 2
DDR_A_DQS#0 11 12
DDR_A_DQS0 DQS0# VSS DDR_A_D6
13 DQS0 DQ6 14
15 16 DDR_A_D7
DDR_A_D2 VSS DQ7
17 DQ2 VSS 18
D DDR_A_D3 DDR_A_D12 D
19 DQ3 DQ12 20
21 22 DDR_A_D13
DDR_A_D8 VSS DQ13
23 DQ8 VSS 24
+1.8V_MEM DDR_A_D9 25 26 DDR_A_DM1
DQ9 DM1
27 VSS VSS 28
DDR_A_DQS#1 29 30 M_CLK_DDR0
DQS1# CK0 M_CLK_DDR0 <10>
DDR_A_DQS1 31 32 M_CLK_DDR#0
DQS1 CK0# M_CLK_DDR#0 <10>
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
33 VSS VSS 34
1 1 1 1 1 DDR_A_D10 35 36 DDR_A_D14
DQ10 DQ14
C166
C167
C168
C169
C170
DDR_A_D11 37 38 DDR_A_D15
DQ11 DQ15
39 VSS VSS 40
2 2 2 2 2
41 VSS VSS 42
DDR_A_D17 DQ16 DQ20 DDR_A_D21
45 DQ17 DQ21 46
47 VSS VSS 48
DDR_A_DQS#2 49 50
DDR_A_DQS2 DQS2# NC DDR_A_DM2
51 DQS2 DM2 52
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
53 VSS VSS 54
1 1 1 1 DDR_A_D18 55 56 DDR_A_D22
DQ18 DQ22
C171
C172
C173
C174
DQ19 DQ23
59 VSS VSS 60
2 2 2 2 DDR_A_D25 DQ24 DQ28 DDR_A_D29
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 VSS VSS 72
75 DQ27 DQ31 76
77 VSS VSS 78
C DDR_CKE0_DIMMA DDR_CKE1_DIMMA C
<10> DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA <10>
81 VDD VDD 82
83 NC NC/A15 84
DDR_A_BS2 85 86 DDR_A_MA14
<11> DDR_A_BS2 BA2 NC/A14
87 VDD VDD 88
DDR_A_MA12 89 90 DDR_A_MA11
DDR_A_MA9 A12 A11 DDR_A_MA7
Layout Note: 91 A9 A7 92
Place one cap close to every 2 pullup 95
A8 A6
96
DDR_A_MA5 VDD VDD DDR_A_MA4
resistors terminated to +0.9V_DDR_VTT 97 A5 A4 98
DDR_A_MA1 A3 A2 DDR_A_MA0
101 A1 A0 102
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS1 DDR_A_BS1 <11>
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
<11> DDR_A_BS0 107 BA0 RAS# 108 DDR_A_RAS# <11>
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
<11> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <10>
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
<11> DDR_A_CAS# CAS# ODT0 M_ODT0 <10>
+0.9V_DDR_VTT DDR_CS1_DIMMA# 115 116 DDR_A_MA13
<10> DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
M_ODT1 119 120
<10> M_ODT1 NC/ODT1 NC
121 VSS VSS 122
DDR_A_D32 123 124 DDR_A_D36
125 DQ33 DQ37 126
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
127 VSS VSS 128

DDR_A_DQS#4 129 130 DDR_A_DM4
DDR_A_DQS4 DQS4# DM4
1 1 1 1 1 1 1 1 1 1 1 1 1 1 131 DQS4 VSS 132
133 134 DDR_A_D38
DDR_A_D34 VSS DQ38 DDR_A_D39
135 DQ34 DQ39 136
DDR_A_D35 137 138
2 2 2 2 2 2 2 2 2 2 2 2 2 2 DQ35 VSS DDR_A_D44
139 VSS DQ44 140
C175
C176
C177
C178
C179
C180
C181
C182
C183
C184
C185
C186
C187
C188
DDR_A_D40 141 142 DDR_A_D45

B DDR_A_D41 DQ40 DQ45 B
143 DQ41 VSS 144
145 146 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 DM5 DQS5 148
149 VSS VSS 150
DDR_A_D42 151 152 DDR_A_D46
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D48 157 158 DDR_A_D52
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 M_CLK_DDR1
NC,TEST CK1 M_CLK_DDR1 <10>
+0.9V_DDR_VTT 165 166 M_CLK_DDR#1
VSS CK1# M_CLK_DDR#1 <10>
DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
RN1 RN2 169 170
DDR_A_MA3 DQS6 DM6
1 4 4 1 DDR_A_MA12 171 VSS VSS 172
DDR_A_MA1 2 3 3 2 DDR_A_MA8 DDR_A_D50 173 174 DDR_A_D54
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D DDR_A_D51 DQ50 DQ54 DDR_A_D55
175 DQ51 DQ55 176
RN3 RN4 Layout Note: 177 VSS VSS 178
DDR_A_BS0 1 4 4 1 DDR_A_MA6 Place these resistor DDR_A_D56 179 180 DDR_A_D60
DDR_A_MA10 DQ56 DQ60
2 3 3 2 DDR_A_MA7 closely JDIMMA,all DDR_A_D57 181 DQ57 DQ61 182 DDR_A_D61
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D 183 184
RN5 RN6 trace length<750 mil DDR_A_DM7 VSS VSS DDR_A_DQS#7
185 DM7 DQS7# 186
DDR_CS0_DIMMA# 1 4 4 1 DDR_A_MA5 187 188 DDR_A_DQS7
DDR_A_RAS# VSS DQS7
2 3 3 2 DDR_A_MA9 DDR_A_D58 189 DQ58 VSS 190
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D DDR_A_D59 191 192 DDR_A_D62
RN8 DQ59 DQ62 DDR_A_D63
RN7 193 194
DDR_A_CAS# VSS DQ63
1 4 4 1 DDR_A_MA4 <17,24> MEM_SDATA
MEM_SDATA 195 SDA VSS 196
DDR_A_WE# 2 3 3 2 DDR_A_MA2 MEM_SCLK 197 198 R128 1 2 10K_0402_5%~D
<17,24> MEM_SCLK SCL SAO
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D +3.3V_M 199 200 R129 1 2 10K_0402_5%~D
RN10 VDDSPD SA1
RN9 201 202
G1 G2
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
DDR_CS1_DIMMA# 1 4 4 1 DDR_A_BS1
M_ODT1 2 3 3 2 DDR_A_MA0 1 1
C189
C190
A 56_0404_4P2R_5%~D 56_0404_4P2R_5%~D FOX_AS0A426-N4RN-7F~D A

RN11
DDR_CKE1_DIMMA 2 1 4 1 DDR_A_MA13
2 2
DIMMA
R130 3 2 M_ODT0
56_0402_5%~D 56_0404_4P2R_5%~D REVERSE
RN13
RN12 Layout Note:
DDR_CKE0_DIMMA 2 1 DDR_A_MA11
DDR_A_BS2 1
3
4
4
3 2 DDR_A_MA14
Place these resistor
closely JDIMMA,all
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
trace length TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Max=1.3" BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRII-SODIMM SLOT1
LA-4041P
5 4 3 2 1
5 4 3 2 1
+1.8V_MEM +1.8V_MEM +V_DDR_MCH_REF

<11> DDR_B_DQS#[0..7]
+V_DDR_MCH_REF
<11> DDR_B_D[0..63]
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
JDIMMB
<11> DDR_B_DM[0..7] Layout Note: 1 VREF VSS 2
3 4 DDR_B_D4 1 1
Place near JDIMMB DDR_B_D0 5
VSS DQ4
6 DDR_B_D5
<11> DDR_B_DQS[0..7] DQ0 DQ5
C191
C192
DDR_B_D1 7 8
DQ1 VSS DDR_B_DM0
<11> DDR_B_MA[0..14] 9 VSS DM0 10
DDR_B_DQS#0 2 2
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D7
15 VSS DQ7 16
DDR_B_D2 17 18
DDR_B_D3 DQ2 VSS DDR_B_D12
19 DQ3 DQ12 20
D +1.8V_MEM 21 22 DDR_B_D13 D
DDR_B_D8 VSS DQ13
23 DQ8 VSS 24
DDR_B_D9 25 26 DDR_B_DM1
DQ9 DM1
27 VSS VSS 28
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
DDR_B_DQS#1 29 30 M_CLK_DDR2
DQS1# CK0 M_CLK_DDR2 <10>
1 1 1 1 1 DDR_B_DQS1 31 32 M_CLK_DDR#2
DQS1 CK0# M_CLK_DDR#2 <10>
C193
C194
C195
C196
C197
33 VSS VSS 34
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
2 2 2 2 2
39 VSS VSS 40
41 VSS VSS 42
45 DQ17 DQ21 46
47 VSS VSS 48
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
DDR_B_DQS#2 49 50
DDR_B_DQS2 DQS2# NC DDR_B_DM2
1 1 1 1 51 DQS2 DM2 52
C198
C199
C200
C201
53 VSS VSS 54
57 DQ19 DQ23 58
2 2 2 2
59 VSS VSS 60
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
71 VSS VSS 72
75 DQ27 DQ31 76
77 VSS VSS 78
DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB
C <10> DDR_CKE2_DIMMB CKE0 NC/CKE1 DDR_CKE3_DIMMB <10> C
81 VDD VDD 82
83 NC NC/A15 84
Layout Note: DDR_B_BS2 85 86 DDR_B_MA14
<11> DDR_B_BS2 BA2 NC/A14
87 88
Place one cap close to every 2 pullup DDR_B_MA12 89
VDD VDD
90 DDR_B_MA11
DDR_B_MA9 A12 A11 DDR_B_MA7
resistors terminated to +0.9V_DDR_VTT 91 A9 A7 92
DDR_B_MA8 93 94 DDR_B_MA6
A8 A6
95 VDD VDD 96
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS1 DDR_B_BS1 <11>
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
<11> DDR_B_BS0 107 BA0 RAS# 108 DDR_B_RAS# <11>
+0.9V_DDR_VTT DDR_B_WE# 109 110 DDR_CS2_DIMMB#
<11> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <10>
111 VDD VDD 112
DDR_B_CAS# 113 114 M_ODT2
<11> DDR_B_CAS# CAS# ODT0 M_ODT2 <10>
DDR_CS3_DIMMB# 115 116 DDR_B_MA13
<10> DDR_CS3_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
M_ODT3 119 120

<10> M_ODT3 NC/ODT1 NC
121 VSS VSS 122
1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_B_D32 123 124 DDR_B_D36
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_B_DQS#4 129 130 DDR_B_DM4
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
C202
C203
C204
C205
C206
C207
C208
C209
C210
C211
C212
C213
C214
133 134 DDR_B_D38

DDR_B_D34 VSS DQ38 DDR_B_D39
135 DQ34 DQ39 136
DDR_B_D35 137 138
DQ35 VSS DDR_B_D44
139 VSS DQ44 140
DDR_B_D40 141 142 DDR_B_D45
DDR_B_D41 DQ40 DQ45
143 DQ41 VSS 144
B DDR_B_DQS#5 B
145 VSS DQS5# 146
DDR_B_DM5 147 148 DDR_B_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D46
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D52
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 M_CLK_DDR3
NC,TEST CK1 M_CLK_DDR3 <10>
+0.9V_DDR_VTT 165 166 M_CLK_DDR#3
VSS CK1# M_CLK_DDR#3 <10>
DDR_B_DQS#6 167 168
RN15 DDR_B_DQS6 DQS6# VSS DDR_B_DM6
RN14 169 170
DDR_B_MA3 DDR_B_MA9 DQS6 DM6
1 4 4 1 171 VSS VSS 172
DDR_B_MA1 2 3 3 2 DDR_B_MA12 DDR_B_D50 173 174 DDR_B_D54
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D DDR_B_D51 DQ50 DQ54 DDR_B_D55
175 DQ51 DQ55 176
RN16 RN17 177 178
DDR_B_BS0 DDR_B_MA14 DDR_B_D56 VSS VSS DDR_B_D60
1 4 4 1 179 DQ56 DQ60 180
DDR_B_MA10 2 3 3 2 DDR_B_MA11 DDR_B_D57 181 182 DDR_B_D61
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D DQ57 DQ61
Layout Note: 183 VSS VSS 184
RN18 RN19 Place these resistor DDR_B_DM7 185 186 DDR_B_DQS#7
DDR_B_BS1 DDR_B_MA5 DM7 DQS7# DDR_B_DQS7
1 4 4 1 closely JDIMMB,all 187 VSS DQS7 188
DDR_B_MA0 2 3 3 2 DDR_B_MA8 DDR_B_D58 189 190
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D trace length<750 mil DDR_B_D59 DQ58 VSS DDR_B_D62
191 DQ59 DQ62 192
RN20 RN21 193 194 DDR_B_D63 +3.3V_M
DDR_CS2_DIMMB# 1 DDR_B_MA7 MEM_SDATA VSS DQ63
4 4 1 <16,24> MEM_SDATA 195 SDA VSS 196
DDR_B_RAS# 2 3 3 2 DDR_B_MA6 MEM_SCLK 197 198
<16,24> MEM_SCLK SCL SAO
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D +3.3V_M 199 200 2 1
VDDSPD SA1
10K_0402_5%~D
RN22 RN23 201 202
GND GND
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
DDR_B_WE# 1 4 4 1 DDR_B_MA4 R131
1
DDR_B_CAS# 2 3 3 2 DDR_B_MA2 FOX_AS0A426-N8RN-7F_RV 10K_0402_5%~D
R132
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D 1 1
C215
C216
A RN24 A
DDR_CKE3_DIMMB 2 1 4 1 M_ODT2 DIMMB
R133 3 2 DDR_B_MA13
STANDARD
2
56_0402_5%~D 56_0404_4P2R_5%~D 2 2
RN26
RN25 Layout Note:
DDR_CS3_DIMMB# 2 DDR_B_BS2
M_ODT3 1
3
4
4
3
1
2 DDR_CKE2_DIMMB
Place these resistor
closely JDIMMB,all
56_0404_4P2R_5%~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
56_0404_4P2R_5%~D trace length TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Max=1.3" BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRII-SODIMM SLOT2
LA-4041P
5 4 3 2 1
5 4 3 2 1
+3.3V_M
1
R134
8.2K_0402_5%~D
+3.3V_M
2
+1.05V_VCCP THERMATRIP1#
R135
1
2.2K_0402_5%~D C 1
D D
1 2 2
B C218 R136
Q5 E 0.1U_0402_16V4Z~D 10K_0402_5%~D
3
MMST3904-7-F_SOT323-3~D 2 JFAN1
2
<7> H_THERMTRIP# <22> FAN1_DET# 1 1
+FAN1_VOUT 2 2
RB751S40T1_SOD523-2~D
FAN1_TACH_FB 3 5
+3.3V_M 3 G1
22U_0805_6.3VAM~D
4 4 G2 6
1
1 PWR_MON_GFX <49>
1
C219
D2 MOLEX_53398-0471~D
1
D38 PWR_MON <47>
R137 RB751S40T1_SOD523-2~D
8.2K_0402_5%~D 2 ISL88731_ICM_R 1 R932 2 ISL88731_ICM <48> Diode circuit at DP4/DN4 is used for skin
1
4.7K_0402_5%~D
temp sensor (placed optimally between CPU,
2
R938
2
+1.05V_VCCP THERMATRIP2# Place C221 close to the MCH and MEM).

R138 0_0402_5%~D Guardian pins as possible.
1
2.2K_0402_5%~D C 1
2
1 2 2 <38> BC_DAT_EMC4002
1
B C220 1 C 1
Q6 E 0.1U_0402_16V4Z~D 2 Q7
3
MMST3904-7-F_SOT323-3~D 2 C221 B MMST3904-7-F_SOT323-3~D @C222

@C222
1
E 100P_0402_50V8K~D
<10> THERMTRIP_MCH# <38> BC_CLK_EMC4002
3
R999 2 2200P_0402_50V7K~D 2
Place under CPU 200K_0402_1%~D Place C222 close to Q7 as
possible.
2
1
2 C 2
@C223
@ C223 2 C224 THERMISTOR OPTION:
100P_0402_50V8K~D B 2200P_0402_50V7K~D
E Q8 Single-ended routing to thermistor is permissible
3
1 MMST3904-7-F_SOT323-3~D 1 U3 (ground return). Place R139 and C226 near EMC4002

C Place C223 close to the Q8 as possible EMC4002 C
Place C224, C225 close to the Guardian pins as possible 10 SMDATA/BC-LINK_DATA 1 2 1 2

<7> H_THERMDA 11 39 R139
SMBCLK/BC-LINK_CLK VIN1 1.2K_0402_1%~D R140
1 VCP1 48
45 10KB_0603_1%_TSM1A103F34D3R~D
C225 VCP2
470P_0402_50V7K~D REM_DIODE1_P 36 44 REM_DIODE4_P
2 REM_DIODE1_N DP1/VREF_T DP4/DN8 REM_DIODE4_N
<7> H_THERMDC 35 DN1/THERM DN4/DP8 43
Place C228 close to the Guardian pins as possible
38 DP2 DP5/DN9 47 1 2
Q9 Place near DIMM 37 DN2 DN5/DP9 46
1 1 C226
1
C C228 REM_DIODE3_P 41 1 0.1U_0402_16V4Z~D

@ C227 2200P_0402_50V7K~D REM_DIODE3_N DP3/DN7 DP6/VREF_T2
2 40 DN3/DP7 DN6/VIN2 2
Place C227 close 100P_0402_50V8K~D B Q9
2 E MMST3904-7-F_SOT323-3~D 2
3
to Q9 2 1 +3.3V_M
+3.3V_M 1 2 +3VSUS_THRM 4 R141 10K_0402_5%~D
VCC
ATF_INT#/BC-LINK_IRQ# 12 BC_INT#_EMC4002 <38>
R142 1 +RTC_CELL 21 26 POWER_SW#
RTC_PWR3V POWER_SW#
1U_0603_10V4Z~D
0_0603_5%~D 1 27 ACAV_IN <38,48>

C229 ACAVAIL_CLR
THERMTRIP_SIO/PWM1/GPIO5 20 2 1 +3.3V_M
C230
0.1U_0402_16V4Z~D 25 R145 10K_0402_5%~D THERM_STP# <44>

2 SYS_SHDN#
<38,41> 3.3V_M_PWRGD 1 2 18 VCC_PWRGD 1 2 +RTC_CELL
2 R146 1
<41> ICH_PWRGD# 2 1K_0402_5%~D 17 3V_PWROK# 2 @ 1 @R147
@ R147 47K_0402_1%~D
R148 1K_0402_5%~D R211 10K_0402_5%~D
THERMATRIP1# 22
THERMATRIP2# THERMTRIP1#
23 THERMTRIP2# At maximum load current of 600mA,the the
THERMATRIP3# 24 19 2 1 +3.3V_SUS
THERMTRIP3# LDO_SHDN# R149 10K_0402_5%~D voltage drop across the should be keep
VSET 42 VSET LDO_POK 34 2.5V_RUN_PWRGD <37,41> in the range of 0.5V to 1V
B B
1
1 +3VSUS_THRM 2 1 3 33 LDO_SET
R151 +5V_RUN R150 4.7K_0402_5%~D ADDR_MODE/XEN LDO_SET
C231 953_0402_1%~D +3.3V_RUN
0.1U_0402_16V4Z~D 6 32 +3V_LDOIN 2 1
2 VDD_5V VDDH/VDD_5V2
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
5 31 R152
2
+3.3V_RUN VDD_5V VDDH/VDD_5V2 0.82_1210_1%~D

1 1
9 28 +1.8V_RUN
1 1 VDD_3V VDDL/VDD_3V2 +1.8V_RUN
C235
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
C232
C233
C234
Rset=953,Tp=88degree 1 1 +FAN1_VOUT 7 29
FAN_OUT LDO_OUT/FAN_OUT2 2 2
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
8 FAN_OUT LDO_OUT/FAN_OUT2 30
2 2
C236
C237
3.16K_0402_1%~D
1 1
1
FAN1_TACH_FB 15 16
2 2 TACH1/GPIO3 TACH2/GPIO4
C238
C239
R153
14 CLK_IN/GPIO2 PWM2/GPIO1 13
2 2 Ra
VSS
2
<38> EC_32KHZ_OUT EC_32KHZ_OUT
LDO_SET
49
5.1K_0402_1%~D
1
R154
2 1 PM_EXTTS# <10>
+3.3V_M R929 0_0402_5%~D
+RTC_CELL C1050 Rb
0.1U_0402_16V4Z~D
2
1 2 Pull-up Resistor For Remote1 SMBUS
1
U68
on ADDR_MODE/XEN mode Address
5
74AHC1G08GW_SOT353-5~D R155 Voltage margining circuit

1 8.2K_0402_5%~D
P
IN1 POWER_SW_IN# <38> for LDO output. Adjustable

POWER_SW# <= 4.7K +/- 5% 2N3904 2F(r/w)
4 O
2
* from 1.2 to 2.5V.
DOCK_PWR_SW# <38>
2
IN2
G
A A
10K 2N3904 2E(r/w) Ra=((LDO_OUT/1.11)-1)*Rb.
THERMATRIP3#
3
18K Thermistor 2F(r/w)

1
1 2 >= 33K Thermistor 2E(r/w)
@R1014
@ R1014 0_0402_5%~D C240
0.1U_0402_16V4Z~D
1 2
@R1015
@ R1015 0_0402_5%~D 2
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, FAN & Thermal Sensor
LA-4041P
5 4 3 2 1
5 4 3 2 1
JLVDS1 LCD Power

59 58 +15V_ALW +LCDVDD +3.3V_RUN
D
MGND1 Even_ClkIN+ LCD_BCLK+_MCH <12>
S
60 MGND2 Even_ClkIN- 57 LCD_BCLK-_MCH <12> 6
61 56 +LCDVDD +15V_ALW 4 5
MGND3 VSS
1
62 MGND4 Even_Rin2+ 55 LCD_B2+_MCH <12> 2
470_0402_5%~D
63 MGND5 Even_Rin2- 54 LCD_B2-_MCH <12> 1
1
+3.3V_RUN
100K_0402_5%~D
R158 Q12
G
64 MGND6 VSS 53 1
1
R161
65 52 100K_0402_5%~D SI3456DV-T1-E3_TSOP6~D
LCD_B1+_MCH <12>
3
MGND7 Even_Rin1+
R162
66 51 1 2 LDDC_CLK_MCH C241
LCD_B1-_MCH <12>
2
MGND8 Even_Rin1- R159 2.2K_0402_5%~D 0.1U_0402_16V4Z~D
67 MGND9 VSS 50
2
2N7002DW-T/R7_SOT363-6~D
68 49 1 2 LDDC_DATA_MCH
LCD_B0+_MCH <12>
6 2
MGND10 Even_Rin0+
100K_0402_5%~D
0.1U_0402_25V4Z~D
D R160 2.2K_0402_5%~D D
69 48 LCD_B0-_MCH <12>
2
MGND11 Even_Rin0-
1
70 47 @ 1
MGND12 VSS
R163
Odd_ClkIN+ 46 LCD_ACLK+_MCH <12> Place near to JLVDS1
Q13B
C242
45 Q13A
Odd_ClkIN- LCD_ACLK-_MCH <12>
44 2N7002DW-T/R7_SOT363-6~D 2 5
VSS 2
43 LCD_A2+_MCH <12>
2
Odd_Rin2+
1
42 LCD_A2-_MCH <12> D3
4
Odd_Rin2-
41
O
VSS
Odd_Rin1+ 40 LCD_A1+_MCH <12> <37> LCD_VCC_TEST_EN 3
39 @ LVDS CABLE
Odd_Rin1- LCD_A1-_MCH <12>
VSS 38 Part Number Description 1 2 I
Odd_Rin0+ 37 LCD_A0+_MCH <12>
36 DAA00000R0L PCB 03P LA-4051P REV0 M/B 2 Q15
Odd_Rin0- LCD_A0-_MCH <12> <12> ENVDD
G
35 DDTC124EUA-7-F_SOT323-3~D
VSS LDDC_DATA_MCH BAT54CW_SOT323~D
34 LDDC_DATA_MCH <12>
3
DATA EEDID LDDC_CLK_MCH
CLK EEDID 33 LDDC_CLK_MCH <12> 1 2
32 LVDS_CBL_DET# @ R164 0_0402_5%~D
VSS LVDS_CBL_DET# <22>
VEEDID 31 +3.3V_RUN
30 CAM_MIC_CBL_DET#
Diag_Loop_CAM CAM_MIC_CBL_DET# <22>
29 DMIC_CLK
MIC_CLK DMIC_CLK <27>
3.3V 28 +3.3V_RUN
27 DMIC0
MIC_SIG DMIC0 <27>
26 +CAMERA_VDD
5V USBP11_D-
USB- 25 Pin28 3.3VRUN is for Mic PWR
SD05.TCT_SOD323-2~D
SD05.TCT_SOD323-2~D
SD05.TCT_SOD323-2~D
24 USBP11_D+
USB+
1
GND 23
CONNTST 22
D47
D56
D48
21 LCD_SMBCLK
SMB_CLK LCD_SMBCLK <38>
20 LCD_SMBDAT
SMB_DATA LCD_SMBDAT <38>+3.3V_RUN
19 +INV_PWR_SRC @ @ @
2
INV_SRC
INV_SRC 18
INV_SRC 17 1 2
1
C C246 C
INV_SRC 16
15 0.1U_0603_50V4Z~D @ R165
VBL-
VBL- 14
13 10K_0402_5%~D
VBL-
12
2
VBL-
INV_PWM 11 1 2 BIA_PWM <12>
10 R166 0_0402_5%~D
+5V_ALW +5V_ALW
9 LCD_TST
TEST LCD_TST <37>
VDD 8 +LCDVDD 1
VDD 7
6 C245 @Q16
@ Q16
VDD
5 0.1U_0402_16V4Z~D Dual layout for Q17 +PWR_SRC FDS4435_NL_SO8~D
CONNTST
4 BREATH_BLUE_LED_LCD
PNL_BKLT_CBL_DET# <22> 2
Overlap on Q16 for pop option 40mil
PWR_LED
BATT2_LED 3 BATT_YELLOW_LED_LCD
BREATH_BLUE_LED_LCD <42>
BATT_YELLOW_LED_LCD <42>
40mil 8 +INV_PWR_SRC
2 BATT_BLUE_LED_LCD 1 7
BATT1_LED BATT_BLUE_LED_LCD <42> +3.3V_RUN +LCDVDD
VSS 1 2 6
1000P_0402_50V7K~D
3 5
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
JAE_FI-DP58SB-VF88L 1
1 1 +PWR_SRC R167 C247
4
C248
Q17 100K_0402_5%~D 0.1U_0603_50V4Z~D
2
C243
C244
SI3457DV-T1_TSOP6~D
2
2
2 2
D
6 +INV_PWR_SRC
S
4 5 PWR_SRC_ON
2
Close to JLVD1.28 Close to JLVD1.6,7,8 1
Q18
G
2N7002W-7-F_SOT323-3~D
S
1 2 1 3
R168 100K_0402_5%~D
B B
G
2
PWR_SRC_ON
+CAMERA_VDD
<28,37,40,41> RUN_ON
PMV45EN_SOT23-3~D @U50
@ U50 SI3457DV : P CHANNAL FDS4435: P CHANNAL
Q125 1 3 USBP11_D-
GND IO2
USBP11_D+ 2 4 +CAMERA_VDD
IO1 VIN
S
3 1 +CAMERA_VDD_R 2 1 +3.3V_RUN
@R935 PRTR5V0U2X_SOT143-4~D
0.1U_0402_16V4Z~D
10U_1206_16V4Z~D
0_0603_5%~D
G
1 1
2
2 1 +5V_RUN
C249
C250
R936
1 0_0603_5%~D
2 2
C1043 @ L59
0.1U_0402_16V4Z~D DLW21SN121SQ2L_4P~D
2 USBP11- USBP11_D-
<24> USBP11- 1 1 2 2
+15V_ALW
USBP11+ 4 3 USBP11_D+
<24> USBP11+ 4 3
100K_0402_5%~D
1
R937
1 2
R457 0_0402_5%~D
1 2
2
R513 0_0402_5%~D
A A
2N7002W-7-F_SOT323-3~D
1
D
0.1U_0402_25V4K~D
1
Q126
<37> CCD_OFF 2
C1023
G
S DELL CONFIDENTIAL/PROPRIETARY
3

Title
LVDS Conn
1.0
5 4 3 2 1
2 1
DA204U_SOT323-3~D
DA204U_SOT323-3~D
DA204U_SOT323-3~D
+5V_RUN
1
@ @ @
SDM10U45-7_SOD523-2~D
2
D5
D6
D7
+3.3V_RUN
D8
2
1
+5V_RUN_CRT
RED_CRT 1 2 RED_CRT_L 1 2
R830 0_0603_5%~D L61
BLM18BB470SN1D_0603~D
GREEN_CRT 1 2 GREEN_CRT_L 1 2
R831 0_0603_5%~D L62 +CRT_VCC
BLM18BB470SN1D_0603~D
5A_125V_R451005.MRL~D
0.01U_0402_16V7K~D
BLUE_CRT 1 2 BLUE_CRT_L 1 2
R832 0_0603_5%~D L63
2
10P_0402_50V8J~D
10P_0402_50V8J~D
10P_0402_50V8J~D
0_1206_5%~D
BLM18BB470SN1D_0603~D 1
2
150_0402_1%~D
150_0402_1%~D
150_0402_1%~D
22P_0402_50V8J~D
22P_0402_50V8J~D
22P_0402_50V8J~D
10P_0402_50V8J~D
10P_0402_50V8J~D
10P_0402_50V8J~D
1 1 1 1 1 1 @
R171
C254
1 1 1
C255
C256
C257
C390
C518
C996
F2
R172
R173
R174
2
C251
C252
C253
1
2 2 2 2 2 2
1
@ @ @ 2 2 2 JCRT1
6
11
R 1
+5V_RUN_SYNC 7
+3.3V_RUN 12
G 2
B U4 B
8 16
2.2K_0402_5%~D
2.2K_0402_5%~D
1K_0402_5%~D
1K_0402_5%~D
4 JVGA_HS 13 17
VCC
1
10 B 3
VCC
R794
R793
@ R175
@ R176
18 48 DAT_DDC2_CRT +CRT_VCC 9
VCC 0B1 CLK_DDC2_CRT JVGA_VS
27 VCC 1B1 47 14
38 43 VSYNC_BUF M_ID2# 4
VCC 2B1 HSYNC_BUF
50 42 To MB CRT Conn. 10
2
VCC 3B1 RED_CRT
56 VCC 4B1 37 15
36 GREEN_CRT 5
DAT_DDC2 5B1 BLUE_CRT DAT_DDC2_CRT
<12> DAT_DDC2 2 A0 6B1 32
CLK_DDC2 3 31 CLK_DDC2_CRT SUYIN_070546FR015S558ZR
<12> CLK_DDC2 A1 7B1
<12> CRT_VSYNC 7 A2 8B1 22
<12> CRT_HSYNC 8 A3 9B1 23
<12> CRT_RED 11 A4
<12> CRT_GRN 12 A5
<12> CRT_BLU 14 A6 1
15 A7
19 46 DAT_DDC2_DOCK L11 C258
A8 0B2 CLK_DDC2_DOCK DAT_DDC2_DOCK <35> BLM18AG121SN1D_0603~D
20 A9 1B2 45 CLK_DDC2_DOCK <35>
VSYNC_DOCK HSYNC_CRT 2
2B2 41 VSYNC_DOCK <35> 1 2 HSYNC_L2 1 2 0.1U_0402_16V4Z~D
CRT_SWITCH HSYNC_DOCK R177 0_0402_5%~D L12
<37> CRT_SWITCH 17 SEL 3B2 40
35 RED_DOCK HSYNC_DOCK <35> To Dock Conn. BLM18AG121SN1D_0603~D
4B2 GREEN_DOCK RED_DOCK <35> VSYNC_CRT
1 GND 5B2 34 GREEN_DOCK <35> 1 2 VSYNC_L2 1 2
6 30 BLUE_DOCK R178 0_0402_5%~D
GND 6B2 BLUE_DOCK <35>
9 GND 7B2 29
CRT_SWITCH 13
16
GND 8B2 25
26
GND 9B2
0: MB 21
24
GND
GND +3.3V_RUN
1: Docking (APR/ EPR) 28 GND
33 GND NC 52
39 GND NC 5
22P_0402_50V8J~D
22P_0402_50V8J~D
44 GND NC 54
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
49 GND NC 51 1 1
53 GND
C267
C268
55 GND 1 1 1 1 1 1 1 1
2 2
C259
C260
C261
C262
C263
C264
C265
C266
TS3DV520ERHUR_QFN56_11X5~D
@ @
2 2 2 2 2 2 2 2
+5V_RUN
2
D9
SDM10U45-7_SOD523-2~D
1
1 2 +5V_RUN_SYNC 1 2
R179 1K_0402_5%~D
C269
5
0.1U_0402_16V4Z~D
P
OE#
HSYNC_BUF 2 4 HSYNC_CRT
A Y
G
U5
SN74AHCT1G125GW_SC70-5~D
3
A A
1 2
5
C270
0.1U_0402_16V4Z~D
P
OE#
VSYNC_BUF 2 4 VSYNC_CRT
A Y
G
U6
SN74AHCT1G125GW_SC70-5~D
3
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CRT/Video switch
LA-4041P
2 1
2 1
SW for MB side SW for eDOCK side Display port Connector

+3.3V_RUN
2
0_1206_5%~D
R295
D10 @
B0540WS-7_SOD323-2~D
+5V_RUN C329 +5V_RUN C356
+3.3V_RUN_R 1
C271 0.1U_0402_16V4Z~D C272 0.1U_0402_16V4Z~D
0.1U_0402_10V7K~D U75 0.1U_0402_10V7K~D U77
2 1 2 1
2 1 DPB_AUX_C 2 8 2 1 DPC_AUX_C 2 8
<12> DPB_AUX 1A VCC <12> DPC_DOCK_AUX 1A VCC
DPB_AUX#_C 5 3 DPB_AUX_SW DPC_AUX#_C 5 3 DPC_AUX_DOCK
2A 1B DPB_AUX#_SW 2A 1B DPC_AUX#_DOCK DPC_AUX_DOCK <35>
<12> DPB_AUX# 2 1 1 1OE# 2B 6 <12> DPC_DOCK_AUX# 2 1 1 1OE# 2B 6 DPC_AUX#_DOCK <35>
7 2OE# GND 4 7 2OE# GND 4
C273 C274
0.1U_0402_10V7K~D SN74CBTD3306CPWR_TSSOP8~D 0.1U_0402_10V7K~D SN74CBTD3306CPWR_TSSOP8~D
2
0_1206_5%~D
@
+5V_RUN C1073 +5V_RUN C1074
R184
0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D F3
U76 U78 1206L150PR~D +VDISPLAY_VCC
1 2 1 2
<10> SDVO_CTRLCLK 2 8 <10> DDPC_CTRLCLK 2 8
1
1A VCC 1A VCC
0.01U_0402_16V7K~D
<10> SDVO_CTRLDATA 5 2A 1B 3 <10,12> DDPC_CTRLDATA 5 2A 1B 3
10U_0805_10V6K~D
1 1OE# 2B 6 1 1OE# 2B 6
7 4 +3.3V_RUN 7 4 +3.3V_RUN 1 1
2OE# GND 2OE# GND
C275
C485
SN74CBTD3306CPWR_TSSOP8~D 2 1 SN74CBTD3306CPWR_TSSOP8~D 2 1
B B
C277 C276 2 2
5
0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
P
NC
NC
DPB_CA_DET# 4 2 DPB_CA_DET DPC_CA_DET# 4 2 DPC_CA_DET
Y A Y A DPC_CA_DET <35>
G
U8 U7
NC7SZ04P5X_NL_SC70-5~D NC7SZ04P5X_NL_SC70-5~D JDP1
3
20 DP_PWR
19 RTN
DPB_MB_HPD 18
DPB_MB_AUX# HP_DET
17 AUX_CH-
16 GND
DPB_MB_AUX 15
DPB_MB_P14 AUX_CH+
14 GND
C984 DPB_MB_CA_DET 13
0.033U_0402_16V7K~D DPB_MB_LANE3#_C CA_DET
12 LANE3- GND 21
2 1 DPB_DOCK_HPD 11 22
DPB_MB_LANE3_C LANE3_shield GND
10 LANE3+ GND 23
DPB_MB_LANE2#_C 9 24
LANE2- GND
8 LANE2_shield
Close to R188 DPB_MB_LANE2_C 7
U9 DPB_MB_LANE1#_C LANE2+
Its for Enhance ESD on dock issue. 6 LANE1-
5 LANE1_shield
+3.3V_RUN +5V_RUN DPB_MB_LANE1_C 4
DPB_MB_LANE0 C278 LANE1+
<12> DPB_LANE_P0_C 3 ML_IN 0(p) ML_A 0(p) 56 2 1 0.1U_0402_10V7K~D DPB_MB_LANE0_C DPB_MB_LANE0#_C 3 LANE0-
4 55 DPB_MB_LANE0# C279 2 1 0.1U_0402_10V7K~D DPB_MB_LANE0#_C 2
<12> DPB_LANE_N0_C ML_IN 0(n) ML_A 0(n) LANE0_shield
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.01U_0402_16V7K~D
1000P_0402_50V7K~D
DPB_MB_LANE0_C 1 LANE0+
1U_0603_10V4Z~D
6 53 DPB_MB_LANE1 C280 2 1 0.1U_0402_10V7K~D DPB_MB_LANE1_C 1 2 DPB_MB_CA_DET

<12> DPB_LANE_P1_C ML_IN 1(p) ML_A 1(p)
1 1 1 1 1 1 7 52 DPB_MB_LANE1# C281 2 1 0.1U_0402_10V7K~D DPB_MB_LANE1#_C R185 @ 1M_0402_5%~D MOLEX_105019-0001
<12> DPB_LANE_N1_C ML_IN 1(n) ML_A 1(n)
1 2 DPB_MB_HPD
C1001
C1002
C1003
C1004
C1005
C1006
9 50 DPB_MB_LANE2 C282 2 1 0.1U_0402_10V7K~D DPB_MB_LANE2_C R186 100K_0402_5%~D

10 49 DPB_MB_LANE2# C283 2 1 0.1U_0402_10V7K~D DPB_MB_LANE2#_C 1 2 DPB_DOCK_CA_DET
2 2 2 2 2 2 <12> DPB_LANE_N2_C ML_IN 2(n) ML_A 2(n) R187 @ 1M_0402_5%~D
12 47 DPB_MB_LANE3 C284 2 1 0.1U_0402_10V7K~D DPB_MB_LANE3_C 1 2 DPB_DOCK_HPD D11 @
13 46 DPB_MB_LANE3# C285 2 1 0.1U_0402_10V7K~D DPB_MB_LANE3#_C R188 100K_0402_5%~D DPB_MB_LANE1#_C 1 10 DPB_MB_LANE1#_C
<12> DPB_LANE_N3_C ML_IN 3(n) ML_A 3(n)
1 2 DPB_MB_P14
45 DPB_MB_AUX R797 5.1M_0603_1% DPB_MB_LANE1_C 2 9 DPB_MB_LANE1_C
+3.3V_RUN DPB_AUX_SW AUX_A (p) DPB_MB_AUX# DPC_CA_DET
36 AUX (p) AUX_A (n) 43 1 2
DPB_AUX#_SW 35 R377 1M_0402_5%~D DPB_MB_LANE0#_C 4 7 DPB_MB_LANE0#_C
AUX (n)
100K_0402_5%~D
DPB_MB_LANE0_C 5 6 DPB_MB_LANE0_C
DP_MB_HPD_EN 40 25 DPB_DOCK_LANE0 C286 2 1 0.1U_0402_10V7K~D
HPD_A ML_B 0(p) DPB_DOCK_LANE0_C <35>
2
DPB_DOCK_HPD 32 24 DPB_DOCK_LANE0# C287 2 1 0.1U_0402_10V7K~D 3

<35> DPB_DOCK_HPD HPD_B ML_B 0(n) DPB_DOCK_LANE0#_C <35>
R189
22 DPB_DOCK_LANE1 C288 2 1 0.1U_0402_10V7K~D 8

DPB_MB_CA_DET ML_B 1(p) DPB_DOCK_LANE1# C289 DPB_DOCK_LANE1_C <35>
41 CAD_A ML_B 1(n) 21 2 1 0.1U_0402_10V7K~D DPB_DOCK_LANE1#_C <35>
DPB_DOCK_CA_DET 33 RCLAMP0524P.TCT~D
<35> DPB_DOCK_CA_DET
1
CAD_B DPB_DOCK_LANE2 C290

ML_B 2(p) 19 2 1 0.1U_0402_10V7K~D DPB_DOCK_LANE2_C <35>
18 DPB_DOCK_LANE2# C291 2 1 0.1U_0402_10V7K~D
+3.3V_RUN_LP ML_B 2(n) DPB_DOCK_LANE2#_C <35> D12 @
30 LP
16 DPB_DOCK_LANE3 C292 2 1 0.1U_0402_10V7K~D DPB_MB_LANE3#_C 1 10 DPB_MB_LANE3#_C
ML_B 3(p) DPB_DOCK_LANE3# C293 DPB_DOCK_LANE3_C <35>
ML_B 3(n) 15 2 1 0.1U_0402_10V7K~D DPB_DOCK_LANE3#_C <35>
DP_PRIORITY 29 +3.3V_RUN DPB_MB_LANE3_C 2 9 DPB_MB_LANE3_C
<37> DP_PRIORITY Priority
28 DPB_DOCK_AUX
AUX_B (p) DPB_DOCK_AUX <35>
2
100K_0402_5%~D
26 DPB_DOCK_AUX# R875 2 1 100K_0402_5%~D DPB_MB_AUX @ 2 R209 1 100K_0402_5%~D DPB_MB_LANE2#_C 4 7 DPB_MB_LANE2#_C

AUX_B (n) DPB_DOCK_AUX# <35>
R190
R877 2 @ 1 100K_0402_5%~D DPB_MB_AUX# 2 R278 1 100K_0402_5%~D DPB_MB_LANE2_C 5 6 DPB_MB_LANE2_C

37 DPB_HPD_R
HPD R878 2 @ 1 100K_0402_5%~D DPB_DOCK_AUX @ 2 R336 1 100K_0402_5%~D 3
1
39 DPB_CA_DET R880 2 @ 1 100K_0402_5%~D DPB_DOCK_AUX# @ 2 R337 1 100K_0402_5%~D 8

CAD
1 DPVadj DPC_DOCK_AUX @ 2 R419 1 100K_0402_5%~D RCLAMP0524P.TCT~D
1
2
5.11K_0402_1%~D
R382 DPC_DOCK_AUX# @ 2 R647 1 100K_0402_5%~D D13 @

R193
+3.3V_RUN 38 5 1M_0402_5%~D DPB_MB_CA_DET 1 10 DPB_MB_CA_DET

VDD*1 GND
GND 11
+3.3V_RUN 2 20 R381 1 @ 2 100K_0402_5%~D DPB_AUX_SW @ 2 R1066 1 100K_0402_5%~D DPB_MB_HPD 2 9 DPB_MB_HPD
+5V_RUN
2
VDD GND
A 8 VDD GND 27 A
14 31 R1067 2 @ 1 100K_0402_5%~D DPB_AUX#_SW @ 2 R674 1 100K_0402_5%~D DPB_MB_AUX# 4 7 DPB_MB_AUX#
VDD GND
2
17 VDD GND 42
R798 23 44 DPB_MB_AUX 5 6 DPB_MB_AUX
VDD GND
20K_0402_5%~D 34 VDD GND 51 R380 2 @ 1 100K_0402_5%~D DPC_AUX_DOCK @ 2 R650 1 100K_0402_5%~D
48 VDD 3
54 57
1
VDD Thermal GND R1068 2 @ 8

DPB_HPD# <12> 1 100K_0402_5%~D DPC_AUX#_DOCK @ 2 R1069 1 100K_0402_5%~D
1
D RCLAMP0524P.TCT~D
2
BSS138_SOT23~D
Q10
DPB_HPD_R 2 TS2DP512_QFN56_8X8~D
G R824
Place close to JDP1 connector
S 7.5K_0402_5%~D
3
100K_0402_5%~D
2
+3.3V_RUN
1
R191
1 2
R918
<35,37> DOCK_DET# 1 @2 C1011 0.1U_0402_16V4Z~D
1
0_0402_5%~D
1 R919 2 1
P
<37> DP_MB_EN IN1

0_0402_5%~D 4 DP_MB_HPD_EN
DPB_MB_HPD O
2 IN2
G
Pin30 Level State Description 74AHC1G08GW_SOT353-5~D DELL CONFIDENTIAL/PROPRIETARY

3
U60
Hi Normal Mode Standard operational mode for device Compal Electronics, Inc.
LP Low Low power Mode Device is forced into a low power mode PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
causing the output s to go to a high-Z BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Display port
state, all other inputs are ignore NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
LA-4041P
2 1
5 4 3 2 1
+3.3V_RUN
R194 1 2 8.2K_0402_5%~D PCI_DEVSEL# <31> PCI_AD[0..31]

D U10B D
R195 1 2 8.2K_0402_5%~D PCI_STOP# PCI_AD0 D11 F1 PCI_REQ0#
PCI_AD1 AD0 REQ0# PCI_GNT0#
R196 1 2 8.2K_0402_5%~D PCI_TRDY# PCI_AD2
C8
D9
AD1 PCI GNT0# G4
B6 PCI_REQ1#
AD2 REQ1#/GPIO50 PCI_REQ1# <31>
PCI_AD3 E12 A7 PCI_GNT1#
AD3 GNT1#/GPIO51 PCI_GNT1# <31>
R197 1 2 8.2K_0402_5%~D PCI_FRAME# PCI_AD4 E9 AD4 REQ2#/GPIO52 F13 PCIE_MCARD2_DET# <34>
PCI_AD5 C9 F12 GNT2#/GPIO53 +3.3V_ALW_ICH
AD5 GNT2#/GPIO53 T165PAD~D
R198 1 2 8.2K_0402_5%~D PCI_PLOCK# PCI_AD6 E10 AD6 REQ3#/GPIO54 E6 PCIE_MCARD3_DET# <34>
C294
PCI_AD7 B7 F6 GNT3#/GPIO55 0.1U_0402_16V4Z~D
R199 1 AD7 GNT3#/GPIO55
2 8.2K_0402_5%~D PCI_IRDY# PCI_AD8 C7 AD8
PCI_AD9 C5 D8 PCI_C_BE0# PCI_C_BE0# <31>
R200 1 AD9 C/BE0#
2 8.2K_0402_5%~D PCI_SERR# PCI_AD10 G11 AD10 C/BE1# B4 PCI_C_BE1# PCI_C_BE1# <31>
PCI_AD11 F8 D6 PCI_C_BE2# PCI_C_BE2# <31>
R201 1 AD11 C/BE2#
2 8.2K_0402_5%~D PCI_PERR# PCI_AD12 PCI_C_BE3#
14
F11 AD12 C/BE3# A5 PCI_C_BE3# <31>
PCI_AD13 E7
PCI_AD14 AD13 PCI_IRDY# PCI_PCIRST#
A3 D3 1
P
AD14 IRDY# PCI_IRDY# <31> IN1
PCI_AD15 D2 E3 PCI_PAR 3 PCI_RST#
AD15 PAR PCI_PAR <31> OUT PCI_RST# <31>
PCI_AD16 F10 R1 PCI_PCIRST# 2
AD16 PCIRST# IN2
G
PCI_AD17 D5 C6 PCI_DEVSEL#
+3.3V_RUN AD17 DEVSEL# PCI_DEVSEL# <31>
PCI_AD18 D10 E4 PCI_PERR# U11A
PCI_PERR# <31>
7
PCI_AD19 AD18 PERR# PCI_PLOCK# 74VHC08MTCX_NL_TSSOP14~D
B3 AD19 PLOCK# C2
PCI_AD20 F7 J4 PCI_SERR#
AD20 SERR# PCI_SERR# <31>
R202 1 2 8.2K_0402_5%~D PCI_PIRQA# PCI_AD21 C3 AD21 STOP# A4 PCI_STOP#
PCI_STOP# <31>
PCI_AD22 F3 F5 PCI_TRDY#
AD22 TRDY# PCI_TRDY# <31> +3.3V_ALW_ICH
R203 1 2 8.2K_0402_5%~D PCI_PIRQB# PCI_AD23 F4 D7 PCI_FRAME#
AD23 FRAME# PCI_FRAME# <31>
PCI_AD24 C1
R204 1 AD24
2 8.2K_0402_5%~D PCI_PIRQC# PCI_AD25 PCI_PLTRST#
14
G7 AD25 PLTRST# C14
PCI_AD26 H7 D4 CLK_PCI_ICH
AD26 PCICLK CLK_PCI_ICH <6>
R205 1 2 8.2K_0402_5%~D PCI_PIRQD# PCI_AD27 D1 R2 ICH_PME# PCI_PLTRST# 4
P
AD27 PME# ICH_PME# <37> IN1
PCI_AD28 G5 6 PLTRST1#
AD28 OUT PLTRST1# <10,32>
R207 1 2 8.2K_0402_5%~D PCI_REQ0# PCI_AD29 H6 AD29 5 IN2
G
PCI_AD30 G1
C AD30 C
R208 1 2 8.2K_0402_5%~D PCI_REQ1# PCI_AD31 H3 U11B
7
AD31 74VHC08MTCX_NL_TSSOP14~D
R702 1 2 100K_0402_5%~D FAN1_DET#
PCI_PIRQA# J5
Interrupt I/F H4 LVDS_CBL_DET#
PIRQA# PIRQE#/GPIO2 LVDS_CBL_DET# <19>
R755 1 2 100K_0402_5%~D LVDS_CBL_DET# PCI_PIRQB# E1 K6 PNL_BKLT_CBL_DET#
<31> PCI_PIRQB# PIRQB# PIRQF#/GPIO3 PNL_BKLT_CBL_DET# <19> +3.3V_ALW_ICH
PCI_PIRQC# J6 F2 CAM_MIC_CBL_DET#
<31> PCI_PIRQC# PIRQC# PIRQG#/GPIO4 CAM_MIC_CBL_DET# <19>
R212 1 2 100K_0402_5%~D CAM_MIC_CBL_DET# PCI_PIRQD# C4 G2 FAN1_DET#
<31> PCI_PIRQD# PIRQD# PIRQH#/GPIO5 FAN1_DET# <18>
14
R817 1 2 100K_0402_5%~D PNL_BKLT_CBL_DET# ICH9M REV 1.0
10
P
IN1 PLTRST2#
OUT 8 PLTRST2# <37,38>
9 IN2
G
U11C
7
74VHC08MTCX_NL_TSSOP14~D
+3.3V_ALW_ICH
14
13
P
IN1
OUT 11 PLTRST3# PLTRST3# <34,36>
12 IN2
G
U11D
7
PCI_GNT0# ICH_SPI_CS1#
<24> ICH_SPI_CS1#
GNT3#/GPIO55
1
B B
1
@ R215 R213 @ R214

@R214
1K_0402_5%~D 1K_0402_5%~D 1K_0402_5%~D
2
2
2
Place closely pin U10.D4

CLK_PCI_ICH
2
A16 away override strap. Boot BIOS Strap
@ R216
@R216
10_0402_5%~D
Low = A16 swap override enabled.
GNT3#/GPIO55 PCI_GNT0# SPI_CS1# Boot BIOS Location
CLK_ICH_TERM 1
High = Default.
* 0 1 SPI
1 0 PCI 1
@ C295
@C295
8.2P_0402_50V8J~D
2
1 1 LPC
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT ICH9-M(1/4)
1.0
5 4 3 2 1
5 4 3 2 1
+RTC_CELL +RTC_CELL
1
R217 R218
332K_0402_1%~D 332K_0402_1%~D
2
ICH_INTVRMEN LAN100_SLP
2
@ R219
@R219 @ R220
0_0402_5%~D 0_0402_5%~D
D +3.3V_ALW_ICH D
1
Package
2 1 GLAN_DOCK#
R221 10K_0402_5%~D 9.6X4.06 mm
ICH9M Internal VR Enable Strap ICH9M LAN100 SLP Strap
(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5) (Internal VR for VccLAN1.05 and VccCL1.05)
C296
CMOS_CLR1 CMOS setting ICH_RTCX1

CIS 2 1
ICH_INTVRMEN Low = Internal VR Disabled ICH_LAN100_SLP Low = Internal VR Disabled
Shunt Clear CMOS High = Internal VR Enabled(Default) High = Internal VR Enabled(Default)
1
4P_0402_50V8B~D
2
Open Keep CMOS Y1 R222
10M_0402_5%~D
32.768KHZ_12.5PF_1TJE125DP1~D
ME_CLR1 TPM setting LPC_LAD[0..3] <36,37,38>
2
C297 R223 U10A +3.3V_RUN
Shunt Clear ME RTC Registers 4P_0402_50V8B~D 0_0402_5%~D C23 K5 LPC_LAD0
RTCX1 FWH0/LAD0 LPC_LAD0 <36,37,38>
2 1 1 2 ICH_RTCX2 C24 K4 LPC_LAD1
RTCX2 FWH1/LAD1 LPC_LAD1 <36,37,38>
Open Keep ME RTC Registers L6 LPC_LAD2 +1.05V_VCCP SIO_A20GATE 2 1
FWH2/LAD2 LPC_LAD2 <36,37,38>
+RTC_CELL R224 1 2 20K_0402_5%~D ICH_RTCRST# A25 K2 LPC_LAD3 R230 10K_0402_5%~D
RTCRST# FWH3/LAD3 LPC_LAD3 <36,37,38>
SRTCRST#
RTC
LPC
R225 1 2 20K_0402_5%~D F20 SIO_RCIN# 2 1
R226 1 SRTCRST#
2 1M_0402_5%~D INTRUDER# C22 INTRUDER# FWH4/LFRAME# K3 LPC_LFRAME#
LPC_LFRAME# <36,37,38>
R231 10K_0402_5%~D
56_0402_1%~D
56_0402_1%~D
<BOM Structure>
1
@R227
@
@R228
@
@SHORT PADS~D ICH_INTVRMEN B22 J3 LPC_LDRQ0#
INTVRMEN LDRQ0# LPC_LDRQ0# <37>
R227
R228
@SHORT PADS~D LAN100_SLP A22 J1 LPC_LDRQ1#
LAN100_SLP LDRQ1#/GPIO23 LPC_LDRQ1# <37> +1.05V_VCCP
1 2 1 2 E25 N7 SIO_A20GATE
1 2 1 2 <29> LAN_CLK GLAN_CLK A20GATE SIO_A20GATE <38>
AJ27 H_A20M# H_FERR# 2 1
H_A20M# <7>
2
A20M# R233 56_0402_5%~D
<29> LAN_RSTSYNC C13 LAN_RSTSYNC
AJ25 H_DPRSTP#
C DPRSTP# H_DPRSTP# <8,10,47> C
LAN_RX0 F14 AE23 H_DPSLP#
LAN / GLAN
<29> LAN_RX0 LAN_RXD0 DPSLP# H_DPSLP# <8>
ME_CLR1 CMOS_CLR1 LAN_RX1 G13 R229
<29> LAN_RX1 LAN_RXD1
1 2 1 2 LAN_RX2 D14 AJ26 2 1
<29> LAN_RX2 LAN_RXD2 FERR# H_FERR# <7>
C298 1U_0603_10V4Z~D C299 1U_0603_10V4Z~D 56_0402_5%~D
LAN_TX0 D13 AD22 H_PWRGOOD
<29> LAN_TX0 LAN_TXD0 CPUPWRGD H_PWRGOOD <8>
LAN_TX1 D12
<29> LAN_TX1 LAN_TXD1
LAN_TX2 E13 AF25 H_IGNNE#
<29> LAN_TX2 LAN_TXD2 IGNNE# H_IGNNE# <7>
CPU
GLAN_DOCK# B10 AE22 H_INIT#
GPIO56 INIT# H_INIT# <7>
Close to U55 AG25 H_INTR +1.05V_VCCP
INTR H_INTR <7>
+1.5V_RUN_PCIE_ICH 1 2 B28 L3 SIO_RCIN#
GLAN_COMPI RCIN# SIO_RCIN# <38>
<27> ICH_AZ_CODEC_SDOUT 1 2 ICH_AZ_SDOUT 2 1 R232 B27 GLAN_COMPO
1
R234 33_0402_5%~D C300 R236 33_0402_5%~D 24.9_0402_1%~D AF23 H_NMI
NMI H_NMI <7>
<27> ICH_AZ_CODEC_SYNC 1 2 ICH_AZ_SYNC <33> ICH_AZ_MDC_BITCLK
27P_0402_50V8J~D 1 2 ICH_AZ_BITCLK AF6 HDA_BIT_CLK SMI# AF24 H_SMI#
H_SMI# <7>
R237
R235 33_0402_5%~D 1 2 ICH_AZ_SYNC AH4 56_0402_5%~D
<33> ICH_AZ_MDC_SYNC HDA_SYNC
<27> ICH_AZ_CODEC_RST# 1 2 ICH_AZ_RST# R238 33_0402_5%~D
STPCLK# AH27 H_STPCLK#
H_STPCLK# <7>
R239 33_0402_5%~D 1 2 ICH_AZ_RST# AE7
<33> ICH_AZ_MDC_RST#
2
HDA_RST#
<27> ICH_AZ_CODEC_BITCLK 1 2 ICH_AZ_BITCLK R240 33_0402_5%~D
THRMTRIP# AG26 THRMTRIP_ICH# 1 2
1 R241 33_0402_5%~D ICH_AZ_CODEC_SDIN0 AF4 C301
<27> ICH_AZ_CODEC_SDIN0 HDA_SDIN0
ICH_AZ_MDC_SDIN1 AG4 AG27 ICH_TP12 T41PAD~D 0.1U_0402_16V4Z~D
<33> ICH_AZ_MDC_SDIN1 HDA_SDIN1 TP12
C302 ICH_AZ_MCH_SDIN2
IHDA
<10> ICH_AZ_MCH_SDIN2 AH3 HDA_SDIN2
27P_0402_50V8J~D AE5
2 HDA_SDIN3
SATA4RXN AH11 ESATA_IRX_DTX_N4_C <33>
1 2 ICH_AZ_SDOUT AG5 AJ11
<33> ICH_AZ_MDC_SDOUT HDA_SDOUT SATA4RXP ESATA_IRX_DTX_P4_C <33>
R242 33_0402_5%~D AG12 ESATA_ITX_DRX_N4_C 2 1
SATA4TXN ESATA_ITX_DRX_N4 <33>
<37> ME_FWP ME_FWP AG7 AF12 ESATA_ITX_DRX_P4_C C303 2 1 0.01U_0402_16V7K~D
HDA_DOCK_EN#/GPIO33 SATA4TXP ESATA_ITX_DRX_P4 <33>
<10> ICH_AZ_MCH_SDOUT 1 2 ICH_AZ_SDOUT PAD~D T46 RTC_BAT_DET# AE8 HDA_DOCK_RST#/GPIO34
C304 0.01U_0402_16V7K~D
R243 33_0402_5%~D AH9
SATA5RXN SATA_SBRX_DTX_N3_C <35>
<10> ICH_AZ_MCH_SYNC 1 2 ICH_AZ_SYNC <42> SATA_ACT#_R
SATA_ACT#_R AG8 SATALED# SATA5RXP AJ9 SATA_SBRX_DTX_P3_C <35>
R244 33_0402_5%~D AE10 SATA_ITX_DRX_N3_C 2 1
SATA5TXN SATA_SBTX_C_DRX_N3 <35>
<10> ICH_AZ_MCH_RST# 1 2 ICH_AZ_RST# <26> PSATA_IRX_DTX_N0_C AJ16 SATA0RXN SATA5TXP AF10 SATA_ITX_DRX_P3_C C305 2 1 0.01U_0402_16V7K~D SATA_SBTX_C_DRX_P3 <35>
R245 33_0402_5%~D AH16 C306 0.01U_0402_16V7K~D
SATA
B <26> PSATA_IRX_DTX_P0_C SATA0RXP B
<10> ICH_AZ_MCH_BITCLK 1 2 ICH_AZ_BITCLK <26> PSATA_ITX_DRX_N0 2 1 PSATA_ITX_DRX_N0_C AF17 SATA0TXN SATA_CLKN AH18 CLK_PCIE_SATA#
CLK_PCIE_SATA# <6>
1 R246 33_0402_5%~D C307 2 1 0.01U_0402_16V7K~D PSATA_ITX_DRX_P0_C AG17 AJ18 CLK_PCIE_SATA
<26> PSATA_ITX_DRX_P0 SATA0TXP SATA_CLKP CLK_PCIE_SATA <6>
C308 0.01U_0402_16V7K~D
C309 AH13 AJ7
27P_0402_50V8J~D <26> SATA_ODD_IRX_DTX_N1_C SATA1RXN SATARBIAS#
<26> SATA_ODD_IRX_DTX_P1_C AJ13 SATA1RXP SATARBIAS AH7 2 1
2 SATA_ODD_ITX_DRX_N1_C AG14 R247 24.9_0402_1%~D
<26> SATA_ODD_ITX_DRX_N1 2 1 SATA1TXN
C310 2 1 0.01U_0402_16V7K~D SATA_ODD_ITX_DRX_P1_C AF14
<26> SATA_ODD_ITX_DRX_P1 SATA1TXP
C311 0.01U_0402_16V7K~D Within 500 mils
ICH9M REV 1.0
+3.3V_RUN
10K_0402_5%~D
1
XOR Chain Entrance Strap @

R84
@ R248
@R248
1K_0402_5%~D ICH_AZ_SYNC 2 1
ICH_RSVD_TP3 HDA SDOUT Description ICH_AZ_SDOUT 2 1
2
0 0 RSVD ICH_AZ_SDOUT R96 @

ICH_RSVD_TP3 <24>
10K_0402_5%~D
1
0 1 Enter XOR Chain

@ R249
@R249
1K_0402_5%~D For WLAN detection issue
A
1 0 Normal Operation (Default) A
Pin AH4 , AG5 has weak internal PD
2
1 1 Set PCIE port config bit 1
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ICH9-M(2/4)
LA-4041P
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
+3.3V_ALW_ICH +3.3V_RUN
1 2 IMVP_PWRGD
@ R251 2.2K_0402_5%~D 1 2 ICH_SMBCLK 1 2
1 2 MCH_ICH_SYNC# R252 2.2K_0402_5%~D U10C R256 8.2K_0402_5%~D
@ R254 10K_0402_5%~D 1 2 ICH_SMBDATA ICH_SMBCLK G16 SMBCLK SATA0GP/GPIO21 AH23
1 2 RSV_THRM# R255 2.2K_0402_5%~D ICH_SMBDATA A13 AF19 SPEAKER_DET# +3.3V_RUN
SMBDATA SATA1GP/GPIO19 SPEAKER_DET# <28>
R258 8.2K_0402_5%~D 1 2 ICH_CL_RST1# ICH_GPIO60 E17 AE21 USB_MCARD3_DET#
SATA
GPIO
LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36 USB_MCARD3_DET# <34>
SMB
2 1 IRQ_SERIRQ @R259
@ R259 10K_0402_5%~D
<38> AMT_SMBCLK
AMT_SMBCLK C17 SMLINK0 SATA5GP/GPIO37 AD20 1394_DET#
1394_DET# <31>
R261 10K_0402_5%~D 1 2 AMT_SMBCLK AMT_SMBDAT B18 1394_DET# 1 2
<38> AMT_SMBDAT SMLINK1
1 2 SPKR R262 10K_0402_5%~D
CLK14 H1 CLK_ICH_14M
CLK_ICH_14M <6>
R836 100K_0402_5%~D
@ R264 1K_0402_5%~D 1 2 AMT_SMBDAT ICH_RI# F19 AF3 CLK_ICH_48M ODD_DET# 2 1
Clocks
RI# CLK48 CLK_ICH_48M <6>
1 2 SPEAKER_DET# R265 10K_0402_5%~D R760 100K_0402_5%~D
R834 100K_0402_5%~D 1 2 ICH_RI# PAD~D T166 SUS_STAT#/LPCPD# R4 P1 ICH_SUSCLK T44 PAD~D HDD_DET# 1 2
SUS_STAT#/LPCPD# SUSCLK
1 2 SIO_EXT_SCI# R267 10K_0402_5%~D
<7> ITP_DBRESET#
ITP_DBRESET# G19 SYS_RESET#
R759 100K_0402_5%~D
D D
R272 10K_0402_5%~D 1 2 ICH_PCIE_WAKE# SLP_S3# C16 SIO_SLP_S3#
SIO_SLP_S3# <37>
2 1 TPM_ID R268 10K_0402_5%~D
<10> PM_SYNC#
PM_SYNC# M6 PMSYNC#/GPIO0 SLP_S4# E16 SIO_SLP_S4#
SIO_SLP_S4# <38>
R273 4@ 100K_0402_5%~D 2 1 ME_SUS_PWR_ACK SLP_S5# G17 SIO_SLP_S5#
SIO_SLP_S5# <38>
ICH_CL_PWROK 1 2
2 1 TPM_ID R269 10K_0402_5%~D SMB_ALERT# A17 SMBALERT#/GPIO11
R250 100K_0402_5%~D
R304 3@ 100K_0402_5%~D 1 2 SIO_EXT_SMI# C10 ICH_GPIO26 T130 PAD~D DPRSLPVR 1 2
R274 10K_0402_5%~D H_STP_PCI# S4_STATE#/GPIO26 @ R253 100K_0402_5%~D
<6> H_STP_PCI# A14 STP_PCI#
2 ICH_GPIO60 H_STP_CPU# ICH_PWRGD ICH_PWRGD
SYS GPIO
TPM_ID: 1
R787 10K_0402_5%~D <6> H_STP_CPU# E19 STP_CPU# PWROK G20 ICH_PWRGD <10,41> 1
R257
2
10K_0402_5%~D
H: Enable 1 2 SMB_ALERT# <31,37,38> CLKRUN# CLKRUN# L4 CLKRUN# DPRSLPVR/GPIO16 M2 DPRSLPVR
DPRSLPVR <10,47>
ICH_RSMRST# 1 2
R192 10K_0402_5%~D R260 10K_0402_5%~D
L: Disable 1 2 IO_LOOP ICH_PCIE_WAKE# E20 B13 ICH_BATLOW# 2 1 ME_WOL_EN 1 2
Power MGT
<37> ICH_PCIE_WAKE# WAKE# BATLOW# +3.3V_ALW_ICH
R835 100K_0402_5%~D 1 2 IRQ_SERIRQ_ICH M5 R275 8.2K_0402_5%~D R263 100K_0402_5%~D
<31,36,37,38> IRQ_SERIRQ SERIRQ
1 2 CONTACTLESS_DET# R122 RSV_THRM# AJ23 THRM# PWRBTN# R3 SIO_PWRBTN#
SIO_PWRBTN# <38>
R911 100K_0402_5%~D 33_0402_5%~D
iTPM function 1 @ 2 LAN_DISABLE# IMVP_PWRGD D21 D20 ICH_LAN_RST#
<37,41,47,49> IMVP_PWRGD VRMPWRGD LAN_RST# ICH_LAN_RST# <38>
R210 10K_0402_5%~D
No stuff = Disable PAD~D T45 ICH_TP11 A20 D22 ICH_RSMRST#
TP11 RSMRST# ICH_RSMRST# <38>
R270
Stuff = Enable SIO_EXT_SCI# AG19 R5 CLK_PWRGD
<38> SIO_EXT_SCI# GPIO1 CK_PWRGD CLK_PWRGD <6>
TPM_ID AH21 Place closely pin U10.H1
+3.3V_LAN GPIO6 ICH_CL_PWROK +3.3V_ALW_ICH
<37> SIO_EXT_WAKE# 1 2 AG21 GPIO7 CLPWROK R6 ICH_CL_PWROK <10,38>
R277 0_0402_5%~D SIO_EXT_SMI# A21 CLK_ICH_14M
<38> SIO_EXT_SMI# GPIO8
10K_0402_5%~D
1 2 ICH_EC_SPI_DO <29> LAN_DISABLE#
LAN_DISABLE# C12 GPIO12 SLP_M# B16 SIO_SLP_M#
SIO_SLP_M# <38>
1
@ R270 1K_0402_5%~D CONTACTLESS_DET# C21
<36> CONTACTLESS_DET# GPIO13
R271
PAD~D T47 ICH_GPIO17 AE18 F24
+3.3V_RUN GPIO17 CL_CLK0 CL_CLK0 <10>
1 2 K1 B19 @ @ R279
<34> USB_MCARD1_DET# GPIO18 CL_CLK1 ICH_CL_CLK1 <34>
R280 0_0402_5%~D ICH_GPIO20 AF8 10_0402_5%~D
PAD~D T132 GPIO20
<34> USB_MCARD2_DET# 1 2 AJ22 F22 CL_DATA0 <10>
2
SCLOCK/GPIO22 CL_DATA0
1
R281 0_0402_5%~D A9 C19 ICH_LAN_RST#

<31> SD_DET# ICH_CL_DATA1 <34>
GPIO
Controller Link
GPIO27 CL_DATA1
47P_0402_50V8J~D
47P_0402_50V8J~D
47P_0402_50V8J~D
R282 IO_LOOP D19 1

<33> IO_LOOP GPIO28
2
10K_0402_5%~D
8.2K_0402_5%~D No Reboot Strap 1 1 1 SATA_CLKREQ# L1 C25 +CL_VREF0_ICH
<6> SATA_CLKREQ# SATACLKREQ#/GPIO35 CL_VREF0
@ C313
@ C315
@ C316
ODD_DET# AE19 A19 +CL_VREF1_ICH @ C312

<26,38> ODD_DET# SLOAD/GPIO38 CL_VREF1
R276
C Low = Default WPAN_RADIO_DIS_MINI# AG22 4.7P_0402_50V8C~D C
PAD~D T48
2
SPKR HDD_DET# SDATAOUT0/GPIO39 CL_RST0# 2

<26> HDD_DET# AF21 SDATAOUT1/GPIO48 CL_RST0# F21 CL_RST0# <10>
CLKRUN# High = No Reboot 2 2 2 ICH_GPIO49 ICH_CL_RST1#
PAD~D T167 AH24 D18
1
GPIO49 CL_RST1# ICH_CL_RST1# <34>
A8 GPIO57/CLGPIO5
MEM_LED/GPIO24 A16 PCIE_MCARD1_DET# <34>
1
Option to " Disable " SPKR M7 C18 ME_SUS_PWR_ACK

<27> SPKR SPKR GPIO10/SUS_PWR_ACK ME_SUS_PWR_ACK <38>
@ R283 MCH_ICH_SYNC# AJ24 C11 AC_PRESENT Place closely pin U10.AF3
clkrun. Pulling it <10> MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT AC_PRESENT <38>
10_0402_5%~D ICH_RSVD_TP3 B21 C20 ME_WOL_EN
<23> ICH_RSVD_TP3 TP3 WOL_EN/GPIO9 ME_WOL_EN <38>
2 ITP_DBRESET# ICH_TP8 CLK_ICH_48M
MISC
down 1 PAD~D T50 AH20 TP8
@ R811 100K_0402_5%~D PAD~D T51 ICH_TP9 AJ20 1 2 +3.3V_ALW_ICH
will keep the clks
2
TP9
1
PAD~D T52 ICH_TP10 AJ21 @ R284
TP10
running. 10K_0402_5%~D
ICH9M REV 1.0 R285
10_0402_5%~D
2
U10D
PCIE_IRX_WANTX_N1 N29 V27 DMI_MTX_IRX_N0 1
<34> PCIE_IRX_WANTX_N1 PERN1 DMI0RXN DMI_MTX_IRX_N0 <10>
PCIE_IRX_WANTX_P1 N28 V26 DMI_MTX_IRX_P0
<34> PCIE_IRX_WANTX_P1 PERP1 DMI0RXP DMI_MTX_IRX_P0 <10>
Direct Media Interface

MiniWWAN (Mini Card 1)---> C317 1 2 0.1U_0402_10V7K~D PCIE_ITX_WANRX_N1 P27 U29 DMI_MRX_ITX_N0 C318
<34> PCIE_ITX_WANRX_N1_C PETN1 DMI0TXN DMI_MRX_ITX_N0 <10> 8.2P_0402_50V8D~D
C319 1 2 0.1U_0402_10V7K~D PCIE_ITX_WANRX_P1 P26 U28 DMI_MRX_ITX_P0
<34> PCIE_ITX_WANRX_P1_C PETP1 DMI0TXP DMI_MRX_ITX_P0 <10> 2
PCIE_IRX_WLANTX_N2 L29 Y27 DMI_MTX_IRX_N1
<34> PCIE_IRX_WLANTX_N2 PERN2 DMI1RXN DMI_MTX_IRX_N1 <10>
PCIE_IRX_WLANTX_P2 L28 Y26 DMI_MTX_IRX_P1
<34> PCIE_IRX_WLANTX_P2 PERP2 DMI1RXP DMI_MTX_IRX_P1 <10>
MiniWLAN (Mini Card 2)---> C320 1 2 0.1U_0402_10V7K~D PCIE_ITX_WLANRX_N2 M27 W29 DMI_MRX_ITX_N1
+3.3V_ALW_ICH <34> PCIE_ITX_WLANRX_N2_C PETN2 DMI1TXN DMI_MRX_ITX_N1 <10>
C321 1 2 0.1U_0402_10V7K~D PCIE_ITX_WLANRX_P2 M26 W28 DMI_MRX_ITX_P1
<34> PCIE_ITX_WLANRX_P2_C PETP2 DMI1TXP DMI_MRX_ITX_P1 <10>
RP1
5 4 USB_OC0_1# PCIE_IRX_MCARDTX_N3 J29 AB27 DMI_MTX_IRX_N2 +3.3V_WLAN +3.3V_M
<34> PCIE_IRX_MCARDTX_N3 PERN3 DMI2RXN DMI_MTX_IRX_N2 <10>
3.24K_0402_1%~D
3.24K_0402_1%~D
6 3 USB_OC2# PCIE_IRX_MCARDTX_P3 J28 AB26 DMI_MTX_IRX_P2
<34> PCIE_IRX_MCARDTX_P3 PERP3 DMI2RXP DMI_MTX_IRX_P2 <10>
PCI-Express
7 2 ESATA_USB_OC# BT/UWB---> C322 1 2 0.1U_0402_10V7K~D PCIE_ITX_MCARDRX_N3 K27 AA29 DMI_MRX_ITX_N2
<34> PCIE_ITX_MCARDRX_N3_C PETN3 DMI2TXN DMI_MRX_ITX_N2 <10>
1
8 1 USB_OC4# C323 1 2 0.1U_0402_10V7K~D PCIE_ITX_MCARDRX_P3 K26 AA28 DMI_MRX_ITX_P2
<34> PCIE_ITX_MCARDRX_P3_C PETP3 DMI2TXP DMI_MRX_ITX_P2 <10>
R286
R287
10K_1206_8P4R_5%~D PCIE_IRX_EXPTX_N4 G29 AD27 DMI_MTX_IRX_N3
B <32> PCIE_IRX_EXPTX_N4 PERN4 DMI3RXN DMI_MTX_IRX_N3 <10> B
RP2 PCIE_IRX_EXPTX_P4 G28 AD26 DMI_MTX_IRX_P3
<32> PCIE_IRX_EXPTX_P4 PERP4 DMI3RXP DMI_MTX_IRX_P3 <10>
5 4 USB_OC5# Express card---> C98 1 2 0.1U_0402_10V7K~D PCIE_ITX_EXPRX_N4 H27 AC29 DMI_MRX_ITX_N3
DMI_MRX_ITX_N3 <10>
2
USB_OC6# <32> PCIE_ITX_EXPRX_N4_C C99 PETN4 DMI3TXN
6 3 <32> PCIE_ITX_EXPRX_P4_C 1 2 0.1U_0402_10V7K~D PCIE_ITX_EXPRX_P4 H26 PETP4 DMI3TXP AC28 DMI_MRX_ITX_P3
DMI_MRX_ITX_P3 <10>
+CL_VREF1_ICH +CL_VREF0_ICH
7 2 USB_OC7#
453_0402_1%~D
453_0402_1%~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
8 1 USB_OC11# E29 T26 CLK_PCIE_ICH#
PERN5 DMI_CLKN CLK_PCIE_ICH# <6>
1
E28 T25 CLK_PCIE_ICH 1 1
PERP5 DMI_CLKP CLK_PCIE_ICH <6>
R289
R290
10K_1206_8P4R_5%~D F27 Within 500 mils
PETN5
C324
C325
1 2 USB_OC9# F26 AF29
R288 10K_0402_5%~D PETP5 DMI_ZCOMP DMI_IRCOMP
DMI_IRCOMP AF28 1 2 +1.5V_RUN_PCIE_ICH
USB_OC10# PCIE_IRX_GLANTX_N6 R292 24.9_0402_1%~D 2 2
1 2 <29> PCIE_IRX_GLANTX_N6 C29
2
R291 10K_0402_5%~D PCIE_IRX_GLANTX_P6 PERN6/GLAN_RXN USBP0-
1 2 USB_OC8#
<29> PCIE_IRX_GLANTX_P6
C326 1 2 0.1U_0402_10V7K~D PCIE_ITX_GLANRX_N6
C28
D27
PERP6/GLAN_RXP USBP0N AC5
AC4 USBP0+
USBP0- <33> ----->Right Side Top
<29> PCIE_ITX_GLANRX_N6_C PETN6/GLAN_TXN USBP0P USBP0+ <33>
R293 10K_0402_5%~D 10/100/1G LAN ---> C327 1 2 0.1U_0402_10V7K~D PCIE_ITX_GLANRX_P6 USBP1-
<29> PCIE_ITX_GLANRX_P6_C R294
D26 PETP6/GLAN_TXP USBP1N AD3
AD2 USBP1+
USBP1- <33> ----->Right Side Bottom
USBP1P USBP1+ <33>
33_0402_5%~D ICH_EC_SPI_CLK USBP2-
D23 SPI_CLK USBP2N AC1 USBP2- <33> ----->Left Side Top +3.3V_M
2.2K_0402_5%~D
2.2K_0402_5%~D
ICH_SPI_CS0# 1 2 ICH_SPI_CS0#_R D24 AC2 USBP2+
200 MIL SO8 SPI_CS0# USBP2P USBP2+ <33>
1
ICH_SPI_CS1#_R USBP3-
+3.3V_LAN <22> ICH_SPI_CS1# 1
33_0402_5%~D
2 F23 SPI_CS1#/GPIO58/CLGPIO6 USBP3N AA5
USBP3+
USBP3- <33> ----->Left Side Bottom
Flash ROM USBP3P AA4 USBP3+ <33>
R296
R297
C328 R387 ICH_EC_SPI_DO USBP4-
1 2 ICH_EC_SPI_DIN
D25
E23
SPI_MOSI USBP4N
SPI AB2
AB3 USBP4+
USBP4- <34> ----->WLAN
<33> USB_OC0_1# SPI_MISO USBP4P USBP4+ <34>
1
R1045 USBP5-
AA1 USBP5- <34> ----->WWAN
2
USBP5N
1
R298 0.1U_0402_16V4Z~D 0_0402_5%~D USB_OC0_1# N4 AA2 USBP5+

OC0#/GPIO59 USBP5P USBP5+ <34>
3.3K_0402_5%~D R299 USB_OC1# USBP6-
3.3K_0402_5%~D
1 2
USB_OC2#
N5 OC1#/GPIO40 USBP6N W5
USBP6+
USBP6- <34> ----->WPAN ICH_SMBDATA 6 1 MEM_SDATA
MEM_SDATA <16,17>
U12
<33> USB_OC2#
ESATA_USB_OC#
N6 OC2#/GPIO41 USB USBP6P W4
USBP7-
USBP6+ <34>
Q27A
<33> ESATA_USB_OC# P6 Y3 USBP7- <32> ----->EXP Card
2
ICH_SPI_CS0# R301 USB_OC4# OC3#/GPIO42 USBP7N USBP7+ 2N7002DW-T/R7_SOT363-6~D

1 8 M1 Y2 USBP7+ <32>
2
2
ICH_EC_SPI_DIN 1 CS# VCC OC4#/GPIO43 USBP7P
2SPI_DIN_R1 2 SO HOLD# 7 33_0402_5%~D USB_OC5# N2 OC5#/GPIO29 USBP8N W1 USBP8-
USBP8- <35> ----->DOCK +3.3V_M
R300 3 6 SPI_CLK_R1 1 2 ICH_EC_SPI_CLK USB_OC6# M4 W2 USBP8+
WP# SCLK OC6#/GPIO30 USBP8P USBP8+ <35>
5
33_0402_5%~D SPI_DO_R11 ICH_EC_SPI_DO USB_OC7# USBP9-
4 GND SI 5
R302
2
33_0402_5%~D USB_OC8#
M3
N3
OC7#/GPIO31 USBP9N V2
V3 USBP9+
USBP9- <35> ----->DOCK
OC8#/GPIO44 USBP9P USBP9+ <35>
R1049 W25X32VSSIG_SO8~D USB_OC9# USBP10- ICH_SMBCLK 3 MEM_SCLK
0_0402_5%~D USB_OC10#
N1
P5
OC9#/GPIO45 USBP10N U5
U4 USBP10+
USBP10- <36> ----->USH 4
Q27B
MEM_SCLK <16,17>
A OC10#/GPIO46 USBP10P USBP10+ <36> A
+3.3V_LAN USB_OC11# USBP11- 2N7002DW-T/R7_SOT363-6~D
1 2
@ C392
P3 OC11#/GPIO47 USBP11N U1
U2 USBP11+
USBP11- <19> ----->Camera
USBP11P USBP11+ <19>
1 2 2 1 USBRBIAS AG2
R303 USBRBIAS
SPI_WP#_SEL <37> AG1 USBRBIAS#
1
0.1U_0402_16V4Z~D 22.6_0402_1%~D
@ R375
3.3K_0402_5%~D
@R383
3.3K_0402_5%~D
Within 500 mils ICH9M REV 1.0 DELL CONFIDENTIAL/PROPRIETARY
@ R385
@R385
33_0402_5%~D @ U13 Compal Electronics, Inc.
2
ICH_SPI_CS1# 1 8 R329 @ ICH_EC_SPI_DIN 1 2 ICH_SPI_DIN_R PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
ICH_SPI_DIN_R 1 CS# VCC TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
2SPI_DIN_R2 2 SO HOLD# 7 33_0402_5%~D @ R386 0_0402_5%~D
ICH9-M(3/4)
3 6 SPI_CLK_R2 1 2 ICH_EC_SPI_CLK Follow Daisy Chain and Star BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
@ R1060 WP# SCLK SPI_DO_R2 ICH_EC_SPI_DO NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
4 GND SI 5 1 2 Topology. Place close to U10
0_0402_5%~D @ R384 PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
SPI_WP#_SEL 1 2 W25X16VSSIG_SO8~D 33_0402_5%~D
pinE23 within 500mils LA-4041P
5 4 3 2 1
5 4 3 2 1
+RTC_CELL
U10E
+1.05V_VCCP AA26 H5
D14 VSS[1] VSS[107]
1U_0603_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
AA27 VSS[2] VSS[108] J23
1 1 1 AA3 VSS[3] VSS[109] J26
+5V_RUN +3.3V_RUN +1.5V_RUN
2 AA6 VSS[4] VSS[110] J27
C330
C331
C332
+1.05V_VCCP R310 AB1 AC22
VSS[5] VSS[111]
1 1 2 AA23 VSS[6] VSS[112] K28
1
2
2 2 2 U10F AB28 VSS[7] VSS[113] K29
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
R311 D15 A23 A15 3 10_0805_5%~D AB29 L13
100_0402_5%~D VCCRTC VCC1_05[1] VSS[8] VSS[114]
RB751S40T1_SOD523-2~D VCC1_05[2] B15 AB4 VSS[9] VSS[115] L15
ICH_V5REF_RUN A6 C15 AB5 L2
V5REF VCC1_05[3] VSS[10] VSS[116]
D15 1 1 AC17 L26
2
1 VCC1_05[4] MMBD4148-7-F_SOT23-3~D VSS[11] VSS[117]

ICH_V5REF_RUN +1.5V_RUN +1.5V_RUN_PCIE_ICH ICH_V5REF_SUS AE1 V5REF_SUS VCC1_05[5] E15 AC26 VSS[12] VSS[118] L27
C333
C334
1 L13 F15 AC27 L5
+1.5V_RUN_PCIE_ICH VCC1_05[6] VSS[13] VSS[119]
D 1 2 AA24 VCC1_5_B[1] VCC1_05[7] L11 AC3 VSS[14] VSS[120] L7 D
C335 BLM21PG600SN1D_0805~D AA25 L12 2 2 AD1 M12
VCC1_5_B[2] VCC1_05[8] VSS[15] VSS[121]
220U_D2_4VY_R15M~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
2.2U_0603_6.3V6K~D
1U_0603_10V6K~D AB24 L14 AD10 M13
2 VCC1_5_B[3] VCC1_05[9] VSS[16] VSS[122]
1 AB25 VCC1_5_B[4] VCC1_05[10] L16 AD12 VSS[17] VSS[123] M14
AC24 L17 L14 +1.5V_RUN AD13 M15
1 1 1 VCC1_5_B[5] VCC1_05[11] VSS[18] VSS[124]
+ AC25 L18 BLM18PG181SN1_0603~D AD14 M16
VCC1_5_B[6] VCC1_05[12] VSS[19] VSS[125]
C336
C337
C338
C339
AD24 VCC1_5_B[7] VCC1_05[13] M11 1 2 2 1 AD17 VSS[20] VSS[126] M17
0.01U_0402_16V7K~D
10U_0805_4VAM~D
AD25 M18 R312 AD18 M23
2 2 2 2 VCC1_5_B[8] VCC1_05[14] 1_0603_1%~D VSS[21] VSS[127]
AE25 VCC1_5_B[9] VCC1_05[15] P11 1 1 AD21 VSS[22] VSS[128] M28
AE26 VCC1_5_B[10] VCC1_05[16] P18 AD28 VSS[23] VSS[129] M29
+5V_ALW +3.3V_ALW_ICH
C340
C341
AE27 VCC1_5_B[11] VCC1_05[17] T11 AD29 VSS[24] VSS[130] N11
AE28 VCC1_5_B[12] VCC1_05[18] T18 AD4 VSS[25] VSS[131] N12
2 2
AE29 VCC1_5_B[13] U11 AD5 N13
CORE
VCC1_05[19] VSS[26] VSS[132]
1
F25 VCC1_5_B[14] VCC1_05[20] U18 AD6 VSS[27] VSS[133] N14

R313 D16 G25 V11 AD7 N15
100_0402_5%~D VCC1_5_B[15] VCC1_05[21] 5ohm@100MHz VSS[28] VSS[134]
RB751S40T1_SOD523-2~D H24 VCC1_5_B[16] VCC1_05[22] V12 AD9 VSS[29] VSS[135] N16
H25 VCC1_5_B[17] VCC1_05[23] V14 1 2 +1.05V_VCCP AE12 VSS[30] VSS[136] N17
+1.05V_VCCP
4.7U_0603_6.3V6M~D
J24 V16 L15 AE13 N18
2
ICH_V5REF_SUS VCC1_5_B[18] VCC1_05[24] BLM18PG181SN1_0603~D VSS[31] VSS[137]

J25 VCC1_5_B[19] VCC1_05[25] V17 AE14 VSS[32] VSS[138] N26
1 K24 VCC1_5_B[20] VCC1_05[26] V18 1 AE16 VSS[33] VSS[139] N27
4.7U_0603_6.3V6M~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
K25 VCC1_5_B[21] AE17 VSS[34] VSS[140] P12
C343
C342 L23 R29 +VCCDMIPLL AE2 P13
1U_0603_10V6K~D VCC1_5_B[22] VCCDMIPLL VSS[35] VSS[141]
L24 VCC1_5_B[23] 1 1 1 AE20 VSS[36] VSS[142] P14
2 +VCC_DMI_ICH 2
L25 VCC1_5_B[24] VCC_DMI[1] W23 AE24 VSS[37] VSS[143] P15
C344
C345
C346
M24 VCC1_5_B[25] VCC_DMI[2] Y23 AE3 VSS[38] VSS[144] P16
M25 VCC1_5_B[26] AE4 VSS[39] VSS[145] P17
N23 AB23 2 2 2 AE6 P2
VCC1_5_B[27] V_CPU_IO[1] +3.3V_RUN VSS[40] VSS[146]
N24 VCC1_5_B[28] V_CPU_IO[2] AC23 AE9 VSS[41] VSS[147] P23
N25 VCC1_5_B[29] AF13 VSS[42] VSS[148] P28
P24 VCC1_5_B[30] VCC3_3[1] AG29 AF16 VSS[43] VSS[149] P29
0.1U_0402_16V4Z~D
P25 VCC1_5_B[31] AF18 VSS[44] VSS[150] P4
+1.5V_RUN
VCCA3GP
R24 VCC1_5_B[32] VCC3_3[2] AJ6 +3.3V_RUN AF22 VSS[45] VSS[151] P7
+1.5V_RUN_SATAPLL
0.1U_0402_16V4Z~D
L16 R25 1 AH26 R11
10UH_LB2012T100MR_20%_0805~D VCC1_5_B[33] VSS[46] VSS[152]
R26 VCC1_5_B[34] VCC3_3[7] AC10 +3.3V_RUN 1 AF26 VSS[47] VSS[153] R12
C347
C
1 2 R27 VCC1_5_B[35] AF27 VSS[48] VSS[154] R13 C
+3.3V/1.5V_RUN_HDA
C348
T24 VCC1_5_B[36] VCC3_3[3] AD19 AF5 VSS[49] VSS[155] R14
2
10U_0805_4VAM~D
1U_0603_10V4Z~D
T27 AF20 C349 AF7 R15
VCCP_CORE
VCC1_5_B[37] VCC3_3[4] 0.1U_0402_16V4Z~D 2 VSS[50] VSS[156]
1 1 T28 VCC1_5_B[38] VCC3_3[5] AG24 2 1 +3.3V_RUN AF9 VSS[51] VSS[157] R16
T29 AC20 1 2 R314 AG13 R17
VCC1_5_B[39] VCC3_3[6] VSS[52] VSS[158]
C350
C351
U24 0_0603_5%~D AG16 R18

VCC1_5_B[40] VSS[53] VSS[159]
U25 VCC1_5_B[41] VCC3_3[8] B9 +3.3V_RUN 2 1 +1.5V_RUN AG18 VSS[54] VSS[160] R28
2 2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
V24 F9 @R315
@ R315 AG20 T12
VCC1_5_B[42] VCC3_3[9] 0_0603_5%~D VSS[55] VSS[161]
V25 VCC1_5_B[43] VCC3_3[10] G3 1 AG23 VSS[56] VSS[162] T13
U23 G6 1 1 1 Choice to support GMCH AG3 T14
VCC1_5_B[44] VCC3_3[11] C352 VSS[57] VSS[163]
W24 VCC1_5_B[45] VCC3_3[12] J2 AG6 VSS[58] VSS[164] T15
C353
C354
C355
0.1U_0402_16V4Z~D
PCI
W25 VCC1_5_B[46] VCC3_3[13] J7 AG9 VSS[59] VSS[165] T16
K23 K7 2 AH12 T17
VCC1_5_B[47] VCC3_3[14] 2 2 2 VSS[60] VSS[166]
Y24 VCC1_5_B[48] AH14 VSS[61] VSS[167] T23
Y25 AJ4 +3.3V_ALW_ICH AH17 B26
VCC1_5_B[49] VCCHDA +3.3V/1.5V_RUN_HDA VSS[62] VSS[168]
AH19 VSS[63] VSS[169] U12
AJ19 VCCSATAPLL VCCSUSHDA AJ3 AH2 VSS[64] VSS[170] U13
AH22 VSS[65] VSS[171] U14
AC16 AC8 TP_VCCSUS1.05_INT_ICH1 T53 PAD~D AH25 U15
VCC1_5_A[1] VCCSUS1_05[1] VSS[66] VSS[172]
1U_0603_10V4Z~D
AD15 VCC1_5_A[2] VCCSUS1_05[2] F17 2 AH28 VSS[67] VSS[173] U16

1 AD16 TP_VCCSUS1.05_INT_ICH2 T122 PAD~D AH5 U17
VCC1_5_A[3] VSS[68] VSS[174]
ARX
AE15 AD8 VCCSUS1_5_ICH_1 C357 AH8 AD23
VCC1_5_A[4] VCCSUS1_5[1] T91 VSS[69] VSS[175]
C358
AF15 VCC1_5_A[5] 0.1U_0402_16V4Z~D AJ12 VSS[70] VSS[176] U26

VCCSUS1_5_ICH_2 1
AG15 VCC1_5_A[6] VCCSUS1_5[2] F18 AJ14 VSS[71] VSS[177] U27
2
AH15 VCC1_5_A[7] AJ17 VSS[72] VSS[178] U3
AJ15 VCC1_5_A[8] AJ8 VSS[73] VSS[179] V1
A18 B11 V13
VCCPSUS
VCCSUS3_3[1] +3.3V_ALW_ICH VSS[74] VSS[180]
AC11 D16 VCCSUS1_5_ICH_2 B14 V15
VCC1_5_A[9] VCCSUS3_3[2] VSS[75] VSS[181]
1U_0603_10V4Z~D
AD11 VCC1_5_A[10] VCCSUS3_3[3] D17 B17 VSS[76] VSS[182] V23

1 AE11 VCC1_5_A[11] VCCSUS3_3[4] E22 1 B2 VSS[77] VSS[183] V28
ATX
AF11 VCC1_5_A[12] B20 VSS[78] VSS[184] V29

C359
AG10 C360 B23 V4

VCC1_5_A[13] +3.3V_ALW_ICH VSS[79] VSS[185]
AG11 VCC1_5_A[14] VCCSUS3_3[5] AF1 0.1U_0402_16V4Z~D B5 VSS[80] VSS[186] V5
2 2
AH10 VCC1_5_A[15] B8 VSS[81] VSS[187] W26
AJ10 VCC1_5_A[16] VCCSUS3_3[6] T1 C26 VSS[82] VSS[188] W27
B
VCCSUS3_3[7] T2 C27 VSS[83] VSS[189] W3 B
0.022U_0402_16V7K~D
0.022U_0402_16V7K~D
0.1U_0402_16V4Z~D
AC9 VCC1_5_A[17] VCCSUS3_3[8] T3 E11 VSS[84] VSS[190] Y1
VCCSUS3_3[9] T4 E14 VSS[85] VSS[191] Y28
AC18 VCC1_5_A[18] VCCSUS3_3[10] T5 1 1 1 E18 VSS[86] VSS[192] Y29
0.1U_0402_16V4Z~D
AC19 VCC1_5_A[19] VCCSUS3_3[11] T6 E2 VSS[87] VSS[193] Y4
C361
C362
C363
U6 E21 Y5
VCCPUSB
VCCSUS3_3[12] VSS[88] VSS[194]

1 AC21 VCC1_5_A[20] VCCSUS3_3[13] U7 E24 VSS[89] VSS[195] AG28
V6 2 2 2 E5 AH6
VCCSUS3_3[14] VSS[90] VSS[196]
C364
G10 VCC1_5_A[21] VCCSUS3_3[15] V7 E8 VSS[91] VSS[197] AF2

G9 VCC1_5_A[22] VCCSUS3_3[16] W6 F16 VSS[92] VSS[198] B25
2
0.1U_0402_16V4Z~D
VCCSUS3_3[17] W7 F28 VSS[93]

AC12 VCC1_5_A[23] VCCSUS3_3[18] Y6 F29 VSS[94] VSS_NCTF[1] A1
1 AC13 VCC1_5_A[24] VCCSUS3_3[19] Y7 G12 VSS[95] VSS_NCTF[2] A2
AC14 VCC1_5_A[25] VCCSUS3_3[20] T7 G14 VSS[96] VSS_NCTF[3] A28
C365
G18 VSS[97] VSS_NCTF[4] A29

AJ5 G22 VCCCL1_05_ICH 1 2 G21 AH1
2 VCCUSBPLL VCCCL1_05 C366 0.1U_0402_16V4Z~D VSS[98] VSS_NCTF[5]
+3.3V_LAN G24 VSS[99] VSS_NCTF[6] AH29
0.1U_0402_16V4Z~D
AA7 G23 VCCCL1_5 G26 AJ1

VCC1_5_A[26] VCCCL1_5 VSS[100] VSS_NCTF[7]
USB CORE
AB6 VCC1_5_A[27] G27 VSS[101] VSS_NCTF[8] AJ2
1U_0603_10V4Z~D
0.1U_0402_16V4Z~D
1 AB7 VCC1_5_A[28] VCCCL3_3[1] A24 +3.3V_LAN G8 VSS[102] VSS_NCTF[9] AJ28
AC6 VCC1_5_A[29] VCCCL3_3[2] B24 1 1 H2 VSS[103] VSS_NCTF[10] AJ29
C367
AC7 VCC1_5_A[30] H23 VSS[104] VSS_NCTF[11] B1
C368
C369
H28 VSS[105] VSS_NCTF[12] B29
2 VCCLAN1.05_INT_ICH
1 2 A10 VCCLAN1_05[1] H29 VSS[106]
C370 2 2
A11 VCCLAN1_05[2]
0.1U_0402_16V4Z~D ICH9M REV 1.0
A12 VCCLAN3_3[1]
B12 VCCLAN3_3[2]
A27 VCCGLANPLL
+1.5V_RUN +VCCGLANPLL
+1.5V_RUN
GLAN POWER
D28 VCCGLAN1_5[1]
1 2 D29 VCCGLAN1_5[2]
2.2U_0603_6.3V6K~D
L17 E26 VCCGLAN1_5[3]

10U_0805_4VAM~D
4.7U_0603_6.3V6M~D
1UH_20%_0805~D E27
A VCCGLAN1_5[4] A
1 1
1 +3.3V_RUN A26 VCCGLAN3_3
C371
C372
C373
ICH9M REV 1.0

2 2
2
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ICH9-M(4/4)
LA-4041P
5 4 3 2 1
5 4 3 2 1
D D
For ODD +5VMOD Source

+15V_ALW +5V_ALW
JSATA1
1
1 +3.3V_ALW2
+5V_MOD SATA_ODD_ITX_DRX_P1 GND R316
<23> SATA_ODD_ITX_DRX_P1 2 RX+
SATA_ODD_ITX_DRX_N1 3 100K_0402_5%~D
<23> SATA_ODD_ITX_DRX_N1 RX-
1
2
5
6
4 GND
1000P_0402_50V7K~D
0.1U_0402_16V4Z~D
2 1 SATA_ODD_IRX_DTX_N1 5 R317 D Q29
2
<23> SATA_ODD_IRX_DTX_N1_C C374 0.01U_0402_16V7K~D TX- 100K_0402_5%~D G SI3456BDV-T1-E3_TSOP6~D
1 1 6 TX+
2 1 SATA_ODD_IRX_DTX_P1 7 2 MOD_EN 3
<23> SATA_ODD_IRX_DTX_P1_C GND
C376
C377
C375 0.01U_0402_16V7K~D S
3
2N7002DW-T/R7_SOT363-6
ODD_DET# 8 +5V_MOD +5V_RUN
4
2 2 <24,38> ODD_DET# DP
0.1U_0603_50V4Z~D
close SATA connector +5V_MOD 9 PJP53
+5V
Q31B
10 +5V 1 2
10U_0805_10V4Z~D
100K_0402_5%~D
11 MD 5 1
1
12 14 1 @ PAD-OPEN 4x4m
GND GND1
6
2N7002DW-T/R7_SOT363-6
C378
13 15
4
GND GND2
C379
R318
2
Q31A
TYCO_1759920-3
2
<37> MODC_EN 2
2
Pleace near ODD CONN
1
Main SATA +5V Default R319
100K_0402_5%~D
2
C C
HDD PWR
+5V_ALW
+15V_ALW
+3.3V_ALW2
1
R320
For HDD
1
2
5
6
100K_0402_5%~D
1
D Q32
JSATA2 G SI3456BDV-T1-E3_TSOP6~D
2
1 R321 HDD_EN_5V 3
PSATA_ITX_DRX_P0 GND 100K_0402_5%~D S
<23> PSATA_ITX_DRX_P0 2 RX+
PSATA_ITX_DRX_N0 3 +5V_HDD +5V_RUN
<23> PSATA_ITX_DRX_N0
4
RX-
3
2N7002DW-T/R7_SOT363-6
4 PJP54
GND
0.1U_0603_50V4Z~D
C380 2 1 0.01U_0402_16V7K~D PSATA_IRX_DTX_N0 5 1 2
<23> PSATA_IRX_DTX_N0_C TX-
Q34B
10U_0805_10V4Z~D
C381 2 1 0.01U_0402_16V7K~D PSATA_IRX_DTX_P0 6
<23> PSATA_IRX_DTX_P0_C TX+
100K_0402_5%~D
7 5 1 1 @ PAD-OPEN 4x4m
GND
1
Open
6
2N7002DW-T/R7_SOT363-6
C382
C383
R322
+3.3V_HDD 8
4
3.3V
close SATA connector 9 3.3V 2 2
Q34A
10 3.3V
11 <37> HDDC_EN 2
2
HDD_DET# GND
<24> HDD_DET# 12 GND
13
1
GND
1
+5V_HDD +3.3V_HDD +5V_HDD 14 5V R323
15
16
5V
5V
100K_0402_5%~D +5V_HDD Source
1000P_0402_50V7K~D
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_10V7K~D
B 17 GND B
18 23
2
Reserved GND1 +3.3V_ALW
1 1 1 1 1 19 GND GND2 24
@ C386
@ C387
@ C388
20 12V
C384
C385
21 12V
22 12V
2 2 2 2 2
FOX_LD2122H-S4SL6_RV
1
2
5
6
Main SATA +5V Default D @ Q124
G SI3456BDV-T1-E3_TSOP6~D
3
Pleace near HDD CONN S
+3.3V_HDD +3.3V_RUN
4
PJP55
1 2
10U_0805_10V4Z~D
@ C1012
100K_0402_5%~D
@ R924
1 @ PAD-OPEN 4x4m
1
Short
2
2
+3.3V_HDD Source
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT ODD/HDD CONNECTOR
5 4 3 2 1
2 1
+3.3V_RUN
1 2 XTALO_12MHZ L18 BLM18EG601SN1D_2P~D

R786 0_0402_5%~D
2 1+3.3V_RUN_I2S_VDD
0.1U_0402_16V7K~D
4.7U_0603_6.3V4Z~D
0.1U_0402_16V7K~D
Y5 +3.3V_RUN 47UH_CBMF1608T470K_10%~D
1 2 XTALI_12MHZ 2 1 2
27P_0402_50V8J~D
1 2 1 2 2 1 +3.3V_RUN_I2S_AVDD
<24> SPKR
27P_0402_50V8J~D
0.1U_0402_16V7K~D
4.7U_0603_6.3V4Z~D
0.1U_0402_16V7K~D
C481
C391
C393
C389 0.1U_0402_16V4Z~D R327 499K_0402_1%~D L35
1 2 1 2 AUD_PC_BEEP 2 12MHZ_18PF_1Y712000CE1J~D 2
<38> BEEP 1 2 1
C394 0.1U_0402_16V4Z~D R828 499K_0402_1%~D TRACE>15 mil 2 1 2 @
C994
C995
C398
C395
C396
R328 U15
@ 10K_0402_5%~D 1 1
1 2 1 SSM2602
3 4
2
AGND DCVDD DVSS
18 AVDD AVSS 19
AGND 12 15 AGND
HPVDD HPVSS
5 DBVDD
+VDDA C79 1000P_0402_50V7K~D
AGND 1 2 AUD_DOCK_HP_L_R 24 16 AUD_DOCK_MIC_IN_L_C
+3.3V_RUN LLINEIN LOUT AUD_DOCK_MIC_IN_R_C
ROUT 17
0.1U_0402_10V7K~D
10U_0805_10V6K~D
0.1U_0402_10V7K~D
reserve for SSM2603 1 2 AUD_DOCK_HP_R_R 23
C81 1000P_0402_50V7K~D RLINEIN
1000P_0402_50V7K~D
1 1 1 +3.3V_RUN DAI_SMBCLK 28 13 NC_LHPOUT T56 PAD~D

SCLK LHPOUT
10U_0805_10V6K~D
1U_0603_10V6K~D
0.1U_0402_10V7K~D
@ C400
DAI_SMBDATA 27 14 NC_RHPOUT T57 PAD~D
SDIN RHPOUT
C399
C401
1 1 1 1 +3.3V_RUN C79/C81
1
@ C403
U16 XTALI_12MHZ 1 6 I2S_12MHZ

2 2 2 close to U15 MCLK/XTI CLKOUT
C402
C404
C405
@ R1073 XTALO_12MHZ 2
10K_0402_5%~D XTO/ POR I2S_BCLK
1 DVDD_CORE AVDD 25 BCLK 7
2 2 2 2 9 38 AGND NC_MICIN 22
DVDD_CORE AVDD PAD~D T59 MICIN
B 40 PAD~D T60 NC_MICBIAS 21 8 I2S_DI# B
2
NC/OTP MICBIAS DACDAT I2S_DO
3 DVDD_IO ADCDAT 10
13 AUD_SENSE_A 25
SENSE_A AUD_SENSE_B MODE I2S_LRCLK
SENSE_B 34 DACLRC 9
Close to U16 pin1 & pin9 +3.3V_RUN 1 @ 2 26 11 NC_ADCLRC T61PAD~D
CSB ADCLRC
1
R330
10K_0402_5%~D
ICH_AZ_CODEC_BITCLK 6 39 R331 10K_0402_5%~D 20 29 AGND
<23> ICH_AZ_CODEC_BITCLK HDA_BITCLK PORT_A_L AUD_HP_OUT_L <28> VMID Thermal Pad
1
41 10K_0402_5%~D
PORT_A_R AUD_HP_OUT_R <28>
R333
1 2 ICH_AC_SDIN0_R 8 37 1 SSM2602_LFCSP28_5X5~D
<23> ICH_AZ_CODEC_SDIN0 HDA_SDI_CODEC NC
R332 33_0402_5%~D
2
ICH_AZ_CODEC_SDOUT 5 C406
<23> ICH_AZ_CODEC_SDOUT HDA_SDO 4.7U_0603_6.3V6M~D
+3.3V_RUN 21 AUD_EXT_MIC_L <33>
2
PORT_B_L 2
<23> ICH_AZ_CODEC_SYNC 10 HDA_SYNC PORT_B_R 22 AUD_EXT_MIC_R <33>
28 +VREFOUT AGND
VREFOUT_B
0.1U_0402_10V7K~D
11 C77
<23> ICH_AZ_CODEC_RST# HDA_RST# 1000P_0402_50V7K~D +3.3V_RUN +3.3V_RUN
1 23 1 2 AGND C77/C78
PORT_C_L
PORT_C_R 24 close to U16
C407
2.2K_0402_5%~D
2.2K_0402_5%~D
EMC Solution 29 1 2 AGND
VREFOUT_C
1
2 92HD71B
R334
R335
1000P_0402_50V7K~D
L75 35 C78
PORT_D_L AUD_LINE_OUT_L <28>
BLM18BB221SN1D_0603~D 36
PORT_D_R AUD_LINE_OUT_R <28>
2
<19> DMIC_CLK 1 2 DMIC_CLK_R 46
2
DMIC_CLK C408 1U_0805_16V7K~D R1091 200_0402_5%~D
Close to U16 pin3 1 2 14 AUD_DOCK_MIC_IN_L 2 1 DOCK_MIC_IN_L_C 1 2 AUD_DOCK_MIC_IN_L_C DAI_SMBCLK 1 6
<19> DMIC0 DMIC0/VOL_UP/GPIO1 PORT_E_L CKG_SMBCLK <6,38,48>
15 AUD_DOCK_MIC_IN_R 2 1 DOCK_MIC_IN_R_C 1 2 AUD_DOCK_MIC_IN_R_C
C486 PORT_E_R C409 1U_0805_16V7K~D R1092 200_0402_5%~D Q36A
4 DMIC1/VOL_DN/GPIO2 GPIO4/VREFOUT_E 31
5
150P_0402_50V8J~D 2N7002DW-T/R7_SOT363-6~D
2 C410 0.22U_0805_16V7K R340 200_0402_5%~D
Close to U16 pin6
16 AUD_DOCK_HP_OUT_L 2 1 AUD_DOCK_HP_L_C 1 2 AUD_DOCK_HP_L_R DAI_SMBDATA 4 3
PORT_F_L CKG_SMBDAT <6,38,48>
17 AUD_DOCK_HP_OUT_R 2 1 AUD_DOCK_HP_R_C 1 2 AUD_DOCK_HP_R_R For next version I2S.
PORT_F_R
10M_0402_5%~D
10M_0402_5%~D
ICH_AZ_CODEC_BITCLK 30 200_0402_5%~D will disconnect SMBUS Q36B
GPIO3
2
C411 0.22U_0805_16V7K R342 and PU. 2N7002DW-T/R7_SOT363-6~D
1
R308
R309
<28> AUD_EAPD 47 SPDIF_OUT_0_1/EAPD/GPIO0 Need check the PU
@ R343 18 Place close to U16
10_0402_5%~D NC value.
48 SPDIF_OUT_0 NC 19
20
1
NC
2
1
12 AUD_PC_BEEP +3.3V_RUN +3.3V_RUN
@C412
@C412 PC_BEEP
10P_0402_50V8J~D
AGND
2
0.1U_0402_16V7K~D
43 32
44
GPIO5 MONO_OUT Layout Skill
GPIO6
45 SPDIF_OUT_1/GPIO7 AGND short to GND
2
DA204U_SOT323-3~D
DA204U_SOT323-3~D
DA204U_SOT323-3~D
DA204U_SOT323-3~D
33 CAP2 2
CAP2
C413
@ D17
@ D18
@ D19
@ D55
27 VREFFILT
VREFFILT
10U_0805_10V6K~D
1U_0603_10V6K~D
Close to U16 pin5 7 DVSS 1 1 1
C414
C415
26 U17
AVSS
49 42 16
1
ICH_AZ_CODEC_SDOUT Thermal PAD GND AVSS VCC
2 2 I2S_BCLK 2 3
1A 1Y# DAI_BCLK# <35>
1
92HD71B7A5NLGXA1X8_QFN48_7x7~D
@ R344 I2S_LRCLK 4 5
47_0402_5%~D 2A 2Y# DAI_LRCK# <35>
AGND I2S_DO 6 7
3A 3Y# DAI_DO# <35>
2
1 I2S_12MHZ 10 9
4A 4Y# DAI_12MHZ# <35>
@C416
@C416 @ SPEAKER SET 12 11
0.1U_0402_10V7K~D 5A 5Y#
2 Part Number Description
14 13 I2S_DI#
6A 6Y#
DAA00000R0L PCB 03P LA-4051P REV0 M/B
<37> EN_I2S_NB_CODEC 1 OE1#
2 1 15 OE2# GND 8
R345 +3.3V_RUN
1K_0402_5%~D
A +VDDA CD74HC366M96_SO16~D A
Place closely to Pin 34
2
Place closely to Pin 13. R346 +VDDA +3.3V_RUN +3.3V_RUN
5.11K_0402_1%~D R347 D20
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
@
AUD_SENSE_A 2 1 5.11K_0402_1%~D DA204U_SOT323-3~D
AUD_SENSE_B 2 1
+3.3V_RUN
1000P_0402_50V7K~D
1000P_0402_50V7K~D
+3.3V_RUN +3.3V_RUN +3.3V_RUN

39.2K_0402_1%~D
20K_0402_1%~D
39.2K_0402_1%~D
1 1 2 2
1
1
20K_0402_1%~D
1
1
R348
R349
C417
C420
C418
C419
@ @
1
1
100K_0402_5%~D
R352
R350
1
1
5
1
5
2 2 1 1
R351
100K_0402_5%~D R354
R353
R355 100K_0402_5%~D @ @
P
NC
NC
2
100K_0402_5%~D 4 2 4 2
2
Y A Y A DAI_DI <35>
2
2
6
G
2
74LVC1G14GV_SOT753-5~D 74LVC1G14GV_SOT753-5~D
3
6
U18 U19
<28,33,37> AUD_HP_NB_SENSE 2 5 AUD_MIC_SWITCH <33>
Q38A Q38B 2 5 1 2
<37> DOCK_HP_DET DOCK_MIC_DET <37>
1
2N7002DW-T/R7_SOT363-6~D 2N7002DW-T/R7_SOT363-6~D R762 0_0402_5%~D

Q40A Q40B
1
2N7002DW-T/R7_SOT363-6~D 2N7002DW-T/R7_SOT363-6~D

Azalia (HD) Codec
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-4041P
2 1
5 4 3 2 1
C421
+5V_SPK_AMP 1 2
0.1U_0402_10V7K~D
5
U20
AUD_NB_MUTE 2 @ R357
P
A
Y 4 1 2
AUD_HP_NB_SENSE 1
<27,33,37> AUD_HP_NB_SENSE B Speaker Connector
G
0_0402_5%~D
74AHCT1G08GW_SOT353-5~D 15 mils trace JSPK1
3
1 1
INT_SPK_R1 2
INT_SPK_R2 2
3 3
D INT_SPK_L1 D
4 4
INT_SPK_L2 5 5
<24> SPEAKER_DET# 6 6
C422 7 GND
+5V_SPK_AMP 1 2 8 GND
L19
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
0.1U_0402_10V7K~D BLM21PG600SN1D_0805~D MOLEX_53780-0670~D
5
U21 1 2 +5V_SPK_AMP
+5V_RUN
AUD_EAPD 2
P
<27> AUD_EAPD A AUD_HP_EN
Y 4 Place Close to Audio Chip Place Close to Audio Chip 1 1 1 1
@ C423
@ C424
@ C425
@ C426
1 B
W=40mils
G
+5V_SPK_AMP
1U_0603_10V6K~D
1U_0603_10V6K~D
0.1U_0402_10V7K~D
1U_0603_10V6K~D
10U_0805_10V6K~D
1U_0603_10V6K~D
10U_0805_10V6K~D
74AHCT1G08GW_SOT353-5~D
3
2 2 2 2
2 2 1 2 1 2 1
C427
C428
C429
C430
C431
C432
C433
1 1 2 1 2 1 2
30
18
8
U22
VDD
SPVDD
SPVDD
C434
0 .033U_0805_50V7K~D
1 2 SPKR_INL_C 3 6 INT_SPK_L1
<27> AUD_LINE_OUT_L SPKR_LIN+ LOUT+
C435
0 .033U_0805_50V7K~D
1 2 SPKR_INR_C 2 7 INT_SPK_L2
<27> AUD_LINE_OUT_R SPKR_RIN+ LOUT-
C436 10U_1206_25VAK~D
Gain Setting
1 2 1 2 HP_INL_C 27 20 INT_SPK_R1 +5V_SPK_AMP
<27> AUD_HP_OUT_L HP_INL ROUT+
R818 1K_0402_5%~D
C C437 10U_1206_25VAK~D C
1 2 1 2 HP_INR_C 26 19 INT_SPK_R2
<27> AUD_HP_OUT_R HP_INR ROUT-
100K_0402_5%~D
100K_0402_5%~D
R827 1K_0402_5%~D
1
47P_0402_50V8J~D
47P_0402_50V8J~D
47P_0402_50V8J~D
47P_0402_50V8J~D
@ R359
1 1 1 1 1 2 24 16 HP_SPK_L1
BYPASS HP_OUTL HP_SPK_L1 <33>
@C439
@
@C440
@
@C441
@
@C442
@
R358
C438 1U_0603_10V6K~D
C439
C440
C441
C442
AUD_SPK_ENABLE# 23 15 HP_SPK_R1 See Note 1
2
2 2 2 2 /SPKR_EN HP_OUTR HP_SPK_R1 <33>
2
AUD_HP_EN 22 AUD_GAIN1
HP_EN
AUD_AMP_MUTE# 25 31 AUD_GAIN1 AUD_GAIN2
REG_EN GAIN0
100K_0402_5%~D
100K_0402_5%~D
32 AUD_GAIN2
GAIN1
1
@ R360
+5V_SPK_AMP 17 HPVDD See Note 2
10U_0805_10V6K~D
1U_0603_10V6K~D
R361
@ R362 0_0402_5%~D
1 2 9 CPVDD SPKR_LIN- 4 1 2 RUN_ON <19,37,40,41>
1 2
2
C444
C445
C443
C1P 10 0.033U_0402_16V7K~D
2 1 1U_0603_10V6K~D C1P
REG_OUT 29 +VDDA
1
1M_0402_1%~D
1U_0603_10V6K~D
1U_0603_10V6K~D
C1N 12 C1N
R363
2 2 2 MINIMAM 150 mA
11 CPGND
C446
C447
C448
+5V_SPK_AMP SET
SPGND
SPGND
1
See Note 1
HPVSS
CPVSS
SPKR_RIN-
SGND
+5V_SPK_AMP
0.033U_0402_16V7K~D
2
1
1 1 1
0_0402_5%~D
TP
2
2
R366
C449
@ GAIN1 GAIN2 AV(inv) INPUT
14
13
28
5
21
33
R364 R367 TPA6040A4RHBR_QFN32_5X5~D IMPEDANCE
100K_0402_5%~D R365 1
100K_0402_5%~D
2
B 100K_0402_5%~D B
@
2 1+CPVSS 0 0 6dB 82K ohm
1
AUD_SPK_ENABLE# 8mil
RUN_ON 1 2 AUD_AMP_MUTE# C450
R368 0_0402_5%~D 1U_0603_10V6K~D 0 1 10dB 66K ohm
6
See Note 2
1 0 15.6dB 45K ohm
<27> AUD_EAPD 2
See Note 2 *
Q42A 1 1 21.6dB 26K ohm
1
2N7002DW-T/R7_SOT363-6~D
See Note 2
3
R362 R366 C443 C449 R367 R368

5
<37> AUD_NB_MUTE
Q42B
* TPA6040 @ @ @
4
2N7002DW-T/R7_SOT363-6~D
9789A @ @ @
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, AMP and PHONE JACK
LA-4041P
5 4 3 2 1
5 4 3 2 1
D D
Layout Notice : Place as close

chip as possible.
+3.3V_ALW
<24> PCIE_IRX_GLANTX_P6 2 1 PCIE_IRX_GLANTX_P6_C
C451 0.1U_0402_10V7K~D U23
52 26 LAN_TX0-
GLAN_TXP MDI_N_0 LAN_TX0- <30>
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
<24> PCIE_IRX_GLANTX_N6 2 1 PCIE_IRX_GLANTX_N6_C 53 GLAN_TXN MDI_P_0 27 LAN_TX0+
LAN_TX0+ <30>
C452 0.1U_0402_10V7K~D Q44 +3.3V_LAN
2 2
55 22 LAN_TX1- STS11NF30L_SO8~D
<24> PCIE_ITX_GLANRX_P6_C GLAN_RXP MDI_N_1 LAN_TX1- <30>
C453
C454
56 23 LAN_TX1+ 8 1
<24> PCIE_ITX_GLANRX_N6_C GLAN_RXN MDI_P_1 LAN_TX1+ <30>
7 2
1 1
10U_0805_10V4Z~D
4.7U_0603_6.3V4Z~D
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
20 LAN_TX2- 6 3
MDI_N_2 LAN_TX2- <30>
1 2 LAN_CLK_R 45 21 LAN_TX2+ 5 1 2 2 2 2
<23> LAN_CLK JKCLK MDI_P_2 LAN_TX2+ <30>
R369 33_0402_5%~D50
<23> LAN_RSTSYNC JRSTSYNC
C455
C456
C457
C458
C459
16 LAN_TX3-
LAN_TX3- <30>
4
MDI_N_3 LAN_TX3+ +3.3V_LAN
<23> LAN_TX0 42 JTXD_0 MDI_P_3 17 LAN_TX3+ <30> <40> ENAB_3VLAN 2 1 1 1 1
<23> LAN_TX1 43 JTXD_1
0.1U_0402_16V4Z~D
4.7U_0603_6.3V4Z~D
<23> LAN_TX2 44 JTXD_2 VDDO_33_3 3
46 +3.3V_LAN
VDDO_33_46
<23> LAN_RX0 47 JRXD_0 AVDD_33_28 28 2 2
<23> LAN_RX1 48 JRXD_1
C463
C464
<23> LAN_RX2 49 JRXD_2 DVDD_10_5 5 +1V_LAN_M
1
2_1210_5%~D
2_1210_5%~D
DVDD_10_8 8
C 1 1 C
DVDD_10_33 33
R370
R371
DVDD_10_38 38
<30> LOM_ACTLED_YEL# 4 LED_0
2 11 +1.8V_LAN_M
+1.8V_LAN_M
2
<30> LOM_SPD100LED_ORG# LED_1 AVDD_18_11
<30> LOM_SPD10LED_GRN# 1 LED_2 AVDD_18_14 14 Trace=12mil
19 +3.3V_LAN_R
AVDD_18_19
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
AVDD_18_18 18
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
4.7U_0603_6.3V4Z~D
470P_0402_50V7K~D
470P_0402_50V7K~D
2 1 15 RSET AVDD_18_24 24 2 1
R372 4.99K_0402_1%~D 25 R374 1 1 1 2 2 2 2 1 1
AVDD_18_25
C466
41 5.1K_0402_5%~D
AVDD_18_41
C465
C467
C468
C469
C470
C471
C472
C473
1 2 LAN_TEST_P 12 54
@R373
@ R373 0_0402_5%~D LAN_TEST_N IEEE_TEST_P AVDD_18_54
13 IEEE_TEST_N AVDD_18_32 32
3
2 2 2 1 1 1 1 2 2
AVDD_18_30 30 Trace=12mil
2 R376 1 34 DIS_REG10
1K_0402_5%~D 29 REGCTL_PNP18 REGCTL_PNP18 1
CTRL18
<24> LAN_DISABLE# 1 2 37 LAN_DISABLE_N CTRL10 31
@R934
@ R934 Q45
0_0402_5%~D 1 2 36 51 BCP69_SOT223~D
2
4
R378 10K_0402_5%~D TEST_EN RESERVED_NC
JTAG_TRST
JTAG_TMS
JTAG_TDO
JTAG_TCK
XTALO +1.8V_LAN_M
JTAG_TDI
<37> LAN_DISABLE#_R 9 XTAL2

XTALI 10 57
XTAL1 GND_PAD
10U_0805_10V4Z~D
1 2 XTALO 1
C474
R379 0_0402_5%~D 82567LM_QFN56~D
35
40
39
7
6
JTAG_TDO_LAN T145 PAD~D

XTALI JTAG_TDI_LAN 2
1 2 T146 PAD~D
JTAG_TMS_LAN T147 PAD~D
Y2 JTAG_TCK_LAN T148 PAD~D
2 25MHZ_18PF_1BX25000CK1D~D 2 JTAG_TRST_LAN T149 PAD~D
B C475 C476 B
+LOM_VCT = 2.5V (WO/Docking)
27P_0402_50V8J~D 27P_0402_50V8J~D
1 1 = 2.65V (W/Docking)
+1V_LAN_M
Need to ensure MA use internal 1V,NOT external solutions. VOUT = 1.204 (1+R1/R2),
crystal at least 82567LM: where R1 = R1017 + R1018, R2 = R1019
+LOM_VCT
4.7U_0805_10V4Z~D
4.7U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
300uW max power B0 version: 1.05V +3.3V_LAN
1 1 2 2 2
drive-level A1 version: 1V Q50
C477
C478
1 VIN VOUT 5
0.1U_0402_16V4Z~D
C479
C217
C314
2 GND 2 2 1 1 1
4.7U_0603_6.3V4Z~D
4.7U_0603_6.3V4Z~D
3 EN ADJ 4
1 1
C483
1
1 TPS73601
C482
C484
R1017
3
E
Q146 4.64K_0402_1%
B 2 2
2
2 MMBT3906WT1G_SC70-3~D
2
C
1
1
R1020
Follow 82567 schematic
1
10K_0402_5%~D chiplist that VCC_1.0 for
R1018
39.2K_0402_1%~D
external use 10uF XR5 *2 and
2
<30,37> DOCKED
DOCKED 0.1uF *2
for internal use 4.7uF X5R *2
2
and 0.1uF *3
1
R1019
A 36.5K_0402_1%~D A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT LAN-82567LM
5 4 3 2 1
5 4 3 2 1
D D
+3.3V_LAN
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2 2 2
C460
C461
C462
LAN ANALOG
1 1 1
SWITCH
56
50
38
27
18
10
4
U25
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
VDD0
48 SW_LAN_TX0-
0B1 SW_LAN_TX0- <33>
47 SW_LAN_TX0+
1B1 SW_LAN_TX0+ <33>
LAN_TX0- 1 2 LAN_TX0-R 2
<29> LAN_TX0- A0
L20 22NH_0603CS-360EJTS_5%_0603~D 43 SW_LAN_TX1-
2B1 SW_LAN_TX1- <33>
LAN_TX0+ 1 2 LAN_TX0+R 3 42 SW_LAN_TX1+
<29> LAN_TX0+ A1 3B1 SW_LAN_TX1+ <33>
L21 22NH_0603CS-360EJTS_5%_0603~D
37 SW_LAN_TX2-
LAN_TX1- LAN_TX1-R 4B1 SW_LAN_TX2+ SW_LAN_TX2- <33>
<29> LAN_TX1- 1 2 7 A2 5B1 36 SW_LAN_TX2+ <33>
L22 22NH_0603CS-360EJTS_5%_0603~D
C LAN_TX1+ 1 LAN_TX1+R SW_LAN_TX3- C
<29> LAN_TX1+ 2 8 A3 6B1 32 SW_LAN_TX3- <33>
L23 22NH_0603CS-360EJTS_5%_0603~D 31 SW_LAN_TX3+
7B1 SW_LAN_TX3+ <33>
LAN_TX2- 1 2 LAN_TX2-R 11 22 LAN_LEDACT#
<29> LAN_TX2- A4 0LED1 LAN_LEDACT# <33>
L24 22NH_0603CS-360EJTS_5%_0603~D 23 LINK_LED10#
1LED1 LINK_LED10# <33>
LAN_TX2+ 1 2 LAN_TX2+R 12 52 LINK_LED100#
<29> LAN_TX2+ A5 2LED1 LINK_LED100# <33>
L25 22NH_0603CS-360EJTS_5%_0603~D
46 DOCK_LOM_TRD0-
0B2 DOCK_LOM_TRD0- <35>
LAN_TX3- 1 2 LAN_TX3-R 14 45 DOCK_LOM_TRD0+
<29> LAN_TX3- A6 1B2 DOCK_LOM_TRD0+ <35>
L26 22NH_0603CS-360EJTS_5%_0603~D
LAN_TX3+ 1 2 LAN_TX3+R 15 41 DOCK_LOM_TRD1-
<29> LAN_TX3+ A7 2B2 DOCK_LOM_TRD1- <35>
L27 22NH_0603CS-360EJTS_5%_0603~D 40 DOCK_LOM_TRD1+
3B2 DOCK_LOM_TRD1+ <35>
DOCKED 17 35 DOCK_LOM_TRD2-
<29,37> DOCKED SEL 4B2 DOCK_LOM_TRD2+ DOCK_LOM_TRD2- <35>
5B2 34 DOCK_LOM_TRD2+ <35>
19 30 DOCK_LOM_TRD3-
<29> LOM_ACTLED_YEL# LED0 6B2 DOCK_LOM_TRD3- <35>
20 29 DOCK_LOM_TRD3+
<29> LOM_SPD10LED_GRN# LED1 7B2 DOCK_LOM_TRD3+ <35>
Layout Notice : Place bead as <29> LOM_SPD100LED_ORG# 54 LED2
25 DOCK_LOM_ACTLED_YEL#
close PI3L500 as possible 0LED2 DOCK_LOM_SPD10LED_GRN#
DOCK_LOM_ACTLED_YEL# <35>
5 NC 1LED2 26 DOCK_LOM_SPD10LED_GRN# <35>
51 DOCK_LOM_SPD100LED_ORG#
2LED2 DOCK_LOM_SPD100LED_ORG# <35>
57 PAD_GND
GND10
GND11
GND12
GND13
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
PI3L500-AZFEX_TQFN56~D TO
1
6
9
13
16
21
24
28
33
39
44
49
53
55
1: TO DOCK DOCK
FROM NIC DOCKED
0: TO RJ45
B B
+3.3V_LAN
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
1
1
@ R392
@ R393
@ R394
2
LOM_ACTLED_YEL#
LOM_SPD10LED_GRN#
LOM_SPD100LED_ORG#
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT LAN TRANSFOMER
5 4 3 2 1
5 4 3 2 1
0.01U_0402_16V7K~D
0.33U_0603_10V7K~D
TPBIAS0
U26A
56.2_0402_1%~D
56.2_0402_1%~D
1 1
1
R5C847-CSP208Q
R398
R399
C492
C493
<22> PCI_AD[0..31] 2 2
PCI_AD0 W12 B19
AD0 CDATA10/CAD31 CBS_CAD31 <32>
PCI_AD1 V12 C18 JS1394
CBS_CAD30 <32>
2
PCI_AD2 AD1 CDATA9/CAD30
T12 AD2 CDATA1/CAD29 D19 CBS_CAD29 <32> 1 1
PCI_AD3 W11 D18 TPAP0 2
AD3 CDATA8/CAD28 CBS_CAD28 <32> 2
PCI_AD4 V11 E19 TPAN0 3
AD4 CDATA0/CAD27 CBS_CAD27 <32> 3
PCI_AD5 T11 E16 4
AD5 CADR0/CAD26 CBS_CAD26 <32> 4
PCI_AD6 W9 F18 TPBP0 5
PCI_AD7 V9 F15 TPBN0 6
+3.3V_RUN AD7 CADR2/CAD24 CBS_CAD24 <32> 6
PCI_AD8 R9 G18 7
1
PCI_AD9 W8 G15 1394_DET# 8
AD9 CADR4/CAD22 CBS_CAD22 <32> <24> 1394_DET# 8
1
D CB_HWSPND# PCI_AD10 PWR_BTN_BD_DET# D
1 2 V8 AD10 CADR5/CAD21 H18 CBS_CAD21 <32> <37> PWR_BTN_BD_DET# 9 9
R400 10K_0402_5%~D PCI_AD11 T8 H15 R403 R401 SNIFFER_BLUE 10
AD11 CADR6/CAD20 CBS_CAD20 <32> <42> SNIFFER_BLUE 10
1 2 CBS_SPK PCI_AD12 R8 J18 56.2_0402_1%~D 56.2_0402_1%~D SNIFFER_YELLOW 11
AD12 CADR25/CAD19 CBS_CAD19 <32> <42> SNIFFER_YELLOW 11
R402 100K_0402_5%~D PCI_AD13 W7 J16 SNIFFER_PWR_SW# 12
CBS_CAD18 <32> <38> SNIFFER_PWR_SW#
2
UDIO3 PCI_AD14 AD13 CADR7/CAD18 WIRELESS_ON#/OFF 12
1 2 V7 J15 CBS_CAD17 <32> <37> WIRELESS_ON#/OFF 13
2
R405 10K_0402_5%~D PCI_AD15 AD14 CADR24/CAD17 Z3008 INSTANT_ON_SW# 13
T7 AD15 CADR17/CAD16 P16 CBS_CAD16 <32> <37,38> INSTANT_ON_SW# 14 14
PCI_AD16 V1 P19 CBS_CAD15 POWER_SW#_MB 15
AD16 IOWR#/CAD15 CBS_CAD15 <32> <38,39> POWER_SW#_MB 15
2
PCI_AD17 U1 R19 2 BREATH_BLUE_LED_IO 16
AD17 CADR9/CAD14 CBS_CAD14 <32> <42> BREATH_BLUE_LED_IO 16
PCI_AD18 U2 P18 CBS_CAD13 R407 17
AD18 IORD#/CAD13 CBS_CAD13 <32> <37,42> LID_CL# 17
+3.3V_RUN_PHY PCI_AD19 T1 R18 C494 5.1K_0402_1%~D +3.3V_ALW 18
0.1U_0402_16V4Z~D
PCI_AD20 T2 T19 270P_0402_50V7K~D 19
AD20 OE#/CAD11 CBS_CAD11 <32> 1 19
PCI I/F
1 2 CPS PCI_AD21 R1 T18 2 20
CBS_CAD10 <32>
1
R404 0_0402_5%~D PCI_AD22 AD21 CE2#/CAD10 20
R2 AD22 CADR10/CAD9 U19 CBS_CAD9 <32>
C685
PCI_AD23 R4 U18 21
AD23 CDATA15/CAD8 CBS_CAD8 <32> GND1
1 2 UDIO4 PCI_AD24 P4 W17 22
AD24 CDATA7/CAD7 CBS_CAD7 <32> 1 GND2
R406 10K_0402_5%~D PCI_AD25 P5 V17
PCI_AD26 N1 W16 Close to U26
16 bit PC card I/F

PCI_AD27 N2 V16 TYCO_2-1734820-0_20P-T
PCI_AD28 N4 W15
PCI_AD29 N5 V15
PCI_AD30 M1 T15
PCI_AD31 M2 R14
PCI_PAR V6 F16 CBS_CC/BE3#
<22> PCI_PAR PAR REG#/CCBE3# CBS_CC/BE3# <32>
<22> PCI_C_BE0# PCI_C_BE0# T9 K18 CBS_CC/BE2#
C/BE0# CADR12/CCBE2# CBS_CC/BE2# <32>
<22> PCI_C_BE1# PCI_C_BE1# W6 P15 CBS_CC/BE1#
C/BE1# CADR8/CCBE1# CBS_CC/BE1# <32>
<22> PCI_C_BE2# PCI_C_BE2# W2 V19 CBS_CC/BE0#
C/BE2# CE1#/CCBE0# CBS_CC/BE0# <32>
<22> PCI_C_BE3# PCI_C_BE3# P2 N15 CBS_CPAR
C/BE3# CADR13/CPAR CBS_CPAR <32>
PCI_AD17 1 2 CBS_IDSEL P1 K16 CBS_CFRAME#
IDSEL CADR23/CFRAME# CBS_CFRAME# <32>
R409 100_0402_5%~D L16 CBS_CTRDY#
CADR22/CTRDY# CBS_CTRDY# <32>
PCI_REQ1# M4 K15 CBS_CIRDY#
<22> PCI_REQ1# REQ# CADR15/CIRDY# CBS_CIRDY# <32>
PCI_GNT1# M5 M16 CBS_CSTOP#
C <22> PCI_GNT1# GNT# CADR20/CSTOP# CBS_CSTOP# <32> C
PCI_FRAME# V3 L18 CBS_CDEVSEL#
<22> PCI_FRAME# FRAME# CADR21/CDEVSEL# CBS_CDEVSEL# <32>
PCI_IRDY# V4 N19 CBS_CBLOCK#
<22> PCI_IRDY# IRDY# CADR19 CBS_CBLOCK# <32>
PCI_TRDY# W4 N18 CBS_CPERR#
<22> PCI_TRDY# TRDY# CADR14/CPERR# CBS_CPERR# <32>
PCI_DEVSEL# T5 G16 CBS_CSERR#
<22> PCI_DEVSEL# DEVSEL# WAIT#/CSERR# CBS_CSERR# <32>
PCI_STOP# V5 G19 CBS_CREQ# must have clean layout
<22> PCI_STOP# STOP# INPACK#/CREQ# CBS_CREQ# <32>
PCI_PERR# W5 M15 CBS_CGNT#
<22> PCI_PERR# PERR# WE#/CGNT# CBS_CGNT# <32>
PCI_SERR# T6 E18 CBS_CSTSCHNG
<22> PCI_SERR# SERR# BVD1/CSTSCHG CBS_CSTSCHNG <32> +3.3V_RUN +CBS_VCC
A18 CBS_CCLKRUN# U27
WP/CCLKRUN# CBS_CCLKRUN# <32>
CBUS_GRST# G2 L19 CBS_CCLK_R 2 1
GBRST# CADR16/CCLK CBS_CCLK <32>
CLK
RST&
L4 M18 CBS_CINT# R410 11 9

<22> PCI_RST# PCIRST# READY/CINT# CBS_CINT# <32> VCC3IN VCCOUT
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
CLK_PCI_PCM K1 H19 CBS_CRST# 22_0402_5%~D 14
<6> CLK_PCI_PCM PCICLK RESET/CRST# CBS_CRST# <32> +5V_RUN VCCOUT
1U_0402_6.3V6K~D
@ C497
CLKRUN# L5 F19 CBS_CAUDIO 12 1 1
<24,37,38> CLKRUN# CLKRUN# BVD2/CAUDIO CBS_CAUDIO <32> VCCOUT
CB_HWSPND# F2 1 2 1
<37> CB_HWSPND# HWSPND#
C496
T14 CBS_CCD1# @ C501 13
CD1#/CCD1# CBS_CCD1# <32> VCC5IN
C495
1U_0402_6.3V6K~D
J2 D15 CBS_CCD2# 0.01U_0402_16V7K~D 15
<22> PCI_PIRQD# INTA# CD2#/CCD2# CBS_CCD2# <32> VCC5IN +CBS_VPP 2 2
K4 R16 CBS_CVS1 1
<22> PCI_PIRQB# INTB# VS1#/CVS1 CBS_CVS1 <32> 2
K2 H16 CBS_CVS2
<22> PCI_PIRQC# INTC# VS2#/CVS2 CBS_CVS2 <32>
AUDIO
INT &
C498
J4 C502 VPPEN0 3 8
<24,36,37,38> IRQ_SERIRQ UDIO0/SRIRQ# EN0 VPPOUT
0.1U_0402_16V4Z~D
0.01U_0402_16V7K~D
H1 W18 CBS_DATA14 CBS_CCD1# 2 1 VPPEN1 4
UDIO1 CDATA14 CBS_DATA14 <32> 2 EN1
@ C500
H2 C19 CBS_DATA2 1 2
UDIO2 CDATA2 CBS_DATA2 <32>
UDIO3 H4 N16 CBS_DATA18 270P_0402_50V7K~D
UDIO3 CADR18 CBS_DATA18 <32>
C499
UDIO4 H5 V13 VPPEN0 C503 VCC3EN# 2
UDIO4 VPPEN0 VPPEN1 CBS_CCD2# VCC5EN# VCC3_EN
G1 UDIO5 VPPEN1 W13 2 1 1 VCC5_EN
VCC5EN# 2 1
G4 RI_OUT#/PME# VCC5EN# R13
CBS_SPK F1 T13 VCC3EN# 270P_0402_50V7K~D
SPKROUT# VCC3EN#
5 FLG NC 7
TPAP0 B12 B1 SDCD#/MMCCD# 16 6
TPAP0 MDIO00 GND NC
1394 I/F
TPAN0 A12 A2 10
TPBP0 TPAN0 MDIO01 NC
B13 TPBP0 MDIO02 A3
TPBN0 A13 B3 SDWP#
TPBIAS0 TPBN0 MDIO03 CARD_PWR R5531V002-E2-FA_SSOP16~D
D12 TPBIAS0 MDIO04 B4
Media Card I/F
CPS D11 A5
B CBVREF CPS MDIO05 B
D13 VREF MDIO06 B5
0.01U_0402_16V7K~D
CBREXT B14 D5 MDIO07 2 1

REXT MDIO07
10K_0402_1%~D
R5C847XI A16 A6 SDCMD/MMCCMD R414 0_0402_5%~D +3.3V_ALW_ICH

XI MDIO08
2
2 R5C847XO B16 B6 SDCLK/MMCCLK 1 2 SDCLK/MMC_CLK_R

XO MDIO09
2
C513
R417
A14 D6 SDDAT0/MMCDAT0 R416 27_0402_5%

FIL0 MDIO10 SDDAT1/MMCDAT1 R910
MDIO11 E6 1
A7 SDDAT2/MMCDAT2 R416/C397 100K_0402_5%~D
1 MDIO12
USB TEST
W14 B7 SDDAT3/MMCDAT3 close to R5C847 C397

1
USBDM MDIO13 MMCDAT4 JSD1

V14 D7 33P_0402_50V8J~D
1
USBDP MDIO14 MMCDAT5 2 SD_DET#
MDIO15 E7 <24> SD_DET# 1 1
A8 MMCDAT6 For MMC PLUS SDWP# 2
MDIO16 MMCDAT7 SDCD#/MMCCD# 2
MDIO17 B8 3 3
close to U26 F4 D8 SDDAT1/MMCDAT1 4
TEST1 MDIO18 SDDAT0/MMCDAT0 4
R7 TEST2 MDIO19 E8 5 5
MMCDAT7 6
MMCDAT6 6
7 7
R5C847-CSP208Q_CSP208~D 8
SDCLK/MMC_CLK_R 8
9 9
10 10
+3.3V_RUN_CARD 11 11
MMCDAT5 12
+3.3V_RUN +3.3V_RUN_CARD SDCMD/MMCCMD 12
13 13
U28 MMCDAT4 14
CLK_PCI_PCM R5C847XI SDDAT3/MMCDAT3 14
2 1 5 IN OUT 1 15 15
+3.3V_RUN C514 2 SDDAT2/MMCDAT2 16
GND 16
2
@
0.01U_0402_16V7K~D
1U_0603_10V4Z~D
150K_0402_5%~D
27P_0402_50V8J~D CARD_PWR 4 3
EN OC#
1
2
10_0402_5%~D
100K_0402_5%~D
0.1U_0402_16V4Z~D
X3 2 1
1
R418
22P_0402_50V8J~D 24.576MHz_16P_1BG24576CKIA~D TPS2051BDBVR_SOT23-5~D 17 G1

R420
C505
C506
R413
C515 1 18
1
R5C847XO G2
2 1 2 1
1 2
C509
R421 0_0402_5%~D
PCI_CBS_TERM 2
1
2
A 2 A
CBUS_GRST# Close to Pin A16,B16 TYCO_1-1775737-6
Close to JSD1 Close to JSD1
1U_0603_10V4Z~D
1
C516
4.7P_0402_50V8C~D
2 VPPEN0 1 2
SDCLK/MMCCLK R411 1 2 100K_0402_5%~D
2 Compal Electronics, Inc.
C517
@R412
@ R412 100K_0402_5%~D
1 @ TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CardBus Controller(R5C843)
LA-4041P
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN +3.3V_RUN L28 +3.3V_RUN_PHY

BLM21A601SPT_0805~D
1 2
10U_0805_10V4Z~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1 1 1 1 1
1 1 1 1 1 1
C524
C525
C526
C527
C528
+1.5V_CARD
C519
C520
C521
C522
C523
C776
2 2 2 2 2
2 2 2 2 2 2 +1.5V_RUN
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
10U_0805_6.3V6M~D
D D
+3.3V_SUS +3.3V_RUN
0.1U_0402_16V4Z~D
1 1 1 1 +3.3V_CARD
+3.3V_RUN 10U_0805_10V4Z~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
C997
C999
C90
C101
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 1 2 2 2 2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
10U_0805_6.3V6M~D
1 1 1 1 U26B U52
C531
C532
C134
C135
12 11
R5C847-CSP208Q 1.5Vin 1.5Vout
C529
C530
14 1.5Vin 1.5Vout 13 1 1 1
2 2
F5 VCC_3V GND J1
2 2 2 2
C91
C92
C93
G5 VCC_3V GND J5
J19 VCC_3V GND K5 2 3.3Vin 3.3Vout 3
2 2 2
DIGITAL
POWER
DIGITAL
K19 VCC_3V GND E9 4 3.3Vin 3.3Vout 5
W3 VCC_PCI3V GND R10 +3.3V_CARDAUX
+3.3V_RUN R11 T10 17 15
VCC_PCI3V GND AUX_IN AUX_OUT
R12 VCC_PCI3V GND V10
+3.3V_SUS
0.1U_0402_16V4Z~D
10U_0805_6.3V6M~D
PLTRST1#
GND
R6 VCC_RIN GND W10 <10,22> PLTRST1# 6 SYSRST# OC# 19
10U_0805_10V4Z~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.1U_0402_10V7K~D
E13 VCC_RIN GND L15

L1 M19 R657 1 @ 2 20 8 1 1
VCC_ROUT GND SHDN# PERST#
C96
E14 100K_0402_5%~D
VCC_ROUT
0.47U_0402_16V4Z~D
0.01U_0402_16V7K~D
0.47U_0402_16V4Z~D
0.01U_0402_16V7K~D
C105
1 1 1 1 A4 R683 1 2 EXPRCRD_STBY_R# 1 16
VCC_MD3V <37> EXPRCRD_STDBY# STBY# NC
1 1 1 1 +3.3V_RUN_PHY A9 0_0402_5%~D
ANALOG
AGND 2 2
C533
C534
C535
C536
POWER
ANALOG
B9 R684 1 @ 2 EXPRCRD_PWREN# 10 7
AGND CPPE# GND
C537
C538
C539
C540
E10 D9 100K_0402_5%~D
2 2 2 2 AVCC_PHY3V AGND R790 1 @ CPUSB#
E11 AVCC_PHY3V AGND D14 2 9 CPUSB#
GND
2 2 2 2 100K_0402_5%~D
A17 AVCC_PHY3V AGND A15
B17 AVCC_PHY3V AGND B15 <37> EXPRCRD_PWREN# 18 RCLKEN
R5538_QFN20~D CARD_RESET#
D10 NC NC A10
E1 A11
C
C2
D2
NC
NC
NC
NC
NC
NC
NC
B10
B11
Express Card C
E2 NC NC C1
L2 NC NC D1
+3.3V_ALW
E4 NC NC E12 +1.5V_CARD: Max. 650mA, Average 500mA
R5C847-CSP208Q_CSP208~D
+3.3V_CARD: Max. 1300mA, Average 1000mA
2
+1.5V_CARD R874
0.1U_0402_16V4Z~D
100K_0402_5%~D
<31> CBS_CAD[0..31] 1
1
C97
JCBUS1 1 2
1 35 @ R791 0_0402_5%~D JEXP1
CBS_CAD0 GND1 GND3 CBS_CCD1# 2
2 CAD0 CCD1# 36 CBS_CCD1# <31> <37> EXPRCRD_DET# 1 GND1
CBS_CAD1 3 37 CBS_CAD2 2
CBS_CAD3 CAD1 CAD2 CBS_CAD4 @ GND2
4 CAD3 CAD4 38 1 2 3 GND3
CBS_CAD5 5 39 CBS_CAD6 R792 0_0402_5%~D 4
CBS_CAD7 CAD5 CAD6 CBS_DATA14 USBP7_D- GND4
6 CAD7 CB_D14 40 CBS_DATA14 <31> <24> USBP7- 1 1 2 2 5 USBD-
<31> CBS_CC/BE0# CBS_CC/BE0# 7 41 CBS_CAD8 USBP7_D+ 6
CBS_CAD9 CCBE0# CAD8 CBS_CAD10 CPUSB# USBD+
8 CAD9 CAD10 42 7 CPUSB#
CBS_CAD11 9 43 CBS_CVS1 4 3 8
CAD11 CVS1 CBS_CVS1 <31> <24> USBP7+ 4 3 RESERVE1
CBS_CAD12 10 44 CBS_CAD13 L64 9
CBS_CAD14 CAD12 CAD13 CBS_CAD15 DLW21SN900SQ2_0805~D EXP_SMBCLK RESERVE2
11 CAD14 CAD15 45 10 SMBCLK
<31> CBS_CC/BE1# CBS_CC/BE1# 12 46 CBS_CAD16 EXP_SMBDATA 11
CBS_CPAR CCBE1# CAD16 CBS_DATA18 SMBDATA
<31> CBS_CPAR 13 CPAR CB_D18 47 CBS_DATA18 <31> 12 +1.5V_1
<31> CBS_CPERR# CBS_CPERR# 14 48 CBS_CBLOCK# CBS_CBLOCK# <31> 13
CBS_CGNT# CPERR# CBLOCK# CBS_CSTOP# PCIE_WAKE# +1.5V_2
<31> CBS_CGNT# 15 CGNT# CSTOP# 49 CBS_CSTOP# <31> <34,37> PCIE_WAKE# 14 WAKE#
<31> CBS_CINT# CBS_CINT# 16 50 CBS_CDEVSEL# CBS_CDEVSEL# <31> +3.3V_CARDAUX 15
CINT# CDEVSEL# +3.3VAUX
0.1U_0402_16V4Z~D
+CBS_VCC 17 51 +CBS_VCC CARD_RESET# 16
B VCC VCC PERST# B
+CBS_VPP 18 VPP1 VPP2 52 +CBS_VPP +3.3V_CARD 17 +3.3V_1
<31> CBS_CCLK CBS_CCLK 19 53 CBS_CTRDY# 1 18
CCLK CTRDY# CBS_CTRDY# <31> +3.3V_2
<31> CBS_CIRDY# CBS_CIRDY# 20 54 CBS_CFRAME# 19
CIRDY# CFRAME# CBS_CFRAME# <31> +3.3V_3
C94
<31> CBS_CC/BE2# CBS_CC/BE2# 21 55 CBS_CAD17 20
CBS_CAD18 CCBE2# CAD17 CBS_CAD19 <6> EXPCLK_REQ# EXPRCRD_PWREN# CLKREQ#
22 CAD18 CAD19 56 21 CPPE#
2
0.1U_0402_16V4Z~D
CBS_CAD20 23 57 CBS_CVS2 22
CAD20 CVS2 CBS_CVS2 <31> NC
CBS_CAD21 24 58 CBS_CRST# 23
CAD21 CRST# CBS_CRST# <31> <6> CLK_PCIE_EXP# REFCLK-
CBS_CAD22 25 59 CBS_CSERR# 1 24
CAD22 CSERR# CBS_CSERR# <31> <6> CLK_PCIE_EXP REFCLK+
CBS_CAD23 26 60 CBS_CREQ# 25
CAD23 CREQ# CBS_CREQ# <31> GND5
C95
CBS_CAD24 27 61 CBS_CC/BE3# 26
CAD24 CCBE3# CBS_CC/BE3# <31> GND6
CBS_CAD25 28 62 CBS_CAUDIO 27
CAD25 CAUDIO CBS_CAUDIO <31> 2 GND7
CBS_CAD26 29 63 CBS_CSTSCHNG 28
CAD26 CSTSCHG CBS_CSTSCHNG <31> GND8
CBS_CAD27 30 64 CBS_CAD28 <24> PCIE_IRX_EXPTX_N4 29
CBS_CAD29 CAD27 CAD28 CBS_CAD30 PERN0
31 CAD29 CAD30 65 <24> PCIE_IRX_EXPTX_P4 30 PERP0
<31> CBS_DATA2 CBS_DATA2 32 66 CBS_CAD31 31
CBS_CCLKRUN# CB_D2 CAD31 CBS_CCD2# GND9
<31> CBS_CCLKRUN# 33 CCLKRUN# CCD2# 67 CBS_CCD2# <31> 32 GND10
34 GND2 GND4 68 33 GND11
+3.3V_SUS 34 GND12
<24> PCIE_ITX_EXPRX_N4_C 35 PETN0
@ IO FPC 69 71 36
GND5 GND7 <24> PCIE_ITX_EXPRX_P4_C PETP0
Part Number Description 70 GND6 GND8 72 37 GND13
2.2K_0402_5%~D
2.2K_0402_5%~D
38 GND14
1
DAA00000R0L PCB 03P LA-4051P REV0 M/B 39 GND15
MOLEX_48315-0012_RT 40 GND16
R126
R127
41 GND17
@ PCMCIA CAGE 42
2
2
GND18
6 1 EXP_SMBDATA HRS_FH28-40S-0.5SH(05)
<34,38> CARD_SMBDAT
+CBS_VPP +CBS_VCC Q112A
0.1U_0402_10V7K~D
2N7002DW-T/R7_SOT363-6
2
A A
+3.3V_SUS
@ EXPRESS CAGE 1
5
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
10U_0805_10V4Z~D
Part Number Description Q112B

2N7002DW-T/R7_SOT363-6
C769
3 4 EXP_SMBCLK
2 1 1 1 <34,38> CARD_SMBCLK
C541
C542
C543
@ SD CABLE 2 2 2 Compal Electronics, Inc.

DAA00000R0L PCB 03P LA-4051P REV0 M/B Close to JCBUS1 Pin18/52 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CardBus/SD card Socket
Close to JCBUS1 pin51/17 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
LA-4041P
5 4 3 2 1
5 4 3 2 1
@ FUSE1
+5V_ESATA USB PORT# DESTINATION
L0603
150U_D_6.3VM_R15M~D
1 2
0 JUSB1 (Ext Right Side Top)
0.1U_0402_16V4Z~D
+5V_ESATA
1
+5V_ALW PJP51 U29 1
PAD-OPEN 4x4m 1 8 ESATA_USB_OC# +
GND OC1# ESATA_USB_OC# <24>
1 JUSB1 (Ext Right Side Bottom)
C544
C545
2 1 +5V_ALW_FUSE 2 7
IN OUT1
3 EN1# OUT2 6
2 2
0.1U_0402_16V4Z~D
10U_1206_16V4Z~D
<37> ESATA_USB_PWR_EN# 4 EN2# OC2# 5
1 1 TPS2062ADR_SO8~D 2 JESA1 (Ext Left Side Top)

C546
C547
JESA1
1 A_VCC
USBP3_D- 2
D 2 2
+5V_CHGUSB
USBP3_D+ 3
A_D-
A_D+
3 JESA1 (Ext Left Side Bottom) D
4 A_GND
5 USB
B_VCC 4 WLAN
150U_D_6.3VM_R15M~D
0.1U_0402_16V4Z~D
USBP2_D- 6
USBP2_D+ B_D-
1 7 B_D+
1 8 B_GND
+
5 WWAN
C588
C548
9 GND
SATA_ITX_DRX_P4_C 10
+5V_CHGUSB 2 2 SATA_ITX_DRX_N4_C A+ ESATA
11 A-
12
U53
USB_OC2#
SATA_IRX_DTX_N4_C 2
C549
1SATA_IRX_DTX_N4
4700P_0402_25V7K~D
13
GND
B-
6 WPAN
1 GND OC1# 8 USB_OC2# <24> 14 B+
+5V_ALW_FUSE 2 7 SATA_IRX_DTX_P4_C 2 1SATA_IRX_DTX_P4 15
IN OUT1 C550 4700P_0402_25V7K~D GND
3 6
<37> USB_POWERSHARE_PWR_EN# 4
EN1#
EN2#
OUT2
OC2# 5 <38> EN_CELL_CHARGER_DET# C1013
1 2
1U_0402_6.3V6K~D
16 DET1
7 Express card
17 DET2
TPS2062ADR_SO8~D 2 1 +3.3V_ALW2
<37> CELL_CHARGER_DET# R927 @ 0_0402_5%~D R1040 18
100K_0402_5%~D 19
G1
G2
8 DOCKING
2 1 1 2 20 G3
21 G4
RB751S40T1_SOD523-2~D D69
TYCO_1759562-1 9 DOCKING
USBP2+ R1082 1 2 0_0402_5%~D
DLW21SN121SQ2L_4P~D
L30
<24> USBP2+
USBP2- R1083
10 USH->BIO
<24> USBP2- 1 2 0_0402_5%~D
USBP2_D+_SW 4 @ USBP2_D+
4 3 3 U54 @
USBP2_D-_SW USBP2_D-
+3.3V_SUS 8 VCC NC 7 11 Camera
1 1 2 2
USBP2_D+_SW
0.1U_0402_16V4Z~D
2 6 HSD- D- 5
C1045
C 1 2 @ 2 3 USBP2_D-_SW C
R424 0_0402_5%~D HSD+ D+
1
1 OE# GND 4
1 2 @ L29
R425 0_0402_5%~D TS3USB31RSER_QFN8_1P5X1P5~D DLW21SN121SQ2L_4P~D
1 1 FP_USB_D+
<36> FP_USBD+ 2 2
close to ICH
@ L31 4 3 FP_USB_D-
<36> FP_USBD- 4 3
DLW21SN121SQ2L_4P~D
USBP3- 1 1 USBP3_D- @ U30
<24> USBP3- 2 2 USBP2_D-
1
R422
2
0_0402_5%~D
1 GND IO2 3
1 2
USBP3+ 4 3 USBP3_D+ USBP2_D+ 2 4 +5V_CHGUSB R423 0_0402_5%~D
<24> USBP3+ 4 3 IO1 VIN
PRTR5V0U2X_SOT143-4~D
1 2 +5V_RUN +3.3V_RUN Fingerprint CONN.
0.1U_0402_16V4Z~D
R426 0_0402_5%~D @ U55
0.1U_0402_16V4Z~D
1 3 USBP3_D- JBIO1
GND IO2
1 2 1 1 +3.3V_RUN
R427 0_0402_5%~D USBP3_D+ 2 4 +5V_ESATA 1 1 2
IO1 VIN 2 FP_USB_D-
Left side USB Port 3 3
C1008
C770
PRTR5V0U2X_SOT143-4~D 4 FP_USB_D+
4
Place ESD diodes as close as USB connector. 2 2 5 5 1 2 FP_RESET# <36>
6 R443 0_0402_5%~D
JIO1 6 +5V_BIO 1 2 +5V_RUN
1 26 DETECT_GND 7
<30> SW_LAN_TX3+ 1 26 GND
2 27 8 @ R867 0_0603_5%~D
<30> SW_LAN_TX3-
3
2
3
27
28 28
AUD_EXT_MIC_L <27>
AUD_EXT_MIC_R <27>
Equalizer Selection GND
TYCO_1734242-6
<30> SW_LAN_TX2- 4 4 29 29
<30> SW_LAN_TX2+ 5 5 30 30 +VREFOUT
6 6 31 31 AUD_MIC_SWITCH <27> SEL0_ [A:B] SEL1_ [A:B] Compliance Channel
<30> SW_LAN_TX1+ 7 7 32 32 LAN_LEDACT# <30>
8 33 UPEK --> 5V U51
<30> SW_LAN_TX1- 8 33 LINK_LED10# <30>
9 34 0 0 no equalization 1 3 FP_USB_D+
9 34 LINK_LED100# <30> AUTHENTEC -->3.3V GND IO2
<30> SW_LAN_TX0- 10 10 35 35 +3.3V_SUS
11 36 +LOM_VCT FP_USB_D- 2 4
<30> SW_LAN_TX0+ 11 36 IO1 VIN +3.3V_RUN
12 37 0 1 [0:2.5dB] @ 1.6 GHz SATA_ITX_DRX_P4
B
+3.3V_LAN 13
12
13
37
38 38
USB_SIDE_EN# <37>
USB_OC0_1# <24>
* R1046 PRTR5V0U2X_SOT143-4~D
B
14 14 39 39 1 2
15 40 1 0 [2.5:4.5dB] @ 1.6 GHz 470_0402_5%~D pop U51 per 02/22 email (ESD team)
<24> USBP0+ 15 40
<24> USBP0- 16 16 41 41 ICH_AZ_MDC_BITCLK <23>
17 42 ICH_AZ_MDC_RST1# SATA_ITX_DRX_N4 @ FP FPC
17 42
<24> USBP1+ 18 18 43 43 ICH_AZ_MDC_SDOUT <23> 1 1 [4.5:6.5dB] @ 1.6 GHz Part Number Description
<24> USBP1- 19 19 44 44 ICH_AZ_MDC_SYNC <23>
20 20 45 45 ICH_AZ_MDC_SDIN1 <23> DAA00000R0L PCB 03P LA-4051P REV0 M/B
21 46 +1.8V_RUN
21 46 AUD_HP_NB_SENSE <27,28,37>
22 22 47 47
23 23 48 48 HP_SPK_L1 <28>
+5V_ALW 24 24 49 49 HP_SPK_R1 <28>
<24> IO_LOOP 25 25 50 50 1 2
0.1U_0402_16V4Z~D
10U_1206_16V4Z~D
@ R324 0_0402_5%~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
TYCO_1759898-1
C623
1 1 1 1 1 1
C1054
C490
C489
C507
C508
U72 C510 ICH_AZ_MDC_RST1#
S
<23> ICH_AZ_MDC_RST# 1 3
2 Q35
<23> ESATA_ITX_DRX_P4 2 AI+ VDD 1
3 6 2N7002W-7-F_SOT323-3~D
<23> ESATA_ITX_DRX_N4 AI- VDD
1
2 2 2 2 2 2
100K_0402_5%~D
10 +5V_ALW
G
2
VDD
<23> ESATA_IRX_DTX_P4_C 1 2 ESATA_IRX_DTX_N4 7 BO+ VDD 23
R325
C491 0.01U_0402_16V7K~D 8 28
BO- VDD
1
<23> ESATA_IRX_DTX_N4_C 1 2 ESATA_IRX_DTX_P4 AVDD 5
C504 0.01U_0402_16V7K~D 34 R326
2
+3.3V_LAN +VREFOUT R1047 0_0402_5%~D SEL0_A SATA_ITX_DRX_P4 SATA_ITX_DRX_P4_C 10K_0402_5%~D
1 2 13 SEL0_B AO+ 27 2 1
R1048 1 2 0_0402_5%~D 26 C1052 4700P_0402_25V7K~D
AO-
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 1 R1051 1 @ 2 0_0402_5%~D 33 SATA_ITX_DRX_N4 2 1 SATA_ITX_DRX_N4_C
2
R1052 @ 0_0402_5%~D SEL1_A SATA_IRX_DTX_N4_C C488 4700P_0402_25V7K~D
1 2 14 SEL1_B BI- 21 <37> MDC_RST_DIS#
C768
C634
22 SATA_IRX_DTX_P4_C
R1053 BI+
1 2 0_0402_5%~D 32 SEL2_A
2 2 R1054 1 2 0_0402_5%~D 15 SEL2_B
OUT+ 17 @ R1079 1 2 0_0402_5%~D Output Swing Control
R1055 1 2 0_0402_5%~D 31 18 @ R1080 1 2 0_0402_5%~D SEL2_ [A:B] Swing
R1056 1 2 0_0402_5%~D 16
SEL3_A
SEL3_B
OUT-
@ R1077
36 1 2 0_0402_5%~D 0 1x @ RJ11 CABLE
Place close Place close +1.8V_RUN R306 1 2 5.1K_0402_1%~D 30 EN_A
SD_A
SD_B 35 @ R1078 1 2 0_0402_5%~D * Part Number Description
R307 1 2 5.1K_0402_1%~D 29 1 1.2x
A to JIO1.13 to JIO1.30 EN_B A
R305 1 2 470_0402_5%~D 19 25
@ IREF GND @ MDC FPC
20
+3.3V_SUS +LOM_VCT GND
GND 9 Output De-emphasis AdjustmentPart Number Description
GND 4 SEL3_ [A:B] De-emphasis
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 1 +1.8V_RUN 24 DAA00000R0L PCB 03P LA-4051P REV0 M/B

R1075 AGND
1 2 0_0402_5%~D 11 0 0dB
CLKIN+ *
C711
C712
R1074 1 2 0_0402_5%~D 12 37
CLKIN- PAD
2 2 PI2EQX3201BZFE_TQFN36_6X5~D
1 -3.5dB
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT USB 2.0 PORT
Place close Place close NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
to JIO1.35 to JIO1.36 PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-4041P
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN 1 2 +15V_ALW +3.3V_ALW +3.3V_WLAN +3.3V_WLAN

@R428
@R428 0_0402_5%~D
100K_0402_5%~D
D
2.2K_0402_5%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
1 2 WLAN_RADIO_DIS#_R 6
S
<37> WLAN_RADIO_DIS#
1
100K_0402_5%~D
5 4
1
R429
R430
R432
R433
R434
D21 2
RB751S40T1_SOD523-2~D 1 Q47
R431
SI3456BDV-T1-E3_TSOP6~D
G
2
2
2
2
2
MINI_SMBCLK 1 6 CARD_SMBCLK WLAN_SMBCLK 1 6 CARD_SMBCLK
CARD_SMBCLK <32,38>
3
2N7002DW-T/R7_SOT363-6~D
4700P_0402_25V7K~D
470K_0402_5%~D
Q48A 1 Q49A
5
Q53B
2N7002DW-T/R7_SOT363-6~D @ 2N7002DW-T/R7_SOT363-6~D
R435
C551
D D
5
200K_0402_5%~D
MINI_SMBDATA 4 3 CARD_SMBDAT WLAN_SMBDATA 4 3 CARD_SMBDAT
CARD_SMBDAT <32,38>
6
Q53A 2
4
1
Q48B 2N7002DW-T/R7_SOT363-6~D @ Q49B
2
R436
2N7002DW-T/R7_SOT363-6~D 2N7002DW-T/R7_SOT363-6~D
Mini WWAN USB_MCARD2_DET# 1

@
2 PCIE_MCARD2_DET#
<38> AUX_EN_WOWL 2 Mini WLAN +3.3V_RUN
1
R740 0_0402_5%~D USB_MCARD1_DET# 1 2
2
+3.3V_RUN +3.3V_RUN R437 +3.3V_WLAN +3.3V_WLAN R438 100K_0402_5%~D
JMINI1 100K_0402_5%~D
PCIE_WAKE# 1 2 JMINI2 +1.5V_RUN +3.3V_ALW_ICH
<32,37> PCIE_WAKE# 1 2
3 4 PCIE_WAKE# 1 2
2
3 4 COEX2_WLAN_ACTIVE R440 1 2 PCIE_MCARD1_DET#
5 5 6 6 +1.5V_RUN 1 2 0_0402_5%~D 3 3 4 4 1 2
MINI1CLK_REQ# 7 8 +SIM_PWR COEX1_BT_ACTIVE R441 1 2 0_0402_5%~D 5 6 R439 100K_0402_5%~D
<6> MINI1CLK_REQ# 7 8 UIM_DATA 5 6
9 9 10 10 <6> MINI2CLK_REQ# 7 7 8 8
CLK_PCIE_MINI1# 11 12 UIM_CLK 9 10
<6> CLK_PCIE_MINI1# CLK_PCIE_MINI1 11 12 UIM_RESET 9 10
<6> CLK_PCIE_MINI1 13 13 14 14 <6> CLK_PCIE_MINI2# 11 11 12 12
15 16 UIM_VPP 13 14 USB_MCARD1_DET# 1 @ 2PCIE_MCARD1_DET#
15 16 <6> CLK_PCIE_MINI2 13 14 R741 0_0402_5%~D
17 17 18 18 15 15 16 16
19 20 WWAN_RADIO_DIS# 17 18
19 20 WWAN_RADIO_DIS# <37> 17 18
21 21 22 22 1 2 PLTRST3# PLTRST3# <22,36> 19 19 20 20 WLAN_RADIO_DIS#_R
PCIE_IRX_WANTX_N1 23 24 R442 0_0402_5%~D 21 22 2 1 PLTRST3#
<24> PCIE_IRX_WANTX_N1 PCIE_IRX_WANTX_P1 23 24 PCIE_IRX_WLANTX_N2 21 22 R444 0_0402_5%~D
<24> PCIE_IRX_WANTX_P1 25 25 26 26 <24> PCIE_IRX_WLANTX_N2 23 23 24 24
27 28 PCIE_IRX_WLANTX_P2 25 26
27 28 MINI_SMBCLK <24> PCIE_IRX_WLANTX_P2 25 26
29 29 30 30 27 27 28 28
PCIE_ITX_WANRX_N1_C 31 32 MINI_SMBDATA 29 30 WLAN_SMBCLK
<24> PCIE_ITX_WANRX_N1_C 31 32 29 30
PCIE_ITX_WANRX_P1_C 33 34 PCIE_ITX_WLANRX_N2_C 31 32 WLAN_SMBDATA
<24> PCIE_ITX_WANRX_P1_C 33 34 <24> PCIE_ITX_WLANRX_N2_C 31 32
35 36 USBP5_D- COEX2_WLAN_ACTIVE PCIE_ITX_WLANRX_P2_C 33 34
35 36 <24> PCIE_ITX_WLANRX_P2_C 33 34
PCIE_MCARD2_DET# 37 38 USBP5_D+ 35 36 USBP4_D-
<22> PCIE_MCARD2_DET# 37 38 USB_MCARD2_DET# PCIE_MCARD1_DET# 35 36 USBP4_D+
39 39 40 40 USB_MCARD2_DET# <24> 1 <24> PCIE_MCARD1_DET# 37 37 38 38
41 42 LED_WWAN_OUT# 39 40 USB_MCARD1_DET#
41 42 LED_WWAN_OUT# <42> 39 40 USB_MCARD1_DET# <24>
43 44 @ C552 41 42 WIMAX LED
C 43 44 WIMAX LED 33P_0402_50V8J~D 41 42 LED_WLAN_OUT# C
45 45 46 46 1 2 43 43 44 44 LED_WLAN_OUT# <42>
R840 0_0402_5%~D 2
47 47 48 48 <24> ICH_CL_CLK1 45 45 46 46 1 2 LED_WPAN_OUT# LED_WPAN_OUT# <42>
49 50 For WIMAX LED debug 47 48 @ R446 0_0402_5%~D
49 50 <24> ICH_CL_DATA1 47 48
51 51 52 52 <24> ICH_CL_RST1# 1 2 49 49 50 50
+3.3V_RUN R448 0_0402_5%~D 51 51 52 52 WLAN Noise
53 GND1 GND2 54
USB_MCARD2_DET# 2 1 53 54 USB_MCARD1_DET#
R447 100K_0402_5%~D +1.5V_RUN +3.3V_WLAN GND1 GND2
1
TYCO_1775861-1~D PCIE_MCARD2_DET# 2 1
+1.5V_RUN
330U_D2E_6.3VM_R25~D
+3.3V_RUN R449 100K_0402_5%~D TYCO_1775861-1~D C553
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
4.7U_0603_6.3V4Z~D
@L32
@ L32 4700P_0402_25V7K~D
DLW21SN121SQ2L_4P~D 2
1
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
33P_0402_50V8J~D
22U_0805_6.3VAM~D
33P_0402_50V8J~D
330U_D2E_6.3VM_R25~D
1 1 USBP5_D- @ L33
<24> USBP5- 2 2 1 1 1 1 1 1 1 1
33P_0402_50V8J~D
0.047U_0402_16V4Z~D
@C557
@
C554
+
1
C555
C556
C557
C558
C559
C560
C561
C562
1 1 1 1 1 DLW21SN121SQ2L_4P~D
+ 4 3 USBP5_D+ 4 USBP4_D-
1 1 <24> USBP5+ 4 3 2 2 2 2 2 2 2 2 2 <24> USBP4- 4 3 3
C564
C565
C566
C567
C568
C563
1 2 @
C569
C570
R450 0_0402_5%~D
2 2 2 2 2 2 USBP4_D+
1 2 <24> USBP4+ 1 1 2 2
2 2 R451 0_0402_5%~D
1 2
R452 0_0402_5%~D
U31 1 2
R453 0_0402_5%~D
UIM_RESET 1 6 UIM_VPP
+SIM_PWR 2 5 +SIM_PWR
WPAN Card WPAN Noise
JSIM1
1 5 +3.3V_RUN +3.3V_RUN USB_MCARD3_DET#
UIM_RESET VCC GND UIM_VPP UIM_CLK UIM_DATA @
2 RST VPP 6 3 4
B UIM_CLK UIM_DATA JMINI3 USB_MCARD3_DET# 1 B
3 CLK I/O 7 2 PCIE_MCARD3_DET# 1
1U_0603_10V4Z~D
33P_0402_50V8J~D
33P_0402_50V8J~D
33P_0402_50V8J~D
33P_0402_50V8J~D
4 8 PCIE_WAKE# 1 2 R742 0_0402_5%~D

NC NC COEX2_WLAN_ACTIVE R454 1 1 2
1 GND 9 1 1 1 1 2 0_0402_5%~D 3 3 4 4 C572
10 SRV05-4.TCT_SOT23-6~D COEX1_BT_ACTIVE R455 1 2 0_0402_5%~D 5 6 +1.5V_RUN 4700P_0402_25V7K~D
GND 5 6 2
C573
C574
C575
C576
C577
MINI3CLK_REQ# 7 8
MOLEX_475531001 <6> MINI3CLK_REQ# 7 8
9 9 10 10 1 2
2 2 2 2 2 CLK_PCIE_MINI3#
<6> CLK_PCIE_MINI3# 11 11 12 12
CLK_PCIE_MINI3 13 14 C571 4700P_0402_25V7K~D
<6> CLK_PCIE_MINI3 13 14
15 16 HOST_DEBUG_TX
15 16 HOST_DEBUG_TX <38>
HOST_DEBUG_RX 17 18
<38> HOST_DEBUG_RX MSCLK 17 18
<38> MSCLK 19 19 20 20 WPAN_RADIO_DIS# <37>
21 21 22 22 2 1 PLTRST3#
PCIE_IRX_MCARDTX_N3 23 24 R456 0_0402_5%~D +3.3V_RUN
<24> PCIE_IRX_MCARDTX_N3 PCIE_IRX_MCARDTX_P3 23 24
Primary Power Aux Power <24> PCIE_IRX_MCARDTX_P3 25 25 26 26
PWR Voltage 27 27 28 28
2
29 30 MINI_SMBCLK
Rail Tolerance Peak Normal Normal PCIE_ITX_MCARDRX_N3_C 31
29 30
32 MINI_SMBDATA R1021
<24> PCIE_ITX_MCARDRX_N3_C 31 32
PCIE_ITX_MCARDRX_P3_C 33 34 100K_0402_5%~D
<24> PCIE_ITX_MCARDRX_P3_C 33 34
35 36 USBP6_D-
PCIE_MCARD3_DET# 35 36 USBP6_D+
+3.3V +-9% 1000 750 37 38
1
<22> PCIE_MCARD3_DET# 37 38 USB_MCARD3_DET#
39 39 40 40 USB_MCARD3_DET# <24>
250 (Wake enable) +3.3V_RUN 1 2 41 42 MSDATA
41 42 MSDATA <38>
+3.3Vaux +-9% 330 250 5 (Not wake enable) R458 100K_0402_5%~D 43 44
43 44
45 45 46 46 1 2 LED_WPAN_OUT#
47 48 R459 0_0402_5%~D
+1.5V_RUN +3.3V_RUN 47 48 @ L34
+1.5V +-5% 500 375 NA 49 49 50 50
51 52 DLW21SN121SQ2L_4P~D
51 52 USBP6_D-
<24> USBP6- 1 1 2 2
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
4.7U_0603_6.3V4Z~D
53 GND1 GND2 54
1 1 1 1 1 1 1 1 4 3 USBP6_D+
<24> USBP6+ 4 3
@C580
@
TYCO_1775861-1~D
C578
C579
C580
C581
C582
C583
C584
C585
A A
1 2
R460 0_0402_5%~D
2 2 2 2 2 2 2 2
1 2
R461 0_0402_5%~D
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Mini Card
LA-4041P
5 4 3 2 1
2 1
JDOCK1
DOCK_DET_1 1 2 DOCK_AC_OFF
1 2 DOCK_AC_OFF <37,50>
<30> DOCK_LOM_SPD10LED_GRN# 3 3 4 4 DOCK_LOM_SPD100LED_ORG# <30>
<21> DPB_DOCK_CA_DET 5 5 6 6 DPC_CA_DET <21>
7 8 D22 @
D23 @ DPB_DOCK_LANE0_C 7 8 DPC_LANE_P0_C DPC_LANE_P0_C
<21> DPB_DOCK_LANE0_C 9 9 10 10 DPC_LANE_P0_C <12> 1 10 DPC_LANE_P0_C
DPB_DOCK_LANE0_C 1 10 DPB_DOCK_LANE0_C DPB_DOCK_LANE0#_C 11 12 DPC_LANE_N0_C
<21> DPB_DOCK_LANE0#_C 11 12 DPC_LANE_N0_C <12> DPC_LANE_N0_C DPC_LANE_N0_C
13 13 14 14 2 9
DPB_DOCK_LANE0#_C 2 9 DPB_DOCK_LANE0#_C DPB_DOCK_LANE1_C 15 16 DPC_LANE_P1_C
<21> DPB_DOCK_LANE1_C DPB_DOCK_LANE1#_C 15 16 DPC_LANE_N1_C DPC_LANE_P1_C <12> DPC_LANE_P1_C DPC_LANE_P1_C
<21> DPB_DOCK_LANE1#_C 17 17 18 18 DPC_LANE_N1_C <12> 4 7
DPB_DOCK_LANE1_C 4 7 DPB_DOCK_LANE1_C 19 20
DPB_DOCK_LANE2_C 19 20 DPC_LANE_P2_C DPC_LANE_N1_C DPC_LANE_N1_C
<21> DPB_DOCK_LANE2_C 21 21 22 22 DPC_LANE_P2_C <12> 5 6
DPB_DOCK_LANE1#_C 5 6 DPB_DOCK_LANE1#_C DPB_DOCK_LANE2#_C 23 24 DPC_LANE_N2_C
<21> DPB_DOCK_LANE2#_C 23 24 DPC_LANE_N2_C <12>
25 25 26 26 3
3 DPB_DOCK_LANE3_C 27 28 DPC_LANE_P3_C
<21> DPB_DOCK_LANE3_C DPB_DOCK_LANE3#_C 27 28 DPC_LANE_N3_C DPC_LANE_P3_C <12> 8
<21> DPB_DOCK_LANE3#_C 29 29 30 30 DPC_LANE_N3_C <12>
8 31 32
DPB_DOCK_AUX 31 32 DPC_AUX_DOCK RCLAMP0524P.TCT~D
<21> DPB_DOCK_AUX 33 33 34 34 DPC_AUX_DOCK <21>
RCLAMP0524P.TCT~D DPB_DOCK_AUX# 35 36 DPC_AUX#_DOCK
<21> DPB_DOCK_AUX# R1095 35 36 R1096 DPC_AUX#_DOCK <21>
37 37 38 38
1 2DOCKB_HPD 39 40 DOCKC_HPD1 2 DPC_DOCK_HPD_R D24 @
D25 @ <21> DPB_DOCK_HPD 39 40 DPC_LANE_P2_C
+NBDOCK_DC_IN_SS 0_0402_5%~D 41 41 42 42 0_0402_5%~D
ACAV_DOCK_SRC# <50> 1 10 DPC_LANE_P2_C
DPB_DOCK_LANE2_C 1 10 DPB_DOCK_LANE2_C 43 44
BLUE_DOCK 43 44 DPC_LANE_N2_C DPC_LANE_N2_C
<20> BLUE_DOCK 45 45 46 46 DAT_DDC2_DOCK <20> 2 9
DPB_DOCK_LANE2#_C 2 9 DPB_DOCK_LANE2#_C 47 48
B 47 48 CLK_DDC2_DOCK <20> B
49 50 DPC_LANE_P3_C 4 7 DPC_LANE_P3_C
DPB_DOCK_LANE3_C DPB_DOCK_LANE3_C 49 50
4 7 51 51 52 52
RED_DOCK 53 54 SATA_SBRX_DTX_P3 2 1 DPC_LANE_N3_C 5 6 DPC_LANE_N3_C
<20> RED_DOCK 53 54 SATA_SBRX_DTX_P3_C <23>
DPB_DOCK_LANE3#_C 5 6 DPB_DOCK_LANE3#_C 55 56 SATA_SBRX_DTX_N3 C586 2 1 0.01U_0402_16V7K~D
55 56 SATA_SBRX_DTX_N3_C <23>
57 58 C587 0.01U_0402_16V7K~D 3
GREEN_DOCK 57 58
3 <20> GREEN_DOCK 59 59 60 60 SATA_SBTX_C_DRX_P3 <23>
61 62 8
8 61 62 SATA_SBTX_C_DRX_N3 <23>
63 63 64 64
65 66 RCLAMP0524P.TCT~D
<20> HSYNC_DOCK 65 66 USBP8+ <24>
RCLAMP0524P.TCT~D 67 68
<20> VSYNC_DOCK 67 68 USBP8- <24>
69 69 70 70
71 72 D26 @
D27 @ <38> CLK_MSE 71 72 USBP9+ <24>
73 74 DPC_AUX_DOCK 1 10 DPC_AUX_DOCK
<38> DAT_MSE 73 74 USBP9- <24>
DPB_DOCK_AUX 1 10 DPB_DOCK_AUX 75 76
75 76 DPC_AUX#_DOCK DPC_AUX#_DOCK
<27> DAI_BCLK# 77 77 78 78 CLK_KBD <38> 2 9
DPB_DOCK_AUX# 2 9 DPB_DOCK_AUX# 79 80
<27> DAI_LRCK# 79 80 DAT_KBD <38>
81 82 DPC_DOCK_HPD_R 4 7 DPC_DOCK_HPD_R
DPB_DOCK_HPD DPB_DOCK_HPD 81 82
4 7 <27> DAI_DI 83 83 84 84
85 86 DPC_CA_DET 5 6 DPC_CA_DET
<27> DAI_DO# 85 86
DPB_DOCK_CA_DET 5 6 DPB_DOCK_CA_DET 87 88
87 88
<27> DAI_12MHZ# 89 89 90 90 3
3 91 91 92 92
93 94 8
8 93 94
95 95 96 96
97 98 RCLAMP0524P.TCT~D
<37> D_LAD0 97 98 BREATH_LED# <38,42>
RCLAMP0524P.TCT~D 99 100
<37> D_LAD1 99 100 DOCK_LOM_ACTLED_YEL# <30>
101 101 102 102 Place close to JP1 connector
<37> D_LAD2 103 103 104 104 DOCK_LOM_TRD0+ <30>
Place close to JDOCK1 connector <37> D_LAD3 105
107
105 106 106
108
DOCK_LOM_TRD0- <30>
107 108
<37> D_LFRAME# 109 109 110 110 DOCK_LOM_TRD1+ <30>
<37> D_CLKRUN# 111 111 112 112 DOCK_LOM_TRD1- <30>
113 113 114 114
<37> D_SERIRQ 115 115 116 116 TR0/1CT
<37> D_DLDRQ1# 117 117 118 118 TR2/3CT +LOM_VCT
119 119 120 120
<6> CLK_PCI_DOCK 121 121 122 122 DOCK_LOM_TRD2+ <30>
123 123 124 124 DOCK_LOM_TRD2- <30>
125 125 126 126
<38> DOCK_SMB_CLK 127 127 128 128 DOCK_LOM_TRD3+ <30>
<38> DOCK_SMB_DAT 129 129 130 130 DOCK_LOM_TRD3- <30>
131 131 132 132
133 134 +3.3V_ALW
<38,43> DOCK_SMB_ALERT# 133 134 DOCK_DCIN_IS+ <48>
135 136 R1038
<43> DOCK_PSID 135 136 DOCK_DCIN_IS- <48>
137 138 100K_0402_5%~D
137 138 D70
<38> DOCK_PWR_BTN# 139 139 140 140 DOCK_POR_RST# <38> 1 2
141 142 RB751S40T1_SOD523-2~D
141 142 DOCK_DET_D#
<37,43,50> SLICE_BAT_PRES# 143 143 144 144 1 2 DOCK_DET# <21,37>
1
145 149 +DOCK_PWR_BAR CLK_PCI_DOCK
GND1 PWR2 @R1057
@ R1057 +RTC_CELL
+DOCK_PWR_BAR 146 PWR1 PWR2 150
1
147 PWR1 PWR2 151
PSOT24C-LF-T7_SOT23-3
0.1U_0603_50V4Z~D
148 152 1K_0402_5%~D @ R462
PWR1 GND2
3
2
0.1U_0603_50V4Z~D
C1009
1 DOCK_DET# 2 1 10_0402_5%~D
2
C1010
D65
1 153 159 R124 @ 100K_0402_5%~D

Shield_G Shield_G
154 160
2
Shield_G Shield_G
155 Shield_G Shield_G 161 1
2 +3.3V_RUN
156 Shield_G Shield_G 162
2 @C590
@C590
157 163
1
Shield_G Shield_G 4.7P_0402_50V8C~D

158 Shield_G Shield_G 164
2
2
R795
JAE_WD2F144WB1 20K_0402_5%~D
A A
1
DPC_DOCK_HPD# <12>
1
D
2
BSS138_SOT23~D
Q114
DPC_DOCK_HPD_R 2
G R825
S 7.5K_0402_5%~D
3
100K_0402_5%~D
1
2
0.033U_0402_16V7K~D
1
C985
R796
Close to R796 2
Its Enhance ESD on dock issue.

Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DOCKING CONN
2 1
2 1
U32C
<6> CLK_PCI_TPM +1.2V_VDDC_5880
U32A @
1
D71
RB751S40T1_SOD523-2~D
2 BCM5880
U32B
C13
BCM5880 R4
C591 1 2 680P_0402_50V7-K~D
@R464
@
4@
R4641 0_0402_5%~D
2
CLK_PCI_TPM
LPC_EN_R
M7
R6
LCLK SMC_ADD_0 H1
J4 F12
BCM5880 A7 +RFID_AVDD2P5
E5
F5
VDDC
VDDC
CORE_CINRUSH
CORE_PWRDN M5
D10 R463
1
1
2
2 2.2K_0402_5%~D
<37> SP_TPM_LPC_EN LPCEN SMC_ADD_1 +1.2V_PLL_5880 POR_AVSS HF_RFIDTAG_AVDD2P5 VDDC ALDO_PWRDN
R1050 10_0402_5%~D
2 PLTRST3#_USH N5 H2 POR_EXTR G13 F7 J11 A14 R465 4.7K_0402_5%~D
<22,34> PLTRST3# GPIO_17/LRESET_N SMC_ADD_2 POR_EXTR HF_RFIDTAG_AVDD2P5 VDDC AVDD33_LDO25
LPC_LFRAME# P5 H3 G15 C6 +RFID_AVDD1P2 K11 G12 +2.5V_AVDD_5880
<23,37,38> LPC_LFRAME# GPIO_18/LFRAME_N SMC_ADD_3 POR_INT12 HF_RFIDTAG_DVDD1P2 VDDC AVDD_2P5I
4.7U_0603_6.3V6M~D
1 2 IRQ_SERIRQ_R M6 G1 G14 E10 K6 B13
<24,31,37,38> IRQ_SERIRQ GPIO_19/LSERIRQ SMC_ADD_4 POR_MONITOR HF_RX_ADC_AVDD1P2 VDDC AVDD_2P5O
1U_0603_10V4Z~D
1U_0603_10V4Z~D
R842 0_0402_5%~D LPC_LAD0 R5 H4 F9 K7 A13 +3.3V_RUN 1 Place
<23,37,38> LPC_LAD0 GPIO_20/LAD[0] SMC_ADD_5 HF_RX_AVDD1P2 VDDC AVDD25_ldo12
LPC_LAD1 N6 F2 1 1 B14 G9 K9 B12 close
<23,37,38> LPC_LAD1 GPIO_21/LAD[1] SMC_ADD_6 PLL_VDD_1P2I HF_RX_AVDD2P5 VDDC AVDD25_ldo12
C108
LPC_LAD2 N7 G4 B15 D8 N4 E11 +1.2V_AVDD_5880 to
<23,37,38> LPC_LAD2
UART LPC
GPIO_22/LAD[2] SMC_ADD_7 PLL_AVDD_1P2O HF_TX_AVDD1P2 +3.3V_RUN VDDC AVDD_1P2O
C592
C593
LPC_LAD3 P6 G2 D12 A8 P4 E13
<23,37,38> LPC_LAD3 GPIO_23/LAD[3] SMC_ADD_8 PLL_VSS HF_TX_AVDD2P5 VDDC AVDD_1P2I_AUX 2 pinA14
1 2 LPD# P7 G3 D13 D9 +RFID_AVDD3P3 F13 +1.2V_PLL_5880
<37> SP_TPM_LPC_EN GPIO_24/LPCPD_N SMC_ADD_9 2 2 PLL_VDD_1P2I HF_TX_AVDD3P3 AVDD_1P2I_REF
@R466
@ R466 0_0402_5%~D E2 E12 E6 D14
UART_RX/GPIO0 SMC_ADD_10 PLL_VSS VDDO_VAR AVDD25_PLL
B5 GPIO_0/UART_RX SMC_ADD_11 F4 A15 NC 1 2 F6 VDDO_VAR OTP_PWR P15 +OTP_PWR 2 R829 1 +SC_PWR
UART_TX/GPIO1 B4 F1 B6 C595 0_0603_5%~D
R849 GPIO_1/UART_TX SMC_ADD_12 HF_RFIDTAG_AVSS
PAD~D T152 UART_CTS D6 F3 OVSTB N9 A6 0.01U_0402_25V7K~D G5 F11
SC_DET SC_DET_R GPIO_2/UART_CTS SMC_ADD_13 SCANMOD M8 OVSTB/ZEROB HF_RFIDTAG_VREF RFTAG_VRXN VDDO_SMC AVSS_LDO12
2 1 A4 GPIO_3/UART_RTS SMC_ADD_14 D2 PAD~D T66 SCANACCMODE HF_RFIDTAG_VRX_N C7 H5 VDDO_SMC AVSS_ldo25 C12
E3 SMC_ADD15 SBOOT P9 B7 RFTAG_VRXP J5 D11
1.5K_0402_5%~D SPI_CLK SMC_ADD_15/REFCLK_FREQ_0 SMC_ADD16 SWV SECURE_BOOT HF_RFIDTAG_VRX_P VDDO_SMC AVSS_ldo25
C5 GPIO_6/SSP_CLK SMC_ADD_16/REFCLK_FREQ_1 D1 M12 SWV/ERROR,OSC1,OSC2,SPL HF_RFIDTAG_VTX E7 AVSS_AUX C15
UART_RX/GPIO0 SPI_CS B3 E1 SMC_ADD17 TSTMOD R9 B10 K8 E15 +1.2V_VDDC_5880
GPIO_7/SSP_FSS SMC_ADD_17/BOOT_SRC_0 PAD~D T68 TESTMODE/TST_SEC_BOOT HF_RX_TEST0 VDDO_LPC AVSS_REF
@R916
@ R916 SPI_RXD D5 C2 SMC_ADD18 PAD~D T69 IDQ_EN R10 C10 L7 C14
GPIO_8/SSP_RXD SMC_ADD_18/BOOT_SR_1 IDDQ_EN/CM3_MODE HF_RX_TEST1 VDDO_LPC AVSS_PLL
RDIF
0_0402_5%~D SPI_TXD
SPI
A3 GPIO_9/SSP_TXD SMC_ADD_19 D3 HF_RX_TEST2 A11
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1 2 C1 REF_XIN F15 A12 K5 G11
SMC_ADD_20 REF_XOUT F14 REFCLK_XTALIN HF_RX_TEST3 RFREADER_RXN VDDO_33CORE VSS
SMC_ADD_21 E4 REFCLK_XTALOUT HF_RX_N C11 L5 VDDO_33CORE VSS G6
UART_TX/GPIO1 GPIO14_TER_ON/OFF C4 B1 B11 RFREADER_RXP L6 G7 2 2 2 2
BCM5880_GPIO15 GPIO_14 SMC_ADD_22 FP_RESET# <33> AUX_XIN HF_RX_P RFREADER_TXN1 VDDO_33CORE VSS
A2 GPIO_15 SMC_ADD_23 C3 PAD~D T70 D15 AUXCLK_XTALIN HF_TX_N C9 VSS G8
C596
C597
C598
C599
GPIO16_TER_TRIS D4 PAD~D T71 AUX_XOUT E14 B9 RFREADER_TXP1 L13 H10
GPIO_16 AUXCLK_XTALOUT HF_TX_P VDDO_33SC VSS
SMC_DATA_0 R2 M14 VDDO_33SC VSS H11
1 1 1 1
CLK
P3 R1070 A1 K13 H6
SMC_DATA_1 CLKOUT VDDO_SC VSS
BootStrap
R468 1 2 0_0402_5%~D USBP10-_R R13 R1 PLTRST3# 1 @ 2 B2 H7
<24> USBP10- USBD_DN SMC_DATA_2 CLKOUT_EN VSS
<24> USBP10+
R469 1 2 0_0402_5%~D USBP10+_R R14 USBD_UP SMC_DATA_3 P2 0_0402_5%~D
HF_RFIDTAG_AVSS C8 BBCLK H14 V3P3_BBLCLK VSS H8
R470 1 2 1.5K_0402_5%~D P14 R3 RST_N N8 D7 H9
GPIO_27/USBD_ATATCH SMC_DATA_4 SPI_RST R931 2 SPI_RST_R RST_N HF_RFIDTAG_AVSS R471 1 VSS
B SMC_DATA_5 M4 1 R8 RSTOUT_N HF_RFIDTAG_DVSS A5 2 H15 V3P3_PWRGOOD VSS J10 B
N2 0_0402_5%~D E9 0_0402_5%~D J12
SMC_DATA_6 HF_RX_ADC_AVSS1 +3.3V_RUN VSS
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
4.7U_0603_6.3V6M~D
FP_USBD- N11 N3 PAD~D T72 JTAG_CLK_USH P10 G10 TAMPER_N H13 J6
<33> FP_USBD- USBH_DN0 SMC_DATA_7 JTAG_TCK HF_RX_ADC_AVSS2 V3P3_TAMPER_N VSS
FP_USBD+ N12 P1 PAD~D T73 JTAG_TDI_USH R11 F10 J7
<33> FP_USBD+ USBH_UP0 SMC_DATA_8 JTAG_TDI HF_RX_AVSS VSS
JTAG
USBH_OC0# M11 M3 PAD~D T74 JTAG_TDO_USH N10 A10 +VDD_BBL H12 J8 2 2 1
USBH_OC_0 SMC_DATA_9 JTAG_TMS_USH JTAG_TDO HF_RX_AVSS VDD_BB VSS
SMC_DATA_10 M2 PAD~D T75 R12 JTAG_TMS HF_TX_AVSS A9 J13 VDD_BB VSS J9
C873
C877
C933
L4 JTAG_RST#_USH P11 B8 K10
SPI
SMC_DATA_11 PAD~D T76 JTAG_TRSTN HF_TX_AVSS VSS
TER_USBH_N1 1 R768 2 22_0402_5%~D USBH_N1 N13 N1 JTCE_USH M9 E8 +3.3V_RUN L8 K12
TER_USBH_P1 R769 2 22_0402_5%~D USBH_P1 USBH_DN1 SMC_DATA_12 @R900
@ R900 JTCE HF_TX_AVSS VESD VSS 1 1 2
1 P13 USBH_UP1 SMC_DATA_13 L3 VSS L12
USBH_OC1# R15 L2 0_0402_5%~D L9 M13
C600 USBH_OC_1 SMC_DATA_14 BCM5880KFBG_FBGA225~D VDDO_33 VSS
SMC_DATA_15 K4 1 2 L10 VDDO_33 VSS F8
680P_0402_50V7-K~D L11
@ 5880_GPIO25 VDDO_33
P8 GPIO_25/SC_SEL5V SMC_ADV_N K2
+3.3V_RUN
Smard Card
1 2 5880_GPIO26 R7 J1
GPIO_26/SC_SEL18V SMC_BLS_N_0 +3.3V_RUN +3.3V_RUN BCM5880KFBG_FBGA225~D
N15 SC_CINRUSH SMC_BLS_N_1 K1
BCM5880_SCCLK L14 J3 1 2 LPD# 1 2 BBCLK
BCM5880_SCVCC SC_CLK SMC_CRE +3.3V_RUN R474 4.7K_0402_5%~D R473 1K_0402_5%~D +1.2V_AVDD_5880 +2.5V_AVDD_5880
L15 SC_VCC SMC_CS_N_0 M1
5.1M_0402_5%~D
PAD~D T142 BCM5880_SCRST K15 K3 1 2 OVSTB 1 2 JTAG_RST#_USH
SC_RST SMC_CS_N_1
4.7K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
BCM5880_IO K14 P12 1 2 R484 4.7K_0402_5%~D R737 1K_0402_5%~D
SC_IO SMC_IO_3V
2
R476
@ R475
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
AUX1UC J14 J2 R339 1 2 TAMPER_N 1 2 SMC_ADD15
SC_FCB SMC_OE_N
R819
R844
R845
AUX2UC J15 L1 4.7K_0402_5%~D R736 4.7K_0402_5%~D R479 4.7K_0402_5%~D
BCM5880_SCDET SC_FCB_ENB SMC_WE_N
M10 SC_DET 1 2 RST_N 1 2 LPC_EN_R 2 2 2 2 2
+SC_PWR M15 R810 4.7K_0402_5%~D R489 3@ 4.7K_0402_5%~D
SC_PWR
C601
C602
C605
C606
C607
N14 1 2 SMC_ADD16
1
SC_PWR
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
R478 4.7K_0402_5%~D SMC_ADD18
2
1 1 1 1 1
1 2 REF_XOUT 2 2 POR_EXTR 2 1 SC_USB# SMC_ADD17
R481 0_0402_5%~D BCM5880KFBG_FBGA225~D R850 10K_0402_5%~D USBH_OC0#
2
C1000
C604
3.3M_0402_5%~D
1 2 FP_RESET# USBH_OC1#
+3.3V_RUN
R488
1 2 1 2 REF_XIN R483 4.7K_0402_5%~D
1 1
@
R486 10M_0402_5%~D 1 2LPC_EN_R

R487 R1058 4@ 3K_0402_5%~D +3.3V_RUN
4.7K_0402_5%~D
4.7K_0402_5%~D
Y3 0_0402_5%~D
2
XI 1 3 XO R485 Function SSMC 00 01 10 11
IN OUT
R820
@R482
@
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
4.7K_0402_5%~D
+SC_VCC +3.3V_RUN
R482
2 GND GND 4 Boot SRC AD[18:17] SMC SPI USB RVD
1 1 2 2 2 2 2 2 2 2
1
10U_0805_6.3V6M~D
27.12MHZ_12PF_1N227120CC0B~D REF CLK AD[16:15] RVD 24MHZ 27.12MHz 48MHz
1
0.1U_0402_16V4Z~D
C612
C613
C614
C615
C616
C617
C618
C619
C608 C609 SBOOT
12P_0402_50V8J~D 12P_0402_50V8J~D 2 1
2
2 2 1 1 1 1 1 1 1 1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
+3.3V_RUN
C620
C706
2 2 R922
4.7K_0402_5%~D +2.5V_AVDD_5880 +1.2V_AVDD_5880 BLM18BB100SN1D_0603~D
1 2
C102
C103
BLM18BB100SN1D_0603~D BLM18BB100SN1D_0603~D 2 1 +RFID_AVDD3P3
1U_0402_6.3V6K~D
0.1U_0402_16V4Z~D
@ 2 1 +RFID_AVDD2P5 2 1 +RFID_AVDD1P2 L38
1
1 1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
0.1U_0402_16V4Z~D
1U_0402_6.3V6K~D
0.1U_0402_16V4Z~D
3.3U_0603_10V4Z~D
L36 L37
1U_0603_10V4Z~D
@ 1 2 1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
U33 1 2 SWV 2 2 1 1 2 1
C626
C630
C631
C632
VCC 19 C621
C624
C625
C627
C628
C629
GPIO14_TER_ON/OFF 24 26 4.7U_0603_6.3V6M~D C594 2 2 2 2 2 1 1
BCM5880_SCCLK ON/OFF VPC 8009_VDDMON 680P_0402_50V7-K~D 2 1 2
2 1 7 CLKIN VDD 29
1 1 2 2 1 2
C635
C636
C637
C638
C875
C106
C107
R771 1K_0402_5%~D 8 15 1 2
PAD~D T139 RDY VP +LIN
9 OFF_ACK LIN 27 2 1
PAD~D T63 L69 10UH_LQH32CN100K53L_10%~D 1 1 1 1 1 2 2
11 OFF_REQ
PAD~D T64 8009_VDDMON TER_USBH_N1
12 CS DM 23 +3.3V_RUN
GPIO16_TER_TRIS 1 2 SC_USB# 13 25 TER_USBH_P1
5880_GPIO26 R490 1 @ SC_USB# DP SC_DET D28
2 47K_0402_1%~D 4 CMDVCC5# PRES 14 R773 2 1 100K_0402_5%~D
3
5880_GPIO25 R766 1 2 47K_0402_1%~D 5 22 R491 1 2 0_0402_5%~D SC_IO BAS40-04_SOT23-3~D
BCM5880_SCRST R767 2 CMDVCC3# I/O
1 47K_0402_1%~D 6 RSTIN AUX1 21 R493 1 2 0_0402_5%~D SC_C4 @
BCM5880_SCDET R770 10K_0402_5%~D 32 20 R492 1 2 0_0402_5%~D SC_C8
OFF# AUX2 R772 1 0_0402_5%~D SC_CLK
10 TEST1 CLK 16 2
30 18 SC_RST 1
TEST2 RST
27P_0402_50V8J~D
27P_0402_50V8J~D
BCM5880_IO 1
AUX1UC I/OUC 100NH_LLQ1608-FR10G_2%~D
2 AUX1UC GND 17 2 2
AUX2UC 3 28 SC_C4 & SC_C8 is for 90 ohm
AUX2UC GND C639 L71
C633
C104
31 R494
GND RFREADER_RXN
33 1 2 1 2RFREADER_TXN1 1 2
2
Therm_GND 1 1 CLK_PCI_TPM
+SC_VCC
150P_0402_50V8J~D
73S8009CN 3K_0402_1%~D
1U_0603_10V6K~D
1
10_0402_5%~D
68P_0402_50V8J~D
1 1 RFREADER_TXN1_PI
R744
JCS1
0.47U_0402_6.3V6K
A A
C1056
When using the 73S8009C,no-stuff R768,R769,R490 RFTAG_VRXN 1 2 1 2 ANT_RFTAG_VRXN_R 1 1
C641
+3.3V_RUN R496 4.12K_0402_1%~D C640 1U_1206_100V4Z~D 2
When using the 73S8009CN,stuff R768,R769,R490 2
2
2 2
1U_0603_10V4Z~D
C611
RFTAG_VRXP 1 2 1 2 ANT_RFTAG_VRXP_R 3
PCI_TPM_TERM 2
R497 4.12K_0402_1%~D C642 1U_1206_100V4Z~D 3

4 4
1 RFREADER_TXP1_PI 5 7
1
JSC1 5 G1
6 6 G2 8
C644
12 GND +3.3V_RUN
11 TYCO_1-1775784-0_6P-T
GND 2 <24> CONTACTLESS_DET#
10 100NH_LLQ1608-FR10G_2%~D
SC_RST 10 U34
9 9 C643 L72
3
SC_CLK SPI_TXD SPI_RXD R498
4.7P_0402_50V8C~D
8 8 1 D Q 8
BAS40-04_SOT23-3~D
SC_C4 7 SPI_CLK 2 7 2 RFREADER_RXP 1 2 1 2RFREADER_TXP1 1 2
7 SPI_RST C VSS
6 6 3 RESET# VCC 6
150P_0402_50V8J~D
68P_0402_50V8J~D
C589
5 SPI_CS 4 5 BCM5880_GPIO15 3K_0402_1%~D

SC_IO 5 S# W# 1U_0603_10V6K~D
4 4 1 1 1
1
D29
SC_C8 3 M45PE16-VMP6TP_SO8~D
3
C647
C1057
SC_DET 2 2
1 1 2 2 @
1 R915 2 BCM5880_GPIO15 1 2
+3.3V_RUN TYCO_1-1734821-0_10P-T R341 @ 4.7K_0402_5%~D
2
300_0402_5%~D SC_DET 1 2
@
R913 100K_0402_5%~D TPM Disable: Depop D71, R1058, Pop R489

Title
@ SMART CARD CAGE PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT USH I/F
2 1
5 4 3 2 1
+3.3V_ALW
2 1 CELL_CHARGER_DET#
R925 100K_0402_5%~D
1 2 PCIE_WAKE# +3.3V_ALW
R501 10K_0402_5%~D +3.3V_RUN
1 2 SLICE_BAT_PRES#
R503 4.7K_0402_5%~D 1 2 WIRELESS_ON#/OFF
1 2 DCIN_CBL_DET# R870 @ 100K_0402_5%~D 1 1 1 1
R871 100K_0402_5%~D 1 2 SP_TPM_LPC_EN 1
1 2 PWR_BTN_BD_DET# R788 @ 10K_0402_5%~D C648 C649 C650 C651
R872 100K_0402_5%~D 0.1U_0402_16V4Z~D C652 0.1U_0402_10V7K~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
2 0.1U_0402_16V4Z~D 2 2 2
2
D D
108
34
57
85
U35
VCC1
VCC1
VCC1
VCC1
PBAT_PRES# 97 +3.3V_ALW +3.3V_ALW
<43> PBAT_PRES# GPIOA[0]
SCRL_LED# 98
<42> SCRL_LED# GPIOA[1]
1 2 LCD_TST <42> NUM_LED#
NUM_LED# 99 GPIOA[2] VCC1(VDDA33) 8
0.1U_0402_16V4Z~D
R816 100K_0402_5%~D DCIN_CBL_DET# 100 14 DOCK_MIC_DET INSTANT_ON_SW_D# 1 2
<43> DCIN_CBL_DET# GPIOA[3] GPIOJ[7](VDDA33) DOCK_MIC_DET <27>
2 1 PANEL_BKEN_MCH <50> PBATT_OFF PBATT_OFF 101 GPIOA[4] GPIOK[4](VDDA33) 20 MCH_TSATN_EC <10>
@R20
@ R20 100K_0402_5%~D
R505 100K_0402_5%~D MDC_RST_DIS# 102 1 SNIFFER_BLUE# 2 1
1 2 SYS_LED_MASK#
<33> MDC_RST_DIS#
<32,34> PCIE_WAKE#
PCIE_WAKE# 103
GPIOA[5]
GPIOA[6]
ECE5028-NU GPIOI[1](VCC1) 119 1.8V_RUN_ON T81 PAD~D @ R507 100K_0402_5%~D
C653
R669 10K_0402_5%~D USB_POWERSHARE_PWR_EN# 104 SNIFFER_YELLOW# 2 1
<33> USB_POWERSHARE_PWR_EN# GPIOA[7]
9 SNIFFER_BLUE# @R508
@ R508 100K_0402_5%~D
<31> WIRELESS_ON#/OFF
WIRELESS_ON#/OFF
WPAN_RADIO_DIS#
24
25
GPIOH[0]
(ECE5018) GPIOJ[2](USBDP0)
GPIOJ[3](USBDN0) 10
13
SNIFFER_YELLOW#
DOCK_HP_DET
SNIFFER_BLUE# <42>
SNIFFER_YELLOW# <42>
2 TP_DET#
R756
2 1
100K_0402_5%~D
<34> WPAN_RADIO_DIS# GPIOH[1] GPIOJ[6](USBDP1) DOCK_HP_DET <27>
EXPRCRD_PWREN# 26 12 CRT_SWITCH CRT_SWITCH <20>
<32> EXPRCRD_PWREN# GPIOH[4] GPIOJ[5](USBDN1)
EXPRCRD_STDBY# 27 15 ME_FWP ME_FWP <23> +3.3V_RUN
<32> EXPRCRD_STDBY# GPIOH[5] GPIOK[0](USBDP2)
BC_INT#_ECE5028 58 16 NB_AC_OFF
+3.3V_ALW2 <38> BC_INT#_ECE5028
<38> BC_DAT_ECE5028
BC_DAT_ECE5028 59
BC_INT#
BC_DAT
USB GPIOK[1](USBDN2)
GPIOK[3](USBDP3) 19 DP_PRIORITY
NB_AC_OFF <43,48,50>
DP_PRIORITY <21>
BC_CLK_ECE5028 60 18 2.5V_RUN_PWRGD D_CLKRUN# 2 1
<38> BC_CLK_ECE5028 BC_CLK GPIOK[2](USBDN3) 2.5V_RUN_PWRGD <18,41>
21 RUN_ON R510 100K_0402_5%~D
GPIOK[5](USBDP4) RUN_ON <19,28,40,41>
1 2 USB_SIDE_EN# 1 GPIOE[0]/RXD GPIOK[6](USBDN4) 22 1.5V_RUN_ON
1.5V_RUN_ON <45>
D_SERIRQ 2 1
R502 10K_0402_5%~D 2 R511 100K_0402_5%~D
GPIOE[1]/TXD
1 2 ESATA_USB_PWR_EN# 3 GPIOE[2]/RTS# GPIOI[6](VDDA33PLL) 125 1 2 IMVP_VR_ON <47>
D_DLDRQ1# 2 1
R504 10K_0402_5%~D 4 124 R509 0_0402_5%~D R512 100K_0402_5%~D
GPIOE[3]/DSR# GPIOI[5](VDDA18PLL) IMVP_PWRGD <24,41,47,49> C657
1 2 USB_POWERSHARE_PWR_EN# <32> EXPRCRD_DET#
EXPRCRD_DET# 5 GPIOE[4]/CTS# GPIOI[2](VDD18) 120 0.9V_DDR_VTT_ON
0.9V_DDR_VTT_ON <46>
R928 100K_0402_5%~D 84 86 +CAP_LDO 8mil 1 2 RUN_ON 2 1
BIOS_RECOVERY GPIOE[5]/DTR# CAP_LDO DP_MB_EN R515 100K_0402_5%~D
PAD~D T151 83 GPIOE[6]/RI# GPIOJ[0](RBIAS) 127 DP_MB_EN <21>
6 4.7U_0603_6.3V4Z~D 1.5V_RUN_ON
2 1
GPIOE[7]/DCD# +3.3V_ALW C672 R516 100K_0402_5%~D
C USB_SIDE_EN# R514 0.1U_0402_16V4Z~D 1.05V_RUN_ON C
<33> USB_SIDE_EN# 65 GPIOB[0]/INIT# 2 1
EN_I2S_NB_CODEC 66 1K_0402_5%~D 1 2 R518 100K_0402_5%~D
<27> EN_I2S_NB_CODEC GPIOB[1]/SLCTIN#
CB_HWSPND# 67 35 2 1 3.3V_RUN_ON 2 1
<31> CB_HWSPND# GPIOC[2]/SCLT TEST_PIN
5
EN_DOCK_PWR_BAR 68 D72 R519 100K_0402_5%~D
<50> EN_DOCK_PWR_BAR
ADAPT_OC 69
GPIOC[3]/PE
GPIO TEST DOCK_AC_OFF_EC 1 RB751S40T1_SOD523-2~D 0.9V_DDR_VTT_ON 2 1
P
<48> ADAPT_OC GPIOC[4]/BUSY IN1
70 4 2 1 R520 100K_0402_5%~D
LCD_TST GPIOC[5]/ACK# O DOCK_AC_OFF <35,50>
PBATT_OFF
<19> LCD_TST 71 GPIOC[6]/ERROR# GPIOI[7](ATEST) 126 <38,48> ACAV_IN_NB 2 IN2 2 1
1
PSID_DISABLE# 73 R521 100K_0402_5%~D
<43> PSID_DISABLE# PANEL_BKEN_MCH GPIOC[7]/ALF# VGA_IDENTIFY
<12> PANEL_BKEN_MCH 74 123 SIO_SLP_S3# <24> 1 @ 2 R1071 1 2
3
DOCKED GPIOD[0]/STROBE# GPIOI[4](XTAL1/CLKIN) 3.3V_RUN_ON U69 R1072 0_0402_5%~D 33K_0402_5%~D R522 100K_0402_5%~D
75 122
<29,30> DOCKED
<21,35> DOCK_DET#
DOCK_DET# 76
GPIOC[1]/PD7
GPIOC[0]/PD6
CLK GPIOI[3](XTAL2) 3.3V_RUN_ON <40>
AUD_NB_MUTE 77 74AHC1G08GW_SOT353-5~D
2
<28> AUD_NB_MUTE CELL_CHARGER_DET# GPIOB[7]/PD5
<33> CELL_CHARGER_DET# 78 GPIOB[6]/PD4 LPC_LAD[0..3] <23,36,38>
LCD_VCC_TEST_EN 79 54 LPC_LAD0
<19> LCD_VCC_TEST_EN GPIOB[5]/PD3 LAD0
CCD_OFF 80 52 LPC_LAD1
<19> CCD_OFF GPIOB[4]/PD2 LAD1
AUD_HP_NB_SENSE 81 49 LPC_LAD2
<27,28,33> AUD_HP_NB_SENSE GPIOB[3]/PD1 LAD2
ESATA_USB_PWR_EN# 82 47 LPC_LAD3
<33> ESATA_USB_PWR_EN# GPIOB[2]/PD0 LAD3
42 LPC_LFRAME#
LFRAME# LPC_LFRAME# <23,36,38>
LID_CL_SIO# 61 41 PLTRST2#
<40> 1.05V_RUN_ON
1.05V_RUN_ON 62
GPIOD[1]
GPIOD[2]
LPC LRESET#
PCICLK 56 CLK_PCI_5028
PLTRST2# <22,38>
CLK_PCI_5028 <6>
37 CLKRUN#
CLKRUN# CLKRUN# <24,31,38>
63 46 LPC_LDRQ0#
GPIOD[3]/VBUS_DET LDRQ0# LPC_LDRQ0# <23>
INSTANT_ON_SW_D# 28 44 LPC_LDRQ1#
GPIOD[4]/OCS1_N LDRQ1# LPC_LDRQ1# <23>
29 39 IRQ_SERIRQ
GPIOD[5]/OCS2_N SER_IRQ IRQ_SERIRQ <24,31,36,38>
HDDC_EN 30
<26> HDDC_EN GPIOD[6]/OCS3_N
MODC_EN 31 64 CLK_SIO_14M
<26> MODC_EN GPIOD[7]/OCS4_N CLKI (14.318 MHz) CLK_SIO_14M <6>
+3.3V_RUN CLK_SIO_14M CLK_PCI_5028
SLICE_BAT_PRES# 32 96
<35,43,50> SLICE_BAT_PRES# GPIOH[6] VSS
PWR_BTN_BD_DET# 33
<31> PWR_BTN_BD_DET# GPIOH[7]
1
55 D_LAD0
LAN_DISABLE#_R DLAD0 D_LAD1 D_LAD0 <35> R648 @R506
@ R506 R527
<29> LAN_DISABLE#_R 88 GPIOG[0] DLAD1 53 D_LAD1 <35>
CAP_LED# 89 50 D_LAD2 10K_0402_5%~D 10_0402_5%~D 10_0402_5%~D
B <42> CAP_LED# SYS_LED_MASK# GPIOG[1] DLAD2 D_LAD3 D_LAD2 <35> B
<42> SYS_LED_MASK# 90 GPIOG[2] DLPC DLAD3 48 D_LAD3 <35>
91 43 D_LFRAME#
D_LFRAME# <35>
2
R526 1 GPIOG[3] DLFRAME#
<24> SIO_EXT_WAKE# 2 0_0402_5%~D 92 GPIOG[4] DCLK_RUN# 38 D_CLKRUN#
D_CLKRUN# <35>
ME_FWP
ICH_PME# 93 45 D_DLDRQ1# 1 1
<22> ICH_PME# GPIOG[5] DLDRQ1# D_DLDRQ1# <35>
2
ICH_PCIE_WAKE# 94 40 D_SERIRQ
<24> ICH_PCIE_WAKE# GPIOG[6] DSER_IRQ D_SERIRQ <35>
WLAN_RADIO_DIS# 95 @ R649 @C654
@ C654 C656
<34> WLAN_RADIO_DIS# GPIOG[7]
10K_0402_5%~D 4.7P_0402_50V8C~D 4.7P_0402_50V8C~D
WWAN_RADIO_DIS# 2 2
<34> WWAN_RADIO_DIS# 106 SYSOPT1/GPIOH[2]
107
1
SYSOPT0/GPIOH[3] RUNPWROK
PWRGD 7 RUNPWROK <38,41,47>
109 GPIOF[7]
@ 110 105 SP_TPM_LPC_EN
D4 GPIOF[6] OUT65 SP_TPM_LPC_EN <36>
VGA_IDENTIFY 111
INSTANT_ON_SW# INSTANT_ON_SW_D# CHIPSET_ID1 GPIOF[5]
<31,38> INSTANT_ON_SW# 1 2 112 GPIOF[4]
R528 11 GPIO_PSID_SELECT
10K_0402_5%~D GPIOJ[4](VSS) GPIO_PSID_SELECT <43> +3.3V_ALW
113 IRTX VSS 17
RB751S40T1_SOD523-2~D 2 1 114 23
IRRX GPIOK[7](VSS) SPI_WP#_SEL <24>
VSS 36
1 2 CHIPSET_ID0 115 51
GPIOF[3]/IRMODE/IRRX3B VSS
1
R1036 BID2 116 72
0_0402_5%~D BID1 GPIOF[2]/IRTX2 VSS R524
117 GPIOF[1]/IRRX2 VSS 87
BID0 118 121 1M_0402_5%~D
GPIOF[0]/IRMODE/IRRX3A VSS
GPIOJ[1](VSS) 128
R525
2
10_0402_5%~D
+3.3V_ALW TP_DET# <39>
ECE5028-NU_VTQFP128_14X14~D LID_CL_SIO# 2 1 LID_CL#
LID_CL# <31,42>
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
2
@ 1
@ R532
@ R533
R529
R530
R531
C655
BID2 BID1 BID0 REV CHIPSET_ID0 CHIPSET_ID1 Note 0.047U_0402_16V4Z~D
2
1
A A
0 0 0 X00 0 0
BID0 1 2
@ R534 10K_0402_5%~D 0 0 1 X01 0 0
BID1 1
R535
2
10K_0402_5%~D 0 1 0 X02 DELL CONFIDENTIAL/PROPRIETARY
BID2 1 2
@ R536 10K_0402_5%~D 0 1 1 X03 Compal Electronics, Inc.
CHIPSET_ID0 1 2
R537 10K_0402_5%~D 1 0 0 X04 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Title
CHIPSET_ID1 1 2
R538 10K_0402_5%~D 1 0 1 A00 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ECE5028
LA-4041P
5 4 3 2 1
5 4 3 2 1
+RTC_CELL
1
R539
100K_0402_5%~D 1 2
@ C658
2
+3.3V_ALW 1U_0402_6.3V6K~D
POWER_SW_IN# 1 2
<18> POWER_SW_IN# POWER_SW#_MB <31,39>
1 2 CKG_SMBDAT 1 R541 1K_0402_5%~D
R540 2.2K_0402_5%~D
1 2 CKG_SMBCLK +RTC_CELL +3.3V_ALW C659
R542 2.2K_0402_5%~D 1U_0603_10V4Z~D
BC_DAT_ECE5028 +RTC_CELL_VBAT 2
1 2 1 2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
R543 100K_0402_5%~D R544 1
D 2 1 BC_DAT_EMC4002 0_0402_5%~D D
R545 100K_0402_5%~D C660
1 1 1 1 1 1 1 1
C661
2 1 BC_DAT_ECE1077 0.1U_0402_16V4Z~D
2
C662
C663
C664
C665
C666
C667
C668
R546 100K_0402_5%~D +RTC_CELL
2 1 DOCK_SMB_ALERT#
R547 10K_0402_5%~D 2 2 2 2 2 2 2 2
1
1 2 LCD_SMBCLK
121
116
104
R548 2.2K_0402_5%~D
21
44
65
83
52
4
1 2 LCD_SMBDAT U36 1 2
R549 2.2K_0402_5%~D R550
VTR[1]
VTR[2]
VTR[3]
VTR[4]
VTR[5]
VTR[6]
VTR[7]
VTR[8]
VBAT
1 2 PBAT_SMBDAT 100K_0402_5%~D @ C669
2
R551 2.2K_0402_5%~D 1U_0402_6.3V6K~D
1 2 PBAT_SMBCLK DOCK_PWR_SW# 1 2
<18> DOCK_PWR_SW# DOCK_PWR_BTN# <35>
R552 2.2K_0402_5%~D PS/2 INTERFACE MISC INTERFACE 1 R554 1K_0402_5%~D
2 1 LPC_LDRQ#_MEC5035 9 GPIO007/I2C1D_DATA/PS2_CLK0B GPIO021/RC_ID 19 RC_ID +RTC_CELL
@ R837 100K_0402_5%~D 10 27 DDR_ON
GPIO010/I2C1D_CLK/PS2_DAT0B GPIO025/UART_CLK DDR_ON <46>
1 2 CARD_SMBDAT CLK_TP_SIO 75 49 RUNPWROK
<39> CLK_TP_SIO GPIO110/PS2_CLK2/GPTP-IN6 VCC_PRWGD RUNPWROK <37,41,47> 2 C670
R838 2.2K_0402_5%~D DAT_TP_SIO 76 50 ICH_LAN_RST# ICH_LAN_RST# <24> INSTANT_ON_SW# @ 2 R560 1 100K_0402_5%~D
<39> DAT_TP_SIO GPIO111/PS2_DAT2/GPTP-OUT6 GPIO060/KBRST
1 2 CARD_SMBCLK CLK_KBD 77 67 1U_0603_10V4Z~D
<35> CLK_KBD GPIO112/PS2_CLK1A GPIO101/ECGP_SCLK
R839 2.2K_0402_5%~D DAT_KBD 78 68 SNIFFER_PWR_SW# 1 R562 2 100K_0402_5%~D
<35> DAT_KBD GPIO113/PS2_DAT1A GPIO102/ECGP_SOUT
2 1 HOST_DEBUG_TX CLK_MSE 79 69
<35> CLK_MSE GPIO114/PS2_CLK0A GPIO103/ECGP_SIN
R879 10K_0402_5%~D DAT_MSE 80 70 HOST_DEBUG_TX EN_CELL_CHARGER_DET# 2 R876 1 200K_0402_5%~D
<35> DAT_MSE GPIO115/PS2_DAT0A GPIO104/UART_TX HOST_DEBUG_TX <34>
PBAT_SMBDAT 111 71 HOST_DEBUG_RX
<43> PBAT_SMBDAT GPIO154/I2C1C_DATA/PS2_CLK1B GPIO105/UART_RX HOST_DEBUG_RX <34>
PBAT_SMBCLK 112 72 RESET_OUT# +3.3V_ALW 2 1
<43> PBAT_SMBCLK GPIO155/I2C1C_CLK/PS2_DAT1B GPIO106/nRESET_OUT RESET_OUT# <41>
81 MSDATA D68 RB751S40T1_SOD523-2~D
GPIO116/MSDATA MSDATA <34>
82 MSCLK
GPIO117/MSCLK MSCLK <34>
92 SIO_A20GATE SNIFFER/INSTANT_SW# 1 R921 2 100K_0402_5%~D
GPIO127/A20M SIO_A20GATE <23>
2
JTAG INTERFACE 110 PS_ID @ +3.3V_ALW
GPIO153/LED3 PS_ID <43>
JTAG_TDI 102 114 BAT1_LED# Bat2 = Amber LED R578
GPIO145/I2C1K_DATA/JTAG_TDI GPIO156/LED1 BAT1_LED# <42>
JTAG_TDO 103 115 BAT2_LED# Bat1 = Blue LED 10K_0402_5%~D INSTANT_ON_SW# 1 R933 2 100K_0402_5%~D
GPIO146/I2C1K_CLK/JTAG_TDO GPIO157/LED2 BAT2_LED# <42>
JTAG_CLK 105 123 FWP#
JTAG_TMS GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK nFWP DOCK_SMB_DAT
106 20mA drive pins 2 R565 1 2.2K_0402_5%~D
1
JTAG_RST# GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS
107 JTAG_RST# FWP# DOCK_SMB_CLK 2 R567 1 2.2K_0402_5%~D
2 1 M_ON GENERAL PURPOSE I/O
R561 1M_0402_5%~D 2 SIO_SLP_M#
GPIO001 SIO_SLP_M# <24>
2
1 2 AUX_ON FAN PWM & TACH 3 DOCK_SMB_ALERT# +5V_RUN
R563 2.7K_0402_5%~D DOCK_POR_RST# GPIO002 ME_WOL_EN DOCK_SMB_ALERT# <35,43> @ R586
C <35> DOCK_POR_RST# 41 GPIO050/FAN_TACH1 GPIO014/GPTP-IN7 14 ME_WOL_EN <24> C
1 2 DDR_ON SUS_ON 42 15 ME_SUS_PWR_ACK 10K_0402_5%~D CLK_KBD 2 R569 1 4.7K_0402_5%~D
<40,41> SUS_ON GPIO051/FAN_TACH2 GPIO015/GPTP-OUT7 ME_SUS_PWR_ACK <24>
R564 100K_0402_5%~D 43 16 1.8V_SUS_PWRGD
GPIO052/FAN_TACH3 GPIO016/GPTP-IN8 1.8V_SUS_PWRGD <46>
1 2 SUS_ON BREATH_LED# 45 17 ICH_CL_PWROK DAT_KBD 2 R570 1 4.7K_0402_5%~D
<35,42> BREATH_LED# ICH_CL_PWROK <10,24>
1
R566 100K_0402_5%~D ICH_ALW_ON GPIO053/PWM0 GPIO017/GPTP-OUT8 3.3V_LAN_PWRGD
<40> ICH_ALW_ON 46 GPIO054/PWM1 GPIO020 18 3.3V_LAN_PWRGD <41>
1 2 ICH_ALW_ON KYBRD_BKLT_PWM 47 28 1.05V_M_PWRGD CLK_MSE 2 R571 1 4.7K_0402_5%~D
<39> KYBRD_BKLT_PWM GPIO055/PWM2 GPIO26/GPTP-IN1 1.05V_M_PWRGD <45>
R568 100K_0402_5%~D C1055 48 29 ALW_PWRGD_3V_5V
GPIO056/PWM3 GPIO27/GPTP-OUT1 ALW_PWRGD_3V_5V <44>
2 1 DOCK_POR_RST# 1 2 30 SUSPWROK DAT_MSE 2 R572 1 4.7K_0402_5%~D
GPIO30/GPTP-IN2 SUSPWROK <41>
R1059 1M_0402_5%~D 31 SIO_SLP_S5#
GPIO31/GPTP-OUT2 SIO_SLP_S5# <24>
0.1U_0402_16V4Z~D 32 BEEP AC_PRESENT 1 R573 2 10K_0402_5%~D
GPIO032/GPTP-IN3 BEEP <27>
BC-LINK 33 AUX_ON +3.3V_ALW
GPIO040/GPTP-OUT3 AUX_ON <40>
BC_CLK_EMC4002 23 34
<18> BC_CLK_EMC4002 GPIO022/BCM_B_CLK/V_CLK GPIO041 ODD_DET# <24,26>
<18> BC_DAT_EMC4002 BC_DAT_EMC4002 24 73 +3.3V_ALW
GPIO023/BCM_B_DAT/V_DATA GPIO107 3.3V_M_PWRGD <18,41>
2
<18> BC_INT#_EMC4002 BC_INT#_EMC4002 25 84
+3.3V_ALW GPIO024/BCM_B_INT#/V_FRAME GPIO120 AUX_EN_WOWL <34> R266
35 GPIO042/BCM_C_INT# GPIO124/GPTP-OUT5 89 SIO_SLP_S4# <24>
2
36 90 M_ON 1K_0402_5%~D
GPIO043/BCM_C_DAT GPIO125/GPTP-IN5 M_ON <40,45>
37 91 ICH_RSMRST# R579
GPIO044/BCM_C_CLK GPIO126 ICH_RSMRST# <24>
100K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
<39> BC_INT#_ECE1077 BC_INT#_ECE1077 38 108 AC_PRESENT 10K_0402_5%~D

AC_PRESENT <24>
1
GPIO045/LSBCM_D_INT# GPIO151/GPTP-IN4
1
<39> BC_DAT_ECE1077 BC_DAT_ECE1077 39 109 SIO_PWRBTN# RC_ID

GPIO046/LSBCM_D_DAT GPIO152/GPTP-OUT4 SIO_PWRBTN# <24>
R574
4700P_0402_25V7K~D
BC_CLK_ECE1077 40 1=JTAG interface Reset disabled
1
<39> BC_CLK_ECE1077 GPIO047/LSBCM_D_CLK
R575
R576
BC_INT#_ECE5028 85 0=Reset JTAG interface

<37> BC_INT#_ECE5028 GPIO121/BCM_A_INT#
@ BC_DAT_ECE5028 86 1 JTAG_RST#
<37> BC_DAT_ECE5028 GPIO122/BCM_A_DAT
BC_CLK_ECE5028 87 SMBUS INTERFACE
<37> BC_CLK_ECE5028
2
GPIO123/BCM_A_CLK
C480
100_0402_1%~D
JDEG1 DOCK_SMB_DAT
0.1U_0402_16V7K~D
GPIO003/I2C1A_DATA 5 DOCK_SMB_DAT <35> 1
1
DOCK_SMB_CLK
5 5 GPIO004/I2C1A_CLK 6 DOCK_SMB_CLK <35> 2
C80
MSDATA LCD_SMBDAT
4 4 GPIO005/I2C1B_DATA 7 LCD_SMBDAT <19>
1
R585
MSCLK HOST INTERFACE LCD_SMBCLK @
3 3 HOST_DEBUG_RX SIO_EXT_SMI# GPIO006/I2C1B_CLK 8
CKG_SMBDAT
LCD_SMBCLK <19> 2
2 2 1 2 11 12
1
<24> SIO_EXT_SMI# GPIO011/nSMI GPIO012/I2C1H_DATA/I2C2D_DATA CKG_SMBDAT <6,27,48>
R577 0_0402_5%~D SIO_RCIN# CKG_SMBCLK
1 1 54 13 CKG_SMBCLK <6,27,48>
2
<23> SIO_RCIN# LPC_LDRQ#_MEC5035 GPIO061/LPCPD# GPIO013/I2C1H_CLK/I2C2D_CLK
55 LDRQ# GPIO130/I2C2A_DATA 93 AMT_SMBDAT <24>
Molex_53261 IRQ_SERIRQ 56 94
<24,31,36,37> IRQ_SERIRQ SER_IRQ GPIO131/I2C2A_CLK AMT_SMBCLK <24>
PLTRST2# 57 95 ACAV_IN_NB
+3.3V_ALW <22,37> PLTRST2# LRESET# GPIO132/I2C1G_DATA ACAV_IN_NB <37,48>
CLK_PCI_5035 58 96
<6> CLK_PCI_5035 PCI_CLK GPIO140/I2C1G_CLK
LPC_LFRAME# 59 97 CARD_SMBDAT
<23,36,37> LPC_LFRAME# LFRAME# GPIO141/I2C1F_DATA/I2C2B_DATA CARD_SMBDAT <32,34>
2
LPC_LAD0 60 98 CARD_SMBCLK
<23,36,37> LPC_LAD0 LAD0 GPIO142/I2C1F_CLK/I2C2B_CLK CARD_SMBCLK <32,34>
LPC_LAD1 61 99 +RTC_CELL
<23,36,37> LPC_LAD1
2
LAD1 GPIO143/I2C1E_DATA
10K_0402_5%~D
49.9_0402_1%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
LPC_LAD2 62 100 EC_JTAG_RST_PAD1

<23,36,37> LPC_LAD2 LAD2 GPIO144/I2C1E_CLK
1
B LPC_LAD3 63 1 2 B
<23,36,37> LPC_LAD3 LAD3
R580
R581
R582
R583
CLKRUN# @ @SHORT PADS~D

R584
<24,31,37> CLKRUN# 64 CLKRUN#

SIO_EXT_SCI# 66 C100 0.1U_0402_16V4Z~D
<24> SIO_EXT_SCI# GPIO100/nEC_SCI
5
DELL PWR SW INF
118 1 SNIFFER_PWR_SW#
P
SNIFFER_PWR_SW# <31>
2
@ JTAG1 BGPO0 SNIFFER/INSTANT_SW# IN1

VCI_IN2# 119 4 O
1 MASTER CLOCK 120 ALWON 2 INSTANT_ON_SW#
1 VCI_OUT ALWON <44> IN2 INSTANT_ON_SW# <31,37>
G
2 JTAG_TDI MEC5035_XTAL1 122 126 EN_CELL_CHARGER_DET#
2 XTAL1 VCI_IN1# EN_CELL_CHARGER_DET# <33>
7 3 JTAG_TMS MEC5035_XTAL2 2 1 124 127 POWER_SW_IN# 74AHC1G08GW_SOT353-5~D
3
G1 3 JTAG_CLK R587 0_0402_5%~D XTAL2 VCI_IN0# ACAV_IN
8 G2 4 4 117 GPIO160/32KHZ_OUT VCI_OVRD_IN 128 ACAV_IN <18,48> U57 @
JTAG_TDO DOCK_PWR_SW#
thermal GND
5 5 <18> EC_32KHZ_OUT VCI_IN3# 1

VR_CAP[1]
6 6
VSS_RO
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[7]
VSS[8]
AGND
ACES_85204-06001~D
2 1
R445 0_0402_5%~D
MEC5035_XVTQFP128_14X14~D
125
26
51
74
88
113
20
53
22
4.7U_0603_6.3V4Z~D +5035_VSS 101
129
1+5035_AGND
Place closely pin 58

32 KHz Clock
+VR_CAP
15mil
15mil
Same as Laguna CLK_PCI_5035

1
MEC5035_XTAL1
R588
8mil
10_0402_5%~D 1 1 2
C671
L39 L40
Y4 BLM18AG121SN1D_0603~D BLM18AG121SN1D_0603~D
2
32.768K_12.5P_1TJS125DJ4A420P~D 1
MEC5035_XTAL2 2
4 1
C673
2
3 2 4.7P_0402_50V8C~D
2
22P_0402_50V8J~D
22P_0402_50V8J~D
1 1
C674
C675
2 2
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, EMC5035
LA-4041P
5 4 3 2 1
5 4 3 2 1
+5V_ALW +5V_RUN
4.7K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
1
1
@ @
R1093
R1094
R594
R595
2
2
TP_CLK L41
D TP_DATA TP_DATA DAT_TP_SIO D
1 2 DAT_TP_SIO <38>
SD05.TCT_SOD323-2~D
SD05.TCT_SOD323-2~D
BLM18AG601SN1D_0603~D
TP_CLK 1 2 CLK_TP_SIO
CLK_TP_SIO <38>
1
L42
10P_0402_50V8J~D
10P_0402_50V8J~D
@ @ BLM18AG601SN1D_0603~D
10P_0402_50V8J~D
10P_0402_50V8J~D
1 1 1 1
D53
D54
C680
C681
C682
C683
2
2
2 2 2 2
Place close to JTP1 connector
C C
JTP1 Close to JTP1 Power Switch for debug

1 1
<38> BC_DAT_ECE1077 2 2
3 +5V_RUN +3.3V_RUN
<38> BC_CLK_ECE1077 3
<38> BC_INT#_ECE1077 4 4
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
+3.3V_ALW 5 5
6 1 1 POWER_SW#_MB 1 2
6 <31,38> POWER_SW#_MB 1 2
7 7
C678
C679
TP_CLK 8 1
TP_DATA 8
9 9 2 2 @ C684
10 10
11 100P_0402_50V8J~D PWR_SW1
+5V_RUN 11 2
+5V_ALW 12 @SHORT PADS~D
12
+3.3V_RUN 13 13 Place on Top
B 14 14 B
KYBRD_BKLT_PWM 15
<38> KYBRD_BKLT_PWM 15 +3.3V_ALW
TP_DET# 16
<37> TP_DET# 16
0.1U_0402_16V4Z~D
17 G1
18 G2 1 1 1 2 2
C771
2
TYCO_1-1775737-6 PWR_SW2
@SHORT PADS~D
Place on Bottom
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Touch PAD/Int KB/LID
LA-4041P
5 4 3 2 1
5 4 3 2 1
DC/DC Interface +3.3V_ALW_ICH Source

+15V_ALW +3.3V_ALW Q54 +3.3V_ALW_ICH +5VRUN Source
SI3456BDV-T1-E3_TSOP6~D
+3.3V_ALW2 +15V_ALW +5V_ALW Q55
D
+3.3V_ALW2 6 STS11NF30L_SO8~D +5V_RUN
S
1
5 4 8 1
1
10U_0805_10V4Z~D
R598 2 7 2
10U_0805_10V4Z~D
100K_0402_5%~D 1 1 R597 6 3
1
100K_0402_5%~D 5 1
C687
R602 R601 R599 R600
C686
100K_0402_5%~D ALW_ENABLE 20K_0402_5%~D 100K_0402_5%~D 20K_0402_5%~D
4
2 RUN_ENABLE
2
3
D 2 D
2
2
3
Q57B
2200P_0402_50V7K~D
2N7002DW-T/R7_SOT363-6~D 1 Q56B
ALW_ON_3.3V# 5 2N7002DW-T/R7_SOT363-6~D
C688 RUN_ON_5V# 5 1
6
3300P_0402_50V7K~D
4
2
C689
Q57A
4
2N7002DW-T/R7_SOT363-6~D
6
2
<38> ICH_ALW_ON 2
Q56A
2N7002DW-T/R7_SOT363-6~D
1
2
+15V_ALW +3.3V_SUS Source <19,28,37,41> RUN_ON
+3.3V_ALW
+3.3V_RUN Source
1
Q60 +3.3V_SUS
1
STS11NF30L_SO8~D
R603 8 1 NTMS4107NR2G_SO8~D
+3.3V_ALW2 100K_0402_5%~D 7 2 Q61 +3.3V_RUN
6 3 +3.3V_ALW2 +15V_ALW +3.3V_ALW
1
20K_0402_5%~D
5 1 8 1
2
10U_0805_10V4Z~D
R605
7 2
1
1
C690
20K_0402_5%~D
6 3 1
R607
10U_0805_10V4Z~D
R604 SUS_ENABLE 5
2
C691
100K_0402_5%~D R606
2
3
100K_0402_5%~D
4
1
Q62B 2
2
2
2N7002DW-T/R7_SOT363-6~D R608
SUS_ON_3.3V# 5 1 100K_0402_5%~D 1 2
@ D30
@D30
6
3
C692 RB751V_SOD323-2~D
4
2
Q62A 4700P_0402_25V7K~D 1 2 1
2 R609
2N7002DW-T/R7_SOT363-6~D
C RUN_ON_3V# 0_0402_5%~D C693 C
<38,41> SUS_ON 2 5
Q64B 470P_0402_50V7K~D
6
2N7002DW-T/R7_SOT363-6~D 2
1
4
Q64A
2N7002DW-T/R7_SOT363-6~D
2
+3.3VM Source Discharge Circuit <37> 3.3V_RUN_ON
1
+3.3V_ALW Q66 +1.05V_M +3.3V_M
+15V_ALW SI3456BDV-T1-E3_TSOP6~D +3.3V_M
+1.05V_VCCP Source
100K_0402_5%~D
1K_0402_5%~D
+3.3V_ALW2
1
D
75_0603_5%~D
@ R616
6
S
1
NTMS4107NR2G_SO8~D
@R615
@
5 4
R610
10U_0805_10V4Z~D
R615
2 Q67 +1.05V_VCCP
1
1
20K_0402_5%~D
1 1 +3.3V_ALW2 +15V_ALW +1.05V_M

R612
R611 8 1
G
2
C694
100K_0402_5%~D 7 2
2
1
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
20K_0402_5%~D
M_ENABLE 6 3 1
1
2 D D
R614
10U_0805_10V4Z~D
5
2
2
3
@ Q71
@ Q72
C695
M_ON_3.3V# 2 2 R613
Q68B G G 100K_0402_5%~D
4
S S 2
2N7002DW-T/R7_SOT363-6~D
2
1
M_ON_3.3V# 5 1
R617 1 2
6
C696 100K_0402_5%~D @D31

@ D31
4
3
Q68A 4700P_0402_25V7K~D RB751V_SOD323-2~D
2
2N7002DW-T/R7_SOT363-6~D 1 2 1
2
2 R618
<38,45> M_ON
RUN_ON_1.05V# 5 0_0402_5%~D C697
Q70B 470P_0402_50V7K~D
1
6
2N7002DW-T/R7_SOT363-6~D 2
4
Q70A
B B
2N7002DW-T/R7_SOT363-6~D
<37> 1.05V_RUN_ON 2
1
+15V_ALW
+3.3V_ALW2 Discharge Circuit

1
R619 +5V_RUN +1.5V_RUN +0.9V_DDR_VTT +3.3V_RUN +1.05V_VCCP

100K_0402_5%~D +3.3V_SUS +3.3V_ALW_ICH
39_0402_5%~D
1
1
1K_0402_5%~D
1K_0402_5%~D
1K_0402_5%~D
1K_0402_5%~D
1K_0402_5%~D
1K_0402_5%~D
2
R625
R620
@ R622
@ R623
@ R624
@ R626
ENAB_3VLAN <29>
@R627
@
@R628
@
100K_0402_5%~D
3
1
2N7002DW-T/R7_SOT363-6~D
R627
R628
1
@ R621
2
2
Q74B
C698 470K_0402_5%~D
2
2
N21917830 5 4700P_0402_25V7K~D
1
1
2 D D D D D
200K_0402_5%~D
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
2N7002W-7-F_SOT323-3~D
2
6
D D
2N7002DW-T/R7_SOT363-6~D
@ Q81
@ Q82
@ Q76
@ Q77
@ Q78
@ Q80
@ RUN_ON_5V# 2 2 2 RUN_ON_3V# 2 RUN_ON_1.05V# 2
4
R629
Q79
SUS_ON_3.3V# 2 ALW_ON_3.3V# 2 G G G G G
Q74A
G G S S S S S
3
<38> AUX_ON 2 S S
2
3
1
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, POWER CONTROL
LA-4041P
5 4 3 2 1
5 4 3 2 1
+3.3V_SUS +3.3V_ALW C699

0.1U_0402_16V4Z~D
100K_0402_5%~D 0.1U_0402_16V4Z~D
<18,37> 2.5V_RUN_PWRGD 2 @ 1 1 2
1
R630 0_0402_5%~D
<45> 1.5V_RUN_PWRGD 2 1 +3.3V_ALW
R632
R631 0_0402_5%~D
8
+5V_ALW
P
+5V_RUN 1 7 6 2 +3.3V_ALW C700
R633 A Y A Y 0.1U_0402_16V4Z~D
G
E
10K_0402_5%~D Q83 1 U39A U39B 1 2
B
2 1 1 2 2 MMBT3906WT1G_SC70-3~D 74LVC3G14DC_VSSOP8~D 74LVC3G14DC_VSSOP8~D
4
C701
D D
1
200K_0402_5%~D
C
D32
14
1 1
1
RB751V_SOD323-2~D R635 2 U40A
1
R634
C702 C703 4.7K_0402_5%~D C 1 74VHC08MTCX_NL_TSSOP14~D
P
0.1U_0402_16V4Z~D 2200P_0402_50V7K~D Q84 IN1
1 2 2 OUT 3
2 2 B MMST3904-7-F_SOT323-3~D <19,28,37,40> RUN_ON 1 2 2
2
IN2
G
E R636 +3.3V_ALW
3
0_0402_5%~D
14
U40B
4 74VHC08MTCX_NL_TSSOP14~D
P
IN1 RUNPWROK
OUT 6 RUNPWROK <37,38,47>
+3.3V_ALW 5 IN2
G
+3.3V_RUN
7
3
E
Q85
2 1 1 2
B
2 MMBT3906WT1G_SC70-3~D
R637
1
200K_0402_5%~D
C
1 D33 1 10K_0402_5%~D
1
RB751V_SOD323-2~D R639
1
R638
C704 C705 4.7K_0402_5%~D C +3.3V_ALW

0.1U_0402_16V4Z~D 2200P_0402_50V7K~D 1 2 2 Q86
2 2 B MMST3904-7-F_SOT323-3~D
14
2
3
10
P
<38,40> SUS_ON IN1
OUT 8 SUSPWROK <38>
3.3V_5V_SUS_PWRGD 9
IN2
G
U40C
7
+3.3V_ALW
+3.3V_SUS
D34 R641 +3.3V_ALW
3
C
E C
RB751V_SOD323-2~D 10K_0402_5%~D B
2 1 1 2 2 Q88
200K_0402_5%~D
2200P_0402_50V7K~D
MMBT3906WT1G_SC70-3~D
1
8
C
1 1 D35 +3.3V_M
1
R642
C708
RB751V_SOD323-2~D
P
C707 2 1 3 5
A Y
1
200K_0402_5%~D
0.1U_0402_16V4Z~D
1
G
2 2 U39C R640
2
R643
74LVC3G14DC_VSSOP8~D 100K_0402_5%~D
4
+3.3V_ALW
2
ICH_PWRGD# ICH_PWRGD# <18>
2
14
1
IMVP_PWRGD D
13
P
<24,37,47,49> IMVP_PWRGD IN1
11 ICH_PWRGD 2 Q87
RESET_OUT# OUT G 2N7002W-7-F_SOT323-3~D
<38> RESET_OUT# 12 IN2
G
U40D S
3
7
IO board ICH_PWRGD <10,24>
H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13

@H_3P0 @H_3P0 @H_3P0 @H_3P0 @H_3P0 @H_3P0 @H_3P0 @H_3P0 @H_3P0 @H_3P0 @H_3P0 @H_3P0 @H_3P0
1
+3.3V_ALW +3.3V_ALW
+3.3V_M
B D36 R644 B
3
E
RB751V_SOD323-2~D 10K_0402_5%~D B
2 1 1 2 2 Q89
200K_0402_5%~D
2200P_0402_50V7K~D
MMBT3906WT1G_SC70-3~D
8
C
1 1
P
R645
C710
C709 2 1 1 7 3.3V_M_PWRGD <18,38>
A Y
200K_0402_5%~D
0.1U_0402_16V4Z~D
G
2 2 D37 U41A
2
RB751V_SOD323-2~D 74LVC3G14DC_VSSOP8~D
EMI CLIP
4
R646
H18 H19 H16 H17 H14 H15 H20 H21 H24
@H_4P2 @H_3P8 @H_4P2 @H_3P9 @H_5P3 @H_5P3 @H_2P2 H_3P75 H_6P1 CLIP1
2
EMI_CLIP
1
1
GND +3.3V_ALW +3.3V_ALW

+3.3V_LAN C713
CLIP2 D40 R651 0.1U_0402_16V4Z~D
3
E
H25 EMI_CLIP RB751V_SOD323-2~D 10K_0402_5%~D
B 1 2
H_5P0 Q91
CPU x 4 eDOCK x 2 2 1 1 2 2
200K_0402_5%~D
2200P_0402_50V7K~D
@ 1 MMBT3906WT1G_SC70-3~D
GND
8
C
1 1
P
1
R652
C715
C714 2 1 6 2 3.3V_LAN_PWRGD <38>
A Y
200K_0402_5%~D
0.1U_0402_16V4Z~D
G
2 2 D41 U41B
2
RB751V_SOD323-2~D 74LVC3G14DC_VSSOP8~D
4
R653
2
A @ FD1 @ FD2 A
1 1
FIDUCIAL MARK~D FIDUCIAL MARK~D
@ FD3 @ FD4 DELL CONFIDENTIAL/PROPRIETARY

1 1
FIDUCIAL MARK~D FIDUCIAL MARK~D Compal Electronics, Inc.

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Sequence & ME Part
LA-4041P
5 4 3 2 1
5 4 3 2 1
+5V_ALW
DDTA114EUA-7-F_SOT323-3~D
+5V_ALW
R995
+3.3V_ALW 1 2
Q143
2N7002DW-T/R7_SOT363-6~D
1
100K_0402_5%~D Q145B +5V_ALW
R656
2N7002DW-T/R7_SOT363-6~D
4 3 2 100K_0402_5%~D
ON MB
3
+3.3V_ALW
Q145A
Battery LED
2
Q99
5
+3.3V_ALW DDTA114EUA-7-F_SOT323-3~D
2N7002DW-T/R7_SOT363-6~D
2 MASK_BASE_LEDS# 2 Q90
1
5
1
1 R997 2BREATH_BLUE_LED_IO BREATH_BLUE_LED_IO <31>
6
Q159A
100_0402_5%~D +5V_ALW D49 2N7002W-7-F_SOT323-3~D
NC
1
2 4 LED 2.3mA BLUE
<35,38> BREATH_LED# A Y
LED 19mA
S
2 1 1 3
NC
G +5V_ALW
U42 2 4 2
<38> BAT2_LED#
1
A Y
1
1 2 BATT_BLUE_LED
R998
3
G
D NC7SZ04P5X_NL_SC70-5~D U43 R658 R665 1K_0402_5%~D D
4 3
G
1
2
+3.3V_ALW 1 2 100K_0402_5%~D
3
3
Q147
NC7SZ04P5X_NL_SC70-5~D +5V_ALW YEL
100K_0402_5%~D Q144B LTST-C155TBJSKT_Blue/YEL~D
2
2N7002DW-T/R7_SOT363-6~D
2N7002DW-T/R7_SOT363-6~D
4 3 2 Q161A
3
2N7002DW-T/R7_SOT363-6~D
2N7002DW-T/R7_SOT363-6~D MASK_BASE_LEDS#
Q103
6
Q160A
5
Q144A
1 62
SYS_LED_MASK#
1
2 1 2BREATH_BLUE_LED_LCD BREATH_BLUE_LED_LCD <19> 2
R1000 1K_0402_5%~D
2
1
1
LED 2.3mA
1
SYS_LED_MASK#
BATT_BLUE_ON_LCD
+3.3V_RUN
LED 2.3mA
+5V_RUN +3.3V_ALW
1
R654
10K_0402_5%~D HDD LED solution for Blue LED
1
+3.3V_ALW
R671
2
3
2N7002DW-7-F_SOT363-6~D 100K_0402_5%~D
Q156B Q92
3
2
4 3 2 Q101
<23> SATA_ACT#_R +3.3V_ALW DDTA114EUA-7-F_SOT323-3~D
2N7002DW-T/R7_SOT363-6~D
2
Q159B
5
3
+3.3V_ALW
1
1
MASK_BASE_LEDS#
NC
1 2 SATA_LED 2 1 <38> BAT1_LED# 2 4 5
1
A Y
1
R659 1K_0402_5%~D 1 2 BATT_YELLOW_LED
G
D42 U44 R664 R666 150_0402_5%~D
4
LED 2.3mA LTST-C191TBKT-5A BLU_0603~D 100K_0402_5%~D
3
C NC7SZ04P5X_NL_SC70-5~D +3.3V_ALW C
2
Q161B
3
+3.3V_WLAN +5V_RUN
2N7002DW-T/R7_SOT363-6~D
Q160B
2N7002DW-T/R7_SOT363-6~D Q104
3
1
4 32
WLAN LED solution for Blue LED
ON LCD
3
R662 2N7002DW-7-F_SOT363-6~D 5
Q156A Q97
5
100K_0402_5%~D DDTA114EUA-7-F_SOT323-3~D 1 2 BATT_BLUE_LED_LCD <19>
2
4
1 6 1 2 2 R689 1K_0402_5%~D
<34> LED_WLAN_OUT#
1
SYS_LED_MASK#
D67 BATT_YELLOW_ON_LCD 1 2 BATT_YELLOW_LED_LCD <19>
SDM10U45-7_SOD523-2~D R690 150_0402_5%~D
2
MASK_BASE_LEDS# LTST-C191TBKT-5A BLU_0603~D

1
1 2 WLAN_LED 2 1
R663 1K_0402_5%~D +5V_ALW
D45
LED 2.3mA
3
<37> CAP_LED# 2
+3.3V_RUN
+5V_RUN Q120
Keyboard Status
3
1
WWAN LED solution for Blue LED
1
3
R206 2N7002DW-7-F_SOT363-6~D 2 1 2 R_CAP_LED# 2 1 +3.3V_RUN C1014 +5V_ALW

<37> NUM_LED#
Q158B Q115 R556 1K_0402_5%~D 0.1U_0402_25V4Z~D
100K_0402_5%~D DDTA114EUA-7-F_SOT323-3~D Q121 D57
2
3
4 3 2 DDTA114EUA-7-F_SOT323-3~D LTST-C191TBKT-5A BLU_0603~D @ 1 2 +PWR_SRC +3.3V_ALW
<34> LED_WWAN_OUT#
C1020
0.1U_0402_25V4Z~D
1
2 1 2 R_NUM_LED# 2 1 C1015 @ 1 2
<37> SCRL_LED#
5
R596 1K_0402_5%~D 0.1U_0402_25V4Z~D

MASK_BASE_LEDS# Q122 D58
1
B B
1 2 WWAN_LED 2 1 DDTA114EUA-7-F_SOT323-3~D LTST-C191TBKT-5A BLU_0603~D @ 1 2
R125 1K_0402_5%~D
D61 1
LED 2.3mA LTST-C191TBKT-5A BLU_0603~D 1 2 R_SCRL_LED# 2 1
R655 1K_0402_5%~D
D59
LTST-C191TBKT-5A BLU_0603~D +3.3V_LAN C1017 +3.3V_ALW
+3.3V_RUN 0.1U_0402_25V4Z~D
EMI Caps
1
+5V_RUN D
0_0402_5%~D
LED 2.3mA ALL
10K_0402_5%~D
@ R1039
MASK_BASE_LEDS# 2 @ 1 2
WPAN LED solution for Blue LED
2
G
R660
Q150 S
3
2N7002W-7-F_SOT323-3~D +3.3V_ALW C1018 +5V_ALW
2
3
0.1U_0402_25V4Z~D
Q158A Q94
1
2N7002DW-7-F_SOT363-6~D DDTA114EUA-7-F_SOT323-3~D @ 1 2
<34> LED_WPAN_OUT# 1 6 2
+3.3V_RUN +5V_RUN
2
C1021
1
MASK_BASE_LEDS# LTST-C191TBKT-5A BLU_0603~D 0.1U_0402_25V4Z~D

D43 @
1 2 WPAN_LED 2 1 LED Circuit Control Table 1 2
R661 1K_0402_5%~D LED 2.3mA C1022

0.1U_0402_25V4Z~D
SYS_LED_MASK# LID_CL# @ 1 2
+3.3V_ALW
Mask All LEDs (Sniffer Function) 0 X

Mask Base MB LEDs (Lid Closed) 1 0
3
@
Do not Mask LEDs (Lid Opened) 1 1
<37> SNIFFER_YELLOW# 2
Q100 +3.3V_ALW
1
A A
5
LID_CL# 1
P
+5V_ALW <31,37> LID_CL# IN1

4 MASK_BASE_LEDS#
SYS_LED_MASK# O
<37> SYS_LED_MASK# 2 IN2
G
SNIFFER LED
3
74AHC1G08GW_SOT353-5~D
3
Q102 U65
<37> SNIFFER_BLUE# 2
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Compal Electronics, Inc.
1 @ 2 SNIFFER_YELLOW BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Title
SNIFFER_YELLOW <31> NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
R667 220_0402_5%~D
LED
1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

1 2 SNIFFER_BLUE Size Document Number Rev
SNIFFER_BLUE <31>
R668 1K_0402_5%~D 1.0
LED 2.3mA LA-4041P
5 4 3 2 1
5 4 3 2 1
+COINCELL
COIN RTC Battery
1
PR1
1K_0402_5%~D JRTC1
+COINCELL 1 1
+3.3V_RTC_LDO 2 4
2
2 G1
3 3 G2 5
Z4012
MOLEX_53398-0371~D
D D
+3.3V_ALW
3
ESD Diodes +RTC_CELL
PD1
1
3
2
BAT54CW_SOT323~D
1
PL1 +3.3V_ALW
FBMA-L18-453215-900LMA90T_1812~D PC1
1 2 1U_0603_10V6K~D
2
Primary Battery Connector PD2 PD3 PD4 PD5
1
@ DA204U_SOT323~D @ DA204U_SOT323~D @ DA204U_SOT323~D @ DA204U_SOT323~D Move to power schematic @ RTC BATTERY
1
10K_0402_1%~D
PJP1 Part Number Description
1 2 PBATT+
PR2
0.1U_0603_25V7K~D
1
FOX_BP02093-P5652-7F~D PAD-OPEN 4x4m
PC2
11 9 PR3
2
GND 9 100_0402_5%~D PR4
10 8
2
GND 8 Z4304 100_0402_5%~D PR5
2200P_0402_50V7K~D
7 7 1 2 PBAT_SMBCLK <38>
6 Z4305 1 2 100_0402_5%~D
6 PBAT_SMBDAT <38>
5 Z4306 1 2 PR6 @
5 PBAT_PRES# <37>
1
PC3
4 100_0402_5%~D
4 PBAT_ALARM#
3 3 1 2
2
2
2
1 1
PBATT1 PQ61
FDN338P_SOT23-3~D
3
1 2 1 3 DOCK_SMB_ALERT# <35,38>
PD32
2
2
C RB751V-40_SOD323~D C
<35,37,50> SLICE_BAT_PRES#
1500P_0402_7K~D
1
PC257
2
+5V_ALW +3.3V_ALW
DA204U_SOT323~D
2
PD6
@ PR7 PU1
2.2K_0402_5%~D
2
1 2 <35> DOCK_PSID 1 NO IN 6 GPIO_PSID_SELECT <37>
0_0402_5%~D
PR8
2 GND V+ 5 +5V_ALW
PL2 PR9
1
BLM18BD102SN1D_0603~D 33_0402_5%~D
NB_PSID NB_PSID_TS5A63157
S
2 1 1 3 1 2 3 NC COM 4 PS_ID <38>
100K_0402_1%~D PQ1 TS5A63157DCKR_SC70-6~D
2
2 FDV301N_SOT23~D +5V_ALW
G
2
PR10
+3.3V_ALW +5V_ALW
DA204U_SOT323~D
2
PD8
10K_0402_1%~D
1
1
@ C
1
PR11
PD7 PQ2
DA204U_SOT323~D
2
SM24_SOT23 B MMST3904-7-F_SOT323~D @
B E B
15K_0402_1%~D
3
3
2
PD17
1
PR12
PR13
@ 1 2
PSID_DISABLE# <37>
1
@ 10K_0402_5%~D
1
PR221
0_0402_5%~D
1 2 DCIN_CBL_DET# <37>
0.47U_0402_6.3V6K
1
PC254
PQ3
DC_IN+ Source
2
+DC_IN FDS6679AZ_SO8~D +DC_IN_SS

@
1 8
2 7
PL3 3 6
FBMJ4516HS720NT_1806~D 5
1 2 +DC_IN
1M_0402_5%~D
0.022U_0805_50V7K
1
VZ0603M260APT_0603
10U_1206_25V6M~D
4.7K_0805_5%~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
4
1
PC4
PR14
PQ4B
1
PD9
1
1
IMD2AT-108_SC74-6~D
PC6
PC7
PC8
PC9
PR15
0.1U_0603_25V7K~D
2
1
@
0.1U_0603_25V7K~D
3 4
2
1
PC5
1M_0402_5%
PJPDC1
1
2
PC10
0_0402_5%~D
22K_0402_5%~D
1
2
1
1
PR17
2 2
PR18
3 -DCIN_JACK
2
3
PR16
4 @
4
5
2
5 +DCIN_JACK PL4 @
A 6 A
2
6 FBMJ4516HS720NT_1806~D
7 7
1 2
MOLEX_87437-0763
1
PQ4A
0.1U_0603_25V7K~D
RHU002N06_SOT323
1
IMD2AT-108_SC74-6~D PR342
1
D 100K_0402_5%~D
PQ5
PC11
5 2 1 2
2
<50> NB_AC_OFF_BJT G NB_AC_OFF <37,48,50>

S
3
PC12
0.1U_0603_25V7K~D Title
6
@ DC-IN cable
+DCIN
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
CONN SET 03N DCJACK-MB DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.5
DC301003B0L
WDMD-DCJAL201-DF MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-4041P
5 4 3 2 1
5 4 3 2 1
+3.3V_ALWP/ +5V_ALWP/ +5V_ALW2 / +15V_ALWP
+DC1_PWR_SRC
D D
PJP2
+PWR_SRC 1 2
PAD-OPEN 4x4m
VOUT1=5V
2
0_0805_5%
0_0805_5%
PJP3 +5V_VCC1
L=3.0uH
2200P_0402_50V7K~D
0.1U_0805_50V7K
+5V_ALW2 1 2
PR19
PR20
Fsw=400KHz
2200P_0402_50V7K~D
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
@ PR21
0.1U_0805_50V7K
D=?
1
PAD-OPEN1x1m 10_0603_5%~D
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
1
1
1
Output Ripple Current=?A
PC18
PC19
PC20
PC21
PC22
4.7U_0805_6.3V6K
2 1
PC13
PC14
PC15
PC16
PC17
Output Ripple Voltage=?A*25mOhm=?mV)
2
2
1
Input Ripple Current=TDC*(D*(1-D))^0.5=3.28A
PC23
+3.3V_ALW2
2
Component select
1U_0603_25V6-K~D
Input CAP 10uF_1206_25V *2
1U_0603_10V6K~D
Output Cap 330uF_D3L_6.3VM_R25(Sanyo_6TPE330ML)
1
PC24
PR22
1U_0603_10V6K~D
1
PC25
H_MOSFET FDS8880 @ 0_0402_5%~D
1
PC26
1 2
L_MOSFET FDS6676AS(5.9/7.25mOhm@4.5V, 14.5A)
2
Inductor 4.7U_HMU1356-4R7-R_10A(DELTA) @ PR23
2
0_0402_5%~D
1 2
EN_3V_5V
PC27
0.1U_0603_25V7K~D
1
GNDA_3V5V 1 2 GNDA_3V5V 0_0402_5%~D
5 Volt +/-5% 1 2 PR25 3.3 Volt +/-5%
Thermal Design Current:5.99A Thermal Design Current: 7.80A
0.1U_0402_10V7K~D
@ PR24
0.1U_0402_10V7K~D
2
8
7
6
5
PC29
Peck current: 8.56A 0_0603_5%~D @ PR26 Peak current: 11.15A
8
7
6
5
4
3
2
1
5
6
7
8
PQ6 GNDA_3V5V PU2 2 1
D
D
D
D
1
+5V_ALWP
OCP min: 10.3A FDS8880_NL_SO8~D OCP min: 13A
PC28
PQ7
V5FILT
LDO
VREF3
EN_LDO
TONSEL
VREF2
LDOREFIN
VIN
D
D
D
D
C 0_0402_5%~D @ FDS8880_NL_SO8~D C
2
2
4 @ PR27
G 158K_0402_1%
9 VSW REFIN2 32 4 G
+5V_ALWP PR28 10 31 1 2 GNDA_3V5V
GNDA_3V5V VOUT1 TRIP2
S
S
S
137K_0402_1% 11 30
VFB1 VOUT2
S
S
S
PR209 1 2 12 29 2 PR29 0_0402_5%~D
1 +3.3V_ALWP
1
2
3
0_0402_5%~D ALW_PWRGD_3V_5V TRIP1 SKIPSEL POK2

13 28
3
2
1
PL5 PGOOD1 PGOOD2 PL6
2 1 14 EN1 EN2 27 2 1 EN_3V_5V
3.0UH_HMP1362-3R0-R_17A_20%~D +5V_ALW_UGATE 15 26 +3.3V_ALW_UGATE PR210 0_0402_5%~D 3.0UH_HMP1362-3R0-R_17A_20%~D
+5V_ALW_PHASE DRVH1 DRVH2 +3.3V_ALW_PHASE
2 1 16 LL1 LL2 25 2 1
0_0603_5%~D
1000P_0603_50V7K~N
1000P_0603_50V7K~D
0.1U_0603_25V7K~D
EN_3V_5V
V5DRV
SECFB
DRVL1
DRVL2
VBST1
VBST2
2
8
7
6
5
PGND
0_0402_5%~D
GNDA_3V5V
0.1U_0603_25V7K~D
GND
PAD
NC
NC
5
6
7
8
1
PR30
PQ8
220U_V_6.3VM_R25M~D
220U_V_6.3VM_R25M~D
330U_D3L_6.3VM_R25~D
1
PC198
PC199
PR31
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
1
PC30
PC31
1 FDS6676AS_NL_SO8~D SN0608098_QFN32_5X5~D 1 1
33
17
18
19
20
21
22
23
24
@ PQ9
1
2
1
1
+ + +
PC32
PC33
PC34
PC35
PC195
4 GNDA_3V5V FDS6676AS_NL_SO8~D
2
4.7_1206_5%~D
4.7_1206_5%~D
4
2
2
PR32 PR33
2
2
2 2 2
PR211
PR212
2.2_0402_5%~D 2.2_0402_5%~D
0_0603_5%~D
0_0402_5%~D
1 2 +5V_ALW_BOOT +3.3V_ALW_BOOT1 2
1
2
3
2
1
3
2
1
PR35
+5V_ALW_LGATE +3.3V_ALW_LGATE
1
1
PR34
@
1
2
GNDA_3V5V
GNDA_3V5V
GNDA_3V5V PC36 PJP4
4.7U_0603_6.3V6K~D
1
+5V_ALWP 2 0.1U_0603_25V7K~D 1 2 VOUT2=3.3V
+3.3V_ALW +3.3V_ALW
PC37
1 1 2
L=3.0uH
+5V_ALW2
0.1U_0603_25V7K~D
2
PAD-OPEN1x1m Fsw=300KHz
D=?
1
B B
PD10 GNDA_3V5V
200K_0402_1%~D
200K_0402_1%~D
PC38
BAT54SW-7-F_SOT323-3~D Output Ripple Current=?A
2
Output Ripple Voltage=?A*25mOhm=?mV
2
PR36
PR37
PC39
2 0.1U_0603_25V7K~D PD12 Input Ripple Current=TDC*(D*(1-D))^0.5=3.28A
1
1 1 2 BAT54CW_SOT323~D
3 @
1
Component select
PR38 PD11 POK2 Input CAP 10uF_1206_25V *2
2K_0402_5%~D
2 1 BAT54SW-7-F_SOT323-3~D Output Cap 220U_V_6.3VM_R25M(KEMET)
<38> ALWON
3
H_MOSFET FDS8880
0_0402_5%~D
L_MOSFET FDS6676AS(5.9/7.25mOhm@4.5V, 14.5A)
1
200K_0402_5%
2
PR41
PR39 Inductor 3.0U_HMP1362-3R0-R_17A(DELTA)
PR40
0_0402_5%~D
<18> THERM_STP# 2 1
2
1
ALW_PWRGD_3V_5V
ALW_PWRGD_3V_5V <38>
PR42
PJP5 200K_0402_1%~D
<BOM Structure> +15V_ALWP
+15V_ALW 2 1 2 1
0.1U_0603_25V7K~D
PAD-OPEN1x1m
39.2K_0402_1%~D
2
PJP34 (100mA,20mils ,Via NO.=1)

1
1 2
PC40
PR43
PAD-OPEN 4x4m
2
PJP6
+5V_ALWP 1 2 +5V_ALW
A PAD-OPEN 4x4m A
GNDA_3V5V
PJP7
+3.3V_ALWP 1 2 +3.3V_ALW
PAD-OPEN 4x4m
PJP35
1 2 Compal Electronics, Inc.
PAD-OPEN 4x4m Title
DC/DC +3V/ +5V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.5
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4041P
5 4 3 2 1
5 4 3 2 1
+1.5V_RUN / +1.05V_M/ +3.3V_RTC_LDO

+DC2_PWR_SRC
PJP8
+PWR_SRC 1 2
D D
2
10U_1206_25V6M~D
2200P_0402_50V7K~D
0_0805_5%~D
1U_0603_25V6-K~D 0_0805_5%~D
0.1U_0603_25V7K~D
PAD-OPEN 4x4m
10U_1206_25V6M~D
2200P_0402_50V7K~D
PR44
PR45
0.1U_0603_25V7K~D
1
10U_1206_25V6M~D
PC41
PC42
PC43
1
PC44
PC45
2
PC46
PC47
2
2
2
PC48
+5V_VCC2
1
+3.3V_RTC_LDO
2
PR46
0_0402_5%~D
PC49
0_0402_5%~D
0.1U_0603_25V7K~D
1.5 Volt +/-5% 1.05 Volt +/-5%
5
6
7
8
1U_0402_6.3V6K~D
REF 1 2
PR47
PQ10
Thermal Design Current: 2.42A Thermal Design Current: 7.89A
D
D
D
D
PR49 2 1 FDS6298_SO8~D
1
0_0402_5%~D
Peak current: 3.46A GNDA_1P5V_1P05V @ 0_0402_5%~D Peack current: 11.27A
PC50
1 2 @ PR51
1
PR48
OCP min: 4.3A OCP min: 13.8A
0.1U_0402_10V7K~D
0_0402_5%~D 4
2
G
1U_0603_10V6K~D
0.1U_0402_10V7K~D
SI4800BDY-T1_SO8~D
2 1
8
7
6
5
1
PR50 GNDA_1P5V_1P05V
S
S
S
PC63
@ 0_0603_5%~D
1
PC51
3
2
1
8
7
6
5
4
3
2
1
+1.05V_MP
PQ11
PC52
C PU3 PL7 C
1
GNDA_1P5V_1P05V 1.4UH_HMU1350-1R4PF_15A_20%~D
LDOREFIN
VIN
LDO
VREF3
EN_LDO
TONSEL
VREF2
V5FILT
1
4 GNDA_1P5V_1P05V
+1.5V_RUN_P 2 1
2
GNDA_1P5V_1P05V @
1000P_0603_25V7K~D
PL8 9 VSW 32 REFIN2_1_05 @
3.3UH_FDVE0640-3R3M_7A_20%~D REFIN2
10 VOUT1 31 1 2
1
2
3
3
TRIP2
0.1U_0402_10V7K~D
2 1 GNDA_1P5V_1P05V PR53 11 VFB1 30 PR52 113K_0402_1%~D GNDA_1P5V_1P05V
VOUT2
1
1000P_0603_25V7K~D
PC201
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
1 2 12 TRIP1 29 PR54 2 0_0402_5%~D
1 GNDA_1P5V_1P05V
SKIPSEL
8
7
6
5
10U_1206_6.3V7K
SI4812BDY-T1-E3_SO8~D
137K_0402_1% 1.5V_RUN_PWRGD
13 PGOOD1 28 1.05V_M_PWRGD 1 1
PGOOD2
0.1U_0402_10V7K~D
EN1 14 27 EN2
D
D
D
D
2
1.5V_UGATE 15 EN1 EN2
2
2
0_0603_5%~D
PC200
PC53
+
PC54
+
@ PC56
PC57
10U_1206_6.3V7K
330U_D2E_2.5VM_R9
26 1.05V_UGATE
1.5V_PHASE 16 DRVH1 DRVH2
4.7_1206_5%~D
1 25 1.05V_PHASE
LL1 SN0608098_QFN32_5X5~D LL2
2
PR55
4
2
1
1
2 2
PQ12
FDMS8670S_MLP8~D
PC55
+
@ PC58
PC59
PR214
0.1U_0603_25V7K~D
4
V5DRV
SECFB
DRVL1
DRVL2
VBST1
VBST2
G
PGND
PQ13
4.7_1206_5%~D
0.1U_0603_25V7K~D
GND
PAD
1
2
2
2
S
S
S
PR213
3
2
1
1
2
2
PC60
PC61
1
2
3
33
17
18
19
20
21
22
23
24
0_0603_5%~D
2
1
PR56
GNDA_1P5V_1P05V
PR57 PR58
1
@ 2.2_0402_5%~D 2.2_0402_5%~D
1 2 1 2
1.5V_LGATE GNDA_1P5V_1P05V
GNDA_1P5V_1P05V 1.05V_LGATE
B B
+5V_ALW +5V_VCC2
VOUT2=1.05V
@ PR59
10_0603_5%~D L=1.4uH
VOUT1=1.5V 2 1 Fsw=300KHz
L=4.7uF D=?
+3.3V_SUS +3.3V_ALW Output Ripple Current=?A
4.7U_0603_6.3V6K~D
Fsw=200KHz
1
D=? Output Ripple Voltage=?A*4.5mOhm=?mV

100K_0402_1%~D
100K_0402_1%~D
PC62
Output Ripple Current=?A Input Ripple Current=TDC*(D*(1-D))^0.5=2.53A

2
1

PR61
PR60
Input Ripple Current=TDC*(D*(1-D))^0.5=0.97A Component select

@
Input CAP 10uF_1206_25V*2
2
Component select Output Cap 330U_D2E_2.5VM_R9*2(Sanyo2R5TPE330M9)

Input CAP 10uF_1206_25V 1.05V_M_PWRGD
H_MOSFET FDS6298
1.05V_M_PWRGD <38>
Output Cap 330U_D2E_2.5VM_R9(Sanyo2R5TPE330M9) L_MOSFET FDS6299S
H_MOSFET SI4800BDY Inductor 1.4U_
L_MOSFET SI4810BDY(16/20mOhm@4.5V, 6A)
Inductor 4.7U_ 1.5V_RUN_PWRGD 1.5V_RUN_PWRGD <41>
PJP9
PR207 1 2
0_0402_5%~D
EN1 2 1 PAD-OPEN 4x4m
1.5V_RUN_ON <37> PJP10
@PR62
@ PR62 2 1 PJP12
PJP11 100K_0402_1%~D +1.05V_MP 1 2 +1.05V_M
+1.5V_RUN_P 1 2 +1.5V_RUN +3.3V_ALW 2 1
A PR63 PAD-OPEN1x1m PAD-OPEN 4x4m A
PAD-OPEN 4x4m 0_0402_5%~D
EN2 2 1 1 2 GNDA_1P5V_1P05V
M_ON <38,40>
PR208
0_0402_5%~D OK to Short if CAD
System can Support
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.5V_RUN / +1.05V_VCCP
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.5
LA-4041P
5 4 3 2 1
5 4 3 2 1
PL17
+1.8VSUSP/ +0.9V_DDR_VTT
MURATA_BLM18SG221TN1E_0603~D
1 2
DDR2 Termination
+DDR_PWR_SRC
PJP13
PAD-OPEN 4x4m
+PWR_SRC 1 2
D D
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
10U_1206_25V6M~D
10U_1206_25V6M~D
1 1
1
PC64
PC65
PC66
PC67
2
2
2 2
+5V_ALW
RB751V-40_SOD323~D
PD13
2
+1.8V_SUSP
1.8 Volt +/-5%
Thermal Design Current: 6.94A
8
7
6
5
1
12
1
7
Peck current: 9.92A PQ14 @ PU4 PC203
D
D
D
D
FDS6298_SO8~D PC68 1U_0402_6.3V6K~D
NC
NC
PR64
2
OCP min: 11.408A 0.22U_0603_10V7K~D
1 2 2 1 22 23
VBST VLDOIN
G 4
2.2_0603_1%~D
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
TPS51116_DRVH 21 24 1 1 1 +0.9V_DDR_VTTP
DRVH VTT
S
S
S
+1.8V_SUSP
PC69
PC70
PC197
3
1
2
3
20 LL VTTGND 1
2 2 2 +1.8V_SUSP
1 2+1.8VSUSP_L
2
TPS51116_DRVL
1000P_0603_25V7K~D
PL9 19 DRVL VTTSNS 2

5
PR65
C 1.4UH_HMU1350-1R4PF_15A_20%~D 0_0402_5%~D
Design current 0.7A for +0.9V_DDR_VTTP C
1
PC202
18 PGND_D GND 3 GNDA_DDR Peak current 1A for +0.9V_DDR_VTTP

0.1U_0402_10V7K~D
330U_D2E_2.5VM_R15~D
330U_D2E_2.5VM_R15~D
PR67
1
1 1 +3.3V_ALW PR66 @
2
4 2 1 16 CS MODE 4 2 1 GNDA_DDR
1
+ +
PC71
PC72
PC73
4.7_1206_5%~D
FDMS8670S_MLP8~D
2
2
PQ15
5.11K_0402_1% +V_DDR_MCH_REF 0_0402_5%~D

PR215
PR68 14 5 PR69 @
2
V5FILT VTTREF
1
2 2 200K_0402_1%~D 0_0402_5%~D
1
2
3
PC74
13 6 0.033U_0603_16V6K~D
1
1
PGOOD COMP
GNDA_DDR
0.1U_0402_10V7K~D
11 S5 VDDQSNS 8
<38> 1.8V_SUS_PWRGD +5V_ALW
PR70
PC196
1 2 10 9
GND_S
<38> DDR_ON S3 VDDQSET
V5IN
2
0_0402_5%~D @
TPS51116RGE_QFN24~D
15
17
<37> 0.9V_DDR_VTT_ON PR71
5.1_0402_1%~D
1U_0603_10V6K~D
2 1
1
1
PC75
PC76
1U_0603_10V6K~D
2
2
+5V_ALW
GNDA_DDR GNDA_DDR
PJP15
PAD-OPEN 4x4m
B
1 2 B
@ PR205 @ PR206
27.4K_0402_1%~D 17.4K_0402_1%
1 2 1 2 GNDA_DDR PJP16
PAD-OPEN 4x4m
2
+1.8V_SUSP 1 2 +1.8V_MEM
PR174
0_0402_5%~D
1
+5V_ALW
VOUT1=1.8V
L=1.4uH PJP14
Fsw=400KHz 2 1
D=?
Output Ripple Current=?A PAD-OPEN1x1m
GNDA_DDR
Input Ripple Current=TDC*(D*(1-D))^0.5=0.97A
Component select
Input CAP 10uF_1206_25V
Output Cap 330U_D2E_2.5VM_R9*2(Sanyo2R5TPE330M9) PJP17
H_MOSFET FDS6298 +0.9V_DDR_VTTP 2 1 +0.9V_DDR_VTT
L_MOSFET FDS6299S PAD-OPEN 2x2m~D
Inductor 1.4U_
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, 1.8VSUSP/0.9VDDR
LA-4041P
5 4 3 2 1
8 7 6 5 4 3 2 1
+CPU_PWR_SRC PL10
FBMJ4516HS720NT_1806~D
1 2 +PWR_SRC
PJP18
100U_25V_M~D
100U_25V_M~D
100U_25V_M~D
2200P_0402_50V7K~D
10U_1206_25V6M~D
10U_1206_25V6M~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
H H
1 1 1 1 2
PC82
PC83
PC84
1
1
+ + +
PC77
PC78
PC80
PC81
PAD-OPEN 4x4m
PC79
2
2
2 2 2
SI4686DY-T1-E3~D
4.7_0805_1%~D
8
7
6
5
+CPU_PWR_SRC
PR72
D
D
D
D
PQ16
+5V_ALW
Iccmax=44A
1
I_TDC=35A
G
S
S
S
680P_0603_50V7K~D
1U_0603_10V6K~D
PR73 OCP=65A, Intel spec=50A
1
2
3
4
1
PC85
10_0603_5%~D
1
PC87
@
PR74 PC86
@ 0.01U_0402_25V7K~D
2
PU5 2.2_0603_1%~D 0.22U_0603_10V7K~D
2
G 5 1 2 1 1 2 G
VDD BST PL11
6 8 UGATE1 0.45UH_ETQP4LR45XFC_25A_20%~D
SKIP DH
1
PC88
2 7 PHASE1 4 1 +VCC_CORE
PWM LX
33K_0402_5%~D
680P_0603_50V7K~D
3 4 3 2
2
GND DL
3
PR321
FDMS8670S_MLP-8~D
9
D
EP
2
+5V_ALW
PC91
PQ17
solve Maxim jitter issue MAX8791GTA+_TQFN8_3X3~D PR76
2
+3.3V_RUN
1U_0603_10V6K~D 10_0603_5%~D
GNDA_VCORE 0_0402_5%~D
2
2
change PR123 to 10_ohm LGATE1 2 G

PR78 PC89
430_0402_1%~D 1U_0603_10V7K~D
change PC122 to PR320 10_ohm
1
PR77
4.7_0805_1%~D
1 2 2 1
2
S
2
PR75
1
1
PR80 @
2
7.68K_0805_1%~D PR81
1
F PR79 F
0_0402_5%~D
1
PC90
1.91K_0603_1%~D
1
PR82 VSUM
2
2
147K_0402_1%~D
1
2 1 IMVP_PWRGD <24,37,41,49>
0_0603_5%~D
VO
1
+CPU_PWR_SRC
PR83
@ PR84
1
13K_0402_1%
0_0402_5%~D GNDA_VCORE +5V_ALW

PR85
2 1
19
20
18
39
40
2
2
PU7
2200P_0402_50V7K~D
4.7_0805_1%~D
0.1U_0603_25V7K~D
SI4686DY-T1-E3~D
PR90
10U_1206_25V6M~D
10U_1206_25V6M~D
N.C.
IMVPOK
V3P3
GND
VCC
2
8
7
6
5
@ PC92
1
PC93
2200P_0402_50V7K~D PAD~D
1U_0603_10V6K~D
D
D
D
D
PQ18
PC94
PC96
PC97
2 1 T1 IMVP6_PROCHOT# 4
1
VRHOT
PC95
@
2
680P_0603_50V7K~D
3 OSC PWM1 27
G
S
S
S
2
E E
PC98 2 PH11 5
1
2
3
4
THRM
1
PC100
470p_0402_50V7K~D PR91 PC99
2 1 @ 100K_0603_5%_ERTJ1VV104J~D 6 23 PU6 2.2_0603_1%~D 0.22U_0603_10V7K~D
CCV CSP1
5 1 2 1 1 2
2
GNDA_VCORE VDD BST PL12
2 PR87 1 28 6 8 UGATE2 0.45UH_ETQP4LR45XFC_25A_20%~D
<8> VID0 D0 SKIP DH
<8> VID1 2 PR86 1 0_0402_5%~D 29 D1
0_0402_5%~D 2 PR89 1 30 26 2 7 PHASE2 4 1 +VCC_CORE
<8> VID2 D2 PWM2 PWM LX
<8> VID3 2 PR88 1 0_0402_5%~D 31 D3
33K_0402_5%~D
0_0402_5%~D 2 PR93
680P_0603_50V7K~D
<8> VID4 1 32 D4 3 GND DL 4 3 2
PR322
<8> VID5 2 PR92 1 0_0402_5%~D 33 D5
3
0_0402_5%~D 2 PR94
FDMS8670S_MLP-8~D
<8> VID6 1 34 D6 CSP2 22 9 EP
1
PC102
0_0402_5%~D
2
37 MAX8791GTA+_TQFN8_3X3~D
PQ19
<8,10,23> H_DPRSTP#
2
PR96 DPRSTP PR97
2
<10,24> DPRSLPVR 2 1 36 DPRSLPVR 0_0402_5%~D
PR98 499_0402_1%~D LGATE2 2 PR100 PC103
G 430_0402_1%~D 1U_0603_10V7K~D
4.7_0805_1%~D
<8> H_PSI# 2 1 1
1
PSI
2
D @ PR99 0_0402_5%~D 1 2 2 1 D
PR95
2 1 2 PGD_IN DRSKP 24
2
<18> PWR_MON 10K_0402_5%~D @
1
2
1
0_0402_5%~D
PR102 PAD~D T2 CLK_ENABLE# 38 PR101 @
CLKEN
PR275
@ PC101 0_0402_5%~D 7.68K_0805_1%~D PR103 @
1
1U_0603_10V6K~D 2 1 35 10_0402_1%~D
1
PR104 10_0402_1%~D SHDN
1
GNDA_VCORE @ PR105 0_0402_5%~D 2 1 12 25 VSUM
CSN2 2
2
FBS PWM3
<37,38,41> RUNPWROK 2 1 <8> VCCSENSE
13 GNDS VO
21 PR106 +CPU_PWR_SRC
CSP3 226K_0402_1%~D
<37> IMVP_VR_ON 11 VPS
2 1 GNDA_VCORE +5V_ALW
@ PR107
0.1U_0603_25V7K~D
2 1 10 TIME
2
11.5K_0402_1%~D
10U_1206_25V6M~D
2200P_0402_50V7K~D
4.7_0805_1%~D
SI4686DY-T1-E3~D
PR108
PH2 PC104 1000P_0402_50V7K~D
10U_1206_25V6M~D
ILIMPK 7 2 1
8
7
6
5
1
PC107
10KB_0603_1%_ERTJ1VG103FA~D 2 1 9 REF
1
PC108
PC106
1U_0603_10V6K~D
C C
D
D
D
D
PQ20
PC110
PR109 PC105 1000P_0402_50V7K~D 17 VSUM
2
PWR
1
PC109
680P_0603_50V7K~D
2 1 2 1 8
2
4.99K_0402_1% TRC
2.43K_0402_1%~D
0.033U_0402_16V7K~D
G
S
S
S
41 MAX8786GTL+_TQFN40_6X6~D PR114 PC113
2
TP
CSN3
CSN2
CSN1
@ PR111
GNDA_VCORE PR110 PU8 2.2_0603_1%~D 0.22U_0603_10V7K~D

4.53K_0402_1%~D
1
2
3
4
1
1
PC114
<8> VSSSENSE 2 1 5 VDD BST 1 2 1 1 2
2
@ PC112
0_0402_5%~D PL13
@ PR112
6 8 UGATE3 0.45UH_ETQP4LR45XFC_25A_20%~D
14
15
16
2
@ PR113 PR115 SKIP DH
1
PHASE3
17.8K_0402_1%~D
0.33U_0603_10V7K
2 1 1 2 2 1 2 2 7 1 4 +VCC_CORE
2
PWM LX
1
PR117
680P_0603_50V7K~D
332_0402_1%~D PR323
@ PC115
@ PC111 @ PR116 6.04K_0603_1%~D 33K_0402_5%~D 3 4 2 3

CSN3
CSN2
6.8KB_0603_5%_ERTJ1VR682J~D
680P_0402_50V7K~D VO GND DL
2 1 2 1
1
1
PC118
1.69K_0402_1%~D
FDMS8670S_MLP-8~D
0.01U_0402_16V7K~D
9 EP
D
2
2
2 1 1 MAX8791GTA+_TQFN8_3X3~D
PQ21
2
PR118 GNDA_VCORE PR120
@ PC116
71.5K_0402_1%~D 0_0402_5%~D
1
B LGATE3 PC119 B
15K_0402_1%~D
@ PR122 PR123 PR125
4.7_0805_1%~D
2 G
2
0_0402_5%~D 10_0402_1%~D 2 430_0402_1%~D 1U_0603_10V7K~D
1 2 2 1
1
@ PH3
@ PR124
PR119
@ PC117 @ PR121 2 1 2 1 1 2 2 1
S
1500P_0402_50V7K~D 82.5K_0402_1%~D
2
PWR_MON <18>
2
1
0_0402_5%~D
PC120 PR320 PR126 @
PR276
0.01U_0402_25V7K~D @ PC121 10_0402_1%~D 7.68K_0805_1%~D PR127 @
1 2 2 1 2 1 10_0402_1%~D
1K_0402_1%~D
1
0_0402_5%~D
1000P_0402_50V7K~D VSUM
22.1K_0402_1%~D
0.1U_0402_10V7K~D
CSN3 2
2
1
1000P_0402_50V7K~D
1000P_0402_50V7K~D
1
1
PR130
PC124
1000P_0402_50V7K~D
2 1
PR128
PR131
VO
1
2
@ PC123
@ PC125
PR129
2
@ PC126
825_0402_1%~D @
2
2
2
0.01U_0402_16V7K~D
A 1 A
GNDA_VCORE
@ PC127
GNDA_VCORE Title
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +VCORE
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.5
GNDA_VCORE MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-4041P
8 7 6 5 4 3 2 1
5 4 3 2 1
PD30 RB081L-20_SOD106~D
2 1
PQ22 +SDC_IN PR132 +PWR_SRC CHAGER_SRC

SI4835BDY-T1-E3_SO8~D 0.01_1206_1%~D PL16
8 1 FBMJ4516HS720NT_1806~D
+DC_IN_SS 7 2 1 4 1 2
TBD_0603_25V7K~D
33K_0402_5%~D
6 3
0.1U_0603_25V7K~D
5 2 3
NTR4502PT1G_SOT23-3~D
+DC_IN
2200P_0402_50V7K~D
@
1
PR133
PC128
PC130
4
PC129
PR134 PR135
NB_AC_OFF <37,43,50>
160K_0402_1%~D
10K_0402_5%~D 24k_0402_1%~D
2
1
1
1
NTR4502PT1G_SOT23-3~D
2 1 2 1
PQ23
PR136
D D
2
1
D 2
10K_0402_5%~D
NB_AC_OFF# 2 PQ24 3
3
1
1
G RHU002N06_SOT323 1
PQ25
PR137
S 2 PQ70B
3
1
RHU002N06_SOT323
2 NTGD4161PT1G_TSOP6~D
2 PQ44 3
3
1
D
S
G RHU002N06_SOT323
D
2 4 DOCK_DCIN_IS+ <35>
2
<50> ACAV_DOCK_SRC
PQ66
RHU002N06_SOT323
S PR307 2
3
200K_0402_1%~D G PQ70A
1
D NTGD4161PT1G_TSOP6~D
G
2 1 S
3
PQ26
2
+SDC_IN
33K_0402_5%~D
0.047uF_0603_25V7K~D
S
G
D
2 1 5 6 DOCK_DCIN_IS- <35>
100K_0402_5%~D
100K_0402_5%~D
S
3
1
0_0402_5%~D
@ PR138
1
PR139
10K_0402_5%~D
G
1
PC131
PR140
PR340
PR339
ISL88731_VDDP ISL88731_VREF PC132 PC133
2
10K_0402_1%~D
10K_0402_5%~D
0.1U_0603_25V7K~D 0.1U_0603_25V7K~D PR338
2
2
1 2 1 2 100K_0402_5%~D
2
1
PR141 2 1 SW_GND <50>

@ PR142
PR143
@ PC134
309K_0402_1% Throttle_ICREF 1U_0603_10V6K~D
Throttle_ICOUT
28
27
1 2 GNDA_CHG
1
1
PC135 GNDA_CHG PU9
2
1U_0805_25V6K~D
CSSP
CSSN
ICREF
2
PR145 2 1 22 26
49.9K_0402_1%~D DCIN ICOUT PR144 @ PR148
RB751V_SOD323~D
2 1 2 2.2_0603_1%~D 33_0603_1%~D
PR146 ACIN
BOOT 25 1 2
15.8K_0402_1%~D
PC136 1 2 13
1
<18,38> ACAV_IN ACOK
1
PC137
0.1U_0603_25V7K~D
0_0402_5%~D
1
PD14
C C
SI4800BDY-T1_SO8~D
SI4800BDY-T1_SO8~D
2 1 11 VDDSMB
5
6
7
8
5
6
7
8
@ PR147
0.01U_0402_25V7K~D 10 PC138
2
SCL
10U_1206_25V6M~D
10U_1206_25V6M~D
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
1U_0603_10V6K~D
PQ27
PQ28
GNDA_CHG +3.3V_ALW 9 21 ISL88731_VDDP 1 2
2
SDA VDDP
1
PC142
PC139
PC140
PC141
GNDA_CHG 14 NC 4 4
24 CHG_UGATE
ISL88731_ICM UGATE
8
2
VICM
1
23 2 PR149
1
PC143 PHASE 0_0603_5%~D
6
3
2
1
3
2
1
FBO
3300PF_0402_50V7K~D
0.1U_0402_10V7K~D
2
<BOM Structure> 1 2 5 @ PC144

PR150 EAI 220P_0402_50V7K~D
2
4.7K_0402_5%~D
GNDA_CHG 200K_0402_5%~D 1 2 1 2 4 20 CHG_LGATE

EAO LGATE
1
+VCHGR
0.01U_0402_25V7K~D56P_0402_50VNPO~D
<6,27,38> CKG_SMBCLK PC145 PR151

PL14
1
PC146
2200P_0402_50V7K~D 7.5K_0402_5%~D PR153
5.6U_HMU1356-5R6_8.8A_20%~D
PR152
<6,27,38> CKG_SMBDAT 0.01_1206_1%~D
2
2
PC147
ISL88731_VREF 3 19 +VCHGR_B 2 1+VCHGR_L 1 4

VREF PGND
1.8K_1206_5%~D
18 @
CSOP
5
6
7
8
1000P_0603_50V7K~D
2200P_0402_50V7K~D
PC148 PR154 2 3
2
<18> ISL88731_ICM
PR156 @
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
0_0402_5%~D
0.1U_0603_25V7K~D
120P_0402_50VNPO~D 1 2 7 17
D
D
D
D
CE CSON
16.2K_0402_1%~D
220P_0402_50V8J~D
10K_0402_5%~D
SI4812BDY-T1-E3_SO8~D
1 2
1
1
PC204
0.1U_0402_10V7K~D
VFB 15 1 PR157 2 +VCHGR

1
1
PR155
PC149
PC159
1U_0603_10V6K~D
0.01U_0402_25V7K~D
0.01U_0402_25V7K~D
12 GND
1
PQ29
PR158
PC155
PC156
PC157
PC158
16 0_0402_5%~D 4
2
NC G
1
1
@ PC150
PC151
@ PC152
PC153
PC154
29
2
2
TP
4.7_1206_5%~D
@ PC160 PC161 @
2
2
2
S
S
S
0.1U_0603_25V7K~D 0.1U_0603_25V7K~D
2
PR216
RHU002N06_SOT323
@ @ BQ24745RHDR_QFN28_5X5~D 1 2 1 2
3
2
1
1
PJP20 D
PQ30
B B
1 2 2
1
G
GNDA_CHG S
3
PAD-OPEN1x1m @
GNDA_CHG
PR141 PR155 PC149 PR152 PC150 PR150 PC148 PC151 PC147 PC152 GNDA_CHG ACAV_IN
GNDA_CHG
Maximum charging current is 6.24A
Throttle_ICREF
TI 309K @ 220p 4.7K @ @ @ ISL88731_VREF
1 Throttle_ICOUT
+5V_ALW +3.3V_ALW
2
Maxim 365K 0.1u 10K @ @ @ PR220 PC145 PR151 PR154 PC154 PC132 PC133 PR138 PC134 PR148
100K_0402_5%~D
0_0402_5%~D PR159
1M_0402_1%~D
1
51.1K_0402_1%~D
1 2 TI @ @ @ @
1
1
200K_0402_1%~D
200K_0402_1%~D
PR162
PR160
PR161
1
100K_0402_1%~D
@ PR219
+3.3V_ALW ISL88731_ICM 1 2 Maxim @ @ @ @ @
1
+DC_IN ISL88731_VREF
@ PR218
PR334 8.45K_0402_5%~D
2
100K_0402_5%~D
1M_0402_5%~D
2
232K_0402_1%~D
PR163
1 2
2
ADAPT_OC <37>
1
1
47K_0402_1%~D
GNDA_CHG
2
1
4
PR331
PR341
PU10A
1
D
PR333
@PR164
@ PR164 2 LM393DR_SO8~D PC144 PR157 PC160 PC161
G
IN-
1K_0402_5%~D
+5V_ALW PAD~D@ 33.2K_0402_1%~D
O 1 2
G
T43 1 2 3
2
IN+
1
P
499_0402_1%~D 16.9K_0402_1%~D
10P_0402_50V8J~D
S TI @ 0
2
3
8
100P_0402_50V8J
PC163
@ PR166
0.1U_0402_10V7K~D
PQ31
8
1
100P_0402_50V8J
PR165
100P_0402_50V8J~D
0.01U_0402_25V7K~D
5 PR335 RHU002N06_SOT323
P
IN+
1
100P_0402_50V8J
21.5K_0402_1%~D
0.01U_0402_25V7K~D
O 7 1 2 ACAV_IN_NB <37,38> Maxim 100 @ @

1
PC162
PC166
6 0_0402_5%~D
2
2
IN-
1
1
100P_0402_50V8J
PC164
PC165
42.2K_0402_1%~D
PU10B
2
2
1
1
PC256
PR336
PC167
PC168
A LM393DR_SO8~D A
4
2
1
2
1
PC255
PR332
PD35
2
2
1
2
GNDA_CHG NB_AC_OFF# 2 1 +5V_ALW

2
PR167
2
GNDA_CHG GNDA_CHG GNDA_CHG GNDA_CHG

RB751S40T1_SOD523-2~D GNDA_CHG
2
Title
GNDA_CHG GNDA_CHG THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Charger
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-4041P
5 4 3 2 1
5 4 3 2 1
PR168
0_0402_5%~D
<10> GFX_VID4 1 2
PR169
0_0402_5%~D
<10> GFX_VID3 1 2
PR170
0_0402_5%~D
D <10> GFX_VID2 1
PR171
2 D
0_0402_5%~D
<10> GFX_VID1 1 2
PR172
0_0402_5%~D
<10> GFX_VID0 1 2
<10> GFX_VR_ON 1 2
PR173
0_0402_5%~D
+5V_ALW
PJP21
+VGFX_SRC 1 2 +PWR_SRC
PAD-OPEN 4x4m
2
PR175
10_0603_5%~D
10U_1206_25V6M~D
10U_1206_25V6M~D
2200P_0402_50V7K~D
0.1U_0805_50V7K
<24,37,41,47> IMVP_PWRGD VGFX_NB
1
Thermal Design Current: 6.14A
PC169
PC170
PC171
PC172
Peak current: 8.77A
SI4682DY-T1-E3_SO8~D
2
1
PC173 OCP min: 10A
C
<14> VSS_AXG_SENSE
C
5
6
7
8
1U_0603_10V6K~D
2
GNDA_VGA
D
D
D
D
PQ32
4.7U_0805_6.3V6K
32
31
30
29
28
27
26
25
PU11
GNDA_VGA
VARFREQ#
VID0
VID1
VID2
VID3
VID4
PWRGD
EN
G
S
S
S
PC174
PD15
1 24 PR177 RB751V-40_SOD323~D
4
3
2
1
FBRTN VCC 2.2_0603_1%~D
2
2 1 2 FB BST 23 2 1 1 2
PL15 +VGFX_COREP
PR176 3 COMP DRVH 22 DRVH S COIL 0.88UH +-20% MPC1040LR88C 17A
33.2K_0402_1%
PC176 4 SS SW 21 SW 4 1
2
22P_0402_50V8J
VSS_AXG_SENSE
PR178 @ PC175
0.012U_0402_16V7K~D
5 ST PVCC 20 3 2
22P_0402_50V8J PC183
680P_0402_50V7K~D
100_0402_5%~D
2
PR180 19 DRVL
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
6
330U_D2E_2.5VM_R15~D
330U_D2E_2.5VM_R15~D
PMON DRVL
1
1
PC178
PC179
PR179 20K_0402_1%~D 1 2 PC184 1 1 1 1

1
5
6
7
8
PC208
PC209
680P_0603_50V7K~D
0.1U_0402_10V7K~D
2 1 1 2 1 2 7 18
SI4362DY-T1-E3_SO8~D
PMONFS PGND + +
PC181
PC182
CSCOMP PC180
2
2
1K_0402_1%~D PC177 8 17 1U_0603_10V6K~D
CSREF
2
CLIM GND 2 2
RAMP
VRPM
LLINE
CSFB
470P_0402_50V7K
RPM
2
2 2
PQ33
RT
AGND 33
2
GNDA_VGA PR182 @ 4
2
2
187K_0402_1%
0_0603_5%~D ADP3209JCPZ-RL_LFCSP32_5X5~D PR181

9
10
11
12
13
14
15
16
PR183
PR184 4.7_0805_5%~D
100K_0402_1%~D PH4
1
GNDA_VGA 1 2
3
2
1
1
1000P_0402_50V7K~D
GNDA_VGA
+VGFX_COREP
200K_0402_1%~D
1000P_0402_50V7K~D
PR185 200K_0402_1%~D 220K_0402_5%_ERTJ0EV224J~D
357K_0603_0.5%~D
1
1
<18> PWR_MON_GFX 2 1
1
PC185
PR186
PR187
PC186
GNDA_VGA VOUT=Vgfx_NB(1.25V)
2
L=0.56uF
2
1
Fsw=436KHz
1
2
1
PR188
PC187 3K_0402_1% PR189 D=?
B 2.2U_0603_6.3VAK~D 0_0402_5%~D Output Ripple Current=?A B
2
GNDA_VGA GNDA_VGA GNDA_VGA

@ Output Ripple Voltage=?A*7.5mOhm=?mV
2
76.8K_0402_1% 165K_0402_1% PR192 Input Ripple Current=TDC*(D*(1-D))^0.5=1.52A

VGFX_CORE_FB 2 1 2 1 1 2
GNDA_VGA
<14> VCC_AXG_SENSE Component select
PR190 PR191 68.1K_0603_1%~D
Input CAP 10uF_1206_25V*2
Output Cap 330U_D2E_2.5VM_R15*2
2
PR193 @ PC188 PC189 H_MOSFET SI4682DY

0_0402_5%~D L_MOSFET SI4362DY(4.2/5.5mOhm@4.5V, 15A)
2
2200P_0402_50V7K~D 1800P_0402_50V7K~D
Inductor 0.56U_MPC1040LR56_23A(NEC_TOKIN)
1
PR194
0_0402_5%~D
1 2 VGFX_CORE_FB
PJP22 PR195 PR196

2 1 340K_0402_1%~D 1K_0402_1%~D
2 1 2 1 +VGFX_SRC
PAD-OPEN1x1m
GNDA_VGA
PJP23
1
+VGFX_COREP 1 2 +VCC_GFXCORE
PC190 PC191
1000P_0402_50V7K~D 100P_0402_50V8J PAD-OPEN 4x4m
2
GNDA_VGA GNDA_VGA
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ADP3209_NB_core
LA-4041P
5 4 3 2 1
PD16
2 PDS1040S-13_POWERDI5-3
1
3
PQ34
FDS6679AZ_SO8~D
+DOCK_PWR_BAR 8 1
+3.3V_ALW 7 2
6 3 PQ35B
3
240K_0402_5%~D
0.47U_0805_25V7K~D
5 IMD2AT-108_SC74-6~D
1
+3.3V_ALW
100K_0402_5%~D
22K_0402_5%~D
1
D PR354 D
1
PC192
PR197
330K_0402_5%~D 2
100K_0402_5%~D
100K_0402_5%~D
PR272
PR198
4
2
2
1
1
+3.3V_ALW2
PR199
PR271
2
4
NB_AC_OFF <37,43,48>
100K_0402_5%~D
1
D
47K_0402_1%~D
5 EN_DOCK_PWR_BAR#
1
2 PQ50 PQ36
1
PR299
G RHU002N06_SOT323 PQ35A RHU002N06_SOT323
1
D D
PR200
S
3
PQ37 2 PQ51 IMD2AT-108_SC74-6~D 2
6
G RHU002N06_SOT323 G EN_DOCK_PWR_BAR <37>
1
RHU002N06_SOT323 D
S S
3
<35> ACAV_DOCK_SRC# 2
G +5V_ALW 1 2
S
3
+3.3V_ALW2
100K_0402_5%~D
22K_0402_5%~D
22K_0402_5%~D
PR201
1
22K_0402_5%~D
PR273
PR274
PR300
2
NB_AC_OFF_BJT <43>
2
ACAV_DOCK_SRC <48>
1
D
SW_GND <48> 2 PQ52

1
D PQ67 G RHU002N06_SOT323
2 RHU002N06_SOT323 S
3
G
C S C
3
PQ63B
3
2N7002DW-T/R7_SOT363-6~D
PQ63A 2 5 PD31
PDS5100H-13_POWERDI5-3
2N7002DW-T/R7_SOT363-6~D 2
4
PR361 1
330K_0402_5%~D 3
SI4835BDY-T1-E3_SO8~D PQ38
PQ41 FDS6679AZ_SO8~D 1 2 PQ39
FDS6679AZ_SO8~D
8 1 PBATT+ 1 8 8 1
390K_0402_5%~D
+VCHGR 7 2 2 7 PBATT_PSRC 7 2 +PWR_SRC
620K_0402_5%~D
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
6 3 3 6 6 3
5 5 5
1
1
PR222
PC193
PC194
PR351
PR202
240K_0402_5%~D
PD19 PQ59B +NBDOCK_DC_IN_SS PD18
4
2
390K_0402_5%~D
RB751V-40_SOD323~D NTGD4161PT1G_TSOP6~D 2
2
PR204 +DC_IN_SS
1
1
S
33_0402_5%~D
D
+DC_IN_SS 2 1 2 4 3
2
1U_0603_25V6-K~D
2 1
2
240K_0402_5%~D
PR223
RB715F_SC70-3~D
2
1
1U_0603_25V6-K~D 1K_1206_5%
47K_0402_5%~D
G
3
1
PR352
PC263
PR325
PR363
2N7002DW-T/R7_SOT363-6~D
+3.3V_ALW
PQ40A
PQ59A
1
2 NTGD4161PT1G_TSOP6~D
PD20
2
1
100K_0402_5%~D
2
+3.3V_ALW2 +DOCK_PWR_BAR
S
B B
D
5 6 2 1
1
1
2
100K_0402_5%~D
240K_0402_5%~D
PR353
RB751V-40_SOD323~D
47K_0402_5%~D
G
1
6
1
PC262
PR326
33K_0402_5%~D
PR329
PR327
<37> PBATT_OFF 5
2
2
2
1
PQ40B
PR203
2N7002DW-T/R7_SOT363-6~D
2
2 4
6 1
PQ76A PR356
2N7002DW-T/R7_SOT363-6~D 0_0402_5%~D 2
1
PQ76B PD34 PQ69A

2
1
3
47K_0402_5%~D
2N7002DW-T/R7_SOT363-6~D RB751S40T1_SOD523-2~D 2N7002DW-T/R7_SOT363-6~D
2
PR328
1
<37> PBATT_OFF 5
1
PQ69B
1
2N7002DW-T/R7_SOT363-6~D
4
<35,37,43> SLICE_BAT_PRES# 5
4
PR355
1
D D
2 PQ43 PQ77 2 2 1 EN_DOCK_PWR_BAR#
G RHU002N06_SOT323 RHU002N06_SOT323 G
S S 0_0402_5%~D
3
PD33
RB751S40T1_SOD523-2~D
2 1 DOCK_AC_OFF <35,37>
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Selector
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D
1 37 ECE5028 2007/10/08 Compal SCH165092 : change BID pop option to X01. R534 (depop) ; R529 ( pop ) X01 D
2 24 ICH 2007/10/08 Compal SCH165096 : modify the net "TPM_ID" connection. change R273 from PD to GND to +3.3V_RUN. (PU = USH ; PD = china TPM) X01
X01
3 40 PWR CTRL 2007/10/08 Dell SCH165105 : modify LAN_DISABLE# connection (MH:10/02 email) Delete U61, add R934 and connect the net to U35(5028) pin 88. All Follow Roush circuit.
4 36 USH 2007/10/08 Compal SCH165106 : Change Y3 P/N & PCB footprint. P/N from SJ10000550L to SJ100005X0L(KDS). X01
5 36 USH 2007/10/11 Dell SCH165108 : MA schematic Issue list , item 139. change the connection ; NET" SMC_ADD15 " to GND. X01
NET " SMC_ADD16 " to +3.3VRUN.
SCH165110: (1)To swap the USB2 & USB3 connection to the JESA1 X01
(1) Per connector spec of the location JESA1. (2)modify connection, U29 pin4 for ESATA_USB_PWR_EN#,U53 pin4 for USB_POWERSHARE_PWR_EN#.
6 33 USB 2007/10/11 Compal (2) Per 10/25 GPIO table, modify net name & connection. (3)Per Roush DF174483, chnage the PU PWR from 3.3VALW to 3.3VALW2 for below, X01
Also refer to Roush DF174483 issue. USB_SIDE_EN# ; ESATA_USB_PWR_EN# ; USB_POWERSHARE_EN#.
7 38 5035 2007/10/11 Dell Modify the PU PWR rail from 5VALW to 3VALW below, X01
SCH165113 : Wrong PWR Rail (PU) for DOCK SMBUS. DOCK_SMB_DAT ; DOCK_SMB_CLK.
8 19 LVDS Conn 2007/10/11 Dell Add Q125, Q126 to control Webcam PWR
SCH165218 : to add webcam control PWR circuit. X01
9 42 LED 2007/10/11 Compal Modify LED circuit concept
SCH165219 : Modify LED circuit concept. X01
10 35 eDOCK 2007/10/11 Dell SCH165220 : ESD solution on DOCK Conn. Add D65 & D66 , make them pop. X01
C
(1)disconnect TV out signals to U4,delete R674,R677,R678,R669,R762,R763. C
11 12 Cantiga 2007/11/02 Dell SCH165221 : Remove TV-out on LIO docking. (2) make U4, pin15,pin19,pin20,pin31,pin22,pin23 all NC.
(3) connect U2(MCH), pinF25,H25,K25,H24,B24,A24,M25 to GND. X01
(4) U2(MCH),PinL28 connect to 1.5V filter.
12 21 DP Circuit 2007/11/02 Compal SCH165222 : Follow Roush to have PD on DPC_CA_DET Add R377 (100K,PD) X01
13 22 ICH 2007/11/02 Dell SCH165223 : Foloow DELL GPIO table, GPIO date code : 1025 Modify U10(ICH), pinF6, net name from MDC_RST_DIS# to GNT3#/GPIO55 X01
14 33 USB 2.0 2007/11/02 Compal R326 needs to PU to +5V_RUN and per GPIO table 10/25, MDC_RST_DIS# should be connected to
SCH165223 : MDC couldn't be detected issue U35(5028) pin84. X01
15 23 ICH 2007/11/02 Dell SCH165224 : To delete RTC detection circuit. Have discussed with MH, HW needs to provide more spacing for ME structure support. X01
to delete below Locations are: R92,R96,Q123,R913,R914
16 31 CardBus 2007/11/02 Compal SCH165229 : SD card PWR S/W is not DELL AVL.(U28) Change U28 to DELL AVL, TI part. X01
SCH165216 : (1)make R449 (pop) and change to 100K ohm.

17 34 Mini Card 2007/11/03 Compal X01
(1)Follow Roush schematic for R449. (2)make C553 (pop) & C572(pop) for EMI noise concern.
(2)follow Roush to pop C553,C572 for EMI noise
18 34 USH5880 2007/11/03 Compal SCH165214 : Per BRCM's comments for L69 concern. Change L69 to 450mA (rated current), They suggest to use 400mA at least. X01
19 34 USH5880 2007/11/03 Dell SCH165213 : BIOS no need SC_DET function. Delete R489,R830, and U35 Pin84 change to MDC_RST_DIS#. X01
B B
20 34 ECE5028 2007/11/15 Compal SCH165211 : Follow Roush to add 10K PD on SYS_LED_MASK# Add R669 (10K , PD to GND) X01
21 30 LAN 2007/11/15 Compal SCH165209 : Duplicate location for function on MB & IO board. To delete R395 ~ R397 on MB to get more room for layout. X01
Transfomer
22 37 ECE5028 2007/11/19 Compal SCH165206 : ALWON Oscillating issue To Add D4 & R20 to the 5028 input on the INSTANT_ON_SW# signal X01
23 37 Intel LAN 2007/11/19 Compal SCH165207 : To Add Intel LOM LDO for 2.65/2.5V To Add Q50,Q146,C482,R1020,R1017,R1018,R1019,C483,C484 X01
To Add Q50,Q146,C482,R1020,R1017,R1018,R1019,C483,C484
24 10 GMCH 2007/11/19 Dell SCH165208 : To Add level shift circuit for MCH HDA. To pop R42,R44,R685~R687,R243~R246. X01
25 36 USH5880 2007/11/19 Compal SCH165205 : To delete R495,R499 Follow Roush schematic, R495 & R499 can be replaced with short. X01
26 28 Codec AMP. 2007/11/20 Dell SCH165253 : Dell Roush WLP Results (1) On MB: C436 & C437; change from 1U 1206 25V to 2.2U 1206 25V
(2) On IO : C2 & C3 from 1uF 0603 to 2.2uF 0805 X01
27 39 TP/KB 2007/11/20 Compal SCH165256 : To remove ECE1088 related circuit To remove U38(ECE1088), C677,C676,R747,R650,R826 to have more layout room X01
28 38 MEC5035 2007/11/20 Compal SCH165257 : To remove SPI ROM related circuit on MEC5035 (1) to delete U37,R591,R589,C672,R590,R592,R593,R558.
(2) make U37, Pin67 ~ Pin69,Pin48 for NC. X01
29 36 USH5880 2007/11/20 Dell SCH165263 : FP_RESET# signal from USH5880 to BIO connector
A A
(1)Add the connection of FP_RESET# between USH5880(U32), pinC3 to JBIO1 pin5.
Also add R483(4.7K) PU on the net FP_RESET#. (2) chnage JBIO1 connector to TYCO_1734242,
same as Roush part. (3) delete the connection of BIO_DET# to the ICH pinA8,and delete R823. X01
Title
Changed-List History 1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-4041P 1.0
5 4 3 2 1
2 1

Request
30 18 EMC4002 2007/11/20 DELL SCH165267 : To add the connection of PWR_MON_GFX (1) add the net of PWR_MON_GFX, between U3 pin39 and PR185 pin2. X01
(2) Add R938 (0 ohm, pop) and add R999 (270K , depop)
(3) change R932 from 0 ohm to 4.7K
31 38 MEC5035 2007/11/20 DELL SCH165272 : change net name following PWR circuit naming. (1) From ACAV_IN_DOCK# to ACAV_DOCK_SRC#
(2) From ACAV_IN_MB/DOCK to ACAV_IN X01
(3) also remove U59,C101 ; and add U69,C672.
32 21 DP circuit 2007/11/20 Compal SCH165273 : Per derating data from Roush team to change D10. to change D10 from SDM10U45 to B0540WS for derating issue X01
33 33 USB2.0 2007/11/20 Compal LAY165112 : U54 need to be placed close to ICH. change the common mode choke connection between SW and connector.
X01
34 30 LAN SW 2007/11/20 DELL SCH165275 : To change MDI BUS L20 ~ L27 value Per Roush WI: SCH164889, we have to change the value for L20 ~ L27 from 36nH to 22nH
to improve the IEEE return loss margins. X01
B B
35 30 LAN SW 2007/11/21 Compal SCH165306 : To remove MDI terminations and caps for LAN TX/RX Follow Roush schematic to remove R384~R391;C488~C491
X01
36 18 EMC4002 2007/11/21 DELL SCH165309 : EMC4002 POWER_SW# input - to add AND gate. To add U68,R169,R170,C1050,R1014,R1015, follow Roush. X01
37 35 Docking 2007/11/21 DELL SCH165310 : docking pinout change to support battery slice. To assign the Pin 41 of the docking connector for +NBDOCK_DC_IN_SS X01
38 33 USB2.0 2007/11/21 Compal SCH165312 : Follow Roush team to add a Cap on U54 Pin8. Follow Roush team to add a Cap on +3.3V_SUS of U54 Pin8. X01
39 37 ECE5028 2007/11/21 DELL SCH165313 : To update 5028 GPIO (1) chnage U35 Pin82, from DELL_ESATA_PWR_EN# to ESATA_USB_PWR_EN#
(2) change U35 Pin104, from ESATA_USB_PWR_EN# to USB_POWERSHARE_PWR_EN# X01
(3) delete R489,R830
For 5035,
40 37 ECE5028 (1) Pin30, from DEBUG_ENABLE# to SUSPWROK, no more net is called DEBUG_ENABLE#
2007/11/21 DELL SCH165315 : To update 5035 & 5028 GPIO
38 MEC5035 (2) Pin19, from SUSPWROK to RC_ID
For 5028, X01
(1) Pin 70, change to NC.
(2) Pin 71, follow Roush to be LCD_TST only,remove R517.
41 37 ECE5028 2007/11/21 DELL Disconnect SNIFFER_DET# from ICH pin AE18 and connect it toEC5028 pin 33.
SCH165316 : To change SNIFFER_DET# connection Rename, SNIFFER_DET# to PWR_BTN_BD_DET# X01
42 34 Mini Card 2007/11/21 DELL SCH165320 : To pop R458 and R449. Follow Roush to pop R458 and R449. R449 change to 100K. X01
43 24 ICH 2007/11/22 DELL SCH165338 : To modify the pop option for the net ICH_LAN_RST# Follow Roush to depop R271, and pop R276 X01
(1) R785 change to depop

(2) R65,R66,R62,R64,R67, from 51 ohm to 56 ohm. X01
44 7 CPU 2007/11/22 DELL SCH165342 : To change BOM pop option and value of ITP circuit
(3) R60 from 10K to 150 ohm
45 7 CPU 2007/11/26 DELL SCH165380 : voltage step up issue on H_RESET# To depop the R923 to solve the voltage step up issue on H_RESET# X01
46 24 ICH 2007/11/27 DELL SCH165428 : To remove the second SPI ROM on ICH to delete R295,R304,R305,C329,U13,R306,R308,R309,R307 X01
47 36 USH5880 2007/11/27 Compal SCH165429 : To delete R846,R847 Per FAE's feedback, we can delete them for more layout room.
Those resisters are the srap pin for chip version control. X01
B0: pop R844,R845 ; so remove R846,R847
48 36 Codec 2007/11/27 DELL SCH165430 : To delete R329 Because we'll fix by PD R331 only. This is for I2C or SPI selection X01
49 7 CPU 2007/11/28 Compal SCH165508 : To add 0 ohm resisters for ESD concern. ESD team require to have some 0 ohm series resisters on the ITP I/F. X01
to add R780 ~ R784,R789.
A A
50 10 GMCH 2007/11/29 Compal SCH165550 : To change R181 value for DP functional workable Per Roush PT build result, need to change the R181 from 100K to 4.02K X01
51 13 GMCH 2007/12/03 Compal SCH165564 : this is Roush team EE WI To remove D1 & R122 X01
(1) CBS_CCD1#/CBS_CCD2# add C502/C503 270PF pull down.
(2) U52.+1.5V_CARD add C101,+3.3V_CARDAUX add C105 10uF 0805.
52 31,32 CardBus 2007/12/06 Compal SCH165942 : Ricoh review result (3) R657,R684,R790 deopo,because chip internal have pull up. X01
(4) PinA14, FIL0 add 0402 0.01uF C603
53 10 GMCH 2007/12/07 Compal SCH165943 : To modify the HDA circuiut change U67 to bi-direction part, and delete U66,C1048,C1049 X01
54 21 Display Port 2007/12/08 Compal SCH165944 : To Follow Intel suggestion to update DP circuit Add Q162,Q163 and modify the DP concept to meet Intel suggestion. X01
55 37,38 5035,5028 2007/12/08 Compal SCH165945 : To follow Roush team Instant SW circuit Add R1036,R445,R933,depop R20,depop C100,depop U57, Depop R560 X01
Title
2 1
2 1
Request Solution Description Rev.

Item Page# Title Date Issue Description
Owner
56 24 ICH 2007/12/08 DELL SCH165946 : To Follow Schematic, it's feedback from Intel To add R210 10K(@) PU to +3.3V_ALW_ICH on the net"LAN_DISABLE#"(depop) X01
57 10 GMCH 2007/12/10 Compal SCH165947 : Intel asks to change R180,R182,R183 value. R180,R182,R183 from 100K to 4.02K. X01
58 37 ECE5028 2007/12/17 Compal SCH166250 : To change the BID from X01 to X02 pop R530, depop R535 ; pop R534, depop R529 X02
59 35 Docking 2007/12/17 DELL SCH166251 : to add PU option for DOCK_DET# Add R1038, and depop R124 X02
60 12 Cantiga 2007/12/17 DELL SCH166253 : to change the R672 value follow Roush team to change the value from 1.02K to 976 ohm. X02
61 12 Cantiga 2007/12/17 DELL SCH166255 : To change R688 value R688 from 2.37K to 2.4K X02
62 42 LED 2007/12/17 Compal SCH166258 : to add D67 for backdrive issue to add D67 to solve backdrive issue in S3 , +3.3VWLAN to +5VRUN via body diode. X02
63 18 EMC4002 2007/12/17 DELL SCH166260 : to follow Rosuh to disable the 2.5V from EMC4002 to add R211, depop R149, depop C238,C239 X02
64 21 DP 2007/12/17 DELL SCH166262 : to follow Roush schematic to pop R875 follow Roush UMA DP circuit to pop R875 X02
65 27 Codec 2007/12/17 DELL SCH166266 : to follow Roush team to change C408 ~ C411 value C408 ~ C411 from 1uF to 2.2uF 0805 10V X02
18,21 EMC4002,DP X02

66 2007/12/17 DELL SCH166268 : About 74AHCT1G08GW AND Gate issue Change U68, U60, U69, U57, and U65 from 74AHCT1G08GW to 74AHC1G08GW
37,38,42 5028,5035,LED
B
X02 B
67 38 MEC5035 2007/12/17 DELL SCH166269 : update the connection of ACAV_DOCK_SRC# The signal ACAV_DOCK_SRC# can be removed from the 5035
68 42 LED 2007/12/17 DELL SCH166271 : to follow Roush to add Q150 and R1039(depop) to follow Roush to add Q150 and R1039(depop) X02
69 33,38 USB,MEC5035 2007/12/17 DELL SCH166273 : to modify for the connection "CELL_CHARGER_DET#" add D68,D69,R1040,Delete R926,change C1013 from 0.1u to 1u. follow Roush team. X02
70 6,8,24 CLK,CPU,ICH 2007/12/17 DELL SCH166276 : Intel NOA test point compliance Add R1041~R1045. X02
71 33 USB2.0 2007/12/17 DELL SCH166277 : to add esata repeter U72 related circuit to add U72,C490,C489,R306,R307,R305,C1052,C488 and U72 change to PI2EQX3201BZFE X02
72 35 Dock 2007/12/21 Compal SCH166435 : Hot Docking then Docking side Apdater Protect add D70 and R1057 on docking connector, and add C1055, R1059. X02
MEC5035 pin41 change to "DOCK_POR_RST#" to dock pin140
73 35 Dock 2007/12/28 Compal SCH166508 : DP function finalize to change DP/DVI circuit add R1060~R1063 for DDC, R1064/R1065 for CD_DET, R1066~R1069 for pull up an dlow X02
74 36 USH 2007/12/28 Dell SCH166328: Add a series resistor on PLTRST3# for the USH Add R1070 for PLTRT3# to USH RST_N X02
RESET_N
75 37 IO 5028 2007/12/28 Compal SCH166510 : DOCK_AC_OFF signals problem Cause the Battery Slice make the DOCK_AC_OFF always Low, add D72/R1071, PR356 and X02
PD33. But depop it
76 42 LED 2008/1/2 Compal SCH166540: DF186056 : ROUSH issues, Maybach have same Change the LED resistors value: X02
design and similar ME design. Follow Roush suggest for LED (1) R997 --> 68ohm (power on LED on IO board)
Resistors value (2) others Blue color LED change to 1K : R125, R556, R596, R655, R659, R663, R665,
R661, R668, R689, R1000
77 37 IO 5028 2008/02/13 Compal SCH168204 : change BID to X03 pop R529, depop R534 X03
78 37 IO 5028 2008/02/13 Dell SCH168206 : follow Roush X05 schematic pop D72, depop R1072, pop R1071 (33K ohm) X03
79 36 USH5880 2008/02/13 Dell SCH168207 : USB EA issue change R468/R469 from 22ohm to 0ohm X03
80 33 USB2.0 2008/02/13 Dell SCH168208 : Follow Roush to add bypass resisters on U54. add R1082,R1083 (make them depop) X03
81 18 EMC4002 2008/02/13 Dell SCH168209 : change R152 from 0ohm to0.82ohm for LDO input change R152 from 0ohm to 0.82ohm X03
82 6 CLOCK 2008/02/13 Dell SCH168210 : Follow Roush to change L1 (derating problem) change L1 to DC PWR Part BK2125HS601 X03
83 36 USH5880 2008/02/13 Dell Schematic : Follow Roush to pop R849 to support USH Low PWR pop R849 X03
84 35 edock 2008/02/13 Dell SCH168211 : follow Roush to depop R1057 depop R1057 X03
85 33 USB2.0 2008/02/13 Dell SCH168213 : for esata EA to pop R1046 pop R1046 X03
86 10 MCH 2008/02/13 Dell SCH168215 : follow Roush to add R1088(depop) for Intel debug depop R1088 X03
87 24,36 ICH,USH5880 2008/02/13 Dell SCH168216 : To have disable / enable TPM pop option 3@ = disable TPM , 4@ = enable TPM X03
R273(4@),D71(4@),R1058(4@)
R304(3@),R489(3@)
88 42 LED 2008/02/13 Dell SCH168217 : to change R997 value, LED current over spec change R997 to 82ohm X03
89 33 USB2.0 2008/02/13 Dell SCH168218 : Follow Roush to update ESATA circuit Add R1075,R1074,R1079,R1080,R1077,R1078 X03
A A
90 13 MCH 2008/02/13 Dell SCH168219 : debug +3.3V_RUN backdrive issue in S3 Add R1076 X03
91 27 Codec 2008/02/13 Dell SCH168220 : Per vendor feedback, change L18 to BLM18EG601SN1D L18 change to BLM18EG601SN1D X03
92 27 Codec 2008/02/13 Dell SCH168221 : Per vendor feedback, update codec circuit Add L35,delete C392,R328(Depop),R327 & R828 change to 499K ohm X03
93 38 MEC5035 2008/02/13 Dell SCH168223 : Dock SMBUS timing failed Change R565, R567 to 2.2K ohm X03
94 10 MCH 2008/02/15 Dell SCH168224 : Follow Roush to change R180~R183 value change to 2.2K X03
95 7 CPU 2008/02/15 Dell SCH168225 : Follow Roush to update ITP circuit resister value R65 from 56ohm to 150ohm;R66 from 56ohm to 649ohm;R64 from 56ohm to 39ohm X03
R67 from 56ohm to 27ohm;R57 from 1Kohm to 124ohm
X03
96 27 Codec 2008/02/20 Dell SCH168336 : Follow Roush to change C406 to 10uF C406 change to 10uF, C436/C437 change to 10uF
to change C436/C437 from 2.2uF to 10uF for Audio performance
97 21 DP 2008/02/20 Dell X03
SCH168338 : to change R377 value to follow DP spec. R377 change to 1M ohm.
Title
2 1
2 1
Request Solution Description Rev.

Item Page# Title Date Issue Description
Owner
98 21 DP 2008/02/20 DELL SCH168340:To modify DP circuit as Roush schematic pop R875,R278 ; depop R1066,R674,R650,R1069 X03
99 9 CPU 2008/02/20 DELL SCH168341:To update CPU Bypass caps value & pop option (1) change C56 ~ C61 from 220uF to 270uF (2) depop C59. X03
100 27 Codec 2008/02/20 Compal SCH168349 : modify codec circuit to have analog GND To add analog GND to solve noise problems. X03
101 27 Codec 2008/02/21 Compal SCH168528 :To modify Audio circuit after discussing with ADI To improve Audio noise problem.
1. change C401 to 0.1uF
2. change C408/C409 to 0.22uF X03
3. change C410/C411 to 0.068uF
4. add C77/C78/C79/C81/R308/R309
5. delete C397
102 36 USH5880 2008/02/21 Compal SCH168529 : to modify RFID circuit for EMI issue. Add L71,L72,C1056,C1057 X03
103 18 EMC4002 2008/02/25 Compal SCH168530 : chnge R153 value to meet the formula of Ra. R153 change to 3.16K X03
104 33 USB2.0 2008/02/29 Compal SCH168775 : To pop U51 per ESD testing result pop U51 X03
B B
105 23,29.36 ICH,USH,LAN 2008/02/29 Compal SCH168776 : X'tal EA result to change some Caps value C296/C297 from 15pF to 10pF ; C475/C476 from 27pF to 12pF;C609/C608 from 22pF to 12pF X03
106 27 Codec 2008/3/3 Compal/IDT SCH168837 : Follow Roush to add R1091/R1092 for Audio noise add R1091/R1092 (100 ohm) X03
107 39 TP/INT KB/LID 2008/3/3 DELL SCH168840 : M09 S3 backdrive issue Touch pad vendor use 5VALW for SMBUS,to add R1093,Ro1094, and depop R594/R595 X03
108 23 ICH 2008/3/3 Compal SCH168842 : 24MHz noise issue (EMI feedback) pop C300,C302,C309 X03
109 31 CardBus 2008/3/4 Compal SCH168876 : Modify SD card circuit per EMI's feedback R416 change to 33ohm and add C397(33pF) X03
110 40 PWR CTRL 2008/3/5 Compal SI4336DY will phse out, impact location Q61,Q67 Q61,Q67 from SI4336DY to NTMS4107NR2G X03
111 20 CRT 2008/3/5 Compal SCH168968 : modify RGB circuit to pass EMI/HW timing L61/L62/L63 from BLM18BB750SN1D to ; depop C267/C268 BLM18BB470SN1D; depop C390/C518/C996 X03
L8/L9/L10 change to R830/R831/R832 all for 0 ohm
112 36 USH5880 2008/3/6 DELL SCH169090 : Per Roush EE WI SCH167486 R849 change to 1.5K , R915 change to 300 ohm X03
113 31 CardBus 2008/3/6 Compal SCH169116 : X'tal EA result (location: X3) change C515 to 22pF, C514 to 27pF X03
114 21 DP circuit 2008/3/11 DELL SCH169224 : modify DP circuit (1)To implement the DP S/W as SN74CBTD3306 for MB & Docking side X03
(2)F1, change to 1206L150PR, make it pop, add C485 (10 uF), R184(depop)
115 12 MCH 2008/3/11 DELL SCH169225 : follow Roush to add 75 ohm on TV signals Add R1114 ~ R1116 X03
116 33 USB2.0 2008/3/11 DELL SCH169226 : to bypass USB S/W depop U54,C1045 ; pop R1082,R1083 X03
117 27 Codec 2008/3/11 ADI SCH169231 : to modify Audio circuit (1) C77,C78,C79,C81 change to 1000pF (2) L35 change to LBR2012T101K
(3) add C481(0.1uF) (4) C410/C411 change to 0.22uF X03
(5) C408,C409 change to 1uF (6) R1091,R1092,R340,R342 change to 200 ohm
(7) R308,R309 change to 10 M ohm and use AGND
118 6,37,38 Clock,5028 2008/3/12 Compal SCH169269 : to improve system noise R19 to 39ohm,R285(pop),C318(pop),R26 to 39ohm,R527(pop),C656(pop) X03
,36 5035, dock R32 to 39ohm,R588(pop),C673(pop),R29 to 39ohm, R744(pop),C589(pop)
119 24 ICH 2008/3/12 DELL SCH169282 : add 2nd SPI ROM add R385,R375,U13,C392,R383,R329.R384,R386,R387 X03
120 24 ICH 2008/3/13 DELL to delete the change for item 119 to delete R385,R375,U13,C392,R383,R329.R384,R386,R387 X03
121 24 ICH 2008/3/12 DELL SCH169282 : add 2nd SPI ROM add R385,R375,U13,C392,R383,R329.R384,R386,R387 X03
122 24 ICH 2008/3/17 DELL SCH169460 : add connection for SPI ROM selection add R1049,R1060, add SPI selection connection of SPI_WP#_SEL X03
123 6 Clock 2008/3/18 DELL SCH169486 : 33MHz clock shared issue CLK_PCI_PCM connection change to U1 pin 33. Pin 32 is for dock 33MHz ONLY. X03
124 21,35 DP,eDOCK 2008/4/28 Compal SCH170959 : C985/C984 from 0.1uF to 0.033uF for ESD concern C985/C984 from 0.1uF to 0.033uF. X04
125 24 ICH 2008/4/28 DELL SCH170960 : to depop 2nd SPI ROM to depop R385,R1060,R375,U13,C392,R383,R329,R384,R386 X04
126 27 Codec 2008/4/28 Compal SCH170961 : EMI concern for DMIC_CLK change R338 to L75, and pop C486 X04
127 27 Codec 2008/4/28 DELL SCH170962 : bypass double inverter of DAI_DI depop U18,U19,C418,C419 and add R762 X04
128 35 eDOCK 2008/4/28 Compal SCH170963 : Follow Roush to add R1095,R1096 add R1095,R1096. (0 ohm) X04
129 37 ECE5028 2008/4/28 Compal SCH170964 : change BID depop R539 add R534, depop R530 add R535, add R531 depop R536 X04
130 40 PWR CTRL 2008/4/28 Compal SCH170965 : add discharge circuit of 3.3VRUN add R625(39 ohm) and Q79 X04
131 42 LED 2008/5/7 Compal SCH171234 : SNIFFER LED only support BLUE color depop Q100,R667 X04
132 18 EMC4002 2008/5/7 Compal SCH171233 : FAN speed couldn't be dectected issue add D38 X04
133 23 ICH 2008/5/8 Compal SCH171331 : WLAN detection issue Follow Roush to add R84,R96 10K PD. (R84 & R96 all depop) X04
A
134 40 PWR CTRL 2008/5/26 Compal SCH172014 : Follow Roush to change C688 value. C688 from 4700pF to 3300pF. X04A A
135 10 MCH 2008/5/26 Compal SCH171331 : PCIe detection for WLAN issue Add Q153~Q155, R1118~R1123 , C1049 X04A
136 24,38 ICH,MEC5035 2008/6/2 DELL SCH172196 : re-route ODD_DET# add a connection to MEC5035 pin 34 also. A00
137 37 ECE5028 2008/6/2 Compal SCH172197 : BID changed from X04 to A00 POP R529, DEPOP R534 A00
138 29 82567LM 2008/6/6 DELL SCH172399 : LOM IEEE test result from Intel C475 & C476 from 12PF to 27PF to pass LOM IEEE test A00
139 42 LED 2008/6/6 Compal SCH172401 : Breath LED current issue R997 from 82 ohm to 100 ohm for current limited A00
140 24 ICH 2008/6/6 Compal SCH172404 : SAWTOOTH waveform on SERIRQ issue Add R122(33 ohm) A00
141 36 USH5880 2008/6/13 BRCM BRCM feedback for PI circuit C1056/C1057 from 5% to 1% ; C641/C647 from 5% to 1% A00
Title
<Title>

CustomLA-4041P 1.0

2 1
5 4 3 2 1

Request
1 43 +DC_IN 11/17 leverage Battery slice need detect Add PQ61 NTR4502PT1G, and PD32 RB751_SOD323 X01
D Roush NB battery is insert or not. Connect to DOCK_SMB_ALERT# and SLICE_BAT_PRES# D
2 43 +DC_IN 11/17 leverage DCIN_CBL_DET# damage ECE5028 Add ESD diedo PD17 DA204U_SOT323 at DCIN_CBL_DET#
Roush Series PR221 1K_0402_5% between PJPDC1, PIN1 and DCIN_CBL_DET# X01
Parallel PC254 0.47uF_0402_6.3V on DCIN_CBL_DET#
Roush component and rework changes PC4 change form 0.47uF_0805_25V to 0.1uF_0805_25V
3 43 +DC_IN 11/17 leverage for Dcoking test PR14 change form 240K_0402_5% to 1M_0402_5%
Roush PR17 change form 47K_0402_1% to 220K_0402_5% X01
PR18 change form 47K_0402_1% to 22K_0402_5%
PR342 change form 0_0402_1% to 100K_0402_5%
4 48 Charger NB DC blocking MOSFET won't turn off Add PQ44 RHU002N06 control NB DC blocking MOSFET.
11/17 when Dock AC insert. Control singal is NB_AC_OFF
leverage
Roush Series PR284 200K_0402_1% between PQ44 PIN1 and ACAV_IN X01
Add PD30 B540C parallel PQ34
5
48 Charger 11/17 leverage Charger of ISL88731 will turn off Add LM393 to replace ISL88731 ACOK function(PU11B)
C Roush When ACIN is no power X01 C
6 48 Charger leverage +PWR_SRC exist on Docking connector Add PQ62 NTGD4161PT1G series DOCK_DCIN_IS+ and -
50 Selector 11/17 Roush through the DOCK_DCIN_IS+ and - Add PQ63 RHU002N06 to control PQ62 on/off X01
7 48 Charger leverage A global signal name change From "ACAV_IN_DOCK" to "ACAV_DOCK_SRC"

50 Selector 11/17 Roush for all notebooks From "ACAV_IN_DOCK#" to "ACAV_DOCK_SRC#" X01
8 48 Charger leverage SCH165050: Validate EMC4002 VIN1/VCP1/VCP2 Depop UL circuit.

11/17 Roush for UMA & Discrete for PT1 SMT X01
PBATT DC blocking MOSFET won't turn off Add PD18 RB715F_SOT323, PD20 and PD19 RB751V_SOD323, PR329 100K_0402_5%
50 leverage when Docking AC insert. PR328 and PR327 47K_0402_5%, PR326 and PR325 240K_0402_5%
9 Selector 11/17 Roush It will cause Battery or adapter protect. PQ69 2N7002DW-7-F_SOT363-6, PQ59 NTG6161PT1G_TSOP6 X01
Extra net name add +NBDOCK_DC_IN_SS from Docking connector
B B
EE / follow HW change To delete the RTC detection circuit

10 43 +DCIN 11/20 SCH165224 X01
48 Selector change charger output to FB pin15 net name from PBATT+ to +VCHGR
11 50 charger 11/30 Dell for slice function implement Add PQ41 PQ70 PR351 PR352 PR353 between +VCHGR and PBATT+ X01
12 43 +DCIN change DCIN connector for ESD issue of "DCIN_CBL_DET#" X02

12/17 Dell from Molex_87437_0663 to MOLEX_87437-0763
change PQ63 from RHU002N06 to 2N7002DW

13 50 Selector follow Roush ADD PD33 RB751V X02
12/28 leverage
Roush ADD PR354
ADD PQ77 RHU002N06 and PR355 0 ohm
14 48 Charger follow Roush X02

A
12/28 leverage Change PC131 from TBD to 0.047uF A
Roush
Title
<Title>

C <Doc> 1.0

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5 4 3 2 1

Request
15 47 +Vcore 02/18 Dell / Reduce Ring-backwithin 20mV when change PR129 change from 909 ohm to 825 ohm
D Maxim bulk caps from 4*220uF to 3*270uF D
Merle Fix BITS CR196131 and CR196130 Add PR363 1K_1206 and PC262 1U_0603_25V from +NBDOCK_DC_IN_SS to ground
16 50 Selector 02/18 DELL Add PD35 RB751S40T1_SOD523-2 from NB_AC_OFF# to ACAV_IN_NB
change PR123 to 10_ohm

17 47 +Vcore 02/18 Maxim Fix Jitter issue change PC122 to PR320 10_ohm
change PR141 to PR217 change PR217 to PR141

18 48/50 charger / 02/26 Compal location change change PR228 to PR218 change PR218 to PR351
selector for Charger 2nd source X76 BOM control change PR230 to PR219 change PR219 to PR352
change PR229 to PR220 change PR220 to PR353
change PR284 to PR307
change PQ62 to PQ70 change PQ70 to PQ76
19 48 Charger 03/06 Compal Delete non-use circuit delete +DC_IN_SS to PR217 and PR217.
C C
Change PQ40 from IMD2AT to 2N7002DW

20 50 Selector 03/06 Compal For slice battery hot docking issue change PR202 from240K_ohm ot 620k_ohm
change PR204 from 47K_ohm to 33_ohm
add PR222 390K_ohm and PR223 390K_ohm
add PD34 RB751S40T1
21 47 +Vcore 03/11 Maxim For driver IC power down issue Add PR321 PR322 PR323 from IC pin 2 to GND
Change PR32 PR33 PR57 PR58 PR64 PR74 PR91 PR144 PR177 to 2.2_ohm
22 44-50 All 03/19 Compal EMI solution Add PC198 PR211 PC199 PR212 PC200 PR213 PC201 PR214 PC202 PR215 PC87
PR72 PC91 PR75 PC100 PR90 PC102 PR95 PC114 PR108 PC118 PR119 PC204
PR216 PC184 PR181 PC128 PC130
23 45 1.5V/1.05v 4/23 Compal change non-lead free part to lead free part PR47 change from SD03415830L to SD03415838L
B B
Driver IC power down issue
need change resistor value change PR321 PR322 PR323 to 33K
24 47 Vcore 4/23 Maxim
25 49 ADP3209 4/23 Intel Follow Roush Change PR192 from 75K_0603 to 68.1K_0603
Compal VGFX DC load line slope change to -7.5mOhm
Compal Add PC257:SE074152K8L(S CER CAP 1500P 50V +-10% X7R 0402)
26 43 DC-IN 6/3 between pin2 of PQ61 and GND.
Glitch issue on SLICE_BAT_PRES#
Add un-pop PR330:SD02847018L(S RES 1/16W 4.7K +-5% 0402)

Compal Reserve a pull high resistor between between +3.3V_ALW2 and PQ40B.5.
27 50 Selector 6/4 +3.3V_ALW2 and SLICE_BAT_PRES#
A A
Title
<Title>

C <Doc> 1.0

5 4 3 2 1

M09 Maybach UMA: uFCPGA Mobile Penryn Intel Cantiga GM + ICH9M

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M09 Maybach UMA: uFCPGA Mobile Penryn Intel Cantiga GM + ICH9M

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A B C D E

PCB NO : LA-4041P (DA800009Y1L)

M09 Maybach UMA

Intel Cantiga GM + ICH9M

CHARGER 1.5V/1.05V DC IN/BATT IN Block Diagram

POWER STATES USB PORT# DESTINATION

S5 (SOFT OFF) / M1 LOW HIGH LOW LOW HIGH ON ON ON OFF ON 4 WLAN

+15V_ALW +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M 10 USH->BIO

Lane 1 MINI CARD-1 WWAN

S5 S4/AC don't exist OFF OFF OFF OFF OFF

Lane 6 10/100/1G LAN

PCI DEVICE IDSEL REQ#/GNT# PIRQ

R5C847 AD17 REQ#1 / GNT#1 PIRQ[B..D]

+5V_HDD +5V_MOD +VDDA

+3.3V_ALW_ICH 2.2K +3.3V_M

SMBUS Address [TBD]

0 0 0 266 100 33.3

FSA CLK_ICH_14M R33 1 2 22_0402_5%~D 66 PCIE_ICH 1 2 CLK_PCIE_ICH

CLK_SIO_14M R35 1 2 22_0402_5%~D 67 PCIE_ICH# 1 2 CLK_PCIE_ICH#

DOT_96#/27M_SS SRC_6 R39 33_0402_5%~D

TME PIN 32 CLKREQ_5# 29

0 overclocking enabled 58 PCIE_EXP 1 2 CLK_PCIE_EXP

SMBCLK PCIE_EXP# CLK_PCIE_EXP#

CLKREQ_4# 57 EXPCLK_REQ# <32>

4 56 MCH_3GPLL# 1 2 CLK_MCH_3GPLL# CLK_MCH_3GPLL# <10>

ITP_EN PIN 37 R47 33_0402_5%~D

42 50 PCIE_SATA 1 2 CLK_PCIE_SATA CLK_PCIE_SATA <23>

68 51 PCIE_SATA# 1 2 CLK_PCIE_SATA# CLK_PCIE_SATA# <23>

A PCI_SIO THRM_PAD DOT96_SSC A

0=UMA DOT96T DOT96C 96/100M_T 96/100M_C 48 DOT96_SSC# 1 2

1=DIS 27M_out 27M SSout SRCT0 SRCC0

Compal Electronics, Inc.

H_FERR# A5 C7 E19 AB13

RSVD[05] +1.05V_VCCP VSS[053] VSS[134]

Place close to JITP within 200ps = 1000 mil

Resistor placed within 0.5" of

For the purpose of testability, route these signals

Reserve for testing

FSB BCLK BSEL2 BSEL1 BSEL0 +1.05V_VCCP

Route VCCSENSE and VSSSENSE trace at

1067 266 0 0 0 R78

Place these inside 1 1 1 1 1 1 1 1 1 1

Place these inside 1 1 1 1 1 1 1 1 1 1

Place these inside 1 1 1 1 1 1

Place these inside 1 1 1 1 1 1 10uF 0805 X6S -> 85 degree C

High Frequence Decoupling

Near VCORE regulator.

ESR <= 1.5m ohm

1 2 SDVO_CTRLCLK RSVD1 M36 TP_MCH_RSVD1 T153PAD~D

DDR CLK/ CONTROL/COMPENSATION

H_D#18 R2 J20 H_A#22 +V_DDR_MCH_REF +V_DDR_MCH_REF AV42

H_D#20 L6 A17 H_A#24 R81 1 2 499_0402_1%~D BF17

H_D#21 M5 B17 H_A#25 1 1 PAD~D T13 TP_SM_DRAMRST# BC36

H_D#25 H_D#_24 H_A#_28 H_A#29 2 2 DREF_SSCLK DPLL_REF_CLK#

H_D#28 H_A#32 CLK_MCH_3GPLL

1 H_D#29 L7 F21 H_A#33 <6> CLK_MCH_3GPLL# CLK_MCH_3GPLL# E43

H_D#30 N10 K21 H_A#34

H_D#31 M3 L20 H_A#35

H_D#34 H_D#_33 H_ADS# H_ADSTB#0 DMI_MRX_ITX_N1 DMI_RXN_0

H_D#_38 H_BREQ# H_BR0# <7> <24> DMI_MRX_ITX_P0 DMI_RXP_0

H_D#50 H_D#_49 DMI_MTX_IRX_P2 DMI_TXP_1 CFG_10

H_D#53 AD3 J8 H_DINV#0 R20 T21 PAD~D

1 H_D#54 AD7 L3 H_DINV#1 M20 T22 PAD~D