Compal confidential NALAE LA-6052P Schematics

A B C D E
1 1
Compal confidential
2
Hamburg 10ADG 2
NALAE LA-6052P Schematics Document
Mobile AMD S1G4/ RS880M / SB820M

3 3
2009-11-27 Rev. 0.2
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008-09-25 Deciphered Date 2009-09-25 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6052
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401851 A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 20, 2010 Sheet 1 of 53
A B C D E
A B C D E
Compal Confidential Thermal Sensor Fan Control AMD S1G4 CPU

Memory BUS(DDRIII)
200pin DDRIII-SO-DIMM X2
page 5 Dual Channel
ADM1032ARMZ page 7 BANK 0, 1, 2, 3 page 9,10
Model Name : NALAE uFCPGA-638 Package 1.5V DDRIII 1066/1333MHZ
File Name : LA-6052P page 5,6,7,8
1 Hyper Transport Link 2.6GHz 1
16X16 PCIeMini Card WLAN

PCIe Port 2
CRT USB Port 8 page 28

page 17
AMD
LCD Conn. RS880M PCIe 4x

page 18 Madison & Park 1.5V 2.5GHz(250MB/s)
Page 35,36,37,38,39
HDMI Conn. 40,41,42,43
page 19
page 11,12,13,14,15
RTL 8105E 10/100 RJ45
PCIe port 3 page 26
2 2
A-Link Express II page 26
4X PCI-E
SATA port 0 SATA HDD

5V 1.5GHz(150MB/s) page 25
AMD
USB/B Card Reader
USB port 0,1 USB port 5 SATA port 1 SATA ODD
page 28 page 27 5V 1.5GHz(150MB/s) page 25
USB SB820M
5V 480MHz
BT conn Int. Camera SATA port 3
USB port 6 USB port 9 5V 1.5GHz(150MB/s)
page 28 page 18 eSATA
USB port 2 page 25
5V 480MHz
page 20,21,22,23,24
3 3
Clock Generator
SLG8SP626 HD Audio 3.3V 24.576MHz/48Mhz
page 16
LPC BUS
3.3V 33 MHz
RTC CKT. ODD/B MDC 1.5 Conn HDA Codec
page 20 page 25 ALC259Q
Debug Port ENE KB926 D3 page 32 page 29
page 32 page 31
Power On/Off CKT. Power/B
page 33
page 33
Audio & USB/B Int.KBD SPI ROM Int.

MIC CONN MIC CONN HP CONN SPK CONN
DC/DC Interface CKT. page 33 page 32 page 32 page 18 page 30 page 30 page 30
page 34
LED/B
page 33
Power Circuit DC/DC
4
page 44,45,46.47 Touch Pad/B 4
48,49,50,51 page 33

SCHEMATIC,MB A6052
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 401851 A
A B C D E
5 4 3 2 1
DESIGN CURRENT 0.1A +3VL

DESIGN CURRENT 0.1A +5VL
B+
RT8205EGQW Ipeak = 5A, Imax = 3.5A, Iocp_min = 7.7A DESIGN CURRENT 5A +3VALW
Ipeak = 5A, Imax = 3.5A, Iocp_min = 7.9A DESIGN CURRENT 5A +5VALW
SUSP
N-CHANNEL DESIGN CURRENT 2A +5VS
D D
SI4800
SUSP#
DESIGN CURRENT 2.5A +1.8VS
MP2121DQ
WOL_EN#
DESIGN CURRENT 330mA +3V_LAN
P-CHANNEL
AO3413
SUSP
N-CHANNEL DESIGN CURRENT 1.5A +3VS
SI4800 VGA_ENVDD
P-CHANNEL DESIGN CURRENT 1A +LCD_VDD
AO3413
BT_PWR#
NALAE Hamburg AMD DIS DESIGN CURRENT 180mA +BT_VCC
C
P-CHANNEL C
AO3413
DESIGN CURRENT 300mA +2.5VS

APL5508
POK
Ipeak = 12A, Imax = 8.4A, Iocp_min = 18.7A DESIGN CURRENT 12A +1.1VALW
RT8209BGQW VLDT_EN#
N-CHANNEL DESIGN CURRENT 3.5A +1.1VS
IRF8113
VLDT_EN#
N-CHANNEL DESIGN CURRENT 6A +NB_CORE
IRF8113
VR_ON
Ipeak = 36A, Imax = 25.2A, Iocp_min = 54A DESIGN CURRENT 36A +CPU_CORE_0
ISL6265A DESIGN CURRENT 4A +VDDNB
B B
SYSON
Ipeak = 11A, Imax = 7.7A, Iocp_min = 19.16A DESIGN CURRENT 11A +1.5V
RT8209BGQW SUSP
N-CHANNEL DESIGN CURRENT 5A +1.5VS
IRF8113
SUSP
DESIGN CURRENT 1A +0.75VS

APL5331KAC
VR_ON#

APL5331KAC
SUSP#

APL5930KAI
SUSP#
A DESIGN CURRENT 20A A

Ipeak = 20A, Imax = 14A, Iocp_min = 20.14A +VGA_CORE
APW7138NITRL

SCHEMATIC,MB A6052
5 4 3 2 1
A B C D E
Voltage Rails Symbol Note :
O : ON
: Digital Ground Platform CPU NB VGA SB Comment
X : OFF S1G4 RS880M NA SB820M
Danube
: Analog Ground
+5VS
1
+3VS 1
power
plane +2.5VS
+1.8VS
GPU CPU NB VGA SB Comment
+1.5VS
@ : just reserve , no build S1G4 RS880M MADISON SB820M MANHA@+MADISON@ or PARK@+
+1.1VS Manhattan
B+ +5VALW S1G4 RS880M PARK SB820M +4PCS or 8PCS
+1.05VS
+3VL +3VALW +1.5V S1G4 RS880M M96 SB820M M9X@+M92@
+0.75VS M9X
+5VL +1.1VALW S1G4 RS880M M92 SB820M +4PCS or 8PCS
State +VGA_CORE
+RTCVCC
+VDDNB
+CPU_CORE
+NB_CORE
BTO (Build-To-Order) Option Table
Function BLUE TOOTH HDMI
S0
O O O O Description (B) (Y)
S1 Explain
O O O O
2 2
BTO BT@ H@
S3
O O O X
S5 S4/AC
O O X X
S5 S4/ Battery only
O X X X
S5 S4/AC & Battery
don't exist X X X X
SMBUS Control Table
CPU
SOURCE BATT SODIMM CLK LCD HDMI
THERMAL WLAN
I2C / SMBUS ADDRESSING I / II GEN DDC DDC
SENSOR ROM ROM
EC_SMB_CK1
DEVICE HEX ADDRESS KB926
V
EC_SMB_DA1
3
DDR SO-DIMM 0 A0 1010000X EC_SMB_CK2 3
KB926
DDR SO-DIMM 1 A2 1010001X EC_SMB_DA2 V
CLOCK GENERATOR (EXT.) D2 11010010 I2C_CLK
RS880M
I2C_DATA V
DDC_CLK0
RS880M
DDC_DATA0 V
SCL0
SB820
EC SM Bus1 address EC SM Bus2 address SDA0 V V
SCL1
Device HEX Address Device HEX Address SB820
SDA1 V
Smart Battery 16H 0001 011X b ADI1032-1 CPU 98H 1001 100X b
HDMI-CEC 34H 0011 010X b ADI1032-2 VGA 9AH 1001 101X b
EC KB926D4 EC KB926D3
4 4

SCHEMATIC,MB A6052
A B C D E
A B C D E
+1.1VS
250 mil VLDT CAP. Near CPU Socket
1 1 1 1 1 1
C1 C2 C3 C4 C5 C6
10U_0805_10V4Z 10U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J

2 2 2 2 2 2
1 1
H_CADIP[0..15] H_CADOP[0..15]
<11> H_CADIP[0..15] H_CADOP[0..15] <11>
H_CADIN[0..15] H_CADON[0..15]
<11> H_CADIN[0..15] H_CADON[0..15] <11>
+1.1VS
+1.1VS
JCPUA
C7
D1 HT LINK AE2 +VLDT_B 1 2 10U_0805_10V4Z < VLDT_A & VLDT_B : HyperTransport I/O ring power >
VLDT_A0 VLDT_B0
VLDT=500mA D2 VLDT_A1 VLDT_B1 AE3
D3 VLDT_A2 VLDT_B2 AE4
D4 VLDT_A3 VLDT_B3 AE5
H_CADIP0 E3 AD1 H_CADOP0

H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP2 G3 AB1 H_CADOP2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
H_CADIP3 G1 AA2 H_CADOP3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
2 H_CADIP4 H_CADOP4 2
J1 L0_CADIN_H4 L0_CADOUT_H4 W2
H_CADIN4 K1 W3 H_CADON4
H_CADIP5 L0_CADIN_L4 L0_CADOUT_L4 H_CADOP5
L3 L0_CADIN_H5 L0_CADOUT_H5 V1
H_CADIN5 L2 U1 H_CADON5
L1 L0_CADIN_H6 L0_CADOUT_H6 U2
H_CADIN6 M1 U3 H_CADON6
N3 L0_CADIN_H7 L0_CADOUT_H7 T1
H_CADIN7 N2 R1 H_CADON7
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4
H_CADIN8 F5 AD3 H_CADON8
< From NB > F3 L0_CADIN_H9 L0_CADOUT_H9 AD5 < To NB >
H_CADIN9 F4 AC5 H_CADON9
G5 L0_CADIN_H10 L0_CADOUT_H10 AB4
H_CADIN10 H5 AB3 H_CADON10
H3 L0_CADIN_H11 L0_CADOUT_H11 AB5
H_CADIN11 H4 AA5 H_CADON11
H_CADIP12 L0_CADIN_L11 L0_CADOUT_L11 H_CADOP12 J2
K3 L0_CADIN_H12 L0_CADOUT_H12 Y5
H_CADIN12 K4 W5 H_CADON12 +1.5V 2 1 +1.5V_CPU
H_CADIP13 L0_CADIN_L12 L0_CADOUT_L12 H_CADOP13 2 1
L5 L0_CADIN_H13 L0_CADOUT_H13 V4
H_CADIN13 M5 V3 H_CADON13 @ JUMP_43X118
M3 L0_CADIN_H14 L0_CADOUT_H14 V5
H_CADIN14 M4 U5 H_CADON14
N5 L0_CADIN_H15 L0_CADOUT_H15 T4
H_CADIN15 P5 T3 H_CADON15
L0_CADIN_L15 L0_CADOUT_L15
<11> H_CLKIP0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 H_CLKOP0 <11>

<11> H_CLKIN0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 H_CLKON0 <11>
<11> H_CLKIP1 J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 H_CLKOP1 <11>
<11> H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 <11>
<11> H_CTLIP0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 H_CTLOP0 <11>

<11> H_CTLIN0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 H_CTLON0 <11>
3 3
<11> H_CTLIP1 P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 H_CTLOP1 <11>
<11> H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 <11>
FOX_PZ6382A-284S-41F_Champlian
< FAN Control Circuit : Vout = 1.6 x Vset >
+5VS
1A
2
+FAN1 C1119
JFAN +3VS
1
C1120 10U_0805_10V4Z +FAN1 1
1 1
2 2
1
10U_0805_10V4Z 2 3
2 U31 C1121 3 R795
1 8 @ 4
EN GND 1000P_0402_25V8J GND 10K_0402_5%
2 VIN GND 7 5 GND
1
3 6
2
VOUT GND @ ACES_85204-0300N

<31> EN_DFAN1 4 VSET GND 5 FAN_SPEED1 <31>
4 4
2
APL5607KI-TRG_SO8 C1122
@
0.01U_0402_25V7K
1

SCHEMATIC,MB A6052
A B C D E
A B C D E
< DDR2 VREF is 0.5 ratio > < Processor DDR3 Memory Interface >
+1.5V_CPU
2
R1
JCPUC
<10> DDR_B_D[63..0]
1K_0402_1% MEM:DATA
DDR_A_D[63..0] <9>
< From/To SO_DIMMB > DDR_B_D0 C11 G12 DDR_A_D0
1
+MCH_REF DDR_B_D1 MB_DATA0 MA_DATA0 DDR_A_D1

A11 MB_DATA1 MA_DATA1 F12 < From/To SO_DIMMA >
DDR_B_D2 A14 H14 DDR_A_D2
MB_DATA2 MA_DATA2
2
1 1 DDR_B_D3 B14 G14 DDR_A_D3

R2 C9 C8 DDR_B_D4 MB_DATA3 MA_DATA3 DDR_A_D4
G11 MB_DATA4 MA_DATA4 H11
DDR_B_D5 E11 H12 DDR_A_D5
1 1K_0402_1% 0.1U_0402_16V7K 1000P_0402_25V8J DDR_B_D6 MB_DATA5 MA_DATA5 DDR_A_D6 1
D12 MB_DATA6 MA_DATA6 C13
2 2 DDR_B_D7 DDR_A_D7
A13 E13
1
DDR_B_D8 MB_DATA7 MA_DATA7 DDR_A_D8

A15 MB_DATA8 MA_DATA8 H15
DDR_B_D9 A16 E15 DDR_A_D9
A19 MB_DATA10 MA_DATA10 E17
DDR_B_D11 A20 H17 DDR_A_D11
C14 MB_DATA12 MA_DATA12 E14
DDR_B_D13 D14 F14 DDR_A_D13
C18 MB_DATA14 MA_DATA14 C17
DDR_B_D15 D18 G17 DDR_A_D15
D20 MB_DATA16 MA_DATA16 G18
DDR_B_D17 A21 C19 DDR_A_D17
D24 MB_DATA18 MA_DATA18 D22
DDR_B_D19 C25 E20 DDR_A_D19
B20 MB_DATA20 MA_DATA20 E18
DDR_B_D21 C20 F18 DDR_A_D21
B24 MB_DATA22 MA_DATA22 B22
DDR_B_D23 C24 C23 DDR_A_D23
E23 MB_DATA24 MA_DATA24 F20
DDR_B_D25 E24 F22 DDR_A_D25
DDR_B_D27 G26 J19 DDR_A_D27
C26 MB_DATA28 MA_DATA28 E21
DDR_B_D29 D26 E22 DDR_A_D29
DDR_B_D31 G24 H22 DDR_A_D31
+1.05VS +1.05VS DDR_B_D32 MB_DATA31 MA_DATA31 DDR_A_D32
AA24 MB_DATA32 MA_DATA32 Y24
JCPUB DDR_B_D33 AA23 AB24 DDR_A_D33
AD24 MB_DATA34 MA_DATA34 AB22
D10 W10 DDR_B_D35 AE24 AA21 DDR_A_D35
VDDR1 MEM:CMD/CTRL/CLK
VDDR5 DDR_B_D36 MB_DATA35 MA_DATA35 DDR_A_D36
C10 VDDR2 VDDR6 AC10 AA26 MB_DATA36 MA_DATA36 W22
Place them close to CPU within 1" B10 AB10 < VTT regulator voltage > DDR_B_D37 AA25 W21 DDR_A_D37
2 VDDR3 VDDR7 DDR_B_D38 MB_DATA37 MA_DATA37 DDR_A_D38 2
AD10 VDDR4 VDDR8 AA10 AD26 MB_DATA38 MA_DATA38 Y22
A10 DDR_B_D39 AE25 AA22 DDR_A_D39
R4 1 VDDR9 MB_DATA39 MA_DATA39
2 39.2_0402_1% MEM_P AF10 MEMZP
DDR_B_D40 AC22 MB_DATA40 MA_DATA40 Y20 DDR_A_D40
+1.5V_CPU R5 1 2 39.2_0402_1% MEM_N AE10 Y10 VTT_SENSE DDR_B_D41 AD22 AA20 DDR_A_D41
MEMZN VDDR_SENSE PAD T1 MB_DATA41 MA_DATA41
DDR_B_D42 AE20 AA18 DDR_A_D42
MEM_MA_RST# +MCH_REF DDR_B_D43 MB_DATA42 MA_DATA42 DDR_A_D43
<9> MEM_MA_RST# H16 MA_RESET_L MEMVREF W17 AF20 MB_DATA43 MA_DATA43 AB18
DDR_B_D44 AF24 AB21 DDR_A_D44
DDR_A_ODT0 MEM_MB_RST# DDR_B_D45 MB_DATA44 MA_DATA44 DDR_A_D45
<9> DDR_A_ODT0 T19 MA0_ODT0 MB_RESET_L B18 MEM_MB_RST# <10> AF23 MB_DATA45 MA_DATA45 AD21
< To SO_DIMMA > <9> DDR_A_ODT1 DDR_A_ODT1 V22 DDR_B_D46 AC20 AD19 DDR_A_D46
MA0_ODT1 DDR_B_ODT0 DDR_B_D47 MB_DATA46 MA_DATA46 DDR_A_D47
U21 MA1_ODT0 MB0_ODT0 W26 DDR_B_ODT0 <10> AD20 MB_DATA47 MA_DATA47 Y18
V19 W23 DDR_B_ODT1 < To SO_DIMMB > DDR_B_D48 AD18 AD17 DDR_A_D48
MA1_ODT1 MB0_ODT1 DDR_B_ODT1 <10> MB_DATA48 MA_DATA48
Y26 DDR_B_D49 AE18 W16 DDR_A_D49
DDR_CS0_DIMMA# T20 MB1_ODT0 DDR_B_D50 MB_DATA49 MA_DATA49 DDR_A_D50
<9> DDR_CS0_DIMMA# MA0_CS_L0 AC14 MB_DATA50 MA_DATA50 W14
< To SO_DIMMA > DDR_CS1_DIMMA# U19 V26 DDR_CS0_DIMMB# DDR_B_D51 AD14 Y14 DDR_A_D51
<9> DDR_CS1_DIMMA# MA0_CS_L1 MB0_CS_L0 DDR_CS0_DIMMB# <10> MB_DATA51 MA_DATA51
DDR_CS1_DIMMB# DDR_B_D52 DDR_A_D52
U20 MA1_CS_L0 MB0_CS_L1 W25 DDR_CS1_DIMMB# <10>< To SO_DIMMB > AF19 MB_DATA52 MA_DATA52 Y17
V20 U22 DDR_B_D53 AC18 AB17 DDR_A_D53
MA1_CS_L1 MB1_CS_L0 DDR_B_D54 MB_DATA53 MA_DATA53 DDR_A_D54
AF16 MB_DATA54 MA_DATA54 AB15
DDR_CKE0_DIMMA J22 J25 DDR_CKE0_DIMMB DDR_B_D55 AF15 AD15 DDR_A_D55
<9> DDR_CKE0_DIMMA MA_CKE0 MB_CKE0 DDR_CKE0_DIMMB <10> MB_DATA55 MA_DATA55
< To SO_DIMMA > <9> DDR_CKE1_DIMMA DDR_CKE1_DIMMA J20 DDR_CKE1_DIMMB DDR_B_D56 DDR_A_D56
MA_CKE1 MB_CKE1 H26 DDR_CKE1_DIMMB <10>< To SO_DIMMB > AF13 MB_DATA56 MA_DATA56 AB13
DDR_B_D57 AC12 AD13 DDR_A_D57
DDR_A_CLK0 DDR_B_CLK0 DDR_B_D58 MB_DATA57 MA_DATA57 DDR_A_D58
<9> DDR_A_CLK0 N19 MA_CLK_H5 MB_CLK_H5 P22 DDR_B_CLK0 <10> AB11 MB_DATA58 MA_DATA58 Y12
DDR_A_CLK#0 N20 R22 DDR_B_CLK#0 DDR_B_D59 Y11 W11 DDR_A_D59
<9> DDR_A_CLK#0 MA_CLK_L5 MB_CLK_L5 DDR_B_CLK#0 <10> MB_DATA59 MA_DATA59
E16 A17 DDR_B_D60 AE14 AB14 DDR_A_D60
MA_CLK_H1 MB_CLK_H1 DDR_B_D61 MB_DATA60 MA_DATA60 DDR_A_D61
F16 MA_CLK_L1 MB_CLK_L1 A18 < To SO_DIMMB > AF14 MB_DATA61 MA_DATA61 AA14
< To SO_DIMMA > Y16 AF18 DDR_B_D62 AF11 AB12 DDR_A_D62
MA_CLK_H7 MB_CLK_H7 DDR_B_D63 MB_DATA62 MA_DATA62 DDR_A_D63
AA16 MA_CLK_L7 MB_CLK_L7 AF17 AD11 MB_DATA63 MA_DATA63 AA12
DDR_A_CLK1 P19 R26 DDR_B_CLK1
<9> DDR_A_CLK1 MA_CLK_H4 MB_CLK_H4 DDR_B_CLK1 <10> <10> DDR_B_DM[7..0] DDR_A_DM[7..0] <9>
DDR_A_CLK#1 P20 R25 DDR_B_CLK#1 DDR_B_DM0 A12 E12 DDR_A_DM0
<9> DDR_A_CLK#1 MA_CLK_L4 MB_CLK_L4 DDR_B_CLK#1 <10> MB_DM0 MA_DM0
< To SO_DIMMA > <9> DDR_A_MA[15..0] < To SO_DIMMB > < To SO_DIMMB > DDR_B_DM1 B16 C15 DDR_A_DM1 < To SO_DIMMA >
DDR_B_MA[15..0] <10> MB_DM1 MA_DM1
DDR_A_MA0 N21 P24 DDR_B_MA0 DDR_B_DM2 A22 E19 DDR_A_DM2
DDR_A_MA1 MA_ADD0 MB_ADD0 DDR_B_MA1 DDR_B_DM3 MB_DM2 MA_DM2 DDR_A_DM3
M20 MA_ADD1 MB_ADD1 N24 E25 MB_DM3 MA_DM3 F24
DDR_A_MA2 N22 P26 DDR_B_MA2 DDR_B_DM4 AB26 AC24 DDR_A_DM4
3 DDR_A_MA3 MA_ADD2 MB_ADD2 DDR_B_MA3 DDR_B_DM5 MB_DM4 MA_DM4 DDR_A_DM5 3
M19 MA_ADD3 MB_ADD3 N23 AE22 MB_DM5 MA_DM5 Y19
DDR_A_MA4 M22 N26 DDR_B_MA4 DDR_B_DM6 AC16 AB16 DDR_A_DM6
DDR_A_MA5 MA_ADD4 MB_ADD4 DDR_B_MA5 DDR_B_DM7 MB_DM6 MA_DM6 DDR_A_DM7
L20 MA_ADD5 MB_ADD5 L23 AD12 MB_DM7 MA_DM7 Y13
DDR_A_MA6 M24 N25 DDR_B_MA6
DDR_A_MA7 MA_ADD6 MB_ADD6 DDR_B_MA7 DDR_B_DQS0 DDR_A_DQS0
L21 MA_ADD7 MB_ADD7 L24 <10> DDR_B_DQS0 C12 MB_DQS_H0 MA_DQS_H0 G13 DDR_A_DQS0 <9>
DDR_A_MA8 L19 M26 DDR_B_MA8 DDR_B_DQS#0 B12 H13 DDR_A_DQS#0
MA_ADD8 MB_ADD8 <10> DDR_B_DQS#0 MB_DQS_L0 MA_DQS_L0 DDR_A_DQS#0 <9>
DDR_A_MA9 K22 K26 DDR_B_MA9 DDR_B_DQS1 D16 G16 DDR_A_DQS1
MA_ADD9 MB_ADD9 <10> DDR_B_DQS1 MB_DQS_H1 MA_DQS_H1 DDR_A_DQS1 <9>
DDR_A_MA10 R21 T26 DDR_B_MA10 DDR_B_DQS#1 C16 G15 DDR_A_DQS#1
DDR_A_MA11 L22 L26 DDR_B_MA11 DDR_B_DQS2 A24 C22 DDR_A_DQS2
DDR_A_MA12 K20 L25 DDR_B_MA12 DDR_B_DQS#2 A23 C21 DDR_A_DQS#2
DDR_A_MA13 V24 W24 DDR_B_MA13 DDR_B_DQS3 F26 G22 DDR_A_DQS3
DDR_A_MA14 K24 J23 DDR_B_MA14 DDR_B_DQS#3 E26 G21 DDR_A_DQS#3
DDR_A_MA15 K19 J24 DDR_B_MA15 DDR_B_DQS4 AC25 AD23 DDR_A_DQS4
DDR_B_DQS#4 AC26 AC23 DDR_A_DQS#4
<10> DDR_B_DQS#4 MB_DQS_L4 MA_DQS_L4 DDR_A_DQS#4 <9>
DDR_A_BS#0 R20 R24 DDR_B_BS#0 DDR_B_DQS5 AF21 AB19 DDR_A_DQS5
<9> DDR_A_BS#0 MA_BANK0 MB_BANK0 DDR_B_BS#0 <10> <10> DDR_B_DQS5 MB_DQS_H5 MA_DQS_H5 DDR_A_DQS5 <9>
< To SO_DIMMA > <9> DDR_A_BS#1 DDR_A_BS#1 R23 U26 DDR_B_BS#1 < To SO_DIMMB > DDR_B_DQS#5 AF22 AB20 DDR_A_DQS#5
MA_BANK1 MB_BANK1 DDR_B_BS#1 <10> <10> DDR_B_DQS#5 MB_DQS_L5 MA_DQS_L5 DDR_A_DQS#5 <9>
DDR_A_BS#2 J21 J26 DDR_B_BS#2 DDR_B_DQS6 AE16 Y15 DDR_A_DQS6
<9> DDR_A_BS#2 MA_BANK2 MB_BANK2 DDR_B_BS#2 <10> <10> DDR_B_DQS6 MB_DQS_H6 MA_DQS_H6 DDR_A_DQS6 <9>
DDR_B_DQS#6 AD16 W15 DDR_A_DQS#6
<10> DDR_B_DQS#6 MB_DQS_L6 MA_DQS_L6 DDR_A_DQS#6 <9>
DDR_A_RAS# R19 U25 DDR_B_RAS# DDR_B_DQS7 AF12 W12 DDR_A_DQS7
<9> DDR_A_RAS# MA_RAS_L MB_RAS_L DDR_B_RAS# <10> <10> DDR_B_DQS7 MB_DQS_H7 MA_DQS_H7 DDR_A_DQS7 <9>
< To SO_DIMMA > DDR_A_CAS# T22 U24 DDR_B_CAS# < To SO_DIMMB > DDR_B_DQS#7 AE12 W13 DDR_A_DQS#7
<9> DDR_A_CAS# MA_CAS_L MB_CAS_L DDR_B_CAS# <10> <10> DDR_B_DQS#7 MB_DQS_L7 MA_DQS_L7 DDR_A_DQS#7 <9>
DDR_A_WE# T24 U23 DDR_B_WE#
<9> DDR_A_WE# MA_WE_L MB_WE_L DDR_B_WE# <10>
< From/To SO_DIMMB > < From/To SO_DIMMA >
4 4

SCHEMATIC,MB A6052
A B C D E
A B C D E
JCPUD
< Filtered PLL Supply Voltage > +1.5V_CPU
+2.5VDDA F8 M11
VDDA1 VSS
F9 VDDA2 RSVD11 W18
+2.5VS +2.5VDDA CPU_SVC 1K_0402_5% 1 2 R19
VDDA=300mA CPU_CLKIN_SC_P A9 A6 CPU_SVC
L1 1 CLKIN_H SVC CPU_SVC <50>
2 FBM_L11_201209_300L_0805 +2.5VDDA CPU_CLKIN_SC_N A8 CLKIN_L SVD A4 CPU_SVD
CPU_SVD <50>
CPU_SVD 1K_0402_5% 1 2 R20
1 1 1 1
C12 C13 C14 LDT_RST# B7 < Serial VID Interface clock & data >
+ C11 H_PWRGD RESET_L R11
A7 PWROK
@ 4.7U_0805_10V4Z 3300P_0402_50V7-K 0.22U_0603_16V4Z LDT_STOP# F10 AF6 CPU_THERMTRIP#_R +1.5V_CPU 1 2 300_0402_5%
150U_B2_6.3VM_R45M 2 2 2 LDTSTOP_L THERMTRIP_L
T2 PAD C6 LDTREQ_L PROCHOT_L AC7 CPU_PROCHOT#
2 @R13
@ R13
MEMHOT_L AA8 PAD T3
+1.5V_CPU 1 2 CPU_SIC AF4 CPU_PROCHOT# 1 2 0_0402_5%
SIC H_PROCHOT# <20>
+1.5V_CPU R12 1 2 1K_0402_5% CPU_SID AF5
1 R14 1K_0402_5% SID THERMDC_CPU 1
AE6 ALERT_L THERMDC W7
W8 THERMDA_CPU
R15 CPU_HTREF0 THERMDA
< 200-MHz PLL Reference Clock > 1 2 44.2_0402_1% R6 HT_REF0
C16 +1.1VS R16 1 2 44.2_0402_1% CPU_HTREF1 P6 HT_REF1
<16> CLK_CPU_BCLK 1 2 3900P_0402_50V7K CPU_CLKIN_SC_P route as differential
CPU_VDD0_RUN_FB_H F6 W9 as short as possible
<50> CPU_VDD0_RUN_FB_H VDD0_FB_H VDDIO_FB_H testpoint under package
<50> CPU_VDD0_RUN_FB_L CPU_VDD0_RUN_FB_L E6 Y9
VDD0_FB_L VDDIO_FB_L
1
R10 <50> CPU_VDD1_RUN_FB_H CPU_VDD1_RUN_FB_H Y6 H6 CPU_VDDNB_RUN_FB_H
VDD1_FB_H VDDNB_FB_H CPU_VDDNB_RUN_FB_H <50>
<50> CPU_VDD1_RUN_FB_L CPU_VDD1_RUN_FB_L AB6 G6 CPU_VDDNB_RUN_FB_L
VDD1_FB_L VDDNB_FB_L CPU_VDDNB_RUN_FB_L <50>
169_0402_1%
CPU_DBRDY G10
2
C15 CPU_TMS DBRDY CPU_DBREQ#
AA9 TMS DBREQ_L E10
<16> CLK_CPU_BCLK# 1 2 3900P_0402_50V7K CPU_CLKIN_SC_N CPU_TCK AC9 TCK
CPU_TRST# AD9 AE9 CPU_TDO
CPU_TDI TRST_L TDO
Address:100_1100 Place close to CPU wihtin 1.5" AF9 TDI
CPU_TEST23 AD7 J7 R6
TEST23 TEST28_H 10K_0402_5%
TEST28_L H8 +1.5V_CPU 1 2
CPU_TEST18 H10
CPU_TEST19 TEST18 CPU_TEST17
G9 TEST19 TEST17 D7 PAD T4
E7 CPU_TEST16
TEST16 PAD T5
CPU_TEST25H E9 F7 CPU_TEST15 R7 1 2 1K_0402_5%
TEST25_H TEST15 PAD T6
2
B
CPU_TEST25L E8 C7 CPU_TEST14 Q1
TEST25_L TEST14 PAD T7
E
CPU_TEST21 AB8 C3 CPU_THERMTRIP#_R 3 1
TEST21 TEST7 H_THERMTRIP# <21>
C
CPU_TEST20 AF7 K8
CPU_TEST24 TEST20 TEST10 MMBT3904_NL_SOT23-3
AE7 TEST24
CPU_TEST22 AE8 C4
CPU_TEST12 TEST22 TEST8
AC8 TEST12
CPU_TEST27 AF8 TEST27 CPU_TEST29_H_FBCLKOUT_P
TEST29_H C9
2 CPU_TEST29_L_FBCLKOUT_N 2
1 2 R24 C2 TEST9 TEST29_L C8 2 1
+1.5V_CPU 0_0402_5% AA6 R25 80.6_0402_1%
TEST6
A3 RSVD1 RSVD10 H18
R22 2 1 510_0402_5% CPU_TEST25H A5 H19
RSVD2 RSVD9
B3 RSVD3 RSVD8 AA7
2 1 CPU_TEST27 B5 D5
R28 1K_0402_5% RSVD4 RSVD7
C1 RSVD5 RSVD6 C5
R27 1 2 510_0402_5% CPU_TEST25L

R29 2 1 1K_0402_5% CPU_TEST12
R30 2 1 1K_0402_5% CPU_TEST18
R31 2 1 1K_0402_5% CPU_TEST19
R32 2 1 1K_0402_5% CPU_TEST20
R33 2 1 1K_0402_5% CPU_TEST21
R34 2 1 1K_0402_5% CPU_TEST22
R265 2 1 1K_0402_5% CPU_TEST23
R35 2 1 1K_0402_5% CPU_TEST24
+1.5VS
2
3 3
R17
300_0402_5%
1
LDT_RST#
<20> LDT_RST#
1
C17 < HDT Connector >
@
0.01U_0402_25V7K JP2
2
1 2
3 4
CPU_DBREQ# 5 6
+1.5VS +1.5V_CPU R40 1 2 300_0402_5% 7 8
CPU_DBRDY
R39 220_0402_5% CPU_TCK 9 10
1 2 11 12
R38 1 2 220_0402_5% CPU_TMS
13 14
2
R37 1 2 220_0402_5% CPU_TDI

R21 R36 220_0402_5% CPU_TRST# 15 16
+1.5V_CPU 1 2 17 18
CPU_TDO
300_0402_5% 19 20
+1.5V_CPU
21 22 LDT_RST# +3VS < Thermal Sensor >
1
H_PWRGD 23 24 U1
<20,50> H_PWRGD 26 EC_SMB_CK2
1 1 VDD SCLK 8 EC_SMB_CK2 <31,43>
C19 1
@ @ SAMTEC_ASP-68200-07 C20 THERMDA_CPU 2 7 EC_SMB_DA2
D+ SDATA EC_SMB_DA2 <31,43>
0.1U_0402_16V7K
2 0.1U_0402_16V7K 1 2 C21 THERMDC_CPU 3 D- ALERT# 6
2 3300P_0402_50V7-K
4 THERM# GND 5
< noise filter cap >
+1.5VS
4 ADM1032ARM-1 ZREEL_MSOP8 4
2
R18
300_0402_5%
1
LDT_STOP#
<12,20> LDT_STOP#
1
C18
@
2
0.01U_0402_25V7K
SCHEMATIC,MB A6052
A B C D E
A B C D E
+CPU_CORE JCPUE +CPU_CORE

VDD decoupling : +CPU_CORE G4 P8
VDD0_1 VDD1_1
H2 VDD0_2 VDD1_2 P10
+CPU_CORE +CPU_CORE +CPU_CORE J9 R4
VDD0_3 VDD1_3
J11 VDD0_4 VDD1_4 R7
J13 VDD0_5 VDD1_5 R9
1 1 1 1 1 1 1 1 1 J15 VDD0_6 VDD1_6 R11
C35 C34 C28 C29 C36 C37 C38 K6 T2
+ C26 + C25 VDD0_7 VDD1_7
K10 VDD0_8 VDD1_8 T6
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 0.22U_0603_16V4Z 0.01U_0402_25V7K 180P_0402_50V8J K12 T8
330U_X_2VM_R6M 330U_X_2VM_R6M 2 2 2 2 2 2 2 VDD0_9 VDD1_9
K14 VDD0_10 VDD1_10 T10
2 2
L4 VDD0_11 VDD1_11 T12
Near CPU Socket Under CPU Socket Under CPU Socket L7 VDD0_12 VDD1_12 T14
L9 VDD0_13 VDD1_13 U7
1 1
L11 VDD0_14 VDD1_14 U9
L13 VDD0_15 VDD1_15 U11
+CPU_CORE +CPU_CORE +CPU_CORE L15 U13
VDD0_16 VDD1_16
M2 VDD0_17 VDD1_17 U15
M6 VDD0_18 VDD1_18 V6
330U_X_2VM_R6M
330U_X_2VM_R6M
330U_2.5V_M
330U_2.5V_M
1 1 1 1 1 1 1 1 1 1 1 M8 VDD0_19 VDD1_19 V8
C30 C31 C32 C33 C39 C40 C41 M10 V10
+@ + C89 + @C24 + C90 VDD0_20 VDD1_20
N7 VDD0_21 VDD1_21 V12
C23 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 0.22U_0603_16V4Z 0.01U_0402_25V7K 180P_0402_50V8J N9 V14
2 2 2 2 2 2 2 +VDDNB VDD0_22 VDD1_22
N11 VDD0_23 VDD1_23 W4
2 2 2 2
VDD1_24 Y2
Near CPU Socket Under CPU Socket Under CPU Socket K16 VDDNB_1 VDD1_25 AC4
M16 AD2 +1.5V_CPU
VDDNB_2 VDD1_26
P16 VDDNB_3
T16 VDDNB_4 VDDIO27 Y25
+1.5V_CPU V16 V25
VDDNB_5 VDDIO26
VDDIO decoupling : DDR SDRAM I/O ring power H25
VDDIO25 V23
V21
+1.5V_CPU VDDIO1 VDDIO24
J17 VDDIO2 VDDIO23 V18
K18 VDDIO3 VDDIO22 U17
K21 VDDIO4 VDDIO21 T25
1 1 1 1 1 1 K23 VDDIO5 VDDIO20 T23
C44 C45 C46 C47 C48 C50 K25 T21
VDDIO6 VDDIO19
L17 VDDIO7 VDDIO18 T18
22U_0805_6.3V6M 22U_0805_6.3V6M 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J M18 R17
2 2 2 2 2 2 VDDIO8 VDDIO17
M21 VDDIO9 VDDIO16 P25
Under CPU Socket M23 VDDIO10 VDDIO15 P23
M25 VDDIO11 VDDIO14 P21
N17 VDDIO12 VDDIO13 P18
+1.5V_CPU
2 2
1 1 1 1
C54 C51 C52 C53
JCPUF
0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z AA4 J6
2 2 2 2 VSS1 VSS66
AA11 VSS2 VSS67 J8
Between CPU Socket and DIMM AA13 VSS3 VSS68 J10
AA15 VSS4 VSS69 J12
AA17 VSS5 VSS70 J14
+1.5V_CPU AA19 J16
VSS6 VSS71
AB2 VSS7 VSS72 J18
AB7 VSS8 VSS73 K2
1 1 AB9 VSS9 VSS74 K7
C64 C65 AB23 K9
VSS10 VSS75
AB25 VSS11 VSS76 K11
0.01U_0402_25V7K 0.01U_0402_25V7K AC11 K13
2 2 VSS12 VSS77
AC13 VSS13 VSS78 K15
Between CPU Socket and DIMM C56 Co-layout with C75 AC15 VSS14 VSS79 K17
AC17 VSS15 VSS80 L6
AC19 VSS16 VSS81 L8
+1.5V_CPU AC21 L10
+1.5V_CPU VSS17 VSS82
AD6 VSS18 VSS83 L12
180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch> 1 AD8 L14
VSS19 VSS84
AD25 VSS20 VSS85 L16
C56 + AE11 L18
1 1 1 1 VSS21 VSS86
C66 C67 C68 C69 AE13 M7
390U_2.5V_M_R10 VSS22 VSS87
2 C1124 Co-layout with C1125 AE15 VSS23 VSS88 M9
180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J AE17 AC6
2 2 2 2 VSS24 VSS89
AE19 VSS25 VSS90 M17
Between CPU Socket and DIMM +1.05VS AE21 N4
VSS26 VSS91
AE23 VSS27 VSS92 N8
1 B4 VSS28 VSS93 N10
+1.5V_CPU B6 N16
3 + C1124 VSS29 VSS94 3
B8 VSS30 VSS95 N18
1 390U_2.5V_M_R10 B9 P2
VSS31 VSS96
1 1 1 1 B11 VSS32 VSS97 P7
C71 C72 C73 C74 + C75 2
B13 VSS33 VSS98 P9
@ B15 P11
4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z VSS34 VSS99
B17 VSS35 VSS100 P17
2 2 2 2 2 330U_D2E_2.5VM_R6M
B19 VSS36 VSS101 R8
Between CPU Socket and DIMM B21 VSS37 VSS102 R10
B23 VSS38 VSS103 R16
B25 VSS39 VSS104 R18
D6 VSS40 VSS105 T7
D8 VSS41 VSS106 T9
+1.05VS
VDDR decoupling. D9
D11
VSS42 VSS107 T11
T13
VSS43 VSS108
D13 VSS44 VSS109 T15
1 1 1 1 1 1 1 1 D15 VSS45 VSS110 T17
C57 C58 C59 C60 C61 C62 C63 C70 D17 U4
VSS46 VSS111
D19 VSS47 VSS112 U6
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J +1.05VS D21 U8
2 2 2 2 2 2 2 2 VSS48 VSS113
D23 VSS49 VSS114 U10
330U_D2E_2.5VM
Near CPU Socket Right side @ 1 D25 U12

+1.05VS VSS50 VSS115
E4 VSS51 VSS116 U14
C1125
+ F2 U16
VSS52 VSS117
F11 VSS53 VSS118 U18
1 1 1 1 1 1 1 1 F13 VSS54 VSS119 V2
C76 C77 C78 C79 C80 C81 C82 C83 2
F15 VSS55 VSS120 V7
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J F17 V9
VSS56 VSS121
F19 VSS57 VSS122 V11
2 2 2 2 2 2 2 2
Near CPU Socket Left side F23 VSS59 VSS124 V15
H7 VSS61 VSS126 W6
4 4
H9 VSS62 VSS127 Y21
H21 VSS63 VSS128 Y23
+VDDNB decoupling : Northbridge power H23
J4
VSS64 VSS129 N6
+VDDNB VSS65
1 1 1
C42 C43 C49 Security Classification Compal Secret Data Compal Electronics, Inc.
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2
SCHEMATIC,MB A6052
A B C D E
A B C D E
+1.5V_RAM +1.5V_RAM
JDDRL
+VREF_DQ 1 VREF_DQ VSS1 2
3 4 DDR_A_D4
4.7U_0805_10V4Z VSS2 DQ4
0.01U_0402_25V7K
1000P_0402_25V8J
DDR_A_D0 5 6 DDR_A_D5
DDR_A_D1 DQ0 DQ5
7 DQ1 VSS3 8
1 2 1 9 10 DDR_A_DQS#0
VSS4 DQS#0 DDR_A_DQS#0 <6>
C84 C85 C10 DDR_A_DM0 11 12 DDR_A_DQS0
DM0 DQS0 DDR_A_DQS0 <6> DDR_A_D[0..63]
13 VSS5 VSS6 14 DDR_A_D[0..63] <6>
2 1 2 DDR_A_D3 DQ2 DQ6 DDR_A_D7 DDR_A_DM[0..7]
17 DQ3 DQ7 18 DDR_A_DM[0..7] <6>
19 VSS7 VSS8 20
1 DDR_A_D8 DDR_A_D12 1
21 DQ8 DQ12 22
DQ9 DQ13 DDR_A_MA[0..15]
25 VSS9 VSS10 26 DDR_A_MA[0..15] <6>
DDR_A_DQS#1 27 28 DDR_A_DM1
<6> DDR_A_DQS#1 DQS#1 DM1
DDR_A_DQS1 29 30 MEM_MA_RST#
<6> DDR_A_DQS1 DQS1 RESET# MEM_MA_RST# <6>
31 VSS11 VSS12 32
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_A_DQS2 47 48
<6> DDR_A_DQS2 DQS2 VSS17
49 50 DDR_A_D22
DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 VSS20 DQ28 56
DDR_A_D24 57 58 DDR_A_D29 +1.5V_RAM
DDR_A_D25 DQ24 DQ29 +1.5V_RAM
59 DQ25 VSS21 60
61 62 DDR_A_DQS#3
2
DDR_A_DM3 63 64 DDR_A_DQS3
DM3 DQS3 DDR_A_DQS3 <6>
2
65 66 R310
DDR_A_D26 VSS23 VSS24 DDR_A_D30 R48 1K_0402_1%
67 DQ26 DQ30 68
DDR_A_D27 69 70 DDR_A_D31 1K_0402_1%
DQ27 DQ31
71 72
1
VSS25 VSS26
1
+VREF_DQ +VREF_CA
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
<6> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <6>
75 VDD1 VDD2 76
2
77 78 DDR_A_MA15
NC1 A15
2
2 DDR_A_BS#2 DDR_A_MA14 R315 2
<6> DDR_A_BS#2 79 BA2 A14 80
81 82 R49 1K_0402_1%
DDR_A_MA12 VDD3 VDD4 DDR_A_MA11 1K_0402_1%
83 A12/BC# A11 84
DDR_A_MA9 85 86 DDR_A_MA7
1
A9 A7
87 88
1
DDR_A_MA8 VDD5 VDD6 DDR_A_MA6
89 A8 A6 90
A5 A4
93 VDD7 VDD8 94
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD9 VDD10 100
DDR_A_CLK0 101 102 DDR_A_CLK1 < Close to JDDRH & JDDRL >
<6> DDR_A_CLK0 CK0 CK1 DDR_A_CLK1 <6>
DDR_A_CLK#0 103 104 DDR_A_CLK#1
<6> DDR_A_CLK#0 CK0# CK1# DDR_A_CLK#1 <6>
105 VDD11 VDD12 106
DDR_A_MA10 107 108 DDR_A_BS#1
A10/AP BA1 DDR_A_BS#1 <6>
DDR_A_BS#0 109 110 DDR_A_RAS#
<6> DDR_A_BS#0 BA0 RAS# DDR_A_RAS# <6>
111 VDD13 VDD14 112
DDR_A_WE# 113 114 DDR_CS0_DIMMA#
<6> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <6>
DDR_A_CAS# 115 116 DDR_A_ODT0
<6> DDR_A_CAS# CAS# ODT0 DDR_A_ODT0 <6>
117 VDD15 VDD16 118
DDR_A_MA13 119 120 DDR_A_ODT1
A13 ODT1 DDR_A_ODT1 <6>
DDR_CS1_DIMMA# 121 122
<6> DDR_CS1_DIMMA# S1# NC2
123 VDD17 VDD18 124
125 NCTEST VREF_CA 126 +VREF_CA
127 VSS27 VSS28 128
1000P_0402_25V8J
0.01U_0402_25V7K
4.7U_0805_10V4Z
DDR_A_D32 129 130 DDR_A_D36
131 DQ33 DQ37 132
133 VSS29 VSS30 134 1 1 2
DDR_A_DQS#4 135 136 DDR_A_DM4 C235 C351 +1.5V_RAM
DDR_A_DQS4 137 138 C680
139 140 DDR_A_D38 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDR_A_D34 VSS32 DQ38 DDR_A_D39 2 2 1
141 DQ34 DQ39 142 2 2 2 2 2 2 2 2 2 2
3 DDR_A_D35 3
143 DQ35 VSS33 144
145 146 DDR_A_D44 C87 C88 C640 C641 C642 C643 C644 C645 C646 C647
DDR_A_D40 VSS34 DQ44 DDR_A_D45 0.1U_0402_16V4Z
147 DQ40 DQ45 148
DDR_A_D41 1 1 1 1 1 1 1 1 1 1
149 DQ41 VSS35 150
151 152 DDR_A_DQS#5 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDR_A_DM5 153 154 DDR_A_DQS5
155 VSS37 VSS38 156
DDR_A_D42 157 158 DDR_A_D46
159 DQ43 DQ47 160
161 VSS39 VSS40 162
DDR_A_D48 163 164 DDR_A_D52
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_A_DQS6 171 172
173 174 DDR_A_D54
DDR_A_D50 VSS44 DQ54 DDR_A_D55 J3
175 DQ50 DQ55 176
DDR_A_D51 177 178 +1.5V 2 1 +1.5V_RAM
DQ51 VSS45 DDR_A_D60 2 1
179 VSS46 DQ60 180
DDR_A_D56 181 182 DDR_A_D61 +0.75VS @ JUMP_43X118
DDR_A_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_A_DQS#7 0.1U_0402_16V4Z
DDR_A_DM7 187 188 DDR_A_DQS7 2 2 1
189 VSS49 VSS50 190
DDR_A_D58 191 192 DDR_A_D62 C665 C664 C961
193 DQ59 DQ63 194
1 1 2
195 VSS51 VSS52 196
197 198 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
SA0 EVENT#
+3VS 199 VDDSPD SDA 200 SMB_CK_DAT0 <10,16,21>
201 SA1 SCL 202 SMB_CK_CLK0 <10,16,21>
+0.75VS 203 VTT1 VTT2 204 +0.75VS Place near DIMM1
1
4 C91 4
205 G1 G2 206
TYCO_2-2013289-1
0.1U_0402_16V4Z 2

2008-09-25 2009-09-25 Title
DIMM_A STD H:5.2 mm Issued Date Deciphered Date
SCHEMATIC,MB A6052
<Address: 00> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A B C D E
A B C D E
+1.5V_RAM +1.5V_RAM
JDDRH
+VREF_DQ 1 VREF_DQ VSS1 2
3 4 DDR_B_D4
DDR_B_D0 VSS2 DQ4 DDR_B_D5
5 DQ0 DQ5 6
4.7U_0805_10V4Z
0.1U_0402_16V4Z
1000P_0402_25V8J
DDR_B_D1 7 8
DQ1 VSS3 DDR_B_DQS#0
9 VSS4 DQS#0 10 DDR_B_DQS#0 <6>
1 1 1 DDR_B_DM0 11 12 DDR_B_DQS0
DM0 DQS0 DDR_B_DQS0 <6> DDR_B_D[0..63]
C92 C93 C682 13 14
DDR_B_D2 VSS5 VSS6 DDR_B_D6 DDR_B_D[0..63] <6>
15 DQ2 DQ6 16
DDR_B_D3 17 18 DDR_B_D7 DDR_B_DM[0..7]
2 2 2 DQ3 DQ7 DDR_B_DM[0..7] <6>
19 VSS7 VSS8 20
1 DDR_B_D8 DDR_B_D12 1
21 DQ8 DQ12 22
DDR_B_D9 23 24 DDR_B_D13 DDR_B_MA[0..15] <6>
DQ9 DQ13 DDR_B_MA[0..15]
25 VSS9 VSS10 26
DDR_B_DQS#1 27 28 DDR_B_DM1
<6> DDR_B_DQS#1 DQS#1 DM1
DDR_B_DQS1 29 30 MEM_MB_RST#
<6> DDR_B_DQS1 DQS1 RESET# MEM_MB_RST# <6>
31 VSS11 VSS12 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_B_DQS2 47 48
<6> DDR_B_DQS2 DQS2 VSS17
49 50 DDR_B_D22
51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS19 DDR_B_D28
55 VSS20 DQ28 56
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_B_DQS#3
VSS22 DQS#3 DDR_B_DQS#3 <6>
DDR_B_DM3 63 64 DDR_B_DQS3
DM3 DQS3 DDR_B_DQS3 <6>
65 VSS23 VSS24 66
69 DQ27 DQ31 70
71 VSS25 VSS26 72
DDR_CKE0_DIMMB 73 74 DDR_CKE1_DIMMB
<6> DDR_CKE0_DIMMB CKE0 CKE1 DDR_CKE1_DIMMB <6>
75 VDD1 VDD2 76
77 78 DDR_B_MA15
2 DDR_B_BS#2 NC1 A15 DDR_B_MA14 2
<6> DDR_B_BS#2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD9 VDD10 100
DDR_B_CLK0 101 102 DDR_B_CLK1
<6> DDR_B_CLK0 CK0 CK1 DDR_B_CLK1 <6>
DDR_B_CLK#0 103 104 DDR_B_CLK#1
<6> DDR_B_CLK#0 CK0# CK1# DDR_B_CLK#1 <6>
105 VDD11 VDD12 106
DDR_B_MA10 107 108 DDR_B_BS#1
A10/AP BA1 DDR_B_BS#1 <6>
DDR_B_BS#0 109 110 DDR_B_RAS#
<6> DDR_B_BS#0 BA0 RAS# DDR_B_RAS# <6>
111 VDD13 VDD14 112
DDR_B_WE# 113 114 DDR_CS0_DIMMB#
<6> DDR_B_WE# WE# S0# DDR_CS0_DIMMB# <6>
DDR_B_CAS# 115 116 DDR_B_ODT0
<6> DDR_B_CAS# CAS# ODT0 DDR_B_ODT0 <6>
117 VDD15 VDD16 118
DDR_B_MA13 119 120 DDR_B_ODT1
A13 ODT1 DDR_B_ODT1 <6>
DDR_CS1_DIMMB# 121 122
<6> DDR_CS1_DIMMB# S1# NC2
123 VDD17 VDD18 124
125 NCTEST VREF_CA 126 +VREF_CA
127 VSS27 VSS28 128
1000P_0402_25V8J
4.7U_0805_10V4Z
0.1U_0402_16V4Z
DDR_B_D32 129 130 DDR_B_D36
131 DQ33 DQ37 132
133 VSS29 VSS30 134 1 1 1
DDR_B_DQS4 137 138
<6> DDR_B_DQS4 DQS4 VSS31
139 140 DDR_B_D38 C683 C352 C353
DDR_B_D34 VSS32 DQ38 DDR_B_D39 2 2 2
141 DQ34 DQ39 142
3 DDR_B_D35 3
143 DQ35 VSS33 144
145 146 DDR_B_D44
147 DQ40 DQ45 148
DDR_B_D41 149 150
DQ41 VSS35 DDR_B_DQS#5
151 VSS36 DQS#5 152 DDR_B_DQS#5 <6>
DDR_B_DM5 153 154 DDR_B_DQS5
155 VSS37 VSS38 156
DDR_B_D42 157 158 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47 +1.5V_RAM
159 DQ43 DQ47 160
161 VSS39 VSS40 162
DDR_B_D48 163 164 DDR_B_D52 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
165 DQ49 DQ53 166 2 2 2 2 2 2 2 2 2 2
167 VSS41 VSS42 168
DDR_B_DQS#6 169 170 DDR_B_DM6 C666 C667 C668 C669 C670 C671 C672 C673 C674 C677
DDR_B_DQS6 171 172
<6> DDR_B_DQS6 DQS6 VSS43 1 1 1 1 1 1 1 1 1 1
173 174 DDR_B_D54
DDR_B_D50 VSS44 DQ54 DDR_B_D55 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
175 DQ50 DQ55 176
DDR_B_D51 177 178
DQ51 VSS45 DDR_B_D60
179 VSS46 DQ60 180
DDR_B_D56 181 182 DDR_B_D61
DDR_B_D57 DQ56 DQ61
183 DQ57 VSS47 184 C128 Co-layout with C86
185 186 DDR_B_DQS#7
VSS48 DQS#7 DDR_B_DQS#7 <6>
DDR_B_DM7 187 188 DDR_B_DQS7 +0.75VS
189 190 +1.5V_RAM +1.5V_RAM
DDR_B_D58 VSS49 VSS50 DDR_B_D62 0.1U_0402_16V4Z
191 DQ58 DQ62 192
DDR_B_D59 193 194 DDR_B_D63 2 2 1 1 1
DQ59 DQ63 @
195 VSS51 VSS52 196
197 198 C676 C675 C925 + C86 + C128
SA0 EVENT# 330U_X_2VM_R6M 390U_2.5V_M_R10
+3VS 199 VDDSPD SDA 200 SMB_CK_DAT0 <9,16,21> 1 1 2
201 SA1 SCL 202 SMB_CK_CLK0 <9,16,21>
0.1U_0402_16V4Z 4.7U_0603_6.3V6K 2 2
+0.75VS 203 VTT1 VTT2 204 +0.75VS
4 4
205 G1 G2 206
Place near DIMM2
LOTES_AAA-DDR-111-K01

DIMM_B STD H:9.2 mm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A6052
<Address: 01> DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401851 A
A B C D E
A B C D E
U3B
PCIE_GTX_C_MRX_P[0..15] PCIE_GTX_C_MRX_N0 D4 A5 PCIE_MTX_GRX_P0 C95 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_P[0..15]
<35> PCIE_GTX_C_MRX_P[0..15] GFX_RX0P GFX_TX0P PCIE_MTX_C_GRX_P[0..15] <35>
PCIE_GTX_C_MRX_P0 C4 PART 2 OF 6 B5 PCIE_MTX_GRX_N0 C96 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
PCIE_GTX_C_MRX_N[0..15] PCIE_GTX_C_MRX_P1 GFX_RX0N GFX_TX0N PCIE_MTX_GRX_P1 C97 0.1U_0402_16V7K PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_N[0..15]
<35> PCIE_GTX_C_MRX_N[0..15] A3 GFX_RX1P GFX_TX1P A4 1 2 PCIE_MTX_C_GRX_N[0..15] <35>
PCIE_GTX_C_MRX_N1 B3 B4 PCIE_MTX_GRX_N1 C98 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
PCIE_GTX_C_MRX_N2 GFX_RX1N GFX_TX1N PCIE_MTX_GRX_P2 C99 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2
C2 GFX_RX2P GFX_TX2P C3 1 2
PCIE_GTX_C_MRX_P2 C1 B2 PCIE_MTX_GRX_N2 C100 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
PCIE_GTX_C_MRX_N3 GFX_RX2N GFX_TX2N PCIE_MTX_GRX_P3 C101 0.1U_0402_16V7K PCIE_MTX_C_GRX_N3
E5 GFX_RX3P GFX_TX3P D1 1 2
PCIE_GTX_C_MRX_P3 F5 D2 PCIE_MTX_GRX_N3 C102 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3
G5 GFX_RX4P GFX_TX4P E2 1 2
PCIE_GTX_C_MRX_P4 G6 E1 PCIE_MTX_GRX_N4 C104 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4
H5 GFX_RX5P GFX_TX5P F4 1 2
PCIE_GTX_C_MRX_P5 H6 F3 PCIE_MTX_GRX_N5 C106 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N5
PCIE_GTX_C_MRX_P6 GFX_RX5N GFX_TX5N PCIE_MTX_GRX_P6 C107 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
J6 GFX_RX6P GFX_TX6P F1 1 2
1 PCIE_GTX_C_MRX_N6 PCIE_MTX_GRX_N6 C108 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6 1
J5 GFX_RX6N GFX_TX6N F2 1 2
PCIE_GTX_C_MRX_N7 J7 H4 PCIE_MTX_GRX_P7 C109 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P7
PCIE_GTX_C_MRX_P7 GFX_RX7P GFX_TX7P PCIE_MTX_GRX_N7 C110 0.1U_0402_16V7K PCIE_MTX_C_GRX_N7
J8 GFX_RX7N GFX_TX7N H3 1 2
PCIE_GTX_C_MRX_N8 L5 H1 PCIE_MTX_GRX_P8 C111 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
L6 GFX_RX8N GFX_TX8N H2 1 2
PCIE_GTX_C_MRX_N9 M8 J2 PCIE_MTX_GRX_P9 C113 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
L8 GFX_RX9N GFX_TX9N J1 1 2
PCIE I/F GFX

PCIE_GTX_C_MRX_N10 P7 K4 PCIE_MTX_GRX_P10 C115 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
M7 GFX_RX10N GFX_TX10N K3 1 2
PCIE_GTX_C_MRX_N11 P5 K1 PCIE_MTX_GRX_P11 C117 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11
M5 GFX_RX11N GFX_TX11N K2 1 2
PCIE_GTX_C_MRX_N12 R8 M4 PCIE_MTX_GRX_P12 C119 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12
PCIE_GTX_C_MRX_P12 GFX_RX12P GFX_TX12P PCIE_MTX_GRX_N12 C120 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
P8 GFX_RX12N GFX_TX12N M3 1 2
PCIE_GTX_C_MRX_N13 R6 M1 PCIE_MTX_GRX_P13 C121 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P13
R5 GFX_RX13N GFX_TX13N M2 1 2
PCIE_GTX_C_MRX_N14 P4 N2 PCIE_MTX_GRX_P14 C123 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14
PCIE_GTX_C_MRX_P14 GFX_RX14P GFX_TX14P PCIE_MTX_GRX_N14 C124 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
P3 GFX_RX14N GFX_TX14N N1 1 2
PCIE_GTX_C_MRX_N15 T4 P1 PCIE_MTX_GRX_P15 C125 1 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P15
T3 GFX_RX15N GFX_TX15N P2 1 2
AE3 GPP_RX0P GPP_TX0P AC1

AD4 GPP_RX0N GPP_TX0N AC2
AE2 GPP_RX1P GPP_TX1P AB4
AD3 GPP_RX1N GPP_TX1N AB3
AD1 AA2 PCIE_ITX_PRX_P2 C129 1 2 0.1U_0402_16V7K
<28> PCIE_PTX_C_IRX_P2 GPP_RX2P GPP_TX2P PCIE_ITX_C_PRX_P2 <28>
< To WLAN > PCIE_ITX_PRX_N2 C130 0.1U_0402_16V7K
<28> PCIE_PTX_C_IRX_N2 AD2 GPP_RX2N PCIE I/F GPP GPP_TX2N AA1 1 2 PCIE_ITX_C_PRX_N2 <28>< To WLAN >
V5 Y1 PCIE_ITX_PRX_P3 C131 1 2 0.1U_0402_16V7K
<26> PCIE_PTX_C_IRX_P3 GPP_RX3P GPP_TX3P PCIE_ITX_C_PRX_P3 <26>
< To LAN > PCIE_ITX_PRX_N3 C132 0.1U_0402_16V7K
<26> PCIE_PTX_C_IRX_N3 W6 GPP_RX3N GPP_TX3N Y2 1 2 PCIE_ITX_C_PRX_N3 <26>< To LAN >
U5 GPP_RX4P GPP_TX4P Y4
U6 GPP_RX4N GPP_TX4N Y3
U8 GPP_RX5P GPP_TX5P V1
U7 GPP_RX5N GPP_TX5N V2
2 2
<20> SB_RX0P AA8 AD7 SB_TX0P_C C133 1 2 0.1U_0402_16V7K

SB_RX0P SB_TX0P SB_TX0P <20>
<20> SB_RX0N Y8 AE7 SB_TX0N_C C134 1 2 0.1U_0402_16V7K
SB_RX0N SB_TX0N SB_TX0N <20>
< From SB820 : x4 PCIE A-link > <20> SB_RX1P AA7 AE6 SB_TX1P_C C135 1 2 0.1U_0402_16V7K
<20> SB_RX1N Y7 AD6 SB_TX1N_C C136 1 2 0.1U_0402_16V7K < To SB820 : x4 PCEI A-link>
<20> SB_RX2P AA5 PCIE I/F SB AB6 SB_TX2P_C C137 1 2 0.1U_0402_16V7K
<20> SB_RX2N AA6 AC6 SB_TX2N_C C138 1 2 0.1U_0402_16V7K
<20> SB_RX3P W5 AD5 SB_TX3P_C C139 1 2 0.1U_0402_16V7K
<20> SB_RX3N Y5 AE5 SB_TX3N_C C140 1 2 0.1U_0402_16V7K
AC8 PCIE_CALRP R59 1 2 1.27K_0402_1% < TX Impedance Calibration. Connect to GND >
PCE_CALRP(PCE_BCALRP) PCIE_CALRN R58 2K_0402_1% < RX Impedance Calibration. Connect to VDDPCIE >
PCE_CALRN(PCE_BCALRN) AB8 1 2 +1.1VS
880MR1@ RS780M_FCBGA528
U3A
H_CADOP[0..15] H_CADOP0 Y25 D24 H_CADIP0 H_CADIP[0..15]
H_CADOP[0..15] <5> HT_RXCAD0P HT_TXCAD0P H_CADIP[0..15] <5>
H_CADON0 Y24 PART 1 OF 6 D25 H_CADIN0
H_CADON[0..15] H_CADOP1 HT_RXCAD0N HT_TXCAD0N H_CADIP1 H_CADIN[0..15]
H_CADON[0..15] <5> V22 HT_RXCAD1P HT_TXCAD1P E24 H_CADIN[0..15] <5>
H_CADON1 V23 E25 H_CADIN1
H_CADOP2 HT_RXCAD1N HT_TXCAD1N H_CADIP2
V25 HT_RXCAD2P HT_TXCAD2P F24
H_CADON2 V24 F25 H_CADIN2
U24 HT_RXCAD3P HT_TXCAD3P F23
H_CADON3 U25 F22 H_CADIN3
T25 HT_RXCAD4P HT_TXCAD4P H23
H_CADON4 T24 H22 H_CADIN4
HT_RXCAD4N HT_TXCAD4N
HYPER TRANSPORT CPU I/F
H_CADOP5 P22 J25 H_CADIP5

H_CADON5 HT_RXCAD5P HT_TXCAD5P H_CADIN5
P23 HT_RXCAD5N HT_TXCAD5N J24
H_CADOP6 P25 K24 H_CADIP6
P24 HT_RXCAD6N HT_TXCAD6N K25
H_CADOP7 N24 K23 H_CADIP7
N25 HT_RXCAD7N HT_TXCAD7N K22
3 3
< From S1G4 CPU : x16 HT> < To S1G4 CPU : x16 HT>
H_CADOP8 AC24 F21 H_CADIP8
AC25 HT_RXCAD8N HT_TXCAD8N G21
H_CADOP9 AB25 G20 H_CADIP9
AB24 HT_RXCAD9N HT_TXCAD9N H21
H_CADOP10 AA24 J20 H_CADIP10
AA25 HT_RXCAD10N HT_TXCAD10N J21
H_CADOP11 Y22 J18 H_CADIP11
Y23 HT_RXCAD11N HT_TXCAD11N K17
H_CADOP12 W21 L19 H_CADIP12
W20 HT_RXCAD12N HT_TXCAD12N J19
H_CADOP13 V21 M19 H_CADIP13
V20 HT_RXCAD13N HT_TXCAD13N L18
H_CADOP14 U20 M21 H_CADIP14
U21 HT_RXCAD14N HT_TXCAD14N P21
H_CADOP15 U19 P18 H_CADIP15
U18 HT_RXCAD15N HT_TXCAD15N M18
<5> H_CLKOP0 T22 HT_RXCLK0P HT_TXCLK0P H24 H_CLKIP0 <5>

<5> H_CLKON0 T23 HT_RXCLK0N HT_TXCLK0N H25 H_CLKIN0 <5>
<5> H_CLKOP1 AB23 HT_RXCLK1P HT_TXCLK1P L21 H_CLKIP1 <5>
<5> H_CLKON1 AA22 HT_RXCLK1N HT_TXCLK1N L20 H_CLKIN1 <5>
H_CTLOP0 M22 M24 H_CTLIP0
<5> H_CTLOP0 HT_RXCTL0P HT_TXCTL0P H_CTLIP0 <5>
H_CTLON0 M23 M25 H_CTLIN0
<5> H_CTLON0 HT_RXCTL0N HT_TXCTL0N H_CTLIN0 <5>
H_CTLOP1 R21 P19 H_CTLIP1
<5> H_CTLOP1 HT_RXCTL1P HT_TXCTL1P H_CTLIP1 <5>
H_CTLON1 R20 R18 H_CTLIN1
<5> H_CTLON1 HT_RXCTL1N HT_TXCTL1N H_CTLIN1 <5>
301_0402_1%1 2 R60 HT_RXCALP C23 B24 HT_TXCALP R61 1 2 301_0402_1% < Transmitter Calibration Resistor to HT_TXCALN >
HT_RXCALN HT_RXCALP HT_TXCALP HT_TXCALN
A24 HT_RXCALN HT_TXCALN B25
0718 Place within 1" 0718 Place within 1"

4 880MR1@ RS780M_FCBGA528 4
layout 1:2 layout 1:2

SCHEMATIC,MB A6052
A B C D E
A B C D E
+3VS AVDD=100mA U3C

L3 +AVDD1 F12 A22
+AVDD1 AVDD1(NC) TXOUT_L0P(NC)
1 2 BLM18PG121SN1D_0603 E12 AVDD2(NC) PART 3 OF 6 TXOUT_L0N(NC) B22
1 +AVDD2 F14 A21
C144 AVDDDI(NC) TXOUT_L1P(NC)
G15 AVSSDI(NC) TXOUT_L1N(NC) B21
+AVDDQ H15 B20
2.2U_0603_6.3V4Z AVDDQ(NC) TXOUT_L2P(NC)
H14 AVSSQ(NC) TXOUT_L2N(DBG_GPIO0) A20
2
TXOUT_L3P(NC) A19
E17 B19 < LVDS dual channel : channel 1 >
+1.8VS C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2)
CRT/TVOUT
F17 Y(DFT_GPIO2)
L4 F15 B18
0_0603_5% +AVDD2 COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC)
TXOUT_U0N(NC) A18
1 1 G18 RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3) A17
C142 C145 G17 B17
REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2)
E18 GREEN(DFT_GPIO1) TXOUT_U2P(NC) D20
1 2.2U_0603_6.3V4Z 0.1U_0402_16V7K 1
F18 GREENb(NC) TXOUT_U2N(NC) D21
2 2
E19 BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5) D18
F19 D19 < LVDS dual channel : channel 2 >
BLUEb(NC) TXOUT_U3N(NC)
+1.8VS UMA_CRT_HSYNC A11 B16
<15> UMA_CRT_HSYNC DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1)
L6 UMA_CRT_VSYNC B11 A16
<15> UMA_CRT_VSYNC DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3)
1 2 BLM18PG121SN1D_0603 +AVDDQ F8 DAC_SCL(PCE_RCALRN) TXCLK_UP(PCIE_RESET_GPIO4) D16
1 E8 DAC_SDA(PCE_TCALRN) TXCLK_UN(PCIE_RESET_GPIO1) D17
C148 +1.8VS
R65 1 2 715_0402_1% G14 L8
2.2U_0603_6.3V4Z DAC_RSET(PWM_GPIO1) +VDDLTP18 +VDDLTP18 BLM18PG121SN1D_0603 1
VDDLTP18(NC) A13 2
2 +NB_PLLVDD A12
+NB_PLLVDD PLLVDD(NC) VSSLTP18(NC) B13 1
+NB_HTPVDD +NB_HTPVDD D14 C153
PLLVDD18(NC) +VDDLT18
B12 A15
LVTM
PLLVSS(NC) VDDLT18_1(NC) 2.2U_0603_6.3V4Z
B15
PLL PWR
+1.1VS VDDLT18_2(NC) 2
+VDDA18HTPLL H17 VDDA18HTPLL VDDLT33_1(NC) A14
L2 B14
+NB_PLLVDD VDDLT33_2(NC)
1 2 BLM18PG121SN1D_0603 +VDDA18PCIEPLL D7 VDDA18PCIEPLL1
1 E7 VDDA18PCIEPLL2 VSSLT1(VSS) C14
C141 D15 +1.8VS
VSSLT2(VSS)
<15,20,26,28,31,32,35> PLT_RST#
R66 1 2 0_0402_5% NB_RESET# D8 SYSRESETb VSSLT3(VSS) C16 L10
2.2U_0603_6.3V4Z NB_PWRGD A10 C18 +VDDLT18 BLM18PG121SN1D_0603 1 2
2 +1.1VS <21> NB_PWRGD POWERGOOD VSSLT4(VSS)
NB_LDTSTOP# C10 C20 1 1
LDTSTOPb VSSLT5(VSS) C156 C157
C12 E20
PM
<20> CPU_LDT_REQ# ALLOW_LDTSTOP VSSLT6(VSS)
2
VSSLT7(VSS) C22
+1.8VS R69 C25 0.1U_0402_16V7K 4.7U_0805_10V4Z
<16> CLK_NBHT HT_REFCLKP 2 2
L5 4.7K_0402_5% C24
<16> CLK_NBHT# HT_REFCLKN
1 2 BLM18PG121SN1D_0603 +NB_HTPVDD
1 <16> NB_OSC_14.318M E11
1
REFCLK_P/OSCIN(OSCIN)
CLOCKs
C146 F11 E9
REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP) F7
1
2.2U_0603_6.3V4Z T2 G12
2 2 <16> NBGFX_CLK GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2) 2
R70 T1
<16> NBGFX_CLK# GFX_REFCLKN
4.7K_0402_5%
U1 GPP_REFCLKP
U2
2
GPP_REFCLKN
<16> CLK_SBLINK_BCLK V4 GPPSB_REFCLKP(SB_REFCLKP)

<16> CLK_SBLINK_BCLK# V3 GPPSB_REFCLKN(SB_REFCLKN)
B9 I2C_CLK
+1.8VS
A9
B8
I2C_DATA MIS. TMDS_HPD(NC) D9
D10
L7 DDC_DATA0/AUX0N(NC) HPD(NC)
A8 DDC_CLK0/AUX0P(NC)
1 2 BLM18PG121SN1D_0603 +VDDA18HTPLL B7 DDC_CLK1/AUX1P(NC) SUS_STAT#(PWM_GPIO5) D12 SUS_STAT# <15,21>
< Strap option pin or gate side-port memory IO >
1 A7 DDC_DATA1/AUX1N(NC)
C150 AE8
THERMALDIODE_P
T8 PAD B10 STRP_DATA THERMALDIODE_N AD8
2.2U_0603_6.3V4Z
2 R84 1
G11 RSVD TESTMODE D13 2 1.8K_0402_5%
Strap pin
<15> AUX_CAL C8 AUX_CAL(NC)
+1.8VS
L9
1 2 BLM18PG121SN1D_0603 +VDDA18PCIEPLL 880MR1@ RS780M_FCBGA528
1
C154
< Dedicated power for the DAC which can affect display quality >
2.2U_0603_6.3V4Z
2
3 +1.8VS 3
+1.8VS R68 1 2 300_0402_5% NB_PWRGD

2
+1.8VS
R83
C149
R366 1 2 1K_0402_1% CPU_LDT_REQ# 2.2K_0402_5%
1 2
1
5
0.1U_0402_16V7K U2
2
P
B NB_LDTSTOP#
Y 4
<7,20> LDT_STOP# 1 A
G
NC7SZ08P5X_NL_SC70-5
3
1 2
R101 0_0402_5%
@
4 4

SCHEMATIC,MB A6052
A B C D E
2 1
U3D
PAR 4 OF 6
AB12 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) AA18
AE16 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) AA20
V11 MEM_A2(NC) MEM_DQ2/DVO_DE(NC) AA19
AE15 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) Y19
AA12 MEM_A4(NC) MEM_DQ4(NC) V17
AB16 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) AA17
AB14 MEM_A6(NC) MEM_DQ6/DVO_D2(NC) AA15
AD14 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) Y15
AD13 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) AC20
AD15 MEM_A9(NC) MEM_DQ9/DVO_D5(NC) AD19
SBD_MEM/DVO_I/F
AC16 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) AE22
AE13 MEM_A11(NC) MEM_DQ11/DVO_D7(NC) AC18
AC14 MEM_A12(NC) MEM_DQ12(NC) AB20
Y14 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) AD22
MEM_DQ14/DVO_D10(NC) AC22
AD16 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC) AD21
AE17 MEM_BA1(NC)
AD17 MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC) Y17
MEM_DQS0N/DVO_IDCKN(NC) W18
W12 MEM_RASb(NC) MEM_DQS1P(NC) AD20
Y12 MEM_CASb(NC) MEM_DQS1N(NC) AE21
AD18 MEM_WEb(NC)
AB13 MEM_CSb(NC) MEM_DM0(NC) W17
AB18 MEM_CKE(NC) MEM_DM1/DVO_D8(NC) AE19
V14 MEM_ODT(NC)
IOPLLVDD18(NC) AE23 +1.8VS
V15 MEM_CKP(NC) IOPLLVDD(NC) AE24 +1.1VS
W14 MEM_CKN(NC)
B B
IOPLLVSS(NC) AD23
AE12 MEM_COMPP(NC)
AD12 MEM_COMPN(NC) MEM_VREF(NC) AE18
A A

SCHEMATIC,MB A6052
2 1
A B C D E
U3E < Main IO power for PCI-E graphics, SB, and GPP interfaces >
2A < Digital IO power for HyperTransport interface >
+1.1VS 2 1 L11 0_0805_5% +VDDHT J17 A6 +VDDA11PCIE FBMA-L11-201209-221LMA30T_0805 1 2 L44 +1.1VS
VDDHT_1 VDDPCIE_1
1 1 1 1 1 K16 VDDHT_2 PART 5/6 VDDPCIE_2 B6
C1126
C173
C174
C160
C162
C163
C171
C172
C165 C166 C167 C168 C159 L16 C6 VDDA_12=2.5A
VDDHT_3 VDDPCIE_3
M16 VDDHT_4 VDDPCIE_4 D6
4.7U_0805_10V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K P16 E6 1 1 1 1 2 2
2 2 2 2 2 VDDHT_5 VDDPCIE_5
R16 VDDHT_6 VDDPCIE_6 F6
T16 VDDHT_7 VDDPCIE_7 G7
2A < IO power for HyperTransport receive interface > VDDPCIE_8 H8
2 2 2 2 1 1
10U_0805_10V4Z
10U_0805_10V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2 1 L13 0_0805_5% +VDDHTRX H18 J9
VDDHTRX_1 VDDPCIE_9
0.1U_0402_16V7K
0.1U_0402_16V7K
1 1 1 1 G19 VDDHTRX_2 VDDPCIE_10 K9
C179 C164 C169 C170 C161 F20 M9
1 VDDHTRX_3 VDDPCIE_11 1
E21 VDDHTRX_4 VDDPCIE_12 L9
10U_0805_10V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K D22 P9
2 2 2 2 VDDHTRX_5 VDDPCIE_13
B23 VDDHTRX_6 VDDPCIE_14 R9
A23 VDDHTRX_7 VDDPCIE_15 T9
2A < IO power for HyperTransport transmit interface > VDDPCIE_16 V9
+1.1VS 2 1 L14 0_0805_5% +VDDHTTX AE25 U9
VDDHTTX_1 VDDPCIE_17
1 1 1 1 1 AD24 VDDHTTX_2
C1127 C175 C176 C177 C178 AC23 K12
VDDHTTX_3 VDDC_1
AB22 VDDHTTX_4 VDDC_2 J14
4.7U_0805_10V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K AA21 U16 +NB_CORE
2 2 2 2 2 VDDHTTX_5 VDDC_3
Y20 VDDHTTX_6 VDDC_4 J11
W19 VDDHTTX_7 VDDC_5 K15 < Core power > VDD_CORE:GM=5A/PM=10A
POWER
V18 VDDHTTX_8 VDDC_6 M12
U17 VDDHTTX_9 VDDC_7 L14
T17 VDDHTTX_10 VDDC_8 L11
C191
C182
C187
C193
C194
C180
C188
C183
C195
R17 VDDHTTX_11 VDDC_9 M13
C184
C196
C189
P17 VDDHTTX_12 VDDC_10 M15 1 C1129 Co-layout with C189
M17 VDDHTTX_13 VDDC_11 N12 2 2 2 2 2 2 2 2 2 1 1
2A < 1.8V IO power for PCI-E graphics, SB, and GPP interfaces > N14 +
L15 0_0805_5% +VDDA18PCIE VDDC_12 +NB_CORE
+1.8VS 2 1 J10 VDDA18PCIE_1 VDDC_13 P11
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
10U_0805_10V4Z
10U_0805_10V4Z
330U_D2E_2.5VM
1 1 1 1 1 1 P10 VDDA18PCIE_2 VDDC_14 P13
C181 C1128 C185 C190 C186 C192 1 1 1 1 1 1 1 1 1 2 2 2
K10 VDDA18PCIE_3 VDDC_15 P14 1
M10 VDDA18PCIE_4 VDDC_16 R12
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K L10 R15 + C1129
2 2 2 2 2 2 VDDA18PCIE_5 VDDC_17 330U_2.5V_M
W9 VDDA18PCIE_6 VDDC_18 T11
H9 VDDA18PCIE_7 VDDC_19 T15
2
T10 VDDA18PCIE_8 VDDC_20 U12
R10 VDDA18PCIE_9 VDDC_21 T14
Y9 VDDA18PCIE_10 VDDC_22 J16
AA9 VDDA18PCIE_11
AB9 AE10 @
VDDA18PCIE_12 VDD_MEM1(NC)
AD9 VDDA18PCIE_13 VDD_MEM2(NC) AA11
2 2
AE9 VDDA18PCIE_14 VDD_MEM3(NC) Y11
U10 VDDA18PCIE_15 VDD_MEM4(NC) AD10
< 1.8V IO transform power > VDD_MEM5(NC) AB10
+1.8VS F9 VDD18_1 VDD_MEM6(NC) AC10
1 G9 VDD18_2
C197 AE11 H11 < 3.3V IO power >
VDD18_MEM1(NC) VDD33_1(NC)
AD11 VDD18_MEM2(NC) VDD33_2(NC) H12 +3VS
1U_0402_6.3V4Z 1 1
2 880MR1@ RS780M_FCBGA528 C198 C199
0.1U_0402_16V4Z 0.1U_0402_16V4Z
U3F 2 2
A25 VSSAHT1 VSSAPCIE1 A2

D23 VSSAHT2 PART 6/6 VSSAPCIE2 B1
E22 VSSAHT3 VSSAPCIE3 D3
G22 VSSAHT4 VSSAPCIE4 D5
G24 VSSAHT5 VSSAPCIE5 E4
G25 VSSAHT6 VSSAPCIE6 G1
H19 VSSAHT7 VSSAPCIE7 G2
J22 VSSAHT8 VSSAPCIE8 G4
L17 VSSAHT9 VSSAPCIE9 H7
L22 VSSAHT10 VSSAPCIE10 J4
L24 VSSAHT11 VSSAPCIE11 R7
L25 VSSAHT12 VSSAPCIE12 L1
M20 VSSAHT13 VSSAPCIE13 L2
N22 VSSAHT14 VSSAPCIE14 L4
P20 VSSAHT15 VSSAPCIE15 L7
R19 VSSAHT16 VSSAPCIE16 M6
R22 VSSAHT17 VSSAPCIE17 N4
R24 VSSAHT18 VSSAPCIE18 P6
R25 VSSAHT19 VSSAPCIE19 R1
3 3
H20 VSSAHT20 VSSAPCIE20 R2
U22 VSSAHT21 VSSAPCIE21 R4
V19 VSSAHT22 VSSAPCIE22 V7
GROUND
W22 VSSAHT23 VSSAPCIE23 U4
W24 VSSAHT24 VSSAPCIE24 V8
W25 VSSAHT25 VSSAPCIE25 V6
Y21 VSSAHT26 VSSAPCIE26 W1
AD25 VSSAHT27 VSSAPCIE27 W2
VSSAPCIE28 W4
L12 VSS11 VSSAPCIE29 W7
M14 VSS12 VSSAPCIE30 W8
N13 VSS13 VSSAPCIE31 Y6
P12 VSS14 VSSAPCIE32 AA4
P15 VSS15 VSSAPCIE33 AB5
R11 VSS16 VSSAPCIE34 AB1
R14 VSS17 VSSAPCIE35 AB7
T12 VSS18 VSSAPCIE36 AC3
U14 VSS19 VSSAPCIE37 AC4
U11 VSS20 VSSAPCIE38 AE1
U15 VSS21 VSSAPCIE39 AE4
V12 VSS22 VSSAPCIE40 AB2
W11 VSS23
W15 VSS24
AC12 VSS25 VSS1 AE14
AA14 VSS26 VSS2 D11
Y18 VSS27 VSS3 G8
AB11 VSS28 VSS4 E14
AB15 VSS29 VSS5 E15
AB17 VSS30 VSS6 J15
AB19 VSS31 VSS7 J12
AE20 VSS32 VSS8 K14
AB21 VSS33 VSS9 M11
4 4
K11 VSS34 VSS10 L15

SCHEMATIC,MB A6052
A B C D E
A B C D E
< RS880 VSYNC mux at CRT_VSYNC pull High to 3K > < VSYNC : STRAP_DEBUG_BUS_GPIO_ENABLEb >
Enables the Test Debug Bus using GPIO.

R92
3K_0402_5%
1 : Disable (RX881, RS880)
<12> UMA_CRT_VSYNC 2 1 +3VS
0 : Enable (RX881, RS880)
PIN: RS880--> VSYNC#

1 R93 1
@ 2 1 3K_0402_5%
< RS880 use register to control PCI-E configure > < DFT_GPIO[4:2] : STRAP_PCIE_GPP_CFG[2:0] >
These pin straps are used to configure PCI-E GPP mode.

000 : 00001
001 : 00010
010 : 01011
011 : 00100
100 : 01010
101 : 01100
111 : 01011
< SUS_SATA# : LOAD_EEPROM_STRAPS >

< RS880 SUS_STAT# >
Selects Loading of STRAPS from EPROM
R85
1 2 150_0402_1%
<12> AUX_CAL 1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected
2 2
D1 RS880:SUS_STAT#
<12,21> SUS_STAT# @ 2 1 CH751H-40PT_SOD323-2 PLT_RST# <12,20,26,28,31,32,35>
< HSYNC : STRAP_DEBUG_BUS_PCIE_ENABLEb >

< RS880 use HSYNC to enable SIDE PORT (internal pull high) >
RX881: Enables the Test Debug Bus using PCIE bus
R94
2 1 3K_0402_5%
1 : Disable ( Can still be enabled using nbcfg register access )
<12> UMA_CRT_HSYNC +3VS
0 : Enable
RS880: Enables Side port memory ( RS780 use HSYNC#)
1. Disable (RS880)
0 : Enable (RS880)
3 3
4 4

SCHEMATIC,MB A6052
A B C D E
A B C D E
+3VS +3VS_CLK
+1.1VS +VDDCLK_IO
R64 1 2 0_0805_5%
1 1 1 1 1 1 1 1
R819 1 2 0_0805_5% C523 C524 C525 C526 C527 C528
1 1 1 1 1 1 C522 C529
22U_0805_6.3V6M 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 1U_0402_6.3V4Z
C515 C516 C517 C518 C519 C520 2 2 2 2 2 2 2 2
22U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2
CLK_48M R820 1 2 33_0402_5% < To Card Reader >

CLK_48M_CR <27>
+3VS_CLK
1 1 1 1
C530 C531 C532 C535 CLK_48M_CRUSB R246 1 2 33_0402_5% < To SB820 USB host >
1 CLK_48M_USB <21> 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 NB_OSC_14.318M_R R244 158_0402_1%
<12> < To RS880M Clock block >
1 2
NB_OSC_14.318M
R243 1 2 90.9_0402_1%
CLK_XTAL_OUT
CLK_XTAL_IN
CLK_NBHT <12>
< To RS880M Clock block >

CLK_NBHT# <12>
Y2 R249 1 2 8.2K_0402_5% +3VS_CLK
+3VS_CLK
+3VS_CLK
+3VS_CLK
2 1
14.318MHZ_16PF_7A14300083 C238 1 2 1U_0402_6.3V4Z

1 1
C536 C537
CLK_CPU_BCLK_R R821 1 2 0_0402_5%
CLK_CPU_BCLK <7>
22P_0402_50V8J 22P_0402_50V8J
2
2 2
R822
@ < To CPU >
CLK_XTAL_OUT
Routing the trace at least 10mil 261_0402_1%
CLK_XTAL_IN
1
2 CLK_CPU_BCLK_R# R823 0_0402_5% 2
SEL_SATA
1 2 CLK_CPU_BCLK# <7>
27M_SEL
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
U10
GND
XTAL_IN
REF_1/SEL_SATA
VSS_48
48MHz_0
48MHz_1
VDD_48
HTT_0/66M_0
HTT_0#/66M_1
PD#
CPU_K8_0
XTAL_OUT
REF_2/SEL_27
VSS_REF
REF_0/SEL_HTT66
VDD_REF
VDD_HTT
VSS_HTT
CPU_K8_0#
CLKREQ_MCARD2# 1 2 +3VS_CLK
R238 8.2K_0402_5%
CLKREQ_LAN# 1 2
1 54 +3VS_CLK R239 8.2K_0402_5%
<9,10,21> SMB_CK_CLK0 SCL VDD_CPU
2 SDA VDD_CPU_I/O 53 +VDDCLK_IO
<9,10,21> SMB_CK_DAT0
+3VS_CLK 3 VDD_DOT VSS_CPU 52
R248 1 2 0_0402_5% 27MCLK 4 51
<36> 27M_CLK @ R247 1 SRC_7#/27M CLKREQ_1#
2 33_0402_5% 27MSSC 5 SRC_7/27M_SS CLKREQ_2# 50 CLKREQ_MCARD2#
<36> 27M_SSC CLKREQ_MCARD2# <28>
6 VSS_DOT VDD_A 49 +3VS_CLK
7 SRC_5# VSS_A 48
8 SRC_5 VSS_SATA 47
<12> CLK_SBLINK_BCLK# 9 SRC_4# SRC_6/SATA 46 CLK_SBSRC_BCLK <20>
SB LINK <12> CLK_SBLINK_BCLK 10 SRC_4 SRC_6#/SATA# 45 CLK_SBSRC_BCLK# <20> SB SRC
11 VSS_SRC VDD_SATA 44 +3VS_CLK
+VDDCLK_IO 12 VDD_SRC_IO CLKREQ_3# 43
13 SRC_3# CLKREQ_4# 42
14 41 R236 1 2 10K_0402_5% +3VS_CLK
SRC_3 SB_SRC_SLOW#
<28> CLK_PCIE_MCARD2# 15 SRC_2# SB_SRC_0 40
WLAN <28> CLK_PCIE_MCARD2 16 SRC_2 SB_SRC_0# 39
+3VS_CLK 17 VDD_SRC VDD_SB_SRC 38 +3VS_CLK
+VDDCLK_IO 18 VDD_SRC_IO VDD_SB_SRC_IO 37 +VDDCLK_IO
VDD_ATIG_IO
VSS_SB_SRC
3 3
ATIGCLK_2#
ATIGCLK_1#
ATIGCLK_0#
CLKREQ_0#
SB_SRC_1#
ATIGCLK_2
ATIGCLK_1
ATIGCLK_0
SB_SRC_1
VDD_ATIG
VSS_ATIG
VSS_SRC
SRC_1#
SRC_0#
SRC_1
SRC_0
+3VS_CLK
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
2
SLG8SP626VTR_QFN72_10x10
R240
@ 8.2K_0402_5% OSC_14M_NB
RS880M 1.1V 158R/90.9R
1
SEL_SATA +3VS_CLK
+3VS_CLK
+VDDCLK_IO
2
R242 NB CLOCK INPUT TABLE

NBGFX_CLK <12>
R241
8.2K_0402_5% NBGFX_CLK# <12> NB GFX
8.2K_0402_5% NB CLOCKS RX881 RX881
CLK_PCIE_VGA <35>
CLK_PCIE_VGA# <35>
1
HT_REFCLKP
1
27M_SEL 100M DIFF 100M DIFF

HT_REFCLKN 100M DIFF 100M DIFF
REFCLK_P
1 configure as SATA output CLKREQ_LAN# 14M SE (1.8V) 14M SE (1.1V)
CLKREQ_LAN# <26>
SEL_SATA 1 * configure as 27M and 27M_SS output REFCLK_N NC vref
CLK_PCIE_LAN <26>
0 * configure as normal SRC(SRC_6) output 27M_SEL GLAN
CLK_PCIE_LAN# <26>
* default 0 configure as SRC_7 output GFX_REFCLK 100M DIFF 100M DIFF(IN/OUT)*
* default
GPP_REFCLK 100M DIFF NC or 100M DIFF OUTPUT
4 4
GPPSB_REFCLK 100M DIFF 100M DIFF
Use voltage divider resistor R243 & R244 to pull low
1 configure as single-ended 66MHz output

NB_OSC_14.318M
0* configure as differential 100MHz output
SCHEMATIC,MB A6052
* default AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A B C D E
A B C D E
+5VS
D7 +R_CRT_VCC +CRT_VCC
< CRT CONNECTOR > 2 F1
1 1 2 1A_6VDC_MINISMDC110
3 1
C237
RB491D_SOT23-3 @ 0.1U_0402_16V4Z
2
1
D19 D20 D21
@ DAN217_SC59 @ DAN217_SC59 @ DAN217_SC59
1 1
+3VS JCRT
6
3
RGND
11 ID0
RED_L 1 Red
7 GGND
D_DDCDATA 12
L22 GREEN_L SDA
2 Green
RED 1 2 NBQ100505T-800Y-N_2P RED_L 8
<36> RED BGND
HSYNC 13
L23 BLUE_L Hsync
3 Blue
GREEN 1 2 NBQ100505T-800Y-N_2P GREEN_L +CRT_VCC 9
<36> GREEN +5V
VSYNC 14
L24 Vsync
4 res
BLUE 1 2 NBQ100505T-800Y-N_2P BLUE_L 10
<36> BLUE SGND
D_DDCCLK 15 SCL
5 GND
1 1 1 1 1 1
1
1
C239 C240 C241 C242 C243 C244 16
R98 R99 R100 6P_0402_50V8K 6P_0402_50V8K 6P_0402_50V8K 6P_0402_50V8K 6P_0402_50V8K 6P_0402_50V8K GND
17 GND
150_0402_1% 150_0402_1% 150_0402_1%
2 2 2 2 2 2
@ SUYIN_070546FR015S263ZR
2
+CRT_VCC
2 R817 2
C245 1 2 0.1U_0402_16V4Z 1 2 10K_0402_5%
5
1
P
OE#
R_HSYNC 2 4 D_HSYNC L25 1 2 10_0402_5% HSYNC
<36,43> R_HSYNC A Y
G
U5
SN74AHCT1G125GW_SOT353-5 < SYNC SIGNAL >
3
L26 1 2 10_0402_5% VSYNC
+CRT_VCC
1 1
C247 C248
@ 10P_0402_50V8J @ 10P_0402_50V8J
5
1
2 2
P
OE#
R_VSYNC 2 4 D_VSYNC
<36,43> R_VSYNC A Y
G
U6
SN74AHCT1G125GW_SOT353-5
3 +CRT_VCC
+3VS
3 3
1
1
R824 R825 +3VS
4.7K_0402_5% 4.7K_0402_5% R805 R806
2K_0402_1% 2K_0402_1%
5
2
Q32B
2
CRT_DATA 4 3 2N7002KDW_SOT363-6 D_DDCDATA
<36> CRT_DATA
1
C255
@ 33P_0402_50V8K
< Display Data Channel >
2
+3VS
2
Q32A
CRT_CLK 1 6 2N7002KDW_SOT363-6 D_DDCCLK
<36> CRT_CLK
1 1
1
C256 C251 C252

@ 33P_0402_50V8K @ 470P_0402_50V8J @ 470P_0402_50V8J
2
2 2
4
FOR EMI 4

SCHEMATIC,MB A6052
A B C D E
A B C D E
LCD/PANEL BD. Conn.
+LCD_VDD +3VS +3VS
1
R90
R807 150_0603_5% 100K_0402_5%
1 1
2
C259
W=60mils
6 2
2
0.1U_0402_16V7K
Q33A 1
3
S
R91 G
2N7002KDW_SOT363-6 2 1 2 47K_0402_5% 2 Q4
1 +LCD_VDD
C260 D AO3413_SOT23
1
0.01U_0402_25V7K
W=60mils
2 Inrush current = 0A
3
1
C262
Q33B
ENVDD 5 0.1U_0402_16V7K
<36> VGA_ENVDD 2
2N7002KDW_SOT363-6
4
2
R3
10K_0402_5%
1
2 < LVDS Connector > 2
INT_MIC_DATA
0.1U_0402_16V4Z +3VS
1 2 INT_MIC_CLK
+3VS_LVDS_CAM C265
3
0_0603_5% W=20mils JLVDS D12 LCD_EDID_CLK 4.7K_0402_5% 2 1 R117
+3VS R808 1 2 2 1
USB20_P9_L 2 1
4 4 3 3 LCD_TXCLK+ <36>
USB20_N9_L 6 5 LCD_EDID_DATA 4.7K_0402_5% 2 1 R118
6 5 LCD_TXCLK- <36>
8 8 7 7
10 9 PACDN042Y3R_SOT23-3
<36> LCD_TXOUT0+ LCD_TZCLK+ <36>
1
10 9
<36> LCD_TXOUT0- 12 12 11 11 LCD_TZCLK- <36>
<36> LCD_TXOUT1+ 14 14 13 13
<36> LCD_TXOUT1- 16 16 15 15 LCD_EDID_CLK <36>
<36> LCD_TXOUT2+ 18 18 17 17 LCD_EDID_DATA <36>
<36> LCD_TXOUT2- 20 20 19 19 INT_MIC_CLK <29>
22 22 21 21 INT_MIC_DATA <29>
24 23 +3VS
<36> LCD_TZOUT0+ 24 23
26 25 INVT_PWM
<36> LCD_TZOUT0- 26 25
<36> LCD_TZOUT1+ 28 28 27 27
<36> LCD_TZOUT1- 30 30 29 29 1 1
32 31 +LCDVDD_R
<36> LCD_TZOUT2+ 32 31
34 33 BKOFF#_R @ C152 C264
<36> LCD_TZOUT2- 34 33
36 35 680P_0402_50V7K 0.1U_0402_16V4Z
36 35 B+ 2 2
38 38 37 37 +LCD_INV
3 Rated Current MAX:3000mA 3
+LCD_INV 40 40 39 39
42 41 L45 2 1
GND GMD FBMA-L11-201209-221LMA30T_0805
ACES_87242-4001-09 1 1 1
@ C151
C268 C263 @ 680P_0402_50V7K
68P_0402_50V8J 0.1U_0402_25V6
2 2 2
BKOFF#_R 33_0402_5% 2 1 R9
BKOFF# <31>
1
R200
10K_0402_5%
2
1.5A
L12
L20 +LCDVDD_R 2 1 0_0805_5% +LCD_VDD
4 3 USB20_P9_L
<21> USB20_P9 4 3 EC_INVT_PWM 1 2 INVT_PWM 1 1
<31> EC_INVT_PWM
M9X@ R96 0_0402_5% C266 C267
1
1 2 USB20_N9_L
<21> USB20_N9 1 2
1 2 R319 0.1U_0402_16V7K 4.7U_0805_10V4Z
<36> VGA_INVT_PWM 2 2
MANHA@R97
MANHA@R97 0_0402_5% 10K_0402_5%
WCM-2012-900T_0805
2
@ C27 2 1 @ R23 1 2 INT_MIC_CLK
4 10P_0402_50V8J 10_0402_5% 4

SCHEMATIC,MB A6052
A B C D E
A B C D E
H@ F2
+5VS H@ D11 2 1 2 1 1.1A_6V_MINISMDC110F-2 +HDMI_5V_OUT
RB161M-20_SOD123-2 1
C22
H@
R121 R125 0.1U_0402_16V7K
HDMI_TX0- @ 0_0402_5% HDMI_R_D0- HDMI_TX1- @ 0_0402_5% HDMI_R_D1- 2
1 2 1 2
H@ C272 1 2 0.1U_0402_16V7K HDMI_TX0+ L17 L19

<36> HDMI_TXD0+
H@ C273 1 2 0.1U_0402_16V7K HDMI_TX0- 1 2 1 2
<36> HDMI_TXD0- 1 2 1 2
4 4 3 3 4 4 3 3
1 1
H@ OCE2012120YZF_0805 H@ OCE2012120YZF_0805 < HDMI Connector >
H@ C275 1 2 0.1U_0402_16V7K HDMI_TX1+
<36> HDMI_TXD1+
H@ C276 1 2 0.1U_0402_16V7K HDMI_TX1- R122 R126 JHDMI
<36> HDMI_TXD1-
HDMI_TX0+ @ 1 2 0_0402_5% HDMI_R_D0+ HDMI_TX1+ @ 1 2 0_0402_5% HDMI_R_D1+ HDMI_HPD 19 HP_DET
+HDMI_5V_OUT 18 +5V
17 DDC/CEC_GND
HDMI_SDATA 16
R123 R127 HDMI_SCLK SDA
15 SCL
H@ C277 1 2 0.1U_0402_16V7K HDMI_TX2+ HDMI_TX2- @ 1 2 0_0402_5% HDMI_R_D2- HDMI_CLK- @ 1 2 0_0402_5% HDMI_R_CK- 14
<36> HDMI_TXD2+ Reserved
H@ C274 1 2 0.1U_0402_16V7K HDMI_TX2- 13
<36> HDMI_TXD2- CEC
HDMI_R_CK- 12 20
CK- GND
11 CK_shield GND 21
L18 L16 HDMI_R_CK+ 10 22
HDMI_R_D0- CK+ GND
1 1 2 2 1 1 2 2 9 D0- GND 23
8 D0_shield
H@ C278 1 2 0.1U_0402_16V7K HDMI_CLK+ HDMI_R_D0+ 7
<36> HDMI_CLK0+ D0+
H@ C279 1 2 0.1U_0402_16V7K HDMI_CLK- 4 3 4 3 HDMI_R_D1- 6
<36> HDMI_CLK0- 4 3 4 3 D1-
5 D1_shield
H@ OCE2012120YZF_0805 H@ OCE2012120YZF_0805 HDMI_R_D1+ 4
HDMI_R_D2- D1+
3 D2-
R124 R128 2
HDMI_TX2+ @ 0_0402_5% HDMI_R_D2+ HDMI_CLK+ @ 0_0402_5% HDMI_R_CK+ HDMI_R_D2+ D2_shield
1 2 1 2 1 D2+
@ SUYIN_100042MR019S153ZL
< Termination resistor >
2 2
< Close to Connector >
HDMI_R_CK+ H@ R102 1 2 499_0402_1%
HDMI_R_CK- H@ R103 1 2 499_0402_1%
+3VS
+3VS +HDMI_5V_OUT
1
H@ H@
1
R826 R827
4.7K_0402_5% 4.7K_0402_5% R53 HDMI_R_D0- H@ R104 1 2 499_0402_1%
2
H@ 2.2K_0402_5%
G
Q25 H@ HDMI_R_D0+ H@ R106 1 2 499_0402_1%

2
BSH111_SOT23-3
2
3 1 HDMI_SDATA
<36> HDMIDAT_VGA
S
1
2
H@ R54
G
Q26 2.2K_0402_5%
BSH111_SOT23-3 H@
3 1 HDMI_SCLK
2
<36> HDMICLK_VGA HDMI_R_D1- H@ R108 1 2 499_0402_1%
S
HDMI_R_D1+ H@ R109 1 2 499_0402_1%
3 3
Q34A
HDMI_R_D2+ H@ R114 1 2 499_0402_1% 6 1
2N7002KDW_SOT363-6
HDMI_R_D2- H@ R116 1 2 499_0402_1%
2
< Hot-plug detection & level shift > +5VS
+5VS
R120 1K_0402_5%
HDMI_HPD_R 1 2 HDMI_HPD
2
+3VS
2
R110 C281
H@ H@
1
100K_0402_5% 0.1U_0402_16V4Z
R113 1
1
2.2K_0402_5%
2 H@
C280
2
5
1
H@
0.1U_0402_16V4Z
P
OE#
1
2 A Y 4 HPD <36>
G
H@ U7
R119
3
100K_0402_5%
4 4
1
SN74AHCT1G125GW_SOT353-5

SCHEMATIC,MB A6052
A B C D E
A B C D E
C572 1 2 150P_0402_50V8J U8A
R325 33_0402_5% P1
SB800 Part 1 of 5
W2
A_RST# PCIE_RST# PCICLK0
2 1 L1 A_RST# PCICLK1/GPO36 W1 PCI_CLK1 <24>
PCI CLKS
PCICLK2/GPO37 W3 PCI_CLK2 <24>
C579 1 2 0.1U_0402_16V7K SB_RX0P_C AD26 W4 PCI_CLK3 <24>
<11> SB_RX0P A_TX0P PCICLK3/GPO38
C573 1 2 0.1U_0402_16V7K SB_RX0N_C AD27 Y1 PCI_CLK4 <24>
<11> SB_RX0N A_TX0N PCICLK4/14M_OSC/GPO39
C574 1 2 0.1U_0402_16V7K SB_RX1P_C AC28
<11> SB_RX1P A_TX1P
C575 1 2 0.1U_0402_16V7K SB_RX1N_C AC29 V2
<11> SB_RX1N A_TX1N PCIRST#
C576 1 2 0.1U_0402_16V7K SB_RX2P_C AB29
<11> SB_RX2P A_TX2P
C580 1 2 0.1U_0402_16V7K SB_RX2N_C AB28
<11> SB_RX2N A_TX2N
C577 1 2 0.1U_0402_16V7K SB_RX3P_C AB26 AA1
<11> SB_RX3P A_TX3P AD0/GPIO0
C578 1 2 0.1U_0402_16V7K SB_RX3N_C AB27 AA4
1 <11> SB_RX3N A_TX3N AD1/GPIO1 1
AD2/GPIO2 AA3
<11> SB_TX0P AE24 A_RX0P AD3/GPIO3 AB1
<11> SB_TX0N AE23 A_RX0N AD4/GPIO4 AA5
<11> SB_TX1P AD25 AB2
PCI EXPRESS INTERFACES

A_RX1P AD5/GPIO5
<11> SB_TX1N AD24 A_RX1N AD6/GPIO6 AB6
<11> SB_TX2P AC24 A_RX2P AD7/GPIO7 AB5
<11> SB_TX2N AC25 A_RX2N AD8/GPIO8 AA6
<11> SB_TX3P AB25 A_RX3P AD9/GPIO9 AC2
<11> SB_TX3N AB24 A_RX3N AD10/GPIO10 AC3
AD11/GPIO11 AC4
R326 2 1 590_0402_1% AD29 AC1
R327 PCIE_CALRP AD12/GPIO12
+1.1VS_PCIE 2 1 2K_0402_1% AD28 PCIE_CALRN AD13/GPIO13 AD1
AD14/GPIO14 AD2
AA28 GPP_TX0P AD15/GPIO15 AC6
AA29 GPP_TX0N AD16/GPIO16 AE2
Y29 GPP_TX1P AD17/GPIO17 AE1
Y28 GPP_TX1N AD18/GPIO18 AF8
Y26 GPP_TX2P AD19/GPIO19 AE3
Y27 GPP_TX2N AD20/GPIO20 AF1
W28 GPP_TX3P AD21/GPIO21 AG1
W29 GPP_TX3N AD22/GPIO22 AF2
AE9 PCI_AD23 PCI_AD23 <24>
AD23/GPIO23 PCI_AD24
AA22 GPP_RX0P AD24/GPIO24 AD9 PCI_AD24 <22,24>
+3VALW Y21 AC11 PCI_AD25
C581 GPP_RX0N AD25/GPIO25 PCI_AD25 <24>
AA25 AF6 PCI_AD26 PCI_AD26 <24>
GPP_RX1P AD26/GPIO26 PCI_AD27
2 1 AA24 GPP_RX1N AD27/GPIO27 AF4 PCI_AD27 <24>
W23 AF3 PCI_AD28 PCI_AD28 <24>
GPP_RX2P AD28/GPIO28
5
0.1U_0402_16V4Z U21 V24 AH2 PCI_AD29 PCI_AD29 <24>

GPP_RX2N AD29/GPIO29
2 W24 AG2
P
B GPP_RX3P AD30/GPIO30
Y 4 PLT_RST# <12,15,26,28,31,32,35> W25 GPP_RX3N AD31/GPIO31 AH3
A_RST# 1 AA8
A CBE0#
G
PCI INTERFACE
NC7SZ08P5X_NL_SC70-5 AD5
2 CBE1# 2
AD8
3
@ CBE2#
2 1 CBE3# AA10
R328 8.2K_0402_5% AE8
FRAME#
DEVSEL# AB9
<16> CLK_SBSRC_BCLK M23 PCIE_RCLKP/NB_LNK_CLKP IRDY# AJ3
<16> CLK_SBSRC_BCLK# P23 PCIE_RCLKN/NB_LNK_CLKN TRDY# AE7
PAR AC5
U29 NB_DISP_CLKP STOP# AF5
U28 NB_DISP_CLKN PERR# AE6
SERR# AE4
+3VS T26 AE11
+1.8VS NB_HT_CLKP REQ0#
T27 NB_HT_CLKN REQ1#/GPIO40 AH5
REQ2#/CLK_REQ8#/GPIO41 AH4
2
V21 CPU_HT_CLKP REQ3#/CLK_REQ5#/GPIO42 AC12

R329 T21 AD12
CPU_HT_CLKN GNT0#
4.7K_0402_5% GNT1#/GPO44 AJ5
2
G
V23 SLT_GFX_CLKP GNT2#/GPO45 AH6

T23 AB12
1
H_PWRGD SLT_GFX_CLKN GNT3#/CLK_REQ7#/GPIO46

3 1 H_PWRGD_L <50> CLKRUN# AB11
S
L29 GPP_CLK0P LOCK# AD7

Q21 L28
FDV301N_NL_SOT23-3 GPP_CLK0N BT_PWR#
INTE#/GPIO32 AJ6 BT_PWR# <28>
N29 GPP_CLK1P INTF#/GPIO33 AG6 BT_DET# <28>
N28 GPP_CLK1N INTG#/GPIO34 AG4 BT_RST# BT_RST# <28>
level shift to ISL6265 INTH#/GPIO35 AJ4
M29 GPP_CLK2P
M28 GPP_CLK2N
ISL6265 PWROK input, TTL level: 0.8V~2.0V
T25
CLOCK GENERATOR
GPP_CLK3P
When this pin is high, the SVI interface is V25 GPP_CLK3N LPCCLK0 H24 CLK_PCI_EC <24,31>
LPCCLK1 H25 CLK_PCI_SIO <24,32>
active and I2C protocol is running. While this L24 J27 LPC_AD0 <31,32>
CLK_PCI_SIO 2 1 R42 @ 1 2 C94 @
3 GPP_CLK4P LAD0 3
pin is low, the SVC, SVD, and VFIXEN input L23 GPP_CLK4N LAD1 J26 LPC_AD1 <31,32>
10_0402_5% 10P_0402_50V8J
LAD2 H29 LPC_AD2 <31,32>
states determine the pre-PWROK metal VID or P25
LPC
H28 LPC_AD3 <31,32>
GPP_CLK5P LAD3
VFIX mode voltage. This pin must be low prior M25 GPP_CLK5N LFRAME# G28 LPC_FRAME# <31,32>
LDRQ0# J25
to the ISL6265 PGOOD output going high P29 GPP_CLK6P LDRQ1#/CLK_REQ6#/GPIO49 AA18
P28 GPP_CLK6N SERIRQ/GPIO48 AB19 SERIRQ <31,32>
N26 GPP_CLK7P
N27 GPP_CLK7N
ALLOW_LDTSTP/DMA_ACTIVE# G21 CPU_LDT_REQ# <12>
1 2 25M_CLK_X1 T29 H21 H_PROCHOT# <7>
C648 GPP_CLK8P PROCHOT#
T28 GPP_CLK8N LDT_PG K19 H_PWRGD <7,50>
2
CPU
27P_0402_50V8J G22 LDT_STOP# <7,12>

Y5 LDT_STP#
LDT_RST# J24 R26 1 2 0_0402_5% LDT_RST# <7>
R370 L25
1M_0402_5% 14M_25M_48M_OSC +RTCBATT
25MHZ_20PF_7A25000012
1
C1 SB_32KHI
2
25M_CLK_X2 32K_X1
1 2
C639 25M_CLK_X1 L26 C2 SB_32KHO
25M_X1 32K_X2
1
27P_0402_50V8J
D2 R331
RTC
RTCCLK PAD T11

INTRUDER_ALERT# B2 1K_0402_5%
25M_CLK_X2 L27 B1
25M_X2 VDDBT_RTC_G +RTCVCC
2
@ R332 20M_0402_5%
@R332
D8
1 2 SB820M_FCBGA605
1 2 3
R333 510_0402_5%
C582
0.1U_0402_16V4Z
C584 1 1 C585 W=20mils 1
0.1U_0402_16V4Z
1 2 SB_32KHI 1U_0402_6.3V4Z J1 1
2
@ JUMP_43X39 C583 2
4 18P_0402_50V8J Y3 4
1
2 2
1
4 OSC NC 3 for Clear CMOS 2 BAS40-04_SOT23-3
R335 Close to SB
1
20M_0603_5% 1 2
OSC NC +CHGRTC
32.768KHZ_12.5PF_Q13MC14610002
C586
2
1 2 SB_32KHO
18P_0402_50V8J
SCHEMATIC,MB A6052
A B C D E
A B C D E
@ @
1 2 C587 1 2 100P_0402_25V8K
R337 100_0402_5%
U8D
J2 PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC A10 CLK_48M_USB <16>
K1 RI#/GEVENT22#
D3 G19 USB_RCOMP 1 2
SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP 11.8K_0402_1% R338
<31> PM_SLP_S3# F1 SLP_S3#
<31> PM_SLP_S5# H1 SLP_S5#
ACPI / WAKE UP EVENTS

<31> PBTN_OUT# F2 PWR_BTN#
USB 1.1 USB MISC

1 <31> SB_PWRGD
SUS_STAT#
H5
G6
PWR_GOOD SB800 J10 1
<12,15> SUS_STAT# SUS_STAT# USB_FSD1P/GPIO186
T14 PAD B3 TEST0 Part 4 of 5 USB_FSD1N H11
T12 PAD C4 TEST1/TMS OHCI4
T13 PAD F6 TEST2 USB_FSD0P/GPIO185 H9
<31> GATEA20 AD21 GA20IN/GEVENT0# USB_FSD0N J8
<31> KB_RST# AE21 KBRST#/GEVENT1#
1 2 EC_RSMRST# K2 B12
<31> EC_SCI# LPC_PME#/GEVENT3# USB_HSD13P
R339 2.2K_0402_5% J29 A12
<31> EC_SMI# LPC_SMI#/GEVENT23# USB_HSD13N
H2 GEVENT5#
J1 SYS_RESET#/GEVENT19# USB_HSD12P F11
<26> EC_SWI# H6 WAKE#/GEVENT8# USB_HSD12N E11 EHCI13 / OHCI3
F3 IR_RX1/GEVENT20#
H_THERMTRIP# J6 E14
+3VS <7> H_THERMTRIP# THRMTRIP#/SMBALERT#/GEVENT2# USB_HSD11P
NB_PWRGD AC19 E12
<12> NB_PWRGD NB_PWRGD USB_HSD11N
EC_RSMRST# G1 J12
<31> EC_RSMRST# RSMRST# USB_HSD10P
R342 1 2 2.2K_0402_5% SMB_CK_CLK0 J14
HDMI_DET USB_HSD10N
AD19 CLK_REQ4#/SATA_IS0#/GPIO64
R343 1 2 2.2K_0402_5% SMB_CK_DAT0 AA16 A13 USB20_P9
CLK_REQ3#/SATA_IS1#/GPIO63 USB_HSD9P USB20_P9 <18>
AB21 B13 USB20_N9 USB-9 Int Camera
SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD9N USB20_N9 <18>
R344 1 2 4.7K_0402_5% SUS_STAT# AC18 CLK_REQ0#/SATA_IS3#/GPIO60 USB20_P8
AF20 SATA_IS4#/FANOUT3/GPIO55 USB_HSD8P D13 USB20_P8 <28>
AE19 C13 USB20_N8 USB-8 WLAN
SATA_IS5#/FANIN3/GPIO59 USB_HSD8N USB20_N8 <28>
<29> PCH_SPKR AF19 SPKR/GPIO66 EHCI2 / OHCI2
+3VS SMB_CK_CLK0 AD22 G12
<9,10,16> SMB_CK_CLK0 SCL0/GPIO43 USB_HSD7P
USB 2.0
<9,10,16> SMB_CK_DAT0 SMB_CK_DAT0 AE22 G14
SMB_CK_CLK1 SDA0/GPIO47 USB_HSD7N
<28> SMB_CK_CLK1 F5 SCL1/GPIO227
2
<28> SMB_CK_DAT1 SMB_CK_DAT1 F4 G16 USB20_P6

SDA1/GPIO228 USB_HSD6P USB20_P6 <28>
R105 AH21 G18 USB20_N6 USB-6 Bluetooth
CLK_REQ2#/FANIN4/GPIO62 USB_HSD6N USB20_N6 <28>
H@ 10K_0402_5% AB18 CLK_REQ1#/FANOUT4/GPIO61 USB20_P5
E1 D16
GPIO
IR_LED#/LLB#/GPIO184 USB_HSD5P USB20_P5 <27>
AJ21 C16 USB20_N5 USB-4 Card Reader (3 IN 1)
USB20_N5 <27>
1
2 SMARTVOLT2/SHUTDOWN#/GPIO51 USB_HSD5N 2
H4 DDR3_RST#/GEVENT7#
HDMI_DET D5 B14
GBE_LED0/GPIO183 USB_HSD4P
D7 GBE_LED1/GEVENT9# USB_HSD4N A14
2
G5 GBE_LED2/GEVENT10#
R107 K3 E18
@ GBE_STAT0/GEVENT11# USB_HSD3P
10K_0402_5% AA20 CLK_REQG#/GPIO65/OSCIN USB_HSD3N E16
EHCI1 / OHCI1
J16 USB20_P2
USB20_P2 <25>
1
USB_HSD2P USB20_N2
H3 BLINK/USB_OC7#/GEVENT18# USB_HSD2N J18 USB20_N2 <25> USB-2 USB/eSATA <Wake Up support>
EC_LID_OUT# D1
<31> EC_LID_OUT# USB_OC6#/IR_TX1/GEVENT6#
E4 B17 USB20_P1
USB_OC5#/IR_TX0/GEVENT17# USB_HSD1P USB20_P1 <30>
USB OC
D4 A17 USB20_N1 USB-1 Right side
USB_OC4#/IR_RX0/GEVENT16# USB_HSD1N USB20_N1 <30>
E8 USB_OC3#/AC_PRES/TDO/GEVENT15#
USB_OC#2 F7 A16 USB20_P0
<25,31> USB_OC#2 USB_OC2#/TCK/GEVENT14# USB_HSD0P USB20_P0 <30>
E7 B16 USB20_N0 USB-0 Right side
USB_OC1#/TDI/GEVENT13# USB_HSD0N USB20_N0 <30> +3VALW
R80 10_0402_5% USB_OC#0 F8
<30,31> USB_OC#0 USB_OC0#/TRST#/GEVENT12#
@C143
@ C143 2 1 10P_0402_50V8J 2 1 @ AZ_BITCLK_HD
R345 1 2 33_0402_5%
<29> AZ_BITCLK_HD
<32> HDA_BITCLK_MDC R136 1 2 33_0402_5%
@C147
@ C147 2 1 10P_0402_50V8J HDA_BITCLK_MDC <29> AZ_SDOUT_HD R346 1 2 33_0402_5% M3 D25
R138 33_0402_5% AZ_BITCLK SCL2/GPIO193
<32> HDA_SDOUT_MDC 1 2 N1 AZ_SDOUT SDA2/GPIO194 F23
2
L2 B26 SB_SIC
<24> HDA_SDOUT AZ_SDIN0/GPIO167 SCL3_LV/GPIO195
M2 E26 SB_SID @ R73 @ R75
@R75 R78
HD AUDIO
<29> AZ_SDIN0_HD AZ_SDIN1/GPIO168 SDA3_LV/GPIO196
<32> HDA_SDIN1 M1 F25 10K_0402_5% 10K_0402_5% 10K_0402_5%
R347 33_0402_5% AZ_SDIN2/GPIO169 EC_PWM0/EC_TIMER0/GPIO197
<29> AZ_SYNC_HD 1 2 M4 AZ_SDIN3/GPIO170 EC_PWM1/EC_TIMER1/GPIO198 E22
<32> HDA_SYNC_MDC R142 1 2 33_0402_5% N2 F22 GPIO199 <24>
1
R348 33_0402_5% AZ_SYNC EC_PWM2/EC_TIMER2/GPIO199 GPIO201
<32> HDA_RST#_MDC
R144
1 2
33_0402_5%
P2 AZ_RST# EC_PWM3/EC_TIMER3/GPIO200 E21 GPIO200 <24> STRAP PIN GPIO202
<29> AZ_RST_HD# 1 2
G24 GPIO201 GPIO203
GBE_COL KSI_0/GPIO201 GPIO202
T1 GBE_COL KSI_1/GPIO202 G25
2
GBE_CRS T4 E28 GPIO203
GBE_CRS KSI_2/GPIO203
2
L6 E29 GPIO204 R74 R77 @ R79
@R79
3 GBE_MDIO GBE_MDCK KSI_3/GPIO204 GPIO205 1K_0402_1% 1K_0402_1% 10K_0402_5% 3
L5 GBE_MDIO KSI_4/GPIO205 D29
T9 GBE_RXCLK KSI_5/GPIO206 D28
+3VALW U1 C29
1
GBE_RXD3 KSI_6/GPIO207
U3 C28
1
GBE_RXD2 KSI_7/GPIO208
T2 GBE_RXD1
GBE LAN
1 2 GBE_MDIO U2 B28 GPIO201 GPIO202 GPIO203
R352 10K_0402_5% GBE_RXD0 KSO_0/GPIO209
T5 GBE_RXCTL/RXDV KSO_1/GPIO210 A27
EMBEDDED CTRL
1 2 GBE_COL GBE_RXERR V5 B27
R353 10K_0402_5% GBE_RXERR KSO_2/GPIO211
P5 GBE_TXCLK KSO_3/GPIO212 D26 High High High Nile-M
1 2 GBE_CRS M5 A26 Nile
R354 10K_0402_5% GBE_TXD3 KSO_4/GPIO213
P9 GBE_TXD2 KSO_5/GPIO214 C26
1 2 GBE_RXERR T7 A24 High High Low Nile-S
R356 10K_0402_5% GBE_TXD1 KSO_6/GPIO215
P7 GBE_TXD0 KSO_7/GPIO216 B25
1 2 GBE_PHY_INTR M7 A25
R358 10K_0402_5% GBE_TXCTL/TXEN KSO_8/GPIO217 +3VALW
P4 GBE_PHY_PD KSO_9/GPIO218 D24 Low Low Low Danube Marseille
M9 GBE_PHY_RST# KSO_10/GPIO219 B24 Danube
+3VALW GBE_PHY_INTR V7 C24
GBE_PHY_INTR KSO_11/GPIO220
KSO_12/GPIO221 B23 Low Low High Danube Hamburg
E23 PS2_DAT/SDA4/GPIO187 KSO_13/GPIO222 A23
E24 PS2_CLK/SCL4/GPIO188 KSO_14/GPIO223 D22
EMBEDDED CTRL
CIR_EN# F21 C22

SPI_CS2#/GBE_STAT2/GPIO166 KSO_15/GPIO224 GPIO204 GPIO205
G29 FC_RST#/GPO160 KSO_16/GPIO225 A22
2
2
KSO_17/GPIO226 B22
R95 D27 R51 R56
+3VALW 10K_0402_5% PS2KB_DAT/GPIO189
F28 PS2KB_CLK/GPIO190
Low Low Madison LP 10K_0402_5% 10K_0402_5%
F29 PS2M_DAT/GPIO191
E27
1
1
PS2M_CLK/GPIO192 GPIO204
Low High None
CIR_EN# GPIO205
SB820M_FCBGA605 @ @
2
1 2 EC_LID_OUT# High Low Park XT
2
R357 100K_0402_5% R55 R57

4 SB_SIC R115 CIR@ 4
1 2 10K_0402_5% 10K_0402_5%
R359 2.2K_0402_5% 1K_0402_1% High High M92-XTX
1 2 SB_SID
1
R360 2.2K_0402_5%
1
1 2 H_THERMTRIP#
R361 10K_0402_5% MADISON@ MANHA@
1 2 SMB_CK_CLK1
R362 2.2K_0402_5%
1
R363
2
2.2K_0402_5%
SMB_CK_DAT1 Security Classification Compal Secret Data Compal Electronics, Inc.
SCHEMATIC,MB A6052
A B C D E
A B C D E
U8B
SATA_STX_DRX_P0 AH9
SB800 AH28
1 <25> SATA_STX_DRX_P0 SATA_TX0P FC_CLK 1
SATA_STX_DRX_N0 AJ9 Part 2 of 5 AG28
<25> SATA_STX_DRX_N0 SATA_TX0N FC_FBCLKOUT
HDD AJ8
FC_FBCLKIN AF26
<25> SATA_RXN0_C SATA_RX0N
<25> SATA_RXP0_C AH8 SATA_RX0P FC_OE#/GPIOD145 AF28
FC_AVD#/GPIOD146 AG29
SATA_STX_DRX_P1 AH10 AG26
<25> SATA_STX_DRX_P1 SATA_TX1P FC_WE#/GPIOD148
SATA_STX_DRX_N1 AJ10 AF27
<25> SATA_STX_DRX_N1 SATA_TX1N FC_CE1#/GPIOD149
AE29
ODD AG10
FC_CE2#/GPIOD150
AF29
<25> SATA_RXN1_C SATA_RX1N FC_INT1/GPIOD144
<25> SATA_RXP1_C AF10 SATA_RX1P FC_INT2/GPIOD147 AH27
AG12 SATA_TX2P FC_ADQ0/GPIOD128 AJ27

AF12 SATA_TX2N FC_ADQ1/GPIOD129 AJ26
FC_ADQ2/GPIOD130 AH25
AJ12 SATA_RX2N FC_ADQ3/GPIOD131 AH24
AH12 SATA_RX2P FC_ADQ4/GPIOD132 AG23
FC_ADQ5/GPIOD133 AH23
SATA_STX_DRX_P3 AH14 AJ22
<25> SATA_STX_DRX_P3 SATA_TX3P FC_ADQ6/GPIOD134
SATA_STX_DRX_N3 AJ14 AG21
<25> SATA_STX_DRX_N3 SATA_TX3N FC_ADQ7/GPIOD135
eSATA AG14
FC_ADQ8/GPIOD136 AF21
AH22
<25> SATA_RXN3_C SATA_RX3N FC_ADQ9/GPIOD137
AF14 AJ23
FLASH
<25> SATA_RXP3_C SATA_RX3P FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139 AF23
AG17 SATA_TX4P FC_ADQ12/GPIOD140 AJ24
AF17 SATA_TX4N FC_ADQ13/GPIOD141 AJ25
FC_ADQ14/GPIOD142 AG25
AJ17 SATA_RX4N FC_ADQ15/GPIOD143 AH26
AH17
SERIAL ATA
SATA_RX4P
AJ18 SATA_TX5P
AH18 SATA_TX5N FANOUT0/GPIO52 W5
FANOUT1/GPIO53 W6
2 2
AH19 SATA_RX5N FANOUT2/GPIO54 Y9
AJ19 SATA_RX5P
FANIN0/GPIO56 W7
FANIN1/GPIO57 V9
R364 2 1 1K_0402_1% SATA_CALRP AB14 W8
SATA_CALRP FANIN2/GPIO58
+1.1VS_SATA R365 2 1 931_0402_1% SATA_CALRN AA14 SATA_CALRN
TEMPIN0/GPIO171 B6
A6 R43 1 2 150K_0402_5% +3VALW
TEMPIN1/GPIO172
<33> SATA_LED# AD11 SATA_ACT#/GPIO67 TEMPIN2/GPIO173 A5
TEMPIN3/TALERT#/GPIO174 B5
TEMP_COMM C7 2 1 D22 ACIN <31,33,44>
+3VS R367 1 2 10K_0402_5% CH751H-40PT_SOD323-2
VIN0/GPIO175 A3
SATA_X1
HW MONITOR
AD16 SATA_X1 VIN1/GPIO176 B4
VIN2/GPIO177 A4
VIN3/GPIO178 C5
A7 MEM_1V5
SATA_X1 VIN4/GPIO179
1 2 VIN5/GPIO180 B7
C588 B8
VIN6/GBE_STAT3/GPIO181
2
27P_0402_50V8J SATA_X2 AC16 A8

Y4 SATA_X2 VIN7/GBE_LED3/GPIO182
@
R368
25MHZ_20PF_7A25000012 10M_0402_5%
1
1 2 SATA_X2 DO J5 G27
C589 @ DI SPI_DI/GPIO164 NC1
E2 Y2
SPI ROM
27P_0402_50V8J @ CLK SPI_DO/GPIO163 NC2
K4 SPI_CLK/GPIO162
@ CS# K9 SPI_CS1#/GPIO165
G2 ROM_RST#/GPIO161
SB820M_FCBGA605
3 +3VALW 3
20mils U47
8 VCC VSS 4
1
C445 3 W
0.1U_0402_16V4Z 7
2 HOLD
CS# 1 S
CLK 6 C
DI 5 2 DO
D Q
SST25LF080A_SO8-200mil
2
Socket: SP07000F500 & SP07000H900 MEM_1V5 is for gating the

R86
glitch on PCI_AD24
10_0402_5%
+3VS
@ C685
1
2 1
1 0.1U_0402_16V4Z
5
U23 Verify when PCBA back
C155 MEM_1V5 2
P
B @
10P_0402_50V8J Y 4 1 2 VDDR_SW <49>
2 R424 33_0402_5%
@ <20,24> PCI_AD24 1 2 1 A
G
R422 0_0402_5% 2
NC7SZ08P5X_NL_SC70-5
3
C686
150P_0402_50V8J
4 1 4
1 @ 2
PCI_AD24 R423 0_0402_5%
1 : VDDR=1.05V
0 : VDDR=0.9V
For VDDR Voltage Switch, AMD suggest

SCHEMATIC,MB A6052
A B C D E
A B C D E
+1.1VS_VDDC U8E
510mA
1 2 +1.1VS
U8C R369 0_0805_5%
Part 3 of 5
SB800
131mA SB800 10U_0805_10V4Z C590
Y14 VSSIO_SATA_1 VSS_1 AJ2
+3VS AH1 VDDIO_33_PCIGP_1 VDDCR_11_1 N13 1 2 Y16 VSSIO_SATA_2 VSS_2 A28
V6 VDDIO_33_PCIGP_2 VDDCR_11_2 R15 AB16 VSSIO_SATA_3 VSS_3 A2
1 2 Y19 N17 1U_0402_6.3V4Z 2 1 C596 AC14 E5
VDDIO_33_PCIGP_3 VDDCR_11_3 VSSIO_SATA_4 VSS_4
CORE S0
C591 22U_0805_6.3V6M AE5 U13 1U_0402_6.3V4Z 2 1 C594 AE12 D23
1 C592 0.1U_0402_16V4Z VDDIO_33_PCIGP_4 VDDCR_11_4 0.1U_0402_16V4Z C597 VSSIO_SATA_5 VSS_5 1
1 2 AC21 VDDIO_33_PCIGP_5 VDDCR_11_5 U17 2 1 AE14 VSSIO_SATA_6 VSS_6 E25
C593 1 2 0.1U_0402_16V4Z AA2 V12 0.1U_0402_16V4Z 2 1 C598 AF9 E6
PCI/GPIO I/O
C599 1 2 0.1U_0402_16V4Z AB4 V18 AF11 F24
AC8 VDDIO_33_PCIGP_8 VDDCR_11_8 W12 AF13 VSSIO_SATA_9 VSS_9 N15
AA7 VDDIO_33_PCIGP_9 VDDCR_11_9 W18 AF16 VSSIO_SATA_10 VSS_10 R13
AA9 VDDIO_33_PCIGP_10 AG8 VSSIO_SATA_11 VSS_11 R17
+1.1VS_CKVDD L69
AF7 VDDIO_33_PCIGP_11 400mA AH7 VSSIO_SATA_12 VSS_12 T10
AA19 VDDIO_33_PCIGP_12 VDDAN_11_CLK_1 K28 2 1 +1.1VS AH11 VSSIO_SATA_13 VSS_13 P10
K29 FBMA-L11-201209-221LMA30T_0805 AH13 V11
VDDAN_11_CLK_2 VSSIO_SATA_14 VSS_14
VDDAN_11_CLK_3 J28
22U_0805_6.3V6M C595
External Clock, connect to +1.1VS AH16 VSSIO_SATA_15 VSS_15 U15
VDDAN_11_CLK_4 K26 1 2 AJ7 VSSIO_SATA_16 VSS_16 M18
71mA J21 directly, no need thick trace AJ11 V19
CLKGEN I/O
VDDAN_11_CLK_5 1U_0402_6.3V4Z C600 VSSIO_SATA_17 VSS_17
AF22 VDDIO_18_FC_1 VDDAN_11_CLK_6 J20 2 1 AJ13 VSSIO_SATA_18 VSS_18 M11
FLASH I/O
AE25 K21 1U_0402_6.3V4Z 2 1 C601 check can be removed? AJ16 L12
VDDIO_18_FC_2 VDDAN_11_CLK_7 0.1U_0402_16V4Z C602 VSSIO_SATA_19 VSS_19
AF24 VDDIO_18_FC_3 VDDAN_11_CLK_8 J22 2 1 VSS_20 L18
1 2 AC22 0.1U_0402_16V4Z 2 1 C603 A9 J7
R371 0_0402_5% VDDIO_18_FC_4 VSSIO_USB_1 VSS_21
B10 VSSIO_USB_2 VSS_22 P3
VDDRF_GBE_S V1 1 2 K11 VSSIO_USB_3 VSS_23 V4
R372 0_0402_5% B9 AD6
POWER VDDIO_33_GBE_S M10 1 2 D10
VSSIO_USB_4
VSSIO_USB_5
VSS_24
VSS_25 AD4
43mA R373 0_0402_5% D12 AB7
VSSIO_USB_6 VSS_26
+VDDPL_3V_PCIE AE28 VDDPL_33_PCIE D14 VSSIO_USB_7 VSS_27 AC9
GBE LAN
D17 VSSIO_USB_8 VSS_28 V8
L70 +1.1VS_PCIE
600mA E9 VSSIO_USB_9 VSS_29 W9
PCI EXPRESS
+1.1VS 2 1 U26 VDDAN_11_PCIE_1 VDDCR_11_GBE_S_1 L7 1 2 F9 VSSIO_USB_10 VSS_30 W10
FBMA-L11-201209-221LMA30T_0805 V22 L9 R374 0_0402_5% F12 AJ28
VDDAN_11_PCIE_2 VDDCR_11_GBE_S_2 VSSIO_USB_11 VSS_31
V26 VDDAN_11_PCIE_3 F14 VSSIO_USB_12 VSS_32 B29
C604 1 2 22U_0805_6.3V6M V27 F16 U4
C605 1U_0402_6.3V4Z VDDAN_11_PCIE_4 VSSIO_USB_13 VSS_33
1 2 V28 VDDAN_11_PCIE_5 VDDIO_GBE_S_1 M6 1 2 C9 VSSIO_USB_14 VSS_34 Y18
C606 1 2 0.1U_0402_16V4Z V29 P8 R375 0_0402_5% G11 Y10
C607 0.1U_0402_16V4Z VDDAN_11_PCIE_6 VDDIO_GBE_S_2 VSSIO_USB_15 VSS_35
GROUND
1 2 W22 VDDAN_11_PCIE_7 F18 VSSIO_USB_16 VSS_36 Y12
W26 VDDAN_11_PCIE_8 D9 VSSIO_USB_17 VSS_37 Y11
2 2
H12 VSSIO_USB_18 VSS_38 AA11
+VDDPL_3V_SATA H14 VSSIO_USB_19 VSS_39 AA12
+3VALW
93mA H16 VSSIO_USB_20 VSS_40 G4
L71 +1.1VS_SATA
AD14 VDDPL_33_SATA 32mA H18 VSSIO_USB_21 VSS_41 J4
VDDIO_33_S_1 A21 J11 VSSIO_USB_22 VSS_42 G8
+1.1VS 2 1 AJ20 VDDAN_11_SATA_1 VDDIO_33_S_2 D21 J19 VSSIO_USB_23 VSS_43 G9
FBMA-L11-201209-221LMA30T_0805 567mA AF18 B21 2.2U_0603_6.3V4Z 1 2 C608 K12 M12
SERIAL ATA
VDDAN_11_SATA_4 VDDIO_33_S_3 2.2U_0603_6.3V4Z C609 VSSIO_USB_24 VSS_44
AH20 VDDAN_11_SATA_2 VDDIO_33_S_4 K10 1 2 K14 VSSIO_USB_25 VSS_45 AF25
3.3V_S5 I/O
C610 1 2 22U_0805_6.3V6M AG19 L10 K16 H7
C611 1U_0402_6.3V4Z VDDAN_11_SATA_3 VDDIO_33_S_5 VSSIO_USB_26 VSS_46
1 2 AE18 VDDAN_11_SATA_5 VDDIO_33_S_6 J9 K18 VSSIO_USB_27 VSS_47 AH29
C612 1 2 1U_0402_6.3V4Z AD18 T6 +1.1VALW H19 V10
C613 0.1U_0402_16V4Z VDDAN_11_SATA_6 VDDIO_33_S_7 VSSIO_USB_28 VSS_48
1 2 AE16 VDDAN_11_SATA_7 VDDIO_33_S_8 T8 VSS_49 P6
C614 1 2 0.1U_0402_16V4Z N4
VSS_50
Y4 EFUSE VSS_51 L4
check 220ohm bead 113mA C615 2 1 1U_0402_6.3V4Z L8
+AVDD_USB VSS_52
CORE S5
L72 658mA F26 C616 2 1 1U_0402_6.3V4Z D8

VDDCR_11_S_1 VSSAN_HWM
+3VALW 2 1 A18 VDDAN_33_USB_S_1 VDDCR_11_S_2 G26
FBMA-L11-201209-221LMA30T_0805 A19 TBD M19 M20
VDDAN_33_USB_S_2 VSSXL VSSPL_SYS
C617 10U_0805_10V4Z
A20 VDDAN_33_USB_S_3 VDDIO_AZ_S M8 +VDDIO_AZ Need to Check +1.1VALW
1 2 B18 VDDAN_33_USB_S_4
C618 10U_0805_10V4Z +VDDCR_USB
C619
1 2
1U_0402_6.3V4Z
B19 VDDAN_33_USB_S_5 VDDCR_11_USB_S_1 A11 197mA P21 VSSIO_PCIECLK_1 VSSIO_PCIECLK_14 H23
1 2 B20 B11 2 1 P20 H26
USB I/O
C620 1U_0402_6.3V4Z VDDAN_33_USB_S_6 VDDCR_11_USB_S_2 L73 FBMA-L11-160808-221LMT 0603 VSSIO_PCIECLK_2 VSSIO_PCIECLK_15

1 2 C18 VDDAN_33_USB_S_7 M22 VSSIO_PCIECLK_3 VSSIO_PCIECLK_16 AA21
C621 1 2 0.1U_0402_16V4Z C20 47mA C622 1 2 10U_0805_10V4Z M24 AA23
VDDAN_33_USB_S_8 VSSIO_PCIECLK_4 VSSIO_PCIECLK_17
D18 VDDAN_33_USB_S_9 VDDPL_33_SYS M21 +VDDPL_3V M26 VSSIO_PCIECLK_5 VSSIO_PCIECLK_18 AB23
D19 62mA C623 2 1 0.1U_0402_16V4Z P22 AD23
VDDAN_33_USB_S_10 C624 VSSIO_PCIECLK_6 VSSIO_PCIECLK_19
D20 VDDAN_33_USB_S_11 VDDPL_11_SYS_S L22 +VDDPL_11V 2 1 0.1U_0402_16V4Z P24 VSSIO_PCIECLK_7 VSSIO_PCIECLK_20 AA26
E19 VDDAN_33_USB_S_12 17mA P26 VSSIO_PCIECLK_8 VSSIO_PCIECLK_21 AC26
PLL
VDDPL_33_USB_S F19 +VDDPL_3V_USB T20 VSSIO_PCIECLK_9 VSSIO_PCIECLK_22 Y20

L74 +1.1V_USB
200mA 5mA +3VALW
T22 VSSIO_PCIECLK_10 VSSIO_PCIECLK_23 W21
+1.1VALW 2 1 C11 VDDAN_11_USB_S_1 VDDAN_33_HWM_S D6 +3V_HWM T24 VSSIO_PCIECLK_11 VSSIO_PCIECLK_24 W20
FBMA-L11-160808-221LMT 0603 +VDDLX_3V
3
D11 VDDAN_11_USB_S_2 197mA V20 VSSIO_PCIECLK_12 VSSIO_PCIECLK_25 AE26
3
VDDXL_33_S L20 2 1 J23 VSSIO_PCIECLK_13 VSSIO_PCIECLK_26 L21
C625 2 1 2.2U_0603_6.3V4Z Need to Check L75 FBMA-L11-160808-221LMT 0603 K20
C626 2 VSSIO_PCIECLK_27
1 0.1U_0402_16V4Z C627 1 2 2.2U_0603_6.3V4Z
SB820M_FCBGA605 Part 5 of 5
SB820M_FCBGA605
+VDDPL_11V +1.1VALW +VDDPL_3V_USB +3VALW +3V_HWM +3VALW

+VDDPL_3V_PCIE +3VS +VDDPL_3V +3VS
L76 L77 L78
L79 L80 2 1 2 1 0_0603_5% 2 1
2 1 2 1 FBMA-L11-160808-221LMT 0603 FBMA-L11-160808-221LMT 0603
FBMA-L11-160808-221LMT 0603 FBMA-L11-160808-221LMT 0603
1 1 1 1 1
1 1 1 C630 C632
C628 C629 C631 C633
C634 C635 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z 2.2U_0603_6.3V4Z
0.1U_0402_16V4Z 2 2 2 2 2
2.2U_0603_6.3V4Z 2.2U_0603_6.3V4Z
2 2 2
+VDDPL_3V_SATA +3VS +VDDIO_AZ +3VALW
L81
4 4
2 1 1 2
FBMA-L11-160808-221LMT 0603 R376 0_0402_5% +1.5VS
1 2
1 1 1 R52 0_0402_5%
C636 @
C637 C638
0.1U_0402_16V4Z 2.2U_0603_6.3V4Z 2.2U_0603_6.3V4Z
2 2 2
For 3V AZ device
SCHEMATIC,MB A6052
A B C D E
A B C D E
REQUIRED STRAPS Check Internal PU/PD
AZ_SDOUT PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4 LPC_CLK0 LCP_CLK1 GPIO200 GPIO199
PULL LOW POWER ALLOW PCIE WATCHDOG USE Inter CLK EC CLOCKGEN
HIGH MODE GEN2 TIMER DEBUG Gen Mode ENABLE ENABLE H,H = Reserved
ENABLE STRAP Enable
1 1
H,L = SPI ROM (Default )
PULL Performance FORCE PCIE WATCHDOG IGNORE Inter CLK EC CLOCKGEN L,H = LPC ROM
LOW MODE GEN1 TIMER DEBUG Gen Mode DISABLE DISABLE L,L = FWH ROM
DISABLE STRAP Disable
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
+VDDIO_AZ +3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
2.2K_0402_5%
R385
R377
R378
R379
R380
R381
R382
R383
R384
2
2
@ @ @ @ @ @ @
<21> HDA_SDOUT @
<20> PCI_CLK1
<20> PCI_CLK2
<20> PCI_CLK3
<20> PCI_CLK4
<20,31> CLK_PCI_EC
<20,32> CLK_PCI_SIO
<21> GPIO200
2 <21> GPIO199 2
2.2K_0402_5%
1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
2.2K_0402_5%
R393
R394
R386
R387
R388
R389
R390
R391
R392
2
2
@
+3VS +3VS
DEBUG STRAPS
10K_0402_5%
10K_0402_5%
1
1
R395
R396
SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
3 3
PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23
2
USE PCI DISABLE ILA USE FC PLL USE DEFAULT DISABLE PCI <20> PCI_AD29
PULL PLL AUTORUN PCIE STRAPS MEM BOOT <20> PCI_AD28
HIGH <20> PCI_AD27
<20> PCI_AD26
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
<20> PCI_AD25
<20,22> PCI_AD24
<20> PCI_AD23
PULL BYPASS ENABLE ILA BYPASS USE EEPROM ENABLE PCI
LOW PCI PLL AUTORUN FC PLL PCIE STRAPS MEM BOOT
1
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
R397
R398
R399
R400
R401
2
2
Check AD29,AD28 strap function @ @ @ @ @
check default
4 4

SCHEMATIC,MB A6052
A B C D E
A B C D E
< SATA HDD Conn > < SATA ODD Conn >
+5VS +3VS JODDB
+5VS
1.2A Place closely JHDD SATA CONN. +3VS rail reserve for SSD GND 14
GND 13
1 1 1 1 1 1 1 1 12 12
C201 C202 C203 C204 C205 C206 C207 C208 11
@ @ @ @ 11
10 10
10U_0805_10V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 10U_0805_10V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 9
2 2 2 2 2 2 2 2 9
8 8
7 7
1 SATA_IRX_DTX_P1 C213 1
6 6 1 2 0.01U_0402_25V7K SATA_RXP1_C <22>
5 SATA_IRX_DTX_N1 C214 1 2 0.01U_0402_25V7K
5 SATA_RXN1_C <22>
4 4
3 SATA_TXN1 C215 1 2 0.01U_0402_25V7K
3 SATA_STX_DRX_N1 <22>
JHDD 2 SATA_TXP1 C216 1 2 0.01U_0402_25V7K
2 SATA_STX_DRX_P1 <22>
1 1
GND 1
2 SATA_TXP0 C209 1 2 0.01U_0402_25V7K ACES_88058-120N
A+ SATA_STX_DRX_P0 <22>
3 SATA_TXN0 C210 1 2 0.01U_0402_25V7K
A- SATA_STX_DRX_N0 <22>
GND 4 @
5 SATA_IRX_DTX_N0 C211 1 2 0.01U_0402_25V7K
B- SATA_RXN0_C <22>
6 SATA_IRX_DTX_P0 C212 1 2 0.01U_0402_25V7K
B+ SATA_RXP0_C <22>
GND 7
V33 8 +3VS
V33 9
V33 10
GND 11
GND 12
GND 13
V5 14 +5VS
V5 15
V5 16
GND 17
Reserved 18
GND 19
V12 20
24 GND V12 21
23 GND V12 22
2 @ SUYIN_127072FR022G210ZR_RV 2
eSATA/USB Conn +USB_VCCB +USB_VCCB
2A W=60mils
U11
W=60mils
1
3 @C373
@ C373 1 3
1 GND VOUT 8 2 4.7U_0805_10V4Z 1 1
2 7 + C376 C377 C378
+5VALW VIN VOUT
3 6 D14
VIN VOUT 220U_6.3V_M 0.1U_0402_16V7K 1000P_0402_50V7K
<30,31> USB_EN# 4 EN FLG 5 USB_OC#2 <21,31> 2
2 2 2
1
G547E2P11U_SO8 3
PJDLC05_SOT23-3
JESATA
1 USB
USB20_N2_R_S VBUS
2 D-
USB20_P2_R_S 3 D+
Reserve for EMI request 4 GND
5 GND
@ R196 1 2 0_0402_5% C379 1 2 0.01U_0402_25V7K SATA_TXP3 6
<22> SATA_STX_DRX_P3 A+
C380 1 2 0.01U_0402_25V7K SATA_TXN3 7 ESATA
<22> SATA_STX_DRX_N3 A-
8 GND
WCM-2012-900T_0805 C381 2 1 0.01U_0402_25V7K SATA_RXN3 9
<22> SATA_RXN3_C B-
C382 2 1 0.01U_0402_25V7K SATA_RXP3 10
<22> SATA_RXP3_C B+
1 2 USB20_N2_R_S 11
<21> USB20_N2 1 2 GND
12 GND
4 3 USB20_P2_R_S 13
<21> USB20_P2 4 3 GND
14 GND
L33 15 GND
@ TYCO_1759576-1
1 2
@R198
@ R198 0_0402_5%
4 4

SCHEMATIC,MB A6052
A B C D E
5 4 3 2 1
UL1
<11> PCIE_PTX_C_IRX_P3 CL1 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_P3 22 HSOP LED3/EEDO 31 LL1,CL13 will be changed to CL4,CL5,CL6,CL7 close to
37 LAN_SK_LINK# +LAN_VDD10
CL2 LED1/EESK 2.2uH&4.7uF after EVT test Pin 27,39,47,48
<11> PCIE_PTX_C_IRX_N3 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_N3 23 HSON LED0 40 LAN_ACTIVITY#
LL1 +3V_LAN
17 30 RL2 2 1 10K_0402_5% +LAN_REGOUT 1 2
<11> PCIE_ITX_C_PRX_P3 HSIP EECS/SCL
18 32 RL1 2 1 10K_0402_5% 4.7UH_1008HC-472EJFS-A_5%_1008
<11> PCIE_ITX_C_PRX_N3 HSIN EEDI/SDA
1 2 1 2
Layout Note: LL1 must be 0.1U_0402_16V4Z CL4
RL19 0_0402_5% 16 1 LAN_MDI0+ within 200mil to Pin36, CL13 CL9 1 2
<16> CLKREQ_LAN# CLKREQB MDIP0
D 2 LAN_MDI0- CL13,CL9 must be within 22U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z CL5 D
MDIN0 LAN_MDI1+ 200mil to LL1 2 1
<12,15,20,28,31,32,35> PLT_RST# 25 PERSTB MDIP1 4 1 2
5 LAN_MDI1- +LAN_REGOUT: Width =60mil 0.1U_0402_16V4Z CL6
MDIN1
<16> CLK_PCIE_LAN 19 REFCLK_P NC/MDIP2 7 1 2
20 8 0.1U_0402_16V4Z CL7
<16> CLK_PCIE_LAN# REFCLK_N NC/MDIN2
NC/MDIP3 10
NC/MDIN3 11
+3V_LAN LAN_X1 43 CKXTAL1
1 2 EC_SWI# LAN_X2 44 CKXTAL2 DVDD10 13 +LAN_VDD10
RL3 100K_0402_5% 29 +LAN_VDD10 +LAN_EVDD10
DVDD10
@ DVDD10 41
EC_SWI# 28 2 1
<21> EC_SWI# LANWAKEB 0_0603_5% LL2 1 2 CL19,CL20,CL21,CL22 close to
+3VS ISOLATEB 26 27
ISOLATEB DVDD33 +3V_LAN Pin 3,13,29,45
39 CL18 CL17
DVDD33 1U_0402_6.3V4Z 0.1U_0402_16V4Z +LAN_VDD10
1
2 1
14 NC/SMBCLK AVDD33 12 +3V_LAN
RL6 15 42 +3V_AVDDXTAL 1 2
1K_0402_1% NC/SMBDATA AVDD33
+3V_LAN 1 RL22 2 1K_0402_5% 38 GPO/SMBALERT AVDD33 47 Close to Pin 21 0.1U_0402_16V4Z CL19
AVDD33 48 1 2
0.1U_0402_16V4Z CL20
2
ISOLATEB ENSWREG 33 1 2
ENSWREG 0.1U_0402_16V4Z CL21
EVDD10 21 +LAN_EVDD10
+LAN_VDDREG 34 VDDREG 1 2
35 3 +LAN_VDD10 0.1U_0402_16V4Z CL22
RL7 VDDREG AVDD10
AVDD10 6
15K_0402_5% 9 +3V_LAN +LAN_VDDREG
AVDD10
1 2 46 RSET AVDD10 45
C RL5 2.49K_0402_1% 2 1 C
24 36 +LAN_REGOUT 0_0603_5% LL3 1 2
GND REGOUT
49 PGND CL28 CL29
4.7U_0603_6.3V6K 0.1U_0402_16V4Z
RTL8105E-GR QFN _6X6 2 1
+3V_LAN +3V_AVDDXTAL RL8

+3VALW TO +3V_LAN 0_0402_5%
+3V_LAN
LAN Conn.
+3VALW RL9
+3VALW +LAN_VDD10
RL4 @ 0_0402_5% JLAN
0_0402_5% Reserved For 1.05V Crystal LAN_ACTIVITY# 2 RL10 1 LAN_ACTIVITY#_R 12 Amber LED-
2
Vgs=-4.5V,Id=3A,Rds<97mohm 1 150_0402_5%
RL25 2 1 11 16
100K_0402_5% ENSWREG CL11 +3V_LAN RL17 150_0402_5% Amber LED+ SHLD4
2
CL12 0.1U_0402_16V4Z 8 15
0.1U_0402_16V7K QL1 2 PR4- SHLD3
1
S
RL23 CL11 close to pin42 7
1 G PR4+
<31> WOL_EN# 1 2 2 0_0402_5%
RL16 47K_0402_5% @ RJ45_MIDI1- 6
D PR2-
1
1
CL14 AO3413_SOT23 5
+3V_LAN YL1 PR3-
0.01U_0402_25V7K
LAN_X1 2 1 LAN_X2 4
2 PR3+
25MHZ_20PF_7A25000012 RJ45_MIDI1+ 3 PR2+
B
1 1 1 1 B
RJ45_MIDI0- 2
CL15 CL8 1U_0402_6.3V4Z CL26 CL27 PR1-
SHLD2 14
4.7U_0805_10V4Z 27P_0402_50V8J 27P_0402_50V8J RJ45_MIDI0+ 1
@ 2 2 2 2 PR1+
LAN_SK_LINK# 2 RL14 1 LAN_SK_LINK#_R 10 13
150_0402_5% Green LED- SHLD1
+3V_LAN 2 1 9 Green LED+

RL18 150_0402_5% LIYO_101005-00803-3
@
RJ45_GND 1 2 1000P_1808_3KV7K LANGND

CL36 1 1
CL37 CL38
UL3
0.1U_0402_16V4Z 4.7U_0603_6.3V6K
LAN_MDI0+ RJ45_MIDI0+ 2 2
1 TD+ TX+ 16
LAN_MDI0- 2 15 RJ45_MIDI0- CL42 1000P_0402_50V7K
TD- TX-
3 CT CT 14 2 1 1 2
4 13 RL15 75_0402_1%
NC NC CL41 1000P_0402_50V7K
5 NC NC 12
6 11 2 1 1 2 RJ45_GND
LAN_MDI1+ CT CT RJ45_MIDI1+ RL13 75_0402_1%
7 RD+ RX+ 10
LAN_MDI1- 8 9 RJ45_MIDI1-
RD- RX-
Place these components 1 LF-H1201P-2

A A
colsed to LAN chip CL34
0.1U_0402_25V4K
2

SCHEMATIC,MB A6052
5 4 3 2 1
5 4 3 2 1
D D
@ CC1
1 2 100P_0402_50V8J
RC1
6.19K_0402_1% UC1
2 1 1 REFE
17 CR_LED#
GPIO0 CR_LED# <33>
USB20_N5 2
+3VS_CR <21> USB20_N5 DM
USB20_P5 3 24 CLK_48M_CR < 48MHz >
<21> USB20_P5 DP CLK_IN CLK_48M_CR <16>
+3VS 1 2 4 3V3_IN XD_D7 23

RC4 0_0603_5% +VCC_3IN1 5
V1_8 CARD_3V3 MSBS
1 1 CC4 6 V18 SP14 22
CC3 0.1U_0402_16V4Z
1 21 SD_DATA2_MS_DATA5
CC2 SP13 MS_DATA1_SD_DATA3
7 XD_CD# SP12 20
4.7U_0805_10V4Z 1U_0402_6.3V4Z 19
2 2 SDWP_MSCLK SP11 SDCMD
8 SP1 SP10 18
2 MSCD# MS_DATA0_SD_DATA5
9 SP2 SP9 16
SD_DATA1 10 15 MS_DATA2_SDCLK
SP3 SP8
EPAD
SD_DATA0 11 14
MS_DATA3_SD_DATA7 SP4 SP7 SDCD#
12 SP5 SP6 13
RTS5138-GR_QFN24_4X4
25
C C
< 3 in 1 Card Reader >

JREAD
1 SDWP_MSCLK
SD-WP SD_DATA1
SD-DAT1 2
3 SD_DATA0
SD-DAT0
SD-GND 4
MS-GND 5
6 MSBS
MS-BS MS_DATA2_SDCLK
SD-CLK 7
8 MS_DATA1_SD_DATA3
MS-DAT1 MS_DATA0_SD_DATA5
MS-DAT0 9
SD-VCC 10 +VCC_3IN1
MS-DAT2 11
SD-GND 12 1 1
13 MSCD# CC5 CC6
MS-INS MS_DATA3_SD_DATA7
MS-DAT3 14
15 SDCMD 0.1U_0402_16V4Z 1U_0402_6.3V4Z
SD-CMD 2 2
MS-SCLK 16
MS-VCC 17
SD-DAT3 18
MS-GND 19
22 20 SD_DATA2_MS_DATA5
GND1 SD-DAT2 SDCD#
23 GND2 SD-CD 21
B @TAITW_R009-025-LR_NR B
@ CC7 2 1 @ RC21 2 MS_DATA2_SDCLK
10P_0402_50V8J 10_0402_5%
@ CC8 2 1 @ RC31 2 SDWP_MSCLK
10P_0402_50V8J 10_0402_5%
A A

SCHEMATIC,MB A6052
5 4 3 2 1
A B C D E
< BlueTooth Interface, USB port6 >
+3VS +3VS
2
2
R199 C383
@
2
100K_0402_5% 0.1U_0402_16V7K
1 BT@ R50
3
S
1 @ R201 1
G 0_0603_5%
<20> BT_PWR# 1 2 47K_0402_5% 2
1 Q27
1
C386 @ D AO3413_SOT23
1
@
0.01U_0402_25V7K
2
+BT_VCC
Inrush current = 0A
WLAN&BT Combo module circuits

BT BT
on module on module
Enable Disable
< Bluetooth Connector >
BT_CRTL HI LO
BT_PWR# LO HI
(MAX=200mA)
**If +3V_WLAN is +3VS, please +BT_VCC
remove D21. 1 1
C488 C487
BT@ BT@
D2 4.7U_0805_10V4Z 0.1U_0402_16V4Z
SUSP# 1 BT_CTRL 2 2
<31,34,46,49,51> SUSP# 2
2 2
CH751H-40PT_SOD323-2 @ ACES_87213-0600G
1
D
1 1
BT_PWR# 2 Q8 2
G USB20_P6 2
<21> USB20_P6 3 3
S 2N7002_SOT23-3 USB20_N6 4
<21> USB20_N6
3
BT@ R442 1 4
<20> BT_RST# 2 0_0402_5% 5 5 G1 7
1 <20> BT_DET# 6 6 G2 8
C489 BT@ JBT
0.1U_0402_16V4Z 2
< PCIe Mini Card for WLAN >

+1.5VS +3VS
1 1 1 1 1 1
CM1 CM2 CM3 CM4 CM5 CM6
0.01U_0402_25V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.01U_0402_25V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z

2 2 2 2 2 2
3 +1.5VS +3VS 3
JWLAN
1 1 2 2
3 3 4 4
BT_CTRL 5 6
5 6
<16> CLKREQ_MCARD2# 7 7 8 8
9 9 10 10
<16> CLK_PCIE_MCARD2# 11 11 12 12
<16> CLK_PCIE_MCARD2 13 13 14 14
15 15 16 16
17 17 18 18
19 19 20 20 WL_OFF# <31>
21 22 PLT_RST#
21 22 PLT_RST# <12,15,20,26,31,32,35>
<11> PCIE_PTX_C_IRX_N2 23 23 24 24
<11> PCIE_PTX_C_IRX_P2 25 25 26 26
27 27 28 28
29 30 SMB_CK_CLK1
29 30 SMB_CK_CLK1 <21>
31 32 SMB_CK_DAT1 SMB_CK_DAT1 <21>
<11> PCIE_ITX_C_PRX_N2 31 32
<11> PCIE_ITX_C_PRX_P2 33 33 34 34
35 36 USB20_N8 USB20_N8 <21>
35 36 USB20_P8
37 37 38 38 USB20_P8 <21>
+3VS 39 39 40 40
41 41 42 42
43 43 44 44
45 45 46 46
47 47 48 48
E51_TXD RM1 1 2 0_0402_5% E51_TXD_R 49 50
<31> E51_TXD E51_RXD RM2 1 49 50
<31> E51_RXD 2 0_0402_5% E51_RXD_R 51 51 52 52
53 GND1 GND2 54
4 @ FOX_AS0B226-S40N-7F 4

SCHEMATIC,MB A6052
A B C D E
5 4 3 2 1
Codec 600 mA RA2

+PVDD1 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z +5VS
1 1 0_0603_1% 1 1
CA57 CA44
+DVDD_IO CA56 CA43
2
RA1 JA1 2 2 2 2
2
+3VS 2 1 0.1U_0402_16V4Z JUMP_43X39 10U_0805_10V4Z 10U_0805_10V4Z
0_0603_1%
1
1 1 @ place close to chip
@ RA19 CA2 CA1
1
+1.5VS 2 1
D 0_0603_1% 10U_0805_10V4Z +3VS_DVDD RA11 D
2 2 +PVDD2 0.1U_0402_16V4Z
2 1 +5VS
1 1 0_0603_1% 1 1
RA17 0.1U_0402_16V4Z CA61 @ CA62
+3VS 2 1 35 mA @ CA63 @ @ CA58
0_0603_1% 1 1 0.1U_0402_16V4Z
2 2 2 2
CA8 CA7 +AVDD 10U_0805_10V4Z 10U_0805_10V4Z
10U_0805_10V4Z RA3
2 2 68 mA 10U_0805_10V4Z 0.1U_0402_16V4Z 2 1 +5VS
0_0603_1%
place close to chip
39
46
25
38
1 1 1 1
9
UA1 CA3 CA4 CA5 CA6
DVDD_IO
PVDD1
PVDD2
AVDD1
AVDD2
DVDD
2 2 2 2 place close to chip
10U_0805_10V4Z 0.1U_0402_16V4Z
23 LINE1_L SPK_OUT_L+ 40 SPKL+ <30>

24 LINE1_R SPK_OUT_L- 41 SPKL- <30>
14 LINE2_L SPK_OUT_R+ 45 SPKR+ <30>
15 LINE2_R SPK_OUT_R- 44 SPKR- <30>
4.7U_0805_10V4Z CA23
2 1 21 32 RA4 75_0402_1%
<30> MIC1_R_L MIC1_L HP_OUT_L HP_L <30>
Ext. Mic 22 MIC1_R HP_OUT_R 33
RA5 75_0402_1% Beep sound
<30> MIC1_R_R 2 1 HP_R <30>
16 MIC2_L
C 4.7U_0805_10V4Z CA29 17 C
MIC2_R
10
SYNC AZ_SYNC_HD <21>
EC Beep RA7
<18> INT_MIC_DATA 2 GPIO0/DMIC_DATA BCLK 6 AZ_BITCLK_HD <21> <31> EC_BEEP# 1 2
47K_0402_5%
<18> INT_MIC_CLK 1 2 3 GPIO1/DMIC_CLK
RA20 FBMA-L10-160808-301LMT_2P 5 AZ_SDOUT_HD <21>
SDATA_OUT
4 PD# SDATA_IN 8 AZ_SDIN0_HD_R 2 1 AZ_SDIN0_HD <21>
PCI Beep RA8
CA13
RA6 33_0402_5% 1 2 1 2 MONO_IN
<21> PCH_SPKR
47K_0402_5%
11 47 0.1U_0402_16V4Z
<21> AZ_RST_HD# RESET# EAPD
SPDIFO 48
1 2 MONO_IN 12
CA12 100P_0402_50V8J PCBEEP
MONO_OUT 20
1
1
SENSE_A 13 SENSE A RA12 CA18
MIC2_VREFO 29
18 10K_0402_5% 0.1U_0402_16V4Z
SENSE B 2
30 +MIC1_VREFO_R CA28 10U_0805_10V4Z
2
MIC1_VREFO_R
1 2 36 CBP LDO_CAP 28 1 2
CA15
2.2U_0603_6.3V4Z 35 27 AC_VREF
CBN VREF
+MIC1_VREFO_L 31 19 AC_JDREF2 RA9 1 20K_0402_1%
MIC1_VREFO_L JDREF
1 1
43 PVSS2 CPVEE 34 1 2
42 CA14 2.2U_0603_6.3V4Z CA17 CA16
B CA47 1 PVSS1 B
2 0.1U_0603_50V7K 49 DVSS2 AVSS1 26 10U_0805_10V4Z
2 2
7 DVSS1 AVSS2 37
CA48 1 2 0.1U_0603_50V7K 0.1U_0402_16V4Z
ALC259-GR_QFN48_7X7
CA49 1 2 0.1U_0603_50V7K place close to chip
CA50 1 2 0.1U_0603_50V7K
DGND AGND
1 2
RA18 0_0603_5%
Sense Pin Impedance Codec Signals Function

place close to chip
39.2K PORT-I (PIN 32, 33) Headphone out SENSE_A
<30> MIC_SENSE 2 1
RA10 20K_0402_1%
20K PORT-B (PIN 21, 22) Ext. MIC
SENSE A
10K PORT-C (PIN 23, 24)
<30> NBA_PLUG
RA21 39.2K_0402_1%
5.1K (PIN 48)
A A
39.2K PORT-E (PIN 14, 15)
SENSE B 20K PORT-F (PIN 16, 17)

10K PORT-H (PIN 20) Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title
SCHEMATIC,MB A6052
5 4 3 2 1
Speaker Connector HeadPhone/LINE Out JACK
placement near Audio Codec
RA13
SPKL+ 2 1 SPK_L1
<29> SPKL+
0_0603_1% 1
CA22 DA9
@ 10U_0805_10V4Z 2 3
2 CA24 1
1 1U_0402_6.3V4Z 2
@
CA21 1 PACDN042Y3R_SOT23-3 JSPK
RA14 @ 10U_0805_10V4Z SPK_L1 1
SPKL- 2 SPK_L2 SPK_L2 1
<29> SPKL- 2 1 2 2
0_0603_1% SPK_R1 3
SPK_R2 3
4 4
RA15
DA6
3
ACES_85204-0400N
@
Ext.MIC/LINE IN JACK
SPKR+ 2 1 SPK_R1 1
<29> SPKR+
0_0603_1% 1 2
RA23 2 RA22
1 +MIC1_VREFO_R
CA25 PACDN042Y3R_SOT23-3 1K_0402_5% 2.2K_0402_5%
@ 10U_0805_10V4Z 2 2 1 MIC1_R
2 <29> MIC1_R_R
CA27
1 1U_0402_6.3V4Z
@ 2 1 MIC1_L
1 <29> MIC1_R_L
CA26 1K_0402_5%
RA16 @ 10U_0805_10V4Z RA24 2 RA25
1 +MIC1_VREFO_L
SPKR- 2 SPK_R2 2.2K_0402_5%
<29> SPKR- 2 1
0_0603_1%
+5VALW +USB_VCCA Audio & USB Sub-Board Conn.

1.4A W=60mils
U25 +USB_VCCA
1 8 C446 1 2 4.7U_0805_10V4Z
GND VOUT
2 VIN VOUT 7
3 6 @ W=80mils JUSBB
USB_EN# VIN VOUT
<25,31> USB_EN# 4 EN FLG 5 USB_OC#0 <21,31> 1
G547E2P11U_SO8 2
3
4
USB20_N0_R 5
USB20_P0_R 6
7
L34 8
USB20_P0_R USB20_N1_R 9
<21> USB20_P0 4 4 3 3 10
USB20_P1_R
11
USB20_N0_R 12
<21> USB20_N0 1 1 2 2 13
HP_R
<29> HP_R 14
HP_L
<29> HP_L 15
WCM-2012-900T_0805 AGND
MIC1_L 16
MIC1_R 17
NBA_PLUG 18
<29> NBA_PLUG 19
<29> MIC_SENSE MIC_SENSE
20
@ ACES_85201-20051
L35
4 3 USB20_P1_R
<21> USB20_P1 4 3
1 2 USB20_N1_R
<21> USB20_N1 1 2
WCM-2012-900T_0805

SCHEMATIC,MB A6052
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 401851 A
A B C D E
+3VL +3VL_EC +EC_AVCC

L36
2 1 0_0603_5%
111
125
22
33
96
67
9
U14
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
@C55
@ C55 2 1 @R44
@ R44 1 2 CLK_PCI_EC
GATEA20 1 GA20/GPIO00 21
1 10P_0402_50V8J 10_0402_5% <21> GATEA20 R330 1 INVT_PWM/PWM1/GPIO0F 1
<21> KB_RST# 2 0_0402_5%
2 KBRST#/GPIO01 BEEP#/PWM2/GPIO10 23 EC_BEEP# <29>
SERIRQ 3 SERIRQ# 26
<20,32> SERIRQ FANPWM1/GPIO12
LPC_FRAME# 4 LFRAME# 27 ACOFF C389
<20,32> LPC_FRAME# ACOFF/FANPWM2/GPIO13 ACOFF <46>
<20,32> LPC_AD3 LPC_AD3 5 LAD3 1 2 100P_0402_50V8J ECAGND
<20,32> LPC_AD2 LPC_AD2 7 LAD2 PWM Output
<20,32> LPC_AD1 LPC_AD1 8 LAD1 63 BATT_TEMPA
BATT_TEMP/AD0/GPIO38 BATT_TEMPA <45>
<20,32> LPC_AD0 LPC_AD0 10 LAD0 LPC & MISC 64 R208
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A 65 1 2 100K_0402_5% ADP_I <46>
CLK_PCI_EC 12 AD Input 66
<20,24> CLK_PCI_EC PCICLK AD3/GPIO3B ADP_V <46>
R8 1 2 0_0402_5% 13 75 C387
<12,15,20,26,28,32,35> PLT_RST# PCIRST#/GPIO05 AD4/GPIO42
+3VL R209 1 2 47K_0402_5% ECRST# 37 76 1 2 0.22U_0603_16V4Z
EC_SCI# ECRST# SELIO2#/AD5/GPIO43
<21> EC_SCI# 20 SCI#/GPIO0E
<33> WL_BT_LED# WL_BT_LED# 38 CLKRUN#/GPIO1D
DAC_BRIG/DA0/GPIO3C 68
C388 2 1 0.1U_0402_16V4Z 70 EN_DFAN1
EN_DFAN1/DA1/GPIO3D EN_DFAN1 <5>
DA Output 71 IREF
IREF/DA2/GPIO3E IREF <46>
KSI0 55 72 CHGVADJ
KSI0/GPIO30 DA3/GPIO3F CHGVADJ <46>
KSI1 56
KSI2 KSI1/GPIO31
57 KSI2/GPIO32
KSI3 58 83
KSI4 KSI3/GPIO33 PSCLK1/GPIO4A
59 KSI4/GPIO34 PSDAT1/GPIO4B 84 USB_EN# <25,30>
KSI5 60 85
EC_SMB_DA2 R210 1 KSI6 KSI5/GPIO35 PSCLK2/GPIO4C
2 2.2K_0402_5% +3VS 61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86
KSI7 62 87 TP_CLK
KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA TP_CLK <33>
39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA <33>
EC_SMB_CK2 R211 1 2 2.2K_0402_5% KSO1 40
KSI[0..7] KSO2 KSO1/GPIO21
<32,33> KSI[0..7] 41 KSO2/GPIO22
KSO3 42 97
KSO[0..17] KSO3/GPIO23 SDICS#/GPXOA00 VGATE <34,50>
EC_SMB_DA1 R212 1 2 2.2K_0402_5% +3VL KSO4 43 98
<32,33> KSO[0..17] KSO4/GPIO24 SDICLK/GPXOA01 WOL_EN# <26>
KSO5
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW#
VLDT_EN <34>
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW# <33>
EC_SMB_CK1 R213 1 2 2.2K_0402_5% KSO7 46 SPI Device Interface
2 KSO8 KSO7/GPIO27 2
47 KSO8/GPIO28
KSO9 48 119
KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO <32>
KSO10 49 120
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI <32>
KSO11 50 SPI Flash ROM 126
KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK <32>
KSO12 51 128
KSO12/GPIO2C SPICS# SPI_CS# <32>
KSO13 52
TP_CLK R215 1 KSO13/GPIO2D
2 4.7K_0402_5% +5VS KSO14 53 KSO14/GPIO2E
KSO15 54 73
KSO16 KSO15/GPIO2F CIR_RX/GPIO40
81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74
TP_DATA R216 1 2 4.7K_0402_5% KSO17 82 89 FSTCHG
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG <46>
90 BATT_FULL_LED#
BATT_CHGI_LED#/GPIO52 BATT_FULL_LED# <33>
CAPS_LED#/GPIO53 91 CAPS_LED# <32>
EC_SMB_CK1 77 GPIO 92 BATT_LOW_LED#
<45> EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_CHG_LOW_LED# <33>
EC_SMB_DA1 78 93
<45> EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_ON_LED# <33>
EC_SMB_CK2 79 SM Bus 95 SYSON
<7,43> EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON <34,48>
SYSON R217 1 2 10K_0402_5% EC_SMB_DA2 80 121 VR_ON
<7,43> EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <34,50>
127 ACIN_D
AC_IN/GPIO59 R219
SUSP# R218 1 2 10K_0402_5% 2 1 10K_0402_5%
PM_SLP_S3# 6 100 EC_RSMRST#
<21> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# <21>
PM_SLP_S5# 14 101
<21> PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# <21>
LID_SW# R220 2 1 100K_0402_5% +3VALW EC_SMI# 15 102
<21> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <33>
16 LID_SW#/GPIO0A EC_SWI#/GPXO06 103
17 104 SB_PWRGD
SUSP#/GPIO0B ICH_PWROK/GPXO06 BKOFF# SB_PWRGD <21>
18 PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08 105 BKOFF# <18>
ON/OFFBTN# R221 2 1 100K_0402_5% +3VL 19 GPIO 106 WL_OFF#
EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# <28>
<18> EC_INVT_PWM 25 EC_THERM#/GPIO11 GPXO10 107
FAN_SPEED1 28 108 EC_SEL
<5> FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11
KSO1 R222 2 1 47K_0402_5% 29
E51_TXD FANFB2/GPIO15
<28> E51_TXD 30 EC_TX/GPIO16
E51_RXD 31 110
KSO2 R223 <28> E51_RXD EC_RX/GPIO17 PM_SLP_S4#/GPXID1
2 1 47K_0402_5% <33> ON/OFFBTN#
ON/OFFBTN# 32 ON_OFF/GPIO18 ENBKL/GPXID2 112 ENBKL
ENBKL <36>
3 PWR_SUSP_LED# USB_OC#2 3
<33> PWR_SUSP_LED# 34 PWR_LED#/GPIO19 GPXID3 114 USB_OC#2 <21,25>
NUM_LED# 36 GPI 115
<32> NUM_LED# NUMLED#/GPIO1A GPXID4
116 SUSP#
GPXID5 SUSP# <28,34,46,49,51>
117 PBTN_OUT#
GPXID6 PBTN_OUT# <21>
C390 118 USB_OC#0
GPXID7 USB_OC#0 <21,30>
R782 1 2 15P_0402_50V8J CRY1 122 XCLK1
123 XCLK0 V18R 124 C391 2 1 4.7U_0805_10V4Z
2 1 100K_0402_5% E51_TXD Y10
1
AGND
GND
GND
GND
GND
GND
R783 1 2 100K_0402_5% PLT_RST# 2 1
NC OSC @ R224
3 4 20M_0402_5% KB926QFD3_LQFP128_14X14
11
24
35
94
113
69
NC OSC
2
32.768KHZ_12.5PF_Q13MC14610002
C392
ECAGND
1 2 15P_0402_50V8J CRY2 +3VL
R227 +3VL_EC L37 1 2 0_0603_5% EC_SEL EC_VERSION
1
1 2 150K_0402_5% +3VL
C393 R270
+EC_AVCC 1 2 0.1U_0402_16V4Z 100K_0402_5%
HIGH KB926D3
2
ACIN_D 2 1 D15 0_0603_5% 1 2 L38
ACIN <22,33,44>
CH751H-40PT_SOD323-2 EC_SEL LOW KB926E0
+3VL_EC
C394
1
2 1 R272 @
1 1 1 1 1 100K_0402_5%
4 100P_0402_50V8J C395 C396 C397 C398 C399 4
2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z 1000P_0402_50V7K
2 2 2 2 2

SCHEMATIC,MB A6052
A B C D E
A B C D E
+3VL
< ROM Part > < MDC 1.5 Conn >
U46 JMDC
SPI_CS# 1 8
<31> SPI_CS# CS# VCC
1 1 1 1 GND1 RES0 2 +MDC_VCC
C400 C402 C401 <21> HDA_SDOUT_MDC HDA_SDOUT_MDC 3 4
@ @ IAC_SDATA_OUT RES1
<31> EC_SI_SPI_SO 2 SO HOLD# 7 5 GND2 3.3V 6 +3VALW
10P_0402_50V8J 10P_0402_50V8J 0.1U_0402_16V4Z <21> HDA_SYNC_MDC HDA_SYNC_MDC 7 8
2 2 2 IAC_SYNC GND3
<21> HDA_SDIN1 R231 1 2 33_0402_5%HDA_SDIN1_MDC 9 IAC_SDATA_IN GND4 10
+3VL 3 6 EC_SPICLK <21> HDA_RST#_MDC 11 12 HDA_BITCLK_MDC <21>
WP# SCLK SPI_CLK <31> IAC_RESET# IAC_BITCLK
1
4 5 R232
GND
GND
GND
GND
GND
GND
1 GND SI EC_SO_SPI_SI <31> +MDC_VCC 1
@
0_0603_5% 10_0402_5%
MX25L2005CMI-12G_SO8 +3VALW R81 1 2 @ ACES_88018-124G
13
14
15
16
17
18
2
1 1 1 2
0_0603_5% C404
+1.5VS @ R82 1 2 C405 C406 C407 Connector for MDC Rev1.5 @
R230 C403 1000P_0402_50V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z 10P_0402_50V8J
EC_SPICLK 1 2 2 2 1
2 10_0402_5% 1 2 10P_0402_50V8C
< LPC Debug Port >

Please place the PAD under DDR DIMM.
H50
+3VS 6 5
SERIRQ 7 4 PLT_RST#
<20,31> SERIRQ PLT_RST# <12,15,20,26,28,31,35>
LPC_AD3 8 3 LPC_AD2
<20,31> LPC_AD3 LPC_AD2 <20,31>
2 2
LPC_AD1 9 2 LPC_AD0
<20,31> LPC_AD1 LPC_AD0 <20,31>
LPC_FRAME# 10 1
<20,31> LPC_FRAME# CLK_PCI_SIO <20,24>
2
R234
@ DEBUG_PAD
22_0402_5%
1
2
C408
22P_0402_50V8J
1
KSI[0..7]
< KEYBOARD Conn > KSI[0..7] <31,33> < For EMI >
KSO[0..17]
KSO[0..17] <31,33>
JKB
300_0402_5% 1 2 R235 +3VS
34 KSO16 KSO16 C438 1
33 2 100P_0402_50V8J
KSO17 C439 1 2 100P_0402_50V8J
32 KSO17
3 31 3
30 KSO2 C409 100P_0402_50V8J
29 1 2
KSO2 KSO1 C410 1 2 100P_0402_50V8J
28 KSO1 KSO0 C411 100P_0402_50V8J
27 1 2
KSO0 KSO4 C412 1 2 100P_0402_50V8J
26 KSO4 KSO3 C413 100P_0402_50V8J
25 1 2
KSO3 KSO5 C414 1 2 100P_0402_50V8J
24 KSO5 KSO14 C418 100P_0402_50V8J
23 1 2
KSO14 KSO6 C419 1 2 100P_0402_50V8J
22 KSO6 KSO7 C420 100P_0402_50V8J
21 1 2
KSO7 KSO13 C421 1 2 100P_0402_50V8J
20 KSO13 KSO8 C422 100P_0402_50V8J
19 1 2
KSO8 KSO9 C423 1 2 100P_0402_50V8J
18 KSO9 KSO10 C424 100P_0402_50V8J
17 1 2
KSO10 KSO11 C425 1 2 100P_0402_50V8J
16 KSO11 KSO12 C426 100P_0402_50V8J
15 1 2
KSO12 KSO15 C427 1 2 100P_0402_50V8J
14 KSO15 KSI7 C428 100P_0402_50V8J
13 1 2
KSI7 KSI2 C429 1 2 100P_0402_50V8J
12 KSI2 KSI3 C430 100P_0402_50V8J
11 1 2
KSI3 KSI4 C431 1 2 100P_0402_50V8J
10 KSI4 KSI0 C432 100P_0402_50V8J
9 1 2
KSI0 KSI5 C433 1 2 100P_0402_50V8J
8 KSI5 KSI6 C434 100P_0402_50V8J
7 1 2
KSI6 KSI1 C435 1 2 100P_0402_50V8J
6 KSI1 CAPS_LED# C436 100P_0402_50V8J
5 1 2
300_0402_5% 2 1 R252 +3VS NUM_LED# C437 1 2 100P_0402_50V8J
4
3 CAPS_LED# <31>
2
1 NUM_LED# <31>
@ ACES_88170-3400
4 4

SCHEMATIC,MB A6052
A B C D E
A B C D E
< Power Button for Debug > < Power Button Circuit > < TP on & off BTN on M/B>
51_ON# <44>
SW1 Q17B
3
1 3 ON/OFFBTN# 2N7002KDW_SOT363-6 SW2
KSI6 1 3 KSO0
<31,32> KSI6 KSO0 <31,32>
2 4
<31> EC_ON 5 2 4
6 SMT1-05-A_4P
5
2
1 SMT1-05-A_4P 1
6
5
R786
10K_0402_5%
1
Sub-B Connector
JTPB
JLEDB 1 KSO0
@ P-TWO_161021-06021 1 KSI6
1 1 2 2
2 JPOWER 6 8 3
2 ON/OFFBTN# SW_R 6 G8 3
<31> LID_SW# 3 3 <31> ON/OFFBTN# 1 1 5 5 G7 7 4 4
ACIN_LED# 4 2 2 SW_L 4 5
4 4 GND
<31> PWR_ON_LED# 5 5 3 3 <31> TP_DATA 3 3 GND 6
<31> PWR_SUSP_LED# 6 6 4 4 <31> TP_CLK 2 2
2
HDD_LED# 7 D23 5 G1 1 @ P-TWO_161011-04021
7 +5VS 1
<27> CR_LED# 8 8 6 G2
9 JTOUCH
<31> BATT_FULL_LED# 9
10 ACES_85201-0405N @
2 <31> BATT_CHG_LOW_LED# 10 2
SW_L 11 17
SW_R 11 GND PACDN042Y3R_SOT23-3
12 18
1
12 GND
<31> WL_BT_LED# 13 13
+3VALW 14 D10
14
+5VS 15 15 2
+5VALW 16 16 1
3
@ ACES_85201-1605N
PACDN042Y3R_SOT23-3
LED Circuit
DC-IN LED HDD LED

SATA_LED# <22>
2
ACIN <22,31,44>
3 3
+3VS 2 R779 1 6 1
2
10K_0402_5%
5
Q31A
ACIN_LED# 6 1 2N7002KDW_SOT363-6
HDD_LED# 3 4
Q17A
2N7002KDW_SOT363-6 Q31B 2N7002KDW_SOT363-6
SCREW
H2 H3 H4 H5 H13 H14 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27
H_4P7 H_4P2 H_4P2X4P7 H_4P2X4P7 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_6P8 H_2P7X3P3N H_2P7N H_2P7X3P3N
1
1
4 @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ 4
H30 H31 H36 H37 H10 H12 H11

PCB Fedical Mark PAD
FD1 FD2 FD3 FD4
SCHEMATIC,MB A6052
H_3P3 H_3P3 H_3P3 H_3P3 H_2P9 H_2P9X3P4 H_3P2 @ @ @ @ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1
@ @ @ @ @ @ @ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401851 A
1
A B C D E
A B C D E
+1.5V +1.5VS
< +5VALW TO +5VS > < +1.5V TO +1.5VS > Q5
IRF8113PBF_SO8
Inrush current = 0A
8 1
+5VS 7 2 1 2
+5VALW +5VS 6 3 C462 C463
5
2
Q2 Inrush current = 0A 1 1U_0402_6.3V4Z 10U_0805_10V4Z
2
R250 C464 2 1
8 1
4
D S R305
7 D S 2 1 1
6 3 C449 C450 470_0805_5% 4.7U_0805_10V4Z
D S RUNON 2 R285 470_0805_5%
5 4
1
D G 1U_0402_6.3V4Z 4.7U_0805_10V4Z 1.5VS_ENABLE 750K_0402_1% +VSB
1 1 2
1
C452 SI4800BDY_SO8 2 2
1
1
3
1 4.7U_0805_10V4Z R286 C466 1
2 Q11B
SUSP 2N7002KDW_SOT363-6 10M_0402_5% 0.01U_0402_25V7K
5
Q34B 2 SUSP 2N7002KDW_SOT363-6
2 5
2
4
Q11A
4
2N7002KDW_SOT363-6
< +3VALW TO +3VS > < +1.1VALW TO +1.1VS > BOOT_ON_1.1V @R62
@ R62 2 1 0_0402_5% SUSP
+1.1VALW
+3VALW +3VS +1.1VS BOOT_ON_1.1V R63 2 1 0_0402_5% VLDT_EN#
Q6
Q3 IRF8113PBF_SO8 BOOT_ON_1.1V @R67
@ R67 2 1 0_0402_5% VGATE#
Inrush current = 0A Inrush current = 0A
8 D S 1 8 1 1
7 D S 2 1 1 7 2 1 1
6 3 C468 C469 6 3 C471 C472 + C158
D S
2
5 D G 4 5
1 1U_0402_6.3V4Z 4.7U_0805_10V4Z R251 1U_0402_6.3V4Z 4.7U_0805_10V4Z 330U_B2_2.5VM_R15M
C470 SI4800BDY_SO8 2 2 2 2 2
2
R287 470_0805_5% 1
4.7U_0805_10V4Z RUNON 2 1 750K_0402_1% +VSB C475 R300
1
2 R290
4.7U_0805_10V4Z 2 1 330K_0402_5% +VSB 470_0805_5%
6
3
2
3 1
1
1 Q14B 1
6
C474 R291 C476
2 SUSP 5 2N7002KDW_SOT363-6 Q12B
0.01U_0402_25V7K 10M_0402_5% 0.01U_0402_25V7K
2 Q14A 2 BOOT_ON_1.1V 2N7002KDW_SOT363-6
2 5
1
2
2 2N7002KDW_SOT363-6 2
Q12A
4
2N7002KDW_SOT363-6
< +1.1VALW TO +NB_CORE > < Inversion of SYSON, SUSP#, VLDT_EN, EC_ON >
+1.1VALW
+NB_CORE
Q7
IRF8113PBF_SO8 +5VALW +5VALW
Inrush current = 0A +5VALW
8 1
7 2 1 1
1
6 3 C479 C478
1
5 R814 R245
1U_0402_6.3V4Z 4.7U_0805_10V4Z
2 2 100K_0402_5% 100K_0402_5% R816
4
1 100K_0402_5%
2
C480 R306
2
R292 SYSON# SUSP
SUSP <49>
4.7U_0805_10V4Z 2 1 330K_0402_5% +VSB 470_0805_5% VLDT_EN#
2
3 1
1
6
1
6
R293 C481 Q15B Q15A

Q13B 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
10M_0402_5% 0.01U_0402_25V7K 5 2 VLDT_EN 2
2 <31,48> SYSON SUSP# <28,31,46,49,51> <31> VLDT_EN
2 BOOT_ON_NB 5 2N7002KDW_SOT363-6 Q16A
2
2N7002KDW_SOT363-6
1
Q13A
1
2N7002KDW_SOT363-6
3 3
< Discharge circuit >

BOOT_ON_NB @ R45 2 1 0_0402_5% SUSP
BOOT_ON_NB R46 2 1 0_0402_5% VLDT_EN#
BOOT_ON_NB @ R47 2 1 0_0402_5% VGATE#
+5VALW +5VALW
+1.5V +0.75VS +1.8VS

1
R802 R803
2
2
2
100K_0402_5% 100K_0402_5% R253
R257 R258
2
470_0805_5%
VGATE# VR_ON# 470_0805_5% 470_0805_5%
VR_ON# <49>
1
1
1
3
1
Q35B D D D
2N7002KDW_SOT363-6 Q35A SYSON#2 Q9 SUSP 2 Q10 SUSP 2 Q23
5 2N7002KDW_SOT363-6 G G G
<31,50> VGATE
2 S 2N7002_SOT23-3 S 2N7002_SOT23-3 S 2N7002_SOT23-3
VR_ON <31,50>
3
3
4
4 4

SCHEMATIC,MB A6052
A B C D E
5 4 3 2 1
PCIE_GTX_C_MRX_P[0..15]
<11> PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15] UV1A
<11> PCIE_GTX_C_MRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15] Close to UV1

<11> PCIE_MTX_C_GRX_P[0..15]
D D
PCIE_MTX_C_GRX_N[0..15]
<11> PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_N15 AA38 Y33 PCIE_GTX_MRX_N15 CV1 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P15
PCIE_MTX_C_GRX_P15 PCIE_RX0P PCIE_TX0P PCIE_GTX_MRX_P15 CV2
Y37 PCIE_RX0N PCIE_TX0N Y32 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N15
PCIE_MTX_C_GRX_N14 Y35 W33 PCIE_GTX_MRX_N14 CV3 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P14

W36 PCIE_RX1N PCIE_TX1N W32 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N14
PCIE_MTX_C_GRX_N13 W38 U33 PCIE_GTX_MRX_N13 CV5 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P13

V37 PCIE_RX2N PCIE_TX2N U32 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N13
PCIE_MTX_C_GRX_N12 V35 U30 PCIE_GTX_MRX_N12 CV7 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P12

U36 PCIE_RX3N PCIE_TX3N U29 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N12
PCIE_MTX_C_GRX_N11 U38 T33 PCIE_GTX_MRX_N11 CV9 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P11

PCIE_MTX_C_GRX_P11 PCIE_RX4P PCIE_TX4P PCIE_GTX_MRX_P11 CV10 1
T37 PCIE_RX4N PCIE_TX4N T32 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N11
PCI EXPRESS INTERFACE

PCIE_MTX_C_GRX_N10 T35 T30 PCIE_GTX_MRX_N10 CV11 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P10
R36 PCIE_RX5N PCIE_TX5N T29 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N10
PCIE_MTX_C_GRX_N9 R38 P33 PCIE_GTX_MRX_N9 CV13 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P9

P37 PCIE_RX6N PCIE_TX6N P32 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N9
C C
PCIE_MTX_C_GRX_N8 P35 P30 PCIE_GTX_MRX_N8 CV15 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P8
N36 PCIE_RX7N PCIE_TX7N P29 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N8
PCIE_MTX_C_GRX_N7 N38 N33 PCIE_GTX_MRX_N7 CV17 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P7

M37 PCIE_RX8N PCIE_TX8N N32 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N7
PCIE_MTX_C_GRX_N6 M35 N30 PCIE_GTX_MRX_N6 CV19 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P6

L36 PCIE_RX9N PCIE_TX9N N29 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N6
PCIE_MTX_C_GRX_N5 L38 L33 PCIE_GTX_MRX_N5 CV21 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P5

K37 PCIE_RX10N PCIE_TX10N L32 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N5
PCIE_MTX_C_GRX_N4 K35 L30 PCIE_GTX_MRX_N4 CV23 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P4

J36 PCIE_RX11N PCIE_TX11N L29 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N4
PCIE_MTX_C_GRX_N3 J38 K33 PCIE_GTX_MRX_N3 CV25 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P3

H37 PCIE_RX12N PCIE_TX12N K32 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N3
PCIE_MTX_C_GRX_N2 H35 J33 PCIE_GTX_MRX_N2 CV27 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P2

G36 PCIE_RX13N PCIE_TX13N J32 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N2
B PCIE_MTX_C_GRX_N1 PCIE_GTX_MRX_N1 CV29 1 B

G38 PCIE_RX14P PCIE_TX14P K30 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P1
PCIE_MTX_C_GRX_P1 F37 K29 PCIE_GTX_MRX_P1 CV30 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N1
PCIE_RX14N PCIE_TX14N
PCIE_MTX_C_GRX_N0 F35 H33 PCIE_GTX_MRX_N0 CV31 1 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_P0

E37 PCIE_RX15N PCIE_TX15N H32 2 0.1U_0402_10V7K PCIE_GTX_C_MRX_N0
CLOCK
<16> CLK_PCIE_VGA AB35 PCIE_REFCLKP
<16> CLK_PCIE_VGA# AA36 PCIE_REFCLKN
CALIBRATION
AJ21 Y30 RV1 1 2 1.27K_0402_1%
MANHA@ NC#1 PCIE_CALRP
AK21 NC#2
RV133 1 2 10K_0402_5% AH16 Y29 RV2 1 2 2K_0402_1% +1.0VS
NC_PWRGOOD PCIE_CALRN
<12,15,20,26,28,31,32> PLT_RST# AA30 PERSTB
216-0729002 A12 M96_BGA962
A A

SCHEMATIC,MB A6052
5 4 3 2 1
5 4 3 2 1
UV1B
UV1G
TXCAP_DPA3P AU24
AV23 LVDS CONTROL AK27
TXCAM_DPA3N VARY_BL VGA_INVT_PWM <18>
DIGON AJ27 VGA_ENVDD <18>
TX0P_DPA2P AT25
MUTI GFX AR24
DPA TX0M_DPA2N
TX1P_DPA1P AU26
+3VS_DELAY AV25 AK35
TX1M_DPA1N TXCLK_UP_DPF3P LCD_TZCLK+ <18>
TXCLK_UN_DPF3N AL36 LCD_TZCLK- <18>
AR8 DVPCNTL_MVP_0 TX2P_DPA0P AT27
10K_0402_5% 2 1 RV30 @ VGA_PWRSEL0 AU8 DVPCNTL_MVP_1 TX2M_DPA0N AR26 TXOUT_U0P_DPF2P AJ38 LCD_TZOUT0+ <18>
AP8 DVPCNTL_0 TXOUT_U0N_DPF2N AK37 LCD_TZOUT0- <18>
10K_0402_5% 2 1 RV131 @ VGA_PWRSEL1 AW8 DVPCNTL_1 TXCBP_DPB3P AR30 HDMI_CLK0+ <19>
AR3 DVPCNTL_2 TXCBM_DPB3N AT29 HDMI_CLK0- <19> TXOUT_U1P_DPF1P AH35 LCD_TZOUT1+ <18>
10K_0402_5% 2 1 RV32 THERM#_VGA AR1 AJ36 LCD_TZOUT1- <18>
D DVPCLK TXOUT_U1N_DPF1N D
<43> VRAM_ID0 AU1 DVPDATA_0 TX3P_DPB2P AV31 HDMI_TXD0+ <19>
10K_0402_5% 2 1 RV33 M9X@ GPIO23_CLKREQ# <43> VRAM_ID1 AU3 DVPDATA_1 TX3M_DPB2N AU30 HDMI_TXD0- <19> TXOUT_U2P_DPF0P AG38 LCD_TZOUT2+ <18>
AW3 DPB AH37 LCD_TZOUT2- <18>
<43> VRAM_ID2 DVPDATA_2 TXOUT_U2N_DPF0N
10K_0402_5% 2 1 RV34 @ R_AC_IN AP6 AR32 HDMI_TXD1+ <19>
DVPDATA_3 TX4P_DPB1P
AW5 DVPDATA_4 TX4M_DPB1N AT31 HDMI_TXD1- <19> TXOUT_U3P AF35
10K_0402_5% 2 1 RV35 @ GENERIC_C AU5 AG36
DVPDATA_5 TXOUT_U3N
AR6 DVPDATA_6 TX5P_DPB0P AT33 HDMI_TXD2+ <19>
AW6 DVPDATA_7 TX5M_DPB0N AU32 HDMI_TXD2- <19>
AU6 LVTMDP
DVPDATA_8
AT7 DVPDATA_9 TXCCP_DPC3P AU14
AV7 DVPDATA_10 TXCCM_DPC3N AV13 TXCLK_LP_DPE3P AP34 LCD_TXCLK+ <18>
10K_0402_5% 1 2 RV17 ENBKL AN7 AR34 LCD_TXCLK- <18>
DVPDATA_11 TXCLK_LN_DPE3N
AV9 DVPDATA_12 TX0P_DPC2P AT15
AT9 DVPDATA_13 TX0M_DPC2N AR14 TXOUT_L0P_DPE2P AW37 LCD_TXOUT0+ <18>
AR10 DVPDATA_14 TXOUT_L0N_DPE2N AU35 LCD_TXOUT0- <18>
AW10 DPC AU16
DVPDATA_15 TX1P_DPC1P
AU10 DVPDATA_16 TX1M_DPC1N AV15 TXOUT_L1P_DPE1P AR37 LCD_TXOUT1+ <18>
AP10 DVPDATA_17 TXOUT_L1N_DPE1N AU39 LCD_TXOUT1- <18>
AV11 DVPDATA_18 TX2P_DPC0P AT17
AT11 DVPDATA_19 TX2M_DPC0N AR16 TXOUT_L2P_DPE0P AP35 LCD_TXOUT2+ <18>
AR12 DVPDATA_20 TXOUT_L2N_DPE0N AR35 LCD_TXOUT2- <18>
AW12 DVPDATA_21 TXCDP_DPD3P AU20
AU12 DVPDATA_22 TXCDM_DPD3N AT19 TXOUT_L3P AN36
AP12 DVPDATA_23 TXOUT_L3N AP37
TX3P_DPD2P AT21
TX3M_DPD2N AR20
DPD AU22
TX4P_DPD1P
TX4M_DPD1N AV21
216-0729002 A12 M96_BGA962
I2C AT23
TX5P_DPD0P
TX5M_DPD0N AR22 @
LCD_EDID_CLK
LCD <18> LCD_EDID_CLK
<18> LCD_EDID_DATA LCD_EDID_DATA
AK26
AJ26
SCL
SDA
AD39 Near UV1
GENERAL PURPOSE I/O R RED <17>
RB AD37
C GPU_GPIO0 AH20 C
<43> GPU_GPIO0 GPIO_0
GPU_GPIO1 AH18 AE36 RED 1 2
<43> GPU_GPIO1 GPIO_1 G GREEN <17>
GPU_GPIO2 AN16 AD35 RV11 150_0402_1%
<43> GPU_GPIO2 GPIO_2 GB
AH23 GREEN 1 2
GPIO_3_SMBDATA RV12 150_0402_1%
AJ23 GPIO_4_SMBCLK B AF37 BLUE <17>
R_AC_IN AH17 AE38 BLUE 1 2
GPIO_5_AC_BATT DAC1 BB RV13 150_0402_1%
AJ17 GPIO_6
<31> ENBKL
SOUT_GPIO8
AK17
AJ13
GPIO_7_BLON HSYNC AC36
AC38
R_HSYNC <17,43> CRT
<43> SOUT_GPIO8 GPIO_8_ROMSO VSYNC R_VSYNC <17,43>
SIN_GPIO9 AH15
<43> SIN_GPIO9 GPIO_9_ROMSI
AJ16 GPIO_10_ROMSCK
GPU_GPIO11 AK16 AB34 1 2
<43> GPU_GPIO11 GPIO_11 RSET
GPU_GPIO12 AL16 RV18 499_0402_1%
<43> GPU_GPIO12 GPIO_12
GPU_GPIO13 AM16 AD34 +AVDD_VGA
<43> GPU_GPIO13 GPIO_13 AVDD
AM14 AE34 BLM18PG121SN1D_0603
VGA_PWRSEL0
T15 PAD
AM13
GPIO_14_HPD2 AVSSQ +AVDD_VGA 70mA 2 1 +1.8VS
<51> VGA_PWRSEL0 GPIO_15_PWRCNTL_0
27M_SSC AK14 AC33 +VDD1DI 1 1 1 LV1
<16> 27M_SSC GPIO_16_SSIN VDD1DI
THERM#_VGA AG30 AC34
<43> THERM#_VGA GPIO_17_THERMAL_INT VSS1DI
AN14 CV33 CV35 CV34
+1.8VS GPIO_18_HPD3 1U_0402_6.3V4Z 10U_0603_6.3V6M
AM17 GPIO_19_CTF
VGA_PWRSEL1 2 2 2
<51> VGA_PWRSEL1 AL13 GPIO_20_PWRCNTL_1 R2 AC30
AJ14 AC31 0.1U_0402_16V4Z
GPIO_21_BB_EN R2B
1
RV20 ROMSE_GPIO22 AK13

<43> ROMSE_GPIO22 GPIO_22_ROMCSB
499_0402_1% GPIO23_CLKREQ# AN13 AD30
GPIO_23_CLKREQB G2
AM23 JTAG_TRSTB G2B AD31
T9 PAD AN23 JTAG_TDI
AK23 AF30 BLM18PG121SN1D_0603
45mA
2
JTAG_TCK B2 +VDD1DI
AL24 JTAG_TMS B2B AF31 2 1 +1.8VS
+VGA_VREF AM24 1 1 1 LV2
T10 PAD JTAG_TDO
AJ19 GENERICA
1
AK19 AC32 CV36 CV37 CV38

RV21 GENERIC_C GENERICB C 1U_0402_6.3V4Z 10U_0603_6.3V6M
1 AJ20 GENERICC Y AD32
249_0402_1% CV49 2 2 2
AK20 GENERICD COMP AF32
AJ24 0.1U_0402_16V4Z
0.1U_0402_16V4Z GENERICE_HPD4 DAC2
AH26
2
2 GENERICF
AH24 GENERICG H2SYNC AD29 HSYNC_DAC2 <43>
V2SYNC AC29 VSYNC_DAC2 <43>
B B
<19> HPD AK24 HPD1 45mA
AG31 +VDD1DI +A2VDD 1 2 +3VS_DELAY
VDD2DI LV4 0_0603_5%
VSS2DI AG32
AG33 +A2VDD
A2VDD
AD33 +A2VDDQ
+VGA_VREF AH13 A2VDDQ BLM18PG121SN1D_0603
VREFG
AF33 +A2VDDQ 10mA 2 1 +1.8VS
A2VSSQ LV6
1 1 1
AA29 1 2 10U_0603_6.3V6M CV46 CV47 CV48

R2SET RV22 715_0402_1% 1U_0402_6.3V4Z
BLM18PG121SN1D_0603 2 2 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z +DPLL_PVDD DDC/AUX CRT_CLK
+1.8VS 2
LV3
1
1 1 1
150mA PLL/CLOCK DDC1CLK AM26
AN26 CRT_DATA
CRT_CLK <17>
CRT_DATA <17>
CRT
CV42 +DPLL_PVDD DDC1DATA
AM32 DPLL_PVDD
CV41 1U_0402_6.3V4Z AN32 AM27
CV40 DPLL_PVSS AUX1P
300mA AUX1N AL27
2 2 2
10U_0603_6.3V6M +DPLL_VDDC HDMICLK_VGA
AN31 DPLL_VDDC DDC2CLK AM19
AL19 HDMIDAT_VGA
HDMICLK_VGA <19>
HDMIDAT_VGA <19>
HDMI
DDC2DATA
<16> 27M_CLK
RV26 1 2 47.5_0402_1% XTALIN AV33 XTALIN AUX2P AN20
1
AU34 XTALOUT AUX2N AM20

RV31
+1.0VS BLM18PG121SN1D_0603 100_0402_1% AL30
0.1U_0402_16V4Z +DPLL_VDDC DDCCLK_AUX3P
2 1 DDCDATA_AUX3N AM30
LV5 1 1 1
2
CV43 AL29
CV44 CV45 DDCCLK_AUX4P
<43> GPU_THERMAL_D+ AF29 DPLUS DDCDATA_AUX4N AM29
AG29 THERMAL
2 2 2 1U_0402_6.3V4Z <43> GPU_THERMAL_D- DMINUS
DDCCLK_AUX5P AN21
10U_0603_6.3V6M AM21
20mA AK32
DDCDATA_AUX5N
+TSVDD TS_FDO
A AJ32 TSVDD DDC6CLK AJ30 A
AJ33 TSVSS DDC6DATA AJ31
NC_DDCCLK_AUX7P AK30
BLM18PG121SN1D_0603 AK29
NC_DDCDATA_AUX7N
+1.8VS 2 1 0.1U_0402_16V4Z +TSVDD

LV7 1 1 1
CV52
CV51 1U_0402_6.3V4Z 216-0729002 A12 M96_BGA962
CV50
2
10U_0603_6.3V6M
2 2
@
SCHEMATIC,MB A6052
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 401851 A
5 4 3 2 1
5 4 3 2 1
MANHA@
BLM18PG121SN1D_0603
MANHA@ +DPA_VDD18 1 2 +1.8VS
BLM18PG121SN1D_0603 LV35
+1.8VS 2 1 +DPC_VDD18 2 2 2
10U_0603_6.3V6M
LV33 MANHA@
1U_0402_6.3V4Z
0.1U_0402_16V4Z
2 2 2 UV1H CV316 CV315 CV314 10U_0603_6.3V6M
MANHA@ MANHA@
CV309 CV308 CV310 DP C/D POWER DP A/B POWER 1 1 1
D D
MANHA@ MANHA@ MANHA@ 1U_0402_6.3V4Z
1 1 1 +DPC_VDD18 +DPA_VDD18 0.1U_0402_16V4Z
AP20 NC_DPC_VDD18#1 NC_DPA_VDD18#1 AN24
AP21 NC_DPC_VDD18#2 NC_DPA_VDD18#2 AP24
200mA
+1.0VS 1 2 +DPC_VDD10 AP13 AP31 +DPA_VDD10 1 2 +1.0VS
LV8 0_0603_5% DPC_VDD10#1 DPA_VDD10#1 LV9 0_0603_5% MANHA@
AT13 DPC_VDD10#2 DPA_VDD10#2 AP32
BLM18PG121SN1D_0603
+DPB_VDD18 1 2 +1.8VS
10U_0603_6.3V6M
LV36
0.1U_0402_16V4Z
AN17 DPC_VSSR#1 DPA_VSSR#1 AN27
1U_0402_6.3V4Z
AP16 DPC_VSSR#2 DPA_VSSR#2 AP27 2 2 2
MANHA@ AP17 AP28
BLM18PG121SN1D_0603 DPC_VSSR#3 DPA_VSSR#3 CV319 CV317 CV318
AW14 DPC_VSSR#4 DPA_VSSR#4 AW24
+1.8VS 2 1 +DPD_VDD18 AW16 AW26 MANHA@ MANHA@ MANHA@
LV34 DPC_VSSR#5 DPA_VSSR#5 1 1 1
1U_0402_6.3V4Z
0.1U_0402_16V4Z
10U_0603_6.3V6M
2 2 2
CV312 CV311 CV313 +DPD_VDD18 AP22 AP25 +DPB_VDD18
MANHA@ MANHA@ MANHA@ NC_DPD_VDD18#1 NC_DPB_VDD18#1
AP23 NC_DPD_VDD18#2 NC_DPB_VDD18#2 AP26
1 1 1
BLM18PG121SN1D_0603
+1.0VS 1 2 +DPD_VDD10 AP14 AN33 +DPB_VDD10 20mA 2 1 +1.0VS
LV10 0_0603_5% DPD_VDD10#1 DPB_VDD10#1 LV11
AP15 DPD_VDD10#2 DPB_VDD10#2 AP33 2 2 2
H@
10U_0603_6.3V6M CV53 CV54 CV55
0.1U_0402_16V4Z
1 1 1 H@
AN19 DPD_VSSR#1 DPB_VSSR#1 AN29
AP18 DPD_VSSR#2 DPB_VSSR#2 AP29
C AP19 AP30 1U_0402_6.3V4Z C
DPD_VSSR#3 DPB_VSSR#3 H@
AW20 DPD_VSSR#4 DPB_VSSR#4 AW30
AW22 DPD_VSSR#5 DPB_VSSR#5 AW32
BLM18PG121SN1D_0603
+1.8VS 2 1 +DPE_VDD18 RV36 150_0402_1%
LV12 2 2 2 2 1 AW18 AW28 1 2
DPCD_CALR DPAB_CALR RV37 150_0402_1%
10U_0603_6.3V6M CV56 CV57 CV58
200mA
1 1 1 +DPE_VDD18 AH34
DP E/F POWER DP PLL POWER
AU28 +DPA_PVDD +DPA_PVDD 20mA 1 2 +1.8VS
1U_0402_6.3V4Z DPE_VDD18#1 DPA_PVDD LV13 0_0603_5%
AJ34 DPE_VDD18#2 DPA_PVSS AV27
0.1U_0402_16V4Z
100mA
+DPE_VDD10 AL33 AV29 +DPB_PVDD
DPE_VDD10#1 DPB_PVDD
AM33 DPE_VDD10#2 DPB_PVSS AR28
BLM18PG121SN1D_0603
2 1 +DPE_VDD10 AN34 AU18 +DPC_PVDD BLM18PG121SN1D_0603
+1.0VS
LV15 2 2 2 AP39
DPE_VSSR#1 DPC_PVDD
AV17 +DPB_PVDD 20mA 2 1 +1.8VS
DPE_VSSR#2 DPC_PVSS LV14
AR39 DPE_VSSR#3 2 2 2
10U_0603_6.3V6M CV60 CV64 CV61 AU37 DPE_VSSR#4 10U_0603_6.3V6M CV59 CV62 CV63
AW35 DPE_VSSR#5
1 1 1 +DPD_PVDD 0.1U_0402_16V4Z
DPD_PVDD AV19
1U_0402_6.3V4Z 1 1 1
200mA DPD_PVSS AR18
0.1U_0402_16V4Z
+DPF_VDD18 AF34 1U_0402_6.3V4Z
DPF_VDD18#1
AG34 DPF_VDD18#2
AM37 +DPE_PVDD
B DPE_PVDD B
100mA DPE_PVSS AN38 20mA
+DPC_PVDD 1 2 +1.8VS
+DPF_VDD10 AK33 LV16 0_0603_5%
BLM18PG121SN1D_0603 DPF_VDD10#1
AK34 DPF_VDD10#2
+1.8VS 2 1 +DPF_VDD18 AL38
LV17 NC_DPF_PVDD
2 2 2 NC_DPF_PVSS AM35
10U_0603_6.3V6M CV65 CV66 CV67 AF39 DPF_VSSR#1

AH39 DPF_VSSR#2
1 1 1
AK39 DPF_VSSR#3
1U_0402_6.3V4Z AL34
0.1U_0402_16V4Z DPF_VSSR#4
AM34 DPF_VSSR#5 20mA
+DPD_PVDD 1 2 +1.8VS
LV18 0_0603_5%
RV38 150_0402_1%
2 1 AM39 DPEF_CALR
216-0729002 A12 M96_BGA962
BLM18PG121SN1D_0603 @
+1.0VS 2 1 +DPF_VDD10
LV19 BLM18PG121SN1D_0603
2 2 2
+DPE_PVDD 20mA 2 1 +1.8VS
10U_0603_6.3V6M CV68 CV69 CV70 1 1 1 LV20
1 1 1 0.1U_0402_16V4Z CV71 CV72 CV73
1U_0402_6.3V4Z 10U_0603_6.3V6M
0.1U_0402_16V4Z 2 2 2
1U_0402_6.3V4Z
A A

SCHEMATIC,MB A6052
5 4 3 2 1
5 4 3 2 1
UV1E
+1.5VS +PCIE_VDDR_VGA
MEM I/O
PCIE 500mA
4A AC7 AA31 1 2 +1.8VS
VDDR1#1 PCIE_VDDR#1 LV21 BLM18PG121SN1D_0603
AD11 VDDR1#2 PCIE_VDDR#2 AA32
1 1 2 1 2 1 2 AF7 VDDR1#3 PCIE_VDDR#3 AA33 1 2
CV74 10U_0603_6.3V6M CV75 1U_0402_6.3V4Z CV76 1U_0402_6.3V4Z AG10 AA34 CV77 10U_0603_6.3V6M
+ CV78 VDDR1#4 PCIE_VDDR#4
1 2 1 2 1 2 AJ7 VDDR1#5 PCIE_VDDR#5 V28 1 2
330U_X_2VM_R6M CV79 10U_0603_6.3V6M CV80 1U_0402_6.3V4Z CV81 1U_0402_6.3V4Z AK8 W29 CV82 1U_0402_6.3V4Z
VDDR1#6 PCIE_VDDR#6
1 2 1 2 1 2 AL9 VDDR1#7 PCIE_VDDR#7 W30 1 2
2 CV83 10U_0603_6.3V6M CV84 1U_0402_6.3V4Z CV85 1U_0402_6.3V4Z CV86 1U_0402_6.3V4Z
G11 VDDR1#8 PCIE_VDDR#8 Y31
1 2 1 2 1 2 G14 VDDR1#9 1 2
D @ CV87 10U_0603_6.3V6M CV88 1U_0402_6.3V4Z CV89 1U_0402_6.3V4Z G17 CV90 1U_0402_6.3V4Z D
VDDR1#10
1 2 1 2 1 2 G20 VDDR1#11 PCIE_VDDC#1 G30 1 2
CV91 10U_0603_6.3V6M CV92 1U_0402_6.3V4Z CV93 1U_0402_6.3V4Z G23 G31 CV94 1U_0402_6.3V4Z
1 2 1 2 G26
VDDR1#12 PCIE_VDDC#2
H29
2A +1.0VS 1 2
CV95 1U_0402_6.3V4Z CV96 1U_0402_6.3V4Z VDDR1#13 PCIE_VDDC#3 CV97 1U_0402_6.3V4Z
G29 VDDR1#14 PCIE_VDDC#4 H30
1 2 1 2 H10 VDDR1#15 PCIE_VDDC#5 J29 1 2 1 2
CV98 1U_0402_6.3V4Z CV99 1U_0402_6.3V4Z J7 J30 CV100 10U_0603_6.3V6M CV101 0.1U_0402_16V4Z
1 2 1 2 J9 VDDR1#17 PCIE_VDDC#7 L28 1 2 1 2
+1.5VS CV102 1U_0402_6.3V4Z CV103 1U_0402_6.3V4Z K11 M28 CV104 1U_0402_6.3V4Z CV105 0.1U_0402_16V4Z
1 2 1 2 K13 VDDR1#19 PCIE_VDDC#9 N28 1 2
CV106 1U_0402_6.3V4Z CV107 1U_0402_6.3V4Z K8 R28 CV108 1U_0402_6.3V4Z
1
1 2 1 2 L12
T28 1 2
25A +VGA_CORE
CV192 + CV109 1U_0402_6.3V4Z CV110 1U_0402_6.3V4Z VDDR1#21 PCIE_VDDC#11 CV111 1U_0402_6.3V4Z
L16 VDDR1#22 PCIE_VDDC#12 U28
330U_X_2VM_R6M
330U_X_2VM_R6M
390U_2.5V_M_R10
390U_2.5V_M_R10
L21 VDDR1#23 1 2 1 1 1 1
390U_2.5V_M_R10 L23 CV112 1U_0402_6.3V4Z
2 VDDR1#24 + @ + + @ +
L26 VDDR1#25 VDDC#1 AA15 1 2
L7 CORE AA17 CV113 1U_0402_6.3V4Z CV116 CV324 CV114 CV323
VDDR1#26 VDDC#2
M11 VDDR1#27 VDDC#3 AA20 1 2
CV115 1U_0402_6.3V4Z 2 2 2 2
N11 VDDR1#28 VDDC#4 AA22
P7 VDDR1#29 VDDC#5 AA24 1 2
R11 AA27 CV118 1U_0402_6.3V4Z
VDDR1#30 VDDC#6
U11 VDDR1#31 VDDC#7 AB13
U7 VDDR1#32 VDDC#8 AB16
Y11 VDDR1#33 VDDC#9 AB18 1 2 1 2 1 2
Y7 AB21 CV120 10U_0603_6.3V6M CV121 1U_0402_6.3V4Z CV122 1U_0402_6.3V4Z
VDDR1#34 VDDC#10
VDDC#11 AB23 1 2 1 2 1 2
AB26 CV124 10U_0603_6.3V6M CV125 1U_0402_6.3V4Z CV126 1U_0402_6.3V4Z
VDDC#12
VDDC#13 AB28 1 2 1 2 1 2
AC12 CV128 10U_0603_6.3V6M CV129 1U_0402_6.3V4Z CV130 1U_0402_6.3V4Z
BLM18PG121SN1D_0603 LEVEL VDDC#14
136mA VDDC#15 AC15 1 2 1 2 1 2
10U_0603_6.3V6M
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
TRANSLATION AC17 CV132 10U_0603_6.3V6M CV133 1U_0402_6.3V4Z CV134 1U_0402_6.3V4Z
+1.8VS VDDC#16
POWER
C 2 1 2 2 2 1 2 +VDD_CT AF26 AC20 1 2 1 2 1 2 C
LV22 VDD_CT#1 VDDC#17 CV136 10U_0603_6.3V6M CV137 1U_0402_6.3V4Z CV138 1U_0402_6.3V4Z
AF27 VDD_CT#2 VDDC#18 AC22
CV119 CV123 CV127 CV131 CV135 AG26 AC24 1 2 1 2 1 2
VDD_CT#3 VDDC#19 CV139 10U_0603_6.3V6M CV140 1U_0402_6.3V4Z CV141 1U_0402_6.3V4Z
1U_0402_6.3V4Z AG27 VDD_CT#4 VDDC#20 AC27
1 1 1 2 1
VDDC#21 AD13 1 2 1 2 1 2
AD16 CV142 10U_0603_6.3V6M CV143 1U_0402_6.3V4Z CV144 1U_0402_6.3V4Z
I/O VDDC#22
60mA VDDC#23 AD18 1 2 1 2 1 2
+3VS_DELAY AF23 AD21 CV145 1U_0402_6.3V4Z CV146 1U_0402_6.3V4Z CV147 1U_0402_6.3V4Z
VDDR3#1 VDDC#24
1 2 AF24 VDDR3#2 VDDC#25 AD23 1 2 1 2 1 2
CV148 10U_0603_6.3V6M AG23 AD26 CV149 1U_0402_6.3V4Z CV150 1U_0402_6.3V4Z CV151 1U_0402_6.3V4Z
VDDR3#3 VDDC#26
1 2 AG24 VDDR3#4 VDDC#27 AF17 1 2 1 2 1 2
BLM18PG121SN1D_0603 CV152 1U_0402_6.3V4Z AF20 CV153 1U_0402_6.3V4Z CV154 1U_0402_6.3V4Z CV155 1U_0402_6.3V4Z
0.1U_0402_16V4Z +VDDR5 VDDC#28
+1.8VS 2 1 1 2 VDDC#29 AF22 1 2 1 2
LV23 CV158 1U_0402_6.3V4Z AF13 AG16 CV159 1U_0402_6.3V4Z CV160 1U_0402_6.3V4Z
1 1
CV156 CV157
1
CV161 1 2
170mA AF15
VDDR5#1 VDDC#30
AG18 1 2 1 2
CV162 1U_0402_6.3V4Z +VDDR5 VDDR5#2 VDDC#31 CV163 1U_0402_6.3V4Z CV164 1U_0402_6.3V4Z
AG13 VDDR5#3 VDDC#32 AG21
10U_0603_6.3V6M 1U_0402_6.3V4Z AG15 AH22 1 2 1 2
2 2 2 VDDR5#4 VDDC#33 CV165 1U_0402_6.3V4Z CV166 1U_0402_6.3V4Z
VDDC#34 M16
170mA VDDC#35 M18 1 2 1 2
AD12 M23 CV167 1U_0402_6.3V4Z CV168 1U_0402_6.3V4Z
+VDDR4 VDDR4#1 VDDC#36
AF11 VDDR4#2 VDDC#37 M26 1 2 1 2
AF12 N15 CV169 1U_0402_6.3V4Z CV170 1U_0402_6.3V4Z
VDDR4#3 VDDC#38
AG11 VDDR4#4 VDDC#39 N17 1 2 1 2
N20 CV174 1U_0402_6.3V4Z CV175 1U_0402_6.3V4Z
VDDC#40
VDDC#41 N22 1 2 1 2
BLM18PG121SN1D_0603 N24 CV176 1U_0402_6.3V4Z CV177 1U_0402_6.3V4Z
0.1U_0402_16V4Z +VDDR4 BLM18PG121SN1D_0603 MEM CLK VDDC#42
+1.8VS 2 1 VDDC#43 N27 1 2 1 2
LV24 1 1 1 +1.5VS 2 1 +VDDRHA M20 R13 CV178 1U_0402_6.3V4Z CV179 1U_0402_6.3V4Z
CV171 CV172 CV173 M9X@ LV25 VDDRHA VDDC#44
M21 VSSRHA VDDC#45 R16 1 2 1 2
R18 CV181 1U_0402_6.3V4Z CV182 1U_0402_6.3V4Z
10U_0603_6.3V6M 1U_0402_6.3V4Z VDDC#46
VDDC#47 R21 1 2 1 2
B 2 2 2 +VDDRHB CV183 1U_0402_6.3V4Z CV184 1U_0402_6.3V4Z B
V12 VDDRHB VDDC#48 R23
U12 VSSRHB VDDC#49 R26
Reserve VDDC#50 T15
VDDC#51 T17
VDDC#52 T20
VDDC#53 T22
BLM18PG121SN1D_0603 PLL T24
+1.8VS 2 1 0.1U_0402_16V4Z 68mA +PCIE_PVDD AB37
VDDC#54
T27
LV27 PCIE_PVDD VDDC#55
1 1 1 VDDC#56 U16
CV186 CV187 CV188 MPV18 H7 U18
MPV18 NC_MPV18#1 VDDC#57
H8 NC_MPV18#2 VDDC#58 U21
10U_0603_6.3V6M 1U_0402_6.3V4Z U23
2 2 2 VDDC#59
VDDC#60 U26
SPV18 AM10 V15
MANHA@ 1U_0402_6.3V4Z NC_SPV18 VDDC#61
414mA VDDC#62 V17
+1.0VS 2 1 +SPV10 AN9 V20
LV28 SPV10 VDDC#63
1 1 2 VDDC#64 V22
CV189 CV190 CV191 AN10 V24
BLM18PG121SN1D_0603 SPVSS VDDC#65
VDDC#66 V27
MANHA@ Y16
2 2 1 VDDC#67
VDDC#68 Y18
BLM18PG121SN1D_0603 10U_0603_6.3V6M 0.1U_0402_16V4Z Y21
0.1U_0402_16V4Z MPV18 M9X@ BACK BIAS VDDC#69
+1.8VS 2 1 VDDC#70 Y23
LV30 1 1 1 +VGA_CORE 2 1 Y26
CV304 CV303 CV302 LV37 VDDC#71
+VGA_CORE AA13 BBP#1 VDDC#72 Y28
MANHA@ MANHA@ Y13 AH27
10U_0603_6.3V6M MANHA@ 1U_0402_6.3V4Z BLM18PG121SN1D_0603 BBP#2 VDDC#73
2 1 VDDC#74 AH28
2 2 2 CV195 CV196
M15 +VDDCI 1U_0402_6.3V4Z 1 2
4A +VGA_CORE
ISOLATED VDDCI#1 N13 1 1 1 1 LV29 PBY201209T-300Y-N_2P
1 2 CORE I/O VDDCI#2 R12 CV197 CV198 CV199
A VDDCI#3 A
0.1U_0402_16V4Z 1U_0402_6.3V4Z T12 CV200
MANHA@ VDDCI#4
BLM18PG121SN1D_0603 2 2 2 2
+1.8VS 2 1 0.1U_0402_16V4Z SPV18 1U_0402_6.3V4Z 1U_0402_6.3V4Z 10U_0603_6.3V6M
LV31 1 1 1 216-0729002 A12 M96_BGA962
MANHA@ CV307 CV305 CV306
MANHA@
10U_0603_6.3V6M
2
MANHA@
2 2
1U_0402_6.3V4Z Security Classification @ Compal Secret Data Compal Electronics, Inc.
SCHEMATIC,MB A6052
5 4 3 2 1
5 4 3 2 1
UV1F
AB39 PCIE_VSS#1 GND#1 A3

E39 PCIE_VSS#2 GND#2 A37
F34 PCIE_VSS#3 GND#3 AA16
F39 PCIE_VSS#4 GND#4 AA18
G33 PCIE_VSS#5 GND#5 AA2
G34 PCIE_VSS#6 GND#6 AA21
H31 PCIE_VSS#7 GND#7 AA23
J31 PCIE_VSS#10 GND#10 AA6
D D
J34 PCIE_VSS#11 GND#11 AB12
K31 PCIE_VSS#12 GND#12 AB15
L31 PCIE_VSS#15 GND#15 AB22
L34 PCIE_VSS#16 GND#16 AB24
M34 PCIE_VSS#17 GND#17 AB27
M39 PCIE_VSS#18 GND#18 AC11
N31 PCIE_VSS#19 GND#19 AC13
N34 PCIE_VSS#20 GND#20 AC16
P31 PCIE_VSS#21 GND#21 AC18
R34 PCIE_VSS#24 GND#24 AC23
T31 PCIE_VSS#25 GND#25 AC26
U31 PCIE_VSS#28 GND#28 AD15
U34 PCIE_VSS#29 GND#29 AD17
V34 PCIE_VSS#30 GND#30 AD20
V39 PCIE_VSS#31 GND#31 AD22
W31 PCIE_VSS#32 GND#32 AD24
W34 PCIE_VSS#33 GND#33 AD27
Y34 PCIE_VSS#34 GND#34 AD9
Y39 PCIE_VSS#35 GND#35 AE2
GND#36 AE6
GND#37 AF10
GND#38 AF16
GND#39 AF18
AF21
F15 GND#101
GND GND#40
GND#41
GND#42
AG17
AG2
C C
F17 GND#102 GND#43 AG20
F19 GND#103 GND#44 AG22
F21 GND#104 GND#45 AG6
F23 GND#105 GND#46 AG9
F25 GND#106 GND#47 AH21
F27 GND#107 GND#48 AH29
F29 GND#108 GND#49 AJ10
F31 GND#109 GND#50 AJ11
F33 GND#110 GND#51 AJ2
G2 GND#113 GND#54 AK11
G6 GND#114 GND#55 AK31
H9 GND#115 GND#56 AK7
J2 GND#116 GND#57 AL11
J27 GND#117 GND#58 AL14
K14 GND#120 GND#61 AL20
K7 GND#121 GND#62 AL21
L11 GND#122 GND#63 AL23
L17 GND#123 GND#64 AL26
L2 GND#124 GND#65 AL32
L6 GND#127 GND#68 AM11
M17 GND#128 GND#69 AM31
M22 GND#129 GND#70 AM9
M24 GND#130 GND#71 AN11
N16 GND#131 GND#72 AN2
N18 GND#132 GND#73 AN30
B B
N23 GND#135 GND#76 AP11
N26 GND#136 GND#77 AP7
N6 GND#137 GND#78 AP9
R15 GND#138 GND#79 AR5
R17 GND#139 GND#80 AW34
R2 GND#140 GND#81 B11
R20 GND#141 GND#82 B13
R22 GND#142 GND#83 B15
R24 GND#143 GND#84 B17
R27 GND#144 GND#85 B19
R6 GND#145 GND#86 B21
T11 GND#146 GND#87 B23
T13 GND#147 GND#88 B25
T16 GND#148 GND#89 B27
T18 GND#149 GND#90 B29
T21 GND#150 GND#91 B31
T23 GND#151 GND#92 B33
T26 GND#152 GND#93 B7
U15 GND#153 GND#94 B9
U17 GND#154 GND#95 C1
U2 GND#155 GND#96 C39
U20 GND#156 GND#97 E35
U22 GND#157 GND#98 E5
U24 GND#158 GND#99 F11
U27 GND#159 GND#100 F13
U6 GND#160
V11 GND#161
V16 GND#162
V18 GND#163
V21 GND#164
V23 GND#165
A A
V26 GND#166
W2 GND#167
W6 GND#168
Y15 GND#169
Y17 GND#170
Y20 GND#171
Y22 GND#172 VSS_MECH#1 A39
Y24 AW1
Y27
GND#173
GND#174
VSS_MECH#2
VSS_MECH#3 AW39
U13 GND#175 Issued Date 2008-09-25 Deciphered Date 2009-09-25 Title
V13 GND#176
SCHEMATIC,MB A6052
216-0729002 A12 M96_BGA962 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401851 A
@ Date: Wednesday, January 20, 2010 Sheet 39 of 53
5 4 3 2 1
5 4 3 2 1
MDB[0..63]
MDA[0..63] MDB[0..63] <42>
MDA[0..63] <41>
Park uses memory group B only

D D
UV1C
UV1D
MDA0 C37 G24 MAA0 MAA[13..0]

DQA_0 MAA_0 MAA[13..0] <41> MAB[13..0]
MDA1 C35 J23 MAA1 MDB0 C5 P8 MAB0
DQA_1 MAA_1 DQB_0 MAB_0 MAB[13..0] <42>
MEMORY INTERFACE A
MDA2 A35 H24 MAA2 MDB1 C3 T9 MAB1
DQA_2 MAA_2 DQB_1 MAB_1
MEMORY INTERFACE B
MDA3 E34 J24 MAA3 MDB2 E3 P9 MAB2
MDA4 DQA_3 MAA_3 MAA4 MDB3 DQB_2 MAB_2 MAB3
G32 DQA_4 MAA_4 H26 E1 DQB_3 MAB_3 N7
MDA5 D33 J26 MAA5 MDB4 F1 N8 MAB4
F32 DQA_6 MAA_6 H21 F3 DQB_5 MAB_5 N9
MDA7 E32 G21 MAA7 MDB6 F5 U9 MAB6
D31 DQA_8 MAA_8 H19 G4 DQB_7 MAB_7 U8
MDA9 F30 H20 MAA9 MDB8 H5 Y9 MAB8
C30 DQA_10 MAA_10 L13 H6 DQB_9 MAB_9 W9
MDA11 A30 G16 MAA11 A_BA[2..0] MDB10 J4 AC8 MAB10
DQA_11 MAA_11 A_BA[2..0] <41> DQB_10 MAB_10
MDA12 F28 J16 MAA12 MDB11 K6 AC9 MAB11
MDA13 DQA_12 MAA_12 A_BA2 MDB12 DQB_11 MAB_11 MAB12
C28 DQA_13 MAA_13/BA2 H16 K5 DQB_12 MAB_12 AA7
MDA14 A28 J17 A_BA0 MDB13 L4 AA8 B_BA2 B_BA[2..0]
DQA_14 MAA_14/BA0 DQB_13 MAB_13/BA2 B_BA[2..0] <42>
MDA15 E28 H17 A_BA1 MDB14 M6 Y8 B_BA0
MDA16 DQA_15 MAA_15/BA1 MDB15 DQB_14 MAB_14/BA0 B_BA1
D27 DQA_16 M1 DQB_15 MAB_15/BA1 AA9
MDA17 F26 A32 DQMA#0 MDB16 M3
DQA_17 DQMA_0 DQMA#[7..0] <41> DQB_16
MDA18 C26 C32 DQMA#1 MDB17 M5 H3 DQMB#0
DQA_18 DQMA_1 DQB_17 DQMB_0 DQMB#[7..0] <42>
MDA19 A26 D23 DQMA#2 MDB18 N4 H1 DQMB#1
MDA20 DQA_19 DQMA_2 DQMA#3 MDB19 DQB_18 DQMB_1 DQMB#2
F24 DQA_20 DQMA_3 E22 P6 DQB_19 DQMB_2 T3
MDA21 C24 C14 DQMA#4 MDB20 P5 T5 DQMB#3
MDA22 A24
DQA_21
DQA_22
DQMA_4
DQMA_5 A14 DQMA#5 Close to pin Y12 MDB21 R4
DQB_20
DQB_21
DQMB_3
DQMB_4 AE4 DQMB#4
MDA23 E24 E10 DQMA#6 +1.5VS MDB22 T6 AF5 DQMB#5
C MDA24 DQA_23 DQMA_6 DQMA#7 MDB23 DQB_22 DQMB_5 DQMB#6 C
C22 DQA_24 DQMA_7 D9 T1 DQB_23 DQMB_6 AK6
MDA25 A22 MDB24 U4 AK5 DQMB#7
DQA_25 DQB_24 DQMB_7
1
MDA26 F22 C34 QSA0 MDB25 V6
DQA_26 QSA_0/RDQSA_0 QSA[7..0] <41> DQB_25
MDA27 D21 D29 QSA1 RV42 MDB26 V1 F6 QSB0
DQA_27 QSA_1/RDQSA_1 DQB_26 QSB_0/RDQSB_0 QSB[7..0] <42>
MDA28 A20 D25 QSA2 MDB27 V3 K3 QSB1
Close to pin L18 MDA29 F20
DQA_28
DQA_29
QSA_2/RDQSA_2
QSA_3/RDQSA_3 E20 QSA3 40.2_0402_1% MDB28 Y6
DQB_27
DQB_28
QSB_1/RDQSB_1
QSB_2/RDQSB_2 P3 QSB2
+1.5VS MDA30 D19 E16 QSA4 MDB29 Y1 V5 QSB3
2
MDA31 DQA_30 QSA_4/RDQSA_4 QSA5 MDB30 DQB_29 QSB_3/RDQSB_3 QSB4
E18 DQA_31 QSA_5/RDQSA_5 E12 Y3 DQB_30 QSB_4/RDQSB_4 AB5
MDA32 C18 J10 QSA6 +MVREFDB MDB31 Y5 AH1 QSB5
DQA_32 QSA_6/RDQSA_6 DQB_31 QSB_5/RDQSB_5
1
MDA33 A18 D7 QSA7 MDB32 AA4 AJ9 QSB6

RV41 MDA34 DQA_33 QSA_7/RDQSA_7 MDB33 DQB_32 QSB_6/RDQSB_6 QSB7
F18 DQA_34 1 AB6 DQB_33 QSB_7/RDQSB_7 AM5
1
40.2_0402_1% MDA35 D17 A34 QSA#0 CV203 MDB34 AB1
DQA_35 QSA_0B/WDQSA_0 QSA#[7..0] <41> DQB_34
MDA36 A16 E30 QSA#1 RV44 0.1U_0402_16V4Z MDB35 AB3 G7 QSB#0
DQA_36 QSA_1B/WDQSA_1 DQB_35 QSB_0B/WDQSB_0 QSB#[7..0] <42>
MDA37 F16 E26 QSA#2 MDB36 AD6 K1 QSB#1
2
MDA38 DQA_37 QSA_2B/WDQSA_2 QSA#3 2 MDB37 DQB_36 QSB_1B/WDQSB_1 QSB#2

D15 DQA_38 QSA_3B/WDQSA_3 C20 AD1 DQB_37 QSB_2B/WDQSB_2 P1
+MVREFDA MDA39 E14 C16 QSA#4 MDB38 AD3 W4 QSB#3
2
MDA40 DQA_39 QSA_4B/WDQSA_4 QSA#5 MDB39 DQB_38 QSB_3B/WDQSB_3 QSB#4
F14 DQA_40 QSA_5B/WDQSA_5 C12 AD5 DQB_39 QSB_4B/WDQSB_4 AC4
1 MDA41 D13 J11 QSA#6 100_0402_1% MDB40 AF1 AH3 QSB#5
DQA_41 QSA_6B/WDQSA_6 DQB_40 QSB_5B/WDQSB_5
1
CV202 MDA42 F12 F8 QSA#7 MDB41 AF3 AJ8 QSB#6

RV43 0.1U_0402_16V4Z MDA43 DQA_42 QSA_7B/WDQSA_7 MDB42 DQB_41 QSB_6B/WDQSB_6 QSB#7
A12 DQA_43 AF6 DQB_42 QSB_7B/WDQSB_7 AM3
100_0402_1% MDA44 D11 J21 ODTA0 MDB43 AG4
2 DQA_44 ODTA0 ODTA0 <41> DQB_43
MDA45 F10 G19 ODTA1 MDB44 AH5 T7 ODTB0
DQA_45 ODTA1 ODTA1 <41> DQB_44 ODTB0 ODTB0 <42>
MDA46 A10 MDB45 AH6 W7 ODTB1
Close to pin AA12 ODTB1 <42>
2
MDA47 DQA_46 CLKA0 MDB46 DQB_45 ODTB1

C10 DQA_47 CLKA0 H27 CLKA0 <41> AJ4 DQB_46
MDA48 G13 G27 CLKA0# +1.5VS MDB47 AK3 L9 CLKB0
DQA_48 CLKA0B CLKA0# <41> DQB_47 CLKB0 CLKB0 <42>
MDA49 H13 MDB48 AF8 L8 CLKB0#
DQA_49 DQB_48 CLKB0B CLKB0# <42>
MDA50 J13 J14 CLKA1 MDB49 AF9
DQA_50 CLKA1 CLKA1 <41> DQB_49
1
MDA51 H11 H14 CLKA1# MDB50 AG8 AD8 CLKB1
DQA_51 CLKA1B CLKA1# <41> DQB_50 CLKB1 CLKB1 <42>
MDA52 G10 RV46 40.2_0402_1% MDB51 AG7 AD7 CLKB1#
B DQA_52 DQB_51 CLKB1B CLKB1# <42> B
MDA53 G8 K23 RASA0# MDB52 AK9
DQA_53 RASA0B RASA0# <41> DQB_52
MDA54 K9 K19 RASA1# MDB53 AL7 T10 RASB0#
DQA_54 RASA1B RASA1# <41> DQB_53 RASB0B RASB0# <42>
MDA55 K10 MDB54 AM8 Y10 RASB1#
RASB1# <42>
2
MDA56 DQA_55 CASA0# +MVREFSB MDB55 DQB_54 RASB1B
G9 DQA_56 CASA0B K20 CASA0# <41> AM7 DQB_55
MDA57 A8 K17 CASA1# MDB56 AK1 W10 CASB0#
DQA_57 CASA1B CASA1# <41> DQB_56 CASB0B CASB0# <42>
MDA58 C8 MDB57 AL4 AA10 CASB1#
DQA_58 DQB_57 CASB1B CASB1# <42>
1
MDA59 E8 K24 CSA0#_0 1 MDB58 AM6
DQA_59 CSA0B_0 CSA0#_0 <41> DQB_58
MDA60 A6 K27 RV52 CV205 MDB59 AM1 P10 CSB0#_0
DQA_60 CSA0B_1 DQB_59 CSB0B_0 CSB0#_0 <42>
MDA61 C6 MDB60 AN4 L10
MDA62 DQA_61 CSA1#_0 0.1U_0402_16V4Z MDB61 DQB_60 CSB0B_1
E6 DQA_62 CSA1B_0 M13 CSA1#_0 <41> AP3 DQB_61
MDA63 2 MDB62 CSB1#_0
A5 K16 AP1 AD10 CSB1#_0 <42>
2
DQA_63 CSA1B_1 MDB63 DQB_62 CSB1B_0
AP5 DQB_63 CSB1B_1 AC10
+MVREFDA L18 K21 CKEA0 100_0402_1%
+1.5VS MVREFDA CKEA0 CKEA0 <41>
+MVREFSA L20 J20 CKEA1 U10 CKEB0
MVREFSA CKEA1 CKEA1 <41> CKEB0 CKEB0 <42>
+MVREFDB Y12 AA11 CKEB1
MVREFDB CKEB1 CKEB1 <42>
MANHA@1 RV48 2 243_0402_1% L27 K26 WEA0# +MVREFSB AA12
NC_MEM_CALRN0 WEA0B WEA0# <41> +3VS_DELAY MVREFSB
MANHA@1 RV49 2 243_0402_1% N12 L15 WEA1# N10 WEB0#
NC_MEM_CALRN1 WEA1B WEA1# <41> WEB0B WEB0# <42>
MANHA@1 RV50 2 243_0402_1% AG12 AB11 WEB1#
NC_MEM_CALRN2 WEB1B WEB1# <42>
AF28
Close to pin L20 RSVD#1
1
1 RV51 2 243_0402_1% M12 MEM_CALRP1 RSVD#2 AG28 M9X@ M9X@ RV54

+1.5VS MANHA@1 RV53 2 243_0402_1% M27 AL31 TESTEN AD28 RV132 0_0402_5% 2 1
NC_MEM_CALRP0 RSVD#3 TESTEN +1.5VS
MANHA@1 RV55 2 243_0402_1% AH12 @ RV56 MANHA@ CV320 0.1U_0402_16V4Z 4.7K_0402_5%
NC_MEM_CALRP2 MAA13 10K_0402_5% RV57 2
RSVD#5 H23 1 51_0402_5% 1 2 TESTA AK10 CLKTESTA
MANHA@RV132
MANHA@RV132
1
J19 RV58 2 1 51_0402_5% 1 2 TESTB AL10 AH11 2 1 DRAM_RST# <41,42>

2
RV45 RSVD#6 TESTEN MANHA@ CLKTESTB DRAM_RST
1
40.2_0402_1% T8 MAB13 CV321 MANHA@
0.1U_0402_16V4Z 1 51_0402_5%
RSVD#9
1
W8 MANHA@ CV206 M9X@ CV206 MANHA@

RSVD#11 RV23 RV59
2
+MVREFSA 10K_0402_5% M9X@ RV125 4.7K_0402_5% MANHA@ 10K_0402_5%

A 2 A
2 1 TESTA
2
216-0729002 A12 M96_BGA962 M9X@ RV129 4.7K_0402_5% 216-0729002 A12 M96_BGA962 68P_0402_50V8J
2
1
1 2 1 TESTB 0.01U_0402_25V7K
RV47 CV204 @ @
100_0402_1%
2 Security Classification Compal Secret Data Compal Electronics, Inc.
2

0.1U_0402_16V4Z
SCHEMATIC,MB A6052
5 4 3 2 1
5 4 3 2 1
UV2 UV3 UV4 UV5
+VREFC_A1 M8 E3 MDA23 +VREFC_A2 M8 E3 MDA25 +VREFC_A3 M8 E3 MDA35 +VREFC_A4 M8 E3 MDA48

+VREFD_A1 H1 VREFCA DQL0 MDA18 +VREFD_A2 VREFCA DQL0 MDA30 +VREFD_A3 VREFCA DQL0 MDA32 +VREFD_A4 VREFCA DQL0 MDA51
VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 MDA22 F2 MDA24 F2 MDA38 F2 MDA55
MAA0 DQL2 MDA19 MAA0 DQL2 MDA29 MAA0 DQL2 MDA34 MAA0 DQL2 MDA54
N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8
MAA1 P7 H3 MDA20 Group2 MAA1 P7 H3 MDA26 Group3 MAA1 P7 H3 MDA37 Group4 MAA1 P7 H3 MDA50 Group6
MDA[0..63] MAA2 A1 DQL4 MDA17 MAA2 A1 DQL4 MDA31 MAA2 A1 DQL4 MDA36 MAA2 A1 DQL4 MDA52
<40> MDA[0..63] P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8
MAA3 N2 G2 MDA21 MAA3 N2 G2 MDA27 MAA3 N2 G2 MDA39 MAA3 N2 G2 MDA49
MAA4 A3 DQL6 MDA16 MAA4 A3 DQL6 MDA28 MAA4 A3 DQL6 MDA33 MAA4 A3 DQL6 MDA53
P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7
MAA5 P2 MAA5 P2 MAA5 P2 MAA5 P2
MAA6 A5 MAA6 A5 MAA6 A5 MAA6 A5
R8 A6 R8 A6 R8 A6 R8 A6
MAA7 R2 D7 MDA0 MAA7 R2 D7 MDA15 MAA7 R2 D7 MDA43 MAA7 R2 D7 MDA63
D MAA8 A7 DQU0 MDA5 MAA8 A7 DQU0 MDA11 MAA8 A7 DQU0 MDA44 MAA8 A7 DQU0 MDA58 D
T8 A8 DQU1 C3 T8 A8 DQU1 C3 T8 A8 DQU1 C3 T8 A8 DQU1 C3
MAA9 R3 C8 MDA1 MAA9 R3 C8 MDA14 MAA9 R3 C8 MDA40 MAA9 R3 C8 MDA60
MAA10 A9 DQU2 MDA7 MAA10 A9 DQU2 MDA10 MAA10 A9 DQU2 MDA45 MAA10 A9 DQU2 MDA59
<40> MAA[13..0] L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
MAA11 R7 A7 MDA3 Group0 MAA11 R7 A7 MDA13 Group1 MAA11 R7 A7 MDA42 Group5 MAA11 R7 A7 MDA61 Group7
MAA12 A11 DQU4 MDA4 MAA12 A11 DQU4 MDA9 MAA12 A11 DQU4 MDA46 MAA12 A11 DQU4 MDA56
N7 A12/BC DQU5 A2 N7 A12/BC DQU5 A2 N7 A12/BC DQU5 A2 N7 A12/BC DQU5 A2
MAA13 T3 B8 MDA2 MAA13 T3 B8 MDA12 MAA13 T3 B8 MDA41 MAA13 T3 B8 MDA62
A13 DQU6 MDA6 A13 DQU6 MDA8 A13 DQU6 MDA47 A13 DQU6 MDA57
DQU7 A3 DQU7 A3 DQU7 A3 DQU7 A3
<40> DQMA#[7..0] +1.5VS +1.5VS +1.5VS +1.5VS
M2 B2 A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2

<40> A_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
N8 D9 A_BA1 N8 D9 A_BA1 N8 D9 A_BA1 N8 D9
<40> A_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
M3 G7 A_BA2 M3 G7 A_BA2 M3 G7 A_BA2 M3 G7
<40> QSA[7..0] <40> A_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
VDD K2 VDD K2 VDD K2 VDD K2
VDD N1 VDD N1 VDD N1 VDD N1
J7 N9 CLKA0 J7 N9 J7 N9 CLKA1 J7 N9
<40> CLKA0 CK VDD CK VDD <40> CLKA1 CK VDD CK VDD
K7 R1 CLKA0# K7 R1 K7 R1 CLKA1# K7 R1
<40> QSA#[7..0] <40> CLKA0# CK VDD CK VDD <40> CLKA1# CK VDD CK VDD
K9 R9 CKEA0 K9 R9 K9 R9 CKEA1 K9 R9
<40> CKEA0 CKE VDD +1.5VS CKE VDD <40>
+1.5VS CKEA1 CKE VDD +1.5VS CKE VDD +1.5VS
K1 A1 ODTA0 K1 A1 K1 A1 ODTA1 K1 A1
<40> ODTA0 ODT VDDQ ODT VDDQ <40> ODTA1 ODT VDDQ ODT VDDQ
L2 A8 CSA0#_0 L2 A8 L2 A8 CSA1#_0 L2 A8
A_BA[2..0] <40> CSA0#_0 CS VDDQ CS VDDQ <40> CSA1#_0 CS VDDQ CS VDDQ
J3 C1 RASA0# J3 C1 J3 C1 RASA1# J3 C1
<40> A_BA[2..0] <40> RASA0# RAS VDDQ RAS VDDQ <40> RASA1# RAS VDDQ RAS VDDQ
K3 C9 CASA0# K3 C9 K3 C9 CASA1# K3 C9
<40> CASA0# CAS VDDQ CAS VDDQ <40> CASA1# CAS VDDQ CAS VDDQ
L3 D2 WEA0# L3 D2 L3 D2 WEA1# L3 D2
<40> WEA0# WE VDDQ WE VDDQ <40> WEA1# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSA2 F3 H2 QSA3 F3 H2 QSA4 F3 H2 QSA6 F3 H2
QSA0 DQSL VDDQ QSA1 DQSL VDDQ QSA5 DQSL VDDQ QSA7 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9
C DQMA#2 DQMA#3 DQMA#4 DQMA#6 C

E7 DML VSS A9 E7 DML VSS A9 E7 DML VSS A9 E7 DML VSS A9
DQMA#0 D3 B3 DQMA#1 D3 B3 DQMA#5 D3 B3 DQMA#7 D3 B3
DMU VSS DMU VSS DMU VSS DMU VSS
VSS E1 VSS E1 VSS E1 VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
QSA#2 G3 J2 QSA#3 G3 J2 QSA#4 G3 J2 QSA#6 G3 J2
QSA#0 DQSL VSS QSA#1 DQSL VSS QSA#5 DQSL VSS QSA#7 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8
VSS M1 VSS M1 VSS M1 VSS M1
VSS P1 VSS P1 VSS P1 VSS P1
T2 P9 DRAM_RST# T2 P9 DRAM_RST# T2 P9 DRAM_RST# T2 P9
<40,42> DRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
VSS T1 VSS T1 VSS T1 VSS T1
L8 ZQ VSS T9 L8 ZQ VSS T9 L8 ZQ VSS T9 L8 ZQ VSS T9
1
1
J1 NC VSSQ B1 J1 NC VSSQ B1 J1 NC VSSQ B1 J1 NC VSSQ B1
RV61 L1 B9 RV62 L1 B9 RV63 L1 B9 RV64 L1 B9
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
243_0402_1% J9 NC VSSQ D1 243_0402_1% J9 NC VSSQ D1 243_0402_1% J9 NC VSSQ D1 243_0402_1% J9 NC VSSQ D1
L9 NC VSSQ D8 L9 NC VSSQ D8 L9 NC VSSQ D8 L9 NC VSSQ D8
E2 E2 E2 E2
2
2
VSSQ VSSQ VSSQ VSSQ
M7 NC VSSQ E8 M7 NC VSSQ E8 M7 NC VSSQ E8 M7 NC VSSQ E8
T7 NC VSSQ F9 T7 NC VSSQ F9 T7 NC VSSQ F9 T7 NC VSSQ F9
8PCS@ G1 8PCS@ G1 8PCS@ G1 8PCS@ G1
VSSQ VSSQ VSSQ VSSQ
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
96-BALL 96-BALL 96-BALL 96-BALL

SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4W2G1646B-HC12_FBGA96~D K4W2G1646B-HC12_FBGA96~D K4W2G1646B-HC12_FBGA96~D K4W2G1646B-HC12_FBGA96~D
+1.5VS +1.5VS +1.5VS +1.5VS +1.5VS +1.5VS +1.5VS +1.5VS
@ 1 @ @ @
1
1
8PCS@ 8PCS@ RV67 8PCS@ RV68 8PCS@ RV69 8PCS@ RV70 8PCS@ RV71 8PCS@ RV72 8PCS@
B RV65 RV66 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% B
4.99K_0402_1% 4.99K_0402_1%
2
2
+VREFC_A2 +VREFD_A2 +VREFC_A3 +VREFD_A3 +VREFC_A4 +VREFD_A4
2
+VREFC_A1 +VREFD_A1
1
1
1 1 1 1 1 1
1
1 1 RV77 CV207 RV78 CV211 RV79 CV208 RV74 CV212 RV75 CV213 RV80 CV214
RV73 CV209 RV76 CV210 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
4.99K_0402_1% 0.1U_0402_16V4Z 4.99K_0402_1% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 2 2 2 2 2 2
2
2
2 2
2
8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@
8PCS@ 8PCS@
+1.5VS +1.5VS +1.5VS

+1.5VS
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
CLKA0 1 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z
RV81 56_0402_1% 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV217
CV218
CV219
CV220
CV221
CV222
CV223
CV224
CV237
CV225
CV226
CV238
CV239
CV227
CV240
CV228
CV241
CV229
CV242
CV243
CV230
8PCS@ 1 1 1 1 1 1 1
CV231
CV215
CV232
CV216
CV233
CV235
CV236
CLKA0# 1 2 1
RV82 56_0402_1% 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CV234 2 2 2 2 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
8PCS@
0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 8PCS@ 8PCS@1U_0402_6.3V4Z 1U_0402_6.3V4Z
2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@
8PCS@ 8PCS@8PCS@8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@
CLKA1 1 2 +1.5VS 10U_0603_6.3V 10U_0603_6.3V +1.5VS 10U_0603_6.3V 10U_0603_6.3V

RV83 56_0402_1% 1 1 1 1 1 1 1 1
A A
8PCS@
CV246 CV247 CV248 CV249 CV250 CV251 CV244 CV245
CLKA1# 1 2
RV84 56_0402_1% 2 2 2 2 2 2 2 2
1
8PCS@ CV252 10U_0603_6.3V 10U_0603_6.3V 10U_0603_6.3V 10U_0603_6.3V
0.1U_0402_16V4Z 8PCS@ 8PCS@ 8PCS@ 8PCS@
2 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@
SCHEMATIC,MB A6052
5 4 3 2 1
5 4 3 2 1
UV6 UV7 UV8 UV9
+VREFC_B1 M8 E3 MDB26 +VREFC_B2 M8 E3 MDB23 +VREFC_B3 M8 E3 MDB35 +VREFC_B4 M8 E3 MDB55

+VREFD_B1 VREFCA DQL0 MDB28 +VREFD_B2 VREFCA DQL0 MDB20 +VREFD_B3 VREFCA DQL0 MDB37 +VREFD_B4 VREFCA DQL0 MDB51
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 MDB27 F2 MDB19 F2 MDB32 F2 MDB54
MAB0 DQL2 MDB29 MAB0 DQL2 MDB18 MAB0 DQL2 MDB39 MAB0 DQL2 MDB48
N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8
MAB1 P7 H3 MDB25 Group3 MAB1 P7 H3 MDB21 Group2 MAB1 P7 H3 MDB34 Group4 MAB1 P7 H3 MDB53 Group6
MAB2 A1 DQL4 MDB30 MAB2 A1 DQL4 MDB17 MAB2 A1 DQL4 MDB38 MAB2 A1 DQL4 MDB49
P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8
MAB3 N2 G2 MDB24 MAB3 N2 G2 MDB22 MAB3 N2 G2 MDB33 MAB3 N2 G2 MDB52
MDB[0..63] MAB4 A3 DQL6 MDB31 MAB4 A3 DQL6 MDB16 MAB4 A3 DQL6 MDB36 MAB4 A3 DQL6 MDB50
<40> MDB[0..63] P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7
MAB5 P2 MAB5 P2 MAB5 P2 MAB5 P2
MAB6 A5 MAB6 A5 MAB6 A5 MAB6 A5
R8 A6 R8 A6 R8 A6 R8 A6
D MAB7 MDB15 MAB7 MDB2 MAB7 MDB45 MAB7 MDB56 D
R2 A7 DQU0 D7 R2 A7 DQU0 D7 R2 A7 DQU0 D7 R2 A7 DQU0 D7
MAB8 T8 C3 MDB10 MAB8 T8 C3 MDB6 MAB8 T8 C3 MDB43 MAB8 T8 C3 MDB59
<40> MAB[13..0] A8 DQU1 A8 DQU1 A8 DQU1 A8 DQU1
MAB9 R3 C8 MDB12 MAB9 R3 C8 MDB0 MAB9 R3 C8 MDB47 MAB9 R3 C8 MDB63
MAB10 A9 DQU2 MDB11 MAB10 A9 DQU2 MDB5 MAB10 A9 DQU2 MDB41 MAB10 A9 DQU2 MDB62
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
MAB11 R7 A7 MDB13 Group1 MAB11 R7 A7 MDB1 Group0 MAB11 R7 A7 MDB44 Group5 MAB11 R7 A7 MDB57 Group7
MAB12 A11 DQU4 MDB9 MAB12 A11 DQU4 MDB7 MAB12 A11 DQU4 MDB40 MAB12 A11 DQU4 MDB61
N7 A12/BC DQU5 A2 N7 A12/BC DQU5 A2 N7 A12/BC DQU5 A2 N7 A12/BC DQU5 A2
MAB13 T3 B8 MDB14 MAB13 T3 B8 MDB3 MAB13 T3 B8 MDB46 MAB13 T3 B8 MDB58
<40> DQMB#[7..0] A13 DQU6 A13 DQU6 A13 DQU6 A13 DQU6
A3 MDB8 A3 MDB4 A3 MDB42 A3 MDB60
DQU7 DQU7 DQU7 DQU7
+1.5VS +1.5VS +1.5VS +1.5VS
M2 B2 B_BA0 M2 B2 B_BA0 M2 B2 B_BA0 M2 B2

<40> QSB[7..0] <40> B_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
N8 D9 B_BA1 N8 D9 B_BA1 N8 D9 B_BA1 N8 D9
<40> B_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
M3 G7 B_BA2 M3 G7 B_BA2 M3 G7 B_BA2 M3 G7
<40> B_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
<40> QSB#[7..0] VDD N1 VDD N1 VDD N1 VDD N1
J7 N9 CLKB0 J7 N9 J7 N9 CLKB1 J7 N9
<40> CLKB0 CK VDD CK VDD <40> CLKB1 CK VDD CK VDD
K7 R1 CLKB0# K7 R1 K7 R1 CLKB1# K7 R1
<40> CLKB0# CK VDD CK VDD <40> CLKB1# CK VDD CK VDD
K9 R9 CKEB0 K9 R9 K9 R9 CKEB1 K9 R9
<40> CKEB0 CKE VDD CKE VDD <40> CKEB1 CKE VDD CKE VDD
+1.5VS +1.5VS +1.5VS +1.5VS
K1 A1 ODTB0 K1 A1 K1 A1 ODTB1 K1 A1
<40> ODTB0 ODT VDDQ ODT VDDQ <40> ODTB1 ODT VDDQ ODT VDDQ
L2 A8 CSB0#_0 L2 A8 L2 A8 CSB1#_0 L2 A8
<40> CSB0#_0 CS VDDQ CS VDDQ <40> CSB1#_0 CS VDDQ CS VDDQ
J3 C1 RASB0# J3 C1 J3 C1 RASB1# J3 C1
<40> RASB0# RAS VDDQ RAS VDDQ <40> RASB1# RAS VDDQ RAS VDDQ
K3 C9 CASB0# K3 C9 K3 C9 CASB1# K3 C9
<40> CASB0# CAS VDDQ CAS VDDQ <40> CASB1# CAS VDDQ CAS VDDQ
L3 D2 WEB0# L3 D2 L3 D2 WEB1# L3 D2
<40> WEB0# WE VDDQ WE VDDQ <40> WEB1# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSB3 F3 H2 QSB2 F3 H2 QSB4 F3 H2 QSB6 F3 H2
QSB1 DQSL VDDQ QSB0 DQSL VDDQ QSB5 DQSL VDDQ QSB7 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9
C C
DQMB#3 E7 A9 DQMB#2 E7 A9 DQMB#4 E7 A9 DQMB#6 E7 A9
DQMB#1 DML VSS DQMB#0 DML VSS DQMB#5 DML VSS DQMB#7 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3
VSS E1 VSS E1 VSS E1 VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
QSB#3 G3 J2 QSB#2 G3 J2 QSB#4 G3 J2 QSB#6 G3 J2
QSB#1 DQSL VSS QSB#0 DQSL VSS QSB#5 DQSL VSS QSB#7 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8
VSS P1 VSS P1 VSS P1 VSS P1
T2 P9 DRAM_RST# T2 P9 DRAM_RST# T2 P9 DRAM_RST# T2 P9
<40,41> DRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
VSS T1 VSS T1 VSS T1 VSS T1
L8 ZQ VSS T9 L8 ZQ VSS T9 L8 ZQ VSS T9 L8 ZQ VSS T9
1
1
J1 NC VSSQ B1 J1 NC VSSQ B1 J1 NC VSSQ B1 J1 NC VSSQ B1
RV85 L1 B9 RV86 L1 B9 RV87 L1 B9 RV88 L1 B9
4PCS@ NC VSSQ 4PCS@ NC VSSQ 4PCS@ NC VSSQ 4PCS@ NC VSSQ
243_0402_1% J9 NC VSSQ D1 243_0402_1% J9 NC VSSQ D1 243_0402_1% J9 NC VSSQ D1 243_0402_1% J9 NC VSSQ D1
L9 NC VSSQ D8 L9 NC VSSQ D8 L9 NC VSSQ D8 L9 NC VSSQ D8
E2 E2 E2 E2
2
2
VSSQ VSSQ VSSQ VSSQ
M7 NC VSSQ E8 M7 NC VSSQ E8 M7 NC VSSQ E8 M7 NC VSSQ E8
T7 NC VSSQ F9 T7 NC VSSQ F9 T7 NC VSSQ F9 T7 NC VSSQ F9
96-BALL 96-BALL 96-BALL 96-BALL

SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4W2G1646B-HC12_FBGA96~D K4W2G1646B-HC12_FBGA96~D K4W2G1646B-HC12_FBGA96~D K4W2G1646B-HC12_FBGA96~D
+1.5VS +1.5VS +1.5VS +1.5VS +1.5VS +1.5VS +1.5VS +1.5VS
@ @ Default @
1
1
B RV89 RV90 RV91 RV92 4PCS@ RV93 4PCS@ @ RV94 4PCS@ RV95 4PCS@ RV96 4PCS@ B
4.99K_0402_1% 4PCS@ 4.99K_0402_1% 4PCS@ 4.99K_0402_1% 4PCS@ 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
2
2
+VREFC_B1 +VREFD_B1 +VREFC_B2 +VREFD_B2 +VREFC_B3 +VREFD_B3 +VREFC_B4 +VREFD_B4
1
1
1 1 1 1 1 1 1 1
RV97 CV253 RV98 CV254 RV99 CV255 RV100 CV256 RV101 CV257 RV102 CV258 RV103 CV259 RV104 CV260
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
4PCS@ 2 4PCS@ 2 4PCS@ 2 4PCS@ 2 4PCS@ 2 4PCS@ 2 4PCS@ 2 4PCS@ 2
2
2
4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@
+1.5VS +1.5VS +1.5VS +1.5VS
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z

1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
CLKB0 1 2
RV105 56_0402_1% 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV261
CV262
CV263
CV264
CV265
CV266
CV267
CV268
CV269
CV270
CV271
CV272
CV273
CV274
CV275
CV287
CV276
CV277
CV278
CV279
CV280
CV281
CV282
CV283
CV284
CV288
CV285
CV286
4PCS@
CLKB0# 1 2
RV106 56_0402_1% 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1
CV289 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z +1.5VS 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
4PCS@
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z +1.5VS 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
0.1U_0402_16V4Z 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 1 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@
2 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@
1
CV193 +
4PCS@ + CV290
10U_0603_6.3V 10U_0603_6.3V 390U_2.5V_M_R10 330U_X_2VM_R6M 10U_0603_6.3V 10U_0603_6.3V
+1.5VS 2 +1.5VS
CLKB1 1 2 1 1 1 1 @ 1 1 1 1
A RV107 56_0402_1% 2 A
4PCS@ CV291 CV293 CV294 CV295 CV296 CV297 CV298 CV292
CLKB1# 2 2 2 2 4PCS@ 2 2 2 2
1 2
RV108 56_0402_1% 1 10U_0603_6.3V 10U_0603_6.3V 10U_0603_6.3V 10U_0603_6.3V
4PCS@ CV299 4PCS@ 4PCS@ 4PCS@
4PCS@
0.1U_0402_16V4Z 4PCS@ 4PCS@ 4PCS@ 4PCS@
2 Security Classification Compal Secret Data Compal Electronics, Inc.
SCHEMATIC,MB A6052
5 4 3 2 1
5 4 3 2 1
CONFIGURATION STRAPS
STRAPS +3VS_DELAY
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
<36> GPU_GPIO0 GPU_GPIO0 @ RV109
@RV109 2 1 10K_0402_5%
GPU by the system BIOS GPU by VBIOS <36> GPU_GPIO1 GPU_GPIO1 @RV110
@ RV110 2 1 10K_0402_5% STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS RECOMMENDED SETTINGS
<36> GPU_GPIO2 GPU_GPIO2 @RV111
@ RV111 2 1 10K_0402_5%
<36> SOUT_GPIO8 SOUT_GPIO8 @RV112
@ RV112 2 1 10K_0402_5%
GPIO22 = 0 (BIOS_ROM_EN = 0) GPIO22 = 1 (BIOS_ROM_EN = 1) <36> SIN_GPIO9 SIN_GPIO9 @RV113
@ RV113 2 1 10K_0402_5% TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING 0
<36> ROMSE_GPIO22 @RV114
@ RV114 2 1 10K_0402_5%
GPIO[13:11] MEMORY SIZE GPIO[13:11] <36> GPU_GPIO11 GPU_GPIO11 RV115 2 1 10K_0402_5% TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED 0
<36> GPU_GPIO12 GPU_GPIO12 @RV116
@ RV116 2 1 10K_0402_5%
D GPU_GPIO13 @RV117
@ RV117 D
128MB 2 1 10K_0402_5%
0 0 0 <36> GPU_GPIO13
BIF_GEN2_EN_A GPIO2 PCIE GNE2 ENABLED 0
256MB
1 0 0
0 0 1
64MB
(M25P05A) H@ RV118 10K_0402_5% BIF_CLK_PM_EN GPIO8 BIF_CLK_PM_EN 0
0 1 0 <17,36> R_VSYNC
<17,36> R_HSYNC H@ RV119
2
2
1
1 10K_0402_5%
<36> HSYNC_DAC2 @RV120
@ RV120 2 1 10K_0402_5%
<36> VSYNC_DAC2 @RV121
@ RV121 2 1 10K_0402_5% BIF_VGA DIS GPIO9 VGA Controller ENABLED 0 (Enable)
GPIO5_AC_BATT TEST
M9X@ QV1 BIOS_ROM_EN GPIO_22_ROMCSB Enable Extermal BIOS device 0

AO3413_SOT23
100mA
D
+3VS 3 1 +3VS_DELAY ROMIDCFG(2:0) GPIO[13:11] ROM Configurations 0 0 1
1
M9X@ CV345 M9X@ CV322 CV346 VIP_DEVICE_STRAP_ENA VSYNC_DAC2 IGNORE VIP DEVICE STRAPS 0
G
2 2
1 2 1 2 0.1U_0402_16V4Z
2 @ AUD[1] AUD[0]
0.1U_0402_16V4Z 0.01U_0402_25V7K AUD[1] HSYNC 0 0 No audio function
0 1 Audio for DisplayPort and HDMI if dongle is detected 11
M9X@ RV134 AUD[0] VSYNC 1 0 Audio for DisplayPort only
47K_0402_5% 1 1 Audio for both DisplayPort and HDMI
11
D
1 2 2 M9X@ QV2
<49> PCIE_OK
M9X@ RV60 0_0402_5% G RSVD HSYNC_DAC2 0
1
S SSM3K7002FU_SC70-3
3
M9X@ RV135 RSVD GENERICC 0

C 100K_0402_5% C
2
AMD RESERVED CONFIGURATION STRAPS

PJ6
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
+3VS 2 1 +3VS_DELAY
2 1
@ JUMP_43X118
HSYNC_DAC2 GENERICC
PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
+1.8VS
GPIO_28_TDO GPIO21_BB_EN
1
RV122 RV123 RV124

10K_0402_5% 10K_0402_5% 10K_0402_5%
@ @ @ STRAPS PIN GPU VRAM size Vendor Part Number# Compal Part Number# VRAM_ID 2,1,0
2
VRAM_ID0 <36>
VRAM_ID1 <36> 512M 64Mx16 (x4) HYN H5TQ1G63BFR-12C SA000032400 000
B B
VRAM_ID2 <36>
512M 64Mx16 (x4) SAM K4W1G1646E-HC12 SA000035700 001
1
Park M2
RV126 RV127 RV128
10K_0402_5% 10K_0402_5% 10K_0402_5% 1G 128Mx16 (x4) HYN 0 1 0 (Reserve)
@ @ @
2
1G 128Mx16 (x4) SAM K4W2G1646B-HC12 SA00003MQ00 0 1 1 (Reserve)

VRAM_ID[2:0] DVPDATA
(2,1,0) 1G 64Mx16 (x8) HYN H5TQ1G63BFR-12C SA000032400 100
1G 64Mx16 (x8) SAM K4W1G1646E-HC12 SA000035700 101

Madison M2
2G 128Mx16 (x8) HYN 1 1 0 (Reserve)
2G 128Mx16 (x8) SAM K4W2G1646B-HC12 SA00003MQ00 1 1 1 (Reserve)
External VGA Thermal Sensor

+3VS
UV1 UV1 UV1
1 2
RV130 0_0402_5%
1
A A
M92 XTX Madison Park
UV11 M92@ MADISON@ PARK@
CV300 2
1 VDD SCLK 8 EC_SMB_CK2 <7,31>
<36> GPU_THERMAL_D+ 0.1U_0402_16V4Z 2 7

D+ SDATA EC_SMB_DA2 <7,31>
CV301
1 2 3 6
2200P_0402_50V7K
D- ALERT# THERM#_VGA <36> Security Classification Compal Secret Data Compal Electronics, Inc.
<36> GPU_THERMAL_D- 4 THERM# GND 5 Issued Date 2008-09-25 Deciphered Date 2009-09-25 Title
SCHEMATIC,MB A6052
ADM1032ARMZ-2REEL_MSOP8 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
5 4 3 2 1
A B C D
VS
VIN PR1
VIN 1M_0402_1%
PL1
PF1
DC30100A700 DC_IN_S1 1 2 DC_IN_S2 1 2
1 2
1
1
PJP1 SMB3025500YA_2P N1 PR2
1 10A_125V_451010MRL PR3 5.6K_0402_5% PR4
+ 84.5K_0402_1% 10K_0402_1%
1
1 1
2 1 2
2
+ PC1 PC2 PC3 PC4 PR5 ACIN <22,31,33>
8
3 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K 100P_0402_50V8J 22K_0402_1% PU1A
2
-
1 2 3
P
+ PACIN
- 4 O 1
2 PACIN <46>
-
G
@ SINGA_2DW-0005-B03
1
PR6 LM393DG_SO8
4
PC5 20K_0402_1% PC6 PD1 PR7
0.068U_0402_10V6K .1U_0402_16V7K GLZ4.3B_LL34-2 10K_0402_1%
2
2
2
2 1 RTCVREF
PR8
VIN 10K_0402_1%
3.3V Vin Detector
2
PD2
High 18.384 17.901 17.430
RLS4148_LL34-2 Low 17.728 17.257 16.976
1
PD3
BATT+ 2 1
1
RLS4148_LL34-2 PR9 PR10
68_1206_5% 68_1206_5%
PQ1
PR11 TP0610K-T1-E3_SOT23-3
2
200_0603_5%
2
CHGRTCP 1 2 N1 3 1 VS
2
1
1
PC8 PR13 1K_1206_5%
PR12 0.1U_0603_25V7K 1 2
100K_0402_1% PC7
2
2
0.22U_0603_25V7K PD4 PR14 1K_1206_5%
2
2 1 N3 1 2
<33> 51_ON# 1 2
VIN B+
PR15 RLS4148_LL34-2 PR16 1K_1206_5%
22K_0402_1% 1 2
RTC Battery
1
RTCVREF
1
PR19 PR20
PR18
200_0603_5%
- PBJ1 + VL
100K_0402_1%
1 2
2.2M_0402_5%
2 1
PR17
499K_0402_1%
PR21 PR22 PU2 G920AT24U_SOT89-3 2 1 +RTCBATT
3.3V +RTCBATT
2
560_0603_5% 560_0603_5%
2
1 2 1 2 3 2 N2
+CHGRTC OUT IN PD5 LM393DG_SO8
8
@ MAXEL_ML1220T10 RB715F_SOT323-3 PU1B
1
GND
2 5
P
PC9 PC10 <47> EN0 1 7
+
10U_0805_10V4Z 1 O
3 6 2 1 RTCVREF
<46> ACON
2
1
G
1U_0805_25V4Z
SP093MX0000
1
PR23 PR24 PC11
1
10K_0402_1% 499K_0402_1% 1000P_0402_50V7K
1
PC12 PR26
2
PC13 @ PR25 191K_0402_1%
2
3 3
1000P_0402_50V7K 1000P_0402_50V7K 66.5K_0402_1%
2
PR27
PJ3
1
PJ1 PJ2 D 47K_0402_1%
+3VALWP 2 1 +3VALW +1.1VALWP 2 1 +1.1VALW +3VLP 2 1 +3VL 2 2 1 PACIN
2 1 2 1 2 1 G
@ JUMP_43X118 @ JUMP_43X118 @ JUMP_43X39 S PQ2
3
(5A,200mils, Via NO.= 10) PJ4 (100mA,40mils ,Via NO.= 2) SSM3K7002FU_SC70-3
1
2 2 1 1
OCP(min) = 7.7A
@ JUMP_43X118
(12A,480mils, Via NO.= 24)
PJ5 PJ18 2 +5VALWP
+5VALWP 2 2 1 1 +5VALW OCP(min) = 18.7A +1.0VSP 2 2 1 1 +1.0VS
@ JUMP_43X118 @ JUMP_43X79 PQ3
(5A,200mils, Via NO.= 10) PJ7 (2.5A,100mils, Via NO.= 5) DTC115EUA_SC70-3
3
+1.5VP 2 1 +1.5V
2 1
OCP(min) = 7.9A
@ JUMP_43X118
PJ8 PJ9
PJ19 PJ20
2 1 2 2 +VGA_COREP +VGA_CORE
+VSBP 2 1 +VSB 1 1 +2.5VSP 2 2 1 1 +2.5VS 2 2 1 1
@ JUMP_43X39 @ JUMP_43X118 @ JUMP_43X39 @ JUMP_43X118

(11A,440mils ,Via NO.= 22) (1A,40mils ,Via NO.= 2) PJ21
(120mA,40mils, Via NO.= 1) 2 2 1 1
OCP(min) = 19.16A
@ JUMP_43X118
PJ11 PJ12 (20A,800mils ,Via NO.= 40) Precharge detector
PJ10
4
+0.75VSP 2 2 1 1 +0.75VS
2 1
+VDDNBP 2 2 1 1 +VDDNB
OCP(min) = 20.14A
15.97V/14.84V FOR 4
+1.8VSP 2 1 +1.8VS
@ JUMP_43X79
@ JUMP_43X79
@ JUMP_43X79 ADAPTOR
(1A,40mils, Via NO.= 2) (4A,160mils ,Via NO.= 8)
(2.5A,100mils, Via NO.= 5)
PJ13
+1.05VSP 2 2 1 1 +1.05VS Security Classification Compal Secret Data Compal Electronics, Inc.
@ JUMP_43X79 Issued Date 2008/9/25 Deciphered Date 2009/9/25 Title
(1.5A,60mils, Via NO.= 3)
SCHEMATIC,MB A6052
Size
Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401851
A B C D
A B C D
PH1 under CPU botten side :

CPU thermal protection at 95 degree C
Recovery at 56 degree C
VMB
1
PF2 PL2
Rset = 3 * Rtmh 1
PJP2
BATT_S1
15A_65V_451015MRL SMB3025500YA_2P Rhyst = (Rset* Rtml) / (3*Rtml - Rset)
1 1 1 2 1 2 BATT+
2 2
3 BATT_P3 1 2 1 2
3 +3VLP
BATT_P4 PR28 PR29
4 4 Rtmh at 95C = 6.64K, Rtml at 57C = 25.1K
1
5 BATT_P5 1K_0402_1% 47K_0402_1%
5 EC_SMDA PC14 PC15
10
11
GND 6 6
7 EC_SMCA 1000P_0402_50V7K 0.01U_0402_25V7K Rset = 3 * 6.64K = 19.92K ==> 19.6K
2
GND 7
12 GND 8 8 Rhyst = (20K * 25.1K) / (3 * 25.1K - 20K) = 9.078K ==> 9.09K
1
13 GND 9 9
PR32
1
SUYIN_200045MR009G171ZR @PD6
@ PD6 1K_0402_1%
@
PJSOT24C_SOT23-3
2
VL
3
PD8
@
19.6K_0402_1%
2
1
1
PR31
3 PC16 PR30
0.1U_0603_25V7K 19.6K_0402_1%
2
PJSOT24C_SOT23-3
2
PR37 PU3
6.49K_0402_1% 1 8
VCC TMSNS1
2 1 +3VLP
2
2
2 GND RHYST1 7
PR38 PR39 PR33
100_0402_1% 100_0402_1% <47> VS_ON 3 6 8.66K_0402_1%
2 OT1 TMSNS2 2
1
2
4 5
1
1
PR40 OT2 RHYST2 PR34
1K_0402_1% G718TM1U_SOT23-8 7.87K_0402_1%
2
1
PH1
BATT_TEMPA <31>
100K_0402_1%_NCP15WF104F03RC
2
PH2
EC_SMB_DA1 <31>
100K_0402_1%_NCP15WF104F03RC
EC_SMB_CK1 <31>
2
PQ6
TP0610K-T1-E3_SOT23-3
+VSBP
B+ 3 1 PH2 near main Battery CONN :
100K_0402_1%
0.1U_0603_25V7K BAT. thermal protection at 95 degree C

1
3 3
PR43
@ PC20
Recovery at 48 degree C
@ PC19
@PC19
2
PR45 0.22U_0603_25V7K
2
22K_0402_1%
VL 1 2
2
PR47
100K_0402_1%
PR48
1
0_0402_5% D
1 2 2 PQ7
<47,48> POK
G SSM3K7002FU_SC70-3
.1U_0402_16V7K
S
3
1
@ PC22
2
4 4

Issued Date 2008/9/25 Deciphered Date 2009/9/25 Title
SCHEMATIC,MB A6052
Size
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401851 A
A B C D
A B C D
PC163
10U_1206_25V6M PQ8
1 2 AO4407A_SO8
PQ9 P2 PQ10 PC164 PC162

1 8 90W 4407A*1
2 7
AO4407A_SO8 AO4407A_SO8 10U_1206_25V6M 10U_1206_25V6M 3 6 120W 4407A*2
8
7
1
2
1
2
8
7 P3 PR49
B+ 2 1 1 2
CHG_B+
5
6 3 3 6 0.015_2512_1% PJ22
4
VIN 5 5 1 4 2 2 1 1 PQ11
AO4407A_SO8
2 3 @ JUMP_43X79 CSIN 1 8
4
2 7
3 6
10U_1206_25V6M
10U_1206_25V6M
CSIP 5
1
1 1
1
PQ12 TP0610K-T1-E3_SOT23-3 PR51
4
3
PC23
PC24
PQ13 PR50 10_0603_5%
2
DTA144EUA_SC70-3 200K_0402_1% 3 1 1 2 DCIN
2
PC25 P3 PR54
2
1
1
2 5600P_0402_25V7K PQ14 47K_0402_1%
1
PC26 PR53 DTC115EUA_SC70-3 1 2
PR52 0.1U_0603_25V7K 100K_0402_1% VIN
2
47K_0402_1% PD10
PR55 2 FSTCHG
2
2
100K_0402_1% 2 1
1
2
1
PD12 2 1 3 PR56 PD11

1SS355_SOD323-2 SUSP# <28,31,34,49,51> 10K_0402_1% 1 2 ACOFF
1 2 6251VDD RB715F_SOT323-3
2.2U_0603_6.3V6K
1SS355_SOD323-2
1
PC27
2 PR57 PR58
1
PQ15 10K_0402_1% 200K_0402_1%
1
DTC115EUA_SC70-3 2 1 PU4 PC29 1 2 VIN
<31> FSTCHG 0.1U_0603_25V7K
2
1
100K_0402_1%
1 2 1 24 DCIN 2 1
3
VDD DCIN
1
1
2 PQ17 PQ16 PD13
PR60
G SSM3K7002FU_SC70-3 PC28 DTC115EUA_SC70-3 2 1 2
S PR59 .1U_0402_16V7K 2 23
3
150K_0402_1% ACSET ACPRN PR61 1SS355_SOD323-2

20_0603_5%
2
2
6251_EN 3 22 1 2 CSON
3
EN CSON
1
PC30 D
5
6
7
8
1
0.047U_0603_16V7K PC32 2 PACIN
4 21 1 2 CSOP 0.1U_0603_25V7K G
1
CELLS CSOP PR62 PQ19 PQ18
S
3
PC33 6800P_0402_25V7K 20_0603_5% AO4466_SO8 SSM3K7002FU_SC70-3
2 2
1 2 5 ICOMP CSIN 20 2 1
1
2
D PR63 4
2 PQ20 PC35 PR64 6.81K_0402_1% PC34 20_0603_5%
G SSM3K7002FU_SC70-3 1 2 1 2 6 19 0.1U_0603_25V7K
1 2 PL4
1
PR66 VCOMP CSIP 10U_LF919AS-100M-P3_4.5A_20% PR67
S
3
0.01U_0402_25V7K 12 47K_0402_1% PR65 0.02_1206_1% BATT+
3
2
1
PR68 PC36 1 2 7 18 LX_CHG 2.2_0603_5% 1 2CHG 1 4
22K_0402_5% @ 100P_0402_50V8J ICM PHASE
5
6
7
8
1
PACIN 1 2 1 2 2 3
<44> PACIN
10U_1206_25V6M
10U_1206_25V6M
6251VREF 8 17 DH_CHG @PR69
@ PR69
PC37 .1U_0402_16V7K VREF UGATE PR70 PC38 4.7_1206_5%
<44> ACON
PR71 2.2_0603_5% 0.1U_0603_25V7K
<31> ADP_I
1
PC39
PC40
154K_0402_1% 9 16 BST_CHG 1 2 BST_CHGA 2 1
1 2
CHLIM BOOT
1
1
PQ22 2 1 4 PQ21
<31> IREF
0.01U_0402_25V7K
DTC115EUA_SC70-3 PR72 PD14 AO4466_SO8 @PC41

@ PC41
2
8.25K_0402_1% 10 15 6251VDDP RB751V-40TE17_SOD323-2 680P_0603_50V7K
ACLIM VDDP
1
6251VREF 1 2 6251aclim
2
1
PC42
ACOFF 2 PR73 1 26251VDD

<31> ACOFF
3
2
1
120K_0402_1% 1 11 VADJ LGATE 14 DL_CHG
2
PR75 PR74
2
26.7K_0402_1% 4.7_0603_5%
2
12 13 PC43
3
1
GND PGND 4.7U_0805_6.3V6K
2
PR76 ISL6251AHAZ-T_QSOP24
15.4K_0402_1%
1 2 VADJ
<31> CHGVADJ
1
PR77
3
31.6K_0402_1% 3
VIN
2
1
PR78
309K_0402_1%
PR79
2
10K_0402_1%
1 2
ADP_V <31>
CP mode
1
Vaclim=2.39*(Rb//152K/(Rt//152K+Rb//152K))
1
@ PD15 PR80
Iinput=(1/PR49)((0.05*Vaclm)/2.39+0.05) GLZ4.3B_LL34-2 47K_0402_1% PC44
where Vaclm=1.09986V, Iinput=3.65A (75W) Iin = 2.512 ADP_I .1U_0402_16V7K
2
2
Vaclm=0.7717V, Iinput=4.41A
Vaclm=0.4204V, Iinput=5.88A
(120W) Iin = 3.35 ADP_I
Vin = 7.57 ADP_V
CC=0.25A~3A CHGVADJ=(Vcell-4)*9.445
IREF=0.9133*Icharge Vcell CHGVADJ
Iada=0~3.421A(65W) CP=3.15A PR49=0.02, PR72=75k, PR75=20k
IREF=0.228V~2.74V 4V 0V
Iada=0~3.947A(75W) CP=3.63A PR49=0.02, PR72=24k, PR75=20k
VCHLIM need over 95mV 4.2V 1.898V
4
Iada=0~4.737A(90W) CP=4.36A PR49=0.015, PR72=53.6k, PR75=20k 4
4.35V 3.315V
Iada=0~6.316A(120W) CP=5.81A PR49=0.015, PR72=8.25k, PR75=26.7k
CP= 92%*Iada
CELLS VDD GND Float
CELL number 4 3 2
SCHEMATIC,MB A6052
A B C D
5 4 3 2 1
AO4712 Rds(on) = 15/18

2VREF_51125
0.22U_0603_10V7K
Ipeak = 5A Ipeak = 5A
Imax = 3.5A Imax = 3.5A
1
D D
F = 305K F = 245K
PC45
2
PR81 PR82
13K_0402_1% 30K_0402_1%
1 2 1 2
PR83 PR84
B++
20K_0402_1% 19.1K_0402_1%
1 2 1 2 B++
PJ24
ENTRIP2
B+ 2 2 1 1 +3VLP
ENTRIP1
4.7U_0805_25V6-K
4.7U_0805_25V6-K
2200P_0402_50V7K
@ JUMP_43X118 PR85 PR86
1
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
150K_0402_1% 150K_0402_1%
1
PC46
PC47
PC48
4.7U_0805_10V6K
1 2 1 2
5
6
7
8
PC49
PC50
PC51
PC52
2
8
7
6
5
1
PQ23
AO4466_SO8
1
PQ24 PU5
C AO4466_SO8 4 C
ENTRIP2
REF
FB2
FB1
ENTRIP1
TONSEL
4
25 P PAD
POK <45,48>
3
2
1
7 24
1
2
3
VO2 VO1
PL6 PC53 8 23 PC54 PL7
4.7UH_SIL104R-4R7PF_5.7A_30% .1U_0402_16V7K PR87 VREG3 PGOOD PR88 .1U_0402_16V7K 4.7UH_SIL104R-4R7PF_5.7A_30%
1 2 1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2 1 2
+3VALWP 0_0603_5% BOOT2 BOOT1 0_0603_5%
UG_3V 10 21 UG_5V +5VALWP
UGATE2 UGATE1
8
7
6
5
5
6
7
8
1
1
PQ25 LX_3V 11 20 LX_5V
PHASE2 PHASE1
220U_6.3VM_R15
@ PR89 AO4712_SO8 @ PR90
220U_6.3VM_R15
1 4.7_1206_5% LG_3V 12 19 LG_5V PQ26 4.7_1206_5% 1

LGATE2 LGATE1 AO4712_SO8
SKIPSEL
+ +
PC55
PC56
4 4
VREG5
1 2
1 2
GND
VIN
@ PC57 RT8205EGQW_WQFN24_4X4
NC
EN
2 680P_0603_50V7K @ PC58 2
<44> EN0 680P_0603_50V7K
2
1
2
3
13
14
15
16
17
18
3
2
1
2
PR91
499K_0402_1%
B+ 1 2
1
100K_0402_1%
1U_0402_6.3V6K
1
PR92
@ PC59
B Total capacitor 220uF 2 1 2 VL B
1
ESR = 15mohm ENTRIP1 ENTRIP2
PC60
4.7U_0805_10V6K
PR93
2
@ 0_0402_5%
Total capacitor 220uF
2
ESR = 15mohm
B++
1
1
D D
0.1U_0603_25V7K
PQ27 2 2 PQ28
SSM3K7002FU_SC70-3 G G SSM3K7002FU_SC70-3
2
PC61
S S
3
2VREF_51125
VL 2 1
PR94
100K_0402_1%
<45> VS_ON
1
VS 1 2 2 PQ29
G SSM3K7002FU_SC70-3
PR95 S
3
A A
1
100K_0402_1%
PR96
42.2K_0402_1%
2

SCHEMATIC,MB A6052
5 4 3 2 1
5 4 3 2 1
PJ25
1.1V_B+ 2 1 B+
2 1
4.7U_0805_25V6-K
4.7U_0805_25V6-K
@ JUMP_43X118
Ipeak = 12A
1
PC62
PC63
Imax = 8.4A
2
F = 315K
D D
PR97
255K_0402_1% 4
PR98
1 2
PR99 PQ30
0_0402_5% 0_0603_5% TPCA8030-H_SOP-ADV8-5 ESR = 5mohm
<45,47> POK 1 2 1 2
3
2
1
1
PL9
15
14
PC65
1
@ PC64 PU6 1UH_FDUE1040D-1R0M-P3_21.3A_20%
.1U_0402_16V7K BST_1.1V 1 2 1 2
NC
EN/DEM
BOOT
+1.1VALWP
2 2 TON UGATE 13 DH_1.1V 0.1U_0603_25V7K (+1.1VALW, +1.1VS, NB_CORE)
4.7_1206_5%
PR101 3 12 LX_1.1V
VOUT PHASE
@ PR100
100_0603_1% 1
220U_6.3VM_R15
+5VALW 1 2 4 11 1 2 +5VALW PQ31
VDD CS
PC66
PR102 +
2
5 10 6.19K_0402_1%
FB VDDP
1
1
DL_1.1V 2
6 PGOOD LGATE 9 4
PGND
680P_0603_50V7K
PC67
GND
@ PC68
4.7U_0603_6.3V6K @ PC70
2
2
47P_0402_50V8J PC69
1 2 RT8209BGQW_WQFN14_3P5X3P5 4.7U_0805_10V6K TPCA8028-H_SOP-ADVANCE8-5
3
2
1
PR103
4.75K_0402_1%
1 2
C C
1
PR104
10K_0402_1%
2
PJ26
1.5V_B+ 2 1 B+
2 1
4.7U_0805_25V6-K
4.7U_0805_25V6-K
@ JUMP_43X118
1
PC71
PC72
Ipeak = 11A
5
Imax = 7.7A
2
F = 315K
PR105
255K_0402_1% 4
1 2
PR107
PR106
0_0603_5% PQ32
<31,34> SYSON 1 2 1 2 TPCA8030-H_SOP-ADV8-5 ESR = 2.73mohm
3
2
1
0_0402_5%
1
PL11
15
14
PC74
1
B @ PC73 PU7 1UH_FDUE1040D-1R0M-P3_21.3A_20% B

.1U_0402_16V7K BST_1.5V 1 2 1 2
NC
EN/DEM
BOOT
+1.5VP
2
2 13 DH_1.5V 0.1U_0603_25V7K
TON UGATE
1
PR109 3 12 LX_1.5V @ PR108
VOUT PHASE
5
100_0603_1% 4.7_1206_5% 1
220U_6.3VM_R15
+5VALW 1 2 4 11 1 2 +5VALW PQ33
VDD CS +
PC75
PR110
2
5 10 6.19K_0402_1%
FB VDDP
1
1
DL_1.5V 2
6 PGOOD LGATE 9 4
PGND
680P_0603_50V7K
PC76
GND
@ PC77
4.7U_0603_6.3V6K @ PC79
2
2
47P_0402_50V8J PC78
1 2 RT8209BGQW_WQFN14_3P5X3P5 4.7U_0805_10V6K TPCA8028-H_SOP-ADVANCE8-5
7
3
2
1
PR111 PU8
10K_0402_1% APL5508-25DC-TRL_SOT89-3
PJ14
1 2 +3VS
1 1 2 2 2 IN OUT 3 +2.5VSP
1
@ JUMP_43X39
PR112 GND
1
10K_0402_1%
PC80 1 PC81
2
1U_0603_10V6K 4.7U_0805_6.3V6K
2
A A

SCHEMATIC,MB A6052
5 4 3 2 1
5 4 3 2 1
D D
+1.5V
1
VDDR_SW VDDR
PJ15
1
@ JUMP_43X79
HIGH 1.05V PR114
2
200K_0402_1%
1 2 SUSP# <28,31,34,46,51>
2
LOW 0.9V
2
1
PC84 +5VALW 316K_0402_1%
1
4.7U_0805_6.3V6K PR116
PR193 PR118 PC83
2
12.4K_0402_1% PU9 402K_0402_1% PU10 0.22U_0402_10V4Z
2
1 6 +5VALW 2 1 1 10
2
VIN VCNTL FB EN/SYNC

SSM3K7002FU_SC70-3
@ PR194
1U_0603_6.3V6M
10K_0402_1% PQ48 2 5 PC85 2 9 PL18
GND NC GND GND
1
1
D
PC82
.1U_0402_16V7K 2.2UH_FMJ-0630T-2R2 HF_8A_20%
2
<22> VDDR_SW 2 3 REFEN NC 7 PJ16 1 2 3 SW SW 8 1 2 +1.8VSP

G +5VALW
2
1
22U_0805_6.3V6M
22U_0805_6.3V6M
S PR113 4 8 1 2 4 7
3
VOUT NC 1 2 IN IN
B340A_SMA2
PR195 4.42K_0402_1%
1
PD16
PC88
PC89
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_25V6
10K_0402_1% 9 1 2 5 6 PR165
2
GND @ JUMP_43X79 PR166 BS POK 4.7_1206_5%
2
PC127
PC128
PC129
RT9173DPSP_SO8 0_0402_5% 11 @
2
1 2
2
TP
.1U_0402_16V7K
C C
2
1
PR115 +1.05VSP MP2121DQ-LF-Z_QFN10_3X3
1
1
D
PC86
0_0402_5% PR117 PC91

1 2 2 10.5K_0402_1% 680P_0603_50V7K
<34> VR_ON#
2
1
G
2
1
S PQ4 PC87
3
@ PC90 SSM3K7002FU_SC70-3 10U_0805_6.3V6M

2
.1U_0402_16V7K
2
+1.5V
1
+1.5V +5VALW PJ17
1
@ JUMP_43X79
1U_0603_6.3V6M
1
2
1
PC132
@ PJ23 PU11
1
2
JUMP_43X79 1 6 +3VALW
VIN VCNTL
2
2
2 GND NC 5
1
B PU14 PC92 B
2
1
APL5930KAI-TRG_SO8 4.7U_0805_6.3V6K 3 7 PC93
PR119 REFEN NC 1U_0603_6.3V6M
6
2
VCNTL
1
PC133 5 3 +1.0VSP 1K_0402_1% 4 8

4.7U_0805_6.3V6K VIN VOUT VOUT NC
9 VIN VOUT 4
1
9
2
2
GND
1
1
0.01U_0402_25V7K
8 PR168
EN
PC134
PR169 7 2 1.82K_0402_1% PC135 RT9173DPSP_SO8

GND
<43> PCIE_OK POK FB
.1U_0402_16V7K
0_0402_5% 22U_0805_6.3V6M
2
1
1 2 PR121 +0.75VSP
<28,31,34,46,51> SUSP#
2
1
D
PC94
0_0402_5% PR120
1
1
1 2 2 1K_0402_1%
<34> SUSP
1
1
@ PC136 G
2
1
.1U_0402_16V7K PR170 S PQ34 PC95
2
2
7.32K_0402_1% @ PC96 SSM3K7002FU_SC70-3 10U_0805_6.3V6M
2
.1U_0402_16V7K
2
2
Madison / Park M96 / M92

PCIE : 1.0V PCIE : 1.1V
PR170 = 7.32K PR170 = 4.75K
A A

SCHEMATIC,MB A6052
5 4 3 2 1
A B C D E
CPU_B+ PL12
HCB4532KF-800T90_1812
PC97 1 2 B+
10U_1206_25V6M
33P_0402_50V8J
68U_25V_M_R0.44
68U_25V_M_R0.44
68U_25V_M_R0.44
68U_25V_M_R0.44
2 1 1 1 1 1
5
6
7
8
PC99
1
+ + + +
PC101
PC98
@ PC160
@ PC161
2 1 2 1
2
PR122 PC100 2 2 2 2
44.2K_0402_1% 1000P_0402_50V7K UGATE_NB 4 PQ35
PR123 AO4466_SO8
1 2_0603_5% 1
+5VS 1 2 PC102 PL13

1000P_0402_50V7K 4.7U_LF919AS-4R7M-P3_5.2A_20%
3
2
1
2 1 PHASE_NB 1 2 +VDDNBP
PR124
5
6
7
8
1
PC103 PR126 2.2_0603_1%
0.1U_0603_16V7K 22K_0402_1% BOOT_NB 1 2 1 2 @ PR125 1
Ipeak = 36A
2 1 4.7_1206_5% Imax = 25.2A
2
PR187 PC104 + PC105
10_0402_1% 0.22U_0603_10V7K PQ36 220U_D2_4VM F = 300K
1 2
1 2 +VDDNB LGATE_NB 4 AO4712_SO8
PR128 @ PC106 2
CPU_B+ 1 2
0_0402_5% 680P_0603_50V7K
PR127 2 1 CPU_VDDNB_RUN_FB_H <7>
2
2_0603_5% PR129
3
2
1
+5VS +3VS 11K_0402_1%
2 1 PHASE_NB ESR = 2.22mohm
LGATE_NB
1
PC107 PR188 CPU_B+
0.1U_0603_25V7K PHASE_NB 10_0402_1%
1
1
1 2
2
1
PR130 UGATE_NB
10U_1206_25V6M
10U_1206_25V6M
0_0402_5% @PR131
@ PR131
1
5
PR132 105K_0402_1% 2 1 CPU_VDDNB_RUN_FB_L <7>
105K_0402_1% PR133 PQ37
2
1
PC108
PC109
0_0402_5%
2
@ PR134
10K_0402_1%
2
2
1
UGATE0 4
PR135
48
47
46
45
44
43
42
41
40
39
38
37
<31,34> VGATE @ 105K_0402_1% PU12
2 PHASE0 PL14 2
FB_NB
COMP_NB
FSET_NB
VSEN_NB
OCSET_NB
LGATE_NB
VIN
VCC
RTN_NB
PGND_NB
PHASE_NB
UGATE_NB
PR137 TPCA8030-H_SOP-ADV8-5 0.36UH_PCMC104T-R36MN1R17_30A_20%
2
3
2
1
0_0603_5%
1 2 1 36 BOOT_NB BOOT0 1 2 1 2 1 4 +CPU_CORE
<7,20> H_PWRGD @PR136
@ PR136 0_0402_5% OFS/VFIXEN BOOT_NB
BOOT0 PC110
TPCA8028-H_SOP-ADVANCE8-5
2 PGOOD BOOT0 35 2 3
5
1 2 0.22U_0603_10V7K
1
<20> H_PWRGD_L PR138 0_0402_5% ISL6265_PWROK 3 34 UGATE0
PWROK UGATE0
2
@ PR139
<7> CPU_SVD 2 1 4 33 PHASE0 4.7_1206_5% PR141
<7> CPU_SVC SVD PHASE0
PQ38
@ PQ39
PR140 16.5K_0402_1%
0_0402_5%2 1 5 32 4 4
1 2
<31,34> VR_ON PR142 SVC PGND0 +5VS
1
PR143 PR144 0_0402_5% 6 31 LGATE0 @ PC111 PC112
21.5K_0402_1% 95.3K_0402_1% ENABLE ISL6265AHRTZ-T_TQFN48_6X6 LGATE0 680P_0603_50V7K 2 1
2 1 2 1 7 30
3
2
1
3
2
1
2
RBIAS PVCC 0.1U_0603_16V7K
8 29 LGATE1
OCSET LGATE1
1
PC113 2 1
9 28 1U_0603_10V6K
VDIFF0 PGND1 LGATE0 PR145
ISN0
ISP0
10 27 PHASE1 4.02K_0402_1%
FB0 PHASE1
11 26 UGATE1
COMP0 UGATE1 CPU_B+
12 25 BOOT1
VW0 BOOT1
COMP1
VDIFF1
VSEN0
VSEN1
RTN0
RTN1
ISN0
ISN1
ISP0
VW1
ISP1
FB1
10U_1206_25V6M
10U_1206_25V6M
TP
5
PR189 PQ40
13
14
15
16
17
18
19
20
21
22
23
24
49
1
PC114
PC115
+CPU_CORE 2 1
3 ISP0 3
10_0402_1% PR146 ISN0
2
ISN1
ISP1
0_0402_5% UGATE1 4
2 1 VSEN0
<7> CPU_VDD0_RUN_FB_H 0_0402_5%
2 PR147 1 RTN0 PHASE1 PL15
<7> CPU_VDD0_RUN_FB_L PR190 PR149 TPCA8030-H_SOP-ADV8-5 0.36UH_PCMC104T-R36MN1R17_30A_20%
3
2
1
10_0402_1% 0_0603_5%
2 1 BOOT1 1 2 1 2 1 4 +CPU_CORE
1RTN1 PC116
@ TPCA8028-H_SOP-ADVANCE8-5
2 2 3
5
<7> CPU_VDD1_RUN_FB_L @ PR191
@PR191 0.22U_0603_10V7K
2
1
1K_0402_1%
10_0402_1% PR148 0_0402_5%
2
PR150
2 1 @ PR151
4.7_1206_5% PR152
PQ41
PQ42
PR192 16.5K_0402_1%
+CPU_CORE 2 1 4 4
1
1 2
+1.5V
1
10_0402_1% PR153 @ PC117 PC118
0_0402_5% 680P_0603_50V7K 2 1
<7> CPU_VDD1_RUN_FB_H 2 1 VSEN1
3
2
1
3
2
1
2
0.1U_0603_16V7K
DIFF_0 VW0 DIFF_1 VW1 2 1
PR155 PC119 @ PR156 @

@PR156 @PC122
PC122 LGATE1 PR154
ISN1
ISP1
255_0402_1% 4700P_0402_25V7K 255_0402_1% 4700P_0402_25V7K 4.02K_0402_1%
2 1 2 1 FB_0 2 1 COMP0 2 1 2 1 2 1 FB_1 2 1 COMP1 2 1
PC120 PC121 @ PC123 @ PC124

180P_0402_50V8J 1000P_0402_50V7K 180P_0402_50V8J 1000P_0402_50V7K
4 PR157 PR159 @ PR160 @PR162

@ PR162 4
1K_0402_5% PR158 PC125 6.81K_0402_1% 1K_0402_5% @PR161
@ PR161 @ PC126 6.81K_0402_1%
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1
54.9K_0402_1% 1200P_0402_50V7K 54.9K_0402_1% 1200P_0402_50V7K

1
PR163 PR164
@ 36.5K_0402_1% @ 36.5K_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
SCHEMATIC,MB A6052
2
A B C D E
5 4 3 2 1
B+ 1 2 B+_core
PL16 LX_VCORE
HCB4532KF-800T90_1812
10U_1206_25VAK
4.7U_0805_25V6-K
10U_1206_25VAK
DH_VCORE
1
PC139
PC137
PC138
1 2 1 2
BST_VCORE
2
PR171 PC143
0_0603_5% 0.1U_0603_25V7K
D
Ipeak =20A D
+5VALW
Imax = 14A
1
F = 231K
5
PR172
0_0603_5% PQ43
27138_VCC
16
15
1
2
8
1
PU15
PR173 4
PHASE
BOOT
UG
GND
PGOOD
4.7_0603_5% ESR = 3.33mohm
3 VIN PVCC 14 1 2 PC146
TPCA8030-H_SOP-ADV8-5
3
2
1
2.2U_0603_6.3V6K
PL17
2.2U_0603_6.3V6K
PC147
7138_VCC 4 13 DL_VCORE +VGA_COREP
VCC LG 0.56U_PCMC104T-R56MN_25A_20%
1
1 2
APW7138NITRL_SSOP16
1
12
2
PGND
390U_2.5V_M
@ PR174
10U_1206_25VAK
10U_1206_25VAK
4.7_1206_5% 1
PR175
PQ45
PC148
1
1 2 5 11 ISEN_VCORE 1 2 +
1 2
EN ISEN
2
<28,31,34,46,49> SUSP#
0_0402_5%
PQ44
@ PC149
PC150
4 4 @
1
PR177
0_0402_5% .1U_0402_16V7K PR176 @ PC153
FSET
2
2
PC152
5.36K_0402_1%
NC
VO
FB
680P_0603_50V7K
2
2
C C
10
3
2
1
3
2
1
1
PR178
57.6K_0402_1%
2 1 +VGA_CORE
49.9K_0402_1%
1
10_0402_1%
1
@ PR179
PR180
@ PC155
0.01U_0402_25V7K
2
2
2
1
1
@ PC154
2200P_0402_25V7K
22P_0402_50V8J @PC157
@ PC157
2
2
1
1000P_0402_50V7K
@ PC156
2
4.22K_0402_1%
2
2
PR181
PR182 PR183
5.9K_0402_1% 28K_0402_1%
B B
VFB(0.6)=Vout*Rbottom/(Rtop+Rbottom)
1
1
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
PR185 PR186
1
D 10K_0402_1% D 10K_0402_1%
Madison/Park M96/M92
PQ46
PQ47
2 1 2 2 1 2
SEL1 SEL0 voltage voltage G G
1
S VGA_PWRSEL1 <36> S VGA_PWRSEL0 <36>

3
3
1
1
PR184 PC158 PC159
L L 1.2 1.2 4.22K_0402_1% 2 .1U_0402_16V7K .1U_0402_16V7K
2
2
L H 1.12 1.0
H L 0.95 0.95
H H 0.9 0.9
FSW=1/(75E-12*57.6K)=231.48KHz
Madison M96
Park M92
A A
PR183 = 28K PR183 = 12K
Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2008/10/23 Deciphered Date 2009/10/23
SCHEMATIC,MB A6052
5 4 3 2 1
5 4 3 2 1
PIR (Product Improve Record)

NALAE LA-6052P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1 TO 0.2
NO DATE PAGE MODIFICATION LIST
----------------------------------------------------------------------------------------------------------------------------
1 2009/12/14 33 Change JLEDB pin define as customer request
2 2009/12/14 25,28,30 Delete JODDB, JBT and JUSBB support pin
3 2009/12/14 33 Change JPOWER Pin2 from GND to NC
4 2009/12/15 28 Add R95 at JWLAN Pin5 for BT/WLAN combo Mini Card
5 2009/12/15 25,30 Change U11, U25 P/N from SA00002XX00 to SA000033H00
D D
6 2009/12/15 28 Reverse JBT pin definition
7 2009/12/16 27 Change CC2 from 0.1u to 100P (SE071101J80), and add BOM structure @
8 2009/12/17 33 Cgange JPOWER footprint to ACES_87151-1207_12P (ZIF_上接點)
9 2009/12/17 33 Cgange JTPB footprint to P-TWO_161011-04021_4P-T (NO ZIF), and reverse pin definition
10 2009/12/17 33 Cgange JLEDB footprint to ACES_85201-1205N_12P (ZIF_上接點)
11 2009/12/17 25 Cgange JUSBB footprint to ACES_85201-20051_20P (ZIF_上接點)
12 2009/12/17 33 Change H36, H37 footprint from H_3P3 to H_3P8
C C
B B
A A

SCHEMATIC,MB A6052
Size
Document Number Rev
A
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) for Power Circuit

Page# Item Title Solution Description
DVT : modification from EVT
P48 change voltage divider to less than 10K change PR104, PR111, PR112 to 10K; PR103 to 4.75K
P48 change 1.1V, 1.5V OCP value change PR102, PR110 to 6.19K
P49 enlarge output cap change PC88, PC89 to 22uF(SE000000I10)
D D
P50 don't use NIPPON cap change PC98, PC99 to SF000000S80
P50 pull high RTN1 1.5V change PR150 to mount
P51 APW7138 pin6 is NC change PR179, PC154, PC156 to unmount
P47 choke need to meet thermal module height change PL6, PL7 to SH000006380
P46 change system power from 90W to 120W change PR72 to 8.25K, PR75 to 26.7K; PQ11 to mount
P50 production line request change PC98, PC99 to 68uF; add PC160, PC161 68uF
P46 EMI request for ISN issue add PC162, PC163, PC164 10uF 1206
P49 mount snubber circuit mount PR165, PC91
P45 OTP setting common change PR30 and PR31 to 19.6K; PR34 to 7.87K; PR33 to 8.66K
P49 change IC to low cost change PU9 and PU11 to RT9173
P49 change VDDR(1.05V) circuit to switchable add PR193, PR194, PR195 & PQ48
C C
B B
A A

SCHEMATIC,MB A6052
Size
Document Number Rev
A
5 4 3 2 1

Compal confidential NALAE LA-6052P Schematics

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Compal confidential NALAE LA-6052P Schematics

Uploaded by

Copyright:

Available Formats

A B C D E

NALAE LA-6052P Schematics Document

Mobile AMD S1G4/ RS880M / SB820M

2009-11-27 Rev. 0.2

Security Classification Compal Secret Data Compal Electronics, Inc.

Compal Confidential Thermal Sensor Fan Control AMD S1G4 CPU

File Name : LA-6052P page 5,6,7,8

1 Hyper Transport Link 2.6GHz 1

16X16 PCIeMini Card WLAN

CRT USB Port 8 page 28

LCD Conn. RS880M PCIe 4x

SATA port 0 SATA HDD

Audio & USB/B Int.KBD SPI ROM Int.

Security Classification Compal Secret Data Compal Electronics, Inc.

DESIGN CURRENT 0.1A +3VL

DESIGN CURRENT 300mA +2.5VS

DESIGN CURRENT 1A +0.75VS

DESIGN CURRENT 1.5A +1.05VS

DESIGN CURRENT 2.5A +1.0VS

A DESIGN CURRENT 20A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Voltage Rails Symbol Note :

Security Classification Compal Secret Data Compal Electronics, Inc.

250 mil VLDT CAP. Near CPU Socket

10U_0805_10V4Z 10U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J

H_CADIP0 E3 AD1 H_CADOP0

<11> H_CLKIP0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 H_CLKOP0 <11>

<11> H_CTLIP0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 H_CTLOP0 <11>

< FAN Control Circuit : Vout = 1.6 x Vset >

VOUT GND @ ACES_85204-0300N

Security Classification Compal Secret Data Compal Electronics, Inc.

+MCH_REF DDR_B_D1 MB_DATA0 MA_DATA0 DDR_A_D1

1 1 DDR_B_D3 B14 G14 DDR_A_D3

DDR_B_D8 MB_DATA7 MA_DATA7 DDR_A_D8

Security Classification Compal Secret Data Compal Electronics, Inc.

R27 1 2 510_0402_5% CPU_TEST25L

R30 2 1 1K_0402_5% CPU_TEST18

R31 2 1 1K_0402_5% CPU_TEST19

R32 2 1 1K_0402_5% CPU_TEST20

R33 2 1 1K_0402_5% CPU_TEST21

R34 2 1 1K_0402_5% CPU_TEST22

R265 2 1 1K_0402_5% CPU_TEST23

R35 2 1 1K_0402_5% CPU_TEST24

R37 1 2 220_0402_5% CPU_TDI

+CPU_CORE JCPUE +CPU_CORE

Near CPU Socket Right side @ 1 D25 U12

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

PCIE I/F GFX

AE3 GPP_RX0P GPP_TX0P AC1

<20> SB_RX0P AA8 AD7 SB_TX0P_C C133 1 2 0.1U_0402_16V7K

H_CADOP5 P22 J25 H_CADIP5

<5> H_CLKOP0 T22 HT_RXCLK0P HT_TXCLK0P H24 H_CLKIP0 <5>

0718 Place within 1" 0718 Place within 1"

Security Classification Compal Secret Data Compal Electronics, Inc.

+3VS AVDD=100mA U3C

<16> CLK_SBLINK_BCLK V4 GPPSB_REFCLKP(SB_REFCLKP)

+1.8VS R68 1 2 300_0402_5% NB_PWRGD

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

A25 VSSAHT1 VSSAPCIE1 A2

Security Classification Compal Secret Data Compal Electronics, Inc.