Professional Documents
Culture Documents
2
Compal Confidential 2
2008/11/20
3
Rev:1.0 3
4 4
Compal Confidential
Project Code: JAW91
File Name : LA-4011P Thermal Sensor Clock Generator AMD S1 CPU DDR-2 DDR2-SO-DIMM X2
Athlon x2 TK-XX
ADM1032ARM ICS951462 page 8,9
1 1
page 4,5,6,7
page 6 page 13 Daul Channel DDR-2
HT 16x16 800MHZ
CRT
page 14 ATI-RS690M(C)
LCD CONN BGA465
page 14 page 10,11,12
USB 2.0
USB conn x 4
page 28
2 Realtek Express Card Mini Card1 2
Int. KBD
Power Circuit DC/DC Power OK CKT. page 27
page 31~38 page 29 Touch Pad
CONN.page 27 SPI BIOS
page 26
4 4
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S4/ S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) ON ON ON S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. ON ON ON
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
+1.2V_HT 1.2V switched power rail ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+0.9V 0.9V switched power rail for DDR terminator ON ON OFF
+1.2VALW 1.2V always on power rail ON ON ON
+1.5VS 1.5V switched power rail ON OFF OFF Board ID Table for AD channel
+1.8VS 1.8V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+1.8V 1.8V power rail for DDR ON ON OFF Ra / Rc 100K +/- 5%
+3VALW 3.3V always on power rail ON ON ON Board ID Rb / Rd V AD_BID min V AD_BID typ V AD_BID max
+3V 3.3V power rail ON ON OFF 0 0 0 V 0 V 0 V
+3VS 3.3V switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+5VALW 5V always on power rail ON ON ON 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+5VS 5V switched power rail ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+RTCVCC RTC power ON ON ON 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V
2 2
4 4
H_CADIP[0..15] H_CADOP[0..15]
<10> H_CADIP[0..15] H_CADOP[0..15] <10>
H_CADIN[0..15] H_CADON[0..15]
<10> H_CADIN[0..15] H_CADON[0..15] <10>
+1.2V_HT
CPU1A
D4 VLDT_A3 VLDT_B3 AE5 1 2
D3 AE4 C394 4.7U_0805_6.3V6K~N
VLDT_A2 VLDT_B2
D2 VLDT_A1 VLDT_B1 AE3
D1 VLDT_A0 VLDT_B0 AE2
H_CADIP15 N5 T4 H_CADOP15
H_CADIN15 L0_CADIN_H15 L0_CADOUT_H15 H_CADON15
P5 L0_CADIN_L15 L0_CADOUT_L15 T3
H_CADIP14 M3 V5 H_CADOP14
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 L0_CADIN_L14 L0_CADOUT_L14 U5
H_CADIP13 L5 V4 H_CADOP13
H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
H_CADIP12 K3 Y5 H_CADOP12
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12
K4 L0_CADIN_L12 L0_CADOUT_L12 W5
H_CADIP11 H3 AB5 H_CADOP11
H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11
H4 L0_CADIN_L11 L0_CADOUT_L11 AA5
H_CADIP10 G5 AB4 H_CADOP10
H_CADIN10 L0_CADIN_H10 L0_CADOUT_H10 H_CADON10
H5 L0_CADIN_L10 L0_CADOUT_L10 AB3
H_CADIP9 F3 AD5 H_CADOP9
H_CADIN9 L0_CADIN_H9 L0_CADOUT_H9 H_CADON9
F4 L0_CADIN_L9 L0_CADOUT_L9 AC5
H_CADIP8 E5 AD4 H_CADOP8
H_CADIN8 L0_CADIN_H8 L0_CADOUT_H8 H_CADON8
F5 L0_CADIN_L8 L0_CADOUT_L8 AD3
H_CADIP7 N3 T1 H_CADOP7
H_CADIN7 L0_CADIN_H7 L0_CADOUT_H7 H_CADON7
N2 L0_CADIN_L7 L0_CADOUT_L7 R1
HTT Interface
H_CADIP6 L1 U2 H_CADOP6
C H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6 C
M1 L0_CADIN_L6 L0_CADOUT_L6 U3
H_CADIP5 L3 V1 H_CADOP5
H_CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5
L2 L0_CADIN_L5 L0_CADOUT_L5 U1
H_CADIP4 J1 W2 H_CADOP4
H_CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4
K1 L0_CADIN_L4 L0_CADOUT_L4 W3
H_CADIP3 G1 AA2 H_CADOP3
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
H_CADIP2 G3 AB1 H_CADOP2
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP0 E3 AD1 H_CADOP0
H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CLKIP1 J5 Y4 H_CLKOP1
<10> H_CLKIP1 L0_CLKIN_H1 L0_CLKOUT_H1 H_CLKOP1 <10>
H_CLKIN1 K5 Y3 H_CLKON1
<10> H_CLKIN1 L0_CLKIN_L1 L0_CLKOUT_L1 H_CLKON1 <10>
H_CLKIP0 J3 Y1 H_CLKOP0
<10> H_CLKIP0 L0_CLKIN_H0 L0_CLKOUT_H0 H_CLKOP0 <10>
H_CLKIN0 J2 W1 H_CLKON0
<10> H_CLKIN0 L0_CLKIN_L0 L0_CLKOUT_L0 H_CLKON0 <10>
+1.2V_HT
R236 1 2 51_0402_1% P3 T5
R235 1 L0_CTLIN_H1 L0_CTLOUT_H1
2 51_0402_1% P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5
H_CTLIP0 N1 R2 H_CTLOP0
<10>
<10>
H_CTLIP0
H_CTLIN0
H_CTLIN0 P1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLOUT_H0
L0_CTLOUT_L0 R3 H_CTLON0
H_CTLOP0 <10>
H_CTLON0 <10>
FAN1 Control and Tachometer +5VS
Athlon 64 S1
1
Processor Socket
D3
2006-10-17 Change from 49.9 1% to 51 1% 1SS355_SOD323 @
B @ B
2
2 1
D14 1N4148_SOT23
+1.2V_HT C424
10U_0805_10V4Z~N
2 1
+5VS
C113
1000P_0402_50V7K~N 1 2
2 1 C410 10U_0805_10V4Z~N
C431
C428
0.22U_0603_10V7K C430
0.22U_0603_10V7K C426
180P_0402_50V8J~N C427
180P_0402_50V8J~N C429
1 1 1 1 1 1 U20
1 VEN GND 8
2 VIN GND 7
4.7U_0805_6.3V6K~N
4.7U_0805_6.3V6K~N
FAN1_POWER 3 6
2 2 2 2 2 2 EN_DFAN1 VO GND
<26> EN_DFAN1 4 VSET GND 5
G993P1UF_SOP8
+3VS
40mil JFAN1
1
1
R38 2
10K_0402_5% 3
4 G
5 G
2
MOLEX_53398-0371~N
<26> FAN_SPEED1
CONN@
2 FAN1
C114
A A
0.01U_0402_16V7K
1
DDRII Cmd/Ctrl//Clk
<8> DDR_CS3_DIMMA# V19 MA0_CS_L3 MA0_CLK_H2 Y16 DDR_A_CLK2 <8> AE20 MB_DATA42 MA_DATA42 AA18
DDR_CS2_DIMMA# J22 AA16 DDR_A_CLK#2 DDR_B_D41 AD22 AA20 DDR_A_D41
<8> DDR_CS2_DIMMA# MA0_CS_L2 MA0_CLK_L2 DDR_A_CLK#2 <8> MB_DATA41 MA_DATA41
DDR_CS1_DIMMA# V22 E16 DDR_A_CLK1 DDR_B_D40 AC22 Y20 DDR_A_D40
<8> DDR_CS1_DIMMA# MA0_CS_L1 MA0_CLK_H1 DDR_A_CLK1 <8> MB_DATA40 MA_DATA40
DDR_CS0_DIMMA# T19 F16 DDR_A_CLK#1 DDR_B_D39 AE25 AA22 DDR_A_D39
<8> DDR_CS0_DIMMA# DDR_A_CLK#1 <8>
2
DDRII Data
DDR_A_MA11 L20 L25 DDR_B_MA11 DDR_B_D23 C24 C23 DDR_A_D23
DDR_A_MA10 MA_ADD11 MB_ADD11 DDR_B_MA10 DDR_B_D22 MB_DATA23 MA_DATA23 DDR_A_D22
R19 MA_ADD10 MB_ADD10 U25 B24 MB_DATA22 MA_DATA22 B22
DDR_A_MA9 L19 L24 DDR_B_MA9 DDR_B_D21 C20 F18 DDR_A_D21
DDR_A_MA8 MA_ADD9 MB_ADD9 DDR_B_MA8 DDR_B_D20 MB_DATA21 MA_DATA21 DDR_A_D20
L22 MA_ADD8 MB_ADD8 M26 B20 MB_DATA20 MA_DATA20 E18
DDR_A_MA7 L21 L26 DDR_B_MA7 DDR_B_D19 C25 E20 DDR_A_D19
DDR_A_MA6 MA_ADD7 MB_ADD7 DDR_B_MA6 DDR_B_D18 MB_DATA19 MA_DATA19 DDR_A_D18
M19 MA_ADD6 MB_ADD6 N23 D24 MB_DATA18 MA_DATA18 D22
DDR_A_MA5 M20 N24 DDR_B_MA5 DDR_B_D17 A21 C19 DDR_A_D17
3 DDR_A_MA4 MA_ADD5 MB_ADD5 DDR_B_MA4 DDR_B_D16 MB_DATA17 MA_DATA17 DDR_A_D16 3
M24 MA_ADD4 MB_ADD4 N25 D20 MB_DATA16 MA_DATA16 G18
DDR_A_MA3 M22 N26 DDR_B_MA3 DDR_B_D15 D18 G17 DDR_A_D15
DDR_A_MA2 MA_ADD3 MB_ADD3 DDR_B_MA2 DDR_B_D14 MB_DATA15 MA_DATA15 DDR_A_D14
N22 MA_ADD2 MB_ADD2 P24 C18 MB_DATA14 MA_DATA14 C17
DDR_A_MA1 N21 P26 DDR_B_MA1 DDR_B_D13 D14 F14 DDR_A_D13
DDR_A_MA0 MA_ADD1 MB_ADD1 DDR_B_MA0 DDR_B_D12 MB_DATA13 MA_DATA13 DDR_A_D12
R21 MA_ADD0 MB_ADD0 T24 C14 MB_DATA12 MA_DATA12 E14
DDR_B_D11 A20 H17 DDR_A_D11
DDR_A_BS#2 MB_DATA11 MA_DATA11
<8> DDR_A_BS#2 K22 MA_BANK2 MB_BANK2 K26 DDR_B_BS#2 DDR_B_BS#2 <9>
DDR_B_D10 A19 MB_DATA10 MA_DATA10 E17 DDR_A_D10
DDR_A_BS#1 R20 T26 DDR_B_BS#1 DDR_B_D9 A16 E15 DDR_A_D9
<8> DDR_A_BS#1 MA_BANK1 MB_BANK1 DDR_B_BS#1 <9> MB_DATA9 MA_DATA9
DDR_A_BS#0 T22 U26 DDR_B_BS#0 DDR_B_D8 A15 H15 DDR_A_D8
<8> DDR_A_BS#0 MA_BANK0 MB_BANK0 DDR_B_BS#0 <9> MB_DATA8 MA_DATA8
DDR_B_D7 A13 E13 DDR_A_D7
DDR_A_RAS# MB_DATA7 MA_DATA7
<8> DDR_A_RAS# T20 MA_RAS_L MB_RAS_L U24 DDR_B_RAS# DDR_B_RAS# <9>
DDR_B_D6 D12 MB_DATA6 MA_DATA6 C13 DDR_A_D6
DDR_A_CAS# U20 V26 DDR_B_CAS# DDR_B_D5 E11 H12 DDR_A_D5
<8> DDR_A_CAS# MA_CAS_L MB_CAS_L DDR_B_CAS# <9> MB_DATA5 MA_DATA5
DDR_A_WE# U21 U22 DDR_B_WE# DDR_B_D4 G11 H11 DDR_A_D4
<8> DDR_A_WE# MA_WE_L MB_WE_L DDR_B_WE# <9> MB_DATA4 MA_DATA4
DDR_B_D3 B14 G14 DDR_A_D3
DDR_B_D2 MB_DATA3 MA_DATA3 DDR_A_D2
A14 MB_DATA2 MA_DATA2 H14
Athlon 64 S1 DDR_B_D1 A11 F12 DDR_A_D1
Processor DDR_B_D0 MB_DATA1 MA_DATA1 DDR_A_D0
C11 MB_DATA0 MA_DATA0 G12
Socket
<9> DDR_B_DM[7..0] DDR_A_DM[7..0] <8>
DDR_B_DM7 AD12 Y13 DDR_A_DM7
DDR_B_DM6 MB_DM7 MA_DM7 DDR_A_DM6
AC16 MB_DM6 MA_DM6 AB16
DDR_B_DM5 AE22 Y19 DDR_A_DM5
DDR_B_DM4 MB_DM5 MA_DM5 DDR_A_DM4
AB26 MB_DM4 MA_DM4 AC24
DDR_A_CLK2 DDR_B_CLK2 DDR_B_DM3 E25 F24 DDR_A_DM3
DDR_B_DM2 MB_DM3 MA_DM3 DDR_A_DM2
1 1 A22 MB_DM2 MA_DM2 E19
DDR_B_DM1 B16 C15 DDR_A_DM1
C392 C393 DDR_B_DM0 MB_DM1 MA_DM1 DDR_A_DM0
A12 MB_DM0 MA_DM0 E12
1.5P 50V F NPO 0402 1.5P 50V F NPO 0402
DDR_A_CLK#2 2 DDR_B_CLK#2 2 DDR_B_DQS7 DDR_A_DQS7
<9> DDR_B_DQS7 AF12 MB_DQS_H7 MA_DQS_H7 W12 DDR_A_DQS7 <8>
DDR_B_DQS#7 AE12 W13 DDR_A_DQS#7
<9> DDR_B_DQS#7 MB_DQS_L7 MA_DQS_L7 DDR_A_DQS#7 <8>
DDR_A_CLK1 DDR_B_CLK1 DDR_B_DQS6 AE16 Y15 DDR_A_DQS6
<9> DDR_B_DQS6 MB_DQS_H6 MA_DQS_H6 DDR_A_DQS6 <8>
1 1 DDR_B_DQS#6 AD16 W15 DDR_A_DQS#6
<9> DDR_B_DQS#6 MB_DQS_L6 MA_DQS_L6 DDR_A_DQS#6 <8>
DDR_B_DQS5 AF21 AB19 DDR_A_DQS5
<9> DDR_B_DQS5 MB_DQS_H5 MA_DQS_H5 DDR_A_DQS5 <8>
C439 C438 DDR_B_DQS#5 AF22 AB20 DDR_A_DQS#5
1.5P 50V F NPO 0402 1.5P 50V F NPO 0402 <9> DDR_B_DQS#5 MB_DQS_L5 MA_DQS_L5 DDR_A_DQS#5 <8>
DDR_B_DQS4 AC25 AD23 DDR_A_DQS4
2 2 <9> DDR_B_DQS4 MB_DQS_H4 MA_DQS_H4 DDR_A_DQS4 <8>
DDR_A_CLK#1 DDR_B_CLK#1 DDR_B_DQS#4 AC26 AC23 DDR_A_DQS#4
<9> DDR_B_DQS#4 MB_DQS_L4 MA_DQS_L4 DDR_A_DQS#4 <8>
DDR_B_DQS3 F26 G22 DDR_A_DQS3
<9> DDR_B_DQS3 MB_DQS_H3 MA_DQS_H3 DDR_A_DQS3 <8>
DDR_B_DQS#3 E26 G21 DDR_A_DQS#3
<9> DDR_B_DQS#3 MB_DQS_L3 MA_DQS_L3 DDR_A_DQS#3 <8>
PLACE CLOSE TO PROCESSOR PLACE CLOSE TO PROCESSOR DDR_B_DQS2 A24 C22 DDR_A_DQS2
2 <9> DDR_B_DQS2 MB_DQS_H2 MA_DQS_H2 DDR_A_DQS2 <8> 2
DDR_B_DQS#2 A23 C21 DDR_A_DQS#2
WITHIN 1.5 INCH WITHIN 1.5 INCH <9> DDR_B_DQS#2
DDR_B_DQS1 MB_DQS_L2 MA_DQS_L2 DDR_A_DQS1
DDR_A_DQS#2 <8>
<9> DDR_B_DQS1 D16 MB_DQS_H1 MA_DQS_H1 G16 DDR_A_DQS1 <8>
DDR_B_DQS#1 C16 G15 DDR_A_DQS#1
<9> DDR_B_DQS#1 MB_DQS_L1 MA_DQS_L1 DDR_A_DQS#1 <8>
DDR_B_DQS0 C12 G13 DDR_A_DQS0
<9> DDR_B_DQS0 MB_DQS_H0 MA_DQS_H0 DDR_A_DQS0 <8>
DDR_B_DQS#0 B12 H13 DDR_A_DQS#0
<9> DDR_B_DQS#0 MB_DQS_L0 MA_DQS_L0 DDR_A_DQS#0 <8>
Athlon 64 S1
Processor Socket
+1.8V A1 A26
VDD_VREF_SUS_CPU
Placement between CPU to DDR area(Reserved for EMI)
+1.8V
Athlon 64 S1g1
2
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
R35 1 1 1 1
uPGA638
C609
C610
C611
C612
1K_0402_1% +CPU_M_VREF
Top View
1
2 2 2 2
1000P_0402_50V7K~N
0.1U_0402_16V7K~N
1 1
2
C54
AF1
C53
1 1
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
R34
1K_0402_1% 1 1 1 1
2 2
C613
C614
C615
C616
1
2 2 2 2
2
EXIT BALL FIELD) AND 500 mils LONG. 2006-10-02 unpop (ATI recommend)
10K_0402_5%
4.7K_0402_5%
L35
300_0402_5%
R220
R229
LQG21F4R7N00_0805
2
300_0402_5%
300_0402_5%
R227
R221
R254
+2.5VDDA 1 2 CPU_+VDDA
R252 @ 1 @
2 1
4.7U_0805_6.3V6K~N
0_0805_5% 1 1 1
+ C458 C460 C459 Q41
+3VALW 2 1 U21 C457 0.22U_0603_10V7K CPU1D
1
+3VS 2 1 1 5 +2.5VDDA 150U_D2_6.3VM F8 AF6 CPU_THERMTRIP#_R 3 1
IN OUT 2 2 2 2 VDDA2 THERMTRIP_L H_THERMTRIP# <16>
2 2 +1.8V F9 VDDA1 PROCHOT_L AC7 CPU_PROCHOT#_1.8 MMBT3904_NL_SOT23
R2530_0805_5% 2 3300P_0402_50V7K
GND
1
C444 CPU_HT_RESET# B7
D 1U_0603_10V6K +1.8V R29 CPU_ALL_PWROK RESET_L +1.8V D
3 SHDN BYP 4 1U_0603_10V6K A7 PWROK
C433 1 1 @ CPU_LDTSTOP#
1 300_0402_5% F10 LDTSTOP_L
G914E_SOT23-5 A5 VID5
VID5 VID5 <36>
1
2
C432 CPU_SIC AF4 C6 VID4
VID4 <36>
2
SIC VID4
10K_0402_5%
R241 0.01U_0402_16V7K 1 R30 2 CPU_SID AF5 A6 VID3
2 <15> CPU_SID_SB SID VID3 VID3 <36>
R219
470_0402_5% R226 0_0402_5% A4 VID2
VID2 VID2 <36> +3VALW
@ 300_0402_5% @ +1.2V_HT R234 1 2 44.2_0402_1% CPU_HTREF1 P6 C5 VID1
HTREF1 VID1 VID1 <36>
4.7K_0402_5%
R233 1 2 44.2_0402_1% CPU_HTREF0 R6 B5 VID0
VID0 <36>
2
CPU_PH_G1
HTREF0 VID0
R218
2
2
<15> CPU_SIC_SB 1 R31 2 CPU_SIC
CPU_PRESENT_L AC6 CPU_PRESENT#
1
D 0_0402_5%
<36> CPU_VDD_FB_H F6 VDD_FB_H
Q42 2 SYSON# @ E6 A3 CPU_PSI# TP50
SYSON# <30,35> <36> CPU_VDD_FB_L VDD_FB_L PSI_L
1
SSM3K7002FU_SC70-3 G place them to CPU within 1" @
@ S R228 TP2 VDDIOFB_H W9 @
CPU_PSI# <36>
3
1
VDDIO_FB_H
2
300_0402_5% TP26 VDDIOFB_L Y9 Q40
VDDIO_FB_L
2
C446 CPU_CLKIN_SC_N CLKIN_H MMBT3904_NL_SOT23
A8 CLKIN_L
1
R249 CPU_DBRDY G10 E10 CPU_DBREQ#
DBRDY DBREQ_L @
169_0402_1% CPU_TMS AA9
CPU_TCK TMS CPU_TDO
AC9 AE9
2
CPU_TRST# TCK TDO R44
<13> CPUCLK0_L 1 2 AD9 TRST_L
C445 3900P_0402_50V7K CPU_TDI AF9 TDI 80.6_0402_1%
CPU_TEST25_H_BYPASSCLK_H E9 C9 CPU_TEST29_H_FBCLKOUT_P 1 2
CPU_TEST25_L_BYPASSCLK_L TEST25_H TEST29_H CPU_TEST29_L_FBCLKOUT_N
E8 TEST25_L TEST29_L C8
TP15 CPU_TEST19_PLLTEST0 G9 TEST19
<15> CPU_PWRGD 1 R248 2 CPU_ALL_PWROK TP19 CPU_TEST18_PLLTEST1 H10 TEST18 ROUTE AS 80 Ohm DIFFERENTIAL PAIR
MISC
0_0402_5% AA7 PLACE IT CLOSE TO CPU WITHIN 1"
TEST13
C2 TEST9
2
B B
220_0402_5% R22
220_0402_5% R24
220_0402_5% R21
220_0402_5% R18
220_0402_5% R20
220_0402_5% R19
220_0402_5% R16
CPUCLK0_H TP49PAD
1
CPUCLK0_L TP51PAD
CPU_VDD_FB_H TP12PAD
CPU_VDD_FB_L TP20PAD @ @
2
CPU_TEST29_H_FBCLKOUT_P TP18PAD
CPU_TEST29_L_FBCLKOUT_N TP17PAD CPU_DBREQ#
CPU_DBRDY CPU_TDO
CPU_TCK +3VS
Thermal Sensor
1
CPU_TMS
CPU_TDI R23 R17
CPU_ALL_PWROK TP46PAD CPU_TRST# 0_0402_5%
CPU_LDTSTOP# TP16PAD
@ @
0_0402_5%
1
ADM1032
2
1
CPU_HT_RESET# TP45PAD C395 R232
NOTE: HDT TERMINATION IS REQUIRED 0.1U_0402_16V7K~N @ 10K_0402_5%
CPU_THERMTRIP#_R TP30PAD THERMDA_CPU 2
FOR REV. Ax SILICON ONLY.
1
2
C396 U19
2 D+ VDD1 1
2200P_0402_50V7K
THERMDC_CPU 2
3 D- ALERT# 6
A +3VALW A
ADM1032ARMZ MSOP 8P
U3
TP54
SB_PWRGD 2
P
<16,26> SB_PWRGD B
4 HDT_RST#
LDT_RST# Y
1 A
G
CPU1F
AA4 VSS1 VSS66 J6
AA11 VSS2 VSS67 J8
AA13 VSS3 VSS68 J10
AA15 VSS4 VSS69 J12
AA17 VSS5 VSS70 J14
AA19 VSS6 VSS71 J16
+CPU_CORE +CPU_CORE AB2 J18
CPU1E VSS7 VSS72
AB7 VSS8 VSS73 K2
AC4 VDD1 VDD43 V12 AB9 VSS9 VSS74 K7
AD2 VDD2 VDD44 V14 AB23 VSS10 VSS75 K9
G4 VDD3 VDD45 W4 AB25 VSS11 VSS76 K11
H2 VDD4 VDD46 Y2 AC11 VSS12 VSS77 K13
D D
J9 VDD5 VDD47 J15 AC13 VSS13 VSS78 K15
J11 VDD6 VDD48 K16 AC15 VSS14 VSS79 K17
J13 VDD7 VDD49 L15 AC17 VSS15 VSS80 L6
K6 VDD8 VDD50 M16 AC19 VSS16 VSS81 L8
K10 P16 AC21 L10
BOTTOMSIDE DECOUPLING K12
VDD9
VDD10
VDD51
VDD52 T16 AD6
VSS17
VSS18
VSS82
VSS83 L12
K14 VDD11 VDD53 U15 AD8 VSS19 VSS84 L14
+CPU_CORE L4 V16 AD25 L16
+CPU_CORE VDD12 VDD54 +1.8V VSS20 VSS85
L7 VDD13 AE11 VSS21 VSS86 L18
L9 VDD14 AE13 VSS22 VSS87 M7
L11 VDD15 VDDIO1 H25 AE15 VSS23 VSS88 M9
1 2 L13 VDD16 VDDIO2 J17 AE17 VSS24 VSS89 M11
330U_D2E_2.5VM
330U_D2E_2.5VM
proadlizer 1200uF 1 1 M2 VDD17 VDDIO3 K18 AE19 VSS25 VSS90 M17
+ PC44 M6 K21 AE21 N4
VDD18 VDDIO4 VSS26 VSS91
C385
C386
1200P_PFAF250E128MNTTE_2.5VM + + M8 K23 AE23 N8
@ @ VDD19 VDDIO5 VSS27 VSS92
Power
M10 VDD20 VDDIO6 K25 B4 VSS28 VSS93 N10
3 4
N7 VDD21 VDDIO7 L17 B6 VSS29 VSS94 N16
2 2
N9 VDD22 VDDIO8 M18 B8 VSS30 VSS95 N18
Ground
N11 VDD23 VDDIO9 M21 B9 VSS31 VSS96 P2
P8 VDD24 VDDIO10 M23 B11 VSS32 VSS97 P7
+1.8V P10 M25 B13 P9
VDD25 VDDIO11 VSS33 VSS98
R4 VDD26 VDDIO12 N17 B15 VSS34 VSS99 P11
R7 VDD27 VDDIO13 P18 B17 VSS35 VSS100 P17
10U_0805_6.3V6M
10U_0805_6.3V6M
0.22U_0603_10V7K
0.22U_0603_10V7K
R9 VDD28 VDDIO14 P21 B19 VSS36 VSS101 R8
1 1 1 1 R11 VDD29 VDDIO15 P23 B21 VSS37 VSS102 R10
C69
C101
C403
C398
T2 VDD30 VDDIO16 P25 B23 VSS38 VSS103 R16
T6 VDD31 VDDIO17 R17 B25 VSS39 VSS104 R18
T8 VDD32 VDDIO18 T18 D6 VSS40 VSS105 T7
2 2 2 2
T10 VDD33 VDDIO19 T21 D8 VSS41 VSS106 T9
T12 VDD34 VDDIO20 T23 D9 VSS42 VSS107 T11
T14 VDD35 VDDIO21 T25 D11 VSS43 VSS108 T13
U7 VDD36 VDDIO22 U17 D13 VSS44 VSS109 T15
C C
U9 VDD37 VDDIO23 V18 D15 VSS45 VSS110 T17
U11 VDD38 VDDIO24 V21 D17 VSS46 VSS111 U4
U13 VDD39 VDDIO25 V23 D19 VSS47 VSS112 U6
V6 VDD40 VDDIO26 V25 D21 VSS48 VSS113 U8
V8 VDD41 VDDIO27 Y25 D23 VSS49 VSS114 U10
V10 VDD42 D25 VSS50 VSS115 U12
E4 VSS51 VSS116 U14
Athlon 64 S1 F2 U16
Processor Socket VSS52 VSS117
F11 VSS53 VSS118 U18
F13 VSS54 VSS119 V2
F15 VSS55 VSS120 V7
F17 VSS56 VSS121 V9
F19 VSS57 VSS122 V11
F21 VSS58 VSS123 V13
F23 V15
+1.8V
PLACE CLOSE TO SO-DIMM1 AS POSSIBLE F25
VSS59
VSS60
VSS124
VSS125 V17
H7 VSS61 VSS126 W6
H9 VSS62 VSS127 Y21
H21 VSS63 VSS128 Y23
H23 VSS64 VSS129 N6
J4 VSS65
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
4.7U_0805_6.3V6K~N
4.7U_0805_6.3V6K~N
1 1 1 1 1 1 1 1 1 1 1 1 1 1
C126
C100
Athlon 64 S1
Processor Socket
2 2 2 2 2 2 2 2 2 2 2 2 2 2
C85
C84
C60
C50
C96
C67
C409
C406
C74
C108
C87
C77
B B
DECOUPLING BETWEEN PROCESSOR AND DIMMs
PLACE CLOSE TO PROCESSOR AS POSSIBLE +1.8V
+1.8V
PLACE CLOSE TO SO-DIMM2 AS POSSIBLE
330U_D2E_2.5VM
330U_D2E_2.5VM
180P_0402_50V8J~N
180P_0402_50V8J~N
0.22U_0603_10V7K
0.22U_0603_10V7K
0.22U_0603_10V7K
0.22U_0603_10V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
4.7U_0805_6.3V6K~N
4.7U_0805_6.3V6K~N
4.7U_0805_6.3V6K~N
4.7U_0805_6.3V6K~N
+1.8V 1 1
1 1 1 1 1 1 1 1 1 1
C92
C166
C397
C49
C423
C125
C408
C401
C102
C404
+ +
C91
C90
C70
C89
@
2 2 2 2 2 2 2 2 2 2 2 2
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
4.7U_0805_6.3V6K~N
4.7U_0805_6.3V6K~N
1 1 1 1 1 1 1 1 1 1 1 1 1 1
C55
C48
+0.9V
2 2 2 2 2 2 2 2 2 2 2 2 2 2
1000P_0402_50V7K~N
1000P_0402_50V7K~N
1000P_0402_50V7K~N
1000P_0402_50V7K~N
180P_0402_50V8J~N
180P_0402_50V8J~N
180P_0402_50V8J~N
180P_0402_50V8J~N
0.22U_0603_10V7K
0.22U_0603_10V7K
0.22U_0603_10V7K
0.22U_0603_10V7K
4.7U_0805_6.3V6K~N
4.7U_0805_6.3V6K~N
4.7U_0805_6.3V6K~N
4.7U_0805_6.3V6K~N
4.7U_0805_6.3V6K~N
C88
C62
C109
C83
C73
C405
C402
C400
C399
C99
C61
C68
1 1 1 1 1 1 1 1 1 2 2 2 2
C391
C461
C447
C52
C111
C448
C464
C390
C389
C387
C435
C436
C434
C437
C462
C463
C388
2 2 2 2 2 2 2 2 2 1 1 1 1
A A
DDR_A_D[0..63]
<5> DDR_A_D[0..63]
+1.8V +1.8V +DIMM_VREF +1.8V DDR_A_DM[0..7]
<5> DDR_A_DM[0..7]
2007-01-17 Add
DDR_A_DQS[0..7]
<5> DDR_A_DQS[0..7]
0.1U_0402_16V7K~N
2
1 DDR_A_MA[0..15]
<5> DDR_A_MA[0..15]
C179
JDIM1 R78 Layout Note:
1 2 1K_0402_1% DDR_A_DQS#[0..7]
3
VREF VSS
4 DDR_A_D4 <5> DDR_A_DQS#[0..7] Place one cap close to every 2 pullup
DDR_A_D0 VSS DQ4 DDR_A_D5 2
5 6 resistors terminated to +0.9V
1
DDR_A_D1 DQ0 DQ5
7 DQ1 VSS 8
9 10 DDR_A_DM0 +1.8V
D DDR_A_DQS#0 VSS DM0 D
11 DQS0# VSS 12
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
DDR_A_DQS0 13 14 DDR_A_D6
DQS0 DQ6
2
0.1U_0402_16V7K~N
15 16 DDR_A_D7
VSS DQ7
1000P_0402_50V7K~N
DDR_A_D2 17 18 1 1 R79 1 1 1 1 1 1 1 1
DQ2 VSS
C180
DDR_A_D3 19 20 DDR_A_D12 1K_0402_1%
DQ3 DQ12
C181
21 22 DDR_A_D13
DDR_A_D8 VSS DQ13
23 24
1
DDR_A_D9 DQ8 VSS DDR_A_DM1 2 2 2 2 2 2 2 2 2 2
25 DQ9 DM1 26
C95
C103
C104
C93
C71
C94
C80
C132
27 VSS VSS 28
DDR_A_DQS#1 29 30 DDR_A_CLK1
DQS1# CK0 DDR_A_CLK1 <5>
DDR_A_DQS1 31 32 DDR_A_CLK#1
DQS1 CK0# DDR_A_CLK#1 <5>
33 34 +0.9V
DDR_A_D10 VSS VSS DDR_A_D14
35 DQ10 DQ14 36
DDR_A_D11 37 38 DDR_A_D15
DQ11 DQ15
39 VSS VSS 40
Layout Note:
+0.9V
41 42 Place one cap close to every 2 pullup
DDR_A_D16 VSS VSS DDR_A_D20
43 DQ16 DQ20 44 resistors terminated to +0.9V
DDR_A_D17 45 46 DDR_A_D21
DQ17 DQ21
47 VSS VSS 48
DDR_A_DQS#2 49 50 +0.9V
DQS2# NC
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
DDR_A_DQS2 51 52 DDR_A_DM2
DQS2 DM2
53 VSS VSS 54
330U_D2E_2.5VM
DDR_A_D18 55 56 DDR_A_D22 1 1 1 1 1 1 1 1 1
DDR_A_D19 DQ18 DQ22 DDR_A_D23
57 DQ19 DQ23 58
C47
59 60 +
DDR_A_D24 VSS VSS DDR_A_D28
61 DQ24 DQ28 62
DDR_A_D25 DDR_A_D29 2 2 2 2 2 2 2 2
63 DQ25 DQ29 64
2
C75
C58
C98
C81
C106
C72
C51
C110
65 66 @
C DDR_A_DM3 VSS VSS DDR_A_DQS#3 C
67 DM3 DQS3# 68
69 70 DDR_A_DQS3
NC DQS3
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
75 DQ27 DQ31 76
77 VSS VSS 78
DDR_CKE0_DIMMA 79 80 DDR_CKE1_DIMMA +0.9V
<5> DDR_CKE0_DIMMA CKE0 NC/CKE1 DDR_CKE1_DIMMA <5>
81 VDD VDD 82
DDR_CS2_DIMMA# 83 84 DDR_A_MA15 RP14
<5> DDR_CS2_DIMMA# NC NC/A15
DDR_A_BS#2 85 86 DDR_A_MA14 DDR_CKE1_DIMMA 8 1
<5> DDR_A_BS#2 BA2 NC/A14
87 88 DDR_A_MA7 7 2
DDR_A_MA12 VDD VDD DDR_A_MA11 DDR_A_MA14
89 A12 A11 90 6 3
DDR_A_MA9 91 92 DDR_A_MA7 DDR_A_MA15 5 4
DDR_A_MA8 A9 A7 DDR_A_MA6
93 A8 A6 94
95 96 47_0804_8P4R_5%
DDR_A_MA5 VDD VDD DDR_A_MA4 RP5
97 A5 A4 98
DDR_A_MA3 99 100 DDR_A_MA2 DDR_A_CAS# 8 1
DDR_A_MA1 A3 A2 DDR_A_MA0 DDR_A_MA10
101 A1 A0 102 7 2
103 104 DDR_A_BS#0 6 3
DDR_A_MA10 VDD VDD DDR_A_BS#1 DDR_A_MA1
105 A10/AP BA1 106 DDR_A_BS#1 <5> 5 4
DDR_A_BS#0 107 108 DDR_A_RAS#
<5> DDR_A_BS#0 BA0 RAS# DDR_A_RAS# <5>
DDR_A_WE# 109 110 DDR_CS0_DIMMA# 47_0804_8P4R_5%
<5> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <5>
111 112 RP6
DDR_A_CAS# VDD VDD DDR_A_ODT0 DDR_A_MA2
<5> DDR_A_CAS# 113 CAS# ODT0 114 DDR_A_ODT0 <5> 8 1
DDR_CS1_DIMMA# 115 116 DDR_A_MA13 DDR_A_BS#1 7 2
<5> DDR_CS1_DIMMA# NC/S1# NC/A13
117 118 DDR_A_MA0 6 3
DDR_A_ODT1 VDD VDD DDR_CS3_DIMMA# DDR_A_RAS#
<5> DDR_A_ODT1 119 NC/ODT1 NC 120 DDR_CS3_DIMMA# <5> 5 4
121 VSS VSS 122
DDR_A_D32 123 124 DDR_A_D36 47_0804_8P4R_5%
DDR_A_D33 DQ32 DQ36 DDR_A_D37 RP9
125 DQ33 DQ37 126
B DDR_A_MA9 B
127 VSS VSS 128 8 1
DDR_A_DQS#4 129 130 DDR_A_DM4 DDR_A_MA5 7 2
DDR_A_DQS4 DQS4# DM4 DDR_A_MA3
131 DQS4 VSS 132 6 3
133 134 DDR_A_D38 DDR_A_MA8 5 4
DDR_A_D34 VSS DQ38 DDR_A_D39
135 DQ34 DQ39 136
DDR_A_D35 137 138 47_0804_8P4R_5%
DQ35 VSS DDR_A_D44 RP10
139 VSS DQ44 140
DDR_A_D40 141 142 DDR_A_D45 DDR_A_MA11 8 1
DDR_A_D41 DQ40 DQ45 DDR_A_MA6
143 DQ41 VSS 144 7 2
145 146 DDR_A_DQS#5 DDR_A_MA4 6 3
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 DM5 DQS5 148 5 4
149 VSS VSS 150
DDR_A_D42 151 152 DDR_A_D46 47_0804_8P4R_5%
DDR_A_D43 DQ42 DQ46 DDR_A_D47 RP1
153 DQ43 DQ47 154
155 156 DDR_A_ODT1 8 1
DDR_A_D48 VSS VSS DDR_A_D52
157 DQ48 DQ52 158 7 2
DDR_A_D49 159 160 DDR_A_D53 DDR_CS1_DIMMA# 6 3
DQ49 DQ53 DDR_A_WE#
161 VSS VSS 162 5 4
163 164 DDR_A_CLK2
NC,TEST CK1 DDR_A_CLK2 <5>
165 166 DDR_A_CLK#2 47_0804_8P4R_5%
VSS CK1# DDR_A_CLK#2 <5>
DDR_A_DQS#6 167 168 RP2
DDR_A_DQS6 DQS6# VSS DDR_A_DM6 DDR_CS0_DIMMA#
169 DQS6 DM6 170 8 1
171 172 DDR_A_MA13 7 2
DDR_A_D50 VSS VSS DDR_A_D54 DDR_A_ODT0
173 DQ50 DQ54 174 6 3
DDR_A_D51 175 176 DDR_A_D55 DDR_CS3_DIMMA# 5 4
DQ51 DQ55
177 VSS VSS 178
DDR_A_D56 179 180 DDR_A_D60 47_0804_8P4R_5%
DDR_A_D57 DQ56 DQ60 DDR_A_D61 RP13
181 DQ57 DQ61 182
183 184 DDR_A_BS#2 8 1
DDR_A_DM7 VSS VSS DDR_A_DQS#7 DDR_A_MA12
185 DM7 DQS7# 186 7 2
A DDR_A_DQS7 DDR_CKE0_DIMMA A
187 VSS DQS7 188 6 3
DDR_A_D58 189 190 DDR_CS2_DIMMA# 5 4
DDR_A_D59 DQ58 VSS DDR_A_D62
191 DQ59 DQ62 192
193 194 DDR_A_D63 47_0804_8P4R_5%
SMB_CK_DAT1 VSS DQ63 R28 0_0402_5%
<9,13,16,27> SMB_CK_DAT1 195 SDA VSS 196
SMB_CK_CLK1 197 198 2 1
<9,13,16,27> SMB_CK_CLK1 SCL SAO
199 200 2 1
+3VS VDDSPD SA1
R25 0_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/7/6 Deciphered Date 2008/7/6 Title
P-TWO_A5692C-A0G16
SCHEMATICS,MB A4011
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CONN@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401521 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 21, 2008 Sheet 8 of 38
5 4 3 2 1
5 4 3 2 1
DDR_B_D[0..63]
+1.8V +1.8V +DIMM_VREF <5> DDR_B_D[0..63]
DDR_B_DM[0..7]
<5> DDR_B_DM[0..7]
DDR_B_DQS[0..7]
<5> DDR_B_DQS[0..7]
JDIM2 DDR_B_MA[0..15]
<5> DDR_B_MA[0..15]
1000P_0402_50V7K~N
1 VREF VSS 2 1
3 4 DDR_B_D4 DDR_B_DQS#[0..7]
VSS DQ4 <5> DDR_B_DQS#[0..7]
C182
DDR_B_D0 5 6 DDR_B_D5 +0.9V
DDR_B_D1 DQ0 DQ5
7 DQ1 VSS 8
DDR_B_DM0 2
9 VSS DM0 10
D DDR_B_DQS#0 D
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D7
15 VSS DQ7 16
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
DDR_B_D2 17 18
DQ2 VSS
330U_D2E_2.5VM
DDR_B_D3 19 20 DDR_B_D12 1
DQ3 DQ12 DDR_B_D13
21 VSS DQ13 22 1 1 1 1 1 1 1 1
C142
DDR_B_D8 +
23 DQ8 VSS 24 Layout Note:
DDR_B_D9 25 26 DDR_B_DM1
27
DQ9 DM1
28 Place one cap close to every 2 pullup
DDR_B_DQS#1 VSS VSS DDR_B_CLK1 2 2 2 2 2 2 2 2 2
29 DQS1# CK0 30 DDR_B_CLK1 <5> resistors terminated to +0.9V
C107
C112
C97
C64
C86
C82
C59
C63
DDR_B_DQS1 31 32 DDR_B_CLK#1
DQS1 CK0# DDR_B_CLK#1 <5>
33 VSS VSS 34
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
39 VSS VSS 40
41 VSS VSS 42
DDR_B_D16 43 44 DDR_B_D20 +1.8V
DDR_B_D17 DQ16 DQ20 DDR_B_D21
45 DQ17 DQ21 46
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
47 VSS VSS 48
DDR_B_DQS#2 49 50
DDR_B_DQS2 DQS2# NC DDR_B_DM2
51 DQS2 DM2 52 1 1 1 1 1 1 1 1 Layout Note:
53 54
DDR_B_D18 55
VSS VSS
56 DDR_B_D22 Place one cap close to every 2 pullup
DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
2 2 2 2 2 2 2 2
resistors terminated to +0.9V
59 VSS VSS 60
C76
C78
C57
C79
C66
C65
C105
C56
DDR_B_D24 61 62 DDR_B_D28
DDR_B_D25 DQ24 DQ28 DDR_B_D29
63 DQ25 DQ29 64
65 66 +0.9V
C DDR_B_DM3 VSS VSS DDR_B_DQS#3 +0.9V C
67 DM3 DQS3# 68
69 70 DDR_B_DQS3
NC DQS3 RP16
71 VSS VSS 72
DDR_B_D26 73 74 DDR_B_D30 DDR_CKE1_DIMMB 8 1
DDR_B_D27 DQ26 DQ30 DDR_B_D31 DDR_B_MA14
75 DQ27 DQ31 76 7 2
77 78 DDR_B_MA15 6 3
DDR_CKE0_DIMMB VSS VSS DDR_CKE1_DIMMB DDR_B_MA11
<5> DDR_CKE0_DIMMB 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMB <5> 5 4
81 VDD VDD 82
DDR_CS2_DIMMB# 83 84 DDR_B_MA15 47_0804_8P4R_5%
<5> DDR_CS2_DIMMB# NC NC/A15
DDR_B_BS#2 85 86 DDR_B_MA14
<5> DDR_B_BS#2 BA2 NC/A14
87 88 RP11
DDR_B_MA12 VDD VDD DDR_B_MA11 DDR_B_MA1
89 A12 A11 90 8 1
DDR_B_MA9 91 92 DDR_B_MA7 DDR_B_MA3 7 2
DDR_B_MA8 A9 A7 DDR_B_MA6 DDR_B_MA9
93 A8 A6 94 6 3
95 96 DDR_B_MA12 5 4
DDR_B_MA5 VDD VDD DDR_B_MA4
97 A5 A4 98
DDR_B_MA3 99 100 DDR_B_MA2 47_0804_8P4R_5%
DDR_B_MA1 A3 A2 DDR_B_MA0
101 A1 A0 102
103 104 RP7
DDR_B_MA10 VDD VDD DDR_B_BS#1 DDR_B_BS#0
105 A10/AP BA1 106 DDR_B_BS#1 <5> 8 1
DDR_B_BS#0 107 108 DDR_B_RAS# DDR_B_MA10 7 2
<5> DDR_B_BS#0 BA0 RAS# DDR_B_RAS# <5>
DDR_B_WE# 109 110 DDR_CS0_DIMMB# DDR_B_WE# 6 3
<5> DDR_B_WE# WE# S0# DDR_CS0_DIMMB# <5>
111 112 DDR_B_MA5 5 4
DDR_B_CAS# VDD VDD DDR_B_ODT0
<5> DDR_B_CAS# 113 CAS# ODT0 114 DDR_B_ODT0 <5>
DDR_CS1_DIMMB# 115 116 DDR_B_MA13 47_0804_8P4R_5%
<5> DDR_CS1_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
DDR_B_ODT1 119 120 DDR_CS3_DIMMB# RP8
<5> DDR_B_ODT1 NC/ODT1 NC DDR_CS3_DIMMB# <5>
121 122 DDR_B_MA2 8 1
DDR_B_D32 VSS VSS DDR_B_D36 DDR_B_BS#1
123 DQ32 DQ36 124 7 2
DDR_B_D33 125 126 DDR_B_D37 DDR_CS0_DIMMB# 6 3
B DQ33 DQ37 DDR_B_RAS# B
127 VSS VSS 128 5 4
DDR_B_DQS#4 129 130 DDR_B_DM4
DDR_B_DQS4 DQS4# DM4 47_0804_8P4R_5%
131 DQS4 VSS 132
133 134 DDR_B_D38
DDR_B_D34 VSS DQ38 DDR_B_D39 RP4
135 DQ34 DQ39 136
DDR_B_D35 137 138 DDR_B_ODT0 8 1
DQ35 VSS DDR_B_D44 DDR_B_MA13
139 VSS DQ44 140 7 2
DDR_B_D40 141 142 DDR_B_D45 DDR_CS3_DIMMB# 6 3
DDR_B_D41 DQ40 DQ45
143 DQ41 VSS 144 5 4
145 146 DDR_B_DQS#5
DDR_B_DM5 VSS DQS5# DDR_B_DQS5 47_0804_8P4R_5%
147 DM5 DQS5 148
149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D46 RP3
DDR_B_D43 DQ42 DQ46 DDR_B_D47
153 DQ43 DQ47 154 8 1
155 156 DDR_B_ODT1 7 2
DDR_B_D48 VSS VSS DDR_B_D52 DDR_CS1_DIMMB#
157 DQ48 DQ52 158 6 3
DDR_B_D49 159 160 DDR_B_D53 DDR_B_CAS# 5 4
DQ49 DQ53
161 VSS VSS 162
163 164 DDR_B_CLK2 47_0804_8P4R_5%
NC,TEST CK1 DDR_B_CLK2 <5>
165 166 DDR_B_CLK#2
VSS CK1# DDR_B_CLK#2 <5>
DDR_B_DQS#6 167 168 RP12
DDR_B_DQS6 DQS6# VSS DDR_B_DM6 DDR_B_MA7
169 DQS6 DM6 170 8 1
171 172 DDR_B_MA0 7 2
DDR_B_D50 VSS VSS DDR_B_D54 DDR_B_MA6
173 DQ50 DQ54 174 6 3
DDR_B_D51 175 176 DDR_B_D55 DDR_B_MA4 5 4
DQ51 DQ55
177 VSS VSS 178
DDR_B_D56 179 180 DDR_B_D60 47_0804_8P4R_5%
DDR_B_D57 DQ56 DQ60 DDR_B_D61
181 DQ57 DQ61 182
183 184 RP15
DDR_B_DM7 VSS VSS DDR_B_DQS#7 DDR_B_BS#2
185 DM7 DQS7# 186 8 1
A DDR_B_DQS7 DDR_B_MA8 A
187 VSS DQS7 188 7 2
DDR_B_D58 189 190 DDR_CKE0_DIMMB 6 3
DDR_B_D59 DQ58 VSS DDR_B_D62 +3VS DDR_CS2_DIMMB#
191 DQ59 DQ62 192 5 4
193 194 DDR_B_D63
SMB_CK_DAT1 VSS DQ63 47_0804_8P4R_5%
<8,13,16,27> SMB_CK_DAT1 195 SDA VSS 196
SMB_CK_CLK1 197 198 R26 1 2 4.7K_0402_5%
<8,13,16,27> SMB_CK_CLK1 SCL SAO
199 200 2 1
+3VS VDDSPD SA1 R27 0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/7/6 Deciphered Date 2008/7/6 Title
P-TWO_A5652C-A0G16
SCHEMATICS,MB A4011
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CONN@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401521 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 21, 2008 Sheet 9 of 38
5 4 3 2 1
5 4 3 2 1
D D
H_CADIP[0..15]
<4> H_CADIP[0..15]
H_CADIN[0..15]
<4> H_CADIN[0..15]
H_CADOP[0..15]
<4> H_CADOP[0..15]
U690B
H_CADON[0..15]
<4> H_CADON[0..15]
G5 GFX_RX0P PART 2 OF 5 GFX_TX0P J1
G4 GFX_RX0N GFX_TX0N H2
J8 GFX_RX1P GFX_TX1P K2
J7 GFX_RX1N GFX_TX1N K1
J4 GFX_RX2P GFX_TX2P K3
J5 L3 U690A
GFX_RX2N GFX_TX2N
L8 GFX_RX3P GFX_TX3P L1
L7 L2 H_CADOP15 R19 P21 H_CADIP15
GFX_RX3N GFX_TX3N H_CADON15 HT_RXCAD15P HT_TXCAD15P H_CADIN15
L4 GFX_RX4P GFX_TX4P N2
H_CADOP14
R18 HT_RXCAD15N PART 1 OF 5 HT_TXCAD15N P22
H_CADIP14
L5 GFX_RX4N GFX_TX4N N1 R21 HT_RXCAD14P HT_TXCAD14P P18
M8 P2 H_CADON14 R22 P19 H_CADIN14
GFX_RX5P GFX_TX5P H_CADOP13 HT_RXCAD14N HT_TXCAD14N H_CADIP13
M7 GFX_RX5N GFX_TX5N P1 U22 HT_RXCAD13P HT_TXCAD13P M22
M4 P3 H_CADON13 U21 M21 H_CADIN13
GFX_RX6P GFX_TX6P H_CADOP12 HT_RXCAD13N HT_TXCAD13N H_CADIP12
M5 GFX_RX6N GFX_TX6N R3 U18 HT_RXCAD12P HT_TXCAD12P M18
C H_CADON12 H_CADIN12 C
P8 R1 U19 M19
PCIE GFX I/F
A A
0.1U_0402_16V7K~N
4.7U_0805_6.3V6K~N
2.2U_0603_10V6K
2 R71
+1.8VS U690C 0_0805_5%
15mil GND_LVSSR 2 1
B22 PART 3 OF 5 B14 LVDSL0+
+1.8VS AVDD1 TXOUT_L0P LVDSL0+ <14>
1 C22 B15 LVDSL0-
AVDD2 TXOUT_L0N LVDSL0- <14>
L39 15mil G17 B13 LVDSL1+
AVSSN1 TXOUT_L1P LVDSL1+ <14>
1 2 C472 H17 A13 LVDSL1-
AVSSN2 TXOUT_L1N LVDSL1- <14>
FBML10160808121LMT_0603 1 2.2U_0603_10V6K A20 H14 LVDSL2+
2 AVDDDI TXOUT_L2P LVDSL2+ <14>
B20 G14 LVDSL2-
AVSSDI TXOUT_L2N LVDSL2- <14>
C473 D17
2.2U_0603_10V6K +AVDDQ TXOUT_L3P
A21 AVDDQ TXOUT_L3N E17
2
A22 AVSSQ
CRT/TVOUT
A15 LVDSU0+
TXOUT_U0P LVDSU0+ <14>
C21 B16 LVDSU0-
C TXOUT_U0N LVDSU0- <14>
C20 C17 LVDSU1+
Y TXOUT_U1P LVDSU1+ <14>
D19 C18 LVDSU1-
COMP TXOUT_U1N LVDSU1- <14>
B17 LVDSU2+
TXOUT_U2P LVDSU2+ <14>
VGA_CRT_R E19 A17 LVDSU2-
<14> VGA_CRT_R RED TXOUT_U2N LVDSU2- <14> +1.8VS
<14> VGA_CRT_G VGA_CRT_G F19 A18
VGA_CRT_B G19 GREEN TXOUT_U3P L9
<14> VGA_CRT_B BLUE TXOUT_U3N B18
VGA_CRT_VSYNC C6 1 2 15mil
2006-12-30 Cap follow Bowfin2.1 <14> VGA_CRT_VSYNC DACVSYNC
VGA_CRT_HSYNC A5 E15 LVDSLC+ 1 FBML10160808121LMT_0603
<14> VGA_CRT_HSYNC DACHSYNC TXCLK_LP LVDSLC+ <14>
D15 LVDSLC-
2006-12-30 Bowfin 2.1 TXCLK_LN LVDSLC- <14>
R280 1 2 715_0402_1%
B21 H15 LVDSUC+ C170
RSET TXCLK_UP LVDSUC+ <14>
G15 LVDSUC- 2.2U_0603_10V6K
+1.8VS TXCLK_UN LVDSUC- <14> 2
L36 VGA_DDC_CLK R277 1 2 0_0402_5% VGA_DDC_CLK_NB B6
<14> VGA_DDC_CLK DACSCL
1 2 VGA_DDC_DATA A6 D14 +LPVDD
LVTM
Reserve for EMI, close to U690 <14> VGA_DDC_DATA DACSDA LPVDD
FBML10160808121LMT_0603 1 15mil E14
+NB_PLLVDD LPVSS L10
A10 PLLVDD(PLLVDD18)
C169 B10 A12 +LVDDR18D 1 2 +1.8VS
NB_REFCLK 2.2U_0603_10V6K PLLVSS LVDDR18D_1 FBML10160808121LMT_0603
LVDDR18D_2 B12
2 +NB_HTPVDD B24
PLL PWR
HTPVDD LVDDR18A_1(LVDDR33_1) C12
B25 C13 +LVDDR33A 15mil
HTPVSS LVDDR18A_2(LVDDR33_2)
1
PM
2 2 LVSSR7
2 1 10K_0402_5% R262 C23 C16
@ C161 HTREFCLK HTTSTCLK LVSSR8
<13> HTREFCLK B23 HTREFCLK
22P_0402_50V8J
1 10K_0402_5% R259 C2
2 1 TVCLKIN LVSSR12 F14
+1.2V_HT F15 GND_LVSSR
L37 NB_REFCLK LVSSR13
<13> NB_REFCLK B11 OSCIN
CLOCKs
15mil 1 2 A11 OSCOUT(PLLVDD12)
FBML10160808121LMT_0603
HTREFCLK NB_GFX_CLKP F2
<13> NB_GFX_CLKP GFX_CLKP
NB_GFX_CLKN E1 E12 ENVDD_NB 2 R69 1 0_0402_5% ENVDD
<13> NB_GFX_CLKN GFX_CLKN LVDS_DIGON ENVDD <14>
G12 ENABLT_NB 2 R68 1 0_0402_5% ENABLT
LVDS_BLON ENABLT <14,26>
1
R273
4.7K_0402_5%
DFT_GPIO1 DVO_D2(DEBUG6)
2
DVO_D7(GPP_TX1N)
DVO
BMREQ#_NB B2 AD19
MIS.
EDID_CLK_LCD EDID_CLK_LCD R274 1 BMREQ# DVO_D8(GPP_TX1P)
<14> EDID_CLK_LCD 2 0_0402_5% EDID_CLK_LCD_NB A2 I2C_CLK DVO_D9(GPP_RX1N) AE20
EDID_DAT_LCD B4 AD20
<14> EDID_DAT_LCD I2C_DATA DVO_D10(GPP_RX1P)
EDID_DAT_LCD AA15 AE21
THERMALDIODE_P DVO_D11(DEBUG15)
AB15 THERMALDIODE_N
2006-12-30 bowfin 2.1 AD13
DVO_VSYNC(DEBUG0)
C14 TMDS_HPD DVO_DE(DEBUG2) AC13 SUS_STAT#
+3VS R303 2 @ 1 4.7K_0402_5% B3 AE13
+3VS R302 1 DDC_DATA DVO_HSYNC(DEBUG1)
2 4.7K_0402_5% C3 TESTMODE DVO_IDCKP(DEBUG14) AE17 Q19
2
NB_STRAP_DATA +5VS
A3 STRP_DATA DVO_IDCKN(DEBUG13) AD17
R239 AP2301GN 1P SOT23
470K_0402_5% @
10K_0402_5%
S
216MQA6AVA11FG FCBGA 465P ENVDD_NB 3 ENVDD
D
1
R81 2
1
1
1
1K_0402_5%
G
2
R275 @
R83
1K_0402_5%
1
POWER PLAY NB_PWRGD5V#
2
+1.8VS
HI: 1.2V
2
1
NB_STRAP_DATA +3VS D @
2
LOW : 1.0V
G
NB_PWRGD 2
2
G
1
10K_0402_5%
10K_0402_5% Q17 S@ ENABLT_NB 3 1 ENABLT
D
R84
R276 SSM3K7002FU_SC70-3
1
+3VS
1K_0402_5%
2K_0402_5% R272 @
@ AP2301GN 1P SOT23
1
Q18 @
D16
2
R82
BMREQ# 2 1 BMREQ#_NB R70
<15> BMREQ#
2
10K_0402_5%
RB751V_SOD323
2
2
@ Q44
3 1 NB_LDTSTOP#
<6,15> LDT_STOP#
1 MMBT3904_NL_SOT23
C471
@ 15P_0402_50V8D
2
2006-09-27
+1.2V_HT
L3
1 2 NB_VDDHT12
FBMA-L11-322513-201LMA40T_1210
40mil
+
150U_D2_6.3VM 2 1 C407 0.5A
@
U690D U690E
C422 2 1 22U_1206_6.3V6M 2A
AA17 VDD_HT1 PART 4 OF 5 VDDA12_1 B1
AB17 VDD_HT2 VDDA12_2 C1 A25 VSS1
AB19 D1 C467 1 2 22U_1206_6.3V6M F11 PAR 5 OF 5 V12
D VDD_HT3 VDDA12_3 VSS2 VSSA2 D
AC18 VDD_HT4 VDDA12_4 D2 D23 VSS3 VSSA3 V11
AC19 D3 1U_0402_6.3V6K2 1 C147 E9 V14
C122 1U_0402_6.3V6K VDD_HT5 VDDA12_5 VSS4 VSSA4
1 2 AC20 VDD_HT6 VDDA12_6 E2 G11 VSS5 VSSA5 F3
C124 1 2 1U_0402_6.3V6K AD21 E3 NB_VDDA12_HT 1U_0402_6.3V6K2 1 C128 Y23 V15
C123 1U_0402_6.3V6K VDD_HT7 VDDA12_7 VSS6 VSSA6
1 2 AD22 VDD_HT8 VDDA12_8 F4 P11 VSS7 VSSA7 A1
C131 1 2 1U_0402_6.3V6K AD23 E6 1U_0402_6.3V6K2 1 C139 R24 H1
C421 1U_0402_6.3V6K VDD_HT9 VDDA12_9 VSS8 VSSA8
1 2 AD24 VDD_HT10 VDDA12_10 G7 AE18 VSS9 VSSA9 G3
AE23 L9 1U_0402_6.3V6K2 1 C115 M15 J2
VDD_HT11 VDDA12_11 VSS10 VSSA10
AE24 VDD_HT12 VDDA12_12 M9 J22 VSS11 VSSA11 H3
AE25 VDD_HT13 G23 VSS12
POWER
W17 VDD_HT14 VDDC_1 A4 J12 VSS13 VSSA13 J6
0.2A Y17 VDD_HT15 VDDC_2 A7 L12 VSS14
15mil VDDC_3 A9 L14 VSS15 VSSA15 F1
+1.8VS J14 VDD18_1 VDDC_4 A19 L20 VSS16 VSSA16 L6
J15 VDD18_2 VDDC_5 B9 L23 VSS17 VSSA17 M2
1U_0402_6.3V6K2 1 C175 B19 M11 M6
NB_VDDA12_HT VDDC_6 VSS18 VSSA18
AB3 VDDA18_1(VDDA12_13) VDDC_7 C9 M20 VSS19 VSSA19 J3
1U_0402_6.3V6K2 1 C164 AB4 D9 M23 P6
VDDA18_2(VDDA12_14) VDDC_8 VSS20 VSSA20
120mil AC3 VDDA18_3(VDDA12_15) VDDC_9 D20 M25 VSS21 VSSA21 T1
AD2 VDDA18_4(VDDA12_16) VDDC_10 G20 N12 VSS22 VSSA22 N3
AE1 H11 +1.2V_NBCORE N14
VDDA18_5(VDDA12_17) VDDC_11 VSS23
AE2 VDDA18_6(VDDA12_18) VDDC_12 J11 300mil VSSA24 R6
U7 VDDA18_7(VDDA12_19) VDDC_13 J19 L24 VSS25 VSSA25 U2
0.3A W7 VDDA18_8(VDDA12_20) VDDC_14 L11 P13 VSS26 VSSA26 T3
15mil L13 5A P20
GROUND
VDDC_15 VSS27 VSSA27 U3
+3VS D11 VDDR3_1 VDDC_16 L15 P15 VSS28 VSSA28 U6
E11 VDDR3_2 VDDC_17 L17 R12 VSS29
1U_0402_6.3V6K2 1 C151 M12 R14 Y1
VDDC_18 VSS30 VSSA30
+1.8VS AC12 VDD_DVO1(VDDR_1) VDDC_19 M14 R20 VSS31
C153
C135
C160
C158
C134
C140
C136
C165
C159
C133
C141
1U_0402_6.3V6K2 1 C150 AD12 N11 W23 W6
1U_0402_6.3V6K2 VDD_DVO2(VDDR_2) VDDC_20 VSS32 VSSA32
1 C121 AE12 VDD_DVO3(VDDR_3) VDDC_21 N13 1 1 1 1 1 1 1 1 1 1 1 Y25 VSS33 VSSA33 AC2
VDDC_22 N15 AD25 VSS34 VSSA34 Y3
C 1U_0402_6.3V6K2 NB_VDDA12 C
1 C130 E7 VDDA12(VDDPLL_1) VDDC_23 P12 U20 VSS35 VSSA35 Y9
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
F7 VDDA12(VDDPLL_2) VDDC_24 P14 H25 VSS36 VSSA36 Y11
2 2 2 2 2 2 2 2 2 2 2
22U_1206_6.3V6M
22U_1206_6.3V6M
1U_0402_6.3V6K2 1 C129 F9 P17 W24 Y12
VSSA12(VSSPLL_1) VDDC_25 VSS37 VSSA93
G9 VSSA12(VSSPLL_2) VDDC_26 R11 Y22 VSS38 VSSA94 Y14
VDDC_27 R13 AC23 VSS39 VSSA95 AA3
+VDDHT_PKG D22 VDDHT_PKG VDDC_28 R15 D25 VSS40 VSSA37 R9
+VDDA12_PKG1 M1 VDDA12_PKG1 VDDC_29 U11 G24 VSS41 VSSA38 AD1
+VDDA12_PKG2 AC11 VDDA12_PKG2 VDDC_30 U12 AC14 VSS42 VSSA39 AC5
VDDC_31 U14 VSSA40 AC6
VDDC_32 U15 AC22 VSS44 VSSA41 AC7
R23 VSS45 VSSA42 AD3
2006-11-13 Follow ATI reference schematic 216MQA6AVA11FG FCBGA 465P C4 AC9
VSS46 VSSA43
AE22 VSS47 VSSA44 AC10
+VDDA12_PKG1 T23 G6
VSS48 VSSA45
T25 VSS49 VSSA46 Y15
AE14 VSS50 VSSA47 AC4
2006-10-03 ATI recommend 1 follow Bowfin 2.1 R17 P9
C456 VSS51 VSSA48
H23 VSS52 VSSA49 AE6
L7 M17 AE10
0.1U_0402_16V7K~N VSS53 VSSA50
+1.2V_HT 1 2 A23 VSS54 VSSA51 M3
FBMA-L11-322513-201LMA40T_1210 2
AC15 VSS55
F17 VSS56
+1.2V_HT D4 VSS57
22U_1206_6.3V6M 2 1 C425 NB_VDDA12_HT M13 VSS59
1
AC16 VSS60
L4 H12
1U_0402_6.3V6K2 VSS61
1 C157 FBML10160808121LMT_0603 B7 VSS62
1U_0402_6.3V6K2 1 C146
2
1U_0402_6.3V6K2 1 C127
B NB_VDDA12 216MQA6AVA11FG FCBGA 465P B
C149
1U_0402_6.3V6K2 1 C145
C148
1U_0402_6.3V6K2 1 C116 1 1
1U_0402_6.3V6K
4.7U_0805_6.3V6K~N
2 2
A A
1
1 2 +3VS_CLK_VDDA 1 2
L15 L14 1 1 FBML10160808121LMT_0603
0.1U_0402_16V7K~N
10U_0805_6.3V6M C220 FBML10160808121LMT_0603 1 0_0805_5% 1 1 1 1 1 1 1 1 C177
1 2 C190 C193 C192 C188 C186 C189 C191 C187
C178
C176 22U_1206_6.3V6M
10U_0805_6.3V6M 2 2
2
C219 0.1U_0402_16V7K~N 2 2 2 2 2 2 2 2 2
1 2 +3VS_CLK_VDD48
1 22U_1206_6.3V6M 0.1U_0402_16V7K~N 0.1U_0402_16V7K~N
0.1U_0402_16V7K~N 1
+3VS
CPUCLK0_H <6>
1
U25
L16 R269
10U_0805_6.3V6M C493 54 50 261_0402_1%
FBML10160808121LMT_0603 VDDCPU VDDA
1 2 14 VDDSRC GNDA 49
23
2
VDDSRC CPUCLK0H R292
28 56 1 2 47.5_0402_1%
2
1
Y3 XTALOUT_CLK 4 24
X2 SRCCLKT3
SRCCLKC3 25
26 CLK_CARD R314 1 2 33_0402_5%CLK_PCIE_CARD CLK_PCIE_CARD <27>
SRCCLKT2 CLK_CARD# R313 33_0402_5%CLK_PCIE_CARD#
27 1 2 CLK_PCIE_CARD# <27>
2
2 CLK_RESET SRCCLKC2 CLK_LAN R290 33_0402_5%CLK_PCIE_LAN 2
11 RESET_IN# SRCCLKT0 47 1 2 CLK_PCIE_LAN <22>
1 2 61 46 CLK_LAN# R289 1 2 33_0402_5%CLK_PCIE_LAN# CLK_PCIE_LAN# <22>
NC SRCCLKC0 SBLINKCLK_R R288 33_0402_5% SBLINKCLK
SRCCLKT1 43 1 2 SBLINKCLK <11>
C481 42 SBLINKCLK#_R R287 1 2 33_0402_5% SBLINKCLK# SBLINKCLK# <11>
27P_0402_50V8J SRCCLKC1 SBSRCCLK_R R318 33_0402_5% SBSRCCLK
SRCCLKT7 12 1 2 SBSRCCLK <15>
13 SBSRCCLK#_R R317 1 2 33_0402_5% SBSRCCLK# SBSRCCLK# <15>
R321 33_0402_5% SRCCLKC7
<8,9,16,27> SMB_CK_CLK1 SMB_CK_CLK1 1 2 SMB_CCK_CLK1 9 57 CLKREQA#
SMBCLK CLKREQA# CLKREQA# <25>
<8,9,16,27> SMB_CK_DAT1 SMB_CK_DAT1 1 2 SMB_CCK_DAT1 10 32 CLKREQB#
SMBDAT CLKREQB# CLKREQB# <27>
R320 33_0402_5% 33 CLKREQC#
CLKREQC# CLKREQC#
1 2 CLKIREF 48 7
R85 475_0603_1% IREF 48MHz_1 CLK_USB R322
48MHz_0 6 1 2 33_0402_5% USBCLK_EXT USBCLK_EXT <16> USBCLK_EXT
1
64 FS0 R297 1 2 33_0402_5% SB_OSC_INT <16>
FS0/REF0 FS2 R117
FS2/REF2 62
59 CLK_HTREFCLKR294 1 2 33_0402_5% HTREFCLK <11> @ 33_0402_5%
HTTCLK0
2
1
ICS951462AGLFT_TSSOP64 2
R74
49.9_0402_1% @ C255
22P_0402_50V8J
1
2
USBCLK_EXT @ C498 1 2 10P_0402_25V8K
+3VS_CLK +3VS_CLK
NB_REFCLK @ C469 1 2 10P_0402_25V8K
EXT CLK FREQUENCY SELECT TABLE(MHZ) 1 SB_OSC_INT @ C470 1 2 10P_0402_25V8K
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
3 3
R299
R77
R295
R293
R311
R283
FS2 FS1 FS0 CPU SRCCLK HTT PCI USB COMMENT
[2:1] CLK_PCIE_WCARD R328 1 2 49.9_0402_1%
CLK_PCIE_WCARD# R327 1 2 49.9_0402_1%
2
2
0 0 0 Hi-Z 100.00 Hi-Z Hi-Z 48.00 Reserved CLK_PCIE_CARD R326 1 2 49.9_0402_1%
CLK_PCIE_CARD# R325 1 2 49.9_0402_1%
0 0 1 X 100.00 X/3 X/6 48.00 Reserved FS0 CLKREQA#
FS1 CLKREQB#
0 1 0 180.00 100.00 60.00 30.00 48.00 Reserved FS2 CLKREQC#
1
1
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
0 1 1 220.00 100.00 36.56 73.12 48.00 Reserved
R298
R76
R75
R73
R312
R284
1 0 0 100.00 100.00 66.66 33.33 48.00 Reserved
1 0 1 133.33 100.00 66.66 33.33 48.00 Reserved @ @ @ @ @ @ CLK_PCIE_LAN R268 1 2 49.9_0402_1%
2
2
CLK_PCIE_LAN# R267 1 2 49.9_0402_1%
1 1 1 200.00 100.00 66.66 33.33 48.00 Normal ATHLON64 operation
SBSRCCLK R330 1 2 49.9_0402_1%
SBSRCCLK# R329 1 2 49.9_0402_1%
4 4
+5VS +CRT_VCC
F2
W=40mils
D1 W=40mils
1 2 2 1
0.1U_0402_16V7K~N
2
150_0402_1%
150_0402_1%
150_0402_1%
8P_0402_50V8K
8P_0402_50V8K
8P_0402_50V8K
8P_0402_50V8K
8P_0402_50V8K
8P_0402_50V8K
1 1 1 3
1
1 1 1 9
R193
R195
R197
C353
C352
C351
C344
C345
C347
14
1
4
R201 2 2 2
10 17
2 2 2
15 16
2
1K_0402_5% CRT_GND 5
D11
2
BKOFF# 1 2 RB751V_SOD323 DISPOFF# SUYIN_070549FR015S208CR
<26> BKOFF# +CRT_VCC
1 2 HSYNC_L CONN@
D12 R191 0_0603_5%
@ 1 2 RB751V_SOD323 1 2 2 1 VGA_DDC_DATA_C
<11,26> ENABLT
C4 0.1U_0402_16V7K~N R200 10K_0402_5% 1 2 VSYNC_L
R192 0_0603_5%
5
1
C348
C1
1 1 1
P
OE#
C3
C2
VGA_CRT_HSYNC 1 2 CRT_HSYNC 2 4 D_CRT_HSYNC VGA_DDC_CLK_C
<11> VGA_CRT_HSYNC A Y
R196 39_0402_5% C346
G
U13 10P_0402_50V8J 1
2 2 2
100P_0402_25V8K
100P_0402_25V8K
TC7SET125FUF SC70
68P_0402_50V8K
10P_0402_50V8J
C6
68P_0402_50V8K
2 +CRT_VCC 2 R3 2
0_0805_5%
1 2 CRT_GND 2 1
C5 0.1U_0402_16V7K~N
5
1
R190
0_0805_5%
P
OE#
VGA_CRT_VSYNC 1 2 CRT_VSYNC 2 4 D_CRT_VSYNC 2 1
<11> VGA_CRT_VSYNC A Y
R199 39_0402_5%
G
U14
TC7SET125FUF SC70
3
+CRT_VCC +CRT_VCC +3VS +3VS +3VS
4.7K_0402_5%
4.7K_0402_5%
Change U13,U14 from SA411250130 to SA00000RZ00
2
0_0402_5%
6.8K_0402_5%
6.8K_0402_5%
R1 R2 R6 R5 R198
1
+LCDVDD +5VALW
2
G
1
VGA_DDC_DATA_C 1 3
R206 R207 VGA_DDC_DATA <11>
2
+3VS Q3
G
100_0402_5%
47K_0402_1% W=60mils BSS138_NL_SOT23
VGA_DDC_CLK_C 1 3
1 2
VGA_DDC_CLK <11>
S
3
D S
AP2301GN 1P SOT23
G
Q5 2 2 1 2 Q6
3 SSM3K7002FU_SC70-3 G R208 1K_0402_1% Q4 3
W=60mils BSS138_NL_SOT23
S
3
1 +LCDVDD
D
1
C373 +LCDVDD
1
D 2
41
1 1
ENVDD 2 0.047U_0402_16V7K JLCD1
<11> ENVDD
G C363 C369 1 2
GND
1 2
1
S 4.7U_0805_6.3V6K~N 0.1U_0402_16V7K~N 3 4
3
R14 Q7 2 2 3 4 LVDSLC+
5 5 6 6 LVDSLC+ <11>
10K_0402_5% +LCDVDD 7 8 LVDSLC-
7 8 LVDSLC- <11>
BSS138_NL_SOT23 9 10
9 10 LVDSL0+
+3VS 11 12 LVDSL0+ <11>
2
EDID_CLK_LCD 13 11 12 LVDSL0-
<11> EDID_CLK_LCD 13 14 14 LVDSL0- <11>
INVT_PWM +3VS EDID_DAT_LCD 15 16
<11> EDID_DAT_LCD 15 16
17 18 LVDSL1+
17 18 LVDSL1+ <11>
1
1 LVDSUC+ 19 20 LVDSL1-
<11> LVDSUC+ 19 20 LVDSL1- <11>
D13 1 LVDSUC- 21 22
<11> LVDSUC- 21 22
C360 23 24 LVDSL2+
23 24 LVDSL2+ <11>
@ 1N4148_SOT23 @ 1U_0603_10V6K C370 LVDSU0+ 25 26 LVDSL2-
2 <11> LVDSU0+ 25 26 LVDSL2- <11>
@ 0.1U_0402_16V7K~N LVDSU0- 27 28
<11> LVDSU0-
2
2 27 28 DISPOFF#
29 29 30 30
LVDSU1+ 31 32 DAC_BRIG
<11> LVDSU1+ 31 32 DAC_BRIG <26>
LVDSU1- 33 34 INVT_PWM
<11> LVDSU1- 33 34 INVT_PWM <26>
35 35 36 36
B+ LVDSU2+ 37 38 INVPWR_B+
GND
<11> LVDSU2+ 37 38
LVDSU2- 39 40 INVPWR_B+
<11> LVDSU2- 39 40
F3
1 2 INVPWR_B+
42
3A_32V 0.1U_0603_50V4Z
4 4
2 2
C361
C359
0.1U_0603_50V4Z CONN@
JST_BM40B-SRDS-G-TFCLFSN~N
1 1
A_RST# AG10
SB600 SB 23x23mm U2 PCICLK0_R R384 1 2 22_0402_5% PCICLK0_R
A_RST# PCICLK0 CLK_PCI_EC <26> PCICLK0_R <17>
Part 1 of 4 T2 PCICLK1_R R385 1 2 22_0402_5% PCICLK1_R
PCICLK1 CLK_PCI_MINI PCICLK1_R <17>
<13> SBSRCCLK SBSRCCLK J24 U1 PCICLK2_R R383 1 2 22_0402_5% PCICLK2_R
PCIE_RCLKP PCICLK2 CLK_PCI_CB <20> PCICLK2_R
PCI CLKS
<13> SBSRCCLK# SBSRCCLK# J25 V2 PCICLK3_R R381 1 2 22_0402_5% PCICLK3_R
PCIE_RCLKN PCICLK3 CLK_PCI_SIO_DB <25> PCICLK3_R
W3 PCICLK4_R
PCICLK4 PCICLK4_R <17>
SB_RX0P C500 0.1U_0402_16V7K SB_RX0P_C P29 U3 PCICLK5_R
<10> SB_RX0P PCIE_TX0P PCICLK5 PCICLK5_R
SB_RX0N C499 0.1U_0402_16V7K SB_RX0N_C P28 V1 PCICLK6_R
<10> SB_RX0N PCIE_TX0N PCICLK6 PCICLK6_R <17>
SB_RX1P C502 0.1U_0402_16V7K SB_RX1P_C M29 T1
<10> SB_RX1P PCIE_TX1P SPDIF_OUT/PCICLK7/GPIO41
SB_RX1N C501 0.1U_0402_16V7K SB_RX1N_C M28
D <10> SB_RX1N PCIE_TX1N D
SB_RX2P C504 0.1U_0402_16V7K SB_RX2P_C K29 AJ9 PCIRST# 1 R368 2 PCI_RST#
<10> SB_RX2P PCIE_TX2P PCIRST# PCI_RST# <20,25>
SB_RX2N C503 0.1U_0402_16V7K SB_RX2N_C K28 33_0402_5%
<10> SB_RX2N PCIE_TX2N
2
SB_RX3P C505 0.1U_0402_16V7K SB_RX3P_C H29
<10> SB_RX3P PCIE_TX3P
SB_RX3N C506 0.1U_0402_16V7K SB_RX3N_C H28 W7 PCI_AD0 R369
<10> SB_RX3N PCIE_TX3N AD0/ROMA18
Y1 PCI_AD1 8.2K_0402_5%
SB_TX0P AD1/ROMA17 PCI_AD2 CLK_PCI_MINI @
@C558
C558 1
<10> SB_TX0P T25 PCIE_RX0P AD2/ROMA16 W8 2 10P_0402_25V8K
<10> SB_TX0N SB_TX0N T26 W5 PCI_AD3
1
SB_TX1P PCIE_RX0N AD3/ROMA15 PCI_AD4 CLK_PCI_CB @C306
@ C306 1
<10> SB_TX1P T22 PCIE_RX1P AD4/ROMA14 AA5 2 10P_0402_25V8K
SB_TX1N PCI_AD5
1U_0603_10V6K C225
22U_0805_6.3V6M C222
2 1 AJ4 PCI_AD17
BLM21A601SPT_0805 AD17/ROMD1 PCI_AD18
U28 PCIE_PVSS AD18/ROMD2 AB1
1
AH4 PCI_AD19 U6 R136
AD19/ROMD3 PCI_AD20 33_0402_5%
F27 AB2
OE#
1 2 PCIE_VDDR_1 AD20/ROMD4 PCI_AD21 A_RST#
F28 PCIE_VDDR_2 AD21/ROMD5 AJ3 2 I O 4 1 2 NB_RST# <11,19,22,25,26,27>
F29 AB3 PCI_AD22 @
PCIE_VDDR_3 AD22/ROMD6
G
G26 AH3 PCI_AD23 2
PCIE_VDDR_4 AD23/ROMD7 PCI_AD24 74LVC1G125GW_SOT3535
G27 AC1
3
PCIE_VDDR_5 AD24 PCI_AD25 C269
G28 PCIE_VDDR_6 AD25 AH2
G29 AC2 PCI_AD26 10P_0402_25V8K
PCIE_VDDR_7 AD26 PCI_AD27 1
J27 PCIE_VDDR_8 AD27 AH1 1 2 @
J29 AD2 PCI_AD28
C PCIE_VDDR_9 AD28 PCI_AD29 R124 0_0402_5% C
L25 PCIE_VDDR_10 AD29 AG2
PCI_AD30
PCI INTERFACE
L18 L26 PCIE_VDDR_11 AD30 AD1
0.5A L29 AG1 PCI_AD31
+PCIE_VDDR PCIE_VDDR_12 AD31 PCI_CBE#0
+1.2V_HT 1 2 N29 PCIE_VDDR_13 CBE0#/ROMA10 AB9 PCI_CBE#0 <20>
AF9 PCI_CBE#1 PCI_CBE#1 <20>
CBE1#/ROMA1
C227
1U_0603_10V6K C232
1U_0603_10V6K C223
0.1U_0402_16V7K~N C507
0.1U_0402_16V7K~N C226
1 2 2 2 2 2 AG3 PCI_CBE#3 PCI_CBE#3 <20>
CBE3# PCI_FRAME#
FRAME# AA2 PCI_FRAME# <20>
AH6 PCI_DEVSEL# PCI_DEVSEL# <20>
DEVSEL#/ROMA0 PCI_IRDY#
IRDY# AG5 PCI_IRDY# <20>
2 1 1 1 1 1
22U_1206_6.3V6M
C561
1 2 SB_32KH0 C1 XTAL
15P_0402_50V8J
<6> CPU_PWRGD 1 2CPU_PWRGD_SB600 AC26
X2
CPU_PG/LDT_PG
LAD0
LAD1
AG24
AG25
LPC_AD0
LPC_AD1
LPC_AD0 <25,26>
LPC_AD1 <25,26>
BATT1 @ +
W26 AH24 LPC_AD2 2 1 RTC_BAT_PWR
INTR/LINT0 LAD2 LPC_AD2 <25,26>
R101 0_0402_5% W24 AH25 LPC_AD3
NMI/LINT1 LAD3 LPC_AD3 <25,26>
W25 AF24 LPC_FRAME#
INIT# LFRAME# LPC_FRAME# <25,26>
1
AA24 AJ24 LDRQ0#
LPC
R103 2 SMI# LDRQ0#
<6,11> LDT_STOP# 1 0_0402_5% AA23 SLP#/LDT_STP# LDRQ1#/GNT5#/GPIO68 AH26 LDRQ1# ML1220T13RE R595
AA22 W22 BMREQ#
<6> CPU_SIC_SB IGNNE#/SIC BMREQ#/REQ5#/GPIO65 BMREQ# <11>
AA26 AF23 SIRQ 510_0603_5%
<6> CPU_SID_SB A20M#/SID SERIRQ SIRQ <20,26>
Y27
CPU
R102
2
ALLOW_LDTSTOP FERR# RTC_CLK
<11> ALLOW_LDTSTOP AA25 STPCLK#/ALLOW_LDTSTP RTCCLK D3 RTC_CLK <17>
+1.8VS 2 1 AH9 F5 RTC_IRQ# R432
CPU_STP#/DPSLP_3V# RTC_IRQ#/GPIO69 RTC_IRQ# <17>
B24 0_0603_5%
DPSLP_OD#/GPIO37
1K_0402_5% W23 DPRSLPVR VBAT E1 +SB_VBAT 1 2
LDT_RST# AC25 D1
<6> LDT_RST# LDT_RST#/DPRSTP#/PROCHOT# RTC_GND
1
RTC
1 2
C621
218S6ECLA13FG FCBGA 548P C290
0.1U_0402_16V7K~N 1U_0603_10V6K D19
2 1 +SB_VBAT BAS40-04_SOT23
R372
2
510_0603_5%
1 2 CHGRTC
J7
W=20mils 1
1 2 C548
@
@ JOPEN 0.1U_0402_16V7K~N
A 2 A
C680 1 2
1U_0603_10V4Z
U600D
SB_OSC_INT
SB600 SB 23x23mm Part 4 of 4
1
EC_SWI# A3 A17 USBCLK_EXT
<26> EC_SWI# PCI_PME#/GEVENT4# USBCLK USBCLK_EXT <13>
R106 EC_SCI# B2
<26> EC_SCI# RI#/EXTEVNT0#
@ 33_0402_5% <26> SLP_S3# SLP_S3# F7 A14 11.8K_0603_1% 1 2 R349
SLP_S5# SLP_S3# USB_RCOMP
<26> SLP_S5# A5 SLP_S5#
PWRBTN_OUT#
2
SB_PWRGD PWR_BTN# USB_ATEST1
2 <6,26> SB_PWRGD B5 PWR_GOOD USB_ATEST0 A10
TP53 SB_SUS_STAT B3
D @ C234 TP55 SB_TEST2 SUS_STAT# D
F9 TEST2 USB_HSDP9+ H12
22P_0402_50V8J TP56 SB_TEST1 E9 G12
1 TP57 SB_TEST0 TEST1 USB_HSDM9-
G9 TEST0
EC_GA20 AF26 E12
<26> EC_GA20 GA20IN USB_HSDP8+ USB20P8+ <25>
KB_RST# AG26 D12
<26> KB_RST# KBRST# USB_HSDM8- USB20P8- <25>
D7 LPC_PME#/GEVENT3#
C25 LPC_SMI#/EXTEVNT1# USB_HSDP7+ E14 USB20P7+ <25>
2006-10-02 Configure unused GPIO to output D9 D14
S3_STATE/GEVENT5# USB_HSDM7- USB20P7- <25>
USB INTERFACE
F4 SYS_RESET#/GPM7#
PCIE_WAKE# E7 G14
<20,22,26,27> PCIE_WAKE# WAKE#/GEVENT8# USB_HSDP6+ USB20P6+ <27>
C2 BLINK/GPM6# USB_HSDM6- H14 USB20P6- <27>
H_THERMTRIP# G7
<6> H_THERMTRIP# SMBALERT#/THRMTRIP#/GEVENT2#
USB_HSDP5+ D16
USB_HSDM5- E16
EC_RSMRST# E2
<26> EC_RSMRST# RSMRST#
OSC / RST USB_HSDP4+ D18 USB20P4+ <27>
SB_OSC_INT B23 E18 USB20P4- <27>
+3VS <13> SB_OSC_INT 14M_OSC USB_HSDM4-
C28 SATA_IS0#/GPIO10 USB_HSDP3+ G16
2006-10-02 Configure unused GPIO to output A26 H16
PWM_CTRL ROM_CS#/GPIO1 USB_HSDM3-
B29 GHI#/SATA_IS1#/GPIO6
R336 1 2 10K_0402_5% PWM_CTRL A23 G18 USB20P2+ <28>
WD_PWRGD/GPIO7 USB_HSDP2+
B27 SMARTVOLT/SATA_IS2#/GPIO4 USB_HSDM2- H18 USB20P2- <28>
D23 SHUTDOWN#/GPIO5
<23> SB_SPKR SB_SPKR B26 D19 USB20P1+ <28>
R341 1 SMB_CK_CLK1 SMB_CK_CLK1 SPKR/GPIO2 USB_HSDP1+
2 2.2K_0402_5% <8,9,13,27> SMB_CK_CLK1 C27 SCL0/GPOC0# USB_HSDM1- E19 USB20P1- <28>
SMB_CK_DAT1 B28
GPIO
<8,9,13,27> SMB_CK_DAT1 SDA0/GPOC1#
R335 1 2 2.2K_0402_5% SMB_CK_DAT1 C3 G19 USB20P0+ <28>
2006-10-02 Configure unused GPIO to output SCL1/GPOC2# USB_HSDP0+
F3 SDA1/GPOC3# USB_HSDM0- H19 USB20P0- <28>
R104 1 2 10K_0402_5% D26 +3VS
R105 1 DDC1_SCL/GPIO9
2 10K_0402_5% C26 DDC1_SDA/GPIO8
L27
A27 B9 +AVDDTX 1 2
SSMUXSEL/SATA_IS3#/GPIO0 AVDDTX_0
0.1U_0402_16V7K~N C253
0.1U_0402_16V7K~N C262
0.1U_0402_16V7K~N C263
C273
C256
C274
C254
C C
A4 LLB#/GPIO66 AVDDTX_1 B11 1 1 1 1 1 1 1
2006-10-02 Configure unused GPIO to output B13 KC FBM-L11-201209-221LMAT_0805
AVDDTX_2
AVDDTX_3 B16
C6 USB_OC9#/SLP_S2/GPM9# AVDDTX_4 B18
2 2 2 2 2 2 2
22U_1206_6.3V6M
1U_0603_10V6K
1U_0603_10V6K
1U_0603_10V6K
C5 USB_OC8#/AZ_DOCK_RST#/GPM8# AVDDRX_0 A9
EC_SMI# C4 B10
<26> EC_SMI# USB_OC7#/GEVENT7# AVDDRX_1
NC_PWR_EN# B4 B12
<27> NC_PWR_EN# USB_OC6#/GEVENT6# AVDDRX_2
B6 USB_OC5#/DDR3_RST#/GPM5# AVDDRX_3 B14
A6 USB_OC4#/GPM4# AVDDRX_4 B17
USB OC
R139 1 2 10K_0402_5% SB_HD_RST# OVCUR#3 C8
<28> OVCUR#3 USB_OC3#/GPM3#
EC_LID_OUT# C7 A12 +AVDDC
<26> EC_LID_OUT# USB_OC2#/GPM2# AVDDC
@ OVCUR#1 B8
<28> OVCUR#1 USB_OC1#/GPM1#
OVCUR#0 A8 A13
<28> OVCUR#0 USB_OC0#/GPM0# AVSSC
AVSS_USB_1 A16
33_0402_5% 1 2 R422 SB_HD_BITCLK N2 C9
2007-01-15 <23> HD_BITCLK AZ_BITCLK AVSS_USB_2
33_0402_5% 1 2 R387 SB_HD_SDOUT
AZALIA
<23> HD_SDOUT M2 AZ_SDOUT AVSS_USB_3 C10
Change SDIN to AZ_SDIN3 HD_SDIN3 K2 C11
<23> HD_SDIN3 AZ_SDIN3/GPIO46 AVSS_USB_4 +3VS
33_0402_5% 1 2 R138 SB_HD_SYNC L3 C12 KC FBM-L11-201209-221LMAT_0805
<23> HD_SYNC AZ_SYNC AVSS_USB_5
33_0402_5% 1 2 R158 SB_HD_RST# K3 C13 L44
<23> HD_RST# AZ_RST# AVSS_USB_6
C14 +AVDDC 1 2
AVSS_USB_7
L1 C16
USB PWR
AC_BITCLK/GPIO38 AVSS_USB_8
<17> AC97_SDOUT L2 AC_SDOUT/GPIO39 AVSS_USB_9 C17
HD_SDIN0 L4 C18
<23> HD_SDIN0 ACZ_SDIN0/GPIO42 AVSS_USB_10
J2 C19 C534 1 2 2.2U_0603_10V6K
ACZ_SDIN1/GPIO43 AVSS_USB_11
AC97
J4 ACZ_SDIN2/GPIO44 AVSS_USB_12 C20
M3 D11 C533 1 2 0.1U_0402_16V7K~N
AC_SYNC/GPIO40 AVSS_USB_13
L5 AC_RST#/GPIO45 AVSS_USB_14 D21
AVSS_USB_15 E11
AVSS_USB_16 E21
AVSS_USB_17 F11
E23 NC1 AVSS_USB_18 F12
B 33_0402_5% 1 B
<23> MDC_HD_SYNC 2 R146 SB_HD_SYNC AC21 NC2 AVSS_USB_19 F14
AD7 NC3 AVSS_USB_20 F16
33_0402_5% 1 2 R159 SB_HD_RST# AE7 F18
<23> MDC_HD_RST# NC4 AVSS_USB_21
AA4 NC5 AVSS_USB_22 F19
33_0402_5% 1 2 R423 SB_HD_SDOUT T4 F21
<23> MDC_HD_SDOUT NC6 AVSS_USB_23
D4 NC7 AVSS_USB_24 G11
47_0402_5% 1 2 R386 SB_HD_BITCLK AB19 G21
<23> MDC_HD_BITCLK NC8 AVSS_USB_25
AVSS_USB_26 H11
Change R386 from 33ohm to 47ohm (For EMI) AVSS_USB_27 H21
J11
AVSS_USB_28
AVSS_USB_29 J12
AVSS_USB_30 J14
AVSS_USB_31 J16
AVSS_USB_32 J18
AVSS_USB_33 J19
A A
SATA_DTX_IRX_P0
U600B
REQUIRED STRAPS
SATA_DTX_IRX_N0
AH21 SATA_TX0+ SB600 SB 23x23mm IDEIORDYA
AJ21 SATA_TX0-
Part 2 of 4
IDE_IORDY AB29
AA28 IDEIRQA
IDEIORDYA <19> SB600 HAS 15K INTERNAL PD FOR AC_SDATA_OUT,
IDE_IRQ IDEIRQA <19>
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0
AH20
AJ20
SATA_RX0- IDE_A0 AA29
AB27
IDESAA0
IDESAA1
IDESAA0 <19> 15K PU FOR RTC_CLK, EXTERNAL PU/PD IS
SATA_RX0+ IDE_A1 IDESAA1 <19>
IDE_A2 Y28 IDESAA2
IDEDACK#A
IDESAA2 <19> NOT REQUIRED; FOR SB460, EXTERNAL PU/PD ARE
AH18 AB28 IDEDACK#A <19>
AJ18
SATA_TX1+
SATA_TX1-
IDE_DACK#
IDE_DRQ AC27 IDEREQA
IDEREQA <19> REQUIRED
AC29 IDEIOR#A
IDE_IOR# IDEIOR#A <19>
AH17 AC28 IDEIOW#A
D SATA_RX1- IDE_IOW# IDEIOW#A <19> D
AJ17 W28 IDECS#A1 IDECS#A1 <19>
SATA_RX1+ IDE_CS1# IDECS#A3
IDE_CS3# W27 IDECS#A3 <19>
AH13 +3VS +3VALW +3VALW +3VS +3VS +3VS +3VS
SATA_TX2+ IDEDA[0..15] <19>
AH14 AD28 IDEDA0
SATA_TX2- IDE_D0/GPIO15 IDEDA1
IDE_D1/GPIO16 AD26
1
AH16 AE29 IDEDA2
SATA_RX2- IDE_D2/GPIO17 IDEDA3 R424 R140 R147 R144 R382 R154 R157
SERIAL ATA
AJ16 AF27
ATA 66/100
SATA_RX2+ IDE_D3/GPIO18 IDEDA4 2.2K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
IDE_D4/GPIO19 AG29
AJ11 AH28 IDEDA5 @ @ @ @ @
SATA_TX3+ IDE_D5/GPIO20 IDEDA6
AH11 AJ28
2
SATA_TX3- IDE_D6/GPIO21 IDEDA7
IDE_D7/GPIO22 AJ27
AH12 AH27 IDEDA8
SATA_RX3- IDE_D8/GPIO23 <16> AC97_SDOUT
AJ13 AG27 IDEDA9
SATA_RX3+ IDE_D9/GPIO24 <15> RTC_IRQ#
R116 1K_0402_1% AG28 IDEDA10
IDE_D10/GPIO25 <15> RTC_CLK
2 1 SATA_CAL AF12 AF28 IDEDA11
SATA_CAL IDE_D11/GPIO26 <15> PCICLK4_R
AF29 IDEDA12
IDE_D12/GPIO27 <15> PCICLK6_R
SATA_X1 AD16 AE28 IDEDA13
SATA_X1 IDE_D13/GPIO28 <15> PCICLK0_R
AD25 IDEDA14
IDE_D14/GPIO29 <15> PCICLK1_R
SATA_X2 AD18 AD29 IDEDA15
SATA_X2 IDE_D15/GPIO30
1
R126
10K_0402_5% +PLLVDD_ATA AD14 R145 R155 R156
PLLVDD_SATA_1 10K_0402_5% 10K_0402_5% 10K_0402_5%
<29> SATA_LED# AJ10 PLLVDD_SATA_2 SPI_DI/GPIO12 J3
J6 @
+XTLVDD_ATA SPI_DO/GPIO11
0.6A AC16 G3
2
L23 XTLVDD_SATA SPI_CLK/GPIO47
SPI ROM
SPI_HOLD#/GPIO31 G2
+1.2V_HT 1 2+1.2V_AVDD_SATA AE14 AVDD_SATA_1 SPI_CS#/GPIO32 G6
FBMA-L11-201209-221LMA30T AE16 AVDD_SATA_2
1 1 1 1 1 AE18 AVDD_SATA_3 LAN_RST#/GPIO13 C23
C238 C229 C248 C239 AE19 G5 AC97_SDOUT RTC_CLK PCICLK4_R PCICLK6_R PCICLK1_R PCICLK0_R
C240 AVDD_SATA_4 ROM_RST#/GPIO14
AF19 AVDD_SATA_5
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
C C
AF21 AVDD_SATA_6 FANOUT0/GPIO3 M4
2 2 2 2 2
22U_1206_6.3V6M
2
AJ14 AVDD_SATA_12 FANIN2/GPIO52 W4
R137 STRAPS DEFAULT H, L = LPC I ROM DEFAULT
1
TEMPIN1/GPIO62
AB14 AVSS_SATA_1 TEMPIN2/GPIO63 T8 PULL IGNORE EXTERNAL USE EXT. CPU IF=P4 L, L = FWH ROM
AB16 T7 EC_THERM#
2006-10-03 Change Bead 3A (ATI recommend) AVSS_SATA_2 TEMPIN3/TALERT#/GPIO64 EC_THERM# <26> LOW DEBUG RTC 48MHZ NOTE: FOR SB460, PCICLK[8:7] ARE
AB18
HW MONITOR
AVSS_SATA_3 STRAPS CONNECTED TO SUBSTRATE
AC14 AVSS_SATA_4 VIN0/GPIO53 V5
DEFAULT DEFAULT BALLS PCICLK[1:0]
AC18 AVSS_SATA_5 VIN1/GPIO54 L7
AC19 AVSS_SATA_6 VIN2/GPIO55 M8
AD12 V6 2006-10-02 GPIO50-64 configure to output
AVSS_SATA_7 VIN3/GPIO56
AD19 AVSS_SATA_8 VIN4/GPIO57 M6
AD21 P4
AE12
AE21
AVSS_SATA_9
AVSS_SATA_10
AVSS_SATA_11
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60
M7
V7
+3VS
DEBUG STRAPS PCI_AD[0..31] PCI_AD[0..31] <15,20>
AF11 AVSS_SATA_12
C525
2 1 SATA_X1
AF14
AF16
AVSS_SATA_13 SB600 HAS 15K INTERNAL PU FOR PCI_AD[28:23]
AVSS_SATA_14
0.1U_0402_16V7K~N
AF18 AVSS_SATA_15 AVDD N1
1
2.2U_0603_10V6K
12P_0402_50V8J~N AG11 1 1 +3VS +3VS +3VS +3VS
AVSS_SATA_16
2
R347 AG12 M1
Y4 10M_0402_5% AVSS_SATA_17 AVSS C286 C287
AG13 AVSS_SATA_18
1
25MHZ_12P_X8A025000FC1H-H AG14 AVSS_SATA_19 2 2 R377 R379 R378 R380
AG16
1
AVSS_SATA_20
2 1 C520 SATA_X2 AG17 AVSS_SATA_21
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
B B
AG18 AVSS_SATA_22 @ @ @ @
10P_0402_50V8J AG19
2
AVSS_SATA_23
AG20 AVSS_SATA_24
AG21 AVSS_SATA_25
AH10 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24
AVSS_SATA_26 2007-01-17 ATI recommend
AH19 AVSS_SATA_27
0.1A L25 2.2K IF USED FOR SB600.
+1.2V_HT 1 2 +PLLVDD_ATA
CHB1608U301_0603 10K IF USED FOR SB460.
218S6ECLA13FG FCBGA 548P
1 1
1
C258 C249
R150 R152 R151 R153
1U_0402_6.3V6K 1U_0402_6.3V6K 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
2 2 @ @ @ @
2
PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24
L24
+3VS 1 2 +XTLVDD_ATA
CHB1608U301_0603 SATA_DTX_IRX_N0 2 1 SATA_DTX_C_IRX_N0 USE PCI USE ACPI USE IDE USE DEFAULT
C519 0.01U_0402_16V7K SATA_DTX_C_IRX_N0 <19>
1 PULL PLL BCLK PLL PCIE STRAPS
C250 SATA_DTX_IRX_P0 2 1 SATA_DTX_C_IRX_P0 HIGH
C514 0.01U_0402_16V7K SATA_DTX_C_IRX_P0 <19> DEFAULT DEFAULT DEFAULT DEFAULT
1U_0402_6.3V6K 2
SATA_ITX_DRX_N0 2 1 SATA_ITX_C_DRX_N0
C579 0.01U_0402_16V7K SATA_ITX_C_DRX_N0 <19>
PULL BYPASS BYPASS BYPASS IDE USE EEPROM
SATA_ITX_DRX_P0 SATA_ITX_C_DRX_P0 LOW PCI PLL ACPI PLL PCIE STRAPS
2 1 SATA_ITX_C_DRX_P0 <19>
A C578 0.01U_0402_16V7K BCLK A
close to connector
U600C
C513 150U_D2_6.3VM 0.6A +3VALW +3VALW TO +3VALW_SB
2 1 A25 VDDQ_1 SB600 SB 23x23mm
+
A28 VDDQ_2 VSS_2 A20
C29 Part 3 of 4 A21 R370
C261 1U_0603_10V6K VDDQ_3 VSS_3 0_0805_5%
1 2 D24 VDDQ_4 VSS_4 A29
C230 1 2 1U_0603_10V6K L9 B1 2 1
C284 1U_0603_10V6K VDDQ_5 VSS_5 Q47 +3VALW_SB
1 2 L21 VDDQ_6 VSS_6 B7
C243 1 2 1U_0603_10V6K M5 B25
VDDQ_7 VSS_7
D
C285 1 2 1U_0603_10V6K P3 C21 6
S
C235 1U_0603_10V6K VDDQ_8 VSS_8
1 2 P9 VDDQ_9 VSS_9 C22 5 4
T5 VDDQ_10 VSS_10 C24 2
V9 VDDQ_11 VSS_11 D6 1
W2 E24 SI3456BDV-T1-E3_TSOP6 1 1
G
VDDQ_12 VSS_12 @
W6 F2
3
VDDQ_13 VSS_13 C541 1 C550 C549
W21 VDDQ_14 VSS_14 F23
+1.2V_HT W29 G1 1U_0603_10V6K 1U_0603_10V6K
VDDQ_15 VSS_15 2 2
AA12 VDDQ_16 VSS_16 J1
AA16 J8 4.7U_0805_6.3V6K~N
VDDQ_17 VSS_17 2 +5VALW
1A AA19 VDDQ_18 VSS_18 L6
1
AC4 VDDQ_19 VSS_19 L8
AC23 VDDQ_20 VSS_20 M9
2
L26 AD27 M12 R390
FBM-L11-321611-260-LMT_1206 VDDQ_21 VSS_21 0_0603_5% 100K_0603_5% R431
AE1 VDDQ_22 VSS_22 M15
AE9 M18 1 2 1 2 @ 10K_0402_5%
VDDQ_23 VSS_23 B+_BIAS
AE23 N13 R389 @
2
VDDQ_24 VSS_24 @
AH29 N17 1
1
VDDQ_25 VSS_25
1
2006-10-03 Change to 1uF (ATI recommend) D
AJ2 VDDQ_26 VSS_26 P1
AJ6 P6 C563 Q50 2 SBPWR_EN#
C241 2 VDDQ_27 VSS_27
1 22U_1206_6.3V6M AJ26 VDDQ_28 VSS_28 P21 0.22U_0603_10V7K @ G
2 SSM3K7002FU_SC70-3 @
R12 S
3
+3VALW_SB C252 1U_0603_10V6K VSS_29
1 2 M13 VDD_1 VSS_30 R15
C260 1 2 1U_0603_10V6K M17 R18
C242 1U_0603_10V6K VDD_2 VSS_31
1 2 N12 VDD_3 VSS_32 T6
1
C547 D
2 1 22U_1206_6.3V6M C259 1 2 1U_0603_10V6K N15 VDD_4 VSS_33 T9
C251 1 2 1U_0603_10V6K +1.2VS_SB_VDD N18 U13 SBPWR_EN 2 Q49
VDD_5 VSS_34 <26> SBPWR_EN
C298 1 2 0.1U_0402_16V7K~N R13 U17 G SSM3K7002FU_SC70-3
C539 0.1U_0402_16V7K~N VDD_6 VSS_35
1 2 R17 V3 S@
3
C540 0.1U_0402_16V7K~N VDD_7 VSS_36
1 2 U12 VDD_8 VSS_37 V8
C559 1 2 0.1U_0402_16V7K~N U15 V12
VDD_9 VSS_38
1
C271 1 2 0.1U_0402_16V7K~N U18 V15
VDD_10 VSS_39 R430
V13 VDD_11 VSS_40 V18
V17 V21 10K_0402_5%
VDD_12 VSS_41 @
VSS_42 W1
0.1A A2 W9
2
+3VALW_SB S5_3.3V_1 VSS_43
A7 S5_3.3V_2 VSS_44 Y29
POWER
F1 S5_3.3V_3 VSS_45 AA11
J5 S5_3.3V_4 VSS_46 AA14
J7 S5_3.3V_5 VSS_47 AA18
+1.2VALW_SB K1 AC6
S5_3.3V_6 VSS_48
VSS_49 AC24
0.1A G4 S5_1.2V_1 VSS_50 AD9
C299
C288
C289
C272
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
D
D27 6
S
L20 2006-10-03 Change to 1uF (ATI recommend) PCIE_VSS_1
PCIE_VSS_2 D28 5 4
+1.8VS 1 2 +SB_CPUPWR AA27 D29 2
FBML10160808121LMT_0603 CPU_PWR PCIE_VSS_3
PCIE_VSS_4 F26 1
+V5_VREF AE11 G23 SI3456BDV-T1-E3_TSOP6 1 2
G
V5_VREF PCIE_VSS_5 @ C301 C300
1 G24
3
+SB_AVDDCK PCIE_VSS_6 C308 1
A24 AVDDCK_3.3V PCIE_VSS_7 G25
C231 H27 4.7U_0805_6.3V6K~N 0.1U_0402_16V7K~N
0.1U_0402_16V7K~N +SB_AVDDCK_1.2V A22 PCIE_VSS_8 2 1
AVDDCK_1.2V PCIE_VSS_9 J23
2 4.7U_0805_6.3V6K~N
PCIE_VSS_10 J26
2
B22 AVSSCK PCIE_VSS_11 J28
R123 K27
1K_0402_5% PCIE_VSS_12
V29 PCIE_VSS_42 PCIE_VSS_13 L22
+5VS 0.1A 1 2 V28 L23 R161
PCIE_VSS_41 PCIE_VSS_14 R388 100K_0603_5%
2 V27 PCIE_VSS_40 PCIE_VSS_15 L24
V26 PCIE_VSS_39 PCIE_VSS_16 L27 1 2 1 2 B+_BIAS
D4 C257 V25 L28 10K_0603_1% @
RB751V_SOD323 1U_0603_10V6K PCIE_VSS_38 PCIE_VSS_17 @
V24 PCIE_VSS_37 PCIE_VSS_18 M21 1
1
1 C562 D
+3VS 2 1 V23 PCIE_VSS_36 PCIE_VSS_19 M24
V22 M27 Q48 2 SBPWR_EN#
PCIE_VSS_35 PCIE_VSS_20 0.22U_0603_10V7K @ G
U27 PCIE_VSS_34 PCIE_VSS_21 N27
2
T29 N28 @ S
3
PCIE_VSS_33 PCIE_VSS_22
T28 PCIE_VSS_32 PCIE_VSS_23 P22
T27 PCIE_VSS_31 PCIE_VSS_24 P23
T24 P24 SSM3K7002FU_SC70-3
PCIE_VSS_30 PCIE_VSS_25
T21 PCIE_VSS_29 PCIE_VSS_26 P25
L22 P27 P26
FBML10160808121LMT_0603 PCIE_VSS_28 PCIE_VSS_27
+3VS 1 2 +SB_AVDDCK
218S6ECLA13FG FCBGA 548P
2 1
4.7U_0805_6.3V6K~N C522
2 1
0.1U_0402_16V7K~N C515
L19
FBML10160808121LMT_0603
+1.2V_HT 1 2 +SB_AVDDCK_1.2V
2 1
4.7U_0805_6.3V6K~N C237
2 1
0.1U_0402_16V7K~N C236
ODD_ACT_LED#
<29> ODD_ACT_LED#
IDEDA[0..15] <17>
+5VS
C183 47P_0402_50V8J
CDROM CONN
2 1 JODD1
1 1 2 2 1 1 1 1
D C441 D
3 3 4 4
NB_RST# IDEDA8 C449 C450 C440
<11,15,22,25,26,27> NB_RST# 5 5 6 6
1000P_0402_50V7K~N
1U_0603_10V6K
10U_0805_10V4Z~N
0.1U_0402_16V7K~N
IDEDA7 7 8 IDEDA9
IDEDA6 7 8 IDEDA10 2 2 2 2
9 9 10 10
IDEDA5 11 12 IDEDA11
IDEDA4 11 12 IDEDA12
13 13 14 14
IDEDA3 15 16 IDEDA13
IDEDA2 15 16 IDEDA14
17 17 18 18
IDEDA1 19 20 IDEDA15
+5VS IDEDA0 19 20 IDEREQA
21 21 22 22 Close to ODD Conn
23 24 IDEIOR#A IDEREQA <17>
IDEIOW#A 23 24 IDEIOR#A <17>
<17> IDEIOW#A 25 25 26 26
1
IDEIORDYA 27 28 IDEDACK#A
<17> IDEIORDYA 27 28 IDEDACK#A <17>
R256 IDEIRQA 29 30
<17> IDEIRQA 29 30
100K_0402_5% <17> IDESAA1 IDESAA1 31 32 PDIAG# 1 R257 2@ 10K_0402_5% +5VS
IDESAA0 31 32 IDESAA2
<17> IDESAA0 33 33 34 34 IDESAA2 <17>
IDECS#A1 35 36 IDECS#A3
2
<17> IDECS#A1 35 36 IDECS#A3 <17>
ODD_ACT_LED# 37 38
37 38 +5VS
+5VS
39 39 40 40 80mils
41 41 42 42
43 43 44 44
45 45 46 46
2 1 SD_CSEL 47 48
R242 470_0402_5% 47 48
49 49 50 50 1 2 +5VS
51 52 R243
GND GND 100K_0402_5%
53 GND GND 54
@
SUYIN_800059MR050S119ZL
CONN@
If CDROM is Slave
C C
then SD_CSEL= Floating
else SD_CSEL= Low
+5VS
1 1 1 1
+
JSATA1 C543 C564 C295 C294 C277
150U_D2_6.3VM
2 2 2 2 2
10U_0805_10V4Z~N
S1 GND
SATA_DTX_C_IRX_P0 S2
<17> SATA_DTX_C_IRX_P0 SATA_DTX_C_IRX_N0 HTX+ 0.1U_0402_16V7K~N 1000P_0402_50V7K~N
<17> SATA_DTX_C_IRX_N0 S3 HTX-
B B
S4 GND
SATA_ITX_C_DRX_N0 S5
<17> SATA_ITX_C_DRX_N0 SATA_ITX_C_DRX_P0 HRX-
<17> SATA_ITX_C_DRX_P0 S6 HRX+
S7 GND
27 +3VS
NC
NC 28
+3VS P1 VCC3.3
P2 10U_0805_10V4Z~N 0.1U_0402_16V7K~N
VCC3.3
P3 VCC3.3
P4 GND 1 1 1 1
P5 GND GND 23
P6 24 C565 @ C311 C570 C569
GND GND
+5VS P7 VCC5 GND 25
2 2 2 2
P8 VCC5 GND 26
P9 VCC5
P10 0.1U_0402_16V7K~N 1000P_0402_50V7K~N
GND
P11 RESERVED
P12 GND
P13 VCC12
Close to SATA HDD
P14 VCC12
P15 VCC12
SUYIN_127043FR022G226ZL
CONN@
A A
U32A
<15,17> PCI_AD[0..31] CBS_CAD[0..31] <21>
PCI_AD31 M2 B19 CBS_CAD31
PCI_AD30 AD31 CAD31/CDATA10 CBS_CAD30 +3V_PHY
M1 AD30 CAD30/CDATA9 C18
PCI_AD29 N5 D19 CBS_CAD29
PCI_AD28 AD29 CAD29/CDATA1 CBS_CAD28 U32B
N4 D18
PCI_AD27
PCI_AD26
N2
N1
AD28
AD27 R5C841 CAD28/CDATA8
CAD27/CDATA0 E19
E16
CBS_CAD27
CBS_CAD26 C575
D11 CPS MDIO00 B1
A2
SDDET#_XDDET0# <21>
PCI_AD25
PCI_AD24
P5
P4
AD26
AD25
CAD26/CADR0
CAD25/CADR1 F18
F15
CBS_CAD25
CBS_CAD24
2 1 R5C841XI R5C841XI A16
R5C841XO B16 XI R5C841 MDIO01
MDIO02 A3
B3
MSDET#_XDDET1# <21>
XDCE# <21>
AD24 CAD24/CADR2 XO MDIO03 SDWP#_XDRB# <21>
PCI_AD23 R4 G18 CBS_CAD23 15P_0402_50V8J C574
1 2 0.01U_0402_16V7K A14 B4
AD23 CAD23/CADR3 FIL0 MDIO04 SD_EN <21>
PCI_AD22 R2 G15 CBS_CAD22 A5
AD22 CAD22/CADR4 MDIO05 XDWP <21>
2
PCI_AD21 R1 H18 CBS_CAD21 X1 IEEE1394_TPAP0 B12 B5 SDLED#_MSLED#_XDLED#
PCI_AD20 AD21 CAD21/CADR5 CBS_CAD20 IEEE1394_TPAN0 TPAP0 MDIO06
T2 AD20 CAD20/CADR6 H15 A12 TPAN0 MDIO07 D5
PCI_AD19 T1 J18 CBS_CAD19 A6 R376
AD19 CAD19/CADR25 MDIO08 SDCMD_MSBS_XDWE# <21>
PCI_AD18 U2 J16 CBS_CAD18 24.576MHz_16P_3XG-24576-43E1 IEEE1394_TPBP0 B13 B6 2 1 SDCLK_MSCLK_XDRE# <21>D
1
D PCI_AD17 AD18 CAD18/CADR7 CBS_CAD17 IEEE1394_TPBN0 TPBP0 MDIO09 22_0402_5%
U1 AD17 CAD17/CADR24 J15 A13 TPBN0 MDIO10 D6 SDDATA0_MSDATA0_XDDATA0 <21>
PCI_AD16 V1 P16 CBS_CAD16 C576 E6
AD16 CAD16/CADR17 MDIO11 SDDATA1_MSDATA1_XDDATA1 <21>
PCI_AD15 T7 P19 CBS_CAD15 2 1 R5C841XO B10 A7
AD15 CAD15/IOWR# TPAP1 MDIO12 SDDATA2_MSDATA2_XDDATA2 <21>
PCI_AD14 V7 R19 CBS_CAD14 A10 B7
AD14 CAD14/CADR9 R391 TPAN1 MDIO13 SDDATA3_MSDATA3_XDDATA3 <21>
PCI_AD13 W7 P18 CBS_CAD13 12P_0402_50V8J~N D7
AD13 CAD13/IORD# MDIO14 XDDATA4 <21>
PCI_AD12 R8 R18 CBS_CAD12 1 2 B11 E7
AD12 CAD12/CADR11 TPBP1 MDIO15 XDDATA5 <21>
PCI_AD11 T8 T19 CBS_CAD11 A11 A8
AD11 CAD11/OE# TPBN1 MDIO16 XDDATA6 <21>
PCI_AD10 V8 T18 CBS_CAD10 B8
AD10 CAD10/CE2# 0_0402_5% MDIO17 XDDATA7 <21>
PCI_AD9 W8 U19 CBS_CAD9 D8
AD9 CAD9/CADR10 MDIO18 XDCLE <21>
PCI_AD8 R9 U18 CBS_CAD8 IEEE1394_TPBIAS0 D12 E8
AD8 CAD8/CDATA15 TPBIAS0 MDIO19 XDALE <21>
PCI_AD7 V9 W17 CBS_CAD7 D10
AD7 CAD7/CDATA7 TPBIAS1
1
PCI_AD6 W9 V17 CBS_CAD6
PCI_AD5 AD6 CAD6/CDATA13 CBS_CAD5 R359
T11 AD5 CAD5/CDATA6 W16 D13 VREF
PCI_AD4 V11 V16 CBS_CAD4 B14 0_0402_5%
AD4 CAD4/CDATA12 REXT
0.01U_0402_16V7K
PCI_AD3 W11 W15 CBS_CAD3
PCI_AD2 AD3 CAD3/CDATA5 CBS_CAD2
T12 V15
2
AD2 CAD2/CDATA11
10K_0603_1%
PCI_AD1 V12 T15 CBS_CAD1 2 V14
AD1 CAD1/CDATA4 USBDP
2
C589
PCI_AD0 W12 R14 CBS_CAD0 W14
AD0 CAD0/CDATA3 USBDM
R436
<21> VPPEN0 V13 VPPEN0
CBS_CC/BE3# 1
<15> PCI_CBE#3 P2 C/BE3# CC/BE3#/REG# F16 CBS_CC/BE3# <21> <21> VPPEN1 W13 VPPEN1
<15> PCI_CBE#2 W2 K18 CBS_CC/BE2#
CBS_CC/BE2# <21>
1
C/BE2# CC/BE2#/CADR12 CBS_CC/BE1#
<15> PCI_CBE#1 W6 C/BE1# CC/BE1#/CADR8 P15 CBS_CC/BE1# <21> <21> VCC5EN# R13 VCC5EN#
<15> PCI_CBE#0 T9 V19 CBS_CC/BE0# T13
C/BE0# CC/BE0#/CE1# CBS_CC/BE0# <21> <21> VCC3EN# VCC3EN#
R7 REGEN#
PCI_PAR V6 N15 CBS_CPAR
<15> PCI_PAR PAR CPAR/CADR13 CBS_CPAR <21> +3V Function Seclect
100K_0402_5%
R5C841_CSP208~D
1
R394
PCI_FRAME# V3 K16 CBS_CFRAME# 1 2
<15> PCI_FRAME# FRAME# CFRAME#/CADR23 CBS_CFRAME# <21>
PCI_TRDY# W4 L16 R395 UDIO3 UDIO4 VPPEN0 SD MS
<15> PCI_TRDY# TRDY# CTRDY#/CADR22 CBS_CTRDY# <21>
PCI_IRDY# V4 K15 CBS_CIRDY# 100K_0402_5%
C <15> PCI_IRDY# IRDY# CIRDY#/CADR15 CBS_CIRDY# <21> C
PCI_STOP# V5 M16 CBS_CSTOP#
<15> PCI_STOP# CBS_CSTOP# <21>
2
PCI_DEVSEL# T5 STOP# CSTOP#/CADR20 CBS_CDEVSEL#
<15> PCI_DEVSEL# DEVSEL# CDEVSEL#/CADR21 L18 CBS_CDEVSEL# <21> 0 0 0 X X
PCI_AD21 1 2 CBS_IDSEL P1 N19 CBS_CBLOCK#
IDSEL RESERVED/CADR19 CBS_CBLOCK# <21>
100_0402_5% R365 N18 CBS_CPERR#
CPERR#/CADR14 CBS_CPERR# <21>
G16 CBS_CSERR# 0 0 1 X X Enable
CSERR#/WAIT# CBS_CSERR# <21> R375
PCI_PERR# W5 G19 CBS_CREQ#
<15> PCI_PERR# PERR# CREQ#/INPACK# CBS_CREQ# <21>
PCI_SERR# T6 M15 CBS_CGNT# SDLED#_MSLED#_XDLED# 1 @ 2 CARD_LED <29>
<15> PCI_SERR# SERR# CGNT#/WE# CBS_CGNT# <21>
E18 CBS_CSTSCHNG 0 1 0 X Enable
CSTSCHG/BVD1(STSCHG#/RI#) CBS_CSTSCHNG <21>
A18 CBS_CCLKRUN#
CCLKRUN#/WP(IOIS16#) CBS_CCLKRUN# <21> 0_0402_5%
M4 L19 CBS_CCLK_INTERNAL 2 1
<15> PCI_REQ#0 REQ# CCLK/CADR16 CBS_CCLK <21>
M5 R435 22_0402_5% 0 1 1 X Enable Enable
<15> PCI_GNT#0 GNT#
M18 CBS_CINT#
CINT#/RDY(IREQ#) CBS_CINT# <21>
<15> CLK_PCI_CB SHIELD GND K1 PCICLK CBS_CCD2# <21> 1 0 0 Enable X X
<15,25> PCI_RST# PCI_RST# L4 PCIRST# CBS_CCD1# <21>
CBS_GRST# G2 H19 CBS_CRST#
GBRST# CRST#/RESET CBS_CRST# <21>
2
0_0402_5%
R367 1 2 @ 0_0402_5% L5 1 2 1 0 1 Enable X Enable
+3V <15,26> PM_CLKRUN# CLKRUN#
R434
C585 0.01U_0402_16V7K
R366 1 2 10K_0402_5% F19 CBS_CAUDIO CBS_CAUDIO <21> R433
CAUDIO/BVD2(SPKR#/LED) 0_0402_5%
J2 INTA#
1 1 0 Enable Enable X
1
K4
1
R362 INTB# CBS_CCD1C#
<15> PCI_PIRQE# K2 INTC# CCD1#/CD1# T14
100K_0402_5% D15 CBS_CCD2C#
* 1 1 1 Enable Enable Enable
<15> PCI_PIRQF# CCD2#/CD2#
270P_0402_50V7K
270P_0402_50V7K
R16 CBS_CVS1
<15> PCI_PIRQG# CVS1/VS1# CBS_CVS1 <21>
J4 H16 CBS_CVS2 2 2
<15,26> SIRQ CBS_CVS2 <21>
2
C582
C577
CBS_GRST# H1 UDIO1
1 H2 UDIO2
R356 1 2 10K_0402_5% UDIO3 H4 W18 CBS_RSVD/D14
UDIO3 RESERVED/CDATA14 CBS_RSVD/D14 <21> 1 1
C531 R364 1 2 10K_0402_5% UDIO4 H5 C19 CBS_RSVD/D2
UDIO4 RESERVED/CDATA2 CBS_RSVD/D2 <21>
1U_0603_10V6K G1 N16 CBS_RSVD/A18
2 UDIO5 RESERVED/CADR18 CBS_RSVD/A18 <21>
R357 1 @ 2 0_0402_5%
B <16,22,26,27> PCIE_WAKE# B
G4 RI_OUT#/PME#
PCM_SPK# F1
PCM_SPK# SPKROUT
F2 HWSPND#
F4 TEST
R360 2 1 10K_0402_5% R5C841_CSP208~D
0.33U_0603_10V7K
56.2_0603_1%
56.2_0603_1%
1 1
1
C567
C566
CLK_PCI_CB
R393
R392
@
1
2 2
10_0402_5%
R363
5
6
7
8
IEEE1394_TPAP0 4
GND1
GND2
GND3
GND4
2
IEEE1394_TPAN0 4
3 3
IEEE1394_TPBP0
CLK_PCI_CB_TERM
2 2
IEEE1394_TPBN0 1 1
SUYIN_020204FR004S506ZL
56.2_0603_1%
56.2_0603_1%
1
J139A1
R429
R428
CONN@
@
4.7P_0402_50V8C
A A
2
2
C532
Z3008
270P_0402_50V7K
5.1K_0603_1%
2
1
2
C571
R427
1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/7/6 Deciphered Date 2008/7/6 Title
1
SCHEMATICS,MB A4011
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401521 C
Placement Near Card Bus Controller MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 21, 2008 Sheet 20 of 38
5 4 3 2 1
5 4 3 2 1
+3V
*as close as possible to VCC_3V pin
JPC1
10U_0805_6.3V6M
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
1 1 35 35
CBS_CAD0 2 36 CBS_CCD1#
2 36 CBS_CCD1# <20> CBS_CAD[0..31] <20>
1 1 1 1 1 CBS_CAD1 3 37 CBS_CAD2
3 37
C587
C545
C537
C536
C586
CBS_CAD3 4 38 CBS_CAD4 CBS_CAD31
U32C CBS_CAD5 4 38 CBS_CAD6 CBS_CAD30
5 5 39 39
F5 L2 CBS_CAD7 6 40 CBS_RSVD/D14 CBS_CAD29
2 2 2 2 2 VCC_3V1 NC1 6 40 CBS_RSVD/D14 <20>
G5 C1 CBS_CC/BE0# 7 41 CBS_CAD8 CBS_CAD28
VCC_3V2 NC2 <20> CBS_CC/BE0# 7 41
J19 D1 CBS_CAD9 8 42 CBS_CAD10 CBS_CAD27
+3VS
K19
VCC_3V3
VCC_3V4 R5C841 NC3
NC4
NC5
E1
C2
D2
CBS_CAD11
CBS_CAD12
CBS_CAD14
9
10
11
8
9
10
42
43
44
43
44
45
CBS_CVS1
CBS_CAD13
CBS_CAD15
CBS_CVS1 <20>
CBS_CAD26
CBS_CAD25
CBS_CAD24
D *as close as possible to VCC_PCI pin NC6 CBS_CC/BE1# 11 45 CBS_CAD16 CBS_CAD23 D
W3 VCC_PCI3V1 NC7 E2 <20> CBS_CC/BE1# 12 12 46 46
R11 E4 CBS_CPAR 13 47 CBS_RSVD/A18 CBS_CAD22
VCC_PCI3V2 NC8 <20> CBS_CPAR 13 47 CBS_RSVD/A18 <20>
10U_0805_6.3V6M
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
C556
C555
10U_0805_6.3V6M
0.01U_0402_16V7K
+CBS_VPP 18 52 +CBS_VPP CBS_CAD17
CBS_CCLK_E 18 52 CBS_CTRDY# CBS_CAD16
<20> CBS_CCLK 19 19 53 53 CBS_CTRDY# <20>
2 2 2 2 CBS_CIRDY# CBS_CFRAME# CBS_CAD15
1 1 R6 VCC_RIN1 <20> CBS_CIRDY# 20 20 54 54 CBS_CFRAME# <20>
1
C535
2
VCC_ROUT2 CBS_CAD23 25 59 CBS_CREQ# CBS_CAD9
2 26 26 60 60 CBS_CREQ# <20>
C313 CBS_CAD24 27 61 CBS_CC/BE3# CBS_CAD8
*as close as possible to VCC_RIN pin 27 61 CBS_CC/BE3# <20>
E10 22P_0402_50V8J CBS_CAD25 28 62 CBS_CAUDIO CBS_CAD7
AVCC_PHY1 28 62 CBS_CAUDIO <20>
10U_0805_6.3V6M
0.1U_0402_16V7K~N
0.01U_0402_16V7K
0.01U_0402_16V7K
C568
C583
0.01U_0402_16V7K
1000P_0402_50V7K~N
1000P_0402_50V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
1 1 BLM21A601SPT_0805 76 86 0.01U_0402_16V7K
GND GND 1
C584
C538
22U_1206_6.3V6M
C C
77 GND GND 87 @
J1 GND1 1 1 1 1 1 78 GND GND 88
C588
C554
C580
C581
C553
J5 GND2
@ 2 @2 K5 GND3 NC 89
E9 GND4 NC 90
2 2 2 2 2
R10 GND5
T10 GND6
V10 GND7
W10 FOX_WZ21131-HR-9F_RB
GND8
L15 GND9
M19 CONN@
GND10
R5C841_CSP208~D
+3VS +SD_VCC
U10
+3V U8 1.5A +CBS_VCC 2007-02-12 Protect Circuit for ALPS conn
3 VIN VOUT 1
11 9 +5VS SD_EN 4 5
VCC3IN VCCOUT <20> SD_EN VIN/CE VOUT
1U_0603_10V6K
0.01U_0402_16V7K
14 U34
VCCOUT
1
0.1U_0402_16V7K~N
1
+5VS
10K_0402_1%
1 <20> SDDATA1_MSDATA1_XDDATA1 2 R173
B
C318
C323
C322
1 2 13 0.5A 1 1 1 SD_MS_XDDATA1 RT9701-CB_SOT23-5 150K_0402_5%
VCC5IN A
R177
15 SDDET#_XDDET0# 4
VCC5IN OE 2 2
0.01U_0402_16V7K
C319
10U_0805_6.3V6M
SHORT PADS +CBS_VPP C316 3
2
@ 2 GND
0.1U_0402_16V7K~N
@
J2
2
+5V
1 3 8 @ 2 2 @ SN74CBT1G384_SOT23-5
EN0 VPPOUT
C317
0.1U_0402_16V7K~N
0.01U_0402_16V7K
1 2 4 EN1
1 1 +5VS
C327
C326
D
S
<20> VPPEN0 5 FLG NC 7 GND 3
<20> VPPEN1 16 GND NC 6 1 1
SN74CBT1G384_SOT23-5 @
G
NC 10
JSD1 Pin3 +3VS C315 Q26 C314
<20> VCC3EN#
2
1U_0603_10V6K AOS3401_SOT23 2.2U_0603_10V6K
<20> VCC5EN# 2 2
R5531V002-E2-FA_SSOP16~D Short (L) SD UnWP
1
@ JSD1 Pin1
Open (H) SD WP R169
@ 33K_0402_5% XDDET0# +3VS
1
JSD1 SDCLK_MSCLK_XDRE#
28 R474 1 2 100_0402_5% XDDET0# R163
R475 1 CD 33K_0402_5%
<20> SDDATA3_MSDATA3_XDDATA3 2 150_0402_1% 24 CD/D3 GND 27 R476 1 2 0_0402_5%
1
R477 1 2 150_0402_1% 22 29 R478 1 2 100_0402_5%
<20> SDCMD_MSBS_XDWE# +SD_VCC CMD R/-B SDWP#_XDRB# <20> +XD_VCC
20 30 R479 1 2 22_0402_5% SDCLK_MSCLK_XDRE# <20> R168 D7
2
VSS -RE R480 100_0402_5% @ RB751V_SOD323
19 VDD -CE 31 1 2 XDCE# <20> 33_0402_5%
R481 1 2 39_0402_5% 8 32 R482 1 2 100_0402_5% XDCLE <20> MSDET#_XDDET1# 2 1 XDDET0#
<20> SDCLK_MSCLK_XDRE# CLK CLE
1
6 33 R483 1 2 100_0402_5% XDALE <20>
2
R484 1 VSS ALE
<20> SDDATA0_MSDATA0_XDDATA0 2 150_0402_1% 4 D0 -WE 34 R485 1 2 100_0402_5% SDCMD_MSBS_XDWE# <20> R171 2
SD_MS_XDDATA1 R486 1 2 150_0402_1% 3 35 R487 1 2 100_0402_5% XDWP <20> 2.2K_0402_5% SDDET#_XDDET0# 2 1
SD_MS_XDDATA2 R488 1 D1 -WP
2 150_0402_1% 25 D2 GND 36 @ C305
37 R489 1 2 100_0402_5% SDDATA0_MSDATA0_XDDATA0 <20> 22P_0402_50V8J D18
2
D0 R490 100_0402_5% 1
D1 38 1 2 SDDATA1_MSDATA1_XDDATA1 <20> XDCE# RB751V_SOD323
39 R491 1 2 100_0402_5% SDDATA2_MSDATA2_XDDATA2 <20>
+SD_VCC D2 R492 100_0402_5%
18 VSS D3 40 1 2 SDDATA3_MSDATA3_XDDATA3 <20>
17 41 R493 1 2 100_0402_5% +3VS
VCC D4 XDDATA4 <20>
<20> SDCLK_MSCLK_XDRE# R494 1 2 22_0402_5% 16 42 R495 1 2 100_0402_5% XDDATA5 <20>
R496 100_0402_5% SCLK D5 R497 100_0402_5%
<20> SDDATA3_MSDATA3_XDDATA3 1 2 15 MS-D3 D6 43 1 2 XDDATA6 <20>
1
BS SDCMD_MSBS_XDWE#
9 VSS NC 5
NC 7
NC 23
NC 21
R504 1 2 100K_0402_5% 1
<20> SDDET#_XDDET0#
+3VS
SDDET#_XDDET0#
R505 1
2
CD_SW
COMMDN
Security Classification Compal Secret Data Compal Electronics, Inc.
+3VS 2 100K_0402_5% 46 WP_SW GND 26 Issued Date 2007/7/6 Deciphered Date 2008/7/6 Title
SDWP#_XDRB#
<20> SDWP#_XDRB#
ALPS_SCDE2B0101_46P SCHEMATICS,MB A4011
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401521 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 21, 2008 Sheet 21 of 38
5 4 3 2 1
5 4 3 2 1
+LAN_IO
3.6K_0402_5%
U15 R209 1 2
U16
PCIE_LAN_C_RX_P2 C378 1 RTL_LAN_TX_P2
2 0.1U_0402_16V7K~N 29 45 LAN_EEDO 4 5 1
<10> PCIE_LAN_C_RX_P2 HSOP EEDO DO GND
47 LAN_EEDI 3 6 1 R212 2 C38
PCIE_LAN_C_RX_N2 C379 1 RTL_LAN_TX_N2 30 EDDI/AUX LAN_EECLK DI NC
<10> PCIE_LAN_C_RX_N2 2 0.1U_0402_16V7K~N HSON EESK 48 2 SK NC 7 0_0402_5% 0.1U_0402_16V7K~N
44 LAN_EECS 1 8 @ +LAN_IO
PCIE_LAN_C_TX_P2 EECS CS VCC 2
<10> PCIE_LAN_C_TX_P2 23 HSIP AT93C46-10SU-2.7 SO 8P
<10> PCIE_LAN_C_TX_N2 PCIE_LAN_C_TX_N2 24 HSIN
LED3 54
D
power trace width=20mil 6 MDIP1 6 1.5A
S
+3VS LAN_CTRL18 MDIP1 MDIN1
1 VCTRL18 MDIN1 7 5 4 1 2
1 2 1 1 1 1 1 1
LAN_CTRL15 63 9 MDIP2 C382 1 C608 C381 C377 C34 C37 C22
VCTRL15 MDIP2 MDIN2 1U_0603_10V6K SI3456BDV-T1-E3_TSOP6 @
10
G
MDIN2
1
1 2RSET 64 12 MDIP3
3
RSET MDIP3 2 2 2 2 2 2 2
22U_1206_6.3V6M
22U_1206_6.3V6M
0.1U_0402_10V7K~N
0.1U_0402_10V7K~N
0.1U_0402_10V7K~N
0.1U_0402_10V7K~N
R210 R204 2.49K_0402_1% 13 MDIN3 B+_BIAS
MDIN3
1K_0402_5%
<16,20,26,27> PCIE_WAKE# 19 LANWAKEB
2
15 LAN_DVDD15
2
VDD15 R213
VDD15 21
1 2 ISOLATEB 36 32 470K_0402_5%
R211 15K_0402_5% ISOLATEB VDD15
VDD15 33
38
1
LAN_XTAL1 VDD15 EN_WOL
60 CKXTAL1 VDD15 41
VDD15 43
2
LAN_XTAL2 D
Y2 61 CKXTAL2 VDD15 49
52 Q38 2 R516
VDD15 SSM3K7002FU_SC70-3 G EN_WOL# <26> @
1 2 VDD15 58 1.5M_0402_5%
2 2 1 2 LAN_GVDD 62 S
3
25MHZ_12P_X8A025000FC1H-H C25 0.1U_0402_10V7K~N GVDD +LAN_IO
1
C375 1 2 16
15P_0402_50V8J C15 1U_0402_6.3V6K VDD33
VDD33 37
1 C374 1
VDD33 53 1.5v & 1.8v output power trace width=40mil
15P_0402_50V8J 25 46 L2
L33 EGND VDD33 FBML10160808121LMT_0603
2 1LAN_EGND 31 EGND AVDD33 2 LAN_AVDD33 2 1 +LAN_IO
C C
0_0603_5% AVDD33 59 1 2
C28 0.1U_0402_16V7K~N
17 NC 1 2
18 5 LAN_AVDD18 C16 0.1U_0402_16V7K~N
NC AVDD18 +LAN_IO
35 NC AVDD18 8
34 NC AVDD18 11
39 NC AVDD18 14
40 NC
42 R205 0_0805_5%
NC
3
50 22 LAN_EVDD18 1 2 LAN_AVDD18
NC EVDD18 Q34
51 NC 1 1 1
28 LAN_CTRL18 1 2SB1188_SOT89
EVDD18 C33 C30 C376 L31
65 GND
0.1U_0402_10V7K~N
0.1U_0402_10V7K~N
4.7U_0805_6.3V6K~N LAN_AVDD18_R 1 2 LAN_AVDD18
RTL8111B-GR_QFN64 2 2 2 @ 0_0603_5%
C364
C17
0.1U_0402_10V7K~N C366
C19
C18
C20
LAN_EGND 1 1 1 1 1 1 1
LAN_AVDD18 1 2 V_DAC C365
22U_1206_6.3V6M
0.1U_0402_10V7K~N
0.1U_0402_10V7K~N
0.1U_0402_10V7K~N
0.1U_0402_10V7K~N
R7
2 2 2 2 2 2 2
4.7U_0805_6.3V6K~N
0_0805_5%
@
T1
RP17
C13 1 2 0.01U_0402_16V7K V_DAC 1 24 8 1 C356
MDIN3 TCT1 MCT1 RJ45_TX3- 1000P_1206_2KV7K
2 TD1+ MX1+ 23 7 2
MDIP3 3 22 RJ45_TX3+ 6 3
TD1- MX1-
5 4 2 1
C11 1 2 0.01U_0402_16V7K V_DAC 4 21
MDIN2 TCT2 MCT2 RJ45_TX2- 75_1206_8P4R_5%
5 TD2+ MX2+ 20
MDIP2 6 19 RJ45_TX2+
B TD2- MX2- B
C12 1 2 0.01U_0402_16V7K V_DAC 7 18
MDIN1 TCT3 MCT3 RJ45_RX1- +LAN_IO
8 TD3+ MX3+ 17
MDIP1 9 16 RJ45_RX1+
TD3- MX3-
C10 1 2 0.01U_0402_16V7K V_DAC 10 15
MDIN0 TCT4 MCT4 RJ45_TX0-
11 TD4+ MX4+ 14
MDIP0 12 13 RJ45_TX0+
TD4- MX4-
3
Q35
LAN_CTRL15 1 2SB1188_SOT89
BOTH_GST5009-LF L32
LAN_DVDD15_R 1 2 LAN_DVDD15
FBMA-L11-160808-601LMA10T_0603
C21
C29
C39
C27
0.1U_0402_10V7K~N C380
C31
C35
C26
C32
C36
1 1 1 1 1 1 1 1 1 1 1 1
C683
C371
22U_1206_6.3V6M
0.1U_0402_10V7K~N
0.1U_0402_10V7K~N
0.1U_0402_10V7K~N
0.1U_0402_10V7K~N
0.1U_0402_10V7K~N
0.1U_0402_10V7K~N
0.1U_0402_10V7K~N
0.1U_0402_10V7K~N
0.1U_0402_10V7K~N
0.1U_0402_16V4Z
JLAN1 2 2 2 2 2 2 2 2 2 2 2 2
12 NC 1 2
C357 0.1U_0402_10V7K~N
11 NC
SHLD2 16
RJ45_TX3- 8 1 2
PR4- C355 0.1U_0402_10V7K~N
SHLD1 15
RJ45_TX3+ 7 PR4+
RJ45_RX1- 6 1 2
PR2- C354 0.1U_0402_10V7K~N
RJ45_TX2- 5 PR3-
RJ45_TX2+ 4 1 2
A PR3+ C358 0.1U_0402_10V7K~N A
RJ45_RX1+ 3 PR2+
RJ45_TX0- 2 PR1-
SHLD2 14
RJ45_TX0+ 1 PR1+
SHLD1 13
10 NC Security Classification Compal Secret Data Compal Electronics, Inc.
9 NC Issued Date 2007/7/6 Deciphered Date 2008/7/6 Title
+VDDA
HD Audio Codec
1
+AVDD_AC97 +3VS_DVDD
R538
L47 1 2 0.1U_0402_16V4Z 680P_0402_50V7K 40mil 0.1U_0402_16V4Z 10U_0805_10V4Z 680P_0402_50V7K L48 1 2
+VDDA +3VS
FBMA-L11-160808-800LMT_0603 FBMA-L11-160808-800LMT_0603 10K_0402_5%
1 1 1 1 20mil 1 1 1 1
2
C629 C630 C631 C632 C633 C634 C635 C636 C637 C638 C639
C640 1 2
10U_0805_10V4Z 100P_0402_50V8J 100P_0402_50V8J
1
2 2 2 2 2 2 2 2 1U_0603_10V4Z
R539
D 0.1U_0402_16V4Z 0.1U_0402_16V4Z 680P_0402_50V7K EC Beep D
10K_0402_5%
25
38
R542
9
U4 C641 1 2 1 2
2
<26> BEEP# 1U_0603_10V4Z C647
1 1 560_0402_5%
AVDD1
AVDD2
DVDD_IO
DVDD
C642 C643 MONO_IN_1 1 2 MONO_IN
@ @ 1U_0603_10V4Z
10P_0402_50V8J 10P_0402_50V8J PCI Beep
1
AMP_LEFT 2 2 C
14 NC LINE_OUT_L 35 AMP_LEFT <24> R541 1 2
C644 @ 1 2 100P_0402_50V8J C645 1 2 1 2 2 Q62
AMP_RIGHT <16> SB_SPKR 1U_0603_10V4Z B R540
15 NC LINE_OUT_R 36 AMP_RIGHT <24> 560_0402_5%
E 2SC2411K_SOT23 2.4K_0402_5%
3
C648 2.2U_0603_6.3V6K MIC2_C_L 16 39 AMP_LEFT_HP
<24> MIC2_L MIC2_L HP_OUT_L AMP_LEFT_HP <24>
CardBus Beep
C646 2.2U_0603_6.3V6K MIC2_C_R 17 41 AMP_RIGHT_HP
<24> MIC2_R MIC2_R HP_OUT_R AMP_RIGHT_HP <24>
C155 @ 1 2 100P_0402_50V8J 23 45
LINE1_L NC
1
24 46 R543 D24
LINE1_R DMIC_CLK
18 43 10K_0402_5% RB751V_SOD323
CD_L NC
2
20 CD_R NC 44
R544 1 @ 2 10_0402_5% C649 1 2 @ 10P_0402_50V8J
C650@ 1 2 100P_0402_50V8J 19 CD_GND HD_BITCLK
BIT_CLK 6 HD_BITCLK <16>
MIC1_L C651 2.2U_0603_6.3V6K MIC1_C_L 21
<24> MIC1_L MIC1_L
MIC1_R C652 2.2U_0603_6.3V6K MIC1_C_R SDIN0
SENSE FOR Ext. Mic.
<24> MIC1_R 22 MIC1_R SDATA_IN 8 1 2 HD_SDIN3 <16>
R545 33_0402_5% R546 1 2 20K_0402_1% SENSE_A
<24> MIC_SENSE
C C653@ 1 2 100P_0402_50V8J MONO_IN 12 37 R547 1 2 39.2K_0402_1% C
PCBEEP MONO_OUT <24> HP_SENSE
C654@ 1 2 100P_0402_50V8J 29 SENSE FOR HP
LINE1_VREFO
<16> HD_RST# 11 RESET#
GPIO1 31
<16> HD_SYNC 10 SYNC
MIC1_VREFO_L 28 10mil +MIC1_VREFO_L
<16> HD_SDOUT 5 SDATA_OUT Sense Pin Impedance Codec Signals Funnction
2
MIC1_VREFO_R 32 10mil +MIC1_VREFO_R
GPIO0
SENSE_A
3 GPIO3 MIC2_VREFO 30 10mil +MIC2_VREFO 39.2K PORT-A (PIN 39, 41) HP
R548 1 2 20K_0402_1% SENSE_B
13 SENSE A ACZ_VREF 10mil
SENSE FOR Solo Int. Mic. 34 SENSE B VREF 27
ACZ_JDREF
20K PORT-B (PIN 21, 22) MIC
<24> EAPD 47 EAPD JDREF 40 SENSE A / B
Moat Bridge
1
48 SPDIFO NC 33 1 1 1 10K PORT-C (PIN 23, 24) LINE IN
2
2
R552 0_0805_5% ALC268-GR_LQFP48
1
1
R553
2
0_0805_5% C658
1 39.2K PORT-E (PIN 14, 15) HP
@
DGND AGND
1 2
R554 0_0805_5% 15P_0402_50V8J 20K PORT-F (PIN 16, 17)
2 MIC
SENSE B
B 10K PORT-G (PIN 43, 44) LINE IN B
1 2
MDC_HD_SDOUT 3
GND1 RES0
4 W=20 mil
R203
<16> MDC_HD_SDOUT
MDC_HD_SYNC
5
IAC_SDATA_OUT
GND2
RES1
3.3V 6 MDC_POWER Regulator for CODEC
0.1U_0402_16V7K~N
4.7U_0805_10V4Z
<16> MDC_HD_SYNC 7 IAC_SYNC GND3 8
1 2 HD_SDIN0_MDC 9 10 1 1
<16> HD_SDIN0 IAC_SDATA_IN GND4
33_0402_5% MDC_HD_RST# 11 12 MDC_HD_BITCLK
<16> MDC_HD_RST# IAC_RESET# IAC_BITCLK
C14
C23
@ @ Adjustable Output
+5VS +VDDA
2 2 U23
GND
GND
GND
GND
GND
GND
2
2 6
13
14
15
16
17
18
1
4.7U_0805_10V4Z SD GND
4.7U_0805_10V4Z
@
1
@ C367 10P_0402_50V8J 0.1U_0402_16V4Z
10_0402_5% 10P_0402_50V8J MDC_HD_SYNC 1 2 0.1U_0402_16V4Z R556
@ C368 10P_0402_50V8J
@
2
A A
10_0402_5% 10P_0402_50V8J
680P_0402_50V7K
10U_0805_10V4Z
0.1U_0402_16V4Z
1 1 2
C662 C663 C664 C665 JMIC1
MIC_SENSE 5
<23> MIC_SENSE
+3VALW 1U_0402_6.3V4Z
2 2 1
4 10
9
1 L8 1 MIC1_R_1 1
<23> MIC1_R 2 3 8
R557 @ 1.5K_0402_1% KC FBM-L11-160808-121LMT 0603
11
19
20
10
6 7
1
fo=1/(2*3.14*R*C)=106Hz 1 2 U2 L6 1 2 MIC1_L_1 2
<23> MIC1_L
R=1.5K / C= 1uF R558 @ 1.5K_0402_1% KC FBM-L11-160808-121LMT 0603 1
CVDD
HVDD
PVDD
PVDD
VDD
1 2 1 1
C465 C466 FOX_JA6333L-B3S0-7F~N
<23> AMP_RIGHT 1 2 AMPR CONN@
C666 1U_0603_10V4Z 3 22 SPKR+ 220P_0402_50V7K 220P_0402_50V7K
INR_A ROUT+
3
AMPL SPKR- 2 2
<23> AMP_LEFT 1 2 5 INL_A ROUT- 21
C667 1U_0603_10V4Z
R559 1 2 100K_0402_5% AMP_EN#27 8 SPKL+
/AMP EN LOUT+ SPKL- D32
LOUT- 9
+5VS R560 1 @ 2 100K_0402_5% AMP_SD#24 PSOT05C-LF-T7 SOT-23-3
HP EN HP_R @
17
1
AMP_RHPIN INR_H HP_R HP_L
<23> AMP_RIGHT_HP 1 2 1 2 4 INR_H HP_L 18
C668 4.7U_0805_10V4Z R561 39K_0402_5% INL_H 6
AMP_LHPIN INL_H
<23> AMP_LEFT_HP 1 2 1 2
C669 4.7U_0805_10V4Z R562 39K_0402_5% 26
AMP_SD# /SD CVSS
CVSS 15
1 R563 2 1 2 2 1 AMP_BEEP 28 BEEP
0_0402_5% C670 0.47U_0603_16V4Z R564 0_0402_5% 16
AMP_CP+ VSS
12 CP+
1 2 AMP_CP- 14 2 1
C671 1U_0805_10V7K CP- GND C673
23
AMP_BIAS 25 BIAS
PGND
PGND 7 HEADPHONE OUT JACK
C672 2.2U_0603_6.3V6K 13 1U_0805_10V7K
CGND 2
2 1 Thermal pad 29
C674 0.1U_0402_16V4Z JHP1
APA2056_TSSOP28 HP_SENSE 5
<23> HP_SENSE
4 10
IN_A Gain = 10dB (Internal Speaker) 9
2 HP_R L42 1 HPR 2
2 3 8
IN_H Gain = 0dB (Headphone) KC FBM-L11-160808-121LMT 0603 6 7
HP_L L41 1 2 HPL 2
KC FBM-L11-160808-121LMT 0603 1
2 2
1
C489 C494 FOX_JA6333L-B3S0-7F~N
3
R88 R92 CONN@
@ @ 10P_0402_50V8J 10P_0402_50V8J
EC_MUTE# AMP_SD# 1K_0402_5% 1K_0402_5% 1 1
<26> EC_MUTE# 2 1
R565 @ 0_0402_5% D33
2
PSOT05C-LF-T7 SOT-23-3
@
1
EAPD 2 1
<23> EAPD
R566 0_0402_5%
3
1 MIC2_R_L 2 1
1 MIC2_L <23>
2 2 1 R575 @ 0_0402_5%
2 C675 220P_0402_50V7K D26
LEFT GND 3
1
C676
PSOT24C_SOT23
GND 4
15P_0402_50V8J @
D28
1
1
ACES_88231-02001 @ 2 @ D27
CONN@
MIC_GND R578 PSOT24C_SOT23
3
1 @
R579 0_0402_5% 2
2 1
2
@ 0_0402_5%
PSOT05C-LF-T7 SOT-23-3
D29
+MIC2_VREFO 2 1 1 @ 2
R580 2.2K_0402_5% L51 1 2
RB751V_SOD323 MBK1608121YZF_0603
JMIC3 @
1 MIC2_R_R 2 1
1 MIC2_R <23>
2 2 1 R583 @ 0_0402_5%
2 C677 @ 220P_0402_50V7K
RIGHT GND 3
1
C678
GND 4
15P_0402_50V8J
ACES_88231-02001 2 @
4 CONN@
MIC_GND 4
L52 1 2
MBK1608121YZF_0603
R586 0_0603_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/7/6 Deciphered Date 2008/7/6 Title
@ MIC_GND
GNDA
SCHEMATICS,MB A4011
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401521 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 21, 2008 Sheet 24 of 38
A B C D E
A B C D E
2 2 2 2 1 2 2
C332 C333 C331 C330 C329 C594 C595
0.1U_0402_16V7K~N 0.1U_0402_16V7K~N 0.1U_0402_16V7K~N 0.1U_0402_16V7K~N 10U_0805_10V4Z~N 0.1U_0402_16V7K~N 0.1U_0402_16V7K~N
1 1 1 1 2 1 1
+3VALW
2 1
C598 C597
+3VS 0.1U_0402_16V7K~N 10U_0805_10V4Z~N +3VS
1 2
2 2 2 2 1
1 C600 C599 C596 C593 C328 1
0.1U_0402_16V7K~N 0.1U_0402_16V7K~N 0.1U_0402_16V7K~N 0.1U_0402_16V7K~N 10U_0805_10V4Z~N
1 1 1 1 2
Placement Closed to JMINI2
Placement Closed to JMINI1
+1.5VS +1.5VS
+3VS +3VS
JMINI1 JMINI2
1 1 2 2 1 1 2 2
3 4 <27> WLAN_ACTIVE WLAN_ACTIVE 3 4
3 4 BT_ACTIVE 3 4
5 5 6 6 <27> BT_ACTIVE 5 5 6 6
7 8 R447 1 2 0_0402_5% LPC_FRAME# LPC_FRAME# <15,26> <13> CLKREQA# 1 2 7 8 0_0402_5%1 2 R442 LPC_FRAME#
7 8 R446 0_0402_5% LPC_AD3 R467 0_0402_5% 9 7 8 0_0402_5%1 R441 LPC_AD3
9 9 10 10 1 2 9 10 10 2
11 12 R445 1 2 0_0402_5% LPC_AD2 11 12 0_0402_5%1 2 R440 LPC_AD2
11 12 <13> CLK_PCIE_WCARD# 11 12
13 14 R444 1 2 0_0402_5% LPC_AD1 13 14 0_0402_5%1 2 R439 LPC_AD1
13 14 <13> CLK_PCIE_WCARD 13 14
15 16 R443 1 2 0_0402_5% LPC_AD0 15 16 0_0402_5%1 2 R438 LPC_AD0
PCI_RST# 15 16 15 16
<15,20> PCI_RST# 1 R184 2 0_0402_5% 17 17 18 18 LPC_AD[0..3] <15,26>
PCI_RST# 1 R460 2 0_0402_5% 17 17 18 18
CLK_PCI_SIO_DB 1 R183 2 0_0402_5% 19 20 CLK_PCI_SIO_DB 1 R459 2 0_0402_5% 19 20 W_DISABLE#
<15> CLK_PCI_SIO_DB 19 20 19 20
21 22 21 22 NB_RST#
21 22 R458 0_0402_5% PCIE_C_RXN2 21 22 NB_RST# <11,15,19,22,26,27>
23 23 24 24 <10> PCIE_WLAN_C_RX_N1 1 2 23 23 24 24
25 26 <10> PCIE_WLAN_C_RX_P1 R457 1 2 0_0402_5% PCIE_C_RXP2 25 26
25 26 25 26
27 27 28 28 27 27 28 28
29 29 30 30 29 29 30 30
31 31 32 32 <10> PCIE_WLAN_C_TX_N1 31 31 32 32
2 2
33 33 34 34 <10> PCIE_WLAN_C_TX_P1 33 33 34 34
35 35 36 36 USB20P7- <16> 35 35 36 36 USB20P8- <16>
37 37 38 38 USB20P7+ <16> 37 37 38 38 USB20P8+ <16>
39 39 40 40 39 39 40 40
41 41 42 42 41 41 42 42
43 44 43 44 LED_WLAN#
43 44 43 44
45 45 46 46 45 45 46 46
47 47 48 48 47 47 48 48
49 49 50 50 49 49 50 50
51 51 52 52 51 51 52 52
53 54 +3VS 53 54
GND1 GND2 GND1 GND2
FOX_AS0B226-S52N-7F~N FOX_AS0B226-S52N-7F~N
1
CONN@ CONN@
R593
10K_0402_5%
2
W_DISABLE#
1
D
Q65 2 WLAN_ON# R588 D30
WLAN_ON# <26>
SSM3K7002FU_SC70-3 G 3.3K_0402_5% Amber
S +5VALW 1 2 4 3 BATT_LOW_LED# <26>
3
A
R589 Blue
1 2 2 1
CAMERA +5VALW
3.3K_0402_5%
B
BATT_CHG_LED# <26>
3 R531 1 @ 3
+5VALW 2 0_0603_5% HT-297UD/CB _BLUE/AMB_0603
3 @R455
@ R455
4 4
5 100K_0402_5% HT-297UD/CB _BLUE/AMB_0603
5
1
L46 @ 6
2
GND1
2
1 2 7 R594
1 2 R535 GND2 100K_0402_5%
ACES_88266-05001 +5VALW
4 3 0_0603_5% CONN@
2
4 3 CAM@ KILL_SW#
KILL_SW# <26> D9
1
WCM-2012-670T_4P @
1 2 1 R469 2
2
1
D @
For EMI : Change D23 from SC300000P00 to SCA00000A00 1.5M_0402_5%
2 Q57
+5VS <26,29> PWR_GREEN_LED#
G SSM3K7002FU_SC70-3
1
1
S @
3
D23 R515
4 USB20_R_P7 LED_WLAN# 10K_0402_5% 4
2 1 2
1 R180 100K_0402_5% @
USB20_R_N7 3
2
PJDLC05_SOT23~D
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/7/6 Deciphered Date 2008/7/6 Title
SCHEMATICS,MB A4011
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401521 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 21, 2008 Sheet 25 of 38
A B C D E
5 4 3 2 1
L43
1 2 R358
+3VALW +EC_AVCC +3VALW
MBK1608800YZF 0603 2 1 R127 0_0402_5%
R141 +EC_AVCC
C228 VLDT_EN 1 2 1 2 SB_PWRGD <6,16>
0.1U_0402_16V7K~N C511 1000P_0402_50V7K~N 1 2+3VALW_ECVCC 0.1U_0402_16V7K~N 0.1U_0402_16V7K~N 1000P_0402_50V7K~N 20K_0402_1% 1 1
1 1 1 1 1 @
1 ECAGND 2 0_0805_5% C275 @ C542
1 2
L21 MBK1608800YZF 0603 C528 C527 C529 C516 C510 1U_0603_10V6K @ 0.47U_0603_16V7K
2 2
2 2 2 2 2
0.1U_0402_16V7K~N 1000P_0402_50V7K~N
111
125
R512
22
33
96
67
9
U5 NB_PWRGD_EC 1 2
D NB_PWRGD <11> D
RS690M & SB600 PowerGD
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
<15,25> LPC_AD[0..3]
0_0402_5%
<16> EC_GA20
EC_GA20 1 21 INVT_PWM <14>
+3VALW FOR Board ID
KB_RST# GA20/GPIO00 INVT_PWM/PWM1/GPIO0F
<16> KB_RST# 2 KBRST#/GPIO01 BEEP#/PWM2/GPIO10 23 BEEP# <23>
CLK_PCI_EC 3 26 PWR_USB_BTN_P#
<15,20> SIRQ SERIRQ# FANPWM1/GPIO12 PWR_USB_BTN_P# <29>
<15,25> LPC_FRAME# 4 LFRAME# ACOFF/FANPWM2/GPIO13 27 ACOFF <31,32>
1
1
LPC_AD3 5
R113 LPC_AD2 LAD3 C508 1
7 LAD2 PWM Output 20.01U_0402_16V7K ECAGND R100
LPC_AD1
@ 10_0402_5% LPC_AD0
8 LAD1 BATT_TEMP/AD0/GPIO38 63 BATT_TEMP <37> Ra 100K_0402_5%
10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64 BATT_OVP <32>
65 ADP_I <32>
2
2
ADP_I/AD2/GPIO3A AD_BID0 AD_BID0
1 <15> CLK_PCI_EC 12 PCICLK AD Input AD3/GPIO3B 66
C247 R334 NB_RST# 13 75 LIGHT_SENSOR 1
<11,15,19,22,25,27> NB_RST# PCIRST#/GPIO05 AD4/GPIO42
2
1 2 EC_RST# 37 76
+3VALW ECRST# SELIO2#/AD5/GPIO43
@ 15P_0402_50V8D EC_SCI# 20 TP59 R337 C512
2 <16> EC_SCI# SCI#/GPIO0E 0.1U_0402_16V7K~N
47K_0402_5% 56K_0402_5%~N
<15,20> PM_CLKRUN# 38 CLKRUN#/GPIO1D
68
Rb 2
2 DAC_BRIG/DA0/GPIO3C DAC_BRIG <14>
C509 70 EN_DFAN1 <4>
1
KSI[0..7] EN_DFAN1/DA1/GPIO3D
<27> KSI[0..7] DA Output IREF/DA2/GPIO3E 71 IREF <32>
0.1U_0402_16V7K~N KSI0 55 72
1 KSI0/GPIO30 DA3/GPIO3F USB_ON# <28>
KSI1 56
KSI2 KSI1/GPIO31
57 KSI2/GPIO32
KSI3 58 83 EC_MUTE#
KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE# <24>
KSI4 59 84
KSI4/GPIO34 PSDAT1/GPIO4B USB_EN +5VALW
KSI5 60 85
KSI5/GPIO35 PSCLK2/GPIO4C ECO_GREEN_LED#
KSI6 61 PS2 Interface 86
KSO[0..15] KSI6/GPIO36 PSDAT2/GPIO4D PWR_USB_LED# <29> 20mil
KSI7 62 87 TP_CLK 1 R520 2 0_0603_5%
<27> KSO[0..15] KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK <27> +3VALW
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <27>
1
+3VALW KSO1 40 0.1U_0402_16V7K~N
KSO2 KSO1/GPIO21 2007-02-12 MUST PULL DOWN!!!
41 KSO2/GPIO22 1 R521 2 C488 1 2 R323
C KSO3 SPI_PD R473 1 C
42 KSO3/GPIO23 SDICS#/GPXOA00 97 2 4.7K_0402_5% 0_0603_5%
KSO4 43 98 @ 100K_0402_5%
KSO4/GPIO24 SDICLK/GPXOA01 EN_WOL# <22>
R108 1 2EC_PME# 1 R112 2 10K_0402_5% KSO5
<16,20,22,27> PCIE_WAKE# 44 KSO5/GPIO25 Int. K/B 99 SBPWR_EN <18>
2
0_0402_5% KSO6 SDIDO/GPXOA02 WOW_VIDEO_BTN# U26
KSO7
45
46
KSO6/GPIO26 Matrix
SPI Device Interface
SDIDI/GPXID0 109 WOW_VIDEO_BTN# <29> MUTE 8 1
KSO8 KSO7/GPIO27 VCC A0
47 KSO8/GPIO28 7 WP A1 2
LID_SW# 1 R344 2 10K_0402_5% KSO9 48 119 FRD#SPI_SO 2 R351 1 15_0402_5% EC_SI_SPI_SO EC_SMB_CK1 6 3
KSO10 KSO9/GPIO29 SPIDI/RD# FWR#SPI_SI R350 15_0402_5% EC_SO_SPI_SI EC_SMB_DA1 SCL A2
49 KSO10/GPIO2A SPIDO/WR# 120 2 1 5 SDA GND 4
KSO11 50 SPI Flash ROM 126 SPI_CLK 2 R130 1 15_0402_5% SPI_CLK_R
EC_MUTE# KSO11/GPIO2B SPICLK/GPIO58
1 R111 2 10K_0402_5% KSO12 51 KSO12/GPIO2C SPICS# 128 FSEL#SPICS# 2 R120 1 15_0402_5% SPI_CS# AT24C16AN-10SU-2-7 SO 8P
KSO13 52
E-Mail_BTN KSO13/GPIO2D
1 R128 2 10K_0402_5% KSO14 53 KSO14/GPIO2E
KSO15 54 KSO15/GPIO2F CIR_RX/GPIO40 73 WLAN_ON# <25> Change U26 from SA024160140 to SA00001N800
1
SW_CONFIG1 81 74 MSEN# MSEN# <14>
+3VALW <27> SW_CONFIG1 KSO16/GPIO48 CIR_RLC_TX/GPIO41
SW_CONFIG2 82 89 R324
<27> SW_CONFIG2 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG <32>
RP19 90 BATT_CHG_LED#
BATT_CHGI_LED#/GPIO52 BATT_CHG_LED# <25>
Internet_BTN 1 8 MSEN# 1 R338 2 10K_0402_5% 91 100K_0402_5%
CAPS_LED#/GPIO53 CAPSLED# <29>
PWR_USB_BTN_P# 2 7 EC_SMB_CK1 77 GPIO 92
<37> EC_SMB_CK1 BATT_LOW_LED# <25>
2
WOW_AUDIO_BTN# EC_SMB_DA1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54
3 6 <37> EC_SMB_DA1 78 SDA1/GPIO45 SUSP_LED#/GPIO55 93 PWR_GREEN_LED# <25,29>
WOW_VIDEO_BTN# 4 5 EC_SMB_CK2 79 SM Bus 95
<6> EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON <27,30,34>
<6> EC_SMB_DA2 EC_SMB_DA2 80 121
SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <36>
10K_0804_8P4R_5% 127 ACIN
AC_IN/GPIO59 ACIN <31>
SPI Flash (8Mb*1)
6 100 Reserve for EMI, close to SPI ROM
<16> SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# <16>
<16> SLP_S5# 14 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 101 EC_LID_OUT# <16>
NB_RST# 1 2 R348 EC_SMI# 15 102
<16> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <29>
@ 100K_0402_5% LID_SW# 16 103 SPI_CLK_R
<29> LID_SW# LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SWI# <16>
17 104 VLDT_EN
<27,30> SUSP# SUSP#/GPIO0B ICH_PWROK/GPXO06 VLDT_EN <30>
<16> PWRBTN_OUT# 18 PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08 105 BKOFF# <14>
1
EC_PME# 19 GPIO 106 DIMMER_STATUS
EC_PME#/GPIO0D WL_OFF#/GPXO09 DIMMER_STATUS <29>
25 107 NB_PWRGD_EC R98
B <25> KILL_SW# EC_THERM#/GPIO11 GPXO10 B
FAN_SPEED1 28 108 BT_ON# +3VALW @ 33_0402_5%
+3VALW <4> FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 BT_ON# <27>
1 R519 2 0_0402_5% 29 C221
<33> PWR_SKIP# FANFB2/GPIO15
RP18 EC_TX_P80DATA 30 1 2
2
SW_CONFIG1 EC_RX_P80CLK EC_TX/GPIO16
1 8 31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 SW_RSV2 <27> 2
2
SW_CONFIG2 2 7 32 112 ENABLT ENABLT <11,14> 0.1U_0402_10V7K~N
<29> ON_OFF ON_OFF/GPIO18 ENBKL/GPXID2 20mils
SW_RSV1 3 6 34 114 WOW_AUDIO_BTN# R99 @ C224
<29> SCRLED# PWR_LED#/GPIO19 GPXID3 WOW_AUDIO_BTN# <29>
SW_RSV2 4 5 36 GPI 115 EC_THERM# U27 22P_0402_50V8J
<29> NUMLED# NUMLED#/GPIO1A GPXID4 EC_THERM# <17> 1
116 SW_RSV1 <27> 10K_0402_5% 8 4
10K_0804_8P4R_5% GPXID5 E-Mail_BTN VCC VSS
117 E-Mail_BTN <29> Q-CHARGING
1
GPXID6 Internet_BTN
GPXID7 118 Internet_BTN <29> 3 W
CRY2 122
+5VS CRY1 XCLK1
123 XCLK0 V18R 124 7 HOLD
AGND
1 SPI_CS# 1
GND
GND
GND
GND
GND
TP_DATA S
1 R119 2 10K_0402_5% ACIN
TP_CLK 1 R118 2 10K_0402_5% @ C619 C620 SPI_CLK_R 6
CRY1 KB926QFA1_LQFP128_14X14 C
0.1U_0402_10V7K~N
11
24
35
94
113
69
C265 C264
4
EC_SMB_CK1 R342 2 1
1 4.7K_0402_5% EC_TX_P80DATA 2 2
EC_RX_P80CLK 3 3
4 4
A A
NC
NC
+3VS ACES_85205-0400
CONN@
3
2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/7/6 Deciphered Date 2008/7/6 Title
C246
@1000P_0402_50V7K~N SCHEMATICS,MB A4011
1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401521 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 21, 2008 Sheet 26 of 38
5 4 3 2 1
BT
KSO8 C209 @ 100P_0402_25V8K KSI7 C194 @ 100P_0402_25V8K
1
KSI2 C199 @ 100P_0402_25V8K KSO0 C217 @ 100P_0402_25V8K
1 R528
KSI1 C200 @ 100P_0402_25V8K KSO1 C216 @ 100P_0402_25V8K C623 C624 BT@
BT@ BT@ 10K_0402_5% +BT_VCC
KSO10 C207 @ 100P_0402_25V8K KSO2 C215 @ 100P_0402_25V8K 0.1U_0402_16V4Z 1U_0603_10V4Z
2
3
2
S
G JBT1
KSO11 C206 @ 100P_0402_25V8K KSI4 C197 @ 100P_0402_25V8K 1 BT@ 2 2 BT_LED# 1
<26> BT_ON# <25> BT_LED# 1
R530 100K_0402_5% Q61 2
KSI0 C201 @ 100P_0402_25V8K KSO3 C214 @ 100P_0402_25V8K SI2301BDS_SOT23 R536 1 BT@ 2
<16> USB20P4+ 2 0_0402_5% USB20P4+_R 3 3
1
BT@ D R537 1 BT@
D <16> USB20P4- 2 0_0402_5% USB20P4-_R 4 4
KSO12 C205 @ 100P_0402_25V8K KSO4 C213 @ 100P_0402_25V8K W=40mils Q63 2 BTON_LED 5
1
2N7002_SOT23 G WLAN_ACTIVE 5
+BT_VCC <25> WLAN_ACTIVE 6 6
KSO13 C204 @ 100P_0402_25V8K KSO5 C212 @ 100P_0402_25V8K BT@ S BT_ACTIVE 7
<25> BT_ACTIVE
3
7
1
1 8 8
KSO14 C203 @ 100P_0402_25V8K KSO6 C211 @ 100P_0402_25V8K C625 C626 R529 9
BT@ BT@ BT@ GND1
10 GND2
KSO15 C202 @ 100P_0402_25V8K KSO7 C210 @ 100P_0402_25V8K 4.7U_0805_10V4Z 0.1U_0402_16V4Z 10K_0402_5%
2 MOLEX_53780-0870
2
CONN@
ON
KSO1 15 1 1 12
15 1 CLR_CMOS
KSI0 14 2
KSO2 14 TP_DATA 2
13 13 <26> TP_DATA 3 3 <26> SW_CONFIG1 2 11
KSO4 12 TP_CLK 4
12 <26> TP_CLK 4
KSO7 11 5 3 10
11 5 <26> SW_CONFIG2
KSO8 10 C335 1 1 C339 C334 1 6
KSO6 10 @ @ 6
9 9 7 GND <26> SW_RSV1 4 9
KSO3 8 8
8 GND
0.01U_0402_16V7K
KSO12 7 5 8
7 2 2 2 <26> SW_RSV2
100P_0402_25V8K
100P_0402_25V8K
KSO13 6 ACES_85201-06051
KSO14 6 CONN@
5 5 6 7
KSO11 4 TP58
KSO10 4
3 3
KSO15 2 FHDS-06-T-V-T/R_12P
2 @
1 1
ACES_85201-2505
CONN@
+1.5V_CARD +3V_CARD
1A 1.5A
C267
C278
C266
C268
C282
C281
1 1 1 1 1 1
+3V_CARD_AUX
+3VALW
10U_0805_6.3V6M
+3VS +1.5VS
+3V_CARD +1.5V_CARD 2 2 2 2 2 2
10U_0805_6.3V6M
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
C297
C283
C279
JP2 1 1 1
1 GND U7
<16> USB20P6- R114 2 1 0_0402_5% USB20P6-_R 2 USB_D- 2 2 2
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
C280
C296
NC_PWR_EN# R510 1 2 0_0402_5% NC_CPPE# 17
<16> NC_PWR_EN# CPPE#
<13> CLK_PCIE_CARD# 18 +3VALW @ 1 R134 2 100K_0402_5% NC_PWR_EN# 10 7 1 1
REFCLK- CPPE# GND
<13> CLK_PCIE_CARD 19 REFCLK+
20 GND
@ 1 R135 2 100K_0402_5% NC_CPUSB# 9 CPUSB#
<11> PCIE_CARD_C_RX_N1 PCIE_CARD_C_RX_N1 21 PERn0 2 2
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
<11> PCIE_CARD_C_RX_P1 PCIE_CARD_C_RX_P1 22 18
PERp0 RCLKEN
23 GND
<11> PCIE_CARD_C_TX_N1 PCIE_CARD_C_TX_N1 24 P2231NF_QFN20
PCIE_CARD_C_TX_P1 PETn0
<11> PCIE_CARD_C_TX_P1 25 PETp0
26 GND
27 GND
28 GND
29 GND GND 31
30 GND GND 32
FOX_1CX41202-KH_26P
CONN@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/7/6 Deciphered Date 2008/7/6 Title
SCHEMATICS,MB A4011
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401521 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 21, 2008 Sheet 27 of 38
A B C D E
+USB_AS W=40mils
+5VALW
+USB_AS
U12
1 GND OUT 8
2 IN OUT 7
1 3 IN OUT 6
1
C350 4 5
1 EN# OC# OVCUR#0 <16> 1
R4
0.1U_0402_16V7K~N G548B2P8U_MSOP8 470_0805_5% JUSB1
2
8 GND4
7
1 2
GND3
D 6 GND2
USB_ON# 5
Q1 SUSP L1 GND1
2 SUSP <30,35>
SSM3K7002FU_SC70-3 G <16> USB20P0- USB20P0- 3 4 4
3 4 VCC
1
S CON-USBP0- 3
3
R592 CON-USBP0+ D-
2 D+
100K_0402_5% <16> USB20P0+ USB20P0+ 2 1 1
@ 2 1 GND
WCM-2012-670T_4P ALLTO_C10797-10403-L
2
CONN@
6
D2
CH1 CH4
Vp
CH2 CH3
NUP4301MR6T1_TSOP6
Vn
1
3
Change JUSB1 from DC233105800 to DC233002A00
2 2
+USB_BS
+5VALW W=40mils
U18 +USB_BS +USB_CS
1 GND OUT 8
2 IN OUT 7
1
3 6 1 2 +USB_BS
1 IN OUT
C384 4 5 R217 R526 @ 0_1206_5%
EN# OC# OVCUR#1 <16>
470_0805_5%
0.1U_0402_16V7K~N G548B2P8U_MSOP8 JUSB3
3 2 3
1
2
1
2 2
3 3
1
D
4 4
<26> USB_ON# 1 2 Q39 2 SUSP USB20P1- 5 5
R216 SSM3K7002FU_SC70-3 G <16> USB20P1- USB20P1+ 6
0_0402_5% <16> USB20P1+ 6
S 7
3
+USB_AS 7
8 8
1
USB20P2- 9
R215 <16> USB20P2- USB20P2+ 9
10 10
100K_0402_5% <16> USB20P2+ 11
@ 11
12 12
13
2
470P_0402_50V7K G1
1 14 G2
1 1
+ C9 C8 ACES_85201-1205_12P
C349 CONN@
150U_D2_6.3VM
2 2 2
+USB_CS
+5VALW W=40mils
U33 470P_0402_50V7K
1 GND OUT 8
2 IN OUT 7
1 3 IN OUT 6
1
C603 4 5
EN# OC# OVCUR#3 <16>
@ R463
0.1U_0402_16V7K~N G548B2P8U_MSOP8 470_0805_5%
2 @ @
1 2
4 D 4
USB_ON# 1 @ 2 Q56 2 SUSP
R468 SSM3K7002FU_SC70-3 G
0_0402_5% @ S
3
1
R466
100K_0402_5%
@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/7/6 Deciphered Date 2008/7/6 Title
2
SCHEMATICS,MB A4011
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401521 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 21, 2008 Sheet 28 of 38
A B C D E
A B C D E
H1 H2 H3 H4 H5 H6 H7
@ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA LID Switch
CF8 CF10 CF11 CF3
SMD40M80 SMD40M80 SMD40M80 SMD40M80
1
1
@ @ @ @
1
+3VALW 1 2 +VCC_LID R597 1 2 100K_0402_5%
H8 H9 H10 H11 H12 H13 H14 H_S354D118 CF1 CF2 CF9 CF7 CF13 R596 0_0402_5%
@ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA @ HOLEA SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80
2
@ @ @ @ @
1 1
VDD
1
1
1
C681 3
OUTPUT LID_SW# <26>
0.1U_0402_16V4Z 2
GND
FD3 FD2 FD1 FD4 FD5 FD6 CF15 2 C682
FIDUCAL FIDUCAL FIDUCAL FIDUCAL FIDUCAL FIDUCAL SMD40M80
H16 H17 @ @ @ @ @ @ @ U37 10P_0402_50V8J
1
@ HOLEA @ HOLEA A3212ELHLT-T_SOT23W-3 1
H_C216D144
1
1
+3VALW
2
@ HOLEA
H_C236D157 R142
100K_0402_5%
1
1
D6 +3VALW
2 ON_OFF <26>
PWR_ON-OFF_BTN# 1
2
3 51ON#
51ON# <31>
H19 H20 H21 H22 R527
@ HOLEA @ HOLEA @ HOLEA @ HOLEA
H_C276D165 (CPU) DAN202U_SC70 100K_0402_5%
1
1
2 D22
1
2 PWR_USB_BTN_P# 2
2 PWR_USB_BTN_P# <26>
@ C276 @ D5 PWR_USB_BTN_D# 1
1000P_0402_50V7K~N RLZ20A_LL34 3 51ON#
1 51ON# <31>
2
DAN202U_SC70
1
Q20 D
H23 EC_ON 2
<26> EC_ON
@ HOLEA G
1
H_S362D118 S@
3
R131 2N7002_SOT23
@
1
10K_0402_5%
Modify 51ON Circuit , Follow IFXXX. +5VS +5VALW
2 JLED1
1 1
2 2
+5VS +5VS_DIMMER PWR_ON-OFF_BTN# 3
H24 Q22 E-Mail_BTN 3
4 4
@ HOLEA AO3401_SOT23 <26> E-Mail_BTN Internet_BTN 5
<26> Internet_BTN PWR_USB_BTN_D# 5
H_C114D114N 6 6
3 1 WOW_AUDIO_BTN# 7
<26> WOW_AUDIO_BTN# WOW_VIDEO_BTN# 7
D
S 2 2 8
1
@ <26> WOW_VIDEO_BTN# 8
9 9
G @ C617 C618 PWR_GREEN_LED# 10
<25,26> PWR_GREEN_LED# 10
R149 @ 1000P_0402_50V7K~N 0.1U_0402_16V7K~N PWR_USB_LED# 11
<26> PWR_USB_LED#
2
1 1 @ SCRLED# 11
1 2 <26> SCRLED# 12 12
NUMLED# 13
<26> NUMLED# 13
2 CAPSLED# 14
1M_0402_5% <26> CAPSLED# 14
H25 H26 C622 IDE_ACT_LED# 15 17
15 G17
1
H27 H28
1
@ HOLEA @ HOLEA D @
+5VS DIMMER_STATUS 2
<26> DIMMER_STATUS
G Q21
S
1
3
2
2 SSM3K7002FU_SC70-3
C383 R148
0.1U_0402_16V7K~N @ 100K_0402_5%
@ PWR_USB_BTN_D# @ C302 100P_0402_25V8K E-Mail_BTN @ C292 100P_0402_25V8K
1
1
<17> SATA_LED# B
4 IDE_ACT_LED# PWR_GREEN_LED# @ C309 100P_0402_25V8K NUMLED# @ C43 100P_0402_25V8K
ODD_ACT_LED# Y
<19> ODD_ACT_LED# 1 A
G
R587 1 2 0_0402_5%
+5VS
4 4
2
CARD_LED_5V
R214
10K_0402_5%
@
1
D
1
CARD_LED# 2 Q60
G SSM3K7002FU_SC70-3
Security Classification Compal Secret Data Compal Electronics, Inc.
1
D
S @
3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401521 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 21, 2008 Sheet 29 of 38
A B C D E
A B C D E
+1.2VALW TO +1.2V_NBCORE
+5VALW TO +5V
+5VALW TO +5VS
+5V +1.2VALW +1.2V_NBCORE
+5VALW +5VS
U11 U36
1 1 8 D S 1 8 D S 1
+5VALW @ 7 2 7 2
@ Q33 C337 C338 D S D S
6 D S 3 1 1 6 D S 3
4.7U_0805_10V4Z~N 1U_0603_10V6K 5 4 5 4 1 1
D G D G
D
2 2 C340 C341
6
S
@
5 4 1 AO4468 1N SO8 4.7U_0805_10V4Z~N 1U_0603_10V6K AO4468 1N SO8 C604 C605
2 2 4.7U_0805_10V4Z~N 1U_0603_10V6K
NB_GATE
2 1
1 C336 2 2 1
1
SI3456BDV-T1-E3_TSOP6 10U_0805_10V4Z~N C606
G
2 10U_0805_10V4Z~N
3
1
2 D 1.2VS_GATE 1 0.22U_0603_10V7K
@ 2
Q32 SUSP 2
2
SSM3K7002FU_SC70-3 G 0_0402_5%
S
3
+3VALW TO +3V +3VALW TO +3VS
+1.2VALW TO +1.2V_HT
+3V +3VS +3VS
J6
1 2
+1.2VALW +1.2V_HT
1 1 1 1
+3VALW SHORT PADS +3VALW
Q51 C591 C590 C321 C324 U22
@ 4.7U_0805_10V4Z~N 1U_0603_10V6K U9 4.7U_0805_10V4Z~N 1U_0603_10V6K 8 1
D S
D
2 2 2 2
6 8 1 7 2
S
D S D S
5 4 7 D S 2 6 D S 3
2 6 D S 3 5 D G 4 1 1
1 5 4 3VS_GATE 1 R174 2 RUN_ON
SI3456BDV-T1-E3_TSOP6 D G 0_0402_5% AO4468 1N SO8 C138 C144
1.2VS_GATE
G
3V_GATE 2 2
1 R448 2 SUSON 1 R187 2 B+_BIAS
2 0_0402_5% 100K_0603_5% C454 2
1 1 1
2
@ 10U_0805_10V4Z~N R60
C592 C325 C320 2 R61 100K_0603_5% R53
1
10U_0805_10V4Z~N C601 10U_0805_10V4Z~N 0.22U_0603_10V7K 1 2 RUN_ON_1.2 1 2 10K_0402_5%
B+_BIAS
1
2 @ 0.22U_0603_10V7K D 2 2
@
Q29 2 SYSON# 1 10K_0402_5%
1
1
2 SSM3K7002FU_SC70-3 G D
@ S C455 2 VLDT_EN#
3
0.1U_0603_25V7K Q15 G
2 S SSM3K7002FU_SC70-3
3
+1.8V TO +1.8VS
Change C455 from 0.22uF to 0.1uF (SE042104K80) for mount
1
+1.8V D
+5VALW +5VALW +1.8VS VLDT_EN 2 Q14
<26> VLDT_EN
U24 G SSM3K7002FU_SC70-3
8 1 S
3
D S
2
1
7 D S 2
R189 R186 6 3 R52
10K_0402_5% 10K_0402_5% D S 10K_0402_5%
5 D G 4 1 1
AO4468 1N SO8 C475 C174
1.8VS_GATE
1
2
SUSP SYSON# 1 4.7U_0805_6.3V6K~N 1U_0603_10V6K
<28,35> SUSP <6,35> SYSON# 2 2
C480
10U_0805_10V4Z~N
Q30 Q31 2
1
S S 1 +5VS
3
1
R32 R36 R33 R72 R175 R179 R176 R37 R181
470_0805_5% 470_0805_5% 470_0805_5% 470_0805_5% 470_0805_5% 470_0805_5% 470_0805_5% 470_0805_5% 470_0805_5%
DISCHG_0.9V 2
DISCHG_1.2VHT 2
DISCHG_1.8V 2
DISCHG_1.8VS 2
2
DISCHG_5VS
DISCHG_1.5VS
DISCHG_3V
DISCHG_5V
DISCHG_3VS
1
1
D D D D D D D D D
SYSON# 2 Q10 SUSP 2 Q12 SYSON# 2 Q11 SUSP 2 Q16 SYSON# 2 Q24 SUSP 2 Q27 SYSON# 2 Q25 SUSP 2 Q13 SUSP 2 Q28
4 G G G G G G G G G 4
S S S S S S S S S
3
3
SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/7/6 Deciphered Date 2008/7/6 Title
SCHEMATICS,MB A4011
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401521 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, November 21, 2008 Sheet 30 of 38
A B C D E
5 4 3 2 1
Vin Detector
ADPIN VIN
Max. typ. Min.
PL2
HCB4532KF-800T90_1812
H-->L 18.234 17.841 17.449
L-->H 17.597 17.210 16.813
1 2
PCN1
D D
1 1 PC37 PR69
@
2200P_0402_50V7K~N @ 56K_0402_5%~N
1000P_0402_50V7K~N
1000P_0402_50V7K~N
1000P_0402_50V7K~N
100P_0402_50V8J~N
100P_0402_50V8J~N
100P_0402_50V8J~N
2 1 2 1 2
1
1
PC135
PC15
PC31
2
PC134
PC14
PC30
PR70
2
2
3 3 1M_0402_1%~N
1 2
VIN
4 VS VIN
4
0.01U_0402_25V7K~N
1
1
SINGA_2WA-8291T041 PR67 PR63
1
PC35
PR71 10K_0402_5%~N 1K_0402_5%~N
82.5K_0402_1%~N 1 2
PR59 ACIN <26>
2
1K_1206_5%~N PR72
2
8
1 2 22K_0402_1%~N PU4A
PQ3 N41 1 2 N40 3
P
TP0610K-T1-E3_SOT23-3 + PACIN
0 1 PACIN <32>
19.6K_0402_1%~N
0.1U_0402_16V7K~N
PR55 N35 2 -
1
VIN PD1 1K_1206_5%~N
B+
1
PC40
PR75
2 1 1 2 3 1 LM393DR_SO8~N PR64
4
PC34 10K_0402_5%~N
RLS4148_LLDS2 PR51 1000P_0402_50V7K~N
2
1K_1206_5%~N PD17
2
VIN 1 2 32.3
470K_0402_5%~N
470K_0402_5%~N
1
1
PR24
PR43 PR65 MMPZ5229BPT_SC76
2
PR18
1K_1206_5%~N 10K_0402_5%~N
2
C C
1 2 2 1
RTCVREF
PJP6 PD11
3.3V
2
PD12 @ RLS4148_LLDS2
1 1
BATT+ 2 1 1 1 2 2
CH751H-40PT_SOD323-2 JUMP_43X118
VS
1
PQ45 PR143
TP0610K-T1-E3_SOT23-3 33_1206_5%~N PR17
2
1
470K_0402_5%
CHGRTCP 3 1 PQ7 PR73
DTC115EUA_SC70-3 VL 2.2M_0402_5%~N B+
1 2
2 1
1
@ <26,32> ACOFF 2
1
PR152 PQ6
PC113
0.1U_0603_25V7K~N
2
1
@ PR153 2
2
3
22K_0402_5% 0.22U_1206_25V7K @ VS PR78
1 2 499K_0402_1%~N
<29> 51ON#
1
PR68
2
100K_0402_1%~N
8
<33,37> MAINPWON PD2 PU4B
2 5
P
+
1 7 0
0.01U_0402_25V7K~N
<32> ACON 3 - 6
1
1
RTCVREF
1000P_0402_50V7K~N
PC39
PR109 RB715F_SOT323-3 LM393DR_SO8~N PR79
4
1
1
B PU9 200_0805_5%~N 191K_0402_1%~N B
3.3V
PC41
G920AT24U_SOT89 PC38 PR74
2
0.1U_0603_25V7K~N
2
PRG++ 2
2
CHGRTC PR113 PR112 499K_0402_1%~N
1 2 1 2 3 OUT IN 2
1
4.7U_0805_6.3V6K~N
560_0603_5%~N 560_0603_5%~N
1
GND
PC74
PC72 SSM3K7002FU_SC70-3
1U_0805_25V4Z~N PR76 PQ20 PR80
2
1
1 34K_0402_1%~N D 47K_0402_5%~N
2
2 1 2 2 1
RTCVREF G PACIN <32>
ACIN
1
S
3
PQ19
Precharge detector
1
DTC115EUA_SC70-3
PR77
Min. typ. Max. 66.5K_0402_1%~N 2 +5VALWP
PJP12 PJP4 @
@ JUMP_43X118 @ JUMP_43X118 H-->L 14.589V 14.84V 15.243V
2
+5VALWP 1 1 2 2 +5VALW +1.5VSP
1 1 2 2 +1.5VS L-->H 15.562V 15.97V 16.388V
3
PJP13 PJP1
@ JUMP_43X118 @ JUMP_43X118 BATT ONLY
1 1 2 2 +0.9VP 1 1 2 2 +0.9V Precharge detector
PJP11 PJP10 Min. typ. Max.
@ JUMP_43X118 @ JUMP_43X118
1 1
H-->L 6.138V 6.214V 6.359V
+3VALWP 2 2 +3VALW +1.2VALWP 1 1 2 2 +1.2VALW
L-->H 7.196V 7.349V 7.505V
A PJP8 PJP9 A
@ JUMP_43X118 @ JUMP_43X118
+1.8VP 1 1 2 2 +1.8V 1 1 2 2
PJP7
@ JUMP_43X118
1 1 2 2 Security Classification Compal Secret Data Compal Electronics,Inc.
Issued Date 2007/1/25 Deciphered Date 2008/01/25 Title
SCHEMATICS,MB A4011
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401521 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, November 24, 2008 Sheet 31 of 38
5 4 3 2 1
A B C D E
P2
PQ51 FDS4435BZ_SO8
P3 B+ PQ53
8 1 1 8 AO4407_SO8~N
D S S D
VIN 7 D S 2 2 S D 7 1 4 1 8
6 D S 3 3 S D 6 2 7
5 4 4 5 2 3 PJP14 3 6
1 D G G D PR239 1
2 2 1 1 B++ 5
PQ52 200K_0402_1%~N PR193
FDS4435BZ_SO8 0.02_2512_1% @ JUMP_43X118 CSIP
VIN 1 2
4
2
PR194
PR240 CSIN 1 2
1
150K_0402_1%~N
VIN
1
PR195 PC139 PC138 PC137 30K_0402_5%
1
47K_0402_1%~N @ PQ54
VIN
11
1
D PQ72 4.7U_1206_25V6K~N
28.2 28.2 DTC115EUA_SC70-3
1
PR196 SSM3K7002FU_SC70-3 6251VDD PQ55 PJP15 10U_1206_25VAK
ACOFF
2
2
<26,31>
200K_0402_1%~N G 2 PAD-OPEN1x1m 10U_1206_25VAK 2 PR197
PQ56 S PD24 150K_0402_5%
3
3
DTA144EUA_SC70-3
1 2 TP0610K-T1-E3_SOT23-3
ACOFF##
2
2
28.2
1
3
1
2 PC140 PR198
1
28.2 0.1U_0603_25V7K~N 47K_0402_1%~N PC141 1 24 1 2
2
VDD DCIN
100K_0402_5%~N
1 2 PC173 2.2U_0603_6.3V6K~N PC142
1
RLZ22B_LL34-2
0.1U_0603_25V7K~N 220K_0402_5%~N PD18
PR200 2 23
1
ACSET ACPRN
1
PR201
0_0402_5% PR231
1
1SS355_SOD323-2
1SS355_SOD323-2
PQ58 1 2 CSON
DTC115EUA_SC70-3 0.1U_0402_16V7K~N 3 22
22
EN CSON
2
PC144 PC143 20_0603_1% ACOFF#
2
2 28.2 @ 680P_0402_50V7K 0.047U_0603_16V7K~N
1
CSON1 2 4 21 1 2 CSOP
1
CELLS CSOP
5
6
7
8
1
PR202 PD19
20_0603_1% PQ61 PR203
1
1
D 47K_0402_5%~N
1 2 5 20 2 1 SI4800BDY-T1-E3_SO8~N 28.2
3
1
ICOMP CSIN
2
2 PQ60 PR205 PR204 20_0603_1% 2
28.2 28.2 PD20
1
G SSM3K7002FU_SC70-3 150K_0402_1%~N PC147 PR206PC145 6800P_0402_25V7K~N PC146 PR235 C
2
S 1 2 1 2 6 19 0.1U_0603_25V7K~N
1 2 4 2PQ62
3
1
2 10K_0402_1%~N VCOMP CSIP B PMBT3904_SOT23-3 PQ59 2
28.2
2
3
PD21 @ PC148 1 2 7 18 LX_CHG 28.2 DTC115EUA_SC70-3
ACOFF# 1 100P_0402_50V8J~N 100_0402_1%~N ICM PHASE
2
3
2
1
6251VREF
1
1SS355_SOD323-2 <26> ADP_I 8 17 DH_CHG PL14
PQ63 PC149 PR208 VREF UGATE 16UH_D104C-919AS-160M_3.7A_20%
1 2 @ 0_0402_5%~N PR210 PC150 1 2 CHG 1 4
28.2 BATT+
1
D
SSM3K7002FU_SC70-3
1
PACIN 1 2 2 1 2 0.1U_0402_16V7K~N 2.2_0603_5%~N 0.1U_0402_16V7K~N 2 3
<31> PACIN <26> IREF
2
PR211 G PD22
3K_0402_1%~N S 143K_0402_1%~N 12.7K_0402_1% 10 15 6251VDDP PR209
3
ACLIM VDDP
5
6
7
8
28.2 6251VREF 1 PR213 2 CH751H-40PT_SOD323-2 0.02_2512_1%
1
1
1 26251VDD PC152
2
ACON 11 14 4.7_0603_5% PC151
<31> ACON VADJ LGATE
2
PR215 2 PR2161 PR214 PQ64
2
100K_0402_1%~N 11K_0402_1% 10U_1206_25V6M~N 10U_1206_25V6M~N
12 13 PC153 4 SI4800BDY-T1-E3_SO8~N
2
1
GND PGND 4.7U_0805_6.3V6K~N
6251VREF 1 2
PR217 ISL6251AHAZ-T_QSOP24
@ 28.7K_0402_1%
IREF=0.972*Icharge
3
2
1
1
DL_CHG
IREF=0.6V~3.21V PR218
@ 47K_0402_1%~N
ACLM=(1/0.02)(0.05*Vaclm/2.39+0.05)
where ACLM=1.05V, Iaclm=3.66A
2
3 3
6251VREF BATT+
1
1
PR241
100K_0402_1% 6251_EN PR37
@ 340K_0402_1%
1
C
2
2 PQ73 VS
2
B @ 2SC2411K_SOT23-3
0.01U_0402_25V7K
E
3
1
1
PC174
0.01U_0402_25V7K~N
PR44
499K_0402_1%
2
PC32
PR107
PQ29 CSON PR242
2
2
B+ 1 2 3 TP0610K-T1-E3_SOT23-3
1 @ 20K_0402_1%
B+_BIAS
2
470K_0402_5%
100_0805_5%~N @
2
+5VALW PU3B
PR108
PC71 5
P
+
7
1
0
0.1U_0603_25V7K~N
6
2
-
G
<26> BATT_OVP
1
1
1
220K_0402_5%
PD7 LM358ADT_SO8~N
4
2
PR111
PR52
1SS355_SOD323-2 105K_0402_1%
2
2
SSM3K7002FU_SC70-3
4 PQ32 4
1
D
2
LI-3S :13.5V----BATT-OVP=1.5V
0.1U_0603_25V7K~N
G
220K_0402_5%
S
3
2
32.8
1
PR110
PC75
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A4011
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 401521 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, November 24, 2008 Sheet 32 of 38
A B C D E
5 4 3 2 1
PL15
HCB4532KF-800T90_1812 B+++
B+ 1 2
4.7U_1206_25V6K~N
4.7U_1206_25V6K~N
4.7U_1206_25V6K~N
4.7U_1206_25V6K~N
1
1
PC154
PC155
1
PC156
PC157
2
2
+VCC_TPS51120
VL
D PR219 D
5.1_0603_5%
5
6
7
8
1U_0603_6.3V6M~N
2 1
10U_0805_6.3V6M~N
1
PC158
0.1U_0603_25V7K~N
PQ65 TDC=5.1A
PQ66
PC159
2
8
7
6
5
SI4800BDY-T1-E3_SO8~N 4 SI4800BDY-T1-E3_SO8~N
2
1
PC160
OCP=9.4A
TDC=3.65A +5VALWP
3
2
1
OCP=6A 4 3.3UH_1164AY-3R3N-P3_7.5A_30%
PU14
1 2
22 21 PR220 PC161
VIN VREG5
1000P_0402_50V7K~N
0_0603_5%~N 0.1U_0402_16V7K~N PL16
5
6
7
8
+3VALWP
10K_0402_1%~N
20 28 1 2 1 2
1
2
3
V5FILT VBST1 PQ67
2
PC162 9 27 DH_5V 1 2 SI4810BDY-T1-E3_SO8~N
PL17 EN5 DRVH1
1
PR221
PC163
220U_6.3V_M
0.1U_0402_16V7K~N 0_0603_5%~N PR237 0_0603_5%~N
2 1 2 1 1 2 13 32 QFN 5X5 LL1 26 LX_5V 1
VBST2
1000P_0402_50V7K~N
PR222 4
2
PQ68
10K_0402_1%~N
+
220U_6.3V_M
1
DRVH2 DRVL1
2
8
7
6
5
SI4810BDY-T1-E3_SO8~N
PC164
1 PR238 0_0603_5%~N
1
PC166
LX_3V 15 24
+ LL2 PGND1 2
PR223
3
2
1
2
PC165
2.49K_0402_1%~N
DL_3V 16 1
2
DRVL2 VO1
1
PR224
4 17 3 FB5
C
PGND2 VFB1 C
COMP1 2
8 7
1
@ VO2 COMP2 TPS51120_CS1
CS1 23
2
4.22K_0402_1%~N
FB3 6 18 TPS51120_CS2
1
2
3
VFB2 CS2
VREF2 4
PR225
12 EN2 TONSEL 31
1000P_0402_50V7K~N
29 EN1 GND 5
30
1
SKIPSEL
PGOOD1
19 VREG3 PGOOD2 11
+VCC_TPS51120
PAD
1
PC167
15.4K_0402_1%
10 EN3
2
10U_0805_6.3V6M~N
32
33
PR226
10.5K_0402_1%
TPS51120RHBR_QFN32_5X5~N
2
+3.3V_RTC_LDO
0_0402_5%~N
PR227
2
1
2
PR229
ripple current
PC168
[(19-3.3)*D]/(3.3UH*430K)
1
1
PR228
=1.92A PD23
1
0_0402_5%~N
1
FB pin ripple around 14.24mV VS 1 2 1 PR230 2 @
2.2U_0805_25V6K
48*4.22/(10+4.22)=14.24mV
PC169
B B
OCP: 10uA*10.5K/(0.016*1.3)=5.05A
<26> PWR_SKIP#
5.05A+1.92A/2=6A
1
VL ripple current
[(19-5)*D]/(3.3UH*280K)
=3.99A
806K_0603_1%~N
0_0402_5%~N
2 1
<31,37> MAINPWON OCP: 10uA*15.4K/(0.016*1.3)=7.4A
1
PC170
7.4A+3.99A/2=9.4A
0.047U_0603_16V7K~N
2
A A
5 4 3 2 1
5 4 3 2 1
D D
B++++
PL6
FBMA-L11-322513-151LMA50T_1210
2 1 B+
4.7U_1206_25V6K~N
4.7U_1206_25V6K~N
4.7U_1206_25V6K~N
4.7U_1206_25V6K~N
1
1
PC67
PC65
PC63
10_0805_5%~N
0.1U_0603_25V7K~N
1
PC61
PC64
PR106
0.1U_0603_25V7K~N
PC68
2
2
@ @
2
+5VALWP
2.2U_0603_6.3V6K~N
2.2U_0603_6.3V6K~N
1
2.2_0603_5%~N
8
7
6
5
1
PC58
PR162
PC121
0.1U_0603_25V7K~N
1
1
PQ28 PD4
5
6
7
8
PC66
SI4800BDY-T1-E3_SO8~N CHP202UPT_SOT323-3
2
PQ27
1
SI4800BDY-T1-E3_SO8~N
4
3
TDC=7A BST_1.8V-2 4
BST_1.2V-2
OCP=10A
1
2
3
14
28
PC128 PU8 PC127
3
2
1
+1.2VALWP PL13 2 1 12 17 2 1
VIN
VCC
1.8U_D104C-919AS-1R8N_9.5A_30% SOFT1 SOFT2
1 2 0.01U_0402_25V7K~N 0.01U_0402_25V7K~N
1 TDC=6A
2 1 1 2BST_1.2V-16 BOOT1 BOOT2 23 BST_1.8V-1
1 2 2 1
+
220U_6.3V_M
4 PHASE1 PHASE2 25 1 2
1
1
S/A
S/A
S/A
PR101 PR102
1
5
6
7
8
+
PC123
220U_6.3V_M
1K_0402_1%~N 1K_0402_1% PQ25
PC124
PR164 1 2 ISE_1.2V 7 22 ISE_1.8V 1 2 AO4704_SO8~N
D/K
D/K
D/K
D/K
2
1
2
3
4
0.01U_0402_25V7K~N
1
DL_1.2V DL_1.8V 2
10.2K_0402_1%
2 LGATE1 LGATE2 27
1
1
S/A
S/A
S/A
PC122
PR104
2
PR163
PR165 0_0402_5%~N
3.4K_0402_1%
4
3
2
1
2
3 26
2
PGND1 PGND2
2
2
VOUT_1.2V 9 20 VOUT_1.8V
VSE_1.2V VOUT1 VOUT2 VSE_1.8V
0.9V 10 VSEN1 VSEN2 19 0.9V
8 EN1 EN2 21 1 2
15 16 SYSON <26,27,30>
PG1 PG2/REF
10K_0402_1%
PR172 10K_0402_5%~N
GND
DDR
1
1
10K_0402_1%~N
PR166
1 PR103 2 1 PR105
1
PR168
13
@ 0_0402_5%~N 47K_0402_1%~N PC62 PR171 PR170 PC126
2
1
2
0.1U_0402_16V7K~N
2
2
B B
A A
+1.5VSP/+0.9VSP
+1.8V
+1.8V
D D
1
PJP2
1
@ JUMP_43X118 PJP3
1
@ JUMP_43X118
2
2
2
PU6
1.8V_0.9V 1 6 +3VALWP PU11
VIN VCNTL 1.8V_1.5V 1 VIN VCNTL 6 +3VALWP
2 GND NC 5
1
2 GND NC 5
1
PC54 3 7 PC47
VREF NC
1
4.7U_0805_6.3V6K~N 1U_0603_6.3V6M~N PC91 3 7 PC92
2
2
PR94 4.7U_0805_6.3V6K~N VREF NC 1U_0603_6.3V6M~N
4 8
2
1K_0402_1%~N VOUT NC PR133 4 VOUT NC 8
9 200_0402_1%~N
2
TP
9
2
G2992F1U_SO8~N TP
PR88 G2992F1U_SO8~N
PQ22 +0.9VP PR132
1
1
0_0402_5%~N D PQ37 +1.5VSP
1
D
SSM3K7002FU_SC70-3
1 2 2 0_0402_5%~N
1
<6,30> SYSON#
SSM3K7002FU_SC70-3
G PR95 PC50 1 2 2
1
S PC48 <28,30> SUSP G PR131 PC89
3
2
1
4.7U_0805_6.3V6K~N S PC90
2
2
1
PC49 4.7U_0805_6.3V6K~N
2
@0.1U_0402_16V7K~N PC88
2
@0.1U_0402_16V7K~N
2
1K_0402_1%~N 0.1U_0402_16V7K~N
1K_0402_1%~N 0.1U_0402_16V7K~N
C C
B B
A A
B+
CPU_B+
+5VS
PL7
PR146 10_0402_5%
HCB4532KF-800T90_1812
+3VS
1 2
0.01U_0402_25V7K~N
2200P_0402_50V7K~N
10U_1206_25VAK
10U_1206_25VAK
0.01U_0402_25V7K~N
1
680P_0402_50V7K
220U_25V_M
PC104
1
PC93
PC112
PC111
1
+
PC172
2
PC109
PC105
2
2
D D
2
1
2
10K_0402_5%
2.2U_0603_6.3V6K~N
@ PR15
5
PC110
PC108
PQ42
2
2.2U_0603_6.3V6K~N SI7686DP-T1-E3_SO8
1
PU2
0.22U_0603_16V7K~N
1
1
4
PC19
VCC 19 25
VCC VDD
2
2 1 31 5 PR45
<6> VID0 PR40 0_0402_5%~N D0 THRM 2.2_0603_5%~N
3
2
1
2 1 32 30 1 2 PR148
<6> VID1 D1 BST1
PR39 0_0402_5%~N 0_0603_5%~N +CPU_CORE
2 1 33 29 DH1 1 2 PL10
<6> VID2 PR36 0_0402_5%~N D2 DH1 0.36UH_PCMC104T-R36MN1R17_30A_20%
2 1 34 28 LX1 1 2
<6> VID3 PR35 0_0402_5%~N D3 LX1
2
680P_0603_50V8J 4.7_1206_5%~N
2 1 35 26 DL1
<6> VID4 D4 DL1
5
6
7
8
D 5
D 6
D 7
D 8
1
4700P_0402_25V7K
PR62
4.22K_0402_1%~N
PR31 0_0402_5%~N PD15
SI4856DY-T1-E3_SO8
SI4856DY-T1-E3_SO8
2 1 36 27 PGND1
D
D
D
D
<6> VID5 D5 PGND1
1
PQ16
PQ11
PR57
PR30 0_0402_5%~N
1
PC25
1 2 1 16 @ SSM34PT_SMA-2
1
VGATE @ PR8 0_0402_5%~N PWRGD CSP1
2
G
4 G
S
S
S
3 S
2 S
1 S
+3VS 1 2 17 15 PH3
2
PHASEGD CSN1
1
PR42 100K_0402_1%~N @ PR61 10KB_0603_ERTJ1VR103J
4
3
2
1
1
PC33
PR28 TP VCC 37 18 AGND 2.1K_0402_1%~N
C 0_0402_5%~N TWO-PH GND PR3 C
1 2 1 2
2
2
<26> VR_ON 1 2 38 40 PR16 PC94 10_0402_5%~N
@ PR27 PR139 71.5K_0402_1%~N SHDN IC 2.55K_0603_1%~N 4700P_0402_25V7K @
2100_0402_1%~N
PR2
1 2 2 1 6 11 FB 1 2 1 2 1 2
2
PC99 TIME FB PR4 20K_0402_1%~N
100K_0402_5%~N 2 1 8 9 1 2 1 2 PR34 0_0402_5% PC29
PR12 10K_0402_1%~N CCV CCI PC3 470P_0402_50V8J~N 0.22U_0603_16V7K~N
+
1 2
EC_ADC
1
1 2 150P_0402_50V8J~N 3 20
POUT BST2
1
1 2 1 2 REF 10 21 DH2
PC1 PR11 PC97 0.1U_0603_25V7K~N REF DH2 PC178
2
0.1U_0402_16V7K~N CPU_B+ 1 2 7 22 LX2 PC177 @ 220P_0402_50V7K
200K_0402_1%~N TON LX2 @ 220P_0402_50V7K
REF 1 2 2 24 DL2
PR13 OFS DL2
1
31.6K_0402_1%~N PR21 4 23 PGND2
VRHOT PGND2
1
0_0402_5%~N CPU_B+
PR14 CSP2 0_0402_5%~N
2 1 39 SKIP CSP2 13
169K_0603_1%~N PR1
2.2_0603_5%~N
14
2
CSN2
GNDS
2200P_0402_50V7K~N
PR49
10U_1206_25VAK
10U_1206_25VAK
0.01U_0402_25V7K~N
1 2
EP
1
D
PC103
PQ38
PC9
2 PQ44
+3VS
41
12
PC100
PC101
G SSM3K7002FU_SC70-3 MAX8774GTL+_TQFN40_6X6~N
2
S SI7686DP-T1-E3_SO8 <6> CPU_VDD_FB_H
3
4
1
0.22U_0603_16V7K~N
1
1
B PR22 PC102 PR26 B
100_0402_1%~N
PC20
PR23 200K_0402_1%~N 4700P_0603_50V7K~N
2
200K_0402_1%~N PR151
3
2
1
0_0603_5%~N
2
1 2
2
PL9
1
PQ8 D 0.36UH_PCMC104T-R36MN1R17_30A_20%
2 1 2
680P_0603_50V8J 4.7_1206_5%~N
G SSM3K7002FU_SC70-3
1
SI4856DY-T1-E3_SO8
SI4856DY-T1-E3_SO8
S
3
D 5
D 6
D 7
D 8
5
6
7
8
2
PR66
<6> CPU_PSI# 2 PQ10
1
2 FDV301N_NL_SOT23-3 PD14 PR56
D
D
D
D
1
PQ18
3 4.22K_0402_1%~N
3
PQ17
PR25 @
10_0402_5%~N PR187 SSM34PT_SMA-2
1
4 G
1
3 S
2 S
1 S
S
S
S
0_0402_5%~N PR60 PH2
2
PC36
2.1K_0402_1%~N 10KB_0603_ERTJ1VR103J
2
4
3
2
1
@ PC24 1 2 1 2
2
2
4700P_0402_25V7K
@
1 2 PC28
0.22U_0603_16V7K~N
1 2
<6> CPU_VDD_FB_L
CSP2
PR144
0_0402_5%~N PR29
AGND 1 2 1 2
A A
1
0_0402_5%~N
@ PC175 PC176
220P_0402_50V7K 220P_0402_50V7K
2
BATT++ PJ23
DC040003600 PAD-OPEN 3x3m
1 2 BATT+
PJP5
1 BATT++ 1 2
1 +3VALWP
2 2
1000P_0603_50V7K
1000P_0603_50V7K
D CNT1 PR48 @ PR33
@PR33 D
3 3
0.01U_0603_50V7K
4 CNT2 1 2 100K_0402_5%
4 +3VALWP
1
5 EC_SMCA
5
Battery Connect/OTP
1
PC16
PC18
PC17
6 EC_SMDA @ 100K_0402_5%
6 TS_A
7
2
7
2
1K_0402_1%
8 GND
2
8
PR38
9 9
G1 10
G2 11 PR46
1K_0402_1%
1
SUYIN_200275MR009G180ZR
1
100_0402_1%
1
1
100_0402_1%
PR41
PR53
2
6.49K_0402_1%
1
PR47
2
BATT_TEMP <26>
VL VS
2
1
PC115
0.1U_0603_25V7K~N
CPU
1
PR87
10.7K_0402_1%~N VL
2
PR82
442K_0402_1%~N
2
1 2
PR81
150K_0402_1%~N
PR83
1
8
61.9K_0402_1%~N PU3A
1 2 3 PD25
P
B +
1 1 2 MAINPWON <31,33> B
0
VL 1 2 2 -
G
PR84 1SS355_SOD323-2
150K_0402_1%~N LM358ADT_SO8~N
4
1
PH1
1
1
1
100K_0603_1%_TH11-4H104FT
PC43 PR85
2
1000P_0402_50V7K~N 150K_0402_1%~N
2
2
PC42
1U_0603_6.3V6M~N
A A
D D
C
Modify 1.8 OCP to 14A PR170 to 49.9K, C
B B
A A