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Compal Confidential 2

KAW60 Schematics Document


AMD AM2 / RS690MC / SB600
2008 / 08 / 08 Rev:1.0 FOR Pre-MP
3 3

4 4

Security Classification Compal Secret Data


Issued Date 2005/05/09 Deciphered Date 2006/03/08 Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 1 of 50
A B C D E
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Compal confidential
Project Code: KAW60 AMD AM2 CPU
Thermal Sensor Clock Generator DDRII 533/667 DDRII-SO-DIMM X2
File Name : LA-4661P
ADM1032ARM ICS951462 940P PGA page 10,11
page 6,7,8,9
page 8 page 17 Dual Channel
D D

H_A#(3..31) H_D#(0..63)
HT 16x16 1000MHZ

SIG1 : 35mm x 35mm x (2.20mm+2.11mm) 638pin


CRT & TV-OUT AM2 : 40mm x 40mm x (4.56mm+2.11mm) 940pin
page 24 ATI-RS690MC
465 BGA RS485 : 21mm x 21mm (19.2mm x 19.2mm) x2.33mm 465pin
RS690 : 21mm x 21mm (19.2mm x 19.2mm) x2.33mm 465pin

Mini card LCD CONN


page 12,13,14,15,16
page 25 SB460 : 27mm x 27mm (21.6mm x 21.6mm) x2.33mm 549pin
page 31 SB600 : 23mm x 23mm (21.6mm x 21.6mm) x2.33mm 549pin
A-Link Express
4 x PCIE
PCIE X1

PCIE X1
USB 2.0 USB conn x 2 / New card / Camera
C
page 34 page 31 C

ATI-SB600 USB 2.0 BT Conn


page 38
PCI BUS 549 BGA
HDA Codec
HD Audio AMP & Audio Jack
ALC268 page 40
Realtek page 18,19,20,21,22 page 39 APA2057
Mini PCI Socket RTL8100CL ENE Controller 1394 Controller MDC Conn.
Mini card RTL8110SCL CB714 VT6311S page 41
page 31 page 26 page 35
page 32
SATA HDD Conn.
page 23
Realtek 6in1 CardReader LPC BUS
RJ45 CONN Slot 0 1394
B RTL8102EL Slot Conn. B
page 27 page 33 page 33 page 35
page 26 SATA
CDROM Conn.
page 23
Power On/Off CKT / LID switch / Power OK CKT
page 37
SMsC LPC47N207 ENE KB926
page 36 page 28
DC/DC Interface CKT. CIR/LED RTC CKT.
page 41 page 38 page 18

Int. KBD
Power Circuit DC/DC FIR module page 29
page 42~48
page 36 Touch Pad
CONN. page 29
SPI BIOS
A
page 30 A

Security Classification Compal Secret Data


Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
BLOCK DIAGRAM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sunday, July 20, 2008 Sheet 2 of 50
5 4 3 2 1
5 4 3 2 1

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
D D
B+ AC or battery power rail for power circuit. N/A N/A N/A
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9V 0.9V switched power rail for DDR terminator ON ON OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.2V_HT 1.2V switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8VALW 1.8V always on power rail ON ON ON* Board ID / SKU ID Table for AD channel
+1.8V 1.8V power rail for DDR ON ON OFF Vcc 3.3V +/- 5%
+1.8VS 1.8V switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+2.5VS 2.5V switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+3VALW 3.3V always on power rail ON ON ON* 0 0 0 V 0 V 0 V
+3VS 3.3V switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+5VALW 5V always on power rail ON ON ON* 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+5VS 5V switched power rail ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+VSB VSB always on power rail ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+RTCVCC RTC power ON ON ON 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
C C
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V

BOARD ID Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

External PCI Devices Board ID PCB Revision BTO Option Table


Device IDSEL# REQ#/GNT# Interrupts
0
BTO Item BOM Structure
1
WITH AMD HDT Debug port HDT@
2
WITH USBx2 USB2@
3
USBX1 WITH CHOKE EMI@
4
USBX1 WITHOUT CHOKE WOEMI@
5
USBx2 WITH CHOKE USB2EMI@
6
USBx2 WITHOUT CHOKE USB2WOEMI@
7
WITH MODEM MDC@
B B
SPI ROM under SB600 SB600SPI@
EC SM Bus1 address EC SM Bus2 address SKU ID Table
Device Address Device Address SKU ID SKU
Smart Battery 0001 011X b ADM1032 1001 100X b 0
EEPROM(24C16/02) 1010 000X b 1
(24C04) 1011 000X b 2
3
4
5
SB600 SM Bus address 6
7
Device Address

Clock Generator 1101 001Xb


(ICS951462)
A DDR DIMM0 A
1001 000Xb
DDR DIMM2 1001 010Xb

Security Classification Compal Secret Data


Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
TABLE OF CONTENTS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HCW51 LA-3121P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 24, 2008 Sheet 3 of 50
5 4 3 2 1
5 4 3 2 1

D D

DIMM3 DIMM4
PCI CLKFB

PCI CLK
DIMM1 DIMM2
33MHZ

PCI CLK0
PCI SLOT0
3 PAIR MEM CLK

3 PAIR MEM CLK

33MHZ
3 PAIR MEM CLK

3 PAIR MEM CLK

PCI CLK1
PCI SLOT1
33MHZ

HTREFCLK PCI CLK1


PCI SLOT2
66MHZ 33MHZ
ATI NB -RS690 ATI SB
M2 CPU 1 PAIR CPU CLK NB-OSC PCI CLK6
LPC BIOS
200MHZ 14.318MHZ SB600 33MHZ
C
M2 SOCKET 14.318MHZ OSC INPUT C
(OPTION)

14.318MHZ
SB-OSCIN
TVCLKIN
NB PCIE CLK
100MHZ
SB PCIE CLK PCI CLK5 KB_CLK
KEYBOARD
100MHZ 33MHZ SUPER IO
SB-OSCIN SB-OSCIN SIO_CLK IT8712F MS_CLK
EXTERNAL
14.318MHZ 14.318MHZ 24/48MHZ MOUSE
CLK GEN.
PCIE CLK
100MHZ PCIE GFX SLOT - 16 LANES
PCIE CLK
AZ_BITCLK AC97 CODEC 24.576MHZ OSC INPUT
100MHZ PCIE GPP SLOT 1 - 1 LANE
AZALIA
PCIE CLK
100MHZ PCIE GPP SLOT 2 - 1 LANE
PCIE CLK
100MHZ PCIE GBE

25M Hz
B B

PCIE CLK
100MHZ PCIE STAT

PCIE CLK
100MHZ
USB CLK
48MHZ

32.768K Hz
48MHZ OSC INPUT FOR USB
(OPTION)

14.31818MHz

A A

Security Classification Compal Secret Data


Issued Date 2005/10/10 Deciphered Date 2006/10/10 Title
CLOCK DISTRIBUTION
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 17, 2008 Sheet 4 of 50
5 4 3 2 1
5 4 3 2 1

CPU_VDDA_RUN (S0, S1) M2


CPU 2.5V SHUNT
REGULATOR VDDA 2.5V 0.1A
ATX P/S WITH 1A STBY CURRENT PW CPU_VDD_RUN (S0, S1) VDDCORE
5VSB 5V 3.3V 12V -12V 12V 0.8-1.55V 80A
+/-5% +/-5% +/-5% +/-5% +/-5% +/-5% CPU_VTT_SUS (S0,S1,S3)
DDRII MEM I/F VTT
CPU_VDDIO_SUS(S0,S1,S3) 0.125A, VDD 3A
VRM SW VLDT 1.2V 0.5A
REGULATOR
DDRII DIMMs
0.9V VTT_DDR
D D
REGULATOR VTT_DDR 2A RS690
+5VDUAL_MEM (S0,S5) 1.8V VDD SW VDDHT 1.2V 0.5A
REGULATOR VDD MEM 12A
PCI-E CORE&VCO
& I/O &PLL 2.25A
NB CORE VDDC
1.2V 5A
1.8V LINEAR +1.8V(S0, S1)
DAC 200mA LVDS
REGULATOR 1.8V 300mA
PLL & DAC-Q 0.1A

VCC 1.2V SW VCC_NB (S0, S1)


PCI-E PLL
REGULATOR

+3.3VSB (S0, S1, S3, S4, S5)


+3.3VDUAL (S0, S1, S3, S4, S5)
+3.3VSB REGULATOR SB600
ACPI CONTROLLER
+5VDUAL (S0, S1, S3, S4, S5) X4 PCI-E 0.8A
C ATA I/O 0.2A C

ATA PLL 0.01A


PCI-E PVDD 80mA
SB CORE 0.6A
1.2V STB LDO +1.2VSB (S5) 1.2V S5 PW 0.22A
REGULATOR
3.3V S5 PW 0.01A
USB CORE I/O 0.2A
3.3V I/O 0.45A

AZALIA CODEC
3.3V CORE 0.3A
5V ANALOG 0.1A
B B

SUPER I/O

+5V SD 0.01A
+5V 0.1A

PCI Slot (per slot) X1 PCIE per X16 PCIE CNR CONNECTOR USB X4 FR USB X6 RL 2XPS/2 GBE SATA

5V 5.0A 3.3V 3.0A 3.3V 3.0A 5V 1.0A VDD VDD 5VDual 3.3V 0.5A (S0, S1) 3.3V 0.3A (S0, S1)
3.3V 7.6A 3.3V 1.0A 5VDual 5VDual 3.3V 0.1A (S3)
12V 0.5A 12V 5.5A 1.0A
12V 0.5A 12V 0.5A 2.0A 2.0A
A
3.3Vaux 0.1A A
3.3Vaux 0.375A 3.3Vaux 1.0A
-12V 0.1A -12V 0.1A
5VDual 0.5A
Security Classification Compal Secret Data
+3.3VDUAL (S0, S1, S3)
Issued Date 2005/10/10 Deciphered Date 2006/10/10 Title
POWER DELIVERY CHART
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, June 17, 2008 Sheet 5 of 50
5 4 3 2 1
5 4 3 2 1

PROCESSOR HYPERTRANSPORT INTERFACE


D D
VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

+1.2V_HT
JCPU1A
AJ4 VLDT_06 VLDT_08 H6 1 2 C455
AJ3 H5 4.7U_0805_10V4Z
VLDT_05 VLDT_07
AJ2 H2
AJ1
VLDT_02
VLDT_01
VLDT_04
VLDT_03 H1 FAN Conn
H_CADIP15 U6 Y5 H_CADOP15
12 H_CADIP15 L0_CADIN_H15 L0_CADOUT_H15 H_CADOP15 12
H_CADIN15 V6 Y4 H_CADON15
12 H_CADIN15 L0_CADIN_L15 L0_CADOUT_L15 H_CADON15 12
H_CADIP14 T4 AB6 H_CADOP14
12 H_CADIP14 L0_CADIN_H14 L0_CADOUT_H14 H_CADOP14 12
H_CADIN14 T5 AA6 H_CADON14
12 H_CADIN14 L0_CADIN_L14 L0_CADOUT_L14 H_CADON14 12
H_CADIP13 R6 AB5 H_CADOP13
12 H_CADIP13 H_CADOP13 12
12
12
H_CADIN13
H_CADIP12
H_CADIN13
H_CADIP12
H_CADIN12
T6
P4
P5
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
AB4
AD6
AC6
H_CADON13
H_CADOP12
H_CADON12
H_CADON13
H_CADOP12
12
12
+5VS
C47
1
10U_0805_10V4Z
2
PVT +5VS

12 H_CADIN12 L0_CADIN_L12 L0_CADOUT_L12 H_CADON12 12

1
H_CADIP11 M4 AF6 H_CADOP11
12 H_CADIP11 L0_CADIN_H11 L0_CADOUT_H11 H_CADOP11 12
H_CADIN11 M5 AE6 H_CADON11 U1 D3
12 H_CADIN11 L0_CADIN_L11 L0_CADOUT_L11 H_CADON11 12
H_CADIP10 L6 AF5 H_CADOP10 1 VEN 8 CH355PT_SOD323 W=40mils
12 H_CADIP10 L0_CADIN_H10 L0_CADOUT_H10 H_CADOP10 12 GND
H_CADIN10 M6 AF4 H_CADON10 2 VIN 7
12 H_CADIN10 L0_CADIN_L10 L0_CADOUT_L10 H_CADON10 12 GND +VCC_FAN1
H_CADIP9 K4 AH6 H_CADOP9 +VCC_FAN1 3 6
12 H_CADIP9 H_CADOP9 12

2
H_CADIN9 L0_CADIN_H9 L0_CADOUT_H9 H_CADON9 EN_DFAN1_R 4 VO GND
12 H_CADIN9 K5 L0_CADIN_L9 L0_CADOUT_L9 AG6 H_CADON9 12 28 EN_DFAN1 1 2 VSET GND 5
H_CADIP8 J6 AH5 H_CADOP8 1 FAN1 1 2
12 H_CADIP8 L0_CADIN_H8 L0_CADOUT_H8 H_CADOP8 12
H_CADIN8 K6 AH4 H_CADON8 R733 0_0402_5% APL5605_SOP8L C83 10U_0805_10V4Z
12 H_CADIN8 L0_CADIN_L8 L0_CADOUT_L8 H_CADON8 12

1
C H_CADIP7 H_CADOP7 C760 C
HT LINK

12 H_CADIP7 U3 L0_CADIN_H7 L0_CADOUT_H7 Y1 H_CADOP7 12


H_CADIN7 U2 W1 H_CADON7 @ 0.01U_0402_16V7K D4
12 H_CADIN7 L0_CADIN_L7 L0_CADOUT_L7 H_CADON7 12 2
H_CADIP6 R1 AA2 H_CADOP6 BAS16_SOT23-3 1 2
12 H_CADIP6 L0_CADIN_H6 L0_CADOUT_H6 H_CADOP6 12
H_CADIN6 T1 AA3 H_CADON6 C90 1000P_0402_50V7K
12 H_CADIN6 L0_CADIN_L6 L0_CADOUT_L6 H_CADON6 12
H_CADIP5 R3 AB1 H_CADOP5
12 H_CADIP5 H_CADOP5 12

2
H_CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5 JP20
12 H_CADIN5
H_CADIP4
R2
N1
L0_CADIN_L5 L0_CADOUT_L5 AA1
AC2 H_CADOP4
H_CADON5 12 PVT 1
12 H_CADIP4 L0_CADIN_H4 L0_CADOUT_H4 H_CADOP4 12 +3VS 1
H_CADIN4 P1 AC3 H_CADON4 2
12 H_CADIN4 L0_CADIN_L4 L0_CADOUT_L4 H_CADON4 12 2
H_CADIP3 L1 AE2 H_CADOP3 3
12 H_CADIP3 L0_CADIN_H3 L0_CADOUT_H3 H_CADOP3 12 3
H_CADIN3 M1 AE3 H_CADON3
12 H_CADIN3 L0_CADIN_L3 L0_CADOUT_L3 H_CADON3 12

1
H_CADIP2 L3 AF1 H_CADOP2 1 4
12 H_CADIP2 L0_CADIN_H2 L0_CADOUT_H2 H_CADOP2 12 GND
H_CADIN2 L2 AE1 H_CADON2 R34 5
12 H_CADIN2 L0_CADIN_L2 L0_CADOUT_L2 H_CADON2 12 GND
H_CADIP1 J1 AG2 H_CADOP1 C92
12 H_CADIP1 L0_CADIN_H1 L0_CADOUT_H1 H_CADOP1 12
H_CADIN1 K1 AG3 H_CADON1 10K_0402_5% 1000P_0402_50V7K ACES_85205-03001
12 H_CADIN1 L0_CADIN_L1 L0_CADOUT_L1 H_CADON1 12 2
H_CADIP0 J3 AH1 H_CADOP0
12 H_CADIP0 H_CADOP0 12

2
H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0 CONN@
12 H_CADIN0 J2 L0_CADIN_L0 L0_CADOUT_L0 AG1 H_CADON0 12 28 FAN_SPEED1
H_CLKIP1 N6 AD5 H_CLKOP1
12 H_CLKIP1 L0_CLKIN_H1 L0_CLKOUT_H1 H_CLKOP1 12
H_CLKIN1 P6 AD4 H_CLKON1
12 H_CLKIN1 L0_CLKIN_L1 L0_CLKOUT_L1 H_CLKON1 12
+1.2V_HT H_CLKIP0 N3 AD1 H_CLKOP0
12 H_CLKIP0 L0_CLKIN_H0 L0_CLKOUT_H0 H_CLKOP0 12
H_CLKIN0 N2 AC1 H_CLKON0
12 H_CLKIN0 L0_CLKIN_L0 L0_CLKOUT_L0 H_CLKON0 12
R38 1 2 51_0402_1% H_CTLIP1 V4 Y6
R37 1 H_CTLIN1 L0_CTLIN_H1 L0_CTLOUT_H1
2 51_0402_1% V5 L0_CTLIN_L1 L0_CTLOUT_L1 W6

H_CTLIP0 U1 W2 H_CTLOP0
12 H_CTLIP0 L0_CTLIN_H0 L0_CTLOUT_H0 H_CTLOP0 12
H_CTLIN0 V1 W3 H_CTLON0
12 H_CTLIN0 L0_CTLIN_L0 L0_CTLOUT_L0 H_CTLON0 12

Trace length limit (Don't care) TYCO_1-1735315-4_940P


B B
CONN@

SOC127MM48X51-948! 6090022000; JCPU1


TEMP SYMBOL

+1.2V_HT
C145
180P_0402_50V8J
1 1 1 1 1 1
C164 C156 C158 C163
C152
180P_0402_50V8J
2 2 2 2 2 2
4.7U_0805_10V4Z 0.22U_0402_10V4Z
4.7U_0805_10V4Z 0.22U_0402_10V4Z

LAYOUT: Place bypass cap on topside of board


NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY
TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY
A A
TO OTHER HT POWER PINS
PLACE CLOSE TO VLDT0 POWER PINS

Security Classification Compal Secret Data


Issued Date 2005/10/11 Deciphered Date 2006/10/11 Title
AMD CPU HT I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 6 of 50
5 4 3 2 1
A B C D E

VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER


Processor DDR2 Memory Interface
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE 11 DDR_B_D[63..0]
JCPU1C
DDR_A_D[63..0] 10
DDR_B_D63 AH13 AE14 DDR_A_D63
DDR_B_D62 MB_DATA63 MA_DATA63 DDR_A_D62
AL13 MB_DATA62 MA_DATA62 AG14
DDR_B_D61 AL15 AG16 DDR_A_D61
DDR_B_D60 MB_DATA61 MA_DATA61 DDR_A_D60
AJ15 MB_DATA60 MA_DATA60 AD17
DDR_B_D59 AF13 AD13 DDR_A_D59
DDR_B_D58 MB_DATA59 MA_DATA59 DDR_A_D58
AG13 MB_DATA58 MA_DATA58 AE13
DDR_B_D57 AL14 AG15 DDR_A_D57
DDR_B_D56 MB_DATA57 MA_DATA57 DDR_A_D56
AK15 MB_DATA56 MA_DATA56 AE16
DDR_B_D55 AL16 AG17 DDR_A_D55
4 DDR_B_D54 MB_DATA55 MA_DATA55 DDR_A_D54 4
AL17 MB_DATA54 MA_DATA54 AE18
DDR_B_D53 AK21 AD21 DDR_A_D53
DDR_B_D52 MB_DATA53 MA_DATA53 DDR_A_D52
AL21 MB_DATA52 MA_DATA52 AG22
DDR_B_D51 AH15 AE17 DDR_A_D51
DDR_B_D50 MB_DATA51 MA_DATA51 DDR_A_D50
AJ16 MB_DATA50 MA_DATA50 AF17
DDR_B_D49 AH19 AF21 DDR_A_D49
+0.9V DDR_B_D48 MB_DATA49 MA_DATA49 DDR_A_D48
AL20 MB_DATA48 MA_DATA48 AE21
JCPU1B DDR_B_D47 AJ22 AF23 DDR_A_D47

DDRII: DATA
DDR_B_D46 MB_DATA47 MA_DATA47 DDR_A_D46
D12 VTT1 AL22 MB_DATA46 MA_DATA46 AE23
C12 AE20 DDR_B_D45 AL24 AJ26 DDR_A_D45
VTT2 MA1_CLK_H2 DDR_B_D44 MB_DATA45 MA_DATA45 DDR_A_D44
B12 VTT3 MA1_CLK_L2 AE19 AK25 MB_DATA44 MA_DATA44 AG26
A12 G20 DDR_B_D43 AJ21 AE22 DDR_A_D43
VTT4 MA1_CLK_H1 DDR_B_D42 MB_DATA43 MA_DATA43 DDR_A_D42
AK12 VTT5 MA1_CLK_L1 G21 AH21 MB_DATA42 MA_DATA42 AG23
+1.8V AJ12 V27 DDR_B_D41 AH23 AH25 DDR_A_D41
VTT6 MA1_CLK_H0 DDR_B_D40 MB_DATA41 MA_DATA41 DDR_A_D40
AH12 VTT7 MA1_CLK_L0 W27 AJ24 MB_DATA40 MA_DATA40 AF25
+0.9VREF_CPU AG12 VTT8 MA0_CLK_H2 AG21 DDR_A_CLK2 DDR_A_CLK2 10
DDR_B_D39 AL27 MB_DATA39 MA_DATA39 AJ28 DDR_A_D39
AL12 VTT9 MA0_CLK_L2 AG20 DDR_A_CLK#2 DDR_A_CLK#2 10
DDR_B_D38 AK27 MB_DATA38 MA_DATA38 AJ29 DDR_A_D38
1

MA0_CLK_H1 G19 DDR_A_CLK1 DDR_A_CLK1 10


DDR_B_D37 AH31 MB_DATA37 MA_DATA37 AF29 DDR_A_D37
R13 F12 MEMVREF MA0_CLK_L1 H19 DDR_A_CLK#1 DDR_A_CLK#1 10
DDR_B_D36 AG30 MB_DATA36 MA_DATA36 AE26 DDR_A_D36
39.2_0402_1%~D U27 DDR_B_D35 AL25 AJ27 DDR_A_D35
PAD TP3 VTT_SENSE MA0_CLK_H0 DDR_B_D34 MB_DATA35 MA_DATA35 DDR_A_D34
E12 VTT_SENSE MA0_CLK_L0 U26 AL26 MB_DATA34 MA_DATA34 AH27
DDR_B_D33 AJ30 AG29 DDR_A_D33
2

M_ZN DDR_B_D32 MB_DATA33 MA_DATA33 DDR_A_D32


AH11 MEMZN MB1_CLK_H2 AL19 AJ31 MB_DATA32 MA_DATA32 AF27
M_ZP AJ11 AL18 DDR_B_D31 E31 E29 DDR_A_D31
MEMZP MB1_CLK_L2 DDR_B_D30 MB_DATA31 MA_DATA31 DDR_A_D30
C19 E30 E28
10:8:10:8:10

DDR II: CMD/CTRL/CLK


R22 DDR_CS3_DIMMA# MB1_CLK_H1 DDR_B_D29 MB_DATA30 MA_DATA30 DDR_A_D29
10 DDR_CS3_DIMMA# AD27 MA1_CS_L1 MB1_CLK_L1 D19 B27 MB_DATA29 MA_DATA29 D27
1

39.2_0402_1%~D DDR_CS2_DIMMA# AA25 W29 DDR_B_D28 A27 C27 DDR_A_D28


10 DDR_CS2_DIMMA# MA1_CS_L0 MB1_CLK_H0 MB_DATA28 MA_DATA28
DDR_CS1_DIMMA# AC25 W28 DDR_B_D27 F29 G26 DDR_A_D27
10 DDR_CS1_DIMMA# MA0_CS_L1 MB1_CLK_L0 MB_DATA27 MA_DATA27
DDR_CS0_DIMMA# AA24 AJ19 DDR_B_CLK2 DDR_B_D26 F31 F27 DDR_A_D26
10 DDR_CS0_DIMMA# MA0_CS_L0 MB0_CLK_H2 DDR_B_CLK2 11 MB_DATA26 MA_DATA26
AK19 DDR_B_CLK#2 DDR_B_D25 A29 C28 DDR_A_D25

To normal SODIMM socket


To reverse SODIMM socket
MB0_CLK_L2 DDR_B_CLK#2 11 MB_DATA25 MA_DATA25
DDR_CS3_DIMMB# AE29 A18 DDR_B_CLK1 DDR_B_D24 A28 E27 DDR_A_D24
11 DDR_CS3_DIMMB# DDR_B_CLK1 11
2

DDR_CS2_DIMMB# MB1_CS_L1 MB0_CLK_H1 DDR_B_CLK#1 DDR_B_D23 MB_DATA24 MA_DATA24 DDR_A_D23


11 DDR_CS2_DIMMB# AB31 MB1_CS_L0 MB0_CLK_L1 A19 DDR_B_CLK#1 11 A25 MB_DATA23 MA_DATA23 F25
DDR_CS1_DIMMB# AE30 U31 DDR_B_D22 A24 E25 DDR_A_D22
11 DDR_CS1_DIMMB# MB0_CS_L1 MB0_CLK_H0 MB_DATA22 MA_DATA22
DDR_CS0_DIMMB# AC31 U30 DDR_B_D21 C22 E23 DDR_A_D21
11 DDR_CS0_DIMMB# MB0_CS_L0 MB0_CLK_L0 MB_DATA21 MA_DATA21
DDR_B_D20 D21 D23 DDR_A_D20
DDR_CKE1_DIMMB DDR_B_ODT1 DDR_B_D19 MB_DATA20 MA_DATA20 DDR_A_D19
PLACE THEM CLOSE TO 11 DDR_CKE1_DIMMB M31 MB_CKE1 MB1_ODT0 AD31 DDR_B_ODT1 11 A26 MB_DATA19 MA_DATA19 E26
DDR_CKE0_DIMMB M29 AD29 DDR_B_ODT0 DDR_B_D18 B25 C26 DDR_A_D18
CPU WITHIN 1" 11 DDR_CKE0_DIMMB
DDR_CKE1_DIMMA MB_CKE0 MB0_ODT0 DDR_A_ODT1
DDR_B_ODT0 11
DDR_B_D17 MB_DATA18 MA_DATA18 DDR_A_D17
10 DDR_CKE1_DIMMA L27 MA_CKE1 MA1_ODT0 AC27 DDR_A_ODT1 10 B23 MB_DATA17 MA_DATA17 G23
3 DDR_CKE0_DIMMA DDR_A_ODT0 DDR_B_D16 DDR_A_D16 3
10 DDR_CKE0_DIMMA M25 MA_CKE0 MA0_ODT0 AC28 DDR_A_ODT0 10 A22 MB_DATA16 MA_DATA16 F23
DDR_B_D15 B21 E22 DDR_A_D15
10 DDR_A_MA[15..0] DDR_B_MA[15..0] 11 MB_DATA15 MA_DATA15
DDR_A_MA15 M27 N28 DDR_B_MA15 DDR_B_D14 A20 E21 DDR_A_D14
DDR_A_MA14 MA_ADD15 MB_ADD15 DDR_B_MA14 DDR_B_D13 MB_DATA14 MA_DATA14 DDR_A_D13
N24 MA_ADD14 MB_ADD14 N29 C16 MB_DATA13 MA_DATA13 F17
DDR_A_MA13 AC26 AE31 DDR_B_MA13 DDR_B_D12 D15 G17 DDR_A_D12
DDR_A_MA12 MA_ADD13 MB_ADD13 DDR_B_MA12 DDR_B_D11 MB_DATA12 MA_DATA12 DDR_A_D11
N26 MA_ADD12 MB_ADD12 N30 C21 MB_DATA11 MA_DATA11 G22
DDR_A_MA11 P25 P29 DDR_B_MA11 DDR_B_D10 A21 F21 DDR_A_D10
DDR_A_MA10 MA_ADD11 MB_ADD11 DDR_B_MA10 DDR_B_D9 MB_DATA10 MA_DATA10 DDR_A_D9
Y25 MA_ADD10 MB_ADD10 AA29 A17 MB_DATA9 MA_DATA9 G18
DDR_A_MA9 N27 P31 DDR_B_MA9 DDR_B_D8 A16 E17 DDR_A_D8
DDR_A_MA8 MA_ADD9 MB_ADD9 DDR_B_MA8 DDR_B_D7 MB_DATA8 MA_DATA8 DDR_A_D7
R24 MA_ADD8 MB_ADD8 R29 B15 MB_DATA7 MA_DATA7 G16
DDR_A_MA7 P27 R28 DDR_B_MA7 DDR_B_D6 A14 E15 DDR_A_D6
DDR_A_MA6 MA_ADD7 MB_ADD7 DDR_B_MA6 DDR_B_D5 MB_DATA6 MA_DATA6 DDR_A_D5
R25 MA_ADD6 MB_ADD6 R31 E13 MB_DATA5 MA_DATA5 G13
DDR_A_MA5 R26 R30 DDR_B_MA5 DDR_B_D4 F13 H13 DDR_A_D4
DDR_A_MA4 MA_ADD5 MB_ADD5 DDR_B_MA4 DDR_B_D3 MB_DATA4 MA_DATA4 DDR_A_D3
R27 MA_ADD4 MB_ADD4 T31 C15 MB_DATA3 MA_DATA3 H17
DDR_A_MA3 T25 T29 DDR_B_MA3 DDR_B_D2 A15 E16 DDR_A_D2
DDR_A_MA2 MA_ADD3 MB_ADD3 DDR_B_MA2 DDR_B_D1 MB_DATA2 MA_DATA2 DDR_A_D1
U25 MA_ADD2 MB_ADD2 U29 A13 MB_DATA1 MA_DATA1 E14
DDR_A_MA1 T27 U28 DDR_B_MA1 DDR_B_D0 D13 G14 DDR_A_D0
DDR_A_MA0 MA_ADD1 MB_ADD1 DDR_B_MA0 MB_DATA0 MA_DATA0
W24 MA_ADD0 MB_ADD0 AA30

DDR_A_BS#2 N25 N31 DDR_B_BS#2 K29 K25


10 DDR_A_BS#2 MA_BANK2 MB_BANK2 DDR_B_BS#2 11 MB_CHECK7 MA_CHECK7
DDR_A_BS#1 Y27 AA31 DDR_B_BS#1 K31 J26
10 DDR_A_BS#1 MA_BANK1 MB_BANK1 DDR_B_BS#1 11 MB_CHECK6 MA_CHECK6
DDR_A_BS#0 AA27 AA28 DDR_B_BS#0 G30 G28
10 DDR_A_BS#0 MA_BANK0 MB_BANK0 DDR_B_BS#0 11 MB_CHECK5 MA_CHECK5
G29 MB_CHECK4 MA_CHECK4 G27
DDR_A_RAS# AA26 AB29 DDR_B_RAS# L29 L24
10 DDR_A_RAS# MA_RAS_L MB_RAS_L DDR_B_RAS# 11 MB_CHECK3 MA_CHECK3
DDR_A_CAS# AB25 AC29 DDR_B_CAS# L28 K27
10 DDR_A_CAS# MA_CAS_L MB_CAS_L DDR_B_CAS# 11 MB_CHECK2 MA_CHECK2
DDR_A_WE# AB27 AC30 DDR_B_WE# H31 H29
10 DDR_A_WE# MA_WE_L MB_WE_L DDR_B_WE# 11 MB_CHECK1 MA_CHECK1
G31 MB_CHECK0 MA_CHECK0 H27
TYCO_1-1735315-4_940P
CONN@ 11 DDR_B_DM[7..0] J29 MB_DM8 MA_DM8 J25 DDR_A_DM[7..0] 10
DDR_B_DM7 AJ14 AF15 DDR_A_DM7
DDR_B_DM6 MB_DM7 MA_DM7 DDR_A_DM6
AH17 MB_DM6 MA_DM6 AF19
DDR_B_DM5 AJ23 AJ25 DDR_A_DM5
DDR_B_DM4 MB_DM5 MA_DM5 DDR_A_DM4
AK29 MB_DM4 MA_DM4 AH29
DDR_B_DM3 C30 B29 DDR_A_DM3
DDR_A_CLK2 DDR_B_CLK2 DDR_B_DM2 MB_DM3 MA_DM3 DDR_A_DM2
A23 MB_DM2 MA_DM2 E24
1 1 DDR_B_DM1 B17 E18 DDR_A_DM1
DDR_B_DM0 MB_DM1 MA_DM1 DDR_A_DM0
B13 MB_DM0 MA_DM0 H15
C66 C35
2 1.5P_0402_50V8C 1.5P_0402_50V8C J31 J28 2
DDR_A_CLK#2 2 DDR_B_CLK#2 2 MB_DQS_H8 MA_DQS_H8
J30 MB_DQS_L8 MA_DQS_L8 J27
DDR_B_DQS7 AK13 AD15 DDR_A_DQS7
11 DDR_B_DQS7 MB_DQS_H7 MA_DQS_H7 DDR_A_DQS7 10
DDR_A_CLK1 DDR_B_CLK1 DDR_B_DQS#7 AJ13 AE15 DDR_A_DQS#7
11 DDR_B_DQS#7 MB_DQS_L7 MA_DQS_L7 DDR_A_DQS#7 10
1 1 DDR_B_DQS6 AK17 AG18 DDR_A_DQS6
11 DDR_B_DQS6 MB_DQS_H6 MA_DQS_H6 DDR_A_DQS6 10
DDR_B_DQS#6 AJ17 AG19 DDR_A_DQS#6
11 DDR_B_DQS#6 MB_DQS_L6 MA_DQS_L6 DDR_A_DQS#6 10
C132 C173 DDR_B_DQS5 AK23 AG24 DDR_A_DQS5
1.5P_0402_50V8C 1.5P_0402_50V8C 11 DDR_B_DQS5 MB_DQS_H5 MA_DQS_H5 DDR_A_DQS5 10
DDR_B_DQS#5 AL23 AG25 DDR_A_DQS#5
2 2 11 DDR_B_DQS#5 MB_DQS_L5 MA_DQS_L5 DDR_A_DQS#5 10
DDR_A_CLK#1 DDR_B_CLK#1 DDR_B_DQS4 AL28 AG27 DDR_A_DQS4
11 DDR_B_DQS4 MB_DQS_H4 MA_DQS_H4 DDR_A_DQS4 10
DDR_B_DQS#4 AL29 AG28 DDR_A_DQS#4
11 DDR_B_DQS#4 MB_DQS_L4 MA_DQS_L4 DDR_A_DQS#4 10
DDR_B_DQS3 D31 D29 DDR_A_DQS3
11 DDR_B_DQS3 MB_DQS_H3 MA_DQS_H3 DDR_A_DQS3 10
PLACE CLOSE TO PROCESSOR PLACE CLOSE TO PROCESSOR DDR_B_DQS#3 C31 C29 DDR_A_DQS#3
11 DDR_B_DQS#3 MB_DQS_L3 MA_DQS_L3 DDR_A_DQS#3 10
DDR_B_DQS2 C24 C25 DDR_A_DQS2
WITHIN 1.2 INCH WITHIN 1.2 INCH 11 DDR_B_DQS2
DDR_B_DQS#2 MB_DQS_H2 MA_DQS_H2 DDR_A_DQS#2
DDR_A_DQS2 10
11 DDR_B_DQS#2 C23 MB_DQS_L2 MA_DQS_L2 D25 DDR_A_DQS#2 10
DDR_B_DQS1 D17 E19 DDR_A_DQS1
11 DDR_B_DQS1 MB_DQS_H1 MA_DQS_H1 DDR_A_DQS1 10
DDR_B_DQS#1 C17 F19 DDR_A_DQS#1
11 DDR_B_DQS#1 MB_DQS_L1 MA_DQS_L1 DDR_A_DQS#1 10
DDR_B_DQS0 C14 F15 DDR_A_DQS0
11 DDR_B_DQS0 MB_DQS_H0 MA_DQS_H0 DDR_A_DQS0 10
DDR_B_DQS#0 C13 G15 DDR_A_DQS#0
11 DDR_B_DQS#0 MB_DQS_L0 MA_DQS_L0 DDR_A_DQS#0 10
TYCO_1-1735315-4_940P
CONN@

+1.8V
A1 A26
1

R33

1K_0402_1% +0.9VREF_CPU
Athlon 64 S1g1
2

CPU_VREF_REF uPGA638
1 1 1 1 1 Top View
1

C32 C33 C34 C29 C28


1 R23 1
1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0402_6.3V4Z
1K_0402_1% 2 2 2 2 2
2

AF1
1000P_0402_50V7K 1000P_0402_50V7K

VDD_VREF_SUS_CPU Security Classification Compal Secret Data


LAYOUT:PLACE CLOSE TO CPU Issued Date 2005/10/11 Deciphered Date 2006/10/11 Title
AMD CPU DDRII MEMORY I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 7 of 50
A B C D E
5 4 3 2 1

ATHLON Control and Debug +1.8V

LAYOUT: ROUTE VDDA TRACE APPROX.

1
50 mils WIDE (USE 2x25 mil TRACES TO
EXIT BALL FIELD) AND 500 mils LONG.
R7 R78
+2.5VS 300_0402_5% 300_0402_5%
FCM2012C-800_0.25ohm/600mA_0805 W=50mils VDDA=300mA JCPU1D

2
1 1 2 L4 C10 VDDA2 THERMTRIP_L AK7 H_THERMTRIP_S#
C506 1 1 1 D10 VDDA1 PROCHOT_L AL7 CPU_PROCHOT#_1.8
+ C189 C187 R372 1 2 300_0402_5%
C136
12/22 Modify CPU_HT_RESET# C7 RESET_L
150U_D2_6.3VM 3300P_0402_50V7K R582 1 @ 2 300_0402_5% CPU_ALL_PWROK C9
2 2 2 2 +1.8VS PWROK
@ R583 1 2 300_0402_5% CPU_LDTSTOP# D8
D 4.7U_0805_10V4Z 0.22U_0603_16V7K @ LDTSTOP_L VID5 D
VID5 D2 VID5 48
Un-stuff R584 1 @ 2 0_0402_5% CPU_SIC_R AL6 D1 VID4
18 CPU_SIC SIC VID4 VID4 48
R585 1 2 0_0402_5% CPU_SID_R AK6 C1 VID3
18 CPU_SID SID VID3 VID3 48
@ E3 VID2
VID2 VID2 48
+1.2V_HT R36 1 2 44.2_0603_1% CPU_HTREF1 V8 E2 VID1
HT_REF1 VID1 VID1 48
R35 1 2 44.2_0603_1% CPU_HTREF0 V7 E1 VID0
HT_REF0 VID0 VID0 48
5:10 AL3 CPU_PRESENT#
+1.8VS +3VS +1.8V CPU_VCC_SENSE CPU_PRESENT_L
48 CPU_VCC_SENSE G2 VDD_FB_H
place them to CPU within 1" CPU_VSS_SENSE G1 F1 PSI#
48 CPU_VSS_SENSE VDD_FB_L PSI_L PSI# 48

1
R64 PAD TP2 AK11 H3
@ 4.7K_0402_5% C147 0.1U_0402_16V4Z PAD TP1 VDDIO_FB_H NC#1
AL11 VDDIO_FB_L NC#2 H4
1

1 2 NC#3 H20
R63 C501 1 2 CPU_CLKIN_SC_P A8 H21
17 CPUCLK CLKIN_H NC#4

5
300_0402_5% @ U5 @ CPU_CLKIN_SC_N B8
2
CLKIN_L

1
2 @ 3900P_0402_50V7K

P
B R70 1 CPU_ALL_PWROK R389 CPU_DBRDY CPU_DBREQ#
4 2 B6 A5
2

Y 0_0402_5% 169_0402_1% DBRDY DBREQ_L


18 CPU_PWRGD 1 A

G
CPU_TMS AL9 TMS
1

@ NC7SZ08P5X_NL_SC70-5 CPU_TCK AH10 AK10 CPU_TDO


3

2
R688 C502 1 CPU_TRST# TCK TDO
17 CPUCLK# 2 AJ10 TRST_L
680_0402_5% CPU_TDI AL10
R543 1 TDI
2 0_0402_5% 3900P_0402_50V7K R68
CPU_TEST25_H_BYPASSCLK_H A10 C11 CPU_TEST29_H_FBCLKOUT_P 1 2
2

CPU_TEST25_L_BYPASSCLK_L TEST25_H TEST29_H


B10 TEST25_L TEST29_L D11 CPU_TEST29_L_FBCLKOUT_N 80.6_0402_1% ROUTE AS 80 Ohm DIFFERENTIAL PAIR
+1.8VS CPU_TEST19_PLLTEST0 PLACE IT CLOSE TO CPU WITHIN 1"
+1.8V CPU_TEST18_PLLTEST1
F10
E9
TEST19 NC#5 AE7
AD19
5:4:5
C155 0.1U_0402_16V4Z TEST18 NC#6
AJ7 TEST13 NC#7 AE8
1

1 2 F6 TEST9 NC#8 AD18


R88 PAD TP5 D6 AK8 CPU_TEST24_SCANCLK1
TEST17 TEST24
5

300_0402_5% @ U8 @ PAD TP6 E7 AH8 TP7 PAD


@ PAD TP8 TEST16 TEST23 CPU_TEST22_SCANSHIFTEN
2 F8 AJ9
P

B R79 1 CPU_LDTSTOP# PAD TP9 TEST15 TEST22 CPU_TEST21_SCANEN


4 2 C5 AL8
2

Y 0_0402_5% CPU_TEST12_SCANSHIFTENB TEST14 TEST21 CPU_TEST20_SCANCLK2


14,18 LDT_STOP# 1 A AH9 TEST12 TEST20 AJ8
G
1

@ NC7SZ08P5X_NL_SC70-5 E5 J10
3

R689 TEST7 TEST28_H


AJ5 TEST6 TEST28_L H9
C 680_0402_5% CPU_THERMDC C
AG9 TEST5 TEST27 AK9
R544 1 2 0_0402_5% CPU_THERMDA AG8 AK5 CPU_TEST26_BURNIN#
TEST4 TEST26
10:10 AH7 G7
2

TEST3 TEST10
AJ6 TEST2 TEST8 D4
+1.8VS
L25 RSVD0 RSVD22 E20
L26 RSVD1 RSVD23 B19
L31 RSVD2
1

L30 RSVD3 RSVD24 AL4


R71 +1.8V AK4
300_0402_5% @ C282 0.1U_0402_16V4Z RSVD25
W26 RSVD4 RSVD26 AK3

MISC
1 2 W25 RSVD5
AE27 F2
2

RSVD6 RSVD27
5

@ U6 @ U24 F3
1 2 SB_PWROK_R 2 @
SCAN Connector V24
RSVD7 RSVD28
P

18,28,37 SB_PWROK B RSVD8


R82 0_0402_5% 4 R65 1 2 CPU_HT_RESET# AE28 G4
LDT_RST# Y 0_0402_5% RSVD9 RSVD29
18 LDT_RST# 1 A RSVD30 G3
G

+1.8V AD25 G5
RSVD10 RSVD31
1

@ NC7SZ08P5X_NL_SC70-5 AE24
3

R690 RSVD11
AE25 RSVD12
680_0402_5% JP38 AJ18 Y31
RSVD13 RSVD32
1 2 AJ20 RSVD14 RSVD33 Y30
R545 1 2 0_0402_5% 3 4 C18 AG31
2

RSVD15 RSVD34
5 6 C20 RSVD16 RSVD35 V31
CPU_TEST18_PLLTEST1 7 8 G24 W31
CPU_TEST19_PLLTEST0 RSVD17 RSVD36
9 10 G25 RSVD18 RSVD37 AF31
CPU_TEST21_SCANEN 11 12 H25
CPU_TEST22_SCANSHIFTEN RSVD19
13 14 V29 RSVD20
+1.8V CPU_TEST12_SCANSHIFTENB 15 16 W30
CPU_TEST24_SCANCLK1 RSVD21
17 18
CPU_TEST20_SCANCLK2 19 20 TYCO_1-1735315-4_940P
R361 1 220_0402_5%

R362 1 220_0402_5%

R363 1 220_0402_5%

R364 1 220_0402_5%

R365 1 220_0402_5%

21 22 CONN@
23 24
HDT Connector 25

ASP-68200-03
KEY
AMD AM2 Processor Socket

CONN@
HDT@

HDT@

HDT@

HDT@

HDT@

B +1.8V B
JP4
+1.8V
1 2 +3VS +3VALW +3VALW
3 4
2

5 6

1
CPU_DBREQ# +1.8V +3VALW
7 8

1
CPU_DBRDY R4
9 10
1

CPU_TCK R572 R2
11 12

1
CPU_TMS 220_0402_5% 1K_0402_5% @ 1K_0402_5%
CPU_TDI 13 14 HDT@ R3

2
CPU_TRST# 15 16 R5

2 2
17 18
2

CPU_TDO 300_0402_5% 10K_0402_5%


G
2

19 20

2
R683 0_0402_5% Q2

2
21 22 3V_LDT_RST# CPU_HT_RESET#_R CPU_HT_RESET# Q3 @ MMBT3904_SOT23
23 24 1 3 1 2
H_THERMTRIP_S# 3 1H_THERMTRIP# 3 1
D

26 MAINPWON 42,43,45
NOTE: HDT TERMINATION IS REQUIRED @ MMBT3904_SOT23
+1.8V
FOR REV. Ax SILICON ONLY. SAMTEC_ASP-68200-07 Q33 H_THERMTRIP# 18
CONN@ HDT@ 2N7002_SOT23

CPU_TEST26_BURNIN# R366 1 2 300_0402_5%


CPU_PRESENT# R369 1 2 1K_0402_5%
CPU_TEST25_H_BYPASSCLK_H R47 1 2 510_0402_5% +1.8V

1
+3VS
CPU_TEST20_SCANCLK2 R684 1 2 300_0402_5% @ R8
CPU_TEST24_SCANCLK1 R685 1 2 300_0402_5% @ +3VS
CPU_TEST12_SCANSHIFTENB R686 1 2 300_0402_5% @ 10K_0402_5%
CPU_TEST22_SCANSHIFTEN R687 1 2 300_0402_5% @

CPU_PH_G 2
1
1

C454

1
R374
0.1U_0402_16V4Z @ 10K_0402_5% CPU_TEST21_SCANEN R368 1 2 300_0402_5% R6
2 CPU_TEST25_L_BYPASSCLK_L R54 1 510_0402_5% 4.7K_0402_5%
1 2
C451 CPU_TEST19_PLLTEST0 R92 1 2 300_0402_5% @
2

U38 CPU_TEST18_PLLTEST1 R91 1 2 300_0402_5%

2
2
B
2200P_0402_50V7K CPU_THERMDA 2 1 Q4
A 2 D+ VDD1 A

E
CPU_THERMDC 3 6 CPU_PROCHOT#_1.8 3 1
D- ALERT# EC_THERM# 19,28

C
MMBT3904_SOT23
EC_SMB_CK2 8 4
28 EC_SMB_CK2 SCLK THERM#
EC_SMB_DA2 7 5
28 EC_SMB_DA2 SDATA GND

ADM1032ARMZ-2REEL_MSOP8
Security Classification Compal Secret Data
U4524 CLOSE CPU,
CPU_THERMDA&CPU_THERMDC PLACE Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title

CLOSE TO PROCESSOR WITHIN 1" INCH


AMD CPU CTRL & DEBUG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 8 of 50
5 4 3 2 1
5 4 3 2 1

CPU_CORE 820u 560u 330u 22u 10u .22u .01u 180p


HCW51 2 2 4 12 2 1 1
+CPU_CORE Moray 15 4 1
+CPU_CORE +CPU_CORE +1.8V
JCPU1E JCPU1F +CPU_CORE KAW60 2 3 15 3 1 1
A4 VDD1 VDD106 R10 R12 VDD107 VDDIO28 Y29
A6 VDD2 VDD105 R8 R14 VDD108 VDDIO27 Y28
AA8 VDD3 VDD104 R5 R16 VDD109 VDDIO26 Y26 1 1 1 1
AA10 R4 R18 Y24
AA12
AA14
AA16
VDD4
VDD5
VDD6
VDD103
VDD102
VDD101
P19
P17
P15
R20
T2
T3
VDD110
VDD111
VDD112
VDDIO25
VDDIO24
VDDIO23
V30
V28
V26
PVT + C505

330U_D2E_2.5VM_R9
+ C504

330U_D2E_2.5VM_R9
+ C453

330U_D2E_2.5VM_R9
+ C452 @

330U_D2E_2.5VM_R9
VDD7 VDD100 VDD113 VDDIO22 2 2 2 2
AA18 VDD8 VDD99 P13 T7 VDD114 VDDIO21 V25
AB7 P11 T9 T30
AB9
AB11
VDD9
VDD10
VDD98
VDD97 P9
P7
T11
T13
VDD115
VDD116
VDDIO20
VDDIO19 T28
T26
KAW60
D VDD11 VDD96 VDD117 VDDIO18 D
AC4 VDD12 VDD95 N18 T15 VDD118 VDDIO17 T24
AC5 VDD13 VDD94 N16 T17 VDD119 VDDIO16 P30
AC8 N14 T19 P28 +CPU_CORE +CPU_CORE
VDD14 VDD93 VDD120 VDDIO15
AC10 VDD15 VDD92 N12 T21 VDD121 VDDIO14 P26
AD2 N10 U8 P24 10U_0805_10V6M 10U_0805_10V6M 22U_0805_6.3V6M
VDD16 VDD91 VDD122 VDDIO13
AD3 VDD17 VDD90 N8 U10 VDD123 VDDIO12 M30 1 1 1 1 1 1 1 1 1
AD7 M19 U12 M28 C195 C17 C194 C193 C192 C97 C16
VDD18 VDD89 VDD124 VDDIO11 @ @ @ @ @ + C450 + C449
AD9 VDD19 VDD88 M17 U14 VDD125 VDDIO10 M26
AE10 M15 U16 M24 560U_25V_M_R10 560U_25V_M_R10
VDD20 VDD87 VDD126 VDDIO9 2 2 2 2 2 2 2
AF7 VDD21 VDD86 M13 U18 VDD127 VDDIO AF30
2 2

POWER2
AF9 M11 U20 AD30 10U_0805_10V6M 10U_0805_10V6M 22U_0805_6.3V6M 10U_0805_10V6M
VDD22 VDD85 VDD128 VDDIO8
AG4 VDD23 VDD84 M9 V9 VDD129 VDDIO7 AD28
POWER1

AG5 VDD24 VDD83 M7 V11 VDD130 VDDIO6 AD26


AG7 VDD25 VDD82 M3 V13 VDD131 VDDIO5 AC24
AH2 VDD26 VDD81 M2 V15 VDD132 VDDIO4 AB30
AH3 L18 V17 AB28
B3
VDD27
VDD28
VDD80
VDD79 L16 V19
VDD133
VDD134
VDDIO3
VDDIO2 AB26
+CPU_CORE
CPU SOCKET AM2 DECOUPLING SMD POLY CAP
B5 VDD29 VDD78 L14 V21 VDD135 VDDIO1 AB24
B7 Y19 W4 SF000001K00 S_A-P_CAP 560U 2.5V M 6.3X5.7 LESR10M H5.7
VDD30 VDD77 VDD136
C2 VDD31 VDD76 Y17 W5 VDD137 VDD184 Y23 SF000001J00 S_A-P_CAP 560U 2.5V M 6.3X5.7 LESR13M H5.7
C4 VDD32 VDD75 L12 W8 VDD138 VDD183 W22
C6 L10 W10 V23 +CPU_CORE
VDD33 VDD74 VDD139 VDD182
C8 VDD34 VDD73 L8 W12 VDD140 VDD181 U22
D3 VDD35 VDD72 L5 W14 VDD141 VDD180 T23
D5 VDD36 VDD71 L4 W16 VDD142 VDD179 R22 1 1 1 1 1 1 1 1 1
D7 K23 W18 P23 C73 C76 C86 @ C118 C109 C96 @ C89 C113 C124
VDD37 VDD70 VDD143 VDD178
D9 VDD38 VDD69 K21 W20 VDD144 VDD177 P21
E4 K19 Y2 N22 22U_0805_6.3V6M 22U_0805_6.3V6M 10U_0805_10V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 10U_0805_10V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VDD39 VDD68 VDD145 VDD176 2 2 2 2 2 2 2 2 2
E6 VDD40 VDD67 K17 Y3 VDD146 VDD175 N20
E8 VDD41 VDD66 K15 Y7 VDD147 VDD174 M23
E10 VDD42 VDD65 K13 Y9 VDD148 VDD173 M21
F5 VDD43 VDD64 K11 Y11 VDD149 VDD172 L22
F7 K9 Y13 L20
F9
F11
VDD44
VDD45
VDD63
VDD62 K7
J24
Y15
Y21
VDD150
VDD151
VDD171
VDD170 AF11
AE12 +CPU_CORE
KAW60
VDD46 VDD61 VDD152 VDD169
G6 VDD47 VDD60 J22 AA20 VDD153 VDD168 AD23
G8 VDD48 VDD59 J20 AA22 VDD154 VDD167 AD11
G10 VDD49 VDD58 J18 AB13 VDD155 VDD166 AC22 1 1 1 1 1 1 1 1 1 1 1
C C70 C120 C100 C91 C738 C739 C740 C741 C742 C743 C744 C
G12 VDD50 VDD57 J16 AB15 VDD156 VDD165 AC20
H7 VDD51 VDD56 J14 AB17 VDD157 VDD164 AC18
H11 J12 AB19 AC16 0.22U_0402_10V4Z 0.22U_0402_10V4Z 180P_0402_50V8J 0.01U_0402_16V7K 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 0.22U_0402_10V4Z
VDD52 VDD55 VDD158 VDD163 2 2 2 2 2 2 2 2 2 2 2
H23 VDD53 VDD54 J8 AB21 VDD159 VDD162 AC14
AB23 VDD160 VDD161 AC12
TYCO_1-1735315-4_940P
CONN@ TYCO_1-1735315-4_940P
AM2 Processor
Socket CONN@

JCPU1G
JCPU1H +1.8V KAW60 DECOUPLING BETWEEN PROCESSOR AND DIMMs
T22 VSS183 VSS184 U4
A3 H10 T20 U5
A7
VSS1
VSS2
VSS121
VSS120 H8 T18
VSS182
VSS181
VSS185
VSS186 U7 1
C82
1
C102
1
C72
1
C116
PLACE CLOSE TO PROCESSOR AS POSSIBLE
A9 VSS3 VSS119 G11 T16 VSS180 VSS187 U9
A11 VSS4 VSS118 G9 T14 VSS179 VSS188 U11
AA4 F30 T12 U13 22U_0805_6.3V6M 22U_0805_6.3V6M 0.22U_0402_10V4Z 0.22U_0402_10V4Z
VSS5 VSS117 VSS178 VSS189 2 2 2 2
AA5 VSS6 VSS116 F28 T10 VSS177 VSS190 U15 +1.8V 22u 10u 4.7u .22u .01u 180p .0047u
AA7 VSS7 VSS115 F26 T8 VSS176 VSS191 U17
AA9 VSS8 VSS114 F24 R23 VSS175 VSS192 U19 HCW51 2 4 6 2 2
AA11 VSS9 VSS113 F22 R21 VSS174 VSS193 U21
AA13 VSS10 VSS112 F20 R19 VSS173 VSS194 U23 Moray 2 2 5 1 3 2
AA15 VSS11 VSS111 F18 R17 VSS172 VSS195 V2
AA17 VSS12 VSS110 F16 R15 VSS171 VSS196 V3 KAW60 2 4 6 2 3
AA19 VSS13 VSS109 F14 R13 VSS170 VSS197 V10
AA21 F4 R11 V12 +1.8V
VSS14 VSS108 VSS169 VSS198
AA23 VSS15 VSS107 E11 R9 VSS168 VSS199 V14
AB2 VSS16 VSS106 D30 R7 VSS167 VSS200 V16
AB3 VSS17 VSS105 D28 P22 VSS166 VSS201 V18 1 1 1 1 1 1 1
AB8 D26 P20 V20 C472 C471 C479 C480 C104 C84 C129
VSS18 VSS104 VSS165 VSS202
AB10 VSS19 VSS103 D24 P18 VSS164 VSS203 V22
AB12 D22 P16 W9 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0402_10V4Z 0.22U_0402_10V4Z 0.22U_0402_10V4Z
VSS20 VSS102 VSS163 VSS204 2 2 2 2 2 2 2
AB14 VSS21 VSS101 D20 P14 VSS162 VSS205 W11
AB16 VSS22 VSS100 D18 P12 VSS161 VSS206 W13
AB18 VSS23 VSS99 D16 P10 VSS160 VSS207 W15
AB20 VSS24 VSS98 D14 P8 VSS159 VSS208 W17
AB22 VSS25 VSS97 C3 P3 VSS158 VSS209 W19 1 1 1 1 1 1
B C127 C128 C85 B
AC7 VSS26 VSS96 B30 P2 VSS157 VSS210 W21
GND1

AC9 B28 N23 W23 C68 C105 C745


VSS27 VSS95 VSS156 VSS211 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J
GND2

AC11 B26 N21 Y8 0.22U_0402_10V4Z 0.01U_0402_16V7K 0.01U_0402_16V7K


VSS28 VSS94 VSS155 VSS212 2 2 2 2 2 2
AC13 VSS29 VSS93 B24 N19 VSS154 VSS213 Y10
AC15 VSS30 VSS92 B22 N17 VSS153 VSS214 Y12
AC17 VSS31 VSS91 B20 Y18 VSS152 VSS215 W7
AC19 VSS32 VSS90 B18 K22 VSS151 VSS216 Y20
AC21 VSS33 VSS89 B16 K20 VSS150 VSS217 Y22
AC23 B14 K18 K24 +0.9V
VSS34 VSS88 VSS149 VSS218
AD8 VSS35 VSS87 B11 K16 VSS148 VSS219 K26
AD10 VSS36 VSS86 B9 K14 VSS147 VSS220 K28
AD12 VSS37 VSS85 B4 K12 VSS146 VSS221 K30 1 1 1 1 1 1 1 1
AD14 AL5 K10 L7 C188 C30 C36 C181 C184 C185 C27 C23
VSS38 VSS84 VSS145 VSS222
AD16 VSS39 VSS83 AK30 K8 VSS144 VSS223 L9
AD20 AK28 K3 L11 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0402_10V4Z 0.22U_0402_10V4Z 0.22U_0402_10V4Z 0.22U_0402_10V4Z
VSS40 VSS82 VSS143 VSS224 2 2 2 2 2 2 2 2
AD22 VSS41 VSS81 AK26 K2 VSS142 VSS225 L13
AD24 VSS42 VSS80 AK24 J23 VSS141 VSS226 L15
AE4 VSS43 VSS79 AK22 J21 VSS140 VSS227 L17
AE5 VSS44 VSS78 AK20 J19 VSS139 VSS228 L19
AE9 VSS45 VSS77 Y16 J17 VSS138 VSS229 L21 1 1 1 1 1 1 1 1
AE11 Y14 J15 L23 C39 C41 C178 C22
VSS46 VSS76 VSS137 VSS230 C179 C26 C175 C182
AF2 VSS47 VSS75 AK18 J13 VSS136 VSS231 M8
AF3 AK16 J11 M10 1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J
VSS48 VSS74 VSS135 VSS232 2 2 2 2 2 2 2 2
AF8 VSS49 VSS73 AK14 J9 VSS134 VSS233 M12
AF10 VSS50 VSS72 AK2 J7 VSS133 VSS234 M14
AF12
AF14
VSS51 VSS71 AH30
AH28
J5
J4
VSS132 VSS235 M16
M18
A1 A26
VSS52 VSS70 VSS131 VSS236
AF16 VSS53 VSS69 AH26 H30 VSS130 VSS237 M20
AF18 VSS54 VSS68 AH24 H28 VSS129 VSS238 M22 +0.9V 4.7u .22u .0047u 1000p 180p
AF20 VSS55 VSS67 AH22 H26 VSS128 VSS239 N4
AF22 VSS56 VSS66 AH20 H24 VSS127 VSS240 N5 HCW51 4 4 4 4
AF24 VSS57 VSS65 AH18 H22 VSS126 VSS241 N7
AF26 VSS58 VSS64 AH16 H18 VSS125 VSS242 N9 Athlon 64 S1g1 Moray 2 4 4 4 4
AF28 VSS59 VSS63 AH14 H16 VSS124 VSS243 N11
AG10 VSS61 VSS62 AG11 H14 VSS123 VSS244 N13 uPGA638 KAW60 4 4 4 4
H12 VSS122 VSS245 N15
TYCO_1-1735315-4_940P
TYCO_1-1735315-4_940P Top View
A CONN@ A
CONN@

AF1 PROCESSOR POWER AND GROUND


AM2 Processor Socket

Security Classification Compal Secret Data


Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
AMD CPU PWR & GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, July 29, 2008 Sheet 9 of 50
5 4 3 2 1
5 4 3 2 1

+1.8V +1.8V +DIMM_VREF +1.8V +1.8V

C640 C642 C644 C646 C648 C650

1
0.1U_0402_16V4Z
R398 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 0.01U_0402_16V7K10P_0402_25V8K 0.22U_0603_16V7K0.22U_0603_16V7K
JDIMM2 C507 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 VREF VSS 2 1 1
3 4 DDR_A_D4 1K_0402_1% C652
VSS DQ4

C503
4.7U_0805_10V4Z
DDR_A_D0 5 6 DDR_A_D5 0.22U_0603_16V7K

2
DDR_A_D1 DQ0 DQ5 2 2 2 2 2 2 2 2 2 2 2 2 2 2
7 DQ1 VSS 8
DDR_A_DM0 2 2 C639 C641 C643 C645 C647 C649 C651
9 VSS DM0 10
D DDR_A_DQS#0 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 0.01U_0402_16V7K10P_0402_25V8K 0.22U_0603_16V7K0.22U_0603_16V7K0.22U_0603_16V7K D
11 DQS0# VSS 12
DDR_A_DQS0 13 14 DDR_A_D6
DQS0 DQ6

1
15 16 DDR_A_D7 R397
DDR_A_D2 VSS DQ7
17 DQ2 VSS 18
DDR_A_D3 19 20 DDR_A_D12
DQ3 DQ12 DDR_A_D13 1K_0402_1%
21 VSS DQ13 22
DDR_A_D8 23 24

2
DDR_A_D9 DQ8 VSS DDR_A_DM1 +1.8V
25 DQ9 DM1 26
27 VSS VSS 28
DDR_A_DQS#1 29 30 DDR_A_CLK1
DQS1# CK0 DDR_A_CLK1 7
DDR_A_DQS1 31 32 DDR_A_CLK#1
DQS1 CK0# DDR_A_CLK#1 7
33 VSS VSS 34
DDR_A_D10 35 36 DDR_A_D14
DQ10 DQ14

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z
DDR_A_D11 37 38 DDR_A_D15 1
DQ11 DQ15
39 VSS VSS 40 1 1 1 1 1 1 1 1 1 1
+ C477
220U_D2_4VM_R15

C470

C62

C77

C98

C475

C55

C473

C57

C463

C58
41 VSS VSS 42
DDR_A_D16 DDR_A_D20 2 2 2 2 2 2 2 2 2 2 2
43 DQ16 DQ20 44
DDR_A_D17 45 46 DDR_A_D21 DDR_A_D[0..63]
DQ17 DQ21 7 DDR_A_D[0..63]
47 VSS VSS 48
DDR_A_DQS#2 49 50 DDR_A_DM[0..7]
DQS2# NC 7 DDR_A_DM[0..7]
DDR_A_DQS2 51 52 DDR_A_DM2
DQS2 DM2 DDR_A_DQS[0..7]
53 VSS VSS 54 7 DDR_A_DQS[0..7]
DDR_A_D18 55 56 DDR_A_D22
DDR_A_D19 DQ18 DQ22 DDR_A_D23 DDR_A_MA[0..15]
57 DQ19 DQ23 58 7 DDR_A_MA[0..15]
59 VSS VSS 60
DDR_A_D24 61 62 DDR_A_D28 DDR_A_DQS#[0..7]
DDR_A_D25 DQ24 DQ28 DDR_A_D29 7 DDR_A_DQS#[0..7] +0.9V
63 DQ25 DQ29 64
65 VSS VSS 66
C DDR_A_DM3 DDR_A_DQS#3 C
67 DM3 DQS3# 68
69 70 DDR_A_DQS3
NC DQS3

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D30 1
DDR_A_D27 DQ26 DQ30 DDR_A_D31 C636
75 DQ27 DQ31 76 1 1 1 1 1 1 1 1 1 1 1 1 1 1
77 78 +
DDR_CKE0_DIMMA VSS VSS DDR_CKE1_DIMMA
7 DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA 7
81 82 150U_D2_6.3VM
DDR_CS2_DIMMA# VDD VDD DDR_A_MA15 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
7 DDR_CS2_DIMMA# 83 NC NC/A15 84

C63

C67

C71

C80

C114

C107

C95

C69

C74

C88

C45

C65

C101

C51
DDR_A_BS#2 85 86 DDR_A_MA14
7 DDR_A_BS#2 BA2 NC/A14
87 VDD VDD 88
DDR_A_MA12 89 90 DDR_A_MA11
DDR_A_MA9 A12 A11 DDR_A_MA7
91 A9 A7 92
DDR_A_MA8 93 94 DDR_A_MA6 Layout Note:
A8 A6
95 96
DDR_A_MA5 97
VDD VDD
98 DDR_A_MA4 Place one cap close to every 2 pullup
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100 resistors terminated to +0.9V
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1 +0.9V
A10/AP BA1 DDR_A_BS#1 7
DDR_A_BS#0 107 108 DDR_A_RAS#
7 DDR_A_BS#0 BA0 RAS# DDR_A_RAS# 7
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
7 DDR_A_WE# WE# S0# DDR_CS0_DIMMA# 7
111 112 DDR_CKE0_DIMMA 1 4
DDR_A_CAS# VDD VDD DDR_A_ODT0 DDR_CS2_DIMMA#
7 DDR_A_CAS# 113 CAS# ODT0 114 DDR_A_ODT0 7 2 3
DDR_CS1_DIMMA# 115 116 DDR_A_MA13 RP28 47_0404_4P2R_5%
7 DDR_CS1_DIMMA# NC/S1# NC/A13
117 118 DDR_A_BS#2 1 4 1 4 DDR_A_MA15
DDR_A_ODT1 VDD VDD DDR_CS3_DIMMA# DDR_A_MA12 DDR_CKE1_DIMMA
7 DDR_A_ODT1 119 NC/ODT1 NC 120 DDR_CS3_DIMMA# 7 2 3 2 3
121 122 RP25 47_0404_4P2R_5% RP22 47_0404_4P2R_5%
DDR_A_D32 VSS VSS DDR_A_D36 DDR_A_MA9 DDR_A_MA7
123 DQ32 DQ36 124 1 4 1 4
DDR_A_D33 125 126 DDR_A_D37 DDR_A_MA8 2 3 2 3 DDR_A_MA14
B DQ33 DQ37 RP21 47_0404_4P2R_5% RP17 47_0404_4P2R_5% B
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4 DDR_A_MA5 1 4 1 4 DDR_A_MA6
DDR_A_DQS4 DQS4# DM4 DDR_A_MA3 DDR_A_MA11
131 DQS4 VSS 132 2 3 2 3
133 134 DDR_A_D38 RP18 47_0404_4P2R_5% RP14 47_0404_4P2R_5%
DDR_A_D34 VSS DQ38 DDR_A_D39 DDR_A_MA1 DDR_A_MA2
135 DQ34 DQ39 136 1 4 1 4
DDR_A_D35 137 138 DDR_A_MA10 2 3 2 3 DDR_A_MA4
DQ35 VSS DDR_A_D44 RP13 47_0404_4P2R_5% RP10 47_0404_4P2R_5%
139 VSS DQ44 140
DDR_A_D40 141 142 DDR_A_D45 DDR_A_BS#0 1 4 1 4 DDR_A_BS#1
DDR_A_D41 DQ40 DQ45 DDR_A_WE# DDR_A_MA0
143 DQ41 VSS 144 2 3 2 3
145 146 DDR_A_DQS#5 RP9 47_0404_4P2R_5% RP6 47_0404_4P2R_5%
DDR_A_DM5 VSS DQS5# DDR_A_DQS5 DDR_A_CAS# DDR_CS0_DIMMA#
147 DM5 DQS5 148 1 4 1 4
149 150 DDR_CS1_DIMMA# 2 3 2 3 DDR_A_RAS#
DDR_A_D42 VSS VSS DDR_A_D46 RP5 47_0404_4P2R_5% RP2 47_0404_4P2R_5%
151 DQ42 DQ46 152
DDR_A_D43 153 154 DDR_A_D47 DDR_A_ODT1 R32 1 2 47_0402_1% 1 4 DDR_A_MA13
DQ43 DQ47 DDR_CS3_DIMMA# R28
155 VSS VSS 156 1 2 47_0402_1% 2 3 DDR_A_ODT0
DDR_A_D48 157 158 DDR_A_D52 RP1 47_0404_4P2R_5%
DDR_A_D49 DQ48 DQ52 DDR_A_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 DDR_A_CLK2 +0.9V +1.8V
NC,TEST CK1 DDR_A_CLK2 7
165 166 DDR_A_CLK#2
VSS CK1# DDR_A_CLK#2 7

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
171 VSS VSS 172 1 1 1 1 1 1 1 1 1
DDR_A_D50 173 174 DDR_A_D54
DDR_A_D51 DQ50 DQ54 DDR_A_D55
175 DQ51 DQ55 176
177 VSS VSS 178
DDR_A_D56 DDR_A_D60 2 2 2 2 2 2 2 2 2
179 DQ56 DQ60 180

C616

C617

C618

C619

C56

C620

C621

C622

C623
DDR_A_D57 181 182 DDR_A_D61
DQ57 DQ61
183 VSS VSS 184
DDR_A_DM7 185 186 DDR_A_DQS#7
A DM7 DQS7# DDR_A_DQS7 A
187 VSS DQS7 188
DDR_A_D58 189 190 Layout Note:
DDR_A_D59 DQ58 VSS DDR_A_D62
191 192
193
DQ59 DQ62
194 DDR_A_D63 Place one 0.1uF cap close to every 2 pullup
SB_CK_SDAT VSS DQ63
11,17,19,31 SB_CK_SDAT 195 SDA VSS 196 resistors terminated to +0.9V
SB_CK_SCLK 197 198 R12 1 2 10K_0402_5%
11,17,19,31 SB_CK_SCLK SCL SAO
199 200 R10 1 2 10K_0402_5%
+3VS VDDSPD SA1 Security Classification Compal Secret Data
1
C448 2005/10/11 2006/10/11 Title
P-TWO_A5692C-A0G16
Issued Date Deciphered Date
DDR2 SO-DIMM I
0.1U_0402_16V4Z CONN@
2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 10 of 50
5 4 3 2 1
5 4 3 2 1

DDR_B_D[0..63]
+1.8V +1.8V +DIMM_VREF 7 DDR_B_D[0..63]
DDR_B_DM[0..7]
7 DDR_B_DM[0..7]
DDR_B_DQS[0..7]
7 DDR_B_DQS[0..7]

0.1U_0402_16V4Z
4.7U_0805_10V4Z

C202

C198
JDIMM1 DDR_B_MA[0..15]
7 DDR_B_MA[0..15]
1 VREF VSS 2 1 1
3 4 DDR_B_D4 DDR_B_DQS#[0..7]
DDR_B_D0 VSS DQ4 DDR_B_D5 7 DDR_B_DQS#[0..7]
5 DQ0 DQ5 6
DDR_B_D1 7 8
DQ1 VSS DDR_B_DM0 2 2
9 VSS DM0 10 <BOM Structure>
D DDR_B_DQS#0 D
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D7 +1.8V
15 VSS DQ7 16
DDR_B_D2 17 18
DDR_B_D3 DQ2 VSS DDR_B_D12
19 DQ3 DQ12 20
21 22 DDR_B_D13
DDR_B_D8 VSS DQ13
23 DQ8 VSS 24
DDR_B_D9 25 26 DDR_B_DM1
DQ9 DM1

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z
27 VSS VSS 28 1
DDR_B_DQS#1 29 30 DDR_B_CLK1 1 1 1 1 1 1 1 1 1 1
DQS1# CK0 DDR_B_CLK1 7 + C633
DDR_B_DQS1 31 32 DDR_B_CLK#1
DQS1 CK0# DDR_B_CLK#1 7
33 34 220U_D2_4VM_R15
VSS VSS

C52

C99

C103

C59

C64

C53

C81

C78

C61

C125
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15 2 2 2 2 2 2 2 2 2 2 2
37 DQ11 DQ15 38
39 VSS VSS 40

41 VSS VSS 42
DDR_B_D16 43 44 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
45 DQ17 DQ21 46
47 VSS VSS 48
DDR_B_DQS#2 49 50
DDR_B_DQS2 DQS2# NC DDR_B_DM2
51 DQS2 DM2 52
53 54 +0.9V
DDR_B_D18 VSS VSS DDR_B_D22
55 DQ18 DQ22 56
DDR_B_D19 57 58 DDR_B_D23
DQ19 DQ23
59 VSS VSS 60

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_B_D24 61 62 DDR_B_D28
DDR_B_D25 DQ24 DQ28 DDR_B_D29
63 DQ25 DQ29 64
65 VSS VSS 66 1 1 1 1 1 1 1 1 1 1 1 1
C DDR_B_DM3 DDR_B_DQS#3 C
67 DM3 DQS3# 68
69 70 DDR_B_DQS3
NC DQS3
71 VSS VSS 72
DDR_B_D26 DDR_B_D30 2 2 2 2 2 2 2 2 2 2 2 2
73 DQ26 DQ30 74

C4

C7

C10

C13

C18

C8

C11

C14

C19

C9

C15

C20
DDR_B_D27 75 76 DDR_B_D31
DQ27 DQ31
77 VSS VSS 78
DDR_CKE0_DIMMB 79 80 DDR_CKE1_DIMMB
7 DDR_CKE0_DIMMB CKE0 NC/CKE1 DDR_CKE1_DIMMB 7
81 VDD VDD 82
DDR_CS2_DIMMB# 83 84 DDR_B_MA15 Layout Note:
7 DDR_CS2_DIMMB# NC NC/A15
DDR_B_BS#2 85 86 DDR_B_MA14
7 DDR_B_BS#2 BA2 NC/A14 Place one cap close to every 2 pullup
87 VDD VDD 88
DDR_B_MA12 89 90 DDR_B_MA11 resistors terminated to +0.9V
DDR_B_MA9 A12 A11 DDR_B_MA7
91 A9 A7 92
DDR_B_MA8 93 94 DDR_B_MA6
A8 A6
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4 +0.9V
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
A1 A0 DDR_CS2_DIMMB#
103 VDD VDD 104 1 4
DDR_B_MA10 105 106 DDR_B_BS#1 DDR_CKE0_DIMMB 2 3
A10/AP BA1 DDR_B_BS#1 7
DDR_B_BS#0 107 108 DDR_B_RAS# RP27 47_0404_4P2R_5%
7 DDR_B_BS#0 BA0 RAS# DDR_B_RAS# 7
DDR_B_WE# 109 110 DDR_CS0_DIMMB# DDR_B_MA12 1 4 1 4 DDR_CKE1_DIMMB
7 DDR_B_WE# WE# S0# DDR_CS0_DIMMB# 7
111 112 DDR_B_BS#2 2 3 2 3 DDR_B_MA15
DDR_B_CAS# VDD VDD DDR_B_ODT0 RP24 47_0404_4P2R_5% RP26 47_0404_4P2R_5%
7 DDR_B_CAS# 113 CAS# ODT0 114 DDR_B_ODT0 7
DDR_CS1_DIMMB# 115 116 DDR_B_MA13 DDR_B_MA8 1 4 1 4 DDR_B_MA14
7 DDR_CS1_DIMMB# NC/S1# NC/A13
117 118 DDR_B_MA9 2 3 2 3 DDR_B_MA11
DDR_B_ODT1 VDD VDD DDR_CS3_DIMMB# RP19 47_0404_4P2R_5% RP23 47_0404_4P2R_5%
7 DDR_B_ODT1 119 NC/ODT1 NC 120 DDR_CS3_DIMMB# 7
121 122 DDR_B_MA3 1 4 1 4 DDR_B_MA7
DDR_B_D32 VSS VSS DDR_B_D36 DDR_B_MA5 DDR_B_MA6
123 DQ32 DQ36 124 2 3 2 3
DDR_B_D33 125 126 DDR_B_D37 RP15 47_0404_4P2R_5% RP20 47_0404_4P2R_5%
B DQ33 DQ37 DDR_B_MA10 DDR_B_MA4 B
127 VSS VSS 128 1 4 1 4
DDR_B_DQS#4 129 130 DDR_B_DM4 DDR_B_MA1 2 3 2 3 DDR_B_MA2
DDR_B_DQS4 DQS4# DM4 RP11 47_0404_4P2R_5% RP16 47_0404_4P2R_5%
131 DQS4 VSS 132
133 134 DDR_B_D38 DDR_B_WE# 1 4 1 4 DDR_B_MA0
DDR_B_D34 VSS DQ38 DDR_B_D39 DDR_B_BS#0 DDR_B_BS#1
135 DQ34 DQ39 136 2 3 2 3
DDR_B_D35 137 138 RP8 47_0404_4P2R_5% RP12 47_0404_4P2R_5%
DQ35 VSS DDR_B_D44 DDR_CS0_DIMMB# DDR_B_CAS#
139 VSS DQ44 140 1 4 1 4
DDR_B_D40 141 142 DDR_B_D45 DDR_B_RAS# 2 3 2 3 DDR_CS1_DIMMB#
DDR_B_D41 DQ40 DQ45 RP7 47_0404_4P2R_5% RP3 47_0404_4P2R_5%
143 DQ41 VSS 144
145 146 DDR_B_DQS#5 DDR_B_ODT1 R29 1 2 47_0402_1% 1 4 DDR_B_ODT0
DDR_B_DM5 VSS DQS5# DDR_B_DQS5 DDR_CS3_DIMMB# R30
147 DM5 DQS5 148 1 2 47_0402_1% 2 3 DDR_B_MA13
149 150 RP4 47_0404_4P2R_5%
DDR_B_D42 VSS VSS DDR_B_D46
151 DQ42 DQ46 152
DDR_B_D43 153 154 DDR_B_D47
DQ43 DQ47
155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
159 DQ49 DQ53 160
161 162 +0.9V +1.8V
VSS VSS DDR_B_CLK2
163 NC,TEST CK1 164 DDR_B_CLK2 7

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
165 166 DDR_B_CLK#2
VSS CK1# DDR_B_CLK#2 7
DDR_B_DQS#6 167 168
DDR_B_DQS6 DQS6# VSS DDR_B_DM6
169 DQS6 DM6 170 1 1 1 1 1 1 1 1 1 1 1
171 VSS VSS 172
DDR_B_D50 173 174 DDR_B_D54
DDR_B_D51 DQ50 DQ54 DDR_B_D55
175 DQ51 DQ55 176
2 2 2 2 2 2 2 2 2 2 2
177 VSS VSS 178

C624

C625

C626

C627

C12

C5

C6

C628

C629

C630

C631
DDR_B_D56 179 180 DDR_B_D60
DDR_B_D57 DQ56 DQ60 DDR_B_D61
181 DQ57 DQ61 182
183 VSS VSS 184
DDR_B_DM7 185 186 DDR_B_DQS#7
A DM7 DQS7# DDR_B_DQS7 A
187 VSS DQS7 188 Layout Note:
DDR_B_D58 189 190
DDR_B_D59 191
DQ58 VSS
192 DDR_B_D62 Place one 0.1uF cap close to every 2 pullup
DQ59 DQ62 DDR_B_D63
193 VSS DQ63 194 resistors terminated to +0.9V
SB_CK_SDAT 195 196
10,17,19,31 SB_CK_SDAT SDA VSS
SB_CK_SCLK 197 198 R11 1 2 10K_0402_5% +3VS
10,17,19,31 SB_CK_SCLK SCL SAO
199 200 R9 1 2 10K_0402_5%
+3VS VDDSPD SA1 Security Classification Compal Secret Data
1
C21 2005/10/11 2006/10/11 Title
P-TWO_A5652C-A0G16
Issued Date Deciphered Date
DDR2 SO-DIMM II
0.1U_0402_16V4Z CONN@
2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 11 of 50
5 4 3 2 1
5 4 3 2 1

U39A

D H_CADOP15 R19 P21 H_CADIP15 D


6 H_CADOP15 HT_RXCAD15P HT_TXCAD15P H_CADIP15 6
H_CADON15 R18 PART 1 OF 5 P22 H_CADIN15
6 H_CADON15 HT_RXCAD15N HT_TXCAD15N H_CADIN15 6
H_CADOP14 R21 P18 H_CADIP14
6 H_CADOP14 HT_RXCAD14P HT_TXCAD14P H_CADIP14 6
H_CADON14 R22 P19 H_CADIN14
6 H_CADON14 HT_RXCAD14N HT_TXCAD14N H_CADIN14 6
H_CADOP13 U22 M22 H_CADIP13
6 H_CADOP13 HT_RXCAD13P HT_TXCAD13P H_CADIP13 6
H_CADON13 U21 M21 H_CADIN13
6 H_CADON13 HT_RXCAD13N HT_TXCAD13N H_CADIN13 6
H_CADOP12 U18 M18 H_CADIP12
6 H_CADOP12 HT_RXCAD12P HT_TXCAD12P H_CADIP12 6
H_CADON12 U19 M19 H_CADIN12
6 H_CADON12 HT_RXCAD12N HT_TXCAD12N H_CADIN12 6
H_CADOP11 W19 L18 H_CADIP11
6 H_CADOP11 HT_RXCAD11P HT_TXCAD11P H_CADIP11 6
H_CADON11 W20 L19 H_CADIN11
6 H_CADON11 HT_RXCAD11N HT_TXCAD11N H_CADIN11 6
H_CADOP10 AC21 G22 H_CADIP10
6 H_CADOP10 HT_RXCAD10P HT_TXCAD10P H_CADIP10 6
H_CADON10 AB22 G21 H_CADIN10
6 H_CADON10 HT_RXCAD10N HT_TXCAD10N H_CADIN10 6
H_CADOP9 AB20 J20 H_CADIP9
6 H_CADOP9 HT_RXCAD9P HT_TXCAD9P H_CADIP9 6
H_CADON9 AA20 J21 H_CADIN9
6 H_CADON9 HT_RXCAD9N HT_TXCAD9N H_CADIN9 6
H_CADOP8 AA19 F21 H_CADIP8
6 H_CADOP8 HT_RXCAD8P HT_TXCAD8P H_CADIP8 6
H_CADON8 Y19 F22 H_CADIN8
6 H_CADON8 HT_RXCAD8N HT_TXCAD8N H_CADIN8 6
H_CADOP7 T24 N24 H_CADIP7
6 H_CADOP7 HT_RXCAD7P HT_TXCAD7P H_CADIP7 6
H_CADON7 R25 N25 H_CADIN7
6 H_CADON7 HT_RXCAD7N HT_TXCAD7N H_CADIN7 6
H_CADOP6 U25 L25 H_CADIP6
6 H_CADOP6 HT_RXCAD6P HT_TXCAD6P H_CADIP6 6
H_CADON6 U24 M24 H_CADIN6
6 H_CADON6 HT_RXCAD6N HT_TXCAD6N H_CADIN6 6
H_CADOP5 V23 K25 H_CADIP5
6 H_CADOP5 HT_RXCAD5P HT_TXCAD5P H_CADIP5 6
H_CADON5 U23 K24 H_CADIN5
6 H_CADON5 HT_RXCAD5N HT_TXCAD5N H_CADIN5 6
H_CADOP4 V24 J23 H_CADIP4
6 H_CADOP4 HT_RXCAD4P HT_TXCAD4P H_CADIP4 6
H_CADON4 V25 K23 H_CADIN4
6 H_CADON4 HT_RXCAD4N HT_TXCAD4N H_CADIN4 6
H_CADOP3 AA25 G25 H_CADIP3
6 H_CADOP3 HT_RXCAD3P HT_TXCAD3P H_CADIP3 6
H_CADON3 AA24 H24 H_CADIN3
6 H_CADON3 HT_RXCAD3N HT_TXCAD3N H_CADIN3 6
H_CADOP2 AB23 F25 H_CADIP2

HYPER TRANSPORT I/F


6 H_CADOP2 HT_RXCAD2P HT_TXCAD2P H_CADIP2 6
H_CADON2 AA23 F24 H_CADIN2
6 H_CADON2 HT_RXCAD2N HT_TXCAD2N H_CADIN2 6
H_CADOP1 AB24 E23 H_CADIP1
C 6 H_CADOP1 HT_RXCAD1P HT_TXCAD1P H_CADIP1 6 C
H_CADON1 AB25 F23 H_CADIN1
6 H_CADON1 HT_RXCAD1N HT_TXCAD1N H_CADIN1 6
H_CADOP0 AC24 E24 H_CADIP0
6 H_CADOP0 HT_RXCAD0P HT_TXCAD0P H_CADIP0 6
H_CADON0 AC25 E25 H_CADIN0
6 H_CADON0 HT_RXCAD0N HT_TXCAD0N H_CADIN0 6
H_CLKOP1 W21 L21 H_CLKIP1
6 H_CLKOP1 HT_RXCLK1P HT_TXCLK1P H_CLKIP1 6
H_CLKON1 W22 L22 H_CLKIN1
6 H_CLKON1 HT_RXCLK1N HT_TXCLK1N H_CLKIN1 6
H_CLKOP0 Y24 J24 H_CLKIP0
6 H_CLKOP0 HT_RXCLK0P HT_TXCLK0P H_CLKIP0 6
H_CLKON0 W25 J25 H_CLKIN0
6 H_CLKON0 HT_RXCLK0N HT_TXCLK0N H_CLKIN0 6
H_CTLOP0 P24 N23 H_CTLIP0
6 H_CTLOP0 HT_RXCTLP HT_TXCTLP H_CTLIP0 6
H_CTLON0 P25 P23 H_CTLIN0
6 H_CTLON0 HT_RXCTLN HT_TXCTLN H_CTLIN0 6
R382 1 2 49.9_0402_1% HT_RXCALP A24 C25 HT_TXCALP 1 R379 2
R380 1 HT_RXCALN HT_RXCALP HT_TXCALP HT_TXCALN
VDDHT_PKG 2 49.9_0402_1% C24 HT_RXCALN HT_TXCALN D24 100_0402_1%

216MQA6AVA11FG_FCBGA465_RS690M

RS690MC : SA00001I480 / S IC 216LQA6AVA12FG RS690MC BGA 465P 0FA

B B

A A

Security Classification Compal Secret Data


Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
RS690MC-HT LINK0 I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 12 of 50
5 4 3 2 1
5 4 3 2 1

U39B

G5 GFX_RX0P PART 2 OF 5 GFX_TX0P J1


G4 GFX_RX0N GFX_TX0N H2
J8 GFX_RX1P GFX_TX1P K2
J7 GFX_RX1N GFX_TX1N K1
J4 GFX_RX2P GFX_TX2P K3
J5 GFX_RX2N GFX_TX2N L3
L8 GFX_RX3P GFX_TX3P L1
L7 GFX_RX3N GFX_TX3N L2
L4 GFX_RX4P GFX_TX4P N2
L5 GFX_RX4N GFX_TX4N N1
D M8 P2 D
GFX_RX5P GFX_TX5P
M7 GFX_RX5N GFX_TX5N P1
M4 GFX_RX6P GFX_TX6P P3
M5 GFX_RX6N GFX_TX6N R3
P8 GFX_RX7P GFX_TX7P R1

PCIE GFX I/F


P7 GFX_RX7N GFX_TX7N R2
P4 GFX_RX8P GFX_TX8P T2
P5 GFX_RX8N GFX_TX8N U1
R4 GFX_RX9P GFX_TX9P V2
R5 GFX_RX9N GFX_TX9N V1
R7 GFX_RX10P GFX_TX10P V3
R8 GFX_RX10N GFX_TX10N W3
U4 GFX_RX11P GFX_TX11P W1
U5 GFX_RX11N GFX_TX11N W2
W4 GFX_RX12P GFX_TX12P Y2
W5 GFX_RX12N GFX_TX12N AA1
Y4 GFX_RX13P GFX_TX13P AA2
Y5 GFX_RX13N GFX_TX13N AB2
V9 GFX_RX14P GFX_TX14P AB1
W9 GFX_RX14N GFX_TX14N AC1
AB7 GFX_RX15P GFX_TX15P AE3
AB6 GFX_RX15N GFX_TX15N AE4

PCIE_MRX_PTX_P0 Y7 AD4 PCIE_MTX_PRX_P0 C457 1 2 0.1U_0402_10V6K PCIE_MTX_C_PRX_P0


WLAN 31 PCIE_MRX_PTX_P0
PCIE_MRX_PTX_N0 AA7
GPP_RX2P GPP_TX2P
AE5 PCIE_MTX_PRX_N0 C458 1 2 0.1U_0402_10V6K PCIE_MTX_C_PRX_N0
PCIE_MTX_C_PRX_P0 31
31 PCIE_MRX_PTX_N0 GPP_RX2N GPP_TX2N PCIE_MTX_C_PRX_N0 31 WLAN
PCIE_MRX_C_PTX_P1 AB9 AD5 PCIE_MTX_PRX_P1 C466 1 2 0.1U_0402_10V6K PCIE_MTX_C_PRX_P1
LAN 26 PCIE_MRX_C_PTX_P1
PCIE_MRX_C_PTX_N1 AA9
GPP_RX3P
PCIE I/F GPP
GPP_TX3P
AD6 PCIE_MTX_PRX_N1 C467 1 2 0.1U_0402_10V6K PCIE_MTX_C_PRX_N1
PCIE_MTX_C_PRX_P1 26
26 PCIE_MRX_C_PTX_N1 GPP_RX3N GPP_TX3N PCIE_MTX_C_PRX_N1 26 LAN
A_MRX_STX_P2 W11 AD8 A_MTX_SRX_P2 C659 1 2 0.1U_0402_10V6K A_MTX_C_SRX_P2
C 18 A_MRX_STX_P2 GPP_RX0P(SB_RX2P) GPP_TX0P(SB_TX2P) A_MTX_C_SRX_P2 18 C
A_MRX_STX_N2 W12 AE8 A_MTX_SRX_N2 C660 1 2 0.1U_0402_10V6K A_MTX_C_SRX_N2
18 A_MRX_STX_N2 GPP_RX0N(SB_RX2N) GPP_TX0N(SB_TX2N) A_MTX_C_SRX_N2 18

A_MRX_STX_P3 AA11 AD7 A_MTX_SRX_P3 C661 1 2 0.1U_0402_10V6K A_MTX_C_SRX_P3


18 A_MRX_STX_P3 GPP_RX1P(SB_RX3P) GPP_TX1P(SB_TX3P) A_MTX_C_SRX_P3 18
A_MRX_STX_N3 AB11 AE7 A_MTX_SRX_N3 C662 1 2 0.1U_0402_10V6K A_MTX_C_SRX_N3
18 A_MRX_STX_N3 GPP_RX1N(SB_RX3N) GPP_TX1N(SB_TX3N) A_MTX_C_SRX_N3 18

A_MRX_STX_P0 W14 AE9 A_MTX_SRX_P0 C465 1 2 0.1U_0402_10V6K A_MTX_C_SRX_P0


18 A_MRX_STX_P0 SB_RX0P SB_TX0P A_MTX_C_SRX_P0 18
A_MRX_STX_N0 W15 AD10 A_MTX_SRX_N0 C464 1 2 0.1U_0402_10V6K A_MTX_C_SRX_N0
18 A_MRX_STX_N0 SB_RX0N SB_TX0N A_MTX_C_SRX_N0 18
A_MRX_STX_P1 AB12 PCIE I/F SB AC8 A_MTX_SRX_P1 C468 1 2 0.1U_0402_10V6K A_MTX_C_SRX_P1
18 A_MRX_STX_P1 SB_RX1P SB_TX1P A_MTX_C_SRX_P1 18
A_MRX_STX_N1 AA12 AD9 A_MTX_SRX_N1 C469 1 2 0.1U_0402_10V6K A_MTX_C_SRX_N1
18 A_MRX_STX_N1 SB_RX1N SB_TX1N A_MTX_C_SRX_N1 18
AA14 AD11 R375 1 2 562_0402_1% VDDA12_PKG2
PCE_ISET(NC) PCE_PCAL(PCE_CALRP) R376 1 2K_0402_1%
AB14 PCE_TXISET(NC) PCE_NCAL(PCE_CALRN) AE11 2

R375: 150 Ohm FOR RS485


216MQA6AVA11FG_FCBGA465_RS690M
562 Ohm FOR RS690
R376: 82.5 Ohm FOR RS485
2KOhm FOR RS690

RS690MC : SA00001I480 / S IC 216LQA6AVA12FG RS690MC BGA 465P 0FA

B B

A A

Security Classification Compal Secret Data


Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
RS690MC-PCIE LINK I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 13 of 50
5 4 3 2 1
5 4 3 2 1

+3VS

R575
4.7K_0402_5%

1
R540 1 2 0_0805_5% +3VS AVDD
L43
1 2 AVDD=100mA R576
MBK2012121YZF_0.2ohm/800mA_0805
1 1 4.7K_0402_5%
+1.8VS C483 C487

2
AVDDQ
D L52 AVSSQ_GND 1U_0603_10V4Z 4.7U_0805_10V4Z D
2.2U_0805_10V6K 2 2
1 2
MBK2012121YZF_0.2ohm/800mA_0805 1 1 1
C495 C489 C484
10U_0805_10V4Z

@ U39C
1U_0603_10V4Z
2 2 2 +1.8VS LVDS_TXLP0
B22 AVDD1 PART 3 OF 5 TXOUT_L0P B14 LVDS_TXLP0 25
L44 MBK2012121YZF_0.2ohm/800mA_0805 C22 B15 LVDS_TXLN0
AVDD2 TXOUT_L0N LVDS_TXLN0 25
1 2 G17 B13 LVDS_TXLP1
AVSSN1 TXOUT_L1P LVDS_TXLP1 25
1 1 1 H17 A13 LVDS_TXLN1
AVSSN2 TXOUT_L1N LVDS_TXLN1 25
C490 C496 AVDD=250mA A20 H14 LVDS_TXLP2
+ AVDDDI TXOUT_L2P LVDS_TXLP2 25
AVSSQ_GND C186 B20 G14 LVDS_TXLN2
AVSSDI TXOUT_L2N LVDS_TXLN2 25
150U_D2_6.3VM 1U_0603_10V4Z 2.2U_0805_10V6K D17
PLLVDD 2 2 TXOUT_L3P
2
AVDDQ=200mA A21 AVDDQ TXOUT_L3N E17
AVDDQ A22 AVSSQ

CRT/TVOUT
L53 A15 LVDS_TXUP0
TXOUT_U0P LVDS_TXUP0 25
1 2 R230-R232 CLOSE TO NB C21 B16 LVDS_TXUN0
C TXOUT_U0N LVDS_TXUN0 25
MBK2012121YZF_0.2ohm/800mA_0805
1 1 1 1 C20 C17 LVDS_TXUP1
Y TXOUT_U1P LVDS_TXUP1 25
C499 C485 C492 D19 C18 LVDS_TXUN1
COMP TXOUT_U1N LVDS_TXUN1 25
10U_0805_10V4Z

C183 + @ B17 LVDS_TXUP2


TXOUT_U2P LVDS_TXUP2 25
4.7U_0805_10V4Z CRT_R AVSSQ_GND E19 A17 LVDS_TXUN2
2 2 24
2 CRT_R RED TXOUT_U2N LVDS_TXUN2 25
CRT_G F19 A18
2 24 CRT_G GREEN TXOUT_U3P
CRT_B G19 B18
24 CRT_B BLUE TXOUT_U3N
150U_D2_6.3VM 1U_0603_10V4Z VGA_CRT_VSYNC C6
24 VGA_CRT_VSYNC DACVSYNC

1
150_0402_1%

150_0402_1%

150_0402_1%
8mils TRACE VGA_CRT_HSYNC A5 E15 LVDS_TXLCKP
24 VGA_CRT_HSYNC DACHSYNC TXCLK_LP LVDS_TXLCKP 25
R75 R76 R74 D15 LVDS_TXLCKN RS485: LVDDR18A=1.8V
TXCLK_LN LVDS_TXLCKN 25
1 2 B21 H15 LVDS_TXUCKP +1.8VS
RSET TXCLK_UP LVDS_TXUCKP 25
R386 715_0402_1% G15 LVDS_TXUCKN L54 +3VS
TXCLK_UN LVDS_TXUCKN 25
+1.8VS R55 1 2 0_0402_5% B6 1 1 1 1 2
24 VGA_DDC_CLK

2
DACSCL

1
HTPVDD R56 1 2 0_0402_5% A6 D14 C154 C172 MBK2012121YZF_0805

LVTM
C 24 VGA_DDC_DATA DACSDA LPVDD C
E14 0.1U_0402_16V4Z C177 MBK2012121YZF_0805 L55
L56 LPVSS 4.7U_0805_10V4Z
PLLVDD PLLVDD18=625mA A10 PLLVDD(PLLVDD18) 2 2 2
1 2 +1.8VS +3VS B10 A12 LPVSS_GND +1.8VS
MBK2012121YZF_0.2ohm/800mA_0805 PLLVSS LVDDR18D_1 1U_0603_10V4Z L57
LVDDR18D_2 B12
HTPVDD=200mA B24

PLL PWR
1 1 1 HTPVDD C12 1 2

2
HTPVDD LVDDR18A_1(LVDDR33_1)

1
10U_0805_10V4Z

@ C493 C498 C488 R568 2 1 10K_0402_5% R46 B25 C13 MBK2012121YZF_0805


1K_0402_5% HTPVSS LVDDR18A_2(LVDDR33_2)
LVDDR33=180mA
2
B

4.7U_0805_10V4Z C10 A16 C491


2 2 2 19,26,28,31 NB_RST# SYSRESET# LVSSR1

4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0805_10V4Z
Q27 R62 1 2 0_0402_5% C11 A14 C171 1 1 1 1 1 1
28,37 NB_PWROK POWERGOOD LVSSR3
E

1U_0603_10V4Z
3 1 LDT_STOP#_NB C5 D12 C176 C481 C131 C497
8,18 LDT_STOP#
2
LDTSTOP# LVSSR5
C

1U_0603_10V4Z
1U_0603_10V4Z B5 C19
18 ALLOW_LDTSTOP ALLOW_LDTSTOP LVSSR6
MMBT3904_SOT23 C15

PM
R383 2 LVSSR7 2 2 2 2 2 2
1 10K_0402_5% C23 HTTSTCLK LVSSR8 C16
17 HTREFCLK B23 HTREFCLK
+1.2V_HT +PLLVDD12
L70 PLLVDD12=70mA C2 F14
TVCLKIN LVSSR12
1 2 LVSSR13 F15
1 1 17 NB_OSC B11 OSCIN

CLOCKs
MBC1608121YZF_0.4ohm/300mA_0603 +PLLVDD12 A11
C690 C691 OSCOUT(PLLVDD12)
PLLVDD12=70mA
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z F2
2 2 17 NBSRC_CLKP GFX_CLKP
E1 E12 LVDS_ENVDD LVSSR_GND
17 NBSRC_CLKN GFX_CLKN LVDS_DIGON
RS690 A11: This clock is needed even if External Graphic slot is not supported G12 LVDS_ENBKL
LVDS_BLON TP4 PAD
17 SBLINK_CLKP G1 SB_CLKP LVDS_BLEN F12
+3VS G2
17 SBLINK_CLKN SB_CLKN
DVO_D0(GPP_TX0P) AD14
R73 1 2 @ 2.7K_0402_5% DFT_GPIO0 D6 AD15
DFT_GPIO0 DVO_D1(GPP_TX0N)
16 LOAD_ROM#
R60 1 2 @ 2.7K_0402_5% DFT_GPIO2
D7
C8
DFT_GPIO1 DVO_D2(DEBUG6) AE15
AD16
PVT
R57 @ 2.7K_0402_5% DFT_GPIO3 DFT_GPIO2 DVO_D3(GPP_RX0P) R744 0_0402_5%
1 2 C7 DFT_GPIO3 DVO_D4(GPP_RX0N) AE16
2

2
4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

B R58 1 2 @ 2.7K_0402_5% DFT_GPIO4 B8 AC17 LVDS_ENVDD 1 2 ENVDD B


DFT_GPIO4 DVO_D5(DEBUG9) ENVDD 25
R50 R51 R49 R59 1 2 @ 2.7K_0402_5% DFT_GPIO5 A8 AD18
DFT_GPIO5 DVO_D6(DEBUG10) R745 @ 0_0402_5%
DVO_D7(GPP_TX1N) AE19

DVO
@ @ R634 1 2 0_0402_5% B2 AD19 LVDS_ENBKL 1 2 ENBKL ENBKL 28
18 BMREQ#

MIS.
EDID_LCD_CLK BMREQ# DVO_D8(GPP_TX1P)
25 EDID_LCD_CLK A2 AE20
1

EDID_LCD_CLK EDID_LCD_DAT I2C_CLK DVO_D9(GPP_RX1N) @


25 EDID_LCD_DAT B4 I2C_DATA DVO_D10(GPP_RX1P) AD20
AA15 THERMALDIODE_P DVO_D11(DEBUG15) AE21
EDID_LCD_DAT AB15 THERMALDIODE_N +3VS C763
DVO_VSYNC(DEBUG0) AD13
DDC_DATA C14 AC13 0.1U_0402_16V4Z
DDC_DATA TMDS_HPD DVO_DE(DEBUG2)
B3 DDC_DATA DVO_HSYNC(DEBUG1) AE13
C3 TESTMODE DVO_IDCKP(DEBUG14) AE17

5
STRP_DATA A3 AD17
STRP_DATA DVO_IDCKN(DEBUG13)
1

LVDS_ENVDD 2

P
R377 B ENVDD
Y 4
4.7K_0402_5% 216MQA6AVA11FG_FCBGA465_RS690M 1 2 1 A

G
R746 2K_0402_5% U48
+3VS +3VS RS690MC : SA00001I480 / S IC 216LQA6AVA12FG RS690MC BGA 465P 0FA NC7SZ08P5X_NL_SC70-5
2

3
NB_PWROK
R541 1 2 0_0805_5%
1

5
1

R40 2

P
10K_0402_5% R41 B ENBKL
Y 4
U2 @ 10K_0402_5% LPVSS_GND LVDS_ENBKL 1 A

G
1 8 U49
2

A0 VCC NC7SZ08P5X_NL_SC70-5
2 7 1 2
2

3
A1 WP EDID_LCD_CLK R542 1
3 A2 SCL 6 2 0_0805_5% R747 2K_0402_5%
4 5 STRP_DATA
A VSS SDA A
AT24C04N-10SI-2.7_SO8
1

@
1 R39
C117 10K_0402_5% LVSSR_GND

0.1U_0402_16V4Z @ Security Classification Compal Secret Data


2

2 @
Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
RS690M-SYSTEM I/F & CLKGEN
NOTE: ACCESS TO STRAP_DATA and I2C_CLK PINS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
IS MANDATORY. Custom KAW60 LA-4661P 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 14 of 50
5 4 3 2 1
5 4 3 2 1

NB RS485 POWER STATES


Power Signal S0 S1 S3 S4/S5 G3
VDDHT ON ON OFF OFF OFF
VDDR ON ON OFF OFF OFF
VDD18 ON ON OFF OFF OFF
VDDC ON ON OFF OFF OFF
D VDDA18 ON ON OFF OFF OFF D

VDDA12 ON ON OFF OFF OFF


AVDD ON ON OFF OFF OFF
AVDDDI ON ON OFF OFF OFF
PLLVDD ON ON OFF OFF OFF
HTPVDD ON ON OFF OFF OFF
VDDR3 ON ON OFF OFF OFF
LPVDD ON ON OFF OFF OFF
LVDDR18D ON ON OFF OFF OFF +1.2V_HT
+1.2V_HT
LVDDR18A ON ON OFF OFF OFF L59
L63 1 2
2 1 KC FBM-L11-201209-221LMAT_0.04ohm/3A_0805 U39E
L60
KC FBM-L11-201209-221LMAT_0.04ohm/3A_0805 +1.2VS_SB_VDD=500mA 1 2 A25
L64 KC FBM-L11-201209-221LMAT_0.04ohm/3A_0805 VSS1
F11 VSS2 PAR 5 OF 5 VSSA2 V12
2 1 D23 VSS3 VSSA3 V11
E9 VSS4 VSSA4 V14
KC FBM-L11-201209-221LMAT_0.04ohm/3A_0805 VDDA12 G11 F3
VDD_HT U39D VSS5 VSSA5
VDDA12=2.5A Y23 VSS6 VSSA6 V15
VDD_HT=800mA AA17 VDD_HT1 PART 4 OF 5 VDDA12_1 B1 P11 VSS7 VSSA7 A1
1U_0402_6.3V4Z AB17 C1 1 1 1 1 1 1 R24 H1
VDD_HT2 VDDA12_2 VSS8 VSSA8
10U_0805_10V4Z

1U_0402_6.3V4Z
C AB19 D1 C110 C130 C112 C93 C106 C75 AE18 G3 C
1 1 1 1 1 1 VDD_HT3 VDDA12_3 VSS9 VSSA9
C37 C46 C54 C50 C49 C48 AC18 D2 + M15 J2
VDD_HT4 VDDA12_4 10U_0805_10V4Z 10U_0805_10V4Z VSS10 VSSA10
AC19 VDD_HT5 VDDA12_5 D3 J22 VSS11 VSSA11 H3
2 2 2 2 2 150U_D2_6.3VM
AC20 VDD_HT6 VDDA12_6 E2 G23 VSS12
2 2 2 2 2 2 2
AD21 VDD_HT7 VDDA12_7 E3 J12 VSS13 VSSA13 J6
1U_0402_6.3V4Z 1U_0402_6.3V4Z AD22 F4 1U_0402_6.3V4Z L12
VDD_HT8 VDDA12_8 VSS14
2006/4/14 FOR EMI 1U_0402_6.3V4Z 1U_0402_6.3V4Z AD23 VDD_HT9 VDDA12_9 E6 1U_0402_6.3V4Z L14 VSS15 VSSA15 F1
AD24 VDD_HT10 VDDA12_10 G7 L20 VSS16 VSSA16 L6
+1.8VS L2 VDD18 AE23 L9 L23 M2
VDD_HT11 VDDA12_11 VSS17 VSSA17
1 2 AE24 VDD_HT12 VDDA12_12 M9 M11 VSS18 VSSA18 M6
MBC1608121YZF_0.4ohm/300mA_06031 1 1 1 AE25 VDDC=5A +1.2V_HT M20 J3
VDD_HT13 VSS19 VSSA19

POWER
C330 C141 C142 C123 W17 A4 M23 P6
VDD_HT14 VDDC_1 VSS20 VSSA20
Y17 VDD_HT15 VDDC_2 A7 1 1 1 1 1 1 M25 VSS21 VSSA21 T1
820P_0402_50V7K VDD18=2mA A9 C115 C126 C87 C94 C60 C79 N12 N3
2 2 2 2 VDDC_3 VSS22 VSSA22
J14 VDD18_1 VDDC_4 A19 N14 VSS23
+1.2V_HT 2.2U_0805_10V6K 1U_0402_6.3V4Z 1U_0402_6.3V4Z J15 B9 1U_0402_6.3V4Z R6
L58 VDDA12 VDD18_2 VDDC_5 2 2 2 2 2 2 VSSA24
VDD12=2.5A VDDC_6 B19 L24 VSS25 VSSA25 U2
1 1 2 KC FBM-L11-201209-221LMAT_0.04ohm/3A_0805 AB3 VDDA18_1(VDDA12_13) VDDC_7 C9 10U_0805_10V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z P13 VSS26 VSSA26 T3
AB4 D9 10U_0805_10V4Z 1U_0402_6.3V4Z P20

GROUND
1 1 1 1 1 1 1 VDDA18_2(VDDA12_14) VDDC_8 VSS27 VSSA27 U3
10U_0805_10V4Z

+ C25 C44 C40 C459 C460 C462 C456 C461 AC3 D20 P15 U6
VDDA18_3(VDDA12_15) VDDC_9 1 1 1 VSS28 VSSA28
AD2 G20 C108 C138 C135 R12
150U_D2_6.3VM VDDA18_4(VDDA12_16) VDDC_10 VSS29
AE1 VDDA18_5(VDDA12_17) VDDC_11 H11 R14 VSS30 VSSA30 Y1
2 2 2 2 2 2 2 2
AE2 VDDA18_6(VDDA12_18) VDDC_12 J11 R20 VSS31
10U_0805_10V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 2 2 2
U7 VDDA18_7(VDDA12_19) VDDC_13 J19 W23 VSS32 VSSA32 W6
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z W7 L11 1 1U_0402_6.3V4Z 1U_0402_6.3V4Z Y25 AC2
+3VS L3 VDDR3 VDDA18_8(VDDA12_20) VDDC_14 C24 1U_0402_6.3V4Z VSS33 VSSA33
VDDR3=70mA VDDC_15 L13 1 AD25 VSS34 VSSA34 Y3
1 2 D11 L15 + C31 U20 Y9
VDDR3_1 VDDC_16 10U_0805_10V4Z VSS35 VSSA35
1 1 E11 VDDR3_2 VDDC_17 L17 H25 VSS36 VSSA36 Y11
MBC1608121YZF_0.4ohm/300mA_0603 C161 C160 M12 150U_D2_6.3VM W24 Y12
VDDC_18 2 2 VSS37 VSSA93
VDDR=100mA AC12 VDD_DVO1(VDDR_1) VDDC_19 M14 Y22 VSS38 VSSA94 Y14
B 1U_0402_6.3V4Z 4.7U_0805_10V4Z AD12 N11 AC23 AA3 B
2 2 VDD_DVO2(VDDR_2) VDDC_20 VSS39 VSSA95
AE12 VDD_DVO3(VDDR_3) VDDC_21 N13 D25 VSS40 VSSA37 R9
VDD12=50mA VDDC_22 N15 G24 VSS41 VSSA38 AD1
VDDR E7 P12 AC14 AC5
+1.8VS L1 VDDA12(VDDPLL_1) VDDC_23 VSS42 VSSA39
F7 VDDA12(VDDPLL_2) VDDC_24 P14 VSSA40 AC6
1 2 F9 VSSA12(VSSPLL_1) VDDC_25 P17 AC22 VSS44 VSSA41 AC7
MBK2012121YZF_0.2ohm/800mA_0805 1 1 1 G9 R11 R23 AD3
VSSA12(VSSPLL_2) VDDC_26 VSS45 VSSA42
1U_0402_6.3V4Z

C38 C42 C43 R13 C4 AC9


VDDC_27 VSS46 VSSA43
VDDHT_PKG D22 VDDHT_PKG VDDC_28 R15 AE22 VSS47 VSSA44 AC10
VDDA12_PKG1 M1 VDDA12_PKG1 VDDC_29 U11 T23 VSS48 VSSA45 G6
2 2 2
VDDA12_PKG2 AC11 VDDA12_PKG2 VDDC_30 U12 T25 VSS49 VSSA46 Y15
1U_0402_6.3V4Z U14 AE14 AC4
1U_0402_6.3V4Z VDDC_31 VSS50 VSSA47
VDDC_32 U15 R17 VSS51 VSSA48 P9
H23 VSS52 VSSA49 AE6
VDDA12 VDDPLL VDDA12_PKG1 216MQA6AVA11FG_FCBGA465_RS690M M17 AE10
L76 VSS53 VSSA50
A23 VSS54 VSSA51 M3
1 2
MBC1608121YZF_0.4ohm/300mA_0603
1 RS690MC : SA00001I480 / S IC 216LQA6AVA12FG RS690MC BGA 465P 0FA AC15 VSS55
1 1 F17 VSS56
4.7U_0805_10V4Z

C140 C168 C134 D4


10U_0805_10V4Z VSS57
1U_0402_6.3V4Z 2
M13 VSS59
2 2
RS485: 0 Ohm RESISTOR AC16 VSS60
RS690: 220 Ohm 500mA FERRITE BEAD H12 VSS61
B7 VSS62

216MQA6AVA11FG_FCBGA465_RS690M

A A

Security Classification Compal Secret Data


Issued Date 2005/10/10 Deciphered Date 2006/10/10 Title
RS690MC-POWER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, August 07, 2008 Sheet 15 of 50
5 4 3 2 1
5 4 3 2 1

R67

1 2 H1 H2 H4 H21 H22
14 LOAD_ROM#
H_S394D138 H_S394D138 H_S394D138 H_S394D138 H_S394D138
2.7K_0402_5%
D D
@ @ @ @ @ @

1
LOAD_ROM#: LOAD ROM STRAP ENABLE

High, LOAD ROM STRAP DISABLE H23 H14 H15 H28 H7


H_S394D138 H_S394D138 H_S394D138 H_S394D138 H_5P2
Low, LOAD ROM STRAP ENABLE
@ @ @ @ @

1
H8 H9 H10 H3 H6
H_5P2 H_5P2 H_5P2 H_C236D161 H_C236D161

@ @ @ @ @

1
H29 H31 H11 H12 H17
H_C236D161 H_S315D118 H_O134X118D55X39 H_O134X118D55X39 H_O134X118D55X39

@ @ @ @ @

1
C +5VS +1.8VALW +5VS +3VALW +1.8VS +3VS +1.8VALW +3VS C

1 1 1 1
C653 C654 C655 C656 H18 H16 H19 H13 H24
H_O134X118D55X39 H_C276D118 H_C276D118 H_S354D138 H_S354D138
@ @ @ @
2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z @ @ @ @ @

1
H25 H32 H33 H35 H34
H_S354D138 H_S315D138 H_C315D236 H_C163D163N H_O217X157D217X157N

@ @ @ @ @

1
B B

FD2 FD1 FD3 FD5 FD4 FD6

@ @ @ @ @ @
1

1
CF8 CF21 CF7 CF10 CF12 CF4 CF6

@ @ @ @ @ @ @
1

1
CF9 CF1 CF2 CF5 CF11

@ @ @ @ @
1

A A

Security Classification Compal Secret Data


Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
RS690MC-STRAPS & SCREW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 16 of 50
5 4 3 2 1
5 4 3 2 1

+3VS
CLK_VDD
L8 CLK_VDD=500mA
1 2 +3VS
MBK2012121YZF_0805 1 1 1 1 1 1 1 1 1 CLK_VDDA=50mA L10

10U_0805_10V4Z
C277 C272 C263 C276 C268 C259 C254 C248 C279 CLK_VDDA 1 2
2 1 MBK2012121YZF_0805
C261 C260
2 2 2 2 2 2 2 2 2
0.1U_0402_16V4Z 10U_0805_10V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2
D 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z D

+3VS

1- PLACE ALL SERIAL TERMINATION L9 CLK_VDD48=50mA CLK_VDD


RESISTORS CLOSE TO U800 1 2
MBK2012121YZF_0805 U40
2- PUT DECOUPLING CAPS CLOSE TO U800 1 R427
POWER PIN C252 54 50 261_0402_1%
VDDCPU VDDA
14 VDDSRC GNDA 49 1 2
+3VS 2.2U_0805_10V6K 23 47.5_0402_1%
2 VDDSRC CPUCLK_EXT_R R423 1
28 VDDSRC CPUCLK8T0 56 2 CPUCLK 8
L6 44 55 CPUCLK#_EXT_R R429 1 2 47.5_0402_1%
VDDSRC CPUCLK8C0 CPUCLK# 8
1 2 CLK_VDD48 5 52
MBK2012121YZF_0805 VDD48 CPUCLK8T1
39 VDDATIG CPUCLK8C1 51
1 CLK_VDDREF 2
C246 VDDREF SBLINK_CLKP_R R435 33_0402_1% SBLINK_CLKP
CLK_VDDREF=50mA 60 VDDHTT SRCCLKT6 16 1 2 SBLINK_CLKP 14
17 SBLINK_CLKN_R R437 1 2 33_0402_1% SBLINK_CLKN PCI-E A-LINK
SRCCLKC6 SBLINK_CLKN 14
2.2U_0805_10V6K 53 41 NBSRC_CLKP_R R450 1 2 33_0402_1% NBSRC_CLKP
2 GNDCPU ATIGCLKT0 NBSRC_CLKP 14
15 40 NBSRC_CLKN_R R456 1 2 33_0402_1% NBSRC_CLKN PCI-E GFX
GNDSRC ATIGCLKC0 NBSRC_CLKN 14
22 GNDSRC ATIGCLKT1 37
PVT Parallel Resonance Crystal 29 GNDSRC ATIGCLKC1 36 RS690 A11: This clock is needed even if External Graphic slot is not supported
45 GNDSRC ATIGCLKT2 35
+3VS C511 1 2 8 34
GND48 ATIGCLKC2
38 GNDATIG ATIGCLKT3 30

2
27P_0402_50V8J 1 31
R412 GNDREF ATIGCLKC3 SBSRC_CLKP_R R443 1
58 GNDHTT SRCCLKT5 18 2 33_0402_1% SBSRC_CLKP 18
Y5 @ 19 SBSRC_CLKN_R R449 1 2 33_0402_1% PCI-E A-LINK
SRCCLKC5 SBSRC_CLKN 18
1

CLK_X1 3 20

2
R415 1M_0402_5% X1 SRCCLKT4
21

1
C C510 1 CLK_X2 SRCCLKC4 C
10K_0402_5% 2 2 1 4 X2 SRCCLKT3 24
14.31818MHz_20P_1BX14318BE1A 25
27P_0402_50V8J R417 0_0402_5% SRCCLKC3 CLK_PCIE_LAN_R R637 33_0402_1%
26 1 2 CLK_PCIE_LAN 26
2

SRCCLKT2 CLK_PCIE_LAN#_R R638 33_0402_1%


SRCCLKC2 27 1 2 CLK_PCIE_LAN# 26
11 47 CLK_PCIE_MINI_R R438 1 2 33_0402_1%
RESET_IN# SRCCLKT0 CLK_PCIE_MINI 31
61 46 CLK_PCIE_MINI#_R R444 1 2 33_0402_1%
NC SRCCLKC0 CLK_PCIE_MINI# 31
SRCCLKT1 43
42 +3VS
SRCCLKC1

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%
12 R63910K_0402_5%
SRCCLKT7
SRCCLKC7 13 1 2

2
R426 0_0402_5%
SB_CK_SCLK R425 1 2 0_0402_5% 9 57 1 2
10,11,19,31 SB_CK_SCLK SMBCLK CLKREQA# LAN_CLKREQ# 26

1 R445

1 R439

1 R458

1 R453

1 R448

1 R442

1 R457

1 R451

1 R436

1 R434
SB_CK_SDAT R431 1 2 0_0402_5% 10 32
10,11,19,31 SB_CK_SDAT SMBDAT CLKREQB#
33 R461 1 2 0_0402_5%
CLKREQC# MINI_CLKREQ# 31
48 IREF 48MHz_1 7 PCI-E resource CLKREQ
Ioh = 5 * Iref 6 CLK_48M_USB_R
48MHz_0
(2.32mA) 2 CLK_VDD 2.2K_0402_5%
R433

1
Voh = 0.71V @ 60 ohm 475_0402_1% 63 R416 1 2 33_0402_1%
FS1/REF1 CLK_USB_48M 19
64 R402 R401 R409
FS0/REF0
62
1

FS2/REF2 2.2K_0402_5% 2.2K_0402_5%


HTTCLK0 59

2
R404 1 2 8.2K_0402_5% R400 2 1 @ 0_0402_5%
ICS951462AGLFT_TSSOP64 R403 1 2 8.2K_0402_5% R399 2 1 @ 0_0402_5%
R413 1 2 8.2K_0402_5% R410 2 1 @ 0_0402_5%

SB_OSCIN_R R407 1 2 33_0402_1% SB_OSCIN 19


B NB_OSCIN_R R418 1 2 33_0402_1% B
NB_OSC 14
HTREFCLK_R R419 1 2 33_0402_1% HTREFCLK 14

1
R420
49.9_0402_1%
EXT CLK FREQUENCY SELECT TABLE(MHZ)

2
FS2 FS1 FS0 CPU SRCCLK HTT PCI USB COMMENT
[2:1]

0 0 0 Hi-Z 100.00 Hi-Z Hi-Z 48.00 Reserved


0 0 1 X 100.00 X/3 X/6 48.00 Reserved
0 1 0 180.00 100.00 60.00 30.00 48.00 Reserved
0 1 1 220.00 100.00 36.56 73.12 48.00 Reserved
1 0 0 100.00 100.00 66.66 33.33 48.00 Reserved
1 0 1 133.33 100.00 66.66 33.33 48.00 Reserved
1 1 1 200.00 100.00 66.66 33.33 48.00 Normal ATHLON64 operation

A A

Security Classification Compal Secret Data


Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
EXTERNAL CLOCK GENERATOR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 17 of 50
5 4 3 2 1
5 4 3 2 1

U18A
SB600 SB U2 CLK_PCI_LAN_R
PCICLK0 CLK_PCI_LAN_R 22
T2 CLK_PCI_LPC_R
PCICLK1 CLK_PCI_LPC_R 22
17 SBSRC_CLKP J24 PCIE_RCLKP PCICLK2 U1

PCI CLKS
17 SBSRC_CLKN J25 PCIE_RCLKN PCICLK3 V2
W3 CLK_PCI_1394_R CLK_PCI_LPC_R R255 1 2 22_0402_5%
PCICLK4 CLK_PCI_1394_R 22 CLK_PCI_LPC 28
A_MRX_STX_P0 C509 1 2 0.1U_0402_16V7K A_MRX_C_STX_P0 P29 U3
13 A_MRX_STX_P0 PCIE_TX0P PCICLK5
+3VALW A_MRX_STX_N0 C508 1 2 0.1U_0402_16V7K A_MRX_C_STX_N0 P28 V1 R237 1 2 22_0402_5%

PCI EXPRESS INTERFACE


13 A_MRX_STX_N0 PCIE_TX0N PCICLK6 PCI_CLK6 22
A_MRX_STX_P1 C216 1 2 0.1U_0402_16V7K A_MRX_C_STX_P1 M29 T1 SB_GPIO41 R702 1 2 10K_0402_5%
13 A_MRX_STX_P1 PCIE_TX1P SPDIF_OUT/PCICLK7/GPIO41
A_MRX_STX_N1 C217 1 2 0.1U_0402_16V7K A_MRX_C_STX_N1 M28
13 A_MRX_STX_N1 PCIE_TX1N
1 2 SB_TEST0 A_MRX_STX_P2 C663 1 2 0.1U_0402_16V7K A_MRX_C_STX_P2 K29 AJ9 @
13 A_MRX_STX_P2 PCIE_TX2P PCIRST#
R692 @ 2.2K_0402_5% A_MRX_STX_N2 C664 1 2 0.1U_0402_16V7K A_MRX_C_STX_N2 K28
13 A_MRX_STX_N2 PCIE_TX2N
1 2 SB_TEST1 A_MRX_STX_P3 C665 1 2 0.1U_0402_16V7K A_MRX_C_STX_P3 H29
D 13 A_MRX_STX_P3 PCIE_TX3P D
R693 @ 2.2K_0402_5% A_MRX_STX_N3 C666 1 2 0.1U_0402_16V7K A_MRX_C_STX_N3 H28 W7
13 A_MRX_STX_N3 PCIE_TX3N AD0/ROMA18
1 2 SB_TEST2 Y1
R694 @ 2.2K_0402_5% A_MTX_C_SRX_P0 AD1/ROMA17
13 A_MTX_C_SRX_P0 T25 PCIE_RX0P AD2/ROMA16 W8
A_MTX_C_SRX_N0 T26 W5
13 A_MTX_C_SRX_N0 PCIE_RX0N AD3/ROMA15
A_MTX_C_SRX_P1 T22 AA5
13 A_MTX_C_SRX_P1 PCIE_RX1P AD4/ROMA14
A_MTX_C_SRX_N1 T23 Y3
13 A_MTX_C_SRX_N1 PCIE_RX1N AD5/ROMA13
A_MTX_C_SRX_P2 M25 AA6
13 A_MTX_C_SRX_P2 PCIE_RX2P AD6/ROMA12
A_MTX_C_SRX_N2 M26 AC5
+1.8VS 13 A_MTX_C_SRX_N2 PCIE_RX2N AD7/ROMA11
A_MTX_C_SRX_P3 M22 AA7
13 A_MTX_C_SRX_P3 PCIE_RX3P AD8/ROMA9
A_MTX_C_SRX_N3 M23 AC3
13 A_MTX_C_SRX_N3 PCIE_RX3N AD9/ROMA8
2 1 ALLOW_LDTSTOP AC7
R691 1K_0402_5% R137 1 AD10/ROMA7
2 562_0402_1% E29 PCIE_CALRP AD11/ROMA6 AJ7
PCIE_VDDR R138 1 2 2.05K_0402_1% E28 AD4
PCIE_CALRN AD12/ROMA5
AD13/ROMA4 AB11
R136 1 2 0_0402_5% E27 AE6
PCIE_CALI AD14/ROMA3
AD15/ROMA2 AC9
AD16/ROMD0 AA3
R440 1 2 0_0402_5% AC26 AJ4
8 CPU_PWRGD CPU_PG/LDT_PG AD17/ROMD1
W26 INTR/LINT0 AD18/ROMD2 AB1
+3VALW W24 AH4
NMI/LINT1 AD19/ROMD3
W25 INIT# AD20/ROMD4 AB2
AA24 SMI# AD21/ROMD5 AJ3
8,14 LDT_STOP# LDT_STOP# AA23 AB3
SB_PCIE_WAKE# CPU_SIC SLP#/LDT_STP# AD22/ROMD6 PCI_AD23
2 1 JAQ60 pop 8 CPU_SIC AA22 IGNNE#/SIC AD23/ROMD7 AH3 PCI_AD23 22
R466 10K_0402_5% CPU_SID AA26 AC1 PCI_AD24 PCI_AD24 22

CPU
8 CPU_SID A20M#/SID AD24
Y27 AH2 PCI_AD25 PCI_AD25 22
@ ALLOW_LDTSTOP FERR# AD25 PCI_AD26
14 ALLOW_LDTSTOP AA25 STPCLK#/ALLOW_LDTSTP AD26 AC2 PCI_AD26 22
2 1 PBTN_OUT# JAQ60 unpop AH9 AH1 PCI_AD27 PCI_AD27 22
R701 1K_0402_1% FOR SB460, THIS BALL CPU_STP#/DPSLP_3V# AD27 PCI_AD28
B24 DPSLP_OD#/GPIO37 AD28 AD2 PCI_AD28 22
IS LDT_RST# ONLY W23 AG2
C @ DPRSLPVR AD29 C
8 LDT_RST# AC25 LDT_RST#/DPRSTP#/PROCHOT# AD30 AD1
2 1 PM_SLP_S3# JAQ60 unpop AG1
R470 4.7K_0402_5% AD31
CBE0#/ROMA10 AB9

PCI INTERFACE
EC_SWI# A3 AF9
28 EC_SWI# PCI_PME#/GEVENT4# CBE1#/ROMA1

ACPI / WAKE UP EVENTS


@ EC_SCI# B2 AJ5
28 EC_SCI# RI#/EXTEVNT0# CBE2#/ROMWE#
2 1 PM_SLP_S5# JAQ60 unpop 28 PM_SLP_S3# PM_SLP_S3# F7 AG3
R184 4.7K_0402_5% PM_SLP_S5# SLP_S3# CBE3#
28 PM_SLP_S5# A5 SLP_S5# FRAME# AA2
PBTN_OUT# E3 AH6
@ 28 PBTN_OUT# SB_PWROK PWR_BTN# DEVSEL#/ROMA0
8,28,37 SB_PWROK B5 PWR_GOOD IRDY# AG5
2 1 S3_STATE_R JAQ60 unpop B3 AA1
R465 10K_0402_5% SB_TEST0 SUS_STAT# TRDY#/ROMOE#
G9 TEST0 PAR/ROMA19 AF7
SB_TEST1 E9 Y2
@ SB_TEST2 TEST1 STOP#
F9 TEST2 PERR# AG8
2 1 BLINK/GPM6# JAQ60 unpop 2 1 S3_STATE_R D9 AC11
28 S3_STATE S3_STATE/GEVENT5# SERR#
R197 10K_0402_5% R577 @ 0_0402_5% F4 AJ8
SB_PCIE_WAKE# SYS_RESET#/GPM7# REQ0#
26,31 SB_PCIE_WAKE# E7 WAKE#/GEVENT8# REQ1# AE2
@ BLINK/GPM6# C2 AG9
EC_SWI# H_THERMTRIP# BLINK/GPM6# REQ2#
2 1 JAQ60 unpop 8 H_THERMTRIP# G7 SMBALERT#/THRMTRIP#/GEVENT2# REQ3#/GPIO70 AH8
R267 10K_0402_5% R741 0_0402_5% AH5 PCI_REQ#4 PCI_REQ#4 22
CRT_DET_R 2 REQ4#/GPIO71
PVT 19 CRT_DET_R
@
1 D7
C25
LPC_PME#/GEVENT3# GNT0# AD11
AF2
EC_SCI# EC_GA20 LPC_SMI#/EXTEVNT1# GNT1#
2 1 JAQ60 unpop 28 EC_GA20 AF26 GA20IN GNT2# AH7
R571 10K_0402_5% EC_KBRST# AG26 AB12
28 EC_KBRST# KBRST# GNT3#/GPIO72 PCI_GNT#4
GNT4#/GPIO73 AG4 PCI_GNT#4 22
LPC_AD0 AG24 AG7 PM_CLKRUN# +3VS
28 LPC_AD0 LAD0 CLKRUN# PM_CLKRUN# 28
@ LPC_AD1 AG25 AF6 @
28 LPC_AD1 LAD1 LOCK#

LPC
20M_0603_5% 2 1 R244 LPC_AD2 AH24 PM_CLKRUN# R120 1 2 10K_0402_5%
28 LPC_AD2 LAD2
LPC_AD3 AH25 AD3
28 LPC_AD3 LAD3 INTE#/GPIO33
18P_0402_50V8J C314 LPC_FRAME# AF24 AF1
28 LPC_FRAME# LFRAME# INTF#/GPIO34
1 2 AJ24 LDRQ0# INTG#/GPIO35 AF4
B AH26 AF3 B
Y3 BMREQ# LDRQ1#/GNT5#/GPIO68 INTH#/GPIO36
14 BMREQ# W22 BMREQ#/REQ5#/GPIO65
2

3 4 SERIRQ AF23
NC OUT R218 28 SERIRQ SERIRQ
2 1 20M_0603_5% 32K_X1 D2 D3 RTC_CLK 22 +RTCBATT
NC IN X1 RTCCLK

XTAL
RTC_IRQ#/GPIO69 F5 RTC_IRQ# 22
1

32.768KHZ_12.5P_1TJS125DJ2A073
1 2 32K_X2 C1 E1 VBAT_IN

RTC
X2 VBAT
RTC_GND D1 1 1
18P_0402_50V8J C307 C322

1
218S6ECLA13FG_FCBGA548_SB600 C315
0.1U_0402_16V4Z D7
2 2
SB600 : SA00001DUD0 / S IC 218S6ECLA21FG SB600 FCBGA 549P 0FA 1U_0402_6.3V4Z BAS40-04_SOT23
+RTCVCC
2 1

2
R240
J2 10K_0603_5% 2 1 +CHGRTC
@ 510_0402_5% 1 1
close to RAM door
C317 C327
@ 0.1U_0402_16V4Z
4.7U_0805_10V4Z 2 2
@
R703 2 1 10K_0402_5% BMREQ#

A
RTC Battery A

Security Classification Compal Secret Data


Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
SB600-PCIE/CPU/LPC/ACPI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 18 of 50
5 4 3 2 1
5 4 3 2 1

+3VALW

@
PLACE SATA AC COUPLING R464 2 1 10K_0402_5% EC_SMI# JAQ60 unpop
@
CAPS CLOSE TO SB460 R44 2 1 10K_0402_5% USB_OC#0 JAQ60 unpop
@
U18B R507 2 1 10K_0402_5% USB_OC#2 JAQ60 unpop
SATA_STX_C_DRX_P0 0.01U_0402_16V7K 1 2 C554 SATA_STX_DRX_P0
23 SATA_STX_C_DRX_P0
SATA_STX_C_DRX_N0 0.01U_0402_16V7K 1 2 C556 SATA_STX_DRX_N0
AH21
AJ21
SATA_TX0+ SB600 SB AB29
23 SATA_STX_C_DRX_N0 SATA_TX0- IDE_IORDY
AH18 SATA_TX1+ IDE_IRQ AA28
+3VALW +3VS
SATA_STX_C_DRX_P2 0.01U_0402_16V7K 1 2 C668 SATA_STX_DRX_P2
AJ18
AH13
SATA_TX1- IDE_A0 AA29
AB27
PVT
23 SATA_STX_C_DRX_P2 SATA_TX2+ IDE_A1
SATA_STX_C_DRX_N2 0.01U_0402_16V7K 1 2 C669 SATA_STX_DRX_N2 AH14 Y28
23 SATA_STX_C_DRX_N2 SATA_TX2- IDE_A2

10K_0402_5%

10K_0402_5%
D AJ11 AB28 D
SATA_TX3+ IDE_DACK#

2
AH11 SATA_TX3- IDE_DRQ AC27
AC29 R743 0_0402_5%
IDE_IOR#

SERIAL ATA

R742

R635
SATA_DTX_C_SRX_P0 0.01U_0402_16V7K 1 2 C564 SATA_DTX_SRX_P0 AJ20 AC28 @ 2 1 CRT_DET_R CRT_DET_R 18
23 SATA_DTX_C_SRX_P0 SATA_RX0+ IDE_IOW#
SATA_DTX_C_SRX_N0 0.01U_0402_16V7K 1 2 C565 SATA_DTX_SRX_N0 AH20 W28 @
23 SATA_DTX_C_SRX_N0 SATA_RX0- IDE_CS1#
AJ17 W27

1
SATA_RX1+ IDE_CS3#
AH17 SATA_RX1-
SATA_DTX_C_SRX_P2 0.01U_0402_16V7K 1 2 C670 SATA_DTX_SRX_P2 AJ16 AD28 TP10 PAD CRT_DET
23 SATA_DTX_C_SRX_P2 SATA_RX2+ IDE_D0/GPIO15
SATA_DTX_C_SRX_N2 0.01U_0402_16V7K 1 2 C667 SATA_DTX_SRX_N2 AH16 AD26 TP11 PAD
23 SATA_DTX_C_SRX_N2 SATA_RX2- IDE_D1/GPIO16

1
TP12 PAD D
+3VS
AJ13 SATA_RX3+ IDE_D2/GPIO17 AE29 High: CRT Plugged
AH12 AF27 TP13 PAD 2
SATA_RX3- IDE_D3/GPIO18 24 CRT_DET#
AG29 TP14 PAD G Q38
R462 2 IDE_D4/GPIO19
Change Y2 from SJ125POM780(KDS) as 1 1K_0402_1% SATA_CAL AF12 AH28 TP15 PAD S 2N7002_SOT23-3

3
SATA_CAL IDE_D5/GPIO20

1
AJ28 TP16 PAD

P-ATA 66/100
SJ125POM200(TXC) (2006/08/31) R146 SATA_X1 IDE_D6/GPIO21
1 2 C544 AD16 SATA_X1 IDE_D7/GPIO22 AJ27 TP17 PAD
10K_0402_5% 2.2U_0603_6.3V6K AH27 TP18 PAD
SATA_X2 IDE_D8/GPIO23 TP19 PAD
C297 @ AD18 AG27
SATA_X2 IDE_D9/GPIO24 TP20 PAD @
AG28

2
SATA_X1 SATA_LED# SATA_ACT# IDE_D10/GPIO25 TP21 PAD
1 2 38 SATA_LED# 2 1 AC12 SATA_ACT#/GPIO67 IDE_D11/GPIO26 AF28 +3VALW 2 1
R143 0_0402_5% SATA ACTIVITY LED AF29 TP22 PAD D30 RB751V_SOD323
IDE_D12/GPIO27
1

OSC / RST
R176 10P_0402_50V8J AE28 TP23 PAD
Y2 A_RST# R178 1 IDE_D13/GPIO28
2 33_0402_5% AG10 A_RST# IDE_D14/GPIO29 AD25 TP24 PAD
10M_0402_5% 25MHZ_20P RSMRST# E2 AD29 TP25 PAD SB600SPI@ SB600SPI@
28 RSMRST# RSMRST# IDE_D15/GPIO30
SB_OSCIN B23 +3VALW 2 1 1 2
C295 17 SB_OSCIN
2

14M_OSC SB_SI_SPI_SO
J3
2

SATA_X2 SPI_DI/GPIO12 SB_SO_SPI_SI R734 0_0603_5% C761 0.1U_0402_16V4Z


1 2 SPI_DO/GPIO11 J6
CLK_USB_48M A17 G3 SB_SPICLK

SPI ROM
17 CLK_USB_48M USBCLK SPI_CLK/GPIO47
10P_0402_50V8J G2 SB_HOLD# SB600SPI@ +SB_SPI_VCC
SPI_HOLD#/GPIO31 SB_SPICS#
2 1 A14 USB_RCOMP SPI_CS#/GPIO32 G6

1K_0402_5%

10K_0402_5%

10K_0402_5%
R164 11.8K_0402_1%

2
C C
2005/12/30 Change net to +3VALW A10 USB_ATEST0 LAN_RST#/GPIO13 C23

SB600SPI@

SB600SPI@
A11 USB_ATEST1 ROM_RST#/GPIO14 G5

31 USB20_P9 USB20_P9 H12


+3VALW R174 10K_0402_5% Camera USB20_N9 USB_HSDP9+
31 USB20_N9 G12 M4

1
USB_HSDM9- FANOUT0/GPIO3
1 2 E12 USB_HSDP8+ FANOUT1/GPIO48 T3

R735

R736

R737
D12 V4 U47
USB_HSDM8- FANOUT2/GPIO49

USB INTERFACE
E14 SB_SPICS# 1 8
C296 USB_HSDP7+ SB_GPIO50 CE# VDD SB_SPICLK
D14 USB_HSDM7- FANIN0/GPIO50 N3 3 WP# SCK 6
1 2 0.1U_0402_16V4Z 38 USB20_P6 USB20_P6 G14 P2 SB_GPIO51 SB_HOLD# 1 @ 2 7 5 SB_SO_SPI_SI
USB_HSDP6+ FANIN1/GPIO51 HOLD# SI
EXT USB CONN_4 38 USB20_N6 USB20_N6 H14 USB_HSDM6- FANIN2/GPIO52 W4 SB_GPIO52 R738 0_0402_5% 4 VSS SO 2 SB_SI_SPI_SO
D16 USB_HSDP5+
5
1

E16 P5 MX25L8005M2C-15G_SOP8
USB20_P4 USB_HSDM5- TEMP_COMM SB600SPI@
D18 P7
P
OE#

38 USB20_P4 USB_HSDP4+ TEMPIN0/GPIO61


A_RST# 2 A Y 4 NB_RST# NB_RST# 14,26,28,31 EXT USB CONN_3 38 USB20_N4 USB20_N4 E18 USB_HSDM4- TEMPIN1/GPIO62 P8 SB_GPIO62
31 USB20_P3 USB20_P3 G16 T8 SB_GPIO63
USB_HSDP3+ TEMPIN2/GPIO63
G

U15 Mini card 31 USB20_N3 USB20_N3 H16 USB_HSDM3- TEMPIN3/TALERT#/GPIO64 T7 EC_THERM#


EC_THERM# 8,28
2

HW MONITOR
74LVC1G125GW_SOT353-5 34 USB20_P2 USB20_P2 G18
3

R570 USB20_N2 USB_HSDP2+ SB_GPIO53


USB CONN_2 34 USB20_N2 H18 USB_HSDM2- VIN0/GPIO53 V5
R177 D19 L7 SB_GPIO54
8.2K_0402_5% 47K_0402_5% USB_HSDP1+ VIN1/GPIO54 SB_GPIO55
E19 USB_HSDM1- VIN2/GPIO55 M8
34 USB20_P0 USB20_P0 G19 V6 SB_GPIO56
1

USB CONN_1 USB20_N0 USB_HSDP0+ VIN3/GPIO56 SB_GPIO57


34 USB20_N0 H19 USB_HSDM0- VIN4/GPIO57 M6
P4 SB_GPIO58
USB_OC#0 VIN5/GPIO58 SB_GPIO59 +3VS
34 USB_OC#0 A8 USB_OC0#/GPM0# VIN6/GPIO59 M7
B8 V7 SB_GPIO60 JAQ60 unpop
USB_OC#2 USB_OC1#/GPM1# VIN7/GPIO60
2006/05/26 Change as SA411250200 from SA411250130 34 USB_OC#2 C7 USB_OC2#/GPM2#

USB OC
C8 N2 SB_AZ_BITCLK @
USB_OC3#/GPM3# AZ_BITCLK

AZALIA
R506 2 1 0_0402_5% USB_OC#4 A6 M2 SB_AZ_SDOUT R180 2 1 10K_0402_5% EC_THERM#
28 EC_LID_OUT# USB_OC4#/GPM4# AZ_SDOUT
B6 USB_OC5#/DDR3_RST#/GPM5# AZ_SDIN3/GPIO46 K2
B R474 2 1 @ 10K_0402_5% ACZ_SDIN0 B4 L3 SB_AZ_SYNC R424 2 1 2.2K_0402_5% SB_CK_SCLK B
R358 @ 10K_0402_5% ACZ_SDIN1 EC_SMI# USB_OC6#/GEVENT6# AZ_SYNC SB_AZ_RST# R430 2 SB_CK_SDAT
2 1 28 EC_SMI# C4 USB_OC7#/GEVENT7# AZ_RST# K3 1 2.2K_0402_5%
R485 @ 10K_0402_5% ACZ_SDIN2
R334
2
2
1
1 @ 10K_0402_5% SB_AC_BITCLK
PVT CRT_DET_R
PVT C5
C6
USB_OC8#/AZ_DOCK_RST#/GPM8#
L1 SB_AC_BITCLK
USB_OC9#/SLP_S2/GPM9# AC_BITCLK/GPIO38 SB_AC_SDOUT
BALLS(C6 AND C5) ARE FOR SB600 ONLY (NC FOR SB460) AC_SDOUT/GPIO39 L2 SB_AC_SDOUT 22
@ CRT_DET A27 L4 ACZ_SDIN0

AC97
SSMUXSEL/SATA_IS3#/GPIO0 ACZ_SDIN0/GPIO42 ACZ_SDIN0 39
2 1 A26 J2 ACZ_SDIN1 ACZ_SDIN1 38
R578 10K_0402_5% ROM_CS#/GPIO1 ACZ_SDIN1/GPIO43 ACZ_SDIN2
SB600 A21 and newer: Made provision for an external 39 SB_SPKR B26 SPKR/GPIO2 ACZ_SDIN2/GPIO44 J4
SB_GPIO4 B27 M3 SB_GPIO63 R704 1 2 10K_0402_5%
10-kohm 5% pull-down resistor, not installed by default. SB_GPIO5 D23
SMARTVOLT/SATA_IS2#/GPIO4 AC_SYNC/GPIO40
L5 SB_AC_RST# @
SHUTDOWN#/GPIO5 AC_RST#/GPIO45

GPIO/ SMBUS
SB_GPIO6 B29 SB_GPIO62 R705 1 2 10K_0402_5%
@ SB_GPIO7 GHI#/SATA_IS1#/GPIO6 @
A23 WD_PWRGD/GPIO7
R298 2 1 10K_0402_5% SB_AZ_RST# SB_GPIO8 C26 E23 SB_GPIO60 R706 1 2 10K_0402_5%
R296 @ 10K_0402_5% SB_AZ_SYNC SB_GPIO9 DDC1_SDA/GPIO8 NC1 @
2 1 D26 DDC1_SCL/GPIO9 NC2 AC21
R294 @ 10K_0402_5% SB_AZ_SDOUT SB_GPIO10 SB_GPIO59 R707 1 2 10K_0402_5%
R333
2
2
1
1 @ 10K_0402_5% SB_AZ_BITCLK
PVT CRT_DET_R
C28
A4
SATA_IS0#/GPIO10 NC3 AD7
AE7 @
R489 @ 10K_0402_5% SB_AC_RST# LLB#/GPIO66 NC4 SB_GPIO58 R708 1
2 1 NC5 AA4 2 10K_0402_5%
SB_CK_SCLK C27 T4 @
10,11,17,31 SB_CK_SCLK SCL0/GPOC0# NC6
SB_CK_SDAT B28 D4 SB_GPIO57 R709 1 2 10K_0402_5%
10,11,17,31 SB_CK_SDAT SDA0/GPOC1# NC7
AB19 @
SB_GPOC2# NC8 SB_GPIO56 R710 1
JAQ60 pop C3 SCL1/GPOC2# 2 10K_0402_5%
+3VS @ SB_GPOC3# F3 @
R142 2 SDA1/GPOC3#
1 10K_0402_5% SB_GPIO6 SB_GPIO55 R711 1 2 10K_0402_5%
@
JAQ60 unpop SB_GPIO54 R712 1 2 10K_0402_5%
R482 2 1 33_0402_5% SB_AZ_BITCLK @ 218S6ECLA13FG_FCBGA548_SB600 @
39 AZ_BITCLK
R713 2 1 10K_0402_5% SB_GPIO4 SB_GPIO53 R714 1 2 10K_0402_5%
R234 2 1 33_0402_5% @ SB600 : SA00001DUD0 / S IC 218S6ECLA21FG SB600 FCBGA 549P 0FA @
38 AC_BITCLK
R715 2 1 10K_0402_5% SB_GPIO5 SB_GPIO52 R716 1 2 10K_0402_5%
R505 2 1 33_0402_5% SB_AZ_SYNC @ @
A 39 AZ_SYNC A
R717 2 1 10K_0402_5% SB_GPIO7 SB_GPIO51 R718 1 2 10K_0402_5%
R236 2 1 33_0402_5% @ @
38 AC_SYNC
MDC@ R719 2 1 10K_0402_5% SB_GPIO8 SB_GPIO50 R720 1 2 10K_0402_5%
R175 2 1 33_0402_5% SB_AZ_RST# @ @
39 AZ_RST#
R721 2 1 10K_0402_5% SB_GPIO9
R483 2 1 33_0402_5% @
38 AC_RST#
R722 2 1 10K_0402_5% SB_GPIO10
R235 2 MDC@ 1 33_0402_5% SB_AZ_SDOUT @ Security Classification Compal Secret Data
39 AZ_SDOUT
R723 2 1 10K_0402_5% SB_GPOC2# 2005/03/08 2006/03/08 Title
R233 2
Issued Date Deciphered Date
38 AC_SDOUT 1 33_0402_5% @ SB600-SATA/GPIO/USB/AUDIO
MDC@ R724 2 1 10K_0402_5% SB_GPOC3#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 19 of 50
5 4 3 2 1
5 4 3 2 1

+3VS XTLVDD_ATA
+1.2V_HT
PLLVDD_ATA

L47 L13
1 2 1 2
MBC1608121YZF_0.4ohm/300mA_0603 1 MBC1608121YZF_0.4ohm/300mA_0603 1 1

1U_0402_6.3V4Z

1U_0402_6.3V4Z
C534 C293 C291
C534 CLOSE TO THE
BALL OF U18 1U_0402_6.3V4Z
2 2 2
D D

+1.2V_HT
AVDD_SATA
L45
1 2 PLLVDD_ATA=65mA U18D

KC FBM-L11-201209-221LMAT_0.04ohm/3A_0805
1
C539
1
C529
1
C522
1
C543
1
C524 AD14
SB600 SB AB14
PLLVDD_ATA PLLVDD_SATA_1 AVSS_SATA_1
AJ10 PLLVDD_SATA_2 AVSS_SATA_2 AB16
22U_0805_6.3V6M 1U_0402_6.3V4Z XTLVDD_ATA=5mA AB18
07/10 Modify same as HCW50 2 2 2 2 2 AVSS_SATA_3
XTLVDD_ATA AC16 XTLVDD_SATA AVSS_SATA_4 AC14
0.1U_0402_16V4Z 1U_0402_6.3V4Z AC18
0.1U_0402_16V4Z AVSS_SATA_5
AVDD_SATA=300mA AVSS_SATA_6 AC19

SATA Analog PWR


AVDD_SATA AE14 AVDD_SATA_1 AVSS_SATA_7 AD12
AE16 AVDD_SATA_2 AVSS_SATA_8 AD19
AE18 AVDD_SATA_3 AVSS_SATA_9 AD21
AE19 AVDD_SATA_4 AVSS_SATA_10 AE12
AF19 AVDD_SATA_5 AVSS_SATA_11 AE21
AF21 AVDD_SATA_6 AVSS_SATA_12 AF11
AG22 AVDD_SATA_7 AVSS_SATA_13 AF14
AG23 AVDD_SATA_8 AVSS_SATA_14 AF16
AH22 AVDD_SATA_9 AVSS_SATA_15 AF18
AH23 AVDD_SATA_10 AVSS_SATA_16 AG11
AJ12 AVDD_SATA_11 AVSS_SATA_17 AG12
AJ14 AVDD_SATA_12 AVSS_SATA_18 AG13
AJ19 AVDD_SATA_13 AVSS_SATA_19 AG14
Change L46 from SM010014500 as AJ22 AVDD_SATA_14 AVSS_SATA_20 AG16
+3VALW AVDD_USB AJ23 AG17
L46
SM010014520 (2006/08/31) AVDD_SATA_15 AVSS_SATA_21
AVDDTX=250mA AVSS_SATA_22 AG18
2 1 B9 AVDDTX_0 AVSS_SATA_23 AG19
C C
1 1 1 1 1 1 1 1 AVDDRX=250mA B11 AVDDTX_1 AVSS_SATA_24 AG20
KC FBM-L11-201209-221LMAT_0.04ohm/3A_0805 C545 C525 C284 C546 C537 C542 C535 C533 B13 AG21
AVDDTX_2 AVSS_SATA_25

USB Analog PWR


B16 AVDDTX_3 AVSS_SATA_26 AH10
0.1U_0402_16V4Z 22U_0805_6.3V6M B18 AH19
2 2 2 2 2 2 2 2 AVDDTX_4 AVSS_SATA_27
A9 AVDDRX_0
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z B10
0.1U_0402_16V4Z 1U_0402_6.3V4Z 10U_0805_10V4Z AVDDRX_1
B12 AVDDRX_2 AVSS_USB_1 A16
B14 AVDDRX_3 AVSS_USB_2 C9
Change L12 from SM010014500 as B17 AVDDRX_4 AVSS_USB_3 C10
+3VALW +3.3V_AVDDC C11
L12
SM010014520 (2006/08/31) AVSS_USB_4
+3.3V_AVDDC=15mA AVSS_USB_5 C12
2 1 A12 AVDDC AVSS_USB_6 C13
1 1 1 AVSS_USB_7 C14
MBC1608121YZF_0.4ohm/300mA_0603 C292 C286 A13 C16
+1.2VALW AVSSC AVSS_USB_8

USB PHY Digi. PWR


C294 C17
1U_0402_6.3V4Z AVSS_USB_9
A18 USB_PHY_1.2V_1 AVSS_USB_10 C18
2 2 2
A19 USB_PHY_1.2V_2 AVSS_USB_11 C19
PLACE C286 AND 0.1U_0402_16V4Z B19 C20
2.2U_0603_6.3V6K USB_PHY_1.2V_3 AVSS_USB_12
C294 CLOSE TO B20 USB_PHY_1.2V_4 AVSS_USB_13 D11
U18 USB_PHY_1.2V=90mA +AVDD
B21 USB_PHY_1.2V_5 AVSS_USB_14 D21
AVSS_USB_15 E11
AVSS_USB_16 E21
AVDD=1mA N1 AVDD AVSS_USB_17 F11
AVSS_USB_18 F12
M1 HW Monitor PWR F14
CPU_PWR=1.2V WHEN SB460 +1.8VS AVSS AVSS_USB_19
AVSS_USB_20 F16
AVSS_USB_21 F18
CPU_PWR=10mA AVSS_USB_22 F19
AA27 CPU_PWR AVSS_USB_23 F21

Special PWR/GND
B
V5_VREF=5mA AVSS_USB_24 G11
B
+5VS R173 2 1 V5_VREF AE11 G21
1K_0402_5% V5_VREF AVSS_USB_25
+AVDDCK_3.3V=10mA AVSS_USB_26 H11
+3VS 1 +AVDDCK_3.3V A24 AVDDCK_3.3V AVSS_USB_27 H21
+AVDDCK_1.2V J11
D6 AVSS_USB_28
A22 AVDDCK_1.2V AVSS_USB_29 J12
2 1 @ C764 2 2 J14
2 1U_0402_6.3V4Z AVSS_USB_30
B22 AVSSCK AVSS_USB_31 J16
C520 C298 J18
CH751H-40PT _SOD323 AVSS_USB_32
AVSS_USB_33 J19
0.1U_0402_16V4Z 1 1 1U_0402_6.3V4Z

VCC_SB=1.2V WHEN SB600 PVT


VCC_SB 1.8V WHEN SB460 2006/4/13 modify 218S6ECLA13FG_FCBGA548_SB600
+AVDDCK_1.2V=40mA

SB600 : SA00001DUD0 / S IC 218S6ECLA21FG SB600 FCBGA 549P 0FA


PLACE SATA_CAL
RES & CAP VERY
CLOSE TO BALL For AMD recommend change to +3.3V_S5
L72 L73
OF U18 @ L71 +3VS 1 2 +AVDDCK_3.3V +1.2V_HT 1 2 +AVDDCK_1.2V
+1.2VALW 1 2
+3VALW +AVDD
MBC1608121YZF_0.4ohm/300mA_0603 MBC1608121YZF_0.4ohm/300mA_0603
NOTE: C361 2 1 1U_0402_6.3V4Z MBC1608121YZF_0.4ohm/300mA_0603 C692 1 2 2.2U_0603_6.3V4Z C693 1 2 2.2U_0603_6.3V4Z
R462 IS 1K 1% FOR 25MHz C364 2 1 1U_0402_6.3V4Z C694 1 2 2.2U_0603_6.3V4Z
C365 2 1 1U_0402_6.3V4Z @ C695 1 2 0.1U_0402_16V4Z C696 1 2 0.1U_0402_16V4Z
XTAL, 4.99K 1% FOR 100MHz C367 2 1 1U_0402_6.3V4Z C697 1 2 0.1U_0402_16V4Z
INTERNAL CLOCK @ GND to B22 GND to B22
A A
GND to M1

Security Classification Compal Secret Data


Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
SB600-PWR & GND I
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 24, 2008 Sheet 20 of 50
5 4 3 2 1
5 4 3 2 1

+1.2VALW +3VS
VDDQ=150mA U18C
A25 VDDQ_1
C750 0.1U_0402_16V4Z
C752
2
2
1
1 0.1U_0402_16V4Z
A28
C29
VDDQ_2 SB600 SB A20
C753 0.1U_0402_16V4Z VDDQ_3 VSS_2
2 1 D24 A21
C751 2 1 0.1U_0402_16V4Z L9
VDDQ_4
VDDQ_5
POWER VSS_3
VSS_4 A29
C754 2 1 10U_0805_10V4Z L21 B1
@ VDDQ_6 VSS_5
M5 VDDQ_7 VSS_6 B7
D P3 B25 D
VDDQ_8 VSS_7
P9 VDDQ_9 VSS_8 C21
T5 VDDQ_10 VSS_9 C22
V9 VDDQ_11 VSS_10 C24
W2 VDDQ_12 VSS_11 D6

3.3V I/O PWR


W6 VDDQ_13 VSS_12 E24
W21 VDDQ_14 VSS_13 F2
W29 VDDQ_15 VSS_14 F23
AA12 VDDQ_16 VSS_15 G1
AA16 VDDQ_17 VSS_16 J1
+3VS +3VALW AA19 J8
C513 VDDQ_18 VSS_17
AC4 VDDQ_19 VSS_18 L6
220U_D2_4VM_R15 AC23 L8
VDDQ_20 VSS_19
1 1 1 1 AD27 VDDQ_21 VSS_20 M9
1 1 1 1 1 1 C555 C558 AE1 M12
+ C521 C526 C523 C518 C519 C517 VDDQ_22 VSS_21
AE9 VDDQ_23 VSS_22 M15
C563 AE23 M18
2 22U_0805_6.3V6M
2 2 VDDQ_24 VSS_23
AH29 VDDQ_25 VSS_24 N13
2 2 2 2 2 2 2 0.1U_0402_16V4Z AJ2 VDDQ_26 VSS_25 N17
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z AJ6 P1
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z +1.2VS_SB_VDD VDDQ_27 VSS_26
AJ26 VDDQ_28 VSS_27 P6
VSS_28 P21
M13 VDD_1 VSS_29 R12
M17 VDD_2 VSS_30 R15
N12 VDD_3 VSS_31 R18

Core PWR
N15 VDD_4 VSS_32 T6
N18 VDD_5 VSS_33 T9
R13 VDD_6 VSS_34 U13
R17 VDD_7 VSS_35 U17
U12 VDD_8 VSS_36 V3
C C
+1.2VS_SB_VDD=500mA U15 VDD_9 VSS_37 V8
L74 U18 V12
VDD_10 VSS_38
+1.2V_HT 1 2 +1.2VS_SB_VDD V13 VDD_11 VSS_39 V15
KC FBM-L11-201209-221LMAT_0.04ohm/3A_0805 +3VALW V17 V18
VDD_12 VSS_40
S5_3.3V=15mA VSS_41 V21
A2 S5_3.3V_1 VSS_42 W1
C698 1 2 22U_0805_6.3V6M A7 W9
S5_3.3V_2 VSS_43
F1 S5_3.3V_3 VSS_44 Y29
C699 1 2 1U_0402_6.3V4Z J5 3.3V Standby PWR AA11
C700 1U_0402_6.3V4Z S5_3.3V_4 VSS_45
1 2 J7 S5_3.3V_5 VSS_46 AA14
C701 1 2 1U_0402_6.3V4Z +1.2VALW K1 AA18
C702 1U_0402_6.3V4Z S5_3.3V_6 VSS_47
1 2 S5_1.2V=80mA VSS_48 AC6
C703 1 2 0.1U_0402_16V4Z G4 AC24
S5_1.2V_1 VSS_49
H1 S5_1.2V_2 VSS_50 AD9
C704 1 2 0.1U_0402_16V4Z H2 1.2V Standby PWR AD23
S5_1.2V_3 VSS_51
H3 S5_1.2V_4 VSS_52 AE3
PCIE_VDDR=450mA VSS_53 AE27
VSS_54 AG6
PCIE_VDDR F27 PCIE_VDDR_1 VSS_55 AJ1
F28 PCIE_VDDR_2 VSS_56 AJ25
F29 PCIE_VDDR_3 VSS_57 AJ29
G26 PCIE_VDDR_4

PCIE Analog PWR


G27 PCIE_VDDR_5
G28 PCIE_VDDR_6
+1.2VS_SB_VDD G29 PCIE_VDDR_7
J27 PCIE_VDDR_8 PCIE_VSS_1 D27
PCIE_VDDR J29 D28
L7 PCIE_VDDR_9 PCIE_VSS_2
L25 PCIE_VDDR_10 PCIE_VSS_3 D29
1 2 L26 PCIE_VDDR_11 PCIE_VSS_4 F26
MBK2012121YZF_0.2ohm/800mA_08051 1 1 1 1 1 L29 G23
B C515 C516 C512 C247 C250 C514 PCIE_VDDR_12 PCIE_VSS_5 B
N29 PCIE_VDDR_13 PCIE_VSS_6 G24
+PCIE_PVDD=35mA PCIE_VSS_7 G25
22U_0805_6.3V6M 0.1U_0402_16V4Z +PCIE_PVDD U29 H27
2 2 2 2 2 2 PCIE_PVDD PCIE_VSS_8
PCIE_VSS_9 J23
1U_0603_10V6K 1U_0603_10V6K U28 J26
1U_0603_10V6K 0.1U_0402_16V4Z PCIE_PVSS PCIE_VSS_10
PCIE_VSS_11 J28
PCIE_VSS_12 K27
V29 PCIE_VSS_42 PCIE_VSS_13 L22
V28 PCIE_VSS_41 PCIE_VSS_14 L23
V27 PCIE_VSS_40 PCIE_VSS_15 L24
V26 PCIE_VSS_39 PCIE_VSS_16 L27
V25 PCIE_VSS_38 PCIE_VSS_17 L28
L75 V24 M21
PCIE_VSS_37 PCIE_VSS_18
+1.2VS_SB_VDD 2 1 +PCIE_PVDD V23 PCIE_VSS_36 PCIE_VSS_19 M24
MBK2012601YZF_0.4ohm/500mA_0805 V22 M27
PCIE_VSS_35 PCIE_VSS_20
U27 PCIE_VSS_34 PCIE_VSS_21 N27
C705 1 2 1U_0402_6.3V4Z T29 N28
C706 1 10U_0805_10V6M PCIE_VSS_33 PCIE_VSS_22
2 T28 PCIE_VSS_32 PCIE_VSS_23 P22
T27 PCIE_VSS_31 PCIE_VSS_24 P23
T24 PCIE_VSS_30 PCIE_VSS_25 P24
GND to U28 T21 PCIE_VSS_29 PCIE_VSS_26 P25
P27 PCIE_VSS_28 PCIE_VSS_27 P26

218S6ECLA13FG_FCBGA548_SB600

SB600 : SA00001DUD0 / S IC 218S6ECLA21FG SB600 FCBGA 549P 0FA

A A

Security Classification Compal Secret Data


Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
SB600-PWR & GND II
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 24, 2008 Sheet 21 of 50
5 4 3 2 1
5 4 3 2 1

NOTE: R473 PU RESISTOR FOR


REQUIRED STRAPS RTC_IRQ# IS REQUIRED FOR SB600
SB600 HAS 15K INTERNAL PD FOR AC_SDATA_OUT, TO KEEP THE INPUT FROM FLOATING.
15K PU FOR RTC_CLK, EXTERNAL PU/PD IS
NOT REQUIRED; FOR SB460, EXTERNAL PU/PD ARE +3VALW
REQUIRED

1
D +3VS +3VALW +3VS +3VS +3VS +3VS R473 D
10K_0402_5%

2
R499
18 RTC_IRQ#
2.2K_0402_5%

1
@
R202 R249 R248 R496 R497

2
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
19 SB_AC_SDOUT
@ @ @

1
18 RTC_CLK
R469
18 CLK_PCI_1394_R
10K_0402_5%
18 PCI_CLK6
@
18 CLK_PCI_LAN_R

2
18 CLK_PCI_LPC_R
1

1
R494 R245 R504 R492 SB460 ONLY
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
@ @
2

2
ACPWRON SPDIF_OUT PCI_MINI_R PCI_PCM_R PCI_SIO_R LFRAME#

PULL MANUAL SIO 24MHz XTAL MODE USB PHY PCIE_CM_SET ENABLE
SB600 SB460 HIGH PWR ON POWERDOWN LOW THERMTRIP#
NOT
C SUPPORTED DISABLE C

AC_SDOUT RTC_CLK PCI_1394_R PCI_CLK6 PCI_LAN_R PCI_LPC_R PCI_LAN_R PCI_LPC_R DEFAULT DEFAULT DEFAULT DEFAULT

PULL USE INTERNAL USE INT. CPU IF=K8 ROM TYPE: ROM TYPE: PULL AUTO SIO 48MHz 48MHZ OSC USB PHY PCIE_CM_SET DISABLE
HIGH DEBUG RTC PLL48 LOW PWR MODE POWERDOWN HIGH THERMTRIP#
H, H = PCI ROM H, H = PCI ROM
STRAPS DEFAULT ON ENABLE
DEFAULT H, L = SPI ROM H, L = LPC I ROM DEFAULT DEFAULT DEFAULT

L, H = LPC ROM DEFAULT L, H = LPC II ROM


PULL IGNORE EXTERNAL USE EXT. CPU IF=P4
LOW DEBUG RTC 48MHZ L, L = FWH ROM L, L = FWH ROM
STRAPS NOTE: FOR SB460, PCICLK[8:7] ARE
DEFAULT DEFAULT CONNECTED TO SUBSTRATE
BALLS PCICLK[1:0] OVERLAP COMMON PADS WHERE
POSSIBLE FOR DUAL-OP RESISTORS.
DEBUG STRAPS
SB600 HAS 15K INTERNAL PU FOR PCI_AD[28:23]
+3VS +3VS +3VS +3VS +3VS +3VS
1

R215 R211 R220 R188 R239 R196


10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
B @ @ B
@ @ @ @
+3VS
2

18 PCI_AD28

2
18 PCI_AD27 1
C302 R198
18 PCI_AD26
0.1U_0402_16V4Z 1K_0402_5%
18 PCI_AD25
@ @ U20
18 PCI_AD24 2
18 PCI_AD23 8 1

1
VCC A0
7 WP A1 2
1

2.2K IF USED FOR SB600. R199 1 2 0_0402_5% @ 6 3


18 PCI_GNT#4 SCL A2
R217 R213 R222 R190 R242 R195 R200 1 2 0_0402_5% @ 5 4
18 PCI_REQ#4 SDA VSS
2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 10K IF USED FOR SB460.
@ @ @ @ @ @ AT24C04N-10SI-2.7_SO8
SB600 = PCI REQ4#/GNT4# @
2

SB460 = GPIO13 (NC3), GPIO14 (NC5)


IDE_DACK# PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23
SB PCIE EEPROM STRAPS
USE USE USE PCI USE ACPI USE IDE USE DEFAULT BOOTFAILTIMER
PULL LONG LONG PLL BCLK PLL PCIE STRAPS DISABLED SB600 ONLY
HIGH RESET RESET
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT

NOTE: FOR
PULL USE USE BYPASS BYPASS BYPASS IDE USE EEPROM BOOTFAILTIMER SB460,
A A
LOW SHORT SHORT PCI PLL ACPI PLL PCIE STRAPS ENABLED PCI_AD23 IS
RESET RESET BCLK RESERVED

SB460 ONLY SB600 ONLY Security Classification Compal Secret Data


Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
SB600-STRAPS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 22 of 50
5 4 3 2 1
5 4 3 2 1

D D

+5VS +3VS
+5VS

0.1U_0402_16V4Z 0.1U_0402_16V4Z
Placea caps. near ODD CONN.
0.1U_0402_16V4Z
1 1 1 1 1 1 1 1
C351 C349 C347 C346 1 1 1 1
C360
C363 C366 C368 C150 C149
10U_0805_10V4Z 10U_0805_10V4Z C153 C148
2 2 2 2 2 2 2 2 10U_0805_10V4Z
2 2 2 2
0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z 1000P_0402_50V7K 1U_0402_6.3V4Z
1000P_0402_50V7K

C C

SATA HDD CONN SATA ODD CONN

JSATA1

1 JSATA2
SATA_STX_C_DRX_P0 GND
19 SATA_STX_C_DRX_P0 2 HTX+
SATA_STX_C_DRX_N0 3 1
19 SATA_STX_C_DRX_N0 HTX- SATA_STX_C_DRX_P2 GND
4 GND 19 SATA_STX_C_DRX_P2 2 A+
SATA_DTX_C_SRX_N0 5 +5VS SATA_STX_C_DRX_N2 3
19 SATA_DTX_C_SRX_N0 HRX- 19 SATA_STX_C_DRX_N2 A-
SATA_DTX_C_SRX_P0 6 4
19 SATA_DTX_C_SRX_P0 HRX+ SATA_DTX_C_SRX_N2 GND
7 GND 1 19 SATA_DTX_C_SRX_N2 5 B-
C370 SATA_DTX_C_SRX_P2 6
+ 19 SATA_DTX_C_SRX_P2 B+
7 GND
@
+3VS 1 2 8 VCC3.3
L16 0_0805_5% 150U_D2_6.3VM 2
9 VCC3.3 1 2 8 DP
10 R617 @ 1K_0402_1% 9
VCC3.3 +5V
11 GND +5VS 10 +5V
12 GND 11 MD
13 GND 12 GND GND 15
+5VS 1 2 14 VCC5 13 GND GND 14
L17 0_0805_5% 15 Close to SATA HDD
VCC5
16 VCC5
17 SANTA_206401-1_13P
B GND CONN@ B
18 RESERVED
19 GND
20 VCC12
07/10 Modify same as HCW50 21 VCC12
22 VCC12

OCTEK_SAT-22SG1G_NR
CONN@

A A

Security Classification Compal Secret Data


Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
HDD/CDROM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 23 of 50
5 4 3 2 1
A B C D E

CRT Connector D18 D20 D19


@ DAN217_SC59 @ DAN217_SC59 @ DAN217_SC59
+5VS +R_CRT_VCC
W=40mils
+CRT_VCC

D17 F1 W=40mils

1
2 1 1 2

CH411DPT_SOT23 1.1A_6VDC_FUSE
1
C407

3
0.1U_0402_16V4Z
2
+3VS

1 1

JCRT1
CRT_R 1 2 CRT_R_L 6
14 CRT_R
L32 11
FCM2012C-800_0805 1
CRT_G 1 2 CRT_G_L 7
14 CRT_G
L34 12
FCM2012C-800_0805 2
CRT_B 1 2 CRT_B_L 8
14 CRT_B
L33 13
FCM2012C-800_0805 3

1
1 1 1 1 1 1 DDC_MD2 9
R339 R338 R340 C408 C412 C414 14
C413 C409 4
6P_0402_50V8C 6P_0402_50V8C 10
150_0402_1% 150_0402_1% 2 8P_0402_50V8K 2 8P_0402_50V8K 2 2 2 2
15

2
8P_0402_50V8K C410 C406 5
150_0402_1% 10P for GMCH 6P_0402_50V8C 100P_0402_50V8J
SUYIN_070549FR015S208CR

16

17
+CRT_VCC HSYNC_L
1 2 (CL55) CONN@
L38 FCM1608C-121T_0603
1 2 2 1 D_DDC_DATA
C434 0.1U_0402_16V4Z R360 10K_0402_5% 1 2 VSYNC_L
L37 FCM1608C-121T_0603 1

5
1
1 1

OE#
P
CRT_DET# 19
VGA_CRT_HSYNC 1 2 CRT_HSYNC 2 4 D_CRT_HSYNC C424 C423
14 VGA_CRT_HSYNC A Y
R354 0_0402_5% 10P_0402_25V8K 10P_0402_25V8K C411 2

G
U36 68P_0402_50V8K D_DDC_CLK

2
SN74AHCT1G125GW_SOT353-5 2 2

3
1 R636
2 +CRT_VCC 2
100K_0402_5%
C422
1 2 68P_0402_50V8K

1
C433 0.1U_0402_16V4Z 2

5
1
PVT

OE#
P
VGA_CRT_VSYNC 1 2 CRT_VSYNC 2 4 D_CRT_VSYNC +CRT_VCC
14 VGA_CRT_VSYNC A Y
R356 0_0402_5%

G
U35
SN74AHCT1G125GW_SOT353-5

3
+CRT_VCC
R359 1 2 0_0402_5% +3VS

1
R355 R344
6.8K_0402_5% 6.8K_0402_5%

2
G
D_DDC_DATA 1 3 VGA_DDC_DATA
VGA_DDC_DATA 14

2
Q26

G
BSS138_SOT23 Q24
3 D_DDC_CLK 1 3 BSS138_SOT23 VGA_DDC_CLK 3
VGA_DDC_CLK 14

S
4 4

Security Classification Compal Secret Data


Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
CRT Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 24 of 50
A B C D E
5 4 3 2 1

LCD POWER CIRCUIT

D D

+LCDVDD +3VALW
1

2
R343
R341 +3VS
300_0603_1% 1K_0402_5%
W=60mils
1 2

R342

3
D S
G
Q22 2 2 1 2 Q23
2N7002_SOT23 G SI2301BDS_SOT23
S 1
3

100K_0402_5%
2
+LCDVDD
D W=60mils

1
R347 C431 +LCDVDD
2 0.047U_0402_16V7K LCD/PANEL CONN.
1

D 100K_0402_5% 1 1
1

ENVDD 2 C415 C420 04/17 modify


14 ENVDD
G
1

S 4.7U_0805_10V4Z 0.1U_0402_16V4Z L36


3

R345 Q25 2 2 FBMA-L11-201209-121LMA40T _0805 JLVDS1


10K_0402_5% 1 2 DAC_BRIG
B+ 40 20 DAC_BRIG 28
BSS138_SOT23 INVT_PWM
39 19 INVT_PWM 28
C FBMA-L11-201209-121LMA40T _0805 DISPOFF# C
2

L42 38 18
+3VS 1 2 37 17
14 EDID_LCD_CLK EDID_LCD_CLK L35 1 2 +LCDVDD
EDID_LCD_DAT 36 16 FBMA-L11-201209-121LMA40T _0805
14 EDID_LCD_DAT 35 15
LVDS_TXUN0 34 14 LVDS_TXLN0
14 LVDS_TXUN0 33 13 LVDS_TXLN0 14
LVDS_TXUP0 LVDS_TXLP0
14 LVDS_TXUP0 32 12 LVDS_TXLP0 14
+3VS +3VS LVDS_TXUP1 31 11 LVDS_TXLN1
14 LVDS_TXUP1 30 10 LVDS_TXLN1 14
LVDS_TXUN1 LVDS_TXLP1
14 LVDS_TXUN1 29 9 LVDS_TXLP1 14
28 8

1
1 LVDS_TXUP2 LVDS_TXLP2
14 LVDS_TXUP2 27 7 LVDS_TXLP2 14
R1 LVDS_TXUN2 LVDS_TXLN2
14 LVDS_TXUN2 26 6 LVDS_TXLN2 14
C426
@ 0.1U_0402_16V4Z 4.7K_0402_5% LVDS_TXUCKN 25 5 LVDS_TXLCKN
2 14 LVDS_TXUCKN 24 4 LVDS_TXLCKN 14
D2 LVDS_TXUCKP LVDS_TXLCKP
14 LVDS_TXUCKP LVDS_TXLCKP 14

2
BKOFF# 23 3
28 BKOFF# 1 2 CH751H-40PT _SOD323 DISPOFF#
22 2
21 1
ACES_88107-4000G
CONN@
INVT_PWM
1

1 (SAME AS ACES_87216-4016)
D21 C416
BAS16_SOT23-3 1U_0402_6.3V4Z @
@
2
2

B B
PVT EMI

C371 220P_0402_50V7K
DAC_BRIG 1 2
C372 220P_0402_50V7K
INVT_PWM 1 2
C377 220P_0402_50V7K
DISPOFF# 1 2

A A

Security Classification Compal Secret Data


Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
LCD Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 25 of 50
5 4 3 2 1
5 4 3 2 1

1 2 +3V_LAN
R640 3.6K_0402_5%
PVT Remove U11 & C707 (Embedded memory to replace ext. EEPROM)
SA000019910 / S IC EE 1K CAT93C46VI-GT3 SOIC 8P
U11
LAN_DO SA093461070 / S IC EE 1K SO-8 I AT93C46-10SI-2.7 (EOL)
4 DO GND 5 2
LAN_DI 3 6 C707
LAN_LINK# DI NC
2 SK NC 7
LAN_CS 1 8 +3V_LAN
CS VCC 1
0.1U_0402_16V4Z
@ CAT93C46VI-GT3_SO8 @

2 1
EFUSE R641 10K_0402_5%
D Place Close to Chip U12
D

C708 2 0.1U_0402_16V7K
1 PCIE_MRX_PTX_P1 20 33 LAN_DO
13 PCIE_MRX_C_PTX_P1 HSOP LED3/EEDO +LAN_VDD12
34 LAN_DI
C709 2 0.1U_0402_16V7K PCIE_MRX_PTX_N1 21 LED2/EEDI/AUX LAN_LINK#
13 PCIE_MRX_C_PTX_N1 1 HSON LED1/EESK 35 Close to Pin48 Close to Pin10,13,30,36
32 LAN_CS
EECS
13 PCIE_MTX_C_PRX_P1 15 HSIP
38 LAN_ACTIVITY#
LED0
13 PCIE_MTX_C_PRX_N1 16 HSIN 2 2 2 2
RTL8102EL 2 LAN_MDI0+ VCTRL12 0.1U_0402_16V4Z C710 C711 C712 C715
MDIP0 LAN_MDI0-
17 CLK_PCIE_LAN 17 REFCLK_P MDIN0 3
18 5 LAN_MDI1+ 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
17 CLK_PCIE_LAN# REFCLK_M MDIP1 1 1 1 1
6 LAN_MDI1- C714
MDIN1 C713
17 LAN_CLKREQ# 25 CLKREQB NC 8
9 @
NC 2 10U_0805_10V4Z 1
14,19,28,31 NB_RST# 27 PERSTB NC 11
NC 12
R515 0_0402_5% R642 2.49K_0402_1%
28 EC_PME# 2 1 1 2 46 RSET NC 4
R651 0_0402_5%
2 1 LAN_PME# 26 48 VCTRL12
18,31 SB_PCIE_WAKE# ISOLATEB LANWAKEB VCTRL12A
28 ISOLATEB
@ 19 +EVDD12
LAN_X1 VDDTX
+3VS
41 CKXTAL1 DVDD12 30 +LAN_VDD12 Close to Pin19
LAN_X2 42 36 LAN_ACTIVITY#
CKXTAL2 DVDD12 +EVDD12
DVDD12 13
10 LAN_LINK#
DVDD12
1

C R643 39 +LAN_VDD12 C
NC

2
1K_0402_1%
23 44 2 2 D27
NC NC +VDD_LAN +3V_LAN C717
24 45 PSOT24C_SOT23-3
2

ISOLATEB NC VCTRL12D L77 C716 @


7 29 1 2 1U_0402_6.3V4Z 0.1U_0402_16V4Z
GND VDD33 KC FBM-L11-201209-221LMAT_0.04ohm/3A_0805 1 1
14 37

1
GND VDD33
31 GND
R644 47 1
15K_0402_5% GND AVDD33
NC 40 EMI_PVT
22 GNDTX NC 43

PV:Add ESD diode for EMI request


RTL8102EL-GR_LQFP48_7X7 EMI_PVT
+VDD_LAN
Close to Pin45 Close to Pin1,37,29
R749 300_0402_5% JRJ45
LAN_ACTIVITY# 1 2 LAN_ACTIVITY#_R 12 Amber LED-
+LAN_VDD12 2 L78 1 11
2 2 2 +3V_LAN Amber LED+
C720 C718 C721 1 16
KC FBM-L11-201209-221LMAT_0.04ohm/3A_0805 SHLD4
8 PR4-
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C719 15
1 1 1 68P_0402_50V8K SHLD3
2 1 7 PR4+
2
C722 C723
EMI_PVT RJ45_MIDI1-
6 PR2-
0.1U_0402_16V4Z @ 10U_0805_10V4Z
1 2
B
short 5 PR3- B
PJP15 4 PR3+
1 2
+3VALW RJ45_MIDI1+ 3
PAD-OPEN 4x4m PR2+
RJ45_MIDI0- 2 PR1-
40 mils SHLD2 14
S

Y1 RJ45_MIDI0+
D

3 1 +3V_LAN 1 PR1+
LAN_X1 2 1LAN_X2 R750 300_0402_5% 13
SHLD1
2

2 LAN_LINK# 1 2 LAN_LINK#_R 10
@ Green LED-
25MHZ_20P @ R646
G
2

1 1 100K_0402_5% C725 Q39 2 1 L79 9


C255 C258 SI2301BDS-T1-E3_SOT23-3 +3V_LAN Green LED+
1
@ 1 KC FBM-L11-201209-221LMAT_0.04ohm/3A_0805 SUYIN_100073FR012S100ZL
1

27P_0402_50V8J 27P_0402_50V8J 28 LANPWR 1 2 C724 CONN@


2 2 R648 10K_0402_5% 0.1U_0402_16V4Z 68P_0402_50V8K HBL-50
@ 2
EMI_PVT
SI2: remove 100K ohm ,use EC pull high
EMI_PVT PVT
EMI_PVT LANGND
T1 1 1
C765 0.1U_0402_16V4Z
2 1 LAN_MDI0+ 1 16 RJ45_MIDI0+ C766 0.1U_0402_16V4Z C726 C727
LAN_MDI0- TD+ TX+ RJ45_MIDI0- 4.7U_0805_10V4Z
2 TD- TX- 15 1 2
R649 2 2
2 1 3 CT CT 14
C728 0.01U_0402_16V7K 4 13 C729 2 1 0.01U_0603_100V4Z 1 2 75_0402_1%
NC NC C730
5 NC NC 12 2 1 0.01U_0603_100V4Z 1 2 75_0402_1% RJ45_GND 1 2 0.1U_0402_16V4Z
C732 2 1 0.01U_0402_16V7K 6 11 R650 C731 1000P_1808_3KV7K
LAN_MDI1+ CT CT RJ45_MIDI1+
A 7 RD+ RX+ 10 A
2 1 LAN_MDI1- 8 9 RJ45_MIDI1-
RD- RX-
C767 0.1U_0402_16V4Z
BOTHHAND_NS0013LF

EMI_PVT Security Classification Compal Secret Data Compal Electronics, Inc.


SP050003N00 S X'FORM_ NS681680 LAN (MHPC , Not for ABO)
SP050001210 S X'FORM_ NS0013LF LAN (BOTHHAND) Issued Date 2005/07/29 Deciphered Date 2006/07/29 Title
SP050001310 S X'FORM_ LF-H80P-1 COUPLING (lankom)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN RTL8102EL & RJ45
SP050004L00 S X'FORM_ HD-024A 10/100 PC CARD LAN (TAIMAG) Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KAW60 LA-4661P
Date: Friday, August 08, 2008 Sheet 26 of 50
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/07/29 Deciphered Date 2006/07/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KAW60 LA-4661P
Date: Tuesday, June 17, 2008 Sheet 27 of 50
5 4 3 2 1
5 4 3 2 1

+3VALW

L48
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2 +EC_VCCA
1 1 C567 1 1 2 2 FBM-L11-160808-800LMT_0603
C569 1
C476 C557 C568 C561
1000P_0402_50V7K 1000P_0402_50V7K C566
2 2 2 2 1 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z BATT_OVP C672 1 100P_0402_50V8J
2

ECAGND
BATT_TEMP C673 1 2 100P_0402_50V8J
D
For EC Tools D
CLK_PCI_LPC

111
125
KSI[0..7]

22
33
96

67
29 KSI[0..7] Place on MiniCard
1

9
U27 +3VALW
R633 KSO[0..17] JP37

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
29 KSO[0..17]
@ 10_0402_5% 1
1 E51RXD_P80CLK
2 2 E51RXD_P80CLK 31
3 E51TXD_P80DATA
E51TXD_P80DATA 31
2

3
1 18 EC_GA20 1 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F 21 INVT_PWM 25 4 4
18 EC_KBRST# 2 KBRST#/GPIO01 BEEP#/PWM2/GPIO10 23 BEEP# 39
C689 3 26 ACES_85205-0400
18 SERIRQ SERIRQ# FANPWM1/GPIO12 EMPWR_BTN# 38
@ 22P_0402_50V8J 4 27 CONN@
2 18 LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF 42,44
18 LPC_AD3 5 LAD3
18 LPC_AD2 7 LAD2 PWM Output
8 63 BATT_TEMP
18 LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 45
BATT_OVP
18 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64 BATT_OVP 44
ADP_I/AD2/GPIO3A 65
+3VALW R632 POUT
18 CLK_PCI_LPC 12 PCICLK AD Input AD3/GPIO3B 66 POUT 48
47K_0402_5% 13 75
14,19,26,31 NB_RST# PCIRST#/GPIO05 AD4/GPIO42 E-MAIL_BTN# 38
2 1 ECRST# ECRST# 37 76 @ R656
ECRST# SELIO2#/AD5/GPIO43 IE_BTN# 38
18 EC_SCI# 20 SCI#/GPIO0E 1 2 0_0402_5%
2 1 18 PM_CLKRUN# 38 CLKRUN#/GPIO1D
C549 0.1U_0402_16V4Z 68 +3VALW
DAC_BRIG/DA0/GPIO3C DAC_BRIG 25
70 U45
EN_DFAN1/DA1/GPIO3D EN_DFAN1 6
DA Output 71 NC7SZ08P5X_NL_SC70-5
IREF/DA2/GPIO3E IREF 44

5
KSI0 55 72
KSI0/GPIO30 DA3/GPIO3F CALIBRATE# 44
+3VALW KSI1 56 R739 2

P
KSI2 KSI1/GPIO31 0_0402_5% B RSMRST#
57 KSI2/GPIO32 Y 4 RSMRST# 19
KSI3 58 83 EC_RSMRST# 1 2 1
KSI3/GPIO33 PSCLK1/GPIO4A A
2

G
C KSI4 59 84 C
KSI4/GPIO34 PSDAT1/GPIO4B

1
R514 KSI5 60 85 E-MAIL_LED# 38 1

3
10K_0402_5% KSI6 KSI5/GPIO35 PSCLK2/GPIO4C R657
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86
KSI7 62 87 TP_CLK @ C762 R740 @ 10K_0402_5%
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK 29
KSO0 39 88 TP_DATA 0.1U_0402_16V4Z 10K_0402_5%
TP_DATA 29
1

KSO1 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 2


40

2
KSO2 KSO1/GPIO21
41 KSO2/GPIO22
EC_PME# KSO3 42 97 LANPWR
KSO3/GPIO23 SDICS#/GPXOA00 LANPWR 26
KSO4 43 98 WLSW_EN#
KSO4/GPIO24 SDICLK/GPXOA01 WLSW_EN# 38
KSO5 S3_STATE
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
VGATE
S3_STATE 18
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 VGATE 48
KSO7 46 SPI Device Interface
+3VALW KSO8 KSO7/GPIO27
47 KSO8/GPIO28
RP37 KSO9 48 119
KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO 30
1 8 IE_BTN# KSO10 49 120
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI 30
2 7 EMPWR_BTN# KSO11 50 SPI Flash ROM 126
E-MAIL_BTN# KSO12 KSO11/GPIO2B SPICLK/GPIO58 EC_SPICLK 30
3 6 51 KSO12/GPIO2C SPICS# 128 EC_SPICS#/FSEL# 30
4 5 USER_BTN# KSO13 52
KSO14 KSO13/GPIO2D
53 KSO14/GPIO2E
100K_1206_8P4R_5% KSO15 54 73
KSO15/GPIO2F CIR_RX/GPIO40 USB_EN# 34,38
KSO16 81 74
KSO16/GPIO48 CIR_RLC_TX/GPIO41 WL_OFF# 31
KSO17 82 89 FSTCHG
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG 44
BATT_CHGI_LED#/GPIO52 90 BATT_FULL_LED# 38
+3VALW 91
CAPS_LED#/GPIO53 CAPS_LED# 38
R729 2.2K_0402_5% EC_SMB_CK1 77 GPIO 92
30,45 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_CHGI_LED# 38
1 2 EC_SMB_CK1 EC_SMB_DA1 78 93
30,45 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_LED 38
1 2 EC_SMB_DA1 EC_SMB_CK2 79 SM Bus 95
8 EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 41
R730 2.2K_0402_5% EC_SMB_DA2 80 121
8 EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 48
127 ACIN
B AC_IN/GPIO59 ACIN 41,45 B

+3VS 6 100 EC_RSMRST# R658 0_0402_5%


18 PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03
14 101 NB_PWRGD 2 1
18 PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 19 NB_PWROK 14,37
R731 2.2K_0402_5% 15 102 @
19 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 37
1 2 EC_SMB_CK2 16 103 R652 0_0402_5%
29 LID_SW# LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SWI# 18
1 2 EC_SMB_DA2 17 104 SB_PWRGD SB_PWRGD 2 1
41 SUSP# SUSP#/GPIO0B ICH_PWROK/GPXO06 SB_PWROK 8,18,37
R732 2.2K_0402_5% 18 GPO 105 @
18 PBTN_OUT# PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# 25
26 EC_PME# 19 EC_PME#/GPIO0D GPIO WL_OFF#/GPXO09 106 2 1 WL_ON_LED# 31,38
25 107 R751 @ 0_0402_5%
8,19 EC_THERM# EC_THERM#/GPIO11 GPXO10
28 108 EC_MUTE
6 FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 EC_MUTE 40
37,41 VLDT_EN 29
E51TXD_P80DATA 30 FANFB2/GPIO15 PVT
E51RXD_P80CLK 31 EC_TX/GPIO16
EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 USER_BTN# 38
37 ON/OFF 32 ON_OFF/GPIO18 ENBKL/GPXID2 112 ENBKL 14
+5VS
38 PWR_SUSP_LED# 34 PWR_LED#/GPIO19 GPXID3 114 EAPD 39
38 NUM_LED# 36 NUMLED#/GPIO1A GPI GPXID4 115
2 1 TP_CLK GPXID5 116 NB_PWRGD
4.7K_0402_5% R208 117
GPXID6
2 1 TP_DATA GPXID7 118
4.7K_0402_5% R207 EC_CRY1 122
EC_CRY2 XCLK1
123 XCLK0 V18R 124
1
AGND
GND
GND
GND
GND
GND

EC_CRY1 EC_CRY2 C674


1U_0805_25V4Z
KB926QFA1_LQFP128_14X14 2
1 1
11
24
35
94
113

69

1 2 ENBKL C344 C343 20mil


1

L69
A A
R519 10K_0402_5% 15P_0402_50V8J 15P_0402_50V8J ECAGND 2 1
OUT
IN

2 2 FBM-L11-160808-800LMT_0603

PVT
NC

NC

Security Classification Compal Secret Data


2

Issued Date 2007/5/18 Deciphered Date 2008/5/18 Title

ENE-KB926
X1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
32.768KHZ_12.5P_MC-306 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 28 of 50
5 4 3 2 1
+3VALW W/O media board (LS2921P) PVT
Lid Switch
JP5 D28

1
TP_CLK 6 3 BTN_R
R337 1 CH3 CH2
100K_0402_5% 2
3
KSO17 4
28 KSO17 +5VS 5 2

2
KSI2 5 Vp Vn
KSI5 6
SW1 7
3 1 28 KSO16 KSO16
LID_SW# 28 8
KSI3 TP_DATA 4 1 BTN_L
KSI4 9 CH4 CH1
10 CM1293-04SO_SOT23-6

3
ACES_85201-10051
4 2 CONN@
D16
MPU-101-81_4P @
PSOT24C_SOT23

1 KSO16 KSO17 Left Right


SW3 SW4
EVQPLHA15_4P EVQPLHA15_4P
BTN_L 3 1 BTN_R 3 1
KSI2 PLAY
4 2 4 2
KSI3 STOP VOL_UP

5
6

5
6
KSI4 NEXT VOL_DOWN
KSI5 REV ARCADE_TV

To TP/B Conn.
JP6
+5VS 1
+5VS TP_DATA 2
28 TP_DATA 3
TP_CLK
28 TP_CLK 4
C137 5
BTN_R 6
0.1U_0402_16V4Z 7
8
9
10
INT_KBD Conn. BTN_L 11
12
ACES_87151-1207
CONN@
(Right) KSO15 JP7

KSO15 C243 1 100P_0402_50V8J KSO7 C231 1 100P_0402_50V8J KSO14 24


2 2 23
KSO13
KSO14 C242 1 100P_0402_50V8J KSO6 C230 1 100P_0402_50V8J KSO12 22
2 2 21
KSI0
KSO13 C241 1 100P_0402_50V8J KSO5 C229 1 100P_0402_50V8J KSO11 20
2 2 19
KSO10
KSO12 C240 1 100P_0402_50V8J KSO4 C228 1 100P_0402_50V8J KSI1 18
2 2 17
KSI2
KSO9 16
KSI0 C239 1 100P_0402_50V8J KSO3 C227 1 100P_0402_50V8J KSI3 15 BTN_R C139 1 100P_0402_50V8J
2 2 14 2
KSO8
KSO11 C238 1 100P_0402_50V8J KSI4 C226 1 100P_0402_50V8J KSO7 13 BTN_L C144 1 100P_0402_50V8J
2 2 12 2
KSO6
KSO10 C237 1 100P_0402_50V8J KSO2 C225 1 100P_0402_50V8J KSO5 11 TP_DATA C169 1 100P_0402_50V8J
2 2 10 2
KSO4
KSI1 C236 1 100P_0402_50V8J KSO1 C224 1 100P_0402_50V8J KSO3 9 TP_CLK C174 1 100P_0402_50V8J
2 2 8 2
KSI4
KSO2 7
KSI2 C235 1 100P_0402_50V8J KSO0 C223 1 100P_0402_50V8J KSO1 6
2 2 5
KSO0
KSO9 C234 1 100P_0402_50V8J KSI5 C222 1 100P_0402_50V8J KSI5 4
2 2 3
KSI6
KSI3 C233 1 100P_0402_50V8J KSI6 C221 1 100P_0402_50V8J KSI7 2
2 2 1
KSO8 C232 1 100P_0402_50V8J KSI7 C220 1 100P_0402_50V8J
(Left) ACES_85201-24051
2 2
CONN@

KSI[0..7]
KSI[0..7] 28
KSO[0..15]
KSO[0..15] 28 Security Classification Compal Secret Data
Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
LID / KB / TP / BTN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 29 of 50
+3VALW 1 2 C675 1 2 0.1U_0402_16V4Z
R618 0_0603_5%

+SPI_VCC
U17

28 EC_SPICS#/FSEL# 1 CE# VDD 8


2 1 SPI_WP# 3 6 EC_SPICLK_R R620 1 2 0_0402_5%
WP# SCK EC_SPICLK 28
+3VALW R619 2 1 4.7K_0402_5% SPI_HOLD# 7 5 EC_SO_SPI_SI_R R622 1 2 0_0402_5%
HOLD# SI EC_SO_SPI_SI 28
R621 4.7K_0402_5% 4 2 EC_SI_SPI_SO_R R623 1 2 0_0402_5%
VSS SO EC_SI_SPI_SO 28
MX25L8005M2C-15G_SOP8

SA00000XT00 : S IC FL 8M MX25L8005M2C-15G SOP 8P


ENE suggestion SPI Frequency over 66MHz
SST: 50MHz
MXIC: 70MHz
ST: 40MHz

U44
EC_SPICS#/FSEL# 1 8 +SPI_VCC
SPI_WP# CS# VCC EC_SPICLK_R
3 WP# SCLK 6
SPI_HOLD# 7 5 EC_SO_SPI_SI
HOLD# SI EC_SI_SPI_SO
4 GND SO 2

MX25L512AMC-12G_SO8
@
Reserved for BIOS simulator.
Footprint SO8
SPI ROM Footprint 150mil

+5VALW +5VALW

1
C348 1 2 0.1U_0402_16V4Z R284

@ 100K_0402_5%
@

2
U31
8 VCC A0 1
7 WP A1 2
28,45 EC_SMB_CK1 6 SCL A2 3
28,45 EC_SMB_DA1 5 SDA GND 4

AT24C16AN-10SI-2.7_SO8
@ 1

R277

100K_0402_5%
2

Security Classification Compal Secret Data


Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
BIOS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 30 of 50
A B C D E

+3VS +1.5VS +3VALW

1 1

1 1 1 1 1 1
C442 C441 C439 C438 C440 C437

4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z


2 2 2 2 2 2

R653 0_0402_5% JMINI1


18,26 SB_PCIE_WAKE# 1 2 1 1 2 2 +3VS
@ 3 4
3 4
5 5 6 6 +1.5VS
17 MINI_CLKREQ# 7 7 8 8
9 9 10 10
17 CLK_PCIE_MINI# 11 11 12 12
17 CLK_PCIE_MINI 13 13 14 14
15 15 16 16 Mini Card Power Rating

R655 0_0402_5%
Power Primary Power (mA) Auxiliary Power (mA)
17 17 18 18
19 20 WL_OFF#_R 1 2 Peak Normal Normal
19 20 WL_OFF# 28
21 22 NB_RST#
21 22 NB_RST# 14,19,26,28
PCIE_MRX_PTX_N0 23 24 +3VALW +3VS 1000 750
13 PCIE_MRX_PTX_N0 23 24
PCIE_MRX_PTX_P0 25 26
13 PCIE_MRX_PTX_P0 25 26
27 27 28 28
ICH_SMBCLK
+3VALW 330 250 250 (wake enable)
29 29 30 30 SB_CK_SCLK 10,11,17,19
2 ICH_SMBDATA 2
13 PCIE_MTX_C_PRX_N0 31 31 32 32 SB_CK_SDAT 10,11,17,19 +1.5VS 500 375 5 (Not wake enable)
13 PCIE_MTX_C_PRX_P0 33 33 34 34
35 35 36 36 USB20_N3 19
37 37 38 38 USB20_P3 19
39 39 40 40
41 41 42 42
(MINI1_LED#)
For MINICARD Port80 Debug 43 43 44 44 1 2 WL_ON_LED# 28,38 PVT
45 45 46 46
47 48 R752 0_0402_5%
E51TXD_P80DATA R654 1 47 48
28 E51TXD_P80DATA 2 0_0402_5% CL_RST#1_R 49 49 50 50
E51RXD_P80CLK 51 52
28 E51RXD_P80CLK 51 52

G1
G2
G3
G3
FOX_AS0B226-S99N-7F

53
54
55
56
CONN@

3 3

Camera

W=30mils
R605
+3VS 1 2 +CAM_VDD
1
0_0805_5%
C657
PVT WOEMI@ 0.1U_0402_16V4Z
R615 1 2
2 0_0402_5% JP35
1 1
L66 2 USB20_N9_R USB20_N9
2 USB20_N9 19
USB20_N9_R 2 1 USB20_N9 3 USB20_P9_R USB20_P9
2 1 3 USB20_P9 19
4 4
5 5
USB20_P9_R 3 4 USB20_P9 6
3 4 GND1
GND2 7
3

WCM2012F2S-900T04_0805
EMI@ ACES_88266-05001
R616 1 2 0_0402_5%
CONN@
D32 WOEMI@

PJDLC05_SOT23-3
1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MINI Card & Camera
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KAW60 LA-4661P
Date: Friday, August 08, 2008 Sheet 31 of 50
A B C D E
A B C D E

1 1

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KAW60 LA-4661P
Date: Tuesday, June 17, 2008 Sheet 32 of 50
A B C D E
A B C D E

1 1

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KAW60 LA-4661P
Date: Tuesday, June 17, 2008 Sheet 33 of 50
A B C D E
A B C D E

1 1

+3VALW

+5VALW

1
+USB_VCCA
U4
1 8 R42
GND OUT 100K_0402_5% R682 0_0402_5%
2 IN OUT 7
3 6 1 2 USB_OC#2 19

2
IN OUT R43
1 4 EN# FLG 5
C111 1K_0402_5%

4.7U_0805_10V4Z
G528_SO8 1 2 USB_OC#0 19 USB CONN. 1 & 2
2 1
C133

USB_EN# 0.1U_0402_16V4Z +USB_VCCA +USB_VCCA


28,38 USB_EN# 2
+USB_AS
W=80mils +USB_BS
W=80mils
2 2
1 1
1 1
+ C478 C474 + C1 C2
USB2@ USB2@
150U_D_6.3VM 470P_0402_50V7K 150U_D_6.3VM 470P_0402_50V7K
2 2 2 2
JUSB1 JUSB2
WOEMI@ 1 USB2WOEMI@ 1
USB20_N0 R598 1 USB20_N0_R VCC USB20_N2 USB20_N2_R VCC
19 USB20_N0 2 0_0402_5% 2 D- 8 8 19 USB20_N2
R599 1 2 0_0402_5% 2 D- 8 8
USB20_P0 R600 1 2 0_0402_5% USB20_P0_R 3 7 USB20_P2 R601 1 2 0_0402_5% USB20_P2_R 3 7
19 USB20_P0 D+ 7 19 USB20_P2 D+ 7
4 GND 4 GND
WOEMI@ USB2WOEMI@
5 GND1 5 GND1
L67 6 L68 6
GND2 GND2
4 4 3 3 4 4 3 3
SUYIN_020173MR004S512ZL SUYIN_020173MR004S512ZL
CONN@ CONN@
1 1 2 2 1 1 2 2

EMI@ WCM2012F2S-900T04_0805 USB2EMI@ WCM2012F2S-900T04_0805

D1
6 3 USB20_P2
CH3 CH2

+USB_VCCA 5 Vp Vn 2
3 3

USB20_N2 4 1
CH4 CH1
CM1293-04SO_SOT23-6

D31
USB20_P0 6 3
CH3 CH2

+USB_VCCA 5 Vp Vn 2

4 1 USB20_N0
CH4 CH1
CM1293-04SO_SOT23-6

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KAW60 LA-4661P
Date: Friday, August 08, 2008 Sheet 34 of 50
A B C D E
A B C D E

1 1

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KAW60 LA-4661P
Date: Tuesday, June 17, 2008 Sheet 35 of 50
A B C D E
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KAW60 LA-4661P
Date: Tuesday, June 17, 2008 Sheet 36 of 50
A B C D E

+3VS +3VALW +3VALW +3VALW +3VALW +3VALW

Power ON Circuit R111

1
10K_0402_5%
D5 @
BAS16_SOT23-3 U10A U10E U10F
@ SN74LVC14APWR_TSSOP14 SN74LVC14APWR_TSSOP14 SN74LVC14APWR_TSSOP14

14

14

14

14
PVT R112 R104

2
R100 47K_0402_1% 100K_0402_1% 10_0402_5%

P
1 1
VLDT_EN 1 2 1
28,41 VLDT_EN I O 2 3 I O 4 11 I O 10 13 I O 12 1 2 SB_PWROK 8,18,28

G
+3V POWER +3V POWER +3V POWER +3V POWER
1 2

7
R105
R106 C203 U10B C204
10K_0402_5% 1U_0603_10V4Z SN74LVC14APWR_TSSOP14 1U_0805_25V4Z 100K_0402_5% @
2 1

R108
10_0402_5%
2006/02/22 Change R100 to 47K +3VALW +3VALW
1 2 NB_PWROK 14,28

U10D
SN74LVC14APWR_TSSOP14

14

14
P

P
1 2 5 I O 6 9 I O 8 2 1

G
R109 R113
@ 10_0402_5% @ 180K_0402_5% note:T1 minimum 15ms,T2 minimum 33ms/maximum 500ms,

7
U10C
SN74LVC14APWR_TSSOP14 SUSP# goes to low after SB_PWRGD goes to low for power
down.
2 T1 2

VLDT_EN

NB_PWRGD

SB_PWRGD
T2
TOP Side +3VALW
SUSP#
2 @ 1
J3 10K_0603_5%
Power Button +1.8VS

2
2 @ 1 R281

J4 10K_0603_5% 100K_0402_5%
Bottom Side
1

D10
2 ON/OFF 28
ON/OFFBTN# 1
38 ON/OFFBTN#
3 51ON#
51ON# 42
CHN202UPT_SC70
3 3

1
2
SW10
SMT1-05-A_4P C358 D11
1 3 1000P_0402_50V7K RLZ20A_LL34
ON/OFFBTN# 1

2
1

D
2 4 2N7002_SOT23
EC_ON 2
28 EC_ON Q17
G
6
5

R290 S
3

10K_0402_5%
<BOM Structure>
MP remove

4 4

Security Classification Compal Secret Data


Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
PWR_OK/ PWR BTN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 37 of 50
A B C D E
W/O Modem

MDC Conn.
JMDC1

1 GND1 RES0 2
AC_SDOUT 3 4 20mil
19 AC_SDOUT IAC_SDATA_OUT RES1
5 GND2 3.3V 6 +3VALW
19 AC_SYNC AC_SYNC 7 8
R357 1 IAC_SYNC GND3
19 ACZ_SDIN1 2 33_0402_5% 9 IAC_SDATA_IN GND4 10
AC_RST# MDC@ 11 12 AC_BITCLK
19 AC_RST# IAC_RESET# IAC_BITCLK AC_BITCLK 19
R538 LED5 1
300_0402_5% +3VALW C432
PWR_LED# 1 2 2 1 PWR_LED# MDC@

GND
GND
GND
GND
GND
GND
+5VS
3 1 22P_0402_50V8J
C3 2
HT-110UYG_1204 MDC@ ACES_88018-124G

13
14
15
16
17
18
1U_0603_10V4Z CONN@
1

D 2
2N7002_SOT23
28 PWR_LED 2 Connector for MDC Rev1.5
G Q1
S
3

R331 LED4
300_0402_5%
+5VALW 1 2 2 1 PWR_SUSP_LED# PWR_SUSP_LED# 28
3

HT-110UD_1204

R332 LED2
300_0402_5% +5VALW
+5VALW 1 2 2 1 BATT_FULL_LED# BATT_FULL_LED# 28
3
1
HT-110UYG_1204 C435
<BOM Structure> + C436
0.1U_0402_16V4Z <BOM Structure>
To LED/B Conn. 2
150U_D2_6.3VM

R537 LED6
300_0402_5% +5VS
+5VALW 1 2 2 1 BATT_CHGI_LED# BATT_CHGI_LED# 28 JP2
3 1 1 2 2 +5VALW
PWR_LED# 3 4
HT-110UD_1204 MEDIA_LED# 3 4
5 5 6 6
28 CAPS_LED# 7 7 8 8
28 NUM_LED# 9 9 10 10 USB20_N4 19
28 E-MAIL_LED# 11 11 12 12 USB20_P4 19
+3VALW
PVT PVT 37 ON/OFFBTN# 13
15
13 14 14
16
28 E-MAIL_BTN# 15 16 USB20_N6 19
28 IE_BTN# 17 17 18 18 USB20_P6 19
+3VS 19 20
28 USER_BTN# 19 20
28 EMPWR_BTN# 21 21 22 22 USB_EN# 28,34
2

+3VALW 23 24
23 24
1

D29 25 26
R329 25 26
DAN217_SC59 27 27 28 28
5

29 30

GND
GND
GND
GND
GND
GND
@ 29 30
1

1 300_0402_5%
5

1 R522
1

2 100K_0402_5% ACES_88018-304G

31
32
33
34
35
36
2 CONN@
3
2

3
2

3 LED3
4 4 WLSW_EN# 28 HT-110UD_1204
6

SW9
6

HSS110_4P
1

WL_ON_LED#
Wireless SWITCH WL_ON_LED# 28,31
+3VS PVT

2
G
19 SATA_LED# SATA_LED# 3 1 MEDIA_LED#

D
Q67
2N7002_SOT23

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MDC / LED / SW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KAW60 LA-4661P
Date: Friday, August 08, 2008 Sheet 38 of 50
A B C D E F G H

+VDDA

+5VAMP
U34 (output = 300 mA)

1
R309 L19 1 2 60mil 1
10K_0402_5%
+5VS
KC FBM-L11-201209-221LMAT_0805 IN
OUT 5 40mil +VDDA
1 1 2 GND
L21 1 2 C390 C397 1 4.75V

2
KC FBM-L11-201209-221LMAT_0805 3 4 C388
10U_0805_10V4Z 0.1U_0402_16V4Z SHDN BYP
1 2
C387 1U_0402_6.3V4Z 2 2 G9191-475T1U_SOT23-5 4.7U_0805_10V4Z
1

1
C737 2
R307
10K_0402_5%
1 2 1

2
C380 0.01U_0402_16V7K
1 2 MONO_IN
1U_0402_6.3V4Z

1
C 1 2
C378 1 R304 Q20 R308 2.4K_0402_1%
28 BEEP# 2 1 2 2
1U_0402_6.3V4Z B
560_0402_5% E 2SC2411K_SOT23

3
C376 1 R302
19 SB_SPKR 2 1 2
1U_0402_6.3V4Z L50
20mil

1
560_0402_5% 1 2

R301
D12
CH751H-40PT_SOD323-2
HD Audio Codec 1 1 1
MBK1608121YZF_0603
+3VS

10K_0402_5% C375 C373 C369

2
0.1U_0402_16V4Z 10U_0805_10V4Z
2 2 2
10U_0805_10V4Z

+AVDD_HDA

L18 1 2 0.1U_0402_16V4Z 40mil


+VDDA
FBM-L11-160808-800LMT_0603 1 1
C389
C381
2 10U_0805_10V4Z 2

25

38

9
2 2 U33

DVDD
AVDD1

AVDD2

DVDD_IO
14 35 AMP_LEFT
NC LINE_OUT_L AMP_LEFT 40
15 36 AMP_RIGHT
NC LINE_OUT_R AMP_RIGHT 40
R659 1K_0402_1% INT_MIC1 2 MIC2_C_L 16 39 HP_LEFT
MIC2_L HP_OUT_L HP_LEFT 40
INT_MIC_R 2 1 C733 4.7U_0805_6.3V6K
1 2 MIC2_C_R 17 41 HP_RIGHT
MIC2_R HP_OUT_R HP_RIGHT 40
C734 4.7U_0805_6.3V6K
23 LINE1_L NC 45

24 LINE1_R DMIC_CLK 46
For EMI
18 CD_L NC 43

20 44 1 2 1 2 C374 MIC2_VREFO
CD_R NC R660 10_0402_5% 22P_0402_50V8J
19 CD_GND
INT(Analog) MIC
BIT_CLK 6 AZ_BITCLK 19

1
MIC1_L 1 2 MIC1_C_L 21
40 MIC1_L MIC1_L
C386 4.7U_0805_6.3V6K R661
MIC1_R 1 2 MIC1_C_R 22 8 1 2 ACZ_SDIN0 19 2.2K_0402_5%
40 MIC1_R MIC1_R SDATA_IN
C392 4.7U_0805_6.3V6K R297 33_0402_5% 15mil
MONO_IN 12 37 JP13

2
PCBEEP MONO_OUT INT_MIC_R MIC_R
1 2 1
29 R662 0_0603_5%
LINE1_VREFO GND_R 2
19 AZ_RST# 11 RESET# 1 1 2
3 C735 R663 0_0603_5% ACES_85204-0200 3
GPIO1 31
19 AZ_SYNC 10 10mil 15mil CONN@
SYNC 220P_0402_50V7K
MIC1_VREFO_L 28 MIC1_VREFO_L 2
19 AZ_SDOUT 5 SDATA_OUT
Place close to Codec 32 MIC1_VREFO_R MIC_GND_R
MIC1_VREFO_R
2 GPIO0
3 GPIO3 MIC2_VREFO 30 MIC2_VREFO
R677 2 1 39.2K_0402_1% SENSE_A 13 10mil
40 HP_PLUG# SENSE A
34 27 CODEC_VREF
SENSE B VREF
1 1
EAPD_R 47 40
R679 2 EAPD JDREF
40 MIC_PLUG# 1 20K_0402_1% C736 C391

1
48 33 0.1U_0402_16V4Z 10U_0805_10V4Z
SPDIFO NC R306 2 2
4 26 20K_0402_1%
DVSS1 AVSS1
7 DVSS2 AVSS2 42

2
DGND ALC268-GR_LQFP48_9X9 AGND
Sense Pin Impedance Codec Signals 1
R664
2
0_0805_5%
1
R665
2
0_0805_5%

39.2K PORT-A (PIN 39, 41) For EMI request


1 2 1 2
R666 0_0805_5% R667 0_0805_5%
20K PORT-B (PIN 21, 22) R696 0_0402_5%
SENSE A EAPD_R
28 EAPD 1 2 1 2 1 2
10K PORT-C (PIN 23, 24) R668 0_0805_5% R669 0_0805_5%

1
5.1K PORT-D (PIN 35, 36) C755
@
220P_0402_50V7K GND GNDA GND GNDA
4 2 4
39.2K PORT-E (PIN 14, 15)

20K PORT-F (PIN 16, 17)


SENSE B
10K PORT-G (PIN 43, 44)
Security Classification Compal Secret Data Compal Electronics, Inc.
5.1K PORT-H (PIN 45, 46) Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDA Codec ALC268
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KAW60 LA-4661P
Date: Friday, August 08, 2008 Sheet 39 of 50
A B C D E F G H
A B C D E

+5VAMP
W=40mil
+3VS +5VAMP
1 1
1
C677 C678 +5VAMP
C676 0.1U_0402_16V4Z HP_PLUG#
HP_PLUG# 39

2
C679 0.1U_0402_16V4Z 2 2
0.47U_0603_16V4Z 2 4.7U_0805_10V4Z R670

2
1 2 AMP_RIGHT_C-1 1 2 AMP_RIGHT_C 100K_0402_5% Q60
39 AMP_RIGHT

1
C680 1U_0402_6.3V4Z R671 D

11

19

20
10

1
1 2 AMP_LEFT_C-1 1 2 AMP_LEFT_C U43 100K_0402_5% 2

1
39 AMP_LEFT C681 C682 1U_0402_6.3V4Z G

CVDD

HVDD

PVDD
PVDD

VDD
1

1
0.47U_0603_16V4Z S 2N7002_SOT23

3
1 R624 R625 Q61 1

1
D
560_0402_5% 560_0402_5% 3 22 SPKR+ PLUG# 2
INR_A ROUT+ SPKR- G
5 21

2
INL_A ROUT- 2N7002_SOT23
HPF Fc = 604Hz S

3
R626 1 2 100K_0402_5% 27 8 SPKL+
/AMP EN LOUT+ SPKL-
LOUT- 9
+5VAMP R627 1 2 100K_0402_5% 24 2 1
HP EN HPOUT_R R672 0_0402_5%
HP_R 17
+5VAMP HP_RIGHT 1 2 HP_RIGHT_C 1 2 HP_RIGHT_R 4 18 HPOUT_L @
39 HP_RIGHT C683 4.7U_0805_6.3V6K R628 39K_0402_5% HP_LEFT_R INR_H HP_L
6 INL_H
HP_LEFT 1 2 HP_LEFT_C 1 2
39 HP_LEFT
1

C684 4.7U_0805_6.3V6K R629 39K_0402_5% VOL_AMP 26


R630 /SD
CVSS 15
30K_0402_5% 28 BEEP
VSS 16
1 12 1
2

CP+ C686
14 CP- GND 2
VOL_AMP C685 23 1U_0603_10V4Z
PGND
1U_0603_10V4Z 25 BIAS PGND 7
1

D 2 2
CGND 13
1

1 2 EC_MUTE EC_MUTE 28 1 GND 29


R631 G C688
100K_0402_1% C687 S Q37 APA2057A_TSSOP28
3

2N7002_SOT23 2.2U_0805_10V6K
2
0.01U_0402_16V7K 2
2

TOP/R
Gain= 14dB
2 2
LINE Out / HP Out JACK
JHP1
8
20mil ESD 7
2 2
C401 C400
FSOV_Change 75 to 54.9 ohm PLUG# 5
330P_0402_50V7K 330P_0402_50V7K
1 1
4
R322 54.9_0603_1%
HPOUT_R 1 2 HPOUT_R_1 1 2 HPOUT_R_2 3
L28 FBM-11-160808-700T_0603 6
HPOUT_L 1 2 HPOUT_L_1 1 2 HPOUT_L_2 2
R321 54.9_0603_1% L27 FBM-11-160808-700T_0603 1

SINGA_2SJ-S351-S39
CONN@

JP12 (HDA Jack for KAW60)


SPKL+ R673 1 2 0_0603_5% SPK_L+
SPKL- R674 0_0603_5% SPK_L- 1
1 2 2
SPKR+ R675 1 2 0_0603_5% SPK_R+
SPKR- R676 1 2 0_0603_5% SPK_R- 3
4 TOP/L
20mil ACES_85204-0400
Speaker Conn. MIC JACK
JMIC1
3 MIC1_VREFO_L MIC1_VREFO_R 8 3

ESD 7

1
MIC_PLUG# 5
39 MIC_PLUG#
R326 R327
2.2K_0402_5% 2.2K_0402_5% 4
R561 1K_0402_1%

2
2 1 MIC1_R_R 1 2 MIC1_R_1 3
39 MIC1_R
L24 FBM-11-160808-700T_0603 6
2 1 MIC1_L_L 1 2 MIC1_L_1 2
39 MIC1_L
L23 FBM-11-160808-700T_0603 1
R681 1K_0402_1% 1 1
SINGA_2SJ-S351-S21
ESD_Change 75 to 1K ohm C404 C405 CONN@
220P_0402_50V7K 220P_0402_50V7K
2 2
(HDA Jack for KAW60)

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Amplifier & Audio Jack
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KAW60 LA-4661P
Date: Friday, August 08, 2008 Sheet 40 of 50
A B C D E
A B C D E

+5VALW
+1.8VALW TO +1.8V
+3VALW TO +3VS +1.8V

2
+3VS R167
10K_0402_5%
1 1
1 1 C121 C122

1
+3VALW C559 C562 SUSP
46 SUSP
+1.8VALW 1U_0603_10V4Z 10U_0805_10V4Z
U41 10U_0805_10V4Z 1U_0603_10V4Z 2 2
2 2 U3
8 D S 1

1
R508 D
1 7 D S 2 8 D S 1 1
6 3 100K_0402_5% 7 2 R289 2
D S D S 28 SUSP#
5 4 2 1 5VS_GATE 1 2 +VSB 6 3 R727 0_0402_5% 100K_0402_5% G
D G D S

1
R562 20K_0402_5% 5 4 1 2 SYSON_ALW 1 2 +VSB Q12 S

3
SI4800BDY_SO8 D G R586
1 SI4856ADY-T1-E3_SO8 10K_0402_5% 2N7002_SOT23

1
C119 D
1
2

1
C560 D C359 2 SYSON#

2
100K_0402_5%
C570 2 SUSP 10U_0805_10V4Z 0.1U_0603_25V7K G

1
1

1
2

100K_0402_5%
10U_0805_10V4Z 0.1U_0603_25V7K G S Q18
1

3
2 R500 Q29 R288 2N7002_SOT23
S PVT

3
2N7002_SOT23
@

2
+5VALW

Q58 Q59

2
D D

28,45 ACIN ACIN 2 ACIN 2 R31


G G 10K_0402_5%
S 2N7002_SOT23 S 2N7002_SOT23
3

3
@

1
SYSON#
46 SYSON#

1
D
+5VALW TO +5VS SYSON 2
28 SYSON
G
+1.8VALW TO +1.8VS

1
2 Q5 S 2

3
+1.8VALW +5VALW +5VS
U7 R589 2N7002_SOT23
U37 8 1 100K_0402_5%
D S
8 1 +1.8VS 7 2

2
D S D S
7 D S 2 6 D S 3 1 1
6 3 5 4 C166 C165
D S D G
5 D G 4 1 1
C447 C446 1 SI4800BDY_SO8 10U_0805_10V4Z 1U_0603_10V4Z
SI4856ADY-T1-E3_SO8 2 2
1 10U_0805_10V4Z 1U_0603_10V4Z C143
2 2 4.7U_0805_10V4Z
C443 2 +5VALW
4.7U_0805_10V4Z R728 0_0402_5%
2 5VS_GATE
1 2

2
R725

2
1 2 R563 5VS_GATE 10K_0402_5%
60.4K_0402_1% C658
0.1U_0603_25V7K

1
2

VLDT_EN#
C632
0.1U_0603_25V7K
1

1
D
12/30 Change R563 to 60.4K VLDT_EN
28,37 VLDT_EN 2
2006/2/22 Add C658 0.1uF G

1
Q66 S

3
R726 2N7002_SOT23
3 +1.2VALW TO +1.2V_HT 100K_0402_5% 3

2
+1.2V_HT

+1.2VALW
1
C756
1
C757
Near PU8 Near PU12
2

U46 1U_0603_10V4Z 10U_0805_10V4Z R698 +0.9V +2.5VS +1.5VS +1.8V +3VS +1.8VS +5VS
2 2 470_0805_5%
8 D S 1
7 D S 2
2

2
6 3
1

D S R604 R587 R588 R26 R224 R270 R181


5 D G 4 1 2 +VSB
1 R699 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5%
SI4856ADY-T1-E3_SO8 33K_0402_5%
1

D Q63 D Q64
1
1

1
C759 2 VLDT_EN# 2
0.1U_0603_25V7K 2 G G 2N7002_SOT23-3
1

1
C758 2N7002_SOT23-3 D D D D D D D
S S
3

2
2 SYSON# 2 SUSP 2 SUSP 2 SYSON# 2 SUSP 2 SUSP 2 SUSP
4.7U_0805_10V4Z G G G G G G G
1

S Q36 S Q34 S Q35 S Q6 S Q14 S Q15 S Q10


3

3
2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23
R700
33K_0402_5%
2

4 4
1

D
ACIN 2 Q65
G
S 2N7002_SOT23
Security Classification Compal Secret Data
3

Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title


DC INTERFACE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 41 of 50
A B C D E
A B C D

PJP1
SINGA_2DC-G756-I06 PL1
ADPIN VIN
FBMA-L18-453215-900LMA90T_1812
1 1 2

1
PR1
G 2 10_1206_5%

560P_0402_50V7K

12P_0402_50V8J
G

560P_0402_50V7K
12P_0402_50V8J
1 3 PR2 1

1 2
1

1
PC1
1K_1206_5%

PC2

PC3

PC4
1 2
PD1 PQ1

2
RLZ24B_LL34 TP0610K_SOT23
PD2 PR3
VIN RLS4148_LL34-2 1K_1206_5%
B+

2
2 1 1 2 3 1

PR4
1K_1206_5%
1 2

100K_0402_5%

100K_0402_5%
1

1
PR5
PR7

PR6
1K_1206_5%

2
1 2

2
VIN

1
PD3
RLS4148_LL34-2 PR8

1
PD4 100K_0402_5%
RLS4148_LL34-2 PQ2

1 1
2 1 DTC115EUA_SC70

1 2
BATT+
2 PR9 28,44 ACOFF 2 2

PQ4 33_1206_5% VS
TP0610K_SOT23
PQ3
2 2 DTC115EUA_SC70

3
CHGRTCP 3 1
0.22U_1206_25V7K
1

3
1

PR10
PC5

100K_0402_5% PC6
0.1U_0603_25V7K
2

PR11
B+
2

22K_0402_5% PR12
37 51ON# 1 2 VL 2.2M_0402_5%
2 1

1
VS PR13
499K_0402_1%

1
1

PR14

2
RTCVREF PR15 100K_0402_1%
PU1 200_0805_5% PU2A
3.3V G920AT24U_SOT89 LM393DR_SO8

8
8,43,45 MAINPWON PD5
2

PR16 PR17 2 3

P
3 3
+
1 2 1 2 3 OUT IN 2 1 1 O

0.01U_0402_25V7K
+CHGRTC 44 ACON 3 2
-
1

1
560_0603_5% 560_0603_5%
4.7U_0805_6.3V6K
1

1
GND

1000P_0402_50V7K

32.4
PC8

PC9
PC7 RB715F_SOT323 PR18

4
1

1
1U_0805_25V4Z 191K_0402_1%
2

PC11
PC10 PR19
2

2
0.1U_0603_25V7K

PRG++ 2

2
499K_0402_1%

ACIN PQ5
PR20 2N7002W T/R7 1N SOT-323 PR21
Precharge detector

1
34K_0402_1% D 47K_0402_5%
Min. typ. Max. RTCVREF 2 1
G
2 2 1
PACIN 44,45

1
H-->L 14.589V 14.84V 15.243V S

3
1
PQ6
- PBJ1 + L-->H 15.562V 15.97V 16.388V @ PR22 DTC115EUA_SC70
66.5K_0402_1% 2 +5VALW
2 1 +RTCBATT
+RTCBATT BATT ONLY

2
Precharge detector

3
ML1220T13RE
45@
Min. typ. Max.
4
H-->L 6.138V 6.214V 6.359V 4

L-->H 7.196V 7.349V 7.505V

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/06/11 Deciphered Date 2009/06/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN/DECTOR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B KAW60 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 42 of 50
A B C D
A B C D

B+

FBMA-L11-322513-151LMA50T_1210
2
PL2

PD6
CHP202UPT_SOT323-3
PC12 PC13
1

0.1U_0603_25V7K 0.1U_0603_25V7K

2
1 2 BST5B BST3B 1 2

1 B+++ 1
2200P_0402_50V7K

PQ7 VL

4.7U_1206_25V6K
8 1

1
G2 D2
7 S2/D1 D2 2
1

2
PC15

6 3 DL5
S2/D1 G1
PC14

5 4 PR23 B+++
S2/D1 S1

47_0402_5%
0_0603_5% B+++ PQ8
2

2200P_0402_50V7K
4.7_1206_5%

4.7_1206_5%
AO4932_SO8 1 8
D2 G2

PR24

4.7U_1206_25V6K
PR27 PC16 2 7

1
D2 S2/D1

PR25

PR26
0_0603_5% 0.1U_0603_25V7K 3 6

2
G1 S2/D1

1
5HG 1 2 DH5 4 5

1
S1 S2/D1

PC17

PC18
@

1 2

2
AO4932_SO8

2
2
PC19
1U_1206_25V7K

0.1U_0603_25V7K
LX5
VL PR28

2
0_0603_5%
2VREF_1999

100K_0402_1%
1 PC22
3HG

4.7U_0805_10V4Z

1
100K_0402_1%
1U_0805_16V7K
1

2
PC20
1

PR29

PR30
BST3A

PC21
LX3

2
PR31

2
0_0603_5%

2 1

2 1
2

499K_0402_1%
18

20

13

17

499K_0402_1%
PL3

10UH_SIL104R-100PF_4.4A_30%
PR32

PR33
10UH_SIL104R-100PF_4.4A_30% BST5A 14

V+
LD05

TON

VCC

1
BST5
2
ILIM3 5 2

16 DL3
DH5
+5VALWP
1

2
15 LX5
19 DL5 ILIM5 11

PL4
21 OUT5
9 PU3 28
FB5 BST3
10.2K_0402_1%

1 26 DH3
N.C.MAX8734AEEI+_QSOP28 DH3
2

24

1
DL3
PR34

6 SHDN# LX3 27
VS 4 22
1 ON5 OUT3
@ 1 2 3
+ ON3
150U_D_6.3VM

PR35 7
1

FB3
PC23

0_0402_5% 12 2 +3VALWP
SKIP# PGOOD
2 2VREF_19998

PRO#

3.57K_0402_1%
LDO3
PZD1 PR37

GND
REF
2

2
0_0402_5%

RLZ5.1B_LL34 47K_0402_5% PR38


PR36

@ PR39
1 2 1 2 1 2

23

25

10
2

1
100K_0402_5%

0.047U_0603_16V7K

0.22U_0603_16V7K
0_0402_5% 1
PR40

PC24

4.7U_0805_10V4Z
1

1
1
+

PC26
2

PC25

2
PC27
45,47 SPOK 330U_D3L_6.3VM_R25M
1

2
2

0_0402_5%
PR42
PR41
0_0402_5%

2
PR43

1
1 2
3 3

47K_0402_5%
1

PC28
0.047U_0603_16V7K
+3.3V Iocp = 5.36A ~ 9.03A
2

Ipeak=4.5A
+5V Iocp = 5.35A ~ 8.65A
Ipeak=4.5A Imax=3.5A
Imax=3.5A
MAINPWON 8,42,45
1

PC29
1U_0603_16V6K
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/06/11 Deciphered Date 2009/06/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+5VALWP/+3VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
KAW60
Friday, August 08, 2008 Sheet 43 of 50
A B C D
A B C D E

CP Point: Charger
Iadp=0~2.912A(65W) 85% CP Point, 3.42A*0.85=2.907A~2.912A
Iinput=(34.8K/44.8K)*(75/20)=2.912A
P2
PQ9 PQ10 PR44 B+ PL5 CHG_B+ PQ11
AO4407A_SO8 AO4407A_SO8 P3 0.02_2512_1% AO4407A_SO8
FBMA-L18-453215-900LMA90T_1812
VIN 8
7
1
2
1
2
8
7
1 4 1 2 1
2
8
7

2200P_0402_50V7K
0.1U_0603_25V7K
6 3 3 6 2 3 3 6

4.7U_1206_25V6K

4.7U_1206_25V6K
5 5 5

1
1 1

PC30

PC31

PC32

PC33
4

4
PR45

2
1

1
PC34 PC35 47K_0402_1%

1
0.1U_0603_25V7K 0.1U_0603_25V7K 1 2
PR46 VIN

2
1

10K_0402_1%
SI4810BDY-T1-E3_SO8
200K_0402_1%

2
PR47

5
6
7
8
47K_0402_5%

2
1

PR48
0.1U_0603_25V7K

D
D
D
D
3

PC36
1SS355_SOD323 CSSN
2

PQ12
PQ13 CSSP
PD9
2

1
47K
DTA144EUA_SC70 ACOFF#

G
S
S
S
2 47K VIN 2 1

4
3
2
1

1
45 6C/8C#

2
G
PC37 PQ15 PQ14
0.1U_0603_25V7K SI2301BDS_SOT23 DTC115EUA_SC70

SI4810BDY-T1-E3_SO8
3 1
1

2
1

D
ACOFF

S
1 DCIN 2 ACOFF 28,42

5
6
7
8
CSSP 27
PC38 0_0402_5%

D
D
D
D

1
1U_0603_10V6K @ PR49 29

2
TP

PQ17
2 PQ16 2 1 17 @ PC39
@PC39

3
DTC115EUA_SC70 PR50 CELLS 1000P_0402_50V7K
26

2
CSSN

G
S
S
S
10K_0402_0.1%
2 1 4

4
3
2
1
REF
150K_0402_5%

25 charger_DHI PR52
3

DHI
1

3 0.015_2512_1%
CLS
PR51

1908LDO BATT+
1

D
0.1U_0402_16V7K

23 charger_LX 1 2 1 4
LX
1
34.8K_0402_1%

2 PQ18 1908LDO 2 1 2 1 1908REFIN 12 REFIN


1
PC40

2 G 2N7002W T/R7 1N SOT-323 PU4 2


2 3
2

2
PR55

10U_LF919AS-100M-P3_4.5A_20%
S PR53 PR54 MAX1908ETI+T_QFN28 21 charger_DLO
3

DLO

PL6

4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K
9.31K_0402_1% 15K_0402_1% PR56 PC41
2

VCTL 15 0_0402_5% 0.1U_0603_25V7K


2

1
VCTL

1
PC42

PC43

PC44
13 24 charger_BST 1 2
ICTL BST

1
11

2
ACOK#

0.01U_0402_25V7K
8 22 charger_DLOV PD10
SHDN# DLOV
1

D PR58 PR57
10 ACIN 1SS355_SOD323
2 PQ19 24.9K_0402_1% 9 2 2 1
ICHG LDO

1
PC45
G 2N7002W T/R7 1N SOT-323 2 1

2
S 28 IREF 28 33_1206_5%
3

IINP 1908LDO
7

2
CCV
CSIP 19
1

2
PGND
18 PC46

GND
CCS
CSIN

CCI
PD11 PR59 16 1U_0603_10V6K
BATT

2
ACOFF# 1 2 100K_0402_1%

1
10K_0402_1%
PC47

14

20
2
RLS4148_LL34-2 1U_0805_25V4Z
2

1
PR60
PR61 MAX1908-CCS
22K_0402_5%

0.01U_0402_25V7K

0.01U_0402_25V7K
42,45 PACIN 1 2

1
CSIP

2
0.1U_0402_16V7K
PR62

PC48

PC49
0_0402_5%

1
PC50
1 2

1
28 FSTCHG CSIN
42 ACON
2

2
PR63
100K_0402_5%
3 BATT+ 3
1

Charger ADJ Calibrate# PR170 PR173 Vrefin=V1908LDO*(15K/(9.31K+15K)) PC51


2
10K_0402_5%

=5.4V**(15K/(9.31K+15K))=3.331V 0.1U_0402_16V7K
2
PR64

4.0V L @ @ VS BATT+
Vvctl=3.331*(221K/(221K+665K))=0.83087V
1

4.1V L 665K 221K Vbatt=CELLS*(4+(0.4*(Vvctl/Vrefin)))

1
=3*(4+(0.4*(0.83087/3.331)))=12.29v
PR65

0.01U_0402_25V7K
4.2V H @ @ 845K_0603_1%

2
1

PC52
@PR169
@ PR169 1908REFIN
0_0402_5% +3VALW

1
IREF=0.832*Icharge 1 2

2
1

PR66

1
IREF=0.73~3.3V PR170 300K_0603_0.1%
665K_0402_1% PR68 PR67
PQ41

8
PU5A 511K_0402_1% 10K_0402_5%

2
SI2301BDS_SOT23 PR171 3 1 2

P
2

0_0402_5% +
2P3S:4400mAH 1

2
1908LDO VCTL 0 PQ20
28 BATT_OVP
S

1 3 1 2 2
D

1
D 2N7002W T/R7 1N SOT-323
0.8C=3.52A

1
LM358ADR_SO8 2

4
1

1
VS PR69 PC53 G
G
2

PR172 PR173 PC132 200K_0402_1% 0.01U_0402_25V7K S PQ21

1
100K_0402_1% 221K_0402_1% 1000P_0402_50V7K PU5B D 2N7002W T/R7 1N SOT-323
2

2
2

OVP-Voltage: LM358ADR_SO8 2 6C/8C# 45

2
8

@ PR174 G
2

LI-3SBattery Pack=13.5V----BATT-OVP=2.0061V 4.3K_0402_5% 5 S


P

3
+
1

4 D 4
Battery-OVP=0.1486*BATT+ 7 0
2 PQ42 6
1

28 CALIBRATE# -
G

G 2N7002W T/R7 1N SOT-323


S
3

Vbatt=CELLS*(4V+(0.4*(Vvctl/Vrefin)))

Charge voltage Security Classification Compal Secret Data Compal Electronics, Inc.
3S CC-CV MODE : 12.6V Issued Date 2008/06/11 Deciphered Date 2009/06/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. KAW60
Date: Friday, August 08, 2008 Sheet 44 of 50
A B C D E
A B C D

PR70
100K_0402_5%
1 2
PH1 under CPU botten side :
+3VALWP
BATT+ BATT++ CPU thermal protection at 90 degree C
PR71
PL7 1K_0402_5%
Recovery at 70 degree C

BATT+
2 1
FBMA-L18-453215-900LMA90T_1812 6C/8C# 44
1 2 BATT++
1
VL 1

2
VS VL
1

1
PC54 @PR72
@PR72
0.01U_0402_25V7K PC55 1K_0402_5%

2
1000P_0402_50V7K
2

1
PR75 PC56 PR76 PR73

1
1K_0402_5% 0.1U_0603_25V7K 442K_0603_1% 150K_0402_1%
1 2 BATT_TEMP PR74 1 2

2
BATT_TEMP 28 9.76K_0402_1%

1
2
PR78 PR77

8
1K_0402_5% 82.5K_0603_1%
2 1 1 2 5

P
7 +
6 O 7 MAINPWON 8,42,43

100K_0603_1%_TH11-4H104FT
TM_REF1
PJP2 battery connector 5 6 -

G
PU2B
4

1
PR79 LM393DR_SO8

4
3
SMART 2
6.49K_0402_1%

PH1
1 2 +3VALWP
Battery: 1

1.GND

1U_0805_16V7K
2
1

1
SUYIN_200275MR007G161ZL

PC58
PC57 PR80
2.SMC PJP2 PR81 1000P_0402_50V7K 150K_0402_1%
100_0402_5%
3.SMD
2 1 VL

2
1 2 EC_SMB_DA1 28,30
4.TS
5.B/I

1
6.ID PR83 PR82
7.BATT+
2 2

100_0402_5% 150K_0402_1%
1 2 EC_SMB_CK1 28,30

2
KAW60 is used JAL90 battery connector footprint, but pin
definition is reverse compare with KAW60 original battery
connector, so schematic must be change to satisfy with
JAL90 connector. Vin Detector
Min. typ. Max.
PQ22 H-->L 16.976V 17.257V 17.728V
TP0610K_SOT23
L-->H 17.430V 17.901V 18.384V
B+ 3 1 +VSBP PR84
1M_0402_1%
1 2
1

1
PR85 VIN VIN
100K_0402_5% PC59 PC60
0.22U_1206_25V7K 0.1U_0603_25V7K PR87
2

1
PR88 10K_0402_5% PR89
2

22K_0402_5% PR86 VS 10K_0402_5%


VL 1 2 84.5K_0402_1% 1 2 ACIN
ACIN 28,41
PR91

2
2

8
22K_0402_5% PU6A
PR90 1 2 3

P
3 3

100K_0402_5% + PACIN
O 1 PACIN 42,44

20K_0402_1%
2 -

G
PR93
1

1
D

PR92
0_0402_5% PC61 LM393DR_SO8

4
1 2 2 PQ23 1000P_0402_50V7K PC62 PZD2 PR94
43,47 SPOK G 2N7002W T/R7 1N SOT-323 0.1U_0603_25V7K RLZ4.3B_LL34 10K_0402_5%

2
S
3

2
1

2
@ PC63
0.1U_0402_16V7K PR95
2

10K_0402_5%
2 1 RTCVREF

8
PU6B
5

P
+
O 7
6 -

G
LM393DR_SO8

4
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/06/11 Deciphered Date 2009/06/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN. / OTP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B KAW60 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 45 of 50
A B C D
5 4 3 2 1

+3VALW

1
PJP3

1
JUMP_43X79
+1.8VALW

22
1

2
4.7U_1206_25V6K
PJP4

PC64
D JUMP_43X79 D

+5VALW

1
2
RTCVREF
+1.8V

2
PU8
PU7 CM8562IS_PSOP8
1 6
VIN VCNTL +3VALW 1 8
VIN PGND
2 GND NC 5

1
1

2
1U_0603_16V6K
PC65 3 7 PC66 2 7
VREF NC +2.5VSP VFB AGND

PC67
10U_1206_25VAK 1U_0603_6.3V6M

2
PR96 4 8

1
1K_0402_1% VOUT NC
3 VTT VCCA 6

10_0603_1%
9

2
TP

AGND
APL5331KAC-TRL_SO8 4 5
VTT REFEN

PR97
2 1

1K_0402_1%

0.1U_0402_16V7K
@ PR162
@PR162 PC68

9
+0.9VP
1

2
D

0.047U_0402_16V7K
0_0402_5% 2N7002W T/R7 1N SOT-323 22U_1206_10V6M PR98

2
1

200K_0402_1%
PQ24

PR99

PC69
1 2 2 60.4K_0402_1%

1
41 SYSON#

PC71
0.1U_0603_25V7K
G

PR100
S @ PC70
3

PC72
22U_1206_10V6M
2

2
PQ25

1
D 2N7002W T/R7 1N SOT-323
2 1 2
G SUSP 41
C S PR163 C

3
0_0402_5%

PJP5 PJP6
+1.8VALW
2 1 2 1
+3VALWP 2 1
+3VALW +1.8VALWP 2 1
+1.8VALW
JUMP_43X113 JUMP_43X113

1
PJP13

1
JUMP_43X79
PJP7 PJP8

2
2 1 2 1
+5VALWP 2 1
+5VALW +2.5VSP 2 1
+2.5VS

2
JUMP_43X113 JUMP_43X113

2
4.7U_1206_25V6K
PC123

1
PJP10 PJP11
+5VALW
2 1 2 1 RTCVREF
+1.2VALWP 2 1
+1.2VALW +1.5VSP 2 1
+1.5VS PU12
CM8562IS_PSOP8
JUMP_43X113 JUMP_43X113
1 VIN PGND 8
B PJP12 PJP14 B
2 1 2 1 2 7
+0.9VP 2 1
+0.9V +VSBP 2 1
+VSB VFB AGND

2
1U_0603_16V6K
+1.5VSP

PC124
JUMP_43X113 JUMP_43X113
3 6

1
VTT VCCA

AGND
10_0603_1%
1
4 VTT REFEN 5

PR164
2 1

9
PC125

0.047U_0402_16V7K
22U_1206_10V6M PR165

51K_0402_1%
60.4K_0402_1%

PC126
0.1U_0603_25V7K
1

PR166
PC127
1

2
PQ40

1
D 2N7002W T/R7 1N SOT-323
2 1 2
G SUSP 41
S PR167

3
0_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/06/11 Deciphered Date 2009/06/11 Title
+0.9VSP/+1.5VSP/+2.5VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 46 of 50
5 4 3 2 1
5 4 3 2 1

PL8
FBMA-L11-322513-151LMA50T_1210
ISL6227B+ 1 2 B+

2200P_0402_25V7K
D D

2200P_0402_25V7K
10U_1206_25VAK

10U_1206_25VAK

10U_1206_25VAK
1

10U_1206_25VAK
1

1
PC78

PC79

PC80

PC81
PR104

PC82

PC83
51_1206_5%

2
+5VALW

1
PC84

2
4.7U_0805_6.3V6K

1
PR105 PC86

2
PC85 2.2_0603_5% 2.2U_0805_10V6K
PD12 0.1U_0603_25V7K

2
DAP202U_SOT323

1
2

3
8
7
6
5
PQ27
SI4800BDY-T1-E3_SO8 BST_1.8VP

D
D
D
D

BST_1.2VSP
PC87 PC88

14

28
G
S
S
S
0.01U_0402_25V7K 0.01U_0402_25V7K
+1.2VALWP

8
7
6
5
PL9 2 1 12 17 2 1

VIN

VCC
1
2
3
4
1.8UH_SIL104R-1R8PF_9.5A_30% SOFT1 SOFT2 PQ28

D
D
D
D
1 2 PC89 PR106 PR107 PC90 SI4800BDY-T1-E3_SO8
0.1U_0402_16V7K 0_0603_5% 0_0603_5% 0.1U_0402_16V7K
C 1 2 1 1 2BST_1.2VSP-1
6 BOOT1 BOOT2 23 BST_1.8VP-1
1 2 2 1 C
1

8
7
6
5

G
S
S
S
SI4810BDY-T1-E3_SO8
PC91 + @ PR175
D
D
D
D

1
2
3
4
PQ29
220U_D2_4VM_R15 4.7_1206_5%
2
DH_1.2VSP 5
UGATE1 UGATE2 24 DH_1.8VP PL10
+1.8VALWP
680P_0402_50V7K

1.8UH_SIL104R-1R8PF_9.5A_30%
1 2

G
S
S
S LX_1.2VSP LX_1.8VP
4 PHASE1 PHASE2 25 1 2
3.48K_0402_1%

@ PC133
0.01U_0402_25V7K

1
1
2
3
4
1

1
PR110 PR111
1

D 5
D 6
D 7
D 8
+
PC93
PR108

1.27K_0402_1% PU10 1.5K_0402_1% @ PR176 PC92

SI4810BDY-T1-E3_SO8
2

PR109 1 2 ISE_1.2VSP 7 ISL6227CAZ-T_SSOP28 22 ISE_1.8VP 1 2 4.7_1206_5% 220U_D2_4VM_R15


ISEN1 ISEN2

PQ30
0_0402_5%
2

1
2

0_0402_5%
680P_0402_50V7K
DL_1.2VSP 2 27 DL_1.8V PC94
2

12
LGATE1 LGATE2

@ PC134

PR112
0.01U_0402_25V7K
2

4 G

1
3 S
2 S
1 S

2
2
3 26 PR113

2
PGND1 PGND2 10.2K_0402_1%

2
9 VOUT1 VOUT2 20
VSE_1.2VSP 10 19 VSE_1.8VP
VSEN1 VSEN2
10K_0402_1%

1 2 8 21 1 PR115 2 +3VALW
43,45 SPOK EN1 EN2
1
PR116

PR114 10K_0402_1% 15 16
PG1 PG2/REF

1
0.1U_0402_16V7K
@ 10K_0402_1%

GND

DDR

1
PC95
11 OCSET1 OCSET2 18
1

0.1U_0402_16V7K

@ PR118 PR117

1
0_0402_5%

PC96
@ PR119

1 2 0_0402_5% 10K_0402_1%
+5VALW
2

13

2
1

1
PR120

2
PR121 56.2K_0402_1% PR168

2
B 56.2K_0402_1% 10K_0402_5% B
2

2
2

Ipeak=8.5A, Imax=6A
Iocpmin=8.76A
Ipeak=6.47A, Imax=6.47*0.7=4.53A
Iocpmax=13.46A
Iocpmin=7.79A
Iocpmax=11.83A

A A

Security Classification Compal Secret Data


Issued Date 2008/06/11 Deciphered Date 2009/06/11 Title
+1.2VSP/+1.8VP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 47 of 50
5 4 3 2 1
5 4 3 2 1

OCP Setting: Rcs*Ceq=L/Req must be satisfy!


Rcs=((R2+Rntc)/(R1+R2+Rntc))*DCR
VILIM=14.5mV (min) +5VS Req=(R1*(R2+Rntc))/(R1+R2+Rntc)
CPU_B+ B+
PL11
17.5mV(typ) +3VS

PR122 10_0402_5%
FBMA-L18-453215-900LMA90T_1812
1 2
Ivalley=17.5mV/Rcs (min)

2200P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K

0.01U_0402_25V7K
1

100U_25V_M
14.5Mv/Rcs(typ) 1

1
PC99

PC100

PC101
+

PC97

PC98
Iocp=Ivalley+1/2 DeltaI

2
D D

2
1
2

10K_0402_5%

2.2U_0603_6.3V6K
DeltaI=((Vin-Vo)*D)/(F*L)

PR123

2
PC102
Iocp=36A~44A

0.01U_0402_25V7K
2

2
PC103

5
PC104

0.22U_0603_16V7K
2.2U_0603_10V6K
PQ31

1
SI7686DP-T1-E3_SO8

PC105
MAX8774_VCC
19 25
VCC VDD

2
2 1 31 5 PR126 4
8 VID0 PR124 0_0402_5% D0 THRM 0_0603_5%
2 1 32 30 1 2 PR128
8 VID1 D1 BST1
PR125 0_0402_5% 0_0603_5% +CPU_CORE
2 1 33 29 DH1 1 2 PL12

3
2
1
8 VID2 PR127 0_0402_5% D2 PU11 DH1 0.45UH_ETQP4LR45XFC_25A_-25+20%
2 1 34 28 LX1 1 2
8 VID3 D3 MAX8774GTL+_TQFN40
LX1

2
1000P_0603_50V7K 3.3_1206_5%
PR129 0_0402_5%

5
6
7
8

PR131
2 1 35 26 DL1
8 VID4 D4 DL1

4700P_0402_25V7K

2.1K_0402_1%
PR130 0_0402_5% PQ32
8 VID5 2 1 36 D5 PGND1 27 AO4456_SO8

1
PR134
PR132 0_0402_5% J1 SHORT PADS 1 2 PC128

1 1
1
PC106
1 2 1 2 1 16 220P_0402_50V8J R1
28 VGATE PR133 0_0402_5% For EC ATE
PWRGD CSP1
1 2 PC129 4 Rntc

PC107
+3VS 1 2 17 15 220P_0402_50V8J

2
PR135 100K_0402_1% PHASEGD CSN1 @ PR136 PH2

1
PR138 MAX8774_VCC 37 18 AGND 5.11K_0402_1% 10KB_0603_5%_ERTJ1VR103J
C 0_0402_5% TWO-PH GND PR137 C
1 2 1 2

3
2
1
2
VR_ON 1 2 38 40 PR141 PC108 10_0402_5%
@ PR139 PR140 71.5K_0402_1% SHDN# IC 4.32K_0603_1% 4700P_0402_25V7K R2

100_0402_1%
PR142
1 2 2 1 6 11 FB 1 2 1 2 1 2

2
PC110 TIME FB PR143 20K_0402_1% Ceq
100K_0402_5% 2 1 8 9 1 2 1 2 PR144 0_0402_5% PC109
PR145 10K_0402_1% CCV CCI PC111 470P_0402_50V8J 0.22U_0603_16V7K
1 2
28 POUT 1 2 150P_0402_50V8J 3 20
POUT BST2 PR146
1 2 1 2 MAX8774_REF 10 21 DH2 0_0402_5%
PC112 PR147 PC113 0.1U_0603_16V7K REF DH2
1 2
0.1U_0402_16V7K CPU_B+ 1 2 7 22 LX2
200K_0402_1% TON LX2
MAX8774_REF1 2 2 24 DL2
PR148 OFS DL2
31.6K_0402_1% PR150 4 23
VRHOT# PGND2
1

0_0402_5% PC130 220P_0402_50V8J


2N7002W T/R7 1N SOT-323

PR149 2 1 39 13
SKIP# CSP2
169K_0603_1% 1 2 CPU_B+

0_0603_5%
CSN2 14
GNDS
PQ34

PR151
1 2

2
PC131
EP

D 220P_0402_50V8J

2200P_0402_50V7K

4.7U_1206_25V6K

4.7U_1206_25V6K

0.01U_0402_25V7K
2 8 CPU_VCC_SENSE
+3VS
41

12

1
G PQ35

1
SI7686DP-T1-E3_SO8

PC117
S
3

PC114

PC115

PC116
2

2
1

0.22U_0603_16V7K
4
1

1
B PR152 PC118 PR153 B
100_0402_1%

PC119
PR154 200K_0402_1% 4700P_0603_50V7K
2

200K_0402_1% PR155

2
0_0603_5%
2

3
2
1
1 2
2

PL13
1

D 0.45UH_ETQP4LR45XFC_25A_-25+20%
2 PQ36 1 2

3.3_1206_5%
G 2N7002W T/R7 1N SOT-323

5
6
7
8
S
3

2
PR156
PQ38
AO4456_SO8 PR157
1

R1 2.1K_0402_1%
1

1 PR158
8 PSI# 2 PQ37 10_0402_5% 4 PH3

1
1
1000P_0603_50V7K
2 FDV301N_NL_SOT23-3 PR159 10KB_0603_5%_ERTJ1VR103J

PC120
3 5.11K_0402_1%
3

1 2 1 2

2
3
2
1
@ PC121 R2 Rntc
1 2 PC122
8 CPU_VSS_SENSE 0.22U_0603_16V7K
4700P_0402_25V7K 1 2

CSP2 Ceq

PR160
A 1 2 A

0_0402_5%

<BOM Structure>

Security Classification Compal Secret Data


Issued Date 2008/06/11 Deciphered Date 2009/06/11 Title
+CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 48 of 50
5 4 3 2 1
5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1


for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

D Change PQ9, PQ10, PQ11 from SB944070000(S TR AO4407 D

1 material issue. Change to currently design 0.1 44 1P SO8 W/D) to SB00000DL00(S TR S TR AO4407A 1P SO8) 08,07/22 to PVT

Change PQ31 and PQ35 from SB578400080(S TR SI7840-T1


-E3 1N SO8) to SB000008L80(S TR SI7686DP-T1-E3 1N
2 material issue. Change to currently design 0.1 48
POWERPAK SO8)
08,07/22 to PVT

Change PQ7 and PQ8 from SB000002W80(S TR AO4916 2N


material issue. AO4916 will be EOL, change to AO4932 0.1 43 SO8) to SB00000BG00(S TR AO4932 2N SO8) 08,07/22 to PVT
3
4 BOM error BOM error 0.1 48
Change PR141 from SD014200180(S RES 1/10W 2K 0603 1%)
to SD014432180(S RES 1/10W 4.32K 0603 1%) 08,07/22 to PVT

Change PQ12, PQ17, PQ29, PQ30 from SB548100020(S TR


5 material issue.
SI4810 will be EOL, change to SI4894. 0.1 47 SI4810BDY-T1-E3 1N SO8) to SB00000D300(S TR SI4894BDY- 08,07/22 to PVT
T1-E3 1N SO8)

Add PR123 SD028100280(S RES 1/16W 10K 0402 5%)


6 Add VGATE pull high resistor. Add VGATE pull high resistor. 0.1 48 08,07/22 to PVT

7
C C

10

11

B 12 B

13

14

15

16

17

18
A A

Security Classification Compal Secret Data


Issued Date 2008/06/11 Deciphered Date 2009/06/11 Title
PIR(PWR)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 49 of 50
5 4 3 2 1
5 4 3 2 1

PHASE PAGE MODIFICATION LIST PURPOSE


-----------------------------------------------------------------------------------------------------------------------------------------------
PVT/MP P.19 & 24 Update CRT_DET & CRT_DET# net name NA
P.18 & 19 Change CRT_DET from GPIO61 to GPIO0 & reserved R741 , R742 , R743 For ACER AP test CRT detect feature
P.20 Remove L71 , C694 & C697 For +3Vs (1.5V) , +5Vs (0.388V) , +1.8Vs (0.154V) on S5 leakege issue
P.28 Change R519 from 100K to 10K For RS690MC ENBKL had unexpected 3.3V pulse before normal display & white screen
D
flash symptom appear D

P.14 Reserved U48 , U49 , R744 , R745 , R746 , R747 , C763 For RS690MC ENBKL , ENVDD if had unexpected 3.3V pulse before normal display
P.28 & 31 Modify WL_ON_LED# from KB926 to JMINI1 control WL LED activity behavior controlled by wireless mini card itself
P.38 Update SW9 Footprint & P/N NA
P.41 Change R586 from 100K to 10K For Susp# had 3V level glitch when G3 to S5 (Plug AC in) & caused +5Vs /+3Vs had
leakege immediately

P.6 Change D4 as SC1BAS16000(S DIO BAS16PT SOT-23) Sourcer recommend


P.26 Change U11 as SA000019910(S IC EE 1K CAT93C46VI-GT3 SOIC 8P) SA093461070 (S IC EE 1K SO-8 I AT93C46-10SI-2.7) EOL
P.50 Change T1 as SP050001210 / S X'FORM_ NS0013LF LAN (BOTHHAND) MHPC X'form part not for ABO , Sourcer recommend
P.18 Delete R695,R179,R484 for SB_TEST pin AMD reference schematic
P.20 Reserved C764 (1u_0402) AMD reference schematic & design guide
P.38 Modify WL_LED power rail as +3Vs NA
P.28 & 38 Modify LED control of SATA drive from EC to SB (Add Q67) EC(media_led#/pin86 , reference sata_led# from SB) control behavior abnormal
P.17 Change C510 , C511 of 14.318MHz as 27P from 22P NA
P.37 & 25 Change D5 , D21 as SC1BAS16000 NA
C C
P.26 Add L77 , C765 , C766 , C767 & change R645 / R647 as L78 / L79 , EMI request
reserved C719 , C724

P.31 & 34 Stuff L66 , L67 , L68 & remove R615 , R616 , R598 , R599 , R600 , R601 EMI request
P.29 Stuff D28 ESD request
P.6 Update net EN_DFAN1_R NA
P.6 Update JCPU1 PCB footprint as SOC127MM48X51-948 NA
P.26 Add R749 , R750 (300ohm_0402) For LAN external EEPROM program issue
P.31 Add D32 (SCA00000A00) ESD request
P.28 & 31 Reserved R751 & R752 Reserved WL_LED controlled by EC (Navarrow project)
P.24 Change C411 & C412 PN from SE081680k80 to SE071680J80 AP Code
P.6 Change U1 as SA00001Z900 (S IC APL5605KI-TRL SOP 8P) (SA009930010) S IC G993P1UF SOP 8P FAN LDO EOL
P.15 Change C330 as 0402 package NA

B B

-----------------------------------------------------------------------------------------------------------------------------------------------

ZZZ
LA4661MB Rev0 : DA600009Z00

PCB 06B LA-4661P REV1 M/B


LA4661MB with Sub/B Rev1 : DAZ06B00100

A A

Security Classification Compal Secret Data


Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
PIR-HW & Option Component
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KAW60 LA-4661P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, August 08, 2008 Sheet 50 of 50
5 4 3 2 1

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