A B C D E

1 1

Compal confidential 2

IGL50/51 Schematics Document

Mobile Yonah uFCPGA with Intel
3
Calistoga_GM/PM+ICH7-M core logic 3

2006-07-31
REV:0.2

4 4

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C u s tom I G L50/51 LA-3771 0 .2
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 1 of 48
A B C D E
 A B C D E

ZZZ1
Compal confidential
File Name : LA-3061
PCB

PCI-E x 16 VGA Sub BD

1 Thermal Sensor Mobile Yonah 1

V RAM AD M1032 uFCBGA-479/uFCPGA-478 CPU

LVDS Panel
Interface 128/ 256MB page 4
page 4, 5, 6
Clock Generator
Fan Control H_A#(3..31)
FSB I CS 954306
page 4
H_D#(0..63) 533/667MHz

page 15
Nvidia
G7 2/G73M PCI-E x 16 DDR2 -400/533/667 DDR2-SO-DIMM X2
page 18 Intel Calistoga GMCH BANK 0, 1, 2, 3 page 13,14

PCBGA 1466 Dual Channel

LVDS Panel
Interface page 16
page 7, 8, 9, 10,11,12
2 Mini-PCIE Card 2

page 28
CRT & TV OUT DMI
page 17, 36 New Card
PCIE x3
Connector x2
page 37
USB2.0
LAN I/F
Intel ICH7-M AC-LINK

PCI BUS mBGA-652

3.3V 33 MHz

page 19, 20, 21, 22

USB conn X3
page 31, 37

10/100/1G LAN CardBus Controller 1394+CARD MO DEM

RTL8110CL/SBL E NE CB1410 READER R5C832 B T Conn A MOM page 29
LPC BUS
page 27 page 24 page 26 page 28
3 3
SubWoofer
page 31

RJ45 CONN Slot 0 1394 3IN1 READER ENE KB910/L

page 28 page 25 page 26 page 38 Audio AD1986A AMP & Audio Jack
page 33 A MOM page 29 page 30

RTC CKT. SATA HDD SPR CONN.

page 20
Int.KBD Connector x2 *RJ45 CONN
page 32
page 23 *MIC IN JACK
Power On/Off CKT. *LINE OUT JACK
BIOS PATA CDROM *1394 CONN
page 32 page 34
*SPDIF CONN
Connector *DC JACK
page 23
T ouch Pad *TVOUT CONN
page 37 *USB CONN x1
4
DC/DC Interface CKT. 4

page 35
*CIR x1
page 34

Power Circuit DC/DC Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10
page 39~45 Block Diagram
THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C u s tom I G L50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 2 of 48
A B C D E

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 A

B+ +VSB
Power Block Diagram Of The IMVP6 +3VALW KB910L mA
+5VALW SB 160mA
RTCVREF SPOK#
MOS
RTL8110SBL/CL
(3.3V) TP0610K
VIN Regulator MOS +5VS +5VALW +VDDA
VIN +CPU_CORE CPU 36A
Detector G920AT24 AO4916

SUSP MOS +VCCP CPU 2.5A

DC IN B+ SI9182DH
PWM CONT. SI4800 NB 9.8A
MAX8734AEE (14.7A)
+3.3VS
BATT+ Switch +3VALW +5VS EXPRESS CARD 1A
Regulator HDD 1.5A
MOS SUSP MOS ODD 1.8A
BATT APL5912-KAC
AO4916 SI4800
+2.5VS MDC 300mA
MOS SUSP# +1.8VS APA2066 1A
+1.8V TPA0211 mA
AO4407 +0.9VS
AD1986 70mA
MOS Regulator SUSP MOS USB PORT * 6 3A
U:SI4810B APL5331KAC SI4800
Charger L:SI4810B
MB39A126 OUT2
SYSON +1.5VS +3VS NB 480mA
PWM ON2
+CPU_CORE P.40 EXPRESS CARD 1A
OZ813 SUSP#
ON1 MOS CLK_GEN 200mA
OUT1
+1.05VS
U:SI7840 X1 U:SI4810B LCDVCC 1A
L:AO4410X2 L:SI4810B VGA CARD (G7XM) 655mA
MOS OUT2 SB 680mA
AO4916
VCCP PWM R5C832 mA
VID[0..6] PWM CONT. SUSP#
ISL6269CRZ BIOS ROM 15mA
MAX8770GTL+
KB910L 200mA
CB1410 mA
O MEANS ON
PCI DEVICES Voltage Rails X MEANS OFF
1

+2.5VS VGA CARD (G7XM) 130mA 1

EXTERNAL IDSEL# R E Q/GNT# PIRQ +5VS NB (143mA)

+3VS
CARD BUS power +2.5VS
AD20 2 PCI_PIRQA# plane +B +1.8VS
CB1410 +5VALW +1.8V +1.5VS
State LDO3 +VGA_CORE
CARD READER & 1394 +3VALW +5V +1.2VS DDR2_DIMM 8A
AD22 0 PCI_PIRQG# PCI_PIRQH# S4 : STD LDO5 +0.9VS +1.8V
R5C832 +CPU_CORE NB (667Mhz) 3.1A
S5 : SOFT OFF +VCCP
L A N CONTROLLER
AD17 3 PCI_PIRQF#
RTL8110SBL/CL O O O O +1.8VS GDDR2 6A
S0
VGA CARD (G7XM) 4.06A
PCIE LANE USB S1 O O O O
LANE DEVICE PORT DEVICE S3 : STR O O O X
+0.9VREF DDR2_DIMM 10mA
0 LEFT SIDE S5 S4/AC O O X X
1 Express Card
1 BLUE TOOTH O X X X
S5 S4/ Battery only +0.9VS GDDR2 1A
2 RIGHT SIDE
2 Mini Card S5 S4/AC & Battery
X X X X
3 JP810 don't exist DDR2_DIMM 2A
4 RIGHT SIDE R119(Ra)=100K Ohm
BRD_ID
I2C / SMB Address 5 CMOS +1.5V SB 40mA
KB910/L (SM1-Pulled-Up 5V) 6 RIGHT SIDE MB_ID ID MB REV# R115(Rb) Vab
DEVICE ADDRESS R/W 0 R0.1 (EVT) 0 0V +1.5VS NB 8.9A(13.8A)
MB ID P NAME
AT24C16AN A3/A2 H BOM Structure 0 IGL-50
1 R0.2 (DVT) 8.2K 0.25V SB 3.8A
SMART BATTERY 17/16 H MARK FUNCTION 2 R0.3 (PVT) 18K 0.50V MiniCard 1A
1 IGL-51
KB910/L (SM2-Pulled-Up 3.3V) @ NC FOR ALL 3 R1.0 (MP) 33K 0.82V EXPRESS CARD 0.65A
ADM1032AR 99/98 H EXP@ PCIE-NEW CARD 4 56K 1.19V VGA CARD (G7XM) 2A
G7xM (I2CC-Pulled-Up 3.3V) BT@ BLUE TOOTH 5 100K 1.65V
G781-1 (RESERVED) 9B/9A UMA@ Internal 945GM 6 200K 2.20V
ICH7M SM Bus VGA@ External G7xM 7 NC 3.30V
ICS9LPR325AKLFT D3/D2 H (3.3V) SUBWOOFER@ SUBWOOFER
DDR II DIMM0 A1/A0 H (3.3V) HGT30@ HGT30 Compal Secret Data
Security Classification
2005/03/10 2006/03/10
Compal Electronics, Inc.
DDR II DIMM1 A3/A2 H (3.3V) CB@ PCMCIA/CARD BUS Title
Issued Date Deciphered Date Notes List
Express Card NC (2.5V) GIGA@ 8110SBL(SCL)Giga LAN THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size D oc um ent Num ber R ev
10/100@ 8110CL 10/100Mb LAN C u s tom I G L50/51 LA-3771 0 .1
Mini-Express NC (2.5V) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 3 of 48
A
 5 4 3 2 1

+ VCCP
7 H_ A# [3..31] H_ D #[0..63] 7
JP 1A This shall place near CPU
I TP_TDI R 98 1 2 56_0402_5%
H_ A #3 J4 E22 H_ D#0
H_ A #4
H_ A #5
L4
A3#
A4#
YONAH D0#
D1#
F24 H_ D#1
H_ D#2
ITP_TMS R 97 1 2 56_0402_5% ITP_DBRESET# R 85 1 2 @ 200_0402_1% P AD T13
M3 E26
H_ A #6 A5# D2# H_ D#3 ITP_TDO R 101 1 56_0402_5% ITP_BPM#0 T17
K5 H22 2 P AD
H_ A #7 A6# D3# H_ D#4 ITP_BPM#1 T18
M1 F23 P AD
H_ A #8 A7# D4# H_ D#5 ITP_BPM#5 R 103 1 56_0402_5% ITP_BPM#2 T20
N2 G25 2 P AD
H_ A #9 J1 A8# D5# E25 H_ D#6 ITP_BPM#3 T16
D A9# D6# P AD D
H_ A#10 N3 E23 H_ D#7 ITP_TRST# R 95 1 2 56_0402_5% ITP_BPM#4 P AD T19
H_ A#11 A10# D7# H_ D#8
P5 K24
H_ A#12 P2 A11# D8# G24 H_ D#9 ITP_TCK R 96 56_0402_5%
1 2
H_ A#13 A12# D9# H_ D#10
L1 J24
H_ A#14 A13# D10# H_ D#11
P4 J23
H_ A#15 P1 A14# D11# H26 H_ D#12
H_ A#16 A15# D12# H_ D#13
R1 F26
H_ A#17 A16# D13# H_ D#14
Y2 K22
H_ A#18 A17# D14# H_ D#15
U5 H25
H_ A#19 A18# D15# H_ D#16
R3 N22
H_ A#20 A19# D16# H_ D#17
W6 K25
H_ A#21 A20# D17# H_ D#18
U4 P26
H_ A#22 Y5 A21# D18# R23 H_ D#19
H_ A#23 A22# D19# H_ D#20
U2 L25
H_ A#24 A23# D20# H_ D#21
R4 L22
H_ A#25 T5 A24# D21# H_ D#22
ADDR GROUP DATA GROUP L23
H_ A#26
H_ A#27
T3
W3
A25#
A26#
D22#
D23#
M23
P25
H_ D#23
H_ D#24
Thermal Sensor G781F
H_ A#28 A27# D24# H_ D#25
W5 P22
H_ A#29 A28# D25# H_ D#26
Y4 P23
H_ A#30 A29# D26# H_ D#27
W2 T24
H_ A#31 A30# D27# H_ D#28
7 H_ REQ#[0..4] Y1 R24 +3VS
A31# D28# L26 H_ D#29
H _REQ#0 D29# H_ D#30 U1 6
K3 T25
H _REQ#1 REQ0# D30# H_ D#31 H_ T H ERMDA
H2 N24 2 1 2 1
H _REQ#2 K2 REQ1# D31# AA23 H_ D#32 C 311 D+ VDD1 C 310 0 . 1 U_0402_16V4Z
H _REQ#3 REQ2# D32# H_ D#33 H_ T H ERMDC
J3 AB24 1 2 3 6
H _REQ#4 REQ3# D33# H_ D#34 2200P_0402_50V7K D- ALERT#
L5 V24
REQ4# D34# H_ D#35 EC_SMB_CK2 T HERM#
V26 33 EC_SMB_CK2 8 4 2 1 +3VS
H _ADSTB#0 L2 D35# W25 H_ D#36 SCLK THERM# 10K_0402_5% R 226
7 H_ADSTB#0 ADSTB0# D36#
H _ADSTB#1 V4 U23 H_ D#37 E C_SMB_DA2 7 5
7 H_ADSTB#1 ADSTB1# D37# 33 E C_SMB_DA2 SDATA GND
U25 H_ D#38
C D38# U22 H_ D#39 C
D39# H_ D#40 G781F_SOP8
AB25
D40# H_ D#41 Address:100_1100
W22
D41# Y23 H_ D#42
C LK_CPU_BCLK A22 D42# H_ D#43
15 C LK_CPU_BCLK AA26
C LK_CPU_BCLK# A21 BCLK0 D43# H_ D#44
15 C LK_CPU_BCLK# BCLK1 HOST CLK D44#
Y26
Y22 H_ D#45
D45# AC26 H_ D#46
D46# H_ D#47
AA24
H_ A DS# D47# H_ D#48
7 H_ ADS# H1 AC22
H_ B NR# E2 ADS# D48# AC23 H_ D#49
7 H_ B NR# BNR# D49#
H_ B PRI# G5 AB22 H_ D#50
7 H_ B PRI# BPRI# D50#
H_ BR0# F1 AA21 H_ D#51
7 H_ BR0# BR0# D51#
H_ D EFER# H5 AB21 H_ D#52
7 H_ D EFER# DEFER# D52#
H_ D R D Y# F21 AC25 H_ D#53
7 H_ D R D Y# DRDY# D53#
R 84 H_ HI T# G6 AD20 H_ D#54
7 H_ HIT# HIT# D54#
56_0402_5% H_ HI TM# E4 CONTROL AE22 H_ D#55
7 H_ HITM# HITM# D55#
1 2 H_ IE RR# D20 AF23 H_ D#56
+ VCCP H _LOCK# IERR# D56# H_ D#57
7 H_LOCK# H4 AD24
H_RESET# LOCK# D57# H_ D#58
7 H_RESET# B1 AE21
RESET# D58# H_ D#59
AD21
D59# H_ D#60
7 H_ R S#[0..2] AE25
H_ RS#0 D60# H_ D#61
F3 AF25
H_ RS#1 F4 RS0# D61# AF22 H_ D#62 +5VS
H_ RS#2 RS1# D62# H_ D#63
G3 AF26
H_ T R DY# RS2# D63#
7 H_ T R DY# G2
TRDY# +VSB 1 2
J26 H_ D INV #0
DINV0# H_ D INV#0 7
M26 H_ D INV #1 C 303
DINV1# H_ D INV#1 7
ITP_BPM#0 AD4 V23 H_ D INV #2 1 0 U_1206_10V4Z
BPM0# DINV2# H_ D INV#2 7 +3VS
ITP_BPM#1 AD3 AC20 H_ D INV #3 2 1 C 309
BPM1# DINV3# H_ D INV#3 7

1
2
5
6
ITP_BPM#2 AD1 0 . 0 1U_0402_25V4Z
B ITP_BPM#3 BPM2# D Q19 B
AC4

P
H_ D STBN#[0..3] 7

2
BPM3# H_ DSTBN#0 G SI3456BDV-T1-E3_TSOP6
H23 33 E N_ F AN1 3
ITP_DBRESET# C20 DSTBN0# H_ DSTBN#1 +IN F AN1 _ON R 222
21 ITP_DBRESET# M24 1 3
H_ D B SY# DBR# DSTBN1# H_ DSTBN#2 OUT S
7 H_ D B S Y# E1 W24 2 10K_0402_5%
H _DPSLP# DBSY# DSTBN2# H_ DSTBN#3 -IN U1 5 A
B5 AD23

4
20 H_DPSLP# H_DSTBP#[0..3] 7

G
H _DPRSTP# E5 DPSLP# DSTBN3# G22 H_DSTBP#0 LM358A_SO8
2 0,45 H_DPRSTP#

1
H_ DPW R# DPRSTP# DSTBP0# H_DSTBP#1
D24 N25

4
7 H_ D PW R# DPWR# DSTBP1#
ITP_BPM#4 AC2 MISC Y25 H_DSTBP#2
45 H_ PROCHOT# ITP_BPM#5 PRDY# DSTBP2# H_DSTBP#3 J P2
AC1 AE24
PREQ# DSTBP3#
1 R 83 2 H_ PROCHOT#D21 1 2 F AN1
+ VCCP 68_0402_5% PROCHOT# R 218 14
25

C305 10U_0805_10V4Z
1000P_0402_50V7K
H_ PW RGOOD D6 100K_0402_5%
20 H_ PW RGOOD PWRGOOD 3

1
H_ C PUSLP# D7 1 1
7 ,20 H_ C PUSLP# SLP#

1
ITP_TCK AC5 R 219 ACES_85205-0300
I TP_TDI TCK H_ A 20M# 150K_0402_5%
AA6 A6 H_ A20M# 20
ITP_TDO AB3 TDI A20M# A5 H_ F ERR# D 11
TDO FERR# H_ F ERR# 20 2 2
R 71 1 2 @ 1K_0402_5% TEST1 C26 C4 H_ IGNN E# 1 N4148_SOD80

2
TEST1 IGNNE# H_ IGNNE# 20
R 74 1 2 51_0402_5% TEST2 D25 B3 H_ INI T#

2
TEST2 INIT# H_ INIT# 20

C307
ITP_TMS AB5 C6 H_ IN TR
TMS LINT0 H_ INTR 20
ITP_TRST# AB6 B4 H _ NMI
TRST# LINT1 H _ NMI 20
LEGACY CPU
THERMAL
H_ T H ERMDA A24 D5 H_STPCLK#
THERMDA DIODE STPCLK# H_STPCLK# 20
H_ T H ERMDC A25 A3 H_ S MI#
THERMDC SMI# H_ S MI# 20 33 F AN_SPEED1
H_ T HERMTRIP# C7 5 1
7 ,20 H_ T HERMTRIP# THERMTRIP# +IN
7
OUT C 308
H_THERMDA, H_THERMDC routing together. 6
-IN
TYCO_1-1674770-2_Yonah~D U1 5B 1000P_0402_50V7K
Trace width / Spacing = 10 / 10 mil ME@ LM358A_SO8 2

A + VCCP A

+ VCCP
1

R 100
R 73 H _DPSLP# 1 2
@ 56_0402_5% @ 56_0402_5%
R 99 Security Classification Compal Secret Data Compal Electronics, Inc.
2 2

H _DPRSTP# 1 2 2005/10/06 2006/10/06 Title

Issued Date Deciphered Date
B

@ 56_0402_5%
THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Yonah CPU in mFCPGA479
E

H_ PROCHOT# 3 1 OCP# Size D oc um ent Num ber R ev

OCP# 21 ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Q4 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C us tom I GL 50/51 LA-3771 0 .1
@ PMBT3904_SOT23 MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 4 of 48
5 4 3 2 1

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 5 4 3 2 1

+ VCCP +CPU_CORE
Length match within 25 mils J P1B J P1C
D
The trace width 18 mils space D

1
45 VC CSENSE VC CSENSE AF7 AB26 AE18 K1
+ CPU_CORE 7 mils 45 VSSENSE
V SSENSE AE7 VCCSENSE
VSSSENSE
VSS
VSS
AA25 AE17 VCC
VCC
VSS
VSS
J2
R 69 R 93 AD25 AB15 M2
+ CPU_GTLREF 1K_0402_1% 100_0402_1% VSS VCC VSS
AE26 AA15 N1
VC CSENSE VSS VCC VSS
1 2 B26 AB23 AD15 T1
2
+1.5VS VCCA VSS VCC VSS
AC24 AC15 R2
R 94 VSS VCC VSS
K6 AF24 AF15 V2
100_0402_1% + VCCP VCCP VSS VCC VSS
J6 AE23 AE15 W1
1

V SSENSE VCCP VSS VCC VSS

1 2 1 1 M6 AA22 AB14 A26
C 122 C 132 VCCP VSS VCC VSS
N6 AD22 AA13 D26
R 62 T6
VCCP
VCCP
YONAH VSS
VSS
AC21 AD14
VCC
VCC
VSS
VSS
C25
2K_0402_1% R6 AF21 AC13 F25
2 2 VCCP VSS VCC VSS
K21 AB19 AF14 B24
2

VCCP VSS VCC VSS

J21 AA19 AE13 A23
M21 VCCP VSS AD19 AB12 VCC VSS D23
1 0 U_0805_10V4Z 0 . 0 1U_0402_25V4Z VCCP VSS VCC VSS
Close to CPU pin N21
VCCP VSS
AC19 AA12
VCC YONAH VSS
E24
Close to CPU pin AD26 within 500mils.
T21
R21
VCCP VSS
AF19
AE19
AD12
AC12
VCC VSS
B21
C22
VCCP VSS VCC VSS
within 500mils. V21
VCCP VSS
AB16 AF12
VCC VSS
F22
W21 AA16 AE12 E21

POWER, GROUNG, RESERVED SIGNALS AND NC

VCCP VSS VCC VSS
V6 AD16 AB10 B19
G21 VCCP VSS AC16 AB9 VCC VSS A19
VCCP VSS VCC VSS
AF16 AA10 D19
VSS VCC VSS
AE16 AA9 C19
H_ P SI# AE6 VSS AB13 AD10 VCC VSS F19
45 H_ PSI# PSI# VSS VCC VSS
AA14 AD9 E19
C P U_ VID0 VSS VCC VSS
45 C P U_ VID0 AD6 AD13 AC10 B16
C P U_ VID1 VID0 VSS VCC VSS
45 C P U_ VID1 AF5 AC14 AC9 A16
C P U_ VID2 AE5 VID1 VSS AF13 AF10 VCC VSS D16
45 C P U_ VID2 VID2 VSS VCC VSS
C P U_ VID3 AF4 AE14 AF9 C16
45 C P U_ VID3 VID3 VSS VCC VSS
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 C P U_ VID4 AE3 AB11 AE10 POWER, GROUND F16
C 45 C P U_ VID4 VID4 VSS VCC VSS C
C P U_ VID5 AF2 AA11 AE9 E16
45 C P U_ VID5 VID5 VSS VCC VSS
C P U_ VID6 AE2 AD11 AB7 B13
45 C P U_ VID6 VID6 VSS VCC VSS
AC11 AA7 A14
VSS AF11 AD7 VCC VSS D13
133 0 0 1 VSS VCC VSS
+ CPU_GTLREF AD26 AE11 AC7 C14
GTLREF VSS VCC VSS
AB8 B20 F13
C PU_BSEL0 VSS VCC VSS
15 CPU_BSEL0 B22 AA8 A20 E14
C PU_BSEL1 B23 BSEL0 VSS AD8 F20 VCC VSS B11
166 0 1 1 15 CPU_BSEL1
C PU_BSEL2 BSEL1 VSS VCC VSS
15 CPU_BSEL2 C21 AC8 E20 A11
BSEL2 VSS VCC VSS
AF8 B18 D11
C OMP0 R26 VSS AE8 B17 VCC VSS C11
C OMP1 COMP0 VSS VCC VSS
U26 AA5 A18 F11
C OMP2 COMP1 VSS VCC VSS
U1 AD5 A17 E11
C OMP3 V1 COMP2 VSS AC6 D18 VCC VSS B8
COMP3 VSS VCC VSS
AF6 D17 A8
VSS VCC VSS
AB4 C18 D8
VSS VCC VSS
+ CPU_CORE E7 AC3 C17 C8
AB20 VCC VSS AF3 F18 VCC VSS F8
VCC VSS VCC VSS
AA20 AE4 F17 E8
VCC VSS VCC VSS
AF20 AB1 E18 G26
VCC VSS VCC VSS
Resistor placed within AE20 AA2 E17 K26
VCC VSS VCC VSS
27.4_0402_1%

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

AB18 AD2 B15 J25

VCC VSS VCC VSS
1

0.5" of CPU pin.Trace AB17 AE1 A15 M25

AA18 VCC VSS B6 D15 VCC VSS N26
should be at least 25 VCC VSS VCC VSS
R70

R72

R102

R104

AA17 C5 C15 T26

mils away from any VCC VSS VCC VSS
AD18 F5 F15 R25
VCC VSS VCC VSS
other toggling signal. AD17 E6 E15 V25
2

VCC VSS VCC VSS

AC18 H6 B14 W26
VCC VSS VCC VSS
AC17 J5 A13 H24
VCC VSS VCC VSS
AF18 M5 D14 G23
AF17 VCC VSS L6 C13 VCC VSS K23
VCC VSS VCC VSS
P6 F14 L24
B VSS VCC VSS B
R5 E13 P24
VSS VCC VSS
D2 V5 B12 N23
RSVD VSS VCC VSS
F6 U6 A12 T23
RSVD VSS VCC VSS
D3 Y6 D12 U24
RSVD VSS VCC VSS
C1 A4 C12 Y24
AF1 RSVD VSS D4 F12 VCC VSS W23
RSVD VSS VCC VSS
D22 E3 E12 H21
RSVD VSS VCC VSS
C23 H3 B10 J22
C24 RSVD VSS G4 B9 VCC VSS M22
RSVD VSS VCC VSS
AA1 K4 A10 L21
RSVD VSS VCC VSS
AA4 L3 A9 P21
RSVD VSS VCC VSS
AB2 P3 D10 R22
RSVD VSS VCC VSS
AA3 N4 D9 V22
RSVD VSS VCC VSS
M4 T4 C10 U21
RSVD VSS VCC VSS
N5 U3 C9 Y21
T2 RSVD VSS Y3 F10 VCC VSS
RSVD VSS VCC
V3 W4 F9
RSVD VSS VCC
B2 D1 E10
RSVD VSS VCC
C3 C2 E9
RSVD VSS VCC
T22 F2 B7
RSVD VSS VCC
B25 G1 A7
RSVD VSS VCC
F7
VCC

TYCO_1-1674770-2_Yonah~D TYCO_1-1674770-2_Yonah~D
ME@ ME@

A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Yonah CPU in mFCPGA479
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C us tom I GL 50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 5 of 48
5 4 3 2 1
 5 4 3 2 1

D + CPU_CORE D

1 1 1 1 1 1
Place these capacitors on L8 C 318 C 326 C 151 C 171 C 346 C184
(North side,Secondary Layer) 1 0 U_0805_6.3V6M 1 0 U_0805_6.3V6M 1 0 U_0805_6.3V6M 1 0 U_0805_6.3V6M 1 0 U_0805_6.3V6M 1 0 U_0805_6.3V6M
2 2 2 2 2 2

+ CPU_CORE

1 1 1 1 1 1 1 1
Place these capacitors on L8 C 325 C 186 C 341 C 178 C 316 C 185 C 166 C342
(North side,Secondary Layer) 1 0 U_0805_6.3V6M 1 0 U_0805_6.3V6M 1 0 U_0805_6.3V6M 1 0 U_0805_6.3V6M 1 0 U_0805_6.3V6M 1 0 U_0805_6.3V6M 1 0 U_0805_6.3V6M 1 0 U_0805_6.3V6M
2 2 2 2 2 2 2 2

+ CPU_CORE

1 1 1 1 1 1 1 1
Place these capacitors on L8 C 183 C 170 C 334 C 319 C 172 C 333 C 181 C 176
(Sorth side,Secondary Layer) 1 0 U_0805_6.3V6M 1 0 U_0805_6.3V6M 1 0 U_0805_6.3V6M 1 0 U_0805_6.3V6M 1 0 U_0805_6.3V6M 1 0 U_0805_6.3V6M 1 0 U_0805_6.3V6M 2 2 U_0805_6.3V6M
2 2 2 2 2 2 2 2

C C
+ CPU_CORE

1 1 1 1 1 1 1 1
Place these capacitors on L8 C 150 C 165 C 345 C 173 C 179 C 177 C 317 C182
(Sorth side,Secondary Layer) 1 0 U_0805_6.3V6M 1 0 U_0805_6.3V6M 1 0 U_0805_6.3V6M 1 0 U_0805_6.3V6M 1 0 U_0805_6.3V6M 2 2 U_0805_6.3V6M 1 0 U_0805_6.3V6M 1 0 U_0805_6.3V6M
2 2 2 2 2 2 2 2

Mid Frequence Decoupling

+ CPU_CORE

ESR <= 1.5m ohm

330U_V_2.5VK_R9

330U_V_2.5VK_R9

330U_V_2.5VK_R9

330U_V_2.5VK_R9

330U_V_2.5VK_R9

1 1
+ +
C324
330U_V_2.5VK_R9
1 1 1 1
+ + + +
Capacitor > 1980uF

C180

C175

C339

C320

C343

North Side Secondary

South Side Secondary
2 2 2 2 2 2
B B

+ VCCP

1
+
1 1 1 1 1 1
C 109 Place these inside
C 190 C 136 C 138 C 137 C 189 C188 socket cavity on L8
2 2 0U_D2_4VM 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z (North side
2 2 2 2 2 2 2 Secondary)

A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU Bypass capacitors
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C us tom I GL 50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 6 of 48
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

U1 4

4 H_ D # [0..63] H_ A#[3..31] 4 PM Description at page15.

U1 4 A VGA@ U1 4B
H_ D#0 F1 H9 H_ A #3
H_ D#1 J1 HD0# HA3# C9 H_ A #4 D M I_TXN0 AE35 K16 MC H_CLKSEL0
HD1# HA4# 21 D MI_TXN0 DMIRXN0 CFG0 MC H_CLKSEL0 15
H_ D#2 H1 E11 H_ A #5 U1 4 D M I_TXN1 AF39 K18 MC H_CLKSEL1
HD2# HA5# 21 D MI_TXN1 DMIRXN1 CFG1 MC H_CLKSEL1 15
H_ D#3 J6 G11 H_ A #6 D M I_TXN2 AG35 J18 MC H_CLKSEL2
HD3# HA6# 21 D MI_TXN2 DMIRXN2 CFG2 MC H_CLKSEL2 15
H_ D#4 H3 F11 H_ A #7 D M I_TXN3 AH39 F18 C F G3 P AD T9
HD4# HA7# 21 D MI_TXN3 DMIRXN3 CFG3
H_ D#5 K2 G12 H_ A #8 E15 C F G4 T3
D HD5# HA8# CFG4 P AD D
H_ D#6 G1 F9 H_ A #9 F15 C F G5
HD6# HA9# CFG5 C F G5 11
H_ D#7 G2 H11 H_ A#10 DMI_TXP0 AC35 E18 C F G6 P AD T10
HD7# HA10# 21 DMI_TXP0 DMIRXP0 CFG6
H_ D#8 K9 J12 H_ A#11 GML DMI_TXP1 AE39 D19 C F G7
HD8# HA11# 21 DMI_TXP1 DMIRXP1 CFG7 C F G7 11
H_ D#9 K1 G14 H_ A#12 UMA_ GML@ DMI_TXP2 AF35 D16 C F G8 P AD T7
HD9# HA12# 21 DMI_TXP2 DMIRXP2 CFG8

DMI
H_ D#10 K7 D9 H_ A#13 DMI_TXP3 AG39 G16 C F G9
HD10# HA13# 21 DMI_TXP3 DMIRXP3 CFG9 C F G9 11
H_ D#11 J8 J14 H_ A#14 E16 C F G10 T5
HD11# HA14# CFG10 P AD
H_ D#12 H4 H13 H_ A#15 D15 C F G11
HD12# HA15# CFG11 C F G11 11
H_ D#13 J3 J15 H_ A#16 D MI _RXN0 AE37 G15 C F G12
HD13# HA16# 21 D MI_RXN0 DMITXN0 CFG12 C F G12 11
H_ D#14 K11 F14 H_ A#17 D MI _RXN1 AF41 K15 C F G13
HD14# HA17# 21 D MI_RXN1 DMITXN1 CFG13 C F G13 11

C FG
H_ D#15 G4 D12 H_ A#18 D MI _RXN2 AG37 C15 C F G14 T2
HD15# HA18# 21 D MI_RXN2 DMITXN2 CFG14 P AD
H_ D#16 T10 A11 H_ A#19 D MI _RXN3 AH41 H16 C F G15 P AD T8
HD16# HA19# 21 D MI_RXN3 DMITXN3 CFG15
H_ D#17 W11 C11 H_ A#20 G18 C F G16
HD17# HA20# CFG16 C F G16 11
H_ D#18 T3 A12 H_ A#21 H15 C F G17 T1
HD18# HA21# CFG17 P AD
H_ D#19 U7 A13 H_ A#22 D M I_RXP0 AC37 J25 C F G18
HD19# HA22# 21 D MI_RXP0 DMITXP0 CFG18 C F G18 11
H_ D#20 U9 E13 H_ A#23 D M I_RXP1 AE41 K27 C F G19
HD20# HA23# 21 D MI_RXP1 DMITXP1 CFG19 C F G19 11
H_ D#21 U11 G13 H_ A#24 D M I_RXP2 AF37 J26 C F G20
HD21# HA24# 21 D MI_RXP2 DMITXP2 CFG20 C F G20 11
H_ D#22 T11 F12 H_ A#25 D M I_RXP3 AG41
HD22# HA25# 21 D MI_RXP3 DMITXP3
H_ D#23 W9 B12 H_ A#26
H_ D#24 HD23# HA26# H_ A#27
T1 B14 AG33 C L K_MCH_3GPLL C L K_MCH_3GPLL 15
H_ D#25 HD24# HA27# H_ A#28 M_ CLK_DDR0 G_CLKP
T8 C12 13 M_ CLK_DDR0 AY35 AF33 C L K_MCH_3GPLL# C L K_MCH_3GPLL# 15
H_ D#26 HD25# HA28# H_ A#29 M_ CLK_DDR1 SM_CK0 G_CLKN
T4 A14 13 M_ CLK_DDR1 AR1
H_ D#27 HD26# HA29# H_ A#30 M_ CLK_DDR2 SM_CK1 C L K _MCH_DREFCLK#
W7 C14 AW7 A27

C LK
HD27# HA30# 14 M_ CLK_DDR2 SM_CK2 D_REF_CLKN C L K _MCH_DREFCLK# 15
H_ D#28 U5 D14 H_ A#31 M_ CLK_DDR3 AW40 A26 C L K _ MCH_DREFCLK
HD28# HA31# 14 M_ CLK_DDR3 SM_CK3 D_REF_CLKP C L K _MCH_DREFCLK 15
H_ D#29 T9
H_ D#30 HD29# M_ CLK_DDR#0
W6 13 M_ CLK_DDR#0 AW35 C40 MC H _SSCDREFCLK# C L K _MCH_SSCDREFCLK# 15
H_ D#31 T5 HD30# HOST M_ CLK_DDR#1 AT1 SM_CK0# D_REF_SSCLKN D41 MC H_ SSCDREFCLK
HD31# H_ REQ#[0..4] 4 13 M_ CLK_DDR#1 SM_CK1# D_REF_SSCLKP C L K _MCH_SSCDREFCLK 15
H_ D#32 AB7 D8 H _REQ#0 M_ CLK_DDR#2 AY7
HD32# HREQ#0 14 M_ CLK_DDR#2 SM_CK2#
H_ D#33 AA9 G8 H _REQ#1 M_ CLK_DDR#3 AY40 H32 MC H_CLKREQ#
HD33# HREQ#1 14 M_ CLK_DDR#3 SM_CK3# CLK_REQ# MC H_CLKREQ# 15
H_ D#34 W4 B8 H _REQ#2
H_ D#35 W3 HD34# HREQ#2 F8 H _REQ#3 D D R _ CKE0_DIMMA AU20
HD35# HREQ#3 13 D D R _ CKE0_DIMMA SM_CKE0

DDR MUXING
H_ D#36 Y3 A8 H _REQ#4 D D R _ CKE1_DIMMA AT20
HD36# HREQ#4 13 D D R _ CKE1_DIMMA SM_CKE1
H_ D#37 Y7 D D R _CKE2_DIMMB BA29 A3
C HD37# 14 D D R _CKE2_DIMMB SM_CKE2 NC0 C
H_ D#38 W5 D D R _CKE3_DIMMB AY29 A39
HD38# 14 D D R _CKE3_DIMMB SM_CKE3 NC1
H_ D#39 Y10 B9 H _ADSTB#0 A4
HD39# HADSTB#0 H_ADSTB#0 4 NC2
H_ D#40 AB8 C13 H _ADSTB#1 D D R _ C S0_DIMMA# AW13 A40
HD40# HADSTB#1 H_ADSTB#1 4 13 D D R _ C S0_DIMMA# SM_CS0# NC3
H_ D#41 W2 D D R _ C S1_DIMMA# AW12 AW1
HD41# 13 D D R _ C S1_DIMMA# SM_CS1# NC4
H_ D#42 AA4 AG1 C L K_MCH_BCLK# D D R _ CS2_DIMMB# AY21 AW41
HD42# HCLKN C L K_MCH_BCLK# 15 14 D D R _ CS2_DIMMB# SM_CS2# NC5
H_ D#43 AA7 AG2 C L K_MCH_BCLK D D R _ CS3_DIMMB# AW21 AY1
HD43# HCLKP C L K_MCH_BCLK 15 14 D D R _ CS3_DIMMB# SM_CS3# NC6
H_ D#44 AA2 BA1

NC
HD44# H_ D STBN#[0..3] 4 NC7
H_ D#45 AA6 K4 H_ DSTBN#0 M _OCDOCMP0 AL20 BA2
H_ D#46 HD45# HDSTBN#0 H_ DSTBN#1 M _OCDOCMP1 SM_OCDCOMP0 NC8
AA10 T7 AF10 BA3
H_ D#47 HD46# HDSTBN#1 H_ DSTBN#2 SM_OCDCOMP1 NC9
Y8 Y5 BA39
H_ D#48 AA1 HD47# HDSTBN#2 AC4 H_ DSTBN#3 M_ODT0 BA13 NC10 BA40
HD48# HDSTBN#3 H_DSTBP#[0..3] 4 +1.8V 13 M_ODT0 SM_ODT0 NC11
H_ D#49 AB4 K3 H_DSTBP#0 M_ODT1 BA12 BA41
HD49# HDSTBP#0 13 M_ODT1 SM_ODT1 NC12
H_ D#50 AC9 T6 H_DSTBP#1 M_ODT2 AY20 C1
HD50# HDSTBP#1 14 M_ODT2 SM_ODT2 NC13
H_ D#51 AB11 AA5 H_DSTBP#2 M_ODT3 AU21 AY41
HD51# HDSTBP#2 14 M_ODT3 SM_ODT3 NC14
H_ D#52 AC11 AC5 H_DSTBP#3 B2
H_ D#53 HD52# HDSTBP#3 R 29 NC15
AB3 1 2 80.6_0402_1% S MR COMPN AV9 B41
+ VCCP H_ D#54 HD53# S MRCOMPP SM_RCOMPN NC16
AC2 1 2 AT9 C41
H_ D#55 AD1 HD54# J7 H_ D INV #0 R 28 80.6_0402_1% SM_RCOMPP NC17 D1
HD55# HDINV#0 H_ D INV#0 4 NC18
H_ D#56 AD9 W8 H_ D INV #1 AK1
HD56# HDINV#1 H_ D INV#1 4 SM_VREF0
H_ D#57 AC1 U3 H_ D INV #2 + D D R _MCH_REF AK41
HD57# HDINV#2 H_ D INV#2 4 SM_VREF1
54.9_0402_1%

54.9_0402_1%

H_ D#58 AD7 AB10 H_ D INV #3 T32

HD58# HDINV#3 H_ D INV#3 4 RESERVED1
1

H_ D#59 AC6 R32

HD59# RESERVED2
R26

R27

H_ D#60 AB5 R 88 21 P M_ B MBUSY# P M_ B MBUSY# G28 F3

H_ D#61 AD10 HD60# B7 H_RESET# 0_0402_5% PM_EXTTS#0 F25 PM_BMBUSY# RESERVED3 F7
HD61# HCPURST# H_RESET# 4 1 3,14 PM_EXTTS#0 PM_EXTTS0# RESERVED4

RESERVED
PM
H_ D#62 AD4 E8 H_ A DS# 2 1,45 D P RSLPVR 2 1 PM_EXTTS#1 H26 AG11
HD62# HADS# H_ ADS# 4 PM_EXTTS1# RESERVED5
H_ D#63 AC8 E7 H_ T R DY# 4 ,20 H_ T HERMTRIP# H_ T HERMTRIP# G6 AF11
2

HD63# HTRDY# H_ T R DY# 4 PM_THERMTRIP# RESERVED6

J9 H_ DPW R# IC H _POK AH33 H7
HDPWR# H_ DPW R# 4 21,33 IC H_POK PWROK RESERVED7
H8 H_ D R D Y# 2 1 PLTRST_R# AH34 J19
HDRDY# H_ D R D Y# 4 1 9,23,28,37 PLT_RST# RSTIN# RESERVED8
J13 C3 H_ D EFER# R 55 100_0402_1% A41
HVREF0 HDEFER# H_ DEFER# 4 RESERVED9
+ H _VREF K13 D4 H_ HI TM# 19 MC H_ IC H_ S YNC# K28 A34
HVREF1 HHITM# H_ HITM# 4 ICH_SYNC# RESERVED10
H _XRCOMP E1 D3 H_ HI T# D28
HXRCOMP HHIT# H_ HIT# 4 RESERVED11
H _XSCOMP E2 B3 H _LOCK# D27
B HXSCOMP HLOCK# H_LOCK# 4 RESERVED12 B
H_ YR C OMP Y1 C7 H_ BR0# A35
HYRCOMP HBREQ0# H_ BR0# 4 RESERVED13
H_ YS COMP U1 C6 H_ B NR#
HYSCOMP HBNR# H_ B NR# 4
+ H _SW NG0 E4 F6 H_ B PRI# C ALISTOGA_FCBGA1466~D
HXSWING HBPRI# H_ B PRI# 4
+ H _SW NG1 W1 A7 H_ D B SY# UMA_ GM@
HYSWING HDBSY# H_ D B SY# 4
E3 H_ C PUSLP# Layout Note:
HCPUSLP# H_ CPUSLP# 4 ,20
24.9_0402_1%

24.9_0402_1%

+DDR_MCH_REF
1

trace width and

R23

R20

B4 H_ RS#0
HRS0# E6 H_ RS#1 spacing is 20/20.
HRS1# H_ RS#2 +3VS
D6
HRS2#
2

H_ R S#[0..2] 4
C ALISTOGA_FCBGA1466~D +1.8V
UMA_ GM@
R 46

1
10K_0402_5%
R 25 PM_EXTTS#0 2 1

Layout Note: 100_0402_1% R 49

@ 10K_0402_5%

2
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 / + D D R _MCH_REF PM_EXTTS#1 2 1
0.1U_0402_16V4Z

H_SWNG1 trace width and spacing is 10/20.

1 1 R 21
+ VCCP +VCCP R 45
C16

100_0402_1% @ 40.2_0402_1%
+ VCCP M _OCDOCMP0 2 1
2

2
221_0603_1%

221_0603_1%
1

1
100_0402_1%

R 31
1

R22

R18

@ 40.2_0402_1%
R30

M _OCDOCMP1 2 1
A A
2

+ H _SW NG0 + H _SW NG1

2

+ H _VREF
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

1
100_0402_1%

100_0402_1%
0.1U_0402_16V4Z

1 1
1

200_0402_1%

R24

R19

1
R36

C26

C19

C11

2 2 Security Classification Compal Secret Data Compal Electronics, Inc.

2

2 Title
Issued Date 2005/10/06 Deciphered Date 2006/10/06
2

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (1/6)
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C u s tom I G L50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 7 of 48
5 4 3 2 1
 5 4 3 2 1

D D

U1 4D U14E
D D R _ A_D[0..63] 13 D D R _B_D[0..63] 14
D DR_A_BS#0 AU12 AJ35 D D R _A_D0 DDR_B_BS#0 AT24 AK39 D D R_B_D0
13 D DR_A_BS#0 SA_BS0 SA_DQ0 14 DDR_B_BS#0 SB_BS0 SB_DQ0
D DR_A_BS#1 AV14 AJ34 D D R _A_D1 DDR_B_BS#1 AV23 AJ37 D D R_B_D1
13 D DR_A_BS#1 SA_BS1 SA_DQ1 14 DDR_B_BS#1 SB_BS1 SB_DQ1
D DR_A_BS#2 BA20 AM31 D D R _A_D2 DDR_B_BS#2 AY28 AP39 D D R_B_D2
13 D DR_A_BS#2 SA_BS2 SA_DQ2 14 DDR_B_BS#2 SB_BS2 SB_DQ2
AM33 D D R _A_D3 AR41 D D R_B_D3
SA_DQ3 D D R _A_D4 SB_DQ3 D D R_B_D4
AJ36 AJ38
SA_DQ4 AK35 D D R _A_D5 SB_DQ4 AK38 D D R_B_D5
13 D D R _ A_DM[0..7] SA_DQ5 14 D D R _B_DM[0..7] SB_DQ5
D D R _A_DM0 AJ33 AJ32 D D R _A_D6 D D R_B_DM0 AK36 AN41 D D R_B_D6
D D R _A_DM1 SA_DM0 SA_DQ6 D D R _A_D7 D D R_B_DM1 SB_DM0 SB_DQ6 D D R_B_D7
AM35 AH31 AR38 AP41
D D R _A_DM2 SA_DM1 SA_DQ7 D D R _A_D8 D D R_B_DM2 SB_DM1 SB_DQ7 D D R_B_D8
AL26 AN35 AT36 AT40
D D R _A_DM3 SA_DM2 SA_DQ8 D D R _A_D9 D D R_B_DM3 SB_DM2 SB_DQ8 D D R_B_D9
AN22 AP33 BA31 AV41
D D R _A_DM4 SA_DM3 SA_DQ9 D D R _A_D10 D D R_B_DM4 SB_DM3 SB_DQ9 D D R_B_D10
AM14 AR31 AL17 AU38
D D R _A_DM5 SA_DM4 SA_DQ10 D D R _A_D11 D D R_B_DM5 SB_DM4 SB_DQ10 D D R_B_D11
AL9 AP31 AH8 AV38
D D R _A_DM6 AR3 SA_DM5 SA_DQ11 AN38 D D R _A_D12 D D R_B_DM6 BA5 SB_DM5 SB_DQ11 AP38 D D R_B_D12
D D R _A_DM7 SA_DM6 SA_DQ12 D D R _A_D13 D D R_B_DM7 SB_DM6 SB_DQ12 D D R_B_D13
AH4 AM36 AN4 AR40
SA_DM7 SA_DQ13 D D R _A_D14 SB_DM7 SB_DQ13 D D R_B_D14
AM34 AW38
SA_DQ14 AN33 D D R _A_D15 SB_DQ14 AY38 D D R_B_D15
SA_DQ15 D D R _A_D16 SB_DQ15 D D R_B_D16
AK26 BA38
SA_DQ16 D D R _A_D17 SB_DQ16 D D R_B_D17
13 D D R _A_DQS[0..7] AL27 14 D D R_B_DQS[0..7] AV36
D D R_A_DQS0 SA_DQ17 D D R _A_D18 D DR_B_DQS0 SB_DQ17 D D R_B_D18
AK33 AM26 AM39 AR36
D D R_A_DQS1 AT33 SA_DQS0 SA_DQ18 AN24 D D R _A_D19 D DR_B_DQS1 AT39 SB_DQS0 SB_DQ18 AP36 D D R_B_D19
D D R_A_DQS2 SA_DQS1 SA_DQ19 D D R _A_D20 D DR_B_DQS2 SB_DQS1 SB_DQ19 D D R_B_D20
AN28 AK28 AU35 BA36

DDR SYS MEMORY B

DDR SYS MEMORY A
D D R_A_DQS3 SA_DQS2 SA_DQ20 D D R _A_D21 D DR_B_DQS3 SB_DQS2 SB_DQ20 D D R_B_D21
AM22 AL28 AR29 AU36
C D D R_A_DQS4 AN12 SA_DQS3 SA_DQ21 AM24 D D R _A_D22 D DR_B_DQS4 AR16 SB_DQS3 SB_DQ21 AP35 D D R_B_D22 C
D D R_A_DQS5 SA_DQS4 SA_DQ22 D D R _A_D23 D DR_B_DQS5 SB_DQS4 SB_DQ22 D D R_B_D23
AN8 AP26 AR10 AP34
D D R_A_DQS6 SA_DQS5 SA_DQ23 D D R _A_D24 D DR_B_DQS6 SB_DQS5 SB_DQ23 D D R_B_D24
AP3 AP23 AR7 AY33
D D R_A_DQS7 AG5 SA_DQS6 SA_DQ24 AL22 D D R _A_D25 D DR_B_DQS7 AN5 SB_DQS6 SB_DQ24 BA33 D D R_B_D25
SA_DQS7 SA_DQ25 D D R _A_D26 SB_DQS7 SB_DQ25 D D R_B_D26
AP21 AT31
SA_DQ26 D D R _A_D27 SB_DQ26 D D R_B_D27
13 D D R _A_DQS#[0..7] AN20 14 D D R_B_DQS#[0..7] AU29
D D R_A_DQS#0 SA_DQ27 D D R _A_D28 D DR_B_DQS#0 SB_DQ27 D D R_B_D28
AK32 AL23 AM40 AU31
D D R_A_DQS#1 AU33 SA_DQS0# SA_DQ28 AP24 D D R _A_D29 D DR_B_DQS#1 AU39 SB_DQS0# SB_DQ28 AW31 D D R_B_D29
D D R_A_DQS#2 SA_DQS1# SA_DQ29 D D R _A_D30 D DR_B_DQS#2 SB_DQS1# SB_DQ29 D D R_B_D30
AN27 AP20 AT35 AV29
D D R_A_DQS#3 SA_DQS2# SA_DQ30 D D R _A_D31 D DR_B_DQS#3 SB_DQS2# SB_DQ30 D D R_B_D31
AM21 AT21 AP29 AW29
D D R_A_DQS#4 AM12 SA_DQS3# SA_DQ31 AR12 D D R _A_D32 D DR_B_DQS#4 AP16 SB_DQS3# SB_DQ31 AM19 D D R_B_D32
D D R_A_DQS#5 SA_DQS4# SA_DQ32 D D R _A_D33 D DR_B_DQS#5 SB_DQS4# SB_DQ32 D D R_B_D33
AL8 AR14 AT10 AL19
D D R_A_DQS#6 SA_DQS5# SA_DQ33 D D R _A_D34 D DR_B_DQS#6 SB_DQS5# SB_DQ33 D D R_B_D34
AN3 AP13 AT7 AP14
D D R_A_DQS#7 AH5 SA_DQS6# SA_DQ34 AP12 D D R _A_D35 D DR_B_DQS#7 AP5 SB_DQS6# SB_DQ34 AN14 D D R_B_D35
SA_DQS7# SA_DQ35 D D R _A_D36 SB_DQS7# SB_DQ35 D D R_B_D36
AT13 AN17
SA_DQ36 D D R _A_D37 SB_DQ36 D D R_B_D37
AT12 AM16
SA_DQ37 D D R _A_D38 SB_DQ37 D D R_B_D38
13 D D R _ A_MA[0..13] AL14 14 D D R _ B_MA[0..13] AP15
D D R _A_MA0 AY16 SA_DQ38 AL12 D D R _A_D39 D D R_B_MA0 AY23 SB_DQ38 AL15 D D R_B_D39
D D R _A_MA1 SA_MA0 SA_DQ39 D D R _A_D40 D D R_B_MA1 SB_MA0 SB_DQ39 D D R_B_D40
AU14 AK9 AW24 AJ11
D D R _A_MA2 SA_MA1 SA_DQ40 D D R _A_D41 D D R_B_MA2 SB_MA1 SB_DQ40 D D R_B_D41
AW16 AN7 AY24 AH10
D D R _A_MA3 SA_MA2 SA_DQ41 D D R _A_D42 D D R_B_MA3 SB_MA2 SB_DQ41 D D R_B_D42
BA16 AK8 AR28 AJ9
D D R _A_MA4 SA_MA3 SA_DQ42 D D R _A_D43 D D R_B_MA4 SB_MA3 SB_DQ42 D D R_B_D43
BA17 AK7 AT27 AN10
D D R _A_MA5 SA_MA4 SA_DQ43 D D R _A_D44 D D R_B_MA5 SB_MA4 SB_DQ43 D D R_B_D44
AU16 AP9 AT28 AK13
D D R _A_MA6 AV17 SA_MA5 SA_DQ44 AN9 D D R _A_D45 D D R_B_MA6 AU27 SB_MA5 SB_DQ44 AH11 D D R_B_D45
D D R _A_MA7 SA_MA6 SA_DQ45 D D R _A_D46 D D R_B_MA7 SB_MA6 SB_DQ45 D D R_B_D46
AU17 AT5 AV28 AK10
D D R _A_MA8 SA_MA7 SA_DQ46 D D R _A_D47 D D R_B_MA8 SB_MA7 SB_DQ46 D D R_B_D47
AW17 AL5 AV27 AJ8
D D R _A_MA9 SA_MA8 SA_DQ47 D D R _A_D48 D D R_B_MA9 SB_MA8 SB_DQ47 D D R_B_D48
AT16 AY2 AW27 BA10
D D R _A_MA10 SA_MA9 SA_DQ48 D D R _A_D49 D D R_B_MA10 SB_MA9 SB_DQ48 D D R_B_D49
AU13 AW2 AV24 AW10
D D R _A_MA11 SA_MA10 SA_DQ49 D D R _A_D50 D D R_B_MA11 SB_MA10 SB_DQ49 D D R_B_D50
AT17 AP1 BA27 BA4
D D R _A_MA12 SA_MA11 SA_DQ50 D D R _A_D51 D D R_B_MA12 SB_MA11 SB_DQ50 D D R_B_D51
AV20 AN2 AY27 AW4
D D R _A_MA13 AV12 SA_MA12 SA_DQ51 AV2 D D R _A_D52 D D R_B_MA13 AR23 SB_MA12 SB_DQ51 AY10 D D R_B_D52
SA_MA13 SA_DQ52 D D R _A_D53 SB_MA13 SB_DQ52 D D R_B_D53
AT3 AY9
B SA_DQ53 D D R _A_D54 SB_DQ53 D D R_B_D54 B
AN1 AW5
SA_DQ54 D D R _A_D55 SB_DQ54 D D R_B_D55
AL2 AY5
D D R _A_CAS# SA_DQ55 D D R _A_D56 D D R_B_CAS# SB_DQ55 D D R_B_D56
13 D D R _A_CAS# AY13 AG7 14 D D R_B_CAS# AR24 AV4
D D R _A_RAS# SA_CAS# SA_DQ56 D D R _A_D57 D D R_B_RAS# SB_CAS# SB_DQ56 D D R_B_D57
13 D D R _A_RAS# AW14 AF9 14 D D R_B_RAS# AU23 AR5
D D R_A_W E# SA_RAS# SA_DQ57 D D R _A_D58 D DR_B_W E# SB_RAS# SB_DQ57 D D R_B_D58
13 D D R_A_W E# AY14 AG4 14 D DR_B_W E# AR27 AK4
S A_ R C V ENIN# AK23 SA_WE# SA_DQ58 AF6 D D R _A_D59 S B _ R C VENIN# AK16 SB_WE# SB_DQ58 AK3 D D R_B_D59
T6 P AD SA_RCVENIN# SA_DQ59 T4 P AD SB_RCVENIN# SB_DQ59
T12 P AD S A_ RCVENOUT# AK24 AG9 D D R _A_D60 T11 P AD S B _RCVENOUT# AK18 AT4 D D R_B_D60
SA_RCVENOUT# SA_DQ60 D D R _A_D61 SB_RCVENOUT# SB_DQ60 D D R_B_D61
AH6 AK5
SA_DQ61 AF4 D D R _A_D62 SB_DQ61 AJ5 D D R_B_D62
SA_DQ62 D D R _A_D63 SB_DQ62 D D R_B_D63
AF8 AJ3
SA_DQ63 SB_DQ63
check layout check layout
C ALISTOGA_FCBGA1466~D C ALISTOGA_FCBGA1466~D
UMA_ GM@ UMA_ GM@

A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (2/6)
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C u s tom I G L50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 8 of 48
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

D D

R 54 + 1.5VS_PCIE
U1 4C 24.9_0402_1%
H27 D40 PEGCOMP 1 2
SDVOCTRL_DATA EXP_COMPI
H28 D38 P EG_RXN[0..15] 18
SDVOCTRL_CLK EXP_COMPO
F34 P EG_RXN0
L VDSA0+ EXP_RXN0 P EG_RXN1
38 L VDSA0+ B37 G38
L VDSA1+ LA_DATA0 EXP_RXN1 P EG_RXN2
38 L VDSA1+ B34 H34
L VDSA2+ A36 LA_DATA1 EXP_RXN2 J38 P EG_RXN3
38 LVDSA2+ LA_DATA2 EXP_RXN3
L34 P EG_RXN4
L VDSA0- EXP_RXN4 P EG_RXN5
C37 M38
38 L VDSA0- L VDSA1- B35 LA_DATA#0 EXP_RXN5 N34 P EG_RXN6
38 L VDSA1- L VDSA2- LA_DATA#1 EXP_RXN6 P EG_RXN7
38 L VDSA2- A37 P38
LA_DATA#2 EXP_RXN7 P EG_RXN8
R34
LVDSB0+ EXP_RXN8 P EG_RXN9
38 LVDSB0+ F30 T38
LVDSB1+ LB_DATA0 EXP_RXN9 P EG_RXN10
D29 V34

LV DS
38 LVDSB1+ LB_DATA1 EXP_RXN10
LVDSB2+ F28 W38 P EG_RXN11
38 LVDSB2+ LB_DATA2 EXP_RXN11 P EG_RXN12
Y34
LVDSB0- G30 EXP_RXN12 AA38 P EG_RXN13
38 LVDSB0- LB_DATA#0 EXP_RXN13
LVDSB1- D30 AB34 P EG_RXN14
38 LVDSB1- LB_DATA#1 EXP_RXN14
LVDSB2- F29 AC38 P EG_RXN15
38 LVDSB2- LB_DATA#2 EXP_RXN15 PEG_RXP[0..15] 18
L VDSAC+ A32 D34 PEG_RXP0
38 L VDSAC+ LA_CLK EXP_RXP0
L V DSAC- A33 F38 PEG_RXP1
38 L VDSAC- LVDSBC+ LA_CLK# EXP_RXP1 PEG_RXP2
38 LVDSBC+ E26 G34
L VDSBC- E27 LB_CLK EXP_RXP2 H38 PEG_RXP3
38 L VDSBC- LB_CLK# EXP_RXP3
J34 PEG_RXP4

PCI-EXPRESS GRAPHICS
EXP_RXP4 PEG_RXP5
D32 L38
C GMC H _ENBKL J30 LBKLT_CTL EXP_RXP5 M34 PEG_RXP6 C
16 GMC H_ENBKL LBKLT_EN EXP_RXP6
H30 N38 PEG_RXP7
LCTLA_CLK EXP_RXP7 PEG_RXP8
H29 P34
L D DC_CLK G26 LCTLB_DATA EXP_RXP8 R38 PEG_RXP9
L D DC_DATA LDDC_CLK EXP_RXP9 PEG_RXP10
G25 T34
GMC H_ L VDDEN LDDC_DATA EXP_RXP10 PEG_RXP11
16 GMC H_ L VDDEN F32 V38
LVDD_EN EXP_RXP11 PEG_RXP12
2 1 B38 W34
R 53 1.5K_0402_1% C35 LIBG EXP_RXP12 Y38 PEG_RXP13
LVBG EXP_RXP13 PEG_RXP14
C33 AA34
LVREFH EXP_RXP14 PEG_RXP15
C32 AB38 P EG_M_TXN[0..15] 18
LVREFL EXP_RXP15
2 1 TV_COMPS F36 PEG_TXN0 C 153 0 . 1 U_0402_16V4Z PEG_M_TXN0
R 207 UMA@ 150_0603_1% TV_COMPS EXP_TXN0 PEG_TXN1 C 124 0 . 1 U_0402_16V4Z PEG_M_TXN1
17 TV_COMPS A16 G40
2 1 T V_ LUMA T V_ LUMA C18 TVDAC_A EXP_TXN1 H36 PEG_TXN2 C 142 0 . 1 U_0402_16V4Z PEG_M_TXN2
17 T V_LUMA TVDAC_B EXP_TXN2
R 208 UMA@ 150_0603_1% 17 T V_CRMA T V _CRMA A19 J40 PEG_TXN3 C 115 0 . 1 U_0402_16V4Z PEG_M_TXN3
TVDAC_C EXP_TXN3

TV
2 1 T V _CRMA L36 PEG_TXN4 C 155 0 . 1 U_0402_16V4Z PEG_M_TXN4
R 209 UMA@ 150_0603_1% EXP_TXN4
2 R 42 1 J20 M40 PEG_TXN5 C 126 0 . 1 U_0402_16V4Z PEG_M_TXN5
4.99K_0402_1% TV_IREF EXP_TXN5 N36 PEG_TXN6 C 148 0 . 1 U_0402_16V4Z PEG_M_TXN6
EXP_TXN6 PEG_TXN7 C 117 0 . 1 U_0402_16V4Z PEG_M_TXN7
B16 P40
TV_IRTNA EXP_TXN7 PEG_TXN8 C 157 0 . 1 U_0402_16V4Z PEG_M_TXN8
B18 R36
TV_IRTNB EXP_TXN8 PEG_TXN9 C 128 0 . 1 U_0402_16V4Z PEG_M_TXN9
B19 T40
TV_IRTNC EXP_TXN9 PEG_TXN10 C 140 0 . 1 U_0402_16V4Z PEG_M_TXN10
V36
EXP_TXN10 PEG_TXN11 C 119 0 . 1 U_0402_16V4Z PEG_M_TXN11
J29 W40
K30 TV_DCONSEL1 EXP_TXN11 Y36 PEG_TXN12 C 159 0 . 1 U_0402_16V4Z PEG_M_TXN12
TV_DCONSEL0 EXP_TXN12 PEG_TXN13 C 130 0 . 1 U_0402_16V4Z PEG_M_TXN13
AA40
EXP_TXN13 PEG_TXN14 C 144 0 . 1 U_0402_16V4Z PEG_M_TXN14
AB36
EXP_TXN14 PEG_TXN15 C 121 0 . 1 U_0402_16V4Z PEG_M_TXN15
AC40 PEG_M_TXP[0..15] 18
3 VD DCCL EXP_TXN15
17 3 VD DCCL C26
DDCCLK
C RT

3 VD D CDA C25 D36 PEG_TXP0 C 152 0 . 1 U_0402_16V4Z PEG_M_TXP0

17 3 VD D CDA DDCDATA EXP_TXP0
F40 PEG_TXP1 C 123 0 . 1 U_0402_16V4Z PEG_M_TXP1
C R T _ V SYNC H23 EXP_TXP1 G36 PEG_TXP2 C 141 0 . 1 U_0402_16V4Z PEG_M_TXP2
17 C R T _ VSYNC VSYNC EXP_TXP2
17 C R T _ HS YNC C R T _ HS YNC G23 H40 PEG_TXP3 C 114 0 . 1 U_0402_16V4Z PEG_M_TXP3
B CRT_B HSYNC EXP_TXP3 PEG_TXP4 C 154 0 . 1 U_0402_16V4Z PEG_M_TXP4 B
17 CRT_B E23 J36
C RT_R BLUE EXP_TXP4 PEG_TXP5 C 125 0 . 1 U_0402_16V4Z PEG_M_TXP5
2 1 D23 L40
R 210 UMA@ 150_0603_1% C RT_G BLUE# EXP_TXP5 PEG_TXP6 C 147 0 . 1 U_0402_16V4Z PEG_M_TXP6
17 C RT_G C22 M36
C RT_G GREEN EXP_TXP6 PEG_TXP7 C 116 0 . 1 U_0402_16V4Z PEG_M_TXP7
2 1 B22 N40
R 211 UMA@ 150_0603_1% C RT_R GREEN# EXP_TXP7 PEG_TXP8 C 156 0 . 1 U_0402_16V4Z PEG_M_TXP8
17 C RT_R A21 P36
2 1 CRT_B B21 RED EXP_TXP8 R40 PEG_TXP9 C 127 0 . 1 U_0402_16V4Z PEG_M_TXP9
R 212 UMA@ 150_0603_1% RED# EXP_TXP9 PEG_TXP10 C 139 0 . 1 U_0402_16V4Z PEG_M_TXP10
T36
EXP_TXP10 PEG_TXP11 C 118 0 . 1 U_0402_16V4Z PEG_M_TXP11
V40
2 R 47 1 J22 EXP_TXP11 W36 PEG_TXP12 C 158 0 . 1 U_0402_16V4Z PEG_M_TXP12
255_0402_1% CRT_IREF EXP_TXP12 PEG_TXP13 C 129 0 . 1 U_0402_16V4Z PEG_M_TXP13
Y40
EXP_TXP13 PEG_TXP14 C 143 0 . 1 U_0402_16V4Z PEG_M_TXP14
AA36
EXP_TXP14 PEG_TXP15 C 120 0 . 1 U_0402_16V4Z PEG_M_TXP15
AB40
EXP_TXP15

C ALISTOGA_FCBGA1466~D
UMA_ GM@
+2.5VS +3VS
2.2K_0402_5%

2.2K_0402_5%
1

1
UMA@

R215

R216

R 214 R 217
UMA@

2 1 2.2K_0402_5% 2.2K_0402_5%
R 709 @ 0_0402_5% UMA@ UMA@
2

2
S

L D DC_CLK 3 1 E D I D_CLK_LCD
E D ID_CLK_LCD 38
Q18
BSS138_SOT23
UMA@
G
2

A A
+2.5VS
2
G

L D DC_DATA 3 1 E D I D_DAT_LCD
E D ID_DAT_LCD 38
S

Q17
BSS138_SOT23
UMA@ Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
2 1 Issued Date 2005/10/06 Deciphered Date 2006/10/06
R 710 @ 0_0402_5%
THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (3/6)
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C u s tom I G L50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 9 of 48
5 4 3 2 1
 5 4 3 2 1

+ VCCP
2

D13 @ +2.5VS
D D
CH751H-40_SC76 U1 4 H
1 1

+ VCCP H22 1 2
VCC_SYNC C306
R221 +2.5VS AC14 0.1U_0402_16V4Z
VTT0
AB14 B30 +2.5VS
@ 10_0402_5% VTT1 VCCTX_LVDS0
W14 C30
VTT2 VCCTX_LVDS1 +1.5VS_PCIE R57
V14 A30
2

VTT3 VCCTX_LVDS2 0_0805_5%

T14
R14
VTT4
VTT5 VCC3G0
AB41 W=40 mils 2 1 +1.5VS

10U_1206_6.3V6M

10U_1206_6.3V6M
P14 AJ41
VTT6 VCC3G1

220U_D2_4VM
+1.5VS N14 L41
VTT7 VCC3G2 1
M14 N41 1 1
VTT8 VCC3G3

C108
L14 R41 +
2

VTT9 VCC3G4 +2.5VS

0.1U_0402_16V4Z
C107

C105
AD13 V41
VTT10 VCC3G5
220U_D2_4VM

D12 AC13 Y41

@ VTT11 VCC3G6 2 2 2
AB13 1
CH751H-40_SC76 VTT12
1 AA13 AC33 +1.5VS_3GPLL
VTT13 VCCA_3GPLL

C99
Y13 G41 +2.5VS
VTT14 VCCA_3GBG
1 1

C91

+ W13 H41
VTT15 VSSA_3GBG 2 +1.5VS_DPLLA L16 +1.5VS_DPLLB L5
V13
R220 +3VS VTT16 L4 F BM-11-160808-601-T_0603 CHB1608U301_0603 CHB1608U301_0603
U13
2 VTT17 +2.5VS_CRT DAC
T13 E21 1 2 +2.5VS 2 1 +1.5VS 2 1 +1.5VS
VTT18 VCCA_CRTDAC0

2200P_0402_50V7K

330U_V_2.5VK_R9
@ 10_0402_5% R13 F21
VTT19 VCCA_CRTDAC1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

330U_V_2.5VK_R9

0.1U_0402_16V4Z
N13
VTT20 VSSA_CRTDAC2
G21 close pin G41
2

M13 1 1 1 1
VTT21

C300

C100
L13 1 1
VTT22

C82

C101
C72

C71
+ +
AB12
VTT23 VCCA_DPLLA
B26 +1.5VS_DPLLA CRTDAC: Route caps within
AA12 C39 +1.5VS_DPLLB
Y12
VTT24 VCCA_DPLLB
AF1 +1.5VS_HPLL
2 2 250mil of Alviso. Route FB UMA@ UMA@
VTT25 VCCA_HPLL 2 2 2 2
W12
VTT26 within 3" of Calistoga
V12
VTT27
U12 A38 +2.5VS
VTT28 VCCA_LVDS
T12 B39
VTT29 VSSA_LVDS
R12
C VTT30 +2.5VS C
P12
VTT31
N12 AF2
M12
VTT32
VTT33
P O W E R VCCA_MPLL +1.5VS_MPLL
+3VS_T VDACA +3VS_T VDACA +3VS_T VDACA +3VS
4.7U_0805_10V4Z

2.2U_0805_16V4Z

L12 H20 +3VS_TVBG

VTT34 VCCA_TVBG

0.1U_0402_16V4Z

0.01U_0402_25V4Z
R11 G20 R206
VTT35 VSSA_TVBG

C102

C304
1 1 P11 2 1
VTT36

2200P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K
C24

C50

N11 1 1 0_0603_5%
VTT37

0.1U_0402_16V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
M11 E19 +3VS_T VDACA
VTT38 VCCA_TVDACA0
R10 F19 1 1 1 1 1 1
2 2 VTT39 VCCA_TVDACA1
P10 C20 +3VS_T VDACA
VTT40 VCCA_TVDACB0 2 2

C55

C54

C297

C58

C45

C46
N10 D20
VTT41 VCCA_TVDACB1
M10 E20 +3VS_T VDACA
VTT42 VCCA_TVDACC0 2 2 2 2 2 2
P9 F20
VTT43 VCCA_TVDACC1
N9
VTT44
M9
VTT45 close pin A38
R8 AH1 +1.5VS
VTT46 VCCD_HMPLL0
P8 AH2
VTT47 VCCD_HMPLL1
N8
VTT48 +3VS_TVBG +3VS
M8
VTT49 R205
P7 A28
VTT50 VCCD_LVDS0
N7 B28 2 1
VTT51 VCCD_LVDS1

4.7U_0805_10V4Z
M7 C28 0_0805_5%
VTT52 VCCD_LVDS2

0.1U_0402_16V4Z
2200P_0402_50V7K
R6
VTT53
P6 D21 +1.5VS_T VDAC 1 1 1
VTT54 VCCD_TVDAC

C711
M6 H19
VTT55 VCCDQ_TVDAC

C49
M CH_A6 A6
VTT56
0.47U_0603_16V4Z

C63
R5 A23 +3VS
VTT57 VCCHV0 2 2 2
P5 B23
VTT58 VCCHV1
10U_1206_6.3V6M
0.1U_0402_16V4Z

1 N5 B25
VTT59 VCCHV2
C296

M5 1 1
VTT60
P4 AK31
VTT61 VCCAUX0
N4 AF31
2 VTT62 VCCAUX1
C302

C298

M4 AE31
VTT63 VCCAUX2 2 2
R3 AC31
B VTT64 VCCAUX3 B
P3 AL30
N3
VTT65
VTT66
VCCAUX4
VCCAUX5
AK30 PCI-E/MEM/PSB PLL decoupling
0.22U_0603_10V7K

M3 AJ30
VTT67 VCCAUX6 +1.5VS
R2 AH30
VTT68 VCCAUX7
P2 AG30
VTT69 VCCAUX8 +1.5VS_3GPLL +1.5VS +1.5VS_TVDAC +1.5VS
0.1U_0402_16V4Z

1 M2 AF30 R56 R213

VTT70 VCCAUX9
C94

MC H_D2 D2 AE30 0_0603_5% 0_0603_5%

VTT71 VCCAUX10
AB1 AD30 1 2 1 2 1
VTT72 VCCAUX11

10U_1206_6.3V6M
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
0.22U_0603_10V7K

2200P_0402_50V7K
R1 AC30
MCH_AB1

2 VTT73 VCCAUX12
C299

1 P1 AG29
VTT74 VCCAUX13
C12

N1 AF29 1 1 1 1 1 1
VTT75 VCCAUX14 2
0.47U_0603_16V4Z

M1 AE29
VTT76 VCCAUX15

C97

C98

C104

C67

C37

C301
AD29
2 VCCAUX16
1 AC29
VCCAUX17 2 2 2 2 2 2
C10

AG28
VCCAUX18
AF28
VCCAUX19 @ @
AE28
2 VCCAUX20
AH22
VCCAUX21
AJ21
VCCAUX22
AG14 AH21
VCCAUX32 VCCAUX23
AF14 AJ20
VCCAUX33 VCCAUX24
AE14 AH20
VCCAUX34 VCCAUX25
Y14 AH19
VCCAUX35 VCCAUX26 +1.5VS_MPLL R16 +1.5VS_HPLL R17
AF13 P19
VCCAUX36 VCCAUX27 0_0603_5% 0_0603_5%
AE13 P16
+1.5VS VCCAUX37 VCCAUX28
AF12
VCCAUX38 VCCAUX29
AH15 45mA Max. 2 1 +1.5VS 45mA Max. 2 1 +1.5VS
AE12 P15
VCCAUX39 VCCAUX30

10U_1206_6.3V6M

10U_1206_6.3V6M
0.1U_0402_16V4Z

0.1U_0402_16V4Z
AD12 AH14
VCCAUX40 VCCAUX31
1 1 1 1
CALIST OGA_F CBGA1466~D

C8

C9
C13

C14
UMA_GM@
2 2 2 2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2005/10/06 2006/10/06 T itle
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (4/6)
Size Document Number Rev
A ND TRA DE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C ustom I G L 5 0/51 LA-3771 0.1
DE P A RTME NT E XCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期一 , 七月 31, 2006 Sheet 10 of 48
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

Strap Pin Table

CFG[3:17] have internal pull up

U1 4 F
CFG[19:18] have internal pull down
+VCCP +1.5VS + VCCP U1 4G + 1.8V

AD27 AG27 AA33 AU41 011 = 667MT/s FSB

VCC_NCTF0 VCCAUX_NCTF0 VCC0 VCC_SM0 MC H_AT41
AC27 AF27 W33 AT41 CFG[2:0] 001 = 533MT/s FSB
AB27 VCC_NCTF1 VCCAUX_NCTF1 AG26 P33 VCC1 VCC_SM1 AM41 MC H_ AM41
VCC_NCTF2 VCCAUX_NCTF2 VCC2 VCC_SM2
AA27 AF26 N33 AU40 0 = DMI x 2
VCC_NCTF3 VCCAUX_NCTF3 VCC3 VCC_SM3

0.47U_0603_16V4Z

0.47U_0603_16V4Z
Y27
VCC_NCTF4 VCCAUX_NCTF4
AG25 L33
VCC4 VCC_SM4
BA34 CFG5 1 = DMI x 4 * (Default)
W27 AF25 J33 AY34
V27 VCC_NCTF5 VCCAUX_NCTF5 AG24 AA32 VCC5 VCC_SM5 AW34
D VCC_NCTF6 VCCAUX_NCTF6 VCC6 VCC_SM6 1 1 0 = Reserved

C106
D
U27
VCC_NCTF7 VCCAUX_NCTF7
AF24 Y32
VCC7 VCC_SM7
AV34 CFG7 1 = Mobile Yonah CPU*(Default)

C103
T27 AG23 W32 AU34
VCC_NCTF8 VCCAUX_NCTF8 VCC8 VCC_SM8
0.22U_0603_10V7K

0.22U_0603_10V7K
0.22U_0603_10V7K

R27 AF23 V32 AT34 0 = Lane Reversal Enable

VCC_NCTF9 VCCAUX_NCTF9 VCC9 VCC_SM9 2 2
AD26
VCC_NCTF10 VCCAUX_NCTF10
AG22 P32
VCC10 VCC_SM10
AR34 CFG9 1 = Normal Operation (Default)*
1 1 1 AC26 AF22 N32 BA30
AB26 VCC_NCTF11 VCCAUX_NCTF11 AG21 M32 VCC11 VCC_SM11 AY30
VCC_NCTF12 VCCAUX_NCTF12 VCC12 VCC_SM12
C69

C61

C25

AA26 AF21 L32 AW30 CFG6 0 = Reserved

VCC_NCTF13 VCCAUX_NCTF13 VCC13 VCC_SM13
Y26 AG20 J32 AV30
2 2 2 VCC_NCTF14 VCCAUX_NCTF14 VCC14 VCC_SM14
W26
V26
VCC_NCTF15 VCCAUX_NCTF15
AF20
AG19
AA31
W31
VCC15 VCC_SM15
AU30
AT30
PSB 4X CLK Enable 1 = Calistoga *
VCC_NCTF16 VCCAUX_NCTF16 VCC16 VCC_SM16
U26 AF19 V31 AR30 Place near pin AT41 & AM41
VCC_NCTF17 VCCAUX_NCTF17 VCC17 VCC_SM17
T26 R19 T31 AP30 00 = Reserved
R26 VCC_NCTF18 VCCAUX_NCTF18 AG18 R31 VCC18 VCC_SM18 AN30
VCC_NCTF19 VCCAUX_NCTF19 VCC19 VCC_SM19 CFG[13:12] 01 = XOR Mode Enabled
AD25 AF18 P31 AM30 10 = All Z Mode Enabled
VCC_NCTF20 VCCAUX_NCTF20 VCC20 VCC_SM20
AC25
VCC_NCTF21 VCCAUX_NCTF21
R18 N31
VCC21 VCC_SM21
AM29 11 = Normal Operation * (Default)
AB25 AG17 M31 AL29
VCC_NCTF22 VCCAUX_NCTF22 VCC22 VCC_SM22
AA25 AF17 AA30 AK29 0 = Dynamic ODT Disabled
VCC_NCTF23 VCCAUX_NCTF23 VCC23 VCC_SM23
Y25
VCC_NCTF24 VCCAUX_NCTF24
AE17 Y30
VCC24 VCC_SM24
AJ29 CFG16 1 = Dynamic ODT Enabled * (Default)
W25 AD17 W30 AH29
VCC_NCTF25 VCCAUX_NCTF25 VCC25 VCC_SM25

0.1U_0402_16V4Z

0.1U_0402_16V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
V25 AB17 V30 AJ28 10 = 1.05V* (Default)
VCC_NCTF26 VCCAUX_NCTF26 VCC26 VCC_SM26
U25 AA17 U30 AH28 CFG10 CFG18 01 = 1.5V
VCC_NCTF27 VCCAUX_NCTF27 VCC27 VCC_SM27
10U_1206_6.3V6M
10U_1206_6.3V6M

1U_0603_10V4Z

T25 W17 T30 AJ27

P O W E R

VCC_NCTF28 VCCAUX_NCTF28 VCC28 VCC_SM28 1 1 1 1

R25 V17 R30 AH27 0 = Normal Operation * (Default)
VCC_NCTF29 VCCAUX_NCTF29 VCC29 VCC_SM29

C21

C20

C86

C47
1 1 1 AD24 T17 P30 BA26 CFG19 1 = DMI Lane Reversal Enable
VCC_NCTF30 VCCAUX_NCTF30 VCC30 VCC_SM30
AC24 R17 N30 AY26
VCC_NCTF31 VCCAUX_NCTF31 VCC31 VCC_SM31 2 2 2 2
C48

C95

C31

AB24 AG16 M30 AW26 0 = No SDVO Device Present *

AA24
VCC_NCTF32
VCC_NCTF33
VCCAUX_NCTF32
VCCAUX_NCTF33
AF16 L30
VCC32
VCC33
P O W E R VCC_SM32
VCC_SM33
AV26 (Default)
2 2 2 Y24 AE16 AA29 AU26
VCC_NCTF34 VCCAUX_NCTF34 VCC34 VCC_SM34 SDVO_CTRLDATA
W24 AD16 Y29 AT26 1 = SDVO Device Present
V24 VCC_NCTF35 VCCAUX_NCTF35 AC16 W29 VCC35 VCC_SM35 AR26
VCC_NCTF36 VCCAUX_NCTF36 VCC36 VCC_SM36
U24 AB16 V29 AJ26
VCC_NCTF37 VCCAUX_NCTF37 VCC37 VCC_SM37
T24 AA16 U29 AH26 0 = Only PCIE or SDVO is
C R24 VCC_NCTF38 VCCAUX_NCTF38 Y16 R29 VCC38 VCC_SM38 AJ25 C
AD23
VCC_NCTF39 VCCAUX_NCTF39
W16 P29
VCC39 VCC_SM39
AH25
CFG20 operational. * (Default)
VCC_NCTF40 VCCAUX_NCTF40 VCC40 VCC_SM40
V23 V16 M29 AJ24 (PCIE/SDVO select) 1 = PCIE/SDVO are operating
U23 VCC_NCTF41 VCCAUX_NCTF41 U16 L29 VCC41 VCC_SM41 AH24
VCC_NCTF42 VCCAUX_NCTF42 VCC42 VCC_SM42 simu.
T23 T16 AB28 BA23
VCC_NCTF43 VCCAUX_NCTF43 VCC43 VCC_SM43
R23 R16 AA28 AJ23
VCC_NCTF44 VCCAUX_NCTF44 VCC44 VCC_SM44
220U_D2_4VM

0.47U_0603_16V4Z
AD22 AG15 Y28 BA22
V22 VCC_NCTF45 VCCAUX_NCTF45 AF15 V28 VCC45 VCC_SM45 AY22
VCC_NCTF46 VCCAUX_NCTF46 VCC46 VCC_SM46
1 U22 AE15 U28 AW22 1
VCC_NCTF47 VCCAUX_NCTF47 VCC47 VCC_SM47
T22 AD15 T28 AV22
+ VCC_NCTF48 VCCAUX_NCTF48 VCC48 VCC_SM48

C27
R22 AC15 R28 AU22
VCC_NCTF49 VCCAUX_NCTF49 VCC49 VCC_SM49
C18

AD21 AB15 P28 AT22

VCC_NCTF50 VCCAUX_NCTF50 VCC50 VCC_SM50 2 R 32 @ 2.2K_0402_5%
V21 AA15 N28 AR22 7 C F G5 1 2
2 U21 VCC_NCTF51 VCCAUX_NCTF51 Y15 M28 VCC51 VCC_SM51 AP22
VCC_NCTF52 VCCAUX_NCTF52 VCC52 VCC_SM52 R 40
T21 W15 L28 AK22 7 C F G7 1 2 @ 2.2K_0402_5%
VCC_NCTF53 VCCAUX_NCTF53 VCC53 VCC_SM53
R21 V15 P27 AJ22
VCC_NCTF54 VCCAUX_NCTF54 VCC54 VCC_SM54 R 37
AD20 U15 N27 AK21 7 C F G9 1 2 @ 2.2K_0402_5%
V20 VCC_NCTF55 VCCAUX_NCTF55 T15 M27 VCC55 VCC_SM55 AK20
VCC_NCTF56 VCCAUX_NCTF56 VCC56 VCC_SM56 Place near pin BA23 R 35
U20 R15 L27 BA19 7 C F G11 1 2 @ 2.2K_0402_5%
VCC_NCTF57 VCCAUX_NCTF57 VCC57 VCC_SM57
T20 P26 AY19
VCC_NCTF58 VCC58 VCC_SM58

10U_1206_6.3V6M

10U_1206_6.3V6M

@ 220U_D2_4M_R45
R20 N26 AW19 R 34 1 2 @ 2.2K_0402_5%
VCC_NCTF59 VCC59 VCC_SM59 7 C F G12
AD19 AE27 L26 AV19 1
VCC_NCTF60 VSS_NCTF0 VCC60 VCC_SM60 R 38
V19 AE26 N25 AU19 1 1 7 C F G13 1 2 @ 2.2K_0402_5%
U19 VCC_NCTF61 VSS_NCTF1 AE25 M25 VCC61 VCC_SM61 AT19 +
VCC_NCTF62 VSS_NCTF2 VCC62 VCC_SM62
@ 220U_D2_4VM

C44

C78

C59
T19 AE24 L25 AR19 R 33 1 2 @ 2.2K_0402_5%
VCC_NCTF63 VSS_NCTF3 VCC63 VCC_SM63 7 C F G16
1 AD18 AE23 P24 AP19
VCC_NCTF64 VSS_NCTF4 VCC64 VCC_SM64 2 2 2
AC18 AE22 N24 AK19
+ VCC_NCTF65 VSS_NCTF5 VCC65 VCC_SM65
AB18 AE21 M24 AJ19
VCC_NCTF66 VSS_NCTF6 VCC66 VCC_SM66
C79

AA18 AE20 AB23 AJ18

VCC_NCTF67 VSS_NCTF7 VCC67 VCC_SM67
Y18 AE19 AA23 AJ17
2 W18 VCC_NCTF68 VSS_NCTF8 AE18 Y23 VCC68 VCC_SM68 AH17
VCC_NCTF69 VSS_NCTF9 VCC69 VCC_SM69
V18 AC17 P23 AJ16
B VCC_NCTF70 VSS_NCTF10 VCC70 VCC_SM70 +3VS B
U18 Y17 N23 AH16
VCC_NCTF71 VSS_NCTF11 VCC71 VCC_SM71
T18 U17 M23 BA15
VCC_NCTF72 VSS_NCTF12 VCC72 VCC_SM72
L23 AY15
+ VCCP VCC73 VCC_SM73

0.47U_0603_16V4Z
AC22 AW15 R 48 1 2 @ 1K_0402_5%
+ 1.8V VCC74 VCC_SM74 7 C F G18
M19 AB22 AV15 R 50 1 2 @ 1K_0402_5%
VCC100 VCC75 VCC_SM75 7 C F G19
L19 AR6 Y22 AU15 1 R 51 1 2 @ 1K_0402_5%
VCC101 VCC_SM100 VCC76 VCC_SM76 7 C F G20
N18 AP6 W22 AT15
VCC102 VCC_SM101 VCC77 VCC_SM77

C93
M18 AN6 P22 AR15
L18 VCC103 VCC_SM102 AL6 N22 VCC78 VCC_SM78 AJ15
VCC104 VCC_SM103 VCC79 VCC_SM79 2
P17 AK6 M22 AJ14
VCC105 VCC_SM104 VCC80 VCC_SM80
N17 AJ6 L22 AJ13
VCC106 VCC_SM105 VCC81 VCC_SM81
M17 AV1 AC21 AH13
VCC107 VCC_SM106 VCC82 VCC_SM82
N16 AJ1 AA21 AK12
VCC108 VCC_SM107 VCC83 VCC_SM83
M16 W21 AJ12
VCC109 VCC84 VCC_SM84
0.47U_0603_16V4Z

0.47U_0603_16V4Z

L16 N21 AH12

VCC110 M21 VCC85 VCC_SM85 AG12
VCC86 VCC_SM86 Place near pin BA15
1 1 L21 AK11
C ALISTOGA_FCBGA1466~D VCC87 VCC_SM87
AC20 BA8
VCC88 VCC_SM88
C15

C17

UMA_ GM@ AB20 AY8

VCC89 VCC_SM89
Y20 AW8
2 2 VCC90 VCC_SM90
W20 AV8
VCC91 VCC_SM91
P20 AT8
VCC92 VCC_SM92
N20 AR8
VCC93 VCC_SM93
M20 AP8
VCC94 VCC_SM94
L20 BA6
VCC95 VCC_SM95
AB19 AY6
VCC96 VCC_SM96
Place near pin AV1 & AJ1 AA19
VCC97 VCC_SM97
AW6
Y19 AV6
VCC98 VCC_SM98
N19 AT6
VCC99 VCC_SM99

C ALISTOGA_FCBGA1466~D
A A
UMA_ GM@

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (5/6)
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C u s tom I G L50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 11 of 48
5 4 3 2 1
 5 4 3 2 1

U 14I U1 4 J
AC41 AE34 AN21 AG10
AA41 VSS0 VSS100 AC34 AL21 VSS200 VSS280 AC10
VSS1 VSS101 VSS201 VSS281
W41 C34 AB21 W10
VSS2 VSS102 VSS202 VSS282
T41 AW33 Y21 U10
VSS3 VSS103 VSS203 VSS283
P41 AV33 P21 BA9
M41 VSS4 VSS104 AR33 K21 VSS204 VSS284 AW9
D VSS5 VSS105 VSS205 VSS285 D
J41 AE33 J21 AR9
VSS6 VSS106 VSS206 VSS286
F41 AB33 H21 AH9
AV40 VSS7 VSS107 Y33 C21 VSS207 VSS287 AB9
VSS8 VSS108 VSS208 VSS288
AP40 V33 AW20 Y9
VSS9 VSS109 VSS209 VSS289
AN40 T33 AR20 R9
AK40 VSS10 VSS110 R33 AM20 VSS210 VSS290 G9
VSS11 VSS111 VSS211 VSS292
AJ40 M33 AA20 E9
VSS12 VSS112 VSS212 VSS291
AH40 H33 K20 A9
VSS13 VSS113 VSS213 VSS293
AG40 G33 B20 AG8
VSS14 VSS114 VSS214 VSS294
AF40 F33 A20 AD8
VSS15 VSS115 VSS215 VSS295
AE40 D33 AN19 AA8
VSS16 VSS116 VSS216 VSS296
B40 B33 AC19 U8
AY39 VSS17 VSS117 AH32 W19 VSS217 VSS297 K8
VSS18 VSS118 VSS218 VSS298
AW39 AG32 K19 C8
VSS19 VSS119 VSS219 VSS299
AV39 AF32 G19 BA7
AR39 VSS20 VSS120 AE32 C19 VSS220 VSS300 AV7
VSS21 VSS121 VSS221 VSS301
AN39 AC32 AH18 AP7
VSS22 VSS122 VSS222 VSS302
AJ39 AB32 P18 AL7
VSS23 VSS123 VSS223 VSS303
AC39 G32 H18 AJ7
VSS24 VSS124 VSS224 VSS304
AB39 B32 D18 AH7
VSS25 VSS125 VSS225 VSS305
AA39 AY31 A18 AF7
VSS26 VSS126 VSS226 VSS306
Y39 AV31 AY17 AC7
W39 VSS27 VSS127 AN31 AR17 VSS227 VSS307 R7
VSS28 VSS128 VSS228 VSS308
V39 AJ31 AP17 G7
T39
VSS29 VSS129
AG31 AM17
VSS229 P O W E R VSS309
D7
R39 VSS30 VSS130 AB31 AK17 VSS230 VSS310 AG6
VSS31 VSS131 VSS231 VSS311
P39 Y31 AV16 AD6
VSS32 VSS132 VSS232 VSS312
N39 AB30 AN16 AB6
VSS33 VSS133 VSS233 VSS313
M39 E30 AL16 Y6
L39 VSS34
VSS35
P O W E R VSS134
VSS135
AT29 J16 VSS234
VSS235
VSS314
VSS315
U6
J39 AN29 F16 N6
VSS36 VSS136 VSS236 VSS316
H39 AB29 C16 K6
C G39 VSS37 VSS137 T29 AN15 VSS237 VSS317 H6 C
VSS38 VSS138 VSS238 VSS318
F39 N29 AM15 B6
VSS39 VSS139 VSS239 VSS319
D39 K29 AK15 AV5
AT38 VSS40 VSS140 G29 N15 VSS240 VSS320 AF5
VSS41 VSS141 VSS241 VSS321
AM38 E29 M15 AD5
VSS42 VSS142 VSS242 VSS322
AH38 C29 L15 AY4
VSS43 VSS143 VSS243 VSS323
AG38 B29 B15 AR4
AF38 VSS44 VSS144 A29 A15 VSS244 VSS324 AP4
VSS45 VSS145 VSS245 VSS325
AE38 BA28 BA14 AL4
VSS46 VSS146 VSS246 VSS326
C38 AW28 AT14 AJ4
AK37 VSS47 VSS147 AU28 AK14 VSS247 VSS327 Y4
VSS48 VSS148 VSS248 VSS328
AH37 AP28 AD14 U4
VSS49 VSS149 VSS249 VSS329
AB37 AM28 AA14 R4
AA37 VSS50 VSS150 AD28 U14 VSS250 VSS330 J4
VSS51 VSS151 VSS251 VSS331
Y37 AC28 K14 F4
VSS52 VSS152 VSS252 VSS332
W37 W28 H14 C4
VSS53 VSS153 VSS253 VSS333
V37 J28 E14 AY3
T37 VSS54 VSS154 E28 AV13 VSS254 VSS334 AW3
VSS55 VSS155 VSS255 VSS335
R37 AP27 AR13 AV3
VSS56 VSS156 VSS256 VSS336
P37 AM27 AN13 AL3
VSS57 VSS157 VSS257 VSS337
N37 AK27 AM13 AH3
VSS58 VSS158 VSS258 VSS338
M37 J27 AL13 AG3
VSS59 VSS159 VSS259 VSS339
L37 G27 AG13 AF3
J37 VSS60 VSS160 F27 P13 VSS260 VSS340 AD3
VSS61 VSS161 VSS261 VSS341
H37 C27 F13 AC3
VSS62 VSS162 VSS262 VSS342
G37 B27 D13 AA3
VSS63 VSS163 VSS265 VSS343
F37 AN26 B13 G3
VSS64 VSS164 VSS264 VSS344
D37 M26 AY12 AT2
VSS65 VSS165 VSS263 VSS345
AY36 K26 AC12 AR2
VSS66 VSS166 VSS266 VSS346
AW36 F26 K12 AP2
AN36 VSS67 VSS167 D26 H12 VSS267 VSS347 AK2
VSS68 VSS168 VSS268 VSS348
AH36 AK25 E12 AJ2
B VSS69 VSS169 VSS269 VSS349 B
AG36 P25 AD11 AD2
VSS70 VSS170 VSS270 VSS350
AF36 K25 AA11 AB2
VSS71 VSS171 VSS271 VSS351
AE36 H25 Y11 Y2
VSS72 VSS172 VSS272 VSS352
AC36 E25 J11 U2
VSS73 VSS173 VSS273 VSS353
C36 D25 D11 T2
B36 VSS74 VSS174 A25 B11 VSS274 VSS354 N2
VSS75 VSS175 VSS275 VSS355
BA35 BA24 AV10 J2
VSS76 VSS176 VSS276 VSS356
AV35 AU24 AP10 H2
AR35 VSS77 VSS177 AL24 AL10 VSS277 VSS357 F2
VSS78 VSS178 VSS278 VSS358
AH35 AW23 AJ10 C2
VSS79 VSS179 VSS279 VSS359
AB35 AT23 AL1
VSS80 VSS180 VSS360
AA35 AN23
VSS81 VSS181 C AL ISTOGA_FCBGA1466~D
Y35 AM23
VSS82 VSS182
W35 AH23 UMA_ GM@
VSS83 VSS183
V35 AC23
T35 VSS84 VSS184 W23
VSS85 VSS185
R35 K23
VSS86 VSS186
P35 J23
VSS87 VSS187
N35 F23
VSS88 VSS188
M35 C23
VSS89 VSS189
L35 AA22
VSS90 VSS190
J35 K22
VSS91 VSS191
H35 G22
VSS92 VSS192
G35 F22
VSS93 VSS193
F35 E22
VSS94 VSS194
D35 D22
VSS95 VSS195
AN34 A22
VSS96 VSS196
AK34 BA21
VSS97 VSS197
AG34 AV21
VSS98 VSS198
AF34 AR21
VSS99 VSS199
C ALISTOGA_FCBGA1466~D
A A
UMA_ GM@

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (6/6)
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C u s tom I G L50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 12 of 48
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

Layout Note:
+1.8V + 1.8V
+DDR_MCH_REF
trace width and + D D R_MCH_REF1
8 D D R_A_DQS#[0..7] + D D R _MCH_REF1 14
spacing is 20/20.
8 D D R _A_D[0..63] JP 3

2.2U_0805_16V4Z

0.1U_0402_16V4Z
1 2
VREF VSS D D R _A_D6
8 D D R _ A_DM[0..7] 3 4 1 1
+ 1.8V VSS DQ4

C145

C134
D D R _A_D4 5 6 D D R _A_D0
D D R _A_D1 DQ0 DQ5
8 D D R _A_DQS[0..7] 7 8
9 DQ1 VSS 10 D D R _A_DM0
VSS DM0

1
D D R_A_DQS#0 11 12 2 2
8 D D R _ A_MA[0..13] DQS0# VSS
R 86 D D R_A_DQS0 13 14 D D R _A_D5
DQS0 DQ6 D D R _A_D7
15 16
100_0402_1% D D R _A_D2 17 VSS DQ7 18
D D D R _A_D3 DQ2 VSS D D R _A_D13 D
19 20

2
+ D D R_MCH_REF1 DQ3 DQ12 D D R _A_D12
14 + D D R_MCH_REF1 21 22
VSS DQ13

0.1U_0402_16V4Z
D D R _A_D8 23 24
DQ8 VSS

1
D D R _A_D14 D D R _A_DM1
Layout Note: R 87
25
DQ9 DM1
26
1 27 28
Pla c e near JP41 D D R_A_DQS#1 29 VSS VSS 30 M_ CLK_DDR0
DQS1# CK0 M_ CLK_DDR0 7

C149
100_0402_1% D D R_A_DQS1 31 32 M_ CLK_DDR#0
DQS1 CK0# M_ CLK_DDR#0 7
33 34

2
2 D D R _A_D9 VSS VSS D D R _A_D11
35 36
D D R _A_D15 DQ10 DQ14 D D R _A_D10
37 38
DQ11 DQ15
39 40
VSS VSS

+1.8V 41 42
D D R _A_D16 VSS VSS D D R _A_D20
43 44
D D R _A_D17 45 DQ16 DQ20 46 D D R _A_D21
DQ17 DQ21
47 48
VSS VSS
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
D D R_A_DQS#2 49 50
DQS2# NC PM_EXTTS#0 7 ,14
1 1 1 1 1 1 1 1 1 D D R_A_DQS2 51 52 D D R _A_DM2
DQS2 DM2
C89

C87

C28

C92

C30

C85

C57

C43

C83
53 54
D D R _A_D18 VSS VSS D D R _A_D23
55 56
D D R _A_D19 DQ18 DQ22 D D R _A_D22
57 58
2 2 2 2 2 2 2 2 2 59 DQ19 DQ23 60
D D R _A_D29 VSS VSS D D R _A_D28
61 62
D D R _A_D24 DQ24 DQ28 D D R _A_D25
63 64
65 DQ25 DQ29 66
D D R _A_DM3 VSS VSS D D R_A_DQS#3
67 68
DM3 DQS3# D D R_A_DQS3
1 4,33 EC_P80_DATA 69 70
NC DQS3
71 72
D D R _A_D26 73 VSS VSS 74 D D R _A_D31
D D R _A_D27 DQ26 DQ30 D D R _A_D30
75 76
DQ27 DQ31
77 78
C D D R _ CKE0_DIMMA 79 VSS VSS 80 D D R _ CKE1_DIMMA C
7 D D R _ CKE0_DIMMA CKE0 NC/CKE1 D D R _ C KE1_DIMMA 7
81 82
VDD VDD
1 4,33 EC_P80_CLK 83 84
D DR_A_BS#2 85 NC NC/A15 86
8 D DR_A_BS#2 BA2 NC/A14
Layout Note: D D R _A_MA12
87
VDD VDD
88
D D R _A_MA11
89 90
Pla c e one cap close to every 2 pullup D D R _A_MA9 A12 A11 D D R _A_MA7
91 92
D D R _A_MA8 93 A9 A7 94 D D R _A_MA6
resistors terminated to +0.9VS 95
A8 A6
96
D D R _A_MA5 VDD VDD D D R _A_MA4
97 98
D D R _A_MA3 99 A5 A4 100 D D R _A_MA2
D D R _A_MA1 A3 A2 D D R _A_MA0
101 102
A1 A0
103 104
D D R _A_MA10 105 VDD VDD 106 D DR_A_BS#1
A10/AP BA1 D DR_A_BS#1 8
D DR_A_BS#0 107 108 D D R _A_RAS#
8 D DR_A_BS#0 BA0 RAS# D D R _A_RAS# 8
D D R_A_W E# 109 110 D D R _ C S0_DIMMA#
+0.9VS 8 D D R_A_W E# WE# S0# D D R _ C S0_DIMMA# 7
111 112
D D R _A_CAS# 113 VDD VDD 114 M_ODT0
8 D D R _A_CAS# CAS# ODT0 M_ODT0 7
D D R _ C S1_DIMMA# 115 116 D D R _A_MA13
7 D D R _ C S1_DIMMA# NC/S1# NC/A13
117 118
VDD VDD
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

M_ODT1 119 120

7 M_ODT1 NC/ODT1 NC
121 122
D D R _A_D37 VSS VSS D D R _A_D39
1 1 1 1 1 1 1 1 1 1 1 1 1 123 124
D D R _A_D36 125 DQ32 DQ36 126 D D R _A_D38
DQ33 DQ37
127 128
D D R_A_DQS#4 VSS VSS D D R _A_DM4
129 130
2 2 2 2 2 2 2 2 2 2 2 2 2 D D R_A_DQS4 DQS4# DM4
131 132
DQS4 VSS
C74

C66

C60

C51

C42

C34

C40

C53

C64

C77

C39

C70

C33

133 134 D D R _A_D34

D D R _A_D35 VSS DQ38 D D R _A_D33
135 136
D D R _A_D32 DQ34 DQ39
137 138
139 DQ35 VSS 140 D D R _A_D45
D D R _A_D40 VSS DQ44 D D R _A_D43
141 142
B D D R _A_D44 DQ40 DQ45 B
143 144
DQ41 VSS D D R_A_DQS#5
145 146
D D R _A_DM5 VSS DQS5# D D R_A_DQS5
147 148
DM5 DQS5
149 150
D D R _A_D41 VSS VSS D D R _A_D47
151 152
D D R _A_D46 153 DQ42 DQ46 154 D D R _A_D42
DQ43 DQ47
155 156
D D R _A_D49 VSS VSS D D R _A_D52
157 158
+0.9VS D D R _A_D48 DQ48 DQ52 D D R _A_D53
Layout Note: 159
DQ49 DQ53
160
P l ace t hese r esi st or 161 162
RP1 R P2 VSS VSS M_ CLK_DDR1
163 164 M_ CLK_DDR1 7
D D R_A_W E# D D R _A_RAS# cl osel y JP41,all NC,TEST CK1 M_ CLK_DDR#1
1 8 8 1 165 166 M_ CLK_DDR#1 7
D D R _A_CAS# D D R _ C S0_DIMMA# D D R_A_DQS#6 VSS CK1#
2 7 7 2 t r ace l engt h M ax=1.5" 167
DQS6# VSS
168
D D R _ C S1_DIMMA# 3 6 6 3 M_ODT0 D D R_A_DQS6 169 170 D D R _A_DM6
M_ODT1 D D R _A_MA13 DQS6 DM6
4 5 5 4 171 172
D D R _A_D54 173 VSS VSS 174 D D R _A_D51
56_0804_8P4R_5% 56_0804_8P4R_5% D D R _A_D50 DQ50 DQ54 D D R _A_D55
175 176
DQ51 DQ55
177 178
R P6 D D R _A_D61 VSS VSS D D R _A_D57
179 180
56_0402_5% D DR_A_BS#1 D D R _A_D60 DQ56 DQ60 D D R _A_D56
5 4 181 182
D DR_A_BS#0 R 39 D D R _A_MA0 DQ57 DQ61
1 2 6 3 183 184
D D R _A_MA2 D D R _A_DM7 VSS VSS D D R_A_DQS#7
7 2 185 186
D D R _A_MA10 R 43 D D R _A_MA4 DM7 DQS7# D D R_A_DQS7
1 2 8 1 187 188
56_0402_5% D D R _A_D59 VSS DQS7
189 190
56_0804_8P4R_5% D D R _A_D58 DQ58 VSS D D R _A_D62
191 192
DQ59 DQ62 D D R _A_D63
193 194
R P7 RP9 C LK_SMBDATA VSS DQ63
14,15 C LK_SMBDATA 195 196
D D R _A_MA1 D D R _A_MA6 CLK_SMBCLK SDA VSS
4 5 5 4 1 4,15 CLK_SMBCLK 197 198
D D R _A_MA3 D D R _A_MA7 SCL SA0
3 6 6 3 +3VS 199 200
D D R _A_MA5 D D R _A_MA11 VDDSPD SA1
2 7 7 2

1
10K_0402_5%

10K_0402_5%
D D R _A_MA8 1 8 8 1 D D R _ CKE1_DIMMA 1
C7 F OX_ASOA426-M2RN-7F
A

R13

R15
56_0804_8P4R_5% 56_0804_8P4R_5% A
ME@
0 . 1 U_0402_16V4Z
R P10 2
SO-DIMM A

2
D D R _A_MA9 4 5
D D R _A_MA12 3 6
D DR_A_BS#2 2 7
D D R _ CKE0_DIMMA 1 8 Top side
56_0804_8P4R_5% Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT1
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C u s tom I G L50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 13 of 48
5 4 3 2 1
 5 4 3 2 1

+ 1.8V +1.8V
8 D D R_B_DQS#[0..7]

8 D D R _B_D[0..63]
+ D D R_MCH_REF1
+ D D R_MCH_REF1 13
8 D D R _B_DM[0..7] J P4

2.2U_0805_16V4Z

0.1U_0402_16V4Z
8 D D R_B_DQS[0..7] 1 2
VREF VSS D D R_B_D5
3 4 1 1
D D R_B_D0 VSS DQ4 D D R_B_D4
8 D D R _ B_MA[0..13] 5 6
DQ0 DQ5

C146

C135
D D R_B_D1 7 8
DQ1 VSS D D R_B_DM0
9 10
D DR_B_DQS#0 VSS DM0 2 2
11 12
D DR_B_DQS0 DQS0# VSS D D R_B_D6
13 14
15 DQS0 DQ6 16 D D R_B_D7
D D D R_B_D2 VSS DQ7 D
17 18
D D R_B_D3 DQ2 VSS D D R_B_D12
Layout Note: 19
DQ3 DQ12
20
D D R_B_D13
21 22
Pla c e near JP42 D D R_B_D8 VSS DQ13
23 24
D D R_B_D9 DQ8 VSS D D R_B_DM1
25 26
27 DQ9 DM1 28
D DR_B_DQS#1 VSS VSS M_ CLK_DDR3
29 30 M_ CLK_DDR3 7
D DR_B_DQS1 DQS1# CK0 M_ CLK_DDR#3
31 32 M_ CLK_DDR#3 7
DQS1 CK0#
33 34
D D R_B_D10 VSS VSS D D R_B_D14
35 36
D D R_B_D11 DQ10 DQ14 D D R_B_D15
37 38
+ 1.8V DQ11 DQ15
39 40
VSS VSS

41 42
VSS VSS
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
D D R_B_D17 43 44 D D R_B_D21
D D R_B_D20 DQ16 DQ20 D D R_B_D16
1 1 1 1 1 1 1 1 1 45 46
DQ17 DQ21
C29

C23

C90

C96

C22

C68

C75

C88

C32
47 48
D DR_B_DQS#2 VSS VSS
49 50 PM_EXTTS#0 7 ,13
D DR_B_DQS2 DQS2# NC D D R_B_DM2
51 52
2 2 2 2 2 2 2 2 2 DQS2 DM2
53 54
D D R_B_D18 VSS VSS D D R_B_D22
55 56
D D R_B_D19 57 DQ18 DQ22 58 D D R_B_D23
DQ19 DQ23
59 60
D D R_B_D28 VSS VSS D D R_B_D26
61 62
D D R_B_D25 63 DQ24 DQ28 64 D D R_B_D24
DQ25 DQ29
65 66
D D R_B_DM3 VSS VSS D DR_B_DQS#3
67 68
DM3 DQS3# D DR_B_DQS3
13,33 EC_P80_DATA 69 70
71 NC DQS3 72
D D R_B_D30 VSS VSS D D R_B_D29
73 74
D D R_B_D31 DQ26 DQ30 D D R_B_D27
75 76
C 77 DQ27 DQ31 78 C
D D R _CKE2_DIMMB VSS VSS D D R _CKE3_DIMMB
7 D D R _CKE2_DIMMB 79 80 D D R _ CKE3_DIMMB 7
CKE0 NC/CKE1
81 82
83 VDD VDD 84
Layout Note: 13,33 EC_P80_CLK
DDR_B_BS#2 NC NC/A15
8 DDR_B_BS#2 85 86
Pla c e one cap close to every 2 pullup BA2 NC/A14
87 88
D D R_B_MA12 VDD VDD D D R_B_MA11
89 90
resistors terminated to +0.9VS D D R_B_MA9 91 A12 A11 92 D D R_B_MA7
D D R_B_MA8 A9 A7 D D R_B_MA6
93 94
A8 A6
95 96
D D R_B_MA5 97 VDD VDD 98 D D R_B_MA4
D D R_B_MA3 A5 A4 D D R_B_MA2
99 100
D D R_B_MA1 A3 A2 D D R_B_MA0
101 102
103 A1 A0 104
D D R_B_MA10 VDD VDD DDR_B_BS#1
105 106 D DR_B_BS#1 8
+ 0.9VS DDR_B_BS#0 A10/AP BA1 D D R_B_RAS#
8 DDR_B_BS#0 107 108 D D R_B_RAS# 8
D DR_B_W E# BA0 RAS# D D R _ CS2_DIMMB#
8 D DR_B_W E# 109 110 D D R _ CS2_DIMMB# 7
111 WE# S0# 112
D D R_B_CAS# VDD VDD M_ODT2
8 D D R_B_CAS# 113 114 M_ODT2 7
CAS# ODT0
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

D D R _ CS3_DIMMB# 115 116 D D R_B_MA13

7 D D R _CS3_DIMMB# NC/S1# NC/A13
117 118
M_ODT3 VDD VDD
1 1 1 1 1 1 1 1 1 1 1 1 1 7 M_ODT3 119 120
NC/ODT1 NC
121 122
D D R_B_D32 123 VSS VSS 124 D D R_B_D36
D D R_B_D33 DQ32 DQ36 D D R_B_D37
125 126
2 2 2 2 2 2 2 2 2 2 2 2 2 DQ33 DQ37
127 128
VSS VSS
C73

C80

C76

C35

C41

C56

C81

C62

C52

C84

C65

C38

C36

D DR_B_DQS#4 129 130 D D R_B_DM4

D DR_B_DQS4 DQS4# DM4
131 132
DQS4 VSS D D R_B_D39
133 134
D D R_B_D34 VSS DQ38 D D R_B_D38
135 136
D D R_B_D35 137 DQ34 DQ39 138
DQ35 VSS D D R_B_D44
139 140
B D D R_B_D40 VSS DQ44 D D R_B_D45 B
141 142
D D R_B_D41 DQ40 DQ45
143 144
DQ41 VSS D DR_B_DQS#5
145 146
D D R_B_DM5 VSS DQS5# D DR_B_DQS5
147 148
DM5 DQS5
149 150
D D R_B_D42 151 VSS VSS 152 D D R_B_D46
D D R_B_D43 DQ42 DQ46 D D R_B_D47
153 154
DQ43 DQ47
155 156
D D R_B_D48 157 VSS VSS 158 D D R_B_D52
D D R_B_D49 DQ48 DQ52 D D R_B_D53
Layout Note: 159
DQ49 DQ53
160
P l ace t hese r esi st or 161 162
+0.9VS VSS VSS M_ CLK_DDR2
163 164 M_ CLK_DDR2 7
cl osel y JP42,all NC,TEST CK1 M_ CLK_DDR#2
165 166
VSS CK1# M_ CLK_DDR#2 7
R P3 RP4 t r ace l engt h M ax=1.5" D DR_B_DQS#6 167 168
D D R_B_CAS# D D R_B_MA13 D DR_B_DQS6 DQS6# VSS D D R_B_DM6
8 1 4 5 169 170
D DR_B_W E# 7 2 3 6 M_ODT2 171 DQS6 DM6 172
D D R _ CS3_DIMMB# D D R _ CS2_DIMMB# D D R_B_D51 VSS VSS D D R_B_D54
6 3 2 7 173 174
M_ODT3 D D R_B_RAS# D D R_B_D50 DQ50 DQ54 D D R_B_D55
5 4 1 8 175 176
DQ51 DQ55
177 178
56_0804_8P4R_5% 56_0804_8P4R_5% D D R_B_D56 VSS VSS D D R_B_D60
179 180
D D R_B_D61 DQ56 DQ60 D D R_B_D57
181 182
RP5 DQ57 DQ61
183 184
DDR_B_BS#1 D D R_B_DM7 VSS VSS D DR_B_DQS#7
4 5 185 186
DDR_B_BS#0 R 44 1 D D R_B_MA0 DM7 DQS7# D DR_B_DQS7
2 3 6 187 188
56_0402_5% D D R_B_MA2 D D R_B_D59 VSS DQS7
2 7 189 190
D D R_B_MA10 R 41 1 D D R_B_MA4 D D R_B_D58 DQ58 VSS D D R_B_D62
2 1 8 191 192
DQ59 DQ62 D D R_B_D63
193 194
56_0804_8P4R_5% C LK_SMBDATA VSS DQ63
1 3,15 C LK_SMBDATA 195 196
CLK_SMBCLK SDA VSS R 12
1 3,15 CLK_SMBCLK 197 198
R P8 RP11 SCL SAO
+3VS 199 200 1 2 +3VS
D D R_B_MA1 D D R_B_MA7 VDDSPD SA1
5 4 4 5

1
10K_0402_5%
D D R_B_MA3 6 3 3 6 D D R_B_MA11 1 10K_0402_5%

R14
A D D R_B_MA5 7 2 2 7 D D R_B_MA6 C6 P-TW O_A5692B-A0G16-P A
D D R_B_MA9 8 1 1 8 D D R _CKE3_DIMMB ME@
0 . 1 U_0402_16V4Z
56_0804_8P4R_5% 56_0804_8P4R_5% 2
SO-DIMM B

2
R P12
D D R _CKE2_DIMMB 8 1
DDR_B_BS#2 7 2
D D R_B_MA12
D D R_B_MA8
6 3
Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
5 4 Issued Date 2005/10/06 Deciphered Date 2006/10/06
56_0804_8P4R_5%
THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT2
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS I G L50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 14 of 48
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

FSLC FSLB FSLA CPU SRC PCI +3VS + C K _ VDD_MAIN1

CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz
+3VS 1 2
R 428 R 419 R 429 0_0805_5% 1 1 1 1 1 1 1
0 0 1 133 100 33.3 C 227 C 218 C 219 C 432 C 222 C 233 C 449
2.2K_0402_5% 2.2K_0402_5%
Q29 1 0 U_0805_10V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z
2N7002_SOT23 2 2 2 2 2 2 2
0 1 1 166 100 33.3
1 3 C LK_SMBDATA

S
2 1,28,37 IC H_ SMBDATA
Table : ICS954306 + C K _ VDD_MAIN2

G
2
D + C K_VDD_REF C446 27P_0402_50V8J D
FSB Frequency Selet: +3VS 1
R 331
2
0_0805_5%
1
R 330
2
+3VS 1 1 1

1
C 413 C 458 C 457 1_0805_1%
Stuff CLK_Ra CLK_Rb CLK_Rc 1 2 + CK_VDD_48 Y2

2
1 0 U_0805_10V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z R 427 C LK_XTAL_IN 1 4 .31818MHZ_16PF_DSX840GA

G
CPU Driven 2 2 2 2.2_0805_1%

2
CLK_SMBCLK CLK_XTAL_OUT C448 27P_0402_50V8J
* (Default) No Stuff CLK_Rd CLK_Re CLK_Rf
2 1,28,37 IC H_SMBCLK 1 3

S
L 17
2N7002_SOT23 C HB1608U301_0603
Stuff CLK_Rd CLK_Re CLK_Rf Q28 U2 9
533MHz + C K _ VDD_MAIN1
1 2 +3VS
1 1
No Stuff CLK_Ra CLK_Rb CLK_Rc C 450 C 451 Pl ace cr yst al within
1 7 500 m i l s of CK410
VDDSRC VDDA 0 . 1 U_0402_16V4Z 1 0 U_0805_10V4Z
49
54 VDDSRC 8 2 2
Stuff CLK_Rd CLK_Rf VDDSRC GNDA Place near U4
65
VDDSRC
667MHz Place these components
No Stuff CLK_Ra CLK_Rb CLK_Rc 25 H _STP_PCI#
PCI_SRC_STOP# H_STP_PCI# 21
30
CLK_Re 36
VDDPCI
VDDPCI CPU_STOP#
24 H _STP_CPU#
H_STP_CPU# 21
near each pin within 40
HGT30 @ 10/11 mils.
12
+ VCCP VDDCPU MC H _BCLK C L K_MCH_BCLK
11 1 2 C L K_MCH_BCLK 7
CPUCLKT1LP
1 2 + C K_VDD_REF 18 R 424 0_0402_5%
C 452 0 . 1 U_0402_16V4Z VDDREF 10 MC H_BCLK# 1 2 C L K_MCH_BCLK#
CPUCLKC1LP C L K_MCH_BCLK# 7
2

1 2 + CK_VDD_48 40 R 423 0_0402_5% C LK_CPU_BCLK 2 1

@ R 349 C 422 0 . 1 U_0402_16V4Z VDD48 R 434 @ 49.9_0402_1%
56_0402_5% 14 C P U_BCLK 1 2 C LK_CPU_BCLK C LK_CPU_BCLK# 2 1
CPUCLKT0LP C LK_CPU_BCLK 4
R 353 CLK_Rd C LK_XTAL_IN 20 R 426 0_0402_5% R 433 @ 49.9_0402_1%
8.2K_0402_5% X1 C P U_BCLK# C LK_CPU_BCLK#
13 1 2
1

CPUCLKC0LP C LK_CPU_BCLK# 4
FSA 2 1 1 2 R 425 0_0402_5% C L K_MCH_BCLK 2 1
C MC H_CLKSEL0 7 C
CLK_XTAL_OUT 19 R 432 @ 49.9_0402_1%
R 326 X2 C L K_MCH_BCLK# 2
5 C PU_BSEL0 1 2 6 1
R 332 1K_0402_5% R 364 CPUCLKT2_ITP/SRCCLKT10LP R 431 @ 49.9_0402_1%
0_0402_5% C L K _ 48M_ICH 2 1 FSA 41 5
21 C L K _ 48M_ICH USB_48MHz/FSLA CPUCLKC2_ITP/SRCCLKC10LP
1

CLK_Ra 33_0402_5%
R 323 F SB 45
FSLB/TEST_MODE/24Mhz P C IE _MCARD11 C L K _ PCIE_MCARD1 C L K _MCH_SSCDREFCLK
3 2 C L K _PCIE_MCARD1 28 1 2
@ 1K_0402_5% C L K _ 14M_ICH C LKREF1 SRCCLKT9LP R 847 0_0402_5% R 345 @ 49.9_0402_1%
21 C L K _ 14M_ICH 2 1 23
R 412 33_0402_5% REF0/FSLC/TEST_SEL P C IE _MCARD1# C L K _PCIE_MCARD1# C L K _MCH_SSCDREFCLK#
2 1 2 1 2
2

SRCCLKC9LP C L K _PCIE_MCARD1# 28
R 848 0_0402_5% R 344 @ 49.9_0402_1%
33_0402_5% 2 1 R 381 P C I_ MINI 34 72 C L KREQ_MCARD1# C L K _ PCIE_MCARD 1 2
26 C LK_PCI_1394 PCICLK4/FCTSEL1 CLKREQ9# C L KREQ_MCARD1# 28
R 341 @ 49.9_0402_1%
+ VCCP 33_0402_5% 2 1 R 387 P C I_EC 33 70 C L K _ PCIE_MCARD# 1 2
33 C LK_PCI_LPC SEL_48M/PCICLK3 SRCCLKT8LP R 340 @ 49.9_0402_1%
24 C L K_PCI_PCM 33_0402_5% 2 1 R 388 P C I _PCM 32 69 C L K_MCH_3GPLL 1 2
SEL_24M/PCICLK2 SRCCLKC8LP
2

R 398 @ 49.9_0402_1%
HGT30 @ 10/7 R 123 HGT30 @ 10/7 15_0402_5% 2 1 R 404 P C I_ LAN 27 71 C L K_MCH_3GPLL# 1 2
27 C L K _ PCI_LAN SEL_PCI6/PCICLK1 CLKREQ8#
15_0402_5% 2 1 R 395 R 409 @ 49.9_0402_1%
3 2,34 C L K_PCI_DB
R 701 @ 1K_0402_5% 66 P C IE_SATA 1 2 C LK_PCIE_SATA C L K _PCIE_VGA 1 2
SRCCLKT7LP C LK_PCIE_SATA 20
8.2K_0402_5% 15_0402_5% 2 1 R 145 C LK_CODEC 22 R 414 0_0402_5% R 343 @ 49.9_0402_1%
1

3 2,34 C LK_14M_SIO SEL_PCI5/REF1

F SB 2 1 1 2 67 P CIE_SATA# 1 2 C LK_PCIE_SATA# C L K _PCIE_VGA# 1 2
MC H_CLKSEL1 7 SRCCLKC7LP C LK_PCIE_SATA# 20
R 417 0_0402_5% R 342 @ 49.9_0402_1%
1 2 R 122 7 C L K _ MCH_DREFCLK C L K _ MCH_DREFCLK 1 2 MC H_ DREFCLK 43 38 SATAREQ# C L K _ P CIE_ICH 1 2
5 C PU_BSEL1 DOTT_96MHz/27MHz_NonspreadCLKREQ7#/48Mhz_1 SATAREQ# 21
R 121 1K_0402_5% R 362 UMA@ 33_0402_5% R 385 @49.9_0402_1%
0_0402_5% 7 C L K _MCH_DREFCLK# C L K _MCH_DREFCLK#1 2 MC H_ DREFCLK# 44 63 C L K _ PCIE_ICH# 1 2
DOTC_96MHz/27MHz_spread SRCCLKT6LP
1

CLK_Rb R 361 UMA@ 33_0402_5% R 392 @ 49.9_0402_1%

@ R 120 64 C L K _ MCH_DREFCLK 1 2
C L K _ P CI_ICH 2 R 372 1 P C I_ I CH SRCCLKC6LP R 347 @49.9_0402_1%
19 C L K _ P CI_ICH 37
0_0402_5% 33_0402_5% ITP_EN/PCICLK_F0 C L K _MCH_DREFCLK#1
62 2
CLKREQ6# R 346 @ 49.9_0402_1%
CLK_Re
2

C LK_ENABLE# 39 60 MC H _3GPLL 1 2 C L K_MCH_3GPLL C LK_PCIE_SATA 1 2

45 C LK_ENABLE# VTT_PWRGD#/PD SRCCLKT5LP C L K_MCH_3GPLL 7
R 399 0_0402_5% R 413 @ 49.9_0402_1%
B 61 MC H_3GPLL# 1 2 C L K_MCH_3GPLL# C LK_PCIE_SATA# 1 2 B
+ VCCP SRCCLKC5LP C L K_MCH_3GPLL# 7
R 410 0_0402_5% R 416 @ 49.9_0402_1%
13,14 CLK_SMBCLK CLK_SMBCLK 16 29 CLKREQ5# 2 1 MC H_CLKREQ# C L K _PCIE_NC1 2 1
SMBCLK CLKREQ5#/PCICLK6 MC H_CLKREQ# 7
R 394 0_0402_5% R 370 @ 49.9_0402_1%
2

58 P C IE _ ICH 1 2 C L K _ P CIE_ICH C L K _PCIE_NC1# 2 1

SRCCLKT4LP C L K _ PCIE_ICH 21
R 383 R 386 0_0402_5% R 377 @49.9_0402_1%
C LK_SMBDATA 17 59 P C IE _ ICH# 1 2 C L K _ PCIE_ICH#
1 3,14 C LK_SMBDATA SMBDAT SRCCLKC4LP C L K _ PCIE_ICH# 21
R 396 @ 1K_0402_5% R 393 0_0402_5%
8.2K_0402_5% 57
1

C LKREF1 2 CLKREQ4#
1 1 2 MCH_CLKSEL2 7
1 2 C L K IREF 9 55 P C I E_NC1 1 2 C L K _PCIE_NC1
GND SRCCLKT3LP C L K _PCIE_NC1 37
1 2 R 407 R 430 0_0402_5% R 371 EXP@ 0_0402_5%
5 C PU_BSEL2
R 397 1K_0402_5% 4 56 P C I E_NC1# 1 2 C L K _PCIE_NC1#
GNDSRC SRCCLKC3LP C L K _PCIE_NC1# 37
0_0402_5% R 378 EXP@ 0_0402_5%
1

CLK_Rc 15 28 C L KREQ_NC#
+3VS +3VS +3VS +3VS GNDCPU CLKREQ3#/PCICLK5 C LKREQ_NC# 37
@ R 390
ITP PCI6 PCI5 21 52 P C IE _MCARD 1 2 C L K _ PCIE_MCARD SATAREQ# 2 1 +3VS
GNDREF SRCCLKT2LP C L K _PCIE_MCARD 28
0_0402_5% R 356 0_0402_5% R366 10K_0402_5%
1

CLK_Rf 31 53 P C IE _MCARD#1 2 C L K _ PCIE_MCARD#

C L K _PCIE_MCARD# 28
2

R 363 R 368 R 382 R 406 GNDPCI SRCCLKC2LP R 355 0_0402_5% C L KREQ_NC# 2 1

35 26 C L KREQ_MCARD# R137 10K_0402_5%
GNDPCI CLKREQ2# C L KREQ_MCARD# 28
10K_0402_5% 10K_0402_5% @ 10K_0402_5% @ 10K_0402_5%
42 50 P C I E_VGA 1 2 C L K _PCIE_VGA C L KREQ_MCARD# 2 1
2

GND48 SRCCLKT1LP C L K _PCIE_VGA 18

C LK_ENABLE# P C I_ I CH P C I_ LAN C LK_CODEC R 358 VGA@ 0_0402_5% R140 10K_0402_5%
68 51 P C I E_VGA# 1 2 C L K _PCIE_VGA#
C L K _PCIE_VGA# 18
1

GNDSRC SRCCLKC1LP R 357 VGA@ 0_0402_5% C L KREQ_MCARD1#2 1

R 352 R 367 R 389 R 405 73 46 R715 10K_0402_5%
GND CLKREQ1#
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 47 S S CDREFCLK 1 C L K _MCH_SSCDREFCLK
2
LCD100/96/SRC0_TLP C L K _MCH_SSCDREFCLK 7
@ @ R 360 UMA@ 0_0402_5%
2

+3VS 48 S SCDREFCLK#1 2 C L K _MCH_SSCDREFCLK#

LCD100/96/SRC0_CLP C L K _MCH_SSCDREFCLK# 7
R 359 UMA@ 0_0402_5%
A A
1

PCI_MINI = FCTSEL1
R 374 PCI_PME=SEL_PCI6 S LG8LP465VTR_QFN72

@ 10K_0402_5%
FCTSEL1
(PIN34) PIN43 PIN44 PIN47 PIN48
PCI_LAN PIN27
2

P C I_ MINI
0 CLKREQ5 Security Classification Compal Secret Data Compal Electronics, Inc.
1

0 DOT96T DOT96C 96/100M_T 96/100M_C

R373 1 PCICLK6 2005/10/06 2006/10/06 Title
Issued Date Deciphered Date
10K_0402_5%
THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock generator
1 27Mout 27MSSout SRCT0 SRCC0 Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS I G L50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 15 of 48
5 4 3 2 1
 A B C D E F G H

1 1

+ L CDVDD + 5VALW

+ LCDVDD +3VS

2
UMA@
R 196 R 201 Q14

100_0402_1% 100K_0402_5% 1 3

S
UMA@ UMA@ AO3413_SOT23

1 2

1
D R 711

G
2
2N7002_SOT23 0 . 047U_0402_16V4Z
2 1 2
Q15 G
U MA@ S 1 1 1 1

3
10K_0402_5% C 291 C 288 C 289
UMA@ UMA@ C 290

1
4 . 7 U_0805_10V4Z 4 . 7 U_0805_10V4Z
Q16 2 2 2 UMA@ 2
UMA@
DTC124EK_SC59
UMA@
9 GMC H_ L VDDEN 2 R 203 1 2 0 . 1 U_0402_16V4Z
U MA@ 0_0402_5% UMA@

2 2

3
B+ INVPW R_B+ +3VS
0 . 1 U_0603_50V4Z
L14 1 2 0_0805_5% 2 1 C 294

2
R 202
@L15 1 2 0_0805_5% 2 1
C 295 4.7K_0402_5%
68P_0402_50V8K D9

1
C H751H-40_SC76
J P40 1 2 D I SPOFF#
33 B KOFF# D ISPOFF#
1
2 8 33 E NBKL
D 10
<BOM Struc ture>
33 INVT_PW M 3 9
D I SPOFF# C H751H-40_SC76
4
33 D AC _ BRIG 9 GMC H_ENBKL 2 R 52 1 1@ 2
3 5 UMA@ 0_0402_5% 3
INVPW R_B+

2
6
7 R 204
MOLEX_53780-0790 18 G7X_ENBKL 2 R 89 1 100K_0402_5%
VGA@ 0_0402_5%

1
4 4

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Connector
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C us tom I GL 50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 16 of 48
A B C D E F G H

WWW.AliSaler.Com
 A B C D E

TV-OUT Conn.

18 C AR D _ LUMA 2 1 L UMA 36
R 60 VGA@0_0402_5%

18 C AR D _ CRMA 2 1 C R MA 36
R 59 VGA@ 0_0402_5%

2 1
1 18 C ARD_COMP R 61 VGA@ 0_0402_5% C OMP 36 1

1
150_0603_1%

150_0603_1%

150_0603_1%
1

1
R3

R5
9 T V_ LUMA 2 1

R4
R 224 UMA@ 0_0402_5%
2 1

2
9 T V_CRMA
R 225 UMA@ 0_0402_5%

2
2 1
9 TV_COMPS R 223 UMA@ 0_0402_5%

Pop when with internal graphics

CRT Conn.

VGA@
18 C AR D _ VGA_R 2 1 1 2 R ED 36
R 64 0_0402_5% L1 0_0603_5%
VGA@
18 C AR D _ VGA_G 2 1 1 2
R 66 0_0402_5% L2 0_0603_5% GR EEN 36
VGA@
18 C AR D _VGA_B 2 1 1 2 B LUE 36

82P_0402_50V8J

82P_0402_50V8J

82P_0402_50V8J
R 68 0_0402_5% L3 0_0603_5%

1
150_0603_1%
150_0603_1%

150_0603_1%
1 1 1

1
R6

R7

R8

C3

C1

C2
UMA@
2 2 1 2 2 2 2
9 C RT_R

2
R 63 0_0402_5%

2
UMA@ @ @ @
9 C RT_G 2 1
R 65 0_0402_5%
UMA@
9 CRT_B 2 1
R 67 0_0402_5%

Pop when with internal graphics

+3VS +2.5VS +3VS

1

R 197 R 198 R 199 R 200

0_0402_5% 0_0402_5% 0_0402_5%0_0402_5%
VGA@ UMA@ UMA@ VGA@
2

+3VS
+3VS
1

R9 R 10
2.2K_0402_5% 2.2K_0402_5%
2
G

Q1
2

2 VGA@1 3 1 2N7002_SOT23
18 C AR D _DDCDATA VGA_DDC_DAT 36
S

R 80 2 10_0402_5%
18 C AR D _DDCCLK
2
G

R 79 VGA@ 0_0402_5%
2 1 Q2
3 UMA@ R2 @ 0_0402_5% 3 1 2N7002_SOT23 3
VGA_DDC_CLK 36
S

9 3 VD DCDA 1 2
R 76 0_0402_5%
UMA@ 2 1
1 2 + CRT_VCC R 11 @ 0_0402_5%
9 3 VD DCCL
R 75 0_0402_5%
1

1
0 . 1 U_0402_16V4Z R1
1K_0402_5%
C5
2
2
5

U1
VGA@
OE#
P

18 C AR D _ HS YNC 2 1 2 4
R 82 0_0402_5% A Y J VGA_HS 36
G

VGA@
2 1 + CRT_VCC 74AHCT1G125GW _SOT353-5
18 C AR D _ VS YNC
3

R 81 0_0402_5%
0.1U_0402_16V4Z

1
9 C R T _ HS YNC 1 UMA@ 2
R 78 39_0402_5%
C4
5

1 U MA@ 2 2 U2
9 C R T _ VSYNC
R 77 39_0402_5%
OE#
P

2 4
A Y J VGA_VS 36
Pop when with internal graphics
G

74AHCT1G125GW _SOT353-5
3

4 4

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TVout
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C us tom I GL 50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 17 of 48
A B C D E
 5 4 3 2 1

D D
MAX. 4.06A @ 1.8V
MAX. 130mA @ 2.5V
MAX. 655mA @ 3.3V

PEG_M_TXP[0..15]
PEG_M_TXP[0..15] 9
P EG_M_TXN[0..15]
P EG_M_TXN[0..15] 9

PEG_RXP[0..15]
PEG_RXP[0:15] 9
JP7 JP 8
1 41 1 41 P E G_RXN[0..15]
1 41 1 41 P E G_RXN[0:15] 9
PEG_M_TXP1 2 42 PEG_RXP1 PEG_M_TXP0 2 42 PEG_RXP0
PEG_M_TXN1 2 42 P EG_RXN1 PEG_M_TXN0 2 42 P EG_RXN0
3 43 3 43
4 3 43 44 4 3 43 44
PEG_M_TXP3 4 44 PEG_RXP3 PEG_M_TXP2 4 44 PEG_RXP2
5 45 5 45
PEG_M_TXN3 5 45 P EG_RXN3 PEG_M_TXN2 5 45 P EG_RXN2
6 46 6 46
7 6 46 47 7 6 46 47
PEG_M_TXP5 7 47 PEG_RXP5 PEG_M_TXP4 7 47 PEG_RXP4
8 48 8 48
PEG_M_TXN5 8 48 P EG_RXN5 PEG_M_TXN4 8 48 P EG_RXN4
9 49 9 49
9 49 9 49
10 50 10 50
PEG_M_TXP7 11 10 50 51 PEG_RXP7 PEG_M_TXP6 11 10 50 51 PEG_RXP6
PEG_M_TXN7 11 51 P EG_RXN7 PEG_M_TXN6 11 51 P EG_RXN6
12 52 12 52
12 52 12 52
13 53 13 53
C PEG_M_TXP9 14 13 53 54 PEG_RXP9 PEG_M_TXP8 14 13 53 54 PEG_RXP8 C
PEG_M_TXN9 14 54 P EG_RXN9 PEG_M_TXN8 14 54 P EG_RXN8
15 55 15 55
15 55 15 55
16 56 16 56
PEG_M_TXP11 17 16 56 57 PEG_RXP11 PEG_M_TXP10 17 16 56 57 PEG_RXP10 +5VS + 2.5VS
PEG_M_TXN11 17 57 P EG_RXN11 PEG_M_TXN10 17 57 P EG_RXN10
18 58 18 58
18 58 18 58
19 59 19 59
19 59 19 59

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
PEG_M_TXP13 20 60 PEG_RXP13 PEG_M_TXP12 20 60 PEG_RXP12
PEG_M_TXN13 21 20 60 61 P EG_RXN13 PEG_M_TXN12 21 20 60 61 P EG_RXN12
21 61 21 61
22 62 22 62 2 2 2 2
22 62 22 62

C244

C240

C112

C113
PEG_M_TXP15 23 63 PEG_RXP15 PEG_M_TXP14 23 63 PEG_RXP14
PEG_M_TXN15 24 23 63 64 P EG_RXN15 PEG_M_TXN14 24 23 63 64 P EG_RXN14
24 64 24 64
25 65 25 65
25 65 +1.8VS 25 65 S USP# 1 1 1 1
+3VS 26 66 +5VS 15 C L K _PCIE_VGA 26 66 S USP# 2 4,26,33,34,35,37,43,44
+1.5VS 27 26 66 67 27 26 66 67 G7X_THER_ALERT#
27 67 15 C L K _PCIE_VGA# 27 67 G7X_THER_ALERT# 21
<@R03> 28 68 <@R03> 28 68 VGA@ VGA@ VGA@ VGA@
28 68 28 68
29 69 17 C AR D _DDCCLK 29 69
+ 2.5VS 29 69 29 69
30 70 17 C AR D _ DDCDATA 30 70 G7X_ENBKL 16
31 30 70 71 31 30 70 71
31 71 31 71 PLTRST_VGA# 19
32 72 17 C AR D _ VS YNC 32 72
32 72 B+ 32 72
33 73 33 73
33 73 33 73
34 74 17 C AR D _ HS YNC 34 74
34 74 34 74
35 75 35 75
35 75 35 75 +3VS
36 76 17 C AR D _VGA_R 36 76 C ARD_COMP 17
37 36 76 77 37 36 76 77
37 77 37 77
38 78 17 C AR D _VGA_G 38 78 C AR D _ LUMA 17
38 78 38 78

0.047U_0402_16V4Z
0.047U_0402_16V4Z
39 79 39 79
39 79 39 79
40 80 17 C AR D_VGA_B 40 80 C AR D _CRMA 17
40 80 40 80
ACES_88363-08001 ACES_88363-08001 1 1

C110

C111
ME@ ME@

B < New Add Pin.28 for +3VS, Pin.68 for +1.8VS @R03 > 2 2 B

VGA@ VGA@

A A

Title
Compal Electronics, Inc.
THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size
VGA/B connector
D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0 .1
C u s tom I GL 50/51 LA-3771
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. D ate: 星 期 一 , 七 月 31, 2006 Sheet 18 of 48
5 4 3 2 1

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 5 4 3 2 1

D D

+3VS

R 271 1 2 8.2K_0402_5% P C I_DEVSEL#

R 268 1 2 8.2K_0402_5% PCI_STOP#

R 269 1 2 8.2K_0402_5% P C I_ TRDY#

R 263 1 2 8.2K_0402_5% P C I_ FRAME# U3 B

2 4,26,27,32 P C I_ AD[0..31]
P C I _AD0 E18 D7 P CI_REQ0#
AD0 REQ0# P CI_REQ0# 26
R 273 1 2 8.2K_0402_5% P CI_PLOCK# P C I _AD1 C18 E7 P C I _GNT0#
AD1 GNT0# P C I_GNT0# 26
P C I _AD2 A16 C16 P CI_REQ1#
R 287 1 2 8.2K_0402_5% P C I_ IR D Y# P C I _AD3 F18
AD2 PCI REQ1#
D16
P C I _AD4 AD3 GNT1# P CI_REQ2#
E16 C17 P CI_REQ2# 24
R 274 1 AD4 REQ2#
2 8.2K_0402_5% P C I_SERR# P C I _AD5 A18 D17 P C I _GNT2#
P C I_GNT2# 24
P C I _AD6 AD5 GNT2# P CI_REQ3#
E17 E13 P CI_REQ3# 27
R 276 1 AD6 REQ3#
2 8.2K_0402_5% P C I_PERR# P C I _AD7 A17 F13 P C I _GNT3#
P C I_GNT3# 27
P C I _AD8 AD7 GNT3# P CI_REQ4#
A15 A13
R 272 1 P CI_REQ4# P C I _AD9 AD8 REQ4# / GPIO22 +3VS
2 8.2K_0402_5% C14 A14
P C I _AD10 AD9 GNT4# / GPIO48 P CI_REQ5#
E14 C8
R 270 1 AD10 GPIO1 / REQ5#
2 8.2K_0402_5% P CI_REQ3# P C I _AD11 D14 D8

5
P C I _AD12 B12 AD11 GPIO17 / GNT5# U2 1
P C I _AD13 AD12 P C I_CBE#0 P C I_PCIRST#
C13 B15 1

P
AD13 C/BE0# P CI_CBE#0 24,26,27,32 B
P C I _AD14 G15 C12 P C I_CBE#1 4 P CI_RST#
AD14 C/BE1# P CI_CBE#1 24,26,27,32 Y P CI_RST# 2 1,24,25,26,27,32,33,34
P C I _AD15 G13 D12 P C I_CBE#2 2
P CI_CBE#2 24,26,27,32

G
P C I _AD16 E12 AD15 C/BE2# C15 P C I_CBE#3 A
AD16 C/BE3# P CI_CBE#3 24,26,27,32
P C I _AD17 C11 T C7SH08FUF_SSOP5

3
P C I _AD18 AD17 P C I_ IR D Y#
D11 A7 P C I_ IR DY# 24,26,27
C P C I _AD19 A11 AD18 IRDY# E10 P C I _PAR C
AD19 PAR P C I_PAR 24,26,27
P C I _AD20 A10 B18 P C I_PCIRST# 2 1
P C I _AD21 AD20 PCIRST# P C I_DEVSEL# R 257 @ 0_0402_5%
F11 A12 P CI_DEVSEL# 2 4,26,27
+3VS P C I _AD22 F10 AD21 DEVSEL# C9 P C I_PERR#
AD22 PERR# P C I_PERR# 2 4,26,27 +3VS
P C I _AD23 E9 E11 P CI_PLOCK#
P C I _AD24 AD23 PLOCK# P C I_SERR# R 236
D9 B10 P C I_SERR# 2 4,26,27
R 298 1 AD24 SERR#
2 8.2K_0402_5% P C I _PIRQA# P C I _AD25 B9 F15 PCI_STOP#
PCI_STOP# 24,26,27 2 1 PLTRST_VGA# 18

5
P C I _AD26 A8 AD25 STOP# F14 P C I_ TRDY# U1 8 0_0402_5%
AD26 TRDY# P C I_ TRDY# 2 4,26,27,32
R 300 1 2 8.2K_0402_5% P C I_PIRQB# P C I _AD27 A6 F16 P C I_ FRAME# PCI_PLTRST# 1

P
AD27 FRAME# P C I_FRAME# 2 4,26,27,32 B
P C I _AD28 C7 4 PLT_RST#
AD28 Y PLT_RST# 7 ,23,28,37
R 294 1 2 8.2K_0402_5% P C I _PIRQC# P C I _AD29 B6 C26 PCI_PLTRST# 2
AD29 PLTRST# A

G
P C I _AD30 E6 A9 C L K _ P CI_ICH
AD30 PCICLK C L K _ P CI_ICH 15
R 291 1 2 8.2K_0402_5% P C I _PIRQD# P C I _AD31 D6 B19 P C I_PME# T C7SH08FUF_SSOP5

3
AD31 PME# P CI_PME# 33
R 283 1 2 8.2K_0402_5% P C I_PIRQE#

R 290 1 2 8.2K_0402_5% P C I _PIRQF# P C I _PIRQA# A3

Interrupt I/F G8 P C I_PIRQE# 2 1
24 P C I_PIRQA# PIRQA# GPIO2 / PIRQE# P C I_PIRQE#
P C I_PIRQB# B4 F7 P C I _PIRQF# R 235 @ 0_0402_5%
P C I_PIRQB# PIRQB# GPIO3 / PIRQF# P C I_PIRQF# 27
R 279 1 2 8.2K_0402_5% P C I _PIRQG# P C I _PIRQC# C5 F8 P C I _PIRQG#
PIRQC# GPIO4 / PIRQG# P C I_PIRQG# 26
P C I _PIRQD# B5 G7 P C I_ PIRQH#
PIRQD# GPIO5 / PIRQH# P C I_ PIRQH# 26
R 284 1 2 8.2K_0402_5% P C I_ PIRQH#

R 286 1
MISC
2 8.2K_0402_5% P CI_REQ0# AE5 AE9
AD5 RSVD[1] RSVD[6] AG8
R 264 1 RSVD[2] RSVD[7]
2 8.2K_0402_5% P CI_REQ1# AG4 AH8
RSVD[3] RSVD[8]
AH4 F21
R 261 1 RSVD[4] RSVD[9]
2 8.2K_0402_5% P CI_REQ2# AD9 AH20 MC H_ IC H_ S YNC# 7
RSVD[5] MCH_SYNC#
R 282 1 2 8.2K_0402_5% P CI_REQ5#
IC H7 _BGA652~D
Place closely pin A9
C L K _ P CI_ICH
B B

2
R 277

@ 10_0402_5%

1
1
C 364

@ 8.2P_0402_50V
2

A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(1/4)
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS I G L50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 19 of 48
5 4 3 2 1
 5 4 3 2 1

C 195 15P_0402_50V8J IC H_RTCX1

10M_0402_5%
1
Y1

R109
2 1
3 2 .768KHZ_12.5P_1TJS125BJ2A251 NC IN
3 4
NC OUT U3 A

2
L P C _AD[0..3] 32,33,34

RTC
AB1 AA6 L P C_AD0
C 196 15P_0402_50V8J IC H_RTCX2 AB2 RTXC1 LAD0 AB5 L P C_AD1
D RTCX2 LAD1 L P C_AD2 D
AC4
R293 1 IC H_RTCRST# LAD2 L P C_AD3
+ RTCVCC 2 AA3 Y6

LPC
20K_0402_5% RTCRST# LAD3
IC H_ INT V RMEN W4 AC3 L PC_DRQ0#
INTVRMEN LDRQ0# L PC_DRQ#0 32
J1 S M_ I NTRUDER# Y5 AA5 LPC_DRQ#1 34
INTRUDER# LDRQ1# / GPIO23
1 2
3 MM AB3 L P C_FRAME#
+ RTCVCC LFRAME# L P C _FRAME# 3 2,33,34
W1
EE_CS
Y1 2 1 R 250 10K_0402_5% +3VS
C 392 EE_SHCLK G ATEA20
Y2 AE22 GATEA20 33
EE_DOUT A20GATE

LAN
1 U_ 0603_10V4Z W3 AH28 H_ A 20M#
EE_DIN A20M# H_ A20M# 4
1

CPU
1 2
R 288 V3 AG27 H_ C PUSLP_R# 2 @ 1 R 233 0_0402_5%
LAN_CLK CPUSLP# H_ C PUSLP# 4 ,7
1 M_0402_5% U3 AF24 DPRSLP# 2 1 R 243 0_0402_5%
LAN_RSTSYNC TP1 / DPRSTP# H_DPRSTP# 4 ,45
AH25 H _DPSLP#
2

TP2 / DPSLP# H_ DPSLP# 4

S M_ I NTRUDER# U5 2 1 56_0402_5% + VCCP
LAN_RXD0 H_ F ERR# R 234
V4 AG26 H_ F E RR# 4
LAN_RXD1 FERR#
T5
LAN_RXD2 H_ PW RGOOD
AG24 H_ PW RGOOD 4
+ RTCVCC GPIO49 / CPUPWRGD
U7
LAN_TXD0 H_ IGNN E#
V6 AG22 H_ IGNNE # 4
C 389@ V7 LAN_TXD1 IGNNE# AG21
LAN_TXD2 INIT3_3V#
2 1 1 R 310 2 AF22 H_ INI T#
H_ INIT# 4
INIT#
1

@ 10_0402_5% R 311 AF25 H_ IN TR

INTR H_ INT R 4
R 296 10P_0402_25V8K 33_0402_5%

AC-97/AZALIA
1 2 IC H_ A C_BITCLK_R U1 2 1 R 251 10K_0402_5% + VCCP
28 IC H_ B ITCLK_MDC ACZ_BCLK +3VS
332K_0402_1% 1 2 IC H_ AC _ S Y NC_R R6 AG23 KB_RST#
28 IC H_ S YNC _ MDC ACZ_SYNC RCIN# KB_RST# 33
R 281 33_0402_5%
2

1
1 2 IC H_ AC_RST_R# R5 AF23 H_ S MI#
28 IC H_RST_MDC# ACZ_RST# SMI# H_ S MI# 4
IC H_ INT V RMEN R 314 33_0402_5% AH24 H _ NMI R 245
NMI H _ NMI 4
IC H_ AC _ SDIN0 T2
C 29 IC H_ AC _ S DIN0 ACZ_SDIN0 C
IC H_ AC _ SDIN1 T3 AH22 H_STPCLK# 56_0402_5%
28 IC H_ AC _ S DIN1 ACZ_SDIN1 STPCLK# H_STPCLK# 4
T1

2
ACZ_SDIN2 T HR MT RIP_ICH#
AF26 1 R 237 2 H_ T HERMTRIP# 4 ,7
IC H_ A C_SDOUT_R THERMTRIP# 24.9_0402_1%
28 IC H_ S DOUT_MDC 1 2 T4
R 315 33_0402_5% ACZ_SDOUT
AH17 P D_A0
DA0 P D _A0 23
SATA_LED# AF18 AE17 P D_A1
38 SATA_LED# SATALED# DA1 P D _A1 23
AF17 P D_A2
DA2 P D _A2 23
PSATA_IRX_DTX_N0_C AF3 AE16 P D_CS#1
23 PSATA_IRX_DTX_N0_C SATA0RXN DCS1# PD_CS#1 23
PSATA_IRX_DTX_P0_C AE3 AD16 P D_CS#3
23 PSATA_IRX_DTX_P0_C SATA0RXP DCS3# PD_CS#3 23
PSATA_ITX_DRX_N0_C AG2
SATA0TXN

SATA
HGT30 @ 10/11 PSATA_ITX_DRX_P0_C AH2
SATA0TXP AB15 P D_D0
R 702 1K_0402_5% DD0 P D_D1
1 2 AF7 AE14
R 703 1K_0402_5% SATA2RXN DD1 P D_D2
SATA RX n/p need tie to GND when no used 1 2 AE7
SATA2RXP DD2
AG13
P D_D3
AG6 AF13
AH6 SATA2TXN DD3 AD14 P D_D4
SATA2TXP DD4 P D_D5
AC13
C LK_PCIE_SATA# DD5 P D_D6
15 C LK_PCIE_SATA# AF1 AD12
C LK_PCIE_SATA SATA_CLKN DD6 P D_D7
15 C L K_PCIE_SATA AE1 AC12
SATA_CLKP DD7 P D_D8
AE12
R 275 DD8 P D_D9
AH10 AF12
1 2 AG10 SATARBIASN DD9 AB13 P D_D10
+3VS SATARBIASP DD10 P D_D11
AC14
24.9_0402_1% DD11 P D_D12
AF14
DD12 P D_D13
AH13
DD13 P D_D14
IDE AH14
4.7K_0402_5% 2 DD14
1 R 266 P D _ IO RDY
23 P D _ IORDY
P D _ IO RDY AG16 AC15 P D_D15
8.2K_0402_5% 2 IORDY DD15
1 R 265 P D _IRQ
23 P D _IRQ
P D _IRQ AH16
10K_0402_5% 2 1 R 259 SATA_LED# P D _DACK# AF16 IDEIRQ
23 P D_DACK# DDACK#
P D_IOW # AH15 AE15 P D_DREQ
B 23 P D _IOW # DIOW# DDREQ PD_DREQ 23 B
P D _IOR# AF15
23 P D _IOR# DIOR#

IC H7_BGA652~D

P D _D[0..15]
P D _D[0..15] 23
PSATA_ITX_DRX_N0 1 2 PSATA_ITX_DRX_N0_C
23 PSATA_ITX_DRX_N0
C 387 3900P_0402_50V7K

PSATA_ITX_DRX_P0 1 2 PSATA_ITX_DRX_P0_C
23 PSATA_ITX_DRX_P0
C 388 3900P_0402_50V7K

BATT1.1

+ RTCVCC
Close to U7

R 114
+ BATT1 -
1 2 1 2
1 2IC H_ A C_SDOUT_R W=20mils
29 IC H_ S D O UT_AUDIO
R 299 33_0402_5% 2 100_0603_1%
D3
C 203
1 2 + C HGRTC ML1220T13RE
1 2IC H_ AC _ S Y NC_R 0 . 1 U_0402_16V4Z 45@
29 IC H_ S YNC _ AUDIO 1
R 280 33_0402_5%
RB751V_SOD323

29 IC H_ R S T_AUDIO# 1 2 IC H_ AC_RST_R#
A R 313 33_0402_5% A

1 2IC H_ A C_BITCLK_R
29 IC H_ B IT CLK_AUDIO
1 R 312 33_0402_5%

@ C 390
2 2P_0402_50V8J
2 Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(2/4)
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C us tom I G L50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 20 of 48
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

+3VS Place closely pin B2 Place closely pin AC1

C L K _ 48M_ICH C L K _ 14M_ICH
+ 3VALW + 3VALW

1
10K_0402_5%
R 253 1 2 S I RQ R 305 R 308

1
2

2
8.2K_0402_5% R 256 R 247 @ 10_0402_5% @ 10_0402_5%
R 258 1 2 P C I_ C LKRUN# R 239 R 241

2
2.2K_0402_5% 2.2K_0402_5% U 3C
10K_0402_5% 10K_0402_5% 10K_0402_5% 1 1

2
R 254 1 2 G7X_THER_ALERT# 15,28,37 IC H_ SMBCLK
IC H _SMBCLK C22 AF19 <> C 384 C 391

1
D IC H_ SMBDATA SMBCLK GPIO21 / SATA0GP D
1 5,28,37 IC H_ S MBDATA B22 AH18 S B _INT_FLASH_SEL 34
SMBDATA GPIO19 / SATA1GP

SMB
SATA
GPIO
L I NKALERT# A26 AH19 @ 4.7P_0402_50V8C @ 4.7P_0402_50V8C
IC H_ S M LINK0 LINKALERT# GPIO36 / SATA2GP 2 2
B25 AE19 1 R260 2
IC H_ S M LINK1 SMLINK0 GPIO37 / SATA3GP 100_0402_5%
A25
SMLINK1
+ 3VALW + 3VALW
R 232 AC1 C L K _ 14M_ICH
CLK14 C L K _ 14M_ICH 15

Clocks
10K_0402_5% 1 2 IC H_ R I# A28 B2 C L K _ 48M_ICH
RI# CLK48 C L K _ 48M_ICH 15
R 242 1 2 L I NKALERT# 8.2K_0402_5%
SB_SPKR A19
29 SB_SPKR SPKR SLP_S4# 33
150_0402_5% P AD T41 SUS_STAT# A27 C20 IC H_ SUSCLK T44 P AD
R 248 1 ITP_DBRESET# ITP_DBRESET# SUS_STAT# SUSCLK SLP_S4#
2 4 ITP_DBRESET# A22 1 2
SYS_RST#

SYS
B24 SLP_S3# R482 @ 0_0402_5%
SLP_S3# SLP_S3# 33
10K_0402_5% P M_ B MBUSY# AB18 D23 SLP_S4#
R 246 1 7 P M_ BMBUSY# GPIO0 / BM_BUSY# SLP_S4#
2 OCP# F22 SLP_S5# SLP_S5# SLP_S5# 33
OCP# B23 SLP_S5#
4 O CP# GPIO11 / SMBALERT#
10K_0402_5% AA4 IC H _POK R 295
PWROK IC H_POK 7,33

POWER MGT
R 304 1 2 S P I_MISO H _STP_PCI# AC20 1 2 10K_0402_5%
15 H_STP_PCI# GPIO18 / STPPCI#

GPIO
H _STP_CPU# AF21 AC22 1 2 D P RSLPVR
15 H_STP_CPU# GPIO20 / STPCPU# GPIO16 / DPRSLPVR D PRSLPVR 7 ,45
10K_0402_5% R 90 100_0402_5%
R 285 1 2 S PI_CS# ID ERST_CD# A21 C21 IC H_LOW _BAT#
23 IDERST_CD# GPIO26 TP0 / BATLOW#
B21 C23 PBTN_OUT#
GPIO27 PWRBTN# PBTN_OUT# 33
E23
GPIO28 P CI_RST#
C19 PCI_RST# 1 9,24,25,26,27,32,33,34
1K_0402_5% P C I_ C LKRUN# AG18 LAN_RST#
24,26,27,33 P C I_ C LKRUN# GPIO32 / CLKRUN# EC_RSMRST#
R 255 1 2 IC H_ PCIE_W AKE# Y4
RSMRST# EC_RSMRST# 33
AC19 R 297 10K_0402_5%
8.2K_0402_5% GPIO33 / AZ_DOCK_EN#
U2 1 2
GPIO34 / AZ_DOCK_RST#
R 252 2 1 IC H_LOW _BAT#
10K_0402_5% IC H_ PCIE_W AKE# F20 E20 E C _SCI#
2 8,37 IC H_ P CIE_W AKE# WAKE# GPIO9 E C _SCI# 33
R 240 1 2 W L_ON S I RQ AH21 A20
C 2 4,26,32,33,34 S IRQ SERIRQ GPIO10 A C IN 33,39 C
E C_THERM# AF20 F19 D P RSLPVR 2 1
33 E C_THERM# THRM# GPIO12
10K_0402_5% E19 E C _LID_OUT# R 91
GPIO13 E C_LID_OUT# 33
R 292 1 2 S P I_MOSI V GATE AD22 R4 @ 100K_0402_5%
45 VGATE VRMPWRGD GPIO14 E22 C PUSB#
GPIO15 C PUSB# 37
R3 W L_ON
GPIO24 E C _ FLASH#
G7X_THER_ALERT#
AC21
AC18
GPIO6 GPIO GPIO25
D20
AD21 SATAREQ#
E C _FLASH# 34
18 G7X_THER_ALERT# GPIO7 GPIO35 / SATAREQ# SATAREQ# 15
E C _SMI# E21 AD20
33 E C _SMI# GPIO8 GPIO38
AE20 K ILL_MDC# 28
GPIO39
IC H7_BGA652~D Need update symbol

U 3D
P C IE_RXN1 F26 V26 D MI _RXN0
37 P C IE_RXN1 PERn1 DMI0RXN D MI_RXN0 7
P CIE_RXP1 F25 V25 D M I_RXP0
37 PCIE_RXP1 PERp1 DMI0RXP D MI_RXP0 7

DIRECT MEDIA INTERFACE

37 PCIE_TXN1 0 . 1U_0402_16V7K C 323 P CIE_C_TXN1 E28 U28 D M I_TXN0
PETn1 DMI0TXN D MI_TXN0 7
37 PCIE_TXP1 0 . 1U_0402_16V7K C 331 PCIE_C_TXP1 E27 U27 DMI_TXP0
PETp1 DMI0TXP DMI_TXP0 7
P C IE_RXN2 H26 Y26 D MI _RXN1
28 P C IE_RXN2 PERn2 DMI1RXN D MI_RXN1 7
P CIE_RXP2 H25 Y25 D M I_RXP1
28 PCIE_RXP2 PERp2 DMI1RXP D MI_RXP1 7
0 . 1U_0402_16V7K C 328 P CIE_C_TXN2 G28 W28 D M I_TXN1
28 PCIE_TXN2 PETn2 DMI1TXN D MI_TXN1 7
28 PCIE_TXP2 0 . 1U_0402_16V7K C 329 PCIE_C_TXP2 G27 W27 DMI_TXP1
PETp2 DMI1TXP DMI_TXP1 7

PCI-EXPRESS
P C IE_RXN3 K26 AB26 D MI _RXN2
28 P C IE_RXN3 PERn3 DMI2RXN D MI_RXN2 7
P CIE_RXP3 K25 AB25 D M I_RXP2
28 PCIE_RXP3 PERp3 DMI2RXP D MI_RXP2 7
28 PCIE_TXN3 0 . 1U_0402_16V7K C 843 P CIE_C_TXN3 J28 AA28 D M I_TXN2
PETn3 DMI2TXN D MI_TXN2 7
28 PCIE_TXP3 0 . 1U_0402_16V7K C 844 PCIE_C_TXP3 J27 AA27 DMI_TXP2
PETp3 DMI2TXP DMI_TXP2 7
M26 AD25 D MI _RXN3
B PERn4 DMI3RXN D MI_RXN3 7 B
FOR IGL50 M25 AD24 D M I_RXP3
PERp4 DMI3RXP D MI_RXP3 7
L28 AC28 D M I_TXN3
PETn4 DMI3TXN D MI_TXN3 7
L27 AC27 DMI_TXP3
PETp4 DMI3TXP DMI_TXP3 7

P26 AE28 C L K _ PCIE_ICH#

PERn5 DMI_CLKN C L K _ PCIE_ICH# 15
P25 AE27 C L K _ P CIE_ICH
PERp5 DMI_CLKP C L K _ P CIE_ICH 15
N28
PETn5 R 238 24.9_0402_1%
N27 C25 Within 500 mils
PETp5 DMI_ZCOMP D25 D MI_ IRCOMP 1 2
DMI_IRCOMP + 1.5VS
T25 RP15
PERn6 US B20_N0 U SB_OC#4
T24 F1 US B20_N0 31 4 5 + 3VALW
PERp6 USBP0N U SB20_P0 U SB_OC#2
R28 F2 USB20_P0 31 3 6
PETn6 USBP0P US B20_N1 U SB_OC#3
R27 G4 US B20_N1 28 2 7
PETp6 USBP1N U SB20_P1 U SB_OC#1
G3 USB20_P1 28 1 8
USBP1P US B20_N2
R2 H1 US B20_N2 37
S PI_CS# P6 SPI_CLK USBP2N H2 U SB20_P2 10K_1206_8P4R_5%
SPI_CS# SPI USBP2P USB20_P2 37
P1 J4 US B20_N3
SPI_ARB USBP3N US B20_N3 28
J3 U SB20_P3
USBP3P USB20_P3 28
S P I_MOSI P5 K1 US B20_N4 RP16
SPI_MOSI USBP4N US B20_N4 37
S P I_MISO P2 K2 U SB20_P4 U SB_OC#0 4 5
SPI_MISO USBP4P USB20_P4 37 + 3VALW
L4 FOR IGL50 U SB_OC#5 3 6
USBP5N US B20_N5 37
L5 U SB_OC#6 2 7
USBP5P USB20_P5 37
U SB_OC#0 D3 M1 U SB_OC#7 1 8
31 USB_OC#0 OC0# USBP6N US B20_N6 37
U SB_OC#1
U SB_OC#2
C4
D5
OC1# USB USBP6P
M2
N4 US B20_N7
USB20_P6 37
10K_1206_8P4R_5%
37 USB_OC#2 OC2# USBP7N US B20_N7 37
U SB_OC#3 D4 N3 U SB20_P7
OC3# USBP7P USB20_P7 37
U SB_OC#4 E5
37 USB_OC#4 OC4#
U SB_OC#5 C3 R 307 22.6_0402_1%
U SB_OC#6 OC5# / GPIO29 US B RBIAS
37 USB_OC#6 A2 D2 1 2
U SB_OC#7 OC6# / GPIO30 USBRBIAS#
B3 D1
OC7# / GPIO31 USBRBIAS
Within 500 mils
A IC H7_BGA652~D A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(3/4)
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C u s tom I G L50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 21 of 48
5 4 3 2 1
 5 4 3 2 1

+ VCCP
U 3F U3E
A4 P28
IC H_ V5 R E F_RUN 0 . 1 U_0402_16V4Z VSS[0] VSS[98]
G10 L11 A23 R1
V5REF[1] Vcc1_05[1] L12 B1 VSS[1] VSS[99] R11
Vcc1_05[2] VSS[2] VSS[100]
AD17 L14 1 B8 R12
V5REF[2] Vcc1_05[3] VSS[3] VSS[101]
L16 1 1 B11 R13
+1.5VS IC H_ V5 REF_SUS Vcc1_05[4] C 363 C 357 + C 351 VSS[4] VSS[102]
F6 L17 B14 R14
V5REF_Sus Vcc1_05[5] L18 B17 VSS[5] VSS[103] R15
D 0 . 1 U_0402_16V4Z Vcc1_05[6] 2 2 0U_D2_4VM VSS[6] VSS[104] D
AA22 M11 B20 R16
Vcc1_5_B[1] Vcc1_05[7] 2 2 2 VSS[7] VSS[105]
1 AA23 M18 B26 R17
+5VS +3VS Vcc1_5_B[2] Vcc1_05[8] VSS[8] VSS[106]

220U_D2_4VM
1 1 1 AB22 P11 B28 R18
+ C335 C 340 C332 Vcc1_5_B[3] Vcc1_05[9] VSS[9] VSS[107]
AB23 P18 C2 T6
Vcc1_5_B[4] Vcc1_05[10] VSS[10] VSS[108]

C327
AC23 T11 1 U_ 0603_10V4Z C6 T12
1

AC24 Vcc1_5_B[5] Vcc1_05[11] T18 C27 VSS[11] VSS[109] T13

R 278 D 15 2 2 2 2 Vcc1_5_B[6] Vcc1_05[12] VSS[12] VSS[110]
AC25 U11 D10 T14
Vcc1_5_B[7] Vcc1_05[13] VSS[13] VSS[111]
AC26 U18 D13 T15
100_0402_5% C H751H-40_SC76 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z Vcc1_5_B[8] Vcc1_05[14] VSS[14] VSS[112]
AD26 V11 D18 T16
Vcc1_5_B[9] Vcc1_05[15] VSS[15] VSS[113]
AD27 V12 D21 T17
2

Vcc1_5_B[10] Vcc1_05[16] VSS[16] VSS[114]

AD28 V14 D24 U4
IC H_ V5 R E F_RUN Vcc1_5_B[11] Vcc1_05[17] VSS[17] VSS[115]
Place closely pin D26
Vcc1_5_B[12] Vcc1_05[18]
V16 E1
VSS[18] VSS[116]
U12
1 1 D27 V17 E2 U13
C 362 C 361 D28,T28,AD28. Vcc1_5_B[13] Vcc1_05[19] VSS[19] VSS[117]
D28 V18 E4 U14
Vcc1_5_B[14] Vcc1_05[20] VSS[21] VSS[118]
E24 E8 U15
0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z E25 Vcc1_5_B[15] U6 E15 VSS[22] VSS[119] U16
2 2 Vcc1_5_B[16] Vcc3_3 / VccHDA +3VS VSS[23] VSS[120]
E26 1 F3 U17
Vcc1_5_B[17] + VCCP C 356 VSS[24] VSS[121]
F23 R7 +3VALW F4 U24
Vcc1_5_B[18] VccSus3_3/VccSusHDA VSS[25] VSS[122]
F24 F5 U25
Vcc1_5_B[19] C 354 0 . 1 U_0402_16V4Z VSS[26] VSS[123]
G22 AE23 F12 U26
Vcc1_5_B[20] V_CPU_IO[1] 2 VSS[27] VSS[124]
G23 AE26 1 2 F27 V2
Vcc1_5_B[21] V_CPU_IO[2] VSS[28] VSS[125]
H22 AH26 F28 V13
+ 5VALW + 3VALW H23 Vcc1_5_B[22] V_CPU_IO[3] 0 . 1 U_0402_16V4Z G1 VSS[29] VSS[126] V15
Vcc1_5_B[23] VSS[30] VSS[127]
J22 AA7 +3VS 1 2 G2 V24
Vcc1_5_B[24] Vcc3_3[3] VSS[31] VSS[128]
J23 AB12 G5 V27
1

K22 Vcc1_5_B[25] Vcc3_3[4] AB20 C 353 G6 VSS[32] VSS[129] V28

Vcc1_5_B[26] Vcc3_3[5] 1 VSS[33] VSS[130]
R 289 D 16 K23 AC16 C 359 0 . 1 U_0402_16V4Z G9 W6
Vcc1_5_B[27] Vcc3_3[6] VSS[34] VSS[131]
L22 AD13 1 2 G14 W24
10_0402_5% C H751H-40_SC76 Vcc1_5_B[28] Vcc3_3[7] 0 . 1 U_0402_16V4Z VSS[35] VSS[132]
L23 AD18 G18 W25
M22 Vcc1_5_B[29] Vcc3_3[8] AG12 2 C 358 G21 VSS[36] VSS[133] W26
2

IC H_ V5 REF_SUS Vcc1_5_B[30] Vcc3_3[9] 4 . 7 U_0805_10V4Z VSS[37] VSS[134]

M23 AG15 G24 Y3
Vcc1_5_B[31] Vcc3_3[10] VSS[38] VSS[135]
N22 AG19 G25 Y24
C N23 Vcc1_5_B[32] Vcc3_3[11] G26 VSS[39] VSS[136] Y27 C
1 Vcc1_5_B[33] VSS[40] VSS[137]
C 371 P22 A5 +3VS H3 Y28
Vcc1_5_B[34] Vcc3_3[12] VSS[41] VSS[138]

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
P23 B13 H4 AA1
0 . 1 U_0402_16V4Z R22 Vcc1_5_B[35] Vcc3_3[13] B16 H5 VSS[42] VSS[139] AA24
2 Vcc1_5_B[36] Vcc3_3[14] 1 1 1 VSS[43] VSS[140]
R23 B7 H24 AA25
Vcc1_5_B[37] Vcc3_3[15] VSS[44] VSS[141]

C368

C350

C337
R24 C10 H27 AA26
Vcc1_5_B[38] Vcc3_3[16] VSS[45] VSS[142]
R25 D15 H28 AB4
R26 Vcc1_5_B[39] Vcc3_3[17] F9 2 2 2 J1 VSS[46] VSS[143] AB6
+3VS Vcc1_5_B[40] Vcc3_3[18] VSS[47] VSS[144]
T22 G11 J2 AB11
Vcc1_5_B[41] Vcc3_3[19] VSS[48] VSS[145]
T23 G12 J5 AB14
T26 Vcc1_5_B[42] Vcc3_3[20] G16 J24 VSS[49] VSS[146] AB16
Vcc1_5_B[43] Vcc3_3[21] VSS[50] VSS[147]
T27 J25 AB19
Vcc1_5_B[44] VSS[51] VSS[148]
1 T28 W5 + RTCVCC J26 AB21
C352 U22 Vcc1_5_B[45] VccRTC K24 VSS[52] VSS[149] AB24
Vcc1_5_B[46] VSS[53] VSS[150]

0.1U_0402_16V4Z

0.1U_0402_16V4Z
U23 P7 K27 AB27
0 . 1 U_0402_16V4Z Vcc1_5_B[47] VccSus3_3[1] + 3VALW VSS[54] VSS[151]
V22 1 1 1 1 K28 AB28
2 Vcc1_5_B[48] VSS[55] VSS[152]

C369

C370
V23 A24 C 386 C 376 L13 AC2
W22 Vcc1_5_B[49] VccSus3_3[2] C24 L15 VSS[56] VSS[153] AC5
Vcc1_5_B[50] VccSus3_3[3] 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z VSS[57] VSS[154]
W23 D19 L24 AC9
Vcc1_5_B[51] VccSus3_3[4] 2 2 2 2 VSS[58] VSS[155]
Y22 D22 L25 AC11
Vcc1_5_B[52] VccSus3_3[5] VSS[59] VSS[156]
Place closely pin AG28 within 100mlis. Y23 G19 L26 AD1
Vcc1_5_B[53] VccSus3_3[6] VSS[60] VSS[157]
M3 AD3
+1.5VS + 1 .5VS_DMIPLLR + 1.5VS_DMIPLL VSS[61] VSS[158]
B27 K3 M4 AD4
R 229 R 230 Vcc3_3[1] VccSus3_3[7] + 3VALW VSS[62] VSS[159]
K4 1 1 M5 AD7
+ 1.5VS_DMIPLL VccSus3_3[8] C 367 C 377 VSS[63] VSS[160]
1 2 1 2 AG28 K5 M12 AD8
VccDMIPLL VccSus3_3[9] VSS[64] VSS[161]
10U_0805_10V4Z

K6 M13 AD11
0.5_0805_1% 0_0805_5% VccSus3_3[10] 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z VSS[65] VSS[162]
1 1 +1.5VS AB7 L1 M14 AD15
Vcc1_5_A[1] VccSus3_3[11] 2 2 VSS[66] VSS[163]
C330

AC6 L2 M15 AD19

C 338 Vcc1_5_A[2] VccSus3_3[12] VSS[67] VSS[164]
AC7 L3 M16 AD23
0 . 0 1U_0402_25V4Z Vcc1_5_A[3] VccSus3_3[13] VSS[68] VSS[165]
1 AD6 L6 M17 AE2
2 2 C 373 AE6 Vcc1_5_A[4] VccSus3_3[14] L7 M24 VSS[69] VSS[166] AE4
Vcc1_5_A[5] VccSus3_3[15] VSS[70] VSS[167]
AF5 M6 M27 AE8
B 0 . 1 U_0402_16V4Z Vcc1_5_A[6] VccSus3_3[16] VSS[71] VSS[168] B
AF6 M7 M28 AE11
2 Vcc1_5_A[7] VccSus3_3[17] VSS[72] VSS[169]
AG5 N7 N1 AE13
Vcc1_5_A[8] VccSus3_3[18] VSS[73] VSS[170]
AH5 N2 AE18
Vcc1_5_A[9] VSS[74] VSS[171]
AB17 +1.5VS N5 AE21
Vcc1_5_A[19] VSS[75] VSS[172]
+1.5VS Place closely pin AG5. AD2
VccSATAPLL Vcc1_5_A[20]
AC17 N6
VSS[76] VSS[173]
AE24
0.1U_0402_16V4Z

N11 AE25
VSS[77] VSS[174]
+3VS AH11 T7 N12 AF2
Vcc3_3[2] Vcc1_5_A[21] VSS[78] VSS[175]
0.1U_0402_16V4Z

1 F17 N13 AF4

Vcc1_5_A[22] VSS[79] VSS[176]
C375

1 AB10 G17 N14 AF8

+ 1.5VS Vcc1_5_A[10] Vcc1_5_A[23] VSS[80] VSS[177]
AB9 N15 AF11
Vcc1_5_A[11] VSS[81] VSS[178]
C355

1 AC10 AB8 1 2 N16 AF27

2 C 365 Vcc1_5_A[12] Vcc1_5_A[24] VSS[82] VSS[179]
AD10 AC8 N17 AF28
2 Vcc1_5_A[13] Vcc1_5_A[25] C 348 0 . 1 U_0402_16V4Z VSS[83] VSS[180]
AE10 N18 AG1
1 U_ 0603_10V4Z Vcc1_5_A[14] IC H _K7 VSS[84] VSS[181]
AF10 K7 P AD T46 N24 AG3
2 Vcc1_5_A[15] VccSus1_05[1] VSS[85] VSS[182]
AF9 N25 AG7
AG9 Vcc1_5_A[16] C28 IC H_ C28 N26 VSS[86] VSS[183] AG11
Vcc1_5_A[17] VccSus1_05[2] P AD T15 VSS[87] VSS[184]
AH9 G20 IC H_ G20 P AD T43 P3 AG14
Vcc1_5_A[18] VccSus1_05[3] VSS[88] VSS[185]
P4 AG17
VSS[89] VSS[186]
+ 3VALW Place closely pin AG9. E3 A1 +1.5VS P12 AG20
VccSus3_3[19] Vcc1_5_A[26] VSS[90] VSS[187]
1 H6 P13 AG25
C 372 Vcc1_5_A[27] VSS[91] VSS[188]
+1.5VS C1 H7 1 P14 AH1
VccUSBPLL Vcc1_5_A[28] C 360 VSS[92] VSS[189]
1 J6 P15 AH3
0 . 1 U_0402_16V4Z C 366 IC H_ A A2 Vcc1_5_A[29] VSS[93] VSS[190]
T47 P AD AA2 J7 P16 AH7
2 I C H_ Y7 VccSus1_05/VccLAN1_05[1] Vcc1_5_A[30] 0 . 1 U_0402_16V4Z VSS[94] VSS[191]
T45 P AD Y7 P17 AH12
0 . 1 U_0402_16V4Z VccSus1_05/VccLAN1_05[2] 2 VSS[95] VSS[192]
P24 AH23
2 VSS[96] VSS[193]
V5 P27 AH27
VccSus3_3/VccLAN3_3[1] VSS[97] VSS[194]
V1
VccSus3_3/VccLAN3_3[2] IC H7_BGA652~D
+ 3VALW 1 2 W2
R 712 @ 0_0402_5% VccSus3_3/VccLAN3_3[3]
W7
VccSus3_3/VccLAN3_3[4]
+3VS 1 2
R 497 0_0402_5% 1 IC H7 _BGA652~D
C349
A A
0 . 1 U_0402_16V4Z
2

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(4/4)
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C u s tom I G L50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 22 of 48
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

D JP 9 D

1
PSATA_ITX_DRX_P0 GND
20 PSATA_ITX_DRX_P0 2
PSATA_ITX_DRX_N0 A+
20 PSATA_ITX_DRX_N0 3
4 A-
PSATA_IRX_DTX_N0 GND
20 PSATA_IRX_DTX_N0_C 2 1 5
C 230 3900P_0402_50V7K B-
6
B+
7
PSATA_IRX_DTX_P0 GND
20 PSATA_IRX_DTX_P0_C 2 1
C 234 3900P_0402_50V7K
8
9 V33
V33
+3VS 1 2 10
R 151 @ 0_0805_5% V33 +5VS +3VS
11
12 GND
GND

22U_1206_6.3V6M

22U_1206_6.3V6M

1000P_0402_50V7K
13 0 . 1 U_0402_16V4Z @ 0 . 1 U_0402_16V4Z
GND

1000P_0402_50V7K

0.1U_0402_16V4Z
0.1U_0402_16V4Z
+5VS 1 2 14
R 170 0_0805_5% V5
15 1 1 1 1 1 1 1 1 1 1
V5

C266

C257

C258

C252

C246

C245
16
V5 C256 C 271 C 247 C 251
17
GND
18
19 Reserved 24 2 2 2 2 2 2 2 2 2 2
GND 24 1 U_ 0603_10V4Z @ 1 U_ 0603_10V4Z
20 25
V12 25 @ @
21
22 V12 @
V12 Pleace near HD CONN
Pleace near HD CONN
ALLTO_C16630-122A4-L_RV

C
Main SATA +5V Default C

P D _D[0..15]
P D _D[0..15] 20
P D _A[0..2]
P D _A[0..2] 20

J P10
29 INT _CD_L 1 2 INT _ CD_R 29
1 2
29 C D _ AGND 3 4
R 262 3 4
21 IDERST_CD# 1 2@ 0_0402_5% 5 6 P D_D8
R 267 33_0402_5% P D_D7 5 6 P D_D9
7 ,19,28,37 PLT_RST# 1 2 7 8
P D_D6 9 7 8 10 P D_D10
P D_D5 9 10 P D_D11
11 12
B P D_D4 11 12 P D_D12 B
13 14
P D_D3 13 14 P D_D13
15 16
P D_D2 15 16 P D_D14
17 18
P D_D1 17 18 P D_D15
19 20
+3VS P D_D0 19 20 P D_DREQ
21 22 P D_DREQ 20
23 21 22 24 P D _IOR#
23 24 P D _IOR# 20
1

P D_IOW # 25 26
20 P D_IOW # 25 26
P D _ IO RDY 27 28 P D _DACK#
20 P D _ IO RDY 27 28 P D _DACK# 20
R 249 P D _IRQ 29 30
20 P D_IRQ 29 30
10K_0402_5% P D_A1 31 32 P D I AG# 1 2
P D_A0 33
31 32
34 P D_A2 R 244 100K_0402_5% +5VS
2

P D_CS#1 33 34 P D_CS#3 +5VS

20 PD_CS#1 35 36 PD_CS#3 20
O DD_LED# 35 36
38 O DD_LED# 37 38
37 38
39 40
39 40
+5VS 41 42 +5VS
43 41 42 44 2 1
43 44 1 1
45 46 C 347 0 . 1 U_0402_16V4Z
P R I_CSEL 45 46 C 344 C 336
47 48
47 48 1 U_ 0603_10V4Z 1 0 U_0805_10V4Z
49 50
53
54

49 50
2

2 2
53
54

R 231
470_0402_5% O C TEK_CDR-50DY1G
1

A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & CDROM
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C us tom I GL 50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 23 of 48
5 4 3 2 1
 A B C D E

C A R D _ S 1 _ A [0 ..2 5 ] +3 V S
C A R D _ S 1 _ A [0 ..2 5 ] 25 + S 1 _ V CC
+ 3VS
C A R D _ S 1 _ D [ 0 ..1 5 ] C431 C438 C454
C A R D _ S 1 _ D [ 0 ..1 5 ] 25
0 .1 U _0402_16V4Z 0 .1 U _0402_16V4Z 0 . 1 U_ 0 4 0 2 _ 1 6 V 4 Z
P C I _ A D [ 0 . .3 1 ] 1 1 1 1 1 1 1 1 1 1 1
P C I _ A D [ 0 . .3 1 ] 1 9 , 2 6 ,2 7 ,3 2
C400 C456 CB@
Power on RESET# 4 . 7 U_ 0 8 0 5 _ 1 0 V 4 Z C 4 02 C 4 36 C B@ CB@ C B@ C B@ C B@ CB@ CB@
CB@ 0 . 1 U_ 0 4 0 2 _ 1 6 V 4 Z 0 . 1 U _ 0 4 0 2 _ 1 6 V 4 Z 0 . 1 U_ 0 4 0 2 _ 1 6 V 4 Z
2 2 C B@ 2 CB @ 2 + 3VS 2 2 2 2 2 2 2
Reset# Here C455 C 4 45 C 4 04
4 +3 V S 0 . 1 U_ 0 4 0 2 _ 1 6 V 4 Z 0 . 1 U_ 0 4 0 2 _ 1 6 V 4 Z 0 . 1 U_ 0 4 0 2 _ 1 6 V 4 Z C421 4
0 .1 U _0402_16V4Z
25 V P P D0
VCC 25 V P P D1 1 2
25 V CCD0#
C403
25 V CCD1#
0 . 1 U_ 0 4 0 2 _ 1 6 V 4 Z
ENE CB1410 just have one vcc plane internal,
CB@ if want S3 wake-up function(PME#),then at S3

126

138
122
102
74
73

72
71

44
18

90

86
50
30
14

63
CLK
U 28 status must keep all Vcc +3V. That is different
with TI 1410 and O2-Micro 6912, just keep the

VCCD1#
VCCD0#

VPPD1
VPPD0

VCCP0
VCCP1

VCCSK0
VCCSK1

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7

VCCI
VCCI pin +3V, the other vcc can use +3VS.
SUSPEND# >1ms P C I _ A D3 1 3 144 C A R D _ S 1 _ D1 0
P C I _ A D3 0 AD31 CAD31/D10 C A R D _ S 1 _ D9
4 142
P C I _ A D2 9 AD30 CAD30/D9 C A R D _ S 1 _ D1
5 141
P C I _ A D2 8 AD29 CAD29/D1 C A R D _ S 1 _ D8
7 140
P C I _ A D2 7 AD28 CAD28/D8 C A R D _ S 1 _ D0
PCIRST# 8 139
P C I _ A D2 6 AD27 CAD27/D0 C A R D _ S 1_A0
9 129
P C I _ A D2 5 AD26 CAD26/A0 C A R D _ S 1_A1
10 128
P C I _ A D2 4 AD25 CAD25/A1 C A R D _ S 1_A2
11 127
P C I _ A D2 3 AD24 CAD24/A2 C A R D _ S 1_A3
15 124
P C I _ A D2 2 AD23 CAD23/A3 C A R D _ S 1_A4
16 121
P C I _ A D2 1 AD22 CAD22/A4 C A R D _ S 1_A5
17 120
P C I _ A D2 0 AD21 CAD21/A5 C A R D _ S 1_A6 + S 1 _ V CC
19 118
P C I _ A D1 9 AD20 CAD20/A6 C A R D _ S 1_A25
23 116
P C I _ A D1 8 AD19 CAD19/A25 C A R D _ S 1_A7
24 115

1
P C I _ A D1 7 AD18 CAD18/A7 C A R D _ S 1_A24
25 113
3 P C I _ A D1 6 AD17 CAD17/A24 C A R D _ S 1_A17 R883 3
26 98
P C I _ A D1 5 AD16 CAD16/A17 C A R D _ S 1 _ I O W R#
38 96 C A R D _ S 1 _ I O W R# 25
P C I _ A D1 4 AD15 CAD15/IOWR# C A R D _ S 1_A9 4 7K_0402_5%
39 97
Entry S3 P C I _ A D1 3 40
AD14 CAD14/A9
93 C A R D _ S 1 _ I O R D#
C A R D _ S 1 _ I O R D# 25 @

2
P C I _ A D1 2 AD13 CAD13/IORD# C A R D _ S 1_A11
>1ms 41 95
P C I _ A D1 1 AD12 CAD12/A11 C A R D _ S 1 _ OE #
43 92 C A R D _ S 1 _ OE # 25
P C I _ A D1 0 AD11 CAD11/OE# C A R D _ S 1 _ CE 2 #
45 91 C A R D _ S 1 _ CE 2 # 25
P C I _ A D9 AD10 CAD10/CE2# C A R D _ S 1_A10
46 89
P C I _ A D8 AD9 CAD9/A10 C A R D _ S 1 _ D1 5
47 87
P C I _ A D7 AD8 CAD8/D15 C A R D _ S 1 _ D7
49 85
P C I _ A D6 AD7 CAD7/D7 C A R D _ S 1 _ D1 3
SUSPEND# 51
AD6 CAD6/D13
82
P C I _ A D5 52 83 C A R D _ S 1 _ D6
P C I _ A D4 AD5 CAD5/D6 C A R D _ S 1 _ D1 2
53 80
P C I _ A D3 AD4 CAD4/D12 C A R D _ S 1 _ D5
54 81
P C I _ A D2 AD3 CAD3/D5 C A R D _ S 1 _ D1 1
55 77
P C I _ A D1 AD2 CAD2/D11 C A R D _ S 1 _ D4
P C I _ A D0
56
57
AD1 PQFP 144 CAD1/D4
79
76 C A R D _ S 1 _ D3
AD0 CAD0/D3
PCIRST#
P C I_ C BE#3 12
22.2 X 22.2 X 1.60 125 C A R D _ S 1 _ R E G#
1 9 , 2 6 ,2 7 ,3 2 P C I_ C BE#3 C/BE3# CC/BE3#/REG# C A R D _ S 1 _ R E G# 25
P C I_ C BE#2 27 112 C A R D _ S 1_A12
1 9 , 2 6 ,2 7 ,3 2 P C I_ C BE#2 C/BE2# CC/BE2#/A12
SUSPEND# will gate the PCIRST# or P C I_ C BE#1 37 99 C A R D _ S 1_A8
1 9 , 2 6 ,2 7 ,3 2 P C I_ C BE#1 C/BE1# CC/BE1#/A8
P C I_ C BE#0 48 88 C A R D _ S 1 _ CE 1 #
1 9 , 2 6 ,2 7 ,3 2 P C I_ C BE#0 C/BE0# CC/BE0#/CE1# C A R D _ S 1 _ CE 1 # 25
GRST#, so need S3 wake up function,
P C I _ RS T # 20 119 C A R D _ S 1 _ RS T
SUSPEND# must be LOW ahead the PCIRST#1 9 , 2 1 , 2 5 ,2 6 ,2 7 ,3 2 ,3 3 ,3 4 P C I _ RS T # 28 RST# CRST#/RESET 111 C A R D _ S 1_A23
C A R D _ S 1 _ RS T 25
1 9 , 2 6 ,2 7 ,3 2 P C I _ F R A ME # FRAME# CFRAME#/A23
about 1ms. 29 110 C A R D _ S 1_A15
1 9 ,2 6 ,2 7 P C I _ I R D Y # IRDY# CIRDY#/A15
31 109 C A R D _ S 1_A22
1 9 , 2 6 ,2 7 ,3 2 P C I _ T R D Y # TRDY# CTRDY#/A22
32 107 C A R D _ S 1_A21
1 9 ,2 6 ,2 7 P C I _ D E V S E L # DEVSEL# CDEVSEL#/A21
33 105 C A R D _ S 1_A20
2 1 9 ,2 6 ,2 7 P C I _ S T OP # STOP# CSTOP#/A20 2
34 104 C A R D _ S 1_A14
1 9 ,2 6 ,2 7 P C I _ P E R R# PERR# CPERR#/A14
35 133 C A R D _ S 1 _ W A IT #
1 9 ,2 6 ,2 7 P C I _ S E R R# SERR# CSERR#/WAIT# C A R D _ S 1 _ W A IT # 25
36 101 C A R D _ S 1_A13
1 9 ,2 6 ,2 7 P C I _ P A R PAR CPAR/A13
1 2 1 123 C A R D _ S 1 _ I N P A CK #
+3 V S 19 P C I _ R E Q2 # REQ# CREQ#/INPACK# C A R D _ S 1 _ I N P A CK # 25
R 3 1 8 10K_0402_5% 2 106 CA RD_ S 1 _ WE#
19 P C I _ G NT 2 # GNT# CGNT#/WE# C A R D _ S 1 _ W E # 25
C L K _ P C I _ P CM C B@ C L K _ P C I _ P CM 21 108 C A R D _ A 1 6 _ CL K 1 2 C A R D _ S 1_A16
15 C L K _ P C I _ P CM PCLK CCLK/A16 R420 3 3_0402_5% CB@
1

59 135 C A R D _ S 1 _ B V D1
33 C B _ P ME # RI_OUT#/PME# CSTSCHG/BVD1 C A R D _ S 1 _ B V D1 25
R379 1 2 70 136 CA RD_ S 1 _ WP
1 8 , 2 6 , 3 3 ,3 4 ,3 5 ,3 7 ,4 3 ,4 4 S U S P # SUSPEND# CCLKRUN#/WP C A R D _ S 1 _ W P 25
3 3_0402_5% @ D 17 CB@
@ R B 7 5 1 V _ S OD3 2 3 P C I _ A D2 0 1 2 P C I _ P C M _ ID 13 103 C A R D _ S 1_A19
R408 100_0402_5% IDSEL CBLOCK#/A19
2

1 P C I _ P I R QA # 60 132 C A RD_S 1_RDY #

19 P C I _ P I R QA # MFUNC0 CINT#/READY C A R D _ S 1 _ R D Y # 25
Note: MF0 -- MF6 must 61
MFUNC1
C429 64 62 P C M_ S P K #
10P_0402_25V8K @ refer the data sheet for 65
MFUNC2 SPKOUT
134 C A R D _ S 1 _ B V D2
P C M_ S P K # 29
2 2 1 , 2 6 ,3 2 ,3 3 ,3 4 S IRQ MFUNC3 CAUDIO/BVD2 C A R D _ S 1 _ B V D2 25
design. 67
MFUNC4 C A R D _ S 1 _ C D 2#
68 137 C A R D _ S 1 _ C D 2 # 25
MFUNC5 CCD2#/CD2#
RSVD/D14
RSVD/A18

69 75 C A R D _ S 1 _ C D 1#
RSVD/D2
2 1 , 2 6 ,2 7 ,3 3 P C I _ C L K R U N # MFUNC6 CCD1#/CD1# C A R D _ S 1 _ C D 1 # 25
117 C A R D _ S 1_VS2 1 1
CVS2/VS2# C A R D _ S 1 _ V S 2 25
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

66 131 C A R D _ S 1_VS1
1 9 , 2 1 , 2 5 ,2 6 ,2 7 ,3 2 ,3 3 ,3 4 P C I _ RS T # VCC/GRST# CVS1/VS1# C A R D _ S 1 _ V S 1 25
C871 C870 @
@
C B 1 4 1 0 _ L QF P 1 4 4 1000P_0402_50V7K 2 2 1000P_0402_50V7K
6
22
42
58
78
94
114
130

84
100
143

C B@

C A R D _ S 1 _ D2
C A R D _ S 1_A18
1
C A R D _ S 1 _ D1 4 1

Security Classification
2005/10/06
Compal Secret Data
2006/10/06 T itle
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CB ENE1410(One Solt)
PROPRIETARY NOTE AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
S ize D o c u m e n t N u mb e r R ev
C u s to m 0 .1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
IGL50/51 LA-3771
Da te : 星期一, C月 31, 2006 S heet 24 of 48
A B C D E

WWW.AliSaler.Com
 A B C D E

PC MC I A Power Controller
C A R D _ S 1 _ A [0 ..2 5 ]
24 C A R D _ S 1 _ A [0 ..2 5 ]
C A R D _ S 1 _ D [ 0 ..1 5 ]
24 C A R D _ S 1 _ D [ 0 ..1 5 ]
J P 11
+ S 1 _ V CC
1 35
C A R D _ S 1 _ D3 GND GND C A R D _ S 1 _ C D 1#
2 36 C A R D _ S 1 _ C D 1 # 24
C A R D _ S 1 _ D4 D3 CD1# C A R D _ S 1 _ D1 1
1 3 37
U5 C A R D _ S 1 _ D5 D4 D11 C A R D _ S 1 _ D1 2
4 38
C210 C A R D _ S 1 _ D6 D5 D12 C A R D _ S 1 _ D1 3
13 5 39
VCC 0 .1 U _0402_16V4Z C A R D _ S 1 _ D7 D6 D13 C A R D _ S 1 _ D1 4
1 12 6 40 1
VCC 2 CB @ C A R D _ S 1 _ CE 1 # D7 D14 C A R D _ S 1 _ D1 5
9 11 24 C A R D _ S 1 _ CE 1 # 7 41
12V VCC +S 1 _ V P P C A R D _ S 1_A10 CE1# D15 C A R D _ S 1 _ CE 2 #
8 42 C A R D _ S 1 _ CE 2 # 24
C A R D _ S 1 _ OE # A10 CE2# C A R D _ S 1_VS1
24 C A R D _ S 1 _ OE # 9 43 C A R D _ S 1 _ V S 1 24
+5 V S C A R D _ S 1_A11 OE# VS1# C A R D _ S 1 _ I O R D#
10 44 C A R D _ S 1 _ I O R D # 24
+ 5VS C A R D _ S 1_A9 A11 IORD# C A R D _ S 1 _ I O W R#
1 11 45 C A R D _ S 1 _ I O W R # 24
C A R D _ S 1_A8 A9 IOWR# C A R D _ S 1_A17
10 12 46
VPP CB @ C209 C A R D _ S 1_A13 A8 A17 C A R D _ S 1_A18
1 1 13 47
C 1 97 0 . 1 U_ 0 4 0 2 _ 1 6 V 4 Z C A R D _ S 1_A14 A13 A18 C A R D _ S 1_A19
5 14 48
C193 5V 2 CA RD_ S 1 _ WE# A14 A19 C A R D _ S 1_A20
6 24 C A R D _ S 1 _ W E # 15 49
1 0 U _ 1 2 0 6 _ 1 0 V 4 Z 0 . 1 U_ 0 4 0 2 _ 1 6 V 4 Z C B@ 5V C A RD_S 1_RDY # WE# A20 C A R D _ S 1_A21
24 C A R D _ S 1 _ R D Y # 16 50
2 C B@ 2 IREQ# A21
1 V CCD0# 24 + S 1 _ V CC 17 51 + S 1 _ V CC
VCCD0 VCC VCC
2 V CCD1# 24 +S 1 _ V P P 18 52 +S 1 _ V P P
+3 V S VCCD1 C A R D _ S 1_A16 VPP1 VPP2 C A R D _ S 1_A22
15 V P P D0 24 19 53
VPPD0 C A R D _ S 1_A15 A16 A22 C A R D _ S 1_A23
14 V P P D1 24 20 54
+ 3VS VPPD1 C A R D _ S 1_A12 A15 A23 C A R D _ S 1_A24
21 55
C A R D _ S 1_A7 A12 A24 C A R D _ S 1_A25
3 22 56
3.3V C A R D _ S 1_A6 A7 A25 C A R D _ S 1_VS2
1 1 4 8 23 57 C A R D _ S 1 _ V S 2 24
3.3V OC A6 VS2#

SHDN
C198 C A R D _ S 1_A5 24 58 C A R D _ S 1 _ RS T

GND
C194 CB @ A5 RESET C A R D _ S 1 _ RS T 24
C A R D _ S 1_A4 25 59 C A R D _ S 1 _ W A IT #
1 0 U _ 1 2 0 6 _ 1 0 V 4 Z 0 . 1 U_ 0 4 0 2 _ 1 6 V 4 Z A4 WAIT# C A R D _ S 1 _ W A IT # 24
C A R D _ S 1_A3 26 60 C A R D _ S 1 _ I N P A CK #
2 C B@ 2 C P -2 2 1 1 _ S S OP 1 6 A3 INPACK# C A R D _ S 1 _ I N P A CK # 24
C A R D _ S 1_A2 27 61 C A R D _ S 1 _ R E G#

16
C B@ A2 REG# C A R D _ S 1 _ R E G# 24
C A R D _ S 1_A1 28 62 C A R D _ S 1 _ B V D2
C A R D _ S 1_A0 A1 SPKR# C A R D _ S 1 _ B V D1 C A R D _ S 1 _ B V D2 24
29 63 C A R D _ S 1 _ B V D1 24
C A R D _ S 1 _ D0 A0 STSCHG# C A R D _ S 1 _ D8
30 64
P C I _ RS T # C A R D _ S 1 _ D1 D0 D8 C A R D _ S 1 _ D9
P C I _ RS T # 1 9 , 2 1 , 2 4 ,2 6 ,2 7 ,3 2 ,3 3 ,3 4 31 65
C A R D _ S 1 _ D2 D1 D9 C A R D _ S 1 _ D1 0
32 66
CA RD_ S 1 _ WP D2 D10 C A R D _ S 1 _ C D 2#
24 C A R D _ S 1 _ W P 33 67 C A R D _ S 1 _ C D 2 # 24
IOIS16# CD2#
34 68
2 +S 1 _ V P P GND GND 2
69 77
GND GND + S 1 _ V CC
70 78
GND GND
71 79
GND GND
1 1 1 72 80
C241 C 2 15 GND GND
73 81 1 1 1
C 2 43 GND GND
74 82
CB@ C B@ 1 U _0805_25V4Z GND GND C239 C238
75 83
2 2 2 C B@ GND GND 0 . 1 U_ 0 4 0 2 _ 1 6 V 4 Z C216 0 . 0 1 U_ 0 4 0 2 _ 2 5 V 4 Z
76 84
0 . 0 1 U_ 0 4 0 2 _ 2 5 V 4 Z 4 . 7 U_ 0 8 0 5 _ 1 0 V 4 Z GND GND CB@ 2 2 2 C B@
87
HOLE1 1 0 U_ 1 2 0 6 _ 1 0 V 4 Z
88
HOLE2 CB @
89
HOLE3
90
HOLE4

F O X _ W Z 2 1 1 3 1 -G2 -P 4 _ L T
ME@

3 3

4 4

Security Classification
2005/10/06
Compal Secret Data
2006/10/06 T itle
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CardBus Socket
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
S ize D o c u m e n t N u mb e r R ev
C u s to m 0 .1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
IGL50/51 LA-3771
Da te : 星期一, C月 31, 2006 S heet 25 of 48
A B C D E
 5 4 3 2 1

+3VS
SD,MMC,MS,XD muti-function pin define
MDIO SD Card MMC Card MS Card XD Card
U34
19,24,27,32 PCI_AD[0..31]
P CI_AD31 125 10
PIN Name PIN Name PIN Name PIN Name PIN Name
AD31 VCC_PCI3V 1 1
P CI_AD30 126
AD30 VCC_PCI3V
20 MDIO00 SDCD# MMCCD# XDCD0#
P CI_AD29 127 27 C468 C506
AD29 VCC_PCI3V
P CI_AD28 1 32 MDIO01 MSCD# XDCD1#
P CI_AD27
P CI_AD26
2
3
AD28
AD27 R5C832 VCC_PCI3V
VCC_PCI3V
41
128
2 2 +3VS
MDIO02 XDCE#
P CI_AD25 AD26 VCC_PCI3V
5
AD25 0.01U_0402_25V4Z 10U_0805_6.3V6M
P CI_AD24 6
AD24 VCC_RIN
61 MDIO03 SDWP# XDR/B#
P CI_AD23 9
AD23
P CI_AD22 11
AD22 VCC_ROUT
16 MDIO04 SDPWR0 MMCPWR MSWR XDPWR
P CI_AD21 12 34 1 1 1 1
D AD21 VCC_ROUT D

C515
P CI_AD20 14
AD20 VCC_ROUT
64 MDIO05 SDPWR1 XDWP#

C507

C489

C522
P CI_AD19 15 114 1 1 1 1
AD19 VCC_ROUT

0.1U_0402_16V4Z

10U_0805_6.3V6M
0.01U_0402_25V4Z

0.01U_0402_25V4Z

0.47U_0603_16V4Z

0.47U_0603_16V4Z

0.01U_0402_25V4Z

0.01U_0402_25V4Z
C464

C460

C491

C516
P CI_AD18 17
AD18 VCC_ROUT
120
2 2 2 2
MDIO06 SDLED# MMCLED# MSLED# XDLED#
P CI_AD17 18
AD17
P CI_AD16 19
AD16 VCC_3V
67 +3VS 2 2 2 2
MDIO07 MSEXTCK
P CI_AD15 36
AD15
P CI_AD14 37
AD14 VCC_MD3V
86 1 1 MDIO08 SDCCMD MMCCMD MSBS XDWE#
P CI_AD13 38
AD13 C486 C505
P CI_AD12 39
AD12 AVCC_PHY3V
98 + 3 V_PHY MDIO09 SDCCLK MMCCLK MSCCLK XDRE#
P CI_AD11 40 106
AD11 AVCC_PHY3V 2 2
P CI_AD10 42
AD10 AVCC_PHY3V
110 MDIO10 SDCDAT0 MMCDAT MSCDAT0 XDCDAT0
P CI_AD9 43 112
AD9 AVCC_PHY3V
P CI_AD8 44
AD8 MDIO11 SDCDAT1 MSCDAT1 XDCDAT1
P CI_AD7 46 113 IEEE1394_T PBIAS0 0.01U_0402_25V4Z 10U_0805_6.3V6M
AD7 TPBIAS0 + 3V_PHY
P CI_AD6 47
AD6 MDIO12 SDCDAT2 MSCDAT2 XDCDAT2
P CI_AD5 48 109 IEEE1394_TPAP0 L18
AD5 TPAP0
P CI_AD4 49
AD4 TPAN0
108 IEEE1394_T PAN0
+3VS
1 2 MDIO13 SDCDAT3 MSCDAT3 XDCDAT3
P CI_AD3 50
AD3

22U_0805_6.3V6M

0.1U_0402_16V4Z
0.1U_0402_16V4Z

1000P_0402_50V7K

1000P_0402_50V7K
P CI_AD2 51 105 IEEE1394_TPBP0 BLM21A601SPT_0805 MDIO14 XDCDAT4
P CI_AD1 AD2 TPBP0 IEEE1394_T PBN0
52 104
AD1 TPBN0
P CI_AD0 53
AD0 1 1 1 1 1 MDIO15 XDCDAT5
80 SDCD#_XDCD0#
MDIO00 S DCD#_XDCD0# 38

C465

C470

C469

C466

C467
MDIO01
79 MSCD#_XDCD1 MSCD#_XDCD1 38 MDIO16 XDCDAT6
P CI_CBE#3 7 78 XD_CE#
19,24,27,32 P CI_CBE#3 C/BE3# MDIO02 XD_CE# 38 2 2 2 2 2
19,24,27,32 P CI_CBE#2
P CI_CBE#2 21
C/BE2# MDIO03
77 SDWP#_XDRB#
S DWP#_XDRB# 38 MDIO17 XDCDAT7
P CI_CBE#1 35 76 S D PWR0_MSPWR_XDPWR
19,24,27,32 P CI_CBE#1 C/BE1# MDIO04
19,24,27,32 P CI_CBE#0
P CI_CBE#0 45
C/BE0# MDIO05
75 X DWP#
XDWP# 38 MDIO18 XDCLE
74 3IN1_LED#
MDIO06 3 IN1_LED#
MDIO07
73 T P_MSEXTCK MDIO19 XDALE
P C I_PAR 33 88 S DCMD_MSBS
19,24,27 P C I_PAR PAR MDIO08 S DCMD_MSBS 38
P CI_F RAME# 23 84 SDCLK_MSCLK
19,24,27,32 PCI_F RAME# FRAME# MDIO09 SDCLK_MSCLK 38
P C I_T RDY# 25 82 SDDAT A0_MSDATA0
C 19,24,27,32 P CI_T RDY#
P C I_ I RDY# 24
TRDY# MDIO10
81 SDDAT A1_MSDATA1
SDDAT A0_MSDATA0 38 Function set pin define C
19,24,27 P C I_ IRDY# IRDY# MDIO11 SDDAT A1_MSDATA1 38
PCI_ST OP# 29 93 SDDAT A2_MSDATA2 UDIO3 UDIO4 MSEN XDEN Function
19,24,27 PCI_ST OP# STOP# MDIO12 SDDAT A2_MSDATA2 38
PCI_DEVSEL# 26 90 SDDAT A3_MSDATA3
19,24,27 PCI_DEVSEL# DEVSEL# MDIO13 SDDAT A3_MSDATA3 38
P CI_AD22 1 2 C BS_IDSEL 8 91 X DD4 Pull-up Pull-up Pull-up Pull-up Enable
IDSEL MDIO14 XDD4 38
R455 100_0402_5% P C I_PERR# 30 89 X DD5
19,24,27 P C I_PERR#
P C I_SERR# PERR# MDIO15 X DD6
XDD5 38 SD,XD,MS,MMC Card
19,24,27 P C I_SERR# 31
SERR# MDIO16
92 XDD6 38 Layout Note: Place close to R5C832 Layout Note: Place close to R5C832
87 X DD7 XDD7 38 and Shield GND for SDCLK_MSCLK and Shield GND for SD_CLK
MDIO17 X DCLE +3VS
85 XDCLE 38
PCI_REQ0#
MDIO18 XDALE
19 PCI_REQ0# 124 83 XDALE 38
PCI_GNT 0# REQ# MDIO19
19 PCI_GNT 0# 123
GNT# MS EN MS EN R474 10K_0402_5%
58 1 2
MSEN XD EN C481 UD I O3 R468 10K_0402_5%
55 1 2
XDEN R5C832XI UD I O4 R475 10K_0402_5%
15 CLK_PCI_1394 121 1 2 1 2
PCICLK R5C832XI UD I O5 R473 100K_0402_5%
19,21,24,25,27,32,33,34 PCI_RST # 119 94 1 2
PCIRST# XI
CBS_GRST# 71 95 R5C832XO 1 2 C471 16P_0603_50V8J

2
R436 1 GBRST# XO 0.01U_0402_25V4Z
2 10K_0402_5% 117 X2 XD EN R471 1 2 10K_0402_5%
CLKRUN#
70 96
R435 1 @ PME# FIL0
21,24,27,33 P C I_ CLKRUN# 2 0_0402_5% 101 24.576MHz_16P_1BG24576CKIA
R5_PME#
REXT C473
33 R5_PME# 100

1
VREF

10K_0402_5%
115 1 2 R5C832XO Solve MS Duo Adaptor short problem
19 P C I_PIRQG# INTA#

2
19 P C I_ PIRQH# 116 72 S I RQ S IRQ 21,24,32,33,34 2
INTB# UDIO0/SERIRQ#

R441
60 T P_UDIO1 16P_0603_50V8J
UDIO1 P AD T49
56 T P_UDIO2 C461
UDIO2 P AD T48
1 2 69 65 UD I O3
+3VS HWSPND# UDIO3
R464 10K_0402_5% 66 59 UD I O4 0.01U_0402_25V4Z 1

1
TEST UDIO4 UD I O5 R705 1
57 2 0_0402_5%
UDIO5
18,24,33,34,35,37,43,44 S USP# 1 2
R463 0_0402_5% 111 4
@ AGND GND Q33
107 13
AGND GND SDDAT A1_MSDATA1
103 22 1 3 2N7002_SOT23 SD_MSDATA1

S
AGND GND SD_MSDATA1 38
102 28 @
AGND GND
99 54 Layout Note: Shield GND for
B AGND GND + V CC_4IN1 B
62 CBS_CCLK_INTERNAL and CBS_CCLK

G
2
GND R706 1
63 2 0_0402_5%
GND Q35
97 68
NC GND
10U_1206_6.3V6M

0.1U_0402_16V4Z
118 2N7002_SOT23
GND SDDAT A2_MSDATA2 SD_MSDATA2

S
122 1 1 1 3@ SD_MSDATA2 38
GND
C521

C437
1 2
R5C832_T QFP128~D R849 0_0805_5%

G
2
2 2 + V CC_4IN1
1 3

S
+5VS + VCC_4IN1_XD
Layout Note: Place close to R5C832
@ Q705
1 2 2N7002_SOT23

G
2
270P_0402_50V7K

R456 @ 10K_0402_5%
5.1K_0603_1%
1

1 1 2
C453

R850 @ 10K_0402_5%
40mil

1
R421

1
D X DCD# 2
2 +3VS U35 + V CC_4IN1 SDCD#_XDCD0# 2 G
2

G S

3
3 1 S @ Q706

3
CLK_PCI_1394 S D PWR0_MSPWR_XDPWR VIN VOUT @ Q34 2N7002_SOT23
4 5
VIN/CE VOUT

1U_0603_10V4Z

150K_0402_5%
Z3008
2N7002_SOT23

1
0.1U_0402_16V4Z
2 1
GND
1

2
56.2_0603_1%

56.2_0603_1%
4.7P_0402_50V8C10_0402_5%

C517

R483
R444

1 RT 9701CB_SOT25
R439

R440

+3VS
@ C494 2

2
100K_0402_5%
2

2
R462

JP13 D22
2 IEEE1394_T PBN0 1 5 MSCD#_XDCD1 2
A IEEE1394_TPBP0
TPB- GND X DCD# A
2 6 1 XDCD# 38
TPB+ GND
C463

IEEE1394_T PAN0 3 7 SDCD#_XDCD0# 3

TPA- GND
2

IEEE1394_TPAP0 4 8
1 @ CBS_GRST# TPA+ GND DAN202U_SC70
SUYIN_020115F B004S512ZL
0.33U_0603_16V4Z

ME@
2

2
56.2_0603_1%

56.2_0603_1%

1
2 2 Layout Note: Shield GND for Compal Electronics, Inc.
R437

R438

C462

C493 IEEE1394_TPA and TPB

1U_0603_10V4Z C459 T itle
2 0.01U_0402_25V4Z
1394+3 in 1 Card
1

1 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
A ND TRA DE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.1
IEEE1394_T PBIAS0
DE P A RTME NT E XCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS HGT30/31 LA3061
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 星期一 , 七月 31, 2006 Sheet 26 of 48
5 4 3 2 1

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 5 4 3 2 1

+ 3VALW
+ 3 V_LAN
C 385 + 3 V_LAN 1 2
1 U_ 0603_10V4Z +3VS
R 498 0_0402_5% GIGA@ 2SB1188_SC62

3
2 1 1 2
U2 4 R 403

3
R 499 0_0402_5% CTRL12 1 + 1 .2V_LAN
@
CTRL25 1
Q21

2
+ 2 .5V_LAN
8100CL 5.6K_0603_1% Q27
1

2
1 00@ 100@ 2SB1188_SC62 1
1 GIGA@ +
D C 374 C379 D
+
1
2 2 U_A_4VM GIGA@ 0 . 1 U_0402_16V4Z
C433 C 393 2 2
2 2 U_A_4VM 0 . 1 U_0402_16V4Z
2 2
P C I_ AD[0..31]
1 9,24,26,32 P C I_ AD[0..31]

R 400 1 2 3.6K_0402_5% + 3 V_LAN

U2 4 U3 1
P C I _AD0 104 108 L A N_EEDO 4 5 1
P C I _AD1 AD0 EEDO L AN_ EEDI DO GND
103 109 3 6
P C I _AD2 102 AD1 AUX/EEDI 111 L A N_EECLK 2 DI NC 7 C 410 0 . 1 U_0402_16V4Z
P C I _AD3 AD2 EESK L A N_EECS SK NC
98 106 1 8 + 3VALW
P C I _AD4 AD3 EECS CS VCC 2
97
P C I _AD5 96 AD4 117 AT93C46-10SU-2.7_SO8
P C I _AD6 AD5 LED0
95 115
P C I _AD7 AD6 LED1
93 114
P C I _AD8 AD7 LED2
90 113
P C I _AD9 AD8 NC/LED3
89
P C I _AD10 AD9 TXD+/MDI0+
87 1 Y3
P C I _AD11 AD10 TXD+/MDI0+ TXD-/MDI0-
86 2
P C I _AD12 85 AD11 TXD-/MDI0- 5 R XI N+/MDI1+ L AN_X1 L AN_X2
1 2
P C I _AD13 AD12 RXIN+/MDI1+ R XIN -/MDI1-
83 6
P C I _AD14 AD13 RXIN-/MDI1-
82
P C I _AD15 79 AD14 14 NC / M DI2+ 2 5 MHZ_20P_1BG25000CK1A 1
AD15 NC/MDI2+ 1
P C I _AD16 59 15 NC / M DI2- + 2 . 5V_LAN
P C I _AD17 AD16 NC/MDI2- NC / M DI3+ C 442 C 443
58 18
P C I _AD18 AD17 NC/MDI3+ NC / M DI3- 2 2P_0402_50V8J 22P_0402_50V8J
57 19

2
P C I _AD19 55 AD18 NC/MDI3- 2 2 U2 3
P C I _AD20 AD19 L AN_X1 R 734
53 121
P C I _AD21 AD20 X1 L AN_X2 @
50 122 0_0402_5%
C P C I _AD22 49 AD21 X2 TXD+/MDI0+ 12 13 MDO0+ C
AD22 TD4- MX4- MDO0+ 38
P C I _AD23 47 105 R319 1 2 1K_0402_5% TXD-/MDI0- 11 14 MDO0-
PCI I/F

1
AD23 LWAKE +3VS TD4+ MX4+ MDO0- 38
P C I _AD24 43 23 ISOLATE# R317 1 2 15K_0402_5% 2 1 C 398 10 15 MCT0 2 1 R 348 R J 45_PR
AD24 ISOLATE# 0 . 0 1U_0402_25V4Z TCT4 MCT4 R J 45_PR 38
P C I _AD25 42 127 RTSET R403 1 2 2.49K_0603_1% 75_0402_5%
P C I _AD26 AD25 RTSET 5.6K for 8100CL GIGA@ R XI N+/MDI1+ MDO1+
40 72 GIGA@ 9 16 MDO1+ 38
P C I _AD27 AD26 NC/SMBCLK R XIN -/MDI1- TD3- MX3- MDO1-
39 74 2.49K for 8110S(B) 8 17 MDO1- 38
P C I _AD28 AD27 NC/SMBDATA TD3+ MX3+
37 2 1 C 396 7 18 MCT1 2 1 R 325
P C I _AD29 36 AD28 88 0 . 0 1U_0402_25V4Z TCT3 MCT3 75_0402_5%
P C I _AD30 AD29 NC/M66EN GIGA@ 0 . 1 U_0402_16V4Z NC / M DI2+ MDO2+
34 GIGA@ 6 19 MDO2+ 38
P C I _AD31 AD30 + AV DDH TD2- MX2-
33 10 1 1 1 R 418 2 GIGA@ 0_0805_5% + 3 V_LAN NC / M DI2- 5 20 MDO2-
MDO2- 38
AD31 NC/AVDDH 120 C 441 2 1 C 418 4 TD2+ MX2+ 21 2 1 R 320
P C I_CBE#0 AVDDH C 420 0 . 0 1U_0402_25V4Z TCT2 MCT2 GIGA@ 75_0402_5%
1 9,24,26,32 P CI_CBE#0 92
P C I_CBE#1 C/BE#0
1 9,24,26,32 P CI_CBE#1 77 11 2 1 0_0402_5% GIGA@ 0 . 1 U_0402_16V4Z GIGA@ NC / M DI3+ 3 22 MDO3+
MDO3+ 38
P C I_CBE#2 60 C/BE#1 NC/HSDAC+ 123 R 354 GIGA@ 2 2 NC / M DI3- 2 TD1- MX1- 23 MDO3-
1 9,24,26,32 P CI_CBE#2 C/BE#2 NC/HG TD1+ MX1+ MDO3- 38
P C I_CBE#3 44 124 2 1 C 408 1 24 2 1 R 322
1 9,24,26,32 P CI_CBE#3 C/BE#3 NC/LG2 0 . 0 1U_0402_25V4Z TCT1 MCT1
126 D VD D_A 1 2 + 1 .2V_LAN GIGA@ 75_0402_5%
P C I _AD17 L AN_ IDSEL46 VDD12A GIGA@
1 2 1
R 302 100_0402_5% IDSEL R 301 GIGA@ 0.5u_24HST1041A-2
76 GIGA@ 0_0402_5% use 24ST1041A-4
LAN I/F

1 9,24,26 P C I_PAR PAR

1 9,24,26,32 P C I_FRAME# 61 9
FRAME# NC/VSS 2
1 9,24,26 P C I_ IR DY# 63 13
IRDY# NC/VSS C 378
1 9,24,26,32 P C I_ TRDY# 67
TRDY#
use 24ST1041A-4
68 GIGA@ 0 . 1 U_0402_16V4Z U2 2
1 9,24,26 P CI_DEVSEL# DEVSEL#
1 9,24,26 PCI_STOP# 69 22
STOP# NC/GND TXD+/MDI0+ MDO0+
48 8 9
NC/GND TXD-/MDI0- TD- TX- MDO0-
1 9,24,26 P C I_PERR# 70 62 7 10
PERR# NC/GND TD+ TX+ MCT0
1 9,24,26 P C I_SERR# 75 73 6 11
SERR# NC/GND CT CT
112
NC/GND
19 P CI_REQ3#
30 118
REQ# NC/GND 0 . 1 U_0402_16V4Z MCT1
29 1 2 3 14
19 P C I_GNT3# GNT# C 401 R XI N+/MDI1+ CT CT MDO1+
2 15
1 00@ R XIN -/MDI1- RD- RX- MDO1- R 324
19 P C I_PIRQF# 25 1 16
B INTA# CTRL25 RD+ RX+ @ 49.9_0402_1% B
8
CTRL25 NC / M DI3+ 2 C 412
33 L AN_PME# 31 1
PME# CTRL12 NS0013_16P
125 2 1
CTRL12 100@ NC / M DI3-
9,21,24,25,26,32,33,34 P CI_RST# 27 2 1
RST# R 321 0 . 0 1U_0402_25V4Z
26 + 3 V_LAN
C L K _ PCI_LAN 28 VDD33 41 @ 49.9_0402_1% @
15 C L K _PCI_LAN CLK VDD33 1 1 1 1 1
2 1,24,26,33 P C I_ C LKRUN# 65 56
CLKRUN# VDD33 C 394 C 381 C 406 C 440 C 423 R 333
71
VDD33 84 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z @ 49.9_0402_1%
VDD33 2 2 2 2 2 NC / M DI2+ 2 C 415
94 1
VDD33
107 2 1
VDD33 NC / M DI2-
4 2 1
GND/VSS R 329 0 . 0 1U_0402_25V4Z
17
GND/VSS @ 49.9_0402_1% @
128
GND/VSS AVD DL R 422 1
3 2 + 3 V_LAN
AVDDL 7 1 00@ 0_0805_5% R 380
AVDDL 1 1 1
21 20 1 00@ 49.9_0402_1%
GND/VSSPST AVDDL C 409 C 425 C 428 GIGA@ 0_0805_5% TXD+/MDI0+ 2 C 430
38 16 1
GND/VSSPST AVDDL 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z + DVDD R 376 1
51 2 + 2 . 5V_LAN 2 1
GND/VSSPST 2 2 2 TXD-/MDI0-
66 2 1
C L K _ PCI_LAN GND/VSSPST + D VDD R 303 1 R 375 0 . 0 1U_0402_25V4Z
81 32 2 + 1 . 2V_LAN
GND/VSSPST VDD12 GIGA@ 0_0805_5% 100@ 49.9_0402_1% 100@
91 54 1 1 1 1
GND/VSSPST VDD12
1

101 78
GND/VSSPST VDD12 C 405 C 427 C 395 C 382 0_0805_5%
119 99
R 316 GND/VSSPST VDD12 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z R 306 R 369
1 2 + 2 . 5V_LAN
@ 10_0402_5% 2 2 2 2 1 00@ 100@ 49.9_0402_1%
35 24 + 1 .2V_LAN R XI N+/MDI1+ 2 1 C 424
2

GND NC/VDD12
Power

1 52 45 2 2 2 2 2 2 1
GND NC/VDD12 GIGA@ C 380 C 383 GIGA@ C 439 C 444 C 407 R XIN -/MDI1-
80 64 2 1
C 397 GND NC/VDD12 GIGA@ R 365 0 . 0 1U_0402_25V4Z
100 110
@ 10P_0402_25V8K GND NC/VDD12 GIGA@ 0 . 1 U_0402_16V4Z GIGA@ 0 . 1 U_0402_16V4Z 1 00@ 49.9_0402_1% 100@
116
2 NC/VDD12 1 1 1 1 1
A 0 . 1 U_0402_16V4Z 0 . 1 U_0402_16V4Z A
12 V _12P R 350 1 2 0 . 1 U_0402_16V4Z
NC
1 100@ 0_0402_5%
+ 2 .5V_LAN
near LAN controller
RTL8110SCL_LQFP128 C 414 R 351 1 2 + AV DDH
GIGA@ GIGA@ 0_0402_5%
0 . 1 U_0402_16V4Z
2

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN CONTROLLER
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C us tom I GL 50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 27 of 48
5 4 3 2 1
 A B C D E

Mini-Express Card(Slot 1-WLAN) Mini-Express Card(Slot 2-WLAN)

2 1,37 IC H_ PCIE_W AKE# 2 1,37 IC H_ P CIE_W AKE#
JP16 J P810
1 2 +3VS 1 2 +3VS
B T_AVTIVE R 480 2 @ 1 2 B T_AVTIVE 1 2
1 0_0402_5% 3 4 R851 2 @ 1 0_0402_5% 3 4
1 W L AN _AVTIVE R 479 2 3 4 3 4 1
1 0_0402_5% 5 6 +1.5VS W L AN _AVTIVE R852 2 1 0_0402_5% 5 6 +1.5VS
5 6 5 6

0.1U_0402_16V4Z

0.1U_0402_16V4Z
@ 7 8 @ 7 8
15 C L K REQ_MCARD# 7 8 15 C L KREQ_MCARD1# 7 8

0.1U_0402_16V4Z

0.1U_0402_16V4Z
9 10 1 9 10 1
9 10 9 10

C498

C845
C L K _ PCIE_MCARD# 11 12 1 C L K _PCIE_MCARD1# 11 12 1
15 C L K _PCIE_MCARD# 11 12 15 C L K _ PCIE_MCARD1# 11 12

C499

C846
C L K _ PCIE_MCARD 13 14 C L K _ PCIE_MCARD1 13 14
15 C L K _PCIE_MCARD 13 14 15 C L K _ PCIE_MCARD1 13 14
15 16 15 16
15 16 2 15 16 2
17 18 17 18
17 18 2 17 18 2
19 20 W L_OFF# 33 19 20 W L_OFF# 33
19 20 PLT_RST# 19 20 PLT_RST#
21 22 PLT_RST# 7 ,19,23,37 21 22 PLT_RST# 7 ,19,23,37
21 22 21 22
21 P C IE_RXN2 23 24 2 1 +3VALW 21 P C IE_RXN3 23 24 2 1 + 3VALW
23 24 R 729 2 23 24
21 PCIE_RXP2 25 26 1 0_0402_5% +3VS 21 P CIE_RXP3 25 26 R 853 2 1 0_0402_5% +3VS
25 26 R 730 @ 0_0402_5% 25 26 R 854 @ 0_0402_5%
27 28 27 28
29 27 28 30 IC H _SMBCLK 29 27 28 30 IC H _SMBCLK
29 30 IC H_SMBCLK 1 5,21,37 29 30 IC H_ SMBCLK 1 5,21,37
31 32 IC H_ SMBDATA IC H_ SMBDATA 1 5,21,37 31 32 IC H_ SMBDATA IC H_ SMBDATA 1 5,21,37
21 P CIE_TXN2 31 32 21 P CIE_TXN3 31 32
21 PCIE_TXP2 33 34 21 PCIE_TXP3 33 34
35 33 34 36 35 33 34 36
35 36 35 36 US B 20_N3 21
37 38 37 38 USB20_P3 21
37 38 37 38
39 40 39 40
39 40 39 40
41 42 41 42
41 42 W IRELESS_LED# 41 42 W IRELESS_LED#
43 44 W IRELESS_LED# 38 43 44 W IRELESS_LED# 38
43 44 43 44
45 46 45 46
45 46 45 46
47 48 47 48
49 47 48 50 49 47 48 50
49 50 49 50
51 52 51 52
51 52 51 52
53 54 53 54
GND1 GND2 GND1 GND2

FOX_AS0B226-S56N-7F FOX_AS0B226-S56N-7F

2 + 3VALW 2

MDC CONN. C 495

1
1 2
R 495 J P17
10K_0402_1%
1 U_ 0 805_25V4Z
@ 1 2

2
1 2
20 IC H_ S DOUT_MDC 3 4
3 4
33_0402_5% A Z_ S YNC
5
5 6
6 +3VALW 11/20
20 IC H_ S YNC _ MDC 7 8
AZ_ S D I N3 7 8
20 IC H_ AC _ S DIN1 1 2 9 10
R 107 9 10
20 IC H_RST_MDC# 2 1 11 12
IC H_ BITCLK_MDC 20
R 496 0_0402_5% 11 12
D 23
2
1

13
14
15
16
17
18
19
20
3 ACES_88012-1207
21 K ILL_MDC#
ME@

13
14
15
16
17
18
19
20
@ DAP202U_SOT323

+5VS
1

3 3
R 108
10K_0402_1%
1 2

BT_OFF

33 BT_OFF# 2 Q9 BT MODULE CONN

DTC124EK_SC59
0.1U_0402_16V4Z

+3VS Q22 +3VS_BT

C 164
3

3 1 2 1
AO3413_SOT23
0 . 1 U_0402_16V4Z
G
2

BTONLED
38 BTONLED
1 J P 38
1

C701

1
1
2
US B20_N1 2
21 US B20_N1 3
2 U SB20_P1 3
21 USB20_P1 4
Q23 BTON_LED 4
2 5
DTC124EK_SC59 B T_AVTIVE 5
6
W L AN _AVTIVE 6
7
7
1

8
8
9
3

R 309 GND1
10
10K_0402_5% GND2
@ MOLEX_53780-0870
2

4 4
ME@

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini Card / MDC CONN
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C us tom I GL 50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 28 of 48
A B C D E

WWW.AliSaler.Com
 A B C D E

+ VDDA

AC97 Codec

1
28.7K for Module Design (VDDA = 4.702)
R 153
10K_0402_1% +5VS +5VAMP
U3 3 (output = 250 mA)
60mil 40mil

2
2 1C255 L22 1 2 4 5 + VDDA
KC FBM-L11-201209-221LMAT_0805 VIN VOUT

2
C 263 1 U_ 0603_10V4Z + VDDA L21
R 168 1 2 2
DELAY SENSE or ADJ
6 1 4.85V
33 BEEP# 2 1 1 2 C 714 1 KC FBM-L11-201209-221LMAT_0805 1
1 R 159 1 2 470P_0402_50V8J C 490 C 482 7 1 R 449 C478
C 477 560_0402_5% 10K_0402_1% ERROR CNOISE 150K_0603_1% 1 0 U_0805_10V4Z

1
1 U_ 0603_10V4Z C487 1 U_ 0603_10V4Z 1 0 U_0805_10V4Z 1 0 U_1206_10V4Z 8 3 2
1

1
2 2 SD GND
@ 0 . 1 U_0402_16V4Z 1 2MO NO _IN1 2 1 MO NO _IN C 476
1 2 R158 20K_0402_5% R 885 S I9182DH-AD_MSOP8 1

1
1 2 10K_0402_1%
R 167 20K_0402_5% 2
C 253

2
1
R 160 C C 712 680P_0402_50V7K L IN E_OUTL R 450
24 PCM_SPK# 2 1 1 2 2 Q12 0 . 1 U_0402_16V4Z 51K_0603_1%
1 B 2SC2411K_SC59 C 713 680P_0402_50V7K L IN E_OUTR

2
1
C 472 560_0402_5% E

3
1 U_ 0603_10V4Z
@ 0 . 1 U_0402_16V4Z R 884
2 10K_0402_1%
C 254

1
D
R 161

2
21 SB_SPKR 2 1 1 2 E APD 2 Q707
G 2N7002_SOT23
1

1
560_0402_5% D4 S Codec For sub woofer

3
1 U_ 0603_10V4Z R 171
@ 10K_0402_5% RB751V_SOD323
ADD C706
2

ALC262
DEL C873,C874
Window mode ADD C873,C874
Driver initial ALC861D
DOS mode DEL C706
ACPI PC Beep for DOS mode
RST + VDDC
R176
2 C HB1608U301_0603 2
+ AVDD_AC97
1 2 +3VS

1 1 1
L 11 C 496 C 503 C 497
C HB1608U301_0603
1 2 0 . 1 U_0402_16V4Z 1 0 U_0805_10V4Z
+ VDDA 2 2 2
1 1 1
C 282 0 . 1 U_0402_16V4Z 2 5 0_LINE_OUTL 1 2
C 277 C280 @ 1000P_0402_50V7K
EC_MUTE 12sec 1 0 U_0805_10V4Z C 264 0 . 1 U_0402_16V4Z 2 5 0_LINE_OUTR 1 2

25

38

9
2 2 2 U1 1 C281 @ 1000P_0402_50V7K
0 . 1 U_0402_16V4Z

AVDD1

AVDD2

DVDD1

DVDD2
1 2 14 35 2 5 0_LINE_OUTL C 509 L IN E_OUTL
30 HP_L LINE2_L LINE_OUT_L L INE_OUTL 30
C 876 1 U_ 0603_10V4Z 1000P_0603_50V7K
1 2 15 36 2 5 0_LINE_OUTR L IN E_OUTR
30 HP _R LINE2_R LINE_OUT_R L INE_OUTR 30
C 875 1 U_ 0603_10V4Z C 508 1000P_0603_50V7K
DOS mode DOS mode 2 1 16
MIC2_L MONO_O
37 1 2 LFE_OUT 31
1 U_ 0603_10V4Z C 704 C 706 1 U_ 0603_10V4Z
3 0,38 INT _ MIC
2 1 17 39
1 U_ 0603_10V4Z C 705 MIC2_R HP_OUT_L
23 41
LINE1_L HP_OUT_R C 267 1 2 2 2P_0402_50V8J
RST 24
LINE1_R
R 174 22_0402_5% @
R 157 2 1 20K_0402_5% C D _R_L 6 1 2 IC H_ B IT CLK_AUDIO
23 INT _CD_L BIT_CLK IC H_ B ITCLK_AUDIO 20
R 156 2 1 20K_0402_5% C 261 1 2 1 U_ 0 402_6.3V4Z C D _RC_L 18
R 155 2 1 20K_0402_5% CD_L 8 2 5 0 _SDIN R 173 1 2 33_0402_5%IC H_ AC _ SDIN0
SDATA_IN IC H_ AC _ SDIN0 20
R 154 2 1 20K_0402_5% C D _R_R C 260 1 2 1 U_ 0 402_6.3V4Z C D _ RC_R 20
3 23 INT _ CD_R CD_R 3
2
C D _ G NA C 479 1 1 U_ 0603_10V4Z C D _ G NDA GPIO2
2 19
CD_GND
M IC 1 2 C _ M IC 21
30 M IC MIC1_L
C 480 1 U_ 0603_10V4Z
1 2 22 3
C 703 1 U_ 0603_10V4Z MIC1_R GPIO3
R 856 1 2 20K_0402_1% 13 29
EC_MUTE 12sec
37 J AC K _ PLUG_MIC SENSE A LINE1_VREFO
MO NO _IN 12 30
PC_BEEP MIC2_VREFO + MIC2_VREFO
E APD R 458 1 2 0_0402_5% 28
10mil
MIC1_VREFO_L + MIC1_VREFO_L
R 459 1 2 0_0402_5%
20 IC H_ R ST_AUDIO# 11
RESET#
27
10mil
VREF
20 IC H_ S YNC _ AUDIO 10
SYNC 32
10mil 2
MIC1_VREFO_R + AUD _VREF
C D _ A GND R 447 2 1 C D _ G NA 5 C 847
23 C D _ AGND 20 IC H_ S D O UT_AUDIO SDATA_OUT
10K_0402_5% 1 0 U_0805_10V4Z
45 31 R 889 @ 10K_0402_5% 1
NC LINE2_VREFO
1

L 701 46 33 1 2 + VDDA
R 448 @ C HB1608U301_0603 NC DCVOL 39.2K_0402_1% 2
34 1 R 877 J AC K_PLUG 37
SENSE B
10K_0402_5% 利 用 R ST PIN來 替 代 EAPD 30,31,33 E APD 1 2 47
SPDIFI/EAPD GPIO0
GPIO1
43
44
C 873 1 2 861@ 1 U_ 0603_10V4Z
L FE_OUT 31
R 887 1 2 1 2 48 C 874 1 2 861@ 1 U_ 0603_10V4Z
2

37 S P D IF SPDIFO
2

10_0402_5% L809
C HB1608U301_0603 40
R 888 LFILT
1 4 26
DVSS1 AVSS1

2
1K_0402_5%7 42
C877 DVSS2 AVSS2 R 859
1 2
R152 0_0603_5% @ 100P_0402_50V8J AL C262-GR_LQFP48-N 20K_0402_1%
1

1
1 2 + MIC2_VREFO + MIC1_VREFO_L
4 R451 0_0603_5% 4

1 2
10mil 10mil
1 1 1 1
R187 0_0603_5% @ @
@ C 850 C 851 @ C852 C 853
1 U_ 0603_10V4Z 0 . 1 U_0402_16V4Z
1 U_ 0603_10V4Z 0 . 1 U_0402_16V4Z
2 2 2G ND A 2
G ND A Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
GND GNDA Issued Date 2005/10/06 Deciphered Date 2006/10/06

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ALC262 Codec
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C us tom I GL 50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 29 of 48
A B C D E
 A B C D E

+ 5VAMP

+ 5VAMP
W=40mil

2
R 704 +3VS
10K_0402_5% 1 1
C 504 C 502 1 2

1 1

2
0 . 1 U_0402_16V4Z 4 . 7 U_0805_10V4Z C 715 0 . 1 U_0402_16V4Z
(0.65V -> 10dB) 2 2
@ R 183
R 708 10K_0402_5% J P20
1 1.5K_0402_1% U3 6 SPKL+O 1
MU TE_AMP SPKL-O 1
10 1

1
15 VDD MUTE 2 M UTE# SPKR+O 2 5

2
VDD SHUTDOWN# SPKR-O 3 6
SPKL- L23 4
9 1 2 0_0603_5% SPKL-O
V OL_AMP 7 LOUT- ACES_85204-0400
VOLUME 1 1 1 1
16 SPKR- L24 1 2 0_0603_5% SPKR-O C 163 C162 C 168 C167 ME@
V OLMAX ROUT-
2 1 8
R 454 0_0402_5% VOLMAX SPKL+ L20
11 1 2 0_0603_5% SPKL+O @ 47P_0402_50V8J @47P_0402_50V8J @ 47P_0402_50V8J
LOUT+ 2 2 2 2
2 1 13
R 467 100K_0402_5% SE/BTL# SPKR+ L8
14 1 2 0_0603_5% SPKR+O @ 4 7P_0402_50V8J
L IN E_OUTL R 165 1 ROUT+
29 L INE_OUTL
2 10K_0402_5% L IN 6
3 LIN-
L IN E_OUTR R 162 1 RIN-
2 10K_0402_5% R IN 5
29 L INE_OUTR GND
4 12
BYPASS GND
1
APA2068KAI-TRL_SOP16
C 488
4 . 7 U_0805_10V4Z
2

+3VS

2
R 735 + MIC1_VREFO_L + MIC2_VREFO
10K_0402_5%
@

1
2 2
MU TE_AMP

2
Q13

2
D 20 R 716

2
E APD 2 10K_0402_5% R 445
29,31,33 E APD
1 M UTE# 2 4.7K_0402_5% R 446 MIC IN
3 4.7K_0402_5%

1
33 E C_MUTE# R 720
L 19

1
@ DAP202U_SOT323 @ DTC124EK_SC59 1 2 1 2 EXT_MIC
29 MIC EXT_MIC 37

1
FBM-11-160808-601-T_0603
3 1K_0402_5%
2 1
R 485 0_0402_5% INT _ MIC
INT _ MIC 29,38

1
1
C 474
4 7P_0402_50V8J C 475
2 47P_0402_50V8J
2

+3VS

3 3
1

R 863 Reserve the 0 ohm resistor.

0_0603_5%
for voltage filtering
1 2 G ND A
2

C 854 1 U_ 0603_10V4Z
1

R 864 HEADPHONE
100K_0402_5% @
19

10

U8 02
R 865 @ 0_0402_5% R179 0_0402_5%
PVDD

SVDD
2

M UTE# 1 2 14 11 HP _OUTR 1 2 H P_CR+ 1 2 PR

SHDNR# OUTR PR 37
L9 FBM-11-160808-601-T_0603
R 891 0_0402_5% 18 9 H P_OUTL 1 2 H P_CL+ 1 2 PL
SHDNL# OUTL PL 37
1 2 L10 FBM-11-160808-601-T_0603
2 9,31,33 E APD
R181 0_0402_5%
1

4 R 180
1

NC-4 R 178
29 HP _R 15 1 1
INR C 279 C 278
6
NC-6 1K_0402_5% 4 7P_0402_50V8J 47P_0402_50V8J
29 HP _L 13
INL 1K_0402_5%
8
2

NC-8 2 2
2

12
NC-12
1 16
C1P NC-16
1
PGND

SGND

3 20
PVss

SVss

C 857 C1N NC-20

4 1 U_ 0603_10V4Z 4
2 MAX4411ETP-T_TQFN20
5

17

1
G ND A
C 858

2G ND A
1 U_ 0603_10V4Z Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMP & Audio Jack
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C us tom I GL 50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 30 of 48
A B C D E

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SUBWOOFER (Reserved for C38)
WOOFER@
+ AUD _VREF_LF + AVDD_AC97

C 514 1 U_ 0603_10V4Z C 285 1 U_ 0603_10V4Z

1 2 + AUD _VREF_LF 1 2

C 518 1 2 0 . 1 U_0603_50V4Z
1 2 U3 7 A

8
C 512 TLV2462CDR_SO8 + AVDD_AC97

8
0 . 1 U_0402_16V4Z 3 R 184 R 182

P
+ 1 2 1 2 1 5 C 523

P
L FE_OUT R 478 1 O +
29 L FE_OUT 2 1 2 C 519 2 7 2 1 M IX_OUT
-

G
560_0402_5% 560_0402_5% O
6
10mil

G
100K_0402_5% 1 U_ 0603_10V4Z - U3 7B 0 .22U_0603_10V7K

4
2 TLV2462CDR_SO8

4
R 477 C 513
2 1 43K_0402_5%
0 . 1 U_0603_50V4Z
C 708 1 2 1 00P_0402_50V8J 1

+ AVDD_AC97 Gain = 3.1dB Fc(LPF)= 1.5KHz

20mil

1
R 722
100K_0402_5% Fc(HPF)= 36.2Hz
+ 5VAMP
Gain = 15.9dB SubWoofer Conn.
2

+ AUD_VREF_LF
+3VS
2
30mil
1

C 709
R 723 R 185 U1 2 J P44

1
100K_0402_5% M IX_OUT 2 1 W O O FER_IN 1 8 W OOFER- L13 1 2 FBMA-L11-160808-700LMT_0603 1
1 U_ 0603_10V4Z 1 20K_0402_5% IN VO- L12 1
1 2 FBMA-L11-160808-700LMT_0603 2
R 878 2
2 7
2

D 811 10K_0402_1% SD# GND

3
2 3 6 4 GND
2 9,30,33 E APD

2
VDD SE/BTL# GND
1
3 2 2 4 5 W OOFER+ MOLEX_53780-0270
33 E C_GPIO09 BYPASS VO+
C 710 C 284 ME@

1
DAP202U_SOT323 2 TPA0211DGN_MSOP8
R 724
1 1 C 283 100K_0402_5%
1 2

1U_0603_10V4Z

0.1U_0402_16V4Z
R 736 0_0402_5%
@ 1 0 . 4 7U_0603_16V4Z

2
USB Port
+ US B_VCCA

+5VALW
1
1 1
C 174 + C 161 C 160
+ USB_VCCA 1 5 0 U_D_6.3VM
U2 5 1000P_0402_50V7K
1 8 2 2 2 J P21
C 411 0 . 1 U_0402_16V4Z GND OUT
2 7 8
IN OUT 0 . 1 U_0402_16V4Z GND
2 1 3 6 7
IN OUT GND
4 5 6
EN# FLG USB_OC#0 21 GND
5
G528_SO8 4 GND
4
33,37 US B_ON# 21 US B 20_N0 3
3
1 21 USB20_P0 2
C 417 2
1 1 1

2
@ 1000P_0402_50V7K 1
D 14 C 321 C 322
2 @ PSOT24C_SOT23 @10P_0402_25V8K @ 10P_0402_25V8K S UYIN_ 0 20173MR004S558ZL
2 2

1
For EMI

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Bluetooth & USB CONN.
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C us tom I GL 50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 二 , 八 月 01, 2006 Sheet 31 of 48
 5 4 3 2 1

+ 5VALW

1 2
+5VS R 893 100_0603_5% IR 1 R 886
1 2 3 4 2 1 R C I RRX R C IRRX 33
R 868 100_0603_5% Vs OUT
1 1 2
@ C 859 GND GND
1 33_0402_5%
TSOP36236TR_4P
4 . 7 U_0805_10V4Z C 872
2
22P_0402_50V8J
2
D D

CIR

INT_KBD CONN.( TYPE "D" KB)

@
C P1
K S I[0..7] K SI1 1 8
K S I[0..7] 3 3,38
K SI7 2 7
K SI6 3 6
KSO[0..16] KSO9 4 5
K SO[0..16] 3 3,38
100P_1206_8P4C_50V8 +3VALW
C P2 @ Power BTN
K SI4 1 8

1
K SI5 2 7
KSO0 3 6 R 118
K SI2 4 5 100K_0402_5%
JP26
K SI1 24 100P_1206_8P4C_50V8

2
K SI7 24 @
23 C P3
K SI6 23 K SI3 1
22 8
KSO9 21 22 KSO5 2 D2
7
K SI4 21 KSO1 3 O N/ OFF
20 6 2 O N/ OFF# 33
K SI5 20 K SI0 4 O N /OFFBTN#
19 5 1
C KSO0 19 38 O N/ OFFBTN# 5 1ON# C
18 3 5 1 ON# 3 8,39
K SI2 18 100P_1206_8P4C_50V8 SW1
17
K SI3 17 C P4 @ +3VALW D AN202U_SC70
16 1 3
KSO5 15 16 KSO2 1 Q10
8
KSO1 15 KSO4 2
14 7 2 4
14

1
K SI0 13 KSO7 3 6 DTC124EK_SC59 1
13

1
KSO2 12 KSO8 4 5 R 113 D1

6
5
KSO4 11 12 4.7K _0402_5% R L Z20A_LL34
KSO7 11 100P_1206_8P4C_50V8 SMT1-05_4P
10 @
KSO8 10 @ 2 C 205
9 C P6

2
KSO6 8 9 KSO6 1 8 E C _ON 2 1000P_0402_50V7K
8 33 E C _ON
KSO3 7 26 KSO3 2 7
KSO12 7 26 KSO123
6 25 6
KSO13 5 6 25 KSO134 5
5

1
KSO14 D
4

3
KSO11 4 100P_1206_8P4C_50V8
3 2
KSO10 3 @ @
2 C P5 G
KSO15 1 2 KSO141 8 S Q703

3
1 KSO112 2N7002_SOT23
7
ACES_85202-2405 KSO103 6
KSO154 5

100P_1206_8P4C_50V8

B B

JP33 J P43
1 20 P C I_CBE#0
1
2
+5VS FOR LPC SIO DEBUG PORT 20
19 P C I _AD6
P C I_CBE#0 1 9,24,26,27
P C I_AD6 1 9,24,26,27
DEBUG PORT
2 19 P C I _AD4
3 +3VS 18 P C I_AD4 1 9,24,26,27
3 18 P C I _AD2
4
4
17
17
P C I _AD0
P C I_AD2 1 9,24,26,27 + 5VALW
R 725
2 1
@ 0_0402_5%
+5VALW : FOR EC
5 16 P C I_AD0 1 9,24,26,27
5 16 P C I _AD1
6
6
L P C_AD0
C LK_14M_SIO 1 5,34 L P C _AD[0..3] 15
15
P C I _AD3
P C I_AD1 1 9,24,26,27 +3VS : FOR P-80
7 L P C_AD[0..3] 2 0,33,34 22 14 P C I_AD3 1 9,24,26,27 + 3VALW 2 1
7 L P C_AD1 2214 P C I _AD5 R 726 0_0402_5%
21 8 21 13 P C I_AD5 1 9,24,26,27
21 8 L P C_AD2 2113 P C I _AD7 J P 22
22
22 9
9
10 L P C_AD3 12
12
11 P C I _AD8
P C I_AD7 1 9,24,26,27 @
1
P80_DATA
10 11 P C I_AD8 1 9,24,26,27 1
11 L P C_FRAME# L P C_FRAME# 2 0,33,34 10 P C I_CBE#1 EC_TX 2 5
11 10 P C I_CBE#1 1 9,24,26,27 3 3,34 EC_TX 2 5
12 L PC_DRQ#0 L PC_DRQ#0 20 R 391 9 P C I_CBE#2 3 6
12 9 P C I_CBE#2 1 9,24,26,27 3 3,34 EC_RX 3 6
13 P CI_RST# 10K_0402_5% 8 P C I_CBE#3 4
13 P CI_RST# 1 9,21,24,25,26,27,33,34 8 P C I_CBE#3 1 9,24,26,27 4
14
14
15
2 1
7
7
6 ACES_85205-0400
P80_CLK
15 C L K_PCI_DB 1 5,34 6 C L K_PCI_DB 15,34
16 S I RQ @ 5 +5VS ME@
16 S IRQ 21,24,26,33,34 5
17 4 P CI_RST# 19,21,24,25,26,27,33,34
17 4
18 3 P C I_ FRAME# 1 9,24,26,27
18 3
19 2 P C I_ TRDY# 1 9,24,26,27
19 2 P C I _AD9
20 1 P C I_AD9 1 9,24,26,27
20 1
ACES_85201-2005 ACES_85201-2005
ME@ ME@
A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KBD,ON/OFF,T/P,LED/B,DEBUG
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C us tom I GL 50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 32 of 48
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

+3VALW

L6 +EC_AVCC
+3VALW 1 2 +EC_AVCC
FBM-11-160808-601-T_0603 2 1
C212 1 1 1 1 1 1 Analog Board ID definition,
C211

0.1U_0402_16V4Z
C231

0.1U_0402_16V4Z
C447

0.1U_0402_16V4Z
C248

0.1U_0402_16V4Z
C220

1000P_0402_50V7K
C237

1000P_0402_50V7K
C201
0.1U_0402_16V4Z
L7 1000P_0402_50V7K Please see page 3.
1 ECAGND 2
1 2
2 2 2 2 2 2
FBM-11-160808-601-T_0603 +3VALW

D D

2
105
127
141
R119 Ra

11
26
37

75
U6 2 1 C202 ECAGND 100K_0402_1%
1 71 BATT_TEMP 0.01U_0402_25V4Z

VCC/ EC VCC
VCC / EC VCC
VCC / EC VCC
VCC / EC VCC
VCC
VCC

EC_AVCC / AVCC
20 GATEA20 GA20/ GPIO00/GA20 BATTEMP/AD0/GPIO38 BATT_TEMP 40
2 1 2 72 BATT_OVP
20 KB_RST# BATT_OVP 41

1
KBRST#/GPIO01/KBRST# BATT OVP/AD1/GPIO39 B RD_ID
21,24,26,32,34 S IRQ 3 73 ADP_ID <For HDL Only>
SERIRQ ADP_I/AD2/GPIO3A B RD_ID
20,32,34 LPC_FRAME# 5 74 1
RB751V_SOD323 LPC_FRAME# / LFRAME# AD BID0/AD3/GPIO3B

2
LPC_AD3 6 1 2 C208 Rb
20,32,34 LPC_AD3 LPC AD3/LAD3
D812 LPC_AD2 9 AD INtput or GPI C206 0.1U_0402_16V4Z
20,32,34 LPC_AD2 LPC AD2/LAD2 BRD ID

0.1U_0402_16V4Z
LPC_AD1 10 Host @ R115
20,32,34 LPC_AD1 LPC AD1/LAD1 INTERFACE 2 8.2K_0402_5%
LPC_AD0 12
20,32,34 LPC_AD0
14
LPC AD0/LAD0
76 DAC_BRIG ID BRD ID R115(Rb) Vab

1
15 CLK_PCI_LPC CLK_PCI_EC/PCICLK DAC_BRIG/DA0/GPIO3D DAC_BRIG 16
15 PWR 78 EN_FAN1
19,21,24,25,26,27,32,34 PCI_RST# PCIRST# EN DFAN1/DA1/GPIO3D EN_FAN1 4
2 1 2 1 1 2 EC_RST# 42 79 IR EF
R143@ 10_0402_5%
+3VALW
R112 47K_0402_5% EC_SCI# 24
EC RST#/ ECRST# IREF2/DA2
80
IRE F 41 0 R01 (EVT) 0 0V
21 EC_SCI# EC SCI#/SCI#/GPIO0E EN DFAN2/DA3/ GPIO3F TP_ACT_LED#
C232 1 2 44
@ 22P_0402_50V8J
21,24,26,27 PCI_CLKRUN#
@ 0_0402_5% PM_CLKRUN#/ CLKRUN# DA output or GPO
1 R02 (DVT) 8.2K 0.25V +3VALW
2
C200 R336 FAN/PWM
37 EC_GPIO1D
25 INVT_PWM
2 R03 (PVT) 18K 0.50V
0.1U_0402_16V4Z INVT_PWM/GPIO0F/PWM1 INVT_PWM 16
KSI0 63 27 BEEP#
BEEP# 29 3 R10A (MP) 33K 0.82V IGL50

2
1 KSI1 KSI0/GPIO30 BEEP#/GPIO10/PWM2
64 30 EC_GPIO12 38
+3VALW KSI2 KSI1/GPIO31 OUT BEEP/GPIO12/PWM3 ACOFF R125
65
KSI2/GPI032 ACOFF/GPIO18/PWM4
31 ACOFF 39,41 4 56K 1.19V Ra
KSI3 66 32 FAN_SPEED1 100K_0402_1%
KSI4 KSI3/GPIO33 FAN SPEED1/GPIO14/FANFB1 MB_ID FAN_SPEED1 4
67 33 UMA@
KSI4/GPIO34 FAN SPEED2/GPIO15/FANFB2 5 100K 1.65V
2

KSI5 68

1
R134 KSI6 KSI5/GPI035 MB_ID
69 6 200K 2.20V
10K_0402_5% KSI7 KSI6/GPIO36 EC_GPIO4A
70 91
KSI7/GPIO37 PSCLK1

2
key Matrix
KSO0 47 scan PSDAT1
92
93 TV_TUNER_LED#
EAPD 29,30,31 7 NC 3.30V R126
TV_TUNER_LED# 38 Rb
1

KSO1 KSO0/GPIO20 PS2 interface PSCLK2 CAMERA_BTN# 0_0402_5%

24 CB_PME# 1 2 48 94 CAMERA_BTN# 38 R119(Ra)=100K Ohm
C R131 @ 0_0402_5% KSO2 KSO1/GPIO21 PSDAT2 TP_CLK VGA@ C
49 95 TP_CLK 37 IGL51
EC_PME# KSO3 KSO2/GPIO22 PSCLK3 TP_DATA
1 2 50 96 MB_ID

1
26 R5_PME# KSO3/GPIO23 PSDAT3 TP_DATA 37
R141 @ 0_0402_5% KSO4 51
KSO5 KSO4/GPIO24 ADB0
1 2 52 125 R125(Ra) R126(Rb)
27 LAN_PME# R138 0_0402_5% KSO6 53
KSO5/GPIO25
KSO6/GPIO26
ADB0/D0
ADB1/D1
126 ADB1 ID MB
1 2 KSO7 54 128 ADB2
19 PCI_PME# R127 0_0402_5% KSO8 55
KSO7/GPIO27 Data ADB2/D2
130 ADB3
0 IGL50(VGA) NC 0 Ohm
KSO[0..15] KSO9 KSO8/GPIO28 BUS ADB3/ D3 ADB4
32 KSO[0..15] KSO10
56
57
KSO9/GPIO29 ADB4/D4
131
132 ADB5
1 IGL51(UMA)100K Ohm NC
K SI[0..7] KSO11 KSO10/GPIO2A ADB5/D5 ADB6
58 133
32,38 KSI[0..7] KSO12 KSO11/GPIO2B ADB6/D6 ADB7
59 134
KSO13 KSO12/GPIO2C ADB7/D7 KBA0
60 111
KSO14 KSO13/GPIO2D KBA0/A0 KBA1 KBA[0..19]
61 112
KSO15 KSO14/GPIO2E KBA1/A1 KBA2 34 KBA[0..19]
62 113
KSO16 KSO15/GPIO2F KBA2/A2 KBA3 ADB[0..7]
38 KSO16 89 114
KSO17 EC URXD/KSO16/GPIO48 KBA3/A3 KBA4 34 ADB[0..7]
+3VALW 90 115
38 KSO17 EC UTXD/KSO17/GPIO49 KBA4/A4 KBA5
RP14 116
KBA5/A5 KBA6
1 8 117
F RD# EC_SMB_DA2 Address KBA6/A6 KBA7
2 7 4 EC_SMB_DA2 88 118
EC_SMB_CK2 EC SMD2/ GPIO47/SDA2 BUS KBA7/A7 KBA8 +5VS
3 6 4 EC_SMB_CK2 87 119
FSEL# EC_SMB_DA1 EC SMC2/GPIO46/SCL2 SM BUS KBA8/A8 KBA9
4 5 34,40 EC_SMB_DA1 86 120
100K_1206_8P4R_5% EC_SMB_CK1 EC SMD1/GPIO44/SDA1 KBA9/A9 KBA10 TP_CLK
34,40 EC_SMB_CK1 85 121 1 2
R7131 0_0402_5% EC SMC1/GPIO44/SCL1 KBA10/A10 KBA11 R142 4.7K_0402_5%
13,14 EC_P80_CLK 2 122
+5VALW R7141 0_0402_5% KBA11/A11 KBA12 TP_DATA 1
13,14 EC_P80_DATA 2 123 2
EC_TX KBA12/A12 KBA13 R146 4.7K_0402_5%
32,34 EC_TX 34 124
EC_SMB_CK1 EC_RX PCM_SPK#/EMAIL_LED#/ GPIO16 KBA13/A13 KBA14
1 2 32,34 EC_RX 35 110
R130 4.7K_0402_5% SB_SPKR/PWR_SUSP_LED#/ GPIO17 KBA14/A14 KBA15
38 PWR_LED# 38 109
EC_SMB_DA1 PWRLED#/ GPIO19 KBA15/A15 KBA16 +3VALW
1 2 38 NUM_LED# 40 108
R133 4.7K_0402_5% CHARGE_LED0# 99 NUMLED#/ GPIO1A KBA16/A16 KBA17
38 CHARGE_LED0# 107
CHARGE_LED1# 101 BATT CHGI LED#/ E51CS# KBA17/A17 KBA18 KBA1 @
38 CHARGE_LED1# 106 1 2
+3VS CAPS_LED# BATT LOW LED#/ E51MR0 KBA18/A18 KBA19 R147 1K_0402_5%
38 CAPS_LED# 100 98
B
CAPS LED#/ E51TMR1 KBA19/A19 KBA4 B
32 RC IRRX 102 1 2
EC_SMB_CK2 S YSON ARROW LED#/ E51 INT0 R148 @ 1K_0402_5%
1 2 35,37,43 S YS ON 104 84 ENBKL 16
R135 4.7K_0402_5% SYSON/GPIO56/ E51 INT1 SELIO2#/ GPIO43 BT_OFF# KBA5
97 BT_OFF# 28 1 2
EC_SMB_DA2 SELIO#/ GPIO50 F RD# R149 @ 1K_0402_5%
1 2 21 EC_RSMRST# 4 135 FRD# 34
R139 4.7K_0402_5% BKOFF# EC_RSMRST#/ GPIO02 FRD#/RD# F WR#
1 1 16 BKOFF# 7 136 F WR# 34
C226 C223 BKOFF#/GPIO03 FWR#/WR# FSEL#
21 SLP_S3# 8 144 FSEL# 34
EC_LID_OUT# PM SLP S3#/GPIO04 FSEL#/SELMEM#
21 EC_LID_OUT# 16
@ 100P_0402_50V8J @100P_0402_50V8J EC LID OUT#/GPIO06 EC_ON
21 SLP_S5# 17 41 EC_ON 32
2 2 EC_SMI# PM SLP S05#/ GPIO07 EC ON/ GPIO1B C RY1 R150 C RY2
21 EC_SMI# 18 43 A C IN 21,39
R4011 0_0402_5% 19 EC SMI#/GPIO08 AC IN/ GPIO1C EC_THERM# 20M_0402_5%
31 EC_GPIO09 2 29 EC_THERM# 21
LID_SWITCH# EC SWI#/GPIO09 ECTHERM#/GPIO11 @
37 L ID_SWITCH# 20 36 ON/OFF# 32
SUSP# LID SW#/ GPIO0A ONOFF/GPIO18 ICH_POK
18,24,26,34,35,37,43,44 SUSP# 21 45 ICH_POK 7,21
PBTN_OUT# SUSP#/GPIO0B PCMRST#/GPIO1E
21 PBTN_OUT# 22 46 WL_OFF# 28
EC_PME# PBTN_OUT#/GPIO0C WL OFF#/GPIO1F
COMM EC_GPIO Configuration 23
EC PME#/GPIO0D
ALI/MH#/GPIO40
81 EC_MUTE# 30
82 FSTCHG
FSTCHG/GPIO41 FSTCHG 41
PIN GPIO HDL00/HDL10 HGT30/HGT31 IGL50/IGL51 83 V R_ON
VR ON/ GPIO42 VR_ON 45
137 EC_GPIO57
C RY1 GPIO57/GPIO57 EC_GPIO58 EC_GPIO57 38
80 EC_GPIO3F NC TP_ACT_LED# NC 140 142 1 2 C250 C249
SLP_S4# 21

4
XCLKO GPIO58/GPIO58
AGND

C RY2 138 143 EC_GPIO59 R486 0_0402_5%

GND
GND
GND
GND
GND
GND

XCLKI GPIO59/GPIO59 EC_GPIO59 38

15P_0402_50V8J

15P_0402_50V8J
19 EC_GPIO09 EASY_KEY1# LED6# SUBWOOFER_MUTE# X1

IN

OUT
35 EC_GPIO17 SUSP_LED# EC_P80_DATA EC_P80_DATA KB910L_LQFP144
139
129
103
13
28
39

77

NC

NC
44 EC_GPIO1D NC LED3# TP_ACT_LED#
E CAGND

@
91 EC_GPIO4A NC LED4# USB_ON# S YSON# 1 2 USB_ON#
35 S YSON# USB_ON# 31,37

3
R737 0_0402_5%
EC_GPIO4A 1 2 <For USB Port>
92 EC_GPIO4B NC EAPD IN EAPD IN R738 0_0402_5%
93 EC_GPIO4C NC LED1# TV_TUNER_LED# 32.768KHZ_12.5P_1TJS125BJ2A251
A A
94 EC_GPIO4D NC LED2# CAMERA_BTN#
102 EC_GPIO55 NC LED5# RCIRRX
97 EC_GPIO50 MEDIA# BT_OFF# BT_OFF#
137 EC_GPIO57 VOL_UP# NOVO_BTN# NOVO_BTN# Security Classification Compal Secret Data Compal Electronics, Inc.
142 EC_GPIO58 VOL_DOWN# SLP_S4# SLP_S4# Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

143 EC_GPIO59 KILL_SW# WIRE_LAN_BTN# RF_BTN# THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ENE-KB910L
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
C ustom 0.1
30 EC_GPIO12 AMP_MUTE TP_LOCK_LED# SUBWOOFER_BTN# DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
IGL50/51 LA-3771
Date: 星期一, 七月 31, 2006 Sheet 33 of 48
5 4 3 2 1
 + 3VALW + 3VALW + 3VALW
C 501

1
1 2 R 442
100K_0402_1% U2 6 R 337 + 5VALW
S USP# 1 8,24,26,33,35,37,43,44

5
0 . 1 U_0402_16V4Z T C7SH32FU_SSOP5 100K_0402_5%
U3 2 R 339

2
INT _ F LASH_EN# +5VALW

G
2 1 2

P
I0

1
T C7SH32FU_SSOP5 IN T_FSEL# 1 2 4 C 199

2
O F SEL#
2 1 3 1 1 2 0 . 1 U_0402_16V4Z R 116

P
I0 E C _ FLASH# 21 F SEL# 33

G
F W E# 22_0402_5% I1 100K_0402_1%
4

S
O
1

3
G
I1 Q30 U4

2
2N7002_SOT23 8 1

3
VCC A0
7 2
WP A1
F W R# 33 3 3,40 EC_SMB_CK1 6 3
SCL A2
3 3,40 E C_SMB_DA1 5 4
SDA GND
R 707 1 2 0_0402_5% 1 2 AT24C16AN-10SU-2.7_SO8
R 338 0_0402_5%
@ @

1
Reserve R339, if U26 is single gate. R 117
100K_0402_1%

2
K B A[0..19]
33 K BA[0..19]
AD B [0..7]
1MB Flash ROM
33 AD B [0..7]
+ 3VALW
U3 0

K BA0 21 31
K BA1 A0 VCC0
20 30 1
K BA2 A1 VCC1 C 416
19
K BA3 A2
18
K BA4 17 A3 25 A DB0 0 . 1 U_0402_16V4Z
K BA5 A4 D0 A DB1 2
16 26
K BA6 A5 D1 A DB2
15 27
K BA7 A6 D2 A DB3
14 28
K BA8 A7 D3 A DB4
8 32
K BA9 A8 D4 A DB5
7 33
K BA10 A9 D5 A DB6
36 34
K BA11 6 A10 D6 35 A DB7
K BA12 A11 D7
5
K BA13 A12
4
K BA14 A13 RESET#
3 10 1 2 + 3VALW
K BA15 A14 RP# R 443
2 11
K BA16 A15 NC 100K_0402_1%
1 12
K BA17 40 A16 READY/BUSY# 29
K BA18 A17 NC0
13 38
K BA19 A18 NC1
37
A19
IN T_FSEL# 22
F R D# CE#
33 F R D# 24 23
F W E# OE# GND0
9 39
WE# GND1

SST39VF080-70-4C-EIE_TSOP40

Change to small socket for ROM part

New LPC Debug Pad ---- MB side J P812

R 879 K BA16 K BA17
1 5,32 C LK_14M_SIO 1 2
@ 0_0402_5% K BA15
H3 1 3 4
1 2 EC_TX EC_TX 32,33
K BA14
R 880 K BA13 5 6 K BA19
@ 0_0402_5% K BA12 7 8 K BA10
EC_RX L PC_DRQ1# SB_INT_FLASH_SEL tie to ATI SB K BA11 9 10 A DB7
32,33 EC_RX 1 2 6 5 1 2 LPC_DRQ#1 20
R 881 K BA9 11 12 A DB6
GPIO41 and pull down 13 14
0_0402_5% K BA8 A DB5
1 2 S E RIRQ 7 4 F W E# 15 16 A DB4
21,24,26,32,33 S IRQ P CI_RST# 1 9,21,24,25,26,27,32,33 17 18
R 882 RESET# + 3VALW
0_0402_5% INT _ F LASH_EN# 19 20
L P C_AD3 L P C_AD2 S B _ INT_FLASH_SEL 21 22
2 0,32,33 L PC_AD3 8 3 L P C_AD2 2 0,32,33 21 S B _INT_FLASH_SEL K BA18 23 24 A DB3
K BA7 25 26 A DB2
L P C_AD1 L P C_AD0 K BA6 27 28 A DB1
2 0,32,33 L PC_AD1 9 2 L P C_AD0 2 0,32,33
K BA5 29 30 A DB0
K BA4 31 32 F R D#
L P C_FRAME# K BA3 33 34
2 0,32,33 L P C_FRAME# 10 1 C L K_PCI_DB 1 5,32
K BA2 35 36 F SEL#
K BA1 37 38 K BA0
39 40
@
D E B UG_PAD S UYIN_80065AR-040G2T
ME@

Under DDR ME Assigment Area

Keep Resistor near Debug Pad and in the same side
Standard side DIMM ---- Pin 1 near DIMM Security Classification Compal Secret Data Compal Electronics, Inc.
2005/10/06 2006/10/06 Title
Reverse side DIMM ---- Pin 1 keep away DIMM Issued Date Deciphered Date
BIOS & EC I/O Port
THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C us tom I GL 50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 34 of 48

WWW.AliSaler.Com
 A B C D E F G H I J

+5VALW

1
R 92
+5VALW to +5VS Transfer
1 47K_0402_5% 1

2
+ 5VALW +5VS S YS ON#
33 S YS ON#

1
U2 7 0 . 1 U_0402_16V4Z
8 1
C 435 D S
1 7 2
+VSB 1 0 U_0805_10V4Z 6 D S 3
D S 1 1
5 4 3 3,37,43 S YS O N 2
D G C 426 C 419

1
2 S I4 800DY_SO8 1 0 U_0805_10V4Z Q6
R 384 2 2
10K _0402_5% DTC124EK_SC59

3
2
R UNO N
2 2
1

1
D
S USP 2 C 434
G 0 . 1 U_0603_50V4Z
Q26 S 2

3
2N7002_SOT23

+ 5VALW

1
R 334

3 10K _0402_5% 3

2
S USP
44 S USP

1
D

1 8,24,26,33,34,37,43,44 S USP# 2
G Q24
+3VALW to +3VS Transfer S 2N7002_SOT23

3
+ 3VALW
+3VS
U7 0 . 1 U_0402_16V4Z
8 1
D S
1 7 2
+VSB C 236 D S
6 3 1 1
1 0 U_0805_10V4Z D S C 229 C 225
5 4
4 D G 4

1
2 S I4 800DY_SO8 1 0 U_0805_10V4Z
R 136 2 2
22K _0402_5%

2
R 132 1 2 R UNO N +5VS + 1.8VS +0.9VS
@0_0402_5%
1

1
D
S USP 2 C 224 R 335 R 58 R 106
G 0 . 1 U_0603_50V4Z
Q11 S 2 470_0402_5% 470_0402_5% 470_0402_5%
3
2N7002_SOT23

1 2

1 2

1 2
D D D
5 5
2 S USP 2 S USP 2 S USP
G G G
S Q25 S Q3 S Q8

3
2N7002_SOT23 2N7002_SOT23 2N7002_SOT23

+1.8V to +1.8VS Transfer + 1.8V +3VS +2.5VS

+1.8V

1
+1.8VS VGA@
U1 7 0 . 1 U_0402_16V4Z R 228 R 731 R 105
8 1
D S 470_0402_5% 470_0402_5% 470_0402_5%
6 1 7 2 6
+VSB C 313 6 D S 3 1 1

1 2

1 2

1 2
VGA@ D S C 131 C 133
5 4
1 0 U_0805_10V4Z D G VGA@ D D D
1

2 S I4 800DY_SO8 1 0 U_0805_10V4Z 2 S YS ON# 2 S USP 2 S USP

R 227 VGA@ 2 2 G G G
33K _0402_5% S Q5 S Q704 S Q7

3
VGA@ 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23
2

R 129 1 2 R UNO N
@ 0_0402_5%
1
1

D
S USP 2 C 312
G 0 . 1 U_0603_50V4Z
Q20 S 2
VGA@
3

7 2N7002_SOT23 7
VGA@

8
Security Classification Compal Secret Data Compal Electronics, Inc. 8
Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Circuit
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C u s tom I G L50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 35 of 48
A B C D E F G H I J
 A B C D E

CLOSE TO JTVOUT1

17 L UMA 1
L 802
2
VGA I/O PORT Connector

82P_0402_50V8J

82P_0402_50V8J
FLM1608081R8K_0603 +3VS
1

1
1 D 802 D 803 D 804

C801
C802
1 2
2
S-VIDEO 1
D A204U_SC70 D A2 04U_SC70 D A204U_SC70

3
@ @ @ J P802
1 7
L UM A_OUT C R MA_OUT 1 G1
2
L 803 3 2
C R MA_OUT L UM A_OUT 3
17 C R MA 1 2 4
4

82P_0402_50V8J
82P_0402_50V8J
FLM1608081R8K_0603 COMP_OUT 5
COMP_OUT 5
1 1 6 8
6 G2
C803

C804
MOLEX_53780-0670
ME @
2 2

L 801
17 C OMP 1 2
82P_0402_50V8J

82P_0402_50V8J
FLM1608081R8K_0603
1 1 +3VS

1
C805

C806 D805 D 801 D 806 +CRT_VCC

2 2
DSUB
J P801
D A204U_SC70 D A2 04U_SC70 D A204U_SC70 1

3
R ED_OUT 1
@ @ @ 2
3 2
+5VS + CRT_VCC GR EEN_OUT 3
4
L804 4
5
2 CHB1608B121_0603 D 807 B LUE_OUT 6 5 2
6

2
17 RED 1 2 7 15
L805 J VG A_VS_OUT 7 15
8 16
CHB1608B121_0603 9 8 16
J VGA _HS_OUT 9
17 GR E EN 1 2 10
L806 RB751V_SOD323 10
MSEMS# 11

1
CHB1608B121_0603 VGA _DDC_DAT_OUT 11
12
VGA _DDC_CLK_OUT 12
17 B L UE 1 2 13
13
14
14
22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

1 1 1 1 1 1 P IN4
1 1 ACES_87213-1400
C807

C808

C809

C 810 C 811 C 812 C814 ME@

10P_0402_25V8K10P_0402_25V8K 10P_0402_25V8K C 813
2 2 2 2 @ 2 @ 2 @ 0 . 0 1U_0402_25V4Z
2 2 0 . 1 U_0402_16V4Z

+ CRT_VCC

PIN ASSIGMENT
1

2
2.2K_0402_5%

2.2K_0402_5%
1K_0402_5%

1K_0402_5%

PIN D-SUB FUNCTION PIN SVIDEO FUNCTION

R801

R803
R802

R804

R ED_OUT
GR EEN_OUT
1 9 +CRT_VCC 1 1 NC
2

B LUE_OUT
17 VGA_DDC_DAT
VGA _DDC_DAT_OUT
L807 CHB1608B121_0603 VGA _DDC_CLK_OUT
17 VGA_DDC_CLK
17 JVGA_ HS
17 JVGA_VS
1
1
2
2
J VGA _HS_OUT
J VG A_VS_OUT
2 1 RED 2 4 CRMA
3 3

3 6 GND 3 2 GND
33P_0402_50V8J

33P_0402_50V8J

L808 CHB1608B121_0603 1 1
C815

C816

@
2
@
2
4 2 GREEN 4 3 LUMA
5 7 GND 5 5 GND
6 3 BLUE 6 6 CVBS
C F1 CF2 C F3 CF4 C F5 CF6 C F7 CF8 C F9 C F 10 C F11 C F 12 C F13 C F 14
7 8 GND
1 1 1 1 1 1 1 1 1 1 1 1 1 1
8 14 VSYNC
F M1 F M2 F M3 F M4 F M5 F M6
1 1 1 1 1 1 9 10 GND
H1 H2 H3 H4 H5 H6 H7 H8 H9 H1 0 H1 1 H1 2 H1 3 H1 4 H1 5
10 13 HSYNC
HO LEA HO LEA HO LEA HO LEA HO LEA HO LEA HO LEA HO LEA HO LEA HO LEA HO LEA HO LEA HO LEA HO LEA HO LEA
11 11 SENSE
12 12 SM_DAT
1

C L2

4 H3 2
C L IP 13 15 SM_CLK 4
H1 7 H1 8 H1 9 H2 0 H2 1 H2 2 H2 3 H2 5 H2 6 H2 7 H2 8 H2 9 H3 0 C L1 H3 3 HOLEA
HO LEA HO LEA HO LEA HO LEA HO LEA HO LEA HO LEA HO LEA HO LEA HO LEA HO LEA HO LEA HO LEA C L IP HO LEA 14 4 PIN4
1
1
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TVout Connector
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C us tom I GL 50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 36 of 48
A B C D E

WWW.AliSaler.Com
 5 4 3 2 1

NEW CARD FOR C38

+1.5VS_PEC
CMOS Camera Conn
4 . 7 U_0805_10V4Z

Express Card Power Switch 1 1

EXP@ C 817 C 818 EXP@ +5VS
EXP@ C 819 +1.5VS 0 . 1 U_0402_16V4Z
U8 01 +1.5VS_PEC 2 2
0 . 1 U_0402_16V4Z
D 2 1 12 11 D
1.5Vin 1.5Vout 2 1
14 13
EXP@ C 820 1.5Vin 1.5Vout C 860 C 861
+3VS +3VS_PEC
0 . 1 U_0402_16V4Z 0 . 1U_0402_10V6K
2 1 2 3 4 . 7 U_0603_6.3V6M 1 2
4 3.3Vin 3.3Vout 5 +3V_PEC J P813
EXP@ C 821 3.3Vin 3.3Vout +3V_PEC
+3VALW 1
US B20_N5 1
2 1 17 15 21 US B20_N5 2 1 2
AUX_IN AUX_OUT U SB20_P5 R869 2 0_0603_5% 2
21 USB20_P5 1 3
0 . 1 U_0402_16V4Z PLT_RST# R870 0_0603_5% 3
7 ,19,23,28 PLT_RST# 6 19 1 1 4
SYSRST# OC# 4
5
S YS ON PERST# EXP@ C 822 C 823 EXP@ 5
3 3,35,43 S YS O N 20 8 6
SHDN# PERST# 0 . 1 U_0402_16V4Z 4 . 7 U_0805_10V4Z 7 GND1
S USP# 2 2 GND2
1 8,24,26,33,34,35,43,44 S USP# 1 16
STBY# NC ACES_88266-05001
+ 3VALW 2 R 807 1EXP@ 100K_0402_5% 10 7 ME@
CPPE# GND
9 +3VS_PEC
21 C P USB# CPUSB# 4 . 7 U_0805_10V4Z
18
RCLKEN
R 5538_QFN20 1 1
EXP@
EXP@ C 824 C 825 EXP@
0 . 1 U_0402_16V4Z
2 2

close to JP14 J P803

C EXP@ 0_0402_5% 1 C
US B20_N7 R 808 U SB7- GND
21 US B20_N7 1 2 2
U SB20_P7 R 809 USB7+ USB_D-
21 USB20_P7 1 2 3
C PUSB# 4 USB_D+
EXP@ 0_0402_5% CPUSB#
5
6
RSV
RSV
USB board
IC H _SMBCLK 7 Pulled up on ICH7M side
1 5,21,28 IC H_SMBCLK SMB_CLK
IC H_ SMBDATA 8
1 5,21,28 IC H_ SMBDATA SMB_DATA + 5VALW
+1.5VS_PEC 9
+1.5V +5VALW + USB_VCCD
+1.5VS_PEC 10
R 811 1 2 P C IE_PME#_R 11 +1.5V U9 + USB_VCCB
2 1,28 IC H_ PCIE_W AKE# WAKE#
12 0 . 1 U_0402_16V4Z 1 8 U8 03
EXP@ +3V_PEC PERST# +3.3VAUX C483 GND OUT
13 2 7 1 8
0_0402_5% 14 PERST# 2 1 3 IN OUT 6 2 GND OUT 7
+3VS_PEC +3.3V IN OUT IN OUT
15 4 5 3 6
C L K RENC# +3.3V EN# FLG USB_OC#2 21 IN OUT
15 C L KREQ_NC# 16 1 4 5 1 2
C PUSB# CLKREQ# G528_SO8 EN# FLG R 871 0_0402_5% USB_OC#4 21
17 1 2 USB_OC#6 21
C L K _PCIE_NC1# 18 CPPE# R 816 0_0402_5% C 862 G528_SO8
15 C L K _PCIE_NC1# REFCLK-
C L K _PCIE_NC1 19 US B_ON# 1 0 . 1 U_0402_16V4Z 1
15 C L K _PCIE_NC1 REFCLK+ 2
20 C500 C863
P C IE_RXN1 GND @ 1000P_0402_50V7K @ 1000P_0402_50V7K
21 P C IE_RXN1 21
P CIE_RXP1 PERn0
21 PCIE_RXP1 22
PERp0 2 2
23
P CIE_TXN1 24 GND
21 P CIE_TXN1 PETn0
21 PCIE_TXP1 PCIE_TXP1 25
PETp0 US B_ON#
26 3 1,33 US B_ON#
GND
27
GND
28
GND
close to JP14 F OX_1CH4110C
ME@
B B

+ USB_VCCB

1
+ C 827
1 1
C826 C 828
1 5 0 U_D_6.3VM J P27
0 . 1 U_0402_16V4Z 1000P_0402_50V7K 1
T/P Board LID Switch
2 2 2
1 2
2
3
1
2
21 US B 20_N6 3
21 USB20_P6 1R 872 0_0402_5%
2 4
R 873 0_0402_5% 4
5 21
5 21
21 US B 20_N2 1 2 6 22
+ USB_VCCD 6 22
21 USB20_P2 1R 814 0_0402_5%
2 7
+3VALW R 815 0_0402_5% 8 7
JP804 8
+ 3VALW 1 2 1 9
R 195 0_0402_5% 9
1 +5VS 1 1 21 US B 20_N4 1 2 10
2

1 C 865 C 864 + C 866 10

2 21 USB20_P4 1R 817 0_0402_5%
2 11
2 11
2

3 TP_DATA TP_DATA 33 R 193 R 481 R 818 0_0402_5% 12

3 TP_CLK 100K_0402_5% 1000P_0402_50V7K 1 5 0 U_D_6.3VM 0 . 1 U_0402_16V4Z 12
9 4 47K_0402_5% 1 2 13
VDD

9 4 TP_CLK 33 2 2 2 30 EXT_MIC 13
10 5 2 1 R 846 0_0402_5% 14
10 5 29 S P DIF 14
6 D 19 15
1

6 29 J AC K _ P LUG_MIC 15
7 R 821 470_0402_5% 1 3 1 2 16
7 OUTPUT L ID _ SW ITCH# 33 16
8 C 286 RB751V_SOD323 17
8 30 PL 17
0 . 1 U_0402_16V4Z 18
GND

29 J AC K _PLUG 18
ACES_87151-0807G C 287 19
2 30 PR 19
ME@ 20
20
15P_0402_50V8J

U1 3 680P_0402_50V7K 1
1

EXT_MIC C836 C 837 C 838 ACES_87213-2000

680P_0402_50V7K C 169 ME@
E C_GPIO1D 33
A3212EEHLT-T_SOT23W-3 C 835 @
A C878 2 A
680P_0402_50V7K 680P_0402_50V7K 680P_0402_50V7K 100P_0402_50V8J
Normally Short For JACK_PLUG
C835 ~ C838 For EMI Solution

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
INDICATE LED
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C us tom I GL 50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 二 , 八 月 01, 2006 Sheet 37 of 48
5 4 3 2 1
 5 4 3 2 1

4 in 1 Card Reader + VC C_4IN1

+ VC C_4IN1_XD
UMA LCD/PANEL Conn.
JP814
41 15
XD-VCC SD-VCC J P815
MS-VCC
9 (60 MIL)
S D DATA0_MSDATA0 33 R 874 22_0402_5% +3VS 16 1
26 S DDATA0_MSDATA0 XD-D0 16 1
S D_MSDATA1 34 4 IN 1 CONN 16 S DCLK 1 2 S DCLK_MSCLK E D I D_CLK_LCD 17 2
26 S D_MSDATA1 XD-D1 SD_CLK 9 E D ID_CLK_LCD 17 2
S D_MSDATA2 35 19 S D DATA0_MSDATA0 E D I D_DAT_LCD 18 3 + L CDVDD
26 S D_MSDATA2 XD-D2 SD-DAT0 S DDATA0_MSDATA0 26 9 E D ID_DAT_LCD 18 3
S D DATA3_MSDATA3 36 20 S D_MSDATA1 19 4
26 S DDATA3_MSDATA3 XD-D3 SD-DAT1 S D_MSDATA1 26 19 4
XDD4 37 11 S D_MSDATA2 L VDSAC+ 20 5 LVDSBC+
26 XDD4 XD-D4 SD-DAT2 S D_MSDATA2 26 9 L VDSAC+ 20 5 L VDSBC+ 9
XDD5 38 12 S D DATA3_MSDATA3 L V DSAC- 21 6 L VDSBC-
D 26 XDD5 XD-D5 SD-DAT3 S DDATA3_MSDATA3 26 9 L VDSAC- 21 6 L VDSBC- 9 D
XDD6 39 13 S DCMD_MSBS 22 7
26 XDD6 XD-D6 SD-CMD S DCMD_MSBS 26 22 7
XDD7 40 21 S DCD#_XDCD0# L VDSA2+ 23 8 LVDSB2+
26 XDD7 XD-D7 SD-CD-SW S DCD#_XDCD0# 26 9 LVDSA2+ 23 8 LVDSB2+ 9
22 L VDSA2- 24 9 LVDSB2-
SD-CD-COM 9 L VDSA2- 24 9 LVDSB2- 9
S DCMD_MSBS 30 43 SDW P#_XDRB# 25 10
26 S DCMD_MSBS XD-WE SD-WP-SW SDW P#_XDRB# 26 25 10
XDW P# 31 44 9 L VDSA1+ L VDSA1+ 26 11 LVDSB1+
26 XDW P# XD-WP SD-WP-COM 26 11 LVDSB1+ 9
XDALE 29 R 875 22_0402_5% L VDSA1- 27 12 LVDSB1-
26 XDALE XD-ALE 9 L VDSA1- 27 12 LVDSB1- 9
X DCD# 23 8 M SCLK 1 2 S DCLK_MSCLK 28 13
26 XDCD# XD-CD MS-SCLK S DCLK_MSCLK 26 28 13
SDW P#_XDRB# 25 4 S D DATA0_MSDATA0 L VDSA0+ 29 14 LVDSB0+
26 SDW P#_XDRB# XD-R/B MS-DATA0 S DDATA0_MSDATA0 26 9 L VDSA0+ 29 14 LVDSB0+ 9
S DCLK_MSCLK 26 3 S D DATA1_MSDATA1 L VDSA0- 30 15 LVDSB0-
XD-RE MS-DATA1 S DDATA1_MSDATA1 26 9 L VDSA0- 30 15 LVDSB0- 9
XD_CE# 27 5 S D DATA2_MSDATA2
26 XD_CE# XD-CE MS-DATA2 S DDATA2_MSDATA2 26
XDCLE 28 7 S D DATA3_MSDATA3 31 32
26 XDCLE XD-CLE MS-DATA3 S DDATA3_MSDATA3 26 GNDGND
6 M SCD#_XDCD1
MS-INS MSCD#_XDCD1 26
32 2 S DCMD_MSBS ME@ ACES_87216-30006
XD-GND MS-BS S DCMD_MSBS 26
24 14
XD-GND SD-GND
18 17
42 N.C. SD-GND 1
N.C. MS-GND
10
MS-GND
45
SHIELD GND
46
SHIELD GND
T AIT W_R012-210-LR

SUBWOOFER_ON/OFF_BTN# +3VS
Left Switch BD
RJ11+RJ45 CONN LED Indicator RF_ON/OFF_BTN#

1
+ 5VALW +5VS
C 3 2 1 R822 R 830 C
100K_0402_5% 100K_0402_5% J P816
1
B B A B A 2 1

2
2
3
33 E C _GPIO12 3
4
33 E C _GPIO59 4
1 2 R 805 300_0402_5% 5
Blue 28 W IRELESS_LED#
BTONLED 1 2 R 806 300_0402_5% 6 5
JP807
Wireless / Bluetooth LED Amber 28 BTONLED
7
6
MDO0+ 7
27 MDO0+ 1
TX1+ BATT_CHG_LED# C HA RGE_LED0# 2 1 R 810 470_0402_5%
8
9 8
MDO0- 2
Blue 33 C HARGE_LED0#
C HA RGE_LED1# 2 1 R 812 470_0402_5% 10
9
27 MDO0- TX1- Amber 33 C HARGE_LED1# 10
MDO1+ 3
BATT_LOW_LED# P W R_LED# 1 2 R 813
11
12 11
27 MDO1+ RX1+ 33 P W R_LED# 12
560_0402_5% 13
MDO2+ 13
4 14
27 MDO2+ TX2+ Blue : Power On, 15
14
MDO2- GND1
27 MDO2- 5
TX2- Blinking Blue : Suspend 1
C 867
1
C868
16
GND2
MDO1- 6
STATUS 1 1
27 MDO1- RX1- C 869 C 831 0 . 1 U_0402_16V4Z MOLEX_53780-1470~D
MDO3+ 7
AC BLUE 2
0 . 1 U_0402_16V4Z 2
27 MDO3+ RX2+
11 0 . 1 U_0402_16V4Z
MDO3- 8 SGND1 Chargin Blinking Blue 2 2
0 . 1 U_0402_16V4Z
27 MDO3- RX2-
12
SGND2 Low BATT Amber
RJ45 +3VS

+ 5VALW +5VS + VCC5_LED

C 829
Right Switch BD
Function
1 2 1 2

2
1 R 819 0_0402_5% 100K_0402_5% 100K_0402_5%

1
B R 827 C 833 KEY Matrix KO16 KO17 1 2 B
R J _TIP 2 1 9 R 820 0_0402_5% 1000P_0402_50V7K R 831 R829
R J_ R ING RJ11_1
2 10_0603_5% 10 @
0_0603_5% RJ11_2 2 KSI0 DW-UP DW-DOWN R 890 @ @

1
R 828 RJ11 10K_0402_5%
Dial Wheel

2
ACES_87151-16071
KSI1 DW-ENTER MUTE 16 18
ALLTO_C100B6-110A4-L 16 G18
0 . 1 U_0402_16V4Z KSO16 15 17
R J 45_PR ME@ 1 2
33 KSO16 K SI1 14 15 G17
27 R J45_PR 3 2,33 K SI1 14
C 840 1 K SI0 13
1000P_1206_2KV7K C 834 3 2,33 K SI0 KSO17 13
12
+3VALW 33 KSO17 12
33 C AMERA_BTN# 11
N OVO_BTN# 11
10
10
1

2
9
R835 9
2 9,30 INT _ MIC 8
4 . 7 U_0805_10V4Z 100K_0402_5% 7 8
NOVO BTN 33 T V_TUNER_LED#
NOVA_BTN# 33 NUM_ LED# R 834 1 2 220_0402_5% 6
7
D 810 R 833 6
1 2 220_0402_5% 5
2

33 C APS_LED# 5
2 E C_GPIO57 D 8081 2 R 832 1 2 220_0402_5% 4
E C_GPIO57 33 20 SATA_LED# 4
N OVO_BTN# C H751H-40_SC76
1
5 1ON#
HDD 3
3
3 5 1ON# 3 2,39 CD-ROM D 8091 2
2
1
2
23 O DD_LED# 1
D AN2 02U_SC70 C H751H-40_SC76
J P808
32 O N/OFFBTN#
0 . 1 U_0402_16V4Z 2 2
1 1 1 C 842
0 . 1 U_0402_16V4Z C 830 C832 C 839
C 841 1000P_0402_50V7K
MDC CONN For EMI
470P_0402_50V8J
2 2 2
1 1
1000P_0402_50V7K @

A A
JP809 KSO17 K SI1
C839, C841, C842 For EMI Solution
R J _TIP
R J_ R ING 1 K SI0 KSO16
2
3

E DL71_MDC
D 814 D 813

@ @
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

INDICATE LED
1

THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PSOT24C_SOT23 PSOT24C_SOT23 Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C us tom I GL 50/51 LA-3771 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 38 of 48
5 4 3 2 1

WWW.AliSaler.Com
 A B C D

ACIN BATT ONLY

Precharge detector Precharge detector
Min. typ. Max. Min. typ. Max.
H-->L 14.620V 14.853V 15.245V H-->L 6.169V 6.231V 6.361V
L-->H 15.534V 15.970V 16.421V L-->H 7.168V 7.349V 7.537V
V IN
P JP1 A D P IN
1 P L2
1
1 F B MA -L 1 8 -4 5 3 2 1 5 -9 0 0 L MA 9 0 T _ 1 812 P R2 1

2 1 2 1 K_1206_5%
2

1 0_1206_5%
1 2

1
100P_0402_50V8J
5 6 0 P _ 0 4 0 2 _ 5 0 V 7K
3
3

P R1
1 00P_0402_50V8J

560P_0402_50V7K
P Q1

1
4 P D2 P R3 T P 0 6 1 0 K -T 1 -E 3 _ S OT23
4

P C1

P C2

P C3

P C4
R L S 4 1 4 8 _ L L DS 2 1 K_1206_5%
VIN 2 1 1 2 3 1

2
1

R L Z24B_LL34
P D1
@ J S T _ B 4 B -E H-A (L F )(S N) P R4
1 K_1206_5%
1 2

1 00K_0402_5%

1 00K_0402_5%
2

1
P R8

P R6

P R7
1 K_1206_5%

2
P R 175 P C 131 1 2
@ 1 0 K _ 0 4 0 2 _ 1 % @ 0 . 0 1 U_ 0 4 0 2 _ 2 5 V 7 K
1 2 1 2

2
VS
P R5
V IN 1 M_ 0 4 0 2 _ 1 %
1 2

1 0K_0402_1%

1 00K_0402_5%
1

1
8 4 .5 K _ 0 4 0 2 _ 1 %
1

VS

P R9

P R13
1
P R10

P R11
1 0K_0402_5%
1 2

1 2
P R12 A CIN < 2 1 ,3 3 >
2

2 2 2K_0402_1% 2 2

1 2 3 < 3 3 ,4 1 > A COFF

P

+ P A CIN
1 P A CIN < 41>
O
2 0K_0402_1%
0 . 0 2 2 U_ 0 6 0 3 _ 2 5 V 7 K

2
B+
1

R L Z 4 .3 B _ L L 3 4

10K_0402_1%
0 . 1 U_ 0 4 0 2 _ 1 6 V 7 K

P U1A PQ2 2

3
1

1
P R14

L M 3 9 3 DG_ S O8 D T C 1 1 5 E UA _ S C7 0
4
P C5

P C6

P R15
P D3
Vin Detector
2

P Q3
2

3
P R16 D T C 1 1 5 E UA _ S C7 0
2

2
1 0K_0402_1%
2 1 RTCV RE F
3.3V High 18.384 17.901 17.430
Low 17.370 16.907 16.630 VL
P R17
2 . 2 M_ 0 4 0 2 _ 5 %
2 1

V IN

499K_0402_1%
1
R L S 4 1 4 8 _ L L DS 2
2

P R18
VS

P D4

1 00K_0402_1%
1
P R 19
P D5

2
R B 7 5 1 V -4 0 T E 1 7 _ S OD3 2 3 -2

1 1
2 1
3.3V BATT+

3 3_1206_5%
P D6

8
R TCV RE F

P R 20
R B 7 1 5 F _ S OT 3 2 3
VS 2 5
3
<40,42> MAINPWON

P
3

P U2 PQ4 +
1 7
O

1 91K_0402_1%

4 99K_0402_1%

0 . 0 1 U_ 0 4 0 2 _ 2 5 V 7 K
P R22 G 9 2 0 A T 2 4 U_ S OT 8 9 P R23 T P 0 6 1 0 K -T 1 -E 3 _ S OT23 <41> ACON 3 6
2

1
-

0 . 1 U_ 0 6 0 3 _ 2 5 V 7 K
P R 21 5 60_0603_5% 2 00_0805_5% P U1B

P C7
P R 24

P R 25
1 0 0 0 P _ 0 4 0 2 _ 5 0 V 7K
5 610 _ 0 6 0 3 _ 5 %2 1 2 3 2 2 1 C H GRTCP 3 1 L M 3 9 3 DG_ S O8

4
1

1
OUT IN

P C8
0 . 2 2 U_ 1 2 0 6 _ 2 5 V 7 K
1

P C10

P C9
1 U _ 0805_25V4Z
4 . 7 U _ 0 8 0 5 _ 6 .3 V 6 K

0 . 1 U_ 0 6 0 3 _ 2 5 V 7 K

+ C HGRTC

2
1

GND
P C11

1 00K_0402_5%

P R G ++ 2

2
1

1
P R26

P C12

P C13
2

1
2

P R 27
2

2 2K_0402_1% P Q5
1 2 P R28 R H U 0 0 2 N 0 6 _ S OT 3 2 3 P R29
< 3 2 ,3 8 > 51ON#

1
P J1 3 4K_0402_1% D 4 7K_0402_5%
P A D - O P E N 3 x3 m PJ2 P A D - O P E N 3 x3 m 2 1 2 2 1
+ 1 .5 V S P 1 2 + 1 .5 V S 1 2 + 1 .8 V
RTCVREF G PACIN <41>
+ 1 .8 V P

1
S

3
6 6 .5 K _ 0 4 0 2 _ 1 %
1
(6A,240mils ,Via NO.=12) (6A,240mils ,Via NO.= 12)

P R 30
P J3 P J4 2 +5VALWP
P A D - O P E N 3 x3 m P A D - O P E N 3 x3 m @
+ 5 VALWP 1 2 + 5 VALW + 0 .9 V S P 1 2 + 0 .9 V S

2
P Q6

3
D T C 1 1 5 E UA _ S C7 0
(5A,200mils ,Via NO.= 10) (0.3A,40mils ,Via NO.= 2)
4 P J6 P J1 1 4

P A D - O P E N 3 x3 m P A D - O P E N 3 x3 m
+ 3 VALWP 1 2 + 3 VALW + 2 .5 V S P 1 2 + 2 .5 V S

(4.5A,180mils ,Via NO.= 9)

P J7 P J8 Security Classification Compal Secret Data Compal Electronics, Inc.
P A D - O P E N 3 x3 m P A D - O P E N 3 x3 m 2005/08/01 2006/08/01 T itle
Issued Date Deciphered Date
1 2 1 2
+ 1 .0 5 V S P +V CCP +VSBP +VSB
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN/DECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
S ize D o c u m e n t N u mb e r R ev
(5A,200mils ,Via NO.= 10) (0.3A,40mils ,Via NO.= 2) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0 .1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te : 星 期 一, 七月 31, 2006 S heet 39 of 48
A B C D
 A B C D

B A T T++ P L3
P JP 2 F B MA -L 1 8 -4 5 3 2 1 5 -9 0 0 L MA 9 0 T _ 1 812
PH1 under CPU botten side :
1 B A T T _S1 1 2 B A T T+
BATT+ P R 177 P R 178
CPU thermal protection at 85 degree C

1000P_0603_50V7K

1000P_0603_50V7K
1 K_0402_1% 4 7K_0402_5%
Recovery at 70 degree C

0 . 0 1 U_ 0 6 0 3 _ 5 0 V 7 K
2 A L I / N I M H# 1 2 1 2 + 3 VALWP

1
ID

P C 15
3 A B /I VS

1
B/I

P C 14

P C 16
4 TS_A
TS E C _ S MDA
5

2
1
SMD VL

1 K_0402_1%

0 . 1 U_ 0 6 0 3 _ 2 5 V 7 K
1 6 E C _ S MCA 1

2
SMC VL

P R 176
7

1
GND

P C 17

150K_0402_1%
@ S U Y I N _ 2 5 0 0 0 5 MR0 0 7 G1 6 1 Z L _ 7 P _ RV

2
1 00_0402_1%

1 00_0402_1%

2
1
P R31

P R32
P R35
P R34
P R 33 1 4 4 2 K _ 0 6 023 _ 1 %
A L I / M H#
1 0 .7 K _ 0 4 0 2 _ 1 %

1
P R36

2
6 .49K_0402_1%

8
1 2 P R37
+ 3 VALWP
16 1 .9 K _ 0 6 0 32_ 1 % 3

P
+
1
O M A I N P W O N < 3 9 ,4 2 >

1 K_0402_1%
T M _ RE F 1 2

G
- P U3A

P R38
L M 3 9 3 DG_ S O8

4
1 0 0 K _ 0 6 0 3 _ 1 % _ T H1 1 -4 H1 0 4 F T
1000P_0402_50V7K
2

1 U _ 0 6 0 3 _ 6 .3 V 6 M
B A T T _ TEMP <3 3 >

P C18

1
P H1

P C 19
P R39
E C _ S MB _ DA 1 < 3 3 ,3 4 >
2 1 5 0 K _ 0 4 012 _ 1 %VL

2
E C _ S MB _ CK 1 < 3 3 ,3 4 >

1 50K_0402_1%
1
P R40
2 2

2
PQ7
T P 0 6 1 0 K -T 1 -E 3 _ S OT23 VS
B+ 3 1 +V S B P
0 . 2 2 U_ 1 2 0 6 _ 2 5 V 7 K

0 . 1 U_ 0 6 0 3 _ 2 5 V 7 K
1

8
100K_0402_5%

1
P R41

P C20

P C21 5

P
+
7
O
6
2

G
P R42 -
2

2 2K_0402_1%

4
VL 1 2 P U3B
L M 3 9 3 DG_ S O8
1 00K_0402_5%
2
P R 43

3 3

P R44
1

0 _0402_5% D
1 2 2
< 42> S P OK G
0 . 1 U_ 0 4 0 2 _ 1 6 V 7 K

S P Q8
3
1

P C22

R H U 0 0 2 N 0 6 _ S OT 3 2 3
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/08/01 Deciphered Date 2006/08/01 T itle

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN. / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
S ize D o c u m e n t N u mb e r R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0 .1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te : 星 期 一, 七月 31, 2006 S heet 40 of 48

WWW.AliSaler.Com
A B C D
 A B C D E

65W PR45=0.02_2512_1% PR54=30K_0402_1% Iadp=0~3.125A

90W PR45=0.02_2512_1% PR54=20K_0402_1% Iadp=0~4.166A Fosc=14100/Rt=14100/47=300KHz Charger
B+ PQ11
P2
PQ9 PQ10 AO4407_SO8
AO4407_SO8 AO4407_SO8 1 8
8 1 1 8 1 2 2 7
P R45 PL4
VIN 7
6
2
3
2
3
7
6 0.02_2512_1% FBMA-L11-322513-201LMA40T_1210 CHG_B+ 3 6
5
5 5 1 2

4.7U_1206_25V6K

4
200K_0402_1%

0.1U_0603_25V7K
4.7U_1206_25V6K

2200P_0402_50V7K
1 1

4
1

1
PR46

PC23

PC24

1
PC25

PC26
0.1U_0603_25V7K
P2
1

47K_0402_5%

PR48

2
1
PR47

PC27
47K_0402_1%

2
1 2
VIN

10K_0402_1%
0_0603_5%
2

2
PR49
P U4

PR50
MB39A126PFV-ER_SSOP24
47K
1 24

3
2
1
2 P R51 PC28 PR52 -INC2 +INC2

2
47K
PQ12 10K_0402_1% 4700P_0402_25V7K 100K_0402_1%

1
D TA144EUA_SC70 M B39A126 1 2 1 2 2 1 2 23 AC OFF#
OUTC2 GND P C29 PQ13
4
0 .22U_0603_16V7K AO4407_SO8

1
3 22 CS 1 2
1

+INE2 CS
1

PC30

NA
0 .1U_0603_25V7K

10K_0402_1%

20K_0402_1%
0.01U_0402_25V7K
4 21 1 2
-INE2 VCC

1
2 AC O FF AC O FF <33,39>

5
6
7
8
1

PC31

PR53

PR54
2
5 20
ACOK OUT P C32
2

0 .1U_0603_25V7K PQ14
2

3
PQ15 6 19 1 2 D T C115EUA_SC70

LXCHRG
3

VREF VH
1

150K_0402_1%

0.22U_0603_16V7K
D T C115EUA_SC70
PR55
1

1
D
PC33 7 18 PL5
P R57 P C34 ACIN XACOK P R58 VIN 10U_LF919AS-100M-P3_4.5A_20%
2
G 1K_0402_1% 2200P_0402_50V7K 47K_0402_1% 1 2 1 2 BATT+
BATT+
2

2 S M B39A1261 2 1 2 8 17 1 2 PR56 2
3

-INE1 RT

47K_0402_5%
PQ16 0.02_2512_1%

1
R HU002N06_SOT323

PR59

B340A_SMA2

B340A_SMA2

4.7U_1206_25V6K

4.7U_1206_25V6K
4.7U_1206_25V6K
<33> IR E F 1 2 9 16
P R61 +INE1 -INE3 PR62 P C35

1
PC36

PC37

PC38
PR60 10K_0402_1% 33K_0402_1% 1500P_0603_50V7K

PD10

PD11
133K_0402_1% 2 1 10 15 M B39A126 1 21 2

2
1

D OUTC1 FB123
100K_0402_1%

2
1

2 0.01U_0402_25V7K
1
PR63

PC39

G 11 14
SEL CTL

47K_0402_5%
S PQ17 PC40
3

1
R HU002N06_SOT323 10P_0402_50V8J
2

PR64
12 13 1 2
2

1
-INC1 +INC1

0_0402_5%
PR65

2
PD12
RLS4148_LLDS2
AC OFF# 1 2 2

PR66
22K_0402_1% +3VALWP
<39> P AC IN 1 2 P C41
47K_0402_5%

CS 47P_0402_50V8J
1

IREF=0.932*Icharge 1 2
PR67

IREF=0.466~2.61V
<39> AC O N CC=2.8A
I fast charge=2.8A
2

3
(100K/(100K+133K))*2.61V=1.12V 3
2
LI-3S :13.05V----BATT-OVP=1.482V 1.12/(20*0.02)=2.8A
1

PQ18
BATT-OVP=0.111*BATT+
3

D TC115EUA_SC70
2 90W HGT30 CP Point=4.166A
<33> F S T CHG BATT+
5V*(10K/(30k+10k))=1.666V

499K_0402_1% 340K_0402_1%
1
PQ19 VS 1.666V/(20*0.02)=4.166A
3

PR68
D T C115EUA_SC70

0.01U_0402_25V7K
65W HGT31 CP Point=3.125A

2
1

PC42
5V*(10K/(30K+10K))=1.25V

1
PR69
1.25V/(20*0.02)=3.125A

2
5
VS +
<33> BATT_OVP 7
0
6
-

105K_0402_1%
1

0.01U_0402_25V7K
P U12B

1
PR72
LM358A_SO8
Charge voltage
8

PC43
3 3S CC-CV MODE : 12.6V
P

2
+
1

2
4 0 SEL is L 4
2
G

-
P U12A
4

LM358A_SO8

Security Classification Compal Secret Data Compal Electronics, Inc.

2005/08/01 2006/08/01 Title
Issued Date Deciphered Date
THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-Charger
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星 期 一 , 七 月 31, 2006 Sheet 41 of 48
A B C D E
 A B C D

B+

P L6
F B MA -L 1 1 -3 2 2 5 1 3 -2 0 1 L MA 4 0 T _ 1 210

P C45 P C 46
1

0 . 1 U_ 0 6 0 3 _ 2 5 V 7 K 0 . 1 U_ 0 6 0 3 _ 2 5 V 7 K

2
1 2 B S T 5B P D13 B S T 3B 1 2
P J 23
1 B +++ 1

S I 4 8 0 0 B DY -T 1 -E 3 _ S O8
2 1 B +++
2 2 0 0 P _ 0 4 0 2 _ 5 0 V 7K VL

8
7
6
5
1 0 U_ 1 2 0 6 _ 2 5 V A K
C H P 2 0 2 UP T _ S OT 3 2 3 -3
P A D - O P E N 3 x3 m

1
D
D
D
D
1

2
P C48

P Q 21

0 _0603_5%
MA X 8 7 4 3_B+
P C47

P R74

S I 4 8 0 0 B DY -T 1 -E 3 _ S O8
2 2 0 0 P _ 0 4 0 2 _ 5 0 V 7K
MA X 8 7 4 3_B+

4 7_0402_5%

0 . 1 U_ 0 4 0 2 _ 1 6 V 7 K

1 0 U_ 1 2 0 6 _ 2 5 V A K
2

5
6
7
8
S
S
S

P R 75
4 .7 _ 1 2 0 6 _ 5 %

4 .7 _ 1 2 0 6 _ 5 %

1
P R76

P R77

P C49
P R78

D
D
D
D
1
2
3
4

P C50

P C51

P Q 20
0 _0603_5%

2
5HG 1 2 D H5

2
2

G
S
S
S
LX5

S I 4 8 1 0 B DY -T 1 -E 3 _ S O8
@

4
3
2
1
8
7
6
5

2
P C52

0 _0603_5%
1 U _ 0805_25V4Z

0 . 1 U_ 0 6 0 3 _ 2 5 V 7 K

P R79
VL 3HG

D
D
D
D
P Q2 9
LX3

2
2VREF_1999
4 . 7 U H _ P C M C 0 6 3 T -4 R7 MN_ 5 .5 A _ 2 0 %

5
6
7
8
1 P C55

2 00K_0402_1%

3 74K_0402_1% 2 00K_0402_1%

S I 4 8 1 0 B DY -T 1 -E 3 _ S O8
4 . 7 U _ 0 8 0 5 _ 6 .3 V 6 K

1
G

2
S
S
S

P R80

P R81
1 U _0805_16V7K

D
D
D
D
1

P C53
1
2
3
4

P Q3 0
B S T 3A

P C 54

G
S
S
S
0 _0603_5%
D L5

P R82

4
3
2
1
2

18

20

13

17

2
3 74K_0402_1%
P R 83

P R 84
PL7

B S T 5A 14

LD05

TON

VCC
V+

1
BST5
2 5 2
ILIM3

4 . 7 U H _ P C M C 0 6 3 T -4 R7 MN_ 5 .5 A _ 2 0 %
16 D L3
DH5
+5VALWP
1

2
15
19 LX5 11
DL5 ILIM5

P L8
21
OUT5 P U6
9 28
FB5 BST3
1 0 .2 K _ 0 4 0 2 _ 1 %

1 26 D H3
2

N.C.MA X 8 7 3 4 A E E I+_ QS OP 2 8 DH3

24

1
DL3
1 5 0 U _ V _ 6 .3 V M_ R1 8

P R 85

6 27
VS SHDN# LX3
1 4 22
ON5 OUT3
1 2 3
ON3
P C56

+ P R86 7
1

@ 0 _0402_5% FB3
12
SKIP# PGOOD
2 +3VALWP
2 2VREF_19998

@ 3 .57K_0402_1%
PRO#
P ZD1 P R88

LDO3
GND
2

2
REF
0 _0402_5%

R L Z 5 .1 B _ L L 3 4 4 7K_0402_5% P R89
P R87

1 2 1 2 10 _ 0 4 0 2 _ 5 %2

1 5 0 U _ V _ 6 .3 V M_ R1 8
23

25

10

P R 90
0 . 0 4 7 U_ 0 6 0 3 _ 1 6 V 7 K

0 . 2 2 U_ 0 6 0 3 _ 1 6 V 7 K
1
1 00K_0402_5%

4 . 7 U _ 0 8 0 5 _ 6 .3 V 6 K
1

1
2

P C59
+

2
P R91

P C57

0 _0402_5%
S P OK
2

2
2

P C 58
0 _0402_5%
<4 0 >

2
P C60

P R92
1

P R93
P R94
+5V Ipeak = 6.5A ~ 10.4A

1
4 7K_0402_5%
1 2
0 . 0 4 7 U_ 0 6 0 3 _ 1 6 V 7 K

3 3

1
1

P C61
2

+3.3V Ipeak = 6.5A ~ 8.26A

M A I N P W O N < 3 9 ,4 0 >
1 U _ 0 6 0 3 _ 6 .3 V 6 M
1

P C62
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/08/01 Deciphered Date 2006/08/01 T itle

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+5VALWP/+3VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
S ize D o c u m e n t N u mb e r R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C u s to m 0 .1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te : 星 期 一, 七月 31, 2006 S heet 42 of 48

WWW.AliSaler.Com
A B C D
 5 4 3 2 1

+1.8VP Ilimit = 7.87A~12.5A

+1.05VSP Ilimit=6.33A~10.03A

D D

O Z813A_B+ OZ813_B+

PL9
P J25
FBMA-L11-322513-201LMA40T_1210
2 1 1 2 B+

10U_1206_25VAK
+ 3VALW P
P AD-OPEN 3x3m

SI4800BDY-T1-E3_SO8

1
1K_0402_1%
1.8VS2N

PC63
1

8
7
6
5
1.8VS2P

PR261

D
D
D
D

2
PQ22
P R262
0_0402_5%
1 2

G
S
S
S
PL10
+5VALW P 3 . 3 UH_PCMC063T-3R3MN_6A_20%28mohm

1
2
3
4
PR266 DH_1.8V 1 2 +1.8VP
0_0402_5% 1.8VSET

1
LX_1.8V

220U_D2_4VM_R15
2 1

1
<33,35,37> S YS O N

51_0402_1%
1

8
7
6
5

PR95
0.01U_0402_25V7K
P C65
1

0.1U_0603_25V7K
+
PC184

PC66
1000P_0402_50V7K P R97 P R98

D
D
D
D
2
100K_0402_1% 22K_0402_1%

2
1
PQ23 1 2 1 2
2

PC67
SI4810BDY-T1-E3_SO8 PC68

G
S
S
S
P U7 6800P_0402_25V7K

25

24
23
22
21
20
19

DL_1.8V
2
C 1.8VS2P 1 2 C

1
2
3
4
2

2
22_0402_1%

1K_0402_1%

CS2N
VSET2

PGD2
LX2
HDR2
GNDA

CS2P
PR99

PR100
@
RB751V-40TE17_SOD323-2
1.8VS2N

4700P_0402_25V7K
P D16
P R101 1 18 BST_1.8V 1 2

1
ON/SKIP2 BST2

1
22P_0402_50V8J
PC69

PC70
0_0402_5% 2 17
DREF VIN LDR2
2 1 3 16 +5VALW P
VREF VDDP
4 15

2
TSET GDNP

1
0.022U_0402_16V7K

0.1U_0603_25V7K

5 14
2

VDDA LDR1
24K_0402_1%

100K_0402_1%
6 13 PC71 +5VALW P
ON/SKIP1 BST1
1

0.01U_0402_25V7K
1U_0603_6.3V6M
PR103

PC72

PC73

PC74
1 U_0805_16V7K
OZ813LN_QFN24

2
PR104

PC75

VSET1

PGD1
CS1N

HDR1
CS1P
2

LX1
P D17
1

BST_1.05V 1

2.2U_0603_6.3V6K
P R105 2
1

@ 75K_0402_1% OZ813A_B+

7
8
9
10
11
12

1
RB751V-40TE17_SOD323-2

PC156
P C76

0_0402_5%
0 .1U_0603_25V7K

2
1.8VSET

PR263

2
DH_1.05V PL11
3 . 3 UH_PCMC063T-3R3MN_6A_20% 28mohm
2

1.05SET LX1.05V 1 2 +1.05VSP

1
2
150K_0402_1%

1
DL_1.05V

51_0402_1%
1.05VS1P
PR106

PR172

PR107
61.9K_0402_1%

220U_D2_4VM_R15
P C77 1
1000P_0402_50V7K 1.05VS1N
1

PC78
P R108 PR109
1

5
6
7
8

SI4800BDY-T1-E3_SO8
100K_0402_1% 29.4K_0402_1%

2
10U_1206_25VAK
1 2 1 2

D
D
D
D
1

1
2

1K_0402_1%
P C80
B
PR264

PC79
5600P_0402_50V7K B
1.05VS1P

PQ24
2 1

2
G
S
S
S
PR179
2

4
3
2
1
100K_0402_1%
1.05VS1N

4700P_0402_25V7K
1 2
<18,24,26,33,34,35,37,44> S USP#
1

1
22P_0402_50V8J
PC81

PC82
+3VALW P
P C132

5
6
7
8

SI4810BDY-T1-E3_SO8
0 . 1U_0402_16V7K
2

2
D
D
D
D
PQ31
G
S
S
S
4
3
2
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2005/08/01 2006/08/01 Title
Issued Date Deciphered Date
1.05VSP/1.8VP
THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C u s tom 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星期一, 七月 31, 2006 Sheet 43 of 48
5 4 3 2 1
 5 4 3 2 1

+1.5VSP Ilimit = 9.38A~12.5A

D PL12 D

B+
1 2 2 1

10U_1206_25VAK
FBMA-L11-322513-201LMA40T_1210
P H ASE_VCCPP

1
P J27 PR265
P AD-OPEN 3x3m 10K_0402_1% UG_ VCCPP

PC83
1 2

2
1 2 1 2
PR110 PC85
0_0603_5% 0 .1U_0402_16V7K
+5VS

1
BOOT_VCCPP
P R111
@ 4.7_0603_5%

5
6
7
8
17

16

15

14

13

D
D
D
D
2
1 P R1122 6 2 69_VCC

GND

PGOOD

UG

BOOT
PHASE
4.7_0603_5%
PQ26

G
S
S
S
1 12 1 2 SI4800BDY-T1-E3_SO8
VIN PVCC P C86

4
3
2
1
2 . 2U_0603_6.3V6K

6 2 69_VCC 2 11 L G _VCCPP
VCC LG
1 2 +1.5VSP

1
PL13
P C87 1 2 3 10 3 . 3 UH_PCMC063T-3R3MN_6A_20% 1
FCCM PGND

5
6
7
8
2 . 2U_0603_6.3V6K P R113

2
0_0402_5% + P C88

D
D
D
D
C 2 2 0 U_D2_4VM_R15 C
1 2 4 9 IS E 1N_VCCPP 2
<18,24,26,33,34,35,37,43> S USP# P R114 EN ISEN PR115 PQ27 2

G
COMP

S
S
S
FSET
47K_0402_5% 8.66K_0402_1% SI4810BDY-T1-E3_SO8
1

VO
FB

4
3
2
1
P C89
0 .01U_0402_25V7K
2

8
P U8
IS L6269CRZ-T_QFN16

1
22P_0402_50V8J
1
P R116 PC90
PC91

49.9K_0402_1% 0 .01U_0402_25V7K

2
P R117
2

2
57.6K_0402_1%

1
P C92
6800P_0402_25V7K
2
1 2
PR118
4.53K_0402_1%

1
P R119
3K_0402_1% +1.8VP

B +3VS B
2

1
1
+5VS
1

P J9

2
J UMP_43X118
1

2
P J10
1

JUMP_43X79 P U9
P C93 1 6 +3VALW P
2

1 U_0603_6.3V6M VIN VCNTL

2

2 5
GND NC

1
6

1
PC94 3 7 PC95
5 P C96 1 0U_1206_6.3V7K VREF NC 1 U_0603_6.3V6M
VCNTL

2
VIN 1 0U_1206_6.3V7K PR120
7 4 8
2

POK 1K_0402_1% VOUT NC

4
VOUT
9

2
TP
3 +2.5VSP
VOUT
0.01U_0402_25V7K

1
1

2.15K_0402_1%

10U_1206_6.3V7K

1 2 8 2 APL5331KAC-TRL_SO8
EN FB
1

<18,24,26,33,34,35,37,43> S USP#

0.1U_0402_16V7K
+
+0.9VSP
GND

1
PR121 P C98 D
9
VIN
1

1
PR122

33K_0402_1% @ 1 5 0 U_D_6.3VM 1 2 2
2

1
2 <35> S USP
PC99

PC97

0.1U_0402_16V7K
P C100 PR123 G PR124
1

0 .01U_0402_25V7K P U10 100K_0402_1% S 1K_0402_1%

2

2
1

PC101
APL5912-KAC-TRL_SO8 PQ28 PC102

2
1

R HU002N06_SOT323 1 0U_1206_6.3V7K
PC103
2

PR125
1K_0402_1%
A A
2

Security Classification Compal Secret Data Compal Electronics, Inc.

2005/08/01 2006/08/01 Title
Issued Date Deciphered Date
+VCCPP/+2.5VSP/0.9VSP
THISSHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size D oc um ent Num ber R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C u s tom 0 .1
MAYBEUSED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: 星期一, 七月 31, 2006 Sheet 44 of 48
5 4 3 2 1

WWW.AliSaler.Com
 5 4 3 2 1

+5VS

CPU_B+ B+
PR214 PL14
5VS12 1 FBM-L11-322513-201LMAT_1210
2 1

0.01U_0402_25V7K
0_1206_5%

0.1U_0603_25V7K

2200P_0402_50V7K
1

100U_25V_M
PC157
PR215

1
10U_1206_25VAK

10U_1206_25VAK

10U_1206_25VAK
+

PC158
10_0402_5%

200K_0402_5%

PC159

PC160

PC161

PC162

PC163
2

2
2 PR216 1

2
D D

2
PC164 2

2
2.2U_0603_6.3V6K

2
PR217 PC165

1
@ 13K_0402_1% 1U_0603_6.3V6M

5
PU11

1
NTC
VCC 19 25
Vcc VDD
4 4
1 2 PR218 6 8
100K_0402_5% THRM TON

<5> CPU_VID0 2 1 PR219 31 30 BST1_CPU 1 2 BSTM1_CPU 1 2

0_0402_5% D0 BST1 PR220 PC166 PQ32 PQ39 +CPU_CORE

3
2
1

3
2
1
2 1 PR221 32 29 DH1__CPU0_0402_5% 1 2 0.22U_0603_16V7KDH1A__CPU @ SI7840DP_SO8 SI7840DP_SO8 PL15
<5> CPU_VID1 D1 DH1
0_0402_5% PR268 P_0.36H_ETQP4LR36WFC_24A_20%
2 1 PR222 33 28 LX1__CPU 2.2_0603_5% 2 1 +CPU_CORE
<5> CPU_VID2 D2 LX1
0_0402_5%

4.7_1206_5%
<5> CPU_VID3 2 1 PR223 34 26 DL1__CPU

5
6
7
8

5
6
7
8

2
0_0402_5% D3 DL1

FDS6676AS_SO8

FDS6676AS_SO8
2 1 PR225 35 27 PR226

D
D
D
D

D
D
D
D
<5> CPU_VID4 D4 PGND1

PQ33

PQ34

PR224
0_0402_5% 2.1K_0402_1%
2 1 PR227 36 18

2
<5> CPU_VID5

1
0_0402_5% D5 GND

1
G

G
S
S
S

S
S
S
1 2 PR228 37 17 CSP1__CPU PR230 NTC PR229
<5> CPU_VID6 D6 CSP1

680P_0603_50V7K
0_0402_5% 3.48K_0402_1% 10_0402_5%

4
3
2
1

4
3
2
1

1
PR232 2 1 7 16 CSN1_CPU 1 2 1 2
71.5K_0402_1% TIME CSN1 PH2 VCCSENSE

2
PC168 2 1 9 12 FB_CPU 10KB_0603_5%_ERTJ1VR103J

2
CCV FB

PC167
470P_0402_50V8J
1 2 11 10 C CI_CPU 1 2
C PC170 REF CCI PC169 C

<7,21> DPRSLPVR 1 2 PR233 0.22U_0603_16V7K 39 21 DH2_CPU 0.22U_0603_16V7K

499_0402_1% DPRSLPVR DH2

2
1 2 PR234 40 20 BST2_CPU
<4,20> H_DPRSTP# DPRSTP BST2
0_0402_5% 2 1 PR235
1 2 PR236 3 22 LX2_CPU PC185 PR237 0_0402_5% 0_0402_5%
<5> H_PSI# PSI LX2
0_0402_5% @ 180P_0402_50V8J 1 2
+3VS 2 24 DL2__CPU 2 1

1
PWRGD DL2 PC186

2
1 23 @ 180P_0402_50V8J
1 2 1 2 CPU_VCC_SENSE
CLKEN PGND2 PR238 PC171
2

0_0402_5%
38 14 CSP2_CPU @ 3K_0603_1% @ 0.022U_0402_16V7K
PR241 SHDN CSP2
1 2 1 2

PR239
PR244 PR240 @ 2K_0402_1% 5 15 CSN2__CPU PR242 PR243

1
0_0402_5% 2.1K_0402_1% VRHOT CSN2 3.65K_0402_1% 100_0402_5%

2
4 13
1

POUT GNDS PC172

1 2 1 2 1 2

BSTM2_CPU
<21> VGATE

1000P_0402_50V7K
PR245 PR246 4700P_0402_25V7K

1
TP @ 3K_0603_1% @ 3K_0603_1%

2
1 2
<15> CLK_ENABLE# PR247 MAX8770GTL+_TQFN40
41

@ 0_0402_5% 1 2 1 2
1
PC174
1 2 PR248 PC173
<33> V R_ON
PR249 20K_0402_1% 470P_0402_50V8J
2

0.22U_0603_16V7K
0_0402_5% CPU_B+
1

1
D +3VS 2
2 PR250
1

G @ 10K_0402_5% PR251

10U_1206_25VAK

10U_1206_25VAK

10U_1206_25VAK

0.1U_0603_25V7K

2200P_0402_50V7K
S PR252 100_0402_5%
3

PC175
PQ38 56_0402_5%

1
PC176

PC177
RHU002N06_SOT323
1

PC178

PC179

PC180
B B
2

1 2 VSSENSE

2
<4> H_PROCHOT# PR253 <5> VSSENSE 4 4
@ 0_0402_5%
1

1 2 PR255
POUT
PR254 @10_0402_5% PQ40 PQ35

3
2
1

3
2
1
2

10K_0402_5% 1 2DH2A_CPU @ SI7840DP_SO8 SI7840DP_SO8

PC181 PR267
2

0.1U_0402_16V7K 2.2_0603_5% 2 1
1

PL16
P_0.36H_ETQP4LR36WFC_24A_20%

4.7_1206_5%
5
6
7
8

5
6
7
8

1
FDS6676AS_SO8

FDS6676AS_SO8

PR256
D
D
D
D

D
D
D
D
PQ37

PQ36

2
PR257
2.1K_0402_1%

G
S
S
S

S
S
S

680P_0603_50V7K

2
4
3
2
1

4
3
2
1

1
DL2__CPU

2
PC182
1 2 NTC1 2
PR258 PH3
3.48K_0402_1% 10KB_0603_5%_ERTJ1VR103J

1 2
2 1 PC183
A PC187 0.22U_0603_16V7K A
@ 180P_0402_50V8J 1 2
2 1 PR260
PC188 0_0402_5%
@ 180P_0402_50V8J

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C ustom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: 星期一 , 七 ?31, 2006 Sheet 45 of 48
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Fixed Issue Reason for change Rev. P G# Modify List VER Phase

D
1 D
MODIFY 3V/5V current limit to 6.5A~8.1A/6.5A to 10.2A 42 MODIFY PR83/PR84 FROM 499K TO 374K DVT

Reserve PR224//PR256: 4.7 1206 ,add

2 ADD or decrease CPU CORE ring with EMI solution : 45
PC167/PC182:680P
DVT
snubber
Reserve PR267,PR268 seperate in CPU CORE high
3 side gate for EMI require
45 Reserve PR267,PR268:0 0603 DVT
4 change PJP1 from 5 pin to 4 pin 39
change PJP1 from 5 pin to 4 pin DVT

5 modify sequecce
43
change PR179 to 100k, PC132 =0.1U
DVT

6 modify Vgate 45 add PQ38:RHU002N06,PR240:2K,delete PR247

7
C C
Prevent noise interference cpu_core feedback 45 Reserve PC185, PC186, PC187, PC188

10

11

B B

A A

Compal Electronics, Inc.

T itle
PIR (PWR)
S ize D o c u m e n t Nu mb e r R ev
0 .2

D a te: 星 期一, 七月 31, 2006 Sheet 46 of 48

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5 4 3 2 1
 A B C D E

Version change list (P.I.R. List) Page 1 of 1

I tem Fixed Issue Rev. PG# Modify List B.Ver# P hase

1 1
1 PC Beep modify 0.2 29 Modify C714 from 0603 to 0402
0.2 DVT

2 Head Phone no sense

0.2 29 Add R892 for Audio channel B use
0.2 DVT
3 PC BEEP FOR DOS MODE
0.2 29 Change 1u to 680p

4 CIR for ALW power 0.2 32 Add R893 for CIR 0.2 DVT

5 To prevent voltage feedback to +3VS from KB_RST# 0.2 33 Add D812

0.2 DVT
6 EAPD change to AC_RST_AUDIO# 0.2 29 Change R458

0.2 DVT
7

2 2

0.2 DVT

0.2 DVT

3 3

8 0.2 DVT

9 0.2 DVT

10
0.2 DVT

0.2 DVT
11

4 4

Compal Electronics, Inc.

T itle
PIR
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
S ize D o c u m e n t N u mb e r R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
HGT30/31 LA-3061 0 .0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te : 星 期 @, 七月 31, 2006 S heet 47 of 48
A B C D E
 A B C D E

Version change list (P.I.R. List) Page 1 of 1

I tem Fixed Issue Rev. PG# Modify List B.Ver# P hase

1 1

12 0.3 PVT

13 0.3 PVT

14 0.3 PVT

15 0.3
PVT

2 2
16 0.3 PVT

3 3

4 4

Compal Electronics, Inc.

T itle
PIR
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
S ize D o c u m e n t N u mb e r R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
HGT30/31 LA-3061 0 .0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te : 星 期 @, 七月 31, 2006 S heet 48 of 48
A B C D E