A B C D E

1 1

Compal Confidential
2 2

KAL90/KALH0 M/B Schematics Document

Intel Penryn Processor with Cantiga + DDRII + ICH9M

3 2008-12-17 3

REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Wednesday, December 17, 2008 Sheet 1 of 52
A B C D E
 A B C D E

Compal Confidential
Intel Penryn Processor Thermal Sensor Clock Generator
Fan Control
Model Name : KAL90/KALH0 page 40
EMC 1402 ICS9LPRS387
uPGA-478 Package page 4 page 16

(Socket P) page 4,5,6

1 1
FSB
H_A#(3..35) 667/800/1066MHz H_D#(0..63)

HDMI Conn. LCD Conn. CRT Conn.

page 24 page 22 page 23
Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
Intel Cantiga
LVDS Dual Channel BANK 0, 1, 2, 3 page 14,15

1.8V DDRII 533/667

TMDS LVDS uFCBGA-1329
PCI-Express page 7,8,9,10,11,12,13
Card Reader 16X
JMB385 VGA USB conn x3 Bluetooth CMOS LS-4494P
page 30 DMI C-Link Finger Print
page 17,18,19,20,21 USB port 0, 2, 5 Conn Camera
page 33 page 34 page 22 AES1610

PCI-Express
2
Intel ICH9-M 3.3V 48MHz USB
2

3.3V 24.576MHz/48Mhz HD Audio

S-ATA
BGA-676
LAN(GbE) MINI Card x2 New Card page 25,26,27,28
ATHEROS AR8121 WLAN, Robson2 Socket
page 31 page 33 page 34 GMCH HDA MDC 1.5 HDA Codec VGA HDA
Conn ALC888S-VC
port 2 port 1 port 0 page 08 page 37 page 38 page 18

RJ45 ESATA CDROM SATA HDD

page 32
Conn.
page 34
Conn.
page 29
Conn.
page 29 Audio AMP
page 39
LPC BUS
3 3

ENE KB926 Phone Jack x3

page 35 page 39

RTC CKT. KAL90

page 37
LS-4493P Touch Pad Int.KBD
page 36 page 36
Media/B Conn. KALH0
Power On/Off CKT.
page 37 LS-4498P LS-4495P EC I/O Buffer BIOS
FUN Conn. USB/B Conn. page 36 page 36
DC/DC Interface CKT. USB port 1
page 44
LS-4492P
LS-5042P
E_KEY/B Conn. LED/B Conn. CIR
Power Circuit DC/DC LS-4495P page 37
LS-5041P
4
page 44,45,46,47,48 ,49,50,51 USB/B Conn. Media/B Conn.
4

USB port 1

POWER SW
Page 42
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 2 of 52
A B C D E
 A B C D E

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF
+1.25VS 1.25V switched power rail ON OFF OFF
+1.5V 1.5V power rail for HDA ON ON OFF Board ID / SKU ID Table for AD channel
+1.5VS 1.5V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+1.8V 1.8V power rail for DDR ON ON OFF Ra/Rc/Re 100K +/- 5%
+1.8VS 1.8V switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.1VS 1.1V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+3VALW 3.3V always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3V 3.3V power rail for SB ON ON X 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3V_LAN 3.3V power rail for LAN ON ON X 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3VS 3.3V switched power rail ON OFF OFF 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VALW 5V always on power rail ON ON ON* 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+5VS 5V switched power rail ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+VSB VSB always on power rail ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
2 2
+RTCVCC RTC power ON ON ON
+VGA_CORE Core voltage for GPU ON OFF OFF
BOARD ID Table BTO Option Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Board ID PCB Revision BTO Item BOM Structure
External PCI Devices 0 0.1 KAL90 JAL90@
1 0.2 UMA GM@
Device IDSEL# REQ#/GNT# Interrupts
2 0.3 PM@ PM@
3 1.0 ALC888VC 888VC@
4 1A ALC888VB 888VB@
5 AR8121 8121@
6 AR8112 8112@
7 ALC268 268@
GL40 GL40@
GM45 GM45@
EC SM Bus1 address EC SM Bus2 address
3 3
Device Address Device Address
Smart Battery 0001 011X b ADI ADT7421 1001 100X b
MEDIA CONSOLE 1010 000X b NB9M THERMAL SENSOR

BOM Configuration Table

ICH9M SM Bus address Project BOM Configuration
KAL90-UMA XXXXXXXXXX:KAL90@/GM@/888VC@/8121@/GM45@
Device Address KAL90-Dis XXXXXXXXXX:KAL90@/PM@/888VC@/8121@
Clock Generator 1101 001Xb
KAL90-GM45 XXXXXXXXXX:KALH0@/GM@/888VC@/8121@/GM45@
(ICS9LPRS387, SLG8SP556V) KAL90-GL40 XXXXXXXXXX:KALH0@/GM@/888VC@/8121@/GL40@
DDR DIMM0 1001 000Xb KAL90-PM45 XXXXXXXXXX:KALH0@/PM@/888VC@/8121@
DDR DIMM2 1001 010Xb

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 3 of 52
A B C D E
 5 4 3 2 1

H_A#[3..35]
<7> H_A#[3..35]
H_REQ#[0..4]
<7> H_REQ#[0..4]
H_RS#[0..2]
<7> H_RS#[0..2]
JCPU1A
H_A#3 J4 H1 H_ADS# <7>
A[3]# ADS#

ADDR GROUP_0
H_A#4 L5 E2 H_BNR# <7>
H_A#5 A[4]# BNR#
D L4 A[5]# BPRI# G5 H_BPRI# <7> D
H_A#6 K5
H_A#7 A[6]#
M3 A[7]# DEFER# H5 H_DEFER# <7>
H_A#8 N2 F21
A[8]# DRDY# H_DRDY# <7>
H_A#9 J1 E1
A[9]# DBSY# H_DBSY# <7>
H_A#10 N3
H_A#11 A[10]#
P5 A[11]# BR0# F1 H_BR0# <7>
H_A#12 P2 A[12]#

CONTROL
H_A#13 L2 D20 H_IERR#
H_A#14 A[13]# IERR#
P4 A[14]# INIT# B3 H_INIT# <26>
H_A#15 P1
H_A#16 A[15]#
R1 A[16]# LOCK# H4 H_LOCK# <7>
<7> H_ADSTB#0 M1 ADSTB[0]#
C1 H_RESET# H_RESET# <7>
H_REQ#0 RESET# H_RS#0
K3 REQ[0]# RS[0]# F3
H_REQ#1 H2 F4 H_RS#1
H_REQ#2 REQ[1]# RS[1]# H_RS#2
K2 REQ[2]# RS[2]# G3
H_REQ#3 J3 G2 H_TRDY# <7>
H_REQ#4 REQ[3]# TRDY#
L1 REQ[4]#
HIT# G6 H_HIT# <7>
H_A#17 Y2 E4
A[17]# HITM# H_HITM# <7>
H_A#18 U5
H_A#19 A[18]#
R3 A[19]# BPM[0]# AD4

ADDR GROUP_1
H_A#20 W6 AD3
H_A#21 A[20]# BPM[1]#
U4 A[21]# BPM[2]# AD1
H_A#22 Y5 AC4
H_A#23 A[22]# BPM[3]#
U1 AC2
XDP/ITP SIGNALS
H_A#24 A[23]# PRDY# XDP_BPM#5
R4 A[24]# PREQ# AC1
H_A#25 T5 AC5 XDP_TCK
C H_A#26 A[25]# TCK XDP_TDI C
T3 A[26]# TDI AA6
H_A#27 W2 AB3
H_A#28 A[27]# TDO XDP_TMS
W5 A[28]# TMS AB5
H_A#29 Y4 AB6 XDP_TRST#
H_A#30 A[29]# TRST# XDP_DBRESET#
U2 A[30]# DBR# C20 XDP_DBRESET# <27>
H_A#31 V4
H_A#32 A[31]# +1.05VS
W3 A[32]#
H_A#33 AA4 THERMAL
H_A#34 A[33]#
AB2 A[34]#
H_A#35 AA3 D21 H_PROCHOT#
A[35]# PROCHOT# H_THERMDA
<7> H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
B25 H_THERMDC XDP_TDI R2 1 2 54.9_0402_1%
THERMDC
<26> H_A20M# A6 A20M#
ICH

<26> H_FERR# A5 FERR# THERMTRIP# C7 H_THERMTRIP# <8,26> left NC if no ITP

<26> H_IGNNE# C4 IGNNE# XDP_TMS R3 1 2 54.9_0402_1% 39Ohm
<26> H_STPCLK# D5 STPCLK#
C6 H CLK XDP_BPM#5 R5 1 @ 2 54.9_0402_1%
<26> H_INTR LINT0
<26> H_NMI B4 LINT1 BCLK[0] A22 CLK_CPU_BCLK <16>
<26> H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# <16>
M4 H_PROCHOT# R13 2 1 56_0402_5%
RSVD[01]
N5 RSVD[02]
T2 H_IERR# R18 2 1 56_0402_5%
RSVD[03]
V3 RSVD[04]
B2 Layout Note:
RESERVED

RSVD[05]
D2 RSVD[06]
D22 H_THERMDA&H_THERMDC Trace / Space = 10 / 10 mil
RSVD[07]
D3 RSVD[08]
B XDP_TRST# R7 54.9_0402_1% B
F6 RSVD[09] 2 1

XDP_TCK R8 1 2 54.9_0402_1%

Penryn

CONN@
+3VS
C2
0.1U_0402_16V4Z
1 2

+1.05VS U1
BSEL2 BSEL1 BSEL0 BCLK H_THERMDA

0 0 0 266 1 VDD SMCLK 8 EC_SMB_CK2 <18,35,36>

1

1
R17 @ C3 2 7
DP SMDATA EC_SMB_DA2 <18,35,36>
0 1 0 200 56_0402_5%
2200P_0402_50V7K 3 DN ALERT# 6 1 2 +3VS
2 R1133
2

0 1 1 166 4 5 10K_0402_5%
H_THERMDC THERM# GND
2
B
E

A
H_PROCHOT# 3 1 OCP# <27> EMC1402-1-ACZL-TR_MSOP8 A
C

Q1
MMBT3904_SOT23-3
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn (1/3)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 4 of 52
5 4 3 2 1
 5 4 3 2 1

H_D#[0..63] JCPU1C
H_D#[0..63] <7>
+CPU_CORE A7 VCC[001] VCC[068] AB20 +CPU_CORE
JCPU1B A9 AB7
H_D#0 H_D#32 VCC[002] VCC[069]
E22 D[0]# D[32]# Y22 A10 VCC[003] VCC[070] AC7
D H_D#1 F24 AB24 H_D#33 A12 AC9 D
H_D#2 D[1]# D[33]# H_D#34 VCC[004] VCC[071]
E26 D[2]# D[34]# V24 A13 VCC[005] VCC[072] AC12

DATA GRP 0
H_D#3 G22 V26 H_D#35 A15 AC13
D[3]# D[35]# VCC[006] VCC[073]

DATA GRP 2
H_D#4 F23 V23 H_D#36 A17 AC15
H_D#5 D[4]# D[36]# H_D#37 VCC[007] VCC[074]
G25 D[5]# D[37]# T22 A18 VCC[008] VCC[075] AC17
H_D#6 E25 U25 H_D#38 A20 AC18
H_D#7 D[6]# D[38]# H_D#39 VCC[009] VCC[076]
E23 D[7]# D[39]# U23 B7 VCC[010] VCC[077] AD7
H_D#8 K24 Y25 H_D#40 B9 AD9
H_D#9 D[8]# D[40]# H_D#41 VCC[011] VCC[078]
G24 D[9]# D[41]# W22 B10 VCC[012] VCC[079] AD10
H_D#10 J24 Y23 H_D#42 B12 AD12
H_D#11 D[10]# D[42]# H_D#43 VCC[013] VCC[080]
J23 D[11]# D[43]# W24 B14 VCC[014] VCC[081] AD14
H_D#12 H22 W25 H_D#44 B15 AD15
H_D#13 D[12]# D[44]# H_D#45 VCC[015] VCC[082]
F26 D[13]# D[45]# AA23 B17 VCC[016] VCC[083] AD17
H_D#14 K22 AA24 H_D#46 B18 AD18
H_D#15 D[14]# D[46]# H_D#47 VCC[017] VCC[084]
H23 D[15]# D[47]# AB25 B20 VCC[018] VCC[085] AE9
<7> H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 <7> C9 VCC[019] VCC[086] AE10
<7> H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 <7> C10 VCC[020] VCC[087] AE12
<7> H_DINV#0 H25 DINV[0]# DINV[2]# U22 H_DINV#2 <7> C12 VCC[021] VCC[088] AE13
C13 VCC[022] VCC[089] AE15
C15 VCC[023] VCC[090] AE17
H_D#16 N22 AE24 H_D#48 C17 AE18
H_D#17 D[16]# D[48]# H_D#49 VCC[024] VCC[091]
K25 D[17]# D[49]# AD24 C18 VCC[025] VCC[092] AE20
H_D#18 P26 AA21 H_D#50 D9 AF9
H_D#19 D[18]# D[50]# H_D#51 VCC[026] VCC[093]
R23 D[19]# D[51]# AB22 D10 VCC[027] VCC[094] AF10
H_D#20 L23 AB21 H_D#52 D12 AF12
D[20]# D[52]# VCC[028] VCC[095]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D14 AF14
D[21]# D[53]# VCC[029] VCC[096]

DATA GRP 3
H_D#22 L22 AD20 H_D#54 D15 AF15
H_D#23 D[22]# D[54]# H_D#55 VCC[030] VCC[097]
M23 D[23]# D[55]# AE22 D17 VCC[031] VCC[098] AF17
H_D#24 P25 AF23 H_D#56 D18 AF18
C H_D#25 D[24]# D[56]# H_D#57 VCC[032] VCC[099] C
P23 D[25]# D[57]# AC25 E7 VCC[033] VCC[100] AF20
+1.05VS H_D#26 P22 AE21 H_D#58 E9
H_D#27 D[26]# D[58]# H_D#59 VCC[034]
T24 D[27]# D[59]# AD21 E10 VCC[035] VCCP[01] G21 +1.05VS
H_D#28 R24 AC22 H_D#60 E12 V6
H_D#29 D[28]# D[60]# H_D#61 VCC[036] VCCP[02]
L25 D[29]# D[61]# AD23 E13 VCC[037] VCCP[03] J6
2

H_D#30 T25 AF22 H_D#62 E15 K6

R27 H_D#31 D[30]# D[62]# H_D#63 VCC[038] VCCP[04]
N25 D[31]# D[63]# AC23 E17 VCC[039] VCCP[05] M6
1K_0402_1% <7> H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 <7> E18 VCC[040] VCCP[06] J21
<7> H_DSTBP#1 M26 DSTBP[1]# DSTBP[3]# AF24 H_DSTBP#3 <7> E20 VCC[041] VCCP[07] K21
<7> H_DINV#1 N24 AC20 H_DINV#3 <7> F7 M21
1

DINV[1]# DINV[3]# VCC[042] VCCP[08]

Trace Close CPU < 0.5' GTL_REF0 COMP0 R26 27.4_0402_1%
F9 VCC[043] VCCP[09] N21
AD26 GTLREF COMP[0] R26 1 2 F10 VCC[044] VCCP[10] N6
Width=4 mil , R21 2 @ 1 1K_0402_5% TEST1 C23 MISC U26 COMP1 R25 1 2 54.9_0402_1% F12 R21
R22 @ 1K_0402_5% TEST2 TEST1 COMP[1] COMP2 R24 27.4_0402_1% VCC[045] VCCP[11]
2 1 D25 AA1 1 2 F14 R6
Spacing: 15mil TEST2 COMP[2] VCC[046] VCCP[12]
2

@ PAD TEST3 C24 Y1 COMP3 R23 1 2 54.9_0402_1% F15 T21

T1 TEST3 COMP[3] VCC[047] VCCP[13]
(55Ohm) R29 C1477 1 2 0.1U_0402_16V4Z TEST4 AF26 F17 T6
TEST5 TEST4 VCC[048] VCCP[14]
2K_0402_1% T2 PAD @ AF1 TEST5 DPRSTP# E5 H_DPRSTP# <8,26,49> F18 VCC[049] VCCP[15] V21
PAD TEST6 A26 B5 F20 W21
T3 TEST6 DPSLP# H_DPSLP# <26> VCC[050] VCCP[16]
@ C3 D24 H_DPWR# <7> AA7 20mils
1

TEST7 DPWR# H_PWRGOOD VCC[051]

<16> CPU_BSEL0@ B22 BSEL[0] PWRGOOD D6 H_PWRGOOD <26> AA9 VCC[052] VCCA[01] B26 +1.5VS
<16> CPU_BSEL1 B23 D7 H_CPUSLP# AA10 C26
BSEL[1] SLP# H_CPUSLP# <7> VCC[053] VCCA[02]
<16> CPU_BSEL2 C21 BSEL[2] PSI# AE6 PSI# <49> AA12 VCC[054] 1 1
AA13 AD6 CPU_VID0 <49> C7 C8
Penryn CONN@ VCC[055] VID[0]
AA15 VCC[056] VID[1] AF5 CPU_VID1 <49>
AA17 AE5 CPU_VID2 0.01U_0402_16V7K
<49>
VCC[057] VID[2] 2 2
TRACE CLOSELY CPU < 0.5' AA18 VCC[058] VID[3] AF4 CPU_VID3 <49>
AA20 VCC[059] VID[4] AE3 CPU_VID4 <49>
COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) AB9 AF3 CPU_VID5 <49> 10U_0805_10V4Z
VCC[060] VID[5]
AC10 AE2 CPU_VID6 <49>
B COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms) AB10
VCC[061] VID[6]
1 2
B
VCC[062] +CPU_CORE
AB12 R28 100_0402_1%
VCC[063] VCCSENSE
AB14 VCC[064] VCCSENSE AF7 VCCSENSE <49>
AB15 VCC[065]
AB17 VCC[066]
AB18 AE7 VSSSENSE VSSSENSE <49>
VCC[067] VSSSENSE
Penryn CONN@ 1 2
. R30 100_0402_1%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn (2/3)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 5 of 52
5 4 3 2 1
 5 4 3 2 1

JCPU1D
A4 VSS[001] VSS[082] P6
A8 VSS[002] VSS[083] P21
A11 VSS[003] VSS[084] P24
A14 VSS[004] VSS[085] R2
A16 R5 +CPU_CORE
VSS[005] VSS[086]
A19 VSS[006] VSS[087] R22
D A23 VSS[007] VSS[088] R25 D
AF2 VSS[008] VSS[089] T1
B6 VSS[009] VSS[090] T4
B8 VSS[010] VSS[091] T23
B11 VSS[011] VSS[092] T26 1 2
B13 VSS[012] VSS[093] U3
B16 U6 + C55
VSS[013] VSS[094] 900P_PFAF250E128MNTTE_2.5VM
B19 VSS[014] VSS[095] U21
B21 VSS[015] VSS[096] U24
3 4
B24 VSS[016] VSS[097] V2
C5 VSS[017] VSS[098] V5
C8 VSS[018] VSS[099] V22
C11 VSS[019] VSS[100] V25
C14 VSS[020] VSS[101] W1
C16 VSS[021] VSS[102] W4
C19 VSS[022] VSS[103] W23
C2 VSS[023] VSS[104] W26
C22 VSS[024] VSS[105] Y3
C25 VSS[025] VSS[106] Y6
D1 VSS[026] VSS[107] Y21
D4 VSS[027] VSS[108] Y24
D8 VSS[028] VSS[109] AA2
D11 VSS[029] VSS[110] AA5
D13 VSS[030] VSS[111] AA8
D16 VSS[031] VSS[112] AA11
D19 VSS[032] VSS[113] AA14
D23 AA16 +CPU_CORE
VSS[033] VSS[114]
D26 VSS[034] VSS[115] AA19
E3 VSS[035] VSS[116] AA22
C E6 AA25 C
VSS[036] VSS[117]
E8 VSS[037] VSS[118] AB1
E11 VSS[038] VSS[119] AB4
E14 VSS[039] VSS[120] AB8 1 1 1 1 1 1 1 1
E16 AB11 C416 C425 C426 C427 C428 C429 C430 C431
VSS[040] VSS[121]
E19 VSS[041] VSS[122] AB13
E21 VSS[042] VSS[123] AB16
2 2 2 2 2 2 2 2
E24 VSS[043] VSS[124] AB19
F5 AB23 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[044] VSS[125] 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
F8 VSS[045] VSS[126] AB26
F11 VSS[046] VSS[127] AC3
F13 VSS[047] VSS[128] AC6
F16 VSS[048] VSS[129] AC8
F19 VSS[049] VSS[130] AC11
F2 VSS[050] VSS[131] AC14
F22 VSS[051] VSS[132] AC16
F25 VSS[052] VSS[133] AC19
G4 VSS[053] VSS[134] AC21
G1 VSS[054] VSS[135] AC24
G23 VSS[055] VSS[136] AD2
G26 VSS[056] VSS[137] AD5
H3 VSS[057] VSS[138] AD8
H6 VSS[058] VSS[139] AD11
H21 VSS[059] VSS[140] AD13
H24 VSS[060] VSS[141] AD16
J2 VSS[061] VSS[142] AD19
J5 VSS[062] VSS[143] AD22
J22 VSS[063] VSS[144] AD25
J25 VSS[064] VSS[145] AE1
B B
K1 VSS[065] VSS[146] AE4
K4 VSS[066] VSS[147] AE8
K23 VSS[067] VSS[148] AE11
K26 VSS[068] VSS[149] AE14 +CPU-CORE C,uF ESR, mohm ESL,nH
L3 AE16
L6
VSS[069] VSS[150]
AE19 Decoupling
VSS[070] VSS[151]
L21 VSS[071] VSS[152] AE23 SPCAP,Polymer 4X330uF 6m ohm/4 1.8nH/6
L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2 32X22uF 3m ohm/32 0.6nH/32
M5 VSS[074] VSS[155] AF6 MLCC 0805 X5R
M22 VSS[075] VSS[156] AF8 32X10uF 3m ohm/32 0.6nH/32
M25 VSS[076] VSS[157] AF11
N1 VSS[077] VSS[158] AF13
N4 VSS[078] VSS[159] AF16
N23 VSS[079] VSS[160] AF19
N26 VSS[080] VSS[161] AF21
P3 A25 +1.05VS
VSS[081] VSS[162]
VSS[163] AF25

Penryn CONN@ 1
. 1 1 1 1 1 1
+ C1478 C45 C46 C47 C48 C49 C50

330U_D2E_2.5VM_R15 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

2 2 2 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn (3/3)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 6 of 52
5 4 3 2 1
 5 4 3 2 1

H_A#[3..35] <4>
<5> H_D#[0..63] U2A
A14 H_A#3
H_D#0 H_A#_3 H_A#4
F2 H_D#_0 H_A#_4 C15
H_D#1 G8 F16 H_A#5
H_D#2 H_D#_1 H_A#_5 H_A#6
F8 H_D#_2 H_A#_6 H13
H_D#3 E6 C18 H_A#7
H_D#4 H_D#_3 H_A#_7 H_A#8
G2 H_D#_4 H_A#_8 M16
D H_D#5 H6 J13 H_A#9 D
H_D#6 H_D#_5 H_A#_9 H_A#10
H2 H_D#_6 H_A#_10 P16
H_D#7 F6 R16 H_A#11
H_D#8 H_D#_7 H_A#_11 H_A#12
D4 H_D#_8 H_A#_12 N17
H_D#9 H3 M13 H_A#13
H_D#10 H_D#_9 H_A#_13 H_A#14
M9 H_D#_10 H_A#_14 E17
H_D#11 M11 P17 H_A#15
H_D#12 H_D#_11 H_A#_15 H_A#16
J1 H_D#_12 H_A#_16 F17
H_D#13 J2 G20 H_A#17
H_D#14 H_D#_13 H_A#_17 H_A#18
N12 H_D#_14 H_A#_18 B19
H_D#15 J6 J16 H_A#19
H_D#16 H_D#_15 H_A#_19 H_A#20
P2 H_D#_16 H_A#_20 E20
H_D#17 L2 H16 H_A#21
H_D#18 H_D#_17 H_A#_21 H_A#22
R2 H_D#_18 H_A#_22 J20
H_D#19 N9 L17 H_A#23
H_D#20 H_D#_19 H_A#_23 H_A#24
L6 H_D#_20 H_A#_24 A17
H_D#21 M5 B17 H_A#25
+1.05VS H_D#22 H_D#_21 H_A#_25 H_A#26
J3 H_D#_22 H_A#_26 L16
H_D#23 N2 C21 H_A#27
H_D#24 H_D#_23 H_A#_27 H_A#28
R1 H_D#_24 H_A#_28 J17
1

H_D#25 N5 H20 H_A#29

R47 H_D#26 H_D#_25 H_A#_29 H_A#30
N6 H_D#_26 H_A#_30 B18
H_D#27 P13 K17 H_A#31
221_0402_1% H_D#28 H_D#_27 H_A#_31 H_A#32
N8 H_D#_28 H_A#_32 B20
H_D#29 L7 F21 H_A#33
2

H_SWING H_D#30 H_D#_29 H_A#_33 H_A#34

N10 H_D#_30 H_A#_34 K21
H_D#31 M3 L20 H_A#35
H_D#32 H_D#_31 H_A#_35
width=10mil Y3 H_D#_32
2

1 H_D#33 AD14 H12 H_ADS#

H_D#_33 H_ADS# H_ADS# <4>
C R55 C59 H_D#34 Y6 B16 H_ADSTB#0 C
H_D#_34 H_ADSTB#_0 H_ADSTB#0 <4>
H_D#35 Y10 G17 H_ADSTB#1
H_D#_35 H_ADSTB#_1 H_ADSTB#1 <4>
100_0402_1% 0.1U_0402_16V4Z H_D#36 Y12 A9 H_BNR#
2 H_D#_36 H_BNR# H_BNR# <4>

HOST
H_D#37 Y14 F11 H_BPRI#
H_BPRI# <4>
1

H_D#38 H_D#_37 H_BPRI# H_BR0#

Y7 H_D#_38 H_BREQ# G12 H_BR0# <4>
H_D#39 W2 E9 H_DEFER#
H_D#_39 H_DEFER# H_DEFER# <4>
H_D#40 AA8 B10 H_DBSY#
H_D#_40 H_DBSY# H_DBSY# <4>
H_D#41 Y9 AH7 CLK_MCH_BCLK
H_D#_41 HPLL_CLK CLK_MCH_BCLK <16>
H_RCOMP H_D#42 AA13 AH6 CLK_MCH_BCLK#
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# <16>
H_D#43 AA9 J11 H_DPWR#
H_D#_43 H_DPWR# H_DPWR# <5>
width=10mil H_D#44 AA11 F9 H_DRDY#
H_D#_44 H_DRDY# H_DRDY# <4>
1

H_D#45 AD11 H9 H_HIT#

H_D#_45 H_HIT# H_HIT# <4>
R54 H_D#46 AD10 E12 H_HITM#
H_D#_46 H_HITM# H_HITM# <4>
H_D#47 AD13 H11 H_LOCK#
H_D#_47 H_LOCK# H_LOCK# <4>
24.9_0402_1% H_D#48 AE12 C9 H_TRDY#
H_D#_48 H_TRDY# H_TRDY# <4>
H_D#49 AE9
2

H_D#50 H_D#_49
AA2 H_D#_50
H_D#51 AD8
H_D#52 H_D#_51
AA3 H_D#_52
H_D#53 AD3 J8 H_DINV#0
H_D#54 H_D#_53 H_DINV#_0 H_DINV#1 H_DINV#0 <5>
AD7 H_D#_54 H_DINV#_1 L3 H_DINV#1 <5>
H_D#55 AE14 Y13 H_DINV#2
H_D#56 H_D#_55 H_DINV#_2 H_DINV#3 H_DINV#2 <5>
AF3 H_D#_56 H_DINV#_3 Y1 H_DINV#3 <5>
H_D#57 AC1
H_D#58 H_D#_57 H_DSTBN#0
AE3 H_D#_58 H_DSTBN#_0 L10 H_DSTBN#0 <5>
H_D#59 AC3 M7 H_DSTBN#1
H_D#60 H_D#_59 H_DSTBN#_1 H_DSTBN#2 H_DSTBN#1 <5>
AE11 H_D#_60 H_DSTBN#_2 AA5 H_DSTBN#2 <5>
H_D#61 AE8 AE6 H_DSTBN#3
H_D#62 H_D#_61 H_DSTBN#_3 H_DSTBN#3 <5>
AG2 H_D#_62
B H_D#63 H_DSTBP#0 B
AD6 H_D#_63 H_DSTBP#_0 L9 H_DSTBP#0 <5>
M8 H_DSTBP#1
H_DSTBP#_1 H_DSTBP#2 H_DSTBP#1 <5>
H_DSTBP#_2 AA6 H_DSTBP#2 <5>
H_SWING C5 AE5 H_DSTBP#3
H_RCOMP H_SWING H_DSTBP#_3 H_DSTBP#3 <5>
E3 H_RCOMP H_REQ#[0..4] <4>
+1.05VS B15 H_REQ#0
H_REQ#_0 H_REQ#1
H_REQ#_1 K13
F13 H_REQ#2
H_REQ#_2
2

B13 H_REQ#3
R46 H_RESET# H_REQ#_3 H_REQ#4
<4> H_RESET# C12 H_CPURST# H_REQ#_4 B14
H_CPUSLP# E11
<5> H_CPUSLP# H_CPUSLP# H_RS#[0..2] <4>
1K_0402_1% B6 H_RS#0
H_RS#_0 H_RS#1
F12
1

H_AVREF H_RS#_1 H_RS#2

width:spacing=10mil:20mil (<0.5") A11 H_AVREF H_RS#_2 C8
B11 H_DVREF
1

1
C58 @ CANTIGA ES_FCBGA1329 GM45@
R52
2K_0402_1% 0.1U_0402_16V4Z
2
2

within 100mil to Ball A11,B11

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH(1/7)-GTL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 7 of 52
5 4 3 2 1
 5 4 3 2 1

U2B +1.8V

M36 RSVD1 SA_CK_0 AP24 DDRA_CLK0 <14>

1
N36 AT21 DDRA_CLK1 <14>
RSVD2 SA_CK_1 R31
R33 AV24 DDRB_CLK0 <15>
RSVD3 SB_CK_0
T33 AU20 DDRB_CLK1 <15>
RSVD4 SB_CK_1

COMPENSATION
AH9 1K_0402_1%
RSVD5
AH10 AR24

2
RSVD6 SA_CK#_0 DDRA_CLK0# <14>
AH12 AR21 SM_RCOMP_VOH
RSVD7 SA_CK#_1 DDRA_CLK1# <14>
AH13 AU24 DDRB_CLK0# <15>
RSVD8 SB_CK#_0
K12 AV20 DDRB_CLK1# <15> 1 1
RSVD9 SB_CK#_1

1
AL34 C52 C51
RSVD10 R32
AK34 RSVD11 SA_CKE_0 BC28 DDRA_CKE0 <14>
AN35 AY28 2.2U_0603_6.3V6K 0.01U_0402_16V7K
D RSVD12 SA_CKE_1 DDRA_CKE1 <14> 2 2 D
AM35 AY36 SM_DRAMRST# would be 3.01K_0402_1%
RSVD13 SB_CKE_0 DDRB_CKE0 <15>
T24 BB36 needed for DDR3 only

2
RSVD14 SB_CKE_1 DDRB_CKE1 <15>
All RSVD balls on GMCH should be left No
Connect. BA17 DDRA_SCS0# <14>
SA_CS#_0 SM_RCOMP_VOL
AY16 DDRA_SCS1# <14>
SA_CS#_1
B31 RSVD15 SB_CS#_0 AV16 DDRB_SCS0# <15> For Cantiga 80 Ohm

1
B2 AR13 DDRB_SCS1# <15> 1 1
RSVD16 SB_CS#_1

DDR CLK/ CONTROL/

M1 R33 C54 C53
RSVD17

RSVD
SA_ODT_0 BD17 DDRA_ODT0 <14>
AY17 1K_0402_1% 2.2U_0603_6.3V6K 0.01U_0402_16V7K
SA_ODT_1 DDRA_ODT1 <14> 2 2
AY21 BF15

2
RSVD20 SB_ODT_O DDRB_ODT0 <15> +1.8V +1.8V
AY13 DDRB_ODT1 <15>
SB_ODT_1
BG22 SMRCOMP R34 1 2 80.6_0402_1%
SM_RCOMP

2
BG23 BH21 SMRCOMP# R35 1 2 80.6_0402_1%
RSVD22 SM_RCOMP# R45 @
BF23
RSVD23 SM_RCOMP_VOH 1K_0402_1%
BH18 RSVD24 SM_RCOMP_VOH BF28
BF18 BH28 SM_RCOMP_VOL
RSVD25 SM_RCOMP_VOL CLK_DREF_96M R1134 1 PM@ 0_0402_5%
20mil 2

1
AV42 SM_VREF 1 2 +DIMM_VREF CLK_DREF_96M# R1136 1 PM@ 2 0_0402_5%
SM_VREF SM_PWROK R36
AR36 1 2 0_0402_5% R1135
SM_PWROK

2
BF17 SM_REXT R37 1 2 499_0402_1% 1 0_0402_5%
SM_REXT C57 R48 CLK_DREF_SSC R1137 1 PM@ 0_0402_5%
SM_DRAMRST# BC36 2
1K_0402_1% CLK_DREF_SSC# R1138 1 PM@ 2 0_0402_5%
0.1U_0402_16V4Z @
CLK_DREF_96M 2
B38

1
DPLL_REF_CLK CLK_DREF_96M# CLK_DREF_96M <16>
A38 CLK_DREF_96M# <16>
DPLL_REF_CLK# CLK_DREF_SSC
DPLL_REF_SSCLK
E41
F41 CLK_DREF_SSC#
CLK_DREF_SSC <16> as close as possible to the related balls
DPLL_REF_SSCLK# CLK_DREF_SSC# <16>

CLK
F43 CLK_MCH_3GPLL
PEG_CLK CLK_MCH_3GPLL# CLK_MCH_3GPLL <16>
E43
C PEG_CLK# CLK_MCH_3GPLL# <16>
Strap Pin Table C

011 = FSB667
AE41 DMI_ITX_MRX_N0 CFG[2:0] 010 = FSB800
DMI_RXN_0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N0 <27>
DMI_RXN_1 AE37 DMI_ITX_MRX_N1 <27> 000 = FSB1067
AE47 DMI_ITX_MRX_N2
DMI_RXN_2 DMI_ITX_MRX_N2 <27>
AH39 DMI_ITX_MRX_N3 0 = DMI x 2
DMI_RXN_3 DMI_ITX_MRX_N3 <27>
AE40 DMI_ITX_MRX_P0
CFG5 1 = DMI x 4 * (Default)
MCH_CLKSEL0 DMI_RXP_0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P0 <27>
<16> MCH_CLKSEL0 T25
CFG_0 DMI_RXP_1
AE38 DMI_ITX_MRX_P1 <27> 0 = iTPM Host Interface is enabled
MCH_CLKSEL1 DMI_ITX_MRX_P2
<16> MCH_CLKSEL1
MCH_CLKSEL2
R25
P25
CFG_1 DMI_RXP_2 AE48
AH40 DMI_ITX_MRX_P3
DMI_ITX_MRX_P2 <27> CFG6 1 = iTPM Host Interface is Disabled *(Default)
<16> MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_ITX_MRX_P3 <27>
P20 CFG_3 DMI_MTX_IRX_N0
0 = Lane Reversal Enable
2 PM_EXTTS#0 MCH_CFG_5
P24
CFG_4 DMI_TXN_0
AE35
DMI_MTX_IRX_N1 DMI_MTX_IRX_N0 <27> CFG9 1 = Normal Operation * (Default)

DMI
+3VS 1 C25 AE43 DMI_MTX_IRX_N1 <27>
R38 10K_0402_5% MCH_CFG_6 CFG_5 DMI_TXN_1 DMI_MTX_IRX_N2
N24
CFG_6 DMI_TXN_2
AE46 DMI_MTX_IRX_N2 <27> 0 = PCIe Loopback Enable
1 2 PM_EXTTS#1 MCH_CFG_7 M24 AH42 DMI_MTX_IRX_N3
DMI_MTX_IRX_N3 <27> CFG10 1 = Disable * (Default)
R39 10K_0402_5% CFG_7 CFG DMI_TXN_3
E21
CFG_8
1 2 MCH_CLKREQ# MCH_CFG_9 C23 AD35 DMI_MTX_IRX_P0
DMI_MTX_IRX_P0 <27> 00 = Reserved
R40 10K_0402_5% MCH_CFG_10 CFG_9 DMI_TXP_0 DMI_MTX_IRX_P1
C24 CFG_10 DMI_TXP_1 AE44 DMI_MTX_IRX_P1 <27> CFG[13:12] 01 = XOR Mode Enabled
N21 AF46 DMI_MTX_IRX_P2 10 = All Z Mode Enabled
CFG_11 DMI_TXP_2 DMI_MTX_IRX_P2 <27>
Use VGATE for GMCH_PWROK MCH_CFG_12 P21 AH43 DMI_MTX_IRX_P3 11 = Normal Operation * (Default)
MCH_CFG_13 CFG_12 DMI_TXP_3 DMI_MTX_IRX_P3 <27>
T21
VGATE @ GMCH_PWROK CFG_13
<16,27,49> VGATE 1 2 R20
CFG_14 0 = Dynamic ODT Disabled
R1139
ICH_PWROK 1 2
0_0402_5%
MCH_CFG_16
M20
L21
CFG_15 CFG16 1 = Dynamic ODT Enabled * (Default)
<27> ICH_PWROK CFG_16
R1140 0_0402_5% H21 CFG_17 0 = Normal Operation *(Default)
P29 CFG19 1 = DMI Lane Reversal Enable
GRAPHICS VID

MCH_CFG_19 CFG_18
R28
MCH_CFG_20 CFG_19
T28
CFG_20 GFX_VID_0
B33 0 = Only PCIE or SDVO is operational.
GFX_VID_1
B32
G33
CFG20 * (Default)
B GFX_VID_2
F33 (PCIE/SDVO select) 1 = PCIE/SDVO are operating simu. B
R1141 1 PM_SYNC#_R GFX_VID_3
<27> PM_SYNC# 2 0_0402_5% R29 PM_SYNC# GFX_VID_4 E33
PM_DPRSTP#_R
<5,26,49> H_DPRSTP# R1142 1 2 0_0402_5%
PM_EXTTS#0
B7
PM_DPRSTP# 0 = No SDVO Card Present * (Default)
<14> PM_EXTTS#0 N33 PM_EXT_TS#_0 SDVO_CTRLDATA 1 = SDVO Card Present
PM

<15> PM_EXTTS#1 PM_EXTTS#1 P32

GMCH_PWROK PM_EXT_TS#_1
R1143 1 2 100_0402_5% MCH_RSTIN#
AT40
PWROK GFX_VR_EN
C34 0 = LFP Disable * (Default)
<17,25,27,30,31,35> PLT_RST#
THERMTRIP#_R
AT11
RSTIN# +1.05VS
L_DDC_DATA 1 = LFP Card Present; PCIE disable
<4,26> H_THERMTRIP# R1144 1 2 0_0402_5% T20
DPRSLPVR_R THERMTRIP#
<27,49> PM_DPRSLPVR
R1145 1 2 0_0402_5% R32
DPRSLPVR 0 = Digital DisplayPort Disable * (Default)
DDPC_CTRLDATA 1 = Digital DisplayPort Device Present

2
BG48 AH37 R43
NC_1 CL_CLK CL_CLK0 <27>
BF48 AH36 1K_0402_1%
NC_2 CL_DATA CL_DATA0 <27>
ME

BD48 AN36 ICH_PWROK

NC_3 CL_PWROK MCH_CFG_5 @
BC48 AJ35 2 1

1
NC_4 CL_RST# CL_VREF CL_RST#0 <27>
BH47 AH34 R1146 2.21K_0402_1%
NC_5 CL_VREF MCH_CFG_6 @
BG47 2 1
NC_6

2
BE47 R79 4.02K_0402_1%
NC_7 C56 R44 MCH_CFG_7 @
BH46 N28 1 2 1
NC_8 DDPC_CTRLCLK
NC

BF46 M28 511_0402_1% R81 2.21K_0402_1%

NC_9 DDPC_CTRLDATA MCH_CFG_9
+3VS
BG45
NC_10 SDVO_CTRLCLK
G36 PAD T34 @ 2 @ 1
BH44 E36 PAD T35 @ 0.1U_0402_16V4Z R84 2.21K_0402_1%

1
NC_11 SDVO_CTRLDATA MCH_CLKREQ# 2 MCH_CFG_10 @
BH43 K36 MCH_CLKREQ# <16> 2 1
NC_12 CLKREQ#
MISC

BH6 H36 MCH_ICH_SYNC# <27> R86 2.21K_0402_1%

NC_13 ICH_SYNC#
1

+3VS BH5 MCH_CFG_12 2 @ 1

R1147 NC_14 R77 2.21K_0402_1%
BG4
1K_0402_5% NC_15 MCH_TSATN# MCH_CFG_13 @
BH3 NC_16 TSATN# B12 2 1
1

+1.05VS BF3 R78 2.21K_0402_1%

R1148 NC_17 MCH_CFG_16 @
BH2 2 1
2

1K_0402_5% NC_18 R1149 2.21K_0402_1%

MCH_TSATN_EC# <35> BG2
NC_19
1

BE2 B28
NC_20 HDA_BCLK
1

R1150 C BG1 B30

2

A 54.9_0402_1% Q75 NC_21 HDA_RST# A

2 BF1 B29
B NC_22 HDA_SDI MCH_CFG_19
R1152 MMBT3904_SOT23-3 BD1 NC_23 HDA_SDO C29 2 @ 1 +3VS
1

C E BC1 A28 R73 4.02K_0402_1%

HDA
2

MCH_TSATN# Q76 NC_24 HDA_SYNC MCH_CFG_20

1 2 2 F1 2 @ 1
B NC_25 R75 4.02K_0402_1%
MMBT3904_SOT23-3 A47 NC_26 Notice: Please check HDA power rail to select HDA controller.
330_0402_5% E
3

CANTIGA ES_FCBGA1329 GM45@

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH(2/7)-DMI/DDR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 8 of 52
5 4 3 2 1
 5 4 3 2 1

DDRA_SDQ[0..63] DDRB_SDQ[0..63]
<14> DDRA_SDQ[0..63] <15> DDRB_SDQ[0..63]
DDRA_SDM[0..7] DDRB_SDM[0..7]
<14> DDRA_SDM[0..7] <15> DDRB_SDM[0..7]

D DDRA_SMA[0..14] DDRB_SMA[0..14] D
<14> DDRA_SMA[0..14] <15> DDRB_SMA[0..14]

U2D U2E
DDRA_SDQ0 AJ38 BD21 DDRB_SDQ0 AK47 BC16
SA_DQ_0 SA_BS_0 DDRA_SBS0# <14> SB_DQ_0 SB_BS_0 DDRB_SBS0# <15>
DDRA_SDQ1 AJ41 BG18 DDRB_SDQ1 AH46 BB17
SA_DQ_1 SA_BS_1 DDRA_SBS1# <14> SB_DQ_1 SB_BS_1 DDRB_SBS1# <15>
DDRA_SDQ2 AN38 AT25 DDRB_SDQ2 AP47 BB33
SA_DQ_2 SA_BS_2 DDRA_SBS2# <14> SB_DQ_2 SB_BS_2 DDRB_SBS2# <15>
DDRA_SDQ3 AM38 DDRB_SDQ3 AP46
DDRA_SDQ4 SA_DQ_3 DDRB_SDQ4 SB_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 DDRA_SRAS# <14> AJ46 SB_DQ_4
DDRA_SDQ5 AJ40 BD20 DDRB_SDQ5 AJ48 AU17
SA_DQ_5 SA_CAS# DDRA_SCAS# <14> SB_DQ_5 SB_RAS# DDRB_SRAS# <15>
DDRA_SDQ6 AM44 AY20 DDRB_SDQ6 AM48 BG16
SA_DQ_6 SA_WE# DDRA_SWE# <14> SB_DQ_6 SB_CAS# DDRB_SCAS# <15>
DDRA_SDQ7 AM42 DDRB_SDQ7 AP48 BF14
SA_DQ_7 SB_DQ_7 SB_WE# DDRB_SWE# <15>
DDRA_SDQ8 AN43 DDRB_SDQ8 AU47
DDRA_SDQ9 SA_DQ_8 DDRB_SDQ9 SB_DQ_8
AN44 SA_DQ_9 AU46 SB_DQ_9
DDRA_SDQ10 AU40 DDRB_SDQ10 BA48
DDRA_SDQ11 SA_DQ_10 DDRB_SDQ11 SB_DQ_10
AT38 SA_DQ_11 AY48 SB_DQ_11
DDRA_SDQ12 AN41 DDRB_SDQ12 AT47
DDRA_SDQ13 SA_DQ_12 DDRA_SDM0 DDRB_SDQ13 SB_DQ_12
AN39 SA_DQ_13 SA_DM_0 AM37 AR47 SB_DQ_13
DDRA_SDQ14 AU44 AT41 DDRA_SDM1 DDRB_SDQ14 BA47
DDRA_SDQ15 SA_DQ_14 SA_DM_1 DDRA_SDM2 DDRB_SDQ15 SB_DQ_14 DDRB_SDM0
AU42 SA_DQ_15 SA_DM_2 AY41 BC47 SB_DQ_15 SB_DM_0 AM47
DDRA_SDQ16 AV39 AU39 DDRA_SDM3 DDRB_SDQ16 BC46 AY47 DDRB_SDM1
DDRA_SDQ17 SA_DQ_16 SA_DM_3 DDRA_SDM4 DDRB_SDQ17 SB_DQ_16 SB_DM_1 DDRB_SDM2
AY44 SA_DQ_17 SA_DM_4 BB12 BC44 SB_DQ_17 SB_DM_2 BD40
DDRA_SDQ18 BA40 AY6 DDRA_SDM5 DDRB_SDQ18 BG43 BF35 DDRB_SDM3
C DDRA_SDQ19 SA_DQ_18 SA_DM_5 DDRA_SDM6 DDRB_SDQ19 SB_DQ_18 SB_DM_3 DDRB_SDM4 C
BD43 SA_DQ_19 SA_DM_6 AT7 BF43 SB_DQ_19 SB_DM_4 BG11
DDRA_SDQ20 AV41 AJ5 DDRA_SDM7 DDRB_SDQ20 BE45 BA3 DDRB_SDM5
DDRA_SDQ21 SA_DQ_20 SA_DM_7 DDRB_SDQ21 SB_DQ_20 SB_DM_5 DDRB_SDM6
AY43 BC41 AP1

B
SA_DQ_21 SB_DQ_21 SB_DM_6
A

DDRA_SDQ22 BB41 DDRB_SDQ22 BF40 AK2 DDRB_SDM7

DDRA_SDQ23 SA_DQ_22 DDRA_SDQS0 DDRB_SDQ23 SB_DQ_22 SB_DM_7
BC40 SA_DQ_23 SA_DQS_0 AJ44 DDRA_SDQS0 <14> BF41 SB_DQ_23
DDRA_SDQ24 AY37 AT44 DDRA_SDQS1 DDRB_SDQ24 BG38
SA_DQ_24 SA_DQS_1 DDRA_SDQS1 <14> SB_DQ_24
DDRA_SDQ25 BD38 BA43 DDRA_SDQS2 DDRB_SDQ25 BF38 AL47 DDRB_SDQS0
SA_DQ_25 SA_DQS_2 DDRA_SDQS2 <14> SB_DQ_25 SB_DQS_0 DDRB_SDQS0 <15>

MEMORY
DDRA_SDQ26 DDRA_SDQS3 DDRB_SDQ26 DDRB_SDQS1
MEMORY

AV37 SA_DQ_26 SA_DQS_3 BC37 DDRA_SDQS3 <14> BH35 SB_DQ_26 SB_DQS_1 AV48 DDRB_SDQS1 <15>
DDRA_SDQ27 AT36 AW12 DDRA_SDQS4 DDRB_SDQ27 BG35 BG41 DDRB_SDQS2
SA_DQ_27 SA_DQS_4 DDRA_SDQS4 <14> SB_DQ_27 SB_DQS_2 DDRB_SDQS2 <15>
DDRA_SDQ28 AY38 BC8 DDRA_SDQS5 DDRB_SDQ28 BH40 BG37 DDRB_SDQS3
SA_DQ_28 SA_DQS_5 DDRA_SDQS5 <14> SB_DQ_28 SB_DQS_3 DDRB_SDQS3 <15>
DDRA_SDQ29 BB38 AU8 DDRA_SDQS6 DDRB_SDQ29 BG39 BH9 DDRB_SDQS4
SA_DQ_29 SA_DQS_6 DDRA_SDQS6 <14> SB_DQ_29 SB_DQS_4 DDRB_SDQS4 <15>
DDRA_SDQ30 AV36 AM7 DDRA_SDQS7 DDRB_SDQ30 BG34 BB2 DDRB_SDQS5
SA_DQ_30 SA_DQS_7 DDRA_SDQS7 <14> SB_DQ_30 SB_DQS_5 DDRB_SDQS5 <15>
DDRA_SDQ31 AW36 DDRB_SDQ31 BH34 AU1 DDRB_SDQS6
SA_DQ_31 SB_DQ_31 SB_DQS_6 DDRB_SDQS6 <15>
DDRA_SDQ32 BD13 DDRB_SDQ32 BH14 AN6 DDRB_SDQS7
SA_DQ_32 SB_DQ_32 SB_DQS_7 DDRB_SDQS7 <15>
DDRA_SDQ33 AU11 AJ43 DDRA_SDQS0# DDRB_SDQ33 BG12
SA_DQ_33 SA_DQS#_0 DDRA_SDQS0# <14> SB_DQ_33
DDRA_SDQ34 BC11 AT43 DDRA_SDQS1# DDRB_SDQ34 BH11
SA_DQ_34 SA_DQS#_1 DDRA_SDQS1# <14> SB_DQ_34
DDRA_SDQ35 BA12 BA44 DDRA_SDQS2# DDRB_SDQ35 BG8 AL46 DDRB_SDQS0#
SA_DQ_35 SA_DQS#_2 DDRA_SDQS2# <14> SB_DQ_35 SB_DQS#_0 DDRB_SDQS0# <15>

SYSTEM
DDRA_SDQ36
SYSTEM

AU13 BD37 DDRA_SDQS3# DDRB_SDQ36 BH12 AV47 DDRB_SDQS1#

SA_DQ_36 SA_DQS#_3 DDRA_SDQS3# <14> SB_DQ_36 SB_DQS#_1 DDRB_SDQS1# <15>
DDRA_SDQ37 AV13 AY12 DDRA_SDQS4# DDRB_SDQ37 BF11 BH41 DDRB_SDQS2#
SA_DQ_37 SA_DQS#_4 DDRA_SDQS4# <14> SB_DQ_37 SB_DQS#_2 DDRB_SDQS2# <15>
DDRA_SDQ38 BD12 BD8 DDRA_SDQS5# DDRB_SDQ38 BF8 BH37 DDRB_SDQS3#
SA_DQ_38 SA_DQS#_5 DDRA_SDQS5# <14> SB_DQ_38 SB_DQS#_3 DDRB_SDQS3# <15>
DDRA_SDQ39 BC12 AU9 DDRA_SDQS6# DDRB_SDQ39 BG7 BG9 DDRB_SDQS4#
SA_DQ_39 SA_DQS#_6 DDRA_SDQS6# <14> SB_DQ_39 SB_DQS#_4 DDRB_SDQS4# <15>
DDRA_SDQ40 BB9 AM8 DDRA_SDQS7# DDRB_SDQ40 BC5 BC2 DDRB_SDQS5#
SA_DQ_40 SA_DQS#_7 DDRA_SDQS7# <14> SB_DQ_40 SB_DQS#_5 DDRB_SDQS5# <15>
DDRA_SDQ41 BA9 DDRB_SDQ41 BC6 AT2 DDRB_SDQS6#
SA_DQ_41 SB_DQ_41 SB_DQS#_6 DDRB_SDQS6# <15>
DDRA_SDQ42 AU10 DDRB_SDQ42 AY3 AN5 DDRB_SDQS7#
SA_DQ_42 SB_DQ_42 SB_DQS#_7 DDRB_SDQS7# <15>
DDRA_SDQ43 AV9 DDRB_SDQ43 AY1
DDRA_SDQ44 SA_DQ_43 DDRA_SMA0 DDRB_SDQ44 SB_DQ_43
BA11 SA_DQ_44 SA_MA_0 BA21 BF6 SB_DQ_44
DDRA_SDQ45 BD9 BC24 DDRA_SMA1 DDRB_SDQ45 BF5 AV17 DDRB_SMA0

DDR
SA_DQ_45 SA_MA_1 SB_DQ_45 SB_MA_0
DDR

DDRA_SDQ46 AY8 BG24 DDRA_SMA2 DDRB_SDQ46 BA1 BA25 DDRB_SMA1

DDRA_SDQ47 SA_DQ_46 SA_MA_2 DDRA_SMA3 DDRB_SDQ47 SB_DQ_46 SB_MA_1 DDRB_SMA2
BA6 SA_DQ_47 SA_MA_3 BH24 BD3 SB_DQ_47 SB_MA_2 BC25
B DDRA_SDQ48 DDRA_SMA4 DDRB_SDQ48 DDRB_SMA3 B
AV5 SA_DQ_48 SA_MA_4 BG25 AV2 SB_DQ_48 SB_MA_3 AU25
DDRA_SDQ49 AV7 BA24 DDRA_SMA5 DDRB_SDQ49 AU3 AW25 DDRB_SMA4
DDRA_SDQ50 SA_DQ_49 SA_MA_5 DDRA_SMA6 DDRB_SDQ50 SB_DQ_49 SB_MA_4 DDRB_SMA5
AT9 SA_DQ_50 SA_MA_6 BD24 AR3 SB_DQ_50 SB_MA_5 BB28
DDRA_SDQ51 AN8 BG27 DDRA_SMA7 DDRB_SDQ51 AN2 AU28 DDRB_SMA6
DDRA_SDQ52 SA_DQ_51 SA_MA_7 DDRA_SMA8 DDRB_SDQ52 SB_DQ_51 SB_MA_6 DDRB_SMA7
AU5 SA_DQ_52 SA_MA_8 BF25 AY2 SB_DQ_52 SB_MA_7 AW28
DDRA_SDQ53 AU6 AW24 DDRA_SMA9 DDRB_SDQ53 AV1 AT33 DDRB_SMA8
DDRA_SDQ54 SA_DQ_53 SA_MA_9 DDRA_SMA10 DDRB_SDQ54 SB_DQ_53 SB_MA_8 DDRB_SMA9
AT5 SA_DQ_54 SA_MA_10 BC21 AP3 SB_DQ_54 SB_MA_9 BD33
DDRA_SDQ55 AN10 BG26 DDRA_SMA11 DDRB_SDQ55 AR1 BB16 DDRB_SMA10
DDRA_SDQ56 SA_DQ_55 SA_MA_11 DDRA_SMA12 DDRB_SDQ56 SB_DQ_55 SB_MA_10 DDRB_SMA11
AM11 SA_DQ_56 SA_MA_12 BH26 AL1 SB_DQ_56 SB_MA_11 AW33
DDRA_SDQ57 AM5 BH17 DDRA_SMA13 DDRB_SDQ57 AL2 AY33 DDRB_SMA12
DDRA_SDQ58 SA_DQ_57 SA_MA_13 DDRA_SMA14 DDRB_SDQ58 SB_DQ_57 SB_MA_12 DDRB_SMA13
AJ9 SA_DQ_58 SA_MA_14 AY25 AJ1 SB_DQ_58 SB_MA_13 BH15
DDRA_SDQ59 AJ8 DDRB_SDQ59 AH1 AU33 DDRB_SMA14
DDRA_SDQ60 SA_DQ_59 DDRB_SDQ60 SB_DQ_59 SB_MA_14
AN12 SA_DQ_60 AM2 SB_DQ_60
DDRA_SDQ61 AM13 DDRB_SDQ61 AM3
DDRA_SDQ62 SA_DQ_61 DDRB_SDQ62 SB_DQ_61
AJ11 SA_DQ_62 AH3 SB_DQ_62
DDRA_SDQ63 AJ12 DDRB_SDQ63 AJ3
SA_DQ_63 SB_DQ_63
CANTIGA ES_FCBGA1329 GM45@ CANTIGA ES_FCBGA1329 GM45@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH(3/7)-DDR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 9 of 52
5 4 3 2 1
 5 4 3 2 1

U2C

<22> DPST_PWM L32 L_BKLT_CTRL

<18,35> ENBKL 1 2 LBKLT_EN G32 T37 PEG_COMP 1 2 +1.05VS
R1154 GM@ 0_0402_5% LCTLA_CLK L_BKLT_EN PEG_COMPI R57 49.9_0402_1%
LCTLB_DATA
M32 L_CTRL_CLK PEG_COMPO T36 10mils
M33 L_CTRL_DATA
<22> GMCH_LCD_CLK GMCH_LCD_CLK K33
GMCH_LCD_DATA L_DDC_CLK PCIE_GTX_C_MRX_N0 PCIE_MTX_C_GRX_N[0..15]
D <22> GMCH_LCD_DATA J33 L_DDC_DATA PEG_RX#_0 H44 PCIE_MTX_C_GRX_N[0..15] <17> D
M29 J46 PCIE_GTX_C_MRX_N1
<22> GMCH_ENVDD L_VDD_EN PEG_RX#_1 PCIE_MTX_C_GRX_P[0..15]
L44 PCIE_GTX_C_MRX_N2
PEG_RX#_2 PCIE_MTX_C_GRX_P[0..15] <17>
1 2 LVDS_IBG C44 L40 PCIE_GTX_C_MRX_N3
R1155 GM@ 2.37K_0402_1% LVDS_IBG PEG_RX#_3 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_N[0..15]
B43 LVDS_VBG PEG_RX#_4 N41 PCIE_GTX_C_MRX_N[0..15] <17>
2 1 E37 P48 PCIE_GTX_C_MRX_N5
R1153 GM@ 0_0402_5% LVDS_VREFH PEG_RX#_5 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_P[0..15]
E38 LVDS_VREFL PEG_RX#_6 N44 PCIE_GTX_C_MRX_P[0..15] <17>
T43 PCIE_GTX_C_MRX_N7
GMCH_TXCLK- PEG_RX#_7 PCIE_GTX_C_MRX_N8
<22> GMCH_TXCLK- C41 LVDSA_CLK# PEG_RX#_8 U43
GMCH_TXCLK+ C40 Y43 PCIE_GTX_C_MRX_N9
<22> GMCH_TXCLK+ LVDSA_CLK PEG_RX#_9
B37 Y48 PCIE_GTX_C_MRX_N10
LVDSB_CLK# PEG_RX#_10 PCIE_GTX_C_MRX_N11
A37 LVDSB_CLK PEG_RX#_11 Y36

LVDS
AA43 PCIE_GTX_C_MRX_N12
GMCH_TXOUT0- PEG_RX#_12 PCIE_GTX_C_MRX_N13
<22> GMCH_TXOUT0- H47 LVDSA_DATA#_0 PEG_RX#_13 AD37
GMCH_TXOUT1- E46 AC47 PCIE_GTX_C_MRX_N14
<22> GMCH_TXOUT1- LVDSA_DATA#_1 PEG_RX#_14
GMCH_TXOUT2- G40 AD39 PCIE_GTX_C_MRX_N15
<22> GMCH_TXOUT2- LVDSA_DATA#_2 PEG_RX#_15
A40 LVDSA_DATA#_3
H43 PCIE_GTX_C_MRX_P0
GMCH_TXOUT0+ PEG_RX_0 PCIE_GTX_C_MRX_P1
<22> GMCH_TXOUT0+ H48 LVDSA_DATA_0 PEG_RX_1 J44
GMCH_TXOUT1+ D45 L43 PCIE_GTX_C_MRX_P2
<22> GMCH_TXOUT1+ LVDSA_DATA_1 PEG_RX_2

GRAPHICS
GMCH_TXOUT2+ F40 L41 PCIE_GTX_C_MRX_P3
<22> GMCH_TXOUT2+ LVDSA_DATA_2 PEG_RX_3
B40 N40 PCIE_GTX_C_MRX_P4
LVDSA_DATA_3 PEG_RX_4 PCIE_GTX_C_MRX_P5
PEG_RX_5 P47
A41 N43 PCIE_GTX_C_MRX_P6
LVDSB_DATA#_0 PEG_RX_6 PCIE_GTX_C_MRX_P7
H38 LVDSB_DATA#_1 PEG_RX_7 T42
G37 U42 PCIE_GTX_C_MRX_P8
LVDSB_DATA#_2 PEG_RX_8 PCIE_GTX_C_MRX_P9
J37 LVDSB_DATA#_3 PEG_RX_9 Y42
W47 PCIE_GTX_C_MRX_P10
PEG_RX_10 PCIE_GTX_C_MRX_P11
B42 LVDSB_DATA_0 PEG_RX_11 Y37
C G38 AA42 PCIE_GTX_C_MRX_P12 C
LVDSB_DATA_1 PEG_RX_12 PCIE_GTX_C_MRX_P13
F37 LVDSB_DATA_2 PEG_RX_13 AD36
K37 AC48 PCIE_GTX_C_MRX_P14
LVDSB_DATA_3 PEG_RX_14

PCI-EXPRESS
AD40 PCIE_GTX_C_MRX_P15
PEG_RX_15
Change to 0Ohm when use PM chip J41 PCIE_MTX_GRX_N0 C1289 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0
PEG_TX#_0 PCIE_MTX_GRX_N1 C1290 1
PEG_TX#_1 M46 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N1
GMCH_TV_COMPS F25 M47 PCIE_MTX_GRX_N2 C1291 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
GMCH_TV_LUMA TVA_DAC PEG_TX#_2 PCIE_MTX_GRX_N3 C1292 1
H25 TVB_DAC PEG_TX#_3 M40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N3
GMCH_TV_CRMA K25 M42 PCIE_MTX_GRX_N4 C1293 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4
TVC_DAC PEG_TX#_4 PCIE_MTX_GRX_N5 C1294 1 0.1U_0402_16V7K PCIE_MTX_C_GRX_N5
PEG_TX#_5 R48 2
2

TV
H24 N38 PCIE_MTX_GRX_N6 PM@ C1295 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6
R107 R108 R93 TV_RTN PEG_TX#_6 PCIE_MTX_GRX_N7 C1296 1
PEG_TX#_7 T40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N7
75_0402_1% 75_0402_1% 75_0402_1% U37 PCIE_MTX_GRX_N8 C1297 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8
GM@ GM@ GM@ PEG_TX#_8 PCIE_MTX_GRX_N9 C1298 1
PEG_TX#_9 U40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N9
TV_DCONSEL_0 C31 Y40 PCIE_MTX_GRX_N10 C1299 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10
1

TV_DCONSEL_1 TV_DCONSEL_0 PEG_TX#_10 PCIE_MTX_GRX_N11 C1300 1

E32 TV_DCONSEL_1 PEG_TX#_11 AA46 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N11
AA37 PCIE_MTX_GRX_N12 C1301 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12
PEG_TX#_12 PCIE_MTX_GRX_N13 C1302 1
PEG_TX#_13 AA40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N13
AD43 PCIE_MTX_GRX_N14 C1303 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14
PEG_TX#_14 PCIE_MTX_GRX_N15 C1304 1
PEG_TX#_15 AC46 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N15
Change to 0Ohm when use PM chip PCIE_MTX_GRX_P0 C1305 1
<23> GMCH_CRT_B E28 CRT_BLUE PEG_TX_0 J42 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
2 GM@ 1 PEG_TX_1 L46 PCIE_MTX_GRX_P1 C1306 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
R1159 150_0402_1% G28 M48 PCIE_MTX_GRX_P2 C1307 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2
<23> GMCH_CRT_G CRT_GREEN PEG_TX_2
2 GM@ 1 PEG_TX_3 M39 PCIE_MTX_GRX_P3 C1308 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3

VGA
R1160 150_0402_1% J28 M43 PCIE_MTX_GRX_P4 C1309 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
<23> GMCH_CRT_R CRT_RED PEG_TX_4
2 GM@ 1 PEG_TX_5 R47 PCIE_MTX_GRX_P5 C1310 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P5
R1161 150_0402_1% G29 N37 PCIE_MTX_GRX_P6 C1311 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
B CRT_IRTN PEG_TX_6 PCIE_MTX_GRX_P7 C1312 1 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P7 B
PEG_TX_7 T39 2
GMCH_CRT_CLK H32 U36 PCIE_MTX_GRX_P8 C1313 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
<23> GMCH_CRT_CLK CRT_DDC_CLK PEG_TX_8
GMCH_CRT_DATA J32 U39 PCIE_MTX_GRX_P9 C1314 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
<23> GMCH_CRT_DATA CRT_DDC_DATA PEG_TX_9
J29 Y39 PCIE_MTX_GRX_P10 C1315 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
<23> GMCH_CRT_HSYNC CRT_HSYNC PEG_TX_10
2 1 CRT_IREF E29 Y46 PCIE_MTX_GRX_P11 C1316 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11
R1162 PM@ 0_0402_5% CRT_TVO_IREF PEG_TX_11 PCIE_MTX_GRX_P12 C1317 1
PEG_TX_12 AA36 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
AA39 PCIE_MTX_GRX_P13 C1318 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P13
PEG_TX_13 PCIE_MTX_GRX_P14 C1319 1 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
<23> GMCH_CRT_VSYNC L29 CRT_VSYNC PEG_TX_14 AD42 2
2 1 AD46 PCIE_MTX_GRX_P15 C1320 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P15
+3VS R1163 PM@ 0_0402_5% PEG_TX_15
2

R1165 CANTIGA ES_FCBGA1329 GM45@

R1164 1 GM@ 2 2.2K_0402_5% GMCH_LCD_CLK 1.02K_0402_1%
GM@
R1166 1 GM@ 2 2.2K_0402_5% GMCH_LCD_DATA
1

R1167 1 GM@ 2 10K_0402_5% LCTLB_DATA

R1168 1 GM@ 2 10K_0402_5% LCTLA_CLK

R1169 1 GM@ 2 2.2K_0402_5% GMCH_CRT_CLK

R1170 1 GM@ 2 2.2K_0402_5% GMCH_CRT_DATA

A A

R1173 1 2 100K_0402_5% LBKLT_EN Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH(4/7)-VGA/LVDS/TV
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 10 of 52
5 4 3 2 1
 5 4 3 2 1

U2F
+VGFX_CORE
+1.8V

2600mA VCC_AXG_NTCF_1
W28
AP33 V28
VCC_SM_1 VCC_AXG_NCTF_2
AN33 VCC_SM_2 VCC_AXG_NCTF_3 W26 Place close to the GMCH
BH32 VCC_SM_3 VCC_AXG_NCTF_4 V26
D
BG32 VCC_SM_4 VCC_AXG_NCTF_5 W25
+1.05VS
VCC: 1930.4mA (GMCH), 1210.34mA (MCH) D
BF32 VCC_SM_5 VCC_AXG_NCTF_6 V25
BD32 W24 (270UF*1, 22UF*1, 0.22UF*2, 0.1UF*1)
VCC_SM_6 VCC_AXG_NCTF_7
BC32 VCC_SM_7 VCC_AXG_NCTF_8 V24
BB32 W23 +1.05VS
VCC_SM_8 VCC_AXG_NCTF_9 1

VCC
BA32 V23 1 1 U2G
VCC_SM_9 VCC_AXG_NCTF_10 + C131 C124 C132 C133 C125
AY32 VCC_SM_10 VCC_AXG_NCTF_11 AM21
AW32 AL21 AG34
VCC_SM_11 VCC_AXG_NCTF_12 220U_D2_4VM_R15 0.22U_0402_6.3V6K 0.1U_0402_16V4Z VCC_1
AV32 VCC_SM_12 VCC_AXG_NCTF_13 AK21 AC34 VCC_2
AU32 W21 2 2 2 AB34
VCC_SM_13 VCC_AXG_NCTF_14 10U_0805_10V4Z 0.22U_0402_6.3V6K VCC_3
AT32 V21 AA34

SM
VCC_SM_14 VCC_AXG_NCTF_15 VCC_4
AR32 VCC_SM_15 VCC_AXG_NCTF_16 U21 Y34 VCC_5
AP32 AM20 Cavity Capacitors V34

VCC CORE
VCC_SM_16 VCC_AXG_NCTF_17 VCC_6
AN32 VCC_SM_17 VCC_AXG_NCTF_18 AK20 U34 VCC_7
BH31 W20 AM33
VCC_SM_18 VCC_AXG_NCTF_19 VCC_8
BG31 U20 AK33
VCC_SM_19 VCC_AXG_NCTF_20 VCC_9
BF31 AM19 AJ33
VCC_SM_20 VCC_AXG_NCTF_21 VCC_10
BG30 VCC_SM_21 VCC_AXG_NCTF_22 AL19 AG33 VCC_11
BH29 AK19 AF33
VCC_SM_22 VCC_AXG_NCTF_23 VCC_12
BG29 VCC_SM_23 VCC_AXG_NCTF_24 AJ19
BF29 AH19 J1 @ VCC_AXG: 6326.84mA
VCC_SM_24 VCC_AXG_NCTF_25 JUMP_43X79 +VGFX_CORE
BD29 AG19
VCC_SM_25 VCC_AXG_NCTF_26 (330UF*2, 22UF*1, 10UF*1, 1U*1, 0.47U*1, 0.1UF*2)
BC29 AF19 AE33
VCC_SM_26 VCC_AXG_NCTF_27 VCC_13
BB29 VCC_SM_27 VCC_AXG_NCTF_28 AE19 +1.05VS 1 1 2 2 AC33 VCC_14
Reference PILLAR_ROCK CRB Rev1.0 BA29 AB19 C1482 C1484 AA33
VCC_SM_28 VCC_AXG_NCTF_29 C1479 GM@ 1 GM@ 1 VCC_15
AY29 AA19 1 2 1 1 1 Y33
VCC_SM_29 VCC_AXG_NCTF_30 R1174 GM@ 0_0805_5% GM@ 10U_0805_10V4Z 0.1U_0402_16V4Z VCC_16
GFX NCTF
AW29 VCC_SM_30 VCC_AXG_NCTF_31 Y19 W33 VCC_17
Pins BA36, BB24, BD16, AV29 W19 V33

POWER
VCC_SM_31 VCC_AXG_NCTF_32 0.47U_0603_16V4Z C1481 C1483 C1480 VCC_18
BB21, AW16, AW13, AT13 AU29 V19 1 2 U33
VCC_SM_32 VCC_AXG_NCTF_33 1 2 GM@ 2 2 GM@ 2 2 GM@ 2 VCC_19
AT29 U19 AH28
could be left NC for DDR2 AR29
VCC_SM_33 VCC_AXG_NCTF_34
AM17 J2 @ R1175 1U_0402_6.3V6K 10U_0805_10V4Z 0.1U_0402_16V4Z AF28
VCC_20
board. VCC_SM_34 VCC_AXG_NCTF_35 JUMP_43X79 0_0402_5% VCC_21
AP29 AK17 AC28
VCC_SM_35 VCC_AXG_NCTF_36 PM@ VCC_22
VCC_AXG_NCTF_37
AH17 Cavity Capacitors AA28
VCC_23
C C
VCC_AXG_NCTF_38 AG17 AJ26 VCC_24
AF17 AG26
VCC_SM_BA36 VCC_AXG_NCTF_39 VCC_25
BA36 AE17 AE26
VCC_SM_BB24 VCC_SM_36/NC VCC_AXG_NCTF_40 VCC_26
BB24 VCC_SM_37/NC VCC_AXG_NCTF_41 AC17 AC26 VCC_27
VCC_SM_BD16 +1.05VS
VCC

BD16 VCC_SM_38/NC VCC_AXG_NCTF_42 AB17 AH25 VCC_28

BB21 Y17 AG25
VCC_SM_AW16 VCC_SM_39/NC VCC_AXG_NCTF_43 VCC_29
AW16 VCC_SM_40/NC VCC_AXG_NCTF_44 W17 1 AF25 VCC_30
AW13 V17 AG24 AM32
VCC_SM_AT13 VCC_SM_41/NC VCC_AXG_NCTF_45 C1485 + VCC_31 VCC_NCTF_1
AT13 VCC_SM_42/NC VCC_AXG_NCTF_46 AM16 AJ23 VCC_32 VCC_NCTF_2 AL32
AL16 GM@ AH23 AK32
VCC_AXG_NCTF_47 330U_D2E_2.5VM_R15 VCC_33 VCC_NCTF_3
VCC_AXG_NCTF_48 AK16 AF23 VCC_34 VCC_NCTF_4 AJ32
POWER

2
AJ16 T32 AH32
+VGFX_CORE VCC_AXG_NCTF_49 VCC_35 VCC_NCTF_5
VCC_AXG_NCTF_50 AH16 VCC_NCTF_6 AG32
AG16 AE32
VCC_AXG_NCTF_51 VCC_NCTF_7
VCC_AXG_NCTF_52
AF16 Place close to the GMCH VCC_NCTF_8
AC32
Y26 AE16 AA32
VCC_AXG_1 VCC_AXG_NCTF_53 VCC_NCTF_9
AE25 AC16 Y32
VCC_AXG_2 VCC_AXG_NCTF_54 VCC_NCTF_10
AB25 AB16 W32
VCC_AXG_3 VCC_AXG_NCTF_55 VCC_NCTF_11
AA25 AA16 U32
VCC_AXG_4 VCC_AXG_NCTF_56 VCC_NCTF_12
AE24 VCC_AXG_5 VCC_AXG_NCTF_57 Y16 VCC_NCTF_13 AM30
AC24
VCC_AXG_6 VCC_AXG_NCTF_58
W16 VCC_SM: 2600mA VCC_NCTF_14
AL30
AA24 V16 AK30
VCC_AXG_7 VCC_AXG_NCTF_59 +1.8V (330UF*1, 22UF*2, 0.1UF*1) VCC_NCTF_15
Y24 U16 AH30
VCC_AXG_8 VCC_AXG_NCTF_60 VCC_NCTF_16
AE23 AG30
VCC_AXG_9 VCC_NCTF_17
AC23 AF30
VCC_AXG_10 VCC_NCTF_18
AB23 1 AE30
VCC_AXG_11 C126 VCC_NCTF_19
AA23 1 1 1 AC30

NCTF
VCC_AXG_12 330U_D2E_2.5VM_R15 + C123 VCC_NCTF_20
AJ21 AB30
VCC_AXG_13 C130 0.1U_0402_16V4Z VCC_NCTF_21
AG21 AA30
VCC_AXG_14 10U_0805_10V4Z VCC_NCTF_22
AE21 Y30
VCC_AXG_15 2 C122 2 2 2 VCC_NCTF_23
AC21 W30
VCC_AXG_16 10U_0805_10V4Z VCC_NCTF_24
AA21 V30
B VCC_AXG_17 VCC_NCTF_25 B
Y21 VCC_AXG_18 VCC_NCTF_26 U30
VCC

VCC
AH20 VCC_AXG_19 Place on the edge VCC_NCTF_27 AL29
AF20 AK29
VCC_AXG_20 VCC_NCTF_28
AE20 VCC_AXG_21 VCC_NCTF_29 AJ29
AC20
VCC_AXG_22 Reference PILLAR_ROCK CRB Rev1.0 VCC_NCTF_30
AH29
AB20 AG29
VCC_AXG_23 VCC_NCTF_31
AA20 AE29
GFX

VCC_AXG_24 VCC_SM_BA36 VCC_NCTF_32

T17 AC29
VCC_AXG_25 VCC_SM_BB24 VCC_NCTF_33
T16 AA29
VCC_AXG_26 VCC_SM_BD16 VCC_NCTF_34
AM15 VCC_AXG_27 VCC_NCTF_35 Y29
AL15 VCC_SM_AW16 W29
VCC_AXG_28 VCC_SM_AT13 C1488 VCC_NCTF_36
AE15 V29
VCC_AXG_29 @ C1490 VCC_NCTF_37
AJ15 VCC_AXG_30 VCC_NCTF_38 AL28
AH15
VCC_AXG_31 1 1 0.1U_0402_16V7K
1 1 @ 1 VCC_NCTF_39
AK28
AG15 C1486 0.1U_0402_16V7K AL26
VCC_AXG_32 @ VCC_NCTF_40
AF15 AK26
VCC_AXG_33 0.1U_0402_16V7K C1487 C1489 VCC_NCTF_41
AB15 AK25
VCC_AXG_34 2 @ 2 2 @ 2 2 VCC_NCTF_42
AA15 AK24
VCC_AXG_35 0.1U_0402_16V7K 0.1U_0402_16V7K VCC_NCTF_43
Y15 AK23
VCC_AXG_36 VCC_NCTF_44
V15
VCC_AXG_37
U15
VCC_AXG_38
AN14 VCC_AXG_39
AM14
VCC_AXG_40 VCCSM_LF1
U14 AV44
VCC SM LF

VCC_AXG_41 VCC_SM_LF1 VCCSM_LF2

T14 BA37
VCC_AXG_42 VCC_SM_LF2 VCCSM_LF3
AM40
VCC_SM_LF3 VCCSM_LF4
VCC_SM_LF4 AV21
AY5 VCCSM_LF5
@ VCC_AXG_SENSE VCC_SM_LF5 VCCSM_LF6 CANTIGA ES_FCBGA1329 GM45@
T4 PAD AJ14 AM10
@ VSS_AXG_SENSE VCC_AXG_SENSE VCC_SM_LF6 VCCSM_LF7
T5 PAD AH14 BB13
VSS_AXG_SENSE VCC_SM_LF7
1 1 1 1 1 1 1
C139 C140 C141 C142 C143 C144 C145
A A
0.1U_0402_16V7K 0.22U_0402_6.3V6K 0.47U_0603_16V4Z 1U_0402_6.3V6K
2 2 2 2 2 2 2
0.1U_0402_16V7K 0.22U_0402_6.3V6K 1U_0402_6.3V6K
CANTIGA ES_FCBGA1329 GM45@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH(5/7)-VCC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 11 of 52
5 4 3 2 1
 5 4 3 2 1

+1.05VS_HPLL
+1.05VS_DPLLA
+1.05VS L16 1 2
MBK1608121YZF_0603 1 1 +1.05VS 1 2

1
VCCA_HPLL: 24mA C1491 C1492 L17 GM@ 1 1 U2H
+1.05VS
VTT: 852mA
0_1210_5% C1494 R1176
(4.7UF*1, 0.1UF*1) 4.7U_0805_10V4Z C1493 + GM@ 0_0402_5% (270UF*1, 4.7UF*2, 2.2UF*1, 0.47UF*1)
2 2
852mA
Please check Power GM@ PM@ 73mA U13
0.1U_0402_16V4Z 2 VTT_1
source if want VCCA_DPLLA 220U_D2_4VM_R15 +3VS_CRTDAC B27 T13 1

2
2 0.1U_0402_16V4Z VCCA_CRT_DAC_1 VTT_2
support IAMT Please check Power VCCA_DPLLB: 64.8mA A26
VCCA_CRT_DAC_2 VTT_3
U12 1 1 1 1
T12 C71 + C72 C80 C82 C81
+1.05VS_MPLL source if want (220UF*1, 0.1UF*1) VTT_4
U11
120Ohm@100MHz support IAMT 2.69mA
VTT_5
T11 220U_D2_4VM_R15 4.7U_0805_10V4Z 0.47U_0603_16V4Z
+1.05VS_DPLLB VTT_6 2 2 2 2 2

CRT
D L19 1 D
2 +3VS_DACBG A25 VCCA_DAC_BG VTT_7 U10
MBK1608121YZF_0603 1 T10 4.7U_0805_10V4Z 2.2U_0603_6.3V6K
VTT_8

1
VCCA_MPLL: 139.2mA C1495 1 2 B25 VSSA_DAC_BG VTT_9 U9

1
R1177 L18 GM@ 1 1 T9
(22UF*1, 0.1UF*1) 0.5_0603_1% 0_1210_5% C1497 R1178 VTT_10
U8
2 GM@ 0_0402_5% VTT_11
64.8mA VTT_12 T8

VTT
0.1U_0402_16V4Z C1496 PM@ +1.05VS_DPLLA F47 U7

2
2
10U_0805_10V4Z 2 VCCA_DPLLA VTT_13
1 T7

2
GM@ 0.1U_0402_16V4Z VTT_14
+1.05VS_DPLLB L48 VCCA_DPLLB VTT_15 U6
C1498 T6
24mA VTT_16

PLL
22U_0805_6.3V6M +1.05VS_HPLL AD1 VCCA_HPLL VTT_17 U5
2 R96 @ T5
+1.8V_TX_LVDS 139.2mA VTT_18
0_0402_5% 1 +1.05VS_MPLL AE1 V3
C1499 VCCA_MPLL VTT_19
+3VS 1 2 U3
GM@ VTT_20
+VCCA_PEG_BG
VCCA_LVDS: 13.2mA 13.2mA VTT_21
V2

A PEG A LVDS
R97 1000P_0402_50V7K J48 U2
0_0402_5% 2 (1000PF*1) VCCA_LVDS VTT_22
T2
VTT_23
+1.5VS 1 2 J47 V1
+3VS_CRTDAC VSSA_LVDS VTT_24
VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1) 1 VTT_25 U1
Please check Power C89 VCCA_PEG_BG: 0.414mA 0.414mA Please check Power
+3VS 1 2 source if want (0.1UF*1) AD48 source if want
L20 GM@ 0.1U_0402_16V4Z VCCA_PEG_BG
support IAMT VCC_AXF: 321.35mA support IAMT
1

MBK1608301YZF_0603 1 2 +1.05VS_AXF
1 (10UF*1, 1UF*1)
1 C1500 C1502 R1179 50mA
GM@ GM@ 0_0402_5% No CIS Symbol AA48 1 2 +1.05VS
C1501 + 0.1U_0402_16V4Z 0.01U_0402_16V7K PM@ L21 1 +1.05VS_PEGPLL VCCA_PEG_PLL R1180
+1.05VS 2
GM@ 2 2 MBK1608221YZF_0603 1 VCCA_PEG_PLL: 50mA 1 1 0_0603_5%
2

220U_D2_4VM_R15 2 1 1 2 C1504 C1505 C1506

2 C1503 R1181 (0.1UF*1) @
Close to Ball A26, B27 10U_0805_6.3V6M 1_0402_1% 0.1U_0402_16V4Z 480mA 10U_0805_6.3V6M 1U_0402_6.3V6K
2
AR20
VCCA_SM_1
POWER 2 2
+1.05VS_A_SM AP20
C VCCA_SM_2 C
VCCA_SM: AN20 VCCA_SM_3
+1.05VS 1 2 (22UF*2, 4.7UF*1, 1UF*1) AR17
VCCA_SM_4 +1.8V_SM_CK
VCC_SM_CK: 119.85mA

A SM
1 R100 1 1 1 AP17
0_0805_5% C95 C96 VCCA_SM_5 (10UF*1, 0.1UF*1)
AN17 VCCA_SM_6 VCC_AXF_1 B22 1uH 30%
+

AXF
Please check Power C94 C97 AT16 B21 1 2 +1.8V
@ 4.7U_0805_10V4Z VCCA_SM_7 VCC_AXF_2 L22
source if want AR16 A21
220U_D2_4VM_R15 2 2 2 VCCA_SM_8 VCC_AXF_3 MBK1608121YZF_0603
AP16 1
support IAMT 2 22U_0805_6.3V6M 1U_0402_6.3V6K VCCA_SM_9 C1507
1 2 1 2
Please check Power 0.1U_0402_16V4Z R1182 C1508
BF21 2 1_0402_1% 10U_0805_6.3V6M
source if want VCC_SM_CK_1

SM CK
VCCA_DAC_BG: 2.6833333mA support IAMT +1.05VS_A_SM_CK VCC_SM_CK_2
BH20
(0.1UF*1, 0.01UF*1) +3VS_DACBG
VCCA_SM_CK: 24mA VCC_SM_CK_3 BG20
(22UF*1, 2.2UF*1, 0.1UF*1) 24mA VCC_SM_CK_4
BF20
+1.8V_TX_LVDS
+1.05VS 1 2 AP28
VCCA_SM_CK_1 +1.8V_TX_LVDS: 118.8mA
1 2 R103 1 1 1 AN28 0.1uH 20%
+3VS
L23 GM@ 0_0603_5% C102 C103 C105 AP25
VCCA_SM_CK_2 (22UF*1, 1000PF*1) 1 2
VCCA_SM_CK_3 +1.8V
1

MBK1608221YZF_0603 1 1 1 @ AN25 118.8mA 1 1 R1183 GM@

VCCA_SM_CK_4

1
C1509 C1510 C1511 R1184 2.2U_0603_6.3V6K 0.1U_0402_16V4Z AN24 K47 C1512 C1513 0_0603_5%
2 2 2 VCCA_SM_CK_5 VCC_TX_LVDS

A CK
GM@ GM@ @ 0_0402_5% AM28 R1185 GM@ GM@
0.1U_0402_16V4Z 10U_0805_6.3V6M PM@ 22U_0805_6.3V6M VCCA_SM_CK_NCTF_1 PM@ 1000P_0402_50V7K
AM26
2 2 2 VCCA_SM_CK_NCTF_2 2 2 10U_0805_10V4Z
AM25 105.3mA VCC_HV: 105.3mA 0_0402_5%
2

0.01U_0402_16V7K VCCA_SM_CK_NCTF_3
NO_STUFF AL25 C35 +3VS

2
VCCA_SM_CK_NCTF_4 VCC_HV_1
AM24 B35 1
VCCA_SM_CK_NCTF_5 VCC_HV_2

HV
Close to Ball A25 AL24 A35 C107
VCCA_SM_CK_NCTF_6 VCC_HV_3
AM23
VCCA_SM_CK_NCTF_7 Please check Power
AL23 0.1U_0402_16V4Z source if want
VCCA_SM_CK_NCTF_8 2
1782mA support IAMT
VCC_PEG_1
V48 +1.05VS_PEG: 1782mA +1.05VS_PEG
U48
VCC_PEG_2 (220UF*1, 22UF*1, 4.7UF*1)

PEG
VCCA_TV_DAC: 40mA (0.1UF*1, VCC_PEG_3
V47 1 2 +1.05VS
B 0.01UF*1 for each DAC) 87.79mA VCC_PEG_4
U47 1 R1186
B
+3VS_TVDAC B24 U46 1 0_0805_5%
+3VS_TVDAC VCCA_TV_DAC_1 VCC_PEG_5 C1514 + C1515
A24 VCCA_TV_DAC_2

TV
+3VS L24 1 2 VCCD_HDA: 50mA 10U_0805_10V4Z 220U_D2_4VM_R15
MBK1608221YZF_0603 2 2
(0.1UF*1) 50mA 456mA
1

180Ohm@100MHz GM@ 1 2 +1.5VS_HDA A32 AH48 +1.05VS

1 1 +1.5VS VCC_HDA VCC_DMI_1

HDA
C1517 C1516 R1187 R1188 @ 1 AF48
VCC_DMI_2
1

DMI
GM@ GM@ 0_0402_5% 0_0402_5% C1518 Close to A32 AH47
0.1U_0402_16V4Z PM@ R1189 GM@ VCC_DMI_3 +1.05VS_DMI
AG47 1 2
2 2 0_0402_5% 0.1U_0402_16V4Z VCC_DMI_4
58.696mA R1190
2

0.01U_0402_16V7K 2
+1.5VS_TVDAC M25 VCCD_TVDAC VCC_DMI: 456mA 1 0_0805_5%

D TV/CRT
C1519
(0.1UF*1)
2

L28 48.363mA
+1.5VS_QDAC VCCD_QDAC 0.1U_0402_16V4Z
2
VCCD_HPLL: 157.2mA (0.1UF*1) 157.2mA
+1.05VS_HPLL AF1
VCCD_HPLL VTTLF_CAP1
A8
+1.05VS_PEGPLL 50mA VTTLF1 VTTLF_CAP2
Please check Power AA47
VCCD_PEG_PLL VTTLF2
L1

VTTLF
VCCD_TVDAC: 58.696mA source if want AB2 VTTLF_CAP3
+1.5VS_TVDAC VTTLF3
(0.1UF*1, 0.01UF*1) support IAMT 60.31mA
M38 1 1 1
VCCD_LVDS_1
LVDS

+1.5VS 1 2 L37 C110 C111 C112

L25 VCCD_LVDS_2
1 1
MBK1608221YZF_0603 C1520 C1521 Also power for internal VCCD_PEG_PLL: 50mA 0.47U_0603_16V4Z 0.47U_0603_16V4Z
2 2 2
Thermal Sensor (0.1UF*1) CANTIGA ES_FCBGA1329
0.1U_0402_16V4Z GM45@ 0.47U_0603_16V4Z
2 2 +1.8V_LVDS
+1.8V 1 2
0.022U_0402_16V7K R1191 GM@
1

0_0603_5% 1 1
C1522 C1523 R1192
GM@ GM@ 0_0402_5%
10U_0805_6.3V6M 1U_0402_6.3V6K PM@
A 2 2 A
VCCD_QDAC: 48.363mA +1.5VS_QDAC
2

R1194
D8
(0.1UF*1, 0.01UF*1) 2 1 1 2
+1.05VS +3VS
+1.5VS 1 2 VCCD_LVDS: 60.311111mA
R1193 1 1 10_0603_5%
(1UF*1)
1

100_0603_1% C1524 C1525 CH751H-40PT_SOD323-2

180Ohm@100MHz R1195
0.1U_0402_16V4Z 0_0402_5%
2 2 @ Security Classification Compal Secret Data Compal Electronics, Inc.
0.01U_0402_16V7K Issued Date 2008/11/10 2008/11/17 Title
Deciphered Date
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Crestline GMCH (6/7)-VCC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 27, 2008 Sheet 12 of 52
5 4 3 2 1
 5 4 3 2 1

U2I U2J

AU48 VSS_1 VSS_100 AM36 BG21 VSS_199 VSS_297 AH8

AR48 AE36 L12 Y8
VSS_2 VSS_101 VSS_200 VSS_298
AL48 P36 AW21 L8
VSS_3 VSS_102 VSS_201 VSS_299
BB47 L36 AU21 E8
VSS_4 VSS_103 VSS_202 VSS_300
AW47 J36 AP21 B8
VSS_5 VSS_104 VSS_203 VSS_301
AN47 VSS_6 VSS_105 F36 AN21 VSS_204 VSS_302 AY7
AJ47 VSS_7 VSS_106 B36 AH21 VSS_205 VSS_303 AU7
AF47 AH35 AF21 AN7
VSS_8 VSS_107 VSS_206 VSS_304
AD47 AA35 AB21 AJ7
VSS_9 VSS_108 VSS_207 VSS_305
AB47 VSS_10 VSS_109 Y35 R21 VSS_208 VSS_306 AE7
Y47 VSS_11 VSS_110 U35 M21 VSS_209 VSS_307 AA7
T47 VSS_12 VSS_111 T35 J21 VSS_210 VSS_308 N7
D D
N47 VSS_13 VSS_112 BF34 G21 VSS_211 VSS_309 J7
L47 VSS_14 VSS_113 AM34 BC20 VSS_212 VSS_310 BG6
G47 VSS_15 VSS_114 AJ34 BA20 VSS_213 VSS_311 BD6
BD46 AF34 AW20 AV6
VSS_16 VSS_115 VSS_214 VSS_312
BA46 AE34 AT20 AT6
VSS_17 VSS_116 VSS_215 VSS_313
AY46 VSS_18 VSS_117 W34 AJ20 VSS_216 VSS_314 AM6
AV46 B34 AG20 M6
VSS_19 VSS_118 VSS_217 VSS_315
AR46 VSS_20 VSS_119 A34 Y20 VSS_218 VSS_316 C6
AM46 VSS_21 VSS_120 BG33 N20 VSS_219 VSS_317 BA5
V46 BC33 K20 AH5
VSS_22 VSS_121 VSS_220 VSS_318
R46 VSS_23 VSS_122 BA33 F20 VSS_221 VSS_319 AD5
P46 AV33 C20 Y5
VSS_24 VSS_123 VSS_222 VSS_320
H46 VSS_25 VSS_124 AR33 A20 VSS_223 VSS_321 L5
F46 AL33 BG19 J5
VSS_26 VSS_125 VSS_224 VSS_322
BF44 AH33 A18 H5
VSS_27 VSS_126 VSS_225 VSS_323
AH44 AB33 BG17 F5
VSS_28 VSS_127 VSS_226 VSS_324
AD44 VSS_29 VSS_128 P33 BC17 VSS_227 VSS_325 BE4
AA44 L33 AW17
VSS_30 VSS_129 VSS_228
Y44 VSS_31 VSS_130 H33 AT17 VSS_229 VSS_327 BC3
U44 N32 R17 AV3
VSS_32 VSS_131 VSS_230 VSS_328
T44 K32 M17 AL3
VSS_33 VSS_132 VSS_231 VSS_329
M44 F32 H17 R3
VSS_34 VSS_133 VSS_232 VSS_330
F44
BC43
VSS_35
VSS_36
VSS_134
VSS_135
C32
A31
C17 VSS_233 VSS VSS_331
VSS_332
P3
F3
AV43 AN29 BA16 BA2
VSS_37 VSS_136 VSS_235 VSS_333
AU43 VSS_38 VSS_137 T29 VSS_334 AW2
AM43 N29 AU16 AU2
VSS_39 VSS_138 VSS_237 VSS_335
J43 K29 AN16 AR2
VSS_40 VSS_139 VSS_238 VSS_336
C43 VSS_41 VSS_140 H29 N16 VSS_239 VSS_337 AP2
BG42
AY42
VSS_42
VSS_43
VSS VSS_141
VSS_142
F29
A29
K16
G16
VSS_240
VSS_241
VSS_338
VSS_339
AJ2
AH2
AT42 BG28 E16 AF2
C VSS_44 VSS_143 VSS_242 VSS_340 C
AN42 VSS_45 VSS_144 BD28 BG15 VSS_243 VSS_341 AE2
AJ42 BA28 AC15 AD2
VSS_46 VSS_145 VSS_244 VSS_342
AE42 AV28 W15 AC2
VSS_47 VSS_146 VSS_245 VSS_343
N42 VSS_48 VSS_147 AT28 A15 VSS_246 VSS_344 Y2
L42 VSS_49 VSS_148 AR28 BG14 VSS_247 VSS_345 M2
BD41 AJ28 AA14 K2
VSS_50 VSS_149 VSS_248 VSS_346
AU41 VSS_51 VSS_150 AG28 C14 VSS_249 VSS_347 AM1
AM41 AE28 BG13 AA1
VSS_52 VSS_151 VSS_250 VSS_348
AH41 VSS_53 VSS_152 AB28 BC13 VSS_251 VSS_349 P1
AD41 Y28 BA13 H1
VSS_54 VSS_153 VSS_252 VSS_350
AA41 VSS_55 VSS_154 P28
Y41 K28 U24
VSS_56 VSS_155 VSS_351
U41 VSS_57 VSS_156 H28 AN13 VSS_255 VSS_352 U28
T41 F28 AJ13 U25
VSS_58 VSS_157 VSS_256 VSS_353
M41 C28 AE13 U29
VSS_59 VSS_158 VSS_257 VSS_354
G41 BF26 N13
VSS_60 VSS_159 VSS_258
B41 AH26 L13 AF32
VSS_61 VSS_160 VSS_259 VSS_NCTF_1
BG40 AF26 G13 AB32
VSS_62 VSS_161 VSS_260 VSS_NCTF_2
BB40 AB26 E13 V32
VSS_63 VSS_162 VSS_261 VSS_NCTF_3
AV40 VSS_64 VSS_163 AA26 BF12 VSS_262 VSS_NCTF_4 AJ30
AN40 C26 AV12 AM29
VSS_65 VSS_164 VSS_263 VSS_NCTF_5
H40 B26 AT12 AF29
VSS_66 VSS_165 VSS_264 VSS_NCTF_6
E40 BH25 AM12 AB29
VSS_67 VSS_166 VSS_265 VSS_NCTF_7
AT39 BD25 AA12 U26

VSS NCTF
VSS_68 VSS_167 VSS_266 VSS_NCTF_8
AM39 BB25 J12 U23
VSS_69 VSS_168 VSS_267 VSS_NCTF_9
AJ39 AV25 A12 AL20
VSS_70 VSS_169 VSS_268 VSS_NCTF_10
AE39 VSS_71 VSS_170 AR25 BD11 VSS_269 VSS_NCTF_11 V20
N39 AJ25 BB11 AC19
VSS_72 VSS_171 VSS_270 VSS_NCTF_12
L39 AC25 AY11 AL17
VSS_73 VSS_172 VSS_271 VSS_NCTF_13
B39 Y25 AN11 AJ17
VSS_74 VSS_173 VSS_272 VSS_NCTF_14
BH38 N25 AH11 AA17
VSS_75 VSS_174 VSS_273 VSS_NCTF_15
BC38 L25 U17
B VSS_76 VSS_175 VSS_NCTF_16 B
BA38 VSS_77 VSS_176 J25 Y11 VSS_275
AU38 VSS_78 VSS_177 G25 N11 VSS_276
AH38 E25 G11 BH48
VSS_79 VSS_178 VSS_277 VSS_SCB_1
AD38 VSS_80 VSS_179 BF24 C11 VSS_278 VSS_SCB_2 BH1
AA38 AD12 BG10 A48
VSS_81 VSS_180 VSS_279 VSS_SCB_3
Y38 AY24 AV10 C1
VSS SCB

VSS_82 VSS_181 VSS_280 VSS_SCB_4

U38 AT24 AT10 A3
VSS_83 VSS_182 VSS_281 VSS_SCB_5
T38 AJ24 AJ10
VSS_84 VSS_183 VSS_282
J38 AH24 AE10
VSS_85 VSS_184 VSS_283
F38 VSS_86 VSS_185 AF24 AA10 VSS_284
C38 VSS_87 VSS_186 AB24 M10 VSS_285
BF37 R24 BF9 E1
VSS_88 VSS_187 VSS_286 NC_26
BB37 VSS_89 VSS_188 L24 BC9 VSS_287 NC_27 D2
AW37 K24 AN9 C3
VSS_90 VSS_189 VSS_288 NC_28
AT37 VSS_91 VSS_190 J24 AM9 VSS_289 NC_29 B4
AN37 G24 AD9 A5
VSS_92 VSS_191 VSS_290 NC_30
AJ37 F24 G9 A6
VSS_93 VSS_192 VSS_291 NC_31
H37 E24 B9 A43
VSS_94 VSS_193 VSS_292 NC_32
C37 BH23 BH8 A44
VSS_95 VSS_194 VSS_293 NC_33
BG36 AG23 BB8 B45
VSS_96 VSS_195 VSS_294 NC_34
BD36 Y23 AV8 C46
NC

VSS_97 VSS_196 VSS_295 NC_35

AK15 VSS_98 VSS_197 B23 AT8 VSS_296 NC_36 D47
AU36 A23 B47
VSS_99 VSS_198 NC_37
VSS_199 AJ6 NC_38 A46
F48
CANTIGA ES_FCBGA1329 NC_39
E48
GM45@ NC_40
NC_41 C48
B48
NC_42

CANTIGA ES_FCBGA1329
GM45@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga GMCH(1/7)-GTL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 13 of 52
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V

JDIMM1 +1.8V
+DIMM_VREF 1 2
VREF VSS DDRA_SDQ4 +DIMM_VREF
3 4
VSS DQ4

1
DDRA_SDQ0 5 6 DDRA_SDQ5 20mils
DDRA_SDQ1 DQ0 DQ5 R1196
7 DQ1 VSS 8
9 10 DDRA_SDM0
DDRA_SDQS0# VSS DM0 1K_0402_1%
<9> DDRA_SDQS0# DDRA_SDQS0
11
DQS0# VSS
12
DDRA_SDQ6
1 20mils
13 14 C151 To SODIMM and GMCH

2
<9> DDRA_SDQS0 DQS0 DQ6 DDRA_SDQ7
15 VSS DQ7 16 +DIMM_VREF
DDRA_SDQ2 17 18 0.1U_0402_16V4Z
DQ2 VSS

1
DDRA_SDQ3 DDRA_SDQ12 2
19 DQ3 DQ12 20
D DDRA_SDQ13 R1197 D
21 VSS DQ13 22
DDRA_SDQ8 23 24
DDRA_SDQ9 DQ8 VSS DDRA_SDM1 1K_0402_1%
25 DQ9 DM1 26
27 28

2
DDRA_SDQS1# VSS VSS
29 30 DDRA_CLK0 <8>
<9> DDRA_SDQS1# DDRA_SDQS1 DQS1# CK0
<9> DDRA_SDQS1 31 DQS1 CK0# 32 DDRA_CLK0# <8>
33 34
DDRA_SDQ10 VSS VSS DDRA_SDQ14
35 DQ10 DQ14 36
DDRA_SDQ11 37 38 DDRA_SDQ15
DQ11 DQ15 DDRA_SMA[0..14]
39 40 <9> DDRA_SMA[0..14]
VSS VSS
DDRA_SDQ[0..63]
<9> DDRA_SDQ[0..63]
41 VSS VSS 42
DDRA_SDQ16 43 44 DDRA_SDQ20 DDRA_SDM[0..7]
DQ16 DQ20 <9> DDRA_SDM[0..7] +1.8V
DDRA_SDQ17 45 46 DDRA_SDQ21
DQ17 DQ21
47 48
DDRA_SDQS2# VSS VSS
49 DQS2# NC 50 PM_EXTTS#0 <8>
<9> DDRA_SDQS2# DDRA_SDQS2 DDRA_SDM2
51 52
<9> DDRA_SDQS2 DQS2 DM2
53 VSS VSS 54 1 1 1 1 1
DDRA_SDQ18 55 56 DDRA_SDQ22 C152 C147 C153 C154 C155
DDRA_SDQ19 DQ18 DQ22 DDRA_SDQ23
57 58
DQ19 DQ23 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K
59 60
DDRA_SDQ24 VSS VSS DDRA_SDQ28 2 2 2 2 2
61 DQ24 DQ28 62
DDRA_SDQ25 63 64 DDRA_SDQ29 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K
DQ25 DQ29
65 66
DDRA_SDM3 VSS VSS DDRA_SDQS3#
67 DM3 DQS3# 68 DDRA_SDQS3# <9>
69 70 DDRA_SDQS3
NC DQS3 DDRA_SDQS3 <9>
71 72
DDRA_SDQ26 VSS VSS DDRA_SDQ30 +1.8V
73 DQ26 DQ30 74
DDRA_SDQ27 75 76 DDRA_SDQ31 +0.9VS
DQ27 DQ31
77 78
DDRA_CKE0 VSS VSS DDRA_CKE1 DDRA_CKE0
<8> DDRA_CKE0 79 80 DDRA_CKE1 <8> 1 4
C CKE0 NC/CKE1 DDRA_SBS2# C
81 VDD VDD 82 2 3 1 1 1 1
83 84 RP1 56_0404_4P2R_5% C156 C148 C149 C157
DDRA_SBS2# NC NC/A15 DDRA_SMA14
<9> DDRA_SBS2# 85 86
BA2 NC/A14 DDRA_SMA12 0.1U_0402_16V4Z 0.1U_0402_16V4Z
87 VDD VDD 88 1 4
DDRA_SMA12 89 90 DDRA_SMA11 DDRA_SMA9 2 3 2 2 2 2
DDRA_SMA9 A12 A11 DDRA_SMA7 RP2 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
91 92
DDRA_SMA8 A9 A7 DDRA_SMA6
93 A8 A6 94
95 96 DDRA_SMA8 1 4
DDRA_SMA5 VDD VDD DDRA_SMA4 DDRA_SMA5
97 A5 A4 98 2 3
DDRA_SMA3 99 100 DDRA_SMA2 RP3 56_0404_4P2R_5%
DDRA_SMA1 A3 A2 DDRA_SMA0
101 A1 A0 102
103 104 DDRA_SMA3 1 4
DDRA_SMA10 VDD VDD DDRA_SBS1# DDRA_SMA1 +0.9VS
105 A10/AP BA1 106 DDRA_SBS1# <9> 2 3
DDRA_SBS0# 107 108 DDRA_SRAS# RP4 56_0404_4P2R_5%
<9> DDRA_SBS0# DDRA_SWE# BA0 RAS# DDRA_SCS0# DDRA_SRAS# <9>
<9> DDRA_SWE# 109 110 DDRA_SCS0# <8>
WE# S0# DDRA_SMA10
111 112 1 4
DDRA_SCAS# VDD VDD DDRA_ODT0 DDRA_SBS0#
<9> DDRA_SCAS# 113 114 DDRA_ODT0 <8> 2 3 1 1 1 1 1
DDRA_SCS1# CAS# ODT0 DDRA_SMA13 RP5 56_0404_4P2R_5% C158 C159 C160 C161 C162
<8> DDRA_SCS1# 115 116
NC/S1# NC/A13
117 118
DDRA_ODT1 VDD VDD DDRA_SWE# 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
<8> DDRA_ODT1 119 NC/ODT1 NC 120 1 4
121 122 DDRA_SCAS# 2 3 2 2 2 2 2
DDRA_SDQ32 VSS VSS DDRA_SDQ36 RP6 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
123 124
DDRA_SDQ33 DQ32 DQ36 DDRA_SDQ37
125 126
DQ33 DQ37 DDRA_SCS1#
127 128 1 4
DDRA_SDQS4# VSS VSS DDRA_SDM4 DDRA_ODT1
129 130 2 3
<9> DDRA_SDQS4# DDRA_SDQS4 DQS4# DM4 RP7 56_0404_4P2R_5% +0.9VS
131 132
<9> DDRA_SDQS4 DQS4 VSS DDRA_SDQ38
133 VSS DQ38 134
DDRA_SDQ34 135 136 DDRA_SDQ39
DDRA_SDQ35 DQ34 DQ39
137 138
DQ35 VSS DDRA_SDQ44 DDRA_SMA14
139 140 1 4 1 1 1 1 1
DDRA_SDQ40 VSS DQ44 DDRA_SDQ45 DDRA_SMA11 C163 C164 C165 C166 C167
141 142 2 3
DDRA_SDQ41 DQ40 DQ45 RP8 56_0404_4P2R_5%
143 144
B DQ41 VSS DDRA_SDQS5# 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z B
145 VSS DQS5# 146
DDRA_SDM5 DDRA_SDQS5 DDRA_SDQS5# <9> DDRA_SMA7 2 2 2 2 2
147 DM5 DQS5 148 DDRA_SDQS5 <9> 1 4
149 150 DDRA_SMA6 2 3 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ42 VSS VSS DDRA_SDQ46 RP9 56_0404_4P2R_5%
151 DQ42 DQ46 152
DDRA_SDQ43 153 154 DDRA_SDQ47
DQ43 DQ47 DDRA_SMA4
155 156 1 4
DDRA_SDQ48 VSS VSS DDRA_SDQ52 DDRA_SMA2 +0.9VS
157 158 2 3
DDRA_SDQ49 DQ48 DQ52 DDRA_SDQ53 RP10 56_0404_4P2R_5%
159 160
DQ49 DQ53
161 162
VSS VSS DDRA_SMA0
163 NC,TEST CK1 164 DDRA_CLK1 <8> 1 4
165 166 DDRA_SBS1# 2 3 1 1 1
VSS CK1# DDRA_CLK1# <8>
DDRA_SDQS6# 167 168 RP11 56_0404_4P2R_5% C168 C169 C170
<9> DDRA_SDQS6# DDRA_SDQS6 DQS6# VSS DDRA_SDM6
169 DQS6 DM6 170
<9> DDRA_SDQS6 DDRA_SRAS# 0.1U_0402_16V4Z 0.1U_0402_16V4Z
171 172 1 4
DDRA_SDQ50 VSS VSS DDRA_SDQ54 DDRA_SCS0# 2 2 2
173 DQ50 DQ54 174 2 3
DDRA_SDQ51 175 176 DDRA_SDQ55 RP12 56_0404_4P2R_5% 0.1U_0402_16V4Z
DQ51 DQ55
177 178
DDRA_SDQ56 VSS VSS DDRA_SDQ60 DDRA_SMA13
179 180 1 4
DDRA_SDQ57 DQ56 DQ60 DDRA_SDQ61 DDRA_ODT0
181 182 2 3
DQ57 DQ61 RP13 56_0404_4P2R_5%
183 184
DDRA_SDM7 VSS VSS DDRA_SDQS7#
185 186
DM7 DQS7# DDRA_SDQS7 DDRA_SDQS7# <9> DDRA_CKE1
187 VSS DQS7 188 DDRA_SDQS7 <9> 1 2
DDRA_SDQ58 189 190 R1198 56_0402_5%
DDRA_SDQ59 DQ58 VSS DDRA_SDQ62
191 DQ59 DQ62 192
193 194 DDRA_SDQ63
D_CK_SDATA VSS DQ63
<15,16> D_CK_SDATA 195 196
D_CK_SCLK SDA VSS R116 1
<15,16> D_CK_SCLK 197 SCL SAO 198 2 10K_0402_5%
+3VS 199 200 R115 1 2 10K_0402_5%
VDDSPD SA1

FOX_ASOA426-M4R-TR
CONN@
A +3VS A

1 1
DIMM0 REV H:10.1mm (BOT)
C171 C172

0.1U_0402_16V4Z
2
2.2U_0603_6.3V6K 2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM0
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 14 of 52
5 4 3 2 1
 A B C D E

+DIMM_VREF +1.8V

+1.8V +1.8V
1 1
1 1
JDIMM2 C173 C182 + C1526 + C1527
+DIMM_VREF 1 2 @
VREF VSS DDRB_SDQ4 2.2U_0603_6.3V6K 330U_D2E_2.5VM_R15
3 4
DDRB_SDQ0 VSS DQ4 DDRB_SDQ1 2 2
0.1U_0402_16V4Z 2 2
5 6
DDRB_SDQ5 DQ0 DQ5
7 DQ1 VSS 8
9 10 DDRB_SDM0 330U_D2E_2.5VM_R15
DDRB_SDQS0# VSS DM0
11 DQS0# VSS 12
1 <9> DDRB_SDQS0# DDRB_SDQS0 DDRB_SDQ6 1
<9> DDRB_SDQS0 13 DQS0 DQ6 14
15 16 DDRB_SDQ7
DDRB_SDQ2 VSS DQ7
17 DQ2 VSS 18
DDRB_SDQ3 19 20 DDRB_SDQ12
DQ3 DQ12 DDRB_SDQ13
21 22
DDRB_SDQ8 VSS DQ13
23 DQ8 VSS 24
DDRB_SDQ9 25 26 DDRB_SDM1
DQ9 DM1
27 VSS VSS 28
DDRB_SDQS1# 29 30
<9> DDRB_SDQS1# DQS1# CK0 DDRB_CLK0 <8>
DDRB_SDQS1 31 32
<9> DDRB_SDQS1 DQS1 CK0# DDRB_CLK0# <8>
33 VSS VSS 34
DDRB_SDQ10 35 36 DDRB_SDQ14 DDRB_SMA[0..14]
DQ10 DQ14 <9> DDRB_SMA[0..14]
DDRB_SDQ11 37 38 DDRB_SDQ15
DQ11 DQ15 DDRB_SDQ[0..63]
39 40
VSS VSS <9> DDRB_SDQ[0..63]
DDRB_SDM[0..7]
<9> DDRB_SDM[0..7]
41 VSS VSS 42
DDRB_SDQ16 43 44 DDRB_SDQ20
DDRB_SDQ17 DQ16 DQ20 DDRB_SDQ21
45 DQ17 DQ21 46
47 48
DDRB_SDQS2# VSS VSS
49 50 PM_EXTTS#1 <8>
<9> DDRB_SDQS2# DDRB_SDQS2 DQS2# NC DDRB_SDM2
51 52
<9> DDRB_SDQS2 DQS2 DM2
53 VSS VSS 54
DDRB_SDQ18 55 56 DDRB_SDQ22
DDRB_SDQ19 DQ18 DQ22 DDRB_SDQ23
57 58
DQ19 DQ23
59 VSS VSS 60
DDRB_SDQ24 61 62 DDRB_SDQ28
DDRB_SDQ25 DQ24 DQ28 DDRB_SDQ29
63 64
DQ25 DQ29
65 VSS VSS 66
DDRB_SDM3 67 68 DDRB_SDQS3# +1.8V
DM3 DQS3# DDRB_SDQS3 DDRB_SDQS3# <9> +0.9VS
69 70
NC DQS3 DDRB_SDQS3 <9>
71 72
2 DDRB_SDQ26 VSS VSS DDRB_SDQ30 2
73 DQ26 DQ30 74
DDRB_SDQ27 75 76 DDRB_SDQ31 DDRB_SBS2# 1 4 1 1 1 1 1
DQ27 DQ31 DDRB_CKE0 C174 C175 C176 C183 C177
77 78 2 3
DDRB_CKE0 VSS VSS DDRB_CKE1 RP14 56_0404_4P2R_5%
<8> DDRB_CKE0 79 CKE0 NC/CKE1 80 DDRB_CKE1 <8>
81 82 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K
VDD VDD DDRB_SMA12 2 2
2.2U_0603_6.3V6K 2 2
2.2U_0603_6.3V6K 2
83 84 1 4
DDRB_SBS2# NC NC/A15 DDRB_SMA14 DDRB_SMA9
<9> DDRB_SBS2# 85 BA2 NC/A14 86 2 3
87 88 RP15 56_0404_4P2R_5%
DDRB_SMA12 VDD VDD DDRB_SMA11
89 A12 A11 90
DDRB_SMA9 91 92 DDRB_SMA7 DDRB_SMA5 1 4
DDRB_SMA8 A9 A7 DDRB_SMA6 DDRB_SMA8 +1.8V
93 A8 A6 94 2 3
95 96 RP16 56_0404_4P2R_5%
DDRB_SMA5 VDD VDD DDRB_SMA4
97 A5 A4 98
DDRB_SMA3 99 100 DDRB_SMA2 DDRB_SMA3 1 4
DDRB_SMA1 A3 A2 DDRB_SMA0 DDRB_SMA1
101 102 2 3 1 1 1 1
A1 A0 RP17 56_0404_4P2R_5% C178 C179 C180 C181
103 104
DDRB_SMA10 VDD VDD DDRB_SBS1#
105 106 DDRB_SBS1# <9>
DDRB_SBS0# A10/AP BA1 DDRB_SRAS# DDRB_SMA10 0.1U_0402_16V4Z 0.1U_0402_16V4Z
<9> DDRB_SBS0# 107 108 DDRB_SRAS# <9> 1 4
DDRB_SWE# BA0 RAS# DDRB_SCS0# DDRB_SBS0# 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2
<9> DDRB_SWE# 109 110 DDRB_SCS0# <8> 2 3
WE# S0# RP18 56_0404_4P2R_5%
111 VDD VDD 112
DDRB_SCAS# 113 114 DDRB_ODT0
<9> DDRB_SCAS# CAS# ODT0 DDRB_ODT0 <8>
DDRB_SCS1# 115 116 DDRB_SMA13 DDRB_SWE# 1 4
<8> DDRB_SCS1# NC/S1# NC/A13 DDRB_SCAS#
117 118 2 3
DDRB_ODT1 VDD VDD RP19 56_0404_4P2R_5%
<8> DDRB_ODT1 119 120
NC/ODT1 NC
121 122
DDRB_SDQ32 VSS VSS DDRB_SDQ36 DDRB_SCS1#
123 124 1 4
DDRB_SDQ33 DQ32 DQ36 DDRB_SDQ37 DDRB_ODT1 +0.9VS
125 DQ33 DQ37 126 2 3
127 128 RP20 56_0404_4P2R_5%
DDRB_SDQS4# VSS VSS DDRB_SDM4
129 130
<9> DDRB_SDQS4# DDRB_SDQS4 DQS4# DM4
131 132
<9> DDRB_SDQS4 DQS4 VSS DDRB_SDQ38
133 134 1 1 1 1 1
DDRB_SDQ34 VSS DQ38 DDRB_SDQ39 DDRB_SMA11 C184 C185 C186 C187 C188
135 136 1 4
3 DDRB_SDQ35 DQ34 DQ39 DDRB_SMA14 3
137 DQ35 VSS 138 2 3
139 140 DDRB_SDQ44 RP21 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SDQ40 VSS DQ44 DDRB_SDQ45 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z
141 142
DDRB_SDQ41 DQ40 DQ45 DDRB_SMA6
143 DQ41 VSS 144 1 4
145 146 DDRB_SDQS5# DDRB_SMA7 2 3
DDRB_SDM5 VSS DQS5# DDRB_SDQS5 DDRB_SDQS5# <9> RP22 56_0404_4P2R_5%
147 148
DM5 DQS5 DDRB_SDQS5 <9>
149 150
DDRB_SDQ42 VSS VSS DDRB_SDQ46 DDRB_SMA2 +0.9VS
151 152 1 4
DDRB_SDQ43 DQ42 DQ46 DDRB_SDQ47 DDRB_SMA4
153 154 2 3
DQ43 DQ47 RP23 56_0404_4P2R_5%
155 VSS VSS 156
DDRB_SDQ48 157 158 DDRB_SDQ52
DDRB_SDQ49 DQ48 DQ52 DDRB_SDQ53 DDRB_SBS1#
159 160 1 4 1 1 1 1 1
DQ49 DQ53 DDRB_SMA0 C189 C190 C191 C192 C193
161 VSS VSS 162 2 3
163 164 RP24 56_0404_4P2R_5%
NC,TEST CK1 DDRB_CLK1 <8>
165 166 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SDQS6# VSS CK1# DDRB_CLK1# <8> DDRB_SCS0# 2 2 2 2 2
167 168 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z
<9> DDRB_SDQS6# DDRB_SDQS6 DQS6# VSS DDRB_SDM6 DDRB_SRAS#
169 170 2 3
<9> DDRB_SDQS6 DQS6 DM6 RP25 56_0404_4P2R_5%
171 172
DDRB_SDQ50 VSS VSS DDRB_SDQ54
173 174
DDRB_SDQ51 DQ50 DQ54 DDRB_SDQ55 DDRB_SMA13 +0.9VS
175 176 1 4
DQ51 DQ55 DDRB_ODT0
177 178 2 3
DDRB_SDQ56 VSS VSS DDRB_SDQ60 RP26 56_0404_4P2R_5%
179 DQ56 DQ60 180
DDRB_SDQ57 181 182 DDRB_SDQ61
DQ57 DQ61 DDRB_CKE1
183 VSS VSS 184 1 2 1 1 1
DDRB_SDM7 185 186 DDRB_SDQS7# R1199 56_0402_5% C194 C195 C196
DM7 DQS7# DDRB_SDQS7 DDRB_SDQS7# <9>
187 188
DDRB_SDQ58 VSS DQS7 DDRB_SDQS7 <9> 0.1U_0402_16V4Z 0.1U_0402_16V4Z
189 DQ58 VSS 190
DDRB_SDQ59 191 192 DDRB_SDQ62 2 2
0.1U_0402_16V4Z 2
DQ59 DQ62 DDRB_SDQ63
193 194
D_CK_SDATA VSS DQ63
<14,16> D_CK_SDATA 195 196
D_CK_SCLK SDA VSS R119 1
<14,16> D_CK_SCLK 197 198 2 10K_0402_5%
SCL SA0 R118 1
+3VS 199 VDDSPD SA1 200 2 10K_0402_5% +3VS
4 4

FOX_AS0A426-N8RN-7F
CONN@

DIMM1 REV H:5.6mm (BOT)

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 15 of 52
A B C D E
 A B C D E F G H

FSLC FSLB FSLA CPU SRC PCI

+CLK_VDDSRC +CLK_VDD
Clock Generator
L56 L57
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz +1.05VS 2 1
KC FBM-L11-201209-221LMAT_0805
+3VS 2 1
KC FBM-L11-201209-221LMAT_0805
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 266 100 33.3 C1883 C1884 C1885 C1886 C1887 C1888 C1889 C1891 C1892 C1893 C1894 C1895 C1896 C1897
C1882 C1890
10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
0 1 0 200 100 33.3 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

0 1 1 166 100 33.3 U43

1 1
R1755 0_0402_5% +CLK_VDD ICS9LPRS387, PN:SA000020H10
Table : ICS9LPRS387
2 GM@ 1 CLK_DREF_SSC 9 D_CK_SDATA
CLK_DREF_SSC <8> SLG8SP556V, PN:SA000020K00 SDATA D_CK_SDATA <14,15>
CLK_REQ# Control Free-Run CLK_DREF_SSC_1 R1756 0_0402_5%
6 VDDREF D_CK_SCLK
SCLK 10 D_CK_SCLK <14,15>
CR#_10(WLAN) PCIEX10 PCIEX0 2 PM@ 1 19
27M_CLK <18> VDD48
CR#_6(MCH) PCIEX6 PCIEX1 2 GM@ 1CLK_DREF_SSC# CLK_DREF_SSC# <8> 72 VDDCPU CPUT0_LPR_F 71 CLK_CPU_BCLK
CLK_CPU_BCLK <4>
R1827 0_0402_5%
CR#_4(NEW CARD) PCIEX4 12 70 CLK_CPU_BCLK#
VDDPCI CPUC0_LPR_F CLK_CPU_BCLK# <4>
CLK_DREF_SSC#_1
CR#_9(MINI CARDII) PCIEX9 2 PM@ 1 27M_SSC <18> 27 VDDPLL3
R1828 0_0402_5% 68 CLK_MCH_BCLK
CPUT1_LPR_F CLK_MCH_BCLK <7>
SRC7(VGA_CLK): Discrete VGA[Enable] UMA[Disable] 55 VDDSRC CLK_MCH_BCLK#
CPUC1_LPR_F 67 CLK_MCH_BCLK# <7>
+3VS
+CLK_VDDSRC 52 VDDSRC_IO
1 PM@ 2 CLK_PCI4 24 CLK_DREF_96M
SRCT0_LPR/DOTT_96_LPR CLK_DREF_96M <8>
R1829 10K_0402_5%
1 2 CLK_PCI2
Must Close to CLKGEN PIN 28,29 38 VDDSRC_IO
25 CLK_DREF_96M#
SRCC0_LPR/DOTC_96_LPR CLK_DREF_96M# <8>
R1584 10K_0402_5% 62 VDDSRC_IO
CLK_PCI2=1, Trusted Mode Enable(No overclocking allowed) VGA: disable this pair by BIOS
31 CLK_DREF_SSC_1
VDDPLL3_IO 27MHz_NonSS/SRCT1_LPR/SE1 28
@
mount to Enable ITP_CLK CLK_DREF_SSC#_1
1 2 66 VDDCPU_IO 27MHz_SS/SRCC1_LPR/SE2 29
R1585 10K_0402_5% +3VS

CLK_PCI5
23 VDD96_IO CLK_PCIE_SATA
VGA: disable this pair by BIOS
1 2 SRCT2_LPR/SATAT_LPR 32 CLK_PCIE_SATA <26>
2

R1586 10K_0402_5%
2 R1583 @ 33 CLK_PCIE_SATA# 2
SRCC2_LPR/SATAC_LPR CLK_PCIE_SATA# <26>
CLK_PCI5=0, Pin63,64 is SRC_CLK 10K_0402_5% H_STP_CPU# 53
<27> H_STP_CPU# CPU_STOP#
CLK_PCI5=1, Pin63,64 is ITP_CLK H_STP_PCI# CLK_PCIE_ICH
<27> H_STP_PCI# 54 35 CLK_PCIE_ICH <27>
1

CK505_PWRGD PCI_STOP# SRCT3_LPR

1 GM@ 2 CLK_PCI4 36 CLK_PCIE_ICH#
D SRCC3_LPR CLK_PCIE_ICH# <27>
1

R1587 10K_0402_5%
CLK_PCI4=0, Pin28, 29 is SRC_CLK 2 CLK_ENABLE# <49>
G 13 39 CLK_PCIE_CARD
Pin24, 25 is DOT96_CLK Q106 @ PCI1 SRCT4_LPR CLK_PCIE_CARD <34>
S
3

1 @ 2 CK_PWRGD 2N7002_SOT23 CLK_PCI2 14 40 CLK_PCIE_CARD#

PCI2/TME SRCC4_LPR CLK_PCIE_CARD# <34>
R1588 10K_0402_5%
CLK_PCI_LPC R1589 2 1 33_0402_5% CLK_PCI3 15
<35> CLK_PCI_LPC PCI3
57 CLK_MCH_3GPLL
SRCT6_LPR CLK_MCH_3GPLL <8>
@ CLK_PCI4 16
C1898 1 10P_0402_50V8J CLK_PCI_LPC PCI4/27_SELECT CLK_MCH_3GPLL#
2 SRCC6_LPR 56 CLK_MCH_3GPLL# <8>
@ CLK_PCI_ICH R1590 2 1 33_0402_5% CLK_PCI5 17
<25> CLK_PCI_ICH PCI_F5/ITP_EN
C1899 1 2 10P_0402_50V8J CLK_PCI_ICH
61 CLK_PCIE_VGA
SRCT7_LPR CLK_PCIE_VGA <17>
For EMI 10/9 0_0402_5% 2 1 R1591 CK505_PWRGD 1
<27> CK_PWRGD CK_PWRGD/PD#
0_0402_5% 2 @ 1 R1592 60 CLK_PCIE_VGA#
<8,27,49> VGATE SRCC7_LPR CLK_PCIE_VGA# <17>
+1.05VS C1900
CLK_XTALIN CLK_PCIE_READER
UMA: disable this pair by BIOS
1 2 5 X1 CPUT2_ITP_LPR/SRCT8_LPR 64 CLK_PCIE_READER <30>
2

R1593 @ 27P_0402_50V8J CLK_XTALOUT 4 CLK_PCIE_READER#

56_0402_5% Y1 X2 CPUC2_ITP_LPR/SRCC8_LPR 63 CLK_PCIE_READER# <30>
C1901 14.31818MHz_20P_FSX8L14.318181M20FDB
R1594 R1595 27P_0402_50V8J 11 44 CLK_PCIE_MINI2
CLK_PCIE_MINI2 <33>
2

3 2.2K_0402_5% 1K_0402_5% NC SRCT9_LPR 3

1 2
1

CLKSEL0 1 2 1 2 45 CLK_PCIE_MINI2#
MCH_CLKSEL0 <8> SRCC9_LPR CLK_PCIE_MINI2# <33>
CLK_ICH_48M R1596 2 1 33_0402_5% CLKSEL0 20
<27> CLK_ICH_48M USB_48MHz/FSLA
1 2 1 2 CPU_BSEL0 <5> 50 CLK_PCIE_MINI1
SRCT10_LPR CLK_PCIE_MINI1 <33>
R1597 @ R1598 CLKSEL1 2
1K_0402_5% 0_0402_5% FSLB/TEST_MODE CLK_PCIE_MINI1#
SRCC10_LPR 51 CLK_PCIE_MINI1# <33>
CLK_ICH_14M R1599 2 1 33_0402_5% CLKSEL2 7
<27> CLK_ICH_14M FSLC/TEST_SEL/REF0
+1.05VS 8 48 CLK_PCIE_LAN
REF1 SRCT11_LPR CLK_PCIE_LAN <31>
47 CLK_PCIE_LAN#
SRCC11_LPR CLK_PCIE_LAN# <31>
2

R1600 @
1K_0402_5% +3VS 69
R1602 GNDCPU
R1601 4.7K_0402_5% 3 37
GNDREF CR#3
2

1K_0402_5%
G

1 2 +3VS 1 2 +3VS
1

CLKSEL1 1 2 18 41 R1603 10K_0402_5%

MCH_CLKSEL1 <8> GNDPCI CR#4 EXP_CLKREQ# <34>
<27,31,33,34> ICH_SMBDATA 1 3 D_CK_SDATA
22 58
D

GND48 CR#6 MCH_CLKREQ# <8>

1 2 1 2 CPU_BSEL1 <5> Q107 (Pull High to +3VS at GMCH side)
R1604 @ R1605 2N7002_SOT23 30 65
0_0402_5% 0_0402_5% GND CR7#
1 2 +3VS
+3VS 26 43 R1606 10K_0402_5%
GND CR#9 MINI2_CLKREQ# <33>
R1608 1 2 +3VS
4.7K_0402_5% 34 49 R1607 10K_0402_5%
GNDSRC CR10# MINI1_CLKREQ# <33>
2

+1.05VS
G

1 2 +3VS
59 GNDSRC CR#11 46
4 <27,31,33,34> ICH_SMBCLK 1 3 D_CK_SCLK 4
2

R1609 @ 42 21
D

GNDSRC CR#A SATA_CLKREQ# <27>

1K_0402_5% Q108 73 (Pull High to +3VS at ICH side)
2N7002_SOT23 GND_THERMAL_PAD
R1610 R1611 ICS9LPRS387BKLFT_MLF72_10x10
10K_0402_5% 1K_0402_5%
1

CLKSEL2 1 2 1 2 MCH_CLKSEL2 <8> Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title
1
R1612 @
2 1
R1613
2 CPU_BSEL2 <5>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock Generator (CK505)
0_0402_5% 0_0402_5% Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 16 of 52
A B C D E F G H
 A B C D E

LVDS & DAC Interface

U17F
PEG Interface
NB9M-GS_BGA_533P
COMMON

#SI Change to +VDDMEM18 6/13 IFPAB

IFPA_TXD0 V4 VGA_TXOUT0- <22>
V5 +1.1VS
IFPA_TXD0 VGA_TXOUT0+ <22> U17A

NB9M-GS_BGA_533P
600 mA
+VDD_MEM18 100mA AA4
COMMON
IFPA_TXD1 VGA_TXOUT1- <22>
IFPA_TXD1 AA5 VGA_TXOUT1+ <22> 1/13 PCI_EXPRESS 1 1 C252 2 1 C254 1 1 C255
2 1 IFPAB_PLLVDD AD5 IFPAB_PLLVDD PEX_IOVDD AC9 C244 PM@ C253 PM@ C245 PM@
1 1
L7 PM@ IFPAB_RSET AB6 IFPAB_RSET A PEX_IOVDD AD7 PM@ 0.1U_0402_16V4Z PM@ 4.7U_0603_6.3V6M PM@ 0.47U_0402_6.3V6K
BLM18PG181SN1D_0603 IFPA_TXD2 Y4 VGA_TXOUT2- <22> PEX_IOVDD AD8 0.1U_0402_16V4Z 1U_0603_10V4Z 0.47U_0402_6.3V6K
2 2 1 2 2 2
1 1 1 C247 2 IFPA_TXD2 W4 VGA_TXOUT2+ <22> PEX_IOVDD AE7

1
C246 PM@ PEX_IOVDD AF7
C257 PM@ 4700P_0402_25V7K PEX_IOVDD AG7
PM@ 4.7U_0603_6.3V6M C248 R205 IFPA_TXD3 AB5
2 2 2 1 PM@ @ IFPA_TXD3 AB4
4.7U_0603_6.3V6M 470P_0402_50V7K 1K_0402_1% PEX_IOVDDQ AB13 +1.1VS

2
DATA PEX_IOVDDQ AB16
IFPB_TXD4 V1 PEX_IOVDDQ AB17 1 1
0.47U_0402_6.3V6K
2
C259
1.920 Amps
IFPB_TXD4 W1 PEX_IOVDDQ AB7
AE9 RFU PEX_IOVDDQ AB8 C258 C249 PM@
PEX_IOVDDQ AB9 PM@ PM@ 1U_0603_10V4Z
2
0.1U_0402_16V4Z 2 1
#SI Change to +VDDMEM18 IFPB_TXD5 W2
R204 PM@
PEX_IOVDDQ AC13
IFPB_TXD5 W3 PEX_IOVDDQ AC7
+VDD_MEM18 0_0402_5% PEX_IOVDDQ AD6
100 mA B <8,25,27,30,31,35> PLT_RST# 1 2 PEX_RST# AD9 PEX_RST PEX_IOVDDQ AE6
2 1 IFPA_IOVDD V3 IFPA_IOVDD IFPB_TXD6 AA3 PEX_IOVDDQ AF6
L8 PM@ IFPB_TXD6 AA2 PEX_IOVDDQ AG6
BLM18PG181SN1D_0603 1 1 2 IFPB_IOVDD V2 IFPB_IOVDD 2 1 1
C266 C267 PEX_REFCLKP AB10 PEX_REFCLK C262
<16> CLK_PCIE_VGA
C251 PM@ PM@ IFPB_TXD7 AA1 PEX_REFCLKN AC10 PEX_REFCLK PM@ C263 C264
<16> CLK_PCIE_VGA#
PM@ 4700P_0402_25V7K 470P_0402_50V7K IFPB_TXD7 AB1 PM@ PM@
2 4.7U_0603_6.3V6M 2 1 PM@C265 1
PM@C265 1 2 2 10U_0805_6.3V6M
<10> PCIE_GTX_C_MRX_P0 2 0.1U_0402_16V4Z PEX_TXP0 AD10 PEX_TX0
PM@C268
PM@C268 1 2 0.1U_0402_16V4Z PEX_TXN0 AD11 PEX_TX0 4.7U_0603_6.3V6M
<10> PCIE_GTX_C_MRX_N0
IFPA_TXC AD4 VGA_TXCLK- <22> 1U_0603_10V4Z
A IFPA_TXC AC4 VGA_TXCLK+ <22> <10> PCIE_MTX_C_GRX_P0 AE12 PEX_RX0
<10> PCIE_MTX_C_GRX_N0 AF12 PEX_RX0
CLOCK
IFPB_TXC AB2 PM@C270
PM@C270 1 2 0.1U_0402_16V4Z PEX_TXP1 AD12 PEX_TX1 VDD J10 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +VGA_CORE
<10> PCIE_GTX_C_MRX_P1
B IFPB_TXC AB3 <10> PCIE_GTX_C_MRX_N1
PM@C271 1
PM@C271 2 0.1U_0402_16V4Z PEX_TXN1 AC12 PEX_TX1 VDD J12
1 2 C280 VDD J13 1 1 1 1 1 1
C279 PM@ PM@ <10> PCIE_MTX_C_GRX_P1 AG12 PEX_RX1 VDD J9
PM@ 470P_0402_50V7K <10> PCIE_MTX_C_GRX_N1 AG13 PEX_RX1 VDD L9 C273 C274 C275 C276 C277 C278
4700P_0402_25V7K VDD M11 PM@ PM@ PM@ PM@ PM@ PM@
2 1 PM@C281 1
PM@C281 2 2 2 2 2 2
<10> PCIE_GTX_C_MRX_P2 2 0.1U_0402_16V4Z PEX_TXP2 AB11 PEX_TX2 VDD M17
PM@C282
PM@C282 1 2 0.1U_0402_16V4Z PEX_TXN2 AB12 PEX_TX2 VDD M9
<10> PCIE_GTX_C_MRX_N2
VDD N11 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
<10> PCIE_MTX_C_GRX_P2 AF13 PEX_RX2 VDD N12
2 <10> PCIE_MTX_C_GRX_N2 AE13 PEX_RX2 VDD N13 2
VDD N14
PM@C283 1
PM@C283 2 0.1U_0402_16V4Z PEX_TXP3 AD13 PEX_TX3 VDD N15 0.1U_0402_16V4Z 22u X 3
<10> PCIE_GTX_C_MRX_P3
PM@C284
PM@C284 1 2 0.1U_0402_16V4Z PEX_TXN3 AD14 PEX_TX3 VDD N16 22U_0805_6.3V6M
<10> PCIE_GTX_C_MRX_N3
VDD N17 1 1 1 1 1 0.47u X 7
<10> PCIE_MTX_C_GRX_P3 AE15 PEX_RX3 VDD N19 C289
<10> PCIE_MTX_C_GRX_N3 AF15 PEX_RX3 VDD N9 C285 C286 C287 C288 PM@ 0.1u X 7
VDD P11 PM@ PM@ PM@ PM@
PM@C291 1
PM@C291 2 2 2 2 2
<10> PCIE_GTX_C_MRX_P4 2 0.1U_0402_16V4Z PEX_TXP4 AD15 PEX_TX4 VDD P12
PM@C292
PM@C292 1 2 0.1U_0402_16V4Z PEX_TXN4 AC15 PEX_TX4 VDD P13 22U_0805_6.3V6M 22U_0805_6.3V6M
<10> PCIE_GTX_C_MRX_N4
VDD P14 0.47U_0402_6.3V6K
<10> PCIE_MTX_C_GRX_P4 AG15 PEX_RX4 VDD P15
<10> PCIE_MTX_C_GRX_N4 AG16 PEX_RX4 VDD P16
VDD P17
PM@C293 1
PM@C293 2 0.1U_0402_16V4Z PEX_TXP5 AB14 PEX_TX5 VDD R11 0.47U_0402_6.3V6K 0.47U_0402_6.3V6K 0.47U_0402_6.3V6K
<10> PCIE_GTX_C_MRX_P5
PM@C294
PM@C294 1 2 0.1U_0402_16V4Z PEX_TXN5 AB15 PEX_TX5 VDD R12
<10> PCIE_GTX_C_MRX_N5
VDD R13 1 1 1 1 1 1
U17D <10> PCIE_MTX_C_GRX_P5 AF16 PEX_RX5 VDD R14
<10> PCIE_MTX_C_GRX_N5 AE16 PEX_RX5 VDD R15 C295 C296 C297 C298 C299 C300
NB9M-GS_BGA_533P VDD R16 PM@ PM@ PM@ PM@ PM@ PM@
COMMON
PM@C301 1
PM@C301 2 2 2 2 2 2
<10> PCIE_GTX_C_MRX_P6 2 0.1U_0402_16V4Z PEX_TXP6 AC16 PEX_TX6 VDD R17
5/13 DACC PM@C302
PM@C302 1 2 0.1U_0402_16V4Z PEX_TXN6 AD16 PEX_TX6 VDD R9
<10> PCIE_GTX_C_MRX_N6
1 R206 2 W5 DACC_VDD VDD T11 0.47U_0402_6.3V6K 0.47U_0402_6.3V6K 0.47U_0402_6.3V6K
<10> PCIE_MTX_C_GRX_P6 AE18 PEX_RX6 VDD T17
PM@ 10K_0402_5% R6 DACC_VREF <10> PCIE_MTX_C_GRX_N6 AF18 PEX_RX6 VDD T9
VDD U19
V6 DACC_HSYNC U6 PM@C303 1
PM@C303 2 0.1U_0402_16V4Z PEX_TXP7 AD17 U9
DACC_RSET
DAC C DACC_VSYNC U4
<10> PCIE_GTX_C_MRX_P7
<10> PCIE_GTX_C_MRX_N7
PM@C304
PM@C304 1 2 0.1U_0402_16V4Z PEX_TXN7 AD18
PEX_TX7
PEX_TX7
VDD
VDD
VDD
W10
W12
<10> PCIE_MTX_C_GRX_P7 AG18 PEX_RX7 VDD W13
DACC_RED T5 <10> PCIE_MTX_C_GRX_N7 AG19 PEX_RX7 VDD W18
VDD W19
DACC_GREEN T4 PM@C305 1
PM@C305 2 0.1U_0402_16V4Z PEX_TXP8 AC18 PEX_TX8 VDD W9
<10> PCIE_GTX_C_MRX_P8
PM@C306
PM@C306 1 2 0.1U_0402_16V4Z PEX_TXN8 AB18 PEX_TX8
<10> PCIE_GTX_C_MRX_N8
DACC_BLUE R4 PM@ R392 0_0402_5%
<10> PCIE_MTX_C_GRX_P8 AF19 PEX_RX8 VDD_SENSE W15 1 2 +NVVDD_SENSE
<10> PCIE_MTX_C_GRX_N8 AE19 PEX_RX8 GND_SENSE W16

PM@C307 1
PM@C307 2 0.1U_0402_16V4Z PEX_TXP9 AB19 PEX_TX9
<10> PCIE_GTX_C_MRX_P9
PM@ PM@C308
PM@C308 1 2 0.1U_0402_16V4Z PEX_TXN9 AB20 PEX_TX9
3 <10> PCIE_GTX_C_MRX_N9 +3VS 3

<10> PCIE_MTX_C_GRX_P9 AE21 PEX_RX9 110 mA VDD33

<10> PCIE_MTX_C_GRX_N9 AF21 PEX_RX9 VDD33 A12
B12

1U_0603_10V4Z
VDD33

0.1U_0402_16V4Z

0.1U_0402_16V4Z
U17C PM@C309 1
PM@C309 2 0.1U_0402_16V4Z PEX_TXP10 AD19 PEX_TX10 VDD33 C12 1 1 1

CRT
<10> PCIE_GTX_C_MRX_P10
PM@C310
PM@C310 1 2 0.1U_0402_16V4Z PEX_TXN10 AD20 PEX_TX10 VDD33 D12
<10> PCIE_GTX_C_MRX_N10 C311
BLM18PG181SN1D_0603 NB9M-GS_BGA_533P VDD33 E12 C1476 C314
COMMON
150 mA <10> PCIE_MTX_C_GRX_P10 AG21 PEX_RX10 VDD33 F12 PM@ PM@ PM@
2 2 2
3/13 DACA <10> PCIE_MTX_C_GRX_N10 AG22 PEX_RX10
+3VS 2 1 DACA_VDD AG2 DACA_VDD
L9 PM@ PM@C315 1
PM@C315 2 0.1U_0402_16V4Z PEX_TXP11 AD21 PEX_TX11
<10> PCIE_GTX_C_MRX_P11
DACA_VREF AF1 DACA_VREF PM@C316
PM@C316 1 2 0.1U_0402_16V4Z PEX_TXN11 AC21 PEX_TX11
<10> PCIE_GTX_C_MRX_N11
AE1 AD2 AF22
4700P_0402_25V7K

470P_0402_50V7K

DACA_RSET DACA_HSYNC PEX_RX11

1U_0402_6.3V6K

0.1U_0402_16V4Z

VGA_CRT_HSYNC <23> <10> PCIE_MTX_C_GRX_P11

1
124_0402_1%

AD1 AE22
1
C317
1
C319
1
C320
1
C321 R207
DAC A DACA_VSYNC VGA_CRT_VSYNC <23> <10> PCIE_MTX_C_GRX_N11

<10> PCIE_GTX_C_MRX_P12
PM@C322 1
PM@C322 2 0.1U_0402_16V4Z PEX_TXP12 AB21
PEX_RX11

PEX_TX12 120mA
PM@ PM@ PM@ PM@ PM@ DACA_RED AE2 PM@C323
PM@C323 1 2 0.1U_0402_16V4Z PEX_TXN12 AB22 PEX_TX12
2 2 2 2 VGA_CRT_R <23> <10> PCIE_GTX_C_MRX_N12
PEX_PLLVDD AF9 PEX_PLLDVDD 2 1 +1.1VS
2

DACA_GREEN AE3 <10> PCIE_MTX_C_GRX_P12 AE24 PEX_RX12 L10 PM@

VGA_CRT_G <23>
AF24 PEX_RX12 1 1 1 1 BLM18PG181SN1D_0603

1U_0402_6.3V6K
0.01U_0402_25V7K
0.1U_0402_16V4Z

4.7U_0603_6.3V6M
<10> PCIE_MTX_C_GRX_N12
DACA_BLUE AD3 VGA_CRT_B <23>
PM@C324 1
PM@C324 2 0.1U_0402_16V4Z PEX_TXP13 AC22 PEX_TX13 C327 C325 C446 C447
<10> PCIE_GTX_C_MRX_P13
PM@C326
PM@C326 1 2 0.1U_0402_16V4Z PEX_TXN13 AD22 PEX_TX13 PM@ PM@ PM@ PM@
<10> PCIE_GTX_C_MRX_N13 2 2 2 2
<10> PCIE_MTX_C_GRX_P13 AG24 PEX_RX13
1

PM@ <10> PCIE_MTX_C_GRX_N13 AF25 PEX_RX13

150_0402_1%

150_0402_1%

150_0402_1%

PM@C328 1
PM@C328 2 0.1U_0402_16V4Z PEX_TXP14 AD23 PEX_TX14
<10> PCIE_GTX_C_MRX_P14
PM@C329
PM@C329 1 2 0.1U_0402_16V4Z PEX_TXN14 AD24 PEX_TX14
<10> PCIE_GTX_C_MRX_N14
@ R208 200_0402_1%

TV-OUT
2

U17E <10> PCIE_MTX_C_GRX_P14 AG25 PEX_RX14 PEX_TSTCLK_OUT AF10 1 2

<10> PCIE_MTX_C_GRX_N14 AG26 PEX_RX14 PEX_TSTCLK_OUT AE10
NB9M-GS_BGA_533P R195 R196 R197
COMMON
PM@ PM@ PM@ PM@C330 1
PM@C330 2 0.1U_0402_16V4Z PEX_TXP15AE25 PEX_TX15
<10> PCIE_GTX_C_MRX_P15
R210 4/13 DACB PM@C331
PM@C331 1 2 0.1U_0402_16V4Z PEX_TXN15AE26 PEX_TX15 RFU AG9
<10> PCIE_GTX_C_MRX_N15
1 2 DACB_VDD D7 DACB_VDD
<10> PCIE_MTX_C_GRX_P15 AF27 PEX_RX15 PEX_TERMP AG10 1 2
PM@ 10K_0402_5% G6 DACB_VREF <10> PCIE_MTX_C_GRX_N15 AE27 PEX_RX15
4 R209 PM@ 4
F8 DACB_RSET 2.49K_0402_1%
#SI Remove TV out PM@
DACB_CSYNC D6

DAC B DACB_RED F7

DACB_GREEN E7

DACB_BLUE E6

#SI Remove TV out Security Classification

Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title
PM@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PEG & LVDS & DAC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom kAL90KALH0 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, November 20, 2008 Sheet 17 of 52
A B C D E
 5 4 3 2 1

U17H
+3VS #SI Change to +VDDMEM18 NB9M-GS_BGA_533P
COMMON

7/13 IFPC

1
+VDD_MEM18 BLM18PG181SN1D_0603
U17L
160 mA MXM DVI DP
R211 @ 2 1 IFPC_PLLVDD P6 IFPC_PLLVDD
NB9M-GS_BGA_533P 10K_0402_5% L12 PM@ IFPC_RSET R5 IFPC_RSET
COMMON

4700P_0402_25V7K

470P_0402_50V7K
1U_0402_6.3V6K

4.7U_0603_6.3V6M
2

1
11/13 MISC 1 1 1 1
Must near connector for eye pattern

C337

1K_0402_1%
IFPC_AUX G5

C338

C340

C341

PM@ R212
ROM_CS B10 ROM_CS# IFPC_AUX G4
STRAP0 C7 STRAP0
2 2 2 2

PM@
STRAP1 B9 STRAP1 ROM_SI A10 ROM_SI

2
PM@

PM@

PM@
STRAP2 A9 STRAP2 ROM_SO C10 ROM_SO IFPC_L3 J4 HDMI_C_CLK- PM@ C1474 1 2 0.1U_0402_16V4Z
TXD0 TXD0 VGA_HDMI_TXC- <24>
ROM_SCLK C9 ROM_SCLK IFPC_L3 H4 HDMI_C_CLK+ PM@ C1475 1 2 0.1U_0402_16V4Z
R213 2.2K_0402_5% C TXD0 TXD0 VGA_HDMI_TXC+ <24>
R214 PM@ PM@ 1 2 +3VS IFPC_L2 K4 HDMI_C_TX0- PM@ C1468 1 2 0.1U_0402_16V4Z VGA_HDMI_TXD0- <24>
D TXD1 TXD2 D
40.2K_0402_1% A3 HDCP_SCL L4 HDMI_C_TX0+ PM@ C1469 1 2 0.1U_0402_16V4Z
1 2 F11 STRAP_REF_3V3
I2CH_SCL
I2CH_SDA A4 HDCP_SDA +1.1VS BLM18PG181SN1D_0603 385 mA TXD1 TXD2 IFPC_L2 VGA_HDMI_TXD0+ <24>
2 1 +3VS TXD2 TXD1 IFPC_L1 M4 HDMI_C_TX1- PM@ C1470 1 2 0.1U_0402_16V4Z VGA_HDMI_TXD1- <24>
1 2 F10 STRAP_REF_MIOB 2.2K_0402_5% R215 2 1 IFPC_IOVDD J6 IFPC_IOVDD TXD2 TXD1 IFPC_L1 M5 HDMI_C_TX1+ PM@ C1471 1 2 0.1U_0402_16V4Z VGA_HDMI_TXD1+ <24>
40.2K_0402_1% PM@ #PV2 change R213,R215 form 10K to 2.2K. L13 PM@

4700P_0402_25V7K

470P_0402_50V7K
1U_0402_6.3V6K

4.7U_0603_6.3V6M
R216 PM@ 1 1 1 1 TXC TXC IFPC_L0 N4 HDMI_C_TX2- PM@ C1472 1 2 0.1U_0402_16V4Z VGA_HDMI_TXD2- <24>
PM@ C1473 1 2 0.1U_0402_16V4Z

C342

C343

C346

C347
BUFRST N5 TXC TXC IFPC_L0 P4 HDMI_C_TX2+ VGA_HDMI_TXD2+ <24>

F9 SPDIF RFU J5
+3VS 2 2 2 2

PM@

PM@

PM@

PM@
RFU F6
U17G PM@
1

SPDIF 10K_0402_5% TESTMODE AD25

R217 C15 RFU
@ D15 RFU

1
C349 @ RFU_GND AC6 NB9M-GS_BGA_533P
2

COMMON
1 2 SPDIF_IN 10K_0402_5%
<38> SPDIF_HDMI
R218 8/13 IFPE
1

0.01U_0402_25V7K PM@ PM@

MXM DVI DP
36K_0402_5%

VGA Thermal Sensor

2
R220 N6 IFPE_PLLVDD
PM@ M6 IFPE_RSET

1
R234
ADM1032ARMZ

1K_0402_5%
2

IFPE_AUX D4
+3VS

PM@
Closed to VGA IFPE_AUX D3

2
C348 2 IFPE_L3 B4
TXD0 TXD0
@ IFPE_L3 B3
E TXD0 TXD0

2
+3VS +3VS 0.1U_0402_16V4Z
#SI2 change to pull hi R219 IFPE_L2 C4
1 TXD1 TXD2
PM@
HDCP 2 IFPE_L2 C3
0.1U_0402_16V4Z

TXD1 TXD2
U6 10K_0402_5%
1

ROM 1 8 VGA_SM_CLK TXD2 TXD1 IFPE_L1 D5

1
C351 10K_0402_5% VDD SCLK
H6 IFPE_IOVDD TXD2 TXD1 IFPE_L1 E4
PM@1 R221 VGA_THERMDA 2 7 VGA_SM_DA
D+ SDATA

1
@ C350 @

R236

1K_0402_5%
TXC TXC IFPE_L0 F4
C U7 1 2 VGA_THERMDC 3 6 THERM_SCI# IFPE_L0 F5 C
THERM_SCI# TXC TXC
2

HDCP_WP HDCP_SCL D- ALERT#

1 8
A0 VCC

PM@
2 7 HDCP_WP 2200P_0402_50V7K THERM#_VGA 4 5
A1 WP THERM# GND
1

1
3 6 HDCP_SCL

2
A2 SCL HDCP_SDA 10K_0402_5% 10K_0402_5% R222 @
4 5
GND SDA R223 R224 ADM1032ARMZ REEL_MSOP8
+3VS 1 2
AT24C16BN PM@ @ @ PM@
PM@ 10K_0402_5%
2

+3VS

U17K
VGA_DDC_CLK 2K_0402_5% 1 PM@ 2 R227
NB9M-GS_BGA_533P VGA_DDC_DATA 2K_0402_5% 1 PM@ 2 R230
COMMON
36 mA R238 0_0402_5%
12/13 XTAL_PLL 1 2 VGA_SM_DA DDC2_CLK 2K_0402_5% 1 PM@ 2 R231
<4,35,36> EC_SMB_DA2
BLM18PG181SN1D_0603 PM@ DDC2_DATA 2K_0402_5% 1 PM@ 2 R232
+1.1VS 2
PM@ L14
1 GPU_PLLVDD K5 PLLVDD GPIO I/O ACTIVE USAGE
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1 1 1 1 K6 VID_PLLVDD
1U_0402_6.3V6K

C497 C352 C353 C354 C355

GPIO0 IN N/A Primary DVI Hot-plug R239 0_0402_5%
L6 SP_PLLVDD
4.7U_0603_6.3V6M PM@ PM@ PM@ PM@ 1 2 VGA_SM_CLK
2 2 2 2 2 <4,35,36> EC_SMB_CK2
1 PM@ GPIO1 IN N/A 2nd DVI Hot-plug PM@
22U_0805_6.3V6M

C1528 NB9M-GS_BGA_533P U17M

COMMON
PM@
2 <16> 27M_SSC D11 XTAL_SSIN XTAL_OUTBUFF E9 GPIO2 OUT H Panel Back-Light PWM 9/13 I2C_GPIO_THERM_JTAG
1

1
R1 VGA_DDC_CLK
R228 XTALIN D10 XTAL_IN XTAL_OUT E10XTALOUT R229 GPIO3 OUT H Panel Power Enable
I2CA_SCL
I2CA_SDA T3 VGA_DDC_DATA
VGA_DDC_CLK
VGA_DDC_DATA
<23>
<23>
CRT
10K_0402_5% 1 1 10K_0402_5%
PM@ PM@ PM@ VGA_THERMDC D8 THERMDN I2CB_SCL R2 I2CB_SCL PAD T36 @
C356 C357 @ GPIO4 OUT H Panel Back-Light Enable I2CB_SDA R3 I2CB_SDA PAD T37 @
2

18P_0402_50V8J 18P_0402_50V8J VGA_THERMDA D9 THERMDP

2 @ 2 DDC2_CLK
A2
GPIO5 OUT N/A NVVDD VID0
I2CC_SCL
I2CC_SDA B1 DDC2_DATA
I2CC_SCL <22>
I2CC_SDA <22>
LVDS
@ PAD JTAG_TCK AF3 JTAG_TCK
T6
@ JTAG_TMS AF4 N2
B
GPIO6 OUT N/A NVVDD VID1 @
T7 PAD
PAD JTAG_TDI AG4
JTAG_TMS
JTAG_TDI
I2CD_SCL
I2CD_SDA N3
VGA_HDMI_SCLK
VGA_HDMI_SDATA
<24>
<24>
HDMI B
T8
XTALIN @ PAD JTAG_TDO AE4 JTAG_TDO
<16> 27M_CLK T9
@ PAD JTAG_TRST AG3 JTAG_TRST I2CE_SCL Y6 I2CE_SCL PAD T43 @
T10
1

GPIO7 OUT N/A FBVDD VID0 I2CE_SDA W6 I2CE_SDA PAD T44 @

R235
10K_0402_5%
@ GPIO8 IN L Thermal Alert GPIO0 N1
GPIO1 G1 HDMI_DET <24>
2

0_0402_5% R225 GPIO2 C1

GPIO9 OUT L FAN PWM DDC2_CLK 2 @ 1 VGA_SM_CLK T1 I2CS_SCL GPIO3 M2 ENVDD ENVDD <22>
DDC2_DATA 2 @ 1 VGA_SM_DA T2 I2CS_SDA GPIO4 M3 ENBKL <10,35>
0_0402_5% R226 GPIO5 K3 GPU_VID0 <50>
GPIO10 OUT N/A FBVref Select GPIO6 K2 GPU_VID1 <50>
GPIO7 J2
GPIO8 C2 THERMAL ALERT 1 PM@ 2 R396 0_0402_5% THERM#_VGA
GPIO11 OUT N/A SLI SYNCO GPIO9 M1 SINN_GPIO9 1 PM@ 2 R395 0_0402_5% THERM_SCI#
GPIO10 D2
GPU_VID1 GPU_VID0 +VGA_CORE GPIO11 D1

Straps GPIO12 IN N/A AC Detect

0 0 0.9V
GPIO12
GPIO13
GPIO14
J3
J1
K1
GPIO13 OUT L PS Control or HDMI_CEC GPIO15 F3
GPIO16 G3
MULTI LEVEL STRAPS GPIO14 OUT H PS Control
0 1 1.17V GPIO17
GPIO18
G2
F1 #SI Add GPU_VID1
GPIO19 F2

DDR2 Resistor Value VGA_HDMI_TXC-

1 0 unused
STRAP0 VGA_HDMI_TXC+
STRAP1 Locating R248 VGA_HDMI_TXD0-
STRAP2 16MX16 Hynix 20 Kohms VGA_HDMI_TXD0+ PM@
ROM_SI 16MX16 Samsung 10 Kohms VGA_HDMI_TXD1-
ROM_SO 32MX16 Hynix 45 Kohms VGA_HDMI_TXD1+ U17I
ROM_SCLK 32MX16 Samsung 30 Kohms VGA_HDMI_TXD2-
+3VS 64MX16 Samsung 10 Kohms VGA_HDMI_TXD2+ NB9M-GS_BGA_533P
HD AUDIO
COMMON
64MX16 Hynix 5.1 Kohms

@ 10/13 HDAUDIO
1 2 1 PM@ 2
1

1
R242 5.1K_0402_5% R243 45.3K_0402_1%
PM@ R960

PM@ R961

PM@ R962

PM@ R963

PM@ R964

PM@ R965

PM@ R966

PM@ R967
499_0402_1%

499_0402_1%

499_0402_1%

499_0402_1%

499_0402_1%

499_0402_1%

499_0402_1%

499_0402_1%
HDA_BCLK A7 HDA_BITCLK_VGA <26>
A A
1 PM@ 2 1 @ 2 HDA_SYNC B7 HDA_SYNC_VGA <26>
R244 10K_0402_1% R245 5.1K_0402_5% HDA_SDI A6 HDA_SDIN2_R R399 33_0402_5% 1 PM@ 2 HDA_SDIN3 <26>
HDA_SDO B6 HDA_SDOUT_VGA <26>
2

1 @ 2 1 PM@ 2 HDA_RST C6 HDA_RST_VGA# <26>

R246 5.1K_0402_5% R247 10K_0402_5%
9/21 R329 near GPU
1 PM512M@ 2 1 @ 2 #SI2 add 2N7002 to GND 1 R237 2
R248 5.1K_0402_5% R249 5.1K_0402_5% 9/21 R237, R238, R240, R241 near ICH @
10K_0402_5%
1

@ PM@ 2 D
1 2 1
R250 5.1K_0402_5% R251 5.1K_0402_5% 2 Q74 PM@
+3VS
G 2N7002_SOT23-3 Security Classification Compal Secret Data Compal Electronics, Inc.
1 PM@ 2 1 @ 2 S Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title
3

R252 15K_0402_5% R253 5.1K_0402_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Straps & HDMI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom kAL90KALH0 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, November 20, 2008 Sheet 18 of 52
5 4 3 2 1
 A

VRAM Interface +VDD_MEM18 1

PJP1
2 +1.8VS

PAD-OPEN 3x3m

@ #SI2 change to short pad

MDA[15..0]
<20> MDA[15..0]
U17B U17J
MDA[31..16]
<20> MDA[31..16] NB9M-GS_BGA_533P NB9M-GS_BGA_533P
MDA[47..32] COMMON COMMON
<21> MDA[47..32]
2/13 FRAME_BUFFER +VDD_MEM18 13/13 GND_NC
MDA[63..48] MDA0 D21 FBA_D0
<21> MDA[63..48]
MDA1 C22 FBA_D1 AC11 GND NC AA6
MDA2 B22 FBA_D2 AC14 GND NC AC19

C358

C366

C359

C360

C367

C368
MDA3 A22 FBA_D3 1 1 1 1 1 1 AC17 GND NC E15

0.022U_0402_16V7K

0.022U_0402_16V7K

0.022U_0402_16V7K

0.1U_0402_16V4Z

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
MDA4 C24 FBA_D4 FBVDDQ A13 AC2 GND NC T6
MDA5 B25 FBA_D5 FBVDDQ B13 AC20 GND

PM@

PM@

PM@

PM@

PM@

PM@
MDA6 A25 FBA_D6 FBVDDQ C13 AC23 GND
MDA7 2 2 2 2 2 2
A26 FBA_D7 FBVDDQ D13 AC26 GND
MDA8 D22 FBA_D8 FBVDDQ D14 AC5 GND
MDA9 E22 FBA_D9 FBVDDQ E13 AC8 GND
MDA10 E24 FBA_D10 FBVDDQ F13 AF11 GND
MDA11 D24 FBA_D11 FBVDDQ F14 AF14 GND
MDA12 D26 FBA_D12 FBVDDQ F15 AF17 GND
MDA13 D27 FBA_D13 FBVDDQ F16 AF2 GND
MDA14 C27 FBA_D14 FBVDDQ F17 AF20 GND

C361

C369

C362

C363

C364

C365
MDA15 B27 F19 AF23

4700P_0402_25V7K

4700P_0402_25V7K

4700P_0402_25V7K
FBA_D15 FBVDDQ 1 1 1 1 1 1 GND

0.022U_0402_16V7K

0.1U_0402_16V4Z

0.1U_0402_16V4Z
MDA16 D16 FBA_D16 FBVDDQ F22 AF26 GND
MDA17 E16 FBA_D17 FBVDDQ H23 AF5 GND

PM@

PM@

PM@

PM@

PM@

PM@
MDA18 D17 FBA_D18 FBVDDQ H26 AF8 GND
MDA19 2 2 2 2 2 2
F18 FBA_D19 FBVDDQ J15 B11 GND
MDA20 D20 FBA_D20 FBVDDQ J16 B14 GND
MDA21 F20 FBA_D21 FBVDDQ J18
MDA22 E21 FBA_D22 FBVDDQ J19 B17 GND
MDA23 F21 FBA_D23 FBVDDQ L19 B2 GND
MDA24 C16 FBA_D24 FBVDDQ L23 B20 GND
MDA25 B18 FBA_D25 FBVDDQ L26 1 B23 GND

C370

C371

C372

C373

C374

C375
MDA26 C18 M19 B26

4700P_0402_25V7K

4700P_0402_25V7K
FBA_D26 FBVDDQ 1 1 1 1 1 GND

1U_0402_6.3V6K

1U_0402_6.3V6K

0.022U_0402_16V7K
0.1U_0402_16V4Z
MDA27 D18 FBA_D27 FBVDDQ N22 B5 GND
MDA28 C19 FBA_D28 FBVDDQ U22 B8 GND
2

PM@

PM@

PM@

PM@

PM@

PM@
MDA29 C21 FBA_D29 FBVDDQ Y22 E11 GND
MDA30 2 2 2 2 2
B21 FBA_D30 E14 GND
MDA31 A21 FBA_D31 E17 GND
MDA32 P22 FBA_D32 E2 GND
MDA33 P24 FBA_D33 E20 GND
MDA34 R23 FBA_D34 E23 GND
MDA35 R24 FBA_D35 E26 GND
MDA36 T23 FBA_D36 E5 GND
MDA37 U24 FBA_D37 E8 GND
CMDA[30..0] <20,21>
MDA38 V23 FBA_D38 H2 GND
MDA39 V24 FBA_D39 FBA_CMD0 F26 CMDA0 H5 GND
MDA40 N25 FBA_D40 FBA_CMD1 J24 CMDA1 J11 GND
MDA41 N26 FBA_D41 FBA_CMD2 F25 CMDA2 J14 GND
MDA42 R25 FBA_D42 FBA_CMD3 M23 CMDA3
MDA43 R26 FBA_D43 FBA_CMD4 N27 CMDA4 J17 GND
MDA44 T25 FBA_D44 FBA_CMD5 M27 CMDA5 K19 GND
MDA45 V26 FBA_D45 FBA_CMD6 K26 CMDA6 K9 GND
MDA46 V25 FBA_D46 FBA_CMD7 J25 CMDA7 L11 GND
MDA47 V27 FBA_D47 FBA_CMD8 J27 CMDA8 L12 GND
MDA48 V22 FBA_D48 FBA_CMD9 G23 CMDA9 L13 GND
MDA49 W22 FBA_D49 FBA_CMD10 G26 CMDA10 L14 GND
MDA50 W23 FBA_D50 FBA_CMD11 J23 CMDA11 L15 GND
MDA51 W24 FBA_D51 FBA_CMD12 M25 CMDA12 L16 GND
MDA52 AA22 FBA_D52 FBA_CMD13 K27 CMDA13 L17 GND
MDA53 AB23 FBA_D53 FBA_CMD14 G25 CMDA14 L2 GND
MDA54 AB24 FBA_D54 FBA_CMD15 L24 CMDA15 L5 GND
MDA55 AC24 FBA_D55 FBA_CMD16 K23 CMDA16 9/18 add R for nvidia M12 GND
MDA56 W25 FBA_D56 FBA_CMD17 K24 CMDA17 M13 GND
MDA57 W26 FBA_D57 FBA_CMD18 G22 CMDA18 M14 GND
MDA58 W27 FBA_D58 FBA_CMD19 K25 CMDA19 R1131 10K_0402_5% M15 GND
1 MDA59 AA25 FBA_D59 FBA_CMD20 H22 CMDA20 CMDA12 1 2 M16 GND 1

MDA60 AB25 FBA_D60 FBA_CMD21 M26 CMDA21 PM@ P19 GND

MDA61 AB26 FBA_D61 FBA_CMD22 H24 CMDA22 P2 GND
MDA62 AD26 FBA_D62 FBA_CMD23 F27 CMDA23 R1132 10K_0402_5% P23 GND
MDA63 AD27 FBA_D63 FBA_CMD24 J26 CMDA24 CMDA11 1 2
FBA_CMD25 G24 CMDA25 PM@ P26 GND
FBA_CMD26 G27 CMDA26 P5 GND
<20> DQMA[3..0]
DQMA0 D23 FBA_DQM0 FBA_CMD27 M24 CMDA27 P9 GND
DQMA1 C26 FBA_DQM1 FBA_CMD28 K22 CMDA28 T12 GND
DQMA2 D19 FBA_DQM2 RFU J22 CMDA29 T13 GND
DQMA3 B19 FBA_DQM3 RFU L22 CMDA30 T14 GND
<21> DQMA[7..4]
DQMA4 T24 FBA_DQM4 T15 GND
DQMA5 T26 FBA_DQM5 T16 GND
DQMA6 AA23 FBA_DQM6 U11 GND
DQMA7 AB27 FBA_DQM7 FBA_CLK0 F24 CLKA0 <20> U12 GND
FBA_CLK0 F23 CLKA0# <20> U13 GND
<20> QSA[3..0] FBA_CLK1 N24 CLKA1 <21> U14 GND
QSA0 A24 FBA_DQS_WP0 FBA_CLK1 N23 CLKA1# <21> U15 GND
QSA1 C25 FBA_DQS_WP1 U16 GND
QSA2 E19 FBA_DQS_WP2 U17 GND
QSA3 A19 FBA_DQS_WP3 U2 GND
<21> QSA[7..4]
QSA4 T22 FBA_DQS_WP4 U23 GND
QSA5 T27 FBA_DQS_WP5 U26 GND
QSA6 AA24 FBA_DQS_WP6 U5 GND
QSA7 AA26 FBA_DQS_WP7 V19 GND

<20> QSA#[3..0] V9 GND

QSA#0 B24 FBA_DQS_RN0 R254 30_0402_1% W11 GND
QSA#1 D25 FBA_DQS_RN1 FB_CAL_PD_VDDQ B15 1 PM@ 2 +VDD_MEM18 W14 GND
QSA#2 E18 FBA_DQS_RN2 W17 GND
QSA#3 A18 FBA_DQS_RN3 FB_CAL_PU_GND A15 1 PM@ 2 R255 30_0402_1% Y2 GND
<21> QSA#[7..4]
QSA#4 R22 FBA_DQS_RN4 Y23 GND
QSA#5 R27 FBA_DQS_RN5 FB_CAL_TERM_GND B16 1 @ 2 R256 40.2_0402_1% Y26 GND
QSA#6 Y24 FBA_DQS_RN6 Y5 GND
QSA#7 AA27 FBA_DQS_RN7

R257
FBA_DEBUG M22 1 @ 2 +VDD_MEM18
10K_0402_5%

PM@

+VDD_MEM18
FB_PLLAVDD R19 FB_PLLAVDD 2 1 +1.1VS
L15 PM@
1

FB_DLLAVDD T19 1 1 1 1 BLM18PG181SN1D_0603

C376

PM@ C377

C379

C394
1U_0402_6.3V6K
0.1U_0402_16V4Z

4.7U_0603_6.3V6M

R258 @ Rt
0.01U_0402_25V7K

1K_0402_1%
2 2 2 2
PM@

PM@

PM@
2

A16 FB_VREF
1

1
0.1U_0402_16V4Z

R259 @ Rb C378
1K_0402_1% @
2
2

PM@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM / GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom kAL90KALH0 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, November 20, 2008 Sheet 19 of 52
A
 5 4 3 2 1

DATA Bus

VRAM DDR2 chips (256MB & 512MB) Address

CMD0
0..31
A3
32..63

CMD1 A0 A0
32Mx16 DDR2 400MHz *4==>256MB CMD2 A2
64Mx16 DDR2 400MHz*4==>512MB CMD3 A1 A1
CMD4 A3
QSA[7..0] CMD5 A4
D <19,21> QSA[7..0] D
QSA#[7..0] CMD6 A5
<19,21> QSA#[7..0]
DQMA[7..0] CMD7
<19,21> DQMA[7..0]
MDA[63..0] CMD8 CS# CS#
<19,21> MDA[63..0]
CMDA[30..0] CMD9 WE# WE#
<19,21> CMDA[30..0]
CMD10 BA0 BA0
CMD11 CKE CKE
CMD12 ODT ODT
CMD13
CMD14 A12 A12
CMD15 RAS# RAS#
U8 U9 CMD16 A11 A11
CMDA10 L2 B9 MDA7 CMDA10 L2 B9 MDA27
BA0 DQ15 BA0 DQ15
CMDA18 L3 BA1 DQ14 B1 MDA0 CMDA18 L3 BA1 DQ14 B1 MDA28 CMD17 A10 A10
D9 MDA5 D9 MDA24
DQ13 DQ13
CMDA14 R2 A12 DQ12 D1 MDA2 CMDA14 R2 A12 DQ12 D1 MDA31 CMD18 BA1 BA1
CMDA16 P7 D3 MDA3 CMDA16 P7 D3 MDA30
A11 DQ11 A11 DQ11
CMDA17 M2
A10/AP DQ10
D7 MDA4 CMDA17 M2
A10/AP DQ10
D7 MDA25 CMD19 A8 A8
CMDA20 P3 C2 MDA1 CMDA20 P3 C2 MDA29
A9 DQ9 A9 DQ9
CMDA19 P8 A8 DQ8 C8 MDA6 CMDA19 P8 A8 DQ8 C8 MDA26 CMD20 A9 A9
CMDA23 P2 F9 MDA23 CMDA23 P2 F9 MDA15
CMDA21 A7 DQ7 MDA18 CMDA21 A7 DQ7 MDA9
C
N7
A6 DQ6
F1 N7
A6 DQ6
F1 CMD21 A6 A6 C
CMDA22 N3 H9 MDA20 CMDA22 N3 H9 MDA12
A5 DQ5 A5 DQ5
CMDA24 N8
A4 DQ4
H1 MDA16 CMDA24 N8
A4 DQ4
H1 MDA8 CMD22 A5
CMDA0 N2 H3 MDA17 CMDA0 N2 H3 MDA11
A3 DQ3 A3 DQ3
CMDA2 M7 A2 DQ2 H7 MDA21 CMDA2 M7 A2 DQ2 H7 MDA13 CMD23 A7 A7
CMDA3 M3 G2 MDA19 CMDA3 M3 G2 MDA10
A1 DQ1 A1 DQ1
CMDA1 M8
A0 DQ0
G8 MDA22 CMDA1 M8
A0 DQ0
G8 MDA14 CMD24 A4
CMD25 CAS# CAS#
CLKA0# K8 A9 CLKA0# K8 A9
CK VDDQ +VDD_MEM18 CK VDDQ +VDD_MEM18
CLKA0 J8 C1 CLKA0 J8 C1 CMD26 A13 A13
CK VDDQ CK VDDQ
VDDQ C3 VDDQ C3
CMDA11 K2
CKE VDDQ
C7 CMDA11 K2
CKE VDDQ
C7 CMD27 BA2 BA2
VDDQ C9 VDDQ C9
VDDQ
E9
VDDQ
E9 CMD28
G1 G1
VDDQ VDDQ
CMDA8 L8
CS VDDQ
G3 CMDA8 L8
CS VDDQ
G3 CMD29
G7 G7
VDDQ VDDQ
CMDA9 K3
WE VDDQ
G9 CMDA9 K3
WE VDDQ
G9 CMD30
CMDA15 K7 A1 CMDA15 K7 A1
RAS VDD RAS VDD
E1 E1
CMDA25 VDD CMDA25 VDD
L7 J9 L7 J9
CAS VDD CAS VDD
M9 M9
DQMA2 VDD DQMA1 VDD
F3 R1 F3 R1
DQMA0 LDM VDD DQMA3 LDM VDD
B3 B3
UDM 0.1U_0402_16V4Z UDM 0.1U_0402_16V4Z
J1 J1
VDDL VDDL
VSSDL J7 1 1 VSSDL J7 1 1
CMDA12 K9 CMDA12 K9
ODT C383 C384 ODT C381 C382
4.7U_0603_6.3V6M 4.7U_0603_6.3V6M
+VDD_MEM18 QSA2 F7 2 2 QSA1 F7 2 2
QSA#2 LDQS QSA#1 LDQS
E8 A7 E8 A7
B LDQS VSSQ PM@ LDQS VSSQ PM@ B
VSSQ B2 VSSQ B2
VSSQ B8 PM@ VSSQ B8 PM@
1

D2 D2
R260 QSA0 VSSQ QSA3 VSSQ
B7 UDQS VSSQ D8 B7 UDQS VSSQ D8
1K_0402_1% QSA#0 A8 E7 QSA#3 A8 E7 CLKA0
UDQS VSSQ UDQS VSSQ <19> CLKA0
F2 F2
VSSQ VSSQ

1
F8 #PV reserve CMD27 to suport 64M x 16 F8
2

MEM_VREF0 VSSQ MEM_VREF0 VSSQ R261

J2 H2 J2 H2
VREF VSSQ VREF VSSQ 475_0402_1%
H8 H8
VSSQ VSSQ
1

PM@
1 A2 A2
R262 NC NC
E2 A3 E2 A3

2
1K_0402_1% C385 CMDA27 NC VSS CMDA27 NC VSS CLKA0#
L1 E3 L1 E3 <19> CLKA0#
NC VSS NC VSS
R3 NC VSS J3 R3 NC VSS J3
2 R7 N1 R7 N1 PM@
2

0.1U_0402_16V4Z NC VSS NC VSS

R8 NC VSS P9 R8 NC VSS P9

PM@ (SSTL-1.8) VREF = .5*VDDQ

PM@ HY5PS1G1631CFR-25 FBGA 84P HY5PS1G1631CFR-25 FBGA 84P

PM512M@ PM512M@

DDR BGA MEMORY

DDR2 BGA MEMORY
+VDD_MEM18 +VDD_MEM18

0.01U_0402_16V7K 4.7U_0603_6.3V6M 0.1U_0402_16V4Z 0.01U_0402_16V7K 4.7U_0603_6.3V6M 0.01U_0402_16V7K

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C395 C396 C397 C398 C399 C400 C401 C402 C386 C387 C388 C389 C390 C391 C392 C393
A 1000P_0402_50V7K 1000P_0402_50V7K A
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

PM@ 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K PM@ 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K

PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM 1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KAL90
Date: Thursday, November 20, 2008 Sheet 7 of 16
5 4 3 2 1
 5 4 3 2 1

DATA Bus

VRAM DDR2 chips (256MB & 512MB) Address

CMD0
0..31
A3
32..63

32Mx16 DDR2 400MHz *4==>256MB CMD1 A0 A0

CMD2 A2
64Mx16 DDR2 400MHz*4==>512MB
CMD3 A1 A1
CMD4 A3
D DQMA[7..0] CMD5 A4 D
<19,20> DQMA[7..0]
CMDA[30..0] CMD6 A5
<19,20> CMDA[30..0]
QSA#[7..0] CMD7
<19,20> QSA#[7..0]
QSA[7..0] CMD8 CS# CS#
<19,20> QSA[7..0]
MDA[63..0] CMD9 WE# WE#
<19,20> MDA[63..0]
CMD10 BA0 BA0
CMD11 CKE CKE
CMD12 ODT ODT
CMD13
CMD14 A12 A12
CMD15 RAS# RAS#
CMD16 A11 A11
CMD17 A10 A10
U10 U11 CMD18 BA1 BA1
CMDA10 L2 B9 MDA39 CMDA10 L2 B9 MDA59
BA0 DQ15 BA0 DQ15
CMDA18 L3 BA1 DQ14 B1 MDA32 CMDA18 L3 BA1 DQ14 B1 MDA60 CMD19 A8 A8
D9 MDA38 D9 MDA58
DQ13 DQ13
CMDA14 R2
A12 DQ12
D1 MDA34 CMDA14 R2
A12 DQ12
D1 MDA62 CMD20 A9 A9
CMDA16 P7 D3 MDA33 CMDA16 P7 D3 MDA63
C A11 DQ11 A11 DQ11 C
CMDA17 M2 A10/AP DQ10 D7 MDA37 CMDA17 M2 A10/AP DQ10 D7 MDA56 CMD21 A6 A6
CMDA20 P3 C2 MDA35 CMDA20 P3 C2 MDA61
A9 DQ9 A9 DQ9
CMDA19 P8
A8 DQ8
C8 MDA36 CMDA19 P8
A8 DQ8
C8 MDA57 CMD22 A5
CMDA23 P2 F9 MDA44 CMDA23 P2 F9 MDA51
CMDA21 A7 DQ7 MDA43 CMDA21 A7 DQ7 MDA53
N7 A6 DQ6 F1 N7 A6 DQ6 F1 CMD23 A7 A7
CMDA6 N3 H9 MDA47 CMDA6 N3 H9 MDA48
A5 DQ5 A5 DQ5
CMDA5 N8 A4 DQ4 H1 MDA40 CMDA5 N8 A4 DQ4 H1 MDA55 CMD24 A4
CMDA4 N2 H3 MDA41 CMDA4 N2 H3 MDA52
A3 DQ3 A3 DQ3
CMDA13 M7 A2 DQ2 H7 MDA46 CMDA13 M7 A2 DQ2 H7 MDA49 CMD25 CAS# CAS#
CMDA3 M3 G2 MDA42 CMDA3 M3 G2 MDA54
A1 DQ1 A1 DQ1
CMDA1 M8 A0 DQ0 G8 MDA45 CMDA1 M8 A0 DQ0 G8 MDA50 CMD26 A13 A13
CMD27 BA2 BA2
CLKA1# K8 A9 CLKA1# K8 A9
CK VDDQ +VDD_MEM18 CK VDDQ +VDD_MEM18
CLKA1 J8 C1 CLKA1 J8 C1 CMD28
CK VDDQ CK VDDQ
C3 C3
VDDQ VDDQ
CMDA11 K2
CKE VDDQ
C7 CMDA11 K2
CKE VDDQ
C7 CMD29
C9 C9
VDDQ VDDQ
VDDQ
E9
VDDQ
E9 CMD30
VDDQ G1 VDDQ G1
CMDA8 L8 G3 CMDA8 L8 G3
CS VDDQ CS VDDQ
G7 G7
CMDA9 VDDQ CMDA9 VDDQ
K3 G9 K3 G9
WE VDDQ WE VDDQ
CMDA15 K7 A1 CMDA15 K7 A1
RAS VDD RAS VDD
E1 E1
CMDA25 VDD CMDA25 VDD
L7 CAS VDD J9 L7 CAS VDD J9
M9 M9
DQMA5 VDD DQMA6 VDD
F3 R1 F3 R1
DQMA4 LDM VDD DQMA7 LDM VDD
B3 B3
UDM 0.1U_0402_16V4Z UDM 0.1U_0402_16V4Z
J1 J1
VDDL VDDL
J7 1 1 J7 1 1
B CMDA12 VSSDL CMDA12 VSSDL B
K9 ODT K9 ODT
C405 C406 C403 C404
+VDD_MEM18 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M
QSA5 F7 2 2 QSA6 F7 2 2
QSA#5 LDQS QSA#6 LDQS
E8 A7 E8 A7
LDQS VSSQ PM@ LDQS VSSQ PM@
B2 B2
VSSQ VSSQ
1

B8 B8
R266 VSSQ PM@ VSSQ PM@
D2 D2
1K_0402_1% QSA4 VSSQ QSA7 VSSQ CLKA1
B7 D8 B7 D8 <19> CLKA1
QSA#4 UDQS VSSQ QSA#7 UDQS VSSQ
A8 UDQS VSSQ E7 A8 UDQS VSSQ E7
F2 F2
2

VSSQ VSSQ

1
MEM_VREF1 VSSQ
F8 #PV reserve CMD27 to suport 64M x 16 MEM_VREF1 VSSQ
F8
J2 H2 J2 H2 R267
PM@ VREF VSSQ VREF VSSQ 475_0402_1%
H8 H8
VSSQ VSSQ
1

1 A2 NC A2 NC
R268 E2 A3 E2 A3

2
1K_0402_1% C407 CMDA27 NC VSS CMDA27 NC VSS CLKA1#
L1 E3 L1 E3 <19> CLKA1#
NC VSS NC VSS
R3 J3 R3 J3
2 NC VSS NC VSS PM@
R7 N1 R7 N1
2

NC VSS NC VSS
R8 P9 R8 P9
0.1U_0402_16V4Z NC VSS NC VSS
PM@
HY5PS1G1631CFR-25 FBGA 84P HY5PS1G1631CFR-25 FBGA 84P
PM@
PM512M@ PM512M@
+VDD_MEM18 DDR2 BGA MEMORY +VDD_MEM18 DDR BGA MEMORY

0.01U_0402_16V7K 4.7U_0603_6.3V6M 0.1U_0402_16V4Z 0.01U_0402_16V7K 4.7U_0603_6.3V6M 0.01U_0402_16V7K

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A C417 C418 C419 C420 C421 C422 C423 C424 C408 C409 C410 C411 C412 C413 C414 C415 A
1000P_0402_50V7K 1000P_0402_50V7K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K
PM@ PM@ 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K
PM@ PM@ PM@ PM@
PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM 2
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KAL90
Date: Thursday, November 20, 2008 Sheet 8 of 16
5 4 3 2 1
 5 4 3 2 1

D +3VS D

LCD POWER CIRCUIT

5
U44
+LCDVDD

P
NC
+3V +3VS INVTPWM 4 2
Y A DPST_PWM <10>
W=60mils

G
1
R1614 NC7SZ14P5X_NL_SC70-5

3
1
300_0603_5% 1
R1615 C1902
100K_0402_5% @

3 2
4.7U_0805_10V4Z

2
2

G
2
R1617
Q109B S

3
G +3VS 1 2 INVTPWM 1 3
2N7002DW-T/R7_SOT363-6 5 2 1 2 Q110

S
R1616 1K_0402_5% AO3413_SOT23-3 10K_0402_5%
D
1
4

1
Q111

6
C1903 +LCDVDD
W=60mils @ 2N7002_SOT23 For GMCH DPST
Q109A 0.047U_0402_16V7K
R1618 1 2 0_0402_5% 2 2
<10> GMCH_ENVDD @
2N7002DW-T/R7_SOT363-6 1 1
R1619 1 GM@ 2 0_0402_5% C1904 C1905

1
<18> ENVDD
1

PM@ 4.7U_0805_10V4Z 0.1U_0402_16V4Z

R1620 2 2
100K_0402_5%
2

C C
TXOUT0+ 1 4 VGA_TXOUT0+
TXOUT0- VGA_TXOUT0- VGA_TXOUT0+ <17>
2 3 VGA_TXOUT0- <17>
RP43 0_0404_4P2R_5%
TXOUT1- 1 PM@ 4 VGA_TXOUT1-
TXOUT1+ VGA_TXOUT1+ VGA_TXOUT1- <17>
2 3 VGA_TXOUT1+ <17>
RP44 0_0404_4P2R_5%
TXOUT2+ 1 PM@ 4 VGA_TXOUT2+
+3VS TXOUT2- VGA_TXOUT2- VGA_TXOUT2+ <17>
2 3 VGA_TXOUT2- <17>
RP45 0_0404_4P2R_5%
TXCLK- 1 PM@ 4 VGA_TXCLK-
VGA_TXCLK- <17>

1
TXCLK+ 2 3 VGA_TXCLK+
VGA_TXCLK+ <17>
R1621 RP46 0_0404_4P2R_5%
PM@
4.7K_0402_5%
D34
2
BKOFF# 1 2 DISPOFF#
<35> BKOFF#

+INVPWR_B+ CH751H-40PT_SOD323-2

L58 2 1 B+
W=40mils KC FBM-L11-201209-221LMAT_0805
DAC_BRIG 1 2
L59 2 1 C1906 220P_0402_50V7K
KC FBM-L11-201209-221LMAT_0805 INVTPWM 1 2
1 1 C1907 220P_0402_50V7K
C1908 C1910 DISPOFF# 1 2
C1909 220P_0402_50V7K I2CC_SCL 1 4 GMCH_LCD_CLK
GMCH_LCD_CLK <10>
680P_0402_50V7K 68P_0402_50V8J I2CC_SDA 2 3 GMCH_LCD_DATA
2 2 GMCH_LCD_DATA <10>
RP47 0_0404_4P2R_5%
B GM@ B

LCD/PANEL BD. Conn. TXOUT0+ 2 3 GMCH_TXOUT0+

TXOUT0- GMCH_TXOUT0- GMCH_TXOUT0+ <10>
1 4 GMCH_TXOUT0- <10>
RP48 0_0404_4P2R_5%
TXOUT1- 2 GM@ 3 GMCH_TXOUT1-
GMCH_TXOUT1- <10>
JLVDS1 TXOUT1+ 1 4 GMCH_TXOUT1+
DAC_BRIG GMCH_TXOUT1+ <10>
42 41 RP49 0_0404_4P2R_5%
GND GND DAC_BRIG <35> TXOUT2+ GMCH_TXOUT2+
+INVPWR_B+ 40 39 2 GM@ 3 GMCH_TXOUT2+ <10>
40 39 INVTPWM R1622 1 TXOUT2- GMCH_TXOUT2-
38 38 37 37 2 0_0402_5% INVT_PWM <35> 1 4 GMCH_TXOUT2- <10>
36 35 DISPOFF# RP50 0_0404_4P2R_5%
+3VS 36 35
I2CC_SCL 34 33 TXCLK- 2 GM@ 3 GMCH_TXCLK-
<18> I2CC_SCL 34 33 +LCDVDD GMCH_TXCLK- <10>
I2CC_SDA 32 31 TXCLK+ 1 4 GMCH_TXCLK+
<18> I2CC_SDA 32 31 GMCH_TXCLK+ <10>
R1767 0_0402_5% 30 29 W=60mils RP51 0_0404_4P2R_5%
30 29
1 2 28 28 27 27 GM@
26 25 TXOUT0- +LCDVDD
26 25 TXOUT0+ +3VS
24 23
24 23
LED PANEL PIN1&34 SHORT
@ 22
20
22 21
21
19 TXOUT1-
20 19 TXOUT1+
18 17 1 1 1
18 17 C1911 C1912 C1913
16 15
16 15 TXOUT2+
14 14 13 13
12 11 TXOUT2- 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
12 11 2 2 2
10 10 9 9
8 7 TXCLK-
0_0402_5% 8 7 TXCLK+
6 5
6 5
<27> USB20_N6
R1623 1 2 USB20_CMOS_N6 4 4 3 3
<27> USB20_P6
R1624 1 2 USB20_CMOS_P6 2 1 +3VS
0_0402_5% 2 1
ACES_88242-4001

A CONN@ A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 22 of 52
5 4 3 2 1
 A B C D E

CRT Connector D35 D36 D37

W=40mils
+5VS +R_CRT_VCC +CRT_VCC
DAN217_SC59 DAN217_SC59 DAN217_SC59
D38 F1 W=40mils

1
2 1 1 2

RB491D_SC59-3 1.1A_6VDC_FUSE
1
C1914

3
0.1U_0402_16V4Z
1 2 1
+3VS

JCRT1
6
CRT_R CRT_R_1 CRT_R_2 RGND
1 2 1 2 11 ID0
L60 FCM2012C-800_0805 L61 FCM2012C-800_0805 1
Red
7 GGND
CRT_G 1 2 CRT_G_1 1 2 CRT_G_2 12
L62 FCM2012C-800_0805 L63 FCM2012C-800_0805 SDA
2
Green
8 BGND
CRT_B 1 2 CRT_B_1 1 2 CRT_B_2 13
L64 FCM2012C-800_0805 L65 FCM2012C-800_0805 Hsync
3 Blue
1

9
+5V
1

R1625 R1626 1 1 1 1 1 1 1 1 1 14
R1627 C1915 C1916 C1917 C1918 C1919 C1920 Vsync
4
C1921 C1922 C1923 res
10 SGND
150_0402_1% 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 15
2

2 2 2 2 2 2 2 2 2 SCL
5
2

150_0402_1% 10P_0402_50V8J 10P_0402_50V8J 22P_0402_50V8J GND

150_0402_1% 22P_0402_50V8J 22P_0402_50V8J GM@ GM@ GM@ 1 16
10P_0402_50V8J C1924 GND
change to 12pf for Discrete 17
GND
1 2 CRT_HSYNC_2
L4 10_0603_5% 2 SUYIN_070546FR015S263ZR
CRT_DET# <27>
change to 15pf for Discrete 100P_0402_50V8J
1 2 CRT_VSYNC_2
CONN@
L5 10_0603_5% 1 1 DSUB_12

2
+CRT_VCC C1926
C1925 1 R1630
1 2 2 1 10P_0402_50V8J 10P_0402_50V8J 100K_0402_5%
C1927 0.1U_0402_16V4Z R1631 10K_0402_5% 2 2
2 DSUB_15 2

1
5

U45 C1928 2
68P_0402_50V8J 1
OE#
P

CRT_HSYNC 2 4 CRT_HSYNC_1
A Y C1929 +CRT_VCC
G

68P_0402_50V8J
74AHCT1G125GW_SOT353-5 2
3

+CRT_VCC

1 2
C1930 0.1U_0402_16V4Z
5

U46
OE#
P

CRT_VSYNC 2 4 CRT_VSYNC_1
A Y
G

74AHCT1G125GW_SOT353-5
3

+CRT_VCC

Place closed to chipset

+3VS
pull-up 10k on AMD M82M MXM side

1
pull-up 2.2k on GPU side
R1632 R1633 1 2 R1634
4.7K_0402_5% 4.7K_0402_5% 0_0402_5% VGA_DDC_DATA <18>
PM@

2
3 3

G
R1636 0_0402_5%
R1635 1 2 30.1_0402_1% CRT_VSYNC DSUB_12 1 3 2 1
<10> GMCH_CRT_VSYNC GMCH_CRT_DATA <10>

S
R1637 1 GM@ 2 30.1_0402_1% CRT_HSYNC Q112
<10> GMCH_CRT_HSYNC

2
2N7002_SOT23

G
GM@
R1638 1 GM@ 2 0_0402_5% CRT_B
<10> GMCH_CRT_B DSUB_15 1 3 2 1
R1640 1 GM@ 0_0402_5% CRT_G R1639 GMCH_CRT_CLK <10>
2

S
<10> GMCH_CRT_G
Q113 0_0402_5%
R1641 1 GM@ 2 0_0402_5% CRT_R 2N7002_SOT23
<10> GMCH_CRT_R GM@
1 2 R1642
0_0402_5% VGA_DDC_CLK <18>
GM@
PM@
pull-up 2.2k on GPU side
CRT_VSYNC
pull-up 10k on AMD M82M MXM side
R1643 1 2 0_0402_5%
<17> VGA_CRT_VSYNC
R1644 1 PM@ 2 0_0402_5% CRT_HSYNC
<17> VGA_CRT_HSYNC
R1645 1 PM@ 2 0_0402_5% CRT_B
<17> VGA_CRT_B
R1646 1 PM@ 2 0_0402_5% CRT_G
<17> VGA_CRT_G
R1647 1 PM@ 2 0_0402_5% CRT_R
<17> VGA_CRT_R
PM@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 23 of 52
A B C D E
 5 4 3 2 1

+HDMI_5V_OUT
DDC to HDMI CONN
JHDMI1
+3VS HDMI_HPD
3.3V Level 19 HP_DET
+HDMI_5V_OUT 18 +5V

1
17 DDC/CEC_GND
R1649 R1650 HDMI_SDATA 16
R1648 1 SDA
+3VS 2 2.2K_0402_5% 4.7K_0402_5% 4.7K_0402_5% HDMI_SCLK 15 SCL

2
G
D +5VS R1651 1 2 2.2K_0402_5% 14 D
Reserved
PM@ 13

2
CEC
<18> VGA_HDMI_SCLK @ VGA_HDMI_SCLK VGA_HDMI_SCLK 3 1 HDMI_SCLK HDMI_R_CK- 12 CK- GND 20

D
11 CK_shield GND 21
Q114 HDMI_R_CK+ 10 22
CK+ GND

2
G
BSH111_SOT23 HDMI_R_D0- 9 23
D0- GND
8 D0_shield
<18> VGA_HDMI_SDATA VGA_HDMI_SDATA VGA_HDMI_SDATA 3 1 HDMI_SDATA HDMI_R_D0+ 7
HDMI_R_D1- D0+

D
6 D1-
+3VS R1652 1 2 2.2K_0402_5% Q115 5
R1653 1 D1_shield
+5VS 2 2.2K_0402_5% BSH111_SOT23 Place closed to JHDMI1 HDMI_R_D1+ 4 D1+
PM@ HDMI_R_D2- 3 D2-
@ 2 D2_shield
HDMI_R_D2+ 1 D2+
TYCO_1939864-1
MP:Update HDMI Hot Plug DET circuit.
+HDMI_5V_OUT CONN@

HDMI_HPD 1 2
1 R104
C1931 2 1 +3VS 0_0603_5%

2
R1654 R1655 +HDMI_5V_OUT
1 @
5

0.1U_0402_16V4Z U47 2.2K_0402_5% 100K_0402_5% C1932

2 D39 F2
W=40mils
OE#
P

2 A Y 4HDMI_DET HDMI_DET <18> 0.1U_0402_16V4Z +5VS 2 1 +HDMI_5V 1 2 HDMI_CLK- 1 2 HDMI_R_CK-

2 R1656 0_0402_5%
1

1
G

RB491D_SC59-3 1.1A_6VDC_FUSE PM@

C C1933 L66 C
3

0.1U_0402_16V4Z 1 2
74AHCT1G125GW_SOT353-5 2 1 2

4 4 3 3
@
WCM-2012-900T_0805

HDMI_CLK+ 1 2 HDMI_R_CK+
R1657 0_0402_5%
PM@

HDMI_TX0- 1 2 HDMI_R_D0-
R1658 0_0402_5%
PM@
L67
1 1 2 2
HDMI_CLK+
<18> VGA_HDMI_TXC+
HDMI_CLK-
<18> VGA_HDMI_TXC-
HDMI_TX0+ 4 3
<18> VGA_HDMI_TXD0+ 4 3
HDMI_TX0- @
<18> VGA_HDMI_TXD0-
HDMI_TX1+ WCM-2012-900T_0805
<18> VGA_HDMI_TXD1+
HDMI_TX1-
<18> VGA_HDMI_TXD1-
HDMI_TX2+ HDMI_TX0+ 1 2 HDMI_R_D0+
<18> VGA_HDMI_TXD2+
HDMI_TX2- R1659 0_0402_5%
<18> VGA_HDMI_TXD2-
PM@

HDMI_TX1- 1 2 HDMI_R_D1-
R1660 0_0402_5%
B PM@ B
L68
1 1 2 2

4 4 3 3
@
WCM-2012-900T_0805

HDMI_TX1+ 1 2 HDMI_R_D1+
R1661 0_0402_5%
PM@

HDMI_TX2- 1 2 HDMI_R_D2-
R1662 0_0402_5%
PM@
L69
1 1 2 2

4 4 3 3

@ WCM-2012-900T_0805

HDMI_TX2+ 1 2 HDMI_R_D2+
R1663 0_0402_5%
PM@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 24 of 52
5 4 3 2 1
 5 4 3 2 1

DMI for ESI-compatible operation

+3VS
Low= DMI for ESI-compatible operation
PCI_GNT#1 High= Default* (Internal pull-up)
RP36
1 8 PCI_DEVSEL#
2 7 PCI_FRAME#
D 3 6 PCI_REQ#1 D
4 5 PCI_REQ#2
U23B
8.2K_1206_8P4R_5% D11 F1 PCI_REQ#0
AD0 REQ0# PCI_GNT#0
C8 AD1 GNT0# G4
RP37 Structure> PCI_REQ#1
1
<BOM
8 PCI_PLOCK#
D9
E12
AD2 PCI REQ1#/GPIO50 B6
A7 PCI_GNT#1
AD3 GNT1#/GPIO51 PAD T11
2 7 PCI_IRDY# E9 F13 PCI_REQ#2
PCI_PERR# AD4 REQ2#/GPIO52 PCI_GNT#2
3 6 C9 AD5 GNT2#/GPIO53 F12 @ PAD T12
4 5 PCI_PIRQB# E10 E6 PCI_REQ#3
AD6 REQ3#/GPIO54 PCI_GNT#3
B7 AD7 GNT3#/GPIO55 F6 @
8.2K_1206_8P4R_5% C7 AD8 PCI_CBE#0
C5 AD9 C/BE0# D8 PAD T13
<BOM Structure> G11 B4 PCI_CBE#1 PAD
AD10 C/BE1# T14
F8 D6 PCI_CBE#2 @ PAD
AD11 C/BE2# T15
F11 A5 PCI_CBE#3 @ PAD
+3VS AD12 C/BE3# T16
E7 AD13 @
A3 D3 PCI_IRDY# @
RP38 AD14 IRDY# PCI_PAR
D2 AD15 PAR E3 PAD T17
1 8 PCI_PIRQG# F10 R1 PCI_RST#
AD16 PCIRST# PCI_RST# <34>
2 7 PCI_REQ#0 D5 C6 PCI_DEVSEL# @
PCI_PIRQH# AD17 DEVSEL# PCI_PERR#
3 6
PCI_PIRQE#
D10 AD18 PERR# E4
PCI_PLOCK#
Place closely pin B10
4 5 B3 AD19 PLOCK# C2
F7 J4 PCI_SERR#
8.2K_1206_8P4R_5% AD20 SERR# PCI_STOP# CLK_PCI_ICH
C3 AD21 STOP# A4
F3 F5 PCI_TRDY#
AD22 TRDY#

2
RP39
<BOM Structure> F4 D7 PCI_FRAME#
PCI_PIRQF# AD23 FRAME#
1 8 C1 AD24
2 7 PCI_SERR# G7 C14 PLT_RST# R1276
AD25 PLTRST# PLT_RST# <8,17,27,30,31,35>
C 3 6 PCI_PIRQA# H7 D4 CLK_PCI_ICH 10_0402_5% C
AD26 PCICLK CLK_PCI_ICH <16>
4 5 PCI_PIRQC# D1 R2 @

1
AD27 PME#
G5 AD28
8.2K_1206_8P4R_5% H6 1
AD29 C1573
G1 AD30
RP40
<BOM Structure> H3 10P_0402_50V8J
PCI_STOP# AD31
1 8
PCI_PIRQD# @ 2
2 7
PCI_REQ#3
3
4
6
5 PCI_TRDY# PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE#
PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF#
E1 PIRQB# PIRQF#/GPIO3 K6
8.2K_1206_8P4R_5% PCI_PIRQC# J6 F2 PCI_PIRQG#
PCI_PIRQD# PIRQC# PIRQG#/GPIO4 PCI_PIRQH#
C4 PIRQD# PIRQH#/GPIO5 G2
<BOM Structure>
ICH9-M ES_FCBGA676

<BOM Structure>

A16 Swap Override Strap

Low= A16 swap override Enable
PCI_GNT#3 High= Default*

R1277 1 2 1K_0402_5% PCI_GNT#3

B B
@

+3VS

5
U24
Boot BIOS Strap PLT_RST# 2 B

P
Y 4 PLT_RST_BUF# <33>
PCI_GNT#0 SPI_CS#1 Boot BIOS Loaction 1 A

1
NC7SZ08P5X_NL_SC70-5

3
R1278
0 1 SPI 100K_0402_5%
<BOM Structure>
1 0 PCI

2
<BOM Structure>
1 1 LPC*

R1280 1 2 1K_0402_5% PCI_GNT#0

@
R1281 1 2 1K_0402_5% SPI_CS#1 <27>

A @ A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(1/4)-PCI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 25 of 52
5 4 3 2 1
 5 4 3 2 1

+RTCVCC CMOS Settings R1290 TPM Settings R1291

C1574
18P_0402_50V8J Clear CMOS SHORT Clear ME RTC Registers SHORT
2 1 ICH_RTCX1 +1.05VS

1
Keep CMOS OPEN Keep ME RTC Registers OPEN
R1283 X1 H_DPRSTP#

10M_0402_5%
2 1

1
3 4 R1284 56_0402_5%
NC OUT

R1285
1M_0402_5% Reset r1290 for power on then shut down issue H_DPSLP# 2 @ 1
32.768KHZ_12.5P_MC-306 2 1 R1286 56_0402_5%
2

SM_INTRUDER# NC IN
@
C1575 U23A

2
D 18P_0402_50V8J C23 K5 LPC_AD0 D
RTCX1 FWH0/LAD0 LPC_AD0 <35>
2 1 ICH_RTCX2 C24 K4 LPC_AD1
+RTCVCC RTCX2 FWH1/LAD1 LPC_AD1 <35>
L6 LPC_AD2
FWH2/LAD2 LPC_AD2 <35>
+RTCVCC 1 2 ICH_RTCRST# A25 K2 LPC_AD3
RTCRST# FWH3/LAD3 LPC_AD3 <35>
R1287 +RTCVCC 1 2 ICH_SRTCRST# F20
20K_0402_5% R1288 SM_INTRUDER# SRTCRST# LPC_FRAME#
C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME# <35>
1

20K_0402_5%

RTC

LPC
R1289 close to RAM door close to RAM door ICH_INTVRMEN B22 INTVRMEN LDRQ0# J3
332K_0402_1% A22 J1
LAN100_SLP LDRQ1#/GPIO23 R1292 2
1 2 1 2 1 10K_0402_5% +3VS
R1290 R1291 E25 N7 EC_GA20
EC_GA20 <35>
2

10K_0603_5% 10K_0603_5% GLAN_CLK A20GATE H_A20M#

A20M# AJ27 H_A20M# <4>
ICH_INTVRMEN C1577
@ C1576
@ C13
1U_0603_10V6K 1U_0603_10V6K LAN_RSTSYNC DPRSTP# R1293 1 0_0402_5% H_DPRSTP#
High = Internal VR Enable DPRSTP# AJ25
DPSLP# R1294 1
2
0_0402_5% H_DPSLP#
H_DPRSTP# <5,8,49>
1 2 1 2 F14 LAN_RXD0 DPSLP# AE23 2 H_DPSLP# <5>
G13 LAN_RXD1
D14 AJ26 FERR# 1 2 H_FERR#
LAN_RXD2 FERR# H_FERR# <4>

LAN / GLAN
R1295 56_0402_5%
+3VS D13 AD22 H_PWRGOOD 2 1
LAN_TXD_0 CPUPWRGD H_PWRGOOD <5> +1.05VS
D12 R1296 56_0402_5%
LAN_TXD_1 H_IGNNE#
E13 LAN_TXD_2 IGNNE# AF25 H_IGNNE# <4>
1

R1297 PROJECT_ID2 B10 AE22 H_INIT# 2 1

GPIO56 INIT# H_INIT# <4> +3VS
AG25 H_INTR R1298 10K_0402_5%

CPU
INTR H_INTR <4>
10K_0402_5% +1.5VS_PCIE_ICH 1 2 GLAN_COMP B28 L3 EC_KBRST#
GLAN_COMPI RCIN# EC_KBRST# <35>
R1299 24.9_0402_1% B27
2

HDA_BITCLK_ICH GLAN_COMPO H_NMI

<37> HDA_BITCLK_MDC 1 2 NMI AF23 H_NMI <4>
SATA_LED# R1300 33_0402_5% AF6 AF24 H_SMI#
HDA_BIT_CLK SMI# H_SMI# <4>
<37> HDA_SYNC_MDC 1 2 HDA_SYNC_ICH AH4 R258 need to place within 2" of ICH9M
C R1301 33_0402_5% HDA_SYNC H_STPCLK# R257 must be place within 2" of R258 w/o stub. C
STPCLK# AH27 H_STPCLK# <4>
1 2 HDA_RST_ICH# AE7
<37> HDA_RST_MDC# HDA_RST#
R1302 33_0402_5% AG26 THRMTRIP_ICH# R1303 1 2 54.9_0402_1% H_THERMTRIP#
+3V THRMTRIP# H_THERMTRIP# <4,8>
<38> HDA_SDIN0 AF4 HDA_SDIN0
<37> HDA_SDIN1 AG4 HDA_SDIN1 TP12 AG27 2 1 +1.05VS
AH3 R1304 56_0402_5%
HDA_SDIN2
AE5

IHDA
<18> HDA_SDIN3 HDA_SDIN3
1

SATA4RXN AH11
R1305 1 2 HDA_SDOUT_ICH AG5 AJ11
<37> HDA_SDOUT_MDC HDA_SDOUT SATA4RXP
R1306 33_0402_5% AG12
10K_0402_5% SATA4TXN
AG7 HDA_DOCK_EN#/GPIO33 SATA4TXP AF12
AE8
2

HDA_DOCK_RST#/GPIO34
PROJECT_ID2 <42> SATA_LED# SATA_LED# AG8 SATALED# SATA_DTX_C_IRX_N5
SATA5RXN AH9 SATA_DTX_C_IRX_N5 <34>
<29> SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 AJ16 AJ9 SATA_DTX_C_IRX_P5 SATA_DTX_C_IRX_P5 <34>
SATA0RXN SATA5RXP
1

SATA for HDD <29> SATA_DTX_C_IRX_P0 SATA_DTX_C_IRX_P0 AH16 AE10 SATA_ITX_DRX_N5

R1307 SATA_ITX_DRX_N0 SATA0RXP SATA5TXN SATA_ITX_DRX_P5
AF17 SATA0TXN SATA5TXP AF10
SATA_ITX_DRX_P0 AG17
10K_0402_5% SATA0TXP CLK_PCIE_SATA#
SATA_CLKN AH18 CLK_PCIE_SATA# <16>

SATA
<29> SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_N1 AH13 AJ18 CLK_PCIE_SATA
CLK_PCIE_SATA <16>
2

SATA_DTX_C_IRX_P1 SATA1RXN SATA_CLKP SATARBIAS

SATA for ODD <29> SATA_DTX_C_IRX_P1
SATA_ITX_DRX_N1
AJ13 SATA1RXP SATARBIAS# AJ7
R1308 1
AG14 SATA1TXN SATARBIAS AH7 2 24.9_0402_1%
@ SATA_ITX_DRX_P1 AF14 10mils width less than 500mils
SATA1TXP

ICH9-M ES_FCBGA676

B HDA_BITCLK_ICH
close ICH9 B
<38> HDA_BITCLK_AUDIO 1 2
R1309 33_0402_5% SATA_ITX_DRX_N0 1 2 SATA_ITX_C_DRX_N0
HDA_SYNC_ICH C1578 0.01U_0402_16V7K SATA_ITX_C_DRX_N0 <29>
<38> HDA_SYNC_AUDIO 1 2
HDA for AUDIO R1310 33_0402_5% SATA_ITX_DRX_P0 1 2 SATA_ITX_C_DRX_P0
HDA_RST_ICH# C1579 0.01U_0402_16V7K SATA_ITX_C_DRX_P0 <29>
<38> HDA_RST_AUDIO# 1 2
R1311 33_0402_5%
<38> HDA_SDOUT_AUDIO 1 2 HDA_SDOUT_ICH
R1312 33_0402_5% SATA_ITX_DRX_N1 1 2 SATA_ITX_C_DRX_N1
C1580 0.01U_0402_16V7K SATA_ITX_C_DRX_N1 <29>
SATA_ITX_DRX_P1 1 2 SATA_ITX_C_DRX_P1
C1581 0.01U_0402_16V7K SATA_ITX_C_DRX_P1 <29>

SATA_ITX_DRX_N5 1 2 SATA_ITX_C_DRX_N5
SATA_ITX_C_DRX_N5 <34> MAINPWON <44,45>
C1582 0.01U_0402_16V7K
SATA_ITX_DRX_P5 1 2 SATA_ITX_C_DRX_P5
C1583 0.01U_0402_16V7K SATA_ITX_C_DRX_P5 <34> R1317

1
330_0402_5% C
+VCC_HDA_ICH 1 2 2 Q89
+1.05VS
B 2SC2411K_SOT23
1 2 HDA_BITCLK_ICH E
<18> HDA_BITCLK_VGA

3
R1318 33_0402_5%
R1319 <18> HDA_SYNC_VGA 1 PM@ 2 HDA_SYNC_ICH @
1K_0402_5% HDA for VGA R1320 33_0402_5% H_THERMTRIP#
@
1 PM@ 2 HDA_RST_ICH#
<18> HDA_RST_VGA#
R1321 33_0402_5%
HDA_SDOUT_ICH <18> HDA_SDOUT_VGA 1 PM@ 2 HDA_SDOUT_ICH
R1322 33_0402_5%
A
@
ICH_TP3 <27> PM@
Flash Descriptor Security Override Strap A
Low= Descriptor Security override
XOR Chain Entrance Strap GPIO33
R1323
1K_0402_5%
High= Default* (Internal pull-up)
ICH_TP3 HDA_SDOUT Description
0 0 RSVD Security Classification Compal Secret Data Compal Electronics, Inc.
0 1 Enter XOR Chain Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title
@
1 0 Normal Operation THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(2/4)-LAN,IDELPC,RTC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1 1 Set PCIE port config bit 1 Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 26 of 52
5 4 3 2 1
 5 4 3 2 1

+3VS
Place closely pin B2 Place closely pin AC1
1 2 SERIRQ U23C
R1324 10K_0402_5% <16,31,33,34> ICH_SMBCLK ICH_SMBCLK G16 AH23 PROJECT_ID1 CLK_ICH_48M CLK_ICH_14M
PM_CLKRUN# ICH_SMBDATA SMBCLK SATA0GP/GPIO21 PROJECT_ID0
1
R1332
2
8.2K_0402_5%
<16,31,33,34> ICH_SMBDATA
LINKALERT#
A13
E17
SMBDATA SMB SATA1GP/GPIO19
AF19
AE21 R1325 1 2 10K_0402_5%

SATA
GPIO
LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36

1
1 2 EC_THERM# ICH_SMLINK0 C17 AD20
R1326 8.2K_0402_5% ICH_SMLINK1 SMLINK0 SATA5GP/GPIO37 R1333 R1328
B18 SMLINK1
1 2 H_STP_PCI# H1 CLK_ICH_14M 10_0402_5% 10_0402_5%
EC_SWI# CLK14 CLK_ICH_48M CLK_ICH_14M <16>
R1327 10K_0402_5%
1 2 H_STP_CPU# <35> EC_SWI#
F19
RI# clocks CLK48
AF3 CLK_ICH_48M <16>
@

2
R1329 10K_0402_5% SUS_STAT# R4 P1 SUS_CLK 1 1
T18 PAD SUS_STAT#/LPCPD# SUSCLK PAD T19
1 @ 2 SB_SPKR XDP_DBRESET# G19 C1585 C1584
<4> XDP_DBRESET# SYS_RESET#
R1334 1K_0402_5% @ C16 PM_SLP_S3# @ @ 10P_0402_50V8J @ 10P_0402_50V8J
D SLP_S3# PM_SLP_S3# <35> D
1 @ 2 CR_WAKE# PM_SYNC# M6 E16 PM_SLP_S4#
<8> PM_SYNC# PMSYNC#/GPIO0 SLP_S4# PM_SLP_S5# PM_SLP_S4# <35> 2 2
R1330 10K_0402_5% G17 PM_SLP_S5# <35>

SYS / GPIO
ICH_SPI_MOSI EC_LID_OUT# SLP_S5#
1 2 <35> EC_LID_OUT# A17 SMBALERT#/GPIO11
R1331 1K_0402_5% C10 S4_STATE# @ @
OCP# H_STP_PCI# S4_STATE#/GPIO26
1 @ 2 <16> H_STP_PCI# A14
R1335 10K_0402_5% H_STP_CPU# STP_PCI# ICH_PWROK LAN_RST#
<16> H_STP_CPU# E19 STP_CPU# PWROK G20 ICH_PWROK <8> 1 2
1 2 CR_CPPE# R1336 10K_0402_5%
R1337 10K_0402_5% PM_CLKRUN# L4 M2 DPRSLPVR 1 2 No used Integrated LAN,
PM_DPRSLPVR <8,49>

Power MGT
ICH_GPIO17 <35> PM_CLKRUN# CLKRUN# DPRSLPVR/GPIO16 R1338 100_0402_5%
1 2
R1339 10K_0402_5%
<33,34> ICH_PCIE_WAKE#
ICH_PCIE_WAKE# E20 B13 PM_BATLOW# connecting LAN_RST# to GND
ICH_GPIO18 SERIRQ WAKE# BATLOW#
1 @ 2 <35> SERIRQ M5 SERIRQ
R1340 10K_0402_5% EC_THERM# AJ23 R3 PBTN_OUT# ICH_PWROK 1 2
ICH_GPIO20 <35> EC_THERM# THRM# PWRBTN# PBTN_OUT# <35>
1 @ 2 R1341 10K_0402_5%
R1342 10K_0402_5% VGATE 2 1 ICH_VGATE D21 D20 LAN_RST# 1 2
SATA_CLKREQ# <8,16,49> VGATE VRMPWRGD LAN_RST# PLT_RST# <8,17,25,30,31,35>
1 @ 2 R1343 0_0402_5% R1344 0_0402_5%
R1345 10K_0402_5% ICH_TP11 A20 D22 SB_RSMRST# EC_PWROK 1 2
T20 PAD TP11 RSMRST# @
1 2 ICH_GPIO38 R1346 10K_0402_5%
R1347 10K_0402_5% @ OCP# AG19 R5 CK_PWRGD
<4> OCP# GPIO1 CK_PWRGD CK_PWRGD <16>
1 @ 2 ICH_GPIO39 CRT_DET AH21
R1348 10K_0402_5% CR_CPPE# GPIO6 ICH_PWROK R1349 2
<30> CR_CPPE# AG21 R6 1 0_0402_5%
ICH_GPIO48 EC_SMI# GPIO7 CLPWROK
1 @ 2 <35> EC_SMI# A21
R1350 10K_0402_5% GPIO8 PM_SLP_M# +3VS
<35> EC_SCI# C12 B16 PAD T21 @
ICH_GPIO13 GPIO12 SLP_M#
C21 GPIO13
+3V ICH_GPIO17 AE18 F24 @
GPIO17 CL_CLK0 CL_CLK0 <8>

5
ICH_GPIO18 K1 B19 U26

GPIO
GPIO18 CL_CLK1

Controller Link
1 2 ICH_SMBCLK ICH_GPIO20 AF8 2 EC_PWROK

P
CR_WAKE# GPIO20 ICH_PWROK B EC_PWROK <35,37>
R1351 2.2K_0402_5% AJ22 F22 4
ICH_SMBDATA +3V <30> CR_WAKE# ICH_GPIO27 SCLOCK/GPIO22 CL_DATA0 CL_DATA0 <8> Y VGATE
1 2 T22 PAD A9 C19 1
GPIO27 CL_DATA1 A

G
R1352 2.2K_0402_5% ICH_GPIO28 D19
T23 PAD GPIO28
1 2 EC_SWI# SATA_CLKREQ# L1 C25 CL_VREF0_ICH NC7SZ08P5X_NL_SC70-5
<16> SATA_CLKREQ# @

3
SATACLKREQ#/GPIO35 CL_VREF0
1

R1353 10K_0402_5% @ ICH_GPIO38 AE19 A19 CL_VREF1_ICH

ICH_SMLINK0 R1355 ICH_GPIO39 SLOAD/GPIO38 CL_VREF1
1 2 AG22
C R1354 10K_0402_5% 10K_0402_5% ICH_GPIO48 SDATAOUT0/GPIO39 C
AF21 SDATAOUT1/GPIO48 CL_RST0# F21 CL_RST#0 <8>
1 2 ICH_SMLINK1 ICH_GPIO49 AH24 D18
R1356 10K_0402_5% ICH_GPIO57 GPIO49 CL_RST1# R1357 2
A8 1 0_0402_5%
2

LINKALERT# ICH_GPIO57 GPIO57/CLGPIO5 ICH_GPIO24

1 2 MEM_LED/GPIO24 A16 PAD T24 2 1 +3V Q90
R1358 10K_0402_5% SB_SPKR M7 C18 ICH_GPIO10 R1359 100K_0402_5% MMBT3906_SOT23-3
@
<38> SB_SPKR SPKR GPIO10/SUS_PWR_ACK
1

1 2 XDP_DBRESET# @ AJ24 C11 ICH_ACIN @ 2 1 SB_RSMRST# 1 3

C
MISC
<8> MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT ACIN <35,41,42,43,46> EC_RSMRST# <35>
R1360 10K_0402_5% R1361 B21 C20 ICH_GPIO9 D12

E
<26> ICH_TP3 TP3 WOL_EN/GPIO9 PAD T25
1 2 ICH_PCIE_WAKE# 100K_0402_5%
T26 PAD
ICH_TP8 AH20 CH751H-40PT_SOD323-2
TP8

1
R1362 1K_0402_5% ICH_TP9 AJ20 @

B
PAD

2
PM_BATLOW# T27 ICH_TP10 TP9
1 2 PAD @ AJ21 R1364 1 2 +3V
2

T28 TP10
R1363 8.2K_0402_5% @ 10K_0402_5% R1365 4.7K_0402_5%
1 2 EC_LID_OUT# @ ICH9-M ES_FCBGA676
R1366 10K_0402_5% D13A

2
1 2 ICH_GPIO10 U23D 1
R1367 10K_0402_5% PCIE_PTX_C_IRX_N1 N29 V27 DMI_MTX_IRX_N0 6
ICH_GPIO13 <34> PCIE_PTX_C_IRX_N1 PCIE_PTX_C_IRX_P1 PERN1 DMI0RXN DMI_MTX_IRX_P0 DMI_MTX_IRX_N0 <8>
1 2 <34> PCIE_PTX_C_IRX_P1 N28 V26 DMI_MTX_IRX_P0 <8> 2
R1368 10K_0402_5% C1586 2 0.1U_0402_16V7K PCIE_ITX_PRX_N1 PERP1 DMI0RXP DMI_ITX_MRX_N0
S4_STATE#
For Express Card<34> PCIE_ITX_C_PRX_N1 1
PCIE_ITX_PRX_P1
P27
PETN1 DMI0TXN
U29
DMI_ITX_MRX_P0
DMI_ITX_MRX_N0 <8>
1 <BOM Structure>
2 C1587 2 1 0.1U_0402_16V7K P26 U28 BAV99DW-7_SOT363

Direct Media Interface

<34> PCIE_ITX_C_PRX_P1 PETP1 DMI0TXP DMI_ITX_MRX_P0 <8>
R1369 10K_0402_5%
PCIE_PTX_C_IRX_N2 L29 Y27 DMI_MTX_IRX_N1 D13B
@ <33> PCIE_PTX_C_IRX_N2 PERN2 DMI1RXN DMI_MTX_IRX_N1 <8>
1 2 PROJECT_ID0 PCIE_PTX_C_IRX_P2 L28 Y26 DMI_MTX_IRX_P1 4
<33> PCIE_PTX_C_IRX_P2 PERP2 DMI1RXP DMI_MTX_IRX_P1 <8>
R1370 10K_0402_5% For Wireless LAN<33> C1588 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N2 M27 W29 DMI_ITX_MRX_N1 3
PCIE_ITX_C_PRX_N2 PETN2 DMI1TXN DMI_ITX_MRX_N1 <8>
1 2 <33> PCIE_ITX_C_PRX_P2 C1589 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_P2 M26 W28 DMI_ITX_MRX_P1 5
PETP2 DMI1TXP DMI_ITX_MRX_P1 <8>

1
R1371 10K_0402_5%

PCI - Express
1 @ 2 PCIE_PTX_C_IRX_N3 J29 AB27 DMI_MTX_IRX_N2 BAV99DW-7_SOT363 R1373
<31> PCIE_PTX_C_IRX_N3 PCIE_PTX_C_IRX_P3 PERN3 DMI2RXN DMI_MTX_IRX_P2 DMI_MTX_IRX_N2 <8>
R1401 10K_0402_5% J28 AB26 2.2K_0402_5%
<31> PCIE_PTX_C_IRX_P3 PERP3 DMI2RXP DMI_MTX_IRX_P2 <8>
1 2 PROJECT_ID1 For PCIE LAN<31> C1590 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N3 K27 AA29 DMI_ITX_MRX_N2
PCIE_ITX_C_PRX_N3 PETN3 DMI2TXN DMI_ITX_MRX_N2 <8>
R1372 10K_0402_5% C1591 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_P3 K26 AA28 DMI_ITX_MRX_P2
<31> PCIE_ITX_C_PRX_P3

2
PM_DPRSLPVR PETP3 DMI2TXP DMI_ITX_MRX_P2 <8>
1 @ 2
R1374 100K_0402_5% PCIE_PTX_C_IRX_N4 G29 AD27 DMI_MTX_IRX_N3
ICH_GPIO49 <33> PCIE_PTX_C_IRX_N4 PCIE_PTX_C_IRX_P4 PERN4 DMI3RXN DMI_MTX_IRX_P3 DMI_MTX_IRX_N3 <8>
1 @ 2 <33> PCIE_PTX_C_IRX_P4 G28 AD26 DMI_MTX_IRX_P3 <8>
R1375 1K_0402_5% C1592 2 0.1U_0402_16V7K PCIE_ITX_PRX_N4 PERP4 DMI3RXP DMI_ITX_MRX_N3
B
For Robson2 <33> PCIE_ITX_C_PRX_N4 1
PCIE_ITX_PRX_P4
H27
PETN4 DMI3TXN
AC29
DMI_ITX_MRX_P3
DMI_ITX_MRX_N3 <8> B
@ <33> PCIE_ITX_C_PRX_P4 C1593 2 1 0.1U_0402_16V7K H26 AC28
PETP4 DMI3TXP DMI_ITX_MRX_P3 <8> +3VS
PCIE_PTX_C_IRX_N5 E29 T26 CLK_PCIE_ICH#
<30> PCIE_PTX_C_IRX_N5 PCIE_PTX_C_IRX_P5 PERN5 DMI_CLKN CLK_PCIE_ICH CLK_PCIE_ICH# <16>
<30> PCIE_PTX_C_IRX_P5 E28 PERP5 DMI_CLKP T25 CLK_PCIE_ICH <16>
+3V 1 2 CP_PE# For Card Reader
<30> PCIE_ITX_C_PRX_N5 C1594 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N5 F27
R1376 10K_0402_5% C1595 2 0.1U_0402_16V7K PCIE_ITX_PRX_P5 PETN5 R1379 24.9_0402_1% R1377
<30> PCIE_ITX_C_PRX_P5 1 F26
PETP5 DMI_ZCOMP
AF29 Within 500 mils
1 @ 2 USB_OC#0 AF28 DMI_IRCOMP 1 2 +1.5VS_PCIE_ICH 3.24K_0402_1%
R1378 10K_0402_5% DMI_IRCOMP
C29
PERN6/GLAN_RXN USB20_N0
C28 AC5 USB20_N0 <33>
PERP6/GLAN_RXP USBP0N USB20_P0 CL_VREF0_ICH
+3VS
D27 PETN6/GLAN_TXN USBP0P AC4
USB20_N1 USB20_P0 <33> USB CONN
RP41 D26 AD3
PETP6/GLAN_TXP USBP1N USB20_N1 <34>
1 8 USB_OC#5 AD2 USB20_P1 New Card 1
USB_OC#9 ICH_SPI_CLK R1380 1 ICH_SPI_CLK_R USBP1P USB20_N2 USB20_P1 <34>
2 7 2 15_0402_5% D23 SPI_CLK USBP2N AC1 USB20_N2 <34>
C1596 R1381
2

3 6 USB_OC#8 ICH_SPI_CS0# R1383 1 2 15_0402_5% ICH_SPI_CS0#_R D24 AC2 USB20_P2 ESATA/USB CONN 453_0402_1%
SPI_CS0# USBP2P USB20_P2 <34>
4 5 USB_OC#11 R1382 @ <25> F23 AA5 USB20_N3 0.1U_0402_16V4Z
SPI_CS#1 SPI_CS1#GPIO58/CLGPIO6 USBP3N PAD T29 2
10K_0402_5% @ AA4 USB20_P3
USBP3P PAD T30
10K_1206_8P4R_5% ICH_SPI_MOSI R1384 1 2 15_0402_5% ICH_SPI_MOSI_R
High: CRT Plugged ICH_SPI_MISO R1385 1 2 15_0402_5% ICH_SPI_MISO_R
D25
E23
SPI_MOSI SPI USBP4N
AB2
AB3
@
@
1

RP42 CRT_DET SPI_MISO USBP4P USB20_N5

@ AA1 USB20_N5 <33>
USB_OC#10 USB_OC#0 USBP5N USB20_P5
1 8 @<34> USB_OC#0 N4
OC0#/GPIO59 USBP5P
AA2 USB20_P5 <33> USB/B
1

USB_OC#3 D CP_PE# USB20_N6 +3V

2 7 N5 W5 USB20_N6 <22>
USB_OC#7 <34> CP_PE# USB_OC#2 OC1#/GPIO40 USBP6N USB20_P6
3
4
6
5 USB_OC#6 <23> CRT_DET# 2
Q91G
<34> USB_OC#2 USB_OC#3
N6
P6
OC2#/GPIO41 USB USBP6P W4
Y3 USB20_N7 USB20_P6 <22> CMOS Camera
OC3#/GPIO42 USBP7N USB20_P7 USB20_N7 <33>
2N7002_SOT23 S M1 Y2 Mini Card(WLAN)
3

USB_OC#5 OC4#/GPIO43 USBP7P USB20_N8 USB20_P7 <33>

10K_1206_8P4R_5% N2 W1 R1386
<33> USB_OC#5 OC5#/GPIO29 USBP8N USB20_N8 <33>
USB_OC#6 M4 W2 USB20_P8 Mini Card(TV-Tuner) 3.24K_0402_1%
OC6#/GPIO30 USBP8P USB20_P8 <33>
USB_OC#7 M3 V2 USB20_N9
USB_OC#8 OC7#/GPIO31 USBP9N USB20_P9 USB20_N9 <34>
Internal TPM Strap DMI Termination Voltage USB_OC#9
N3
OC8#/GPIO44 USBP9P
V3
USB20_N10 USB20_P9 <34> Bluetooth CL_VREF1_ICH
N1 U5 USB20_N10 <34>
USB_OC#10 OC9#/GPIO45 USBP10N USB20_P10
Low= Disable* Low= Desktop used USB_OC#11
P5
OC10#/GPIO46 USBP10P
U4 USB20_P10 <34> Finger Print
P3 U1
SPI_MOSI High= iTPM enable by MCH strap GPIO49 High= Mobile* (Internal pull-up) OC11#/GPIO47 USBP11N
USBP11P U2 C1597
1
R1387
A USBRBIAS 453_0402_1% A
AG2
2 1 AG1
USBRBIAS
USBRBIAS#
No Reboot Strap 0.1U_0402_16V4Z
R1388 2
Within 500 mils Low= Default*
ICH SPI ROM for HDCP 22.6_0402_1% ICH9-M ES_FCBGA676
+3VS SB_SPKR High= "No Reboot"
+3VS R1389 U27
3.3K_0402_5% ICH_SPI_CS0# 1 8
ICH_SPI_WP# CS# VCC ICH_SPI_CLK
1
R1390 1
2
2 ICH_SPI_HOLD#
3
7
WP#
HOLD#
SCLK
SI
6
5 ICH_SPI_MOSI ICH_GPIO13 2 1 CP_PE# Security Classification Compal Secret Data Compal Electronics, Inc.
3.3K_0402_5% 4 2 ICH_SPI_MISO R1406 0_0402_5% 2008/11/10 2008/11/17 Title
GND SO Issued Date Deciphered Date
@
@ MX25L4005AMC-12G_SO8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(3/4)-USB,GPIO,PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
If ICH SPI not used, Left NC SPI ROM Footprint 150mil Custom 0.2
@ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 27 of 52
5 4 3 2 1
 5 4 3 2 1

+5VS +3VS U23F

+RTCVCC A23 A15 +1.05VS U23E
VCCRTC VCC1_05[01]
1 1 B15 AA26 H5
VCC1_05[02] VSS[001] VSS[107]

2
C1598 C1599 +ICH_V5REF A6 C15 1 1 AA27 J23
R1392 D14 V5REF VCC1_05[03] C1600 C1601 VSS[002] VSS[108]
D15 AA3 J26
100_0402_1% 0.1U_0402_16V4Z VCC1_05[04] VSS[003] VSS[109]
CH751H-40PT_SOD323-2 E15 AA6 J27
2
1U_0402_6.3V6K 2 +ICH_V5REF_SUS VCC1_05[05] 0.1U_0402_16V4Z VSS[004] VSS[110]
AE1 F15 AB1 AC22
V5REF_SUS VCC1_05[06] 2 2 VSS[005] VSS[111]
L11 AA23 K28
1

1
+ICH_V5REF VCC1_05[07] 0.1U_0402_16V4Z VSS[006] VSS[112]
AA24 L12 AB28 K29
VCC1_5_B[01] VCC1_05[08] VSS[007] VSS[113]
1 AA25 L14 AB29 L13
VCC1_5_B[02] VCC1_05[09] VSS[008] VSS[114]
AB24 L16 AB4 L15
C1602 VCC1_5_B[03] VCC1_05[10] VSS[009] VSS[115]
AB25 L17 AB5 L2
1U_0402_6.3V6K VCC1_5_B[04] VCC1_05[11] VSS[010] VSS[116]
AC24 L18 AC17 L26
2 VCC1_5_B[05] VCC1_05[12] +1.5VS_DMIPLL_ICH VSS[011] VSS[117]
AC25 M11 AC26 L27
VCC1_5_B[06] VCC1_05[13] VSS[012] VSS[118]
AD24 M18 AC27 L5
VCC1_5_B[07] VCC1_05[14] L37 1 VSS[013] VSS[119]

CORE
D AD25 P11 2 +1.5VS AC3 L7 D
+5VALW +5V +3V VCC1_5_B[08] VCC1_05[15] MBK1608301YZF_0603 VSS[014] VSS[120]
AE25 P18 AD1 M12
VCC1_5_B[09] VCC1_05[16] VSS[015] VSS[121]
AE26
VCC1_5_B[10] VCC1_05[17]
T11 1
C1604
(10UF*1, 0.01UF*1) AD10
VSS[016] VSS[122]
M13
AE27 T18 AD12 M14
VCC1_5_B[11] VCC1_05[18] VSS[017] VSS[123]
2

AE28 U11 C1603 AD13 M15

R1393 R1391 D15 VCC1_5_B[12] VCC1_05[19] VSS[018] VSS[124]
AE29 U18 10U_0805_10V4Z AD14 M16
100_0402_1% VCC1_5_B[13] VCC1_05[20] 2 VSS[019] VSS[125]
F25 V11 AD17 M17
10_0402_5% CH751H-40PT_SOD323-2 VCC1_5_B[14] VCC1_05[21] 0.01U_0402_16V7K VSS[020] VSS[126]
G25 V12 AD18 M23
VCC1_5_B[15] VCC1_05[22] VSS[021] VSS[127]
H24 V14 AD21 M28
1

+ICH_V5REF_SUS VCC1_5_B[16] VCC1_05[23] VSS[022] VSS[128]

H25 V16 AD28 M29
VCC1_5_B[17] VCC1_05[24] VSS[023] VSS[129]
1 J24 V17 +1.05VS AD29 N11
VCC1_5_B[18] VCC1_05[25] VSS[024] VSS[130]

VCCA3GP
@ J25 V18 AD4 N12
C1605 VCC1_5_B[19] VCC1_05[26] VSS[025] VSS[131]
1U_0402_6.3V6K
K24
VCC1_5_B[20] C1606
1 (4.7UF*1) AD5
VSS[026] VSS[132]
N13
K25 AD6 N14
2 VCC1_5_B[21] VSS[027] VSS[133]
L23 AD7 N15
+1.5VS_PCIE_ICH VCC1_5_B[22] 4.7U_0805_10V4Z VSS[028] VSS[134]
L24 R29 AD9 N16
VCC1_5_B[23] VCCDMIPLL 2 VSS[029] VSS[135]
(220UF*1, 22UF*2, 2.2UF*1) L25
VCC1_5_B[24]
AE12
VSS[030] VSS[136]
N17
+1.5VS L38 2 1 M24 W23 AE13 N18
KC FBM-L11-201209-221LMAT_08051 VCC1_5_B[25] VCC_DMI[1] VSS[031] VSS[137]
M25 Y23 AE14 N26
VCC1_5_B[26] VCC_DMI[2] VSS[032] VSS[138]
1 1 N23 AE16 N27
C1607 + C1608 C1609 C1610 VCC1_5_B[27] VSS[033] VSS[139]
N24 AB23 +1.05VS AE17 P12
VCC1_5_B[28] V_CPU_IO[1] VSS[034] VSS[140]
N25 AC23 1 1 AE2 P13
220U_D2_4VM_R15 10U_0805_10V4Z VCC1_5_B[29] V_CPU_IO[2] C1611 C1612 C1613 VSS[035] VSS[141]
2 2 2
P24
VCC1_5_B[30] (4.7UF*1, 0.1UF*2) AE20
VSS[036] VSS[142]
P14
P25 AG29 AE24 P15
10U_0805_10V4Z 2.2U_0603_6.3V6K VCC1_5_B[31] VCC3_3[01] 4.7U_0805_10V4Z 0.1U_0402_16V4Z VSS[037] VSS[143]
R24 AJ6 AE3 P16
VCC1_5_B[32] VCC3_3[02] 2 2 VSS[038] VSS[144]
R25 AC10 AE4 P17
VCC1_5_B[33] VCC3_3[07] 0.1U_0402_16V4Z VSS[039] VSS[145]
R26 AE6 P2
VCC1_5_B[34] VSS[040] VSS[146]
R27 AD19 AE9 P23
VCC1_5_B[35] VCC3_3[03] VSS[041] VSS[147]

VCCP_CORE
T24 AF20 AF13 P28
VCC1_5_B[36] VCC3_3[04] VSS[042] VSS[148]
T27
VCC1_5_B[37] VCC3_3[05]
AG24 close to AG29 close to AD19 close to G6 AF16
VSS[043] VSS[149]
P29
T28 AC20 AF18 P4
VCC1_5_B[38] VCC3_3[06] VSS[044] VSS[150]
T29 +3VS AF22 P7
+1.5VS_SATAPLL_ICH VCC1_5_B[39] VSS[045] VSS[151]
U24 AH26 R11
C VCC1_5_B[40] VSS[046] VSS[152] C
U25 B9 1 1 1 1 1 1 AF26 R12
L39 1 VCC1_5_B[41] VCC3_3[08] C1614 C1615 C1616 C1617 C1618 C1619 VSS[047] VSS[153]
+1.5VS 2 V24 F9 AF27 R13
MBK1608301YZF_0603 VCC1_5_B[42] VCC3_3[09] VSS[048] VSS[154]
V25 G3 AF5 R14
VCC1_5_B[43] VCC3_3[10] 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VSS[049] VSS[155]
1 1 U23 G6 AF7 R15
VCC1_5_B[44] VCC3_3[11] VSS[050] VSS[156]

PCI
2 2 2 2 2 2
W24 J2 AF9 R16
C1620 C1621 VCC1_5_B[45] VCC3_3[12] 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VSS[051] VSS[157]
W25 J7 AG13 R17
VCC1_5_B[46] VCC3_3[13] VSS[052] VSS[158]
10U_0805_10V4Z K23 K7 AG16 R18
2 2 VCC1_5_B[47] VCC3_3[14] VSS[053] VSS[159]
(10UF*1, 1UF*1) 1U_0402_6.3V6K
Y24
VCC1_5_B[48] close to AJ6 close to B9 close to K7 AG18
VSS[054] VSS[160]
R28
Y25 AG20 T12
VCC1_5_B[49] +VCC_HDA_ICH VSS[055] VSS[161]
AJ4 +3VS AG23 T13
VCCHDA R1394 0_0603_5% VSS[056] VSS[162]
AG3 T14
VSS[057] VSS[163]
AJ3 +1.5VS AG6 T15
+5VALW VCCSUSHDA R1395 0_0603_5% VSS[058] VSS[164]
AJ19 1 AG9 T16
VCCSATAPLL C1622 @ VSS[059] VSS[165]
AH12 T17
VSS[060] VSS[166]
AC8 TP_VCCSUS1_05_ICH_1 PAD T31 AH14 T23
VCCSUS1_05[1] VSS[061] VSS[167]
+1.5VS AC16 F17 TP_VCCSUS1_05_ICH_2 PAD T32
0.1U_0402_16V4Z AH17 B26
VCC1_5_A[01] VCCSUS1_05[2] VSS[062] VSS[168]
3

S
AD15 2 AH19 U12
G VCC1_5_A[02] @ VSS[063] VSS[169]
<41> SBPWR_EN# 2 1 1 AD16 @ AH2 U13
C1623 C1624 VCC1_5_A[03] +VCCSUS_HDA_ICH VSS[064] VSS[170]
AE15 AD8 TP_VCCSUS1_5_ICH_1 PAD T33 +3V AH22 U14
VCC1_5_A[04] VCCSUS1_5[1] VSS[065] VSS[171]
ARX

1 Q92 D AF15 R1396 0_0603_5% AH25 U15

1

C1625 AO3413_SOT23-3 VCC1_5_A[05] +VCCSUS1_5_ICH_INT_2 VSS[066] VSS[172]

AG15 F18 @ +1.5V AH28 U16
2
1U_0402_6.3V6K 2 VCC1_5_A[06] VCCSUS1_5[2] R1397 0_0603_5% VSS[067] VSS[173]
AH15 1 1 AH5 U17
0.1U_0402_16V4Z 1U_0402_6.3V6K VCC1_5_A[07] C1626 C1627 VSS[068] VSS[174]
AJ15 @ AH8 AD23
2 +5V VCC1_5_A[08] VSS[069] VSS[175]
VCCSUS3_3[01]
A18 Check Power Source AJ12
VSS[070] VSS[176]
U26
AC11 D16 0.1U_0402_16V4Z 0.1U_0402_16V4Z AJ14 U27
VCC1_5_A[09]
VCCPSUS

VCCSUS3_3[02] 2 2 VSS[071] VSS[177]

AD11 D17 AJ17 U3
VCC1_5_A[10] VCCSUS3_3[03] VSS[072] VSS[178]
AE11 E22 AJ8 V1
VCC1_5_A[11] VCCSUS3_3[04] VSS[073] VSS[179]
AF11 B11 V13
VCC1_5_A[12] VSS[074] VSS[180]
ATX

AG10 B14 V15

VCC1_5_A[13] VSS[075] VSS[181]
AG11 B17 V23
VCC1_5_A[14] VSS[076] VSS[182]
AH10 B2 V28
VCC1_5_A[15] VSS[077] VSS[183]
AJ10 AF1 +3V B20 V29
VCC1_5_A[16] VCCSUS3_3[05] VSS[078] VSS[184]
B B23 V4 B
VSS[079] VSS[185]
AC9 1 1 B5 V5
VCC1_5_A[17] C1628 C1629 C1630 VSS[080] VSS[186]
B8 W26
VSS[081] VSS[187]
AC18 C26 W27
VCC1_5_A[18] 0.022U_0402_16V7K 0.1U_0402_16V4Z VSS[082] VSS[188]
AC19
VCC1_5_A[19] 2 2 (0.1UF*1, 0.022UF*2) C27
VSS[083] VSS[189]
W3
T1 E11 Y1
VCCSUS3_3[06] 0.022U_0402_16V7K VSS[084] VSS[190]
AC21 T2 E14 Y28
VCC1_5_A[20] VCCSUS3_3[07] VSS[085] VSS[191]
T3 E18 Y29
VCCSUS3_3[08] VSS[086] VSS[192]
G10 T4 E2 Y4
VCC1_5_A[21] VCCSUS3_3[09] VSS[087] VSS[193]
G9
VCC1_5_A[22] VCCSUS3_3[10]
T5 close to A18 close to T1 E21
VSS[088] VSS[194]
Y5
T6 E24 AG28
VCCSUS3_3[11] VSS[089] VSS[195]
AC12 U6 E5 AH6
VCCPUSB

VCC1_5_A[23] VCCSUS3_3[12] VSS[090] VSS[196]

AC13 U7 E8 AF2
VCC1_5_A[24] VCCSUS3_3[13] VSS[091] VSS[197]
close to AC7 AC14
VCC1_5_A[25] VCCSUS3_3[14]
V6 F16
VSS[092] VSS[198]
B25
V7 F28
VCCSUS3_3[15] VSS[093]
+1.5VS AJ5 W6 F29
VCCUSBPLL VCCSUS3_3[16] VSS[094]
1 1 W7 G12
VCCSUS3_3[17] VSS[095]
USB CORE

C1631 C1632 AA7 Y6 G14 A1

VCC1_5_A[26] VCCSUS3_3[18] VSS[096] VSS_NCTF[01]
0.1U_0402_16V4Z
close to AJ5 AB6
VCC1_5_A[27] VCCSUS3_3[19]
Y7 G18
VSS[097] VSS_NCTF[02]
A2
AB7 T7 G21 A28
2 2 VCC1_5_A[28] VCCSUS3_3[20] VSS[098] VSS_NCTF[03]
AC6 G24 A29
0.1U_0402_16V4Z VCC1_5_A[29] VSS[099] VSS_NCTF[04]
AC7 G26 AH1
VCC1_5_A[30] VSS[100] VSS_NCTF[05]
G27 AH29
VSS[101] VSS_NCTF[06]
2 1 +VCCLAN1_05_INT_ICH A10 G8 AJ1
C1633 VCCLAN1_05[1] +VCCCL1_05_INT_ICH VSS[102] VSS_NCTF[07]
A11 G22 H2 AJ2
0.1U_0402_16V4Z VCCLAN1_05[2] VCCCL1_05 +VCCCL1_5_INT_ICH VSS[103] VSS_NCTF[08]
G23 H23 AJ28
+VCCLAN_ICH VCCCL1_5 VSS[104] VSS_NCTF[09]
+3VS A12 H28 AJ29
R1398 0_0603_5% VCCLAN3_3[1] VSS[105] VSS_NCTF[10]
1 B12 1 1 1 H29 B1
C1634 VCCLAN3_3[2] C1635 C1637 C1636 VSS[106] VSS_NCTF[11]
A24 +3VS B29
VCCCL3_3[1] VSS_NCTF[12]
VCCCL3_3[2]
B24 (0.1UF*1)
GLAN POWER

+1.5VS +VCC_GLANPLL_ICH A27 1U_0402_6.3V6K

2 R1399 0_0603_5% VCCGLANPLL 2 2 2 ICH9-M ES_FCBGA676
1
0.1U_0402_16V4Z C1639 D28 0.1U_0402_16V4Z 0.1U_0402_16V4Z
A
C1638 VCCGLAN1_5[1] @
A
D29
VCCGLAN1_5[2]
(10UF*1, 2.2UF*1) 10U_0805_10V4Z
2
E26
VCCGLAN1_5[3] @
2.2U_0603_6.3V6K
E27
VCCGLAN1_5[4] (1UF*1, 0.1UF*1)
A26
+VCCGLAN_ICH VCCGLAN3_3
+1.5VS
R1400 0_0603_5% ICH9-M ES_FCBGA676
C1640
(4.7UF*1)
+3VS Security Classification
Classification Compal Secret Data Compal Electronics, Inc.
4.7U_0805_10V4Z Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9M(4/4)-POWER&GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 28 of 52
5 4 3 2 1
 5 4 3 2 1

+5VS +3VS

0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 1 1 1 1
C1934 C1935 C1936 C1937 C1938 C1939

2 2 2 2 2 2

D 1000P_0402_50V7K 10U_0805_10V4Z 1000P_0402_50V7K 10U_0805_10V4Z D

SATA HDD Conn.

JSATA1
<26> SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 1 2 SATA_DTX_IRX_N0
C1940 0.01U_0402_16V7K 1
SATA_ITX_C_DRX_P0 GND
<26> SATA_ITX_C_DRX_P0 2 HTX+
<26> SATA_DTX_C_IRX_P0 SATA_DTX_C_IRX_P0 1 2 SATA_DTX_IRX_P0 SATA_ITX_C_DRX_N0 3
C1941 0.01U_0402_16V7K <26> SATA_ITX_C_DRX_N0 HTX-
4 GND
SATA_DTX_IRX_N0 5
SATA_DTX_IRX_P0 HRX-
6 HRX+
7 GND

+3VS 8 VCC3.3
9 VCC3.3
10 VCC3.3
11 GND
12 GND
13 GND
+5VS 14 VCC5
15 VCC5
16 VCC5
17 GND
18 RESERVED
19 GND
C 20 C
VCC12
21 VCC12 GND 24
22 VCC12 GND 23

OCTEK_SAT-22SU1G_NR

CONN@
+5VS

0.1U_0402_16V4Z

1 1 1
C1942 C1943 C1944

2 2 2

1000P_0402_50V7K 10U_0805_10V4Z

SATA ODD Conn.

B JSATA2 B

1 1
SATA_ITX_C_DRX_P1 2
<26> SATA_ITX_C_DRX_P1 SATA_ITX_C_DRX_N1 2
<26> SATA_ITX_C_DRX_N1 3 3
4 4
SATA_DTX_IRX_N1 5
SATA_DTX_IRX_P1 5
6 6
7 7
R1664 1 2 1K_0402_1% 8 8
+5VS 9 9
@ 10 10
11 11
12 12
13 13
14 14 GND 16
15 15 GND 17

OCTEK_SLS-13DB1G_NR

<26> SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_N1 1 2 SATA_DTX_IRX_N1

C1945 0.01U_0402_16V7K

A <26> SATA_DTX_C_IRX_P1 SATA_DTX_C_IRX_P1 1 2 SATA_DTX_IRX_P1 A

C1946 0.01U_0402_16V7K

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & ODD Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 29 of 52
5 4 3 2 1
 5 4 3 2 1

MDIO PULL HIGH/LOW ?

+3VS L70 +1.8VS_APVDD
40mil MBK1608121YZF_0603
0.1U_0402_16V4Z 0.1U_0402_16V4Z
40mil 0.1U_0402_16V4Z
+1.8VS 1 2
+3V_MCVCC
1 1 1 1 1 1 1 1 1
C1947 C1948 C1949 C1950 C1951 C1952 C1953 C1954 C1955
@ XDWP_SDWP 1 2
D 0.1U_0402_16V4Z R1665 10K_0402_5% D
2 2 2 2 2 2 2 2 2
10U_0805_10V4Z XD_RB 1 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K R1666 10K_0402_5%

+3VS

XD_CLE 1 2
U48 R1667 10K_0402_5%

3 5 +1.8VS_APVDD XDCD0#_SDCD# 1 2
<16> CLK_PCIE_READER# APCLKN APVDD
4 10 R1668 4.7K_0402_5%
<16> CLK_PCIE_READER APCLKP APV18
TAV33 30 +3VS
PCIE_ITX_C_PRX_N5 9 XDCD1#_MSCD# 1 2
<27> PCIE_ITX_C_PRX_N5 APRXN
PCIE_ITX_C_PRX_P5 8 19 R1669 4.7K_0402_5%
<27> PCIE_ITX_C_PRX_P5 APRXP DV33
DV33 20
<27> PCIE_PTX_C_IRX_N5 C1956 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_N5 11 44
C1957 1 0.1U_0402_16V7K PCIE_PTX_IRX_P5 APTXN DV33
<27> PCIE_PTX_C_IRX_P5 2 12 APTXP DV18 18 +1.8VS_APVDD
DV18 37
R1670 1 2 8.2K_0402_1% APREXT 7 APREXT
APREXT 12 mil MDIO0 48 XD_SD_MS_D0
47 XD_SD_MS_D1
MDIO1 XD_SD_MS_D2
+3VS 38 PCIES_EN MDIO2 46
XD_SD_MS_D3 XD_RE
39 PCIES JMB385 MDIO3
MDIO4
45
43 SDCMD_MSBS_XDWE# R1671
1 2
200K_0402_5%
42 MDIO5 R1672 1 2 22_0402_5% XDCE_SDCLK_MSCLK
MDIO5 XDWP_SDWP XD_ALE
MDIO6 41 1 2
40 XD_CLE R1673 200K_0402_5%
C MDIO7 XD_D4 C
MDIO8 29
<8,17,25,27,31,35> PLT_RST# 1 28 XD_D5
XRSTN MDIO9 XD_D6
2 XTEST MDIO10 27
26 XD_D7
R1674 MDIO11 XD_RE
MDIO12 25
<27> CR_CPPE# 1 2 0_0402_5% 13 SEEDAT MDIO13 23 XD_RB
TP_SEECLK 14 22 XD_ALE
T39 PAD SEECLK MDIO14
D40 @ @ 34
CH751H-40PT_SOD323-2 XDCD1#_MSCD# NC
15 CR1_CD1N NC 35
<27> CR_WAKE# 1 2 XDCD0#_SDCD# 16 36
CR1_CD0N NC
1 2 APGND 6
R1675 MC_PWREN# 17 D41
CR1_PCTLN
0_0402_5%
@ MC_PWREN# 30 mil GND 24 XDCD0#_SDCD# 2
@ 31 1 XD_CD#
GND XDCD1#_MSCD#
<42> 5IN1_LED# 21 CR1_LEDN GND 32 3
GND 33
DAN202UT106_SC70-3 C1958

270P_0402_50V7K
JMB385-LGEZ0B_LQFP48_7X7

4 IN 1 Socket Push Type(New)

B JREAD1 B

3 21
Memory Card Power Switch +3V_MCVCC
XD_SD_MS_D0 32
XD-VCC SD-VCC
MS-VCC 28
+3V_MCVCC

XD_SD_MS_D1 XD-D0 XDCE_SDCLK_MSCLK

10 XD-D1 7 IN 1 CONN SD_CLK 20
XD_SD_MS_D2 9 14 XD_SD_MS_D0
+3VS +3V_MCVCC XD_SD_MS_D3 XD-D2 SD-DAT0 XD_SD_MS_D1
8 XD-D3 SD-DAT1 12
XD_D4 7 30 XD_SD_MS_D2
U49 XD_D5 XD-D4 SD-DAT2 XD_SD_MS_D3
40mil XD_D6
6 XD-D5 SD-DAT3 29
XD_D4 (MMC Data Bit 4)
1 GND OUT 8 5 XD-D6 SD-DAT4 27
2 7 XD_D7 4 23 XD_D5 (MMC Data Bit 5)
IN OUT C1959 1 C1960 1 C1961 1 XD-D7 SD-DAT5 XD_D6 (MMC Data Bit 6)
3 IN OUT 6 SD-DAT6 18
MC_PWREN# 4 5 SDCMD_MSBS_XDWE# 34 16 XD_D7 (MMC Data Bit 7)
EN# FLG XDWP_SDWP XD-WE SD-DAT7 SDCMD_MSBS_XDWE#
33 XD-WP SD-CMD 25
1

TPS2061DRG4_SO8 4.7U_0805_10V4Z 0.1U_0402_16V4Z XD_ALE 35 1 XDCD0#_SDCD#

R1676 2 2 2 XD_CD# XD-ALE SD-CD-SW
40 XD-CD
@ 300_0603_5% 0.1U_0402_16V4Z XD_RB 39 2 XDWP_SDWP
XD_RE XD-R/B SD-WP-SW
38 XD-RE
XDCE_SDCLK_MSCLK 37
1 2

XD_CLE XD-CE XDCE_SDCLK_MSCLK

D 36 XD-CLE MS-SCLK 26
17 XD_SD_MS_D0
MC_PWREN# @ Q116 MS-DATA0 XD_SD_MS_D1
2 11 7IN1 GND MS-DATA1 15
G 2N7002_SOT23 31 19 XD_SD_MS_D2
7IN1 GND MS-DATA2 XD_SD_MS_D3
S 24
3

MS-DATA3 XDCD1#_MSCD#
MS-INS 22
13 SDCMD_MSBS_XDWE#
@ MS-BS
41 7IN1 GND
42 7IN1 GND
A A
MC_PWREN# 1 2 +3V_MCVCC TAITW_R015-B10-LM
R1677 0_0805_5%
1 CONN@
C1962

4.7U_0805_10V4Z
2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Card Reader JMB385
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 30 of 52
5 4 3 2 1
 5 4 3 2 1

LAN AR8121/8112
L71 R1678 49.9_0402_1%
+1.2_AVDDL

A
R
8
1
2
1
:
4.7UH_1008HC-472EJFS-A_5%_1008 LAN_MIDI0+ 1 2
+3V_LAN 1 2 +1.2_DVDDL R1679 49.9_0402_1% 1 2 C1963 0.1U_0402_16V4Z
LAN_MIDI0- 1 2
R1682 49.9_0402_1%
R1680 1 2 0_0603_5% R1681 2 0_0603_5% LAN_MIDI1+

4
.
7
u
H
c
h
o
k
e
1 1 2
8121@ R1683 49.9_0402_1% 1 2 C1964 0.1U_0402_16V4Z
8121@ 8121@ LAN_MIDI1- 1 2
R1684 49.9_0402_1%
D 0_0603_5% LAN_MIDI2+ 1 2 clos to u40 D

P
i
n
1
1
MMJT9435T1G_SOT223 R1685
1 2 R1686 1 2 0_0603_5% AVDDVCO1 R1687 49.9_0402_1% 1 2 C1965 0.1U_0402_16V4Z

1
1 1 1 LAN_MIDI2- 1 2
C1966 R1688 8112@ C1968 R1689 49.9_0402_1%
8121@ 8121@
10K_0402_1% C1967 LAN_MIDI3+ 1 2
3

0.1U_0402_16V4Z Q117 1000P_0402_50V7K 1U_0603_10V4Z R1691 49.9_0402_1%

8121@ 1 2 C1969 0.1U_0402_16V4Z
2 L72 2 2 LAN_MIDI3- 1 2
2

P
i
n
5

P
i
n
4
2
1 R1690
1 2 0_0603_5% VDDLO/CTR12 1 2 AVDDVCO2 8121@ 8121@
8121@ 1
+1.2_AVDDL

P
i
n
6
8121@
+2.5V_AVDDH R1692
1 8121@ 2 0_0603_5% +2.5V_VDD 4.7UH_1008HC-472EJFS-A_5%_1008 C1970 8121@
+3V_LAN +3V_LAN
4
2

P
i
n
2
2
P
i
n
3
6
1 +1.2_AVDDL +1.2_AVDDL R1693
1 8121@ 2 0_0603_5% DVDDL/AVDDL 0.1U_0402_16V4Z
2
1

1
P
i
n
2
5
C1971 C1972 +2.5V_AVDDH R1694 1 8121@ 2 0_0603_5% SPI_DO/AVDDH

A
R
8
1
1
3
/
A
R
8
1
2
1
:
I
f
o
v
e
r
c
l
o
c
k
i
n
g
,
R
5
9
2
,
L
4
9
s
t
u
f
f
e
d
a
10U_0603_6.3V6M 1 1 R1695
2 0.1U_0402_16V4Z C1973 8121@ C1974 4.7K_0402_1%
2

r
e
m
o
v
e
d
.
I
f
n
o
t
o
v
e
r
c
l
o
c
k
i
n
g
,
R
5
9
1
,
L
4
9
s
u
f
f
e
d
a
n
d
R
5
9
2
e
m
o
v
e
d
.
8121@ 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1
8121@ 2 2

P
i
n
2
8
+1.2_DVDDL R1696 1 2 0_0603_5%
1 SPI_CLK/DVDDL R1697
8121@ C1975 U50 4.7K_0402_1%

A
R
8
1
1
2
:

S
t
u
f
f
R
5
9
1
,
R
4
8
a
n
d
L
4
9
f
o
r
a
l
l
m
o
d
e
.
8121@ 1 A0 VCC 8
0.1U_0402_16V4Z 2 7

2
2 A1 WP TWSI_SCL
3 A2 SCL 6
4 5 TWSI_SDA
GND SDA

P
i
n
4
5
+1.2_DVDDL R1698 1 2 0_0603_5%
8121@ AVDDL/DVDDL
1U_0603_10V4Z @ AT24C02BN-SH-T_SO8
C1976
8121@
1 2 U51
C C
A
R
8
1
1
2
:

VDDHO/VDD18O 1 30 TWSI_SDA
<32> LAN_TCT VDDHO/VDD18O/VDD18O TWSI_DATA
29 TWSI_SCL
C1978 0.1U_0402_16V4Z TWSI_CLK 10/100_LINK_LED
LED_LINK10_100n 48
+2.5V_AVDDH 1 2 +3V_LAN 2 47
0_0603_5% 1U_0603_10V4Z VDD3V LED_ACTn LAN_ACTIVITY# <32>
C1977
P
i
n
1

1+2.5V_AVDDH R1699
1 2 VDDHO/VDD18O
SPI_CS/LED_DUPLEXn/LED_DUPLEXn 27
C1979 1 2 +2.5V_VDD 6 VDD3V/VDDHO/VDDHO
10U_0805_10V4Z 1000_LINK_LED
2 CE2 is 8112@
ceramic capacitor VDDLO/CTR12 5 VDDLO/CTR12/CTR12
SPI_DI/NC/LED_Link1000n 26
C1980 0.1U_0402_16V4Z
40 CLK_PCIE_C_LAN#1 2
REFCLKN CLK_PCIE_C_LAN 1 CLK_PCIE_LAN# <16>
REFCLKP 41 2
+1.2_AVDDL LAN_RESET# 3 C1981 0.1U_0402_16V4ZCLK_PCIE_LAN <16>
<8,17,25,27,30,35> PLT_RST# PERSTn
0_0603_5% 14 LAN_MIDI0-
C1983 TXN0/TXN0/TRXN0 LAN_MIDI0- <32>
P
i
n
5

AVDDL R1700
1 2 1 VDDLO/CTR12 13 LAN_MIDI0+
TXP0/TXP0/TRXP0 LAN_MIDI0+ <32>
C1982 2 1 VAUX/VREF 7 18 LAN_MIDI1-
VAUX_AVL/VBG1P18/VBG1P18 RXN1/RXN1/TRXN1 LAN_MIDI1- <32>
0_0402_5% 17 LAN_MIDI1+
RXP1/RXP1/TRXP1 LAN_MIDI1+ <32>
8112@ 0.1U_0402_16V4Z <35> EC_PME# 1000P_0402_50V7K R1701 1 2 4 WAKEn NC/NC/TRXN2 21 LAN_MIDI2-
LAN_MIDI2- <32>
2 C1984 1
<27> PCIE_PTX_C_IRX_N3 2 0.1U_0402_16V7K PCIE_PTX_IRX_N3 37 TX_N NC/NC/TRXP2 20 LAN_MIDI2+
LAN_MIDI2+ <32>

A
t
h
e
r
o
s
0_0603_5% <27> PCIE_PTX_C_IRX_P3 C1985 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_P3 38 24 LAN_MIDI3-
TX_P NC/NC/TRXN3 LAN_MIDI3- <32>
P
i
n
6

+3V_LAN R1702
1 2 8121@
+2.5V_VDD PCIE_ITX_C_PRX_N3 44 23 LAN_MIDI3+
<27> PCIE_ITX_C_PRX_N3 RX_N NC/NC/TRXP3 LAN_MIDI3+ <32>
0_0603_5% PCIE_ITX_C_PRX_P3 43
<27> PCIE_ITX_C_PRX_P3 RX_P
P
i
n
7

+3V_LAN R1703
1 2
0_0603_5%
VAUX/VREF AR8112/8113/8121
8112@ Place closed to Chip LAN_X1 9 42 AVDDVCO2
XTLO AVDDL0
P
i
n
2
2
P
i
n
3
6

+1.2_DVDDL R1704
1 2 DVDDL/AVDDL LAN_X2 10 39 +1.2_AVDDL 1 2 C1986 0.1U_0402_16V4Z
0_0603_5% XTLI AVDDL1 AVDDL/DVDDL C1987 0.1U_0402_16V4Z
8112@ AVDDL2 36 1 2
P
i
n
4
5

+1.2_AVDDL R1705
1 2 AVDDL/DVDDL 22 AVDDL/DVDDL 1 2 C1988 0.1U_0402_16V4Z
B DVDDL/AVDDL/AVDDL +1.2_AVDDL C1989 0.1U_0402_16V4Z B
8112@ 34 TESTMODE AVDDL3 16 1 2
35 11 AVDDVCO1
NC AVDDL4 +1.2_AVDDL
8112@ AVDDL5 8 1 2 C1990 0.1U_0402_16V4Z

Y2 +3V_LAN
LAN_X1 1 2 LAN_X2 60mil 31 46 +1.2_DVDDL 1 2 C1991 0.1U_0402_16V4Z
<16,27,33,34> ICH_SMBCLK SMCLK DVDDL0
+3VALW 1 2 +3V_LAN 1 2 33 45 AVDDL/DVDDL 1 2 C1992 0.1U_0402_16V4Z
25MHZ_20P R1707 0_1206_5% R1706 4.7K_0402_1% SMDATA AVDDL/DVDDL/DVDDL +1.2_DVDDL
1 1 DVDDL1 32 1 2 C1993 0.1U_0402_16V4Z
1 1 1 1 28 SPI_CLK/DVDDL
<16,27,33,34> ICH_SMBDATA SPI_CLK/DVDDL/DVDDL
C1994 C1995 C1996 C1997 C1998 C1999
27P_0402_50V8J 27P_0402_50V8J 49
2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z GND SPI_DO/AVDDH
R1708 SPI_DO/AVDDH/AVDDH 25
2 2 2 2 2.37K_0402_1% +2.5V_AVDDH 1
AVDDH0 19 2 C2000 0.1U_0402_16V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2 12 15 +2.5V_AVDDH 1 2 C2001 0.1U_0402_16V4Z
RBIAS AVDDH1

For AR8112: R294=2.49K

8121@ AR8121-AL1E_QFN48_6X6
For AR8113/8121: R294==2.37K
D42
10/100_LINK_LED 1 2

1SS355_SOD323-2

A LAN_LINK# <32> A

D43
1000_LINK_LED 1 2 Security Classification Compal Secret Data Compal Electronics, Inc.
1SS355_SOD323-2 Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Atheros Ar121/8112
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 31 of 52
5 4 3 2 1
 5 4 3 2 1

LAN AR8121/8112
D T40 D
1 TCT1 MCT1 24
<31> LAN_MIDI0+ LAN_MIDI0+ L_LAN_MIDI0+ 2 23 RJ45_MIDI0+
LAN_MIDI0- L_LAN_MIDI0- TD1+ MX1+ RJ45_MIDI0-
<31> LAN_MIDI0- 3 TD1- MX1- 22
4 TCT2 MCT2 21
L_LAN_MIDI1+ 5 20 RJ45_MIDI1+
LAN_MIDI1+ L_LAN_MIDI1- TD2+ MX2+ RJ45_MIDI1-
<31> LAN_MIDI1+ 6 TD2- MX2- 19 1 2
7 TCT3 MCT3 18
<31> LAN_MIDI1- LAN_MIDI1- L_LAN_MIDI2+ 8 17 RJ45_MIDI2+ C2002
L_LAN_MIDI2- TD3+ MX3+ RJ45_MIDI2- 220P_0402_50V7K
9 TD3- MX3- 16
10 TCT4 MCT4 15
<31> LAN_MIDI2+ LAN_MIDI2+ L_LAN_MIDI3+ 11 14 RJ45_MIDI3+ JPJ1
L_LAN_MIDI3- TD4+ MX4+ RJ45_MIDI3- L_LAN_ACTIVITY# 12
12 TD4- MX4- 13 <31> LAN_ACTIVITY# Yellow LED-
<31> LAN_MIDI2- LAN_MIDI2-
350uH_GSL5009-1 LF 2 1 11
+3V_LAN Yellow LED+
R1709 1K_0402_5%
<31> LAN_MIDI3+ LAN_MIDI3+ RJ45_MIDI3- 8 Guide Pin
PR4-
<31> LAN_MIDI3- LAN_MIDI3- RJ45_MIDI3+ 7 PR4+

1
RJ45_MIDI1- 6
R1710 R1711 PR2-
75_0402_1% 75_0402_1% RJ45_MIDI2- 5
LAN_TCT PR3-
<31> LAN_TCT

1
RJ45_MIDI2+ 4 PR3+
1 1 1 1 8121@
R1712
8121@ R1713 RJ45_MIDI1+ 3
C2003 C2004 C2005 C2006 75_0402_1% 75_0402_1% PR2+
RJ45_MIDI0- 2

2
C 0.1U_0402_16V4Z 0.1U_0402_16V4Z PR1- C
SHLD2 14
2 2 2 2 RJ45_GND RJ45_MIDI0+ 1 PR1+
SHLD1 13
0.1U_0402_16V4Z8121@ 0.1U_0402_16V4Z 40mil L_LAN_LINK# 10
<31> LAN_LINK# Green LED-

+3V_LAN 2 1 9 Green LED+

8121@ R1714 1K_0402_5%
Place close to TCT pin SUYIN_100073FR012G101ZL

1 2

C2007
220P_0402_50V7K

RJ45_GND 1 2 LANGND 40mil

1 1
C2008
1000P_1206_2KV7K C2009 C2010
4.7U_0805_10V4Z
2 2

0.1U_0402_16V4Z

B L_LAN_ACTIVITY# B
1 2
C2011
68P_0402_50V8J
@
L_LAN_LINK# 1 2
C2012
68P_0402_50V8J
@

For EMI

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN Magnetic & RJ45
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 32 of 52
5 4 3 2 1
 A B C D E

For Robson2
+1.5VS +3VS

1
C2013 1 1 1 1 Mini Card Power Rating
C2014 C2015 C2016 C2017
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z Power Primary Power (mA) Auxiliary Power (mA)
2 KAL90@ KAL90@ KAL90@ KAL90@ KAL90@
2 2 2 2
Peak Normal Normal
1 1
+3VS 1000 750
JMINI1 +3V 330 250 250 (wake enable)
1 2 +3VS
1 2
3
3 4
4 +1.5VS 500 375 5 (Not wake enable)
5 5 6 6 +1.5VS
<16> MINI1_CLKREQ# 7 8
7 8
9 9 10 10
<16> CLK_PCIE_MINI1# 11 11 12 12
<16> CLK_PCIE_MINI1 13 14
13 14
15 15 16 16

17 18
17 18
19 20
19 20 PLT_RST_BUF#
21 22 PLT_RST_BUF# <25>
21 22
<27> PCIE_PTX_C_IRX_N4 23 23 24 24
<27> PCIE_PTX_C_IRX_P4 25 26
25 26
27 27 28 28
29 30 MINI1_SMBCLK R1715 1 @ 2 0_0402_5% ICH_SMBCLK ICH_SMBCLK <16,27,31,34>
29 30 MINI1_SMBDATA
<27> PCIE_ITX_C_PRX_N4 31 32 R1716 1 @ 2 0_0402_5% ICH_SMBDATA ICH_SMBDATA <16,27,31,34>
31 32
<27> PCIE_ITX_C_PRX_P4 33 34
33 34
35 35 36 36 USB20_N7 <27>
37 37 38 38 USB20_P7 <27>
39 40
+3VS
41
43
39
41
40
42 42
44
(LED_WWAN#)
(LED_WLAN#)
USB CONN.
43 44
For MINICARD Port80 Debug 45
45 46
46
KAL90@ 47 48
E51TXD_P80DATA R1717 1 47 48 +USB_VCCA
<35> E51TXD_P80DATA 2 0_0402_5% CL_RST#1_R 49 49 50 50
E51RXD_P80CLK 51 52 W=80mils
<35> E51RXD_P80CLK 51 52 +USB_VCCA
2 2

G1
G2
G3
G3
1
1
FOX_AS0B226-S99N-7F C2018 + C2019

53
54
55
56
CONN@ 150U_D2_6.3VM
@ 470P_0402_50V7K
2 2

JUSB1
D62
1 VCC
4 2 USB20_P0 USB20_N0 2
+USB_VCCA VIN IO1 <27> USB20_N0 D-
USB20_P0 3
USB20_N0 <27> USB20_P0 D+
3 1 4
IO2 GND GND
PRTR5V0U2X_SOT143-4 5
GND1
6
GND2
7
For Wireless LAN 8
GND3
GND4
SUYIN_020173MR004G565ZR
CONN@
+3VS_WLAN +1.5VS

+3VS_WLAN R1718 1 2 0_1206_5% +3VS 1 1 1 1 1 1

C2020 C2021 C2022 C2023 C2024 C2025
R1719 1 @ 2 0_1206_5% +3V
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
To USB/B Connector
2 2 2 2 2 2
80mil +5VALW
JP15
3 JMINI2 3
1 1 +5VALW
<27,34> ICH_PCIE_WAKE#
R1720 1 @ 2 0_0402_5% 1 (WAKE#) 2 +3VS_WLAN 2
WLAN_BT_DATA 1 2 2
<34> WLAN_BT_DATA 3 4 3 SYSON# <34,41> 1
WLAN_BT_CLK 3 4 3 C2026
<34> WLAN_BT_CLK 5 5 6 6 +1.5VS 4 4
<16> MINI2_CLKREQ# 7 8 5 USB20_N5
7 8 5 USB20_P5 USB20_N5 <27>
9 10 6 4.7U_0805_10V4Z
9 10 6 USB20_P5 <27> 2
<16> CLK_PCIE_MINI2# 11 12 7
11 12 7
<16> CLK_PCIE_MINI2 13 14 8 USB_OC#5 <27>
13 14 8
15 16 9
15 16 GND
GND 10

17 18 ACES_85201-08051
17 18 WL_OFF#
19 19 20 20 WL_OFF# <35>
21 22 PLT_RST_BUF#
21 22 +3V_WLAN R1721 1
<27> PCIE_PTX_C_IRX_N2 23 23 24 24 2 0_0603_5% +3VS
25 26 R1722 1 @ 2 0_0603_5% +3V
<27> PCIE_PTX_C_IRX_P2 25 26
27 28
27 28 MINI2_SMBCLK R1723 1
29 30 @ 2 0_0402_5% ICH_SMBCLK
29 30 MINI2_SMBDATA R1724 1
<27> PCIE_ITX_C_PRX_N2 31 32 @ 2 0_0402_5% ICH_SMBDATA
31 32
<27> PCIE_ITX_C_PRX_P2 33 34
33 34
35 36 USB20_N8 <27>
35 36
37 37 38 38 USB20_P8 <27>
+3VS_WLAN 39 40
39 40
41 42 (LED_WWAN#)
41 42
43 44 (LED_WLAN#) MINI1_LED# <36>
43 44
For MINICARD Port80 Debug 45
45 46
46

E51TXD_P80DATA R1725 1 2 0_0402_5% CL_RST#2_R

47
49
47 48 48
50
(9~16mA)
E51RXD_P80CLK 49 50
51 52
51 52
G1
G2
G3
G3

4 FOX_AS0B226-S99N-7F 4
53
54
55
56

CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MINI CARD (WLAN & Robson2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 33 of 52
A B C D E
 A B C D E

New Card Power Switch

New Card Socket (Left/TOP)
U52 +3VALW_CARD +3VS_CARD +1.5VS_CARD
40mil
+1.5VS 12 11 +1.5VS_CARD Imax = 0.275A Imax = 1.35A Imax = 0.75A JEXP1
1.5Vin 1.5Vout
14 13
1.5Vin 1.5Vout
1 GND
60mils 1 1 1 1 1 1 <27> USB20_N1 2 USB_D-
+3VS 2 3 +3VS_CARD C2027 C2028 C2029 C2030 C2031 C2032 3
1 3.3Vin 3.3Vout <27> USB20_P1 USB_D+ 1
4 5 CP_USB# 4
3.3Vin 3.3Vout 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z CPUSB#
40mil 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z
5 RSV
+3V 17 AUX_IN AUX_OUT 15 +3VALW_CARD 6 RSV
<16,27,31,33> ICH_SMBCLK 7
PCI_RST# SMB_CLK
<25> PCI_RST# 6 19 <16,27,31,33> ICH_SMBDATA 8
SYSRST# OC# SMB_DATA
+1.5VS_CARD 9 +1.5V
SYSON 20 8 PERST1# 10
<35,41,47> SYSON SHDN# PERST# +1.5V
<27,33> ICH_PCIE_WAKE# 11 WAKE#
SUSP# 1 16 +3VS 12
<35,37,41,50> SUSP# STBY# NC +3VALW_CARD +3.3VAUX
PERST1# 13
CP_PE# PERST#
10 CPPE# GND 7 +3VS_CARD 14 +3.3V
(Internal Pull High to AUXIN) +3VS 1 15
CP_USB# C2033 CLKREQ1# +3.3V
9 CPUSB# Thermal_Pad 21 16 CLKREQ#
(Internal Pull High to AUXIN) CP_PE# 17
<27> CP_PE# CPPE#

1
RCLKEN1 18 0.1U_0402_16V4Z 18
RCLKEN 2 <16> CLK_PCIE_CARD# REFCLK-
R1726 19
<16> CLK_PCIE_CARD REFCLK+

5
G577NSR91U_TQFN20_4x4 10K_0402_5% U53 20
CLKREQ1# GND
2 21

G Vcc
B <27> PCIE_PTX_C_IRX_N1 PERn0
4 22

2
Y EXP_CLKREQ# <16> <27> PCIE_PTX_C_IRX_P1 PERp0
1 23
A GND
<27> PCIE_ITX_C_PRX_N1 24
PETn0

1
D NC7SZ32P5X_NL_SC70-5 <27> PCIE_ITX_C_PRX_P1 25

3
RCLKEN1 2 Q118 PETp0
26 GND
G 2N7002_SOT23
+3VS +3V +1.5VS S 27 29

3
GND GND
28 GND GND 30

1 1 1 SANTA_131851-A_LT
C2034 C2035 C2036
CONN@
10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z
2 2 2
2 +3V +3VS 2

1
R577
0_0603_5%
R578
0_0603_5%
Finger Print Conn.
@ KAL90@
JP16
ESATA CONN

2
KAL90@ C2037 6
0.1U_0402_16V4Z G2
5 G1
2 1 4
USB20_N10 4
<27> USB20_N10 3 3
USB20_P10 2
<27> USB20_P10 2
1
1

2
+USB_VCCA
D44 ACES_85201-04051 W=60mils
SM05T1G_SOT23-3 1000P_0402_50V7K
Bluetooth Conn. CONN@ 1
1 1
C2038 +

1
150U_Y_6.3VM C2039 C2040
+3VALW +3VS @ 2 2 2
0.1U_0402_16V4Z
@
JP17
1 1 1 USB
D59 USB20_N2 VBUS
C2041 C2042 2
USB20_P2 <27> USB20_N2 USB20_P2 D-
+USB_VCCA 4 2 <27> USB20_P2 3
0.1U_0402_16V4Z 1U_0603_10V4Z VIN IO1 D+
4
S GND
3

2 2 USB20_N2 3 1
3
G IO2 GND 3
<35> BT_ON# 1 2 2 5 GND
R1727 10K_0402_5% Q119 PRTR5V0U2X_SOT143-4 SATA_ITX_C_DRX_P5 6
<26> SATA_ITX_C_DRX_P5 SATA_ITX_C_DRX_N5 A+ ESATA
D AO3413_SOT23-3 7
1

<26> SATA_ITX_C_DRX_N5 A-
1 8 GND SHIELD 12
C2043 W=40mils C2044 2 1 0.01U_0402_25V7K SATA_IRX_DTX_N5 9 13
<26> SATA_DTX_C_IRX_N5 SATA_IRX_DTX_P5 B- SHIELD
+BT_VCC C2045 2 1 0.01U_0402_25V7K 10 14
<26> SATA_DTX_C_IRX_P5 B+ SHIELD
0.1U_0402_16V4Z 11 15
2 GND SHIELD
1 1
1

C2046 C2047 TYCO_1909574-1

R1728
4.7U_0805_10V4Z 300_0603_5% CONN@
2 2
D60
0.1U_0402_16V4Z
2

4 2 SATA_ITX_C_DRX_P5
+5VALW VIN IO1
1

D SATA_ITX_C_DRX_N5 3 1
Q120 IO2 GND
2
G 2N7002_SOT23 PRTR5V0U2X_SOT143-4
S
3

+BT_VCC +3V

JP18
80mil
+5VALW

1
1 9 +USB_VCCA R1730
1 GND U54 0_0402_5%
2
2 R1729
<27> USB20_P9 3 3 D61 1 GND OUT 8 1 2 USB_OC#2 <27>
4 2 7 100K_0402_5%
<27> USB20_N9 4 SATA_IRX_DTX_N5 IN OUT
R1754 0_0402_5% 5 +5VALW 4 2 3 6

2
5 VIN IO1 IN OUT
<33> WLAN_BT_DATA 1R1768 0_0402_5%
2 6 1 4 5 1 2 USB_OC#0 <27>
6 SATA_IRX_DTX_P5 C2048 EN# FLG R1731
<33> WLAN_BT_CLK 1 2 7 3 1
7 IO2 GND TPS2061DRG4_SO8 10K_0402_5%
8 8 GND 10 1
4 PRTR5V0U2X_SOT143-4 4.7U_0805_10V4Z C2049 4
@
ACES_87213-0800G 2
@
0.1U_0402_16V4Z
2
CONN@
<33,41> SYSON#

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NEW CARD & eSATA Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 34 of 52
A B C D E
 5 4 3 2 1

+3VALW For EC Tools

KSI[0..7]
KSI[0..7] <36>
L73
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 +EC_VCCA KSO[0..17] +3VALW
1 1 C2053 1 1 2
1
2 FBM-L11-160808-800LMT_0603
KSO[0..17] <36>
JP19 Place on RAM door
C2052 1 1
+3VALW C2050 C2054 C2055 C2056 1 E51RXD_P80CLK
2 2 E51RXD_P80CLK <33>
1000P_0402_50V7K 1000P_0402_50V7K C2051 3 E51TXD_P80DATA
2 2 2 2 1 1 3 E51TXD_P80DATA <33>
1 2 EC_PME#
2 9/21 add R for nvidia 4 4
R1732 10K_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

ECAGND
ACES_85205-0400
ENBKL 2 1
D R1733 10K_0402_5% @ D

111
125
22
33
96

67
9
U55

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
1 21 INVT_PWM
<26> EC_GA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM <22>
2 23 BEEP# PAD T41
<26> EC_KBRST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# <38>
<27> SERIRQ 3 SERIRQ# FANPWM1/GPIO12 26
<26> LPC_FRAME# 4 LFRAME# ACOFF/FANPWM2/GPIO13 27 ACOFF <46>
C2057 @ LPC_AD3 5 2 1 ECAGND 3S/4S# 1 2
<26> LPC_AD3 LAD3
22P_0402_50V8J LPC_AD2 7 PWM Output C2059 0.01U_0402_16V7K
@ R1734 4.7K_0402_5%
<26> LPC_AD2 LAD2
2 1 R1735 2 @ 1 33_0402_5% LPC_AD1 8 63 BATT_TEMP
<26> LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP <44>
LPC_AD0 BATT_OVP
<26> LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64 BATT_OVP <46>
ADP_I/AD2/GPIO3A 65 ADP_I <46>
12 AD Input 66 AD_BID0
<16> CLK_PCI_LPC PCICLK AD3/GPIO3B
13 75 PAD T48
@
<8,17,25,27,30,31> PLT_RST# PCIRST#/GPIO05 AD4/GPIO42 +3VALW
37 76 PAD T42
EC_SCI# ECRST# SELIO2#/AD5/GPIO43
<27> EC_SCI# 20 SCI#/GPIO0E
+3VALW 2 1 <27> PM_CLKRUN# 38 CLKRUN#/GPIO1D @
R1736 47K_0402_5% 68 DAC_BRIG ID_JAL90_JAW50# 2 1
DAC_BRIG/DA0/GPIO3C DAC_BRIG <22>
2 1 70 EN_DFAN1 R1737 100K_0402_5%
EN_DFAN1/DA1/GPIO3D EN_DFAN1 <40>
C2058 0.1U_0402_16V4Z DA Output 71 IREF 2 @ 1
IREF/DA2/GPIO3E IREF <46>
KSI0 55 72 R1738
+3VALW +3VALW KSI0/GPIO30 DA3/GPIO3F CALIBRATE# <46>
KSI1 56 100K_0402_5%
KSI2 KSI1/GPIO31
57 KSI2/GPIO32 @
+3VALW KSI3 58 83 EC_MUTE
KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE <39>
2

C KSI4 59 84 EC_I2C_INT2 C
KSI4/GPIO34 PSDAT1/GPIO4B EC_I2C_INT2 <37> +3VALW
R1841 R1840 KSI5 60 85
KSI5/GPIO35 PSCLK2/GPIO4C PGD_IN <49>
2

47K_0402_5% 47K_0402_5% KSI6 61 PS2 Interface 86 BT_LED# <36>

R1739 KSI7 KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK 65W/90W#
62 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E 87 TP_CLK <36> 2 1
10K_0402_5% KSO0 39 88 TP_DATA R1740 100K_0402_5%
TP_DATA <36>
1

KSO1 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F

40 KSO1/GPIO21
KSO2 41
1

KSO3 KSO2/GPIO22 3S/4S#

42 KSO3/GPIO23 SDICS#/GPXOA00 97 3S/4S# <46>
D45 KSO4 43 98 65W/90W#
KSO4/GPIO24 SDICLK/GPXOA01 65W/90W# <46>
EC_RCIRRX KSO5 SBPWR_EN
<37> RCIRRX 1 2
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
ID_JAL90_JAW50#
SBPWR_EN <41,47> Analog Board ID definition,
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109
CH751H-40PT_SOD323-2 KSO7 46 SPI Device Interface Please see page 3.
KSO8 KSO7/GPIO27
47 KSO8/GPIO28
KSO9 48 119 EC_SPIDI/FWR#
KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO <36> +3VALW
+5VS KSO10 49 120 EC_SPIDO/FRD#
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI <36>
KSO11 50 SPI Flash ROM 126 EC_SPICLK
KSO11/GPIO2B SPICLK/GPIO58 EC_SPICLK <36>
KSO12 51 128 EC_SPICS#/FSEL#
KSO12/GPIO2C SPICS# EC_SPICS#/FSEL# <36>

2
1 2 TP_CLK KSO13 52 KSO13/GPIO2D
R1741 4.7K_0402_5% KSO14 53 R1742
KSO14/GPIO2E
1 2 TP_DATA KSO15 54 KSO15/GPIO2F CIR_RX/GPIO40 73 EC_RCIRRX PAD T51 Ra 100K_0402_5%
R1743 4.7K_0402_5% KSO16 81 74
KSO17 KSO16/GPIO48 CIR_RLC_TX/GPIO41 FSTCHG
82 89 FSTCHG <46>

1
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 BATT_GRN_LED# AD_BID0
BATT_CHGI_LED#/GPIO52 90 BATT_GRN_LED# <36>
91 CAPS_LED# @ <42>
CAPS_LED#/GPIO53 CAPS_LED#

1
EC_SMB_CK1 77 GPIO 92 BATT_AMB_LED# R1744 1
<36,44> EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_AMB_LED# <36>
EC_SMB_DA1 78 93 PWR_LED C2060
<36,44> EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_LED <42>
+3VALW <4,18,36> EC_SMB_CK2
EC_SMB_CK2 79 SCL2/GPIO46 SM Bus SYSON/GPIO56 95 SYSON
SYSON <34,41,47> Rb 8.2K_0402_5%
EC_SMB_DA2 80 121 VR_ON
<4,18,36> EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <37,49> 2
127 ACIN 0.1U_0402_16V4Z
ACIN <27,41,42,43,46>

2
B AC_IN/GPIO59 B
1 2 EC_SMB_CK1
R1745 4.7K_0402_5%
1 2 EC_SMB_DA1 <27> PM_SLP_S3#
PM_SLP_S3# 6 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 100 EC_RSMRST# <27>
R1746 4.7K_0402_5% PM_SLP_S5# 14 101 EC_LID_OUT#
<27> PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# <27>
EC_SMI# 15 102 EC_ON
<27> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <37>
2 1 EC_I2C_INT2 <36> LID_SW#
LID_SW# 16 LID_SW#/GPIO0A EC_SWI#/GPXO06 103 EC_SWI# <27>
R1769 @ 10K_0402_5% EC_GPIOB 17 104 EC_PWROK EC_CRY1 EC_CRY2
SUSP#/GPIO0B ICH_PWROK/GPXO06 EC_PWROK <27,37>
EC_GPIOC 18 GPO 105 BKOFF#
PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# <22>
1 2 LID_SW# <31> EC_PME#
EC_PME# 19 EC_PME#/GPIO0D GPIO WL_OFF#/GPXO09 106 WL_OFF#
WL_OFF# <33> 1 1
R1747 100K_0402_5% 25 107 C2061 C2062
<8> MCH_TSATN_EC# EC_THERM#/GPIO11 GPXO10

4
FAN_SPEED1 28 108 PAD T49 @
<40> FAN_SPEED1 BT_ON# FAN_SPEED1/FANFB1/GPIO14 GPXO11 PAD T50 @ 15P_0402_50V8J 15P_0402_50V8J
29

IN

OUT
<34> BT_ON# FANFB2/GPIO15 2 2
E51TXD_P80DATA 30
E51RXD_P80CLK EC_TX/GPIO16
31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 PM_SLP_S4# <27>
ON/OFF 32 112 ENBKL
+3VS <37> ON/OFF ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL <10,18>
PWR_SUSP_LED EAPD

NC

NC
<42> PWR_SUSP_LED 34 PWR_LED#/GPIO19 GPXID3 114 EAPD <38>
NUM_LED# 36 GPI 115
<36,42> NUM_LED# NUMLED#/GPIO1A GPXID4 EC_THERM# <27>
116 SUSP#
SUSP# <34,37,41,50>

3
GPXID5
1 2 EC_SMB_CK2 GPXID6 117 PBTN_OUT#
PBTN_OUT# <27>
R1748 2.2K_0402_5% 118 MC_RST#
GPXID7 MC_RST# <36>
1 2 EC_SMB_DA2 EC_CRY1 122 XCLK1
X2
R1749 2.2K_0402_5% EC_CRY2 123 124 32.768KHZ_12.5P_MC-306
XCLK0 V18R
1
AGND

For KB926 C0 reversion

GND
GND
GND
GND
GND

C2063
+3VS 1U_0402_6.3V6K C2064 100P_0402_50V8J
KB926QFC0_LQFP128_14X14 2 BATT_TEMP 2 1
11
24
35
94
113

69

20mil C2065 100P_0402_50V8J

A 1 2 @ L74 BATT_OVP 2 1 A
R1750 4.7K_0402_5% ECAGND 2 1 C2066 100P_0402_50V8J
1 2 @ FBM-L11-160808-800LMT_0603 ACIN 2 1
R1751 4.7K_0402_5%
<36> EC_ESB_CK 1 2 @ EC_GPIOB
R1752 0_0402_5%
1 2 @ EC_GPIOC
<36> EC_ESB_DA
R1753 0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE KB926
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 35 of 52
5 4 3 2 1
 U56
To TP/B Conn.
EC_SPICS#/FSEL# +SPI_VCC JP21
+3VALW 1 2 C2067 1 2 0.1U_0402_16V4Z 1 8
R1757 0_0603_5% SPI_WP# CS# VCC EC_SPICLK_R
3 6 +5VS 6 8
SPI_HOLD# WP# SCLK EC_SO_SPI_SI TP_CLK 6 8
7 5 <35> TP_CLK 5 7
+SPI_VCC HOLD# SI EC_SI_SPI_SO TP_DATA 5 7
4 GND SO 2 <35> TP_DATA 4 4
LEFT_BTN# 3
U57 MX25L512AMC-12G_SO8 RIGHT_BTN# 3
2 2
EC_SPICS#/FSEL# 1 8 1
<35> EC_SPICS#/FSEL# CE# VDD 1
R1758 1 2 4.7K_0402_5% SPI_WP# 3 WP# SCK 6 EC_SPICLK_R R1759 1 2 0_0402_5% EC_SPICLK <35> Reserved
@ for BIOS simulator. 1 1
+3VALW R1760 1 2 4.7K_0402_5% SPI_HOLD# 7 HOLD# SI 5 R1761 1 2 0_0402_5% EC_SO_SPI_SI <35> Footprint SO8 SW4 C2068
R1762 1 ACES_85201-0605
4 VSS SO 2 2 0_0402_5% EC_SI_SPI_SO <35>
SMT1-05-A_4P C2069
LEFT_BTN# 3 1 100P_0402_50V8J 100P_0402_50V8J
MX25L8005M2C-15G_SOP8 2 2
CONN@
4 2

5
6
TP_CLK

SW5 +5VS TP_DATA

+5VS +3VS MCVCC SMT1-05-A_4P
ENE suggestion SPI Frequency over 66MHz

3
RIGHT_BTN#3 1
SST: 50MHz C2070
MXIC: 70MHz 4 2 D46

1
0.1U_0402_16V4Z

1
ST: 40MHz

0_0603_5%

0_0603_5%
R106

R109
PSOT24C_SOT23

5
6
R105

1
To Media/B Conn. 0_0603_5%

KALH0@ 2

KAL90@ 2
KSI[0..7] @
INT_KBD Conn.

2
KSI[0..7] <35>
SW1 SW2
KSO[0..17] 1 KALH0@2 SMT1-05-A_4P SMT1-05-A_4P
KSO[0..17] <35> <4,18,35> EC_SMB_CK2 LEFT_BTN# 3 RIGHT_BTN#3
R1846 0_0402_5% 1 1
JP23 1 KALH0@2
<4,18,35> EC_SMB_DA2
R1847 0_0402_5% 4 2 4 2
(Left) KSO0 1 1@ 2
KSO1 1 <35> EC_ESB_CK
2 R1763 0_0402_5% kal90@ kal90@

5
6

5
6
KSO2 2
3 <35> EC_ESB_DA 1 @ 2
KSO3 3 R1764 0_0402_5%
4
KSO4 4 JP22
5 5
KSO5 6 1 KAL90@ 2 1
KSO6 6 <35,44> EC_SMB_CK1 1
7 R1765 0_0402_5% 2
KSO7 7 MEDIA_CK 2
8 <35,44> EC_SMB_DA1 1 KAL90@ 2 3
KSO8 8 R1766 0_0402_5% 3
9 9 <37> EC_I2C_INT1 4 4
KSO9 MEDIA_DA
KSO10
KSO11
10
11
10
11 <35> MC_RST#
MC_RST# 1 2
5
6
5
6
e-key/B JP28
12 @ R1790 7
12 7

2
KSO12 13 0_0402_5% 8 JP25 1
13 8 1 +5VS
KSO13 14 C2093 @ R1808 9 KSO0 1 2
14 +3VALW GND 1 2
KSO14 15 0.1U_0402_16V4Z 10K_0402_5% 10 KSI5 2 3 +3VS
KSO15 15 GND 2 3 MINI1_LED#
16 3 4 MINI1_LED# <33>
KSO16 16 ACES_85201-08051 3 4 FB_KSI4
17 4 5

1
KSO17 17 4 5 BT_LED#
18 6 BT_LED# <35>
KSI0 18 6 FB_KSI3
19 19 CONN@ E&T_6905-E04N-00R 7 7
KSI1 20 8
KSI2 20 8
21 21 GND 9
KSI3 22 CONN@ 10
KSI4 22 GND
23
KSI5 23 CONN@
24
KSI6 24 ACES_85201-08051
25 27
KSI7 25 G1
26 28
26 G2
(Right)
ACES_85201-26051
To BTN/B Conn.
KSO16 C2071 1 2 100P_0402_50V8J @
CONN@ 1 2 KSI4 KSO0
KSO17 C2072 1 2 100P_0402_50V8J FB_KSI4 R1834 0_0402_5%
NUM_LED# <35,42> KSI1 WL_BTN# JP26
1 2 1 +5VS
KSO15 C2073 1 100P_0402_50V8J KSO7 C2074 1 100P_0402_50V8J R1835 0_0402_5% 1
2 2 KSI2 BT_BTN# 2 2
MINI1_LED#
+3VS
3 MINI1_LED# <33>
KSO14 C2075 1 100P_0402_50V8J KSO6 C2076 1 100P_0402_50V8J @ 3 KSI1
2 2
KSI3
KSI3 EMAIL_BTN# 4 4
FB_KSI4
1 2 5
KSO13 C2077 1 100P_0402_50V8J KSO5 C2079 1 100P_0402_50V8J FB_KSI3 R1832 0_0402_5% 5 KSO0
2 2 KSI4 IE_BTN# 6
6
KSI2
1 2 MEDIA_LED# <42> 7
KSO12 C2080 1 100P_0402_50V8J KSO4 C2078 1 100P_0402_50V8J R1833 0_0402_5% 7 BT_LED#
2 2 KSI5 E-KEY_BTN# 8 8
FB_KSI3 BT_LED# <35>
9
9
10
KSI0 C2081 1 100P_0402_50V8J KSO3 C2082 1 100P_0402_50V8J 10
2 2 GND 11
12
KSO11 C2083 1 100P_0402_50V8J KSI4 C2084 1 100P_0402_50V8J GND
2 2
ACES_85201-1005N
KSO10 C2085 1 2 100P_0402_50V8J KSO2 C2086 1 2 100P_0402_50V8J

KSI1 C2087 1 2 100P_0402_50V8J KSO1 C2088 1 2 100P_0402_50V8J

Lid Switch CONN@

(Hall Effect Switch) FOR EMI

KSI2 C2089 1 2 100P_0402_50V8J KSO0 C2090 1 2 100P_0402_50V8J
+3VALW
KSO9 C2091 1 2 100P_0402_50V8J KSI5 C2092 1 2 100P_0402_50V8J
KSI5 C2101 1 2 100P_0402_50V8J
KSI3 C2094 1 2 100P_0402_50V8J KSI6 C2095 1 2 100P_0402_50V8J +3VS
R1770 @
KSO8 C2097 1 2 100P_0402_50V8J KSI7 C2098 1 2 100P_0402_50V8J 10K_0402_5%
1

2 1 2 MINI1_LED# C2099 1 2 100P_0402_50V8J

2

C2103 R1771
47K_0402_5% BT_LED# C2100 1 @ 2 100P_0402_50V8J
VDD

0.1U_0402_16V4Z
1
@ @
2

3 1 2 LID_SW# LID_SW# <35>

LED1 OUTPUT D48 RB751V_SOD323 KSO0 C2104 1 100P_0402_50V8J
2
Compal Footprint+5VALW
GND

1 R1772 2 2 1 PWR_LED# 1 KSI1 C2106 1 @ 2 100P_0402_50V8J

B PWR_LED# <42>
200_0402_1% C2111
4 2 U58 KSI2 C2108 1 @ 2 100P_0402_50V8J
1

+5VALW 1 R1773 2 4 A 3PWR_SUSP_LED# PWR_SUSP_LED# <42> A3212ELHLT-T_SOT23W-3 10P_0402_50V8J

@ 2 KSI3 C2110 1 @ 2 100P_0402_50V8J
3 1 330_0402_5%
HT-297UD/CB _BLUE/AMB_0603 KSI4 C2113 1 @ 2 100P_0402_50V8J
footpint not right @
LED2
R1774
1 2 2 1 BATT_GRN_LED#
+5VALW
180_0402_5%
YG BATT_GRN_LED# <35> Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title
1 R1775 2 4 3 BATT_AMB_LED#
+5VALW A BATT_AMB_LED# <35>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS, I/O Port & K/B Connector
360_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
HT-297DQ-GQ_AMB-YG B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Tuesday, January 06, 2009 Sheet 36 of 52
 A B C D E

Power Button
ON/OFF switch
HDA MDC Conn.
+3V
+3VALW
TOP Side
1
1 2 15mil 1 2 +3V C2114
R1777 10K_0603_5% JMDC1 R1776 0_0402_5%

2
1 +MDC_VCC 1U_0603_10V4Z 1
@ 1 1 2 2 1 2 +1.5V
1 2 R1780 3 4 R1778 0_0402_5% @ 2
<26> HDA_SDOUT_MDC 3 4
R1779 10K_0603_5% 5 6
5 6 +3V
@ 100K_0402_5% <26> HDA_SYNC_MDC 7 8
HDA_SDIN1_MDC 7 8
Bottom Side <26> HDA_SDIN1 1 2 9 10

1
D49 R1781 33_0402_5% 9 10
<26> HDA_RST_MDC# 11 11 12 12 HDA_BITCLK_MDC <26>
2 ON/OFF <35>

1
ON/OFFBTN# 1 ACES_88018-124N
<42> ON/OFFBTN# 51ON#
3 R1782
51ON# <43>
CONN@ 0_0402_5%
DAN202UT106_SC70-3 51ON#

2
1
C2115
MCVCC

1
2 22P_0402_50V8J

1
C2116 D50 2
R1836 kal90@
1000P_0402_50V7K RLZ20A_LL34 510K_0402_5%
1
For EMI

2
D

1
MCVCC +3VS

2
2 Q124 kal90@

10K_0402_5%
R1845 KALH0@
G
R1838 kal90@ S 2N7002_SOT23

3
1
D
EC_ON 2 Q122 10K_0402_5%
<35> EC_ON
G

1
2

1
D
S 2N7002_SOT23
3

R1783 2 Q138 kal90@

<36> EC_I2C_INT1
G
10K_0402_5% S 2N7002_SOT23

3
1

2 2

+3VALW

2
R1837 10K_0402_5%
@
D47
@
Power ON Circuit

1
1 2 EC_I2C_INT2 <35>

1SS355_SOD323-2
+3VS

+3VALW +3VALW R42 1 2 0_0402_5%

1

U59A U59B
R1784 @ SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
14

14

180K_0402_5%
D51 @
P

P
2

1 2 1 2 3 4 SYS_PWROK 1 2
<35,49> VR_ON I O I O EC_PWROK <27,35>
R1785 @ 0_0402_5%
G

CH751H-40PT_SOD323-2 2
For South Bridge
7

C2117
1U_0603_10V6K
@ 1

3 3

+3VS

+3VALW +3VALW
+RTCBATT
1

R1786 @
10K_0402_1% U59C U59D
14

14

R1787 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14

CIR

2
10K_0402_1%
P

P
2

1 2 5 6 9 8 +3VALW R1788
<34,35,41,50> SUSP# I O I O VS_ON <47,48>
2 1K_0402_5%
G

G
1

D
For +VCCP/+1.05VS

1
SUSP 2 C2118
7

1 1
<41,48> SUSP
G 0.1U_0402_16V7K R1789
Q123 S 1 100_0805_5% D52
3

2N7002_SOT23 KAL90@

2
IR1 KAL90@
3 4 RCIRRX +RTCVCC
Vs OUT RCIRRX <35>
1 2

2
GND GND
1
C2119 TSOP36236TR_4P 1 BAS40-04_SOT23-3
C2121 KAL90@
+CHGRTC
4.7U_0805_10V4Z 1
KAL90@ 2 1000P_0402_50V7K C2122
2
0.1U_0402_16V4Z
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power OK, Reset,RTC, CIR, MDC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 37 of 52
A B C D E
 A B C D E F G H

+VDDA

+5VAMP
60mil U40 (output = 300 mA)

1
R1528 L45 1 2 1
10K_0402_5%
+5VS
KC FBM-L11-201209-221LMAT_0805 IN
OUT
5 40mil +VDDA
1 1 2
GND
L46 1 2 C1831 C1832 1 4.75V

2
KC FBM-L11-201209-221LMAT_0805 3 4 C1834
10U_0805_10V4Z SHDN BYP
1 2
2 2
0.1U_0402_16V4Z G9191-475T1U_SOT23-5 4.7U_0805_10V4Z
1

1
C1833 1U_0402_6.3V6K C1835 2
R1529
10K_0402_5%
1 2 1

2
C1836 0.01U_0402_16V7K
1 2 MONO_IN BOM Option
1U_0402_6.3V6K
ALC268 268@

1
C1837 C 1 2
1 2 1
R1530
2 2 Q103 R1531 1.3K_0402_1%
ALC888S-VB 888VB@
<35> BEEP# B
1U_0402_6.3V6K 560_0402_5% E 2SC2411K_SOT23
ALC888S-VC 888VC@

3
C1838
R1532 L47
1 2 1 2
<27> SB_SPKR MBK1608121YZF_0603
10mil
ANALOG MIC

1
1U_0402_6.3V6K 560_0402_5% +3VS_DVDD 1 2

R1533
D29
CH751H-40PT_SOD323-2
HD Audio Codec 1 1
+3VS

1
10K_0402_5% C1839 C1840
R1534 JP24

2
0.1U_0402_16V4Z 0_0603_5% DMIC_DATA_R 1
2 2 DMIC_CLK_R 1
2
10U_0805_10V4Z 2

2
L48 3
+AVDD_HDA MBK1608121YZF_0603 G1
10mil +1.5VS_DVDD 1 2
4 G2
+1.5VS
@ ACES_88266-02001
L49 1 2 0.1U_0402_16V4Z
40mil CONN@
+VDDA 1 1
FBM-L11-160808-800LMT_0603 1 1 C1843 C1844
C1842
C1841 0.1U_0402_16V4Z 10U_0805_10V4Z
2 10U_0805_10V4Z 2 2 2

25

38

9
2 2 U41

DVDD_IO
AVDD1

AVDD2

DVDD
MIC2_VREFO

14 35 AMP_LEFT
LINE2-L FRONT_L AMP_LEFT <39>

1
15 36 AMP_RIGHT R1535
LINE2-R FRONT_R AMP_RIGHT <39>
2.2K_0402_5%
R49 1K_0402_5% 1 2 MIC2_C_L 16 39 HP_LEFT 15mil KALH0@
MIC2_L SURR_L HP_LEFT <39>
DMIC_CLK_R 2 1 INT_MIC_R C1845 KALH0@ 4.7U_0603_6.3V6M

2
KLH0@ 1 2 MIC2_C_R 17 41 HP_RIGHT DMIC_CLK_R
MIC2_R SURR_R HP_RIGHT <39>
C1846 KALH0@ 4.7U_0603_6.3V6M
LINE_L 1 2 LINE_C_L 23 45 @ DMIC_DATA_R 1
<39> LINE_L LINE1_L SIDE_L PAD T38
C1847 4.7U_0603_6.3V6M R1537 KALH0@ 0_0603_5%
LINE_R 1 2 LINE_C_R 24 46 DMIC_CLK_268 1 2 DMIC_CLK C1849
<39> LINE_R LINE1_R SIDE_R
C1848 4.7U_0603_6.3V6M For EMI R1538 @ 0_0402_5% 220P_0402_50V7K
18 43 2 KALH0@
CD_L CENTER
20 44 1 2 1 2 C1850
CD_R LFE R1539 0_0402_5% 22P_0402_50V8J
19
CD_GND
6 HDA_BITCLK_AUDIO <26>
MIC1_L MIC1_C_L BITCLK
<39> MIC1_L 1 2 21
C1851 4.7U_0603_6.3V6M MIC1_L

<39> MIC1_R
MIC1_R 1
C1852
2 MIC1_C_R
4.7U_0603_6.3V6M
22 MIC1_R SDATA_IN 8 HDA_SDIN0_AUDIO 1
R1540
2
33_0402_5%
HDA_SDIN0 <26> Digital MIC
MONO_IN 12 37 +3VS
PCBEEP PIN37_VREFO
29 JP13
LINE1_VREFO
<26> HDA_RST_AUDIO# 11 1
3 RESET# DMIC_CLK R1541 KAL90@ 0_0603_5% DMIC_CLK_R 1 3
LINE2_VREFO 31 2 2
10 10mil DMIC_DATA DMIC_DATA_R 3 5
<26> HDA_SYNC_AUDIO SYNC 3 G1
28 MIC1_VREFO_L R1542 KAL90@ 0_0603_5% 4 6
MIC1_VREFO_L 4 G2
<26> HDA_SDOUT_AUDIO 5 SDATA_OUT
Place close to Codec 32 MIC1_VREFO_R ACES_88266-04001
HDA_GPIO0 MIC1_VREFO_R CONN@
2
SPDIFO2

2
HDA_GPIO3 3 30
GPIO0/DMIC_CLK MIC2_VREFO MIC2_VREFO
R1543 1 2 10K_0402_1% SENSE_A 13 10mil D30 1 2
<39> LINEIN_PLUG# SENSE A CODEC_VREF
R1544 2 1 20K_0402_1% 34 27 SM05T1G_SOT23-3
<39> MIC_PLUG# SENSE B VREF
1 1 C1854
R1545 2 1 39.2K_0402_1% 47 40 C1855 220P_0402_50V8J
<39> HP_PLUG# <35> EAPD SPDIFI/EAPD JDREF 2 1
C1856 For ESD 10/11 @

1
1
1 2 SPDIF_R 48 SPDIFO SENSE C 33 0.1U_0402_16V4Z 10U_0805_10V4Z C1853
<39> SPDIF 100P_0402_50V8J 1 2 2
2 C1857 R1546 0_0402_5% R1547 220P_0402_50V8J
DMIC_DATA 1 2 4 26 20K_0402_1%
R1548 GPIO1/DMIC_DATA AVSS1
1 KAL90@ 2 0_0402_5% 7 42
R1549 888VB@ 0_0402_5% DVSS AVSS2

2
ALC888S-VC_LQFP48_7x7
Sense Pin Impedance Codec Signals 1 2 888VC@
1
R1550
2
0_0805_5%
1
R1551
2
0_0805_5%
R1552 KALH0@ 0_0402_5%
39.2K PORT-A (PIN 39, 41) DGND AGND
1 2 1 2
R1553 0_0805_5% R1554 0_0805_5%
20K PORT-B (PIN 21, 22)
SENSE A
1 2 1 2
10K PORT-C (PIN 23, 24) DMIC_DATA 1 2 HDA_GPIO0 R1555 0_0805_5% R1556 0_0805_5%
R1557 @ 0_0402_5%
SPDIF_HDMI 1 2
<18> SPDIF_HDMI
5.1K PORT-D (PIN 35, 36) R1558 888VC@ 0_0402_5%

DMIC_DATA 1888VB@ 2 HDA_GPIO3 GND GNDA GND GNDA

4 R1559 0_0402_5% 4
39.2K PORT-E (PIN 14, 15) DMIC_CLK 1 2
R1560 KAL90@ FBMA-L10-160808-301LMT_0603
20K PORT-F (PIN 16, 17)
SENSE B
10K PORT-G (PIN 43, 44)
Security Classification Compal Secret Data Compal Electronics, Inc.
5.1K PORT-H (PIN 45, 46) Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec ALC888S-VC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Wednesday, December 10, 2008 Sheet 38 of 52
A B C D E F G H
 A B C D E

+5VAMP Int. Speaker Conn.

W=40mil 20mil JP14
+3VS
1 1 SPKL+ R1561 1 2 0_0603_5% SPK_L+ 1
SPKL- R1562 1 0_0603_5% SPK_L- 1
1 2 2
C1859 C1860 SPKR+ R1563 1 0_0603_5% SPK_R+ 2
2 3 5
C1858 0.1U_0402_16V4Z SPKR- R1564 1 0_0603_5% SPK_R- 3 G1
2 4 6
C1861 0.1U_0402_16V4Z 2 2 4 G2
0.47U_0603_16V4Z 2 4.7U_0805_10V4Z 1 C1865 ACES_88266-04001

2
1 2 AMP_RIGHT_C-1 1 2 AMP_RIGHT_C 220P_0402_50V8K
<38> AMP_RIGHT C1862 1U_0402_6.3V6K D31

11

19

20
10
CONN@

1
1 2 AMP_LEFT_C-1 1 2 AMP_LEFT_C U42 D32 SM05T1G_SOT23-3 1
<38> AMP_LEFT C1863 C1864 1U_0402_6.3V6K SM05T1G_SOT23-3 2 C1866

CVDD

HVDD

PVDD
PVDD

VDD
1

1
0.47U_0603_16V4Z 220P_0402_50V8K
R1566 R1565 1

1
1 2 C1867 1
2.2K_0402_5% 2.2K_0402_5% 3 22 SPKR+ 1
INR_A ROUT+ SPKR- @ @ 220P_0402_50V8K
5 21

2
INL_A ROUT- 2
HPF Fc = 154Hz For ESD 10/11 C1868
R1567 1 2 100K_0402_5% 27 8 SPKL+ 220P_0402_50V8K
/AMP EN LOUT+ SPKL- 2
LOUT- 9
+5VAMP R1568 1 2 100K_0402_5% 24
HP EN HPOUT_R
HP_R 17
+5VAMP HP_RIGHT 1 2 HP_RIGHT_C 1 2 HP_RIGHT_R 4 18 HPOUT_L +5VAMP
<38> HP_RIGHT C1869 4.7U_0603_6.3V6M R1569 39K_0402_5% HP_LEFT_R INR_H HP_L
6
HP_LEFT HP_LEFT_C INL_H +5VAMP
<38> HP_LEFT 1 2 1 2
1

C1870 4.7U_0603_6.3V6M R1570 39K_0402_5% VOL_AMP 26 HP_PLUG#

/SD HP_PLUG# <38>

2
R1571 15
CVSS

3
43K_0402_1% 28 R1572
BEEP
16 100K_0402_5%
VSS

2
1 12 1 Q44B
2

CP+ C1872 R1573 2N7002DW-T/R7_SOT363-6

14 2 5

6 1
VOL_AMP C1871 CP- GND Q105
23 1U_0603_10V4Z 100K_0402_5%
PGND AO3413_SOT23-3
1U_0603_10V4Z 25 7

4
BIAS PGND
1

D 2 2
13

1
CGND S
1

3
1 2 EC_MUTE 1 29 Q44A
R1574 G EC_MUTE <35> GND G
SPDIF_PLUG# 2N7002DW-T/R7_SOT363-6
2 2
100K_0402_1% C1873 S Q104 C1874 APA2057A_TSSOP28
S/PDIF Out JACK
3

2N7002_SOT23 2.2U_0603_10V6K D

1
3

2
2
0.01U_0402_16V7K 2
LINE Out/Headphone Out
2

+5VSPDIF D33
PJDLC05_SOT23-3

1
20mil
Gain= 10dB 2 2 D63
C1875 C1876 PJDLC05_SOT23-3
2 @ 2
For ESD Protect

1
330P_0402_50V7K 330P_0402_50V7K
R1575 1 1 JHP1
56.2_0603_1% 1

3
HPOUT_L 1 2 HPOUT_L_1 1 2 HPOUT_L_2 2
L51 FBM-11-160808-700T_0603 6
HPOUT_R 1 2 HPOUT_R_1 1 2 HPOUT_R_2 3
L50 FBM-11-160808-700T_0603
R1576 SPDIF_PLUG# 5
56.2_0603_1%
4
SPDIF 7
<38> SPDIF
+5VSPDIF 8
1 10
C1877
100P_0402_50V8J 9
2 SINGA_2SJ-E373-T01

CONN@
<38> LINEIN_PLUG#
LINE-IN JACK

1
JLINE1
8
7
D64
PJDLC05_SOT23-3
KAL90@ LINEIN_PLUG# 5

R1577 KAL90@ L52 KAL90@ 4

3 75_0603_1% FBM-11-160808-700T_0603 3

3
1 2 LINE_R_1 1 2 LINE_R_R 3
<38> LINE_R
6
1 2 LINE_L_1 1 2 LINE_L_R 2
<38> LINE_L
L53 1
R1578 FBM-11-160808-700T_06031 1
75_0603_1% KAL90@ SINGA_2SJ-E351-S03
KAL90@ C1878 C1879
220P_0402_50V7K 220P_0402_50V7K
2 2 KAL90@ CONN@(HDA Jack)
For ESD
I/O status:
a. input/output mount 75 ohm <38> MIC_PLUG#
MIC JACK
b. input only mount 1K ohm
JMIC1
MIC1_VREFO_L MIC1_VREFO_R 8
7

1
R1579 R1580 5
2.2K_0402_5% 2.2K_0402_5%
R1581 L54 4
75_0603_1% FBM-11-160808-700T_0603

2
1 2 MIC1_R_1 1 2 MIC1_R_R 3
<38> MIC1_R
6
1 2 MIC1_L_1 1 2 MIC1_L_R 2
<38> MIC1_L
L55 1

2
R1582 FBM-11-160808-700T_0603
1 1
75_0603_1% SINGA_2SJ-E351-S01
C1880 C1881
220P_0402_50V7K D65 CONN@
4 2 2 4
PJDLC05_SOT23-3 (HDA Jack)
220P_0402_50V7K

1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Amplifier & Audio Jack
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Tuesday, January 06, 2009 Sheet 39 of 52

A B C D E
 FAN1 Conn
+5VS
C2124 10U_0805_10V4Z +5VS
1 2

1
U60 D53
1 8 1SS355_SOD323-2 H1 H3 H4 H5 H6 H7 H8
VEN GND H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2
2 VIN GND 7
+VCC_FAN1 3 6

2
VO GND
<35> EN_DFAN1 2 R41 1 4 5 D54
300_0402_5% VSET GND
1 2

1
1 APL5605KI-TRL SOP 8P
C60 BAS16_SOT23-3
C2125
0.1U_0402_16V4Z 10U_0805_10V4Z @ @ @ @ @ @ @
2 1 2 H9 H10 H11 H12
H_4P2 H_4P2 H_4P2 H_4P2 H13
+3VS C2126 H_3P7N
1000P_0402_50V7K
1 2

1
1

1
R1791
10K_0402_5%
@ @ @ @
40mil @ H22
JP27 H17 H18 H19 H20 H21 H23 H_7P0 H25 H26
2

+VCC_FAN1 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2 H_3P2
1
<35> FAN_SPEED1 2
3
1

1
C2127 ACES_85205-03001
1000P_0402_50V7K
2 CONN@ @ @ @ @ @ @ @ @ @ @

H29 H30 H33 H34

H_4P7X3P7N H_5P1X4P1N H_10P0X6P0N H_5P5X4P3N

1
@ FD1 @ FD2 @ @ FD3 FD4

1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80

@ @ @ @

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN & COVER LIGHT& Screw Hole
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 40 of 52
 A B C D E

+5VALW TO +5VS +3VALW TO +3V_SB(ICH8M AUX Power) +5VALW

+5VALW +5VS +3VALW +3V

2
4

4
U61 U62 R1792
5 5 100K_0402_5%
6 3 6 3

2
7 2 1 1 7 2 1 1

1
1 1 8 1 C2132 C2133 R1793 1 8 1 C2135 C2136 R1794
C2130 C2131 470_0603_5% C2134 470_0603_5% SYSON#
<33,34> SYSON#
10U_0805_10V4Z 10U_0805_10V4Z

6
10U_0805_10V4Z SI4800BDY-T1-E3_SO8 2 2
1U_0603_10V4Z SI4800BDY-T1-E3_SO8 2 2
1U_0603_10V4Z

3 1
1 2 2
10U_0805_10V4Z 2
10U_0805_10V4Z 1
Q31A

3
SYSON 2
<34,35,47> SYSON
Q39B 2N7002DW-T/R7_SOT363-6

1
Q30B 2N7002DW-T/R7_SOT363-6 5 SBPWR_EN#

1
+VSB 2 1 5VS_GATE 2N7002DW-T/R7_SOT363-6 5 SUSP +VSB 2 1 3V_GATE R1797
R1795 R1796 100K_0402_5%

4
6
200K_0402_5% 1 200K_0402_5% 1

4
6

C2137 C2138

2
Q39A
Q30A 0.1U_0603_25V7K SBPWR_EN# 2 0.1U_0603_25V7K
SUSP 2 2
2N7002DW-T/R7_SOT363-6 2 +5VALW
2N7002DW-T/R7_SOT363-6

1
1

2
R1798
100K_0402_5%

1
+3VS +5VS SUSP
+3VALW TO +3VS <37,48> SUSP

3
+3VALW +3VS
4

1
U63 Q31B
5 R1403 R1404 5
<34,35,37,50> SUSP#
6 3 4.7K_0402_5% 4.7K_0402_5% 2N7002DW-T/R7_SOT363-6

2
7 2 1 1

4
1
1 1 8 1 C2139 C2140 R1799

2
C2141 C2142 470_0603_5% R1800
10U_0805_10V4Z 10K_0402_5%
10U_0805_10V4Z SI4800BDY-T1-E3_SO8 2 2
1U_0603_10V4Z @ @
2 2 2
10U_0805_10V4Z 1 1 VGA_SUSP 2 1 2

2
D R1405 0_0402_5%

1
D
2 SUSP @
G 2
S Q125 G
3

5VS_GATE 2N7002_SOT23 S Q128

3
VGA_SUSP 2 1 SUSP @ 2N7002_SOT23
R1402 0_0402_5%
+5VALW
<50> NVVDD_PWRGD

2
+1.8V to +1.8VS +1.5V to +1.5VS R1801
100K_0402_5%
+1.8V +1.8VS +1.5V +1.5VS

1
4
U64 U65
8 1 5
D S SBPWR_EN#
7 2 1 1 6 3 1 1 <28> SBPWR_EN#
D S
2

2
6 3 C2143 C2144 7 2 C2145 C2146
D S R1802 R1803
1 1 5 4 1 1 8 1
C2147 C2148 D G 10U_0805_10V4Z 470_0603_5% C2149 C2150 10U_0805_10V4Z 470_0603_5%

1
SI4856ADY_SO8 2 2
1U_0603_10V4Z 2 2
1U_0603_10V4Z D
10U_0805_10V4Z 10U_0805_10V4Z SI4800BDY-T1-E3_SO8 <35,47> SBPWR_EN 2
1

1
2 2
10U_0805_10V4Z PM@ 2 2
10U_0805_10V4Z G
PM@
PM@ Q126
SI4856/AO4430 S

3
3

1
PM@ PM@ 2N7002_SOT23
PM@ R1804
R1805 Q14B Q19B 100K_0402_5%
1 2 1.8VS_GATE 2N7002DW-T/R7_SOT363-6 5 VGA_SUSP 2 1 1.5VS_GATE 2N7002DW-T/R7_SOT363-6 5 SUSP
+VSB +VSB
R1806

2
910K_0402_5%~D 1 510K_0402_5% 1
4

4
3 C2151 C2152 3
6

6
PM@
0.1U_0603_25V7K PM@ 0.1U_0603_25V7K
Q14A 2 Q19A 2
VGA_SUSP 2 2N7002DW-T/R7_SOT363-6 SUSP 2 2N7002DW-T/R7_SOT363-6
PM@

2
1

1
2

R1825
R1824 2.2M_0402_1%
2.2M_0402_1% @
PM@ 1
1 1

D D
2N7002_SOT23 2N7002_SOT23
<27,35,42,43,46> ACIN 2 <27,35,42,43,46> ACIN 2
G Q136 G Q137
S PM@ S @
3

+1.5VS +1.05VS +0.9VS +1.8V +1.5V

2

R1807 R1809 R1810 R1811 R1812

470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5%
4 4
1

1
1

D D D
@ D D
@
2 SUSP 2 SUSP 2 SUSP 2 SYSON# 2 SYSON#
G G G G G
S Q127 S Q129 S Q130 S Q131 S Q132
3

2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title
@ @
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Wednesday, December 24, 2008 Sheet 41 of 52
A B C D E
 5 4 3 2 1

Enlightener LED
+5VALW +5VALW ON/OFF LED LEFT ON/OFF LED RIGHT
(BLUE) (BLUE)

2
(BLUE) (BLUE)
R1813 R1826
300_0402_5% 300_0402_5% LED3 LED4
R1814 R1815
D KAL90@ KAL90@ +5VALW 1 2 2 1 PWR_LED# +5VALW 1 2 2 1 PWR_LED# PWR_LED# <36> D
1

1
B B
KAL90@ 220_0402_5% KAL90@ 220_0402_5%
R1816 R1817
+5VALW 1 2 4 A 3 PWR_SUSP_LED# +5VALW 1 2 4 A 3 PWR_SUSP_LED# PWR_SUSP_LED# <36>
KAL90@ 453_0402_1% KAL90@ 453_0402_1%
2

2
LED5 LED10 HT-297UD/CB _BLUE/AMB_0603 (AMB) HT-297UD/CB _BLUE/AMB_0603
HT-191NBQA_BLUE_0603 HT-191NBQA_BLUE_0603 (AMB) KAL90@
KAL90@ KAL90@ KAL90@
1

1
ACIN# ACIN#
ON/OFF Button
ON/OFF LED DOWN
SW3
EVQPLHA15_4P
(BLUE)
3 1 LED6
ON/OFFBTN# ON/OFFBTN# <37> R1818
4 2 +5VALW 1 2 2 B 1 PWR_LED#
KAL90@ 220_0402_5%
(AMB) R1819

5
6
LED11 KALH0@ R1839 KALH0@ +5VALW 1 2 4 A 3 PWR_SUSP_LED#
453_0402_1% KAL90@ 453_0402_1%
3 1 2 PWR_SUSP_LED#
UD

R1842 KALH0@
(AMB) HT-297UD/CB _BLUE/AMB_0603
KAL90@
+5VALW 1
220_0402_5%
NB
2 1 2 PWR_LED#
C C
MEDIA_LED NUM_LED CAPS_LED (BLUE) FOR EMI
HT-210UD/NB_AMB/BLUE
+5VS +5VS +5VS @
(BLUE) (BLUE) (BLUE) PWR_SUSP_LED# C2158 1 2 100P_0402_50V8J
LED12 KALH0@ R1843 KALH0@
453_0402_1% PWR_LED# C2155 1 @ 2 100P_0402_50V8J
3 1 2 PWR_SUSP_LED#
2

2
UD
ON/OFFBTN# C2160 1 @ 2 100P_0402_50V8J
R1820 R1822 R1823 +5VALW 1 R1844 KALH0@
10K_0402_5% R1821 150_0402_1% 150_0402_1% 220_0402_5%
453_0402_1% KAL90@ KAL90@ NB
2 1 2 PWR_LED#
KAL90@
1

1
@
HT-210UD/NB_AMB/BLUE NUM_LED# C2162 1 2 100P_0402_50V8J
2

2
@
LED7 LED8 LED9 CAPS_LED# C2167 1 @ 2 100P_0402_50V8J
HT-191NBQA_BLUE_0603 HT-191NBQA_BLUE_0603 HT-191NBQA_BLUE_0603
KAL90@ KAL90@ KAL90@ MEDIA_LED# C2165 1 @ 2 100P_0402_50V8J
1

1
MEDIA_LED# NUM_LED# NUM_LED# <35,36> CAPS_LED# CAPS_LED# <35>

PWR_LED#

6
Q133A
B 2N7002DW-T/R7_SOT363-6 B
PWR_LED# MEDIA_LED# CAPS_LED# ON/OFFBTN# <35> PWR_LED 2

1
PWR_SUSP_LED# NUM_LED# ACIN#

1
R1831
3

2
D55 D56 D57 D58
10K_0402_5%

2
PWR_SUSP_LED#
1

3
PJMBZ6V8_3P_C/A_SOT-23 PJMBZ6V8_3P_C/A_SOT-23 PJMBZ6V8_3P_C/A_SOT-23 PJSOT24C_3P_C/A_SOT-23
Q133B
2N7002DW-T/R7_SOT363-6
KAL90@ KAL90@ 5
<35> PWR_SUSP_LED

4
R1830
D1 D2 D3 USE PANJIT PJMBZ6V8 10K_0402_5%
ACIN# D4 USE
SCA00000I00

2
PJSOT24C 3P C/A SOT-23
6.8V D
1

Q135 2
SCA00000E00
+3VS ACIN <27,35,41,43,46>
KAL90@
2N7002_SOT23 S
G 24V
3

Q134A
2

A
2N7002DW-T/R7_SOT363-6 A

<30> 5IN1_LED# 1 6

SATA_LED# 4 3 MEDIA_LED#
<26> SATA_LED# MEDIA_LED# <36>

Q134B Security Classification Compal Secret Data Compal Electronics, Inc.

5

2N7002DW-T/R7_SOT363-6 2008/11/10 2008/11/17 Title

+3VS Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR/B
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Wednesday, December 24, 2008 Sheet 42 of 52
5 4 3 2 1
 A B C D

1 1

PR1
DC231000500 1M_0402_1%
<BOM Structure>
1 2
SINGA_2DC-G756I200 PL1
SMB3025500YA_2P
VIN VIN
VS
VIN
DC_IN_S1 1 2DC_IN_S2
1

1
@ PR2 PR3
G 2 10K_0402_5% 84.5K_0402_1%
G PR209 PR5

8
3 PC2 PR4 10K_0402_1% 22K_0402_5%

2
PC3 PC4 100P_0402_50V8J PC1 0_0402_5% 3 1 2

P
PJP3 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K +
1 2 1 2 1

2
<27,35,41,42,46> ACIN 0

20K_0402_1%
- 2

1
PR6
PU1A

1
PC6
LM358DT_SO8 PC5

0.1U_0603_25V7K
4
PR7 PD3 1000P_0402_50V7K

2
10K_0402_1% GLZ4.3B_LL34-2

2
2

2
PR8
PR123
10K_0402_1%
1 2 1 2
RTCVREF
0_0603_5%

PQ25 MCVCC PQ28

@ SI2301BDS-T1-E3_SOT23-3 @ SI2301BDS-T1-E3_SOT23-3
+3VALWP
2

Vin Dectector 2

S
S

D
1 3 3 1 RTCVREF
D

Min. Typ Max.

G
G
2

2
1

PR102 PR122
H-->L 16.976V 17.525V 17.728V
@ 200K_0402_1% @ 200K_0402_1% L-->H 17.430V 17.901V 18.384V
2

D
2
G PQ46
PQ45 S @ 2N7002W-T/R7_SOT323-3
3
1

D @ 2N7002W-T/R7_SOT323-3
2
G SPOK <44,45> PJ2 PJ3
S
+3VALWP 2 1 +3VALW +1.5VP 2 1 +1.5V
3

2 1 2 1
JUMP_43X118 JUMP_43X118

PJ4 PJ5
VIN +5VALWP 2 2 1 1 +5VALW +0.9VSP 2 2 1 1 +0.9VS
3 3

JUMP_43X118 JUMP_43X79
2

PD4
LL4148_LL34-2
PJ6
PJ7
PD5 2 1 +1.8VP 2 1 +1.8V
+VSBP +VSB
1

LL4148_LL34-2 2 1 2 1
BATT+ 2 1 JUMP_43X39 JUMP_43X118
1

PR9 PR10
PQ1 68_1206_5% 68_1206_5%
TP0610K-T1-E3_SOT23-3
PR11 PJ8 PJ17
2

200_0603_5% 2 1 +1.8VP 2 1 +1.8V

CHGRTCP N1 +1.05VSP 2 1 +1.05VS 2 1
1 2 3 1
VS JUMP_43X118 JUMP_43X118
1

PR12 PC8
PJ18
100K_0402_1% PC7 0.1U_0603_25V7K PJ16
0.22U_0603_25V7K +1.1VSP
+1.05VSP 2 1 +1.05VS 1 2 +1.1VS
2

PR13 2 1 1 2
2

22K_0402_1% JUMP_43X118 @

<37> 51ON#
1 2 - PBJ1 + JUMP_43X79

2 1 +RTCBATT
+RTCBATT PJ9 PJ20
+VGA_COREP 2 2 1 1 +VGA_CORE +VGA_COREP 2 2 1 1 +VGA_CORE
RTCVREF ML1220T13RE JUMP_43X118 JUMP_43X118
1

4 4
45@
PR14
PU2 200_0603_5%
PR15 PR16 G920AT24U_SOT89-3
560_0603_5% 560_0603_5% 3.3V
2

1 2 1 2 3 2 N2
OUT IN
+CHGRTC
Security Classification Compal Secret Data Compal Electronics, Inc.
1

GND PC10
PC9 1U_0805_25V4Z 2008/11/10 2008/11/17 Title
10U_0805_10V4Z 1 Issued Date Deciphered Date
DCIN & DETECTOR
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Tuesday, December 09, 2008 Sheet 43 of 52
A B C D
 A B C D

PH1 under CPU botten side :

CPU thermal protection at 96 degree C
Recovery at 60 degree C
VL
VL
VL
VMB

2
PL2 PR17

1
1 1

PJP2 SMB3025500YA_2P 47K_0402_1%

1 1 BATT_S1 1 2 BATT+ PH1 PC11
MAINPWON <26,45>
2 100K_0603_1%_TH11-4H104FT 0.1U_0603_25V7K PR18

1
2 47K_0402_1%
3 3

1
4 EC_SMCA 1 2

2
4 EC_SMDA PC12 PC13 PR19 PQ2
5 5

8
6 1000P_0402_50V7K 0.01U_0402_25V7K 13.7K_0402_1% DTC115EUA_SC70-3

2
6 PD6
7 1 2 3

P
7 +
O 1 2 1 2
SUYIN_250133MR007G115ZL TM_REF1 2 -

G
PU3A LL4148_LL34-2
LM393DG_SO8

3
2

0.22U_0603_16V7K
PR20 PR21
100_0402_1% 100_0402_1%

15.4K_0402_1%
1

1
PC14
PR23

PR22
100K_0402_1%

1000P_0402_50V7K
1

2 1 VL

1
PR24

PC15
6.49K_0402_1%

2
2 1 +3VALWP

1
1

PR25
PR26 100K_0402_1%
1K_0402_1%

2
2

2 2

BATT_TEMP <35>

EC_SMB_CK1 <35,36> PH2 near main Battery CONN :

BAT. thermal protection at 79 degree C
EC_SMB_DA1 <35,36>
Recovery at 47 degree C
VL

2
@ PR27
VL 47K_0402_1%
@ PR28
47K_0402_1%

1
1 2

1
PQ3
TP0610K-T1-E3_SOT23-3
@ PH2
100K_0603_1%_TH11-4H104FT VL

B+
3 1 +VSBP

2
0.22U_1206_25V7K

@ PR30
0.1U_0603_25V7K
1

8
13.7K_0402_1% @ PD7
1

1
PC16

PC17

PR29 1 2 5 LL4148_LL34-2

P
100K_0402_1% +
O 7 2 1
@ @ TM_REF1 6
2

G
1
3 3

PR31 PU3B
2

1
VL 22K_0402_1% LM393DG_SO8

4
1 2 @ PC18 @ PR32
0.22U_0603_16V7K 15.4K_0402_1%

2
2

PR33
100K_0402_1%

PR34
1

0_0402_5% PQ4 D
1 2 2
<43,45> SPOK G 2N7002W-T/R7_SOT323-3
0.1U_0402_16V7K

S <BOM Structure>
3
1

PC19

@
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 44 of 52
A B C D
 5 4 3 2 1

ISL6237_B+
ISL6237_B+

PR35
PJ10 0_0805_5%
2 1 1 2
D
B+ 2 1
D
JUMP_43X118

2200P_0402_50V7K

2200P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K
1

5
6
7
8
PC20

PC21

PC22

8
7
6
5

1
PC25
<BOM Structure> VL

PC23

PC24
1U_0603_10V6K
2

2
PQ6

2
2
PQ5 PC26 AO4466_SO8

2
AO4466_SO8 0.1U_0603_25V7K 4

<BOM Structure>
4.7U_0603_6.3V6M
1
PC27
4

PC28
1
+5VALWP

3
2
1
PL4

1
2
3
PL3 8.2UH +-20% FDV0630-8R2M=P3 3.7A

7
8.2UH +-20% FDV0630-8R2M=P3 3.7A PC29 2 1
1 2 1U_0603_10V6K

LDO
VIN

VCC
+3VALWP 33 19 1 2
TP PVCC

5
6
7
8

1
4.7_1206_5%
1

8
7
6
5

PR39
DH3 26 15 DH5
PR36 PR37 UGATE2 UGATE1 PR40 0_0603_5% PQ8
4.7_1206_5% PQ7 2 1 BST3A 24 17 BST5A 2 <BOM 1Structure> AO4712_SO8
BOOT2 BOOT1
1

AO4712_SO8 0_0603_5%

63.4K_0402_1%
1

2
2

2
PR38 <BOM Structure> PC32 4

2
+

PR41
PC30 0_0402_5% 4 PC31 0.1U_0603_25V7K

2
330U_D2E_6.3VM_R25M 0.1U_0603_25V7K

680P_0402_50V7K
1

1
1
LX3 25 16 LX5 1
2

2 PHASE2 PHASE1

PC34
PC33

3
2
1

2
C 680P_0402_50V7K + PC35 C

1
2
3
DL3 23 18 DL5 150U_D2E_6.3VM_R18

1
LGATE2 LGATE1
2
2

10K_0402_1%
PGND 22

2
FB3 30 OUT2

PR43
@ PR42
10K_0402_1% 10
OUT1
VL 32
1

REFIN2

1
11 FB5
2VREF_ISL6237 FB1

1 2 1 REF
PC36 0.22U_0603_10V7K
BYP 9
8 LDOREFIN
+3.3VALWP Ipeak=8.444A ; Imax=5.91A @ PR44 0_0402_5%
29 2 1 VL
Choke DCRmax=60m ohm, DCRtyp=54m ohm SKIP
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) PR45 0_0402_5%
Vlimit=(5E-06 * 330K)/10=165mV 1 2
20 NC POK2 28
Ilimit=165mV/18m ~ 165mV/15m PD8 PR46
=9.167A ~ 11A GLZ5.1B_LL34-2 100K_0402_1%
1 2 1 2 4 13 SPOK <43,44>
Iocp=Ilimit+Delta I/2 VS EN_LDO POK1 PR48
2

=10.134A ~ 11.967A 330K_0402_1%

200K_0402_5%

B B
PR47

14 12 ILM1 2 1
Delta I=1.934A (Freq=300KHz) PC37 EN1 ILIM1
0.22U_0603_25V7K
1

27 31 ILIM2 2 1

GND
TON
1

EN2 ILIM2
1

NC
2

PD12 PR49
0_0402_5%

1SS355_SOD323-2 VL @ PR50
2
PU4 330K_0402_1%

21
PR51

0_0402_5% ISL6237IRZ-T_QFN32_5X5
2
2

PR52
1

1
806K_0603_1%
1U_0603_10V6K
1

PR54 @ PR55 PR53

+5VALWP Ipeak=8.444A ; Imax=5.91A
2VREF_ISL6237
1

2
0_0402_5% 47K_0402_5% 0_0402_5%
PC143

2 1 1 2 Choke DCRmax=60m ohm, DCRtyp=54m ohm

2
1

Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)

0.047U_0402_16V7-K

2VREF_ISL6237

<26,44> MAINPWON
Vlimit=(5E-06 * 330K)/10=165mV
1

PC38

Ilimit=165mV/18m ~ 165mV/15m
2

=9.167A ~ 11A
1

@ PC39 Iocp=Ilimit+Delta I/2

3

0.047U_0402_16V7K
2

=10.147A ~ 11.980A
Delta I=1.96A (Freq=400KHz)
A 2 PQ35 A
TP0610K-T1-E3_SOT23-3
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+5VALWP/+3VALWP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 45 of 52
5 4 3 2 1
 A B C D

PQ9 PQ10 B+
AO4407A_SO8 AO4407A_SO8
VIN 8 1 1 8
7 2 2 7 PJ11
6 3 3 6 2 PR56
1 2 1 CHG_B+
2 1

1
5 5 0.015_1206_1%

2
JUMP_43X118 PR57

2200P_0402_25V7K
4.7U_1206_25V6K

4.7U_1206_25V6K
PR58 CHGEN# PC40 100K_0402_1%

2
3.3_1210_5% 0.01U_0402_25V7K

0.01U_0402_25V7K

1
PC42

PC43

PC44
100K_0402_1%

2
1
PC46 PC48

1
2

5
6
7
8

3
2
1
1 1

PC45

PR59
0.1U_0402_16V7K PU5 0.1U_0603_25V7K
1 2 1 28 PVCC 1 2 PQ12
CHGEN PVCC

1
SI4835DDY-T1-E3_SO8

1
PR174 PR61 /BATDRV 4

2
3.3_1210_5% PC47 @PC49
@PC49 0_0603_5% PQ11
0.1U_0603_25V7K 0.1U_0603_25V7K 27 BTST 1 2 4 AO4466_SO8

2
BTST

2
2
PR60
340K_0402_1% ACN 2 26 DH_CHG
ACN HIDRV
1

ACP 3

3
2
1

5
6
7
8
PC50 ACP

1
2.2U_0805_25V6K ACDRV 4 25 LX_CHG PL5
2

ACDET ACDRV PH PD10 10UH_PCMB104T-100MS_6A_20% PR62 0.02_1206_1%

5 ACDET
2 1 1 2 1 2 1 4
BATT+
Place close to back to back MOS

10U_1206_25V6M
1
LL4148_LL34-2 PC51

10U_1206_25V6M
REGN
2 3

2
0.1U_0603_25V7K @ PR64 <BOM Structure>

5
6
7
8

PC53
24751_VREF PR63 4.7_1206_5%

PC52
CELLS GND 3 Cell 54.9K_0402_1% ACSET 6 ACSET
24

2
REGN
VREF 4 Cell
1
2

1
PC54 PQ13
@ PR65 1U_0603_10V6K 4 AO4466_SO8

@
47K_0402_1% PR66 PC56 PC55
P C55

2
2

0_0402_5% 0.47U_0603_16V7K 680P_0402_50V7K

1 2 1 2 7
1

2
PR67 ACOP DL_CHG
23

3
2
1
340K_0402_1% LODRV
CELLS
1

PGND 22
@ PQ14 OVPSET 8 PC57
OVPSET
1

2 D 2N7002W-T/R7_SOT323-3 0.1U_0402_16V7K 2

2 3S/4S# <35> 1 2
G 9 21 ACOFF <35>
AGND LEARN
2

S
3

1
PR68
54.9K_0402_1% PC58 @PC59
@PC59
24751_VREF CELLS 0.1U_0603_25V7K 0.1U_0603_25V7K
Cells selector 20

2
CELLS
1

24751_VREF 10
PQ15 VREF
3

1
SI2301BDS-T1-E3_SOT23-3
PC60
PR69 1U_0603_10V6K 19 SE_CHG+

2
SRP
100K_0402_1% RTCVREF
CP Point Setting 1 2PQ15_GATE
2 11 VDAC SRN 18 SE_CHG-
1

CP point=Iadapter*85% BAT 17
1

PR70

1
90W adapter PC62 100K_0402_1% VADJ 12
0.1U_0603_25V7K VADJ PC61
Vacset=3.3*(100K/(64.9K+100K))=2.001V
2

ACSET 0.1U_0603_25V7K
2

2
CP Point=(Vacset/Vvdac)*(0.1/PR56)=4.04A TP 29 Icharge Setting
ACGOOD# 13 ACGOOD ICHG setting PR71 For 2200mA, Icharge=0.8C=0.8*2*2.2=3.52A
65W adapter R=(100K*100K)/(100K+100K)=50K 17.4K_0402_1% For 2400mA, Icharge=0.8C=0.8*2.4*2=3.84A
VMB 16 SRSET 2 1 Icharge=(Vsrset/Vdac)*(0.1/PR62)
Vacset=3.3*(50K/(50K+64.9K))=1.436V /BATDRV 14
SRSET IREF <35> IREF=((100k/(100K+17.4K))/3.3)*(0.1/0.02)=Icharge
BATDRV

1
PR72
IREF=0.7748*Icharge

1
CP POINT=(1.436V/3.3V)*(0.1/0.015)=2.901A 10_0603_5% PR73
1

15 1 2 100K_0402_1% @PC63
@PC63
IADAPT 0.01U_0402_25V7K

2
VS PR74 BQ24751ARHDR_QFN28_5X5 24751_VREF
Input OVP : 22.3V

2
3 3

LI-4S :18.0V----BATT-OVP=2.001V 340K_0402_1%

1
Input UVP : 17.26V
2

2
BATT-OVP=0.1112*VMB PC64
0.01U_0402_25V7K

Fsw : 300KHz 100P_0402_50V8J @ PR75

2
LI-3S :13.5V----BATT-OVP=1.5012V 100K_0402_1%
1

PC65

24751_VREF 24751_VREF ADP_I <35> @ PR176

1

BATT-OVP=0.1112*VMB 0_0402_5% 24751_VREF

1
PR76
200K_0402_1%
1 2
2

1
Per cell=4.5V 499K_0402_1%
100K_0402_1%

ACIN <27,35,41,42,43>
1

1
PR180

PQ15_GATE

1
D
PR179

PR78
2
8

PR77 PU1B 887K_0402_1% ACGOOD# 2 @ PQ16

1
10K_0402_1% LM358DT_SO8 PQ36 D PQ17 G 2N7002W-T/R7_SOT323-3
5
P

+ SI2301BDS-T1-E3_SOT23-3 PR80
1 2 7 0 2 S
2

3
<35> BATT_OVP 6 PC163 G 2N7002W-T/R7_SOT323-3 0_0402_5%
-
G

S
0.1U_0402_16V7K PQ37 REGN VADJ

D
S 3 1 1 2
3
1

ACOFF 1 24751_VREF
0.01U_0402_25V7K

2 2
4

PR79 G 2N7002W-T/R7_SOT323-3

1
PC66

105K_0402_1%

G
S
3

2
1

2
PR82
340K_0402_1%

221K_0402_1%
2

1
PR181

100K_0402_1% PC144 PR81

2

PR84
@ PR177 1000P_0402_50V7K 100K_0402_1%

2
PR83 4.3K_0402_5%

2
64.9K_0402_1%
2

1
24751_VREF 1 2 ACSET CHGEN#

2
1
PQ19 D
1

1
PQ18 D
2
<35> CALIBRATE# G 2N7002W-T/R7_SOT323-3 <35> FSTCHG 2
PR85 S G 2N7002W-T/R7_SOT323-3

3
100K_0402_1% S

3
1

4 4
2

PR86
100K_0402_1%
1

PQ20 D

<35> 65W/90W# 2 Charger ADJ Calibrate# PR78 PR84

2

G 2N7002W-T/R7_SOT323-3
S
3

4.0V L @ @ Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title
4.1V L 887K 221K CHARGER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
CP setting 4.2V H @ @
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 46 of 52
A B C D
 A B C D

PC68

1
PC67 1U_0402_6.3V6K
1U_0402_6.3V6K

2
PR87 PR88
2.2_0603_1% 2.2_0603_1%
1
+5VALW 2 1 1 2 +5VALW 1

PJ15
JUMP_43X118
2 2 1 1
B+ ISL6228_B++

1
PC70 PC69
0.1U_0603_25V7K 0.1U_0603_25V7K

2
PJ12
JUMP_43X118 PR89 PR90
2 2 10_0603_1% 10_0603_1%
1 1
B+ ISL6228_B+ ISL6228_B++ 2 1 2 1 ISL6228_B+

22K_0402_1%

2
1000P_0402_50V7K
2
PR92

PR91
18.2K_0402_1%

1
PC72 PR93 PC71

PC73
1000P_0402_50V7K 3.3K_0402_5% PR94 1000P_0402_50V7K

1
2 1 1 2 59K_0402_1%

2
<BOM Structure>

1
PR95

1
45.3K_0402_1%
FB_1.05V 2 1 FB_1.05V-1 29

PGOOD1

FSET1

VIN1

VCC1

VCC2

VIN2

FSET2
GND_T
PR98 PC74

2
PR96 3.3K_0402_5% 1000P_0402_50V7K
11.8K_0402_1% 8 28 PR97 2 1 1 2
2
6228_1.05VO1 FB1 PGOOD2 22.6K_0402_1% 2
1 2

PR99

1
45.3K_0402_1%
ISL6228_B++ 9 27 FB_1.8V-1 1 2 FB_1.8V
VO1 FB2

PR100
4.7U_1206_25V6K

4.7U_1206_25V6K
1

1
PC76

PC77

10K_0402_1%
8
7
6
5

PC75 OCSET_1.05V 10 26 6228_1.8VO2 1 2

0.015U_0402_16V7K OCSET1 VO2
2

1 2 PQ21
AO4466_SO8
Vref=0.6V
2

PR101 4 1.05V_EN 11 25 OCSET_1.8V

11.8K_0402_1% EN1 PU6 OCSET2
PR103
ISL6228HRTZ-T_QFN28_4X4 0_0402_5% SYSON <34,35,41> ISL6228_B+
+1.05VSP 1 2
1

1
2
3

1 2 LX_1.05V 12 24
PHASE1 EN2 @ PC78
1

8
7
6
5

PL6 0.01U_0402_25V7K PC82

4.7U_1206_25V6K

4.7U_1206_25V6K
5
6
7
8

1
PC81

PC79
1UH +-20% FDV0630-1R0M=P3 10.3A PQ22 1 2 0.022U_0402_16V7K
D
D
D
D

1 PR104 FDS6670AS_NL_SO8 1 2
@ 4.7_1206_5% UG_1.05V 13 23

2
PC80 + UGATE1 PHASE2
2

2
330U_D2E_2.5VM 4 PR105
G PR106 PQ23 10K_0402_1%
4
2 0_0603_5% AO4466_SO8
1

S
S
S

PC83 2 1 2 1BST_1.05V14 BOOT1 UGATE2 22 UG_1.8V

@ 680P_0402_50V7K
1
2
3

1
LGATE1

LGATE2
PC84
PGND1

PGND2

BOOT2
PVCC1

PVCC2
2

3
2
1
3 3

0.1U_0402_16V7K LX_1.8V 1 2
+1.8VP

1
5
6
7
8
@ PR108 PL12
DCR 11.9m ohm(max) Cout ESR=15m ohm 4.7_1206_5% 1UH_FDV0630-1R0M-P3_10.3A_20%

FDS6670AS_NL_SO8
1

D
D
D
D
15

16

17

18

19

20

21
+1.05VSP OCP Seting is same as ICL50 +

PQ24
PC88
Vo=Vref*((PR80+PR82)/PR80)

2
PR109 PC87 330U_D2E_2.5VM
Ipeak=14.02A, Imax=9.81A 0_0603_5% 0.1U_0402_16V7K 4 G

1
BST_1.8V 1 @ PC89 2
Iocp=14.02*1.2=16.824A +5VALW 2 1 2
680P_0402_50V7K
+5VALW
2

S
S
S
Csen=L/(Rocset*DCR)

2
0.015U=1U/(Rocset*6m) Rocset=11.111K~11.8K PC85 PC86

3
2
1
1U_0402_6.3V6K 1U_0402_6.3V6K
1

Iocp=(Rocset*10uA)/DCR
Iocp=(11K*10uA)/(6m ohm*1.3) =15.1A
DCR 6m ohm(max) Cout ESR=15m ohm
LG_1.05V LG_1.8V
Vo=0.6*((PR87+PR83)/PR83)=1.8V
1.8VP Ipeak=11.93A, Imax=8.351A
Csen=L/(Rocset*DCR)=1uF/(Rocset*6m ohm)=0.022uF
@ PR178
=>Rocset=7.575K, Choose 10K because of thermal factor
0_0402_5% Iocp=(Rocset*10uA)/DCR=(10K*10uA)/(0.006*1.3)=12.82A
1 2 1.05V_EN
<35,41> SBPWR_EN
1

@PC94
@PC94
4
0.1U_0402_16V7K 4
2

PR112
0_0402_5%
1 2
<37,48> VS_ON

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.8VP / 1.05VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 47 of 52
A B C D
 5 4 3 2 1

D
PJ13 D
JUMP_43X118

4.7U_1206_25V6K
51117_B+ 2 2 1 1 B+

PC91
PQ26

2
DH_1.5V 8 1
PR111 G2 D2
7 S2/D1 D2 2
200K_0402_1% 6 3 DL_1.5V
PR110 S2/D1 G1
1 2 5 S2/D1 S1 4
0_0402_5%
2 1 AO4932_SO8
<37,47> VS_ON

PR113 PC93 2.2UH +-20% FDV0630-2R2M=P3 7.2A

1
0_0603_1% 0.1U_0603_25V7K PL8

15

14
1
@ PC90
0.01U_0402_25V7K
PU7 BST_1.5V 1 2BST_1.5V-1 1 2 1 2 +1.5VP

EN_PSV

TP

VBST
2
2 13 DH_1.5V
TON DRVH
3 12 LX_1.5V 1
VOUT LL
VFB=0.75V + PC95
4 V5FILT TRIP 11 +5VALW 330U_D2E_2.5VM
5 VFB V5DRV 10
2
6 9 DL_1.5V
PGOOD DRVL

PGND
PR114

GND

1
300_0603_5%

17.8K_0402_1%
PR115
1 2 @ PC96 PC97
C +5VALW 47P_0402_50V8J TPS51117RGYR_QFN14_3.5x3.5 4.7U_0805_10V6K C

2
1 2
1

2
PC98
1U_0603_10V6K
2

PR116
10K_0402_1%
1 2
1

PR117
10K_0402_1%
2

+1.8V
VFB=0.75V
Vo=VFB*(1+PR87/PR88)=0.75*(1+4.02K/10K)=1.05V
Ton=200K

1
Fsw=400KHz PJ14

1
JUMP_43X79

2
PU8

2
1 VIN VCNTL 6 +3VALW
B Cout ESR=15m ohm B
2 5
Ipeak=14.02A, Imax=9.81A GND NC

1
1
Delta I=((19-1.05)*(1.05/19))/(L*Fsw)=2.4872A PC99 3 REFEN NC 7 PC100
4.7U_0603_6.3V6M PR118 1U_0402_6.3V6K
=>1/2DeltaI=1.243A

2
1K_0402_1% 4 8
Vtrip=Rtrip*10uA=17.8K*10uA=0.178V VOUT NC

Iocpmin=Vtrip/Rdsonmax*1.2+1.243A 9

2
GND
=0.178/(0.0115*1.2)+1.243=12.898A+1.243A=14.141A RT9173DPSP_SO8
Iocpmax=(0.178/(0.009*1.1))+1.243A=17.98A+1.243A
PR119

0.1U_0402_16V7K
=19.22A +0.9VSP

1
0_0402_5% PQ27 D
Iocp=14.141A~19.22A <37,41> SUSP

PC101
1 2 2 PR120

1
G 2N7002W-T/R7_SOT323-3

2
1
S <BOM Structure> PC104

3
PC103 1K_0402_1% 10U_0805_6.3V6M

2
0.1U_0402_16V7K

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.5VP/+0.9VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 48 of 52
5 4 3 2 1
 5 4 3 2 1

+5VS

B+
CPU_VID6 <5> CPU_B+

2
CPU_VID5 <5> PR125 PL9
1_0603_5% FBMA-L18-453215-900LMA90T_1812
CPU_VID4 <5> 2 1
<35,37> VR_ON

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_50V7K
CPU_VID3 <5>
PR126

1000P_0603_50V7K
1

1
PC112

PC113
D
499_0402_1% CPU_VID2 <5> D

1
+

PC114
<8,27> PM_DPRSLPVR 1 2 PC110 PC115
220U_25V_M

PC116
CPU_VID1 <5> PC109 2.2U_0603_6.3V6K

2
5
PR127 0_0402_5% 0.022U_0402_16V7K

2
2
<5,8,26> H_DPRSTP# 1 2 CPU_VID0 <5>
PR128 0_0402_5% PR107
1 2 0_0603_5% PQ29

1
<16> CLK_ENABLE#

PR130 0_0402_5%

PR131 0_0402_5%

PR132 0_0402_5%

PR133 0_0402_5%
PR129 0_0402_5%

PR135 0_0402_5%

PR136 0_0402_5%

PR137 0_0402_5%
UGATE_CPU1 2 1 U_CPU1 4 SI7686DP-T1-E3_SO8
PR134 0_0402_5%
+3VS 1 2
+3VS

3
2
1
1
PR138 PC119 PL10

1U_0402_6.3V6K
PC118
0_0603_1% 0.22U_0603_10V7K 0.36UH_PCMC104T-R36MN1R17_30A_20%

1.91K_0402_1%
+CPU_CORE
1
BOOT_CPU1 1 2 1 2 PHASE_CPU1 1 4

2
2

PR140

5
6
7
8

5
6
7
8

1
PR139

6.8_1206_5%
2 3

1
PR142

10K_0402_1%
499_0402_1%

49

48

47

46

45

44

43

42

41

40

39

38

37

1
PR144
3.65K_0805_1%
2

PR143
PQ30 PR145

GND

3V3

CLK_EN#

DPRSTP#

DPRSLPVR

VR_ON

VID6

VID5

VID4

VID3

VID2

VID1

VID0
1

AO4456_SO8 @ PR146 1_0402_5%

1 2
PQ31 0_0603_5%

680P_0402_50V7K
1 36 4 4

2
<8,16,27> VGATE PGOOD BOOT1 AO4456_SO8 1 2

2
PC120
<5> PSI# PR147
1 20_0402_5% 2 35 UGATE_CPU1
PSI# UGATE1 VSUM 1 2

2
<35> PGD_IN 1@ PR148 2 3 34 PHASE_CPU1

3
2
1

3
2
1
PMON PHASE1

LGATE_CPU1

LGATE_CPU1
PC121
0_0402_5% 1 PR149
2 147K_0402_1% 4 33 0.22U_0603_10V7K VCC_PRM
RBIAS PGND1 ISEN1
VR_TT# 5 32 LGATE_CPU1 CPU_B+
VR_TT# LGATE1

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_50V7K
5
C C

1000P_0603_50V7K
6 NTC PVCC 31

1
PC122

PC123
7 PU10 30 LGATE_CPU2
SOFT LGATE2

PC124

PC117
ISL6262ACRZ-T_QFN48_7X7 PR121
PC125 8 29 0_0603_5%

2
OCSET PGND2
0.022U_0603_25V7K 2 1 U_CPU2-1 4
1 2 9 28 PHASE_CPU2
VW PHASE2 PQ32
PR151 13K_0402_1% 10 27 UGATE_CPU2-1 PL11
COMP UGATE2 SI7686DP-T1-E3_SO8 0.36UH_PCMC104T-R36MN1R17_30A_20%
1 2

3
2
1
11 26 BOOT_CPU2
1 2 1 2 1 4
FB BOOT2 PR152
1 2

5
6
7
8

5
6
7
8

1
DROOP

PC126 1000P_0402_50V7K 0_0603_1% PC127

6.8_1206_5%
12 FB2 NC 25 2 3
VDIFF

VSUM

ISEN2

ISEN1
VSEN

PR154
PR153 6.81K_0402_1% 0.22U_0603_10V7K PQ34

3.65K_0805_1%
GND

VDD
RTN

DFB

1
VIN
VO

10K_0402_1%
1 2 AO4456_SO8

PR157

PR155
PQ33
1 2 AO4456_SO8 PR156
13

14

15

16

17

18

19

20

21

22

23

24

1 2
4 4 1_0402_5%
PC128 1000P_0402_50V7K @ PR159

2
PC129
ISEN1 0_0603_5%

680P_0402_50V7K
ISEN2 1 2

2
2

0_0402_5%

1K_0402_1%

PR160 97.6K_0402_1% PC130 470P_0402_50V7K 1 2 +5VS

3
2
1

3
2
1
1
@ PR161

1 2 2 1 PR158 1_0603_5% VSUM

1
PR162

1 2
PC133 220P_0402_50V7K PC131
1 2 1U_0402_6.3V6K PC132
1

LGATE_CPU2

LGATE_CPU2
0.22U_0603_10V7K
2

VCC_PRM
PR163 PR164 ISEN2
255_0402_1% PC134 1000P_0402_50V7K 10_0603_5%
1 2 1 2 1 2 CPU_B+
B B
1

1 2 PC135
PR165 1K_0402_1% 0.1U_0603_25V7K
PR166
2

0_0402_5% PC136 820P_0402_50V7K

<5> VCCSENSE 1 2 1 2
VSUM
1

PR167
1

20_0402_5% @PC137
@PC137 PC138
+CPU_CORE 1 2 0.022U_0603_50V7K 0.01U_0603_50V7K PR168
2

PR169 2.61K_0402_1%
2

0_0402_5%
<5> VSSSENSE 1 2
2
1
11K_0402_1%

PC139 180P_0402_50V8J
2

PR171

1 2
2

PR170
20_0402_5% 1 2 1 2 PH3
10KB_0603_5%_ERTJ1VR103J
2

PR172 1K_0402_1% PR173 4.42K_0402_1%

1

VCC_PRM
PC140
0.1U_0402_16V7K
1 2

2 1
2

PC141 0.22U_0402_6.3V6K
PC142
A 0.22U_0603_10V7K A
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 49 of 52
5 4 3 2 1
 5 4 3 2 1

PL13

1 2 B+_core
B+

FBMA-L11-322513-201LMA40T_1210
6269_VCORE VGA_CORE

10U_1206_25V6M

10U_1206_25V6M
LX_VCORE

1
Imax=15.9A

1
PC164
DH_VCORE 1 PR183 2 DH_VCORE-1
Ipeak=22.8A

PC165
PR182 PR184 0_0603_5%

2
10K_0402_1% BST_VCORE
1 2 1 2
Iocp=30A

2
D 0_0603_5% PC166 0.1U_0603_25V7K D

2
+5VS
<41> NVVDD_PWRGD

5
PR185 PQ38
0_0603_5% SI7686DP-T1-E3_SO8

16

15
8

1
PU12

2
1 PR1862 6269_VCORE 4

UG

BOOT
PHASE
GND

PGOOD
4.7_0603_5%
3 VIN PVCC 14 1 2 PC167 DCR=3m OHM
+3VS

3
2
1
6269_VCORE 2.2U_0603_6.3V6K
PL14
PC168 4 13 DL_VCORE
2
2.2U_0603_6.3V6K VCC LG 1UH_PCMB103E-1R0MS_20A_20%

1
1 2 +VGA_COREP
PR187

1
@ 10K_0402_5% 12

2
PGND PQ39 PQ40 PR191

2
@4.7_1206_5% 1 PC169
PR189
1

10_0402_1%
PR190 SI7636DP-T1-E3_SO8 SI7636DP-T1-E3_SO8
+

PR192
SUSP# 1 2 5 11 ISEN_VCORE
1 2
<34,35,37,41> SUSP#

1 2
EN ISEN

330U_V_2.5VM_R9M
4 G 4 G

COMP
100K_0402_1% 6.34K_0402_1% PC171

FSET

1
1

VO
FB

S
S
S

S
S
S
PC170 @680P_0603_50V7K 1 2 +NVVDD_SENSE

2
PR194
2

10

3
2
1

3
2
1
C 0.1U_0402_16V7K ISL6268CAZ-T_SSOP16 C
0_0402_5%

2
PR193

1
1

1
22P_0402_50V8J
1 Rds=4.8mOHM 3K_0402_1%

1
PR195 VFB=0.6V
+3VS
PC172

PR196
6800P_0402_25V7K
49.9K_0402_1% PC173
0.01U_0402_25V7K
2

2
PR197

2
9.76K_0402_1%

PC174
@ PR211
57.6K_0402_1%
10K_0402_5%
2

1 1
1
PR199

1
PQ41D 10K_0402_1%
PR198 2 1 2 GPU_VID1 <18>
2N7002W-T/R7_SOT323-3
G

2
5.9K_0402_1% S <BOM Structure>

1
PR200
PC175 10K_0402_1%
0.022U_0402_25V7K

1
1
PR201
B 6.81K_0402_1% +3VS B
+1.8VS

2
@ PR210
PCIE_OK

2
10K_0402_5%
1

+5VS

1
1
PJ19 PQ42 D PR202
1

+3VS JUMP_43X79 2N7002W-T/R7_SOT323-3 2 1 2 GPU_VID0 <18>

4.7K_0402_5% @ G
2

PR203 S <BOM Structure> 10K_0402_1%

3
1

1
1 2 PC176
2

PC177 PR204
1U_0402_6.3V6K 10K_0402_1%
2

2
PR205 0.022U_0402_25V7K
2

M86-M

2
6

@ 10K_0402_5% PU13
5 PC178
VCNTL

VIN 10U_0805_10V4Z GPU_VID0 GPU_VID1 Core Voltage Level

7
2

POK
4
1

PR206 VOUT

VOUT 3 +1.1VSP 0 0 0.9 V

10K_0402_1%
1

SUSP# 1 2 8 2
<34,35,37,41> SUSP# EN FB
1

PC182 0 1 1.05 V
GND

9 PR207 PC179 22U_0805_6.3V6M

2

VIN
1

1.15K_0402_1%
2

NVVDD_PWRGD 2 1 PC180 0.01U_0402_25V7K 1 0 1.17 V

1
2

A A
PR212 S IC APL5913-KAC-TRL SO 8P
@ 10K_0402_5% @ PC181 1 1 1.35 V
22U_1206_6.3V6M
0.1U_0402_16V7K
1

PR208 Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title
3K_0402_1%
VGA_CORE/1.1VSP
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom kAL90KALH0 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, November 20, 2008 Sheet 50 of 52
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 2

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

D 0.2 change the resistance value of D

cpu load line fail Measure cpu load line can't fit spec 49 2008/08/08 DVT
1 pr173.from 4.42k to 3.83k

0.2 Change pc116 and pc117 size

Change resistance size EMI request 49 2008/08/08 DVT
2 from 0402 to 0603

0.2 PQ12 part number from DVT

Change p-mos part number Vender change EOL 46 2008/08/08
3 4835bdy to 483500y

0.2 PQ4,PQ14,PQ16,PQ18,PQ19,PQ20,PQ27,PQ36,PQ37,PQ41,PQ42 2008/08/12

Change device size device too large can't fit layout space 44-50 DVT
4 change to sot323-3

Change resistance value 1.05V tranient fail 0.2 47 PR94 from 60.4k to 59k 2008/08/12 DVT
5
change resistance for hdmi 0.2 45 pr41 change from 61.3k to 63.4k 2008/08/14 DVT
6

C 8 C

10

11

12

13

14

15
B B

16

17

18

19

20

21

22
A A

23

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title
PIR (PWR)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Thursday, November 20, 2008 Sheet 51 of 52
5 4 3 2 1
 5 4 3 2 1

A --> C Change List

1120-------------------
Page 35,Chang
R1745,R1746 to 4.7K SD028470180

1120-------------------
D Page 36,Add D
R106,R109,R1846,R1847 to 0R

1120-------------------
Page 37,Add
R1845 to 10K
1120-------------------
Page 37,Add
R49 to 1K, JP24 to ACES_88266_02001

1217-------------------
Page 42,Delete
R1814,R1815,R1816,R1817,R1818,R1819

0106-------------------
Page 39, Delete D63 for Microsoft certification;
Page 36, Delelte R1773, modify value or R1774, R1775 for LED color.

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/11/10 Deciphered Date 2008/11/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
kAL90KALH0
Date: Tuesday, January 06, 2009 Sheet 52 of 52
5 4 3 2 1