A B C D E

1 1

Compal Confidential
2 2

NAL00 Schematics Document

AMD L310/L110 Processor with RS780MN/SB710/M92-S2/S3 LP

3
2009-04-24 3

REV:0.2

hexainf@hotmail.com
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 1 of 49
A B C D E
 A B C D E

Compal Confidential
Model Name : NAL00

VRAM 512MB Fan Control AMD S1G1 Processor

page 4 Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
1 64M16 x 4 uPGA-638 Package 1

page 18 Dual Channel BANK 0, 1, 2, 3 page 8,9

page 4,5,6,7 1.8V DDRII 667/800

LVDS Conn. DDR3

page 21 Hyper Transport Link
ATI M92-S2 LP 16 x 16 5 in 1 socket
uFCBGA-631 PCI-Express 8x Thermal Sensor Clock Generator page 30
CRT Conn. Page 14,15,16,17,19
Gen1 ATI RS780MN ADM1032 SLG8SP626VTR
page 23
page 6 page 20
uFCBGA-528 Card Reader
RTS5159
HDMI Conn. page 30
page 22
PCI-Express 1x page 31
page 32 page 31 page 32
page 10,11,12,13
Port 2 Port 0 Port 1 USB conn To IO Board Mini Card 2
BT Conn (WWAN)
MINI Card 2 MINI Card 1 To IO board A link Express2 X2 USB conn X 2 page 31

Mini Card 1 Port 4

2
WWANpage 31 WLANpage 31 LAN(GbE) page 21 2

Realtek RTL8111CA Camera (WLAN)

page 31
ATI SB710 Port 1 Port 0
USB Port 6 Port 2 Port 3 Port 12 Port 8 Port 5
3.3V 48MHz
uFCBGA-528
HD Audio 3.3V 24.576MHz/48Mhz

S-ATA
port 0 port 1 HDA Codec
page 24,25,26,27,28
IO Board ALC269X-GR Digital MIC
page 31 page 37
SATA HDD CDROM page 36

PWR Board Conn.page 29 Conn.

page 29
page 35
LPC BUS Phone Jack x2
page 37
TP Board
page 34

3 LID SW/Cap sensor Board 3

page 33
ENE KB926
LED page 33
page 35

Power On/Off CKT.

page 35
Int.KB BIOS
page 34 page 34
RTC CKT.
page 24

DC/DC Interface CKT.

page 38

Power Circuit
page 39,40,41,42,43,44,4546,47

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 2 of 49
A B C D E
 A B C D E

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Voltage Rails Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU (0.7-1.2V) ON OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+NB_CORE 1.0V switched power rail ON OFF OFF
+0.9V 0.9V switched power rail for DDR terminator ON ON OFF
+1.1VS 1.1V switched power rail for NB VDDC & VGA ON OFF OFF Board ID / SKU ID Table for AD channel
+1.2V_HT 1.2V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+VGA_CORE 0.90-0.95V switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+1.5VS 1.5V power rail for PCIE Card ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.8V 1.8V power rail for CPU VDDIO and DDR ON ON OFF 0 0 0 V 0 V 0 V
+1.8VS 1.8V switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+2.5VS 2.5V for CPU_VDDA ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VALW 3.3V always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3V_LAN 3.3V power rail for LAN ON ON ON 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+3VS 3.3V switched power rail ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+5VALW 5V always on power rail ON ON ON* 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+5VS 5V switched power rail ON OFF OFF 7 NC 2.500 V 3.300 V 3.300 V
2 2
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON
BOARD ID Table BTO Option Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Board ID PCB Revision BTO Item BOM Structure
External PCI Devices 0 0.1 Discrete VGA@
Device IDSEL# REQ#/GNT# Interrupts 1 0.2 UMA UMA@
2 0.3 UMA_HDMI UMA_H@
3 1.0 Side port SP@
4 JM51 JM@
5 HM52 HM@
6
7

EC SM Bus1 address EC SM Bus2 address

3 3

Device Address HEX Device Address HEX

Smart Battery 0001 011X b 16H ADI ADM1032 (CPU) 1001 100X b 98H SB700 SB700 RS780MN DISPLAY OUTPUT
PX_GPIO0 PX_GPIO1 PX_GPIO2
SB-Temp Sensor 9CH Function Description dGPU_Reset dGPU_PWR_Enable PX Mode Switch
IGP only mode X X X
PowerXpress mode H : Enable H : Enable L : iGPU(DC) / H : dGPU(AC) LVDS / CRT
SB710 SB700
SM Bus 0 address SM Bus 1 address KB926
PX_GPIO1 PX_GPIO2 PX_+3VS PX_+1.8VS PX_+VGA_CORE PX_GPIO2_NB
Device Address HEX Device Address Function Description Enable +1.1VS_PX PX MODE SWITCH Enable +3VS_DELAY Enable +1.8VS_PX Enable +VGA_CORE Trigger from SB
New card IGP only mode X X X X X X
Clock Generator 1101 001Xb D2
(SILEGO SLG8SP626) PowerXpress mode H : Enable Reserved H : Enable H : Enable H : Enable Reserved
DDR DIMM1 1001 000Xb 90
KB926
DDR DIMM2 1001 010Xb 94
PX_GPIO1_SB
Mini card
Function Description Trigger from SB to Enable (PX_GPIO1/PX_+3VS/PX_+1.8VS/PX_+VGA_CORE)

hexainf@hotmail.com
4 4
IGP only mode X
PowerXpress mode H : Enable

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 3 of 49
A B C D E
 5 4 3 2 1

D H_CADIP[0..15] H_CADOP[0..15] D
<10> H_CADIP[0..15] H_CADOP[0..15] <10>
H_CADIN[0..15] H_CADON[0..15]
<10> H_CADIN[0..15] H_CADON[0..15] <10>

+1.2V_HT
JCPU1A
D4 VLDT_A3 VLDT_B3 AE5 1 2
VLDT=500mA D3 AE4 C904 4.7U_0805_10V4Z
VLDT_A2 VLDT_B2
D2 VLDT_A1 VLDT_B1 AE3
D1 VLDT_A0 VLDT_B0 AE2

H_CADIP15 N5 T4 H_CADOP15
H_CADIN15 L0_CADIN_H15 L0_CADOUT_H15 H_CADON15
P5 L0_CADIN_L15 L0_CADOUT_L15 T3
H_CADIP14 M3 V5 H_CADOP14
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 U5
H_CADIP13
H_CADIN13
L5
L0_CADIN_L14
L0_CADIN_H13
L0_CADOUT_L14
L0_CADOUT_H13 V4 H_CADOP13
H_CADON13
FAN1 Conn
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
H_CADIP12 K3 Y5 H_CADOP12
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12 +5VS
K4 L0_CADIN_L12 L0_CADOUT_L12 W5
H_CADIP11 H3 AB5 H_CADOP11 C108 10U_0805_10V4Z +5VS
H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11
H4 L0_CADIN_L11 L0_CADOUT_L11 AA5 1 2
H_CADIP10 G5 AB4 H_CADOP10
L0_CADIN_H10 L0_CADOUT_H10

1
H_CADIN10 H5 AB3 H_CADON10
H_CADIP9 L0_CADIN_L10 L0_CADOUT_L10 H_CADOP9 U10 D11
F3 L0_CADIN_H9 L0_CADOUT_H9 AD5
H_CADIN9 F4 AC5 H_CADON9 1 8 1SS355_SOD323-2
H_CADIP8 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP8 EN GND @
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4 2 VIN GND 7
H_CADIN8 F5 AD3 H_CADON8 +VCC_FAN1 3 6

2
C H_CADIP7 L0_CADIN_L8 L0_CADOUT_L8 H_CADOP7 VOUT GND D12 C
N3 L0_CADIN_H7 L0_CADOUT_H7 T1 <33> EN_DFAN1 2 1 4 VSET GND 5
H_CADIN7 N2 R1 H_CADON7 R62 300_0402_5% 1 2
L0_CADIN_L7 L0_CADOUT_L7

HTT Interface
H_CADIP6 L1 U2 H_CADOP6 1 APL5607KI-TRG_SO8
H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6 @ BAS16_SOT23-3
M1 L0_CADIN_L6 L0_CADOUT_L6 U3
H_CADIP5 L3 V1 H_CADOP5 C105 C121
H_CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5 10U_0805_10V4Z
L2 L0_CADIN_L5 L0_CADOUT_L5 U1 0.1U_0402_16V4Z
H_CADIP4 H_CADOP4 2
J1 L0_CADIN_H4 L0_CADOUT_H4 W2 1 2
H_CADIN4 K1 W3 H_CADON4
H_CADIP3 L0_CADIN_L4 L0_CADOUT_L4 H_CADOP3 +3VS C119
G1 L0_CADIN_H3 L0_CADOUT_H3 AA2
H_CADIN3 H1 AA3 H_CADON3 1000P_0402_50V7K
H_CADIP2 L0_CADIN_L3 L0_CADOUT_L3 H_CADOP2
G3 L0_CADIN_H2 L0_CADOUT_H2 AB1 1 2

1
H_CADIN2 G2 AA1 H_CADON2
H_CADIP1 L0_CADIN_L2 L0_CADOUT_L2 H_CADOP1 R298
E1 L0_CADIN_H1 L0_CADOUT_H1 AC2
H_CADIN1 F1 AC3 H_CADON1 10K_0402_5%
H_CADIP0 L0_CADIN_L1 L0_CADOUT_L1 H_CADOP0
H_CADIN0
E3 L0_CADIN_H0 L0_CADOUT_H0 AD1
H_CADON0
40mil JP13
E2 AC1

2
L0_CADIN_L0 L0_CADOUT_L0 +VCC_FAN1
1
<10> H_CLKIP1 J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 H_CLKOP1 <10> <33> FAN_SPEED1 2
<10> H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 <10> 3
<10> H_CLKIP0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 H_CLKOP0 <10> 1
J2 W1 C670 ACES_85205-03001
<10> H_CLKIN0 L0_CLKIN_L0 L0_CLKOUT_L0 H_CLKON0 <10>
1000P_0402_50V7K CONN@

H_CTLIP1_R P3 H_CTLOP1_R 2
<10> H_CTLIP1 1 2 L0_CTLIN_H1 L0_CTLOUT_H1 T5 1 2 H_CTLOP1 <10>
R225
1 0_0402_5%
2 H_CTLIN1_R P4 R5 H_CTLON1_R R227
1 0_0402_5%
2
<10> H_CTLIN1 L0_CTLIN_L1 L0_CTLOUT_L1 H_CTLON1 <10>
R226 0_0402_5% R250 0_0402_5%
H_CTLIP0 N1 R2 H_CTLOP0
<10> H_CTLIP0 L0_CTLIN_H0 L0_CTLOUT_H0 H_CTLOP0 <10>
H_CTLIN0 P1 R3 H_CTLON0
<10> H_CTLIN0 L0_CTLIN_L0 L0_CTLOUT_L0 H_CTLON0 <10>
FOX_PZ63823-284S-41F
CONN@
Athlon 64 S1
B Processor Socket B
+1.2V_HT
R829 2 1@ 51_0402_1% H_CTLIP1_R
R814 2 1@ 51_0402_1% H_CTLIN1_R

AMD : 49.9 1%
ATI : 51 1%

+1.2V_HT

250 mil
VLDT CAP.
1 1 1 1 1 1
C910 C911 C912 C913 C914 C915
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2

<BOM Structure> <BOM Structure>

Near CPU Socket
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/5/18 Deciphered Date 2009/06/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401728 A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 04, 2009 Sheet 4 of 49
5 4 3 2 1
 A B C D E

Processor DDR2 Memory Interface

<9> DDR_B_D[63..0]
JCPU1C
DDR_A_D[63..0] <8>
+1.8V DDR_B_D63 AD11 AA12 DDR_A_D63
4 DDR_B_D62 MB_DATA63 MA_DATA63 DDR_A_D62 4
AF11 MB_DATA62 MA_DATA62 AB12
DDR_B_D61 AF14 AA14 DDR_A_D61
MB_DATA61 MA_DATA61
2

DDR_B_D60 AE14 AB14 DDR_A_D60

R801 DDR_B_D59 MB_DATA60 MA_DATA60 DDR_A_D59
Y11 MB_DATA59 MA_DATA59 W11
1K_0402_1% DDR_B_D58 AB11 Y12 DDR_A_D58
+CPU_M_VREF DDR_B_D57 MB_DATA58 MA_DATA58 DDR_A_D57
AC12 MB_DATA57 MA_DATA57 AD13
DDR_B_D56 AF13 AB13 DDR_A_D56
1

DDR_B_D55 MB_DATA56 MA_DATA56 DDR_A_D55

AF15 MB_DATA55 MA_DATA55 AD15
1000P_0402_50V7K
0.1U_0402_16V4Z

DDR_B_D54 AF16 AB15 DDR_A_D54

MB_DATA54 MA_DATA54
2

1 1 DDR_B_D53 AC18 AB17 DDR_A_D53

MB_DATA53 MA_DATA53
C916

C917

R800 DDR_B_D52 AF19 Y17 DDR_A_D52

1K_0402_1% DDR_B_D51 MB_DATA52 MA_DATA52 DDR_A_D51
AD14 MB_DATA51 MA_DATA51 Y14
DDR_B_D50 AC14 W14 DDR_A_D50
2 2 DDR_B_D49 MB_DATA50 MA_DATA50 DDR_A_D49
AE18 W16
1

DDR_B_D48 MB_DATA49 MA_DATA49 DDR_A_D48

AD18 MB_DATA48 MA_DATA48 AD17
DDR_B_D47 AD20 Y18 DDR_A_D47
DDR_B_D46 MB_DATA47 MA_DATA47 DDR_A_D46
AC20 MB_DATA46 MA_DATA46 AD19
+CPU_M_VREF DDR_B_D45 AF23 AD21 DDR_A_D45
JCPU1B +0.9V DDR_B_D44 MB_DATA45 MA_DATA45 DDR_A_D44
AF24 MB_DATA44 MA_DATA44 AB21
DDR_B_D43 AF20 AB18 DDR_A_D43
DDR_B_D42 MB_DATA43 MA_DATA43 DDR_A_D42
W17 M_VREF VTT1 D10 AE20 MB_DATA42 MA_DATA42 AA18
C10 DDR_B_D41 AD22 AA20 DDR_A_D41
TP1 VTT_SENSE VTT2 DDR_B_D40 MB_DATA41 MA_DATA41 DDR_A_D40
Y10 VTT_SENSE VTT3 B10 AC22 MB_DATA40 MA_DATA40 Y20
AD10 DDR_B_D39 AE25 AA22 DDR_A_D39
VTT4 DDR_B_D38 MB_DATA39 MA_DATA39 DDR_A_D38
VTT5 W10 AD26 MB_DATA38 MA_DATA38 Y22
+1.8V R802 1 2 M_ZN AE10 AC10 DDR_B_D37 AA25 W21 DDR_A_D37
R803 2 M_ZN VTT6 MB_DATA37 MA_DATA37
1 39.2_0402_1% M_ZP AF10
M_ZP VTT7 AB10 DDR_B_D36 AA26 MB_DATA36 MA_DATA36 W22 DDR_A_D36
39.2_0402_1% AA10 DDR_B_D35 AE24 AA21 DDR_A_D35
VTT8 DDR_B_D34 MB_DATA35 MA_DATA35 DDR_A_D34
VTT9 A10 AD24 MB_DATA34 MA_DATA34 AB22
DDR_B_D33 AA23 AB24 DDR_A_D33
DDR_CS3_DIMMA# DDR_A_CLK2 DDR_B_D32 MB_DATA33 MA_DATA33 DDR_A_D32
V19 Y16 AA24 Y24
3
<8>
<8>
DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
DDR_CS2_DIMMA# J22
MA0_CS_L3
MA0_CS_L2
DDRII Cmd/Ctrl//Clk MA0_CLK_H2
MA0_CLK_L2 AA16 DDR_A_CLK#2
DDR_A_CLK2
DDR_A_CLK#2
<8>
<8>
DDR_B_D31 G24
MB_DATA32
MB_DATA31
MA_DATA32
MA_DATA31 H22 DDR_A_D31
3
DDR_CS1_DIMMA# V22 E16 DDR_A_CLK1 DDR_B_D30 G23 H20 DDR_A_D30
<8> DDR_CS1_DIMMA# MA0_CS_L1 MA0_CLK_H1 DDR_A_CLK1 <8> MB_DATA30 MA_DATA30
DDR_CS0_DIMMA# T19 F16 DDR_A_CLK#1 DDR_B_D29 D26 E22 DDR_A_D29
<8> DDR_CS0_DIMMA# MA0_CS_L0 MA0_CLK_L1 DDR_A_CLK#1 <8> MB_DATA29 MA_DATA29
DDR_B_D28 C26 E21 DDR_A_D28
DDR_CS3_DIMMB# DDR_B_CLK2 DDR_B_D27 MB_DATA28 MA_DATA28 DDR_A_D27
<9> DDR_CS3_DIMMB# Y26 MB0_CS_L3 MB0_CLK_H2 AF18 DDR_B_CLK2 <9> G26 MB_DATA27 MA_DATA27 J19
DDR_CS2_DIMMB# J24 AF17 DDR_B_CLK#2 DDR_B_D26 G25 H24 DDR_A_D26
<9> DDR_CS2_DIMMB# MB0_CS_L2 MB0_CLK_L2 DDR_B_CLK#2 <9> MB_DATA26 MA_DATA26
DDR_CS1_DIMMB# W24 A17 DDR_B_CLK1 DDR_B_D25 E24 F22 DDR_A_D25
<9> DDR_CS1_DIMMB# MB0_CS_L1 MB0_CLK_H1 DDR_B_CLK1 <9> MB_DATA25 MA_DATA25
DDR_CS0_DIMMB# U23 A18 DDR_B_CLK#1 DDR_B_D24 E23 F20 DDR_A_D24
<9> DDR_CS0_DIMMB# MB0_CS_L0 MB0_CLK_L1 DDR_B_CLK#1 <9> MB_DATA24 MA_DATA24

DDRII Data
DDR_B_D23 C24 C23 DDR_A_D23
DDR_CKE1_DIMMB DDR_B_ODT1 DDR_B_D22 MB_DATA23 MA_DATA23 DDR_A_D22
<9> DDR_CKE1_DIMMB H26 MB_CKE1 MB0_ODT1 W23 DDR_B_ODT1 <9> B24 MB_DATA22 MA_DATA22 B22
DDR_CKE0_DIMMB J23 W26 DDR_B_ODT0 DDR_B_D21 C20 F18 DDR_A_D21
<9> DDR_CKE0_DIMMB MB_CKE0 MB0_ODT0 DDR_B_ODT0 <9> MB_DATA21 MA_DATA21
DDR_CKE1_DIMMA J20 V20 DDR_A_ODT1 DDR_B_D20 B20 E18 DDR_A_D20
<8> DDR_CKE1_DIMMA MA_CKE1 MA0_ODT1 DDR_A_ODT1 <8> MB_DATA20 MA_DATA20
DDR_CKE0_DIMMA J21 U19 DDR_A_ODT0 DDR_B_D19 C25 E20 DDR_A_D19
<8> DDR_CKE0_DIMMA MA_CKE0 MA0_ODT0 DDR_A_ODT0 <8> MB_DATA19 MA_DATA19
DDR_B_D18 D24 D22 DDR_A_D18
<8> DDR_A_MA[15..0] DDR_B_MA[15..0] <9> MB_DATA18 MA_DATA18
DDR_A_MA15 K19 J25 DDR_B_MA15 DDR_B_D17 A21 C19 DDR_A_D17
DDR_A_MA14 MA_ADD15 MB_ADD15 DDR_B_MA14 DDR_B_D16 MB_DATA17 MA_DATA17 DDR_A_D16
K20 MA_ADD14 MB_ADD14 J26 D20 MB_DATA16 MA_DATA16 G18
DDR_A_MA13 V24 W25 DDR_B_MA13 DDR_B_D15 D18 G17 DDR_A_D15
DDR_A_MA12 MA_ADD13 MB_ADD13 DDR_B_MA12 DDR_B_D14 MB_DATA15 MA_DATA15 DDR_A_D14
K24 MA_ADD12 MB_ADD12 L23 C18 MB_DATA14 MA_DATA14 C17
DDR_A_MA11 L20 L25 DDR_B_MA11 DDR_B_D13 D14 F14 DDR_A_D13
DDR_A_MA10 MA_ADD11 MB_ADD11 DDR_B_MA10 DDR_B_D12 MB_DATA13 MA_DATA13 DDR_A_D12
R19 MA_ADD10 MB_ADD10 U25 C14 MB_DATA12 MA_DATA12 E14
DDR_A_MA9 L19 L24 DDR_B_MA9 DDR_B_D11 A20 H17 DDR_A_D11
DDR_A_MA8 MA_ADD9 MB_ADD9 DDR_B_MA8 DDR_B_D10 MB_DATA11 MA_DATA11 DDR_A_D10
L22 MA_ADD8 MB_ADD8 M26 A19 MB_DATA10 MA_DATA10 E17
DDR_A_MA7 L21 L26 DDR_B_MA7 DDR_B_D9 A16 E15 DDR_A_D9
DDR_A_MA6 MA_ADD7 MB_ADD7 DDR_B_MA6 DDR_B_D8 MB_DATA9 MA_DATA9 DDR_A_D8
M19 MA_ADD6 MB_ADD6 N23 A15 MB_DATA8 MA_DATA8 H15
DDR_A_MA5 M20 N24 DDR_B_MA5 DDR_B_D7 A13 E13 DDR_A_D7
DDR_A_MA4 MA_ADD5 MB_ADD5 DDR_B_MA4 DDR_B_D6 MB_DATA7 MA_DATA7 DDR_A_D6
M24 MA_ADD4 MB_ADD4 N25 D12 MB_DATA6 MA_DATA6 C13
DDR_A_MA3 M22 N26 DDR_B_MA3 DDR_B_D5 E11 H12 DDR_A_D5
DDR_A_MA2 MA_ADD3 MB_ADD3 DDR_B_MA2 DDR_B_D4 MB_DATA5 MA_DATA5 DDR_A_D4
N22 MA_ADD2 MB_ADD2 P24 G11 MB_DATA4 MA_DATA4 H11
DDR_A_MA1 N21 P26 DDR_B_MA1 DDR_B_D3 B14 G14 DDR_A_D3
DDR_A_MA0 MA_ADD1 MB_ADD1 DDR_B_MA0 DDR_B_D2 MB_DATA3 MA_DATA3 DDR_A_D2
R21 MA_ADD0 MB_ADD0 T24 A14 MB_DATA2 MA_DATA2 H14
DDR_B_D1 A11 F12 DDR_A_D1
DDR_A_BS#2 MB_DATA1 MA_DATA1
<8> DDR_A_BS#2 K22 MA_BANK2 MB_BANK2 K26 DDR_B_BS#2 DDR_B_BS#2 <9>
DDR_B_D0 C11 MB_DATA0 MA_DATA0 G12 DDR_A_D0
DDR_A_BS#1 R20 T26 DDR_B_BS#1
2 <8> DDR_A_BS#1 MA_BANK1 MB_BANK1 DDR_B_BS#1 <9> <9> DDR_B_DM[7..0] DDR_A_DM[7..0] <8> 2
DDR_A_BS#0 T22 U26 DDR_B_BS#0 DDR_B_DM7 AD12 Y13 DDR_A_DM7
<8> DDR_A_BS#0 MA_BANK0 MB_BANK0 DDR_B_BS#0 <9> MB_DM7 MA_DM7
DDR_B_DM6 AC16 AB16 DDR_A_DM6
DDR_A_RAS# MB_DM6 MA_DM6
<8> DDR_A_RAS# T20 MA_RAS_L MB_RAS_L U24 DDR_B_RAS# DDR_B_RAS# <9>
DDR_B_DM5 AE22 MB_DM5 MA_DM5 Y19 DDR_A_DM5
DDR_A_CAS# U20 V26 DDR_B_CAS# DDR_B_DM4 AB26 AC24 DDR_A_DM4
<8> DDR_A_CAS# MA_CAS_L MB_CAS_L DDR_B_CAS# <9> MB_DM4 MA_DM4
DDR_A_WE# U21 U22 DDR_B_WE# DDR_B_DM3 E25 F24 DDR_A_DM3
<8> DDR_A_WE# MA_WE_L MB_WE_L DDR_B_WE# <9> MB_DM3 MA_DM3
DDR_B_DM2 A22 E19 DDR_A_DM2
CONN@ FOX_PZ63823-284S-41F DDR_B_DM1 MB_DM2 MA_DM2 DDR_A_DM1
B16 MB_DM1 MA_DM1 C15
Athlon 64 S1 DDR_B_DM0 A12 E12 DDR_A_DM0
Processor MB_DM0 MA_DM0
Socket DDR_B_DQS7 AF12 W12 DDR_A_DQS7
<9> DDR_B_DQS7 MB_DQS_H7 MA_DQS_H7 DDR_A_DQS7 <8>
DDR_B_DQS#7 AE12 W13 DDR_A_DQS#7
<9> DDR_B_DQS#7 MB_DQS_L7 MA_DQS_L7 DDR_A_DQS#7 <8>
DDR_B_DQS6 AE16 Y15 DDR_A_DQS6
<9> DDR_B_DQS6 MB_DQS_H6 MA_DQS_H6 DDR_A_DQS6 <8>
DDR_B_DQS#6 AD16 W15 DDR_A_DQS#6
<9> DDR_B_DQS#6 MB_DQS_L6 MA_DQS_L6 DDR_A_DQS#6 <8>
DDR_B_DQS5 AF21 AB19 DDR_A_DQS5
<9> DDR_B_DQS5 MB_DQS_H5 MA_DQS_H5 DDR_A_DQS5 <8>
DDR_B_DQS#5 AF22 AB20 DDR_A_DQS#5
<9> DDR_B_DQS#5 MB_DQS_L5 MA_DQS_L5 DDR_A_DQS#5 <8>
PLACE CLOSE TO PROCESSOR DDR_B_DQS4 AC25 AD23 DDR_A_DQS4
<9> DDR_B_DQS4 MB_DQS_H4 MA_DQS_H4 DDR_A_DQS4 <8>
DDR_B_DQS#4 AC26 AC23 DDR_A_DQS#4
WITHIN 1.5 INCH <9> DDR_B_DQS#4
DDR_B_DQS3 MB_DQS_L4 MA_DQS_L4 DDR_A_DQS3
DDR_A_DQS#4 <8>
<9> DDR_B_DQS3 F26 MB_DQS_H3 MA_DQS_H3 G22 DDR_A_DQS3 <8>
DDR_B_DQS#3 E26 G21 DDR_A_DQS#3
<9> DDR_B_DQS#3 MB_DQS_L3 MA_DQS_L3 DDR_A_DQS#3 <8>
DDR_B_DQS2 A24 C22 DDR_A_DQS2
<9> DDR_B_DQS2 MB_DQS_H2 MA_DQS_H2 DDR_A_DQS2 <8>
DDR_A_CLK2 DDR_B_CLK2 DDR_B_DQS#2 A23 C21 DDR_A_DQS#2
<9> DDR_B_DQS#2 MB_DQS_L2 MA_DQS_L2 DDR_A_DQS#2 <8>
1 1 DDR_B_DQS1 D16 G16 DDR_A_DQS1
<9> DDR_B_DQS1 MB_DQS_H1 MA_DQS_H1 DDR_A_DQS1 <8>
DDR_B_DQS#1 C16 G15 DDR_A_DQS#1
<9> DDR_B_DQS#1 MB_DQS_L1 MA_DQS_L1 DDR_A_DQS#1 <8>
C918 C919 DDR_B_DQS0 C12 G13 DDR_A_DQS0
1.5P_0402_50V8C 1.5P_0402_50V8C <9> DDR_B_DQS0 MB_DQS_H0 MA_DQS_H0 DDR_A_DQS0 <8>
DDR_B_DQS#0 B12 H13 DDR_A_DQS#0
2 2 <9> DDR_B_DQS#0 MB_DQS_L0 MA_DQS_L0 DDR_A_DQS#0 <8>
DDR_A_CLK#2 DDR_B_CLK#2

DDR_A_CLK1 DDR_B_CLK1 CONN@ FOX_PZ63823-284S-41F

1 1 Athlon 64 S1
Processor Socket
C920 C921
1.5P_0402_50V8C 1.5P_0402_50V8C

hexainf@hotmail.com
1 DDR_A_CLK#1 2 DDR_B_CLK#1 2 1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/5/18 Deciphered Date 2009/06/11 Title
SCHEMATICS,MB A5401
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401728 A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 04, 2009 Sheet 5 of 49
A B C D E
 5 4 3 2 1

+1.8VS

A:Need to re-Link "SGN00000200"

2
R339 +2.5VDDA +1.8V
VDDA=300mA
300_0402_5% L91
+2.5VS 1 2 3300P_0402_50V7K

1
1 FCM2012CF-800T06_2P

1
LDT_RST# 1 1 1
<24> LDT_RST# + C391 R830
1 150U_B2_6.3VM C923 C924 C925 300_0402_5%
C721 0.22U_0603_16V4Z +1.8V

2
0.01U_0402_25V4Z 2 2 2 2
D @ 4.7U_0805_10V4Z JCPU1D VID1: For compatibility D
2 CPU_THERMTRIP#_R CPU_VID1 with future processors
F8 VDDA2 THERMTRIP_L AF6 1 2
F9 AC7 CPU_PROCHOT#_1.8 1 R372 2 R805 300_0402_5%
VDDA1 PROCHOT_L H_PROCHOT_R# <24>
0_0402_5% CPU_PRESENT# 1 2
LDT_RST# B7 R806 1K_0402_5%
H_PWRGD RESET_L CPU_TEST26_BURNIN#
A7 PWROK 1 2
+1.8VS LDT_STOP# F10 R807 300_0402_5%
LDTSTOP_L
VID5 A5 CPU_VID5 <46>
2 1 CPU_SIC AF4 C6
SIC VID4 CPU_VID4 <46>
2

R808 300_0402_5% AF5 A6 CPU_TEST21_SCANEN 1 2

SID VID3 CPU_VID3 <46>
R338 A4 R809 300_0402_5%
VID2 CPU_VID2 <46>
300_0402_5% +1.2V_HT R811 1 2 44.2_0402_1% CPU_HTREF1 P6 C5
HTREF1 VID1 CPU_VID1 <46>
R812 1 2 44.2_0402_1% CPU_HTREF0 R6 B5
HTREF0 VID0 CPU_VID0 <46>
1

H_PWRGD R61&R16 close to CPU within 1" AC6 CPU_PRESENT#

<24> H_PWRGD CPU_PRESENT_L
<46> CPU_VCC_SENSE F6 VDD_FB_H
1 <46> CPU_VSS_SENSE E6 VDD_FB_L PSI_L A3 PSI_L <46>
C720 +1.8V
TP2
0.01U_0402_25V4Z W9
@ TP3 VDDIO_FB_H CPU_TEST25_H_BYPASSCLK_H
Y9 VDDIO_FB_L 2 1
2 R813 510_0402_5%
<20> CLK_CPU_BCLK 1 2 3900P_0402_50V7K CPU_CLKIN_SC_P A9 CLKIN_H
C926 CPU_CLKIN_SC_N A8 2 1 CPU_TEST25_L_BYPASSCLK_L
CLKIN_L

1
R815 510_0402_5%
CPU_DBRDY G10 E10 CPU_DBREQ# 2 1 CPU_TEST19_PLLTEST0
+1.8VS R816 DBRDY DBREQ_L R817 300_0402_5%
169_0402_1% CPU_TMS AA9 2 1 CPU_TEST18_PLLTEST1
CPU_TCK TMS CPU_TDO R818 300_0402_5%
AC9 AE9

2
TCK TDO
2

1 2 CPU_TRST# AD9
<20> CLK_CPU_BCLK# TRST_L
R337 C927 3900P_0402_50V7K CPU_TDI AF9 R819
TDI 80.6_0402_1%
300_0402_5%
CPU_TEST25_H_BYPASSCLK_H E9 C9 CPU_TEST29_H_FBCLKOUT_P 1 2
C CPU_TEST25_L_BYPASSCLK_L TEST25_H TEST29_H CPU_TEST29_L_FBCLKOUT_N C
E8 C8
1

LDT_STOP# CPU_TEST19_PLLTEST0 TEST25_L TEST29_L

<11,24> LDT_STOP# G9 TEST19
CPU_TEST18_PLLTEST1 H10 ROUTE AS 80 Ohm DIFFERENTIAL PAIR
TEST18

MISC
1 AA7 TEST13 PLACE IT CLOSE TO CPU WITHIN 1"
C719 C2
0.01U_0402_25V4Z TP4 TEST9 TP5
D7 TEST17 TEST24 AE7
@ TP6 E7 AD7 TP7
2 TP8 TEST16 TEST23 TP9
F7 TEST15 TEST22 AE8
TP10 C7 AB8 CPU_TEST21_SCANEN
TP11 TEST14 TEST21 TP12
AC8 TEST12 TEST20 AF7

+3VS C3 J7
C928 TEST7 TEST28_H
AA6 TEST6 TEST28_L H8
0.1U_0402_16V4Z CPU_THERMDC W7 AF8
CPU_THERMDA THERMDC TEST27 CPU_TEST26_BURNIN#
1 2 W8 THERMDA TEST26 AE6
Y6 TEST3 TEST10 K8
AB6 TEST2 TEST8 C4

P20 RSVD0 RSVD8 H16

1 U55 P19 B18
C929 RSVD1 RSVD9
1 VDD SCLK 8 EC_SMB_CK2 <19,33> N20 RSVD2
N19 RSVD3 RSVD10 B3
2200P_0402_50V7K CPU_THERMDA 2 7 C1
2 D+ SDATA EC_SMB_DA2 <19,33> RSVD11
CPU_THERMDC 3 6 H6
D- ALERT# RSVD12 +1.8V
RSVD13 G6
4 5 D5 +3VALW
THERM# GND RSVD14

1
R24 +1.8V +3VALW
RSVD15

1
ADM1032ARMZ-2REEL_MSOP8 W18 R820
RSVD16 R821
R26 RSVD4 RSVD17 R23

1
F75383M_MSOP8 R25 AA8 1K_0402_5% @ 1K_0402_5%
B RSVD5 RSVD18 R822 R823 B
P22 H18

2
RSVD6 RSVD19
SMBus Address: 1001110X (b) R22 H19

2 2
RSVD7 RSVD20 300_0402_5% 10K_0402_5%

2
B

B
Q70

2
FOX_PZ63823-284S-41F Q69 MMBT3904_NL_SOT23-3

E
CONN@ CPU_THERMTRIP#_R 3 1H_THERMTRIP# 3 1 MAINPWON <42,45>

C
@
MMBT3904_NL_SOT23-3

H_THERMTRIP# <25>

AMD: suggest DBREQ need pull high

+1.8V
@ 220_0402_5%R824

@ 220_0402_5%R825

@ 220_0402_5%R826

@ 220_0402_5%R827

220_0402_5%R828

HDT Connector
1

JP18
1 2
2

3 4
CPU_DBREQ#
5 6
CPU_DBRDY 7 8
CPU_TCK
9 10
CPU_TMS 11 12 +3VS
CPU_TDI
13 14
CPU_TRST#
15 16
17 18
5

CPU_TDO
A 19 20 LDT_RST# A
2
P

21 22 HDT_RST# B
23 24 4 Y
26 A 1 SB_PWRGD <25,35>
G

NOTE: HDT TERMINATION IS REQUIRED

@ U56
@U56
FOR REV. Ax SILICON ONLY.
3

@ SAMTEC_ASP-68200-07 NC7SZ08P5X_NL_SC70-5

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/5/18 Deciphered Date 2009/06/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401728 A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 04, 2009 Sheet 6 of 49
5 4 3 2 1
 5 4 3 2 1

JCPU1F
AA4 VSS1 VSS66 J6
+CPU_CORE +CPU_CORE AA11 J8
JCPU1E VSS2 VSS67
AA13 J10
VDD(+CPU_CORE) decoupling. AC4
AD2
VDD1
VDD2
VDD43
VDD44
V12
V14
AA15
AA17
VSS3
VSS4
VSS5
VSS68
VSS69
VSS70
J12
J14
G4 VDD3 VDD45 W4 AA19 VSS6 VSS71 J16
H2 VDD4 VDD46 Y2 AB2 VSS7 VSS72 J18
+CPU_CORE J9 J15 AB7 K2
D VDD5 VDD47 VSS8 VSS73 D
J11 VDD6 VDD48 K16 AB9 VSS9 VSS74 K7
J13 VDD7 VDD49 L15 AB23 VSS10 VSS75 K9
K6 VDD8 VDD50 M16 AB25 VSS11 VSS76 K11
1 1 1 1 K10 VDD9 VDD51 P16 AC11 VSS12 VSS77 K13
K12 VDD10 VDD52 T16 AC13 VSS13 VSS78 K15
+ C931 + C930 + C934 + C935 K14 U15 AC15 K17
330U_D2E_2.5VM_R9M 330U_D2E_2.5VM_R9M 330U_D2E_2.5VM_R9M 330U_D2E_2.5VM_R9M VDD11 VDD53 VSS14 VSS79
L4 VDD12 VDD54 V16 AC17 VSS15 VSS80 L6
L7 +1.8V AC19 L8
2 2 2 2 VDD13 VSS16 VSS81
L9 VDD14 AC21 VSS17 VSS82 L10
L11 VDD15 VDDIO1 H25 AD6 VSS18 VSS83 L12
L13 J17 AD8 L14
Near CPU Socket M2
VDD16
VDD17
VDDIO2
VDDIO3 K18 AD25
VSS19
VSS20
VSS84
VSS85 L16
M6 VDD18 VDDIO4 K21 AE11 VSS21 VSS86 L18
M8 VDD19 VDDIO5 K23 AE13 VSS22 VSS87 M7
+CPU_CORE

Power
M10 VDD20 VDDIO6 K25 AE15 VSS23 VSS88 M9
N7 VDD21 VDDIO7 L17 AE17 VSS24 VSS89 M11
N9 VDD22 VDDIO8 M18 AE19 VSS25 VSS90 M17
N11 VDD23 VDDIO9 M21 AE21 VSS26 VSS91 N4
1 1 1 1 1 1 1 1 1 P8 VDD24 VDDIO10 M23 AE23 VSS27 VSS92 N8
C936 C937 C938 C939 C940 C941 C942 C943 C944 P10 M25 B4 N10
VDD25 VDDIO11 VSS28 VSS93
R4 VDD26 VDDIO12 N17 B6 VSS29 VSS94 N16
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M R7 P18 B8 N18
2 2 2 2 2 2 2 2 2 VDD27 VDDIO13 VSS30 VSS95

Ground
R9 VDD28 VDDIO14 P21 B9 VSS31 VSS96 P2
R11 VDD29 VDDIO15 P23 B11 VSS32 VSS97 P7
T2 VDD30 VDDIO16 P25 B13 VSS33 VSS98 P9
+CPU_CORE +CPU_CORE +CPU_CORE T6 R17 B15 P11
VDD31 VDDIO17 VSS34 VSS99
T8 VDD32 VDDIO18 T18 B17 VSS35 VSS100 P17
T10 VDD33 VDDIO19 T21 B19 VSS36 VSS101 R8
T12 VDD34 VDDIO20 T23 B21 VSS37 VSS102 R10
1 1 1 1 T14 VDD35 VDDIO21 T25 B23 VSS38 VSS103 R16
C945 C946 C947 C948 U7 U17 B25 R18
0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.01U_0402_25V7K 180P_0402_50V8J VDD36 VDDIO22 VSS39 VSS104
U9 VDD37 VDDIO23 V18 D6 VSS40 VSS105 T7
C C
U11 VDD38 VDDIO24 V21 D8 VSS41 VSS106 T9
2 2 2 2
U13 V23 D9 T11
Under CPU Socket V6
VDD39
VDD40
VDDIO25
VDDIO26 V25 D11
VSS42
VSS43
VSS107
VSS108 T13
V8 VDD41 VDDIO27 Y25 D13 VSS44 VSS109 T15
V10 VDD42 D15 VSS45 VSS110 T17
D17 VSS46 VSS111 U4
D19 VSS47 VSS112 U6
FOX_PZ63823-284S-41F D21 VSS48 VSS113 U8
CONN@ D23 U10
VDDIO decoupling. Athlon 64 S1
Processor Socket
D25
E4
VSS49
VSS50
VSS51
VSS114
VSS115
VSS116
U12
U14
F2 VSS52 VSS117 U16
F11 VSS53 VSS118 U18
F13 VSS54 VSS119 V2
+1.8V F15 V7
+1.8V VSS55 VSS120
F17 VSS56 VSS121 V9
F19 VSS57 VSS122 V11
F21 VSS58 VSS123 V13
1 1 1 1 F23 VSS59 VSS124 V15
C949 C950 C951 C952 F25 V17
22U_0805_6.3V6M 22U_0805_6.3V6M 0.22U_0603_16V4Z 0.22U_0603_16V4Z VSS60 VSS125
H7 VSS61 VSS126 W6
H9 VSS62 VSS127 Y21
2 2 2 2
H21 VSS63 VSS128 Y23
H23 VSS64 VSS129 N6
J4 VSS65
FOX_PZ63823-284S-41F
Under CPU Socket CONN@
Athlon 64 S1
+0.9V Processor Socket
Near Power Supply
B VTT decoupling. 1
+
C: Change to NBO CAP
C392
B

Between CPU Socket and DIMM 150U_B2_6.3VM

+1.8V
2

1 1 1 1
C954 C955 C956 C957
0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z +0.9V
2 2 2 2

1 1 1 1 1 1 1 1
180PF Qt'y follow the distance between C958 C959 C960 C961 C962 C963 C964 C965
+1.8V +1.8V CPU socket and DIMM0. <2.5inch> 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_50V7K 1000P_0402_50V7K 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2 2 2
1 1 1 1 1 1
C966 C967 C968 C969 C970 C971
0.01U_0402_25V7K 0.01U_0402_25V7K 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2
Near CPU Socket Right side.
+0.9V

+1.8V 1 1 1 1 1 1 1 1
C972 C973 C974 C975 C976 C977 C978 C979
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_50V7K 1000P_0402_50V7K 180P_0402_50V8J 180P_0402_50V8J
1 2 2 2 2 2 2 2 2
1 1 1 1
+ C536
C980 C981 C982 C983 220U_B2_2.5VM_R35

hexainf@hotmail.com
A 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z A
2 2 2 2 2 Near CPU Socket Left side.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/5/18 Deciphered Date 2009/06/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401728 A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 04, 2009 Sheet 7 of 49
5 4 3 2 1
 5 4 3 2 1

+1.8V +DIMM_VREF +1.8V

1
+1.8V +1.8V

0.1U_0402_16V4Z
R832 +0.9V
JDIMM1 C986 RP24
1 2 1 1 DDR_A_MA11 8 1 1 2
VREF VSS DDR_A_D4 1K_0402_1% DDR_A_MA7 C985 0.1U_0402_16V4Z
3 VSS DQ4 4 7 2

C987
4.7U_0805_10V4Z
DDR_A_D0 5 6 DDR_A_D5 DDR_A_MA6 6 3 1 2

2
DDR_A_D1 DQ0 DQ5 DDR_A_MA4 C988 0.1U_0402_16V4Z
7 DQ1 VSS 8 5 4
DDR_A_DM0 2 2 <BOM Structure>
9 VSS DM0 10
D DDR_A_DQS#0 47_0804_8P4R_5% D
11 DQS0# VSS 12
DDR_A_DQS0 13 14 DDR_A_D6 RP25
DQS0 DQ6

1
15 16 DDR_A_D7 R833 DDR_A_MA12 8 1 1 2
DDR_A_D2 VSS DQ7 DDR_A_BS#2 C989 0.1U_0402_16V4Z
17 DQ2 VSS 18 7 2
DDR_A_D3 19 20 DDR_A_D12 DDR_CS2_DIMMA# 6 3 1 2
DQ3 DQ12 DDR_A_D13 1K_0402_1% DDR_CKE0_DIMMA C990 0.1U_0402_16V4Z
21 VSS DQ13 22 5 4
DDR_A_D8 23 24 <BOM Structure>

2
DDR_A_D9 DQ8 VSS DDR_A_DM1 47_0804_8P4R_5%
25 DQ9 DM1 26 <BOM Structure>
27 28 RP26
DDR_A_DQS#1 VSS VSS DDR_A_CLK1 DDR_A_MA2
29 DQS1# CK0 30 DDR_A_CLK1 <5> 8 1 1 2
DDR_A_DQS1 31 32 DDR_A_CLK#1 DDR_A_MA0 7 2 C991 0.1U_0402_16V4Z
DQS1 CK0# DDR_A_CLK#1 <5>
33 34 DDR_A_BS#1 6 3 1 2
DDR_A_D10 VSS VSS DDR_A_D14 DDR_CS0_DIMMA# C992 0.1U_0402_16V4Z
35 DQ10 DQ14 36 5 4
DDR_A_D11 37 38 DDR_A_D15 <BOM Structure>
DQ11 DQ15 47_0804_8P4R_5%
39 VSS VSS 40 <BOM Structure>
RP27
DDR_A_MA5 8 1 1 2
41 42 DDR_A_MA8 7 2 C993 0.1U_0402_16V4Z
DDR_A_D16 VSS VSS DDR_A_D20 DDR_A_MA9
43 DQ16 DQ20 44 6 3 1 2
DDR_A_D17 45 46 DDR_A_D21 DDR_A_D[0..63] 5 4 C994 0.1U_0402_16V4Z
DQ17 DQ21 <5> DDR_A_D[0..63]
47 VSS VSS 48
DDR_A_DQS#2 49 50 DDR_A_DM[0..7] 47_0804_8P4R_5% <BOM Structure>
DQS2# NC <5> DDR_A_DM[0..7]
DDR_A_DQS2 51 52 DDR_A_DM2 RP28
DQS2 DM2 DDR_A_DQS[0..7] DDR_A_BS#0
53 VSS VSS 54 <5> DDR_A_DQS[0..7] 8 1 1 2
DDR_A_D18 55 56 DDR_A_D22 DDR_A_MA10 7 2 C995 0.1U_0402_16V4Z
DDR_A_D19 DQ18 DQ22 DDR_A_D23 DDR_A_MA[0..15] DDR_A_MA1
57 DQ19 DQ23 58 <5> DDR_A_MA[0..15] 6 3 1 2
59 60 DDR_A_MA3 5 4 C996 0.1U_0402_16V4Z
DDR_A_D24 VSS VSS DDR_A_D28 DDR_A_DQS#[0..7]
61 DQ24 DQ28 62 <5> DDR_A_DQS#[0..7]
DDR_A_D25 63 64 DDR_A_D29 47_0804_8P4R_5%
DQ25 DQ29 RP29
65 VSS VSS 66
C DDR_A_DM3 DDR_A_DQS#3 DDR_A_ODT1 C
67 DM3 DQS3# 68 8 1 1 2
69 70 DDR_A_DQS3 DDR_CS1_DIMMA# 7 2 C998 0.1U_0402_16V4Z
NC DQS3 DDR_A_CAS#
71 VSS VSS 72 6 3 1 2
DDR_A_D26 73 74 DDR_A_D30 DDR_A_WE# 5 4 C997 0.1U_0402_16V4Z
DDR_A_D27 DQ26 DQ30 DDR_A_D31
75 DQ27 DQ31 76
77 78 47_0804_8P4R_5%
DDR_CKE0_DIMMA VSS VSS DDR_CKE1_DIMMA RP30
<5> DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA <5>
81 82 DDR_A_RAS# 8 1 1 2
DDR_CS2_DIMMA# VDD VDD DDR_A_MA15 DDR_A_ODT0 C999 0.1U_0402_16V4Z
<5> DDR_CS2_DIMMA# 83 NC NC/A15 84 7 2
DDR_A_BS#2 85 86 DDR_A_MA14 DDR_A_MA13 6 3 1 2
<5> DDR_A_BS#2 BA2 NC/A14
87 88 DDR_CS3_DIMMA# 5 4 C1000 0.1U_0402_16V4Z
DDR_A_MA12 VDD VDD DDR_A_MA11
89 A12 A11 90
DDR_A_MA9 91 92 DDR_A_MA7 47_0804_8P4R_5%
DDR_A_MA8 A9 A7 DDR_A_MA6 RP31
93 A8 A6 94
95 VDD VDD 96 8 1 1 2
DDR_A_MA5 97 98 DDR_A_MA4 DDR_CKE1_DIMMA 7 2 C1002 0.1U_0402_16V4Z
DDR_A_MA3 A5 A4 DDR_A_MA2 DDR_A_MA15
99 A3 A2 100 6 3 1 2
DDR_A_MA1 101 102 DDR_A_MA0 DDR_A_MA14 5 4 C1001 0.1U_0402_16V4Z
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1 47_0804_8P4R_5%
A10/AP BA1 DDR_A_BS#1 <5>
DDR_A_BS#0 107 108 DDR_A_RAS#
<5> DDR_A_BS#0 BA0 RAS# DDR_A_RAS# <5>
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
<5> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <5>
111 VDD VDD 112
DDR_A_CAS# 113 114 DDR_A_ODT0
<5> DDR_A_CAS# CAS# ODT0 DDR_A_ODT0 <5>
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
<5> DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
DDR_A_ODT1 119 120 DDR_CS3_DIMMA#
<5> DDR_A_ODT1 NC/ODT1 NC DDR_CS3_DIMMA# <5>
121 VSS VSS 122
DDR_A_D32 123 124 DDR_A_D36
DDR_A_D33 DQ32 DQ36 DDR_A_D37
125 DQ33 DQ37 126
B B
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_A_D38
DDR_A_D34 VSS DQ38 DDR_A_D39
135 DQ34 DQ39 136
DDR_A_D35 137 138
DQ35 VSS DDR_A_D44
139 VSS DQ44 140
DDR_A_D40 141 142 DDR_A_D45
DDR_A_D41 DQ40 DQ45
143 DQ41 VSS 144
145 146 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 DM5 DQS5 148
149 VSS VSS 150
DDR_A_D42 151 152 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D48 157 158 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 DDR_A_CLK2
NC,TEST CK1 DDR_A_CLK2 <5>
165 166 DDR_A_CLK#2
VSS CK1# DDR_A_CLK#2 <5>
DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
171 VSS VSS 172
DDR_A_D50 173 174 DDR_A_D54
DDR_A_D51 DQ50 DQ54 DDR_A_D55
175 DQ51 DQ55 176
177 VSS VSS 178
DDR_A_D56 179 180 DDR_A_D60
DDR_A_D57 DQ56 DQ60 DDR_A_D61
181 DQ57 DQ61 182
183 VSS VSS 184
DDR_A_DM7 185 186 DDR_A_DQS#7
A DM7 DQS7# DDR_A_DQS7 A
187 VSS DQS7 188
DDR_A_D58 189 190
DDR_A_D59 DQ58 VSS DDR_A_D62
191 DQ59 DQ62 192
193 194 DDR_A_D63
SB_CK_SDAT VSS DQ63
<9,20,25,31> SB_CK_SDAT 195 SDA VSS 196
SB_CK_SCLK 197 198 R834 1 2 10K_0402_5%
<9,20,25,31> SB_CK_SCLK SCL SAO
199 200 R835 1 2 10K_0402_5%
+3VS
1
C1003
203
VDDSPD
GND
SA1
GND 204
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/5/18 Deciphered Date 2009/06/11 Title
FOX_AS0A426-M2RN-7F
2
0.1U_0402_16V4Z CONN@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
Size Document Number Rev
JAWD0 used AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom A
401728
DIMM1 REV H:5.2mm (BOT) MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 04, 2009 Sheet 8 of 49
5 4 3 2 1
 5 4 3 2 1

+1.8V +DIMM_VREF

+0.9V +1.8V
RP32
+1.8V

0.1U_0402_16V4Z
DDR_CS0_DIMMB# 8 1 2 1

4.7U_0805_10V4Z

C1006

C1007
JDIMM2 DDR_B_BS#1 7 2 C1005 0.1U_0402_16V4Z
1 2 1 1 DDR_B_MA2 6 3 1 2
VREF VSS DDR_B_D4 DDR_B_MA0 C1004 0.1U_0402_16V4Z
3 VSS DQ4 4 5 4
DDR_B_D0 5 6 DDR_B_D5
DDR_B_D1 DQ0 DQ5 47_0804_8P4R_5%
7 DQ1 VSS 8
DDR_B_DM0 2 2
9 VSS DM0 10
DDR_B_DQS#0 11 12 RP33
D DDR_B_DQS0 DQS0# VSS DDR_B_D6 DDR_B_MA6 D
13 DQS0 DQ6 14 8 1 2 1
15 16 DDR_B_D7 DDR_B_MA4 7 2 C1009 0.1U_0402_16V4Z
DDR_B_D2 VSS DQ7 DDR_B_MA11
17 DQ2 VSS 18 6 3 1 2 Structure>
<BOM
DDR_B_D3 19 20 DDR_B_D12 DDR_B_MA7 5 4 C1008 0.1U_0402_16V4Z
DQ3 DQ12 DDR_B_D13
21 VSS DQ13 22 <BOM Structure>
DDR_B_D8 23 24 47_0804_8P4R_5%
DDR_B_D9 DQ8 VSS DDR_B_DM1
25 DQ9 DM1 26
27 28 RP34
DDR_B_DQS#1 VSS VSS DDR_B_CLK1
29 DQS1# CK0 30 DDR_B_CLK1 <5> 8 1 2 1
DDR_B_DQS1 31 32 DDR_B_CLK#1 DDR_CS2_DIMMB# 7 2 C1011 0.1U_0402_16V4Z
DQS1 CK0# DDR_B_CLK#1 <5>
33 34 DDR_B_BS#2 6 3 1 2 Structure>
<BOM
DDR_B_D10 VSS VSS DDR_B_D14 DDR_CKE0_DIMMB C1010 0.1U_0402_16V4Z
35 DQ10 DQ14 36 5 4
DDR_B_D11 37 38 DDR_B_D15 <BOM Structure>
DQ11 DQ15 47_0804_8P4R_5%
39 VSS VSS 40

RP35
41 42 DDR_B_MA5 8 1 2 1
DDR_B_D16 VSS VSS DDR_B_D20 DDR_B_MA8 C1013 0.1U_0402_16V4Z
43 DQ16 DQ20 44 7 2
DDR_B_D17 45 46 DDR_B_D21 DDR_B_MA9 6 3 1 2 Structure>
<BOM
DQ17 DQ21 DDR_B_MA12 C1012 0.1U_0402_16V4Z
47 VSS VSS 48 5 4
DDR_B_DQS#2 49 50 <BOM Structure>
DDR_B_DQS2 DQS2# NC DDR_B_DM2 DDR_B_D[0..63] 47_0804_8P4R_5%
51 DQS2 DM2 52 <5> DDR_B_D[0..63]
53 VSS VSS 54
DDR_B_D18 55 56 DDR_B_D22 DDR_B_DM[0..7] RP36
DQ18 DQ22 <5> DDR_B_DM[0..7]
DDR_B_D19 57 58 DDR_B_D23 DDR_B_BS#0 8 1 2 1
DQ19 DQ23 DDR_B_DQS[0..7] DDR_B_MA10 C1014 0.1U_0402_16V4Z
59 VSS VSS 60 <5> DDR_B_DQS[0..7] 7 2
DDR_B_D24 61 62 DDR_B_D28 DDR_B_MA1 6 3 1 2
DDR_B_D25 DQ24 DQ28 DDR_B_D29 DDR_B_MA[0..15] DDR_B_MA3 C1015 0.1U_0402_16V4Z
63 DQ25 DQ29 64 <5> DDR_B_MA[0..15] 5 4
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3 DDR_B_DQS#[0..7] 47_0804_8P4R_5%
DM3 DQS3# DDR_B_DQS3 <5> DDR_B_DQS#[0..7]
69 NC DQS3 70
71 72 RP37
C DDR_B_D26 VSS VSS DDR_B_D30 DDR_B_ODT1 C
73 DQ26 DQ30 74 8 1 2 1
DDR_B_D27 75 76 DDR_B_D31 DDR_CS1_DIMMB# 7 2 C1016 0.1U_0402_16V4Z
DQ27 DQ31 DDR_B_CAS#
77 VSS VSS 78 6 3 1 2
DDR_CKE0_DIMMB 79 80 DDR_CKE1_DIMMB DDR_B_WE# 5 4 C1017 0.1U_0402_16V4Z
<5> DDR_CKE0_DIMMB CKE0 NC/CKE1 DDR_CKE1_DIMMB <5>
81 VDD VDD 82
DDR_CS2_DIMMB# 83 84 DDR_B_MA15 47_0804_8P4R_5%
<5> DDR_CS2_DIMMB# NC NC/A15
DDR_B_BS#2 85 86 DDR_B_MA14
<5> DDR_B_BS#2 BA2 NC/A14
87 88 RP38
DDR_B_MA12 VDD VDD DDR_B_MA11 DDR_B_ODT0
89 A12 A11 90 8 1 2 1
DDR_B_MA9 91 92 DDR_B_MA7 DDR_B_MA13 7 2 C1018 0.1U_0402_16V4Z
DDR_B_MA8 A9 A7 DDR_B_MA6 DDR_CS3_DIMMB#
93 A8 A6 94 6 3 1 2
95 96 DDR_B_RAS# 5 4 C1019 0.1U_0402_16V4Z
DDR_B_MA5 VDD VDD DDR_B_MA4
97 A5 A4 98
DDR_B_MA3 99 100 DDR_B_MA2 47_0804_8P4R_5%
DDR_B_MA1 A3 A2 DDR_B_MA0
101 A1 A0 102
103 104 RP39
DDR_B_MA10 VDD VDD DDR_B_BS#1 DDR_B_MA14
105 A10/AP BA1 106 DDR_B_BS#1 <5> 8 1 2 1
DDR_B_BS#0 107 108 DDR_B_RAS# DDR_B_MA15 7 2 C1020 0.1U_0402_16V4Z
<5> DDR_B_BS#0 BA0 RAS# DDR_B_RAS# <5>
DDR_B_WE# 109 110 DDR_CS0_DIMMB# DDR_CKE1_DIMMB 6 3 1 2
<5> DDR_B_WE# WE# S0# DDR_CS0_DIMMB# <5>
111 112 5 4 C1021 0.1U_0402_16V4Z
DDR_B_CAS# VDD VDD DDR_B_ODT0
<5> DDR_B_CAS# 113 CAS# ODT0 114 DDR_B_ODT0 <5>
DDR_CS1_DIMMB# 115 116 DDR_B_MA13 47_0804_8P4R_5%
<5> DDR_CS1_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
DDR_B_ODT1 119 120 DDR_CS3_DIMMB#
<5> DDR_B_ODT1 NC/ODT1 NC DDR_CS3_DIMMB# <5>
121 VSS VSS 122
DDR_B_D32 123 124 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_B_DQS#4 129 130 DDR_B_DM4
DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_B_D38
DDR_B_D34 VSS DQ38 DDR_B_D39
135 DQ34 DQ39 136
B DDR_B_D35 B
137 DQ35 VSS 138
139 140 DDR_B_D44
DDR_B_D40 VSS DQ44 DDR_B_D45
141 DQ40 DQ45 142
DDR_B_D41 143 144
DQ41 VSS DDR_B_DQS#5
145 VSS DQS5# 146
DDR_B_DM5 147 148 DDR_B_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 DDR_B_CLK2
NC,TEST CK1 DDR_B_CLK2 <5>
165 166 DDR_B_CLK#2
VSS CK1# DDR_B_CLK#2 <5>
DDR_B_DQS#6 167 168
DDR_B_DQS6 DQS6# VSS DDR_B_DM6
169 DQS6 DM6 170
171 VSS VSS 172
DDR_B_D50 173 174 DDR_B_D54
DDR_B_D51 DQ50 DQ54 DDR_B_D55
175 DQ51 DQ55 176
177 VSS VSS 178
DDR_B_D56 179 180 DDR_B_D60
DDR_B_D57 DQ56 DQ60 DDR_B_D61
181 DQ57 DQ61 182
183 VSS VSS 184
DDR_B_DM7 185 186 DDR_B_DQS#7
DM7 DQS7# DDR_B_DQS7
187 VSS DQS7 188
DDR_B_D58 189 190
DDR_B_D59 DQ58 VSS DDR_B_D62
191 DQ59 DQ62 192
193 194 DDR_B_D63
SB_CK_SDAT VSS DQ63
<8,20,25,31> SB_CK_SDAT 195 SDA VSS 196
SB_CK_SCLK 197 198 R836 1 2 10K_0402_5% +3VS
<8,20,25,31> SB_CK_SCLK SCL SAO
+3VS 199 200 R837 1 2 10K_0402_5%

hexainf@hotmail.com
A VDDSPD SA1 A
1
C1022
P-TWO_A5652C-A0G16
0.1U_0402_16V4Z CONN@
2
KAV10 used
DIMM2 H:5.2mm (BOT) Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/5/18 Deciphered Date 2009/06/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401728 A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 04, 2009 Sheet 9 of 49

5 4 3 2 1
 A B C D E

PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P[0..15] PCIE_MTX_GRX_N[0..3]

<14> PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P[0..15] <14> PCIE_MTX_GRX_N[0..3] <22>
PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_N[0..15] PCIE_MTX_GRX_P[0..3]
<14> PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_N[0..15] <14> PCIE_MTX_GRX_P[0..3] <22>

U3B
PCIE_GTX_C_MRX_P0 D4 A5 PCIE_MTX_GRX_P0 C647 1 2 @ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
PCIE_GTX_C_MRX_N0 GFX_RX0P GFX_TX0P PCIE_MTX_GRX_N0 C646 1 PCIE_MTX_C_GRX_N0
C4 GFX_RX0N PART 2 OF 6 GFX_TX0N B5 2 @ 0.1U_0402_16V7K
PCIE_GTX_C_MRX_P1 A3 A4 PCIE_MTX_GRX_P1 C649 1 2 @ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
PCIE_GTX_C_MRX_N1 GFX_RX1P GFX_TX1P PCIE_MTX_GRX_N1 C648 1 @ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N1
B3 GFX_RX1N GFX_TX1N B4 2
1 PCIE_GTX_C_MRX_P2 PCIE_MTX_GRX_P2 C651 1 @ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2 1
C2 GFX_RX2P GFX_TX2P C3 2
PCIE_GTX_C_MRX_N2 C1 B2 PCIE_MTX_GRX_N2 C650 1 2 @ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
PCIE_GTX_C_MRX_P3 GFX_RX2N GFX_TX2N PCIE_MTX_GRX_P3 C653 1 @ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3
E5 GFX_RX3P GFX_TX3P D1 2 For M92 S2-LP
PCIE_GTX_C_MRX_N3 F5 D2 PCIE_MTX_GRX_N3 C652 1 2 @ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N3
PCIE_GTX_C_MRX_P4 G5
GFX_RX3N GFX_TX3N
E2 PCIE_MTX_GRX_P4 C654 1 2 @ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4 disable PCIE GFX 0~7
PCIE_GTX_C_MRX_N4 GFX_RX4P GFX_TX4P PCIE_MTX_GRX_N4 C655 1 @ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4
G6 GFX_RX4N GFX_TX4N E1 2
PCIE_GTX_C_MRX_P5 H5 F4 PCIE_MTX_GRX_P5 C656 1 2 @ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P5
PCIE_GTX_C_MRX_N5 GFX_RX5P GFX_TX5P PCIE_MTX_GRX_N5 C657 1 @ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N5
H6 GFX_RX5N GFX_TX5N F3 2
PCIE_GTX_C_MRX_P6 J6 F1 PCIE_MTX_GRX_P6 C658 1 2 @ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
PCIE_GTX_C_MRX_N6 GFX_RX6P GFX_TX6P PCIE_MTX_GRX_N6 C659 1 @ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6
J5 GFX_RX6N GFX_TX6N F2 2
PCIE_GTX_C_MRX_P7 J7 H4 PCIE_MTX_GRX_P7 C642 1 2 @ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P7
PCIE_GTX_C_MRX_N7 GFX_RX7P GFX_TX7P PCIE_MTX_GRX_N7 C641 1 @ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N7
J8 GFX_RX7N GFX_TX7N H3 2
PCIE_GTX_C_MRX_P8 L5 H1 PCIE_MTX_GRX_P8 C638 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
PCIE_GTX_C_MRX_N8 GFX_RX8P GFX_TX8P PCIE_MTX_GRX_N8 C636 1 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8
L6 GFX_RX8N GFX_TX8N H2 2
PCIE_GTX_C_MRX_P9 M8 J2 PCIE_MTX_GRX_P9 C637 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
PCIE_GTX_C_MRX_N9 GFX_RX9P GFX_TX9P PCIE_MTX_GRX_N9 C635 1 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N9
L8 GFX_RX9N GFX_TX9N J1 2

PCIE I/F GFX

PCIE_GTX_C_MRX_P10 P7 K4 PCIE_MTX_GRX_P10 C634 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
PCIE_GTX_C_MRX_N10 GFX_RX10P GFX_TX10P PCIE_MTX_GRX_N10 C632 1 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10
M7 GFX_RX10N GFX_TX10N K3 2
PCIE_GTX_C_MRX_P11 P5 K1 PCIE_MTX_GRX_P11 C631 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11
PCIE_GTX_C_MRX_N11 GFX_RX11P GFX_TX11P PCIE_MTX_GRX_N11 C630 1 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N11
M5 GFX_RX11N GFX_TX11N K2 2
PCIE_GTX_C_MRX_P12 R8 M4 PCIE_MTX_GRX_P12 C629 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
PCIE_GTX_C_MRX_N12 GFX_RX12P GFX_TX12P PCIE_MTX_GRX_N12 C627 1 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12
P8 GFX_RX12N GFX_TX12N M3 2
PCIE_GTX_C_MRX_P13 R6 M1 PCIE_MTX_GRX_P13 C625 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P13
PCIE_GTX_C_MRX_N13 GFX_RX13P GFX_TX13P PCIE_MTX_GRX_N13 C623 1 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N13
R5 GFX_RX13N GFX_TX13N M2 2
PCIE_GTX_C_MRX_P14 P4 N2 PCIE_MTX_GRX_P14 C620 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
PCIE_GTX_C_MRX_N14 GFX_RX14P GFX_TX14P PCIE_MTX_GRX_N14 C624 1 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14
P3 GFX_RX14N GFX_TX14N N1 2
PCIE_GTX_C_MRX_P15 T4 P1 PCIE_MTX_GRX_P15 C621 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P15
PCIE_GTX_C_MRX_N15 GFX_RX15P GFX_TX15P PCIE_MTX_GRX_N15 C619 1 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N15
T3 GFX_RX15N GFX_TX15N P2 2

AE3 AC1 PCIE_ITX_PRX_P0 C617 1 2 0.1U_0402_16V7K

<31> PCIE_PTX_C_IRX_P0 GPP_RX0P GPP_TX0P PCIE_ITX_C_PRX_P0 <31>
AD4 AC2 PCIE_ITX_PRX_N0 C618 1 2 0.1U_0402_16V7K WLAN
<31> PCIE_PTX_C_IRX_N0 GPP_RX0N GPP_TX0N PCIE_ITX_C_PRX_N0 <31>
AE2 AB4 PCIE_ITX_PRX_P1 C614 1 2 0.1U_0402_16V7K
2 <31> PCIE_PTX_C_IRX_P1 GPP_RX1P GPP_TX1P PCIE_ITX_C_PRX_P1 <31> 2
AD3 AB3 PCIE_ITX_PRX_N1 C613 1 2 0.1U_0402_16V7K GLAN
<31> PCIE_PTX_C_IRX_N1 GPP_RX1N GPP_TX1N PCIE_ITX_C_PRX_N1 <31>
AD1 AA2 PCIE_ITX_PRX_P2 @C46
@ C46 1 2 0.1U_0402_16V7K
<31> PCIE_PTX_C_IRX_P2 GPP_RX2P GPP_TX2P PCIE_ITX_C_PRX_P2 <31>
AD2 PCIE I/F GPP AA1 PCIE_ITX_PRX_N2 @C42
@ C42 1 2 0.1U_0402_16V7K WWAN ( Remove 3G Function )
<31> PCIE_PTX_C_IRX_N2 GPP_RX2N GPP_TX2N PCIE_ITX_C_PRX_N2 <31>
V5 GPP_RX3P GPP_TX3P Y1
W6 GPP_RX3N GPP_TX3N Y2
U5 GPP_RX4P GPP_TX4P Y4
U6 Y3 H_CADOP[0..15] H_CADIP[0..15]
GPP_RX4N GPP_TX4N <4> H_CADOP[0..15] H_CADIP[0..15] <4>
U8 GPP_RX5P GPP_TX5P V1
U7 V2 H_CADON[0..15] H_CADIN[0..15]
GPP_RX5N GPP_TX5N <4> H_CADON[0..15] H_CADIN[0..15] <4>

<24> SB_RX0P AA8 AD7 SB_TX0P_C C615 1 2 0.1U_0402_16V7K

SB_RX0P SB_TX0P SB_TX0P <24>
<24> SB_RX0N Y8 AE7 SB_TX0N_C C609 1 2 0.1U_0402_16V7K
SB_RX0N SB_TX0N SB_TX0N <24>
<24> SB_RX1P AA7 AE6 SB_TX1P_C C38 1 2 0.1U_0402_16V7K
SB_RX1P SB_TX1P SB_TX1P <24>
<24> SB_RX1N Y7 AD6 SB_TX1N_C C33 1 2 0.1U_0402_16V7K U3A
SB_RX1N SB_TX1N SB_TX1N <24>
<24> SB_RX2P AA5 PCIE I/F SB AB6 SB_TX2P_C C37 1 2 0.1U_0402_16V7K H_CADOP0 Y25 D24 H_CADIP0
SB_RX2P SB_TX2P SB_TX2P <24> HT_RXCAD0P HT_TXCAD0P
<24> SB_RX2N AA6 AC6 SB_TX2N_C C32 1 2 0.1U_0402_16V7K H_CADON0 Y24 PART 1 OF 6 D25 H_CADIN0
SB_RX2N SB_TX2N SB_TX2N <24> HT_RXCAD0N HT_TXCAD0N
<24> SB_RX3P W5 AD5 SB_TX3P_C C610 1 2 0.1U_0402_16V7K H_CADOP1 V22 E24 H_CADIP1
SB_RX3P SB_TX3P SB_TX3P <24> HT_RXCAD1P HT_TXCAD1P
<24> SB_RX3N Y5 AE5 SB_TX3N_C C616 1 2 0.1U_0402_16V7K H_CADON1 V23 E25 H_CADIN1
SB_RX3N SB_TX3N SB_TX3N <24> HT_RXCAD1N HT_TXCAD1N
H_CADOP2 V25 F24 H_CADIP2
R32 1 1.27K_0402_1% H_CADON2 HT_RXCAD2P HT_TXCAD2P H_CADIN2
PCE_CALRP(PCE_BCALRP) AC8 2 V24 HT_RXCAD2N HT_TXCAD2N F25
AB8 R267 1 2 2K_0402_1% +1.1VS H_CADOP3 U24 F23 H_CADIP3
PCE_CALRN(PCE_BCALRN) H_CADON3 HT_RXCAD3P HT_TXCAD3P H_CADIN3
U25 HT_RXCAD3N HT_TXCAD3N F22
RS780M_FCBGA528 H_CADOP4 T25 H23 H_CADIP4
H_CADON4 HT_RXCAD4P HT_TXCAD4P H_CADIN4
T24 HT_RXCAD4N HT_TXCAD4N H22

HYPER TRANSPORT CPU I/F

RS780M Display Port Support (muxed on GFX) H_CADOP5 P22 J25 H_CADIP5
H_CADON5 HT_RXCAD5P HT_TXCAD5P H_CADIN5
P23 HT_RXCAD5N HT_TXCAD5N J24
H_CADOP6 P25 K24 H_CADIP6
GFX_TX0,TX1,TX2 and TX3 H_CADON6 HT_RXCAD6P HT_TXCAD6P H_CADIN6
P24 HT_RXCAD6N HT_TXCAD6N K25
DP0 H_CADOP7 N24 K23 H_CADIP7
AUX0 and HPD0 H_CADON7 HT_RXCAD7P HT_TXCAD7P H_CADIN7
N25 HT_RXCAD7N HT_TXCAD7N K22

H_CADOP8 AC24 F21 H_CADIP8

3 GFX_TX4,TX5,TX6 and TX7 H_CADON8 HT_RXCAD8P HT_TXCAD8P H_CADIN8 3
AC25 HT_RXCAD8N HT_TXCAD8N G21
DP1 H_CADOP9 AB25 G20 H_CADIP9
AUX1 and HPD1 H_CADON9 HT_RXCAD9P HT_TXCAD9P H_CADIN9
AB24 HT_RXCAD9N HT_TXCAD9N H21
H_CADOP10 AA24 J20 H_CADIP10
H_CADON10 HT_RXCAD10P HT_TXCAD10P H_CADIN10
AA25 HT_RXCAD10N HT_TXCAD10N J21
H_CADOP11 Y22 J18 H_CADIP11
H_CADON11 HT_RXCAD11P HT_TXCAD11P H_CADIN11
Y23 HT_RXCAD11N HT_TXCAD11N K17
H_CADOP12 W21 L19 H_CADIP12
H_CADON12 HT_RXCAD12P HT_TXCAD12P H_CADIN12
W20 HT_RXCAD12N HT_TXCAD12N J19
H_CADOP13 V21 M19 H_CADIP13
H_CADON13 HT_RXCAD13P HT_TXCAD13P H_CADIN13
V20 HT_RXCAD13N HT_TXCAD13N L18
H_CADOP14 U20 M21 H_CADIP14
H_CADON14 HT_RXCAD14P HT_TXCAD14P H_CADIN14
U21 HT_RXCAD14N HT_TXCAD14N P21
H_CADOP15 U19 P18 H_CADIP15
H_CADON15 HT_RXCAD15P HT_TXCAD15P H_CADIN15
U18 HT_RXCAD15N HT_TXCAD15N M18

<4> H_CLKOP0 T22 HT_RXCLK0P HT_TXCLK0P H24 H_CLKIP0 <4>

<4> H_CLKON0 T23 HT_RXCLK0N HT_TXCLK0N H25 H_CLKIN0 <4>
<4> H_CLKOP1 AB23 HT_RXCLK1P HT_TXCLK1P L21 H_CLKIP1 <4>
<4> H_CLKON1 AA22 HT_RXCLK1N HT_TXCLK1N L20 H_CLKIN1 <4>
H_CTLOP0 M22 M24 H_CTLIP0
<4> H_CTLOP0 HT_RXCTL0P HT_TXCTL0P H_CTLIP0 <4>
H_CTLON0 M23 M25 H_CTLIN0
<4> H_CTLON0 HT_RXCTL0N HT_TXCTL0N H_CTLIN0 <4>
H_CTLOP1 R21 P19 H_CTLIP1
<4> H_CTLOP1 HT_RXCTL1P HT_TXCTL1P H_CTLIP1 <4>
H_CTLON1 R20 R18 H_CTLIN1
<4> H_CTLON1 HT_RXCTL1N HT_TXCTL1N H_CTLIN1 <4>
1 R56 2 C23 B24 1 R51 2
HT_RXCALP HT_TXCALP
A24 HT_RXCALN HT_TXCALN B25
301_0402_1%~D 301_0402_1%~D
0718 Place within 1" RS780M_FCBGA528 0718 Place within 1"
layout 1:2 layout 1:2
4 4
SA00002DR30 S IC 216-0674026 A13 RS780MN FCBGA 0FA

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 10 of 49
A B C D E
 A B C D E

For RS780M A13

RED: Connected to GND through two separate 140ohm 1% resistor

UMA@ 1 2 GMCH_CRT_R
R45 140_0402_1%
UMA@ 1 2 GMCH_CRT_G
R49 150_0402_1%
UMA@ 1 2 GMCH_CRT_B
R50 150_0402_1%

1 1

+3VS AVDD=0.11A
PLLVDD=65mA L15
+1.1VS +NB_PLLVDD 1 2 +AVDD1
L59 FBM-L11-201209-300LMA30T_0805 1
1 2 AVDDDI=20mA C94
MBK2012221YZF 0805 1 +1.8VS 2.2U_0603_6.3V4Z
1
L10
C645 C663 +AVDD2 2
1 2
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z FBM-L11-201209-300LMA30T_0805 1
2 2 U3C
C74 F12 A22 GMCH_TXOUT0+ <21>
+1.8VS 0.1U_0402_16V4Z AVDD1(NC) TXOUT_L0P(NC)
PLLVDD18=20mA 2
E12 AVDD2(NC) PART 3 OF 6 TXOUT_L0N(NC) B22 GMCH_TXOUT0- <21>
+1.8VS +NB_HTPVDD L8
AVDDQ=4mA F14 AVDDDI(NC) TXOUT_L1P(NC) A21 GMCH_TXOUT1+ <21>
G15 AVSSDI(NC) TXOUT_L1N(NC) B21 GMCH_TXOUT1- <21>
L13 1 2 +AVDDQ H15 B20 GMCH_TXOUT2+ <21>
FBM-L11-201209-300LMA30T_0805 AVDDQ(NC) TXOUT_L2P(NC)
1 2 1 H14 AVSSQ(NC) TXOUT_L2N(DBG_GPIO0) A20 GMCH_TXOUT2- <21>
MBK2012221YZF 0805 1 1 A19
C61 TXOUT_L3P(NC)
E17 C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2) B19
C93 C84 2.2U_0603_6.3V4Z

CRT/TVOUT
F17 Y(DFT_GPIO2)
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z 2
F15 COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC) B18 GMCH_TZOUT0+ <21>
2 2
TXOUT_U0N(NC) A18 GMCH_TZOUT0- <21>
GMCH_CRT_R G18 A17 GMCH_TZOUT1+ <21>
<23> GMCH_CRT_R RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3)
G17 REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2) B17 GMCH_TZOUT1- <21>
VDDA18HTPLL=20mA GMCH_CRT_G E18 D20 GMCH_TZOUT2+ <21>
<23> GMCH_CRT_G GREEN(DFT_GPIO1) TXOUT_U2P(NC)
F18 GREENb(NC) TXOUT_U2N(NC) D21 GMCH_TZOUT2- <21>
+1.8VS +VDDA18HTPLL GMCH_CRT_B E19 D18
<23> GMCH_CRT_B BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5)
L9 F19 D19
BLUEb(NC) TXOUT_U3N(NC)
1 2
MBK2012221YZF 0805 1 GMCH_CRT_HSYNC A11
VDDLTP18=15mA L56
1 <13,23> GMCH_CRT_HSYNC DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1) B16 GMCH_TXCLK+ <21>
2 GMCH_CRT_VSYNC B11 +VDDLTP18 2
<13,23> GMCH_CRT_VSYNC DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3) A16 GMCH_TXCLK- <21> 1 2 +1.8VS
C66 C72 GMCH_CRT_CLK F8 D16 GMCH_TZCLK+ <21> 1 1 MBC1608121YZF_0603
<23> GMCH_CRT_CLK DAC_SCL(PCE_RCALRN) TXCLK_UP(PCIE_RESET_GPIO4)
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z GMCH_CRT_DATA E8 D17 GMCH_TZCLK- <21>
2 2 <23> GMCH_CRT_DATA DAC_SDA(PCE_TCALRN) TXCLK_UN(PCIE_RESET_GPIO1) C665 C644
R42 1 2 715_0402_1% G14 1U_0402_6.3V4Z 2.2U_0603_6.3V4Z
DAC_RSET(PWM_GPIO1) +VDDLTP18 2 2
VDDA18PCIEPLL=0.12A +NB_PLLVDD VDDLTP18(NC) A13
+NB_PLLVDD A12 PLLVDD(NC) VSSLTP18(NC) B13
+1.8VS +VDDA18PCIEPLL +NB_HTPVDD D14
+NB_HTPVDD PLLVDD18(NC)
L14 B12 A15 +VDDLT18

LVTM
PLLVSS(NC) VDDLT18_1(NC)
1 2 B15 VDDLT18=0.3A

PLL PWR
MBK2012221YZF 0805 1 VDDLT18_2(NC) L12
1 +VDDA18HTPLL H17 VDDA18HTPLL VDDLT33_1(NC) A14
B14 +VDDLT18 1 2 +1.8VS
C87 C86 VDDLT33_2(NC) MBC1608121YZF_0603
+VDDA18PCIEPLL D7 VDDA18PCIEPLL1 1 1
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z E7 C14
2 2 VDDA18PCIEPLL2 VSSLT1(VSS) C90 C95
VSSLT2(VSS) D15
1 2 NB_RESET# D8 C16 0.1U_0402_16V4Z 4.7U_0805_10V4Z
<13,14,24,31,33> PLT_RST# SYSRESETb VSSLT3(VSS) 2 2
R296 0_0402_5% A10 C18
<25> NB_PWRGD POWERGOOD VSSLT4(VSS)
NB_LDTSTOP# C10 C20
NB_ALLOW_LDTSTOP LDTSTOPb VSSLT5(VSS)
2 1 C12 E20

PM
+1.8VS ALLOW_LDTSTOP VSSLT6(VSS)
R283 300_0402_5% C22
VSSLT7(VSS)
<20> CLK_NBHT C25 HT_REFCLKP
<20> CLK_NBHT# C24 HT_REFCLKN
CLK_NB_14.318M
CLK_NB_14.318M E11
<20> CLK_NB_14.318M REFCLK_P/OSCIN(OSCIN)

CLOCKs
F11 E9 UMA_ENVDD
REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP) UMA_ENBKL
LVDS_BLON(PCE_RCALRP) F7 UMA_ENBKL <21>
1

+1.1VS 1 2 1 2 T2 G12 UMA_DPST

<20> CLK_NBGFX GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2)

1.27K_0402_1%

1.27K_0402_1%
R477 R293 R290 T1
<20> CLK_NBGFX# GFX_REFCLKN

2
100_0402_5% 4.7K_0402_5% 4.7K_0402_5% AMD Vari bright function
@ U1 R469
GPP_REFCLKP

1 R294

1 R29
U2 1.27K_0402_1% UMA@ UMA@
2

GPP_REFCLKN @ UMA_DPST 1 ENBKL

2
3 R758 @ 0_0402_5% 3
1 <20> CLK_SBLINK_BCLK V4

2
GPPSB_REFCLKP(SB_REFCLKP)
<20> CLK_SBLINK_BCLK# V3 GPPSB_REFCLKN(SB_REFCLKN)
C854 DVT
100P_0402_25V8K GMCH_LCD_CLK B9
2 <21> GMCH_LCD_CLK I2C_CLK
GMCH_LCD_DATA
@ <21> GMCH_LCD_DATA
GMCH_HDMI_DATA_R2
A9
B8
I2C_DATA MIS. TMDS_HPD(NC) D9
D10
HDMI_DET <15,22>
GMCH_HDMI_CLK_R2 DDC_DATA0/AUX0N(NC) HPD(NC)
A8 DDC_CLK0/AUX0P(NC)
GMCH_HDMI_CLK_R1 B7 D12 1 2 SUS_STAT# <25>
DDC_CLK1/AUX1P(NC) SUS_STAT#(PWM_GPIO5)
DVT GMCH_HDMI_DATA_R1 A7 DDC_DATA1/AUX1N(NC)
R297 0_0402_5% SUS_STAT_R# <13> Strap pin
THERMALDIODE_P AE8
+3VS 2 @ 1 B10 AD8
R288 10K_0402_5% STRP_DATA THERMALDIODE_N
POWER_SEL G11 D13 1 2
<43> POWER_SEL RSVD TESTMODE R279 R744 0_0402_5%
C8 1.8K_0402_5% 1 2
<13> AUX_CAL AUX_CAL(NC)
+3VS
+3VS
Strap pin RS780M_FCBGA528
C857 0.1U_0402_16V4Z
POWER_SEL
R295 1 2 4.7K_0402_5% GMCH_LCD_CLK DVT R491 @ 0_0402_5%

5
R289 1 2 4.7K_0402_5% GMCH_LCD_DATA 1 2GMCH_HDMI_CLK_R2
HIGH 1.0V UMA_ENVDD 2

P
B
Y 4 UMA_ENVDD_R <21>
R488 UMA@ 0_0402_5% 1 A

G
LOW 1.1V <22> GMCH_HDMI_CLK GMCH_HDMI_CLK 1 2 GMCH_HDMI_CLK_R1 U48
GMCH_HDMI_DATA 1 2 GMCH_HDMI_DATA_R1 NC7SZ08P5X_NL_SC70-5
<22> GMCH_HDMI_DATA

3
R489 UMA@ 0_0402_5% @
NB_PWRGD
+1.8VS 1 2GMCH_HDMI_DATA_R2
R492 @ 0_0402_5%

5
2

hexainf@hotmail.com
4 B 4
Y 4 ENBKL <33>
2

Un-stuff for Tigris Change as 1K_5% ohm 0_0402_5% UMA_ENBKL 1 A

G
1 2 NB_LDTSTOP# U49
for Tigris <6,24> LDT_STOP#
R60 R280 NC7SZ08P5X_NL_SC70-5

3
300_0402_5% UMA@
1

R59 0_0402_5%
<24> ALLOW_LDTSTOP 1 2 NB_ALLOW_LDTSTOP Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 11 of 49
A B C D E
 A B C D E

VDDHTRX+VDDHT=0.68A
L49 0.1U_0402_16V4Z 1U_0402_6.3V4Z
+1.1VS 2 1 +VDDHT
U3F
FBMA-L11-201209-221LMA30T_0805 1 1 1 1 A25 A2
L3 VSSAHT1 VSSAPCIE1
C612 C75 C71 C62
D23 VSSAHT2 PART 6/6 VSSAPCIE2 B1
1 2 +1.1VS E22 VSSAHT3 VSSAPCIE3 D3
VDDPCIE=1.1A FBMA-L11-201209-221LMA30T_0805 G22 D5
2 2 2 2 U3E VSSAHT4 VSSAPCIE4
G24 VSSAHT5 VSSAPCIE5 E4
4.7U_0805_10V4Z 0.1U_0402_16V4Z J17 A6 +VDDA11PCIE C30 1 2 10U_0603_6.3V6M G25 G1
1 VDDHT_1 VDDPCIE_1 C28 VSSAHT6 VSSAPCIE6 1
K16 VDDHT_2 PART 5/6 VDDPCIE_2 B6 1 2 10U_0603_6.3V6M H19 VSSAHT7 VSSAPCIE7 G2
L16 VDDHT_3 VDDPCIE_3 C6 J22 VSSAHT8 VSSAPCIE8 G4
L11 1U_0402_6.3V4Z M16 D6 L17 H7
0.1U_0402_16V4Z +VDDHTRX VDDHT_4 VDDPCIE_4 C29 VSSAHT9 VSSAPCIE9
2 1 P16 VDDHT_5 VDDPCIE_5 E6 1 2 4.7U_0805_10V4Z L22 VSSAHT10 VSSAPCIE10 J4
R16 VDDHT_6 VDDPCIE_6 F6 L24 VSSAHT11 VSSAPCIE11 R7
FBMA-L11-201209-221LMA30T_0805 1 1 1 1 T16 G7 C53 1 2 1U_0402_6.3V4Z L25 L1
VDDHT_7 VDDPCIE_7 C79 VSSAHT12 VSSAPCIE12
VDDPCIE_8 H8 1 2 1U_0402_6.3V4Z M20 VSSAHT13 VSSAPCIE13 L2
C83 C82 C85 C91 H18 J9 N22 L4
VDDHTRX_1 VDDPCIE_9 VSSAHT14 VSSAPCIE14
G19 VDDHTRX_2 VDDPCIE_10 K9 1 2 P20 VSSAHT15 VSSAPCIE15 L7
2 2 2 2 C88
F20 VDDHTRX_3 VDDPCIE_11 M9 1 2 0.1U_0402_16V4Z R19 VSSAHT16 VSSAPCIE16 M6
4.7U_0805_10V4Z 0.1U_0402_16V4Z E21 L9 C57 0.1U_0402_16V4Z R22 N4
VDDHTRX_4 VDDPCIE_12 VSSAHT17 VSSAPCIE17
D22 VDDHTRX_5 VDDPCIE_13 P9 R24 VSSAHT18 VSSAPCIE18 P6
B23 VDDHTRX_6 VDDPCIE_14 R9 R25 VSSAHT19 VSSAPCIE19 R1

L4
VDDHTTX=0.68A A23 VDDHTRX_7 VDDPCIE_15 T9 H20 VSSAHT20 VSSAPCIE20 R2
VDDPCIE_16 V9 U22 VSSAHT21 VSSAPCIE21 R4
+1.2V_HT 2 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDHTTX AE25 U9 VDDC=7.6A V19 V7
VDDHTTX_1 VDDPCIE_17 VSSAHT22 VSSAPCIE22

GROUND
AD24 VDDHTTX_2 W22 VSSAHT23 VSSAPCIE23 U4
FBMA-L11-201209-221LMA30T_0805 1 1 1 1 1 AC23 K12 +1.1VS 1 2 +NB_CORE W24 V8
VDDHTTX_3 VDDC_1 @L6
@ L6 0_1206_5% VSSAHT24 VSSAPCIE24
AB22 VDDHTTX_4 VDDC_2 J14 W25 VSSAHT25 VSSAPCIE25 V6
C31 C49 C50 C54 C52 AA21 U16 1 2 Y21 W1
VDDHTTX_5 VDDC_3 @L7
@ L7 0_1206_5% VSSAHT26 VSSAPCIE26
2 2 2 2 2
Y20 VDDHTTX_6 VDDC_4 J11 DVT AD25 VSSAHT27 VSSAPCIE27 W2
W19 VDDHTTX_7 VDDC_5 K15 VSSAPCIE28 W4

POWER
4.7U_0805_10V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z V18 M12 L12 W7
VDDHTTX_8 VDDC_6 VSS11 VSSAPCIE29
U17 VDDHTTX_9 VDDC_7 L14 M14 VSS12 VSSAPCIE30 W8
FOR Version A11 pop 1.35VS A12 T17 VDDHTTX_10 VDDC_8 L11 N13 VSS13 VSSAPCIE31 Y6

UMA@ C27
R17 M13 P12 AA4
use 1.2V_HT P17
VDDHTTX_11 VDDC_9
M15 P15
VSS14 VSSAPCIE32
AB5
VDDHTTX_12 VDDC_10 VSS15 VSSAPCIE33
VDDA18PCIE=0.7A M17 VDDHTTX_13 VDDC_11 N12 R11 VSS16 VSSAPCIE34 AB1

C35

C60

C34

C69

C43

C76

C64

C81

C68

C36

C44
L5 N14 1 R14 AB7
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDA18PCIE VDDC_12 VSS17 VSSAPCIE35
+1.8VS 2 1 J10 VDDA18PCIE_1 VDDC_13 P11 1 1 1 1 1 1 1 1 1 1 1 T12 VSS18 VSSAPCIE36 AC3
FBMA-L11-201209-221LMA30T_0805 P10 P13 + U14 AC4
VDDA18PCIE_2 VDDC_14 VSS19 VSSAPCIE37
1 1 1 1 1 1 K10 VDDA18PCIE_3 VDDC_15 P14 U11 VSS20 VSSAPCIE38 AE1

330U_D2E_2.5VM_R9M
10U_0603_6.3V6M

10U_0603_6.3V6M
2 2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
M10 VDDA18PCIE_4 VDDC_16 R12 U15 VSS21 VSSAPCIE39 AE4
C45 C47 C40 C51 C48 C73 2 2 2 2 2 2 2 2 2 2 2 2
L10 VDDA18PCIE_5 VDDC_17 R15 V12 VSS22 VSSAPCIE40 AB2
10U_0805_10V4Z W9 T11 W11
2 2 2 2 2 2 VDDA18PCIE_6 VDDC_18 VSS23
H9 VDDA18PCIE_7 VDDC_19 T15 W15 VSS24
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z T10 U12 AC12 AE14
VDDA18PCIE_8 VDDC_20 VSS25 VSS1
R10 VDDA18PCIE_9 VDDC_21 T14 AA14 VSS26 VSS2 D11
Y9 VDDA18PCIE_10 VDDC_22 J16 Y18 VSS27 VSS3 G8
AA9 VDDA18PCIE_11 AB11 VSS28 VSS4 E14
AB9 VDDA18PCIE_12 VDD_MEM1(NC) AE10 AB15 VSS29 VSS5 E15
AD9 VDDA18PCIE_13 VDD_MEM2(NC) AA11 AB17 VSS30 VSS6 J15
AE9 Y11 +1.8VS AB19 J12
VDDA18PCIE_14 VDD_MEM3(NC) VSS31 VSS7
U10 VDDA18PCIE_15 VDD_MEM4(NC) AD10 AE20 VSS32 VSS8 K14
VDD18=10mA AB10 VDD_MEM=70mA C249 2 1 SP@ 4.7U_0805_10V4Z AB21 M11
VDD_MEM5(NC) C248 SP@ 0.1U_0402_16V4Z VSS33 VSS9
+1.8VS F9 VDD18_1 VDD_MEM6(NC) AC10 2 1 2 1 K11 VSS34 VSS10 L15
G9 R407 SP@0_0603_5% C597 2 1 SP@ 0.1U_0402_16V4Z
VDD18_2
+1.8VS 1 2+1.8V_VDD_SP AE11 VDD18_MEM1(NC) VDD33_1(NC) H11 2 1 C598 2 1 SP@ 0.1U_0402_16V4Z RS780M_FCBGA528
R224 SP@ 0_0402_5% AD11 H12 R406 VGA@ 0_0603_5% C599 2 1 SP@ 0.1U_0402_16V4Z
VDD18_MEM2(NC) VDD33_2(NC)
1

VDD18_MEM=25mA 1
C92 RS780M_FCBGA528
1
C89 R223 SP@ VDD33=60mA
1U_0402_6.3V4Z VGA@ 1U_0402_6.3V4Z +3VS
0_0402_5% 2
2

2
1 1
C80 C78
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 12 of 49
A B C D E
 A B C D E

DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb

Enables the Test Debug Bus using GPIO. (VSYNC)

1 : Disable (RS780)
0 : Enable (Rs780)

U61
MEM_BA0 L2 B9 MEM_DQ12 2 1 +3VS
1 BA0 DQ15 <11,23> GMCH_CRT_VSYNC 1
MEM_BA1 L3 B1 MEM_DQ13 R286 3K_0402_5%
BA1 DQ14 MEM_DQ9
DQ13 D9 2 1
MEM_A12 R2 D1 MEM_DQ14 R287 @ 3K_0402_5%
MEM_A11 A12 DQ12 MEM_DQ15
P7 A11 DQ11 D3
MEM_A10 M2 D7 MEM_DQ8
MEM_A9 A10/AP DQ10 MEM_DQ10
P3 A9 DQ9 C2
MEM_A8 P8 C8 MEM_DQ11
MEM_A7 A8 DQ8 MEM_DQ5
P2 A7 DQ7 F9
MEM_A6 N7 F1 MEM_DQ2
MEM_A5 A6 DQ6 MEM_DQ6
N3 A5 DQ5 H9
MEM_A4 N8 H1 MEM_DQ1 DFT_GPIO1: LOAD_EEPROM_STRAPS
MEM_A3 A4 DQ4 MEM_DQ0
N2 A3 DQ3 H3
MEM_A2 M7 H7 MEM_DQ4
MEM_CLKN MEM_A1 A2 DQ2 MEM_DQ3
M3 A1 DQ1 G2 Selects Loading of STRAPS from EPROM
MEM_A0 M8 G8 MEM_DQ7
A0 DQ0 1 : Bypass the loading of EEPROM straps and use Hardware Default Values
1

R135 0 : I2C Master can load strap values from EEPROM if connected, or use
+1.8V_MEM_VDDQ
SP@ K8 CK VDDQ A9 default values if not connected
100_0402_1% J8 C1 RS740/RX780: DFT_GPIO1 RS780:SUS_STAT
CK VDDQ
C3
2

MEM_CLKP MEM_CKE VDDQ

K2 CKE VDDQ C7
VDDQ C9
VDDQ E9
VDDQ G1
MEM_CS# L8 G3 1 2
CS VDDQ <11> AUX_CAL
G7 @R284
@ R284 150_0402_1%
MEM_WE# VDDQ D29
K3 WE VDDQ G9 RS780 DFT_GPIO1
@ CH751H-40_SC76
MEM_RAS# K7 A1 2 1
RAS VDD <11> SUS_STAT_R# PLT_RST# <11,14,24,31,33>
VDD E1
MEM_CAS# L7 J9
CAS VDD
VDD M9 2 1
2 MEM_DM0 R299 @ 3K_0402_5% 2
F3 LDM VDD R1
MEM_DM1 B3 UDM SP@ L23
VDDL J1 2 1 +1.8V_MEM_VDDQ
J7 1 FBMA-L11-160808-221LMT 0603
VSSDL

SP@ C184
1U_0402_6.3V4Z
MEM_ODT K9 ODT

2 Layout Note: 50 mil for VSSDL RS780 use HSYNC to enable SIDE PORT
MEM_DQS_P0 F7
MEM_DQS_N0 LDQS
E8 LDQS VSSQ A7
VSSQ B2 RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)
VSSQ B8 0. Enable (RS780)
VSSQ D2
MEM_DQS_P1 B7 D8 1 : Disable(RS780)
MEM_DQS_N1 UDQS VSSQ
A8 UDQS VSSQ E7
VSSQ F2
VSSQ F8
+MEM_VREF J2 H2
VREF VSSQ
VSSQ H8 RS780 use HSYNC to enable SIDE PORT
A2 NC
E2 NC VSS A3
MEM_BA2 L1 E3 2 1 +3VS
NC VSS <11,23> GMCH_CRT_HSYNC
R3 J3 R281 VGA@ 3K_0402_5%
NC VSS
R7 NC VSS N1 2 1
R8 P9 R282 SP@ 3K_0402_5%
NC VSS
Support 8M x 16bit x 8 bank side port
HY5PS561621AFP-25_FBGA84
@ U3D
03/16 SA000031O00 S IC D2 64M16/500 K4N1G164QE-HC20 FBGA84 PAR 4 OF 6
03/16 SA00002UH00 S IC D2 64M16/500 H5PS1G63EFR-20L FBGA84 MEM_A0 AB12 AA18 MEM_DQ0
MEM_A1 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) MEM_DQ1
AE16 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) AA20
MEM_A2 V11 AA19 MEM_DQ2
3 MEM_A3 MEM_A2(NC) MEM_DQ2/DVO_DE(NC) MEM_DQ3 3
AE15 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) Y19
MEM_A4 AA12 V17 MEM_DQ4
MEM_A5 MEM_A4(NC) MEM_DQ4(NC) MEM_DQ5
AB16 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) AA17
MEM_A6 AB14 AA15 MEM_DQ6
MEM_A7 MEM_A6(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7
AD14 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) Y15
MEM_A8 AD13 AC20 MEM_DQ8
MEM_A9 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) MEM_DQ9
AD15 MEM_A9(NC) MEM_DQ9/DVO_D5(NC) AD19

SBD_MEM/DVO_I/F
MEM_A10 AC16 AE22 MEM_DQ10
MEM_A11 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) MEM_DQ11
AE13 MEM_A11(NC) MEM_DQ11/DVO_D7(NC) AC18
MEM_A12 AC14 AB20 MEM_DQ12
MEM_A12(NC) MEM_DQ12(NC) MEM_DQ13
Y14 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) AD22
AC22 MEM_DQ14
MEM_BA0 MEM_DQ14/DVO_D10(NC) MEM_DQ15
AD16 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC) AD21
+1.8V_MEM_VDDQ +1.8V_MEM_VDDQ MEM_BA1 AE17
MEM_BA2 MEM_BA1(NC) MEM_DQS_P0
AD17 MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC) Y17
W18 MEM_DQS_N0
MEM_DQS0N/DVO_IDCKN(NC)
1K_0402_1%
0.1U_0402_16V4Z

220 ohm @ 100MHz,2A MEM_RAS# W12 AD20 MEM_DQS_P1

MEM_RASb(NC) MEM_DQS1P(NC)
0.1U_0402_16V4Z

MEM_CAS# Y12 AE21 MEM_DQS_N1

+1.8V_MEM_VDDQ +1.8VS MEM_WE# MEM_CASb(NC) MEM_DQS1N(NC)
AD18 MEM_WEb(NC)
2

1K_0402_1%

1 1 MEM_CS# AB13 W17 MEM_DM0

MEM_CSb(NC) MEM_DM0(NC) +1.8VS
SP@ C195

MEM_CKE AB18 AE19 MEM_DM1 15mA

MEM_CKE(NC) MEM_DM1/DVO_D8(NC)
1 SP@

C197

1 2 MEM_ODT V14 MEM_ODT(NC)

SP@

SP@

22U_0805_6.3V6M
R117

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1U_0402_6.3V4Z

1U_0402_6.3V4Z

L16 SP@ 0_0805_5% AE23 FBMA-L11-160808-221LMT 0603 2 1 L21

2 2 IOPLLVDD18(NC)
1K_0402_1% R118

MEM_CLKP V15 AE24 2 1 L22 +1.1VS 1 FBMA-L11-160808-221LMT 0603

1

MEM_CLKN MEM_CKP(NC) IOPLLVDD(NC)

+MEM_VREF +MEM_VREF1
2 2 1 1 1 W14 MEM_CKN(NC) 26mA 1
C185 C183
IOPLLVSS(NC) AD23
C628

C626

C201

C206

C208 2 1 MEM_COMP_P AE12 SP@ SP@

MEM_COMPP(NC) 2
0.1U_0402_16V4Z

0.1U_0402_16V4Z

R140 SP@ 40.2_0402_1% AD12 AE18 +MEM_VREF1 2.2U_0603_6.3V4Z 2.2U_0603_6.3V4Z

1 1 2 2 2 MEM_COMP_N MEM_COMPN(NC) MEM_VREF(NC) 2
+1.8V_MEM_VDDQ 2 1
1 1 R136 SP@ 40.2_0402_1% RS780M_FCBGA528
2

1K_0402_1%
SP@ C207

SP@ SP@ SP@ SP@ SP@ +1.8VS=W/S=20/10mil For Memory PLL power
C200

+1.1VS=W/S=20/10mil For Memory PLL power

hexainf@hotmail.com
1 SP@

SP@

SP@

4 4
2 2
R120
R119

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 13 of 49
A B C D E
 5 4 3 2 1

PCIE_GTX_C_MRX_P[0..15]
<10> PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
<10> PCIE_GTX_C_MRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
<10> PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
<10> PCIE_MTX_C_GRX_N[0..15]

D D

U64A

PCIE_MTX_C_GRX_N15 AF30 AH30 PEG_NRX_C_GTX_N15 C1061 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N15

PCIE_MTX_C_GRX_P15 AE31 PCIE_RX0P PCIE_TX0P PEG_NRX_C_GTX_P15 C1060 1 0.1U_0402_16V7K PCIE_GTX_C_MRX_P15
PCIE_RX0N PCIE_TX0N AG31 2
VGA@
VGA@
PCIE_MTX_C_GRX_N14 AE29 AG29 PEG_NRX_C_GTX_N14 C1063 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N14
PCIE_MTX_C_GRX_P14 AD28 PCIE_RX1P PCIE_TX1P PEG_NRX_C_GTX_P14 C1062 1 0.1U_0402_16V7K PCIE_GTX_C_MRX_P14
PCIE_RX1N PCIE_TX1N AF28 2
VGA@
VGA@
PCIE_MTX_C_GRX_N13 AD30 AF27 PEG_NRX_C_GTX_N13 C1065 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N13
PCIE_MTX_C_GRX_P13 AC31 PCIE_RX2P PCIE_TX2P PEG_NRX_C_GTX_P13 C1064 1 0.1U_0402_16V7K PCIE_GTX_C_MRX_P13
PCIE_RX2N PCIE_TX2N AF26 2
VGA@
VGA@
PCIE_MTX_C_GRX_N12 AC29 AD27 PEG_NRX_C_GTX_N12 C1067 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N12
PCIE_MTX_C_GRX_P12 AB28 PCIE_RX3P PCIE_TX3P PEG_NRX_C_GTX_P12 C1066 1 0.1U_0402_16V7K PCIE_GTX_C_MRX_P12
PCIE_RX3N PCIE_TX3N AD26 2
VGA@
VGA@
PCIE_MTX_C_GRX_N11 AB30 AC25 PEG_NRX_C_GTX_N11 C1069 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N11
PCIE_RX4P PCIE_TX4P

PCI EXPRESS INTERFACE

PCIE_MTX_C_GRX_P11 AA31 AB25 PEG_NRX_C_GTX_P11 C1068 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P11
PCIE_RX4N PCIE_TX4N
VGA@
VGA@
PCIE_MTX_C_GRX_N10 AA29 Y23 PEG_NRX_C_GTX_N10 C1071 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N10
PCIE_MTX_C_GRX_P10 Y28 PCIE_RX5P PCIE_TX5P PEG_NRX_C_GTX_P10 C1070 1 0.1U_0402_16V7K PCIE_GTX_C_MRX_P10
PCIE_RX5N PCIE_TX5N Y24 2
VGA@
VGA@
C PCIE_MTX_C_GRX_N9 PEG_NRX_C_GTX_N9 C1073 0.1U_0402_16V7K PCIE_GTX_C_MRX_N9 C
Y30 PCIE_RX6P PCIE_TX6P AB27 1 2
PCIE_MTX_C_GRX_P9 W31 AB26 PEG_NRX_C_GTX_P9 C1072 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P9
PCIE_RX6N PCIE_TX6N
VGA@
VGA@
PCIE_MTX_C_GRX_N8 W29 Y27 PEG_NRX_C_GTX_N8 C1075 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N8

PCIE LANE REVERSAL PCIE_MTX_C_GRX_P8 V28

PCIE_RX7P
PCIE_RX7N
PCIE_TX7P
PCIE_TX7N Y26 PEG_NRX_C_GTX_P8 C1074 1 2
VGA@
0.1U_0402_16V7K PCIE_GTX_C_MRX_P8 PCIE LANE REVERSAL
VGA@
PCIE_MTX_C_GRX_N7 V30 W24 PEG_NRX_C_GTX_N7 C1077 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N7
PCIE_MTX_C_GRX_P7 PCIE_RX8P PCIE_TX8P PEG_NRX_C_GTX_P7 C1076 1 0.1U_0402_16V7K PCIE_GTX_C_MRX_P7
U31 PCIE_RX8N PCIE_TX8N W23 2
@
@
PCIE_MTX_C_GRX_N6 U29 V27 PEG_NRX_C_GTX_N6 C1079 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N6
PCIE_MTX_C_GRX_P6 PCIE_RX9P PCIE_TX9P PEG_NRX_C_GTX_P6 C1078 1 0.1U_0402_16V7K PCIE_GTX_C_MRX_P6
T28 PCIE_RX9N PCIE_TX9N U26 2
@
@
PCIE_MTX_C_GRX_N5 T30 U24 PEG_NRX_C_GTX_N5 C1081 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N5
PCIE_MTX_C_GRX_P5 PCIE_RX10P PCIE_TX10P PEG_NRX_C_GTX_P5 C1080 1 0.1U_0402_16V7K PCIE_GTX_C_MRX_P5
R31 PCIE_RX10N PCIE_TX10N U23 2
@
@
PCIE_MTX_C_GRX_N4 R29 T26 PEG_NRX_C_GTX_N4 C1083 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N4
PCIE_MTX_C_GRX_P4 PCIE_RX11P PCIE_TX11P PEG_NRX_C_GTX_P4 C1082 1 0.1U_0402_16V7K PCIE_GTX_C_MRX_P4
P28 PCIE_RX11N PCIE_TX11N T27 2
@ For M92 S2-LP
@ disable PCIE GFX 0~7
PCIE_MTX_C_GRX_N3 P30 T24 PEG_NRX_C_GTX_N3 C1085 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N3
PCIE_MTX_C_GRX_P3 PCIE_RX12P PCIE_TX12P PEG_NRX_C_GTX_P3 C1084 1 0.1U_0402_16V7K PCIE_GTX_C_MRX_P3
N31 PCIE_RX12N PCIE_TX12N T23 2
@
@
PCIE_MTX_C_GRX_N2 N29 P27 PEG_NRX_C_GTX_N2 C1087 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N2
PCIE_MTX_C_GRX_P2 PCIE_RX13P PCIE_TX13P PEG_NRX_C_GTX_P2 C1086 1 0.1U_0402_16V7K PCIE_GTX_C_MRX_P2
M28 PCIE_RX13N PCIE_TX13N P26 2
@
@
B PCIE_MTX_C_GRX_N1 M30 PEG_NRX_C_GTX_N1 C1089 0.1U_0402_16V7K PCIE_GTX_C_MRX_N1 B
PCIE_RX14P PCIE_TX14P P24 1 2
PCIE_MTX_C_GRX_P1 L31 P23 PEG_NRX_C_GTX_P1 C1088 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P1
PCIE_RX14N PCIE_TX14N
@
@
PCIE_MTX_C_GRX_N0 L29 M27 PEG_NRX_C_GTX_N0 C1091 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_N0
PCIE_MTX_C_GRX_P0 K30 PCIE_RX15P PCIE_TX15P PEG_NRX_C_GTX_P0 C1090 1 0.1U_0402_16V7K PCIE_GTX_C_MRX_P0
PCIE_RX15N PCIE_TX15N N26 2
@
@
CLOCK
CLK_PCIE_VGA AK30
<20> CLK_PCIE_VGA PCIE_REFCLKP
CLK_PCIE_VGA# AK32
<20> CLK_PCIE_VGA# PCIE_REFCLKN
For Future ASIC Pin CALIBRATION
N10 need pull down VGA@
L9 Y22 R864 1 2 1.27K_0402_1%
@ 10K_0402_5% NC#1 PCIE_CALRP VGA@
N9 NC#2
2 1 N10 AA22 R865 1 2 2K_0402_1% +1.1VS
R955 NC_PWRGOOD PCIE_CALRN

<11,13,24,31,33> PLT_RST# AL27 PERSTB

2 1 216-0728002 A11 M92-S2_FCBGA631

@C780
@ C780 10P_0402_50V8J VGA@
ESD

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/11 Deciphered Date 200810/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401728 A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 04, 2009 Sheet 14 of 49
5 4 3 2 1
 5 4 3 2 1

For M92-S2: DO NOT Install any Component U64B

in this Box. MUTI GFX U64F
1 2 AA1 DVPCNTL_MVP_0 TXCAP_DPA3P AF2 HDMI_CLK+_VGA <22>
+1.8VS R278 @ 150_0402_1% Y4 AF4
DVPCNTL_MVP_1 TXCAM_DPA3N HDMI_CLK-_VGA <22>
L125 (1.8V@120mA +DPLL_PVDD) AC7 DVPCNTL_0
Y2 AG3 LVDS CONTROL AB11
DVPCNTL_1 TX0P_DPA2P HDMI_TX0+_VGA <22> VARY_BL VGA_DPST <21>
1 2 @ 1U_0402_6.3V4Z +DPC_VDD18 U5 AG5 AB12
DVPCNTL_2 DPA TX0M_DPA2N HDMI_TX0-_VGA <22> DIGON VGA_ENVDD <21>
U1 DVPCLK
@ MCK1608471YZF 0603 1 1 1 VRAM_ID0 Y7 AH3
<19> VRAM_ID0 DVPDATA_0 TX1P_DPA1P HDMI_TX1+_VGA <22>
C1251 C1250 C1252 VRAM_ID1 V2 AH1
<19> VRAM_ID1 DVPDATA_1 TX1M_DPA1N HDMI_TX1-_VGA <22>
@ 10U_0603_6.3V6M VRAM_ID2 Y8
<19> VRAM_ID2 DVPDATA_2
VRAM_ID3 V4 AK3 AH20 VGA_TZCLK+ VGA_TZCLK+ <21>
2 2 2 <19> VRAM_ID3 DVPDATA_3 TX2P_DPA0P HDMI_TX2+_VGA <22> TXCLK_UP_DPF3P
AB7 AK1 AJ19 VGA_TZCLK- VGA_TZCLK- <21>
DVPDATA_4 TX2M_DPA0N HDMI_TX2-_VGA <22> TXCLK_UN_DPF3N
W1 DVPDATA_5
AB8 AK5 AL21 VGA_TZOUT0+ VGA_TZOUT0+ <21>
@ 0.1U_0402_10V6K DVPDATA_6 TXCBP_DPB3P TXOUT_U0P_DPF2P VGA_TZOUT0-
W3 DVPDATA_7 TXCBM_DPB3N AM3 TXOUT_U0N_DPF2N AK20 VGA_TZOUT0- <21>
AB9 DVPDATA_8
W5 AK6 AH22 VGA_TZOUT1+ VGA_TZOUT1+ <21>
DVPDATA_9 TX3P_DPB2P TXOUT_U1P_DPF1P VGA_TZOUT1-
D AC6 DVPDATA_10 TX3M_DPB2N AM5 TXOUT_U1N_DPF1N AJ21 VGA_TZOUT1- <21> D
+1.1VS (1.8V@120mA +DPLL_PVDD) +DPC_VDD18 W6 DPB
L128 DVPDATA_11 VGA_TZOUT2+
AD7 DVPDATA_12 TX4P_DPB1P AJ7 TXOUT_U2P_DPF0P AL23 VGA_TZOUT2+ <21>
1 2 @ 1U_0402_6.3V4Z +DPC_VDD10 AA3 AH6 AK22 VGA_TZOUT2- VGA_TZOUT2- <21>
DVPDATA_13 TX4M_DPB1N TXOUT_U2N_DPF0N
AC8 DVPDATA_14
@ MCK1608471YZF 0603 1 1 1 +DPC_VDD10 AA5 AK8 AK24
C1258 C1260 C1259 DVPDATA_15 TX5P_DPB0P TXOUT_U3P
AE8 DVPDATA_16 TX5M_DPB0N AL7 TXOUT_U3N AJ23
@ 10U_0603_6.3V6M 1 2 AA6
R957 @ 0_0402_5%AE9 DVPDATA_17
2 2 2 DVPDATA_18 LVTMDP
AB4 DVPDATA_19
AD9 DVPDATA_20
AB2 DVPDATA_21 R AM26 VGA_CRT_R <23> TXCLK_LP_DPE3P AL15 VGA_TXCLK+ <21>
@ 0.1U_0402_10V6K AC10 DAC1 AK14 VGA_TXCLK- <21>
DVPDATA_22 TXCLK_LN_DPE3N
AC5 DVPDATA_23 RB AK26
TXOUT_L0P_DPE2P AH16 VGA_TXOUT0+ <21>
AL25 VGA_CRT_G <23> VGA_CRT_R 1 VGA@ 2 AJ15 VGA_TXOUT0- <21>
+3.3V_DELAY G R870 150_0402_1% TXOUT_L0N_DPE2N
AJ25
LCD GB VGA_CRT_G 1 VGA@ 2 TXOUT_L1P_DPE1P AL17 VGA_TXOUT1+ <21>
1 2 VGA_LCD_CLK <21> VGA_LCD_CLK R1 I2C AH24 R872 150_0402_1% AK16 VGA_TXOUT1- <21>
SCL B VGA_CRT_B <23> TXOUT_L1N_DPE1N
R871 VGA@ 4.7K_0402_5% <21> VGA_LCD_DATA R3 AG25 VGA_CRT_B 1 VGA@ 2
SDA BB R874 150_0402_1%
TXOUT_L2P_DPE0P AH18 VGA_TXOUT2+ <21>
1 2 VGA_LCD_DATA AH26 VGA_CRT_HSYNC <19,23> AJ17 VGA_TXOUT2- <21>
R873 VGA@ 4.7K_0402_5% HSYNC TXOUT_L2N_DPE0N
VSYNC AJ27 VGA_CRT_VSYNC <19,23>
TXOUT_L3P AL19
GENERAL PURPOSE I/O AK18
R875 2 VGA_PWRSEL TXOUT_L3N
1 RSET AD22 1 R876 2
@ 10K_0402_5% VGA@ 499_0402_1%
GPU_GPIO0 U6 AG24 +AVDD
<19> GPU_GPIO0 GPIO_0 AVDD
GPU_GPIO1 U10 AE22
<19> GPU_GPIO1 GPIO_1 AVSSQ
GPU_GPIO2 T10
<19> GPU_GPIO2 GPIO_2 216-0728002 A11 M92-S2_FCBGA631
U8 AE23 +VDD1DI
GPIO_3_SMBDATA VDD1DI VGA@
U7 GPIO_4_SMBCLK VSS1DI AD23
R877 1 2 @ 0_0402_5% T9
R878 1 VGA@ 10K_0402_5% GPIO_5_AC_BATT
2 T8 GPIO_6
T7 +1.8VS (1.8V@70mA AVDD) +AVDD
<33> VGA_ENBKL GPIO_7_BLON
SOUT_GPIO8 P10 L104
<19> SOUT_GPIO8 GPIO_8_ROMSO
GPU_GPIO9 P4 2 1 VGA@ 1U_0402_6.3V4Z
<19> GPU_GPIO9 GPIO_9_ROMSI
P2 AM12 BLM18PG121SN1D_0603 1 1 1
GPU_GPIO11 GPIO_10_ROMSCK R2 VGA@ C1098 C1099 C1100
<19> GPU_GPIO11 N6 GPIO_11 R2B AK12
GPU_GPIO12 N5
<19> GPU_GPIO12 GPIO_12
GPU_GPIO13 N3 AL11 10U_0603_6.3V
<19> GPU_GPIO13 GPIO_13 G2 2 2 2
C Y9 AJ11 VGA@ C
VGA_PWRSEL GPIO_14_HPD2 G2B 0.1U_0402_10V6K
<47> VGA_PWRSEL N1 GPIO_15_PWRCNTL_0
1 R879 2 @ 0_0402_5%R_27M_SSC M4 AK10 VGA@
<20> 27M_SSC GPIO_16_SSIN B2
R6 AL9 (1.8V@45mA VDD1DI) +VDD1DI
<19> THM_ALERT# GPIO_17_THERMAL_INT DAC2 B2B
W10 L105
+VGA_CORE GPIO_18_HPD3
@ 1 R880 2 10K_0402_5% GPU_CTF M2 GPIO_19_CTF 2 1 VGA@ 1U_0402_6.3V4Z
P8 AH12 PADT2
PAD T2 BLM18PG121SN1D_0603 1 1 1
BB_EN @ 1 R881 GPU_GPIO21 P7 GPIO_20_PWRCNTL_1 C
2 0_0402_5% GPIO_21_BB_EN Y AM10 PAD T3
PADT3 VGA@ C1101 C1102 C1103
N8 AJ9 PAD T4
PADT4
GPIO_22_ROMCSB COMP
1

@ GPIO23_CLKREQB N7 VGA@ 10U_0603_6.3V

R882 GPIO_23_CLKREQB 2 2 2
T11 GPIO_29_DRM_0
10K_0402_5% R11 AL13 HSYNC_DAC2 <19> 0.1U_0402_10V6K
GPIO_30_DRM_1 H2SYNC VGA@
V2SYNC AJ13 VSYNC_DAC2 <19>
GPIO24_TRSTB L6 (1.8V@1mA A2VDDQ)
2

T5 PAD JTAG_TRSTB +A2VDDQ

10/24 Reference AMD REF136-1 L5 JTAG_TDI
BB_EN T6 PAD L3 AD19 +VDD2DI L106
T7 PAD JTAG_TCK VDD2DI VGA@ 1U_0402_6.3V4Z
L1 JTAG_TMS VSS2DI AC19 2 1
Do not use Back Bais than T8 PAD K4 BLM18PG121SN1D_0603 1 1 1
TESTEN JTAG_TDO VGA@ C1104 C1105 C1106
pull high to +VDDC <17> TESTEN AF24 TESTEN
AE20 +A2VDD
+3.3V_DELAY A2VDD VGA@ 10U_0603_6.3V
AB13 GENERICA
+1.8VS +A2VDDQ 2 2 2
W8 GENERICB A2VDDQ AE17
W9 0.1U_0402_10V6K
GENERICC VGA@
W7 GENERICD A2VSSQ AE19
1

AD10 GENERICE_HPD4 (1.8V@40mA VDD2DI)

1

R883 +VDD2DI
@ 10K_0402_5% R884 AC14 AG13 1 R885 2 L107
<11,22> HDMI_DET HPD1 R2SET
499_0402_1% 2 1 VGA@ 1U_0402_6.3V4Z
VGA@ 715_0402_1% BLM18PG121SN1D_0603 1 1 1
2

GPIO23_CLKREQB VGA@ VGA@ C1107 C1108 C1109

2

AC16 DDC/AUX VGA@ 10U_0603_6.3V

VREFG 2 2 2
AE6
VGA@ DDC1CLK
DDC1DATA AE5
VGA_CRT_CLK <23>
VGA_CRT_DATA <23>
CRT 0.1U_0402_10V6K
1

1 0.1U_0402_10V6K VGA@
R886 C1110 AD2
249_0402_1% PLL/CLOCK AUX1P
AUX1N AD4 (3.3V@65mA A2VDD)
VGA@ +DPLL_PVDD AF14 +3.3V_DELAY L108 +A2VDD
2 DPLL_PVDD
AE14 AC11 VGA_HDMI_SCLK <22> HDMI
2

DPLL_PVSS DDC2CLK VGA@ 1U_0402_6.3V4Z

DDC2DATA AC13 VGA_HDMI_SDATA <22> 2 1
BLM18PG121SN1D_0603 1 1 1
B +DPLL_VDDC VGA@ C1111 C1112 C1113 B
AD14 DPLL_VDDC AUX2P AD13
VGA@ AD11
75_0402_1% AUX2N VGA@ 10U_0603_6.3V
1.8V 2 2 2
1 2 27MCLK AM28
<20> 27M_NSSC XTALIN
R887 XTALOUT AK28 AB22 PADT14
PAD T14 0.1U_0402_10V6K
XTALOUT NC1
2

AC22 PAD T13

PADT13 DO NOT INSTALL for M93-S3 VGA@
+3.3V_DELAY R888 NC2

100_0402_5% AE16
DDCAUX5P
1

VGA@ T4 AD16
<19> GPU_THERMAL_D+
1

R548 DPLUS THERMAL DDCAUX5N

<19> GPU_THERMAL_D- T2 DMINUS
@ 5.1K_0402_1% AC1 +3.3V_DELAY
DDC6CLK
DDC6DATA AC3
L109 VGA@ 1U_0402_6.3V4Z T9 PAD R5
2

TESTEN TS_FDO
+1.8VS 2 1 AD17 TSVDD NC_DDCAUX7P AD20
1 1 1 AC17 TSVSS NC_DDCAUX7N AC20

1
BLM18PG121SN1D_0603 C1114 C1115 C1116 @
1

VGA@ R890
R889 10U_0603_6.3V 0.1U_0402_10V6K 10K_0402_5%
5.1K_0402_1% VGA@ 2 2 2 VGA@
VGA@ (1.8V@20mA TSVDD)

2
216-0728002 A11 M92-S2_FCBGA631
2

VGA@ GPIO24_TRSTB

1
27MCLK @
R895
1

+1.8VS 1K_0402_5%
L102 (1.8V@120mA +DPLL_PVDD)
@ R896
@R896

2
1 2 VGA@ 1U_0402_6.3V4Z +DPLL_PVDD 1M_0402_5%
2

VGA@ MCK1608471YZF 0603 1 1 1 XTALOUT

C1092 C1093 C1094
10U_0603_6.3V6M @Y6
@ Y6
VGA@ 0.1U_0402_10V6K 4 3
2 2 2 VGA@ GND OUT
1 IN GND 2 1
1 @C1118
@ C1118

hexainf@hotmail.com
27MHz_16PF_6P27000126 22P_0402_50V8J
A
+1.1VS A
@C1117
@ C1117 2
L103 (1.1V@300mA +DPLL_VDDC) 2 22P_0402_50V8J
1 2 VGA@ 1U_0402_6.3V4Z +DPLL_VDDC Close to M92
MCK1608471YZF 0603 1 1 1
VGA@ C1095 C1096 C1097
10U_0603_6.3V6M
VGA@ 0.1U_0402_10V6K
2 2 2 VGA@

Security Classification Compal Secret Data Compal Electronics, Inc.

2007/10/11 200810/11 Title
Issued Date Deciphered Date SCHEMATICS,MB A5401
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401728 A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 04, 2009 Sheet 15 of 49
5 4 3 2 1
 5 4 3 2 1

MAA[12..0]
MAA[12..0] <18> MDA[0..63]
BA[2..0] <18> MDA[0..63]
BA[2..0] <18>

U64C U64G
(1.8V@200mA +DPE_VDD18)
+1.8VS +DPE_VDD18 DP E/F POWER DP A/B POWER
MDA0 K27 K17 MAA0 L110 VGA@
MDA1 DQA_0 MAA_0 MAA1 1U_0402_6.3V4Z +DPA_VDD18
J29 DQA_1 MAA_1 J20 2 1 AG15 DPE_VDD18#1 NC_DPA_VDD18#1 AE11
MDA2 H30 H23 MAA2 BLM18PG121SN1D_0603 AG16 AF11
MDA3 DQA_2 MAA_2 MAA3 VGA@ DPE_VDD18#2 NC_DPA_VDD18#2 +1.1VS
H32 DQA_3 MAA_3 G23 1 1 1
MDA4 MAA4 C1119 C1120 C1121 +DPF_VDD10 (1.1V@200mA +DPA_VDD10)

MEMORY INTERFACE
G29 DQA_4 MAA_4 G24
D MDA5 MAA5 VGA@ L111 D
F28 DQA_5 MAA_5 H24
MDA6 F32 J19 MAA6 10U_0603_6.3V 0.1U_0402_10V6K AG20 AF6 +DPA_VDD10 1U_0402_6.3V4Z 2 1
MDA7 DQA_6 MAA_6 MAA7 VGA@ 2 2 2 VGA@ DPE_VDD10#1 DPA_VDD10#1 BLM18PG121SN1D_0603
F30 DQA_7 MAA_7 K19 AG21 DPE_VDD10#2 DPA_VDD10#2 AF7
MDA8 C30 J14 MAA8 1 1 1 VGA@
MDA9 DQA_8 MAA_8 MAA9 C1122 C1123 C1124
F27 DQA_9 MAA_9 K14
MDA10 A28 J11 MAA10 +DPE_VDD18 AG14 AE1
MDA11 DQA_10 MAA_10 MAA11 +1.8VS R897 VGA@ VGA@ DPE_VSSR#1 DPA_VSSR#1 VGA@ 10U_0603_6.3V 0.1U_0402_10V6K
C28 DQA_11 MAA_11 J13 AH14 DPE_VSSR#2 DPA_VSSR#2 AE3
MDA12 MAA12 2 2 2 VGA@
E27 DQA_12 MAA_12 H11 1 2 0_0402_5% 1U_0402_6.3V4Z AM14 DPE_VSSR#3 DPA_VSSR#3 AG1
MDA13 G26 G11 BA2 1 1 1 AM16 AG6
MDA14 DQA_13 MAA_13/BA2 BA0 C1125 C1126 C1127 DPE_VSSR#4 DPA_VSSR#4
D26 DQA_14 MAA_14/BA0 J16 2 1 AM18 DPE_VSSR#5 DPA_VSSR#5 AH5
MDA15 F25 L15 BA1 @ L112
MDA16 DQA_15 MAA_15/BA1 BLM18PG121SN1D_0603 10U_0603_6.3V +DPF_VDD18
A25 DQA_16 DQMA#[7..0] <18>
MDA17 DQMA#0 VGA@ 2 2 2
C25 DQA_17 DQMA_0 E32
MDA18 E25 E30 DQMA#1 AF16 AE13
MDA19 DQA_18 DQMA_1 DQMA#2 0.1U_0402_10V6K DPF_VDD18#1 NC_DPB_VDD18#1
D24 DQA_19 DQMA_2 A21 AG17 DPF_VDD18#2 NC_DPB_VDD18#2 AF13
MDA20 E23 C21 DQMA#3 +1.1VS VGA@
MDA21 DQA_20 DQMA_3 DQMA#4 VGA@ +DPF_VDD10
F23 DQA_21 DQMA_4 E13
MDA22 D22 D12 DQMA#5 L2 1U_0402_6.3V4Z
MDA23 DQA_22 DQMA_5 DQMA#6
F21 DQA_23 DQMA_6 E3 2 1 AF22 DPF_VDD10#1 DPB_VDD10#1 AF8
MDA24 E21 F4 DQMA#7 BLM18PG121SN1D_0603 AG22 AF9
MDA25 DQA_24 DQMA_7 VGA@ DPF_VDD10#2 DPB_VDD10#2
D20 DQA_25 QSA[7..0] <18> 1 1 1
MDA26 F19 H28 QSA0 (1.1V@170mA +DPF_VDD10) C1128 C1129 C1130
MDA27 DQA_26 RDQSA_0 QSA1
A19 DQA_27 RDQSA_1 C27 AF23 DPF_VSSR#1 DPB_VSSR#1 AF10
MDA28 D18 A23 QSA2 10U_0603_6.3V 0.1U_0402_10V6K AG23 AG9
MDA29 DQA_28 RDQSA_2 QSA3 VGA@ 2 2 2 VGA@ DPF_VSSR#2 DPB_VSSR#2
F17 DQA_29 RDQSA_3 E19 AM20 DPF_VSSR#3 DPB_VSSR#3 AH8
MDA30 A17 E15 QSA4 AM22 AM6
MDA31 DQA_30 RDQSA_4 QSA5 DPF_VSSR#4 DPB_VSSR#4
C17 DQA_31 RDQSA_5 D10 AM24 DPF_VSSR#5 DPB_VSSR#5 AM8
MDA32 E17 D6 QSA6
MDA33 DQA_32 RDQSA_6 QSA7
D16 DQA_33 RDQSA_7 G5 QSA#[7..0] <18>
MDA34 F15 R898 R899
MDA35 DQA_34 QSA#0 VGA@ 150_0402_1% VGA@ 150_0402_1%
A15 DQA_35 WDQSA_0 H27
MDA36 D14 A27 QSA#1 1 2 AF17 AE10 1 2 (1.8V@20mA +DPA_PVDD)
C MDA37 DQA_36 WDQSA_1 QSA#2 +1.8VS DPEF_CALR DPAB_CALR +1.8VS C
F13 DQA_37 WDQSA_2 C23 (1.8V@20mA +DPE_PVDD)
MDA38 A13 C19 QSA#3 +DPE_PVDD
MDA39 DQA_38 WDQSA_3 QSA#4 L113 VGA@ VGA@ L114
C13 DQA_39 WDQSA_4 C15
MDA40 E11 E9 QSA#5 2 1 1U_0402_6.3V4Z AG18 DP PLL POWER AG8 +DPA_PVDD 1U_0402_6.3V4Z 2 1
MDA41 DQA_40 WDQSA_5 QSA#6 BLM18PG121SN1D_0603 DPE_PVDD DPA_PVDD BLM18PG121SN1D_0603
A11 DQA_41 WDQSA_6 C5 AF19 DPE_PVSS DPA_PVSS AG7
MDA42 C11 H4 QSA#7 VGA@ 1 1 1 1 1 1 VGA@
MDA43 DQA_42 WDQSA_7 C1131 C1132 C1133 +DPE_PVDD VGA@ 10U_0603_6.3V C1134 C1135 C1136
F11 DQA_43
MDA44 A9 L18 ODTA0
DQA_44 ODTA0 ODTA0 <18>
MDA45 C9 K16 ODTA1 10U_0603_6.3V VGA@ 0.1U_0402_10V6K AG19 AG10 +DPB_PVDD 0.1U_0402_10V6K
DQA_45 ODTA1 ODTA1 <18> 2 2 2 NC_DPF_PVDD DPB_PVDD 2 2 2 VGA@
MDA46 F9 VGA@ AF20 AG11
MDA47 DQA_46 CLKA0 NC_DPF_PVSS DPB_PVSS
D8 DQA_47 CLKA0 H26 CLKA0 <18>
MDA48 E7 H25 CLKA0#
DQA_48 CLKA0B CLKA0# <18>
MDA49 A7
MDA50 DQA_49 CLKA1
C7 DQA_50 CLKA1 G9 CLKA1 <18>
MDA51 CLKA1# 216-0728002 A11 M92-S2_FCBGA631
F7 DQA_51 CLKA1B H9 CLKA1# <18>
MDA52 A5 VGA@ (1.8V@20mA +DPB_PVDD) +1.8VS
MDA53 DQA_52 RASA#0
E5 DQA_53 RASA0B G22 RASA#0 <18>
MDA54 C3 G17 RASA#1 VGA@ L115
DQA_54 RASA1B RASA#1 <18>
MDA55 E1 1U_0402_6.3V4Z 2 1
MDA56 DQA_55 CASA#0 BLM18PG121SN1D_0603
G7 DQA_56 CASA0B G19 CASA#0 <18>
MDA57 G6 G16 CASA#1 1 1 1 VGA@
DQA_57 CASA1B CASA#1 <18>
MDA58 G1 C1137 C1138 C1139
MDA59 DQA_58 CSA0#
G3 DQA_59 CSA0B_0 H22 CSA0# <18> (For future use only)
MDA60 J6 J22 0.1U_0402_10V6K
MDA61 DQA_60 CSA0B_1 +1.8VS 10U_0603_6.3V 2 2 2 VGA@
J1 DQA_61
MDA62 J3 G13 CSA1# (1.8V@120mA +DPLL_PVDD) VGA@
+1.5VS DQA_62 CSA1B_0 CSA1# <18> L126
MDA63 J5 K13
DQA_63 CSA1B_1 @ 1U_0402_6.3V4Z +DPA_VDD18
1 2
+VDD_MEM15_REFD K26 K20 CKEA0
MVREFDA CKEA0 CKEA0 <18>
+VDD_MEM15_REF1 J26 J17 CKEA1 @ MCK1608471YZF 0603 1 1 1
MVREFSA CKEA1 CKEA1 <18>
C1254 C1253 C1255
@ 243_0402_1%1 R900 2 J25 G25 WEA#0 @ 10U_0603_6.3V6M
B NC_MEM_CALRN0 WEA0B WEA#0 <18> B
@ 243_0402_1%1 R901 2 K7 H10 WEA#1 @ 0.1U_0402_10V6K
NC_MEM_CALRN1 WEA1B WEA#1 <18> +1.5VS 2 2 2
VGA@ 243_0402_1%1 R902 2 J8 AB16
@ 243_0402_1%1 R903 MEM_CALRP1 RSVD#1 PAD T10
2 K25 NC_MEM_CALRP0 RSVD#2 G14
G20 PAD T11
DRAM_RST# RSVD#3 PAD T12
L10 DRAM_RST
1

K8 R316
CLKTESTA 4.7K_0402_5%
L7 CLKTESTB
VGA@
0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1 VGA@
2

VGA@ 1U_0402_6.3V4Z

216-0728002 A11 M92-S2_FCBGA631 DRAM_RST#

2 2 VGA@ <18> DRAM_RST#
1

VGA@
C2

C3

R317
2

C337

1
R904 R905
51_0402_1% 51_0402_1%
2

VGA@ VGA@
2
1
@ 4.7K_0402_5%

+1.5VS +1.5VS

Close to K26 Close to J26

1

R906 R907
100_0402_1% 100_0402_1%
VGA@ VGA@
2

A +VDD_MEM15_REFD +VDD_MEM15_REF1 A

1 1
1

C1140 C1141
R908 0.1U_0402_16V4Z R909 0.1U_0402_16V4Z
100_0402_1% VGA@ 100_0402_1% VGA@
VGA@ 2 VGA@ 2

Security Classification Compal Secret Data Compal Electronics, Inc.

2

Issued Date 2007/10/11 Deciphered Date 200810/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401728 A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 04, 2009 Sheet 16 of 49
5 4 3 2 1
 5 4 3 2 1

U64E

AA27 PCIE_VSS#1 GND#1 A3

AB24 PCIE_VSS#2 GND#2 A30
D D
AB32 PCIE_VSS#3 GND#3 AA13
AC24 PCIE_VSS#4 GND#4 AA16
AC26 PCIE_VSS#5 GND#5 AB10
+1.5VS U64D AC27 AB15
PCIE_VSS#6 GND#6
(1.5V@2200mA) AD25 PCIE_VSS#7 GND#7 AB6
VGA@ VGA@ MEM I/O +1.8VS AD32 AC9
VGA@ 1U_0402_6.3V4Z VGA@ 1U_0402_6.3V4Z PCIE VGA@ L116 PCIE_VSS#8 GND#8
(1.8V@500mA +PCIE_GDDR) AE27 PCIE_VSS#9 GND#9 AD6
1U_0402_6.3V4Z 1U_0402_6.3V4Z H13 AB23 +PCIE_GDDR 10U_0603_6.3V 1 2 AF32 AD8
VDDR1#1 PCIE_VDDR#1 MCK2012221YZF 0805 PCIE_VSS#10 GND#10
H16 VDDR1#2 PCIE_VDDR#2 AC23 1 1 1 AG27 PCIE_VSS#11 GND#11 AE7

C1145

C1151

C1152
1 1 1 1 1 1 1 1 H19 AD24 VGA@ AH32 AG12
VDDR1#3 PCIE_VDDR#3 PCIE_VSS#12 GND#12
C1146

C1147

C1143

C1144

C1142

C1148

C1149

C1150
J10 VDDR1#4 PCIE_VDDR#4 AE24 K28 PCIE_VSS#13 GND#13 AH10
J23 VDDR1#5 PCIE_VDDR#5 AE25 K32 PCIE_VSS#14 GND#14 AH28
2 0.1U_0402_10V6K
2 2
J24 VDDR1#6 PCIE_VDDR#6 AE26 L27 PCIE_VSS#15 GND#15 B10
2 2 2 2 2 2 2 2 VGA@ 1U_0402_6.3V4Z
J9 VDDR1#7 PCIE_VDDR#7 AF25 M32 PCIE_VSS#16 GND#16 B12
VGA@ 1U_0402_6.3V4Z 1U_0402_6.3V4Z K10 AG26 VGA@ +1.1VS N25 B14
1U_0402_6.3V4Z VGA@ 1U_0402_6.3V4Z VDDR1#8 PCIE_VDDR#8 PCIE_VSS#17 GND#17
K23 VDDR1#9 (1.1V@2000mA +PCIE_VDDC) N27 PCIE_VSS#18 GND#18 B16
VGA@ VGA@ VGA@ VGA@ K24 VGA@ P25 B18
10U_0603_6.3V 10U_0603_6.3V VDDR1#10 +PCIE_VDDC VGA@ 1U_0402_6.3V4Z1U_0402_6.3V4Z VGA@ 10U_0603_6.3V PCIE_VSS#19 GND#19
K9 VDDR1#11 PCIE_VDDC#1 L23 P32 PCIE_VSS#20 GND#20 B20
1 1 1 1 L11 VDDR1#12 PCIE_VDDC#2 L24 1 1 1 1 1 1 R27 PCIE_VSS#21 GND#21 B22
C1153

C1154

C1155

C1156

C1157

C1158

C1159

C1160

C1161

C1162
L12 VDDR1#13 PCIE_VDDC#3 L25 T25 PCIE_VSS#22 GND#22 B24
L13 VDDR1#14 PCIE_VDDC#4 L26 T32 PCIE_VSS#23 GND#23 B26
L20 VDDR1#15 PCIE_VDDC#5 M22 U25 PCIE_VSS#24 GND#24 B6
2 2 2 2 2 2 2 2 2 2
L21 VDDR1#16 PCIE_VDDC#6 N22 U27 PCIE_VSS#25 GND#25 B8
10U_0603_6.3V 10U_0603_6.3V L22 N23 0.1U_0402_10V6K 1U_0402_6.3V4Z 1U_0402_6.3V4Z V32 C1
VGA@ VGA@ VDDR1#17 PCIE_VDDC#7 VGA@ VGA@ VGA@ PCIE_VSS#26 GND#26
PCIE_VDDC#8 N24 W25 PCIE_VSS#27 GND#27 C32
+1.8VS +VDDC_CT R22 +VGA_CORE W26 E28
PCIE_VDDC#9 PCIE_VSS#28 GND#28
PCIE_VDDC#10 T22 W27 PCIE_VSS#29 GND#29 F10
VGA@ LEVEL U22 Y25 F12
L117
10U_0603_6.3V TRANSLATION PCIE_VDDC#11 PCIE_VSS#30 GND#30
(1.8V@110mA +VDDC_CT) PCIE_VDDC#12 V22 (+VGA_CORE@9000mA +VDDC) Y32 PCIE_VSS#31 GND#31 F14
2 1 AA20 VGA@ F16
BLM18PG121SN1D_0603 1 VDD_CT#1 VGA@ 1U_0402_6.3V4Z VGA@ 1U_0402_6.3V4Z GND#32
1 1 AA21 VDD_CT#2 GND#33 F18
C1163

C1164

C1165

VGA@ AB20 AA15 1U_0402_6.3V4Z VGA@ 1U_0402_6.3V4Z VGA@ 1U_0402_6.3V4Z F2

C VDD_CT#3 CORE VDDC#1 GND#34 C
AB21 VDD_CT#4 VDDC#2 N15 1 GND#35 F20
VDDC#3 N17 1 1 1 1 1 1 1 1 1 1 M6 GND#56 GND#36 F22
2 2 2 0.1U_0402_10V6K

C1166

C1167

C1168

C1169

C1170

C1171

C1172

C1173

C1174

C1175
R13 + C1176 N11 F24
+3.3V_DELAY 1U_0402_6.3V4Z VGA@ I/O VDDC#4 330U_D2E_2.5VM_R9M GND#57 GND#37
VDDC#5 R16 N12 GND#58 GND#38 F26
VGA@ AA17 R18 VGA@ N13 F6
VGA@ VDDR3#1 VDDC#6 2 2 2 2 2 2 2 2 2 2 2 GND#59 GND#39
AA18 R21 N16 F8
10U_0603_6.3V
VGA@ 1 1
1U_0402_6.3V4Z
1 1
AB17
AB18
VDDR3#2
VDDR3#3
VDDR3#4
VDDC#7
VDDC#8
VDDC#9
T12
T15
1U_0402_6.3V4Z
VGA@
VGA@ 1U_0402_6.3V4Z VGA@ 1U_0402_6.3V4Z
1U_0402_6.3V4Z VGA@ 1U_0402_6.3V4Z
N18
N21
GND#60
GND#61
GND#62
GND GND#40
GND#41
GND#42
G10
G27
C1177

C1178

C1179

C1180

1 2 T17 VGA@ P6 G31

<15> TESTEN VDDC#10 GND#63 GND#43
R9@ 0_0402_5% T20 P9 G8
VDDC#11 GND#64 GND#44
1 2 U11 VDDR5#1 VDDC#12 U13 R12 GND#65 GND#45 H14
2 2 2 2 R2 1VGA@ 0_0402_5% VGA@ VGA@ VGA@
2 U12 VDDR5#2 VDDC#13 U16 R15 GND#66 GND#46 H17
1U_0402_6.3V4Z 1U_0402_6.3V4Z +VDDR5 R3 1VGA@ 0_0402_5%
2 V11 U18 VGA@ 10U_0603_6.3V 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z R17 H2
VGA@ VGA@ R12 1VGA@ 0_0402_5% VDDR5#3 VDDC#14 GND#67 GND#47
2 V12 VDDR5#4 VDDC#15 U21 R20 GND#68 GND#48 H20
POWER
+VDDR4 R7 1 @ 0_0402_5%
2 V15 1 1 1 1 1 1 1 1 T13 H6
VDDC#16 GND#69 GND#49

C1185

C1186

C1187

C1188

C1189

C1190

C1191

C1192
R13 VGA@ 0_0402_5% V17 T16 J27
VDDC#17 GND#70 GND#50
1 2 AA11 VDDR4#1 VDDC#18 V20 T18 GND#71 GND#51 J31
R300 1@ 150_0402_1%
2 AA12 V21 T21 K11
R11 1VGA@ 0_0402_5% VDDR4#2 VDDC#19 2 2 2 2 2 2 2 2 GND#72 GND#52
2 Y11 VDDR4#3 VDDC#20 Y13 T6 GND#73 GND#53 K2
R14 VGA@ 0_0402_5% Y12 Y16 10U_0603_6.3V 10U_0603_6.3V 1U_0402_6.3V4Z 1U_0402_6.3V4Z U15 K22
+1.5VS VDDR4#4 VDDC#21 VGA@ VGA@ L124 VGA@ VGA@ GND#74 GND#54
VDDC#22 Y18 U17 GND#75 GND#55 K6
L119 VGA@ VGA@ Y21 2 1 U20
VDDC#23 GND#76

1U_0402_6.3V4Z
2 1 1U_0402_6.3V4Z 1U_0402_6.3V4Z MEM CLK 1 1 BLM18PG121SN1D_0603 U3 GND#77

VGA@ C1256

VGA@ C1257
10U_0603_6.3V
BLM18PG121SN1D_0603 1 1 L17 VGA@ L127 For S2: Install L124 and DO U9
VDDRHA GND#78
C1194

C1195

VGA@ 2 1 not Install L127 V13

+1.1VS GND#79
L16 ISOLATED @ BLM18PG121SN1D_0603 V16
VSSRHA CORE I/O 2 2 For S3: Install L127 and DO GND#80
V18 GND#81
+1.8VS 2 2 not Install L124
VDDCI#1 M13 V6 GND#82
L121 PLL M15 Y10 A32
VGA@ 1U_0402_6.3V4Z +PCIE_PVDD VDDCI#2 GND#83 VSS_MECH#1
2 1 AM30 PCIE_PVDD VDDCI#3 M16 Y15 GND#84 VSS_MECH#2 AM1
BLM18PG121SN1D_0603 1 1 1 M17 Y17 AM32
VDDCI#4 GND#85 VSS_MECH#3
C1196

C1197

C1198

VGA@ M18 VGA@ VGA@ (+VGA_CORE@2000mA +VDDCI) Y20

B VDDCI#5 +VDDCI 1U_0402_6.3V4Z 10U_0603_6.3V GND#86 B
L8 NC_MPV18 VDDCI#6 M20 1 2 Y6 GND#87
M21 L120
+VGA_CORE 2 2 2 VDDCI#7 MCK2012221YZF 0805
VDDCI#8 N20 1 1 1 1
C1199

C1200

C1201

C1202
VGA@ 10U_0603_6.3V 0.1U_0402_10V6K H7 VGA@
L122 VGA@ NC_SPV18
VGA@ 1U_0402_6.3V4Z +SPV10 216-0728002 A11 M92-S2_FCBGA631
1 2 H8 SPV10
MCK1608471YZF 0603 2 2 2 2 VGA@
VGA@ 1 1 1 J7 VGA@ 1U_0402_6.3V4Z1U_0402_6.3V4Z
SPVSS
C1203

C1204

C1205

VGA@

+3.3V_DELAY Q73
2 2 2 BACK BIAS
VGA@ 10U_0603_6.3V
VGA@ 0.1U_0402_10V6K

S
M11 1 3

D
BBP#1 +3VS
M12 BBP#2
+VGA_CORE VGA@ 1U_0402_6.3V4Z SI2301BDS_SOT23

2
1 1 VGA@ R910

G
2
C1206

C1207

100K_0402_5%
VGA@
216-0728002 A11 M92-S2_FCBGA631
2 2 VGA@

1
0.1U_0402_10V6K
VGA@

1
D
+3VS 1 2 2 Q74
+1.8VS R911 4.7K_0402_5% G
VGA@ 1U_0402_6.3V4Z +VDDR4 VGA@ S 2N7002_SOT23-3

3
1 1 1 VGA@
C1209

C1210

C1211

L123 1
2 1 C1208
BLM18PG121SN1D_0603 0.1U_0402_10V6K

hexainf@hotmail.com
A VGA@ 2 2 2 VGA@ A
VGA@ 10U_0603_6.3V 0.1U_0402_10V6K 2
VGA@
+1.8VS
VGA@ 1U_0402_6.3V4Z +VDDR5
1 1 1
C1181

C1182

C1183

L118
2 1
BLM18PG121SN1D_0603
VGA@ 2 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/11 Deciphered Date 200810/11 Title
VGA@ 10U_0603_6.3V 0.1U_0402_10V6K
VGA@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401728 A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 04, 2009 Sheet 17 of 49
5 4 3 2 1
 5 4 3 2 1

U65 U66 U67 U68

VREFC_A1 M8 E3 MDA4 VREFC_A2 M8 E3 MDA10 VREFC_A3 M8 E3 MDA40 VREFC_A4 M8 E3 MDA63

VREFD_Q1 VREFCA DQL0 MDA6 VREFD_Q2 VREFCA DQL0 MDA12 VREFD_Q3 VREFCA DQL0 MDA45 VREFD_Q4 VREFCA DQL0 MDA57
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 MDA1 F2 MDA8 F2 MDA44 F2 MDA58
MAA0 DQL2 MDA2 MAA0 DQL2 MDA13 MAA0 DQL2 MDA43 MAA0 DQL2 MDA56
N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8
MAA1 P7 H3 MDA5 MAA1 P7 H3 MDA11 MAA1 P7 H3 MDA42 MAA1 P7 H3 MDA62
MAA2 A1 DQL4 MDA0 MAA2 A1 DQL4 MDA15 MAA2 A1 DQL4 MDA47 MAA2 A1 DQL4 MDA60
P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8
MAA3 N2 G2 MDA7 MAA3 N2 G2 MDA9 MAA3 N2 G2 MDA41 MAA3 N2 G2 MDA61
MAA4 A3 DQL6 MDA3 MAA4 A3 DQL6 MDA14 MAA4 A3 DQL6 MDA46 MAA4 A3 DQL6 MDA59
P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7
MAA5 P2 MAA5 P2 MAA5 P2 MAA5 P2
MAA6 A5 MAA6 A5 MAA6 A5 MAA6 A5
R8 A6 R8 A6 R8 A6 R8 A6
MAA7 R2 D7 MDA18 MAA7 R2 D7 MDA28 MAA7 R2 D7 MDA34 MAA7 R2 D7 MDA50
MAA8 A7 DQU0 MDA19 MAA8 A7 DQU0 MDA26 MAA8 A7 DQU0 MDA35 MAA8 A7 DQU0 MDA54
T8 A8 DQU1 C3 T8 A8 DQU1 C3 T8 A8 DQU1 C3 T8 A8 DQU1 C3
MAA9 R3 C8 MDA16 MAA9 R3 C8 MDA29 MAA9 R3 C8 MDA38 MAA9 R3 C8 MDA51
D MAA10 A9 DQU2 MDA22 MAA10 A9 DQU2 MDA27 MAA10 A9 DQU2 MDA36 MAA10 A9 DQU2 MDA52 D
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
MDA[0..63] MAA11 R7 A7 MDA20 MAA11 R7 A7 MDA30 MAA11 R7 A7 MDA37 MAA11 R7 A7 MDA48
<16> MDA[0..63] MAA12 A11 DQU4 MDA23 MAA12 A11 DQU4 MDA24 MAA12 A11 DQU4 MDA32 MAA12 A11 DQU4 MDA55
N7 A12 DQU5 A2 N7 A12 DQU5 A2 N7 A12 DQU5 A2 N7 A12 DQU5 A2
T3 B8 MDA17 T3 B8 MDA31 T3 B8 MDA39 T3 B8 MDA49
A13 DQU6 MDA21 A13 DQU6 MDA25 A13 DQU6 MDA33 A13 DQU6 MDA53
T7 A14 DQU7 A3 T7 A14 DQU7 A3 T7 A14 DQU7 A3 T7 A14 DQU7 A3
M7 A15/BA3 M7 A15/BA3 M7 A15/BA3 M7 A15/BA3
+1.5VS +1.5VS +1.5VS +1.5VS

M2 B2 BA0 M2 B2 BA0 M2 B2 BA0 M2 B2

MAA[12..0] <16> BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
N8 D9 BA1 N8 D9 BA1 N8 D9 BA1 N8 D9
<16> MAA[12..0] <16> BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
M3 G7 BA2 M3 G7 BA2 M3 G7 BA2 M3 G7
<16> BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
VDD K2 VDD K2 VDD K2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
J7 N9 CLKA0 J7 N9 J7 N9 CLKA1 J7 N9
<16> CLKA0 CK VDD CK VDD <16> CLKA1 CK VDD CK VDD
K7 R1 CLKA0# K7 R1 K7 R1 CLKA1# K7 R1
DQMA#[7..0] <16> CLKA0# CK VDD CK VDD <16> CLKA1# CK VDD CK VDD
K9 R9 CKEA0 K9 R9 K9 R9 CKEA1 K9 R9
<16> DQMA#[7..0] <16> CKEA0 CKE/CKE0 VDD +1.5VS CKE/CKE0 VDD +1.5VS <16> CKEA1 CKE/CKE0 VDD +1.5VS CKE/CKE0 VDD +1.5VS

K1 A1 ODTA0 K1 A1 K1 A1 ODTA1 K1 A1
<16> ODTA0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ <16> ODTA1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
L2 A8 CSA0# L2 A8 L2 A8 CSA1# L2 A8
<16> CSA0# CS/CS0 VDDQ CS/CS0 VDDQ <16> CSA1# CS/CS0 VDDQ CS/CS0 VDDQ
J3 C1 RASA#0 J3 C1 J3 C1 RASA#1 J3 C1
QSA[7..0] <16> RASA#0 RAS VDDQ RAS VDDQ <16> RASA#1 RAS VDDQ RAS VDDQ
K3 C9 CASA#0 K3 C9 K3 C9 CASA#1 K3 C9
<16> QSA[7..0] <16> CASA#0 CAS VDDQ CAS VDDQ <16> CASA#1 CAS VDDQ CAS VDDQ
L3 D2 WEA#0 L3 D2 L3 D2 WEA#1 L3 D2
<16> WEA#0 WE VDDQ WE VDDQ <16> WEA#1 WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSA0 F3 H2 QSA1 F3 H2 QSA5 F3 H2 QSA7 F3 H2
QSA2 DQSL VDDQ QSA3 DQSL VDDQ QSA4 DQSL VDDQ QSA6 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9
QSA#[7..0]
<16> QSA#[7..0]
DQMA#0 E7 A9 DQMA#1 E7 A9 DQMA#5 E7 A9 DQMA#7 E7 A9
DQMA#2 DML VSS DQMA#3 DML VSS DQMA#4 DML VSS DQMA#6 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3
C C
VSS E1 VSS E1 VSS E1 VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
QSA#0 G3 J2 QSA#1 G3 J2 QSA#5 G3 J2 QSA#7 G3 J2
QSA#2 DQSL VSS QSA#3 DQSL VSS QSA#4 DQSL VSS QSA#6 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8
VSS M1 VSS M1 VSS M1 VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
T2 P9 DRAM_RST# T2 P9 DRAM_RST# T2 P9 DRAM_RST# T2 P9
<16> DRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
VSS T1 VSS T1 VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
R912 L1 B9 R913 L1 B9 R914 L1 B9 R915 L1 B9
NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ
240_0402_1% J9 NC/CE1 VSSQ D1 240_0402_1% J9 NC/CE1 VSSQ D1 240_0402_1% J9 NC/CE1 VSSQ D1 240_0402_1% J9 NC/CE1 VSSQ D1
VGA@ L9 D8 VGA@ L9 D8 VGA@ L9 D8 VGA@ L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2 E2 E2
2

2
VSSQ VSSQ VSSQ VSSQ
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9

96-BALL 96-BALL 96-BALL 96-BALL

SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
VRAM@ VRAM@ VRAM@ VRAM@

B +1.5VS +1.5VS +1.5VS +1.5VS +1.5VS +1.5VS +1.5VS +1.5VS B

1

1
R916 R917 R918 R919 R920 R921 R922 R923
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
VGA@ VGA@ VGA@ VGA@ VGA@ 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
VGA@ VGA@ VGA@
2

2
VREFD_Q1 VREFC_A1 VREFC_A2 VREFD_Q2 VREFC_A3 VREFD_Q3 VREFC_A4 VREFD_Q4
1

1
0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
C1212

C1213

C1214

C1215

C1216

C1217

C1218

C1219
1 1 1 1 1 1 1 1
0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
R924 R925 R926 R927 R928 R929 R930 R931
4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
VGA@ VGA@ VGA@ VGA@ VGA@ 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
2 2 2 2 2 VGA@ 2 VGA@ 2 VGA@ 2
2

2
VGA@

VGA@

VGA@
VGA@

VGA@

VGA@

VGA@

VGA@
+1.5VS
+1.5VS VGA@ VGA@
VGA@ VGA@ VGA@ 1U_0402_6.3V4Z VGA@ 1U_0402_6.3V4Z VGA@
VGA@ VGA@ VGA@ VGA@ 1U_0402_6.3V4Z VGA@ 1U_0402_6.3V4Z VGA@ 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
+1.5VS 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

C1230

C1243

C1231

C1232

C1244

C1233

C1245

C1234

C1235

C1236
1 1 1 1 1 1 1 1 1 1
C1238

C1225

C1239

C1240

C1241

C1226

C1227

C1228

C1242

C1229
CLKA0 1 2 C1220 C1221 C1222 C1237 C1223 C1224
R932 56_0402_1% CLKA1 1 2
A VGA@ R933 56_0402_1% 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 A
VGA@ 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 2 2 2 2 2 2 2 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
CLKA0# 1 2 VGA@ VGA@ VGA@ 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z VGA@ 1U_0402_6.3V4Z VGA@ 1U_0402_6.3V4Z VGA@
R934 56_0402_1% CLKA1# 1 2 VGA@ 1U_0402_6.3V4Z VGA@ 1U_0402_6.3V4Z VGA@ VGA@ VGA@
VGA@ 1 R935 56_0402_1% 1 VGA@ VGA@
C1246 VGA@ C1247
0.01U_0402_25V7K 0.01U_0402_25V7K
VGA@ VGA@
2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/09 Deciphered Date 2010/01/09 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401728 A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 04, 2009 Sheet 18 of 49
5 4 3 2 1
 5 4 3 2 1

CONFIGURATION STRAPS
STRAPS +3.3V_DELAY
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET

STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS RECOMMENDED SETTINGS

<15> GPU_GPIO0 GPU_GPIO0 @ R936 2 1 10K_0402_5%
<15> GPU_GPIO1 GPU_GPIO1 @ R937 2 1 10K_0402_5%
<15> GPU_GPIO2 GPU_GPIO2 @ R938 2 1 10K_0402_5% TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING 1
<15> SOUT_GPIO8 SOUT_GPIO8 @ R939 2 1 10K_0402_5%

TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED 1

<15> GPU_GPIO9 GPU_GPIO9 @ R940 2 1 10K_0402_5%
D GPU_GPIO11 R941 10K_0402_5% D
<15> GPU_GPIO11 2 1
<15> GPU_GPIO12 GPU_GPIO12 @ R942 2 1 10K_0402_5% BIF_GEN2_EN_A GPIO2 PCIE GNE2 ENABLED 1
GPU_GPIO13 @ R943 10K_0402_5%
<15> GPU_GPIO13 2 1 VSYNC_DAC1 and HSYNC_DAC1
pull up to HDMI & DISPLAYPORT BIF_CLK_PM_EN GPIO8 BIF_CLK_PM_EN 0

<15,23> VGA_CRT_VSYNC R944 2 1 10K_0402_5% AUDIO funciton

<15,23> VGA_CRT_HSYNC R945 2 1 10K_0402_5% BIF_VGA DIS GPIO9 VGA ENABLED 0
<15> VSYNC_DAC2 @ R946 2 1 10K_0402_5%
<15> HSYNC_DAC2 @ R947 2 1 10K_0402_5% 0
BIF_RX_PLL_CALIB_BP GPIO21

GPIO5_AC_BATT TEST
BIOS_ROM_EN GPIO_22_ROMCSB 1

+3.3V_DELAY ROMIDCFG(2:0) GPIO[13:11] BIF_RX_PLL_CALIB_BP 0 0 1

VIP_DEVICE_STRAP_ENA V2SYNC ENABLE EXTERNAL BIOS ROM 0

1

R948
10K_0402_5% SMS_EN_HARD H2SYNC SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT 0
VGA@
IGNORE VIP DEVICE STRAPS
2

+3VS CCBYPASS GENERICC 0

R949
10K_0402_5% AUD[1] AUD[0]
VGA@ AUD[1] HSYNC 0 0 No audio function
0 1 Audio for DisplayPort and HDMI if dongle is detected XX
2

AUD[0] VSYNC 1 0 Audio for DisplayPort only

1 1 Audio for both DisplayPort and HDMI
C EC_SMB_CK2_PX C
6 1 EC_SMB_CK2 <6,33>
5

Q75A
2N7002DW-T/R7_SOT363-6
EC_SMB_DA2_PX VGA@ 3 4 EC_SMB_DA2 <6,33>
AMD RESERVED CONFIGURATION STRAPS
Q75B ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
2N7002DW-T/R7_SOT363-6
VGA@ THEY MUST NOT CONFLICT DURING RESET

H2SYNC GENERICC

PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
+3.3V_DELAY THEY MUST NOT CONFLICT DURING RESET
VGA Thermal Sensor
2 GPIO_28_TDO GPIO21_BB_EN
C1248
VGA@
0.1U_0402_16V4Z
Closed to GPU
1
U69
1 8 EC_SMB_CK2_PX
VRAM_ID0=VRAM_ID0_0
VDD SCLK
EC_SMB_DA2_PX
VRAM_ID1=VRAM_ID1_1
<15> GPU_THERMAL_D+ 2 D+ SDATA 7
C1249 VGA@ 2200P_0402_50V7K VRAM_ID2=VRAM_ID2_2
1 2 3 D- ALERT# 6 THM_ALERT# <15>
VRAM_ID3=VRAM_ID3_3
4 5 +3.3V_DELAY
B
<15> GPU_THERMAL_D- THERM# GND B
1 2 STRAPS PIN GPU Project VRAM size Vendor Part Number# Compal Part Number# VRAM_ID 3,2,1,0
ADM1032ARMZ REEL_MSOP8 R950 VGA@ 4.7K_0402_5%
VGA@ JM51_PU 512MB(x4) Samsung 64Mx16 1.5V SA000035700 0000
Change to SA010320120 0001
M92 S2-LP JM51_PU 512MB(x4) Hynix 64Mx16 1.5V SA000032400 0010
0011
DVPDATA 0100
2 1 +1.8VS 2 1 +1.8VS VRAM_ID[3:0] (3,2,1,0)
R951 @ 10K_0402_5% R952 @ 10K_0402_5% 0101
VRAM_ID0 <15> VRAM_ID1 <15>

Internal pull low

2 1 +1.8VS 2 1 +1.8VS
R953 @ 10K_0402_5% R954 @ 10K_0402_5%
VRAM_ID2 <15> VRAM_ID3 <15>

hexainf@hotmail.com
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/10/11 Deciphered Date 200810/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401728 A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 04, 2009 Sheet 19 of 49
5 4 3 2 1
 5 4 3 2 1

+3VS_CLK
L41
+3VS 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1 1 1 1 1 1 1
FBMA-L11-201209-221LMA30T_0805 C483 C476 C480 C526 C479 C498 C511 C477 C508 C528 C474

+1.2V_HT +VDDCLK_IO 22U_0805_10V4Z 1U_0402_6.3V4Z

2 2 2 2 2 2 2 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
L39
1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1 1 1 1U CLOSE PIN 69
FBMA-L11-201209-221LMA30T_0805 C432 C471 C475 C516 C530 C529 C527

D D
2 2 2 2 2 2 2
22U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

L40
+3VS 1 2 +3VS_CLKVDDA
+3VS_CLK
FBMA-L11-201209-221LMA30T_0805
1 1 U18

1
C463
CLK_XTAL_OUT 22U_0805_10V4Z C473 R178
2 2
0.1U_0402_16V4Z ICS 9LPRS488 8.2K_0402_5%
CLK_XTAL_IN 49 1
VDDA SMBCLK SB_CK_SCLK <8,9,25,31>
48 2

2
GNDA SMBDAT SB_CK_SDAT <8,9,25,31>
SRC_SLOW
+3VS_CLK 62 41 SRC_SLOW R430
VDDREF SB_SRC_SLOW# 261_0402_1%
Y1 66 GNDREF

1
2 1 1 2
2 1 C500 0.1U_0402_16V4Z 47.5_0402_1% R177
+VDDCLK_IO 12 56 CPUCLK_EXT_R R428 1 2 @ 8.2K_0402_5%
VDDSRC_IO CPUKG0T_LPRS CLK_CPU_BCLK <6>
14.31818MHZ_20P_6X14300202 18 55 CPUCLK#_EXT_R R429 1 2 CPU
VDDSRC_IO CPUKG0C_LPRS CLK_CPU_BCLK# <6>
1 1 28

2
C518 C517 VDDATIG_IO 47.5_0402_1%
37 VDDSB_SRC_IO
53 VDDCPU_IO HTT0T_LPRS / 66 M 60 CLK_NBHT <11>
27P_0402_50V8J 27P_0402_50V8J +3VS_CLK 59
2 2 HTT0C_LPRS / 66 M CLK_NBHT# <11>
C C
+3VS_CLK 3 VDDDOT
17 VDDSRC SB_SRC0T_LPRS 40
Routing the trace at least 10mil 29 VDDATIG SB_SRC0C_LPRS 39
R175 8.2K_0402_5%

R219 8.2K_0402_5%

R176 8.2K_0402_5%

38 VDDSB_SRC
44 VDDSATA
2

54 VDDCPU SB_SRC1T_LPRS 35
ESD L45 61 34
VDDHTT SB_SRC1C_LPRS
1 2 69 VDD48
FBMA-L11-160808-601LMT 0603
C41 2 1 0.1U_0402_16V4Z 2 1 33 CLK_NBGFX <11>
1

C538 0.1U_0402_16V4Z ATIG0T_LPRS

ATIG0C_LPRS 32 CLK_NBGFX# <11> NB GFX
LAN <31> LAN_CLKREQ# 24 CLKREQ0 #
ATIG1T_LPRS 31 CLK_PCIE_VGA <14>
WWAN <31> WWAN_CLKREQ# 51 CLKREQ1# ATIG1C_LPRS 30 CLK_PCIE_VGA# <14> VGA
WLAN <31> MINI1_CLKREQ# 50 CLKREQ2#
ATIG2T_LPRS 26
43 CLKREQ3# ATIG2C_LPRS 25

CLK_NB_14.318M 42 CLKREQ4#
SRC0T_LPRS 23 CLK_PCIE_LAN <31>
RS780 1.1V 158R/90.0R SRC0C_LPRS 22 CLK_PCIE_LAN# <31> GLAN

For Tigris 27M_SEL 63 21

REF2/SEL_27 SRC1T_LPRS CLK_PCIE_WWAN <31>
SRC1C_LPRS 20 CLK_PCIE_WWAN# <31> WWAN
2 1 SEL_SATA 64
<24> SB710_CLK_14M R185 33_0402_5% REF1/SEL_SATA
1 2 CLK_14.318M 65 16
<11> CLK_NB_14.318M REF0/SEL_HTT66 SRC2T_LPRS CLK_PCIE_MINI1 <31>
R201 158_0402_1% 15 WLAN
For EMI SRC2C_LPRS CLK_PCIE_MINI1# <31>
B
1 2 2 1 NB CLOCK INPUT TABLE B
R187 90.9_0402_1% @ C870 22P_0402_50V8J
<30> CLK_48M_SD 2 1 CLK_48MHZ 71 48MHz_0 SRC3T_LPRS 14 NB CLOCKS RS740 RX780 RS780
R676 22_0402_5% 13
SRC3C_LPRS
2 1 CLK_48M 70 48MHz_1
HT_REFCLKP
<25> CLK_48M_USB R209 33_0402_5% 66M SE(SINGLE END) 100M DIFF 100M DIFF
10 HT_REFCLKN NC 100M DIFF 100M DIFF
SRC4T_LPRS CLK_SBLINK_BCLK <11>
SRC4C_LPRS 9 CLK_SBLINK_BCLK# <11> NB A LINK
CLK_XTAL_IN 67 REFCLK_P
X1 14M SE (3.3V) 14M SE (1.8V) 14M SE (1.1V)
CLK_XTAL_OUT 68 8 REFCLK_N NC NC vref
X2 SRC5T_LPRS
SRC5C_LPRS 7
+3VS_CLK GFX_REFCLK 100M DIFF 100M DIFF 100M DIFF(IN/OUT)*

6 46 GPP_REFCLK NC 100M DIFF NC

GNDDOT SRC6T/SATAT_LPRS CLK_SBSRC_BCLK <24>
11 GNDSRC SRC6C/SATAC_LPRS 45 CLK_SBSRC_BCLK# <24> SB RCLK
19 GPPSB_REFCLK 100M DIFF 100M DIFF 100M DIFF
GNDSRC
27 GNDATIG
2

36 5 CLK_SRC7T R210 1 @ 2 0_0402_5% VGA (Spread spectrum)

GNDSB_SRC SRC7T_LPRS/27MHz_SS 27M_SSC <15>
R200 R198 47 4 CLK_SRC7C R461 1 2 0_0402_5%
GNDSATA SRC7C_LPRS/27MHz_NS 27M_NSSC <15>
8.2K_0402_5% 8.2K_0402_5% 52 VGA@ VGA (Non spread spectrum)
@ GNDCPU
58 GNDHTT
72
1

GND48
73 GNDPAD PD# 57 2 1 +3VS_CLK
SEL_SATA R184 8.2K_0402_5%

27M_SEL
2

SLG8SP626VTR_QFN72_10x10
R186
8.2K_0402_5%
1st (SILEGO) : SA00001Z310 S IC SLG8SP626VTR QFN 72P CLK GEN
1

A
2nd (ICS) : SA000023H10 S IC ICS9LPRS488CKLFT MLF 72P CLK GEN A

1 single-ended 66MHz HTT output

SEL_HTT66 Security Classification Compal Secret Data Compal Electronics, Inc.
0* differential 100MHz HTT output 2008/10/06 2009/10/06 Title
Issued Date Deciphered Date
1* NON SPREAD 100M SATA SRC6 output 1 * NON SPREAD 27M and SPREAD 27M output
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
SEL_SATA 27M_SEL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0 SPREAD 100M SATA SRC6 output 0 differential spread SRC_7 output Custom A
* default
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 20 of 49
5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT

+LCDVDD

+3VALW +3VS

1
R254
W=60mils
300_0603_5%

1
1
R252 C579

2
100K_0402_5%
D 4.7U_0805_10V4Z D

6
2 TZOUT0+ VGA_TZOUT0+
2 3 VGA_TZOUT0+ <15>

2
TZOUT0- 1 4 VGA_TZOUT0-
VGA_TZOUT0- <15>

3
S
RP41 @ 0_0404_4P2R_5%
2N7002DW-T/R7_SOT363-6 G
AO3413_SOT23-3 TZOUT1+ VGA_TZOUT1+
2 2 1 2 1 4 VGA_TZOUT1+ <15>
Q32A R253 1K_0402_5% Q33 TZOUT1- 2 3 VGA_TZOUT1-
VGA_TZOUT1- <15>
1
D RP43 @ 0_0404_4P2R_5%

1
3
C578 +LCDVDD TZOUT2+ 1 4 VGA_TZOUT2+
VGA_TZOUT2+ <15>
W=60mils TZOUT2- 2 3 VGA_TZOUT2-
VGA_TZOUT2- <15>
UMA@ 0_0402_5% 0.1U_0402_16V4Z RP40 @ 0_0404_4P2R_5%
R36 2N7002DW-T/R7_SOT363-6 2 TZCLK+ VGA_TZCLK+
<11> UMA_ENVDD_R 1 2 5 1 4 VGA_TZCLK+ <15>
Q32B TZCLK- 2 3 VGA_TZCLK-
1 1 VGA_TZCLK- <15>

1
C582 C583 RP42 @ 0_0404_4P2R_5%

4
R508
2.7K_0402_5% 4.7U_0805_10V4Z 0.1U_0402_16V4Z
UMA@ 2 2
2

R35 1 2 TXOUT0+ 1 4 VGA_TXOUT0+

<15> VGA_ENVDD VGA_TXOUT0+ <15>
TXOUT0- 2 3 VGA_TXOUT0-
VGA_TXOUT0- <15>
1

VGA@ 0_0402_5% VGA@ RP21 0_0404_4P2R_5%

R251 TXOUT1+ 1 4 VGA_TXOUT1+
VGA_TXOUT1+ <15>
10K_0402_5% TXOUT1- 2 3 VGA_TXOUT1-
VGA_TXOUT1- <15>
VGA@ VGA@ RP22 0_0404_4P2R_5%
TXOUT2- 1 4 VGA_TXOUT2-
VGA_TXOUT2- <15>
2

TXOUT2+ 2 3 VGA_TXOUT2+
VGA_TXOUT2+ <15>
AMD Vari bright function VGA@ RP23 0_0404_4P2R_5%
TXCLK+ 1 4 VGA_TXCLK+
VGA_TXCLK+ <15>
TXCLK- 2 3 VGA_TXCLK-
+3VS +3VS VGA_TXCLK- <15>
VGA@ RP20 0_0404_4P2R_5%

C C
1

R501 R503 VGA_LCD_CLK <15>

@ 4.7K_0402_5% @ 4.7K_0402_5% +3VS +3VS
VGA_LCD_DATA <15>

1
2

INVT_PWM_R 2 Q50A

1
2N7002DW-T/R7_SOT363-6
6

R255 VGA@
4.7K_0402_5%

4
R500@ 0_0402_5% @ D24

6
1 2 2 5 RB751V_SOD323 5 Q50B
<15> VGA_DPST

2
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
1 2 Q52A Q52B 1 2 DISPOFF# VGA@
<11> UMA_ENBKL <33> BKOFF#
1

@ 2N7002DW-T/R7_SOT363-6
1

R502@ 0_0402_5%

3
R504 I2CC_SCL 1 4 GMCH_LCD_CLK GMCH_LCD_CLK <11>
@ 4.7K_0402_5% I2CC_SDA 2 3 GMCH_LCD_DATA GMCH_LCD_DATA <11>
UMA@ RP15 0_0404_4P2R_5%
TXOUT0- 1 4 GMCH_TXOUT0-
GMCH_TXOUT0- <11>
2

TXOUT0+ 2 3 GMCH_TXOUT0+
GMCH_TXOUT0+ <11>
UMA@ RP19 0_0404_4P2R_5%
TXOUT1- 1 4 GMCH_TXOUT1-
GMCH_TXOUT1- <11>
TXOUT1+ 2 3 GMCH_TXOUT1+
GMCH_TXOUT1+ <11>
UMA@ RP18 0_0404_4P2R_5%
TXOUT2+ 1 4 GMCH_TXOUT2+
GMCH_TXOUT2+ <11>
Add D2<SC300000B00> for ESD TXOUT2- 2 3 GMCH_TXOUT2-
GMCH_TXOUT2- <11>
UMA@ RP17 0_0404_4P2R_5%
20081114 TXCLK- GMCH_TXCLK-
1 4

USB20_P3_1 6
D2
3
LCD/PANEL BD. Conn. TXCLK+ 2
UMA@ RP16
3
0_0404_4P2R_5%
GMCH_TXCLK+
GMCH_TXCLK- <11>
GMCH_TXCLK+ <11>
CH3 CH2
B JLVDS1 B
42 41 TZOUT0- 1 4 GMCH_TZOUT0-
GND GND GMCH_TZOUT0- <11>
+3VS 5 2 +INVPWR_B+ 40 39 DAC_BRIG TZOUT0+ 2 3 GMCH_TZOUT0+
Vp Vn 40 39 DAC_BRIG <33> GMCH_TZOUT0+ <11>
38 37 INVT_PWM_R 1 2 RP5 @ 0_0404_4P2R_5%
38 37 INVT_PWM <33>
+3VS 36 35 DISPOFF# R514 TZOUT1- 2 3 GMCH_TZOUT1-
36 35 GMCH_TZOUT1- <11>
I2CC_SCL 34 33 +LCDVDD 0_0402_5% TZOUT1+ 1 4 GMCH_TZOUT1+
34 33 GMCH_TZOUT1+ <11>
4 1 USB20_N3_1 I2CC_SDA 32 31 RP6 @ 0_0404_4P2R_5%
CH4 CH1 32 31 TZOUT2- GMCH_TZOUT2-
@ CM1293-04SO_SOT23-6 TZOUT0-
30 30 29 29 W=60mils TZOUT2+
2 3
GMCH_TZOUT2+
GMCH_TZOUT2- <11>
28 28 27 27 1 4 GMCH_TZOUT2+ <11>
TZOUT0+ 26 25 TXOUT0- RP7 @ 0_0404_4P2R_5%
26 25 TXOUT0+ TZCLK- GMCH_TZCLK-
24 24 23 23 2 3 GMCH_TZCLK- <11>
TZOUT1+ 22 21 TZCLK+ 1 4 GMCH_TZCLK+
22 21 GMCH_TZCLK+ <11>
Add L8<SM0700001310> for EMI TZOUT1- 20 19 TXOUT1- RP8 @ 0_0404_4P2R_5%
20 19 TXOUT1+
20081114 18 18 17 17
TZOUT2+ 16 15
TZOUT2- 16 15 TXOUT2+
1 2 14 14 13 13
R147 @ 0_0402_5% 12 11 TXOUT2-
TZCLK- 12 11
10 10 9 9
L17 TZCLK+ 8 7 TXCLK-
USB20_N3 8 7 TXCLK+
<25> USB20_N3 4 4 3 3 6 6 5 5
USB20_N3_1 4 3
USB20_P3_1 4 3
2 2 1 1 +3VS
USB20_P3 1 2
<25> USB20_P3 1 2
Camera ACES_88242-4001
WCM2012F2S-900T04_0805 CONN@ DAC_BRIG 1 2
C587 220P_0402_50V8J
1 2 INVT_PWM 1 2
R146 @ 0_0402_5% C586 220P_0402_50V8J
DISPOFF# 1 2
C588 220P_0402_50V8J

+INVPWR_B+

hexainf@hotmail.com
A A
L47 2 1 B+
W=40mils @ KC FBM-L11-201209-221LMAT_0805

L46 2 1
KC FBM-L11-201209-221LMAT_0805
1 1
C581 C580
Security Classification Compal Secret Data Compal Electronics, Inc.
470P_0402_50V7K 100P_0402_50V8J 2008/10/06 2009/10/06 Title
2 2 Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 21 of 49
5 4 3 2 1
 5 4 3 2 1

DDC to HDMI CONN

+3VS_DELAY +3VS +3VS +HDMI_5V_OUT

R114 R132 R116 R128

10K_0402_5%

10K_0402_5%

2K_0402_5%
4.7K_0402_5%

4.7K_0402_5%

JM@ R332
1

1
2K_0402_5%
JM@ R326
D UMA_H@ D

<11> GMCH_HDMI_CLK 1 2 DIP

2
G
R124 0_0402_5%
JHDMI1

2
VGA_HDMI_SCLK 3 1 HDMI_SCLK +HDMI_5V_OUT 18
<15> VGA_HDMI_SCLK +5V
UMA_H@ VGA@ VGA@ UMA_H@ UMA_H@ HDMI_SDATA

D
16 SDA CEC 13
1 2 HDMI_SCLK 15 14
SCL Reserved

2
<11> GMCH_HDMI_DATA

G
R121 0_0402_5% JM@ Q13 HDMI_HPD 19
BSH111 1N_SOT23-3 HP_DET
GND 2
VGA_HDMI_SDATA 3 1 HDMI_SDATA HDMI_R_CK- 12 5
<15> VGA_HDMI_SDATA HDMI_R_CK+ CK- GND

D
10 CK+ GND 8
HDMI_R_D0- 9 11
JM@ Q10 HDMI_R_D0+ D0- GND
Place closed to JHDMI1 7 D0+ GND 20
BSH111 1N_SOT23-3 HDMI_R_D1- 6 21
HDMI_R_D1+ D1- GND
4 D1+ GND 22
HDMI_R_D2- 3 23
HDMI_R_D2+ D2- GND
1 D2+ DDC/CEC_GND 17

+HDMI_5V_OUT +HDMI_5V_OUT SUYIN_100042MR019S153ZL

CONN@
HDMI_HPD JM@ D17 JM@ F2 W=40mils
1 +5VS 2 1+HDMI_5V_OUT_1 1 2

100K_0402_5%
JM@ C751 2 1 +3VS 1

2
JM@ R354
0.1U_0402_16V4Z JM@ R352 1 RB491D_SC59-3 1.1A_6VDC_FUSE C743
5
1

2.2K_0402_5% C749 JM@

2 @ 0.1U_0402_16V4Z
P
OE#

HDMI_DET 0.1U_0402_16V4Z 2
2 A Y 4 HDMI_DET <11,15> 2

1
G

JM@ U28
3

SN74AHCT1G125GW_SOT353-5
C C

HDMI_CLK+ 1 2 HDMI_R_CK+
R340 @ 0_0402_5%
Close to NB Close to GPU
WCM-2012-900T_0805
VGA@ 1 2
C708 1 1 2
<15> HDMI_CLK-_VGA 2 0.1U_0402_16V7K HDMI_CLK-
C707 1 2 0.1U_0402_16V7K HDMI_CLK+
<15> HDMI_CLK+_VGA
4 4 3 3
UMA_H@ UMA_H@ VGA@
C98 1 2 0.1U_0402_16V7K HDMICLK- 1 2 JM@ L72
<10> PCIE_MTX_GRX_N3
R315 0_0402_5%
C97 1 2 0.1U_0402_16V7K HDMICLK+ 1 2 HDMI_CLK- 1 2 HDMI_R_CK-
<10> PCIE_MTX_GRX_P3
UMA_H@ R314 0_0402_5% VGA@ R333 @ 0_0402_5%
UMA_H@ C705 1 2 0.1U_0402_16V7K HDMI_TX0-
<15> HDMI_TX0-_VGA
C704 1 2 0.1U_0402_16V7K HDMI_TX0+ HDMI_TX0+ 1 2 HDMI_R_D0+
<15> HDMI_TX0+_VGA
R342 @ 0_0402_5%
UMA_H@ UMA_H@ VGA@
C100 1 2 0.1U_0402_16V7K HDMITX0- 1 2 WCM-2012-900T_0805
<10> PCIE_MTX_GRX_N2
R313 0_0402_5% 1 2
C99 1 2
<10> PCIE_MTX_GRX_P2 1 2 0.1U_0402_16V7K HDMITX0+ 1 2
UMA_H@ R312 0_0402_5% VGA@
UMA_H@ C701 1 2 0.1U_0402_16V7K HDMI_TX1- 4 3
<15> HDMI_TX1-_VGA 4 3
C700 1 2 0.1U_0402_16V7K HDMI_TX1+
<15> HDMI_TX1+_VGA
JM@ L73
UMA_H@ UMA_H@ VGA@
C102 1 2 0.1U_0402_16V7K HDMITX1- 1 2 HDMI_TX0- 1 2 HDMI_R_D0-
<10> PCIE_MTX_GRX_N1
R311 0_0402_5% R341 @ 0_0402_5%
C101 1 2 0.1U_0402_16V7K HDMITX1+ 1 2
<10> PCIE_MTX_GRX_P1
UMA_H@ R310 0_0402_5% VGA@ HDMI_TX1+ 1 2 HDMI_R_D1+
UMA_H@ C699 1 2 0.1U_0402_16V7K HDMI_TX2- R344 @ 0_0402_5%
B <15> HDMI_TX2-_VGA B
C698 1 2 0.1U_0402_16V7K HDMI_TX2+
<15> HDMI_TX2+_VGA WCM-2012-900T_0805
UMA_H@ UMA_H@ VGA@ 1 2
C104 1 HDMITX2- 1 2
<10> PCIE_MTX_GRX_N0 2 0.1U_0402_16V7K 1 2
R309 0_0402_5%
C103 1 2 0.1U_0402_16V7K HDMITX2+ 1 2 4 3
<10> PCIE_MTX_GRX_P0 4 3
UMA_H@ R307 0_0402_5%
UMA_H@ JM@ L74

HDMI_TX1- 1 2 HDMI_R_D1-
R343 @ 0_0402_5%

HDMI_TX2+ 1 2 HDMI_R_D2+
R346 @ 0_0402_5%

HDMI_CLK- HDMI_TX0- HDMI_TX1- HDMI_TX2- WCM-2012-900T_0805

HDMI_CLK+ HDMI_TX0+ HDMI_TX1+ HDMI_TX2+ 1 2
1 2

Update (For Puma / Tigris default value)

1
1

1
1

UMA_H@ UMA_H@ R155 R152 4 3

R141 R137 UMA_H@ UMA_H@ 4 3
1
1

1
1

715_0402_1% 715_0402_1% 715_0402_1% 715_0402_1% JM@ L75

R149 R145 R158 R157 UMA use 715 ohm
UMA_H@ UMA_H@ UMA_H@ UMA_H@ VGA use 499 ohm HDMI_TX2- 1 2 HDMI_R_D2-
2
2

2
2

715_0402_1% 715_0402_1% 715_0402_1% 715_0402_1% R345 @ 0_0402_5%

2
2

2
2
6

+3VS

R505 0_0402_5%
A A
1 2 2 5 2 5

1 2 JM@ JM@
1

R506JM@
0_0402_5% 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
@ Q53A JM@ Q54A JM@
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
+5VS Q53B Q54B
Security Classification Compal Secret Data Compal Electronics, Inc.
DVT Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 22 of 49
5 4 3 2 1
 A B C D E

CRT CONNECTOR
+5VS +CRT_VCC
D28 D27 D26
W=40mils
DAN217_SC59 DAN217_SC59 DAN217_SC59 D25
2 1

1
1
RB491D_SC59-3
C622
1 +3VS 0.1U_0402_16V4Z 1
2

3
JCRT1
6
L57 FCM2012C-800_0805 L58 FCM2012C-800_0805 11
<11> GMCH_CRT_R 2 UMA@ 1 CRT_R 1 2 CRT_R_1 1 2 CRT_R_2 1
R291 0_0402_5% 7
L54 FCM2012C-800_0805 L55 FCM2012C-800_0805 DDCDATA 12
<11> GMCH_CRT_G 2 UMA@ 1 CRT_G 1 2 CRT_G_1 1 2 CRT_G_2 2
R277 0_0402_5% 8
L52 FCM2012C-800_0805 L53 FCM2012C-800_0805 HSYNC 13
<11> GMCH_CRT_B 2 UMA@ 1 CRT_B 1 2 CRT_B_1 1 2 CRT_B_2 3
R274 0_0402_5% +CRT_VCC 9

6P_0402_50V8K

6P_0402_50V8K

6P_0402_50V8K
5P_0402_50V8C

5P_0402_50V8C

5P_0402_50V8C
VSYNC 14 G 16

140_0402_1%

150_0402_1%

150_0402_1%
1 1 1 1 1 1 4 17

1
R285 R276 R273 C633 C640 C662 G
10
DVT C667 C660 C639 DDCCLK 15
<15> VGA_CRT_R 2 VGA@ 1 5
R493 0_0402_5% 2 2 2 2 2 2
UMA@ UMA@ UMA@ UMA@ UMA@ UMA@ UMA@ SUYIN_070546FR015S297ZR

2
<15> VGA_CRT_G 2 VGA@ 1 CONN@
R495 0_0402_5%

<15> VGA_CRT_B 2 VGA@ 1

R494 0_0402_5%

CRT_DET# <25>

2 2

2
R269
+CRT_VCC 100K_0402_5%
R479
1 2 1 2

1
<11,13> GMCH_CRT_HSYNC 2 UMA@ 1 C674

5
1
R325 0_0402_5% 0.1U_0402_16V4Z
10K_0402_5% L50 FCM1608C-121T_0603

P
OE#
<15,19> VGA_CRT_HSYNC 2 VGA@ 1 2 A Y 4 HSYNC_L 1 2 HSYNC +CRT_VCC
R507 0_0402_5%

G
U33
SN74AHCT1G125GW_SOT353-5

3
1 2
<11,13> GMCH_CRT_VSYNC 2 UMA@ 1 C678

5
1
R327 0_0402_5% 0.1U_0402_16V4Z
L51 FCM1608C-121T_0603

P
OE#
<15,19> VGA_CRT_VSYNC 2 VGA@ 1 2 A Y 4 VSYNC_L 1 2 VSYNC
R511 0_0402_5% Place closed to chipset

G
U34
SN74AHCT1G125GW_SOT353-5 +CRT_VCC +3VS_DELAY

3
+3VS

1
R54 R46 R55 R48
4.7K_0402_5% 4.7K_0402_5% 10K_0402_5% 10K_0402_5%
UMA@ UMA@ VGA@ VGA@
3 3

2
2
DDCDATA 2 R57 1 DDCDATA_R 6 1
VGA_CRT_DATA <15>
33_0402_5% Q6A

5
2N7002DW-T/R7_SOT363-6
VGA@
DDCCLK 2 R44 1 DDCCLK_R 3 4
VGA_CRT_CLK <15>
33_0402_5% Q6B
2N7002DW-T/R7_SOT363-6
VGA@

1 2
R58 0_0402_5% GMCH_CRT_DATA <11>
UMA@
1 2
R47 0_0402_5% GMCH_CRT_CLK <11>
UMA@ DVT

hexainf@hotmail.com
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 23 of 49
A B C D E
 A B C D E

U14A

A_RST# N2
SB700 P4
A_RST# PCICLK0
Part 1 of 5 PCICLK1 P3

PCI CLKS
C468 1 2 0.1U_0402_16V7K SB_RX0P_C V23 P1
1 <10> SB_RX0P PCIE_TX0P PCICLK2 PCI_CLK2 <28> 1
C465 1 2 0.1U_0402_16V7K SB_RX0N_C V22 P2
<10> SB_RX0N PCIE_TX0N PCICLK3 PCI_CLK3 <28>
C459 1 2 0.1U_0402_16V7K SB_RX1P_C V24 T4
<10> SB_RX1P PCIE_TX1P PCICLK4 PCI_CLK4 <28>
C431 1 2 0.1U_0402_16V7K SB_RX1N_C V25 T3
<10> SB_RX1N PCIE_TX1N PCICLK5/GPIO41 PCI_CLK5 <28>
C429 1 2 0.1U_0402_16V7K SB_RX2P_C U25
<10> SB_RX2P PCIE_TX2P
C430 1 2 0.1U_0402_16V7K SB_RX2N_C U24
<10> SB_RX2N PCIE_TX2N
C460 1 2 0.1U_0402_16V7K SB_RX3P_C T23
<10> SB_RX3P PCIE_TX3P
C464 1 2 0.1U_0402_16V7K SB_RX3N_C T22 N1
<10> SB_RX3N PCIE_TX3N PCIRST#

PCI EXPRESS INTERFACE

<10> SB_TX0P U22 PCIE_RX0P
<10> SB_TX0N U21 PCIE_RX0N AD0 U2
<10> SB_TX1P U19 PCIE_RX1P AD1 P7
<10> SB_TX1N V19 PCIE_RX1N AD2 V4
<10> SB_TX2P R20 PCIE_RX2P AD3 T1
<10> SB_TX2N R21 PCIE_RX2N AD4 V3
<10> SB_TX3P R18 PCIE_RX3P AD5 U1
<10> SB_TX3N R17 PCIE_RX3N AD6 V1
AD7 V2
R356 2 1 562_0402_1% T25 T2
R173 2.05K_0402_1% T24 PCIE_CALRP AD8
PCIE_CALRP=W/S=4/8(55ohm impedance), <1" +PCIE_VDDR 2 1 PCIE_CALRN AD9 W1
L78 PCIE_PVDD=43mA T9
+SB_PCIEVDD AD10
PCIE_CALRN=W/S=4/8(55ohm impedance), <1" +1.2V_HT 1 2 P24 PCIE_PVDD AD11 R6
MBC1608121YZF_0603 1 1 R7
AD12
P25 PCIE_PVSS AD13 R5
C757 C762 U8
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z AD14
AD15 U5
2 2
AD16 Y7
+3VALW W8
C798 AD17
AD18 V9
2 1 AD19 Y8
AD20 AA8
5

0.1U_0402_16V4Z U30 Y4
NC7SZ08P5X_NL_SC70-5 AD21
2 Y3
P

2 B AD22 2
Y 4PLT_RST# PLT_RST# <11,13,14,31,33> AD23 Y2 PCI_AD23 PCI_AD23 <28>
A_RST# 1 AA2 PCI_AD24 PCI_AD24 <28>
A AD24
G

AB4 PCI_AD25 PCI_AD25 <28>

AD25
2

N25 AA1 PCI_AD26 PCI_AD26 <28>

<20> CLK_SBSRC_BCLK
3

R426 R373 PCIE_RCLKP/NB_LNK_CLKP AD26 PCI_AD27

<20> CLK_SBSRC_BCLK# N24 PCIE_RCLKN/NB_LNK_CLKN AD27 AB3 PCI_AD27 <28>
8.2K_0402_5% 100K_0402_5% AB2 PCI_AD28 PCI_AD28 <28>
AD28
@ K23 NB_DISP_CLKP AD29 AC1
K22 AC2
1

NB_DISP_CLKN AD30
AD31 AD1
M24 W2

PCI INTERFACE
NB_HT_CLKP CBE0#
M25 NB_HT_CLKN CBE1# U7
CBE2# AA7
P17 CPU_HT_CLKP CBE3# Y1
M18 CPU_HT_CLKN FRAME# AA6
DEVSEL# W5
M23 SLT_GFX_CLKP IRDY# AA5
M22 SLT_GFX_CLKN TRDY# Y5
PAR U6
J19 GPP_CLK0P STOP# W6
J18 GPP_CLK0N PERR# W4
SERR# V7
L20 GPP_CLK1P REQ0# AC3
L19 GPP_CLK1N REQ1# AD4
REQ2# AB7
M19 GPP_CLK2P REQ3#/GPIO70 AE6
M20 GPP_CLK2N REQ4#/GPIO71 AB6
C853 @ 100P_0402_25V8K @ AD2
GNT0#

CLOCK GENERATOR
2 1 2 1 N22 GPP_CLK3P GNT1# AE4
R470 100_0402_5% P22 AD5
GPP_CLK3N GNT2#
GNT3#/GPIO72 AC6
<20> SB710_CLK_14M L18 25M_48M_66M_OSC GNT4#/GPIO73 AE5
CLKRUN# AD6
3 3
For Tigris LOCK# V5
J21 25M_X1
Close to SB INTE#/GPIO33 AD3
INTF#/GPIO34 AC4
INTG#/GPIO35 AE2
@ R380 20M_0402_5%
@R380 J20 AE3
25M_X2 INTH#/GPIO36
1 2

G22 CLK_LPC_EC 1 2 CLK_PCI_EC

C779 LPCCLK0 CLK_PCI_EC <28,33>
R357 22_0402_5%
1 2 SB_32KHI SB_32KHI A3
LPCCLK1 E22
H24
LPCCLK1 <28> STRAP PIN
X1 LAD0 LPC_AD0 <33>
Y4 LAD1 H23 LPC_AD1 <33>
18P_0402_50V8J J25
LAD2 LPC_AD2 <33>
1

4 3 J24
RTC XTAL

OUT NC LAD3 LPC_AD3 <33>

LPC

R382 SB_32KHO B3 H25

X2 LFRAME# LPC_FRAME# <33>
20M_0603_5% 1 2 H22
IN NC LDRQ0#
LDRQ1#/GNT5#/GPIO68 AB8
AD7 +RTCBATT
C787
2

32.768KHZ_12.5P_MC-306 BMREQ#/REQ5#/GPIO65
SERIRQ V15 SERIRQ <33>

1
1 2 SB_32KHO
F23 R237
<11> ALLOW_LDTSTOP ALLOW_LDTSTP
18P_0402_50V8J H_PROCHOT_R#
<6> H_PROCHOT_R# F24
F22
PROCHOT# RTCCLK C3
C2 1 @ 2
RTC_CLK <28> STRAP PIN 1K_0402_5%
<6> H_PWRGD LDT_PG INTRUDER_ALERT# +RTCVCC
R403 1M_0402_5%
CPU

<6,11> LDT_STOP# G25 B2

2
LDT_STP# VBAT +RTCVCC
<6> LDT_RST# G24 LDT_RST#
RTC

D22
1 2 3
218S7EALA11FG_BGA528_SB700 R400 510_0402_5%

0.1U_0402_16V4Z
C795 1 1 C794 W=20mils 1

2
0.1U_0402_16V4Z

1U_0402_6.3V4Z 1
4 R397 C566 4
SA00001S570 S IC 218S7EBLA12FG SB700 BGA 528P SB 0FA @
2
2 2 0_0603_5%
for Clear CMOS 2 BAS40-04_SOT23-3

1
+CHGRTC

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 24 of 49
A B C D E
 A B C D E

+3VALW

2
R368
100K_0402_5%

1
CRT_DET

1
D
2 U14D @ @
<23> CRT_DET#
Q37G demo circuit LID use RI# 1 2 C775 1 2 100P_0402_25V8K
2N7002_SOT23 Part 4 of 5 R376 100_0402_5%
S
SB700

3
1 1
<33> EC_SWI# E1 PCI_PME#/GEVENT4#
E2 RI#/EXTEVNT0# USBCLK/14M_25M_48M_OSC C8 CLK_48M_USB <20>
CRT_DET H7 SLP_S2/GPM9# USB_RCOMP 1
<33> PM_SLP_S3# F5 SLP_S3# USB_RCOMP G8 2
G1 11.8K_0402_1% R370
<33> PM_SLP_S5# SLP_S5#

USB MISC
ACPI / WAKE UP EVENTS
<33> PBTN_OUT# H2 PWR_BTN#
<6,35> SB_PWRGD H1 PWR_GOOD
SUS_STAT# K3
<11> SUS_STAT# SUS_STAT#
+3VS 1 2 SUS_STAT# TP13 H5 E6
R405 4.7K_0402_5% TP14 TEST2 USB_FSD13P
H4 TEST1 USB_FSD13N E7
TP15 H3 TEST0

USB 1.1
Y15 F7 USB20_P12
<33> EC_GA20 GA20IN/GEVENT0# USB_FSD12P USB20_P12 <32>
USB20_N12
<33> EC_KBRST# W15 KBRST#/GEVENT1# USB_FSD12N E8 USB20_N12 <32> USB-12 Bluetooth
<33> EC_SCI# K4 LPC_PME#/GEVENT3#
<33> EC_SMI# K24 LPC_SMI#/EXTEVNT1# USB_HSD11P H11
F1 S3_STATE/GEVENT5# USB_HSD11N J10
J2 SYS_RESET#/GPM7#
<31> SB_PCIE_WAKE# H6 WAKE#/GEVENT8# USB_HSD10P E11
F2 BLINK/GPM6# USB_HSD10N F11
1 2 EC_RSMRST# H_THERMTRIP# J6
<6> H_THERMTRIP# SMBALERT#/THRMTRIP#/GEVENT2#
R404 2.2K_0402_5% NB_PWRGD W14 A11
<11> NB_PWRGD NB_PWRGD USB_HSD9P
USB_HSD9N B11
EC_RSMRST# D3
<33> EC_RSMRST# RSMRST#
C10 USB20_P8
USB_HSD8P USB20_P8 <31>
VRAM ID SB700 has internal PD D10 USB20_N8 USB-8 MiniCard(WLAN)
USB_HSD8N USB20_N8 <31>
High->HYNIX R212 1 @ 2 10K_0402_5%
Low->SAMSUNG AE18 SATA_IS0#/GPIO10 USB_HSD7P G11
+3VS R182 1 @ 2 10K_0402_5% LFB_ID AD18 H12
+3VS CLK_REQ3#/SATA_IS1#/GPIO6 USB_HSD7N
AA19 SMARTVOLT1/SATA_IS2#/GPIO4
+3VS R509 1 VGA@ 2 2.2K_0402_5% SKU_ID W17 E12 USB20_P6 USB-6 Int USB 1st
CLK_REQ0#/SATA_IS3#/GPIO0 USB_HSD6P USB20_P6 <32>
V17 E14 USB20_N6
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39 USB_HSD6N USB20_N6 <32> (Dedicated HS USB port / lower-left)
R183 1 2 2.2K_0402_5% SB_CK_SCLK R510 1 UMA@ 2 2.2K_0402_5% W20
2 CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40 USB20_P5 2
<36> SB_SPKR W21 C12

USB 2.0
SPKR/GPIO2 USB_HSD5P USB20_P5 <31>
R179 1 2 2.2K_0402_5% SB_CK_SDAT <8,9,20,31> SB_CK_SCLK SB_CK_SCLK AA18 D12 USB20_N5 USB-5 MiniCard(WWAN)
SCL0/GPOC0# USB_HSD5N USB20_N5 <31>
<8,9,20,31> SB_CK_SDAT SB_CK_SDAT W18 SDA0/GPOC1# USB20_P4
K1 SCL1/GPOC2# USB_HSD4P B12 USB20_P4 <30>
K2 A12 USB20_N4 USB-4 USB Card reader
SDA1/GPOC3# USB_HSD4N USB20_N4 <30>
SB_SPKR=W/S=4/4(55ohm impedance) AA20 DDC1_SCL/GPIO9

GPIO
Y18 G12 USB20_P3
DDC1_SDA/GPIO8 USB_HSD3P USB20_P3 <21>
C1 G14 USB20_N3 USB-3 USB Camera
LLB#/GPIO66 USB_HSD3N USB20_N3 <21>
Y19 SMARTVOLT2/SHUTDOWN#/GPIO5
G5 H14 USB20_P2
DDR3_RST#/GEVENT7# USB_HSD2P USB20_P2 <31>
H15 USB20_N2 USB-2 Ext USB 4rd
+3VALW USB_HSD2N USB20_N2 <31>
A13 USB20_P1
USB_HSD1P USB20_P1 <32>
B13 USB20_N1 USB-1 Int USB 2nd
USB_HSD1N USB20_N1 <32>
1 2 SB_PCIE_WAKE# B14 USB20_P0
USB_HSD0P USB20_P0 <31>
R388 10K_0402_5% B9 A14 USB20_N0 USB-0 Ext USB 3rd
USB_OC6#/IR_TX1/GEVENT6# USB_HSD0N USB20_N0 <31>
1 @ 2 EC_LID_OUT# B8
R379 100K_0402_5% EC_LID_OUT# USB_OC5#/IR_TX0/GPM5#
A8 A18

USB OC
<33> EC_LID_OUT# USB_OC4#/IR_RX0/GPM4# IMC_GPIO8
A9 USB_OC3#/IR_RX1/GPM3# IMC_GPIO9 B18
USB_OC#2 E5 F21
USB_OC#1 USB_OC2#/GPM2# IMC_PWM0/IMC_GPIO10
<32> USB_OC#1 F8 USB_OC1#/GPM1# SCL2/IMC_GPIO11 D21
USB_OC#0 E4 F19
<32> USB_OC#0 USB_OC0#/GPM0# SDA2/IMC_GPIO12
AMD (un-used) SCL3_LV/IMC_GPIO13 E20
R414 33_0402_5% 1 2 HDA_BITCLK M1 E21
<36> HDA_BITCLK_AUDIO AZ_BITCLK SDA3_LV/IMC_GPIO14
R416 33_0402_5% 1 2 HDA_SDOUT M2 E19
<36> HDA_SDOUT_AUDIO AZ_SDOUT IMC_PWM1/IMC_GPIO15
HDA_SDIN0 J7 D19 STRAP PIN
<36> HDA_SDIN0 AZ_SDIN0/GPIO42 IMC_PWM2/IMC_GPO16 GPIO16 <28>
J8
L8
AZ_SDIN1/GPIO43 IMC_PWM3/IMC_GPO17 E18 GPIO17 <28> STRAP PIN

HD AUDIO
AZ_SDIN2/GPIO44
M3 AZ_SDIN3/GPIO46 IMC_GPIO18 G20
R412 33_0402_5% 1 2 HDA_SYNC L6 G21
<36> HDA_SYNC_AUDIO AZ_SYNC IMC_GPIO19
M4 AZ_RST# IMC_GPIO20 D25
3 3
L5 AZ_DOCK_RST#/GPM8# IMC_GPIO21 D24

INTEGRATED uC
IMC_GPIO22 C25
R408 33_0402_5% 1 2 HDA_RST# C24
<36> HDA_RST_AUDIO# IMC_GPIO23
IMC_GPIO24 B25
IMC_GPIO25 C23

<28> HDA_RST# IMC_GPIO26 B24

IMC_GPIO27 B23
IMC_GPIO28 A23
STRAP PIN IMC_GPIO29 C22
A22
IMC_GPIO30
+3VALW IMC_GPIO31 B22
IMC_GPIO32 B21
IMC_GPIO33 A21
H19 IMC_GPIO0 IMC_GPIO34 D20
1

H20 IMC_GPIO1 IMC_GPIO35 C20

R435
INTEGRATED uC

H21 SPI_CS2#/IMC_GPIO2 IMC_GPIO36 A20

100K_0402_5% F25 B20
IDE_RST#/F_RST#/IMC_GPO3 IMC_GPIO37
IMC_GPIO38 B19
D22 A19
2

USB_OC#2 IMC_GPIO4 IMC_GPIO39

E24 IMC_GPIO5 IMC_GPIO40 D18
1 E25 IMC_GPIO6 IMC_GPIO41 C18
D23 IMC_GPIO7
C811
0.1U_0402_16V4Z
2
218S7EALA11FG_BGA528_SB700

hexainf@hotmail.com
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 25 of 49
A B C D E
 A B C D E

U14B
1 1
Close chip
C504 1 2 0.01U_0402_25V7K SATA_STX_DRX_P0 AD9
SB700 AA24
<29> SATA_STX_C_DRX_P0 C507 1 SATA_TX0P IDE_IORDY
<29> SATA_STX_C_DRX_N0 2 0.01U_0402_25V7K SATA_STX_DRX_N0 AE9 SATA_TX0N Part 2 of 5 IDE_IRQ AA25
HDD IDE_A0 Y22
<29> SATA_DTX_C_SRX_N0 AB10 SATA_RX0N IDE_A1 AB23
<29> SATA_DTX_C_SRX_P0 AC10 SATA_RX0P IDE_A2 Y23
IDE_DACK# AB24
C522 1 2 0.01U_0402_25V7K SATA_STX_DRX_P1 AE10 AD25
<29> SATA_STX_C_DRX_P1 SATA_TX1P IDE_DRQ
C519 1 2 0.01U_0402_25V7K SATA_STX_DRX_N1 AD10 AC25
<29> SATA_STX_C_DRX_N1 SATA_TX1N IDE_IOR#
ODD IDE_IOW# AC24
<29> SATA_DTX_C_SRX_N1 AD11 SATA_RX1N IDE_CS1# Y25
<29> SATA_DTX_C_SRX_P1 AE11 SATA_RX1P IDE_CS3# Y24

AB12 SATA_TX2P IDE_D0/GPIO15 AD24

AC12 SATA_TX2N IDE_D1/GPIO16 AD23

ATA 66/100/133
IDE_D2/GPIO17 AE22
AE12 SATA_RX2N IDE_D3/GPIO18 AC22
AD12 SATA_RX2P IDE_D4/GPIO19 AD21
IDE_D5/GPIO20 AE20
AD13 SATA_TX3P IDE_D6/GPIO21 AB20
AE13 SATA_TX3N IDE_D7/GPIO22 AD19
AE19

SERIAL ATA
IDE_D8/GPIO23
AB14 SATA_RX3N IDE_D9/GPIO24 AC20
AC14 SATA_RX3P IDE_D10/GPIO25 AD20
IDE_D11/GPIO26 AE21
AE14 SATA_TX4P IDE_D12/GPIO27 AB22
AD14 SATA_TX4N IDE_D13/GPIO28 AD22
IDE_D14/GPIO29 AE23
AD15 SATA_RX4N IDE_D15/GPIO30 AC23
AE15 SATA_RX4P
2 SATA_X1 2
2 1 C770 AB16 SATA_TX5P
AC16 SATA_TX5N
1

10P_0402_50V8J G6
SPI_DI/GPIO12
AE16 SATA_RX5N SPI_DO/GPIO11 D2
R371 SATA_CAL=W/S=9/20(35ohm impedance), <1" AD16 D1
25MHZ_20P Y3 10M_0402_5% SATA_RX5P SPI_CLK/GPIO47
F4

SPI ROM
2

SATA_CAL SPI_HOLD#/GPIO31
2 1 V12 F3
2

SATA_CAL SPI_CS1#/GPIO32
2 1 C772 SATA_X2 R375 1K_0402_1%
SATA_X1 Y12 U15
10P_0402_50V8J SATA_X1 LAN_RST#/GPIO13
ROM_RST#/GPIO14 J1
SATA_X2 AA12 SATA_X2
+3VS R377 1 2 10K_0402_5% FANOUT0/GPIO3 M8
<35> SATA_LED# W11 SATA_ACT#/GPIO67 FANOUT1/GPIO48 M5
+1.2V_HT M7
L82 FANOUT2/GPIO49
2 1 +PLLVDD_SATA AA11 P5
BLM18PG121SN1D_0603 PLLVDD_SATA FANIN0/GPIO50
FANIN1/GPIO51 P8

SATA PWR
PLLVDD_SATA=93mA 1 1 W12 XTLVDD_SATA FANIN2/GPIO52 R8

C784 C783 C6
2.2U_0603_6.3V4Z 0.1U_0402_16V4Z TEMP_COMM
TEMPIN0/GPIO61 B6
2 2
TEMPIN1/GPIO62 A6
TEMPIN2/GPIO63 A5
B5

HW MONITOR
TEMPIN3/TALERT#/GPIO64 EC_THERM# <33>
+3VS A4 2 1
VIN0/GPIO53 ACIN <33,39>
L81 XTLVDD_SATA=6mA B4 D30 RB751V_SOD323
+XTLVDD_SATA VIN1/GPIO54
2 1 VIN2/GPIO55 C4
BLM18PG121SN1D_0603 2 1 D4
VIN3/GPIO56
VIN4/GPIO57 D5
C777 C776 D6 R369 2 1 100K_0402_5% +3VALW
1U_0402_6.3V4Z 0.1U_0402_16V4Z VIN5/GPIO58
VIN6/GPIO59 A7
3 1 2 R374 2 3
VIN7/GPIO60 B7 1 100K_0402_5% +3VS
+3VALW @

AVDD F6 AVDD=5mA
AVSS G7

218S7EALA11FG_BGA528_SB700

Port Number Pri/SEC,Mas/Slave assignment SATA drive controlled by

Port 0 Primary master SATA controler

Port 1 Secondary master SATA controler

Port 2 Primary slave SATA controler

Port 3 Secondary slave SATA controler

Port 4 Primary (Secondary) master PATA controler

4 4

Port 5 Primary (Secondary) slave PATA controler

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 26 of 49
A B C D E
 A B C D E

U14C U14E
VDD=0.51A
VDDQ=131mA SB700 +1.2V_SB_CORE
+3VS L9
M9
VDDQ_1
Part 3 of 5
VDD_1 L15
M12
1
R171
2
0_0805_5%
+1.2V_HT SB700 A2
VDDQ_2 VDD_2 10U_0805_10V4Z C467 VSS_1
1 2 T15 VDDQ_3 VDD_3 M14 1 2 VSS_2 A25
C472 22U_0805_6.3V6M U9 N13 B1

CORE S0
1 VDDQ_4 VDD_4 VSS_3 1
U16 VDDQ_5 VDD_5 P12 VSS_4 D7
U17 VDDQ_6 VDD_6 P14 T10 AVSS_SATA_1 VSS_5 F20

PCI/GPIO I/O
V8 R11 1U_0402_6.3V4Z 2 1 C478 U10 G19
VDDQ_7 VDD_7 1U_0402_6.3V4Z C487 AVSS_SATA_2 VSS_6
W7 VDDQ_8 VDD_8 R15 2 1 U11 AVSS_SATA_3 VSS_7 H8
Y6 T16 0.1U_0402_16V4Z 2 1 C494 U12 K9
C489 0.1U_0402_16V4Z VDDQ_9 VDD_9 0.1U_0402_16V4Z C482 AVSS_SATA_4 VSS_8
1 2 AA4 VDDQ_10 2 1 V11 AVSS_SATA_5 VSS_9 K11
C499 1 2 0.1U_0402_16V4Z AB5 V14 K16
C493 0.1U_0402_16V4Z VDDQ_11 AVSS_SATA_6 VSS_10
1 2 AB21 VDDQ_12 W9 AVSS_SATA_7 VSS_11 L4
Y9 AVSS_SATA_8 VSS_12 L7
Y11 AVSS_SATA_9 VSS_13 L10
VDD=138mA Y14 AVSS_SATA_10 VSS_14 L11
VDD33=71mA +1.2V_HT
Y17 AVSS_SATA_11 VSS_15 L12
+3VS Y20 VDD33_18_1 CKVDD_1.2V_1 L21 +1.2V_HT AA9 AVSS_SATA_12 VSS_16 L14
AA21 VDD33_18_2 CKVDD_1.2V_2 L22 AB9 AVSS_SATA_13 VSS_17 L16
AA22 L24 AB11 M6

IDE/FLSH I/O

CLKGEN I/O
VDD33_18_3 CKVDD_1.2V_3 AVSS_SATA_14 VSS_18
AE25 VDD33_18_4 CKVDD_1.2V_4 L25 AB13 AVSS_SATA_15 VSS_19 M10
AB15 AVSS_SATA_16 VSS_20 M11
AB17 AVSS_SATA_17 VSS_21 M13
AC8 AVSS_SATA_18 VSS_22 M15
AD8 AVSS_SATA_19 VSS_23 N4
AE8 AVSS_SATA_20 VSS_24 N12
PCIE_VDDR=0.6A +PCIE_VDDR VSS_25 N14
P6
L37 POWER VSS_26
VSS_27 P9
+1.2V_HT 2 1 VSS_28 P10
FBMA-L11-201209-221LMA30T_0805 A15 P11
AVSS_USB_1 VSS_29
P18 PCIE_VDDR_1 B15 AVSS_USB_2 VSS_30 P13
C466 1 2 10U_0805_10V4Z P19 +3VALW C14 P15
C763 1 PCIE_VDDR_2 AVSS_USB_3 VSS_31
2 1U_0402_6.3V4Z P20 PCIE_VDDR_3 S5_3.3V=32mA D8 AVSS_USB_4 VSS_32 R1
P21 A17 +S5_3V D9 R2

A-LINK I/O
PCIE_VDDR_4 S5_3.3V_1 AVSS_USB_5 VSS_33
R22 PCIE_VDDR_5 S5_3.3V_2 A24 D11 AVSS_USB_6 VSS_34 R4
R24 PCIE_VDDR_6 S5_3.3V_3 B17 D13 AVSS_USB_7 VSS_35 R9

GROUND
2 C759 1 2
2 0.1U_0402_16V4Z R25 PCIE_VDDR_7 S5_3.3V_4 J4 D14 AVSS_USB_8 VSS_36 R10

3.3V_S5 I/O
C497 1 2 0.1U_0402_16V4Z J5 D15 R12
S5_3.3V_5 2.2U_0603_6.3V4Z C769 AVSS_USB_9 VSS_37
S5_3.3V_6 L1 1 2 E15 AVSS_USB_10 VSS_38 R14
AVDD_SATA=567mA +1.2V_SATA S5_3.3V_7 L2
2.2U_0603_6.3V4Z C486
F12 AVSS_USB_11 VSS_39 T11
1 2 F14 AVSS_USB_12 VSS_40 T12
L79 G9 T14
AVSS_USB_13 VSS_41
+1.2V_HT 2 1 AA14 AVDD_SATA_1 H9 AVSS_USB_14 VSS_42 U4
FBMA-L11-201209-221LMA30T_0805 AB18 +1.2VALW H17 U14
AVDD_SATA_4 AVSS_USB_15 VSS_43
AA15 AVDD_SATA_2 +S5_1.2V
S5_1.2V=113mA J9 AVSS_USB_16 VSS_44 V6
AA17 G2 J11 Y21

CORE S5
AVDD_SATA_3 S5_1.2V_1 AVSS_USB_17 VSS_45

SATA I/O
C764 1 2 22U_0805_6.3V6M AC18 G4 J12 AB1
C766 1U_0402_6.3V4Z AVDD_SATA_5 S5_1.2V_2 +1.2VALW C797 2 AVSS_USB_18 VSS_46
1 2 AD17 AVDD_SATA_6 USB_PHY_1.2V=197mA 1 1U_0402_6.3V4Z J14 AVSS_USB_19 VSS_47 AB19
C765 1 2 1U_0402_6.3V4Z AE17 C796 2 1 1U_0402_6.3V4Z J15 AB25
C767 0.1U_0402_16V4Z AVDD_SATA_7 +1.2_USB AVSS_USB_20 VSS_48
1 2 2 1 K10 AVSS_USB_21 VSS_49 AE1
C768 1 2 0.1U_0402_16V4Z A10 L80 FBMA-L11-160808-221LMT 0603 K12 AE24
USB_PHY_1.2V_1 C771 1 AVSS_USB_22 VSS_50
USB_PHY_1.2V_2 B10 2 10U_0805_10V4Z K14 AVSS_USB_23
K15 AVSS_USB_24
C773 2 1 0.1U_0402_16V4Z P23
C774 2 PCIE_CK_VSS_9
1 0.1U_0402_16V4Z PCIE_CK_VSS_10 R16
AVDDTX/RX=658mA +AVDD_USB PCIE_CK_VSS_11 R19
PCIE_CK_VSS_12 T17
L38 V5_VREF=1mA U18
+V5_VREF 1K_0402_5% 2 PCIE_CK_VSS_13
+3VALW 2 1 A16 AVDDTX_0 V5_VREF AE7 1 R386 +5VS H18 PCIE_CK_VSS_1 PCIE_CK_VSS_14 U20
FBMA-L11-201209-221LMA30T_0805 B16 2 D31 J17 V18
AVDDTX_1 +AVDDCK_3.3V PCIE_CK_VSS_2 PCIE_CK_VSS_15
C16 AVDDTX_2 AVDDCK_3.3V J16 1 2 +3VS J22 PCIE_CK_VSS_3 PCIE_CK_VSS_16 V20
C461 1 2 10U_0805_10V4Z D16 C786 K25 V21
C469 10U_0805_10V4Z AVDDTX_3 +AVDDCK_1.2V PCIE_CK_VSS_4 PCIE_CK_VSS_17
1 2 D17 K17 1U_0402_6.3V4Z CH751H-40PT_SOD323-2 M16 W19
PLL

C495 1U_0402_6.3V4Z AVDDTX_4 AVDDCK_1.2V 1 PCIE_CK_VSS_5 PCIE_CK_VSS_18

1 2 E17 AVDDTX_5 M17 PCIE_CK_VSS_6 PCIE_CK_VSS_19 W22
USB I/O

C485 1 2 1U_0402_6.3V4Z F15 E9 +AVDDC M21 W24

AVDDRX_0 AVDDC PCIE_CK_VSS_7 PCIE_CK_VSS_20
F17 AVDDRX_1 AVDDC=17mA L42
P16 PCIE_CK_VSS_8 PCIE_CK_VSS_21 W25
F18 AVDDRX_2
C481 1 2 0.1U_0402_16V4Z G15 2 1 +3VALW F9 L17
3 AVDDRX_3 BLM18PG121SN1D_0603 AVSSC AVSSCK 3
G17 AVDDRX_4 Part 5 of 5
G18 AVDDRX_5 2.2U_0603_6.3V4Z 2 1 C484 218S7EALA11FG_BGA528_SB700

0.1U_0402_16V4Z 2 1 C496
218S7EALA11FG_BGA528_SB700

AVDDCK_1.2V=62mA L77
+AVDDCK_1.2V 2 1 +1.2V_HT
BLM18PG121SN1D_0603

2.2U_0603_6.3V4Z 2 1 C758

0.1U_0402_16V4Z 2 1 C761

AVDDCK_3.3V=47mA L76
+AVDDCK_3.3V 2 1 +3VS
BLM18PG121SN1D_0603

2.2U_0603_6.3V4Z 2 1 C756

0.1U_0402_16V4Z 2 1 C760

hexainf@hotmail.com
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 27 of 49
A B C D E
 A B C D E

REQUIRED STRAPS NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK

LPC_CLK0
PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5 CLK_PCI_EC LPC_CLK1 RTC_CLK AZ_RST_CD# GP17 GP16

PULL BOOTFAIL USE RESERVED RESERVED ENABLE PCI CLKGEN INTERNAL EC Internal pull up
HIGH TIMER DEBUG MEM BOOT ENABLED RTC ENABLED
ENABLED STRAPS H,H = Reserved
1
H,L = SPI ROM 1
DEFAULT
L,L = FWH ROM
EXT. RTC
PULL BOOTFAIL IGNORE DISABLE PCI CLKGEN (PD on X1, EC
LOW TIMER DEBUG MEM BOOT DISABLED apply DISABLED L,H = LPC ROM (SB700)
DISABLED STRAPS 32KHz to DEFAULT L,NC = LPC ROM (SB710)
DEFAULT DEFAULT DEFAULT DEFAULT RTC_CLK)

+3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
R363

R367
R427

R425

R423

R421

R359

R361

R401

R411
2

2
@ @ @ @ @ @ @ @ @ @
<24> PCI_CLK2
<24> PCI_CLK3
<24> PCI_CLK4
<24> PCI_CLK5
<24,33> CLK_PCI_EC
<24> LPCCLK1
<24> RTC_CLK
<25> HDA_RST#
2 <25> GPIO17 2
<25> GPIO16

1
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
R402

R362

R366
R424

R422

R420

R398

R358

R360

R410
2

2
@ @ @ @

DEBUG STRAPS
SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23

USE USE PCI USE ACPI USE IDE USE DEFAULT RESERVED
PULL LONG PLL BCLK PLL PCIE STRAPS
HIGH RESET
3 DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT 3

PULL USE BYPASS BYPASS BYPASS IDE USE EEPROM

LOW SHORT PCI PLL ACPI PLL PCIE STRAPS
RESET BCLK

<24> PCI_AD28
<24> PCI_AD27
<24> PCI_AD26
<24> PCI_AD25
<24> PCI_AD24
<24> PCI_AD23
1

1
2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
R392

R393

R395

R389

R396

R399
2

2
@ @ @ @ @ @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 28 of 49
A B C D E
 A B C D E F G H

1 SATA ODD Conn. 1

JSATA1

1 GND
SATA_STX_C_DRX_P1 2
<26> SATA_STX_C_DRX_P1 A+
SATA_STX_C_DRX_N1 3
<26> SATA_STX_C_DRX_N1 A-
4 GND
<26> SATA_DTX_C_SRX_N1 C513 1 2 0.01U_0402_25V7K SATA_DTX_SRX_N1 5
C510 SATA_DTX_SRX_P1 B-
<26> SATA_DTX_C_SRX_P1 1 2 0.01U_0402_25V7K 6 B+
7 GND
Close conn
R199 1 2 1K_0402_1% 8
@ DP
9 +5V
SI3456DV: N CHANNEL +5VALW Q66 10
+5VMOD +5V
VGS: 4.5V, RDS: 65 mOHM +5VMOD 11 MD

D
6 12 15

S
Id(MAX): 5.1A 5 4 13
GND GND
14
VGS,+-20V GND GND
2
1
SANTA_206401-1_13P

1
CONN@

3
R214 Placea caps. near ODD CONN.
SI3456BDV-T1-E3_TSOP6 470_0402_5% +5VMOD

0.1U_0402_16V4Z 10U_0805_10V4Z

2
+VSB 2 1
R216 1 1 1 1

6
200K_0402_5% Q67A C491 C492 C505
3

2N7002DW-T/R7_SOT363-6
2 C490 2
SUSP 2 2 2 2
1 2
5 C204
<35,38> SUSP
1000P_0402_50V7K 1U_0402_6.3V4Z

1
0.1U_0603_25V7K
4

Q67B 2
2N7002DW-T/R7_SOT363-6

SATA HDD Conn.

JSATA2

1 GND
SATA_STX_C_DRX_P0 2
<26> SATA_STX_C_DRX_P0 SATA_STX_C_DRX_N0 A+
<26> SATA_STX_C_DRX_N0 3 A-
4 GND
<26> SATA_DTX_C_SRX_N0 C515 1 2 0.01U_0402_25V7K SATA_DTX_SRX_N0 5
3 C521 B- 3
<26> SATA_DTX_C_SRX_P0 1 2 0.01U_0402_25V7K SATA_DTX_SRX_P0 6 B+
7 GND
Close conn
+3VS 8 V33
9 V33
10 V33
11 GND
12 GND
13 GND
+5VS 14
+5VS V5
10U_0805_10V4Z 15
0.1U_0402_16V4Z V5
16 V5
+3VS 17 GND
1 1 1 1 1 1 18 Reserved
1 C556 C554 C557 C555 C552 19
C792 GND
20 V12
C551 21 24
0.1U_0402_16V4Z 2 2 2 2 2 2 V12 GND
22 V12 GND 23
2
1000P_0402_50V7K 1U_0402_6.3V4Z
0.1U_0402_16V4Z 0.1U_0402_16V4Z OCTEK_SAT-22SO1G_RV
CONN@
IAT50 (CL 4.3mm)

for ESD issue

hexainf@hotmail.com
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 29 of 49
A B C D E F G H
 5 4 3 2 1

2 1
R745 0_0402_5%

U21

2 1 1 AV_PLL
+3VS 2 1 C858 0.1U_0402_16V4Z 3
R746 0_0603_5% NC
7 NC
+3VALW 2 1 +XDPWR_SDPWR_MSPWR 9
R747 @ 0_0603_5% CARD_3V3
11 D3V3
33 D3V3 VREG 10 1 2
22 C859 1U_0402_6.3V4Z
MS_D4
1 NC 30
D 8 3V3_IN
D
C860 RST# 44
@ 4.7U_0805_10V4Z MODE_SEL RST#
45 MODE_SEL

2
2 XDCLE
47 XTLO XD_CLE_SP19 43
1 XTLI 48 42 XDCE#
R748 XTLI XD_CE#_SP18 XDALE
XD_ALE_SP17 41
@ 100K_0402_5% C861 USB20_N4 4 40 SDDAT2_XDRE#
<25> USB20_N4 DM SD_DAT2/XD_RE#_SP16
0.1U_0402_16V4Z USB20_P4 5 39 SDDAT3_XDWE#
<25> USB20_P4

1
2 DP SD_DAT3/XD_WE#_SP15 XD_RDY
<35> 5IN1_LED# 14 GPIO0 XD_RDY_SP14 38
RST#_L 2 1 RST# 37 SDDAT4_XDWP#_MSD7
R749 0_0402_5% SD_DAT4/XD_WP#/MS_D7_SP13 SDDAT5_XDD0_MSD6
SD_DAT5/XD_D0/MS_D6_SP12 35
SDCLK_XDD1_MSCLK_L SDCLK_XDD1_MSCLK
Vender suggesttion SD_CLK/XD_D1/MS_CLK_SP11 34
31 SDDAT6_XDD7_MSD3
2
R750
1
0_0402_5%
1 SD_DAT6/XD_D7/MS_D3_SP10
29 MS_INS#
C862 MS_INS#_SP9 SDDAT7_XDD2_MSD2
SD_DAT7/XD_D2/MS_D2_SP8 28
1U_0402_6.3V4Z 27 SDDAT0_XDD6_MSD0
2 SD_DAT0/XD_D6/MS_D0_SP7 SDDAT1_XDD3_MSD1
SD_DAT1/XD_D3/MS_D1_SP6 26
25 XDD5_MSBS
XD_D5_SP5 XDD4_SDDAT1
XD_D4/SD_DAT1_SP4 23
21 SDCD
MODE_SEL SD_CD#_SP3 SDWP
SD_WP_SP2 20
19 XDCD
XD_CD#_SP1
EEDI 18

1
1
R751 2 13 XTAL_CTR 2 1 +3VS
@ C863 0_0402_5% RREF XTAL_CTR R752 0_0603_5%
MS_D5 24
47P_0402_50V8J 12 XTAL_CTR
2 DGND
32 15 If Open , use 12MHz. crystal

2
Change to 0ohm for RTS5159 DGND EEDO
EECS 16 If Pull high , use CLKGEN 48MHz.
20081128 6 17
AGND EESK SD_CMD
46 AGND SD_CMD 36

2
<20> CLK_48M_SD 1 2 XTLI R754
R753 0_0402_5% 6.19K_0402_1% RTS5158E-GR_LQFP48_7X7
C C
R755
0_0402_5% Change to RT5159-GR <SA00002YP00>

1
20081104
1

R756
@ 33_0402_5%
2

1
@ C865
22P_0402_50V8J
2

EMI

+XDPWR_SDPWR_MSPWR

+XDPWR_SDPWR_MSPWR
JREAD1

10U_0805_10V4Z
3 XD-VCC SD-VCC 21
MS-VCC 28
B SDDAT5_XDD0_MSD6 32 1 B
SDCLK_XDD1_MSCLK XD-D0 SDCLK_XDD1_MSCLK
10 XD-D1 7 IN 1 CONN SD_CLK 20
2

C868
1 SDDAT7_XDD2_MSD2 9 14 SDDAT0_XDD6_MSD0
SDDAT1_XDD3_MSD1 XD-D2 SD-DAT0 XDD4_SDDAT1
8 XD-D3 SD-DAT1 12
R757 C867 XDD4_SDDAT1 SDDAT2_XDRE# 2
7 XD-D4 SD-DAT2 30
100K_0402_5% 0.1U_0402_16V4Z XDD5_MSBS 6 29 SDDAT3_XDWE#
2 SDDAT0_XDD6_MSD0 XD-D5 SD-DAT3 SDDAT4_XDWP#_MSD7
5 27
1

SDDAT6_XDD7_MSD3 XD-D6 SD-DAT4 SDDAT5_XDD0_MSD6

4 XD-D7 SD-DAT5 23
18 SDDAT6_XDD7_MSD3
SDDAT3_XDWE# SD-DAT6 SDDAT7_XDD2_MSD2
34 XD-WE SD-DAT7 16
SDDAT4_XDWP#_MSD7 33 25 SD_CMD
XD-WP SD-CMD
MSCLK and SDCLK 該二電阻是預留給EMI XDALE
XDCD
35
40
XD-ALE SD-CD-SW 1 SDCD
XD-CD
solution使用, (但請靠近RTS5158E側). XD_RDY 39 XD-R/B SD-WP-SW 2 SDWP
SDDAT2_XDRE# 38
XDCE# XD-RE
37 XD-CE
XDCLE 36 26 SDCLK_XDD1_MSCLK
XD-CLE MS-SCLK SDDAT0_XDD6_MSD0 SDCLK_XDD1_MSCLK
MS-DATA0 17
11 15 SDDAT1_XDD3_MSD1 1
7IN1 GND MS-DATA1 SDDAT7_XDD2_MSD2
31 7IN1 GND MS-DATA2 19
24 SDDAT6_XDD7_MSD3 C869
MS-DATA3 MS_INS# @ 22P_0402_50V8J
MS-INS 22
XDD5_MSBS 2
MS-BS 13
41 7IN1 GND
42 7IN1 GND
TAITW_R015-B10-LM
CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2007/8/18 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 401728 A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 04, 2009 Sheet 30 of 49
5 4 3 2 1
 A B C D E

Mini Card Power Rating

For Wireless LAN
Power Primary Power (mA) Auxiliary Power (mA)
+3VS +1.5VS
Peak Normal Normal
+3VS 1000 750
1 1 1 1 1 1
1 C842 C841 C813 C825 C808 C823 1
+3V 330 250 250 (wake enable)
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +1.5VS 500 375 5 (Not wake enable)
2 2 2 2 2 2

JMINI1 +5VALW JP2

SB_PCIE_WAKE# R457 1 @ 2 0_0402_5% 1 2 +3VS 1
<25> SB_PCIE_WAKE# 1 2 <33> LAN_DET 1

4.7U_0805_10V4Z
3 3 4 4 +5VALW 2 2
5 5 6 6 +1.5VS 1 160mil 3 3
<20> MINI1_CLKREQ# 7 7 8 8 4 4
9 9 10 10 80mil +3VALW 5 5
<20> CLK_PCIE_MINI1# 11 11 12 12 6 6
2

C819
<20> CLK_PCIE_MINI1 13 13 14 14 20mil +3VS 7 7
15 15 16 16 8 8
<33> EC_PME# 9 9
<32,38,44> SYSON# 10 10
17 17 18 18 <20> LAN_CLKREQ# 11 11 GND 17
19 20 WL_OFF# <33> EJECTBTN# 12 18
19 20 WL_OFF# <33> 12 GND
21 22 PLT_RST# 13
21 22 PLT_RST# <11,13,14,24,33> <25> USB20_N0 13
23 24 +3V_WLAN R458 1 2 0_0603_5% +3VS 14
<10> PCIE_PTX_C_IRX_N0 23 24 <25> USB20_P0 14
25 26 R459 1 2 0_0603_5% +3VALW 15
<10> PCIE_PTX_C_IRX_P0 25 26 <25> USB20_P2 15
27 28 @ 16
27 28 <25> USB20_N2 16
29 30 SB_CK_SCLK SB_CK_SCLK <8,9,20,25>
29 30 SB_CK_SDAT ACES_85201-1605N
<10> PCIE_ITX_C_PRX_N0 31 31 32 32 SB_CK_SDAT <8,9,20,25>
<10> PCIE_ITX_C_PRX_P0 33 34 CONN@
33 34
35 35 36 36 USB20_N8 <25>
37 38 JP21
37 38 USB20_P8 <25>
+3VS 39 39 40 40 <10> PCIE_PTX_C_IRX_N1 1 1
41 42 (MINI1_LED#) <10> PCIE_PTX_C_IRX_P1 2
41 42 2
43 43 44 44 MINI1_LED# <33> <11,13,14,24,33> PLT_RST# 3 3
2 2
45 45 46 46 <10> PCIE_ITX_C_PRX_N1 4 4
0_0402_5%
R432 1 2 E51TXD_P80DATA_R
47
49
47 48 48
50
(9~16mA) <10> PCIE_ITX_C_PRX_P1 5
6
5
<33> E51TXD_P80DATA 49 50 6
E51RXD_P80CLK 51 52 7
<33> E51RXD_P80CLK 51 52 <20> CLK_PCIE_LAN 7
<20> CLK_PCIE_LAN# 8 8
G1
G2
G3
G3
9 GND1
10 GND2
FOX_AS0B226-S99N-7F
53
54
55
56
CONN@ ACES_88231-08001
CONN@

+3VS_WWAN

+3VS +3VS_WWAN +3VALW

1
+ C394
Mini-Express Card for WWAN 1 2
R218 3G@ 0_1206_5%
1
R156 @
2
0_1206_5%
2
3G@
150U_B2_6.3VM

Close to WWAN CONN

JMINI2
SB_PCIE_WAKE# 1 2 1 2
R460 @ 0_0402_5% 1 2
3 3 4 4
5 5 6 6 +1.5VS
<20> WWAN_CLKREQ# WWAN_CLKREQ# 7 8 +UIM_PWR
7 8 UIM_DATA
9 9 10 10
11 12 UIM_CLK
<20> CLK_PCIE_WWAN# 11 12
13 14 UIM_RST
<20> CLK_PCIE_WWAN 13 14
15 16 UIM_VPP
15 16

17 17 18 18
3 WXMIT_OFF# 3
19 19 20 20 WXMIT_OFF# <33>
21 22 PLT_RST#
21 22
<10> PCIE_PTX_C_IRX_N2 23 23 24 24 1 2 +3VS_WWAN
<10> PCIE_PTX_C_IRX_P2 25 26 R159 3G@ 0_0402_5%
25 26
27 27 28 28 1 2 +3VALW
29 30 R409 @ 0_0402_5%
29 30
<10> PCIE_ITX_C_PRX_N2 31 31 32 32
<10> PCIE_ITX_C_PRX_P2 33 33 34 34
35 35 36 36 USB20_N5 <25>
37 37 38 38 USB20_P5 <25>
+3VS_WWAN 39 39 40 40
1 2 41 41 42 42 WWAN_LED# <33>
43 43 44 44
D8 C317 3G@10U_0805_10V4Z
@ CM1293-04SO_SOT23-6
45
47
45 46 46
48
(9~16mA)
UIM_VPP UIM_CLK 47 48
1 CH1 CH4 4 49 49 50 50
51 51 52 52
G1
G2
G3
G3

2 Vn Vp 5 +UIM_PWR
FOX_AS0B226-S99N-7F
53
54
55
56

CONN@ +3VS_WWAN

UIM_RST 3 6 UIM_DATA
CH2 CH3
1 1 1 1
C324 C125 C205 C203
JP5 40mil 3G@ 3G@ 3G@ 3G@
4 1 +UIM_PWR 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.01U_0402_25V7K
UIM_VPP GND VCC UIM_RST 2 2 2 2
5 VPP RST 2
UIM_DATA 6 3 UIM_CLK
I/O CLK
1U_0402_6.3V4Z

0.1U_0402_16V4Z

7 DET
22P_0402_50V8J

1 1

hexainf@hotmail.com
22P_0402_50V8J

22P_0402_50V8J

3G@ C277

3G@ C272

4 4
1 1 1
1
10K_0402_5%
C123

R217

C124

C325

GND 8
@ 2 2
GND 9
@ @ 2 @ 2 2
2

+UIM_PWR Security Classification Compal Secret Data Compal Electronics, Inc.

TAITW_PMPAT6-06GLBS7N14N0 CONN@ 2008/10/06 2009/10/06 Title
Issued Date Deciphered Date
Reserve for SIM card does not meet rise time THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
Size Document Number Rev
and pull-up is needed. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 31 of 49
A B C D E
 A B C D E

Bluetooth Conn. USB PORT x 2

+USB_VCCA

+3VALW +3VS +USB_VCCA

1 W=80mils
1
+ C531 C427
1 JM@
1 C839 C832 150U_B2_6.3VM 470P_0402_50V7K 1
2 2
0.1U_0402_16V4Z 1U_0402_6.3V4Z

3
2
S
AO3413_SOT23-3
G
<33> BT_ON# 1 2 2
R451 10K_0402_5% Q41 1 2
D R172 @ 0_0402_5%

1
C840 W=40mils
+BT_VCC JM@ L36 JUSB1
0.1U_0402_16V4Z USB20_N6 4 3 1
<25> USB20_N6 4 3 1
1 USB20_N6_R 2 2

1
C830 C831 USB20_P6_R 3
R450 USB20_P6 3
<25> USB20_P6 1 1 2 2 4 4
4.7U_0805_10V4Z 300_0603_5% 5
2 0.1U_0402_16V4Z WCM2012F2S-900T04_0805 GND
6 GND
7

2
GND
8 GND
1 2

1
D R170 @ 0_0402_5% SUYIN_020133MB004S580ZL-C D18
2 Q42 CONN@ USB20_P1_R 6 3 USB20_P6_R
G 2N7002_SOT23 CH3 CH2
S

3
+USB_VCCA 5 2
+USB_VCCA Vp Vn
+USB_VCCA
1 W=80mils USB20_N6_R USB20_N1_R
1 4 CH4 CH1 1
+BT_VCC + C406 C246
@ CM1293-04SO_SOT23-6
JP4 150U_B2_6.3VM 470P_0402_50V7K
2 2 2 Change to Panjit SC300000B00 2
8 8 GND 10
7 7
<25> USB20_P12 6 6
<25> USB20_N12 5 5
4 4 1 2
3 R102 @ 0_0402_5%
3
2 2
1 1 GND 9
L29 JUSB2
CONN@ USB20_N1 4 3 1
<25> USB20_N1 4 3 1
ACES_87213-0800G USB20_N1_R 2
USB20_P1_R 2
3 3
Swap for new footprint USB20_P1 1 2 4
<25> USB20_P1 1 2 4
5
20090303 WCM2012F2S-900T04_0805 6
GND
GND
7 GND
8 GND
1 2
R103 @ 0_0402_5% SUYIN_020133MB004S580ZL-C
CONN@

+3VALW

+5VALW

1
+USB_VCCA R166
U16 80mil R168 0_0402_5%
3 100K_0402_5% 3
1 GND OUT 8 1 2 USB_OC#1 <25>
2 IN OUT 7
3 6

2
IN OUT R167 1
1 4 EN# FLG 5 2 10K_0402_5% USB_OC#0 <25>
C428
TPS2061DRG4_SO8
4.7U_0805_10V4Z 1
2 C421
0.1U_0402_16V4Z
2
<31,38,44> SYSON#

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 32 of 49
A B C D E
 5 4 3 2 1

+3VL
+3VL For EC Tools
+3VALW L43
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2+EC_VCCA +3VL
60mil 1 2 +3VL 1 1 C501 1 1 2
1
2 FBM-L11-160808-800LMT_0603 JP6 Place on RAM door
R256 @ 0_0805_5% C537 1 KSI[0..7] 1
KSI[0..7] <34> 1
+3VLP 1 2 C525 C546 C548 C549 2 E51RXD_P80CLK
KSO[0..17] 2 E51RXD_P80CLK <31>
R261 0_0805_5% 1000P_0402_50V7K C502 E51TXD_P80DATA
60mil 2 2 2 2 1 1
1000P_0402_50V7K KSO[0..17] <34> 3
4
3
4
E51TXD_P80DATA <31>
2

ECAGND
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z KSI[0..7]
KSI[0..7] <34>
ACES_85205-0400
ENBKL @
ENBKL <11>
D D
+3VL +3VL
DVT2

111
125
22
33
96

67
9
U20 65W/90W# 2 1
2 1 LID_SW# R205 100K_0402_5%

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
R221 100K_0402_5% VR_ON 2 1
R213 100K_0402_5%
ESD 3S/4S# 1 2
2 1 PLT_RST# EC_GA20 1 21 INVT_PWM R203 4.7K_0402_5%
<25> EC_GA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM <21>
@ C778 10P_0402_50V8J EC_KBRST# 2 23 BEEP#
<25> EC_KBRST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# <36>
SERIRQ 3 26
<24> SERIRQ LPC_FRAME# SERIRQ# FANPWM1/GPIO12 ACOFF
<24> LPC_FRAME# 4 LFRAME# ACOFF/FANPWM2/GPIO13 27 ACOFF <41,45>
C547 LPC_AD3 5 2 1 ECAGND
<24> LPC_AD3 LAD3
@ 22P_0402_50V8J LPC_AD2 7 PWM Output C520 0.01U_0402_25V7K
<24> LPC_AD2 LAD2
2 1 R220 2 1 @ 33_0402_5% LPC_AD1 8 63 BATT_TEMP Analog Project ID definition
<24> LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP <40>
LPC_AD0 BATT_OVP
<24> LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
BATT_OVP <41>
ADP_I/AD2/GPIO3A 65 ADP_I <41>
CLK_PCI_EC 12 AD Input 66 AD_BID0 +3VL
<24,28> CLK_PCI_EC PCICLK AD3/GPIO3B
PLT_RST# 13 75
<11,13,14,24,31> PLT_RST# PCIRST#/GPIO05 AD4/GPIO42
37 76 AD_PID0
ECRST# SELIO2#/AD5/GPIO43

2
EC_SCI# 20
<25> EC_SCI# SCI#/GPIO0E
+3VL 2 1 38 R181
R215 47K_0402_5% CLKRUN#/GPIO1D DAC_BRIG 100K_0402_5%
DAC_BRIG/DA0/GPIO3C 68 DAC_BRIG <21> Ra
2 1 70 EN_DFAN1
EN_DFAN1/DA1/GPIO3D EN_DFAN1 <4>
+5VS C533 0.1U_0402_16V4Z DA Output 71 IREF
IREF <41>

1
KSI0 IREF/DA2/GPIO3E CALIBRATE# AD_PID0
55 KSI0/GPIO30 DA3/GPIO3F 72 CALIBRATE# <41>
KSI1 56 KSI1/GPIO31

2
1 2 TP_CLK KSI2 57 KSI2/GPIO32 1
R189 4.7K_0402_5% KSI3 58 83 WXMIT_OFF# Rb R180 C488
KSI3/GPIO33 PSCLK1/GPIO4A WXMIT_OFF# <31>
C 1 2 TP_DATA KSI4 59 KSI4/GPIO34 PSDAT1/GPIO4B 84 C
R188 4.7K_0402_5% KSI5 60 85 TP_LOCK _LED# TP_LOCK _LED# <34> 33K_0402_5% 0.1U_0402_16V4Z
+3VS KSI6 KSI5/GPIO35 PSCLK2/GPIO4C 2
61 PS2 Interface 86

1
KSI7 KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK
ESB_CK KSO0
62 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E 87
TP_DATA
TP_CLK <34> DVT
1 2 39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA <34>
R257 2.2K_0402_5% KSO1 40
ESB_DA KSO2 KSO1/GPIO21
1 2 41 KSO2/GPIO22
R258 2.2K_0402_5% KSO3 42 97 3S/4S# Analog Board ID definition
KSO3/GPIO23 SDICS#/GPXOA00 3S/4S# <41>
1 2 EC_SMB_CK2 KSO4 43 98 65W/90W#
KSO4/GPIO24 SDICLK/GPXOA01 65W/90W# <41>
R191 2.2K_0402_5% KSO5 EC_VLDT_EN +3VL
EC_SMB_DA2 KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW#
EC_VLDT_EN <35>
1 2 45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109
R190 2.2K_0402_5% KSO7 46 SPI Device Interface
KSO7/GPIO27

2
1 2 EC_I2C_INT1 KSO8 47
R259 2.2K_0402_5% KSO9 KSO8/GPIO28 R195
48 KSO9/GPIO29 SPIDI/RD# 119 EC_SI_SPI_SO <34>
Follow ENE check KSO10 49 120 Ra
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI <34>
KSO11 50 SPI Flash ROM 126 100K_0402_5%
+3VL KSO11/GPIO2B SPICLK/GPIO58 EC_SPICLK <34>
KSO12 51 128 EC_SPICS#/FSEL# <34>

1
KSO13 KSO12/GPIO2C SPICS# AD_BID0
52 KSO13/GPIO2D
1 2 EC_SMB_CK1 KSO14 53 KSO14/GPIO2E

1
R193 2.2K_0402_5% KSO15 54 73 1
KSO15/GPIO2F CIR_RX/GPIO40
1 2 EC_SMB_DA1 KSO16 81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74 EC_I2C_INT1 ESD Rb R194 C503
R192 2.2K_0402_5% KSO17 82 89
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG <41>
1 2 KSO1 90 BATT_BLUE_LED# BATT_BLUE_LED# <35> 18K_0402_5% 0.1U_0402_16V4Z
R75 47K_0402_5% BATT_CHGI_LED#/GPIO52 EJECTBTN# EJECTBTN# 1 2
91 EJECTBTN# <31> 2

2
KSO2 EC_SMB_CK1 CAPS_LED#/GPIO53 BATT_AMB_LED#
1 2 <40> EC_SMB_CK1 77 SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54 92 BATT_AMB_LED# <35>
R78 47K_0402_5% EC_SMB_DA1 78 93 PWR_LED PWR_LED <35> C39 0.1U_0402_16V4Z DVT2
<40> EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55
EC_SMB_CK2 79 SM Bus 95 SYSON
<6,19> EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON <38,43>
Follow ENE AP sheet EC_SMB_DA2 80 121 VR_ON
<6,19> EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <46>
KB926D-AN1-100 127 ACIN
B AC_IN/GPIO59 ACIN <26,39> B
EC_CRY1 EC_CRY2
1 2 EJECTBTN# PM_SLP_S3# 6 100 EC_RSMRST#
<25> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# <25>
R260 2.2K_0402_5% PM_SLP_S5# 14 101 EC_LID_OUT# 2 2
<25> PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# <25>
Follow ENE check EC_SMI# 15 102 EC_ON
<25> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <35>

4
+3VL AD_ON# 16 103 EC_SWI# C532 C535
<39> AD_ON# LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SWI# <25>
ESB_CK 17 104 EC_PWROK 15P_0402_50V8J

OUT
IN
SUSP#/GPIO0B ICH_PWROK/GPXO06 EC_PWROK <35> 1 1
1 2 EC_PME# ESB_DA 18 GPO 105 BKOFF# 15P_0402_50V8J
PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# <21>
R222 @ 10K_0402_5% 19 GPIO 106 WL_OFF#
EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# <31>
25 EC_THERM#/GPIO11 GPXO10 107
FAN_SPEED1

NC

NC
<4> FAN_SPEED1 28 FAN_SPEED1/FANFB1/GPIO14 GPXO11 108
BT_ON# 29
<32> BT_ON# FANFB2/GPIO15
E51TXD_P80DATA 30

3
E51RXD_P80CLK EC_TX/GPIO16 VGATE
31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 VGATE <46>
ON/OFF 32 112 ENBKL 1 2
<35> ON/OFF ON_OFF/GPIO18 ENBKL/GPXID2 VGA_ENBKL <15>
<35> PWR_SUSP_LED PWR_SUSP_LED 34 114 EAPD
PWR_LED#/GPIO19 GPXID3 EAPD <36>
<31> LAN_DET LAN_DET 36 GPI 115 EC_THERM# D41 RB751V_SOD323 X1
NUMLED#/GPIO1A GPXID4 EC_THERM# <26>

1
ESB_CK 1 2 116 SUSP# VGA@ 32.768KHZ_12.5P_MC-306
GPXID5 SUSP# <35,38,41,45>
JM@ R562 0_0402_5% 117 PBTN_OUT#
For Lid SW GPXID6 EC_PME# PBTN_OUT# <25> R211
GPXID7 118 EC_PME# <31>
C541 @ 33P_0402_50V8K EC_CRY1 122 10K_0402_5%
+3VL EC_CRY2 XCLK1
123 124

2
ESB_DA +3VS XCLK0 V18R
1 2 1
AGND

JM@ R563 0_0402_5% +5VS

GND
GND
GND
GND
GND

JP3 C534 C523 100P_0402_50V8J

C540 @ 33P_0402_50V8K 1 4.7U_0805_10V4Z BATT_TEMP 2 1
1 KB926QFB1_LQFP128_14X14 2 C514 100P_0402_50V8J
2
11
24
35
94
113

69

KSO3 2 BATT_OVP
1 2 3 3 KS03 20mil 2 1
HM@ R564 0_0402_5% MEDIA_CK 4 L44 C539 100P_0402_50V8J

hexainf@hotmail.com
A 4 A
KSI5 1 2 MEDIA_DA 5 KSI4 TP Lock ECAGND 2 1 ACIN 2 1
EC_I2C_INT1 1 HM@ R565 0_0402_5% 5 FBM-L11-160808-800LMT_0603
2 6
JM@R566
JM@R566 0_0402_5% <31> MINI1_LED# MINI1_LED# 7
6
7 KSI5 WL_BTN# KB926 Rev:D3(SA00001J580)
KSI4 1 2 <31> WWAN_LED# WWAN_LED# 8
HM@R567 0_0402_5% MEDIA_LED# 8
<35> MEDIA_LED# 9 9
Modify for e-Machine
LID_SW#
TP_LOCK _LED# 1 2
10
11
10
11 GND 13
20090415 Security Classification Compal Secret Data Compal Electronics, Inc.
HM@R568 0_0402_5% 12 14 2008/10/06 2009/10/06 Title
12 GND Issued Date Deciphered Date
JM@
1
JM@R569
R569
2
0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
ACES_85201-1205N AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
CONN@ B A
To Media/B Conn. DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 33 of 49
5 4 3 2 1
 BIOS(SYS / EC / VGA)
To TP/B Conn.
+3VALW C512 1 2 0.1U_0402_16V4Z
JP7
12 GND
+SPI_VCC 11 GND
+5VS 10 10
U19 9
EC_SPICS#/FSEL# R208 0_0402_5% TP_CLK +3VS 9
<33> EC_SPICS#/FSEL# 1 CE# VDD 8 <33> TP_CLK 8 8
R207 1 2 4.7K_0402_5% SPI_WP# 3 6 1 2 TP_DATA 7
WP# SCK EC_SPICLK <33> <33> TP_DATA 7
+3VALW R204 1 2 4.7K_0402_5% SPI_HOLD# 7 HOLD# SI 5 EC_SO_SPI_SI <33>
KSO3 6 6
4 2 KSI4 5
VSS SO EC_SI_SPI_SO <33> 5
<33> TP_LOCK _LED# TP_LOCK _LED# 4
MX25L8005M2C-15G_SOP8 4
1 1 3 3

1
C403 2
R206 C404 2
1 1
22_0402_5% 100P_0402_50V8J 100P_0402_50V8J
@ 2 2 ACES_85201-1005N
CONN@

2
C524
33P_0402_50V8K
TP_CLK
@ +5VS
TP_DATA

3
C402

D9 0.1U_0402_16V4Z

PSOT24C_SOT23

1
INT_KBD Conn.
JP8
KSI[0..7]
KSI[0..7] <33>
(Left) KSO0 1
KSO1 1 KSO[0..17]
2 2 KSO[0..17] <33>
KSO2 3
KSO3 3
4 4
KSO4 5
KSO5 5
6 6
KSO6 7
KSO7 7
8 8
KSO8 9
KSO9 9
10 10
KSO10 11
KSO11 11
12 12
KSO12 13
KSO13 13
14 14
KSO14 15
KSO15 15
16 16
KSO16 17
KSO17 17
18 18
KSI0 19
KSI1 19
20 20
KSI2 21
KSI3 21
22 22
KSI4 23
KSI5 23
24 24
KSI6 25 27
KSI7 25 G1
(Right) 26 26 G2 28

ACES_85201-26051 KSO16 C449 1 2 100P_0402_50V8J

CONN@
KSO17 C450 1 2 100P_0402_50V8J
KSO4 KSO2 KSO3
KSO15 C448 1 2 100P_0402_50V8J KSO7 C440 1 2 100P_0402_50V8J

KSO14 C447 1 100P_0402_50V8J KSO6 C439 1 100P_0402_50V8J

KSI5 WL_BTN# Volume Down Back Up
2 2

KSO13 C446 1 2 100P_0402_50V8J KSO5 C438 1 2 100P_0402_50V8J Program (KBLG0)

KSO12 C445 1 100P_0402_50V8J KSO4 C437 1 100P_0402_50V8J
KSI6 BT_BTN# Volume Up
2 2 Battery (KALG0)

KSI0 C451 1 2 100P_0402_50V8J KSO3 C436 1 2 100P_0402_50V8J KSI4 T/P lock

KSO11 C444 1 2 100P_0402_50V8J KSI4 C455 1 2 100P_0402_50V8J

KSO10 C443 1 2 100P_0402_50V8J KSO2 C435 1 2 100P_0402_50V8J

KSI1 C452 1 2 100P_0402_50V8J KSO1 C434 1 2 100P_0402_50V8J

KSI2 C453 1 2 100P_0402_50V8J KSO0 C433 1 2 100P_0402_50V8J

KSO9 C442 1 2 100P_0402_50V8J KSI5 C456 1 2 100P_0402_50V8J

KSI3 C454 1 2 100P_0402_50V8J KSI6 C457 1 2 100P_0402_50V8J

KSO8 C441 1 2 100P_0402_50V8J KSI7 C458 1 2 100P_0402_50V8J

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 34 of 49
 A B C D E

Power Button To PWR/B Conn.

+5VS +5VALW
ON/OFF switch
JP9
1
ON/OFFBTN# 2
+3VALW 3
TOP Side PWR_LED#
PWR_SUSP_LED# 4
5
1 2 6
1 R5 @ 10K_0603_5% 1

2
ACES_85201-0605
1 2 R8 CONN@
R4 @ 10K_0603_5%
100K_0402_5%
Bottom Side

1
D3
2 ON/OFF <33>
ON/OFFBTN# 1
3 51ON# <39>
DAN202UT106_SC70-3

GA_ON/OFFBTN# 1 2 PWR_LED# PWR_SUSP_LED#

<39> GA_ON/OFFBTN#
R268 0_0402_5%
Green adapter on/off control

1
D

3
EC_ON 2 Q1
<33> EC_ON
G

2
S 2N7002_SOT23

3
R6 <33> PWR_LED 2 Q31A <33> PWR_SUSP_LED 5
2N7002DW-T/R7_SOT363-6

1
10K_0402_5% Q31B

4
R240 R249 2N7002DW-T/R7_SOT363-6

1
10K_0402_5% 10K_0402_5%
2 2

2
+3VS

+3VS

2
Power ON Circuit @ R10

Q2A 10K_0402_5%

2
2N7002DW-T/R7_SOT363-6

1
+3VS
6 1 5IN1_LED# <30>
+3VALW +3VALW
MEDIA_LED# 3 4
<33> MEDIA_LED# SATA_LED# <26>
1

U22A U22B
R235 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 Q2B
For South Bridge
14

14

5
@ 180K_0402_5% @ @ 2N7002DW-T/R7_SOT363-6 +3VS
P

P
2

1 I O 2 3 I O 4 1 2 SB_PWRGD <6,25>
1U_0402_6.3V4Z

R234 @ 0_0402_5%
1

D
1
C568

<29,38> SUSP 2 LED9

7

G
Q25 S +5VALW 1 2 2 1 BATT_BLUE_LED#
BATT_BLUE_LED# <33>
3

@ 2N7002_SOT23 2 R245 4.99K_0402_1% HT-191NBQA_BLUE_0603

<33> EC_PWROK 1 2
R233 0_0402_5%
3 @ BATT_AMB_LED# 3
+5VALW 1 2 2 1 BATT_AMB_LED# <33>
R244 4.99K_0402_1% HT-191NBQA_BLUE_0603
+3VS LED10

+3VALW +3VALW
1

LED11
R236
U22C U22D
For +1.2HT BATT_BLUE_LED#
14

14

+5VALW 1 2 2 1 BATT_BLUE_LED# <33>

@ 10K_0402_1% SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 R247 4.99K_0402_1% HT-191NBQA_BLUE_0603
D23
@ @
P

P
2

SUSP# 1 2 5 @ BATT_AMB_LED#
<33,38,41,45> SUSP# I O 6 9 I O 8 1
R232
2
0_0402_5%
VLDT_EN <38,43,44> +5VALW 1 2
R246 4.99K_0402_1%
2 1
HT-191NBQA_BLUE_0603
BATT_AMB_LED# <33>
2
G

@ RB751V_SOD323 C567 LED12

7

@ 0.1U_0402_16V4Z
1 <33> EC_VLDT_EN 1
R228
2
0_0402_5% BLUE / AMBER

+3VALW +3VALW

C565 @ 0.1U_0402_16V4Z
1 2

U22E U22F
For +VGA_CORE
14

14

SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
R230 @ 200K_0402_5% @ @ @
P

SUSP# 1 2 11 I O 10 13 I O 12 1
R231
2
0_0402_5%
VGA_ON <47>
G

2
1 2 C563

hexainf@hotmail.com
7

4 0.1U_0402_16V4Z 4
2
D21 @ RB751V_SOD323 VGA@ @
C564 SUSP# 1
1 2
0.22U_0603_16V7K R229 0_0402_5%
1 @

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 35 of 49
A B C D E
 5 4 3 2 1

+5VS
Codec Regulator
+5V_VDDA_HD
Beep Circuit +3VS +5V_VDDA_HD
U62

1
4.7U_0805_10V4Z +5V_VDDA_HD
C1023
1 VIN VOUT 5 4.75v R838 R839
C1024 2 +5VS 10K_0402_5% 20K_0402_1%
0.1U_0402_16V4Z GND C1025
C1026 4.7U_0805_10V4Z
W=40mil EC Beep
3 4

2
SHDN# BP @ C1027 1 R840
2 1 1 1 <33> BEEP# 2 1 2
D 1 2 C1030 D
+5VS 560_0402_5%
R841 10K_0402_5% 0.22U_0402_6.3V6K C1028 C1029 1U_0402_6.3V4Z 1 2 MONO_IN
APL5151-475BC-TRL_SOT23-5 10U_0805_10V4Z 0.1U_0402_16V4Z C1031
2 2
<25> SB_SPKR 1 2 1R842 2 1U_0402_6.3V4Z
1 2
1U_0402_6.3V4Z 560_0402_5%
R843

1
C
+5VS 2.4K_0402_5%
2
B Q72
W=40mil

1
E

3
1
1 1 MMBT3904_SOT23-3
D43 R844
C1032 C1033 CH751H-40PT_SOD323-2 10K_0402_5%
10U_0805_10V4Z 0.1U_0402_16V4Z @

2
2 2

2
+3VS L92 +3VS_HD
20mil
+HD_AVDD +5V_VDDA_HD
2 1 1 10U_0805_10V4Z 0.1U_0402_16V4Z
40mil
10mil FBMA-L11-160808-800LMT_0603 L93
INT MIC C1034
@ C1035
1
C1036
1
C1037
1
100P_0402_50V8J 0.1U_0402_16V4Z 2 1
2 1 1 1 1 FBMA-L11-160808-800LMT_0603
+MIC1_VREFO_L +MIC1_VREFO_R 100P_0402_50V8J 2 2 2 C1038 C1039 C1040 C1041
10mil 0.1U_0402_16V4Z @
2 2 2 2
Left Main Speaker Connector

39

46

25

38
1

9
0.1U_0402_16V4Z 10U_0805_10V4Z
R845 R846 U63

DVDD_IO

PVDD1

PVDD2

AVDD1

AVDD2
DVDD
4.7K_0402_5% 4.7K_0402_5%
For EMI
Chage to BEAD SM01000CB00 +3VS
2

JP19
C C1042
1 2 100P_0402_50V8J 23 40 SPKL+ 1 C
@ LINE1_L SPK_OUT_L+ SPKL- DMIC_CLK R849 0_0603_5% DMIC_CLK_R 1
24 LINE1_R SPK_OUT_L- 41 2 2
<37> MIC1_L 2 1 MIC1_R_L 1 2 MIC1_C_L DMIC_DATA DMIC_DATA_R 3 3 G1 5
R847 1K_0402_5% C1045 4.7U_0805_10V4Z 14 45 SPKR+ R848 0_0603_5% 4 6
LINE2_L SPK_OUT_R+ 4 G2
<37> MIC1_R 2 1 MIC1_R_R 1 2 MIC1_C_R 15 LINE2_R SPK_OUT_R- 44 SPKR-
R850 1K_0402_5% C1043 4.7U_0805_10V4Z ACES_88266-04001
@ 1 2 MIC1_C_L 21 32 CONN@
MIC1_L HP_OUT_L HP_L <37>

2
C1044 100P_0402_50V8J MIC1_C_R 22 33 1 2
MIC1_R HP_OUT_R HP_R <37>
D44
16 SM05T1G_SOT23-3 C1047
MIC2_L
17 MIC2_R 220P_0402_50V8J
2 1
SYNC 10 HDA_SYNC_AUDIO <25>

1
DMIC_DATA 2 6 HDA_BITCLK_AUDIO HDA_BITCLK_AUDIO <25> HDA_BITCLK_AUDIO 1 2 1 2 C1046
GPIO0/DMIC_DATA BCLK 220P_0402_50V8J
DMIC_CLK 3 R851 C1048
GPIO1/DMIC_CLK @ 22_0402_5% @ 10P_0402_50V8J
SDATA_OUT 5 HDA_SDOUT_AUDIO <25>
R852
4 8 AZ_SDIN0_HD_R 1 2
<33> EAPD PD# SDATA_IN HDA_SDIN0 <25>
33_0402_5%

<25> HDA_RST_AUDIO# 11 RESET# EAPD/SPDIFO2 47

48 +MIC1_VREFO_R +MIC1_VREFO_L
SPDIFO SPDIF <37>
MONO_IN 12 PCBEEP
MONO_OUT 20

SENSE_A 13 C1050 C1051

SENSE A 0.1U_0402_16V4Z 0.1U_0402_16V4Z
MIC2_VREFO 29
SENSE_A
<37> NBA_PLUG 2
R853
1
39.2K_0402_1%
18 SENSE B
30
10mil
MIC1_VREFO_R +MIC1_VREFO_R
<37> MIC_SENSE 1 2 1 2 36 CBP MIC1_VREFO_L 28 +MIC1_VREFO_L
B R854 20K_0402_1% C1052 2.2U_0402_6.3V4Z B
35 27
10mil
CBN VREF
1 1
31 19
EXPOSE_PAD

CPVREF JDREF C1053 C1054

1
43 34 10U_0805_10V4Z 0.1U_0402_16V4Z
PVSS2 CPVEE 2 @ 2
42 2 For EMI
PVSS1 C1055 R856
26 Change to SM01000AL00
7 DVSS
AVSS1
AVSS2 37 2.2U_0402_6.3V4Z 20K_0402_1% Speaker Conn.

2
ALC269Q-GR_QFN48_7X7AGND 1
DGND
49

SPKL+ 1 L94 2 0_0603_5% SPK_L1

Sense Pin Impedance Codec Signals JP20
1 1
39.2K PORT-A (PIN 32, 33) SPKL- 1 L95 2 0_0603_5% SPK_L2 2
SPKR+ 2
1 L96 2 0_0603_5% SPK_R1 3 3 G1 5
DGND To AGND Bypass 4 4 G2 6
20K PORT-B (PIN 21, 22) ACES_88266-04001
SENSE A 1
R857
2
0_0603_5% SPKR- 1 L97 2 0_0603_5% SPK_R2 CONN@
10K PORT-C (PIN 23, 24) 1 2

3
R858 0_0603_5%
1 2 D45 D46
5.1K PORT-D (PIN 48) R859 0_0603_5% PJDLC05_SOT23-3 PJDLC05_SOT23-3
1 2
R860 0_0603_5%
39.2K PORT-E (PIN 14, 15) 1
R861
2
0_0603_5%

20K PORT-F (PIN 16, 17)

1
A
SENSE B DGND AGND A

10K PORT-G (PIN 20)

5.1K PORT-H (PIN 47)

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 401728 A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 04, 2009 Sheet 36 of 49
5 4 3 2 1
 5 4 3 2 1

+5VAMP change to +5VS

20090408 +5VS

+5VS
NBA_PLUG
NBA_PLUG <36>

3
GNDA R513
100K_0402_5%

2
Q77B
H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 R512 5 2N7002DW-T/R7_SOT363-6

6 1
D H_7P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 D
100K_0402_5%

4
1
3
S
@ @ @ @ @ @ @ @ @ @ Q43 Q77A
1

1
G
JM@ 2 SPDIF_PLUG# 2 2N7002DW-T/R7_SOT363-6
AO3413_SOT23-3
D

1
3

2
H11 H12 H13 H14 H15 H16
H_3P0 H_3P0 H_3P4 H_3P9 H_3P9 H_3P0 +5VSPDIF

20mil <BOM Structure>

@ @ @ @ @ @
1

1
D32
PJDLC05_SOT23-3

1
H21 H22 H23 H24 For ESD Protect
H_4P2 H_4P2 H_4P2 H_4P2

@ @ @ @ HeadPhone JACK
1

JHP1 connector Pin1/4 need change by PVT-3/17 JHP1

Update ok-4/14 6
C C
1 2 HPR_L 1 2 HPL 1
<36> HP_L
R862 75_0402_1% L98 BLM15AG121SN1D_0402
H31 H32 H33 H34 1 2 HPR_R 1 2 HPR 4
<36> HP_R
H_4P0N H_4P1X4P4N H_4P1X4P4N H_2P2N R863 75_0402_1% L99 BLM15AG121SN1D_0402
5

2
10P_0402_50V8J

10P_0402_50V8J
1 1
@ @ @ @ SPDIF_PLUG# 7
1

C1056 C1057 +5VSPDIF 3

@ @ SPDIF 8
2 2 <36> SPDIF
FD1 FD2 FD3 FD4 D47 1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 C584 2
100P_0402_50V8J
PJDLC05_SOT23-3 SINGA_2SJ1533-000111

1
@ @ @ @ 2 CONN@
1

B B

Ext.MIC JACK
JMIC1
1
MIC1_L 1 2 MIC1_L_1 2
<36> MIC1_L
L100BLM15AG121SN1D_0402
MIC1_R 1 2 MIC1_R_1 3
<36> MIC1_R
L101BLM15AG121SN1D_0402

2
220P_0402_50V8J

220P_0402_50V8J
1 1 4
C1058 C1059

@
<36> MIC_SENSE 5
2 2
D48
6

PJDLC05_SOT23-3 SINGA_2SJ-0960-C01

1
CONN@

A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 401728 A

hexainf@hotmail.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 04, 2009 Sheet 37 of 49
5 4 3 2 1
 A B C D E

+5VALW

+5VALW TO +5VS +1.2VALW TO +1.2V_HT

2
+5VALW +5VS R169
4.305A +1.2VALW +1.2V_HT 100K_0402_5%
U24 3.265A
8 1 U17

1
D S
7 D S 2 8 D S 1

2
6 3 1 1 DVT 7 2 SYSON#
D S D S <31,32,44> SYSON#

2
1 1 5 4 C576 R238 6 3 1 1
D G D S

1
C571 C570 470_0603_5% C470 R197 D
1 5 D G 4
SI4800BDY_SO8 10U_0805_10V4Z C573 R202 C509 470_0603_5% SYSON 2 Q21
2 2 <33,43> SYSON
10U_0805_10V4Z 1K_0402_5% SI4800BDY_SO8 10U_0805_10V4Z C462 G 2N7002_SOT23

1
1 2 2
10U_0805_10V4Z 1U_0402_6.3V4Z 2 2 S 1

3
1
2 1U_0402_6.3V4Z

2
6
10U_0805_10V4Z R174

6
100K_0402_5%

5VS_GATE 2N7002DW-T/R7_SOT363-6 SUSP

+VSB 2 1 2

2
R239 Q29A 1.2VS_GATE 2N7002DW-T/R7_SOT363-6 VLDT_EN#
+VSB 2 1 2
200K_0402_5% R196 Q22A
1

1
3

C577 200K_0402_5% +5VALW

1
1

3
0.1U_0603_25V7K C506
2N7002DW-T/R7_SOT363-6 2

2
SUSP 5
Q29B 0.1U_0603_25V7K R242
VLDT_EN# 2 100K_0402_5%
5
4

Q22B

1
2N7002DW-T/R7_SOT363-6 SUSP
<29,35> SUSP

1
D
2 Q30
<33,35,41,45> SUSP#
G 2N7002_SOT23
S

3
1
+3VALW TO +3VS R248
+3VALW +3VS 10K_0402_5%
4.121A

2
U23 +5VALW
8 D S 1
7 D S 2
2

2
6 D S 3 1 1
2 C572 R243 R43 2
1 1 5 D G 4
C575 C574 470_0603_5% 100K_0402_5%
SI4800BDY_SO8 10U_0805_10V4Z C569
10U_0805_10V4Z 2 2
1 1

1
2 2
10U_0805_10V4Z 1U_0402_6.3V4Z VLDT_EN#
D
2 SUSP

1
G D
S Q27 <35,43,44> VLDT_EN 2 Q4
3

5VS_GATE 2N7002_SOT23 G 2N7002_SOT23

S

3
1
R40
10K_0402_5%

2
+1.8V to +1.8VS
+1.8V +1.8VS
6.988A
U40
8 D S 1
7 D S 2
2

6 D S 3 1 1
1 1 5 4 C712 R292
C714 C710 D G 470_0603_5%
SI4800BDY_SO8 10U_0805_10V4Z C709
3 2 2 3
1

2 2 1U_0402_6.3V4Z
10U_0805_10V4Z 10U_0805_10V4Z
6

1.8VS_GATE 2N7002DW-T/R7_SOT363-6 SUSP

+VSB 2 1 2
R271 Q46A
200K_0402_5%
1

1
3

C711

0.1U_0603_25V7K
SUSP 2
5

Q46B
4

2N7002DW-T/R7_SOT363-6

+1.5VS +2.5VS +0.9V +1.8V +1.1VS

2

4 R241 R153 R112 R113 R41 4

470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5%
1

1
1

D D D D D
2 SUSP 2 SUSP 2 SYSON# 2 SYSON# 2 VLDT_EN#
G G G G G Security Classification Compal Secret Data Compal Electronics, Inc.
S Q26 S Q18 S Q11 S Q12 S Q5 2008/10/06 2009/10/06 Title
Issued Date Deciphered Date
3

2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 38 of 49
A B C D E
 A B C D

03/05 change footprint (refer to the JAL70)

Vin Dectector

PL1
VIN Min. Typ Max.
PJP1
DC_IN_S1
SMB3025500YA_2P H-->L 16.976V 17.525V 17.728V
1 1 1 2DC_IN_S2
2 2 L-->H 17.430V 17.901V 18.384V
3 AD_ON
3

1
4 PC3
4 PC1 PC2 100P_0402_50V8J PC4
5 5
6 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K

2
6
1
GND 7 1

GND 8

ACES_88299-0600

PR1
1M_0402_1%
1 2
- PBJ1 + +RTCBATT
VIN VIN
2 1 +RTCBATT

1
VS
PR4 @PR2
@ PR2 PR3
0_0402_5% 10K_0402_5% 84.5K_0402_1%
ML1220T13RE 1 2 PR5 PR6
<26,33> ACIN

8
<BOM Structure> 10K_0402_1% 22K_0402_5%

2
VIN 3 1 2

P
PACIN +
1 2 1 0
<41,45> PACIN

20K_0402_1%
- 2

1
G

PR7
PU1A

1
PC6
0.1U_0603_25V7K
LM358DT_SO8 PC5

4
PD1 PR8 PD2 1000P_0402_50V7K

2
LL4148_LL34-2 10K_0402_1% GLZ4.3B_LL34-2

2
PD3

2
LL4148_LL34-2
BATT+ 2 1

1
PR11
PR9 PR10 10K_0402_1%
N1 PQ1 68_1206_5% 68_1206_5% 1 2
2
TP0610K-T1-E3_SOT23-3 RTCVREF 2

PR12

2
200_0603_5%
CHGRTCP 1 2 N1 3 1
VS
1

1
PR13 PC8
100K_0402_1% PC7 0.1U_0603_25V7K
0.22U_0603_25V7K
2

PR14
2

22K_0402_1%
1 2
<35> 51ON#
PJ1 PJ2
+3VALWP 2 2 1 1 +3VALW +0.9VP 2 2 1 1 +0.9V
RTCVREF
1

JUMP_43X118 JUMP_43X79
PR15
PU2 200_0603_5%
PR16 PR17 G920AT24U_SOT89-3
560_0603_5% 560_0603_5% 3.3V PJ3 PJ4
2

1 2 1 2 3 2 N2 2 1 +1.8VP 2 1 +1.8V
OUT IN +5VALWP 2 1 +5VALW 2 1
+CHGRTC
1

GND PC10 JUMP_43X118 JUMP_43X118

PC9 1U_0805_25V4Z
10U_0805_10V4Z 1
2

PJ5
3 3

+VSBP 2 2 1 1 +VSB Delete one of PJ6 for 1.8V jumper (0305) EVT
JUMP_43X39

PJ8
PJ7
PQ2 2 1 1 2
+RTCBATT TP0610K-T1-E3_SOT23-3 LL4148_LL34-2 +1.2VALWP 2 1 +1.2VALW +1.5VSP 1 2 +1.5VS
PR18 PR19
PD4
0_0402_5% 470_0402_5% JUMP_43X118 @ JUMP_43X79
3 1 1 2 2 1 1 2 AD_ON
1

PJ10
PD14 PJ9
1

LL4148_LL34-2 +NB_COREP 2 2 1 1 +NB_CORE +VGA_COREP 1 1 2 2 +VGA_CORE

PR20
100K_0402_1%
2

JUMP_43X118 @ JUMP_43X79
2

PQ3
2

TP0610K-T1-E3_SOT23-3
PJ11
<33> AD_ON#
2

1 1 2 2 +2.5VS
PD15 +2.5VSP
2 Delete one VGA jumper (0306) EVT
LL4148_LL34-2
1

PR23 @ JUMP_43X79
1

0_0402_5% PR22
PJ14

hexainf@hotmail.com
GA_ON/OFFBTN# 1 2 100K_0402_1%
3

4 <35> GA_ON/OFFBTN# PJ13 1 2 4

+NB_COREP 1 2 +NB_CORE
+1.1VSP 2 1 +1.1VS
2

2 1
@ JUMP_43X118 @ JUMP_43X79

+3VLP
S5 W/O WOL S5 W WOL S3/S0 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
AD_ON# H L L
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 39 of 49
A B C D
 A B C D

--03/05--OK->add OLB to Library)

--03/09--PJP1 mirror to correct location (update OK)
PH1 under CPU botten side :
CPU thermal protection at 93 degree C
Recovery at 57 degree C
VL
VL
<40,41> VL
VMB

2
PJP2
PL2 PR24
<40,41>

1
1 1

1 SMB3025500YA_2P 47K_0402_1%
1
2 2 BATT_S1 1 2 BATT+ PH1 PC11 ENTRIP2 <42>
3 PI 100K_0603_1%_TH11-4H104FT 0.1U_0603_25V7K PR25

1
3 TH 47K_0402_1%
4 4

1
5 EC_SMCA 1 2

2
5 PC12 PC13 PR26
6 6

8
7 EC_SMDA 1000P_0402_50V7K 0.01U_0402_25V7K 13.7K_0402_1%

2
7

1
PD5 PQ52 D
8 1 2 3

P
8 +
GND 9 O 1 2 1 2
10 TM_REF1 2 G 2N7002W-T/R7_SOT323-3
GND -

G
PU3A LL4148_LL34-2 S

3
SUYIN_200275GR008G13GZR LM393DG_SO8

4
2

0.22U_0603_16V7K
PR27 PR28
1

15.4K_0402_1%
100_0402_1% 100_0402_1%

1
PC14
PR29

1000P_0402_50V7K
PR30
100K_0402_1%
1

PR216 2 1 ENTRIP1 <42>

VL

1
1K_0402_5% PR31
2

PC15
<BOM Structure> @ 6.49K_0402_1%

2
2 1 +3VLP

1
PQ51 D
1

PR32 2
PR33 100K_0402_1% G 2N7002W-T/R7_SOT323-3
1K_0402_1% S

3
2

2 2

BATT_TEMP <33>

EC_SMB_CK1 <33> PH2 near main Battery CONN :

BAT. thermal protection at 79 degree C
EC_SMB_DA1 <33>
Recovery at 47 degree C
VL

2
@ PR34
@PR34
VL 47K_0402_1%
@PR35
@ PR35
47K_0402_1%

1
1 2

1
PQ5
TP0610K-T1-E3_SOT23-3
@PH2
@ PH2
100K_0603_1%_TH11-4H104FT VL

B+ 3 1 +VSBP

2
0.22U_1206_25V7K

0.1U_0603_25V7K

@PR37
@ PR37
1

8
13.7K_0402_1% @PD6
@ PD6
1

1
PC16

PC17

PR36 1 2 5 LL4148_LL34-2

P
100K_0402_1% +
O 7 2 1
@ @ TM_REF1 6
2

G
3 3

PR38 PU3B
2

1
VL 22K_0402_1% LM393DG_SO8

4
1 2 @ PC18
@PC18 @ PR39
@PR39
0.22U_0603_16V7K 15.4K_0402_1%

2
2

PR40
100K_0402_1%

PR41
1

0_0402_5% PQ6 D
1 2 2
<42,44> POK G 2N7002W-T/R7_SOT323-3
0.1U_0402_16V7K

S
3
1

PC19

@
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 40 of 49
A B C D
 A B C D

Iada=0~4.74A(90W/19V=4.736A) B+
ADP_I = 19.9*Iadapter*Rsense CP = 85%*Iada ; CP = 4.07A

PQ7 P2 PQ8 P3
PR42
0.02_2512_1%
B+ CHG_B+ PQ9
AO4407_SO8 AO4407_SO8 PJ15 AO4407_SO8
VIN 8 1 1 8 1 4 2 2 1 1 1 8
7 2 2 7 2 7
6 3 3 6 2 3 JUMP_43X118 CSIN 3 6
5 5 5

10U_1206_25V6M

10U_1206_25V6M

0.1U_0603_25V7K
1 1

5600P_0402_25V7K

2200P_0402_25V7K
CSIP PR44

4
1

1
PC20

PC22
47K_0402_1%

1
PC23
PQ10 TP0610K-T1-E3_SOT23-3 1 2
VIN

PC21

PC24
2

2
1

3 1 DCIN PD7

2
P3

2
PR43 1SS355TE-17_SOD323-2

1
100K_0402_1%
0.1U_0603_25V7K
47K_0402_1% PR47 1 2 ACOFF

1
PR45 PQ11 10K_0402_1%

1
PC25

PR46
200K_0402_1% PDTC115EU_SOT323
2

PR49

1 1
PD8 200K_0402_1%

2
PR48 2 FSTCHG 1 2 VIN
FSTCHG <33>

2
3

PD9 2 1 2 1
47K PQ12 1SS355TE-17_SOD323-2 3 SUSP# PD10
PDTA144EU_SOT323-3 1 2 6251VDD 100K_0402_1% SUSP# <33,35,38,45> PQ13 1SS355TE-17_SOD323-2

2.2U_0603_6.3V6K
2 47K BAS40CW_SOT323-3 PDTC115EU_SOT323 2 1 2

PC26
PR50

3
1
10K_0402_5% wrong Value
2 1 PU4 PC28
<33> FSTCHG
1

0.1U_0603_25V7K
0.1U_0603_25V7K

1
PQ14 1 2 1 24 DCIN 2 1 PQ15D
1

VDD DCIN
1

1
100K_0402_1%

PC29
PDTC115EU_SOT323 PR52 47K_0402_5% PC27 2 PACIN
6251VDD 1 2 0.1U_0402_16V7K 2N7002W-T/R7_SOT323-3
G

PR53
2 PR51 2 23 S

3
ACSET ACPRN

1
150K_0402_1% PR54
PQ17 20_0402_5%
2

2
1

PQ16 D PDTC115EU_SOT323 6251_EN CSON

3 EN CSON 22 1 2

2
2 PC30
3

5
6
7
8
G 2N7002W-T/R7_SOT323-3 2 0.047U_0603_16V7K
<33> 3S/4S#
S 4 21 1 2 CSOP PQ18
3

1
CELLS CSOP PR55 AO4466_SO8
2
PC31 6800P_0402_25V7K 20_0402_5% 2

3 1 2 5 ICOMP CSIN 20 2 1
1

2
PQ19 D PR56 4
PC33 20_0402_5%
2
G 2N7002W-T/R7_SOT323-3 1 2 1 PR57 2 10K_0402_1% 6 19 0.1U_0603_25V7K
1 2
02/26 EVT <40,41>

1
PR59 VCOMP CSIP PR58 PL3
S
3

PC32 1 2 100_0402_1% 2_0402_5% 10UH_PCMB104T-100MS_6A_20% BATT+

3
2
1
ACON 0.01U_0402_25V7K PC34 1 2 7 18 LX_CHG 1 2 CHG 1 4
<45> ACON ICM PHASE

4.7_1206_5%
@ 100P_0402_50V8J

1
<33> ADP_I 2 3

5
6
7
8

PR61
PR62 PC35 6251VREF 8 17 DH_CHG
22K_0402_5% PR63 VREF UGATE PR64 PC36 PQ20 PR60
1 2

10U_1206_25V6M

10U_1206_25V6M
PACIN 1 2 80.6K_0402_1% 2.2_0603_5% 0.1U_0603_25V7K AO4466_SO8 0.02_2512_1%
<39,45> PACIN
2 1 0.1U_0402_16V7K 9 16 BST_CHG 1 2 BST_CHGA 2 1

2
<33> IREF CHLIM BOOT

1
0.01U_0402_25V7K
1

1
PC39

PC40
PQ21 PR66 PD11 4

680P_0402_50V7K
PC37

PDTC115EU_SOT323 PR65 6251VREF 1 2 6251aclim 10 15 6251VDDP RB751V-40TE17_SOD323-2

ACLIM VDDP

PC38
100K_0402_1%
2

2
1
2.37K_0402_1%
PR67
11.5K_0402_1% 20K_0402_1% 1 26251VDD

2
ACOFF 2 PR69 11 14 DL_CHG
<33,45> ACOFF
2

3
2
1
1 VADJ LGATE

2
PR68
4.7_0603_5%
12 13 PC41
2

1
GND PGND 4.7U_0805_6.3V6K
3

2
1

PQ22 D ISL6251AHAZ-T_QSOP24
2
<33> 65W/90W# G 2N7002W-T/R7_SOT323-3
S
3

3
CP mode 3

VMB
Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) <40,41>
where Vaclm=1.502V, Iinput=4.07A PR70
18.2K_0402_1%

1
1 2
<33> CALIBRATE#
2

VS PR71
Part Number is wrong with 18.2K PR72 LI-3S :13.5V----BATT-OVP=1.5012V 340K_0402_1%
CC=0.6~4.48A 31.6K_0402_1%

2
0.01U_0402_25V7K
BATT-OVP=0.1112*VMB
IREF=0.7224*Icharge
1

Per cell=3.5V

PC42

1
IREF=0.43V~3.24V PR73

2
499K_0402_1%

2
8
PR74 PU1B
10K_0402_1% LM358DT_SO8 5

P
+
1 2 7 0
<33> BATT_OVP 6
-

0.01U_0402_25V7K
4

1
PR75

PC43
105K_0402_1%
Charging Voltage
BATT Type CV mode

2
(0x15)

hexainf@hotmail.com
4 4

Normal 3S LI-ON Cells

12600mV 12.60V

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
-
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401728 A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 04, 2009 Sheet 41 of 49
A B C D
 5 4 3 2 1

Frequency different
RT8205C TPS51125
2VREF_51125 300KHZ/375KHZ 245KHZ/305KHZ
OCP calculation method different

0.22U_0603_10V7K
RT8205C TPS51125
D D
Rtrip*Itrip/10 (Rtrip*Itrip/9)-24mV

1
PC44
GND pad need add via to ground

2
Add pull high resistor to +3VLP on pin13

PR76 PR77
13K_0402_1% 30K_0402_1%
1 2 1 2

PR78 PR79
B++
20K_0402_1% 19.1K_0402_1%
B++
1 2 1 2

PJ16 @
B+ 2 2 1 1 +3VLP

ENTRIP2

ENTRIP1
2200P_0402_50V7K

JUMP_43X118 PR80 PR81

10U_1206_25V6M

10U_1206_25V6M
196K_0402_1% 226K_0402_1%
1

2200P_0402_50V7K
PC45

4.7U_0805_10V6K
1 2 1 2

1
PC46

PC49
PC48
2

2
6

5
6
7
8
PC47
PU5

8
7
6
5

1
C C

VREF
ENTRIP2

VFB2

VFB1

ENTRIP1
TONSEL
25 PQ24
PQ23 P PAD AO4466_SO8

2
AO4466_SO8
7 VO2 VO1 24 POK <40,44> 4
4
8 23 PR83 PC51
PR82 VREG3 PGOOD 2.2_0603_1% 0.1U_0402_16V7K
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2 02/27_EVT_change 7_7

3
2
1
2.2_0603_1% VBST2 VBST1
02/27_EVT_ change 7_7
1
2
3

PL4 PC50 UG_3V 10 21 UG_5V PL5

8.2UH_PCMB063T-8R2MS_4.5A_20% 0.1U_0402_16V7K DRVH2 DRVH1 8.2UH_PCMB063T-8R2MS_4.5A_20%
2 1 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP LL2 LL1
1

8
7
6
5

5
6
7
8

1
4.7_1206_5%

680P_0603_50V7K 4.7_1206_5%
LG_3V 12 19 LG_5V
DRVL2 DRVL1
PR84

PR85
SKIPSEL

330U_D2E_6.3VM_R25M
PQ25 PQ26

VREG5

VCLK
330U_D2E_6.3VM_R25M

1 AO4712_SO8 AO4712_SO8

GND
<6,45> MAINPWON 1

EN0

VIN
2

2
+ +
PC52

PC53
4 4
TPS51125RGER_QFN24_4X4

13

14

15

16

17

18
1

1
680P_0603_50V7K

PC55
PR86
2 2
PC54

499K_0402_1%
B+ 1 2
2

1
2
3

3
2
1

2
(ME interference)

1
100K_0402_1%
1 2 VL

1
PR88

PC56
4.7U_0805_10V6K
PC89 PR87 (ME interference)
B 1U_0603_10V6K @ 0_0402_5% B

2
2

2
B++

1
ENTRIP1 <40> ENTRIP2 <40>

0.1U_0603_25V7K
2
PC57
2VREF_51125
1

PQ27D PQ28 D
2 2
+5VALWP Ipeak=7A ; Imax=4.9A;DCR=54m~60m ohm
S
2N7002W-T/R7_SOT323-3
G G
S
2N7002W-T/R7_SOT323-3 C(330U,ESR=25m ohm)
3

Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)

+3.3VALWP Ipeak=5.6A ; Imax=3.92A ; DCR=54m~60m ohm Iocp=13.63~16.18A (Freq=245KHz) (Rtrip=226K)
C (330U,ESR=25m ohm) Note:Poscap (P/N:SGA*)
VL 2 1 Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
PR89 Iocp=11.41~13.58A (Freq=305KHz) (Rtrip=196K)
100K_0402_1%
1

PQ29 D

VS 1 2 2
G 2N7002W-T/R7_SOT323-3
A A
49.9K_0402_1%

0.01U_0402_16V7K

PR90 S
3
1

100K_0402_1%
1
PR91

@ PC58
2

Security Classification Compal Secret Data Compal Electronics, Inc.

2

Issued Date 2007/11/12 Deciphered Date 2008/11/12 Title

SCHEMATICS,MB A5401
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KAQB0
Date: Monday, May 04, 2009 Sheet 42 of 49
5 4 3 2 1
 A B C D

Confirm :UMA (pop-->o/p:adjustable) Discrete(unpop-->o/p:fix)

FB2_NB_COREP
POWER_SEL +5VALW

2
@
PC60 HIGH 1.0V

1
PC59 1U_0402_6.3V6K PR92

1
1U_0402_6.3V6K 12K_0402_1%
LOW 1.1V PR93

1
PR95 PR96 @ 10K_0402_1%
2.2_0603_1% 2.2_0603_1% PR94

1
@ 10K_0402_5% D
+5VALW 2 1 1 2 +5VALW

2
1 1

1 2 2
@ PQ31 G

1
SSM3K7002F_SC59-3 D
S

3
1 2 2 PQ30
<11> POWER_SEL

1
PC63 PC64 PR97 G @ SSM3K7002F_SC59-3
0.1U_0603_25V7K 0.1U_0603_25V7K @ 10K_0402_5% S

3
1
@PC61
@ PC61

2
PC62 0.1U_0402_16V7K
PR98 PR99 0.1U_0402_16V7K

2
10_0603_1% 10_0603_1% @ R*C>1ms
ISL6228_B+ 2 1 2 1 ISL6228_B+
PJ17
JUMP_43X118
2 2 1 1
B+ ISL6228_B+ R*C>1ms

18.2K_0402_1%

2
1000P_0402_50V7K
68U_25V_M_R0.44

1 Avoid ME Interference (03/10)

2
PR100

1
PC65

PR101
+ 22K_0402_1%

1
PC67 PR102 PC66

PC68
1000P_0402_50V7K 3.3K_0402_5% PR103 1000P_0402_50V7K

1
2 22.6K_0402_1%
2 1 1 2

2
1
PR104

1
45.3K_0402_1%
2 1 FB_1.8V-1 29

PGOOD1

FSET1

VIN1

VCC1

VCC2

VIN2

FSET2
GND_T
PR107 PC69

2
PR105 3.3K_0402_5% 1000P_0402_50V7K
22.6K_0402_1% 8 28 PR106 2 1 1 2
2
6228_1.8VO1 FB1 PGOOD2 30K_0402_1% 2
1 2

PR108

1
20K_0402_1%
ISL6228_B+ 9 27 FB2_NB_COREP 1 2 +NB_COREP
VO1 FB2
4.7U_1206_25V6K

4.7U_1206_25V6K

PR109
1

1
PC70

PC71

8.66K_0402_1%
8
7
6
5

PC72 OCSET_1.8V 10 26 6228_1.1VO2 1 2

22P_0402_50V8J OCSET1 VO2
2

1 2 PQ32
AO4466_SO8
Vref=0.6V
2

PR110 4 1.8V_EN 11 25 OCSET_1.1V

11K_0402_1% EN1 PU6 OCSET2

change to big for efficiency ISL6228HRTZ-T_QFN28_4X4 ISL6228_B+

+1.8VP
1

1
2
3

1 2 LX_1.8V 12 24 1.1V_EN
PHASE1 EN2
1

8
7
6
5

4.7U_1206_25V6K

4.7U_1206_25V6K
PL6 PC77

5
6
7
8

1
PC74

PC76
1.8UH_1164AY-1R8N=P3_9.5A_30% PQ33 0.033U_0402_16V7K
D
D
D
D

1 PR112 FDS6670AS_NL_SO8 1 2
4.7_1206_5% UG_1.8V 13 23 LX_1.1V

2
+ PC75 UGATE1 PHASE2
2

2
330U_D2E_2.5VM 4
G PR114 PR113
4
2 0_0603_5% 8.66K_0402_1%
AO4466_SO8
1

S
S
S

PC78 2 1 2 1BST_1.8V14 22 UG_1.1V

680P_0402_50V7K BOOT1 UGATE2 PQ34 +NB_COREP
1
2
3

1
LGATE1

LGATE2
PC79
PGND1

PGND2

BOOT2
PVCC1

PVCC2
2

3
2
1
3 3

0.1U_0402_16V7K 1 2

1
avoid ME interference

5
6
7
8
PR115 PL7

FDS6670AS_NL_SO8
4.7_1206_5% 1UH_PCMB103E-1R0MS_20A_20% 1

D
D
D
D
15

16

17

18

19

20

21

PQ35
+ PC80

2
PR116 PC81 330U_D2E_2.5VM
0_0402_5% 0_0603_5% 0.1U_0402_16V7K 4 G

1
BST_1.1V 1 PC82 2
2 1 +5VALW 2 1 2
<33,38> SYSON 680P_0402_50V7K
+5VALW
2

S
S
S
PR111 1.8V_EN

2
PC83 PC84

3
2
1
2 1 1U_0402_6.3V6K 1U_0402_6.3V6K
1

avoid ME interference
@PC73
@ PC73
0.01U_0402_25V7K
LG_1.8V LG_1.1V

DCR=3.5m ohm /tolerance :20%/(L=1uH )

PR117 C(330U,ESR=15m ohm)
DCR=7.5m ohm /tolerance :30%/(L=1.8uH ) 0_0402_5%
1 2 1.1V_EN 1.8VP Ipeak=11.93A, Imax=8.351A, Iocp=1.2*Ipeak=14.316A
C(330U,ESR=15m ohm) <35,38,44> VLDT_EN Fsw=1/1.5E-10*22k =303K
1.8VP Ipeak=9.023A, Imax=6.316A, Iocp=1.2*Ipeak=10.8276A Vo=Vref*((PR97+PR99)/PR97)
Fsw=1/1.5E-10*18.2k =366K Roset=change to 8.66k ohm (remember)
1

Vo=Vref*((PR97+PR99)/PR97) @PC85
@PC85 Csen=change to 0.033UF=33PF (remember)
Roset=change to 11k ohm (remember) 0.1U_0402_16V7K Iocp=20.619A

hexainf@hotmail.com
2

4
Csen=change to 0.022UF=22PF (remember) 4

Iocp=11.282A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 43 of 49
A B C D
 5 4 3 2 1

PJ18

4.7U_0805_25V6-K

4.7U_0805_25V6-K
JUMP_43X118
51117_B+ 2 2 1 1 B+

2200P_0402_25V7K
PC86

PC87

2
PQ36

PC88
DH_1.2V 8 1
PR118 G2 D2
7 2

1
200K_0402_5% S2/D1 D2 DL_1.2V
6 S2/D1 G1 3
PR119 1 2 5 4
0_0402_5% S2/D1 S1
2 1 AO4932_SO8
<40,42> POK
D D

1
PR120 PC91 2.2UH +-20% FDV0630-2R2M=P3 7.2A

1
0_0603_5% 0.1U_0603_25V7K PL8

15

14
1
@ PC90
@PC90
0.01U_0402_25V7K
PU7 BST_1.2V 1 2BST_1.2V-1 1 2 1 2 +1.2VALWP

EN_PSV

TP

VBST
2
@

2
PR200 2 13 DH_1.2V
100K_0402_5% TON DRVH
3 12 LX_1.2V 1
VOUT LL
VFB=0.75V + PC92
4 V5FILT TRIP 11 +5VALW 330U_D2E_2.5VM
Add pull down resistance 5 10
VFB V5DRV 2
6 9 DL_1.2V
PGOOD DRVL

PGND
PR121

GND

1
10K_0402_1%
300_0603_5%

PR122
1 2 @ PC94
@PC94 PC93
+5VALW 47P_0402_50V8J TPS51117RGYR_QFN14_3.5x3.5 4.7U_0805_10V6K

2
1 2

2
PC95
1U_0603_10V6K

2
PR123
6.34K_0402_1%
1 2

1
+1.2VALW

PR124
C 10K_0402_1% C
+5VALW
2

1
PJ19

1
JUMP_43X79
@

2
PC96

2
1U_0402_6.3V6K

2
PC97

1
4.7U_0805_6.3V6K

6
VFB=0.75V ; Rdson=15.8m ~ 19.6m ohm PU8

2
5

VCNTL
L(2.2U,DCR=21m ohm) ; C(330U,ESR=15 mohm) 7
VIN
POK
Vo=VFB*(1+PR116/PR117)=1.2V VOUT 4 +1.1VSP
Fsw=274.6KHz PR125 3
VOUT

22U_0805_6.3V6M
0_0402_5%

PC98
Ipeak=2.865A, Imax=2.0055A,1.2*Ipeak=3.438A VLDT_EN 1 2 8 2
EN FB

1
<35,38,43> VLDT_EN PR126

GND

2
Delta I=((19-1.2)*(1.2/19))/(L*Fsw)=2.589A

1
@ 9 1.15K_0402_1%
@ PC99
@PC99 PR127 VIN
=>1/2DeltaI=1.2945A

2
1U_0603_10V6K 47K_0402_5% APL5912-KAC-TRL_SO8
Vtrip=Rtrip*10uA=10K*10uA=0.1V

1
2
Iocp=4.938~6.568A PC100

1
0.01U_0402_25V7K

PR128
pull down resistance 3K_0402_1%
B B

2
+1.8V

1
PJ20

1
JUMP_43X79

2
PU9

2
1 VIN VCNTL 6 +3VALW
2 GND NC 5

1
1
PC101 3 7 PC102
4.7U_0603_6.3V6M PR129 REFEN NC 1U_0402_6.3V6K

2
1K_0402_1% 4 8
VOUT NC
9

2
GND
RT9173DPSP_SO8

0.1U_0402_16V7K
PR130 2N7002W-T/R7_SOT323-3
+0.9VP

1
0_0402_5% PQ37 D

PC103
<31,32,38> SYSON# 1 2 2 PR131

1
G 1K_0402_1%

2
1
S PC104

3
10U_0805_6.3V6M

2
A A
2

PC105
0.1U_0402_16V7K

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 44 of 49
5 4 3 2 1
 5 4 3 2 1

PJ21

4.7U_0805_25V6-K

4.7U_0805_25V6-K
JUMP_43X118
1.5V_51117 2 2 1 1 B+

2200P_0402_25V7K
PC110

PC157

2
PQ45

PC160
DH_1.5V 8 1
PR139 G2 D2
7 2

1
300K_0402_5% S2/D1 D2 DL_1.5V
6 S2/D1 G1 3
PR141 1 2 5 4
0_0402_5% S2/D1 S1

D 2 1 AO4932_SO8 D
<33,35,38,41> SUSP#

1
VFB=0.75V ; Rdson=15.8m ~ 19.6m ohm PR215 PC108 2.2UH +-20% FDV0630-2R2M=P3 7.2A

1
0_0603_5% 0.1U_0603_25V7K PL14

15

14
L(2.2U,DCR= 21m ohm); C(330U,ESR=15m ohm)

1
Vo=VFB*(1+PR116/PR117)=1.5V
@
PR207
@ PC158
@PC158
0.01U_0402_25V7K
PU10 BST_1.5V 1 2BST_1.5V-1 1 2 1 2 +1.5VSP

EN_PSV

TP

VBST
2
100K_0402_5%
Fsw=207.756KHz

2
2 13 DH_1.5V
TON DRVH
Ipeak=1A, Imax=0.7A,1.2*Ipeak=1.2A
3 12 LX_1.5V 1
Delta I=((19-1.2)*(1.2/19))/(L*Fsw)=3.0227A VOUT LL
=>1/2DeltaI=1.5113A VFB=0.75V + PC161
Add pull down resistance
4 V5FILT TRIP 11 +5VALW 330U_D2E_2.5VM
Vtrip=Rtrip*10uA=10K*10uA=0.1V 5 10
VFB V5DRV 2
Iocp=5.1556~6.7856A
6 9 DL_1.5V
PGOOD DRVL

PGND
PR213

GND

1
10K_0402_1%
300_0603_5%

PR142
1 2 @ PC109
@PC109 PC159
+5VALW 47P_0402_50V8J TPS51117RGYR_QFN14_3.5x3.5 4.7U_0805_10V6K

2
1 2

2
PC106
1U_0603_10V6K

2
PR214
10K_0402_1%
1 2

1
C C
PR140
10K_0402_1%
N1

2
PU11
APL5508-25DC-TRL_SOT89-3

+3VS 2 3
IN OUT
+2.5VSP

1
8

4.7U_0805_6.3V6K
PC111
PU12B

1
GND
+ 5
P

2
1
7 PC112
O 1U_0402_6.3V6K 1 @ PR145
@PR145
- 6
G

150_1206_5%
B+

2
LM393DG_SO8 PR143
4

2
VL 2.2M_0402_5%
2 1

1
PR144
N1 499K_0402_1%
1

PR146

2
100K_0402_1% PR132
1K_1206_5%
1 2
2

<6,42> MAINPWON PD13 PU12A

B 2 TP0610K-T1-E3_SOT23-3 B
+ 3
P

1 1 PR133 PQ38
O PD12

0.01U_0402_25V7K
<41> ACON VIN 1K_1206_5%
3 - 2
B+
1

1
G

2 1 1 2 3 1
1
1000P_0402_50V7K

32.4

BAS40CW_SOT323-3 LM393DG_SO8 PR147 PC115

4
1

<BOM Structure> 191K_0402_1% PR134

LL4148_LL34-2
PC114

PC113 PR148 1K_1206_5%

2

0.1U_0603_25V7K 1 2
2

PRG++ 2

100K_0402_5%

100K_0402_5%
499K_0402_1%

1
PR136
PR135

PR137
1K_1206_5%

2
1 2

PR149 PR150

2
1

34K_0402_1% PQ41D 47K_0402_5%

2 1 2 2 1
RTCVREF 2N7002W-T/R7_SOT323-3
G PACIN <39,41>
1

S
3

PQ42
1

1
PDTC115EU_SOT323
@ PR151
@PR151 PR138

1
66.5K_0402_1% 2 +5VALW 100K_0402_5%
PQ39
PDTC115EU_SOT323
ACIN
2

1 2
<33,41> ACOFF
Precharge detector 2
3

PQ40
PDTC115EU_SOT323
Min. typ. Max.
H-->L 14.589V 14.84V 15.243V 2

hexainf@hotmail.com
A
L-->H 15.562V 15.97V 16.388V A

3
BATT ONLY
Precharge detector
Min. typ. Max. Security Classification Compal Secret Data Compal Electronics, Inc.
H-->L 6.138V 6.214V 6.359V Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
SCHEMATICS,MB A5401
L-->H 7.196V 7.349V 7.505V THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 45 of 49
5 4 3 2 1
 5 4 3 2 1

VR_ON

<33>
+3VS CPU_VID5 <6>

<6>
PSI_L
CPU_VID4 <6>
(ME interference /change to 6mm)

2
CPU_VID3 <6>

0_0402_5%
PL9
PR152 CPU_VID2 <6> FBMA-L18-453215-900LMA90T_1812
D D
10K_0402_5% CPU_B+ 1 2
CPU_VID1 <6> B+

2200P_0402_50V7K
CPU_VID0 <6>

0_0402_5%

10U_1206_25V6M

10U_1206_25V6M
1

2
<33> VGATE

PR153

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

PC116

PC117

PC118
+ PC119

2
+3VS 68U_25V_M_R0.44

1
1

2.2_0603_1%
VCC_PRM

5
6
7
8
2

PR162
PR154
PC120
0.22U_0603_25V7K 03/03_EVT

1
2

2
10K_0402_5%

10K_0402_5%

PR159

PR160

PR155

PR156

PR157

PR161

2
PQ43

PR158

PR163
R163
UG_CPU1 4

1
AO4466_SO8
@
@P

1
1000P_0402_50V7K

150K_0402_1%
0.047U_0402_16V7K
PL10
+CPU_CORE

2
1000P_0402_50V7K

36.5K_0402_1%
1UH_FDV0630-1R0M-P3_10.3A_20%

3
2
1
2

2
6.81K_0402_1%

4.02K_0402_1%
PHASE_CPU1

40

39

38

37

36

35

34

33

32

31
1 2
2
PC122
C122

PR167

PC123

PR165
2

5
6
7
8
PR166

PR164

BOOT1
PGOOD

PSI_L

VID5

VID4

VID3

VID2

VID1

VID0
VR_ON
1

10K_0402_1%
PC121

@
@P

2
1_0402_5%
PQ44
1

4.7_1206_5%
1 30 AO4456_SO8 PR169
1

SET UGATE1

2
PR171

PR172
3.65K_0805_1%
10K_0402_1%

PR168
2 RBIAS PHASE1 29 4

PR170
PC124

1
3 28 LG_CPU1 0.22U_0603_16V7K

1
OFS PGND1
1 2

1
4 27 PR173 0_0402_5%

3
2
1
SOFT LGATE1

680P_0603_50V8J
2 1 CPU_ISEN2
C +5VS C
PR174 PC125 5 26
OCSET PVCC

PC127
97.6K_0402_1% 470P_0402_50V7K 2 1 CPU_ISEN1 VCC_PRM
1 2 1 2 6 25 PC126
PC128 VW PU13 LGATE2 4.7U_0603_6.3V6K Rs

2
220P_0402_50V8J 7 ISL6264CRZ-T_QFN40_6X6 24
COMP PGND2 VSUM
1 2
8 FB PHASE2 23

9 VDIFF UGATE2 22
PR175
1K_0402_1% 10 21 2 1
VSEN BOOT2 PR176

DROOP
2 1

ISEN2

ISEN1
VSUM
1000P_0402_50V7K

PR177 PC129 41 2.2_0603_1%

GND

VDD
RTN

DFB
GND PAD
2

2
VIN
255_0402_1% 1000P_0402_50V7K CPU_B+

VO
2

1 2 1 2 @PC131
@ PC131
PC130
C130

0.068U_0402_16V7K
1

11

12

13

14

15

16

17

18

19

20

2200P_0402_50V7K
1

10U_1206_25V6M

10U_1206_25V6M
@
@P PC132

2
2 1 0.22U_0603_25V7K
<6> CPU_VCC_SENSE

5
6
7
8

PC134

PC135

PC136
CPU_ISEN1
PR178 PC133

1
1000P_0402_50V7K

PR179 0_0402_5% 180P_0402_50V8J 03/03_EVT

2

10_0402_5% 1 2 CPU_ISEN2
PC137
C137

+CPU_CORE 2 1 PR180 PR181

1K_0402_1% 1.4K_0402_1% 4
1

平行線from output Bulk Cap @

@P 2 1 1 2 +5VS

PR182 PQ46 AO4466_SO8

10_0402_5% B+

3
2
1
10_0402_5%
1 2

2
Close to Phase1 Choke PL11 PL11
+CPU_CORE
10_0603_5%

PR183
B VCC_PRM 1UH_FDV0630-1R0M-P3_10.3A_20% B
2

PHASE_CPU2 1 2
10K_0603_5%_TSM1A103J4302RE

PR185

2 1
<6> CPU_VSS_SENSE
2

5
6
7
8
11K_0402_1%

10K_0402_1%
1
PH3

PR184

2
1_0402_5%
PR186
0.22U_0402_6.3V6K

0_0402_5% PQ47
1
0.022U_0402_16V7K
0.22U_0402_6.3V6K

AO4456_SO8 PR187
2

2
PC138

PR190

PR191
4.7_1206_5%

3.65K_0805_1%
10K_0402_1%
1

1
PC139

PC140

1U_0402_6.3V6K

LG_CPU2 4

PR188

PR189
0.01U_0402_50V7K

PC142
1

1
2

1
PC141
2.61K_0402_1%

0.22U_0603_16V7K
2
PC143

1 2

1
PR192

CPU_ISEN1
2

3
2
1
1

680P_0603_50V8J
1

PC144
CPU_ISEN2 VCC_PRM
One phase :Ipeak=10A ; Imax=6A ; 1.2Ipeak=12A
L(1U, DCR= 10m ohm) VSUM

2
Rdson=4.5m ~ 5.6m ohm Rn VSUM
Rocset=13K ohm // Iocp=12.873A
MLCC*9(22U,6.3V,X5R) ; Poscap*4(330U,ESR=9m ohm)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 46 of 49
5 4 3 2 1
 5 4 3 2 1

5
6
7
8
PQ49
AO4466_SO8
UMA@
4

D D

3
2
1
+3VS

5
6
7
8
PJ22

2
PR194 UMA@ B+_core
JUMP_43X118
2 2
B+
10K_0402_5% PR195 PQ50 1 1
4

1
@ 200K_0402_5% AO4456_SO8 PC145
1 2 4.7U_1206_25V6K UMA@
PR193

2
1 2 EN_PSV change to AO4456 (EVT)
<35> VGA_ON

3
2
1
100K_0402_1% PR196 PC147 PL13

1
UMA@ 2.2_0603_5% 0.1U_0603_25V7K
PC146 1UH_PCMB103E-1R0MS_20A_20% +VGA_COREP

15

14
1
0.1U_0402_16V7K PU14 BST_VCORE 1 2BST_VCORE-1
1 2 1 2

2
UMA@ UMA@

EN_PSV

TP

VBST
UMA@ UMA@
2 13 DH_VCORE
TON DRVH

1
3 12 LX_VCORE
VOUT LL PR197
VFB=0.75V 4.7_1206_5%
4 V5FILT TRIP 11 +5VALW UMA@
1
PC149

2
5 10 + 330U_V_2.5VM_R9M
VFB V5DRV UMA@
C 6 9 DL_VCORE DL_VCORE C
PGOOD DRVL

1
PGND
PR206 UMA@ 2

GND

1
7.5K_0402_1%
300_0402_5% PC148
680P_0402_50V7K

PR198
1 2 @ PC151 PC150
+5VALW

2
47P_0402_50V8J TPS51117RGYR_QFN14_3.5x3.5 4.7U_0805_10V6K UMA@

2
1 2 UMA@ UMA@

1
VFB=0.75V ; Rdson=4.6m ~ 5.6m ohm

2
UMA@ PC153
L(1U,DCR= 2.7~3.0m ohm); C(330 U,ESR= 9m ohm) 1U_0603_10V6K 2 UMA@
Vo=VFB*(1+PR116/PR117)=0.95V
Fsw=254.237KHz
PR199
UMA@
Ipeak=6.52A, Imax=4.564A,1.2*Ipeak=7.824A 2 1 +VGA_COREP
Delta I=((19-1.2)*(1.2/19))/(L*Fsw)=4.8735A 2K_0402_1% 02/27_EVT (high:0.95/low:0.9)
=>1/2DeltaI=2.4367A
Vtrip=Rtrip*10uA=7.5K*10uA=0.075V
Iocp=12.0031~16.0237A VFB=0.75Volt VFB

2
UMA@ 1.Remember to change input cap from 4.7U*1 to 10U*2
30K_0402_1%
M92-M2 XT PR202 2.change one of the input cap from 4.7U*1 to 10U*1

1
+3VS 3.C-test --> change to input cap 10U*1 -->10U*2
1

VGA_PWRSEL Core Voltage Level

2
B 2N7002W-T/R7_SOT323-3 B
UMA@ PR201
0 0.95V PQ48 UMA@ PR208 UMA@ PR210 UMA@
1
10K_0402_1% D 10K_0402_1% 10K_0402_5%
2

2 1 2

1
1 0.9V G

2
S
3

1
@ PR209
UMA@ 10K_0402_1%
PC175

2
02/27_EVT (high:0.95/low:0.9) 0.1U_0402_16V7K

1
+3VS

2
BOM control (R*C>1ms) (03/12) PR204 UMA@
PR203 10K_0402_5%

1
D
10K_0402_1%
VGA_PWRSEL <15>

1
PQ53 2 1 2
UMA@ G VGA_PWRSEL
S UMA@

2
2N7002W-T/R7_SOT323-3 PR205 @
10K_0402_1%

1
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/12/18 Deciphered Date 2008/12/18 Title

SCHEMATICS,MB A5401

hexainf@hotmail.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401728 A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 04, 2009 Sheet 47 of 49
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 2

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
0.1 50 ADD PC107, PC105, PR121, PR123, PR122, PR102, PQ25, 2009/01/04 DVT
D 1 ADD circuit Switch NB_core voltage PQ28 at UMA Sku D

Switch NB_core voltage 0.1 51 ADD PC110, PC111, PC108, PC109, PC1113, PR1128, 2009/01/04
2 ADD circuit PR194, PR129, PR127 at UMA Sku DVT

EMI requestmrnt 0.1 50 Add PR104 4.7 ohm and PC83 680p 2009/01/04 DVT
3 ADD snubber

EMI requestmrnt 0.1 50 Add PR108 4.7 ohm and PC89 680p 2009/01/04
4 ADD snubber DVT

EMI requestmrnt 0.1 53 Add PR229 2.2 ohm 2009/01/04 DVT

5 ADD CPU boot

EMI requestmrnt 0.1 53 Add PR243 2.2 ohm 2009/01/04 DVT

6 ADD CPU boot

Change resistance value Switch NB_core voltage 0.1 50 Change PR95 from 51 Kohm to 39.2 Kohm 2009/01/04 DVT
7
Change resistance value Switch NB_core voltage 0.1 50 Change PR122 from 12 Kohm to 226 Kohm 2009/01/04 DVT
8
C C
Change resistance value soft start of Switch NB_core voltage 0.1 50 Change PR123 from 0 ohm to 10 Kohm 2009/01/04 DVT
9
Change capacitor value soft start of Switch NB_core voltage 0.1 50 Change PC105 from 0.01 uF to o.1 uF 2009/01/04 DVT
10
Change IC part number Change IC part number 0.1 48 Change PU4 part number to SA00002V400 2009/01/04 DVT
11

12

13

14

15
B B

16

17

18

19

20

21

22
A A

23

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401728
Date: Monday, May 04, 2009 Sheet 48 of 49
5 4 3 2 1
 5 4 3 2 1

PHASE PAGE Modification list PURPOSE

PVT P.29 Delete Q24 and modify ODD power circuit Modify ODD power circuit to follow up SUSP#
P.36 Change L94~L97 to bead , delete C1184/C1193 Follow Realtek suggest
P.37 Change SPDIF detec power +5VAMP to +5VS
C45、C466 Change to 10U
D
P.33 Add R566、R567 for e-machine D

4/20 Add H34 For FAN

4/21 Add LAN_DET function For FAN
IO/B PLT_RST# change to JP21 For ESD
4/22 Add R212 For VRAM ID
Update USB footprint -FOX_UB511AC-RABA7-7F_4P-T
C536 Change to 220U
4/23 Add C39、C41、C778、C780 For ESD
4/24 Change Lid SW power to +3VL

C C

B
For Discrete B

For E-Machine ZZZ

CRT HDMI PCB
2 1 2 1 disable side port
R285 VGA@ 150_0402_1% R141 VGA@ 499_0402_1% 2 1
R281 HM@ 3K_0402_5%
2 1
R137 VGA@ 499_0402_1% 1 2 PCB 06F LA-5401P REV0 M/B
2 1 R223 HM@ 0_0402_5%
R54 VGA@ 2.2K_0402_5% LA5401P MB Rev0: DA80000ET00
2 1 2 1 LA5401P MB Rev1: DA80000ET10
R46 VGA@ 2.2K_0402_5% R149 VGA@ 499_0402_1% 2 1
R406 HM@ 0_0603_5% LA5401P MB with Sub/B Rev1: DAZ~
2 1
R145 VGA@ 499_0402_1%

C633 C640 C662

1 1 1 2 1
R155 VGA@ 499_0402_1%
2
VGA@ VGA@ 2 VGA@ 2
3.3P_0402_50V8J 2 1
A 3.3P_0402_50V8J 3.3P_0402_50V8J R152 VGA@ 499_0402_1% A

C667 C660 C639

1 1 1 2 1 Security Classification Compal Secret Data Compal Electronics, Inc.
R158 VGA@ 499_0402_1% 2008/10/06 2009/10/06 Title
VGA@
2 VGA@2 VGA@2
Issued Date Deciphered Date
8P_0402_50V8J 2 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A5401
8P_0402_50V8J 8P_0402_50V8J R157 VGA@ 499_0402_1% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
401728

hexainf@hotmail.com
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 04, 2009 Sheet 49 of 49
5 4 3 2 1