Mosaic Schematics Document uFCBGA/uFCPGA Northwood: Title

A B C D E
1 1

2 2
Mosaic Schematics Document

uFCBGA/uFCPGA Northwood

2001-09-19
3 3
REV: 0.1

4 4

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
0.1
Date: Wednesday, September 19, 2001 Sheet 1 of 37

A B C D E
A B C D E
Compal confidential Block Diagram

Model Name :ADY13(Mosaic)
File Name : LA-1271
.%$$

!
-/ $

8"
1
page 6

1
page 4,5

,;/ page 5 page 14
page 7 $$
page 7

.$/$

/
.
(-

'""(*
page 15

page 11,12

63;
8
page 8,9

page 15

2 2

:
%

page 27
0

IDSEL:AD20
page 30
IDSEL:AD17
(PIRQA#,GNT#3,REQ#3)
(PIRQA/B#,GNT#2,REQ#2)
<37
AC-LINK
"

page 25

0)0+39
)56+73 page 16,17
page 20 page 21
3
(<;
page 20

9
page 22

"&

'""(()*
+,

-+,99
3

page 19 page 23

!))## 4
($(-

page 30

14M_5V page 26 page 24
""# page 28 ) )

$% page 27 page 27
-

page 31 page 27
&)## 12" ""

page 29 page 19

!
4 4
page 29
""
page ) 3

32,33,34,35,36,37 page 28 page 27

Title
0.1

A B C D E
5 4 3 2 1
Power Managment table

Model
+3VS
Function Mosaic Midas
Signal +5VS CHIPS Rev CHIPS Rev
+3VALW +3V +1.8VS RG82845 FW82801CAM
D FDD YES YES +5VALW +5V +1.5VS SST-Build A3(QC45) B1(QC42) D
State +1.8VALW +2.5V +1.2VP

PS/2 YES YES +12VALW +CPU_CORE
+1.25V
Serial port NO NO
ON ON ON
S0
Parallel port YES YES
S1 ON ON ON
RJ45 YES YES

S3 ON ON OFF

OZ6912/TPS2211 YES YES
S5 S4/AC ON OFF OFF
3Com Lan YES YES
chipset(3C920)
S/W S5 S4/AC don't exist

disable OFF OFF OFF
C C
Note1:
"@" means all model depop
Note2:

Removed serial port,because add 2nd Fan

B
B

A A
Compal Electronics, Inc.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL Note & Revision
ADY13 LA-1271 0.1
5 4 3 2 1
A B C D E
1 1
+CPU_CORE
AC10
AC12
AC14
AC16
AC18
AD11
AD13
AD15
AD17
AD19
AA10
AA12
AA14
AA16
AA18
AB11
AB13
AB15
AB17
AB19
AE10
AE12
AE14
AE16
AE18
AE20
AF11
AF13
AF15
AF17
AF19
AF21
AC8
AD7
AD9
AA8
AB7
AB9
AE6
AE8
AF2
AF5
AF7
AF9
C10
C12
C14
C16
C18
C20
D11
D13
D15
D17
D19
A10
A12
A14
A16
A18
A20
B11
B13
B15
B17
B19
E10
C8
D7
D9
A8
B7
B9
HA#[3..31] U4A HD#[0..63]
<8> HA#[3..31] HD#[0..63] <8>
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
HA#3 K2 B21 HD#0
HA#4 A#3 D#0 HD#1
K4 B22
HA#5 A#4 D#1 HD#2
L6 A23
A#5 D#2
HA#6 K1 A25 HD#3

HA#7 A#6 D#3 HD#4
L3 C21
HA#8 A#7 D#4 HD#5
M6 D22
HA#9 A#8 D#5 HD#6
L2 B24
HA#10 A#9 D#6 HD#7
M3 C23
HA#11 A#10 D#7 HD#8
M4 C24
A#11 D#8

HA#12 N1 B25 HD#9
HA#13 A#12 D#9 HD#10
M1 G22
HA#14 A#13 D#10 HD#11
N2 H21
HA#15 A#14 D#11 HD#12
N4 C26
HA#16 A#15 D#12 HD#13
N5 D23
HA#17 A#16 D#13 HD#14
T1 J21
HA#18 A#17 D#14 HD#15
R2 D25
HA#19 A#18 D#15 HD#16
P3 H22

HA#20 A#19 D#16 HD#17
P4 E24
HA#21 A#20 D#17 HD#18
R3 G23
2 HA#22 A#21 D#18 HD#19 2
T2 F23
HA#23 A#22 D#19 HD#20
U1 F24
HA#24 A#23 D#20 HD#21
P6 E25
HA#25 A#24 D#21 HD#22
U3 F26
HA#26 A#25 D#22 HD#23
T4 D26
HA#27 A#26 D#23 HD#24
V2 L21
HA#28 A#27 D#24 HD#25

R6 G26
HA#29 A#28 D#25 HD#26
W1 H24
HA#30
HA#31
T5
U4
V3
A#29
A#30
A#31
Mobile D#26
D#27
D#28
M21
L22
J24
HD#27
HD#28
HD#29
A#32 D#29 HD#30
W2 K23
A#33 D#30 HD#31
Y1 H25
A#34 D#31 HD#32
AB1 M23
<8> HREQ#[0..4]
HREQ#[0..4]
HREQ#0 J1
A#35
NorthWood D#32
D#33
D#34
N22
P21
M24
HD#33
HD#34
HD#35
HREQ#1 REQ#0 D#35 HD#36
K5 N23
J4 M26
J3 N26
H3 N25

REQ#4 D#39 HD#40
<8> HADS# G1 R21
ADS# D#40 HD#41
P24
D#41 HD#42
R25
D#42 HD#43
AC1 R24
+CPU_CORE AP#0 D#43 HD#44
V5 T26
R98 10K_0402 AP#1 D#44 HD#45
AA3 T25
BINIT# D#45 HD#46
1 2 AC3 T22
3
<8> HBR0#
<8> HBPRI#
<8> HBNR#
<8> HLOCK#
1 2 R31 51.1_1%
H6
D2
G2
G4
IERR#
BR0#
BPRI#
BNR#
LOCK#
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
T23
U26
U24
U23
V25
U21
V22
V24
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
3

CLK_HCLK AF22 W26 HD#55
<14> CLK_HCLK BCLK0 D#55
CLK_HCLK# AF23 Y26 HD#56
<14> CLK_HCLK# BCLK1 D#56
W25 HD#57
D#57 HD#58
Y23
D#58 HD#59
Y24
D#59 HD#60
<8> HIT# F3 Y21
HIT# D#60 HD#61
<8> HITM# E3 AA25
HITM# D#61 HD#62
<8> HDEFER# E2 AA22

DEFER# D#62 HD#63

AA24
D#63
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_80
VCC_79
VCC_78
VCC_77
VCC_76
VCC_75
VCC_74
A24 VSS_10
A26 VSS_11
A3 VSS_12
A9 VSS_13
AA1 VSS_14
AA11 VSS_15
AA13 VSS_16
AA15 VSS_17
AA17 VSS_18
AA19 VSS_19
AA23 VSS_20
AA26 VSS_21
AA4 VSS_22
AA7 VSS_23
AA9 VSS_24
AB10 VSS_25
AB12 VSS_26
AB14 VSS_27
AB16 VSS_28
AB18 VSS_29
AB20 VSS_30
AB21 VSS_31
AB24 VSS_32
AB3 VSS_33
AB6 VSS_34
AB8 VSS_35
AC11VSS_36
AC13VSS_37
AC15VSS_38
AC17VSS_39
AC19VSS_40
AC2 VSS_41
AC22VSS_42
AC25VSS_43
AC5 VSS_44
AC7 VSS_45
AC9 VSS_46
AD1 VSS_47
AD10VSS_48
AD12VSS_49
AD14VSS_50
AD16VSS_51
AD18VSS_52
AD21VSS_53
AD23VSS_54
AD4 VSS_55
AD8 VSS_56
H1 VSS_0
H4 VSS_1
H23 VSS_2
H26 VSS_3
A11 VSS_4
A13 VSS_5
A15 VSS_6
A17 VSS_7
A19 VSS_8
A21 VSS_9
E20
E18
E16
E14
E12
F13
F15
F17
F19
F11
E8
F9
NorthWood
+CPU_CORE
4 4

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL !
0.1
Date: Monday, September 10, 2001 Sheet 4 of 37

A B C D E
A B C D E
+CPU_CORE
AE11
AE13
AE15
AE17
AE19
AE22
AE24
AE26
AF10
AF12
AF14
AF16
AF18
AF20
AF26
R102 200_0402
AE7
AE9
AF1
AF6
AF8
C11
C13
C15
C17
C19
C22
C25
D10
D12
D14
D16
D18
D20
D21
D24
B10
B12
B14
B16
B18
B20
B23
B26
E11
E13
E15
E17
E19
E23
E26
F10
F12
F14
F16
F18
F22
F25
C2
C5
C7
C9
D3
D6
D8
H_A20M#
B4
B8
E1
E4
E7
E9
F2
F5
2 1
U4B
R100 200_0402
2 1 H_SMI#
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
SKTOCC#
R104 200_0402
2 1 H_IGNNE#
R117 200_0402
2 1 H_STPCLK#
R83 200_0402 <8> H_RS#0 F1 J26
H_DPSLP# RS#0 DP#0
2 1 <8> H_RS#1 G5 K25
RS#1 DP#1
R103 200_0402 <8> H_RS#2 F4 K26
H_NMI RS#2 DP#2 +H_GTLREF1
2 1 AB2 L25
1 RSP# DP#3 1
R95 200_0402 <8> H_TRDY# J6
H_INIT# TRDY#
2 1
R110 200_0402 GTLREF0
AA21 All of these pin
2 1 H_INTR H_A20M# C6 AA6
<16> H_A20M#
H_F_FERR# A20M# GTLREF1 connected inside
<16> H_F_FERR# B6 F20
H_IGNNE# FERR# GTLREF2
R97 56_0402 <16> H_IGNNE# B2 F6
H_F_FERR# H_SMI# IGNNE# GTLREF3 +CPU_CORE
2 1 <16> H_SMI# B5 A22
H_PWRGD SMI# NC1
R89 300_0402 <16> H_PWRGD AB23 A7
H_PWRGD H_STPCLK# PWRGOOD NC2
2 1 <16> H_STPCLK# Y4
H_DPSLP# STPCLK#
<16> H_DPSLP# AD25
51.1_1% H_INTR DPSLP# TESTTHI0_1 R18
R85 <16> H_INTR D1 AD24 1 2 1K_0402
H_RESET# H_NMI LINT0 TESTHI0
2 1 <16> H_NMI E5 AA2
H_INIT# LINT1 TESTHI1 TESTTHI2_7 R19
<16> H_INIT# W5 AC21 1 2 1K_0402
H_RESET# INIT# TESTHI2
R96 200_0402 <8> H_RESET# AB25 AC20
PM_CPUPERF# RESET# TESTHI3
2 1 AC24
TESTHI4
AC23
TESTHI5
<8> H_DBSY# H5 AA20

DBSY# TESTHI6
Place resistor <100mils from <8> H_DRDY# H2
DRDY# TESTHI7
AB22
CPU pin AD6 U6 TESTTHI8_10 R32 1 2 1K_0402
<14> H_BSEL0 BSEL0 TESTHI8
<14> H_BSEL1 AD5 W4
BSEL1 TESTHI9
Y3
Mobile TESTHI10
GHI#
A6 PM_CPUPERF# <16>

H_THERMDA B3 H_DSTBN#[0..3]
+1.2VP THERMDA H_DSTBN#[0..3] <8>
H_THERMDC C4
THERMDC H_DSTBN#0
E22
H_THERMTRIP# DSTBN#0 H_DSTBN#1
1 2 A2 K22
R113 56_0402 THERMTRIP# DSTBN#1 H_DSTBN#2
R22
AC6
AB5
BPM#0
NorthWood DSTBN#2
DSTBN#3
W22 H_DSTBN#3
H_DSTBP#[0..3]
H_DSTBP#[0..3] <8>

ITP_BPM0 BPM#1 H_DSTBP#0
AC4 F21
ITP_BPM1 BPM#2 DSTBP#0 H_DSTBP#1
Y6 J23
2 ITP_PRDY# BPM#3 DSTBP#1 H_DSTBP#2 2
AA5 P23
ITP_PREQ# BPM#4 DSTBP#2 H_DSTBP#3
AB4 W23
BPM#5 DSTBP#3
ITP_TCK D4 L5
TCK ADSTB#0 H_ADSTB#0 <8>
ITP_TDI C1 R5
TDI ADSTB#1 H_ADSTB#1 <8>

D5
+1.2VP ITP_TMS TDO H_DBI#[0..3]
F7 H_DBI#[0..3] <8>
Murata LQG21F4R7N00 ITP_TRST# TMS H_DBI#0
E6 E21
TRST# DBI#0 H_DBI#1
G25
L17 4.7UH_80mA DBI#1 H_DBI#2
P26
H_VCCA DBI#2 H_DBI#3
1 2 AD20 V21
4.7UH_80mA TP2 VCCA DBI#3 +CPU_CORE
L16 1 A5
H_VCCIOPLL AE23 VCCSENSE
1 2 AE25 ITP_DBR# <7>
VCCIOPLL DBR#
AF25 R108 56_0402
NC7 H_PROCHOT#
AF3 C3 1 2
1
NC8 PROCHOT#
V6
C22 C36 MCERR# H_SLP#
If used ITP port must depop + +
SLP#
AB26 H_SLP# <16>
33UF_D2_16V 33UF_D2_16V
AC26 2 1

ITP_CLK0 +CPU_CORE
RP23 8P4R_1.5K
2
AD26 AD22 H_VSSA

ITP_TDI H_VSSA ITP_CLK1 VSSA R84 200_0402
1 8 A4 1
ITP_TMS VSSSENSE
2 7 L24
ITP_TRST# COMP0 TP3
3 6 P1
ITP_TCK COMP1
4 5 AD2
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
2
NC3
AF4 VCCVID
AD3
R86 R116 NC4

VID0
VID1
VID2
VID3
VID4
<14> CLK_ITPP
AE21 NC5
AF24 NC6
<14> CLK_ITPP#
W21
W24
+CPU_CORE
M22
M25
G21
G24
AE5
AE4
AE3
AE2
AE1
N21
N24
R23
R26
U22
U25
K21
K24
P22
P25
V23
V26
Y22
Y25
T21
T24
51.1_1% 51.1_1%
L23
L26
J22
J25
W3
W6
M2
M5
G3
G6
N3
N6
R1
R4
U2
U5
K3
K6
P2
P5
V1
V4
Y2
Y5
T3
T6
F8
L1
L4
J2
J5
1
NorthWood
3 R107 51.1_1% 3
2 1 ITP_PREQ# +1.2VP
2 1 ITP_PRDY#

R111 51.1_1%
C226
R105 51.1_1% CPU_VR_VID4 <6>
2 1 ITP_BPM0 CPU_VR_VID3 <6> .1UF_0402
<8,15,16,20,21,26,27,28> PCIRST#
2 1 ITP_BPM1 CPU_VR_VID2 <6>
CPU_VR_VID1 <6>
2
G
R106 51.1_1% CPU_VR_VID0 <6>

+5VALW 1 3
<33,35> SHDN#
W=15mil
S
+5VALW
+VL
Q13
GTL Reference Voltage
2
@2N7002
Thermal Sensor
2
2
C229 R124 +CPU_CORE Layout note :
2
MAX6654MEE 10K_0402
R337
2
.1UF_0402 R119
1. Place R_A and R_B near CPU.
2
1
2. Place decoupling cap 220PF near CPU.(Within 1K_0402 R382

1
1
300_0402 R118
500mils) 470_0402
1
R82
U12 470_0402 <29> PROCHOT#
1
R_A
49.9_1% 1 Q39
1
1 16
NC NC
1 Q14
1
2 15 2
VCC STBY
1
H_THERMDA Trace width>=7mila

2
3 14 SMB_EC_CK1 <7,15,28,29,33> 2 3
C231 H_THERMDC DXP SMBCLK
4 13 +H_GTLREF1 3
2200PF DXN NC 3904
5 12 SMB_EC_DA1 <7,15,28,29,33>
NC SMBDATA
1
1 Q41 R114
2
6 11 R79 3904
ADD1 ALERT THRM# <29>
7 10 C165 C175 1 Q11 R115 2 1 2 H_PROCHOT#
4 GND ADD0 100_1% H_THERMTRIP# 4
8
GND NC
9 R_B 2 1 2 3
R126 1K_0402 1UF 220PF 3 470_0402
2 1 MAX6654MEE 470_0402 3904
+5VALW
2
3904
2
R127 R125
10K_0402
1K_0402

1
Address:1001_110X Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL !"#$%$
+5VALW DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
0.1

A B C D E
A B C D E
Layout note : Layout note :

Place close to CPU, Use 2~3 vias per PAD. Place close to CPU power and
Place .22uF caps underneath balls on solder side. ground pin as possible
Place 10uF caps on the peripheral near balls.
Use 2~3 vias per PAD. (<1inch)
Please place these cap in the socket cavity area

1 1
+CPU_CORE
Used ESR 25m ohm cap total ESR=2.5m ohm
+CPU_CORE
1
1
1
+ C177 + C223 + C164 + C190 + C193
C181 C198 C183 C182 C199 220UF_D2_4V_25m @220UF_D2_4V_25m 220UF_D2_4V_25m 220UF_D2_4V_25m 220UF_D2_4V_25m
10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R
2
2
+CPU_CORE +CPU_CORE
1
C185 C201 C200 C184 C202 + C172 + C206 + C56 + C222 + C166
10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 220UF_D2_4V_25m 220UF_D2_4V_25m 220UF_D2_4V_25m @220UF_D2_4V_25m 220UF_D2_4V_25m
2
2

Please place these cap on the socket north side
+CPU_CORE +CPU_CORE

1
1
C21 C23 C30 C37 C17 C31 C32 C33 C34 C35 C45 C46 C47 C48 C49
2 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R .22UF_X7R .22UF_X7R .22UF_X7R .22UF_X7R .22UF_X7R .22UF_X7R .22UF_X7R .22UF_X7R .22UF_X7R .22UF_X7R 2
2
2
+CPU_CORE

1
C59 C67 C77 C210 C214

10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R
2
+CPU_CORE
CPU Voltage ID R42 0_0402

1 2
1

C174 C180 C192 C203
10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R +3VS RP3
2
1 8
2 7
3 6
1
2
3
4
4 5
Please place these cap on the socket south side R43 RP4
+CPU_CORE 10K_0402 8P4R_10K
U5
8P4R_0
8
7
6
5
3 3 2 CPU_VID0 3
<5> CPU_VR_VID0 A0 C0 CPU_VID0 <32>
7 6 CPU_VID1
1
11 10 CPU_VID2
C170 C173 C178 C186 C191 17 16 CPU_VID3

10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 21 20 CPU_VID4
2
<17> AC_VID0 4 5
B0 D0
<17> AC_VID1 8 9
B1 D1
<17> AC_VID2 14 15
+CPU_CORE B2 D2
<17> AC_VID3 18 19
B3 D3 +5VS
<17> AC_VID4 22 23
B4 D4

PM_GMUXSEL = 0 : for low Voltage A-C 1 24

1
BE# VCC
1 : for high Voltage B-C
1
C195 C204 C209 C212 C179 13 12 C95
<16,32> PM_DPRSLPVR BX GND
10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R @.01UF_0402
2
@SN74CBT3383
2
+CPU_CORE
1
C187 C197 C205 C213

10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R
2
4 4
EMI Clip PAD for CPU

PAD2 PAD6 PAD20
1 1 1

PAD-2.5X3 PAD-2.5X3 PAD-2.5X3 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL &'($$" &)*
0.1

A B C D E
5 4 3 2 1
+3VS
D D
R208
240
U23C
<5> ITP_DBR# 9
8 1 2 PM_PWROK <16>
10 R195 5.6K_0402
<30> ITP_PWROK
74HCT08
R190
+5VS POWER 10K_0402

R199 @0_0402
1 2 +5VALW
EC_HPOWON <28>
R194 100_0402

1
C C547 C
.1UF_0402
2
U9
<5,15,28,29,33> SMB_EC_DA1 1 SDA VCC 8
<5,15,28,29,33> SMB_EC_CK1 2 SCL A0 7
3 6 R94 1K_0402

OS# A1
4 GND A2 5 1 2
LM75CIMMX-5
Address:1001_000X

Fan1 Control circuit Fan2 Control circuit
+12VALW +12VALW

2
2
B B
R169 R8
3.48K_1% Q20 +5VALW 3.48K_1% Q9 +5VALW
1
1
FMMT619 1 FMMT619 1
D15 D8
1
1
2 2

3 1SS355 3 1SS355
2
2
D14 D3
2
2
1N4148 +5VFAN 1N4148 +5VFAN2
2
2
C348 C15
2.2UF_16V_0805 JP16 2.2UF_16V_0805 JP20
1
1
1
1

D13 C131 1 D9 C160 1

3 2 3 2
2 Q19 2 Q3
<28> EN_DFAN 3 <28> EN_DFAN2 3
1 2SA1036K 1N4148 @1000PF_0402 1 2SA1036K 1N4148 @1000PF_0402
53398-0310 53398-0310
2
2
+3V +3V
1
1
R346 R77
10K_0402 10K_0402
2
2
FAN1_TACH <28> FAN2_TACH <28>
A A
COMPAL Electronics,Inc
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL LM75 Thermal sensor & Fan control
ADY13 LA-1271 0.1
5 4 3 2 1
A B C D E
HD#[0..63]
HD#[0..63] <4>
HA#[3..31]
<4> HA#[3..31]
U10A AGP_AD[0..31] U10B HUB_PD[0..10]
<15> AGP_AD[0..31] HUB_PD[0..10] <16>
HA#3 T4 AA2 HD#0 AGP_AD0 R27 P25 HUB_PD0
HA#4 HA#3 HD#0 HD#1 AGP_AD1 G_AD0 HI_0 HUB_PD1
T5 AB5 R28 P24
T3 AA5 T25 N27
U3 AB3 R25 P23
R3 AB4 T26 M26
1 HA#8 HA#7 HD#4 HD#5 AGP_AD5 G_AD4 HI_4 HUB_PD5 1
P7 AC5 T27 M25
R2 AA3 U27 L28
P4 AA6 U28 L27
HA#10 HD#7 G_AD7 HI_7
HUB
HA#11 R6 AE3 HD#8 AGP_AD8 V26 M27 HUB_PD8
P5 AB7 V27 N28
P3 AD7 T23 M24
HA#14 HA#13 HD#10 HD#11 AGP_AD11 G_AD10 HI_10
N2 AC7 U23
HA#15 HA#14 HD#11 HD#12 AGP_AD12 G_AD11
N7 AC6 T24
N3 AC3 U24 N25 HUB_PSTRB <16>
HA#17 HA#16 HD#13 HD#14 AGP_AD14 G_AD13 HI_STB
K4 AC8 U25 N24 HUB_PSTRB# <16>
HA#18 HA#17 HD#14 HD#15 AGP_AD15 G_AD14 HI_STB# +1.8VS +VS_HUBREF
M4 AE2 V24
M3 AG5 Y27 36.5_1%
HA#20 HA#19 HD#16 HD#17 AGP_AD17 G_AD16 HLRCOMP R36
L3 AG2 Y26 P27 1 2
HA#21 HA#20 HD#17 HD#18 AGP_AD18 G_AD17 HLRCOMP
L5 AE8 AA28 P26
HA#22 HA#21 HD#18 HD#19 AGP_AD19 G_AD18 HI_REF
K3 AF6 AB25
HA#22 HD#19 G_AD19
1
HA#23 J2 AH2 HD#20 AGP_AD20 AB27 C57
HA#23 HD#20 G_AD20
Layout note : HA#24 M5 AF3 HD#21 AGP_AD21 AA27 AGP_SBA[0..7] .01UF_0402

HA#24 HD#21 G_AD21 AGP_SBA[0..7] <15>
HA#25 J3 AG3 HD#22 AGP_AD22 AB26
HA#26 HA#25 HD#22 HD#23 AGP_AD23 G_AD22 AGP_SBA0
2
Place this resistor L2
HA#26 HD#23
AE5 Y23
G_AD23 SBA0
AH28
HA#27 H4 AH7 HD#24 AGP_AD24 AB23 AH27 AGP_SBA1 Place this cap near MCH
closely ball AE17 HA#28 HA#27 HD#24 HD#25 AGP_AD25 G_AD24 SBA1 AGP_SBA2
N5
HA#28 HD#25
AH3 AA24
G_AD25 SBA2
AG28 Place closely
HA#29 G2 AF4 HD#26 AGP_AD26 AA25 AG27 AGP_SBA3 +AGPREF
HA#29 HD#26 G_AD26 SBA3 ball P26

HA#30 M6 AG8 HD#27 AGP_AD27 AB24 AE28 AGP_SBA4
HA#31 HA#30 HD#27 HD#28 AGP_AD28 G_AD27 SBA4 AGP_SBA5
L7 AG7 AC25 AE27
HA#31 HD#28 HD#29 AGP_AD29 G_AD28 SBA5 AGP_SBA6
AG6 AC24 AE24
HD#29 G_AD29 SBA6
1
R5 AF8 HD#30 AGP_AD30 AC22 AE25 AGP_SBA7 C39 Place closely pin P22
<5> H_ADSTB#0 HADSTB#0 HD#30 G_AD30 SBA7
AGP
N6 AH5 HD#31 AGP_AD31 AD24 .1UF_0402
<5> H_ADSTB#1 R10 @0_0402 HADSTB#1 HD#31 HD#32 G_AD31
AC11
HD#32 HD#33
2
2 1 AC12 CLK_AGP_MCH
HD#33 <15> AGP_C/BE#[0..3]
AE17 AE9 HD#34 AGP_C/BE#0 V25 AA21

<5> H_RESET# CPURST# HD#34 G_C/BE#0 AGPREF
2
U7 AC9 HD#35 AGP_C/BE#1 V23 R23
<5> H_TRDY# HTRDY# HD#35 G_C/BE#1
HOST
Y4 AE10 HD#36 AGP_C/BE#2 Y25 AD25 2 1 36.5_1% R33
2 <4> HDEFER# DEFER# HD#36 G_C/BE#2 GRCOMP 2
Y7 AD9 HD#37 AGP_C/BE#3 AA23 @33_0402
<4> HBPRI# BPRI# HD#37 G_C/BE#3
W5 AG9 HD#38 P22 CLK_AGP_MCH
<4> HLOCK# HLOCK# HD#38 66IN CLK_AGP_MCH <14>
J27 AC10 HD#39
<5,15,16,20,21,26,27,28> PCIRST# RSTIN# HD#39 HD#40
1
H26 AE12 <15> AGP_ST[0..2]
TESTIN# HD#40 HD#41 AGP_ST0 C55
<5> H_DBSY# V5 AF10 AG25
DBSY# HD#41 HD#42 AGP_ST1 ST0 AGP_RBF# @10PF_0402
<5> H_DRDY# V4 AG11 AF24 AE22 AGP_RBF# <15>
DRDY# HD#42 HD#43 AGP_ST2 ST1 RBF# AGP_WBF#

<4> HIT# Y5 AG10 AG26 AE23 AGP_WBF# <15>
HIT# HD#43 HD#44 ST2 WBF#
<4> HITM# Y3 AH11
HITM# HD#44 HD#45
<4> HBR0# V7 AG12
BREQ#0 HD#45 HD#46 AGP_ADSTB0
<4> HADS# V3 AE13 <15> AGP_ADSTB0 R24
ADS# HD#46 HD#47 AGP_ADSTB0# AD_STB0
<4> HBNR# W3 AF12 <15> AGP_ADSTB0# R23 A19
BNR# HD#47 HD#48 AGP_ADSTB1 AD_STB#0 VSS11
AG13 <15> AGP_ADSTB1 AC27 A23
HD#48 HD#49 AGP_ADSTB1# AD_STB1 VSS12 +1.5VS
AH13 <15> AGP_ADSTB1# AC28 A27
HD#49 HD#50 AGP_SBSTB AD_STB#1 VSS13
<5> H_RS#0 W2 AC14 <15> AGP_SBSTB AF27 D5
RS#0 HD#50 HD#51 AGP_SBSTB# SB_STB VSS14
<5> H_RS#1 W7 AF14 AF26 D9
RS#1 HD#51 HD#52 <15> AGP_SBSTB# SB_STB# VSS15
<5> H_RS#2 W6 AG14 D13
RS#2 HD#52 VSS16
1
HREQ#[0..4] AE14 HD#53 D17 Place this cap near AGP
<4> HREQ#[0..4] HD#53 VSS17
HREQ#0 U6 AG15 HD#54 <15> AGP_FRAME# AGP_FRAME# Y24 D21 R12
HREQ#1 HREQ#0 HD#54 HD#55 AGP_DEVSEL# W28 G_FRAME# VSS18 1K_1%
T7 AG16 <15> AGP_DEVSEL# E1
HREQ#2 HREQ#1 HD#55 HD#56 AGP_IRDY# G_DEVSEL# VSS19
R7 AG17 <15> AGP_IRDY# W27 E4
HREQ#3 HREQ#2 HD#56 HD#57 AGP_TRDY# G_IRDY# VSS20
U5 AH15 W24 E26

HREQ#3 HD#57 <15> AGP_TRDY# G_TRDY# VSS21
HREQ#4 HD#58 AGP_STOP#
2
U2 AC17 <15> AGP_STOP# W23 E29 AGP_NBREF
HREQ#4 HD#58 HD#59 AGP_PAR G_STOP# VSS22
AF16 <15> AGP_PAR W25 F8
HD#59 G_PAR VSS23
1
AE15 HD#60 AGP_REQ# AG24 F12
HD#60 <15> AGP_REQ# G_REQ# VSS24
1
CLK_GHT J8 AH17 HD#61 AGP_GNT# AH25 F16 R11 C16
<14> CLK_GHT BCLK HD#61 <15> AGP_GNT# G_GNT# VSS25
CLK_GHT# K8 AD17 HD#62 AGP_PIPE# AF22 F20 1K_1% .1UF_0402
<14> CLK_GHT# BCLK# HD#62 <15> AGP_PIPE# PIPE# VSS26
AE16 HD#63 F24
H_DBI#[0..3] HD#63 VSS27
2
G26
<5> H_DBI#[0..3] H_DBI#0
VSS28
2
AD5 H9
H_DBI#1 DBI#0 H_DSTBN#0 VSS29
AG4 AD4 N22 H11
H_DBI#2 DBI#1 HDSTBN#0 H_DSTBN#1 VSS0 VSS30
AH9 AE6 K27 H13
H_DBI#3 DBI#2 HDSTBN#1 H_DSTBN#2 VSS1 VSS31
AD15 AE11 K5 H15
3 +CPU_CORE DBI#3 HDSTBN#2 H_DSTBN#3 VSS2 VSS32 3
AC15 L24 H17
HDSTBN#3 H_DSTBP#0 VSS3 VSS33
AD3 M23 H19
HDSTBP#0 H_DSTBP#1 VSS4 VSS34
AE7 K7 H21
HDSTBP#1 H_DSTBP#2 +CPU_CORE VSS5 VSS35
AD11 J26 J1
HDSTBP#2 VSS6 VSS36
1

H_SWNG0 H_DSTBP#3
AA7
HSWNG0 HDSTBP#3
AC16 A3
VSS7 VSS37
J4
HUB Interface Reference
1
R35 C58 H_SWNG1 AD13 A7 J6

HSWNG1 VSS8 VSS38
1
301_1% .01UF_0402 +V_MCH_GTLREF A11 J22 Layout note :

R26 VSS9 VSS39 +1.8VS
M7 A15 J29
HVREF0 VSS10 VSS40
2
HVREF1
R8 R_E 1. Place R_C and R_D in middle of Bus.
Trace
2
Y8 49.9_1% 2. Place capacitors near MCH.

HVREF2 BROOKDALE(MCH-M)
AC2 AB11 width>=7mila
HRCOMP0 HVREF3
1
AC13 AB17

HRCOMP1 HVREF4
1
R37
1
1
150_1% +1.5VS R91 C208
1
BROOKDALE(MCH-M) R27 C42 C69 301_1% @470PF

R22 R25 R_F
2
100_1% RP20 @8P4R_8.2K
2
R_C
24.9_0603_1% 24.9_0603_1% 1UF 220PF AGP_FRAME# 1
2
8
1
2
AGP_TRDY# 2 7
2
AGP_PAR 3 6 R93
+CPU_CORE AGP_STOP# 4 5 @56.2_1%
H_DSTBN#[0..3] RP21 @8P4R_8.2K

H_DSTBN#[0..3] <5>
2
H_DSTBP#[0..3] AGP_GNT#
H_DSTBP#[0..3] <5> GTL Reference Voltage 1 8 +VS_HUBREF
1
AGP_REQ# 2 7
1
1
R29 C44 Layout note : AGP_IRDY# 3 6
301_1% .01UF_0402 AGP_DEVSEL# 4 5 R92
1. Place R_E and R_F near MCH 0_0402
2
2. Place decoupling cap 220PF near MCH pin.(Within RP22 @8P4R_8.2K
1
2
AGP_WBF# 1 8
+1.5VS 500mils) AGP_PIPE# R90
12
2 7
1
AGP_RBF# 3 6 R_D 301_1% C196

4 R24 R30 8.2K_0402 R34 @8.2K_0402 .01UF_0402 4
4 5
150_1% 2 1 AGP_ADSTB0 2 1 AGP_ADSTB0# AGP_ST1
R13 2K_0402 R9 @1K_0402 R14 @6.2K_0402
2
R20 8.2K_0402 R21 @8.2K_0402 AGP_ST0 AGP_ST1
0=533Mhz
AGP_ST0 2 1 2 1 2 1
AGP_ADSTB1 AGP_ADSTB1# 1=400Mhz
2
2 1 2 1 0=System memory is DDR R15 @6.2K_0402

R16 8.2K_0402 R17 @8.2K_0402 1=System memory is SDR AGP_ST2 2 1
2 1 AGP_SBSTB 2 1 AGP_SBSTB#

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL +,-.
0.1

A B C D E
A B C D E
U10D
U10C
M8 R22 <11> DDR_SDQ[0..63] DDR_SDQ[0..63]
+CPU_CORE VTT_0 VCC1_5_0 +1.5VS DDR_SDQ0
U8 R29 G28 E14 DDR_CLK0 <11>
VTT_1 VCC1_5_1 DDR_SDQ1 SDQ0 SCK0
AA9 U22 F27 F15 DDR_CLK0# <11>
VTT_2 VCC1_5_2 DDR_SDQ2 SDQ1 SCK#0
AB8 U26 C28 J24 DDR_CLK1 <11>
AB18 W22 E28 G25 DDR_CLK1# <11>
AB20 W29 H25 G6 DDR_CLK2 <11>
AC19 AA22 G27 G7 DDR_CLK2# <11>
AD18 AA26 F25
VTT_7 VCC1_5_7 DDR_SDQ7 SDQ6
AD20 AB21 B28 G15 DDR_CLK3 <12>
AE19 AC29 E27 G14 DDR_CLK3# <12>
AE21 AD21 C27 E24 DDR_CLK4 <12>
1 VTT_10 VCC1_5_10 DDR_SDQ10 SDQ9 SCK4 1
AF18 AD23 B25 G24 DDR_CLK4# <12>
AF20 AE26 C25 H5 DDR_CLK5 <12>
AG19 AF23 B27 F5 DDR_CLK5# <12>
AG21
VTT_14 VCC1_5_14
AG29 Layout note : D27
SDQ13
AG23 AJ25 DDR_SDQ14 D26 K25
AJ19
VTT_16 Trace width 5mil ; Spacing E25
SDQ15 SCK#6
J25
AJ21 N14 DDR_SDQ16 D24 G17
AJ23
VTT_17 VCC1_5_16
N16 10mil DDR_SDQ17 E23
SDQ16 SCK7
G16
VTT_18 VCC1_5_17 SDQ17 SCK#7
VCC1_5_18
P13 Trace A to ball U13/T13 or DDR_SDQ18 C22
SDQ18 SCK8
H7
P15 DDR_SDQ19 E21 H6
A5
VCC1_5_19
P17
U17/T7 =1.5" Max DDR_SDQ20 C24
SDQ19 SCK#8
+2.5V VCCSM1 VCC1_5_20 SDQ20
A9 R14 DDR_SDQ21 B23 E9 DDR_SCS#0
VCCSM2 VCC1_5_21 SDQ21 SCS#0 DDR_SCS#0 <11>
A13 R16 DDR_SDQ22 D22 F7 DDR_SCS#1
A17 T15 DDR_SDQ23 B21 F9 DDR_SCS#2
A21 U14 +1.5VS DDR_SDQ24 C21 E7 DDR_SCS#3
A25 U16 DDR_SDQ25 D20 G9
VCCSM6 VCC1_5_25 SDQ25 SCS#4
C1 DDR_SDQ26 C19 G10

VCCSM7 SDQ26 SCS#5
MEMORY
C29 Murata LQG21N4R7K10 DDR_SDQ27 D18
VCCSM8
1
DDR_SDQ28 SDQ27
D7 L29 C20
VCCSM9 VCC1_8_0 +1.8VS L18 L19 DDR_SDQ29 SDQ28 DDR_SDQS0
D11 N26 E19 F26 DDR_SDQS0 <11>
VCCSM10 VCC1_8_1 DDR_SDQ30 SDQ29 SDQS0 DDR_SDQS1
D15 L25 C18 C26 DDR_SDQS1 <11>
VCCSM11 VCC1_8_2 4.7UH_30mA 4.7UH_30mA DDR_SDQ31 SDQ30 SDQS1 DDR_SDQS2
D19 M22 E17 C23 DDR_SDQS2 <11>
VCCSM12 VCC1_8_3 SDQ31 SDQS2

D23 N23 DDR_SDQ32 E13 B19 DDR_SDQS3
VCCSM13 VCC1_8_4 SDQ32 SDQS3 DDR_SDQS3 <11>
D25 DDR_SDQ33 C12 D12 DDR_SDQS4
VCCSM14 SDQ33 SDQS4 DDR_SDQS4 <11>
DDR_SDQS5
2
F6 "Trace A" DDR_SDQ34 B11 C8
VCCSM15 SDQ34 SDQS5 DDR_SDQS5 <11>
F10 T17 VCC_MCH_PLL1 "Trace A" DDR_SDQ35 C10 C5 DDR_SDQS6
VCCSM16 VCCGA1 SDQ35 SDQS6 DDR_SDQS6 <11>
F14 T13 VCC_MCH_PLL0 DDR_SDQ36 B13 E3 DDR_SDQS7
VCCSM17 VCCHA1 SDQ36 SDQS7 DDR_SDQS7 <11>
F18 DDR_SDQ37 C13 E15 DDR_SDQS8
VCCSM18 DDR_SDQS8 <11>
1
DDR_SDQ38 SDQ37 SDQS8
F22 C11
VCCSM19 VSS_MCH_PLL1 C92 C91 DDR_SDQ39 SDQ38 DDR_SMA[0..12]
G1 U17 + + D10

VCCSM20 VSSGA2 SDQ39 DDR_SMA[0..12] <11,12>
G4 U13 VSS_MCH_PLL0 33UF_D2_16V 33UF_D2_16V DDR_SDQ40 E10 E12 DDR_SMA0
VCCSM21 VSSHA2 DDR_SDQ41 SDQ40 SMA0/CS#11 DDR_SMA1
G29
VCCSM22
"Trace A" C9
SDQ41 SMA1/CS#10
F17
2 2
2
H8 DDR_SDQ42 D8 E16 DDR_SMA2
VCCSM23 SDQ42 SMA2/CS#6
POWER/GND
H10 AA4 DDR_SDQ43 E8 G18 DDR_SMA3

VCCSM24 VSS83 DDR_SDQ44 SDQ43 SMA3/CS#9 DDR_SMA4
H12
VCCSM25 VSS84
AA8 "Trace A" E11
SDQ44 SMA4/CS#5
G19
H14 AA29 DDR_SDQ45 B9 E18 DDR_SMA5
H16 AB6 B7 F19
H18 AB9 C7 G21

H20 AB10 C6 G20
H22 AB12 D6 F21
H24 AB13 D4 F13
VCCSM31 VSS90 DDR_SDQ51 SDQ50 SMA10 DDR_SMA11
K22 AB14 B3 E20
K24 AB15 E6 G22
VCCSM33 VSS92 DDR_SDQ53 SDQ52 SMA12/CS#1
K26 AB16 B5
VCCSM34 VSS93 DDR_SDQ54 SDQ53 DDR_SBS0
L23 AB19 C4 G12 DDR_SBS0 <11,12>
VCCSM35 VSS94 DDR_SDQ55 SDQ54 SBS0 DDR_SBS1
K6 AB22 E5 G13 DDR_SBS1 <11,12>
VCCSM36 VSS95 DDR_SDQ56 SDQ55 SBS1
J5 AC1 C3
VCCSM37 VSS96 DDR_SDQ57 SDQ56 DDR_CKE0
J7 AC4 D3 G23 DDR_CKE0 <11>
VCCSM38 VSS97 DDR_SDQ58 SDQ57 SCKE0 DDR_CKE1
AC18 F4 E22 DDR_CKE1 <11>
VSS98 DDR_SDQ59 SDQ58 SCKE1 DDR_CKE2
AC20 F3 H23 DDR_CKE2 <12>
VSS99 DDR_SDQ60 SDQ59 SCKE2 DDR_CKE3
L1 AC21 B2 F23 DDR_CKE3 <12>
VSS41 VSS100 DDR_SDQ61 SDQ60 SCKE3
L4
VSS42 VSS101
AC23 C2
SDQ61 SCKE4
J23 Layout note
L6 AC26 DDR_SDQ62 E2 K23 R39 27.4_1%

L8
VSS43 VSS102
AD6 DDR_SDQ63 G5
SDQ62 SCKE5
2 1
Place this cap
VSS44 VSS103 DDR_CB[0..7] SDQ63 +1.25V
L22
VSS45 VSS104
AD8 <11> DDR_CB[0..7] closely pinJ28
L26 AD10 DDR_CB0 C16 J28 SM_RCOMP
VSS46 VSS105 DDR_CB1 SDQ64/CB0 SMRCOMP RCVIN# C78 .1UF_0402_X5R
N1 AD12 D16 G3
VSS47 VSS106 DDR_CB2 SDQ65/CB1 RCVENIN# RCVOUT#
N4 AD14 B15 H3 2 1
VSS48 VSS107 DDR_CB3 SDQ66/CB2 RCVENOUT# C81 @47PF_0402
N8 AD16 C14 R38 0_0402
VSS49 VSS108 DDR_CB4 SDQ67/CB3
N13 AD19 B17 H27
3
N15
N17
N29
P6
P8
P14
P16
R1
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
AD22
AE1
AE4
AE18
AE20
AE29
AF5
AF7
SDREF
DDR_CB5
DDR_CB6
DDR_CB7
C17
C15
D14
J21
J9
SDQ68/CB4
SDQ69/CB5
SDQ70/CB6
SDQ71/CB7
SDREF0
SDREF1
SSI_ST
SRAS#
SWE#
SCAS#
NC0
NC1
F11
G11
G8
AD26
AD27
DDR_SRAS#
DDR_SWE#
DDR_SCAS#
R_J
DDR_SRAS# <11,12>
DDR_SWE# <11,12>
DDR_SCAS# <11,12>
Layout note
3

R4 AF9
VSS59 VSS118
1
R13 AF11 Place R_J closely Ball
VSS60 VSS119 C72 BROOKDALE(MCH-M)
R15 AF13 H3<40mil,Ball H3 to G3 trace
VSS61 VSS120 .1UF_0402_X5R
R17 AF15
VSS62 VSS121 must
2
R26 AF17
VSS63 VSS122
T6 AF19 routing 1"
VSS64 VSS123
T8
VSS65 VSS124
AF21 Layout note
T14 AF25
Please closely pinJ21 and J9

VSS66 VSS125
T16 AG1
VSS67 VSS126
T22 AG18
VSS68 VSS127
U1 AG20
VSS69 VSS128
U4 AG22
VSS70 VSS129
U15 AH19
VSS71 VSS130
U29 AH21
VSS72 VSS131
V6 AH23
VSS73 VSS132
V8 AJ3
VSS74 VSS133
V22 AJ5
VSS75 VSS134
W1 AJ7
VSS76 VSS135
W4 AJ9
VSS77 VSS136
W8 AJ11
VSS78 VSS137
W26 AJ13
VSS79 VSS138
Y6 AJ15
Y22
VSS80 VSS139
AJ17
EMI Clip PAD for MCH
VSS81 VSS140
AA1 AJ27
VSS82 VSS141
PAD10 PAD21
BROOKDALE(MCH-M)
1 1
4 4
PAD-2.5X3 PAD-2.5X3

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL +, -.
0.1

A B C D E
5 4 3 2 1
Layout note : DDR Memory interface

Layout note : Processor system bus
Distribute as close as possible
Distribute as close as possible to MCH Processor Quadrant.(between VCCSM and VSS pin)
to MCH Processor Quadrant.(between VTTFSB and VSS pin)
+CPU_CORE +2.5V
D D
1
1
C41 C40 C24 C27 C28 C73 C75 C74 C79 C86 C84 C90 C94
.1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R 22UF_10V_1206 22UF_10V_1206
2
2
+2.5V
+CPU_CORE
1
C225 C71 C89 C85 C83
1
.1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R

C38 C51 C61 C25 C29
2
.1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R
2

+2.5V
+CPU_CORE
1
C70 C87 C88 C82
1
.1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R

C20 C19 C18
2
C 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R C
2
+2.5V

1
+ C93
Layout note : AGP/CORE 150UF_D2_6.3V
2
to MCH Processor Quadrant.(between VCCAGP/VCCCORE
and VSS pin)

+1.5VS
1
C26 C50 C54 C43 C52 C53

.1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R

2
B B
+1.5VS

1
C65 C64 + C176

10UF_6.3V_1206_X5R 10UF_6.3V_1206_X5R 100UF_D_16V
2

Layout note : Hub-Link

to MCH Processor Quadrant.(between VCCHL and VSS pin)
+1.8VS
A A
1
C60 C68 C62 C66

10UF_6.3V_1206_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R
2

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL MCH-M Decoupling
ADY13 LA-1271 0.1
5 4 3 2 1
A B C D E F G H
+2.5V +2.5V DDR_DQ[0..63]

DDR_DQ[0..63] <12>
SDREF DDR_F_CB[0..7]
DDR_F_CB[0..7] <12>
RP48 4P2R_22 RP56 4P2R_22 DDR_DQS[0..8]
DDR_DQS[0..8] <12>
DDR_SDQ0 1 4 DDR_DQ0 DDR_SDQ30 1 4 DDR_DQ30 JP22
DDR_SDQ4 2 3 DDR_DQ4 DDR_SDQ26 2 3 DDR_DQ26 1 2
VREF VREF
3 4
VSS VSS
1
DDR_DQ4 5 6 DDR_DQ0 C260
RP24 4P2R_22 RP33 4P2R_22 DDR_DQ5 DQ0 DQ4 DDR_DQ1
7 8
DDR_SDQ1 DDR_DQ1 DDR_SDQ31 DDR_DQ31 DQ1 DQ5 .1UF_0402
1 4 1 4 9 10
DDR_SDQ5 DDR_DQ5 DDR_SDQ27 DDR_DQ27 DDR_DQS0 VDD VDD
2
2 3 2 3 11 12
DDR_DQ3 DQS0 DM0 DDR_DQ6
13 14 DDR_SMA[0..12] <9,12>
DQ2 DQ6
15 16
RP49 4P2R_22 RP57 4P2R_22 DDR_DQ7 VSS VSS DDR_DQ2
17 18
DDR_SDQ6 DDR_DQ6 DDR_CB5 DDR_F_CB5 DDR_DQ12 DQ3 DQ7 DDR_DQ8 RP8 4P2R_10
1 4 1 4 19 20
DDR_SDQS0 DDR_DQS0 DDR_CB4 DDR_F_CB4 DQ8 DQ12 DDR_SMA12 1
2 3 2 3 21 22 4 DDR_F_SMA12
1 DDR_DQ13 VDD VDD DDR_DQ9 DDR_SMA9 2 1
Layout note 23 24 3 DDR_F_SMA9
DDR_DQS1 DQ9 DQ13
25 26
RP25 4P2R_22 RP34 4P2R_22 DQS1 DM1
27 28
DDR_SDQ2 DDR_DQ2 DDR_CB1 DDR_F_CB1 DDR_DQ14 VSS VSS DDR_DQ10 RP35 4P2R_10
Place these resistor 1 4 1 4 29
DQ10 DQ14
30
DDR_SDQ3 2 3 DDR_DQ3 DDR_CB0 2 3 DDR_F_CB0 DDR_DQ11 31 32 DDR_DQ15 DDR_SMA8 1 4 DDR_F_SMA8
closely DIMM0, 33
DQ11 DQ15
34 DDR_SMA11 2 3 DDR_F_SMA11
VDD VDD
all trace length<750mil <9> DDR_CLK1 35
CK0 VDD
36
RP50 4P2R_22 RP58 4P2R_22 37 38
<9> DDR_CLK1# CK0# VSS
DDR_SDQ8 1 4 DDR_DQ8 DDR_CB2 1 4 DDR_F_CB2 39 40 RP7 4P2R_10
DDR_SDQ7 DDR_DQ7 DDR_SDQS8 DDR_DQS8 VSS VSS DDR_SMA7
2 3 2 3 1 4 DDR_F_SMA7
DDR_SMA5 2 3 DDR_F_SMA5
DDR_DQ20 41 42 DDR_DQ16
43 44
DDR_SDQ9 DDR_DQ9 DDR_CB3 DDR_F_CB3 DQ17 DQ21 RP36 4P2R_10
1 4 1 4 45 46
DDR_SDQ12 DDR_DQ12 DDR_CB6 DDR_F_CB6 DDR_DQS2 VDD VDD DDR_SMA4
2 3 2 3 47 48 1 4 DDR_F_SMA4
DDR_DQ22 DQS2 DM2 DDR_DQ18 DDR_SMA6
49 50 2 3 DDR_F_SMA6
DQ18 DQ22
51 52
53 54
DDR_SDQS1 DDR_DQS1 DDR_DQ28 DQ19 DQ23 DDR_DQ24 RP6 4P2R_10
1 4 1 4 55 56
DDR_SDQ13 DDR_DQ13 DDR_CB7 DDR_F_CB7 DQ24 DQ28 DDR_SMA3
2 3 2 3 57 58 1 4 DDR_F_SMA3
DDR_DQ29 VDD VDD DDR_DQ25 DDR_SMA1
59 60 2 3 DDR_F_SMA1
DDR_DQS3 DQ25 DQ29
61 62
DQS3 DM3

RP27 4P2R_22 RP59 4P2R_22 63 64
DDR_SDQ10 DDR_DQ10 DDR_SDQ36 DDR_DQ36 DDR_DQ26 VSS VSS DDR_DQ30 RP37 4P2R_10
1 4 1 4 65 66
DDR_SDQ14 DDR_DQ14 DDR_SDQ32 DDR_DQ32 DDR_DQ27 DQ26 DQ30 DDR_DQ31 DDR_SMA0
2 3 2 3 67 68 1 4 DDR_F_SMA0
DQ27 DQ31 DDR_SMA2
69 70 2 3 DDR_F_SMA2
DDR_F_CB4 VDD VDD DDR_F_CB5
71 72
RP52 4P2R_22 RP39 4P2R_22 DDR_F_CB0 CB0 CB4 DDR_F_CB1
73 74
DDR_SDQ15 DDR_DQ15 DDR_SDQ33 DDR_DQ33 CB1 CB5 R44 10_0402
1 4 1 4 75 76
DDR_SDQ11 DDR_DQ11 DDR_SDQ37 DDR_DQ37 DDR_DQS8 VSS VSS DDR_SMA10 1
2 3 2 3 77 78 2 DDR_F_SMA10

DDR_F_CB6 DQS8 DM8 DDR_F_CB2
79 80
CB2 CB6
81 82
2 RP29 4P2R_22 RP40 4P2R_22 DDR_F_CB7 VDD VDD DDR_F_CB3 2
83 84 <12> DDR_F_SMA[0..12]
DDR_SDQ16 DDR_DQ16 DDR_SDQ38 DDR_DQ38 CB3 CB7
1 4 1 4 85 86
DDR_SDQ20 DDR_DQ20 DDR_SDQS4 DDR_DQS4 DU DU/RESET#
2 3 2 3 87 88
VSS VSS
<9> DDR_CLK0 89
CK2 VSS
90 Layout note
<9> DDR_CLK0# 91 92
RP53 4P2R_22 RP60 4P2R_22 CK2# VDD
93
VDD VDD
94 Place these resistor
DDR_SDQ21 DDR_DQ21 DDR_SDQ39 DDR_DQ39 DDR_CKE1 DDR_CKE0

1 4 1 4 <9> DDR_CKE1 95 96 DDR_CKE0 <9>
DDR_SDQ17 2 3 DDR_DQ17 DDR_SDQ34 2 3 DDR_DQ34 97
CKE1 CKE0
98 closely DIMM0,
DDR_SMA12 DU/A13 DU/BA2 DDR_SMA11
99
A12 A11
100 all trace length<=750mil
DDR_SMA9 101 102 DDR_SMA8
RP30 4P2R_22 RP41 4P2R_22 A9 A8
103 104
DDR_SDQ18 DDR_DQ18 DDR_SDQ44 DDR_DQ44 DDR_SMA7 VSS VSS DDR_SMA6
1 4 1 4 105 106
DDR_SDQS2 DDR_DQS2 DDR_SDQ35 DDR_DQ35 DDR_SMA5 A7 A6 DDR_SMA4
2 3 2 3 107 108
DDR_SMA3 A5 A4 DDR_SMA2
109 110
DDR_SMA1 A3 A2 DDR_SMA0
111
A1 A0
112 Layout note
RP54 4P2R_22 RP61 4P2R_22 113 114
DDR_SDQ19 DDR_DQ19 DDR_SDQ45 DDR_DQ45 DDR_SMA10 VDD VDD DDR_SBS1
1 4 1 4 115
A10/AP BA1
DDR_SDQ22 2 3 DDR_DQ22 DDR_SDQ40 2 3 DDR_DQ40 DDR_SBS0 117 118 DDR_SRAS#
DDR_SWE# 119
BA0 RAS#
120 DDR_SCAS# closely DIMM0,
DDR_SCS#0 WE# CAS# DDR_SCS#1
<9> DDR_SCS#0 121
S0# S1#
122 DDR_SCS#1 <9> all trace length Max=1.3"
RP31 4P2R_22 RP42 4P2R_22 123 124

DDR_SDQ24 DDR_DQ24 DDR_SDQS5 DDR_DQS5 DU DU +1.25V
1 4 1 4 125 126
DDR_SDQ23 DDR_DQ23 DDR_SDQ41 DDR_DQ41 DDR_DQ36 VSS VSS DDR_DQ32
2 3 2 3 127 128
DDR_DQ33 DQ32 DQ36 DDR_DQ37
129 130
DQ33 DQ37
131 132
RP55 4P2R_22 RP62 4P2R_22 DDR_DQS4 VDD VDD RP89 4P2R_56
133 134
DDR_SDQ25 DDR_DQ25 DDR_SDQ43 DDR_DQ43 DDR_DQ38 DQS4 DM4 DDR_DQ34 DDR_CKE1
1 4 1 4 135 136 1 4
DDR_SDQ28 DDR_DQ28 DDR_SDQ42 DDR_DQ42 DQ34 DQ38 DDR_CKE0
2 3 2 3 137 138 2 3
3
DDR_SDQS3
DDR_SDQ29
RP32
1
2
4P2R_22
4
3
DDR_DQS3
DDR_DQ29
DDR_SDQ47
DDR_SDQ46
RP43
1
2
4P2R_22
4
3

DDR_DQ47
DDR_DQ46
DDR_DQ39
DDR_DQ44
DDR_DQ45
DDR_DQS5
DDR_DQ43
DDR_DQ47
139
141
143
145
147
149
151
153
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
140
142
144
146
148
150
152
154
DDR_DQ35
DDR_DQ40
DDR_DQ41
DDR_DQ42
DDR_DQ46
RP94
DDR_SCS#0 1
DDR_SCS#1 2
4P2R_56
4
3 3

155 156
DDR_SDQ[0..63] VDD VDD
<9> DDR_SDQ[0..63] 157 158 DDR_CLK2# <9>
DDR_CB[0..7] VDD CK1#
<9> DDR_CB[0..7] 159 160 DDR_CLK2 <9>
DDR_SDQS[0..8] RP63 4P2R_22 VSS CK1
<9> DDR_SDQS[0..8] 161 162
DDR_SDQ49 DDR_DQ49 DDR_DQ49 VSS VSS DDR_DQ48
1 4 163 164
DDR_SDQ48 DDR_DQ48 DDR_DQ53 DQ48 DQ52 DDR_DQ52
2 3 165 166
DQ49 DQ53
167 168
DDR_DQS6 VDD VDD
169 170

RP44 4P2R_22 DDR_DQ54 DQS6 DM6 DDR_DQ50

171 172
DDR_SDQ53 DDR_DQ53 DQ50 DQ54
1 4 173 174
DDR_SDQ52 DDR_DQ52 DDR_DQ55 VSS VSS DDR_DQ51
2 3 175 176
177 178
RP65 4P2R_22 DQ56 DQ60
179
VDD VDD
180 Layout note
DDR_SDQ56 1 4 DDR_DQ56 RP64 4P2R_22 DDR_DQ60 181 182 DDR_DQ61
DDR_SDQ51 DDR_DQ51 DDR_SDQ54 DDR_DQ54 DDR_DQS7 DQ57 DQ61
2 3 1 4 183
DQS7 DM7
DDR_SDQS6 2 3 DDR_DQS6 185 186
DDR_DQ62 VSS VSS DDR_DQ58 closely DIMM0,
187 188
RP46 4P2R_22 DDR_DQ63 DQ58 DQ62 DDR_DQ59
189 190 all trace
DDR_SDQ60 DDR_DQ60 RP45 4P2R_22 DQ59 DQ63
1 4 191 192
DDR_SDQ57 DDR_DQ57 DDR_SDQ55 DDR_DQ55 VDD VDD length<=750mil
2 3 1 4 <12,14> DIMM_SMDATA 193 194
DDR_SDQ50 DDR_DQ50 SDA SA0 RP5 4P2R_10
2 3 <12,14> DIMM_SMCLK 195 196
SCL SA1 DDR_SBS0
197 198 <9,12> DDR_SBS0 1 4 DDR_F_SBS0 DDR_F_SBS0 <12>
+3VS VDD_SPD SA2 DDR_SWE#
199 200 <9,12> DDR_SWE# 2 3 DDR_F_SWE# DDR_F_SWE# <12>
RP66 4P2R_22 VDD_ID DU
DDR_SDQS7 1 4 DDR_DQS7
DDR_SDQ61 2 3 DDR_DQ61 DDR-SODIMM_200_Normal RP38 4P2R_10
<9,12> DDR_SCAS# DDR_SCAS# 1 4 DDR_F_SCAS# DDR_F_SCAS# <12>
<9,12> DDR_SRAS# DDR_SRAS# 2 3 DDR_F_SRAS#
4 DDR_F_SRAS# <12> 4
RP47 4P2R_22 DIMM0
DDR_SDQ62 1 4 DDR_DQ62 R137 10_0402
DDR_SDQ58 2 3 DDR_DQ58 Bottom <9,12> DDR_SBS1 DDR_SBS1 1 2 DDR_F_SBS1 DDR_F_SBS1 <12>
side
DDR_SDQ63
RP67
1
4P2R_22
4 DDR_DQ63
DDR_SDQ59 2 3 DDR_DQ59 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL /01*01#
0.1

A B C D E F G H
A B C D E
+2.5V +2.5V
+1.25V +1.25V
SDREF
DDR_F_CB[0..7] <11>
JP12
RP73 4P2R_56 RP84 4P2R_56 RP104 4P2R_56
DDR_DQS[0..8] <11> 1 2
DDR_DQ4 VREF VREF
1 4 4 1 DDR_DQ26 4 1 DDR_DQ48 3 4
VSS VSS
1
DDR_DQ0 2 3 3 2 DDR_DQ30 3 2 DDR_DQ49 DDR_DQ[0..63] DDR_DQ0 5 6 DDR_DQ4
DDR_DQ[0..63] <11> DQ0 DQ4
DDR_DQ1 7 8 DDR_DQ5 C123
DQ1 DQ5 .1UF_0402
DDR_F_SMA[0..12] <11> 9 10
RP74 4P2R_56 RP15 4P2R_56 RP105 4P2R_56 DDR_DQS0 VDD VDD
2
11 12
DDR_DQ5 DQS0 DM0
1 4 4 1 DDR_DQ27 4 1 DDR_DQ52 DDR_SMA[0..12] <9,11>
DDR_DQ1 DQ2 DQ6
2 3 3 2 DDR_DQ31 3 2 DDR_DQ53 15 16
DDR_DQ2 VSS VSS DDR_DQ7
17 18
DDR_DQ8 DQ3 DQ7 DDR_DQ12 +1.25V
19 20
RP75 4P2R_56 RP85 4P2R_56 RP106 4P2R_56 DQ8 DQ12
21 22
1 DDR_DQS0 VDD VDD RP90 4P2R_56 1
1 4 4 1 DDR_F_CB4 4 1 DDR_DQ54 DDR_DQ9 23 24 DDR_DQ13
DDR_DQ6 DQ9 DQ13
2 3 3 2 DDR_F_CB5 3 2 DDR_DQS6 DDR_DQS1 25 26 4 1 DDR_SMA9
DQS1 DM1
27 28 3 2 DDR_SMA12
29 30
RP76 4P2R_56 RP14 4P2R_56 RP107 4P2R_56 DDR_DQ15 DQ10 DQ14 DDR_DQ11
31 32
DDR_DQ3 DQ11 DQ15 RP69 4P2R_56
1 4 4 1 DDR_F_CB0 4 1 DDR_DQ50 33 34
DDR_DQ2 VDD VDD
2 3 3 2 DDR_F_CB1 3 2 DDR_DQ55 <9> DDR_CLK4 35 36 4 1 DDR_SMA11
CK0 VDD
<9> DDR_CLK4# 37 38 3 2 DDR_SMA8
CK0# VSS
39 40
RP77 4P2R_56 RP86 4P2R_56 VSS VSS
DDR_DQ7 RP13 4P2R_56 RP91 4P2R_56
1 4 4 1 DDR_F_CB2
DDR_DQ8 2 3 3 2 DDR_DQS8 4 1 DDR_DQ51 DDR_DQ16 41 42 DDR_DQ20 4 1 DDR_SMA5
DQ16 DQ20
3 2 DDR_DQ56 DDR_DQ21 43 44 DDR_DQ17 3 2 DDR_SMA7
DQ17 DQ21
45 46
RP78 4P2R_56 RP87 4P2R_56 DDR_DQS2 VDD VDD
47 48
DDR_DQ12 RP110 4P2R_56 DQS2 DM2 RP70 4P2R_56
1 4 4 1 DDR_F_CB3 DDR_DQ18 49 50 DDR_DQ22
DQ18 DQ22
DDR_DQ9 2 3 3 2 DDR_F_CB6 4 1 DDR_DQ57 51 52 4 1 DDR_SMA6

VSS VSS
3 2 DDR_DQ60 DDR_DQ19 53 54 DDR_DQ23 3 2 DDR_SMA4
55 56
RP79 4P2R_56 RP88 4P2R_56 DQ24 DQ28
57 58
DDR_DQS1 RP12 4P2R_56 DDR_DQ25 VDD VDD DDR_DQ29 RP92 4P2R_56
1 4 4 1 59 60
DDR_DQ13 DQ25 DQ29
2 3 3 2 DDR_F_CB7 4 1 DDR_DQ61 DDR_DQS3 61 62 4 1 DDR_SMA1
DQS3 DM3

3 2 DDR_DQS7 63 64 3 2 DDR_SMA3
65 66
67 68
DDR_DQ14 RP108 4P2R_56 DQ27 DQ31 RP71 4P2R_56
1 4 4 1 DDR_DQ36 69 70
DDR_DQ10 VDD VDD
2 3 3 2 DDR_DQ32 4 1 DDR_DQ58 DDR_F_CB5 71 72 DDR_F_CB4 4 1 DDR_SMA2
CB0 CB4
3 2 DDR_DQ62 DDR_F_CB1 73 74 DDR_F_CB0 3 2 DDR_SMA0
CB1 CB5
75 76
RP81 4P2R_56 RP96 4P2R_56 DDR_DQS8 VSS VSS
77 78

DDR_DQ11 RP11 4P2R_56 DQS8 DM8
1 4 4 1 DDR_DQ37 DDR_F_CB2 79 80 DDR_F_CB6 R160 56_0402
DDR_DQ15 CB2 CB6
2 3 3 2 DDR_DQ33 4 1 DDR_DQ59 81 82 1 2 DDR_SMA10
2 VDD VDD 2
3 2 DDR_DQ63 DDR_F_CB3 83 84 DDR_F_CB7
CB3 CB7
85 86
RP19 4P2R_56 RP97 4P2R_56 DU DU/RESET# RP93 4P2R_56
87 88
DDR_DQ20 VSS VSS
1 4 4 1 DDR_DQ38 <9> DDR_CLK3 89 90 4 1 DDR_SWE#
DDR_DQ16 CK2 VSS
2 3 3 2 DDR_DQS4 <9> DDR_CLK3# 91 92 3 2 DDR_SBS0
CK2# VDD
93 94
DDR_CKE3 VDD VDD DDR_CKE2

<9> DDR_CKE3 95 96 DDR_CKE2 <9>
RP82 4P2R_56 RP98 4P2R_56 CKE1 CKE0 RP72 4P2R_56
97 98
DDR_DQ17 DU/A13 DU/BA2
1 4 4 1 DDR_DQ39 DDR_F_SMA12 99 100 DDR_F_SMA11 4 1 DDR_SRAS#
DDR_DQ21 A12 A11
2 3 3 2 DDR_DQ34 DDR_F_SMA9 101 102 DDR_F_SMA8 3 2 DDR_SCAS#
A9 A8
103 104
DDR_F_SMA7 VSS VSS DDR_F_SMA6
105 106
RP18 4P2R_56 RP99 4P2R_56 DDR_F_SMA5 A7 A6 DDR_F_SMA4 R142 56_0402
107 108
DDR_DQS2 A5 A4
1 4 4 1 DDR_DQ35 DDR_F_SMA3 109 110 DDR_F_SMA2 1 2 DDR_SBS1
DDR_DQ18 A3 A2
2 3 3 2 DDR_DQ44 DDR_F_SMA1 111 112 DDR_F_SMA0
A1 A0
113 114
DDR_F_SMA10 VDD VDD DDR_F_SBS1
115 116 DDR_F_SBS1 <11>
RP83 4P2R_56 RP100 4P2R_56 DDR_F_SBS0 A10/AP BA1 DDR_F_SRAS#
<11> DDR_F_SBS0 117 118 DDR_F_SRAS# <11>
DDR_DQ22 BA0 RAS#
1 4 4 1 DDR_DQ40 <11> DDR_F_SWE#
DDR_F_SWE# 119 120 DDR_F_SCAS#
DDR_F_SCAS# <11>
DDR_DQ19 WE# CAS#
2 3 3 2 DDR_DQ45 <9> DDR_SCS#2
DDR_SCS#2 121 122 DDR_SCS#3
DDR_SCS#3 <9>
S0# S1#
123 124

DU DU
125 126
127 128
DDR_DQ23 DQ32 DQ36
1 4 4 1 DDR_DQ41 DDR_DQ37 129 130 DDR_DQ33 <9,11> DDR_SBS0 DDR_SBS0
DDR_DQ24 DQ33 DQ37
2 3 3 2 DDR_DQS5 131 132 <9,11> DDR_SWE# DDR_SWE#
DDR_DQS4 VDD VDD
133 134
DDR_DQ34 DQS4 DM4 DDR_DQ38
135 136
RP109 4P2R_56 RP102 4P2R_56 DQ34 DQ38
137 138
3
DDR_DQ28
DDR_DQ25
DDR_DQS3
DDR_DQ29
1
2
RP16
1
2
4
3
4P2R_56
4
3
4
3
RP103
4
3
1 DDR_DQ42
2 DDR_DQ43
4P2R_56
1 DDR_DQ46
2 DDR_DQ47
DDR_DQ35
DDR_DQ40
DDR_DQ41
DDR_DQS5
DDR_DQ42
DDR_DQ46
139
141
143
145
147
149
151
153
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
140
142
144
146
148
150
152
154
DDR_DQ39
DDR_DQ44
DDR_DQ45
DDR_DQ43
DDR_DQ47
<9,11> DDR_SCAS#
<9,11> DDR_SRAS#
<9,11> DDR_SBS1
DDR_SCAS#
DDR_SRAS#
DDR_SBS1
3

155 156
VDD VDD
157 158 DDR_CLK5# <9>
VDD CK1#
Layout note 159
VSS CK1
160 DDR_CLK5 <9>
161 162
Place these resistor 163
DQ48 DQ52
164
closely DIMM1, DQ49 DQ53
167 168
DDR_DQS6 VDD VDD
all trace 169 170

DDR_DQ50 DQS6 DM6 DDR_DQ54 +1.25V

171 172
length<=800mil DQ50 DQ54
173 174
175 176
177 178
DQ56 DQ60 RP10 4P2R_56
179 180
DDR_DQ61 VDD VDD DDR_DQ60 DDR_CKE2
181 182 1 4
DDR_DQS7 DQ57 DQ61 DDR_CKE3
183 184 2 3
DQS7 DM7
185 186
187 188
DDR_DQ59 DQ58 DQ62 DDR_DQ63 RP9 4P2R_56
189 190
DQ59 DQ63 DDR_SCS#2 1
191 192 4
VDD VDD DDR_SCS#3 2
<11,14> DIMM_SMDATA 193 194 +3VS 3
SDA SA0
<11,14> DIMM_SMCLK 195 196
SCL SA1
197 198
+3VS VDD_SPD SA2
199 200
VDD_ID DU
Layout note
DDR-SODIMM_200_Reverse Place these resistor
closely DIMM0,
4 4
all trace length
DIMM1 Max=1.3"
EMI Clip PAD for Memory Door Top side
PAD7 PAD8 PAD11 PAD12 PAD19 PAD14 PAD16 PAD18

1 1 1 1 1 1 1 1 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL /01*01#
PAD-2.5X3 PAD-2.5X3 PAD-2.5X3 PAD-2.5X3 PAD-2.5X3 PAD-2.5X3 PAD-2.5X3 PAD-2.5X3 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
0.1

A B C D E
A B C D E
Layout note :
to DDR-SODIMM.
+2.5V
1
1
1 C98 C118 C97 C111 C102 C99 C119 C121 C120 C113 1
.1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R
2
2
+2.5V +2.5V
1
1
C101 C105 C104 C100 C76 C103 + C122 + C117
.1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R 150UF_D2_6.3V 150UF_D2_6.3V
2

Layout note :
Place one cap close to every 2 pull up resistors termination to
+1.25V

2 2
+1.25V
1
1
C303 C302 C301 C300 C299 C326 C298 C325 C324 C304

2
2
+1.25V
1
1
C330 C331 C305 C332 C297 C295 C294 C293 C250 C306
2
2

+1.25V

1
1
C307 C308 C309 C253 C251 C252 C114 C310 C311 C312
3 3
2
2

+1.25V
1
C313 C314 C315 C316 C317 C328 C318 C329 C319 C320

2
+1.25V
1
C321 C322 C284 C285 C286 C115 C296 C323 C292 C291
2
+1.25V
4 4
1
C290 C289 C288 C287

.1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R
2

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL /01* (%
0.1

A B C D E
A B C D E F G H
+3VS L21 +3V_CLK

BLM21A601SPT
SEL1 SEL0 Function 1 2 Width=40 mils
1
L48
1
0 0 66Mhz Host CLK BLM21A601SPT +
1 2 C132 C139 C364 C382 C388 C386 C385 C137
0 1 100Mhz Host CLK 22UF_10V_1206 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402
2
1 0 200Mhz Host CLK
1 1 133Mhz Host CLK +3VS_VDD48M
1 L22 1
10_0805
1 2 +3VS
*BLM21A601SPT
1
C138 C133
14
19
32
37
46
50
1
8
U22 +3VS_CLKVDD .1UF_0402 10UF_10V_1206
2
VDD_REF
VDD_3V66
VDD_3V66
VDD_48MHZ
VDD_PCI
VDD_PCI
VDD_CPU
VDD_CPU
Place Crystal within 500 mils of CK_Titan L45 +3VS
+3VS BLM21A601SPT
2 1 2 26 1 2
+3VS C381 @10PF_0402 XTAL_IN VDD_CORE
1
1 caps are internal Y2
to CK_TITAN 14.318MHZ C393 C396

R60 R61 .1UF_0402 10UF_10V_1206
2
@1K_0402 1K_0402 2 1 3 27
C380 @10PF_0402 XTAL_OUT GND_CORE
2
45 CLK_BCLK 1 2
CPUCLKT2 CLK_HCLK <4>

H_BSEL2 40 R184 33.2_1% 1 2
H_BSEL0 SEL2 R87 49.9_1%
<5> H_BSEL0 55
BSEL0 SEL1
<5> H_BSEL1 1 2 54
SEL0
Place resistor near R184,R185 ;Trace
R397 @1K_0402
R394 @0_0402
<=400mils
+3VS 1 2
1
R65 R88 1 2 49.9_1%

R59 R63 @1K_0402 25 44 CLK_BCLK# R1851 2 33.2_1%
<16,28> SLP_S1# PWR_DWN# CPU_CLKC2 CLK_HCLK# <4>
1K_0402 34

<16> PM_STPPCI# PCI_STOP#
1K_0402 R64 1 2 0_0402 53 49 CLK_HT 1 2
<16,32> PM_STPCPU# CPU_STOP# CPUCLKT1 CLK_GHT <8>
R182 33.2_1% 1 2
2 2
2
R41 49.9_1%
Place resistor near R182,R183 ;Trace
<30> CK408_PWRGD# 28 <=400mils
VTT_PWRGD#
R40 1 2 49.9_1%
R58 1 2 10K_0402 48 CLK_HT# R1831 2 33.2_1% CLK_GHT# <8>
+3VS R57 CPUCLKC1
2 @10K_0402

1 43
MULT0 CLK_ITP
52 1 2 CLK_ITPP <5>
CPUCLKT0 R180 33.2_1% 1 2
R197 49.9_1%
DIMM_SMDATA 29 Place resistor near R180,R181 ;Trace
DIMM_SMCLK SDATA
30 <=500mils
SCLK
R1961 2 49.9_1%
51 CLK_ITP# R1811 2 33.2_1% CLK_ITPP# <5>
CPUCLKC0
33
3V66_0/DRCG
35 24
3V66_1/VCH_CLK 66MHZ_IN/3V66_5
Please closely pin42 23 CLK66MCH R217 1 2 33.2_1%

66MHZ_OUT2/3V66_4 CLK_AGP_MCH <8>
R66 1 2 475_1% 42 22 CLK66AGP R216 1 2 33.2_1%

IREF 66MHZ_OUT1/3V66_3 CLK_AGP <15>
21 CLKICHHUB R227 1 2 33.2_1%
66MHZ_OUT0/3V66_2 CLK_ICHHUB <16>
R179 1 2 22_0402 CLK_ICH48M 39 7 CLKPCI_F2 R219 1 2 33.2_1%

<16> CLK_ICH48 48MHZ_USB PCICLK_F2 CLK_ICHPCI <16>
6
PCICLK_F1
5
PCICLK_F0
3
<16> CLK_ICH14
<26> CLK_14M_SIO
R186 1
R177
1
2 33_0402
2
33_0402
CLK_ICH14M
38
56
48MHZ_DOT
REF
GND_48MHZ
GND_3V66
GND_3V66
GND_IREF
GND_CPU
GND_REF
GND_PCI
GND_PCI
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
18
17
16
13
12
11
10
CLKPCI_LPC
CLKPCI_SIO
CLKPCI_LAN
CLKPCI_PCM
R223
R215
R214
R222
1
1
1
1
2
2
2
2
33.2_1%
33.2_1%
33.2_1%
33.2_1%
CLK_PCI_LPC
CLK_PCI_SIO
CLK_PCI_PCM
CLK_PCI_LAN
<27>
<26>
<21>
<20>
3

W320-04
15
20
31
36
41
47
4
9
or ICS 9508-05

Note:
CPU_CLK[2:0] needs to be running in C3, C4.
+5VS
2
G
<16,18> SMB_DATA 1 3 DIMM_SMDATA <11,12>

D
4 4
Q44 2N7002
+5VS
2

G
1 3 Title
<16,18> SMB_CLK DIMM_SMCLK <11,12> THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL !%
D
Q45 2N7002
0.1

A B C D E F G H
A B C D E
JP8
1
GND GND
2 AGP 140 Pin connector +12VALW +1.5VS +5VS +5VALW +2.5V +5V +3VS +3V
CRT_R 3 4
3 4
5 6 INVPWR_B+
5 6
1
CRT_G 7 8
7 8 C215 C217 C218 C224 C216 C220 C219 C221
9 10
CRT_B 9 10 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402
11 12
11 12
2
13 14 SMB_EC_CK1 <5,7,28,29,33>
CRT_HSYNC 13 14
15 16 SMB_EC_DA1 <5,7,28,29,33>
CRT_VSYNC 15 16
17 18 INVT_PWM <28>
3VDDCDA 17 18
19 20 DAC_BRIG <28>
19 20
21 22
3VDDCCL GND GND +3V
23 24 SUS_STAT# <16,26>
23 24
25 26
VGA_DECT 25 26 AGP_ST1 INVPWR_B+
27 28
1 AGP_ST0 27 28 AGP_SBA1 1
29 30
29 30
1
AGP_ST2 31 32 AGP_SBA3 B+
AGP_SBA0 31 32 AGP_SBA5 Q10
33 34
AGP_SBA2 33 34 AGP_SBA7 R80
35 36 AGP_NBREF 1 8
AGP_SBA4 35 36 10K_0402
37 38 AGP_SBSTB <8> 2 7
AGP_SBA6 37 38
39 40 AGP_SBSTB# <8> 3 6
39 40
1
D
2
41 42 5
GND GND
1
AGP_AD30 43 44 AGP_C/BE#3 VGA_DECT 2 Q5
43 44
1
AGP_AD28 45 46 AGP_AD31 G R81 FDS4435
45 46 2N7002
AGP_AD26 AGP_AD29 C168 02234 +
4
47 48 S
AGP_AD24 47 48 AGP_AD27 100K_0402
3
49 50 .1UF_0402
49 50 AGP_AD25
2
51 52 +AGPREF
51 52
2
<8> AGP_ADSTB1# 53 54
53 54 AGP_C/BE#2
<8> AGP_ADSTB1 55 56
55 56 AGP_AD23
57 58
AGP_AD22 57 58 AGP_AD21
59 60 <8> AGP_ST[0..2]
59 60
61 62
AGP_AD20 GND GND AGP_AD19 R78
63 64 <8> AGP_SBA[0..7]
65 66
AGP_AD16 65 66 AGP_AD[0..31] 75K
67 68 <8> AGP_AD[0..31]
67 68 AGP_C/BE#1
69 70
2
71 72 <8> AGP_C/BE#[0..3]
71 72

AGP_AD12 73 74 AGP_AD11 +5V
75 76
75 76
1
AGP_AD8 AGP_AD15 D
77 78
77 78 Q4
79 80 2
GND GND AGP_C/BE#0 G
<8> AGP_ADSTB0 81 82
81 82 AGP_AD7 2N7002
<8> AGP_ADSTB0# 83 84 S
83 84 AGP_AD5
3
85 86
87 88

89 90
AGP_AD4 89 90
91 92
2 AGP_AD6 91 92 R99 0_0402 2
93 94 PM_C3_STAT# <16>
93 94 AGP_RST#
95 96 1 2 PCIRST# <5,8,16,20,21,26,27,28>
95 96
<14> CLK_AGP 97 98 AGP_DEVSEL# <8>
97 98
99 100
GND GND
<8> AGP_PAR 101 102 AGP_STOP# <8> 1 2 EC_AGPRST# <29>
101 102
<8> AGP_IRDY# 103 104 AGP_FRAME# <8>
103 104 R101 @0_0402

<8> AGP_TRDY# 105 106 PIRQA# <16,18,21>
105 106
<8> AGP_GNT# 107 108 AGP_RBF# <8>
107 108 CRTVCC
<8> AGP_REQ# 109 110 BKOFF# <28>
109 110
2 1 RB751V 111 112 +AGPREF
<16> AGP_BUSY# D4 111 112 CRTVCC
<8> AGP_PIPE# 113 114 AGP_NBREF
113 114 +3VS +3VS
<8> AGP_WBF# 115 116 ENABKL# <29>
115 116 M_SEN#
+12VALW 117 118
117 118
1
119 120
GND GND C6
+1.5VS 121 122 +5V
121 122
1
123 124 .1UF_0402 R1 R2
123 124
2
125 126 10K_0402 10K_0402
+5VS 125 126 +3VS
127 128 R4 R69 R3
127 128
2
129 130 0_0402 4.7K_0402 4.7K_0402
+5VALW 129 130 +3V CRTVCC
131 132
131 132
2
133 134

+2.5V 133 134
135 136
135 136
137 138
137 138
2
G
139 140 Q7
GND GND 2N7002
1
1 3 3VDDCDA
1
D1 @DAN217 D7 @DAN217 D2 @DAN217 C145
S
FOXCONN_QTS0140A-1121_M140P_VGA .1UF_0402

2
G
2
Q1
2N7002
1 3 3VDDCCL
1
1
C7 C152 C9
S
3 +3VS 3
3
@3.3PF @3.3PF @3.3PF JP2
2
6
DDC_MONID0 M_SEN# 11

CRT_R 1 2 CRTR 1
L11 FCM2012C-800(0805) 7
L31 12
CRT_G 1 2 CRTG 2
FCM2012C-800(0805) 8
L12 13
CRT_B 1 2 CRTB 3
CRT Connector
FCM2012C-800(0805) 9

1
R71 1 14
1
CRTVCC 1 2 R5 R70 R6 C1 C153 C8 4
@75_1% @75_1% @75_1% 10
1K_0402 3.3PF 3.3PF 3.3PF 15
2
2
5
1
+12VALW
2
5
CRT CONN.
CRT_HSYNC 2 4 L1 1 2
1
FBM-11-160808-121
R7
U1 74AHCT1G125GW
3
47K_0402 L23 1 2
CRTVCC FBM-11-160808-121
1
1
D
2
1 2 C2 C150 C146 C5 C4 C3
R73 100K_0402 2
1
G Q2 C151 27PF 27PF
2
S SI2302DS
1
D
3
.1UF_0402
1
<29> CRT_ON# 2 5
G 100PF_0402 100PF_0402 100PF_0402
4 Q8 +5VS CRT_VSYNC 100PF_0402 4
S 2 4
3
2N7002
74AHCT1G125GW
U7
3

Title
T H I S S H E E T O F E N G I N E E RING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL! %%5"/#
A N D T R A D E S E C R E T I N F O RMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION Size Document
CONTAINS MAY Number
BE Rev
U S E D B Y O R D I S C LOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
0.1

A B C D E
A B C D
D29
+3VALW 1 2 ICH_WAKE_UP#
<29> EC_WAKEUP#
D21 RB751V
1 2 ICH_SCI# 1 2 C532 @33PF_0402
<28> SCI# <30> ICH_VGATE LAD0 <26>
R263 10K_0402 1 2
<5> PM_CPUPERF# LAD1 <26>
RB751V 1 2
<32> PM_GMUXSEL LAD2 <26> +3VALW
ICH_THRM# R348 10K_0402
LAD3 <26>
D20
<15,26> SUS_STAT# LDRQ#0 <26>
<29> LID_OUT# 1 2 ICH_L_OUT# 1 2 RTCCLK
2
R259 10K_0402 PM_STPPCI# R383
<14> PM_STPPCI# LFRAME# <26>
2
RB751V 10K_0402 D19
<14,32> PM_STPCPU# PIDEPWR <19>
R362 1 2 ICH_RI#
<28> SLP_S5# <29> SWI#
D22 @22_0402
<28> SLP_S3#
1 2 ICH_THRM# 1 2 RB751V
2 IAC_SYNC
<28> EC_THRM# +3VS <14,28> SLP_S1#
R267 10K_0402
1
1 <30> RSMRST# 1
RB751V ICH_RI#
1
GPIO2 1 2
<18> ICH_RI# +3VS
1 2 R389 8.2K_0402
<7> PM_PWROK
D18 PBTN_OUT# R301 10K_0402 GPIO3 1 2
IDE_PATADET
1 2 PBTN_OUT# R391 8.2K_0402
ICH_L_OUT#
<29> PWRBTN_OUT# <6,32> PM_DPRSLPVR
IAC_BITCLK
SDATA_IN0
SDATA_IN1
GPIO4 1 2
<18,20,21,26> PM_CLKRUN# IRQ14 <18,19>
PIDEPWR
R363
AC_RST#
ICH_SCI#
RB751V R392 8.2K_0402
EC_SMI#
SDATAO
PIRQC#
PIRQD#
<15> PM_C3_STAT# IRQ15 <18,19>
PIRQA#
PIRQB#
GPIO2
GPIO3
GPIO4
GPIO5
BATTLOW# GPIO5 1 2
R237 SIRQ <18,21,26>
PM_PWROK 1 2 33_0402 R390 8.2K_0402
<15> AGP_BUSY# Place closely to
0_0402
1
ICH3-M
AB21
AB14
IDE_PATADET 1 2 1 2
W20
W19
AC2
AB3
AB1
AA6
AA1
AA7
AA5
AA2
AA4
AB4
U21
U20
D11
C11
H22
+3VS +3VS
V21
V19
B11
Y20
J19
J20
J21
W2
W3
W4
U5
C7
U3
U2
U4
U1
C1
C5
R246 10K_0402 PIRQA# CLK_ICHPCI
V4
V5
B7
A7
V1
V2
B1
B2
A2
A6
B5
A5
Y5
Y4
Y2
Y3
T3
T2
U35A <15,18,21> PIRQA#
R28 10K_0402 PIRQB#
<18,20> PIRQB#
1
PIRQC#
PM_AGPBUSY#/GPIO6
PM_RI#
PM_SLP_S3#
PM_SLP_S5#
PM_RSMRST#
PM_SLP_S1#/GPIO19
PM_SUS_CLK
PM_GMUXSEL/GPIO23
AC_SYNC
PM_STPCPU#/GPIO20
PM_THRM#
PM_CPUPREF#/GPIO22
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ#0
LPC_DRQ#1
GPIO_7
GPIO_8
GPIO_12
GPIO_13
GPIO_25
GPIO_27
GPIO_28
PM_AUXPWROK
PM_C3_STAT#/GPIO21
PM_CLKRUN#/GPIO24
PM_DPRSLPVR
PM_STPPCI#/GPIO18
PM_SUS_STAT#
AC_BITCLK
AC_RST#
AC_SDATAIN0
AC_SDATAIN1
INT_APICCLK
INT_APICD0
INT_APICD1
INT_PIRQA#
INT_PIRQB#
PM_BATLOW#
PM_VGATE/VRMPWRGD
INT_PIRQC#
INT_PIRQD#
INT_PIRQE#/GPIO2
INT_PIRQF#/GPIO3
INT_PIRQG#/GPIO4
INT_PIRQH#/GPIO5
INT_IRQ14
INT_IRQ15
INT_SERIRQ
PM_PWRBTN#
PM_PWROK
AC_SDATAOUT
<18> PIRQC#
PIRQD# R270
<20,21,27> AD[0..31] <18> PIRQD#
10_0402
EC_SMI# AD0 CLK_ICHPCI
12
<26,28> EC_SMI# J2 T5 CLK_ICHPCI <14>
AD1 PCI_AD0 PCI_CLK C454
K1 M3 DEVSEL# <18,20,21>
AD2 PCI_AD1 PCI_DEVSEL#
J4 F1 FRAME# <18,20,21,27>
IAC_BITCLK AD3 PCI_AD2 PCI_FRAME# 15PF
<23,25> IAC_BITCLK K3 C4 PCI_REQA# <18>
PCI_AD3 PCI_GPIO0/REQA#
2

AD4 H5 D4
PCI_AD4 PCI_GPIO1/REQB#/REQ5# PCI_REQB# <18>
1 2 AD5 K4 AC'97 LPC unMUX Interrupt B6
R372 @10K_0402 AD6 PCI_AD5 PCI_GPIO16/GNTA#
H3
PCI_AD6 Power Management Geyserville Interface Interface GPIO Interface PCI_GPIO17/GNTB#/GNT5#
B3
AD7 L1 N3
PCI_AD7 PCI_IRDY# IRDY# <18,20,21>
SDATA_IN0 AD8 L2 G5
<23> SDATA_IN0 PCI_AD8 PCI_PAR PAR <20,21>
AD9 G2 M2
PCI_AD9 PCI_PERR# PERR# <18,20,21>
1 2 AD10 L4 M1
PCI_AD10 PCI_LOCK# PLOCK# <18,21>
R387 10K_0402 AD11 H4 PCI W1 ICH_WAKE_UP#

AD12 PCI_AD11 PCI_PME#
M4 Interface Y1 2 R257 1 33_0402
SDATA_IN1 AD13 PCI_AD12 PCI_RST# PCIRST# <5,8,15,20,21,26,27,28>
<25> SDATA_IN1 J3 L5 SERR# <18,20,21>
2 AD14 PCI_AD13 PCI_SERR# 2
M5 H2 STOP# <18,20,21>
AD15 PCI_AD14 STOP#
J1 H1
SDATAO
PCI_AD15 PCI_TRDY# TRDY# <18,20,21,27>

1 2 AD16 F5
+3VS PCI_AD16
R385 @10K_0402 AD17 N2
AD18 PCI_AD17 +CPU_CORE
G4 Y6 SM_INTRUDER# <18>
R364 AD19 PCI_AD18 SM_INTRUDER#
P2 AC3 SMLINK0 <18>
IAC_SDATAO AD20 PCI_AD19 SMLINK0

<23,25> IAC_SDATAO 2 1 G1 System AB2 SMLINK1 <18>
AD21 PCI_AD20 SMLINK1
P1
PCI_AD21 Managment SMB_CLK AC4 SMB_CLK <14,18>
1
22_0402 AD22 F2 AB5
IAC_SYNC AD23 PCI_AD22 Interface SMB_DATA SMB_DATA <14,18>
R248
<23,25> IAC_SYNC P3 AC5
AD24 PCI_AD23 SMB_ALERT#/GPIO11 SMB_ALERT# <18> @10K_0402
F3 PCI
AD25 R1
PCI_AD24
Interface
ICH3-M (1/2)
1
C543 C544 AD26 PCI_AD25

E2 Y22 GATEA20 <28>
AD27 PCI_AD26 CPU_A20GATE
2
N4 V23 H_A20M# <5>
@27PF @27PF AD28 PCI_AD27 CPU_A20M# R249 1
D1 AB22 2 0_0402
PCI_AD28 CPU_DPSLP#
2
AD29 P4 J22 H_FERR#

AD30 PCI_AD29 CPU_FERR#
E1 AA21 H_IGNNE# <5>
AD31 PCI_AD30 CPU_IGNNE# <5> H_DPSLP#
P5 AB23 H_INIT# <5>
PCI_AD31 CPU_INIT#
<23,25> AC97_RST# 1 2 AC_RST# CPU AA23 H_INTR <5>
+3VS (for use if CPU unable
CPU_INTR
Interface CPU_NMI
Y21 H_NMI <5> to support DPSLP#)
R388 33_0402 K2 W23

<20,21,27> C/BE#0 PCI_C/BE#0 CPU_PWRGOOD H_PWRGD <5>
1
<20,21,27> C/BE#1 K5 U22 KBRST# <28>
PCI_C/BE#1 CPU_RCIN# R318
<20,21,27> C/BE#2 N1 W21 H_SLP# <5>
PCI_C/BE#2 CPU_SLP#
1
R2 Y23 300_0402
<20,21,27> C/BE#3 PCI_C/BE#3 CPU_SMI# H_SMI# <5>
U23 R333
STPCLK# H_STPCLK# <5>
470_0402
H_FERR#
2
<18> GNT#0 A4
PCI_GNT#0 HUB_PD0
E3 L22
<18> GNT#1 PCI_GNT#1
HUB_PD0 HUB_PD1 1 Q32
2
<18,21> GNT#2 D2 M21
PCI_GNT#2 HUB_PD1 HUB_PD2
<18,20> GNT#3 D5 M23 2
PCI_GNT#3 HUB_PD2 HUB_PD3
<18> GNT#4 B4 N20 3
PCI_GNT#4 HUB_PD3
Place closely to P21 HUB_PD4 1 Q31
3 HUB_PD4 HUB_PD5 3904 3
ICH3-M R22 2
HUB_PD5 HUB_PD6
<18> REQ#0 D3 R20 3
PCI_REQ#0 HUB_PD6 HUB_PD7
<18> REQ#1 F4
PCI_REQ#1 VSS Clocks LAN EEPROM HubLink HUB_PD7
T23
CLK_ICH14 CLK_ICH48 A3 Interface Interface Interface M19 HUB_PD8 3904
<18,21> REQ#2 PCI_REQ#2 HUB_PD8 R307

R4 P19 HUB_PD9
<18,20> REQ#3 PCI_REQ#3
1
HUB_PD9 HUB_PD10
<18> REQ#4 E4 N19 <5> H_F_FERR# 1 2
PCI_REQ#4 HUB_PD10
LAN_RSTSYNC
R312 R338
HUB_VSWING
HUB_PSTRB#
HUB_RCOMP
CLK_RTEST#
HUB_PSTRB
470_0402
EEP_SHCLK
CLK_RTCX1
CLK_RTCX2
CLK_VBIAS
EEP_DOUT
HUB_VREF
LAN_RXD2
LAN_RXD1
LAN_RXD0
LAN_TXD2
LAN_TXD1
LAN_TXD0
LAN_JCLK
@10 10_0402 HUB_PD[0..10]
HUB_PAR
HUB_CLK
EEP_DIN
HUB_PD[0..10] <8>
EEP_CS
CLK_14
CLK_48
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
12
12
CLK_ICHHUB
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
C491 C511 +ICH_HUBREF

2
AC7
AC6
+VS_HUBVSWING
RTC_VBIAS AB7
C14
C15
C16
C17
C18
C19
C20
C21
C22
D13
D16
D17
D20
D21
D22
C10
D10
N22
R19
A13
A16
A17
A20
A23
B10
B13
B14
B15
B18
B19
B20
B22
A10
K19
P23
T19
F19
F20
@15PF 5PF_0402 R265
L19
L20
J23
C3
C6
D9
D7
C9
C8
D8
ICH3-M
A1
B8
E5
B9
A9
A8
E8
E9
RTC_RST# Y7
2
33_0402
CLK_ICHHUB
RTC_X1
RTC_X2
+RTCVCC CLK_ICHHUB <14>
1
2
CLK_ICH14 HUB_PSTRB <8> C450
<14> CLK_ICH14 HUB_PSTRB# <8>
CLK_ICH48 R384 HUB_ICH_RCOMP 1 2 5PF_0402
<14> CLK_ICH48
1 2 +R_VBAIS C415 1 2 RTC_VBIAS R295 36.5_1%
R234 1K_0402 .047UF 1 2 @1K_0402
+RTCVCC
RTC_X1
1
1
RTC_X2 R241 15K
1
1 2 1 2 1 2
R229 @22M R242 10M R243 10M C476 C470
C408 J1
.01UF_0402 .01UF_0402
JOPEN
X2 1UF
2
Close to ICH3-M.
2
1 2
2
+1.8VS R218 Layout note:

HUB Interface VSwing Voltage @2.4M_1% Locate J1 and R265 on bottom side and with
1
32.768KHZ R225
1
C387 C383 +1.8VS 1K_0402 easy access through memory door

R281 12PF 12PF
4 301_1% 4
1
R_K HUB Reference Voltage 1 2 BATTLOW# 1 2

<29> VLBA# +3VALW
1
1. Place R_G and R_H in middle of Bus. R221 10K_0402

R_G R298 Place R_K and R_L D16 1SS355
2
301_1%
Closely ICH3
+VS_HUBVSWING
1
+ICH_HUBREF
1
R297 C468 R_L

1
301_1% .1UF_0402
R280 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL *%*+
2
R_H 301_1%
2

2
0.1
A B C D
A B C D
+3VS
+VCC_RTC +RTCVCC
+3V
1
+5VS +3VS +3VALW
R341
RP122
1
OVCUR#5 1 8 R226 100K_0402
OVCUR#4 2 7 R200 D17 R371 1 2
OVCUR#3 1K_0402 1SS355
2
3 6
0_0402
1
OVCUR#1 4 5 1K_0402
C398 1 2 ICH_ACIN
8P4R_10K <28,33,35> ACIN
2
.1UF_0402 Closely Pin AB6 D32 RB751V
2
1
1 VCC5REF 1
C539
1
.1UF_0402
C418 C509
2
.1UF_0402 1UF +1.8VALW
USBP0+ +3VALW
2
<30> USBP0+
USBP0- +CPU_CORE
<30> USBP0-
1
1
R374
+1.8VALW VCC1.8SUS +V1.8_ICHLAN R376
1 2
VCCREFSUS
C534 5PF_0402 L53 0_0805
R361 +VCC_RTC 0_0805
1 2 1 2
VCC1.8SUS 2
USBP2+ 0_0805
<30> USBP2+ +3VS +1.8VS
VCC1.8SUS
USBP2- BLM21A601SPT
VCCPAU 2
<30> USBP2-
1 2
C535 5PF_0402 Layout note The Cap close to
ICH3-M(< 1 inch)
M10
M14
AB6
G18
C13
U18
C23
H18
R18
E13
K12
P10
K10
P14
V22
B23
A21
A22
P12
V15
V16
V17
V18
E11
K18
P18
V10
V14
T21
T18
F14
F15
F16
F10
J18
W8
W5
G6
D6
C2
H6
R6
U6
V6
V7
E6
E7
K6
P6
T1
T6
F7
F8
F9
F6
J6
U35B

VSS102
VSS103
VCC_SUS0
VCC_SUS1
VCC_SUS2
VCC_SUS3
VCC_SUS4
VCC_SUS5
VCC_USB0/VCC_SUS6
VCC_USB1/VCC_SUS7
VCC_AUX0/VCCLAN1_8
VCC_AUX1/VCCLAN1_8
VCC_AUX2/VCCLAN1_8
VCC5REF1
VCC5REF2
VCC5REFSUS1
VCC5REFSUS2
VCCPAUX0/VCCLAN3_3
VCCPAUX1/VCCLAN3_3
VCCPCPU0
VCCPCPU1
VCCPCPU2
VCCUSBBG/VCC_SUS8
VCCUSBPLL/VCC_SUS9
N/C0
N/C1
N/C2
N/C3
N/C4
VCCPPCI0
VCCPPCI1
VCCPPCI2
VCCPPCI3
VCCPPCI4
VCCPPCI5
VCCPPCI6
VCCPPCI7
VCCP0
VCCP1
VCCPIDE0
VCCPIDE1
VCCPIDE2
VCCPIDE3
VCCPIDE4
VCCPHL0
VCCPHL1
VCCPHL2
VCCPHL3
VCCCORE0
VCCCORE1
VCCCORE2
VCCCORE3
VCCCORE4
VCCCORE5
VCCCORE6
VCC_RTC
AC15
+3VS IDE_PDCS1# PDCS1# <19>
AB15
USBP0+ IDE_PDCS3# PDCS3# <19>
D19 AC21
USB_PP0 IDE_SDCS1# SDCS1# <19>
A19 AC22
IDE_SDCS3#
1
USBP2+ USB_PP1 SDCS3# <19>

E17

R330 USB_PP2
B17 AA14
USB_PP3 IDE_PDA0 PDA0 <19>
2
D15
USB_PP4 Power IDE_PDA1
AC14
PDA1 <19> 2
1K_0402 A15 AA15
USBP0- USB_PP5 IDE_PDA2 PDA2 <19>
D18 AC20
USB_PN#0 IDE_SDA0 SDA0 <19>
2
AV_VID4 A18 AA19

USBP2- USB_PN#1 IDE_SDA1 SDA1 <19>
E16 AB20
USB_PN#2 IDE_SDA2 SDA2 <19>
0=I2C CTRL CPUVID select B16
USB_PN#3 PDD[0..15] <19>
D14 W12 PDD0
1=Bus switch CPUVID select USB_PN#4 IDE_PDD0 PDD1

A14 AB11
USB_PN#5 IDE_PDD1 PDD2
AA10
IDE_PDD2 PDD3
AC10
OVCUR#0 IDE_PDD3 PDD4
<30> OVCUR#0 E12 W11
OVCUR#1 USB_OC#0 IDE_PDD4 PDD5
D12 Y9
<30> OVCUR#2 C12 AB9
B12 AA9
A12
USB_OC#4 USB IDE_PDD8
AC9
OVCUR#5 A11 Interface Y10 PDD9
USB_OC#5 IDE_PDD9 PDD10
W9
R205 0_0402 IDE_PDD10 PDD11
Y11
IDE_PDD11 PDD12
<19> PIDERST# 1 2 H20 AB10
ICH_IDE_SRST# USB_LEDA#0/GPIO32 IDE_PDD12 PDD13
G22 AC11
U21 +5VS USB_LEDA#1/GPIO33 IDE_PDD13 PDD14
<6> AC_VID0 F21 AA11
USB_LEDA#2/GPIO34 IDE_PDD14 PDD15
G19 AC12

@74AHCT1G125GW
<6>
<6>
<6>
AC_VID1
AC_VID2
AC_VID3
E22
E21
USB_LEDA#3/GPIO35
USB_LEDA#4/GPIO36
USB_LEDA#5/GPIO37
ICH3-M (2/2) IDE
Interface
IDE_PDD15
IDE_SDD0
Y17 SDD0
SDD[0..15] <19>
1
5 AV_VID4 H21 W17 SDD1

<6> AC_VID4 USB_LEDG#0/GPIO38 IDE_SDD1
MB_ID0 G23 AC17 SDD2
MB_ID1 USB_LEDG#1/GPIO39 IDE_SDD2 SDD3
<19> SIDERST# 4 2 F23 AB16
USB_LEDG#2/GPIO40 IDE_SDD3 SDD4
<28> EC_FLASH# G21 W16
ICH_ACIN USB_LEDG#3/GPIO41 IDE_SDD4 SDD5
D23 Y14
<18> ICH_M_SEN# E23
USB_LEDG#4/GPIO42
USB_LEDG#5/GPIO43
IDE_SDD5
IDE_SDD6
AA13 SDD6
3
W15 SDD7
IDE_SDD7 SDD8
W13
IDE_SDD8 SDD9
B21 Y16
3 USB_RBIAS IDE_SDD9 SDD10 3
Y15
IDE_SDD10
1
R209 0_0402 AC16 SDD11

R347 ICH_SPKR IDE_SDD11 SDD12
1 2 * <24> ICH_SPKR H23
SPKR Misc IDE_SDD12
AB17
18.2_1% AA17 SDD13
IDE_SDD13

Y18 SDD14
IDE_SDD14 SDD15
+1.8VS U19 AC18
VCCA IDE_SDD15
2
Power
Y13 PDDACK# <19>
+3VS R369 IDE_PDDACK#
M/B ID +3VALW 1 2 F17
VCCPSUS3/VCCPUSB0 IDE_SDDACK#
Y19 SDDACK# <19>
0_0805 F18 AB12 PDDREQ <19>
VCCPSUS4/VCCPUSB1 IDE_PDDREQ
K14 AB18 SDDREQ <19>
VCCPSUS5/VCCPUSB2 IDE_SDDREQ
AC13

IDE_PDIOR# PDIOR# <19>

VSS IDE_SDIOR#
AC19 SDIOR# <19>
1
E10 Y12 PDIOW# <19>

R331 R332 VCCPSUS VCCPSUS0 IDE_PDIOW#
V8 AA18 SDIOW# <19>
VCCPSUS1 IDE_SDIOW#
V9 AB13 PDIORDY <19>
@10K_0402 @10K_0402 VCCPSUS2 IDE_PIORDY
AB19 SDIORDY <19>
IDE_SIORDY
2
MB_ID0
AC1 VSS100
AC8 VSS101
E14 VSS35
E15 VSS36
E18 VSS37
E19 VSS38
E20 VSS39
F22 VSS40
G3 VSS41
G20 VSS42
H19 VSS43
AA22 VSS44
J5 VSS45
K11 VSS46
K13 VSS47
K20 VSS48
K21 VSS49
K22 VSS50
K23 VSS51
L3 VSS52
L10 VSS53
L11 VSS54
L12 VSS55
L13 VSS56
L14 VSS57
L21 VSS58
L23 VSS59
M11 VSS60
M12 VSS61
M13 VSS62
M20 VSS63
M22 VSS64
N5 VSS65
N10 VSS66
N11 VSS67
N12 VSS68
N13 VSS69
N14 VSS70
N21 VSS71
N23 VSS72
P11 VSS73
P13 VSS74
P20 VSS75
P22 VSS76
R3 VSS77
R5 VSS78
R21 VSS79
R23 VSS80
T4 VSS81
T20 VSS82
T22 VSS83
V3 VSS84
AC23VSS85
V20 VSS86
W6 VSS87
W7 VSS88
W10 VSS89
W14 VSS90
W18 VSS91
W22 VSS92
Y8 VSS93
AA3 VSS94
AA8 VSS95
AA12 VSS96
AA16 VSS97
AA20 VSS98
AB8 VSS99
MB_ID1
1
ICH3-M
R327 R326
10K_0402 10K_0402
Note:
2
R376=22.6_1% for B0(QB63 part)

R376=18.2_1% for B0(QB62 & SL5LF part)
4 4
MB_ID0 MB_ID1
SST 0 0 R308
1 2 ICH_SPKR
+3VS
PT 1 0
ST 0 1 @1K_0402
Title
QT 1 1 Disable Timeout feature THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL *%*+
0.1

A B C D
A B C D
+3VS +3VS
RP114
<16,20,21,27> FRAME# 1 10
<16,20,21> IRDY# 2 9 SERR# <16,20,21>
<16,20,21,27> TRDY# 3 8 DEVSEL# <16,20,21>
4 7 +CPU_CORE
<16,20,21> STOP# PERR# <16,20,21>
5 6 PLOCK# <16,21>
10P8R_8.2K
1
1 1
1
+
+3VS +3VS C440 C434 C453
1UF .1UF_0402 .1UF_0402
RP121
2
<16> PCI_REQA# 1 10
<16> PCI_REQB# 2 9 REQ#2 <16,21>
<16> REQ#0 3 8 REQ#3 <16,20>
<16> REQ#1 4 7 REQ#4 <16>
5 6 +3VS
SIRQ <16,21,26>
10P8R_8.2K
1
+3VS +3VS + +
C406 C533 C505 C503 C528 C502 C527 C499 C504 C457 C412 C460 C421 C423
RP119 22UF_10V_1206 22UF_10V_1206 .1UF_0402 .1UF_0402 47PF_0402 .1UF_0402 .1UF_0402 47PF_0402 .1UF_0402 .1UF_0402 47PF_0402 .1UF_0402 .1UF_0402 .1UF_0402
2
<16> GNT#1 1 10
<16,21> GNT#2 2 9 IRQ15 <16,19>
<16> PIRQD# 3 8 PIRQA# <15,16,21>
4 7 +3VS
<16,19> IRQ14 PIRQB# <16,20>
5 6 PIRQC# <16>

10P8R_8.2K
1
C512 C459 C546 C541 C407 C416
+3VS 47PF_0402 .1UF_0402 .1UF_0402 47PF_0402 .1UF_0402 .1UF_0402
2
<16> GNT#0 1 2
R365 @8.2K_0402

<16,20> GNT#3 1 2
R367 @8.2K_0402 VCCPSUS
2 2
<16> GNT#4 1 2
R366 @8.2K_0402
1
+
C545 C524 C526 C538 C537
+3VS 22UF_10V_1206 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402

2
2
R311 1 2 10K_0402
<16,20,21,26> PM_CLKRUN# +1.8VS
R375 1 2 10K_0402
<17> ICH_M_SEN#
1
+
C458 C487 C455 C482 C445 C466 C497 C432
100UF_D2_6.3V .1UF_0402 33PF_0402 .1UF_0402 .1UF_0402 33PF_0402 .1UF_0402 .1UF_0402
+3V
2

R228 1 2 4.7K_0402 VCC1.8SUS
<14,16> SMB_DATA
R220 1 2 4.7K_0402
<14,16> SMB_CLK
1
C522
+3VALW 10UF_6.3V_P C519 C525 C540
R252 1 10K_0402
2
.1UF_0402 .1UF_0402 .1UF_0402
2
<16> ICH_RI# 2
3 R250 1 2 10K_0402 3
<16> SMB_ALERT#
+3VALW

R244 1 2 4.7K_0402
<16> SMLINK0
R245 1 2 4.7K_0402
<16> SMLINK1

+RTCVCC
<16> SM_INTRUDER# 1 2
R224 10K_0402
4 4

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL *+ (%" &(
0.1

A B C D
A B C D E
+5VS Q23

+5VSHDD
+12VALW SI2301DS

!
3 1
"#$%

1
HDD Connector
R176 #$%
&
100K_0402

2
<17> PDD[0..15]
PDD[0..15] 0 !
2
1
Correct HDD pin define ,pls update layout FDD Connector 1
JP18
1
+5VS
<17> PIDERST# 1 2
1
D
PDD7
3 4
PDD8 R178
PDD6 PDD9 2 Q22 150K JP24
<16> PIDEPWR
2
5 6
1
PDD5 PDD10 G 1
R198 PDD4 7 8 PDD11 2N7002 C359 INDEX# +5V
S <26> INDEX# 2
9 10 .01UF_0402 INDEX
2
@10K_0402 PDD3 PDD12 3
PDD2 11 12 PDD13 +5V
2
DRV0# 4
13 14 <26> DRV0# DRIVE SELECT
PDD1 PDD14 5
15 16 +5V
1
PDD0 PDD15 DISKCHG# 6

17 18 <26> DISKCHG# DISK CHANGE
19 20
7
NC Placec caps. near FDD CONN.
<17> PDDREQ PDDREQ 8
21 22 READY +5VS
<17> PDIOW# 23 24 Placea caps. near HDD 9
DENSITY OUT
MTR0# 10
<17> PDIOR#
PDIORDY 25 26 PCSEL 1
R188
2 CONN. <26> MTR0# 3MODE#_11 11
MOTOR ON
<17> PDIORDY 27 28 NC
RPDDACK# +5VSHDD Layout Note: +5VSHDD trace FDDIR# 12

29 30 470_0402 <26> FDDIR# DIRECTION
RIRQ14 width 60 mil 3MODE#_13 13
31 32 DENSITY 2
1
STEP# 14 C536 C529 C523 C520
<17> PDA1 33 34 <26> STEP# STEP
PDA2 <17> 15
<17> PDA0 35 36 WDATA# GND / NC .1UF_0402 10UF_16V_1206 1UF_25V_0805 .1UF_0402
PDCS3# <17> 16
<17> PDCS1# 37 38 WRITE DATA
1
PHDD_LED# C369 C367 C366 C134 C136 <26> WDATA#
2
17
39 40 GND

+5VSHDD WGATE# 18
+5VSHDD 41 42 <26> WGATE# WRITE GATE
1000PF_0402 10UF_16V_1206 10UF_16V_1206 1UF_25V_0805 .1UF_0402 19
43 44 GND
2
TRK0# 20
<26> TRK0# TRACK 00
21
HH99221-S6-HDDCON WRPRT# NC / GND
<26> WRPRT# 22
WRITE PROTECT
23
RDATA# GND
<26> RDATA# 24
READ DATA
25

<29> FDD_PRES# GND
HDSEL# 26
<26> HDSEL# SIDE 1 SELECT
2 R193 RPDDACK# ACES 85201-2605-FDDCON 2
<17> PDDACK# 1 2
1 2 PDIORDY R192 22_0402
+3VS
1 2 RIRQ14
4.7K_0402 <16,18> IRQ14
R191 22_0402
PDDREQ 1 2
R189 @5.6K_0402

C365 1 2 3MODE#_11
1 2 R336 @0_0402
3MODE# 1 2 3MODE#_13
33PF_0402 <26> 3MODE# R335 0_0402
CD-ROM Connector
1 2 RSDDACK# +5VS
<17> SDDACK#
R152 22_0402 RP120 RP115
<16,18> IRQ15 1 2 RIRQ15 DISKCHG# 1 8 WDATA# 6 5 +5VS
<17> SDD[0..15] SDD[0..15] R149 22_0402 INDEX# 2 7 WGATE# 7 4 STEP#
WRPRT# 3 6 HDSEL# 8 3 MTR0#
SDDREQ 1 2 TRK0# 4 5 FDDIR# 9 2 RDATA#
R155 @5.6K_0402 10 1 DRV0#

+5VS
C277 8P4R_1K
1 2 10P8R_1K
1 2 33PF_0402
C280 47PF_0402
1 2 Placea caps. near CDROM
3
<23> INT_CD_L
<17> SIDERST#
C333 47PF_0402
SDD7
SDD6
JP15
1
3
5
7
2
4
6
8
SDD8
SDD9
SDD10
CD_AGND <23>
INT_CD_R <23>
1
C337
2
47PF_0402 CONN.
+5VS
+5VS
3
2
SDD5 9 10 SDD11
11 12
1
1

R51 SDD4 SDD12 C258 C257 C110 C96
@10K_0402 SDD3 13 14 SDD13
15 16
2
SDD2 SDD14 1000PF_0402 .1UF_0402 1UF_25V_0805 10UF_16V_1206
SDD1 17 18 SDD15
2
19 20 2 R62 R187
1
SDD0 SDDREQ 100K_0402 100K_0402

21 22 SDDREQ <17>
23 24 SDIOR# <17>
+5VS
<17> SDIOW# 25 26
SDIORDY RSDDACK# +5VS
1
<17> SDIORDY

RIRQ15 27 28 U23D C135

29 30 PDIAG# R148
<17> SDA1 1 2 100K_0402 PHDD_LED# 12 1 2
31 32 +5VS
<17> SDA0 SDA2 <17> 11
33 34 SHDD_LED# .1UF_0402
<17> SDCS1# SDCS3# <17> 13
35 36
1
SHDD_LED# W=80mils C262 C263 C112 C116 14 U23A

37 38 74HCT08 1
39 40 1000PF_0402 .1UF_0402 1UF_25V_0805 10UF_16V_1206 ACT_LED#
+5VS 3 ACT_LED# <27>
41 42 +5VS
2
1 2 DRV0# 2
43 44 C271 .1UF_0402 7
SEC_CSEL 45 46 74HCT08
47 48
2
49 50
R139
470_0402
1
4 4
R151
1 2 SDIORDY
+3VS
4.7K_0402

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL *6--/1
0.1

A B C D E
5 4 3 2 1
+3VASB +3RX_PWR +3VASB +3VALW +3RX_PWR
L44 BLM11A121S L43 @BLM21A601SPT
1
2 1 2 1
1
1
C126 C259 C261 C125 C129 C345 C354 C350 C349 C255 C256 C341 C335 C327 R173
C351 L20 BLM21A601SPT 11.5K_1%
.01UF_0402 .01UF_0402 .01UF_0402 .01UF_0402 .01UF_0402 .01UF_0402 .01UF_0402 .01UF_0402 .01UF_0402 .01UF_0402 .01UF_0402 .01UF_0402 .01UF_0402 .01UF_0402 2 1
2.2UF_16V_0805 +3V
2
2
LAN_100
2
1
1
C130
1
+3VS +3VASB R170 C249 R172 C353
+3RX_PWR +3TX_PWR 2 1 +3TX_PWR 2.2UF_16V_0805 .01UF_0402 1.62K_1%
+3VASB L42 BLM11A121S
2
.1UF_0402
1
C343
2
2 1
1
D C344 10K_0402 LAN_P1 D
2
1
1
1UF C274 C272
1
2
.01UF_0402 C273
G14
C14
P10
A11
B10
1
L14
J14
M2
M7
M1
M4
G1
D1
H1
N3
N1
N5
N7
2
.01UF_0402 .01UF_0402 R171 C352
K1
A6
E1
P9
B8
P2
J1
U17 2.2UF_16V_0805
2
1.91K_1%
<16,21,27> AD[0..31]
.01UF_0402
VDDX1
VDDX2
VDDX3
VDDX4
VDDX5
VDDX7
PME
MAINP5
AUX5PN
AUXP
VDDRX1
VDDRX2
VDDRX3
VDDPCI1
VDDPCI2
VDDPCI3
VDDPCI4
VDDPCI5
VDDTX1
VDDTX2
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDLVDET
2
2
AD0 B11 LAN_10
AD1 AD0 R48 10K_0402
D11
AD1 LD0 / POR0
B7 FDC6320C
AD2 C11 C7 1 2 Set Standard features
AD3 B12
AD2 LD1 / POR1
B6 Gate 1: N-MOS +3VASB
AD3 LD2 / POR2
AD4 A12
AD4 LD3
D6 R49 10K_0402 Gate 2: P-MOS Q15
AD5 C12 C6 1 2 Set SMBus Mandatory
AD6 AD5 LD4 / POR4
B13 C5
AD7 AD6 LD5
A14 A5 1 2 1 6
AD8 AD7 LD6 / POR6 G1 D1
C13
AD8 LD7
B5 Set 16K EEPROM
AD9 E11 R50 10K_0402 2 5

AD10 AD9 S2 S1 R128
B14
AD11 AD10 LAN_DTOEE
E12 A4 3 4 2 1
AD12 AD11 LA0 (LAN_100LINK) G2 D2
D13 D5
AD13 AD12 LA1 200_0402
F11 B4
AD14 AD13 LA2 / POR10 FDC6320C
E13 C4
AD14 LA3

AD15 E14 A3
AD16 AD15 LA4
J12 A2
AD17 AD16 LA5
J13
AD18 AD17 Q17
K11
AD19 AD18
L12 C1
AD20
AD21
K12
K13
AD19
AD20
AD21
3COM RXD0 / LA6
RXD1 / LA7
RXD2 / LA8
D3
E4
+3VASB LAN_DFRMEE
(LAN_10LINK)
1
G1 D1
6
AD22 L11
3C920 LAN CONTROLLER E3 2 5

AD23 AD22 RXD3 / LA9 S2 S1 R136
L13
AD24 AD23
N14 3 4 2 1
AD24
2
C AD25 G2 D2 C
N13 F3
AD26 AD25 RXER / LA10 R135 200_0402
P14 G4
AD27 AD26 RXDV / LA11 FDC6320C
P12
AD28 AD27 10K_0402
M11
AD29 AD28 U16
N12 H3
AD29 TXD0 / LA12
1
AD30 P11 H4 1 8
AD31 AD30 TXD1 / LA13 CS VCC
AT93C66 Pin6 (ORG)

N11 J4 2 7
AD31 TXD2 / LA14
2
SK NC
J3 3 6 1=16 bit ; 0=8 bit
TXD3 / LA15 R133 DI NC/ORG
K4 4 5
COL / LA16 DO GND
<16,21,27> C/BE#0 D12
CBE#0 10K_0402 AT93C86-10SC2.7
<16,21,27> C/BE#1 F12
CBE#1 Place closely to Lan chips
<16,21,27> C/BE#2 H13 D7
CBE#2 ROMCS#
1
<16,21,27> C/BE#3 M13 B3
CBE#3 MEMR#
MEMW#
D4 10M LINK :Green LED
R53 L41
B2 1 2 10K_0402 68nH
100M LINK :Orange LED
LAN_SOS1# MDIO
M3 2 1
SOS2# SOS1# Activity :
L3
SOS2# / TXCLK
1
SOS3# L4 D9 LAN_EESEL Blink(Yellow LED)
SOS4# SOS3# / TXEN EESEL LAN_EECLK R153 R154 +3VASB
K3 A9
LAN_SOS5# SOS4# / CRS EECLK / ACT LAN_DTOEE
F4
SOS5# / RXOE DTOEE / 100LNK
C8 R448 Closely AT93C86
SOS6# C2 D8 LAN_DFRMEE 61.9_1%_0805 61.9_1%_0805

SOS7# SOS6# / RXCLK DFRAMEE / 10LNK
B1
SOS7# / MDCLK R140
2
N6 LAN_TX+ LAN_EECLK 2 1
TXOP LAN_TX- (LAN_ACT)
<16,21> PAR G12 P6
LAN_AD17 PAR TXON 200_0402
M12
IDSEL
<16,18> PIRQB# L9
INTA#
The cap please closely to H0022
LAN_RX+
12
11
10
N9 N4
<5,8,15,16,21,26,27,28> PCIRST# RST#
RXIP JP9
9
M9 P4 LAN_RX-
<16,18> GNT#3 GNT# RXIN
L10 LAN_RJ45T- 2
LED_GREEN
LED_ORANGE
LDE_YELLOW+
LDE_YELLOW-
<16,18> REQ#3 REQ# U14 PR1-
<16,18,21,27> FRAME# J11
FRAME# LAN_100 C242 LAN_RJ45T+
<16,18,21> IRDY# H11 M5 1
B IRDY# REF100 LAN_10 LAN_RX+ LAN_RJ45R+ PR1+ B
<16,18,21,27> TRDY# G13
TRDY# REF10
L6 Note1 1 2 1
RD+ RX+
16
H12 LAN_RX- 2 15 LAN_RJ45R- 3
<16,18,21> DEVSEL# DEVSEL# TP1 RD- RX- PR2+
F14 4.7PF_NPO 3 14
<16,18,21> STOP# STOP#
1
CT CT
<16,18,21> PERR# G11 L7 1 4
PERR# MEDTEST PR3+

F13 C9 R161 R158
<16,18,21> SERR# SERR# GLBTEST#
<29> LAN_PME# M8 B9 6 11 5
PME# PHYTEST# 56.2_1%_0805 56.2_1%_0805 LAN_TX+ CT CT PR3-
<16,18,21,26> PM_CLKRUN# M10 7 10
CLKRUN# LAN_CRY1 LAN_TX- TD+ TX+
G2 8 9 6
X25L0 TD- TX- PR2-
2
A1 7
SHLD1
SHLD2
R54 SMBDATA PR4+
C3 Pulse-H0022
SMBCLK
1
1 2 G3 F1 LAN_CRY2 C336 8

SMBCS# X25HI PR4-

10K_0402
1
Y1 .1UF_0402 Layout Note: JM36113-L5H7
C10
13
14
WPOUT
1
LAN_RST# 25MHZ
2
D10 L5 H0022 Pls closely to RJ45 Conn. R123 R122
GRST# TXCT (NC) 75_1% 75_1% R112 R109
XTAL
L2 75_1% 75_1%
CLK_PCI_LAN NC3
1
<14> CLK_PCI_LAN L8 P8
PCICLK NC5
2
P13
VSSPCI1
VSSPCI2
VSSPCI3
VSSPCI4
VSSPCI5
NC6
VSSRX1
VSSRX2
VSSRX3
VSSTX1
VSSTX2
R120
2
VSSIO1
VSSIO2
VSSIO3
VSSIO4
VSSX1
VSSX2
VSSX3
VSSX4
VSSX5
VSSX6
VSSX7
VSSX8
VSSX9
1
Place closely to Lan chips 1 2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C347 C346
2
33PF_0402 33PF_0402 0_0402
M14
N10
H14
D14
A13
A10
K14
2
C227 C211
M6
G6
G7
G8
G9
D2
H2
N8
N2
H6
H7
H8
H9
A7
E2
P1
P7
A8
P3
K2
P5
F2
F6
F7
F8
F9
L1
J2
J6
J7
J8
J9
3C920-V3
R141 @1000PF_1206_2KV
1
1000PF_1206_2KV
AD17 1 2 LAN_AD17 DSX630G H:1.2mm +-30ppm
100_0402 (20PF)
LAN_P1 R159 10K_0402
1 2 +3VASB
A A
CLK_PCI_LAN R52 10K_0402
<29> SOS5# 1 2 LAN_SOS5# 1 2
2
D12 RB751V
R147 Note1:Place this test point in the RAM door area
+3VASB @33_0402 1 2 LAN_SOS1# R162 10K_0402
<29> SOS1#
+3VASB D5 RB751V 1 2
RP111 R168 @10K_0402
SOS1# SOS5#
1
1 8 1 2 1 2 LAN_RST#
<28> LAN_DISABLE#
SOS2# 2 7 R167 @10K_0402 D11 RB751V Title
SOS3# 3 6 SOS6# 1 2 C268 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL 3COM 3C920 LAN
SOS4# 4 5 R163 @10K_0402 @10PF_0402 R46 @0_0402 AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
SOS7# 1 2 1 2 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE Size Document Number Rev
@8P4R_10K ADY13 LA-1271 0.1
5 4 3 2 1
A B C D E
+3VS
+3VS S1_VCC
1
C334 C266 C270 C247 C241 C246 C245 C339 C278 C275 C340
4.7UF_10V_0805
.1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402
2
S1_A[0..25]
S1_A[0..25] <22>
+3VALW
4 +3VS C265 4
S1_D[0..15] .1UF_0402
S1_D[0..15] <22> <22> VPPD0
<22> VPPD1 1 2
<22> VCCD0#
<22> VCCD1#
126
138
122
102
AD[0..31]
74
73
72
71
44
18
90
86
50
30
14
63
<16,20,27> AD[0..31]
U18
VCCCB
VCCCB
VCCP
VCCP
VCC
VCC
VCC
VCC
VCCP
VCCP
VCC
VCCI
VCCD1#
VCCD0#
VPPD1
VPPD0
AD31 3 144 S1_D10
AD30 AD31 CAD31/D10 S1_D9

4 AD30 CAD30/D9 142
AD29 5 141 S1_D1
7 AD28 CAD28/D8 140
AD27 8 139 S1_D0
AD26 AD27 CAD27/D0 S1_A0
9 AD26 CAD26/A0 129
AD25 S1_A1

10 AD25 CAD25/A1 128
AD24 11 127 S1_A2
AD23 AD24 CAD24/A2 S1_A3
15 AD23 CAD23/A3 124
AD22 16 121 S1_A4
17 AD21 CAD21/A5 120
AD20 19 118 S1_A6
23 AD19 CAD19/A25 116

AD18 24 115 S1_A7
25 AD17 CAD17/A24 113
3 AD16 26 98 S1_A17 3
AD15 AD16 CAD16/A17 S1_IOWR#
38 AD15 CAD15/IOWR# 96 S1_IOWR# <22>
AD14 39 97 S1_A9
AD13 AD14 CAD14/A9 S1_IORD#
40 AD13 CAD13/IORD# 93 S1_IORD# <22>
AD12 41 95 S1_A11
AD11 AD12 CAD12/A11 S1_OE#
43 92

AD11 CAD11/OE# S1_OE# <22>
AD10 45 91 S1_CE2#
AD10 CAD10/CE2# S1_CE2# <22>
AD9 46 89 S1_A10
AD8 AD9 CAD9/A10 S1_D15
47 AD8 CAD8/D15 87
AD7 49 85 S1_D7
51 AD6 CAD6/D13 82
AD5 52 83 S1_D6
53 AD4 CAD4/D12 80
AD3 54 81 S1_D5
55 AD2 CAD2/D11 77
AD1 S1_D4
AD0
56
57
AD1 PQFP 144 CAD1/D4 79
76 S1_D3
AD0 CAD0/D3
22.2 X S1_REG#
12 125

<16,20,27> C/BE#3 C/BE3# CCBE3#/REG# S1_REG# <22>
<16,20,27> C/BE#2 27 C/BE2#
22.2 X CCBE2#/A12 112 S1_A12
37 99 S1_A8
<16,20,27>
<16,20,27>
C/BE#1
C/BE#0 48
C/BE1#
C/BE0#
1.60 CCBE1#/A8
CCBE0#/CE1# 88 S1_CE1#
S1_CE1# <22>
PCIRST# 20 119 S1_RST
<5,8,15,16,20,26,27,28> PCIRST# PCIRST# CRST#/RESET S1_RST <22>
28 111 S1_A23
<16,18,20,27> FRAME#
+3VS 1 2
<16,18,20> IRDY#
<16,18,20,27> TRDY#
<16,18,20> DEVSEL#
<16,18,20> STOP#
<16,18,20> PERR#
<16,18,20> SERR#
<16,20> PAR
29
31
32
33
34
35
36
1
PCIFRAME#
PCIIRDY#
PCITRDY#
PCIDEVSEL#
PCISTOP#
PCIPERR#
PCISERR#
PCIPAR
CFRAME#/A23
CIRDY#/A15
CTRDY#/A22
CDEVSEL#/A21
CSTOP#/A20
CPERR#/A14
CSERR#/WAIT#
CPAR/A13
110
109
107
105
104
133
101
123
S1_A15
S1_A22
S1_A21
S1_A20
S1_A14
S1_WAIT#
S1_A13
S1_INPACK#
S1_WAIT# <22>
2

<16,18> REQ#2 PCIREQ# CREQ#/INPACK# S1_INPACK# <22>
R131 10K_0402 2 106 S1_WE#
<16,18> GNT#2 PCIGNT# CGNT#/WE# S1_WE# <22>
21 108 1 2 S1_A16
<14> CLK_PCI_PCM PCIPCLK CCCLK/A16 R138 33_0402
D10 <29> PCM_PME# 1 2 59 135 S1_BVD1
RI_OUT#/PME# CSTSCHNG/BVD1 S1_BVD1 <22>
1 2 R146 0_0402 70 136 S1_WP
<28> PCM_SUSP# SUSPEND# CCLKRUN#/WP S1_WP <22>
RB751V AD20 S1_A19

1 2 13 IDSEL CBLOCK#/A19 103

R166 100_0402
60 132 S1_RDY#
<15,16,18> PIRQA# MF0 CINT#/READY S1_RDY# <22>
CLK_PCI_PCM 61
PCM_RI# MF1 PCM_SPK#
<27> PCM_RI# 64 62 PCM_SPK# <24>
1
MF2 SPKROUT S1_BVD2

<16,18,26> SIRQ 65 MF3 CAUDIO#/BVD2 134 S1_BVD2 <22>
R165 67
<16,18> PLOCK# MF4
@33_0402 68 137 S1_CD2#
MF5 CCD2#/CD2# S1_CD2# <22>
84 RSVD/D14
100 RSVD/A18
69 75 S1_CD1#
143 RSVD/D2
<16,18,20,26> PM_CLKRUN# MF6 CCD1#/CD1# S1_CD1# <22>

117 S1_VS2
CVS2/VS2# S1_VS2 <22>
12
66 131 S1_VS1
GND
GND
GND
GND
GND
GND
GND
GND
<22,28> V_PRST# G_RST# CVS1/VS1# S1_VS1 <22>

C342
114
130
@22PF_0402
22
42
58
78
94
2
OZ6912
S1_D2
S1_A18
1
S1_D14 1
Title
Compal Electronics, Ltd.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL PCMCIA controller OZ6912
ADY13 LA-1271 0.1
A B C D E
A B C D E
PCMCIA Power Controller
+12VALW S1_VCC
U19
1
C283 TPS2211 C281
1 13 1
.1UF_0402 VCC 4.7UF_10V_0805
12
VCC
2
9 11
12V VCC S1_VPP
+5VALW
10 C282
VPP
C358 5 .1UF_0402
5V
6
.1UF_0402 5V
1 VCCD0# <21>
VCCD0
2 VCCD1# <21>
+3VALW VCCD1
15 VPPD0 <21>
VPPD0
14 VPPD1 <21>
VPPD1
3
3.3V
4 8
3.3V OC
SHDN
C357
GND
S1_A[0..25]
<21> S1_A[0..25]
.1UF_0402 S1_D[0..15]
<21> S1_D[0..15]

16
7
V_PRST#
V_PRST# <21,28>
CardBus Socket C236
1 2

JP10
2 1000PF_0402 2
1 2
S1_D3 1 2 S1_CD1#
3 4
S1_D4 3 4 S1_D11 S1_CD1# <21>
5 6
S1_D5 5 6 S1_D12
7 8
S1_D6 7 8 S1_D13
9 10
S1_D7 9 10 S1_D14

11 12
S1_CE1# 11 12 S1_D15
13 14
+3VALW +5VALW S1_VPP <21> S1_CE1# S1_A10 13 14 S1_CE2#
S1_VPP 15 16
S1_OE# 15 16 S1_VS1 S1_CE2# <21>
17 18
18
1
C248 <21> S1_OE# S1_A11 17 S1_IORD# S1_VS1 <21>

19 20
20
1
C356 C363 C338 + C254 S1_A9 19 S1_IOWR# S1_IORD# <21>

21 22
.01UF_0402 S1_A8 21 22 S1_A17 S1_IOWR# <21>
23 24
10UF_10V_1206 10UF_10V_1206 1UF_25V_0805 23 24 S1_A18
2
4.7UF_25V_1206 S1_A13 25 26
25 26 S1_A19
2
S1_A14 27 28
S1_WE# 27 28 S1_A20
<21> S1_WE# 29 30
S1_RDY# 29 30 S1_A21
L40 <21> S1_RDY# 31 32
S1_VCCL 31 32 S1_VCCL
S1_VCC 1 2 33 34
FBM-11-160808-800LMT 33 34
S1_VPP 35 36 S1_VPP
S1_A16 35 36 S1_A22
37 38
S1_A15 37 38 S1_A23
39 40

S1_A12 39 40 S1_A24
41 42
S1_A7 41 42 S1_A25
43 44
S1_VCCL S1_A6 43 44 S1_VS2
45 46
S1_A5 45 46 S1_RST S1_VS2 <21>
47 48
48
1
C244 C243 S1_A4 47 S1_WAIT# S1_RST <21>
49 50
S1_A3 49 50 S1_INPACK# S1_WAIT# <21>
51 52
S1_A23 .1UF_0402 10UF_10V_1206 S1_A2 51 52 S1_REG# S1_INPACK# <21>
1 2 53 54
R144 22K_0402 S1_VCC
53 54 S1_BVD2 S1_REG# <21>
2
S1_A1 55 56
S1_WP S1_A0 55 56 S1_BVD1 S1_BVD2 <21>
1 2 57 58
R134 22K_0402 S1_VCC S1_D0 57 58 S1_D8 S1_BVD1 <21>
59 60
S1_D1 59 60 S1_D9
61 62
3 S1_D2 61 62 S1_D10 3
63 64
S1_WP 63 64 S1_CD2#
65 66
<21> S1_WP 65 66 S1_CD2# <21>
67 68
67 68
69 70
GND GND
1

71 72
GND GND C279
73 74
GND GND 1000PF_0402
75 76
GND GND
2
77 78
GND GND
79 80
GND GND
81 82
GND GND
83 84
GND GND

FOXCONN_1CA415M1-TA_68P
4 4

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL $0
0.1

A B C D E
A B C D E F G H
+5VAU reserve for AC97 coedc using only

L51 +5VALW
2 1 +12VALW
+5VALW
@BLM21A601SPT @.1UF_0402
1 1 2
1
R317 C494 C496
@2.4K
@.1UF_0402
8
R334 U32A
2
1
D
2
1 2 3 +
1 2 Q30 +5VALW VDDA
3
1
@100K_0402 D G @SI2306DS
2 -
1
D28 2 @LM358 S U34
SUSP <31>
1
1 @AS2431L C508 W=40Mil 1
3
2 G 4 5
@.1UF_0402 Q35 VIN VOUT
4
2 S R323 R355
3
@2N7002 @5.1K 2 6 1 2
1
DELAY SENSE
1
1
C517 C207 C516 C518
1
7 1 28.7K_1%
ERROR CNOISE
2
2 1 @4.7UF_10V_0805 .1UF_0402 10K_1% 4.7UF_10V_0805 .1UF_0402
1
R305 C507 @68PF
R304
2
8 3
ON/OFF# GND C513 R368
1 2 1 2 1 2
R302 @5.11K_0.5% SI9182DH-AD
@442_1% @5.11K_0.5% R300
2
1 2 2 1 VDDA
@0_0402 C486 @220PF <27,28,31,36,37> SUSP# .01UF_0402
1
C485
@.1UF_0402
AVDD_AC97

L49
1 2
VDDA VDDC
HB-1M2012-121JT
1 2 +3VS
R260 0_0805
C446

1
1
C443 C411 4.7UF_10V_0805 C420 C435 C436
2 .1UF_0402 .1UF_0402 .1UF_0402 .1UF_0402 4.7UF_10V_0805 2

2
2
VDDA
25
38
9
C399
2 1 1000PF_0402
AVCC
AVCC
VCC
VCC
C410

1 2 1000PF_0402
1
C376 C379
14 35 LINEL
AUX_L LINE_OUT_L LEFT <24>
@.1UF_0402 @4.7UF_10V_0805
LINER
2
15 36 RIGHT <24>
AUX_R LINE_OUT_R C409
C448 16 37 MDMIC 1 2 @1UF_25V_0805
VIDEO_L MONO_OUT MD_MIC <25>
2 1
17 39 1 2 1 2
VIDEO_R HP_OUT_L C405 @1000PF_0402 R233
.1UF_0402 23 41 1 2 1 2 @100K_0402
LIN_IN_L HP_OUT_R C404 @1000PF_0402 C401 @1000PF_0402
24 C431
LIN_IN_R @15PF_0402
6 1 2

BIT_CLK IAC_BITCLK <16,25>
2 1 CD_L_R 1 2 18 R254 22_0402
<19> INT_CD_L CD_L
R287 6.8K_1% C461 1UF_25V_0805 8 1 2
SDATA_IN SDATA_IN0 <16>
2 1 CD_R_R 1 2 20 R255 47_0402
<19> INT_CD_R CD_R
R288 6.8K_1% C463 1UF_25V_0805 2 C425 22PF_0402
CD_GNA 1 XTL_IN
2 1 2 19
R306 6.8K_1% C462 2.2UF_16V_0805 CD_GNA Y3
2 1 21
<24> MONO_IN
<25> MD_SPK
MONO_IN
R269
1 2
R286
2
R277
2
R278
6.8K_1%
1
@1K_0402
1
1K_0402
MDSPK
<24> MICIN
C452
1
C465
1
C447
1
2
2 .1UF_0402
1UF_25V_0805
1UF_25V_0805
22
13
12
MIC1
MIC2
PHONE
PC_BEEP

XTL_OUT
AFLT1
AFLT2
3
29
30
1
C433
1
C430
2
2
1000PF_0402
1000PF_0402
24.576 MHz
C429 22PF_0402 short the digital ground and analong ground
3
2
47K_0402 28
1
VREFOUT

R268 C451 11
<16,25> AC97_RST# RESET#
4.7K_0402 27
2700PF REFFLT
<16,25> IAC_SYNC 10
SYNC
2
32
FLT3D
1
<16,25> IAC_SDATAO 5
SDATA_OUT
1
C438 C437
1
C472 2 1 45 31
ID0# BPCFG
1
R235 2 1 @10K_0402 46 33 C414 .1UF_0402 1UF_25V_0805

2200PF R238 @10K_0402 ID1# FLTI C424
2
34
FLTO
2
2
47 43 1UF_25V_0805 .1UF_0402
EAPD# NC
1
+ C426
2
44
NC R258
48
S/PDIF_OUT
1
40 C419 @4.7U_25V_1206 @100K_0402

NC
2
4 26
GND AGND
7
GND AGND
42 @1000PF_0402 1
2
C427
2 1 CD_GNA @1UF_25V_0805
U28
1
<19> CD_AGND C417

R290
3.3K_0402 STAC9700 @.047UF
1
R279
3.3K_0402
2
4 4

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL 7
16
0.1

A B C D E F G H
A B C D E
Speaker Connector
L46
1 2 +5VALW JP17
BLM21A05_0805 INTSPK_R+ 1
+5VAMP L47 INTSPK_R- 1
2
INTSPK_L+ 2
1 2 VDDA 3
@BLM21A05_0805 INTSPK_L- 3
4
4
1 W=40mils 10 mils trace Speaker Conn. 1
1
C391 C390
C394
.1UF_0402 4.7UF_10V_0805 .1UF_0402
18
7
2
U24
2
LVDD
RVDD
INTSPK_L+ 1 2
150K R202 VDDA
LEFT 1 2 1 2 4
<23> LEFT C374 .01UF_0402 50K R201 LLINEIN INTSPK_R+
22
ROUT+
1
INTSPK_R+ 1 2
150K R206 21 R315
RLINEIN
RIGHT 1 2 1 2 15 INTSPK_R-
<23> RIGHT C375 .01UF_0402 50K R207 ROUT- 100K
INTSPK_L+ 1 2 VDDA
100K R211 INTSPK_L+ C479 C188
2
LEFT 1 2 1 2 5
LOUT+
3
1 2 2 1
EXT. MIC
C378 1UF_25V_0805 75K R210 LHPIN JP7

INTSPK_R+ 1 2 10 INTSPK_L- .1UF_0402 47PF_0402 5
100K R212 LOUT-
20
RHPIN
4
RIGHT 1 2 1 2 U30 MICSEL 4
C377 1UF_25V_0805 75K R213
VSUP
9 OP_SHUT 3 VBIAS 1 2 BIAS 3
MUTEOUT MICSEL BIAS C370 L38 BLM11A121S
16 1 6
HO/LINE# SEL EXTRMIC EXTMIC EXT_MIC
8 1 2 1 2 2
NBA_PLUG C456 R276 EXT_MIC L39 BLM11A121S
14 2 1

OP_SHUT SE/BTL# NC MIC_IN MIC- .22UF_0805
8 17 1 2 2 6
SHUTDW NC <23> MICIN OUT INT_MIC-
11 23
<28> MUTE MUTEIN NC
1
2 .22UF_0805 MIC+ C189 C194 JA6333L-100 2
5
GND
0 INT_MIC+
6 47PF_0402 47PF_0402
LBYPASS
GND/HS
GND/HS
GND/HS
GND/HS
CMAMP110
2
OPBPASS
7
19 C475
RBYPASS
1 2 INT_MIC- <30>

1
1
TPA0202 C392 .22UF_0805 VDDA
24
13
12
1
C389 R314
4.7UF_10V_0805 .1UF_0402 C467 R271 @1K_0402
2K_0402
2
1 2
R296
@.22UF_0805 2K_0402
1
R204 C495
1K_0402 R313
1K_0402 1UF_25V_0805
2
R203 C489
R289
1UF_25V_0805
VDDA 1K_0402
2

+3VS C474
1
2K_0402 C373 1 2 INT_MIC+ <30>
1
+5VS 1UF_25V_0805 .22UF_0805
2
R320 +3VS VDDA
100K_0402
1
C493

1
1 2 R319
U33
2
100K_0402 R285
U23B 1 .1UF_0402 100K_0402
NC C490
<29> BEEP 4 R324 5 R310
3 VCC C469 3
2
6 1 2 2 1 2 1 2
A
2
5 10K_0402 4 2K_0402 1 2
+5V POWER Y 1UF_25V_0805
3
1
74HCT08 GND

C498 TC7SH14 @.1UF_0402
.1UF_0402 VDDA
2
C464
1 2 MONO_IN
+3V POWER MONO_IN <23>
R299 C483 1 1UF_25V_0805 R230

1 2 1 2 2
<21> PCM_SPK#
3 Q26
100K LINE OUT

2K_0402 1UF_25V_0805 2SC2411EK C169 JP6

2 1 5
C372 NBA_PLUG 47PF_0402 4

220UF_10V_D
INTSPK_R+ 2 PR_RIGHT PR
+
1 1 2 3
L36 BLM11A121S 6
INTSPK_L+ 1 2 PR_LEFT PL
+
1 2 2
L37 BLM11A121S 1
C371
1
R291 C473 220UF_10V_D
1 2 1 2 JA6333L-100
<17> ICH_SPKR
C171 C167
2K_0402
1UF_25V_0805 47PF_0402
2
47PF_0402
1
R274 D24
@10K_0402 1SS355
4 4
2

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL " 8
0.1

A B C D E
5 4 3 2 1
+3V
1
C109 C108 +5VMDC 1 2
1
C267 C269 R45 @0_0805 +5V
MDC Note
@1000PF_0402 @.1UF_0402
@1000PF_0402 @.1UF_0402
2
Pin 1 is NC for Pctel and connexant MDC modem
2
JP21
Pin 2 is NC for Pctel and connexant MDC modem
<23> MD_MIC 1 2
+3VMDC MONO_OUT/PC_BEEP AUDIO_PWDN
3 4
D AGND MONO_PHONE MD_SPK <23> D
5 6
AUXA_RIGHT RESERVED
1 2 7 8
+3V R150 0_0805 AUXA_LEFT GND
9 10
CD_GND +5V
1 2 11 12
+3VALW R143 @0_0805 CD_RIGHT RESERVED
13 14
CD_LEFT RESERVED
15 16 1 2
GND RESERVED
2
C276 C264 17 18 R145 10K_0402 +3V 1: Have primary CODEC on mother board
.1UF_0402 +3VMDC 3.3Vaux RESERVED
19 20
4.7UF_10V_P GND RESERVED
21 22 IAC_SYNC <16,23>
3.3Vmain AC97_SYNC
1
23 24 2 R157 1
<16,23> IAC_SDATAO AC97_SDATA_OUT AC97_SDATA_IN1 SDATA_IN1 <16>
25 26 @22_0402
<16,23> AC97_RST# AC97_RESET# AC97_SDATA_IN0
27 28 2 R156 1
GND GND 22_0402
29 30 IAC_BITCLK <16,23>
AC97_MSTRCLK AC97_BITCLK
AMP 3-1473290-0
MDC Conn.

C C

Spare Logic Gate
Screw Hole
H5 H2 H1 H6 H19 H10 H9
Fiduial Mark +12VALW
C315D126 C315D126 C315D126 C315D126 C315D118 O197X138D197X138N S315D118
FD1 FD3 FD2 FD4
1 1 1 1
8
U32B
1
FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK FIDUCIAL MARK 5 +

7
FD6 FD5 6 -
1 1 @LM358
H3 H4 H27 H26 H7 H14

C315D157 C315D157 C256D157 C256D157 C315D157 C138D138N FIDUCIAL MARK FIDUCIAL MARK
4
CF2 CF1 CF13 CF17 CF3
1 1 1 1 1
1
SMDC40M80 SMDC40M80 SMDC40M80 SMDC40M80 SMDC40M80
B
H20
C354D244
H21
C354D244
H12 H13
O217X106D177X67 O217X106D177X67
M5 M6
S173D95 S173D95
1
CF4
SMDC40M80
CF7
1
CF12
SMDC40M80
CF8
1
CF5
SMDC40M80
CF10
1
CF14
SMDC40M80
CF16 CF15
B
1
1 1 1 1 1

SMDC40M80 SMDC40M80 SMDC40M80 SMDC40M80 SMDC40M80
H16 H22 H25 M7 M2 CF11 CF6 CF9

O106X217D67X177 O106X217D67X177 C315D110 S276D110 S394D138 1 1 1
SMDC40M80 SMDC40M80 SMDC40M80

1

10
13
U36C U36D
9 8 12 11
H17 H18 H23 M3
O106X217D67X177 O106X217D67X177 O106X217D67X177 S315D118 74LVC125 74LVC125
1
H15 H11 H8 H24 M1 M4 M8

S315D118 S315D118 R256X315D138 C244D118 C315D118 C315D118 S315D244
1
A A

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL %% -0+
0.1

5 4 3 2 1
A B C D E
+3VALW +3VALW
14
14
9 8 1 2 5 6 LPC_RST#
<5,8,15,16,20,21,27,28> PCIRST#
R379 10K_0402
U38D U38C
1
+3VS 74LVC14 C542 74LVC14
+3VS
7
.01UF_0402
1 1
2
1
1
C442 C471 C439 C413 +3VS
.1UF_0402 .1UF_0402 1000PF_0402 4.7UF_10V_0805
14
39
63
88
U31
2
2
1 2
R293 10K_0402
VDD
VDD
VDD
VDD
LAD0 15 52 LPD0
+3VS <16> LAD0 LAD0 PD0/INDEX# LPD0 <27>
LAD1 16 50 LPD1
<16> LAD1 LAD1 PD1/TRK0# LPD1 <27>
LAD2 17 48 LPD2
<16> LAD2 LAD2 PD2/WP# LPD2 <27>
LAD3 18 46 LPD3
<16> LAD3 LAD3 PD3/RDATA# LPD3 <27>
1
45 LPD4
PD4/DSKCHG# LPD4 <27>
R292 CLK_PCI_SIO 8 44 LPD5
<14> CLK_PCI_SIO LCLK PD5/MSEN0 LPD5 <27>
4.7K_0402 LPC_RST# 9 43 LPD6
LRESET# PD6/DRATE0 LPD6 <27>
LFRAME# 12 42 LPD7
<16> LFRAME# LFRAME# PD7/MSEN1 LPD7 <27>
LDRQ#0 11
<16> LDRQ#0 LDRQ# PC87393
2
<15,16> SUS_STAT# 7 35
LPCPD# PNF/XRDY LPTSLCT
<16,18,20,21> PM_CLKRUN# 6 36 LPTSLCT <27>
SIRQ CLKRUN#/GPIO36 SLCT/WGATE# LPTPE
<16,18,21> SIRQ 10 37 LPTPE <27>
SERIRQ PE/WDATA#
<16,28> EC_SMI# 1 2 LPCSMI# 19 40 LPTBUSY
LPTBUSY <27>
R303 @0_0402 SMI#/GPIO35 BUSY_WAIT#/MTR1# LPTACK#
41 LPTACK# <27>
CLK_PCI_SIO CLK_14M_SIO CLK_14M_SIO ACK#/DR1# LPTSLCTIN#
<14> CLK_14M_SIO 20 47 LPTSLCTIN# <27>
CLKIN SLIN#_ASTRB#/STEP#

1 2 49 LPTINIT#
LPTINIT# <27>
1
+3VS R294 @10K_0402 INIT#/DIR# LPTERR#

51 LPTERR# <27>
DISKCHG# ERR#/HDSEL# LPTAFD#
<19> DISKCHG# 21 53 LPTAFD# <27>
R283 R284 HDSEL# DSKCHG# AFD#_DSTRB#/DENSEL LPTSTB#
<19> HDSEL# 22 54 LPTSTB# <27>
10_0402 @33_0402 RDATA# HDSEL# STB#_WRITE#
<19> RDATA# 23
WRPRT# RDATA#
<19> WRPRT# 24
WP#
2
TRK0# 25 55
<19> TRK0# TRK0# DCD1# DCDA# <27>
WGATE# 26 56

<19> WGATE# DSRA# <27>
1
C480 C481 WDATA# WGATE# DSR1#

<19> WDATA# 27 57 RXDA <27>
STEP# WDATA# SIN1
<19> STEP# 28 58 RTSA# <27>
2 5PF_0402 @15PF_0402 FDDIR# SETP# RTS1#/TEST 2
<19> FDDIR# 29 59 TXDA <27>
DIR# SOUT1/XCNF0
2
DRV0# 30 60
<19> DRV0# DR0# CTS1# CTSA# <27>
MTR0# 31 61
<19> MTR0# MTR0# DTR1#_BOUT1/BADDR DTRA# <27>
+3VS INDEX# 32 62
<19> INDEX# INDEX# RI1# RIA# <27>
3MODE# 33
<19> 3MODE# DENSEL
34
DRATE0/IRSL2

70
IRTX
69
IRRX1
5
6
7
8
XA0 95 68
<28> XA0 XA0/GPIO20 IRRX2_IRSL0
RP112 XA1 94 67
<28> XA1 XA1/GPIO21 IRSL1
8P4R_10K XA2 93 66
<28> XA2 XA2/GPIO22 IRSL3/PWUREQ#
XA3 92
<28> XA3 XA3/GPIO23
XSTB0# 91
<28> XSTB0# XA4/GPIO24/XSTB0#
4
3
2
1
XCNF2 90 3 XD0
XA5/XSTB1#/XCNF2 XD0/GPIO00/JOYABTN1 XD0 <28>
87 2 XD1
<28> IRQ1 XA6/GPIO26/PRIQA/XSTB2# XD1/GPIO01/JOYBBTN1 XD1 <28>
IRQ8 86 1 XD2
XA7/GPIO27/PIRQB XD2/GPIO02/JOYAY XD2 <28>
85 100 XD3
<28> IRQ11 XA8/GPIO30/PIRQC XD3/GPIO03/JOYBY XD3 <28>
84 99 XD4
<28> IRQ12 XA9/GPIO31/MTR1#/PIRQD XD4/GPIO04/JOYBX XD4 <28>
XIOR# 83 98 XD5
<28> XIOR# XA10/GPIO32/XIORD#/MDRX XD5/GPIO05/JOYAX XD5 <28>
XIOW# 82 97 XD6
<28> XIOW# XA11/GPIO33/XIOWR#/MDTX XD6/GPIO06/JOYBBTN0 XD6 <28>
XA12 81 96 XD7

<28> XA12 XA12/GPIO10/JOYABTN1/RI2# XD7/GPIO07/JOYABTN0 XD7 <28>
XA13 80
<28> XA13 XA13/GPIO11/JOYBBTN1/DTR2#_BOUT2
XA14 79 4 XMEMW#
<28> XA14 XA14/GPIO12/JOYAY/CTS2# XWR#/XCNF1 XMEMW# <28>
XA15 78 5 XMEMR#
<28> XA15 XA15/GPIO13/JOYBY/SOUT2 XRD#/GPIO34/WDO# XMEMR# <28>
XA16 77 73
<28> XA16 XA16/GPIO14/JOYBX/RTS2# XIOWR#/XCS1#/MTR1#/DRATE0
XA17 76 71
<28> XA17 XA17/GPIO15/JOYAX/SIN2 XIORD#/GPIO37/IRSL2/DR1#
XA18 75 72 XIOCHRDY
<28> XA18 XA18/GPIO16/JOYBBTN0/DSR2# XCS0#/DR1#/XDRY/GPIO25 XIOCHRDY <28>
74
XA19/DCD2#/JOYABTN0/GPIO17
VSS
VSS
VSS
VSS
2 1
10K_0402 R236 +3VS
3 3
PC87393F
13
38
64
89

Signal Pin # Description
BADDR 61 BASE Address Selection

"0": 2E~2F (Default)
"1": 4E~4F

BADDR PULL-UP :4E

TEST 58 "0": Normal (Default) +3VS BADDR PULL-DOWN:2E
(DEFAULT)
"1": Test Mode +3VS
TXDA 1 2
XCNF0 R240 @10K_0402 DTRA# 1 2
XCNF[2:0] 90, 4, 59 2 1 0 Function R239 @10K_0402
XMEMW# 1 2
x 0 0 No BIOS XCNF1 R282 10K_0402
x 0 1 Normal Mode. XRDY disabled XCNF2 1 2

R262 @10K_0402 Pin # 61
(default) 0 1 0 Latch Mode. XA12-19, XRDY enabled * 1 ROM SOLUTION
XBUS RESET CONFIGURATION BASE ADDRESS CONFIGURATION
1 1 0 Latch Mode. GPIO10~17,XRDY enabled
0 1 1 Latch Mode. XA12-19, XRDY disabled
4 1 1 1 Latch Mode. GPIO10~17,XRDY disabled 4

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL 0(*-10 9
7
0.1

A B C D E
A B C D E
CP2 +5V_PRN
Touch Pad & Status LED Conn. RP1

+5V_PRN AFD/3M#
ERR#
1
2
8
7
Parallel Port
PRNINIT# 3 6
1
FD0 1 10 SLCTIN# 4 5 C147 C149 +5V_PRN
FD1 2 9 FD7
JP13 FD2 FD6 8P4C_270PF 4.7UF_10V_0805 .1UF_0402 D6
3 8
2
<28> TP_CLK
TP_CLK TP_DATA
TP_DATA <28>
FD3 4 7 FD5 CP12 +5VS 2 1w=10mils
1 2 FD4 ACK#
+5VS 5 6 1 8
3 4 +5V_PRN
1
BUSY 2 7
+5VS 5 6 10P8R_2.7K PE 3 6 1SS355 R68
7 8 PWR_LED# +5VALW SLCT 2.7K_0402
PWR_LED# <29> 4 5
ACT_LED# 9 10 BATT_LED# R67
<19> ACT_LED# 11 12 BATT_LED# <29> +5V_PRN C148
CHARGE_LED# 8P4C_270PF 33_0402
<29> CHARGE_LED# 13 14 RP2 LPTSTB# PWRPRN 1
2
1 2 2
15 16 <26> LPTSTB#
w=10mils
1 SLCTIN# 1 10 1
+3VS 17 18 LID_SW# <29,30>
PRNINIT# 2 9 ACK# CP1
19 20 ERR# BUSY FD0 47PF_0402
3 8 1 8
AFD/3M# 4 7 PE FD1 2 7 1
JST BM20B-SRDS-G 5 6 SLCT FD2 3 6 1 2 AFD/3M# 14
+5V_PRN FD3 <26> LPTAFD# LPD0 L30 0 FD0
4 5 1 2 2
10P8R_2.7K L6 1 2 0 ERR# 15
8P4C_270PF <26> LPTERR# LPD1 L24 0 FD1
1 2 3
C127 L29 1 2 0 PRNINIT# 16
<26> LPTINIT#
1 2 TP_CLK CP13 LPD2 L7 1 2 0 FD2 4 JP1
FD4 1 8 L28 1 2 0 SLCTIN# 17
<26> LPTSLCTIN#
@220PF FD5 2 7 LPD3 L27 1 2 0 FD3 5 LPTCN-25-SUYIN
C128 FD6 3 6 L26 0 18
1 2 TP_DATA FD7 4 5 LPD4 1 2 FD4 6
L25 0 19
@220PF 8P4C_270PF LPD5 1 2 FD5 7
CP3 L8 0 20
5 4 CHARGE_LED# LPD6 1 2 FD6 8
6 3 ACT_LED# L9 0 21
7 2 PWR_LED# LPD7 1 2 FD7 9
8 1 BATT_LED# LPD[0..7] L10 0 22
<26> LPD[0..7] ACK#
1 2 10
<26> LPTACK#

@8P4C_220PF L5 0 23
1 2 BUSY 11
<26> LPTBUSY L2 0 24
1 2 PE 12
<26> LPTPE L3 0 25
1 2 SLCT 13
PS2 CONN. <26> LPTSLCT
L4 0

U3
PS2_DATA 1 6
2 <28> PS2_DATA DATA IN DATA OUT 2
2 5
PS2_CLK GND VCC
<28> PS2_CLK 3 4
CLK IN CLK OUT
KBMF01SC6

+5VS PS2KB_VCC KB_AS
F1 JP5
W=40mils 1 2 W=40mils 4 6
L15
1
POLYSWITCH_1.1A FBM-11-451616-800T C14 2

4516 1UF_25V_0805 1
3 5
2
KBD/PS2_6 Reserved serial port for software ACPI debug +5V
33005A-06T1-01-PS2 ACPI Debug port

I16795326
1
C141
U2 JP19

KBD_DATA 1 6 @.1UF_0402 DCD1# 1 2 RXD1
<28> KBD_DATA DATA IN DATA OUT + +
TXD1 DTR1#
2
2 5 3 4
KBD_CLK GND VCC + + DSR1#
3 4
26
<28> KBD_CLK 5 6
CLK IN CLK OUT C142 @.1UF_0402 RTS1# + + CTS1#
7 8
KBMF01SC6 C140 RI1# + +
1 2 28 9 10
VCC
C1+ + +
27 1 2
@.1UF_0402 V+ @E&T 2041-010-10
3
<26> DTRA#
<26> RTSA#
<26> TXDA
DTRA#
RTSA#
TXDA
1
C143
2
@.1UF_0402
24
1
2
14
13
12
C1-
C2+
C2-
TIN1
TIN2
TIN3
TOUT1
TOUT2
TOUT3
V-
3
9
10
11
1 2
C144
@.1UF_0402
DTR1#
RTS1#
TXD1
3

+5VS CTSA# 19 4 CTS1# CP11
<26> CTSA# RIA# ROUT1 RIN1 RI1# @8P4C_270PF
18 5
<26> RIA# RXDA ROUT2 RIN2 RXD1 TXD1
17 6 1 8
<26> RXDA DCDA# ROUT3 RIN3 DCD1# CTS1#
JP23 16 7 2 7
<26> DCDA# DSRA# ROUT4 RIN4 DSR1# DTR1#
<16,20,21> AD9 TRDY# <16,18,20,21> 15 8 3 6
1 2 <26> DSRA# ROUT5 RIN5 RI1#
<16,18,20,21> FRAME# PCIRST# <5,8,15,16,20,21,26,28> 20 4 5
3 4 ROUTB2
CLK_PCI_LPC <14> 21
5 6 SUSP# INVLD#
23

7 8 C/BE#3 <16,20,21> <23,28,31,36,37> SUSP# FORCEON

<16,20,21> C/BE#2 C/BE#1 <16,20,21> 25
9 10 GND DCD1#
<16,20,21> AD8 AD7 <16,20,21> 22 1 8
11 12 FORCEOFF# DSR1#
<16,20,21> AD5 AD3 <16,20,21> 2 7
13 14 RXD1
<16,20,21> AD1 AD0 <16,20,21> 3 6
15 16 U6 RTS1#
<16,20,21> AD2 AD4 <16,20,21> 4 5
17 18 @MAX3243
<16,20,21> AD6 19 20 C/BE#0 <16,20,21>
@8P4C_270PF
AMP 5-175638-0 CP10
'()*
)'+,*
-+

)+..*)-+/
+5VALW
CLK_PCI_LPC
Debug PORT
2
1
R47
@33_0402 R345
20K_0402
4 from cardbus 4
1
2
C124 D31
@10PF_0402 1 2
<21> PCM_RI# RING# <28>
RB751V

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL *1- 0 -#: %%5" * %%5
0.1

A B C D E
A B C D E
+5VALW
1
L52 +5VALW
+5VALW BLM11A20 +3VALW
1
KB_VCC
2
R129
1
C449 C501 C444 C441 C402 C478 L50 10K_0402 R261
1 2 ECAGND 1 2 Pin 130 PU for 100K_0402
.1UF_0402 .1UF_0402 1000PF_0402 .1UF_0402 1000PF_0402 BLM11A20
Zero Latch
161
108
1 D26 1
2
.1UF_0402
2
67
23
91
80
92
U26 570_SMI#
2
1 2 EC_SMI# <16,26>
U15
VCC
VCC
VCC
VCC
AVCC
VREF
AGND
39SF040
XA0 166 114 KBA0 12 13 ADB0 RB751V
<26> XA0 HA0 A0 A0 D0
XA1 167 115 KBA1 11 14 ADB1
<26> XA1 HA1 A1 A1 D1
XA2 168 116 KBA2 10 15 ADB2
<26> XA2 HA2 A2 A2 D2
XA3 169 117 KBA3 9 17 ADB3
<26> XA3 HA3 A3 A3 D3
XD0 170 118 KBA4 8 18 ADB4
<26> XD0 HA4 A4 A4 D4 +5VALW
XD1 171 119 KBA5 7 19 ADB5
<26> XD1 HA5 A5 A5 D5
XD2 172 120 KBA6 6 20 ADB6
<26> XD2
<26> XD3
XD3 173
HA6
HA7
PC87570 A6
A7
121 KBA7 5
A6
A7
D6
D7
21 ADB7
1
XD4 174 122 KBA8 27
<26> XD4 HA8 A8 A8
XD5 3 123 KBA9 26 R130
<26> XD5 HA9 A9 A9
XD6 4 124 KBA10 23 1 KBA18 0_0402
<26> XD6 HA10 A10 A10 VPP
XD7 5 125 KBA11 25
<26> XD7 HA11 A11 A11
XA12 6 126 KBA12 4

<26> XA12 HA12 A12 A12
2
XA13 7 127 KBA13 28
<26> XA13 HA13 A13/BE0 A13 +5VBIOS
XD[0..7] XA14 8 128 KBA14 29
<26> XD[0..7] <26> XA14 HA14 A14/BE1 A14
XA15 9 129 KBA15 3
<26> XA15 HA15 A15/PG1/CBRD A15
1
XA16 10 130 KBA16 2
<26> XA16 PA3/HA16 A16/PA5/FXBUSEN A16
2
XA17 11 135 KBA17 30 32 + C239 C238
<26> XA17 PA4/HA17 A17/PA6 A17 VCC

XA18 12 136 KBA18
<26> XA18 PE0/HA18 A18/PE1/SHBM#
22 10UF_10V_1206 .1UF_0402
XD0 ADB0 CE#
1
15 137 24
XD1 HD0 D0 ADB1 OE#
16 138 31 16
XD2 HD1 D1 ADB2 WE# GND
17 139
XD3 HD2 D2 ADB3
<26> XSTB0# 18 140
XD4 HD3 D3 ADB4
19 141
1
XD5 HD4 D4 ADB5

20 142

R266 XD6 HD5 D5 ADB6 +5VALW
R381 21 143
10K_0402 XD7 HD6 D6 ADB7
1 2 +5VS 22 144
2 HD7 D7 2
100K_0402
2
13 111 FRD# R380
HAEN RD/HDEN FWR# +5VALW
2
<26> XIOCHRDY 14 112 1 2 +5VS

HIOCHRDY WR0# FSEL# R386
<26> XIOR# 158 105
HIOR# HRMS/SEL0#
2
2
G
+5VALW
G
159 100K_0402 100K_0402
<26> XIOW# HIOW# U43A
2 1 157 14 RP117
Q27 3 HMEMR# 1K_0402 R264 162 HMEMCS#/PA0 KSI0
1

<26> XMEMR# 1 36 1 1 3 1 8
2N7002 HMEMRD#/PA1 KBSIN0 EC_FLASH# <17>
S
HMEMW# 163 35 KSI1 FWE# 3 FRD# 2 7
S
2
HMEMWR#/PA2 KBSIN1
G
34 KSI2 2 FWR# Q40 SELIO# 3 6

KBSIN2 KSI3 2N7002 BKOFF#
<26> IRQ1 156 33 7 4 5
Q28 3 IRQ1 KBSIN3 KSI4
<26> XMEMW# 1 155 32
2N7002 IRQ8# KBSIN4
S
154 31 KSI5 74HCT32 8P4R_10K

<26> IRQ11 IRQ11 KBSIN5
153 30 KSI6
<26> IRQ12 IRQ12 KBSIN6
29 KSI7
KBSIN7
2 1 PFAIL# 79 56 KSO0
+5VALW R325 10K_0402 PFAIL# KBSOUT0
2 R253 1 51RST 164 55 KSO1
10K_0402 HMR KBSOUT1 KSO2
<7> EC_HPOWON 165 54 RP113
HPWRON KBSOUT2 KSO3 KBD_DATA
53 +5VS 10 1
KBSOUT3 KSO4 KBD_CLK
52 9 2
KBSOUT4 KSO5 TP_DATA
95 51 8 3

<7> EN_DFAN DA0 KBSOUT5
96 50 KSO6 PS2_DATA 7 4 TP_CLK
NC: 1,2,43,44,45,46,87,88,89,90,131,132,133,134,175,176
<34> IREF DA1 KBSOUT6
IREF: Charger current control <7> EN_DFAN2 97
DA2 KBSOUT7
49 KSO7 PS2_CLK 6 5
98 48 KSO8 +5VS
ADPREF: Adapter current <15> DAC_BRIG DA3 KBSOUT8 KSO9
47 10P8R_10K
control KBSOUT9
42 KSO10
KBSOUT10 KSO11
<34> BATT-OVP 81 41
VBATT ECAGND VBATT PD0/AD0 KBSOUT11 KSO12
1 2 82 40
3
BATT_CHGI
BATT_TEMP
C488
1
1
C492
C484
.01UF_0402
2
ECAGND
.01UF_0402
ECAGND
.01UF_0402
<16> SLP_S5#
<16> SLP_S3#
<14,16> SLP_S1#
LI/MH#
<33> BATT_TEMP
BATT_CHGI
BATT_TEMP
83
84
85
86
93
94

PD1/AD1
PD2/AD2
PD3/AD3
PD4/AD4
PD5/AD5
PD6/AD6
PD7/AD7
KBSOUT12
KBSOUT13
KBSOUT14
KBSOUT15
PSDAT1
PSCLK1
PSDAT2
39
38
37
57
58
59
KSO13
KSO14
KSO15
KBD_DATA
KBD_CLK
PS2_DATA
KBD_DATA <27>
KBD_CLK <27>
PS2_DATA <27>
FSEL#
KBA18
KBA15
KBA17
1
2
3
4
RP116
8P4R_10K
8
7
6
5
3

BATT-OVP 1 2 ECAGND 61 60 PS2_CLK
<30> CAPSLED# PC0 PSCLK2 PS2_CLK <27>
C477 .01UF_0402 62 69 TP_DATA
<30> SCRLED# PC1 PSDAT3/PC7 TP_DATA <27>
63 70 TP_CLK +5VALW
<30> NUMLED# PC2 PSCLK3/PC6 TP_CLK <27>
64
PC3/EXINT0 EC_THRM#
<7> FAN2_TACH 65 113
PC4/EXINT11 PG4/WR1#
1
68 106 G_RST# EC_THRM# <16> +3VALW
<23,27,31,36,37> SUSP# PC5/EXINT15 PG3/SEL1# G_RST#
107 R343
PG2/CLK LAN_DISABLE# <20>
+5VALW 110

PG0/SELIO SELIO# <29> 100K

<27> RING# 71
PB0/RING#
5
SMB_EC_CK1 72 U29
<5,7,15,29,33> SMB_EC_CK1 PB1/SCL
SMB_EC_DA1 G_RST#
2
<5,7,15,29,33> SMB_EC_DA1 73 104 PCM_SUSP# <21> 2
PB2/SDA PH0/BST0/ENV0
1
<15> INVT_PWM 74 103 KSO17 <30> 4

PB3/TA PH1/BST1/ENV1 ACOFF V_PRST# <21,22>
<7> FAN1_TACH 75 102 ACOFF <34> 1
R275 R272 G20 PB4/TB/EXINT10 PH2/BST2/TRIS 570_SMI# <5,8,15,16,20,21,26,27> PCIRST#
76 101
4.7K_0402 4.7K_0402 RCL# PB5/GA20 PH3/PFS EC_ON 7SH32
77 100 EC_ON <30>
PB6/HRSTO# PH4/PLI
<30> ON/OFF 78 99 SCI# <16>
PB7/SWIN PH5/ISE#
2
C397 1 R256 2
SMB_EC_DA1 1UF_25V_0805 @0_0402
SMB_EC_CK1 28 145
+RTCVCC VBAT D8/PF0
1 2 146 ADB[0..7]
+3VS D9/PF1 ADB[0..7] <29>
147 RP118
D10/PF2 VR_ON <31,32>
CRY1 25 148 570_SMI# 1 8 KBA[0..18]
32KX1/32CLKIN D11/PF3 FSTCHG <34> KBA[0..18] <29>
27 149 PCM_SUSP# 2 7
32KX2 D12/PF4 MUTE <24>
R232 150 KSO17 3 6 KSI[0..7]
D13/PF5 SYSON <31,33,37> KSI[0..7] <29,30>
2
2
1 2 CRY2 151 4 5
D14/PF6 ACIN <17,33,35>
R273 R309 152 KSO[0..15]
D15/PF7 BKOFF# <15> KSO[0..15] <29>
10K_0402 10K_0402 22M 8P4R_10K
GND
GND
GND
GND
GND
X1 R231
4 D23 4
2 1
1
1
1 G20 51K_0402
109
160
2
24
26
66
<16> GATEA20
1
C400 32.768KHZ C403 PC87570C4-176PIN

RB751V
D25 10PF_0402 33PF_0402
1 RCL#
2
<16> KBRST# 2
RB751V

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL 9
3
;
0.1

A B C D E
A B C D E
ADB[0..7]
<28> ADB[0..7]
KBA[0..18]
<28> KBA[0..18]
1 R342 2
+5VALW 100K_0402 Input Port
1 R353 2 Output Port
+5VALW 100K_0402
1 R360 2
+5VALW 100K_0402 +5VALW +5VALW
C530
1 R370 2 C514 1 2
1 +3VALW 100K_0402 1
1 2
.1UF_0402
R377 2 .1UF_0402
20
+3VS 1
100K_0402 U39
20
R328 U37 ADB0 3 2
VCC
<33,34> 6C/8C#/4C# D0 Q0 PWR_LED# <27>
2 1 2 18 ADB0 ADB1 4 5
VCC
<5> PROCHOT# 1A1 1Y1 D1 Q1 CHARGE_LED# <27>
0_0402 2 R321 1 4 16 ADB1 C510 ADB2 7 6
<5> THRM# 1A2 1Y2 D2 Q2 SWI# <16>
@0_0402 6 14 ADB2 1 2 ADB3 8 9
<19> FDD_PRES# 1A3 1Y3 +5VALW D3 Q3 LID_OUT# <16>
8 12 ADB3 ADB4 13 12
<20> LAN_PME# 1A4 1Y4 D4 Q4 PWRBTN_OUT# <16>
11 9 ADB4 .1UF_0402 ADB5 14 15
<27,30> LID_SW# 2A1 2Y1 U43B D5 Q5 VLBA# <16>
PCM_PME# 13 7 ADB5 ADB6 17 16
<21> PCM_PME# 2A2 2Y2 74HCT32 D6 Q6 BATT_LED# <27>
15 5 ADB6 14 ADB7 18 19
<15> ENABKL# 2A3 2Y3 D7 Q7 BEEP <24>
17 3 ADB7 KBA3 4
<33,34> AIR_ADP# 2A4 2Y4
6 AA 11
GND
SELIO# LARST# CLK
1 5 1
GND
1G CLR
19 7
+5VALW 2G
74HCT273
10
74HCT244
10
U43C
14 74HCT32 C531
KBA1 9 1 2 1 2
+5VALW
8 CC R356 20K_0402

SELIO# 10 1UF_25V_0805
<28> SELIO#
7
+3V
+5VALW
PCM_PME# 1 2 RP124
R358 100K_0402 AA 1 8

CC 2 7
BB 3 6
2 DD 2
4 5
+5VALW +5VALW
8P4R_100K
+5VALW
+5VALW
4
3
2
1
4
3
2
1
C549 C548

RP125 RP123 1 2 1 2
@8P4R_100K @8P4R_100K
20 @.1UF_0402 .1UF_0402
20
5
6
7
8
5
6
7
8
U41 U40
2 18 ADB0 ADB0 3 2
VCC
VCC
1A1 1Y1 D0 Q0 EC_AGPRST# <15>
4 16 ADB1 ADB1 4 5
1A2 1Y2 D1 Q1 SOS1# <20>
6 14 ADB2 ADB2 7 6
+5VALW 1A3 1Y3 D2 Q2 SOS5# <20>
8 12 ADB3 +5VALW ADB3 8 9
C550 1A4 1Y4 D3 Q3 EC_WAKEUP# <16>
11 9 ADB4 ADB4 13 12
2A1 2Y1 D4 Q4 CRT_ON# <15>
1 2 13 7 ADB5 ADB5 14 15
2A2 2Y2 ADB6 U43D ADB6 D5 Q5
15 5 17 16
2A3 2Y3 ADB7 74HCT32 ADB7 D6 Q6
17 3 14 18 19
5
@.1UF_0402 2A4 2Y4 KBA4 D7 Q7

12

KBA2 2 1 11 BB 11
GND
GND
DD 1G SELIO# LARST# CLK
4 19 13 1
SELIO# 2G CLR
1 7
@74HCT244 74HCT273
10
10
U42
3
@7SH32
<28> KSO[0..15]
KSO[0..15]
3

KSI[0..7]
<28,30> KSI[0..7]
KSI1 4 5
KSI7 3 6
INT_KBD CONN. KSI6 2 7 CP9 NM24C164 Address definition: 1 A2 A1# A0 B2 B1 B0 R/W#
KSO9 1 8 8P4C_220PF
KSI4 4 5 +5VALW

KSI5 3 6
KSO0 2 7 CP8 +5VALW
KSI4
KSI6
KSI1
1
KSI3
KSI2 1 8 8P4C_220PF
1 2
KSO10
KSO14
KSO12
KSO6
KSO7
KSO2
KSO1
KSO0
KSI3 4 5 C384 .1UF_0402 R247

KSO5 3 6 100K_0402
KSO1 CP7 U25
2 7
KSI0 8P4C_220PF
2
1 8 8 1
VCC A0
25
23
21
19
17
15
13
11
7 2
9
KSO2 WC A1
4 5 <5,7,15,28,33> SMB_EC_CK1 6 3
JP14 KSO4 SCL A2
3 6 5 4
Dummy
23
21
19
17
15
13
11
CP6 <5,7,15,28,33> SMB_EC_DA1 SDA GND

KSO7 2 7
INT_KB_CONN. KSO8 NM24C16
1 8 8P4C_220PF
24
22
20
18
16
14
12
10
KSO6 4 5 EC I2C Bus Address:

24
22
20
18
16
14
12
10
KSO3 3 6
KSO12 CP5
2 7 24C164: 1011xxx R/W#
KSO15
KSO11
KSO13
KSO3
KSO8
KSO4
KSO5
KSO9
KSO13 1 8 8P4C_220PF 24C16: 1010xxx R/W#

KSO14 4 5
KSI0
KSI2
KSI5
KSI7
4 KSO11 4
3 6
KSO10 2 7 CP4
KSO15 1 8
8P4C_220PF

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL 66<%*-1= %%5"*10
0.1

A B C D E
A B C D E
+5VALW
Power ON Circuit RTC Battery
1
+3VALW
BATT1 R329
+3VALW +3VALW 100K_0402 Power BTN
- +
1
2 1 RTCPWR
R359 D27
150K
2
U38A 1 ON/OFF
ON/OFF <28>
ON/OFFBTN#
14
14
3
74LVC14 RTCBATT 2 EC_ON# <36>
1
R350
2
2 1 1 2 3 4 D33 +5VALW
RSMRST# <16> DAN202U
1M_0402 1 U38B
1
1 C521 74LVC14 +RTCVCC 1
1
7
7
R373 R339 C500 D30
1
3
2
.1UF_0402 10K_0402 4.7K_0402
2
CHGRTC 1000PF_0402 RLZ20A
2
HSM126S
2
22K
2
EC_ON
2
<28> EC_ON 1 2 2
R322 22K
22K_0402
Q36
DTC124EK
3
+3V
WHEN R=0,Vbe=1.35V
WHEN R=33K,Vbe=0.8V
1
+3VALW +3VALW +3VALW

R344
10K_0402
14
14
1
2
14 U36A
R349 20K_0402

<32> VGATE 2 3 1 2 11 10 13 12 ITP_PWROK <7>
7 74LVC125 U38E U38F
2
74LVC14 74LVC14
7
C506
1
D 1UF_0805_X7R
Q34
1

<31> VR_ON#
G
@2N7002
S
2 +3V 2
3
USB_AS USB_A
USB Port 0
1
L34 4516
R357 1 2 W=40mils
10K_0402 FBM-11-451616-800T
4
U36B

2
R351 0_0402 C11 + C162 C13
2
5 6 1 2 ICH_VGATE <16>
.1UF_0402 150UF_10V_E 1000PF_0402
1
74LVC125 1 2 +3VS
R395 10K_0402
L14 JP4
CK408_PWRGD# <14>
FBM-11-160808-121 1
R396 10K_0402 Q43 USBP0- USB0D- VCC
1 <17> USBP0- 1 2 2
USBP0+ USB0D+ D-
1 2 2 <17> USBP0+ 1 2 3
FBM-11-160808-121 D+
3 4
L13 GND
2
C555 3904 USB_CONN

C12 @150PF_0402

100PF_0402 USB0D- 1 2
1
USB0D+ 1 2
+5V USB_AS USB_BS +3V
USB Over Current C10 @150PF_0402
'()*
)'+,*
-+
01
)+..*)-+/
1
3
W=40mils R75
100K_0402
R72
100K_0402
3
2
U8
1 8 1 2 OVCUR#0
GND OC1# OVCUR#0 <17>
2 7 R74 47K_0402
IN OUT1
3 6
1
EN1# OUT2

C163 4 5 1 2 OVCUR#2
EN2# OC2# R76 47K_0402
1
OVCUR#2 <17>
USB_BS USB_B
USB Port 1
1
.1UF_0402 TPS2042 C158 C159
2
L35 4516
.1UF_0402 .1UF_0402 1 2 W=40mils
2
2
FBM-11-451616-800T
Note:
2
C154 + C161 C157

USB_AS=USB_BS=Trace width=40mils
.1UF_0402 150UF_10V_E 1000PF_0402
1
L32 JP3
FBM-11-160808-121 1
LID Switch & Function Button USBP2- 1 2 USB2D- 2
VCC
<17> USBP2- D-
USBP2+ 1 2 USB2D+ 3
<17> USBP2+ D+
FBM-11-160808-121 4
L33 GND
USB_CONN
C155 @150PF_0402
USB2D- 1 2
JP11 USB2D+ 1 2
<24> INT_MIC- 1 2 INT_MIC+ <24>
C156 @150PF_0402
3 4
<28,29> KSI3 5 6 KSI2 <28,29> '()*
)'+,*
-+
01
)+..*)-+/
<28,29> KSI1 7 8 KSI0 <28,29>
4
<28> KSO17 9 10 SCRLED# <28> 4
<28> CAPSLED# 11 12 NUMLED# <28>
<27,29> LID_SW# ON/OFFBTN#
13 14
+5VS 15 16 +5VS
SUYIN 12750AR-16G2T-9

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL 1=-/$-/#'-&0 %%5"0
0.1

A B C D E
A B C D E
+12VALW +12VALW
+5VALW to +5V Transfer
1
R175
100K_0402 +CPU_CORE R55
+3VALW
47K_0402
+5VALW
1
2
+5V
U20 R340 R316
2
1
2
8 1 @100K_0402 SYSON#
1
1
D C355 D S @330
7 2
D S
1
SYSON# R174 D
2 6 3
D S
1
1 .01UF_0402 C360 R164 1
2
G 5 4 C361 2 Q6
D G <28,33,37> SYSON
Q21 1M_0402
2
S 470_0402 G 2N7002
1
D
3
1
2N7002 SI4800 10UF_10V_1206 .1UF_0402 S
SUSON
2
VR_ON#
3
<30> VR_ON# 2
1
12
G
D Q29 Q25
S
2 SYSON#
3
@2N7002
G @SMO5
1
+5VALW +5VALW D
S
3
Q18 VR_ON 2
<28,32> VR_ON
2N7002
3
G
1
S Q33
3
C368 + C362 @2N7002
33UF_D2_16V +12VALW
4.7UF_10V_P 2
1
R352
10K_0402
2

+3VALW to +3V Transfer 1.8VALW/+1.5VS Power direct provide <23> SUSP
1
D
+3VALW
+3V 2 Q37
<23,27,28,36,37> SUSP#
G 2N7002
U11 S

3
8 1
D S
7 2
D S
1
2 2
6 3
D S
1
5 4 C230 C228 R121

D G 470_0402
1
SI4800 22UF_10V_1206 .1UF_0402

1
C232 C234
2
+
100UF_D_16V
2
6.3V 10UF_6.3V_P

1
D
2
2 SYSON#
SUSON G
S Q12
3
2N7002
+5VALW to +5VS Transfer

+12VALW
1
+5VALW +5VS
R378
100K_0402 U44 SI4800
8
7
D
D
S
S
1
2
+1.8VALW +1.8VS
+1.8VALW to +1.8VS Transfer
1
U27 SI4800
2
6 3
D S R354
5 4 8 1
1
D G
1
3 C554 470_0402 D S 3
C553 7 2
1
D S
1
D C552 C428 C422
6 3
SUSP RUNON .1UF_0402 22UF_10V_1206 D S R251
2 5 4
D G
2
G R393 .1UF_0402 470_0402

1

Q42 1M_0402
2
.01UF_0402
2
22UF_10V_1206
2
S
2N7002
3
Q38 C395
10UF_6.3V_P
2
1
D
2
Q24
1
D
2 SUSP 2N7002
+5VALW +5VALW G RUNON 2 SUSP
S G
3
2N7002 S

1
C515
3
+ C551
4.7UF_10V_P 100UF_D_16V
2
+3VALW +3VS
+3VALW to +3VS Transfer
U13 SI4800
8 1
D S
7 2
D S
1
6 3 C240 C237
D S R132
5 4
1
D G .1UF_0402 470_0402
1
4 C235 4
2
22UF_10V_1206
2
+
100UF_D_16V C233
10UF_6.3V_P
2
2
Q16
1
D 2N7002
RUNON 2 SUSP
G
S

3
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL -
0.1

A B C D E
A B C D E
PR30 PM_GMUXSEL <16> DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
+3VALWP 0
CPU-CORE
2
PQ37 2N7002 B+ B++
3 1 PL1
4.7UF_1210_25V
2
0.1UF_0805_25V
PR26 KC-FBM-L11-322513-201LMAT PC8 4.7UF_1210_25V
PC12
2 1
2200PF
1 30K 1
PC11
PC6 PC7 PC9 PC10
PR27 4.7UF_1210_25V 4.7UF_1210_25V
1
4.7UF_1210_25V
1
2
2
PQ36 9.31K_1%
PR28
2
5
6
7
8
5
6
7
8
12.7K_1% PR8
2 1
2N7002 +3VALWP 10
3
1
1
+5VALWP 4 4
PQ35 PR6
1 2 PQ1
2N7002 0 PQ2
2
2
PC42 IR7811A IR7811A
1UF_0805 PD1 PC13 +CPU_CORE

16> PM_STPCPU# RB051L-40 PL2
3
PR29 PU1 SC1474 PR10 220UF_D2_4V_25m
3
2
1
3
2
1
HK-AE26A0R6
30.1K_1% VTTLX
1
38 V5_1 DRN1 1 2 1

20 2 1 2 1mR
V5_2 TG1
1
+1.8VALWP 0 PR14 PC19
2
PC23 PC25 3 1 2 PC15 PQ3 +

BST1
5
6
7
8
1 PR16 1UF_0805 SI4362DY PQ4 4.7UF_0805_10V
5
6
7
8
4.7UF_0805_10V 36 37 SI4362DY PD2
PGND1 BG1 EC31QS04
2
22 34 4

PC41 PQ38 PGND2 ISH1
4
2 3 CL1 33 2
10UF_1206_6.3V 2 4.7UF_0805_10V
1 CMP1 32
CLRF 31
2SA1036K
3
2
1
3
2
1
4 30

+1.2VP VIDFB VCCA
PC32 5 29
PC30 + VIDB CMPRF
7 25 PR1
0.1U_16V 22UF_B_6.3V OSB GND PR31 2 1
8 24 2 1 PR2
HYS DAC 10K
2 1
23 PC1 619_1%
CORE PC2 PR3 332_1%
15 1000PF 2 1
PR7 0 SS PR4
2 1 10 35 330PF 475_1% 2 1
<6> CPU_VID4 PR9 0 VID4 EN PR5

2 1 11 16 2 1 475_1%
<6> CPU_VID3 VID3 PWRGD
PR11 0 PR19
2 1 12 19 392_1%
<6> CPU_VID2 VID2 DRN2
PR12 0 PC24
2 1 13 18 PC26 PC4 PC5 PC20 1K
<6> CPU_VID1 PR15 0 VID1 TG2 PR17 10K
PC29 PR32
3
<6> CPU_VID0
<6,16> PM_DPRSLPVR
2 1 14
6
VID0
DPRSL
BST2
BG2
ISH2
CL2
17
21
26
27
0.01U_50V 330PF 180PF 180PF
PC3
330PF
0.1UF_0805_25V
B++
1
PR21
PR20
2
332_1%
2
475_1%
1
1
2 330PF
@0
OUTPUT VOLTS 3

9 VDPR CMP2 28
PC18
PR25
5
6
7
8
5
6
7
8
PC21 0.1UF_0805_25V
20K_1%
2
PR42 0 180PF
1 2 PR40 4 4

<28,31> VR_ON
1 PQ6
PQ7
PC22 +3VALWP IR7811A IR7811A
1
+5VALWP
1
PR39 PL3
0.01U_50V PR24 PD4 PC31 PR36 +CPU_CORE
3
2
1
3
2
1
1 2
PR23 HK-AE26A0R6
<30> VGATE 32.4K_1% 10K 2 1 0 2 1
1mR
2
1
RB051L-40 1UF_0805 PC14
PQ8 PC16 +
5
6
7
8
SI4362DY PQ9 220UF_D2_4V_25m
5
6
7
8
SI4362DY PD3
EC31QS04 4.7UF_0805_10V
2
4
4 4 4
B++ A1 CPU Silicon set DSoff =1.2V

4.7UF_1210_25V 4.7UF_1210_25V
PR25=13.3K,PR24=39.2K
0.1UF_0805_25V
A2 CPU Silicon set DSoff =1.0V

1
PC39
3
2
1
PR25=20K,PR24=32.4K Compal Electronics, Ltd.

2200PF
PC38
PC33 PC34 PC35 PC36 PC37

3
2
1
4.7UF_1210_25V For A1,A2 CPU Silicon stepping Title
2
PQ37 is pop and PR27=9.31K CPU VCORE

4.7UF_1210_25V 4.7UF_1210_25V For B0 CPU Silicon stepping Size Document Number Rev
ADY13 LA-1271 0.1
PQ37 is pop and PR27=37.4K
A B C D E
A B C D E
+5VALWP Detector
1
PR43
100K_0402
+5VALWP
2
AIR_ADP# <29,34> BATT+
1
PR161
PQ11 BATT++
BATT+
1 DTC115EUA 100K 1
100K
2
PL5
100K 1 2 BATT++
3
FBM-L11-453215-900LMAT PR162
1
VIN 6C/8C#/4C# <29,34>
PCN1 PR163 1K_1%
RP34-8RD-3PDL2J PC45 PC46 PL6 PC44
100PF 1000PF
2
PC43
2
0.1UF_0805_25V @1K_1%
3 ADPIN 1 2 0.1UF_0805_25V
VIN
1
1 GND FBM-L11-453215-900LMAT
PR44
AIR_ADP 2 10_1206
1
PR45
@EC10QS04
1
1K
PD5
4
5
6
7
PC47
12
1 2 BATT_TEMP
BATT_TEMP <28>
2
100PF
1
2
PZD1 PCN2

PL7 RLZ24B BTC-07GR1 7P PD6
ADPGND1 1 @BAS40-04
2
2
2
FBM-L11-453215-900LMAT 3
4
2
PC48
1000PF 5
6

7
2
PCN3 PR47
@2DC-0007B200 1 2
2 PR46 +5VALWP 2
1
1 ADPIN 1K 6.49K_1%
1
2 ADPGND PR48
100
2 SMB_EC_DA1 <5,7,15,28,29>

1 2
1
PR49 100
PCN2 battery connector pin assignment 2 1
<5,7,15,28,29> SMB_EC_CK1 PD7
@BAS40-04

2

PD8
@BAS40-04 +5VALWP

3

PR51
+5VALWP 1M_1%
!" +5VP 1 2 2 1
VS
B+
PR50
100K
1

1
PC52 PR52
0.01UF 499K_1%
2
PD9
8
3 PU5A 3
2
RB751V
+ 3
2 1 1
<5,35> SHDN#
Vin Detector - 2
1

PD10
1
17.93V/17.2V LM393A PR53
0.1UF_16V
RB751V
1
PC51
PC50
4
PR54 499K_1% PC49
2 1 10K PR55 1000PF
<34> ACON
2
215K_1%
PR56 1000PF
2
1M_1%
2
1 2

VIN RTCVREF
VIN
1
1
PR59
PR58 10k PR60
PR57 10K 1 2 47K PACIN <34>
84.5K_1% PU5B ACIN <17,28,35>
2 2 1 PACIN
PR61 LM393A PQ12
Precharge detector 2N7002
2
22K
2
15.9V/13.2V FOR
3
1 2 5 +
7
PACIN <34>
1
6 - ADAPTOR
1
1
PC53 PR62
1000PF 20K_1% PC54 PZD2 PR63
100K
0.1UF_16V RLZ5.1B 10K 2 SYSON
2
PQ13
2
DTC115EUA
100K
2
SYSON <28,31,37>
4 4
3
2 1 RTCVREF
PR64
10K

Title
0.1

A B C D E
A B C D E
Iadp=0~3.22A <-----Actually about 3A Charger

Iair=0~2.26A
B+++
P3 B+
P2
PQ14 PQ15 PR65 PL8 PC55 PC56 PC57 PQ16
SI4835DY SI4835DY 0.02_2010_1% 4.7UF_1210_25V 4.7UF_1210_25V 0.1UF_0805_25V SI4835DY
VIN 8 1 1 8 2 1 1 2 1 8
7 2 2 7 2 7
1
6 3 3 6 FBM-L11-322513-151LMAT 3 6
1
5 5 5
1
1 1
PR66
2
PC58
4
200K_0402 2200PF PR67
47K
1 2
3
2
1
VIN
2
1
2
PD11
PR69 4 PR70
1SS355
PR68 PU6 0
ACOFF# 150K_0402 MB3878 PQ17 10K
1 2
1 24 FDS4435
-INC2 +INC2
1
ACOFF#
1
PR72 1 2 1 2 23 PC59
47K_0402 D PR75 PR74 PC61 OUTC2 GND
5
6
7
8
2200PF
1 2 2 10K_1% 21K_1% .01UF_0402_16V PR71

<33> PACIN
G 100K 3 22 1 2
+INE2 CS 100K
S PQ19 2
ACOFF <28>
3
2N7002
1
ACON 4 21 1 2
<33> ACON -INE2 VCC(o)
1
100K PQ18

PR73 PC60 DTC115EUA
15.8K_1%
2
0.1UF_0805_25V
3
1 2 1 2 5 20
PQ20 FB2 OUT PC63
PR77
31
TP0610T PC64
2
PC62 PR76 0.1UF_16V
47K
2
0.1UF_16V 4700PF 10K 6 19 1 2 LXCHRG
VREF VH PC66
1 2 2
2
1
<29,33> AIR_ADP# 0.1UF_0805_25V
1
1
PR78 1 2 1 2 7 18 1 2

@ PC67 PR80 FB1 VCC PL9 PR82
1000PF
2
@30.1K_1% PC65 PR79 15UH_SPC-1205PA 0.02_2512_1% BATT+
2 FSTCHG <28> 2
2
2200PF 1K 8 17 1 2 1 2 1 2 BATT+
-INE1 RT
1
2
PC72 PR81
1 2 .01UF_0402_16V 9 16 66.5K_1%
4.7UF_1210_25V
4.7UF_1210_25V
+INE1 -INE3
1
<28> IREF PD13
68UF_EC_25V
1
EA60QC04
PC68
PC70
PC71
PR83 +
1
100K_1%

2 1 10 15 1 2 1 2
OUTC1 FB3
1
IREF=1.746*Icharge PR86 PR84 PR85 PC69
2
40.2K_1% 10K 330K 1500PF
IREF=0~5V 11
OUTD CTL
14
2
3
1
2
1 2
12 13 PR87
-INC1 +INC1 10K
PC73
10PF
2

2 1 2 1
3
BATT++ PQ40
3 1
PR88
152K_0.1%
PR164
305K_0.1%
PR89
309K_0.1%
1 2
Charge voltage
3
1
2N7002 PR165 PC74

4S LI-ION

PR90
2
22PF
205K_1% +5VP
100K
NI-MH : 17.00V
1
2
PQ41
3S LI-ION : 12.75V
PC154 DTC115EK
100K
1
2 6C/8C#/4C# <29,33>

PR91 0.1UF
300K_0.5%
100K
2
PU7A
8
LM358
+ 3
1
<28> BATT-OVP - 2
4
1
PR92
1
PR93 PC76
2.2K 143K_0.5% 0.01UF
PC75
2
0.1UF_16V
2
4 4
OVP voltage :
LI-4S :18.3V----BATT-OVP=4.04V

Title
LI-3S :13.5V----BATT-OVP=3.82V THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
BATT-OVP=0.2206*BATT++ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE

0.1
A B C D E
A B C D E
+3.3V/+5V/+12V
B+
1 1
PL10
FBM-L11-322513-151LMAT
PC77
1
2.2UF_1206_25V
1 2
1
470PF_0805_100V
2
PC79
DAP202U PD14
PC78
0.1UF_0805_25V PD15 PR94 EC11FS2
BST31 BST51
1
1 2 22_1206
B++++
3
SNB 1 FLYBACK
2
2
4 2
8
7
6
5
0.1UF_0805_25V
4.7UF_1210_25V
4.7UF_1210_25V
VL
PC84
1
1
2200PF
PQ21 VS
1
0.1UF_0805_25V 1 3
PC82
PC83
PC80
PC81
SI4800DY PR95 1 2

0_0402 PT1
4.7UF_1206_10V
2
4 DH31 1 2 B++++ PQ22 SDT-1205P-100
1
SI4800DY
0.1UF_16V
1
2
PR96 PR97
PC85
PC86
0_0402 10_1206 +12VALWP
5
6
7
8
4.7UF_1210_25V
0.1UF_0805_25V
4.7UF_1210_25V
1
2
3
LX3
1
2
PC89
PC90

2200PF
8
7
6
5
PC88
PC87
0.1UF_0805_25V
+3.3V Ipeak = 6.66A ~ 10A
0.1UF_0805_25V
4.7UF_1210_25V
1
2 2
2
47PF_0402 PQ23 PR98 4
1
PC91
SI4810DY 0_0402
PC92
1
PC93
1
DH3
DL3
1
4
PC94
2
1
2
3
2
1
PL11 PC95
SLF12565T-100M @1000PF DH51

1 2
5
6
7
8
1
2
3
PR99
1
2
0_0402 PQ24 PC96
22
21
SI4810DY 47PF_0402
25 4
V+
VL
2
BST3 12OUT DL5
2
5 4
VDD CSH5
27 18
DH3 BST5
1
1
PU8 16
PR100 DH5 PC97
26 17
LX3 LX5
1
+3VALWP PR101 1M_0402 24 19 @1000PF
DL3 DL5
1
0.012_2512_1%
1
3
2
1
20
PGND PR102 PR103
14
CSH5
2
CSH3 1 13 2M_0402 0.012_2512_1%

CSH3 CSL5
2 12

CSL3 MAX1632 FB5
2
3 15
150UF_D_6.3V_FP
150UF_D_6.3V_FP
FB3 SEQ
2
<17,28,33> ACIN 1 2 10 9 2.5VREF
1
SKIP# REF
23 6
SHDN# SYNC
1
1
PC98
+ + PR105 PR104
PC99
11
RST#
1
10K_0402 7
3.57K_1% PC102 TIME/ON5 PC103 CSL5 +5VALWP
2
100PF_0402 PR106 28 4.7UF_1206_10V

GND
RUN/ON3
2
@300K_0402
2
2
150UF_D_6.3V_FP
+5VALWP
1
1
150UF_D_6.3V_FP
1
PC106
PD16 PC109 PC104 +
8
1 2 1 2 PR109 PD17
VL
2
+5VP
PC105
3 EP10QY03 @.01UF_0402 10.2K_0402_1% PC108 EP10QY03 + 3
1
10K_0402
PR110
2
680PF_0402 PR107 PR108 100PF_0402
1
PR111
@0 @0_0402 0_0402
2
1
2
PR112

2
PR113 @100K_0402
1
1
47K_0402
1
PR114 PC110
1
NC_TEST2
2
PR115
2
1 2 POK @100PF_0402
10K_0402_1%
PR116 @0
2
1
VL PC111 VL PD18
2
2 1

@RB751V
0.047UF_16V
2
47K_0402_1%
+5V Ipeak = 6.66A ~ 10A
PR118 NC_TEST1
PR117 47K_1%
2.15K_1%
PR119 PU9A
16.9K_1%
8
LM393A
3 +
1
SHDN# <5,33>
2 -
1
4
PR166 PC112
PR167 0.047UF_16V
2
10K_1%_0805
4 PR120 4
1
PC113 100K_1% VL
1UF_0805_25V
1000PF
PH1
@ @
2
PC114
CPU thermal protection at 85 degree C

PR121
100K_1%
Recovery at 45 degree C
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL >5)->3)-> )
0.1

A B C D E
A B C D E
+1.8VALW/+1.5VS
+1.8V+-5%
+1.8VALWP PQ25
+1.5VS+-5%
PQ26 SI3442DV
+5VALWP SI3445DV PL12
D
5UH_SPC_06704-5R0A 6
S
D
6 LX18 2 1 5 4
S
+1.8VALWP +1.5VSP
4 5 2
1 2 1 1
4.7UF_1206_25V
0.1UF_16V
1
1
VS
PC147
1
G
2
1
+ PC115
PR124
G
5.1K
PR123
RB051L-40
PC117
+ PC116
0
150UF_D_6.3V_KO
PD20
1
1
PD19 PQ27
2
PR122 PC148 150UF_D_6.3V_KO
0.1UF_16V
PC118 RB751V PR126 2SC2411K
2
1
4.7UF_1206_25V 1K PR125 10K 470PF
1
1
PC119
1
220PF
2
2
10K
PC120
1 2 2
3 PR127
2
1M
2
1
VL
PC121 PU7B PR128
2
2200PF 200K_1%
LM358
2
5 2 1 2.5VREF
0.1UF_16V
+ 2.5VREF <35>
PC122
7
6 +5VALWP
-
2

0.01UF
300K_0.5%
PR129
2
PU9B
8
PQ29
2
LM393A
PC123
PC124
1
3 5 PR131 PR132 DTC115EK
100K
+ 68PF
PR130
PQ28 2 7 38.3K_1% 5.1K
2SA1036K 1
1
- 6 2 1 2.5VREF 1 2

100K
1
2 PQ30
1
4
1
PC125 PR133 DTC115EK
0.01UF 100K_1% 100K
3
100K
2
2

SUSP# <23,27,28,31,37>
2 100K 2
3

PR134
200_1206
1 2
PD22 VS1
PD21 RLS4148
PR135 2 1
RLS4148
200_1206
2 1 1 2
VIN
1
PD23 VS
RLS4148 PR136 PR137 PR138 PR33

PJP2
1.5K_1206 1.5K_1206 1.5K_1206 1.5K_1206
BATT+ 2 1 4MM
1 2
PQ31 +2.5VP +2.5V
2
TP0610T +5VP
PR140
PJP3
10K B+
3
2
PR139
200_0805
1 2
PZD3
RLZ4.3B
1 3 1 1 2
+1.5VSP 1
2MM
2
+1.5VS
3
2
PJP4
1
0.22UF_1206_25V
3MM
1
1
PC126
PR141 PC127 PR142 PZD4 1 2

+5VALWP +5VALW

100K 0.1UF_0805_25V 150K RLZ5.1B
2
PJP5
2
3MM
1 2
+3VALWP +3VALW
1 2

<30> EC_ON# PC128

PJP6
PR143 0.1UF_16V
22K 2MM
1 2
+12VALWP +12VALW
RTCVREF PJP7
PU10
S-81233SG 3MM
PR144 PR34 1 2 +1.8VALW
+1.8VALWP
200 200
CHGRTCP 2 3 1 2 1 2 CHGRTC
IN OUT
PJP8
1
GND PC129
1
PZD5 4.7UF_1206_25V 3MM

RLZ16B PC130
1
1 2 +1.25V
+1.25VP
1UF_0805_25V
2
2
4 4
2

Title
>59)?
Size Document Number Rev

0.1

A B C D E
A B C D
0_0805 PR145
+5VALW 2 1 PC131 PC132 PC133 PL16
0.1UF_0805_25V 4.7UF_1210_25V 4.7UF_1210_25V
2.5_B+ 1 2 B+
1 PD24 1
5
6
7
8
1SS355 FBM-L11-322513-151LMAT
PC134 PQ32
D
D
D
D
2
PR147 10 4.7UF_1206_16V
SI4800DY
PU11
G
S
S
S
PC135 15 14 0.1UF_0805_25V
4.7UF_1206_16V VCC VDD PR35 PL14
(+2.5V : I_peak =8.5A)
4
3
2
1
18 19 4.7UH_SPC-1205P-100
SKIP BST 0 +2.5VP
17 1 2.5DH PC136 PR148 0
8
7
6
5
V+ DH
10 20 2.5VLX PQ33
D
D
D
D
PR149 0 PGOOD LX
SI4810 PC149
<28,31,33> SYSON 3 13 2.5DL + + PR150
SHDN DL
15K_1%
G
S
S
S
6 12 47UF_D_6.3V
ILIM PGND PC137 PR37
1
2
3
4
2 11 150UF_D_6.3V NC_TEST3
N/C N/C
1 2 7 9 PR152 @0

REF N/C 10K_1%
PR151 16 5
1
15K TON OUT

PR153 8 4 FB
84.5K AGND FB
MAX1714A
PC140

2
PC138 PC139 @1UF_0805_16V

2 0.1UF_16V @150PF_50V 2
+2.5VP

VS
1
PR159
+2.5VP
0.1UF_16V
100K_0.5%
PC151
2
PR154
10
2
2 1 1 VCC1 VCC2 16
SDREF
1
PD26
1
8
PC141
0.1UF_16V
2 PVDD1 PVDD2 15
@EP10QY03
+1.25V 7
+ 5
PL15
2
+1.25VP
5UH_SPC_06704-5R0A - 6
2
1
3 PU12 14 2 1 LM358
VL1 VL2
4
PU13B
3 CM8500 3
1
1
2
4.7UF_1206_16V PD25 PC142 PC153
1
1
PR157 4 13 220UF_D_4V_FP PC150 @0.1UF_16V PR160 PC152
1
PC144 PGND1 PGND2 @EP10QY03 PR155 + + 100K_0.5% 0.01UF

PC143

100K 1K @220UF_D_4V_FP
1 2 2 1
2
2
5 AGND1 AGND2 12
2
1000PF
PR156
PQ39 100K
6 11 2 1

2N7002 SD VFB
1
PR158
1
PR38
7 VIN/2 VCCQ 10 +2.5VP
2
1
8
,36> SUSP# @10K @0 PC145
1000PF PC146 + 3
3
NC_TEST4 8 9 0.1UF_16V 1
AGSEN AGND
2
- 2
LM358
4
PU13A
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY

COMPAL ELECTRONICS, INC
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE DDR POWER 2.5V & 1.25V
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number Rev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY B ADY13 LA-1271 0.1
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC. Date: Monday, September 10, 2001 Sheet 37 of 37
A B C D
www.s-manuals.com

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A B C D E

Mosaic Schematics Document

Date: Wednesday, September 19, 2001 Sheet 1 of 37

Compal confidential Block Diagram

""#  page 28 ) )

&)## 12" ""

Date: Wednesday, September 19, 2001 Sheet 2 of 37

Power Managment table

State +1.8VALW +2.5V +1.2VP

RJ45 YES YES

Compal Electronics, Inc.

HA#6 K1 A25 HD#3

DEFER# D#62 HD#63

Date: Monday, September 10, 2001 Sheet 4 of 37

<8> H_DBSY# H5 AA20

AD26 AD22 H_VSSA

2. Place decoupling cap 220PF near CPU.(Within 1K_0402 R382

H_THERMDA Trace width>=7mila

Date: Monday, September 10, 2001 Sheet 5 of 37

Layout note : Layout note :

Please place these cap in the socket cavity area

C59 C67 C77 C210 C214

CPU Voltage ID R42 0_0402

+CPU_CORE  10K_0402 8P4R_10K

PM_GMUXSEL = 0 : for low Voltage A-C 1 24

C187 C197 C205 C213

EMI Clip PAD for CPU

Date: Monday, September 10, 2001 Sheet 6 of 37

D13 C131 1 D9 C160 1

Layout note : HA#24 M5 AF3 HD#21 AGP_AD21 AA27 AGP_SBA[0..7] .01UF_0402

R35 C58 H_SWNG1 AD13 A7 J6

301_1% .01UF_0402 +V_MCH_GTLREF A11 J22 Layout note :

Y8 49.9_1% 2. Place capacitors near MCH.

BROOKDALE(MCH-M) R27 C42 C69 301_1% @470PF

100_1% RP20 @8P4R_8.2K

H_DSTBN#[0..3] RP21 @8P4R_8.2K

2. Place decoupling cap 220PF near MCH pin.(Within RP22 @8P4R_8.2K

AGP_RBF# 3 6 R_D 301_1% C196

2 1 2 1 0=System memory is DDR R15 @6.2K_0402

Date: Monday, September 10, 2001 Sheet 8 of 37

C1 DDR_SDQ26 C19 G10

H10 AA4 DDR_SDQ43 E8 G18 DDR_SMA3

Date: Monday, September 10, 2001 Sheet 9 of 37

Layout note : DDR Memory interface

.1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R

.1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R .1UF_0402_X5R

Distribute as close as possible

C26 C50 C54 C43 C52 C53

C65 C64 + C176

Layout note : Hub-Link

C60 C68 C62 C66

Compal Electronics, Inc.

+2.5V +2.5V DDR_DQ[0..63]

RP44 4P2R_22 DDR_DQ54 DQS6 DM6 DDR_DQ50

Date: Monday, September 10, 2001 Sheet 11 of 37

DDR_DQ9 2 3 3 2 DDR_F_CB6 4 1 DDR_DQ57 51 52 4 1 DDR_SMA6

DDR_DQ50 DQS6 DM6 DDR_DQ54 +1.25V

PAD7 PAD8 PAD11 PAD12 PAD19 PAD14 PAD16 PAD18

Date: Monday, September 10, 2001 Sheet 12 of 37

C290 C289 C288 C287

Date: Wednesday, September 19, 2001 Sheet 13 of 37

+3VS L21 +3V_CLK

to CK_TITAN 14.318MHZ C393 C396

""# page 28 ) )

&)## 12" ""

+CPU_CORE 10K_0402 8P4R_10K

HUB_PD0 HUB_PD1 1 Q32

R297 C468 R_L

+5VS Q23

53 54 S1_BVD2 S1_REG# <21>