NM-A451 (ThinkPad P50) BP500

5 4 3 2 1
DDR4 / 1.2V PCB Layer Stackup

LCD CONN
eDP 15.6"
eDPx4
eDP
Mux
eDPx4 Channel A UNBUFFERED UNBUFFERED
Walter-Note Block Diagram L1:TOP
L2:GND1
FHD/QFHD 42 41 DDR4 2133MHz DDR4 DDR4 Project Code: L3:Signal 1
CPU
SM Bus_B
SO-DIMMA1
27
SO-DIMMA2
28
2014 July ' 10 L4:GND 2
HDMI Conn. SPI Flash TBT eDPx4 PCB(Raw Card): L5:Signal 2
45 4Mbits (U?) ? Intel L6:GND3
Channel B UNBUFFERED UNBUFFERED
PEG-16X Skylake_H DDR4 2133MHz DDR4 DDR4 Wireless LAN Wireless WAN L7:VCC1
D dGPU GEN3 Antenna Antenna L8:Signal 3 D
SO-DIMMB1 SO-DIMMB2
NVIDIA BGA1440
SM Bus_B 29 30 L9:VCC2
DPx4 N16P-Q1 L10:Signal 4
Thunderbolt 45W
TBT-PWR SW N16P-Q3 L11:GND4
/USB Type-C CPU XDP (M.2 WLAN Card) (M.2 WWAN Card) L12:BOTTOM
52 N16S 24
(port 1) 3,4,5,6,7,8,9,
46-51 31-38 10,11,12,13 Bluetooth Battery Charger
61 61
BQ24780SRUYR 88
PCI Express x4
Mini DisplayPort DMI x4 Type-A M.2 Card Type-B M.2 Card INPUTS OUTPUTS
44
DP Mux PECI3.0
DisplayPort DOCK_PWR20_F M-BAT-PWR
(Docking) 71 43
SIM Card
USB Port 3 Slot 61 USB System DC/DC
USB3.0 Back SM Bus
CONN (USB1) 54
USB2.0 CH02
USB3.0 CH02
PCH Port 14 (X1) Port 3
TPS51285BRUKR 90
C-Link
USB3.0 Back VINT20 VCC5M
USB2.0 CH01 USB x 12 ports 16 M.2 SLOT M.2 SLOT VCC3M
C
AOU (USB2) 54 USB3.0 CH01 Intel SSD 60 SSD 60 C
SATA x? CPU DC/DC

USB2.0 M.2 USB2.0 CH03
HDD CONN CH0 11
Skylake-H Port 11 Port 19 M: NCP81205MNTXG 91
WWAN Slot 61 USB3.0 CH03 SSD ? (X1) (X1) S: NCP81382MNTXG 92,93,94

vPro PCI Express x7 ports VINT20
VCCCPUCORE
VCCGFXCORE_I
Thunderbolt VCCSA
USB3.0 USB2.0 CH04
M.2 SLOT CH?
Docking 74 USB3.0 CH04 SSD 60 Port 13 Port 1 Port 4 VCCCPUIO
HDA (X1) (X1) (X1) NB681AGD-Z 95
USB3.0 Right M.2 SLOT
USB2.0 CH05 CH?
CONN (USB3) 55 USB3.0 CH05 SSD 60 VINT20 VCCCPUIO
Right
SPI Flash VCC1R0_SUS
USB3.0 USB2.0 CH06 64Mbits ALC3268 HDA Multi-Media Express
CONN (USB4) 55 USB3.0 CH06 CODEC Controller Card Slot Intel GbE PHY SN1409027RVER 96
(SPI1) 26 JACKSONVILLE
RTS5250s
USB2.0 M.2 14,15,16,17,18 VCC5M VCC1R0_SUS
USB2.0 CH14 RTC Battery 25 19,20,21,22,23 SPI Flash Stereo 67 62 64 56
WLAN Slot (BT) 61 VCC1R2A/VCC0R6B
32Mbits Speaker
(SPI2) 26 +SMDDR_VREF_DIMM
USB3.0 2D/3D 69
USB2.0 CH08 I2C TPS51716RUKR 99
Camera 40 USB3.0 CH08
LPC Bus 33MHz LAN +SMDDR_VREF_DIMM

B VINT20 VCC0R6B B
USB2.0 USB2.0 CH10
CPU FAN MUX VCC1R2A
Touch Panel 78 GPU GAN 80
Microphone Audio Internal SD/MMC 57
Docking
Headphone (Docking) Mic Card Slot
USB2.0 68,69 71 42 63 VCC1R8B
USB2.0 CH11 G-Sensor BD9139MUV-E2 98
Smart Card Slot 64 81 TPM 1.2 VCC5M VCC1R8B
82
USB2.0 USB2.0 CH12 MAGNETICS
Express Slot 64
DC/DC VCC2R5A
Thermal Sensor Converter RJ45
BD91364BMUU-ZE2 100
AC-DC IN Main 58,59
PECI 3.0 Embedded Lenovo 86 Battery VCC5M VCC2R5A
SMB-MB/SB Controller ASIC
LED for Camera MEC1653L GFXCORE_D
ThinkEngine Audio 66
LED for ThinkPad Logos Combo Jack I2C 88 NCP81172MNTWG 110
75,76,77 84,85 VINT20 VCCGFXCORE_D
I/O SubCard Interface
USB2.0 USB2.0 USB 2.0 P?/P? VCC1R35VIDEO
Port 09 Port 13 SM Bus USB 3.0 P?
Camera-(USB3)/LID SW
SATA P?/P? LAN Sub Card External Connector/Socket TPS51219RTER 111
MDI 40
VCC5M VCC1R35VIDEO
Internal Connector/Socket
A
LED for ThinkPad Logo VCC1R05VIDEO A
Fingerprint Color CS13 Keyboard with Power Button LED for ThinkPad Logos On A cover Internal Switch NB681AGD-Z 112
Reader Sensor ClickPad Numpad Subcard 40
79 78 40 VCC1R05VIDEO
Conn Conn VCC5M VCC1R05VIDEO_PLL
79 40
Security Classification LC Future Center Secret Data Title
Camera Issued Date 2015/07/16 Deciphered Date 2016/01/16 TITLE PAGE

USB Port 8 Subcard 40 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. NM-A451
Date: Friday, October 02, 2015 Sheet 1 of 116
5 4 3 2 1
HTTPS://EN-MANUALS.CLAN.SU
5 4 3 2 1
TABLE: SYSTEM POWER STATE

EC SMBus0 address EC SMBus1 address
Gx State Sx State Mx State SW M SUS AMT A B User Observation Chipset
(System State) (System State) (System State) Power Power Power Power Power Power Device Address Device Address
G0 S0 M0 ON ON ON ON ON ON System Operating Full On Smart Battery 0001 011X b G-Senor (LIS3DH) 0011 000Xb
D D
M3 ON ON ON ON ON OFF Standby G-Senor (KX023) 0011 110Xb
S3 Standby Suspend-to-RAM
M-OFF ON ON ON OFF ON OFF
with USB wake enabled (STR)
G1 Deep S3 M-OFF ON ON OFF OFF ON OFF Standby
EC SMBus2 address EC SMBus10 address
S4 M3 ON ON ON ON OFF OFF Hibernation Suspend-to-Disk
with RTC wakeup (STD)
Deep S4 M-OFF ON ON OFF OFF ON OFF Device Address Device Address
S5 M3 ON ON ON ON OFF OFF Hibernation or Charge Controller 0001 0010 Master VGA 0x9E
Shutdown
G2 Deep S5 M-OFF ON ON OFF OFF ON OFF Soft Off
S5 EC OFF M-OFF OFF OFF OFF OFF OFF OFF
G3 --- --- OFF OFF OFF OFF OFF OFF No Power Mechanical Off
PCH SM Bus address PCH SM Bus0 address
Device Address Device Address
Schematics Mark Definition CH-A P DDR DIMM0 Intel Lan_I219
1001 0000b 0XC8
BOM Structure BTO Item CH-A S DDR DIMM1 1001 0001b
@ Not assembled. CH-B P DDR DIMM2 1001 0010b
EMC@ Assembled. EMC related parts. CH-B S DDR DIMM3 1001 0011b
RF@ Assembled. RF related parts.
C C
ME@ Assembled. ME related parts.
PRxxx,PCxxx, PWR related parts.
PLxxx If @, not assembled.
N16P@ Assembled. for N16P GPU SKU
N16S@ Assembled. for N16S GPU SKU
VP@ Assembled. for support vPro
NVP@ Assembled. Not support vPro
Any other mark like below is prohibited on Payton/Walter.

ESD@,EMI@,EMC_NS@,EMC_PX@,EMC_OPT@,CONN@,
CONN_NS@... RH,CH,LH(PCH related RLC)..
Capacitor Naming Note

B
Ceramic Capacitors: B
0.1U_0402_6.3VXX
Tolerance
Temperature Characteristics
Rated Voltage
Package Size
Temperature Characteristics:
Symbol 0 1 2 3 4 5 6 7 8 9 A
Code Z5U Z5V Z5P Y5U Y5V Y5P X5R X7R NPO COG X6S
B C D E F G H I J K L CPU PCB
BJ CH CJ CK SH SJ UJ UK SL X5S NOJ U1 U1 U1 U1 U1 ZZZ1
A
Tolerance: A
Symbol A B C D F G H J K M N i5 45W (vPro) i7 45W Non-vPro i7 45W vPro Z1 45W vPro Z2 45W vPro PCB NNM-A451
SA00007HA10 SA00007HB10 SA00007HC10 SA00007HD10 SA00007HF10 DAZ0Z600100
Tolerance +-0.05PF +-0.1PF +-0.25PF +-0.5PF +-1% +-2% +-3% +-5% +-10% +-20% +-30% I5@ I7NV@ I7VP@ Z1@ Z2@

Symbol P Q V X Z S Y Issued Date 2015/07/16 Deciphered Date 2016/01/16 Blank
HTTPS://EN-MANUALS.CLAN.SU THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Tolerance +100,-0% +30,-10% +20,-10% +40,-20% +80,-20% +50,-20% -30% ~ 10% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number
Custom
Rev
0.1
5 4 3 2 1
5 4 3 2 1
Payton Common
D D
U1A SKYLAKE_HALO
<27,28> M_A_DQ[0..63]
M_A_DQ0 BR6 BGA1440 AG1 M_A_DDRCLK0_1066M
DDR0_DQ[0] DDR0_CKP[0] M_A_DDRCLK0_1066M <27>
M_A_DQ1 BT6 AG2 -M_A_DDRCLK0_1066M
DDR0_DQ[1] DDR0_CKN[0] -M_A_DDRCLK0_1066M <27>
M_A_DQ2 BP3 AK1 -M_A_DDRCLK1_1066M
DDR0_DQ[2] DDR0_CKN[1] -M_A_DDRCLK1_1066M <27>
M_A_DQ3 BR3 AK2 M_A_DDRCLK1_1066M
DDR0_DQ[3] DDR0_CKP[1] M_A_DDRCLK1_1066M <27>
M_A_DQ4 BN5 AL3 M_A_DDRCLK2_1066M
DDR0_DQ[4] DDR0_CLKP[2] M_A_DDRCLK2_1066M <28>
M_A_DQ5 BP6 AK3 -M_A_DDRCLK2_1066M
DDR0_DQ[5] DDR0_CLKN[2] -M_A_DDRCLK2_1066M <28>
M_A_DQ6 BP2 AL2 M_A_DDRCLK3_1066M
DDR0_DQ[6] DDR0_CLKP[3] M_A_DDRCLK3_1066M <28>
M_A_DQ7 BN3 AL1 -M_A_DDRCLK3_1066M
DDR0_DQ[7] DDR0_CLKN[3] -M_A_DDRCLK3_1066M <28>
M_A_DQ8 BL4
M_A_DQ9 BL5 DDR0_DQ[8] AT1 M_A_CKE0
DDR0_DQ[9] DDR0_CKE[0] M_A_CKE0 <27>
M_A_DQ10 BL2 AT2 M_A_CKE1
M_A_DQ11 BM1 AT3 M_A_CKE2
M_A_DQ12 BK4 AT5 M_A_CKE3
M_A_DQ13 BK5
M_A_DQ14 BK1 DDR0_DQ[13] AD5 -M_A_CS0
DDR0_DQ[14] DDR0_CS#[0] -M_A_CS0 <27>
M_A_DQ15 BK2 AE2 -M_A_CS1
DDR0_DQ[15] DDR0_CS#[1] -M_A_CS1 <27>
M_A_DQ16 BG4 AD2 -M_A_CS2
DDR0_DQ[16]/DDR0_DQ[32] DDR0_CS#[2] -M_A_CS2 <28>
M_A_DQ17 BG5 AE5 -M_A_CS3
DDR0_DQ[17]/DDR0_DQ[33] DDR0_CS#[3] -M_A_CS3 <28>
M_A_DQ18 BF4
M_A_DQ19 BF5 DDR0_DQ[18]/DDR0_DQ[34] AD3 M_A_ODT0
DDR0_DQ[19]/DDR0_DQ[35] DDR0_ODT[0] M_A_ODT0 <27>
M_A_DQ20 BG2 AE4 M_A_ODT1
M_A_DQ21 BG1 AE1 M_A_ODT2
M_A_DQ22 BF1 AD4 M_A_ODT3
M_A_DQ23 BF2
M_A_DQ24 BD2 DDR0_DQ[23]/DDR0_DQ[39] AH5 M_A_BA0
DDR0_DQ[24]/DDR0_DQ[40] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] M_A_BA0 <27,28>
M_A_DQ25 BD1 AH1 M_A_BA1
DDR0_DQ[25]/DDR0_DQ[41] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] M_A_BA1 <27,28>
M_A_DQ26 BC4 AU1 M_A_BG0
DDR0_DQ[26]/DDR0_DQ[42] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] M_A_BG0 <27,28>
M_A_DQ27 BC5
C M_A_DQ28 BD5 DDR0_DQ[27]/DDR0_DQ[43] AH4 M_A_A16_RAS_N C
DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] M_A_A16_RAS_N <27,28>
M_A_DQ29 BD4 AG4 M_A_A14_WE_N
DDR0_DQ[29]/DDR0_DQ[45] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] M_A_A14_WE_N <27,28>
M_A_DQ30 BC1 AD1 M_A_A15_CAS_N
DDR0_DQ[30]/DDR0_DQ[46] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] M_A_A15_CAS_N <27,28>
M_A_DQ31 BC2
DDR0_DQ[31]/DDR0_DQ[47] M_A_A[0..9] <27,28>
M_A_DQ32 AB1 AH3 M_A_A0
M_A_DQ33 AB2 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] AP4 M_A_A1
M_A_DQ34 AA4 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AN4 M_A_A2
M_A_DQ35 AA5 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AP5 M_A_A3
M_A_DQ36 AB5 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] AP2 M_A_A4
M_A_DQ37 AB4 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] AP1 M_A_A5
M_A_DQ38 AA2 DDR0_DQ[37]/DDR1_DQ[5] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] AP3 M_A_A6
M_A_DQ39 AA1 DDR0_DQ[38]/DDR1_DQ[6] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AN1 M_A_A7
M_A_DQ40 V5 DDR0_DQ[39]/DDR1_DQ[7] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AN3 M_A_A8
M_A_DQ41 V2 DDR0_DQ[40]/DDR1_DQ[8] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AT4 M_A_A9
M_A_DQ42 U1 DDR0_DQ[41]/DDR1_DQ[9] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] AH2 M_A_A10_AP
DDR0_DQ[42]/DDR1_DQ[10] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] M_A_A10_AP <27,28>
M_A_DQ43 U2 AN2 M_A_A11
DDR0_DQ[43]/DDR1_DQ[11] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] M_A_A11 <27,28>
M_A_DQ44 V1 AU4 M_A_A12
DDR0_DQ[44]/DDR1_DQ[12] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] M_A_A12 <27,28>
M_A_DQ45 V4 AE3 M_A_A13
DDR0_DQ[45]/DDR1_DQ[13] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] M_A_A13 <27,28>
M_A_DQ46 U5 AU2 M_A_BG1
DDR0_DQ[46]/DDR1_DQ[14] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] M_A_BG1 <27,28>
M_A_DQ47 U4 AU3 -M_A_ACT
DDR0_DQ[47]/DDR1_DQ[15] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# -M_A_ACT <27,28>
M_A_DQ48 R2
M_A_DQ49 P5 DDR0_DQ[48]/DDR1_DQ[32] AG3 M_A_PARITY
DDR0_DQ[49]/DDR1_DQ[33] DDR0_PAR M_A_PARITY <27,28>
M_A_DQ50 R4 AU5 -M_A_ALERT
DDR0_DQ[50]/DDR1_DQ[34] DDR0_ALERT# -M_A_ALERT <27,28>
M_A_DQ51 P4
M_A_DQ52 R5 DDR0_DQ[51]/DDR1_DQ[35]
M_A_DQ53 P2 DDR0_DQ[52]/DDR1_DQ[36] BR5 -M_A_DQS0
M_A_DQ54 R1 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSN[0] BL3 -M_A_DQS1
M_A_DQ55 P1 DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQSN[1] BG3 -M_A_DQS2
M_A_DQ56 M4 DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQSN[2]/DDR0_DQSN[4] BD3 -M_A_DQS3
M_A_DQ57 M1 DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQSN[3]/DDR0_DQSN[5] AB3 M_A_DQS4
M_A_DQ58 L4 DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQSP[4]/DDR1_DQSP[0] V3 M_A_DQS5
M_A_DQ59 L2 DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQSP[5]/DDR1_DQSP[1] R3 M_A_DQS6
B M_A_DQ60 M5 DDR0_DQ[59]/DDR1_DQ[43] DDR0_DQSP[6]/DDR1_DQSP[4] M3 M_A_DQS7 B
DDR0_DQ[60]/DDR1_DQ[44] DDR0_DQSP[7]/DDR1_DQSP[5] -M_A_DQS[0..7] <27,28>
M_A_DQ61 M2
M_A_DQ62 L5 DDR0_DQ[61]/DDR1_DQ[45] BP5 M_A_DQS0
DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQSP[0] M_A_DQS[0..7] <27,28>
M_A_DQ63 L1 BK3 M_A_DQS1
DDR0_DQ[63]/DDR1_DQ[47] DDR0_DQSP[1] BF3 M_A_DQS2
M_A_CB0 BA2 DDR0_DQSP[2]/DDR0_DQSP[4] BC3 M_A_DQS3
<27,28> M_A_CB0 DDR0_ECC[0] DDR0_DQSP[3]/DDR0_DQSP[5]
<27,28> M_A_CB1 M_A_CB1 BA1 AA3 -M_A_DQS4
M_A_CB2 AY4 DDR0_ECC[1] DDR0_DQSN[4]/DDR1_DQSN[0] U3 -M_A_DQS5
<27,28> M_A_CB2 DDR0_ECC[2] DDR0_DQSN[5]/DDR1_DQSN[1]
<27,28> M_A_CB3 M_A_CB3 AY5 P3 -M_A_DQS6
M_A_CB4 BA5 DDR0_ECC[3] DDR0_DQSN[6]/DDR1_DQSN[4] L3 -M_A_DQS7
<27,28> M_A_CB4 DDR0_ECC[4] DDR0_DQSN[7]/DDR1_DQSN[5]
<27,28> M_A_CB5 M_A_CB5 BA4
M_A_CB6 AY1 DDR0_ECC[5] AY3 M_A_DQS8
<27,28> M_A_CB6 DDR0_ECC[6] DDR0_DQSP[8] M_A_DQS8 <27,28>
<27,28> M_A_CB7 M_A_CB7 AY2 BA3 -M_A_DQS8
DDR0_ECC[7] DDR0_DQSN[8] -M_A_DQS8 <27,28>
DDR CHANNEL
A
1 OF 14
SKYLAKE-H-CPU_BGA1440
@
A DDR4 INTERLEAVE IMPLEMENTATION A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 CPU SKL-H : DDR4 CH-A
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common
D D
U1B SKYLAKE_HALO
<29,30> M_B_DQ[0..63]
M_B_DQ0 BT11 BGA1440 AM9 M_B_DDRCLK0_1066M
DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKP[0] M_B_DDRCLK0_1066M <29>
M_B_DQ1 BR11 AN9 -M_B_DDRCLK0_1066M
DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[0] -M_B_DDRCLK0_1066M <29>
M_B_DQ2 BT8 AM8 -M_B_DDRCLK1_1066M
DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKN[1] -M_B_DDRCLK1_1066M <29>
M_B_DQ3 BR8 AM7 M_B_DDRCLK1_1066M
DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] M_B_DDRCLK1_1066M <29>
M_B_DQ4 BP11 AM11 M_B_DDRCLK2_1066M
DDR1_DQ[4]/DDR0_DQ[20] DDR1_CLKP[2] M_B_DDRCLK2_1066M <30>
M_B_DQ5 BN11 AM10 -M_B_DDRCLK2_1066M
DDR1_DQ[5]/DDR0_DQ[21] DDR1_CLKN[2] -M_B_DDRCLK2_1066M <30>
M_B_DQ6 BP8 AJ10 M_B_DDRCLK3_1066M
DDR1_DQ[6]/DDR0_DQ[22] DDR1_CLKP[3] M_B_DDRCLK3_1066M <30>
M_B_DQ7 BN8 AJ11 -M_B_DDRCLK3_1066M
DDR1_DQ[7]/DDR0_DQ[23] DDR1_CLKN[3] -M_B_DDRCLK3_1066M <30>
M_B_DQ8 BL12
M_B_DQ9 BL11 DDR1_DQ[8]/DDR0_DQ[24] AT8 M_B_CKE0
DDR1_DQ[9]/DDR0_DQ[25] DDR1_CKE[0] M_B_CKE0 <29>
M_B_DQ10 BL8 AT10 M_B_CKE1
M_B_DQ11 BJ8 AT7 M_B_CKE2
M_B_DQ12 BJ11 AT11 M_B_CKE3
M_B_DQ13 BJ10
M_B_DQ14 BL7 DDR1_DQ[13]/DDR0_DQ[29] AF11 -M_B_CS0
DDR1_DQ[14]/DDR0_DQ[30] DDR1_CS#[0] -M_B_CS0 <29>
M_B_DQ15 BJ7 AE7 -M_B_CS1
M_B_DQ16 BG11 AF10 -M_B_CS2
M_B_DQ17 BG10 AE10 -M_B_CS3
M_B_DQ18 BG8
M_B_DQ19 BF8 DDR1_DQ[18]/DDR0_DQ[50] AF7 M_B_ODT0
DDR1_DQ[19]/DDR0_DQ[51] DDR1_ODT[0] M_B_ODT0 <29>
M_B_DQ20 BF11 AE8 M_B_ODT1
M_B_DQ21 BF10 AE9 M_B_ODT2
M_B_DQ22 BG7 AE11 M_B_ODT3
M_B_DQ23 BF7
M_B_DQ24 BB11 DDR1_DQ[23]/DDR0_DQ[55] AH10 M_B_A16_RAS_N
DDR1_DQ[24]/DDR0_DQ[56] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] M_B_A16_RAS_N <29,30>
M_B_DQ25 BC11 AH11 M_B_A14_WE_N
DDR1_DQ[25]/DDR0_DQ[57] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] M_B_A14_WE_N <29,30>
M_B_DQ26 BB8 AF8 M_B_A15_CAS_N
DDR1_DQ[26]/DDR0_DQ[58] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] M_B_A15_CAS_N <29,30>
M_B_DQ27 BC8
C M_B_DQ28 BC10 DDR1_DQ[27]/DDR0_DQ[59] AH8 M_B_BA0 C
DDR1_DQ[28]/DDR0_DQ[60] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] M_B_BA0 <29,30>
M_B_DQ29 BB10 AH9 M_B_BA1
DDR1_DQ[29]/DDR0_DQ[61] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] M_B_BA1 <29,30>
M_B_DQ30 BC7 AR9 M_B_BG0
DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] M_B_BG0 <29,30>
M_B_DQ31 BB7
DDR1_DQ[31]/DDR0_DQ[63] M_B_A[0..9] <29,30>
M_B_DQ32 AA11 AJ9 M_B_A0
M_B_DQ33 AA10 DDR1_DQ[32]/DDR1_DQ[16] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] AK6 M_B_A1
M_B_DQ34 AC11 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] AK5 M_B_A2
M_B_DQ35 AC10 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] AL5 M_B_A3
M_B_DQ36 AA7 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[3] AL6 M_B_A4
M_B_DQ37 AA8 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[4] AM6 M_B_A5
M_B_DQ38 AC8 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AN7 M_B_A6
M_B_DQ39 AC7 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] AN10 M_B_A7
M_B_DQ40 W8 DDR1_DQ[39]/DDR1_DQ[23] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AN8 M_B_A8
M_B_DQ41 W7 DDR1_DQ[40]/DDR1_DQ[24] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AR11 M_B_A9
M_B_DQ42 V10 DDR1_DQ[41]/DDR1_DQ[25] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] AH7 M_B_A10_AP
DDR1_DQ[42]/DDR1_DQ[26] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] M_B_A10_AP <29,30>
M_B_DQ43 V11 AN11 M_B_A11
DDR1_DQ[43]/DDR1_DQ[27] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] M_B_A11 <29,30>
M_B_DQ44 W11 AR10 M_B_A12
DDR1_DQ[44]/DDR1_DQ[28] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] M_B_A12 <29,30>
M_B_DQ45 W10 AF9 M_B_A13
DDR1_DQ[45]/DDR1_DQ[29] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] M_B_A13 <29,30>
M_B_DQ46 V7 AR7 M_B_BG1
DDR1_DQ[46]/DDR1_DQ[30] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] M_B_BG1 <29,30>
M_B_DQ47 V8 AT9 -M_B_ACT
DDR1_DQ[47]/DDR1_DQ[31] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# -M_B_ACT <29,30>
M_B_DQ48 R11
M_B_DQ49 P11 DDR1_DQ[48] AJ7 M_B_PARITY
DDR1_DQ[49] DDR1_PAR M_B_PARITY <29,30>
M_B_DQ50 P7 AR8 -M_B_ALERT
DDR1_DQ[50] DDR1_ALERT# -M_B_ALERT <29,30>
M_B_DQ51 R8
M_B_DQ52 R10 DDR1_DQ[51]
DDR1_DQ[52] -M_B_DQS[0..7] <29,30>
M_B_DQ53 P10 BP9 -M_B_DQS0
M_B_DQ54 R7 DDR1_DQ[53] DDR1_DQSN[0]/DDR0_DQSN[2] BL9 -M_B_DQS1
M_B_DQ55 P8 DDR1_DQ[54] DDR1_DQSN[1]/DDR0_DQSN[3] BG9 -M_B_DQS2
M_B_DQ56 L11 DDR1_DQ[55] DDR1_DQSN[2]/DDR0_DQSN[6] BC9 -M_B_DQS3
M_B_DQ57 M11 DDR1_DQ[56] DDR1_DQSN[3]/DDR0_DQSN[7] AC9 -M_B_DQS4
M_B_DQ58 L7 DDR1_DQ[57] DDR1_DQSN[4]/DDR1_DQSN[2] W9 -M_B_DQS5
M_B_DQ59 M8 DDR1_DQ[58] DDR1_DQSN[5]/DDR1_DQSN[3] R9 -M_B_DQS6
B M_B_DQ60 L10 DDR1_DQ[59] DDR1_DQSN[6] M9 -M_B_DQS7 B
M_B_DQ61 M10 DDR1_DQ[60] DDR1_DQSN[7]
DDR1_DQ[61] M_B_DQS[0..7] <29,30>
M_B_DQ62 M7 BR9 M_B_DQS0
M_B_DQ63 L8 DDR1_DQ[62] DDR1_DQSP[0]/DDR0_DQSP[2] BJ9 M_B_DQS1
DDR1_DQ[63] DDR1_DQSP[1]/DDR0_DQSP[3] BF9 M_B_DQS2
M_B_CB0 AW11 DDR1_DQSP[2]/DDR0_DQSP[6] BB9 M_B_DQS3
<29,30> M_B_CB0 DDR1_ECC[0] DDR1_DQSP[3]/DDR0_DQSP[7]
<29,30> M_B_CB1 M_B_CB1 AY11 AA9 M_B_DQS4
M_B_CB2 AY8 DDR1_ECC[1] DDR1_DQSP[4]/DDR1_DQSP[2] V9 M_B_DQS5
<29,30> M_B_CB2 DDR1_ECC[2] DDR1_DQSP[5]/DDR1_DQSP[3]
<29,30> M_B_CB3 M_B_CB3 AW8 P9 M_B_DQS6
M_B_CB4 AY10 DDR1_ECC[3] DDR1_DQSP[6] L9 M_B_DQS7
<29,30> M_B_CB4 DDR1_ECC[4] DDR1_DQSP[7]
<29,30> M_B_CB5 M_B_CB5 AW10
M_B_CB6 AY7 DDR1_ECC[5] AW9 M_B_DQS8
<29,30> M_B_CB6 DDR1_ECC[6] DDR1_DQSP[8] M_B_DQS8 <29,30>
<29,30> M_B_CB7 M_B_CB7 AW7 AY9 -M_B_DQS8
DDR1_ECC[7] DDR1_DQSN[8] -M_B_DQS8 <29,30>
DDR CHANNEL B
R543 2 1 121_0402_1% DDR_RCOMP0 G1 BN13 M_A_VREF_CA_CPU

DDR_RCOMP[0] DDR_VREF_CA M_A_VREF_CA_CPU <27>
R544 2 1 75_0402_1% DDR_RCOMP1 H1 BP13
R545 2 1 100_0402_1% DDR_RCOMP2 J2 DDR_RCOMP[1] 2 OF 14 DDR0_VREF_DQ BR13 M_B_VREF_DQ_CPU
DDR_RCOMP[2] DDR1_VREF_DQ M_B_VREF_DQ_CPU <29>
PLACE CLOSE TO CPU SKYLAKE-H-CPU_BGA1440
DDR_VREF_CA : Connected to VREF_CA on DIMM CH-A
@ DDR0_VREF_DQ : NC
DDR1_VREF_DQ : Connected to VREF_CA on DIMM CH-B
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 CPU SKL-H : DDR4 CH-B
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Walter Unique
D D
<31> PEG_RXP[15:0] PEG_TXP[15:0] <31>
<31> PEG_RXN[15:0] SKYLAKE_HALO PEG_TXN[15:0] <31>

U1C
BGA1440
PEG_RXP15 E25 B25 PEG_TXP15_C C2004 1 2 0.22U_0201_6.3V6-K PEG_TXP15

PEG_RXN15 D25 PEG_RXP[0] PEG_TXP[0] A25 PEG_TXN15_C C9071 1 2 0.22U_0201_6.3V6-K PEG_TXN15
PEG_RXN[0] PEG_TXN[0]
PEG_RXN14 F24 PEG_RXP[1] PEG_TXP[1] C24 PEG_TXN14_C C9070 1 2 0.22U_0201_6.3V6-K PEG_TXN14
C PEG_RXN[6] PEG_TXN[6] C
PEG_RXP7 D17 A17 PEG_TXP7_C C9050 1 2 0.22U_0201_6.3V6-K PEG_TXP7
PEG_RXN7 E17 PEG_RXP[8] PEG_TXP[8] B17 PEG_TXN7_C C9063 1 2 0.22U_0201_6.3V6-K PEG_TXN7
PEG_RXP6 F16 C16 PEG_TXP6_C C9051 1 2 0.22U_0201_6.3V6-K PEG_TXP6
VCCCPUIO R1
1 2 PEG_COMP_W12mil G2
PEG_RCOMP
24.9_0402_1%
B B
DMI_TXP0 D8 B8 DMI_RXP0
<15> DMI_TXP0 DMI_RXP[0] DMI_TXP[0] DMI_RXP0 <15>
DMI_TXN0 E8 A8 DMI_RXN0
<15> DMI_TXN0 DMI_RXN[0] DMI_TXN[0] DMI_RXN0 <15>
DMI_TXP1 E6 C6 DMI_RXP1
DMI_TXN1 F6 B6 DMI_RXN1
DMI_TXP2 D5 B5 DMI_RXP2
DMI_TXN2 E5 A5 DMI_RXN2
DMI_TXP3 J8 D4 DMI_RXP3
DMI_TXN3 J9 B4 DMI_RXN3
3 OF 14
@
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 CPU SKL-H : PEG/DMI
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common
D D
Walter Only U1D SKYLAKE_HALO
0.1U_0201_6.3V6-K 1 2 C9315 N16S@ EXT_DP0P_CPU K36 BGA1440 D29 EDP_TXP0_I

<32,43> EXT_DP0P DDI1_TXP[0] EDP_TXP[0] EDP_TXP0_I <41>
0.1U_0201_6.3V6-K 1 2 C9297 N16S@ EXT_DP0N_CPU K37 E29 EDP_TXN0_I
<32,43> EXT_DP0N DDI1_TXN[0] EDP_TXN[0] EDP_TXN0_I <41>
0.1U_0201_6.3V6-K 1 2 C9310 N16S@ EXT_DP1P_CPU J35 F28 EDP_TXP1_I
<32,43> EXT_DP1P DDI1_TXP[1] EDP_TXP[1] EDP_TXP1_I <41>
0.1U_0201_6.3V6-K 1 2 C9311 N16S@ EXT_DP1N_CPU J34 E28 EDP_TXN1_I
<32,43> EXT_DP1N DDI1_TXN[1] EDP_TXN[1] EDP_TXN1_I <41>
0.1U_0201_6.3V6-K 1 2 C9312 N16S@ EXT_DP2P_CPU H37 B29 EDP_TXN2_I
DP <32,43> EXT_DP2P
0.1U_0201_6.3V6-K 1 2 C9314 N16S@ EXT_DP2N_CPU H36 DDI1_TXP[2] EDP_TXN[2] A29 EDP_TXP2_I
EDP_TXN2_I <41>
<32,43> EXT_DP2N DDI1_TXN[2] EDP_TXP[2] EDP_TXP2_I <41>
0.1U_0201_6.3V6-K 1 2 C9313 N16S@ EXT_DP3P_CPU J37 B28 EDP_TXN3_I
<32,43> EXT_DP3P DDI1_TXP[3] EDP_TXN[3] EDP_TXN3_I <41>
0.1U_0201_6.3V6-K 1 2 C9316 N16S@ EXT_DP3N_CPU J38 C28 EDP_TXP3_I
<32,43> EXT_DP3N DDI1_TXN[3] EDP_TXP[3] EDP_TXP3_I <41>
VCCCPUIO
EXT_AUXP_CPU D27 C26 EDP_AUXP_I
<43> EXT_AUXP_CPU DDI1_AUXP EDP_AUXP EDP_AUXP_I <41>
EXT_AUXN_CPU E27 B26 EDP_AUXN_I
C <43> EXT_AUXN_CPU DDI1_AUXN EDP_AUXN EDP_AUXN_I <41> C
1
0.1U_0201_6.3V6-K 1 2 C9335 N16S@ TBT_SNK0_DP0P_CPU H34
<32,46> TBT_SNK0_DP0P DDI2_TXP[0]
0.1U_0201_6.3V6-K 1 2 C9329 N16S@ TBT_SNK0_DP0N_CPU H33 R2
<32,46> TBT_SNK0_DP0N DDI2_TXN[0]
0.1U_0201_6.3V6-K 1 2 C9331 N16S@ TBT_SNK0_DP1P_CPU F37 A33 Leave EDP_DISP_UTIL NC 24.9_0402_1%
<32,46> TBT_SNK0_DP1P 0.1U_0201_6.3V6-K 1 2 C9332 N16S@ TBT_SNK0_DP1N_CPU G38 DDI2_TXP[1] EDP_DISP_UTIL
0.1U_0201_6.3V6-K 1 2 C9330 N16S@ TBT_SNK0_DP2P_CPU F34
<32,46> TBT_SNK0_DP2P
2
0.1U_0201_6.3V6-K 1 2 C9334 N16S@ TBT_SNK0_DP2N_CPU F35 DDI2_TXP[2] D37 EDP_RCOMP_W12mil
<32,46> TBT_SNK0_DP2N DDI2_TXN[2] EDP_RCOMP
0.1U_0201_6.3V6-K 1 2 C9333 N16S@ TBT_SNK0_DP3P_CPU E37
0.1U_0201_6.3V6-K 1 2 C9336 N16S@ TBT_SNK0_DP3N_CPU E36
0.1U_0201_6.3V6-K 1 2 C9337 N16S@ TBT_SNK0_AUXP_CPU F26
<46> TBT_SNK0_AUXP DDI2_AUXP
0.1U_0201_6.3V6-K 1 2 C9338 N16S@ TBT_SNK0_AUXN_CPU E26
TBT <46> TBT_SNK0_AUXN DDI2_AUXN
0.1U_0201_6.3V6-K 1 2 C9326 N16S@ TBT_SNK1_DP0P_CPU C34 Need to confirm
<32,46> TBT_SNK1_DP0P DDI3_TXP[0] we required these signals for PY/WLT
0.1U_0201_6.3V6-K 1 2 C9319 N16S@ TBT_SNK1_DP0N_CPU D34
0.1U_0201_6.3V6-K 1 2 C9320 N16S@ TBT_SNK1_DP1P_CPU B36
<32,46> TBT_SNK1_DP1P 0.1U_0201_6.3V6-K 1 2 C9322 N16S@ TBT_SNK1_DP1N_CPU B34 DDI3_TXP[1]
0.1U_0201_6.3V6-K 1 2 C9321 N16S@ TBT_SNK1_DP2P_CPU F33
0.1U_0201_6.3V6-K 1 2 C9324 N16S@ TBT_SNK1_DP2N_CPU E33
0.1U_0201_6.3V6-K 1 2 C9323 N16S@ TBT_SNK1_DP3P_CPU C33
0.1U_0201_6.3V6-K 1 2 C9325 N16S@ TBT_SNK1_DP3N_CPU B33
<32,46> TBT_SNK1_DP3N DDI3_TXN[3] G27 PROC_AUDIO_CLK_CPU
PROC_AUDIO_CLK PROC_AUDIO_CLK_CPU <17>
0.1U_0201_6.3V6-K 1 2 C9328 N16S@ TBT_SNK1_AUXP_CPU A27 G25 PROC_AUDIO_SDO_CPU
<32,46> TBT_SNK1_AUXP DDI3_AUXP PROC_AUDIO_SDI PROC_AUDIO_SDO_CPU <17>
0.1U_0201_6.3V6-K 1 2 C9327 N16S@ TBT_SNK1_AUXN_CPU B27 G29 PROC_AUDIO_SDI_CPU_R 20_0402_5% 1 2 R3
<32,46> TBT_SNK1_AUXN DDI3_AUXN PROC_AUDIO_SDI_CPU <17>
4 OF 14 PROC_AUDIO_SDO
Place near CPU.
Need create 5% P/N
@
2
R9989 @
0_0402_5%
B B
EMI
1
1
C9355 @
0.1U_0402_10V6-K
2
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 CPU SKL-H : DDI/EDP
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common VCCST VCCSTG
2
VCC3M VCC3B
R4 R5 @ R6 R7
56_0402_5% 100_0402_5% 100_0402_5% 1K_0402_1%
2
1
R659 @ R774
100K_0402_5% 100K_0402_5% -SVID_ALERT
D D
SVID_CLK
1
1
VCC1R2A DDR_VTT_PG_CTRL SVID_DATA
DDR_VTT_PG_CTRL <99>
-PROCHOT
1
VCC1R2A
Q55 @ C709
2 DTC115TMT2L_VMT3 1 2
U1E SKYLAKE_HALO
5
0.1U_0402_16V7-K
1 U36 B31 BGA1440 BN25 CFG0
P <20> CPU_BCLK_100M
3
NC 4 A32 BCLKP CFG[0] BN27 Test_Point_32MIL 1 TP53

Y <20> -CPU_BCLK_100M BCLKN CFG[1]
DDR_PG_CTRL 2 BN26 CFG2
A CFG[2]
G
SN74AUP1G07DCKR SC70 D35 BN28 CFG3 CFG3 <24>

<20> CPU_PCI_BCLK_100M PCI_BCLKP CFG[3]
C36 BR20 CFG4
<20> -CPU_PCI_BCLK_100M
3
PCI_BCLKN CFG[4] BM20 CFG5

CFG[5]
2
E31 BT20 CFG6

<20> CPU_REFCLK_24M CLK24P CFG[6]
R77 @ D31 BP20 CFG7
<20> -CPU_REFCLK_24M CLK24N CFG[7]
10K_0402_5% BR23 Test_Point_32MIL 1 TP37
CFG[8] BR22 Test_Point_32MIL 1 TP38
CFG[9] BT23 Test_Point_32MIL 1 TP39
1
CFG[10] BT22 Test_Point_32MIL 1 TP40

CFG[11]
1
BM19 Test_Point_32MIL 1 TP41
CFG[12] BR19 Test_Point_32MIL 1 TP42 R8 R9 R10 R11 R12 R13
CFG[13] BP19 Test_Point_32MIL 1 TP43 1K_0402_1% 1K_0402_1% 1K_0402_1% 1K_0402_1% 1K_0402_1% 1K_0402_1%
-SVID_ALERT R14 1 2 220_0402_5% BH31 CFG[14] BT19 Test_Point_32MIL 1 TP44 @ N16S@ N16S@ @
<91> -SVID_ALERT VIDALERT# CFG[15]
<91> SVID_CLK SVID_CLK R772 1 2 0_0402_5% BH32
2
SVID_DATA R773 1 2 0_0402_5% BH29 VIDSCK BN23 Test_Point_32MIL 1 TP45
<91> SVID_DATA VIDSOUT CFG[17]
-PROCHOT R15 1 2 510_0402_1% BR30 BP23 Test_Point_32MIL 1 TP46
<76,91> -PROCHOT PROCHOT# CFG[16] BP22 Test_Point_32MIL 1 TP47
DDR_PG_CTRL BT13 CFG[19] BN22 Test_Point_32MIL 1 TP48
C DDR_VTT_CNTL CFG[18] C
BR27 IST_TRIG 1 TP49 Test_Point_32MIL Walter Only
BPM#[0] BT27 1 TP50 Test_Point_32MIL
BPM#[1] BM31 1 TP51 Test_Point_32MIL
VCCST_PWRGD R586 1 2 60.4_0402_1% H13 BPM#[2] BT30 1 TP52 Test_Point_32MIL
VCCST_PWRGD BPM#[3]
PROCPWRGD_CPU BT31
<17> PROCPWRGD_CPU PROCPWRGD
PROCPWRGD From PCH to CPU 1 2 BP35 BT28 XDP_TDO <24>
<16> -PCH_PLTRST_PROC RESET# PROC_TDO
RESET# From PCH to CPU BM34 BL32
<16> PM_SYNC PM_SYNC PROC_TDI XDP_TDI <24>
R16 0_0402_5% BP31 BP28
<16> PM_DOWN PM_DOWN PROC_TMS XDP_TMS <24>
BT34 BR28
<16,76> PECI PECI PROC_TCK XDP_TCK <24>
J31
<16> -THERMTRIP THERMTRIP# BP30
PROC_TRST# -XDP_TRST <24>
BR33 BL30
SKTOCC# PROC_PREQ# -XDP_PREQ <24>
VCCST BN1 BP27 -XDP_PRDY <24>
PROC_SELECT# PROC_PRDY#
R78 2 1 10K_0402_5% BM30
CATERR# BT25 CFG_RCOMP
CFG_RCOMP
2
5 OF 14
R17 R18 @
SKYLAKE-H-CPU_BGA1440 49.9_0402_1% 51_0402_1% 51_0402_1%
NEED TO CONFIRM R297 @
@
1
VCC1R0_SUS
VCC3_SUS
If VCCSTG is used instead of VCC1R0_SYS,

B VCCST_PWRGD will be off in Sleep S0 because B
VCCSTG may be turned off when in Sleep S0. TABLE CFG[19:0] pin has internal Pull up to VCCCPUIO with 5-8 k ohm.
2
Currently, VCCSTG is still on in Sleep S0

2
R20 but we may change logic to turn off VCCSTG in sleep S0.
R19 10K_0402_5% (CT_20141216)
10K_0402_5% CFG[0] : Stall reset sequence after CPU PLL lock until de-asserted:
1 : No Stall <----------- LOGIC
1
1
VCCST_PWRGD 0 : Stall
CFG[2] : PEG Static Lane Reversal

1 : Normal Operation
1
D D
CPUCORE_ON 2 Q1 2 Q2
<84,91> CPUCORE_ON G LSK3541G1ET2L_VMT3 G LSK3541G1ET2L_VMT3 0 : Lane Reversal <----------- LOGIC
S S
CFG[4] : eDP enable
3
1 : Disabled
0 : Enabled <----------- LOGIC
CFG[6:5] : PEG Bifurcation, bus#:dev#:func#=0:1:0
VCCST_PWRGD requirements (546884_SKL_H_PDG_Rev0_71) 11 : 1x16 <----------- LOGIC
1) Indication that the VCCST/VDDQ power supplies are stable and within specification. CFG[7] : PEG Training
(Table 41-1) 1 : PEG Train immediately following RESET# deassertion <----------- LOGIC
2) VCCST_PWRGD must go low during Sx pwr states, regardless of the voltage level of VCCST. 0 : PEG Wait for BIOS for training
(Figure 41-1 Note 1) CFG[19:8] : Reserved
A A
3) VCCST_PWRGD should be equal or ealier than PCH_PWROK.
(Table 41-5, tCPU16. See also 543016_SKL_PDG_UY_1_0) For x16 Reversal Lanes - CFG[6/5/2] setting is 110
4) VCCST_PWRGD is typically made from ALL_SYS_PWRGD For x4 Reversal Lanes - CFG[6/5/2] setting is 000
(CPUCORE_ON/VR_ON for CPU DCDC), not PCH_PWROK (CPUCORE_PWRGD).
(Figure 41-1) Security Classification LC Future Center Secret Data Title
Issued Date 2015/07/16 Deciphered Date 2016/01/16 CPU SKL-H : MISC/CLK/JTAG/CFG
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common
U1F SKYLAKE_HALO U1L SKYLAKE_HALO U1M SKYLAKE_HALO

D D
Y38 BGA1440 K1 C17 BGA1440 C25 BB4 BGA1440 AK30
Y37 VSS_1 VSS_78 J36 C13 VSS_154 VSS_239 C23 BB3 VSS_300 VSS_378 AK29
Y14 VSS_2 VSS_79 J33 C9 VSS_155 VSS_240 C21 BB2 VSS_301 VSS_379 AK4
Y13 VSS_3 VSS_80 J32 BT32 VSS_156 VSS_241 C19 BB1 VSS_302 VSS_380 AJ38
Y11 VSS_4 VSS_81 J25 BT26 VSS_157 VSS_242 C15 BA38 VSS_303 VSS_381 AJ37
Y7 VSS_8 VSS_85 J7 BT14 VSS_161 VSS_246 BM29 BA10 VSS_307 VSS_385 AJ3
W34 VSS_9 VSS_86 J4 BT12 VSS_162 VSS_247 BM25 BA9 VSS_308 VSS_386 AJ2
W33 VSS_10 VSS_87 H35 BT9 VSS_163 VSS_248 BM18 BA8 VSS_309 VSS_387 AJ1
W12 VSS_11 VSS_88 H32 BT5 VSS_164 VSS_249 BM11 BA7 VSS_310 VSS_388 AH34
W5 VSS_12 VSS_89 H25 BR36 VSS_165 VSS_250 BM8 BA6 VSS_311 VSS_389 AH33
W4 VSS_13 VSS_90 H22 BR34 VSS_166 VSS_251 BM7 B9 VSS_312 VSS_390 AH12
W3 VSS_14 VSS_91 H18 BR29 VSS_167 VSS_252 BM5 AY34 VSS_313 VSS_391 AH6
W2 VSS_15 VSS_92 H12 BR26 VSS_168 VSS_253 BM3 AY33 VSS_314 VSS_392 AG30
W1 VSS_16 VSS_93 H11 BR24 VSS_169 VSS_254 BL38 AY14 VSS_315 VSS_393 AG29
V30 VSS_17 VSS_94 G28 BR21 VSS_170 VSS_255 BL35 AY12 VSS_316 VSS_394 AG11
V29 VSS_18 VSS_95 G26 BR18 VSS_171 VSS_256 BL13 AW30 VSS_317 VSS_395 AG10
V12 VSS_19 VSS_96 G24 BR14 VSS_172 VSS_257 BL6 AW29 VSS_318 VSS_396 AG8
V6 VSS_20 VSS_97 G23 BR12 VSS_173 VSS_258 BK25 AW12 VSS_319 VSS_397 AG7
U38 VSS_21 VSS_98 G22 BR7 VSS_174 VSS_259 BK22 AW5 VSS_320 VSS_398 AG6
U37 VSS_153 VSS_99 G20 BP34 VSS_175 VSS_260 BK13 AW4 VSS_321 VSS_399 AF14
U6 VSS_22 VSS_100 G18 BP33 VSS_176 VSS_261 BK6 AW3 VSS_322 VSS_400 AF13
T34 VSS_23 VSS_101 G16 BP29 VSS_177 VSS_262 BJ30 AW2 VSS_323 VSS_401 AF12
T33 VSS_24 VSS_102 G14 BP26 VSS_178 VSS_263 BJ29 AW1 VSS_324 VSS_402 AF4
T14 VSS_25 VSS_103 G12 BP24 VSS_179 VSS_264 BJ15 AV38 VSS_325 VSS_403 AF3
T13 VSS_26 VSS_104 G10 BP21 VSS_180 VSS_265 BJ12 AV37 VSS_326 VSS_404 AF2
T12 VSS_27 VSS_105 G9 BP18 VSS_181 VSS_266 BH11 AU34 VSS_327 VSS_405 AF1
T11 VSS_28 VSS_106 G8 BP14 VSS_182 VSS_267 BH10 AU33 VSS_328 VSS_406 AE34
T10 VSS_29 VSS_107 G6 BP12 VSS_183 VSS_268 BH7 AU12 VSS_329 VSS_407 AE33
C T9 VSS_30 VSS_108 G5 BP7 VSS_184 VSS_269 BH6 AU11 VSS_330 VSS_408 AE6 C
T8 VSS_31 VSS_109 G4 BN34 VSS_185 VSS_270 BH3 AU10 VSS_331 VSS_409 AD30
T7 VSS_32 VSS_110 F36 BN31 VSS_186 VSS_271 BH2 AU9 VSS_332 VSS_410 AD29
T5 VSS_33 VSS_111 F31 BN30 VSS_187 VSS_272 BG37 AU8 VSS_333 VSS_411 AD12
T2 VSS_36 VSS_114 F25 BN21 VSS_190 VSS_275 BF34 AT30 VSS_336 VSS_414 AD9
T1 VSS_37 VSS_115 F23 BN20 VSS_191 VSS_276 BF6 AT29 VSS_337 VSS_415 AD8
R30 VSS_38 VSS_116 F21 BN19 VSS_192 VSS_277 BE30 AT6 VSS_338 VSS_416 AD7
R29 VSS_39 VSS_117 F19 BN18 VSS_193 VSS_278 BE5 AR38 VSS_339 VSS_417 AD6
R12 VSS_40 VSS_118 F17 BN14 VSS_194 VSS_279 BE4 AR37 VSS_340 VSS_418 AC38
P38 VSS_41 VSS_119 F15 BN12 VSS_195 VSS_280 BE3 AR14 VSS_341 VSS_419 AC37
P6 VSS_44 VSS_122 F9 BN4 VSS_198 VSS_283 BD38 AR4 VSS_344 VSS_422 AC5
N34 VSS_45 VSS_123 F8 BN2 VSS_199 VSS_284 BD37 AR3 VSS_345 VSS_423 AC4
N33 VSS_46 VSS_124 F5 BM38 VSS_200 VSS_285 BD12 AR2 VSS_346 VSS_424 AC3
N12 VSS_47 VSS_125 F4 BM35 VSS_201 VSS_286 BD11 AR1 VSS_347 VSS_425 AC2
N11 VSS_48 VSS_126 F3 BM28 VSS_202 VSS_287 BD10 AP34 VSS_348 VSS_426 AC1
N10 VSS_49 VSS_127 F2 BM27 VSS_203 VSS_288 BD8 AP33 VSS_349 VSS_427 AB34
N9 VSS_50 VSS_128 E38 BM26 VSS_204 VSS_289 BD7 AP12 VSS_350 VSS_428 AB33
N8 VSS_51 VSS_129 E35 BM23 VSS_205 VSS_290 BD6 AP11 VSS_351 VSS_429 AB6
N7 VSS_52 VSS_130 E34 BM21 VSS_206 VSS_291 BC33 AP10 VSS_352 VSS_430 AA30
N4 VSS_55 VSS_133 D33 BM9 VSS_209 VSS_294 BC6 AN30 VSS_355 VSS_433 A30
N3 VSS_56 VSS_134 D30 BM6 VSS_210 VSS_295 BB30 AN29 VSS_356 VSS_434 A28
N2 VSS_57 VSS_135 D28 BM2 VSS_211 VSS_296 BB29 AN12 VSS_357 VSS_435 A26
N1 VSS_58 VSS_136 D26 BL29 VSS_212 VSS_297 BB6 AN6 VSS_358 VSS_436 A24
M14 VSS_59 VSS_137 D24 BK29 VSS_213 VSS_298 BB5 AN5 VSS_359 VSS_437 A22
M13 VSS_60 VSS_138 D22 BK15 VSS_214 VSS_299 AM38 VSS_360 VSS_438 A20
M12 VSS_61 VSS_139 D20 BK14 VSS_215 AM37 VSS_361 VSS_439 A18
B M6 VSS_62 VSS_140 D18 BJ32 VSS_216 AM12 VSS_362 VSS_440 A16 B
L34 VSS_63 VSS_141 D16 BJ31 VSS_217 AM5 VSS_363 VSS_441 A14
L29 VSS_66 VSS_144 D10 BH14 VSS_220 AM2 VSS_366 VSS_444 A9
K38 VSS_67 VSS_145 D9 BH12 VSS_221 C2 AM1 VSS_367 VSS_445 A6
K11 VSS_68 VSS_146 D6 BH9 VSS_222 NCTFVSS_2 BT36 TP959 1 Test_Point_20MIL AL34 VSS_368 VSS_446
K10 VSS_69 VSS_147 D3 BH8 VSS_223 NCTFVSS_3 BT35 TP960 1 Test_Point_20MIL AL33 VSS_369
K9 VSS_70 VSS_148 C37 BH5 VSS_224 NCTFVSS_4 BT4 AL14 VSS_370 B37 TP963 1 Test_Point_20MIL
K8 VSS_71 VSS_149 C31 BH4 VSS_225 NCTFVSS_5 BT3 TP961 1 Test_Point_20MIL AL12 VSS_371 NCTFVSS_8 B3
K7 VSS_72 VSS_150 C29 BH1 VSS_226 NCTFVSS_6 BR38 TP962 1 Test_Point_20MIL AL10 VSS_372 NCTFVSS_9 A34 TP964 1 Test_Point_20MIL
K5 VSS_73 VSS_151 C27 BG38 VSS_227 NCTFVSS_7 AL9 VSS_373 NCTFVSS_10 A4
K4 VSS_74 VSS_152 BG13 VSS_228 AL8 VSS_374 NCTFVSS_11 A3 TP965 1 Test_Point_20MIL
K3 VSS_75 D38 TP958 1 BG12 VSS_229 AL7 VSS_375 NCTFVSS_12
K2 VSS_76 NCTFVSS_1 BF33 VSS_230 AL4 VSS_376
VSS_77 6 OF 14 Test_Point_20MIL BF12 VSS_231 VSS_377
BE29 VSS_232 13 OF 14
SKYLAKE-H-CPU_BGA1440 BE6 VSS_233
BD9 VSS_234 SKYLAKE-H-CPU_BGA1440
@ VSS_235
BC34 @
BC12 VSS_236
BB12 VSS_237
VSS_238 12 OF 14
@
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 CPU SKL-H : GND
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common
D D
VCCCPUCORE VCCCPUCORE
U1G SKYLAKE_HALO
BGA1440
AA13 V32
AA31 VCC_1 VCC_64 V33
AA37 VCC_7 VCC_70 W13
AA38 VCC_8 VCC_71 W14
AB29 VCC_9 VCC_72 W29
AC13 VCC_17 VCC_80 Y29
C AC34 VCC_24 VCC_87 Y36 C
AC35 VCC_25 VCC_88 L14
AC36 VCC_26 VCC_89 P29
AD13 VCC_27 VCC_90 P30
AD36 VCC_34 VCC_97 R13
AE13 VCC_37 VCC_100 R33
AE14 VCC_38 VCC_101 R34
AE30 VCC_39 VCC_102 R35
AE31 VCC_40 VCC_103 R36
AE32 VCC_41 VCC_104 R37
AE35 VCC_42 VCC_105 R38
AE36 VCC_43 VCC_106 T29
AE37 VCC_44 VCC_107 T30
AE38 VCC_45 VCC_108 T31
AF35 VCC_46 VCC_109 T32
AF36 VCC_47 VCC_110 T35
AF37 VCC_48 VCC_111 T36
AF38 VCC_49 VCC_112 T37
K13 VCC_50 VCC_113 T38
K14 VCC_51 VCC_114 U29
L13 VCC_52 VCC_115 U30
N13 VCC_53 VCC_116 U31 VCCCPUCORE
N14 VCC_54 VCC_117 U32
N30 VCC_55 VCC_118 U33
B N31 VCC_56 VCC_119 U34 B
N32 VCC_57 VCC_120 U35
N35 VCC_58 VCC_121 U36
VCC_59 VCC_122
1
N36 V13
N37 VCC_60 VCC_123 V14
N38 VCC_61 VCC_124 V31 100_0402_1%
P13 VCC_62 VCC_125 P14 R21
VCC_63 VCC_126
2
AG37 R750 1 2 0_0402_5%
VCC_SENSE VCCCORE_SENSE <91>
AG38 R751 1 2 0_0402_5%
VSS_SENSE VSSCORE_SENSE <91>
7 OF 14
1
100_0402_1%
@
R22
2
NEAR PROCESSOR PINS
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 CPU SKL-H : VCC
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Walter Unique
VCCGFXCORE_I VCCGFXCORE_I VCCGFXCORE_I
U1H SKYLAKE_HALO U1N SKYLAKE_HALO
BG34 BGA1440 AV29 AJ29 BGA1440

D BG35 VCCGT_1 VCCGT_55 AV30 AJ30 VCCGT_109 D
BG36 VCCGT_2 VCCGT_56 AV31 AJ31 VCCGT_110 AF29
BH33 VCCGT_3 VCCGT_57 AV32 AJ32 VCCGT_111 VCCGTX_1 AF30
BH38 VCCGT_8 VCCGT_62 AW14 AK31 VCCGT_116 VCCGTX_6 AG13
BJ37 VCCGT_9 VCCGT_63 AW31 AK32 VCCGT_117 VCCGTX_7 AG14
BJ38 VCCGT_10 VCCGT_64 AW32 AK33 VCCGT_118 VCCGTX_8 AG31
BL36 VCCGT_11 VCCGT_65 AW33 AK34 VCCGT_119 VCCGTX_9 AG32
BL37 VCCGT_12 VCCGT_66 AW34 AK35 VCCGT_120 VCCGTX_10 AG33
BM36 VCCGT_13 VCCGT_67 AW35 AK36 VCCGT_121 VCCGTX_11 AG34
BM37 VCCGT_14 VCCGT_68 AW36 AK37 VCCGT_122 VCCGTX_12 AG35
BN36 VCCGT_15 VCCGT_69 AW37 AK38 VCCGT_123 VCCGTX_13 AG36
BN37 VCCGT_16 VCCGT_70 AW38 AL13 VCCGT_124 VCCGTX_14 AH13
BN38 VCCGT_17 VCCGT_71 AY29 AL29 VCCGT_125 VCCGTX_15 AH14
BP37 VCCGT_18 VCCGT_72 AY30 AL30 VCCGT_126 VCCGTX_16 AH29
BP38 VCCGT_19 VCCGT_73 AY31 AL31 VCCGT_127 VCCGTX_17 AH30
BR37 VCCGT_20 VCCGT_74 AY32 AL32 VCCGT_128 VCCGTX_18 AH31
BT37 VCCGT_21 VCCGT_75 AY35 AL35 VCCGT_129 VCCGTX_19 AH32
BE38 VCCGT_22 VCCGT_76 AY36 AL36 VCCGT_130 VCCGTX_20 AJ13
BF13 VCCGT_23 VCCGT_77 AY37 AL37 VCCGT_131 VCCGTX_21 AJ14
BF14 VCCGT_24 VCCGT_78 AY38 AL38 VCCGT_132 VCCGTX_22
BF29 VCCGT_25 VCCGT_79 BA13 AM13 VCCGT_133
C BG29 VCCGT_33 VCCGT_87 BA35 AM35 VCCGT_141 C
BG30 VCCGT_34 VCCGT_88 BA36 AM36 VCCGT_142
BG31 VCCGT_35 VCCGT_89 BB13 AN13 VCCGT_143
BC36 VCCGT_38 VCCGT_92 BB32 AN32 VCCGT_146
BD13 VCCGT_41 VCCGT_95 BB35 AN35 VCCGT_149
BD31 VCCGT_45 VCCGT_99 BC29 AP13 VCCGT_153 VCCGFXCORE_I
BD32 VCCGT_46 VCCGT_100 BC30 AP14 VCCGT_154
BD36 VCCGT_50 VCCGT_104 BE33 AP32 VCCGT_158
1
BE31 VCCGT_51 VCCGT_105 BE34 AP35 VCCGT_159
BE32 VCCGT_52 VCCGT_106 BE35 AP36 VCCGT_160
BE37 VCCGT_53 VCCGT_107 BE36 AP37 VCCGT_161 100_0402_5%
VCCGT_54 VCCGT_108 AP38 VCCGT_162 R23
8 OF 14 AR29 VCCGT_163
2
AR30 VCCGT_164
SKYLAKE-H-CPU_BGA1440 AR31 VCCGT_165
AR32 VCCGT_166
@ VCCGT_167
AR33 AH38 R752 1 2 0_0402_5%
VCCGT_168 VCCGT_SENSE VCCGT_SENSE <91>
AR34 AH35
AR35 VCCGT_169 VSSGTX_SENSE AH37 R754 1 2 0_0402_5%
VCCGT_170 VSSGT_SENSE VSSGT_SENSE <91>
AR36 AH36
AT14 VCCGT_171 VCCGTX_SENSE
AT31 VCCGT_172
B AT32 VCCGT_173 B
AT33 VCCGT_174
VCCGT_175
1
AT34
AT35 VCCGT_176
AT36 VCCGT_177 100_0402_5%
AT37 VCCGT_178 R24
AT38 VCCGT_179
2
AU14 VCCGT_180
AU29 VCCGT_181
AU30 VCCGT_182
AU31 VCCGT_183
AU32 VCCGT_184
AU35 VCCGT_185
AU36 VCCGT_186
AU37 VCCGT_187
AU38 VCCGT_188
VCCGT_189 14 OF 14
@
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 CPU SKL-H : VCCGT/VCCGTX
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common
D D
VCCSA VCC1R2A
U1I SKYLAKE_HALO
J30 BGA1440 AA6

K29 VCCSA_1 VDDQ_1 AE12
K30 VCCSA_2 VDDQ_2 AF5
K31 VCCSA_3 VDDQ_3 AF6
K32 VCCSA_4 VDDQ_4 AG5
K33 VCCSA_5 VDDQ_5 AG9
K34 VCCSA_6 VDDQ_6 AJ12
K35 VCCSA_7 VDDQ_7 AL11
L31 VCCSA_8 VDDQ_8 AP6
L32 VCCSA_9 VDDQ_9 AP7
L35 VCCSA_10 VDDQ_10 AR12
VCCSA_11 VDDQ_11 VDDQC : Memory Control Clock Power
L36 AR6
L37 VCCSA_12 VDDQ_12 AT12
VCCSA_13 VDDQ_13 VCCPLL_OC : CPU digital PLL power rails
L38 AW6
M29 VCCSA_14 VDDQ_14 AY6
M30 VCCSA_15 VDDQ_15 J5 VCC1R2A VCC1R2A VCCST VCCSTG
M31 VCCSA_16 VDDQ_16 J6
M32 VCCSA_17 VDDQ_17 K12
M33 VCCSA_18 VDDQ_18 K6
1U_0402_6.3V6-K
1U_0402_6.3V6-K
VCCSA_19 VDDQ_19
10U_0603_6.3V6-M
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
C M34 L12 C
M35 VCCSA_20 VDDQ_20 L6
VCCSA_21 VDDQ_21 1
C122
C177
C252
VCCCPUIO M36 R6
VCCSA_22 VDDQ_22
C1
C2
C3
T6
VDDQ_23 W6
AG12 VDDQ_24 2
G15 VCCIO_1 Y12
VCCIO_2 VDDQC
10U_0603_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
G17
G19 VCCIO_3 BH13
1 1 1 VCCIO_4 VCCPLL_OC_1
C289
C379
C380 G21 G11

H15 VCCIO_5 VCCPLL_OC_2
H16 VCCIO_6
2 2 2 H17 VCCIO_7 H30 VCCCPUIO VCCSA
H19 VCCIO_8 VCCST
H20 VCCIO_9 H29
VCCIO_10 VCCSTG_1
1
H21
H26 VCCIO_11 G30
H27 VCCIO_12 VCCSTG_2 100_0402_5% 100_0402_5%
J15 VCCIO_13 H28 R25 R26
J16 VCCIO_14 VCCPLL_1 J28
2
J17 VCCIO_15 VCCPLL_2
J19 VCCIO_16
J20 VCCIO_17 M38 R756 1 2 0_0402_5%
VCCIO_18 VCCSA_SENSE VCCSA_SENSE <91>
J21 M37 R757 1 2 0_0402_5%
VCCIO_19 VSSSA_SENSE VSSSA_SENSE <91>
J26
J27 VCCIO_20 H14
VCCIO_21 VCCIO_SENSE VCCCPUIO_SENSE <95>
J14
VSSIO_SENSE VSSCPUIO_SENSE <95>
VCCST
1
B B
9 OF 14 100_0402_5% 100_0402_5%
R27 R28
1U_0402_6.3V6-K
2
@
C4
RESISTORS CLOSE TO CPU PINS
A A

CPU SKL-H : VCCSA/VCCIO/VDDQ
Issued Date 2015/07/16 Deciphered Date 2016/01/16
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5 4 3 2 1
5 4 3 2 1
Walter Unique
D D
U1J SKYLAKE_HALO
BGA1440
BJ17
BJ19 VCCOPC_1
BJ20 VCCOPC_2
BK17 VCCOPC_3
BK19 VCCOPC_4
BK20 VCCOPC_5
BL16 VCCOPC_6
BL17 VCCOPC_7
BL18 VCCOPC_8
BL19 VCCOPC_9
BL20 VCCOPC_10
BL21 VCCOPC_11
BM17 VCCOPC_12
BN17 VCCOPC_13
VCCOPC_14
BJ23
BJ26 RSVD_1
BJ27 RSVD_2
BK23 RSVD_3
BK26 RSVD_4
BK27 RSVD_5
BL23 RSVD_6
BL24 RSVD_7
BL25 RSVD_8
BL26 RSVD_9
BL27 RSVD_10
BL28 RSVD_11
C BM24 RSVD_12 C
RSVD_13
BL15
BM16 VCCOPC_SENSE
VSSOPC_SENSE
BL22
BM22 RSVD_14
RSVD_15
BP15
BR15 VCCEOPIO_1
BT15 VCCEOPIO_2
VCCEOPIO_3
BP16
BR16 RSVD_16
BT16 RSVD_17
RSVD_18
BN15
BM15 VCCEOPIO_SENSE
VSSEOPIO_SENSE
BP17
BN16 RSVD_19
RSVD_20
BM14
BL14 VCC_OPC_1P8_1
VCC_OPC_1P8_2
BJ35
BJ36 RSVD_21
RSVD_22
B B
AT13
AW13 ZVM#
MSM#
AU13
AY13 ZVM2#
MSM2#
R155 2 1 49.9_0402_1% OPC_RCOMP BT29
R156 2 1 49.9_0402_1% OPCE_RCOMP BR25 OPC_RCOMP
R281 2 1 49.9_0402_1% OPCE_RCOMP2 BP25 OPCE_RCOMP
OPCE_RCOMP2
10 OF 14
@
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 CPU SKL-H : VCCOPC/RSVD
5 4 3 2 1
5 4 3 2 1
Payton Common
D D
U1K SKYLAKE_HALO
BGA1440
D1 BM33
E1 RSVD_TP_1 RSVD_TP_7 BL33
E3 RSVD_TP_2 RSVD_TP_8
E2 RSVD_TP_3 BJ14
RSVD_TP_4 RSVD_TP_9 BJ13
BR1 RSVD_TP_10
BT2 RSVD_TP_5 BK28
RSVD_TP_6 RSVD_43 BJ28
BN35 RSVD_44
RSVD_23 BJ18
J24 VSS_447
H24 RSVD_24 BJ16
C BN33 RSVD_25 RSVD_TP_11 BK16 C
BL34 RSVD_26 RSVD_TP_12
RSVD_27
N29 BK24
R14 RSVD_28 RSVD_TP_13 BJ24
AE29 RSVD_29 RSVD_TP_14
AA14 RSVD_30 BK21
RSVD_31 RSVD_45 BJ21
Test_Point_40MIL TP34 1 A36 RSVD_46
Test_Point_40MIL TP33 1 A37 RSVD_32 BT17
RSVD_33 RSVD_47 BR17
H23 RSVD_48
<22> PCH_2_CPU_TRIGGER R590 PROC_TRIGIN
2 1 30_0402_1% J23 BK18
<22> CPU_2_PCH_TRIGGER PROC_TRIGOUT VSS_448
F30 BJ34
E30 RSVD_34 RSVD_TP_15 BJ33
RSVD_35 RSVD_TP_16
B30
C30 RSVD_36
RSVD_37 G13
G3 RSVD_49 AJ8
J3 RSVD_38 RSVD_50 BL31
RSVD_39 RSVD_51
B2
NCTF_1 B38
NCTF_2 BP1 TP967 1 Test_Point_20MIL
BR35 NCTF_3 BR2
BR31 RSVD_40 NCTF_4 C1 TP966 1 Test_Point_20MIL
BH30 RSVD_41 NCTF_5 C38
RSVD_42 11 OF 14 NCTF_6
B B
@
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 CPU SKL-H : RSVD
5 4 3 2 1
5 4 3 2 1
Payton Common
D75
2 1
<18,32,46> TBT_SNK0_DPHPD
RB521CS-30GT2RA_VMN2-2
D D
D76
2 1 MUX_DP_HPD
<18,32,46> TBT_SNK1_DPHPD
100K_0402_5%
1
D77
R830
2 1
<18,32,43> EXT_DP_HPD
2
VCC3M
Need to check target device

U2 position to assign
1 5
NC VCC
-PLTRST 2 R29 1 2 33_0402_5%
IN_A -PLTRST_FAR <24,46,52,56,60,62>
U3A SPT-H_PCH 3 4
GND OUT_Y
BD17 BB27 R30 1 2 33_0402_5%
GPP_A11/PME# GPP_B13/PLTRST# -PLTRST_NEAR <61,64,75,82,83,84>
TC7SG17FE_SON5
100P_0402_50V8-J
100P_0402_50V8-J
AG15 1 1
AG14 RSVD_1 P43
RSVD_2 GPP_G16/GSXCLK
C5
C6
AF17 R39
AE17 RSVD_3 GPP_G12/GSXDOUT R36
RSVD_4 GPP_G13/GSXSLOAD R42 2 2
AR19 GPP_G14/GSXDIN R41
C AN17 TP2 GPP_G15/GSXSRESET# C
TP1
<26,82> SPI_MOSI_IO0 BB29 AF41 SYSTEM_DISPLAY_HPD R10045 1 2 0_0402_5% MUX_DP_HPD

BE30 SPI0_MOSI GPP_E3/CPU_GP0 AE44
<26,82> SPI_MISO_IO1 SPI0_MISO GPP_E7/CPU_GP1
<26> -SPI_CS0 BD31 BC23
BC31 SPI0_CS0# GPP_B3/CPU_GP2 BD24
<26,82> SPI_CLK SPI0_CLK GPP_B4/CPU_GP3
AW31
CS0# for SPI ROM, CS2# for dTPM SPI0_CS1# BC36
BC29 GPP_H18/SML4ALERT# BE34
<24,26> SPI_IO2 SPI0_IO2 GPP_H17/SML4DATA -EXC_PWR_SHDN <64>
<26> SPI_IO3 BD30 BD39 -VGA_DISABLE <34>
AT31 SPI0_IO3 GPP_H16/SML4CLK BB36
<82> -SPI_CS2 SPI0_CS2# GPP_H15/SML3ALERT# BA35
<74> DOCKID[3:0] DOCKID1 AN36 GPP_H14/SML3DATA BC35 R785 1 2 0_0402_5%
GPP_D1/SPI1_CLK GPP_H13/SML3CLK -DGFX_OUTPUT_ENABLE <41>to DP Bus Switch
DOCKID0 AL39 BD35 Leave as NC
DOCKID3 AN41 GPP_D0/SPI1_CS# GPP_H12/SML2ALERT# AW35
from Docking Connector GPP_D3/SPI1_MOSI GPP_H11/SML2DATA
DOCKID2 AN38 BD34
AH43 GPP_D2/SPI1_MISO GPP_H10/SML2CLK
AG44 GPP_D22/SPI1_IO3 BE11 -INTRUDER
GPP_D21/SPI1_IO2 1 OF 12 INTRUDER#
VCC3B
SKYLAKE-H-PCH_FCBGA837
R10049 1 2 10K_0402_5% -DGFX_OUTPUT_ENABLE
RTCVCC
DOOR SWITCH -INTRUDER
1
B
CLOSE OPEN HIGH B
R31
1M_0402_5%
OPEN CLOSE LOW (ACTIVE)
to EC
2
R32 D1
3 2 1 2 1 2 -INTRUDER_EC <77>
1000P_0402_25V7-K
0_0402_5% 2
4 1
C7
SPVR310100_4P SW1 1
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 PCH SKL-H : SPI
5 4 3 2 1
5 4 3 2 1
Payton Common
Flexible I/O Configuration (v0.51) USB2.0 Configuration (v0.51) PCIE Configuration (v0.51) USB3.0 Configuration (v0.51)
I/O High Speed Signals Configuration Net Name USB2 # Assignment OCx # PCIE # High Speed Signals GEN
USB 3# High Speed Signals
Port 1 - 6 Please see Page 19 USB2 1 System Port 1 0 PCIE 1 USB3 1 - 6 Please see Page 19
PCIE1_EXP_SLOT
Port 7 USB3 7 / PCIE 1 USB3 7 or PCIE 1 USB2 2 System Port 2 1 PCIE 2
D USB3 7 D
Port 8 USB3 8 / PCIE 2 USB3 8 USB2 3 WWAN PCIE 3 WLAN Card 2 USB3 8
PCIE3_WLAN_SLOT
Port 9 USB3 9 / PCIE 3 PCIE 3 USB2 4 DOCK PCIE 4 GBE
USB3 9
PCIE4_GBE
Port 10 USB3 10 / PCIE 4 (GBE) GBE USB2 5 System Port 3 2 PCIE 5 Thunderbolt 1 3 USB3 10
PCIE5_L0_TBT
Port 11 PCIE 5 (GBE) PCIE 5 USB2 6 System Port 4 3 PCIE 6 Thunderbolt 2
PCIE5_L1_TBT
Port 12 PCIE 6 PCIE 6 USB2 7 Reserved PCIE 7 Thunderbolt 3
PCIE5_L2_TBT
Port 13 PCIE 7 PCIE 7 USB2 8 Camera PCIE 8 Thunderbolt 4
PCIE5_L3_TBT
Port 14 PCIE 8 PCIE 8 USB2 9 Finger print PCIE 9 - 20 Please see Page 16
USB2 10 Touch panel
USB2 11 Smart Card VCC3_SUS
USB2 12 Reserved
USB2 13 Color Sensor
USB2 14 WLAN
R33
R34
R35
R36
R37
R38
R39
2
2
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
1
1
C C
U3B SPT-H_PCH
DMI_RXN0 L27
<5> DMI_RXN0 DMI_RXN0
DMI_RXP0 N27 AF5
<5> DMI_RXP0 DMI_RXP0 USB2N_1 USBP1-_SYSP1 <54>
DMI_TXN0 C27 AG7
<5> DMI_TXN0 DMI_TXN0 USB2P_1 USBP1+_SYSP1 <54>
DMI_TXP0 B27 AD5
<5> DMI_TXP0 DMI_TXP0 USB2N_2 USBP2-_SYSP2 <54>
DMI_RXN1 E24 AD7
<5> DMI_RXN1 DMI_RXN1 USB2P_2 USBP2+_SYSP2 <54>
DMI_RXP1 G24 AG8
<5> DMI_RXP1 DMI_RXP1 USB2N_3 USBP3-_WWAN <61>
DMI_TXN1 B28 AG10
<5> DMI_TXN1 DMI_TXN1 USB2P_3 USBP3+_WWAN <61>
DMI_TXP1 A28 AE1
<5> DMI_TXP1 DMI_TXP1 USB2N_4 USBP4-_DOCK <74>
DMI_RXN2 G27 DMI AE2
<5> DMI_RXN2 DMI_RXN2 USB2P_4 USBP4+_DOCK <74>
DMI_RXP2 E26 AC2
<5> DMI_RXP2 DMI_RXP2 USB2N_5 USBP5-_SYSP3 <55>
DMI_TXN2 B29 AC3
<5> DMI_TXN2 DMI_TXN2 USB2P_5 USBP5+_SYSP3 <55>
DMI_TXP2 C29 AF2
<5> DMI_TXP2 DMI_TXP2 USB2N_6 USBP6-_SYSP4 <55>
DMI_RXN3 L29 AF3
<5> DMI_RXN3 DMI_RXN3 USB2P_6 USBP6+_SYSP4 <55>
DMI_RXP3 K29 AB3
<5> DMI_RXP3 DMI_RXP3 USB2N_7
DMI_TXN3 B30 USB 2.0 AB2
<5> DMI_TXN3 DMI_TXN3 USB2P_7
DMI_TXP3 A30 AL8
<5> DMI_TXP3 DMI_TXP3 USB2N_8 USBP8-_CAMERA <40>
AL7
USB2P_8 USBP8+_CAMERA <40>
R40 PCIE_RCOMPN B18 AA1
PCIE_RCOMPN USB2N_9 USBP9-_FINGER_PRINT <79>
2 1 PCIE_RCOMPP C17 AA2
PCIE_RCOMPP USB2P_9 USBP9+_FINGER_PRINT <79>
100_0402_1% AJ8
USB2N_10 USBP10-_TOUCH <40>
AJ7
USB2P_10 USBP10+_TOUCH <40>
H15 W2
<64> PCIE1_EXP_SLOT_RXN PCIE1_RXN/USB3_7_RXN USB2N_11 USBP11-_SMART_CARD <64>
G15 W3
Express Card
<64>
<64>
PCIE1_EXP_SLOT_RXP
PCIE1_EXP_SLOT_TXN C8 1 2 0.1U_0201_6.3V6-K PCIE1_EXP_SLOT_TXN_C
PCIE1_EXP_SLOT_TXP_C
A16 PCIE1_RXP/USB3_7_RXP
PCIE1_TXN/USB3_7_TXN
USB2P_11
USB2N_12
AD3
USBP11+_SMART_CARD
USBP12-_EXP_SLOT <64>
<64>
C9 1 2 0.1U_0201_6.3V6-K B16 AD2
PCIe/USB 3
<64> PCIE1_EXP_SLOT_TXP PCIE1_TXP/USB3_7_TXP USB2P_12 USBP12+_EXP_SLOT <64>
B19 V2
PCIE2_TXN/USB3_8_TXN USB2N_13 USBP13-_COLOR_SENSOR <40>
C19 V1
PCIE2_TXP/USB3_8_TXP USB2P_13 USBP13+_COLOR_SENSOR <40>
E17 AJ11
B PCIE2_RXN/USB3_8_RXN USB2N_14 USBP14-_WLAN <61> B
G17 AJ13
PCIE2_RXP/USB3_8_RXP USB2P_14 USBP14+_WLAN <61>
L17
<61> PCIE3_WLAN_SLOT_RXN PCIE3_RXN/USB3_9_RXN
K17
WLAN Card <61>
<61>
PCIE3_WLAN_SLOT_RXP
PCIE3_WLAN_SLOT_TXN C10 1 2 0.1U_0201_6.3V6-K PCIE3_WLAN_SLOT_TXN_C
PCIE3_WLAN_SLOT_TXP_C
B20 PCIE3_RXP/USB3_9_RXP
<61> PCIE3_WLAN_SLOT_TXP C11 1 2 0.1U_0201_6.3V6-K C20 AD43
E20 PCIE3_TXP/USB3_9_TXP GPP_E9/USB2_OC0# AD42 -USB_PORT0_OC0 <54>
<56> PCIE4_GBE_RXN G19 PCIE4_RXN/USB3_10_RXN GPP_E10/USB2_OC1# AD39 -USB_PORT1_OC1 <54>
GbE <56>
<56>
PCIE4_GBE_RXP
PCIE4_GBE_TXN C12 1 2 0.1U_0201_6.3V6-K PCIE4_GBE_TXN_C
PCIE4_GBE_TXP_C
B21 PCIE4_RXP/USB3_10_RXP
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
AC44 -USB_PORT2_OC2
-USB_PORT3_OC3
<55>
<55>
C13 1 2 0.1U_0201_6.3V6-K A21 Y43
<56> PCIE4_GBE_TXP PCIE4_TXP/USB3_10_TXP GPP_F15/USB2_OCB_4 PLANARID3 <18>
K19 Y41
<46> PCIE5_L0_TBT_RXN PCIE5_RXN GPP_F16/USB2_OCB_5
L19 W44
<46> PCIE5_L0_TBT_RXP PCIE5_RXP GPP_F17/USB2_OCB_6
C14 2 1 0.22U_0201_6.3V6-K PCIE5_L0_TBT_TXN_C D22 W43
<46> PCIE5_L0_TBT_TXN PCIE5_TXN GPP_F18/USB2_OCB_7
C15 2 1 0.22U_0201_6.3V6-K PCIE5_L0_TBT_TXP_C C22
<46> PCIE5_L0_TBT_TXP PCIE5_TXP
G22
<46> PCIE5_L1_TBT_RXN E22 PCIE6_RXN AG3 USB2_COMP R41 1 2 113_0402_1%
<46> PCIE5_L1_TBT_RXP C16 2 1 0.22U_0201_6.3V6-K PCIE5_L1_TBT_TXN_C B22 PCIE6_RXP USB2_COMP AD10
Thunderbolt <46>
<46>
PCIE5_L1_TBT_TXN
PCIE5_L1_TBT_TXP
C17 2 1 0.22U_0201_6.3V6-K PCIE5_L1_TBT_TXP_C A23 PCIE6_TXN
PCIE6_TXP
USB2_VBUSSENSE
RSVD_AB13
AB13
Leave RSVD_AB13 NC
L22 AG2
x 4 <46>
<46>
PCIE5_L2_TBT_RXN
PCIE5_L2_TBT_RXP C18 2 1 0.22U_0201_6.3V6-K PCIE5_L2_TBT_TXN_C
K22
C23
PCIE7_RXN
PCIE7_RXP
USB2_ID
<46> PCIE5_L2_TBT_TXN PCIE7_TXN

C19 2 1 0.22U_0201_6.3V6-K PCIE5_L2_TBT_TXP_C B23
<46> PCIE5_L2_TBT_TXP PCIE7_TXP
K24 BD14
<46> PCIE5_L3_TBT_RXN PCIE8_RXN GPD7/RSVD
1
L24
<46> PCIE5_L3_TBT_RXP C20 2 1 0.22U_0201_6.3V6-K PCIE5_L3_TBT_TXN_C C24 PCIE8_RXP R845 R10066
<46> PCIE5_L3_TBT_TXN PCIE8_TXN
C21 2 1 0.22U_0201_6.3V6-K PCIE5_L3_TBT_TXP_C B24 0_0402_5% 1K_0402_1%
<46> PCIE5_L3_TBT_TXP PCIE8_TXP 2 OF 12
2
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 PCH SKL-H : DMI/PCIE/USB
5 4 3 2 1
5 4 3 2 1
PCIE / SATA Configuration (v0.51)
Payton Common I/O

Port 15
High Speed Signals
SATA 0A / PCIE 9
Configuration
M.2 SSD1 (L0) / SATA0A
GEN
3/3 VCC3_SUS VCC3B VCCST
Port 16 SATA 1A / PCIE 10 M.2 SSD1 (L1)
Port 17 / PCIE 11 M.2 SSD1 (L2)
1 R10055
1 R10056
2 R768
Port 19 SATA 0B / PCIE 13 Media Card 2
1 R43
1 R44
1 R46
1 R47
1 R45
Port 20 SATA 1B / PCIE 14 Reserved ---
D D
Port 21 SATA 2 / PCIE 15 SATA2 for HDD1 3

Port 22 SATA 3 / PCIE 16 SATA3 for HDD2 3
10K_0402_5% 2
10K_0402_5% 2
10K_0402_5% 2
10K_0402_5% 2
10K_0402_5% 2
10K_0402_5% 2
10K_0402_5% 1
1K_0402_5% 2
Port 23 SATA 4 / PCIE 17 M.2 SSD2 (L0) / SATA4 3
VCC3_SUS Port 24 SATA 5 / PCIE 18 M.2 SSD2 (L1)
1
R42 @
10K_0402_5%
U3C SPT-H_PCH
2
AV2 G31
<61> CL_CLK_WLAN CL_CLK PCIE9_RXN/SATA0A_RXN PCIE9L0_SATA0A_MD2_SSD1_RXN <60>
AV3 H31 0.22U_0201_6.3V6-K
from / to WLAN <61>
<61>
CL_DATA_WLAN
-CL_RST_WLAN
AW2 CL_DATA
CL_RST#
CLINK PCIE9_RXP/SATA0A_RXP
PCIE9_TXN/SATA0A_TXN
C31 PCIE9L0_SATA0A_MD2_SSD1_TXN_C
B31 PCIE9L0_SATA0A_MD2_SSD1_TXP_C
1
1
2 C22
2 C23
PCIE9L0_SATA0A_MD2_SSD1_RXP
PCIE9L0_SATA0A_MD2_SSD1_TXN
M.2 SSD1 L0
<60>
<60>
PCIE9_TXP/SATA0A_TXP PCIE9L0_SATA0A_MD2_SSD1_TXP <60>
R44 0.22U_0201_6.3V6-K
R43 GPP_G8/FAN_PWM_0
U39 GPP_G9/FAN_PWM_1 G29
GPP_G10/FAN_PWM_2 PCIE10_RXN/SATA1A_RXN PCIE9L1_MD2_SSD1_RXN <60>
N42 E29 0.22U_0201_6.3V6-K
U43
GPP_G11/FAN_PWM_3
FAN
PCIE10_RXP/SATA1A_RXP
PCIE10_TXN/SATA1A_TXN
C32 PCIE9L1_MD2_SSD1_TXN_C
B32 PCIE9L1_MD2_SSD1_TXP_C
1
1
2 C24
2 C25
PCIE9L1_MD2_SSD1_RXP
PCIE9L1_MD2_SSD1_TXN
<60>
<60>
M.2 SSD1 L1
GPP_G0/FAN_TACH_0 PCIE10_TXP/SATA1A_TXP PCIE9L1_MD2_SSD1_TXP <60>
U42 0.22U_0201_6.3V6-K
U41 GPP_G1/FAN_TACH_1 F41
GPP_G2/FAN_TACH_2 PCIE15_RXN/SATA2_RXN SATA2_HDDBAY1_RXN <65>
M44 E41
U36
P44
GPP_G3/FAN_TACH_3
GPP_G4/FAN_TACH_4
PCIE15_RXP/SATA2_RXP
PCIE15_TXN/SATA2_TXN
B39 SATA2_TXN_C
A39 SATA2_TXP_C
0.01U_0201_6.3V7-K 1 2 C26
SATA2_HDDBAY1_RXP
SATA2_HDDBAY1_TXN
<65>
<65>
SATA2 HDD1
0.01U_0201_6.3V7-K 1 2 C27 SATA2_HDDBAY1_TXP <65>
C T45 GPP_G5/FAN_TACH_5 PCIE15_TXP/SATA2_TXP C
T44 GPP_G6/FAN_TACH_6 D43
SATA3_HDDBAY2_RXN <66>
PCIe/SATA
GPP_G7/FAN_TACH_7 PCIE16_RXN/SATA3_RXN E42
<60> PCIE9L2_MD2_SSD1_TXP C28 1
1
2 0.22U_0201_6.3V6-K PCIE9L2_MD2_SSD1_TXP_C B33
2 0.22U_0201_6.3V6-K PCIE9L2_MD2_SSD1_TXN_C C33 PCIE11_TXP
A41 SATA3_TXN_C
A40 SATA3_TXP_C
0.01U_0201_6.3V7-K 1 2 C29
SATA3_HDDBAY2_RXP
SATA3_HDDBAY2_TXN
<66>
<66>
SATA3 HDD2
Walter Only
C30 0.01U_0201_6.3V7-K 1 2 C31
M.2 SSD1 L2
<60>
<60>
K31 PCIE11_TXN
PCIE11_RXP
PCIE16_TXP/SATA3_TXP SATA3_HDDBAY2_TXP <66>
L31 H42
<60> PCIE9L2_MD2_SSD1_RXN PCIE11_RXN PCIE17_RXN/SATA4_RXN PCIE17L0_SATA4_MD2_SSD2_RXN <60>
H40 0.22U_0201_6.3V6-K
AB33
AB35 GPP_F10/SCLOCK
E45 PCIE17L0_SATA4_MD2_SSD2_TXN_C
F45 PCIE17L0_SATA4_MD2_SSD2_TXP_C
1
1
2 C32
2 C33
PCIE17L0_SATA4_MD2_SSD2_RXP
PCIE17L0_SATA4_MD2_SSD2_TXN
M.2 SSD2 L0
<60>
<60>
<61> WWAN_CFG3 GPP_F11/SLOAD PCIE17_TXP/SATA4_TXP PCIE17L0_SATA4_MD2_SSD2_TXP <60>
AA44 0.22U_0201_6.3V6-K
<18> PLANARID1 GPP_F13/SDATAOUT0
AA45 K37
<18> PLANARID0 GPP_F12/SDATAOUT1 PCIE18_RXN/SATA5_RXN PCIE17L1_MD2_SSD2_RXN <60>
G37 0.22U_0201_6.3V6-K PCIE17L1_MD2_SSD2_RXP <60>
B38
C38 PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN
G45 PCIE17L1_MD2_SSD2_TXN_C
G44 PCIE17L1_MD2_SSD2_TXP_C
1
1
2 C34
2 C35
PCIE17L1_MD2_SSD2_TXP
<60>
<60>
M.2 SSD2 L1
D39 PCIE14_TXP/SATA1B_TXP PCIE18_TXP/SATA5_TXP 0.22U_0201_6.3V6-K
E37 PCIE14_RXN/SATA1B_RXN AD44 -SATALED
PCIE14_RXP/SATA1B_RXP GPP_E8/SATALED# AG36
GPP_E0/SATAXPCIE0/SATAGP0 -PCIE_DETECT_SSD1 <60>
C37 1 2 0.1U_0201_10V6-K PCIE13_MEDIACARD_TXN_C C36 AG35
<62> PCIE13_MEDIACARD_TXN PCIE13_TXN/SATA0B_TXN GPP_E1/SATAXPCIE1/SATAGP1
C36 1 2 0.1U_0201_10V6-K PCIE13_MEDIACARD_TXP_C B36 AG39
Media Card <62>
<62>
PCIE13_MEDIACARD_TXP
PCIE13_MEDIACARD_RXN
G35 PCIE13_TXP/SATA0B_TXP
PCIE13_RXN/SATA0B_RXN
GPP_E2/SATAXPCIE2/SATAGP2
GPP_F0/SATAXPCIE3/SATAGP3
AD35
E35 AD31
<62> PCIE13_MEDIACARD_RXP PCIE13_RXP/SATA0B_RXP GPP_F1/SATAXPCIE4/SATAGP4 -PCIE_DETECT_SSD2 <60>
AD38
C38 1 2 0.22U_0201_6.3V6-K PCIE9L3_MD2_SSD1_TXP_C A35 GPP_F2/SATAXPCIE5/SATAGP5 AC43 -MIC_HW_EN
<60> PCIE9L3_MD2_SSD1_TXP PCIE12_TXP GPP_F3/SATAXPCIE6/SATAGP6
C39 1 2 0.22U_0201_6.3V6-K PCIE9L3_MD2_SSD1_TXN_C B35 AB44
M.2 SSD1 L3 <60>
<60>
H33 PCIE12_TXN
PCIE12_RXP
GPP_F4/SATAXPCIE7/SATAGP7 -WWAN_RESET <61>
G33
<60> PCIE9L3_MD2_SSD1_RXN PCIE12_RXN W36
GPP_F21/EDP_BKLTCTL PANEL_BKLT_CTRL_I <41>
C40 1 2 0.22U_0201_6.3V6-K PCIE17L3_MD2_SSD2_TXP_CJ45 W35 To eDP
<60> PCIE17L3_MD2_SSD2_TXP PCIE20_TXP/SATA7_TXP GPP_F20/EDP_BKLTEN VGA_BLON_I <41>
C41 1 2 0.22U_0201_6.3V6-K PCIE17L3_MD2_SSD2_TXN_CK44 W42
M.2 SSD2 L3<60>
<60>
N38
N39
PCIE20_RXP/SATA7_RXP HOST
GPP_F19/EDP_VDDEN
AJ3
PANEL_POWER_ON_I <41>
604_0402_1% 1 2 R48
<60> PCIE17L3_MD2_SSD2_RXN PCIE20_RXN/SATA7_RXN THERMTRIP# -THERMTRIP <7>
B C42 1 2 0.22U_0201_6.3V6-K PCIE17L2_MD2_SSD2_TXP_CH44 AL3 B
<60> PCIE17L2_MD2_SSD2_TXP PCIE19_TXP/SATA6_TXP PECI R49 PECI <7,76>
C43 1 2 0.22U_0201_6.3V6-K PCIE17L2_MD2_SSD2_TXN_CH43 AJ4 30_0402_1% 1 2
M.2 SSD2 L2<60>
<60>
L39 PCIE19_TXN/SATA6_TXN
PM_SYNC
PLTRST_PROC#
AK2
PM_SYNC <7>
-PCH_PLTRST_PROC <7>
L37 3 OF 12 AH2 20_0402_1% 1 2 R50
<60> PCIE17L2_MD2_SSD2_RXN PCIE19_RXN/SATA6_RXN PM_DOWN PM_DOWN <7>
1
10K_0402_5%
10K_0402_5%
0_0402_5%
100K_0402_5%
100K_0402_5%
VCC3B
R51
R52
R53
R159
R285
@ @
1
R10028
100K_0402_5%
2
-SATALED_CONN <40>
1
D D
-SATALED 2 Q59 2 Q60
<60> -SATALED G G
LSK3541G1ET2L_VMT3 LSK3541G1ET2L_VMT3
S S
3
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 PCH SKL-H : SATA/PCIE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
5 4 3 2 1
5 4 3 2 1
Payton Common TABLE : Functional Strap

GPP_C5/SML0ALERT#(LPC or SPI)
HIGH eSPI is selected
LOW LPC is selected(Default)
TABLE : Functional Strap
HDA_SDO VCC3_SUS PLACE ON BOTTOM SIDE
Flash Descriptor Security Override GPP_C5/SML0ALERT#(TLS Confidentiality)
R54 R55 @
D 1 2 1 2 D
HIGH Disable Flash Descriptor Security (Override) HIGH Enable ME Crypto TLS with Confldentlality
LOW Enable Flash Descriptor Security (Default) 1K_0402_5% 0_0402_5% LOW Disable ME Crypto TLS(Default)
VCC3_SUS
HDA_SDO is used to update the Descriptor and/or the
ME regions of the SPI after MFG Done bit is set. TP5 TP6
1 1
Test_Point_20MIL Test_Point_20MIL
TEST PAD
1K_0402_5%
BOTTOM SIDE
R56
@
C44
DO NOT MOVE AFTER FIX
1 2
2
47P_0402_50V8-J U3D SPT-H_PCH
<67> HDA_BCLK R57 1 2 33_0402_5% HDA_BCLK_R BA9 BB17

R58 1 2 33_0402_5% -HDA_RST_R BD8 HDA_BCLK GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF# AW22 -CLKRUN
<67> -HDA_RST HDA_RST# GPP_A8/CLKRUN# -CLKRUN <75,83> from LPC Device(EC)
HDA_SDIN0 BE7
<67> HDA_SDIN0 HDA_SDI0
BC8
HDA_SDI1 GPD11/LANPHYPC
AR15 LANPHYPC <56> to GBE
<67> HDA_SDO R59 1 2 33_0402_5% HDA_SDO_R BB7 AV13 -PCH_SLP_WLAN <76> to M.2 WLAN
R60 1 2 33_0402_5% HDA_SYNC_R BD9 HDA_SDO GPD9/SLP_WLAN#
<67> HDA_SYNC HDA_SYNC BC14 -DRAMRST to DIMM/SMBU SW
DRAM_RESET# -DRAMRST <27,28,29,30>
BD1 BD23
20140730: As of now, we cannot get information about these pins Leave RSVD_BD1/BE2 NC RSVD_BD1 GPP_B2/VRALERT#
BE2 AL27
from SKL-H RVP and other documents. We need to confirm about them later. RSVD_BE2 GPP_B1 AR27 SKL-H PCH doenn't
C PROC_AUDIO_SDO_CPU R61 2 1 30_0402_1% PROC_AUDIO_SDO_PCH AM1 AUDIO GPP_B0 N44 -GPU_EVENT require CORE VDD C
<6> PROC_AUDIO_SDO_CPU DISPA_SDO GPP_G17/ADR_COMPLETE -GPU_EVENT <34>
<6> PROC_AUDIO_SDI_CPU PROC_AUDIO_SDI_CPU AN2 AN24 to PHY PLL power FET
PROC_AUDIO_CLK_CPU R62 2 1 30_0402_1% PROC_AUDIO_CLK_PCH AM2 DISPA_SDI GPP_B11 AY1 R63 1 2 0_0402_5%
<6> PROC_AUDIO_CLK_CPU DISPA_BCLK SYS_PWROK BPWRG <24,76,83,85> from ASIC
PLACE NEAR PCH AL42 BC13 -PCIE_WAKE from M.2 WLAN Slot
GPP_D8/I2S0_SCLK WAKE# -PCIE_WAKE <46,61,64,84>
AN42 BC15 to ASIC
GPP_D7/I2S0_RXD GPD6/SLP_A# -PCH_SLP_M <84>
DDI_PRIORITY2 IS DESIGN HOOK FOR WALTER. AM43 AV15 -PCH_SLP_LAN to ASIC
GPP_D6/I2S0_TXD SLP_LAN# -PCH_SLP_LAN <77>
THIS WILL BE REMOVED FORM PAYTON FVT. AJ33 BC26
GPP_D5/I2S0_SFRM GPP_B12/SLP_S0# -PCH_SLP_S0 <95,104>
AH44 AW15 to EC/FPR/ASIC/DebugPort
PAYTON HAS HDMI PORT ON DOCK ALWAYS THEN DON'T NEED THIS FUNCTION AJ35 GPP_D20/DMIC_DATA0 GPD4/SLP_S3# BD15
-PCH_SLP_S3 <46,76,84,95>
GPP_D19/DMIC_CLK0 GPD5/SLP_S4# -PCH_SLP_S4 <76,84> to EC/ASIC/DebugPort
DDI_PRIORITY2 AJ38 BA13 to ASIC
<43> DDI_PRIORITY2 GPP_D18/DMIC_DATA1 GPD10/SLP_S5# -PCH_SLP_S5 <84>
AJ42
GPP_D17/DMIC_CLK1 AN15
GPD8/SUSCLK SUSCLK_32K <61,75> to EC/ASIC/WLAN
BD13 from ASIC
GPD0/BATLOW# -BATLOW <46,77>
BB19 -SUSACK R64 1 2 0_0402_5%
BC10 GPP_A15/SUSACK# BD19 -SUSWARN
<25> -RTCRST RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK
From RTC Reset circuits<25> BB10
-SRTCRST SRTCRST#
From CPU DCDC R65 1 2 0_0402_5% AW11 BD11 -LANWAKE from GBE
<24,91> CPUCORE_PWRGD PCH_PWROK GPD2/LAN_WAKE# -LANWAKE <56>
BA11 BB15 from ASIC
<24,76> -RSMRST RSMRST# GPD1/ACPRESENT AC_PRESENT <76>
From ASIC BB13 to EC
SLP_SUS# -PCH_SLP_SUS <76>
R66 1 2 0_0402_5% AV11 AT13 from EC
<76,85> MPWRG DSW_PWROK GPD3/PWRBTN# -PWRSW_EC <76>
From ASIC -SMB_ALERT BB41 AW1 from XDP port
GPP_C2/SMBALERT# SYS_RESET# -XDP_DBR <24>
SMB_CLK AW44 BD26
SMBUS
<83> SMB_CLK GPP_C0/SMBCLK GPP_B14/SPKR PCH_SPKR <72> to Audio Mixer
From/to DIMM SMB_DATA BB43 AM3 PROCPWRGD_PCH R72 1 2 0_0402_5%
<83> SMB_DATA GPP_C1/SMBDATA PROCPWRGD PROCPWRGD_CPU <7>
BA40
and TP SML0_CLK AY44 GPP_C5/SML0ALERT# AT2 Test_Point_32MIL 1 TP59
<56> SML0_CLK GPP_C3/SML0CLK ITP_PMODE
From/to GBE SML0_DATA BB39 AR3
<56> SML0_DATA GPP_C4/SML0DATA JTAGX JTAGX <24>
PCHHOT# AT27 JTAG AR2
GPP_B23/SML1ALERT#/PCHHOT# JTAG_TMS PCH_TMS <24>
<76> EC_SCL2 EC_SCL2 AW42 AP1
GPP_C6/SML1CLK JTAG_TDO PCH_TDO <24> to/from debug port
From/to EC EC_SDA2 AW45 AP2
<76> EC_SDA2 GPP_C7/SML1DATA JTAG_TDI PCH_TDI <24>
AN3
B JTAG_TCK PCH_TCK <24> B
4 OF 12
VCC3_SUS SKYLAKE-H-PCH_FCBGA837 GPP_B14/SPKR(Top Swap Owerride)
VCC1R0_SUS
HIGH Enable "TOP Swap" Mode
2
R819 @ TP987 1 Test_Point_12MIL -PCH_SLP_S4
VCC3_SUS 2 1 PCHHOT# TP988 1 Test_Point_12MIL -PCH_SLP_S5 R820 R821 R822 LOW Disable "TOP Swap" Mode (Default by Internal PD)
TP989 1 Test_Point_12MIL -PWRSW_EC 51_0402_1% 51_0402_1% 51_0402_1%
150K_0402_5% TP990 1 Test_Point_12MIL -PCH_SLP_M @ @ @
1
To enable DCI function
1
1
499_0402_1%
499_0402_1%
4.7K_0402_5%
4.7K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
R68
R69
R560
R559
R67
R70
R71
VCC1R2A VCC3B VCC3M

2
1
470_0402_5%
10K_0402_5%
1K_0402_5%
8.2K_0402_5%
R73
R74
R75
R76
SMB_CLK
-DRAMRST
SMB_DATA @
1
2
SML0_CLK
C9360
SML0_DATA 330P_0402_50V7-K
2
-SMB_ALERT
-PCIE_WAKE
EC_SCL2 -PCH_SLP_LAN
A A
EC_SDA2 -CLKRUN
EMI
Pullups on SMB are located in SMBUS Switch page. -DRAMRST

Issued Date 2015/07/16 Deciphered Date 2016/01/16 PCH SKL-H : AUDIO/SMBUS/JTAG
5 4 3 2 1
5 4 3 2 1
Walter Unique
D D
VCC3_SUS
1
2
3
4
1
2.2K_0201_5%
2.2K_0201_5%
DDP[B:C]_CTRLCLK/DATA
N16S@ R9927
N16S@ R9926
DDP[B:D]_HPD[0:2] 2.2K_0804_8P4R_5% PAYTON: NC
PAYTON: NC RP1 WALTER:
WALTER: N16P QUADRO = NC
N16P QUADRO = NC N16S GEFORCE= CONNECT FROM DISPLAYS
N16S@ 8
7
6
5
2
N16S GEFORCE= CONNECT FROM DISPLAYS
U3E SPT-H_PCH
BB3 TBT_SNK0_DDC_CLK <46>

N16S@ R105 1 2 0_0402_5% EXT_DP_HPD_I AW4 GPP_I7/DDPC_CTRLCLK BD6
<14,32,43> EXT_DP_HPD GPP_I0/DDPB_HPD0 GPP_I8/DDPC_CTRLDATA TBT_SNK0_DDC_DATA <46>
<14,32,46> TBT_SNK0_DPHPD N16S@ R10038 1 2 0_0402_5% TBT_SNK0_DPHPD_I AY2 BA5 I_DDPB_CTRLCLK <43>
GPP_I1/DDPC_HPD1 GPP_I5/DDPB_CTRLCLK
TBT <14,32,46> TBT_SNK1_DPHPD N16S@ R10039 1 2 0_0402_5% TBT_SNK1_DPHPD_I AV4
GPP_I2/DDPD_HPD2 GPP_I6/DDPB_CTRLDATA
BC4 I_DDPB_CTRLDATA <43>
From / to TBT TBT BA4
GPP_I3/DDPE_HPD3 GPP_I9/DDPD_CTRLCLK
BE5
BE6
C GPP_I10/DDPD_CTRLDATA C
Y44 PLANARID2 VCC3_SUS
GPP_F14 V44
GPP_F23 -SC_DTCT <64> SmartCard
W39
GPP_F22
10K_0402_5%
BD7
<41> EDP_HPD_I GPP_I4/EDP_HPD
R10021
N16S@
L43
GPP_G23 L44
GPP_G22 U35
GPP_G21 R35
2
GPP_G20 BD36 -DGFX_WITH_DISPLAYOUT
GPP_H23
10K_0402_5%
5 OF 12 GPP_H23
R10022
PAYTON: NC
N16P@
WALTER: -DGFX_WITH_DISPLAYOUT (INPUT)
SKYLAKE-H-PCH_FCBGA837 N16P QUADRO = LOW
N16S GEFORCE= HIGH
2
TABLE
Configuration -DGFX_WITH -DGFX_OUTPUT dGFX_output iGFX_output
PLANAR ID _DISPLAYOUT _DISPLAYOUT
3 2 1 0
N16S H H eDP,mDP,TBT
R79 R80 R81 R82
N16S / (Invalid) H L --- mDP,TBT
PLANARID3 1 NA NA NA NA
PLANARID3 <15>
PLANARID2 N16P L H mDP,TBT eDP
B PLANARID1 B
PLANARID1 <16> 0 ASM ASM ASM ASM
PLANARID0 N16P L L eDP,mDP,TBT
PLANARID0 <16>
(P.14)
1
R79 R80 @ R81 R82

0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% TABLE
2
LEVEL PLANARID[3..0] CPU PCH

PDV -------- -------- --------
SDV 0001b ES(Q0) ES2(C0)
FVT 0010b ES(Q0) ES2(C0)
SIT 0011b QS(R0) QS(D1)
SIT-4G 0011b QS(R0) QS(D1)
SIT-2 0011b QS(R0) QS(D1)
SVT 0100b Prod Prod
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 PCH SKL-H : DDI CONTROL
5 4 3 2 1
5 4 3 2 1
Payton Common VCC3_SUS VCC3B

I/O
Port 1
Flexible I/O Configuration (v0.51)
High Speed Signals
USB3 1 Capable of OTG
Configuration
USB3
Net Name
USB3P1_SYSP1
8.2K_0402_5%
10K_0402_5%
1
1
USB3P2_SYSP2
Port 2 USB2 3 / SSIC 1 USB3
R562
R83
USB3P3_WWAN
Port 3 USB3 3 / SSIC 2 USB3 or SSIC
2
USB3P4_DOCK
Port 4 USB3 4 USB3
D U3F SPT-H_PCH Port 5 USB3 5 USB3 USB3P5_SYSP3 D
C11 AT22 LPC_AD0 Port 6 USB3 6 USB3 USB3P6_SYSP4
LPC/eSPI
<54> USB3P1_SYSP1_TXN USB3_1_TXN GPP_A1/LAD0/ESPI_IO0 LPC_AD0 <75,83>
B11 AV22 LPC_AD1
System Port 1 <54>
<54>
USB3P1_SYSP1_TXP
USB3P1_SYSP1_RXN
B7 USB3_1_TXP GPP_A2/LAD1/ESPI_IO1 AT19 LPC_AD2
LPC_AD1
LPC_AD2
<75,83>
<75,83>
A7 USB3_1_RXN GPP_A3/LAD2/ESPI_IO2 BD16 LPC_AD3
<54> USB3P1_SYSP1_RXP USB3_1_RXP GPP_A4/LAD3/ESPI_IO3 LPC_AD3 <75,83>
B12
<54> USB3P2_SYSP2_TXN USB3_2_TXN/SSIC_1_TXN
A12 BE16
System Port 2 <54>
<54>
USB3P2_SYSP2_TXP
USB3P2_SYSP2_RXN
C8 USB3_2_TXP/SSIC_1_TXP GPP_A5/LFRAME#/ESPI_CS0# BA17
-LPC_FRAME
IRQSER
<75,83>
<75,83>
B8 USB3_2_RXN/SSIC_1_RXN GPP_A6/SERIRQ/ESPI_CS1# AW17
<54> USB3P2_SYSP2_RXP USB3_2_RXP/SSIC_1_RXP GPP_A7/PIRQA#/ESPI_ALERT0# -TPM_IRQ <82>
AT17
GPP_A0/RCIN#/ESPI_ALERT1# -KBRC <75>
USB3P6_SYSP4_TXN_I B15 BC18
USB3_6_TXN GPP_A14/SUS_STAT#/ESPI_RESET# -SUS_STAT <75,83>
USB3P6_SYSP4_TXP_I C15
System Port 4 USB3P6_SYSP4_RXN_I K15 USB3_6_TXP
USB3_6_RXN
<Walter Only>
USB
USB3P6_SYSP4_RXP_I K13 BC17 R84 1 2 0_0402_5% LPCCLK_EC_24M <75>
USB3_6_RXP GPP_A9/CLKOUT_LPC0/ESPI_CLK AV19 R85 1 2 0_0402_5%
GPP_A10/CLKOUT_LPC1 LPCCLK_DEBUG_24M <83>
USB3P5_SYSP3_TXN_I B14
USB3P5_SYSP3_TXP_I C14 USB3_5_TXN M45
System Port 3 USB3P5_SYSP3_RXN_I G13 USB3_5_TXP GPP_G19/SMI# N43
USB3_5_RXN GPP_G18/NMI#
<Walter Only> USB3P5_SYSP3_RXP_I H13
USB3_5_RXP
D13 AE45
C13 USB3_3_TXP/SSIC_2_TXP GPP_E6/DEVSLP2 AG43
A9 USB3_3_TXN/SSIC_2_TXN GPP_E5/DEVSLP1 AG42
B10 USB3_3_RXP/SSIC_2_RXP GPP_E4/DEVSLP0 AB39
DEVSLP0_MD2_SSD1 to
<60> SSD in M.2 Slot
USB3_3_RXN/SSIC_2_RXN GPP_F9/DEVSLP7 AB36
SATA
GPP_F8/DEVSLP6 WWAN_CFG0 <61>
B13 AB43
<74> USB3P4_DOCK_TXP USB3_4_TXP GPP_F7/DEVSLP5 -INT_MIC_DTCT <40>
A14 AB42
DOCK <74>
<74>
USB3P4_DOCK_TXN
USB3P4_DOCK_RXP
G11 USB3_4_TXN GPP_F6/DEVSLP4 AB41
DEVSLP4_MD2_SSD2 <60>to SSD in M.2 Slot
E11 USB3_4_RXP 6 OF 12 GPP_F5/DEVSLP3
<74> USB3P4_DOCK_RXN USB3_4_RXN
C C
VCC3M VCC3M VCC3M VCC3M

USB3.0 Redriver <Walter Only> USB3.0 Redriver <Walter Only>
Port-4 Port-3
0.1U_0402_16V7-K
1U_0402_6.3V6-K
0.1U_0402_16V7-K
1U_0402_6.3V6-K
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
1 1
2
2
R9957 @
R9966 @
C9276
C9275
R9848
C9350
C9349
R9969
2 2
1
1
U233 U234
1 8 1 8
VCC DE VCC DE
USB3P6_SYSP4_TXP_I C9284 1 2 0.1U_0402_16V7-K USB3P6_SYSP4_TXP_C 2 7 USB3P5_SYSP3_TXP_IC9294 1 2 0.1U_0402_16V7-K USB3P5_SYSP3_TXP_C 2 7
RXP TXP USB3P6_SYSP4_TXP <55> RXP TXP USB3P5_SYSP3_TXP <55>
USB3P6_SYSP4_TXN_I C9283 1 2 0.1U_0402_16V7-K USB3P6_SYSP4_TXN_C 3 6 USB3P5_SYSP3_TXN_IC9293 1 2 0.1U_0402_16V7-K USB3P5_SYSP3_TXN_C 3 6
RXN TXN USB3P6_SYSP4_TXN <55> RXN TXN USB3P5_SYSP3_TXN <55>
VCC3M R9852 1 2 4.99K_0402_1% 4 5 VCC3M R9970 1 2 4.99K_0402_1% 4 5

R9960 1 @ 2 4.99K_0402_1% OS EQ R9971 1 @ 2 4.99K_0402_1% OS EQ
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
9 10 9 10
GND1 GND2 GND1 GND2
2
2
R9959 @
R9968 @
R9958
R9967
12 11 12 11
GND4 GND3 GND4 GND3
B TUSB501DRFR_WSON8_2X2 TUSB501DRFR_WSON8_2X2 B
1
1
VCC3M VCC3M
VCC3M VCC3M
1U_0402_6.3V6-K
0.1U_0402_16V7-K
4.99K_0402_1%
4.99K_0402_1%
1
R9974 @
1U_0402_6.3V6-K
0.1U_0402_16V7-K
R9977
C9351
C9352
4.99K_0402_1%
4.99K_0402_1%
1
2
R9962 @
2
R9965
C9347
C9348
1
2 U235
1
U232 8 1
DE VCC
8 1 USB3P5_SYSP3_RXP_IC9295 1 2 0.1U_0402_16V7-K USB3P5_SYSP3_RXP_C 7 2
DE VCC TXP RXP USB3P5_SYSP3_RXP <55>
USB3P6_SYSP4_RXP_I C9287 1 2 0.1U_0402_16V7-K USB3P6_SYSP4_RXP_C 7 2 USB3P5_SYSP3_RXN_IC9296 1 2 0.1U_0402_16V7-K USB3P5_SYSP3_RXN_C 6 3
TXP RXP USB3P6_SYSP4_RXP <55> TXN RXN USB3P5_SYSP3_RXN <55>
USB3P6_SYSP4_RXN_I C9288 1 2 0.1U_0402_16V7-K USB3P6_SYSP4_RXN_C 6 3 5 4 4.99K_0402_1% 2 1 R9972 VCC3M
TXN RXN USB3P6_SYSP4_RXN <55> EQ OS 4.99K_0402_1% 2 @ 1 R9973
4.99K_0402_1%
4.99K_0402_1%
5 4 4.99K_0402_1% 2 1 R9857 VCC3M 10 9
EQ OS GND2 GND1
2
R9976 @
4.99K_0402_1% 2 @ 1 R9961
R9975
4.99K_0402_1%
4.99K_0402_1%
10 9 11 12
GND2 GND1 GND3 GND4
2
2
R9964 @
R9963
11 12
GND3 GND4 TUSB501DRFR_WSON8_2X2
1
A TUSB501DRFR_WSON8_2X2 A
1

Issued Date 2015/07/16 Deciphered Date 2016/01/16 PCH SKL-H : USB3/LPC
5 4 3 2 1
5 4 3 2 1
Payton Common
D D
U3G SPT-H_PCH
AR17
GPP_A16/CLKOUT_48
<7> CPU_REFCLK_24M G1 L1
F1 CLKOUT_CPUNSSC_P CLKOUT_ITPXDP L2
<7> -CPU_REFCLK_24M CLKOUT_CPUNSSC CLKOUT_ITPXDP_P
<7> CPU_BCLK_100M G2 J1 -CPU_PCI_BCLK_100M <7>
H2 CLKOUT_CPUBCLK_P CLKOUT_CPUPCIBCLK J2
<7> -CPU_BCLK_100M CLKOUT_CPUBCLK CLKOUT_CPUPCIBCLK_P CPU_PCI_BCLK_100M <7>
VCC1R0_SUS XTAL24_OUT A5 N7 -PCIE0_CLK_100M_UHS2 <62>
XTAL24_IN A6 XTAL24_OUT CLKOUT_PCIE_N0 N8
XTAL24_IN CLKOUT_PCIE_P0 PCIE0_CLK_100M_UHS2 <62>
R86 1 2 2.7K_0402_0.5% XCLK_BIASREF E1 L7
XCLK_BIASREF CLKOUT_PCIE_N1 L5
RTCX1 BC9 CLKOUT_PCIE_P1
RTCX2 BD10 RTCX1 D3
RTCX2 CLKOUT_PCIE_N2 -PCIE2_CLK_100M_WLAN <61>
F2
BC24 CLKOUT_PCIE_P2 PCIE2_CLK_100M_WLAN <61>
C <62> -CLKREQ_PCIE0_UHS2 GPP_B5/SRCCLKREQ0# C
AW24 E5 -PCIE3_CLK_100M_GBE <56>
AT24 GPP_B6/SRCCLKREQ1# CLKOUT_PCIE_N3 G4
<61> -CLKREQ_PCIE2_WLAN GPP_B7/SRCCLKREQ2# CLKOUT_PCIE_P3 PCIE3_CLK_100M_GBE <56>
BD25
<56> -CLKREQ_PCIE3_GBE GPP_B8/SRCCLKREQ3#
BB24 D5 -PCIE4_CLK_100M_MD2_SSD1 <60>
<60> -CLKREQ_PCIE4_MD2_SSD1 GPP_B9/SRCCLKREQ4# CLKOUT_PCIE_N4
BE25 E6
<31> -CLKREQ_PCIE5_PEG GPP_B10/SRCCLKREQ5# CLKOUT_PCIE_P4 PCIE4_CLK_100M_MD2_SSD1 <60>
AT33
<64> -CLKREQ_PCIE6_EXPCARD GPP_H0/SRCCLKREQ6#
AR31 D8 -PCIE5_CLK_100M_PEG <31>
<60> -CLKREQ_PCIE7_MD2_SSD2 GPP_H1/SRCCLKREQ7# CLKOUT_PCIE_N5
BD32 D7
<46> -CLKREQ_PCIE8_TBT GPP_H2/SRCCLKREQ8# CLKOUT_PCIE_P5 PCIE5_CLK_100M_PEG <31>
BC32
BB31 GPP_H3/SRCCLKREQ9# R8
GPP_H4/SRCCLKREQ10# CLKOUT_PCIE_N6 -PCIE6_CLK_100M_EXPCARD <64>
BC33 R7
BA33 GPP_H5/SRCCLKREQ11# CLKOUT_PCIE_P6 PCIE6_CLK_100M_EXPCARD <64>
GPP_H6/SRCCLKREQ12#
1
AW33 U5 -PCIE7_CLK_100M_MD2_SSD2 <60>

R10068 BB33 GPP_H7/SRCCLKREQ13# CLKOUT_PCIE_N7 U7
BD33 GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_P7 PCIE7_CLK_100M_MD2_SSD2 <60>
100K_0402_5%
External Pull on CLKREQ# should be placed in device page, GPP_H9/SRCCLKREQ15# W10 -PCIE8_CLK_100M_TBT <46>
CLKOUT_PCIE_N8
as power railis may be different from PCH-H.. R13 W11
2
R11 CLKOUT_PCIE_N15 CLKOUT_PCIE_P8 PCIE8_CLK_100M_TBT <46>

CLKOUT_PCIE_P15 N3
P1 CLKOUT_PCIE_N9 N2
VCC3B R2 CLKOUT_PCIE_N14 CLKOUT_PCIE_P9
CLKOUT_PCIE_P14 P3
W7 CLKOUT_PCIE_N10 P2
Y5 CLKOUT_PCIE_N13 CLKOUT_PCIE_P10
R10046 2 1 10K_0402_5% -CLKREQ_PCIE5_PEG CLKOUT_PCIE_P13 R3
U2 CLKOUT_PCIE_N11 R4
U3 CLKOUT_PCIE_N12 CLKOUT_PCIE_P11
CLKOUT_PCIE_P12 7 OF 12
C46 1 2 10P_0402_50V8-J RTCX1
1
1
R87
B 32.768KHZ_9PF_1TJH090DR1A0001 10M_0402_5% B
Y1
2
C47 1 2 10P_0402_50V8-J RTCX2
Y1 ->
KDS 1TJH090DR1A0001
PCIE Clock Assignment
Clock 0 : UHS II
Clock 1 : NA
Clock 2 : Wireless LAN M.2 Slot
Clock 3 : Giga Bit Ethernet
C48 1 2 3.9P_0402_50V8-B XTAL24_OUT Clock 4 : PCIe SSD on M.2 Slot
Clock 5 : Discrete GFX(MXM or Onboard)
1
24MHZ_6PF_8Y24000010 4 2 R88 Clock 6 : Express Slot

1M_0402_5%
Clock 7 : PCIe SSD on M.2 Slot
3
Y2
Clock 8 : Thunderbolt
2
C49 1 2 3.9P_0402_50V8-B XTAL24_IN

Clock 9 - 15 : NA
Y1 ->
TXC 8Y24000010
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 PCH SKL-H : CLK
5 4 3 2 1
5 4 3 2 1
Payton Common
To use eSPI, VCCPGPPA should have 1.8V
D D
0.195A
1 1
VCC1R0_SUS VCC3M C658 C659
3.137A 0.1U_0402_16V7-K 0.1U_0402_16V7-K
1.0V 2
NEAR 2
NEAR
BA31 BA31
VCC1R0_SUS
U3H SPT-H_PCH
AA23
AA26 VCCPRIM_1P0_1 0.746A
VCCPRIM_1P0_2
22U_0805_6.3V6-M
22U_0805_6.3V6-M
AA28 AL22
1U_0402_10V6-K
VCCPRIM_1P0_3 VCCPRIM_1P0_17 VCC3_SUS
CORE
AC23
1 1 1 AC26 VCCPRIM_1P0_4 BA24
NEAR
C52
C50
C51
AC28 VCCPRIM_1P0_5 VCCDSW_3P3_2 BA31
K2 VCCPRIM_1P0_6 VCCPGPPA
VCCGPIO
AE23
4.110A AE26 VCCPRIM_1P0_7 BC42
2 @ 2 @ 2 @
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
Y23 VCCPRIM_1P0_8 VCCPGPPBCH_1 BD40
1.0V Y25 VCCPRIM_1P0_9 VCCPGPPBCH_2 AJ41 1
@
1
@
1
@
1
@
1 1
VCC1R0_SUS BA29 VCCPRIM_1P0_10 VCCPGPPEF_1 AL41
C53
C54
C55
C56
C57
C58
DCPDSW_1P0 VCCPGPPEF_2
1U_0402_10V6-K
AD41 RTCVCC
C N17 VCCPGPPG AN5 C
1 VCCCLK1_1 VCCPRIM_3P3 2 2 2 2 2 2
C59
R19
U20 VCCCLK3_2
VCCCLK4_3 NEAR NEAR NEAR NEAR NEAR NEAR
V17 AD15 BC42 AJ41 AD41 AN5 BA20 AD13
2 VCCCLK2_4 VCCPRIM_1P0_15
22U_0805_6.3V6-M
R17 AD13 VCC3B

1U_0402_10V6-K
K2 VCCCLK2_5 VCCATS BA20

1 1 K3 VCCCLK5_6 VCCRTCPRIM_3P3 BA22
C61
C60
VCCCLK5_7 VCCRTC BA26

NEAR DCPRTC
BA29
0.1U_0402_25V6-K
0.1U_0402_25V6-K
1U_0402_6.3V6-K
U21 AJ20
2 2 VCCMPHY_1P0_1 VCCPRIM_1P0_11 0.029A
MPHY
U23 AJ21 1 1 1
VCCMPHY_1P0_2 VCCPRIM_1P0_12
C288
U25 AJ23
C62
C63
U26 VCCMPHY_1P0_3 VCCPRIM_1P0_13 AJ25 VCC3_SUS
NEAR PCH PKG V26 VCCMPHY_1P0_4 VCCPRIM_1P0_14
VCCMPHYPLL_1P0 A43 VCCMPHY_1P0_5 2 2 2
B43 VCCMPHYPLL_1P0_1 BE41
0.007A
C44 VCCMPHYPLL_1P0_2 VCCSPI_1 BE43
C45 VCCPCIE3PLL_1P0_1 VCCSPI_2 BE42
VCCPCIE3PLL_1P0_2 VCCSPI_3 BC44 VCC3B
VCCAPLLEBB_1P0 V28 VCCPGPPD_1 BA45 NEAR NEAR
VCCAPLLEBB_1P0 VCCPGPPD_2 BA22
USB
AC17 BC45 BA26
VCCUSB2PLL_1P0 AJ5 VCCPRIM_1P0_16 VCCPGPPD_3 BB45 VCC3B
AL5 VCCUSB2PLL_1P0_1 VCCPGPPD_4
VCCHDAPLL_1P0 AN19 VCCUSB2PLL_1P0_2 BD3
BA15 VCCHDAPLL_1P0 VCCPRIM_3P3_1 BE3
VCC3_SUS VCCHDA VCCPRIM_3P3_2
W15 BE4
1U_0402_6.3V6-K
VCC3M VCCDSW_3P3_1 8 OF 12 VCCPRIM_3P3_3
1
C514
0.1U_0402_25V6-K
2
1
B NEAR B
C64
AD13
@ 2
0.11A NEAR 0.03A 0.012A

1.0V W15 0.033A
VCC1R0_SUS
1.0V VCC1R0_SUS
VCC1R0_SUS
VCC1R0_SUS
R89 R91
R92
1 2 VCCMPHYPLL_1P0 1 2 VCCUSB2PLL_1P0
R90
1 2 VCCHDAPLL_1P0
22U_0805_6.3V6-M
1U_0402_10V6-K
22U_0805_6.3V6-M
1 2 VCCAPLLEBB_1P0
0_0603_5% 0_0603_5%
1 1 0_0603_5%
1U_0402_10V6-K
1
C67
C66
C65
0_0603_5%
1U_0402_10V6-K
1
C68
2 @ 2 @ 1
C69
2 @
2
2
NEAR PCH PIN
NEAR PCH PKG

NEAR PCH PKG
Note 1: Ampere in this page means Iccmax current described in SKL PCH H EDS r0.91 page 57.
A A
Note 2: Decoupling capacitors refers SKL H PDG r0.7 page 507.
SKL H RVP11 schematics r0.5 also referred.

Issued Date 2015/07/16 Deciphered Date 2016/01/16 PCH SKL-H : POWER
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom WALTER 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common
Test_Point_20MIL 1 TP968
D Test_Point_20MIL 1 TP970 D
U3I SPT-H_PCH U3L SPT-H_PCH U3J SPT-H_PCH
AC18 AR5 C42 AB11

AN4 VSS_1 VSS_75 AR7 D10 VSS_149 VSS_217 AB7 BD2 AR22
AN10 VSS_2 VSS_76 U15 D12 VSS_150 VSS_218 AB14 BD45 VSS_286 RSVD_7 W13
BE14 VSS_3 VSS_77 AL4 D15 VSS_151 VSS_219 AB31 BD44 VSS_287 RSVD_8 U13
BE18 VSS_4 VSS_78 AE29 D16 VSS_152 VSS_220 AB32 BE44 VSS_288 RSVD_9 P31
BE23 VSS_5 VSS_79 AE4 D17 VSS_153 VSS_221 AB38 D45 VSS_289 RSVD_10 N31
BE28 VSS_6 VSS_80 AE42 D19 VSS_154 VSS_222 AB4 A42 VSS_290 RSVD_11 Leave as NC
BE32 VSS_7 VSS_81 AF18 D21 VSS_155 VSS_223 AB5 B45 VSS_291 P27
BE37 VSS_8 VSS_82 AF20 D24 VSS_156 VSS_224 AC1 B44 VSS_292 RSVD_12 R27
BE40 VSS_9 VSS_83 AF21 D25 VSS_157 VSS_225 AC20 A4 VSS_293 RSVD_13 N29
BE9 VSS_10 VSS_84 AF23 D27 VSS_158 VSS_226 AC21 A3 VSS_294 RSVD_14 P29
C10 VSS_11 VSS_85 AF25 D29 VSS_159 VSS_227 AC25 B2 VSS_295 RSVD_15 AN29
C2 VSS_12 VSS_86 AF26 D30 VSS_160 VSS_228 AC29 A2 VSS_296 RSVD_16 R24
C28 VSS_13 VSS_87 AF28 D31 VSS_161 VSS_229 AC45 B1 VSS_297 RSVD_17 P24
C37 VSS_14 VSS_88 AF29 D33 VSS_162 VSS_230 AB8 BB1 VSS_298 RSVD_18
J7 VSS_15 VSS_89 AG11 D35 VSS_163 VSS_231 AD11 BC1 VSS_299 AT3
VSS_16 VSS_90 VSS_164 VSS_232 VSS_300 PREQ# -PCH_PREQ <24>
K10 AG13 D36 AD14 A44 AT4
VSS_17 VSS_91 VSS_165 VSS_233 VSS_301 PRDY# -PCH_PRDY <24>
K27 AG31 E13 AB15 AY5
VSS_18 VSS_92 VSS_166 VSS_234 CPU_TRST# R656 -CPU_TRST <24>
K33 AG32 E15 AD32 C1 AL2 2 1 30_0402_1%
VSS_19 VSS_93 VSS_167 VSS_235 RSVD_5 PCH_TRIGOUT PCH_2_CPU_TRIGGER <13>
K36 AG33 E31 AD33 D1 AK1
VSS_20 VSS_94 VSS_168 VSS_236 RSVD_6 PCH_TRIGIN CPU_2_PCH_TRIGGER <13>
K4 AG38 E33 AD36
K42 VSS_21 VSS_95 AG4 F44 VSS_169 VSS_237 AD4 10 OF 12
K43 VSS_22 VSS_96 AH1 F8 VSS_170 VSS_238 AD8
C L12 VSS_23 VSS_97 AH17 G42 VSS_171 VSS_239 AE18 SKYLAKE-H-PCH_FCBGA837 C
L13 VSS_24 VSS_98 AH18 G9 VSS_172 VSS_240 AE20
L15 VSS_25 VSS_99 AH20 H17 VSS_173 VSS_241 AE21
L8 VSS_28 VSS_102 AH25 H24 VSS_176 VSS_244 AL10 TP972 1 Test_Point_20MIL
M35 VSS_29 VSS_103 AH26 H27 VSS_177 VSS_245 AL11 TP973 1 Test_Point_20MIL
M42 VSS_30 VSS_104 AH28 H29 VSS_178 VSS_246 AL13 TP974 1 Test_Point_20MIL
N10 VSS_31 VSS_105 AH29 H3 VSS_179 VSS_247 AL17 TP975 1 Test_Point_20MIL
N15 VSS_32 VSS_106 AH45 H35 VSS_180 VSS_248 AL19
N19 VSS_33 VSS_107 AJ10 J10 VSS_181 VSS_249 AL24
N4 VSS_38 VSS_112 AJ26 T42 VSS_186 VSS_254 AM15
N41 VSS_39 VSS_113 AJ28 U10 VSS_187 VSS_255 AM17
N5 VSS_40 VSS_114 AJ29 U11 VSS_188 VSS_256 AM19
P17 VSS_41 VSS_115 AJ31 U14 VSS_189 VSS_257 AM22
P45 VSS_44 VSS_118 AK4 U28 VSS_192 VSS_260 AM29
R10 VSS_45 VSS_119 AK42 U29 VSS_193 VSS_261 AM45
R14 VSS_46 VSS_120 AU7 U31 VSS_194 VSS_262 AN11
R22 VSS_47 VSS_121 AV17 U32 VSS_195 VSS_263 AN22
T1 VSS_52 VSS_126 AV6 V18 VSS_200 VSS_268 AN8
T2 VSS_53 VSS_127 AW13 V20 VSS_201 VSS_269 AP11
T4 VSS_54 VSS_128 AW19 V21 VSS_202 VSS_270 AP4
B Y18 VSS_55 VSS_129 AW29 V23 VSS_203 VSS_271 AR33 B
Y20 VSS_56 VSS_130 AW37 V25 VSS_204 VSS_272 AR34
Y21 VSS_57 VSS_131 AW9 V29 VSS_205 VSS_273 AR42
Y26 VSS_58 VSS_132 AY38 V3 VSS_206 VSS_274 AR9
Y28 VSS_59 VSS_133 AY45 V45 VSS_207 VSS_275 AT10
Y29 VSS_60 VSS_134 B25 W14 VSS_208 VSS_276 AT15
A18 VSS_61 VSS_135 B3 W31 VSS_209 VSS_277 AT36
A25 VSS_62 VSS_136 B37 W32 VSS_210 VSS_278 AT9
A32 VSS_63 VSS_137 B40 W33 VSS_211 VSS_279 AU1
A37 VSS_64 VSS_138 B6 W38 VSS_212 VSS_280 AU35
AA17 VSS_65 VSS_139 BA1 W4 VSS_213 VSS_281 AU36
AA18 VSS_66 VSS_140 BB11 W8 VSS_214 VSS_282 AU39
AA20 VSS_67 VSS_141 BB16 Y17 VSS_215 VSS_283 AU45
AA21 VSS_68 VSS_142 BB21 VSS_216 VSS_284 C4
AA25 VSS_69 VSS_143 BB25 VSS_285
AA29 VSS_70 VSS_144 BB30
AA4 VSS_71 VSS_145 BB34
AA42 VSS_72 VSS_146 BC2 12 OF 12
AB10 VSS_73 VSS_147 BD43
VSS_74 VSS_148 SKYLAKE-H-PCH_FCBGA837
9 OF 12
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 PCH SKL-H : GND/RSVD
5 4 3 2 1
5 4 3 2 1
Walter Unique
PAYTON WALTER
GPP_D9 -MXM_PRESENCE -DISCRETE_PRESENCE

: Always Low
N16P N16S
GPP_D11 HIGH LOW
D D
VCC3_SUS
1
N16P@
R9881 R9928
10K_0402_5% 10K_0402_5%
U3K SPT-H_PCH
2
AT29
AR29 GPP_B22/GSPI1_MOSI AL44 -DISCRETE_PRESENCE
AV29 GPP_B21/GSPI1_MISO GPP_D9 AL36
GPP_B20/GSPI1_CLK GPP_D10 DGFX_PWRGD <110>
BC27 AL35 WALTER_P_T
GPP_B19/GSPI1_CS# GPP_D11 AJ39
GPP_D12
1
GPP_B18_NO_REBOOT BD28 N16S@
<24> GPP_B18_NO_REBOOT GPP_B18/GSPI0_MOSI
BD27 AJ43 R9929 R9882
AW27 GPP_B17/GSPI0_MISO
GPP_B16/GSPI0_CLK
GPP_D16/ISH_UART0_CTS#
GPP_D15/ISH_UART0_RTS#
AL43 Leave as NC 10K_0402_5% 0_0402_5%
AR24 AK44
GPP_B15/GSPI0_CS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL AK45
2
AV44 GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA
Leave as NC BA41 GPP_C9/UART0_TXD
GPP_C8/UART0_RXD
AU44
AV43 GPP_C11/UART0_CTS#
GPP_C10/UART0_RTS#
AU41 BC38
AT44 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H20/ISH_I2C0_SCL BB38
AT43 GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_H19/ISH_I2C0_SDA
AU43 GPP_C13/UART1_TXD/ISH_UART1_TXD BD38
C GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H22/ISH_I2C1_SCL TBT_FORCE_ON <46> C
BE39
GPP_H21/ISH_I2C1_SDA -CIO_PLUG_EVENT <46>
AN43
<75> -EC_WAKE GPP_C23/UART2_CTS#
From EC AN44
<75> -EC_SCI GPP_C22/UART2_RTS#
AR39
AR45 GPP_C21/UART2_TXD BC22
GPP_C20/UART2_RXD GPP_A23/ISH_GP5 BD18
AR41
GPP_C19/I2C1_SCL
GPP_A22/ISH_GP4
GPP_A21/ISH_GP3
BE21 Leave as NC
AR44 BD22
Leave as NC AR38 GPP_C18/I2C1_SDA
GPP_C17/I2C0_SCL
GPP_A20/ISH_GP2
GPP_A19/ISH_GP1
BD21
AT42 BB22
GPP_C16/I2C0_SDA GPP_A18/ISH_GP0 BC19
AM44 GPP_A17/ISH_GP7
AJ44 GPP_D4/ISH_I2C2_SDA/ISH_I2C3_SDA
GPP_D23/ISH_I2C2_SCL/ISH_I2C3_SCL 11 OF 12
B B
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 PCH SKL-H : GSPI/UART/I2C
5 4 3 2 1
5 4 3 2 1
Walter Unique <17> JTAGX

JTAGX R591 1 @ 2 0_0402_5% XDP_TCK
<14,26> SPI_IO2
PCH_TMS R593 1 @ 2 0_0402_5% XDP_TMS
TABLE : CPU ITP DEBUG REPORT <17> PCH_TMS
1
PCH_TDI R594 1 @ 2 0_0402_5% XDP_TDI R597
<17> PCH_TDI
1K_0402_1%
Individual DCI 2.0 -CPU_TRST R595 1 @ 2 0_0402_5% -XDP_TRST @
No use Port w/o connector <22> -CPU_TRST
2
PCH_TDO R596 1 @ 2 0_0402_5% XDP_TDO
<17> PCH_TDO
D D
R591 NO ASM NO ASM ASM -PCH_PRDY R657 1 @ 2 0_0402_5% -XDP_PRDY

<22> -PCH_PRDY
R593 NO ASM NO ASM ASM -PCH_PREQ R658 1 @ 2 0_0402_5% -XDP_PREQ
<22> -PCH_PREQ
R594 NO ASM NO ASM ASM
VCC1R0_SUS
2
R93
R102 NO ASM ASM NO ASM 51_0402_1%
@
R597 NO ASM ASM NO ASM
1
R9907 NO ASM ASM ASM
JXDP1 NO ASM ASM NO ASM
C70 NO ASM ASM NO ASM
R96 ASM ASM ASM PCH_TDI R9913 1 @ 2 0_0402_5% TDI
PCH_TDO R9915 1 @ 2 0_0402_5% TDO
C C
R9910 NO ASM ASM ASM VCCST VCC3B VCC1R0_SUS
R99 NO ASM ASM ASM
R9912 NO ASM ASM ASM 2
C70
0.1U_0402_25V6-K
10K_0402_5%
2
2
@
1
R96
R9907
R9930 NO ASM ASM ASM 51_0402_1%
@
1
R9932 NO ASM ASM ASM R9908 1 @ 2 0_0402_5% JXDP1
<17> PCH_TCK
R9909 1 @ 2 0_0402_5% 26
R9933 NO ASM ASM ASM <7> XDP_TCK
25 26 28
PCH_TMS R9911 1 @ 2 0_0402_5% 24 25 GND_2 27
R9910 1 @ 2 0_0402_5% 23 24 GND_1
<7> XDP_TMS 23
R9912 1 @ 2 0_0402_5% TDI 22
<7> XDP_TDI 22
R9934 1 @ 2 0_0402_5% 21
<7> -XDP_TRST 21
LOGIC <7> XDP_TDO R9916 1 @ 2 0_0402_5% TDO 20
19 20
18 19
TABLE : PCH ITP DEBUG REPORT <17> -XDP_DBR
R99 1 @ 2 1K_0402_5% 17 18
<14,46,52,56,60,62> -PLTRST_FAR @ 17
R9917 1 2 1K_0402_5% 16
<17,91> CPUCORE_PWRGD 16
15
No use Individual DCI 2.0 14 15
14
Port w/o connector <17,76,83,85> BPWRG
R9930 1 @ 2 0_0201_5% 13
13
12
11 12
B -RSMRST R101 1 @ 2 1K_0402_5% 10 11 B
R93 NO ASM ASM NO ASM <17,76> -RSMRST
9 10
R9931 1 @ 2 0_0402_5% 8 9
JXDP1 NO ASM ASM NO ASM <7> CFG3
7 8
6 7
R9917 NO ASM ASM NO ASM 5 6
4 5
R101 NO ASM ASM NO ASM 3 4
R9932 1 @ 2 0_0402_5% 2 3
R9908 NO ASM ASM NO ASM <7> -XDP_PRDY
R9933 1 @ 2 0_0402_5% 1 2
<7> -XDP_PREQ 1
R9911 NO ASM ASM NO ASM MOLEX_52435-2671
1
@
R9913 NO ASM ASM NO ASM R102
1K_0402_1%
R9915 NO ASM ASM NO ASM @
2
LOGIC

R821 NO ASM ASM NO ASM SHEET 17
VCC3_SUS
A
TABLE : Functional Strap A
GPP_B18/GSPI0_MOSI (No Reboot) R563

HIGH Enable "No Reboot" Mode ASM
1
LOW Disable "No Reboot" Mode (Default ) NO ASM LOGIC R563

1K_0402_5% Place near PCH
@ Title
Security Classification LC Future Center Secret Data
2
Issued Date 2015/07/16 Deciphered Date 2016/01/16 XDP CONNECTOR

GPP_B18_NO_REBOOT
GPP_B18_NO_REBOOT <23> THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom WALTER 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common
VCC3SW
1
D D
R10043
4.7K_0402_5% RTCVCC must be less than 3.2V from SKL.
RTCVCC
2
1
2
R10044
47K_0402_1% RB520CS-30GT2RA_VMN2-2 D2
1
1
C71
2
1U_0402_10V6K
2
D3
2 1
2
R107
1K_0402_5%
1
C C
JRTC1
1 R108
1 2 1 2 -RTCRST
2 -RTCRST <17>
3 20K_0402_5%
GND1 4
GND2
HIGHS_WS33021-S0351-HF 1
2
@ C72 JCMOS
1U_0402_10V6K SHORT PADS
@
1
2
R109
1 2 -SRTCRST
-SRTCRST <17>
20K_0402_5%
2
B C73 JME B
1U_0402_10V6K SHORT PADS
@
1
2
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 RTC BATTERY
5 4 3 2 1
5 4 3 2 1
Payton Common
R110 R598 U5 R592 R358
D PRE ES1 NO ASM ASM QE="1" ASM ASM D

ES1/ES2
QE= Don't LOGIC
AFTER QS ASM NO ASM Care NO ASM NO ASM
VCC3_SUS VCC3_SUS_SPI
2
D4
1
VCC3_SUS_SPI
0.1U_0402_25V6-K
0.1U_0402_25V6-K
1
1 1
1
R592 @
1
1K_0402_1% R111
C74
C75
R110 1K_0402_1% R358 @
2 2 1K_0402_1% 1K_0402_1%
2
2
2
C C
U5
8 1 -SPI_CS0_R R112 1 2 0_0402_5% -SPI_CS0
VCC CS# -SPI_CS0 <14>
SPI_IO3 R113 1 2 15_0402_5% SPI_IO3_R 7 2 SPI_MISO_IO1_R R114 1 2 15_0402_5% SPI_MISO_IO1
<14> SPI_IO3 HOLD# DO SPI_MISO_IO1 <14,82>
SPI_CLK R115 1 2 15_0402_5% SPI_CLK_R 6 3 SPI_IO2_R R116 1 2 15_0402_5% SPI_IO2
<14,82> SPI_CLK CLK WP# SPI_IO2 <14,24>
SPI_MOSI_IO0 R117 1 2 15_0402_5% SPI_MOSI_IO0_R 5 4
<14,82> SPI_MOSI_IO0 DI GND
W25Q128FVSIQ_SO8
NOTE:
1
2
R598 @
1K_0402_1% R9990 @ Pull-down on SPI_IO2 is placed on page-24
0_0402_5%
2
EMI
1
1
C9356 @
0.1U_0402_10V6-K
2 TABLE
SF100 PIN HEADER INTERFACE (TOP VIEW)
B 1 VCC D12.1 GND GND 2 B

3 CS# R322.2 R681.2 CLK 4
5 MISO R694.2 R674.2 MOSI 6
7 (KEY) N/A N/A (RESET) 8
U5 SPI ROM
vPRO model(16MB)
WINBOND W25Q128FVSIQ
MACRONIX MX25L12873FM2I-10G
MICRON N25Q128A13ESEDFF
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 SPI FLASH
5 4 3 2 1
5 4 3 2 1
VCC1R2A VCC2R5A VCC0R6B
VCC3B VCC3B VCC3B

M_A_DQ[0..63] <3,28>
M_A_A[0..9] <3,28>
1
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1 1 1 1 1 1 1 1 1 1 1 1 R118 R119 R120
-M_A_DQS[0..7] <3,28>
0_0402_5% 0_0402_5% 0_0402_5%
C76
C77
C78
C79
C80
C81
C82
C83
C84
C85
C86
C87
C88
C89
C90
M_A_DQS[0..7] <3,28> @ @ @
2
VCC1R2A 2 2 2 2 2 2 2 2 2 2 2 2
SA0_CHA_P SA1_CHA_P SA2_CHA_P
1
D R542 D
1K_0402_1% R121 R122 R123
0_0402_5% 0_0402_5% 0_0402_5%
M_A_VREF_CA_CPU R546
2
1 2 M_A_VREF_CA_CHA_DIMM
2
330U_D2_2VM_R9M
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1
1 2_0402_1% 1
+
C99
C91
C92
C93
C94
C95
C96
C97
C98
C688 R548
0.022U_0402_25V7-K 1K_0402_1% @
1
2 C885 2
SPD Address = 0H
1
0.1U_0402_16V7-K
2
R553
2
24.9_0402_1%
VCC1R2A
VCC2R5A VCC1R2A VCC1R2A VCC0R6B
2
VCC1R2A
2
VCC1R2A VCC1R2A JDIMM1B R555
240_0402_1%
VCC1R2A VCC1R2A M_A_A3 131 132 M_A_A2
1
M_A_A1 133 A3 A2 134
JDIMM1A 135 A1 EVENT_n/NF 136
M_A_DDRCLK0_1066M 137 VDD_9 VDD_10 138 M_A_DDRCLK1_1066M
<3> M_A_DDRCLK0_1066M CK0_t CK1_t/NF M_A_DDRCLK1_1066M <3>
-M_A_DDRCLK0_1066M 139 140 -M_A_DDRCLK1_1066M
<3> -M_A_DDRCLK0_1066M CK0_c CK1_c/NF -M_A_DDRCLK1_1066M <3>
1 2 141 142
M_A_DQ4 3 VSS_1 VSS_2 4 M_A_DQ1 M_A_PARITY 143 VDD_11 VDD_12 144 M_A_A0
DQ5 DQ4 <3,28> M_A_PARITY Parity A0
5 6
M_A_DQ0 7 VSS_3 VSS_4 8 M_A_DQ5
C 9 DQ1 DQ0 10 M_A_BA1 145 146 M_A_A10_AP C
VSS_5 VSS_6 <3,28> M_A_BA1 BA1 A10/AP M_A_A10_AP <3,28>
-M_A_DQS0 11 12 147 148
M_A_DQS0 13 DQS0_C DM0_n/DBI0_n 14 -M_A_CS0 149 VDD_13 VDD_14 150 M_A_BA0
DQS0_t VSS_7 <3> -M_A_CS0 CS0_n BA0 M_A_BA0 <3,28>
15 16 M_A_DQ6 M_A_A14_WE_N 151 152 M_A_A16_RAS_N
VSS_8 DQ6 <3,28> M_A_A14_WE_N WE_n/A14 RAS_n/A16 M_A_A16_RAS_N <3,28>
M_A_DQ7 17 18 153 154
19 DQ7 VSS_9 20 M_A_DQ2 M_A_ODT0 155 VDD_15 VDD_16 156 M_A_A15_CAS_N
VSS_10 DQ2 <3> M_A_ODT0 ODT0 CAS_n/A15 M_A_A15_CAS_N <3,28>
M_A_DQ3 21 22 -M_A_CS1 157 158 M_A_A13
DQ3 VSS_11 <3> -M_A_CS1 CS1_n A13 M_A_A13 <3,28>
23 24 M_A_DQ9 159 160
VSS_12 DQ12 VDD_17 VDD_18 M_A_VREF_CA_CHA_DIMM <28>
M_A_DQ13 25 26 M_A_ODT1 161 162
DQ13 VSS_13 <3> M_A_ODT1 ODT1 C0/CS2_n/NC
27 28 M_A_DQ8 163 164 M_A_VREF_CA_CHA_DIMM
M_A_DQ12 29 VSS_14 DQ8 30 165 VDD_19 VREFCA 166 SA2_CHA_P
31 DQ9 VSS_15 32 -M_A_DQS1 167 C1/CS3_n/NC SA2 168
33 VSS_16 DQS1_c 34 M_A_DQS1 M_A_DQ33 169 VSS_53 VSS_54 170 M_A_DQ36 VCC1R2A
35 DM1_n/DBl1_n DQS1_t 36 171 DQ37 DQ36 172
M_A_DQ15 37 VSS_17 VSS_18 38 M_A_DQ10 M_A_DQ37 173 VSS_55 VSS_56 174 M_A_DQ32
39 DQ15 DQ14 40 175 DQ33 DQ32 176
M_A_DQ14 41 VSS_19 VSS_20 42 M_A_DQ11 -M_A_DQS4 177 VSS_57 VSS_58 178
43 DQ10 DQ11 44 M_A_DQS4 179 DQS4_c DM4_n/DBl4_n 180
M_A_DQ21 45 VSS_21 VSS_22 46 M_A_DQ16 181 DQS4_t VSS_59 182 M_A_DQ35
DQ21 DQ20 M_A_DQ38 VSS_60 DQ39
2.2U_0402_6.3V6-M
0.1U_0402_10V7-K
47 48 183 184 1 2
M_A_DQ20 49 VSS_23 VSS_24 50 M_A_DQ17 185 DQ38 VSS_61 186 M_A_DQ34
DQ17 DQ16 VSS_62 DQ35
C692
C691
51 52 M_A_DQ39 187 188
-M_A_DQS2 53 VSS_25 VSS_26 54 189 DQ34 VSS_63 190 M_A_DQ40 @
M_A_DQS2 55 DQS2_c DM2_n/DBl2_n 56 M_A_DQ44 191 VSS_64 DQ45 192 2 1
57 DQS2_t VSS_27 58 M_A_DQ19 193 DQ44 VSS_65 194 M_A_DQ45
M_A_DQ22 59 VSS_28 DQ22 60 M_A_DQ41 195 VSS_66 DQ41 196
61 DQ23 VSS_29 62 M_A_DQ23 197 DQ40 VSS_67 198 -M_A_DQS5
M_A_DQ18 63 VSS_30 DQ18 64 199 VSS_68 DQS5_c 200 M_A_DQS5
65 DQ19 VSS_31 66 M_A_DQ24 201 DM5_n/DBl5_n DQS5_t 202
M_A_DQ29 67 VSS_32 DQ28 68 M_A_DQ43 203 VSS_69 VSS_70 204 M_A_DQ47
69 DQ29 VSS_33 70 M_A_DQ25 205 DQ46 DQ47 206
B 73 DQ25 VSS_35 74 -M_A_DQS3 209 DQ42 DQ43 210 B
75 VSS_36 DQS3_c 76 M_A_DQS3 M_A_DQ50 211 VSS_73 VSS_74 212 M_A_DQ48 VCC1R2A
81 DQ30 DQ31 82 217 DQ49 DQ48 218
M_A_CB5 87 VSS_41 VSS_42 88 M_A_CB4 223 DQS6_t VSS_79 224 M_A_DQ53
<3,28> M_A_CB5 CB5/NC CB4/NC M_A_CB4 <3,28> VSS_80 DQ54
89 90 M_A_DQ54 225 226
M_A_CB0 91 VSS_43 VSS_44 92 M_A_CB1 227 DQ55 VSS_81 228 M_A_DQ55
93 94 M_A_DQ51 229 230
-M_A_DQS8 95 VSS_45 VSS_46 96 231 DQ51 VSS_83 232 M_A_DQ56
<3,28> -M_A_DQS8 DQS8_c DBI8_n/DBI_n/NC VSS_84 DQ60
M_A_DQS8 97 98 M_A_DQ57 233 234
<3,28> M_A_DQS8 DQS8_t VSS_47 DQ61 VSS_85
99 100 M_A_CB7 235 236 M_A_DQ60
VSS_48 CB6/NC M_A_CB7 <3,28> VSS_86 DQ57
M_A_CB3 101 102 M_A_DQ61 237 238
<3,28> M_A_CB3 CB2/NC VSS_49 DQ56 VSS_87
103 104 M_A_CB6 239 240 -M_A_DQS7
VSS_50 CB7/NC M_A_CB6 <3,28> VSS_88 DQS7_c
M_A_CB2 105 106 241 242 M_A_DQS7
<3,28> M_A_CB2 CB3/NC VSS_51 DM7_n/DBl7_n DQS7_t
107 108 -DRAMRST 243 244
VSS_52 RESET_n -DRAMRST <17,28,29,30> VSS_89 VSS_90
M_A_CKE0 109 110 M_A_CKE1 M_A_DQ62 245 246 M_A_DQ59
<3> M_A_CKE0 CKE0 CKE1 M_A_CKE1 <3> DQ62 DQ63
111 112 247 248
M_A_BG1 113 VDD_1 VDD_2 114 -M_A_ACT M_A_DQ58 249 VSS_91 VSS_92 250 M_A_DQ63
<3,28> M_A_BG1 BG1 ACT_n -M_A_ACT <3,28> DQ58 DQ59
M_A_BG0 115 116 -M_A_ALERT 251 252
<3,28> M_A_BG0 BG0 ALERT_n -M_A_ALERT <3,28> VSS_93 VSS_94
117 118 SMB_CLK_3B 253 254 SMB_DATA_3B
VDD_3 VDD_4 <28,29,30,79,83> SMB_CLK_3B SCL SDA SMB_DATA_3B <28,29,30,79,83>
M_A_A12 119 120 M_A_A11 255 256 SA0_CHA_P
<3,28> M_A_A12 A12 A11 M_A_A11 <3,28> VCC3B VDDSPD SA0
M_A_A9 121 122 M_A_A7 257 258
A9 A7 VPP_1 Vtt SA1_CHA_P
0.1U_0402_10V7-K
2.2U_0402_6.3V6-M
123 124 259 260
VDD_5 VDD_6 R124 VPP_2 SA1
M_A_A8 125 126 M_A_A5 1 1
M_A_A6 127 A8 A5 128 M_A_A4 1 2 261 262
A6 A4 GND_1 GND_2
C100
C101
129 130
VDD_7 VDD_8
0.1U_0402_10V7-K
FOX_AS0A826-H4RB-7H
0_0402_5% 2 2
C689@
1 @
A FOX_AS0A826-H4RB-7H A
@ 2

Issued Date 2015/07/16 Deciphered Date 2016/01/16 DDR4 CH-A PRIMARY
Payton Common HTTPS://EN-MANUALS.CLAN.SU THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number
Custom
Rev
0.1

5 4 3 2 1
5 4 3 2 1
M_A_DQ[0..63] <3,27> VCC3B VCC3B VCC3B

M_A_A[0..9] <3,27>
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1
-M_A_DQS[0..7] <3,27> 1 1 1 1 1 1 1 1 1 1 1 1
R125 R126 R127
C102
C103
C104
C105
C106
C107
C108
C109
C110
C111
C112
C113
C114
C115
C116
M_A_DQS[0..7] <3,27> 0_0402_5% 0_0402_5% 0_0402_5%
@ @
2 2 2 2 2 2 2 2 2 2 2 2
2
SA0_CHA_S SA1_CHA_S SA2_CHA_S
1
D D
R128 R129 R130
0_0402_5% 0_0402_5% 0_0402_5%
@
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
2
C117
C118
C119
C123
C120
C124
C121
C125
SPD ADDRESS = 1H
VCC1R2A
VCC1R2A
1
VCC1R2A VCC1R2A JDIMM2B R556
240_0402_1%
VCC1R2A VCC1R2A M_A_A3 131 132 M_A_A2
2
M_A_A1 133 A3 A2 134
JDIMM2A 135 A1 EVENT_n 136
M_A_DDRCLK2_1066M 137 VDD_9 VDD_10 138 M_A_DDRCLK3_1066M
<3> M_A_DDRCLK2_1066M CK0_t CK1_t M_A_DDRCLK3_1066M <3>
-M_A_DDRCLK2_1066M 139 140 -M_A_DDRCLK3_1066M
<3> -M_A_DDRCLK2_1066M CK0_c CK1_c -M_A_DDRCLK3_1066M <3>
1 2 141 142
M_A_DQ4 3 VSS_1 VSS_2 4 M_A_DQ1 M_A_PARITY 143 VDD_11 VDD_12 144 M_A_A0
DQ5 DQ4 <3,27> M_A_PARITY Parity A0
5 6
M_A_DQ0 7 VSS_3 VSS_4 8 M_A_DQ5
9 DQ1 DQ0 10 M_A_BA1 145 146 M_A_A10_AP
VSS_5 VSS_6 <3,27> M_A_BA1 BA1 A10/AP M_A_A10_AP <3,27>
C -M_A_DQS0 11 12 147 148 C
M_A_DQS0 13 DQS0_C DM0_n/DBIO_n 14 -M_A_CS2 149 VDD_13 VDD_14 150 M_A_BA0
DQS0_t VSS_7 <3> -M_A_CS2 CS0_n BA0 M_A_BA0 <3,27>
15 16 M_A_DQ6 M_A_A14_WE_N 151 152 M_A_A16_RAS_N
VSS_8 DQ6 <3,27> M_A_A14_WE_N WE_n/A14 RAS_n/A16 M_A_A16_RAS_N <3,27>
M_A_DQ7 17 18 153 154
19 DQ7 VSS_9 20 M_A_DQ2 M_A_ODT2 155 VDD_15 VDD_16 156 M_A_A15_CAS_N
VSS_10 DQ2 <3> M_A_ODT2 ODT0 CAS_n/A15 M_A_A15_CAS_N <3,27>
M_A_DQ3 21 22 -M_A_CS3 157 158 M_A_A13
DQ3 VSS_11 <3> -M_A_CS3 CS1_n A13 M_A_A13 <3,27>
23 24 M_A_DQ9 159 160
M_A_DQ13 25 VSS_12 DQ12 26 M_A_ODT3 161 VDD_17 VDD_18 162
DQ13 VSS_13 <3> M_A_ODT3 ODT1 C0/CS2_n/NC M_A_VREF_CA_CHA_DIMM <27>
27 28 M_A_DQ8 163 164 M_A_VREF_CA_CHA_DIMM
M_A_DQ12 29 VSS_14 DQ8 30 165 VDD_19 VREFCA 166 SA2_CHA_S
31 DQ9 VSS_15 32 -M_A_DQS1 167 C1/CS3_n/NC RFU 168
VSS_16 DQS1_c M_A_DQS1 M_A_DQ33 VSS_53 VSS_54 M_A_DQ36
2.2U_0402_6.3V6-M
0.1U_0402_10V7-K
33 34 169 170 VCC1R2A 1 2
VSS_17 VSS_18 VSS_55 VSS_56
C694
C693
M_A_DQ15 37 38 M_A_DQ10 M_A_DQ37 173 174 M_A_DQ32
39 DQ15 DQ14 40 175 DQ33 DQ32 176 @
M_A_DQ14 41 VSS_19 VSS_20 42 M_A_DQ11 -M_A_DQS4 177 VSS_57 VSS_58 178 2 1
M_A_DQ21 45 VSS_21 VSS_22 46 M_A_DQ16 181 DQS4_t VSS_59 182 M_A_DQ35
47 DQ21 DQ20 48 M_A_DQ38 183 VSS_60 DQ39 184
M_A_DQ20 49 VSS_23 VSS_24 50 M_A_DQ17 185 DQ38 VSS_61 186 M_A_DQ34
51 DQ17 DQ16 52 M_A_DQ39 187 VSS_62 DQ35 188
M_A_DQS2 55 DQS2_c DM2_n/DBl2_n 56 M_A_DQ44 191 VSS_64 DQ45 192
57 DQS2_t VSS_27 58 M_A_DQ19 193 DQ44 VSS_65 194 M_A_DQ45
M_A_DQ22 59 VSS_28 DQ22 60 M_A_DQ41 195 VSS_66 DQ41 196
61 DQ23 VSS_29 62 M_A_DQ23 197 DQ40 VSS_67 198 -M_A_DQS5
M_A_DQ18 63 VSS_30 DQ18 64 199 VSS_68 DQS5_c 200 M_A_DQS5
65 DQ19 VSS_31 66 M_A_DQ24 201 DM5_n/DBl5_n DQS5_t 202
69 DQ29 VSS_33 70 M_A_DQ25 205 DQ46 DQ47 206
73 DQ25 VSS_35 74 -M_A_DQS3 209 DQ42 DQ43 210
B 75 VSS_36 DQS3_c 76 M_A_DQS3 M_A_DQ50 211 VSS_73 VSS_74 212 M_A_DQ48 VCC1R2A B
81 DQ30 DQ31 82 217 DQ49 DQ48 218
M_A_CB5 87 VSS_41 VSS_42 88 M_A_CB4 223 DQS6_t VSS_79 224 M_A_DQ53
89 90 M_A_DQ54 225 226
M_A_CB0 91 VSS_43 VSS_44 92 M_A_CB1 227 DQ55 VSS_81 228 M_A_DQ55
93 94 M_A_DQ51 229 230
<3,27> -M_A_DQS8 DQS8_c DBI8_n VSS_84 DQ60
M_A_DQS8 97 98 M_A_DQ57 233 234
<3,27> M_A_DQS8 DQS8_t VSS_47 DQ61 VSS_85
99 100 M_A_CB7 235 236 M_A_DQ60
VSS_48 CB6/NC M_A_CB7 <3,27> VSS_86 DQ57
M_A_CB3 101 102 M_A_DQ61 237 238
<3,27> M_A_CB3 CB2/NC VSS_49 DQ56 VSS_87
103 104 M_A_CB6 239 240 -M_A_DQS7
VSS_50 CB7/NC M_A_CB6 <3,27> VSS_88 DQS7_c
M_A_CB2 105 106 241 242 M_A_DQS7
<3,27> M_A_CB2 CB3/NC VSS_51 DM7_n/DBl7_n DQS7_t
107 108 -DRAMRST 243 244
VSS_52 RESET_n -DRAMRST <17,27,29,30> VSS_89 VSS_90
M_A_CKE2 109 110 M_A_CKE3 M_A_DQ62 245 246 M_A_DQ59
<3> M_A_CKE2 CKE0 CKE1 M_A_CKE3 <3> DQ62 DQ63
111 112 247 248
M_A_BG1 113 VDD_1 VDD_2 114 -M_A_ACT M_A_DQ58 249 VSS_91 VSS_92 250 M_A_DQ63
<3,27> M_A_BG1 BG1 ACT_n -M_A_ACT <3,27> DQ58 DQ59
M_A_BG0 115 116 -M_A_ALERT 251 252
<3,27> M_A_BG0 BG0 ALERT_n -M_A_ALERT <3,27> VSS_93 VSS_94
117 118 SMB_CLK_3B 253 254 SMB_DATA_3B
VDD_3 VDD_4 <27,29,30,79,83> SMB_CLK_3B SCL SDA SMB_DATA_3B <27,29,30,79,83>
M_A_A12 119 120 M_A_A11 255 256 SA0_CHA_S
<3,27> M_A_A12 A12 A11 M_A_A11 <3,27> VCC3B VDDSPD SA0
M_A_A9 121 122 M_A_A7 257 258
A9 A7 VPP_1 Vtt SA1_CHA_S
0.1U_0402_10V7-K
2.2U_0402_6.3V6-M
123 124 259 260
VDD_5 VDD_6 R131 VPP_2 SA1
M_A_A8 125 126 M_A_A5 1 1
M_A_A6 127 A8 A5 128 M_A_A4 1 2 261 262
A6 A4 GND_1 GND_2
C126
C127
129 130
VDD_7 VDD_8 FOX_AS0A826-H4SB-7H
0_0402_5% 2 2
@
FOX_AS0A826-H4SB-7H
A A
@

Issued Date 2015/07/16 Deciphered Date 2016/01/16 DDR4 CH-A SECONDARY
Payton Common THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Custom

Rev
0.1
5 4 3 2 1
5 4 3 2 1
M_B_DQ[0..63] <4,30> VCC3B VCC3B VCC3B

M_B_A[0..9] <4,30>
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1
-M_B_DQS[0..7] <4,30> 1 1 1 1 1 1 1 1 1 1 1 1
R132 R136 R134
C128
C129
C130
C131
C132
C133
C134
C135
C136
C137
C138
C139
C140
C141
C142
M_B_DQS[0..7] <4,30> 0_0402_5% 0_0402_5% 0_0402_5%
2 2 2 2 2 2 2 2 2 2 2 2 @ @
2
VCC1R2A
SA0_CHB_P SA1_CHB_P SA2_CHB_P
1
D D
R549 R135 R133 R137
1K_0402_1% 0_0402_5% 0_0402_5% 0_0402_5%
M_B_VREF_DQ_CPU R550
<4>
330U_D2_2VM_R9M
M_B_VREF_CA_CHB_DIMM
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1 2 1 @
2
2_0402_1% +
C151
1 1
C143
C144
C145
C146
C147
C148
C149
C150
C687 @
1
0.022U_0402_25V7-K R551 C686 2
2 1K_0402_1% 0.1U_0402_16V7-K
SPD Address = 2H
1
2
R552
24.9_0402_1% VCC1R2A
2
VCC1R2A
1
VCC1R2A VCC1R2A
JDIMM3B R557
240_0402_1%
VCC1R2A VCC1R2A
M_B_A3 131 132 M_B_A2
2
JDIMM3A M_B_A1 133 A3 A2 134
135 A1 EVENT_n 136
M_B_DDRCLK0_1066M 137 VDD_9 VDD_10 138 M_B_DDRCLK1_1066M
<4> M_B_DDRCLK0_1066M CK0_t CK1_t M_B_DDRCLK1_1066M <4>
1 2 -M_B_DDRCLK0_1066M 139 140 -M_B_DDRCLK1_1066M
VSS_1 VSS_2 <4> -M_B_DDRCLK0_1066M CK0_c CK1_c -M_B_DDRCLK1_1066M <4>
M_B_DQ2 3 4 M_B_DQ4 141 142
5 DQ5 DQ4 6 M_B_PARITY 143 VDD_11 VDD_12 144 M_B_A0
VSS_3 VSS_4 <4,30> M_B_PARITY Parity A0
M_B_DQ5 7 8 M_B_DQ0
9 DQ1 DQ0 10
-M_B_DQS0 11 VSS_5 VSS_6 12 M_B_BA1 145 146 M_B_A10_AP
DQS0_C DM0_n/DBIO_n <4,30> M_B_BA1 BA1 A10/AP M_B_A10_AP <4,30>
C M_B_DQS0 13 14 147 148 C
15 DQS0_t VSS_7 16 M_B_DQ1 -M_B_CS0 149 VDD_13 VDD_14 150 M_B_BA0
VSS_8 DQ6 <4> -M_B_CS0 CS0_n BA0 M_B_BA0 <4,30>
M_B_DQ6 17 18 M_B_A14_WE_N 151 152 M_B_A16_RAS_N
DQ7 VSS_9 <4,30> M_B_A14_WE_N WE_n/A14 RAS_n/A16 M_B_A16_RAS_N <4,30>
19 20 M_B_DQ7 153 154
M_B_DQ3 21 VSS_10 DQ2 22 M_B_ODT0 155 VDD_15 VDD_16 156 M_B_A15_CAS_N
DQ3 VSS_11 <4> M_B_ODT0 ODT0 CAS_n/A15 M_B_A15_CAS_N <4,30>
23 24 M_B_DQ8 -M_B_CS1 157 158 M_B_A13
VSS_12 DQ12 <4> -M_B_CS1 CS1_n A13 M_B_A13 <4,30>
M_B_DQ10 25 26 159 160
27 DQ13 VSS_13 28 M_B_DQ9 M_B_ODT1 161 VDD_17 VDD_18 162
VSS_14 DQ8 <4> M_B_ODT1 ODT1 C0/CS2_n/NC M_B_VREF_CA_CHB_DIMM <30>
M_B_DQ14 29 30 163 164 M_B_VREF_CA_CHB_DIMM
31 DQ9 VSS_15 32 -M_B_DQS1 165 VDD_19 VREFCA 166 SA2_CHB_P
33 VSS_16 DQS1_c 34 M_B_DQS1 167 C1/CS3_n/NC RFU 168
35 DM1_n/DBl1_n DQS1_t 36 M_B_DQ38 169 VSS_53 VSS_54 170 M_B_DQ34 VCC1R2A
M_B_DQ12 37 VSS_17 VSS_18 38 M_B_DQ11 171 DQ37 DQ36 172
39 DQ15 DQ14 40 M_B_DQ35 173 VSS_55 VSS_56 174 M_B_DQ39
43 DQ10 DQ11 44 -M_B_DQS4 177 VSS_57 VSS_58 178
M_B_DQ22 45 VSS_21 VSS_22 46 M_B_DQ17 M_B_DQS4 179 DQS4_c DM4_n/DBl4_n 180
47 DQ21 DQ20 48 181 DQS4_t VSS_59 182 M_B_DQ36
M_B_DQ18 VSS_23 VSS_24 M_B_DQ16 M_B_DQ33 VSS_60 DQ39
2.2U_0402_6.3V6-M
0.1U_0402_10V7-K
49 50 183 184 1 1
51 DQ17 DQ16 52 185 DQ38 VSS_61 186 M_B_DQ37
VSS_25 VSS_26 VSS_62 DQ35
C696
C695
-M_B_DQS2 53 54 M_B_DQ32 187 188
M_B_DQS2 55 DQS2_c DM2_n/DBl2_n 56 189 DQ34 VSS_63 190 M_B_DQ44 @
57 DQS2_t VSS_27 58 M_B_DQ23 M_B_DQ40 191 VSS_64 DQ45 192 2 2
M_B_DQ20 59 VSS_28 DQ22 60 193 DQ44 VSS_65 194 M_B_DQ45
61 DQ23 VSS_29 62 M_B_DQ21 M_B_DQ41 195 VSS_66 DQ41 196
M_B_DQ19 63 VSS_30 DQ18 64 197 DQ40 VSS_67 198 -M_B_DQS5
65 DQ19 VSS_31 66 M_B_DQ28 199 VSS_68 DQS5_c 200 M_B_DQS5
M_B_DQ27 67 VSS_32 DQ28 68 201 DM5_n/DBl5_n DQS5_t 202
69 DQ29 VSS_33 70 M_B_DQ25 M_B_DQ42 203 VSS_69 VSS_70 204 M_B_DQ47
M_B_DQ31 71 VSS_34 DQ24 72 205 DQ46 DQ47 206
73 DQ25 VSS_35 74 -M_B_DQS3 M_B_DQ46 207 VSS_71 VSS_72 208 M_B_DQ43
75 VSS_36 DQS3_c 76 M_B_DQS3 209 DQ42 DQ43 210
B 77 DM3_n/DBl3_n DQS3_t 78 M_B_DQ52 211 VSS_73 VSS_74 212 M_B_DQ54 VCC1R2A B
81 DQ30 DQ31 82 M_B_DQ48 215 VSS_75 VSS_76 216 M_B_DQ55
M_B_CB2 87 VSS_41 VSS_42 88 M_B_CB4 M_B_DQS6 221 DQS6_c DM6_n/DBl6_n 222
<4,30> M_B_CB2 CB5/NC CB4/NC M_B_CB4 <4,30> DQS6_t VSS_79
89 90 223 224 M_B_DQ53
M_B_CB6 91 VSS_43 VSS_44 92 M_B_CB3 M_B_DQ50 225 VSS_80 DQ54 226
<4,30> M_B_CB6 CB1/NC CB0/NC M_B_CB3 <4,30> DQ55 VSS_81
93 94 227 228 M_B_DQ49
-M_B_DQS8 95 VSS_45 VSS_46 96 M_B_DQ51 229 VSS_82 DQ50 230
<4,30> -M_B_DQS8 DQS8_c DBI8_n DQ51 VSS_83
M_B_DQS8 97 98 231 232 M_B_DQ59
<4,30> M_B_DQS8 DQS8_t VSS_47 VSS_84 DQ60
99 100 M_B_CB5 M_B_DQ57 233 234
VSS_48 CB6/NC M_B_CB5 <4,30> DQ61 VSS_85
M_B_CB7 101 102 235 236 M_B_DQ62
<4,30> M_B_CB7 CB2/NC VSS_49 VSS_86 DQ57
103 104 M_B_CB0 M_B_DQ61 237 238
M_B_CB1 105 106 239 240 -M_B_DQS7
<4,30> M_B_CB1 CB3/NC VSS_51 VSS_88 DQS7_c
107 108 -DRAMRST 241 242 M_B_DQS7
VSS_52 RESET_n -DRAMRST <17,27,28,30> DM7_n/DBl7_n DQS7_t
M_B_CKE0 109 110 M_B_CKE1 243 244
<4> M_B_CKE0 CKE0 CKE1 M_B_CKE1 <4> VSS_89 VSS_90
111 112 M_B_DQ56 245 246 M_B_DQ63
M_B_BG1 113 VDD_1 VDD_2 114 -M_B_ACT 247 DQ62 DQ63 248
<4,30> M_B_BG1 BG1 ACT_n -M_B_ACT <4,30> VSS_91 VSS_92
M_B_BG0 115 116 -M_B_ALERT M_B_DQ60 249 250 M_B_DQ58
<4,30> M_B_BG0 BG0 ALERT_n -M_B_ALERT <4,30> DQ58 DQ59
117 118 251 252
M_B_A12 119 VDD_3 VDD_4 120 M_B_A11 SMB_CLK_3B 253 VSS_93 VSS_94 254 SMB_DATA_3B
<4,30> M_B_A12 A12 A11 M_B_A11 <4,30> <27,28,30,79,83> SMB_CLK_3B SCL SDA SMB_DATA_3B <27,28,30,79,83>
M_B_A9 121 122 M_B_A7 255 256 SA0_CHB_P
123 A9 A7 124 VCC3B 257 VDDSPD SA0 258
M_B_A8 VDD_5 VDD_6 M_B_A5 VPP_1 Vtt SA1_CHB_P
0.1U_0402_10V7-K
2.2U_0402_6.3V6-M
125 126 259 260
A8 A5 R138 VPP_2 SA1
M_B_A6 127 128 M_B_A4 1 1
129 A6 A4 130 1 2 261 262
VDD_7 VDD_8 GND_1 GND_2
C152
C153
0.1U_0402_10V7-K
@
1 FOX_AS0A827-H8RB-7H
0_0402_5% 2 2
C690
@
FOX_AS0A827-H8RB-7H
@ 2
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 DDR4 CH-B PRIMARY
Custom
Rev
0.1

5 4 3 2 1
5 4 3 2 1
M_B_DQ[0..63] <4,29> VCC3B VCC3B VCC3B

M_B_A[0..9] <4,29>
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1
-M_B_DQS[0..7] <4,29> 1 1 1 1 1 1 1 1 1 1 1 1
R139 R140 R141
C154
C155
C156
C157
C158
C159
C160
C161
C162
C163
C164
C165
C166
C167
C168
M_B_DQS[0..7] <4,29> 0_0402_5% 0_0402_5% 0_0402_5%
2 2 2 2 2 2 2 2 2 2 2 2 @
2
SA0_CHB_S SA1_CHB_S SA2_CHB_S
1
D D
R142 R143 R144
0_0402_5% 0_0402_5% 0_0402_5%
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
@ @
2
C169
C170
C171
C172
C173
C174
C175
C176
SPD ADDRESS = 3H
VCC1R2A
VCC1R2A
1
JDIMM4B R558
VCC1R2A VCC1R2A 240_0402_1%
M_B_A3 131 132 M_B_A2
2
VCC1R2A VCC1R2A M_B_A1 133 A3 A2 134
135 A1 EVENT_n/NF 136
JDIMM4A M_B_DDRCLK2_1066M 137 VDD_9 VDD_10 138 M_B_DDRCLK3_1066M
<4> M_B_DDRCLK2_1066M CK0_t CK1_t/NF M_B_DDRCLK3_1066M <4>
-M_B_DDRCLK2_1066M 139 140 -M_B_DDRCLK3_1066M
<4> -M_B_DDRCLK2_1066M CK0_c CK1_c/NF -M_B_DDRCLK3_1066M <4>
141 142
1 2 M_B_PARITY 143 VDD_11 VDD_12 144 M_B_A0
VSS_1 VSS_2 <4,29> M_B_PARITY Parity A0
M_B_DQ2 3 4 M_B_DQ4
5 DQ5 DQ4 6
M_B_DQ5 7 VSS_3 VSS_4 8 M_B_DQ0 M_B_BA1 145 146 M_B_A10_AP
C DQ1 DQ0 <4,29> M_B_BA1 BA1 A10/AP M_B_A10_AP <4,29> C
9 10 147 148
-M_B_DQS0 11 VSS_5 VSS_6 12 -M_B_CS2 149 VDD_13 VDD_14 150 M_B_BA0
DQS0_C DM0_n/DBl0_n <4> -M_B_CS2 CS0_n BA0 M_B_BA0 <4,29>
M_B_DQS0 13 14 M_B_A14_WE_N 151 152 M_B_A16_RAS_N
DQS0_t VSS_7 <4,29> M_B_A14_WE_N A14/WE_n A16/RAS_n M_B_A16_RAS_N <4,29>
15 16 M_B_DQ1 153 154
M_B_DQ6 17 VSS_8 DQ6 18 M_B_ODT2 155 VDD_15 VDD_16 156 M_B_A15_CAS_N
DQ7 VSS_9 <4> M_B_ODT2 ODT0 A15/CAS_n M_B_A15_CAS_N <4,29>
19 20 M_B_DQ7 -M_B_CS3 157 158 M_B_A13
VSS_10 DQ2 <4> -M_B_CS3 CS1_n A13 M_B_A13 <4,29>
M_B_DQ3 21 22 159 160
23 DQ3 VSS_11 24 M_B_DQ8 M_B_ODT3 161 VDD_17 VDD_18 162
VSS_12 DQ12 <4> M_B_ODT3 ODT1 C0/CS2_n/NC M_B_VREF_CA_CHB_DIMM <29>
M_B_DQ10 25 26 163 164 M_B_VREF_CA_CHB_DIMM
27 DQ13 VSS_13 28 M_B_DQ9 165 VDD_19 VREFCA 166 SA2_CHB_S
M_B_DQ14 29 VSS_14 DQ8 30 167 C1/CS3_n/NC SA2 168
DQ9 VSS_15 -M_B_DQS1 M_B_DQ38 VSS_53 VSS_54 M_B_DQ34
2.2U_0402_6.3V6-M
0.1U_0402_10V7-K
31 32 169 170 VCC1R2A 1 2
DM1_n/DBl1_n DQS1_t VSS_55 VSS_56
C698
C697
35 36 M_B_DQ35 173 174 M_B_DQ39
M_B_DQ12 37 VSS_17 VSS_18 38 M_B_DQ11 175 DQ33 DQ32 176 @
39 DQ15 DQ14 40 -M_B_DQS4 177 VSS_57 VSS_58 178 2 1
M_B_DQ22 45 VSS_21 VSS_22 46 M_B_DQ17 M_B_DQ33 183 VSS_60 DQ39 184
47 DQ21 DQ20 48 185 DQ38 VSS_61 186 M_B_DQ37
M_B_DQ18 49 VSS_23 VSS_24 50 M_B_DQ16 M_B_DQ32 187 VSS_62 DQ35 188
51 DQ17 DQ16 52 189 DQ34 VSS_63 190 M_B_DQ44
M_B_DQS2 55 DQS2_c DM2_n/DBl2_n 56 193 DQ44 VSS_65 194 M_B_DQ45
57 DQS2_t VSS_27 58 M_B_DQ23 M_B_DQ41 195 VSS_66 DQ41 196
M_B_DQ20 59 VSS_28 DQ22 60 197 DQ40 VSS_67 198 -M_B_DQS5
61 DQ23 VSS_29 62 M_B_DQ21 199 VSS_68 DQS5_c 200 M_B_DQS5
M_B_DQ19 63 VSS_30 DQ18 64 201 DM5_n/DBl5_n DQS5_t 202
M_B_DQ27 67 VSS_32 DQ28 68 205 DQ46 DQ47 206
M_B_DQ31 71 VSS_34 DQ24 72 209 DQ42 DQ43 210
B 73 DQ25 VSS_35 74 -M_B_DQS3 M_B_DQ52 211 VSS_73 VSS_74 212 M_B_DQ54 VCC1R2A B
77 DM3_n/DBl3_n DQS3_t 78 M_B_DQ48 215 VSS_75 VSS_76 216 M_B_DQ55
<4,29> M_B_CB2 CB5/NC CB4/NC M_B_CB4 <4,29> DQS5 VSS_81
89 90 227 228 M_B_DQ49
<4,29> M_B_CB6 CB1/NC CB0/NC M_B_CB3 <4,29> DQ51 VSS_83
93 94 231 232 M_B_DQ59
<4,29> -M_B_DQS8 DQS8_c DM8_n/DBl8_n/NC DQ61 VSS_85
M_B_DQS8 97 98 235 236 M_B_DQ62
<4,29> M_B_DQS8 DQS8_t VSS_47 VSS_86 DQ57
99 100 M_B_CB5 M_B_DQ61 237 238
M_B_CB7 101 102 239 240 -M_B_DQS7
<4,29> M_B_CB7 CB2/NC VSS_49 VSS_88 DQS7_c
103 104 M_B_CB0 241 242 M_B_DQS7
VSS_50 CB7/NC M_B_CB0 <4,29> DM7_n/DBl7_n DQS7_t
M_B_CB1 105 106 243 244
<4,29> M_B_CB1 CB3/NC VSS_51 VSS_89 VSS_90
107 108 -DRAMRST M_B_DQ56 245 246 M_B_DQ63
VSS_52 RESET_n -DRAMRST <17,27,28,29> DQ62 DQ63
M_B_CKE2 109 110 M_B_CKE3 247 248
<4> M_B_CKE2 CKE0 CKE1 M_B_CKE3 <4> VSS_91 VSS_92
111 112 M_B_DQ60 249 250 M_B_DQ58
M_B_BG1 113 VDD_1 VDD_2 114 -M_B_ACT 251 DQ58 DQ59 252
<4,29> M_B_BG1 BG1 ACT_n -M_B_ACT <4,29> VSS_93 VSS_94
M_B_BG0 115 116 -M_B_ALERT SMB_CLK_3B 253 254 SMB_DATA_3B
<4,29> M_B_BG0 BG0 ALERT_n -M_B_ALERT <4,29> <27,28,29,79,83> SMB_CLK_3B SCL SDA SMB_DATA_3B <27,28,29,79,83>
117 118 255 256 SA0_CHB_S
M_B_A12 119 VDD_3 VDD_4 120 M_B_A11 VCC3B 257 VDDSPD SA0 258
<4,29> M_B_A12 A12 A11 M_B_A11 <4,29> VPP_1 VTT
M_B_A9 M_B_A7 SA1_CHB_S
0.1U_0402_10V7-K
2.2U_0402_6.3V6-M
121 122 259 260
A9 A7 R145 VPP_2 SA1
123 124 1 1
M_B_A8 125 VDD_5 VDD_6 126 M_B_A5 1 2 261 262
A8 A5 GND_1 GND_2
C178
C179
M_B_A6 127 128 M_B_A4
129 A6 A4 130 FOX_AS0A826-H4RB-7H
VDD_7 VDD_8 0_0402_5% 2 2
@
A FOX_AS0A826-H4RB-7H A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 DDR4 CH-B SECONDARY
Payton Common THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Custom

Rev
0.1
5 4 3 2 1
5 4 3 2 1
Walter Unique <5>
<5>
PEG_RXP[15:0]
PEG_RXN[15:0]
<5> PEG_TXP[15:0]
<5> PEG_TXN[15:0]
VCC3VIDEO
<77,111,115> 1R35VIDEO_ON 3300mA
1
R9142 UV1A VCC1R05VIDEO
10K_0402_5%
1
D 1/18 PCI_EXPRESS D
R9998 GM107/GM108 NEAR BALLS UNDER GPU
2
10K_0402_5% GK107/GK208
GF117
AJ11 NC
2 2
PEX_WAKE_N AG19
PEX_IOVDD_1 1 1 1 1 1 1 1
2N7002W-T/R7_SOT323-3 AJ12 AG21 C9034 C8389 C8390 C8391 C9033 C8393 C8394
G
<34,77> -GPU_RST PEX_RST_N PEX_IOVDD_2
QV15 AG22
1 3 AK12 PEX_IOVDD_3 AG24 1UF_0402_6.3V6-K 1UF_0402_6.3V6-K 4.7U_0603_6.3VAK 10U_0603_6.3V6M 10U_0603_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
<20> -CLKREQ_PCIE5_PEG PEX_CLKREQ_N PEX_IOVDD_4 2 2 2 2 2 2 2
AH21
D
S AL13 PEX_IOVDD_5 AH25

<20> PCIE5_CLK_100M_PEG PEX_REFCLK PEX_IOVDD_6
AK13
<20> -PCIE5_CLK_100M_PEG PEX_REFCLK_N
PEG_RXP0 C8395 1 2 0.22U_0201_6.3V6-K PEG_RXP0_C AK14
PEG_RXN0 C8396 1 2 0.22U_0201_6.3V6-K PEG_RXN0_C AJ14 PEX_TX0
PEX_TX0_N
PEG_TXP0 AN12 NEAR BALLS UNDER GPU
PEG_TXN0 AM12 PEX_RX0 AG13
PEX_RX0_N PEX_IOVDDQ_01 AG15
PEG_RXP1 C8397 1 2 0.22U_0201_6.3V6-K PEG_RXP1_C AH14 PEX_IOVDDQ_02 AG16
PEG_RXN1 C8398 1 2 0.22U_0201_6.3V6-K PEG_RXN1_C AG14 PEX_TX1 PEX_IOVDDQ_03 AG18
PEX_TX1_N PEX_IOVDDQ_04 1 1 1 1 1 1 1
AG25 C8399 C8400 C8401 C8402 C8403 C8404 C8405
PEG_TXP1 AN14 PEX_IOVDDQ_05 AH15
PEG_TXN1 AM14 PEX_RX1 PEX_IOVDDQ_06 AH18 1UF_0402_6.3V6-K 1UF_0402_6.3V6-K 4.7U_0603_6.3VAK 10U_0603_6.3V6M 10U_0603_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
PEX_RX1_N PEX_IOVDDQ_07 AH26 2 2 2 2 2 2 2
PEG_RXP2 C8406 1 2 0.22U_0201_6.3V6-K PEG_RXP2_C PEX_IOVDDQ_08 AH27
AK15
PEG_RXN2 C8407 1 2 0.22U_0201_6.3V6-K PEG_RXN2_C AJ15 PEX_TX2 PEX_IOVDDQ_09 AJ27
PEX_TX2_N PEX_IOVDDQ_10 AK27
PEG_TXP2 AP14 PEX_IOVDDQ_11 AL27
PEG_TXN2 AP15 PEX_RX2 PEX_IOVDDQ_12 AM28
PEX_RX2_N PEX_IOVDDQ_13 AN28
PEG_RXP3 C8408 1 2 0.22U_0201_6.3V6-K PEG_RXP3_C AL16 PEX_IOVDDQ_14
PEG_RXN3 C8409 1 2 0.22U_0201_6.3V6-K PEG_RXN3_C AK16 PEX_TX3
PEX_TX3_N
PEG_TXP3 AN15
PEG_TXN3 AM15 PEX_RX3
PEX_RX3_N
C PEG_RXP4 C9010 1 2 0.22U_0201_6.3V6-K PEG_RXP4_C AK17 C
PEX_TX4_N
PEG_TXP4 AN17
210mA
PEG_TXN4 AM17 PEX_RX4 VCC3VIDEO
PEX_RX4_N
PEG_RXP5 C9012 1 2 0.22U_0201_6.3V6-K PEG_RXP5_C AH17
PEG_RXN5 C9014 1 2 0.22U_0201_6.3V6-K PEG_RXN5_C AG17 PEX_TX5
PEX_TX5_N AH12
PEG_TXP5 PEX_PLL_HVDD
0.1U_0402_10V7-K
AP17
PEG_TXN5 AP18 PEX_RX5 AG12
PEX_RX5_N PEX_SVDD_3V3 1 1 1
C9298
PEG_RXP6 C9015 1 2 0.22U_0201_6.3V6-K PEG_RXP6_C AK18 C8411 C8412
PEG_RXN6 C9009 1 2 0.22U_0201_6.3V6-K PEG_RXN6_C AJ18 PEX_TX6 4.7U_0402_6.3V6M
PEX_TX6_N 4.7U_0402_6.3V6M
2 2 2
PEG_TXP6 AN18
PEX_RX6_N
PEG_RXP7 C9016 1 2 0.22U_0201_6.3V6-K PEG_RXP7_C AL19 VCCGFXCORE_D
PEX_TX7_N
2
PEG_TXP7 AN20
PEG_TXN7 AM20 PEX_RX7 R9143@
PEX_RX7_N
0_0402_5%
1
PEX_TX8_N L4
PEG_TXP8 VDD_SENSE GFXCORE_VDD_SENSE_D <110>
AP20
PEG_TXN8 AP21 PEX_RX8
PEX_RX8_N L5
PEG_RXP9 PEG_RXP9_C GND_SENSE GFXCORE_GND_SENSE_D <110>
C9020 1 2 0.22U_0201_6.3V6-K AH20
PEX_TX9
2
PEG_RXN9 C9022 1 2 0.22U_0201_6.3V6-K PEG_RXN9_C AG20
PEX LANES 4 TO 15 NC FOR GM108
PEX_TX9_N
PEG_TXP9 AN21 0_0402_5%
PEG_TXN9 AM21 PEX_RX9 R9144@
PEX_RX9_N
1
B PEX_TX10_N P8 B
PEG_TXP10 AN23 3V3AUX_NC
PEX_RX10_N
PEG_RXP11 C9024 1 2 0.22U_0201_6.3V6-K PEG_RXP11_C AL22
PEX_TX11_N 150mA
PEG_TXP11 VCC1R05VIDEO_PLL
AP23
PEX_RX11_N AJ26 R9642 @1 2 200_0402_1%
PEG_RXP12 C9026 1 2 0.22U_0201_6.3V6-K PEG_RXP12_C AK23 PEX_TSTCLK_OUT AK26
PEX_TX12 PEX_TSTCLK_OUT_N
1
PEG_RXN12 C9029 1 2 0.22U_0201_6.3V6-K PEG_RXN12_C AJ23
PEX LANES 8 TO 15 NC FOR GK208/GF117
PEX_TX12_N
PEG_TXP12 AN24 0_0402_5% VRAM
PEG_TXN12 AM24 PEX_RX12 R9148 ZZZ ZZZ
PEX_RX12_N
2
PEG_RXP13 C9028 1 2 0.22U_0201_6.3V6-K PEG_RXP13_C AH23 VCC1R05VIDEO_PEX_PLLVDD
PEG_RXN13 C9030 1 2 0.22U_0201_6.3V6-K PEG_RXN13_C AG23 PEX_TX13 AG26
PEX_TX13_N PEX_PLLVDD
PEG_TXP13 AN26 2 1 1
PEG_TXN13 AM26 PEX_RX13 X7606101006 X7606101008
PEX_RX13_N C8413 C8414 C8415 H1G@ H2G@
PEG_RXP14 C9031 1 2 0.22U_0201_6.3V6-K PEG_RXP14_C AK24 0.1U_0402_25V7K 1UF_0402_6.3V6-K 4.7U_0402_6.3V6M
PEG_RXN14 C9025 1 2 0.22U_0201_6.3V6-K PEG_RXN14_C AJ24 PEX_TX14 AK11 1 2 2
PEX_TX14_N TESTMODE
PEG_TXP14 AP26 ZZZ ZZZ ZZZ
PEX_RX14_N
PEG_RXP15 C9032 1 2 0.22U_0201_6.3V6-K PEG_RXP15_C AL25
PEX_TX15_N
PEG_TXP15 AN27 AP29 X7606101005 X7606101007 X7606101009
PEG_TXN15 AM27 PEX_RX15 PEX_TERMP S1G@
PEX_RX15_N S2G@ S4G@
1
R9656 R9657
N16P-GX_BGA908 2.49K_0402_1% 10K_0402_5%
GPU UV1 UV1 UV1
A A
2
N16S-GX1-A2 FCBGA 908P N16P-Q1-A2 FCBGA 908P N16P-Q3-A2 FCBGA 908P

SA00007DF00 SA00007CP00 SA00007CN00
N16S@ Q1@ Q3@
WALTER
Print Out Engineer Title
HTTPS://EN-MANUALS.CLAN.SU Issued Date 2015/07/16 Deciphered Date 2016/01/16 N16P-Q1/Q3(1/6): PEG I/F
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
5 4 3 2 1
5 4 3 2 1
Walter Unique
D D
UV1K UV1J UV1M

7/18 IFPD 6/18 IFPC 9/18 IFPG
ALL PINS NC FOR GF117
ALL PINS NC FOR GF117 ALL PINs XVDD FOR GM108/
ALL PINS NC FOR GM108 EXCEPT GPIO17
ALL PINS NC FOR GM108 EXCEPT GPIO15 GK107/GK208/GF117
AN2 NC
AF8
IFPD_RSET IFPC_RSET AA8
DVI/HDMI DP IFPCD_RSET DVI/HDMI DP NC_40 DVI/HDMI DP
VCC3VIDEO VCC3VIDEO
L50 GK107/GK208 GM107 L44 GM107
1 2 AG7 I2CX_SDA AK2 EDP_AUXN_D 1 2 AF7 I2CW_SDA AG2 EXT_AUXN_GPU AA6
IFPD_PLLVDD IFPD_AUX_I2CX_SDA_N EDP_AUXN_D <41> IFPC_PLLVDD IFPC_AUX_I2CW_SDA_N EXT_AUXN_GPU <43> NC_41
I2CX_SCL AK3 EDP_AUXP_D I2CW_SCL AG3 EXT_AUXP_GPU
IFPD_AUX_I2CX_SCL EDP_AUXP_D <41> IFPC_AUX_I2CW_SCL EXT_AUXP_GPU <43>
1
1K_0402_5%
1U_0402_10V6-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
4.7U_0402_6.3V6-M
BLM18PG181SN1D_0603 BLM18PG181SN1D_0603
R9951
1 1 1 1
1K_0402_5%
C9086
C9094
C9092
C9093
AK5 EDP_TXN3_D AG4 EXT_DP3N_GPU N16P@ 0.1U_0201_6.3V6-K 1 2 C292 AA5
TXC IFPD_L3_N EDP_TXN3_D <41> TXC IFPC_L3_N EXT_DP3N <6,43> TXC NC_17
R9952
AK4 EDP_TXP3_D AG5 EXT_DP3P_GPU N16P@ 0.1U_0201_6.3V6-K 1 2 C293 AA4
TXC IFPD_L3 EDP_TXP3_D <41> TXC IFPC_L3 EXT_DP3P <6,43> TXC NC_18
2
2 AL4 EDP_TXN2_D 2 2 2 AH4 EXT_DP2N_GPU N16P@ 0.1U_0201_6.3V6-K 1 2 C294 Y3

TXD0 IFPD_L2_N EDP_TXN2_D <41> TXD0 IFPC_L2_N EXT_DP2N <6,43> TXD0 NC_19
IFPD TXD0
AL3 EDP_TXP2_D
EDP_TXP2_D <41> IFPC TXD0
AH3 EXT_DP2P_GPU N16P@ 0.1U_0201_6.3V6-K 1 2 C295 EXT_DP2P <6,43> IFPG TXD0
Y2
2
VCC1R05VIDEO IFPD_L2 IFPC_L2 NC_20
L45 EDP_TXN1_D EXT_DP1N_GPU N16P@ 0.1U_0201_6.3V6-K 1
TXD1 AM4 EDP_TXN1_D <41> TXD1 AJ2 2 C296 EXT_DP1N <6,43> TXD1 AA3
1 2 IFPD_L1_N AM3 EDP_TXP1_D IFPC_L1_N AJ3 EXT_DP1P_GPU N16P@ 0.1U_0201_6.3V6-K 1 2 C297 NC_21 AA2
TXD1 IFPD_L1 EDP_TXP1_D <41> TXD1 IFPC_L1 EXT_DP1P <6,43> TXD1 NC_22
VCC1R05VIDEO
EDP_TXN0_D L43 EXT_DP0N_GPU N16P@ 0.1U_0201_6.3V6-K 1
BLM18PG181SN1D_0603 AM2 EDP_TXN0_D <41> AJ1 2 C298 EXT_DP0N <6,43> Y1
TXD2 IFPD_L0_N TXD2 IFPC_L0_N TXD2 NC_23
1U_0402_10V6-K
EDP_TXP0_D EXT_DP0P_GPU N16P@ 0.1U_0201_6.3V6-K 1

0.1U_0402_10V7-K
0.1U_0402_10V7-K
4.7U_0402_6.3V6-M
TXD2
AM1 EDP_TXP0_D <41> 1 2 TXD2
AK1 2 C299 EXT_DP0P <6,43> TXD2
AA1
IFPD_L0 IFPC_L0 NC_24
1 1 1 1
C9090
C9089
C9091
C9168
BLM18PG181SN1D_0603
1U_0402_10V6-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
4.7U_0402_6.3V6-M
AG6 M6 EDP_HPD_D 1 1 1 1 AF6 P2 AA7
2 2 2 2 IFPD_IOVDD GPIO17 EDP_HPD_D <41> IFPC_IOVDD GPIO15 EXT_DP_HPD <14,18,43> NC_42
C9097
C9096
C9098
C9095
N16P-GX_BGA908 N16P-GX_BGA908 N16P-GX_BGA908
2 2 2 2 EXT_AUXN_GPU
1
EXT_AUXP_GPU
100K_0402_5%
C C
R10005 TBT_SNK0_AUXN_GPU
EDP_AUXN_D
2
EDP_AUXP_D TBT_SNK0_AUXP_GPU
TBT_SNK1_AUXN_GPU
1
100K_0201_5%
100K_0201_5%
@ @
R10051
R10052
TBT_SNK1_AUXP_GPU
1
100K_0201_5%
100K_0201_5%
100K_0201_5%
100K_0201_5%
100K_0201_5%
100K_0201_5%
2
R10009
R10008
R10007
R10006
R10030
R10029
UV1L
8/18 IFPEF
2
UV1I ALL PINS NC FOR GF117
5/18 IFPAB ALL PINS NC FOR GM108 EXCEPT GPIO18/19
ALL PINS NC FOR GF117
ALL PINS NC FOR GM108 EXCEPT GPIO14
DVI-DL DVI-SL/HDMI DP
DP
LVDS
(GK208/GM107)
DPA_L3
AN6
R9953 IFPA_TXC_N TBT_SNK0_AUXN_GPU
DPA_L3
AM6 VCC3VIDEO I2CY_SDA I2CY_SDA AB4 TBT_SNK0_AUXN_GPU <46>
IFPA_TXC L49 IFPE_AUX_I2CY_SDA_N TBT_SNK0_AUXP_GPU
2 1 AJ8 I2CY_SCL I2CY_SCL AB3 TBT_SNK0_AUXP_GPU <46>
1K_0402_5% IFPAB_RSET 1 2 AB8 IFPE_AUX_I2CY_SCL
AN3 IFPEF_PLLVDD
DPA_L2 IFPA_TXD0_N TBT_SNK0_DP3N_GPU
0.1U_0402_10V7-K
DPA_L2
AP3 BLM18PG181SN1D_0603 AC5 N16P@ C322 2 1 0.1U_0201_6.3V6-K TBT_SNK0_DP3N <6,46>
IFPA_TXD0 TXC TXC IFPE_L3_N
1 AD6 AC4 TBT_SNK0_DP3P_GPU N16P@ C323 2 1 0.1U_0201_6.3V6-K TBT_SNK0_DP3P <6,46>
IFPEF_RSET TXC TXC IFPE_L3
C9099
AH8
IFPAB_PLLVDD AM5 NC FOR GK208 AC3 TBT_SNK0_DP2N_GPU N16P@ C324 2 1 0.1U_0201_6.3V6-K
DPA_L1 IFPA_TXD1_N IFPE_L2_N TBT_SNK0_DP2N <6,46>
1
1
TXD0 TXD0
10K_0402_5%
1K_0402_5%
DPA_L1 AN5 AC2 TBT_SNK0_DP2P_GPU N16P@ C325 2 1 0.1U_0201_6.3V6-K TBT_SNK0_DP2P <6,46>
IFPA_TXD1 2 TXD0 TXD0 IFPE_L2
R10002
R9954
AC1 TBT_SNK0_DP1N_GPU N16P@ C326 2 1 0.1U_0201_6.3V6-K TBT_SNK0_DP1N <6,46>
TXD1 TXD1 IFPE_L1_N
@ DPA_L0
AK6 AD1 TBT_SNK0_DP1P_GPU N16P@ C328 2 1 0.1U_0201_6.3V6-K TBT_SNK0_DP1P <6,46>
DPA_L0
IFPA_TXD2_N AL6 IFPE TXD1 TXD1 IFPE_L1
2
2
IFPA_TXD2 AD3 TBT_SNK0_DP0N_GPU N16P@ C330 2 1 0.1U_0201_6.3V6-K
TXD2 TXD2 IFPE_L0_N TBT_SNK0_DP0N <6,46>
AD2 TBT_SNK0_DP0P_GPU N16P@ C331 2 1 0.1U_0201_6.3V6-K TBT_SNK0_DP0P <6,46>
AH6 TXD2 TXD2 IFPE_L0
B IFPA_TXD3_N AJ6 B
IFPA_TXD3 NC FOR GK208
DPB_L3
AH9
IFPB_TXC_N AJ9 R1 TBT_SNK0_DPHPD_GPU N16P@ R10040 1 2 0_0402_5%
DPB_L3 HPD_E HPD_E
IFPB_TXC GPIO18 TBT_SNK0_DPHPD <14,18,46>
AG8
IFPA_IOVDD AP5
DPB_L2 IFPB_TXD4_N
AG9 DPB_L2
AP6
IFPB_IOVDD IFPB_TXD4
VCC1R05VIDEO
L42
1
1
10K_0402_5%
10K_0402_5%
DPB_L1 AL7
IFPB_TXD5_N
R10003
R10004
DPB_L1 AM7 1 2 AC7

IFPB_TXD5 IFPE_IOVDD AF2 TBT_SNK1_AUXN_GPU N16P@ C332 2 1 0.1U_0201_6.3V6-K
I2CZ_SDA IFPF_AUX_I2CZ_SDA_N TBT_SNK1_AUXN <6,46>
@ @ BLM18PG181SN1D_0603 I2CZ_SCL AF3 TBT_SNK1_AUXP_GPU N16P@ C333 2 1 0.1U_0201_6.3V6-K
IFPF_AUX_I2CZ_SCL TBT_SNK1_AUXP <6,46>
1U_0402_10V6-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
4.7U_0402_6.3V6-M
DPB_L0
AM8 AC8
2
IFPB_TXD6_N AN8 IFPF_IOVDD

DPB_L0 IFPB_TXD6 1 1 1 1
C9102
C9101
C9103
C9100
NC FOR GK208 TXC AF1 TBT_SNK1_DP3N_GPU N16P@ C334 2 1 0.1U_0201_6.3V6-K TBT_SNK1_DP3N <6,46>
IFPF_L3_N AG1 TBT_SNK1_DP3P_GPU N16P@ C335 2 1 0.1U_0201_6.3V6-K
TXC IFPF_L3 TBT_SNK1_DP3P <6,46>
AL8
IFPB_TXD7_N AK8 2 2 2 2 AD5 TBT_SNK1_DP2N_GPU N16P@ C336 2 1 0.1U_0201_6.3V6-K
IFPB_TXD7 TXD3 TXD0 IFPF_L2_N TBT_SNK1_DP2N <6,46>
AD4 TBT_SNK1_DP2P_GPU N16P@ C337 2 1 0.1U_0201_6.3V6-K TBT_SNK1_DP2P <6,46>
TXD3 TXD0 IFPF_L2
TXD4 TXD1 AF5 TBT_SNK1_DP1N_GPU N16P@ C338 2 1 0.1U_0201_6.3V6-K TBT_SNK1_DP1N <6,46>
IFPF TXD4 TXD1
IFPF_L1_N
IFPF_L1
AF4 TBT_SNK1_DP1P_GPU N16P@ C339 2 1 0.1U_0201_6.3V6-K TBT_SNK1_DP1P <6,46>
N4 AE4 TBT_SNK1_DP0N_GPU N16P@ C340 2 1 0.1U_0201_6.3V6-K TBT_SNK1_DP0N <6,46>
GPIO14 TXD5 TXD2 IFPF_L0_N AE3 TBT_SNK1_DP0P_GPU N16P@ C342 2 1 0.1U_0201_6.3V6-K
IFPAB TXD5 TXD2 IFPF_L0 TBT_SNK1_DP0P <6,46>
N16P-GX_BGA908 NC FOR GK208
HPD_F P3 TBT_SNK1_DPHPD_GPU N16P@ R10041 1 2 0_0402_5%

GPIO19 TBT_SNK1_DPHPD <14,18,46>
N16P-GX_BGA908
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 N16P-Q1/Q3(2/6): DIGITAL OUT I/F
5 4 3 2 1
5 4 3 2 1
Walter Unique UV1B

2/18 FBA
UV1C
3/18 FBB
ALL PINS NC FOR GM108/

<37> FBA_D[0..63] <38> FBB_D[0..63] GK208/GF117
FBA_D0 L28 E1 FBB_D0 G9
FBA_D1 M29 FBA_D0 FB_CLAMP FBB_D1 E9 FBB_D0
FBA_D1 FBB_D1
10K_0402_5%
FBA_D2 L29 FBB_D2 G8
FBA_D2 FBB_D2
R10015
FBA_D3 M28 FBB_D3 F9
FBA_D4 N31 FBA_D3 FBB_D4 F11 FBB_D3
FBA_D5 P29 FBA_D4 K27 FBB_D5 G11 FBB_D4
FBA_D6 R29 FBA_D5 FB_DLL_AVDD FBB_D6 F12 FBB_D5
D D
2
FBA_D7 P28 FBA_D6 FBB_D7 G12 FBB_D6
FBA_D8 J28 FBA_D7 FB_PLLAVDD VCC1R05VIDEO FBB_D8 G6 FBB_D7
FBA_D9 H29 FBA_D8 FBB_D9 F5 FBB_D8
FBA_D10 J29 FBA_D9 LB3 FBB_D10 E6 FBB_D9
FBA_D11 H28 FBA_D10 FB_PLLAVDD 1 2 FBB_D11 F6 FBB_D10
FBA_D12 G29 FBA_D11 FBB_D12 F4 FBB_D11
FBA_D13 E31 FBA_D12 MPZ1608S300AT_2P~D FBB_D13 G4 FBB_D12
FBA_D13 FBB_D13
22U_0805_6.3VA-M
FBA_D14 FBB_D14
0.1U_0402_16V7-K
E32 E2
FBA_D15 F30 FBA_D14 FBB_D15 F3 FBB_D14
FBA_D15 1 1 FBB_D15
C9143
C9146
FBA_D16 C34 FBB_D16 C2
FBA_D17 D32 FBA_D16 FBB_D17 D4 FBB_D16
FBA_D18 B33 FBA_D17 FBB_D18 D3 FBB_D17
FBA_D19 C33 FBA_D18 2 2 FBB_D19 C1 FBB_D18
FBA_D20 F33 FBA_D19 FBB_D20 B3 FBB_D19
FBA_D21 F32 FBA_D20 FBB_D21 C4 FBB_D20
FBA_D22 H33 FBA_D21 FBB_D22 B5 FBB_D21
FBA_D23 H32 FBA_D22 FBB_D23 C5 FBB_D22
FBA_D24 P34 FBA_D23 FBB_D24 A11 FBB_D23
FBA_D25 P32 FBA_D24 FBB_D25 C11 FBB_D24
FBA_D26 P31 FBA_D25 FBB_D26 D11 FBB_D25
FBA_D27 P33 FBA_D26 FBB_D27 B11 FBB_D26
FBA_D28 L31 FBA_D27 FBB_D28 D8 FBB_D27
FBA_D29 L34 FBA_D28 FBB_D29 A8 FBB_D28
FBA_D30 L32 FBA_D29 FBB_D30 C8 FBB_D29
FBA_D31 L33 FBA_D30 FBB_D31 B8 FBB_D30
FBA_D32 AG28 FBA_D31 FBB_D32 F24 FBB_D31
FBA_D33 AF29 FBA_D32 U30 FBA_CS#_L FBB_D33 G23 FBB_D32 D13 FBB_CS#_L
FBA_D33 FBA_CMD0 FBA_CS#_L <37> FBB_D33 FBB_CMD0 FBB_CS#_L <38>
FBA_D34 AG29 T31 FBA_BA3_L FBB_D34 E24 E14 FBB_BA3_L
FBA_D34 FBA_CMD1 FBA_BA3_L <37> FBB_D34 FBB_CMD1 FBB_BA3_L <38>
FBA_D35 AF28 U29 FBA_BA0_L FBB_D35 G24 F14 FBB_BA0_L
FBA_D36 AD30 R34 FBA_BA2_L FBB_D36 D21 A12 FBB_BA2_L
FBA_D37 AD29 R33 FBA_BA1_L FBB_D37 E21 B12 FBB_BA1_L
FBA_D38 AC29 U32 FBA_WE#_L FBB_D38 G21 C14 FBB_WE#_L
FBA_D38 FBA_CMD5 FBA_WE#_L <37> FBB_D38 FBB_CMD5 FBB_WE#_L <38>
FBA_D39 AD28 U33 FBA_MA8_L FBB_D39 F21 B14 FBB_MA8_L
FBA_D39 FBA_CMD6 FBA_MA8_L <37> FBB_D39 FBB_CMD6 FBB_MA8_L <38>
FBA_D40 AJ29 U28 FBA_MA11_L FBB_D40 G27 G15 FBB_MA11_L
C FBA_D40 FBA_CMD7 FBA_MA11_L <37> FBB_D40 FBB_CMD7 FBB_MA11_L <38> C
FBA_D41 AK29 V28 FBA_ABI#_L FBB_D41 D27 F15 FBB_ABI#_L
FBA_D41 FBA_CMD8 FBA_ABI#_L <37> FBB_D41 FBB_CMD8 FBB_ABI#_L <38>
FBA_D42 AJ30 V29 FBA_RFU_L FBB_D42 G26 E15 FBB_RFU_L
FBA_D42 FBA_CMD9 FBA_RFU_L <37> FBB_D42 FBB_CMD9 FBB_RFU_L <38>
FBA_D43 AK28 V30 FBA_MA10_L FBB_D43 E27 D15 FBB_MA10_L
FBA_D44 AM29 U34 FBA_MA9_L FBB_D44 E29 A14 FBB_MA9_L
FBA_D45 AM31 U31 FBA_RAS#_L FBB_D45 F29 D14 FBB_RAS#_L
FBA_D45 FBA_CMD12 FBA_RAS#_L <37> FBB_D45 FBB_CMD12 FBB_RAS#_L <38>
FBA_D46 AN29 V34 FBA_RST#_L FBB_D46 E30 A15 FBB_RST#_L
FBA_D46 FBA_CMD13 FBA_RST#_L <37> FBB_D46 FBB_CMD13 FBB_RST#_L <38>
FBA_D47 AM30 V33 FBA_CKE_L FBB_D47 D30 B15 FBB_CKE_L
FBA_D47 FBA_CMD14 FBA_CKE_L <37> FBB_D47 FBB_CMD14 FBB_CKE_L <38>
FBA_D48 AN31 Y32 FBA_CAS#_L FBB_D48 A32 C17 FBB_CAS#_L
FBA_D48 FBA_CMD15 FBA_CAS#_L <37> FBB_D48 FBB_CMD15 FBB_CAS#_L <38>
FBA_D49 AN32 AA31 FBA_CS#_H FBB_D49 C31 D18 FBB_CS#_H
FBA_D49 FBA_CMD16 FBA_CS#_H <37> FBB_D49 FBB_CMD16 FBB_CS#_H <38>
FBA_D50 AP30 AA29 FBA_BA3_H FBB_D50 C32 E18 FBB_BA3_H
FBA_D50 FBA_CMD17 FBA_BA3_H <37> FBB_D50 FBB_CMD17 FBB_BA3_H <38>
FBA_D51 AP32 AA28 FBA_BA0_H FBB_D51 B32 F18 FBB_BA0_H
FBA_D52 AM33 AC34 FBA_BA2_H FBB_D52 D29 A20 FBB_BA2_H
FBA_D53 AL31 AC33 FBA_BA1_H FBB_D53 A29 B20 FBB_BA1_H
FBA_D54 AK33 AA32 FBA_WE#_H FBB_D54 C29 C18 FBB_WE#_H
FBA_D54 FBA_CMD21 FBA_WE#_H <37> FBB_D54 FBB_CMD21 FBB_WE#_H <38>
FBA_D55 AK32 AA33 FBA_MA8_H FBB_D55 B29 B18 FBB_MA8_H
FBA_D55 FBA_CMD22 FBA_MA8_H <37> FBB_D55 FBB_CMD22 FBB_MA8_H <38>
FBA_D56 AD34 Y28 FBA_MA11_H FBB_D56 B21 G18 FBB_MA11_H
FBA_D57 AD32 Y29 FBA_ABI#_H FBB_D57 C23 G17 FBB_ABI#_H
FBA_D57 FBA_CMD24 FBA_ABI#_H <37> FBB_D57 FBB_CMD24 FBB_ABI#_H <38>
FBA_D58 AC30 W31 FBA_RFU_H FBB_D58 A21 F17 FBB_RFU_H
FBA_D58 FBA_CMD25 FBA_RFU_H <37> FBB_D58 FBB_CMD25 FBB_RFU_H <38>
FBA_D59 AD33 Y30 FBA_MA10_H FBB_D59 C21 D16 FBB_MA10_H
FBA_D60 AF31 AA34 FBA_MA9_H FBB_D60 B24 A18 FBB_MA9_H
FBA_D61 AG34 Y31 FBA_RAS#_H FBB_D61 C24 D17 FBB_RAS#_H
FBA_D61 FBA_CMD28 FBA_RAS#_H <37> FBB_D61 FBB_CMD28 FBB_RAS#_H <38>
FBA_D62 AG32 Y34 FBA_RST#_H FBB_D62 B26 A17 FBB_RST#_H
FBA_D62 FBA_CMD29 FBA_RST#_H <37> FBB_D62 FBB_CMD29 FBB_RST#_H <38>
FBA_D63 AG33 Y33 FBA_CKE_H FBB_D63 C26 B17 FBB_CKE_H
FBA_D63 FBA_CMD30 FBA_CKE_H <37> FBB_D63 FBB_CMD30 FBB_CKE_H <38>
V31 FBA_CAS#_H E17 FBB_CAS#_H
FBA_CMD31 FBA_CAS#_H <37> FBB_CMD31 FBB_CAS#_H <38>
FBA_DEBUG0
R28 FBB_DEBUG0
G14
FBA_DBI0# P30 FBA_CMD32 AC28 FBB_DBI0# E11 FBB_CMD32 G20
<37> FBA_DBI0# FBA_DQM0 FBA_DEBUG1 FBA_CMD33 <38> FBB_DBI0# FBB_DQM0 FBB_DEBUG1 FBB_CMD33
FBA_DBI1# F31 R32 FBB_DBI1# E3 C12
<37> FBA_DBI1# FBA_DQM1 NC FBA_CMD34 <38> FBB_DBI1# FBB_DQM1 NC FBB_CMD34
FBA_DBI2# F34 AC32 FBB_DBI2# A3 NC C20
<37> FBA_DBI2# FBA_DQM2 NC FBA_CMD35 <38> FBB_DBI2# FBB_DQM2 FBB_CMD35
FBA_DBI3# M32 FBB_DBI3# C9
<37> FBA_DBI3# FBA_DQM3 GK107/GK208
GM107/GM108 <38> FBB_DBI3# FBB_DQM3 GK107 GM107
FBA_DBI4# AD31 GF117 FBB_DBI4# F23
<37> FBA_DBI4# FBA_DQM4 <38> FBB_DBI4# FBB_DQM4
FBA_DBI5# AL29 FBB_DBI5# F27
FBA_DBI6# AM32 FBB_DBI6# C30
FBA_DBI7# AF34 FBB_DBI7# A24
B B
FBA_EDC0 M31 FBB_EDC0 D10
<37> FBA_EDC0 FBA_DQS_WP0 <38> FBB_EDC0 FBB_DQS_WP0
FBA_EDC1 G31 FBB_EDC1 D5
FBA_EDC2 E33 R30 FBB_EDC2 C3 D12
<37> FBA_EDC2 FBA_DQS_WP2 FBA_CLK0 FBA_CLK0 <37> <38> FBB_EDC2 FBB_DQS_WP2 FBB_CLK0 FBB_CLK0 <38>
FBA_EDC3 M33 R31 FBB_EDC3 B9 E12
<37> FBA_EDC3 FBA_DQS_WP3 FBA_CLK0_N FBA_CLK0# <37> <38> FBB_EDC3 FBB_DQS_WP3 FBB_CLK0_N FBB_CLK0# <38>
FBA_EDC4 AE31 AB31 FBB_EDC4 E23 E20
<37> FBA_EDC4 FBA_DQS_WP4 FBA_CLK1 FBA_CLK1 <37> <38> FBB_EDC4 FBB_DQS_WP4 FBB_CLK1 FBB_CLK1 <38>
FBA_EDC5 AK30 AC31 FBB_EDC5 E28 F20
<37> FBA_EDC5 FBA_DQS_WP5 FBA_CLK1_N FBA_CLK1# <37> <38> FBB_EDC5 FBB_DQS_WP5 FBB_CLK1_N FBB_CLK1# <38>
FBA_EDC6 AN33 FBB_EDC6 B30
FBA_EDC7 AF33 FBB_EDC7 A23
M30 K31 D9 F8
FBA_DQS_RN0 FBA_WCK01 FBA_WCK0 <37> FBB_DQS_RN0 FBB_WCK01 FBB_WCK0 <38>
H30 L30 E4 E8
FBA_DQS_RN1 FBA_WCK01_N FBA_WCK0_N <37> FBB_DQS_RN1 FBB_WCK01_N FBB_WCK0_N <38>
E34 H34 B2 A5
M34 J34 A9 A6
AF30 AG30 D22 D24
AK31 AG31 D28 D25
AM34 AJ34 A30 B27
AF32 AK34 B23 C27
J30 D6
NC_25 J31 NC_33 D7
FBA_WCKBxx ARE FBB_WCKBxx ARE
NC_26 J32 NC_34 C6
RESERVED,NC ON: RESERVED,NC ON:
NC_27 J33 NC_35 B6
GM108/GM107 GM108/GM107
NC_28 AH31 NC_36 F26
GK208/GF117
NC_29 AJ31 USED ONLY ON: NC_37 E26
USED ONLY ON: NC_30 AJ32 GK107 NC_38 A26
GK107 NC_31 AJ33 NC_39 A27
NC_32 NC_40
TP918
1 Test_Point_20MIL H26 H17 FB_PLLAVDD
FB_VREF FB_PLLAVDD FBB_PLL_AVDD
0.1U_0402_16V7-K
U27
FBA_PLL_AVDD
0.1U_0402_16V7-K
C9147
N16P-GX_BGA908 1 N16P-GX_BGA908
C9144
A 2 A
2
FBx_PLL_AVDD
Capactior GB4B-128/GDDR5
Type NV DG Actual
0.1uF_0402 3 3
22uF_0805 1 1

Issued Date 2015/07/16 Deciphered Date 2016/01/16 033_N16P-Q1/Q3(3/6): MEMORY I/F
5 4 3 2 1
5 4 3 2 1
Walter Unique
-GPU_RST <31,77>
VCC3VIDEO
VCC3VIDEO
1
10K_0402_1%
10K_0402_1%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
2.2K_0402_1%
2.2K_0402_1%
2.2K_0402_1%
2.2K_0402_1%
2
G
R9646
R9163
R9836
R9837
R9838
R9839
R9945
R9946
R9948
R9947
D -GPU_RST D
@ @ QV16
100K_0201_5%
3 1
I2C_CLK_VIDEO <77>
R9997
@
D
1
2
G
UV1R 2N7002W-T/R7_SOT323-3
11/18 MISC1
T4 3 1 VCC3VIDEO
I2C_DATA_VIDEO <77>
2
I2CS_SCL
2
G T3 QV17
D
GM107/GM108 GK107
GK208 GF117
I2CS_SDA
2N7002W-T/R7_SOT323-3
1 3 M1 GPIO8
R2
<77> -VIDEO_THERM_OVERT OVERT I2CC_SCL
1
10K_0402_5%
10K_0402_5%
R3
D
I2CC_SDA
R10000
R10001
UV1N
NC R7 4/18 DACA
QV14 K4 I2CB_SCL R6 VCC3VIDEO
THERMDN NC I2CB_SDA
GM107
GM108/GF117
GF117 GM107/GK208
2N7002W-T/R7_SOT323-3 GK107/GK208 GM108 GK107
2
GM107/GM108
K3 GF117
GK107/GK208 AG10 NC R4
THERMDP DACA_VDD NC I2CA_SCL
1
100K_0201_5%
10K_0402_5%
NC R5
I2CA_SDA
10K_0402_5%
R432
R9983
AP9 TSEN_VREF
DACA_VREF GM108 GM107
R9999
Test_Point_20MIL TP919 1 AM10 GF117 GK107/GK208
Test_Point_20MIL TP920 1 AP11 JTAG_TCK @ AP8 AM9
Test_Point_20MIL TP921 1 AM11 JTAG_TMS GPIO 0,5,6 / @ DACA_RSET NC NC
NC
DACA_HSYNC AN9
2
JTAG_TDI DACA_VSYNC
Test_Point_20MIL TP922 1 AP12 Reserve for GC6
2
AN11 JTAG_TDO P6
JTAG_TRST_N GPIO0 M3 AK9
GPIO1 NC DACA_RED
L6
GPIO2 PANEL_BKLT_CTRL_D <41>
P5 NC
AL10
GPIO3 PANEL_POWER_ON_D <41> DACA_GREEN
P7
GPIO4 VGA_BLON_D <41>
L7 AL9
2
GPIO5 NC DACA_BLUE
M7
R9643 GPIO6 -GPU_EVENT <17>
N8
10K_0402_5% GK107/GK208/GF117 GPIO7 L3 GPIO8_GPU N16P-GX_BGA908
NC
GPIO8 M2
GPIO9 -VIDEO_THERM_ALERT <61,77>
L1
1
GPIO10 MEM_VREF <37,38>

M5
GPIO11 VIDEO_PWM_VID <110>
N3
GPIO12 GFX_PSI -VIDEO_POWER_LIMIT <77>
M4
GPIO13 GFX_PSI <110>
GPIO16 NC GPIO16
R8
GPIO16 P4
GPIO20 NC NC GPIO20
GPIO8 NC NC
P1
GPIO21
GM107
GK208 GF117 GK107 GM108
@
TABLE
1 R9942
1 R9941
1 R9940
1 R9647
1 R9943
1 R9944
1 R9949
N15P-Q1 QS: N15P-Q3 QS:
STRAP2 0x0FF6 0x11FC N16P-GX_BGA908
PU R8607 NO_ASM 24.9K ohm
100K_0402_5% 2
100K_0402_5% 2
100K_0402_5% 2
100K_0402_5% 2
C C
PD R8610 34.8K ohm NO_ASM
10K_0402_5% 2
10K_0402_5% 2
100K_0402_5% 2
ROM_SI table for VRAM vendor ROM_SI table for 8G VRAM
TABLE Vendor PD R9735 LCFC P/N Vendor PU R9734 LCFC P/N
Samsung S@ 20K_1% SD02820028T Samsung S8G@ 4.99K SD03449910T
N16P-Q1 QS: N16P-Q3 QS:
STRAP2 0x0FF6 0x11FC Hynix H@ 34.8K_1% SD03434828T
PU R8607 NO_ASM 24.9K ohm
52mA
PD R8610 34.8K ohm NO_ASM
VCC1R05VIDEO_PLL
30ohm@100MHz ESR=0.01
LB2 need to check -ROM_CS_GPU connector?
1 2 LOGIC VCC3VIDEO
VCC3VIDEO
MPZ1608S300AT_2P~D
2 2 UV1Q
13/18 MISC2
C8420 C8421
1
22U_0805_6.3V7M 0.1U_0402_25V7K For VBIOS ROM X76@ @
1
112mA 1 1 R9734 R9736 R9738
R9724 R9726 @ R9728 @ R9731 @ R9733 @ TP956 2.2K_0402_1% 10K_0402_5% 20K_0402_1%
VCC1R05VIDEO_PLL UV1P 49.9K_0402_1% 34.8K_0402_1% 45.3K_0402_1% 4.99K_0402_1% 10K_0402_5% H6 -ROM_CS_GPU1
NEAR BALL ROM_CS_N
12/18 XTAL_PLL
2
H5 ROM_SI_GPU Test_Point_20MIL
2
ROM_SI H7 ROM_SO_GPU
L39 STRAP0_GPU ROM_SO
AD8 J2 H4 ROM_SCLK_GPU
1 2
180ohm@100MHz ESR=0.09 AE8 PLLVDD STRAP1_GPU J7 STRAP0 ROM_SCLK
SP_PLLVDD STRAP1 NC
STRAP2_GPU J6
STRAP2 NC
BLM18PG181SN1_0603~D AD7 STRAP3_GPU J5 NC
VID_PLLVDD NC STRAP3
2 1 2 2 STRAP4_GPU J3 NC
C8422 STRAP4
GM107 GM108 GK107/GK208
1
C8423 C8424 C8425 GK107/GK208 GF117 GF117 GM107 GM108 X76@
1
22U_0805_6.3V7M 4.7U_0402_6.3V6M 0.1U_0402_25V7K 0.1U_0402_25V7K R9735 R9739 @
1 2 1 1 R9725 @ R9727 @ R9729 @ R9730 @ R9732 @ 30K_0402_1% 15K_0402_5%
VIDEO_CLK_XTAL_SS H1 J4 XTAL_OUTBUFF_GPU 2K_0402_1% 4.99K_0402_1% 34.8K_0402_1% 4.99K_0402_1% 45.3K_0402_1% L2
XTAL_SSIN XTAL_OUTBUFF BUFRST_N
50-ohm TRACE
2
2
2
H3 H2
UNDER GPU XTAL_IN XTAL_OUT MULTI_STRAP_REF0_GND_GPU
J1
MULTI_STRAP_REF0_GND
1
1
N16P-GX_BGA908
B R9744 R9743 B
10K_0402_5% 10K_0402_5%
1
R9740
2
2
40.2K_0402_1%
N16P-GX_BGA908
2
R9741 @ 1 2 1M_0402_5% 27MHZ_OUT
1
R9742
2.2K_0402_5%
VCC3B
Crystal 2 ROM_SO_GPU
4 3
GND2 OUT
1
1
27MHZ_IN 1 2 R10047
IN GND1 R10050 4.99K_0201_1%
1 10K_0402_5%
Y5 1
2
C9187 27MHZ_7PF_8Y27000005
2
10P_0402_50V8-J C9188
1
2 8P_0402_50V8-B D
1
2 2
G R10048
1
D
S QV18 4.99K_0201_1%
3
2 2N7002W-T/R7_SOT323-3
<14> -VGA_DISABLE
G
2
S QV19
3
2N7002W-T/R7_SOT323-3
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 034_N16P-Q1/Q3(4/6): GPIO
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
5 4 3 2 1
5 4 3 2 1
Walter Unique VCCGFXCORE_D UV1G

UV1D
UV1H
10/18 XVDD
14/18 NVVDD 15/18 FBVDDQ CONFIGURABLE

POWER
AA12 AA27 CHANNELS
AA14 VDD_01 AA30 FBVDDQ_01 U1
VDD_02 FBVDDQ_02 XVDD_01
47U_0805_6.3V6-M
22U_0805_6.3V6-M
4.7U_0402_6.3V6-M
4.7U_0402_6.3V6-M
4.7U_0402_6.3V6-M
4.7U_0402_6.3V6-M
4.7U_0402_6.3V6-M
0.1U_0402_16V7-K
0.1U_0402_16V7-K
0.1U_0402_16V7-K
0.1U_0402_16V7-K
AA16 AB27 U2
AA19 VDD_03 AB33 FBVDDQ_03 XVDD_02 U3
1 1 1 1 1 1 1 1 1 1 1 VDD_04 FBVDDQ_04 XVDD_03
C9127
C9126
C9125
C9124
C9123
C9122
C9121
C9128
C9129
C9130
C9131
AA21 AC27 U4
AA23 VDD_05 AD27 FBVDDQ_05 XVDD_04 U5
AB13 VDD_06 AE27 FBVDDQ_06 XVDD_05 U6
D 2 2 2 2 2 2 2 2 2 2 2 AB15 VDD_07 AF27 FBVDDQ_07 XVDD_06 U7 D
AB17 VDD_08 AG27 FBVDDQ_08 XVDD_07 U8
AB18 VDD_09 B13 FBVDDQ_09 XVDD_08 V1
AB20 VDD_10 B19 FBVDDQ_10 XVDD_09
AB22 VDD_11 E13 FBVDDQ_11
AC12 VDD_12 E19 FBVDDQ_12 V2
AC14 VDD_13 H10 FBVDDQ_13 XVDD_10 V3
4.7U_0603_6.3VA-K
4.7U_0603_6.3VA-K
4.7U_0603_6.3VA-K
4.7U_0603_6.3VA-K
4.7U_0603_6.3VA-K
4.7U_0603_6.3VA-K
4.7U_0603_6.3VA-K
4.7U_0603_6.3VA-K
4.7U_0603_6.3VA-K
4.7U_0603_6.3VA-K
1 1 1 1 1 1 1 1 1 1 VDD_17 FBVDDQ_17 XVDD_14
C9141
C9140
C9138
C9139
C9137
C9136
C9135
C9134
C9133
C9132
AC23 H14 V7
M12 VDD_18 H18 FBVDDQ_18 XVDD_15 V8
M14 VDD_19 H19 FBVDDQ_19 XVDD_16 W2
2 2 2 2 2 2 2 2 2 2 M16 VDD_20 H20 FBVDDQ_20 XVDD_17 W3
M19 VDD_21 H21 FBVDDQ_21 XVDD_18
M21 VDD_22 H22 FBVDDQ_22
M23 VDD_23 H23 FBVDDQ_23 W4
N13 VDD_24 H24 FBVDDQ_24 XVDD_19 W5
N18 VDD_27 L27 FBVDDQ_27 XVDD_22 Y4
N20 VDD_28 M27 FBVDDQ_28 XVDD_23 Y5
N22 VDD_29 N27 FBVDDQ_29 XVDD_24 Y6
P12 VDD_30 P27 FBVDDQ_30 XVDD_25 Y7
P14 VDD_31 R27 FBVDDQ_31 XVDD_26 Y8
P16 VDD_32 T27 FBVDDQ_32 XVDD_27
P19 VDD_33 T30 FBVDDQ_33
P21 VDD_34 T33 FBVDDQ_34
P23 VDD_35 Y27 FBVDDQ_35
R13 VDD_36 FBVDDQ_36
R15 VDD_37 B16
VDD_38 FBVDDQ_AON_1 FBVDDQ VCC1R35VIDEO
R17 E16 FBVDDQ
C UV1O R18 VDD_39 H15 FBVDDQ_AON_2 C
VDD_40 FBVDDQ_AON_3 FBVDDQ
R20 H16 FBVDDQ
18/18 NC/VDD33 VCC3VIDEO VDD_41 FBVDDQ_AON_4
R22 V27 FBVDDQ
T12 VDD_42 W27 FBVDDQ_AON_5
GK208 GM107
VDD_43 FBVDDQ_AON_6 FBVDDQ
GF117
GK107
GM108 UNDER GPU T14 W30 FBVDDQ
VDD_44 FBVDDQ_AON_7
2
AJ28 J8 T16 W33 FBVDDQ
NC_1 VDD33 3V3MISC 3V3_AON_1 K8 T19 VDD_45 FBVDDQ_AON_8 R9658 R9183
C15 VDD33 3V3MISC 3V3_AON_2 VDD_46 GK107/
0.1U_0402_25V6-K
0.1U_0402_25V6-K
1U_0402_6.3V6-K
4.7U_0402_6.3V6-M
NC_2 T21 100_0402_1% 40.2_0402_1%

0.1U_0402_25V6-K
D19 VDD_47 GM107/GM108 GK208/

D20 NC_3 L8 T23 GF117
NC_4 3V3_MAIN_1 M8 U13 VDD_48
D23 1 1 1 1
1
3V3_MAIN_2 VDD_49
CV293
CV75
NC_5 U15
CV109
CV111
CV288
D26 VDD_50
H31 NC_6 U17 F1 N16P-GX_BGA908
VDD_51 FB_VDDQ_SENSE VCC_VCC1R35VIDEO_SENSE <111>
V32 NC_7 U18
NC_8 2 2 2 2 U20 VDD_52 F2
VDD_53 FB_GND_SENSE VSS_VCC1R35VIDEO_SENSE <111>
AC6 U22
NC_9 DO NOT V13 VDD_54 J27 FB_CAL_PD_VDDQ_GPU
AJ4 VDD_55 FB_CAL_PD_VDDQ
AJ5 NC_10 CONNECT V15
NC_11 THESE V17 VDD_56 H27 FB_CAL_PU_GND_GPU
AL11 VDD_57 FB_CAL_PU_GND
T8 NC_12 PINS V18
NC_13 V20 VDD_58 H25 FB_CAL_TERM_GND_GPU
V22 VDD_59 FB_CAL_TERM_GND
W12 VDD_60
N16P-GX_BGA908 W14 VDD_61 N16P-GX_BGA908
VDD_62
1
100_0402_1%
60.4K_0402_1%
40.2_0402_1%
W16
VDD_63
R9660
R9655
R9659
W19
W21 VDD_64
W23 VDD_65
Y13 VDD_66
2
Y15 VDD_67
Y17 VDD_68
Y18 VDD_69
Y20 VDD_70
B Y22 VDD_71 B
VDD_72
N16P-GX_BGA908
VCC1R35VIDEO
UNDER GPU
22U_0805_6.3V6-M
22U_0805_6.3V6-M
10U_0603_6.3V6-M
10U_0603_6.3V6-M
4.7U_0402_6.3V6-M
4.7U_0402_6.3V6-M
4.7U_0402_6.3V6-M
4.7U_0402_6.3V6-M
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV275
CV276
CV270
CV271
CV263
CV264
CV265
CV266
CV278
CV279
CV280
CV281
CV284
CV285
CV286
CV287
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Power Team Request:

From two 22uF 0805 to four 10uF 0603
NVVDD Decoupling FBVDDQ Decoupling

Capactior GB4B-128 Capactior GB4B-128/GDDR5
A Type NV DG Actual Type NV DG Actual A
4.7uF_0603 15 4 0.1uF_0402 4 4
1uF_0402 8 4 1uF_0603 4 4
22uF_0805 14 4 4.7uF_0603 4 4
4.7uF_0805 10uF_0805 2
330uF_7343 2 2 22uF_0805 2 2

Issued Date 2015/07/16 Deciphered Date 2016/01/16 035_N16P-Q1/Q3(5/6): POWER
5 4 3 2 1
5 4 3 2 1
Walter Unique
D D
UV1E
16/18 GND_1/2
A2 AM25
A33 GND_001 GND_071 AN1
AA13 GND_002 GND_072 AN10
AA18 GND_005 GND_075 AN19 UV1F
AA20 GND_006 GND_076 AN22 17/18 GND_2/2
AB12 GND_008 GND_078 AN30 N19 T28
AB14 GND_009 GND_079 AN34 N2 GND_141 GND_171 T32
AB2 GND_012 GND_082 AP2 N28 GND_144 GND_174 U12
AB21 GND_013 GND_083 AP33 N30 GND_145 GND_175 U14
AB23 GND_014 GND_084 B1 N32 GND_146 GND_176 U16
AB5 GND_018 GND_088 B28 P13 GND_150 GND_180 V12
AB7 GND_019 GND_089 B31 P15 GND_151 GND_181 V14
AC13 GND_020 GND_090 B34 P17 GND_152 GND_182 V16
AC18 GND_023 GND_093 C10 P22 GND_155 GND_185 V23
AC20 GND_024 GND_094 C13 R12 GND_156 GND_186 W13
AC22 GND_025 GND_095 C19 R14 GND_157 GND_187 W15
C AE2 GND_026 GND_096 C22 R16 GND_158 GND_188 W17 C
AE28 GND_027 GND_097 C25 R19 GND_159 GND_189 W18
AE33 GND_030 GND_100 D2 T13 GND_162 GND_192 W28
AE5 GND_031 GND_101 D31 T15 GND_163 GND_193 Y12
AE7 GND_032 GND_102 D33 T17 GND_164 GND_194 Y14
AH10 GND_033 GND_103 E10 T18 GND_165 GND_195 Y16
AH2 GND_037 GND_107 E7 GND_169 GND_199
AH22 GND_038 GND_108 F28
AH24 GND_039 GND_109 F7
AH28 GND_040 GND_110 G10
AH29 GND_041 GND_111 G13
AH30 GND_042 GND_112 G16
AH32 GND_043 GND_113 G19 AG11 AH11
AH33 GND_044 GND_114 G2 GND_170 GND_200
AH5 GND_045 GND_115 G22
AH7 GND_046 GND_116 G25
AJ7 GND_047 GND_117 G28
AK10 GND_048 GND_118 G3
AK7 GND_049 GND_119 G30
AL12 GND_050 GND_120 G32
AL14 GND_051 GND_121 G33 C16
AL15 GND_052 GND_122 G5 GND_OPT_1 W32
AL17 GND_053 GND_123 G7 GND_OPT_2
AL18 GND_054 GND_124 K2 Optional CMD GNDs (2)
AL2 GND_055 GND_125 K28 NC for 4-Lyr cards
AL20 GND_056 GND_126 K30
AL21 GND_057 GND_127 K32 N16P-GX_BGA908
B AL23 GND_058 GND_128 K33 B
AL24 GND_059 GND_129 K5
AL26 GND_060 GND_130 K7
AL28 GND_061 GND_131 M13
AL30 GND_062 GND_132 M15
AL32 GND_063 GND_133 M17
AL33 GND_064 GND_134 M18
AL5 GND_065 GND_135 M20
AM13 GND_066 GND_136 M22
AM16 GND_067 GND_137 N12
AM19 GND_068 GND_138 N14
AM22 GND_069 GND_139 N16
GND_070 GND_140
N16P-GX_BGA908
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 036_N16P-Q1/Q3(6/6): GND
5 4 3 2 1
5 4 3 2 1
Walter Unique
<33> FBA_D[0..63]
<33> FBA_EDC[7..0]
D D
UV4
MF=0 MF=1 MF=1 MF=0 UV6
VCC1R35VIDEO A4 FBA_D0 MF=0 MF=1 MF=1 MF=0

FBA_EDC0 C2 DQ24 DQ0 A2 FBA_D1
@ R9883 1 2 0_0402_5% FBA_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D2 With Y51 Same A4 FBA_D32
FBA_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D3 BYTE0 VCC1R35VIDEO FBA_EDC4 C2 DQ24 DQ0 A2 FBA_D33 With Y51 Same
FBA_EDC3 R2 EDC2 EDC1 DQ27 DQ3 E4 FBA_D4 @ R9884 1 2 0_0402_5% FBA_EDC5 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D34
EDC3 EDC0 DQ28 DQ4 E2 FBA_D5 FBA_EDC6 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D35
DQ29 DQ5 EDC2 EDC1 DQ27 DQ3 BYTE4
1
F4 FBA_D6 FBA_EDC7 R2 E4 FBA_D36

R10011 FBA_DBI0# D2 DQ30 DQ6 F2 FBA_D7 EDC3 EDC0 DQ28 DQ4 E2 FBA_D37
<33> FBA_DBI0# FBA_DBI1# DBI0# DBI3# DQ31 DQ7 FBA_D8 DQ29 DQ5 FBA_D38
10K_0402_1% D13 A11 F4
<33> FBA_DBI1# FBA_DBI2# DBI1# DBI2# DQ16 DQ8 FBA_D9 FBA_DBI4# DQ30 DQ6 FBA_D39
P13 A13 D2 F2
<33> FBA_DBI2# DBI2# DBI1# DQ17 DQ9 <33> FBA_DBI4# DBI0# DBI3# DQ31 DQ7
1
FBA_DBI3# P2 B11 FBA_D10 FBA_DBI5# D13 A11 FBA_D40
<33> FBA_DBI3# <33> FBA_DBI5#
2
DBI3# DBI0# DQ18 DQ10 B13 FBA_D11 R10012 FBA_DBI6# P13 DBI1# DBI2# DQ16 DQ8 A13 FBA_D41
FBA_CLK0 DQ19 DQ11 FBA_D12
BYTE1 <33> FBA_DBI6# FBA_DBI7# DBI2# DBI1# DQ17 DQ9 FBA_D42
J12 E11 10K_0402_1% P2 B11
With Y51 Same <33>
<33>
FBA_CLK0
FBA_CLK0#
FBA_CLK0# J11 CK DQ20 DQ12 E13 FBA_D13 <33> FBA_DBI7# DBI3# DBI0# DQ18 DQ10 B13 FBA_D43 BYTE5
FBA_CKE_L J3 CK# DQ21 DQ13 F11 FBA_D14 FBA_CLK1 J12 DQ19 DQ11 E11 FBA_D44
<33> FBA_CKE_L With Y51 Same <33> FBA_CLK1
2
CKE# DQ22 DQ14 F13 FBA_D15 FBA_CLK1# J11 CK DQ20 DQ12 E13 FBA_D45
DQ23 DQ15 FBA_D16 <33> FBA_CKE_H FBA_CLK1# CK# DQ21 DQ13 FBA_D46
U11 J3 F11
FBA_BA0_L DQ8 DQ16 FBA_D17 <33> FBA_CKE_H CKE# DQ22 DQ14 FBA_D47
H11 U13 F13
<33>
<33>
FBA_BA0_L
FBA_BA1_L
FBA_BA1_L K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBA_D18 With Y51 Same DQ23 DQ15 U11 FBA_D48
FBA_BA2_L K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBA_D19 FBA_BA0_H H11 DQ8 DQ16 U13 FBA_D49
<33> FBA_BA2_L FBA_BA3_L BA2/A4 BA0/A2 DQ11 DQ19 FBA_D20
BYTE2 <33> FBA_BA0_H FBA_BA1_H BA0/A2 BA2/A4 DQ9 DQ17 FBA_D50 With Y51 Same
H10 N11 K10 T11
<33> FBA_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 FBA_D21 <33> FBA_BA1_H FBA_BA2_H BA1/A5 BA3/A3 DQ10 DQ18 FBA_D51
N13 K11 T13
DQ13 DQ21 FBA_D22 <33> FBA_BA2_H FBA_BA3_H BA2/A4 BA0/A2 DQ11 DQ19 FBA_D52
M11 H10 N11 BYTE6
FBA_MA8_L DQ14 DQ22 FBA_D23 <33> FBA_BA3_H BA3/A3 BA1/A5 DQ12 DQ20 FBA_D53
K4 M13 N13
<33> FBA_MA8_L FBA_MA9_L A8/A7 A10/A0 DQ15 DQ23 FBA_D24 DQ13 DQ21 FBA_D54
H5 U4 M11
<33> FBA_MA9_L FBA_MA10_L A9/A1 A11/A6 DQ0 DQ24 FBA_D25 FBA_MA8_H DQ14 DQ22 FBA_D55
H4 U2 K4 M13
<33> FBA_MA10_L FBA_MA11_L A10/A0 A8/A7 DQ1 DQ25 FBA_D26 <33> FBA_MA8_H FBA_MA9_H A8/A7 A10/A0 DQ15 DQ23 FBA_D56
K5 T4 H5 U4
<33> FBA_MA11_L FBA_RFU_L A11/A6 A9/A1 DQ2 DQ26 FBA_D27 <33> FBA_MA9_H FBA_MA10_H A9/A1 A11/A6 DQ0 DQ24 FBA_D57
J5 T2 H4 U2
<33> FBA_RFU_L A12/RFU/NC DQ3 DQ27 FBA_D28 <33> FBA_MA10_H FBA_MA11_H A10/A0 A8/A7 DQ1 DQ25 FBA_D58
N4 BYTE3 K5 T4
DQ4 DQ28 FBA_D29 <33> FBA_MA11_H FBA_RFU_H A11/A6 A9/A1 DQ2 DQ26 FBA_D59
A5 N2 J5 T2
VPP/NC1 DQ5 DQ29 FBA_D30 <33> FBA_RFU_H A12/RFU/NC DQ3 DQ27 FBA_D60
U5 M4 N4 BYTE7
VPP/NC2 DQ6 DQ30 M2 FBA_D31 A5 DQ4 DQ28 N2 FBA_D61
DQ7 DQ31 U5 VPP/NC1 DQ5 DQ29 M4 FBA_D62
RV115 2 1 1K_0402_1% J1 VCC1R35VIDEO VPP/NC2 DQ6 DQ30 M2 FBA_D63
RV117 2 1 1K_0402_1% J10 MF DQ7 DQ31
RV119 2 1 121_0402_1% J13 SEN B1 RV220 2 1 1K_0402_1% J1 VCC1R35VIDEO
ZQ VDDQ1 D1 RV222 2 1 1K_0402_1% J10 MF
VDDQ2 F1 RV221 2 1 121_0402_1% J13 SEN B1
FBA_ABI#_L J4 VDDQ3 M1 ZQ VDDQ1 D1
<33> FBA_ABI#_L FBA_RAS#_L ABI# VDDQ4 VDDQ2
G3 P1 F1
<33> FBA_RAS#_L FBA_CS#_L RAS# CAS# VDDQ5 FBA_ABI#_H VDDQ3
G12 T1 J4 M1
<33> FBA_CS#_L FBA_CAS#_L CS# WE# VDDQ6 <33> FBA_ABI#_H FBA_RAS#_H ABI# VDDQ4
L3 G2 G3 P1
<33> FBA_CAS#_L FBA_WE#_L CAS# RAS# VDDQ7 <33> FBA_RAS#_H FBA_CS#_H RAS# CAS# VDDQ5
L12 L2 G12 T1
<33> FBA_WE#_L WE# CS# VDDQ8 <33> FBA_CS#_H FBA_CAS#_H CS# WE# VDDQ6
B3 L3 G2
C VDDQ9 <33> FBA_CAS#_H FBA_WE#_H CAS# RAS# VDDQ7 C
D3 L12 L2
VDDQ10 <33> FBA_WE#_H WE# CS# VDDQ8
F3 B3
FBA_WCK0_N D5 VDDQ11 H3 VDDQ9 D3
<33> FBA_WCK0_N FBA_WCK0 WCK01# WCK23# VDDQ12 VDDQ10
D4 K3 F3
<33> FBA_WCK0 WCK01 WCK23 VDDQ13 FBA_WCK2_N VDDQ11
M3 D5 H3
FBA_WCK1_N VDDQ14 <33> FBA_WCK2_N FBA_WCK2 WCK01# WCK23# VDDQ12
P5 P3 D4 K3
<33> FBA_WCK1_N FBA_WCK1 WCK23# WCK01# VDDQ15 <33> FBA_WCK2 WCK01 WCK23 VDDQ13
P4 T3 M3
<33> FBA_WCK1 WCK23 WCK01 VDDQ16 FBA_WCK3_N VDDQ14
E5 P5 P3
VDDQ17 <33> FBA_WCK3_N FBA_WCK3 WCK23# WCK01# VDDQ15
N5 P4 T3
+FBA_VREFD_L VDDQ18 <33> FBA_WCK3 WCK23 WCK01 VDDQ16
A10 E10 E5
U10 VREFD1 VDDQ19 N10 VDDQ17 N5
+FBA_VREFC0 J14 VREFD2 VDDQ20 B12 +FBA_VREFD_H A10 VDDQ18 E10
VREFC VDDQ21 D12 U10 VREFD1 VDDQ19 N10
VDDQ22 F12 +FBA_VREFC1 J14 VREFD2 VDDQ20 B12
VDDQ23 H12 VREFC VDDQ21 D12
FBA_RST#_L J2 VDDQ24 K12 VDDQ22 F12
<33> FBA_RST#_L RESET# VDDQ25 VDDQ23
M12 H12
VDDQ26 P12 FBA_RST#_H J2 VDDQ24 K12
VDDQ27 <33> FBA_RST#_H RESET# VDDQ25
1
T12 M12
R9667 VDDQ28 G13 VDDQ26 P12
VDDQ29 VDDQ27
1
10K_0402_1% H1 L13 T12
K1 VSS1 VDDQ30 B14 R9666 VDDQ28 G13
B5 VSS2 VDDQ31 D14 10K_0402_1% H1 VDDQ29 L13
2
G5 VSS3 VDDQ32 F14 K1 VSS1 VDDQ30 B14

L5 VSS4 VDDQ33 M14 B5 VSS2 VDDQ31 D14
2
T5 VSS5 VDDQ34 P14 G5 VSS3 VDDQ32 F14
B10 VSS6 VDDQ35 T14 L5 VSS4 VDDQ33 M14
D10 VSS7 VDDQ36 T5 VSS5 VDDQ34 P14
G10 VSS8 B10 VSS6 VDDQ35 T14
L10 VSS9 A1 D10 VSS7 VDDQ36
P10 VSS10 VSSQ1 C1 G10 VSS8
T10 VSS11 VSSQ2 E1 L10 VSS9 A1
H14 VSS12 VSSQ3 N1 P10 VSS10 VSSQ1 C1
K14 VSS13 VSSQ4 R1 T10 VSS11 VSSQ2 E1
VCC1R35VIDEO VSS14 VSSQ5 U1 H14 VSS12 VSSQ3 N1
VSSQ6 H2 K14 VSS13 VSSQ4 R1
G1 VSSQ7 K2 VCC1R35VIDEO VSS14 VSSQ5 U1
L1 VDD1 VSSQ8 A3 VSSQ6 H2
G4 VDD2 VSSQ9 C3 G1 VSSQ7 K2
L4 VDD3 VSSQ10 E3 L1 VDD1 VSSQ8 A3
C5 VDD4 VSSQ11 N3 G4 VDD2 VSSQ9 C3
R5 VDD5 VSSQ12 R3 L4 VDD3 VSSQ10 E3
C10 VDD6 VSSQ13 U3 C5 VDD4 VSSQ11 N3
R10 VDD7 VSSQ14 C4 VCC1R35VIDEO R5 VDD5 VSSQ12 R3
D11 VDD8 VSSQ15 R4 C10 VDD6 VSSQ13 U3
G11 VDD9 VSSQ16 F5 R10 VDD7 VSSQ14 C4
VDD10 VSSQ17 VDD8 VSSQ15
1U_0603_25V7-K
1U_0603_25V7-K
1U_0603_25V7-K
1U_0603_25V7-K
10U_0603_6.3V6-M
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
L11 M5 D11 R4
CV189
CV185
CV186
CV191
CV184
CV190
CV188
CV187
P11 F10 2 1 1 1 1 1 1 1 G11 F5
G14 VDD12 VSSQ19 M10 L11 VDD10 VSSQ17 M5
L14 VDD13 VSSQ20 C11 P11 VDD11 VSSQ18 F10
B VDD14 VSSQ21 R11 G14 VDD12 VSSQ19 M10 B
VSSQ22 A12 1 2 2 2 2 2 2 2 L14 VDD13 VSSQ20 C11
VCC1R35VIDEO VSSQ23 C12 VDD14 VSSQ21 R11
VSSQ24 E12 VSSQ22 A12
VSSQ25 N12 VSSQ23 C12
VSSQ26 VSSQ24
1U_0603_25V7-K
1U_0603_25V7-K
1U_0603_25V7-K
1U_0603_25V7-K
10U_0603_6.3V6-M
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
R12 E12
VSSQ27 VSSQ25
CV166
CV68
CV69
CV77
CV78
CV129
CV132
CV133
2 1 1 1 1 1 1 1 170-BALL U12 N12

VSSQ28 H13 VSSQ26 R12
SGRAM GDDR5 VSSQ29 K13 170-BALL VSSQ27 U12
VSSQ30 A14 VSSQ28 H13
1 2 2 2 2 2 2 2 VSSQ31 VSSQ29
10U_0603_6.3V6-M
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
C14 SGRAM GDDR5 K13
VSSQ32 VSSQ30
CV302
CV303
CV304
CV305
CV308
CV306
CV307
CV309
E14 2 1 1 1 1 1 1 1 A14
VSSQ34 R14 VSSQ32 E14
VSSQ35 U14 VSSQ33 N14
VSSQ36 1 2 2 2 2 2 2 2 VSSQ34 R14
X76@ VSSQ35 U14
VSSQ36
H5GQ1H24AFR-T2L_BGA170 X76@
10U_0603_6.3V6-M
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
CV294
CV296
CV295
CV297
CV299
CV298
CV300
CV301
H5GQ1H24AFR-T2L_BGA170
2 1 1 1 1 1 1 1 12/17 Add Cap counts
1 2 2 2 2 2 2 2
VCC1R35VIDEO VCC1R35VIDEO
1
1
RV127 RV143
549_0402_1% 549_0402_1%
FBA_CLK0 RV212 16 mil RV214 16 mil

1 2
2
2
RV21 40.2_0402_1% 1 2 +FBA_VREFC0 1 2 +FBA_VREFC1
820P_0402_50V7-K
820P_0402_50V7-K
931_0402_1% 931_0402_1%
2
1
CV42
CV59
12/17 Add Cap counts RV123 @ RV128
1
RV144
1
160_0402_1% 1.33K_0402_1% 1.33K_0402_1% FBA_CLK1 1 2

RV31 40.2_0402_1%
2 2
1
2
FBA_CLK0# 1 2
RV28 40.2_0402_1% RV216 @
160_0402_1%
0.01U_0402_25V7-K
CV155
1
FBA_CLK1# 1 2
RV36 40.2_0402_1%
VCC1R35VIDEO
2 VCC1R35VIDEO
CV175
0.01U_0402_25V7-K
A A
1
1
1
RV129
549_0402_1% RV145
549_0402_1% 2
RV213
RV215
2
1 2 +FBA_VREFD_L
2
820P_0402_50V7-K
931_0402_1% 1 2 +FBA_VREFD_H
1
820P_0402_50V7-K
CV58
1 931_0402_1%
CV60
RV130 1
1
D
1.33K_0402_1% RV146
1
D
2 1.33K_0402_1%
Note: need to decide 4VRAM <34,38> MEM_VREF G 2 MEM_VREF 2

2
S QV9 G 2
3
2
2N7002W-T/R7_SOT323-3 S QV11
3
2N7002W-T/R7_SOT323-3
or 8VRAM before SDV design. Security Classification

Issued Date 2015/07/16
LC Future Center Secret Data
Deciphered Date 2016/01/16
Title
VRAM CH_A
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Walter Unique <33> FBB_D[0..63]
<33> FBB_EDC[7..0]
UV8
MF=0 MF=1 MF=1 MF=0 UV10
A4 FBB_D0 MF=0 MF=1 MF=1 MF=0

VCC1R35VIDEO @ FBB_EDC0 C2 DQ24 DQ0 A2 FBB_D1 With Y51 Same With Y51 Same
R9885 1 2 0_0402_5% FBB_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBB_D2 A4 FBB_D32
FBB_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBB_D3 BYTE0 VCC1R35VIDEO @ FBB_EDC4 C2 DQ24 DQ0 A2 FBB_D33 With Y51 Same
D FBB_EDC3 R2 EDC2 EDC1 DQ27 DQ3 E4 FBB_D4 R9886 1 2 0_0402_5% FBB_EDC5 C13 EDC0 EDC3 DQ25 DQ1 B4 FBB_D34 D
EDC3 EDC0 DQ28 DQ4 E2 FBB_D5 FBB_EDC6 R13 EDC1 EDC2 DQ26 DQ2 B2 FBB_D35
DQ29 DQ5 FBB_D6 FBB_EDC7 EDC2 EDC1 DQ27 DQ3 FBB_D36
BYTE4
F4 R2 E4
FBB_DBI0# D2 DQ30 DQ6 F2 FBB_D7 EDC3 EDC0 DQ28 DQ4 E2 FBB_D37
<33> FBB_DBI0# DBI0# DBI3# DQ31 DQ7 DQ29 DQ5
1
FBB_DBI1# D13 A11 FBB_D8 F4 FBB_D38
<33> FBB_DBI1# FBB_DBI2# DBI1# DBI2# DQ16 DQ8 FBB_D9 FBB_DBI4# DQ30 DQ6 FBB_D39
R10013 P13 A13 D2 F2
<33> FBB_DBI2# DBI2# DBI1# DQ17 DQ9 <33> FBB_DBI4# DBI0# DBI3# DQ31 DQ7
1
10K_0402_1% FBB_DBI3# P2 B11 FBB_D10 FBB_DBI5# D13 A11 FBB_D40
<33> FBB_DBI3# DBI3# DBI0# DQ18 DQ10 FBB_D11 <33> FBB_DBI5# FBB_DBI6# DBI1# DBI2# DQ16 DQ8 FBB_D41
B13 BYTE1 R10014 P13 A13
FBB_CLK0 DQ19 DQ11 FBB_D12 <33> FBB_DBI6# FBB_DBI7# DBI2# DBI1# DQ17 DQ9 FBB_D42
J12 E11 10K_0402_1% P2 B11
With Y51 Same <33> FBB_CLK0 <33> FBB_DBI7#
2
FBB_CLK0# J11 CK DQ20 DQ12 E13 FBB_D13 DBI3# DBI0# DQ18 DQ10 B13 FBB_D43
FBB_CKE_L <33> FBB_CLK0# CK# DQ21 DQ13 FBB_D14 FBB_CLK1 DQ19 DQ11 FBB_D44
J3 F11 J12 E11 BYTE5
<33> FBB_CKE_L <33> FBB_CLK1
2
CKE# DQ22 DQ14 F13 FBB_D15 FBB_CLK1# J11 CK DQ20 DQ12 E13 FBB_D45
DQ23 DQ15 FBB_D16 FBB_CKE_H <33> FBB_CLK1# CK# DQ21 DQ13 FBB_D46
U11 J3 F11
<33> FBB_BA0_L
FBB_BA0_L H11 DQ8 DQ16 U13 FBB_D17 With Y51 Same <33> FBB_CKE_H CKE# DQ22 DQ14 F13 FBB_D47
FBB_BA1_L K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBB_D18 DQ23 DQ15 U11 FBB_D48
<33>
<33>
FBB_BA1_L
FBB_BA2_L
FBB_BA2_L K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBB_D19 BYTE2 <33> FBB_BA0_H
FBB_BA0_H H11 DQ8 DQ16 U13 FBB_D49 With Y51 Same
FBB_BA3_L H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 FBB_D20 FBB_BA1_H K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBB_D50
<33> FBB_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 FBB_D21 <33> FBB_BA1_H FBB_BA2_H BA1/A5 BA3/A3 DQ10 DQ18 FBB_D51
N13 K11 T13
DQ13 DQ21 FBB_D22 <33> FBB_BA2_H FBB_BA3_H BA2/A4 BA0/A2 DQ11 DQ19 FBB_D52
M11 H10 N11 BYTE6
FBB_MA8_L DQ14 DQ22 FBB_D23 <33> FBB_BA3_H BA3/A3 BA1/A5 DQ12 DQ20 FBB_D53
K4 M13 N13
<33> FBB_MA8_L FBB_MA9_L A8/A7 A10/A0 DQ15 DQ23 FBB_D24 DQ13 DQ21 FBB_D54
H5 U4 M11
<33> FBB_MA9_L FBB_MA10_L A9/A1 A11/A6 DQ0 DQ24 FBB_D25 FBB_MA8_H DQ14 DQ22 FBB_D55
H4 U2 K4 M13
<33> FBB_MA10_L FBB_MA11_L A10/A0 A8/A7 DQ1 DQ25 FBB_D26 <33> FBB_MA8_H FBB_MA9_H A8/A7 A10/A0 DQ15 DQ23 FBB_D56
K5 T4 H5 U4
<33> FBB_MA11_L FBB_RFU_L A11/A6 A9/A1 DQ2 DQ26 FBB_D27 <33> FBB_MA9_H FBB_MA10_H A9/A1 A11/A6 DQ0 DQ24 FBB_D57
J5 T2 H4 U2
<33> FBB_RFU_L A12/RFU/NC DQ3 DQ27 FBB_D28 <33> FBB_MA10_H FBB_MA11_H A10/A0 A8/A7 DQ1 DQ25 FBB_D58
N4 BYTE3 K5 T4
DQ4 DQ28 FBB_D29 <33> FBB_MA11_H FBB_RFU_H A11/A6 A9/A1 DQ2 DQ26 FBB_D59
A5 N2 J5 T2
VPP/NC1 DQ5 DQ29 FBB_D30 <33> FBB_RFU_H A12/RFU/NC DQ3 DQ27 FBB_D60
U5 M4 N4 BYTE7
VPP/NC2 DQ6 DQ30 M2 FBB_D31 A5 DQ4 DQ28 N2 FBB_D61
DQ7 DQ31 U5 VPP/NC1 DQ5 DQ29 M4 FBB_D62
RV226 2 N16P@ 1 1K_0402_1% J1 VCC1R35VIDEO VPP/NC2 DQ6 DQ30 M2 FBB_D63
RV228 2 N16P@ 1 1K_0402_1% J10 MF DQ7 DQ31
RV227 2 N16P@ 1 121_0402_1% J13 SEN B1 RV240 2 N16P@ 1 1K_0402_1% J1 VCC1R35VIDEO
ZQ VDDQ1 D1 RV242 2 N16P@ 1 1K_0402_1% J10 MF
VDDQ2 F1 RV241 2 N16P@ 1 121_0402_1% J13 SEN B1
FBB_ABI#_L J4 VDDQ3 M1 ZQ VDDQ1 D1
<33> FBB_ABI#_L FBB_RAS#_L ABI# VDDQ4 VDDQ2
G3 P1 F1
<33> FBB_RAS#_L FBB_CS#_L RAS# CAS# VDDQ5 FBB_ABI#_H VDDQ3
G12 T1 J4 M1
<33> FBB_CS#_L FBB_CAS#_L CS# WE# VDDQ6 <33> FBB_ABI#_H FBB_RAS#_H ABI# VDDQ4
L3 G2 G3 P1
<33> FBB_CAS#_L FBB_WE#_L CAS# RAS# VDDQ7 <33> FBB_RAS#_H FBB_CS#_H RAS# CAS# VDDQ5
L12 L2 G12 T1
<33> FBB_WE#_L WE# CS# VDDQ8 <33> FBB_CS#_H FBB_CAS#_H CS# WE# VDDQ6
B3 L3 G2
VDDQ9 <33> FBB_CAS#_H FBB_WE#_H CAS# RAS# VDDQ7
D3 L12 L2
VDDQ10 <33> FBB_WE#_H WE# CS# VDDQ8
F3 B3
FBB_WCK0_N D5 VDDQ11 H3 VDDQ9 D3
<33> FBB_WCK0_N FBB_WCK0 WCK01# WCK23# VDDQ12 VDDQ10
D4 K3 F3
<33> FBB_WCK0 WCK01 WCK23 VDDQ13 FBB_WCK2_N VDDQ11
M3 D5 H3
FBB_WCK1_N VDDQ14 <33> FBB_WCK2_N FBB_WCK2 WCK01# WCK23# VDDQ12
P5 P3 D4 K3
<33> FBB_WCK1_N FBB_WCK1 WCK23# WCK01# VDDQ15 <33> FBB_WCK2 WCK01 WCK23 VDDQ13
P4 T3 M3
<33> FBB_WCK1 WCK23 WCK01 VDDQ16 FBB_WCK3_N VDDQ14
E5 P5 P3
VDDQ17 <33> FBB_WCK3_N FBB_WCK3 WCK23# WCK01# VDDQ15
N5 P4 T3
+FBB_VREFD_L VDDQ18 <33> FBB_WCK3 WCK23 WCK01 VDDQ16
C A10 E10 E5 C
U10 VREFD1 VDDQ19 N10 VDDQ17 N5
+FBB_VREFC0 J14 VREFD2 VDDQ20 B12 +FBB_VREFD_H A10 VDDQ18 E10
VREFC VDDQ21 D12 U10 VREFD1 VDDQ19 N10
VDDQ22 F12 +FBB_VREFC1 J14 VREFD2 VDDQ20 B12
VDDQ23 H12 VREFC VDDQ21 D12
FBB_RST#_L J2 VDDQ24 K12 VDDQ22 F12
<33> FBB_RST#_L RESET# VDDQ25 VDDQ23
M12 H12
VDDQ26 P12 FBB_RST#_H J2 VDDQ24 K12
VDDQ27 <33> FBB_RST#_H RESET# VDDQ25
1
N16P@ T12 M12

R9665 VDDQ28 G13 VDDQ26 P12
VDDQ29 VDDQ27
1
10K_0402_1% H1 L13 N16P@ T12
K1 VSS1 VDDQ30 B14 R10010 VDDQ28 G13
B5 VSS2 VDDQ31 D14 10K_0402_1% H1 VDDQ29 L13
2
G5 VSS3 VDDQ32 F14 K1 VSS1 VDDQ30 B14

L5 VSS4 VDDQ33 M14 B5 VSS2 VDDQ31 D14
2
T5 VSS5 VDDQ34 P14 G5 VSS3 VDDQ32 F14
B10 VSS6 VDDQ35 T14 L5 VSS4 VDDQ33 M14
D10 VSS7 VDDQ36 T5 VSS5 VDDQ34 P14
G10 VSS8 B10 VSS6 VDDQ35 T14
L10 VSS9 A1 D10 VSS7 VDDQ36
P10 VSS10 VSSQ1 C1 G10 VSS8
T10 VSS11 VSSQ2 E1 L10 VSS9 A1
H14 VSS12 VSSQ3 N1 P10 VSS10 VSSQ1 C1
K14 VSS13 VSSQ4 R1 T10 VSS11 VSSQ2 E1
VCC1R35VIDEO VSS14 VSSQ5 U1 H14 VSS12 VSSQ3 N1
VSSQ6 H2 K14 VSS13 VSSQ4 R1
G1 VSSQ7 K2 VCC1R35VIDEO VSS14 VSSQ5 U1
L1 VDD1 VSSQ8 A3 VSSQ6 H2
G4 VDD2 VSSQ9 C3 G1 VSSQ7 K2
L4 VDD3 VSSQ10 E3 L1 VDD1 VSSQ8 A3
VCC1R35VIDEO C5 VDD4 VSSQ11 N3 G4 VDD2 VSSQ9 C3
R5 VDD5 VSSQ12 R3 L4 VDD3 VSSQ10 E3
C10 VDD6 VSSQ13 U3 C5 VDD4 VSSQ11 N3
1U_0603_25V7-K
1U_0603_25V7-K
1U_0603_25V7-K
1U_0603_25V7-K
10U_0603_6.3V6-M
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
R10 C4 R5 R3
N16P@ CV218
N16P@ CV201
N16P@ CV202
N16P@ CV225
N16P@ CV200
N16P@ CV219
N16P@ CV217
N16P@ CV216
2 1 1 1 1 1 1 1 D11 R4 C10 U3
G11 VDD9 VSSQ16 F5 VCC1R35VIDEO R10 VDD7 VSSQ14 C4
L11 VDD10 VSSQ17 M5 D11 VDD8 VSSQ15 R4
P11 VDD11 VSSQ18 F10 G11 VDD9 VSSQ16 F5
1 2 2 2 2 2 2 2 VDD12 VSSQ19 VDD10 VSSQ17
1U_0603_25V7-K
1U_0603_25V7-K
1U_0603_25V7-K
1U_0603_25V7-K
10U_0603_6.3V6-M
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
G14 M10 L11 M5
N16P@ CV208
N16P@ CV203
N16P@ CV205
N16P@ CV210
N16P@ CV204
N16P@ CV209
N16P@ CV207
N16P@ CV206
L14 C11 2 1 1 1 1 1 1 1 P11 F10
VDD14 VSSQ21 R11 G14 VDD12 VSSQ19 M10
VSSQ22 A12 L14 VDD13 VSSQ20 C11
VSSQ23 C12 VDD14 VSSQ21 R11
VSSQ24 E12 1 2 2 2 2 2 2 2 VSSQ22 A12
VSSQ26 R12 VSSQ24 E12
170-BALL VSSQ27 U12 VSSQ25 N12
VSSQ28 VSSQ26
10U_0603_6.3V6-M
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
H13 R12
VSSQ29 VSSQ27
CV310
CV311
CV312
CV313
CV316
CV314
CV315
CV317
2 1 1 1 1 1 1 1 SGRAM GDDR5 K13 170-BALL U12

B VSSQ30 A14 VSSQ28 H13 B
VSSQ31 C14 SGRAM GDDR5 VSSQ29 K13
VSSQ32 E14 VSSQ30 A14
1 2 2 2 2 2 2 2 VSSQ33 VSSQ31
10U_0603_6.3V6-M
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
N14 C14
VSSQ34 VSSQ32
CV318
CV319
CV320
CV321
CV324
CV322
CV323
CV325
R14 2 1 1 1 1 1 1 1 E14
VSSQ35 U14 VSSQ33 N14
VSSQ36 VSSQ34 R14
X76@ VSSQ35 U14
1 2 2 2 2 2 2 2 VSSQ36
H5GQ1H24AFR-T2L_BGA170 X76@
H5GQ1H24AFR-T2L_BGA170
12/17 Add Cap counts VCC1R35VIDEO

VCC1R35VIDEO
1
N16P@ N16P@
RV253
12/17 Add Cap counts RV232
N16P@ 549_0402_1% N16P@ 549_0402_1%
N16P@ 16 mil 16 mil
FBB_CLK0 RV248 RV234
1 2
2
2
RV247 40.2_0402_1% 1 2 +FBB_VREFC0 1 2 +FBB_VREFC1
820P_0402_50V7-K
820P_0402_50V7-K
931_0402_1% 931_0402_1%
2
1
N16P@ CV229
N16P@ CV212
@ N16P@ 1 N16P@ 1
RV249 RV250 RV229
160_0402_1% 1.33K_0402_1% 1.33K_0402_1% FBB_CLK1 1 N16P@ 2
RV239 40.2_0402_1%
2 2
1
2
FBB_CLK0# 1 N16P@ 2 @
RV246 40.2_0402_1% RV255
160_0402_1%
0.01U_0402_25V7-K
N16P@ CV227
1
FBB_CLK1# 1 N16P@ 2
RV238 40.2_0402_1%
VCC1R35VIDEO
2 VCC1R35VIDEO
N16P@ CV226
0.01U_0402_25V7-K
1
1
N16P@
1
RV254 N16P@
N16P@ 549_0402_1% RV233
N16P@ 549_0402_1% 2
RV252
RV230
2
1 2 +FBB_VREFD_L
2
820P_0402_50V7-K
931_0402_1% 1 2 +FBB_VREFD_H
1
820P_0402_50V7-K
N16P@ CV228
A N16P@ 1 931_0402_1% A
N16P@ CV211
RV251 N16P@ 1
1
D
1.33K_0402_1% RV231
1
D
2 1.33K_0402_1%
<34,37> MEM_VREF G 2 MEM_VREF 2
2
S QV13 N16P@ G 2
3
2
2N7002W-T/R7_SOT323-3 S QV12 N16P@
Note: need to decide 4VRAM
3
2N7002W-T/R7_SOT323-3
or 8VRAM before SDV design.

Issued Date 2015/07/16 Deciphered Date 2016/01/16 VRAM CH_B
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Walter Unique
VCC1R35VIDEO
D
For UV4/UV6 VCC1R35VIDEO
For UV8/UV10
D
VCC1R35VIDEO Decaps:
1x 0805 10uF
6x 0402 0.1uF
1U_0402_10V7K
1U_0402_10V7K
1U_0402_10V7K
1U_0402_10V7K
1U_0402_10V7K
1U_0402_10V7K
1U_0402_10V7K
1U_0402_10V7K
1U_0402_10V7K
1U_0402_10V7K
1U_0402_10V7K
1U_0402_10V7K
1U_0402_10V7K
1U_0402_10V7K
1U_0402_10V7K
1U_0402_10V7K
4x 0603 1.0uF
0.1U_0402_10V6-K
0.1U_0402_10V6-K
0.1U_0402_10V6-K
0.1U_0402_10V6-K
2 2 2 2 2 2 2 2 2 2 2 2
0.1U_0402_16V7-K
0.1U_0402_16V7-K
0.1U_0402_16V7-K
0.1U_0402_16V7-K
C6174
C6175
C6176
C6177
C6178
C6179
C6180
C6181
2 2 2 2 2 2 2 2 2 2 2 2
C6183
C6184
C6185
C6186
C6189
C6190
C6191
C6192
C6193
C6194
C6195
C6196
C6198
C6199
C6200
C6201
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
CLOSE TO THE MEMORY CLOSE TO THE MEMORY

C C
VCC1R35VIDEO VCC1R35VIDEO VCC1R35VIDEO

10U_0805_10V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
0.1U_0402_16V7-K
0.1U_0402_16V7-K
0.1U_0402_16V7-K
0.1U_0402_16V7-K
0.1U_0402_16V7-K
0.1U_0402_16V7-K
1 1 1 1 1
C9167
C9166
C9165
C9164
C9163
1 1 1 1 1 1
C9155
C9156
C9157
C9158
C9159
C9160
2 2 2 2 2
2 2 2 2 2 2
VCC1R35VIDEO Decaps:
Spare Capacitors(DNI) 1x 0805 10uF
(Nvidia use only)
4x 0603 1.0uF
B B
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 BLANK
Custom 0.1
5 4 3 2 1
5 4 3 2 1
EMI VCC3M
PWR-PWRSWITCH
BUTTON3 D84
Payton Common 4 -LEDPWR
1
2 5 R9950
180_0402_1%
2
1 6
AOZ8904CIL_SOT23-6 JPBTN1
EMC@
D 1 D
2 1
<74,83,84> -PWRSWITCH 2
<75> -LEDPWR R9786 2 1 220_0402_5% 3 5
4 3 GND1 6
4 GND2
HIGHS_WS32041-S0471-HF
@
VCC3B VCC3SW VCC3B VCC3M

COLOR SENSOR
VCC5B
@
D44
USBP13-_COLOR_SENSOR 3 4 USBP13+_COLOR_SENSOR
2
100K_0402_5%
100K_0402_5%
1
2
F4 F5
1
2 5
R829
R157
0.5A_32V_ERBRD0R50X
0.5A_32V_ERBRD0R50X
F2
0.5A_32V_ERBRD0R50X
1
C 1 6 C
2
AOZ8904CIL_SOT23-6 JCS1 @
1
2 1
<15> USBP13-_COLOR_SENSOR 2
JCAM1 3
<15> USBP13+_COLOR_SENSOR 3
VCC3M_F_LOGO_LED 1 4
2 1 5 4
3 2 6 5
INDICATOR LED 4 3 7 6
<16> -SATALED_CONN 4 7
5 8
6 5 9 8
VCC3B_F_TOUCH_PANEL 7 6 10 9 11
-LID_CLOSE D46 1 2 -TOUCH_STOP 8 7 10 GND1 12
RB521CM_30 9 8 GND2
TOUCH PANEL 10 9 DRAPH_BT5P0101-1001H
<15> USBP10-_TOUCH 10
11
<15> USBP10+_TOUCH 11
12
<42> PANEL_HSYNC_OUT 12
13
14 13
MIC_DATA 15 14
<67> MIC_DATA 15
MIC_CLK 16
<67> MIC_CLK 16
-INT_MIC_DTCT 17
2D CAM/MIC/(LID) <19> -INT_MIC_DTCT 17
18
USBP8+_CAMERA_R 19 18
USBP8-_CAMERA_R 20 19
21 20
22 21
23 22
-LID_CLOSE 24 23
<76> -LID_CLOSE 24
VCC3SW 25
B LOGO LED/LID -LEDLOGO 26 25 B
<75> -LEDLOGO 26
R784 2 1 27
28 27
2.49K_0402_1% 29 28
30 29 41
31 30 GND1 42
32 31 GND2 43
33 32 GND3 44
For EMC
34 33 GND4 45
34 GND5 AOZ8904CIL_SOT23-6
35 46
36 35 GND6 47 -LID_CLOSE 3 4
37 36 GND7 48
38 37 GND8 49
39 38 GND9 50
40 39 GND10 51 2 5
40 GND11
I-PEX_20439-040E-01
@
-LEDLOGO 1 6
D78 EMI
EMC@ -LID_CLOSE
<15> USBP8+_CAMERA USBP8+_CAMERA R680 1 2 0_0402_5% USBP8+_CAMERA_R

L1 @ For EMC
1 2 @ 2
1 2 C574 1 2 10P_0402_50V8-J R644 1 @ 2 MIC_CLK C255
EXC24CH900U_4P 2200P_0402_50V7-K
4 3 33_0402_5%
4 3 1
EMC@
<15> USBP8-_CAMERA USBP8-_CAMERA R681 1 2 0_0402_5% USBP8-_CAMERA_R
A A
EMC@

Issued Date 2015/07/16 Deciphered Date 2016/01/16 CAMERA/TOUCH/PWR BUTTON
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Place Near Pin5, 8 and 13
Payton Common VCC3B

Place Near 18, 20
Place Near 30, 40 and 42
1U_0402_6.3V6-K
.1U_0402_16V4-Z
.1U_0402_16V4-Z
.1U_0402_16V4-Z
C256
C257
C258
C259
D D
13
18
20
30
40
42
5
8
U6
2
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
<42> EDP_TXP0 A0_P
3
<42> EDP_TXN0 A0_N
6
<42> EDP_TXP1 A1_P
7
<42> EDP_TXN1 A1_N
11
<42> EDP_TXP2 A2_P
12
<42> EDP_TXN2 A2_N
15 9 -DGFX_OUTPUT_ENABLE
<42> EDP_TXP3 A3_P SEL -DGFX_OUTPUT_ENABLE <14>
16 41
<42> EDP_TXN3 A3_N XSD01 19
38 XSD23
<32> EDP_TXP0_D B0_P
37
<32> EDP_TXN0_D B0_N
36
35
dGPU -> <32>
<32>
EDP_TXN1_D
EDP_TXP2_D
29 B1_N
28 B2_P
27
26
34
<6> EDP_TXP0_I C0_P
33
<6> EDP_TXN0_I C0_N
32
<6> EDP_TXP1_I C1_P
31
iGPU -> <6> EDP_TXN1_I C1_N
25
<6> EDP_TXP2_I C2_P
24
<6> EDP_TXN2_I C2_N
23 43
<6> EDP_TXP3_I C3_P THERMAL_PAD
22
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
<6> EDP_TXN3_I C3_N
C CBTL04083ABS_HVQFN42_3P5X9 C
1
4
10
14
17
21
39
DOCK DP Switch
Vendor Vendor PN LCFC PN
NXP CBTL04083ABS "-DGFX_OUTPUT_ENABLE" signal controls DOCK DP Bus switch
Pericom PI3PCIE3412ZHE+DAX
High : iGPU output is selected.
Low : dGPU output is selected.
SEL :(L,H) = (B -> A, C ->A)

SEL :(L,H) = (dGPU, iGPU)
Aux
S : (L,H) = (nA to nB1, nA to nB2)
= (dGPU, iGPU)
from / to dGPU VCC5B
B from / to dGPU VCC5B B

from / to iGPU U8
16
from / to iGPU U7 Vcc 4
EDP_AUXN <42>
16 2 1A 7
Vcc <32> EDP_AUXN_D 1B1 2A EDP_AUXP <42>
4 3 9
1A VGA_BLON <75> <6> EDP_AUXN_I 1B2 3A EDP_HPD <42>
2 7 5 12
<34> VGA_BLON_D 1B1 2A PANEL_POWER_ON <85> <32> EDP_AUXP_D 2B1 4A
3 9 6
<16> VGA_BLON_I 1B2 3A PANEL_BKLT_CTRL <42> <6> EDP_AUXP_I 2B2
5 12 11 15
<34> PANEL_POWER_ON_D 2B1 4A <32> EDP_HPD_D 3B1 OE
6 10 1 -DGFX_OUTPUT_ENABLE
<16> PANEL_POWER_ON_I 2B2 <18> EDP_HPD_I 3B2 S
11 15 14
<34> PANEL_BKLT_CTRL_D 3B1 OE 4B1
10 1 -DGFX_OUTPUT_ENABLE 13 8
<16> PANEL_BKLT_CTRL_I 3B2 S 4B2 GND
14 17
13 4B1 8 T-PAD
4B2 GND
100K_0402_5%
17 CBT3257ABQ_DHVQFN16_2P5X3P5
T-PAD
1
CBT3257ABQ_DHVQFN16_2P5X3P5
R158
1U_0402_6.3V6-K
1U_0402_6.3V6-K
C260
C261
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 eDP DEMUX
Custom 0.1
NM-A451
5 4 3 2 1
5 4 3 2 1
VCC3M
Payton Common Q4
VCC3P VINT20 VBL20
1 8
F6
2 7 1 2
3 6 1 3A_32V_ERBRD3R00X
1
4 5 C262
0.01U_0402_25V7K
47_0402_5% 2
D R160 D
TPCF8002_2-3U1A
2
100_0402_5%
1
R161
2
D6
2
1
VCC3P_DRV
<85> VCC3P_DRV
1
1
0.068U_0402_25V 47K_0402_5%
C263 R162
2
VCC3P
2
F7 0.9A
VCC3LCD 1 2
0.01U_0402_25V7-K
3A_32V_ERBRD3R00X
0.1U_0402_25V6-K
1U_0402_10V6K
1 1 1
C266
C264
C265
2 2 2
VBL20
C C
2A
VCC3P
1
R163 1
1
10K_0402_5%
C267 C268 C269
0.01U_0402_25V7K 0.1U_0402_25 1UF_25V_0603
LCD CONNECTOR
2
2
2
JEDP1
1
2 1
C272 1 2 0.1U_0402_25V6-K EDP_TXN3_CONN 3 2
<41> EDP_TXN3 3
C273 1 2 0.1U_0402_25V6-K EDP_TXP3_CONN 4
<41> EDP_TXP3 4
5
C270 1 2 0.1U_0402_25V6-K EDP_TXN2_CONN 6 5
<41> EDP_TXN2 6
C274 1 2 0.1U_0402_25V6-K EDP_TXP2_CONN 7
<41> EDP_TXP2 7
8
C271 1 2 0.1U_0402_25V6-K EDP_TXN1_CONN 9 8
<41> EDP_TXN1 9
C275 1 2 0.1U_0402_25V6-K EDP_TXP1_CONN 10
<41> EDP_TXP1 10
11
C276 1 2 0.1U_0402_25V6-K EDP_TXN0_CONN 12 11
<41> EDP_TXN0 12
C277 1 2 0.1U_0402_25V6-K EDP_TXP0_CONN 13
<41> EDP_TXP0 13
14
B C278 1 2 0.1U_0402_25V6-K EDP_AUXP_CONN 15 14 B
<41> EDP_AUXP 15
C279 1 2 0.1U_0402_25V6-K EDP_AUXN_CONN 16
<41> EDP_AUXN 16
17
18 17
19 18
20 19
21 20
22 21
23 22
24 23
25 24
26 25
27 26
28 27
<41> EDP_HPD 28
29
30 29 41
31 30 GND1 42
Test_Point_40MIL TP56 1 32 31 GND2 43
BACKLIGHT_ON 33 32 GND3 44
<75> BACKLIGHT_ON 33 GND4
PANEL_BKLT_CTRL 34
<41> PANEL_BKLT_CTRL 34
PANEL_HSYNC_OUT 35
<40> PANEL_HSYNC_OUT 35
36
Test_Point_40MIL TP57 1 37 36
38 37
39 38
Planar side pin assignment follow to Payton design, 40 39
but cable design need to unique design for pin 40
assignment of LCD panel.
1 FOX_GS12401-1011P-9H
@
C280 @
1000P_0402_25V7-K
2
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 LCD CONNECTOR
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common
Circuit to turn on/off pull up resistors on AUXP/AUXN to support DP dongles.
D VCC3B D
DP_DGL_DTCT DP MODE 2SK3541 RTM002 AUXP/N
LOW DP (Native) OFF OFF No pull-up

HIGH TMDS (Dongle) ON ON Pull up to 4.7k
1U_0402_6.3V6-K
0.1U_0402_10V7-K
0.1U_0402_10V7-K
0.01U_0402_25V7-K
0.01U_0402_25V7-K
2 2 2 2
EXT_DP_HPD
C283
C282
C284
C285
C286
1 1 1 1 U9
2
R476
100K_0402_5% 5 50
VDD33_1 OUT1_D0p SYSTEM_DP0P <44>
21 49
VDD33_2 OUT1_D0n SYSTEM_DP0N <44>
30 47
SYSTEM_DP1P <44>
1
51 VDD33_3 OUT1_D1p 46
VDD33_4 OUT1_D1n SYSTEM_DP1N <44>
57 45
VDD33_5 OUT1_D2p SYSTEM_DP2P <44>
44
OUT1_D2n SYSTEM_DP2N <44>
42
OUT1_D3p SYSTEM_DP3P <44>
EXT_DP_HPD 3 41
<14,18,32> EXT_DP_HPD IN_HPD OUT1_D3n SYSTEM_DP3N <44>
DP_DGL_DTCT 4
IN_CA_DET
6 40
<6,32> EXT_DP0P IN_D0p OUT2_D0p DOCK_DP0P <74>
7 39
<6,32> EXT_DP0N IN_D0n OUT2_D0n DOCK_DP0N <74>
9 37
10 36
12 35
<6,32> EXT_DP2P IN_D2P OUT2_D2p DOCK_DP2P <74>
VCC3B VCC3B 13 34
15 32
16 31
C Q37 27 C
RTM002P02GT2L_VMT3 Walter Only N16S@C9317 1 2 0.1U_0201_6.3V6-K M_AUXP 24 OUT1_AUXn_SDA 26
SYSTEM_AUXN <44>
<6> EXT_AUXP_CPU IN_AUXp OUT1_AUXp_SCL SYSTEM_AUXP <44>
2
N16S@C9318 1 2 0.1U_0201_6.3V6-K M_AUXN 25 29

<6> EXT_AUXN_CPU IN_AUXn OUT2_AUXn_SDA DOCK_AUXN <74>
R228 28
S
3 1 OUT2_AUXp_SCL DOCK_AUXP <74>

4.7K_0402_5% <18> I_DDPB_CTRLCLK N16S@ R9922 1 2 0_0201_5% M_DDC_SCL 22
N16S@ R9923 1 2 0_0201_5% M_DDC_SDA 23 IN_DDC_SCL
<18> I_DDPB_CTRLDATA IN_DDC_SDA OUT1/2_HPD has internal PD 150K
48
SYSTEM_DP_HPD <44>
1
N16P@ R9918 1 2 0_0201_5% N16P@C290 1 2 0.1U_0201_6.3V6-K OUT1_HPD 38

G
<32> EXT_AUXP_GPU OUT2_HPD DOCK_DP_HPD <74>

N16P@ R9919 1 2 0_0201_5% N16P@C291 1 2 0.1U_0201_6.3V6-K 2
2
<32> EXT_AUXN_GPU I2C_CTL_EN 43

OUT1_CA_DET SYSTEM_DP_DGL_DTCT <44>
Test_Point_20MIL TP2 1 PS8338_PI1 1 33
PI1/SCL_CTL OUT2_CA_DET
2
PS8338_PI0 60
R168 PI0/SDA_CTL
4.7K_0402_5% VCC3B VCC3B 56 PS8338_PC10
PC10
1
D 17 55 PS8338_PC11
DP_DGL_DTCT 2 20 CEXT PC11 54 PS8338_PC20
1
G REXT PC20 53 PS8338_PC21

R154 1 2 4.7K_0402_5% 59 PC21 8 PS8338_PEQ
Q36 S @ R9985 1 2 4.7K_0402_5% 58 CFG0 PEQ
3
LSK3541G1ET2L_VMT3 EXT_AUXP_GPU CFG1 11

EXT_AUXN_GPU GND1 19
GND2
2
14 52
R165 1 2 4.7K_0402_5% 18 PD GND3 61 R167
VCC3B SW EPAD 1M_0402_5%
2
G
2.2U_0402_6.3V6-M
<17> DDI_PRIORITY2
1
2
2
4.7K_0402_5%
4.7K_0402_5%
R164 1 PS8338BQFN60GTR-A1_QFN60_5X9
R9986
R9984
C281
3 1 2 1 R166
D
S
4.99K_0402_1%
4.7K_0402_5%
RTM002P02GT2L_VMT3 2
1
Q40 Automatic EQ AUX interception
B L Enable Enable B
@ @
CFG0 H Disable Enable LOGIC
M Disable Disable
TABLE : Automatic Switching Mode (CFG0 = H) Auto test Input offset cancellation
L Disable Enable
CFG1 H Enable Enable
SW (DDI_PRIORITY2) M Disable Disable LOGIC
L Port 1 has higher priority when both ports are plugged
H Port 2 has higher priority when both ports are plugged

VCC3B
R229 1 @ 2 4.7K_0402_5% PS8338_PEQ R235 1 @ 2 4.7K_0402_5%
R230 1 @ 2 4.7K_0402_5% PS8338_PC10 R236 1 @ 2 4.7K_0402_5%
R231 1 @ 2 4.7K_0402_5% PS8338_PC11 R237 1 @ 2 4.7K_0402_5%
R232 1 @ 2 4.7K_0402_5% PS8338_PC20 R238 1 @ 2 4.7K_0402_5%
R233 1 @ 2 4.7K_0402_5% PS8338_PC21 R239 1 @ 2 4.7K_0402_5%
A A
R234 1 @ 2 4.7K_0402_5% PS8338_PI0

Issued Date 2015/07/16 Deciphered Date 2016/01/16 DP DEMUX
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Walter Unique VCC3B

NEAR DP CONN
Typ. 500mA
Max 1.5A VCC3VIDEO_DP
U12
5 1
IN OUT 2
4 GND 3
10U_0603_6.3V6M
1 1 EN OC#
C9214 C9202 @ TPS2530DBVR 1
1
C300
10U_0603_6.3V6M 0.1U_0402_25V6-K
2 2 C301
4.7U_0402_6.3V6M
2
2
D D
Vendor P/N
TI TPS2530
On-semi NCP380HSN05AAT1G SYSTEM_DP_DGL_DTCT
DP CONN
5.4Gbps VCC3VIDEO_DP
JDP1 @
SYSTEM_DP_HPD_OUT 2 20
HOT_PLUG DP_PWR 19
DP_AUXP_CONN 16 GND6 14
DP_AUXN_CONN 18 AUX_CH_P GND5 6
0.1U_0402_25V6-K
AUX_CH_N CONFIG2
1
EMC@ 4
1
D10 DP3P 10 CONFIG1 13
LANE3_P GND4 1
R9795 @ DP3N 12 8
DF2S6P8UFS_1-1L1A2
100K_0402_5% LANE3_N GND3 7
DP2P 15 GND2 1
2
VCC3B DP2N 17 LANE2_P GND1 2
2
LANE2_N 21
DP1P 9 GND7 22
C9211
PS8330B has internal PD on HPD DP1N 11 LANE1_P GND8 23
D56 D55 LANE1_N GND9 24
C C
GND10
1
RCLAMP0524PATCT_SLP2510P8-10-9 RCLAMP0524PATCT_SLP2510P8-10-9
100K_0402_5%
DP0N 5
LANE0_N
R9787
DP0P 3
LANE0_P
R9790
C9212
1 R9794
0.01U_0402_25V7-K
DP2N 1 9 DP2N DP0N 1 9 DP0N
2
DP2P 2 8 DP2P DP0P 2 8 DP0P
DP1N 4 7 DP1N DP3P 4 7 DP3P FOX_3VT1127-42BB1-7H
1
DP1P 5 6 DP1P DP3N 5 6 DP3N 1
1
2
1
1
R9788 2
0.1U_0402_25V6-K
2
2
D9 EMC@ 100K_0402_5% D8 EMC@
3
5.1M_0402_5%
NEAR DP CONN DF2S6P8UFS_1-1L1A2 DF2S6P8UFS_1-1L1A2
1M_0402_5%
1
C9213
2
NEAR DP CONN
2
@
VCC3B
1 1 1 1
C9226 C9227 C9228 C9229
0.1U_0402_16V7-K 0.1U_0402_16V7-K 0.1U_0402_16V7-K 0.1U_0402_16V7-K
B 2 2 2 2 B
12
25
32
36
1
6
U220
VDD33_1
VDD33_2
VDD33_3
VDD33_4
VDD33_5
VDD33_6
SYSTEM_DP0P C9230 1 2 0.1U_0402_16V7-K SYSTEM_DP0P_IN 38 23 SYSTEM_DP0P_OUT C9247 1 2 0.1U_0402_25V6-K DP0P

<43> SYSTEM_DP0P IN0p OUT0p
SYSTEM_DP0N C9231 1 2 0.1U_0402_16V7-K SYSTEM_DP0N_IN 39 22 SYSTEM_DP0N_OUT C9246 1 2 0.1U_0402_25V6-K DP0N
<43> SYSTEM_DP0N IN0n OUT0n
<43> SYSTEM_DP1P SYSTEM_DP1N SYSTEM_DP1N_IN IN1p OUT1p SYSTEM_DP1N_OUT
C9233 1 2 0.1U_0402_16V7-K 42 19 C9244 1 2 0.1U_0402_25V6-K DP1N
<43> SYSTEM_DP1N SYSTEM_DP2P SYSTEM_DP2P_IN IN1n OUT1n SYSTEM_DP2P_OUT
C9234 1 2 0.1U_0402_16V7-K 44 17 C9243 1 2 0.1U_0402_25V6-K DP2P
<43> SYSTEM_DP2P SYSTEM_DP2N SYSTEM_DP2N_IN IN2p OUT2p SYSTEM_DP2N_OUT
C9235 1 2 0.1U_0402_16V7-K 45 16 C9242 1 2 0.1U_0402_25V6-K DP2N
<43> SYSTEM_DP3P IN3p OUT3p
SYSTEM_DP3N C9237 1 2 0.1U_0402_16V7-K SYSTEM_DP3N_IN 48 13 SYSTEM_DP3N_OUT C9203 1 2 0.1U_0402_25V6-K DP3N
VCC3B
I2C_ADDR has internal Pull-down 150k ohm 3 40 CFG1 R9987 1 @ 2 4.7K_0402_5%
I2C_ADDR CFG1 VCC3B
R9988 1 @ 2 4.7K_0402_5%
PEQ 4 46
DP_CFG0 5 SCL_CTL/PEQ NC1
SDA_CTL/CFG0 35 RST#
RST#
1
PD# has internal Pull-up 150k ohm 26 10 SYSTEM_DP_DGL_DTCT
PD# CAD_SNK SYSTEM_DP_DGL_DTCT <43>
R9812 1 2 4.99K_0402_1% REXT 7 R9821 R9822 R9820
REXT 11 SYSTEM_DP_HPD_OUT 4.7K_0402_5% 4.7K_0402_5% 10K_0402_5%
HPD_SINK @ @
TP992 1 Test_Point_40MIL 8
2
CAD_SRC
SYSTEM_DP_HPD 9 28 PEQ
<43> SYSTEM_DP_HPD HPD_SRC AUX_SNKP DP_CFG0
27
AUX_SNKN RST#
33
34 SCL_DDC
SDA_DDC 2 CEXT
CEXT 15
SYSTEM_AUXP 30 NC2 21
<43> SYSTEM_AUXP AUX_SRCP NC3
1
SYSTEM_AUXN 29 37 1
<43> SYSTEM_AUXN AUX_SRCN NC4 43 1 R9817 R9818 C9240
NC5 4.7K_0402_5% 4.7K_0402_5% 2.2U_0402_6.3V6-K
A C9241 @ @ A
2
GND1
GND2
GND3
EPAD
2.2U_0402_6.3V6-K
2
2
18
24
31
49
PS8330BQFN48GTR2-A0_QFN48_7X7
HTTPS://EN-MANUALS.CLAN.SU Issued Date 2015/07/16 Deciphered Date 2016/01/16 DISPLAY PORT CONNECTOR
C 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common VCC5B VCC5B_HDMI
D12 RCLAMP0524PATCT_SLP2510P8-10-9 U13
1 6
IN OUT
HDMI_CLK 9 1 HDMI_CLK 1 4 5
HDMI_DAT 8 2 HDMI_DAT FAULT ILIM
1
VCC5B_HDMI 7 4 VCC5B_HDMI C302 3 2
EN GND
1
D HDMI_HPD 6 5 HDMI_HPD 0.1U_0402_25V6-K C303 D
2 4.7U_0402_6.3V6M
R169
2
61.9K_0402_1%
TPS2553DBVR_SOT23-6
VCC3B
2
EMC@
3
SDV & FVT will use SD03459028J(59K_0402_1%)
SIT will use SA000073T00 (61.9K_0402_1%)
2
R170
G
D13 RCLAMP0524PATCT_SLP2510P8-10-9 1M_0402_5% Q5
LSK3541G1ET2L_VMT3
D
3 1
<46> TBT_SRC_DPHPD
HDMI_TX0+_CON 9 1 HDMI_TX0+_CON
HDMI_TX0-_CON HDMI_TX0-_CON VCC5B_HDMI
1
8 2
HDMI_TXC+_CON 7 4 HDMI_TXC+_CON VCC3B
HDMI_TXC-_CON 6 5 HDMI_TXC-_CON R171
20K_0402_5%
No need diode here because TPS2553 has
1
reverse voltage protection function.
2
2
G
EMC@ R172
Q6
3
1.5K_0402_1%
LSK3541G1ET2L_VMT3
1
S
D
3 1
<46> TBT_HDMI_DDC_DAT
1.5K_0402_1% 1.5K_0402_1%
D14 RCLAMP0524PATCT_SLP2510P8-10-9 R173 R174
HDMI CONN.
2
C
VCC3B 6Gbps C
HDMI_TX2-_CON 8 2 HDMI_TX2-_CON
HDMI_TX1-_CON 6 5 HDMI_TX1-_CON
1
JHDMI1
2
R175 HDMI_HPD 19
G
1.5K_0402_1% Q7 18 HP_DET
LSK3541G1ET2L_VMT3 17 +5V
EMC@ HDMI_DAT 16 DDC/CEC_GND
2
3
SDA
D
<46> TBT_HDMI_DDC_CLK 3 1 HDMI_CLK 15
14 SCL
13 Reserved
HDMI_TXC-_CON 12 CEC
11 CK-
HDMI_TXC+_CON 10 CK_shield
HDMI_TX0-_CON 9 CK+
8 D0-
C304 1 2 0.1U_0402_25V6-K H_HDMI_TXC- HDMI_TX0+_CON 7 D0_shield
<46> TBT_SRC_DP3N D0+
HDMI_TX1-_CON 6
C305 1 2 0.1U_0402_25V6-K H_HDMI_TXC+ 5 D1-
<46> TBT_SRC_DP3P D1_shield
C306 1 2 0.1U_0402_25V6-K H_HDMI_TX0- HDMI_TX1+_CON 4 20
<46> TBT_SRC_DP2N D1+ GND1
HDMI_TX2-_CON 3 21
C307 1 2 0.1U_0402_25V6-K H_HDMI_TX0+ 2 D2- GND2 22
<46> TBT_SRC_DP2P D2_shield GND3
C308 1 2 0.1U_0402_25V6-K H_HDMI_TX1- HDMI_TX2+_CON 1 23
<46> TBT_SRC_DP1N D2+ GND4
C309 1 2 0.1U_0402_25V6-K H_HDMI_TX1+ ALLTO_C128D1-K1909-L
<46> TBT_SRC_DP1P
C310 1 2 0.1U_0402_25V6-K H_HDMI_TX2- @
<46> TBT_SRC_DP0N
C311 1 2 0.1U_0402_25V6-K H_HDMI_TX2+
<46> TBT_SRC_DP0P
B L2 EMC@ B
H_HDMI_TXC- 4 3 HDMI_TXC-_CON
4 3
475_0402_1%
475_0402_1%
475_0402_1%
475_0402_1%
475_0402_1%
475_0402_1%
475_0402_1%
475_0402_1%
1
H_HDMI_TXC+ 1 2 HDMI_TXC+_CON
1 2
R176
R177
R178
R179
R180
R181
R182
R183
EXC24CH900U_4P
2
L3 EMC@
H_HDMI_TX0- 4 3 HDMI_TX0-_CON
VCC3B 4 3
H_HDMI_TX0+ 1 2 HDMI_TX0+_CON
1 2
1
D EXC24CH900U_4P
2 Q8
G LSK3541G1ET2L_VMT3
L4 EMC@
S H_HDMI_TX1- 4 3 HDMI_TX1-_CON
3
4 3
1 2
EXC24CH900U_4P
L5 EMC@
H_HDMI_TX2- 4 3 HDMI_TX2-_CON
4 3
A 1 2 A
EXC24CH900U_4P

Issued Date 2015/07/16 Deciphered Date 2016/01/16 HDMI CONNECTOR
5 4 3 2 1
5 4 3 2 1
U14A
C312 1 2 0.22U_0201_6.3V6-K PET0_P V23 Y23
<15> PCIE5_L0_TBT_RXP PET0_N PCIE_TX0_P PCIE_RX0_P PCIE5_L0_TBT_TXP <15>
VCC3V3_LC C315 1 2 0.22U_0201_6.3V6-K V22 Y22 VCC3_SUS
<15> PCIE5_L0_TBT_RXN PCIE_TX0_N PCIE_RX0_N PCIE5_L0_TBT_TXN <15>
CPU PCIE RX
CPU PCIE TX
C316 1 2 0.22U_0201_6.3V6-K PET1_P P23 T23
TBT_TDI <15> PCIE5_L1_TBT_RXP PET1_N PCIE_TX1_P PCIE_RX1_P PCIE5_L1_TBT_TXP <15>
R184 1 2 10K_0402_5% C313 1 2 0.22U_0201_6.3V6-K P22 T22
PCIe GEN3
TBT_TMS <15> PCIE5_L1_TBT_RXN PCIE_TX1_N PCIE_RX1_N PCIE5_L1_TBT_TXN <15>
R185 1 2 10K_0402_5%
1
R186 1 2 10K_0402_5% TBT_TCK C317 1 2 0.22U_0201_6.3V6-K PET2_P K23 M23
TBT_TDO <15> PCIE5_L2_TBT_RXP PET2_N PCIE_TX2_P PCIE_RX2_P PCIE5_L2_TBT_TXP <15>
R188 1 2 10K_0402_5% C318 1 2 0.22U_0201_6.3V6-K K22 M22 R189
<15> PCIE5_L2_TBT_RXN PCIE_TX2_N PCIE_RX2_N PCIE5_L2_TBT_TXN <15>
10K_0402_5%
C319 1 2 0.22U_0201_6.3V6-K PET3_P F23 H23
<15> PCIE5_L3_TBT_RXP PET3_N PCIE_TX3_P PCIE_RX3_P PCIE5_L3_TBT_TXP <15>
C314 1 2 0.22U_0201_6.3V6-K F22 H22
<15> PCIE5_L3_TBT_RXN PCIE5_L3_TBT_TXN <15>
2
PCIE_TX3_N PCIE_RX3_N
L4 V19
<14,24,52,56,60,62> -PLTRST_FAR PERST_N PCIE_REFCLK_100_IN_P PCIE8_CLK_100M_TBT <20>
T19
PCIE_REFCLK_100_IN_N -PCIE8_CLK_100M_TBT <20>
3.01K_0402_1% 2 1 R190 PCIe_RBIAS N16 AC5 R10067 1 @ 2 0_0402_5%
PCIE_RBIAS PCIE_CLKREQ_N -CLKREQ_PCIE8_TBT <20>
@ C9368 1 2 1.5P_0201_25V8-B
R187 1 2 0_0402_5% TBT_XTAL_25_OUT R2 AB7
D <45> TBT_SRC_DP0P DPSRC_ML0_P DPSNK0_ML0_P TBT_SNK0_DP0P <6,32> D
R1 AC7
TBT_XTAL_25_IN <45> TBT_SRC_DP0N DPSRC_ML0_N DPSNK0_ML0_N TBT_SNK0_DP0N <6,32>
@ C9369 1 2 1.5P_0201_25V8-B
Y3 25MHZ_18PF_8Y25000004 Need to confirm Intel Kent
N2 AB9
<45> TBT_SRC_DP1P DPSRC_ML1_P DPSNK0_ML1_P TBT_SNK0_DP1P <6,32>
N1 AC9
<45> TBT_SRC_DP1N DPSRC_ML1_N DPSNK0_ML1_N TBT_SNK0_DP1N <6,32>
1 3 @ C9370 1 2 1.5P_0201_25V8-B
SOURCE PORT 0
1 3 L2 AB11
SINK PORT 0
GND1 GND2 <45> TBT_SRC_DP2P DPSRC_ML2_P DPSNK0_ML2_P TBT_SNK0_DP2P <6,32>
L1 AC11
@ C9371 1 2 1.5P_0201_25V8-B
2 4 J2 AB13
1 1 <45> TBT_SRC_DP3P DPSRC_ML3_P DPSNK0_ML3_P TBT_SNK0_DP3P <6,32>
J1 AC13
C327 C329
27P_0402_50V8-J 27P_0402_50V8-J TP950 1 Test_Point_20MIL TBT_SRC_AUXP W19 Y11
2 2 DPSRC_AUX_P DPSNK0_AUX_P TBT_SNK0_AUXP <6>
TP951 1 Test_Point_20MIL TBT_SRC_AUXN Y19 W11
DPSRC_AUX_N DPSNK0_AUX_N TBT_SNK0_AUXN <6>
G1 AA2
<45> TBT_SRC_DPHPD DPSRC_HPD DPSNK0_HPD TBT_SNK0_DPHPD <14,18,32>
R191 1 2 14K_0402_1% DPSRC_RBIAS N6 Y5 TBT_SNK0_DDC_CLK_R R100241 2 0_0402_5%
N16S@ TBT_SNK0_DDC_CLK <18>
TXC 8Y25000004 DPSRC_RBIAS DPSNK0_DDC_CLK R4 TBT_SNK0_DDC_DATA_R R100251 2 0_0402_5%
N16S@
ESPON Q22FA1280023800 DPSNK0_DDC_DATA TBT_SNK0_DDC_DATA <18>
<52> TBT_I2C_SDA U1
U2 GPIO_0 AB15
<52> TBT_I2C_SCL GPIO_1 DPSNK1_ML0_P TBT_SNK1_DP0P <6,32>
TBT_WP_N V1 AC15
GPIO_2 DPSNK1_ML0_N TBT_SNK1_DP0N <6,32>
R193 1 2 100K_0402_5% V2
LC GPIO
W1 GPIO_3 AB17
<17,61,64,84> -PCIE_WAKE GPIO_4 DPSNK1_ML1_P TBT_SNK1_DP1P <6,32>
AR/PC COMMON FLASH W2 AC17
<23> -CIO_PLUG_EVENT GPIO_5 DPSNK1_ML1_N TBT_SNK1_DP1N <6,32>
Y1
<45> TBT_HDMI_DDC_DAT GPIO_6
Y2 AB19
<45> TBT_HDMI_DDC_CLK TBT_GPIO8 GPIO_7 DPSNK1_ML2_P TBT_SNK1_DP2P <6,32>
AA1 AC19
SINK PORT 1
GPIO_8 DPSNK1_ML2_N TBT_SNK1_DP2N <6,32>
@ R10064 J4
<52> TBTA_I2C_INT TBTB_I2C_INT POC_GPIO_0
1 2 E2 AB21
POC_GPIO_1 DPSNK1_ML3_P TBT_SNK1_DP3P <6,32>
100K_0402_1% 1 2 R10016 D4 AC21
POC GPIO
POC_GPIO_2 DPSNK1_ML3_N TBT_SNK1_DP3N <6,32>
0_0402_5% H4
<23> TBT_FORCE_ON -BATLOW_TBT POC_GPIO_3
F2 Y12 TBT_SNK1_AUXP <6,32>
2 1 -BATLOW_TBT -PCH_SLP_S3_TBT D2 POC_GPIO_4 DPSNK1_AUX_P W12
<17,77> -BATLOW POC_GPIO_5 DPSNK1_AUX_N TBT_SNK1_AUXN <6,32>
100K_0402_1% 1 2 R10017 F1
D85 RB521CS-30GT2RA_VMN2-2 POC_GPIO_6 Y6
DPSNK1_HPD TBT_SNK1_DPHPD <14,18,32>
D86 RB521CS-30GT2RA_VMN2-2 100_0402_5%1 2 R199 TBT_TEST_EN E1
TEST_EN Y8 TBT_SNK1_DDC_CLK R614 1 2 100K_0402_5%
2 1 -PCH_SLP_S3_TBT 100_0402_5%1 2 R200 TBT_TEST_PWG AB5 DPSNK1_DDC_CLK N4 SNK0_CONFIG1 R615 1 2 100K_0402_5%
Misc
<17,76,84,95> -PCH_SLP_S3 TEST_PWR_GOOD DPSNK1_DDC_DATA
F4 Y18 DPSNK_RBIAS R201 1 2 14K_0402_1%
<52> TBT_RESET_N RESET_N DPSNK_RBIAS
@ R10065 TBT_XTAL_25_IN D22 Y4 TBT_TDI
C 1 2 TBT_XTAL_25_OUT D23 XTAL_25_IN TDI V4 TBT_TMS C
XTAL_25_OUT TMS T4 TBT_TCK
0_0402_5% AB3 TCK W4 TBT_TDO
<52> TBT_EE_DI EE_DI MISC TDO
AC4
<52> TBT_EE_DO EE_DO TBT_RBIAS
AC3 H6 R202 1 2 4.75K_0402_0.5%
<52> TBT_EE_CS_N EE_CS_N RBIAS TBT_RSENSE
AB4 J6
<52> TBT_EE_CLK EE_CLK RSENSE
B7 A15
PB_RX1_P PA_RX1_P TBTA_CA2HD_1_P <52>
A7 B15
PB_RX1_N PA_RX1_N TBTA_CA2HD_1_N <52>
A9 A17 TBTA_TX1_P C344 1 2 0.22U_0201_6.3V6-K
TBTA_HD2CA_1_P <52>
Walter Unique B9 PB_TX1_P PA_TX1_P B17 TBTA_TX1_N C346 1 2 0.22U_0201_6.3V6-K

PB_TX1_N PA_TX1_N TBTA_HD2CA_1_N <52>
A11 A19 TBTA_TX0_P C348 1 2 0.22U_0201_6.3V6-K
PB_TX0_P PA_TX0_P TBTA_HD2CA_0_P <52>
B11 B19 TBTA_TX0_N C350 1 2 0.22U_0201_6.3V6-K
PB_TX0_N PA_TX0_N TBTA_HD2CA_0_N <52>
A13 B21
TBT PORTS
PB_RX0_P PA_RX0_P TBTA_CA2HD_0_P <52>
B13 A21
PB_RX0_N PA_RX0_N TBTA_CA2HD_0_N <52>
PORT B
Port A
Y16 Y15 TBTA_AUX_P C352 1 2 0.1U_0201_6.3V6-K TBTA_DPSRC_AUX_P <52> VCC3_FLASH
W16 PB_DPSRC_AUX_P PA_DPSRC_AUX_P W15 TBTA_AUX_N C354 1 2 0.1U_0201_6.3V6-K
PB_DPSRC_AUX_N PA_DPSRC_AUX_N TBTA_DPSRC_AUX_N <52>
VCC3_SUS E19 E20 TBTA_USB2_D_P <52>
D19 PB_USB2_D_P PA_USB2_D_P D20 C341
PB_USB2_D_N PA_USB2_D_N TBTA_USB2_D_N <52>
1 2
100K_0402_1% 1 2 R9664 B4 A5
PB_LSTX PA_LSTX TBTA_LSTX <52>
100K_0402_1% 1 2 R9663 B5 A4 0.1U_0402_16V7-K
TBTA_LSRX <52>
POC
PB_LSRX PA_LSRX
POC
100K_0402_1% 1 2 R9662 G2 M4
PB_DPSRC_HPD PA_DPSRC_HPD TBTA_HPD <52>
TBT_RESET_N @ R9991 1 2 10K_0402_5% 499_0402_1% 1 2 R203 PB_USB2_RBIAS F19 H19 PA_USB2_RBIAS R204 1 2 499_0402_1%
PB_USB2_RBIAS PA_USB2_RBIAS
1
TBT_SNK0_DDC_CLK_R R205 1 2 2.2K_0402_5%
TBT_SNK0_DDC_DATA_R R206 1 2 2.2K_0402_5% D6 AC23 R198
MONDC_SVR THERMDA_1 AB23 3.3K_0402_5%
THERMDA_2
8
A23 VCC3_FLASH U15
VCC3_SUS_TBT B23 ATEST_P V18
VCC
2
ATEST_N PCIE_ATEST
E18 DEBUG AC1
USB2_ATEST TEST_EDM R197 1 2 3.3K_0402_5% TBT_EE_CS_N 1 5 TBT_EE_DI
TBT_SRC_CFG1 HDMI Mode /CS DI(IO0)
W13 L15
TBT_GPIO8 R9993 1 2 10K_0402_5% MONDC_DPSNK_0 FUSE_VQPS_64 N15
TBT_I2C_SDA R209 1 2 2.2K_0402_5% W18 FUSE_VQPS_128 R196 1 2 3.3K_0402_5% TBT_EE_DO 2 6 TBT_EE_CLK
TBT_I2C_SCL R210 1 2 2.2K_0402_5% MONDC_DPSNK_1 C23 DO(IO1) CLK
B TBTA_I2C_INT R211 1 2 10K_0402_5% AB2 MONDC_CIO_0 C22 B
TBTB_I2C_INT R212 1 2 10K_0402_5% MONDC_DPSRC MONDC_CIO_1 R195 1 2 3.3K_0402_5% TBT_WP_N 3 7 TBT_HOLD_N
-BATLOW @ R345 1 2 10K_0402_5% ALPINE-RIDGE-SP_BGA377 /WP(IO2) /HOLD(IO3)
-CIO_PLUG_EVENT R344 1 2 10K_0402_5%
-PCH_SLP_S3 @ R10019 1 2 10K_0402_5%
-BATLOW_TBT @ R10058 2 1 10K_0402_5%
GND
-PCH_SLP_S3_TBT @ R858 1 2 10K_0402_5%
-BATLOW_TBT R10069 1 2 10K_0402_5% W25Q80BLSNIG_SO8
4
-PCH_SLP_S3_TBT R10063 1 2 10K_0402_5%
TBT_SRC_DPHPD R215 1 2 100K_0402_1%
TBT_SNK0_DPHPD R216 1 2 100K_0402_1%
TBT_SNK1_DPHPD R217 1 2 100K_0402_1% EMC
TBTA_LSTX R218 1 2 1M_0402_5% @ @
TBTA_HPD R219 1 2 100K_0402_5% TBT_EE_CLK R640 1 2 0_0402_5% C457 1 2 10P_0402_50V8-J
TBTA_LSRX R220 1 2 1M_0402_5%
TBT_FORCE_ON R347 1 2 100K_0402_1%
VCC5B
Alpine Ridge U37 N16P@

16
0.1U_0201_6.3V6-K Vcc 4 TBT_SNK0_AUXP_GPU_R N16P@ R833 1 2 0_0201_5%
TBT_SNK0_AUXP N16P@ C711 2 1 TBT_SNK0_AUXP_C 2 1A 7 TBT_SNK0_AUXN_GPU_R N16P@ R834 1 2 0_0201_5%
TBT_SNK0_AUXP_GPU <32> from / to
TBT_SNK0_AUXN 1B1 2A TBT_SNK0_AUXN_GPU <32> dGPU DP_A
N16P@ C712 2 1 3 9
TBT_SNK0_AUXN_C 5 1B2 3A 12
SINK0 0.1U_0201_6.3V6-K 6 2B1 4A
TBT_SNK0_DDC_CLK_R 11 2B2 15
TBT_SNK0_DDC_DATA_R 10 3B1 OE 1 SNK0_CONFIG1
3B2 S SINK0_CONFIG1
14
4B1
C713 N16P@
1U_0201_6.3V6-K
13 8 VCC5B is Off : Low

4B2 GND 17
T-PAD VCC5B is ON :
CBT3257ABQ_DHVQFN16_2P5X3P5 High : DDC (HDMI1.4)
Low : AUX (HDMI2.0 or Displayport)
S : (L,H) = (nA to nB1, nA to nB2)
A TBT_SNK0_DDC_CLK_R @ R856 1 2 0_0201_5% TBT_SNK0_AUXP_GPU A

TBT_SNK0_DDC_DATA_R @ R857 1 2 0_0201_5% TBT_SNK0_AUXN_GPU
HTTPS://EN-MANUALS.CLAN.SU Issued Date 2015/07/16 Deciphered Date 2016/01/16 Alpine Ridge (1/6)
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Walter Unique
IN from outside of Alpine Ridge
VCC3V3_LC
D MAX MAX D
0.1A 0.9A
Internal Use (TBD) (TBD)
OUT
VCC0R9_TBT_DP VCC3_SUS
VCC0R9_TBT_CIO VCC0R9_TBT_USB VCC0R9_TBT_PCIE VCC0R9_TBT_DP VCC3_SUS_TBT VCC3V3_S0 VCC0R9_TBT_SVR
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
0.1U_0402_16V7-K
1U_0402_6.3V6-K
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M
1 1 1 1 IN
C355
C356
C357
C358
C359
C360
C361
C370
C371
C372
C373
C366
C367
2 2 2 2
R13
R6
H9
F8
U14B
L8 A2
VCC3P3_LC
VCC3P3_SX
VCC3P3_S0
VCC3P3A
VCC0R9_TBT_USB L11 VCC0P9_DP_1 VCC3P3_SVR_1 A3
L12 VCC0P9_DP_2 VCC3P3_SVR_2 B3 VCC 0.9V from SVR (Step Voltage Regulator)
M8 VCC0P9_DP_3 VCC3P3_SVR_3
VCC0P9_DP_4
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
T11
VCC0P9_DP_5
1U_0402_6.3V6-K
1U_0402_6.3V6-K
T12 L9
L6 VCC0P9_DP_6 VCC0P9_SVR_1 M9
VCC0P9_ANA_DPSRC_1 VCC0P9_SVR_2
C9353
C9354
C383
C384
C385
C386
C387
M6 E12
VCC0P9_ANA_DPSRC_2 VCC0P9_SVR_ANA_1
C374
C377
V11 E13
V12 VCC0P9_ANA_DPSNK_1 VCC0P9_SVR_ANA_2 F11
V13 VCC0P9_ANA_DPSNK_2 VCC0P9_SVR_ANA_3 F12
VCC0P9_ANA_DPSNK_3 VCC0P9_SVR_ANA_4 VCC0R9_TBT_SVR
F13
M13 VCC0P9_SVR_ANA_5 F15
M15 VCC0P9_PCIE_1 VCC0P9_SVR_ANA_6 J9
M16 VCC0P9_PCIE_2 VCC0P9_SVR_SENSE
L19 VCC0P9_PCIE_3
VCC0R9_TBT_PCIE N19 VCC0P9_ANA_PCIE_1_1 C1 TBT_SVR_IND 1 2 L6 OUT
VCC0P9_ANA_PCIE_1_2 SVR_IND_1
47U_0603_6.3V6-M
47U_0603_6.3V6-M
47U_0603_6.3V6-M
L18 C2
M18 VCC0P9_ANA_PCIE_2_1 SVR_IND_2 D1 0.6UH_CMME051B-R60MS_7A_20%
N18 VCC0P9_ANA_PCIE_2_2 SVR_IND_3
C 1 1 1 C
VCC0P9_ANA_PCIE_2_3
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
VCC
C389
C390
C391
XFL4012-601MEC
R15 A1
R16 VCC0P9_USB_1 SVR_VSS_1 B1
VCC0P9_USB_2 SVR_VSS_2 2 2 2
C392
C393
C394
C395
B2
R8 SVR_VSS_3
R9 VCC0P9_CIO_1
R11 VCC0P9_CIO_2
R12 VCC0P9_CIO_3 F18 VCC0R9_TBT_LVR
VCC0P9_CIO_4 VCC0P9_LVR_1 H18
VCC3_TBT_ANA_PCIE L16 VCC0P9_LVR_2 J11 VCC 0.9V from LVR (Linear Voltage Regulator)
VCC3_TBT_ANA_USB2 J16 VCC3P3_ANA_PCIE VCC0P9_LVR_3 H11 Internal Use
VCC3P3_ANA_USB2 VCC0P9_LVR_SENSE
1U_0402_6.3V6-K
VCC0R9_TBT_CIO 1U_0402_6.3V6-K A6
VSS_ANA_1 VSS_ANA_81
V5
10U_0402_6.3V6-M
10U_0402_6.3V6-M
1U_0402_6.3V6-K
1U_0402_6.3V6-K
A8 V6
A10 VSS_ANA_2 VSS_ANA_82 V8
VSS_ANA_3 VSS_ANA_83 1 1
C399
C400
C401
C402
C403
C404
A12 V9
1U_0402_6.3V6-K
1U_0402_6.3V6-K
1U_0402_6.3V6-K
A14 V15
A16 VSS_ANA_5 VSS_ANA_85 V16
A18 VSS_ANA_6 VSS_ANA_86 V20 2 2
C405
C406
C407
A20 W5
A22 VSS_ANA_8 VSS_ANA_88 W6
B6 VSS_ANA_9 VSS_ANA_89 W8
B16 VSS_ANA_14 VSS_ANA_94 Y9
B22 VSS_ANA_17 VSS_ANA_97 AA22
D8 VSS_ANA_18 VSS_ANA_98 AA23
D9 VSS_ANA_19 VSS_ANA_99 AB6
GND
D18 AB18
VCC3V3_S0 VCC3_SUS E8 VSS_ANA_26 VSS_ANA_106 AB20
B
E9 VSS_ANA_27 VSS_ANA_107 AB22 B
L51 VSS_ANA_28 VSS_ANA_108
E11 AC6
1 2 E15 VSS_ANA_29 VSS_ANA_109 AC8
E16 VSS_ANA_30 VSS_ANA_110 AC10
E22 VSS_ANA_31 VSS_ANA_111 AC12
1UH_PCFE20161T-1R0MDR_2.1A_20% VSS_ANA_32 VSS_ANA_112
47U_0603_6.3V6-M
1U_0402_6.3V6-K
E23 AC14
F9 VSS_ANA_33 VSS_ANA_113 AC16
F16 VSS_ANA_34 VSS_ANA_114 AC18
C368
C369
F20 AC20
G22 VSS_ANA_36 VSS_ANA_116 AC22
G23 VSS_ANA_37 VSS_ANA_117 D5
H1 VSS_ANA_38 VSS_1 E4
H13 VSS_ANA_41 VSS_4 F5
H15 VSS_ANA_42 VSS_5 F6
H16 VSS_ANA_43 VSS_6 H5
H20 VSS_ANA_44 VSS_7 H8
J5 VSS_ANA_45 VSS_8 J8
J22 VSS_ANA_49 VSS_12 L13
J23 VSS_ANA_50 VSS_13 M11
K1 VSS_ANA_51 VSS_14 M12
K2 VSS_ANA_52 VSS_15 N8
L5 VSS_ANA_53 VSS_16 N9
M1 VSS_ANA_57 VSS_20 T6
VSS_ANA_61 VSS_24
VSS_ANA_67
VSS_ANA_68
VSS_ANA_69
VSS_ANA_70
VSS_ANA_71
VSS_ANA_72
VSS_ANA_73
VSS_ANA_74
VSS_ANA_75
VSS_ANA_76
VSS_ANA_77
VSS_ANA_78
VSS_ANA_79
VSS_ANA_80
M20 T15
N5 VSS_ANA_62 VSS_25 T16
N20 VSS_ANA_63 VSS_26 T18
N22 VSS_ANA_64 VSS_27 AB1
N23 VSS_ANA_65 VSS_28 AC2
VSS_ANA_66 VSS_29
A A
ALPINE-RIDGE-SP_BGA377
P1
P2
R5
R18
R19
R20
R22
R23
T1
T2
T5
T20
U22
U23
HTTPS://EN-MANUALS.CLAN.SU Issued Date 2015/07/16 Deciphered Date 2016/01/16 Alpine Ridge (2/6)
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Walter Unique
D D
C C
B B
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 Alpine Ridge (3/6)
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Walter Unique
D D
C C
B B
A A

Custom 0.1
5 4 3 2 1
5 4 3 2 1
Walter Unique
D D
C C
B B
A A

Custom 0.1
5 4 3 2 1
5 4 3 2 1
Walter Unique
D D
C C
B B
A A

Custom 0.1
5 4 3 2 1
5 4 3 2 1
Walter Unique TBTA_CC1 1

D89
1
EMC@
2
2 2
2
EMC@ D91
1
1 TBTA_CC2
SESD0201X1BN-0010-098_DFN2 SESD0201X1BN-0010-098_DFN2
D90 EMC@ EMC@ D92
TBTA_RFU1 1 2 2 1 TBTA_RFU2
1 2 2 1
VCC5M
D D
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
VCC_TBTA
VCC2V5_ACEA_LDO_BB
R760
R761
R762
R763
VCC1V8D_ACEA_LDO
C409
C410
C411
C412
VCC1V8A_ACEA_LDO
2.2U_0402_6.3V6-K
2.2U_0402_6.3V6-K
2.2U_0402_6.3V6-K
VCC3_SUS_TBT
0.47U_0402_25V6-K
0.47U_0402_25V6-K
0.47U_0402_25V6-K
0.47U_0402_25V6-K
1
1
1
1
1 1 1 1
1U_0402_6.3V6-K
C414
C415
C416
C433
C434
C435
C436
2 2 2 2
2
2
2
2
C419
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
FL18 1 2 BLM31PG330SN1L_2P
@@@@ @
VCC3_FLASH JTBT1
2
1U_0603_10V6-K
VCC3_SUS D58 @ 4 5 TBTA_CC1
1 9 VBUS1 CC1 17 TBTA_CC2
GSOT24C_SOT23-3 16 VBUS2 CC2
C9359
10U_0805_6.3V7-K
1U_0402_6.3V6-K
21 VBUS3 8 TBTA_RFU1
VBUS4 SBU1 20 TBTA_RFU2
2
SBU2
1
TBTA_USB2_N_T 7
DN1
C420
C417
TBTA_USB2_P_T 6
H10
C11
D11
H11
A11
B11
K11
DP1
J10
J11
G1
H1
H2
B1
K1
A2
E1
A6
A7
A8
B7
TBTA_USB2_N_B 19
F1 TBTA_USB2_P_B 18 DN2
VIN_3V3
VDDIO
LDO_3V3
LDO_1V8A
VOUT_3V3
LDO_1V8D
LDO_BMC
PP_5V0_1
PP_5V0_2
PP_5V0_3
PP_5V0_4
PP_HV_1
PP_HV_2
PP_HV_3
PP_HV_4
VBUS_1
VBUS_2
VBUS_3
VBUS_4
PP_CABLE
I2C_ADDR DP2
C
VCC3_FLASH D1 3 1 C
<46> TBT_I2C_SDA I2C_SDA1 <46> TBTA_HD2CA_0_N SSTX_N1 GND1
<46> TBT_I2C_SCL D2 2 12
I2C_SCL1 <46> TBTA_HD2CA_0_P SSTX_P1 GND2
C1 <46> TBTA_CA2HD_0_P 23 13
<46> TBTA_I2C_INT I2C_IRQ1Z SSRX_P1 GND3
<46> TBTA_CA2HD_0_N 22 24
1 2 ACE_I2C_SDA2 A5 SSRX_N1 GND4 25
R246 10K_0402_5%
1 2 ACE_I2C_SCL2 B5 I2C_SDA2 3A 3A 10 GND5 26
R247 10K_0402_5% <46> TBTA_CA2HD_1_N
TP986 1 Test_Point_12MIL B6 I2C_SCL2 11 SSRX_N2 GND6 27
I2C_IRQ2Z <46> TBTA_CA2HD_1_P SSRX_P2 GND7
ACE_I2C_SDA2 A10 15 28
<77> ACE_I2C_SDA2 SENSEN <46> TBTA_HD2CA_1_N SSTX_N2 GND8
ACE_I2C_SCL2 TP976 1 Test_Point_12MIL B2 14 29
<77> ACE_I2C_SCL2 GPIO0 <46> TBTA_HD2CA_1_P SSTX_P2 GND9
TP977 1 Test_Point_12MIL C2 B10 30
TP978 1 Test_Point_12MIL D10 GPIO1 SENSEP GND10
TP979 1 Test_Point_12MIL G11 GPIO2 JAE_DX07S024JJ2
C10 GPIO3
<46> TBTA_HPD GPIO4
TP980 1 Test_Point_12MIL E10
TP981 1 Test_Point_12MIL G10 GPIO5
Still open to which GPIO6
GPIO should be TP982 1 Test_Point_12MIL D7
connected to HPD TP983 1 Test_Point_12MIL H6 GPIO7
GPIO8 K6 TBTA_USB2_P_T
A3 C_USB_TP L6 TBTA_USB2_N_T
<46> TBT_EE_CLK SPI_CLK C_USB_TN
B4
<46> TBT_EE_DI SPI_MOSI
A4 A9
<46> TBT_EE_DO SPI_MISO HV_GATE2
B3 B9
<46> TBT_EE_CS_N SPI_SSZ HV_GATE1
<46> TBTA_USB2_D_P L5
K5 USB_RP_P K7 TBTA_USB2_P_B
<46> TBTA_USB2_D_N USB_RP_N C_USB_BP L7 TBTA_USB2_N_B VCC3_FLASH
R240 1 2 100K_0402_5% TBTA_UART_RX E2 C_USB_BN
F2 UART_TX
UART_RX D81 EMC@ EMC@ D79
TP984 1 Test_Point_12MIL F4 L9 TBTA_CC1 C9357 220P_0402_50V7-K TBTA_USB2_P_B 1 2 2 1 TBTA_USB2_P_T
TP985 1 Test_Point_12MIL G4 SWD_DATA C_CC1 L10 TBTA_CC2 220P_0402_50V7-K 1 2 2 1
C9358
SWD_CLK C_CC2
1
10K_0402_5%
10K_0402_5%
R9995
B SESD0201X1BN-0010-098_DFN2 SESD0201X1BN-0010-098_DFN2 B
R9994
@ D82 EMC@ EMC@ D80
R241 1 2 100K_0402_5% TBTA_MRESET E11 K9
MRESET RPD_G1 K10
@ R846 1 2 0_0402_5% RPD_G2 TBTA_USB2_N_B 1 2 2 1 TBTA_USB2_N_T
0,62> -PLTRST_FAR
2
R847 1 2 0_0402_5% 1 2 2 1
> -TBT_ACE_MRESET
E4 SESD0201X1BN-0010-098_DFN2 SESD0201X1BN-0010-098_DFN2
L4 DEBUG_CTL1 D5
<46> TBTA_LSTX LSX_R2P DEBUG_CTL2
K4 Recommended ESD 0201
<46> TBTA_LSRX LSX_P2R
structures on high speed lines D65 EMC@ D61 EMC@
R242 1 2 100K_0402_5% TBTA_DIG_AUD_P L3
R243 1 2 100K_0402_5% TBTA_DIG_AUD_N K3 DEBUG3 K8 TBTA_RFU1
DEBUG4 C_SBU1 TBTA_HD2CA_0_P 1 2 2 1 TBTA_HD2CA_1_P
1 2 2 1
R244 1 2 100K_0402_5% TBTA_DEBUG1 L2 L8 TBTA_RFU2
R245 1 2 100K_0402_5% TBTA_DEBUG2 K2 DEBUG1 C_SBU2
DEBUG2 SESD0201X1BN-0010-098_DFN2 SESD0201X1BN-0010-098_DFN2
D66 EMC@ D62 EMC@
VCC3_FLASH <46> TBTA_DPSRC_AUX_P J1
J2 AUX_P F11
<46> TBTA_DPSRC_AUX_N AUX_N RESETZ TBT_RESET_N <46> TBTA_HD2CA_0_N 1 2 2 1 TBTA_HD2CA_1_N
1 2 2 1
F10
BUSPOWERZ
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
TBTA_ACE_ROSC G2 D67 EMC@ D63 EMC@
R_OSC
NC
SS
TBTA_CA2HD_0_P 1 2 2 1 TBTA_CA2HD_1_P
1
U16 1 2 2 1
A1
B8
D6
D8
E5
E6
E7
E8
F5
F6
F7
F8
G5
G6
G7
G8
H4
H5
TBTA_SS H7
0.22U_0402_10V6-K H8
L1
L11
R225 TPS65982ZQZR_BGA96
15K_0402_0.1% SESD0201X1BN-0010-098_DFN2 SESD0201X1BN-0010-098_DFN2
D68 EMC@ D64 EMC@
2
TBTA_CA2HD_0_N 1 2 2 1 TBTA_CA2HD_1_N
1 2 2 1
VCC3_FLASH
C701
A SESD0201X1BN-0010-098_DFN2 SESD0201X1BN-0010-098_DFN2 A
1
R10036 1 2 100K_0402_5% TBTA_DPSRC_AUX_N

R10035 1 2 100K_0402_5% TBTA_DPSRC_AUX_P 2

Issued Date 2015/07/16 Deciphered Date 2016/01/16 Thunderbolt Power TPS65982/USB Type-C (1/2)
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Walter Unique
D D
C C
B B
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 Thunderbolt Power TPS65982/USB Type-C (2/2)
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Walter Unique USB_PWR_S1 JUSB2 @

4
L47 EXC24CH900U_4P
4 3
3
9 USB3P1_TXP_CONN 1 2
StdA_SSTX+ 1 2
Co-lay
1
VBUS 8 USB3P1_TXN_CONN EMC@
StdA_SSTX- 3
D+ 7
GND_1 @
@ 10 2 USB3P1_RXN_CONN R9777 1 2 0_0402_5%
GND_2 D- USB3P1_SYSP1_RXN <19>
USBP1-_AOU R9773 1 2 0_0402_5% USBP1-_CONN 11 6 USB3P1_RXP_CONN R9776 1 2 0_0402_5%
GND_3 StdA_SSRX+ USB3P1_SYSP1_RXP <19>
USBP1+_AOU R9772 1 2 0_0402_5% USBP1+_CONN 12 4 @
@ 13 GND_4 PGND 5 R9778 1 @ 2 0_0402_5% USB3P1_TXN_C C9215 1 2 0.1U_0402_25V6-K
GND_5 StdA_SSRX- USB3P1_SYSP1_TXN D<19>
D
1 R9779 1 2 0_0402_5% USB3P1_TXP_C C9216 1 2 0.1U_0402_25V6-K
L48 EXC24CH900U_4P USB3P1_SYSP1_TXP <19>
2 2 ALLTO_C107LP-109H5-L @
1 2 +
1 2 C437
C9222 C9223 150U_B2_6.3VM_R35M D16
4 3 0.1U_0402_25V6-K 0.1U_0402_25V6-K RCLAMP0524PATCT_SLP2510P8-10-9
4 3 1 1 2
L9 EXC24CH900U_4P
EMC@ 4 3
WIDE PATTERN(MIN 500mA) AOZ8904CIL_SOT23-6 4 3
3 4 USB3P1_RXN_CONN 1 9 USB3P1_RXN_CONN
PLACE NEAR USB CONN 1 2 USB3P1_RXP_CONN 2 8 USB3P1_RXP_CONN
1 2 USB3P1_TXN_CONN 4 7 USB3P1_TXN_CONN
EMC@ USB3P1_TXP_CONN 5 6 USB3P1_TXP_CONN
2 5
L11 EXC24CH900U_4P
L10 EXC24CH900U_4P 4 3
USB_PWR_S2 4 3
1 2
1 2 1 6
3
1 2 EMC@
D15 1 2
4 3
4 3 EMC@
Co-lay
EMC@
EMC@
@
@ USB3P2_RXN_CONN R9783 1 2 0_0402_5%
USB3P2_SYSP2_RXN <19>
USBP2-_SYSP2 R9774 1 2 0_0402_5% USBP2-_CONN USB3P2_RXP_CONN R9780 1 2 0_0402_5%
<15> USBP2-_SYSP2 USB3P2_SYSP2_RXP <19>
USBP2+_SYSP2 R9775 1 2 0_0402_5% USBP2+_CONN @
<15> USBP2+_SYSP2
R9782 1 @
0.1U_0402_25V6-K
0.1U_0402_25V6-K
JUSB1 @ USB3P2_TXN_CONN 2 0_0402_5% USB3P2_TXN_C C438 1 2 0.1U_0402_25V6-K
USB3P2_SYSP2_TXN <19>
@ 1 9 USB3P2_TXP_CONN R9781 1 2 0_0402_5% USB3P2_TXP_C C440 1 2 0.1U_0402_25V6-K
StdA_SSTX+ 1 USB3P2_SYSP2_TXP <19>
2 2 @
+ C442 VBUS 8
C441 C439 150U_B2_6.3VM_R35M StdA_SSTX- 3
D+ 7 L12 EXC24CH900U_4P
C 1 1 2 10 GND_1 2 4 3 C
PLACE NEAR USB CONNECTOR 11 GND_2 D- 6
4 3
12 GND_3 StdA_SSRX+ 4
WIDE PATTERN(MIN 500mA) 13 GND_4 PGND 5 1 2
GND_5 StdA_SSRX- 1 2
ALLTO_C107LP-109H5-L EMC@
VCC5M
1st:Semtech RCLAMP0524PATCT (SC300000T0J)
D16,D18 2nd:LittelFuse SP3012-04UTG-1 MO-229 (SC300003900)
3th:LittelFuse SP3012-04UTG UDFN (SC300003800)
D18
RCLAMP0524PATCT_SLP2510P8-10-9
2
F18
3A_32V_ERBRD3R00X
USB3P2_TXP_CONN 1 9 USB3P2_TXP_CONN
USB3P2_TXN_CONN 2 8 USB3P2_TXN_CONN
USB3P2_RXP_CONN 4 7 USB3P2_RXP_CONN
1
USB3P2_RXN_CONN 5 6 USB3P2_RXN_CONN
B B
0.1U_0402_25V6-K
4.7U_0402_6.3V6M
3
EMC@
2 2
@ VCC5M
C443 C444
1 1 @
1 2
Current Limit Target: C445 4.7U_0402_6.3V6M
2.3A(2.1 - 2.45A)
USB_PWR_S2
C446
USB_PWR_S1 1 2
U19
U18 9
1 12 0.1U_0402_25V6-K GND_2
IN OUT 1 8
13 9 2 GND_1 OUT_8 7
<15> -USB_PORT0_OC0 FAULT# STATUS# -AOU_IFLG <76> IN_2 OUT_7
3 6
2 11 USBP1-_AOU 4 IN_3 OUT_6 5 -USB_PORT1_OC1
<15> USBP1-_SYSP1 DM_OUT DM_IN <55,76> USB_ON2 EN/EN FLT -USB_PORT1_OC1 <15>
3 10 USBP1+_AOU
<15> USBP1+_SYSP1 DP_OUT DP_IN
2.7M_0402_5% TPS2069CDGNR-2_MSOP8
4 15 R9785 1 2
<76> AOU_SEL2 ILIM_SEL ILIM_LO
<76> USB_ON1 5 16 1 2
EN ILIM_HI
R9784 22.1K_0402_1%
<76> AOU_SEL1 6
7 CTL1 14
8 CTL2 GND 17
CTL3 GPAD TABLE of USB3.0 Single LCFC P/N
TPS2546RTER_QFN16_3X3
A GMT G548A1F51U SA00005RL00 A

TABLE of USB Charge LCFC P/N
TI TPS2069CDGNR-2 SA000079Y00
TI TPS2546RTER SA00005TD00
Pericom PI5USB2546ZHEX SA000066I00

Issued Date 2015/07/16 Deciphered Date 2016/01/16 USB POWER/CONN (1/2)
5 4 3 2 1
5 4 3 2 1
Walter Unique USB_PWR_D1

4
L13 EXC24CH900U_4P
4 3
3
@ JUSB3 1 2
1 2
Co-lay
1
VBUS 2 EMC@
D- 3
D+ 4
GND @
@ 5 USB3P5_RXN_CONN R9798 1 2 0_0402_5%
Stda_SSRX- USB3P5_SYSP3_RXN <19>
<15> USBP5-_SYSP3 R9802 1 2 0_0402_5% USBP5-_CONN 10 6 USB3P5_RXP_CONN R9800 1 2 0_0402_5%
GND2 Stda_SSRX+ USB3P5_SYSP3_RXP <19>
<15> USBP5+_SYSP3 R9801 1 2 0_0402_5% USBP5+_CONN 11 7 @
12 GND3 GND_DRAIN 8 USB3P5_TXN_CONN R9797 1 @ 2 0_0402_5% USB3P5_TXN_C C447 1 2 0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
D @ GND4 Stda_SSTX- USB3P5_SYSP3_TXN D <19>
1 13 9 USB3P5_TXP_CONN R9799 1 2 0_0402_5% USB3P5_TXP_C C448 1 2 0.1U_0402_25V6-K
L14 EXC24CH900U_4P GND5 Stda_SSTX+ USB3P5_SYSP3_TXP <19>
1 2 2 2 @
1 2 + C451 FOX_UEA111Y-N40A1-7H
C449 C450 150U_B2_6.3VM_R35M D20
4 3 1 1 2 RCLAMP0524PATCT_SLP2510P8-10-9
4 3
L15 EXC24CH900U_4P
EMC@ AOZ8904CIL_SOT23-6
WIDE PATTERN(MIN 500mA) 4 3
4
4 3
3
USB3P5_RXN_CONN 1 9 USB3P5_RXN_CONN
PLACE NEAR USB CONN 1 2
1 2 USB3P5_TXN_CONN 4 7 USB3P5_TXN_CONN
5 2 USB3P5_TXP_CONN 5 6 USB3P5_TXP_CONN
EMC@
L17 EXC24CH900U_4P
L16 EXC24CH900U_4P 4 3
USB_PWR_D2 6 1 4 3
1 2
1 2
3
D19 EMC@
1 2
EMC@ 1 2
4 3
4 3 EMC@
EMC@
@ USB3P6_RXN_CONN R9805 1
@
2 0_0402_5%
Co-lay USB3P6_SYSP4_RXN <19>
<15> USBP6-_SYSP4 R249 1 2 0_0402_5% USBP6-_CONN USB3P6_RXP_CONN R9806 1 2 0_0402_5%
USB3P6_SYSP4_RXP <19>
<15> USBP6+_SYSP4 R251 1 2 0_0402_5% USBP6+_CONN @
@ JUSB4 USB3P6_TXN_CONN R9804 1 @ 2 0_0402_5% USB3P6_TXN_C C452 1 2 0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
1 USB3P6_SYSP4_TXN <19>
@ 1 USB3P6_TXP_CONN R9803 1 2 0_0402_5% USB3P6_TXP_C C9345 1 2 0.1U_0402_25V6-K
VBUS 2 USB3P6_SYSP4_TXP <19>
2 2 D- @
+ C9342 3
150U_B2_6.3VM_R35M D+ 4
C455 C453
GND 5 L18 EXC24CH900U_4P
C 1 1 2 10 Stda_SSRX- 6 4 3 C
PLACE NEAR USB CONNECTOR 11 GND2 Stda_SSRX+ 7 4 3
12 GND3 GND_DRAIN 8
WIDE PATTERN(MIN 500mA) 13 GND4 Stda_SSTX- 9 1 2
GND5 Stda_SSTX+ 1 2
FOX_UEA111Y-N40A1-7H EMC@

D21
D20,D22 2nd:LittelFuse SP3012-04UTG-1 MO-229 (SC300003900)
1 6
3th:LittelFuse SP3012-04UTG UDFN (SC300003800)
D22
2 5 RCLAMP0524PATCT_SLP2510P8-10-9
3 4 USB3P6_RXN_CONN 1 9 USB3P6_RXN_CONN
AOZ8904CIL_SOT23-6 USB3P6_TXN_CONN 4 7 USB3P6_TXN_CONN
EMC@ USB3P6_TXP_CONN 5 6 USB3P6_TXP_CONN
3
B B
EMC@
VCC5M
@
C9343 1 2 4.7U_0402_6.3V6M
USB_PWR_D1 USB_PWR_D2
C9346 1 2 0.1U_0402_25V6-K
TABLE of USB3.0 Dual LCFC P/N
U20
1 8
2 GND1 FLT1 7
-USB_PORT2_OC2 <15> GMT G546A1F51U SA00005PF00
3 IN OUT1 6
USB_ON2 4 EN1 OUT2 5
<54,76> USB_ON2 EN2 FLT2 -USB_PORT3_OC3 <15> TI TPS2064CDGNR-2 SA000079X00
9
GND2
DIODE AP2192MPG-13 SA00005VA00
TPS2064CDGNR-2_MSOP-POWERPAD8 Need Confirm
A FOR ON BOARD DUAL USB 3.0 CONNECTOR A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 USB POWER/CONN (2/2)
5 4 3 2 1
5 4 3 2 1
Payton Common
VCC3M VCC3B VCC3GBE
D D
1
R494 R254 R255 @
4.7K_0402_5% 10K_0402_5% 10K_0402_5%
2
U21
-CLKREQ_PCIE3_GBE 48 13 MDI_0+
<20> -CLKREQ_PCIE3_GBE CLK_REQ_N MDI_PLUS[0] MDI_0+ <57>
-PLTRST_FAR 36 14 MDI_0-
<14,24,46,52,60,62> -PLTRST_FAR PE_RST_N MDI_MINUS[0] MDI_0- <57>
PCIE3_CLK_100M_GBE 44 17 MDI_1+
<20> PCIE3_CLK_100M_GBE PE_CLKP MDI_PLUS[1] MDI_1+ <57>
-PCIE3_CLK_100M_GBE 45 18 MDI_1-
<20> -PCIE3_CLK_100M_GBE PE_CLKN MDI_MINUS[1] MDI_1- <57>
PCIE
MDI
PCIE4_GBE_RXP C459 1 2 0.1U_0402_25V6-K PCIE4_RXP_C 38 20 MDI_2+
<15> PCIE4_GBE_RXP PETp MDI_PLUS[2] MDI_2+ <57>
PCIE4_GBE_RXN C460 1 2 0.1U_0402_25V6-K PCIE4_RXN_C 39 21 MDI_2-
<15> PCIE4_GBE_RXN PETn MDI_MINUS[2] MDI_2- <57>
VCC3GBE
PCIE4_GBE_TXP 41 23 MDI_3+
<15> PCIE4_GBE_TXP PERp MDI_PLUS[3] MDI_3+ <57>
PCIE4_GBE_TXN 42 24 MDI_3-
<15> PCIE4_GBE_TXN PERn MDI_MINUS[3] MDI_3- <57>
SMBUS DEVICE ADDRESSES 0XC8
SML0_CLK 28 6 R256 1 2 0_0402_5%
<17> SML0_CLK SML0_DATA 31 SMB_CLK SVR_EN_N
SMBUS
<17> SML0_DATA SMB_DATA 1 R259 1 2 4.7K_0402_5%
RSVD1_VCC3P3
-LANWAKE 2 5
<17> -LANWAKE LANWAKE_N VDD3P3_IN
LANPHYPC 3
<17> LANPHYPC LAN_DISABLE_N 4
VDD3P3_4
15 C461 1 2 1UF_0402_6.3V
C RJ45_LINKUP 26 VDD3P3_15 19 C
<57,76> RJ45_LINKUP LED0 VDD3P3_19
RJ45_ACTIVITY 27 29
<57> RJ45_ACTIVITY LED1 VDD3P3_29
25 VCC0R9GBE
LED
LED2
47 VCC0R9GBE
VDD0P9_47 46
VCC3GBE 32 VDD0P9_46 37
34 JTAG_TDI VDD0P9_37
R260 1 2 10K_0402_5% 33 JTAG_TDO 43
KEEP SHORT AND WIDE
JTAG
R261 1 2 10K_0402_5% 35 JTAG_TMS VDD0P9_43 PATTERN
JTAG_TCK 11
R262 VDD0P9_11
XTAL_OUT_R 1 2 XTAL_OUT 9 40
XTAL_IN 10 XTAL_OUT VDD0P9_40 22
XTAL_IN VDD0P9_22 16
0_0402_5% VDD0P9_16 8
30 VDD0P9_8
TEST_EN
Placed close to FL40
RBIAS 12 7 VCC0R9GBE_L FL1 1 2 4.7UH_LQH32PN4R7NN0_30%
Y4 25MHZ_18PF_8Y25000004 RBIAS CTRL0P9
49
1 3 GND
1 3 WGI219LM-QREF-A0_QFN48_6X6
GND1 GND2
@
FL1 1
C462
1
C463
1
C464 @
1
1
1
C465 2 4 C466
1
R263 R264
TDK FLF3215T-4R7M <-EOL 22U_0805_6.3V6M 0.1U_0402_25V6-K 0.1U_0402_25V6-K
27P_0402_50V8-J 27P_0402_50V8-J 1K_0402_5% 3.01K_0402_1% MURATA LQH32PN4R7NN0 2 2 2
2 2
2
B B
TXC 8Y25000004
ESPON Q22FA1280023800
U21 GBE PHY

VCC3LAN VCC3LAN_F VCC3GBE
vPRO Model Non-vPRO Model

F20 R265
1 2 1 2
I219LM I219V
3A_32V_ERBRD3R00X 0.01_0603_LE_1%
1 1 1 1
C467 C468 C469 C470
0.1U_0402_25V6-K 0.1U_0402_25V6-K 22U_0805_6.3V6M 0.1U_0402_25V6-K
2 2 2 2
U21 U21
A A
Intel Ethernet I219V Intel Ethernet I219LM
SA000072Z10 SA000073020
NVP@ VP@

Issued Date 2015/07/16 Deciphered Date 2016/01/16 GBE JACKSONVILLE
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common
VCC3GBE
D D
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
VCC3GBE
1 1 1 1 1
1
2 2 2 2 2
C472
C471
C473
C474
C475
R266
4.7K_0402_5%
39
30
21
14
8
4
1
U22
VDD_7
VDD_6
VDD_5
VDD_4
VDD_3
VDD_2
VDD_1
38 DOCK_MDI_3-
B0+ DOCK_MDI_3- <74>
37 DOCK_MDI_3+
B0- DOCK_MDI_3+ <74>
MDI_3- 2
<56> MDI_3- A0+ 34 DOCK_MDI_2-
MDI_3+ 3 33 DOCK_MDI_2+
<56> MDI_3+ A0- B1- DOCK_MDI_2+ <74>
C 29 DOCK_MDI_1- C
MDI_2- 6 28 DOCK_MDI_1+
<56> MDI_2- A1+ B2- DOCK_MDI_1+ <74>
MDI_2+ 7 25 DOCK_MDI_0-
<56> MDI_2+ A1- B3+ DOCK_MDI_0- <74>
24 DOCK_MDI_0+
B3- DOCK_MDI_0+ <74>
MDI_1- 9 17
<56> MDI_1- A2+ LEDB0 18
MDI_1+ 10 LEDB1 41
<56> MDI_1+ A2- LEDB2
36 SYS_MDI_3-
C0+ SYS_MDI_3- <58>
MDI_0- 11 35 SYS_MDI_3+
<56> MDI_0- A3+ C0- SYS_MDI_3+ <58>
MDI_0+ 12 32 SYS_MDI_2-
<56> MDI_0+ A3- C1+ SYS_MDI_2- <58>
31 SYS_MDI_2+
C1- SYS_MDI_2+ <58>
-DOCK_ATTACHED_AUX 13 27 SYS_MDI_1-
<74> -DOCK_ATTACHED_AUX SEL C2+ SYS_MDI_1- <58>
26 SYS_MDI_1+
C2- SYS_MDI_1+ <58>
15 23 SYS_MDI_0-
<56> RJ45_ACTIVITY LEDA0 C3+ SYS_MDI_0- <58>
16 22 SYS_MDI_0+
<56,76> RJ45_LINKUP LEDA1 C3- SYS_MDI_0+ <58>
42
LEDA2 19
LEDC0 RJ45_ACTIVITY_SYS <59>
5 20 RJ45_LINKUP_SYS <59>
PD LEDC1 40
43 LEDC2
PAD_GND
PI3L720ZHEX_TQFN42_9X3P5
B B
U22
Vendor P/N
Pericom PI3L720ZHE
TI TS3L501E
Add TI LAN Switch since On Semi informed us of the EOL of NCN7201 in 2015.
But TI LAN Switch may fail CDE Test at 8KV. In case of the failure at 8KV, Need to use two TVS Diodes with TI LAN Switch. Remove On Semi.
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 GBE LAN SWITCH
Custom 0.1
5 4 3 2 1
5 4 3 2 1
T1
SYS_MDI_3- 1 1:1
<57> SYS_MDI_3- TD1+ T1/B
24 RJ45_TXD3N
TX1+ RJ45_TXD3N <59>
SYS_MDI_3+ 2
<57> SYS_MDI_3+ TD1-
23 RJ45_TXD3P
TX1- RJ45_TXD3P <59>
3 22
TDCT1 T1/A TXCT1
4 21
TDCT2 1:1 TXCT2
SYS_MDI_2- 5 T1/B
D <57> SYS_MDI_2- TD2+ D
20 RJ45_TXD2N
SYS_MDI_2+ 6
<57> SYS_MDI_2+ TD2- 19 RJ45_TXD2P
T1/A
SYS_MDI_1- 1:1
7
<57> SYS_MDI_1- TD3+ T1/B
18 RJ45_TXD1N
SYS_MDI_1+ 8
<57> SYS_MDI_1+ TD3-
17 RJ45_TXD1P
9 16
TDCT3 T1/A TXCT3
10 15
TDCT4 1:1 TXCT4
SYS_MDI_0- 11 T1/B
<57> SYS_MDI_0- TD4+ 14 RJ45_TXD0N
SYS_MDI_0+ 12
<57> SYS_MDI_0+ TD4- 13 RJ45_TXD0P
75_0805_5%
75_0805_5%
75_0805_5%
75_0805_5%
T1/A
C C
Bothhand_NA69LF
EMC@
THE WIDTH OF THESE TRACE SHOULD
BE WIDER THAN 35MIL TO PREVENT
VOLTAGE DROP.
1
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
1UF_0402_6.3V
R267 2
R268 2
R269 2
R270 2
PATTERN MUST BE
1 1 1 1 1 1 1 SHORT AND WIDE.
C303
2 2 2 2 2 2 2
SHOULD BE PLACED AS CLOSE
C476
C477
C478
C479
C480
C481
C482
TO MAGNETICS AS POSSIBLE.
1
EMC@ HIGH VOLTAGE
@ @ R271 C483
1M_0805_5% 1500P_1808_2KV7K 1500PF CAP
2
IS OPTIONAL
2
ESD REASON
B B
T1
Vendor P/N
Timag IH-115-F
Bothhand NA69LF
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 GBE MAGNETICS
Payton Common
Custom
NM-A451
Rev
0.1

5 4 3 2 1
5 4 3 2 1
Payton Common D23


RJ45_TXD0P 1 9 RJ45_TXD0P
RJ45_TXD0N 2 8 RJ45_TXD0N D23,D24 2nd:LittelFuse SP3012-04UTG-1 MO-229 (SC300003900)
RJ45_TXD2N 5 6 RJ45_TXD2N 3th:LittelFuse SP3012-04UTG UDFN (SC300003800)
D D
3
EMC@
D24
RJ45_TXD1N 2 8 RJ45_TXD1N
RJ45_TXD3N 5 6 RJ45_TXD3N
3
EMC@
RJ45_TXD1P
<58> RJ45_TXD1P
RJ45_TXD1N
<58> RJ45_TXD1N
RJ45_TXD3P
<58> RJ45_TXD3P
RJ45_TXD3N
<58> RJ45_TXD3N
C C
JGBE1 @
10
Yellow_LED-
9
Yellow_LED+
1
PR1+
2
PR1-
R547 1 2 3
<57> RJ45_ACTIVITY_SYS PR2+
330_0402_5%
RJ45_TXD0P 4
<58> RJ45_TXD0P PR3+
RJ45_TXD0N
<58> RJ45_TXD0N
5
RJ45_TXD2P PR3-
<58> RJ45_TXD2P
RJ45_TXD2N 6
<58> RJ45_TXD2N PR2-
7 14
PR4+ G2
8 13
PR4- G1
12
Green_LED-
R554 1 2 330_0402_5% 11
<57> RJ45_LINKUP_SYS Green_LED+
SINGA_2RJ3062-138211F
B B
0.1U_0402_25V6-K
0.1U_0402_25V6-K
1 1
C485
C486
2 2
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 RJ45 CONNECTOR
Custom 0.1
5 4 3 2 1
5 4 3 2 1
M.2 PCIe SSD M.2 SATA SSD

Planar M.2 PCIe SSD Module Planar M.2 SATA SSD Module
PCH SOCKET PLUG CHIP PCH SOCKET PLUG CHIP
PCIE9_RXP/SATA0A_RXP PCIE9L0_SATA0A_MD2_SSD1_RXP 41: PERN0/SATA_B+ 41: PETN0 PCIE9_RXP/SATA0A_RXP PCIE9L0_SATA0A_MD2_SSD1_RXP 41: PERN0/SATA_B+ 41: SATA B+
PCIE9_RXN/SATA0A_RXN PCIE9L0_SATA0A_MD2_SSD1_RXN 43: PERP0/SATA_B- 43: PETP0 PCIE9_RXN/SATA0A_RXN PCIE9L0_SATA0A_MD2_SSD1_RXN 43: PERP0/SATA_B- 43: SATA B-
D PCIe: Lane Polarity Inversion Used SATA: Straight D
0.22uF 0.22uF
PCIE9_TXN/SATA0A_TXN PCIE9L0_SATA0A_MD2_SSD1_TXN 47: PETN0/SATA_A- 47: PERN0 PCIE9_TXN/SATA0A_TXN PCIE9L0_SATA0A_MD2_SSD1_TXN 47: PETN0/SATA_A- 47: SATA A-
PCIE9_TXP/SATA0A_TXP PCIE9L0_SATA0A_MD2_SSD1_TXP 49: PETP0/SATA_A+ 49: PERP0 PCIE9_TXP/SATA0A_TXP PCIE9L0_SATA0A_MD2_SSD1_TXP 49: PETP0/SATA_A+ 49: SATA A+
0.22uF 0.22uF
VCC3B
VCC3B
M.2 SSD slot 2
M.2 SSD slot 1
2
Type-M 2280 R844
2
Type-M 2280 R843
0.01_0603_LE_1% JSSD2
0.01_0603_LE_1%
1
JSSD1 VCC3B
1 2
GND_1 3.3V_1
1
VCC3B 3 4
1 2 5 GND_2 3.3V_2 6
C 3 GND_1 3.3V_1 4 <16> PCIE17L3_MD2_SSD2_RXN PERN3 N/C_2 C
GND_2 3.3V_2 <16> PCIE17L3_MD2_SSD2_RXP 7 8
<16> PCIE9L3_MD2_SSD1_RXN 5 6 9 PERP3 N/C_3 10 -DAS_MD2_SSD2
7 PERN3 N/C_2 8 M.2 SSD2 L3 GND_3 DAS/DSS#/LED1#
<16> PCIE9L3_MD2_SSD1_RXP PERP3 N/C_3 11 12
9 10 -DAS_MD2_SSD1 <16> PCIE17L3_MD2_SSD2_TXN PETN3 3.3V_3
1
M.2 SSD1 L3 GND_3 DAS/DSS#/LED1# <16> PCIE17L3_MD2_SSD2_TXP 13 14
11 12 15 PETP3 3.3V_4 16
<16> PCIE9L3_MD2_SSD1_TXN PETN3 3.3V_3
1
<16> PCIE9L3_MD2_SSD1_TXP 13 14 17 GND_4 3.3V_5 18 R273
15 PETP3 3.3V_4 16 <16> PCIE17L2_MD2_SSD2_RXN PERN2 3.3V_6
GND_4 3.3V_5 R272 19 20 10K_0402_5%
17 18 10K_0402_5% <16> PCIE17L2_MD2_SSD2_RXP PERP2 N/C_4
<16> PCIE9L2_MD2_SSD1_RXN PERN2 3.3V_6 M.2 SSD2 L2 21 22
2
<16> PCIE9L2_MD2_SSD1_RXP 19 20 23 GND_5 N/C_5 24
21 PERP2 N/C_4 22 <16> PCIE17L2_MD2_SSD2_TXN PETN2 N/C_6
M.2 SSD1 L2 25 26
2
23 GND_5 N/C_5 24 <16> PCIE17L2_MD2_SSD2_TXP PETP2 N/C_7
<16> PCIE9L2_MD2_SSD1_TXN PETN2 N/C_6 27 28
<16> PCIE9L2_MD2_SSD1_TXP 25 26 29 GND_6 N/C_8 30
27 PETP2 N/C_7 28 <16> PCIE17L1_MD2_SSD2_RXN PERN1 N/C_9
GND_6 N/C_8 <16> PCIE17L1_MD2_SSD2_RXP 31 32
<16> PCIE9L1_MD2_SSD1_RXN 29 30 33 PERP1 N/C_10 34
31 PERN1 N/C_9 32 M.2 SSD2 L1 GND_7 N/C_11
<16> PCIE9L1_MD2_SSD1_RXP PERP1 N/C_10 35 36
M.2 SSD1 L1 33 34 <16> PCIE17L1_MD2_SSD2_TXN PETN1 N/C_12
GND_7 N/C_11 <16> PCIE17L1_MD2_SSD2_TXP 37 38
35 36 PETP1 DEVSLP DEVSLP4_MD2_SSD2 <19>
<16> PCIE9L1_MD2_SSD1_TXN PETN1 N/C_12 39 40
<16> PCIE9L1_MD2_SSD1_TXP 37 38 41 GND_8 N/C_13 42
PETP1 DEVSLP DEVSLP0_MD2_SSD1 <19> <16> PCIE17L0_SATA4_MD2_SSD2_RXP
39 40 43 PERN0/SATA_B+ N/C_14 44
41 GND_8 N/C_13 42 <16> PCIE17L0_SATA4_MD2_SSD2_RXN PERP0/SATA_B- N/C_15
<16> PCIE9L0_SATA0A_MD2_SSD1_RXP PERN0/SATA_B+ N/C_14 M.2 SSD2 L0 45 46
<16> PCIE9L0_SATA0A_MD2_SSD1_RXN 43 44 47 GND_9 N/C_16 48
45 PERP0/SATA_B- N/C_15 46 <16> PCIE17L0_SATA4_MD2_SSD2_TXN PETN0/SATA-A- N/C_17
M.2 SSD1 L0 GND_9 N/C_16 <16> PCIE17L0_SATA4_MD2_SSD2_TXP 49 50
47 48 PETP0/SATA-A+ PERST# -PLTRST_FAR <14,24,46,52,56,62>
<16> PCIE9L0_SATA0A_MD2_SSD1_TXN PETN0/SATA-A- N/C_17 51 52 -CLKREQ_PCIE7_MD2_SSD2 <20>
<16> PCIE9L0_SATA0A_MD2_SSD1_TXP 49 50 -PLTRST_FAR 53 GND_10 CLKREQ# 54
51 PETP0/SATA-A+ PERST# 52 <20> -PCIE7_CLK_100M_MD2_SSD2 REFCLKN PEWAKE#
GND_10 CLKREQ# -CLKREQ_PCIE4_MD2_SSD1 <20> <20> PCIE7_CLK_100M_MD2_SSD2 55 56
53 54 57 REFCLKP N/C_18 58
<20> -PCIE4_CLK_100M_MD2_SSD1 REFCLKN PEWAKE#
<20> PCIE4_CLK_100M_MD2_SSD1 55 56 GND_11 N/C_19
57 REFCLKP N/C_18 58
GND_11 N/C_19 59 NC NC 60
61 NC NC 62
59 NC NC 60 63 NC NC 64
61 NC NC 62 65 NC NC 66
63 NC NC 64
67 68
B 65 NC NC 66 N/C_1 SUSCLK B
PCIE_DETECT_SSD2 69 70
67 68 71 PEDET 3.3V_7 72
PCIE_DETECT_SSD1 69 N/C_1 SUSCLK 70 GND_12 3.3V_8
PEDET 3.3V_7 73 74
71 72 75 GND_13 3.3V_9
73 GND_12 3.3V_8 74 <77> -SSD2_DTCT GND_14
75 GND_13 3.3V_9
<77> -SSD1_DTCT GND_14 77 76
79 PEG1 PEG2 78
77 76 PEG3 PEG4
10U_0603_6.3V6-M
79 PEG1 PEG2 78
PEG3 PEG4 DEREN_40-42381-067B3RHFL
@ 1 1
10U_0603_6.3V6-M
DEREN_40-42381-067B3RHFL
C489
@ 1 1 C490
.01U_0402_16V7-K
2@
C487
C488 2
PCIe RXP/RXN is using 2
.01U_0402_16V7-K
2@
PCIe RXP/RXN is using
polarity inversion function. polarity inversion function.
D71
VCC3B -DAS_MD2_SSD1 1 2 VCC3B
-SATALED <16>
D72
-PCIE_DETECT_SSD1 -DAS_MD2_SSD2 1 2 -PCIE_DETECT_SSD2 -PCIE_DETECT_SSD2 <16>
1
-PCIE_DETECT_SSD1 <16>
1
RB521CS-30GT2RA_VMN2-2 R275
R274 10K_0402_5%
10K_0402_5% TABLE
TABLE -PCIE_DETECT_SSD2 Device
1
2
D
1
D
PCIE_DETECT_SSD2 2 Q14
PCIE_DETECT_SSD1 2 Q13 -PCIE_DETECT_SSD1 Device G LSK3541G1ET2L_VMT3
PEDET (PE_DTCT) High SATA SSD
A PEDET (PE_DTCT) S A
S
High SATA SSD SATA Device GND
3
SATA Device GND
3
PCIe Device Open PCIe Device Open LOW PCIe SSD

LOW PCIe SSD

Issued Date 2015/07/16 Deciphered Date 2016/01/16 M.2 SATA/PCIE SSD CARD SLOT
Custom

Rev
0.1
5 4 3 2 1
5 4 3 2 1
Payton Common TYPE-B NGFF CCARD FOR WWAN

VCC3WAN
VCC3WAN
RF
VCC3WAN
3.2H CONNECTOR
2200P_0402_25V7-K
68P_0402_50V8-J
10U_0603_6.3V6M
0.1U_0402_25V6-K
1UF_0402_6.3V
1
1 1 1
1
C9362
C9361
C491
C492
@ C493
R277
JWWAN1 47K_0402_5%
1 2
<16> WWAN_CFG3
2
3 CONFIG_3 3.3VAUX1 4 2 2 2
2
D 5 GND1 3.3VAUX2 6 D
R278 1 2 0_0402_5% USBP3+_WWAN_C 7 GND2 FULL_CARD_POWER_OFF# 8 -WWAN_DISABLE
<15> USBP3+_WWAN USB_D+ W_DISABLE#1 -WWAN_DISABLE <83>
R276 1 2 0_0402_5% USBP3-_WWAN_C 9 10
<15> USBP3-_WWAN USB_D- GPIO9/LED1#/DAS/DSS#
11
GND3 NC 12
13 NC NC 14
15 NC KEY-B NC 16
17 NC NC 18
19 NC 20
21 GPIO_5 22
<19> WWAN_CFG0 CONFIG_0 GPIO_6
23 24
25 GPIO_11 GPIO_7 26 JSIM1
27 DPR GPIO_10 28 1
29 GND4 GPIO_8 30 UIM_RESET 5 VCC 4
31 PERn1/USB3.0-RX-/SSIC-RxN UIM-RESET 32 R279 1 2 200_0402_1% UIM_CLK VPP GND1 8
33 PERp1/USB3.0-RX+/SSIC-RxP UIM-CLK 34 UIM_DATA Micro SIM ConnGND2 9
35 GND5 UIM-DATA 36 UIM_PWR GND3 10
37 PETn1/USB3.0-TX-/SSIC-TxN UIM-PWR 38 2 GND4 11
39 PETp1/USB3.0-TX+/SSIC-TxP DEVSLP 40 3 RST GND5 12
41 GND6 GPIO_0 42 6 CLK GND6 13
43 PERn0/SATA-B+ GPIO_1 44 I/O GND7 14
PERp0/SATA-B- GPIO_2 GND8
47P_0402_50V8-J
1 4.7U_0402_6.3V6M
FTZ6.8EGT148_SC-74A5
45 46 15
47 GND7 GPIO_3 48 GND9 16
49 PETn0/SATA-A- GPIO_4 50 7 GND10 17
51 PETp0/SATA-A+ PERST# 52 Detection_Switch GND11
GND8 CLKREQ# 1
53 54 @
55 REFCLKN PEWake# 56 C494
57 REFCLKP NC1 58 TE_2229333-2
GND9 NC2
1
2
3
5
59 60 2
ANTCTRL0 COEX3 @
61 62 D26
63 ANTCTRL1 COEX2 64
65 ANTCTRL2 COEX1 66
4
ANTCTRL3 SIM_DETECT
1
51_0402_5%
C R10042 1 2 0_0402_5% 67 68 @ C
<16> -WWAN_RESET
C495 2
69 RESET# SUSCLK 70 R280
CONFIG_1 3.3VAUX3
3
71 72
@ D25 73 GND10 3.3VAUX4 74
75 GND11 3.3VAUX5
2
RCLAMP0502BPTCT_SC75-3 CONFIG_2
76 77
1
PEG1 PEG2
TE_2-2199119-2
@
TYPE-A NGFF CCARD FOR WLAN

VCC3WLAN_F VCC3WLAN
3.2H CONNECTOR
1
JWLAN1
0_0402_5% 1 2 F21
R282 1 2 USBP14+_WLAN_C 3 GND1 3.3VAUX1 4
<15> USBP14+_WLAN USB_D+ 3.3VAUX2 5A_32V_ERBRE5R00V
R283 1 2 USBP14-_WLAN_C 5 6
<15> USBP14-_WLAN
7 USB_D- KEY A LED#1
8
GND2 NC
0_0402_5% 9 10
2
NC NC
11 12 VCC3WLAN_F
NC NC
13 NC NC 14
15 16
NC LED#2
17 18
B 19 MLDIR_SENSE GND16 20 B
21 DP_ML3N DP_AUXN 22
23 DP_ML3P DP_AUXP 24
1UF_0402_6.3V
GND3 GND13 1
1
25 26
DP_ML2N DP_ML1N
C497
27 28 C496 C498 @
29 DP_ML2P DP_ML1P 30 0.1U_0402_25V6-K 10U_0603_6.3V6M
2
31 GND4 GND14 32 2
33 DP_HPD DP_ML0N 34
35 GND5 DP_ML0P 36
<15> PCIE3_WLAN_SLOT_TXP PETP0 GND15
37 38
<15> PCIE3_WLAN_SLOT_TXN PETN0 RESERVED1 -CL_RST_WLAN <16>
39 40
GND6 RESERVED2 CL_DATA_WLAN <16>
41 42
<15> PCIE3_WLAN_SLOT_RXP PERP0 RESERVED3 CL_CLK_WLAN <16>
43 44
<15> PCIE3_WLAN_SLOT_RXN PERN0 COEX3
45 46
47 GND7 COEX2 48
<20> PCIE2_CLK_100M_WLAN REFCLKP0 COEX1
49 50 SUSCLK_32K
<20> -PCIE2_CLK_100M_WLAN REFCLKN0 SUSCLK SUSCLK_32K <17,75>
51 52 -PLTRST_NEAR WLAN CARD LCFC P80 CARD LCFC UART CARD
GND8 PERST0# -PLTRST_NEAR <14,64,75,82,83,84>
-CLKREQ_PCIE2_WLAN 53 54
<20> -CLKREQ_PCIE2_WLAN CLKREQ0# W_DISABLE#2 BDC_ON <83>
-PCIE_WAKE 55 56 -WLAN_RF_KILL
<17,46,64,84> -PCIE_WAKE PEWAKE0# W_DISABLE#1 -WLAN_RF_KILL <83>
57 58 PIN54 BDC_ON CLK NC (RX NOT USED)
59 GND9 I2C_DATA 60
VCC3B 61 PETP1 I2C_CLK 62
63 PETN1 ALERT# 64 R611 1 2 0_0402_5% PIN64 RESERVED DATA UART_TX
GND10 RESERVED4 EC_P80DATA <77>
65 66
PERP1 PERST1#
1
67 68
10K_0402_5% 69 PERN1 CLKREQ1# 70 R609 1 @ 2 0_0402_5% R611 ASM NO_ASM
GND11 PEWAKE1# -VIDEO_THERM_ALERT <34,77>
1
R284 71 72
73 REFCLKP1 3.3VAUX4 74 @
75 REFCLKN1 3.3VAUX5 R608 R610 R609 NO_ASM ASM
2
GND12 100K_0402_5% 100K_0402_5%

76 77
2
PEG1 PEG2
2
A TE_2-2199119-3 A
@ D27 @ TO DETECT LCFC NGFF PORT80 CARD.
RCLAMP0502BPTCT_SC75-3 THORPE DOESN'T HAVE THIS LOGIC. LOGIC
PULL-DOWN ON PIN#64 IS JUST RESERVE.
1

Issued Date 2015/07/16 Deciphered Date 2016/01/16 M.2 WIRELESS CARD SLOT
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common
VCC3B VCC3B_UHS2
D D
R286
1 2
10U_0603_6.3V6-M
0.1U_0402_25V6-K
0.01_0603_LE_1%
1 1
C500
close to IC
C499
SD_CLK
2 2
6.8P_0201_25V8--J
VCC3_AUX_UHS2 1
C572
2@
VCC3B
R289
AV12 AV12
1 2
10U_0402_6.3V6-M
0.1U_0402_25V6-K
0.01_0603_LE_1% VCC3R3_SD VCC3B_UHS2
1 1 MS_INS# has internal pull up VCC3_AUX_UHS2
resisters 200k ohm.
C502
U23
2 C501 2 VCC3B_UHS2 11 30
3V3_IN SD_CD# -SD_CD <63>
C DV33_18 18 31 C
DV33_18 MS_INS#
1U_0402_10V6-K
AV12 10 32 R290 1 2 10K_0402_5%
AV12 WAKE#
close to IC 14
DV12S
C506
VCC3_AUX_UHS2
close to IC
15 SD_D1_RCLK_M_R R300 1 2 0_0402_5%
SP1 SD_D1_RCLK_M <63>
VCC3R3_SD 12 16 SD_D0_RCLK_P_R R299 1 2 0_0402_5%
Card_3V3 SP2 SD_D0_RCLK_P <63>
17 SD_CLK_R R296 1 2 0_0402_5%
SP3 SD_CLK <63>
27
3V3aux 19 SD_CMD_R R295 1 2 0_0402_5%
R298 SP4 SD_CMD <63>
2 1 RREF 9 20 SD_D3_R R294 1 2 0_0402_5%
RREF SP5 SD_D3 <63>
21 SD_D2_R R293 1 2 0_0402_5%
6.2K_0402_1% SP6 SD_D2 <63>
PCIE13_MEDIACARD_TXP 3 29
<16> PCIE13_MEDIACARD_TXP HSIP SP7 -SD_WPI <63>
PCIE13_MEDIACARD_TXN 4
<16> PCIE13_MEDIACARD_TXN HSIN
PCIE13_MEDIACARD_RXP C504 1 2 0.1U_0402_25V6-K PCIE13_MEDIACARD_RXP_C 7
<16> PCIE13_MEDIACARD_RXP HSOP VCC1R8_SD
PCIE13_MEDIACARD_RXN C505 1 2 0.1U_0402_25V6-K PCIE13_MEDIACARD_RXN_C 8 13 VCC1R8_SD
<16> PCIE13_MEDIACARD_RXN HSON SD_VDD2
AV12
Close to IC close to IC SD_LN1_P
22
SD_D1P <63>
PCIE0_CLK_100M_UHS2 5 23
<20> PCIE0_CLK_100M_UHS2 REFCLKP SD_LN1_M SD_D1M <63>
-PCIE0_CLK_100M_UHS2 6 24 SDREG2
<20> -PCIE0_CLK_100M_UHS2 REFCLKN SDREG2
0.1U_0402_25V6-K
4.7U_0402_6.3V6-M
0.1U_0402_25V6-K
B B
1 1 1 Zdiff = 100 ohm 25

SD_LN0_M SD_D0M <63>
C507
C508
C509
-PLTRST_FAR 1 26
<14,24,46,52,56,60> -PLTRST_FAR PERST# SD_LN0_P SD_D0P <63>
2 2 2
1U_0402_10V6-K
-CLKREQ_PCIE0_UHS2 2
<20> -CLKREQ_PCIE0_UHS2 CLK_REQ#
C503
R291
1 2 28 33
GPIO E-PAD
VCC3B_UHS2 10K_0402_5%
RTS5234S-GR_QFN32_4X4
VCC3_AUX_UHS2
1
10K_0402_5%
R292
2
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 MEDIA CARD CONTROLLER UHS-II
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common Normal type UHS-II SD Slot

Pin No SD Mode UHS II Mode
1 CD/DAT3
2 CMD
3 VSS1
4 VDD VDD1
Bottom View
5 CLK
6
7
VSS2
DAT0
UHS II Interface UHS I Inteface
RCLKP
8
9
DAT1 RCLKM 12345678 4 VDD1 3.3V 1 CD/DAT3
D 10
DAT2 9 7 RCLKP 2 CMD D
11 VSS3
12 D0P 8 RCLKM 3 VSS1
13 D0M
VSS4
10 VSS3 4 VDD 3.3V
14
15 VDD2 10 1314 17 11 D0P 5 CLK
16 D1M
D1P
1112 1516 12 D0M 6 VSS2
17
CD VSS5 13 VSS4 7 DAT0
WP 14 VDD2 1.8V 8 DAT1
15 D1M 9 DAT2
CARD DETECT 16 D1P
WRITE PROTECT
17 VSS5
VCC3R3_SD
VCC1R8_SD
JSD1
4 14
VDD_1 VDD_2 11
D0+ SD_D0P <62>
12
D0- SD_D0M <62>
15
D1- SD_D1M <62>
2 16
C <62> SD_CMD CMD D1+ SD_D1P <62> C
5 10
<62> SD_CLK CLK VSS_3 13
7 VSS_4 17
<62> SD_D0_RCLK_P DAT0/RCLK+/DAT VSS_5
8
<62> SD_D1_RCLK_M DAT1/RCLK-
9 20
<62> SD_D2 DAT2 GND_1
1 21
<62> SD_D3 CD/DAT3/RSV GND_2 22
GND_3 23
18 GND_4 24
<62> -SD_CD CARD_DETECT GND_5
19 25
<62> -SD_WPI WRITE_PROTECT GND_6
0.1U_0402_10V6-K
4.7U_0603_10V6-K
26
GND_7
0.1U_0402_10V6-K
4.7U_0603_10V6-K
1 3
VSS_1
C510
C511
6 1
VSS_2
C512
C513
TAISO_156-2000302612
2
@ 2
CD : Low => Insertion Card

High => No Card
WP : Low => Write Protection on
High => Write Protection off or No Card
B B
A EMC A
@ @
SD_CLK R643 1 2 0_0402_5% C573 1 2 10P_0402_50V8-J Title
Issued Date 2015/07/16 Deciphered Date 2016/01/16 MEDIA CARD INTERFACE UHS-II
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Walter Unique
EXC POWER IC has internal PU for
PIN#9(-CPUSB), PIN#10(-CPPE)
D D
VCC3M VCC3AUX_EXC VCC3M
VCC3_EXC VCC3AUX_EXC VCC1R5_EXC
100K_0402_1%
10K_0402_5%
10K_0402_5%
10K_0402_5%
100K_0402_1%
1
1
VCC3B VCC5B @ @ @
R301 R304 R305 R302 R303
2
JEXC1
10 2
+1.5V_2 USBD- USBP12-_EXP_SLOT <15>
9 3
0.5A_32V_ERBRD0R50X
+1.5V_1 USBD+ USBP12+_EXP_SLOT <15>
7.87K_0402_1%
12 21
+3.3VAUX PERn0/SSRX- PCIE1_EXP_SLOT_RXN <15>
1
F17 22
PERp0/SSRX+ PCIE1_EXP_SLOT_RXP <15>
R9906
15 24
+3.3V_2 PETn0/SSTX- PCIE1_EXP_SLOT_TXN <15>
14 25
+3.3V_1 PETp0/SSTX+ PCIE1_EXP_SLOT_TXP <15>
SMART CARD 7 EXP_CONN_7
2
SMBCLK 8 EXP_CONN_8
SMBDATA
JSC1 18
REFCLK- -PCIE6_CLK_100M_EXPCARD <20>
1 19
<18> -SC_DTCT 1 REFCLK+ PCIE6_CLK_100M_EXPCARD <20>
2
3 2
<15> USBP11+_SMART_CARD 3
4 17 -CPPE EXC_PWRG
<15> USBP11-_SMART_CARD 4 CPPE#
5
5
2
C 6 13 -PERST C
G
7 6 PERST# LSK3541G1ET2L
8 7 1 4 -CPPUSB Q17
.1U_0402_16V4-Z
.1U_0402_16V4-Z
.1U_0402_16V4-Z
9 8 20 GND1 CPUSB#
9 GND2 EXC_PWRG_CONN
D
10 11 1 1 1 23 16 3 1
10 GND1 GND3 CLKREQ# -CLKREQ_PCIE6_EXPCARD <20>
12 26
GND2 C516 C515 C9340 27 GND4 11
GND5 WAKE# -PCIE_WAKE <17,46,61,84>
DRAPH_BT5P0101-1001H 28
2 2 2 29 GND6 5
ME@ GND7 USB3#
30 VCC3B
GND8 6
RESERVED
TAISO_5-421507001000-6 R10020 1 2 10K_0402_5%
@
VCC3M VCC1R5B VCC1R5_EXC VCC3_EXC VCC3AUX_EXC
B B
U24
17 15
2 AUXIN AUXOUT 3
12 3.3VIN 3.3VOUT 11
1.5VIN 1.5VOUT
20 8 -PERST
<14> -EXC_PWR_SHDN SHDN# PERST#
1 10 -CPPE
<77,83,84,95,98,99,100,104> B_ON STBY# CPPE#
6 9 -CPPUSB
<14,61,75,82,83,84> -PLTRST_NEAR SYSRST# CPUSB#
19
OC#
4
5 NC_1 18 EXC_PWRG
13 NC_2 RCLKEN
NC_3
1U_0402_10V6-K
.01U_0402_25V7-K
14 7
NC_4 GND
1000P_0402_50V7-K
1000P_0402_50V7-K
1000P_0402_50V7-K
1U_0603_10V6-K
1U_0603_10V6-K
2.2U_0603_10V7-K
1 1 16 21
NC_5 GND_PAD
1 1 1 1 1 1
C517 C518 TPS2231MRGPR-3_QFN20_4X4
C519 C9152 C521 C9153 C523 C9154
2 2
2 2 2 2 2 2
EXPRESS POWER SW Table

Supplier Vendor P/N LCFC P/N
A A
TI TPS2231MRGPR-3
NUVOTON W83L351YG V.ASA
U24
ROHM BD4157MUV-GE2
ROHM BD4156MUV-SGE2
Issued Date 2015/07/16 Deciphered Date 2016/01/16 EXPRESS SLOT / SMART CARD
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Walter Unique
VCC5B
D D
Design note:
RF solution, close to SATA conn.
1
C525
47P_0402_50V8-J
1
@
F19 2
1A_32V_ERBRD1R00X
2
JHDD1
AC Cap for TX side placed on PCH side check OK, 0923 conn list
1
2 1
<16> SATA2_HDDBAY1_TXP 2
3
<16> SATA2_HDDBAY1_TXN 3
4
C9189 1 2 0.01U_0402_25V7-K SATA2_RXN_C 5 4
<16> SATA2_HDDBAY1_RXN 5
C9190 1 2 0.01U_0402_25V7-K SATA2_RXP_C 6
<16> SATA2_HDDBAY1_RXP 6
7
8 7
9 8
10 9
11 10
12 11
C <77> -HDD1_DTCT 12 C
13
VCC5B_HDD 14 13
15 14
16 15
17 16
18 17
19 18 21
20 19 GND1 22
20 GND2
I-PEX_20374-020E-31
@
0.01U_0402_25V7-K
10U_0603_6.3V6-M
2@ 1
C9192
C9191
1 2
SATA HDD board to cable CONN
B B
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 SATA HDD CONN
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Walter Unique
D D
VCC5B
VCC5B
0.1U_0402_25V6-K
2
0.1U_0402_25V6-K 1 2
C531
C530 1UF_0402_6.3V C532
1
2 1
Need to confirm about DTCT PIN

C C
VCC5B
1A_32V_ERBRD1R00X
2
F9
1
check OK, 0923 conn list
JHDD2
1
2 1
<16> SATA3_HDDBAY2_TXP 2
3
<16> SATA3_HDDBAY2_TXN 3
4
SATA3_RXN_CONN 4
<16> SATA3_HDDBAY2_RXN C533 1 2 0.01U_0402_25V7-K 5
SATA3_RXP_CONN 5
<16> SATA3_HDDBAY2_RXP C534 1 2 0.01U_0402_25V7-K 6
7 6
8 7
9 8
10 9
B 11 10 B
12 11
<77> -HDD2_DTCT 12
13
14 13
15 14
16 15
17 16
18 17
SATA HDD Board to Cable CONN 19 18 21
20 19 GND1 22
20 GND2
I-PEX_20374-020E-31
@
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 SATA HDD B2C CONN
5 4 3 2 1
5 4 3 2 1
VCC3_SUS Max 0.4A VCC1R8BA
VCC3B VCC3SW R309 FL2 MPZ1608S331AT_2P VCC5B Max 1.5A
1 2 1 2 1 2 1 2 R310 1 2 0_0603_5%
1
0_0603_5%
10U_0603_10V6-K
10U_0603_10V6-K
10U_0603_10V6-K
10U_0402_6.3V6-M
0.1U_0402_10V6-K
0.1U_0402_10V6-K
2.2U_0402_10V6-K
2.2U_0402_10V6-K
R308 R10070 0_0603_5%
R655
10U_0603_10V6-K
10U_0603_10V6-K
10U_0603_10V6-K
0.1U_0402_10V6-K
0.1U_0402_10V6-K
0.1U_0402_10V6-K
0_0603_5% 0_0603_5% 1 1 1 1 1 1 1 1
C537
C538
C540
C541
C542
C543
C544
C545
0.1U_0402_10V6-K
1 1 1 1 1 1
C535
C536
C546
C547
C548
C549
VCC3B 1
C539
2
2 2 2 2 2 2 2 2
2 2 2 2 2 2
2
100K_0402_1%
100K_0402_1%
AGND AGND AGND
1
AGND AGND Place next to CODEC
R313
R314
D
SENSE A: Pin 9 200K : HP Detect Analog Plane MPZ1608S331AT_2P D
SENSE B: Pin 8 200K : Dock Mic Detect FL3 VCC5B Max 1.5A
100K : Dock HP Detect 1 2 R318 1 2 0_0603_5%
2
Analog Plane R9979
10U_0603_10V6-K
10U_0603_10V6-K
0.1U_0402_10V6-K
0.1U_0402_10V6-K
Max 0.25A VCC5BA
R337 1 2 SENSE_A 1 2 1 1 1 1
69> SENSE_A_SYS_HP
C553
C554
C550
C555
10U_0603_10V6-K
0.1U_0402_10V6-K
200K_0402_1%
10
18
19
22
24
29
31
44
51
46
45
1 1 0_0402_5%
C551
C552
R446 1 2 100K_0402_1% SENSE_B PCB trace width of Mic1-R/Mic1-L(SLEEVE/RING2) are U25
69> SENSE_B_DOCK_HP required at least 40 mil for HP crosstalk consideration 2 2 2 2
DVDD
AVDD1
LDO3-CAP
AVDD2/CPVDD
PVDD2
PVDD1
VD33STB
DVDD-IO
LDO2-CAP
CPVPP
CPVEE
LDO1-CAP
and its length should be as short as possible
R341 1 2 200K_0402_1% 2 2
69> SENSE_B_DOCK_MIC
Analog Plane VCC3B
Place next to CODEC
AGND
HP_L_JACK R315 1 2 113_0402_1% HP_L_JACK_R 32 1 0_0402_5% 1 2 R316 DOCK_I2S_LRCLK
<68> HP_L_JACK HPOUT-L I2S-LRCK/GPIO9 DOCK_I2S_LRCLK <74>
HP_R_JACK R317 1 2 113_0402_1% HP_R_JACK_R 33 2
<68> HP_R_JACK HPOUT-R GPIO1/DMIC-CLK2/SPDIF-OUT/I2S-IN-JD
34 3 0_0402_5% 1 2 R319 DOCK_I2S_SD_O
LINE1-R GPIO6/I2S-OUT DOCK_I2S_SD_O <74>
35 4 Test_Point_12MIL 1 TP991
LINE1-L GPIO2/DMIC-DATA2/I2S-OUT-JD
36 5 DOCK_I2S_SD_I
<70> RING2 MIC1-L/RING2 GPIO5/I2S-IN DOCK_I2S_SD_I <74>
37 6 1
100K_0402_5% 2 R495
<70> SLEEVE MIC1-R/SLEEVE GPIO0/IRQOUT/HD-I2S-SEL
8 SENSE_B
BEEP_MIX_ATT C556 1 2 0.1U_0402_10V6-K 23 I2S-OUT-JD/MIC-JD
<72> BEEP_MIX_ATT PCBEEP 9 SENSE_A
HP-JD/LINE-JD
C 47 11 C
<71> CODEC_SP_OUTL+ SPK-OUT-LP I2C-DATA
48 12
Speaker 4 ohm ==> 40 mils <71> CODEC_SP_OUTL- SPK-OUT-LN I2C-CLK
Speaker 8 ohm ==> 20 mils 49 13 HDA_BCLK
<71> CODEC_SP_OUTR- SPK-OUT-RN AUDIOLINK_BCLK/BCLK HDA_BCLK <17>
50 14
<71> CODEC_SP_OUTR+ SPK-OUT-RP AUDIOLINK_SYNC/LRCK HDA_SYNC <17>
15 -HDA_RST
AUDIOLINK_RESETO/MCLK -HDA_RST <17>
21 16 HDA_SDIN0_R 33_0402_5% 1 2 R320 HDA_SDIN0
VBG/VREF1 AUDIOLINK_SDATA-IN/DOUT HDA_SDIN0 <17>
C557 1 2 2.2U_0603_6.3V6-K 25 17 HDA_SDO
CBN2 AUDIOLINK_SDATA-OUT/DIN HDA_SDO <17>
26
CBP2 52 -SPK_MUTE
EAPD+PD#/GPIO11 -SPK_MUTE <75>
C558 1 2 2.2U_0603_6.3V6-K 27
CBP1 53 0_0402_5% 1 2 R677 EMC@ MIC_CLK
DMIC-CLK1 MIC_CLK <40>
28
CBN1 54 MIC_DATA
DMIC-DATA1 MIC_DATA <40>
30
CPVREF 55 0_0402_5% @1 2 R321 DOCK_I2S_MCLK
GPIO8/I2S-MCLK/SPDIF-IN DOCK_I2S_MCLK <74>
38
<70> MIC1_VREFOL MIC1-VREFO-L/AGPO-0 56 0_0402_5% 1 2 R322 DOCK_I2S_BCLK
GPIO7/I2S-BCLK DOCK_I2S_BCLK <74>
39
<70> MIC1_VREFOR MIC1-VREFO-L/AGPO-1 0_0402_5% 1 2 R661
I2S_CTRL <74>
40
LINE1-VREFO
41
Thermal_pad
MIC1-CAP DOCK_I2S_SD_I R323 2 1 10K_0402_0.5%
43
AVSS1
AVSS2
VREF -HDA_RST R324 @1 2 47K_0402_5%
33P_0402_50V8-J
33P_0402_50V8-J
33P_0402_50V8-J
33P_0402_50V8-J
10U_0402_6.3V6-M
10U_0402_6.3V6-M
B B
2.2U_0603_6.3V6-K
0.1U_0603_6.3V7-K
1 1 1 1 1 1 1 1 HDA_SDO C560 @ 1 2 47P_0402_25V8-J

C559
C561
C562
C563
C564
C565
C566
C567
ALC3268-CG_QFN56_7X7
42
20
57 -SPK_MUTE R325 2 1 10K_0402_0.5%

2 2 2 2 2 2 2 2 MIC_CLK C568 1 2 33P_0402_50V8-J
MIC_DATA C569 1 2 33P_0402_50V8-J

@ @ @ @
Near Codec Place next to CODEC

AGND
Analog Plane
VCC1R8B VCC1R8BA VCC5B VCC5BA

R327 R328
1 2 1 2 PLACE UNDER ALC3268
R326
0.01_0603_LE_1% 0.01_0603_LE_1% 1 2
10U_0603_10V6-K
10U_0603_10V6-K
10U_0603_10V6-K
10U_0603_10V6-K
0.1U_0402_10V6-K
0.1U_0402_10V6-K
0.1U_0402_10V6-K
0.1U_0402_10V6-K
1 1 1 1 1 1 1 1
0_0402_5%
C575
C576
C577
C578
C579
C580
C581
C582
EMC@
2 2 2 2 2 2 2 2 EMC
AGND
C583 @ C584 @ C570 @ @ @
1 2 1 2 1 2 HDA_BCLK R642 1 2 0_0402_5% C484 1 2 10P_0402_50V8-J
A 0.01U_0402_25V7-K 0.01U_0402_25V7-K 0.01U_0402_25V7-K A
AGND AGND
AGND

Issued Date 2015/07/16 Deciphered Date 2016/01/16 AUDIO ALC3268
Custom
Date:
NM-A451
Friday, October 02, 2015 Sheet 67 of 116
Rev
0.1
5 4 3 2 1
5 4 3 2 1
Walter Unique
NEAR AUDIO CONN
FL8
HP_L_JACK 1 2
<67> HP_L_JACK
TDK_MMZ1005Y152CT_2P
D D
EMC@
FL9
HP_R_JACK 1 2
<67> HP_R_JACK
TDK_MMZ1005Y152CT_2P
1000P_0402_25V7-K
1000P_0402_25V7-K
EMC@
2 2
2
R329 @ R330 @ C9344 C586
220_0402_5% 220_0402_5% EMC@ EMC@
1 1
1
AGND
MIC_SLEEVE <70>
MIC_RING2 <70>
WIDE AND SHORT PATTERN
C C
VCC3B
1
R9808
JHP1 10K_0402_5%
10
9 GND4
2
8 GND3 3 MIC_RING2
7 GND2 M/G
GND1
2 HP_R_JACK_conn
R
1 HP_L_JACK_conn
L
6
B TRANSFER B
5 HP_JACK_SYS D28
BREAK HP_JACK_SYS <69>
DAN222MGT2L_VMD3 HP_JACK_IN
HP_JACK_IN <75>
2
4 MIC_SLEEVE 1
G/M 3
VCC3B
100K_0402_5%
VCC3B
2
LOTES_AJAK0046-P002A
RSB5.6SGTE61_SC-79-2-2
@
1
2
D32 D33
EMC@ D30
EMC@ EMC@ R332

EMC@ D29
R333 1
4.7K_0402_5%
2
C587 470K_0402_5%
1
2
2
R335
1 2
R334
1
100K_0402_5%
2
2
1U_0402_10V6K
1
1
EMC@
AGND D31
EMC@ SENSE_B_DOCK_HP_CTRL <69>
1
2 Q18
<74> -DOCK_HP_DCT
DTC115EMGT2L_VMT3
3
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 AUDIO CONNECTOR
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common
D D
SENSE_A_SYS_HP
SENSE_A_SYS_HP <67>
1
D
HP_JACK_SYS 22K_0402_5% 1 2 R573 2 Q19
<68> HP_JACK_SYS G LSK3541G1ET2L_VMT3
1 S
3
C588
2.2U_0402_10V6-K
@
2
AGND
C C
SENSE_B_DOCK_HP
SENSE_B_DOCK_HP <67>
1
D
SENSE_B_DOCK_HP_CTRL 22K_0402_5% 1 2 R585 2 Q39
<68> SENSE_B_DOCK_HP_CTRL G LSK3541G1ET2L_VMT3
1 S
3
C623
2.2U_0402_6.3V6-M
@
2
AGND
B VCC3B VCC3B B
1
SENSE_B_DOCK_MIC <67>
R340 R339
10K_0402_5% 100K_0402_5%
2
1
D
R342 1 2 22K_0402_5% 2 Q21
1
3
2 Q20
<74> -DOCK_MIC_DCT
DTC115EMGT2L_VMT3
1000P_0402_25V7-K
1
3
C589
AGND
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 AUDIO JACK SENSE
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common
<67> MIC1_VREFOR
1
1
C590 R574
D 1UF_0402_6.3V 2.2K_0402_5% D
2
L19
AGND 1 2
BK1005HS102-T_2P
EMC@
<67> MIC1_VREFOL
1
C591
1UF_0402_6.3V R577
2.2K_0402_5%
2
AGND
L20
1 2
BK1005HS102-T_2P
EMC@
C C
MIC_SLEEVE R9980 1 2 0_0402_5%

<68> MIC_SLEEVE SLEEVE <67>
1
1 EMC@
R578 @ C592
0_0402_5% 1000P_0402_25V7-K
PCB trace width of Mic1-R/Mic1-L(SLEEVE/RING2) are 2
2
required at least 40 mil for HP crosstalk consideration
and its length should be as short as possible
AGND
MIC_RING2 R9981 1 2 0_0402_5%

<68> MIC_RING2 RING2 <67>
1000P_0402_25V7-K
1
B B
2
R576 @ EMC@
0_0402_5% C593
1
2
@ R575 1 2 0_0402_5%
AGND
AGND
NEAR EXT MIC CONN

EMC@ C594 1 2 0.01U_0402_25V7-K
AGND
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 AUDIO EXT MIC I/F
5 4 3 2 1
5 4 3 2 1
Payton Common
D D
EMC@ FL10 BLM18SG260TN1D_2P

1 2 SP_OUTR+
<67> CODEC_SP_OUTR+
FL11 BLM18SG260TN1D_2P
EMC@ 1 2 SP_OUTR-
<67> CODEC_SP_OUTR-
EMC@ FL12 BLM18SG260TN1D_2P

1 2 SP_OUTL-
<67> CODEC_SP_OUTL-
FL13 BLM18SG260TN1D_2P
EMC@ 1 2 SP_OUTL+
<67> CODEC_SP_OUTL+
2 2 2 2
1000P_0402_16V7-K
1000P_0402_16V7-K
1000P_0402_16V7-K
1000P_0402_16V7-K
EMC@
EMC@
EMC@
EMC@
C595
C596
C597
C598
1 1 1 1
Speaker 4 ohm ==> 40 mils
Speaker 8 ohm ==> 20 mils
PLACE NEAR Codec
C C
JSPK1
ALC3268 speaker output part SP_OUTR+

SP_OUTR-
1
2 1
SP_OUTL- 3 2 5
SP_OUTL+ 4 3 GND1 6
4 GND2
2 2 2 2 HIGHS_WS32041-S0471-HF
EMC@ EMC@ EMC@ EMC@
@
C599 C600 C601 C602
220P_0402_50V7-K 220P_0402_50V7-K 220P_0402_50V7-K 220P_0402_50V7-K
1 1 1 1
PLACE, NEAR SPEAKER CONNECTOR
B B
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 AUDIO SPEAKER
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common
D D
D34
EC_SPKR 2 1
<75> EC_SPKR
D35
PCH_SPKR 2 1
<17> PCH_SPKR
1
R350
33K_0402_5%
2
C C
2
R351
10K_0402_5%
1
BEEP_MIX_ATT
BEEP_MIX_ATT <67>
1
D
-BEEP_ENABLE 2 Q22
<75> -BEEP_ENABLE G LSK3541G1ET2L_VMT3
3
B B
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 AUDIO BEEP
Custom 0.1
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 SMART AMP
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common
DOCK_DCIN20 VCC3SW
VCC3B
R580 2 1 4.7K_0402_5% DOCKID3

R581 2 1 4.7K_0402_5% DOCKID2
1
33K_0402_5%
R582 2 1 4.7K_0402_5% DOCKID1
R365
R583 2 1 4.7K_0402_5% DOCKID0
check OK on ME list
-PWRSHUTDOWN and DISCHARGE JDOCK1A @
are not used in Thorpe. @
2
Payton needs these signals
because system AC adapter 70 1 -DOCKED0
69 GND_1 DOCKED0# 2 DOCK_MDI_0+
can be attached even when docked. RESERVE_7 DOCK_MDI_0P DOCK_MDI_0+ <57>
68 3 DOCK_MDI_0-
NC DOCK_MDI_0N DOCK_MDI_0- <57>
67 4
D 66 DOCK_DCIN20 GND_5 5 DOCK_MDI_1+ D
NC will be update symbolDOCK_MDI_1P DOCK_MDI_1+ <57>
-PWRSWITCH 65 6 DOCK_MDI_1-
<40,83,84> -PWRSWITCH DOCK_PWR_SW# DOCK_MDI_1N DOCK_MDI_1- <57>
DOCK_I2S_MCLK 64 7
<67> DOCK_I2S_MCLK DOCK_I2S_MCLK GND_6
DOCK_I2S_SD_I 63 8 DOCK_MDI_2+
<67> DOCK_I2S_SD_I DOCK_I2S_SD_I DOCK_MDI_2P DOCK_MDI_2+ <57>
DOCK_I2S_SD_O 62 9 DOCK_MDI_2-
<67> DOCK_I2S_SD_O DOCK_I2S_SD_O DOCK_MDI_2N DOCK_MDI_2- <57> VCC3B
DOCK_I2S_BCLK 61 10
<67> DOCK_I2S_BCLK DOCK_I2S_BCLK GND_7
DOCK_I2S_LRCLK 60 11 DOCK_MDI_3+
<67> DOCK_I2S_LRCLK DOCK_I2S_LRCLK DOCK_MDI_3P DOCK_MDI_3+ <57>
-DOCK_HP_DCT 59 12 DOCK_MDI_3-
<68> -DOCK_HP_DCT DOCK_HP_DCT# DOCK_MDI_3N DOCK_MDI_3- <57>
-DOCK_MIC_DCT 58 13
<69> -DOCK_MIC_DCT DOCK_MIC_DCT# GND_8
57 14
RESERVE_1 RESERVE_5
2
-PWRSHUTDOWN 56 15
<85,86,88> -PWRSHUTDOWN #DOCK_PWRSHUTDOWN RESERVE_6
DISCHARGE 55 16 DOCK_DP_HPD
<84,85> DISCHARGE DOCK_DISCHARGE DOCK_DP0_HPD DOCK_DP_HPD <43>
-DOCK_PWRDCT 54 17 R366
<87> -DOCK_PWRDCT #DOCK_PWRDCT DOCK_DP0_DGL_DCT
53 18 100K_0402_5%
52 DOCK_PWRGOOD DOCK_DP0_DDC_DATA 19
<84> -PWRON_DOCK
1
DOCKID3 51 DOCK_PWRON# DOCK_DP0_DDC_CLK 20
<14> DOCKID[3:0] DOCK_ID3 GND_9
DOCKID2 50 21
DOCK_ID2 DOCK_DP0_AUXN DOCK_AUXN <43>
DOCKID1 49 22
DOCK_ID1 DOCK_DP0_AUXP DOCK_AUXP <43>
DOCKID0 48 23
ACDC_ID 47 DOCK_ID0 GND_10 24 DOCK_DP3N_C C625 1 2 0.1U_0402_10V7-K
<76,86> ACDC_ID DOCK_ACDC_ID DOCK_DP0_LANE3N DOCK_DP3N <43>
2
DOCK_CONSUMP 46 25 DOCK_DP3P_C C626 1 2 0.1U_0402_10V7-K
<88> DOCK_CONSUMP DOCK_CONSUMP DOCK_DP0_LANE3P DOCK_DP3P <43>
45 26
44 GND_2 GND_11 27 DOCK_DP2N_C C627 1 2 0.1U_0402_10V7-K R367
<19> USB3P4_DOCK_TXP DOCK_USB_SS_TXP DOCK_DP0_LANE2N DOCK_DP2N <43>
<19> USB3P4_DOCK_TXN 43 28 DOCK_DP2P_C C628 1 2 0.1U_0402_10V7-K 100K_0402_5%
DOCK_USB_SS_TXN DOCK_DP0_LANE2P DOCK_DP2P <43>
42 29
1
41 GND_3 GND_12 30 DOCK_DP1N_C C629 1 2 0.1U_0402_10V7-K
<19> USB3P4_DOCK_RXP DOCK_USB_SS_RXP DOCK_DP0_LANE1N DOCK_DP1N <43>
<19> USB3P4_DOCK_RXN 40 31 DOCK_DP1P_C C630 1 2 0.1U_0402_10V7-K
DOCK_USB_SS_RXN DOCK_DP0_LANE1P DOCK_DP1P <43>
39 32
38 GND_4 GND_13 33 DOCK_DP0N_C C631 1 2 0.1U_0402_10V7-K
<15> USBP4+_DOCK DOCK_USB_SS_DP DOCK_DP0_LANE0N DOCK_DP0N <43>
<15> USBP4-_DOCK 37 34 DOCK_DP0P_C C632 1 2 0.1U_0402_10V7-K
DOCK_USB_SS_DN DOCK_DP0_LANE0P DOCK_DP0P <43>
36 35 -DOCKED0
DOCKED2# DOCKED1#
C C
TE_2129525-6 NEAR DOCK CONN DOCK_PWR20_IN
check OK on ME list
JDOCK1B @
D36
DOCK_PWR20 DOCK_PWR20_IN 71 73
1 2 I2S_CTRL PWR20 SHELL_1 74
Q23 I2S_CTRL <67> SHELL_2 75
SI7149DP-T1-GE3_POWERPAK8-5 RB521CS-30GT2RA_VMN2-2 SHELL_3 76
1 SHELL_4 77
D37 SHELL_5
2 78
3 1 2 -DOCK_ATTACHED_20 SHELL_6 79
5 SHELL_7 80
1SS400CMT2R SHELL_8 81
72 SHELL_9 82
4
GND_14 SHELL_10
1
1
R368
1
200K_0402_5% C633
R369 0.1U_0402_25V4Z
100_0402_5% 2
VCC3M
2
R370 1 R371 2
-DOCK_ATTACHED_20 1 2 100K_0402_5% TE_2129525-6
D39
100K_0402_5% 3 -DOCK_ATTACHED_3M
-DOCK_ATTACHED_3M <83>
1
DCIN_PWR20_F 2 -DOCK_ATTACHED_AUX
-DOCK_ATTACHED_AUX <57>
B DAN222MGT2L_VMD3 B
1
R372
1M_0402_5%
DCIN_PWR20_F DCIN_PWR20_F VCC3SW

D40
2
2 1
<86,88> -DOCK_ATTACHED_BAT_OP
2
1SS400CMT2R
1
R373
1
R375 R376
R374 1M_0402_5% 1M_0402_5% 100K_0201_5%
1M_0402_5%
1
2
2
DISCHARGE2
DISCHARGE2 <86>
2
LSK3541G1ET2L_VMT3
Q24
1
D
2
1
LSK3541G1ET2L_VMT3
LSK3541G1ET2L_VMT3
Q25 Q26 G
1
1
D D R379
LSK3541G1ET2L_VMT3
-DOCK_ATTACHED_BAT_OP 2 R377 2 R378 Q27 S 0_0402_5%
3
1
G 1M_0402_5% G 1M_0402_5% D
@
2
2
S S G
3
2
S
3
A A
DISCHARGE

Issued Date 2015/07/16 Deciphered Date 2016/01/16 DOCKING CONNECTOR
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common VCC3B VCC3_SUS

VCC3M
1
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
4.7K_0201_5%
4.7K_0201_5%
R566
R565
R564
R380
R381
R382
R383
R384
R388
U27A
2
D D
DRV[17:0] <78>
<84> -EC_RESET F1 L11 DRV0

RESETI# KSO0 B7 DRV1
KSO1 E6 DRV2
B3 KSO2 B6 DRV3
<17,61> SUSCLK_32K 32KHZ_IN/GPIO165 KSO3 H12 DRV4
J5 KSO4 G10 DRV5
<19> -KBRC KBRST KSO5 G9 DRV6
KSO6 H13 DRV7
K6 KSO7 C6 DRV8
<23> -EC_SCI EC_SCI# KSO8 C7 DRV9
N7 KSO9 B5 DRV10
<23> -EC_WAKE SMI# KSO10 H10 DRV11
KSO11
HOST I/F
<19,83> -SUS_STAT H6 H11 DRV12
LPCPD# KSO12 A5 DRV13
L5 KSO13 L13 DRV14
<17,83> -CLKRUN CLKRUN# KSO14 N12 DRV15
N5 KSO15 M11 DRV16
<19,83> IRQSER SER_IRQ KSO16/GPIO152 D5 DRV17
KSO17/GPIO175
Keyboard/TrackPoint
M5 VCC3M VCC3SW VCC3B
64,82,83,84> -PLTRST_NEAR LRESET# SENSE[7:0] <78>
<19,83> -LPC_FRAME L6 N13 SENSE0

LFRAME# KSI0
100K_0201_5%
100K_0201_5%
20K_0201_5%
100K_0201_5%
J6 SENSE1
KSI1
1
<19> LPCCLK_EC_24M N6 N8 SENSE2
PCI_CLK KSI2
R389
R390
R391
R386
J11 SENSE3
LPC_AD0 M6 KSI3 J12 SENSE4
LPC_AD1 M7 LAD0 KSI4 J13 SENSE5
LPC_AD2 L7 LAD1 KSI5 M12 SENSE6
2
LPC_AD3 K7 LAD2 KSI6 M13 SENSE7
LAD3 KSI7
C C
<19,83> LPC_AD[3:0]
C2
VCI_IN2#/GPIO161 -HOTKEY <78>
<87> M_TEMP 1 R392 2 K3 M9

ADC0/GPIO200 PWM0/GPIO053 KBD_BL_PWM <78>
1K_0201_5%
E7 A6 -KBD_BL_DTCT <78>
<87> I2C_DATA_BT SMB00_DATA GPIO036
A7
<87> I2C_CLK_BT SMB00_CLK
Battery
F11 R393 1 2 33_0201_5%
PS2_CLK0A/GPIO114 IPDCLK <79>
<88> -CHG_PROCHOT H7
GPIO223 K13 R394 1 2 33_0201_5%
PS2_DAT0A/GPIO115 IPDDATA <79>
<87> BAT_FET_HOT K1
ADC1/GPIO201
J7
GPIO052 -PAD_RESET <79>
R395 1 2 100_0201_5% E8
<88> I2C_DATA_CHARGE SMB02_DATA
R396 1 2 100_0201_5% B8 A13
<88> I2C_CLK_CHARGE SMB02_CLK GPIO133 TP4_RESET <78,79>
1 C12
GPIO134 BYPASS_PAD <79>
L4
C287 @ ADC4/GPIO204
0.1U_0201_6.3V6-K R433 1 2 2.2K_0201_5% -I_AM_WALTER G7
2 GPIO224
EC changes thermal table C9 VGA_BLON <41>
based on "-I_AM_WALTER" bit. GPIO143/SMB04_DATA
LCD
A8
GPIO144/SMB04_CLK BACKLIGHT_ON <42>
A4
<40> -LEDLOGO LED0/GPIO156
F5
<40> -LEDPWR LED1/GPIO157 C11
GPIO145/JTAG_TDI BDC_ON_R <83>
Wireless
C3 A11
B <78> -LEDMICMUTE GPIO024 GPIO146/JTAG_TDO -WWAN_DISABLE_R <83>
B
D12 C10
<78> -LED_MUTE GPIO035 GPIO147/JTAG_CLK -WLAN_RF_KILL_R <83>
LED
F6
<78> -LEDFNLOCK GPIO034
H2
<78> -LEDCAPSLOCK GPIO221 J8
PWM2/GPIO055 EC_SPKR <72>
LED_AC_ADAPTER_ON C5 K5
GPIO225 GPIO166 -BEEP_ENABLE <72>
LED_AC_ADAPTER_CHG
Audio
H1 D10
GPIO226 GPIO171/MSDATA -SPK_MUTE <67>
E10 HP_JACK_IN <68>
GPIO170/MSCLK
220P_0201_25V7-K
220P_0201_25V7-K
100K_0201_5%
100K_0201_5%
4700P_0201_6.3V7-K
1 1 1
1
C634
C635
C636
MEC1653
R398
R385
2 2 2
YELLOW
2
R149 LED1
LED_AC_ADAPTER_CHG 1 2 2 1
470_0402_5% Thorpe has 0 ohm jumpers on MSDATA/MSCLK

3 but it's not required on payton because
LNV/LCFC won;t use it.(CT_20140903)
R568 12-22A/S2G6C-A30/2C ORG/YEL/GREEN
LED_AC_ADAPTER_ON 1 2
300_0402_1%
A A
Place near DC-IN GREEN
CONNECTOR (MB EDGE)
EMC
@ @ Title
LPCCLK_EC_24M R641 1 2 0_0402_5% C458 1 2 10P_0402_50V8-J Security Classification LC Future Center Secret Data
Issued Date 2015/07/16 Deciphered Date 2016/01/16 MEC1653L(1/3)
Custom 0.1
5 4 3 2 1
5 4 3 2 1
VCC3M
Payton Common VCCSTG
1
1
2
VCC3M
100K_0201_5%
100K_0201_5%
100K_0201_5%
750_0201_1%
10K_0201_5%
10K_0201_5%
10K_0201_5%
D41
R406 @
R399
R400
R401
R402
R403
R404
R405
510_0201_5%
@
1
100K_0201_5%
2.2K_0201_5%
2.2K_0201_5%
2
1
1
@ R410 1 2
-PROCHOT <7,91>
R407
R408
R409
Q28
LSK3541G1ET2L_VMT3
1
D 75_0201_1%
PROCHOT_EC 2
47P_0201_25V8
G
2
U27B 1
1
100K_0201_5%
C637
D
S D
3
R411
Sensor
<84> -PWRSW D7 D8 1 R570 2 22_0201_5%
GPIO127/A20M SMB01_DATA/GPIO005 I2C_DATA_GSENSE <81> 2
G2 C8 1 R569 2 22_0201_5%
<17> -PWRSW_EC I2C_CLK_GSENSE <81>
2
GPIO106 SMB01_CLK/GPIO006
Damper resisters to fine- to/from APS sensor
RB521CS-30GT2RA_VMN2-2 tune I2C signals.
<84,88> -EXTPWR D42 1 2 L9

GPIO001/PWM4
<74,86> ACDC_ID 1 R412 2 L2 M1 FAN_ID_CPU <80>

10K_0201_5% ADC2/GPIO202 ADC3/GPIO203
E2
FAN
<17> AC_PRESENT GPIO022 N9
PWM1/GPIO054 FAN_ON_CPU <80> to/from CPU FAN Module
<17> -PCH_SLP_SUS K12 D6 FAN_FRQ_CPU <80>

GPIO140/SMB06_CLK FAN_TACH0/GPIO050
@ R10057 1 2 0_0201_5% -RSMRST_EC E3
<17,24> -RSMRST BGPO3/GPIO172 -SHUTDOWN <85>
B2 VCCST
<85> SUS_ON1 BGPO1/GPIO101
1
C4
<96> SUS_ON2 BGPO2/GPIO102 Q29
Power Management
B11 BPWRG 2 DTC015EMT2L_VMT3
VREF_VTT
<17,46,84,95> -PCH_SLP_S3 G11 B12 43_0201_5% 1 2 R413
GPIO110 PECI_DAT PECI <7,16>
3
G12 VCC3B
<17,84> -PCH_SLP_S4 GPIO111
<17,24,83,85> BPWRG F3
VCC_PWRGD
D9 100_0201_5% 1 2 R414
SMB03_DATA/GPIO007 EC_SDA2 <17>
1
1
<40> -LID_CLOSE R9992 1 2 0_0402_5% -LID_CLOSE_R A1 F8 100_0201_5% 1 2 R415 from/to PCH-H R416 R417
VCI_IN3#/GPIO000 SMB03_CLK/GPIO010 EC_SCL2 <17>
4.7K_0201_5% 1K_0201_5% C638
0.1U_0201_6.3V6-K
2
C C
2
<17> -PCH_SLP_WLAN A12
GPIO043
E12 R418 1 2 0_0201_5% -THRM
M8 SYS_SHDN#
<85> VCC5_TP_ON GPIO222
Thermal
3
C E
1 1 1
G3 2 Q30 2
B S TR 2SCR523MT2L NPN VMT3
<56,57> RJ45_LINKUP GPIO033 Q31
G13 C639 C640 B S TR 2SCR523MT2L NPN VMT3 C641
DP1_DN4 E C
1
B10 2 2 2
<83> -DOCK_ATTACHED_3M_R GPIO150/JTAG_TMS F13 2200P_0201_25V7-K 22P_0402_50V8-J 22P_0402_50V8-J
DN1_DP4
3
N1 E13 C E
<88> ISYS ADC5/GPIO205 DP2_DN5 1 1 1
2 Q32 2
J4 C642 C643 B S TR 2SCR523MT2L NPN VMT3 C644 Q33
<88> -BOOST_MODE GPIO227 D13 E C
1
PROCHOT_EC D3 DN2_DP5 2 2 2
LED2/GPIO153 2200P_0201_25V7-K 22P_0402_50V8-J 22P_0402_50V8-J
C13
DP3_DN6
3
C E
1 1 1
B13 2 Q34 2
M10 DN3_DP6 C645 C646 B S TR 2SCR523MT2L NPN VMT3 C647 Q35
<54> AOU_SEL1 GPIO015/PWM7 E C
1
L8 2 2 2
<54> AOU_SEL2 GPIO016 2200P_0201_25V7-K 22P_0402_50V8-J 22P_0402_50V8-J
<54> -AOU_IFLG H9
GPIO025/UART_CLK USB/AOU D11
Plance near EC pinout
GPIO220/VIN Cap should be placed near 2SCR523M
B4
<54> USB_ON1 BGPO4/GPIO173 E11
E4 VSET
<54,55> USB_ON2 BGPO5/GPIO174
Thermal Diode Table
1
ESD5Z3.3T1G SOD-523
B R419 R420 ID Device Placed on B

4.53K_0201_1% 10K_0201_5%
1
DIODE 1(Q30) CPU DCDC BOT

D54
MEC1653
1
2
1
1
100K_0201_5%
100K_0201_5%
100K_0201_5%
100K_0201_5%
100K_0201_5%
DIODE 2(Q31) GPU DCDC BOT

R425
R421
R422
R423
R424
DIODE 3(Q32) GPU FAN BOT

@ DIODE 4(Q33) CPU FAN BOT
2
2
2
DIODE 5(Q34) DDR DCDC BOT

2
DIODE 6(Q35) 3/5 V Power chock TOP
VCC3_SUS
VCC3SW
2
R853 @ R855 EMI

10K_0402_5% -RSMRST 10K_0402_5%
-LID_CLOSE_R
1
1
1
D D83
2 Q71 @ -RSMRST 2 1 -RSMRST_EC
G LSK3541G1ET2L_VMT3 2
RB521CS-30GT2RA_VMN2-2 C9363 EMC@
S 1 2200P_0201_25V7-K
3
1
D C721
2 Q70 @ 100P_0402_50V8-J 1
<17,85> MPWRG
G LSK3541G1ET2L_VMT3 @
A A
2
S
3

HTTPS://EN-MANUALS.CLAN.SU Issued Date 2015/07/16 Deciphered Date 2016/01/16 MEC1653L(2/3)
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common VCC3M
1
R426
2
VCC3M_EC
10_0402_5% 1 2 R427
VCC3M
VCC3B VCC3M VCC3B
10U_0603_10V6-K
0.1U_0201_6.3V6-K
0.1U_0201_6.3V6-K
0.01U_0201_6.3V7-K
0_0603_5%
1 1 1 1
C648
C649
C650
C651
1
2 2 2 2
100K_0402_5%
1
1
100K_0201_5%
100K_0201_5%
R9905
R428
R430
D D
2
VCC3M
2
VCC3SW
4.7U_0402_6.3V6-M
1
VCC3M_EC
100K_0402_5%
1
R10037
C652
F12
G6
G8
H8
H3
H4
F4
J1
J3
U27C 2
2
2
10K_0201_5%
2.2K_0402_1%
2.2K_0402_1%
@
VBAT
VTR
VTR_18
VTR_LPC
VTR_REG
VTR_FLASH
AVTR_ADC
VREF_ADC
VR_CAP
R456
R10032
R10031
<52> -TBT_ACE_MRESET
1
100K_0402_5%
R10053
1
2
R571 1 2 22_0402_5% J10 L12 B_ON <64,83,84,95,98,99,100,104>

<34> I2C_DATA_VIDEO GPIO130/SMB10_DATA GPIO012/SMB07_DATA
R572 1 2 22_0402_5% K10 K11 GFXCORE_ON_D
<34> I2C_CLK_VIDEO GPIO131/SMB10_CLK GPIO013/SMB07_CLK GFXCORE_ON_D <110,115>
N11 1R35VIDEO_ON
Damper resisters to fine-tune I2C signals GPIO014/PWM6 1R35VIDEO_ON <31,111,115>
R10061 1 2 0_0402_5% E9
<52> ACE_I2C_SDA2 GPIO141/SMB05_DATA
R10062 1 2 0_0402_5% B9 E1 1R05VIDEO_ON
<52> ACE_I2C_SCL2 GPIO142/SMB05_CLK GPIO023 1R05VIDEO_ON <112,115>
F10 -PCH_SLP_LAN -PCH_SLP_LAN <17>
JTAG Port Option (JTAG_RST#) GPIO135
Set to High : Enable F9 Need to assign this signal as "3VIDEO_ON"
Set to Low : Disable <34,61> -VIDEO_THERM_ALERT GPIO104/UART_TX instead of "MMX_ON" on Walter
C A9 M3 3VIDEO_ON C
<31,34> -GPU_RST GPIO105/UART_RX ADC6/GPIO206 3VIDEO_ON <114,115>
VCC3M N3
ADC7/GPIO207 FAN_ID_VIDEO <80>
N10 J2
<80> FAN_ON2_VIDEO GPIO056/PWM3 ADC8/GPIO210
1
10K_0201_5%
R434
<80> FAN_FRQ_VIDEO E5 K2 GSENSE_INT <81>

GPIO051/FAN_TACH1 ADC9/GPIO211
@ L1
ADC10/GPIO212 -LEDNUMLOCK <78>
F2
2
GPIO062 L3
ADC11/GPIO213 -VIDEO_THERM_OVERT <34>
A10
JTAG_RST# M2
VCC3SW ADC12/GPIO214 EC_P80DATA <61>
1
10K_0201_5%
N2 100_0402_5% 1 2 R9935
0.1U_0201_6.3V6-K
1 ADC13/GPIO215 GPUVCORE_CURRENT_VINT20 <110>

C653
R435
J9 M4
<84> ECSPI_CLK SPI_CLK ADC14/GPIO216 -VIDEO_POWER_LIMIT <34>
2 K9 N4
<84> ECSPI_MOSI -EC_SLP_LAN <84>
2
SPI_MOSI ADC15/GPIO217
1
1
1M_0201_5%
1M_0201_5%
1M_0201_5%
1M_0201_5%
100K_0201_5%
SPI
R436
R437
R438
R439
R440
<84> ECSPI_MISO K8
SPI_MISO
L10
<84> -ECSPI_SS SPI_CS#
2
D2
VBAT
<65> -HDD1_DTCT VCI_IN0#/GPIO163
G1 D1
B VCI_IN1#/GPIO162 VCI_OUT EC_PWRREQ <84> B
<66> -HDD2_DTCT B1
VCI_IN4#/GPIO234
Payton only?
Connect to connector A2 C1
on 2nd HDD/SSD Slot VCI_IN5#/GPIO235 BGPO0 -BATLOW <17,46>
<60> -SSD1_DTCT
<60> -SSD2_DTCT D4
VCI_IN6#/GPIO167
1
100K_0201_5%
100K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
1U_0402_10V6-K
1
R441
R442
R443
C9341
R9956
R448
R449
R450
R451
R452
R453
These signal name are Walter Unique. VSS_ADC
VSS_RO
2
1
BGND
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
VSS0
VSS1
VSS2
JTAG Port Option (JTAG_RST#)

R454
R455
R457
R458
@ @
Set to High : Enable
Set to Low : Disabe MEC1653
H5
G5
F7
G4
K4
A3
Schematics is set as Enable.

2
@ @ @ @
PD on -PCH_SLP_LAN is NO_ASM on Thorpe

but keep for Payton for the case of Hi-Z in PCH side.
These are device tamper detection <14> -INTRUDER_EC (CT_20150428)
pins. If storage is detached, BIOS
will not automatically send password INTRUDER pin has two function.
to storage. (1) FAST POST
BIOS will skip device test in POST
if door is not opened.
A (2) SAFE BOTTOM ACCESS A
EC will turn off power of devices if

door is opened to be safe.

Issued Date 2015/07/16 Deciphered Date 2016/01/16 MEC1653L(3/3)
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common
VCC3M VCC3M
0.5A_32V_ERBRD0R50X
2
1 15K_0402_5%
1 15K_0402_5%
1 15K_0402_5%
1 15K_0402_5%
1 15K_0402_5%
1 15K_0402_5%
1 15K_0402_5%
1 15K_0402_5%
0.1U_0402_25V6-K
F10
D D
1
C719
1
2
R459 2
R460 2
R461 2
R462 2
R463 2
R464 2
R465 2
R466 2
JKBD1 @
40 42
R10059 39 40 GND2 41
1 2 38 39 GND1
<77> -LEDNUMLOCK 38
0_0402_5% DRV17 37
<75> DRV17 37
DRV16 36
<75> DRV16 36
TP_MIDDLE 35
TP_RIGHT 34 35
TP_LEFT 33 34
R10060 32 33
1 2 31 32
<75> -LEDCAPSLOCK 31
0_0402_5% 30
-HOTKEY 29 30
<75> -HOTKEY 29
R468 1 2 510_0402_5% -LEDMICMUTE_KBD 28
<75> -LEDMICMUTE 28
R467 1 2 510_0402_5% -LED_MUTE_KBD 27
<75> -LED_MUTE 27
R469 1 2 100_0402_5% -LEDFNLOCK_KBD 26
<75> -LEDFNLOCK 26
VCC3M_FUSE_KBD 25
DRV11 24 25
DRV8 23 24
DRV10 22 23
<75> DRV[15:0] 22
DRV12 21
DRV9 20 21
C DRV13 19 20 C
<75> SENSE[7:0] 19
DRV15 18
DRV5 17 18
DRV7 16 17
DRV6 15 16
DRV3 14 15
DRV1 13 14
SENSE5 12 13
DRV2 11 12 VCC5_TP
DRV4 10 11 VCC5_TP VCC5B
SENSE0 9 10
SENSE2 8 9
DRV0 7 8
7
4.7K_0402_5%
4.7K_0402_5%
10K_0402_5%
SENSE1 6
6
1A_32V_ERBRD1R00X
1A_32V_ERBRD1R00X
SENSE4 5
DRV14 4 5
4
2
SENSE6 3
SENSE7 2 3
SENSE3 1 2
1
F11
F12
JAE_FJ04B040HT1R3000-DT
1
R470 2
R472 2
R471 2
JTP1 @
12 14
-KBD_BL_DTCT 11 12 GND2 13
<75> -KBD_BL_DTCT 11 GND1
KBD_BL_PWM 10
B <75> KBD_BL_PWM 10 B
9
TP4CLK 8 9
<79> TP4CLK 8
7
TP_LEFT 6 7
TP_RIGHT 5 6
TP_MIDDLE 4 5
TP4_RESET 3 4
<75,79> TP4_RESET 3
TP4DATA 2
<79> TP4DATA 2
1
1
220P_0402_50V7-K
22U_0805_6.3V6M
22U_0805_6.3V6M
0.01U_0402_25V7-K
JAE_FL10F012HA1R3000
1 1 2 2
C655
C654
C656
C657
2 2 1 1
Need confirm 5BCP conn

and change to symbol
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 KEYBOARD CONNECTOR
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common
VCC5B VCC3B
0.5A_32V_ERBRD0R50X
1
D D
F14
R473 R474
4.7K_0402_5% 4.7K_0402_5%
2
2
JCP1 @
BYPASS_PAD 12 14
<75> BYPASS_PAD 12 GND2
11 13
<75,78> TP4_RESET 11 GND1
10
<75> IPDDATA 10
9
<75> IPDCLK 9
8
<75> -PAD_RESET 8
CP_VCC5B_FUSE 7
6 7
<27,28,29,30,83> SMB_DATA_3B 6
5
<78> TP4CLK 5
<78> TP4DATA 4
3 4
2 3
<27,28,29,30,83> SMB_CLK_3B 2
1
1
KYOCE_046811-612-000846
C C
VCC3B
0.5A_32V_ERBRD0R50X
1
F13
2
JFPR1
FPR_VCC3FP_FUSE 1
R9792 1 2 0_0402_5% USBP9-_FINGER_PRINT_R 2 1
<15> USBP9-_FINGER_PRINT 2
R9793 1 2 0_0402_5% USBP9+_FINGER_PRINT_R 3
<15> USBP9+_FINGER_PRINT 3
4
5 4
6 5
B 7 6 9 B
8 7 GND1 10
8 GND2
1
D88 D87 KYOCE_046811608000846_8P-T
DF2S6.8UFS_1-1L1A2 DF2S6.8UFS_1-1L1A2 @
2
EMC Parts
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 TOUCH PAD/FPR
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common
D D
VCC5B
VCC5B
FAN CURRENT FAN CURRENT

IS 0.5A MAX IS 0.5A MAX
C C
FUSE 2.0A FUSE 2.0A
1
F15 F16
2A_32V_ERBRD2R00X 2A_32V_ERBRD2R00X
GPU FAN
2
2
CPU FAN
JCFAN1 JVFAN1
VCC5B_CPU_FAN 1 VCC5B_VIDEO_FAN 1
FAN_ON_CPU 2 1 FAN_ON2_VIDEO 2 1
<76> FAN_ON_CPU 2 <77> FAN_ON2_VIDEO 2
3 3
4 3 4 3
5 4 5 4
6 5 6 5
6 6
7 7
8 GND1 8 GND1
GND2 GND2
HIGHS_WS32061-S0471-HF HIGHS_WS32061-S0471-HF
@ @
FAN_ID_CPU <76>
FAN_FRQ_CPU <76> FAN_ID_VIDEO <77>
FAN_FRQ_VIDEO <77>
B B
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 FAN CONNECTOR
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common
D D
TABLE
CS Mode Selection
H I2C Mode
L SPI Mode
C VCC3M C
VCC3M VCC3M
1 1
1
C662 C663
0.1U_0402_25V6-K 10U_0402_6.3V6-M
R481
10K_0402_5% 2 2
2
R480 @
10K_0402_5%
14
1
U28
2
TABLE
IO_Vdd
Vdd
P/N ADDR_SEL Address I2C_CLK_GSENSE 4 13
<76> I2C_CLK_GSENSE SCLK/SCL TRIG
I2C_DATA_GSENSE 6 2
<76> I2C_DATA_GSENSE SDI/SDA NC_1
H 32h (W) & 33h (R) ADDR_SEL 7 3
LIS3DH SDO/ADDR NC_2
L 30h (W) & 31h (R) 8 10
B nCS NC_3 B
PIN# 10, 15, 16 should be
R10033 1 @ 2 0_0402_5% 9 15
INT2 NC_4 connected GND for LIS3DH
H 3Eh (W) & 3Fh (R) R10034 1 2 0_0402_5% 11 16 (CT_20140927)
KX023-1025 <77> GSENSE_INT INT1 NC_5
L 3Ch (W) & 3Dh (R)
1
R482
10K_0402_5%
GND_1
GND_2
2
KX023-1025_LGA16_3X3
12
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 G-SENSOR
5 4 3 2 1
5 4 3 2 1
Payton Common
D D
VCC3_SUS TABLE
Pin TCG Infineon Nuvoton

No SLB9670VQ1.2 NPCT650LA0YX
PTP Spec (v38)
1 VDD VDD VSB

1 1 2 GND GND NC
3 GPIO NC GPX/GPIO2
1
C664 C665
@ R483 R647 0.1U_0402_25V6-K 10U_0603_6.3V6-M 4 GPIO NC PP
10K_0402_5% 10K_0402_5% 2 2 5 NC NC TEST
6 VNC/GPIO GPIO GPIO3
7 GPIO/VDD PP NC
2
8 VDD VDD VDD
C 9 GND GND GND C

10 VNC NC NC
22
14
1
U29 11 NC NC NC
Reserved
VDD3
VDD2
VDD1
VSB
12 NC NC
13 VNC/GPIO NC GPIO4
15
LAD3 PP
4 14 VDD NC VDD
-TPM_IRQ 18 3
<19> -TPM_IRQ
SPI_MOSI_IO0 R486 1 2 33_0402_5% SPI_MOSI_IO0_2_R 21 LAD2/SPI_IRQ GPX/GPIO2 30
15 NC NC DNC
<14,26> SPI_MOSI_IO0
SPI_MISO_IO1 R487 1 2 33_0402_5% SPI_MISO_IO1_2_R 24 LAD1/MOSI SCL/GPIO1 16 GND NC GND
<14,26> SPI_MISO_IO1 LAD0/MISO
-SPI_CS2 R484 1 2 33_0402_5% -SPI_CS2_R 20
<14> -SPI_CS2 LFRAME/SCS
27
SPI_CLK R485 1 2 33_0402_5% SPI_CLK_2_R 19 SERIRQ 29
<14,26> SPI_CLK LCLK/SCLK XOR_OUT/SDA/GPIO0 6 SPI_RST#
13 GPIO3/BADD 5 17 SPI_RST# RST#
-PLTRST_NEAR 17 CLKRUN/GPIO04/SINT TEST 18 SPI_PIRQ# PIRQ# SPI_IRQ#
<14,61,64,75,83,84> -PLTRST_NEAR LRESET/SPI_RST/SRESET
19 SPI_CLK SCLK SCLK
28 2 20 SPI_CS# CS# SCS#
LPCPD NC1 7 21 MOSI MOSI MOSI
NC2
NC3
10 22 VDD VDD VDD
11 GND
12 NC4 25
23 GND GND
Reserved NC5 26 24 MISO MISO MISO
NC6 31
NC7
GND1
GND2
GND3
GND4
33
EX-PAD
25 NC NC NC
SLB9670VQ1.2_VQFN32_5X5 26 NC NC NC
9
16
23
32
27 NC NC (SERIRQ)
B 28 NC NC DNC B
31 VNC NC NC
32 GND GND GND
A EMC A
@ @ Title
SPI_CLK_2_R R645 1 2 0_0402_5% C585 1 2 10P_0402_50V8-J Security Classification LC Future Center Secret Data
Issued Date 2015/07/16 Deciphered Date 2016/01/16 TPM
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common VCC3M
2
JTAG can work in MHz order
R604 @ R605 @ R606 @ R607 @
10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
1
D D
JTAG1
@ R600 1 2 0_0201_5% EC_JTAG_TMS 1
<76> -DOCK_ATTACHED_3M_R 1
2
@ R601 1 2 0_0201_5% EC_JTAG_TDI 3 2
<75> BDC_ON_R 3
4
@ R602 1 2 0_0201_5% EC_JTAG_TDO 5 4
<75> -WWAN_DISABLE_R 5
6
@ R603 1 2 0_0201_5% EC_JTAG_TCK 6
<75> -WLAN_RF_KILL_R
7
8 GND1
GND2
PLACE NEAR EC HIGHS_WS32061-S0471-HF
@
R94 1 2 0_0201_5%
-DOCK_ATTACHED_3M <74>
R95 1 2 0_0201_5%
BDC_ON <61>
R103 1 2 0_0201_5%
-WWAN_DISABLE <61>
R104 1 2 0_0201_5%
-WLAN_RF_KILL <61>
-PWRSWITCH <40,74,84>
JDBUG1
LPCCLK_DEBUG_24M 1 2 -PWRSWITCH
<19> LPCCLK_DEBUG_24M 1 2
C 3 4 LPC_AD_DBG0 @ R488 1 2 0_0402_5% LPC_AD0 C
-LPC_FRAME 5 3 4 6 LPC_AD_DBG1 @ R489 1 2 0_0402_5% LPC_AD1
<19,75> -LPC_FRAME 5 6
-CLKRUN 7 8 LPC_AD_DBG2 @ R490 1 2 0_0402_5% LPC_AD2
<17,75> -CLKRUN 7 8
IRQSER 9 10 LPC_AD_DBG3 @ R491 1 2 0_0402_5% LPC_AD3
<19,75> IRQSER 9 10
-PLTRST_NEAR 11 12
<14,61,64,75,82,84> -PLTRST_NEAR 11 12 LPC_AD[3:0] <19,75>
B_ON 13 14 -SUS_STAT
<64,77,84,95,98,99,100,104> B_ON 13 14 -SUS_STAT <19,75>
15 16
GND1 GND2
HRS_DF12L3P014DP0P5V86A
@
LPC Debug Port
ENABLE DISABLE
JDBUG1 ASM NO_ASM
R488 ASM NO_ASM
R489 ASM NO_ASM
VCC3B R490 ASM NO_ASM
R491 ASM NO_ASM
LOGIC
10K_0402_5%
10K_0402_5%
VCC5M
1
1
R492
R493
U30
2
B B
SMB_CLK_3B 1 5
<27,28,29,30,79> SMB_CLK_3B A Vcc
2
B
3 4
GND OE
TC7SB385FU_SSOP5 SMB_CLK
SMB_CLK <17>
SMB_DATA
SMB_DATA <17>
BPWRG
<17,24,76,85> BPWRG
U31
SMB_DATA_3B 1 5
<27,28,29,30,79> SMB_DATA_3B A Vcc
2
B
3 4
GND OE
1
C666
TC7SB385FU_SSOP5 0.01U_0402_25V7-K
2
A EMC A
@ @ Title
LPCCLK_DEBUG_24M R637 1 2 0_0402_5% C454 1 2 10P_0402_50V8-J Security Classification LC Future Center Secret Data
Issued Date 2015/07/16 Deciphered Date 2016/01/16 EEPROM/SMBUS SW
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common
VCC3B
VCC3SW
VL5
VCC3SW
1
47K_0402_5%
0.01U_0402_25V7-K
0.01U_0402_25V7-K
0.01U_0402_25V7-K
D R10018 D
1
AND LOGIC. Once -PCH_SLP_S3 is de-asserted 10K_0402_5%
R496 VCCST_PWRGD and IMVP VR_ON should be de-asserted in <= 1 usec.
R497
1 1 1 These are tCPU28 and tPLT17 defined in Intel SKL-H PDG.
C667
C668
C669
10K_0402_5% (CT_20141216)
2
2
2
2 2 2 CPUCORE_ON_ASIC D59 1 2 RB521CM_30 CPUCORE_ON <7,91>
-PCH_SLP_S3 D60 1 2 RB521CM_30
1
D
2 Q38
1
C670 S U32A
3
1000P_0402_50V7-K
2
from charger
-EXTPWR_ASIC F5 E7 M_ON <90> to DCDC
<76,88> -EXTPWR EXTPWR# EON
D9 VCCLAN_ON <85> to ASIC
-PCH_SLP_S3 H7 LANON
from PCH <17,46,76,95> -PCH_SLP_S3 SLP_S3# E8
-PCH_SLP_S4 J7 MEON
from PCH <17,76> -PCH_SLP_S4 SLP_S4# F9 A_ON <99,100,104> to DCDC
-PCH_SLP_S5 J8 AON
from PCH <17> -PCH_SLP_S5 SLP_S5# E9 B_ON <64,77,83,95,98,99,100,104>
to DCDC
-EC_SLP_LAN G6 BON
from EC <77> -EC_SLP_LAN SLP_LAN# E6 CPUCORE_ON_ASIC to DCDC
-PCH_SLP_M F6 CPUON
from PCH <17> -PCH_SLP_M SLP_M#
C SUS_PWR_ACK H6 C
SUSPWRACK
-PLTRST_NEAR A7 B8 -PWRON_DOCK <74> to Dock

from <14,61,64,75,82,83>
PCH -PLTRST_NEAR PLTRST# PWRON_DOCK#
-PWRSW_ASIC F8
PWRSW#
1/2
-PCIE_WAKE F7 B6 -EC_RESET <75> to EC
from M.2 WLAN slot <17,46,61,64> -PCIE_WAKE PME# ECRST#
PGPIO0 C6
PGPIO0
EC_PWRREQ C7 H3
from EC <77> EC_PWRREQ PGPIO1 MTRCL
PGPIO2 C8 G3
PGPIO2 STRCL
PGPIO3 C9 B7 BAT_CRG BAT_CRG <88> to charger
PGPIO3 BATCRG
DISCHARGE E4
<74,85> DISCHARGE PGPIO4
PGPIO5 A8
PGPIO5 H9 ECSPI_CLK_R R498 1 2 33_0402_5%
SPISCK ECSPI_CLK <77> from EC
H8 ECSPI_MOSI_R R499 1 2 33_0402_5% from EC
SPIMOSI ECSPI_MOSI <77>
1
A1
R512 A9 (TEST_IN1) G8 -ECSPI_SS_R R500 1 2 33_0402_5%
(TEST_IN2) SPISS# -ECSPI_SS <77> from EC
VCC3SW 100K_0402_5% J1
J9 (TEST_IN3) G7 ECSPI_MISO_R R501 1 2 0_0402_5%
(TEST_IN4) SPIMISO ECSPI_MISO <77> to EC
G5
2
B TEST B
100K_0402_5%
100K_0402_5%
100K_0402_5%
100K_0402_5%
1
1
4.7K_0402_5%
1
R503
R504
R505
R506
R502
TC62D517XBG
BAT_CRG
2
2
2
ECSPI_CLK_R
PGPIO0
PGPIO2 -ECSPI_SS_R
PGPIO3
100K_0402_5%
100K_0402_5%
100K_0402_5%
1
1
PGPIO5
VCC3M
R507
R508
R509
-PWRSW_ASIC
2
1
1 R510
2
C720 SUS_PWR_ACK
10K_0402_5%
0.22U_0402_10V6-K D48
1SS400CMT2R
1
2
100K_0402_5%
2
1
R511
@
For EMC
D49 C456 1 2 10P_0402_50V8-J R639 1 @ 2 ECSPI_CLK_R
2
1 2 -PWRSW <76>
<40,74,83> -PWRSWITCH 33_0402_5%
A A

Issued Date 2015/07/16 Deciphered Date 2016/01/16 THINK ENGINE 2(1/2)
5 4 3 2 1
5 4 3 2 1
Payton Common VREGIN20 VINT20
VREGIN20
1
1
1
R516 R515 R517
1
20_0603_5% 20_0603_5% 10_0603_5%
R514 ESR03EZPJ200/ROHM ESR03EZPJ200/ROHM
2
1.78M_0402_1%
VCC5M
2
D D
VCC5M
VDD10
2
R518 D50 D51
1 2 VCC3M VCC5M VDD10
1 2 1 2
No need Reset Switch 0_0402_5% 1
C673
VCC3SW
on Workstation model
1U_0603_25V6-K
1U_0603_25V6-K
0.1U_0402_25V6-K
because of detachable 1 1 1 VCC5B
2.2U_0805_25V6-K
2
C675
C676
0.1U_0402_25V6-K
0.1U_0402_25V6-K
0.1U_0402_25V6-K
C672
1
battery. 1 1 1
C677
C678
C679
R520
1
100_0402_5%
2 2 2
470P_0402_50V8-J
1.24M_0402_1%
R519
1U_0402_6.3V6-K
2 1 2 2 2
1
C671
C674
need to confirm HONDA VREGIN20
H1
A5
A2
2
VCC5B 2 U32B
2
VREGIN20
VDD10
VCC5M
1
R521
100K_0402_5% G1
VINT20
1
A4
R429 G2 CP10OUT
2
100_0402_5% BAT_VOLT J4
H2 VCC3SW C5
3SW_OFF# 5B
2
B4 B3 need to confirm VCC5MUBAY

RD0_ON/5MUBAY RD0_DRV/UBAY_DRV
G4 C3 VCC3LAN_DRV <106>
<84> VCCLAN_ON RD1_ON RD1_DRV
C H4 D4 C
<76> SUS_ON1 RD2_ON RD2_DRV SUS_DRV <105>
J5 D3 VCC5_TP_DRV <105>
<76> VCC5_TP_ON RD3_ON RD3_DRV
R522
1 2 H5 D2
RD4_ON RD4_DRV
0_0402_5% D1 VCC3WLAN_DRV <108>
RD5_DRV/WLAN_DRV
E3 VCC3WAN_DRV <108>
RD6_DRV/WWAN_DRV
F3 need to check
RD7_DRV/B_DRV
2/2
VCC3B
F4 B5 VCC3P_DRV <42> VCC3M
<41> PANEL_POWER_ON 3P_ON 3P_DRV
A6 VCC3B_DRV <107>
VINT20 3B_DRV C4
5B_DRV VCC5B_DRV <107>
1
E2
1
C680 1 2 1U_0603_25V6-K E1 M1_DRV C1 R524
CP25OUT M2_DRV M2_DRV <87> R523
D52 D53 2.2K_0402_5%
10K_0402_5%
2 1 2 1 B1 F1
VCPIN25 S1_DRV
0.22U_0805_25V7-K
C2
2
S2_DRV
2
1
C682
J6 F2 BAT_DRV <87>
<74,84> DISCHARGE DISCHARGE BAT_DRV
1 VCC3SW B2 DCIN_DRV <86>
C681 DCIN_DRV
0.01U_0402_25V7-K 2 D7 D6 R525 1 2 0_0402_5%
SHUTDWNIN# M_PGS MPWRG <17,76>
D5 BPWRG <17,24,76,83>
B_PGS
1
2
R526 J3 D8
33K_0402_5% TH_DET PWRSHUTDWN#
B VCC3SW B
DGND1
PGND1
PGND2
AGND1
2
R527
1 2
<90> 5M_3M_PWRG
<76> -SHUTDOWN 0_0402_5%
1
TC62D517XBG
1
G9
A3
B9
J2
R529 1
R528 @ 33K_0402_5% C683 @
0_0402_5% 470P_0402_50V8-J
Need creage 0.22U_0805_25 PN
2
2
2
-PWRSHUTDOWN <74,86,88>
540_0402NEW_30%_PRF15BB541NB6RC
540_0402NEW_30%_PRF15BB541NB6RC
540_0402NEW_30%_PRF15BB541NB6RC
540_0402NEW_30%_PRF15BB541NB6RC
540_0402NEW_30%_PRF15BB541NB6RC
540_0402NEW_30%_PRF15BB541NB6RC
540_0402NEW_30%_PRF15BB541NB6RC
540_0402NEW_30%_PRF15BB541NB6RC
540_0402NEW_30%_PRF15BB541NB6RC
540_0402NEW_30%_PRF15BB541NB6RC
540_0402NEW_30%_PRF15BB541NB6RC
540_0402NEW_30%_PRF15BB541NB6RC
Location Place near Power
RT530 PQ1 DCIN20_PWR FET
0.1U_0402_25V6-K
RT531 PQ25 VCC5M_PWR FET

2
2
2
1
C684
RT538
RT540
RT539
RT537
RT536
RT534
RT535
RT533
RT530
RT531
RT532
RT541
RT532 PQ26 VCC3M_PWR FET
Walter Only
RT533 Q23 DOCK_PWR FET 2
1
1
1
RT534 U1 CPU die
RT535 PU5 VCCCPUCORE
A RT536 PU8 VCCGFXCORE_I A
RT537 PQ27 DDR_PWR FET

RT538 PQ20 Battery Charger FET
RT539 PQ46 Charge FET
RT540 PQ10 M_BAT_PWR FET Security Classification LC Future Center Secret Data Title
RT541 PQ100 VCCGFXCORE_D FET Issued Date 2015/07/16 Deciphered Date 2016/01/16 THINK ENGINE 2(2/2)
PRT1(BAT_FET_HOT) PQ11 BAT_IN THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
5 4 3 2 1
5 4 3 2 1
Walter Unique 1 2
PR243 @ 0_0402_5%
PQ40 PQ41
LSK3541G1ET2L_VMT3 LSK3541G1ET2L_VMT3
1 3 ACDC_ID_C 3 1
ACDC_ID <74,76>
D
D
G
G
2
2
1
PD26
1
D ESD5Z3.3T1G SOD-523 D
-DOCK_ATTACHED_BAT_OP <74,88>
2
2
DCIN PJ55
DCIN_PWR20_F
2 1 PQ1 DOCK_PWR20 VINT20

2 1 SI7149DP-T1-GE3_POWERPAK8-5
@ JUMP_43X118 1
PJ1 PF1 2 PQ2
1 1 2 1 2 3 SIS402DNT1GE_POWERPAK1212-8-5
1 2 5
2 3 @ PL110 15A_32V_0501015.WR 1
3 PR2
0.47U_0402_25V6-K
4 SMB-403025-EJ_2P 2
4
4
1000P_0402_25V7-K
5 2 CV20 3 5 1 2
5
100P_0402_50V8J
6
6
2
470K_0402_5%
200K_0402_5%
PC2
7 DCIN EMI Bead(PL110) 0.005_3008_LE_1%_2W
7
2
1
PC1
PC3
10 8 PR4
4
PTH1 8
2
1
0_0201_5%
0_0201_5%
PR1
PR3
11 9 100_0402_5% PQ3
PTH2 9 PD1
1M_0402_5%
PRJ1
PRJ2
EDZVT2R12B_EMD2-2
DTC115EMGT2L_VMT3
1
FOX_GS7309Y-10272-M-7H 2 1 2 3 1
100_0402_5%
ME@
0.01U_0402_25V7K
PC4
1
PD27
PR5
0.01U_0402_25V7K 1SS400CMT2R_VMN2M2 2 2
1
470P_0402_50V7K
PC5
PC6
2
2
2
270_0402_5%
C C
1
1 1
2CV20_E
PR6
1
PR7 1
PQ4
3 1 PD28
1SS400CMT2R_VMN2M2
@
SDV use PAYTON of SDV ,9-PIN Conn
1
PR9
2 1 2 2 1
DTA114EMGT2L_VMT3 <85> DCIN_DRV
2
PR244 @ 0_0402_5% 100K_0402_5%
PR8
100K_0402_5%
1
PQ5 D
2
1
G PQ42
LSK3541G1ET2L DTA015EMT2L_VMT3
S 3 1
3
PQ6
DTC115EMGT2L_VMT3
2
1
1M_0402_5%
2
2
PR10
@ 0_0402_5%
2
3
1
B B
PR245
1
1
PQ7 D
2
<74> DISCHARGE2
1
G PQ43 D
LSK3541G1ET2L -DOCK_ATTACHED_BAT_OP 2
S G
3
LSK3541G1ET2L
2
S
3
PR11
1
PQ8 D @ 0_0402_5%
2
<74,85,88> -PWRSHUTDOWN G
1
LSK3541G1ET2L
S
3
TABLE
PEAK SHIFT YES NO <88> DCIN_CURRENT_P
<88> DCIN_CURRENT_N
PR10 NO-ASM ASM
PR1 ASM NO-ASM
PQ6 ASM NO-ASM
A
PQ7 ASM NO-ASM A
LOGIC Issued Date 2014/07/01 Deciphered Date 2015/12/31 DC-IN

Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common
VCC3M
Walter Unique
2
PR12
6.19K_0402_1%
1
D PN D
M-BAT-PWR BAT-PWR12 VINT20
BAT CONN
PJ2 PQ11
FOX_BBP27D1-B460A-7H PQ10 SIS402DNT1GE_POWERPAK1212-8-5
Walter Unique SI7149DP-T1-GE3_POWERPAK8-5
ME@
7 PF2 1 PR50 1
7 6 M_BAT_IN 1 2 2 1 2 2
6 5
EDZVT2R15B_EMD2-2
PR13 3 3 5
5 4 100_0402_5% 15A_32V_0501015.WR 5 0.01_1206_LE_1%
4 3
1
2 1
3 2 I2C_CLK_BT <75>
9 PR14 2
4
8 PTH2 2 1
PD29
100_0402_5%
PTH1 1 2 1 PR15 PC7
I2C_DATA_BT <75>
100_0402_5%
510K_0402_5% 0.01U_0402_25V7K
2
2
2
1
0_0201_5%
0_0201_5%
PR16
PRJ3
PRJ4
2BAT_PWR12_D
M_TEMP <75>
2
100_0402_5%
2200P_0402_25V7-K
2200P_0402_25V7-K
@
1
390P_0402_50V
390P_0402_50V
PR17
1
1
2
1
PC8
PC9
PC10
PC11
1
PR20
750K_0402_1%
1
2
PD30 2 1 BAT_DRV_R
@ 1SS400CMT2R_VMN2M2
@ @ PR18
PD2
27K_0402_1% PR246
1
2 1 2 1 1 2
PR21
2 1 2 @ 0_0402_5%
<85> M2_DRV
1SS400CMT2R_VMN2M2
150K_0402_5% PC12
<88> SRN
1500P_0402_50V7K <85> BAT_DRV
1
<88> SRP
C C
PQ44
DTA015EMT2L_VMT3
3 1
BAT-PWR12
2
2
2
PR248
PR247 1M_0402_5%
1M_0402_5%
1
1
1
PQ45 D
2
<74> -DOCK_PWRDCT G
LSK3541G1ET2L
2
S
3
PR249
1M_0402_5%
1
B B
VCC3B
2
M-BAT-PWR M-BAT-PWR_F VREGIN20
PR30
4.7K_0402_5%
PD3
DAN222MGT2L_VMD3
PF4
1
0.1U_0402_10V7-K
2
2 1 1
1
PC17
3
BAT_FET_HOT <75>
0.5A_32V_ERBRD0R50X
1
DOCK_DCIN20 DOCK_DCIN20_F
PD4 PRT1
DAN222MGT2L_VMD3 540_0402NEW_30%_PRF15BB541NB6RC
PF6 2
1 2 1
NEAR TO PQ11
2
3
0.5A_32V_ERBRD0R50X
DCIN_PWR20_F DCIN_PWR20_F_F
PD6
DAN222MGT2L_VMD3
PF7 2
1 2 1
3
0.5A_32V_ERBRD0R50X
A A

Issued Date 2014/07/01 Deciphered Date 2015/12/31 BATTERY INPUT
HTTPS://EN-MANUALS.CLAN.SU AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Walter Unique
BAT-PWR12
CHARGER_OUT12
PQ46
SI7149DP-T1-GE3_POWERPAK8-5
1
2
3
5
1U_0603_25V7-K
4
470K_0402_5%
2
PC483
2
100_0402_5%
PR251
D D
VREGIN20 PR283 PR250
1
PR252
PR231 0_0402_5% 39K_0402_1%
1
ESR03EZPJ200_20ohm/5%/0603/0.25W 2 1 DCIN_CURRENT_P <86>
1 2
1
DCIN_CURRENT_N <86>
1
PR253
1 2 150K_0402_1%
PR232
2
ESR03EZPJ200_20ohm/5%/0603/0.25W
2
PR233 PR254
1
4.99_0402_1% 200K_0402_1% PQ47 D
DCIN_PWR20_F_F 1 2 2
PR235 <84> BAT_CRG G
0.033U_0402_16V
@ 0_0603_5% PR234 LSK3541G1ET2L
2
PC484
2 1 1K_0402_1% S
3
1 2 DOCK_CONSUMP <74>
PR255
PD31
1
PQ38 1K_0402_1%
1 2 1 2
3 1
PC22
1 2 1SS400CMT2R_VMN2M2
2
1U_0603_25V7-K
RSM002P03GT2L_SC-105AA
2
0.1U_0402_25V6
PR236
2
1M_0402_5% PC24
2
DOCK_DCIN20_F
PC26
0.1U_0402_25V6 PC25
1
PR42 PR43 0.1U_0402_25V6
1
RB530SM-30T2R_EMD2-2
RB530SM-30T2R_EMD2-2
0_0402_5% 0_0402_5%
@ @ @
2
1
2
CH_AGND CH_AGND CH_AGND

C C
1
PR237 VINT20
1M_0402_5%
PD24
PD25
1
2200P_0402_25V7-K
10U_0805_25V6-K
10U_0805_25V6-K
10U_0805_25V6-K
10U_0805_25V6-K
47P_0402_50V8-J
BQ24780_ACDET_R
1
PC27
PC28
PC29
PC30
PC488
PC489
PC478
1
PQ49 D 0.1U_0402_25V6
1
2 @
2
ACN
<74,86> -DOCK_ATTACHED_BAT_OP
ACP
G PR46 PC462
LSK3541G1ET2L 432K_0603_1% 1 2
S
3
5
1U_0603_25V7-K
1
PR48 PC32
ACP
ACN
66.5K_0603_1% 2.2U_0603_25V6M
1 2 28 24 1 2
6A
CH_AGND VCC REGN 4
6 PC34 PL1: NEC TOKIN MPLCG0630L2R2
PC33 ACDET PR49 0.047U_0603_25V7M CHARGER_OUT12
1 2 25 BST_CHG
1 2 2 1 TDK SPM6530T-2R2M
BTST PQ20
PR50: 1W 0.01 +-1% 1206_LE
3
2
1
@ 0.1U_0402_25V6 0_0603_5% CSD17552Q3A PL1
3 26 DH_CHG 2.2UH_SPM6530T-2R2M_8.2A_20%
CMSRC HIDRV 1 2
4
ACDRV
5
27 LX_CHG
PHASE
1
PC527
PC537
PC528
1
5
ACOK PC35
2
<75> I2C_DATA_CHARGE PR53 1 2 @ 0_0402_5% 11 @680P_0603_50V7-K
SDA 2
10U_0805_25V6-K
10U_0805_25V6-K
10U_0805_25V6-K
PU1 23 DL_CHG 4 PC38 PC39
LODRV
10U_0805_25V6-K
10U_0805_25V6-K
PR55 1 2 @ 0_0402_5% 12 BQ24780SRUYR 22 CH_AGND
SCL GND
2
<75> I2C_CLK_CHARGE
PQ21 PR54
3
2
1
PR56 1 2 @ 0_0402_5% 7 29 CSD17552Q3A @ 75_0805_5%
<76> ISYS
1
B IADP PAD B
2
PR57 1 2 @ 0_0402_5% 8 18
IDCHG BATDRV PC36
PR58 1 2 @ 0_0402_5% 9 CH_AGND 1 2
<91> PSYS PMON 17 PR293 2 1 10_0402_1%
BATSRC 0.1U_0402_25V6
PC41 20 PR60 2 1 0_0402_5% SRP SRP <87>
PR61 1 2 10 SRP
<75> -CHG_PROCHOT PROCHOT#
2
100P_0402_50V8J
@ 0_0402_5%
2
PR238 1 2 13 PC529
PC40 PC42 10K_0402_5% CMPIN
0.1U_0402_25V6
1
BATPRES#
100P_0402_50V8J 100P_0402_50V8J PR239 1 2 14 TB_STAT#
1
VCC3SW CH_AGND 10K_0402_5% CMPOUT 19 PR62 2 1 0_0402_5% SRN

SRN SRN <87>
21 PC37
VCC3M PR448 ILIM 1 2
CH_AGND
10K_0402_5%
CH_AGND CH_AGND CH_AGND 1 2 0.1U_0402_25V6
16
15
PRJ5
2
PR63 1 2
VCC3SW 0_0402_5%
2
@
PR256 PR294 @ 0_0402_5%
1
2
100K_0402_5% PR64 10K_0402_5%

PR257 100K_0402_1%
100K_0402_5% 1 2 CH_AGND
VCC3M
1
2
1
<76,84> -EXTPWR
PR295
1
1M_0603_5%
1
D PQ48 PR66 CH_AGND

2
PC485 2 PC43 100K_0402_1%

2
47P_0402_50V8-J G 0.01U_0402_25V7-K -BOOST_MODE <76>

2
1
PQ52 D
1
S LSK3541G1ET2L 2
3
LSK3541G1ET2L S CH_AGND CH_AGND

3
CH_AGND CH_AGND
A A
1
PQ53 D
2
<74,85,86> -PWRSHUTDOWN G
LSK3541G1ET2L S
3

CH_AGND BATTERY CHARGER
Issued Date 2014/07/01 Deciphered Date 2015/12/31
HTTPS://EN-MANUALS.CLAN.SU AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common
D D
C C
B B
A A

Issued Date 2014/07/01 Deciphered Date 2015/12/31 BLANK
Custom 0.1
5 4 3 2 1
5 4 3 2 1
Payton Common
PJ3
2 1
VCC3MP 2 1 VCC3M
@ JUMP_43X118
D D
PJ4
2 1
VCC5MP 2 1 VCC5M
@ JUMP_43X118
PJ5
2 1
2 1
@ JUMP_43X79
PJ6
2 1 5V_VIN
VINT20 2 1
10U_0603_25V6-M
10U_0603_25V6-M
10U_0603_25V6-M
10U_0603_25V6-M
10U_0603_25V6-M
10U_0603_25V6-M
2200P_0402_25V7-K
0.1U_0402_25V6
@ JUMP_43X118
VINT20
47P_0402_50V8-J
1 1 1 1 1 1
1
3.3V_ALW
PC447
PC446
PC445
PC444
PC44
PC45
PC490
PC491
PC482
2
2
2 2 2 2 2 2 @ PJ7
PR71 3V_VIN 2 1
0_0402_5% VL5 2 1 VINT20
2200P_0402_25V7-K
10U_0603_25V6-M
10U_0603_25V6-M
10U_0603_25V6-M
10U_0603_25V6-M
@ JUMP_43X79
47P_0402_50V8-J
PR72 1 1 1 1
1
PC492
PC493
PC46
PC47
PC448
PC449
@ 0_0402_5% PC481
0.1U_0402_25V6
4.7U_0402_6.3V
4.7U_0402_6.3V
1 2 1 1 @
<84> M_ON
2
1
2 2 2 2
PC49
PC50
PC48
0.1U_0603_25V7K
2
2 2
12
13
3
C
MAX:25A C
VREG5
VREG3
VIN
TDC:22A 20
EN1 EN2
6
PR180 PR179
0_0603_5% 0_0603_5% PQ26
VCC5MP 2 1 5V_DH 16 10 3V_DH 2 1 BSC0924NDI
DRVH1 DRVH2
2
2
PC51 PR73 PR74 PC52
1 1 0.1U_0603_25V7K 0_0603_5% 0_0603_5% 0.1U_0603_25V7K 1
1 2 2 1 5V_BST17 9 2 1 1 2 PL5
MAX:15A
VBST1 VBST2
PL4 PU2 1UH_PCMC063T-1R0MN_+-20% TDC:12A
1UH_PCMC133E-1R0MF_24A_20% TPS51285BRUKR_WQFN20_3X3
1 2 7 7 5V_LX 18 8 3V_LX 7 1 2
SW1 SW2 VCC3MP
1
PC57 6 6 6
2200P_0402_25V7-K
5V_DL 3V_DL
0.1U_0402_25V6
@ 680P_0402_50V7K 15 11 PC58 PC471 PC53 PC54
DRVL1 DRVL2 @ 680P_0402_50V7K 1 1 1
2
1
220U_B2_6.3VM_R35M
220U_B2_6.3VM_R35M
220U_B2_6.3VM_R35M
PC494
2
+ + +
PC495
14 4 3V_VFB2
5
4
3
5
4
3
3
4
5
VO1 VFB2
2
2200P_0402_25V7-K
0.1U_0402_25V6
PC470 PC469 PC468 PC56 PC55
PGOOD
2
2
PR75 5V_FB1 2
VCLK
1 1 1 1 1
GND
VFB1
CS1
CS2
1
1
2 2 2
220U_B2_6.3VM_R35M
220U_B2_6.3VM_R35M
220U_B2_6.3VM_R35M
220U_B2_6.3VM_R35M
220U_B2_6.3VM_R35M
PC496
PC497
@ 4.7_0603_5% PQ25 PR76

+ + + + + PR77 BSC0924NDI PQ50 @ 4.7_0603_5% PR78
BSC0924NDI
2
19
21
7
15.8K_0402_1% 13.7K_0402_1%
1
2 2 2 2 2
2
2
2
11.3K_0402_1%
1
1
PR80
PR81
1
PR79
2
200_0402_1% 15K_0402_1% PC20 PR82
1
1
5M_3M_PWRG <85>
2
2
PR83 PC19 @ 100P_0402_50V8J 20K_0402_1%
2
10K_0402_1% @ 100P_0402_50V8J
1
2
B B
A A
HTTPS://EN-MANUALS.CLAN.SU Issued Date 2014/07/01 Deciphered Date 2015/12/31 DC/DC VCC5M/VCC3M

C 0.1
5 4 3 2 1
5 4 3 2 1
Walter Unique
Support Skylake H-line 42 PC59 close to PL11 VCCST
processor only 2 1
PR85 PRT2 PR87 PR88
@ 0_0402_5% 1000P_0402_25V7-K 100K_0402_1%_NCP15WF104F03RC 13.3K_0402_1% 6.81K_0603_1%
1 2 1 2 VSN_1PH 1 2 2 1 2 1
<11> VSSSA_SENSE SW_1PH <94>
PR86
PC61
1
PC60 1.54K_0402_1%
1
1000P_0402_25V7-K 1 2 AGND_NCP81205 PR89 PR90
2
100_0402_1%
@ PR91 PC62
45.3_0402_1%
PR93 0.015U_0402_25V7-K 0.1U_0402_25V6
2
VCC3B
56.2_0402_1%
2.49K_0402_1% PC63
1 2 1 2 VSP_1PH 1 2
<11> VCCSA_SENSE
1
D D
PC64
1
2
PR92 4700P_0402_25V7-K CPUCORE_PWRGD <17,24> PR96 AGND_NCP81205
2
@ 0_0402_5% 2 1 PR95 81205_SCLK 1 2
2
51.1K_0402_1% 49.9_0402_1% SVID_CLK <7>
<94> CSN_1PH PWM1_1PH/ICCMAX1 <94>
1000P_0402_25V7-K PC66 1000P_0402_25V7-K PR97 PR176 PR98
1 2 1 0_0402_5% 81205_ALERT 2 1
10K_0402_1%
1
PC65 @ 0_0402_5% -SVID_ALERT <7>
AGND_NCP81205 1 2 470P_0402_50V7K PR100
1
24.9K_0402_1% PR104 81205_SDIO 1 2
SVID_DATA <7>
PR102 PR99 34.8K_0402_1% 10_0402_1%
PC67
750_0402_1% 1 2 AGND_NCP81205
PR105 AGND_NCP81205 1 2 1 2 1 2
@ 0_0402_5% 81205_SCLK CPUCORE_ON <7,84>
1 2 VSP_3PH_A 0.015U_0402_25V7-K 81205_ALERT PR103
<9> VCCCORE_SENSE 81205_SDIO
PC68 1 2 @ 0_0402_5%
15P_0402_50V PR107
2
PC69 @ 0_0402_5%
1000P_0402_25V7-K
PR109 VSN_1PH 1 2
1
1.37K_0402_1% VCCGT_SENSE <10>
1 2 1 2 VSN_3PH_A
<9> VSSCORE_SENSE
1
VSP_1PH PC71
PR108 PC70 1000P_0402_25V7-K
@ 0_0402_5% 1 2
2
AGND_NCP81205 PR111
2200P_0402_25V7-K 1.37K_0402_1%
1 2 1 2 VSSGT_SENSE <10>
PC72 PR112
PC73 PC74 1 2 @ 0_0402_5%
53
52
51
50
49
48
47
46
45
44
43
42
41
40
47P_0402_50V8-J PR114 470P_0402_50V7K
49.9_0402_1% 2200P_0402_25V7-K
PAD
VSP_1PH
VSN_1PH
COMP_1PH
ILIM_1PH
CSN_1PH
CSP_1PH
IMON_1PH
VR_RDY
PWM_1PH/ICCMAX_1PH
EN
SCLK
ALERT#
SDIO
1 2 1 2 1 2 PR115
24K_0402_1% PC77 PC78
PR116 PR117 1 2 PR118 470P_0402_50V7K 47P_0402_50V8-J
3K_0402_1% PC75 1K_0402_1% PR119 49.9_0402_1%
C 2 1 1 2 1 2 PC76 VSP_3PH_A 1 39 PR388 2 1 100_0402_5% 25.5K_0402_1% 1 2 1 2 1 2 C
470P_0402_50V7K VSN_3PH_A 2 VSP_3PH_A VR_HOT# 38 -PROCHOT 1 <7,76> 2 PR121 PC79
2200P_0402_25V7-K 1 2 3 VSN_3PH_A VSP_3PH_B 37 1 PR120 2 2 1 1 2
AGND_NCP81205 IMON_3PH_A VSN_3PH_B AGND_NCP81205
DIFFOUT_3PH_A 4 36 1 2 PC80 1K_0402_1%
FB_3PH_A 5 DIFFOUT_3PH_A IMON_3PH_B 35 DIFFOUT_3PH_B 470P_0402_50V7K 3K_0402_1%2200P_0402_25V7-K
COMP_3PH_A 6 FB_3PH_A DIFFOUT_3PH_B 34 FB_3PH_B
1 2 PR122 ILIM_3PH_A 7 COMP_3PH_A PU3 FB_3PH_B 33 COMP_3PH_B
CSCOMP_3PH_A 14.3K_0402_1% 8 ILIM_3PH_A NCP81205MNTXG_QFN52_6X6 COMP_3PH_B 32 ILIM_3PH_B 1 2 PR123
CSSUM_3PH_A 9 CSCOMP_3PH_A ILIM_3PH_B 31 18.2K_0402_1% CSCOMP_3PH_B
close to PL6 CSSUM_3PH_A CSCOMP_3PH_B close to PL9
2
10 30 CSSUM_3PH_B
PWM1_3PH_A/ICCMAX_3PH_A
PWM1_3PH_B/ICCMAX_3PH_B
CSREF_3PH_A CSSUM_3PH_B
1
1
PR124 CSP1_3PH_A 11 29
CSP2_3PH_A 12 CSP1_3PH_A CSREF_3PH_B 28 CSP1_3PH_B @ PR125
PWM3_3PH_B/ROSC_3PH
PWM2_3PH_B/ROSC_1PH
73.2K_0402_1% CSP2_3PH_A CSP1_3PH_B
1
100P_0402_50V
1000P_0402_25V7-K
73.2K_0402_1%
PRT3 PC81 CSP3_3PH_A 13 27 CSP2_3PH_B PRT4
CSP3_3PH_A CSP2_3PH_B
2
100P_0402_50V
PWM3_3PH_A/VBOOT
MURAT_NCP15WM224E03RC PC82 PC83 0.01U_0402_25V MURAT_NCP15WM224E03RC
TTSENSE_1PH/PSYS
PWM2_3PH_A/ADDR
1
1
PC85
2
2
2
TTSENSE_3PH_A
TTSENSE_3PH_B
PR126 PC84 PC86
1
680P_0402_50V7-K
1 2 0.01U_0402_25V PR129
<92> SW1_3PH_A
2
CSP3_3PH_B
2
2
82.5K_0603_1% 1 2 SW1_3PH_B
1
PR130 PR127 PR128 73.2K_0603_1%
1 2 165K_0402_1% AGND_NCP81205 165K_0402_1%
<92> SW2_3PH_A
DRON
VRMP
82.5K_0603_1%
VCC
PR131 VINT20
PR135 is ASM for 42 only AGND_NCP81205 PR132
1
1
1 2 RGB(128,255,128) 1 2 SW2_3PH_B
<92> SW3_3PH_A
82.5K_0603_1% PR135 is NO-ASM for 44e only 73.2K_0603_1%
14
15
16
17
18
19
20
21
22
23
24
25
26
2
PR133
1 2 PR134 PR135 0_0402_5%
<92> CSN1_3PH_A CSP3_3PH_B2
10_0402_1% 1K_0402_1% PC87 1 VCC5M
PR136 0.1U_0402_25V6 PSYS <88>
1 2 CSREF_3PH_A PC88 2 1 TSENSE_3PH_A PC89 AGND_NCP81205
<92> CSN2_3PH_A
1
10_0402_1% 0.01U_0402_25V 0.1U_0402_25V6 PR141

PR139 AGND_NCP81205 1 2 TSENSE_3PH_B 2 1 32.4K_0402_1% PR137 1 2
1 2 2 1 1 2 10_0402_1% CSN1_3PH_B <93>
<92> CSN3_3PH_A VCC5M
10_0402_1% PR140 2 1 AGND_NCP81205
2.2_0603_1% 1U_0402_10V6-K CSREF_3PH_B PR138 1 2
PR143 PR142 10_0402_1% CSN2_3PH_B <93>
2
SW1_3PH_A 2 1 CSP1_3PH_A PC90 PR144 43K_0402_1%
2
53.6K_0402_1%
2
2.26K_0402_1% PWM1_3PH_B/ICCMAX3B <93>
1
1
2
B B
PC91 PR145 PR146
PR147 PWM2_3PH_B/DOSC1 <93>
3.92K_0402_1%
0.1U_0402_25V6 97.6K_0402_1%
2
1
CSREF_3PH_A 97.6K_0402_1%
<92,93,94> DRON
1
<92> PWM1_3PH_A/ICCMAX3A
1
PR149
SW2_3PH_A 2 1 CSP2_3PH_A AGND_NCP81205
PR148
<92> PWM2_3PH_A/ADDR
1
2.26K_0402_1% AGND_NCP81205 CSP1_3PH_B 2 1

PC93 AGND_NCP81205 AGND_NCP81205 SW1_3PH_B <93>
1
0.1U_0402_25V6 2.26K_0402_1%
2
PC92
CSREF_3PH_A <92> PWM3_3PH_A/VBOOT
0.1U_0402_25V6
2
2
PR151 PR152 PR152 Vboot for Core/GT CSREF_3PH_B

SW3_3PH_A 2 1 CSP3_3PH_A 24.9K_0402_1%
PR150
1
2.26K_0402_1% 24.9Kohm 0V CSP2_3PH_B 2 1

1
PC95 SW2_3PH_B <93>

PRJ9
1
0.1U_0402_25V6 2.26K_0402_1%
2
1 2 169Kohm 1.05V PC94

CSREF_3PH_A TSENSE_3PH_A AGND_NCP81205 0.1U_0402_25V6
2
@ 0_0402_5% TSENSE_3PH_B CSREF_3PH_B
2
PR153
2
1.5K_0402_1%
PR154
AGND_NCP81205 1.5K_0402_1%
1
1
2
PR155
7.32K_0402_1%
2
PRT5 PR156
7.32K_0402_1%
100K_0402_1%_NCP15WF104F03RC
PRT21
1
100K_0402_1%_NCP15WF104F03RC
A close to PU4 A
1
close to PU7
HTTPS://EN-MANUALS.CLAN.SU Issued Date 2014/07/01 Deciphered Date 2015/12/31 DC/DC IMVP8

C 0.1
5 4 3 2 1
A
B
C
D
<91>
<91>
<91>
<91,93,94>
VCC5M
PWM3_3PH_A/VBOOT
DRON
DRON
VCC5M
PWM2_3PH_A/ADDR
DRON
PWM1_3PH_A/ICCMAX3A
VCC5M
PR113
PC177
1
2.2_0603_1%
PR106
1U_0402_10V
PR162
5
5
PC215
2 1 1 2
1
1
1
1
2.2_0603_1%
1U_0402_10V
PR167
PR94
PC125
VCC5M
2 1 1 2
1
2.2_0603_1%
PR262
PR261
1U_0402_10V
PR157
2 1
2
1
1
0_0402_5%
VCC5M
2 1 1 2
2
0_0402_5%
VINT20
1 2 2 1
2
2
2
2
VINT20
VCC5M
1 2
PL24
PL23
PC176
PR266 @ 0_0402_5%
PR265 @ 0_0402_5%
PR264 @ 0_0402_5%
PR263 @ 0_0402_5%
2 1
PL26
PL25
2
0_0402_5%
VINT20
@
2
2
1
1
PC214
1U_0402_10V
@
1 2
PL22
PL21
1
1
3
31
2
4
5
7
6
PR241
@ 0_0402_5%
@ 0_0402_5%
3
31
2
4
5
7
6
PR110
1U_0402_10V
PC113
1
1
0_0402_5%
@
3
31
2
4
5
7
6
VCC
0_0402_5%
PWM
1U_0402_10V
VCCD
DISB#
PR101
VCC
CGND1
PWM
SMOD#
1
VCCD
DISB#
ZCD_EN
2
2
THWN
CGND1
SMOD#
BLM18KG300TN1D
BLM18KG300TN1D
1 8
ZCD_EN
2
2
VCC
0_0402_5%
THWN GL1
PWM
BLM18KG300TN1D
BLM18KG300TN1D
8 9 20
VCCD
DISB#
GL1 GL2 VIN1

CGND1
SMOD#
9 20 10 21 PC169 1
ZCD_EN
2
2
GL2 VIN1 GL3 VIN2 THWN

BLM18KG300TN1D
BLM18KG300TN1D
10 21 11 22 10U_0805_25V 8
11 GL3 VIN2 22 PC207 GL4 VIN3 23 9 GL1 20
GL4 VIN3 VIN4 GL2 VIN1
2
1
23 10U_0805_25V 24 10 21 PC96
PU5
VIN4 24 VIN5 25 PC170 11 GL3 VIN2 22 10U_0805_25V
PU6
VIN5 VIN6 GL4 VIN3
2
1
25 10U_0805_25V 23
VIN6 VIN4
2
1
PC208 28 24
PU4
GH VIN5
2
1
28 10U_0805_25V 19 25 PC97
19 GH 26 PGND1 30 PC171 VIN6 10U_0805_25V
PGND1 PGND2 BOOT
2
1
NCP81382MNTXG_QFN39-31_6X4
26 30 10U_0805_25V 28
2
PGND2 BOOT GH
2
1
PC209 19
2
PGND1
2
1
10U_0805_25V 26 30 PC98
PGND2 BOOT
PC172 10U_0805_25V
2
VSW7
VSW6
VSW5
VSW4
VSW3
VSW2
VSW1
PHASEF
PHASED
2
1
PR163
10U_0805_25V
VSW7
VSW6
VSW5
VSW4
VSW3
VSW2
VSW1
PHASEF
PHASED
2
1
PR168
PC210
18
17
16
15
14
13
12
27
29
2
1
10U_0805_25V PC99
1
VSW7
VSW6
VSW5
VSW4
VSW3
VSW2
VSW1
PHASEF
PHASED
18
17
16
15
14
13
12
27
29
PR158
1 2 PC173 10U_0805_25V
2
1
10U_0805_25V
1
18
17
16
15
14
13
12
27
29
2
1
1 2 PC211 1 2 2 1 2
1
1 2 2 1 10U_0805_25V PC100
PC175
@
@
PC174 1 2 10U_0805_25V
2
1
@
@
10U_0805_25V 1 2 2 1
1
2
1
3.9_0603_5%_ESR03EZPJ3R9
PR164
PC188
PC212
PC213
4
4
2
1
3.9_0603_5%_ESR03EZPJ3R9
PR169
@
@
10U_0805_25V PC101
1
PL7
PC502 10U_0805_25V
PC102
2
1
3.9_0603_5%_ESR03EZPJ3R9
PR159
PC147
0.1U_0402_25V6
1
0.22U_0603_25V7-K
PL8
2
1
PC231
PC504 2 1
680P_0402_50V7K
0.1U_0402_25V6 PC498
2
PL6
680P_0402_50V7K
0.22U_0603_25V7-K
2 1 PC503 0.1U_0402_25V6
2
2200P_0402_25V7-K 2 1
2
680P_0402_50V7K
2 1
0.22U_0603_25V7-K
PC505
2200P_0402_25V7-K PC499
2
2
2
2.2_0603_5%_ESR03EZPJ2R2
PR161
2 1 2200P_0402_25V7-K
2
2.2_0603_5%_ESR03EZPJ2R2
CMLE064T-R15MS0R725-88(0.72mohm+/-5%) 2 1 2 1
1
2
2
@ 0_0402_5%
2.2_0603_5%_ESR03EZPJ2R2
PR166
PR165
2 1
CMLE064T-R15MS0R725-88(0.72mohm+/-5%)
PC522
PR160
68P_0402_50V8J 2 1
1
1
PR171
PR170
@ 0_0402_5%
@ 0_0402_5%
CMLE064T-R15MS0R725-88(0.72mohm+/-5%)
PC1008
1
@ 0_0402_5%
68P_0402_50V8J PC487
1
1
@ 0_0402_5%
@ 0_0402_5%
68P_0402_50V8J
SW1_3PH_A
SW2_3PH_A
CSN2_3PH_A
CSN1_3PH_A
SW3_3PH_A
<91>
CSN3_3PH_A
<91>
<91>
<91>
<91>
<91>
PC126 PC103 PC148 PC199 PC178
PC216 330U_B2_2.5VM_R9M
1
2
1
2
1
2
1
2
1
2
2 1
1
2
2
PC224 1
+
1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K 10U_0402_6.3V 10U_0402_6.3V

PC129 PC104 PC149 PC200 PC179 22U_0603_6.3V6M PC226
PC217 47U_0805_6.3V6M
1
2
1
2
1
2
1
2
1
2
2 1
H42-45W
330U_B2_2.5VM_R9M
1
2
H44e-45W
1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K 10U_0402_6.3V 10U_0402_6.3V
3
3
2
+

PC218 47U_0805_6.3V6M
1
2
1
2
1
2
1
2
1
2
2 1 330U_B2_2.5VM_R9M
1
2
67A(TDC:56A)
68A(TDC:56A)
1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K 10U_0402_6.3V 10U_0402_6.3V

2
+

1uF 63pcs
Walter Unique
PC219 47U_0805_6.3V6M
1
2
1
2
1
2
1
2
1
2
@
2 1 330U_B2_2.5VM_R9M
1
2
1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K 10U_0402_6.3V 10U_0402_6.3V

Panasonic:ETQP4LR15AFM
2
+

PC220 47U_0805_6.3V6M
1
2
1
2
1
2
1
2
1
2
@
330U_B2_2.5VM_R9M
1
2
1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K 10U_0402_6.3V 10U_0402_6.3V
Issued Date
2
PC225 1 PC230 1 PC418 1 PC419 1
+
PC127 PC108 PC153 PC204 PC183 22U_0603_6.3V6M

PC221
1
2
1
2
1
2
1
2
1
2
Security Classification
1
2
1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K 10U_0402_6.3V 10U_0402_6.3V

PC128 PC109 PC154 PC205 PC184 22U_0603_6.3V6M
Cyntec:CMLE064T-R15MSOR725-88
1
2
1
2
1
2
1
2
1
2
PC222
1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K 10U_0402_6.3V 10U_0402_6.3V
1
2
PC133 PC110 PC155 PC206 PC185

22U_0603_6.3V6M
1
2
1
2
1
2
1
2
1
2
processor only
PC223
1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K 10U_0402_6.3V 10U_0402_6.3V
1
2
PC134 PC111 PC156 PC195 PC186

22U_0603_6.3V6M
47uF 4pcs
1
2
1
2
1
2
1
2
1
2
2014/07/01
1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K 10U_0402_6.3V 10U_0402_6.3V
PC135 PC112 PC157 PC196 PC187 0.1U_0402_25V6
2 1
1
2
1
2
1
2
1
2
1
2
1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K 10U_0402_6.3V 10U_0402_6.3V 2200P_0402_25V7-K

PC114 PC158 PC136 PC197 PC189 2 1
PC500 PC501
Support Skylake H-line 42
1
2
1
2
1
2
1
2
1
2
1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K 10U_0402_6.3V 10U_0402_6.3V

PC115 PC159 PC137 PC190
PC198
1
2
1
2
1
2
1
2
1
2
1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K 10U_0402_6.3V
2
2
PC116 PC160 PC138 10U_0402_6.3V PC191

PC193
1
2
1
2
1
2
1
2
22uF 8pcs
Deciphered Date
1
2
1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K 10U_0402_6.3V

PC117 PC161 PC139 10U_0402_6.3V PC192
VCCCPUCORE
PC194
1
2
1
2
1
2
1
2
1
2
1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K 10U_0402_6.3V

LC Future Center Secret Data
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PC118 PC162 PC140 10U_0402_6.3V
1
2
1
2
1
2
1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K

PC119 PC163 PC141

1
2
1
2
1
2
2015/12/31
1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K

330uF 3pcs+2pcs(no mount)
PC120 PC164 PC142

1
2
1
2
1
2
1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K

PC121 PC165 PC143
1
2
1
2
1
2
1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K

C
PC122 PC166 PC144

Size
Date:
1
2
1
2
1
2
Title
10uF 28pcs
1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K

PC123 PC167 PC145
1
2
1
2
1
2
1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K

PC124 PC168 PC146
1
2
1
2
1
2
Document Number
1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K

DC/DC VCCPUCORE
1
1
Friday, October 02, 2015

NM-A451
Sheet
92
of
116
Rev
0.1
A
B
C
D
A
B
C
D
<91>
<91>
processor only
<91,92,94>
PWM2_3PH_B/DOSC1
VCC5M
DRON
PWM1_3PH_B/ICCMAX3B
DRON
PC318
2.2_0603_1%
5
5
1U_0402_10V
PR177
VCC5M
2 1 1 2
PR305
1
VCC5M
Support Skylake H-line 42
2
2
Walter Unique
PR270
PR269
2 1
PC238
2
2
2.2_0603_1%
PR242
PR268
PR267
1U_0402_10V
PR172
1
2 1 1 2
2
PC316
0_0402_5%
VINT20
1
1
VCC5M
1 2
PL32
PL31
PL30
1U_0402_10V
2 1
1
1
@ 0_0402_5%
@ 0_0402_5%
2
1
1
1
0_0402_5%
VINT20
@
3
31
2
4
5
7
6
@ 0_0402_5%
@ 0_0402_5%
1 2
PL29
PL28
PL27
PR306
PC239
1
1
1
0_0402_5%
VCC
PWM
1U_0402_10V
VCCD
DISB#
3
31
2
4
5
7
6
CGND1
SMOD#
1
ZCD_EN
2
2
2
PR304
THWN
BLM18KG300TN1D
BLM18KG300TN1D
BLM18KG300TN1D
8
9 GL1 20
0_0402_5%
VCC
GL2 VIN1
PWM
10 21
VCCD
DISB#
GL3 VIN2
CGND1
SMOD#
11 22 PC310 1
ZCD_EN
2
2
2
GL4 VIN3 THWN

BLM18KG300TN1D
BLM18KG300TN1D
BLM18KG300TN1D
23 10U_0805_25V 8
VIN4 24 9 GL1 20
PU8
VIN5 GL2 VIN1
2
1
25 10 21
VIN6 PC311 11 GL3 VIN2 22 PC232
28 10U_0805_25V GL4 VIN3 23 10U_0805_25V
19 GH VIN4 24
PU7
PGND1 VIN5
2
1
2
1
26 30 25
PGND2 BOOT VIN6
PC312 PC233
10U_0805_25V 28 10U_0805_25V
2
GH
19
PGND1
2
1
2
1
26 30
VSW7
VSW6
VSW5
VSW4
VSW3
VSW2
VSW1
PHASEF
PHASED
PGND2 BOOT
PC313 PC234
2
PR178
10U_0805_25V 10U_0805_25V
18
17
16
15
14
13
12
27
29
1
2
1
2
1
VSW7
VSW6
VSW5
VSW4
VSW3
VSW2

NM-A451 (ThinkPad P50) BP500

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

NM-A451 (ThinkPad P50) BP500

Uploaded by

Copyright:

Available Formats

5 4 3 2 1

DDR4 / 1.2V PCB Layer Stackup

SATA x? CPU DC/DC

WWAN Slot 61 USB3.0 CH03 SSD ? (X1) (X1) S: NCP81382MNTXG 92,93,94

LPC Bus 33MHz LAN +SMDDR_VREF_DIMM

Camera Issued Date 2015/07/16 Deciphered Date 2016/01/16 TITLE PAGE

TABLE: SYSTEM POWER STATE

Any other mark like below is prohibited on Payton/Walter.

Capacitor Naming Note

Security Classification LC Future Center Secret Data Title

A DDR4 INTERLEAVE IMPLEMENTATION A

Security Classification LC Future Center Secret Data Title

R543 2 1 121_0402_1% DDR_RCOMP0 G1 BN13 M_A_VREF_CA_CPU

Security Classification LC Future Center Secret Data Title

<31> PEG_RXP[15:0] PEG_TXP[15:0] <31>

<31> PEG_RXN[15:0] SKYLAKE_HALO PEG_TXN[15:0] <31>

PEG_RXP15 E25 B25 PEG_TXP15_C C2004 1 2 0.22U_0201_6.3V6-K PEG_TXP15

Security Classification LC Future Center Secret Data Title

Walter Only U1D SKYLAKE_HALO

0.1U_0201_6.3V6-K 1 2 C9315 N16S@ EXT_DP0P_CPU K36 BGA1440 D29 EDP_TXP0_I

Security Classification LC Future Center Secret Data Title

Payton Common VCCST VCCSTG

NC 4 A32 BCLKP CFG[0] BN27 Test_Point_32MIL 1 TP53

SN74AUP1G07DCKR SC70 D35 BN28 CFG3 CFG3 <24>

PCI_BCLKN CFG[4] BM20 CFG5

E31 BT20 CFG6

CFG[10] BT22 Test_Point_32MIL 1 TP40

If VCCSTG is used instead of VCC1R0_SYS,

Currently, VCCSTG is still on in Sleep S0

CFG[2] : PEG Static Lane Reversal

U1F SKYLAKE_HALO U1L SKYLAKE_HALO U1M SKYLAKE_HALO

Security Classification LC Future Center Secret Data Title

Security Classification LC Future Center Secret Data Title

U1H SKYLAKE_HALO U1N SKYLAKE_HALO

BG34 BGA1440 AV29 AJ29 BGA1440

Security Classification LC Future Center Secret Data Title

J30 BGA1440 AA6

C380 G21 G11

Security Classification LC Future Center Secret Data Title

Security Classification LC Future Center Secret Data Title

Security Classification LC Future Center Secret Data Title

Need to check target device

<26,82> SPI_MOSI_IO0 BB29 AF41 SYSTEM_DISPLAY_HPD R10045 1 2 0_0402_5% MUX_DP_HPD

R10049 1 2 10K_0402_5% -DGFX_OUTPUT_ENABLE

DOOR SWITCH -INTRUDER

Security Classification LC Future Center Secret Data Title

<46> PCIE5_L2_TBT_TXN PCIE7_TXN

Security Classification LC Future Center Secret Data Title

PCIE / SATA Configuration (v0.51)

Payton Common I/O

Port 21 SATA 2 / PCIE 15 SATA2 for HDD1 3

Security Classification LC Future Center Secret Data Title

Payton Common TABLE : Functional Strap

<67> HDA_BCLK R57 1 2 33_0402_5% HDA_BCLK_R BA9 BB17

VCC1R2A VCC3B VCC3M

Security Classification LC Future Center Secret Data Title

BB3 TBT_SNK0_DDC_CLK <46>

R79 R80 @ R81 R82

LEVEL PLANARID[3..0] CPU PCH

Security Classification LC Future Center Secret Data Title

Payton Common VCC3_SUS VCC3B

C11 AT22 LPC_AD0 Port 6 USB3 6 USB3 USB3P6_SYSP4

VCC3M VCC3M VCC3M VCC3M

VCC3M R9852 1 2 4.99K_0402_1% 4 5 VCC3M R9970 1 2 4.99K_0402_1% 4 5