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Y530 M/B Schematics Document


2 2

Coffee Lake H-Processor with DDR4 + NV N17P-G0/G1 GPU

XXXXX
2017-09-11
3
REV:0.1 3

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Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY
PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION
DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT
WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 1 of 74
A B C D E
A B C D E

LCFC confidential

nVidia N17P-G0/G1
HDMI Conn. GB4C-128 Package 29x29
Page 24~31
1
Page 36 PCI-Express 16X Gen3 Memory BUS (DDR4 non-ECC) 1

Channel B DDR4-SO-DIMM x1
mDP Conn. GDDR5*4 4GB
Intel CPU Page 12,13

Coffee Lake H 45W 1.2V DDR4 2666 MT/s


Page 43 Page 32~34 UP TO 16G x 1
Memory BUS (DDR4 non-ECC)
BGA-1440 Channel A
DDI x4 Lane eDP Conn
eDP x2 Lane 42mm*28mm
DDR4-SO-DIMM x1
FHD : 15" Page 12,13
1.2V DDR4 2666 MT/s
Page 35 Page 5~11
UP TO 16G x 1
DMI *4
USB Type-C
USB Type-C PD Controller USB 3.0 1x 5Gbps
Conn. RTS5455-GR USB 3.1 1x
Page 39 USB Right
USB2.0 1x
SUB-Board
USB3.1 Port4 USB20 Port3

Page 38 HDD Conn. SATA Gen3


Intel PCH
2 2

Page 46 SATA Port2


USB Left(AOU port x1)
PCIe 4x Gen3
Cannon Lake H USB3.1 2x
SSD M.2 Conn. USB3.1 Port1 USB2.0 Port1
/Optane Memory USB2.0 2x
SATA Gen3
Page 45 PCIe Port 9-12 USB Back port x1
USB3.1 Port2 USB2.0 Port2
FCBGA
LAN Realtek PCIe 1x 26mm*24mm
RJ45 Conn.
RTL8111GUL
Page 83 PCIe Port14
USB 2.0 1x M.2 Card (WLAN&BT)
PCIe 1x PCIe Port13 USB2.0 Port10
Int. Camera & Mic USB2.0 1x
CNVio
M.2 CRF Module
Page 35 USB2.0 Port6 Page 45

HD Audio SPI BUS SPI ROM


Page 14~22
16MB
3 Page 07 3

LPC
SPK Conn. Codec
Page 48 ALC3240
Page 48
EC TPM
ITE IT8226-LQFP128 Z32H320TC Sub-board
Page 49
Page 50
HP&Mic Combo Conn. USB3.1 x1 DB
Page 48

Battery int. keyboard Touch Pad Thermal Sensor CPU FAN


TP button DB
F75303M GPU FAN
Page 52 Page 51 Page 50 Page 44 Page 40

4 4

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 2 of 74
A B C D E
A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )


SIGNAL
+5VS STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+3VS
Power Plane Full ON HIGH HIGH HIGH HIGH ON ON ON ON
VCCIO
VCCSA S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
1
VCCSTG 1
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+3VALW
VCCCPUCORE S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
B+ +3VALW_PCH +1.2V VCCGFXCORE
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+5VALW +1.8VS_AON
+1.8VGS
State NVVDD BOM Structure Control Table
NVVDDS BOM Structure BTO Item
+1.0VGS @ Not stuff
FBVDDQ AOAC@ AOAC support part
CNVI@ CNVi support part
ME@ ME part(connector, hole)
S0 O O O O O
OPT@ For NV GPU part
S3 O O O O X OPTANE@ Optane memory support part
2 TPM@ For support TPM sku part 2

S3
Battery only O O O O X

S5 S4/AC Only O O O X X
CD@ Cost down part
S5 S4
Battery only O X X X X
S5 S4
AC & Battery X X X X X
don't exist

3 3

USB2.0 Port table USB3.0 Port table SATA Port table PCIE Port table
Port Function Port Function Port Function Port Function
1 Back USB3.0 1 Back USB3.0 0A NA 1:8 NA
2 Left USB3.0 2 Type-C Port 0B NA 9 M.2 SSD/Optane
3 Right USB3.0 3 Left USB3.0 1A M.2 SSD Gen3 10 M.2 SSD/Optane
4 Type-C Port 4 Right USB3.0 1B NA 11 M.2 SSD/Optane
5 NA 5 NA 2 HDD Gen3 12 M.2 SSD/Optane
6 Camera 6 NA 3 NA 13 WLAN Gen1
7:13 NA 4 NA 14 LAN Gen1
14 BT 5 NA 15:24 NA
4 4

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 3 of 74
A B C D E
5 4 3 2 1

+3VALW
PD Controller
RTS5455
2.2K
U4
D D

EC_SMB_CK0
EC_SMB_DA0

+3VALW_R
Change IC
Battery BQ24780SRUYR
2.2K
JBATT1 PU201

EC
EC_SMB_CK1
EC_SMB_DA1

C C
+1.8VS_AON +3VALW_PCH
UE1
IT8226E
2.2K 2.2K
VGA( UV1 ) PCH( UH1 )
+3VS Thermal sensor
VGA_SMB_CK2 SML1CLK
VGA_SMB_DA2 SML1DATA F75303M
+1.8VS_AON +3VS U1 (reserved)
2.2K
Dual MOS Control Dual MOS Control

EC_SMB_CK2
EC_SMB_DA2

B B

SMBUS Control Table

SOURCE VGA BATT IT8226E SODIMM WLAN Thermal PCH TP Charger RGB KB USB-C HiFi Audio
WiMAX Sensor Module Backlight PD

EC_SMB_CK1 IT8226E V V V
EC_SMB_DA1 +3VALW_R X +3VALW_R +3VALW_R X X X X X +3VALW_R X X X

EC_SMB_CK2 IT8226E V V
X X V V X X X X X
EC_SMB_DA2 +3VS +1.8VS_AON X +3VS +3VS +3VALW_PCH
Reserve

PCH_SMBCLK PCH
X V V V V X X X X
PCH_SMBDATA +3VALW_PCH X X +3VS +3VS X +3VALW_PCH
Reserve +3VS

PCH_RGBKB_SCL
X X X X X X X X X X X X X
PCH_RGBKB_SDA

EC_SMB_CK0 IT8226E V
EC_SMB_DA0 +3VALW X X X X X X X X X X +LDO_3V3 X

A A

EC SM Bus1 address EC SM Bus2 address PCH SM Bus address PCH I2C 2 Bus address
Device Address Device Address
Device Address Device Address
DDR DIMMA 1010 000X b RGB Backlight Need to update
Smart Battery 0X16 Thermal Sensor F75303M 1001_100x b
DDR DIMMB 1010 010X b
Charger 0001 0010 b VGA 0x9E (default)
TP Module Need to update
PCH Need to update
Wlan Reserved

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 Blank4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 4 of 74
5 4 3 2 1
5 4 3 2 1

[24] PCIE_CRX_GTX_N[0..15]

[24] PCIE_CRX_GTX_P[0..15]

PCIE_CTX_C_GRX_N[0..15] [24]

PCIE_CTX_C_GRX_P[0..15] [24]
D D

UC1C
PCIE_CRX_GTX_P15 E25 B25 PCIE_CTX_GRX_P15 OPT@ CC32 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P15
PCIE_CRX_GTX_N15 D25 PEG_RXP_0 PEG_TXP_0 A25 PCIE_CTX_GRX_N15 OPT@ CC16 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N15
PEG_RXN_0 PEG_TXN_0
PCIE_CRX_GTX_P14 E24 B24 PCIE_CTX_GRX_P14 OPT@ CC31 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P14
PCIE_CRX_GTX_N14 F24 PEG_RXP_1 PEG_TXP_1 C24 PCIE_CTX_GRX_N14 OPT@ CC15 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N14
PEG_RXN_1 PEG_TXN_1
PCIE_CRX_GTX_P13 E23 B23 PCIE_CTX_GRX_P13 OPT@ CC30 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P13
PCIE_CRX_GTX_N13 D23 PEG_RXP_2 PEG_TXP_2 A23 PCIE_CTX_GRX_N13 OPT@ CC14 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N13
PEG_RXN_2 PEG_TXN_2
PCIE_CRX_GTX_P12 E22 B22 PCIE_CTX_GRX_P12 OPT@ CC29 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P12
PCIE_CRX_GTX_N12 F22 PEG_RXP_3 PEG_TXP_3 C22 PCIE_CTX_GRX_N12 OPT@ CC13 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N12
PEG_RXN_3 PEG_TXN_3
PCIE_CRX_GTX_P11 E21 B21 PCIE_CTX_GRX_P11 OPT@ CC28 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P11
PCIE_CRX_GTX_N11 D21 PEG_RXP_4 PEG_TXP_4 A21 PCIE_CTX_GRX_N11 OPT@ CC12 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N11
PEG_RXN_4 PEG_TXN_4
PCIE_CRX_GTX_P10 E20 B20 PCIE_CTX_GRX_P10 OPT@ CC27 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P10
PCIE_CRX_GTX_N10 F20 PEG_RXP_5 PEG_TXP_5 C20 PCIE_CTX_GRX_N10 OPT@ CC11 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N10
PEG_RXN_5 PEG_TXN_5
PCIE_CRX_GTX_P9 E19 B19 PCIE_CTX_GRX_P9 OPT@ CC26 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P9
PCIE_CRX_GTX_N9 D19 PEG_RXP_6 PEG_TXP_6 A19 PCIE_CTX_GRX_N9 OPT@ CC10 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N9
PEG_RXN_6 PEG_TXN_6
PCIE_CRX_GTX_P8 E18 B18 PCIE_CTX_GRX_P8 OPT@ CC25 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P8
PCIE_CRX_GTX_N8 F18 PEG_RXP_7 PEG_TXP_7 C18 PCIE_CTX_GRX_N8 OPT@ CC9 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N8
C PEG_RXN_7 PEG_TXN_7 C
PCIE_CRX_GTX_P7 D17 A17 PCIE_CTX_GRX_P7 OPT@ CC24 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P7
PCIE_CRX_GTX_N7 E17 PEG_RXP_8 PEG_TXP_8 B17 PCIE_CTX_GRX_N7 OPT@ CC8 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N7
PEG_RXN_8 PEG_TXN_8
PCIE_CRX_GTX_P6 F16 C16 PCIE_CTX_GRX_P6 OPT@ CC23 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P6
PCIE_CRX_GTX_N6 E16 PEG_RXP_9 PEG_TXP_9 B16 PCIE_CTX_GRX_N6 OPT@ CC7 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N6
PEG_RXN_9 PEG_TXN_9
PCIE_CRX_GTX_P5 D15 A15 PCIE_CTX_GRX_P5 OPT@ CC22 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P5
PCIE_CRX_GTX_N5 E15 PEG_RXP_10 PEG_TXP_10 B15 PCIE_CTX_GRX_N5 OPT@ CC6 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N5
PEG_RXN_10 PEG_TXN_10
PCIE_CRX_GTX_P4 F14 C14 PCIE_CTX_GRX_P4 OPT@ CC21 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P4
PCIE_CRX_GTX_N4 E14 PEG_RXP_11 PEG_TXP_11 B14 PCIE_CTX_GRX_N4 OPT@ CC5 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N4
PEG_RXN_11 PEG_TXN_11
PCIE_CRX_GTX_P3 D13 A13 PCIE_CTX_GRX_P3 OPT@ CC20 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P3
PCIE_CRX_GTX_N3 E13 PEG_RXP_12 PEG_TXP_12 B13 PCIE_CTX_GRX_N3 OPT@ CC4 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N3
PEG_RXN_12 PEG_TXN_12
PCIE_CRX_GTX_P2 F12 C12 PCIE_CTX_GRX_P2 OPT@ CC19 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P2
PCIE_CRX_GTX_N2 E12 PEG_RXP_13 PEG_TXP_13 B12 PCIE_CTX_GRX_N2 OPT@ CC3 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N2
PEG_RXN_13 PEG_TXN_13
PCIE_CRX_GTX_P1 D11 A11 PCIE_CTX_GRX_P1 OPT@ CC18 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P1
PCIE_CRX_GTX_N1 E11 PEG_RXP_14 PEG_TXP_14 B11 PCIE_CTX_GRX_N1 OPT@ CC2 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N1
PEG_RXN_14 PEG_TXN_14
PCIE_CRX_GTX_P0 F10 C10 PCIE_CTX_GRX_P0 OPT@ CC17 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P0
VCCIO PCIE_CRX_GTX_N0 E10 PEG_RXP_15 PEG_TXP_15 B10 PCIE_CTX_GRX_N0 OPT@ CC1 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N0
PEG_RXN_15 PEG_TXN_15

RC1 2 1 24.9_0402_1% PEG_COMP G2


PEG_RCOMP
Note:
Place R_comp inside CPU cavity
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils. DMI_CRX_PTX_P0 D8 B8 DMI_CTX_PRX_P0
[19] DMI_CRX_PTX_P0 DMI_CRX_PTX_N0 DMI_RXP_0 DMI_TXP_0 DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 [19]
B E8 A8 B
[19] DMI_CRX_PTX_N0 DMI_RXN_0 DMI_TXN_0 DMI_CTX_PRX_N0 [19]
DMI_CRX_PTX_P1 E6 C6 DMI_CTX_PRX_P1
[19] DMI_CRX_PTX_P1 DMI_CRX_PTX_N1 DMI_RXP_1 DMI_TXP_1 DMI_CTX_PRX_N1 DMI_CTX_PRX_P1 [19]
F6 B6
[19] DMI_CRX_PTX_N1 DMI_RXN_1 DMI_TXN_1 DMI_CTX_PRX_N1 [19]
DMI_CRX_PTX_P2 D5 B5 DMI_CTX_PRX_P2
[19] DMI_CRX_PTX_P2 DMI_CRX_PTX_N2 DMI_RXP_2 DMI_TXP_2 DMI_CTX_PRX_N2 DMI_CTX_PRX_P2 [19]
E5 A5
[19] DMI_CRX_PTX_N2 DMI_RXN_2 DMI_TXN_2 DMI_CTX_PRX_N2 [19]
DMI_CRX_PTX_P3 J8 D4 DMI_CTX_PRX_P3
[19] DMI_CRX_PTX_P3 DMI_CRX_PTX_N3 DMI_RXP_3 3 OF 13 DMI_TXP_3 DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 [19]
J9 B4
[19] DMI_CRX_PTX_N3 DMI_RXN_3 DMI_TXN_3 DMI_CTX_PRX_N3 [19]
COFFEELAKE-H-CPU_BGA1440
@

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 CPU (1/7) DMI,PEG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 5 of 74
5 4 3 2 1
5 4 3 2 1

UC1E

[17]
[17]
PCH_CPU_BCLK
PCH_CPU_BCLK#
RC28
RC29
1
1
2 0_0402_5%
2 0_0402_5%
CPU_BCLK
CPU_BCLK#
B31
A32 BCLKP
BCLKN
CFG_0
CFG_1
CFG_2
BN25
BN27
BN26
CFG0
CFG1 @
CFG2
PAD 1
TC89
CFG STRAPS for CPU
RC15 1 2 0_0402_5% CPU_PCIBCLK D35 BN28 CFG3 Stall reset sequence after PCU PLL lock until de-asserted
VCCST [17] PCH_CPU_PCIBCLK CPU_PCIBCLK# C36 PCI_BCLKP CFG_3 BR20 CFG3 [42]
RC13 1 2 0_0402_5% CFG4
[17] PCH_CPU_PCIBCLK# PCI_BCLKN CFG_4 BM20 CFG5  Default ormal eration
[17] PCH_CPU_NSSC_CLK
RC17
RC16
1
1
2 0_0402_5%
2 0_0402_5%
CPU_NSSC_CLK
CPU_NSSC_CLK#
E31
D31 CLK24P
CFG_5
CFG_6
BT20
BP20
CFG6
CFG7
* o stall
[17] PCH_CPU_NSSC_CLK# CLK24N CFG_7 BR23 CFG8 @ PAD 1 CFG0
CFG_8 TC77
2

1 CFG_9
BR22 CFG9 @ PAD 1
TC78 0 Stall
RC66 RC76 BT23 CFG10@ PAD 1
56.2_0402_1% CFG_10 TC79
C10225 100_0402_1% BT22 CFG11@ PAD 1
0.1U_0201_6.3V7-K CFG_11 TC80
BM19 CFG12@ PAD 1 Reserved configuration lane
2 CFG_12 TC81
@ BR19 CFG13@ PAD 1
TC82
1

D CFG_13 BP19 1 D
CFG14@ PAD
CFG_14 TC83
RC65 1 2 220_0402_5% VR_SVID_ALRT#_R BH31 BT19 CFG15@ PAD 1
[65] SVID_ALERT# VIDALERT# CFG_15 TC84
RC3 1 2 0_0402_5% VR_SVID_CLK BH32 /A
[65] SVID_CLK
RC14 1 2 0_0402_5% VR_SVID_DAT BH29 VIDSCK BN23 @ PAD 1 CFG1
[65] SVID_DATA VIDSOUT CFG_17 TC85
RC9 1 2 499_0402_1% H_PROCHOT#_R BR30 BP23 @ PAD 1
[49,65] H_PROCHOT# PROCHOT# CFG_16 TC86
BP22 @ PAD 1
CFG_19 TC87
RC7 1 2 1K_0201_5% CC178 1 2 .1U_0402_10V6-K DDR_PG_CTRL BT13 BN22 @ PAD 1
VCCSTG DDR_VTT_CNTL CFG_18 TC88
@ PCI ress Static Lane umbering Reversal

 

 
 

 



 

 

 

 



 
 
 
BR27 @ PAD 1
BPM#_0 TC27
BT27 @ PAD 1
BPM#_1 TC28
BM31 @ PAD 1








 






VCCST_PWRGD H13 BPM#_2 BT30 @ PAD 1
TC29 CFG2
VCCST_PWRGD BPM#_3 TC42

[16] H_CPUPWRGD
RC32 1 2 1/20W_22_5%_0201 CPUPWRGOOD_R BT31
PROCPWRGD
*
RC22 1 2 0_0201_5% BUF_CPU_RST# BP35 BT28
[14] CPU_PLTRST# H_PM_SYNC BM34 RESET# PROC_TDO BL32 PROC_TDO [42]
[14] H_PM_SYNC PM_SYNC PROC_TDI PROC_TDI [42] Reserved configuration lane
RC33 1 2 20_0402_5% H_PM_DOWN_R BP31 BP28
[14] H_PM_DOWN EC_PECI BT34 PM_DOWN PROC_TMS BR28 PROC_TMS [42]
[14,49] EC_PECI THRMTRIP#_CPU J31 PECI PROC_TCK PROC_TCK [42]
RC34 1 2 0_0402_5%
[14,24] H_THRMTRIP# THERMTRIP# BP30
PROC_TRST# PROC_TRST# [42] CFG3 /A
RC11 1 2 1K_0402_5% BR33 BL30
VCCST SKTOCC# PROC_PREQ# PROC_PREQ# [42]
BN1 BP27
PROC_SELECT# PROC_PRDY# PROC_PRDY# [42]
RC174 1 @ 2 10K_0402_5% H_CATERR# BM30
CATERR# BT25
CFG_RCOMP eDP enable
33P_0402_50V8J

.1U_0402_10V6-K
.1U_0402_10V6-K

1 1 1 AT13
ZVM# 2
CC177
CC176
CC175

AW13
MSM#
 Disabled
AU13 RC175
2 @2 @2 AY13 RSVD1 49.9_0402_1%
RSVD2 CFG4  0 nabled
*
1

5 OF 13 close to CPU
COFFEELAKE-H-CPU_BGA1440 PCI ress Bifurcation
+3VALW +3VS @

C  00 PCI ress C
UC1M
CFG[6:5]
2

 0 reserved
RC177 RC178
+1.2V 100K_0402_5% 100K_0402_5% E2
RSVD_TP5 VCCST  0 PCI ress
@ 1 PAD @ E3
TC111 IST_TRIG
E1
* PCI ress
1

D1 RSVD_TP4
RSVD_TP3
1

SM_PG_CTRL
SM_PG_CTRL [61]
1

RC18 BR1 BK28 P G Training


1K_0402_5% BT2 RSVD_TP1 RSVD11 BJ28 RC57
RSVD_TP2 RSVD10 51_0402_5%
*
1

C BN35 @  default P G Train immediately


2

2 QC1 RSVD15
following R S T# deassertion
2

B MMBT3904WH_SOT323-3 J24
RSVD28
H24 CFG7 0 P G Wait for BI S for training
3

BN33 RSVD27
DDR_PG_CTRL BL34 RSVD14 PROC_PREQ#
RSVD13
N29 Reserved configuration lane
R14 RSVD30
RSVD31 VCCSTG
2

AE29
RSVD33
RC179
10K_0402_5%
AA14
AP29 RSVD32 CFG[19:8] /A
@ AP14 RSVD5
RSVD4
2

R10439 1 2 0_0402_5% A36


1

VSS_A36 R10455
R10440 1 2 0_0402_5% A37 51_0402_1%
Debug Pin VSS_A37 @
Logic Buffer CPU_TRIGIN H23
[22] CPU_TRIGIN
1

PCH_TRIGIN RC4 1 2 30_0402_5% CPU_TRIGOUT J23 PROC_TRIGIN


[22] PCH_TRIGIN PROC_TRIGOUT
1 F30
CC174 RSVD24 PROC_TDO
.1U_0402_10V6-K
@ E30
2 RSVD23

B B
B30 BL31
C30 RSVD7 RSVD12 AJ8
RSVD21 RSVD3 G13
RSVD25
G3 VCCIO
J3 RSVD26 C38
RSVD29 RSVD22 C1
RSVD20 BR2
BR35 RSVD17 BP1
BR31 RSVD19 RSVD16 B38
+3VS +3VALW VCCST BH30 RSVD18 RSVD8 B2
RSVD9 RSVD6
13 OF 13
1

COFFEELAKE-H-CPU_BGA1440
RC75 @
2

1
2

1
1K_0402_5%
R292 R291 RC139 RC140 RC141 RC142 RC143 RC144
10K_0402_5% 10K_0402_5% 1K_0201_5% 1K_0201_5% 1K_0201_5% 1K_0201_5% 1K_0201_5% 1K_0201_5%
2

@ @ @ @ @ @ @
1

2
1

RC50 1 2 60.4_0402_1% VCCST_PWRGD


CFG3
CFG1 CFG7
CFG6
1

CC179 CFG5
330P_0402_50V8J CFG4
1

Q1 D Q2 D CFG2
2

CPUCORE_ON 2 2 CFG0
[49,65] CPUCORE_ON G G
1

1
1

L2N7002KWT1G_SOT323-3 S S L2N7002KWT1G_SOT323-3 RC185 RC146


1
3

CC33 1K_0201_5% 1K_0201_5% RC56 RC53 RC54 RC52 RC51 RC55


0.022U_0402_16V7-K @ @ 1K_0201_5% 1K_0201_5% 1K_0201_5% 1K_0201_5% 1K_0201_5% 1K_0201_5%
@ @ @ @ @
2

2
2

2
2

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 CPU (2/7) PM, XDP, CLK, CFG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 6 of 74
5 4 3 2 1
5 4 3 2 1

DDRA_DQ[0..63] [12]
UC1A
DDRB_DQ[0..63] [13]
AG1 BR6 DDRA_DQ0 UC1B
[12] DDRA_CLK0 DDR0_CKP_0/DDR0_CKP_0 DDR0_DQ_0/DDR0_DQ_0 AM9 DDRB_DQ0
AG2 BT6 DDRA_DQ1 BT11
[12] DDRA_CLK0# DDR0_CKN_0/DDR0_CKN_0 DDR0_DQ_1/DDR0_DQ_1 [13] DDRB_CLK0 AN9 DDR1_CKP_0/DDR1_CKP_0 DDR1_DQ_0/DDR0_DQ_16 BR11 DDRB_DQ1
AK2 BP3 DDRA_DQ2
[12] DDRA_CLK1 DDR0_CKP_1/DDR0_CKP_1 DDR0_DQ_2/DDR0_DQ_2 [13] DDRB_CLK0# AM7 DDR1_CKN_0/DDR1_CKN_0 DDR1_DQ_1/DDR0_DQ_17 BT9 DDRB_DQ2
AK1 BR3 DDRA_DQ3
[12] DDRA_CLK1# DDR0_CKN_1/DDR0_CKN_1 DDR0_DQ_3/DDR0_DQ_3 [13] DDRB_CLK1 AM8 DDR1_CKP_1/DDR1_CKP_1 DDR1_DQ_2/DDR0_DQ_18 DDRB_DQ3
AL3 BN5 DDRA_DQ4 BR8
NC/DDR0_CKP_2 DDR0_DQ_4/DDR0_DQ_4 [13] DDRB_CLK1# AM11 DDR1_CKN_1/DDR1_CKN_1 DDR1_DQ_3/DDR0_DQ_19 BP11 DDRB_DQ4
AK3 BP6 DDRA_DQ5
AL2 NC/DDR0_CKN_2 DDR0_DQ_5/DDR0_DQ_5 BP2 DDRA_DQ6 AM10 NC/DDR1_CKP_2 DDR1_DQ_4/DDR0_DQ_20 BN11 DDRB_DQ5
AL1 NC/DDR0_CKP_3 DDR0_DQ_6/DDR0_DQ_6 BN3 DDRA_DQ7 AJ10 NC/DDR1_CKN_2 DDR1_DQ_5/DDR0_DQ_21 BP8 DDRB_DQ6
D NC/DDR0_CKN_3 DDR0_DQ_7/DDR0_DQ_7 BL4 DDRA_DQ8 AJ11 NC/DDR1_CKP_3 DDR1_DQ_6/DDR0_DQ_22 BN8 DDRB_DQ7 D
AT1 DDR0_DQ_8/DDR0_DQ_8 BL5 DDRA_DQ9 NC/DDR1_CKN_3 DDR1_DQ_7/DDR0_DQ_23 BL12 DDRB_DQ8
[12] DDRA_CKE0 DDR0_CKE_0/DDR0_CKE_0 DDR0_DQ_9/DDR0_DQ_9 AT8 DDR1_DQ_8/DDR0_DQ_24 BL11 DDRB_DQ9
AT2 BL2 DDRA_DQ10
[12] DDRA_CKE1 DDR0_CKE_1/DDR0_CKE_1 DDR0_DQ_10/DDR0_DQ_10 [13] DDRB_CKE0 AT10 DDR1_CKE_0/DDR1_CKE_0 DDR1_DQ_9/DDR0_DQ_25 BL8 DDRB_DQ10
AT3 BM1 DDRA_DQ11
DDR0_CKE_2/DDR0_CKE_2 DDR0_DQ_11/DDR0_DQ_11 [13] DDRB_CKE1 AT7 DDR1_CKE_1/DDR1_CKE_1 DDR1_DQ_10/DDR0_DQ_26 BJ8 DDRB_DQ11
AT5 BK4 DDRA_DQ12
DDR0_CKE_3/DDR0_CKE_3 DDR0_DQ_12/DDR0_DQ_12 BK5 DDRA_DQ13 AT11 DDR1_CKE_2/DDR1_CKE_2 DDR1_DQ_11/DDR0_DQ_27 BJ11 DDRB_DQ12
AD5 DDR0_DQ_13/DDR0_DQ_13 BK1 DDRA_DQ14 DDR1_CKE_3/DDR1_CKE_3 DDR1_DQ_12/DDR0_DQ_28 BJ10 DDRB_DQ13
[12] DDRA_CS0# DDR0_CS#_0/DDR0_CS#_0 DDR0_DQ_14/DDR0_DQ_14 DDR1_DQ_13/DDR0_DQ_29 DDRB_DQ14
AE2 BK2 DDRA_DQ15 AF11 BL7
[12] DDRA_CS1# DDR0_CS#_1/DDR0_CS#_1 DDR0_DQ_15/DDR0_DQ_15 [13] DDRB_CS0# AE7 DDR1_CS#_0/DDR1_CS#_0 DDR1_DQ_14/DDR0_DQ_30 BJ7 DDRB_DQ15
AD2 BG4 DDRA_DQ16
NC/DDR0_CS#_2 DDR0_DQ_16/DDR0_DQ_32 DDRA_DQ17 [13] DDRB_CS1# DDR1_CS#_1/DDR1_CS#_1 DDR1_DQ_15/DDR0_DQ_31 DDRB_DQ16
AE5 BG5 AF10 BG11
NC/DDR0_CS#_3 DDR0_DQ_17/DDR0_DQ_33 BF4 DDRA_DQ18 AE10 NC/DDR1_CS#_2 DDR1_DQ_16/DDR0_DQ_48 BG10 DDRB_DQ17
DDRA_ODT0 AD3 DDR0_DQ_18/DDR0_DQ_34 BF5 DDRA_DQ19 NC/DDR1_CS#_3 DDR1_DQ_17/DDR0_DQ_49 BG8 DDRB_DQ18
[12] DDRA_ODT0 DDR0_ODT_0/DDR0_ODT_0 DDR0_DQ_19/DDR0_DQ_35 DDR1_DQ_18/DDR0_DQ_50 BF8 DDRB_DQ19
DDRA_ODT1 AE4 BG2 DDRA_DQ20 DDRB_ODT0 AF7
[12] DDRA_ODT1 NC/DDR0_ODT_1 DDR0_DQ_20/DDR0_DQ_36 [13] DDRB_ODT0 AE8 DDR1_ODT_0/DDR1_ODT_0 DDR1_DQ_19/DDR0_DQ_51
AE1 BG1 DDRA_DQ21 DDRB_ODT1 BF11 DDRB_DQ20
NC/DDR0_ODT_2 DDR0_DQ_21/DDR0_DQ_37 [13] DDRB_ODT1 AE9 NC/DDR1_ODT_1 DDR1_DQ_20/DDR0_DQ_52 BF10 DDRB_DQ21
AD4 BF1 DDRA_DQ22
NC/DDR0_ODT_3 DDR0_DQ_22/DDR0_DQ_38 BF2 DDRA_DQ23 AE11 NC/DDR1_ODT_2 DDR1_DQ_21/DDR0_DQ_53 BG7 DDRB_DQ22
AH5 DDR0_DQ_23/DDR0_DQ_39 BD2 DDRA_DQ24 NC/DDR1_ODT_3 DDR1_DQ_22/DDR0_DQ_54 BF7 DDRB_DQ23
[12] DDRA_BA0 DDR0_CAB_4/DDR0_BA_0 DDR0_DQ_24/DDR0_DQ_40 AH10 DDR1_DQ_23/DDR0_DQ_55 BB11 DDRB_DQ24
AH1 BD1 DDRA_DQ25
[12] DDRA_BA1 DDR0_CAB_6/DDR0_BA_1 DDR0_DQ_25/DDR0_DQ_41 [13] DDRB_MA16_RAS# DDR1_CAB_3/DDR1_MA_16 DDR1_DQ_24/DDR0_DQ_56 DDRB_DQ25
AU1 BC4 DDRA_DQ26 AH11 BC11
[12] DDRA_BG0 DDR0_CAA_5/DDR0_BG_0 DDR0_DQ_26/DDR0_DQ_42 [13] DDRB_MA14_WE# DDR1_CAB_2/DDR1_MA_14 DDR1_DQ_25/DDR0_DQ_57 DDRB_DQ26
BC5 DDRA_DQ27 AF8 BB8
DDR0_DQ_27/DDR0_DQ_43 DDRA_DQ28 [13] DDRB_MA15_CAS# DDR1_CAB_1/DDR1_MA_15 DDR1_DQ_26/DDR0_DQ_58 BC8 DDRB_DQ27
AH4 BD5
[12] DDRA_MA16_RAS# DDR0_CAB_3/DDR0_MA_16 DDR0_DQ_28/DDR0_DQ_44 DDRA_DQ29 DDR1_DQ_27/DDR0_DQ_59 DDRB_DQ28
AG4 BD4 AH8 BC10
[12] DDRA_MA14_WE# DDR0_CAB_2/DDR0_MA_14 DDR0_DQ_29/DDR0_DQ_45 DDRA_DQ30 [13] DDRB_BA0 AH9 DDR1_CAB_4/DDR1_BA_0 DDR1_DQ_28/DDR0_DQ_60 BB10 DDRB_DQ29
AD1 BC1
[12] DDRA_MA15_CAS# DDR0_CAB_1/DDR0_MA_15 DDR0_DQ_30/DDR0_DQ_46 DDRA_DQ31 [13] DDRB_BA1 DDR1_CAB_6/DDR1_BA_1 DDR1_DQ_29/DDR0_DQ_61 BC7 DDRB_DQ30
BC2 AR9
[12] DDRA_MA[0..9] DDR0_DQ_31/DDR0_DQ_47 [13] DDRB_BG0 DDR1_CAA_5/DDR1_BG_0 DDR1_DQ_30/DDR0_DQ_62 BB7 DDRB_DQ31
DDRA_MA0 AH3 AB1 DDRA_DQ32
DDR0_CAB_9/DDR0_MA_0 DDR0_DQ_32/DDR1_DQ_0 DDRA_DQ33 [13] DDRB_MA[0..9] DDR1_DQ_31/DDR0_DQ_63 AA11 DDRB_DQ32
DDRA_MA1 AP4 AB2 DDRB_MA0 AJ9
DDRA_MA2 AN4 DDR0_CAB_8/DDR0_MA_1 DDR0_DQ_33/DDR1_DQ_1 AA4 DDRA_DQ34 DDRB_MA1 AK6 DDR1_CAB_9/DDR1_MA_0 DDR1_DQ_32/DDR1_DQ_16 AA10 DDRB_DQ33
DDRA_MA3 AP5 DDR0_CAB_5/DDR0_MA_2 DDR0_DQ_34/DDR1_DQ_2 AA5 DDRA_DQ35 DDRB_MA2 AK5 DDR1_CAB_8/DDR1_MA_1 DDR1_DQ_33/DDR1_DQ_17 AC11 DDRB_DQ34
DDRA_MA4 AP2 NC/DDR0_MA_3 DDR0_DQ_35/DDR1_DQ_3 AB5 DDRA_DQ36 DDRB_MA3 AL5 DDR1_CAB_5/DDR1_MA_2 DDR1_DQ_34/DDR1_DQ_18 AC10 DDRB_DQ35
DDRA_MA5 AP1 NC/DDR0_MA_4 DDR0_DQ_36/DDR1_DQ_4 AB4 DDRA_DQ37 DDRB_MA4 AL6 NC/DDR1_MA_3 DDR1_DQ_35/DDR1_DQ_19 AA7 DDRB_DQ36
DDRA_MA6 AP3 DDR0_CAA_0/DDR0_MA_5 DDR0_DQ_37/DDR1_DQ_5 AA2 DDRA_DQ38 DDRB_MA5 AM6 NC/DDR1_MA_4 DDR1_DQ_36/DDR1_DQ_20 AA8 DDRB_DQ37
DDRA_MA7 AN1 DDR0_CAA_2/DDR0_MA_6 DDR0_DQ_38/DDR1_DQ_6 AA1 DDRA_DQ39 DDRB_MA6 AN7 DDR1_CAA_0/DDR1_MA_5 DDR1_DQ_37/DDR1_DQ_21 AC8 DDRB_DQ38
DDRA_MA8 AN3 DDR0_CAA_4/DDR0_MA_7 DDR0_DQ_39/DDR1_DQ_7 V5 DDRA_DQ40 DDRB_MA7 AN10 DDR1_CAA_2/DDR1_MA_6 DDR1_DQ_38/DDR1_DQ_22 AC7 DDRB_DQ39
DDRA_MA9 AT4 DDR0_CAA_3/DDR0_MA_8 DDR0_DQ_40/DDR1_DQ_8 V2 DDRA_DQ41 DDR1_CAA_4/DDR1_MA_7 DDR1_DQ_39/DDR1_DQ_23
DDRA_MA10_AP AH2 DDR0_CAA_1/DDR0_MA_9 DDR0_DQ_41/DDR1_DQ_9 U1 DDRA_DQ42 DDRB_MA8 AN8 W8 DDRB_DQ40
[12] DDRA_MA10_AP DDR0_CAB_7/DDR0_MA_10 DDR0_DQ_42/DDR1_DQ_10 DDRA_DQ43 AR11 DDR1_CAA_3/DDR1_MA_8 DDR1_DQ_40/DDR1_DQ_24 DDRB_DQ41
DDRA_MA11 AN2 U2 DDRB_MA9 W7
[12] DDRA_MA11 DDR0_CAA_7/DDR0_MA_11 DDR0_DQ_43/DDR1_DQ_11 DDRA_DQ44 DDR1_CAA_1/DDR1_MA_9 DDR1_DQ_41/DDR1_DQ_25 DDRB_DQ42
DDRA_MA12 AU4 V1 DDRB_MA10_AP AH7 V10
[12] DDRA_MA12 DDR0_CAA_6/DDR0_MA_12 DDR0_DQ_44/DDR1_DQ_12 DDRA_DQ45 [13] DDRB_MA10_AP DDR1_CAB_7/DDR1_MA_10 DDR1_DQ_42/DDR1_DQ_26 DDRB_DQ43
C DDRA_MA13 AE3 V4 DDRB_MA11 AN11 V11 C
[12] DDRA_MA13 DDR0_CAB_0/DDR0_MA_13 DDR0_DQ_45/DDR1_DQ_13 DDRA_DQ46 [13] DDRB_MA11 DDR1_CAA_7/DDR1_MA_11 DDR1_DQ_43/DDR1_DQ_27 DDRB_DQ44
DDRA_BG1 AU2 U5 DDRB_MA12 AR10 W11
[12] DDRA_BG1 DDR0_CAA_9/DDR0_BG_1 DDR0_DQ_46/DDR1_DQ_14 DDRA_DQ47 [13] DDRB_MA12 AF9 DDR1_CAA_6/DDR1_MA_12 DDR1_DQ_44/DDR1_DQ_28 DDRB_DQ45
DDRA_ACT# AU3 U4 DDRB_MA13 W10
[12] DDRA_ACT# DDR0_CAA_8/DDR0_ACT# DDR0_DQ_47/DDR1_DQ_15 DDRA_DQ48 [13] DDRB_MA13 AR7 DDR1_CAB_0/DDR1_MA_13 DDR1_DQ_45/DDR1_DQ_29 V7 DDRB_DQ46
R2 DDRB_BG1
DDR0_DQ_48/DDR1_DQ_32 DDRA_DQ49 [13] DDRB_BG1 AT9 DDR1_CAA_9/DDR1_BG_1 DDR1_DQ_46/DDR1_DQ_30 DDRB_DQ47
DDRA_PARITY AG3 P5 DDRB_ACT# V8
[12] DDRA_PARITY NC/DDR0_PAR DDR0_DQ_49/DDR1_DQ_33 DDRA_DQ50 [13] DDRB_ACT# DDR1_CAA_8/DDR1_ACT# DDR1_DQ_47/DDR1_DQ_31 DDRB_DQ48
DDRA_ALERT# AU5 R4 R11
[12] DDRA_ALERT# NC/DDR0_ALERT# DDR0_DQ_50/DDR1_DQ_34 DDRA_DQ51 DDR1_DQ_48/DDR1_DQ_48 DDRB_DQ49
P4 DDRB_PARITY AJ7 P11
DDR0_DQ_51/DDR1_DQ_35 DDRA_DQ52 [13] DDRB_PARITY NC/DDR1_PAR DDR1_DQ_49/DDR1_DQ_49 DDRB_DQ50
R5 DDRB_ALERT# AR8 P7
[12] DDRA_DQS#[0..7] DDR0_DQ_52/DDR1_DQ_36 DDRA_DQ53 [13] DDRB_ALERT# NC/DDR1_ALERT# DDR1_DQ_50/DDR1_DQ_50 DDRB_DQ51
DDRA_DQS#0 BR5 P2 R8
DDRA_DQS#1 BL3 DDR0_DQSN_0/DDR0_DQSN_0DDR0_DQ_53/DDR1_DQ_37 R1 DDRA_DQ54 DDR1_DQ_51/DDR1_DQ_51 R10 DDRB_DQ52
DDR0_DQSN_1/DDR0_DQSN_1DDR0_DQ_54/DDR1_DQ_38 DDRA_DQ55 [13] DDRB_DQS#[0..7] BN9 DDR1_DQ_52/DDR1_DQ_52 DDRB_DQ53
DDRA_DQS#2 BG3 P1 DDRB_DQS#0 P10
DDRA_DQS#3 BD3 DDR0_DQSN_2/DDR0_DQSN_4DDR0_DQ_55/DDR1_DQ_39 M4 DDRA_DQ56 DDRB_DQS#1 BL9 DDR1_DQSN_0/DDR0_DQSN_2DDR1_DQ_53/DDR1_DQ_53 R7 DDRB_DQ54
DDRA_DQS#4 AA3 DDR0_DQSN_3/DDR0_DQSN_5DDR0_DQ_56/DDR1_DQ_40 M1 DDRA_DQ57 DDRB_DQS#2 BG9 DDR1_DQSN_1/DDR0_DQSN_3DDR1_DQ_54/DDR1_DQ_54 P8 DDRB_DQ55
DDRA_DQS#5 U3 DDR0_DQSN_4/DDR1_DQSN_0DDR0_DQ_57/DDR1_DQ_41 L4 DDRA_DQ58 DDRB_DQS#3 BC9 DDR1_DQSN_2/DDR0_DQSN_6DDR1_DQ_55/DDR1_DQ_55 L11 DDRB_DQ56
DDRA_DQS#6 P3 DDR0_DQSN_5/DDR1_DQSN_1DDR0_DQ_58/DDR1_DQ_42 L2 DDRA_DQ59 DDRB_DQS#4 AC9 DDR1_DQSN_3/DDR0_DQSN_7DDR1_DQ_56/DDR1_DQ_56 M11 DDRB_DQ57
DDRA_DQS#7 L3 DDR0_DQSN_6/DDR1_DQSN_4DDR0_DQ_59/DDR1_DQ_43 M5 DDRA_DQ60 DDRB_DQS#5 W9 DDR1_DQSN_4/DDR1_DQSN_2DDR1_DQ_57/DDR1_DQ_57 L7 DDRB_DQ58
DDR0_DQSN_7/DDR1_DQSN_5DDR0_DQ_60/DDR1_DQ_44 M2 DDRA_DQ61 DDRB_DQS#6 R9 DDR1_DQSN_5/DDR1_DQSN_3DDR1_DQ_58/DDR1_DQ_58 M8 DDRB_DQ59
[12] DDRA_DQS[0..7] DDR0_DQ_61/DDR1_DQ_45 DDRA_DQ62 DDR1_DQSN_6/DDR1_DQSN_6DDR1_DQ_59/DDR1_DQ_59 DDRB_DQ60
DDRA_DQS0 BP5 L5 DDRB_DQS#7 M9 L10
DDRA_DQS1 BK3 DDR0_DQSP_0/DDR0_DQSP_0DDR0_DQ_62/DDR1_DQ_46 L1 DDRA_DQ63 DDR1_DQSN_7/DDR1_DQSN_7DDR1_DQ_60/DDR1_DQ_60 M10 DDRB_DQ61
DDRA_DQS2 DDR0_DQSP_1/DDR0_DQSP_1DDR0_DQ_63/DDR1_DQ_47 [13] DDRB_DQS[0..7] BP9 DDR1_DQ_61/DDR1_DQ_61 DDRB_DQ62
BF3 DDRB_DQS0 M7
DDRA_DQS3 BC3 DDR0_DQSP_2/DDR0_DQSP_4 BA2 DDRB_DQS1 BJ9 DDR1_DQSP_0/DDR0_DQSP_2DDR1_DQ_62/DDR1_DQ_62 L8 DDRB_DQ63
DDRA_DQS4 AB3 DDR0_DQSP_3/DDR0_DQSP_5 NC/DDR0_ECC_0 BA1 DDRB_DQS2 BF9 DDR1_DQSP_1/DDR0_DQSP_3DDR1_DQ_63/DDR1_DQ_63
DDRA_DQS5 V3 DDR0_DQSP_4/DDR1_DQSP_0 NC/DDR0_ECC_1 AY4 DDRB_DQS3 BB9 DDR1_DQSP_2/DDR0_DQSP_6 AW11
DDRA_DQS6 R3 DDR0_DQSP_5/DDR1_DQSP_1 NC/DDR0_ECC_2 AY5 DDRB_DQS4 AA9 DDR1_DQSP_3/DDR0_DQSP_7 NC/DDR1_ECC_0 AY11
DDRA_DQS7 M3 DDR0_DQSP_6/DDR1_DQSP_4 NC/DDR0_ECC_3 BA5 DDRB_DQS5 V9 DDR1_DQSP_4/DDR1_DQSP_2 NC/DDR1_ECC_1 AY8
DDR0_DQSP_7/DDR1_DQSP_5 NC/DDR0_ECC_4 BA4 DDRB_DQS6 P9 DDR1_DQSP_5/DDR1_DQSP_3 NC/DDR1_ECC_2 AW8
AY3 DDR CHANNEL A NC/DDR0_ECC_5 AY1 DDRB_DQS7 L9 DDR1_DQSP_6/DDR1_DQSP_6 NC/DDR1_ECC_3 AY10
BA3 DDR0_DQSP_8/DDR0_DQSP_8 NC/DDR0_ECC_6 AY2 DDR1_DQSP_7/DDR1_DQSP_7 NC/DDR1_ECC_4 AW10
1 OF 13
DDR0_DQSN_8/DDR0_DQSN_8 NC/DDR0_ECC_7 AW9 NC/DDR1_ECC_5 AY7
COFFEELAKE-H-CPU_BGA1440 AY9 DDR1_DQSP_8/DDR1_DQSP_8 NC/DDR1_ECC_6 AW7
DDR1_DQSN_8/DDR1_DQSN_8 NC/DDR1_ECC_7
@

+V_DDR_REFA_R BN13 G1 SM_RCOMP0


+V_DDR_REF_R BP13 DDR_VREF_CA DDR CHANNEL B DDR_RCOMP_0 H1 SM_RCOMP1
+V_DDR_REFB_R BR13 DDR0_VREF_DQ DDR_RCOMP_1 J2 SM_RCOMP2
2 OF 13
B DDR1_VREF_DQ DDR_RCOMP_2 B
COFFEELAKE-H-CPU_BGA1440
@

+VREF_CA_DIMMA_R RC1471 2 0_0402_5% +V_DDR_REFA_R


PAD @ TC109 1 +VREF_DQ_DIMM_R RC36 1 2 0_0402_5% @ +V_DDR_REF_R
+VREF_DQ_DIMMB_R RC37 1 @ 2 0_0402_5% +V_DDR_REFB_R

CAD Note: @
Trace width= 20 mil, Spcing=20 mils
DDR_VR F_CA : Connected to VR F_CA on DIMM CH-A
DDR0_VR F_DQ : C
DDR _VR F_DQ : Connected to VR F_CA on DIMM CH-B

DDR4 COMPENSATION SIGNALS


SM_RCOMP0 RC5 1 2 121_0402_1%

SM_RCOMP1 RC6 1 2 75_0402_1%

SM_RCOMP2 RC8 1 2 100_0402_1%

CAD Note:
A
Trace width=12~15 mil, Spcing=20 mils A
Max trace length= 500 mil

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 CPU (3/7) DDRVI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 7 of 74
5 4 3 2 1
5 4 3 2 1

UC1D

D K36 D29 CPU_EDP_TX0+ D


DDI1_TXP_0 EDP_TXP_0 CPU_EDP_TX0- CPU_EDP_TX0+ [35]
K37 E29
DDI1_TXN_0 EDP_TXN_0 CPU_EDP_TX1+ CPU_EDP_TX0- [35]
J35 F28
DDI1_TXP_1 EDP_TXP_1 CPU_EDP_TX1- CPU_EDP_TX1+ [35]
J34 E28
DDI1_TXN_1 EDP_TXN_1 CPU_EDP_TX2+ CPU_EDP_TX1- [35]
H37 A29
DDI1_TXP_2 EDP_TXP_2 CPU_EDP_TX2- CPU_EDP_TX2+ [35]
H36 B29
DDI1_TXN_2 EDP_TXN_2 CPU_EDP_TX3+ CPU_EDP_TX2- [35]
J37 C28
DDI1_TXP_3 EDP_TXP_3 CPU_EDP_TX3- CPU_EDP_TX3+ [35]
J38 B28
DDI1_TXN_3 EDP_TXN_3 CPU_EDP_TX3- [35]
D27 C26 CPU_EDP_AUX
DDI1_AUXP EDP_AUXP CPU_EDP_AUX# CPU_EDP_AUX [35]
E27 B26
DDI1_AUXN EDP_AUXN CPU_EDP_AUX# [35]
H34
H33 DDI2_TXP_0
F37 DDI2_TXN_0 A33 VCCIO
G38 DDI2_TXP_1 EDP_DISP_UTIL
F34 DDI2_TXN_1
F35 DDI2_TXP_2 D37 EDP_COMP 2 1
E37 DDI2_TXN_2 DISP_RCOMP 24.9_0402_1% RC49
DDI2_TXP_3
E36
DDI2_TXN_3 COMPENSATION FOR DDI interface
F26
E26 DDI2_AUXP CAD Note:Trace width=20 mils ,Spacing=25mil,
DDI2_AUXN
Max length=100 mils.
C34
D34 DDI3_TXP_0
B36 DDI3_TXN_0
B34 DDI3_TXP_1
C F33 DDI3_TXN_1 C
E33 DDI3_TXP_2
C33 DDI3_TXN_2
B33 DDI3_TXP_3
DDI3_TXN_3 G27 PROC_AUDIO_CLK_CPU
PROC_AUDIO_CLK PROC_AUDIO_CLK_CPU [16]
A27 G25 PROC_AUDIO_SDO_CPU PROC_AUDIO_SDO_CPU [16]
B27 DDI3_AUXP PROC_AUDIO_SDI G29 PROC_AUDIO_SDI_CPU_R RC180 1 2 20_0402_5%
DDI3_AUXN PROC_AUDIO_SDO PROC_AUDIO_SDI_CPU [16]
4 of 13
Place near CPU
COFFEELAKE-H-CPU_BGA1440
@
1

RH762
33_0402_5%
@
2

1
CH264
10P_0402_50V8J
2@

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 CPU (4/7) eDP, DDI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A3 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 8 of 74
5 4 3 2 1
5 4 3 2 1

VCCGFXCORE VCCGFXCORE
VCCCPUCORE VCCCPUCORE VCCCPUCORE
UC1J VCCCPUCORE UC1K
UC1I AT14 BD35
AA13 AH13 AT31 VCCGT1 VCCGT80 BD36
K14 W35
AA31 VCC1 VCC64 AH14 VCC125 VCC188 AT32 VCCGT2 VCCGT81 BE31
L13 W36
VCC2 VCC65 AH29 VCC126 VCC189 AT33 VCCGT3 VCCGT82 BE32
AA32 L14 W37
VCC3 VCC66 VCC127 VCC190 AT34 VCCGT4 VCCGT83 BE33
AA33 AH30 N13 W38
VCC4 VCC67 VCC128 VCC191 AT35 VCCGT5 VCCGT84 BE34
AA34 AH31 N14 Y29
AA35 VCC5 VCC68 AH32 VCC129 VCC192 AT36 VCCGT6 VCCGT85 BE35
N30 Y30
AA36 VCC6 VCC69 VCC130 VCC193 AT37 VCCGT7 VCCGT86 BE36
AJ14 N31 Y31
AA37 VCC7 VCC70 VCC131 VCC194 AT38 VCCGT8 VCCGT87 BE37
AJ29 N32 Y32
AA38 VCC8 VCC71 AJ30 VCC132 VCC195 AU14 VCCGT9 VCCGT88 BE38
N35 Y33
AB29 VCC9 VCC72 AJ31 VCC133 VCC196 AU29 VCCGT10 VCCGT89 BF13 CRB lace to CPU
N36 Y34
AB30 VCC10 VCC73 AJ32 VCC134 VCC197 AU30 VCCGT11 VCCGT90 BF14
N37 Y35
AB31 VCC11 VCC74 AJ33 VCC135 VCC198 AU31 VCCGT12 VCCGT91 BF29 VCCGFXCORE
N38 Y36
AB32
AB35
VCC12
VCC13
VCC75
VCC76
AJ34
AJ35
P13
P14
VCC136
VCC137
VCC199 AU32
AU35
VCCGT13
VCCGT14
VCCGT15
VCCGT92
VCCGT93
VCCGT94
BF30
BF31 VCCGT_SENSE

1
AB36 VCC14 VCC77 AJ36 P29 VCC138 AU36 BF32 RC60
VCC15 VCC78 VCC139 AU37 VCCGT16 VCCGT95 BF35 100_0402_1%
AB37 AK31 P30
VCC16 VCC79 VCC140 AU38 VCCGT17 VCCGT96 BF36
AB38 AK32 P31
VCC17 VCC80 VCC141 AV29 VCCGT18 VCCGT97 BF37
AC13 AK33 P32
AC14 VCC18 VCC81 VCC142 AV30 VCCGT19 VCCGT98 BF38
D AK34 P33 D

2
AC29 VCC19 VCC82 AK35 VCC143 AV31 VCCGT20 VCCGT99 BG29 RC40 1 2 0_0402_5% VCCGT_SENSE_R
P34
AC30 VCC20 VCC83 AK36 VCC144 AV32 VCCGT21 VCCGT100 BG30 [65] VCCGT_SENSE
P35
VCC21 VCC84 VCC145 VCCGT22 VCCGT101

@
AC31 AK37 P36 AV33 BG31 RC41 1 2 0_0402_5% VSSGT_SENSE_R
AC32 VCC22 VCC85 AK38 VCC146 AV34 VCCGT23 VCCGT102 BG32 [65] VSSGT_SENSE
R13
VCCGT24 VCCGT103

1
VCC23 VCC86 VCC147

@
AC33 AL13 R31 AV35 BG33
VCC24 VCC87 AL29 VCC148 AV36 VCCGT25 VCCGT104 BG34
AC34 R32
VCC25 VCC88 AL30 VCC149 AW14 VCCGT26 VCCGT105 BG35 RC63
AC35 R33
VCC26 VCC89 VCC150 AW31 VCCGT27 VCCGT106 BG36 100_0402_1%
AC36 AL31 R34
VCC27 VCC90 VCC151 AW32 VCCGT28 VCCGT107 BH33
AD13 AL32 R35

2
AD14 VCC28 VCC91 VCC152 AW33 VCCGT29 VCCGT108 BH34
AL35 R36
AD31 VCC29 VCC92 AL36 VCC153 AW34 VCCGT30 VCCGT109 BH35
R37
AD32 VCC30 VCC93 AL37 VCC154 AW35 VCCGT31 VCCGT110 BH36
R38
AD33 VCC31 VCC94 AL38 VCC155 AW36 VCCGT32 VCCGT111 BH37
T29
AD34 VCC32 VCC95 AM13 VCC156 AW37 VCCGT33 VCCGT112 BH38
T30
AD35 VCC33 VCC96 AM14 VCC157 AW38 VCCGT34 VCCGT113 BJ16
T31
AD36 VCC34 VCC97 AM29 VCC158 AY29 VCCGT35 VCCGT114 BJ17
T32
AD37 VCC35 VCC98 AM30 VCC159 AY30 VCCGT36 VCCGT115 BJ19
T35
AD38 VCC36 VCC99 AM31 VCC160 AY31 VCCGT37 VCCGT116 BJ20
T36
AE13 VCC37 VCC100 AM32 VCC161 AY32 VCCGT38 VCCGT117 BJ21
T37
AE14 VCC38 VCC101 AM33 VCC162 AY35 VCCGT39 VCCGT118 BJ23
T38
AE30 VCC39 VCC102 AM34 VCC163 AY36 VCCGT40 VCCGT119 BJ24
U29
AE31 VCC40 VCC103 AM35 VCC164 AY37 VCCGT41 VCCGT120 BJ26
U30
AE32 VCC41 VCC104 AM36 VCC165 AY38 VCCGT42 VCCGT121 BJ27
U31
AE35 VCC42 VCC105 AN13 VCC166 BA13 VCCGT43 VCCGT122 BJ37 CRB lace to CPU
U32
AE36 VCC43 VCC106 AN14 VCC167 BA14 VCCGT44 VCCGT123 BJ38
U33
AE37 VCC44 VCC107 AN31 VCC168 BA29 VCCGT45 VCCGT124 BK16 VCCCPUCORE
U34
AE38 VCC45 VCC108 AN32 VCC169 BA30 VCCGT46 VCCGT125 BK17
U35
AF29
AF30
VCC46
VCC47
VCC109
VCC110
AN33
AN34
U36
V13
VCC170
VCC171
BA31
BA32
VCCGT47
VCCGT48
VCCGT49
VCCGT126
VCCGT127
VCCGT128
BK19
BK20 VCC_SENSE

1
AF31 VCC48 VCC111 AN35 V14 VCC172 BA33 BK21 RC59
AF32 VCC49 VCC112 AN36 VCC173 BA34 VCCGT50 VCCGT129 BK23 100_0402_1%
V31
AF33 VCC50 VCC113 AN37 VCC174 BA35 VCCGT51 VCCGT130 BK24
V32
AF34 VCC51 VCC114 AN38 VCC175 BA36 VCCGT52 VCCGT131 BK26
V33
AF35 VCC52 VCC115 AP13 VCC176 BB13 VCCGT53 VCCGT132 BK27
V34
CAD Note: RC38 SHOULD BE PLACED CLOSE TO CPU

2
AF36 VCC53 VCC116 AP30 VCC177 BB14 VCCGT54 VCCGT133 BL15
V35
AF37 VCC54 VCC117 AP31 VCC178 BB31 VCCGT55 VCCGT134 BL16
V36
AF38 VCC55 VCC118 AP32 VCC179 BB32 VCCGT56 VCCGT135 BL17 VCCCORE_SENSE 1 2 0_0402_5% VCCSENSE_R
V37 [65] VCCCORE_SENSE RC38
AG14 VCC56 VCC119 AP35 VCC180 BB33 VCCGT57 VCCGT136 BL23
V38
VCC57 VCC120 AP36 VCC181 BB34 VCCGT58 VCCGT137 BL24

@
AG31 W13
AG32 VCC58 VCC121 AP37 VCC182 BB35 VCCGT59 VCCGT138 BL25
W14
AG33 VCC59 VCC122 AP38 W29 VCC183 BB36 VCCGT60 VCCGT139 BL26
CAD Note: RC39 SHOULD BE PLACED CLOSE TO CPU
AG34 VCC60 VCC123 K13 VCC184 BB37 VCCGT61 VCCGT140 BL27
W30
AG35 VCC61 VCC124 VCC185 BB38 VCCGT62 VCCGT141 BL28 VSSCORE_SENSE RC39 1 2 0_0402_5% VSSSENSE_R
W31 [65] VSSCORE_SENSE
AG36 VCC62 VCC186 BC29 VCCGT63 VCCGT142 BL36
W32
VCC63 VCC187 VCCGT64 VCCGT143

@
10 OF 13 BC30 BL37
VCCGT144

1
BC31 VCCGT65 BM15
COFFEELAKE-H-CPU_BGA1440
BC32 VCCGT66 VCCGT145 BM16
@

AG37 VCCSENSE_R BC35 VCCGT67 VCCGT146 BM17 RC62


VCC_SENSE AG38 VSSSENSE_R BC36 VCCGT68 VCCGT147 BM36 100_0402_1%
C 9 OF 13 VSS_SENSE BC37 VCCGT69 VCCGT148 BM37 C

2
COFFEELAKE-H-CPU_BGA1440 BC38 VCCGT70 VCCGT149 BN15
BD13 VCCGT71 VCCGT150 BN16
@

BD14 VCCGT72 VCCGT151 BN17


BD29 VCCGT73 VCCGT152 BN36
BD30 VCCGT74 VCCGT153 BN37
BD31 VCCGT75 VCCGT154 BN38
BD32 VCCGT76 VCCGT155 BP15
BD33 VCCGT77 VCCGT156 BP16
BD34 VCCGT78 VCCGT157 BP17
BP37 VCCGT79 VCCGT158 BR37
BP38 VCCGT159 VCCGT164 BT15
BR15 VCCGT160 VCCGT165 BT16
BR16 VCCGT161 VCCGT166 BT17
BR17 VCCGT162 VCCGT167 BT37
VCCGT163 VCCGT168

AH37 VSSGT_SENSE_R
VSSGT_SENSE AH38 VCCGT_SENSE_R
11 OFVCCGT_SENSE
13
COFFEELAKE-H-CPU_BGA1440
@

VCCGFXCORE
10uF 10pcs CD 1pcs
10U_0402_6.3V6M

10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M

1 1 1 1 1 1 1 1 1 1
CC104

CC103
CC108
CC98

CC110

CC106

CC105

CC117
CC102
CC107

B 2 2 2 2 2 2 2 2 2 2 B
CD@

VCCCPUCORE
10uF 21pcs CD 2pcs
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
10U_0402_6.3V6M

10U_0402_6.3V6M
10U_0402_6.3V6M

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1uF 12pcs CD 1pcs


CC76

CC75

CC88

CC89
CC62

CC82

CC81
CC79

CC77

CC83

CC92

CC86

CC84
CC80

CC78

CC87

CC94

CC93
CC91

CC85
CC74

CD75 CD76
33P_0201_50V8-J 33P_0201_50V8-J
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RF_NS@ 2 RF_NS@
1U_0201_6.3V6K

1U_0201_6.3V6K
1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD@

CD@

CD77 CD78
CH169

CH168
CH159

CH163

CH166
CH160

CH162

CH164

CH165
CH158

CH161

CH167

33P_0402_50V8J 33P_0402_50V8J
RF_NS@ RF_NS@
2 2 2 2 2 2 2 2 2 2 2 2 2 2
CD@

Near CPU

Near CPU
1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
1U_0201_6.3V6K

1U_0201_6.3V6K

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CH94

CH96

CH99

CH101

CH103

CH109

CH118
CH93

CH97

CH102

CH104

CH111

CH112

CH114

CH116
CH105

CH106

CH108

CH115
CH100

CH113

CH117

CH119

CH120
CH98

CH107

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
@

@
@

@
@

@
@

@
1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
1U_0201_6.3V6K

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CH125

CH126

CH136

CH137

CH138

CH139
CH131

CH135

CH140
CH132

CH133

CH134
CH124

CH128

CH129

CH130
CH121

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
@

@
@

@
@

@
@

A A

1uF 43pcs CD 2pcs

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 CPU (5/7) PWR, BYPASS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 9 of 74
5 4 3 2 1
5 4 3 2 1

VCCSA

VCCSA +1.2V
10uF 7pcs
UC1L

10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
J30 AA6
K29 VCCSA1 VDDQ1 AE12
VCCSA2 VDDQ2 1 1 1 1 1 1 1 1 1
K30 AF5 CD79 CD80
VCCSA3 VDDQ3

CC142
CC136

CC138

CC137
CC141

CC140

CC139
K31 AF6 33P_0402_50V8J 33P_0402_50V8J
K32 VCCSA4 VDDQ4 AG5 RF_NS@ RF_NS@
K33 VCCSA5 VDDQ5 AG9 +1.2V 2 2 2 2 2 2 2 2 2
K34 VCCSA6 VDDQ6 AJ12
K35 VCCSA7 VDDQ7 AL11
L31 VCCSA8 VDDQ8 AP6
L32 VCCSA9 VDDQ9 AP7
L35 VCCSA10 VDDQ10 AR12
L36 VCCSA11 VDDQ11 AR6
VCCSA12 VDDQ12 1
D
L37
L38
M29
VCCSA13
VCCSA14
VDDQ13
VDDQ14
AT12
AW6
AY6
CC172
10U_0603_6.3V6M Near CPU D

VCCSA15 VDDQ15 2
1U_0402_6.3V6K

M30 J5 1
M31 VCCSA16 VDDQ16 J6 Close to Y12 Pin
VCCSA17 VDDQ17
1uF 1pcs
CH223

M32 K12
M33 VCCSA18 VDDQ18 K6
M34 VCCSA19 VDDQ19 L12 2
M35 VCCSA20 VDDQ20 L6
M36 VCCSA21 VDDQ21 R6
VCCIO VCCSA22 VDDQ22 T6
VDDQ23 W6
VDDQ24 Y12
AG12 VDDQ25
G15 VCCIO1 +1.2V
G17 VCCIO2
G19 VCCIO3 BH13
G21 VCCIO4 VCCPLL_OC1 BJ13
VCCIO5 VCCPLL_OC2 VCCST
1U_0402_6.3V6K
10U_0402_6.3V6M

1U_0402_6.3V6K
10U_0402_6.3V6M

10U_0402_6.3V6M

1 1 1 H15 G11 1 1
H16 VCCIO6 VCCPLL_OC3
VCCIO7
CC150
CC147

CH252
CC148

CC149

H17 H30
H19 VCCIO8 VCCST VCCSTG
2 2 2 VCCIO9 2 2
1U_0402_6.3V6K

H20 H29 1
H21 VCCIO10 VCCSTG2
VCCIO11
1U_0402_6.3V6K

CH242
1U_0402_6.3V6K

H26 G30 1 1
H27 VCCIO12 VCCSTG1 VCCST
VCCIO13 2
CH250
CH249

J15 H28
J16 VCCIO14 VCCPLL1 J28
J17 VCCIO15 VCCPLL2 2 2
J19 VCCIO16
J20 VCCIO17 M38 VCCSA_SENSE_R
J21 VCCIO18 VCCSA_SENSE M37 VSSSA_SENSE_R
J26 VCCIO19 VSSSA_SENSE
J27 VCCIO20 H14 VCCIO_SENSE_R
VCCIO21 VCCIO_SENSE J14 VSSIO_SENSE_R
VSSIO_SENSE
1U_0402_6.3V6K

VCCIO 1 1
12 OF 13
CH251

COFFEELAKE-H-CPU_BGA1440 CC180
C @ 47U_0805_6.3V6-M C
2 2 @

Follow PDG Rev1.0


10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1 1 1
CC182

CC183

CC184

@ @ @
2 2 2
+1.2V
10uF 11pcs CD 1pcs
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

1 1 1 1 1 1 1 1 1 1
CC51

CC52

CC53

CC54

CC56
CC55

CC57

CC59

CC60
CC58

2 2 2 2 2 2 2 2 2 2
CD@
CC63
22U_0603_6.3V6-M

22U_0603_6.3V6-M
CC64
22U_0603_6.3V6-M

CC66
CC65
22U_0603_6.3V6-M

1 1 1 1

2 2 2 2
22uF 4pcs
B B

CRB lace to CPU CRB lace to CPU


VCCSA VCCIO
VCCSA_SENSE VCCIO_SENSE
1
1

RC151 RC155
100_0402_1% 100_0402_1%
2
2

RC150 1 2 VCCSA_SENSE_R RC154 1 2 VCCIO_SENSE_R


[65] VCCSA_SENSE [64] VCC_IO_SEN
0_0402_5% 0_0402_5%
RC148 1 @ 2 VSSSA_SENSE_R RC152 1 @ 2 VSSIO_SENSE_R
[65] VSSSA_SENSE [64] VSS_IO_SEN
0_0402_5% 0_0402_5%
1
1

@ @
RC149 RC153
100_0402_1% 100_0402_1%
2
2

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 CPU (6/7) PWR, BYPASS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 10 of 74
5 4 3 2 1
5 4 3 2 1

D UC1G D
UC1F UC1H
A10 AK4 AW5 BJ15 BN4 F15
A12 VSS_1 VSS_82 AL10 AY12 VSS_163 VSS_244 BJ18 VSS_325 VSS_409 F17
BN7
A16 VSS_2 VSS_83 AL12 AY33 VSS_164 VSS_245 BJ22 VSS_326 VSS_410 F19
BP12
A18 VSS_3 VSS_84 AL14 AY34 VSS_165 VSS_246 BJ25 VSS_327 VSS_411 F2
BP14
A20 VSS_4 VSS_85 AL33 B9 VSS_166 VSS_247 BJ29 VSS_328 VSS_412 F21
BP18
A22 VSS_5 VSS_86 AL34 BA10 VSS_167 VSS_248 BJ30 VSS_329 VSS_413 F23
BP21
A24 VSS_6 VSS_87 AL4 BA11 VSS_168 VSS_249 BJ31 VSS_330 VSS_414 F25
BP24
A26 VSS_7 VSS_88 AL7 BA12 VSS_169 VSS_250 BJ32 BP25 VSS_331 VSS_415 F27
A28 VSS_8 VSS_89 AL8 BA37 VSS_170 VSS_251 BJ33 VSS_332 VSS_416 F29
BP26
A30 VSS_9 VSS_90 AL9 BA38 VSS_171 VSS_252 BJ34 VSS_333 VSS_417 F3
BP29
A6 VSS_10 VSS_91 AM1 BA6 VSS_172 VSS_253 BJ35 VSS_334 VSS_418 F31
BP33
A9 VSS_11 VSS_92 AM12 BA7 VSS_173 VSS_254 BJ36 BP34 VSS_335 VSS_419 F36
AA12 VSS_12 VSS_93 AM2 BA8 VSS_174 VSS_255 BK13 BP7 VSS_336 VSS_420 F4
AA29 VSS_13 VSS_94 AM3 BA9 VSS_175 VSS_256 BK14 BR12 VSS_337 VSS_421 F5
AA30 VSS_14 VSS_95 AM37 BB1 VSS_176 VSS_257 BK15 BR14 VSS_338 VSS_422 F8
AB33 VSS_15 VSS_96 AM38 BB12 VSS_177 VSS_258 BK18 BR18 VSS_339 VSS_423 F9
AB34 VSS_16 VSS_97 AM4 BB2 VSS_178 VSS_259 BK22 BR21 VSS_340 VSS_424 G10
AB6 VSS_17 VSS_98 AM5 BB29 VSS_179 VSS_260 BK25 BR24 VSS_341 VSS_425 G12
AC1 VSS_18 VSS_99 AN12 BB3 VSS_180 VSS_261 BK29 BR25 VSS_342 VSS_426 G14
AC12 VSS_19 VSS_100 AN29 BB30 VSS_181 VSS_262 BK6 BR26 VSS_343 VSS_427 G16
AC2 VSS_20 VSS_101 AN30 BB4 VSS_182 VSS_263 BL13 BR29 VSS_344 VSS_428 G18
AC3 VSS_21 VSS_102 AN5 BB5 VSS_183 VSS_264 BL14 BR34 VSS_345 VSS_429 G20
AC37 VSS_22 VSS_103 AN6 BB6 VSS_184 VSS_265 BL18 BR36 VSS_346 VSS_430 G22
AC38 VSS_23 VSS_104 AP10 BC12 VSS_185 VSS_266 BL19 BR7 VSS_347 VSS_431 G23
AC4 VSS_24 VSS_105 AP11 BC13 VSS_186 VSS_267 BL20 BT12 VSS_348 VSS_432 G24
AC5 VSS_25 VSS_106 AP12 BC14 VSS_187 VSS_268 BL21 BT14 VSS_349 VSS_433 G26
AC6 VSS_26 VSS_107 AP33 BC33 VSS_188 VSS_269 BL22 BT18 VSS_350 VSS_434 G28
AD10 VSS_27 VSS_108 AP34 BC34 VSS_189 VSS_270 BL29 BT21 VSS_351 VSS_435 G4
AD11 VSS_28 VSS_109 AP8 BC6 VSS_190 VSS_271 BL33 BT24 VSS_352 VSS_436 G5
AD12 VSS_29 VSS_110 AP9 BD10 VSS_191 VSS_272 BL35 BT26 VSS_353 VSS_437 G6
AD29 VSS_30 VSS_111 AR1 BD11 VSS_192 VSS_273 BL38 BT29 VSS_354 VSS_438 G8
AD30 VSS_31 VSS_112 AR13 BD12 VSS_193 VSS_274 BL6 BT32 VSS_355 VSS_439 G9
AD6 VSS_32 VSS_113 AR14 BD37 VSS_194 VSS_275 BM11 BT5 VSS_356 VSS_440 H11
AD8 VSS_33 VSS_114 AR2 BD6 VSS_195 VSS_276 BM12 C11 VSS_357 VSS_441 H12
AD9 VSS_34 VSS_115 AR29 BD7 VSS_196 VSS_277 BM13 C13 VSS_358 VSS_442 H18
AE33 VSS_35 VSS_116 AR3 BD8 VSS_197 VSS_278 BM14 C15 VSS_359 VSS_443 H22
AE34 VSS_36 VSS_117 AR30 BD9 VSS_198 VSS_279 BM18 C17 VSS_360 VSS_444 H25
C C
AE6 VSS_37 VSS_118 AR31 BE1 VSS_199 VSS_280 BM2 C19 VSS_361 VSS_445 H32
AF1 VSS_38 VSS_119 AR32 BE2 VSS_200 VSS_281 BM21 C21 VSS_362 VSS_446 H35
AF12 VSS_39 VSS_120 AR33 BE29 VSS_201 VSS_282 BM22 C23 VSS_363 VSS_447 J10
AF13 VSS_40 VSS_121 AR34 BE3 VSS_202 VSS_283 BM23 C25 VSS_364 VSS_448 J18
AF14 VSS_41 VSS_122 AR35 BE30 VSS_203 VSS_284 BM24 C27 VSS_365 VSS_449 J22
AF2 VSS_42 VSS_123 AR36 BE4 VSS_204 VSS_285 BM25 C29 VSS_366 VSS_450 J25
AF3 VSS_43 VSS_124 AR37 BE5 VSS_205 VSS_286 BM26 C31 VSS_367 VSS_451 J32
AF4 VSS_44 VSS_125 AR38 BE6 VSS_206 VSS_287 BM27 C37 VSS_368 VSS_452 J33
AG10 VSS_45 VSS_126 AR4 BF12 VSS_207 VSS_288 BM28 C5 VSS_369 VSS_453 J36
AG11 VSS_46 VSS_127 AR5 BF33 VSS_208 VSS_289 BM29 C8 VSS_370 VSS_454 J4
AG13 VSS_47 VSS_128 AT29 BF34 VSS_209 VSS_290 BM3 C9 VSS_371 VSS_455 J7
AG29 VSS_48 VSS_129 AT30 BF6 VSS_210 VSS_291 BM33 D10 VSS_372 VSS_456 K1
AG30 VSS_49 VSS_130 AT6 BG12 VSS_211 VSS_292 BM35 D12 VSS_373 VSS_457 K10
AG6 VSS_50 VSS_131 AU10 BG13 VSS_212 VSS_293 BM38 D14 VSS_374 VSS_458 K11
AG7 VSS_51 VSS_132 AU11 BG14 VSS_213 VSS_294 BM5 D16 VSS_375 VSS_459 K2
AG8 VSS_52 VSS_133 AU12 BG37 VSS_214 VSS_295 BM6 D18 VSS_376 VSS_460 K3
AH12 VSS_53 VSS_134 AU33 BG38 VSS_215 VSS_296 BM7 D20 VSS_377 VSS_461 K38
AH33 VSS_54 VSS_135 AU34 BG6 VSS_216 VSS_297 BM8 D22 VSS_378 VSS_462 K4
AH34 VSS_55 VSS_136 AU6 BH1 VSS_217 VSS_298 BM9 D24 VSS_379 VSS_463 K5
AH35 VSS_56 VSS_137 AU7 BH10 VSS_218 VSS_299 BN12 D26 VSS_380 VSS_464 K7
AH36 VSS_57 VSS_138 AU8 BH11 VSS_219 VSS_300 BN14 D28 VSS_381 VSS_465 K8
AH6 VSS_58 VSS_139 AU9 BH12 VSS_220 VSS_301 BN18 D3 VSS_382 VSS_466 K9
AJ1 VSS_59 VSS_140 AV37 BH14 VSS_221 VSS_302 BN19 D30 VSS_383 VSS_467 L29
AJ13 VSS_60 VSS_141 AV38 BH2 VSS_222 VSS_303 BN2 D33 VSS_384 VSS_468 L30
AJ2 VSS_61 VSS_142 AW1 BH3 VSS_223 VSS_304 BN20 D6 VSS_385 VSS_469 L33
AJ3 VSS_62 VSS_143 AW12 BH4 VSS_224 VSS_305 BN21 D9 VSS_386 VSS_470 L34
AJ37 VSS_63 VSS_144 AW2 BH5 VSS_225 VSS_306 BN24 E34 VSS_387 VSS_471 M12
AJ38 VSS_64 VSS_145 AW29 BH6 VSS_226 VSS_307 BN29 E35 VSS_388 VSS_472 M13
AJ4 VSS_65 VSS_146 AW3 BH7 VSS_227 VSS_308 BN30 E38 VSS_389 VSS_473 N10
AJ5 VSS_66 VSS_147 AW30 BH8 VSS_228 VSS_309 BN31 E4 VSS_390 VSS_474 N11
AJ6 VSS_67 VSS_148 AW4 BH9 VSS_229 VSS_310 BN34 E9 VSS_391 VSS_475 N12
W4 VSS_68 VSS_149 U6 T2 VSS_230 VSS_311 P38 N3 VSS_392 VSS_476 N2
W5 VSS_69 VSS_150 V12 T3 VSS_231 VSS_312 P6 N33 VSS_393 VSS_477 BT8
Y10 VSS_70 VSS_151 V29 T33 VSS_232 VSS_313 R12 N34 VSS_394 VSS_478 BR9
Y11 VSS_71 VSS_152 V30 T34 VSS_233 VSS_314 R29 N4 VSS_395 VSS_479
Y13 VSS_72 VSS_153 A14 T4 VSS_234 VSS_315 AY14 N5 VSS_396 A3
Y14 VSS_73 VSS_154 AD7 T5 VSS_235 VSS_316 BD38 N6 VSS_397 VSS_A3 A34
B
Y37 VSS_74 VSS_155 V6 T7 VSS_236 VSS_317 R30 N7 VSS_398 VSS_A34 A4 B
Y38 VSS_75 VSS_156 W1 T8 VSS_237 VSS_318 T1 N8 VSS_399 VSS_A4 B3
Y7 VSS_76 VSS_157 W12 T9 VSS_238 VSS_319 T10 N9 VSS_400 VSS_B3 B37
Y8 VSS_77 VSS_158 W2 U37 VSS_239 VSS_320 T11 P12 VSS_401 VSS_B37 BR38
Y9 VSS_78 VSS_159 W3 U38 VSS_240 VSS_321 T12 P37 VSS_402 VSS_BR38 BT3
AK29 VSS_79 VSS_160 W33 BJ12 VSS_241 VSS_322 T13 M14 VSS_403 VSS_BT3 BT35
AK30 VSS_80 VSS_161 W34 BJ14 VSS_242 VSS_323 T14 M6 VSS_404 VSS_BT35 BT36
VSS_81 6 OF 13 VSS_162 VSS_2437 OF 13 VSS_324 N1 VSS_405 VSS_BT36 BT4
COFFEELAKE-H-CPU_BGA1440 COFFEELAKE-H-CPU_BGA1440 F11 VSS_406 VSS_BT4 C2
F13 VSS_407 VSS_C2 D38
@ @ VSS_4088 OF 13 VSS_D38
COFFEELAKE-H-CPU_BGA1440
@

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 CPU (6/7) PWR, VSS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 11 of 74
5 4 3 2 1
5 4 3 2 1

DDR4 SO-DIMM A
+1.2V+1.2V +1.2V+1.2V
+1.2V
JDDRL1B
+1.2V+1.2V +1.2V+1.2V

1
RD5
JDDRL1A
240_0402_5% DDRA_MA3 131 132 DDRA_MA2
[7] DDRA_MA3 A3 A2 134 DDRA_EVENT# DDRA_MA2 [7]
DDRA_MA1 133
[7] DDRA_MA1 A1 EVENT_n/NF 136
135

2
1 2 DDRA_CLK0 137 VDD_9 VDD_10 138 DDRA_CLK1
DDRA_DQ4 3 VSS_1 VSS_2 4 DDRA_DQ1 DDRA_EVENT# [7] DDRA_CLK0 CK0_t CK1_t/NF 140 DDRA_CLK1 [7]
DDRA_CLK0# 139 DDRA_CLK1#
[7] DDRA_DQ4 5 DQ5 DQ4 6 DDRA_DQ1 [7] [7] DDRA_CLK0# CK0_c CK1_c/NF DDRA_CLK1# [7]
141 142
DDRA_DQ0 7 VSS_3 VSS_4 8 DDRA_DQ5 DDRA_PARITY 143 VDD_11 VDD_12 144 DDRA_MA0
[7] DDRA_DQ0 9 DQ1 DQ0 10 DDRA_DQ5 [7] [7] DDRA_PARITY Parity A0 DDRA_MA0 [7]
DDRA_DQS#0 11 VSS_5 VSS_6 12
D [7] DDRA_DQS#0 13 DQS0_C DM0_n/DBl0_n 14 D
DDRA_DQS0 DDRA_BA1 145 146 DDRA_MA10_AP
[7] DDRA_DQS0 15 DQS0_t VSS_7 16 DDRA_DQ6 [7] DDRA_BA1 BA1 A10/AP DDRA_MA10_AP [7]
147 148
17 VSS_8 DQ6 18 DDRA_DQ6 [7] VDD_13 VDD_14 DDRA_BA0
DDRA_DQ7 DDRA_CS0# 149 150
[7] DDRA_DQ7 19 DQ7 VSS_9 20 DDRA_DQ2 [7] DDRA_CS0# CS0_n BA0 DDRA_BA0 [7]
DDRA_MA14_WE# 151 152 DDRA_MA16_RAS#
21 VSS_10 DQ2 22 DDRA_DQ2 [7] [7] DDRA_MA14_WE# A14/WE_n A16/RAS_n DDRA_MA16_RAS# [7]
DDRA_DQ3 153 154
[7] DDRA_DQ3 23 DQ3 VSS_11 24 DDRA_DQ9 VDD_15 VDD_16 DDRA_MA15_CAS#
DDRA_ODT0 155 156
25 VSS_12 DQ12 26 DDRA_DQ9 [7] [7] DDRA_ODT0 ODT0 A15/CAS_n DDRA_MA15_CAS# [7]
DDRA_DQ13 DDRA_CS1# 157 158 DDRA_MA13
[7] DDRA_DQ13 27 DQ13 VSS_13 28 DDRA_DQ8 [7] DDRA_CS1# CS1_n A13 DDRA_MA13 [7]
159 160
29 VSS_14 DQ8 30 DDRA_DQ8 [7] VDD_17 VDD_18
DDRA_DQ12 DDRA_ODT1 161 162
[7] DDRA_DQ12 31 DQ9 VSS_15 32 [7] DDRA_ODT1 ODT1 C0/CS2_n/NC +VREF_CA_DIMMA
DDRA_DQS#1 163 164
33 VSS_16 DQS1_c 34 DDRA_DQS#1 [7] VDD_19 VREFCA DDRA_SA2
DDRA_DQS1 165 166
DM1_n/DBl_n DQS1_t DDRA_DQS1 [7] C1/CS3_n/NC SA2

.1U_0402_10V6-K
35 36 167 168

2.2U_0603_6.3V6K
DDRA_DQ15 37 VSS_17 VSS_18 38 DDRA_DQ10 DDRA_DQ33 169 VSS_53 VSS_54 170 DDRA_DQ36
[7] DDRA_DQ15 DQ15 DQ14 DDRA_DQ10 [7] [7] DDRA_DQ33 DQ37 DQ36 DDRA_DQ36 [7] 1 1
39 40 171 172
DDRA_DQ14 41 VSS_19 VSS_20 42 DDRA_DQ11 DDRA_DQ37 173 VSS_55 VSS_56 174 DDRA_DQ32
[7] DDRA_DQ14 43 DQ10 DQ11 44 DDRA_DQ11 [7] [7] DDRA_DQ37 DQ33 DQ32 DDRA_DQ32 [7]
175 176
DDRA_DQ21 45 VSS_21 VSS_22 46 DDRA_DQ16 DDRA_DQS#4 177 VSS_57 VSS_58 178 2 2
[7] DDRA_DQ21 47 DQ21 DQ20 48 DDRA_DQ16 [7] [7] DDRA_DQS#4 DQS4_c DM4_n/DBl4_n
DDRA_DQS4 180

CD3
179

CD2
DDRA_DQ20 49 VSS_23 VSS_24 50 DDRA_DQ17 [7] DDRA_DQS4 DQS4_t VSS_59 DDRA_DQ35
181 182
[7] DDRA_DQ20 51 DQ17 DQ16 52 DDRA_DQ17 [7] VSS_60 DQ39 DDRA_DQ35 [7]
DDRA_DQ38 183 184
53 VSS_25 VSS_26 54 [7] DDRA_DQ38 DQ38 VSS_61 DDRA_DQ34
DDRA_DQS#2 185 186
[7] DDRA_DQS#2 DDRA_DQS2 55 DQS2_c DM2_n/DBl2_n 56 DDRA_DQ39 VSS_62 DQ35 DDRA_DQ34 [7]
187 188
[7] DDRA_DQS2 57 DQS2_t VSS_27 58 [7] DDRA_DQ39 DQ34 VSS_63 DDRA_DQ40
DDRA_DQ19 189 190
59 VSS_28 DQ22 60 DDRA_DQ19 [7] VSS_64 DQ45 DDRA_DQ40 [7]
DDRA_DQ22 DDRA_DQ44 191 192
[7] DDRA_DQ22 61 DQ23 VSS_29 62 DDRA_DQ23
[7] DDRA_DQ44 DQ44 VSS_65 DDRA_DQ45
193 194
63 VSS_30 DQ18 64 DDRA_DQ23 [7] VSS_66 DQ41 DDRA_DQ45 [7]
DDRA_DQ18 DDRA_DQ41 195 196
[7] DDRA_DQ18 65 DQ19 VSS_31 66 DDRA_DQ24
[7] DDRA_DQ41 DQ40 VSS_67 DDRA_DQS#5
197 198
67 VSS_32 DQ28 68 DDRA_DQ24 [7] VSS_68 DQS5_c DDRA_DQS5 DDRA_DQS#5 [7]
DDRA_DQ29 199 200
[7] DDRA_DQ29 69 DQ29 VSS_33 70 DDRA_DQ25 DM5_n/DBl5_n DQS5_t DDRA_DQS5 [7]
201 202
VSS_34 DQ24 72 DDRA_DQ25 [7] VSS_69 VSS_70
DDRA_DQ28 71 DDRA_DQ43 203 204 DDRA_DQ47
[7] DDRA_DQ28 DQ25 VSS_35 74 [7] DDRA_DQ43 DQ46 DQ47 DDRA_DQ47 [7]
73 DDRA_DQS#3 205 206
75 VSS_36 DQS3_c 76 DDRA_DQS#3 [7] DDRA_DQ46 VSS_71 VSS_72 DDRA_DQ42
DDRA_DQS3 207 208
DM3_n/DBl3_n DQS3_t 78 DDRA_DQS3 [7] [7] DDRA_DQ46 DQ42 DQ43 DDRA_DQ42 [7]
77 209 210
DDRA_DQ27 79 VSS_37 VSS_38 80 DDRA_DQ26 DDRA_DQ50 211 VSS_73 VSS_74 212 DDRA_DQ48
[7] DDRA_DQ27 DQ30 DQ31 82 DDRA_DQ26 [7] [7] DDRA_DQ50 DQ52 DQ53 DDRA_DQ48 [7]
81 213 214
DDRA_DQ30 83 VSS_39 VSS_40 84 DDRA_DQ31 DDRA_DQ52 215 VSS_75 VSS_76 216 DDRA_DQ49
[7] DDRA_DQ30 85 DQ26 DQ27 86 DDRA_DQ31 [7] [7] DDRA_DQ52 DQ49 DQ48 DDRA_DQ49 [7]
217 218
87 VSS_41 VSS_42 88 DDRA_DQS#6 219 VSS_77 VSS_78 220
C C
89 CB5/NC CB4/NC 90 [7] DDRA_DQS#6 DDRA_DQS6 DQS6_c DM6_n/DBl6_n
221 222
91 VSS_43 VSS_44 92 [7] DDRA_DQS6 DQS6_t VSS_79 DDRA_DQ53
223 224
93 CB1/NC CB0/NC 94 VSS_80 DQ54 DDRA_DQ53 [7]
DDRA_DQ54 225 226
95 VSS_45 VSS_46 96 [7] DDRA_DQ54 DQS5 VSS_81 DDRA_DQ55
227 228
97 DQS8_c DM8_n/DBl_n/NC 98 VSS_82 DQ50 DDRA_DQ55 [7]
DDRA_DQ51 229 230
99 DQS8_t VSS_47 100 [7] DDRA_DQ51 DQ51 VSS_83 DDRA_DQ61
231 232
101 VSS_48 CB6/NC 102 VSS_84 DQ60 DDRA_DQ61 [7]
DDRA_DQ60 233 234
103 CB2/NC VSS_49 104 [7] DDRA_DQ60 DQ61 VSS_85 DDRA_DQ57
235 236
105 VSS_50 CB7/NC 106 VSS_86 DQ57 DDRA_DQ57 [7]
DDRA_DQ56 237 238
107 CB3/NC VSS_51 108 PCH_DRAMRST# [7] DDRA_DQ56 DQ56 VSS_87
239 240 DDRA_DQS#7
109 VSS_52 RESET_n 110 DDRA_CKE1 PCH_DRAMRST# [13,16] VSS_88 DQS7_c DDRA_DQS#7 [7]
DDRA_CKE0 241 242 DDRA_DQS7
[7] DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 [7] DM7_n/DBl7_n DQS7_t DDRA_DQS7 [7]
111 112 243 244
DDRA_BG1 113 VDD_1 VDD_2 114 DDRA_ACT# DDRA_DQ62 245 VSS_89 VSS_90 246 DDRA_DQ59
[7] DDRA_BG1 BG1 ACT_n DDRA_ACT# [7] [7] DDRA_DQ62 DQ62 DQ63 DDRA_DQ59 [7]
DDRA_BG0 115 116 DDRA_ALERT# 247 248
[7] DDRA_BG0 BG0 ALERT_n DDRA_ALERT# [7] VSS_91 VSS_92
117 118 DDRA_DQ58 249 250 DDRA_DQ63
119 VDD_3 VDD_4 120 [7] DDRA_DQ58 DQ58 DQ59 DDRA_DQ63 [7]
DDRA_MA12 DDRA_MA11 251 252
[7] DDRA_MA12 A12 A11 DDRA_MA11 [7] VSS_93 VSS_94
DDRA_MA9 121 122 DDRA_MA7 1 [13,16] SMB_CLK_S3 SMB_CLK_S3 253 254 SMB_DATA_S3
[7] DDRA_MA9 A9 A7 DDRA_MA7 [7] SCL SDA SMB_DATA_S3 [13,16]
123 124 RD18 1 2 0_0402_5% DDRA_VDDSPD 255 256 DDRA_SA0
VDD_5 VDD_6 +3VS VDDSPD SA0
DDRA_MA8 125 126 DDRA_MA5 CD69 257 258 +0.6VS
[7] DDRA_MA8 A8 A5 DDRA_MA5 [7] 0.1U_0402_10V7K VPP_1 VTT
DDRA_MA6 127 128 DDRA_MA4 @ 1 1 259 260 DDRA_SA1
[7] DDRA_MA6 A6 A4 DDRA_MA4 [7] 2 VPP_2 SA1
129 130
VDD_7 VDD_8 @
CD27 CD28 261 262
2.2U_0603_6.3V6K .1U_0402_10V6-K GND_1 GND_2
Layout Note: 2 2
ARGOS_D4AR0-26005-1P40
Place near DIMM ARGOS_D4AR0-26005-1P40 ME@
ME@

RD20 1 2 0_0402_5%
+2.5V +2.5V

+0.6VS
+3VS +3VS +3VS 1U_0402_6.3V6K

1U_0402_6.3V6K
10U_0402_6.3V6M
10U_0402_6.3V6M
1

1 1 1 1
RD22 RD24
CD59

RD26 CD60
CD58
CD57
1U_0402_6.3V6K
1U_0402_6.3V6K

10U_0402_6.3V6M

B 0_0402_5% 0_0402_5% 0_0402_5% B


1 1 1
CD24

@ 2@ 2@
CD25

CD23 @ @ 2 2
2

2 2 2 DDRA_SA0 DDRA_SA1 DDRA_SA2


1
1

RD23 RD25 RD27


0_0402_5% 0_0402_5% 0_0402_5%
2
2

@ @ @
Note:
VREF trace width:20 mils at least
Spacing:20mils to other signal/planes
Place near DIMM scoket
SPD Address 0H Layout Note:
Place near DIMM
+1.2V
+VREF_CA_DIMMA_R

Change RD to 0ohm jum


1

+1.2V

RD1
1K_0402_1%
220U_B2_6.3VM_R25M
2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
10U_0603_6.3V6M

1U_0402_6.3V6K
1U_0402_6.3V6K

1 2 +VREF_CA_DIMMA
0.1U_0402_10V7K
0.1U_0402_10V7K

RD2 CD7 1 CD8 1 CD9 1 CD10 1 CD11 1 CD12 1 CD13 1 CD14 1


CD98 1 CD97 1 CD96 1 CD95 1 1 1 1 1 1 1 1 1 1 1 1
1

.1U_0402_10V6-K

CD15

CD18
CD16

CD17

CD65

CD66

CD68
CD67

2_0402_5% CD81 CD82


1K_0402_1%

+
CD5

1 1 33P_0402_50V8J 33P_0402_50V8J
CD21

CD1 RF_NS@ RF_NS@


EMC_NS@

EMC_NS@

EMC_NS@
EMC_NS@

0.022U_0402_16V7-K 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 @ 2 2
2
2

2 2
RD3

A A
1

RD4
24.9_0402_1%
Near JDDRL1
2

For EMC Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 DDRVI SO-DIMM A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 12 of 74
5 4 3 2 1
5 4 3 2 1

DDR4 SO-DIMM B
+1.2V +1.2V +1.2V +1.2V
+1.2V
JDDRH1A
+1.2V+1.2V +1.2V+1.2V

1
RD6
2 240_0402_5% JDDRH1B
1
DDRB_DQ2 3 VSS_1 VSS_2 4 DDRB_DQ4
[7] DDRB_DQ2 5 DQ5 DQ4 6 DDRB_DQ4 [7]

2
DDRB_DQ5 7 VSS_3 VSS_4 8 DDRB_DQ0 DDRB_MA3 131 132 DDRB_MA2
D [7] DDRB_DQ5 9 DQ1 DQ0 10 DDRB_DQ0 [7] DDRB_EVENT# [7] DDRB_MA3 A3 A2 DDRB_EVENT# DDRB_MA2 [7] D
DDRB_MA1 133 134
DDRB_DQS#0 11 VSS_5 VSS_6 12 [7] DDRB_MA1 A1 EVENT_n/NF
135 136
[7] DDRB_DQS#0 13 DQS0_C DM0_n/DBI0_n 14 VDD_9 VDD_10
DDRB_DQS0 DDRB_CLK0 137 138 DDRB_CLK1
[7] DDRB_DQS0 15 DQS0_t VSS_7 16 DDRB_DQ1 [7] DDRB_CLK0 CK0_t CK1_t/NF DDRB_CLK1 [7]
DDRB_CLK0# 139 140 DDRB_CLK1#
17 VSS_8 DQ6 18 DDRB_DQ1 [7] [7] DDRB_CLK0# CK0_c CK1_c/NF DDRB_CLK1# [7]
DDRB_DQ6 141 142
[7] DDRB_DQ6 19 DQ7 VSS_9 20 DDRB_DQ7 VDD_11 VDD_12
DDRB_PARITY 143 144 DDRB_MA0
21 VSS_10 DQ2 22 DDRB_DQ7 [7] [7] DDRB_PARITY Parity A0 DDRB_MA0 [7]
DDRB_DQ3
[7] DDRB_DQ3 23 DQ3 VSS_11 24 DDRB_DQ8
25 VSS_12 DQ12 26 DDRB_DQ8 [7]
DDRB_DQ10 DDRB_BA1 145 146 DDRB_MA10_AP
[7] DDRB_DQ10 DQ13 VSS_13 [7] DDRB_BA1 BA1 A10/AP DDRB_MA10_AP [7]
27 28 DDRB_DQ9 147 148
29 VSS_14 DQ8 30 DDRB_DQ9 [7] VDD_13 VDD_14
DDRB_DQ14 DDRB_CS0# 149 150 DDRB_BA0
[7] DDRB_DQ14 DQ9 VSS_15 [7] DDRB_CS0# CS0_n BA0 DDRB_BA0 [7]
31 32 DDRB_DQS#1 DDRB_MA14_WE# 151 152 DDRB_MA16_RAS#
33 VSS_16 DQS1_c 34 DDRB_DQS#1 [7] [7] DDRB_MA14_WE# WE_n/A14 RAS_n/A16 DDRB_MA16_RAS# [7]
DDRB_DQS1 153 154
35 DM1_n/DBl1_n DQS1_t 36 DDRB_DQS1 [7] VDD_15 VDD_16
DDRB_ODT0 155 156 DDRB_MA15_CAS#
DDRB_DQ12 37 VSS_17 VSS_18 38 DDRB_DQ11 [7] DDRB_ODT0 ODT0 CAS_n/A15 DDRB_MA15_CAS# [7]
[7] DDRB_CS1# DDRB_CS1# 157 158 DDRB_MA13
[7] DDRB_DQ12 39 DQ15 DQ14 40 DDRB_DQ11 [7] CS1_n A13 DDRB_MA13 [7]
159 160
DDRB_DQ13 41 VSS_19 VSS_20 42 DDRB_DQ15 DDRB_ODT1 161 VDD_17 VDD_18 162
[7] DDRB_DQ13 43 DQ10 DQ11 44 DDRB_DQ15 [7] [7] DDRB_ODT1 ODT1 C0/CS2_n/NC +VREF_CA_DIMMB
163 164
DDRB_DQ22 45 VSS_21 VSS_22 46 DDRB_DQ17 165 VDD_19 VREFCA 166 DDRB_SA2
[7] DDRB_DQ22 47 DQ21 DQ20 48 DDRB_DQ17 [7] C1/CS3_n/NC RFU/SA2
167 168

.1U_0402_10V6-K
VSS_23 VSS_24 VSS_53 VSS_54

2.2U_0603_6.3V6K
DDRB_DQ18 49 50 DDRB_DQ16 DDRB_DQ38 169 170 DDRB_DQ34
[7] DDRB_DQ18 51 DQ17 DQ16 52 DDRB_DQ16 [7] [7] DDRB_DQ38 DQ37 DQ36 DDRB_DQ34 [7]
171 172 1 1
DDRB_DQS#2 53 VSS_25 VSS_26 54 DDRB_DQ35 173 VSS_55 VSS_56 174 DDRB_DQ39
[7] DDRB_DQS#2 55 DQS2_c DM2_n/DBl2_n 56 [7] DDRB_DQ35 DQ33 DQ32 DDRB_DQ39 [7]
DDRB_DQS2 175 176
[7] DDRB_DQS2 57 DQS2_t VSS_27 58 DDRB_DQ23 DDRB_DQS#4 VSS_57 VSS_58
177 178 2
59 VSS_28 DQ22 60 DDRB_DQ23 [7] [7] DDRB_DQS#4 DQS4_c DM4_n/DBl4_n 2
DDRB_DQ20 DDRB_DQS4 179 180
[7] DDRB_DQ20 DQ23 VSS_29 [7] DDRB_DQS4 DQS4_t VSS_59

CD31
CD30
61 62 DDRB_DQ21 181 182 DDRB_DQ36
63 VSS_30 DQ18 64 DDRB_DQ21 [7] VSS_60 DQ39 DDRB_DQ36 [7]
DDRB_DQ19 DDRB_DQ33 183 184
[7] DDRB_DQ19 65 DQ19 VSS_31 66 DDRB_DQ28 [7] DDRB_DQ33 DQ38 VSS_61 DDRB_DQ37
185 186
67 VSS_32 DQ28 68 DDRB_DQ28 [7] DDRB_DQ32 VSS_62 DQ35 DDRB_DQ37 [7]
DDRB_DQ27 187 188
[7] DDRB_DQ27 69 DQ29 VSS_33 70 DDRB_DQ25 [7] DDRB_DQ32 DQ34 VSS_63 DDRB_DQ44
189 190
71 VSS_34 DQ24 72 DDRB_DQ25 [7] VSS_64 DQ45 DDRB_DQ44 [7]
DDRB_DQ31 DDRB_DQ40 191 192
[7] DDRB_DQ31 73 DQ25 VSS_35 74 [7] DDRB_DQ40 DQ44 VSS_65 DDRB_DQ45
DDRB_DQS#3 193 194
75 VSS_36 DQS3_c 76 DDRB_DQS#3 [7] VSS_66 DQ41 DDRB_DQ45 [7]
DDRB_DQS3 DDRB_DQ41 195 196
77 DM3_n/DBl3_n DQS3_t 78 DDRB_DQS3 [7] [7] DDRB_DQ41 DQ40 VSS_67
197 198 DDRB_DQS#5
DDRB_DQ30 79 VSS_37 VSS_38 80 DDRB_DQ26 VSS_68 DQS5_c DDRB_DQS5 DDRB_DQS#5 [7]
199 200
[7] DDRB_DQ30 81 DQ30 DQ31 82 DDRB_DQ26 [7] DM5_n/DBl5_n DQS5_t DDRB_DQS5 [7]
201 202
DDRB_DQ24 83 VSS_39 VSS_40 84 DDRB_DQ29 DDRB_DQ42 203 VSS_69 VSS_70 204 DDRB_DQ47
C C
[7] DDRB_DQ24 85 DQ26 DQ27 86 DDRB_DQ29 [7] [7] DDRB_DQ42 DQ46 DQ47 DDRB_DQ47 [7]
205 206
87 VSS_41 VSS_42 88 DDRB_DQ46 207 VSS_71 VSS_72 208 DDRB_DQ43
89 CB5/NC CB4/NC 90 [7] DDRB_DQ46 DQ42 DQ43 DDRB_DQ43 [7]
209 210
91 VSS_43 VSS_44 92 DDRB_DQ52 211 VSS_73 VSS_74 212 DDRB_DQ54
93 CB1/NC CB0/NC 94 [7] DDRB_DQ52 DQ52 DQ53 DDRB_DQ54 [7]
213 214
95 VSS_45 VSS_46 96 DDRB_DQ48 215 VSS_75 VSS_76 216 DDRB_DQ55
97 DQS8_c DM8_n/DBI_n/NC 98 [7] DDRB_DQ48 DQ49 DQ48 DDRB_DQ55 [7]
217 218
99 DQS8_t VSS_47 100 DDRB_DQS#6 219 VSS_77 VSS_78 220
101 VSS_48 CB6/NC 102 [7] DDRB_DQS#6 DDRB_DQS6 DQS6_c DM6_n/DBl6_n
221 222
103 CB2/NC VSS_49 104 [7] DDRB_DQS6 DQS6_t VSS_79 DDRB_DQ53
223 224
105 VSS_50 CB7/NC 106 DDRB_DQ50 VSS_80 DQ54 DDRB_DQ53 [7]
225 226
107 CB3/NC VSS_51 108 PCH_DRAMRST# [7] DDRB_DQ50 DQ55 VSS_81 DDRB_DQ49
227 228
109 VSS_52 RESET_n 110 PCH_DRAMRST# [12,16] DDRB_DQ51 VSS_82 DQ50 DDRB_DQ49 [7]
DDRB_CKE0 DDRB_CKE1 229 230
[7] DDRB_CKE0 111 CKE0 CKE1 112 DDRB_CKE1 [7] [7] DDRB_DQ51 DQ51 VSS_83 DDRB_DQ59
231 232
113 VDD_1 VDD_2 114 DDRB_DQ57 VSS_84 DQ60 DDRB_DQ59 [7]
DDRB_BG1 DDRB_ACT# 233 234
[7] DDRB_BG1 115 BG1 ACT_n 116 DDRB_ACT# [7] [7] DDRB_DQ57 DQ61 VSS_85 DDRB_DQ62
DDRB_BG0 DDRB_ALERT# 235 236
[7] DDRB_BG0 117 BG0 ALERT_n 118 DDRB_ALERT# [7] DDRB_DQ61 VSS_86 DQ57 DDRB_DQ62 [7]
1 237 238
119 VDD_3 VDD_4 120 [7] DDRB_DQ61 DQ56 VSS_87
DDRB_MA12 DDRB_MA11 239 240 DDRB_DQS#7
[7] DDRB_MA12 DDRB_MA9 121 A12 A11 122 DDRB_MA7 DDRB_MA11 [7] VSS_88 DQS7_c DDRB_DQS7 DDRB_DQS#7 [7]
CD70 241 242
[7] DDRB_MA9 123 A9 A7 124 DDRB_MA7 [7] 0.1U_0402_10V7K DM7_n/DBl7_n DQS7_t DDRB_DQS7 [7]
243 244
DDRB_MA8 125 VDD_5 VDD_6 126 DDRB_MA5 2 DDRB_DQ56 245 VSS_89 VSS_90 246 DDRB_DQ63
[7] DDRB_MA8 A8 A5 DDRB_MA5 [7] @ [7] DDRB_DQ56 DQ62 DQ63 DDRB_DQ63 [7]
DDRB_MA6 127 128 DDRB_MA4 247 248
[7] DDRB_MA6 129 A6 A4 130 DDRB_MA4 [7] DDRB_DQ60 VSS_91 VSS_92 DDRB_DQ58
249 250
VDD_7 VDD_8 [7] DDRB_DQ60 DQ58 DQ59 DDRB_DQ58 [7]
251 252
SMB_CLK_S3 253 VSS_93 VSS_94 254 SMB_DATA_S3
RD19 [12,16]
0_0402_5% SMB_CLK_S3 DDRB_VDDSPD SCL SDA DDRB_SA0 SMB_DATA_S3 [12,16]
1 2 255 256
+3VS VDDSPD SA0
1 1 257 258 +0.6VS
ARGOS_D4AS0-26005-1P40 CD53 259 VPP_1 Vtt 260 DDRB_SA1
@
ME@ 2.2U_0603_6.3V6K CD54 VPP_2 SA1
.1U_0402_10V6-K 261 262
2 2 GND_1 GND_2
+3VS +3VS +3VS
ARGOS_D4AS0-26005-1P40
ME@
1
1

RD28 RD33
RD30
0_0402_5% 0_0402_5% RD21 1 2 0_0402_5%
B
0_0402_5% +2.5V B
@ @
2
2

@
DDRB_SA0 DDRB_SA1 DDRB_SA2
1

1
1

RD31
RD29 RD32
0_0402_5% +2.5V
0_0402_5% 0_0402_5%
@
2

2
2

@ @
1U_0402_6.3V6K

1U_0402_6.3V6K
10U_0402_6.3V6M
10U_0402_6.3V6M

+VREF_DQ_DIMMB_R +1.2V
1 1 1 1
CD61

CD62
CD64
CD63

Change RD to 0ohm jum


SPD Address H
1

2 2@ 2 2@
RD11
Layout Note: 1K_0402_1%
Place near DIMM
1 2 +VREF_CA_DIMMB
2

RD12
+1.2V 2_0402_5%
1

1 1
.1U_0402_10V6-K

CD29
1K_0402_1%

Layout Note: 0.022U_0402_16V7-K


Place near DIMM 2 2
2
1

CD47
RD13

RD14
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

24.9_0402_1%
CD35 1 CD36 1 CD37 1 CD38 1 CD39 1 CD40 1 CD41 1 CD42 1 1 1 1 1 1 1 1 1 1 1
CD44

CD45

CD72

CD73
CD46

CD71

CD74
CD43

CD83 CD84
2

+0.6VS 33P_0402_50V8J 33P_0402_50V8J


RF_NS@ RF_NS@
A
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 CAD Note: A
Trace width= 20 mil, Spcing=20 mils
1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0402_6.3V6M

For EMC
1 1 1
Near JDDRH1
CD50

CD49
CD51

2 2 2

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 DDRVI SO-DIMM B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 13 of 74
5 4 3 2 1
5 4 3 2 1

D D

+3VS

UH1C
AR2 G36 PCIE_PRX_DTX_N9
CL_CLK PCIE9_RXN PCIE_PRX_DTX_P9 PCIE_PRX_DTX_N9 [45]
AT5 F36
CL_DATA PCIE9_RXP PCIE_PTX_DRX_N9 PCIE_PRX_DTX_P9 [45]
AU4 C34 NGFF SSD
CL_RST# PCIE9_TXN PCIE_PTX_DRX_N9 [45]
1

D34 PCIE_PTX_DRX_P9
PCIE9_TXP PCIE_PTX_DRX_P9 [45]
P48
RH133 V47 GPP_K8 K37 PCIE_PRX_DTX_N10
GPP_K9 PCIE10_RXN PCIE_PRX_DTX_P10 PCIE_PRX_DTX_N10 [45]
10K_0201_5% V48 J37
GPP_K10 PCIE10_RXP PCIE_PTX_DRX_N10 PCIE_PRX_DTX_P10 [45]
W47 C35 NGFF SSD
PCIE_PTX_DRX_N10 [45]
2

GPP_K11 PCIE10_TXN B35 PCIE_PTX_DRX_P10


PCIE10_TXP PCIE_PTX_DRX_P10 [45]
L47
L46 GPP_K0 F44
EC_SCI# RH95 1 2 0_0201_5% U48 GPP_K1 PCIE15_RXN/SATA2_RXN E45
[20,49] EC_SCI# RTS5455_SM_INT GPP_K2 PCIE15_RXP/SATA2_RXP
RH828 1 @ 2 0_0201_5% U47 B40
[38,49] RTS5455_SM_INT GPP_K3 PCIE_15_SATA_2_TXN
N48 C40
N47 GPP_K4 PCIE15_TXP/SATA2_TXP
P47 GPP_K5 L41
R46 GPP_K6 PCIE16_RXN/SATA3_RXN M40
GPP_K7 PCIE16_RXP/SATA3_RXP B41
PCIE_PTX_DRX_P11 C36 PCIE16_TXN/SATA3_TXN C41
[45] PCIE_PTX_DRX_P11 PCIE_PTX_DRX_N11 PCIE11_TXP/SATA0A_TXP PCIE16_TXP/SATA3_TXP
B36
[45] PCIE_PTX_DRX_N11 PCIE_PRX_DTX_P11 PCIE11_TXN/SATA0A_TXN SATA_PRX_DTX_N4
NGFF SSD[45] F39 K43
PCIE_PRX_DTX_P11 PCIE_PRX_DTX_N11 PCIE11_RXP/SATA0A_RXP PCIE17_RXN/SATA4_RXN SATA_PRX_DTX_P4 SATA_PRX_DTX_N4 [46]
G38 K44
[45] PCIE_PRX_DTX_N11 PCIE11_RXN/SATA0A_RXN PCIE17_RXP/SATA4_RXP SATA_PTX_DRX_N4
SATA_PRX_DTX_P4 [46]
A42 HDD
PCIE17_TXN/SATA4_TXN SATA_PTX_DRX_P4 SATA_PTX_DRX_N4 [46]
C AR42 B42 C
GPP_F10/SATA_SCLOCK PCIE17_TXP/SATA4_TXP SATA_PTX_DRX_P4 [46]
AR48
AU47 GPP_F11/SATA_SLOAD P41
AU46 GPP_F13/SATA_SDATAOUT0 PCIE18_RXN/SATA5_RXN R40
GPP_F12/SATA_SDATAOUT1 PCIE18_RXP/SATA5_RXP C42
CH15 1 2 0.1u_0201_10V6K PCIE_PTX_DRX_N14 C39 PCIE18_TXN/SATA5_TXN D42
[51] PCIE_PTX_C_DRX_N14 PCIE_PTX_DRX_P14 PCIE14_TXN/SATA1B_TXN PCIE18_TXP/SATA5_TXP
CH16 1 2 0.1u_0201_10V6K D39
[51] PCIE_PTX_C_DRX_P14 PCIE_PRX_DTX_N14 PCIE14_TXP/SATA1B_TXP
LAN D46 AK48 SATA_LED# RH15 1 2 10K_0201_5% +3VS
[51] PCIE_PRX_DTX_N14 PCIE_PRX_DTX_P14 PCIE14_RXN/SATA1B_RXN GPP_E8/SATA_LED#
C47 AH41
[51] PCIE_PRX_DTX_P14 PCIE14_RXP/SATA1B_RXP GPP_E0/SATAXPCIE0/SATAGP0 SSD_DET#
AJ43
PCIE_PTX_DRX_N13 GPP_E1/SATAXPCIE1/SATAGP1 SSD_DET# [45]
CH17 1 2 0.1u_0201_10V6K B38 AK47
[45] PCIE_PTX_C_DRX_N13 PCIE_PTX_DRX_P13 PCIE13_TXN/SATA0B_TXN GPP_E2/SATAXPCIE2/SATAGP2
CH18 1 2 0.1u_0201_10V6K C38 AN47
[45] PCIE_PTX_C_DRX_P13 PCIE_PRX_DTX_N13 PCIE13_TXP/SATA0B_TXP GPP_F0/SATAXPCIE3/SATAGP_3
WLAN [45] C45 AM46
PCIE_PRX_DTX_N13 PCIE_PRX_DTX_P13 PCIE13_RXN/SATA0B_RXN GPP_F1/SATAXPCIE4/SATAGP4
C46 AM43
[45] PCIE_PRX_DTX_P13 PCIE13_RXP/SATA0B_RXP GPP_F2/SATAXPCIE5/SATAGP5 AM47
PCIE_SATA_PTX_DRX_P12 E37 GPP_F3/SATAXPCIE6/SATAGP6 AM48
[45] PCIE_SATA_PTX_DRX_P12 PCIE_SATA_PTX_DRX_N12 PCIE12_TXP/SATA1A_TXP GPP_F4/SATAXPCIE7/SATAGP7
D38
[45] PCIE_SATA_PTX_DRX_N12 PCIE_SATA_PRX_DTX_P12 PCIE12_TXN/SATA1A_TXN
NGFF SSD [45] J41 AU48
PCIE_SATA_PRX_DTX_P12 PCIE_SATA_PRX_DTX_N12 PCIE12_RXP/SATA_1A_RXP GPP_F21/EDP_BKLTCTL PCH_EDP_PWM [35]
H42 AV46
[45] PCIE_SATA_PRX_DTX_N12 PCIE12_RXN/SATA1A_RXN GPP_F20/EDP_BKLTEN PCH_EDP_ENBKL [49]
B44 AV44
PCIE20_TXP/SATA7_TXP GPP_F19/EDP_VDDEN PCH_EDP_ENVDD [35]
A44
R37 PCIE20_TXN/SATA7_TXN AD3 THRMTRIP#_PCH RH34 1 2 620_0402_5%
PCIE20_RXP/SATA7_RXP THRMTRIP# H_THRMTRIP# [6,24]
R35 AF2 PCH_PECI RH35 1 2 13_0402_5%
PCIE20_RXN/SATA7_RXN PECI H_PM_SYNC_R EC_PECI [6,49]
D43 AF3 RH13 1 2 30_0402_1%
PCIE19_TXP/SATA6_TXP PM_SYNC H_PM_SYNC [6]
C44 AG5 CPU_PLTRST#
PCIE19_TXN/SATA6_TXN PLTRST_CPU# H_PM_DOWN CPU_PLTRST# [6]
N42 AE2
PCIE19_RXP/SATA6_RXP PM_DOWN H_PM_DOWN [6]
M44
PCIE19_RXN/SATA6_RXN 3 OF 13
1

CANNONLAKE-H-PCH_FCBGA874 1 1
B B
.1U_0402_10V6-K
CH281
.1U_0402_10V6-K
CH280

@
@ RH836
10K_0201_5%
@2 @2
2

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 PCH (1/9) PCIe/SATA/GPPFG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A3
EY515 1.0

Date: Tuesday, March 20, 2018 Sheet 14 of 74


5 4 3 2 1
5 4 3 2 1

+3VS

D HM370 only have 4(#1-#4) USB3.1 GEN2 port D

1
10K_0201_5%

10K_0201_5%
UH1F

RH104

RH113
USB30_TX_N1 F9 BB39 LPC_AD0_R RH128 1 2 0_0201_5%
[48] USB30_TX_N1 USB30_TX_P1 USB31_1_TXN GPP_A1/LAD0/ESPI_IO0 LPC_AD1_R LPC_AD0 [49,50]
F7 AW37 RH130 1 2 0_0201_5%
Back USB (3.0) [48] USB30_TX_P1
USB30_RX_N1 D11 USB31_1_TXP GPP_A2/LAD1/ESPI_IO1 AV37 LPC_AD2_R RH131 1 2 0_0201_5%
LPC_AD1 [49,50]
[48] USB30_RX_N1 USB31_1_RXN GPP_A3/LAD2/ESPI_IO2 LPC_AD2 [49,50]
USB30_RX_P1 C11 BA38 LPC_AD3_R RH132 1 2 0_0201_5%
[48] USB30_RX_P1 LPC_AD3 [49,50]

2
USB31_1_RXP GPP_A4/LAD3/ESPI_IO3
TYPE-C_USB3_TX_N2 C3
[37] TYPE-C_USB3_TX_N2 TYPE-C_USB3_TX_P2 USB31_2_TXN
D4 BE38 LPC_FRAME#
TYPE-C USB (3.0) [37] TYPE-C_USB3_TX_P2 TYPE-C_USB3_RX_N2 B9 USB31_2_TXP GPP_A5/LFRAME#/ESPI_CS0# AW35 SERIRQ
LPC_FRAME# [49,50]
[37] TYPE-C_USB3_RX_N2 TYPE-C_USB3_RX_P2 USB31_2_RXN GPP_A6/SERIRQ/ESPI_CS1# SERIRQ [49,50]
C9 BA36
[37] TYPE-C_USB3_RX_P2 USB31_2_RXP GPP_A7/PIRQA#/ESPI_ALERT0# BE39 KBRST#
GPP_A0/RCIN#/ESPI_ALERT1# KBRST# [49]
C17 BF38
C16 USB31_6_TXN GPP_A14/SUS_STAT#/ESPI_RESET#
G14 USB31_6_TXP For LPC_CLK
F14 USB31_6_RXN R:0Ω t o Ω
USB31_6_RXP BB36 CLK_PCI_EC_R RH84 1 2 22_0402_5% CLK_PCI_EC
GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_PCI_TPM_R CLK_PCI_TPM CLK_PCI_EC [49]
C15 BB34 RH87 1 2 22_0402_5% TPM@
USB31_5_TXN GPP_A10/CLKOUT_LPC1 CLK_PCI_TPM [50]
B15
J13 USB31_5_TXP T48 PCH_SMI# RH821 1 @ 2 0_0201_5%
USB31_5_RXN GPP_K19/SMI# EC_SMI# [49]
K13 T47 1
USB31_5_RXP GPP_K18/NMI#

CH265
10P_0402_50V8J
EMC_NS@
RH129 1 @ 2 10K_0201_5% +3VS
USB30_TX_P3 G12 AH40
[47] USB30_TX_P3 USB30_TX_N3 USB31_3_TXP GPP_E6/SATA_DEVSLP2
F11 AH35 DEVSLP1
LEFT USB (3.0) [47] USB30_TX_N3 USB30_RX_P3 C10 USB31_3_TXN GPP_E5/SATA_DEVSLP1 AL48
DEVSLP1 [45] NGFF SSD 2
[47] USB30_RX_P3 USB31_3_RXP GPP_E4/SATA_DEVSLP0
MB(AOU) [47] USB30_RX_N3
USB30_RX_N3 B10
USB31_3_RXN GPP_F9/SATA_DEVSLP7
AP47 change D VSLP to SATA Port by Bing 0
AN37 H:Slee Mode
USB30_TX_P4 C14 GPP_F8/SATA_DEVSLP6 AN46 L:Active Mode
[50] USB30_TX_P4 USB30_TX_N4 USB31_4_TXP GPP_F7/SATA_DEVSLP5
B14 AR47
C
Right USB (3.0) [50] USB30_TX_N4 USB30_RX_P4 J15 USB31_4_TXN 6 OF 13 GPP_F6/SATA_DEVSLP4 AP48
C

[50] USB30_RX_P4 USB31_4_RXP GPP_F5/SATA_DEVSLP3


DB [50] USB30_RX_N4
USB30_RX_N4 K16
USB31_4_RXN

CANNONLAKE-H-PCH_FCBGA874
1

CH293
@

10P_0402_50V8J
EMC_NS@
2

+3VS

DDPB_DATA RH834 1 @ 2 2.2K_0201_5%


B B
DDPC_DATA RH33 1 @ 2 2.2K_0201_5%
UH1E
RH23 1 2 0_0201_5% AT6 AL13 DDPB_CLK PAD1 @
[38] TYPE-C_DP_HPD GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I5/DDPB_CTRLCLK IT37
RH26 1 2 0_0201_5% AN10 AR8 DDPB_DATA DDPD_DATA RH835 1 @ 2 2.2K_0201_5%
[36] HDMI_HPD GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I6/DDPB_CTRLDATA DDPC_CLK
RH27 1 2 0_0201_5% AP9 AN13 PAD 1 @
[43] DP_HPD GPP_I2/DPPD_HPD2/DISP_MISC2 GPP_I7/DDPC_CTRLCLK DDPC_DATA IT28
AL15 AL10
GPP_I3/DPPE_HPD3/DISP_MISC3 GPP_I8/DDPC_CTRLDATA AL9 DDPD_CLK PAD 1 @
GPP_I9/DDPD_CTRLCLK IT36
AR3 DDPD_DATA
GPP_I10/DDPD_CTRLDATA AN40
GPP_F23/DDPF_CTRLDATA AT49
GPP_F22/DDPF_CTRLCLK
AP41
PCH_EDP_HPD AN6 GPP_F14/EXT_PWR_GATE#/PS_ON#
[35] PCH_EDP_HPD GPP_I4/EDP_HPD/DISP_MISC4
GPP_K23/IMGCLKOUT1
M45 DDPB_CTRLDATA
L48 The signal has a weak internal pull-down.
GPP_K22/IMGCLKOUT0 T45
GPP_K21 H Port B is detected.
T46

5 OF 13
GPP_K20
GPP_H23/TIME_SYNC0
AJ47 * L Port B is not detected.

CANNONLAKE-H-PCH_FCBGA874 DDPC_CTRLDATA
@ The signal has a weak internal pull-down.
H Port C is detected.
* L Port C is not detected. (Default)
DDPD_CTRLDATA
The signal has a weak internal pull-down.
H Port D is detected.
A
*L Port D is not detected. (Default) A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 PCH (2/9) USB3/GPPAEFGHI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A3 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 15 of 74
5 4 3 2 1
5 4 3 2 1

+3VALW_PCH
HDA_SDO This signal has a weak internal pull-down.
* 0 = Enable security measures defined in the Flash Descriptor.
1 = Disable Flash Descriptor Security (override). This
1

strap should only be asserted high using external pull- RH25


up in manufacturing/debug environments ONLY. 1K_0201_5%
@
2

+1.2V
RH9 1 2 0_0201_5%
[49] ME_FLASH
UH1D
RH8051 2 33_0402_5% HDA_BIT_CLK BD11 BF36
[40] PCH_HDA_BIT_CLK HDA_BCLK/I2S0_SCLK GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF#
1

PCH_HDA_SDIN0 BE11 AV32


[40] PCH_HDA_SDIN0 RH8061 2 33_0402_5% HDA_SDOUT HDA_SDI0/I2S0_RXD GPP_A8/CLKRUN# PM_CLKRUN# [50]
D BF12 RH756 D
[40] PCH_HDA_SDOUT RH8041 2 33_0402_5% HDA_SYNC BG13 HDA_SDO/I2S0_TXD BF41 470_0201_5%
[40] PCH_HDA_SYNC HDA_SYNC/I2S0_SFRM GPD11/LANPHYPC
PLAC AR PCH BE10 BD42
2

BF10 HDA_RST#/I2S1_SCLK GPD9/SLP_WLAN#


BE12 HDA_SDI1/I2S1_RXD BB46
I2S1_TXD/SNDW2_DATA DRAM_RESET# BE32 PCH_DRAMRST# [12,13]
BD12
I2S1_SFRM/SNDW2_CLK GPP_B2/VRALERT# BF33
PLAC AR PCH GPP_B1/GSPI1_CS1#/TIME_SYNC1 BE29
RH754 1 2 30_0402_5% PROC_AUDIO_SDO_PCH AM2 GPP_B0/GSPI0_CS1# R47
[8] PROC_AUDIO_SDO_CPU HDACPU_SDO GPP_K17/ADR_COMPLETE
AN3 AP29
[8] PROC_AUDIO_SDI_CPU RH755 1 2 30_0402_5% PROC_AUDIO_CLK_PCH AM3 HDACPU_SDI GPP_B11/I2S_MCLK SYS_PWROK_R
AU3 RH1931 2 0_0201_5%
[8] PROC_AUDIO_CLK_CPU HDACPU_SCLK SYS_PWROK SYS_PWROK [49]
AV18 BB47 WAKE# RH69 1 2 0_0201_5%
AW18 GPP_D8/I2S2_SCLK WAKE# BE40 SLP_A# PCIE_WAKE# [45,49]
1
CNVI_MODEM_CLKREQ BA17 GPP_D7/I2S2_RXD GPD6/SLP_A# SLP_LAN# TH30 PAD @
BF40 1
CNVI_RF_RESET# GPP_D6/I2S2_TXD/MODEM_CLKREQ SLP_LAN# SLP_S0 1 TH31 PAD @
BE16 BC28
GPP_D5/I2S2_SFRM/CNV_RF_RESET# GPP_B12/SLP_S0# TH32 PAD @
BF15 BF42 PM_SLP_S3#_R RH70 1 2 0_0201_5%
GPP_D20/DMIC_DATA0/SNDW4_DATA GPD4/SLP_S3# PM_SLP_S4#_R RH71 1 2 0_0201_5% PM_SLP_S3# [49]
BD16 BE42
AV16 GPP_D19/DMIC_CLK0/SNDW4_CLK GPD5/SLP_S4# BC42 PM_SLP_S5#_R 1 PM_SLP_S4# [49]
GPP_D18/DMIC_DATA1/SNDW3_DATA GPD10/SLP_S5# TH33 PAD @
AW15
GPP_D17/DMIC_CLK1/SNDW3_CLK BE45 SUSCLK
PCH_RTCRST# BE47 GPD8/SUSCLK SUSCLK [45]
BF44 BATLOW#
[49] PCH_RTCRST# PCH_SRTCRST# RTCRST# GPD0/BATLOW# SUSACK#_R
BD46 BE35
SRTCRST# GPP_A15/SUSACK# BC37 SUSWARN#_R RH745 1 @ 2 0_0201_5%
RH12 1 2 0_0201_5% PCH_PWROK_R AY42 GPP_A13/SUSWARN#/SUSPWRDNACK
[49] PCH_PWROK RH14 1 2 0_0201_5% PCH_RSMRST#_R PCH_PWROK
BA47
[42,49] EC_RSMRST# RSMRST# BG44 PCH_LAN_WAKE#
RH2391 2 0_0201_5% PCH_DPWROK_R AW41 GPD2/LAN_WAKE# BG42 PCH_AC_PRESENT_R RH76 1 2 0_0201_5%
SMB_ALERT# DSW_PWROK GPD1/ACPRESENT SLP_SUS# AC_PRESENT [49]
BE25 BD39 1
PCH_SMBCLK GPP_C2/SMBALERT# SLP_SUS# PM_PWRBTN#_R TH34 PAD@
BE26 BE46 RH75 1 2 0_0201_5%
PCH_SMBDATA BF26 GPP_C0/SMBCLK GPD3/PWRBTN# SYS_RESET# PBTN_OUT# [42,49]
AU2
SMB0_ALERT# GPP_C1/SMBDATA SYS_RESET# AW29 SYS_RESET# [42]
BF24
GPP_C5/SML0ALERT# GPP_B14/SPKR PCH_BEEP [40]
SML0CLK BF25 AE3
GPP_C3/SML0CLK CPUPWRGD H_CPUPWRGD [6]
SML0DATA BE24
SMB1_ALERT# BD33 GPP_C4/SML0DATA AL3
[44] SMB1_ALERT# BF27 GPP_B23/SML1ALERT#/PCHHOT# ITP_PMODE ITP_PMODE [42]
SML1CLK AH4
BE27 GPP_C6/SML1CLK PCH_JTAGX AJ4 JTAGX [42]
SML1DATA
GPP_C7/SML1DATA PCH_JTAG_TMS AH3 PCH_TMS [42]
+3VALW_PCH PCH_JTAG_TDO AH2 PCH_TDO [42]
PCH_JTAG_TDI AJ3 PCH_TDI [42]
RH56 1 @ 2 10K_0201_5% SUSWARN#_R 4 OF 13 PCH_JTAG_TCK PCH_TCK [42]

CANNONLAKE-H-PCH_FCBGA874
@

+3VALW
2EC_RSMRST#

RH17 1 2 10K_0201_5% PM_PWRBTN#_R CMOS


C RH58 1 2 10K_0201_5% PCH_AC_PRESENT_R RC278 1 @ 2 0_0201_5% C
+3VL
RH60 1 2 10K_0201_5% BATLOW#
RH80 1 2 4.7K_0201_5% WAKE#
2

RH747 1 2 10K_0201_5% PCH_LAN_WAKE#


1 RC276 RC277
1

VCCRTC CH4 @ @ 0_0402_5% @ 100K_0402_5%


+3VS 1U_0402_6.3V6K JME1
SHORT PADS
3 1

1
2

RH31 2 20K_0402_5% 2 PCH_SRTCRST#


RH67 1 2 10K_0201_5% SYS_RESET# D QH3B
RH65 1 2 8.2K_0201_5% PM_CLKRUN# 5
RH41 2 20K_0402_5% PCH_RTCRST# @ G
6

1 @ D QH3A
1

CH5 JCMOS1 S 2 RC272 1 @ 2 0_0201_5%


1 ALW_PWRGD [60,62]
4

CH1 1U_0402_6.3V6K SHORT PADS @ G


1U_0402_6.3V6K L2N7002KDW1T1G_SOT363-6
2

2 S
2@
1

L2N7002KDW1T1G_SOT363-6

RH18 1 2 100K_0201_5% SYS_PWROK_R


RH54 1 2 10K_0201_5% PCH_PWROK_R
RH59 1
1
2 100K_0201_5%
2 100K_0201_5%
PCH_RSMRST#_R
PCH_DPWROK_R
RSMRST# sequence control circuit
RH61
@

+3VALW_PCH AS EMC request


close to PCH
HDA_SDOUT
+3VALW_PCH RH28 1 @ 2 1K_0201_5% PCH_BEEP PCH_PWROK_R SYS_PWROK_R PCH_DPWROK_R PCH_HDA_SDIN0
ST 
Kh
P

R
/g

G
P
P
_
B

4

RPH3 @

D



h¨¨
T


ww
 w

k









D
f



-


w)
 

 

1 4 SML0CLK 1 1 1 1 1








S
cTT




(T
h



CH85 EMC_NS@

.1U_0402_10V6-K
CH84 EMC_NS@

.1U_0402_10V6-K

CH283
2.2P_0402_50V8-C
CH83 EMC_NS@

.1U_0402_10V6-K

CH284
2.2P_0402_50V8-C

2 3 SML0DATA
* 〃
fFA(

E




TS
Pc
S

w





,




c
k



c




 


c
c


f
Ih



fh

 S
Pw


h



h


 




2.2K_0404_4P2R_5%
h






-








4


A


f


f

2 2 2 2 2

c
c
g

g




kh

C
H
w
w

KA
B
 ,
6c
(,


h
)

EMC_NS@

EMC_NS@
W
y

h


g








6
- 

 

kA


RH765 1 2 2.2K_0201_5% SMB_ALERT# RH768 1 @ 2 2.2K_0201_5%


H


c




 )







(z
6


7


RH766 1 @ 2 2.2K_0201_5% SMB0_ALERT# RH769 1 @ 2 2.2K_0201_5%


8h
)




g

F




B
c
k

f


RH767 1 @ 2 2.2K_0201_5% SMB1_ALERT# RH770 1 @ 2 2.2K_0201_5%






h

h

I
C

Strap
GPP_C2 /SMBALERT#
This signal has a weak internal pull-down.
0 = Disable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (no confidentiality). (Default)
1 = Enable Intel ME Crypto Transport Layer Security DIMM1, DIMM2, WLAN, TP RPH8 +3VS GPU, EC, Thermal Sensor
(TLS) cipher suite (with confidentiality). Must be +3VS +3VALW_PCH 1 4
2

B
pulled up to support Intel AMT with TLS. RPH4 RPH7 2 3 B
G
2

1 4 2N7002KDWH 1 4
G

+3VALW_PCH Vth= min 1V, max 2.5V +3VS


2 3 2 3 2.2K_0404_4P2R_5%
GPP_C5 /SML0ALERT# ESD 2KV
This signal has a weak internal pull-down. 2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5% 6 1 EC_SMB_CK2
SML1CLK
S

0 = LPC is selected (for EC). (Default) PCH_SMBCLK 6 1 SMB_CLK_S3 EC_SMB_CK2 [27,44,49]


D
S

1 = eSPI is selected (for EC). SMB_CLK_S3 [12,13]


5

QH2A L2N7002KDW1T1G_SOT363-6
D

G
5

QH1A L2N7002KDW1T1G_SOT363-6
G

GPP_B23 /SML1ALERT# /PCHHOT#


0 = Disable Intel DCI-OOB (Default)
1 = Enable Intel DCI-OOB SML1DATA 3 4 EC_SMB_DA2
S

Note:When used as PCHHOT# and strap low, a 150K PCH_SMBDATA SMB_DATA_S3 EC_SMB_DA2 [27,44,49]
3 4
D
S

pull-up is needed to ensure it does not override the SMB_DATA_S3 [12,13]


QH2B L2N7002KDW1T1G_SOT363-6
D

internal pull-down strap sampling. QH1B L2N7002KDW1T1G_SOT363-6

CNVI_RF_RESET#
CNVI_MODEM_CLKREQ CNVI_RF_RESET# [45]
CNVI_MODEM_CLKREQ [45]
1

RH830
71.5K_0402_1% RH829
CNVI@ 75K_0402_5%
CNVI@
2

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 PCH (3/9) HDA,RTC,SMBUS,PM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 16 of 74
5 4 3 2 1
5 4 3 2 1

D UH1G D
BE33 Y3
GPP_A16/CLKOUT_48 CLKOUT_ITPXDP Y4
D7 CLKOUT_ITPXDP_P
[6] PCH_CPU_NSSC_CLK CLKOUT_CPUNSSC_P
C6 B6
[6] PCH_CPU_NSSC_CLK# CLKOUT_CPUNSSC CLKOUT_CPUPCIBCLK PCH_CPU_PCIBCLK# [6]
A6
CLKOUT_CPUPCIBCLK_P PCH_CPU_PCIBCLK [6]
B8
[6] PCH_CPU_BCLK CLKOUT_CPUBCLK_P
C8 AJ6
[6] PCH_CPU_BCLK# CLKOUT_CPUBCLK CLKOUT_PCIE_N0 AJ7
XTAL24_OUT U9 CLKOUT_PCIE_P0
XTAL24_IN U10 XTAL_OUT AH9
XTAL_IN CLKOUT_PCIE_N1 AH10
RH6 1 2 60.4_0402_1% PCH_CLK_BIASREF T3 CLKOUT_PCIE_P1
XCLK_BIASREF AE14 CLK_PCIE_WLAN#
PDG_0 7 0Ω ± % PCH_RTCX1 CLKOUT_PCIE_N2 CLK_PCIE_WLAN CLK_PCIE_WLAN# [45]
BA49 AE15
CRB 0 Ω ± % PCH_RTCX2 RTCX1 CLKOUT_PCIE_P2 CLK_PCIE_WLAN [45] WLAN
need to confirm 0903
BA48
RTCX2 AE6 CLK_PCIE_LAN#
CLKOUT_PCIE_N3 CLK_PCIE_LAN CLK_PCIE_LAN# [51]
BF31 AE7
+3VS GPP_B5/SRCCLKREQ0# CLKOUT_PCIE_P3 CLK_PCIE_LAN [51] LAN
BE31
WLAN_CLKREQ# AR32 GPP_B6/SRCCLKREQ1# AC2
[45] WLAN_CLKREQ# LAN_CLKREQ# GPP_B7/SRCCLKREQ2# CLKOUT_PCIE_N4
BB30 AC3
[51] LAN_CLKREQ# GPP_B8/SRCCLKREQ3# CLKOUT_PCIE_P4
BA30
AN29 GPP_B9/SRCCLKREQ4# AB2
RH89 1 2 10K_0201_5% LAN_CLKREQ# AE47 GPP_B10/SRCCLKREQ5# CLKOUT_PCIE_N5 AB3
SSD_CLKREQ# AC48 GPP_H0/SRCCLKREQ6# CLKOUT_PCIE_P5
WLAN_CLKREQ# [45] SSD_CLKREQ# GPP_H1/SRCCLKREQ7#
RH90 1 2 10K_0201_5% AE41 W4
AF48 GPP_H2/SRCCLKREQ8# CLKOUT_PCIE_N6 W3
RH93 1 2 10K_0201_5% SSD_CLKREQ# AC41 GPP_H3/SRCCLKREQ9# CLKOUT_PCIE_P6
GPU_CLKREQ# AC39 GPP_H4/SRCCLKREQ10# W7 CLK_PCIE_SSD#
GPU_CLKREQ# [24] GPU_CLKREQ# GPP_H5/SRCCLKREQ11# CLKOUT_PCIE_N7 CLK_PCIE_SSD CLK_PCIE_SSD# [45]
C RH94 1 2 10K_0201_5% AE39 W6 M.2 SSD C
GPP_H6/SRCCLKREQ12# CLKOUT_PCIE_P7 CLK_PCIE_SSD [45]
AB48
AC44 GPP_H7/SRCCLKREQ13# AC14
AC43 GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_N8 AC15
GPP_H9/SRCCLKREQ15# CLKOUT_PCIE_P8
V2 U2
V3 CLKOUT_PCIE_N15 CLKOUT_PCIE_N9 U3
CLKOUT_PCIE_P15 CLKOUT_PCIE_P9
T2 AC9
T1 CLKOUT_PCIE_N14 CLKOUT_PCIE_N10 AC11
CLKOUT_PCIE_P14 CLKOUT_PCIE_P10
AA1 AE9 CLK_PCIE_GPU#
CLKOUT_PCIE_N13 CLKOUT_PCIE_N11 CLK_PCIE_GPU CLK_PCIE_GPU# [24]
Y2 AE11
CLKOUT_PCIE_P13 CLKOUT_PCIE_P11 CLK_PCIE_GPU [24] GPU
AC7 R6
CLKOUT_PCIE_N12 CLKIN_XTAL CLKIN_XTAL_LCP [45]
AC6 RH8241 2 10K_0402_5%
CLKOUT_PCIE_P12
7 OF 13
CANNONLAKE-H-PCH_FCBGA874
@
change from 0ohm to 0K on 0 0 by Bing

change to 200K± 1% on 0703


PCH_RTCX1
RH92 2 1 200K_0402_1%
B B
RH1 1 2 10M_0402_5% PCH_RTCX2
YH2
RH30
2 3 XTAL24_IN_LR 1 2 XTAL24_IN YH1
RH32 GND1 OSC2 1 2
XTAL24_OUT 1 2 XTAL24_OUT_LR 1 4 0_0402_5%
OSC1 GND2 32.768KHZ_9PF_X1A0001410002
0_0402_5% 1 1 1 1
24MHZ_6PF_7V24000032 CH2 CH3
CH9 CH10 9P_0402_50V8-B 9P_0402_50V8-B
15P_0402_50V8J 18P_0402_50V8J
2 2 2 2

Stone 05

Default De-Po if want to Po in B M need change P to SM07000 00

L78 @
XTAL24_IN 1 2 XTAL24_IN_LR
1 2

XTAL24_OUT 4 3 XTAL24_OUT_LR
4 3
EXC24CH500U_4P
A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 PCH (3/9) CLOCK,GPPBH
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A3 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 17 of 74
5 4 3 2 1
5 4 3 2 1

D D

UH1A
BE36 AV29
GPP_A11/PME#/SD_VDD2_PWR_EN# GPP_B13/PLTRST# PLT_RST# [27,45,49,50,51]

1
R15 Y47
R13 RSVD9 GPP_K16/GSXCLK Y46 RH43
RSVD10 GPP_K12/GSXDOUT RGB_KB_INT [50]
Y48 100K_0201_5%
RH826 1 2 0_0201_5% AL37 GPP_K13/GSXSLOAD W46
1 AN35 VSS_247 GPP_K14/GSXDIN AA45
@ PAD TH37

2
TP_1 GPP_K15/GSXSRESET#
SPI_SI_R0 RH109 1 2 33_0402_5% SPI_SI AU41 AL47
[49] SPI_SI_R0 SPI_SO_R0 SPI_SO SPI0_MOSI GPP_E3/CPU_GP0
RH111 1 2 33_0402_5% BA45 AM45
[49] SPI_SO_R0 SPI_CS0#_R SPI_CS0# SPI0_MISO GPP_E7/CPU_GP1
RH107 1 2 0_0201_5% AY47 BF32
[49] SPI_CS0#_R SPI_CLK_PCH_0 SPI_CLK_PCH SPI0_CS0# GPP_B3/CPU_GP2
RH105 1 2 33_0402_5% AW47 BC33
[49] SPI_CLK_PCH_0 SPI0_CLK GPP_B4/CPU_GP3
AW48
SPI_WP#_R0 RH250 1 2 33_0402_5% SPI0_CS1# AE44 +3VALW_PCH
SPI_WP# AY48 GPP_H18/SML4ALERT# AJ46
[42] SPI_WP# SPI_HOLD#_R0 SPI_HOLD# SPI0_IO2 GPP_H17/SML4DATA
RH252 1 2 33_0402_5% BA46 AE43
AT40 SPI0_IO3 GPP_H16/SML4CLK AC47 RH825 1 2 100K_0402_5% Follow PDG: 00K
SPI0_CS2# GPP_H15/SML3ALERT# AD48
BE19 GPP_H14/SML3DATA AF47 Strap PIN
BF19 GPP_D1/SPI1_CLK/SBK1_BK1 GPP_H13/SML3CLK AB47 RH753 1 @ 2 4.7K_0402_5%
BF18 GPP_D0/SPI1_CS#/SBK0_BK0 GPP_H12/SML2ALERT# AD47
BE18 GPP_D3/SPI1_MOSI/SBK3_BK3 GPP_H11/SML2DATA AE48
BC17 GPP_D2/SPI1_MISO/SBK2_BK2 GPP_H10/SML2CLK
BD17 GPP_D22/SPI1_IO3 BB44 RH743 2 1 1M_0402_5%
GPP_D21/SPI1_IO2 INTRUDER# VCCRTC
1 OF 13
CANNONLAKE-H-PCH_FCBGA874
@

+3VALW_PCH

change to 00K ull-u on 0703 GPP_H15 /SML3ALERT# (Strap reserved)


External pull-up is required. Recommend 100K if pulled
RH123 1 2 100K_0402_5% SPI_WP# up to 3.3V or 75K if pulled up to 1.8V.
This strap should sample HIGH. There should NOT be
C RH125 1 2 100K_0402_5% SPI_HOLD# RH771 1 @ 2 1K_0402_5% any on-board device driving it to opposite direction C
during strap sampling.
Power Plane: Primary Well
RH772 1 @ 2 1K_0402_5% SPI_SO GPP_H12 /SML2ALERT#
This signal has a weak internal pull-down.
0 = Master Attached Flash Sharing (MAFS) enabled
RH773 1 2 100K_0402_5% SPI_SI RH833 1 @ 2 1K_0402_5% (Default)
SPI_SI_XDP [42]
1 = Slave Attached Flash Sharing (SAFS) enabled.
change to 00K ull-u on 070 Warning: This strap must be configured to ‘ 0’
+3V_SPI (SAFS is disabled) if the eSPI or LPC
+3VALW_PCH +3V_SPI strap is configured to ‘ 0’ (eSPI is
SPI0_MOSI,SPI0_MISO,SPI0_IO[2:3] all have internal pull up disabled)
RC171 1 2 0_0402_5% Notes:
SPI0_MOSI 1. The internal pull-down is disabled after RSMRST#
+3VS 128Mb Flash ROM 1 External pull-up is required. Recommend 100K if pulled de-asserts.
UC3 2. This signal is in the primary well.
CH13 up to 3.3V or 75K if pulled up to 1.8V.
RC172 1 @ 2 0_0402_5% SPI_CS0#_R 1 8 .1U_0402_10V6-K This strap should sample HIGH. There should NOT be
/CS VCC
any on-board device driving it to opposite direction
SPI_SO_R0 2 7 SPI_HOLD#_R0 2 during strap sampling.
DO(IO1) /HOLD(IO3)
+3V_SPI
SPI_WP#_R0 3 6 SPI_CLK_PCH_0 SPI0_IO2
1. If support DS3, connect to +3VS and don't support EC mirror code; /WP(IO2) CLK
External pull-up is required. Recommend 100K if pulled
* 2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code. 4
GND DI(IO0)
5 SPI_SI_R0 up to 3.3V or 75K if pulled up to 1.8V.
This strap should sample HIGH. There should NOT be
2

1 any on-board device driving it to opposite direction


RH119 CH268 during strap sampling.
W25Q128JVSIQ_SO8 10_0402_5% 10P_0402_50V8J
EMC_NS@ @ SPI0_IO3
2 External pull-up is required. Recommend 100K if pulled
1

1 up to 3.3V or 75K if pulled up to 1.8V.


CH11 This strap should sample HIGH. There should NOT be
10P_0402_50V8J any on-board device driving it to opposite direction
EMC_NS@ during strap sampling.
2

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 PCH (5/9) SPI,SMBUS,GPPBEGH
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A2 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 18 of 74
5 4 3 2 1
5 4 3 2 1

UH1B
DMI_CTX_PRX_N0 K34 J3 USB20_N0
[5] DMI_CTX_PRX_N0 DMI0_RXN USB2N_1 USB20_N0 [48]
DMI_CTX_PRX_P0 J35 J2 USB20_P0
[5] DMI_CTX_PRX_P0
DMI_CRX_PTX_N0 C33 DMI0_RXP USB2P_1 N13 USB20_N1 USB20_P0 [48] BACK USB (3.0)
[5] DMI_CRX_PTX_N0 DMI_CRX_PTX_P0 DMI0_TXN USB2N_2 USB20_P1 USB20_N1 [47]
B33 N15
[5] DMI_CRX_PTX_P0 DMI_CTX_PRX_N1 G33 DMI0_TXP USB2P_2 K4 USB20_N2 USB20_P1 [47] LEFT USB (3.0)
[5] DMI_CTX_PRX_N1 DMI1_RXN USB2N_3 USB20_N2 [50]
D DMI_CTX_PRX_P1 F34 K3 USB20_P2 D
[5] DMI_CTX_PRX_P1
DMI_CRX_PTX_N1 C32 DMI1_RXP USB2P_3 M10
USB20_P2 [50] Right USB (3.0)
[5] DMI_CRX_PTX_N1 DMI_CRX_PTX_P1 DMI1_TXN USB2N_4 TYPE-C_PCH_USB20_N4 [39]
B32 L9
[5] DMI_CRX_PTX_P1 DMI_CTX_PRX_N2 K32 DMI1_TXP USB2P_4 M1
TYPE-C_PCH_USB20_P4 Type
[39] C
[5] DMI_CTX_PRX_N2 DMI2_RXN USB2N_5
DMI_CTX_PRX_P2 J32 L2
[5] DMI_CTX_PRX_P2 DMI2_RXP USB2P_5
DMI_CRX_PTX_N2 C31 K7 USB20_N6
[5] DMI_CRX_PTX_N2 DMI_CRX_PTX_P2 DMI2_TXN USB2N_6 USB20_P6 USB20_N6 [35]
B31 K6
[5] DMI_CRX_PTX_P2 DMI_CTX_PRX_N3 G30 DMI2_TXP USB2P_6 L4
USB20_P6 [35] Camera
[5] DMI_CTX_PRX_N3 DMI3_RXN USB2N_7
DMI_CTX_PRX_P3 F30 L3
[5] DMI_CTX_PRX_P3 DMI3_RXP USB2P_7
DMI_CRX_PTX_N3 C29 G4
[5] DMI_CRX_PTX_N3 DMI_CRX_PTX_P3 DMI3_TXN USB2N_8
B29 G5
[5] DMI_CRX_PTX_P3 DMI3_TXP USB2P_8
A25 M6
B25 DMI7_TXP USB2N_9 N8
P24 DMI7_TXN USB2P_9 H3
R24 DMI7_RXP USB2N_10 H2
C26 DMI7_RXN USB2P_10 R10
B26 DMI6_TXP USB2N_11 P9 +3VALW_PCH
F26 DMI6_TXN USB2P_11 G1 RPH5
G26 DMI6_RXP USB2N_12 G2
B27 DMI6_RXN USB2P_12 N3 USB_OC4# 4 5
C27 DMI5_TXP USB2N_13 N2 USB_OC7# 3 6
L26 DMI5_TXN USB2P_13 E5 USB20_N14 USB_OC6# 2 7
DMI5_RXP USB2N_14 USB20_P14 USB20_N14 [45] USB_OC3#
M26 F6 1 8
D29 DMI5_RXN USB2P_14 USB20_P14 [45] Bluetooth
E28 DMI4_TXP AH36 USB_OC0# 10K_1206_8P4R_5%
K29 DMI4_TXN GPP_E9/USB2_OC0# AL40 USB_OC1#
DMI4_RXP GPP_E10/USB2_OC1# USB_OC2# USB_OC1# [50]USB 3.1 RPH6
M29 AJ44
DMI4_RXN GPP_E11/USB2_OC2# USB_OC3# USB_OC2# [47]USB Charger USB_OC0# 4 5
AL41
GPP_E12/USB2_OC3# USB_OC4# USB_OC3# [48]USB 3.1 USB_OC5# 3 6
G17 AV47
F16 PCIE1_RXN/USB31_7_RXNGPP_F15/USB2_OC4# AR35 USB_OC5# USB_OC2# 2 7
A17 PCIE1_RXP/USB31_7_RXPGPP_F16/USB2_OC5# AR37 USB_OC6# USB_OC1# 1 8
B17 PCIE1_TXN/USB31_7_TXNGPP_F17/USB2_OC6# AV43 USB_OC7#
R21 PCIE1_TXP/USB31_7_TXP GPP_F18/USB2_OC7#
P21 PCIE2_RXN/USB31_8_RXN F4 Within RH127 2 1 113_0402_1% 10K_1206_8P4R_5%
B18 PCIE2_RXP/USB31_8_RXP USB2_COMP 500 mils RC184 2 1 1K_0402_5%
F3
C18 PCIE2_TXN/USB31_8_TXN USB2_VBUSSENSE U13 +3VALW_PCH
K18 PCIE2_TXP/USB31_8_TXP RSVD11 G3 RC183 2 1 1K_0402_5%
J18 PCIE3_RXN/USB31_9_RXN USB2_ID
B19 PCIE3_RXP/USB31_9_RXP BE41 GPD7 RH814 1 2 100K_0201_5%
C19 PCIE3_TXN/USB31_9_TXN GPD7
C N18 PCIE3_TXP/USB31_9_TXP G45 C
R18 PCIE4_RXN/USB31_10_RXN PCIE24_TXP G46
Strap Pin, refer PDG
D20 PCIE4_RXP/USB31_10_RXP PCIE24_TXN Y41
C20 PCIE4_TXN/USB31_10_TXN PCIE24_RXP Y40
PCIE4_TXP/USB31_10_TXP PCIE24_RXN
2

F20 G48
G20 PCIE5_RXN PCIE23_TXP G49 RH837
B21 PCIE5_RXP PCIE23_TXN W44
PCIE5_TXN PCIE23_RXP 10K_0201_5%
A22 W43 @
K21 PCIE5_TXP PCIE23_RXN H48
1

J21 PCIE6_RXN PCIE22_TXP H47


D21 PCIE6_RXP PCIE22_TXN U41
C21 PCIE6_TXN PCIE22_RXP U40
B23 PCIE6_TXP PCIE22_RXN F46
C23 PCIE7_TXP PCIE21_TXP G47
J24 PCIE7_TXN PCIE21_TXN R44
L24 PCIE7_RXP PCIE21_RXP T43
F24 PCIE7_RXN PCIE21_RXN
G24 PCIE8_RXN
B24 PCIE8_RXP
C24 PCIE8_TXN
PCIE8_TXP 2 OF 13
CANNONLAKE-H-PCH_FCBGA874
@

+3VS

RH19 2 @ 1 10K_0201_5% PCH_GPU_EVENT#

B B

UH1M

PXS_PWREN RC10 1 2 0_0201_5% PXS_PWREN_R AW13 BD4 CNVI_WR_CLK_N


[27,28,53] PXS_PWREN PCH_GPU_EVENT# GPP_G0/SD_CMD CNV_WR_CLKN CNVI_WR_CLK_N [45]
BE9 BE3 CNVI_WR_CLK_P
[27] PCH_GPU_EVENT# GPP_G1/SD_A0 CNV_WR_CLKP CNVI_WR_CLK_P [45]
BF8
BF9 GPP_G2/SD_A1 BB3 CNVI_WR_D0_N
PXS_RST# PXS_RST#_R GPP_G3/SD_A2 CNV_WR_D0N CNVI_WR_D0_N [45]
RC12 1 2 0_0201_5% BG8 BB4 CNVI_WR_D0_P
[27] PXS_RST# GPP_G4/SD_A3 CNV_WR_D0P CNVI_WR_D0_P [45]
eed to confirm with intel 05 @Stone BE8 BA3 CNVI_WR_D1_N
GPP_G5/SD_CD# CNV_WR_D1N CNVI_WR_D1_N [45]
BD8 BA2 CNVI_WR_D1_P
+1.8VALW PCH_FB_GC6_EN GPP_G6/SD_CLK CNV_WR_D1P CNVI_WR_D1_P [45]
AV13
[27] PCH_FB_GC6_EN GPP_G7/SD_WP BC5 CNVI_WT_CLK_N CNVI_WT_CLK_N [45]
CNV_WT_CLKN BB6 CNVI_WT_CLK_P
CNV_WT_CLKP CNVI_WT_CLK_P [45]
RH815 2 1 10K_0201_5% GPP_J4 AP3
RH809 1 2 20K_0402_5% GPP_J6 RH812 1 @ 2 2.2K_0402_5% +1.8VALW AP2 GPP_I11/M2_SKT2_CFG0 BE6 CNVI_WT_D0_N
GPP_I12/M2_SKT2_CFG1 CNV_WT_D0N CNVI_WT_D0_N [45]
RH810 1 @ 2 2.2K_0201_5% GPP_J9 RH808 1 @ 2 2.2K_0201_5% AN4 BD7 CNVI_WT_D0_P CNVI_WT_D0_P [45]
AM7 GPP_I13/M2_SKT2_CFG2 CNV_WT_D0P BG6 CNVI_WT_D1_N
GPP_I14/M2_SKT2_CFG3 CNV_WT_D1N CNVI_WT_D1_N [45]
Strap Pin BF6 CNVI_WT_D1_P CNVI_WT_D1_P [45]
CNV_WT_D1P
1

AV6 BA1 R10391 1 CNVI@ 2


RH831 RH832 AY3 GPP_J0/CNV_PA_BLANKING CNV_WT_RCOMP 150_0402_1%
20K_0402_5% 20K_0402_5% AR13 GPP_ J1 / CPU_C10_GATE# B12 PCIE_RCOMN
@ @ AV7 GPP_J11/A4WP_PRESENT PCIE_RCOMPN A13 PCIE_RCOMP RH741 2 1 100_0402_1%
GPP_J10 PCIE_RCOMPP CAD Note:
AW3 BE5 SD_1P8_RCOMP RH742 1 2 200_0402_1% Trace width=15 mils ,Spacing=15mil
2

AT10 GPP_J2 SD_1P8_RCOMP BE4 SD_3P3_RCOMP RH819 1 2 200_0402_1%


R10389 1 CNVI@ 2 33_0402_5% GPP_J4 AV4 GPP_J3 SD_3P3_RCOMP BD1
Max length= N/A mils.
[45] CNVI_BRI_DT GPP_J4/CNV_BRI_DT_UART0B_RTS# GPPJ_RCOMP_1P8_1
AY2 BE1 RCOMP_1P8 RH820 1 2 200_0402_1% 0602 Stone: Add refer to EDS&CRB
[45] CNVI_BRI_RSP GPP_J5/CNV_BRI_RSP/UART0B_RXD GPPJ_RCOMP_1P8_2
R10393 1 CNVI@ 2 33_0402_5% GPP_J6 BA4 BE2
[45] CNVI_RGI_DT GPP_J6/CNV_RGI_DT/UART0B_TXD GPPJ_RCOMP_1P8_3
[45] CNVI_RGI_RSP AV3
AW2 GPP_J7/CNV_RGI_RSP/UART0B_CTS# Y35
GPP_J9 AU9 GPP_J8/CNV_MFUART2_RXD RSVD12 Y36
GPP_J9/CNV_MFUART2_TXD RSVD13
BC1 CNVI_LDO_MON 1
13 OF 13 RSVD14 TH38 @
AL35
TP_2
CANNONLAKE-H-PCH_FCBGA874
@

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 19 of 74
5 4 3 2 1
5 4 3 2 1

+3VS

Bit Boot BI S
RH160 2 1 10K_0201_5% PCH_BT_OFF#
GPP_B22 /GSPI1_MOSI (Boot BIOS Strap Bit BBS) Destination
RH161 2 1 10K_0201_5% PCH_WLAN_OFF# This Signal has a weak internal pull-down.
This field determines the destination of accesses to the SPI (Default)
BIOS memory range. Also controllable using Boot BIOS 0
Destination bit (Bus0, Device31, Function0, offset DCh,bit6)
0: SPI(default)
1: LPC LPC
D
Notes: 1 D

1. The internal pull-down is disabled after PCH_PWROK is high.


4. This signal is in the primary well.

+3VALW_PCH
Strap PIN SKU ID +3VALW_PCH
UH1K
RH750 1 @ 2 4.7K_0201_5% BA26
PCH_WLAN_OFF# BD30 GPP_B22/GSPI1_MOSI BA20
[45] PCH_WLAN_OFF# GPP_B21/GSPI1_MISO GPP_D9/ISH_SPI_CS#/GSPI2_CS0#
AU26 BB20 RH152 RH155 RH153 RH163 RH774 RH776
AW26 GPP_B20/GSPI1_CLK GPP_D10/ISH_SPI_CLK/GSPI2_CLK BB16
GPP_B19/GSPI1_CS0# GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO

2
1 1050Ti@ 2

2
10K_0201_5%

10K_0201_5%

10K_0201_5%
10K_0201_5%

10K_0201_5%

10K_0201_5%
AN18
GPP_B18_NO_REBOOT BE30 GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI
[42] GPP_B18_NO_REBOOT GPP_B18/GSPI0_MOSI
BD29 BF14 @ @ @ @ @
[51] LAN_PWR_ON# GPP_B17/GSPI0_MISO GPP_D16/ISH_UART0_CTS#/CNV_WCEN
BF29 AR18
BB26 GPP_B16/GSPI0_CLK GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN BF17

1
1

1
GPP_B15/GSPI0_CS0# GPP_D14/ISH_UART0_TXD/I2C2_SCL BE17
EC_SCI# RH780 1 @ 2 0_0201_5% BB24 GPP_D13/ISH_UART0_RXD/I2C2_SDA
[14,49] EC_SCI# GPP_C9/UART0A_TXD
PCH_BT_OFF# BE23 PCH_GPA18
[45] PCH_BT_OFF# GPP_C8/UART0A_RXD PCH_GPA19
AP24 AG45
[50] PCH_TP_INT GPP_C11/UART0A_CTS# GPP_H20/ISH_I2C0_SCL PCH_GPA20
BA24 AH46
[48] USBDEBUG GPP_C10/UART0A_RTS# GPP_H19/ISH_I2C0_SDA PCH_GPA21
BD21 AH47 PCH_GPA23
AW24 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H22/ISH_I2C1_SCL AH48 PCH_GPA22
AP21 GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_H21/ISH_I2C1_SDA
[24,27] VGA_PWRGD VGA_ALERT#_PCH GPP_C13/UART1_TXD/ISH_UART1_TXD
AU24
GPP_C12/UART1_RXD/ISH_UART1_RXD AV34 PCH_GPA23
AV21 GPP_A23/ISH_GP5 AW32 PCH_GPA22 RH157 RH158 RH159 RH195 RH775 RH777
AW21 GPP_C23/UART2_CTS# GPP_A22/ISH_GP4 BA33 PCH_GPA21
GPP_C22/UART2_RTS# GPP_A21/ISH_GP3

2
1 1050@ 2

10K_0201_5%

10K_0201_5%
10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%
PCH_UART2_TXD BE20 BE34 PCH_GPA20
[45] PCH_UART2_TXD GPP_C21/UART2_TXD GPP_A20/ISH_GP2
PCH_UART2_RXD BD20 BD34 PCH_GPA19
[45] PCH_UART2_RXD GPP_C20/UART2_RXD GPP_A19/ISH_GP1 BF35 PCH_GPA18 @ @ @ @ @
BE21 GPP_A18/ISH_GP0 BD38
[50] PCH_TP_CLK GPP_C19/I2C1_SCL GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
BF21
[50] PCH_TP_DATA

1
1

1
RH846 1 RGB@ 2 0_0201_5% BC22 GPP_C18/I2C1_SDA
[50] PCH_RGBKB_SCL GPP_C17/I2C0_SCL
C RH847 1 RGB@ 2 0_0201_5% BF23 C
[50] PCH_RGBKB_SDA GPP_C16/I2C0_SDA
BE15
BE14 GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4
GPP_D23/ISH_I2C2_SCL/I2C3_SCL 11 OF 13
CANNONLAKE-H-PCH_FCBGA874
@

Function PCH_GPA PCH_GPA 9 PCH_GPA 0 PCH_GPA PCH_GPA PCH_GPA 3

1050 0 X X X X X
+1.8VS_AON reservd by Bing 0627
PCH is input
1050Ti 1 X X X X X
2
G

3 1 VGA_ALERT#_PCH 1160 X 0 X X X X
[27] VGA_ALERT#
S

QV22
LBSS139WT1G_SC70-3
KB BL X X 1 X X X
@
B B
NO KB BL X X 0 X X X

PCIE SSD X X X 1 X X

Optane memory X X X 0 X X

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 PCH (6/9) GPPPABCD, I2C
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 20 of 74
5 4 3 2 1
5 4 3 2 1

+VCCPGPPD +1.8VALW

RH221 1 2 0_0402_5% +3VALW_PCH

+VCCPRIM_1P05 +VCCPFUSE_3P3
D D
1

RH220 1 2 0_0402_5%
RH789 +1.05VALW Need short +VCCPRIM_1P05
0_0805_5%
JC2 UH1H
1 2 AA22 AW9 +VCCPHV_3P3
2

+VCCPRIM_FUSE_1P05 1 2 AA23 VCCPRIM_1P05_1 VCCPRIM_3P3_2


AB20 VCCPRIM_1P05_2 BF47 +VCCPGPPA
JUMP_43X79 VCCPRIM_1P05_3 DCPRTC_1
AB22 BG47

.1U_0402_10V6-K
VCCPRIM_1P05_4 DCPRTC_2 2
RH791 1 2 0_0402_5% @ AB23 RH222 1 2 0_0402_5%
VCCPRIM_1P05_5

CH26
AB27 V23 +VCCPUSB2_3P3
+VCCPRIM_CNV_HVLDO_1P05 AB28 VCCPRIM_1P05_6 VCCPRIM_3P3_5 AN44 +VCCPGPPBC
VCCPRIM_1P05_7 VCCSPI +3V_SPI 1
AB30
RH790 1 2 0_0402_5% 4.174A (VCCPRIM_1P05) AD20 VCCPRIM_1P05_8 BC49 RH223 1 2 0_0402_5%
AD23 VCCPRIM_1P05_9 VCCRTC_1 BD49
+VCCDUSB_1P05 VCCPRIM_1P05_10 VCCRTC_2 +VCCRTC_3P3 +VCCPGPPEF
AD27
AD28 VCCPRIM_1P05_11 AN21
VCCPRIM_1P05_12 VCCPGPPG_3P3 +VCCPGPPG
RH792 1 2 0_0402_5% AD30 AY8 +VCCPHVLDO_3P3 RH224 1 2 0_0402_5%
+VCCPRIM_1P05 +VCCMPHY_1P05 VCCPRIM_1P05_13 VCCPRIM_3P3_3
AF23 BB7
+VCCDSW_1P05 AF27 VCCPRIM_1P05_16 VCCPRIM_3P3_4 +VCCPGPPG
JC4 AF30 VCCPRIM_1P05_17 AC35
VCCPRIM_1P05_18 VCCPGPPHK_1 +VCCPGPPHK
RH7931 @ 2 0_0402_5% 1 2 U26 AC36 RH225 1 2 0_0402_5%
1 2 U29 VCCPRIM_1P05_23 VCCPGPPHK_2 AE35
+VCCCLPLLEBB_1P05 VCCPRIM_1P05_24 VCCPGPPEF_1 +VCCPGPPEF +VCCPUSB2_3P3
V25 AE36
JUMP_43X79 VCCPRIM_1P05_25 VCCPGPPEF_2
V27
RH794 1 2 0_0402_5% @ V28 VCCPRIM_1P05_26 AN24 RH226 1 2 0_0402_5%
Add Jump by Bing 0627 +VCCPGPPD
V30 VCCPRIM_1P05_27 VCCPGPPD
+VCCAZPLL_1P05 V31 VCCPRIM_1P05_28 AN26 +VCCPGPPHK
VCCPRIM_1P05_29 VCCPGPPBC_1 AP26
VCCPGPPBC_2 +VCCPGPPBC
RH795 1 2 0_0402_5% AD31 RH784 1 2 0_0402_5%
+VCCA_SRC_1P05 +VCCPRIM_FUSE_1P05 VCCPRIM_1P05_14
+VCCPRIM_CNV_HVLDO_1P05 AE17 AN32 +VCCPGPPA
VCCPRIM_1P05_15 VCCPGPPA +VCCPHV_3P3
RH797 1 2 0_0402_5% W22 AT44 +VCCPGPPHK
+VCCDUSB_1P05 VCCDUSB_1P05_1 VCCPRIM_3P3_1 +VCCPFUSE_3P3 +VCCPGPPEF
W23 RH746 1 2 0_0402_5%
VCCDUSB_1P05_2 BE48
+VCCA_OCPLL1_1P05 VCCDSW_3P3_1 +VCCDSW +VCCPHVLDO_3P3
BG45 BE49

.1U_0402_10V6-K
+VCCDSW_1P05

.1U_0402_10V6-K
BG46 VCCDSW_1P05_1 VCCDSW_3P3_2
RH787 1 2 0_0402_5% VCCDSW_1P05_2 BB14 RH785 1 2 0_0402_5% 1 1

CH270
C +VCCHDA C

CH81
W31 VCCHDA @
+VCCCLPLLEBB_1P05 VCCPRIM_MPHY_1P05 @
+VCCA_OC_1P05 D1 AG19
+VCCAZPLL_1P05 VCCPRIM_1P05_21 VCCPRIM_1P8_3
E1 AG20 2 2
RH798 1 2 0_0402_5% VCCPRIM_1P05_22 VCCPRIM_1P8_4 AN15
C49 VCCPRIM_1P8_5 AR15
+VCCAMPHYPLL_1P05 VCCAMPHYPLL_1P05_1 VCCPRIM_1P8_6
+VCCA_BCLKPLL2_1P05 D49 BB11
VCCAMPHYPLL_1P05_2 VCCPRIM_1P8_7 +VCCPRIM_1P8
E49
RH799 1 2 0_0402_5% VCCAMPHYPLL_1P05_3 AF19
P2 VCCPRIM_1P8_1 AF20 Option1:Use external VRM(default)
+VCCA_XTAL_1P05 VCCA_XTAL_1P05_1 VCCPRIM_1P8_2 +VCCPHVLDO_1P8 stuff RH816,unstuff RH807
P3
VCCA_XTAL_1P05_2 AG31 Option2:Use internal LDO
VCCPRIM_1P05_20 +VCCFHV1_1P05 unstuff RH816,stuff RH807
+VCCA_SRC_1P05 W19 AF31 +VCCFHV0_1P05 RH807 RH816
+VCCPRIM_1P05 W20 VCCA_SRC_1P05_1 VCCPRIM_1P05_19 +VCCPHVLDO_1P8 1 2 0_0402_5% +VCCPRIM_1P8 1 2 0_0402_5%
VCCA_SRC_1P05_2 +1.8VALW
+VCCFHV1_1P05 AK22 +VCCLDOSRAM_IN_1P24 @
C1 VCCPRIM_1P24_1 AK23
+VCCA_OCPLL1_1P05 VCCAPLL_1P05_4 VCCPRIM_1P24_2
RH199 1 2 0_0402_5% C2
VCCAPLL_1P05_5 AJ22
+VCCFHV0_1P05 V19 VCCDPHY_1P24_1 AJ23
+VCCA_OC_1P05 VCCA_BCLK_1P05 VCCDPHY_1P24_2 +VCCDPHY_1P24 1 1

CH278
1U_0402_6.3V6K
BG5

C10118
4.7U_0603_6.3V6K
VCCDPHY_1P24_3 +VCCDPHY_1P24_MAR
RH200 1 2 0_0402_5% B1
+VCCA_BCLKPLL2_1P05 B2 VCCAPLL_1P05_1 8 OF 13 K47 VCCMPHY_SENSE
B3 VCCAPLL_1P05_2 VCCMPHY_SENSE K46 VSSMPHY_SENSE 2 2@
VCCAPLL_1P05_3 VSSMPHY_SENSE
CANNONLAKE-H-PCH_FCBGA874
@

RH817 1 2 0_0402_5% +VCCDPHY_1P24


+VCCPRIM_1P05
+VCCA_XTAL_1P05
+VCCDPHY_1P24_MAR RH818 1 2 0_0402_5% +VCCLDOSRAM_IN_1P24
+VCCPRIM_1P05 +VCCMPHY_1P05 +VCCDSW_1P05 +VCCA_BCLKPLL2_1P05 +VCCDUSB_1P05
RH8271 2 0_0603_5%
4.7U_0603_6.3V6K

1
CH276
22U_0603_6.3V6-M

CH274
22U_0603_6.3V6-M

C10119

1 1
1U_0402_6.3V6K
CH253
22U_0603_6.3V6-M

1 1 1 1 2 1 +VCCAMPHYPLL_1P05
.1U_0402_10V6-K
CH25
1U_0402_6.3V6K

CH272
1U_0402_6.3V6K
CH29
22U_0603_6.3V6-M

CH30
1U_0402_6.3V6K

2 Place close to BG5


B 2 B
CH292
CH279

@ LH2 1 2 0_0603_5% 2@ 2@
2 2 2 2 1@ 2
1 @ 1 1 1
CH255
1U_0402_6.3V6K

CH275
22U_0603_6.3V6-M
CH273
22U_0603_6.3V6-M

folllow PDG:
placeholder LC filter
If used,need to confirm LC spec
2 2 @ 2 @

VCCRTC +VCCRTC_3P3

RH2161 2 0_0402_5%

1U_0402_6.3V6K

.1U_0402_10V6-K
1 1
CRB lace to PCH

CH245
+VCCPRIM_1P05 CH244
+1.05VALW_SENSE 2 2
1

RC283
100_0402_1%
@
2

+3VALW +VCCHDA +3VALW_PCH +VCCDSW


[63] VCCMPHY_SENSE

[63] VSSMPHY_SENSE
LH1 1 2 0_0402_5% RH2061 2 0_0402_5%
1

@
+3VS +3VALW
@ RC281
100_0402_1%
LH3 1 @ 2 0_0402_5% RH2051 2 0_0402_5%
2

.1U_0402_10V6-K

+VCCA_OCPLL1_1P05 +VCCPHVLDO_3P3 +VCCCLPLLEBB_1P05 +VCCAZPLL_1P05 +VCCA_OC_1P05


.1U_0402_10V6-K

2 1
CH248

CH271

A A
@
.1U_0402_10V6-K

.1U_0402_10V6-K
.1U_0402_10V6-K
4.7U_0603_6.3V6K

1 2
2 1 1 1 2 1
CH288

CH290
1U_0402_6.3V6K

CH291
CH287
1U_0402_6.3V6K

CH289
C10050

1@ 2 2@ 2@ 1@ 2@

Security Classification LC Future Center Secret Data Title

follow CRB
Issued Date 2015/02/26 Deciphered Date 2016/02/26 PCH (7/9) PWR
reservd by Bing 0627 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 21 of 74
5 4 3 2 1
5 4 3 2 1

UH1L
BG3 M24
BG33 VSS_145 VSS_196 M32 UH1I
BG37 VSS_146 VSS_197 M34 A2 AL12
BG4 VSS_147 VSS_198 M49 A28 VSS_1 VSS_73 AL17
BG48 VSS_148 VSS_199 M5 A3 VSS_2 VSS_74 AL21
C12 VSS_149 VSS_200 N12 A33 VSS_3 VSS_75 AL24
D C25 VSS_150 VSS_201 N16 A37 VSS_4 VSS_76 AL26 D
C30 VSS_151 VSS_202 N34 A4 VSS_5 VSS_77 AL29
C4 VSS_152 VSS_203 N35 A45 VSS_6 VSS_78 AL33
C48 VSS_153 VSS_204 N37 A46 VSS_7 VSS_79 AL38
C5 VSS_154 VSS_205 N38 A47 VSS_8 VSS_80 AM1
D12 VSS_155 VSS_206 P26 A48 VSS_9 VSS_81 AM18
D16 VSS_156 VSS_207 P29 A5 VSS_10 VSS_82 AM32 UH1J
D17 VSS_157 VSS_208 P4 A8 VSS_11 VSS_83 AM49 Y14
D30 VSS_158 VSS_209 P46 AA19 VSS_12 VSS_84 AN12 RSVD7 Y15
D33 VSS_159 VSS_210 R12 AA20 VSS_13 VSS_85 AN16 RSVD8
VSS_160 VSS_211 VSS_14 VSS_86 U37
D8 R16 AA25 AN34 RSVD6
VSS_161 VSS_212 VSS_15 VSS_87 U35
E10 R26 AA27 AN38 RSVD5
E13 VSS_162 VSS_213 R29 AA28 VSS_16 VSS_88 AP4 N32
E15 VSS_163 VSS_214 R3 AA30 VSS_17 VSS_89 AP46 RSVD3 R32
E17 VSS_164 VSS_215 R34 AA31 VSS_18 VSS_90 AR12 RSVD4
E19 VSS_165 VSS_216 R38 AA49 VSS_19 VSS_91 AR16 AH15
E22 VSS_166 VSS_217 R4 AA5 VSS_20 VSS_92 AR34 RSVD2 AH14
E24 VSS_167 VSS_218 T17 AB19 VSS_21 VSS_93 AR38 RSVD1
E26 VSS_168 VSS_219 T18 AB25 VSS_22 VSS_94 AT1
E31 VSS_169 VSS_220 T32 AB31 VSS_23 VSS_95 AT16
E33 VSS_170 VSS_221 T4 AC12 VSS_24 VSS_96 AT18 AL2
VSS_171 VSS_222 VSS_25 VSS_97 PREQ#
10 OF 13 PCH_PREQ# [42]
E35 T49 AC17 AT21 AM5
VSS_172 VSS_223 VSS_26 VSS_98 PRDY# PCH_PRDY# [42]
E40 T5 AC33 AT24 AM4
VSS_173 VSS_224 VSS_27 VSS_99 CPU_TRST# CPU_TRST# [42]
E42 T7 AC38 AT26 AK3 PCH_TRIGOUT RH758 1 2 30_0402_5% CPU_TRIGIN [6]
C
E8 VSS_174 VSS_225 U12 AC4 VSS_28 VSS_100 AT29 TRIGGER_OUT AK2
C
VSS_175 VSS_226 VSS_29 VSS_101 TRIGGER_IN PCH_TRIGIN [6]
F41 U15 AC46 AT32
F43 VSS_176 VSS_227 U17 AD1 VSS_30 VSS_102 AT34 CANNONLAKE-H-PCH_FCBGA874
F47 VSS_177 VSS_228 U21 AD19 VSS_31 VSS_103 AT45
VSS_178 VSS_229 VSS_32 VSS_104 @
G44 U24 AD2 AV11 1
G6 VSS_179 VSS_230 U33 AD22 VSS_33 VSS_105 AV39 CC181
H8 VSS_180 VSS_231 U38 AD25 VSS_34 VSS_106 AW10 .1U_0402_10V6-K
J10 VSS_181 VSS_232 V20 AD49 VSS_35 VSS_107 AW4 @
J26 VSS_182 VSS_233 V22 AE12 VSS_36 VSS_108 AW40 2
J29 VSS_183 VSS_234 V4 AE33 VSS_37 VSS_109 AW46
J4 VSS_184 VSS_235 V46 AE38 VSS_38 VSS_110 B47
J40 VSS_185 VSS_236 W25 AE4 VSS_39 VSS_111 B48
J46 VSS_186 VSS_237 W27 AE46 VSS_40 VSS_112 B49
J47 VSS_187 VSS_238 W28 AF22 VSS_41 VSS_113 BA12
J48 VSS_188 VSS_239 W30 AF25 VSS_42 VSS_114 BA14
J9 VSS_189 VSS_240 Y10 AF28 VSS_43 VSS_115 BA44
K11 VSS_190 VSS_241 Y12 AG1 VSS_44 VSS_116 BA5
K39 VSS_191 VSS_242 Y17 AG22 VSS_45 VSS_117 BA6
M16 VSS_192 VSS_243 Y33 AG23 VSS_46 VSS_118 BB41
M18 VSS_193 VSS_244 AG25 VSS_47 VSS_119 BB43
M21 VSS_194 Y38 AG27 VSS_48 VSS_120 BB9
VSS_19512 OF 13VSS_245 Y9 AG28 VSS_49 VSS_121 BC10
VSS_246 AG30 VSS_50 VSS_122 BC13
CANNONLAKE-H-PCH_FCBGA874 AG49 VSS_51 VSS_123 BC15
B B
AH12 VSS_52 VSS_124 BC19
@ VSS_53 VSS_125
AH17 BC24
AH33 VSS_54 VSS_126 BC26
AH38 VSS_55 VSS_127 BC31
AJ19 VSS_56 VSS_128 BC35
AJ20 VSS_57 VSS_129 BC40
AJ25 VSS_58 VSS_130 BC45
AJ27 VSS_59 VSS_131 BC8
AJ28 VSS_60 VSS_132 BD43
AJ30 VSS_61 VSS_133 BE44
AJ31 VSS_62 VSS_134 BF1
AK19 VSS_63 VSS_135 BF2
AK20 VSS_64 VSS_136 BF3
AK25 VSS_65 VSS_137 BF48
AK27 VSS_66 VSS_138 BF49
AK28 VSS_67 VSS_139 BG17
AK30 VSS_68 VSS_140 BG2
AK31 VSS_69 VSS_141 BG22
AK4 VSS_70 VSS_142 BG25
AK46 VSS_71 VSS_143 BG28
VSS_72 9 OF 13 VSS_144
CANNONLAKE-H-PCH_FCBGA874
@
A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 PCH (9/9) VSS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 22 of 74
5 4 3 2 1
5 4 3 2 1

STRAP2 STRAP1 STRAP0 RAMCFG[4:0] H=High: Tied to 1.8V


N17P-G1 GPIO M=Middle: Tied to 0.9V
L L L 00000
L=Low: Tied to 0V
GPIO I/O ACTIVE Function Description I/O Termination L H L 00010

GPIO0 OUT - PWM Output to control NVVDD L H H 00011

GPIO1 OUT - FB Enable for GC6 2.1 H H L 00110

GPIO2 IN - GPU wake signal for GC6 2.1 H H H 00111


D D

GPIO3 OUT - PWM Output to control the SRAM power supply


ROM_SO ROM_SI ROM_SCLK SOR_EXPOSED[3:0] 1:ENABLE 0:DISABLE
GPIO4 OUT - GPU power sequencing for GC6 2.1 --- 1V8_MAIN_EN
L L L 1111 DEFAULT SOR0/1/2/3 ENABLE
GPIO5 IN N/A Active low Frame Lock
L L H 1110
GPIO6 OUT - Phase Shedding, NVVDD_PSI
L H L 1101
GPIO7 OUT N/A Panel Backlight enable
L H H 1100
GPIO8 OUT - Memory voltage Control
H L L 1011
GPIO9 I/O - Active Low Thermal Alert
H L H 1010
GPIO10 OUT - Memory VREF Control (100K pull Down)
H H L 1001
GPIO11 OUT - Panel Power enable
H H H 1000
GPIO12 IN - AC power detect or power supply overdraw input (10K pull High)
L L M 0111
GPIO13 OUT N/A LCD Panel Backlight Enable
L M L 0110
GPIO14 IN N/A Hot Plug Detect for IFPA
L M H 0101
C GPIO15 IN N/A Hot Plug Detect for IFPB C

L H M 0100
GPIO16 OUT - System side PCIe reset monitor
H L M 0011
GPIO17 IN N/A Hot Plug Detect for IFPD
H M L 0010
GPIO18 IN N/A Hot Plug Detect for IFPE
H M H 0001
GPIO19 OUT N/A 3D Vision L/R Signal
H H M 0000
GPIO20 N/A GC5_MODE

GPIO21 I/O N/A UNUSED


1:SMB_ALT_ADDR ENABLE
STRAP5 STRAP4 STRAP3 SMB_ALT_ADDR DEVID_SEL PCIE_CFG VGA_DEVICE
GPIO22 I/O N/A UNUSED 0:SMB_ALT_ADDR DISABLE
M H H 1 1 1 1
GPIO23 OUT - GPU PCIe self-reset control 1:DEVID_SEL REBRAND
M H L 1 1 1 0 0:DEVID_SEL ORIGNAL
GPIO24 IN N/A Hot Plug Detect for IFPF
M L H 1 1 0 1 1:PCIE_CFG LOW POWER
GPIO25 N/A UNUSED
0:PCIE_CFG HIGH POWER
M L L 1 1 0 0
GPIO26 N/A UNUSED
1:VGA_DEVICE ENABLE
L H M 1 0 1 1
GPIO27 IN N/A Hot Plug Detect for IFPC 0:VGA_DEVICE DISABLE
B B
L M H 1 0 1 0

L M L 1 0 0 1

L L M 1 0 0 0

H H H 0 1 1 1
N17P-G1 Power Sequence
H H L 0 1 1 0

H L H 0 1 0 1

H L L 0 1 0 0

+ VS_A VVDDS/+ 0VGS L H H 0 0 1 1

+ VGS L H L 0 0 1 0
VVDD
VVDD L L H 0 0 0 1 DEFAULT

VVDDS/+ 0VGS L L L 0 0 0 0

FBVDDQ

A A
All ower rail ram u time should be larger than 0us VVDDS/P X_DVDD must ram down before VVDD all
and is recommended to be less than ms other ower rails can ram down together with VVDD
T from V _MAI _ to P X_DVDD/ VVDD_Pgood All 3 3V devices that connect to the GPU must be
must T e ceed ms ram down before V _A GPU can T have any 3 3V
leakage ath after V _A and V_MAI ower down
3 All 3 3V devices that connect to the GPU must be
owered after V _A GPU can T have any 3 3V 3 The revious ower rail must ram down to 0% before
leakage ath before V _A resent the ne t ower rail can start ram ing down
Security Classification LC Future Center Secret Data Title
The revious ower rail must ram u to 90% before
the ne t ower rail can start ram ing u Issued Date 2016/02/26 VGA Notes List
2015/02/26 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
EY515
Date: Tuesday, March 20, 2018 Sheet 23 of 74
5 4 3 2 1
5 4 3 2 1

UV1A
1/17 PCI_EXPRESS 3A
D +1.0VGS D
2000mA
Under GPU(below 150mils) Near GPU Mid way
PEX_DVDD AG19

33P_0402_50V8J

33P_0402_50V8J
10U_0603_6.3V6M

22U_0603_6.3V6-M
AJ12 AG21

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K
PLT_RST_VGA#

4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
[27] PLT_RST_VGA# PEX_RST PEX_DVDD 1 1 1 1 1 1 2 1 1 1
PEX_DVDD AG22
CLK_REQ_GPU# AK12 PEX_CLKREQ PEX_DVDD AG24
AH21

RF_NS@

RF_NS@
PEX_DVDD
2 2 2 2 2 2 1 2 2 2

OPT@

OPT@
OPT@

OPT@
OPT@
CLK_PCIE_GPU AL13 PEX_REFCLK PEX_DVDD AH25
[17] CLK_PCIE_GPU

OPT@

OPT@
CV4

CV5

CV7
CV2

CV8
CV6

CV14
CV3
AK13

CD85

CD86
CLK_PCIE_GPU# PEX_REFCLK @
[17] CLK_PCIE_GPU#
PCIE_CRX_GTX_P0 CV12 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P0 AK14 PEX_TX0
[5] PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0 CV13 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N0 AJ14 PEX_TX0
[5] PCIE_CRX_GTX_N0
PCIE_CTX_C_GRX_P0 AN12 PEX_RX0
[5]
[5]
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_N0 AM12 PEX_RX0 PEX_HVDD
PEX_HVDD
AG13
AG15
Near GPU 1A
PCIE_CRX_GTX_P1 CV17 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P1 AH14 PEX_TX1 PEX_HVDD AG16
[5] PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1 CV19 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N1 AG14 PEX_TX1 PEX_HVDD AG18 VGA_MAIN_3V_1.8V VGA_MAIN_3V_1.8V
[5] PCIE_CRX_GTX_N1
PEX_HVDD AG25 Under GPU(below 150mils) Near GPU Mid way
PCIE_CTX_C_GRX_P1 AN14 PEX_RX1 PEX_HVDD AH15
[5] PCIE_CTX_C_GRX_P1

2
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K

PCIE_CTX_C_GRX_N1 AM14 AH18


1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0402_6.3V6M
1U_0402_6.3V6K

4.7U_0402_6.3V6M
PEX_RX1 PEX_HVDD 1 1 1 1 1 1 2 2 1

22U_0603_6.3V6-M
[5] PCIE_CTX_C_GRX_N1
PEX_HVDD AH26 RV29
PCIE_CRX_GTX_P2 CV22 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P2 AK15 PEX_TX2 PEX_HVDD AH27 0_0402_5%
[5] PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2 CV23 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N2 AJ15 AJ27
[5] PCIE_CRX_GTX_N2 PEX_TX2 PEX_HVDD
2 2 2 2 2 2 1 1 2 When VGA_PWRGD is work, CV66 is 100K
OPT@
OPT@

OPT@

OPT@
OPT@

AK27 @ OPT@

OPT@
PEX_HVDD

1
OPT@
OPT@
VGA_MAIN_3V_1.8V
CV302

CV10
CV9
CV303

CV304

CV306
CV305

CV307
PCIE_CTX_C_GRX_P2 AP14 PEX_RX2 PEX_HVDD AL27 RV8 +1.8VS_AON

CV18
[5] PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2 AP15 PEX_RX2 PEX_HVDD AM28 1 2
[5] PCIE_CTX_C_GRX_N2 [20,27] VGA_PWRGD
PEX_HVDD AN28

2
PCIE_CRX_GTX_P3 CV24 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P3 AL16 PEX_TX3 75K_0402_5% 1
[5] PCIE_CRX_GTX_P3

2
PCIE_CRX_GTX_N3 CV25 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N3 AK16 PEX_TX3 @ CV66
[5] PCIE_CRX_GTX_N3
.1U_0402_10V6-K

10K_0402_5%
PCIE_CTX_C_GRX_P3 AN15

10K_0402_5%
PEX_RX3 @
[5] PCIE_CTX_C_GRX_P3 2
PCIE_CTX_C_GRX_N3 AM15 PEX_RX3
[5] PCIE_CTX_C_GRX_N3

1
1

OPT@
RV31
PCIE_CRX_GTX_P4 CV26 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P4 AK17

RV30
[5] PCIE_CRX_GTX_P4 PEX_TX4
PCIE_CRX_GTX_N4 CV27 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N4 AJ17 PEX_TX4 @
[5] PCIE_CRX_GTX_N4
MAX:100mA

2
PCIE_CTX_C_GRX_P4 AN17

G
[5] PCIE_CTX_C_GRX_P4 PEX_RX4
PCIE_CTX_C_GRX_N4 AM17 PEX_RX4
[5] PCIE_CTX_C_GRX_N4
1 3 CLK_REQ_GPU#
VGA_MAIN_3V_1.8V [17] GPU_CLKREQ#
PCIE_CRX_GTX_P5 CV28 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P5 AH17 PEX_TX5 Near GPU

S
[5] PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5 CV29 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N5 AG17 PEX_TX5 N17 1.8V
[5] PCIE_CRX_GTX_N5
PEX_PLL_HVDD AH12 PEX_PLL_HVDD RV7 1 2 0_0402_5% QV5
PCIE_CTX_C_GRX_P5 AP17
0.1U_0402_10V7K

[5] PCIE_CTX_C_GRX_P5 PEX_RX5 LBSS139WT1G_SC70-3

2
PCIE_CTX_C_GRX_N5 AP18 PEX_RX5 1 @ LBSS 39WT G OPT@
[5] PCIE_CTX_C_GRX_N5
Vds 50V RV33
PCIE_CRX_GTX_P6 CV30 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P6 AK18 PEX_TX6 Vgs +- 0V 10K_0402_5%
[5] PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6 CV34 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N6 AJ18 PEX_TX6 N16 3.3V Vgs th 0 5V-- V 1 2 @
[5] PCIE_CRX_GTX_N6 2
OPT@

C RV35 C

1
CV31

PCIE_CTX_C_GRX_P6 AN18 PEX_RX6 0_0402_5%


[5] PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6 AM18 PEX_RX6 @
[5] PCIE_CTX_C_GRX_N6
PCIE_CRX_GTX_P7 CV35 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P7 AL19 PEX_TX7
[5] PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7 CV36 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N7 AK19 PEX_TX7
[5] PCIE_CRX_GTX_N7
PCIE_CTX_C_GRX_P7 AN20 PEX_RX7
[5] PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7 AM20 PEX_RX7
[5] PCIE_CTX_C_GRX_N7
PCIE_CRX_GTX_P8 CV444 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P8 AK20 PEX_TX8
[5] PCIE_CRX_GTX_P8
PCIE_CRX_GTX_N8 CV39 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N8 AJ20 PEX_TX8
[5] PCIE_CRX_GTX_N8
PCIE_CTX_C_GRX_P8 AP20 PEX_RX8
[5] PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_N8 AP21 PEX_RX8
[5] PCIE_CTX_C_GRX_N8
PCIE_CRX_GTX_P9 CV40 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P9 AH20 PEX_TX9
[5] PCIE_CRX_GTX_P9
PCIE_CRX_GTX_N9 CV42 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N9 AG20 PEX_TX9 CV33 1 2 .1U_0402_10V6-K
[5] PCIE_CRX_GTX_N9
OPT@
PCIE_CTX_C_GRX_P9 AN21 PEX_RX9
[5] PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_N9 AM21 PEX_RX9 CV37 1 2 .1U_0402_10V6-K
[5] PCIE_CTX_C_GRX_N9
OPT@
PCIE_CRX_GTX_P10 CV43 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P10AK21 CORE_PLLVDD
[5] PCIE_CRX_GTX_P10
PCIE_CRX_GTX_N10 CV44 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N10AJ21
PEX_TX10 MAX:250mA CV32 1 2 .1U_0402_10V6-K
DG Require 0.1U *3Pcs
[5] PCIE_CRX_GTX_N10 PEX_TX10
OPT@
PCIE_CTX_C_GRX_P10AN23 PEX_RX10
[5] PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_N10AM23 PEX_RX10 CV16 1 2 .1U_0402_10V6-K
[5] PCIE_CTX_C_GRX_N10 UV1O
VGA_MAIN_3V_1.8V OPT@
PCIE_CRX_GTX_P11 CV45 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P11AL22 PEX_TX11 30 ohms @100MHz (ESR=0.05) 11/17 XTAL_PLL
[5] PCIE_CRX_GTX_P11
PCIE_CRX_GTX_N11 CV46 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N11AK22 PEX_TX11 +1.8VS_AON
[5] PCIE_CRX_GTX_N11
1 2 RV4 1 2 0_0603_5% CORE_PLLVDD_GPU AD8 XS_PLLVDD
PCIE_CTX_C_GRX_P11AP23 PEX_RX11 LV1 RV9 1 2 0_0603_5% GPCPLL_VDD H26 GPCPLL_AVDD
[5] PCIE_CTX_C_GRX_P11
22U_0805_6.3V6M

PCIE_CTX_C_GRX_N11AP24 PEX_RX11 SBK160808T-300Y-N RV10 1 @ 2 0_0603_5% +SP_PLLVDD AE8 SP_PLLVDD


[5] PCIE_CTX_C_GRX_N11
OPT@
4.7U_0603_6.3V6K

1 1 @

2
PCIE_CRX_GTX_P12 CV47 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P12AK23 PEX_TX12 RV11 1 @ 2 0_0603_5% +VID_PLLVDD AD7 VID_PLLVDD
[5] PCIE_CRX_GTX_P12
PCIE_CRX_GTX_N12 CV48 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N12AJ23 PEX_TX12 RV211
[5] PCIE_CRX_GTX_N12
@ 10K_0402_5%
2 2
OPT@
CV11

PCIE_CTX_C_GRX_P12AN24 PEX_RX12 @
[5] PCIE_CTX_C_GRX_P12
OPT@
CV15

PCIE_CTX_C_GRX_N12AM24 PEX_RX12
[5] PCIE_CTX_C_GRX_N12

1
PCIE_CRX_GTX_P13 CV49 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P13AH23 PEX_TX13 XTALSSIN H1 XTAL_SSIN XTAL_OUTBUFF J4 XTALOUT
[5] PCIE_CRX_GTX_P13
PCIE_CRX_GTX_N13 CV50 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N13AG23 PEX_TX13
[5] PCIE_CRX_GTX_N13
2

PCIE_CTX_C_GRX_P13AN26 PEX_RX13 RV14 XTAL_IN H3 XTAL_IN XTAL_OUT H2 XTAL_OUT


[5] PCIE_CTX_C_GRX_P13

1
PCIE_CTX_C_GRX_N13AM26 PEX_RX13 10K_0402_5%
[5] PCIE_CTX_C_GRX_N13
OPT@ N17P-G1_FCBGA908 RV46
PCIE_CRX_GTX_P14 CV54 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P14AK24 PEX_TX14 COMMON RV209 10K_0402_5%
[5] PCIE_CRX_GTX_P14
1

PCIE_CRX_GTX_N14 CV55 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N14AJ24 PEX_TX14 ? 1 2 OPT@


[5] PCIE_CRX_GTX_N14
INS57007091 10M_0402_5%

2
PCIE_CTX_C_GRX_P14AP26 PEX_RX14 @ OPT@
B [5] PCIE_CTX_C_GRX_P14 B
PCIE_CTX_C_GRX_N14AP27 PEX_RX14
[5] PCIE_CTX_C_GRX_N14
PCIE_CRX_GTX_P15 CV56 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P15AL25 YV1
[5] PCIE_CRX_GTX_P15 PEX_TX15
PCIE_CRX_GTX_N15 CV57 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N15AK25 PEX_TX15
[5] PCIE_CRX_GTX_N15
XTAL_IN 1 4
PCIE_CTX_C_GRX_P15AN27 OSC1 GND2
[5] PCIE_CTX_C_GRX_P15 PEX_RX15 PEX_TERMP AP29 PEX_TERMP 1 2
PCIE_CTX_C_GRX_N15AM27 PEX_RX15 RV34 2 3 XTAL_OUT
[5] PCIE_CTX_C_GRX_N15 GND1 OSC2
2.49K_0402_1%
OPT@ 1 1
27MHZ_10PF_7V27000050
CV262 OPT@ CV263
N17P-G1_FCBGA908 12P_0402_50V8-J 12P_0402_50V8-J
Change PEG from X8 to X16 INS57006630 OPT@ 2 2 OPT@
?
COMMON
@

Change CV262&CV263 from 10P to 12P


HLZ SIT 0921

1 2 VCCIO TO +1.0VGS 2A
WRST# [49]
RV20

+1.8VS_AON
0_0402_5%
@
For SWG mode
1 2 QV31
H_THRMTRIP# [6,14]
RV1 AON7400A_DFN8-5
1

0_0402_5% VCCIO +1.0VGS


RV2 @
1
For UMA mode
choose one 10K_0402_5%
@
D
CV1
.1U_0402_10V6-K 5
D
S1
S2
1
2
3

2@ +5VALW +5VALW 3
2

5 QV1B S3
LBSS 3 LT G
G

G LBSS138DW1T1G_SOT363-6 Vds 50V


1

S @ Id 00mA 1 @ 1
4
4

Rdson Ma 0ohm RV100 RV339 CV455


D
6

47K_0402_5% 47K_0402_5% CV454 0.01U_0402_25V7K


OVERT# 2 QV1A
Vgs +- 0V @ @ .1U_0402_10V6-K @
[27] OVERT# Vgs th 0 5V-- V 2@ 2
G LBSS138DW1T1G_SOT363-6
2

S @ 1 2
1

A +1.0VGS_PWR_EN# RV103 A
0_0402_5% 1
@ CV456
D
1

D
3

1 .1U_0402_10V6-K
D
6

PLT_RST_VGA# 1 2 2 QV2 5 QV14B @


RV3 G LBSS139WT1G_SC70-3 CV20 2 QV14A G 2
LBSS138DW1T1G_SOT363-6
[27,29,70] 1V0_MAIN_EN
0_0402_5% S @ .1U_0402_10V6-K G LBSS138DW1T1G_SOT363-6 S @
3

4
1

@ 2@ S @
1

1 RV338
CV21 @ 100K_0402_5%
.1U_0402_10V6-K
@
2

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 N17P-G1_PEG I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
EY515
Date: Tuesday, March 20, 2018 Sheet 24 of 74
5 4 3 2 1
5 4 3 2 1

GPU_SNK0_AUX_DN RV1122 1 OPT@ 2 100K_0402_5%


GPU_SNK0_AUX_DP RV15 1 OPT@ 2 100K_0402_5%

UV1L
5/17 IFPAB

.1U_0402_10V6-K
UV1M
DVI HDMI DP
7/17 IFPEF

CV461
SL/DL

IFPA_L3 AN6 GPU_SNK0_DP3N


TXC/TXC GPU_SNK0_DP3N [38]

OPT@
D IFPA_L3 AM6 GPU_SNK0_DP3P 2 D
TXC/TXC GPU_SNK0_DP3P [38]
2 OPT@ 1 IFPAB_RSET AJ8 IFPAB_RSET
RV68 1K_0402_1%
TXD0/0 IFPA_L2 AN3 GPU_SNK0_DP2N DVI HDMI DP
CORE_PLLVDD GPU_SNK0_DP2P GPU_SNK0_DP2N [38] 1
TXD0/0 IFPA_L2 AP3
GPU_SNK0_DP2P [38] SL/DL
RV69 1 2 +IFPAB_PLLVDD AH8 IFPAB_PLLVDD
CORE_PLLVDD IFPE_AUX_SDA AB4
GPU_SNK0_DP1N HDMI1_DAT [36]
0_0603_5% TXD1/1 IFPA_L1 AM5 IFPE_AUX_SCL AB3
GPU_SNK0_DP1P GPU_SNK0_DP1N [38] +IFPEF_PLLVDD AB8 HDMI1_CLK [36]
1 TXD1/1 IFPA_L1 AN5 RV1124 1 2 IFPEF_PLLVDD
GPU_SNK0_DP1P [38]
CV447
.1U_0402_10V6-K

OPT@

0_0603_5%
IFPE_L3 AC5 HDMI1_TXC-
GPU_SNK0_DP0N IFPEF_RSET TXC/TXC
HDMI1_TXC+ HDMI1_TXC- [36]
TXD2/2 IFPA_L0 AK6 2 1 AD6 IFPEF_RSET IFPE_L3 AC4 HDMI CLK
2 GPU_SNK0_DP0P GPU_SNK0_DP0N [38] TXC/TXC HDMI1_TXC+ [36]
TXD2/2 IFPA_L0 AL6 RV1123 OPT@ 1K_0402_1%
GPU_SNK0_DP0P [38] HDMI1_TX0-
IFPE_L2 AC3
TXD0/0 HDMI1_TX0+ HDMI1_TX0- [36]
IFPE_L2 AC2 HDMI D0
GPU_SNK0_AUX_DN TXD0/0 HDMI1_TX0+ [36]
IFPA_AUX_SDA AH6
IFPA_AUX_SCL AJ6 GPU_SNK0_AUX_DP GPU_SNK0_AUX_DN
GPU_SNK0_AUX_DP
[38]
[38]
IFPE TXD1/1 IFPE_L1 AC1 HDMI1_TX1-
HDMI1_TX1- [36]
IFPE_L1 AD1 HDMI1_TX1+ HDMI D1
TXD1/1 HDMI1_TX1+ [36]
AH9 AD3 HDMI1_TX2-
+1.0VGS TXC IFPB_L3
AJ9
ADD Type-C DP Port TXD2/2 IFPE_L0
AD2 HDMI1_TX2+ HDMI1_TX2- [36]
TXC IFPB_L3 TXD2/2 IFPE_L0 HDMI1_TX2+ [36] HDMI D2
RV72 1 2 0_0603_5% +IFPAB_IOVDD AG8 IFP_IOVDD
TXD0/3 IFPB_L2 AP5
AG9 IFP_IOVDD TXD0/3 IFPB_L2 AP6
4.7U_0603_6.3V6K

1 1 1 1
OPT@
OPT@

OPT@
.1U_0402_10V6-K
1U_0402_6.3V6K

.1U_0402_10V6-K

AL7
ADD HDMI Port
TXD1/4 IFPB_L1
TXD1/4 IFPB_L1 AM7
2 2 2 2
OPT@
CV445

+1.0VGS
CV70
CV69

CV71

TXD2/5 IFPB_L0 AM8 DVI HDMI DP


TXD2/5 IFPB_L0 AN8
SL/DL
RV337 1 2 +IFPF_IOVDD AC7 IFP_IOVDD
AL8 0_0603_5% AF2
ADD Type-C DP Port IFPB_AUX_SDA
AK8
IFPF_AUX_SDA
AF3
IFPB_AUX_SCL IFPF_AUX_SCL
AC8 IFP_IOVDD
4.7U_0603_6.3V6K

1 1 1 1 TXC IFPF_L3 AF1


IFPAB
OPT@

1U_0402_6.3V6K

TXC IFPF_L3 AG1


OPT@

OPT@
CV458

CV446
.1U_0402_10V6-K

.1U_0402_10V6-K
C N17P-G1_FCBGA908 AD5 C
INS57009497
ADD DP Port 2 2 2 2 TXD0/3 IFPF_L2
AD4
TXD0/3 IFPF_L2
IFPF
OPT@
CV459

?
CV460

COMMON TXD1/4 IFPF_L1 AF5


@ TXD1/4 IFPF_L1 AF4

TXD2/5 IFPF_L0 AE4


TXD2/5 IFPF_L0 AE3

UV1N

6/17 IFPCD
N17P-G1_FCBGA908
INS57009312
?
COMMON
@
2 OPT@1 IFPCD_RSET AF8 IFPCD_RSET
RV73 1K_0402_1%

CORE_PLLVDD
DVI HDMI DP
SL/DL
LV4 1 2 0_0603_5% +IFPCD_PLLVDD AF7 IFPCD_PLLVDD IFPC_AUX_SDA AG2 GPU_DPC_AUX_DN
GPU_DPC_AUX_DP GPU_DPC_AUX_DN [43]
IFPC_AUX_SCL AG3
GPU_DPC_AUX_DP [43]
1
CV222
.1U_0402_10V6-K

OPT@

IFPC_L3 AG4 GPU_DPC_TX3_DN


TXC/TXC
GPU_DPC_TX3_DP GPU_DPC_TX3_DN [43]
IFPC_L3 AG5
2 TXC/TXC GPU_DPC_TX3_DP [43]
IFPC_L2 AH4 GPU_DPC_TX2_DN
IFPC TXD0/0
TXD0/0 IFPC_L2 AH3 GPU_DPC_TX2_DP GPU_DPC_TX2_DN
GPU_DPC_TX2_DP
[43]
[43]
IFPC_L1 AJ2 GPU_DPC_TX1_DN
TXD1/1
GPU_DPC_TX1_DP GPU_DPC_TX1_DN [43]
IFPC_L1 AJ3
TXD1/1 GPU_DPC_TX1_DP [43]
B IFPC_L0 AJ1 GPU_DPC_TX0_DN B
TXD2/2 GPU_DPC_TX0_DP GPU_DPC_TX0_DN [43]
IFPC_L0 AK1
TXD2/2 GPU_DPC_TX0_DP [43]

GPU_DPC_AUX_DN RV336 1 OPT@ 2 100K_0402_5%


UV1K
GPU_DPC_AUX_DP RV113 1 OPT@ 2 100K_0402_5% 4/17 NC

AC6 NC
+1.0VGS AG10 NC
AG12 NC
LV5 1 2 0_0603_5% +IFPC_IOVDD AF6 IFP_IOVDD AG26 NC
DVI HDMI DP AG7
SL/DL ADD DP Port AJ11
NC
NC
AG6 IFP_IOVDD IFPD_AUX_SDA AK2 AJ26 NC
AK3 AJ28
4.7U_0603_6.3V6K

1 1 1 1 IFPD_AUX_SCL NC
OPT@

CV223
.1U_0402_10V6-K

OPT@

CV68
.1U_0402_10V6-K

OPT@
1U_0402_6.3V6K

AJ4 NC
AJ5 NC
TXC IFPD_L3 AK5 AK26 NC
2 2 2 2 AK4 AK9
TXC IFPD_L3 NC
OPT@
CV227

AL10
ADD HDMI Port NC
CV457

TXD0/3 IFPD_L2 AL4 AL11 NC


IFPD TXD0/3 IFPD_L2 AL3 AL9 NC
AM9 NC
TXD1/4 IFPD_L1 AM4 AN2 NC
TXD1/4 IFPD_L1 AM3 AN9 NC
AP8 NC
TXD2/5 IFPD_L0 AM2 C15 NC
TXD2/5 IFPD_L0 AM1 D19 NC
D20 NC
D23 NC
D26 NC
V32 NC

N17P-G1_FCBGA908
INS57009077
N17P-G1_FCBGA908 ?
INS57009661 COMMON
A ? A
@
COMMON
@

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 N17P-G1_DIGITAL OUT I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
EY515
Date: Tuesday, March 20, 2018 Sheet 25 of 74
5 4 3 2 1
5 4 3 2 1

MAX:250mA MAX:250mA

VGA_MAIN_3V_1.8V
30ohms (ESR=0.01) Bead +FB_PLLAVDD
P/N;SM010007W00
200mA GDDR5
1 2 +FB_PLLAVDD
LV7 Mode H - Mirror Mode Mapping
SBK160808T-300Y-N
OPT@
DATA Bus
Place close to BGA
UV1C Address 0 3 3 3
INS57011274
? FB _CMD0 CS#
COMMON
D D
3/17 FBB FB _CMD A3_BA3
FB _CMD A _BA0
[32,33] FBC_D[0..63]
UV1B G9
FB _CMD3 A _BA
FBC_D0 FBB_D0
2/17 FBA FBC_D1 E9 FBB_D1 FB _CMD A5_BA
FBC_D2 G8 FBB_D2
FBC_D3 F9 FBB_D3 FB _CMD5 W #
FBC_D4 F11 FBB_D4
[30,31] FBA_D[0..63] G11
FBC_D5 FBB_D5 FB _CMD A7_A
FBA_D0 L28 FBA_D0 FBC_D6 F12 FBB_D6
FBA_D1 M29 FBA_D1 FBC_D7 G12 FBB_D7 FB _CMD7 A _A
FBA_D2 L29 FBA_D2 +FB_PLLAVDD FBC_D8 G6 FBB_D8
FBA_D3 M28 FBA_D3 FBC_D9 F5 FBB_D9 FB _CMD ABI#
FBA_D4 N31 FBA_D4 FBC_D10 E6 FBB_D10
FBA_D5 P29 FBA_D5 FB_REFPLL_AVDD K27 FB_REFPLL_AVDD_GPU RV301 1 2 0_0603_5% FBC_D11 F6 FBB_D11 FB _CMD9 A _RFU
FBA_D6 R29 FBA_D6 FBC_D12 F4 FBB_D12
FBA_D7 P28 FBA_D7 @ FBC_D13 G4 FBB_D13 FB _CMD 0 A0_A 0
FBA_D8 J28 FBA_D8 1 FBC_D14 E2 FBB_D14
FBA_D9 H29 FBA_D9 CV172 FBC_D15 F3 FBB_D15 FB _CMD A _A9
FBA_D10 J29 FBA_D10 0.1U_0402_10V7K FBC_D16 C2 FBB_D16
FBA_D11 H28 FBA_D11 OPT@ FBC_D17 D4 FBB_D17 FB _CMD RAS#
FBA_D12 G29 2 FBC_D18 D3
FBA_D12 FBB_D18
FBA_D13 E31 FBA_D13 FBC_D19 C1 FBB_D19 FB _CMD 3 RST#
FBA_D14 E32 FBA_D14 FBC_D20 B3 FBB_D20
FBA_D15 F30 FBA_D15 FBC_D21 C4 FBB_D21 FB _CMD CK #
FBA_D16 C34 FBA_D16 FBC_D22 B5 FBB_D22
FBA_D17 D32 FBA_D17 Under GPU FBC_D23 C5 FBB_D23 FB _CMD 5 CAS#
FBA_D18 B33 FBA_D18 FBC_D24 A11 FBB_D24
FBA_D19 C33 FBA_D19 FBC_D25 C11 FBB_D25 FB _CMD CS#
FBA_D20 F33 FBA_D20 FBC_D26 D11 FBB_D26
FBA_D21 F32 FBA_D21 FBC_D27 B11 FBB_D27 FB _CMD 7 A3_BA3
FBA_D22 H33 FBA_D22 FBC_D28 D8 FBB_D28
FBA_D23 H32 FBA_D23 FBC_D29 A8 FBB_D29 FB _CMD A _BA0
FBA_D24 P34 FBA_D24 FBC_D30 C8 FBB_D30
FBA_D25 P32 FBA_D25 FBC_D31 B8 FBB_D31 FB _CMD 9 A _BA
FBA_D26 P31 FBA_D26 FBC_D32 F24 FBB_D32
FBA_D27 P33 FBA_D27 FBC_D33 G23 FBB_D33 FBB_CMD0 D13 FBC_CS#_L FB _CMD 0 A5_BA
FBA_D28 E24 E14 FBC_CS#_L [32]
C L31 FBA_D28 FBC_D34 FBB_D34 FBB_CMD1 FBC_MA3_BA3_L C
FBA_D29 G24 F14 FBC_MA3_BA3_L [32]
L34 FBA_D29 FBC_D35 FBB_D35 FBB_CMD2 FBC_MA2_BA0_L FB _CMD W #
FBA_D30 D21 A12 FBC_MA4_BA2_L FBC_MA2_BA0_L [32]
L32 FBA_D30 FBC_D36 FBB_D36 FBB_CMD3
FBA_D31 E21 B12 FBC_MA5_BA1_L FBC_MA4_BA2_L [32]
L33 FBA_D31 FBC_D37 FBB_D37 FBB_CMD4 FB _CMD A7_A
FBA_D32 G21 C14 FBC_WE#_L FBC_MA5_BA1_L [32]
AG28 FBA_D32 FBC_D38 FBB_D38 FBB_CMD5
FBA_D33 U30 FBA_CS#_L F21 B14 FBC_MA7_MA8_L FBC_WE#_L [32]
AF29 FBA_D33 FBA_CMD0 FBC_D39 FBB_D39 FBB_CMD6 FB _CMD 3 A _A
FBA_D34 T31 FBA_MA3_BA3_L FBA_CS#_L [30] G27 G15 FBC_MA6_MA11_L
FBC_MA7_MA8_L [32]
AG29 FBA_D34 FBA_CMD1 FBC_D40 FBB_D40 FBB_CMD7
FBA_D35 U29 FBA_MA2_BA0_L FBA_MA3_BA3_L [30] D27 F15 FBC_ABI#_L FBC_MA6_MA11_L [32]
AF28 FBA_D35 FBA_CMD2 FBC_D41 FBB_D41 FBB_CMD8 FB _CMD ABI#
FBA_D36 R34 FBA_MA4_BA2_L FBA_MA2_BA0_L [30] G26 E15 FBC_MA12_RFU_L FBC_ABI#_L [32]
AD30 FBA_D36 FBA_CMD3 FBC_D42 FBB_D42 FBB_CMD9
FBA_D37 R33 FBA_MA5_BA1_L FBA_MA4_BA2_L [30] E27 D15 FBC_MA0_MA10_L FBC_MA12_RFU_L [32]
AD29 FBA_D37 FBA_CMD4 FBC_D43 FBB_D43 FBB_CMD10 FB _CMD 5 A _RFU
FBA_D38 U32 FBA_WE#_L FBA_MA5_BA1_L [30] E29 A14 FBC_MA1_MA9_L FBC_MA0_MA10_L [32]
AC29 FBA_D38 FBA_CMD5 FBC_D44 FBB_D44 FBB_CMD11
FBA_D39 U33 FBA_MA7_MA8_L FBA_WE#_L [30] F29 D14 FBC_RAS#_L FBC_MA1_MA9_L [32]
AD28 FBA_D39 FBA_CMD6 FBC_D45 FBB_D45 FBB_CMD12 FB _CMD A0_A 0
FBA_D40 U28 FBA_MA6_MA11_L FBA_MA7_MA8_L [30] E30 A15 FBC_RST#_L FBC_RAS#_L [32]
AJ29 FBA_D40 FBA_CMD7 FBC_D46 FBB_D46 FBB_CMD13
FBA_D41 V28 FBA_ABI#_L FBA_MA6_MA11_L [30] D30 B15 FBC_CKE_L FBC_RST#_L [32]
AK29 FBA_D41 FBA_CMD8 FBC_D47 FBB_D47 FBB_CMD14 FB _CMD 7 A _A9
FBA_D42 V29 FBA_MA12_RFU_L FBA_ABI#_L [30] A32 C17 FBC_CAS#_L FBC_CKE_L [32]
AJ30 FBA_D42 FBA_CMD9 FBC_D48 FBB_D48 FBB_CMD15
FBA_D43 V30 FBA_MA0_MA10_L FBA_MA12_RFU_L [30] C31 D18 FBC_CS#_H FBC_CAS#_L [32]
AK28 FBA_D43 FBA_CMD10 FBC_D49 FBB_D49 FBB_CMD16 FB _CMD RAS#
FBA_D44 U34 FBA_MA1_MA9_L FBA_MA0_MA10_L [30] C32 E18 FBC_MA3_BA3_H FBC_CS#_H [33]
AM29 FBA_D44 FBA_CMD11 FBC_D50 FBB_D50 FBB_CMD17
FBA_D45 U31 FBA_RAS#_L FBA_MA1_MA9_L [30] B32 F18 FBC_MA2_BA0_H FBC_MA3_BA3_H [33]
AM31 FBA_D45 FBA_CMD12 FBC_D51 FBB_D51 FBB_CMD18 FB _CMD 9 RST#
FBA_D46 V34 FBA_RST#_L FBA_RAS#_L [30] D29 A20 FBC_MA4_BA2_H FBC_MA2_BA0_H [33]
AN29 FBA_D46 FBA_CMD13 FBC_D52 FBB_D52 FBB_CMD19
FBA_D47 V33 FBA_CKE_L FBA_RST#_L [30] A29 B20 FBC_MA5_BA1_H FBC_MA4_BA2_H [33]
AM30 FBA_D47 FBA_CMD14 FBC_D53 FBB_D53 FBB_CMD20 FB _CMD30 CK #
FBA_D48 Y32 FBA_CAS#_L FBA_CKE_L [30] C29 C18 FBC_WE#_H FBC_MA5_BA1_H [33]
AN31 FBA_D48 FBA_CMD15 FBC_D54 FBB_D54 FBB_CMD21
FBA_D49 AA31 FBA_CS#_H FBA_CAS#_L [30] B29 B18 FBC_MA7_MA8_H FBC_WE#_H [33]
AN32 FBA_D49 FBA_CMD16 FBC_D55 FBB_D55 FBB_CMD22 FB _CMD3 CAS#
FBA_D50 AA29 FBA_MA3_BA3_H FBA_CS#_H [31] B21 G18 FBC_MA6_MA11_H FBC_MA7_MA8_H [33]
AP30 FBA_D50 FBA_CMD17 FBC_D56 FBB_D56 FBB_CMD23
FBA_D51 AA28 FBA_MA2_BA0_H FBA_MA3_BA3_H [31] C23 G17 FBC_ABI#_H FBC_MA6_MA11_H [33]
AP32 FBA_D51 FBA_CMD18 FBC_D57 FBB_D57 FBB_CMD24
FBA_D52 FBA_MA2_BA0_H [31] F17 FBC_ABI#_H [33]
AM33 FBA_D52 FBA_CMD19 AC34 FBA_MA4_BA2_H FBC_D58 A21 FBB_D58 FBB_CMD25 FBC_MA12_RFU_H
FBA_D53 FBA_MA4_BA2_H [31] D16 FBC_MA12_RFU_H [33]
AL31 FBA_D53 FBA_CMD20 AC33 FBA_MA5_BA1_H FBC_D59 C21 FBB_D59 FBB_CMD26 FBC_MA0_MA10_H
FBA_D54 FBA_MA5_BA1_H [31] A18 FBC_MA0_MA10_H [33]
AK33 FBA_D54 FBA_CMD21 AA32 FBA_WE#_H FBC_D60 B24 FBB_D60 FBB_CMD27 FBC_MA1_MA9_H
FBA_D55 AA33 FBA_MA7_MA8_H FBA_WE#_H [31] FBC_D61 C24 D17 FBC_RAS#_H FBC_MA1_MA9_H [33]
AK32 FBA_D55 FBA_CMD22 FBB_D61 FBB_CMD28
FBA_D56 Y28 FBA_MA6_MA11_H FBA_MA7_MA8_H [31] FBC_D62 B26 A17 FBC_RST#_H FBC_RAS#_H [33]
AD34 FBA_D56 FBA_CMD23 FBB_D62 FBB_CMD29
FBA_D57 FBA_MA6_MA11_H [31] B17 FBC_CKE_H FBC_RST#_H [33]
AD32 FBA_D57 FBA_CMD24 Y29 FBA_ABI#_H FBC_D63 C26 FBB_D63 FBB_CMD30
FBA_D58 W31 FBA_MA12_RFU_H FBA_ABI#_H [31] E17 FBC_CAS#_H FBC_CKE_H [33]
AC30 FBA_D58 FBA_CMD25 FBB_CMD31
FBA_D59 Y30 FBA_MA0_MA10_H FBA_MA12_RFU_H [31] G14 FBC_CAS#_H [33]
AD33 FBA_D59 FBA_CMD26 FBB_CMD32
FBA_D60 AA34 FBA_MA1_MA9_H FBA_MA0_MA10_H [31] FBC_DBI0# E11 G20
AF31 FBA_D60 FBA_CMD27 FBB_DQM0 FBB_CMD33
FBA_D61 Y31 FBA_RAS#_H FBA_MA1_MA9_H [31] [32] FBC_DBI0# FBC_DBI1# E3 C12 FBB_DEBUG0
AG34 FBA_D61 FBA_CMD28 FBB_DQM1 FBB_CMD34 1 2 FBVDDQ 1.55V
FBA_D62 Y34 FBA_RST#_H FBA_RAS#_H [31] [32] FBC_DBI1# FBC_DBI2# A3 C20
AG32 FBA_D62 FBA_CMD29 FBB_DQM2 FBB_CMD35 RV121
FBA_D63 Y33 FBA_CKE_H FBA_RST#_H [31] [32] FBC_DBI2# FBC_DBI3# C9
AG33 FBA_D63 FBA_CMD30 FBB_DQM3 60.4_0402_1%
V31 FBA_CAS#_H FBA_CKE_H [31] [32] FBC_DBI3# FBC_DBI4# F23
FBA_CMD31 FBB_DQM4 @
R28 FBA_CAS#_H [31] [33] FBC_DBI4# FBC_DBI5# F27 FBB_DEBUG1 1 2
FBA_CMD32 FBB_DQM5
FBA_DBI0# P30 AC28 [33] FBC_DBI5# FBC_DBI6# C30 RV122
FBA_DQM0 FBA_CMD33 FBB_DQM6
[30] FBA_DBI0# FBA_DBI1# F31 R32 FBA_DEBUG0 1 2 [33] FBC_DBI6# FBC_DBI7# A24 60.4_0402_1%
B [30] FBA_DBI1# FBA_DQM1 FBA_CMD34 FBVDDQ 1.55V [33] FBC_DBI7# FBB_DQM7
B
FBA_DBI2# F34 FBA_DQM2 FBA_CMD35 AC32 RV119 @
[30] FBA_DBI2# FBA_DBI3# M32 60.4_0402_1%
FBA_DQM3
[30] FBA_DBI3# FBA_DBI4# AD31 @ FBC_EDC0 D10
FBA_DQM4 FBB_DQS_WP0
[31] FBA_DBI4# FBA_DBI5# AL29 FBA_DEBUG1 1 2 [32] FBC_EDC0 FBC_EDC1 D5
FBA_DQM5 FBB_DQS_WP1
[31] FBA_DBI5# FBA_DBI6#AM32 RV120 [32] FBC_EDC1 FBC_EDC2 C3 D12 FBC_CLK0
FBA_DQM6 FBB_DQS_WP2 FBB_CLK0
[31] FBA_DBI6# FBA_DBI7# AF34 60.4_0402_1% [32] FBC_EDC2 FBC_EDC3 B9 E12 FBC_CLK0# FBC_CLK0 [32]
FBA_DQM7 FBB_DQS_WP3 FBB_CLK0
[31] FBA_DBI7# @ [32] FBC_EDC3 FBC_EDC4 E23 E20 FBC_CLK1 FBC_CLK0# [32]
FBB_DQS_WP4 FBB_CLK1
[33] FBC_EDC4 FBC_EDC5 E28 F20 FBC_CLK1# FBC_CLK1 [33]
FBB_DQS_WP5 FBB_CLK1
FBA_EDC0 M31 [33] FBC_EDC5 FBC_EDC6 B30 FBC_CLK1# [33] FBVDDQ
FBA_DQS_WP0 FBB_DQS_WP6
[30] FBA_EDC0 FBA_EDC1 G31 [33] FBC_EDC6 FBC_EDC7 A23
FBA_DQS_WP1 FBB_DQS_WP7
[30] FBA_EDC1 FBA_EDC2 E33 R30 FBA_CLK0 FBVDDQ [33] FBC_EDC7
FBA_DQS_WP2 FBA_CLK0
[30] FBA_EDC2 FBA_EDC3 M33 R31 FBA_CLK0# FBA_CLK0 [30]
FBA_DQS_WP3 FBA_CLK0
[30] FBA_EDC3 FBA_CLK0# [30]
1

1
FBA_EDC4 AE31 FBA_DQS_WP4 FBA_CLK1 AB31 FBA_CLK1 D9 FBB_DQS_RN0 FBB_WCK01 F8 FBC_WCK0
[31] FBA_EDC4 FBA_EDC5 AK30 AC31 FBA_CLK1# FBA_CLK1 [31] E4 E8 FBC_WCK0_N FBC_WCK0 [32] RV309 RV308
FBA_DQS_WP5 FBA_CLK1 FBB_DQS_RN1 FBB_WCK01
[31] FBA_EDC5 FBA_CLK1# [31]
1

FBC_WCK0_N [32]
1

FBA_EDC6 AN33 FBA_DQS_WP6 B2 FBB_DQS_RN2 FBB_WCK23 A5 FBC_WCK1 10K_0402_5% 10K_0402_5%


[31] FBA_EDC6 FBA_EDC7 AF33 RV306 RV307 A9 A6 FBC_WCK1_N FBC_WCK1 [32] OPT@ OPT@
FBA_DQS_WP7 FBB_DQS_RN3 FBB_WCK23
[31] FBA_EDC7 10K_0402_5% 10K_0402_5% D22 D24 FBC_WCK2 FBC_WCK1_N [32]
FBB_DQS_RN4 FBB_WCK45
2

2
OPT@ OPT@ D28 D25 FBC_WCK2_N FBC_WCK2 [33] FBC_CKE_L
FBB_DQS_RN5 FBB_WCK45
M30 K31 FBA_WCK0 A30 B27 FBC_WCK3 FBC_WCK2_N [33] FBC_CKE_H
FBA_DQS_RN0 FBA_WCK01 FBB_DQS_RN6 FBB_WCK67
2
2

H30 L30 FBA_WCK0_N FBA_WCK0 [30] FBA_CKE_L B23 C27 FBC_WCK3_N FBC_WCK3 [33]
FBA_DQS_RN1 FBA_WCK01 FBB_DQS_RN7 FBB_WCK67
E34 H34 FBA_WCK1 FBA_WCK0_N [30] FBA_CKE_H FBC_WCK3_N [33] FBC_RST#_L
FBA_DQS_RN2 FBA_WCK23
M34 J34 FBA_WCK1_N FBA_WCK1 [30] D6 FBC_RST#_H
FBA_DQS_RN3 FBA_WCK23 FBB_WCKB01
AF30 AG30 FBA_WCK2 FBA_WCK1_N [30] FBA_RST#_L D7
FBA_DQS_RN4 FBA_WCK45 FBB_WCKB01
AK31 AG31 FBA_WCK2_N FBA_WCK2 [31] FBA_RST#_H C6
FBA_DQS_RN5 FBA_WCK45 FBB_WCKB23
FBA_WCK2_N [31]
1

AM34 FBA_DQS_RN6 FBA_WCK67 AJ34 FBA_WCK3 FBB_WCKB23 B6


AF32 AK34 FBA_WCK3_N FBA_WCK3 [31] F26 RV125 RV126
FBA_DQS_RN7 FBA_WCK67 FBB_WCKB45
FBA_WCK3_N [31] E26 10K_0402_5% 10K_0402_5%
FBB_WCKB45
1
1

FBA_WCKB01 J30 FBB_WCKB67 A26 OPT@ OPT@


FBA_WCKB01 J31 RV123 RV124 FBB_WCKB67 A27
2

FBA_WCKB23 J32 10K_0402_5% 10K_0402_5%


FBA_WCKB23 J33 OPT@ OPT@ FBB_PLL_AVDD H17 FB_PLL_AVDD
FBA_WCKB45 AH31
2
2

FBA_WCKB45 AJ31 1
0.1U_0402_10V7K

FBA_WCKB67 AJ32 N17P-G1_FCBGA908


FBA_WCKB67 AJ33 +FB_PLLAVDD @
H31 U27 FB_PLL_AVDD RV305 1 2 0_0603_5% 2
FB_VREF FBA_PLL_AVDD
22U_0603_6.3V6-M

OPT@
CV176

1 @ 1 1
0.1U_0402_10V7K

A A
N17P-G1_FCBGA908
1U_0402_6.3V6K

COMMON
OPT@

? 2 2 2
INS57010640
CV175

@
OPT@
CV173

CV174

@ Under GPU

Under GPU Near GPU


Security Classification LC Future Center Secret Data Title
Issued Date 2015/02/26 Deciphered Date 2016/02/26 N17P-G1_VRAM I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
EY515
Date: Tuesday, March 20, 2018 Sheet 26 of 74
5 4 3 2 1
5 4 3 2 1

+1.8VS_AON
+1.8VS_AON
2

UV1P
INS57014971 RV130

2
2
2
? 0_0402_5% GPU FB Memory (GDDR5) RAMCFG[4:0] STRAP2 STRAP1 STRAP0
COMMON RV187 RV188 RV189
12/17 MISC2 100K_0402_5% 100K_0402_5% 100K_0402_5%
1

X76@ X76@ X76@ Samsung 8Gb K4G80325FB-HC28 0(0x0000) L L L


@

1
1
1
H6 @ PAD 1
8Gb Micron 8Gb MT51J256M32HF-70:A 1(0x0001) L L H
ROM_CS TC1 ROM_SO ROM_SI ROM_SCLK SOR_EXPOSED[3:0] 1:ENABLE 0:DISABLE STRAP2
2
2

ROM_SI H5 ROM_SI RV197 RV198 RV199 STRAP1 Hynix 8Gb H5GC8H24MJR-R0C 2(0x0010) L H L
ROM_SO H7 ROM_SO 100K_0402_5% 100K_0402_5% 100K_0402_5% L L H 1110 SOR0 DISABLE
STRAP0 J2 STRAP0 ROM_SCLK H4 ROM_SCLK @ @ OPT@ STRAP0
STRAP1 J7 SOR1 ENABLE
STRAP1 Samsung 4Gb K4G41325FE-HC28 7(0x0111) H H H
1
1

SOR2 ENABLE
1

D STRAP2 J6 STRAP2 D

2
STRAP3 J5 STRAP3 SOR3 ENABLE
RV17 STRAP4 J3 STRAP4 ROM_SO RV192 RV193 RV194 4Gb Hynix 4Gb H5GC4H24AJR-R0C 6(0x0110) H H L
STRAP5 1 2 MULTI_STRAP J1 STRAP5 100K_0402_5% 100K_0402_5% 100K_0402_5%
ROM_SI X76@ X76@ X76@
1

0_0402_5% Micron 4Gb EDW4032BABG-70-F 8(0x1000) L L M

1
@ RV16 ROM_SCLK
40.2K_0402_1% BUFRST E1
@
1
2

2
2

RV203
10K_0402_5% RV200 RV201 RV202
100K_0402_5% 100K_0402_5% 100K_0402_5%
@
OPT@ OPT@ @
2

1
1

N17P-G1_FCBGA908
@ E1 is FB_CLAMP of N16P +1.8VS_AON

STRAP5 STRAP4 STRAP3 SMB_ALT_ADDR DEVID_SEL PCIE_CFG VGA_DEVICE

2
2

2
+3VS
RV19 RV21 RV74 L L H 0 0 0 1
100K_0402_5% 100K_0402_5% 100K_0402_5%
OPT@ @ @
2

+3VALW RV12 RV51

1
1

1
10K_0402_5% 1 2 1: SMB_ALT_ADDR ENABLE
PCH_FB_GC6_EN [19]
OPT@ STRAP5
0_0402_5% 0: SMB_ALT_ADDR DISABLE
2

RV57 @ STRAP4
1

10K_0402_5%
OPT@ FB_GC6_EN_R STRAP3 1: DEVID_SEL REBRAND
0: DEVID_SEL ORIGNAL
1

D
3

2
2
5 QV7B
G LBSS138DW1T1G_SOT363-6 RV78 RV75 RV77 1: PCIE_CFG LOW POWER
S OPT@ 100K_0402_5% 100K_0402_5% 100K_0402_5%
4

@ OPT@ OPT@ 0: PCIE_CFG HIGH POWER

1
1
6

D
FB_GC6_EN 2 QV7A 1: VGA_DEVICE ENABLE
G LBSS138DW1T1G_SOT363-6
S OPT@ 0: VGA_DEVICE DISABLE
1
1

C C
+1.8VS_AON PLT_RST_VGA# RV313
10K_0402_5%
OPT@
2
1

+1.8VS_AON
2

RV1137
RV1139 1K_0402_5% RV55 1 @ 2 0_0402_5% VGA_MAIN_3V_1.8V +3VS
+1.8VS_AON
1

0_0402_5% OPT@ +3VS


@ RV1136 RV1138 Add RV13 for VGA_MAIN_3V_1.8V and change RV88 from stuff to ns
BAT54AW
2

1K_0402_5% 0_0402_5% HLZ SIT 0922


1

VF=0.32V @ IF=1mA

1
1
OPT@ @

2
RV13 RV334
Reserve RV333 & DV9 & RV334 & RV335 for DG new sequence
2

1
2

0_0402_5% 10K_0402_1% RV104


RV5 RV6 Hai Y520 SVT @ 10K_0402_5%
2.2K_0402_5% 2.2K_0402_5% DV9 OPT@

2
2
OPT@ OPT@

1
5
G

PXS_PWREN RV220 1 2 0_0402_5% 3


DV3
1

[19,28,53] PXS_PWREN 1
VGA_SMB_CK2 4 3 1V8_MAIN_EN_R 2 NVVDD_EN [29,71] RV49 1 2 0_0402_5% 2
EC_SMB_CK2 [16,44,49] [69] VDDQPWROK 1
S

+1.8VS_AON
VGA_PWRGD [20,24]

1
+1.8VS_AON +3VS BAT54AW_SOT323-3 RV64 1 @ 2 0_0402_5% 3
QV3B [27,71] NVVDD_PWRGD
RV335
LBSS138DW1T1G_SOT363-6 100K_0402_1%
BAT54AW_SOT323-3
2

OPT@ @ RV1127 1 2 0_0402_5%


[70] 1.0VGS_PG
1

RV59 RV333 1 @ 2 0_0402_5% OPT@

2
RV319 0_0402_5%
1

10K_0402_5%
2
G

OPT@ RV320
1

@ 10K_0402_5% Add DV3 for VGA_PWRGD


2

VGA_SMB_DA2 1 6 OPT@
EC_SMB_DA2 [16,44,49] ADD PXS_PWREN for NVVDDS & 1V0_MAIN_EN Power down +3VS HLZ SIT 0922
S

+1.8VS_AON
2
2
G

RV318
HLZ SIV 0725
QV3A GPU_EVENT# 3 1 GPU_EVENT#_R 1 2 DV8
PU AT C SID +3VS A D 7K PCH_GPU_EVENT# [19]
LBSS138DW1T1G_SOT363-6
S

OPT@ 0_0402_5% PXS_PWREN 1 2


For Optimus Power OFF
2

QV8 @ RV331
LBSS139WT1G_SC70-3 RB751V-40_SOD323-2 RV89 8.2K_0402_1%
OPT@ OPT@ 10K_0402_5% OPT@ Use RV331 & RV330 and unstuff RV89 based on NV suggestion
@
HLZ SIV 0811
2

RV317 1 @ 2 0_0402_5% 1V8_MAIN_EN_R RV1135 1 2 0_0402_5%


DV7
1

1V8_MAIN_EN RV1134 1 @ 2 0_0402_5%2


For GC6 Power OFF 1 RV98 1 2 0_0402_5%
NVVDD_PWRGD 1V0_MAIN_EN [24,29]
3
For Power ON
[27,71] NVVDD_PWRGD
1

BAT54AW_SOT323-3 RV330
B 1 OPT@
RV1126 2 OPT@ 10K_0402_1% B
+3VS
10K_0402_5% @
2

+3VS
Delete RV96(ns)
Delete FRM_LCK# +1.8VS_AON Delete RV40 & RV97 0ohm & RV54 (ns) HLZ SIT 0922
HLZ SIV 0725

2
+1.8VS_AON +3VALW RV1129
10K_0402_5%
UV1Q 1V8_MAIN_EN RV27 2 OPT@ 1 10K_0402_5% OPT@
INS57014190

2
? GPU_GPIO3 RV1125 1 OPT@2 10K_0402_5% RV1132

1
COMMON DV4 10K_0402_5%
Rick 0804
2

10/17 MISC1 FB_GC6_EN_R RV110 1 2 0_0402_5% 2 OPT@ 1V8_MAIN_EN_R


RV214 NVVDD_PSI RV28 1 @ 2 10K_0402_5%
100K_0402_5% 1
FBVDDQ_PWR_EN [29,69]

3
OPT@ D
I2CS_SCL T4 VGA_SMB_CK2 +1.8VS_AON VGA_ALERT# RV23 1 OPT@ 2 10K_0402_5% NVVDD_PWRGD RV325 1 OPT@ 2 1K_0402_1% 3 5 QV32B
1

I2CS_SDA T3 VGA_SMB_DA2 Internal Thermal Sensor G LBSS138DW1T1G_SOT363-6


VGA_AC_DET_R RV26 1 OPT@ 2 100K_0402_5% S OPT@

4
1

OVERT# M1 OVERT I2CC_SCL R2 VGA_EDID_CLK RV212 1 2 2.2K_0402_5% OPT@ 1.0VGS_PG RV1128 1 @ 2 0_0402_5% BAT54CW_SOT323-3
[24] OVERT#
I2CC_SDA R3 VGA_EDID_DATA RV210 1 2 2.2K_0402_5% OPT@ OPT@ RV112

6
1 AP9 200K_0402_5% D
TV5 @ TS_VREF 1
I2CB_SCL R7 I2CB_SCL RV22 1 2 2.2K_0402_5% OPT@ OPT@ 1V8_MAIN_EN 2 QV32A
K4 THERMDN I2CB_SDA R6 I2CB_SDA RV25 1 2 2.2K_0402_5% OPT@ SYS_PEX_RST_MON# RV39 1 @ 2 10K_0402_5% C10177 G LBSS138DW1T1G_SOT363-6
2

1U_0402_6.3V6K S OPT@

1
1

K3 2 OPT@
THERMDP
GPU_PEX_RST_HOLD# RV18 1 @ 2 10K_0402_5% RV1133
GPIO0 P6 NVVDD_VID 10K_0402_5%
1 AM10 M3 FB_GC6_EN NVVDD_VID [71]
TV1 @ JTAG_TCK GPIO1 @
TV2 @ 1 AP11 JTAG_TMS GPIO2 L6 GPU_EVENT#
2

TV3 @ 1 AM11 JTAG_TDI GPIO3 P5 GPU_GPIO3


TV4 @ 1 AP12 JTAG_TDO GPIO4 P7 1V8_MAIN_EN
AN11 L7 1V8_MAIN_EN [28] MEM_VREF
JTAG_TRST GPIO5 RV32 2 OPT@ 1 100K_0402_5%
AK11 NVJTAG_SEL GPIO6 M7 NVVDD_PSI_GPU RV107 2 1 0_0402_5% Combine NVVDD_PSI&NVVDDS_PSI
NVVDD_PSI [71]
2

N8 @DG-07875-001 V04
RV37
GPIO7
L3 VRAM_VDDQ_ADJ @
Delete 3D VISION
GPIO8 VRAM_VDDQ_ADJ [69]
10K_0402_5% GPIO9 M2 VGA_ALERT#
2

OPT@ GPIO10 L1 MEM_VREF


MEM_VREF [30,32]
RV24 GPIO11 M5
1

10K_0402_5% GPIO12 N3 VGA_AC_DET_R


OPT@ GPIO13 M4
GPIO14 N4 +1.8VS_AON
IFPA_HPD [38]
1

GPIO15 P2 RV322 VGA_MAIN_3V_1.8V +1.8VS_AON


GPIO16 R8 SYS_PEX_RST_MON#_R 1 @ 2 SYS_PEX_RST_MON# +3VS
GPIO17 M6 0_0402_5% +1.8VS_AON
GPIO18 R1 IFPE_HPD VRAM_VDDQ_ADJ RV41 2 @ 1 10K_0402_5% RV38
P3 IFPE_HPD [36]
GPIO19 1 2 0_0402_5%
GPIO20 P4 GC5_MODE 1 @ TV7 1
2

GPIO21 P1 RV43 2 OPT@ 1 10K_0402_5% @


2

GPIO22 P8 CV58 RV52 RV50


A
GPIO23 T8 GPU_PEX_RST_HOLD#_R @ 1 RV321 2 GPU_PEX_RST_HOLD# RV216 .1U_0402_10V6-K 10K_0402_5% 10K_0402_5% A
L2 0_0402_5% 10K_0402_5% 2 OPT@ @ @
GPIO24 DV2
GPIO25 R4 @
1

GPIO26 R5 GPU_PEX_RST_HOLD# 2
1

U3 IFPC_HPD UV2 1 PLT_RST_VGA#


GPIO27 IFPC_HPD [43] PLT_RST_VGA# [24]
SYS_PEX_RST_MON# 3
N17P-G1_FCBGA908 PLT_RST# 1 5
VGA_ALERT# [20] [18,45,49,50,51] PLT_RST# B VCC
1

@ BAT54AW_SOT323-3
2 RV311
[19] PXS_RST# A @ 100K_0402_5%
3 4 SYS_PEX_RST_MON# @
VGA_ALERT# 2 1 GND Y
2
1

DV6 RB751V-40_SOD323-2 RV44 1 2 0_0402_5%


OPT@ 74LVC1G08SE-7 SOT353-1-5
RV217 OPT@ @
VGA_AC_DET_R 2 1 100K_0402_5%
VGA_AC_DET [49]
1

DV1 RB751V-40_SOD323-2 OPT@ Title


Security Classification LC Future Center Secret Data
2

@ RV324
100K_0402_5% N17P-G1_GPIO,STRAP
Issued Date 2015/02/26 Deciphered Date 2016/02/26
OPT@
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 27 of 74
5 4 3 2 1
5 4 3 2 1

5A Peak 8A UV1E UV1F


FBVDDQ
INS57016640 INS57017501 1.8V Total 1A (AON+MAIN)
? ? UV1G
COMMON COMMON 0.5A INS57017097
14/17 FBVDDQ 17/17 VDD18/AON ?
+1.8VS_AON NVVDDS COMMON
Under GPU(below 150mils)
AA27 FBVDDQ Under GPU Near GPU 8/17 VDDS
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 1 1 1 1 1 1 1 AA30 FBVDDQ RV65


AB27 FBVDDQ 1V8_AON J8 +VDD_AON 2 1 AA12 VDDS
AB33 FBVDDQ 1V8_AON K8 AA16 VDDS

4.7U_0805_25V6-K
0.1U_0402_10V7K

0.1U_0402_10V7K
AC27 FBVDDQ 1 1 1 1 0_0603_5% AA19 VDDS
2 2 2 2 2 2 2 2 2 2 2 2
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

1U_0603_10V6K
@

@
CV114

CV103

CV104

CV105

CV106

CV115

AD27 VDD18 L8 AA23

@
FBVDDQ VDDS
OPT@

OPT@
CV112

CV113

CV100

CV101

CV102
CV99

AE27 FBVDDQ VDD18 M8 AC14 VDDS


AF27 FBVDDQ AC21 VDDS
AG27 2 2 2 2 M14
FBVDDQ VDDS

CV118
OPT@

OPT@

OPT@
OPT@
CV116

CV117
CV443
D B13 FBVDDQ M21 VDDS D
B16 FBVDDQ P12 VDDS
B19 FBVDDQ P16 VDDS
FBVDDQ E13 FBVDDQ P19 VDDS
E16 P23
Under GPU(below 150mils) E19
H10
FBVDDQ
FBVDDQ 0.5A T14
T21
VDDS
VDDS
FBVDDQ VDDS
VGA_MAIN_3V_1.8V
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

2 2 2 2 H11 FBVDDQ U17 VDDS


H12 FBVDDQ V18 VDDS
H13 FBVDDQ N17P-G1_FCBGA908 RV53 W14 VDDS
H14 +VDD_MAIN 2 1 W21

@
FBVDDQ VDDS
1 1 1 1 H15 FBVDDQ
OPT@

OPT@

OPT@
@

0.1U_0402_10V7K
CV94

CV86

CV87

CV88

4.7U_0603_6.3V6K
0.1U_0402_10V7K
H16 FBVDDQ 1 1 1 1 0_0603_5%

1U_0603_10V6K
H18

@
FBVDDQ
H19 FBVDDQ VDDS_SENSE U1
H20 FBVDDQ
H21 2 2 2 2
FBVDDQ GNDS_SENSE U2

OPT@

OPT@

OPT@
OPT@
CV119

CV122
CV120

CV121
H22 FBVDDQ
H23 FBVDDQ
FBVDDQ H24 FBVDDQ N17P-G1_FCBGA908
Near GPU H8

@
FBVDDQ
H9 FBVDDQ Under GPU Near GPU
Near GPU L27 FBVDDQ

@
M27 TV8 1
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

FBVDDQ
10U_0603_6.3V6M

10U_0603_6.3V6M

2 2 1 1 1 1 1 N27 FBVDDQ
33P_0402_50V8J

33P_0402_50V8J

@
1 1 P27 FBVDDQ TV9 1
R27 FBVDDQ
T27 trace width: 16mils
CALIBRATI PI GDDR5
OPT@

OPT@

OPT@
@

FBVDDQ
1 1 2 2 2 2 2
OPT@
RF_NS@

RF_NS@

T30 Connect NVVDD to NVVDDS


CV90

CV91

CV97

CV92

CV93

FBVDDQ differential voltage sensing.


2 2
OPT@

OPT@
CV95

CV89

T33 FBVDDQ
19A Peak 42A Cost down list: differential signal routing.
CD89

CD90

V27
W27
FBVDDQ
FBVDDQ
FB_CAL_ _PD_VDDQ 0 hm 4.7U 1Pcs
W30 FBVDDQ 1U 1Pcs
W33 NVVDD NVVDDS
Y27
FBVDDQ
FBVDDQ
FB_CAL_ _PU_G D 0 hm
Near GPU
FB_CAL_ T RM_G D 0 hm

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
10U_0603_6.3V6M

10U_0603_6.3V6M
330U_D2_2.5VY_R9M
1 2 2 1 1 1

FBVDDQ_SENSE F1 FBVDDQ_SENSE_GPU RV90 1 OPT@ 2 0_0402_5%


+
POSCAP

OPT@
FBVDD_VCC_SENSE [69] 1 1 2 2 2

CV435

CV436

CV432
OPT@
OPT@
C 2 C

OPT@

OPT@
@

CV428

CV429
PROBE_FB_GND F2 FBVDDQ_SENSE_GND_GPU RV91 1 2 0_0402_5%

CV425
FB_CAL_PD_VDDQJ27 FBCAL_VDDQ 1 2 FBVDDQ
RV92 40.2_0402_1%OPT@
FB_CAL_PU_GND H27 FBCAL_GND 1 2
RV93 40.2_0402_1%OPT@
FB_CALTERM_GND H25 FBCAL_TERM 1 2
RV94 60.4_0402_1%OPT@
Under GPU
Place near balls
N17P-G1_FCBGA908

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
@

1 1 1 1 1 1 1 1 1 1

FBVDDQ
2 2 2 2 2 2 2 2 2 2

OPT@

OPT@

OPT@

OPT@

@
OPT@

OPT@

OPT@

OPT@

OPT@
CV433

CV434

CV430

CV431

CV437

CV438

CV439

CV440

CV441

CV442
FBVDD_VCC_SENSE RV310 1 OPT@ 2 2_0402_5%

PLAC MIDWAY B TW FBA A D FBB

2A
A 7 0 L
Vds 30V
+1.8VS_AON +1.8VS_AON VGA_MAIN_3V_1.8V
Ids 5A
V20B+ Rdson mohm@Vgs V
QV16
0mohm@Vgs V
AON7408L_DFN8-5 mohm@Vgs> 0V
Vgs +- 0V
1

+3VS +5VALW RV42


RV66 1 Vgsth ~3V
470_0603_5% 47K_0402_5% 5 S1 2
B B
D S2
1

OPT@ OPT@ 3
S3
2

RV108
2

1
RV109 47K_0402_5% +5VALW
2 1 1
10K_0402_5% OPT@ OPT@ CV73 RV85 CV74
4

OPT@ Vg=16.4V@AC CV72 0.01U_0402_25V7K 47_0603_5% 10U_0603_6.3V6M


2

@
D Vg=7.38V@Battery 0.1U_0402_25V6 OPT@ OPT@
1

1 2 2
@

PXS_PWREN# 2 RV86

2
G 47K_0402_5% 1 2
QV13 OPT@ RV83
1

D S 2N7002KW_SOT323-3 1K_0402_5% 2
3

D
2 QV18 OPT@ OPT@
[19,27,53] PXS_PWREN

1
G LBSS139WT1G_SC70-3 +1.8VGS_PWR_EN# 5 RV47 CV75 D
S OPT@ G 210K_0402_1% 0.1U_0402_25V6 +1.8VGS_PWR_EN# 2
3
1

1
LBSS138DW1T1G_SOT363-6

S QV9B OPT@ OPT@ G QV20


4
LBSS138DW1T1G_SOT363-6

OPT@ 2N7002KW_SOT323-3
2
6

D S
RV115 3 OPT@
100K_0402_5% RV58 1 2 0_0402_5% 2 QV9A
[27] 1V8_MAIN_EN
@

G OPT@
2

0.1U_0402_25V6

S
1
1

2
@

@
CV38

PD3 0_0402_5% RV84


3 PR4 1 2 100K_0402_5% Add +1.8V_MAIN discharger circuit
@

1 1 HLZ SIT 0928


2
@

0_0402_5%
2 PR5 1 2

LBAT54SWT1G_SOT323-3
@

Delete PD3503 and Reserve PD3/PR4/PR5/CV38


Add +1.8V-AON discharger circuit HLZ SIV 0811 HLZ SIT 0923

Change QV18 from LBSS138LT1G_SOT-23-3 to LBSS139WT1G_SC70-3 Hai Y520 SVT

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 N17P-G1_POWER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
EY515
Date: Tuesday, March 20, 2018 Sheet 28 of 74
5 4 3 2 1
5 4 3 2 1

UV1I UV1J UV1H 47A Peak90A Follow NV suggestion for NVVDD Hai Y520 SVT UV1D
INS57019119 INS57019839 INS57020144 INS57020321
? ? ? ?
COMMON COMMON COMMON COMMON
NVVDD NVVDD
A2
A33
GND
GND
15/17 GND_1/2
GND
GND
AM25
AN1 N19 GND
16/17 GND_2/2

GND T28
9/17 XVDD

CONFIGURABLE
NEAR GPU UNDER GPU 13/17 NVVDD

AA13 GND GND AN10 N2 GND GND T32 POWER NVVDD AA14 VDD
AA15 GND GND AN13 N21 GND GND T5 CHANNELS AA21 VDD

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
AA17 GND GND AN16 N23 GND GND T7 XVDD U4 1 1 1 1 1 1 1 1 1 1 1 1 1 AB13 VDD

33P_0402_50V8J

33P_0402_50V8J

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
AA18 GND GND AN19 N28 GND GND U12 XVDD U5 1 1 AB15 VDD
D D

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
AA20 GND GND AN22 N30 GND GND U14 XVDD U6 AB17 VDD
AA22 GND GND AN25 N32 GND GND U16 XVDD U7 AB18 VDD
2 2 2 2 2 2 2 2 2 2 2 2 2

RF_NS@

RF_NS@
AB12 GND GND AN30 N33 GND GND U19 XVDD U8 AB20 VDD
2 2

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
@

@
CV148

CV135

CV136

CV147

CV138

CV139

CV145

CV146
AB14 GND GND AN34 N5 GND GND U21 XVDD V1 AB22 VDD

OPT@

OPT@

OPT@

OPT@

OPT@
CV140

CV141

CV142

CV143

CV144
CD94

CD93
AB16 GND GND AN4 N7 GND GND U23 XVDD V2 AC12 VDD
AB19 GND GND AN7 P13 GND GND V12 XVDD V3 AC16 VDD
AB2 GND GND AP2 P15 GND GND V14 XVDD V4 AC19 VDD
AB21 GND GND AP33 P17 GND GND V16 AC23 VDD
AB23 GND GND B1 P18 GND GND V19 M12 VDD
AB28 GND GND B10 P20 GND GND V21 XVDD V5 M16 VDD
AB30 B22 P22 V23 V6 M19
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
GND GND GND GND XVDD VDD

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
AB32 B25 R12 W13 V7 M23

4.7U_0603_6.3V6K
GND GND GND GND XVDD 1 1 1 1 1 1 1 VDD
AB5 GND GND B28 R14 GND GND W15 XVDD V8 N13 VDD
AB7 GND GND B31 R16 GND GND W17 XVDD W2 N15 VDD
AC13 B34 R19 W18 W3 N17
OPT@

GND GND GND GND XVDD @ VDD


2 2 2 2 2 2 2

CV151

CV152

CV153

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AC15 B4 R21 W20 W4 N18
CV137

CV134

CV149

GND GND GND GND XVDD 1 1 1 1 1 1 1 1 VDD

OPT@
@

@
AC17 B7 R23 W22 W5 N20
@
CV150
GND GND GND GND XVDD VDD
AC18 GND GND C10 T13 GND GND W28 XVDD W7 N22 VDD
AC20 GND GND C13 T15 GND GND Y12 P14 VDD
AC22 C19 T17 Y14 2 2 2 2 2 2 2 2 P21
GND GND GND GND VDD

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
@
CV154

CV155

CV156

CV157

CV158

CV159

CV160
AE2 C22 T18 Y16 W8 R13

CV161
GND GND GND GND XVDD VDD
AE28 GND GND C25 T2 GND GND Y19 XVDD Y1 R15 VDD
AE30 GND GND C28 T20 GND GND Y21 XVDD Y2 R17 VDD
AE32 GND GND C7 T22 GND GND Y23 XVDD Y3 R18 VDD
AE33 GND GND D2 AG11 GND GND AH11 XVDD Y4 R20 VDD
AE5 D31 Y5 R22
330U_D2_2.5VY_R9M

GND GND XVDD 1 VDD


AE7 GND GND D33 XVDD Y6 T12 VDD
AH10 E10 Y7 + T16
GND GND XVDD VDD
AH13 E22 Y8 T19
GND GND XVDD
POSCAP VDD
@

AH16 GND GND E25 T23 VDD


2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AH19 GND GND E5 1 1 1 1 1 1 1 U13 VDD
CV162

AH2 GND GND E7 XVDD AA1 U15 VDD


AH22 GND GND F28 XVDD AA2 U18 VDD
AH24 GND GND F7 XVDD AA3 U20 VDD
AH28 G10 AA4 2 2 2 2 2 2 2 U22
GND GND XVDD VDD

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
@
CV164

CV165

CV166

CV167

CV168

CV169
AH29 G13 AA5 V13

CV170
GND GND XVDD VDD
AH30 GND GND G16 XVDD AA6 V15 VDD
C AH32 GND GND G19 XVDD AA7 V17 VDD C
AH33 GND GND G2 GND_OPT C16 XVDD AA8 V20 VDD
AH5 GND GND G22 GND_OPT W32 V22 VDD
AH7 GND GND G25 W12 VDD
AJ7 GND GND G28 Optional CMD GNDs (2) W16 VDD
AK10 GND GND G3 NC for 4-Lyr cards W19 VDD
AK7 GND GND G30 W23 VDD
AL12 GND GND G32 N17P-G1_FCBGA908 Y13 VDD
AL14 G33 Y15
@

GND GND VDD


AL15 GND GND G5 Y17 VDD
AL17 GND GND G7 N17P-G1_FCBGA908 Y18 VDD
AL18 K2 Y20
@

GND GND VDD


AL2 GND GND K28 Y22 VDD
AL20 GND GND K30
AL21 GND GND K32
AL23 GND GND K33 Change QV6/RV48/QV4/RV62 from REV@ to ns Hai Y520 SVT
AL24 GND GND K5
AL26 GND GND K7
AL28 GND GND M13
AL30 GND GND M15 NVVDD
AL32 GND GND M17 FBVDDQ
AL33 M18
GND GND
Change NVVDDS & +1.0VGS discharge circuit
1

AL5 GND GND M20 +5VALW


1

+5VALW
AM13
AM16
GND GND M22
N12
HLZ SIV 0725 RV61
RV36
470_0603_5%
GND GND
1

AM19 GND GND N14 470_0603_5%


1

AM22 GND GND N16 RV62 VDD_SENSE L4


2

NVVDDS +1.0VGS RV48 47K_0402_5%


2

LBSS138DW1T1G_SOT363-6
@

47K_0402_5%
@

GND_SENSE L5
2

D
N17P-G1_FCBGA908
2

QV4B

D QV6B 5
@

5 G N17P-G1_FCBGA908
2N7002KDWH_SOT363-6
LBSS138DW1T1G_SOT363-6
15_0805_1%

15_0805_1%

15_0805_1%

15_0805_1%

15_0805_1%

15_0805_1%

15_0805_1%

@
S
4
RV332 1

RV45 1

RV326 1

2 RV327 1

RV63 1

RV328 1

RV329 1

Add RV332 for NVVDDS discharge Hai Y520 SVT


6

D
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

S
4
6

QV4A

D QV6A 2
+5VALW [27,71] NVVDD_EN
2 G
B [27,69] FBVDDQ_PWR_EN G 2N7002KDWH_SOT363-6 B
S
2

1
@
1

S
1

RV60
47K_0402_5%
1

OPT@
D

D
2

2 2
G G
LBSS139WT1G_SC70-3

QV11 QV29 QV12


1

D
AO3402_SOT-23-3 AO3402_SOT-23-3
3

2
OPT@

2
[24,27,70] 1V0_MAIN_EN
G OPT@ OPT@ RV341
S 100_0402_1%
3

NVVDD_VSS_SENSE
[71] NVVDD_VSS_SENSE

trace width: 16mils


differential voltage sensing.
differential signal routing. VR Remote Sense - Tie to GPU sense points

NVVDD_VCC_SENSE
[71] NVVDD_VCC_SENSE
2

RV350
100_0402_1%
1

A NVVDD A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 N17P-G1_POWER,GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
EY515
Date: Tuesday, March 20, 2018 Sheet 29 of 74
5 4 3 2 1
5 4 3 2 1

Memory Partition A - Lower 64 bits(MF=0) UV4

MF 0 MF MF MF 0

FBA_D0 FBA_D[0..7] [26] BYTE0 DQ0-DQ7/EDC0/DBI0#/WCK0


A4
FBA_EDC0 C2 DQ24 DQ0 A2 FBA_D1
[26] FBA_EDC0 FBA_EDC1 EDC0 EDC3 DQ25 DQ1 FBA_D2
C13 B4
[26] FBA_EDC1 FBA_EDC2 EDC1 EDC2 DQ26 DQ2 FBA_D3
R13 B2
[26] FBA_EDC2 FBA_EDC3 EDC2 EDC1 DQ27 DQ3 FBA_D4
R2 E4
[26] FBA_EDC3 EDC3 EDC0 DQ28 DQ4 FBA_D5
E2
DQ29 DQ5 F4 FBA_D6
FBA_DBI0# D2 DQ30 DQ6 F2 FBA_D7
[26] FBA_DBI0# FBA_DBI1# DBI0# DBI3# DQ31 DQ7 FBA_D8 FBA_D[8..15] [26] BYTE1 DQ8-DQ15/EDC1/DBI1#/WCK0
D13 A11
[26] FBA_DBI1# FBA_DBI2# DBI1# DBI2# DQ16 DQ8 FBA_D9
P13 A13
[26] FBA_DBI2# FBA_DBI3# DBI2# DBI1# DQ17 DQ9 FBA_D10
D P2 B11 D
[26] FBA_DBI3# DBI3# DBI0# DQ18 DQ10 FBA_D11
B13
FBA_CLK0 J12 DQ19 DQ11 E11 FBA_D12
[26] FBA_CLK0 FBA_CLK0# CK DQ20 DQ12 FBA_D13
J11 E13
[26] FBA_CLK0# FBA_CKE_L CK# DQ21 DQ13 FBA_D14
J3 F11
[26] FBA_CKE_L CKE# DQ22 DQ14 FBA_D15
F13 BYTE2 DQ16-DQ23/EDC2/DBI2#/WCK1
DQ23 DQ15 FBA_D16 FBA_D[16..23] [26]
U11
FBA_MA2_BA0_L H11 DQ8 DQ16 U13 FBA_D17
[26] FBA_MA2_BA0_L FBA_MA5_BA1_L BA0/A2 BA2/A4 DQ9 DQ17 FBA_D18
K10 T11
[26] FBA_MA5_BA1_L FBA_MA4_BA2_L BA1/A5 BA3/A3 DQ10 DQ18 FBA_D19
[26] FBA_MA4_BA2_L K11 T13
FBA_MA3_BA3_L H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 FBA_D20
[26] FBA_MA3_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 FBA_D21
N13
DQ13 DQ21 M11 FBA_D22
FBA_MA7_MA8_L K4 DQ14 DQ22 M13 FBA_D23
[26] FBA_MA7_MA8_L FBA_MA1_MA9_L A8/A7 A10/A0 DQ15 DQ23 FBA_D24 FBA_D[24..31] [26] BYTE3 DQ24-DQ31/EDC3/DBI3#/WCK1
H5 U4
[26] FBA_MA1_MA9_L FBA_MA0_MA10_L A9/A1 A11/A6 DQ0 DQ24 FBA_D25
H4 U2
[26] FBA_MA0_MA10_L FBA_MA6_MA11_L A10/A0 A8/A7 DQ1 DQ25 FBA_D26
K5 T4
[26] FBA_MA6_MA11_L FBA_MA12_RFU_L A11/A6 A9/A1 DQ2 DQ26 FBA_D27
J5 T2
[26] FBA_MA12_RFU_L A12/RFU/NC DQ3 DQ27 FBA_D28
N4
A5 DQ4 DQ28 N2 FBA_D29
U5 VPP/NC1 DQ5 DQ29 M4 FBA_D30
VPP/NC2 DQ6 DQ30 M2 FBA_D31
DQ7 DQ31
RV127 2 1 1K_0402_1% OPT@ J1 FBVDDQ
RV129 2 1 1K_0402_1% OPT@ J10 MF
RV131 2 1 121_0402_1% OPT@ J13 SEN B1
Cost down list:
ZQ VDDQ1
VDDQ2
D1
F1
2A Peak 3A 22U 2Pcs
Follow DG FBA_ABI#_L VDDQ3
J4 M1
[26] FBA_ABI#_L FBA_RAS#_L ABI# VDDQ4
G3 P1
FBA_CLK0 [26] FBA_RAS#_L FBA_CS#_L RAS# CAS# VDDQ5
1 2 G12 T1
[26] FBA_CS#_L FBA_CAS#_L CS# WE# VDDQ6
RV133 L3 G2 FBVDDQ UV4 SIDE
[26] FBA_CAS#_L FBA_WE#_L CAS# RAS# VDDQ7
40.2_0402_1% L12 L2
[26] FBA_WE#_L WE# CS# VDDQ8
1

OPT@ B3
RV134 VDDQ9 D3
VDDQ10
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
80.6_0402_1% F3 2 2 2 2 2 2 2 2 2
VDDQ11
@

FBA_WCK0_N

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
D5 H3
C
[26]
[26]
FBA_WCK0_N
FBA_WCK0
FBA_WCK0 D4 WCK01# WCK23# VDDQ12 K3 GDDR5 C
2

WCK01 WCK23 VDDQ13

OPT@
FBA_CLK0# 1 2 M3
VDDQ14 1 1 1 1 1 1 1 1 1 Mode H - Mirror Mode Mapping
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
RV135 FBA_WCK1_N P5 P3
[26] FBA_WCK1_N WCK23# WCK01# VDDQ15
CV188

CV308

CV309

CV310

CV311

CV312

CV313

CV314

CV315
40.2_0402_1% 1 FBA_WCK1 P4 T3
[26] FBA_WCK1 WCK23 WCK01 VDDQ16
0.01U_0402_25V7K

OPT@ E5
VDDQ17 N5
VDDQ18 DATA Bus
A10 E10
2 VREFD1 VDDQ19
U10
VREFD2 VDDQ20
N10 Address 0 3 3 3
OPT@

+FBA_VREFC0 J14 B12 AROUND DRAM CLOSE TO DRAM


VREFC VDDQ21
CV177

D12 FB _CMD0 CS#


VDDQ22 F12
VDDQ23 H12
VDDQ24 FB _CMD A3_BA3
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

FBA_RST#_L J2 K12 2 2 2 2 2 2 2
[26] FBA_RST#_L RESET# VDDQ25
1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
M12 FB _CMD A _BA0
VDDQ26 P12
VDDQ27 T12 FB _CMD3 A _BA
2

VDDQ28 1 1 1 1 1 1 1
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
@

@
CV316

CV317

CV318

CV319

CV320

G13
VDDQ29
CV321

CV322

CV323

CV324

CV325

CV326

CV327
H1 L13 FB _CMD A5_BA
K1 VSS1 VDDQ30 B14
B5 VSS2 VDDQ31 D14
VSS3 VDDQ32 FB _CMD5 W #
G5 F14
L5 VSS4 VDDQ33 M14
VSS5 VDDQ34 FB _CMD A7_A
T5 P14 AROUND DRAM CLOSE TO DRAM
B10 VSS6 VDDQ35 T14
VSS7 VDDQ36 FB _CMD7 A _A
D10
G10 VSS8
VSS9 FB _CMD ABI#
L10 A1
P10 VSS10 VSSQ1 C1
VSS11 VSSQ2 FB _CMD9 A _RFU
T10 E1
H14 VSS12 VSSQ3 N1
VSS13 VSSQ4 FB _CMD 0 A0_A 0
K14 R1
FBVDDQ VSS14 VSSQ5 U1 FBVDDQ
VSSQ6 FB _CMD A _A9
H2 UNDER DRAM
G1 VSSQ7 K2
VDD1 VSSQ8 FB _CMD RAS#
L1 A3
G4 VDD2 VSSQ9 C3
VDD3 VSSQ10 2 2 2 2 FB _CMD 3 RST#
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

L4 E3
C5 VDD4 VSSQ11 N3
B VDD5 VSSQ12 FB _CMD CK # B
R5 R3
VDD6 VSSQ13 1 1 1 1
OPT@

OPT@

OPT@
@

C10 U3 FB _CMD 5 CAS#


VDD7 VSSQ14
CV357

CV350

CV351

CV352

R10 C4
D11 VDD8 VSSQ15 R4
VDD9 VSSQ16 FB _CMD CS#
G11 F5
L11 VDD10 VSSQ17 M5
VDD11 VSSQ18 FB _CMD 7 A3_BA3
P11 F10
G14 VDD12 VSSQ19 M10
VDD13 VSSQ20 FB _CMD A _BA0
L14 C11 UNDER DRAM
VDD14 VSSQ21 R11
VSSQ22 FB _CMD 9 A _BA
A12
VSSQ23 C12
VSSQ24 2 2 2 2 FB _CMD 0 A5_BA
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

E12
VSSQ25 N12
VSSQ26 FB _CMD W #
R12
VSSQ27 1 1 1 1
OPT@

OPT@

OPT@

OPT@

170-BALL U12 FB _CMD A7_A


VSSQ28
CV358

CV354

CV355

CV356

H13
SGRAM GDDR5 VSSQ29 K13
VSSQ30 FB _CMD 3 A _A
A14
VSSQ31 C14
VSSQ32 FB _CMD ABI#
E14
VSSQ33 N14
FBVDDQ VSSQ34 FB _CMD 5 A _RFU
R14
VSSQ35 U14
VSSQ36 FB _CMD A0_A 0
X76@ FB _CMD 7 A _A9
1

RV136 H5GC2H24BFR-T2C_BGA170 FB _CMD RAS#


549_0402_1%
OPT@
16 mil FB _CMD 9 RST#
2

1 2 +FBA_VREFC0 FB _CMD30 CK #
+FBA_VREFC0 [31]
RV137
1

931_0402_1% RV138 1 FB _CMD3 CAS#


OPT@ 1.33K_0402_1% CV178
OPT@ 820P_0402_25V7
A OPT@ A
2
2

QV261
D
2
[27] MEM_VREF
G
S
3
PJA138K_SOT23-3
Security Classification LC Future Center Secret Data Title
OPT@
Issued Date 2015/02/26 Deciphered Date 2016/02/26 N17P-G1_VRAM A Lower
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
EY515
Date: Tuesday, March 20, 2018 Sheet 30 of 74
5 4 3 2 1
5 4 3 2 1

Memory Partition A- Upper 64 bits(MF=0)


UV6

MF 0 MF MF MF 0

FBA_D39 FBA_D[32..39] [26] BYTE4 DQ32-DQ39/EDC4/DBI4#/WCK2


A4
FBA_EDC4 C2 DQ24 DQ0 A2 FBA_D38
[26] FBA_EDC4 FBA_EDC5 EDC0 EDC3 DQ25 DQ1 FBA_D36
C13 B4
[26] FBA_EDC5 FBA_EDC6 EDC1 EDC2 DQ26 DQ2 FBA_D37
R13 B2
[26] FBA_EDC6 FBA_EDC7 EDC2 EDC1 DQ27 DQ3 FBA_D34
R2 E4
[26] FBA_EDC7 EDC3 EDC0 DQ28 DQ4 FBA_D33
E2
DQ29 DQ5 F4 FBA_D32
FBA_DBI4# D2 DQ30 DQ6 F2 FBA_D35
[26] FBA_DBI4# FBA_DBI5# DBI0# DBI3# DQ31 DQ7 FBA_D40 FBA_D[40..47] [26] BYTE5 DQ40-DQ47/EDC5/DBI5#/WCK2
D13 A11
[26] FBA_DBI5# FBA_DBI6# DBI1# DBI2# DQ16 DQ8 FBA_D41
P13 A13
[26] FBA_DBI6# FBA_DBI7# DBI2# DBI1# DQ17 DQ9 FBA_D42
D P2 B11 D
[26] FBA_DBI7# DBI3# DBI0# DQ18 DQ10 FBA_D43
B13
FBA_CLK1 J12 DQ19 DQ11 E11 FBA_D44
[26] FBA_CLK1 FBA_CLK1# CK DQ20 DQ12 FBA_D45
J11 E13
[26] FBA_CLK1# FBA_CKE_H CK# DQ21 DQ13 FBA_D46
J3 F11
[26] FBA_CKE_H CKE# DQ22 DQ14 FBA_D47
F13 BYTE6 DQ48-DQ55/EDC6/DBI6#/WCK3
DQ23 DQ15 FBA_D48 FBA_D[48..55] [26]
U11
FBA_MA2_BA0_H H11 DQ8 DQ16 U13 FBA_D49
[26] FBA_MA2_BA0_H FBA_MA5_BA1_H BA0/A2 BA2/A4 DQ9 DQ17 FBA_D50
K10 T11
[26] FBA_MA5_BA1_H FBA_MA4_BA2_H K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBA_D51
[26] FBA_MA4_BA2_H FBA_MA3_BA3_H H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 FBA_D52
[26] FBA_MA3_BA3_H BA3/A3 BA1/A5 DQ12 DQ20 N13 FBA_D53
DQ13 DQ21 M11 FBA_D54
FBA_MA7_MA8_H DQ14 DQ22 FBA_D55
BYTE7 DQ56-DQ63/EDC7/DBI7#/WCK3
[26] FBA_MA7_MA8_H K4 M13
FBA_MA1_MA9_H A8/A7 A10/A0 DQ15 DQ23 FBA_D56 FBA_D[56..63] [26]
[26] FBA_MA1_MA9_H H5 U4
FBA_MA0_MA10_H H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBA_D57
[26] FBA_MA0_MA10_H FBA_MA6_MA11_H A10/A0 A8/A7 DQ1 DQ25 FBA_D58
K5 T4
[26] FBA_MA6_MA11_H FBA_MA12_RFU_H A11/A6 A9/A1 DQ2 DQ26 FBA_D59
J5 T2
[26] FBA_MA12_RFU_H A12/RFU/NC DQ3 DQ27 FBA_D60
Follow DG N4
A5 DQ4 DQ28 N2 FBA_D61
U5 VPP/NC1 DQ5 DQ29 M4 FBA_D62
FBA_CLK1 1 2 VPP/NC2 DQ6 DQ30 M2 FBA_D63
RV148 DQ7 DQ31
40.2_0402_1% RV143 2 1 1K_0402_1% OPT@ J1 FBVDDQ
OPT@ RV145 2 1 1K_0402_1% OPT@ J10 MF
SEN
1

RV147 2 1 121_0402_1% OPT@ J13 B1


RV149 ZQ VDDQ1 D1
80.6_0402_1% VDDQ2 F1
VDDQ3
@

FBA_ABI#_H J4 M1
[26] FBA_ABI#_H FBA_RAS#_H ABI# VDDQ4
G3 P1
[26] FBA_RAS#_H
2

FBA_CLK1# 1 2 FBA_CS#_H G12 RAS# CAS# VDDQ5 T1


[26] FBA_CS#_H FBA_CAS#_H CS# WE# VDDQ6
RV150 L3 G2
[26] FBA_CAS#_H FBA_WE#_H CAS# RAS# VDDQ7 Cost down list: GDDR5
0.01U_0402_25V7K

40.2_0402_1% L12 L2
OPT@
1 [26] FBA_WE#_H WE# CS# VDDQ8
VDDQ9
B3
D3
2A Peak 3A 22U 2Pcs
Mode H - Mirror Mode Mapping
VDDQ10 F3
2 VDDQ11
OPT@

FBA_WCK2_N D5 H3
[26] FBA_WCK2_N WCK01# WCK23# VDDQ12
CV196

C
FBA_WCK2 D4 K3 DATA Bus C
[26] FBA_WCK2 WCK01 WCK23 VDDQ13 M3 FBVDDQ UV6 SIDE
FBA_WCK3_N VDDQ14
[26] FBA_WCK3_N
P5
WCK23# WCK01# VDDQ15
P3 Address 0 3 3 3
FBA_WCK3 P4 T3
[26] FBA_WCK3 WCK23 WCK01 VDDQ16 E5 FB _CMD0 CS#
VDDQ17
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
N5 2 2 2 2 2 2 2 2 2
VDDQ18

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
A10 E10 FB _CMD A3_BA3
U10 VREFD1 VDDQ19 N10
+FBA_VREFC0 J14 VREFD2 VDDQ20 B12
VREFC VDDQ21 1 1 1 1 1 1 1 1 1
FB _CMD A _BA0
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
D12
VDDQ22
CV329

CV330

CV331

CV332

CV334

CV333

CV335

CV336

CV337
F12 FB _CMD3 A _BA
VDDQ23 H12
FBA_RST#_H J2 VDDQ24 K12
[26] FBA_RST#_H RESET# VDDQ25 FB _CMD A5_BA
M12
VDDQ26 P12
VDDQ27 FB _CMD5 W #
T12 AROUND DRAM CLOSE TO DRAM
VDDQ28 G13
VDDQ29 FB _CMD A7_A
H1 L13
K1 VSS1 VDDQ30 B14
VSS2 VDDQ31 FB _CMD7 A _A
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

B5 D14 2 2 2 2 2 2 2
VSS3 VDDQ32
1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
G5 F14 FB _CMD ABI#
L5 VSS4 VDDQ33 M14
T5 VSS5 VDDQ34 P14 FB _CMD9 A _RFU
2

VSS6 VDDQ35 1 1 1 1 1 1 1
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
@

@
CV338

CV339

CV340

CV341

CV342

B10 T14
16 mil VSS7 VDDQ36
CV343

CV345

CV344

CV346

CV347

CV348

CV328

D10 FB _CMD 0 A0_A 0


G10 VSS8
L10 VSS9 A1
VSS10 VSSQ1 FB _CMD A _A9
+FBA_VREFC0 P10 C1
[30] +FBA_VREFC0 VSS11 VSSQ2
T10 E1 FB _CMD RAS#
H14 VSS12 VSSQ3 N1
1 VSS13 VSSQ4 AROUND DRAM CLOSE TO DRAM
K14 R1 FB _CMD 3 RST#
CV197 FBVDDQ VSS14 VSSQ5 U1
820P_0402_25V7 VSSQ6 H2
2 OPT@ VSSQ7 FB _CMD CK #
G1 K2
L1 VDD1 VSSQ8 A3
VDD2 VSSQ9 FB _CMD 5 CAS#
G4 C3
L4 VDD3 VSSQ10 E3
VDD4 VSSQ11 FB _CMD CS#
B C5 N3 FBVDDQ B
R5 VDD5 VSSQ12 R3
VDD6 VSSQ13 UNDER DRAM FB _CMD 7 A3_BA3
C10 U3
R10 VDD7 VSSQ14 C4
VDD8 VSSQ15 FB _CMD A _BA0
D11 R4 2 2 2 2
VDD9 VSSQ16
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

G11 F5 FB _CMD 9 A _BA


L11 VDD10 VSSQ17 M5
P11 VDD11 VSSQ18 F10
VDD12 VSSQ19 1 1 1 1
FB _CMD 0 A5_BA
OPT@

OPT@

OPT@

G14 M10
VDD13 VSSQ20
CV365

CV360

CV359

CV361

L14 C11 FB _CMD W #


VDD14 VSSQ21 R11
VSSQ22 A12
VSSQ23 FB _CMD A7_A
C12
VSSQ24 E12
VSSQ25 FB _CMD 3 A _A
N12
VSSQ26 R12
VSSQ27 UNDER DRAM FB _CMD ABI#
170-BALL U12
VSSQ28 H13
VSSQ29 FB _CMD 5 A _RFU
SGRAM GDDR5 K13 2 2 2 2
VSSQ30
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

A14 FB _CMD A0_A 0


VSSQ31 C14
VSSQ32 E14
VSSQ33 1 1 1 1
FB _CMD 7 A _A9
OPT@

OPT@

OPT@
@

N14
VSSQ34
CV366

CV362

CV363

CV364

R14 FB _CMD RAS#


VSSQ35 U14
VSSQ36
FB _CMD 9 RST#
X76@
FB _CMD30 CK #
H5GC2H24BFR-T2C_BGA170
FB _CMD3 CAS#

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 N17P-G1_VRAM A Upper
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
EY515
Date: Tuesday, March 20, 2018 Sheet 31 of 74
5 4 3 2 1
5 4 3 2 1

Memory Partition B - Lower 32 bits(MF=0)


UV8

MF 0 MF MF MF 0
FBC_D[0..7] [26] BYTE0 DQ0-DQ7/EDC0/DBI0#/WCK0
A4 FBC_D0
FBC_EDC0 C2 DQ24 DQ0 A2 FBC_D1
[26] FBC_EDC0 FBC_EDC1 EDC0 EDC3 DQ25 DQ1 FBC_D2
C13 B4
[26] FBC_EDC1 FBC_EDC2 EDC1 EDC2 DQ26 DQ2 FBC_D3
R13 B2
[26] FBC_EDC2 FBC_EDC3 EDC2 EDC1 DQ27 DQ3 FBC_D4
R2 E4
[26] FBC_EDC3 EDC3 EDC0 DQ28 DQ4 FBC_D5
E2
DQ29 DQ5 F4 FBC_D6
FBC_DBI0# D2 DQ30 DQ6 F2 FBC_D7
[26] FBC_DBI0# DBI0# DBI3# DQ31 DQ7 FBC_D[8..15] [26] BYTE1 DQ8-DQ15/EDC1/DBI1#/WCK0
D
FBC_DBI1# D13 A11 FBC_D8 D
[26] FBC_DBI1# FBC_DBI2# DBI1# DBI2# DQ16 DQ8 FBC_D9
P13 A13
[26] FBC_DBI2# FBC_DBI3# DBI2# DBI1# DQ17 DQ9 FBC_D10
P2 B11
[26] FBC_DBI3# DBI3# DBI0# DQ18 DQ10 FBC_D11
B13
FBC_CLK0 J12 DQ19 DQ11 E11 FBC_D12
[26] FBC_CLK0 FBC_CLK0# CK DQ20 DQ12 FBC_D13
J11 E13
[26] FBC_CLK0# FBC_CKE_L CK# DQ21 DQ13 FBC_D14
J3 F11
[26] FBC_CKE_L CKE# DQ22 DQ14 FBC_D15
F13 BYTE2 DQ16-DQ23/EDC2/DBI2#/WCK1
DQ23 DQ15 FBC_D16 FBC_D[16..23] [26]
U11
FBC_MA2_BA0_L H11 DQ8 DQ16 U13 FBC_D17
[26] FBC_MA2_BA0_L FBC_MA5_BA1_L BA0/A2 BA2/A4 DQ9 DQ17 FBC_D18
K10 T11
[26] FBC_MA5_BA1_L FBC_MA4_BA2_L BA1/A5 BA3/A3 DQ10 DQ18 FBC_D19
K11 T13
[26] FBC_MA4_BA2_L FBC_MA3_BA3_L BA2/A4 BA0/A2 DQ11 DQ19 FBC_D20
[26] FBC_MA3_BA3_L H10 N11
BA3/A3 BA1/A5 DQ12 DQ20 N13 FBC_D21
DQ13 DQ21 M11 FBC_D22
FBC_MA7_MA8_L K4 DQ14 DQ22 M13 FBC_D23
[26] FBC_MA7_MA8_L A8/A7 A10/A0 DQ15 DQ23 FBC_D[24..31] [26] BYTE3 DQ24-DQ31/EDC3/DBI3#/WCK1
Follow DG FBC_MA1_MA9_L H5 U4 FBC_D24
[26] FBC_MA1_MA9_L FBC_MA0_MA10_L H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBC_D25
[26] FBC_MA0_MA10_L FBC_MA6_MA11_L A10/A0 A8/A7 DQ1 DQ25 FBC_D26
K5 T4
FBC_CLK0 [26] FBC_MA6_MA11_L FBC_MA12_RFU_L A11/A6 A9/A1 DQ2 DQ26 FBC_D27
1 2 [26] FBC_MA12_RFU_L J5 T2
RV163 A12/RFU/NC DQ3 DQ27 N4 FBC_D28
40.2_0402_1% A5 DQ4 DQ28 N2 FBC_D29
OPT@ U5 VPP/NC1 DQ5 DQ29 M4 FBC_D30
VPP/NC2 DQ6 DQ30
1

M2 FBC_D31
RV164 DQ7 DQ31
80.6_0402_1% RV157 2 1 1K_0402_1% OPT@ J1 FBVDDQ
MF
@

RV159 2 1 1K_0402_1% OPT@ J10


RV161 2 1 121_0402_1% OPT@ J13 SEN B1
2

ZQ VDDQ1 D1
VDDQ2 F1
FBC_CLK0# 1 2 FBC_ABI#_L J4 VDDQ3 M1
[26] FBC_ABI#_L FBC_RAS#_L ABI# VDDQ4
RV165 G3 P1
40.2_0402_1% [26] FBC_RAS#_L FBC_CS#_L G12 RAS# CAS# VDDQ5 T1
1 [26] FBC_CS#_L CS# WE# VDDQ6 Cost down list:
0.01U_0402_25V7K

OPT@ FBC_CAS#_L L3 G2
[26]
[26]
FBC_CAS#_L
FBC_WE#_L
FBC_WE#_L L12 CAS#
WE#
RAS#
CS#
VDDQ7
VDDQ8
L2
B3
2A Peak 3A 22U 2Pcs
2 VDDQ9 D3
VDDQ10
OPT@

F3
C VDDQ11 GDDR5 C
CV215

FBC_WCK0_N D5 H3
[26] FBC_WCK0_N FBC_WCK0 WCK01# WCK23# VDDQ12
D4 K3 FBVDDQ UV8 SIDE
[26] FBC_WCK0 WCK01 WCK23 VDDQ13
VDDQ14
M3 Mode H - Mirror Mode Mapping
FBC_WCK1_N P5 P3
[26] FBC_WCK1_N FBC_WCK1 WCK23# WCK01# VDDQ15
P4 T3
[26] FBC_WCK1 WCK23 WCK01 VDDQ16
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
E5 2 2 2 2 2 2 2 2 2 DATA Bus
VDDQ17

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
N5
A10 VDDQ18 E10
VREFD1 VDDQ19
Address 0 3 3 3
U10 N10
VREFD2 VDDQ20 1 1 1 1 1 1 1 1 1
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
+FBC_VREFC0 J14 B12 FB _CMD0 CS#
VREFC VDDQ21
CV368

CV369

CV371

CV370

CV373

CV372

CV374

CV375

CV376
D12
VDDQ22 F12
VDDQ23 FB _CMD A3_BA3
H12
FBC_RST#_L J2 VDDQ24 K12
[26] FBC_RST#_L RESET# VDDQ25 FB _CMD A _BA0
M12
VDDQ26 P12
VDDQ27 AROUND DRAM CLOSE TO DRAM FB _CMD3 A _BA
T12
VDDQ28 G13
VDDQ29 FB _CMD A5_BA
H1 L13
VSS1 VDDQ30
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

K1 B14 2 2 2 2 2 2 2 FB _CMD5 W #
VSS2 VDDQ31
1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
B5 D14
G5 VSS3 VDDQ32 F14
VSS4 VDDQ33 FB _CMD A7_A
L5 M14
2

VSS5 VDDQ34 1 1 1 1 1 1 1
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
@

@
CV377

CV378

CV379

CV380

CV381

T5 P14 FB _CMD7 A _A
VSS6 VDDQ35
CV382

CV384

CV383

CV385

CV386

CV387

B10 T14 CV367


D10 VSS7 VDDQ36
VSS8 FB _CMD ABI#
G10
L10 VSS9 A1
VSS10 VSSQ1 FB _CMD9 A _RFU
P10 C1
T10 VSS11 VSSQ2 E1
VSS12 VSSQ3 AROUND DRAM CLOSE TO DRAM FB _CMD 0 A0_A 0
H14 N1
K14 VSS13 VSSQ4 R1
VSS14 VSSQ5 FB _CMD A _A9
U1
FBVDDQ VSSQ6 H2
VSSQ7 FB _CMD RAS#
G1 K2
L1 VDD1 VSSQ8 A3
VDD2 VSSQ9 FB _CMD 3 RST#
B G4 C3 B
L4 VDD3 VSSQ10 E3 FBVDDQ
VDD4 VSSQ11 FB _CMD CK #
C5 N3 UNDER DRAM
R5 VDD5 VSSQ12 R3
VDD6 VSSQ13 FB _CMD 5 CAS#
C10 U3
R10 VDD7 VSSQ14 C4
VDD8 VSSQ15 2 2 2 2 FB _CMD CS#
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

D11 R4
G11 VDD9 VSSQ16 F5
VDD10 VSSQ17 FB _CMD 7 A3_BA3
L11 M5
VDD11 VSSQ18 1 1 1 1
OPT@

OPT@

OPT@

OPT@

P11 F10 FB _CMD A _BA0


VDD12 VSSQ19
CV394

CV388

CV389

CV390

G14 M10
L14 VDD13 VSSQ20 C11
VDD14 VSSQ21 FB _CMD 9 A _BA
R11
VSSQ22 A12
VSSQ23 FB _CMD 0 A5_BA
C12
VSSQ24 E12
VSSQ25 FB _CMD W #
N12 UNDER DRAM
VSSQ26 R12
VSSQ27 FB _CMD A7_A
170-BALL U12
VSSQ28 H13
VSSQ29 2 2 2 2 FB _CMD 3 A _A
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

SGRAM GDDR5 K13


VSSQ30 A14
VSSQ31 FB _CMD ABI#
C14
VSSQ32 1 1 1 1
OPT@

OPT@

OPT@

FBVDDQ
@

E14 FB _CMD 5 A _RFU


VSSQ33
CV395

CV391

CV393

CV392

N14
VSSQ34 R14
VSSQ35 FB _CMD A0_A 0
U14
VSSQ36
1

FB _CMD 7 A _A9
RV166 X76@
549_0402_1%
16 mil FB _CMD RAS#
OPT@ H5GC2H24BFR-T2C_BGA170
FB _CMD 9 RST#
2

1 2 +FBC_VREFC0
+FBC_VREFC0 [33]
RV167 FB _CMD30 CK #
1

931_0402_1% 1
OPT@ RV168 CV216 FB _CMD3 CAS#
1.33K_0402_1% 820P_0402_25V7
A OPT@ OPT@ A
2
2

QV281
D
2
[27] MEM_VREF
G
S
3 Security Classification LC Future Center Secret Data Title
PJA138K_SOT23-3
Issued Date 2015/02/26 Deciphered Date 2016/02/26 N17P-G1_VRAM B Lower
OPT@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 32 of 74
5 4 3 2 1
5 4 3 2 1

Memory Partition B - Upper 32 bits(MF=0)


UV10

MF 0 MF MF MF 0
FBC_D[32..39] [26] BYTE4 DQ32-DQ39/EDC4/DBI4#/WCK2
A4 FBC_D32
FBC_EDC4 C2 DQ24 DQ0 A2 FBC_D33
[26] FBC_EDC4 FBC_EDC5 EDC0 EDC3 DQ25 DQ1 FBC_D34
C13 B4
[26] FBC_EDC5 FBC_EDC6 EDC1 EDC2 DQ26 DQ2 FBC_D35
R13 B2
[26] FBC_EDC6 FBC_EDC7 EDC2 EDC1 DQ27 DQ3 FBC_D36
R2 E4
[26] FBC_EDC7 EDC3 EDC0 DQ28 DQ4 FBC_D37
E2
DQ29 DQ5 F4 FBC_D38
FBC_DBI4# D2 DQ30 DQ6 F2 FBC_D39
[26] FBC_DBI4# DBI0# DBI3# DQ31 DQ7 FBC_D[40..47] [26] BYTE5 DQ40-DQ47/EDC5/DBI5#/WCK2
FBC_DBI5# D13 A11 FBC_D40
[26] FBC_DBI5# FBC_DBI6# DBI1# DBI2# DQ16 DQ8 FBC_D41
D P13 A13 D
[26] FBC_DBI6# FBC_DBI7# DBI2# DBI1# DQ17 DQ9 FBC_D42
P2 B11
[26] FBC_DBI7# DBI3# DBI0# DQ18 DQ10 FBC_D43
B13
FBC_CLK1 J12 DQ19 DQ11 E11 FBC_D44
[26] FBC_CLK1 FBC_CLK1# CK DQ20 DQ12 FBC_D45
J11 E13
[26] FBC_CLK1# FBC_CKE_H CK# DQ21 DQ13 FBC_D46
J3 F11
[26] FBC_CKE_H CKE# DQ22 DQ14 FBC_D47
F13 BYTE6 DQ48-DQ55/EDC6/DBI6#/WCK3
DQ23 DQ15 FBC_D48 FBC_D[48..55] [26]
U11
FBC_MA2_BA0_H H11 DQ8 DQ16 U13 FBC_D49
[26] FBC_MA2_BA0_H FBC_MA5_BA1_H K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBC_D50
[26] FBC_MA5_BA1_H FBC_MA4_BA2_H K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBC_D51
Follow DG [26] FBC_MA4_BA2_H BA2/A4 BA0/A2 DQ11 DQ19
FBC_MA3_BA3_H H10 N11 FBC_D52
[26] FBC_MA3_BA3_H BA3/A3 BA1/A5 DQ12 DQ20 N13 FBC_D53
FBC_CLK1 1 2 DQ13 DQ21 M11 FBC_D54
DQ14 DQ22 BYTE7 DQ56-DQ63/EDC7/DBI7#/WCK3
RV178 FBC_MA7_MA8_H K4 M13 FBC_D55
[26] FBC_MA7_MA8_H FBC_MA1_MA9_H A8/A7 A10/A0 DQ15 DQ23 FBC_D56 FBC_D[56..63] [26]
40.2_0402_1% H5 U4
OPT@ [26] FBC_MA1_MA9_H FBC_MA0_MA10_H H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBC_D57
[26] FBC_MA0_MA10_H A10/A0 A8/A7 DQ1 DQ25
1

FBC_MA6_MA11_H K5 T4 FBC_D58
RV179 [26] FBC_MA6_MA11_H FBC_MA12_RFU_H J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBC_D59
80.6_0402_1% [26] FBC_MA12_RFU_H A12/RFU/NC DQ3 DQ27 N4 FBC_D60
DQ4 DQ28
@

A5 N2 FBC_D61
U5 VPP/NC1 DQ5 DQ29 M4 FBC_D62
2

VPP/NC2 DQ6 DQ30 M2 FBC_D63


DQ7 DQ31
FBC_CLK1# 1 2 RV172 2 1 1K_0402_1% OPT@ J1 FBVDDQ
RV180 RV174 2 1 1K_0402_1% OPT@ J10 MF
SEN
0.01U_0402_25V7K

40.2_0402_1% 1 RV175 2 1 121_0402_1% OPT@ J13 B1


OPT@ ZQ VDDQ1 D1
VDDQ2 F1
FBC_ABI#_H J4 VDDQ3 M1
2 [26] FBC_ABI#_H ABI# VDDQ4 Cost down list:
OPT@

FBC_RAS#_H G3 P1
[26] FBC_RAS#_H RAS# CAS# VDDQ5
2A Peak 3A 22U 2Pcs
CV234

FBC_CS#_H G12 T1
[26] FBC_CS#_H FBC_CAS#_H CS# WE# VDDQ6
L3 G2
[26] FBC_CAS#_H FBC_WE#_H CAS# RAS# VDDQ7
L12 L2
[26] FBC_WE#_H WE# CS# VDDQ8 B3
VDDQ9
VDDQ10
D3 GDDR5
F3 FBVDDQ UV10 SIDE
C [26] FBC_WCK2_N
FBC_WCK2_N D5
WCK01# WCK23#
VDDQ11
VDDQ12
H3 Mode H - Mirror Mode Mapping C
FBC_WCK2 D4 K3
[26] FBC_WCK2 WCK01 WCK23 VDDQ13 M3
VDDQ14
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
FBC_WCK3_N P5 P3 2 2 2 2 2 2 2 2 2 DATA Bus
[26] FBC_WCK3_N WCK23# WCK01# VDDQ15

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
FBC_WCK3 P4 T3
[26] FBC_WCK3 WCK23 WCK01 VDDQ16 E5 Address 0 3 3 3
VDDQ17 N5
VDDQ18 1 1 1 1 1 1 1 1 1
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
A10 E10 FB _CMD0 CS#
VREFD1 VDDQ19
CV397

CV398

CV400

CV399

CV402

CV401

CV404

CV403

CV405
U10 N10
+FBC_VREFC0 J14 VREFD2 VDDQ20 B12
VREFC VDDQ21 FB _CMD A3_BA3
D12
VDDQ22 F12
VDDQ23 FB _CMD A _BA0
H12
FBC_RST#_H J2 VDDQ24 K12
[26] FBC_RST#_H RESET# VDDQ25 AROUND DRAM Cost down CLOSE TO DRAM FB _CMD3 A _BA
M12
VDDQ26 P12
VDDQ27 FB _CMD A5_BA
T12
VDDQ28
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

G13 2 2 2 2 2 2 2 FB _CMD5 W #
VDDQ29
1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
H1 L13
K1 VSS1 VDDQ30 B14
VSS2 VDDQ31 FB _CMD A7_A
B5 D14
2

VSS3 VDDQ32 1 1 1 1 1 1 1
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
@

@
CV406

CV408

CV407

CV409

CV410

G5 F14 FB _CMD7 A _A
VSS4 VDDQ33
CV412

CV413

CV411

CV414

CV415

CV416

CV396
L5 M14
T5 VSS5 VDDQ34 P14
VSS6 VDDQ35 FB _CMD ABI#
B10 T14
16 mil D10 VSS7 VDDQ36
FB _CMD9 A _RFU
G10 VSS8
L10 VSS9 A1
VSS10 VSSQ1 AROUND DRAM CLOSE TO DRAM FB _CMD 0 A0_A 0
+FBC_VREFC0 P10 C1
[32] +FBC_VREFC0 VSS11 VSSQ2
T10 E1 FB _CMD A _A9
H14 VSS12 VSSQ3 N1
1 VSS13 VSSQ4
CV235 K14 R1 FB _CMD RAS#
820P_0402_25V7 FBVDDQ VSS14 VSSQ5 U1
OPT@ VSSQ6 H2
2 VSSQ7 FB _CMD 3 RST#
G1 K2
L1 VDD1 VSSQ8 A3 FBVDDQ
VDD2 VSSQ9 FB _CMD CK #
G4 C3 UNDER DRAM
L4 VDD3 VSSQ10 E3
B VDD4 VSSQ11 FB _CMD 5 CAS# B
C5 N3
R5 VDD5 VSSQ12 R3
VDD6 VSSQ13 2 2 2 2 FB _CMD CS#
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

C10 U3
R10 VDD7 VSSQ14 C4
VDD8 VSSQ15 FB _CMD 7 A3_BA3
D11 R4
VDD9 VSSQ16 1 1 1 1
OPT@

OPT@

OPT@
@

G11 F5 FB _CMD A _BA0


VDD10 VSSQ17
CV423

CV417

CV419

CV418

L11 M5
P11 VDD11 VSSQ18 F10
VDD12 VSSQ19 FB _CMD 9 A _BA
G14 M10
L14 VDD13 VSSQ20 C11
VDD14 VSSQ21 FB _CMD 0 A5_BA
R11
VSSQ22 A12
VSSQ23 FB _CMD W #
C12 UNDER DRAM
VSSQ24 E12
VSSQ25 FB _CMD A7_A
N12
VSSQ26 R12
VSSQ27 2 2 2 2 FB _CMD 3 A _A
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

170-BALL U12
VSSQ28 H13
VSSQ29 FB _CMD ABI#
SGRAM GDDR5 K13
VSSQ30 1 1 1 1
OPT@

OPT@

OPT@

OPT@

A14 FB _CMD 5 A _RFU


VSSQ31
CV424

CV421

CV422

CV420

C14
VSSQ32 E14
VSSQ33 FB _CMD A0_A 0
N14
VSSQ34 R14
VSSQ35 FB _CMD 7 A _A9
U14
VSSQ36
FB _CMD RAS#
X76@
FB _CMD 9 RST#
H5GC2H24BFR-T2C_BGA170
FB _CMD30 CK #
FB _CMD3 CAS#

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 N17P-G1_VRAM B Upper
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 33 of 74
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 N17P-G1_VRAM B Upper
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 34 of 74
5 4 3 2 1
5 4 3 2 1

LCD POWER CIRCUIT V20B+ +LED_VDD

2A 80 mil 2A 80 mil
R17 1 2 0_0805_5%

+LCD_VDD +3VS 1 1
F3 C14 C15
1 2 4.7U_0805_25V6K 0.1U_0402_25V6
CD@ EMC@
U9 2 2
W=60mils W=60mils 3A_32V_ERBRD3R00X
R22 1 2 0_0603_5% 1 5 @
OUT IN
4.7U_0603_6.3V6K

0.1u_0201_10V6K

2 EMI Request
GND
1 1
D 2 1 3 4 D
OCB EN
C7

C8

R275
0_0402_5%
2 2 SY6288C20AAC_SOT23-5
@

JEDP1
2A 80 mil
+LED_VDD 1
R6 1 2 0_0402_5% 2 1
[14] PCH_EDP_ENVDD 2
3
4 3
4
1
100K_0402_5%

.1U_0402_10V6-K

1 1A Inrush 2A 5
6 5
+LCD_VDD 6
R7

C23

+5VS R10533 2 1 0_0402_5% 7


DISPOFF# 8 7
2@ INVT_PWM 9 8
2

R10531 1 @ 2 0_0402_5% PCH_EDP_HPD 10 9


+3VALW 10
Logo_led_PWM 11
R10532 1 @ 2 0_0402_5% Logo_led_Power 12 11
+5VALW 12
13
CPU_EDP_TX0+ C19 1 2 0.1u_0201_10V6K EDP_TX0+ 14 13
[8] CPU_EDP_TX0+ CPU_EDP_TX0- EDP_TX0- 14
C16 1 2 0.1u_0201_10V6K 15
Logo_led_PWM [8] CPU_EDP_TX0- 15
16
CPU_EDP_AUX# C21 1 2 0.1u_0201_10V6K EDP_AUX# 17 16
[8] CPU_EDP_AUX# CPU_EDP_AUX EDP_AUX 17
C20 1 2 0.1u_0201_10V6K 18
[8] CPU_EDP_AUX 18
19
CPU_EDP_TX1- C18 1 2 0.1u_0201_10V6K EDP_TX1- 20 19
[8] CPU_EDP_TX1- 20
1

D CPU_EDP_TX1+ C17 1 2 0.1u_0201_10V6K EDP_TX1+ 21


[8] CPU_EDP_TX1+ 21
2

PWR_LED2# 2 22
[49] PWR_LED2# G +3VS_DMIC 22
Q5819 R10534 +3VS 0.5A R10402 1 2 0_0603_5% 23
2N7002KW_SOT323-3 R10403 2 1 0_0402_5% DMIC_DATA 24 23
0_0402_5% [40] DMIC_DATA_R 24
S DMIC_CLK_R 25
[40] DMIC_CLK_R
3

C
@ R261 1 2 0_0603_5% +3VS_CMOS 26 25 C
+3VS 0.5A
1

27 26
R10400 1 @ 2 0_0402_5% USB20_N6_R 28 27
[19] USB20_N6 USB20_P6_R 28
R10401 1 @ 2 0_0402_5% 29 31
[19] USB20_P6 29 GND1
R12 1 2 0_0402_5% DISPOFF# 30 32
[49] BKOFF# 30 GND2
@ 2 HIGHS_FC5AF301-3181H
C10155 ME@
0.047U_0402_16V7K
CD@
1

PCH_EDP_PWM R19 1 2 0_0402_5% INVT_PWM PCH_EDP_HPD


[14] PCH_EDP_PWM PCH_EDP_HPD [15]
JEDP3
@
2A 80 mil
1

+LED_VDD 1 37
R20 R57 2 1 GND1 38
100K_0402_5% 100K_0402_5% 3 2 GND2
4 3
5 4
1A Inrush 2A
2

6 5
+LCD_VDD 6
7
DISPOFF# 8 7
INVT_PWM 9 8
PCH_EDP_HPD 10 9
Logo_led_PWM 11 10
Logo_led_Power 12 11
13 12
EDP_TX0+ 14 13
B B
EDP_TX0- 15 14
16 15
EDP_AUX# 17 16
EDP_AUX 18 17
19 18
EDP_TX1- 20 19
EDP_TX1+ 21 20
22 21
+3VS_DMIC 23 22
EMI request DMIC_DATA 24 23
DMIC_CLK_R 25 24
DMIC_CLK_R DMIC_DATA DISPOFF# INVT_PWM +3VS_CMOS 26 25
27 26
USB20_N6_R 28 27
28
33P_0402_50V8J

1 1 1 1 USB20_P6_R 29
CH19 29
EMC@

C11

C12 C13 30
10P_0402_50V8J 470P_0402_50V7K 470P_0402_50V7K CPU_EDP_TX3+ C10203 1 2 0.1u_0201_10V6K EDP_TX3+ 31 30
[8] CPU_EDP_TX3+ CPU_EDP_TX3- C10202 1 31
EMC_NS@ EMC_NS@ EMC_NS@ 2 0.1u_0201_10V6K EDP_TX3- 32
2 2 2 2 [8] CPU_EDP_TX3- 32
33
CPU_EDP_TX2- C10204 1 2 0.1u_0201_10V6K EDP_TX2- 34 33
[8] CPU_EDP_TX2- CPU_EDP_TX2+ C10205 1 34
2 0.1u_0201_10V6K EDP_TX2+ 35
[8] CPU_EDP_TX2+ 35
36
36

HIGHS_FC5AF361-1151H
ME@

For EMI
L12
USB20_N6 1 2 USB20_N6_R
A 1 2 A

USB20_P6 4 3 USB20_P6_R
4 3
EXC24CH900U_4P
EMC@

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 eDP/ CMOS/Touch screen
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 35 of 74
5 4 3 2 1
5 4 3 2 1

+1.8VS_AON

1
RRE59
10K_0402_5%
R10498 2 @ 1 0_0402_5%

2
EMC@
HDMI1_TX0- CRE261 2 0.1u_0201_10V6K HDMI1_TX0-_C L89 1 2 HDMI1_TX0-_R IFPE_HPD
[25] HDMI1_TX0- 1 2 [27] IFPE_HPD

HDMI D0 HDMI1_TX0+
[25] HDMI1_TX0+ CRE251 2 0.1u_0201_10V6K HDMI1_TX0+_C 4 3 HDMI1_TX0+_R QRE3
4 3 MMBT3904WH_SOT323-3

1
EXC24CH500U_4P C
D R10505 2 @ 1 0_0402_5% 2 RRE57 1 2 100K_0402_5% RRE58 1 2 0_0402_5% HDMI1_HPD_CON D
B

3
1 1

1
CRE9 CRE10
RRE56 220P_0402_50V7K 220P_0402_50V7K
100K_0402_5%
R10499 2 @ 1 0_0402_5% 2 2

2
EMC@
HDMI1_TX1- CRE281 2 0.1u_0201_10V6K HDMI1_TX1-_C L91 1 2 HDMI1_TX1-_R
[25] HDMI1_TX1- 1 2
HDMI D1 HDMI1_TX1+
[25] HDMI1_TX1+ CRE271 2 0.1u_0201_10V6K HDMI1_TX1+_C 4 3 HDMI1_TX1+_R +3VS
4 3
EXC24CH500U_4P
R10504 2 @ 1 0_0402_5%

R10500 2 @ 1 0_0402_5%

EMC@ HPD

1
HDMI1_TX2- CRE301 2 0.1u_0201_10V6K HDMI1_TX2-_C L90 1 2 HDMI1_TX2-_R
[25] HDMI1_TX2- 1 2
HDMI D2 RRE61

2
1M_0402_5%

G
HDMI1_TX2+ CRE291 2 0.1u_0201_10V6K HDMI1_TX2+_C 4 3 HDMI1_TX2+_R
[25] HDMI1_TX2+ 4 3

1
EXC24CH500U_4P HDMI_HPD HDMI1_HPD_CON
[15] HDMI_HPD
R10503 2 @ 1 0_0402_5%

D
R10501 2 @ 1 0_0402_5% QRE5
PJA138K_SOT23-3
EMC@
HDMI1_TXC- CRE321 2 0.1u_0201_10V6K HDMI1_CLK-_C L88 1 2 HDMI1_CLK-_R
[25] HDMI1_TXC- 1 2

HDMI CLK HDMI1_TXC+ CRE311 2 0.1u_0201_10V6K HDMI1_CLK+_C 4 3 HDMI1_CLK+_R


[25] HDMI1_TXC+ 4 3
EXC24CH500U_4P
R10502 2 @ 1 0_0402_5%
C C

HDMI1_TX0+_C R10337 1 2 499_0402_1% HDMI1_TX0+_B R10426 1 2 0_0402_5%

HDMI1_TX0-_C R10338 1 2 499_0402_1% HDMI1_TX0-_B R10427 1 2 0_0402_5%

HDMI1_TX1+_C R10339 1 2 499_0402_1% HDMI1_TX1+_B R10428 1 2 0_0402_5%

HDMI1_TX1-_C R10340 1 2 499_0402_1% HDMI1_TX1-_B R10429 1 2 0_0402_5%

HDMI1_TX2+_C R10341 1 2 499_0402_1% HDMI1_TX2+_B R10430 1 2 0_0402_5%

HDMI1_TX2-_C R10342 1 2 499_0402_1% HDMI1_TX2-_B R10431 1 2 0_0402_5%

HDMI1_CLK+_C R10343 1 2 499_0402_1% HDMI1_CLK+_B R10432 1 2 0_0402_5%

HDMI1_CLK-_C R10344 1 2 499_0402_1% HDMI1_CLK-_B R10433 1 2 0_0402_5%


1

D Q13
+3VS 2
G 2N7002KW_SOT323-3

S
3

+5VS +5VS_HDMI1_F +5VS_HDMI1


R42 1 @ 2 QRE4
LP2301ALT1G_SOT23-3
100K_0402_5% F2
1 3 1 2
D

B 1.1A_8V_1206L110THYR B
G
2

D46
HDMI1_HPD_CON 1 1 10 9 HDMI1_HPD_CON

HDMI1_DAT_CON HDMI1_DAT_CON [40,43,53] SUSP


2 2 9 8 1
CRE11
HDMI1_CLK_CON 4 4 7 7 HDMI1_CLK_CON
1/16W_3.3K_5%_0402

1/16W_3.3K_5%_0402

.1U_0402_10V6-K

+5VS_HDMI1 5 5 6 6 +5VS_HDMI1 2
1

3 3
RRE15

RRE16
2

AZ1045-04F_DFN2510P10E-10-9 JHDMI1
EMC_NS@ HDMI1_HPD_CON 19
18 Hot_Plug_Detect
17 +5V_Power
HDMI1_DAT_CON 16 DDC/CEC_GND
D47 HDMI1_CLK_CON 15 SDA
HDMI1_TX0-_R 1 1 HDMI1_TX0-_R SCL
10 9 14
Utility
13 20
HDMI1_TX0+_R 2 2 HDMI1_TX0+_R HDMI1_CLK-_R HDMI1_CLK-_CON CEC GND1
9 8 R10326 1 2 1/16W_6.8_5%_0402 12
11 TDMS_Clock- 21
HDMI1_CLK-_R 4 4 HDMI1_CLK-_R HDMI1_CLK+_R HDMI1_CLK+_CON TDMS_Clock_Shield GND2
7 7 R10325 1 2 1/16W_6.8_5%_0402 10
HDMI1_TX0-_R R10320 1 2 1/16W_6.8_5%_0402 HDMI1_TX0-_CON 9 TDMS_Clock+ 22
HDMI1_CLK+_R 5 5 6 6 HDMI1_CLK+_R AUX +1.8VS_AON +1.8VS_AON
HDMI1_TX0+_R R10319 1 2 1/16W_6.8_5%_0402 HDMI1_TX0+_CON
8
7
TDMS_Data0-
TDMS_Data0_Shield
GND3
23
3 3 HDMI1_TX1-_R R10322 1 2 1/16W_6.8_5%_0402 HDMI1_TX1-_CON 6 TDMS_Data0+ GND4
5 TDMS_Data1-
TDMS_Data1_Shield
1

HDMI1_TX1+_R R10321 1 2 1/16W_6.8_5%_0402 HDMI1_TX1+_CON 4


RRE55 RRE54 HDMI1_TX2-_R R10324 1 2 1/16W_6.8_5%_0402 HDMI1_TX2-_CON 3 TDMS_Data1+
1.8K_0402_5% 1.8K_0402_5% 2 TDMS_Data2-
TDMS_Data2_Shield
2

AZ1045-04F_DFN2510P10E-10-9 For EMC HDMI1_TX2+_R R10323 1 2 1/16W_6.8_5%_0402 HDMI1_TX2+_CON 1


G

TDMS_Data2+
EMC_NS@
2

ALLTO_C128AU-K1939-L
ME@
HDMI1_DAT_CON 6 1
S

HDMI1_DAT [25]
D

A D48 QRE2A A
5

HDMI1_TX1-_R 1 1 10 9 HDMI1_TX1-_R DMN5L06DWK-7 2N SOT363-6


G

HDMI1_TX1+_R 2 2 9 8 HDMI1_TX1+_R

HDMI1_TX2-_R 4 4 7 7 HDMI1_TX2-_R HDMI1_CLK_CON 3 4


S

HDMI1_CLK [25]
D

HDMI1_TX2+_R 5 5 6 6 HDMI1_TX2+_R QRE2B


DMN5L06DWK-7 2N SOT363-6
3 3

For EMC Security Classification LC Future Center Secret Data Title

AZ1045-04F_DFN2510P10E-10-9 Issued Date 2015/02/26 Deciphered Date 2016/02/26 HDMI_CONN


EMC_NS@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
EY515 1.0

Date: Tuesday, March 20, 2018 Sheet 36 of 74


5 4 3 2 1
5 4 3 2 1

+3VS_USB3_RE

+3VALW +3VS_USB3_RE
1 1
CW32 CW33
.1U_0402_10V6-K .1U_0402_10V6-K
D 2 2 D
@ @
+3VS RW31 1 2 0_0402_5%
USB3.0 Repeator
U124
R282 1 @ 2 0_0402_5% 1
13 VDD1
VDD2

USB_EQ1_A 15 4 USB_EQ1_B
USB_DE0_A 16 A_EQ1_SDA_CTL B_EQ1_I2C_ADDR1 3 USB_DE0_B
USB_EQ0_A 17 A_DE0_SCL_CTL B_DE0_I2C_ADDR0 2 USB_EQ0_B
USB_DE1_A 18 A_EQ0_NC B_EQ0_NC 6 USB_DE1_B
A_DE1_NC B_DE1_NC
CW30 1 2 0.1U_0201_6.3V6-K USB3_TX2+_REIN 19 12 USB30_TX_P2_B
[15] TYPE-C_USB3_TX_P2 USB3_TX2-_REIN A_INp A_OUTp USB30_TX_N2_B USB30_TX_P2_B [38]
CW31 1 2 0.1U_0201_6.3V6-K 20 11
[15] TYPE-C_USB3_TX_N2 A_INn A_OUTn USB30_TX_N2_B [38]

USB30_RX_P2_B 9 22 USB3_RX2+_REOUT CW37 1 2 0.1U_0201_6.3V6-K


[38] USB30_RX_P2_B USB30_RX_N2_B B_INp B_OUTp USB3_RX2-_REOUT TYPE-C_USB3_RX_P2 [15]
8 23 CW36 1 2 0.1U_0201_6.3V6-K TYPE-C_USB3_RX_N2 [15]
[38] USB30_RX_N2_B B_INn B_OUTn

TP4303 1 5
REXT 7 PD# 10
TEST 14 REXT GND1 21
@
24 TEST GND2 25
I2C_EN GPAD
1

RW30 PS8713BTQFN24GTR2A_TQFN24_4X4
3.9K_0402_1%

Base on test result fine turn the resistor value


2

C +3VS_USB3_RE C
LFPS swing adjust
3 3V tolerant Internally ulled down at ~ 50KΩ
T ST
TEST RW27 1 2 4.7K_0201_5% L: ormal LFPS swing default
H:Turn down LFPS swing

+3VS_USB3_RE
qualizer control and rogram for channel A +3VS_USB3_RE qualizer control and rogram for channel B
3 3V tolerant Internally ulled down at ~ 50K 3 3V tolerant Internally ulled down at ~ 50K
[A_ Q A_ Q0] [B_ Q B_ Q0]
USB_EQ1_A RW19 1 @ 2 4.7K_0201_5% LL: rogram Q for channel loss u to 9 5dB default USB_EQ1_B RW23 1 @ 2 4.7K_0201_5% LL: rogram Q for channel loss u to 9 5dB default
LH: rogram Q for channel loss u to 3dB LH: rogram Q for channel loss u to 3dB
USB_EQ0_A RW20 1 @ 2 4.7K_0201_5% HL: rogram Q for channel loss u to 5dB USB_EQ0_B RW24 1 2 4.7K_0201_5% HL: rogram Q for channel loss u to 5dB
HH: rogram Q for channel loss u to 7 5dB HH: rogram Q for channel loss u to 7 5dB
+3VS_USB3_RE +3VS_USB3_RE
Programmable out ut de-em hasis level setting for channel A Programmable out ut de-em hasis level setting for channel B
3 3V tolerant Internally ulled down at ~ 50K 3 3V tolerant Internally ulled down at ~ 50K
USB_DE0_A RW21 1 @ 2 4.7K_0201_5% [A_D A_D 0] USB_DE0_B RW25 1 2 4.7K_0201_5% [B_D B_D 0]
LL: 3 5dB de-em hasis default LL: 3 5dB de-em hasis default
USB_DE1_A RW22 1 @ 2 4.7K_0201_5% LH: o de-em hasis USB_DE1_B RW26 1 2 4.7K_0201_5% LH: o de-em hasis
HL: 7dB de-em hasis HL: 7dB de-em hasis
HH: 5dB de-em hasis HH: 5dB de-em hasis

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 DDI Redriver PS8330
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 37 of 74
5 4 3 2 1
4 3 2 1

500mA 500mA
+5VALW VCONN_IN

@
R105 1 2 0_0603_5%

100mA 100mA
1 3
D

Q8 +5V_IN_RTS5455 +5VALW +5V_IN_RTS5455


LP2301ALT1G_SOT23-3 1
G
2

R2078
47K_0402_5%
R103 1 2 0_0603_5%
2

TYPEC_GPIO9

10U_0603_6.3V6M
D Low 2 D

HiZ 1

C10144
C4205
0.1U_0402_10V7K
1
2

VCONN_IN +LDO_3V3
500mA

10U_0805_10V6K

.1U_0402_10V6-K
1 2
C102

C101
2 1
1 2
C4206 C10120
4.7U_0402_6.3V6M 0.1U_0402_10V7K
2 1

+VBUS_P0 USBC_CC1_CONN USBC_CC2_CONN

10

25

26
U4
1 1
VCON_IN

5V_IN

LDO_3V3
C4212 C4214
220P_0402_50V7K 220P_0402_50V7K
1

2 2
R4208 Zdiff 90ohm o via
200K_0402_1%
[37] USB30_TX_N2_B
C4230 1 2 0.22U_0201_6.3V6-K USB3P2_TXN_C 41
SSTX_1P/2N
PD Controller SBU2/MGPIO7
4 USBC_DPAUX2_CONN
USBC_DPAUX2_CONN [39]
C4207 1 2 0.22U_0201_6.3V6-K USB3P2_TXP_C 42 3 USBC_DPAUX1_CONN
[37] USB30_TX_P2_B USBC_DPAUX1_CONN [39]
2

SSTX_1N/2P SBU1/MGPIO6
10Gbps MUX System Side

Type-C Port side


VMON C10183 1 2 0.22U_0201_6.3V6-K USB3P2_RXN_C 39 8 VBUS_DSCHG
[37] USB30_RX_N2_B USB3P2_RXP_C SSRX_1P/2N C_DM/BB_DM VBUS_DSCHG [39]
C10182 1 2 0.22U_0201_6.3V6-K 40 7 1
[37] USB30_RX_P2_B SSRX_1N/2P C_DP/BB_DP TP4305
1

Zdiff=90ohm 11 USBC_CC2_CONN@
TYPE-C_DP_RE_TXP3 CC2 USBC_CC1_CONN USBC_CC2_CONN [39]
R4209 C10125 1 2 0.1u_0201_10V6K 38 9
[25] GPU_SNK0_DP3P TYPE-C_DP_RE_TXN3 DP3_1N/2P CC1 USBC_CC1_CONN [39]
10K_0402_1% C10127 1 2 0.1u_0201_10V6K 37
[25] GPU_SNK0_DP3N TYPE-C_DP_RE_TXP2 DP3_1P/2N TYPEC_RXP2
C10128 1 2 0.1u_0201_10V6K 46 18
[25] GPU_SNK0_DP2P TYPE-C_DP_RE_TXN2 DP2_1N/2P C_RX2_1N/2P TYPEC_RXN2 TYPEC_RXP2 [39]
C10126 1 2 0.1u_0201_10V6K 45 19
[25] GPU_SNK0_DP2N TYPEC_RXN2 [39]
2

C10121 1 2 0.1u_0201_10V6K TYPE-C_DP_RE_TXP1 44 DP2_1P/2N C_RX2_1P/2N 14 TYPEC_TXP2 C4220 1 2 0.1u_0201_10V6K TYPEC_C_TXP2


C [25] GPU_SNK0_DP1P TYPE-C_DP_RE_TXN1 DP1_1N/2P C_TX2_1N/2P TYPEC_TXN2 TYPEC_C_TXN2 TYPEC_C_TXP2 [39] C
C10124 1 2 0.1u_0201_10V6K 43 15 C4221 1 2 0.1u_0201_10V6K
[25] GPU_SNK0_DP1N TYPE-C_DP_RE_TXP0 DP1_1P/2N C_TX2_1P/2N TYPEC_RXP1 TYPEC_C_TXN2 [39]
C10122 1 2 0.1u_0201_10V6K 36 16
[25] GPU_SNK0_DP0P TYPE-C_DP_RE_TXN0 DP0_1N/2P C_RX1_1N/2P TYPEC_RXN1 TYPEC_RXP1 [39]
C10123 1 2 0.1u_0201_10V6K 35 17
[25] GPU_SNK0_DP0N DP0_1P/2N C_RX1_1P/2N TYPEC_TXP1 TYPEC_C_TXP1 TYPEC_RXN1 [39]
12 C4215 1 2 0.1u_0201_10V6K
C_TX1_1N/2P TYPEC_TXN1 TYPEC_C_TXN1 TYPEC_C_TXP1 [39]
13 C4218 1 2 0.1u_0201_10V6K
C_TX1_1P/2N TYPEC_C_TXN1 [39]

100K_0402_5% 2 1 R39 Zdiff=100ohm


+3VS

[25] GPU_SNK0_AUX_DN C10157 1 2 0.1U_0402_10V7K TYPE-C_DP_RE_AUXN 2


C10156 1 2 0.1U_0402_10V7K TYPE-C_DP_RE_AUXP 1 AUX_N/MGPIO5
[25] GPU_SNK0_AUX_DP AUX_P/MGPIO4
100K_0402_5% 2 1 R38 1 MGPIO3 6 33 RTS5455_SM_INT
H_DM/DCI_CLK/MGPIO3 SM_INT/GPIO4 RTS5455_SM_INT [14,49]
TP4301 5
H_DP/DCI_DATA/MGPIO2 31 RTS5455_SM_SDA
@ SM_SDA/GPIO6
VBUS_EN 27 32 RTS5455_SM_CK
+LDO_3V3 +5VALW [39] VBUS_EN
TYPEC_GPIO9 28
I2C_EN/GPIO10
RTS5455 SM_SCL/GPIO5

I2C_INT/GPIO9
TYPE_C_OCP# R10271 1 2 0_0402_5% 29 24
[39] TYPE_C_OCP# I2C_SDA/GPIO8 REXT
2

1 30 20
R4210 @ R4212 TP4304 I2C_SCL/GPIO7 DB_CFG
0_0402_5% 590K_0402_1% @ 34 TYPE-C_DP_RE_HPD
@ HPD/GPIO3

1
1

R4245 R4244
LOC_PWR_MON LOC_PWR_MON 23 0_0402_5% 6.2K_0402_1%
LOC_PWR_MON
22 47

2
IMON E_PAD
1

VMON 21
R4211 R4213 VMON
10K_0402_1% 10K_0402_1%
@
2

RTS5455-GR_QFN46_6P5X4P5

+LDO_3V3

B R4348 2 1 4.7K_0402_5% RTS5455_SM_INT B

R4349 2 1 4.7K_0402_5% RTS5455_SM_SDA

R4350 2 1 4.7K_0402_5% RTS5455_SM_CK

+3VALW
+1.8VS_AON
2

R2080
HPD
1

0_0402_5% Change EC side SMbus power level HLZ SIV 0811 RRE67
10K_0402_5%
1

@
2

IFPA_HPD
[27] IFPA_HPD
2

Address 0xAC
G

to NV GPU QRE8
MMBT3904WH_SOT323-3
1

C
R139 1 2 0_0402_5% 1 6 RTS5455_SM_CK 2 RRE65 1 2 100K_0402_5% TYPE-C_DP_RE_HPD
S

[49] EC_SMB_CK0
D

B
5
G

Q10A
1

2N7002KDWH_SOT363-6 RRE63
EC 100K_0402_5%
R140 1 2 0_0402_5% 4 3 RTS5455_SM_SDA
S

[49] EC_SMB_DA0
D

Q10B 2N7002KDWH
2N7002KDWH_SOT363-6 Vth= min 1V, max 2.5V
ESD 2KV

TYPE-C_DP_HPD RRE70 1 2 0_0402_5% TYPE-C_DP_RE_HPD


[15] TYPE-C_DP_HPD
A A

to PCH

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 USB TYPE-C Controller
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 38 of 74
4 3 2 1
4 3 2 1

R63 1 @ 2 0_0402_5%
TYPE-C_USB20_P4_C
TYPE-C_USB20_N4_C

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2
L6
TYPE-C_PCH_USB20_N4 4 3 TYPE-C_USB20_N4_C
[19] TYPE-C_PCH_USB20_N4 4 3

2
D18 D4313

2
TYPE-C_PCH_USB20_P4 1 2 TYPE-C_USB20_P4_C
[19] TYPE-C_PCH_USB20_P4 1 2

GND4
GND3
GND2
GND1
EXC24CH900U_4P
EMC@
JUSBC1

1
R81 1 @ 2 0_0402_5% EMC@ EMC@

GND8
GND7
GND6
GND5

1
B12 A1
D GND4 GND1 D
TYPE-C_RX1_P_C B11 A2 TYPE-C_TX1_P_C
SSRXp1 SSTXp1
TYPE-C_RX1_N_C B10 A3 TYPE-C_TX1_N_C
R84 1 @ 2 0_0402_5% SSRXn1 SSTXn1
B9 A4
+VBUS_P0 Vbus4 Vbus1 +VBUS_P0
L1 USBC_DPAUX2_CONN B8 A5 USBC_CC1_CONN
TYPEC_C_TXN1 TYPE-C_TX1_N_C [38] USBC_DPAUX2_CONN SBU2 CC1 USBC_CC1_CONN [38]
1 2
[38] TYPEC_C_TXN1 1 2 TYPE-C_USB20_N4_C TYPE-C_USB20_P4_C
B7 A6
Dn2 Dp1
TYPEC_C_TXP1 4 3 TYPE-C_TX1_P_C TYPE-C_USB20_P4_C B6 A7 TYPE-C_USB20_N4_C
[38] TYPEC_C_TXP1 4 3 Dp2 Dn1
EXC24CH900U_4P USBC_CC2_CONN B5 A8 USBC_DPAUX1_CONN
[38] USBC_CC2_CONN CC2 SBU1 USBC_DPAUX1_CONN [38]
EMC@
B4 A9
+VBUS_P0 Vbus3 Vbus2 +VBUS_P0
R86 1 @ 2 0_0402_5% TYPE-C_TX2_N_C B3 A10 TYPE-C_RX2_N_C
SSTXn2 SSRXn2
TYPE-C_TX2_P_C B2 A11 TYPE-C_RX2_P_C
SSTXp2 SSRXp2
B1 A12
GND10

@ GND3 GND2
GND9

R89 1 2 0_0402_5% D21


USBC_DPAUX1_CONN9 10 1 1 USBC_DPAUX1_CONN

USBC_DPAUX2_CONN8 9 2 2 USBC_DPAUX2_CONN
GND5
GND6

L22 ATOB_066-12A1-3211
TYPEC_C_TXN2 1 2 TYPE-C_TX2_N_C USBC_CC1_CONN 7 7 4 4 USBC_CC1_CONN
[38] TYPEC_C_TXN2 1 2
ME@ USBC_CC2_CONN 6 5 USBC_CC2_CONN
6 5
TYPEC_C_TXP2 4 3 TYPE-C_TX2_P_C
[38] TYPEC_C_TXP2 4 3 3
3
EXC24CH900U_4P
EMC@
AZ1045-04F_DFN2510P10E-10-9
R91 1 @ 2 0_0402_5% EMC_NS@
C C

R92 1 @ 2 0_0402_5% D19


TYPE-C_TX2_N_C 9 10 1 1 TYPE-C_TX2_N_C

TYPE-C_TX2_P_C 8 9 2 2 TYPE-C_TX2_P_C
EMC@
EXC24CH900U_4P TYPE-C_TX1_N_C 7 7 4 4 TYPE-C_TX1_N_C
TYPEC_RXP1 4 3 TYPE-C_RX1_P C10227 1 2 0.33U_10V_K_X5R_0402 TYPE-C_RX1_P_C
[38] TYPEC_RXP1 4 3 TYPE-C_TX1_P_C 6 5 TYPE-C_TX1_P_C
6 5

TYPEC_RXN1 1 2 TYPE-C_RX1_N C10228 1 2 0.33U_10V_K_X5R_0402 TYPE-C_RX1_N_C 3 3


[38] TYPEC_RXN1 1 2
L13
220K_0201_5%

AZ1045-04F_DFN2510P10E-10-9
1

220K_0201_5%

EMC_NS@
@
1
R10522

R98 1 2 0_0402_5%
R10523

D20
TYPE-C_RX2_N 9 10 1 1 TYPE-C_RX2_N
2

TYPE-C_RX2_P 8 9 2 2 TYPE-C_RX2_P

R100 1 @ 2 0_0402_5% TYPE-C_RX1_N 7 7 4 TYPE-C_RX1_N


4
TYPE-C_RX1_P 6 6 5 5 TYPE-C_RX1_P
EMC@ 3
3
EXC24CH900U_4P
TYPEC_RXP2 4 3 TYPE-C_RX2_P C10229 1 2 0.33U_10V_K_X5R_0402 TYPE-C_RX2_P_C
[38] TYPEC_RXP2 4 3
AZ1045-04F_DFN2510P10E-10-9
TYPEC_RXN2 1 2 TYPE-C_RX2_N C10230 1 2 0.33U_10V_K_X5R_0402 TYPE-C_RX2_N_C EMC_NS@
B [38] TYPEC_RXN2 1 2 B
L21
220K_0201_5%

@
1

220K_0201_5%

R101 1 2 0_0402_5%
1
R10525

R10524
2

+VBUS_P0

+VBUS_P0
1

R171 +5VALW
High enable discharge @ 470_0603_5% 3A
Low disable discharge +5VALW +VBUS_P0
AZ5725-01F.R7GR_DFN1006P2X2
2

.47U_0402_6.3V6K

.47U_0402_6.3V6K

.47U_0402_6.3V6K

.47U_0402_6.3V6K

U27
1

10U_0603_25V6-M

R4203 R3147 1 1 1 1 1
1

C922

C921

C920

C53

0_0402_5% Q19 D 5 1 10K_0402_5%


1

IN OUT
EMC_NS@

D4316

C924

VBUS_DSCHG 1 2 2
[38] VBUS_DSCHG @ G @ 2
1

GND 2 2 2 2 2
2

S 2N7002KW_SOT323-3 VBUS_EN 4 3 TYPE_C_OCP#


[38] VBUS_EN TYPE_C_OCP# [38]
3

EN FLAG
2

R4204
@ 100K_0402_5% Active high R10272 G517G1TO1U_TSOT-23-5
2

100K_0402_5%
1

A A
+5VALW
22U_0603_6.3V6-M

22U_0603_6.3V6-M

C1333 1 1 1
150U_B2_6.3VM_R35M

@ 2 2
2 Title
CV462

CV463

Security Classification LC Future Center Secret Data


Issued Date 2015/02/26 Deciphered Date 2016/02/26 USB TYPE-C Port
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 39 of 74
4 3 2 1
5 4 3 2 1

PCH_HDA_BIT_CLK DMIC_CLK DMIC_DATA_R


+3V_AUD
22P_0201_25V8

EMC_NS@

2200P_0402_50V7K
33P_0402_50V8J

1 1 1
EMC@
CA16

CA104

CA105

EMC@
R4
2 2 2 100K_0201_1%
2

HPOUT-JD_R

+5VS
U121
4.7U_0402_6.3V6M

+5VS
10 20 +5VA RA684 1 2 0_0402_5% 1200mA
DC_DET AVDD1 33 +1.8V_SYSA 1 2 0_0603_5% +5V_AUD
AVDD2 1 19mA
CA325

2.2U_0402_6.3V6M

[16] PCH_HDA_BIT_CLK 5 +1.8VS 1 1 RA20


BCLK
0.1u_0201_10V6K
CA317

10U_0603_6.3V6M
CA381

10U_0402_6.3V6M
29 131mA 1 1 1 1 1
CPVDD
4.7U_0402_6.3V6M

CA383

CA327
0.1u_0201_10V6K

CA320
0.1u_0201_10V6K
PCH_HDA_SYNC

CA384
9
[16] PCH_HDA_SYNC SYNC ALC3240-CG +3VALW 2 HP/MIC Jack
CA326

D 1 +3V_AUD D
RA3 1 2 22_0402_5% PCH_HDA_SDIN0_R 7 DVDD 2 2
[16] PCH_HDA_SDIN0 PCH_HDA_SDOUT SDATA-IN 2 2 2@ 2 2
[16] PCH_HDA_SDOUT 4 8 AUDIO_AGND
SDATA-OUT DVDD-IO
1 1mA
CA318
0.1u_0201_10V6K

34 +5V_AUD JHP1
DMIC_DATA_R 2 PVDD1 39
[35] DMIC_DATA_R DMIC_CLK GPIO0/DMIC-DATA12 PVDD2
RA687 1 2 0_0201_5% 3
[35] DMIC_CLK_R GPIO1/DMIC-CLK 2
1U_0201_6.3V6-K

AUDIO_AGND A_RING2_CONN 3
SPKR_MUTE# 40 22 R2 1 2 C10138 2 1 EMC_NS@ A_HP_OUTL_R 1 G/M
PDB VREF 1 L
HPOUT_JDR10110 1 2 200K_0201_1% HPOUT-JD_R 12 EMC_NS@ 0_0402_5% 1000P_0402_50V7K
CA382

HPOUT_JD HP/LINE1-JD(JD1) 23 MIC2-VREFO +3VS AUDIO_AGND 5


BEEP 11 MIC2-VREFO 5
A_RING2_CONN 13 PCBEEP 24 LINE1-VREFO-L 2 1 2 0_0603_5% +3V_AUD HPOUT_JD 6
A_SLEEVE 14 MIC2-L(PORT-F-L)/RING2 LINE1-VREFO-L RA18 6
MIC2-R(PORT-F-R)/SLEEVE R10270 1 2 C10139 2 1 EMC_NS@ A_HP_OUTR_R 2
1 1 5mA R

1U_0201_6.3V6-K

CA330
0.1u_0201_10V6K
27 AUDIO_AGND EMC_NS@ 0_0402_5% 1000P_0402_50V7K

CA380
4.7U_0402_6.3V6M 2 1 CA324 15 CPVEE 28 A_SLEEVE 4
AUDIO_AGND MIC2-CAP CBN M/G
LINE1-R 17 30 1
LINE1-R(PORT-C-R) CBP 2 2
1U_0201_6.3V6-K

LINE1-L 18 7
CA388

LINE1-L(PORT-C-L) 1 AUDIO_AGND MS
4.7U_0402_6.3V6M

1U_0201_6.3V6-K

21 AUDIO_AGND
CA385

LDO1-CAP 1
CA328

32 1 1 SINGA_2SJ3095-140111F
LDO2-CAP 2
4.7U_0402_6.3V6M

1000P_0402_50V7K

1000P_0402_50V7K
SPK_L+ 35 6
SPK_L+ SPK-OUT-LP LDO3-CAP 2 ME@

EMC@
4.7U_0402_6.3V6M

SPK_L-

C10140

C10141
36 1
SPK_L- SPK-OUT-LN 2

EMC@
CA329

SPK_R- 37 16 RA5 1 2 0_0402_5%


SPK_R- SPK_R+ 38 SPK-OUT-RN VD33STB 2 2
SPK-OUT-RP 1
SPK_R+
CA331

@ AUDIO_AGND
19 2
RA688 1 2 4.7K_0201_5% A_HP_OUTL_R RA57 1 2 1/20W_60.4_1%_0201HPOUT-L 25 AVSS1 31
LINE1-VREFO-L RA689 1 2 4.7K_0201_5% A_HP_OUTR_R RA59 1 2 1/20W_60.4_1%_0201HPOUT-R26 HPOUT-L(PORT-I-L) AVSS2 2 AUDIO_AGND
HPOUT-R(PORT-I-R) 41 +3VL AUDIO_AGND
GND(Thermal_Pad) +1.8VS
LINE1-L 1U_0402_10V6K 2 1 C225
ALC3240-CG_MQFN40_5X5
AUDIO_AGND RA26 1 2 +1.8V_SYSA
LINE1-R 1U_0402_10V6K 2 1 C10137
0_0402_5% 26mA F R SD Close to Connector
A_RING2_CONN

A_SLEEVE

A_HP_OUTL_R

A_HP_OUTR_R
CA378
470P_0201_25V7K

CA392
470P_0201_25V7K
MIC2-VREFO
1 1 HPOUT_JD
1

RA683 RA685 AUDIO_AGND

AZ5425-01F.R7GR_DFN1006P2E2

AZ5425-01F.R7GR_DFN1006P2E2

AZ5425-01F.R7GR_DFN1006P2E2

AZ5425-01F.R7GR_DFN1006P2E2

AZ5425-01F.R7GR_DFN1006P2E2
C RA15 1 2 0_0201_5% SPKR_MUTE# 2.2K_0201_5% 2.2K_0201_5% 2 2 C
[49] EC_MUTE#

1
D25 D2 D26 D4 D27

56P 50V J NPO 0402


1

1
2

RA23 RA2 1 2 0_0402_5% VD33STB:Power for combo jack depop circuit at system shutdown mode.

EMC_NS@
10K_0201_5%
A_SLEEVE

C10143
@
RA8 1 2 0_0402_5% AVDD1:Analog power for mixers ,IO ports 2
2

2
A_RING2_CONN
RA12 1 @ 2 0_0402_5% EMC_NS@
DVDD-IO:Digital power for HDA link

2
RA13 1 @ 2 0_0402_5%
DVDD:Digital power for digital I/0 circuit
@ EMC_NS@ EMC_NS@ EMC_NS@ EMC@
AUDIO_AGND
AUDIO_AGND AVDD2:Analog power for DACS ,ADCS
PVDD1,PVDD2:Power supply for full-bridge left and right channel

JSPK1
SPK_R+ R10435 1 2 0_0402_5% SPK_R+_CONN 1
SPK_R- R10436 1 2 0_0402_5% SPK_R-_CONN 2 1 SPK_L+ 1 2 EMC_NS@ 1 2 EMC_NS@
SPK_L- R10437 1 2 0_0402_5% SPK_L-_CONN 3 2 RA194 15_0402_5% CA173 220P_0201_25V7-K
SPK_L+ R10438 1 2 0_0402_5% SPK_L+_CONN 4 3
5 4 SPK_L- 1 2 EMC_NS@ 1 2 EMC_NS@
6 G1 RA195 15_0402_5% CA174 220P_0201_25V7-K
AZ5725-01F.R7GR_DFN1006P2X2

AZ5725-01F.R7GR_DFN1006P2X2

G2
1

1
470P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K

470P_0402_50V7K

HIGHS_WS32040-S0471-HF SPK_R+ 1 2 EMC_NS@ 1 2 EMC_NS@


1 1 1 1 D4314 D39 ME@ RA196 15_0402_5% CA175 220P_0201_25V7-K
1

1
CA31

CA32

CA33

CA34

SPK_R- 1 2 EMC_NS@ 1 2 EMC_NS@


AZ5725-01F.R7GR_DFN1006P2X2

AZ5725-01F.R7GR_DFN1006P2X2

RA197 15_0402_5% CA176 220P_0201_25V7-K


1

2 2 2 2
Place Close To Codec
2

D40 D41
1

1
2

EMC_NS@ EMC_NS@
2

EMC@ EMC@ EMC@ EMC@


2

EMC_NS@ EMC_NS@

B B

+1.8VS
+1.8VALW

CA401
RA39
1 2 1 2

4.7K_0402_5% 0.1U_0402_10V7K

PC-BEEP LP2301ALT1G_SOT23-3
Q183
DA1
S

BEEP# 2 3 1
[49] BEEP# CA35
@ +3VS +3VS
1 RA10 1 2 0_0402_5% PC_BEEP_C 1 2 BEEP +3VS +3VS +VCCPRIM_1P05 +VCCPRIM_1P05
1 1
C8473
0.1u_0201_10V6K

C8475
0.1u_0201_10V6K
G
2

PCH_BEEP 3 @
[16] PCH_BEEP 0.1U_0402_10V7K
1

BAT54CW_SOT323-3 RA11 2 2
1 1 1 1
@ 10K_0402_5% 1 1
C8472
4.7U_0402_6.3V6M

@ SUSP 1 2 0_0402_5% 1 1 1 C10223 C10231 C10232 C10233


[36,43,53] SUSP
C8471
0.1u_0201_10V6K

C8470
0.1u_0201_10V6K

R10068 C10218 C10220 0.1U_0201_6.3V7-K 0.1U_0201_6.3V7-K 0.1U_0201_6.3V7-K 0.1U_0201_6.3V7-K


2

0.1U_0201_6.3V7-K 0.1U_0201_6.3V7-K 2 @ 2 2 2
1

2 @ 2 @
1 2 2 2
C8474
0.1u_0201_10V6K

R10070
@ 470K_0402_5%
CA402
RA38
1 2 1 2 2 +3VS +3VS
2

+3VALW
4.7K_0402_5% 0.1U_0402_10V7K

+3VS

Follow think update 1


C10234
0.1U_0201_6.3V7-K
2

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 Codec_CX20752
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 40 of 74
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/6/23 Deciphered Date 2015/6/23 Audio Jack
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 41 of 74

5 4 3 2 1
5 4 3 2 1

[18] SPI_WP#

1
TABLE : CPU ITP DEBUG REPORT R597
1K_0402_1%
Individual DCI 2.0 VCCSTG
@
No use

2
Port w/o connector

R591 NO ASM NO ASM ASM


D 2 D

2
R593 NO ASM NO ASM ASM R93 R55 R56
51_0402_1% 51_0402_1% 51_0402_1%
R594 NO ASM NO ASM ASM DCI@ @ @
R595 NO ASM NO ASM ASM
1

1
PCH_TDO R596 1 DCI@ 2 0_0201_5% XDP_TDO PAD 1 @
R596 NO ASM NO ASM ASM [16] PCH_TDO IT9
PCH_TDI R594 1 DCI@ 2 0_0201_5% XDP_TDI PAD 1 @
R657 NO ASM NO ASM ASM [16] PCH_TDI IT10
PCH_TMS R593 1 DCI@ 2 0_0201_5% XDP_TMS PAD 1 @
R658 NO ASM NO ASM ASM [16] PCH_TMS IT11
PCH_TCK R99 1 @ 2 0_0201_5% PCH_TCK1 PAD 1 @
[16] PCH_TCK IT12
R102 NO ASM ASM NO ASM JTAGX R591 1 DCI@ 2 0_0201_5% XDP_TCK0 PAD 1 @
[16] JTAGX IT13
R597 NO ASM ASM NO ASM
R9907 NO ASM ASM ASM
2

R58
JXDP1 NO ASM ASM NO ASM 51_0402_1%
@
C70 NO ASM ASM NO ASM
1

R96 NO ASM ASM NO ASM


R101 NO ASM ASM NO ASM
R9909 NO ASM ASM ASM R224 1 DCI@ 2 0_0201_5% XDP_TDO
[6] PROC_TDO
R9910 NO ASM ASM ASM R222 1 DCI@ 2 0_0201_5% XDP_TDI
[6] PROC_TDI
R9916 NO ASM ASM ASM R221 1 DCI@ 2 0_0201_5% XDP_TMS
[6] PROC_TMS
R99 NO ASM ASM ASM R219 1 DCI@ 2 0_0201_5% XDP_TCK0
[6] PROC_TCK
R9912 NO ASM ASM ASM
C C
R9934 NO ASM ASM ASM
2

DCI@
RC176
R9930 NO ASM ASM ASM 51_0402_1%
R9931 NO ASM ASM ASM Mount RC 7 to enable
DCI function
1

+3VALW +3VALW_PCH
R9932 NO ASM ASM ASM +3V_SPI +1.05VALW
R9933 NO ASM ASM ASM
1

2
R225 R226 R228 R229
LOGIC 2.2K_0402_5% 2.2K_0402_5% 1K_0402_5% 1K_0402_5%
@ @ @ @
TABLE : PCH ITP DEBUG REPORT
2

1
@
R233 1 2 1K_0402_5% PAD 1 @
[16,49] EC_RSMRST# IT14
PAD 1 @
No use Individual DCI 2.0 [18] SPI_SI_XDP
PAD 1 @
IT15
[16] ITP_PMODE IT16
Port w/o connector [16,49] PBTN_OUT#
PAD 1 @
IT17
PAD 1 @
[16] SYS_RESET# IT18
R230 1 DCI@ 2 0_0402_5% PAD 1 @
R93 NO ASM ASM NO ASM [6] CFG3 IT19
need change to 5K refer CRB
JXDP1 NO ASM ASM NO ASM lace within 500mil of T-connection

R9917 NO ASM ASM NO ASM


R101 NO ASM ASM NO ASM
R9908 NO ASM ASM NO ASM
R9911 NO ASM ASM NO ASM
B R9913 NO ASM ASM NO ASM B

R9915 NO ASM ASM NO ASM R220 1 DCI@ 2 0_0402_5% R595 1 @ 2 0_0402_5% XDP_TRST# PAD 1 @
[22] CPU_TRST# IT20
PCH_PRDY# R657 1 @ 2 0_0402_5% XDP_PRDY# PAD 1 @
[22] PCH_PRDY# IT21
PCH_PREQ# R658 1 @ 2 0_0402_5% XDP_PREQ# PAD 1 @
G
P
P
_D
BE

8
_ 

O
_
R¨¨ 
E
B
O
O R
T

[22] PCH_PREQ# IT22


LOGIC +3VS




R /








 



(P
D

fw




)


*
TTw
Ch
O
 
 
 

 P
 D

( T
C 
H
 
 f
 
 

 

 


 
h 
 

PROC_TRST#
〃 [6] PROC_TRST#



y


g
I



f






)

h


c




f

TABLE : Functional Strap R223 1 DCI@ 2 0_0402_5%


[6] PROC_PRDY#





T
X
P

1

GPP_B18/GSPI0_MOSI (No Reboot) R563 R217 1 DCI@ 2 0_0402_5%


[6] PROC_PREQ#
R563
HIGH Enable "No Reboot" Mode ASM 1K_0402_5% Place near PCH
@
LOW Disable "No Reboot" Mode (Default ) NO ASM LOGIC
2

GPP_B18_NO_REBOOT GPP_B18_NO_REBOOT [20]

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 XDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 42 of 74
5 4 3 2 1
5 4 3 2 1

R43 1 2 0_0402_5%

L2
GPU_DPC_AUX_DN C34 2 1 0.1u_0201_10V6K GPU_DPC_AUX_DN_C 1 2 GPU_DPC_AUX_DN_CON
[25] GPU_DPC_AUX_DN 1 2
@
GPU_DPC_AUX_DP C341 2 1 0.1u_0201_10V6K GPU_DPC_AUX_DP_C 4 3 GPU_DPC_AUX_DP_CON
[25] GPU_DPC_AUX_DP 4 3
EXC24CH900U_4P
R44 1 2 0_0402_5% +5VS
D D

R45 1 2 0_0402_5%

L3
GPU_DPC_TX3_DN C342 2 1 0.1u_0201_10V6K GPU_DPC_TX3_DN_C 1 2 GPU_DPC_TX3_DN_CON
[25] GPU_DPC_TX3_DN 1 2

1
@ D
GPU_DPC_TX3_DP C347 2 1 0.1u_0201_10V6K GPU_DPC_TX3_DP_C 4 3 GPU_DPC_TX3_DP_CON GPU_DIS_PWR_EN 2 Q194
[25] GPU_DPC_TX3_DP 4 3 G L2N7002KWT1G_SOT323-3
EXC24CH900U_4P
R46 1 2 0_0402_5% S

3
DMN5L06DWK-7 2N SOT363-6
DMN5L06DWK-7 2N SOT363-6 Q186B
R47 1 2 0_0402_5% Q186A
GPU_DPC_AUX_DN 1 6 3 4 GPU_DPC_AUX_DN_C

D
S
+3VS

S
L4

1
R10238
10K_0402_5%
GPU_DPC_TX2_DP C349 2 1 0.1u_0201_10V6K GPU_DPC_TX2_DP_C 1 2 GPU_DPC_TX2_DP_CON
[25] GPU_DPC_TX2_DP 1 2
@

G
GPU_DPC_TX2_DN C348 2 1 0.1u_0201_10V6K GPU_DPC_TX2_DN_C 4 3 GPU_DPC_TX2_DN_CON

G
[25] GPU_DPC_TX2_DN

5
4 3

1
EXC24CH900U_4P
R48 1 2 0_0402_5% HD_DET

R10237
10K_0402_5%
2

5
Q193B

2
3
R49 1 2 0_0402_5% D 2N7002KDWH_SOT363-6

1
1 5

R10246
1M_0402_5%

C10149
0.01U_0201_6.3V7-K
L5 G
GPU_DPC_TX1_DP C351 2 1 0.1u_0201_10V6K GPU_DPC_TX1_DP_C 1 2 GPU_DPC_TX1_DP_CON GPU_DPC_AUX_DP 1 6 3 4 GPU_DPC_AUX_DP_C

S
[25] GPU_DPC_TX1_DP

S
1 2

D
S

4
@ Q187A 2

2
Q187B

6
GPU_DPC_TX1_DN C350 2 1 0.1u_0201_10V6K GPU_DPC_TX1_DN_C 4 3 GPU_DPC_TX1_DN_CON DMN5L06DWK-7 2N SOT363-6 D
[25] GPU_DPC_TX1_DN 4 3 DMN5L06DWK-7 2N SOT363-6 2 HDMI_DONGLE_DETECT
EXC24CH900U_4P G
R50 1 2 0_0402_5% 1
S 2N7002KDWH_SOT363-6 C10150

1
Q193A 0.01UF_0402_25V7-K

R10221 1 2 0_0402_5% 2

L92
GPU_DPC_TX0_DP C353 2 1 0.1u_0201_10V6K GPU_DPC_TX0_DP_C 1 2 GPU_DPC_TX0_DP_CON
[25] GPU_DPC_TX0_DP 1 2
@
GPU_DPC_TX0_DN C352 2 1 0.1u_0201_10V6K GPU_DPC_TX0_DN_C 4 3 GPU_DPC_TX0_DN_CON
[25] GPU_DPC_TX0_DN 4 3
EXC24CH900U_4P
R10222 1 2 0_0402_5%
C C

+1.8VS_AON
1

R317
10K_0402_5%
2

IFPC_HPD
[27] IFPC_HPD

Q181
MMBT3904WH_SOT323-3
1

C
2 R318 1 2 100K_0402_5% R319 1 2 0_0402_5% DP_HPD_CON
B
3

1 1
R324 C366 C367
100K_0402_5% 220P_0402_50V7K 220P_0402_50V7K
2 2
2

+5VS

+3VS
2

+3VS_DP
G
3

DP_HPD R10223 1 2 0_0402_5% DP_HPD_CON


[15] DP_HPD
S

F1
1 3 1 2
D

Q192
2

PJA138K_SOT23-3 1.1A_8V_1206L110THYR 1 1
B R311 C369 C368 B
G
2

10K_0402_5% Q196 10U_0805_10V6K .1U_0402_10V6-K


@ LP2301ALT1G_SOT23-3
2 2
1

V20B+ [36,40,53] SUSP


+3VS
1

D3
R10240
10K_0402_5%

DP_HPD_CON 1 1 10 9 DP_HPD_CON
2

JDP1
+3VS_DP 2 2 9 8 +3VS_DP R10410 500mA
2

0_0402_5% Add by Bing 0 DP_HPD_CON 2 20


HOT_PLUG DP_PWR
1

GPU_DPC_TX2_DN_CON 4 4 7 7 GPU_DPC_TX2_DN_CON +3VS Q191 D 19


GPU_DIS_PWR_EN 2 GPU_DPC_AUX_DP_CON 16 GND6 14
1

GPU_DPC_TX2_DP_CON 5 5 GPU_DPC_TX2_DP_CON G GPU_DPC_AUX_DN_CON AUX_CH_P GND5


6 6 18 6 R326 1 2 1M_0402_5%
AUX_CH_N CONFIG2 4 HDMI_DONGLE_DETECT
CONFIG1
1

3 3 S L2N7002KWT1G_SOT323-3 GPU_DPC_TX3_DP_CON 10 13
3

R10334 @ GPU_DPC_TX3_DN_CON 12 ML_LANE3_P GND4 8


Modified by Bing 0
R10241
10K_0402_5%

ML_LANE3_N GND3 7
100K_0402_5% GND2
GPU_DPC_TX2_DP_CON 15 1 Add DP++ function-Harry 0/
ML_LANE2_P GND1
1

VGA_MAIN_3V_1.8V GPU_DPC_TX2_DN_CON 17
For EMC Low : DP ort enable
2

ML_LANE2_N
R325
1M_0402_5%

AZ1045-04F_DFN2510P10E-10-9 21
R315 1 2 100K_0402_5%GPU_DPC_AUX_DN_C GPU_DPC_TX1_DP_CON 9 GND7 High: HDMI ort enable
EMC_NS@ D ML_LANE1_P
3

GPU_DPC_TX1_DN_CON 11 22
ML_LANE1_N GND8
1

5 Q190B R316 1 2 100K_0402_5%GPU_DPC_AUX_DP_C


2

G LBSS138DW1T1G_SOT363-6 GPU_DPC_TX0_DN_CON 5 23
R10242
10K_0402_5%

GPU_DPC_TX0_DP_CON 3 ML_LANE0_N GND9


S
4

D5 ML_LANE0_P 24
GPU_DPC_TX3_DP_CON 1 1 GPU_DPC_TX3_DP_CON GND10
10 9
2

GPU_DPC_TX3_DN_CON 2 2 9 8 GPU_DPC_TX3_DN_CON ALLTO_C17717-120A9-L


D
6

ME@
GPU_DPC_AUX_DP_CON 4 4 7 7 GPU_DPC_AUX_DP_CON 2 Q190A
G LBSS138DW1T1G_SOT363-6 +3VS
GPU_DPC_AUX_DN_CON 5 5 6 6 GPU_DPC_AUX_DN_CON S
1

3 3

Q1951
AZ1045-04F_DFN2510P10E-10-9 For EMC D
EMC_NS@
HD_DET 2 @
G PJA138K_SOT23-3
S
A D6 A
GPU_DPC_TX1_DN_CON 1 1 GPU_DPC_TX1_DN_CON 3
10 9
GPU_DPC_TX1_DP_CON 2 2 9 8 GPU_DPC_TX1_DP_CON
1

GPU_DPC_TX0_DN_CON 4 4 7 7 GPU_DPC_TX0_DN_CON

GPU_DPC_TX0_DP_CON 5 5 6 6 GPU_DPC_TX0_DP_CON R10336 R10335


2.2K_0402_5% 2.2K_0402_5%
3 3
2

@ @

For EMC GPU_DPC_AUX_DN_C


AZ1045-04F_DFN2510P10E-10-9
EMC_NS@
GPU_DPC_AUX_DP_C Title
Security Classification LC Future Center Secret Data
Issued Date 2013/08/08 Deciphered Date 2016/02/26 DP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 43 of 74
5 4 3 2 1
5 4 3 2 1

+3VS +3VS

REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-:


Fintek thermal sensor Trace width/space:10/10 mil
placed near DIMM Trace length:<8"
2

+3VS R881 R882


D U1 4.7K_0402_5% 4.7K_0402_5% REMOTE1+
Near GPU&VRAM REMOTE2+
Near CPU core D
@ @ 1 1

1
C C
1

1 10 EC_SMB_CK2 C45 2 Q15 C46 2 Q16


VCC SCL EC_SMB_CK2 [16,27,49] B B
3300P_0402_50V7-K MMBT3904WH_SOT323-3 3300P_0402_50V7-K MMBT3904WH_SOT323-3
1 REMOTE1+ 2 9 EC_SMB_DA2 @2 @ @2 @
EC_SMB_DA2 [16,27,49]

3
DP1 SDA REMOTE1- REMOTE2-
C47 REMOTE1- 3 8 THEM_ALERT# R301 1 2 0_0402_5%
.1U_0402_10V6-K DN1 ALERT# SMB1_ALERT# [16]
2 @
@ REMOTE2+ 4 7 THERM_L
DP2 THERM#
REMOTE2- 5 6
DN2 GND

F75303M_MSOP10
@

Near GPU&VRAM
Near CPU

+5VLP +5VLP +3VALW


+5VLP +3VALW

HW thermal sensor
2

1
2

C254 R29 R36 R10351

1
C 0.1U_0603_25V7-M 21.5K_0402_1% 21.5K_0402_1% 13.7K_0402_1% C
@ @ @ R10353
1

13.7K_0402_1%
1

2
U18 NTC_V1_GPU
[44,49] NTC_V1_GPU

2
1 8 TMSNS1 R88 1 @ 2 0_0402_5% NTC_V1_GPU
VCC TMSNS1 NTC_V1_GPU [44,49]
1 [44,49] NTC_V2_CPU
NTC_V2_CPU
2 7 PHYST1 R175 1 @ 2 10K_0402_5% RT2
GND RHYST1
100K_0402_1%_TSM0B104F4251RZ
3 6 TMSNS2 R176 1 @ 2 0_0402_5% NTC_V2_CPU
OT1 TMSNS2 NTC_V2_CPU [44,49]
2

1
4 5 PHYST2 R177 1 @ 2 10K_0402_5%
[49,60,64] EC_ON OT2 RHYST2 RT3
G718TM1U_SOT23-8 100K_0402_1%_TSM0B104F4251RZ
2

@
R10352

2
0_0402_5%
over temperature threshold:
RSET=3*RTMH
1

92+/-30C @

Hysteresis temperature threshold.


RHYST=(RSET*RTML)/(3*RTML-RSET)
56+/-30C
for layout optimized, change the EC_AGND to GND
B B

Near DIMM FAN Conn


+3VALW Address 1001_101xb
+5VS
1

JFAN1
R10355 R52 1 2 0_0603_5% +5VS_FAN1 1
13.7K_0402_1% 2 1
[49] EC_FAN1_SPEED 2
1 @ 1 [49] EC_FAN1_PWM 3
C50 4 3
2

C49 .1U_0402_10V6-K 5 4
NTC_V3_DIMM 10U_0805_10V6K @ 6 G1
[49] NTC_V3_DIMM 2 2 G2
HIGHS_WS32040-S0471-HF
ME@
1

RT4
100K_0402_1%_TSM0B104F4251RZ +5VS
JFAN2
R75 1 2 0_0603_5% +5VS_FAN2 1
2

2 1
[49] EC_FAN2_SPEED 2
1 @ 1 [49] EC_FAN2_PWM 3
C60 4 3
C81 .1U_0402_10V6-K 5 4
A G1 A
2

10U_0805_10V6K @ 6
R10354 R188 2 2 G2
0_0402_5% 0_0402_5% HIGHS_WS32040-S0471-HF
@ ME@
1

@
Security Classification LC Future Center Secret Data Title

EC_AGND
Issued Date 2015/02/26 Deciphered Date 2016/02/26 Thermal sensor/FAN CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 44 of 74
5 4 3 2 1

AMP/Volume Control
A B C D E

+3VS_WLAN

Mini-Express Card(WLAN/WiMAX)

10U_0603_6.3V6M

4.7U_0603_6.3V6K
1 1 2 1

CV464

CV465
C10184 C10185
1U_0402_10V6K @
@ 0.1u_0201_10V6K
2 2 1 2
JWLAN2 +3VS

1 2
USB20_P14 3 GND1 3.3VAUX1 4
[19] USB20_P14 USB20_N14 USB_D+ 3.3VAUX2
5 6 1 @ T1

49.9K_0402_1%
[19] USB20_N14 USB_D- LED1#
7 8
GND2 PCM_CLK/I2S_SCK

1
CNVI_WR_D1_N 9 10 R10381 1 2 0_0402_5%
[19] CNVI_WR_D1_N CNVI_WR_D1_P SDIO_CLK PCM_SYNC/I2S_WS CNVI_RF_RESET# [16]
11 12

R344
[19] CNVI_WR_D1_P SDIO_CMD PCM_IN/I2S_SD_IN
13 14 R10392 1 2 0_0402_5%
CNVI_WR_D0_N SDIO_DATA0 PCM_OUT/I2S_SD_OUT CNVI_MODEM_CLKREQ [16]
15 16 1 @ T2
[19] CNVI_WR_D0_N CNVI_WR_D0_P SDIO_DATA1 LED#2
17 18
[19] CNVI_WR_D0_P

2
19 SDIO_DATA2 GND11 20
CNVI_WR_CLK_N 21 SDIO_DATA3 UART_WAKE# 22 R10382 1 CNVI@ 2 22_0402_5%
[19] CNVI_WR_CLK_N CNVI_WR_CLK_P SDIO_WAKE# UART_RXD CNVI_BRI_RSP [19] PCH_UART2_RXD [20]
23
[19] CNVI_WR_CLK_P SDIO_RESET# +3VS

1 1

49.9K_0402_1%
K Y

1
5 PI ~PI 3 C PI
7

R345
9
3 30

2
33 32 PCH_UART2_TXD [20]
GND3 UART_TXD CNVI_RGI_DT [19]
35 34 R10385 1 CNVI@ 2 22_0402_5%
[14] PCIE_PTX_C_DRX_P13 PETP0 UART_CTS CNVI_RGI_RSP [19]
37 36
+3VS +3VS_WLAN [14] PCIE_PTX_C_DRX_N13 PETN0 UART_RTS EC_TX_RSVD EC_TX CNVI_BRI_DT [19]
39 38 R2075 1 @ 2 0_0402_5%
GND4 VENDOR_DEFINED1 EC_RX_RSVD EC_RX
WLAN [14] PCIE_PRX_DTX_P13
41
PERP0 VENDOR_DEFINED2
40 R2067 1 @ 2 0_0402_5%
2

[14] PCIE_PRX_DTX_N13 43 42 change EC_RX/TX to pin58/60 for new debug card


PERN0 VENDOR_DEFINED3
2

Q165 R2072 45 44
G

GND5 COEX3 EC_TX [48,49] 2017_0802


10K_0402_5% 47 46
[17] CLK_PCIE_WLAN REFCLKP0 COEX2 EC_RX [48,49]
AOAC@ 49 48
[17] CLK_PCIE_WLAN# REFCLKN0 COEX1 SUSCLK_R
51 50 R2076 1 2 0_0402_5%
SUSCLK [16]
1

3 1 WLAN_CLKREQ_Q# 53 GND6 SUSCLK 52 PLT_RST#


[17] WLAN_CLKREQ# CLKREQ0# PERST0# PLT_RST# [18,27,49,50,51]
S

R401 1 AOAC@ 2 0_0402_5% 55 54 BT_OFF# R2070 1 2 1K_0402_5%


[16,49] PCIE_WAKE# PEWAKE0# W_DISABLE2# WLAN_OFF# PCH_BT_OFF# [20]
L2N7002KWT1G_SOT323-3 R2071 1 @ 2 0_0402_5% 57 56 R2066 1 2 0_0402_5%
[49,51] LAN_WAKE# GND7 W_DISABLE1# PCH_WLAN_OFF# [20]
AOAC@
@
CNVI_WT_D1_N 59 58 EC_RX
[19] CNVI_WT_D1_N CNVI_WT_D1_P RSRVD/PETP1 I2C_DATA EC_TX
R80 1 2 0_0402_5% 61 60
[19] CNVI_WT_D1_P RSRVD/PETN1 I2C_CLK
63 62
CNVI_WT_D0_N 65 GND8 ALERT# 64
[19] CNVI_WT_D0_N CNVI_WT_D0_P RSRVD/PERP1 RSRVD CLKIN_XTAL_LCP [17]
If su ort A AC C R 0 67 66
[19] CNVI_WT_D0_P RERVD/PERN1 UIM_SWP/PERST1# +3VS_WLAN
69 68
if not su ort A AC stuff R 0 GND9 UIM_POWER_SNK/CLKREQ1#

1
CNVI_WT_CLK_N 71 70
[19] CNVI_WT_CLK_N CNVI_WT_CLK_P RSRVD/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1#
73 72 R2073
[19] CNVI_WT_CLK_P RSRVD/REFCLKN1 3.3VAUX3 PLT_RST#
75 74 100K_0402_5%
GND10 3.3VAUX4
77 76 1

2
GND15 GND14 C381
1000P_0402_50V7K

ARGOS_NASE0-S6701-TS40 2
ME@

1
C10186 1
1U_0402_10V6K C10187
@ @
2 0.1u_0201_10V6K
2

+3VS +3VS_WLAN

J3 Don't short
1 2
1 2 JUMP_43X79
@ 1
+3VALW C325
J8 Need short 1U_0402_10V6K
1 2 @
1 2 JUMP_43X79 2
@

2 2

M.2 SSD(SATA/PCIE) +3VS +3.3V_NGFF

2A
R94 1 2 0_0805_5%
C239
22U_0603_6.3V6-M

1 1 1
C240
4.7U_0402_6.3V6M

@ C241
.1U_0402_10V6-K
OPTANE@
2 2 2

JSSD1 NGFF +3.3V_NGFF

1 2
3 GND_1 3.3V_1 4
PCIE_PRX_DTX_N9 5 GND_2 3.3V_2 6
[14] PCIE_PRX_DTX_N9 PERN3 N/C_2 2
PCIE_PRX_DTX_P9 7 8 C238
3 [14] PCIE_PRX_DTX_P9 PERP3 N/C_3 3
9 10 .1U_0402_10V6-K
PCIE_PTX_DRX_N9 CC170 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_N9_C 11 GND_3 DAS/DSS# 12
[14] PCIE_PTX_DRX_N9 PCIE_PTX_DRX_P9 PETN3 3.3V_3 1
CC171 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_P9_C 13 14
[14] PCIE_PTX_DRX_P9 PETP3 3.3V_4 +3.3V_NGFF
15 16
PCIE_PRX_DTX_N10 17 GND_4 3.3V_5 18
[14] PCIE_PRX_DTX_N10 PCIE_PRX_DTX_P10 PERN2 3.3V_6
19 20
[14] PCIE_PRX_DTX_P10 PERP2 N/C_4
21 22
PCIE_PTX_DRX_N10 CC168 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_N10_C 23 GND_5 N/C_5 24
[14] PCIE_PTX_DRX_N10 PETN2 N/C_6
1

PCIE_PTX_DRX_P10 CC169 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_P10_C 25 26


[14] PCIE_PTX_DRX_P10 PETP2 N/C_7
27 28 R95
PCIE_PRX_DTX_N11 29 GND_6 N/C_8 30 10K_0201_5%
[14] PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11 PERN1 N/C_9
31 32 @
[14] PCIE_PRX_DTX_P11 PERP1 N/C_10
33 34
2

PCIE_PTX_DRX_N11 CC166 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_N11_C 35 GND_7 N/C_11 36


[14] PCIE_PTX_DRX_N11 PCIE_PTX_DRX_P11 PETN1 N/C_12
CC167 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_P11_C 37 38 DEVSLP1_R R96 1 @ 2 0_0201_5% DEVSLP1
[14] PCIE_PTX_DRX_P11 PETP1 DEVSLP DEVSLP1 [15]
39 40
PCIE_SATA_PRX_DTX_P12 41 GND_8 N/C_13 42
[14] PCIE_SATA_PRX_DTX_P12 PCIE_SATA_PRX_DTX_N12 PERN0/SATA-B+ N/C_14
43 44
[14] PCIE_SATA_PRX_DTX_N12 PERP0/SATA-B- N/C_15
1

45 46
PCIE_SATA_PTX_DRX_N12 CC39 2 1 0.22U_0201_6.3V6-K PCIE_SATA_PTX_DRX_N12_C 47 GND_9 N/C_16 48 R97
[14] PCIE_SATA_PTX_DRX_N12 PCIE_SATA_PTX_DRX_P12 PETN0/SATA-A- N/C_17
CC165 2 1 0.22U_0201_6.3V6-K PCIE_SATA_PTX_DRX_P12_C 49 50 PLT_RST# 10K_0201_5%
[14] PCIE_SATA_PTX_DRX_P12 PETP0/SATA-A+ PERST# SSD_CLKREQ#
51 52
CLK_PCIE_SSD# GND_10 CLKREQ# SSD_CLKREQ# [17]
53 54 1 1
[17] CLK_PCIE_SSD#
2

CLK_PCIE_SSD 55 REFCLKN PEWAKE# 56 @ C382


[17] CLK_PCIE_SSD REFCLKP N/C_18
+3.3V_NGFF 57 58 TP76 1000P_0402_50V7K
GND_11 N/C_19
1

59 C C 0 2
R274 C C
10K_0201_5% 3 C C
5 C C
67 68 +3.3V_NGFF
2

0_0402_5% 2 1 R249 SSD_DET 69 N/C_1 SUSCLK 70


[14] SSD_DET# PEDET 3.3V_7
71 72
73 GND_12 3.3V_8 74
@
GND_13 3.3V_9
0.1u_0201_10V6K

C255
22U_0603_6.3V6-M

75 1 1 1
GND_14
1

0.01U_0201_10V6K
C310

C237

PEDET (PE_DTCT) R290 77 76


PEG1 PEG2
OPTANE@

OPTANE@

OPTANE@

10K_0201_5%
SATA Device GND @ 2 2 2
PCIe Device Open
2

ARGOS_NASM0-S6701-TS40
ME@
SSD_DET#
0 - SATA
1 - PCIE

4 4

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 NGFF WLAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 45 of 74
A B C D E
A B C D E F G H

SATA HDD Conn.

+5VS
JHDD1

+5VS R342 1 2 0_0805_5% 1


1 2 1 1
3 2
1 1 1 1 3
C74 C75 C76 C77 4
1000P_0402_50V7K .1U_0402_10V6-K 1U_0402_10V6K 10U_0805_10V6K SATA_PRX_DTX_P4 C69 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P4 5 4
@ @ @ [14] SATA_PRX_DTX_P4 SATA_PRX_DTX_N4 C68 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N4 6 5
2 2 2 2 [14] SATA_PRX_DTX_N4 7 6
SATA_PTX_DRX_N4 C67 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_N4 8 7 12
[14] SATA_PTX_DRX_N4 8 GND2
SATA_PTX_DRX_P4 C66 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P4 9
[14] SATA_PTX_DRX_P4 9
10 11
10 GND1
For EMC
HIGHS_FC5AF101-2931H
ME@

2 2

3 3

4 4

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 HDD/XBOX CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 46 of 74
A B C D E F G H
A B C D E

+USB_VCCA

C59 1 2 220U_B2_6.3VM_R35M

+
C62 1 2
1 1
@ 1U_0603_25V6M

C63 1 2
@ 470P_0402_50V7K

JUSB2
1
USB20_N1_B R71 1 @ 2 0_0402_5% USB20_N1_R 2 VBUS
USB20_P1_B R70 1 @ 2 0_0402_5% USB20_P1_R 3 D-
4 D+
USB30_RX_N3 R73 1 @ 2 0_0402_5% USB30_RX_R_N3 5 GND1
[15] USB30_RX_N3 USB30_RX_P3 USB30_RX_R_P3 SSRX-
R72 1 @ 2 0_0402_5% 6 10
[15] USB30_RX_P3 SSRX+ GND3
7 11
USB30_TX_N3 C65 1 2 .1U_0402_10V6-K USB30_TX_C_N3 R69 1 @ 2 0_0402_5% USB30_TX_R_N3 8 GND2 GND4 12
[15] USB30_TX_N3 USB30_TX_P3 C64 SSTX- GND5
1 2 .1U_0402_10V6-K USB30_TX_C_P3 R68 1 @ 2 0_0402_5% USB30_TX_R_P3 9 13
[15] USB30_TX_P3 SSTX+ GND6

ALLTO_C107MJ-10939-L
ME@

USB20_P1_R
+USB_VCCA
USB20_N1_R
3

2 2
1

D63
AZC199-02S.R7G_SOT23-3 D11
1

EMC@ AZ5725-01F.R7GR_DFN1006P2X2
EMC@

USB charger
2

2.5A
2

+5VALW
1

U3

C197 2 1 .1U_0402_16V7K 1 16 ILIM_HI R2047 1 2 20K_0402_1%


@ IN ILIM_HI
USB20_N1 2 15 ILIM_LO R2048 1 @ 2 20K_0402_1%
[19] USB20_N1 DM_OUT ILIM_LO
USB20_P1 3 14
[19] USB20_P1 DP_OUT GND
ILIM_SEL 4 13
ILIM_SEL FAULT USB_OC2# [19]
5 12 +USB_VCCA
[49] USB_CHG_EN EN OUT
D12 EMC@
USB30_RX_R_N3 9 10 1 1USB30_RX_R_N3 CHG_MOD1 6 11 USB20_N1_B
[49] CHG_MOD1 CLT1 DM_IN
USB30_RX_R_P3 8 9 2 2 USB30_RX_R_P3 CHG_MOD2 7 10 USB20_P1_B
CLT2 DP_IN
E_PAD

USB30_TX_R_N3 7 7 4 4 USB30_TX_R_N3 CHG_MOD3 8 9 STATUS#


[49] CHG_MOD3 CLT3 STATUS STATUS# [49]
USB30_TX_R_P3 6 6 5 5 USB30_TX_R_P3
SN1702001RTER_WQFN16_3X3
17

3 3

AZ1045-04F_DFN2510P10E-10-9
3 +5VALW 3

For EMC
+5VALW

ILIM_SEL R2064 2 1 10K_0402_5% STATUS# R10394 2 1 10K_0402_5%

L9 CHG_MOD2 R10357 2 1 10K_0402_5% for placement optimization


EXC24CH900U_4P [close to EC side]
USB30_RX_P3 4 3 USB30_RX_R_P3
4 3
ILIM_SEL R2065 2 @ 1 10K_0402_5%
USB30_RX_N3 1 2 USB30_RX_R_N3
1 2 CHG_MOD2 R10356 2 @ 1 10K_0402_5%
EMC@ CLT1 CLT2 CLT3 ILIM_SEL MOD
USB_CHG_EN R2052 2 1 10K_0402_5%
L10
EXC24CH900U_4P 0 0 0 X DCH OUT held low
USB30_TX_C_P3 4 3 USB30_TX_R_P3
4 3

USB30_TX_C_N3 1 2 USB30_TX_R_N3
* 1 1 1 1 CDP Data Connected and Port Power Mgt. Function Active
1 2
EMC@
* 1 1 1 0 SDP2 Data Connected

L11
EXC24CH900U_4P
* 1 1 0 X SDP1 Data Connected
USB20_P1_B 4 3 USB20_P1_R
4 3
* 0 1 0 X SDP1 Data Connected
USB20_N1_B 1 2 USB20_N1_R
1 2
EMC@ 1 0 0 X DCP_Short Device Forced to stay in DCP BC 1.2 charging mode

1 0 1 X DCP_Divider Device Forced to stay in DCP Divider 1 Charging Mode


For EMC
4 4

* 0 1 1 X DCP_Auto Data Disconnected and Port Power Mgt. Function Active

0 0 1 X DCP_Auto Data Disconnected and Power Wake Function Active

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 USB2.0/USB3.0 PORT (LEFT)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 47 of 74
A B C D E
5 4 3 2 1

+USB_VCCD

C55 1 2 220U_6.3V_M

+
USB3.1 PORT x1
C56 1 2
@ 1U_0603_25V6M Low Active 1.8A
+5VALW +USB_VCCD
C57 1 2
@ 470P_0402_50V7K U125
5 1
IN OUT
D D
JUSB1 2 2
USB30_TX_P1 C79 1 2 .1U_0402_10V6-K USB30_TX_C_P1 R74 1 @ 2 0_0402_5% USB30_TX_R_P1 9 C10159 GND
[15] USB30_TX_P1 StdA_SSTX+ USB_OC3#
1 1U_0402_16V6K 4 3
USB30_TX_N1 C80 1 2 .1U_0402_10V6-K USB30_TX_C_N1 R76 1 @ 2 0_0402_5% USB30_TX_R_N1 8 VBUS ENB OCB USB_OC3# [19]
[15] USB30_TX_N1 USBP2+_S USBP2+_S_R StdA_SSTX- 1
R64 1 @ 2 0_0402_5% 3 G517E2T11U_SOT23-5 1
UARTA_P80_EN 7 D+ C10158
USBP2-_S R65 1 @ 2 0_0402_5% USBP2-_S_R 2 GND_DRAIN 10 1000P_0402_50V7K
USB30_RX_P1 R79 1 @ 2 0_0402_5% USB30_RX_R_P1 6 D- GND_2 11 @
[15] USB30_RX_P1 StdA_SSRX+ GND_3 2
4 12
USB30_RX_N1 R78 1 @ 2 0_0402_5% USB30_RX_R_N1 5 GND_1 GND_4 13 USB_ON#
[15] USB30_RX_N1 StdA_SSRX- GND_5 [49,50] USB_ON#
ALLTO_C190DU-10939-L
ME@
2 Debug@ 1

R537 R538
2

100K_0402_5%
USB@

0_0402_5%
1

For USB Debug Function

2 Debug@ 1 USB_UART_SEL
[20] USBDEBUG
C R531 0_0402_5% C

D24
USB30_RX_R_N1 9 10 1 1USB30_RX_R_N1 USBP2+_S_R +USB_VCCD

USB30_RX_R_P1 8 9 2 2 USB30_RX_R_P1 USBP2-_S_R


U129
3

USB30_TX_R_N1 7 7 4 4 USB30_TX_R_N1
1

USB30_TX_R_P1 6 6 5 5 USB30_TX_R_P1
1

D62 D65 R533 2 Debug@ 1 0_0402_5% EC_TX_C 1 10 R104562 Debug@ 1 0_0402_5% +3VALW
[45,49] EC_TX 1D+ VCC
3 3 AZC199-02S.R7G_SOT23-3 AZ5725-01F.R7GR_DFN1006P2X2
EMC@ EMC@ R536 2 Debug@ 1 0_0402_5% EC_RX_C 2 9 USB_UART_SEL
[45,49] EC_RX 1D- S
2

3 8 USBP2+_S
[19] USB20_P0 2D+ D+
AZ1045-04F_DFN2510P10E-10-9 NCY3958Y
2

EMC@ 4 7 USBP2-_S
[19] USB20_N0 2D- D-
5 6
1

GND1 OE#
for EMC 11
GND2

L15 NCT3958Y_DFN10_3X3
EXC24CH900U_4P Debug@
USB30_RX_N1 4 3 USB30_RX_R_N1
4 3

USB30_RX_P1 1 2 USB30_RX_R_P1
1 2
EMC@
USB20_P0 2 USB@1 USBP2+_S
L16 R539 0_0402_5%
EXC24CH900U_4P
USB30_TX_C_N1 4 3 USB30_TX_R_N1 USB20_N0 2 USB@1 USBP2-_S
B 4 3 R541 0_0402_5% B
USBDEBUG Kernel debug
USB30_TX_C_P1 1 2 USB30_TX_R_P1
1 2 Set in ut Set in ut
EMC@
Set out ut Low ABL
L8
EXC24CH900U_4P
USBP2-_S 4 3 USBP2-_S_R +3VALW
4 3

USBP2+_S 1 2 USBP2+_S_R
1 2 UARTA_P80_EN POST 80
1

for EMC EMC@


Set in ut DISABL R547
Debug@ 10K_0402_5%
Set out ut Low ABL
2

USB_UART_SEL
1

D
UARTA_P80_EN 2
OE# S FUNCTION G L2N7002KWT1G_SOT323-3
Q56
H X DISABL S Debug@
3

L L D +/- to D +/-

L H D +/- to D +/-

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/6/23 Deciphered Date 2015/6/23 USB2.0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 48 of 74
5 4 3 2 1
5 4 3 2 1

+3VALW_R +VFSPI RE1 1 2 0_0603_5%


For EMI +3VL 0.5A

+3VALW RE75 1 @ 2 0_0402_5% RE3 1 2 0_0603_5% +3VALW


@
2 @ 1 RE2 CLK_PCI_EC
+3VALW_R +3VALW_R +3VALW_EC
10_0402_5% RE97 1 2 0_0402_5%
1
For SPI ROM Mirror RE4 1 2 0_0603_5%
CE2 +3VALW_R All capacitors close to EC
10P_0402_50V8J 1 1
2

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
@ CE4
+VFSPI .1U_0402_10V6-K CE5
EMC_NS@ 220P_0402_50V7K 2 1 CE24 LPC_FRAME# Close EC +3VS
1
CE6
1
CE7
1
CE8
1
CE9
1
CE10
1
CE11 1000P_0402_50V7K
+3VALW_EC RE6 1 2 0_0603_5% 2 EC_AGND 2
D LPC_AD3 D
EMC_NS@ 220P_0402_50V7K 2 1 CE25 CE3 CD@ @ @
PLT_RST# 1 2 VCOREVCC 2 2 2 2 2 2
EMC_NS@ 220P_0402_50V7K 2 1 CE26 LPC_AD2
1 .1U_0402_10V6-K EC_AGND
CE1 EMC_NS@ 220P_0402_50V7K 2 1 CE27 LPC_AD1 +3VS
1000P_0402_50V7K For Cost down
EMC_NS@ 220P_0402_50V7K 2 1 CE28 LPC_AD0
minimum trace width 12 mil
121
127
114
106

2
12

11

26
50
92

74

UE1 EC_FAN2_SPEED RE66 1 2 10K_0402_5%


Reserved Cap HLZ SDV 0616
VFSPI
VCORE

VCC

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY(PLL)5
VSTBY6

AVCC

EC_FAN2_PWM RE65 1 @ 2 10K_0402_5%


change CE1 from @ to stuff due to signal waveform abnormal EC_FAN1_SPEED RE10 1 2 10K_0402_5%
HLZ SIV 0811
EC_FAN1_PWM RE11 1 @ 2 10K_0402_5%
[24] WRST#
KBRST# 4 24 PWR_LED1#
+3VALW_R [15] KBRST# KBRST#/GPB6 PWM0/GPA0 PWR_LED2# PWR_LED1# [50] LPC_FRAME#
SERIRQ 5 25 RE7 1 @ 2 10K_0402_5%
[15,50] SERIRQ LPC_FRAME# ALERT#/SERIRQ/GPM6 PWM1/GPA1 BATT_LOW_LED# PWR_LED2# [35]
6 28
[15,50] LPC_FRAME# LPC_AD3 ECS#/LFRAME#/GPM5 PWM2/GPA2 LED_KB_PWM BATT_LOW_LED# [50]
7 29 ENBKL RE9 1 @ 2 100K_0402_5%
[15,50] LPC_AD3 LPC_AD2 EIO3/LAD3/GPM3 PWM3/GPA3 EC_FAN2_PWM LED_KB_PWM [50]
DE1 1 2 @ 8 PWM 30
[15,50] LPC_AD2 LPC_AD1 EIO2/LAD2/GPM2 PWM4/GPA4 EC_FAN1_PWM EC_FAN2_PWM [44]
9 31
[15,50] LPC_AD1 LPC_AD0 EIO1/LAD1/GPM1 PWM5/GPA5 EC_FAN1_PWM [44]
10 32 BEEP#
RB751V-40_SOD323-2 [15,50] LPC_AD0 CLK_PCI_EC EIO0/LAD0/GPM0 PWM6/SSCK/GPA6 BATT_CHG_LED# BEEP# [40] +3VALW
13 LPC 34
[15] CLK_PCI_EC ESCK/LPCCLK/GPM4 PWM7/RIG1#/GPA7 RTS5455_SM_INT BATT_CHG_LED# [50]
RE8 1 2 100K_0402_5% WRST# 14 120 RTS5455_SM_INT [14,38]
EC_SMI# 15 WRST# GPC4 124 SUSP#
[15] EC_SMI# EC_RX PLTRST#/ECSMI#/GPD4 GPC6 SUSP# [53,61,64]
1 16
[45,48] EC_RX EC_TX SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7 NTC_V1_GPU EC_ON_1.8V
17 66 NTC_V1_GPU [44] RE98 1 @ 2 10K_0402_5%
CE12 [45,48] EC_TX PLT_RST# SOUT0/LPCPD#/GPE6 ADC0/GPI0 NTC_V2_CPU
22 67 NTC_V2_CPU [44] Change to NTC_V1_GPU & NTC_V2_CPU
1U_0402_6.3V6K [18,27,45,50,51] PLT_RST# EC_SCI# ERST#/LPCRST#/GPD2 ADC1/GPI1 BATT_TEMP
23 68
2 [14,20] EC_SCI# PCH_PWR_EN ECSCI#/GPD3 ADC2/GPI2 BATT_I BATT_TEMP [58,59] HLZ SDV 0613
126 ADC 69
[53] PCH_PWR_EN GA20/GPB5 ADC3/GPI3 BATT_I [59]
70 PSYS [59,65] change ENBKL to PSYS on GPI4 by Bing 0717
[50] RGB_PWR_EN
RE99 1 RGB@ 2 0_0402_5% IT8226E-128/BX ADC4/GPI4
ADC5/DCD1#/GPI5
71
72
ADP_I
ADAPTER_ID
PSYS
ADP_I [59] [14] PCH_EDP_ENBKL
R299 1 2 0_0402_5% ENBKL
[58,59] Change CHG_MOD2 to NTC_V3_DIMM
[50] KSI[0..7]
KSI[0..7]
KSI0 58
KSI0/STB#
LQFP128 ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7
73 NTC_V3_DIMM ADAPTER_ID
NTC_V3_DIMM [44]
HLZ SDV 0613 R10 2 1 100K_0402_5%
KSO[0..16] KSI1 59 78 CPU_PWRGD
+3VALW_R [50] KSO[0..16] KSI1/AFD# DAC2/TACH0B/GPJ2 CHG_MOD1 CPU_PWRGD [65]
KSI2 60 79
KSI2/INIT# DAC3/TACH1B/GPJ3 H_PROCHOT#_EC CHG_MOD1 [47]
C KSI3 61 DAC 80 C
KSI4 62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81 EC_RTCRST#_ON
KSI4 DAC5/RIG0#/GPJ5 change to CHG_MOD1 on GPJ3 by Bing 0717
RPE2 KSI5 63
1 4 EC_SMB_CK1 KSI6 64 KSI5 85 EC_ON_1.8V +5VALW
EC_SMB_DA1 KSI6 PS2CLK0/TMB0/CEC/GPF0 PBTN_OUT# EC_ON_1.8V [70]
2 3 KSI7 65 86
KSI7 PS2DAT0/TMB1/GPF1 PBTN_OUT# [16,42]
15P_0402_50V8J

15P_0402_50V8J

1 1 KSO0 36 87 EC_SMB_CK0
KSO0/PD0 SMCLK0/GPF2 EC_SMB_DA0 EC_SMB_CK0 [38] USB_ON#
2.2K_0404_4P2R_5% KSO1 37 Int. K/B PS2 88 RE15 1 2 100K_0402_5%
KSO1/PD1 SMDAT0/GPF3 EC_SMB_DA0 [38] Add SMBUS0 for RTS5400
C113

C112

@ @ KSO2 38 89 EC_TP_ON SYSON_VDDQ RE64 1 @ 2 100K_0402_5%


KSO2/PD2 Matrix PS2CLK2/GPF4 VCCIO_PG EC_TP_ON [50] HLZ SIV 0811
KSO3 39 90 VCCIO_PG [64]
2 2 KSO4 40 KSO3/PD3 PS2DAT2/GPF5
+3VS KSO5 41 KSO4/PD4 96 STATUS# +3VALW_R
KSO5/PD5 EXTERNAL SERIAL FLASH GPH3/ID3 STATUS# [47]
KSO6 42 97 CPUCORE_ON
KSO6/PD6 GPH4/ID4 ME_FLASH CPUCORE_ON [6,65]
RPE3 KSO7 43 98
EC_SMB_CK2 KSO7/PD7 GPH5/ID5 SYS_PWROK ME_FLASH [16]
1 4 KSO8 44 99
EC_SMB_DA2 KSO8/ACK# GPH6/ID6 SYS_PWROK [16]
2 3 KSO9 45 SUSP# RE18 1 @ 2 100K_0402_5%
KSO9/BUSY
15P_0402_50V8J

15P_0402_50V8J

1 1 KSO10 46 101 EC_SPI_CS0#


2.2K_0404_4P2R_5% KSO11 51 KSO10/PE FSCE# 102 EC_SPI_SI SUSP# RE19 1 2 100K_0402_5%
KSO11/ERR# FMOSI
CE30

C117

@ @ KSO12 52 SPI Flash ROM 103 EC_SPI_SO


+3VALW KSO13 53 KSO12/SLCT FMISO 105 EC_SPI_CLK SYSON RE21 1 2 100K_0402_5%
2 2 KSO14 54 KSO13 FSCK
KSO15 55 KSO14 CPUCORE_ON RE14 1 @ 2 100K_0402_5%
RPE4 KSO16 56 KSO15 108 ACIN#
2 3 EC_SMB_CK0 EC_PS2 57 KSO16/SMOSI/GPC3 AC_IN#/GPB0 109 LID_SW#
[54] EC_PS2 KSO17/SMISO/GPC5 UART LID_SW#/GPB1 LID_SW# [50]
1 4 EC_SMB_DA0

2.2K_0404_4P2R_5% ON/OFF 110 82 EC_MUTE#


[50] ON/OFF PWRSW/GPB3 EGAD/GPE1 EC_MUTE# [40]
EC_ON RE96 2 @ 1 0_0402_5%111 83 RE92 1 2 0_0402_5%
EC_SMB_CK1 XLP_OUT/GPB4 EGCS#/GPE2 CHG_MOD3 EC_ON [44,60,64]
115 84
[58,59,65] EC_SMB_CK1 EC_SMB_DA1 SMCLK1/GPC1 EGCLK/GPE3 CHG_MOD3 [47]
116
[58,59,65] EC_SMB_DA1 PECI_EC 117 SMDAT1/GPC2 PM_SLP_S4#
[6,14] EC_PECI RE24 1 2 33_0402_5% SM Bus 77 PM_SLP_S4# [16] change to CHG_MOD3 on GPE3 by Bing 0717
USB_CHG_EN 118 SMCLK2/PECI/GPF6 GPJ1 100 GPG2
[47] USB_CHG_EN EC_SMB_CK2 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2
94 GPIO 125 change SUSWARN# to ENBKL on GPG6 by Bing 0717
[16,27,44] EC_SMB_CK2 EC_SMB_DA2 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 AOAC_ON#
95 119 ENBKL
change to USB_CHG_EN on GPF7 by Bing 0717[16,27,44] EC_SMB_DA2 CTX1/SOUT1/SMDAT3/GPH2/ID2 DSR0#/GPG6 122 LAN_WAKE#
DTR1#/SBUSY/GPG1/ID7 113 BKOFF# RE30 1 2 0_0402_5% VGA_AC_DET
CRX0/GPC0 BKOFF# [35] VGA_AC_DET [27] Change R 30 to 0ohm jum
123 PCH_PWROK
CTX0/TMA0/GPB2 PM_SLP_S3# PCH_PWROK [16]
+3VL 112 18 Mount RE30 Reserve for VGA_AC_DET
VSTBY0 RI1#/GPD0 EC_ON_1V PM_SLP_S3# [16]
[50] NOVO# NOVO# 107 WAKE UP 21
B GPE4/BTN# RI2#/GPD1 EC_ON_1V [63] ADAPTER_ID B
76 SYSON CE31 1 2 .1U_0402_10V6-K
TACH2/GPJ0 48 EC_FAN2_SPEED SYSON [53] Delete EC_WF_MUTE#
EC_FAN2_SPEED [44]
TACH1A/TMA1/GPD7 47 EC_FAN1_SPEED EC_FAN1_SPEED HLZ SDV 0531
[44] SYSON CE13 1 2 .1U_0402_10V6-K EMC_NS@
USB_ON# 33 TACH0A/GPD6 19 RE76 1 2 0_0402_5%
[48,50] USB_ON# SYSON_VDDQ GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0 CAPS_LED# [50]
35 GPIO 20 RE77 1 2 0_0402_5%
EC_RSMRST#[61] SYSON_VDDQ
1 2 0_0201_5% EC_RSMRST#_R 93 RTS1#/GPE5 L80LLAT/GPE7 3 EC_ON_5V NUM_LED# [50]
[16,42] EC_RSMRST# CLKRUN#/GPH0/ID0 GPH7 EC_ON_5V [60]
RH848

RE29 1 2 0_0402_5% 2 Clear CMOS issue


[16,45] PCIE_WAKE# GPJ7
Clock
AC_PRESENT 128
+3VL [16] AC_PRESENT GPJ6/THERMTRIP_SHUTDOWN#
Delete 2nd RTCRST#
RE95 1 2 10K_0402_5% EC_ON HLZ SDV 0606
MIRROR@ RE34 1 2 0_0402_5% H_PROCHOT# [6,65]
[59] VR_HOT#
AVSS
VSS1

VSS2
VSS3
VSS4
VSS5

RE36 1 @ 2 10K_0402_5% BKOFF#


1

EC_SMB_CK1 PAD 1 @ QE1 D


1
IT1
RE38 2 1 100K_0402_5% LID_SW# EC_SMB_DA1 PAD 1 @ H_PROCHOT#_EC 2 CE14
IT2 PCH_RTCRST# [16]
1

27
49
91
104

75

PAD 1 @ G 47P_0402_50V8J
IT3
PAD 1 @ IT8226E-128-BX_LQFP128_14X14 @
IT4
1

PAD 1 @ 2N7002KW_SOT323-3 S 2 QE3 D


IT5
3

EC_RTCRST#_ON 2
RE40 1 2 100K_0402_5% BKOFF# G

KSI7 PAD 1 @ EC_AGND S 2N7002KW_SOT323-3


IT6
3
1

KSI6 PAD 1 @ @
IT7 PECI_EC
WRST# PAD 1 @ CE15 1 2 47P_0402_50V8J EMC_NS@ RE50
IT8
100K_0402_5%
BATT_TEMP CE16 1 2 100P_0402_50V8J EMC_NS@ @
For factory C flash +3VL
Unmount QE3,QE4,RE99,RE50 by
2

ACIN# CE17 1 2 100P_0402_50V8J EMC_NS@


same net name with PCH ON/OFF CE18 1 2 1U_0402_6.3V6K EMC_NS@ +3VS
Intel request
1

EC_SPI_CS0# RE45 1 2 0_0402_5%


SPI_CS0#_R [18] RE42
+3VALW_R EC_SPI_SI RE47 1 @ 2 0_0402_5% 1 100K_0402_5% +3VALW_R
SPI_SI_R0 [18] CE19
A A
EC_SPI_SO RE48 1 @ 2 0_0402_5% NOVO# C48 1 2 .01U_0402_16V7-K @ .1U_0402_10V6-K
SPI_SO_R0 [18]
2

GPG2 RE44 2 1 10K_0402_5% ACIN# RE94 1 2 0_0402_5%


EC_SPI_CLK PM_SLP_S3# 2 ACIN [59]
MIRROR@ RE49 2 @ 1 0_0402_5% CE29 1 2 .01U_0402_16V7-K @ RE5
GPG2 RE46 2 1 10K_0402_5% SPI_CLK_PCH_0 [18] 10K_0402_5%
@
NOMIRROR@ PM_SLP_S4# C135 1 2 .01U_0402_16V7-K @
Delete MOS
when mirror, GPG2 pull high
2

LAN_WAKE#
Reserved Cap HLZ SDV 0616 Reserved Cap HLZ SDV 0616 LAN_WAKE# [45,51]
when no mirror, GPG2 pull low EC_SPI_CS0# CE20 1 2 .01U_0402_16V7-K @
Security Classification LC Future Center Secret Data Title
EC_SPI_SI CE21 1 2 .01U_0402_16V7-K @

EC_SPI_SO CE22 1 2 .01U_0402_16V7-K @


Issued Date 2015/02/26 Deciphered Date 2016/02/26 ITE8371LQFP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
EC_SPI_CLK CE23 1 2 .01U_0402_16V7-K @ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 49 of 74
5 4 3 2 1
5 4 3 2 1

+3VS LED_KB_C

ON/OFF switch +3VL


+3VS TP_PWR_530P 1
D
No function field
2

1
JKB1 2 Q121
[49] LED_KB_PWM
R82 R10497 1 530P@ 2 0_0402_5% TP_PWR_530P R885 R90 G PJA138K_SOT23-3
100K_0402_5% 33 32 KB_PIN32 300_0402_5% 300_0402_5% S BL@
GND1 32
K/B Connector

2
KB_PIN31
.1U_0402_10V6-K

R899 1 2 0_0402_5% 34 31
GND2 31 30 R116 3
1
1

2
30
530P@
C10226

D15 @ 29 100K_0402_5%
NOVO# 2 29 28 PWR_NUM_LED BL@
[49] NOVO# 28 NUM_LED# KSI[0..7]
27
NUM_LED# [49] KSI[0..7] [49]

1
1 NOVO_BTN# 2 27 26 PWR_CAPS_LED
26 25 CAPS_LED# KSO[0..16]
25 CAPS_LED# [49] KSO[0..16] [49]
ON/OFF 1 2 R85 3 24 KSO15
24 23 KSO14 D23 AZ5725-01F.R7GR_DFN1006P2X2 KSO16 1 @ T11
0_0402_5% 23
@ BAT54CW_SOT323-3 22 KSO12
22 21 KSO10 1 2 EMC@ KSO9 R400 1 2 0_0402_5% KB_PIN32
@
J5 1 2 @ +3VL
TP CONN FOR 530P 21
20
20
19
KSO11
KSO6
1 2
KSI7 R418 1 @ 2 0_0402_5% KB_PIN31
JTP2 19 18 KSO8 D35 AZ5725-01F.R7GR_DFN1006P2X2
SHORT PADS TP_PWR_530P 1 18 17 KSO4 @
1 17
2

PCH_TP_CLK 2 16 KSO2 1 2 EMC@


D J6 1 2 @ R111 PCH_TP_DATA 3 2 16 15 KSO5 1 2 +5VS D
100K_0402_5% 4 3 15 14 KSO13
0.5A JKBL1
SHORT PADS R10527 1 53017@ 2 0_0402_5% 5 4 14 13 KSI0 1
+3VL 5 13 1
LID_SW# R10528 1 53017@ 2 0_0402_5% 6 12 KSI3 LED_KB_C 2
1

PCH_TP_INT 7 6 12 11 KSO1 R343 1 2 0_0603_5% LED_Power_C 3 2


ON/OFFBTN# R119 1 2 0_0402_5% ON/OFF EC_TP_ON 8 7 11 10 KSI2 BL@ 4 3
ON/OFF [49] 8 10 4

0.1U_0402_10V6K
9 KSI4
9

C316
@ 9 8 KSO3 2 5
10 GND1 8 7 KSI5 6 GND1
GND2 7 6 KSI6 GND2
6 5 KSO9 @
HIGHS_FC5AF081-2931H 5 4 KSI7 1 HIGHS_FC1AF041-1201H
4 3 KSI1 ME@
ME@ 3
PWR_LED1# 2 KSO0
2 1 KSO7
1

ON/OFFBTN# HIGHS_FC8AF321-3201H
AZ5123-01F.R7GR_DFN1006P2X2

ME@
1

1
1

D1 D4320
1
1

AZ5725-01F.R7GR_DFN1006P2X2 EMC_NS@ LED2


EMC@ [49,50] PWR_LED1#
PWR_LED1# Power LED 1 2 R9746 1 21/16W_82_1%_0402 +3VALW
B1931TX--05P-000314_WHITE
2

SW5 530@
530@
2

T4BJB16_4P
2

Power LED for 530PLED305


2

PWR_LED1# 1 2 R10518 1 21/16W_82_1%_0402 +3VALW


[49,50] PWR_LED1#
B1931TX--05P-000314_WHITE
530P@ 530P@

+3VS TP_PWR

R141 1 2 0_0402_5% TP_PWR


Right Side USB2.0 Port X 1 (USB/B) +USB_VCCB
Charger LED
.1U_0402_10V6-K

LED301 HIGHS_FC5AF201-2931H
1
C +3VALW R67 1 2 0_0402_5% 1 C
BATT_LOW_LED# 4 3 2 1
[49,50] BATT_LOW_LED# 2
R3001 3
PCH_TP_CLK 2 3
C114

+3VS R10448 1 2 2.2K_0201_5% 1 2 L14 4


R10449 1 2 2.2K_0201_5% PCH_TP_DATA USB20_P2 2 1 USB20_P2_CONN 5 4
BATT_CHG_LED# [19] USB20_P2 2 1 USB20_P2_CONN 5
1 2 150_0402_5% 6
[49,50] BATT_CHG_LED# USB20_N2_CONN 6
1 1 530@ 7
USB20_N2 3 4 USB20_N2_CONN 8 7
[19] USB20_N2 3 4 USB30_RX_N4 8
C1940 C1941 9
B2972UDBS05P-000114_AMBER-WHITE [15,50] USB30_RX_N4 USB30_RX_P4 9
220P_0402_50V7K 220P_0402_50V7K EXC24CH900U_4P 10
[15,50] USB30_RX_P4 10
EMC_NS@ 2 2 EMC_NS@ 530@ EMC_NS@ 11
USB30_TX_N4 12 11
[15,50] USB30_TX_N4 USB30_TX_P4 12
R66 1 2 0_0402_5% 13
[15,50] USB30_TX_P4 13
14
PWR_LED1# 15 14 22
16 15 GND2 21
+3VALW 16 GND1
17
LED306 18 17
PCH_TP_CLK +3VALW NOVO_BTN# 19 18
19
C116

100P_0201_25V8J
C115

100P_0201_25V8J

BATT_LOW_LED# 1 20
PCH_TP_DATA [49,50] BATT_LOW_LED# R10521 20
1 1
TP/B Connector 2 1 2
USB3.1 PORT x1
JP1 ME@
1

@ @
BATT_CHG_LED# 3 1K_0402_5%
AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

1
1

2 2 [49,50] BATT_CHG_LED# C1942


530P@
D4317 D4318 .1U_0402_10V6-K Low Active 1.8A
JTP1 B2102UDBS05P-000133_WHI-AMB 530P@ +5VALW +USB_VCCB
TP_PWR 1 2
1 530P@
2

PCH_TP_CLK 2 U2
[20] PCH_TP_CLK PCH_TP_DATA 2
3 5 1
[20] PCH_TP_DATA
2

4 3 IN OUT
EMC_NS@ EMC_NS@ 4 BATT_LOW_LED#
R10441 1 2 0_0201_5% 5 2
[20] PCH_TP_INT 5 GND
For EMC 6 2
[49] EC_TP_ON 6 BATT_CHG_LED# USB_OC1#
7 C58 4 3
G1 ENB OCB USB_OC1# [19]
2

2
10K_0201_5%

8 1U_0402_16V6K
G2
RG50

G517E2T11U_SOT23-5
AZ5123-01F.R7GR_DFN1006P2X2

1 1
@ RG49 CVILU_CF31061D0R4-10-NH_6P C61
10K_0201_5% ME@ 1000P_0402_50V7K
AZ5123-01F.R7GR_DFN1006P2X2

@
1

2
D13 D14 USB_ON#
1

[48,49] USB_ON#
EMC_NS@
+3VS +3VS
2

EMC_NS@
2

B B

+USB_VCCB

Nationz TPM Nuvoton TPM JP5


1
2 1
3 2
1. Add R93 for NationZ TPM R626 Stuff NC 4 3
4
5
2. Add R94 & +3VALW for Nuvoton TPM USB20_P2_CONN 6 5
6
USB20_N2_CONN
3. Add R163 PD & R185 for PM_CLKRUN# of Nuvoton TPM JTP4
7
8 7
8
HLZ SIT 0920 R93 Stuff NC ON/OFFBTN# 1
2 1 [15,50] USB30_RX_N4
USB30_RX_N4
USB30_RX_P4
9
10 9
2 [15,50] USB30_RX_P4 10
3 11
PWR_LED1# 4 3 USB30_TX_N4 12 11
4 [15,50] USB30_TX_N4 USB30_TX_P4 12
+3VALW 5 13
5 [15,50] USB30_TX_P4 13
R94 NC Stuff 6 14
6 7 PWR_LED1# 15 14
G1 8 16 15
G2 +3VALW 16
17
TPM CVILU_CF31061D0R4-10-NH_6P 18 17
0.5A ME@ NOVO_BTN# 19
20
18
19
PCH_RGBKB_SCL 21 20
+3VS +3VS_TPM [20] PCH_RGBKB_SCL PCH_RGBKB_SDA 21
22
[20] PCH_RGBKB_SDA 22
23
RGB_KB_INT 24 23
[18] RGB_KB_INT RGB_PWR_EN 24
R227 1 TPM@ 2 0_0603_5% 25
[49] RGB_PWR_EN 25
1 1 1 26
27 26
C176 C177 C178 28 27
.1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K 29 28 32
2 2 2 +5VS 29 GND2
TPM@ TPM@ TPM@ 30 31
30 GND1

HIGHS_FC5AF301-2931H
ME@

+3VS_TPM

UTPM1
for Nationz TPM
1 24
A 2 NC_1 VDD3 10 A
3 NC_2 VDD1
NC_3 for Nationz TPM
R104051 TPMZ@ 2 0_0402_5% 7 28 R626 1 TPMZ@ 2 10K_0402_5%
PP LPCPD# 27
SERIRQ SERIRQ [15,49]
6 26 1
9 NC_4
NC_7
LAD0
LAD1
23
22
LPC_AD0
LPC_AD1
[15,49]
[15,49] Hall Sensor C1943
LFRAME# LPC_FRAME# [15,49] 100P_0402_50V8J
4 20
GND_1 LAD2 LPC_AD2 [15,49] 2 EMC@
11 17
+3VALW GND_2 LAD3 LPC_AD3 [15,49] U5
18
GND_3 25 +3VS_TPM 1
GND_4 1 GND
R104061 TPMN@ 2 0_0603_5% 5 21 CLK_PCI_TPM [15]
8 NC_5 LCLK 19 C1944 3 LID_SW#
NC_6 VDD2 OUTPUT LID_SW# [49]
12 15 R185 1 @ 2 0_0402_5% 0.01UF_0402_25V7-K
NC_8 CLK_RUN# PM_CLKRUN# [16] EMC@ 2
for Nuvoton TPM 13
NC_9
2

14 16 R127 1 TPM@ 2 0_0402_5% PLT_RST# PLT_RST# Reserved


[18,27,45,49,51] for Nuvoton TPM +3VL R1 1 2 0_0402_5% +VCC_LID 2
NC_10 LRESET# R10404 VCC
Security Classification LC Future Center Secret Data Title
0_0402_5% AH9247-W-7_SC59-3
Z32H320TC-LPC-T28-LT1_TSSOP28
TPM@
Issued Date 2015/02/26 Deciphered Date 2016/02/26 KBD/PWR/IO/LED/TP Conn.
1

TPM@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 50 of 74
5 4 3 2 1
5 4 3 2 1

+3VALW TO +3VALW_LAN
+3VALW_LAN rising t i me ( 10 %~90 %):
+3VALW +3VALW_LAN
0.5ms <s pec< 10 0m
s +3VALW_LAN +LAN_VDDREG
Need short
JL1 1 2 @ width : 40 mils RL7 1 2 0_0603_5% width : 40 mils
1 2
JUMP_43X79 @
1 1
.1U_0402_10V6-K

.1U_0402_10V6-K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

CL10 CL11
D D
1 1 1 1 4.7U_0603_6.3V6K .1U_0402_10V6-K
CL35 CL5 CL6 CL7 EMC@
+3VALW LP2301ALT1G_SOT23-3 2 2

2 2 2 2
S

Q182 3 1 @
0.01U_0201_10V6K
1

1 1
RL2 CL8 CL9 EMC@ EMC@
G
2

100K_0402_5% 0.1U_0201_6.3V6-K
@ @ @
2 2 +3VALW_LAN
Close to Pin11 Close to Pin32
2

LAN_PWR_ON# RL3 1 @ 2
[20] LAN_PWR_ON#
47K_0402_5%
Close to Pin11 Close to Pin32

2
RL19
10K_0402_5%
@

1
LAN_CLKREQ#_R RL18 1 2 0_0402_5%
LAN_CLKREQ# [17]
+3VALW_LAN @
UL1
2

RL27
10K_0402_5%
@ 33
+3VALW_LAN 32 GND 16 CLK_PCIE_LAN#
C C
CLK_PCIE_LAN# [17]
1

RL8 1 2 RSET_LAN 31 AVDD33_2 REFCLK_N 15 CLK_PCIE_LAN


PCIE_WAKE#_R +LAN_VDD10 RSET REFCLK_P PCIE_PTX_C_DRX_N14 CLK_PCIE_LAN [17]
[45,49] LAN_WAKE# RL28 1 2 0_0402_5% 2.49K_0402_1% 30 14
LAN_XTALO AVDD10 HSIN PCIE_PTX_C_DRX_P14 PCIE_PTX_C_DRX_N14 [14]
29 13
LAN_XTALI CKXTAL2 HSIP LAN_CLKREQ#_R PCIE_PTX_C_DRX_P14 [14]
@ 28 12
TL3 @ 1 27 CKXTAL1 CLKREQB 11 +3VALW_LAN
LAN_PWR_ON# RL121 @ 2 LAN_DISABLE# 26 LED0 AVDD33_1 10 LAN_MDI3-
LED1/GPO MDIN3 LAN_MDI3+ LAN_MDI3- [52]
0_0402_5% TL4 @ 1 25 9
+3VS +LAN_REGOUT LED2 MDIP3 +LAN_VDD10 LAN_MDI3+ [52]
24 8
+LAN_VDDREG 23 REGOUT AVDD10_2 7 LAN_MDI2-
+LAN_VDD10 VDDREG MDIN2 LAN_MDI2+ LAN_MDI2- [52]
22 6
DVDD10 MDIP2 LAN_MDI2+ [52]
1

PCIE_WAKE#_R 21 5 LAN_MDI1-
LANWAKEB MDIN1 LAN_MDI1+ LAN_MDI1- [52]
RL9 ISOLATE# 20 4
PLT_RST# ISOLATEB MDIP1 +LAN_VDD10 LAN_MDI1+ [52]
1K_0402_1% 19 3
[18,27,45,49,50] PLT_RST# PCIE_PRX_C_DTX_N1418 PERSTB AVDD10_1 LAN_MDI0-
CL12 1 2 .1U_0402_10V6-K 2
[14] PCIE_PRX_DTX_N14 PCIE_PRX_C_DTX_P14 17 HSON MDIN0 LAN_MDI0+ LAN_MDI0- [52]
CL13 1 2 .1U_0402_10V6-K 1
[14] PCIE_PRX_DTX_P14 LAN_MDI0+ [52]
2

HSOP MDIP0

ISOLATE# RL26 1 @ 2 0_0402_5% LAN_PWR_ON#


CL12 close to Pin18
CL13 close to Pin17
1

RL11 PLT_RST#
15K_0402_5%
@ RTL8111H-CG_QFN32_4X4
1
CL1 @
2

1000P_0402_50V7K
2

B B

LAN_XTALI
YL1 LAN_XTALO
8111H@ +LAN_VDD10
1 4 RL25 1 2 0_0805_5%
OSC1 GND2
2 3 60mil 60mil
GND1 OSC2 +LAN_REGOUT LL1 1 2
1 1 2.2UH_NLC252018T-2R2J-N_5%
CL15 CL14 8111GUL@ 1 1 1 1 1 1 1 1
12P_0402_50V8-J 25MHZ_10PF_7V25000014 12P_0402_50V8-J CL36 CL37
Layout Note: LL1 must be 4.7U_0603_6.3V6K .1U_0402_10V6-K CL17 CL18 CL19 CL20 CL21 CL22
2 2 EMC@ EMC@ .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K .1U_0402_10V6-K 1U_0402_6.3V6K .1U_0402_10V6-K
within 200mil to Pin24, 2 2 2 2 2 2 2 @ 2 @
CL36,CL37 must be within
200mil to LL1
+LAN_REGOUT: Width =60mil Close to Pin3, 8, 22, 30 Close to Pin22(Reserved)

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2014/10/22 Deciphered Date 2014/10/22 LAN_RTL8111
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 51 of 74

5 4 3 2 1
5 4 3 2 1

DL1/DL2 TL1
1'S PN:SC300005900 : 24 LAN_MDO3-
LAN_MDI3- 1 T /B MX1+
Place Close to TL1 [51] LAN_MDI3- TD1+

23 LAN_MDO3+
MX1-
LAN_MDI3+ 2
[51] LAN_MDI3+ TD1-
TDCT 3 22
TCT1 T /A MCT1
DL1
D LAN_MDI3- LAN_MDI2- D
4 3 4 21
I/O3 I/O2 TCT2 : MCT2
T /B 20 LAN_MDO2-
LAN_MDI2- 5 MX2+
[51] LAN_MDI2- TD2+
5 2
VDD GND
19 LAN_MDO2+
LAN_MDI2+ 6 MX2-
LAN_MDI3+ LAN_MDI2+ [51] LAN_MDI2+ TD2-
6 1
I/O4 I/O1
AZ1215-04S.R7G_SOT23-6L-6 T /A
EMC_8111H@ :
18 LAN_MDO1-
T /B MX3+
LAN_MDI1- 7
[51] LAN_MDI1- TD3+

17 LAN_MDO1+
MX3-
LAN_MDI1+ 8
[51] LAN_MDI1+ TD3-
DL2 9 16
LAN_MDI1- 4 3 LAN_MDI0- TCT3 T /A MCT3
I/O3 I/O2
10 15
TCT4 : MCT4
T /B 14 LAN_MDO0-
5 2 LAN_MDI0- 11 MX4+
VDD GND [51] LAN_MDI0- TD4+
2
LAN_MDI1+ 6 1 LAN_MDI0+ CL24 13 LAN_MDO0+
I/O4 I/O1 LAN_MDI0+ 12 MX4-
0.01U_0201_25V6-K [51] LAN_MDI0+ TD4-
AZ1215-04S.R7G_SOT23-6L-6 1
EMC@
EMC_8111H@
T /A

BOTH_NA0069R-LF
C C

1
RL17
20_0603_5%

1
DL3

1
2
BS4200N-C-LV_SMB-F2
EMC@

2
2
1 1
CL32 CL25
68P_0402_50V8J 1000P_1206_2KV7-K
EMC@ EMC_NS@
2 2

CHASSIS1_GND

B B

RL14 1 2 0_0402_5%

RL15 1 @ 2 0_0402_5%

RL16 1 @ 2 0_0402_5%

RL24 1 @ 2 0_0402_5%

@ JRJ1

Reserve for MI go rural solution


CHASSIS1_GND LAN_MDO3- J8
BI_DD-
LAN_MDO3+ J7
BI_DD+
LAN_MDO1- J6
BI_DB-
LAN_MDO2- J5
BI_DC-
LAN_MDO2+ J4
BI_DC+
LAN_MDO1+ J3
BI_DB+
LAN_MDO0- J2
BI_DA-
LAN_MDO0+ J1 GND1
BI_DA+ GND_1
GND2
GND_2
LOTES_AJKM0044-P002A11
ME@
CHASSIS1_GND

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2014/10/22 Deciphered Date 2014/10/22 LAN_Transformer
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 52 of 74
5 4 3 2 1
A B C D E

+1.8VALW to +1.8VS_AON
+5VALW to +5VS
+5VALW +1.8VALW +1.8VS_AON
No function field +5VLP +5VALW

5VS_CT1 +0.6VS
1
1000P_0402_50V7K

C121 +5VS 1
U56

1
C125

1U_0402_16V6K R161 R157


2 1 14 100K_0402_5% @ 100K_0402_5% R159
IN1_1 OUT1_2 1 Q5811
Change net to SUSP# for PWR sequence 2 13 C216 47_0603_5% AON7400A_DFN8-5
IN1_2 OUT1_1 .1U_0402_10V6-K 2 @ +5VALW V20B+
2

SUSP# R263 1 2 0_0402_5% 3 12 5VS_CT1 @ 1

2
EN1 CT1 2 S1

0.1U_0402_25V6
SUSP 5 2
[36,40,43] SUSP D S2

1
4 11 3 1
VBIAS GND S3
1

1
D RV1114 @ CV451 1

G
R264 1 2 0_0402_5% 5 10 3VS_CT2 +3VS 2 SUSP 47K_0402_5% 0.01U_0402_25V7K RV1116 CV448
EN2 CT2 3VS_CT2

CV452
+3VALW G Q18 RV1113 OPT@ @ 470_0603_5% 10U_0603_6.3V6M

4
1

2
2200P_0402_25V7-K

6 9 D 2N7002KW_SOT323-3 47K_0402_5% OPT@ @ @


1

2
1 7 IN2_1 OUT2_2 8 SUSP# 2 S @ OPT@ RV1119 2 1
1 2
3

2
C123 IN2_2 OUT2_1
C124

C215 G Q6 1 2
1

2
0.01UF_0402_25V7-K 15 .1U_0402_10V6-K 2N7002KW_SOT323-3 1K_0402_5%
2 Thermal Pad S

0.1U_0402_25V6
C122 @ OPT@
@
3

3
1U_0402_10V6K 2 1 QC25B D
G2898KD1U_TDFN14P_2X3

1
2

L2N7002KDW1T1G_SOT363-6
+1.8VS_AON_EN# 5
G

OPT@
2
6

CV450
QC25A D OPT@ S RV1121

4
L2N7002KDW1T1G_SOT363-6
RV1115 1 2 0_0402_5% 2 210K_0402_1%
[19,27,28] PXS_PWREN G OPT@ OPT@

1
D

2
1
S +1.8VS_AON_EN# 2 QV23

1
1
CV449 RV1117 G L2N7002KWT1G_SOT323-3
0.1U_0402_25V6 100K_0402_5% @
@ @ S

3
2
LP 30 ALT G
Rds 0mohm @
VGS 5V ID A
VGS th V Ma

+3VALW Need short +3VALW_PCH

J7
1 2
1 2
+5VALW
JUMP_43X79
1 1
@
1

C327 C328
LP2301ALT1G_SOT23-3 1U_0402_10V6K 1U_0402_10V6K
R155 2@ 2@
S

100K_0402_5% 3 1
2 @ 2
2

1 Q29 1
PCH_PWR_EN# @
G
2

C129 C130
change EN to PCH_PWR_EN by Bing 0717 .1U_0402_10V6-K 0.01U_0402_25V7K
1

D 2@ 2@
PCH_PWR_EN 2
[49] PCH_PWR_EN
G R163 1 @ 2 PCH_PWR_EN#_R
0_0402_5%
S Q30
3
1

L2N7002KWT1G_SOT323-3 1
R162 @ R87
100K_0402_5% 100K_0402_5% C131
@ @ .1U_0402_10V6-K
2@
2

+1.05VALW
1U_0402_16V6K

1 VCCSTG_CT2
1000P_0402_50V7K
C10168

VCCST 1
U126
C10165

2
0mA
1 14 1
2 IN1_1 OUT1_2 13 C10166
IN1_2 OUT1_1 .1U_0402_10V6-K 2
R10424 1 2 0_0402_5% 3 12 VCCST_CT1 @
[49,53,62] SYSON EN1 CT1 2
+5VALW 4 11
VBIAS GND
R10425 1 2 0_0402_5% 5 10 VCCSTG_CT2 VCCSTG
[49,61,64] SUSP# EN2 CT2 VCCST_CT1
+1.05VALW
1000P_0402_50V7K

6 9 0mA
R104571 @ 2 7 IN2_1 OUT2_2 8
[49,53,62] SYSON IN2_2 OUT2_1 1 1
C10170
1U_0402_10V6K

100K_0402_5% 1 C10164
C10169

3
1 15 .1U_0402_10V6-K 3
Thermal Pad @
C10167 @ 2 2
2 G2898KD1U_TDFN14P_2X3
0.01UF_0402_25V7-K
2

4 4

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 DC V TO VS INTERFACE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 53 of 74
A B C D E
5 4 3 2 1

+3VS

D D
2

R10468
2.2K_0201_5%
sensor@ 1 R10476 1 sensor@ 2 470_0402_5% ANT1
1

C10214
R10484 1 sensor@ 2 0_0402_5% 10P_0201_25V8G
2 sensor@
U132
@ 1 R10477 1 @ 2 0_0402_5% 1 6
PAD IT38 IO1/SCL Cx
2 5 R10475 1 sensor@ 2 47_0402_5% +3VS
VSS VDDHI
@ 1 R10478 1 @ 2 0_0402_5% 3 4
PAD IT39 IO2/SDA VREG 1 1
1U_0201_6.3V6-M

xxxxxxxxxxx C10212 C10208


sensor@ 1 1 100P_0201_25V8J 1U_0201_6.3V6-M
2 2
C10209
sensor@

sensor@ sensor@
C10216
100P_0201_25V8J
2 2 sensor@

+3VS
2

R10486
2.2K_0201_5%
C sensor@ 1 R10481 1 sensor@ 2 470_0402_5% ANT2 C
1

C10215
EC_PS2 R10485 1 sensor@ 2 0_0402_5% 10P_0201_25V8G
[49] EC_PS2 2 sensor@
U133
@ 1 R10482 1 @ 2 0_0402_5% 1 6
PAD IT40 IO1/SCL Cx
2 5 R10480 1 sensor@ 2 47_0402_5% +3VS
VSS VDDHI
@ 1 R10483 1 @ 2 0_0402_5% 3 4
PAD IT41 IO2/SDA VREG 1 1
1U_0201_6.3V6-M

xxxxxxxxxxx C10213 C10210


sensor@ 1 1 100P_0201_25V8J 1U_0201_6.3V6-M
2 2
C10211
sensor@

sensor@ sensor@
C10217
100P_0201_25V8J
2 2 sensor@

JP2
ANT1 1 3
1 GND2

2 4
GND1 GND3

I-PEX_20449-001E-03
ME@

B B

JP3
ANT2 1 3
1 GND2

2 4
GND1 GND3

I-PEX_20449-001E-03
ME@

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 Virtual symbol
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 54 of 74
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 Virtual symbol
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 55 of 74
5 4 3 2 1
5 4 3 2 1

H1 H3 H5 NH6 H7
HOLEA HOLEA HOLEA HOLEA HOLEA
1

PAD_CT8P0B6P0D2P3 PAD_CT8P0D2P5 PAD_CT8P0B6P0D2P3 PAD_C5P0D5P0N PAD_ST8P0CB6P0D2P3


D D

H8 H9 H10 NH11 H12 H13 H14


HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

PAD_ST8P0D2P5

PAD_ST8P0D2P5 PAD_ST8P0CB8P0D2P5 PAD_O2P5X3P1D2P5X3P1N PAD_ST8P0D2P5 PAD_ST8P0D2P5 PAD_CB6P0D2P3

CHASSIS1_GND

NH15 NH16 NH17 NH18 NH19 NH20 NH21 H22 NH23 NH24
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

PAD_C4P0D4P0N PAD_C4P0D4P0N PAD_C4P0D4P0N PAD_C4P0D4P0N PAD_C4P0D4P0N PAD_C4P0D4P0N PAD_C4P0D4P0N PAD_C8P0D4P5 PAD_C2P5D2P5N PAD_O2P5X3P1D2P5X3P1N

C C
SH9 ME@ SH13 ME@ SH16 ME@

1 1 1
1 1 1

SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P


SH10 ME@ SH14 ME@

1 1 SH17 ME@
1 1
1
1
SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P

SH11 SHIELDING_SUL-35A2M_9P2X3P3_1P
ME@
SH15 ME@
1
1 1
1

SHIELDING_SUL-35A2M_9P2X3P3_1P
SHIELDING_SUL-35A2M_9P2X3P3_1P

SH12 ME@

1
1

SHIELDING_SUL-35A2M_9P2X3P3_1P

B SO-DIMM Shielding B

FD1 FD2 FD3 FD4 FD5 FD6


1

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EY515
Date: Tuesday, March 20, 2018 Sheet 56 of 74
5 4 3 2 1
5 4 3 2 1

B+ +5VLP/ 100mA
Richtek Silergy
Adaptor RT6585B +5VALW/10A SY8032 +1.0VGS/2A
D
C_ _5V Switch Mode Converter
D

FOR SYS ALW_PWRGD V0_MAI _


135W/20V PG D FOR GPU PG D
Page 0
Page 70
C_ +3VLP/ 100mA

+3VALW/ 8A GMT
G9661 +2.5V/600mA
SYS LDO
FOR DDR PG D

Richtek Page
+1.2V/10A
RT8231
Switch Mode +0.6VS/1A
SYS S5 FOR DDR Silergy
SM_PG_CTRL S3 Page PG D +1.8VALW/3.4A
SY8033
C_ _ V Converter
FOR GPU PG D

Silergy Page 70
TI SY8286 +1.05VALW/ 6A
C
BQ24780SRUYR Converter C

C_ _ V FOR PCH PG D
Battery Charger Page 3

Switch Mode
Page 59 AOS
AOZ2264 FBVDDQ/ 11A
Converter
VRAM_VDDQ_ADJ PG D VDDQPWR K
FOR GPU
Page 9
SMBus

Silergy
SY8286 VCCIO/ 6A
Converter
SUSP# FOR CPU PG D VCCI _PG
Page

MPS VCC_CORE/80A/124A

B
MP2949 VCCGT/25A/32A B
Switch Mode
FOR CPU Core VCCSA/10A
CPUC R _
Page 5- PG D
CPU_PWRGD

Battery Richtek
Li-ion RT8813D NVVDD/59A/124A
3S1P/52.5WH Switch Mode
VVDD_ FOR GPU NVVDD PG D GPU_PWRGD
Page 7

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 Power Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DZ510/DY512
Date: Tuesday, March 20, 2018 Sheet 57 of 74
5 4 3 2 1
5 4 3 2 1

PJ101@
2 1
2 1

JUMP_43X118 +3VL
PL101 EMC@
HCB2012KF-121T50_0805
VIN

1
1 2
D
JDCIN1
PL102
EMC@ PR101 @
0_0603_5%
VCCRTC D
PF101
1 HCB2012KF-121T50_0805
GND_1 2 APDIN 1 2 APDIN1 1 2
RTC_VCC

2
POWER_1 3
DETECT(ID) PR103 PR102 PD101
4 12A_24V_F1206HB12V024T/M 47K_0402_1%
POWER_2
0.1U_0402_25V6

5 2 1VCCRTC_D_R 2 1 VCCRTC_D 3
GND_2
0.1U_0402_25V6

EMC_NS@
1000P_0402_50V7K

1000P_0402_50V7K

6
GND_3
EMC_NS@
PC101 EMC@

7 EMC@ @ 1
GND_4 0_0603_5%
1

1
PC102

PC103

1 2@ RTC_VCC_R 2
HIGHS_PJSSS56-B4000-1H ADAPTER_ID [49,59]
JRTC1
2

PC104

ME@ PR104
BAT54CW_SOT323-3
1K_0603_5%
1
1 2
2

1
3 PC105
GND1 4
GND2 1U_0402_10V6K
@

2
HIGHS_WS33021-S0351-HF
ME@
C C
GND4 16
GND3 15
GND2 14
GND1
12
13
12
VMB BATT+
11 11 PL104 EMC@
10 10 HCB2012KF-121T50_0805
9 9 1 2
8 8 EC_SMCA
7 7 EC_SMDA
6 PL105 EMC@
6 5 HCB2012KF-121T50_0805
5
3

4 PC106 1 2 PC107
4 3 1000P_0402_50V7K 0.01U_0402_25V7K
3 2 EMC@ EMC@
2

2 1
1
1

100_0402_1%

JBATT1
PR105

SUYIN_125022HB012M200ZL
1

100_0402_1%

ME@
PR106

2
2

B PD103 EC_SMB_CK1 [49,59,65] B


AZC199-02S.R7G_SOT23-3
EMC_NS@
EC_SMB_DA1 [49,59,65]

PR107 1 2 100K_0402_1% +3VALW

BATT_TEMP_IN 1 2
BATT_TEMP [49,59]A/D
PR108
10K_0402_5%

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-DCIN/BATT/RTC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom DZ510/DY512 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, March 20, 2018 Sheet 58 of 74
5 4 3 2 1
5 4 3 2 1

PQ201 PQ202
AON6366E_DFN8-5 AON6414AL_DFN8-5
P2 PR201 V20B+
VIN 1 1 P3 0.01_1206_1%
2 2 PJ201@
3 3 5 2 1 1 4
2 1
2 3
10U_0805_25V6K

JUMP_43X118 10U_0805_25V6K
EMC_NS@

EMC_NS@
4

4
1

D D
PC203

PC204
1

PC202
5

PC201 PR202 0.022U_0402_25V7K


2

4.7_0603_5%
2

470P_0402_50V7K

5
2

PQ203
AON6414AL_DFN8-5
1 2

PC205 780s_BATDRV 4
1

PC206 0.1U_0402_25V6

1
0.1U_0402_25V6 PC207
0.1U_0402_25V6
2

1
2

3
2
1
1
PR203
499K_0402_1% PC208
VIN BATT+ 0.01U_0402_25V7K

2
2
780s_ACDRV_R

PD201 V20B+
BAT54CW_SOT323-3
1780s_VCC_R
1

0.1U_0402_25V6

10U_0805_25V6K

10U_0805_25V6K
VIN
1

2
EMC@
4.02K_0603_1%

4.02K_0603_1%

PC211
ACN
ACP
PR206

PR207

PC212
BQ24780S_VDD

PC209
2

1
1

5
PR209
2

PR208 PC213 10_1206_5% PQ205

D
6.2K_0603_1% 39K_0603_1% 1U_0603_25V6K AON7408L_DFN8-5
ACP

ACN

C 1 2 C
2

PR210 1 2 780s_VCC 28 24 1 2
2

VCC REGN 2.2U_0603_10V6-K PC214 4


2 1 780s_ACDET 6 PC216 G
PC215 ACDET 0.047U_0603_16V7K

S3
S2
S1
0.01U_0402_25V7K 25 780s_BS
1 2780s_BS_R
2 1
BTST PR211 PR213
3 BATT+
2
1
2.2_0603_5% 0.01_1206_1%
780s_CMSRC 3 26 780s_HG PL201
CMSRC HIDRV 1 2 1 4
780s_ACDRV 4 4.7UH_PCMB063T-4R7MS_5.5A_20%
ACDRV 2 3
5

0.1U_0402_25V6
10U_0805_25V6K

10U_0805_25V6K
27 780s_LX
PHASE

EMC@
@ PR216
D

PC218
PC221

PC217
PR215 1 2 0_0402_5% 780s_ACOK 5 PQ206 4.7_0805_5%
[49] ACIN @ ACOK PU201 AON7408L_DFN8-5 EMC_NS@
PR217 1 2 0_0402_5% 780s_SDA 11
2

2
[49,58] EC_SMB_DA1 SDA 23 780s_LG 4
780s_SN

@ LODRV G
PR218 1 2 0_0402_5% 780s_SCL 12 22
S3
S2
S1

SCL GND
1

[49,58] EC_SMB_CK1
@ PC222
3
2
1

780s_IADP

0.1U_0402_25V6

0.1U_0402_25V6
[49] ADP_I
PR219 1 2 0_0402_5% 7 29 1000P_0402_50V9-J
2

@ IADP PAD
EMC_NS@

1
PC223

PC224
PR220 1 2 0_0402_5% 780s_IDCHG 8 18 780s_BATDRV
[49] BATT_I IDCHG BATDRV
100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

@
PR221 1 2 0_0402_5% 780s_PMON 9
[49,65] PSYS

2
PMON 17 780s_BATSRC 1 2 780s_BATSRC_R
BATSRC PR222 10_0603_5%
20 780s_SRP 1 2 780s_SRP_R
A D PR 3 dele PR 950 PSYS RC 10 SRP PR224 10_0603_5%
[49] VR_HOT# PROCHOT#
PR 3 when Psys 35W V sys 35V
2

1
1

PR231 13 PC228
disable CPU ready VR system ower Consum tion Function 10K_0402_1%
CMPIN
0.1U_0402_25V6
2
BATPRES#
TB_STAT#
PC225

PC226

PC227

14
2

CMPOUT 19 780s_SRN 1 2 780s_SRN_R


1

780s_ILIM21 SRN PR225 10_0603_5%


ILIM
2

B B
PR226
780s_TB#16

15

0_0402_5% BQ24780SRUYR_QFN28_4X4

+3VALW
1

1 2 780s_ILIM_R 1 2
+3VALW BATT_TEMP [49,58]
PR227 PR228
1

143K_0402_1% 32.4K_0402_1%
1

PR230
PC229 100K_0402_1%
0.1U_0402_25V6
V20B+
2

IchargeLIM 7A
1

IDischargeLIM 0A
PR229
1000P_0402_25V7-K

1000P_0402_25V7-K

1000P_0402_25V7-K

1000P_0402_25V7-K

1000P_0402_25V7-K
0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

750_0603_1%
2

1
PC301

PC302

PC303

PC304

PC305

PC306

PC307

PC308

PC309

PC310
2

ADAPTER_ID [49,58]
680P_0402_50V7K

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
AZ5123-01F.R7GR_DFN1006P2X2
1
0.1U_0402_25V6

@
1
1

1
PC230

PC231

PD203

@
A A
2

2
2

Security Classification LC Future Center Secret Data Title


Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-charger
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom DY520 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, March 20, 2018 Sheet 59 of 74
5 4 3 2 1
5 4 3 2 1

D D

3V5V_VIN
PJ603
+5VLP 2 1
+3VLP 2 1 +3VL 1A
24K_0402_1%
0.1U_0402_25V7-K

JUMP_43X39
62K_0402_1%

@
4.7U_0603_6.3V6K
1

3V5V_VIN
PC602

4.7U_0603_6.3V6K
2

0_0603_5%

V20B+
1

1
PC601

PR602

PC603

3V5V_VIN
2

PJ604
2

2 1
+3VALW
1

2 1
PR604

@
+3V5V_CS22

+3V5V_CS12
PR601

JUMP_43X118
0.1U_0402_25V6

+5V_LDO
10U_0805_25V6K

10U_0805_25V6K

@ Vout 5V+-5%
1

0.1U_0402_25V6
EMC_NS@

PC609

PC610

PC611

10U_0805_25V6K

10U_0805_25V6K
+3VLP

1
Vset 5 0 V+- 5%

PC607
PC605

PC606
PR605

EMC_NS@
C 100K_0402_1% C
FSW 00KHz
2

Vout 3 3V+-5%

2
TDC 0A CP A
12

13
1

Vset 3 3V+- 5%
5

AON7506_DFN8-5
VP Vout 3%
VIN

CS2

CS1

LDO5

LDO3

FSW 75KHz 21
AON7408L_DFN8-5

TDC A CP 3A [16,62] ALW_PWRGD


ALW_PWRGD 7
PGOOD
GND UVP Vout 5 %
PQ601

PQ603

VP Vout 3% 4 +3V_UG 10 UGATE1


16 +5V_UG
PR606 PC614
4
G
UVP Vout 5 % G PC613 PR607 UGATE2
PU601 2.2_0603_5% 0.1U_0603_25V7K
S3
S2
S1

0.1U_0603_25V7K 2.2_0603_5% 17 +5V_BST1 2 1 2 1.5UH_PCME064T-1R5MS_12A_20%


S1
S2
S3

1.5UH_PCMB063T-1R5MS_10A_20% 1 2 1 2 +3V_BST9 BOOT1


PL601 +5VALW
3
2
1

BOOT2
+3VALW PL602
1
2
3

18 +5V_LX 1 2
1 2 +3V_LX 8
PHASE2
PHASE1
10A
5

5
330P_0402_50V7K

RT6585BGQW_WQFN20_3x3 15 +5V_LG
LGATE1
2
680K_0402_1%

+3V_LG 11
AON7408L_DFN8-5

PK6D0BA_DFN8-5
D

LGATE2
1

14 PR608
BYP1
220U_B2_6.3VM_R25M

1
22U_0603_6.3V6-M

22U_0603_6.3V6-M
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

PC633

PR619

PR612
VCLK

PR609 4.7_0805_5%
EN2

EN1
FB2

FB1
PQ602

PQ604

1 4.7_0805_5% EMC_NS@
1

0.1U_0402_25V6

0.1U_0402_25V6
PC627

PC626

22U_0603_6.3V6-M
PC624 @
PC632

PC631

PC630

PC629

PC628

PC625

4 4 1
2

2
PC618

+
13K_0402_1%
@

220U_6.3V_M
2

20

1+3V5V_CLK 19

2
2

1
PC617

PC620
+

PC616
EMC_NS@
S1
S2
S3
2

PR610

+5V_FB

2
EC_ON_3V_R

EC_ON_5V_R
1

1
2
3

3
2
1

2
1

1 2
1

PC619 30K_0402_1%
1

PC621 1000P_0402_50V9-J
2
1

200_0402_1%
PC634

1000P_0402_50V9-J EMC_NS@
2

PR611

EMC_NS@
@

0.01U_0402_25V7K
2
@

+3V_FB
2
2

@ @
B B
PR613 PR614 1 2 0_0402_5% PR615 1 2 0_0402_5%
[44,49] EC_ON EC_ON_5V [49]
20K_0402_1%
1

1
1M_0402_5%

1M_0402_5%
1

0.1U_0402_10V7K

0.1U_0402_10V7K
1

1
PR617
@ PC622

PR618

1
@ PC623
@

Vout=2V*(1+PR610/PR613)
2

PR616 Vout=2V*(1+PR612/PR616)
2

19.6K_0402_1%
2

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-3/5VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom DZ510/DY512 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, March 20, 2018 Sheet 60 of 75
5 4 3 2 1
A B C D

V20B+

+1.2V_VIN 1.5A

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
@

1
1 1

PC1402

PC1403
PC1401
2

2
+1.2V

1A
5

PR1401 PC1404
PQ1401
D

2.2_0603_5% 0.1U_0603_25V7-M
AON7408L_DFN8-5
PC1418 1 2 +1.2V_BST_R 1 2
10U_0603_6.3V6M
1 2 1 2 +1.2V_UG_R 4
+0.6VSP G
@ PR1404
S3
S2
S1

0_0603_5%
PL1401
+1.2V
3
2
1

0.68UH_PCMB063T-R68MS_16A_20%
1A 8A
+1.2V_BST

1 2
+1.2V_UG

+1.2V_LX
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
5
1

1
PC1413

AON7408L_DFN8-5
D

PC1406

PC1409

PC1410

PC1421
PC1407

PC1408

PC1417

PC1420
PR1402
4.7_0805_5%
20

19

18

17

16
2

2
PQ1402

470P_0402_50V7K
EMC_NS@
1
4
VTT

VLDOIN

BOOT

UGATE

PHASE

G
1

PC1405

21
PAD PR1407 @ @
S3
S2
S1

+1.2V_LG
@ @
1 15 60.4K_0402_1%
+1.2V_SN

VTTGND LGATE
3
2
1

@ A
2 14
VTTSNS PGND +1.2V_FB

3
PU1401
13 +1.2V_CS 1
PR1406
2 +5VALW +0.6VSP @
+0.6VS
GND CS
1

RT8231AGQW_WQFN20_3X3 560K_0402_1% PR1405 PJ1405


1

2 5.1_0603_5% PC1412 2 1 2

VTTREFP 4 12 +1.2V_VDD 1 2 1000P_0402_50V9-J PR1411 2 1


VTTREF VDD 100K_0402_1%
+3VALW EMC_NS@
2
1

PR1417 JUMP_43X79
PC1419
2

+1.2V 5 11 +1.2V_VID 1 2 @
1U_0402_6.3V6K VDDQ VID
1
PGOOD

PC1411
100K_0402_1%
2

1U_0402_6.3V6K
TON
FB

S3

S5

1 PR1418 2
100K_0402_1%
6

10
+1.2V_FB

+1.2V_TON

+1.2V_PG

PR1403
100K_0402_1%
@
+1.2V_S3

+1.2V_S5

1 2 +3VALW
+1.2V Vout V± 5%
PR1410 1 2 499K_0402_1% V20B+
Vset V± %
0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

CP 3A
1

1
PC321

PC322

PC323

PC324

Vref 0 V
VP 5~ 35 Vref
2

UVP 0 7~0 Vref


EMC_NS@ EMC_NS@ EMC_NS@ EMC_NS@
Fsw 700Khz Rmode 0
Fsw 500Khz Rmode 50K

3 3

Vout 0 V± 5%
PR1408 @
1 2 0_0402_5% +1.2V_S3 CP 5A
[6] SM_PG_CTRL
1M_0402_5%
0.1U_0402_10V7K

VTT / VDDQ
1

@
1

PC1414

PR1413

[49,53,64] SUSP# 1 2 @
STAT VDDQ VTT_R FP VTT
2

PR1409 @
2

0_0402_5%
S0 Hi Hi n n n
ff
S3 Lo Hi n n Hi-Z
PR1412 @
1 2 0_0402_5% +1.2V_S5
[49] SYSON_VDDQ S /S5 Lo Lo ff ff ff
1M_0402_5%
1
1

PR1414

PC1416
0.1U_0402_10V7K
@
ote: S3 - slee S5 - ower off
2

4 4

Security Classification LC Future Center Secret Data Title


Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-VDDQ/VTT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C DY520 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, March 20, 2018 Sheet 61 of 74
A B C D
A B C D

1 1

+3VALW

2
+5VALW PR2003
100K_0402_5%
@

1
1

PC2001
1U_0402_6.3V6K
+3VALW PU2001
2

+2.5V_POK
+2.5V
0 5A @ 10 5
PJ2001 VPP POK
@
2 1 +2.5V_VIN 7 PJ2002 0 5A
2 1 VIN1 2 +2.5V_P 2 1
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K

8 VO1 2 1
JUMP_43X39 VIN2
1

1
PC2004

PC2007

3
VO2 JUMP_43X39

22U_0603_6.3V6-M

22U_0603_6.3V6-M
PC2002 @
2

6 PR2001 220P_0402_50V7K @

2
VEN

1
PR2002 39K_0402_1%

PC2003

PC2006
@ 0_0402_5% Vout 5V± 5%

2
1 2 @
[16,60] ALW_PWRGD

2
1 4 +2.5V_FB
2 NC1 ADJ Vset 5 V± 3% 2

PR2005 @ 9 11
NC2 THERMAL_PAD Ilimit 3A
1
1 2 +2.5V_EN
[53] SYSON
PR2004
18.2K_0402_1%
Vref 0 V +- 5%
G9661-25ADJRE1U_TDFN10_3X3
1

0_0402_5%
PC2005 SA000091800
2

.1U_0402_10V6-K
2

eed again link cis only change P

3 3

4 4

Security Classification LC Future Center Secret Data Title


Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-2.5V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom DY520 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, March 20, 2018 Sheet 62 of 74
A B C D
A B C D

Vout 05V± 5%
1 1

Vset 05 V± %
Vref 0 V +- %
TDC A
CP A
VP 5~ 5 Vout
UVP 0 ~0 7 Vout
+3VALW Fsw 500Khz min 5K ma 575K
1

PR2101 @
10K_0402_5%
V20B+
@ PU2101 +1.05VALW
2

PJ2101 PC2101
5A 2 1 +1.0VALW_VIN 5 9 +1.0VALW_PG 0.1U_0603_25V7-M
2 1 4 IN1 PG 1 +1.0VALW_BS 1 2
IN2 BS
EMC_NS@

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

JUMP_43X79 3 PL2101
IN3
1

1
PC2102

PC2103

PC2104

2 0.68UH_PCMB063T-R68MS_16A_20%
IN4 6 +1.0VALW_LX 1 2 +1.0VALW_P A
7 LX1 19
2

GND1 LX2
1

330P_0402_50V8J

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
8 20
GND2 LX3
1

2 18 PR2102 2
GND3

1
PC2105

21 4.7_0805_5%
GND4

PC2106

PC2107

PC2108

PC2109

PC2110

PC2111
PR2103 @ 14 +1.0VALW_FB EMC_NS@
2

FB
1

100K_0402_5%
2

2
1 2 +1.0VALW_ILMT 13 12 PR2115
1VALW_SN

+3VALW
1 2 +1.0VALW_EN 11 ILMT NC3 10 10_0402_1%
EN NC1
1

1K_0402_1%
.1U_0402_10V6-K

[49] EC_ON_1V PR2104 +3VALW 16


NC2
1

PR2108

@ 100K_0402_5% 15 @ @
2

BYP
1

1
1M_0402_5%

PR2106 17 +1.0VALW_VCC PC2113


VCC
1

PC2112

PR2107

1000P_0402_50V9-J
4.7U_0603_6.3V6K

1M_0402_5%
1

EMC_NS@
2

PC2114 SY8286RAC_QFN20_3X3
1
PC2115

PR2111
2

4.7U_0603_6.3V6K 0_0402_5%
2

1 2 1.05VLAW_FB_R1 2 1
2

VCCMPHY_SENSE [21]
90.9K_0402_1% @
PR2105
1

PR2109
121K_0402_1%
0VGS can not merge with 05V SY change to SY PR2114
2

0_0402_5%
1.05VLAW_FB_R2 2 1
VSSMPHY_SENSE [21]
@
1

PR2116
3 10_0402_1% 3
2

4 4

Security Classification LC Future Center Secret Data Title


Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-1.0VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom DY510/DY511 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, March 20, 2018 Sheet 63 of 74
A B C D

LA-8551P
A B C D

VCCI 0VB+ change to Core VI for layout


1 1

+3VALW
1

PR901
10K_0402_5%
VCCCPUCORE_VIN
PU901 VCCIO
2

PR902 @
5A VCCIO_VIN 5 9 VCCIO_PG_R 1 2 0_0402_5%
IN1 PG VCCIO_PG [49]
4 1 VCCIO_BS 1 2
IN2 BS
EMC_NS@

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

3 PL901 @
IN3
1

1
PC901

PC902

PC904

2 PC903 1UH_PCMB053T-1R0MS_7A_20% PJ902


IN4 6 VCCIO_LX 0.1U_0603_25V7-M 1 2 VCCIO_P 2 1
A
7 LX1 19 2 1
2

GND1 LX2
1

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
8 20 JUMP_43X79
18 GND2 LX3 PR903 PC908
2 2
GND3 1

1
21 4.7_0805_5% 330P_0402_50V8J
2

GND4
PC905

PC906

PC907

PC909
PR904 @ 14 VCCIO_FB
VCCIO_FB_R3

FB EMC@
1

100K_0402_5%
2

2
1 2 VCCIO_ILMT 13 12 PR905
VCCIO_SN

+3VALW
VCCIO_EN 11 ILMT NC3 10 10_0402_1%
+3VALW
EN NC1 16
Vout 0 95V± 50mV
NC2
1

@ 15
Vset 0 9 V± 7 %
2

BYP
1

PR906 17 VCCIO_VCC PC910


VCC 1500P_0402_50V7-K
4.7U_0603_6.3V6K

1M_0402_5%
Vref 0 V
1

EMC@ PR907
2

PC911 SY8286RAC_QFN20_3X3
1
PC912

1K_0402_1% PR908
TDC A
2

4.7U_0603_6.3V6K 37.4K_0402_1% VCCIO_FB_R1 PR909 @


2

1 2 1 2 0_0402_5%
CP 9 5A TYP 0 5A MAX 5A
2

VCC_IO_SEN [10]
VP 5~ 5 Vout
1

ILMT 0 CP 5A PR910
UVP 0 ~0 7 Vout
62K_0402_1%
ILMT floating CP 9 5A
@
Fsw 500Khz min 5K ma 575K
ILMT CP 5A
2

VCCIO_FB_R2 PR911 1 2 0_0402_5%


VSS_IO_SEN [10]
1

PR912
[49,53,61] SUSP# 1 2 10_0402_1%
PR913
1K_0402_1%
2

3
[44,49] EC_ON 1 2 VCCIO_EN 3
100K_0402_1%

.1U_0402_10V6-K

PR914
2

1M_0402_5%

1K_0402_1% @
1

PC913

PR916

@
PR915

2
1

4 4

Security Classification LC Future Center Secret Data Title


Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-VCCIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom DY510/DY511 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, March 20, 2018 Sheet 64 of 74
A B C D

LA-8551P
5 4 3 2 1

Check MP2949 LCFC PN


SA00008XG00 is Y530 (014D) for H62 MP2949_AGND MP2949_AGND VCCST
@
SA000098100 (014F) for H42

1
100_0402_1%

75_0402_1%

45.3_0402_1%
1
4.7U_0603_6.3V6M

PR2901

PR2902

PR2903
PC2955
PC2902

1U_0402_10V6K 0.1U_0201_6.3V7-K
1

2
MP2949_AGND 2 @

2
PC2903 PR2904
PR2905 4.7_0402_5%
PC2904 V20B+ 49.9_0402_1%
2

1
2 1 1 2 MP2949A_SCLK1 2
+3VALW SVID_CLK [6]
0.01U_0402_50V7-K
MP2949A_VDD33

MP2949A_VDD18

PR2908 MP2949A_ALT#1
PR2953 2
D SVID_ALERT# [6] D
2 1 2 PR2907 1 2 1 0_0402_5% PR2906
PSYS 0 V MP 9 9 trigger VRH T +3VS
330P_0402_50V7K

133K_0402_1% MP2949A_SDIO# 1 2
4.7_0402_5% MP2949_AGND 2M_0402_1%
2

SVID_DATA [6]
PC2905

+3VS
1

PR2910 @ 10_0402_1% PR2909


PSYS function enable PR2952 680K_0402_1%
PU2901 +3VS
and PR2910 mount
2

10K_0402_1%
1

2
PR2913
44

26

10K_0402_1%
@ MP2949AGQKT-014D-Z_TQFN48_6X6

10K_0402_1%

10K_0402_1%
PR2914
2M_0402_1% PR2952
VDD33

VDD18

2
[49,59] PSYS

PR2915

PR2916
2 1 MP2949A_PSYS 46 47 MP2949A_VINSEN @
PSYS VIN_SEN 0_0402_5%
PR2918
1
@
PR2917 1 2 MP2949A_EN 37 30 MP2949A_VRRDY 2 1
[6,49] CPUCORE_ON CPU_PWRGD [49]

1
EN VRRDY

1
0_0402_5%
MP2949A_SCLK 27 35 MP2949A_SLPS0# @ @
SCLK SLP_S0#
@
PR2919 0_0402_5%
MP2949A_ALT# 29 32 MP2949A_SDAP 2 1
ALT# SDA_P EC_SMB_DA1 [49,58]
PR2911 0_0402_5%
MP2949A_SDIO# 28 33 MP2949A_SCLP 2 1
SDIO SCL_P EC_SMB_CK1 [49,58]
@
PR2948 1 2 0_0402_5% MP2949A_VRHOT# 31 36 MP2949A_PE
[6,49] H_PROCHOT# VRHOT# PE
PR292110K_0402_1%
2 1 MP2949_AGND
1.43K_0402_1% 2 1 PR2912MP2949A_VDIFFA 6
VDIFFA 34
STB SYNC [66,67,68]
2.15K_0402_1% 2 1 PR2922 MP2949A_VDIFFB
10
VDIFFB
8.25K_0402_1% 2 1 PR2923 MP2949A_VDIFFC
14
VDIFFC
38 MP2949A_PWM6
PWM6 PWM6_SA [68]
C MP2949A_VFBA 7 C
VFBA 39 MP2949A_PWM5
PWM5 PWM5_GT [67]
MP2949A_VFBB 11
VFBB
MP2949A_VFBC 15 40 MP2949A_PWM4
VFBC PWM4 PWM4_VCORE [66]

41 MP2949A_PWM3
PWM3 PWM3_VCORE [66]
@
PR2925 1 2 0_0402_5% MP2949A_VOSENA 8 42 MP2949A_PWM2
[9] VCCCORE_SENSE VOSENA PWM2 PWM2_VCORE [66]
@
PR2926 1 2 0_0402_5% MP2949A_VORTNA 9
[9] VSSCORE_SENSE VORTNA 43 MP2949A_PWM1
PWM1 PWM1_VCORE [66]
@ CS1_VCORE [66]
PR2929 1 2 0_0402_5% MP2949A_VOSENB 12
[9] VCCGT_SENSE VOSENB
@ CS2_VCORE [66]
PR2930 1 2 0_0402_5% MP2949A_VORTNB 13
[9] VSSGT_SENSE VORTNB
CS3_VCORE [66]
@
PR2933 1 2 0_0402_5% MP2949A_VOSENC 16
[10] VCCSA_SENSE VOSENC CS4_VCORE [66]
@
PR2935 1 2 0_0402_5% MP2949A_VORTNC 17 5 MP2949A_CS1 PR2934 1 2 1.5K_0402_1%
[10] VSSSA_SENSE VORTNC CS1

4 MP2949A_CS2 PR2936 1 2 1.5K_0402_1% CSSUMA


CSSUMA 18 CS2
CS_SUMA
CSSUMB 19 3 MP2949A_CS3 PR2938 1 2 1.5K_0402_1%
CS_SUMB CS3
CSSUMC 20 I7@
I5:PU2901=SA000098100(MP2949-014F) CS_SUMC
CS4
2 MP2949A_CS4 PR2939 1 2 1.5K_0402_1%

PR2944=SD00001KR00(43.2K)
1 MP2949A_CS5 PR2940 1 2 1.5K_0402_1% CSSUMB
PR2949=SD03410008J(100Ω ) CS5

61.9K_0402_1% 2 1 PR2941 MP2949A_IREF 24 48 MP2949A_CS6 PR2942 1 2 1.5K_0402_1% CSSUMC


MP2949_AGND IREF CS6

B B
CS6_SA [68]
21 PR2943 0_0402_5%
IMONA
CS5_GT [67]
25 MP2949A_ADDRP 1 2
ADDR_P MP2949_AGND
28.7K_0402_1%

22
IMONB
1
PR2944

I7@
115K_0402_1%

23 45 TEMP [66,67,68]
IMONC TEMP
1
2

560P_0402_50V7-K

332K_0402_1%
PC2906

PR2945

AGND
1

2
392_0402_1%

2
1

PR2946

I7@ PR2947 PC2909


49
220P_0402_50V7K
PR2949

49.9K_0402_1% 1U_0402_10V6K
1
1.37K_0402_1%

68P_0402_50V8J
1

MP2949A_AGND
1

I7@
2
PR2950

PC2907

PC2908
2

1
PR2951
2

3.4K_0402_1%

MP2949_AGND
2

MP2949_AGND MP2949_AGND

MP2949_AGND

MP2949_AGND

PJ2901 @
1 2

JUMPER

A MP2949_AGND A

Security Classification LC Future Center Secret Data Title


Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-IMVP8_MP2949
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom DY530 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, March 20, 2018 Sheet 65 of 74
5 4 3 2 1
5 4 3 2 1

VCCCPUCORE_VIN
VCCCPUCORE_VIN V20B+
@
PJ3001
A

10U_0805_25V6K

10U_0805_25V6K
10U_0805_25V6K

0.1U_0402_25V6
2 1
2 1
0.1U_0402_25V6

10U_0805_25V6K
1

1
10U_0805_25V6K

PC3026

PC3027

PC3028

PC3029

PC3030
JUMP_43X118 EMC@
1
10U_0805_25V6K

PC3005

EMC@
1

1
PC3052

PC3053

2
2

@ @ @
2

5
PD3001 RB751V-40_SOD323-2 PQ3003

1 2
@ PK6D0BA_DFN8-5 VCCCPUCORE
Phase3 PU3002 PR3049 0_0402_5%
PQ3009 3 12 HG_A2 1 2 HG_A2_R 4
[65] PWM2_VCORE PWM HGATE
AON6982_DFN8-7
2

BST_A2
D PU3001 PR3037 0_0402_5%
VCCCPUCORE [65,66] SYNC
4
SYNC BST
1 1 2 D

1
3 12 HG_A3 1 2 HG_A3_R 1 PC3031
[65] PWM3_VCORE PWM HGATE Phase2 [65,66] TEMP
2 PR3035 0_0603_5% 0.22U_0402_25V6-K PL3002

3
2
1
4 1 BST_A3
1 2 PL3001 TEMP 0.15UH_PCME064T-R15MS0R667_36A_20%
[65,66] SYNC

2
SYNC BST
1

PC3009 0.15UH_PCME064T-R15MS0R667_36A_20% 5 11 SW_A2 1 2


SW_A3 [65] CS2_VCORE CS SW
2 PR3033 0_0603_5% 0.22U_0402_25V6-K 7 1 2
[65,66] TEMP TEMP

5
13 9
2

EPAD LGATE
1

1
5 11 SW_A3 LG_A3
6 PQ3004
[65] CS3_VCORE CS SW

1
PR3002 8 PK632BA_DFN8-5 PR3006 PR3019
VCC
1

13 9 1/8W_1_5%_0805 7 1/8W_1_5%_0805 1.78K_0402_1% PR3020


EPAD LGATE ISENP
1

PC3083 EMC@ PR3001 PR3003 10 EMC@ 10_0402_1%


8 1000P_0402_50V7K GND 6 LG_A2 4
1.78K_0402_1% 10_0402_1%
3
4
5

2
VCC 7 @ +5VALW_DRIVE ISENN
2

2
ISENP

2
10 MP8693GDT-Z_TQFN12_2x3 chang PN chang PN
2

GND 6 chang PN PC3042


+5VALW_DRIVE ISENN
1 1U_0402_10V6K

3
2
1
2

MP8693GDT-Z_TQFN12_2x3
PC3010
1

1
1U_0402_10V6K PC3015 PC3078 1 2 PC3043
1

4700P_0402_50V7K 4700P_0402_50V7K PC3080 1 2 .47U_0402_6.3V6K


EMC@ .47U_0402_6.3V6K EMC@
2

2
4.7K +-1% TSM0A472F34D1RZ
4.7K +-1% TSM0A472F34D1RZ
PR3007 PR3004 PR3005
PH3003
ISENP_A3 ISENP_A3_R PR3024 PR3021 PR3022
1 2 1 2 1 2 1 2 PH3002
ISENP_A2 1 2 ISENP_A2_R 1 2 1 2 1 2
511_0402_1%
130_0402_1% 412_0402_1% 511_0402_1%
PR3008 130_0402_1% 412_0402_1%
PR3023
1 2
PR3009
1 2
ISENN_A3 1 2 ISENN_A3_R 1.5K_0402_1%
PR3025
1.5K_0402_1%
ISENN_A2 1 2 ISENN_A2_R
130_0402_1%

130_0402_1%

VCCCPUCORE_VIN
VCCCPUCORE_VIN

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
I7_EMC@

1
10U_0805_25V6K

10U_0805_25V6K

PC3069

PC3064

PC3065
0.1U_0402_25V6

C EMC@ C
1

1
PC3054

PC3057

PC3058

RB751V-40_SOD323-2 @

2
I7@
PD3002
2

1 2
5

PQ3005
VCCCPUCORE @ VCCCPUCORE
PK6D0BA_DFN8-5 PQ3012
AON6982_DFN8-7

2
PU3003 PR3039 0_0402_5% PU3004 PR3038 0_0402_5%
Phase1
[65] PWM1_VCORE
3
PWM HGATE
12 HG_A1 1 2 HG_A1_R 4
[65] PWM4_VCORE
3
PWM HGATE
12 HG_A4 1 2 HG_A4_R 1

4 1 BST_A1 1 2 4 1 BST_A4 1 2I7@ PL3004


[65,66] SYNC SYNC BST [65,66] SYNC SYNC BST
1

PC3059 0.15UH_PCME064T-R15MS0R667_36A_20%
1

2 PR3034 0_0603_5% 0.22U_0402_25V6-K PL3003 2 PR3036 0_0603_5% PC3062 7 SW_A4 1 2


[65,66] TEMP [65,66] TEMP
3
2
1

TEMP 0.15UH_PCME064T-R15MS0R667_36A_20% TEMP 0.22U_0402_25V6-K


Phase4 I7@
2

1
5 11 SW_A1 1 2 5 11 SW_A4 6 I7@
[65] CS1_VCORE [65] CS4_VCORE
2

CS SW CS SW

1
PR3015
I7@ LG_A4
5

1
13 9 13 9 1/8W_1_5%_0805 PR3026
EPAD LGATE EPAD LGATE
1

PR3010 I7_EMC@ 1.78K_0402_1% PR3027


1

8 1/8W_1_5%_0805 PR3011 8 PC3082 10_0402_1%


3
4
5

2
VCC 7 PR3012 VCC 7 1000P_0402_50V7K
EMC@ 1.78K_0402_1% I7@

2
10 ISENP 10 ISENP I7@
10_0402_1% @ chang PN
2

2
+5VALW_DRIVE GND 6 LG_A1 4 +5VALW_DRIVE GND 6 chang PN I7@
2

ISENN ISENN
chang PN
2
2

MP8693GDT-Z_TQFN12_2x3 PQ3006 MP8693GDT-Z_TQFN12_2x3


PC3001 PC3068 I7@

1
1U_0402_10V6K 1U_0402_10V6K PC3066
1

3
2
1

PK632BA_DFN8-5 4700P_0402_50V7K PC3081 1 2 .47U_0402_6.3V6K


I7@
1

PC3061 I7_EMC@

2
4700P_0402_50V7K PC3079 1 2 .47U_0402_6.3V6K I7@
EMC@ 4.7K +-1% TSM0A472F34D1RZ
2

PR3031 PR3028 PR3029


4.7K +-1% TSM0A472F34D1RZ PH3004
ISENP_A4 1 2 ISENP_A4_R 1 2 1 2 1 2
PR3018 PR3013 PR3014
PH3001
ISENP_A1 1 2 ISENP_A1_R 1 2 1 2 1 2 511_0402_1% I7@
130_0402_1% 412_0402_1%
I7@ PR3030I7@
511_0402_1% I7@
130_0402_1% 412_0402_1% 1 2
PR3016
PR3032
1 2 1.5K_0402_1%
ISENN_A4 1 2 ISENN_A4_R I7@
PR3017
1.5K_0402_1%
ISENN_A1 1 2 ISENN_A1_R
B
+5VALW_DRIVE 130_0402_1%
B
I7@
130_0402_1%
@
2 1
+5VALW
PR3050 0_0603_5%
@ 0_0603_5%
PR3051

+5VS 2 1
SIZE:B2 VCCCPUCORE
330u*2PCS+22u*24PCS
A
330U_D2_2V_Y
330U_B2_2.5VM_R9M

330U_D2_2V_Y

330U_D2_2V_Y
PC3011

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1 1 1 1
+ + + + Vboot 0V Loadline mΩ
PC3012

PC3013

PC3014

1
PC3032

PC3033

PC3034

PC3035

PC3036

PC3037

PC3038

PC3039

PC3040

PC3041

PC3044

PC3045

PC3046

PC3047

PC3048

PC3049

PC3050

PC3051

PC3016

PC3017

PC3018

PC3019

PC3020

PC3021

PC3022

PC3023

PC3024

PC3025

Ri le +30mV/- 0mV 0A-0 5A


2 2 2 2
Ri le ± 0mV 0 5A-TDC
2

Ri le ± 5mV TDC-Iccma
@
@ TDC 0A H 0A
@ @ @ @ CP 55A H 9 A
Iccma A H
PC3014 with heat pipe Gap too small for 1160 ,so PC3014@ PC3013 NA VP VID+ 00mV
VP V during SS
UVP VID-300mV
VCCCPUCORE_VIN VCCCPUCORE
Fsw 500Khz
1000P_0402_25V7-K
0.1U_0402_25V6

1000P_0402_25V7-K

1000P_0402_25V7-K
0.1U_0402_25V6

0.1U_0402_25V6
1

1
PC331

PC332

1
PC333

PC334

PC335

PC336
2

A A

EMC_NS@ EMC_NS@
EMC_NS@ EMC_NS@ EMC_NS@ EMC_NS@

Security Classification LC Future Center Secret Data Title


Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-VCCCPUCORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom DY520 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, March 20, 2018 Sheet 66 of 74
5 4 3 2 1

LG_A4
5 4 3 2 1

V20B+
A
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

10U_0805_25V6K

10U_0805_25V6K
1

1
PC3125

PC3126

PC3127
Vboot 0V Loadline 7mΩ

1
PC3151

PC3152
Ri le +30mV/- 0mV 0A-0 5A
2

2
Ri le ± 0mV 0 5A-TDC
@ @
D
Ri le ± 5mV TDC-Iccma D
EMC_NS@

TDC 5A Iccma 3 A CP 5 A
VP V during SS VP VID+ 00mV
5

PQ3101
PK6D0BA_DFN8-5
UVP VID-300mV
PR3110 0_0402_5%
Fsw 500Khz
1 2 HG_B1_R 4
PU3102
3 12 HG_B1
[65] PWM5_GT PWM HGATE

[65] SYNC
4 1 1 2
VCCGFXCORE
3
2
1

SYNC BST
1

PC3102
2 PR3109 0_0603_5% 0.22U_0402_25V6-K PL3102
[65] TEMP TEMP 0.15UH_PCME064T-R15MS0R667_36A_20%
3 A
2

5 11 SW_B1 1 2
[65] CS5_GT CS SW

330U_D2_2V_Y

330U_D2_2V_Y
5

13 9 1 1
EPAD LGATE
5

PQ3102 PR3106
1

+ +

PC3111

PC3109
8 PK632BA_DFN8-5 PQ3103 1/8W_1_5%_0805
VCC

1
7 PK632BA_DFN8-5 EMC@ PR3101
10 ISENP PR3102
1.78K_0402_1%
+5VALW_DRIVE
2

GND 6 LG_B1 4 2 2
ISENN 10_0402_1%
LG_B1 4 @
2
2

MP8693GDT-Z_TQFN12_2x3 chang PN

2
PC3139
1U_0402_10V6K chang PN
1

3
2
1

3
2
1

PC3150
4700P_0402_50V7K
C C
EMC@
2

PC3101 1 2 .47U_0402_6.3V6K

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1

1
PC3122

PC3121

PC3120

PC3119

PC3118

PC3117

PC3116

PC3115

PC3114

PC3113
4.7K +-1% TSM0A472F34D1RZ
PR3108 PR3103 PR3104
PH3101

2
ISENP_B 1 2 ISENP_B_R 1 2 1 2 1 2

511_0402_1%
140_0402_1% 412_0402_1%
PR3105
@
1 2
PR3107
1.5K_0402_1%

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
ISENN_B 1 2 ISENN_B_R

140_0402_1%

1
PC3137

PC3136

PC3135

PC3134

PC3133

PC3132

PC3131

PC3130

PC3129

PC3128
2

2
@ @

B
330u*1PCS+22u*17PCS B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-VCCGFXCORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom DY520 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, March 20, 2018 Sheet 67 of 74
5 4 3 2 1
5 4 3 2 1

D D

VCCCPUCORE_VIN Vboot 05V Loadline 0 3mΩ


Ri le +30mV/- 0mV 0A-0 5A
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
Ri le ± 0mV 0 5A-TDC
1

EMC@
PC3201

PC3202

PC3203

Ri le ± 5mV TDC-Iccma
TDC 0A Iccma A CP A
2

VP V during SS VP VID+ 00mV


5

AON7408L_DFN8-5

UVP VID-300mV
D

PQ3201

PU3201 PR3288 0_0402_5%


Fsw 500Khz
3 12 HG_C 1 2 HG_C_R4
[65] PWM6_SA PWM HGATE G
4 1 1 2
S3
S2
S1

[65] SYNC SYNC BST


1

2 PR3287 0_0603_5%
PC3243
0.22U_0402_25V6-K PL3201
VCCSA
[65] TEMP 0A
3
2
1

TEMP 0.47UH +-20% PCMB053T-R47MS 13A


2

C C
5 11 SW_C 1 2
[65] CS6_SA CS SW
1

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
13 9 LG_C
EPAD LGATE
5

PR3202
8
AON7534_DFN8-5

1/8W_1_5%_0805
D

VCC

1
PC3213

PC3212

PC3211

PC3210

PC3209

PC3208

PC3207
7 EMC@
ISENP
1
PQ3202

10
2

GND
1

6 PR3280

2
ISENN 4 PR3281 10_0402_1%
+5VALW_DRIVE G
2

MP8693GDT-Z_TQFN12_2x3 chang PN 1.3K_0402_1%


PC3205
S3
S2
S1

1U_0402_10V6K
1

@ @
3
2
1

PC3214
4700P_0402_50V7K
PC3242
EMC@
2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1 2

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
0.1U_25V_K_X5R_0402
1

2
PC3215

PC3216

PC3217

PC3219

PC3220

PC3221
4.7K +-1% TSM0A472F34D1RZ
PR3285 PR3283
PH3201
2

1
ISENP_C 1 2 ISENP_C_R 1 2 1 2 1 PR3282 2
B B
511_0402_1% 240_0402_1%
1.78K_0402_1%
PR3284 @
1 2
PR3286 22u*10PCS
ISENN_C 1 2 ISENN_C_R 1.5K_0402_1%

1.78K_0402_1%

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-VCCSA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B DY520 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, March 20, 2018 Sheet 68 of 74
5 4 3 2 1
A B C D

V20B+
@

3A PJ1803
2 1 FBVDDQ_VIN
2 1 PR1801
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

0_0603_5%
JUMP_43X79 +1.55VGS_BST 1 2 +1.55VGS_BST_R
1

EMC_NS@
PC1801

PC1802

PC1803

1
PU1801
2

AOZ2264QI-20_QFN23_4X4 PC1804
20

0.1U_0603_25V7K

2
BST

1 1

+1.55VGS_LX
+5VALW 7
IN_1 LX_1
10

8 11
IN_2 LX_2 FBVDDQ

@
PJ1801
2

9 16
PR1802 IN_3 LX_3 2 1
2.2_0603_5%
22u*8PCS 2 1
22 17 PL1801 JUMP_43X118
IN_4 LX_4

@
PJ1802
1

0.47UH_PCMB063T-R47MS_18A_20%
PC1805 18 +1.55VGS_LX 1 2 +1.55VGS_P 2 1
A
2 1 21 LX_5 2 1
VCC

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
JUMP_43X118
@ 0_0402_5% 4.7U_0603_6.3V6K PR1803
PR1804

1
PC1806

PC1807

PC1808

PC1809

PC1810

PC1811

PC1812

PC1813

PC1814

PC1815

PC1816

PC1817

PC1818

PC1819
5 2.2_0805_5%
FB

1+1.55VGS_SN

22U_0603_6.3V6-M
[27,29] FBVDDQ_PWR_EN 2 1 +1.55VGS_EN 2 EMC_NS@
EN

2
12
PGND_1

1
PC1820 @
.1U_0402_10V6-K

1 2 6 PR1806
V20B+ PR1805 TON 13 100_0402_1% @ @ @ @ @ @
PGND_2
1

110K_0402_1% PC1821
1000P_0402_50V9-J

2
1 2 +1.55VGS_RF 3 14 EMC_NS@
2

2
100K_0402_1% PFM PGND_3
PR1807
PC1822 15
1 2 23 PGND_4
SS PR1809 @
0.01U_0402_25V7K 19 +1.55VGS_FB 1 2 1 2 0_0402_5%
PGND_5
FBVDD_VCC_SENSE [28]
+1.55VGS_PG 1 PR1808
[27] VDDQPWROK PGOOD 10.2K_0402_1%
Vout:
P5 35V± 3%
AGND

+3VS 1 2+1.55VGS_FB_R2 1 2
P0 5V± 3%
1 2 PR1810 PC1823
TDC A
4

PR1811 0_0402_5% 1500P_0402_50V7-K


100K_0402_5%
PK-PK :55mV
DP-c A DP- 0A
CP A
1

1.35/1.55V PR1812=30.9K SD03430928J PR1812 PR1813


2
1.35/1.50V PR1812=37.4K SD03437428J 37.4K_0402_1% 8.2K_0402_1%
VP ~ 3 Vout 2

change to X76 VRAM UVP 0 5~0 75 Vout


2

Fsw 500Khz
+1.55VGS_FB_R3

CAD ote: VRAM_VDDQ_ADJ


FB 0 V +- 5%
L 3 V
H 507V
1

D
PR1814 @
1 VRAM_VDDQ_ADJ_R
2 0_0402_5% 2 PQ1801
[27] VRAM_VDDQ_ADJ
G LBSS139WT1G_SC70-3
S
3
1

@
PR1815
100K_0402_1%
2

3 3

4 4

Security Classification LC Future Center Secret Data Title


Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-FBVDDQ
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom DY510/DY511 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, March 20, 2018 Sheet 69 of 74
A B C D
A B C D

V VI change to 3 3V
+3VS

1 1

PR1901
+3VALW 100K_0402_1%
@
2

@
PJ1901
A2 2 1
1
22U_0603_6.3V6-M

22U_0603_6.3V6-M

1.8VALW_PG
0.1U_0402_25V6
1
EMC_NS@

JUMP_43X79 +1.8VALW
1

4
PC1901

PC1902

PC1903

@
2

+1.8VALW_VIN 10 1 PL1901 PJ1902


PG
2

PVIN2 NC1 1UH_PH041H-1R0MS_3.8A_20% JUMP_43X79


9
PVIN1 LX2
2 +1.8VALW_LX 1 2 +1.8VALW_P 2
2 1
1 3 A
@ 8 3
SVIN LX1

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
PR1902
4.7_0603_5%

1
5 6 EMC_NS@ Vout V± 3%
GND

NC2

EN FB

PC1904

PC1905

PC1906
2
+1.8VALW_SN
Vset V± 9%

2
11

PU1901
Vref 0 V +- 5%
SY8033BDBC_DFN10_3X3 1
CP A
PR1903 @ PC1907 @
1 2 0_0402_5% +1.8VALW_EN 680P_0402_50V7K
[49] EC_ON_1.8V
EMC_NS@
Fsw Mhz
2

2 2
1

1M_0402_5%
PR1904

PD1901 0_0402_5% @ PC1908 PR1906


3 PR19051 2 .1U_0402_10V6-K 33K_0402_1%
2

+1.8VALW_FB 1 2
1
2

0_0402_5% @
Hai 2 PR19071 2 PC1909
1

220P_0402_50V7K
LBAT54SWT1G_SOT323-3 PR1908 1 2
@ 16.2K_0402_1%
2

+5VALW
PJ1903
@

A 2
2 1
1 +1.0VGS
22U_0603_6.3V6-M

22U_0603_6.3V6-M
0.1U_0402_25V6

@
JUMP_43X39
1

1
EMC_NS@

PU1902 PL1902 PJ1904


PC1922

PC1923

1UH_PH041H-1R0MS_3.8A_20% JUMP_43X79
A
PC1921

+1.0VGS_VIN 4 3 +1.0VGS_LX 1 2 +1.0VGS_P 2 1


+3VS
2

3
IN LX 2 1 3

5 2
PG GND
1

6 1 PR1911 22U_0603_6.3V6-M 22U_0603_6.3V6-M


@

FB EN
1

4.7_0603_5%
1

PR1910 SY8032ABC_SOT23-6 EMC_NS@


10K_0402_1% PC1924 PC1926
Vout 0V± 3%
+1.0VGS_SN 2

Vset 0 V± %
2

2
2

1.0VGS_PG Vref 0 V
[27] 1.0VGS_PG
CP 3 5A
Fsw Mhz
1

PC1928
680P_0402_50V7K
PR1912 @ EMC_NS@
2

1 2 0_0402_5% +1.0VGS_EN
[24,29] 1V0_MAIN_EN
0.1U_0402_10V6-K

1 2
@ 1M_0402_5%

+1.0VGS_FB PR1914 1 2 88.7K_0402_1%


1
@

PR1913

PD1902
1

@ PC1927

LRB751V-40T1G_SOD323-2
PC1929
1

220P_0402_50V7K
2

PR1915 1 2
2

133K_0402_1%
@
2

4 4

Security Classification LC Future Center Secret Data Title


Issued Date 2016/01/20 Deciphered Date 2016/01/20 PWR-1.8/1.0VGS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom DY520 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, March 20, 2018 Sheet 70 of 74
A B C D
5 4 3 2 1

PWM-VID S ecification Com onent Value


Config R KΩ PR5 9 PSI Level Power Mode Phase Configuration
Vmin V 0 3 R KΩ PR5 0 5 PSI<0 V PSH Phase D M
Vma V 3 R3 KΩ PR5 5 3 0 V<PSI< V PS0 Phase FCCM
Vboot V 0 R KΩ PR5 3 5 V<PSI<5 5V PS 3Phase FCCM
Vste mV 5 R5 KΩ PR5 0 309
level 0 C nF PC5 3 7
F wm KHz 75 V20B+
NVVDD_B+
Tdmin nS 9
T uS < 00 +5VS PJ5801@
2 1
2 1
EMC@
2200P_0402_25V7-K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

JUMP_43X118
1
1

22U_25V_M
D D
Vboot 0 V
5

PC5852
PR5801
PU5801
PC5810

PC5801

PC5802

PQ5801
2.2_0603_5%
PK6D0BA_DFN8-5
Ri le ± 0mV
2

2
PC5809

TDC_50W 59A Iccma A


2

NVVDD_PVCC 21 @
PVCC 2 NVVDD_HG1 4 @ NVVDD TDC_ 0W 50A Iccma 00A
UGATE1
+1.8VS_AON
1

PC5803 PR5807 PC5804


1U_0402_6.3V6K 2.2_0603_5% 0.22U_0603_25V7K
Vref V
1 NVVDD_BS1 1 2 1 2
FUVP:Vfb 0 V
2

3
2
1

BOOT1
1

25
PR5802 GND SUVP:Vcom 3V
PL5801
5.1K_0402_1%
24 NVVDD_PH1 NVVDD_PH1 1 2
VP:Vfb V
PHASE1 0.22UH_PCMB104T-R22MS_35A_20%
Fsw 3 5KHz
2

PR5803 @ PQ5802
330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y
1 1 1
1

1 2 0_0402_5% NVVDD_PSI_R 4 PK632BA_DFN8-5 PQ5803


[27] NVVDD_PSI PSI + + +
PC5806

PC5807

PC5811
PR5805 @ 1050TI@ PR5808
5.1K_0402_1%
PK632BA_DFN8-5
4.7_0805_5%
CP 90A
1 PR5804 2 @ 1 2
+1.8VS_AON 10K_0402_1% 23 NVVDD_LG1 4 NVVDD_LG1
4 EMC@ 2 2 2
2

16 LGATE1
[27] NVVDD_PWRGD PGOOD
PR5806 30K_0402_1% @
1 2 NVVDD_EN_R 3
[27,29] NVVDD_EN
3
2
1

3
2
1

EN
1

PC5813
NVVDD_B+
1

1500P_0402_50V7-K

22U_0603_6.3V6-M
PR5837 PC5808 1M_0402_5%
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

10U_0603_6.3V6-M

22U_0603_6.3V6-M
PD5801 0_0402_5% @ .1U_0402_10V6-K PR5838 EMC@
2

3 1 2
50W:330uF*4PCS+22U*11
2

1
PC5814

PC5815

PC5816

PC5817

PC5818

PC5819

PC5820
1
40W:330uF*3PCS+22U*11
2

3K_0402_5%
2

2
@ NVVDD_HG2
10U_0805_25V6K

10U_0805_25V6K

LBAT54SWT1G_SOT323-3 2 1 2 5 17 PQ5804 10U_0805_25V6K


VID UGATE2
PC5818 for rick require
EMC@
2200P_0402_25V7-K

PK6D0BA_DFN8-5
PR5836 PR5810 PC5821
1

PR5809 @ 2.2_0603_5% 0.22U_0603_25V7K @


NVVDD_VID_R NVVDD_BS2 1
PC5824

PC5826

[27] NVVDD_VID 1 2 0_0402_5% 18 2 1 2 4 PC5825


BOOT2
@
2

2
1

PC5823

PC5822 @
0.1U_0402_10V7K @
2

3
2
1

PL5802
19 NVVDD_PH2 NVVDD_PH2 1 2
2 1 NVVDD_VREF 8 PHASE2 0.22UH_PCMB104T-R22MS_35A_20%
VREF
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
5

PC5827
1

1
PC5828

PC5829

PC5830

PC5831

PC5832

PC5833

PC5834

0.1U_0402_25V6 PQ5805
PR5811 PK632BA_DFN8-5 PQ5806 PR5812
C 20.5K_0402_1% 4.7_0805_5% C
1050TI@ PK632BA_DFN8-5
2

20 NVVDD_LG2 4 EMC@
2

LGATE2 NVVDD_LG2 4
1

NVVDD_REFIN 7 @15K_0402_1% PC5835


REFIN 1500P_0402_50V7-K @
3
2
1

PR5834 EMC@
3
2
1

2
1

PR5813
2

16.5K_0402_1%
PR5816
PR5815
6.19K_0402_1% PR5814
2

1 2 1 2 NVVDD_VIDBUF 6 100_0402_1%
PC5836 @ REFADJ
1

10 NVVDD_VSS_SENSE_R 1 2
0.01U_0402_25V7K RGND
4.32K_0402_1% @
1
2

PR5818 PC5838
309_0402_1% 4700P_0402_25V7-K 11 NVVDD_VCC_SENSE_R PR5817 @
VSNS 1 2 0_0402_5%
2

NVVDD_VSS_SENSE [29]
2

1 2NVVDD_FS9 12 NVVDD_COMP VVDD rail from ou ut ca for debug


TON ILIM
1

PR5819 PC5837 @ and Rmote sense tie to GPU


PR5821 442K_0402_1% 1000P_0402_25V7-K
1

2.2_0603_5%
2

1 2 PR5820 @
V20B+
1

12.1K_0402_1%

PR5835 @ 1 2 0_0402_5%
1

1050TI@

22K_0402_1% NVVDD_VCC_SENSE [29]


PR5822

PC5839
2

1U_0402_25V6-K PR5823
2

100_0402_1%
2

PC5851 @
1000P_0402_25V7-K
1 2
@
NVVDD NVVDD_B+
2

NVVDD_PH1 1 PR5824 2 15 PR5822=20K SD03420028J for1050


VCC/ISEN1
+5VS PR5822=12.1K for1050TI
EMC@
2200P_0402_25V7-K

10U_0805_25V6K

10U_0805_25V6K

PR5839 10K_0402_1%
0_0402_5%
1 2
+5VS
1

NVVDD_PWM3
PC5842

PC5843

@ 22 PR5825
PWM3
2.2_0603_5%
2

2
5

PC5841

NVVDD_PH2 1 PR5826 2 14 PQ5807


2

TALERT/ISEN2
2

PK6D0BA_DFN8-5
10K_0402_1% PR5840
@ 0_0402_5%
B NVVDD_HG3 4 B
2

0_0402_5%

PC5840
1

PR5827

1 2
PR5828 PR5829 PC5845
NVVDD_PH3 1 2 13 1U_0402_6.3V6K PU5802 2.2_0603_5% 0.22U_0603_25V7K
NVVDD
3
2
1

TSNS/ISEN3 4 NVVDD_BS3 1 2 1 2
1

10K_0402_1% 8 BOOT
@ VCC 3
5 UGATE PL5803
RT8813DGQW_WQFN24_4X4 PR5830 @ PWM 2 NVVDD_PH3 NVVDD_PH3 1 2
NVVDD_EN_R 1 2 PWM3_EN 1 PHASE 0.22UH_PCMB104T-R22MS_35A_20%
EN
5

7
LGATE
1
0.1U_0402_10V7K

0_0402_5% 6 PQ5808 PQ5809 PR5831


330U_D2_2V_Y

330U_D2_2V_Y

GND1 1 1
PC5846

@ 9 PK632BA_DFN8-5 PK632BA_DFN8-5 4.7_0805_5%


GND2 + +
PC5847

PC5850
2

RT9610CGQW_WDFN8_2X2 1050TI@ EMC@


2

NVVDD_LG3 4 NVVDD_LG3 4
2 2

1050TI@
3
2
1

3
2
1

PC5848
1500P_0402_50V7-K
EMC@
2

A A

Security Classification LC Future Center Secret Data Title


Issued Date
PWR-NVVDD
2016/01/20 Deciphered Date 2016/01/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D DZ510/DY512 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Tuesday, March 20, 2018 Sheet 71 of 74
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 PWR-Power schematic history
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DZ510/DY512
Date: Tuesday, March 20, 2018 Sheet 72 of 74
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DZ510/DY512
Date: Tuesday, March 20, 2018 Sheet 73 of 74
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/02/26 Deciphered Date 2016/02/26 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DZ510/DY512
Date: Tuesday, March 20, 2018 Sheet 74 of 74
5 4 3 2 1

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