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Introduction
In computers very wide,, 32 bit or 64 bit, adders form part of the in the Arithmetic
Logic Unit (ALU) where other arithmetic and logical operations are performed. In
this laboratory, we will use the ISE tools to design, simulate and synthesise an eight
bit Ripple Carry Adder. In addition, we will use hierarchy, that is, we will use
components already written in order to reduce the design effort.
PRE-LAB READING
In advance of this lab, please read RealDigital module 7.
Procedure
Please fill in the report as you go, answering the questions in blue. When asked to
paste screenshots, please put them at the end of the report.
Using ISE Project Manager generate a new project called Byte_Add in the junk
directory. Target a Xilinx Spartan 3E and leave all properties at default values. In
your Project Summary, make sure you have the following values.
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Lab 3 :-8 bit adder
Project summary
Create a VHDL file called XSE.vhd which will hold a library of components for use in
this, and other, designs, including a Full Adder. We will use 8 copies, known as
instances, of the Full Adder as the basis for building the Byte Adder. Put the code for
the XSE file at the bottom of this sheet into the XSE.vhd file. Next, create a library in
the project called XSE and move the XSE.vhd to the library by right clicking on the
file in the Libraries tab and moving it to the XSE library. You should see this in your
ISE environment.
Now create a top level VHDL Module, ByteAdd.vhd, describing the 8 bit adder using
the Fulladder module from the XSE library. Put the code for the file at the bottom of
this sheet into the ByteAdd.vhd file.
The USE xse.adder.all statement gives file access to all of the components of the
Adder package of the XSE library. The ByteAdd module uses a FOR loop to
iteratively instantiate 8 copies of the FullAdd module. The GENERATE and END
GENERATE statements surround the instantiation. The loop counter, i, indexes the
input and output arrays as the loop proceeds. For example, the first time through the
loop the inputs to the FullAdd module are a(0), b(0) and c(0) – which is connected
to the carry input on the line c(0)<=cin; The modules sum and carry outputs are
connected to sum(0) and c(1) respectively. The c(1) element connects the carry
output from the first adder bit to the carry input of the next adder bit on the next
loop iteration.
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Lab 3 :-8 bit adder
Right click on ByteAdd and set it as Top Module. Synthesise the design. View the
RTL schematic after choosing all the signals, primitives etc before creating the
schematic. It should be similar to that shown below.
Take a screenshot of your RTL schematic and paste it to the end of your report
Double Click on the Fulladd block and you should get the block below it. Note the
combinational logic necessary to generate the carry out signal for each Full Adder
stage.
SAMPLE
RTL view
SAMPLE
Right click to highlight the box and then choose New Schematic with Selected
Objects. You should get a view of the chain of 8 full adders required to build this 8 bit
adder, together with the circuitry required to combine them.
Have a close look at this. Note how the carry input at the top of the diagram feeds
into the first full adder. The carry_ out from here is the carry_ in of the next stage. In
this way, the carry ripples through the circuit.
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Lab 3 :-8 bit adder
SAMPLE
Generate the Technology View of the circuit. You should get something like the one
shown below
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Lab 3 :-8 bit adder
SAMPLE
Technology view
Take a screenshot of your Technology View and paste it to the end of your report
Note the area of combinational logic here to generate the carry (black oval). Note the
area of combinational logic here to generate the sum. All of the combinational logic is
implemented in the LUTs of the FPGA.
Create a testbench called ByteAdd_tb and add it to the project. Place the (minimal)
testbench code below into the file ByteAdd_tb. Associate the testbench with
ByteAdd. Simulate the circuit with the testbench supplied. You should get something
like this....
SAMPLE
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Lab 3 :-8 bit adder
The testbench does the following arithmetic. Obviously, a real testbench would test
the device a lot more exhaustively.
Verify that the answers are correct from the waveforms and tick the boxes if they
are.
Add at least 3 other stimulus vectors to the testbench, in other words, get the device
to perform 3 more calculations by modifying the testbench and insert the
simulation results into your report.
Fill in Table 1.
Name of Slices
No of 4 input LUTs
No of I/Os
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Lab 3 :-8 bit adder
CODE LISTINGS
ByteAdd.vhd file
-- 8-bit Adder
LIBRARY IEEE,xse;
USE IEEE.std_logic_1164.all;
USE xse.adder.all; -- use the adder-bit module from the XSE
library
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Lab 3 :-8 bit adder
carry_output=>c(i+1) -- carry output from this stage
becomes the
); -- input to the
next stage of the adder
END GENERATE;
cout<=c(8); -- output carry comes from the last bit of the carry array
END byteadd_arch;
--
-- Notes:
-- that these types always be used for the top-level I/O of a design in
order
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY byteadd_Byte_Add_tb_vhd_tb IS
END byteadd_Byte_Add_tb_vhd_tb;
COMPONENT byteadd
PORT(
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Lab 3 :-8 bit adder
b : IN std_logic_vector(7 downto 0);
cin : IN std_logic;
);
END COMPONENT;
BEGIN
a => a,
b => b,
);
tb : PROCESS
BEGIN
a<="00000000";
b <="00000000";
cin<= '0';
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Lab 3 :-8 bit adder
wait for 10 ns;
a<="00000100";
b <="00001100";
cin<= '0';
a<="11111111";
b <="00000000";
END PROCESS;
END;
PACKAGE evpar IS
-- 2-bit parity generator component declaration
COMPONENT evpar2
PORT
(
b0,b1: IN STD_LOGIC;
par: OUT STD_LOGIC
);
END COMPONENT;
-- 4-bit parity generator component declaration
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Lab 3 :-8 bit adder
COMPONENT evpar4
PORT
(
b0,b1,b2,b3: IN STD_LOGIC;
par: OUT STD_LOGIC
);
END COMPONENT;
END evpar;
ENTITY evpar2 IS
PORT (
b0,b1: IN STD_LOGIC;
par: OUT STD_LOGIC
);
END evpar2;
LIBRARY IEEE,XSE;
USE IEEE.std_logic_1164.all;
USE XSE.evpar.all;
ENTITY evpar4 IS
PORT (
b0,b1,b2,b3: IN STD_LOGIC;
par: OUT STD_LOGIC
);
END evpar4;
PACKAGE adder IS
COMPONENT fulladd
PORT
(
input0: IN STD_LOGIC;
input1: IN STD_LOGIC;
carry_input: IN STD_LOGIC;
sum: OUT STD_LOGIC;
carry_output: OUT STD_LOGIC
);
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Lab 3 :-8 bit adder
END COMPONENT;
END adder;
ENTITY fulladd IS
PORT (
input0: IN STD_LOGIC;
input1: IN STD_LOGIC;
carry_input: IN STD_LOGIC;
sum: OUT STD_LOGIC;
carry_output: OUT STD_LOGIC
);
END fulladd;
PACKAGE led IS
COMPONENT leddcd
PORT
(
d : IN STD_LOGIC_VECTOR (3 DOWNTO 0); -- 4-bit input
s : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) -- 7 outputs to
drive LED dISplay
);
END COMPONENT;
END led;
ENTITY leddcd IS
PORT(
d : IN STD_LOGIC_VECTOR (3 DOWNTO 0); -- 4-bit input
s : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) -- 7 outputs to drive LED
dISplay
);
END leddcd;
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Lab 3 :-8 bit adder
"0010010" WHEN "0001",
"1011101" WHEN "0010",
"1011011" WHEN "0011",
"0111010" WHEN "0100",
"1101011" WHEN "0101",
"1101111" WHEN "0110",
"1010010" WHEN "0111",
"1111111" WHEN "1000",
"1111011" WHEN "1001",
"1111110" WHEN "1010",
"0101111" WHEN "1011",
"1100101" WHEN "1100",
"0011111" WHEN "1101",
"1101101" WHEN "1110",
"1101100" WHEN "1111",
"0000000" WHEN others;
END leddcd_arch;
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