COURSE FILE

DEPARTMENT: ELECTRONICS AND COMMUNICATION ENGINEERING

COURSE:VLSI DESIGN
Academic Year: 2022-2023
Regulation: R18

Name of the Faculty: G DEEPTHI

Department: ECE
Branch & Year: III BTech - II Sem
 Check List of the Course File

Department: ELECTRONICS AND COMMUNICATION ENGINEERING

Subject Code: EC603PC` Title of the subject:VLSI DESIGN

S.No Attributes Yes/No

1 Vision and Mission of institute
2 Course handout& its contents
a) Vision and Mission of department
b) PEOs of the program
c) Program Outcomes (POs)
d) Prerequisites
e) Course Objectives and Course Outcomes (COs)
f) Detailed syllabus
g) Course Plan
h) Evaluation scheme
3 CO-PO mapping
4 Academic calendar
5 Department calendar
6 Subject time table
7 Course material
8 Teaching diary for the course
9 Question bank prepared by faculty (unit wise)
10 Quiz question bank
11 Descriptive question bank for assignment
12 Sets of copies of old question papers

Name & Signatures IQAC members Dean Academics

1.
2.
3.

COURSE FILE
 COURSE DESCRIPTION / COURSE INFORMATION SHEET

Course Title VLSI DESIGN

Course Code EC603PC Programme B.Tech

Regulation R18 Year/Semester III/II

Lectures Tutorials Practical Credits

Course Structure
03 01 00 04

Course Teacher G DEEPTHI

Email deepthitkr@gmail.com

Phone No 6305369913

No of Hours Allotted Lectures Tutorial Practical

per Week 03 01 00
 COURSE OVERVIEW
1. Vision & Mission of the Institution

To flourish as a centre of excellence for producing the skilled technocrats and committed
Vision
human beings
 To create conducive environment for teaching & learning.
 To impart quality education through demanding academic programs.
 To enhance career opportunities by exposure to recent & industriestechnologies.
Mission
 To develop professionals with strong ethics and human values for the betterment
of society.

a) Vision & Mission of the Department

To be in the frontiers of Computer Science and Engineering with academic excellence and
Vision
Research.

 To ensure dissemination of knowledge through effective teaching and learning in

Electronics Communication Engineering.

 To excel in research and development activities in emerging areas by promoting

Mission
industry-institution interaction.

 To establish center of excellence in trust areas to nurture the spirit of innovation and
creativity among students to meet global needs.
2. Course Handout

b) Program Educational Objectives (PEOs)

PEO1 To be well acquainted with fundamentals of Electronics & Communication

Engineering for leading a successful career in industry or as an entrepreneur or pursuing
higher education.
PEO 2 To produce graduates with communicative, leadership & organizational skills and
to inculcate professional ethics and lifelong learning attitude.
PEO 3 To foster techno-commercial skills for innovative solutions in Electronics &
Communication Engineering or related areas and addressing global societal needs.
PEO 4

c) Program Outcomes and Program Specific Outcomes (POs)& (PSOs)

Engineering Knowledge: Apply the knowledge of mathematics, science, engineering

PO1 fundamentals, and an engineering specialization to the solution of complex engineering
problems.

Problem Analysis: Identify, formulate, review research literature, and analyze

PO2 complex engineering problems reaching substantiated conclusions using first principles
of mathematics, natural sciences, and engineering sciences.

Design/Development of Solutions: Design solutions for complex engineering

PO3 problems and design system components or processes that meet the specified needs
with appropriate consideration for the public health and safety, and the cultural,
societal, and environmental considerations
Conduct Investigations of Complex Problems: Use research-based knowledge and
PO4 research methods including design of experiments, analysis and interpretation of data,
and synthesis of the information to provide valid conclusions.
Modern Tool Usage: Create, select, and apply appropriate techniques, resources, and
PO5 modern engineering and IT tools including prediction and modeling to complex
engineering activities with an understanding of the limitations.
The Engineer and Society: Apply reasoning informed by the contextual knowledge to
PO6 assess societal, health, safety, legal and cultural issues and the consequent
responsibilities relevant to the professional engineering practice.
Environment and Sustainability: Understand the impact of the professional
PO7 engineering solutions in societal and environmental contexts, and demonstrate the
knowledge of, and need for sustainable development.

PO8 Ethics: Apply ethical principles and commit to professional ethics and responsibilities
and norms of the engineering practice.

PO9 Individual and Team Work: Function effectively as an individual, and as a member
or leader in diverse teams, and in multidisciplinary settings.
Communication: Communicate effectively on complex engineering activities with the
PO10 engineering community and with society at large, such as, being able to comprehend
and write effective reports and design documentation, make effective presentations, and
give and receive clear instructions.

PO11 Project Management and Finance: Demonstrate knowledge and understanding of the
 engineering and management principles and apply these to one’s own work, as a
member and leader in a team, to manage projects and in multidisciplinary
environments.
Life-long Learning: Recognize the need for, and have the preparation and ability to
PO12 engage in independent and lifelong learning in the broadest context of technological
change.
Ability to solve real world problems in Electronics and Communication Engineering
PSO 1
using state of art techniques, along with analytical and managerial skills.

Ability to participate successfully in competitive examinations, career advancement and

PSO 2
higher studies with professional ethics.

e) Course Outcomes (COs)

CO-1 Acquire qualitative knowledge about the fabrication process of integrated circuits
using MOStransistors.
CO-2 Draw the layout of any logic circuit which helps to understand and estimate parasitic
effect ofany logic circuit
CO-3 Design building blocks of data path systems, memories and simple logic circuits using
PLA,PAL, FPGA and CPLD.
CO-4 Understand different types of faults that can occur in a system and learn theconcept of
testingand adding extra hardware to improve testability of system.

f) Detailed Syllabus
EC603PC: VLSI DESIGN

B.Tech. III Year II Sem. LTPC

3104

Pre-Requisites: Nil
Course Objectives:The objectives of the course are to
 Give exposure to different steps involved in the fabrication of ICs.
 Explain electrical properties of MOS and BiCMOS devices to analyze the behaviour of
invertersdesigned with various loads.
 Give exposure to the design rules to be followed to draw the layout of any logic circuit.
 Provide design concepts to design building blocks of data path of any system using
gates.
 Understand basic programmable logic devices and testing of CMOS circuits.

Course Outcomes: Upon completing this course, the student will be able to
 Acquire qualitative knowledge about the fabrication process of integrated circuits using
MOStransistors.
 Draw the layout of any logic circuit which helps to understand and estimate parasitic
effect ofany logic circuit.
 Design building blocks of data path systems, memories and simple logic circuits using
PLA,PAL, FPGA and CPLD.
 Understand different types of faults that can occur in a system.

UNIT - I:
Introduction: Introduction to IC Technology – MOS, PMOS, NMOS, CMOS & BiCMOS
Basic Electrical Properties: Basic Electrical Properties of MOS and BiCMOS Circuits: I ds-
Vdsrelationships, MOS transistor threshold Voltage, g m, gds, Figure of merit; Pass transistor,
NMOS Inverter,Various pull ups, CMOS Inverter analysis and design, Bi-CMOS Inverters.

UNIT - II:
VLSI Circuit Design Processes: VLSI Design Flow, MOS Layers, Stick Diagrams, Design
Rules andLayout, Transistors Layout Diagrams for NMOS and CMOS Inverters and Gates,
Scaling of MOScircuits.
UNIT - III
Gate Level Design: Logic Gates and Other complex gates, Switch logic, Alternate gate
 circuits, Timedelays, Driving large capacitive loads, Wiring capacitance, Fan – in, Fan – out.

UNIT - IV
Data Path Subsystems: Subsystem Design, Shifters, Adders, ALUs, Multipliers, Parity
generators,Comparators, Zero/One Detectors, Counters.
Array Subsystems: SRAM, DRAM, ROM, Serial Access Memories.

UNIT - V
Programmable Logic Devices: Design Approach – PLA, PAL, Standard Cells FPGAs,
CPLDs.
CMOS Testing: CMOS Testing, Test Principles, Design Strategies for test, Chip level Test
Techniques.

TEXT BOOKS:
 Essentials of VLSI circuits and systems – Kamran Eshraghian, Eshraghian Dougles and
A.Pucknell, PHI, 2005 Edition.
 CMOS VLSI Design – A Circuits and Systems Perspective, Neil H. E Weste, David
Harris, AyanBanerjee, 3rd Ed, Pearson, 2009.

REFERENCE BOOKS:
 Introduction to VLSI Systems: A Logic, Circuit and System Perspective – Ming-BO Lin,
CRCPress, 2011.
 CMOS logic circuit Design - John. P. Uyemura, Springer, 2007.
 Modern VLSI Design - Wayne Wolf, Pearson Education, 3rd Edition, 1997.
 VLSI Design- K. Lal Kishore, V. S. V. Prabhakar, I.K International, 2009.

g) Course Plan (Theory)

 Topic (s) Proposed
Unit/
No. of
Item No.
Periods
INTRODUCTIONANDBASICELECTRICPROPERTIES 19
I
1.1 IntroductiontoICTechnology 1
1.2 MOSFETEnhancement anddepletionmode operation 1
1.3 NMOSandPMOSfabrication 2
1.4 CMOSfabrication&BiCMOStechnologies 2
1.5 Ids-VdsRelationshipofMOS 1
1.6 MOStransistorthresholdVoltage,gm,gds,figureofmerit 2
1.7 NMOS Inverter, pull up to pull down ratio of NMOS inverter driven 4
byanother inverter,pullup to pulldownratio ofNMOS inverterdriven
bytwoormorepasstransistors
1.8 Alternateformsofpullup(depletionmode,resistive 1
load,enhancementmode)
1.9 CMOSinverter,MOScircuitmodel 1
1.10 BiCMOSinverter,latchupinCMOSinverter 3
1.11 BiCMOS latchupsusceptibility 1
II VLSICIRCUITDESIGNPROCESSES 11
2.1 VLSIDesignFlow 1
2.2 MOSLayers 1
2.3 StickDiagrams 2
2.4 DesignRulesand Layout 1
2.5 2umCMOS Designrulesforwires,Contactsand Transistors 1
2.6 ContactsandtransistorsLayoutDiagrams forNMOSandCMOS 2
Inverters
2.7 LayoutDiagramsforGates 2
2.8 ScalingofMOScircuits,LimitationsofScaling. 1
III GATELEVELDESIGN 9
3.1 Logic Gates 1
3.2 Complexgates 1
3.3 Switchlogic 1
3.4 Alternategatecircuits 1
3.5 TimeDelays,Driving largeCapacitiveLoads 2
3.6 WiringCapacitances, Fan-inandfan-out 2
 3.7
IV DATAPATHSUBSYSTEMS
4.1 SubsystemDesign 1

4.2 Shifters,Adders 2
4.3 ALUs,Paritygenerators 1
4.4 Multipliers 1
4.5 Comparators,Zero/OneDetectors 1
4.6 Counters 1
4.7 ArraySubsystems,SRAM,DRAM 1
4.8 ROM 1
4.9 Serialaccessmemories,Contentaddressablememory 1

h) Evaluation Scheme Theory

Evaluation Criteria Marks

Assignment I 05
Midterm-1 Objective paper 10
Descriptive Paper 10
Total 25
Assignment II 05
Midterm-2 Objective paper 10
Descriptive Paper 10
Total 25
Average of Midterm-1 and Midterm-2 25
End-Examination 75
Total 100
 3.Mapping of CO-PO&PSO
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2
CO/PO
CO-1 2 2 1 2 2 1 1 1 1 1 1 2 2 2
CO-2 1 2 2 2 2 1 1 1 1 1 1 2 2 2
CO-3 1 2 2 2 2 1 1 1 1 1 1 2 2 2
CO-4 1 2 2 2 2 1 1 1 1 1 1 2 2 2
CO-5 1 2 2 2 2 1 1 1 1 1 2 2 2 2
Weightage 1.2 2 1.8 2 2 1 1 1 1 1 1.2 2 2 2

Type Course PO PO PO PO PO PO PO1 PO1 PO1 PSO PSO

PO1 PO2 PO3
Code, Title 4 5 6 7 8 9 0 1 2 1 2
DIGITAL
Theory SYSTEM 1 2 2 2 2 1 1 1 1 1 2 2 2 2
DESIGN
Contribution of course to program outcomes& Program Specific outcomes

Academic calendar
Department calendar
Subject time table
 UNIT WISE IMPORTANT QUESTIONS
UNIT –I (Long answer questions)

S.N0 Question BloomsTa CourseO

xonomyLe utcome
vel
A) ConvertthegivenGraycodenumbertoequivalent Apply 1
1. binary001001011110010.
B) Convert(A0F9.0EBA98.0DC)16todecimal,binary,octal.
A) SimplifythefollowingBooleanexpressionsusingtheBool Apply 1
eantheorems.
i)(A+B+C)(B’+C)+(A+D)(A’+C)ii)(A+B)(A’+B)(A+B’)
2. B) WhyaNANDandNORgatesareknownasuniversalgates?
SimulateallthebasicGates.
A) Encodethemessagebits(1110)2into7- Apply 1
3. bitevenparityhammingcode.
B) Performthefollowingarithmeticusing2’scomplementm
ethod.
i)101111-100110ii)111001-011010
A) Convertthefollowingexpressionintosumofproductsandp Apply 1
4. roductofsums. X'+X(X+Y')(Y+Z')
B) ImplementthefollowingBooleanfunctionwithNANDgat
es
only.F(X,Y,Z)=∑m(1,2,3,4,5,7)
ObtaindualofthefollowingBooleanexpressions Apply 1
(i)AB+A(B+C)+B’(B+D)ii)A+B+A’B’C
5. b)Obtainthecompliment
 ofthefollowingBooleanexpressions
i)A’BA’BC’+A’BCD+A’BC’D’E
ii)ABEF+ABE’F’+A’B’EF.
a) Convert the number(1222)and(4413) Apply 1
intodecimalandhexadecimalnumbersystem.
6. b) Add and multiplythe numbers (23)5 and(345)6
withoutconvertingtodecimal.
c) Considerafunction‘F’.ShowthatF.F’=0andF+F’=1.
a) Findthe9’scomplement Apply 1
7. ofthenumbers12345678,87654321.
b) ExpressthefunctionB’D+A’D+BDinsumofmintermsand
productofmaxterms.
8. a) Given2binarynumbersX=1010100andY=1000011perfo Apply 1
rmi)X-Yii)Y-Xusing2’scomplementmethod.
b) ProvethattheGrayCodeisthereflectingcode.
9. a) Findthecomplementofthefollowingfunctioninsumofmin Apply 1
terms.F(A,B,C,D)=∑(3,5,9,11,15)
b) obtainthedualofthefollowingfuncti
on.F=A’B+A’BC’+A’BCD+A’B(C
DE)’.
10. a) ExplaintheoperationanduseaTTLgatewithanopen- Understand 1
collectoroutput.
b) DiscussthelogiclevelsandnoisemarginwithreferencetoT
TLfamily
11. a) ExplaintheoperationoftheCMOSgatewithopendrainoutpu Understand 1
t.
b) DrawastandardtwoinputTTLNANDgateandexplainthe
operation.
12. ExplainhowCMOS- Understand 1
TTLinterfacingcanbeachieved.Givethe
inputand outputlevels ofvoltages andexplainthesame.
13. a) Writeshortnotes ontristateTTL Understand 1
b) ClassifyICsbasedonapplication,deviceusedandchipco
mplexity.
14. WhatisthenecessityofseparateinterfacingcircuittoconnectC Understand 1
MOSgatetoTTLgate?
Drawtheinterfacecircuitandexplainthe
operation?
 UNIT I (Short answer questions)

S.No. Question BloomsTa CourseO

xonomyLe utcome
vel

AB+AB+BC=AC+ABrepresentswhich theorem? Apply 1

1.
2. Howdo youobtaindualofanexpression? Understand 1
Convertthefollowingtotherequiredform.i)(101001.001)2=( Apply 1
3. )10 ii) (1264)8=( )10
iii)(A3B)16=( )10
4. ShowthatthedualoftheExclusive–ORis equaltoitscomplement. Apply 1

5. WhatisGraycode? Remember 1

6. DefineBinarycoded decimalcode. Remember 1

DrawthelogicdiagramofNANDgateandexplain. Understand 1
7.
AddandSubtract thefollowinginbinary. Apply 1
8. i)1111and1010ii)100100and10110
9. GivethecharacteristicsofTTLfamily. Understand 1
DrawaCMOStristatebufferandexplain. Understand 1
10.
DrawtheinterfacingcircuitofCMOSdrivingTTLgate Understand 1
11.
DefineLinearandDigital ICs Understand 1
12.
WhyIntegratedcircuitsareneeded? Understand 1
13
ClassifytheICs Understand 1
14.
a) Listtheparameterswhichareused tocomparelogicfamilies. Understand 1
15.
b) Drawthediagramofbasicgateof2inputTTLgate.
a) RealizeEX-ORgatewithCMOS circuit. Understand 1
16.
b) Mentionthereasonswhyopenloopisnotpreferredforlinearapplicatio
ns

UNIT II (Long answer questions)

S.No. Question BloomsTa CourseO

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 A combinational circuit has 4 inputs (A,B,C,D) and three
outputs(X,Y,Z). XYZ represents a binary number whose value
equals thenumberof1’sattheinput
i. Findthemintermexpansion fortheX,Y,Z
ii. FindthemaxtermexpansionfortheYandZ.
Acombinationalcircuithasfourinputs(A,B,C,D),whichrepresent a Evaluate
binary-coded-decimal digit. The circuit has two groupsof four
outputs- S,T, U, V (MSB digit) and W, X,Y,Z (LSB digit).Each
2. group represents a BCD digit. The output digits represent adecimal 2
number which is five times the input number. Write
downtheminimumexpressionforalltheoutputs.

SimplifythefollowingBooleanexpressionsusingK- Analyze
3. mapandimplementthemusingNORgates: 2
(a) F(A,B, CD)=AB’C’+AC+A’CD’
(b) F(W,X,Y,Z)=W’X’ Y’Z’+WXY’Z’+W’X’YZ+WXYZ
4. DesignBCDtoGraycodeconverterandrealizeusinglogicgates. Analyze 2
5. Design2*4decoderusingNANDgates. Analyze 2
6. Reducethefollowingexpression usingK-map(BA+A’B+AB’) Apply 2
Designacircuitwiththreeinputs(A,B,C)andtwooutputs(X,Y) Analyze
7. wheretheoutputsarethe 2

binarycountofthenumberof“ON”(HIGH)inputs
Designathreeinputmajorityfunctionsuchthattheoutputis1if Analyze
8. 2
theinputhasevennumberof1’s otherwisetheoutputis0.
Designacombinationalcircuitwiththethreeinputsandoneoutput.theoutp Analyze
9. utisequaltologic-1whenthebinaryvalueofthe 2
inputisless than4otherwisetheoutputislogic-0.
a) Minimize the following expression using K-map and realize Apply
usingNAND Gates,
10. F(A,B,C,D)=∑m(0,1,2,9,11)+d(8,10,14,15). 2
b) MinimizethefollowingexpressionusingK-
mapandrealizeusingNORGates.
f=M(0,4,6,7,8,12,13,14,15)

UNIT II (Short answer questions)

S.No. Question BloomsTa CourseO

xonomy utcome
Level
1. DefineK-map? Remember 2
2. Writetheblockdiagramof2-4and3-8decoders? Understand 2
3. Definemagnitudecomparator? Remember 2
4. Whatdoyoumean bylook-aheadcarry? Remember 2
5. Simplify the Boolean function using K-Map F(X,Y,Z)= Apply
2
∑m(0,2,4,5,6).
 6.
7. WhataretheICcomponentsusedtodesigncombinatorialcircuits Understand
2
withMSIandLSI?
8. Definetheimportanceofprimeimplications Understand 2

9. Locatethemintersin athreevariablemap forf=∑m(0,1,5,7) Apply 2

10. SimplifytheBooleanfunctionx′yz+x′yz′+xy′z′+xy′zwithout Apply
2
using K-map
11. Whataredon’tcares? Whatisminterms? Understand
2
12. a) Comparecombinationalandsequentialcircuits. Understand
2
b) Explain aboutbinarycell.
13. Realizea fulladderusing2halfaddersandexplainthetruthtable. Analyze 2
14. Explainthewiredlogic. Understand 2
15. WhatisaDecoder?Constructa4×16decoderwithtwo3×8 Analyze
2
Decoders.
16. Realizeafulladderusing2halfaddersandexplainthetruthtable. Analyze 2

UNIT III (Long answer questions)

S.No. Question Blooms CourseO

Taxonomy utcome
Level
Whatismeantby‘edgetriggered’?DifferentiateSR-FFandJK-FF Evaluate 2
1. withtheirfunctionaloperationandexcitationtables.
Draw andexplainthecircuitdiagramofpositiveedgetriggeredJ-K Evaluate 2
2. flip-
flopusingNORgateswithitstruthtable.Howracearoundconditionsareeli
minated?
a) Discussaboutsynchronousandripplecounters.Comparetheirmerits Understand 2
3. anddemerits.
b) Whatdoyoumeanbyuniversalshiftregister?Drawandexplainits
circuitdiagramandoperation.
Explainindetailabouttimingandtriggeringconsiderations Understand 2
4. sequentialcircuits.
a) What is a shift register? Explain about the following modes Understand 2
ofoperations in a four bit shift register (i) shift right (ii) shift left
5. (iii)bidirectional.
b) ExplainthedifferencesbetweenringandJohnsoncounters.Design
andexplaintheoperationofadecadeJohnson counters.
Deducethedesignprocedureforsequentiallogiccircuitsandgive Understand 2
6. theclassificationofsequentiallogiccircuits.
a) DesignandexplainasynchronousMOD-12down-counterusingj- 2
7. kflipflop.
b) Designandexplaina4-bitringcounterusingD-
flipflopswithrelevanttimingdiagrams.
 8.
a) Design aMOD-10ripplecounter. Apply 2
9. b) DesignandconstructMOD-5synchronouscounterusing
JKflipflops.
10. Differentiatecombinationalandsequentialcircuits. Understand 2

11. ExplaintheworkingprincipleofJKflip flop indetail. Understand 2

12. DeriveaJK-flip-flop fromSRflip flop. Create 2

13. Explain serialtransfer in 4-bitshiftregisters Understand 2

14. HowmanyFlipFlopswillbecomplementedina10bitbinary Evaluate 2

ripplecountertoreach thenextcountaftercounting 1111110011?

15. ExplainaboutBinaryRipplecounter. Understand 2

16. DefineLatch.Explain differenttypesofLatchesin detail Understand 2

17. Examinewiththehelpofablockdiagram,thebasiccomponentsof Understand 2

asequentialcircuit.

18. ExplaintheRipplecounterdesign. Mentionitsapplication Understand 2

19. a) Explainthedesign ofring counterusingshiftregisters. Apply 2

b) Draw thelogicdiagramofa4-bitbinaryripplecounterusingflipflops
thattriggeronnegativeedgetransition.
20. Explainabout designofanALUsubsysteminbrief. Understand 2

UNIT III (Short answer questions)

S.No. Question BloomsTa CourseO

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1. Distinguishbetweenashiftregisterandcounter? Understand 2
2. Whataretheapplications ofshiftregisters? Understand 2
3. WhataretheapplicationsofFlip-Flops? Understand 2
4. Discussabout abidirectional shiftregister? Understand 2
5. Howdo you buildalatchusinguniversalgates? Analyze 2
 6.
7. Distinguishbetweensynchronousandasynchronouslatch? Understand 2

8. Whatismeantbyclockedflip-flop? Understand 2

9. WhyagatedDlatchis calledatransparentlatch? Understand 2

10. Whatarethetwotypesofflip-flops? Understand 2

11. WriteashortnotesonRippleCounter. Understand 2

Drawaneatdiagramofa3-bitJhonsonCounterandexplainits Understand 2
12.
truthtableinbrief.
13. Comparelatch andflipflop. Understand 2

14. Whatarethe drawbacksofripplecounters? Understand 2

15. DefineLevel trigger,Edgetrigger, Clockskew. Understand 2

16. ExplainaboutRingcounterwith aneatdiagram. Understand 2

17. Whatarethebasictypes ofshiftregisters? Understand 2

18. Compareasynchronousandsynchronouscounters. Understand 2

UNIT IV (Long answer questions)

S.No. Question BloomsTa CourseO

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Level
a) ExplaintheoperationofSuccessiveapproximationADC. Understand 3
1. b) WriteabouttheADCspecifications.
a) Discussaboutthebinaryweightedresistor DAC. Understand 3
2. b) MentiontheapplicationsofDACand ADC.
a) Explaintheworking of weighted resistorD/Aconverter andstateits Understand 3
3. features.
b) Findtheresolutionofa12bitD/A converter.
a) ExplaintheworkingofdualslopeA/Dconverter. Understand 3
4. b) DrawtheIC1408DACpindiagramandexplain.
a) DescribeParallelComparatortypeADCoperation. Understand 3
5. b) Explain theworkingofInvertedR-2RladderD/Aconverter.
a) FindouttheStepsizeandAnalogoutputwheninputis0011and1011.A Evaluate 3
6. ssumeVref=+5V.
b) ExplainSuccessiveApproximationADCwiththehelpofblockdiagra
m.
7. ComparethedualslopeADCwithsuccessiveapproximationADC. Understand 3
a) Explaintheoperationofflash ADCusingrelevantdiagrams. Understand 3
8. b) Whatarethemeritsanddemeritsofcountertype ADC?Explain.
 9.
a) FindtheResolutionof12-bitD/AConverter. Evaluate 3
10. b) An8-
bitSuccessiveApproximationADCisdrivenbya1MHzclock.FinditsCo
nversiontime.
a) DiscusstheoperationofcountertypeADC. Understand 3
11. b) Explain theoperationofdualslopeADC
a) For the D/A converter using an R-2R ladder network, Evaluate 3
12. determinethe size of each step if Rf = 27kΩ and R= 10kΩ and also
calculatetheoutputvoltagewhentheinputsb0,b1,b2andb3areat5V.
b) WriteabouttheADCspecifications.
a) DrawthecircuitdiagramofDualslopeADCandexplainitsworking. Understand 3
13. b) Whatis theroleofDACinsuccessiveapproximationADC?

UNIT IV (Short answer questions)

S.No. Question Blooms CourseO

Taxonomy utcome
Level
1. CompareR-2RandWeightResistortypesofADC. Understand 3
An8bitsuccessiveapproximationtypeADCisdrivenbya1MHz Understand 3
2. clock.Findtheconversion time.
3. Whatarethedifferentsourcesoferrors inDAC? Understand 3

4. List thevariousA/Dconversiontechniques. Understand 3

ListthedrawbacksofBinaryweightedResistortechniqueD/A Understand 3
5. conversion.
Howmanyresistorsarerequiredina12-bitweightedresistor Understand 3
6. DAC?Why?
7. ExplainhowDual-slopeADCprovidesnoiserejection? Understand 3
8. WhichisthefastestADCand why? Understand 3

9. Foraparticular8-bitADC,theconversiontimeis9µs.Findthe Evaluate 3
maximumfrequencyofaninputsinewavethatcan bedigitized.
10. Whatismeant byresolutionofDAC? Understand 3

11. WhatistheconversiontimeofcountingtypeADCandparallel Understand 3

comparatorADC.
12. WhatistheadvantageofR-2RladderD/Aconverterovertheone Understand 3
withbinaryweightedresistors?
13. WhatarethedifferenttypesofADCsandcomparethemintermsof Understand 3
speed ofoperation

UNIT V (Long answer questions)

S.No. Question BloomsTa CourseO

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a) Drawthestructureofa4×4staticRAMandexplainit’soperation. Understand 4
1. b) Whatisaprogrammabledevice?HowitdiffersfromROM?

Discussany two typesof programming technology Understand 4

2. usedinFPGAdesign.

ExplainthedetailedlogicconfigurableBlockArchitectureofFPGA. Understand 4
3.

4. Design aPALtorealizeafullAdder circuit. Understand 4

DrawthebasiccircuitdiagramofstaticRAMandexplainits Understand 4
5. operation.
6. Comparevariousprogrammabledevices. Understand 4
Explain about Serial access Understand 4
7. memories.ExplainArchitectureofFPGAi
ndetail.
WhatarethedrawbacksofPLAs?HowPLAsareusedto Understand 4
8. implement combinationalandsequentiallogiccircuits?
9. Explain thedetailedArchitectureofCPLD anditsImplementations Understand 4

UNIT V (Short answer questions)

S.No. Question BloomsTa CourseO

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Level
1. Whatis programmablelogicarray? Understand 4
2. Mention aboutSRAM anditsusage. Understand 4
3. Describeabout theSerialAccessMemories. Understand 4
4. ExplainthedifferencebetweenEPROMandEEPROM. Understand 4
5. ExplaindifferencebetweenPLAandPAL. Understand 4
6. Drawthe1-bitSRAM cell. Understand 4
7. Whatarethevariousserialaccess memories? Understand 4
8. Implement2:1 MUXusingPAL Understand 4
9. WritetheComparisonbetweenFPGAandCPLD. Understand 4
 I Mid Question Papers:

ANUBOSE INSTITUTE OF TECHNOLOGY

KSP ROAD, PALONCHA- 507115
(Approved by AICTE, New Delhi, Affiliated to JNTU, Hyderabad)
I MID Term Examinations
Course: II B. Tech-I-SEM Branch: ECE Date: 24-01-2023
Subject Name: DSD Answer any TWO questions Max. Marks: 10m

1. Convert the given Gray code number to equivalent binary 001001011110010.

2. Minimize the following expressions using K-map.
f = ∑m (1, 3, 5, 8, 9, 11, 15) +d (2, 13).
3. Convert (A0F9.0EB)16 to decimal, binary, octal.
4. Solve the following function using Q-M method
A=f(w,x,y,z)= ∑m (0,1,9,15,24,29,30)+d∑m(8,11,31)

ANUBOSE INSTITUTE OF TECHNOLOGY

KSP ROAD, PALONCHA- 507115
(Approved by AICTE, New Delhi, Affiliated to JNTU, Hyderabad)
I MID Term Examinations
Course: II B. Tech-I-SEM Branch: ECE Date: 24-01-2023
Subject Name: DSD Answer any TWO questions Max. Marks: 10m

1. Convert the following:

i) AB16=( )10
ii) 101100112=( )10
iii) 77210=( )16
iv) (0.513)10=( )8
v) Convert (0011001.0101)2 to decimal and octal.
2. Decode the following message assuming that at most a single bit error occurred in each
code word when it is transmitted through a noisy channel using 7-bit Hamming code.
1110111, 0011011, 1101101.
3. Solve the following function using K-MAP
A=f(w,x,y,z)=π(1,2,3,4,8,9,10,11,12,13,14,15).
 4. Solve the following function using Q-M method
A=f(w,x,y,z)= ∑m (8,9,10,11,13,15,16,18,21,24,25,26,27,30,31)

ANUBOSE INSTITUTE OF TECHNOLOGY

KSP ROAD, PALONCHA- 507115
(Approved by AICTE, New Delhi, Affiliated to JNTU, Hyderabad)

I MID Term Examinations, January- 2023

Course: II B. Tech I SEM Subject Name: DSD
Name: ___________________________________ H.T NO: ____________________

Answer all questions. All questions carry equal marks Time: 20min
Marks: 10M

1. Which number system has a base 16? [ ]

a) Hexadecimal
b) Octal
c) Binary
d) Decimal
2. How many entries will be in the truth table of a 4-input NAND gate? [ ]
a) 6
b) 8
c) 32
d) 16
3. How many bits are needed to store one BCD digit? [ ]
a) 2 bits
b) 4 bits
c) 3 bits
d) 1 bit
4. Which of these sets of logic gates are known as universal gates? [ ]
a) XOR, NAND, OR
b) OR, NOT, XOR
c) NOR, NAND, XNOR
d) NOR, NAND
5. DeMorgan's Law states that [ ]
a) (A+B)' = A'*B
b) (AB)' = A' + B'
c) (AB)' = A' + B
d) (AB)' = A + B
6. A K-map (Karnaugh map) is an abstract form of which diagram organized as a square
matrix. [ ]
a) Block diagram
b) Cycle diagram
c) Square diagram
d) Venn diagram
7. In a K-map each square can represent [ ]
a) literal
b) sum term
c) min-term
d) product-term
8. Identify the circuit given below [ ]
a) XNOR

b) XOR
c) AND
d) OR
9. is called [ ]
a) Demorgans theorem
b) Consensus theorem
c) Logic adjacency theorem
d) Involution
10. Group of four adjacent minterm is called [ ]
a) pair
b) quad
c) octet
d) redundant group
 11. Convert (312)8 into decimal ___________________
12. What is the addition of the binary number 101001+ 010011= __________________
13. What is the binary subtraction of 101001 - 010110 = _________________________
14. Different methods for solving the Boolean expressions are ________________________
15. The excess-3 code for 584 is given by ________________________________________
16. A six variable K-map need __________________ squares.
17. Simplified expressions produced by a K-map are in __________________ form.
18. If all elements in a group are covered by some other groups, then the group is called
________________
19. The unspecified minterms of a function are called ______________________
20. Ex-OR functions are useful in _____________ and ______________________

II MID QUESTION PAPERS

ANUBOSE INSTITUTE OF TECHNOLOGY

KSP ROAD, PALONCHA- 507115
(Approved by AICTE, New Delhi, Affiliated to JNTU, Hyderabad)
II MID Term Examinations
Course: II B.Tech-I-SEM Branch: ECE Date: 02-05-2023
Subject Name: DSD Answer any TWO questionsMax. Marks: 10M

1. Discuss about serial binary adder.

2. Draw the state diagram of a sequence detector for sequence 1010.
3. Draw the circuit diagram of basic TTL NAND gate and explain.
4. Design a 2 input CMOS NOR gate and explain the operation.

ANUBOSE INSTITUTE OF TECHNOLOGY

KSP ROAD, PALONCHA- 507115
(Approved by AICTE, New Delhi, Affiliated to JNTU, Hyderabad)
II MID Term Examinations
 Course: II B.Tech-I-SEM Branch: ECE Date: 02-05-2023
Subject Name: DSD Answer any TWO questionsMax. Marks: 10M

1. Discuss about parity bit generator.

2. Design a mod-3 counter.
3. Draw and explain the operation of CMOS open drain and CMOS transmission gate.
4. Explain the operation tristate TTL with the help of circuit diagram.

ANUBOSE INSTITUTE OF TECHNOLOGY

KSP ROAD, PALONCHA- 507115
(Approved by AICTE, New Delhi, Affiliated to JNTU, Hyderabad)

II MID Term Examinations, May- 2023

Course: II B.Tech I SEM Subject Name: DSD
Name: ___________________________________ H.T NO: ____________________

Answer all questions. All questions carry equal marks Time: 20min
Marks: 10M

1. The combinational circuits are______ than sequential circuits [ ]

A) slower B) faster C) same speed D) None
2. In combinational circuits the o/p depends on ________i/p [ ]
A) present B) past C) A & B D) None
3. Serial binary adder is a _______circuit [ ]
A) combinational B) sequential C) A or B D) None
4. A 4 bit parallel adder is designed using _______number of full adders [ ]
A)2 B) 4 C) 5 D) 3
5. An SR latch is a [ ]
A) Combinational circuit B) Synchronous sequential circuit C)One bit memory element
 D) One clock delay element
6. Synchronous counters are ________ than the ripple counters. [ ]
A) Slower B) Faster C) Moderate D)None
7. In S-R latch, if S=R=1, the present state of the latch is [ ]
A) 1 B) 0 C) Undetermined D) None
8. The DTL propagation delay is relatively ___________ [ ]
A) Large B) Small C) Moderate D) Negligible
9. The D- latch sometimes called as _____ Latch. [ ]
A) Flipflop B) Buffer C) Transparent D) None
10. ____ and______are building blocks of Sequential Circuits. [ ]
A) Flipflop B) Latches C) Both D) None
11. For Moore Sequential Circuit, the output depends on _____________________ State.
12. The state reduction technique avoids _________________________states.
13. The acronym of SIPO is______________________.
14. The _____________________ register has capability of both shifts and parallel load.
15. The __________________ are used to transfer and storage of data in the registers.
16. A major advantage of DTL over the earlier resistor–transistor logic is the ___________.
17. Which logic family has lower power dissipation ______________________.
18. The fastest logic family ____________________________.
19. Ring counter is also called as ____________________________.
20. ____________ and _______________ models are used for the design of finite state
machines.