1. Write a Excess 3-to-Seven Segment Verilog Module.

Simulate the created module by

providing a testbench and a timing waveform.
Program:

module segment7(bcd,seg);
input [3:0] bcd;
output [6:0] seg;
reg [6:0] seg;
always @ (bcd)
begin
case (bcd) //case statement
0 : seg = 7'b0000001;
1 : seg = 7'b1001111;
2 : seg = 7'b0010010;
3 : seg = 7'b0000110;
4 : seg = 7'b1001100;
5 : seg = 7'b0100100;
6 : seg = 7'b0100000;
7 : seg = 7'b0001111;
8 : seg = 7'b0000000;
9 : seg = 7'b0000100;
default : seg = 7'b1111111;
endcase
end
endmodule

Testbench:

module tb_segment7;
reg [3:0] bcd;
wire [6:0] seg;
integer i;
segment7 uut (.bcd(bcd),.seg(seg));
initial begin
for(i = 0; i < 16; i = i+1) //loop for 0 to 15.
begin
bcd = i;
#10; //wait for 10ns
end
end
endmodule
Timing waveform:
2. Design an FSM that will detect a sequence “111001”. Write a module and a corresponding
testbench for the Sequence Recognizer Circuit. Please include also the FSM model in the
documentation.

module det_101101( input clk, input rstn, input in, output reg out);
parameter S000 = 0,
S001 = 1,
S010 = 2,
S011 = 3,
S100 = 4,
S101 = 5,
S110 = 6;
reg [2:0] cur_state, next_state;

always @(posedge clk)

begin
#1 out =0;
end

always @ (posedge clk) begin

if (rstn)
cur_state <= S000;
else
cur_state <= next_state;
end

always @ (cur_state or in) begin

case (cur_state)
S000 : begin
if (in) next_state = S001;
else next_state = S000;
end

S001: begin
if (in) next_state = S001;
else next_state = S010;
end
S010: begin
if (in) next_state = S011;
else next_state = S000;
end

S011: begin
if (in) next_state = S100;
else next_state = S010;
end
S100 : begin
if (in) next_state = S001;
else next_state = S101;
end
S101 : begin
if (in) begin next_state = S011 , out =1 ; end
else next_state = S000;
end

end
endcase
end
endmodule
Testbench:
module tb;
reg clk, in, rstn, i;
wire out;
reg [1:0] l_dly;
reg tb_in;
integer loop = 1;

always #10 clk = ~clk;

det_101101 u0 ( .clk(clk), .rstn(rstn), .in(in), .out(out) );

initial begin
clk <= 0;
rstn <= 0;
in <= 0;

repeat (5) @ (posedge clk);

rstn <= 1;

@(posedge clk) in <= 1;

@(posedge clk) in <= 1;
@(posedge clk) in <= 1;
@(posedge clk) in <= 0;
@(posedge clk) in <= 0;
@(posedge clk) in <= 1;
@(posedge clk) in <= 1;
@(posedge clk) in <= 1;
@(posedge clk) in <= 0;
@(posedge clk) in <= 0;
@(posedge clk) in <= 1;

for ( i = 0 ; i < loop; i = i + 1)

begin
l_dly = $random;
repeat (l_dly) @ (posedge clk);
tb_in = $random;
in <= tb_in;
end

#100 $finish;
end
endmodule