EX.

NO:11 DESIGN AND IMPLEMENTATION OF FINITE STATE MACHINE USING FPGA

(MOORE AND MEALY MACHINE)
DATE:

Aim
To design, simulate and implement FSM Moore and Mealy machine in FPGA using Verilog HDL

Software Required
 Vivado 2014.4

Hardware Required
 Nexys A7: FPGA Trainer Board

Theory

The synchronous sequence machine is described by the finite state machine (FSM),
which is an abstract model. In a sequential circuit, the output is determined by the current input as
well as previous history, necessitating an endless storage capacity.

Finite state machines are utilized because machines with infinite storage capacity are
impossible to implement. Finite state machines are sequential circuits with a finite number of
ways in which their past history might affect their future behavior.

Machines with a finite number of states are known as finite state machines. There are a
limited number of memory devices in any finite-state system. We can construct a periodic
sequence of fewer than or equal to n-states using an n-state machine.

There are two types of finite state machines (FSM). The way the output is generated is
the main difference between them.
o Moore Machine
o Mealy Machine

The fundamental difference between the Mealy and Moore machines is that the dependency
of output is on the current state and input. The current output of the Moore machine is solely
determined by its current state. The current output of the Mealy machine is determined by the
present state and present external inputs. Moore and Mealy machines are quite complex
machines.

Moore and mealy machines are generators. Moore and Mealy machines have no knowledge
of a final state because they aren't used to recognize languages. Moore and Mealy machines are
finite-state deterministic devices.
Moore Machine

State Diagram State Table

Next State
Present State Out
in = 0 in = 1
S0 S1 S0 0
S1 S1 S2 0
S2 S3 S0 0
S3 S1 S2 1

Program Test bench Program

module moore(out, in, rst, clk); module tb_moore();
output out; input in; input clk, rst; wire tb_out;
reg out; reg[1:0] state; reg tb_in; reg tb_clk, tb_rst;
moore uut(.out(tb_out),
parameter s0=2'd0, s1=2'd1, s2=2'd2, s3=2'd3;
.in(tb_in),.rst(tb_rst),.clk(tb_clk));
always @(posedge clk or negedge rst) initial begin
if(rst==0) begin state=s0; out=0; end tb_clk=1;tb_rst=1;
else begin #10
case (state) tb_in=0; #10 tb_in=1; #10
s0: begin out=0; if(in==0) state=s1; else state=s0; end tb_in=0; #10 tb_in=1; #10
s1: begin out=0; if(in==0) state=s1; else state=s2; end tb_in=1; #10 tb_in=1;
end
s2: begin out=0; if(in==0) state=s3; else state=s0; end
always #5 tb_clk = ~tb_clk;
s3: begin out=1; if(in==0) state=s1; else state=s2; end initial #100 $stop;
default: state=s0; endcase end endmodule endmodule
Program to Implement Moore Model in FPGA
module moore(out, in, rst, clk); else begin
output out; case (state)
input in; input clk, rst; s0: begin out=0; if(in==0) state=s1;
reg out; reg[1:0] state; else state=s0; end
parameter s0=2'd0, s1=2'd1, s2=2'd2, s3=2'd3; s1: begin out=0; if(in==0) state=s1;
reg newclk; else state=s2; end
reg [27:0] count=0; s2: begin out=0; if(in==0) state=s3;
always @ (posedge clk) else state=s0; end
begin s3: begin out=1; if(in==0) state=s1;
count=count+1; else state=s2; end
newclk=count[27]; default: state=s0;
end endcase
always @(posedge newclk or negedge rst) end
if(rst==0) endmodule
begin state=s0; out=0; end
Procedure

1. Double Click on “ vivado2014.4”

2. Clickcreate new project
3. Clicknext
4. Enter your project name,and click, next.,
5. Select “RTL project” and click next.,
6. Click create file
7. Select your file type as Verilog
8. Enter your “file name” and click ok.,
9. Clicknext.,
10. Click next.,
11. Create xdc file
11.a, Clickcreate file.,
11.b. Enter your “xdc name” and click ok.,
12. Clicknext.,
13. Select your ic details.,(ex:Nexys A7” xc7a100tcpg324-1”)
14. Click finish.,
15. Enter your input and output details and click ok, else click cancel directly enter your program and
declare your input output
16. Goto project manager and click your verilog file under Design Sources.,
17. Enter your program and save file.,
Mealy Machine

State Diagram State Table

Next State Out

Present State
in = 0 in = 1 in = 0 in = 1
S0 S1 S0 0 0
S1 S1 S2 0 0
S2 S3 S0 0 0
S3 S1 S2 0 1
Program Test bench Program
module mealy_verilog_code(out, in, rst, clk); module tb_mealy_verilog_code();
output out; input in; input clk, rst; wire tb_out;
reg out; reg[1:0] state; reg tb_in;
reg tb_clk, tb_rst;
parameter s0=2'd0, s1=2'd1, s2=2'd2, s3=2'd3;
mealy_verilog_code
always @(posedge clk or negedge rst) dut(.out(tb_out),.in(tb_in),.clk(tb_clk),.rst(tb_rst));
if(rst==0) begin state=s0; out=0; end initial begin
else begin tb_clk=1;tb_rst=1;
case (state) #20
s0: if(in==0) begin out=0; state=s1; end tb_in=0; #10
else begin out=0; state=s0; end tb_in=1; #10
tb_in=0; #10
s1: if(in==0) begin out=0; state=s1; end
tb_in=1; #10
else begin out=0; state=s2; end tb_in=1; #10
s2: if(in==0) begin out=0; state=s3; end tb_in=0;
else begin out=0; state=s0; end end
s3: if(in==0) begin out=0; state=s1; end always #5 tb_clk = ~tb_clk;
else begin out=1; state=s2; end initial #100 $stop;
default: state=s0; endmodule
endcase end endmodule
Program to Implement Melay Model in FPGA
module mealy_verilog_code(out, in, rst, clk); if(rst==0) begin state=s0; out=0; end
output out; else begin
input in; case (state)
input clk, rst; s0: if(in==0) begin out=0; state=s1; end
reg out; else begin out=0; state=s0; end
reg[1:0] state; s1: if(in==0) begin out=0; state=s1; end
parameter s0=2'd0, s1=2'd1, s2=2'd2, s3=2'd3; else begin out=0; state=s2; end
reg newclk; s2: if(in==0) begin out=0; state=s3; end
reg [27:0] count=0; else begin out=0; state=s0; end
always @ (posedge clk) s3: if(in==0) begin out=0; state=s1; end
begin else begin out=1; state=s2; end
count=count+1; default: state=s0;
newclk=count[27]; endcase
end end
always @(posedge newclk or negedge rst) endmodule
Steps for Test bench creation

18. Goto project manager  right click on Simulation SourcesSelect Add or create simulation sources,
19. Click on Create File  Select your file type as Verilog
20. Enter your “file name” and click Finish.,
21. Goto project manager and click your verilog file under Simulation Sources.,
22. Enter your program and save file.,
23. Click on”run synthesis”Running synthesis.,

Steps for Simulation

24. After successful synthesis completion, close the pop-up window and select Simulation  Run
Behavioural Simulation is enough to see output waveform If we run through testbench program.
25. Else After the Run Behavioral Simulation, Force the value for inputs by Force Constant option and
save the waveform
26. Run the simulation by clicking on Run for amount of time previously set Output of simulation is
verified with the help of waveform
RTL Schematics and Output

RTL
Schematics

Moore
Machine

Output

RTL
Schematics

Mealy
Machine

Output
Steps for Implementation

1. Click open synthesis design and click ok.,

2. Create floor plan details
a. Clickconstraints wizard
b. Click define target
c. Select your xdc file and click ok.,
d. Click schematic(F4)
e. ClickI/O Ports
f. Enter your pin details.,
g. Select I/O STDLVCMOS33
h. Clicksave, and yes,
3. Clickrun implementation
4. ClickGenerate Bitstream and click “open target”
5. Opentargetopen new target.,
6. ClickAuto connect.,
7. Clickprogram deviceselect your device
8. Clickprogram
Implemented Moore in
Nexys A7: FPGA Trainer
Board

Output : 1

Input : 0101

Implemented Melay in
Nexys A7: FPGA Trainer
Board

Output : 1

Input : 0101
Result

Thus the simulation of Moore and Mealy machines of FSM were done, implemented in Nexys
A7 FPGA Trainer Board and outputs were verified

Inference from the Result:

Practice Question

Design and simulate the performance of a module to detect ‘00’ and ‘11’ in a 2 bit counter