TASK-3

Mohammed Mohsin Jawed

21BCT0226
 1. Write Verilog code for JK, D, T Flip-flops along with
Testbench

JK Flip flop
Code:
//21BCT0226
//Mohammed Mohsin Jawed
module jk_ff ( input j, input k, input clk, output q);

reg q;

always @ (posedge clk)

case ({j,k})
2'b00 : q <= q;
2'b01 : q <= 0;
2'b10 : q <= 1;
2'b11 : q <= ~q;
endcase
endmodule
 Test bench:
//21BCT0226

//Mohammed Mohsin Jawed

module tb_jk;

reg j; reg k; reg clk;

always #5 clk = ~clk;

jk_ff jk0 ( .j(j),

.k(k),

.clk(clk),
.q(q));

initial begin j <= 0;

k <= 0;

#5 j <= 0;

k <= 1;
#20 j <= 1;

k <= 0;

#20 j <= 1;

k <= 1;

#20 $finish; end

initial

$monitor ("j=%0d k=%0d q=%0d", j, k, q); endmodule

D Flip flop
Code:
//21BCT0226
//Mohammed Mohsin Jawed

module dff (input d,

input rstn,
input clk,
output reg q);

always @ (posedge clk)

if (!rstn)
q <= 0;
else
q <= d;
endmodule
Test bench:
//21BCT0226
//Mohammed Mohsin Jawed
module tb_dff;
reg clk;
reg d;
reg rstn;
reg [2:0] delay;

dff dff0 ( .d(d),

.rsnt (rstn),
.clk (clk),
.q (q));

always #10 clk = ~clk;

initial begin
clk <= 0;
d <= 0;
rstn <= 0;

#15 d <= 1;
#10 rstn <= 1;
for (int i = 0; i < 5; i=i+1) begin
delay = $random;
#(delay) d <= i;
end
end
endmodule
 T Flip flop
Code:
//21BCT0226
//Mohammed Mohsin Jawed
module tff ( input clk, input rstn, input t, output reg q);

always @ (posedge clk) begin

if (!rstn)
q <= 0;
else
if (t)
q <= ~q;
else
q <= q;
end
endmodule
 Test bench:

//21BCT0226

//Mohammed Mohsin Jawed

module tb;

reg clk;

reg rstn;

reg t;

tff u0 ( .clk(clk),

.rstn(rstn),

.t(t),

.q(q));

always #5 clk = ~clk;

initial begin

{rstn, clk, t} <= 0;

$monitor ("T=%0t rstn=%0b t=%0d q=%0d", $time, rstn, t, q);

repeat(2) @(posedge clk);

rstn <= 1;

for (integer i = 0; i < 20; i = i+1) begin

reg [4:0] dly = $random;

#(dly) t <= $random;

end

#20 $finish;

end

endmodule
2. Write the Verilog code and Testbench for SISO, SIPO, PISO,
SIPO.

SISO:
Code:
//21BCT0226

//Mohammed Mohsin Jawed

module sisomod(clk,clear,si,so); input clk,si,clear;

output so; reg so;

reg [3:0] tmp;

always @(posedge clk ) begin

if (clear)

tmp <= 4’b0000; else

tmp <= tmp << 1;

 tmp[0] <= si; so = tmp[3];

end
endmodule

Test bench:
//21BCT0226

//Mohammed Mohsin Jawed

module sisot_b;

reg clk; reg clear; reg si; wire so;

sisomod uut (.clk(clk),

.clear(clear),.si(si),.so(so)); initial
begin

clk = 0;

clear = 0;

si = 0;

#5 clear=1’b1;

#5 clear=1’b0;

#10 si=1’b1;

#10 si=1’b0;

#10 si=1’b0;

#10 si=1’b1;

#10 si=1’b0;

#10 si=1’bx;
end

always #5 clk = ~clk; initial #150

$stop;

endmodule
 SIPO:
Code:

//21BCT0226
//Mohammed Mohsin Jawed

module sipomod(clk,clear, si, po);

input clk, si,clear;
output [3:0] po;
reg [3:0] tmp;
reg [3:0] po;
always @(posedge clk) begin
if (clear)
tmp <= 4’b0000;
else
tmp <= tmp << 1; tmp[0] <= si;
po = tmp;
end
endmodule
Test bench:
//21BCT0226

//Mohammed Mohsin Jawed

module sipot_b;

reg clk; reg clear; reg si;

wire [3:0] po;

sipomod uut (.clk(clk),.clear(clear),

.si(si),.po(po) ); initial begin

clk = 0;

clear = 0;

si = 0;

#5 clear=1’b1;

#5 clear=1’b0;

#10 si=1’b1;

#10 si=1’b0;

#10 si=1’b0;

#10 si=1’b1;

#10 si=1’b0;

#10 si=1’bx;

end

always #5 clk = ~clk; initial #150

$stop;

endmodule
 PISO:
Code:
//21BCT0226
//Mohammed Mohsin Jawed

module Shiftregister_PISO(Clk, Parallel_In,load, Serial_Out);

input Clk,load;
input [3:0]Parallel_In;
output reg Serial_Out;
reg [3:0]tmp;
always @(posedge Clk)
begin
if(load) tmp<=Parallel_In;
else
begin Serial_Out<=tmp[3];
tmp<={tmp[2:0],1'b0};
end
end
endmodule
PIPO:
Code:
//21BCT0226
//Mohammed Mohsin Jawed

module pipomod(clk,clear, pi, po);

input clk,clear;
input [3:0] pi;
output [3:0] po;
wire [3:0] pi;
reg [3:0] po;
always @(posedge clk)
begin
if (clear)
po<= 4’b0000;
else
po <= pi;
end
endmodule
Testbench:
//21BCT0226
//Mohammed Mohsin Jawed

module pipot_v;
reg clk; reg clear;
reg [3:0] pi;
wire [3:0] po;
pipomod uut
(.clk(clk),.clear(clear),.pi(pi),.po(po
) ); initial begin
clk = 0;
clear = 0;
pi = 0;
#5 clear=1’b1;
#5 clear=1’b0;
#10 pi=4’b1001;
#10 pi=4’b1010;
#10 pi=4’b1011;
#10 pi=4’b1110;
#10 pi=4’b1111;
#10 pi=4’b0000;
end
always #5 clk = ~clk;
initial #150 $stop;
endmodule
 3. Design bit universal shift register and write Verilog code.
Code:

//21BCT0226
//Mohammed Mohsin Jawed
module juniversalShiftRegister(DATAOUT, clock, reset, MODE, DATAIN);
output reg [3:0] DATAOUT;
input clock, reset;
input [1:0] MODE;
input [3:0] DATAIN;
always @(posedge clock)
begin
if(reset) DATAOUT <= 0;
else
begin
case(MODE)
2'b00 : DATAOUT <= DATAOUT;
2'b01 : DATAOUT <= {DATAIN[0], DATAOUT[3:1]};
2'b10 : DATAOUT <= {DATAOUT[2:0], DATAIN[0]};
2'b11 : DATAOUT <= DATAIN;
endcase
end
end
endmodule
Testbench:
//21BCT0226

//Mohammed Mohsin Jawed

module juniversalShiftRegisterTb;

wire [3:0] DATAOUT;

reg clock, reset;

reg [1:0] MODE;

reg [3:0] DATAIN;

juniversalShiftRegister

jusr(DATAOUT, clock, reset,

MODE, DATAIN);

initial

begin

clock =0; MODE = 2'b00; DATAIN

= 4'b0000;

reset = 1; #10; reset = 0; #10;

$display("RSLT\tD == DOUT");

MODE = 2'b00; reset = 1; #10;

reset = 0; #10;

MODE = 2'b01; DATAIN =

4'b0011; #10;

if ( DATAOUT === 4'b1000 )

$display("PASS\t%p is %p with

%p", DATAIN, MODE, DATAOUT);

else

$display("FAIL\t%p is %p with

%p", DATAIN, MODE, DATAOUT);

MODE = 2'b01; DATAIN =

4'b0011; #10;

if ( DATAOUT === 4'b1100 )

$display("PASS\t%p is %p with

%p", DATAIN, MODE, DATAOUT);

else

$display("FAIL\t%p is %p with

%p", DATAIN, MODE, DATAOUT);

MODE = 2'b00; reset = 1; #10;

reset = 0; #10; MODE = 2'b10;

DATAIN = 4'b0111; #10;

if ( DATAOUT === 4'b0001 ) //

$display("PASS\t%p is %p with

%p", DATAIN, MODE, DATAOUT);

else

$display("FAIL\t%p is %p with

%p", DATAIN, MODE, DATAOUT);

MODE = 2'b10; DATAIN =

4'b0111; #10;

if ( DATAOUT === 4'b0011 ) //

$display("PASS\t%p is %p with

%p", DATAIN, MODE, DATAOUT);

else

$display("FAIL\t%p is %p with

%p", DATAIN, MODE, DATAOUT);

MODE = 2'b00; reset = 1; #10;

reset = 0; #10; MODE = 2'b11;

DATAIN = 4'b1010; #10;

if ( DATAOUT === 4'b1010 )

$display("PASS\t%p is %p with

%p", DATAIN, MODE, DATAOUT);

else

$display("FAIL\t%p is %p with

%p", DATAIN, MODE, DATAOUT);

#20;

$finish;

end

initial

begin

$dumpfile("dump.vcd");

$dumpvars;

end

always #5 clock = ~clock;

endmodule