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  • 21BCT0226 VL2022230104560 Ast03

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    Mohammed Mohsin
    5 views26 pages
    The document describes tasks to implement combinational logic circuits using multiplexers, decoders/demultiplexers in Verilog. The tasks include: 1) Implementing Boolean functions F and F' using multiplexers. 2) Implementing F and F' using demultiplexers. 3) Writing Verilog code for a 32x1 multiplexer and full subtractor using a 4x1 multiplexer. 4) Implementing F and F' using decoders. 5) Designing a decimal to binary converter using an encoder. Verilog code and test benches are provided for each implementation.

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    21BCT0226_VL2022230104560_AST03

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    The document describes tasks to implement combinational logic circuits using multiplexers, decoders/demultiplexers in Verilog. The tasks include: 1) Implementing Boolean functions F and F' using multiplexers. 2) Implementing F and F' using demultiplexers. 3) Writing Verilog code for a 32x1 multiplexer and full subtractor using a 4x1 multiplexer. 4) Implementing F and F' using decoders. 5) Designing a decimal to binary converter using an encoder. Verilog code and test benches are provided for each implementation.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    5 views26 pages

    21BCT0226 VL2022230104560 Ast03

    Uploaded by

    Mohammed Mohsin
    The document describes tasks to implement combinational logic circuits using multiplexers, decoders/demultiplexers in Verilog. The tasks include: 1) Implementing Boolean functions F and F' using multiplexers. 2) Implementing F and F' using demultiplexers. 3) Writing Verilog code for a 32x1 multiplexer and full subtractor using a 4x1 multiplexer. 4) Implementing F and F' using decoders. 5) Designing a decimal to binary converter using an encoder. Verilog code and test benches are provided for each implementation.

    Copyright:

    © All Rights Reserved
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    of 26

    Task-3

    Mohammed Mohsin Jawed


    21BCT0226
    Implementation of combinational circuits using Multiplexer, Decoder/
    Demultiplexer

    1. Using your register number formulate expressions in SOP and POS for F and
    F'. Implement F and F’ using MUX.
    2. Using your register number formulate expressions in SOP and POS for F and F’.
    Implement F and F’ using DEMUX.
    3. Write Verilog code & Test Bench in Gate/Data flow/Behavioral model for (a)
    32X1 MUX (b) Full Subtractor using 4X1 MUX.
    (a) 32X1 MUX
    Data flow:

    Output:
    Behavioural:

    Output:
    Testbench:
    Output:

    (b) Full Subtractor using 4X1 MUX.

    Gate level:
    Output:

    Data Flow

    Output:
    Behavioural:

    Output:
    Testbench:

    Output:
    4. using your register number formulate expressions in SOP for F and F’.
    Implement F and F’ using Decoder. Write Verilog code and test bench.
    Output:
    Output:
    Testbench:

    Output:
    5. Design Decimal to binary convertor using Encoder. Write Verilog code and test
    bench.
    Output:

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