SDM College of Engineering and Technology, Dharwad

Department of Electronics and Communication Engineering

HDL Programming Lab (18UECL405) Question bank
1. Write a Verilog code to implement full adder using two half adders and OR gate using structural style of
modeling.
2. Write a Verilog code to implement full subtractor using two half subtractor and OR gate using structural
style of modeling.
3. Write a Verilog code to implement 3:8 Decoder using two 2:4 Decoder with enable signal using
Structural style modeling.
4. Write a Verilog code to implement 4:1 Multiplexer using 2:1 MUX in structural style of modeling
5. Write a Verilog code to implement 8:1 Multiplexer using 4:1 Multiplexer and 2:1 MUX.
6. Write a Verilog code to implement 4- bit Gray to Binary code converter and binary to Excess-3 code
converter.
7. Write a Verilog code to implement 4-bit comparator using conditional operator.
8. Write a Verilog code to implement Full subtractor using 1:4 DEMUX.
9. Write a verilog code to implement full adder using 4:1 MUX
10. Write a verilog code to implement AND gate using 2:1 MUX
11. Write a verilog code to implement OR gate using 2:1 MUX
12. Write a verilog code to implement NOR gate using 2:1 MUX
13. Write a verilog code to implement NAND gate using 2:1 MUX
14. Write a verilog code to implement sum expression of half adder using 2:1 MUX
15. Write a verilog code to implement 6-bit parity detector.
16. Write a verilog code to implement BCD error detector.
17. Write a verilog code to implement full Subtractor using 4:1 MUX
18. Write a verilog code to implement 4:1 MUX using conditional statement
19. Write a verilog code to count the number of 1’s in the given 8-bit vector.
20. Write a verilog code to count the number of 0’s in the given 8-bit vector.
21. Write a verilog code to rotate 8-bit vector by 2 times to its left.
22. Write a verilog code to rotate 8-bit vector by once to its right.