University of Engineering

&
Technology, Taxila

DSD
Lab Manual# 15
GROUP NO 3

6TH SEMESTER

OMEGA SECTION

SUBMITTED TO: ENGR.ASGHAR ISMAIL

Dated;
18/07/2023
 LAB MANUAL NO 15

TASK NO 1
Write a Verilog code for designing the 4-digit number conditional sum adder.
Objectives:
The objective of this project is to design a Verilog code for a 4-digit number conditional sum adder.
The adder should perform addition on two 4-digit numbers while considering a conditional flag. If
the flag is set, the adder should perform the addition; otherwise, it should output the first input
number as the result. The goal is to implement the Verilog code for the adder and evaluate its
functionality and performance.

Apparatus List:
• Verilog HDL
• FPGA Development Board
• Xilinx Vivado or any other Verilog simulation and synthesis tool

Procedure:
• Design the Verilog code for the 4-digit number conditional sum adder.
• Simulate the Verilog code to verify its correctness and functionality.
• Synthesize the Verilog code to obtain the gate-level implementation.
• Implement the synthesized design on an FPGA development board.
• Verify the functionality and performance of the adder on the FPGA.

Logic Circuit:
The 4-digit number conditional sum adder takes two 4-digit numbers and a conditional flag as
inputs. It performs addition on the two numbers only if the flag is set; otherwise, it outputs the first
input number as the result.
The logic circuit consists of multiple full adders connected in a cascaded manner. Each full adder
adds three bits: the corresponding bits from the two input numbers (A and B) and the carry-in
(Cin) from the previous stage. The output sum (S) from each full adder is fed to the next stage as
the carry-in (Cin) for the subsequent full adder. The carry-out (Cout) from the last stage is the final
carry-out of the adder.
Additionally, a multiplexer is used to select between the conditional sum (output of the adder) and
the first input number (A) based on the value of the conditional flag. If the flag is set, the output is
the sum; otherwise, it is the first input number (A).

Truth Table:
The truth table for the 4-digit number conditional sum adder can be constructed by considering
all possible combinations of the input numbers (A and B), the conditional flag (Flag), and the
resulting output (Result). It would have 16 rows corresponding to all possible 4-digit binary
numbers.

K-Map:
Karnaugh Maps (K-Maps) are applicable for the 4-digit number conditional sum adder, as it is a
combinational circuit with multiple inputs and outputs.
Boolean Expression:
The Boolean expression for the 4-digit number conditional sum adder can be derived by analyzing
the behavior of the circuit. It involves the logical operations performed by the full adders and the
multiplexer.
Let's go through each group and derive the corresponding Boolean terms:
Group 1: A3A2
Group 2: A1A0
The Boolean terms can be derived as follows:
Term 1: A3A2
Term 2: A1A0
The Boolean expression for the Result output can be written as:
Result = Term 1 + Term 2
Therefore, the Boolean expression for the Result output of the 4-digit number conditional sum
adder is:
Result = A3A2 + A1A0

Schematic Diagram:
A schematic diagram represents the gate-level implementation of the 4-digit number conditional
sum adder. It shows the interconnections between logic gates and the overall structure of the
circuit.
Code:
module conditional_sum_adder(
input [3:0] A,
input [3:0] B,
input Flag,
output reg [3:0] Result
);

always @(A, B, Flag)

begin
if (Flag)
Result <= A + B;
else
Result <= A;
end

endmodule

Results:
Simulation Results:
FPGA Implementation Results:

Conclusion:
The Verilog code implementation of the 4-digit number conditional sum adder provides an
effective solution for adding two 4-digit numbers with a conditional flag. The circuit's behavior and
performance can be evaluated through simulations, synthesis, and FPGA implementation. The
results obtained from these evaluations will help analyze the correctness, efficiency, and
effectiveness of the 4-digit number conditional sum adder.

Task No 2
Compare the designs of conditional sum adder ,ripple carry, carry select and carry
lookahead adders for efficiency and area overhead. Fill the following table with your
results.

24 ns 4
10 ns 2
72
72nsns 12
6 ns 1