To be submitted by 3122213002048 B Krithika

To be Verified by 3122213002027 Gauri Jayakrishnan Nair

Date of Submission 10-11-2022

Topics VHDL Coding

1. What is meant by dataflow modelling?

2. What is the meaning of <= operator in dataflow modelling?
3. Write the keyworks for logic gates used in dataflow modelling.
4. Write the VHDL code to model a NOT Gate using data flow model.
5. Write the VHDL code to model a OR Gate using data flow model.
6. Write the VHDL code to model a AND Gate using data flow model.
7. Write the VHDL code to model a NAND Gate using data flow model.
8. Write the VHDL code to model a NOR Gate using data flow model.
9. Write the VHDL code to model a XOR Gate using data flow model.
10. Write the VHDL code to model a XNOR Gate using data flow model.
11. State the difference between array and records types.
12. What is the difference between function and procedure in VHDL? Give suitable
examples.
13. Write a VHDL code to model a Home Alarm System.
14. Write a VHDL code to model a Digital Safe System.
15. Write VHDL source code for the following combinational logic circuits using
behavioural, data flow and structural modelling styles. Write the VHDL testbench to
verify the functionality.
a. 2-to-1 Multiplexer
b. 4-to-1 Multiplexer
c. 8-to-1 Multiplexer
16. Implement the four-to-one multiplexer in VHDL using
a. case statement.
b. if statement.