Sequential Circuit Design

Jawahar .A
SSN College of Engineering
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Session Objectives

• To learn the basic block in designing a sequential circuit -

Latches & Flip-flops
• To know the different types of Latches and flip-flops - SR,
JK, D & T

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Session Outcomes

At the end of the session, students will be able to

•Define, identify and differentiate the digital circuits as
combinational and sequential circuits.
•Explain the working of a latch and flip-flop.

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Outline

• Types of digital circuits

– Combinational & sequential circuits
• Latches and Flip-flops
– Characteristic table, characteristic equation and
excitation table

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Introduction
• Combinational circuits
 contains no memory elements
 the outputs depends on the inputs
• Sequential circuits
Inputs Combinational
Circuit Outputs
Memory
Elements

 a feedback path
 the state of the sequential circuit
 (inputs, current state)  (outputs, next state)
 synchronous: the transition happens at discrete instants of time
 asynchronous: at any instant of time
Synchronous sequential circuits
 a master-clock generator to generate a periodic train of clock
pulses
 the clock pulses are distributed throughout the system
 clocked sequential circuits
 most commonly used
 no instability problems
 single bit storage element: flip-flop
 binary cells capable of storing one bit of information
 two outputs: one for the normal value and one for the
complement value
 maintain a binary state indefinitely until directed by an
input signal to switch states
Inputs Combinational Outputs
circuit
Flip Flops
Next
state Present
state

Timing signal
(clock)
Timing signal
Fig. Block diagram
(clock)of Clocked Sequential Circuit

Clock
a periodic external event (input)
Clock
• synchronizes when current state changes happen
• keeps system well-behaved
• makes it easier to design and build large systems
Latches:
A basic type of flip flop is a latch. Latches are made from logic
gates like NAND, NOR, AND, OR, Inverter gates.
A stable value can be stored at inverter outputs

0 1

1 0

State 1 State 2
• SR Latch

more complicated types can be built upon it

direct-coupled RS flip-flop: the cross-coupled connection
an asynchronous sequential circuit
 (S,R)= (0,0): no operation
 (S,R)=(0,1): reset (Q=0, the clear state)
 (S,R)=(1,0): set (Q=1, the set state)
 (S,R)=(1,1): indeterminate state (Q=Q'=0)
 consider (S,R) = (1,1)  (0,0)
 SR latch with NAND gates

 Latch made from cross-coupled NANDs

 Sometimes called S’-R’ latch
 S=0 and R=0 generates unpredictable results
SR Latch with control input

 Occasionally, desirable to avoid latch changes

 C = 0 disables all latch state changes
 Control signal enables data change when C = 1
 Right side of circuit same as ordinary S-R latch.
D Latch
• eliminate the undesirable conditions of the indeterminate
state in the RS flip-flop
• D: data
• gated D-latch
• D  Q when C=1; no change when C=0

• Input value D is passed to output Q when C is high

• Input value D is ignored when C is low
Graphic Symbols for Latches:

Fig. Graphic symbols for different latches

 SR latch is based on NOR gates
 S’R’ latch based on NAND gates
 D latch can be based on either.
 D latch sometimes called transparent latch
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Flip-flops
• Latches respond to trigger levels on control inputs
– Example: If C = 1, input reflected at output
• Difficult to precisely time when to store data with latches
• Flip flops store data on a rising or falling trigger edge.
– Example: control input transitions from 0 → 1, data input
appears at output
– Data remains stable in the flip flop until next rising edge.

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Clocked RS Flip-flop
• Flip flop works when there is a transition in the clock.

Q S R Q(t + 1)
0 0 0 0
Clock
0 0 1 0
0 1 0 1
0 1 1 Indeterminate
(a) Logic
1 0 0 1
Diagram
1 0 1 0 SR 00 01 11 10
Q
1 1 0 1 0
1 1 1 Indeterminate 1
(b) Characteristic (c) Characteristic
Table Q (t +1) Equation
= S + R′Q ; SR = 0
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Clocked D Flip-Flop

Clock

(a) Logic
Diagram
Q D Q (t +1)
0 0 0
0 1 1
1 0 0
1 1 1 (c) Characteristic
Equation
Q (t + 1) = D
(b) Characteristic
Table
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Positive Edge-Triggered JK Flip-flop

• J - sets; K - resets
• J=K=1 → inverts output
Q J K Q (t + 1)
0 0 0 0
0 0 1 0
0 1 0 1
(a) Logic Diagram
0 1 1 1
JK 00 01 11 10
1 0 0 1 Q
1 0 1 0 0
1 1 0 1 1
1 1 1 0 (c) Characteristic
(b) Characteristic
Equation
Q (t + 1) = JQ′ + K′Q
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Table
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Clocked T Flip-flop

Q T Q (t +1) (a) Logic Diagram

0 0 0
0 1 1
1 0 1
1 1 0
(b) Characteristic (c) Characteristic
Table Q (t +Equation
1) = T ⊕ Q = TQ′ + T′Q
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Summary

• Difference between combinational and sequential logic

circuits
• Definition for latches
• Different types of latches such as SR NOR latch, SR NAND
latch and D-Latch
 Practice Questions

• What is forbidden state SR latch and how to overcome?

• Write the difference between latches and flip-flop
• Draw the state diagram for SR, JK, D and T flip-flop