Counters

Timing Diagram:
• Timing diagrams which show how each signal in the circuit varies as a
function of time
If at some instant of time the inverter
EX: input is 0, this 0 will propagate
through the inverter and cause the
output to become 1 after the inverter
delay.

The inverter output will continue to oscillate back and forth between 0 and 1, as shown in Figure (b),and it will
never reach a stable condition.
• Let us consider, a feedback loop which has two inverters in it, as shown
in Fig a.

In this case, the circuit has two stable conditions, often referred to as stable states.

If the input to the first inverter is 0, its output will be 1. Then, the input to the second inverter will be 1, and its output will
be 0. This 0 will feed back into the first inverter, but because this input is already 0, no changes will occur. The circuit is
then in a stable state
One-bit Memory Cell
• The basic bi-stable element has
1.The outputs Q and Q’ are always complementary
2.The circuit has two stable states.
The state corresponds to Q=1 is referred as I state or Set state.
The state corresponds to Q=0 is referred as 0 state or Reset State
3. If the circuit is in the set (1) state, it will remain in the set State and if the
circuit is in the Reset(0) state, it will remain in the reset state. This property of
the circuit shows that it can store 1-bit of digital information. Therefore the
circuit is called 1-bit memory cell.
4.The 1-bit information stored in the circuit is locked or latched in the circuit.
Therefore this circuit is also referred as Latch.
• Basically, latches and flip-flops are memory devices which can assume
one of two stable output states and which have one or more inputs that
can cause the output state to change.
• Latch:
A memory element that has no clock input is often called a latch

Flip Flop

A memory device that changes its output in response to a clock input and not in response to a data input.

Latches controlled by a clock transition are flip-flops

• Controlled latches are level-triggered

C
• Flip-Flops are edge-triggered

CLK Positive Edge

CLK Negative Edge

7
Latches
• SR Latch
S R Q
0 0 Q0 No change
0 1 0 Reset
1 0 1 Set
1 1 Q=Q’=0 Invalid

S’ R’ Q
0 0 Q=Q’=1 Invalid
0 1 1 Set
1 0 0 Reset
1 1 Q0 No change
8
Flip-Flop Characteristic Tables

D Q(t+1)
0 0 Reset
1 1 Set

J K Q(t+1)
0 0 Q(t) No change
0 1 0 Reset
1 0 1 Set
1 1 Q’(t) Toggle

T Q(t+1)
0 Q(t) No change
1 Q’(t) Toggle
9
Flip-Flop Characteristic Equations

D Q(t+1)
0 0
Q(n+1) = D
1 1

J K Q(t+1)
0 0 Q(t)
0 1 0 Q(n+1) = JQ’ + K’Q
1 0 1
1 1 Q’(t)

T Q(t+1)
0 Q(t)
Q(n+1) = T  Q
1 Q’(t)
10
COUNTERS
ASYNCHRONOUS SYNCHRONOUS
Flip-flops are connected in such a No connection between output of
way that output of first flip-flop first flip-flop and clock input of next
drives the clock for the next flip-flop. flip-flop.

All the flip-flops are not clocked All the flip-flops are clocked
simultaneously. simultaneously.

Logic circuit is simple even for more Design involves complex logic circuit
number of states. as number of states increases.

Main drawback is their low speed as As the clock is simultaneously given

the clock is propagated through to all flip-flops there is no problem
number of flip-flops before it of propagation delay.
reaches last flip-flop.
Asynchronous counter
• The term asynchronous refers to events, do not occur at the same time
• An Asynchronous counter is one in which the flip-flops within the counter don’t
change states exactly the same time because they don’t have a common clock pulse.
• As a natural consequence of this, not all flip-flops change state at the same time.
The second flip-flop can change state only after the output of the first flip-flop has
changed its state

Note: Both counters and registers comprise a cascaded arrangement of more than one flipflop
with or without combinational logic devices
 A 2-bit Asynchronous binary counter:

The clock input of an asynchronous counter is always connected

only to the LSB Flip-flop.

Asynchronous counter are also known as ripple counter

A ripple counter is a cascaded arrangement of flip-flops where the
output of one flip-flop drives the clock input of the following flip-
flop

The 2-bit counter exhibits four(4) different states

Note: In digital logic Q0 is always LSB unless other wise specified

A 3-bit Asynchronous binary counter:

A 3-bit Binary asynchronous Binary counter

State sequence of 3- bit counter

A Timing Diagram
observation
A 4-bit Asynchronous binary counter
A Timing Diagram

For the total delay time, the effect of CLK 8 or CLK 16 must propagate through four flip-flops
before Q3 Changes, So
Asynchronous Decade counter
𝑁
• A counter can have 2 states where N is number of flip-flops in the counter
• A Modulus of a counter is the number of unique states (K) through which the counter will sequence.
(or)
• The modulus (MOD number) of a counter is the number of different logic states it goes through before it
comes back to the initial state to repeat the count sequence.

• An n-bit counter that counts through all its natural states and does not skip any of the states has a modulus
of
• Counters can be designed to have a number of states in their sequence that is less then the maximum
number of states. This type of sequence is called Truncated sequence.
• Counter with ten states in their sequence are called Decade counter
• To obtain the truncated sequence, it is necessary to force the counter to recycle before going through all of
its possible states
• For example, the BCD decade counter must recycle back to the 0000 after the 1001 state.
• To determine the number of flip-flops required to build a counter having a given modulus, identify the
smallest integer m that is either equal to or greater than the desired modulus and is also equal to an
integral power of 2.
For instance, if the desired modulus is 10, which is the case in a decade counter, the smallest integer
greater than or equal to 10 and which is also an integral power of 2 is 16. The number of flip-flops in this
case would be 4,

In general, the arrangement of a

minimum number of N flip-flops
can be used to construct any
counter with a modulus given by
the equation

BCD Decade Counter sequence table

When the counter goes in to count ten
(1010), the decoding gate output goes
low and asynchronously reset(clear) all
flip-flops
 Synchronous counter
• The term synchronous refers to events that have fixed time
relationship with each other.
• A synchronous counter is one in which all the flip-flops in the counter
are clocked at the same time by a common clock pulse.

A 2-bit Synchronous Binary counter

A Timing Diagram
A 3-bit Synchronous Binary counter

Since the different flip-flops in a

synchronous counter are clocked at the
same time, there needs to be additional
logic circuitry to ensure that the various
flip-flops toggle at the right time
A 4-bit Synchronous Binary counter
A 4-bit Synchronous Decade counter
Operation

The FFo(Qo), toggles on each clock pulse, so the logic equations for its Jo and Ko inputs is

This equation is implemented by connecting Jo and Ko inputs to constant HIGH level

The FF1(Q1), changes on the next clock pulse each time Qo=1 and
Q3=0, so the logic equation for the J1 and K1 inputs is

This equation is implemented by ANDing Q0 and Q3 and connecting the gate

output to the J1 and K1 inputs of Flip-flop1

The FF2(Q2), changes on the next clock pulse each time both Qo=1 and Q1 =1. this requires an input logic
equation

This equation is implemented by ANDing Q0 and Q1 and connecting the gate output to the J2 and K2
inputs of Flip-flop2
The FF3(Q3), changes on the next clock pulse each time both Qo=1, Q1 =1 and Q2=1 (state 7) or when Qo=1
and Q3=1(state 9). this requires an input logic equation

This equation is implemented by AND/OR logic connected to the J3 and K3 inputs of Flip-
flop3
Up/Down synchronous Counter(Bidirectional
Counter)
It can have any specified sequence of states.

A 3 bit Synchronous Up/Down counter It counts in Up direction 0-1-2-3-4-5-6-7

And Counts in down direction 7-6-5-4-3-2-1-0
 Consider, the complete up/down sequence for a 3-bit binary counter

The arrows indicate the state-to-state movement of the counter for both Up/Down modes of
operation.
An examination of Qo for both up and down sequences show that FFo toggles on each clock
pulse, Thus Jo, Ko inputs of Ffo are Jo=Ko=1

For the UP sequence Q1 changes state on the next clock pulse when Qo=1.
For the DOWN sequence Q1 changes state on the next clock pulse when Qo=0

Under these conditions J1 and K1 expressed following equation

Note: