FSM

Finite State Machine

Finite State Machine
• An electronic machine which has
– external inputs
– externally visible outputs
– internal state
• Output and next state depend on
– inputs
– current state
Abstract Model of FSM
• Machine is M = ( S, I, O,  )
• S: Finite set of states
• I: Finite set of inputs
• O: Finite set of outputs
•  : State transition function
• Next state depends on present input and present state

Circuit representation of a
synchronous sequential
machine
For l inputs : x1, x2… xl, the input alphabet is given by:
𝑝= 2𝑙
For example, if a machine has two input variables x1 and x2
then its input alphabet I consists of four symbols (or
configurations), that is, I = {00, 01, 11, 10}.
For m outputs : z1, z2… zm, the output alphabet is given by:
The signal value at the output of each memory element is
referred to as the state variable, and {y1, y2, . . . , yk} constitutes
the set of state variables.
The combination of values at the outputs of the k memory
elements y1, y2, . . . , yk defines the present internal state (or
state) of the machine.
the entire set of states of the machine
Types of FSM
• Mealy Machine:
• Output depends on the present states and the input(s).
• Next state depends on the present states and the input(s).

• Moore Machine:
• Output depends on the present states only.
• Next state depends on the present states and the input(s).
Sequence Detector(An Example)
• It is a circuit which produces output 1 whenever a specific sequence is
detected in the input stream

• There are two possibilities of generating the output 1 based on input

data
• Overlapping
• Non- overlapping
Sequence Detector (An
overlapping example)
Problem: We wish to design a one-input one-output sequence detector that produces an
output value 1 every time the sequence 0101 is detected and an output value 0 at all other
times.

For example, if the input sequence is 010101 then the corresponding output sequence is
000101.
Solution:

State table for a sequence

detector
State diagram for a sequence (0101) detector

As there are 4 total states(A,B,C,D), it is a two state

variable problem lets it denoted as Y1 ,Y2
Output and excitation maps
 Logic diagram of a sequence detector.

D represents a delay
element like D Flip flop

Question: Is this a Best solution ?

Answer: May be not
 The better possible
solution

Old assignment New assignment

if we interchange the codes assigned to states C and D, and proceed again then we
will get

second state assignment requires less than half the number of gates for
 X1 and X2, carrying the two binary sequence
numbers to be added

one output, Z, which represents the sum.

Block Diagram of Serial Binary Adder

Consider the following addition of two binary

numbers:
x( ti ), z( ti ) represents the input and output at
instant t=ti

The output value at time ti is a function of the

input values x1 and x2 at that time and of the carry
that was generated at t i-1.
 Mealy FSM Serial Adder

A single flip flop is needed to represent the

two states (A and B)

Let A designate the state of the adder at ti if 0 carry generated at ti-1 and

Let B designate the state of the adder at ti if 1 carry generated at ti-1

A & B are internal states

The output value z(ti) is a function of the input values x1(ti) and x2(ti) and the state of the adder at time ti.
y
Y y
Moore Machine type FSM for Serial
Adder
• Output depends only on present state
• Since in both states A and B(Which represents the input carry either 0
or 1), it is possible to generate two outputs (i.e. sum can be 0 or 1)
depending on the input, a Moore-type FSM will need more than two
states
• A0: carry is 0 sum is 0
• A1: carry is 0 sum is 1
• B0: carry is 1 sum is 0
• B1: carry is 1 sum is 1
𝑧 =𝑦 1
Mealy Vs Moore Machine

Mealy Machine Moore Machine

• Output is a function of the present state and the • Output is a functions of only the present state
present inputs and are independent of the inputs
• less number of states and thereby less hardware • More no. of states required
to solve any problem.
• the output is generated one clock cycle earlier. • the output remains stable over entire clock
• one important disadvantage associated with such
period and changes only when there occurs a
circuit. The input transients, glitches etc. (if any) state change at clock trigger based on input
are directly conveyed to the output. available at that time.
• Mealy machines react faster to inputs as it reacts • Moore machine are safer to use
in the same cycle and need not wait for the clock
to arrive and hence if we want output transitions
to be synchronized while input can change any
time Mealy model is not preferred
State Reduction
• The reduction in the number of flip-flops in a sequential circuit is
referred to as the state-reduction problem keeping the input output
relation unchanged
• Remove the redundant states from the state table
Given a state diagram/ state table

consider the input sequence

01010110100 starting from the initial state a
If we carefully see, the state e & g are same. So, we can replace g with e and remove g
from the table.

Now, the state d & f are same. So, we can replace f with d and remove f from the table.
No further redundant
state.

Now solve for reduced

state table
State Assignment
• How are we assigning code to the state
The simplest way to code five states is to use the first five integers in binary counting order, as
shown in the first assignment

Another similar assignment is the Gray code shown in assignment 2. Here, only one bit in the code group changes when
going from one number to the next. This code makes it easier for the Boolean functions to be placed in the map for
simplification.

In the one-hot assignment, we use as many bits as there are states in the circuit and hence the no. of flip flop
increases , which is not an issue for register-rich field-programmable gate arrays (FPGA).
One-hot encoding usually leads to simpler decoding logic for the next state and output.

One-hot machines can be faster than machines with sequential binary encoding, and the silicon area required by the
extra flip-flops can be offset by the area saved by using simpler decoding logic. This trade-off is not guaranteed, so it
must be evaluated for a given design
 Procedure for designing
synchronous sequential circuits
1. From the word description and specifications of the desired
operation, derive a state diagram for the circuit.
2. Reduce the number of states if necessary.
3. Assign binary values to the states.
4. Obtain the binary-coded state table.
5. Choose the type of flip-flops to be used.
6. Derive the simplified flip-flop input equations and output equations.
7. Draw the logic diagram