Module-03

Q- How can we convert one flip-flop to another flip flop?

Ans.-
Conversion of flip-flops causes one type of flip-flop to behave like another type of flip-flop. In
order to make one flip-flop mimic the behavior of another certain additional circuitry and/or
connections become necessary.

Conversion of JK Flip-Flop to SR Flip-Flop

Step 1: Write the Truth Table of the Desired Flip-Flop
Here SR flip-flop is to be designed using JK flip-flop. Thus one needs to write the truth table for
SR flip-flop.

Step 2: Obtain the Excitation Table for the given Flip-Flop from its Truth Table
Excitation tables provide the details regarding the inputs which must be provided to the flip-
flop to obtain a definite next state (Qn+1) from the known current state (Qn).

From the truth table of JK flip-flop one can see that Qn+1 will become 0 from Qn = 0 for both (i) J =
K = 0 and (ii) J = 0 and K =1 (blue entries in first and third rows of the truth table).
This means that to obtain the next state, Qn+1 as 0 from the current state Qn = 0, J must be made
zero while K can be either 0 or 1.

This is indicated by the first row of the excitation table (blue entries in the first row of excitation
table) where the value of K is expressed as ‘X’ indicating don’t care condition. Similarly to
obtain the next state as 1 from the current state 0, one has to have J equal to 1 while K can be
either 0 or 1 (indicated by green entries of the truth table).

This leads to the second row of excitation table (green entries) to be filled with values Qn = 0,
Qn+1 = 1, J = 1 and K = X. On the same grounds, the entire excitation table needs to be filled
(entries in pink and dark red colors).
Step 3: Append the Excitation Table of the given Flip-Flop to the Truth Table of the Desired
Flip-Flop Appropriately to obtain Conversion Table
Here the conversion table is obtained by filling-up the values of the J and K inputs for the given
Qn and Qn+1, by referring to the excitation table.

Step 4: Simplify the Expressions for the Inputs of the given Flip-Flop
In this case, one needs to arrive at the logical expressions for the inputs J and K in terms of S, R,
and Qn using suitable simplification techniques like K-map.

Step 5: Design the Necessary Circuit and make the Connections accordingly
Here neither additional circuit nor new connections are necessary.

On the same grounds, one can convert the given flip-flop to any other type of flip-flop as shown
below.
Conversion of JK Flip Flop to D Flip Flop
Conversion of JK Flip Flop to T Flip Flop
The conversion from a JK flip flop to a T flip flop is shown below.

Conversion of D Flip Flop to T Flip Flop

Conversion of T Flip Flop to JK Flip Flop
Conversion of T Flip Flop to SR Flip Flop
Conversion of T Flip Flop to D Flip Flop
Q.- Explain some special type shift registers which act as counters.

Ans.-

Shift Register Counters are the shift registers in which the outputs are connected back to the
inputs in order to produce particular sequences. There are basically two types:
 Ring Counter
 Johnson Counter
Ring Counter
A ring counter is basically a shift register counter in which the output of the first flip-flop is
connected to the next flip-flop and so on and the output of the last flip-flop is again fed back to
the input of the first flip-flop, thus the name ring counter. The data pattern within the shift register
will circulate as long as clock pulses are applied. The logic circuit given below shows a Ring
Counter.
 Ring Counter Truth Table

The circuit consists of four D flip-flops which are connected. Since the circuit consists of four
flip-flops the data pattern will repeat after every four clock pulses as shown in the truth table. A
Ring counter is generally used because it is self-decoding. No extra decoding circuit is needed
to determine what state the counter is in.

Ring Counter

Johnson Counter
A Johnson counter is basically a shift register counter in which the output of the first flip flop is
connected to the next flip flop and so on and the inverted output of the last flip flop is again fed
back to the input of the first flip flop. They are also known as twisted ring counters. The logic
circuit given below shows a Johnson Counter. The circuit consists of four D flip-flops which are
connected.

Design for Mod-N counter :

The steps for the design are –
Step 1 : Decision for number of flip-flops –
Example : If we are designing mod N counter and n number of flip-flops are required then n
can be found out by this equation.
N <= 2n
Here we are designing Mod-10 counter Therefore, N= 10 and number of Flip flops(n) required
is
For n =3, 10<=8, which is false.
For n= 4,10<=16, which is true.
Therefore number of FF required is 4 for Mod-10 counter.
Step 2 : Write excitation table of Flip flops –
Here T FF is used

Excitation table of T FF.

Step 3 : Draw state diagram and circuit excitation table –

Counting Sequence of Decade counter

A decade counter is called as mod -10 or divide by 10 counter. It counts from 0 to 9 and again
reset to 0. It counts in natural binary sequence. Here 4 T Flip flops are used. It resets after
Q3 Q2 Q1 Q0 = 1001.
Circuit excitation table –
Here Q3 Q2 Q1 Q0 are present states of four flip-flops and Q*3 Q*2 Q*1 Q*0 are next counting
state of 4 Flip flops. If there is a transition in current state i.e if Q3 value changes from 0 to 1
or 1 to 0 then there’s corresponding T(toggle) bit is written as 1 otherwise 0.

Circuit excitation table

Step 4 : Create Karnaugh map for each FF input in terms of flip-flop outputs as the
input variable –
Simplify the K map –

K map for finding minimal expressions.

Step 5 : Create circuit diagram –

Here negative edge triggered clock is used for toggling purpose.
 The clock is provided to every Flip flop at same instant of time.
 The toggle(T) input is provided to every Flip flop according to the simplified equation of K
map.
 Circuit diagram

Timing diagram : Here toggling is used.

Characteristic table of T FF.

The state of a FF will change only when toggle input(T) of a FF is 1.

 Timing diagram of synchronous Decade counter

Explanation :
 Initially Q3 Q2 Q1 Q0 are 0 0 0 0.
 The sequence of counter can be verified from the timing diagram. At every falling edge of
the clock output Q0 toggles because T 0 is connected to logic 1.
 T1 becomes 1 only when expression T1 = Q’ 3Q0 becomes 1 also if clock falling edge
occurs(because there is negative edge triggering) then the output state of T 1 i.e Q1 will
change.
 T2 becomes 1 only when expression T2 = Q 1Q0 becomes 1 also if clock falling edge occurs
then the output state Q2 will change.
 T3 becomes 1 only when expression T1 = Q 3Q0 + Q2Q1Q0 resultant becomes 1 also if
clock falling edge occurs(because there is negative edge triggering) then the state of Q3
will change.
 We get Output as Q3(MSB) Q2 Q1 Q0(LSB).
 After 10th falling edge the output state of all the FFs again becomes 0 0 0 0.

Q.- Explain the working of Master-Slave JK Flip flop.

Ans.-

Master Slave JK flip flop – The Master-Slave Flip-Flop is basically a combination of two JK
flip-flops connected together in a series configuration. Out of these, one acts as
the “master” and the other as a “slave”. The output from the master flip flop is connected to
the two inputs of the slave flip flop whose output is fed back to inputs of the master flip flop. In
addition to these two flip-flops, the circuit also includes an inverter. The inverter is connected
to clock pulse in such a way that the inverted clock pulse is given to the slave flip-flop. In other
words if CP=0 for a master flip-flop, then CP=1 for a slave flip-flop and if CP=1 for master flip
flop then it becomes 0 for slave flip flop.
Working of a master slave flip flop –
1. When the clock pulse goes to 1, the slave is isolated; J and K inputs may affect the state
of the system. The slave flip-flop is isolated until the CP goes to 0. When the CP goes
back to 0, information is passed from the master flip-flop to the slave and output is
obtained.
2. Firstly the master flip flop is positive level triggered and the slave flip flop is negative level
triggered, so the master responds before the slave.
3. If J=0 and K=1, the high Q’ output of the master goes to the K input of the slave and the
clock forces the slave to reset, thus the slave copies the master.
4. If J=1 and K=0, the high Q output of the master goes to the J input of the slave and the
Negative transition of the clock sets the slave, copying the master.
5. If J=1 and K=1, it toggles on the positive transition of the clock and thus the slave toggles
on the negative transition of the clock.
6. If J=0 and K=0, the flip flop is disabled and Q remains unchanged.
Timing Diagram of a Master Slave flip flop –

1. When the Clock pulse is high the output of master is high and remains high till the clock is
low because the state is stored.
2. Now the output of master becomes low when the clock pulse becomes high again and
remains low until the clock becomes high again.
3. Thus toggling takes place for a clock cycle.
4. When the clock pulse is high, the master is operational but not the slave thus the output of
the slave remains low till the clock remains high.
5. When the clock is low, the slave becomes operational and remains high until the clock
again becomes low.
6. Toggling takes place during the whole process since the output is changing once in a
cycle.

Q.- Explain the working of BCD or Decade Counter Circuit.

Ans.- A binary coded decimal (BCD) is a serial digital counter that counts ten digits .And it
resets for every new clock input. As it can go through 10 unique combinations of output, it is
also called as “Decade counter”. A BCD counter can count 0000, 0001, 0010, 1000, 1001,
1010, 1011, 1110, 1111, 0000, and 0001 and so on.

A 4 bit binary counter will act as decade counter by skipping any six outputs out of the 16 (24)
outputs. There are some available ICs for decade counters which we can readily use in our
circuit, like 74LS90. It is an asynchronous decade counter.

The above figure shows a decade counter constructed with JK flip flop. The J output and K
outputs are connected to logic 1. The clock input of every flip flop is connected to the output of
next flip flop, except the last one.

The output of the NAND gate is connected in parallel to the clear input ‘CLR’ to all the flip flops.
This ripple counter can count up to 16 i.e. 24.

Decade Counter Operation

When the Decade counter is at REST, the count is equal to 0000. This is first stage of the
counter cycle. When we connect a clock signal input to the counter circuit, then the circuit will
count the binary sequence. The first clock pulse can make the circuit to count up to 9 (1001).
The next clock pulse advances to count 10 (1010).

Then the ports X1 and X3 will be high. As we know that for high inputs, the NAND gate output
will be low. The NAND gate output is connected to clear input, so it resets all the flip flop stages
in decade counter. This means the pulse after count 9 will again start the count from count 0.
Truth Table of Decade Counter

The above table describes the counting operation of Decade counter. It represents the count of
circuit for decimal count of input pulses. The NAND gate output is zero when the count reaches
10 (1010).

The count is decoded by the inputs of NAND gate X1 and X3. After count 10, the logic gate
NAND will trigger its output from 1 to 0, and it resets all flip flops.

State Diagram of Decade Counter

The state diagram of Decade counter is given below.

If we observe the decade counter circuit diagram, there are four stages in it, in which each stage
has single flip flop in it. So it is capable of counting 16 bits or 16 potential states, in which only
10 are used. The count starts from 0000 (zero) to 1001 (9) and then the NAND gate will reset
the circuit.

Multiple counters are connected in series, to count up to any desired number. The number that
a counter circuit can count is called “Mod” or “Modulus”. If a counter resets itself after counting n
bits is called “Mod- n counter” “Modulo- n counter”, where n is an integer.
The Mod n counter can calculate from 0 to 2n-1. There are several types of counters available,
like Mod 4 counter, Mod 8 counter, Mod 16 counter and Mod 5 counters etc.

Q.- Explain the basics of Asynchronous counter.

Ans.-

1 bit asynchronous/ripple counter

When -ve edge clock pulse is applied and input is given to FF logic 1 then the output state of
FF will toggle for every falling edge. The output frequency will be f/2 (If f is clock frequency). It
is known as binary or mod -2 counter or bit ripple counter.
It has 2 unique output states (0 and 1).

2 bit asynchronous Up counter.

When two FFs are connected in series and output of one FF is act as clock for 2nd FF. So the
state of 2nd FF will change only when output and 1st FF is logic 1 and falling edge occur. The
output frequency of Q1 is f/4(if f is clock frequency).
It can generate 4 different unique states. This is known as divide by 4 circuits or mod 4 ripple
counter.
Here output is taken as Q 1(MSB) Q0(LSB).
By this, we can conclude that –
If there are n FFs then the output frequency will be divide by 2 n. Also generate 2n unique
states.
So the frequency division basically forms counting state.
Here we are seeing that the output of the 1st FF act as clock for 2nd FF. Suppose the FF
takes 30ns for generating output(i.e. propagation delay because of gates). Therefore, the
output of second FF will be obtained after 60 ns. So the propagation delay is ripples through
the FFs and becomes more when the number of FFs increases.
Therefore, asynchronous counter are too slow for generating big counting.
 As we know, when the output state (i.e. Q) of previous FF is feed as clock to next FF then
the counter will perform up counting as you seen above(i.e. 0 1 2 3).
After 4th -ve edge clock pulse the sequence will repeat.
 When the complemented output state (i.e. Q’) of previous FF is feed as clock to next FF
then the counter will perform down counting as you seen below(i.e. 3 2 1 0).
After 4th -ve edge clock pulse the sequence will repeat.

2 bit asynchronous down counter

Now we are designing Up/Down counter.

Up/Down counter is the combination of both the counters in which we can perform up or down
counting by changing the Mode control input.
Q.- Design a 3 bit Asynchronous up/down counter
Ans.
It is used more than separate up or down counter.
1. In this a mode control input (say M) is used for selecting up and down mode.
2. A combinational circuit is required between each pair of flip-flop to decide whether to do
up or do down counting.
For n = 3, i.e for 3 bit counter –
Maximum count = 2n -1 and number of states are 2n.
Steps involve in design are :
Step 1 : Decision for Mode control input –

Decision for mode control input

When M = 0, then Y= Q, therefore it will perform Up counting (As discussed above).

When M = 1, then Y= Q’ therefore it will perform Down counting (As discussed above).
Combinational circuit is required for deciding mode control(i.e whether counter will perform Up
counting or Down counting).
So the all possible combinations are –
K-map for finding output Y that will be given as clock to next FF.

K map for finding Y

Step 2 : Insertion of Combinational logic between every pair of FFs –

 Up/Down Counter

Timing diagram :
Initially Q3 = 0, Q2 = 0, Q1 = 0.

Timing diagram for 3 bit asynchronous up/down counter

Case 1 – When M=0, then M’ =1.

Put this in Y= M’Q + MQ’= Q So Q is acting as clock for next FFs.
Therefore, the counter will act as Up counter.
Explanation of Up counter –
 The 1st FF is connected to logic 1. Therefore, it will toggle for every falling edge.
 The 2nd FF input is connected to Q 1.Therefore it changes its state when Q 1= 1 and there
is falling edge of clock.
 Similarly, 3rd FF is connected to Q 2. Therefore, it changes its state when Q 2= 1 and there
is falling edge of clock.
 By this we can generate counting states of Up counter.
 After every 8th falling edge the counter is again reaching to state 0 0 0.
Therefore, it is also known as divide by 8 circuit or mod 8 counter.
Case 2 – When M=1, then M’ =0.
Put this in Y= M’Q + MQ’= Q’. So Q’ is acting as clock for next FFs.
Therefore, the counter will act as Down counter.
Explanation of Down counter –
 The 1st FF is connected to logic 1. Therefore, it will toggle for every falling edge.
 The 2nd FF input is connected to Q’1.Therefore it changes its state when Q’ 1= 1 and there
is falling edge of clock.
 Similarly, 3rd FF is connected to Q’ 2. Therefore, it changes its state when Q’ 2= 1 and there
is falling edge of clock.
 By this we can generate counting states of down counter.
 After every 8th falling edge the counter is again reaching to state 0 0 0.
Therefore, it is also known as divide by 8 circuit or mod 8 counter.