Lecture 10: JK Master Slave flip flop

The JK master- slave flip flop was developed to

eliminate the problem of toggling more than
once which is associated with the JK flip flop.
This flip flop is made up of two flip flop in one,
the master which is used to’ manufacture’ the
contents and the slave which is used to store
the ‘manufactured’ contents.
The JK master-slave flip flop logic
circuit is shown below:
JK Master Slave flip flop operation
The JK Master-Slave flip flop operates as follows:
• On a 1 to 0 clock transition, the master flip flop is
connected to the JK input lines and the slave is
inhibited from operating because of the NOT gate
that complements the clock signal to the slave flip
flop.
• On a 0 to 1 clock transition, the master is isolated
from the input lines and the slave is activated and
the contents of the master are transferred to the
slave flip flop. The purpose of the slave is to hold the
output of the master whilst it is being set for the next
input as determined by the J and K inputs.
• When the clock pulse set to 1, the output of
the master flip flop will be one until the clock
input remains 0. When the clock pulse
becomes high again, then the master's output
is 0, which will be set to 1 when the clock
becomes one again. ... The slave flip flop is
operational when the clock pulse is 0.
• Although the slave flip-flop is also level
triggered, it will not change after the clock
input has gone low, because its input is taken
from the output of the master flip-flop, which
will not be accepting changes due to the clock
input being low.
JK Master Slave truth table
Full design of a sequential circuit
• The design procedure of a sequential circuit
consists of the following steps:
• Translating the circuit specifications into a
state diagram;
• Converting the state diagram into a state table
(excitation table)
• From the excitation table obtain the logic
equations of the circuit diagram.
 Cont…
Example: Design a clocked sequential circuit
that goes through a sequence of repeated
binary States 00, 01, 10, 11, 00, 01, etc when
an external input x is equal to 1. The state of
the sequential circuit remains unchanged
when the external input x = 0.Produce its state
table showing how it functions.
 Cont…
The JK master-slave eliminates the problem of
toggling more than one but it is expensive.
The edge triggered flip flops have been
developed to replace it in some instances,
especially the edge triggered JK flip flop which
has become universal and most widely used
flip flop. The JK flip flop, because of its
toggling nature is used to implement binary
counters.
Cont…
The T (Toggle) Flip Flop
The T (toggle) flip flop changes its output on
each clock edge, giving an output which is half
frequency of the signal to the T input. For
example:
 Cont…..
It is useful for the construction of binary
counters, frequency dividers, and general
binary addition devices. The T flip flop can be
implemented from a special JK flip flop. The
special JK flip flop is the one where the inputs
J and K are tied together. This type of flip flop
operates by toggling the previous state every
time a clock pulse is applied at the input T. T =
J & K.
The T flip flop (A special JK flip flop)
The D (data) Flip flop
The D flip flop is the best way to avoid the
ambiguous case. This flip flop has one data
input line and the D input to the upper NAND
gate is the complement to the D input of the
lower NAND gate.
In this way the case of both inputs being logical
ones (1s) does not arise. (See logic diagram
below in figure 45.
D flip flop implemented on AND and
NOR gates
D flip flop implemented on NAND
gates only
The D flip flop can also be implemented on AND
and NOR gates. The D flip flop operates as
follows:
• When the clock C = 1 and D = 1, Q = 0 and = 1
• When C = 1 and D = 1, Q =1 and = 0
D flip flop operation
Edge triggered flip flops
The edge triggered flip flops were developed to
eliminate the JK flip flop problem of toggling
more than once.
The JK master-slave flip flop eliminates this
problem but it is expensive.
The edge triggered flip flops operate either on
the rising edge of a clock pulse (positive edge
transition) or on the falling edge of a clock
pulse (negative edge transition). For example:
Positive edge transition
When the positive edge transition threshold is
reached, the inputs are locked out and the flip
flop becomes irresponsive to any further
inputs and will only accept inputs on the next
positive edge transition
Positive edge transition symbol
Negative edge clock transition

The negative edge clock pulse transition is also

known as:
• the falling edge transition,
• leading edge or the 1 to 0 transition.
The negative edge and positive transition
principle of operation is basically the same.
Negative edge transition
Negative edge transition flip flop
symbol
Flip flop state diagrams

Flip flop state diagrams are used in the design of state

diagrams.
The state diagrams show the transitions from one state to the
next as dictated by the flip flop inputs and the present
states.
In a state diagram, a state is shown by a circle.
The binary number inside the circle defines the present state.
Transition from one state to the next is shown by a directed
line and
the present inputs that cause the transitions are labelled on
the directed line.
Where the present state is the same as the next
state, a directed line is drawn connecting the
circle with itself and labelled the present
inputs, for example in the SR state table, S = R
= 0, the next state is the same as the present
state. When S = 1 and R = 0, transition is from
state Q = 0 to state Q = 1. When S = 0 and R
=1, transition is from state Q = 1 to state Q = 0.
(see figure 50 below).
SR flip flop state diagram
The JK flip flop state diagram
The JK flip flop state diagram is similar to the SR
flip flop state diagram but the only difference
is that the JK state diagram include the
toggling combination, C = 1, J = K = 1. This
combination is a prohibited combination in
the SR flip flop.
The JK flip flop state diagram
SR and JK flip flops Excitation Tables

• Excitation tables are derived from the state tables

of flip flops. The state tables specify the next
state when the inputs and present states are
known.
• During designing, the designer usually knows the
required transition from present state to next
state but wishes to find out the flip flop input
conditions that will cause the required transition.
• So an excitation table lists the required input
combinations for a given change of state.
The excitation tables can be produced from flip-
flop state tables or from state diagrams.
The SR excitation table works as follows:
Transition from state 0 (Q = 0) to next state Q = 0,
the S input must be zero (0), R input is a don’t
care, meaning whether a 0 or a one is used, the
output remains the same.
The designer will however choose to use a 0 or a 1
or whatever is at his/her disposal during the
design stage.
Transitions from state Q = 0 to state Q = 1 and from
state Q =1 to state Q = 0 are straight forward and
easy to understand.
Transition from State Q = 1 to next state Q = 1, R
must be equal to zero (0) and S is a don’t care,
meaning a zero or a one can be used. If a zero
is chosen when in state one, it means S = 0, R
= 0, thus a no change. A no change means if
you are in state 1 and S = 0, R = 0, you will
remain in state 1. The same applies if you are
in state 0.
The JK flip flop Excitation Table
The JK flip flop is slightly complicated by the
toggling input combination.
So it has don’t care conditions in each line of the JK
inputs. The first and the last are just like in the SR
excitation table.
This is however not surprising since the JK flip flop
is a modification of the SR flip flop.
The second and third input combinations make use
of the toggling input combination of the JK flip
flop. The best way to produce the SR and JK
excitation tables is to use their state diagrams.
SEQUENTIAL CIRCUIT EQUATIONS
Example of a sequential circuit diagram
• The diagram below shows a typical example of a
sequential circuit. The AND gates, OR gates and
the INVERTER (NOT gate) form the combinational
logic part of the circuit. The two D flip-flops form
the storage part of the sequential circuit.
• The interconnections among the gates in the
combinational circuit can be specified by a set of
Boolean expressions,
Sequential circuit state table
The Sequential State Diagram

Information in a state table can be represented

graphically in a state diagram. In a state diagram a
circle represents a state and the transition
between states is indicated by directed lines
connecting the circles. The binary number inside
the circle represents the state of the flip flops.
The directed lines are labeled with two binary
numbers separated by a slash. The input value
during the present state is labeled first and the
binary number after the slash gives the output. A
directed line connecting a circle with itself means
that no change of state occurs.
Sequential circuit state diagram
Full design of a sequential circuit
Full design of a sequential circuit
• The design procedure of a sequential circuit
consists of the following steps:
• Translating the circuit specifications into a state
diagram;
• Converting the state diagram into a state table
(excitation table)
• From the excitation table obtain the logic
equations of the circuit diagram.
Example: Design a clocked sequential circuit
that goes through a sequence of repeated
binary States 00, 01, 10, 11, 00, 01, etc when
an external input x is equal to 1. The state of
the sequential circuit remains unchanged
when the external input x = 0.Produce its state
table showing how it functions.
Workings: Step 1: From the problem
specifications produce state table
JA ,KA and JB,KB inputs of flip flops A and B
The state table below shows the
operation of the 2-bit UP counter