Chapter 3 Sequential Circuits

Digital Electronics
Table of Contents
3. SEQUENTIAL CIRCUITS ................................................................................................... 2
3.1. Classification of sequential circuits ................................................................................ 2
3.1.1. Synchronous Sequential Circuit ............................................................................... 2
3.1.2. Asynchronous Sequential Circuit ............................................................................ 2
3.2. FLIP-FLOPS ................................................................................................................... 2
3.2.1. JK flip-flop:.............................................................................................................. 2
3.2.2. D flip-flop: ............................................................................................................... 4
3.2.3. T flip-flop: ................................................................................................................ 4
3.3. Clock types: .................................................................................................................... 5
3.3.1. Level trigger ............................................................................................................. 5
3.3.2. Edge trigger .............................................................................................................. 5
3.4. COUNTERS: .................................................................................................................. 5
3.4.1. Counters types:......................................................................................................... 6
3.4.2. UP/DOWN Counter: ................................................................................................ 6
3.5. ASYNCHRONOUS COUNTER (RIPPLE COUNTER): .............................................. 7
3.5.1. MOD-2 Counter (Binary counter): .......................................................................... 7
3.5.2. MOD-8 Counter: ...................................................................................................... 7
SYNCHRONOUS (PARALLEL) COUNTERS: .............................................................. 8
3.6. Preset and Clear Inputs ................................................................................................... 8
Example: ............................................................................................................................ 8

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 3. SEQUENTIAL CIRCUITS
A Sequential circuits consists of combinational logic which receives digital signals
from external inputs (A) and from outputs of memory elements and generate signals for
external outputs(Z) and for inputs to memory elements

A Sequential circuit is specified by a “time sequence of inputs, outputs and internal states”.

3.1. Classification of sequential circuits

3.1.1. Synchronous Sequential Circuit
 The change in input signals can affect memory element upon activation of clock
signals.
 The maximum operation speed of clock depends on time delays involved.
 In this circuits, memory elements are “clocked flip-flops”.
 It is easier to design.
 It is generally “Edge triggered”
3.1.2. Asynchronous Sequential Circuit
 The change in input signals can affect memory element at any instant of time.
 In this circuits, memory elements are either “unclocked flip-flops or time delay
elements”.
 More difficult to design.
 It is generally “Level triggered”

3.2. FLIP-FLOPS
 The memory elements used in ”clocked sequential circuits ” are called “flip-flops”
 It is basic memory element.
 These are binary cells and it can store in one Bit of information.
 It has two outputs (Q and Q̅ ), which are complemented to each other.
 It has two stable states which are known as “Bistable Multivibrator” or “Latch”.
 A flip-flop circuit can be constructed from NAND gates or NOR gates.
 Flip-flops can be divided into common types: the SR ("set-reset"), D ("data" or
"delay"), T ("toggle"), and JK.
3.2.1. JK flip-flop:
A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the
SR type is defined in the JK type.

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 ̅ and Q respectively to obtain S
The data inputs are J and K which are ANDed with Q
and R inputs i.e.,
S=J𝑄̅ and R=KQ
̅ are compliment with each other.
Here Q and Q

Fig: Logic diagram

This JK-flip-flop is called an universal flip-flop because the FFs like D-flip-flop, SR-flip-flop
and T-flip-flop can be derived from it.

Fig: Graphical and Timing Diagram

Clock J K 𝐐(t) ̅ (t)
𝑸 Q(t+1)
0 X X Q 𝑄̅ Q Memory
1 0 0 Q 𝑄̅ Q Hold
1 0 1 X X 0 Reset
1 1 0 X X 1 Set
1 1 1 Q 𝑄̅ 𝑄̅ Toggle

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 Truth table for JK flip flop
Here X = Don’t care (0 or 1) and Q(t+1) is next state.
3.2.2. D flip-flop:
The D-flip-flop is a modification of the clocked JK-FF. It is a flip-flop with a delay
equal to exactly one cycle of CLK. It is also called “Transparent Latch”.

Fig: (a). Logic diagram and (b). Graphical diagram

Clock D 𝑸(t) ̅ (t)

𝑸 Q(t+1)

0 X Q 𝑄̅ Q Memory
1 0 X X 0 Reset
1 1 X X 1 Set

Truth table for D flipflop

3.2.3. T flip-flop:
The T-flip-flop is a single input version of the JK-flip-flop. T-flip-flop can be obtained
from a JK-flip-flop if J and K tied together as shown in figure. The designation ‘T’ comes from
the flip-flop to “Toggle” or “Change state”.

(a) (b)

Fig: (a). Logic diagram and (b). Graphical diagram

Clock T 𝐐(t) ̅ (t)

𝑸 Q(t+1)
0 X Q 𝑄̅ Q Memory
1 0 Q 𝑄̅ Q Hold
1 1 Q 𝑄̅ 𝑄̅ Toggle

Truth table for T flip flop

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3.3. Clock types:
3.3.1. Level trigger
 High level trigger
 Low level trigger

3.3.2. Edge trigger

 Positive edge trigger
 Negative edge trigger

3.4. COUNTERS:
 The counters are composed with flip-flops and combinational elements.
 It is a sequential circuit forming by the cascading of flip-flops.
 A counter circuit with n-flip-flops has maximum 2n possible states.
 Also, if N=total number of states and n=number of flip-flops then,
N ≤ 2n n ≥ log 2 𝑁 n ≥ 3.32log10 𝑁
 n
If N = 2 , then we get BINARY COUNTER.
 If N = 2n, then we get NON- BINARY COUNTER.
MOD Number:
 The “MOD-number” indicates the number of states in counting sequence.
 For n-flip-flops, counter will have 2n different states and then this counter is said to be
“MOD-2n Counter”.

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  MOD number indicates the frequency division obtained from the last flip-flop.
 It would be capable of counting up-to (2n - 1) before returning to zero state.
3.4.1. Counters types:
Based upon the applying CLK pulse, Counters are of two types:
 Synchronous counter
 All flip-flops are triggered with same CLK.
 Operation is faster.
 Any required sequence can be designed.
 No decoding error occurs.
 Its design is complex.
 Ex: Ring counter,…
 Asynchronous counter
 Different flip-flops are run with different CLK.
 Operation is slower.
 Only fixed sequence can be designed (up and down).
 Decoding error occurs due to “tpd”.
 Its design is relatively easy.
 Ex: Ripple counter,...
3.4.2. UP/DOWN Counter:
 If a counter counts in such a way that the decimal equivalent of output increases with
successive CLK pulses is called as “UP Counter”.
 If the decimal equivalent of the output decreases with successive CLK pulses then it is
called “DOWN Counter”.
 An “UP/DOWN Counter” can count in any direction depending upon the control input.
3.4.3. Application of Counters:
 To count the number of CLK pulses.
 To count the number of items in industry.
 As a “Frequency divider”.
 In time measurement.
 For distance measurement in Radar system.
 In Analog to Digital converter (ADC).
 In measurement of PRI (Pulse Repetition interference).

 In MOD-N Counter, if applied input frequency is “f”, then output frequency is “f/N”.
 If two counters are cascaded with MOD-M followed by MOD-N, then number of overall
states of combined counter is (M × N) and counter is called “MOD-MN” counter.

I/p Freq of f MOD-N MOD-MN counter

MOD-M
O/p O/p Freq.= f/MN

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3.5. ASYNCHRONOUS COUNTER (RIPPLE COUNTER):
3.5.1. MOD-2 Counter (Binary counter):
It can be seen from the frequency waveforms below, that by “feeding back” the output
from Q to the input terminal D, the output pulses at Q have a frequency that are exactly one
half ( f ÷ 2 ) that of the input clock frequency. In other words the circuit produces Frequency
Division as it now divides the input frequency by a factor of two.

Fig: MOD-2 counter and Timing diagram

3.5.2. MOD-8 Counter:
 It is a 3-bit binary ripple counter which consists of a series connection of
complementing flip-flops, with the output of each flip-flop connected to the clock pulse
input of the next higher order flip-flop.
 The flip-flop holding the LSB receives the incoming clock pulses.

Timing diagram for MOD-8 counter

CLK Q2 Q1 Q0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0

Truth table for MOD-8 Counter

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  Initially all flip-flops are set to zero.
 Maximum possible states = 8 (from 0 to 7)
 Fixed sequence follows, so it is an “UP Counter”.
 If input frequency is ‘f’ then here output frequency = f/8.
 In ripple counter with n-flip-flops there are 2n possible states.
 With n-flip-flops the maximum count that can be counted by this counter is 2n – 1.
 It is also called ( 2n : 1 ) scalar counter.
Disadvantages of Ripple Counter:
 Decoding error is present.
 This error occurs due to propagation delay of flip-flops i.e. tpd(ff).
 For proper operation of the ripple counter. It should be noted that,
TCLK ≥ ntpd(ff)
∴ fCLK ≤ 1/ ntpd(ff)
Maximum CLK frequency = 1/ ntpd(ff)
 To overcome the decoding error in ripple counter, we may use “Strobe input”.
Identifying whether the counter is UP/Down Counter:
Triggering with CLK connection in Access as
(-ve) edge Q UP counter
(-ve) edge 𝑄̅ Down counter
(+ve) edge Q Down counter
(+ve) edge 𝑄̅ UP counter

SYNCHRONOUS (PARALLEL) COUNTERS:

 The problems encountered with ripple counters are caused by the accumulated flip-flops
propagation delay.
 In other words, the flip-flops do not change states simultaneously in synchronism with the
input pulses.
 These above limitations can be overcome with the use of Synchronous or parallel counters
in which all the flip-flops are triggered simultaneously by the CLK input pulses.

3.6. Preset and Clear Inputs

Commercially available flip-flops include separate inputs for setting the flip-flop to 1
or clearing the flip-flop to 0. These inputs are called “preset” and “clear” inputs respectively.
These inputs are useful for initializing the flip-flops without the clock pulse. When the power
is turned ON, the output of the flip-flop is in undefined state. The preset and clear inputs can
directly set or clear the flip-flop as desired prior to its clocked operation.

Example:
MOD-5 Ripple Counter
In ripple counter in order to reduce number of states feedback is applied through clear
(clr) or preset (pr).clear signal is used to reset counter and preset signal is used to set counter.

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 Clock Q2 Q1 Q0 clr
0 0 0 0 0
1 0 0 1 0
2 0 1 0 0
3 0 1 1 0
4 1 0 0 0
5 0 0 0 1

101 ̅ 𝟏 𝑸𝟎
𝑸𝟐 𝑸 after tpd of AND gate
0 1 2 3 4 0 1 2 3 4 0 1………
Note:
𝑐𝑙𝑟 Q AND gate ̅̅̅̅
𝑐𝑙𝑟 Q NAND gate
𝑐𝑙𝑟 𝑄̅ OR gate ̅̅̅̅
𝑐𝑙𝑟 𝑄̅ NOR gate