Sequential Logic Circuits and memory

elements.
Types of Sequential logic
design
1. Synchronous circuit design.
• Depends on discrete time instants of the signal.

2. Asynchronous circuit design.

• Depends on input signal at a given time and the order in
which the input changes.

2
Synchronous Circuits
• Synchronous sequential circuit uses clock signal.
• The clock is commonly denoted by clk.
e.g.: Full adder circuit with a storage element.

Train of clock pulses

3
Asynchronous sequential circuit design

• The output depends on

• input signal at a given time,
• the order in which input changes.

• Asynchronous sequential circuits uses time-delay devices, as storage

elements.

4
Storage elements
There are two types of storage elements, which are
• Latches
• Flip-flops

Latches Flip-flops.
Storage elements that Storage elements that operates
operates with signal levels. with signal transitions.
Level sensitive devices. Edge sensitive devices.
Can be constructed from logic Can be constructed from latches.
gates.
Used in asynchronous Used in synchronous sequential
sequential circuit design circuit design
7
Flip-Flops.
• Flip-flop uses clock signal transition to trigger its
state.

• Signal transition can be

• positive transition(0 -> 1)
• negative transition(1 -> 0).

Positive Transition Negative Transition

Types of Flip-Flop
• D flip-flop

• SR flipflop

• JK flip-flop

• T flip-flop
Applications

• Counters
• Frequency Dividers
• Shift Registers
• Storage Registers
TRIGGERING OF FLIP-FLOPS

• The state of a Flip-Flop is switched by a

momentary change in the input signal. This
momentary change is called a trigger and the
transition it causes is said to trigger the Flip-Flop

• Latches are controlled by enable signal, and they

are level triggered, either positive level triggered
or negative level triggered.
TRIGGERING OF FLIP-FLOPS
TRIGGERING OF FLIP-FLOPS
• If the flip-flop is triggered when the clock pulse goes from low
to high (positive edge), then it is called positive
Edge Triggering Method
• If the flip-flop is triggered to update its output when the clock
pulse goes from high to low (negative edge), then it is
called negative edge- triggering method.
 D Flip-Flop with Negative
Transition

A
• When Clk = 0,
• Master latch is disabled.
• Slave latch is enabled.
• o/p of master latch is transferred to o/p of slave latch
• When Clk changes from 0 -> 1,
• External input (D) is transferred to output of master latch.
• Slave latch is disabled.
• When Clk changes from 1 -> 0,
• Master latch is disabled.
• Slave latch is enabled.
• O/p of master latch is transferred to o/p of slave latch.
• Output of flip-flop can be triggered by negative edge transition of the
clock.
 D Flip-Flop with Positive
Transition
Additional inverter can be connected between Clk and the
junction referred by ‘A’

Negative edge
Positive edge triggered 14
triggered
 Race Around Condition in JK Flip-Flop
• Race Around Condition In JK Flip-flop – For J-K flip-
flop, if J=K=1, and if clk=1 for a long period of time,
then Q output will toggle as long as CLK is high,
which makes the output of the flip-flop unstable or
uncertain. This problem is called race around
condition in J-K flip-flop.
Master-Slave JK Flip-Flop
Working of Master Slave JK Flip-Flop
Master–slave D flip-flop
T Flip-Flop
• T Flip-flop has only one input (T).

• Can be used to perform Toggle operation

• Following characteristic expression defines the

behavior of a T FF.
𝑄 𝑡 + 1 = 𝑇𝑄 ! + 𝑇 ! 𝑄
T Flip-flop (cont’d)
T Flip-flop (cont’d)
• JK FF can be used to construct a T FF.
• Following diagram shows the construction of a T
FF which uses JK FF.
T Flip-flop (cont’d)
• D FF also can be used to construct a T FF.
• Following diagram shows the construction of a T
FF which uses D FF.

T: Q(t+1) = T xor Q(t)

D: Q(t+1) = D
JK Flip-Flop
• JK Flip-flop has two inputs (J, and K).
• Can be used to perform following operations
• Set
• Reset
• Toggle (complement operation)

• Following characteristic expression defines the

behavior of a JK.
𝑄(𝑡 + 1) = 𝐽𝑄′ + 𝐾′𝑄
JK Flip-flop
Logic
 JK Flip-Flop from D Flip-
Flop
• D FF can be used to construct a JK FF.

D: Q(t+1) = D

JK:
Q(t+1) = JQ’(t) + K’Q(t)
D = JQ’(t) + K’Q(t)
Summary: Characteristic Equations
Characteristic equations of D, SR, JK, and T FF are
given below.
• D FF: 𝑄(𝑡 + 1) = 𝐷
• JK FF: 𝑄 𝑡 + 1 = 𝐽𝑄 ! + 𝐾 ! 𝑄
• T FF: 𝑄 𝑡 + 1 = 𝑇 ⊕ 𝑄 = 𝑇𝑄 ! + 𝑇 ! 𝑄
Summary: Characteristic
Tables
Characteristic tables of SR, JK, D, and T FF are given
below.
D Q(t+1) J K Q(t+1)
0 0 0 0 Q *
1 1 0 1 0
1 0 1 *
1 1 Q’

T Q(t+1)
0 Q
1 Q’
 Summary: Excitation Tables
Excitation tables of SR, JK, D, and T FF are given below.
Summary: Excitation Tables
Exercise
1. A PN flip-flop has four operations: clear to 0, no
change, complement, and set to 1, when inputs P
and N are 00, 01, 10, and 11, respectively.
I. Tabulate the characteristic table.
II. Derive the characteristic equation.
III. Tabulate the excitation table.
IV. Show how the PN flip-flop can be converted to a D flip-flop
(I)
P N Q(t+1) Description

0 0 0 Reset

0 1 Q(t) No change

1 0 Q’(t) Complement

1 1 1 Set

Q(t +1)
(II) NQ
00 01 11 10
P
0 0 1 0
0
1 0 1 1
1

Q(t+1) = NQ(t) + PQ’(t)

(III) Excitation table

Q(t) Q(t+1) P N

0 0 0 X

0 1 1 X

1 0 X 0

1 1 X 1

(IV) Characteristic table of D FF

D Q(t + 1) Des

0 0 Reset

1 1 Set
D P Q

Q’
CLK
N
Asynchronous reset logic in Flip-flop.
• Asynchronous reset can be used in a FF.
• Logic circuit diagram of D flip-flop with
asynchronous reset is shown below.
Flip flop Conversion – SR flip-flop to
JK flip-flop
• Step 1: Write the truth table of the required flip-flop

J K QN QN+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Step 2: Write the excitation table of the given
flip-flop

QN QN+1 S R

0 0 0 X

0 1 1 0

1 0 0 1

1 1 X 0
Step 3: Write the conversion table
J K QN QN+1 S R
0 0 0 0 0 X
0 0 1 1 X 0
0 1 0 0 0 X
0 1 1 0 0 1
1 0 0 1 1 0
1 0 1 1 X 0
1 1 0 1 1 0
1 1 1 0 0 1
Step 4: Find the Boolean expressions for the inputs
of the given flip-flop.
• S = JQN/

• R = KQN
Step 5: Draw the circuit for
implementing JK flip-flop using SR
flip-flop