CPE523 TUTORIAL QUESTIONS

1. VHDL is a language for describing digital electronic systems. Write short notes on the history of
VHDL, its alternative and highlight three of its advantages
2. Write short notes on the following:
i. HDL ii. PLD iii. EDA iv. ASIC v. UUT
vi. FPGA vii. PAL viii. OLMC ix. Netlist x. EDIF xi. RTL
3. What is a design methodology? Describe the six steps involved in VHDL/PLD design methodology.
4. Distinguish between the two industry standards of HDL.
5. What is a VHDL Model?
6. With the aid of suitable diagrams, briefly discuss the phases in the design flow of the VHDL/PLD
design methodology.
7. Write two VHDL descriptions of a two-to-four decoder with two inputs a, b and outputs y0 to y3 using
when-else and with-select-when statements. The inputs are the binary equivalent of the suffix of the
output with only one of the outputs having ‘0’ at any time
8. Describe some advantages of using a PLD as opposed to fixed-function ICs to implement a digital
system
9. Design a full adder using the traditional approach. From the truth table create a Karnaugh map for
each output. From the Karnaugh maps, determine the simplified sum-of-products expression for each
output. Draw a logic diagram for two implementations of the circuit, one using AND, OR, and NOT
gates and the other using only NAND gates. Show the programmed implementation on a conceptual
SPLD logic diagram arranged as a PAL having four buffer/inverter gates, eight 8-input AND gates
and eight 8-input OR gates.
10. Write the VHDL description a 4-to-3 priority encoder with inputs i4, i3, i2, and i1 in order of priority,
and outputs a2, a1 and a0. The outputs are binary encoding of the suffix of the highest priority input
asserted with inputs asserted high; otherwise, the output is “000”
11. What is a testbench and what is the relationship of a design entity to its testbench? Can the same
testbench be used for each of the three kinds of simulations?
12. What are the primary advantages of using a testbench for simulation rather than performing an
interactive simulation or a command–line–driven simulation?
13. List six advantages of the VHDL/PLD methodology over traditional digital design.
14. Design a 2-to-1 multiplexer with two data inputs c1 and c0, one select input a, an enable input g and
output y. When the enable input is ‘1’, the select inputs select the value at one of data inputs as the
output otherwise y is ‘0’. Show a condensed truth table for your design and write a VHDL description
for your design using a single Boolean expression concurrent, Selected and Conditional signal
assignment statements
15. State the major differences in today’s PAL-type SPLDs and the conceptual PAL.
16. Write the VHDL description using the behavioural architecture coding style of a one-bit comparator
that compares x and y to produce an output eq whose value is ‘1’ if the inputs are equal, otherwise
‘0’.
17. What is a synthesizer and its required inputs? Describe the steps performed during synthesis with
suitable diagrammatic illustrations.
18. Describe a two-to-four decoder using nested if-statements in VHDL.
19. Write VDHL description for a 4-bit magnitude comparator using processes containing if statements.
20. Write VDHL description for a 4-bit magnitude comparator using for-loop statements.
21. Distinguish between a variable and a signal
22. Write VDHL description for a 4-bit magnitude comparator using for-loop statements with variables
23. Design a 4-bit odd parity detector in VHDL using the dataflow style with and without loops