DSDV (18EC644) Question Bank Prepared by: Abhishek N, Asst Prof

DIGITAL SYSTEM DESIGN USING VERILOG

B.E., VI Semester (Open Elective)
[As per Choice Based Credit System (CBCS) Scheme]
Course Code: 18EC644 CIE Marks: 40
Number of Lecture Hours/Week: 03 SEE Marks: 60
Total Number of Lecture Hours: 40 (08 Hrs per module) Exam Hours: 03
CREDITS – 03

QUESTION BANK
Note: This question bank is prepared by referring to June/July 2018, Dec/ Jan 2019,
June/July 2019 and Dec/Jan 2020 VTU Semester End Exam (SEE) question papers for the
course 15EC663. Also, some important questions (apart from SEE QPs) have been added for
reference.

MODULE 1
1. Define the terms setup time, hold time and clock to output time of a flip flop and what are
the constraints imposed by these parameters on the circuit operations.
2. Develop verilog module for 7 segment decoder. Include an additional input „blank‟ that
overrides the BCD input and causes all segments not to be lit.
3. Explain functional verification and formal verification for a verilog module
4. What are the effects of capacitive loading and propagation delay on signal transitions
between logic levels?
5. Develop verilog module for 4:1 MUX.
6. Explain general view of digital system with data path & control section.
7. Explain with illustration, a simple design methodology followed in IC industries.
8. Explain the following constraints imposed in real world circuits:
(i) Noise margin (ii) Propagation delay (iii) Static Levels
(iv) Static and dynamic power consumption.
9. Develop a verilog module of a debouncer for a push button switvh that uses a debounce
interval of 10ns. Assume the system clock frequency is 50 MHz.
10. Design and develop a circuit and verilog module for modulo 10 counters.
11. What is the distinction between a Moore and Mealy finite state machine?
12. What are the two sources of power consumption in digital components? Explain.

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DSDV (18EC644) Question Bank Prepared by: Abhishek N, Asst Prof

13. Design an encoder for the burglar alarm that has sensors for each of the 8 zones as a
priority encoder with zone 1 having highest priority down to zone 8 having lowest
priority.
14. Develop a datapath to perform complex multiplication of two complex number whose real
and imaginary parts are represented as signed fixed point numbers with 4-pre binary
points and 12 post binary points. Real and imaginary parts of the product are represented
with 8 pre-binary points and 24 post-binary points. Area is the main constraint. Also,
write the verilog model of the complex multiplier datapath.
15. Write a logic circuit and Verilog model for a Vat Buzzer circuit in a factory. The factory
has two vats onl one of which is used at a time he liquid in the vat in use needs to be
at the right temperature between and ach vat has two temperature sensors
indicating whether the temperature is above and above respectivel he vats
also have low level sensors. The supervisor needs to be woken up by a buzzer when the
temperature is too high or too low or the vat level is too low. He has a switch to select
which vat is in use.
16. Write a Verilog model for an encoder for use in a domestic burglar alarm that has sensors
for each of eight zones. Each sensor signal is 1 when an intrusion is detected in that zone,
and 0 otherwise. The encoder has three bits of output, encoding the zone as follows: Zone
1: 000, Zone 2: 001, Zone 3: 010, Zone 4: 011, Zone 5: 100, Zone 6: 101, Zone 7: 110 &
Zone 8: 111.
17. Explain the concept of verification of combinational circuits with suitable example.
18. Explain the constraints of clocked synchronous timing methodology with suitable
diagrams.
19. Write a Verilog model of complex multiplier Control Section FSM.
20. Describe the embedded system design methodology.
21. Describe the concept of Logic Levels and Noise Margin in Digital Circuits.

MODULE 2
1. Write a symbol for basic memory component and explain its parts.
2. Explain about the multiport memories.
3. Compute the 12-bit ECC word corresponding to the 8-bit data word “ 11 1”
4. Design a 64K x 16 bit composite memory using 16K x 8 bit components and also explain
how memory components with tristate data outputs simplify the construction of larger
memories.

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DSDV (18EC644) Question Bank Prepared by: Abhishek N, Asst Prof

5. What is the difference between asynchronous static RAM and synchronous static RAM?
6. Using a Hamming code, how many check bits are required for single error correction and
double error detection for 4-bit data word?
7. Explain asynchronous static RAM with timing diagrams.
8. Write a note on multiport memories.
9. Explain error detection and correction with one example.
10. Design a 1M x 8 bit composite memory using 512 K x 8 bit memory components.
11. Design a 16K x 48 bit memory using 16K x 16 bit memory components.
12. Explain flow through and pipelined SSRAM with the help of timing diagram.
13. Determine whether there is an error in the ECC word 000111000100 and if so, correct it.
14. Develop a verilog model of a dual port 4K x 16 bit flow through SSRAM. One port
allows data to be written and read, while the other port allows data to be read.
15. Explain dynamic RAM operation.
16. Draw the circuit of a 64K*8-bit composite memory using four 16K*8-bit components.
Revise the circuit using bi-directional I/O ports.
17. Describe Read only memories.
18. Write a logic circuit that computes the function y = ci × x2, where x is a binary-coded
input value and ci is a coefficient stored in a flow-through SSRAM. x, ci and y are all
signed fixed-point values with 8 pre binary-point and 12 post-binary-point bits. The index
i is also an input to the circuit, encoded as a 12-bit unsigned integer. Values for x and i
arrive at the input during the cycle when a control input, start, is 1. The circuit should
minimize area by using single multiplier to multiply ci by x and then by x again.
19. Explain the common cause of soft errors in DRAMs. Compute the 12-bit ECC word
corresponding to the 8-bit data word 01100001.
20. Write a logic circuit a FIFO to store up to 256 data items of 16 bits each, using a 256x16-
bit dual-port SSRAM for the data storage. The FIFO should provide status outputs to
indicate when the FIFO is empty and full. Assume that the FIFO will not be read when it
is empty, nor be written to when it is full, and that the write and read ports share a
common clock.

MODULE 3
1. Explain briefly about the sequence of steps involved in IC manufacture.
2. Write and explain the internal organization of a CPLD.
3. What are the two main design and manufacturing techniques for ASICs? Explain

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DSDV (18EC644) Question Bank Prepared by: Abhishek N, Asst Prof

4. Write and explain the internal organization of the FPGA.

5. What distinguishes a platform FPGA from a simple FPGA?
6. Explain differential signalling in detail.
7. What are the purposes of logic blocks and I/O blocks in FPGA?
8. Explain different types of PCB design.
9. Explain implementation fabrics for digital system based on integrated circuit.
10. What are EMI and cross talk?
11. Briefly explain programmable array logic (PAL).
12. Explain signal integrity issue in PCB design and also explain measures to reduce these
issues.
13. Use the following components to design a 4-digit decimal counter with a 7-segment LED
display: two 74LS390 dual decade counters, four 74LS47 BCD to 7-segment decoders,
four 7-segment displays, plus any additional gates required.
14. Explain signal integrity interconnection issue in PCB design.

MODULE 4
1. Show how a 64-bit data word can be transmitted serially between two parts of a system.
Assume that the transmitter and the receiver are both within the same clock domain, and
that the signal start is set to 1 on a clock cycle in which data is ready to be transmitted.
2. Explain any 4 analog sensors.
3. Explain the concept of multiplexed buses.
4. Explain the analog inputs used in input devices.
5. Explain any four serial interface standards.
6. Explain briefly the tristate buses and weak keepers.
7. Design and develop verilog code for an input controller that has 8-bit binary-coded input
from a sensor. The value can be read from an 8-bit input register. The controller should
interrupt the embedded Gumnut core when the input value changes. The controller is the
only interrupt source in the system.
8. What are the purposes of the following in an I/O controller:
(i) input register (ii) output register (iii) control register (iv) status register
9. With a neat diagram, explain R-string DAC and R/2R ladder DAC.
10. What are the serial input standards? Breifly explain each.
11. Explain flash ADC and successive approximation ADC with the help of necessary
diagrams.

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DSDV (18EC644) Question Bank Prepared by: Abhishek N, Asst Prof

12. Write a Verilog model that represents a tri-state bus driver for an 8-bit bus. Also sketch
the logic circuit.
13. Describe the Interrupt Mechanism in I/O software.
14. Describe the concept of Polling in I/O software.
15. Develop a Verilog model of a display multiplexer and decoder for the 4-digit 7-segment
display. The circuit has four BCD inputs. The decimal point for the left-most digit should
be lit, and the remaining decimal points not lit. The system clock has a frequency of
10MHz.

MODULE 5
1. Explain the hardware and software co-design flow.
2. Explain the design optimizations that are must to meet the design constraints.
3. Write a short note on Scan design and boundary scan.
4. Write a short note Built-in Self Test (BIST)
5. Explain logical partitioning and physical partitioning of a transport monitoring system.
6. Explain fault model and fault simulation.
7. Explain a 4 bit LFSR and CFSR for generating pseudorandom test vectors.
8. Explain briefly area, power and timing optimization in digital circuits.
9. Briefly describe techniques used in power optimization.
10. Explain floorplan, placement and routing of ASIC physical design.
11. Describe the process of functional verification.

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